diff --git a/projects/ssc338q_sdcard/br-ext-chip-sigmastar/Config.in b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/Config.in new file mode 100644 index 0000000..cb5a74f --- /dev/null +++ b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/Config.in @@ -0,0 +1,40 @@ +source "$BR2_EXTERNAL_SIGMASTAR_PATH/linux/Config.ext.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/sigmastar_patcher/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/aura-httpd/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/baresip-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/comgt/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/dropbear-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/fdk-aac-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/ffmpeg-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/fwprintenv-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/gdbserver-lite/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/ipctool/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/json-c-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/jsonfilter/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/lame-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libcurl-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libevent-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libhv-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libogg-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libre-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/librem-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libsrt-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/libwebsockets-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/linux-firmware-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/majestic-fonts/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/majestic/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/mbedtls-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/microbe-web/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/motors/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/node-exporter/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/opus-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/rtl8188fu-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/rtl8192eu-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/rtl8733bu-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/sigmastar-osdrv-msc313e/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/sigmastar-osdrv-ssc335/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/sigmastar-osdrv-infinity6e/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/ssw101b/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/uacme-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/vtund-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/yaml-cli/Config.in" diff --git a/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/overlay/arch/arm/boot/dts/infinity6e-ssc338q-camhi.dts b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/overlay/arch/arm/boot/dts/infinity6e-ssc338q-camhi.dts new file mode 100644 index 0000000..6677914 --- /dev/null +++ b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/overlay/arch/arm/boot/dts/infinity6e-ssc338q-camhi.dts @@ -0,0 +1,2252 @@ +/dts-v1/; + +/ { + #address-cells = <0x01>; + #size-cells = <0x01>; + model = "INFINITY6E SSC012B-S01A"; + compatible = "sstar,infinity6e"; + + chosen { + bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; + }; + + aliases { + console = "/soc/uart0@1F221000"; + serial0 = "/soc/uart0@1F221000"; + serial1 = "/soc/uart1@1F221200"; + serial2 = "/soc/uart2@1F220400"; + }; + + memory { + device_type = "memory"; + reg = <0x20000000 0x6000000>; + }; + + camclkinit { + compatible = "camdriver,camclkinit"; + status = "ok"; + }; + + camclk { + compatible = "camdriver,camclk"; + status = "ok"; + }; + + camclkut { + compatible = "camdriver,camclkut"; + status = "ok"; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <0x3b9aca00>; + clocks = <0x01>; + reg = <0x00>; + operating-points = <0x124f80 0xf4240 0x10c8e0 0xf4240 0xf4240 0xdbba0 0xdbba0 0xdbba0 0xc3500 0xcf850 0x927c0 0xcf850 0x61a80 0xcf850>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <0x3b9aca00>; + clocks = <0x01>; + reg = <0x01>; + }; + }; + + oscillator { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xb71b00>; + }; + + phy { + compatible = "sstar,infinity6e-sata-phy"; + io_phy_addr = <0x1f000000>; + banks = <0x1523 0x1524 0x1525>; + reg = <0x1f2a4600 0x300>; + #phy-cells = <0x00>; + phy_type = "utmi"; + status = "ok"; + linux,phandle = <0x71>; + phandle = <0x71>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + gic@16000000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <0x03>; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-controller; + interrupt-parent = <0x03>; + reg = <0x16001000 0x1000 0x16002000 0x1000>; + linux,phandle = <0x03>; + phandle = <0x03>; + }; + + ms_main_intc { + compatible = "sstar,main-intc"; + #interrupt-cells = <0x03>; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x03>; + interrupt-controller; + linux,phandle = <0x02>; + phandle = <0x02>; + }; + + ms_pm_intc { + compatible = "sstar,pm-intc"; + #interrupt-cells = <0x01>; + interrupt-parent = <0x02>; + interrupt-controller; + interrupts = <0x00 0x22 0x04>; + }; + + ms_gpi_intc { + compatible = "sstar,gpi-intc"; + #interrupt-cells = <0x01>; + interrupt-parent = <0x02>; + interrupt-controller; + interrupts = <0x00 0x58 0x04>; + linux,phandle = <0x5d>; + phandle = <0x5d>; + }; + + arch_timer { + compatible = "arm,cortex-a7-timer\0arm,armv7-timer"; + interrupt-parent = <0x03>; + interrupts = <0x01 0x0d 0x308 0x01 0x0e 0x308 0x01 0x0b 0x308 0x01 0x0a 0x308>; + clock-frequency = <0x5b8d80>; + always-on; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <0x03>; + interrupts = <0x00 0x0a 0x04 0x00 0x10 0x04 0x00 0x16 0x04 0x00 0x1c 0x04>; + }; + + clocks { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + CLK_VOID { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x01>; + linux,phandle = <0x17>; + phandle = <0x17>; + }; + + CLK_utmi_480m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x1c9c3800>; + linux,phandle = <0x35>; + phandle = <0x35>; + }; + + CLK_mpll_432m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x19bfcc00>; + linux,phandle = <0x14>; + phandle = <0x14>; + }; + + CLK_upll_384m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x16e36000>; + linux,phandle = <0x15>; + phandle = <0x15>; + }; + + CLK_mpll_345m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x14904840>; + linux,phandle = <0x3e>; + phandle = <0x3e>; + }; + + CLK_upll_320m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x1312d000>; + linux,phandle = <0x36>; + phandle = <0x36>; + }; + + CLK_mpll_288m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x112a8800>; + linux,phandle = <0x04>; + phandle = <0x04>; + }; + + CLK_utmi_240m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xe4e1c00>; + linux,phandle = <0x37>; + phandle = <0x37>; + }; + + CLK_mpll_216m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xcdfe600>; + linux,phandle = <0x05>; + phandle = <0x05>; + }; + + CLK_utmi_192m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xb71b000>; + linux,phandle = <0x08>; + phandle = <0x08>; + }; + + CLK_mpll_172m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xa4cb800>; + linux,phandle = <0x26>; + phandle = <0x26>; + }; + + CLK_utmi_160m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x9896800>; + linux,phandle = <0x09>; + phandle = <0x09>; + }; + + CLK_mpll_123m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x75aef40>; + linux,phandle = <0x06>; + phandle = <0x06>; + }; + + CLK_mpll_86m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x5265c00>; + linux,phandle = <0x07>; + phandle = <0x07>; + }; + + CLK_mpll_288m_div2 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x04>; + clock-div = <0x02>; + clock-mult = <0x01>; + linux,phandle = <0x27>; + phandle = <0x27>; + }; + + CLK_mpll_288m_div4 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x04>; + clock-div = <0x04>; + clock-mult = <0x01>; + linux,phandle = <0x23>; + phandle = <0x23>; + }; + + CLK_mpll_288m_div8 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x04>; + clock-div = <0x08>; + clock-mult = <0x01>; + linux,phandle = <0x20>; + phandle = <0x20>; + }; + + CLK_mpll_216m_div2 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x05>; + clock-div = <0x02>; + clock-mult = <0x01>; + linux,phandle = <0x1c>; + phandle = <0x1c>; + }; + + CLK_mpll_216m_div4 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x05>; + clock-div = <0x04>; + clock-mult = <0x01>; + linux,phandle = <0x22>; + phandle = <0x22>; + }; + + CLK_mpll_216m_div8 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x05>; + clock-div = <0x08>; + clock-mult = <0x01>; + linux,phandle = <0x1f>; + phandle = <0x1f>; + }; + + CLK_mpll_123m_div2 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x06>; + clock-div = <0x02>; + clock-mult = <0x01>; + linux,phandle = <0x2b>; + phandle = <0x2b>; + }; + + CLK_mpll_86m_div2 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x07>; + clock-div = <0x02>; + clock-mult = <0x01>; + linux,phandle = <0x2d>; + phandle = <0x2d>; + }; + + CLK_mpll_86m_div4 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x07>; + clock-div = <0x04>; + clock-mult = <0x01>; + linux,phandle = <0x2e>; + phandle = <0x2e>; + }; + + CLK_mpll_86m_div16 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x07>; + clock-div = <0x10>; + clock-mult = <0x01>; + linux,phandle = <0x2f>; + phandle = <0x2f>; + }; + + CLK_utmi_192m_div4 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x08>; + clock-div = <0x04>; + clock-mult = <0x01>; + linux,phandle = <0x2c>; + phandle = <0x2c>; + }; + + CLK_utmi_160m_div4 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x09>; + clock-div = <0x04>; + clock-mult = <0x01>; + linux,phandle = <0x38>; + phandle = <0x38>; + }; + + CLK_utmi_160m_div5 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x09>; + clock-div = <0x05>; + clock-mult = <0x01>; + linux,phandle = <0x3b>; + phandle = <0x3b>; + }; + + CLK_utmi_160m_div8 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x09>; + clock-div = <0x08>; + clock-mult = <0x01>; + linux,phandle = <0x3c>; + phandle = <0x3c>; + }; + + CLK_xtali_12m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xb71b00>; + linux,phandle = <0x0a>; + phandle = <0x0a>; + }; + + CLK_xtali_12m_div2 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x02>; + clock-mult = <0x01>; + linux,phandle = <0x24>; + phandle = <0x24>; + }; + + CLK_xtali_12m_div4 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x04>; + clock-mult = <0x01>; + linux,phandle = <0x25>; + phandle = <0x25>; + }; + + CLK_xtali_12m_div8 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x08>; + clock-mult = <0x01>; + linux,phandle = <0x18>; + phandle = <0x18>; + }; + + CLK_xtali_12m_div16 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x10>; + clock-mult = <0x01>; + linux,phandle = <0x19>; + phandle = <0x19>; + }; + + CLK_xtali_12m_div40 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x28>; + clock-mult = <0x01>; + linux,phandle = <0x3d>; + phandle = <0x3d>; + }; + + CLK_xtali_12m_div64 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x40>; + clock-mult = <0x01>; + linux,phandle = <0x1a>; + phandle = <0x1a>; + }; + + CLK_xtali_12m_div128 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0a>; + clock-div = <0x80>; + clock-mult = <0x01>; + linux,phandle = <0x1b>; + phandle = <0x1b>; + }; + + CLK_xtali_24m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + linux,phandle = <0x0b>; + phandle = <0x0b>; + }; + + CLK_RTC_CLK_32K { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x7d00>; + }; + + CLK_pm_riu_w_clk_in { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x66ff300>; + }; + + CLK_miupll_clk { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x17d78400>; + linux,phandle = <0x16>; + phandle = <0x16>; + }; + + CLK_ddrpll_clk { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x7f22ff40>; + }; + + CLK_lpll_clk { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x5f5e100>; + linux,phandle = <0x30>; + phandle = <0x30>; + }; + + CLK_ven_pll { + #clock-cells = <0x00>; + compatible = "sstar,complex-clock"; + clocks = <0x0b>; + linux,phandle = <0x39>; + phandle = <0x39>; + }; + + CLK_ven_pll_div6 { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x632ea00>; + linux,phandle = <0x21>; + phandle = <0x21>; + }; + + CLK_lpll_div2 { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x2faf080>; + linux,phandle = <0x31>; + phandle = <0x31>; + }; + + CLK_lpll_div4 { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x17d7840>; + linux,phandle = <0x32>; + phandle = <0x32>; + }; + + CLK_lpll_div8 { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xbebc20>; + linux,phandle = <0x33>; + phandle = <0x33>; + }; + + CLK_armpll_37p125m { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x23c3460>; + linux,phandle = <0x34>; + phandle = <0x34>; + }; + + CLK_riu_w_clk_in { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_riu_w_clk_top { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_riu_w_clk_sc_gp { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_riu_w_clk_vhe_gp { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_riu_w_clk_hemcu_gp { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_riu_w_clk_mipi_if_gp { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_riu_w_clk_mcu_if_gp { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_fuart0_synth_out { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x19bfcc00>; + linux,phandle = <0x28>; + phandle = <0x28>; + }; + + CLK_miu_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0d>; + clock-div = <0x01>; + clock-mult = <0x01>; + linux,phandle = <0x1e>; + phandle = <0x1e>; + }; + + CLK_mspi0_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0e>; + clock-div = <0x01>; + clock-mult = <0x01>; + linux,phandle = <0x29>; + phandle = <0x29>; + }; + + CLK_mspi1_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0f>; + clock-div = <0x01>; + clock-mult = <0x01>; + linux,phandle = <0x2a>; + phandle = <0x2a>; + }; + + CLK_miu_vhe_gp_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0d>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_miu_sc_gp_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0d>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_mcu_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x0c>; + clock-div = <0x01>; + clock-mult = <0x01>; + linux,phandle = <0x1d>; + phandle = <0x1d>; + }; + + CLK_fclk1_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x10>; + clock-div = <0x01>; + clock-mult = <0x01>; + linux,phandle = <0x12>; + phandle = <0x12>; + }; + + CLK_sdio_p { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x11>; + clock-div = <0x01>; + clock-mult = <0x01>; + }; + + CLK_tck_buf { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x2faf080>; + }; + + CLK_eth_buf { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + linux,phandle = <0x3f>; + phandle = <0x3f>; + }; + + CLK_rmii_buf { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + linux,phandle = <0x40>; + phandle = <0x40>; + }; + + CLK_emac_testrx125_in_lan { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + linux,phandle = <0x3a>; + phandle = <0x3a>; + }; + + CLK_gop0 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x12>; + clock-div = <0x01>; + clock-mult = <0x01>; + linux,phandle = <0x48>; + phandle = <0x48>; + }; + + CLK_rtc_32k { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x8000>; + linux,phandle = <0x41>; + phandle = <0x41>; + }; + + CLK_fro { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x2dc6c00>; + linux,phandle = <0x13>; + phandle = <0x13>; + }; + + CLK_fro_div2 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x13>; + clock-div = <0x02>; + clock-mult = <0x01>; + linux,phandle = <0x43>; + phandle = <0x43>; + }; + + CLK_fro_div8 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x13>; + clock-div = <0x08>; + clock-mult = <0x01>; + linux,phandle = <0x42>; + phandle = <0x42>; + }; + + CLK_fro_div16 { + #clock-cells = <0x00>; + compatible = "fixed-factor-clock"; + clocks = <0x13>; + clock-div = <0x10>; + clock-mult = <0x01>; + linux,phandle = <0x44>; + phandle = <0x44>; + }; + + CLK_cpupll_clk { + #clock-cells = <0x00>; + compatible = "sstar,complex-clock"; + clocks = <0x14>; + linux,phandle = <0x01>; + phandle = <0x01>; + }; + + CLK_utmi { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x1c9c3800>; + linux,phandle = <0x70>; + phandle = <0x70>; + }; + + CLK_bach { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x15>; + reg = <0x1f2071b4 0x04>; + gate-shift = <0x07>; + linux,phandle = <0x56>; + phandle = <0x56>; + }; + + CLK_miu { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x16 0x17 0x17>; + reg = <0x1f20705c 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + glitch-shift = <0x04>; + auto-enable = <0x01>; + linux,phandle = <0x0d>; + phandle = <0x0d>; + }; + + CLK_miu_boot { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x0d>; + reg = <0x1f20705c 0x04>; + mux-shift = <0x02>; + mux-width = <0x01>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_ddr_syn { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x14 0x05 0x0a 0x17>; + reg = <0x1f207064 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_miu_rec { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x18 0x19 0x1a 0x1b>; + reg = <0x1f207060 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_mcu { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x14 0x15 0x1c>; + reg = <0x1f207004 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + glitch-shift = <0x04>; + auto-enable = <0x01>; + linux,phandle = <0x0c>; + phandle = <0x0c>; + }; + + CLK_riubrdg { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1d 0x17 0x17 0x17>; + reg = <0x1f207004 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x01>; + }; + + CLK_bdma { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1e 0x17 0x17 0x17>; + reg = <0x1f207180 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x63>; + phandle = <0x63>; + }; + + CLK_spi_arb { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x1c 0x07 0x1e>; + reg = <0x1f2070c8 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + glitch-shift = <0x04>; + auto-enable = <0x01>; + }; + + CLK_spi_flash { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x1f 0x20 0x21 0x22 0x23 0x07 0x1c>; + reg = <0x1f2070e0 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + glitch-shift = <0x05>; + auto-enable = <0x01>; + }; + + CLK_pwm { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x24 0x25 0x18 0x0b 0x07 0x17 0x17>; + reg = <0x1f2070e0 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x6e>; + phandle = <0x6e>; + }; + + CLK_uart0 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x26 0x27 0x0a 0x17>; + reg = <0x1f2070c4 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x60>; + phandle = <0x60>; + }; + + CLK_uart1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x26 0x27 0x0a 0x17>; + reg = <0x1f2070c4 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x61>; + phandle = <0x61>; + }; + + CLK_fuart0_synth_in { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x14 0x05 0x17 0x17>; + reg = <0x1f2070d0 0x04>; + mux-shift = <0x06>; + mux-width = <0x02>; + gate-shift = <0x04>; + auto-enable = <0x00>; + }; + + CLK_fuart { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x26 0x27 0x0a 0x28>; + reg = <0x1f2070d0 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x62>; + phandle = <0x62>; + }; + + CLK_mspi0 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1c 0x22 0x0a 0x27>; + reg = <0x1f2070cc 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x0e>; + phandle = <0x0e>; + }; + + CLK_mspi1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1c 0x22 0x0a 0x27>; + reg = <0x1f2070cc 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x0f>; + phandle = <0x0f>; + }; + + CLK_mspi { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x29 0x2a>; + reg = <0x1f2070cc 0x04>; + mux-shift = <0x0e>; + mux-width = <0x01>; + gate-shift = <0x0c>; + auto-enable = <0x00>; + linux,phandle = <0x5b>; + phandle = <0x5b>; + }; + + CLK_miic0 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x23 0x22 0x0a 0x17>; + reg = <0x1f2070dc 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x5c>; + phandle = <0x5c>; + }; + + CLK_miic1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x23 0x22 0x0a 0x17>; + reg = <0x1f2070dc 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x5e>; + phandle = <0x5e>; + }; + + CLK_miic2 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x23 0x22 0x0a 0x17>; + reg = <0x1f2070dc 0x04>; + mux-shift = <0x0e>; + mux-width = <0x02>; + gate-shift = <0x0c>; + auto-enable = <0x00>; + linux,phandle = <0x5f>; + phandle = <0x5f>; + }; + + CLK_bist { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x26 0x1c 0x22 0x0a>; + reg = <0x1f207008 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + }; + + CLK_pwr_ctl { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x19 0x18 0x0a 0x17>; + reg = <0x1f207010 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_xtali { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x17 0x17 0x17>; + reg = <0x1f207000 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_live { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x17 0x17 0x17>; + reg = <0x1f207000 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x01>; + }; + + CLK_sr00_mclk { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1f 0x23 0x2b 0x22 0x2c 0x2d 0x20 0x0b 0x2e 0x0a 0x2f 0x30 0x31 0x32 0x33 0x34>; + reg = <0x1f207188 0x04>; + mux-shift = <0x0a>; + mux-width = <0x04>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x57>; + phandle = <0x57>; + }; + + CLK_sr01_mclk { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1f 0x23 0x2b 0x22 0x2c 0x2d 0x20 0x0b 0x2e 0x0a 0x2f 0x30 0x31 0x32 0x33 0x34>; + reg = <0x1f207194 0x04>; + mux-shift = <0x02>; + mux-width = <0x04>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x59>; + phandle = <0x59>; + }; + + CLK_sr1_mclk { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1f 0x23 0x2b 0x22 0x2c 0x2d 0x20 0x0b 0x2e 0x0a 0x2f 0x30 0x31 0x32 0x33 0x34>; + reg = <0x1f207194 0x04>; + mux-shift = <0x0a>; + mux-width = <0x04>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x58>; + phandle = <0x58>; + }; + + CLK_bist_pm { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x1c 0x22 0x1f 0x0a>; + reg = <0x1f207008 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + }; + + CLK_bist_ipu_gp { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x04 0x05 0x26 0x1c 0x07 0x22 0x1f 0x0a>; + reg = <0x1f207014 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_ipu { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x35 0x14 0x15 0x36 0x37 0x05 0x06>; + reg = <0x1f207140 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + }; + + CLK_ipuff { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x14 0x15 0x36 0x37>; + reg = <0x1f207140 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + }; + + CLK_bist_usb30_gp { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x26 0x1c 0x22 0x0a>; + reg = <0x1f207014 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + }; + + CLK_csi_mac_lptx_top_i_m00 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207160 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x4b>; + phandle = <0x4b>; + }; + + CLK_csi_mac_top_i_m00 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207160 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x4c>; + phandle = <0x4c>; + }; + + CLK_ns_top_i_m00 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207164 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x4d>; + phandle = <0x4d>; + }; + + CLK_csi_mac_lptx_top_i_m01 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207164 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x51>; + phandle = <0x51>; + }; + + CLK_csi_mac_top_i_m01 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207168 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x52>; + phandle = <0x52>; + }; + + CLK_ns_top_i_m01 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207168 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x53>; + phandle = <0x53>; + }; + + CLK_csi_mac_lptx_top_i_m1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f20716c 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x4e>; + phandle = <0x4e>; + }; + + CLK_csi_mac_top_i_m1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f20716c 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x4f>; + phandle = <0x4f>; + }; + + CLK_ns_top_i_m1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x37 0x26 0x27 0x07 0x38 0x17 0x17>; + reg = <0x1f207170 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x50>; + phandle = <0x50>; + }; + + CLK_mipi1_tx_csi { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x30 0x09 0x27 0x1c 0x05 0x37 0x04 0x36>; + reg = <0x1f207170 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x55>; + phandle = <0x55>; + }; + + CLK_bist_vhe_gp { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x04 0x05 0x26 0x1c 0x07 0x22 0x1f 0x0a>; + reg = <0x1f20700c 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + }; + + CLK_vhe { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x39 0x35 0x14 0x15 0x36 0x04 0x08 0x06>; + reg = <0x1f2071a0 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x07>; + auto-enable = <0x00>; + linux,phandle = <0x45>; + phandle = <0x45>; + }; + + CLK_mfe { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x15 0x36 0x39>; + reg = <0x1f2071a4 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x46>; + phandle = <0x46>; + }; + + CLK_xtali_sc_gp { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x17 0x17 0x17>; + reg = <0x1f207000 0x04>; + mux-shift = <0x06>; + mux-width = <0x02>; + gate-shift = <0x04>; + auto-enable = <0x01>; + }; + + CLK_bist_sc_gp { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x04 0x05 0x26 0x1c 0x07 0x22 0x1f 0x0a>; + reg = <0x1f20700c 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_emac_ahb { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x27 0x06 0x07 0x3a>; + reg = <0x1f207108 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x68>; + phandle = <0x68>; + }; + + CLK_jpe { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x35 0x14 0x15 0x36 0x04 0x05 0x17 0x17>; + reg = <0x1f2071a8 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x5a>; + phandle = <0x5a>; + }; + + CLK_aesdma { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x07 0x26 0x17 0x17>; + reg = <0x1f207184 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + glitch-shift = <0x04>; + auto-enable = <0x00>; + linux,phandle = <0x6f>; + phandle = <0x6f>; + }; + + CLK_sdio { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x2c 0x2d 0x38 0x20 0x3b 0x3c 0x0a 0x3d>; + reg = <0x1f207114 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x11>; + phandle = <0x11>; + }; + + CLK_sd { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x2c 0x2d 0x38 0x20 0x3b 0x3c 0x0a 0x3d>; + reg = <0x1f20710c 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x64>; + phandle = <0x64>; + }; + + CLK_ecc { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x09 0x1c 0x22 0x0a>; + reg = <0x1f207110 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + linux,phandle = <0x65>; + phandle = <0x65>; + }; + + CLK_isp { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x36 0x04 0x05 0x08 0x26 0x06 0x23 0x15>; + reg = <0x1f207184 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x4a>; + phandle = <0x4a>; + }; + + CLK_fclk1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x3e 0x14 0x15 0x36 0x04 0x37 0x26 0x06>; + reg = <0x1f207190 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x10>; + phandle = <0x10>; + }; + + CLK_odclk { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x07 0x2d 0x2e 0x30>; + reg = <0x1f207198 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x54>; + phandle = <0x54>; + }; + + CLK_dip { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x35 0x14 0x15 0x36 0x04 0x37 0x26 0x06>; + reg = <0x1f207148 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x47>; + phandle = <0x47>; + }; + + CLK_emac_tx { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x3f 0x40>; + reg = <0x1f22668c 0x04>; + mux-shift = <0x02>; + mux-width = <0x01>; + gate-shift = <0x00>; + linux,phandle = <0x69>; + phandle = <0x69>; + }; + + CLK_emac_rx { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x3f 0x40>; + reg = <0x1f226688 0x04>; + mux-shift = <0x02>; + mux-width = <0x01>; + gate-shift = <0x00>; + linux,phandle = <0x6a>; + phandle = <0x6a>; + }; + + CLK_emac_tx_ref { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x40 0x17>; + reg = <0x1f22668c 0x04>; + mux-shift = <0x0a>; + mux-width = <0x01>; + gate-shift = <0x08>; + linux,phandle = <0x6b>; + phandle = <0x6b>; + }; + + CLK_emac_rx_ref { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x40 0x17>; + reg = <0x1f226688 0x04>; + mux-shift = <0x0a>; + mux-width = <0x01>; + gate-shift = <0x08>; + linux,phandle = <0x6c>; + phandle = <0x6c>; + }; + + CLK_ive { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x05 0x26 0x06 0x07 0x04 0x36 0x15 0x17>; + reg = <0x1f2071a8 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + auto-enable = <0x00>; + linux,phandle = <0x67>; + phandle = <0x67>; + }; + + CLK_ldcfeye { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x35 0x14 0x15 0x36 0x04 0x05 0x07 0x17>; + reg = <0x1f20714c 0x04>; + mux-shift = <0x02>; + mux-width = <0x03>; + gate-shift = <0x00>; + auto-enable = <0x00>; + linux,phandle = <0x49>; + phandle = <0x49>; + }; + + CLK_live_pm { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x41 0x17 0x17>; + reg = <0x1f001cd0 0x04>; + mux-shift = <0x00>; + mux-width = <0x02>; + auto-enable = <0x00>; + }; + + CLK_mcu_pm_p1 { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x42 0x41 0x43>; + reg = <0x1f001c80 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + + CLK_spi_pm { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x13 0x41 0x07 0x1c 0x0a 0x43 0x0b 0x22>; + reg = <0x1f001c80 0x04>; + mux-shift = <0x0a>; + mux-width = <0x03>; + gate-shift = <0x08>; + glitch-shift = <0x0d>; + auto-enable = <0x01>; + }; + + CLK_miic_pm { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x07 0x0a 0x43 0x41>; + reg = <0x1f001c98 0x04>; + mux-shift = <0x0e>; + mux-width = <0x02>; + gate-shift = <0x0c>; + auto-enable = <0x00>; + }; + + CLK_pm_sleep { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x41 0x43 0x17>; + reg = <0x1f001c88 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + auto-enable = <0x01>; + }; + + CLK_rtc { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x41 0x17 0x17>; + reg = <0x1f001c88 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + linux,phandle = <0x66>; + phandle = <0x66>; + }; + + CLK_sar { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x41 0x17 0x17>; + reg = <0x1f001c88 0x04>; + mux-shift = <0x07>; + mux-width = <0x02>; + gate-shift = <0x05>; + auto-enable = <0x01>; + }; + + CLK_pir { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x44 0x42 0x43>; + reg = <0x1f001c98 0x04>; + mux-shift = <0x0a>; + mux-width = <0x02>; + gate-shift = <0x08>; + auto-enable = <0x00>; + }; + + CLK_pm_uart { + #clock-cells = <0x00>; + compatible = "sstar,composite-clock"; + clocks = <0x0a 0x41 0x1c 0x07>; + reg = <0x1f001c94 0x04>; + mux-shift = <0x02>; + mux-width = <0x02>; + gate-shift = <0x00>; + auto-enable = <0x01>; + }; + }; + + venc { + compatible = "sstar,venc"; + reg = <0x1f345200 0x800 0x1f2c5200 0x100 0x1f203c00 0x100 0x1f207800 0x100>; + reg-names = "vpu-bit\0venc-brige\0hw-uart0\0hw-uart1"; + interrupts = <0x00 0x35 0x04>; + interrupt-parent = <0x02>; + interrupt-names = "mhe-irq"; + clocks = <0x45 0x46>; + clock-names = "CKG_venc"; + status = "ok"; + }; + + dip { + compatible = "sstar,dip"; + interrupts = <0x00 0x5f 0x04>; + clocks = <0x47>; + status = "ok"; + }; + + dla { + compatible = "sstar,dla"; + interrupts = <0x00 0x55 0x04>; + status = "ok"; + }; + + gop { + compatible = "sigmastar,gop"; + clocks = <0x48 0x10 0x47 0x49>; + status = "ok"; + }; + + isp { + compatible = "isp"; + io_phy_addr = <0x1f000000>; + banks = <0x1302>; + interrupts = <0x00 0x39 0x04>; + clocks = <0x4a>; + status = "ok"; + clock-frequency-index = <0x00>; + }; + + csi { + compatible = "sstar,csi"; + io_phy_addr = <0x1f000000>; + banks = <0x120b 0x120c 0x120d 0x1208 0x1209 0x120a 0x1202 0x1203 0x1204 0x1038 0x120e>; + interrupts = <0x00 0x41 0x04>; + clocks = <0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53>; + status = "ok"; + csi_sr0_lane_num = <0x04>; + csi_sr1_lane_num = <0x04>; + csi_sr2_lane_num = <0x02>; + csi_sr0_lane_select = <0x02 0x04 0x03 0x01 0x00>; + csi_sr1_lane_select = <0x00 0x00 0x00 0x00 0x00>; + csi_sr2_lane_select = <0x00 0x00 0x00>; + csi_sr0_lane_pn_swap = <0x01 0x01 0x01 0x01 0x01>; + csi_sr1_lane_pn_swap = <0x00 0x00 0x00 0x00 0x00>; + csi_sr2_lane_pn_swap = <0x00 0x00 0x00>; + }; + + pnl { + compatible = "sstar,pnl"; + status = "ok"; + ttl-24bit-mode = <0x00>; + ttl-16bit-mode = <0x01>; + jtag-mode = <0x01>; + clocks = <0x54>; + clock-names = "CLK_odclk"; + interrupts = <0x00 0x5b 0x04>; + }; + + disp { + compatible = "sstar,disp"; + status = "ok"; + clocks = <0x54>; + clock-names = "CLK_odclk"; + interrupts = <0x00 0x5b 0x04 0x00 0x34 0x04 0x00 0x5a 0x04 0x00 0x31 0x04>; + }; + + mipitx_csi { + compatible = "sstar,mipitx"; + status = "ok"; + clocks = <0x55>; + clock-names = "CLK_mipi1_tx_csi"; + interrupts = <0x00 0x56 0x04>; + }; + + sound { + compatible = "sstar,audio"; + interrupts = <0x00 0x4a 0x04>; + playback-volume-level = <0x40>; + capture-volume-level = <0x40>; + micin-pregain-level = <0x00>; + micin-gain-level = <0x03>; + linein-gain-level = <0x02>; + amp-gpio = <0x07 0x01>; + clocks = <0x56>; + digmic-padmux = <0x06>; + i2s-trx-shared-padmux = <0x01>; + i2s-tx-padmux = <0x00>; + i2s-rx-padmux = <0x00>; + i2smck-padmux = <0x01>; + i2smod-padmux = <0x00>; + keep-i2s-clk = <0x00>; + i2s-rx-tdm-ws-pgm = <0x00>; + i2s-rx-tdm-ws-width = <0x00>; + i2s-rx-tdm-ch-swap = <0x00 0x00>; + i2s-tx-tdm-ws-pgm = <0x00>; + i2s-tx-tdm-ws-width = <0x00>; + i2s-tx-tdm-ch-swap = <0x00 0x00>; + i2s-tx-tdm-active-slot = <0x03>; + status = "ok"; + }; + + vif { + compatible = "sstar,vif"; + status = "ok"; + reg = <0x1f260800 0x600 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1f207800 0x200 0x1f226600 0x200 0x1f207000 0x200 0x1f000000 0x400000 0x1f203c00 0x200>; + clocks = <0x57 0x58 0x59>; + interrupts = <0x00 0x59 0x04>; + vif_sr0_mclk_37p125 = <0x01>; + vif_sr1_mclk_37p125 = <0x01>; + vif_sr2_mclk_37p125 = <0x01>; + vif_sr0_par_mode = <0x02>; + vif_sr0_mipi_mode = <0x01>; + vif_sr0_bt656_mode = <0x01>; + vif_sr0_mclk_mode = <0x00>; + vif_sr0_parallel_rst_mode = <0x00>; + vif_sr0_parallel_pdn_mode = <0x00>; + vif_sr0_mipi_rst_mode = <0x00>; + vif_sr0_mipi_pdn_mode = <0x01>; + vif_sr0_mipi_ctrl_mode = <0x01>; + vif_sr1_par_mode = <0x00>; + vif_sr1_mipi_mode = <0x01>; + vif_sr1_bt656_mode = <0x00>; + vif_sr1_mipi_ctrl_mode = <0x01>; + vif_sr1_mclk_mode = <0x00>; + vif_sr1_rst_mode = <0x00>; + vif_sr2_mipi_mode = <0x00>; + vif_sr2_mipi_ctrl_mode = <0x00>; + vif_sr2_mclk_mode = <0x00>; + vif_sr2_rst_mode = <0x00>; + }; + + ispalgo { + compatible = "sstar,ispalgo"; + status = "ok"; + }; + + ispmid { + compatible = "sstar,ispmid"; + status = "ok"; + }; + + sensorif { + compatible = "sstar,sensorif"; + status = "ok"; + sensorif_grp0_i2c = <0x01>; + sensorif_grp1_i2c = <0x02>; + sensorif_grp2_i2c = <0x01>; + }; + + jpe@0x1F2c4000 { + compatible = "sstar,cedric-jpe"; + reg = <0x1f2c4000 0x100>; + interrupts = <0x00 0x3d 0x04>; + clocks = <0x5a>; + clock-names = "CKG_jpe"; + clk-select = <0x00>; + status = "ok"; + }; + + spi { + compatible = "sstar_spi"; + io_phy_addr = <0x1f000000>; + banks = <0x1110 0x1111 0x1038 0x103c>; + interrupts = <0x00 0x46 0x04 0x00 0x47 0x04>; + spi0_mode = <0x01>; + spi1_mode = <0x03>; + status = "disabled"; + }; + + spidev { + compatible = "spidev"; + }; + + spi0@0 { + compatible = "sstar,mspi"; + mspi-group = <0x00>; + clocks = <0x0e 0x5b>; + reg = <0x1f222000 0x200>; + interrupts = <0x00 0x46 0x04>; + use-dma = <0x01>; + status = "ok"; + }; + + spi1@1 { + compatible = "sstar,mspi"; + mspi-group = <0x01>; + clocks = <0x0f 0x5b>; + reg = <0x1f222200 0x200>; + interrupts = <0x00 0x47 0x04>; + use-dma = <0x01>; + status = "ok"; + }; + + i2c0@0 { + compatible = "sstar,i2c"; + reg = <0x1f223000 0x200 0x1f207800 0x200 0x1f207000 0x200>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x5c>; + i2c-group = <0x00>; + i2c-en-dma = <0x01>; + status = "ok"; + interrupts = <0x00 0x44 0x04>; + i2c-padmux = <0x03>; + + goodix_gt911@5D { + compatible = "goodix,gt911"; + reg = <0x5d>; + goodix_rst = <0x31>; + goodix_int = <0x40>; + interrupts-extended = <0x5d 0x05>; + interrupt-names = "goodix_int"; + }; + }; + + i2c1@1 { + compatible = "sstar,i2c"; + reg = <0x1f223200 0x200 0x1f207800 0x200 0x1f207000 0x200>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x5e>; + i2c-group = <0x01>; + i2c-en-dma = <0x01>; + i2c-padmux = <0x01>; + interrupts = <0x00 0x45 0x04>; + status = "ok"; + }; + + i2c2@2 { + compatible = "sstar,i2c"; + reg = <0x1f223400 0x200 0x1f207800 0x200 0x1f207000 0x200>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x5f>; + i2c-group = <0x02>; + i2c-en-dma = <0x01>; + i2c-padmux = <0x04>; + interrupts = <0x00 0x2c 0x04>; + status = "ok"; + }; + + cmdq0 { + compatible = "sstar,cmdq0"; + clocks = <0x0c>; + interrupts = <0x00 0x31 0x04>; + status = "ok"; + }; + + cmdq1 { + compatible = "sstar,cmdq1"; + clocks = <0x0c>; + interrupts = <0x00 0x31 0x04>; + status = "ok"; + }; + + cmdq2 { + compatible = "sstar,cmdq2"; + clocks = <0x0c>; + interrupts = <0x00 0x31 0x04>; + status = "ok"; + }; + + cmdq3 { + compatible = "sstar,cmdq3"; + clocks = <0x0c>; + interrupts = <0x00 0x31 0x04>; + status = "ok"; + }; + + ldc { + compatible = "sstar,ldc"; + reg = <0x1f287800 0x100 0x1f287a00 0x100>; + interrupts = <0x00 0x4b 0x04>; + clocks = <0x49>; + clock-names = "CLK_ldcfeye"; + clk-select = <0x01>; + status = "ok"; + }; + + scl { + compatible = "sstar,scl"; + status = "ok"; + }; + + vpe { + compatible = "sigmastar,vpe"; + reg = <0x1f242000 0x100>; + interrupts = <0x00 0x34 0x04 0x00 0x5a 0x04 0x00 0x5b 0x04 0x00 0x31 0x04>; + clocks = <0x10 0x54>; + clock-names = "CLK_fclk1\0CLK_fclk2\0CLK_odclk"; + clk-select = <0x02>; + status = "ok"; + }; + + uart0@1F221000 { + compatible = "sstar,uart"; + reg = <0x1f221000 0x100>; + interrupts = <0x00 0x42 0x04>; + status = "ok"; + clocks = <0x60>; + }; + + uart1@1F221200 { + compatible = "sstar,uart"; + reg = <0x1f221200 0x100 0x1f006a00 0x100>; + interrupts = <0x00 0x43 0x04 0x00 0x24 0x04>; + clocks = <0x61>; + pm_uart = <0x00>; + pad = <0x3b>; + status = "ok"; + }; + + uart2@1F220400 { + compatible = "sstar,uart"; + reg = <0x1f220400 0x100 0x1f220600 0x100>; + interrupts = <0x00 0x4f 0x04 0x00 0x50 0x04>; + clocks = <0x62>; + sctp_enable = <0x01>; + dma = <0x01>; + pad = <0x2e>; + status = "ok"; + }; + + flashisp { + compatible = "mtd-flashisp"; + clocks = <0x63>; + quadread = <0x00>; + status = "ok"; + }; + + spinandflash { + compatible = "ms-spinand"; + clocks = <0x63>; + status = "ok"; + }; + + emmc { + compatible = "sstar_mci"; + clocks = <0x64 0x65>; + interrupts = <0x00 0x32 0x04>; + bus-width = <0x04>; + status = "ok"; + }; + + sdmmc { + compatible = "sstar,sdmmc"; + slotnum = <0x02>; + revcdz = <0x00>; + slot-ip-orders = <0x00 0x01 0x02>; + slot-max-clks = <0x1312d00 0x1312d00 0x1312d00>; + slot-intcdzs = <0x01 0x01 0x00>; + slot-pwr-gpios = <0x1d 0x39 0xffff>; + slot-pwr-off-delay = <0x1e 0x1e 0x1e>; + interrupts-extended = <0x02 0x00 0x32 0x04 0x02 0x00 0x33 0x04 0x02 0x00 0x77 0x04 0x02 0x00 0x78 0x04>; + interrupt-names = "mie0_irq\0mie1_irq\0cdz_slot0_irq\0cdz_slot1_irq"; + clocks = <0x64 0x11 0x17>; + status = "ok"; + slot-fakecdzs = <0x00 0x00 0x00>; + slot-pad-orders = <0x00 0x02 0x01>; + slot-cdzs-gpios = <0x1e 0x2b 0xffff>; + slot-sdio-use = <0x00 0x00 0x00>; + slot-removable = <0x01 0x01 0x01>; + }; + + bdma0 { + compatible = "sstar,bdma0"; + interrupts = <0x00 0x48 0x04>; + clocks = <0x63>; + status = "ok"; + }; + + bdma1 { + compatible = "sstar,bdma1"; + interrupts = <0x00 0x49 0x04>; + clocks = <0x63>; + status = "ok"; + }; + + bdma2 { + compatible = "sstar,bdma2"; + interrupts = <0x00 0x5d 0x04>; + clocks = <0x63>; + status = "ok"; + }; + + movdma { + compatible = "sstar,movdma"; + interrupts = <0x00 0x5c 0x04>; + clocks = <0x0d>; + status = "ok"; + }; + + cpufreq { + compatible = "sstar,infinity-cpufreq"; + status = "ok"; + }; + + watchdog { + compatible = "sstar,infinity-wdt"; + reg = <0x1f006000 0x40>; + status = "ok"; + }; + + sar { + compatible = "sstar,infinity-sar"; + reg = <0x1f002800 0x200>; + status = "ok"; + }; + + rtcpwc { + compatible = "sstar,infinity-rtcpwc"; + reg = <0x1f006800 0x200>; + interrupts = <0x00 0x28 0x04>; + clocks = <0x66>; + status = "ok"; + }; + + ive@0x1F2A4000 { + compatible = "sstar,infinity-ive"; + reg = <0x1f2a4000 0x100 0x1f2a4200 0x100>; + interrupts = <0x00 0x4d 0x04>; + clocks = <0x67>; + status = "ok"; + }; + + emac0 { + compatible = "sstar-emac"; + interrupts = <0x00 0x3a 0x04 0x00 0x75 0x04>; + clocks = <0x68 0x69 0x6a 0x6b 0x6c>; + reg = <0x1f2a2000 0x800 0x1f343c00 0x600 0x1f2a2800 0x600>; + pad = <0x1f2079b8 0x01 0x01>; + pad_led = <0x1f20798c 0x77 0x21>; + phy-handle = <0x6d>; + status = "ok"; + + mdio-bus { + + ethernet-phy@0 { + phy-mode = "mii"; + linux,phandle = <0x6d>; + phandle = <0x6d>; + }; + }; + }; + + gpio { + compatible = "sstar,gpio"; + }; + + pwm { + compatible = "sstar,infinity-pwm"; + reg = <0x1f203200 0x400>; + npwm = <0x0b>; + pm_group_base = <0x1f003400>; + clocks = <0x6e>; + interrupts = <0x00 0x54 0x01>; + pad-ctrl = <0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff>; + status = "ok"; + }; + + aesdma { + compatible = "sstar,infinity-aes"; + interrupts = <0x00 0x37 0x04>; + clocks = <0x6f>; + status = "ok"; + }; + + miu { + compatible = "sstar,miu"; + interrupts = <0x00 0x51 0x04>; + status = "ok"; + }; + + mmu { + compatible = "sstar,mmu"; + interrupts = <0x00 0x2e 0x04>; + status = "ok"; + }; + + timer { + compatible = "sstar,timer"; + reg = <0x1f006040 0x40 0x1f006080 0x40 0x1f0060c0 0x40>; + interrupts = <0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x63 0x04>; + status = "ok"; + }; + + core_voltage { + vid_width = <0x02>; + vid_gpios = <0x0d 0x0e>; + vid_voltages = <0x352 0x384 0x3b6 0x3e8>; + }; + + Sstar-ehci-1 { + compatible = "Sstar-ehci-1"; + clocks = <0x70>; + interrupts = <0x00 0x3f 0x04>; + dpdm_swap = <0x00>; + power-enable-pad = <0x6b>; + status = "ok"; + }; + + Sstar-udc { + compatible = "sstar,infinity-udc"; + interrupts = <0x00 0x40 0x04>; + status = "ok"; + }; + + dwc3 { + compatible = "snps,dwc3"; + reg = <0x1f344200 0xcfff>; + clocks = <0x4d>; + clock-names = "ss_clk"; + maximum-speed = "super-speed"; + interrupts = <0x00 0x38 0x04>; + interrupt-names = "dwc_usb3"; + phy_type = "utmi_wide"; + phys = <0x71 0x71>; + phy-names = "usb2-phy\0usb3-phy"; + snps,incr-burst-type-adjustment = <0x01 0x04 0x08 0x10>; + }; + + iopower { + compatible = "sstar-iopower"; + reg = <0x1f002800 0x64>; + status = "disabled"; + pm_sar_atop_vddp1 = <0x00>; + pm_sar_atop_pmspi = <0x00>; + }; + + padmux { + compatible = "sstar-padmux"; + schematic = <0x6b 0x47 0x80000 0x6c 0x00 0x80100 0x6d 0x53 0x80200 0x6e 0x59 0x80300 0x6f 0x5f 0x80400 0x70 0x65 0x80500 0x71 0x6b 0x80600 0x72 0x71 0x80700 0x0f 0x7f 0x80900 0x1d 0x00 0x20000 0x21 0x39 0x20002 0x22 0x39 0x20003 0x20 0x39 0x20004 0x1f 0x39 0x20005 0x24 0x39 0x20006 0x23 0x39 0x20007 0x1e 0x3a 0x20001 0x39 0x00 0x20100 0x27 0x3c 0x20102 0x28 0x3c 0x20103 0x26 0x3c 0x20104 0x25 0x3c 0x20105 0x2a 0x3c 0x20106 0x29 0x3c 0x20107 0x2b 0x3e 0x20101 0x2c 0x88 0x10000 0x2d 0x8d 0x10100 0x31 0x00 0x70033 0x7f 0xff 0x00>; + status = "ok"; + }; + + ipu { + compatible = "sstar,ipu"; + operating-points = <0xdbba0 0xf4240 0xc3500 0xf4240 0x927c0 0xdbba0 0x7a120 0xdbba0 0x61a80 0xdbba0 0x493e0 0xcf850>; + status = "ok"; + }; + }; +}; diff --git a/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/patches/00_infinity6e_kernel_4.9.84_sdk.patch b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/patches/00_infinity6e_kernel_4.9.84_sdk.patch new file mode 100644 index 0000000..785206a --- /dev/null +++ b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/patches/00_infinity6e_kernel_4.9.84_sdk.patch @@ -0,0 +1,861289 @@ +diff --git a/Documentation/dev-tools/kasan.rst b/Documentation/dev-tools/kasan.rst +index f7a18f274357..fd4299110d86 100644 +--- a/Documentation/dev-tools/kasan.rst ++++ b/Documentation/dev-tools/kasan.rst +@@ -12,7 +12,7 @@ KASAN uses compile-time instrumentation for checking every memory access, + therefore you will need a GCC version 4.9.2 or later. GCC 5.0 or later is + required for detection of out-of-bounds accesses to stack or global variables. + +-Currently KASAN is supported only for the x86_64 and arm64 architectures. ++Currently KASAN is supported only for the x86_64, arm and arm64 architectures. + + Usage + ----- +diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt +index 703f5784bc90..c59267e172a1 100644 +--- a/Documentation/features/debug/KASAN/arch-support.txt ++++ b/Documentation/features/debug/KASAN/arch-support.txt +@@ -8,7 +8,7 @@ + ----------------------- + | alpha: | TODO | + | arc: | TODO | +- | arm: | TODO | ++ | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | +diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt +index 3db8c67d2c8d..0335285f3918 100644 +--- a/Documentation/networking/ip-sysctl.txt ++++ b/Documentation/networking/ip-sysctl.txt +@@ -122,14 +122,11 @@ min_adv_mss - INTEGER + + IP Fragmentation: + +-ipfrag_high_thresh - INTEGER +- Maximum memory used to reassemble IP fragments. When +- ipfrag_high_thresh bytes of memory is allocated for this purpose, +- the fragment handler will toss packets until ipfrag_low_thresh +- is reached. This also serves as a maximum limit to namespaces +- different from the initial one. +- +-ipfrag_low_thresh - INTEGER ++ipfrag_high_thresh - LONG INTEGER ++ Maximum memory used to reassemble IP fragments. ++ ++ipfrag_low_thresh - LONG INTEGER ++ (Obsolete since linux-4.17) + Maximum memory used to reassemble IP fragments before the kernel + begins to remove incomplete fragment queues to free up resources. + The kernel still accepts new fragments for defragmentation. +@@ -408,6 +405,7 @@ tcp_min_rtt_wlen - INTEGER + minimum RTT when it is moved to a longer path (e.g., due to traffic + engineering). A longer window makes the filter more resistant to RTT + inflations such as transient congestion. The unit is seconds. ++ Possible values: 0 - 86400 (1 day) + Default: 300 + + tcp_moderate_rcvbuf - BOOLEAN +diff --git a/Makefile b/Makefile +old mode 100644 +new mode 100755 +index db13b13cdcc2..28bd05e2f957 +--- a/Makefile ++++ b/Makefile +@@ -4,6 +4,8 @@ SUBLEVEL = 84 + EXTRAVERSION = + NAME = Roaring Lionus + ++SSTAR_CHIP_MODEL = infinity6e ++ + # *DOCUMENTATION* + # To see a list of typical targets execute "make help" + # More info can be located in ./README +@@ -410,6 +412,8 @@ GCC_PLUGINS_CFLAGS := + KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) + KERNELVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) + ++export SSTAR_CHIP_MODEL ++ + export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION + export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC + export CPP AR NM STRIP OBJCOPY OBJDUMP +@@ -802,15 +806,33 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=implicit-int) + # require functions to have arguments in prototypes, not empty 'int foo()' + KBUILD_CFLAGS += $(call cc-option,-Werror=strict-prototypes) + ++# disable warnings in gcc 4.9.4 + # Prohibit date/time macros, which would make the build non-deterministic +-KBUILD_CFLAGS += $(call cc-option,-Werror=date-time) ++#KBUILD_CFLAGS += $(call cc-option,-Werror=date-time) + + # enforce correct pointer usage + KBUILD_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types) + ++# disable warnings in gcc 8.2 ++KBUILD_CFLAGS += $(call cc-option,-Wno-stringop-overflow) ++KBUILD_CFLAGS += $(call cc-option,-Wno-attribute-alias) ++KBUILD_CFLAGS += $(call cc-option,-Wno-stringop-truncation) ++KBUILD_CFLAGS += $(call cc-option,-Wno-sizeof-pointer-memaccess) ++KBUILD_CFLAGS += $(call cc-option,-Wno-array-bounds) ++KBUILD_CFLAGS += $(call cc-option,-Wno-packed-not-aligned) ++ ++# disable warnings in gcc 9.2 ++KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) ++ ++# disable warnings in gcc 7.2.1 ++#KBUILD_CFLAGS += $(call cc-option,-Wno-switch-unreachable) ++#KBUILD_CFLAGS += $(call cc-option,-Wno-misleading-indentation) ++ + # use the deterministic mode of AR if available + KBUILD_ARFLAGS := $(call ar-option,D) + ++KBUILD_CFLAGS += -Werror ++ + include scripts/Makefile.kasan + include scripts/Makefile.extrawarn + include scripts/Makefile.ubsan +@@ -1000,10 +1022,68 @@ define filechk_kernel.release + echo "$(KERNELVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + endef + ++MS_KERNEL_TYPE := ++ifneq ($(CONFIG_MS_KERNEL_TYPE),"") ++ MS_KERNEL_TYPE=--lib_type $(CONFIG_MS_KERNEL_TYPE) ++endif ++ ++# Retrieve platform ID abbreviation with the following rules: UPPER_CASE(Part I+II+III) ++# Part I : the leading charactor ++# Part II : the 1st digit ++# Part III: the the reset after 1st digit ++# for examples: foobar2m -> F2M ++MS_PLATFORM_ID := $(shell echo $(SSTAR_CHIP_MODEL) | sed -e 's/^\([a-zA-Z]\)[a-zA-Z]*\([0-9]*\)\(.*\)/\1\2\3/g' | tr a-z A-Z) ++ ++COMMITNUMBER := g$(shell git log --format=%h -n 1 2> /dev/null) ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++GCCVERISON := $(shell $(CC) -dumpversion) ++ ++#COMMITNUMBER := g$(shell git log --format=%h -n 1 2> /dev/null) ++GITVERNUM := $(shell git log --format=%H -n 1 2> /dev/null) ++#BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++BUILDCODEDATE = $(shell date +"%Y_%m_%d_%H_%M_%S") ++BUILDCODEUSER = $(shell whoami) ++ ++ ++ifeq ($(COMMITNUMBER),g) ++file := gitInformation.txt ++gitLog := $(shell strings ${file}) ++gitTemp := $(subst \#, ,$(gitLog)) ++COMMITNUMBER := g$(word 1, $(gitTemp)) ++BRANCH_ID := g$(word 2, $(gitTemp)) ++endif ++ + # Store (new) KERNELRELEASE string in include/config/kernel.release + include/config/kernel.release: include/config/auto.conf FORCE + $(call filechk,kernel.release) ++ifneq ($(CONFIG_ARCH_SSTAR),) ++ @echo ' GCC version: $(GCCVERISON)' ++ifeq ($(MS_PLATFORM_ID),) ++ @echo "ERROR!! MS_PLATOFRM_ID is empty!!"; /bin/false ++else ++ @echo ' MVXV' ++ @echo ' changelist ${COMMITNUMBER}' ++ @echo ' BRANCHID ${BRANCH_ID} ' ++ @echo ' MS_PLATFORM_ID: $(MS_PLATFORM_ID)' ++ @python scripts/ms_gen_mvxv_h.py drivers/sstar/include/ms_version.h --comp_id KL_LX409 \ ++ --changelist $(COMMITNUMBER) --chip_id $(MS_PLATFORM_ID) --branch $(BRANCH_ID) $(MS_KERNEL_TYPE) ++endif ++endif + ++ifneq ($(CONFIG_SSTAR_CEVAXM6),) ++ @python scripts/ms_gen_ceva_version_h.py drivers/sstar/include/ms_version.h --comp_id KL_LX409 \ ++ --changelist $(COMMITNUMBER) --chip_id $(MS_PLATFORM_ID) --branch $(BRANCH_ID) $(MS_KERNEL_TYPE)\ ++ --gitver $(GITVERNUM) --builddate $(BUILDCODEDATE) --buildusr $(BUILDCODEUSER) ++endif ++ ++ifneq ($(CONFIG_CAM_DRIVERS),) ++ @mkdir -p drivers/sstar/camdriver/include ++ @python scripts/ms_gen_mvxv_h.py drivers/sstar/camdriver/include/mdrv_ms_version.h \ ++ --changelist g$(shell cd drivers/sstar/camdriver;git log --format=%h -n 1 2> /dev/null) \ ++ --branch $(shell cd drivers/sstar/camdriver;git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') \ ++ $(MS_KERNEL_TYPE) --chip_id $(MS_PLATFORM_ID) --comp_id CAMDRV_LX409 ++endif + + # Things we need to do before we recursively start building the kernel + # or the modules are listed in "prepare". +@@ -1206,6 +1286,9 @@ modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin + @$(kecho) ' Building modules, stage 2.'; + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modbuild ++ @if [ -e "./ms_pack_modules.sh" ]; then \ ++ ./ms_pack_modules.sh ${MODULE_PACK_OPTIONS}; \ ++ fi + + modules.builtin: $(vmlinux-dirs:%=%/modules.builtin) + $(Q)$(AWK) '!x[$$0]++' $^ > $(objtree)/modules.builtin +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +old mode 100644 +new mode 100755 +index b5d529fdffab..554bdec95151 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -38,6 +38,7 @@ config ARM + select HAVE_ARCH_HARDENED_USERCOPY + select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU + select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU ++ select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL + select HAVE_ARCH_MMAP_RND_BITS if MMU + select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_TRACEHOOK +@@ -227,6 +228,9 @@ config FIQ + config NEED_RET_TO_USER + bool + ++config MULTIPLATFORM_XIP_CAPABLE ++ bool ++ + config ARCH_MTD_XIP + bool + +@@ -325,11 +329,29 @@ choice + default ARM_SINGLE_ARMV7M if !MMU + default ARCH_MULTIPLATFORM if MMU + ++config ARCH_INFINITY2 ++ bool "MSTAR I-series family" ++ depends on MMU ++ select ARCH_WANT_OPTIONAL_GPIOLIB ++ select ARM_HAS_SG_CHAIN ++ select AUTO_ZRELADDR ++ select CLKSRC_OF ++ select COMMON_CLK ++ select GENERIC_CLOCKEVENTS ++ select MIGHT_HAVE_PCI ++ select MULTI_IRQ_HANDLER ++ select SPARSE_IRQ ++ select USE_OF ++ select CPU_V7 ++ select HAVE_SMP ++ select MIGHT_HAVE_CACHE_L2X0 ++ ++ + config ARCH_MULTIPLATFORM + bool "Allow multiple platforms to be selected" + depends on MMU + select ARM_HAS_SG_CHAIN +- select ARM_PATCH_PHYS_VIRT ++ select ARM_PATCH_PHYS_VIRT if !XIP_KERNEL + select AUTO_ZRELADDR + select CLKSRC_OF + select COMMON_CLK +@@ -763,6 +785,8 @@ source "arch/arm/mach-ks8695/Kconfig" + + source "arch/arm/mach-meson/Kconfig" + ++source "arch/arm/mach-sstar/Kconfig" ++ + source "arch/arm/mach-moxart/Kconfig" + + source "arch/arm/mach-aspeed/Kconfig" +@@ -1448,6 +1472,15 @@ config PAGE_OFFSET + default 0xB0000000 if VMSPLIT_3G_OPT + default 0xC0000000 + ++config KASAN_SHADOW_OFFSET ++ hex ++ depends on KASAN ++ default 0x1f000000 if PAGE_OFFSET=0x40000000 ++ default 0x5f000000 if PAGE_OFFSET=0x80000000 ++ default 0x9f000000 if PAGE_OFFSET=0xC0000000 ++ default 0x8f000000 if PAGE_OFFSET=0xB0000000 ++ default 0xffffffff ++ + config NR_CPUS + int "Maximum number of CPUs (2-32)" + range 2 32 +@@ -1738,6 +1771,7 @@ config FORCE_MAX_ZONEORDER + int "Maximum zone order" + default "12" if SOC_AM33XX + default "9" if SA1111 || ARCH_EFM32 ++ default "10" if ARCH_SSTAR + default "11" + help + The kernel memory allocator divides physically contiguous memory +@@ -1988,7 +2022,7 @@ endchoice + + config XIP_KERNEL + bool "Kernel Execute-In-Place from ROM" +- depends on !ARM_LPAE && !ARCH_MULTIPLATFORM ++ depends on (!ARM_LPAE && !ARCH_MULTIPLATFORM) || (!ARM_LPAE && MULTIPLATFORM_XIP_CAPABLE) + help + Execute-In-Place allows the kernel to run from non-volatile storage + directly addressable by the CPU, such as NOR flash. This saves RAM +@@ -2060,6 +2094,10 @@ config AUTO_ZRELADDR + 0xf8000000. This assumes the zImage being placed in the first 128MB + from start of memory. + ++config MEMORY_START_ADDRESS ++ hex "Physical address of the memory starting" ++ depends on ARCH_INFINITY2 ++ + config EFI_STUB + bool + +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +old mode 100644 +new mode 100755 +index 6be9ee148b78..8a06aba3200c +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_MESON) += meson + machine-$(CONFIG_ARCH_MMP) += mmp + machine-$(CONFIG_ARCH_MPS2) += vexpress + machine-$(CONFIG_ARCH_MOXART) += moxart ++machine-$(CONFIG_ARCH_SSTAR) += sstar + machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 + machine-$(CONFIG_ARCH_MVEBU) += mvebu + machine-$(CONFIG_ARCH_MXC) += imx +@@ -334,6 +335,13 @@ $(INSTALL_TARGETS): + + %.dtb: | scripts + $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@ ++ ifeq ($(CONFIG_SS_BUILTIN_DTB), y) ++ @if [ -e arch/arm/boot/Image ]; then \ ++ echo " BNDTB $@"; \ ++ python scripts/ms_builtin_dtb_update.py arch/arm/boot/Image arch/arm/boot/dts/$@; \ ++ echo; \ ++ fi; ++ endif + + PHONY += dtbs dtbs_install + +diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile +old mode 100644 +new mode 100755 +index 50f8d1be7fcb..152fc218ed84 +--- a/arch/arm/boot/Makefile ++++ b/arch/arm/boot/Makefile +@@ -13,6 +13,34 @@ + + OBJCOPYFLAGS :=-O binary -R .comment -S + ++ifneq ($(CONFIG_ARM_PATCH_PHYS_VIRT),) ++LD_ADDR = 0x20008000 ++else ++LD_ADDR = $(shell /bin/bash -c 'printf "0x%08x" $$[$(CONFIG_PHYS_OFFSET) + 0x8000]') ++endif ++ ++LOADADDR = ${LD_ADDR} ++ ++MKIMAGE_BIN = scripts/mkimage ++MZ_BIN = scripts/mz ++KERNEL_RELEASE_FILE = include/config/kernel.release ++ROOTFS = $(obj)/ramdisk_linaro4.8_minit.img.xz ++ ++_BUILTIN_DTB_NAME=$(strip $(shell echo ${CONFIG_SS_DTB_NAME})) ++ifneq ($(_BUILTIN_DTB_NAME),) ++ifneq ($(wildcard arch/arm/boot/dts/$(_BUILTIN_DTB_NAME).dts),) ++SS_DTB_NAME=arch/arm/boot/dts/$(_BUILTIN_DTB_NAME).dtb ++endif ++endif ++ ++CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++ifeq ($(CONFIG_FPGA),y) ++MS_EXTRA_DTBS=arch/arm/boot/dts/$(CHIP_NAME)-fpga.dtb ++else ++MS_EXTRA_DTBS= ++endif ++ + ifneq ($(MACHINE),) + include $(MACHINE)/Makefile.boot + endif +@@ -49,12 +77,71 @@ $(obj)/xipImage: FORCE + $(obj)/Image: vmlinux FORCE + $(call if_changed,objcopy) + +-$(obj)/compressed/vmlinux: $(obj)/Image FORCE ++$(obj)/compressed/vmlinux: $(obj)/Image FORCE $(SS_DTB_NAME) $(MS_EXTRA_DTBS) + $(Q)$(MAKE) $(build)=$(obj)/compressed $@ + + $(obj)/zImage: $(obj)/compressed/vmlinux FORCE + $(call if_changed,objcopy) ++ifneq ($(CONFIG_ARCH_SSTAR),) ++ifeq ($(CONFIG_SS_BUILTIN_DTB), y) ++ #update builtin DTB ++ @test "${SS_DTB_NAME}" = "" || \ ++ if [ -e ${SS_DTB_NAME} ]; then \ ++ echo " IMAGE $(obj)/Image"; \ ++ echo " BNDTB ${SS_DTB_NAME}"; \ ++ python scripts/ms_builtin_dtb_update.py $(obj)/Image ${SS_DTB_NAME}; \ ++ echo; \ ++ fi; ++ #update Image-fpga DTB ++ @if [ -e "arch/arm/boot/dts/$(CHIP_NAME)-fpga.dtb" ]; then \ ++ echo " IMAGE $(obj)/Image-fpga"; \ ++ cp -f $(obj)/Image $(obj)/Image-fpga; \ ++ echo " BNDTB $(CHIP_NAME)-fpga.dtb"; \ ++ python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpga "arch/arm/boot/dts/$(CHIP_NAME)-fpga.dtb"; \ ++ echo; \ ++ fi; ++endif ++ ++ifeq ($(CONFIG_SS_BUILTIN_UNFDT), y) ++ #update builtin UNFDT ++ @test "${SS_DTB_NAME}" = "" || \ ++ if [ -e ${SS_DTB_NAME} ]; then \ ++ echo " BNDTB ${SS_DTB_NAME}"; \ ++ scripts/dtc/dtb2unfdt/dtb2unfdt ${SS_DTB_NAME} $(obj)/unfdt.bin; \ ++ python scripts/ms_builtin_unfdt_update.py $(obj)/Image $(obj)/unfdt.bin; \ ++ echo; \ ++ fi; ++endif + ++ #update the image size into Image ++ @python scripts/ms_bin_option_update_int.py $(obj)/Image '#IMG_SZ#' $$(stat -c %s $(obj)/Image) ++ #build Image ++ @IMGNAME=$(shell strings -a -T binary $(obj)/Image | grep 'MVX' | grep 'LX' | sed 's/\\*MVX/MVX/g' | cut -c 1-32 ); \ ++ if [ -e ${MKIMAGE_BIN} ]; then \ ++ ${MKIMAGE_BIN} -A arm -O linux -T kernel -C none -a ${LD_ADDR} -e ${LD_ADDR} -n $${IMGNAME} -d $(obj)/Image $(obj)/uImage; \ ++ echo; \ ++ echo 'Compress Kernel Image'; \ ++ xz -z -k -f $(obj)/Image; \ ++ ${MKIMAGE_BIN} -A arm -O linux -C lzma -a ${LD_ADDR} -e ${LD_ADDR} -n $${IMGNAME} -d $(obj)/Image.xz $(obj)/uImage.xz; \ ++ ${MZ_BIN} c $(obj)/Image $(obj)/Image.mz ; \ ++ echo; \ ++ ${MKIMAGE_BIN} -A arm -O linux -C mz -a ${LD_ADDR} -e ${LD_ADDR} -n $${IMGNAME} -d $(obj)/Image.mz $(obj)/uImage.mz; \ ++ echo; \ ++ else \ ++ echo ">> Can't find $${MKIMAGE}. Please check the u-boot path or build u-boot <<"; \ ++ fi; \ ++ if [ -e $(ROOTFS) ]; then \ ++ ${MKIMAGE_BIN} -A arm -O linux -T multi -C none -a ${LD_ADDR} -e ${LD_ADDR} -n $${IMGNAME} -d $(obj)/Image:$(ROOTFS) $(obj)/kernel.img; \ ++ echo; \ ++ if [ -e ${MZ_BIN} ]; then \ ++ ${MZ_BIN} c $(obj)/Image $(obj)/Image.mz ; \ ++ echo; \ ++ ${MKIMAGE_BIN} -A arm -O linux -T multi -C mz -a ${LD_ADDR} -e ${LD_ADDR} -n $${IMGNAME} -d $(obj)/Image.mz:$(ROOTFS) $(obj)/kernel.mz.img; \ ++ echo; \ ++ fi; \ ++ fi; ++ @echo ++endif + endif + + ifneq ($(LOADADDR),) +diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile +index d50430c40045..ab5693b21d39 100644 +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -23,6 +23,7 @@ OBJS += hyp-stub.o + endif + + GCOV_PROFILE := n ++KASAN_SANITIZE := n + + # + # Architecture dependencies +diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c +index a0765e7ed6c7..5719ded8aa66 100644 +--- a/arch/arm/boot/compressed/decompress.c ++++ b/arch/arm/boot/compressed/decompress.c +@@ -46,8 +46,13 @@ extern char * strstr(const char * s1, const char *s2); + #endif + + #ifdef CONFIG_KERNEL_XZ ++#ifndef memmove + #define memmove memmove ++#endif ++ ++#ifndef memcpy + #define memcpy memcpy ++#endif + #include "../../../../lib/decompress_unxz.c" + #endif + +diff --git a/arch/arm/boot/compressed/string.c b/arch/arm/boot/compressed/string.c +index 689467448736..7c01641a5932 100644 +--- a/arch/arm/boot/compressed/string.c ++++ b/arch/arm/boot/compressed/string.c +@@ -6,6 +6,25 @@ + + #include + ++/* ++ * The decompressor is built without KASan but uses the same redirects as the ++ * rest of the kernel when CONFIG_KASAN is enabled, defining e.g. memcpy() ++ * to __memcpy() but since we are not linking with the main kernel string ++ * library in the decompressor, that will lead to link failures. ++ * ++ * Undefine KASan's versions, define the wrapped functions and alias them to ++ * the right names so that when e.g. __memcpy() appear in the code, it will ++ * still be linked to this local version of memcpy(). ++ */ ++#ifdef CONFIG_KASAN ++#undef memcpy ++#undef memmove ++#undef memset ++void *__memcpy(void *__dest, __const void *__src, size_t __n) __alias(memcpy); ++void *__memmove(void *__dest, __const void *__src, size_t count) __alias(memmove); ++void *__memset(void *s, int c, size_t count) __alias(memset); ++#endif ++ + void *memcpy(void *__dest, __const void *__src, size_t __n) + { + int i = 0; +@@ -129,8 +148,3 @@ void *memset(void *s, int c, size_t count) + *xs++ = c; + return s; + } +- +-void __memzero(void *s, size_t count) +-{ +- memset(s, 0, count); +-} +diff --git a/arch/arm/boot/dts/infinity2-clks.dtsi b/arch/arm/boot/dts/infinity2-clks.dtsi +new file mode 100755 +index 000000000000..ab31051a8e35 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2-clks.dtsi +@@ -0,0 +1,53 @@ ++/* */ ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_cevapll_clk: CLK_cevapll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_12m>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; ++ mux-width = <3>; ++ gate-shift = <8>; ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <3>;//[4:2]: Select clock source ++ gate-shift = <0>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_uart2: CLK_uart2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //10+REG_CKG_UART2_OFFSET ++ mux-width = <3>;//[4:2]: Select clock source ++ gate-shift = <8>; //8+REG_CKG_UART2_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART2_OFFSET ++ mux-width = <2>;//[3:2]: Select clock source ++ gate-shift = <0>; //0+REG_CKG_UART2_OFFSET ++}; +diff --git a/arch/arm/boot/dts/infinity2-msc006a-s01a-s.dts b/arch/arm/boot/dts/infinity2-msc006a-s01a-s.dts +new file mode 100755 +index 000000000000..d107666e6d7e +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2-msc006a-s01a-s.dts +@@ -0,0 +1,201 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity2.dtsi" ++ ++ ++/ { ++ model = "INFINITY2 MSC006A-S01A-S"; ++ compatible = "sstar,infinity2"; ++ ++ memory { ++ reg = <0x20000000 0x20000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc"; ++ /*linux,initrd-start = <0x21FE0000>; ++ linux,initrd-end = <0x22000000>;*/ ++ }; ++ ++/* rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x2D000000 0x03000000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++*/ ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ XM6_reserved: XM6_reserved@500000 { ++ reg = <0x3FB00000 0x500000>; ++ status = "okay"; ++ }; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++/* ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x6400000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++*/ ++ }; ++ ++ soc{ ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ //isp-flag = <0x3>; //enable DNR and ROT ++ //isp-res = <0x5>; //max image size 5M ++ }; ++ vif { ++ ccir0_ctrl_mode = <1>; ++ ccir1_ctrl_mode = <1>; ++ ccir2_ctrl_mode = <1>; ++ ccir3_ctrl_mode = <1>; ++ ++ ccir0_8b_mode = <1>; ++ ccir1_8b_mode = <1>; ++ ccir2_8b_mode = <1>; ++ ccir3_8b_mode = <1>; ++ ++ ccir0_clk_mode = <1>; ++ ccir1_clk_mode = <1>; ++ ccir2_clk_mode = <1>; ++ ccir3_clk_mode = <1>; ++ ++ ccir0_16b_mode = <0>; ++ ccir2_16b_mode = <0>; ++ mcu = <1>; //1:Enable MCU 0:Disable MCU ++ }; ++ ispmid { ++ compatible = "mstar,ispmid"; ++ status = "ok"; ++ }; ++ sensorif { ++ compatible = "sigma,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <1>; ++ sensorif_grp2_i2c = <2>; ++ sensorif_grp3_i2c = <2>; ++ }; ++ pwm{ ++ /*PWM0: PAD_PWM0 (PAD_PWM0, PAD_MIPI_TX_IO0, PAD_SNR3_D0) ++ * PWM1: PAD_PWM1 (PAD_PWM1, PAD_MIPI_TX_IO1, PAD_SNR3_D1) ++ * PWM2: PAD_GPIO8 (PAD_GPIO8, PAD_MIPI_TX_IO2, PAD_SNR3_D2) ++ * PWM3: PAD_GPIO9 (PAD_GPIO9, PAD_MIPI_TX_IO3, PAD_SNR3_D3) ++ * PWM4: PAD_GPIO10 (PAD_GPIO10, PAD_MIPI_TX_IO4, PAD_SNR3_D8) ++ * PWM5: PAD_SNR3_D9 (PAD_GPIO11, PAD_MIPI_TX_IO5, PAD_SNR3_D9) ++ * PWM6: PAD_PM_LED0 (PAD_GPIO12, PAD_MIPI_TX_IO6, PAD_PW_LED0) ++ * PWM7: PAD_PM_LED1 (PAD_GPIO13, PAD_MIPI_TX_IO7, PAD_PW_LED1) ++ */ ++ pad-ctrl = ; ++ }; ++ i2c0@0 { ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * padmux: 2 -> PAD_SNR3_GPIO6 , PAD_SNR3_GPIO7 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1 { ++ /* ++ * padmux: 1 -> PAD_SNR0_GPIO6, PAD_SNR0_GPIO7 ++ * padmux: 2 -> PAD_SNR1_GPIO6, PAD_SNR1_GPIO7 ++ * padmux: 3 -> PAD_SNR0_GPIO6, PAD_SNR0_GPIO7 ++ * +PAD_SNR1_GPIO6, PAD_SNR1_GPIO7 ++ * padmux: 4 -> PAD_SNR1_GPIO6, PAD_SNR1_GPIO7 ++ * +PAD_SNR2_GPIO6, PAD_SNR2_GPIO7 ++ * +PAD_SNR3_GPIO6, PAD_SNR3_GPIO7 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ i2c2@2 { ++ /* ++ * padmux: 1 -> PAD_I2C2_SDA, PAD_I2C2_SCL ++ * padmux: 2 -> MIPI_TX_IO8, MIPI_TX_IO9 ++ * padmux: 3 -> PAD_GPIO5, PAD_GPIO4 ++ * padmux: 4 -> PAD_NAND_DA6, PAD_NAND_DA7 ++ * padmux: 5 -> PAD_SNR3_GPIO6, PAD_SNR3_GPIO7 ++ * padmux: 6 -> PAD_SNR3_GPIO6, PAD_SNR3_GPIO7 ++ * padmux: 7 -> PAD_SNR2_GPIO6, PAD_SNR2_GPIO7 ++ * +PAD_SNR3_GPIO6, PAD_SNR3_GPIO7 ++ */ ++ i2c-padmux = <7>; ++ }; ++ i2c3@3 { ++ /* ++ * padmux: 1 -> PAD_I2C3_SDA, PAD_I2C3_SCL ++ * padmux: 2 -> PAD_TTL_GPIO2, PAD_TTL_GPIO1 ++ * padmux: 3 -> PAD_SNR1_GPIO6 , PAD_SNR1_GPIO7 ++ * padmux: 4 -> PAD_SNR2_GPIO6, PAD_SNR2_GPIO7 ++ * padmux: 5 -> PAD_HDMITX_SDA , PAD_HDMITX_SCL ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ power-enable-pad = ; ++ power-enable-voltage = <1>; ++ ++ }; ++ ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ power-enable-pad = ; ++ power-enable-voltage = <1>; ++ ++ }; ++ ++ Sstar-ehci-3 { ++ compatible = "Sstar-ehci-3"; ++ power-enable-pad = ; ++ power-enable-voltage = <1>; ++ ++ }; ++ ++ Sstar-ehci-4 { ++ compatible = "Sstar-ehci-4"; ++ power-enable-pad = ; ++ power-enable-voltage = <1>; ++ ++ }; ++ ++ vcore_info { ++ compatible = "sstar,vcore_info"; ++ gpio_total_num = <2>; ++ gpio_pins = ; ++ voltages = <903 950 1000 1050>; ++ status = "ok"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity2.dtsi b/arch/arm/boot/dts/infinity2.dtsi +new file mode 100755 +index 000000000000..c6fd48fa5331 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2.dtsi +@@ -0,0 +1,881 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity2/irqs.h> ++#include <../../../../drivers/sstar/include/infinity2/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <0x0>; ++ //clocks = <&CLK_cpupll_clk>; ++ }; ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <0x1>; ++ //clocks = <&CLK_cpupll_clk>; ++ }; ++ ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ arm_timer_clk: arm_timer_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <500000000>; ++ }; ++/* ++ periph_clk: periph_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ clock-output-names = "periph"; ++ }; ++ */ ++ }; ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ /*serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3;*/ ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a9-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16000100 0x100>; ++ }; ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++/* ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++*/ ++/* ++ ms_pmsleep_intr: interrupt-controller@0 { ++ compatible = "mstar,intrctl-infinity2"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++*/ ++ global_timer { ++ interrupt-parent = <&gic>; ++ compatible = "arm,cortex-a9-global-timer"; ++ reg = <0x16000200 0x100>; ++ interrupts = ; ++ clocks = <&arm_timer_clk>; ++ }; ++ ++ local_timer: local-timer@1e600 { ++ compatible = "arm,cortex-a9-twd-timer"; ++ reg = <0x1e600 0x20>; ++ interrupts = ; ++ clocks = <&arm_timer_clk>; ++ }; ++ ++ twd_watchdog: watchdog@1e620 { ++ compatible = "arm,cortex-a9-twd-wdt"; ++ reg = <0x1e620 0x20>; ++ interupts = ; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts =, ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ ++ uart0: uart0@1F201300 { ++ compatible = "sstar,uart"; ++ reg = <0x1F201300 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++ status = "ok"; ++ }; ++ timer0 { ++ compatible = "sstar,timer0"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ timer1 { ++ compatible = "sstar,timer1"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ timer2{ ++ compatible = "sstar,timer2"; ++ interrupts = ; ++ status = "ok"; ++ }; ++/* ++ uart1: uart1@1F220C00 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220C00 0x100>; ++ interrupts = ; ++ pad = ; ++ clocks = <&CLK_uart1>; ++ status = "ok"; ++ }; ++ ++ uart2: uart2@1F220A00 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220A00 0x100>; ++ interrupts = ; ++ pad = ; ++ clocks = <&CLK_uart2>; ++ status = "ok"; ++ }; ++ uart3: uart3@1F220D00 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220D00 0x100>; ++ interrupts = ; ++ pad = ; ++ clocks = <&CLK_fuart>; ++ status = "ok"; ++ }; ++ Not ready ++ fuart: uart3@1F220A00 { ++ compatible = "mstar,uart"; ++ reg = <0x1F220D00 0x100>, <0x1F206980 0x20>; ++ interrupts = ; ++ dma = <1>; ++ //clocks = <&CLK_fuart>; ++ pad = ; ++ status = "disable"; ++ }; ++*/ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ /*clocks = <&CLK_bdma>;*/ ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ vif { ++ compatible = "mstar,vif"; ++ status = "ok"; ++ reg = <0x1F2A0400 0xC00>,<0x1F2E0A00 0x400>,<0x1F201200 0x200>,<0x1F002000 0x200>,<0x1F001C00 0x200>,<0x1F206600 0x200>, <0x1F204c00 0x200>, <0x1F286400 0x200>, <0x1F201400 0x200>, <0x1F000000 0x400000>; ++ IPCRamPhys = <0x20200000>; ++ //clocks = <&xtal>; ++/* ++ ccir0_ctrl_mode = <1>; ++ ccir1_ctrl_mode = <0>; ++ ccir2_ctrl_mode = <0>; ++ ccir3_ctrl_mode = <0>; ++ ++ ccir0_8b_mode = <1>; ++ ccir1_8b_mode = <1>; ++ ccir2_8b_mode = <1>; ++ ccir3_8b_mode = <1>; ++ ++ ccir0_clk_mode = <1>; ++ ccir1_clk_mode = <1>; ++ ccir2_clk_mode = <1>; ++ ccir3_clk_mode = <1>; ++ ++ ccir0_16b_mode = <0>; ++ ccir2_16b_mode = <0>; ++*/ ++ }; ++ ++ csi { ++ compatible = "csi"; ++ //io_phy_addr = <0x1f000000>; ++ //banks = <0x1204>; ++ //interrupts = ; ++ status = "ok"; ++ }; ++ ++ ispalgo { ++ compatible = "mstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ middle { ++ compatible = "mstar,middle"; ++ status = "ok"; ++ }; ++ ++ vip: vip { ++ compatible = "mstar,vip"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ ethsys: syscon@1fc00000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "eth,noe-sys"; ++ reg = <0x1fc00000 0x200000>; ++ #clock-cells = <1>; ++ }; ++ ++ eth: ethernet{ ++ compatible = "eth,noe"; ++ interrupts = , ++ , ++ ; ++ noe,ethsys = <ðsys>; ++ #reset-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "ok"; ++ }; ++ ++ mdip: mdip { ++ compatible = "mstar,dip"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ sclmgwin: sclmgwin { ++ compatible = "mstar,sclmgwin"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ sclhvsp1_i2: sclhvsp1_i2 { ++ compatible = "mstar,sclhvsp1_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ++ , ++ ; ++ }; ++ ++ sclhvsp2_i2: sclhvsp2_i2 { ++ compatible = "mstar,sclhvsp2_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ++ ; ++ }; ++ ++ sclhvsp3_i2: sclhvsp3_i2 { ++ compatible = "mstar,sclhvsp3_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ sclhvsp4_i2: sclhvsp4_i2 { ++ compatible = "mstar,sclhvsp4_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ scldma1_i2: scldma1_i2 { ++ compatible = "mstar,scldma1_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ scldma2_i2: scldma2_i2 { ++ compatible = "mstar,scldma2_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ scldma3_i2: scldma3_i2 { ++ compatible = "mstar,scldma3_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ scldma4_i2: scldma4_i2 { ++ compatible = "mstar,scldma4_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ //clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ //clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ }; ++ ++ vcore_dvfs: vcore_dvfs { ++ compatible = "sstar,vcore_dvfs"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <8>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ //clocks = <&CLK_mcu>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ //clocks = <&CLK_mcu>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ //clocks = <&CLK_mcu>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ //clocks = <&CLK_mcu>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq4 { ++ compatible = "sstar,cmdq4"; ++ //clocks = <&CLK_mcu>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ //clocks = <&CLK_rtc>; ++ }; ++ ++ rtcpwc { ++ compatible = "sstar,infinity-rtcpwc"; ++ reg = <0x1F006800 0x200>; ++ //interrupts=; //need to check ++ //clocks = <&CLK_rtc>; ++ }; ++ ++ ir { ++ compatible = "mstar,ir"; ++ reg = <0x1F007A00 0x200>; ++ interrupts=; ++ }; ++ ++ spi0@0 { ++ compatible = "sstar_spi"; ++ spi-num = <0>; ++ pad-mode = <1>; ++ reg = <0x1F202600 0x200>,<0x1F204c00 0x200>,<0x1F201600 0x200>; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ spi-max-frequency = <100000>; ++ }; ++ }; ++ ++ spi1@1 { ++ compatible = "sstar_spi"; ++ spi-num = <1>; ++ pad-mode = <1>; ++ reg = <0x1F201800 0x200>,<0x1F204c00 0x200>,<0x1F201600 0x200>; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ reg = <1>; ++ spi-max-frequency = <100000>; ++ }; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ status = "ok"; ++ reg = <0x1F226800 0x200>,<0x1F204c00 0x200>,<0x1F206600 0x200>; ++ //clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ i2c-dma = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ rt1716@4e { ++ compatible = "richtek,rt1716"; ++ reg = <0x4e>; ++ rt1716,irq_pin = ; ++ rt-dual,supported_modes = <2>; /* 0: dfp/ufp, 1: dfp, 2: ufp */ ++ rt-tcpc,name = "rt1716"; /* tcpc_device's name */ ++ rt-tcpc,role_def = <0>; /* 0: SNK Only, 1: SRC Only, 2: DRP, 3: Try.SRC, 4: Try.SNK */ ++ rt-tcpc,rp_level = <0>; /* 0: Default, 1: 1.5, 2: 3.0 */ ++ rt-tcpc,notifier_supply_num = <0>; /* the number of notifier supply */ ++ }; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ status = "ok"; ++ reg = <0x1F226A00 0x200>,<0x1F204c00 0x200>,<0x1F206600 0x200>; ++ //clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ i2c-dma = <1>; ++ /* ++ * padmux: 1 -> PAD_SNR0_GPIO6, PAD_SNR0_GPIO7 ++ * padmux: 2 -> PAD_SNR1_GPIO6, PAD_SNR1_GPIO7 ++ * padmux: 3 -> TBC, TBC ++ * padmux: 4 -> TBC, TBC ++ ++ i2c-padmux = <1>; ++ */ ++ ++ //24c512@54 { ++ // compatible = "mstar,24c512"; ++ // reg = <0x54>; ++ //}; ++ ++ // if use rtc chip it7c4337 on i2c1 bus, just open this ++ /* ++ #address-cells = <1>; ++ #size-cells = <0>; ++ it7c4337@68 { ++ compatible = "rtc,it7c4337"; ++ reg = <0x68>; ++ }; ++ */ ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ status = "ok"; ++ reg = <0x1F226C00 0x200>,<0x1F204c00 0x200>,<0x1F206600 0x200>; ++ //clocks = <&CLK_miic2>; ++ i2c-group = <2>; ++ i2c-dma = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C2_SDA, PAD_I2C2_SCL ++ * padmux: 2 -> MIPI_TX_IO8, MIPI_TX_IO9 ++ * padmux: 3 -> PAD_GPIO5, PAD_GPIO4 ++ * padmux: 4 -> PAD_NAND_DA6, PAD_NAND_DA7 ++ * padmux: 5 -> PAD_SNR3_GPIO6, PAD_SNR3_GPIO7 ++ * padmux: 6 -> PAD_SNR3_GPIO6, PAD_SNR3_GPIO7 ++ * padmux: 7 -> TBC, TBC ++ i2c-padmux = <1> ; ++ */ ++ }; ++ ++ i2c3@3{ ++ compatible = "sstar,i2c"; ++ status = "ok"; ++ reg = <0x1F227400 0x200>,<0x1F204c00 0x200>,<0x1F201400 0x200>; ++ //clocks = <&CLK_miic3>; ++ i2c-group = <3>; ++ i2c-dma = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C3_SDA, PAD_I2C3_SCL ++ * padmux: 2 -> PAD_TTL_GPIO2, PAD_TTL_GPIO1 ++ * padmux: 3 -> PAD_SNR1_GPIO6 , PAD_SNR1_GPIO7 ++ * padmux: 4 -> PAD_SNR2_GPIO6, PAD_SNR2_GPIO7 ++ * padmux: 5 -> PAD_HDMITX_SDA , PAD_HDMITX_SCL ++ i2c-padmux = <1> ;*/ ++ }; ++ ++ sdmmc { ++ compatible = "mstar,sdmmc"; ++ ++ slotnum = <2>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-max-clks = <200000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<0>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-pwr-gpios = <19>,<0>,<0>; ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ ++ //clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>; ++ //clocks = <&CLK_fcie_syn>,<&CLK_sdio_0>,<&CLK_sdio_1>; ++ interrupts = , ; ++ ++ }; ++ ++ mfe0: mfe0 { ++ compatible = "mstar,mfe0", "mstar,mfe"; ++ reg = <0x1F222000 0x300>; ++ interrupts=; ++ //clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ //clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ mfe1: mfe1 { ++ compatible = "mstar,mfe1"; ++ reg = <0x1F2E7200 0x300>; ++ interrupts=; ++ //clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ //clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ mhe0: mhe0 { ++ compatible = "mstar,mhe0", "mstar,mhe"; ++ reg = <0x1F2E3A00 0x100>,<0x1F2E3C00 0x100>,<0x1F2E3E00 0x100>,<0x1F2E1200 0x100>; ++ interrupts=; ++ //clocks = <&CLK_mhe>,<&GATE_MCM_mhe>, <&GATE_SRAM_mhe>; ++ //clock-names = "CKG_mhe"; ++ status = "ok"; ++ }; ++ ++ mhe1: mhe1 { ++ compatible = "mstar,mhe1"; ++ reg = <0x1F2E7800 0x100>,<0x1F2E7A00 0x100>,<0x1F2E7C00 0x100>,<0x1F2E7E00 0x100>; ++ interrupts=; ++ //clocks = <&CLK_mhe>,<&GATE_MCM_mhe>, <&GATE_SRAM_mhe>; ++ //clock-names = "CKG_mhe"; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe0 { ++ compatible = "mstar,cedric-jpe"; ++ reg = <0x1F202A00 0x100>; ++ interrupts = ; ++ //clocks = <&CLK_jpe>,<&GATE_MCM_jpe>, <&GATE_SRAM_jpe>; ++ //clock-names = "CKG_jpe"; ++ //clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ sound { ++ compatible = "mstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ ++ amp-gpio = ; ++ //clocks = <&CLK_upll_384m>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>; ++ }; ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++// vid0-gpio = ; ++ vid1-gpio = ; ++ }; ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ /*clocks =<&CLK_bdma>;*/ ++ status = "ok"; ++ }; ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ }; ++ ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = ; ++ reg = <0x1F244000 0x800>, <0x1F344200 0x600>, <0x1F006200 0x600>; ++// pad = <0x1F203C3C 0x0004 0x0000>; ++ phy-handle = <&phy0>; ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ gmac { ++ compatible = "mstar-gmac"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "mstar_mci"; ++ //clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ /* EMMC PAD - 1: NAND pad, 2: SNR0 pad */ ++ pad = <1>; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ //clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ //clocks = <&CLK_utmi>; ++ interrupts = ; ++ //dpdm_swap=<0>; ++ //power-enable-pad = ; //PAD_SPI0_CK ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ //clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ //clocks = <&CLK_utmi>; ++ interrupts = ; ++ //dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-3 { ++ compatible = "Sstar-ehci-3"; ++ //clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ //clocks = <&CLK_utmi>; ++ interrupts = ; ++ //dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-4 { ++ compatible = "Sstar-ehci-4"; ++ //clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ //clocks = <&CLK_utmi>; ++ interrupts = ; ++ //dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Sstar-xhci-1 { ++ compatible = "Sstar-xhci-1"; ++ //clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ //dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Sstar-xhci-2 { ++ compatible = "Sstar-xhci-2"; ++ //clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ //dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Mstar-udc { ++ compatible = "Mstar-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ //io_phy_addr = <0x1f000000>; ++ //banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ //interrupts = ; ++ //clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ //clk-pad = ; ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ //isp-flag = <0>; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F223A00 0x100>,<0x1F223C00 0x100>; ++ interrupts = ; ++ //clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ warp: warp@0x1F344800 { ++ compatible = "sstar,infinity2-warp"; ++ reg = <0x1F344800 0x100>,<0x1F225000 0x100>,<0x1F224c00 0x40>,<0x1F224c40 0x40>,<0x1F224E00 0x40>,<0x1F224E40 0x40>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ xm6: xm6@0x1F344800 { ++ compatible = "sstar,infinity2-xm6"; ++ reg = <0x1F344800 0x100>,<0x1F225000 0x100>,<0x1F224c00 0x40>,<0x1F224c40 0x40>,<0x1F224E00 0x40>,<0x1F224E40 0x40>,<0xC0400000 0x100>,<0x1F203C00 0x100>,<0x1F2C5C00 0x100>; ++ interrupts = ; ++ clocks = <&CLK_cevapll_clk>; ++ status = "ok"; ++ }; ++ ++ swi2c0@0{ ++ compatible = "sstar,swi2c"; ++ //status = "ok"; ++ port-idx = <0>; ++ i2c-group = <4>; ++ i2c-speed = <100>; ++ sda-gpio = ; ++ scl-gpio = ; ++ ++ //pcf8563@51 { ++ // compatible = "nxp,pcf8563"; ++ // reg = <0x51>; ++ //}; ++ }; ++ ++ movedma { ++ compatible = "sstar,movdma"; ++ reg = <0x1F224A00 0x100>; ++ interrupts=; ++ /*clocks = <&CLK_miu>;*/ ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ /*clocks = <&CLK_miu>;*/ ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ /*clocks = <&CLK_miu>;*/ ++ status = "ok"; ++ }; ++ ++ sata { ++ compatible = "sstar,sata", "sstar,sata-ahci"; ++ interrupts=; ++ reg-names = "ahci", "ahci_port0", "ahci_misc"; ++ reg = <0x1F205600 0x100>, <0x1F205800 0x100>, <0x1F205A00 0x200>; ++ phy_mode = <1>; ++ }; ++ ++ sata1 { ++ compatible = "sstar,sata1", "sstar,sata-ahci1"; ++ interrupts=; ++ reg-names = "ahci", "ahci_port0", "ahci_misc"; ++ reg = <0x1F226200 0x100>, <0x1F226400 0x100>, <0x1F226600 0x200>; ++ phy_mode = <1>; ++ }; ++ gfx { ++ compatible = "sstar,gfx"; ++ interrupts=; ++ status = "ok"; ++ }; ++ disp { ++ compatible = "sstar,disp"; ++ interrupts=; ++ status = "ok"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity2/reg_clks.h> ++ #include "infinity2-clks.dtsi" ++}; +diff --git a/arch/arm/boot/dts/infinity2m-BGA128M.dts b/arch/arm/boot/dts/infinity2m-BGA128M.dts +new file mode 100755 +index 000000000000..d65ec441155c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-BGA128M.dts +@@ -0,0 +1,69 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++ ++/ { ++ model = "INFIITY2M SSC007A-S01A"; ++ compatible = "sstar,infinity2m"; ++ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reg = <0x26E00000 0x01000000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ Sstar-ehci-3 { ++ compatible = "Sstar-ehci-3"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ cpufreq { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ vid_default = <0>; //2b'00 ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity2m-clks.dtsi b/arch/arm/boot/dts/infinity2m-clks.dtsi +new file mode 100755 +index 000000000000..468e7e21c82c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-clks.dtsi +@@ -0,0 +1,1540 @@ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I2m/iNfinity2m_Clock_Table_20190226_SW.xls */ ++/* REG FILENAME: I2m/iNfinity2m_reg_CLKGEN.xls, I2m/iNfinity2m_reg_pm_sleep.xls, I2m/iNfinity2m_reg_block.xls, I2m/iNfinity2m_reg_chiptop.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi_480m: CLK_utmi_480m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div32: CLK_mpll_288m_div32 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <32>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div2: CLK_lpll_clk_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div4: CLK_lpll_clk_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div8: CLK_lpll_clk_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_dec_gp: CLK_riu_w_clk_dec_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fcie_p: CLK_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_mipi_tx_dsi_p: CLK_mipi_tx_dsi_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mipi_tx_dsi>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sc_pixel_p: CLK_sc_pixel_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sc_pixel>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_armpll_37p125m: CLK_armpll_37p125m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_hdmi_in: CLK_hdmi_in { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_dac_in: CLK_dac_in { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dec_gp: CLK_miu_dec_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_miic0: CLK_miu_miic0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_miic1: CLK_miu_miic1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dma0: CLK_miu_dma0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_nogating: CLK_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_dec_gp: CLK_riu_dec_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_dec_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CHIPTOP_DUMMY_1_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <5>; //5+REG_CKG_MCU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_uart2: CLK_uart2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_UART2_OFFSET ++ mux-width = <2>; ++ gate-shift = <12>; //0+REG_CKG_UART2_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_pwr_ctl: CLK_pwr_ctl { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_PWR_CTL_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_PWR_CTL_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live_c: CLK_live_c { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sata_phy_108: CLK_sata_phy_108 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SATA_PHY_108_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SATA_PHY_108_OFFSET ++}; ++ ++CLK_sata_phy_432: CLK_sata_phy_432 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SATA_PHY_432_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_SATA_PHY_432_OFFSET ++}; ++ ++CLK_disp_432: CLK_disp_432 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DISP_432_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DISP_432_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_bist_dec_gp: CLK_bist_dec_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_DEC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_DEC_GP_OFFSET ++}; ++ ++CLK_dec_pclk: CLK_dec_pclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DEC_PCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DEC_PCLK_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_dec_aclk: CLK_dec_aclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_DEC_ACLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_DEC_ACLK_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_dec_bclk: CLK_dec_bclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CLKGEN0_RESERVED0_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CLKGEN0_RESERVED0_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_dec_cclk: CLK_dec_cclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_384m>,<&CLK_mpll_432m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //10+REG_CLKGEN0_RESERVED0_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //8+REG_CLKGEN0_RESERVED0_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; //max safe clock is 320m ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_dip: CLK_dip { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DIP_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_DIP_OFFSET ++}; ++ ++CLK_ge: CLK_ge { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_432m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_GE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_GE_OFFSET ++}; ++ ++CLK_mop: CLK_mop { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_288m>,<&CLK_utmi_240m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MOP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MOP_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_disp_216: CLK_disp_216 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_DISP_216_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_DISP_216_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_sc_pixel: CLK_sc_pixel { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_lpll_clk>,<&CLK_lpll_clk_div2>,<&CLK_lpll_clk_div4>,<&CLK_lpll_clk_div8>,<&CLK_mpll_288m_div8>,<&CLK_mpll_288m_div32>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SC_PIXEL_OFFSET ++ mux-width = <4>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SC_PIXEL_OFFSET ++}; ++ ++CLK_sata_pm: CLK_sata_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_xtali_12m>,<&CLK_xtali_24m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SATA_PM_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_SATA_PM_OFFSET ++}; ++ ++CLK_sata_axi: CLK_sata_axi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_288m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SATA_AXI_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SATA_AXI_OFFSET ++}; ++ ++CLK_mipi_tx_dsi: CLK_mipi_tx_dsi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_lpll_clk>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIPI_TX_DSI_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_MIPI_TX_DSI_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_mipi_tx_dsi_apb: CLK_mipi_tx_dsi_apb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_mipi_tx_dsi_p>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIPI_TX_DSI_APB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIPI_TX_DSI_APB_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_hdmi: CLK_hdmi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_hdmi_in>,<&CLK_sc_pixel_p>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_HDMI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_HDMI_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_dac: CLK_dac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_dac_in>,<&CLK_hdmi_in>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DAC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DAC_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_emac1_tx: CLK_emac1_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC1_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC1_TX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac1_rx: CLK_emac1_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC1_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC1_RX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac1_tx_ref: CLK_emac1_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC1_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC1_TX_REF_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac1_rx_ref: CLK_emac1_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC1_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC1_RX_REF_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++ auto-enable = <1>; ++}; ++ ++CLK_pwm: CLK_pwm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_mpll_86m>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PWM_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++}; ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_armpll_37p125m>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_dec_gp>, <&CLK_bist_sc_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_dac>, <&CLK_dac_in>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_dec_aclk>, <&CLK_dec_bclk>, <&CLK_dec_cclk>, <&CLK_dec_pclk>, <&CLK_dip>, <&CLK_disp_216>, <&CLK_disp_432>, <&CLK_emac1_rx>, <&CLK_emac1_rx_ref>, <&CLK_emac1_tx>, <&CLK_emac1_tx_ref>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_ge>, <&CLK_hdmi>, <&CLK_hdmi_in>, <&CLK_hemcu_216m>, <&CLK_ir>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_c>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_lpll_clk_div2>, <&CLK_lpll_clk_div4>, <&CLK_lpll_clk_div8>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_mipi_tx_dsi>, <&CLK_mipi_tx_dsi_apb>, <&CLK_mipi_tx_dsi_p>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_dec_gp>, <&CLK_miu_dig>, <&CLK_miu_dma0>, <&CLK_miu_ff>, <&CLK_miu_miic0>, <&CLK_miu_miic1>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_urdma>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mop>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div32>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi>, <&CLK_mspi0>, <&CLK_mspi0_p>, <&CLK_mspi1>, <&CLK_mspi1_p>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_pwm>, <&CLK_pwr_ctl>, <&CLK_riu>, <&CLK_riu_dec_gp>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_w_clk_dec_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sata_axi>, <&CLK_sata_phy_108>, <&CLK_sata_phy_432>, <&CLK_sata_pm>, <&CLK_sc_pixel>, <&CLK_sc_pixel_p>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_uart2>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_utmi_480m>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>; ++ clock-count = <167>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity2m-clks_simple.dtsi b/arch/arm/boot/dts/infinity2m-clks_simple.dtsi +new file mode 100755 +index 000000000000..e4f75f7e8dd1 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-clks_simple.dtsi +@@ -0,0 +1,818 @@ ++/* generated manually for fast booting */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fcie_p: CLK_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_hdmi_in: CLK_hdmi_in { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_dac_in: CLK_dac_in { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++ auto-enable = <1>; ++}; ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <5>; //5+REG_CKG_MCU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_uart2: CLK_uart2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_UART2_OFFSET ++ mux-width = <2>; ++ gate-shift = <12>; //0+REG_CKG_UART2_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++ ++CLK_sata_phy_108: CLK_sata_phy_108 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SATA_PHY_108_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SATA_PHY_108_OFFSET ++}; ++ ++CLK_sata_phy_432: CLK_sata_phy_432 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SATA_PHY_432_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_SATA_PHY_432_OFFSET ++}; ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; //max safe clock is 320m ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++CLK_sata_pm: CLK_sata_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_xtali_12m>,<&CLK_xtali_24m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SATA_PM_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_SATA_PM_OFFSET ++}; ++ ++CLK_sata_axi: CLK_sata_axi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_288m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SATA_AXI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SATA_AXI_OFFSET ++}; ++CLK_dac: CLK_dac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_dac_in>,<&CLK_hdmi_in>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DAC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DAC_OFFSET ++}; ++ ++CLK_emac1_tx: CLK_emac1_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC1_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC1_TX_OFFSET ++}; ++ ++CLK_emac1_rx: CLK_emac1_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC1_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC1_RX_OFFSET ++}; ++ ++CLK_emac1_tx_ref: CLK_emac1_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC1_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC1_TX_REF_OFFSET ++}; ++ ++CLK_emac1_rx_ref: CLK_emac1_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC1_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC1_RX_REF_OFFSET ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++ auto-enable = <1>; ++}; ++ ++CLK_pwm: CLK_pwm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_mpll_86m>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PWM_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++}; ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_armpll_37p125m>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_dec_gp>, <&CLK_bist_sc_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_dac>, <&CLK_dac_in>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_dec_aclk>, <&CLK_dec_bclk>, <&CLK_dec_cclk>, <&CLK_dec_pclk>, <&CLK_dip>, <&CLK_disp_216>, <&CLK_disp_432>, <&CLK_emac1_rx>, <&CLK_emac1_rx_ref>, <&CLK_emac1_tx>, <&CLK_emac1_tx_ref>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_ge>, <&CLK_hdmi>, <&CLK_hdmi_in>, <&CLK_hemcu_216m>, <&CLK_ir>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_c>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_lpll_clk_div2>, <&CLK_lpll_clk_div4>, <&CLK_lpll_clk_div8>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_mipi_tx_dsi>, <&CLK_mipi_tx_dsi_apb>, <&CLK_mipi_tx_dsi_p>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_dec_gp>, <&CLK_miu_dig>, <&CLK_miu_dma0>, <&CLK_miu_ff>, <&CLK_miu_miic0>, <&CLK_miu_miic1>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_urdma>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mop>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div32>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi>, <&CLK_mspi0>, <&CLK_mspi0_p>, <&CLK_mspi1>, <&CLK_mspi1_p>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_pwm>, <&CLK_pwr_ctl>, <&CLK_riu>, <&CLK_riu_dec_gp>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_w_clk_dec_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sata_axi>, <&CLK_sata_phy_108>, <&CLK_sata_phy_432>, <&CLK_sata_pm>, <&CLK_sc_pixel>, <&CLK_sc_pixel_p>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_uart2>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_utmi_480m>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>; ++ clock-count = <167>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity2m-fpga.dts b/arch/arm/boot/dts/infinity2m-fpga.dts +new file mode 100755 +index 000000000000..a325bd466020 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-fpga.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity2m-fpga.dtsi" ++ ++/ { ++ model = "INFINITY2M FPGA"; ++ compatible = "sstar,infinity2m"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x6000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity2m-fpga.dtsi b/arch/arm/boot/dts/infinity2m-fpga.dtsi +new file mode 100755 +index 000000000000..64273cd55838 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-fpga.dtsi +@@ -0,0 +1,521 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity2m/irqs.h> ++#include <../../../../drivers/sstar/include/infinity2m/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++/* ++ venc{ ++ compatible = "sstar,venc"; ++ reg = <0x1F264800 0x100>, <0x1F264A00 0x100>, <0x1F264C00 0x100>, ++ <0x1F264E00 0x100>, <0x1F265000 0x100>, ++ <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; ++ reg-names = "mhe-0", "mhe-1", "mhe-2", "mfe-0", "mfe-1", "ven-0", "ven-1", "ven-2", "ven-3"; ++ interrupts = , ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq", "mfe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_miu_vhe>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_vhe_gp>; ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,sclhvsp1_i6"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , , , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "sstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "sstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++*/ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ hdmitx: hdmitx { ++ compatible = "sstar,hdmitx"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ ge: ge { ++ compatible = "sstar,ge"; ++ status = "ok"; ++ interrupts = ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++ // reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x00000000 0x000>; ++ pad = <0x1F203C38 0x0001 0x0001>; // pad selection from 0x0001 ++ phy-handle = <&phy0>; ++ max-speed = <10>; ++ mdio_path = <0>; // force internal mdio ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ // phy-mode = "rmii"; ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++/* ++ emac1: emac1 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++ reg = <0x1F2A2800 0x800>, <0x1F344200 0x600>, <0x00000000 0x000>; ++ pad = <0x1F203C38 0x0F00 0x0100>; // pad selection from 0x0100/0x0200/0x0300/0x0400/0x0500/0x0600/0x0700/0x0800/0x0900 ++ phy-handle = <&phy1>; ++ max-speed = <10>; ++ status = "ok"; ++ mdio-bus { ++ phy1: ethernet-phy@1 { ++ // phy-mode = "rmii"; ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++*/ ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "disabled"; ++ }; ++/* ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ }; ++*/ ++/* ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ status = "ok"; ++ }; ++ vif: vif { ++ compatible = "sigma,vif"; ++ status = "ok"; ++ reg = <0x1F263200 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F203C00 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>; ++ clocks = <&CLK_sr_mclk>; ++ interrupts = ; ++ // Config sensor 0 pad mux ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <2>; ++ // Config sensor 1 pad mux ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++*/ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sigma,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++/* ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "ok"; ++ }; ++*/ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ sound { ++ compatible = "sstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++ status = "ok"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++ status = "ok"; ++ }; ++ /* ++ gop{ ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ */ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <4>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&CLK_mcu>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++/* ++ Mstar-udc { ++ compatible = "sstar,infinity-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++*/ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ mmu { ++ compatible = "sstar,mmu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ dec { ++ compatible = "sstar,dec"; ++ banks = <0x1137>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity2m/reg_clks.h> ++ #include "infinity2m-clks.dtsi" ++ #include "infinity2m-gates.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity2m-gates.dtsi b/arch/arm/boot/dts/infinity2m-gates.dtsi +new file mode 100755 +index 000000000000..805936b3d522 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-gates.dtsi +@@ -0,0 +1,158 @@ ++GATE_MCM_vhe: GATE_MCM_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_mfe: GATE_MCM_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_jpe: GATE_MCM_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_aesdma: GATE_MCM_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_emac: GATE_MCM_emac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_gop: GATE_MCM_gop { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_bach: GATE_MCM_bach { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_usb: GATE_MCM_usb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++ ++GATE_MCM_fcie: GATE_MCM_fcie { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_sdio: GATE_MCM_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++/* ++GATE_MCM_urdma: GATE_MCM_urdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++*/ ++ ++GATE_SRAM_vhe: GATE_SRAM_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_mfe: GATE_SRAM_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <9>; ++}; ++ ++GATE_SRAM_jpe: GATE_SRAM_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_SRAM_aesdma: GATE_SRAM_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <1>; ++}; ++ ++GATE_SRAM_emac: GATE_SRAM_emac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <3>; ++}; ++ ++GATE_SRAM_gop: GATE_SRAM_gop { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <5>; ++}; ++ ++GATE_SRAM_bach: GATE_SRAM_bach { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_usb: GATE_SRAM_usb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <11>; ++}; ++ ++ ++GATE_SRAM_fcie: GATE_SRAM_fcie { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <4>; ++}; ++ ++GATE_SRAM_sdio: GATE_SRAM_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <10>; ++}; ++ ++ ++GATE_SRAM_mailbox: GATE_SRAM_mailbox { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <2>; ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-2Gb.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-2Gb.dts +new file mode 100755 +index 000000000000..5d5f756c9759 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-2Gb.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x0FE00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0xFE00000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-amp.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-amp.dts +new file mode 100755 +index 000000000000..2b828df5ac14 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-amp.dts +@@ -0,0 +1,54 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#define __DTS_DCDO__ ++ ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x05000000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x5000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000,mem=80m,maxcpus=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-display.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-display.dts +new file mode 100755 +index 000000000000..c2560df134fd +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a-display.dts +@@ -0,0 +1,53 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a-display.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux-display.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x7E00000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a.dts +new file mode 100755 +index 000000000000..3be2d34b8ec0 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc010a-s01a.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x7E00000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-display.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-display.dts +new file mode 100755 +index 000000000000..bf507e86190d +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-display.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a-display.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux-display.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x3E00000 mma_heap=mma_heap_name0,miu=0,sz=0x1000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-display_for_mipi.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-display_for_mipi.dts +new file mode 100755 +index 000000000000..7a3c5523d113 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-display_for_mipi.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a-display_for_mipi.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux-display_for_mipi.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x3E00000 mma_heap=mma_heap_name0,miu=0,sz=0x1000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-rgb565-rmii.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-rgb565-rmii.dts +new file mode 100755 +index 000000000000..da5745d77c99 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a-rgb565-rmii.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a-rgb565-rmii.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux-rgb565-rmii.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x3E00000 mma_heap=mma_heap_name0,miu=0,sz=0x1000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a.dts b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a.dts +new file mode 100755 +index 000000000000..d23ebc0fa949 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-spinand-ssc011a-s01a.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "ubi.mtd=9,2048 root=ubi:SYSTEM rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x3E00000 mma_heap=mma_heap_name0,miu=0,sz=0x1000000"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-2Gb.dts b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-2Gb.dts +new file mode 100755 +index 000000000000..cd00c8229403 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-2Gb.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x0FE00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench-padmux.dtsi b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench-padmux.dtsi +new file mode 100755 +index 000000000000..7a72e39a81cd +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench-padmux.dtsi +@@ -0,0 +1,121 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ //, // gpio: ehci power ++ , // gpio: gpioi2c_sda ++ , // gpio: gpioi2c_scl ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ , ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO ++ , ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ //, ++ ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ ; ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench.dts b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench.dts +new file mode 100755 +index 000000000000..56824b2bbf1f +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench.dts +@@ -0,0 +1,53 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a-bench.dtsi" ++#include "infinity2m-ssc010a-s01a-bench-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench.dtsi b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench.dtsi +new file mode 100755 +index 000000000000..bc90b093db51 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-bench.dtsi +@@ -0,0 +1,123 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++ ++/* ++ cpufreq { ++ vid-num = /bits/ 8 <2>; ++ vid-gpios = /bits/ 8 ; ++ }; ++*/ ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++/* ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++*/ ++ /* ++ * padmux: 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 3 -> PAD_FUART_CTS, PAD_FUART_RTS ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++// i2c-padmux = <4>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++/* ++ i2c-speed = <1>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; for hdmi: cannot be enabled ++ status = "ok"; ++ }; ++*/ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-3 { ++ compatible = "Sstar-ehci-3"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ dpdm_swap=<0>; ++ //power-enable-pad = ; ++ status = "ok"; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_hdmi>, <&CLK_dac>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_hdmi", "CLK_dac", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-display.dts b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-display.dts +new file mode 100755 +index 000000000000..b3a9dd4b807b +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-display.dts +@@ -0,0 +1,53 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a-display.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux-display.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-display.dtsi b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-display.dtsi +new file mode 100755 +index 000000000000..28ea9051541d +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-display.dtsi +@@ -0,0 +1,150 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++/* ++ cpufreq { ++ vid-num = /bits/ 8 <2>; ++ vid-gpios = /bits/ 8 ; ++ }; ++*/ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 3 -> PAD_FUART_CTS, PAD_FUART_RTS ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++ i2c-padmux = <5>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <1>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; for hdmi: cannot be enabled ++ status = "ok"; ++ goodix_gt911@5D{ ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ goodix_rst = ; ++ goodix_int = ; ++ interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_SD_D0>; ++ interrupt-names = "goodix_int"; ++ }; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-3 { ++ compatible = "Sstar-ehci-3"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ dpdm_swap=<0>; ++ //power-enable-pad = ; ++ status = "ok"; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_hdmi>, <&CLK_dac>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_hdmi", "CLK_dac", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) ++ // capture-dma-buffer=<122880>; //640(ms)*48(kHz)*2(ch)*2(16bits) ++ digmic-padmux = <1>; ++ i2s-padmux = <3>; ++ keep-i2s-clk = <0>; ++ status = "ok"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-padmux-display.dtsi b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-padmux-display.dtsi +new file mode 100755 +index 000000000000..b9114ff89be8 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-padmux-display.dtsi +@@ -0,0 +1,111 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ , ++ , ++ , ++ //, ++ //, ++ , ++ //, ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO ++ , ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ //, ++ , ++ , ++ //; ++ ++ // for ttl ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ ++ status = "ok"; // ok or disable ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a-padmux.dtsi b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-padmux.dtsi +new file mode 100755 +index 000000000000..d8fcc76f2629 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a-padmux.dtsi +@@ -0,0 +1,122 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ //, // gpio: ehci power ++ , // gpio: gpioi2c_sda ++ , // gpio: gpioi2c_scl ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ , ++ , ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ , ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO ++ , ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ //, ++ , ++ ; ++ /* ++ // for eth1 ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ */ ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a.dts b/arch/arm/boot/dts/infinity2m-ssc010a-s01a.dts +new file mode 100755 +index 000000000000..03d4952369bf +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a.dts +@@ -0,0 +1,53 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc010a-s01a.dtsi" ++#include "infinity2m-ssc010a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC010A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc010a-s01a.dtsi b/arch/arm/boot/dts/infinity2m-ssc010a-s01a.dtsi +new file mode 100755 +index 000000000000..7d77205626b1 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc010a-s01a.dtsi +@@ -0,0 +1,119 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++/* ++ cpufreq { ++ vid-num = /bits/ 8 <2>; ++ vid-gpios = /bits/ 8 ; ++ }; ++*/ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 3 -> PAD_FUART_CTS, PAD_FUART_RTS ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++ i2c-padmux = <4>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <1>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; for hdmi: cannot be enabled ++ status = "ok"; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-3 { ++ compatible = "Sstar-ehci-3"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ dpdm_swap=<0>; ++ //power-enable-pad = ; ++ status = "ok"; ++ }; ++#ifndef __DTS_DCDO__ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_hdmi>, <&CLK_dac>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_hdmi", "CLK_dac", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++#endif ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display.dts b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display.dts +new file mode 100755 +index 000000000000..9b639a8c6e77 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a-display.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux-display.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=4m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display.dtsi +new file mode 100755 +index 000000000000..2725531ec7dd +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display.dtsi +@@ -0,0 +1,153 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++ ++ cpufreq { ++ vid-num = /bits/ 8 <2>; ++ vid-gpios = /bits/ 8 ; ++ }; ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ }; ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ * 4 -> PAD_GPIO6, PAD_GPIO7 ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_GPIO2, PAD_GPIO3 ++ * 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ goodix_gt911@5D{ //EVB i2c-padmux=2 SSD201_SZ_DEMO_BOARD i2c-padmux=1 ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ goodix_rst = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO1 EVB PAD_GPIO0 ++ goodix_int = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO13 EVB PAD_GPIO1 ++ interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_GPIO13>; ++ interrupt-names = "goodix_int"; ++ }; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ scl-gpio = ; ++ sda-gpio = ; ++ status = "ok"; ++ }; ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) ++ // capture-dma-buffer=<122880>; //640(ms)*48(kHz)*2(ch)*2(16bits) ++ digmic-padmux = <2>; ++ i2s-padmux = <2>; ++ keep-i2s-clk = <0>; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ npwm = <2>; ++ pad-ctrl = ; ++ status = "ok"; // no available pads ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display_for_mipi.dts b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display_for_mipi.dts +new file mode 100755 +index 000000000000..caaa06b43616 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display_for_mipi.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a-display_for_mipi.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux-display_for_mipi.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=4m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display_for_mipi.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display_for_mipi.dtsi +new file mode 100755 +index 000000000000..794272f42558 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-display_for_mipi.dtsi +@@ -0,0 +1,149 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++ ++ cpufreq { ++ vid-num = /bits/ 8 <2>; ++ vid-gpios = /bits/ 8 ; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ * 4 -> PAD_GPIO6, PAD_GPIO7 ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_GPIO2, PAD_GPIO3 ++ * 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ goodix_gt911@5D{ //EVB i2c-padmux=2 SSD201_SZ_DEMO_BOARD i2c-padmux=1 ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ goodix_rst = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO1 EVB PAD_GPIO0 ++ goodix_int = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO13 EVB PAD_GPIO1 ++ interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_GPIO13>; ++ interrupt-names = "goodix_int"; ++ }; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ scl-gpio = ; ++ sda-gpio = ; ++ status = "ok"; ++ }; ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) ++ // capture-dma-buffer=<122880>; //640(ms)*48(kHz)*2(ch)*2(16bits) ++ digmic-padmux = <1>; ++ i2s-padmux = <2>; ++ keep-i2s-clk = <0>; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ npwm = <2>; ++ pad-ctrl = ; ++ status = "ok"; // no available pads ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display-doubleNet.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display-doubleNet.dtsi +new file mode 100755 +index 000000000000..440883e6dc2b +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display-doubleNet.dtsi +@@ -0,0 +1,124 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default non-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO, ++ //, // sar: default not-GPIO ++ //, // sar: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ , ++ , ++ ; ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display.dtsi +new file mode 100755 +index 000000000000..10951e7f4ebb +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display.dtsi +@@ -0,0 +1,124 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default non-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO, ++ //, // sar: default not-GPIO ++ //, // sar: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ , ++ , ++ ; ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display_for_mipi.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display_for_mipi.dtsi +new file mode 100755 +index 000000000000..68e656f35742 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-display_for_mipi.dtsi +@@ -0,0 +1,106 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default non-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO, ++ //, // sar: default not-GPIO ++ //, // sar: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ , ++ , ++ ; ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-rgb565-rmii.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-rgb565-rmii.dtsi +new file mode 100755 +index 000000000000..9037d0a22cc9 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-rgb565-rmii.dtsi +@@ -0,0 +1,126 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ , ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ , ++ //, ++ , ++ //, ++ //, ++ //, ++ , ++ //, ++ //, ++ , // IR: default non-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO, ++ //, // sar: default not-GPIO ++ //, // sar: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ //, ++ , ++ ; ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux.dtsi +new file mode 100755 +index 000000000000..4738a3f1c646 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux.dtsi +@@ -0,0 +1,124 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity2m/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ , ++ //, ++ , ++ //, ++ , ++ , ++ , ++ //, ++ , ++ , ++ , // IR: default non-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, // default not-GPIO ++ //, ++ //, ++ , // sar: default not-GPIO, ++ //, // sar: default not-GPIO ++ //, // sar: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ //, // ETH: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ , // utmi: default not-GPIO ++ //, ++ //, ++ , ++ , ++ //, ++ , ++ ; ++ //; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-rgb565-rmii.dts b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-rgb565-rmii.dts +new file mode 100755 +index 000000000000..6add240ac037 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-rgb565-rmii.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a-rgb565-rmii.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux-rgb565-rmii.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=4m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a-rgb565-rmii.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-rgb565-rmii.dtsi +new file mode 100755 +index 000000000000..8fc46a83498c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a-rgb565-rmii.dtsi +@@ -0,0 +1,120 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++ core_voltage { ++ //vid_gpios = ; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <0>; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ * 4 -> PAD_GPIO6, PAD_GPIO7 ++ */ ++ i2c-padmux = <4>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_GPIO2, PAD_GPIO3 ++ * 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++ i2c-padmux = <2>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ goodix_gt911@5D{ //EVB i2c-padmux=2 SSD201_SZ_DEMO_BOARD i2c-padmux=1 ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ goodix_rst = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO1 EVB PAD_GPIO0 ++ goodix_int = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO13 EVB PAD_GPIO1 ++ interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_GPIO13>; ++ interrupt-names = "goodix_int"; ++ }; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ scl-gpio = ; ++ sda-gpio = ; ++ status = "ok"; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a.dts b/arch/arm/boot/dts/infinity2m-ssc011a-s01a.dts +new file mode 100755 +index 000000000000..2ad3f8381b38 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a.dts +@@ -0,0 +1,52 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/dts-v1/; ++#include "infinity2m.dtsi" ++#include "infinity2m-ssc011a-s01a.dtsi" ++#include "infinity2m-ssc011a-s01a-padmux.dtsi" ++ ++/ { ++ model = "INFINITY2M SSC011A-S01A-S"; ++ compatible = "sstar,infinity2m"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x03E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=4m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m-ssc011a-s01a.dtsi b/arch/arm/boot/dts/infinity2m-ssc011a-s01a.dtsi +new file mode 100755 +index 000000000000..46f0b35452b1 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m-ssc011a-s01a.dtsi +@@ -0,0 +1,114 @@ ++/* ++* infinity2m-scc010a-s01a-s.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/ { ++ soc { ++ core_voltage { ++ vid_gpios = ; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ /* ++ * padmux: 1 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 2 -> PAD_TTL1, PAD_TTL2 ++ * 3 -> PAD_TTL14, PAD_TTL15 ++ * 4 -> PAD_GPIO6, PAD_GPIO7 ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_GPIO2, PAD_GPIO3 ++ * 2 -> PAD_HDMITX_SCL, PAD_HDMITX_SDA ++ * 4 -> PAD_TTL22, PAD_TTL23 ++ * 5 -> PAD_SD_CLK, PAD_SD_CMD ++ */ ++ i2c-padmux = <1>; ++ /* ++ * speed: 0 -> HWI2C_HIGH(high speed: 400 KHz) ++ * 1 -> HWI2C_NORMAL(normal speed: 300 KHz) ++ * 2 -> HWI2C_SLOW(slow speed: 200 KHz) ++ * 3 -> HWI2C_VSLOW(very slow: 100 KHz) ++ * 4 -> HWI2C_USLOW(ultra slow: 50 KHz) ++ * 5 -> HWI2C_UVSLOW(ultra-very slow: 25 KHz) ++ */ ++ i2c-speed = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ status = "ok"; ++ goodix_gt911@5D{ //EVB i2c-padmux=2 SSD201_SZ_DEMO_BOARD i2c-padmux=1 ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ goodix_rst = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO1 EVB PAD_GPIO0 ++ goodix_int = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO13 EVB PAD_GPIO1 ++ interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_GPIO13>; ++ interrupt-names = "goodix_int"; ++ }; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ scl-gpio = ; ++ sda-gpio = ; ++ status = "ok"; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , ; ++ clocks = <&CLK_mop>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_mop", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity2m.dtsi b/arch/arm/boot/dts/infinity2m.dtsi +new file mode 100755 +index 000000000000..cb0793d66384 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity2m.dtsi +@@ -0,0 +1,696 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity2m/irqs.h> ++#include <../../../../drivers/sstar/include/infinity2m/gpio.h> ++#include <../../../../drivers/sstar/include/vcore_defs.h> ++#include ++#include ++#include "skeleton.dtsi" ++#include <../../../../include/generated/autoconf.h> ++#ifdef CONFIG_CAM_CLK ++#include <../../../../drivers/sstar/include/infinity2m/camclk.h> ++#endif ++ ++/ { ++ camclk: camclkinit { ++ compatible = "camdriver,camclkinit"; ++ status = "ok"; ++ }; ++ camclk { ++ compatible = "camdriver,camclk"; ++ status = "ok"; ++ }; ++ camclkut { ++ compatible = "camdriver,camclkut"; ++ status = "ok"; ++ }; ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clock-frequency = <1000000000>; ++ clocks = <&CLK_cpupll_clk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x0>; ++ operating-points = < ++ /* kHz uV */ ++ /* ++ 1200000 1000000 ++ 1100000 1000000 ++ */ ++ 1000000 900000 ++ /* ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ */ ++ >; ++ }; ++#ifndef __DTS_DCDO__ ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clock-frequency = <1000000000>; ++ clocks = <&CLK_cpupll_clk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1>; ++ operating-points = < ++ /* kHz uV */ ++ /* ++ 1200000 1000000 ++ 1100000 1000000 ++ */ ++ 1000000 900000 ++ /* ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ */ ++ >; ++ }; ++#endif ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ serial3 = &uart2; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ always-on; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clocksource","sstar,piu-clockevent"; ++#ifdef CONFIG_CAM_CLK ++ camclk = <>; ++#endif ++ reg = <0x1F006040 0x100>; ++ interrupts=<&ms_main_intc GIC_SPI INT_FIQ_TIMER_0 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++*/ ++#ifndef __DTS_DCDO__ ++ dec: dec { ++ compatible = "sstar,dec"; ++ banks = <0x1137>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ clocks = <&CLK_hdmi>, <&CLK_dac>, <&CLK_sc_pixel>, <&CLK_mipi_tx_dsi>, <&CLK_mipi_tx_dsi_apb>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_hdmi", "CLK_dac", "CLK_sc_pixel", "CLK_mipi_tx_dsi", "CLK_mipi_tx_dsi_apb"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ hdmitx: hdmitx { ++ compatible = "sstar,hdmitx"; ++ status = "ok"; ++ i2c_id = <0>; ++ hpd_gpio = <89>; ++ i2c_sw = <1>; ++ i2c_sda_gpio = <88>; ++ i2c_scl_gpio = <87>; ++ clocks = <&CLK_hdmi>, <&CLK_disp_432>, <&CLK_disp_216>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_hdmi", "CLK_disp_432", "CLK_disp_216"; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ ge: ge { ++ compatible = "sstar,ge"; ++ status = "ok"; ++ clocks = <&CLK_ge>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ gop: gop { ++ compatible = "sstar,gop"; ++ status = "ok"; ++ ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ clocks = <&CLK_dip>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++#endif ++ uart0: uart0@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++ dma = <1>; ++ tolerance = <2>; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ uart2: uart2@1F221400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221400 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart2>; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; ++ pad = <0x1F203C38 0x0001 0x0000>; // pad selection from 0x0001 ++ phy-handle = <&phy0>; ++ status = "ok"; ++ mdio-bus@emac0 { ++ phy0: ethernet-phy@0 { ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ emac1: emac1 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac1_tx>,<&CLK_emac1_rx>,<&CLK_emac1_tx_ref>,<&CLK_emac1_rx_ref>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1F2A2800 0x800>, <0x1F344200 0x600>, <0x00000000 0x000>; ++ pad = <0x1F203C38 0x0F00 0x0300>; // pad selection from 0x0100/0x0200/0x0300/0x0400/0x0500/0x0600/0x0700/0x0800/0x0900 ++ status = "ok"; ++#if 1 ++ phy-handle = <&phy1>; ++ mdio-bus@emac1 { ++ phy1: ethernet-phy@1 { ++ phy-mode = "rmii"; ++ }; ++ }; ++#else ++ phy-mode = "rmii"; ++ fixed-link = <0 1 100 0 0>; ++#endif ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>,<0x100B>; ++ clocks = <&CLK_mspi0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ /* ++ * padmux: ++ * mode=1: PAD_PM_SD_CDZ,PAD_SD_D1,PAD_SD_D0,PAD_SD_CLK,PAD_SD_CMD ++ * mode=2: PAD_TTL16,PAD_TTL17,PAD_TTL18,PAD_TTL19 ++ * mode=3: PAD_GPIO4,PAD_GPIO5,PAD_GPIO6,PAD_GPIO7 ++ * mode=4: PAD_FUART_RX,PAD_FUART_TX,PAD_FUART_CTS,PAD_FUART_RTS ++ * mode=5: PAD_GPIO8,PAD_GPIO9,PAD_GPIO10,PAD_GPIO11 ++ * mode=6: PAD_GPIO0,PAD_GPIO1,PAD_GPIO2,PAD_GPIO3 ++ */ ++ dma = <1>; ++ spi0_mode = <2>; ++ status = "ok"; ++ }; ++ ++ spidev: spidev { ++ compatible = "spidev"; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ dpdm_swap=<0>; ++ //power-enable-pad = ; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ dpdm_swap=<0>; ++ //power-enable-pad = ; ++ status = "ok"; ++ }; ++ ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) ++ // capture-dma-buffer=<122880>; //640(ms)*48(kHz)*2(ch)*2(16bits) ++ digmic-padmux = <1>; ++ i2s-padmux = <3>; ++ keep-i2s-clk = <0>; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks =<&CLK_sdio>, <&CLK_sdio>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ bus-width = <4>; ++ max-clks = <2>; // 0:48M 1:43M 2:40M 3:36M 4:32M 5:20M 6:12M 7:300K ++ clk-driving = <0>; ++ cmd-driving = <0>; ++ data-driving = <0>; ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <1>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; // 0:IP_SDIO ++ slot-pad-orders = <0>,<1>,<2>; // 0:PAD_SD 1:PAD_GPIO ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-cdzs-gpios = ,<0>,<0>; ++ slot-pwr-gpios = ,<0>,<0>; // ssc010a:PAD_TTL0 P2_ssc011a: PAD_GPIO0 ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ ++ interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, // No need to change. ++ <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, // No need to change. ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>, // CDZ int for Slot 0, default is for PAD_PM_SD_CDZ ++ <&ms_gpi_intc 42>, // CDZ int for Slot 1, None. ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>; // CDZ int for Slot 2, None. ++ interrupt-names = "mie0_irq", "mie1_irq", "cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"; // No need to change. ++ clocks = <&CLK_sdio>,<&CLK_VOID>,<&CLK_VOID>; // No need to change. ++ ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ //clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; ++ clocks = <&CLK_aesdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ sata { ++ compatible = "sstar,sata", "sstar,sata-ahci"; ++ reg-names = "ahci", "ahci_port0", "ahci_misc"; ++ reg = <0x1F345000 0x100>, <0x1F345100 0x100>, <0x1F2A4A00 0x200>; ++ interrupts=; ++ clocks = <&CLK_sata_axi>,<&CLK_sata_pm>,<&CLK_sata_phy_108>,<&CLK_sata_phy_432>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ phy_mode = <2>; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ rtcpwc { ++ compatible = "sstar,infinity-rtcpwc"; ++ reg = <0x1F006800 0x200>; ++ interrupts=; //need to check ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ status = "ok"; ++ }; ++ ++ core_voltage { ++ vid_width = <2>; ++ vid_gpios = ; ++ vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 ++ }; ++/* ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <950 1000>; //2b'00 2b'01 ++ }; ++*/ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "ok"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ clocks = <&CLK_sar>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ ircut { ++ compatible = "sstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ ir: ir@1F007A00 { ++ compatible = "sstar,infinity-ir"; ++ reg = <0x1F007A00 0x1000>; ++ clocks = <&CLK_ir>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ npwm = <4>; ++ pad-ctrl = ; ++ status = "disabled"; // no available pads ++ }; ++ ++ /* ++ pm { ++ compatible = "sstar,infinity-pm"; ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ detect-gpio = ; ++ }; ++ */ ++ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ mmu { ++ compatible = "sstar,mmu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity2m/reg_clks.h> ++#ifndef __DTS_DCDO__ ++ #include "infinity2m-clks.dtsi" ++#else ++ #include "infinity2m-clks_simple.dtsi" ++#endif ++/* #include "infinity2m-gates.dtsi"*/ ++}; ++ +diff --git a/arch/arm/boot/dts/infinity3-BGA128M.dts b/arch/arm/boot/dts/infinity3-BGA128M.dts +new file mode 100755 +index 000000000000..aa394b5a213e +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-BGA128M.dts +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S01A"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++/* ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ ++ }; ++ ++ soc{ ++ //Mstar-ehci-1 { ++ // dpdm_swap=<1>; ++ //}; ++ ++ //Mstar-ehci-2 { ++ // dpdm_swap=<1>; ++ //}; ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-BGA256M.dts b/arch/arm/boot/dts/infinity3-BGA256M.dts +new file mode 100755 +index 000000000000..c64495883a34 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-BGA256M.dts +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S01A-256M"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x9000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-EXT256M.dts b/arch/arm/boot/dts/infinity3-EXT256M.dts +new file mode 100755 +index 000000000000..00e7b8ad9984 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-EXT256M.dts +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S02A-256M"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x9000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-EXT512M.dts b/arch/arm/boot/dts/infinity3-EXT512M.dts +new file mode 100755 +index 000000000000..befd5a1edfe2 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-EXT512M.dts +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S02A-512M"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++ temp0:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x30000000 0x10000000>; ++ bank-width = <1>; ++ erase-size = <0x10000>; ++ linux,mtd-name = "temp0"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x7000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN128M.dts b/arch/arm/boot/dts/infinity3-QFN128M.dts +new file mode 100755 +index 000000000000..c3f55efde8b8 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN128M.dts +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S04A"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x2>; //enable DNR and disable ROT ++ isp-res = <0x5>; //max image size 4M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN128MDC.dts b/arch/arm/boot/dts/infinity3-QFN128MDC.dts +new file mode 100755 +index 000000000000..d8040cc5ce77 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN128MDC.dts +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S04A"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN64M.dts b/arch/arm/boot/dts/infinity3-QFN64M.dts +new file mode 100755 +index 000000000000..f91093f3be0b +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN64M.dts +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S03A-64M"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@23F00000 { ++ reg = <0x23F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01C00000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x0>; //Disable DNR and ROT ++ isp-res = <0x1>; //max image size 2M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ vip: vip { ++ CMDQ-mode = <0>; ++ }; ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN64MC.dts b/arch/arm/boot/dts/infinity3-QFN64MC.dts +new file mode 100755 +index 000000000000..ba8ce58d80f6 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN64MC.dts +@@ -0,0 +1,72 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S03A-64M C313"; ++ compatible = "sstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@23F00000 { ++ reg = <0x23F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01C00000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; ++ clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0>; //disable DNR and ROT ++ isp-res = <1>; //max image size 2M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ vip: vip { ++ CMDQ-mode = <0>; ++ }; ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-clks.dtsi b/arch/arm/boot/dts/infinity3-clks.dtsi +new file mode 100755 +index 000000000000..16db1266ca23 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-clks.dtsi +@@ -0,0 +1,1519 @@ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172000000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123000000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86000000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_pm>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_isp_p: CLK_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_isp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk2_p: CLK_fclk2_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fcie_p: CLK_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fcie>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp: CLK_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe: CLK_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfeh: CLK_miu_mfeh { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfe: CLK_miu_mfe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe1: CLK_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe0: CLK_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bach: CLK_miu_bach { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_file: CLK_miu_file { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_uhc0: CLK_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_emac: CLK_miu_emac { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_cmdq: CLK_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dnr: CLK_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_rot: CLK_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dma: CLK_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_sta: CLK_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_gop: CLK_miu_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr: CLK_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_crop: CLK_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_frm: CLK_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snp: CLK_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snpi: CLK_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_dbg: CLK_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_frm: CLK_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_snpi: CLK_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc3_frm: CLK_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_fcie: CLK_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sdio: CLK_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_ive: CLK_miu_ive { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_nogating: CLK_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_vhe_gp: CLK_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck: CLK_tck { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_tck_buf>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop0: CLK_gop0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop1: CLK_gop1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop2: CLK_gop2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_xtali_24m>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_csi_mac>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr_mclk: CLK_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_mpll_288m_div8>,<&CLK_mpll_216m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_123m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_bist_pm: CLK_bist_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_utmi_160m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++}; ++ ++CLK_mfe: CLK_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_172m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_fcie: CLK_fcie { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_mpll_86m_div16>,<&CLK_xtali_12m_div40>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCIE_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_FCIE_OFFSET ++}; ++ ++CLK_ecc: CLK_ecc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET ++}; ++ ++CLK_sr: CLK_sr { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_pad2isp_sr_pclk>,<&CLK_csi2_mac_p>,<&CLK_utmi_160m_div4>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SR_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SR_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_mpll_288m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++}; ++ ++CLK_idclk: CLK_idclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_isp_p>,<&CLK_ccir_in_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_IDCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_IDCLK_OFFSET ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++}; ++ ++CLK_fclk2: CLK_fclk2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++}; ++ ++CLK_ive: CLK_ive { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_IVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_IVE_OFFSET ++}; ++ ++CLK_nlm: CLK_nlm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++}; ++ ++CLK_csi_mac: CLK_csi_mac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET ++}; ++ ++CLK_mac_lptx: CLK_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET ++}; ++ ++CLK_ns: CLK_ns { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_NS_OFFSET ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET ++ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++ auto-enable = <1>; ++}; ++ ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_pm>, <&CLK_bist_sc_gp>, <&CLK_bist_vhe_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_csi_mac>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_ecc>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie>, <&CLK_fcie_p>, <&CLK_fclk1>, <&CLK_fclk1_p>, <&CLK_fclk2>, <&CLK_fclk2_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_gop0>, <&CLK_gop1>, <&CLK_gop2>, <&CLK_hemcu_216m>, <&CLK_idclk>, <&CLK_imi>, <&CLK_ir>, <&CLK_isp>, <&CLK_isp_p>, <&CLK_ive>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_mac_lptx>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_mfe>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_bach>, <&CLK_miu_bdma>, <&CLK_miu_cmdq>, <&CLK_miu_dig>, <&CLK_miu_emac>, <&CLK_miu_fcie>, <&CLK_miu_ff>, <&CLK_miu_file>, <&CLK_miu_gop>, <&CLK_miu_isp_dma>, <&CLK_miu_isp_dnr>, <&CLK_miu_isp_rot>, <&CLK_miu_isp_sta>, <&CLK_miu_ive>, <&CLK_miu_jpe0>, <&CLK_miu_jpe1>, <&CLK_miu_mfe>, <&CLK_miu_mfeh>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc1_dbg>, <&CLK_miu_sc1_frm>, <&CLK_miu_sc1_snp>, <&CLK_miu_sc1_snpi>, <&CLK_miu_sc2_frm>, <&CLK_miu_sc2_snpi>, <&CLK_miu_sc3_frm>, <&CLK_miu_sc_crop>, <&CLK_miu_sc_dnr>, <&CLK_miu_sc_dnr_sad>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_sdio>, <&CLK_miu_uhc0>, <&CLK_miu_urdma>, <&CLK_miu_vhe>, <&CLK_miu_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi0>, <&CLK_mspi1>, <&CLK_nlm>, <&CLK_ns>, <&CLK_odclk>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_riu>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_sr>, <&CLK_sr_mclk>, <&CLK_tck>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_vhe>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>; ++ clock-count = <179>; ++}; ++ +diff --git a/arch/arm/boot/dts/infinity3-fpga.dts b/arch/arm/boot/dts/infinity3-fpga.dts +new file mode 100755 +index 000000000000..2493a6637574 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpga.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity3-fpga.dtsi" ++ ++/ { ++ model = "INFINITY3 FPGA"; ++ compatible = "sstar,infinity3"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-fpga.dtsi b/arch/arm/boot/dts/infinity3-fpga.dtsi +new file mode 100755 +index 000000000000..8d22d7fe9ec7 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpga.dtsi +@@ -0,0 +1,306 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity3/irqs.h> ++#include <../../../../drivers/sstar/include/infinity3/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "sstar,mfe"; ++ reg = <0x1F264800 0x400>; ++ interrupts=; ++ clocks = <&xtal>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "sstar,vhe"; ++ reg = <0x1F265200 0x600>,<0x1F265000 0x200>; ++ interrupts=; ++ clocks = <&xtal>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "sstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "sstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ ++ ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ status = "ok"; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "disabled"; ++ }; ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ sound { ++ compatible = "sstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ ++ gop{ ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ ++ ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity3/reg_clks.h> ++ #include "infinity3-clks.dtsi" ++ #include "infinity3-gates.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity3-fpgaxl.dts b/arch/arm/boot/dts/infinity3-fpgaxl.dts +new file mode 100755 +index 000000000000..5625063fd254 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpgaxl.dts +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3-fpgaxl.dtsi" ++ ++/ { ++ model = "INFINITY3 FPGA"; ++ compatible = "sstar,infinity3"; ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x03000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity3-fpgaxl.dtsi b/arch/arm/boot/dts/infinity3-fpgaxl.dtsi +new file mode 100755 +index 000000000000..4dd2a5fcff65 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpgaxl.dtsi +@@ -0,0 +1,428 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity3/irqs.h> ++#include <../../../../drivers/sstar/include/infinity3/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <27000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_pmsleep_intr: interrupt-controller@0 { ++ compatible = "sstar,pmsleep-intr"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <27000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "sstar,mfe"; ++ reg = <0x1F264800 0x200>; ++ interrupts=; ++ clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "sstar,vhe"; ++ reg = <0x1F265200 0x200>,<0x1F265000 0x100>; ++ interrupts=; ++ clocks = <&CLK_vhe>,<&GATE_MCM_vhe>, <&GATE_SRAM_vhe>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "sstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "sstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ status = "ok"; ++ }; ++ uart1: uart@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ status = "disabled"; ++ }; ++ fuart: uart@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&xtal>; ++ dma = <1>; ++ status = "disabled"; ++ }; ++ ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>,<&GATE_MCM_emac>, <&GATE_SRAM_emac>; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ nandflash { ++ compatible = "ms-nand"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++ status = "disabled"; ++ }; ++ ++ Mstar-ehci-1 { ++ compatible = "Mstar-ehci-1"; ++ clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ }; ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ status = "disabled"; ++ }; ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ i2c0: i2c@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ i2c-speed = <2>;//0~6 ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ i2c-speed = <2>;//0~6 ++ status = "disabled"; ++ 24c512@54 { ++ compatible = "sstar,24c512"; ++ reg = <0x54>; ++ }; ++ }; ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "sstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ clocks = <&CLK_utmi>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ interrupts=, ++ , ++ , ++ ; ++ //,,.... fice1->fice2->fice3 setting ++ clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>; ++ status = "disabled"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; ++ }; ++ ++ gop{ ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ status = "disabled"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "disabled"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "disabled"; ++ }; ++ ++ ircut { ++ compatible = "sstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ status = "disabled"; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "disabled"; ++ }; ++ ++ pm { ++ compatible = "sstar,infinity-pm"; ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ detect-gpio = ; ++ status = "disabled"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity3/reg_clks.h> ++ #include "infinity3-clks.dtsi" ++ #include "infinity3-gates.dtsi" ++}; +diff --git a/arch/arm/boot/dts/infinity3-gates.dtsi b/arch/arm/boot/dts/infinity3-gates.dtsi +new file mode 100755 +index 000000000000..805936b3d522 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-gates.dtsi +@@ -0,0 +1,158 @@ ++GATE_MCM_vhe: GATE_MCM_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_mfe: GATE_MCM_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_jpe: GATE_MCM_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_aesdma: GATE_MCM_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_emac: GATE_MCM_emac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_gop: GATE_MCM_gop { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_bach: GATE_MCM_bach { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_usb: GATE_MCM_usb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++ ++GATE_MCM_fcie: GATE_MCM_fcie { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_sdio: GATE_MCM_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++/* ++GATE_MCM_urdma: GATE_MCM_urdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++*/ ++ ++GATE_SRAM_vhe: GATE_SRAM_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_mfe: GATE_SRAM_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <9>; ++}; ++ ++GATE_SRAM_jpe: GATE_SRAM_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_SRAM_aesdma: GATE_SRAM_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <1>; ++}; ++ ++GATE_SRAM_emac: GATE_SRAM_emac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <3>; ++}; ++ ++GATE_SRAM_gop: GATE_SRAM_gop { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <5>; ++}; ++ ++GATE_SRAM_bach: GATE_SRAM_bach { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_usb: GATE_SRAM_usb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <11>; ++}; ++ ++ ++GATE_SRAM_fcie: GATE_SRAM_fcie { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <4>; ++}; ++ ++GATE_SRAM_sdio: GATE_SRAM_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <10>; ++}; ++ ++ ++GATE_SRAM_mailbox: GATE_SRAM_mailbox { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <2>; ++}; +diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi +new file mode 100755 +index 000000000000..c7f6176a5160 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3.dtsi +@@ -0,0 +1,515 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity3/irqs.h> ++#include <../../../../drivers/sstar/include/infinity3/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&CLK_cpupll_clk>; ++ }; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ }; ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "sstar,mfe"; ++ reg = <0x1F264800 0x200>; ++ interrupts=; ++ clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "sstar,vhe"; ++ reg = <0x1F265200 0x200>,<0x1F265000 0x100>; ++ interrupts=; ++ clocks = <&CLK_vhe>,<&GATE_MCM_vhe>, <&GATE_SRAM_vhe>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ DigitalZoom-Dropmode = <1>; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "sstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "sstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ttl-mode = <1>; ++ jtag-mode = <0>; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart0@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++ status = "ok"; ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++ dma = <1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++ //led-orange = ; //software toggle GPIO LED For QFN ++ //led-green = ; //software toggle GPIO LED For QFN ++ status = "ok"; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ nandflash { ++ compatible = "ms-nand"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++ status = "ok"; ++ }; ++ ++ Mstar-ehci-1 { ++ compatible = "Mstar-ehci-1"; ++ clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ dpdm_swap=<0>; ++ power-enable-pad = ; //PAD_SPI0_CK ++ status = "ok"; ++ }; ++ ++ Mstar-ehci-2 { ++ compatible = "Mstar-ehci-2"; ++ clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Mstar-udc { ++ compatible = "Mstar-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ clk-pad = ; ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ //isp-flag = <0>; ++ }; ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ spi0_mode = <1>; ++ spi1_mode = <1>; ++ status = "disabled"; ++ }; ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>,<&GATE_MCM_jpe>, <&GATE_SRAM_jpe>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "sstar,infinity3-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>; ++ // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) ++ // capture-dma-buffer=<122880>; //640(ms)*48(kHz)*2(ch)*2(16bits) ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <1>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-pwr-gpios = <19>,<0>,<0>; ++ ++ clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>; ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++ status = "ok"; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++// vid0-gpio = ; ++ vid1-gpio = ; ++ status = "ok"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "ok"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "ok"; ++ }; ++ ++ ircut { ++ compatible = "sstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity3-pwm"; ++ reg = <0x1F003400 0x400>; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <8>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ /* ++ pm { ++ compatible = "sstar,infinity-pm"; ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ detect-gpio = ; ++ }; ++ */ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity3/reg_clks.h> ++ #include "infinity3-clks.dtsi" ++ #include "infinity3-gates.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity5-BGA128M.dts b/arch/arm/boot/dts/infinity5-BGA128M.dts +new file mode 100755 +index 000000000000..80c91d723772 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-BGA128M.dts +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity5.dtsi" ++ ++/ { ++ model = "INFINITY5 SSC007A-S01A"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5-alkaid.dts b/arch/arm/boot/dts/infinity5-alkaid.dts +new file mode 100644 +index 000000000000..48e79e3820cf +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-alkaid.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity5-fpga.dtsi" ++ ++/ { ++ model = "INFINITY5 FPGA"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x6000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5-clks.dtsi b/arch/arm/boot/dts/infinity5-clks.dtsi +new file mode 100644 +index 000000000000..96dcd54738f9 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-clks.dtsi +@@ -0,0 +1,1750 @@ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172000000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123000000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86000000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_pm>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_isp_p: CLK_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_isp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk2_p: CLK_fclk2_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fcie_p: CLK_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fcie>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp: CLK_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe: CLK_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe1: CLK_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe0: CLK_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bach: CLK_miu_bach { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_file: CLK_miu_file { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_uhc0: CLK_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_emac: CLK_miu_emac { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_cmdq: CLK_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dnr: CLK_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_rot: CLK_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dma: CLK_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_sta: CLK_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_gop: CLK_miu_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr: CLK_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_crop: CLK_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_frm: CLK_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snp: CLK_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snpi: CLK_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_dbg: CLK_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_frm: CLK_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_snpi: CLK_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc3_frm: CLK_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_fcie: CLK_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sdio: CLK_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_ive: CLK_miu_ive { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_nogating: CLK_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_vhe_gp: CLK_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck: CLK_tck { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_tck_buf>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop0: CLK_gop0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop1: CLK_gop1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop2: CLK_gop2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_lpll_clk_div2: CLK_lpll_clk_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div4: CLK_lpll_clk_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div8: CLK_lpll_clk_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_ipupll_clk: CLK_ipupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_venpll_clk: CLK_venpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_csi_mac>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <4>; //4+EG_CKG_BDMA_OFFSET ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr_mclk: CLK_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_clk_div2>,<&CLK_lpll_clk_div4>,<&CLK_lpll_clk_div8>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <4>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_sr_mclk1: CLK_sr_mclk1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_clk_div2>,<&CLK_lpll_clk_div4>,<&CLK_lpll_clk_div8>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <4>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_bist_pm: CLK_bist_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET ++}; ++ ++CLK_pwr_ctl: CLK_pwr_ctl { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_PWR_CTL_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_PWR_CTL_OFFSET ++}; ++ ++CLK_ipu: CLK_ipu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_ipupll_clk>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_123m>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_IPU_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_IPU_OFFSET ++}; ++ ++CLK_bist_ipu_gp: CLK_bist_ipu_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_BIST_IPU_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <12>; //0+REG_CKG_BIST_IPU_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miic2: CLK_miic2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC2_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_MIIC2_OFFSET ++}; ++ ++CLK_miic3: CLK_miic3 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC3_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_MIIC3_OFFSET ++}; ++ ++CLK_csi_mac_lptx_top_i_0: CLK_csi_mac_lptx_top_i_0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_LPTX_TOP0_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_LPTX_TOP0_OFFSET ++}; ++ ++CLK_csi_mac_top_i_0: CLK_csi_mac_top_i_0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_CSI_MAC_TOP0_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_CSI_MAC_TOP0_OFFSET ++}; ++ ++CLK_csi_ns_top_i_0: CLK_csi_ns_top_i_0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_TOP0_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_NS_TOP0_OFFSET ++}; ++ ++CLK_csi_mac_lptx_top_i_1: CLK_csi_mac_lptx_top_i_1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_CSI_MAC_LPTX_TOP1_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_CSI_MAC_LPTX_TOP1_OFFSET ++}; ++ ++CLK_csi_mac_top_i_1: CLK_csi_mac_top_i_1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_TOP1_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_TOP1_OFFSET ++}; ++ ++CLK_csi_ns_top_i_1: CLK_csi_ns_top_i_1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NS_TOP1OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_NS_TOP1_OFFSET ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_venpll_clk>,<&CLK_mpll_432m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_384m>,<&CLK_mpll_288m>,<&CLK_utmi_192m>,<&CLK_mpll_216m_div8>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_fcie: CLK_fcie { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_mpll_86m_div16>,<&CLK_xtali_12m_div40>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCIE_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_FCIE_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <6>; //6+REG_CKG_FCIE_OFFSET ++}; ++ ++CLK_ecc: CLK_ecc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET ++}; ++ ++CLK_sr: CLK_sr { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_pad2isp_sr_pclk>,<&CLK_csi2_mac_p>,<&CLK_utmi_160m_div4>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SR_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SR_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_144m>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <4>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++}; ++ ++CLK_idclk: CLK_idclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_isp_p>,<&CLK_ccir_in_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_IDCLK_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_IDCLK_OFFSET ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_upll_320m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_fclk2: CLK_fclk2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_upll_320m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++}; ++ ++CLK_ive: CLK_ive { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_IVE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_IVE_OFFSET ++}; ++ ++CLK_dip: CLK_dip { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DIP_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_DIP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++}; ++ ++CLK_csi_mac: CLK_csi_mac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET ++}; ++ ++CLK_mac_lptx: CLK_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET ++}; ++ ++CLK_ns: CLK_ns { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_NS_OFFSET ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET ++ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET ++ glitch-shift = <15>; //7+REG_CKG_SPI_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++ auto-enable = <1>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++ auto-enable = <1>; ++}; ++ ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_ipu_gp>, <&CLK_bist_pm>, <&CLK_bist_sc_gp>, <&CLK_bist_vhe_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_csi_mac>, <&CLK_csi_mac_lptx_top_i_0>, <&CLK_csi_mac_lptx_top_i_1>, <&CLK_csi_mac_top_i_0>, <&CLK_csi_mac_top_i_1>, <&CLK_csi_ns_top_i_0>, <&CLK_csi_ns_top_i_1>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_dip>, <&CLK_ecc>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie>, <&CLK_fcie_p>, <&CLK_fclk1>, <&CLK_fclk1_p>, <&CLK_fclk2>, <&CLK_fclk2_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_gop0>, <&CLK_gop1>, <&CLK_gop2>, <&CLK_hemcu_216m>, <&CLK_idclk>, <&CLK_imi>, <&CLK_ipu>, <&CLK_ipupll_clk>, <&CLK_ir>, <&CLK_isp>, <&CLK_isp_p>, <&CLK_ive>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_lpll_clk_div2>, <&CLK_lpll_clk_div4>, <&CLK_lpll_clk_div8>, <&CLK_mac_lptx>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_miic2>, <&CLK_miic3>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_bach>, <&CLK_miu_bdma>, <&CLK_miu_cmdq>, <&CLK_miu_dig>, <&CLK_miu_emac>, <&CLK_miu_fcie>, <&CLK_miu_ff>, <&CLK_miu_file>, <&CLK_miu_gop>, <&CLK_miu_isp_dma>, <&CLK_miu_isp_dnr>, <&CLK_miu_isp_rot>, <&CLK_miu_isp_sta>, <&CLK_miu_ive>, <&CLK_miu_jpe0>, <&CLK_miu_jpe1>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc1_dbg>, <&CLK_miu_sc1_frm>, <&CLK_miu_sc1_snp>, <&CLK_miu_sc1_snpi>, <&CLK_miu_sc2_frm>, <&CLK_miu_sc2_snpi>, <&CLK_miu_sc3_frm>, <&CLK_miu_sc_crop>, <&CLK_miu_sc_dnr>, <&CLK_miu_sc_dnr_sad>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_sdio>, <&CLK_miu_uhc0>, <&CLK_miu_urdma>, <&CLK_miu_vhe>, <&CLK_miu_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi0>, <&CLK_mspi1>, <&CLK_ns>, <&CLK_odclk>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_pwr_ctl>, <&CLK_riu>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_sr>, <&CLK_sr_mclk>, <&CLK_sr_mclk1>, <&CLK_tck>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_venpll_clk>, <&CLK_vhe>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>; ++ clock-count = <196>; ++}; ++ +diff --git a/arch/arm/boot/dts/infinity5-fpga.dts b/arch/arm/boot/dts/infinity5-fpga.dts +new file mode 100644 +index 000000000000..eec3b932cbfb +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-fpga.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity5-fpga.dtsi" ++ ++/ { ++ model = "INFINITY5 FPGA"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5-fpga.dtsi b/arch/arm/boot/dts/infinity5-fpga.dtsi +new file mode 100755 +index 000000000000..04270b3ad1af +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-fpga.dtsi +@@ -0,0 +1,432 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity5/irqs.h> ++#include <../../../../drivers/sstar/include/infinity5/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "sstar,mfe"; ++ reg = <0x1F264E00 0x100>, <0x1F265000 0x100>, <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; ++ interrupts=; ++ //clocks = <&xtal>; ++ //clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ mhe: mhe { ++ compatible = "sstar,mhe"; ++ reg = <0x1F264800 0x100>, <0x1F264A00 0x100>, <0x1F264C00 0x100>, <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; ++ interrupts=; ++ //clocks = <&xtal>; ++ //clock-names = "CKG_mhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,sclhvsp1_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "disabled"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "disabled"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "disabled"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "disabled"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "disabled"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "disabled"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "disabled"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ status = "disable"; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ clocks = <&CLK_utmi>; ++ interrupts = ; ++ dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ clocks = <&CLK_utmi>; ++ interrupts = ; ++ dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++ status = "ok"; ++ clock-frequency-index = <8>; ++ }; ++ ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ spi0_mode = <1>; ++ spi1_mode = <1>; ++ status = "ok"; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1202>,<0x1203>,<0x1204>,<0x1205>,<0x1206>,<0x1207>,<0x1038>; ++ interrupts = ,; ++ clocks = <&CLK_csi_mac_lptx_top_i_0>,<&CLK_csi_mac_top_i_0>,<&CLK_csi_ns_top_i_0>,<&CLK_csi_mac_lptx_top_i_1>,<&CLK_csi_mac_top_i_1>,<&CLK_csi_ns_top_i_1>; ++ status = "ok"; ++ }; ++ ++ vif: vif { ++ compatible = "sigma,vif"; ++ status = "ok"; ++ reg = <0x1F263800 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F203C00 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>; ++ clocks = <&CLK_sr_mclk>,<&CLK_sr_mclk1>; ++ interrupts = ; ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <6>; ++ vif_sr0_mipi_mode_2lane = <2>; ++ vif_sr0_mipi_mode_4lane = <1>; ++ vif_sr0_bt656_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <1>; ++ vif_sr1_mipi_mode_1lane = <2>; ++ vif_sr1_mipi_mode_2lane = <1>; ++ vif_sr1_bt656_mode = <1>; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sigma,sensorif"; ++ status = "ok"; ++ }; ++ ++ middle: middle { ++ compatible = "sstar,middle"; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SNR0_D0, PAD_SNR0_D1 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SNR0_GPIO2, PAD_SNR0_GPIO4 ++ * 4 -> PAD_SNR1_GPIO5, PAD_SNR1_GPIO6 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++ }; ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ clocks = <&xtal>; ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>; ++ status = "disabled"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>; ++ status = "disabled"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>; ++ status = "disabled"; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ dla: dla { ++ compatible = "sstar-dla"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ ldc: ldc { ++ compatible = "sstar,ldc"; ++ reg = <0x1F245400 0x100>, <0x1F245600 0x100>, <0x1F245800 0x100>; ++ interrupts=; ++ //clocks = <&xtal>; ++ //clock-names = "CKG_ldc"; ++ //clk-select = <0>; // 0: 288MHz 1: 86MHz 2: 216MHz 3: 320MHz ++ status = "ok"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity5/reg_clks.h> ++ #include "infinity5-clks.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity5-ssc007a-at520d-s01a.dts b/arch/arm/boot/dts/infinity5-ssc007a-at520d-s01a.dts +new file mode 100755 +index 000000000000..2f406fc2e4f0 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-ssc007a-at520d-s01a.dts +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity5.dtsi" ++ ++/ { ++ model = "INFINITY5 SSC007A-S01A"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc LX_MEM=0x7E00000 mma_heap=mma_heap_name0,miu=0,sz=0x4000000"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reg = <0x27A00000 0x00400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5-ssc007a-s01a.dts b/arch/arm/boot/dts/infinity5-ssc007a-s01a.dts +new file mode 100755 +index 000000000000..f319ddeb979f +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-ssc007a-s01a.dts +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity5.dtsi" ++ ++/ { ++ model = "INFINITY5 SSC007A-S01A"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc LX_MEM=0x7E00000 mma_heap=mma_heap_name0,miu=0,sz=0x4000000"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5-ssc007b-s01a.dts b/arch/arm/boot/dts/infinity5-ssc007b-s01a.dts +new file mode 100644 +index 000000000000..34e71b66f75c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-ssc007b-s01a.dts +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity5.dtsi" ++ ++/ { ++ model = "INFINITY5 SSC007B-S01A"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ //reg = <0x26E00000 0x00400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5-ssc007b-s01b.dts b/arch/arm/boot/dts/infinity5-ssc007b-s01b.dts +new file mode 100755 +index 000000000000..85f0a22a07e7 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5-ssc007b-s01b.dts +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity5.dtsi" ++ ++/ { ++ model = "INFINITY5 SSC007B-S01A"; ++ compatible = "sstar,infinity5"; ++ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ //reg = <0x26E00000 0x00400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity5.dtsi b/arch/arm/boot/dts/infinity5.dtsi +new file mode 100755 +index 000000000000..ce7bd653e0fd +--- /dev/null ++++ b/arch/arm/boot/dts/infinity5.dtsi +@@ -0,0 +1,848 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity5/irqs.h> ++#include <../../../../drivers/sstar/include/infinity5/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++#include <../../../../include/generated/autoconf.h> ++#ifdef CONFIG_CAM_CLK ++#include <../../../../drivers/sstar/include/infinity5/camclk.h> ++#endif ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&CLK_cpupll_clk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++*/ ++ ++ venc{ ++ compatible = "sstar,venc"; ++ reg = <0x1F264800 0x100>, <0x1F264A00 0x100>, <0x1F264C00 0x100>, ++ <0x1F264E00 0x100>, <0x1F265000 0x100>, ++ <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; ++ reg-names = "mhe-0", "mhe-1", "mhe-2", "mfe-0", "mfe-1", "ven-0", "ven-1", "ven-2", "ven-3"; ++ interrupts = , ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq", "mfe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_miu_vhe>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_vhe_gp>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,sclhvsp1_i2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ttl-mode = <1>; ++ jtag-mode = <1>; ++ interrupts = ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart0@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ dma = <1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ ++/* ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ //led-orange = ; //software toggle GPIO LED For QFN ++ //led-green = ; //software toggle GPIO LED For QFN ++ status = "ok"; ++ }; ++*/ ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; ++ pad = <0x1F203C3C 0x0004 0x0000>; ++ phy-handle = <&phy0>; ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ nandflash { ++ compatible = "ms-nand"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ bus-width = <8>; ++ status = "ok"; ++ }; ++ ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-2 { ++ compatible = "Sstar-ehci-2"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ clock-frequency-index = <8>; ++ }; ++ ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ spi0_mode = <1>; ++ spi1_mode = <1>; ++ status = "ok"; ++ }; ++ ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1202>,<0x1203>,<0x1204>,<0x1205>,<0x1206>,<0x1207>,<0x1038>; ++ interrupts = ,; ++ clocks = <&CLK_csi_mac_lptx_top_i_0>,<&CLK_csi_mac_top_i_0>,<&CLK_csi_ns_top_i_0>,<&CLK_csi_mac_lptx_top_i_1>,<&CLK_csi_mac_top_i_1>,<&CLK_csi_ns_top_i_1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ /* Config max lane number */ ++ csi_sr0_lane_num = <4>; ++ csi_sr1_lane_num = <2>; ++ status = "ok"; ++ }; ++ ++ vif: vif { ++ compatible = "sigma,vif"; ++ status = "ok"; ++ reg = <0x1F263800 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F203C00 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>; ++ clocks = <&CLK_sr_mclk>,<&CLK_sr_mclk1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <6>; ++ vif_sr0_mipi_mode_2lane = <2>; ++ vif_sr0_mipi_mode_4lane = <1>; ++ vif_sr0_bt656_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <1>; ++ vif_sr1_mipi_mode_1lane = <2>; ++ vif_sr1_mipi_mode_2lane = <1>; ++ vif_sr1_bt656_mode = <1>; ++ /* Config mclk 37.125MHz supported */ ++ vif_sr0_mclk_37p125 = <1>; ++ vif_sr1_mclk_37p125 = <1>; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sigma,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <2>; ++ }; ++ ++ middle: middle { ++ compatible = "sstar,middle"; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 384Mhz 1: 288MHz 2: 192MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SNR0_D0, PAD_SNR0_D1 ++ */ ++ i2c-padmux = <1>; ++ goodix_gt911@5D{ ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ reset-gpio = ; ++ irq-gpio = ; ++ }; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SNR0_GPIO2, PAD_SNR0_GPIO4 ++ * 4 -> PAD_SNR1_GPIO5, PAD_SNR1_GPIO6 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223400 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic2>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <2>; ++ /* ++ * padmux: 1 -> PAD_SNR1_GPIO5, PAD_SNR1_GPIO6 ++ * 2 -> PAD_UART0_RX, PAD_UART0_TX ++ * 3 -> PAD_LCD_D4, PAD_LCD_D5 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++ }; ++ ++ i2c3@3{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223600 0x200>,<0x1F203C00 0x200>, <0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size = <0>; ++ clocks = <&CLK_miic3>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <3>; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_NAND_DA2, PAD_NAND_DA3 ++ * 3 -> PAD_LCD_D0, PAD_LCD_D1 ++ * 4 -> PAD_LCD_D6, PAD_LCD_D7 ++ * 5 -> PAD_UART0_RX, PAD_UART0_TX ++ */ ++ i2c-padmux = <2>; ++ status = "disable"; ++ }; ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sar-gpio{ ++ compatible = "sstar,sar-gpio"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ ++ digmic-padmux = <6>; //1~6 ++ i2stdm-padmux = <1>; //only 1 mode ++ i2smck-padmux = <1>; //only 1 mode ++ i2smod-padmux = <0>; //0:i2s tdm, 1:i2s normal ++ keep-i2s-clk = <0>; ++ ++ //I2S RX TDM ++ i2s-rx-tdm-ws-pgm = <0>; // 0: OFF 1: ON ++ i2s-rx-tdm-ws-width = <0>; // value: 0~31 (width = value + 1) ++ i2s-rx-tdm-ch-swap = <0 0>; // 0: OFF 1: ON ++ ++ //I2S TX TDM ++ i2s-tx-tdm-ws-pgm = <0>; // 0: OFF 1: ON ++ i2s-tx-tdm-ws-width = <0>; // value: 0~31 (width = value + 1) ++ i2s-tx-tdm-ch-swap = <0 0>; // 0: OFF 1: ON ++ i2s-tx-tdm-active-slot = <0x03>; // value: 0x00 ~ 0xFF (bit0->slot0, bit1->slot1, ... ) ++ ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <2>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; ++ slot-pad-orders = <2>,<0>,<1>; ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-cdzs-gpios = ,,<0>; // Pad 0: PAD_PM_SD_CDZ ++ slot-pwr-gpios = ,,<0>; // Pad 0: PAD_FUART_RTS ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ ++ interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_main_intc GIC_SPI INT_IRQ_FCIE IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_main_intc GIC_SPI INT_IRQ_FCIE IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_pm_intc INT_PMSLEEP_IRIN>, ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "mie0_irq", "mie1_irq", "mie2_irq", "cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"; ++ clocks = <&CLK_sdio>,<&CLK_fcie>,<&CLK_fcie>; ++ ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ interrupts=; ++ clocks = <&CLK_aesdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop { ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop1 { ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop2 { ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ rtcpwc { ++ compatible = "sstar,infinity-rtcpwc"; ++ reg = <0x1F006800 0x200>; ++ interrupts=; //need to check ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ vid0-gpio = ; ++ vid1-gpio = ; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "ok"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "ok"; ++ }; ++ ++ ircut { ++ compatible = "sstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x400>; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ npwm = <8>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ clocks = <&CLK_dip>; ++ status = "ok"; ++ }; ++ ++ dla: dla { ++ compatible = "sstar-dla"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ /* ++ pm { ++ compatible = "sstar,infinity-pm"; ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ detect-gpio = ; ++ }; ++ */ ++ ++ Mstar-udc { ++ compatible = "sstar,infinity-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ ldc: ldc { ++ compatible = "sstar,ldc"; ++ reg = <0x1F245400 0x100>, <0x1F245600 0x100>, <0x1F245800 0x100>; ++ interrupts=; ++ clocks = <&CLK_fclk2>; ++ //clock-names = "CKG_ldc"; ++ //clk-select = <0>; // 0: 288MHz 1: 86MHz 2: 216MHz 3: 320MHz ++ status = "ok"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity5/reg_clks.h> ++ #include "infinity5-clks.dtsi" ++}; +diff --git a/arch/arm/boot/dts/infinity6-clks.dtsi b/arch/arm/boot/dts/infinity6-clks.dtsi +new file mode 100755 +index 000000000000..c0906bff2b34 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-clks.dtsi +@@ -0,0 +1,1800 @@ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I6/iNfinity6_Clock_Table_1022_SW.xls */ ++/* REG FILENAME: I6/iNfinity6_reg_CLKGEN.xls, I6/iNfinity6_reg_pm_sleep.xls, I6/iNfinity6_reg_block.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi_480m: CLK_utmi_480m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div2: CLK_lpll_clk_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div4: CLK_lpll_clk_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div8: CLK_lpll_clk_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_armpll_37p125m: CLK_armpll_37p125m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_432m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_pm>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_isp_p: CLK_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_isp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk2_p: CLK_fclk2_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp: CLK_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe: CLK_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfeh: CLK_miu_mfeh { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfe: CLK_miu_mfe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe1: CLK_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe0: CLK_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bach: CLK_miu_bach { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_file: CLK_miu_file { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_uhc0: CLK_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_emac: CLK_miu_emac { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_cmdq: CLK_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dnr: CLK_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_rot: CLK_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dma: CLK_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_sta: CLK_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_gop: CLK_miu_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr: CLK_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_crop: CLK_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_frm: CLK_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snp: CLK_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snpi: CLK_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_dbg: CLK_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_frm: CLK_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_snpi: CLK_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc3_frm: CLK_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_fcie: CLK_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sdio: CLK_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_ive: CLK_miu_ive { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_nogating: CLK_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_vhe_gp: CLK_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck: CLK_tck { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_tck_buf>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop0: CLK_gop0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop1: CLK_gop1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop2: CLK_gop2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <3>; ++ clock-mult = <30>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_xtali_24m>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_csi_mac>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_pwr_ctl: CLK_pwr_ctl { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_PWR_CTL_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_PWR_CTL_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr_mclk: CLK_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_clk_div2>,<&CLK_lpll_clk_div4>,<&CLK_lpll_clk_div8>,<&CLK_armpll_37p125m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <4>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET ++}; ++ ++CLK_mfe: CLK_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_upll_384m>,<&CLK_upll_320m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET ++ auto-enable = <1>; ++}; ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_sd: CLK_sd { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SD_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SD_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_172m>,<&CLK_utmi_192m>,<&CLK_utmi_240m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_mpll_172m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++}; ++ ++CLK_fclk2: CLK_fclk2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++}; ++ ++CLK_dip: CLK_dip { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DIP_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_DIP_OFFSET ++}; ++ ++CLK_nlm: CLK_nlm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++}; ++ ++CLK_csi_mac: CLK_csi_mac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET ++}; ++ ++CLK_mac_lptx: CLK_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET ++}; ++ ++CLK_ns: CLK_ns { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_NS_OFFSET ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET ++ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++ auto-enable = <1>; ++}; ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, ++ <&CLK_VOID>, ++ <&CLK_aesdma>, ++ <&CLK_armpll_37p125m>, ++ <&CLK_axi2x>, ++ <&CLK_bdma>, ++ <&CLK_bist>, ++ <&CLK_bist_sc_gp>, ++ <&CLK_bist_vhe_gp>, ++ <&CLK_ccir_in_clk>, ++ <&CLK_cpupll_clk>, ++ <&CLK_csi2_mac_p>, ++ <&CLK_csi_mac>, ++ <&CLK_ddr_syn>, ++ <&CLK_ddrpll_clk>, ++ <&CLK_dip>, ++ <&CLK_emac_ahb>, ++ <&CLK_emac_rx>, ++ <&CLK_emac_rx_ref>, ++ <&CLK_emac_testrx125_in_lan>, ++ <&CLK_emac_tx>, ++ <&CLK_emac_tx_ref>, ++ <&CLK_eth_buf>, ++ <&CLK_fclk1>, ++ <&CLK_fclk1_p>, ++ <&CLK_fclk2>, ++ <&CLK_fclk2_p>, ++ <&CLK_fuart>, ++ <&CLK_fuart0_synth_in>, ++ <&CLK_fuart0_synth_out>, ++ <&CLK_gop0>, ++ <&CLK_gop1>, ++ <&CLK_gop2>, ++ <&CLK_hemcu_216m>, ++ <&CLK_imi>, ++ <&CLK_ir>, ++ <&CLK_isp>, ++ <&CLK_isp_p>, ++ <&CLK_jpe>, ++ <&CLK_live>, ++ <&CLK_live_pm>, ++ <&CLK_lpll_clk>, ++ <&CLK_lpll_clk_div2>, ++ <&CLK_lpll_clk_div4>, ++ <&CLK_lpll_clk_div8>, ++ <&CLK_mac_lptx>, ++ <&CLK_mcu>, ++ <&CLK_mcu_p>, ++ <&CLK_mcu_pm>, ++ <&CLK_mcu_pm_p>, ++ <&CLK_miic0>, ++ <&CLK_miic1>, ++ <&CLK_miu>, ++ <&CLK_miu2x>, ++ <&CLK_miu2x_p>, ++ <&CLK_miu_bach>, ++ <&CLK_miu_bdma>, ++ <&CLK_miu_cmdq>, ++ <&CLK_miu_dig>, ++ <&CLK_miu_emac>, ++ <&CLK_miu_fcie>, ++ <&CLK_miu_ff>, ++ <&CLK_miu_file>, ++ <&CLK_miu_gop>, ++ <&CLK_miu_isp_dma>, ++ <&CLK_miu_isp_dnr>, ++ <&CLK_miu_isp_rot>, ++ <&CLK_miu_isp_sta>, ++ <&CLK_miu_ive>, ++ <&CLK_miu_jpe0>, ++ <&CLK_miu_jpe1>, ++ <&CLK_miu_mfe>, ++ <&CLK_miu_mfeh>, ++ <&CLK_miu_p>, ++ <&CLK_miu_rec>, ++ <&CLK_miu_sc1_dbg>, ++ <&CLK_miu_sc1_frm>, ++ <&CLK_miu_sc1_snp>, ++ <&CLK_miu_sc1_snpi>, ++ <&CLK_miu_sc2_frm>, ++ <&CLK_miu_sc2_snpi>, ++ <&CLK_miu_sc3_frm>, ++ <&CLK_miu_sc_crop>, ++ <&CLK_miu_sc_dnr>, ++ <&CLK_miu_sc_dnr_sad>, ++ <&CLK_miu_sc_gp>, ++ <&CLK_miu_sc_gp_p>, ++ <&CLK_miu_sdio>, ++ <&CLK_miu_uhc0>, ++ <&CLK_miu_urdma>, ++ <&CLK_miu_vhe>, ++ <&CLK_miu_vhe_gp>, ++ <&CLK_miu_vhe_gp_p>, ++ <&CLK_miu_xd2miu>, ++ <&CLK_miupll_clk>, ++ <&CLK_mpll_123m>, ++ <&CLK_mpll_123m_div2>, ++ <&CLK_mpll_144m>, ++ <&CLK_mpll_144m_div2>, ++ <&CLK_mpll_144m_div4>, ++ <&CLK_mpll_172m>, ++ <&CLK_mpll_216m>, ++ <&CLK_mpll_216m_div2>, ++ <&CLK_mpll_216m_div4>, ++ <&CLK_mpll_216m_div8>, ++ <&CLK_mpll_288m>, ++ <&CLK_mpll_288m_div2>, ++ <&CLK_mpll_288m_div4>, ++ <&CLK_mpll_288m_div8>, ++ <&CLK_mpll_432m>, ++ <&CLK_mpll_86m>, ++ <&CLK_mpll_86m_div16>, ++ <&CLK_mpll_86m_div2>, ++ <&CLK_mpll_86m_div4>, ++ <&CLK_mspi>, ++ <&CLK_mspi0>, ++ <&CLK_mspi0_p>, ++ <&CLK_mspi1>, ++ <&CLK_mspi1_p>, ++ <&CLK_nlm>, ++ <&CLK_ns>, ++ <&CLK_odclk>, ++ <&CLK_pad2isp_sr_pclk>, ++ <&CLK_pm_riu_w_clk_in>, ++ <&CLK_pm_sleep>, ++ <&CLK_pwr_ctl>, ++ <&CLK_riu>, ++ <&CLK_riu_hemcu_gp>, ++ <&CLK_riu_mcu_if>, ++ <&CLK_riu_mipi_gp>, ++ <&CLK_riu_nogating>, ++ <&CLK_riu_pm>, ++ <&CLK_riu_sc_gp>, ++ <&CLK_riu_vhe_gp>, ++ <&CLK_riu_w_clk_hemcu_gp>, ++ <&CLK_riu_w_clk_in>, ++ <&CLK_riu_w_clk_mcu_if_gp>, ++ <&CLK_riu_w_clk_mipi_if_gp>, ++ <&CLK_riu_w_clk_sc_gp>, ++ <&CLK_riu_w_clk_top>, ++ <&CLK_riu_w_clk_vhe_gp>, ++ <&CLK_riubrdg>, ++ <&CLK_rmii_buf>, ++ <&CLK_rtc>, ++ <&CLK_rtc_32k>, ++ <&CLK_rtc_32k_div4>, ++ <&CLK_sar>, ++ <&CLK_sd>, ++ <&CLK_sdio>, ++ <&CLK_sdio_p>, ++ <&CLK_spi>, ++ <&CLK_spi_pm>, ++ <&CLK_sr_mclk>, ++ <&CLK_tck>, ++ <&CLK_tck_buf>, ++ <&CLK_uart0>, ++ <&CLK_uart1>, ++ <&CLK_upll>, ++ <&CLK_upll_320m>, ++ <&CLK_upll_384m>, ++ <&CLK_utmi>, ++ <&CLK_utmi_160m>, ++ <&CLK_utmi_160m_div4>, ++ <&CLK_utmi_160m_div5>, ++ <&CLK_utmi_160m_div8>, ++ <&CLK_utmi_192m>, ++ <&CLK_utmi_192m_div4>, ++ <&CLK_utmi_240m>, ++ <&CLK_utmi_480m>, ++ <&CLK_vhe>, ++ <&CLK_xtali>, ++ <&CLK_xtali_12m>, ++ <&CLK_xtali_12m_div12>, ++ <&CLK_xtali_12m_div128>, ++ <&CLK_xtali_12m_div16>, ++ <&CLK_xtali_12m_div2>, ++ <&CLK_xtali_12m_div4>, ++ <&CLK_xtali_12m_div40>, ++ <&CLK_xtali_12m_div64>, ++ <&CLK_xtali_12m_div8>, ++ <&CLK_xtali_24m>, ++ <&CLK_xtali_sc_gp>; ++ clock-count = <182>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity6-clks_simple.dtsi b/arch/arm/boot/dts/infinity6-clks_simple.dtsi +new file mode 100755 +index 000000000000..5cd6d1ebe842 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-clks_simple.dtsi +@@ -0,0 +1,707 @@ ++/* generated manually for fast booting */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi_480m: CLK_utmi_480m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_xtali_24m>; ++}; ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_xtali_24m>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_sd: CLK_sd { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SD_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SD_OFFSET ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++}; ++ ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, ++ <&CLK_VOID>, ++ <&CLK_aesdma>, ++ <&CLK_armpll_37p125m>, ++ <&CLK_axi2x>, ++ <&CLK_bdma>, ++ <&CLK_bist>, ++ <&CLK_bist_sc_gp>, ++ <&CLK_bist_vhe_gp>, ++ <&CLK_ccir_in_clk>, ++ <&CLK_cpupll_clk>, ++ <&CLK_csi2_mac_p>, ++ <&CLK_csi_mac>, ++ <&CLK_ddr_syn>, ++ <&CLK_ddrpll_clk>, ++ <&CLK_dip>, ++ <&CLK_emac_ahb>, ++ <&CLK_emac_rx>, ++ <&CLK_emac_rx_ref>, ++ <&CLK_emac_testrx125_in_lan>, ++ <&CLK_emac_tx>, ++ <&CLK_emac_tx_ref>, ++ <&CLK_eth_buf>, ++ <&CLK_fclk1>, ++ <&CLK_fclk1_p>, ++ <&CLK_fclk2>, ++ <&CLK_fclk2_p>, ++ <&CLK_fuart>, ++ <&CLK_fuart0_synth_in>, ++ <&CLK_fuart0_synth_out>, ++ <&CLK_gop0>, ++ <&CLK_gop1>, ++ <&CLK_gop2>, ++ <&CLK_hemcu_216m>, ++ <&CLK_imi>, ++ <&CLK_ir>, ++ <&CLK_isp>, ++ <&CLK_isp_p>, ++ <&CLK_jpe>, ++ <&CLK_live>, ++ <&CLK_live_pm>, ++ <&CLK_lpll_clk>, ++ <&CLK_lpll_clk_div2>, ++ <&CLK_lpll_clk_div4>, ++ <&CLK_lpll_clk_div8>, ++ <&CLK_mac_lptx>, ++ <&CLK_mcu>, ++ <&CLK_mcu_p>, ++ <&CLK_mcu_pm>, ++ <&CLK_mcu_pm_p>, ++ <&CLK_miic0>, ++ <&CLK_miic1>, ++ <&CLK_miu>, ++ <&CLK_miu2x>, ++ <&CLK_miu2x_p>, ++ <&CLK_miu_bach>, ++ <&CLK_miu_bdma>, ++ <&CLK_miu_cmdq>, ++ <&CLK_miu_dig>, ++ <&CLK_miu_emac>, ++ <&CLK_miu_fcie>, ++ <&CLK_miu_ff>, ++ <&CLK_miu_file>, ++ <&CLK_miu_gop>, ++ <&CLK_miu_isp_dma>, ++ <&CLK_miu_isp_dnr>, ++ <&CLK_miu_isp_rot>, ++ <&CLK_miu_isp_sta>, ++ <&CLK_miu_ive>, ++ <&CLK_miu_jpe0>, ++ <&CLK_miu_jpe1>, ++ <&CLK_miu_mfe>, ++ <&CLK_miu_mfeh>, ++ <&CLK_miu_p>, ++ <&CLK_miu_rec>, ++ <&CLK_miu_sc1_dbg>, ++ <&CLK_miu_sc1_frm>, ++ <&CLK_miu_sc1_snp>, ++ <&CLK_miu_sc1_snpi>, ++ <&CLK_miu_sc2_frm>, ++ <&CLK_miu_sc2_snpi>, ++ <&CLK_miu_sc3_frm>, ++ <&CLK_miu_sc_crop>, ++ <&CLK_miu_sc_dnr>, ++ <&CLK_miu_sc_dnr_sad>, ++ <&CLK_miu_sc_gp>, ++ <&CLK_miu_sc_gp_p>, ++ <&CLK_miu_sdio>, ++ <&CLK_miu_uhc0>, ++ <&CLK_miu_urdma>, ++ <&CLK_miu_vhe>, ++ <&CLK_miu_vhe_gp>, ++ <&CLK_miu_vhe_gp_p>, ++ <&CLK_miu_xd2miu>, ++ <&CLK_miupll_clk>, ++ <&CLK_mpll_123m>, ++ <&CLK_mpll_123m_div2>, ++ <&CLK_mpll_144m>, ++ <&CLK_mpll_144m_div2>, ++ <&CLK_mpll_144m_div4>, ++ <&CLK_mpll_172m>, ++ <&CLK_mpll_216m>, ++ <&CLK_mpll_216m_div2>, ++ <&CLK_mpll_216m_div4>, ++ <&CLK_mpll_216m_div8>, ++ <&CLK_mpll_288m>, ++ <&CLK_mpll_288m_div2>, ++ <&CLK_mpll_288m_div4>, ++ <&CLK_mpll_288m_div8>, ++ <&CLK_mpll_432m>, ++ <&CLK_mpll_86m>, ++ <&CLK_mpll_86m_div16>, ++ <&CLK_mpll_86m_div2>, ++ <&CLK_mpll_86m_div4>, ++ <&CLK_mspi>, ++ <&CLK_mspi0>, ++ <&CLK_mspi0_p>, ++ <&CLK_mspi1>, ++ <&CLK_mspi1_p>, ++ <&CLK_nlm>, ++ <&CLK_ns>, ++ <&CLK_odclk>, ++ <&CLK_pad2isp_sr_pclk>, ++ <&CLK_pm_riu_w_clk_in>, ++ <&CLK_pm_sleep>, ++ <&CLK_pwr_ctl>, ++ <&CLK_riu>, ++ <&CLK_riu_hemcu_gp>, ++ <&CLK_riu_mcu_if>, ++ <&CLK_riu_mipi_gp>, ++ <&CLK_riu_nogating>, ++ <&CLK_riu_pm>, ++ <&CLK_riu_sc_gp>, ++ <&CLK_riu_vhe_gp>, ++ <&CLK_riu_w_clk_hemcu_gp>, ++ <&CLK_riu_w_clk_in>, ++ <&CLK_riu_w_clk_mcu_if_gp>, ++ <&CLK_riu_w_clk_mipi_if_gp>, ++ <&CLK_riu_w_clk_sc_gp>, ++ <&CLK_riu_w_clk_top>, ++ <&CLK_riu_w_clk_vhe_gp>, ++ <&CLK_riubrdg>, ++ <&CLK_rmii_buf>, ++ <&CLK_rtc>, ++ <&CLK_rtc_32k>, ++ <&CLK_rtc_32k_div4>, ++ <&CLK_sar>, ++ <&CLK_sd>, ++ <&CLK_sdio>, ++ <&CLK_sdio_p>, ++ <&CLK_spi>, ++ <&CLK_spi_pm>, ++ <&CLK_sr_mclk>, ++ <&CLK_tck>, ++ <&CLK_tck_buf>, ++ <&CLK_uart0>, ++ <&CLK_uart1>, ++ <&CLK_upll>, ++ <&CLK_upll_320m>, ++ <&CLK_upll_384m>, ++ <&CLK_utmi>, ++ <&CLK_utmi_160m>, ++ <&CLK_utmi_160m_div4>, ++ <&CLK_utmi_160m_div5>, ++ <&CLK_utmi_160m_div8>, ++ <&CLK_utmi_192m>, ++ <&CLK_utmi_192m_div4>, ++ <&CLK_utmi_240m>, ++ <&CLK_utmi_480m>, ++ <&CLK_vhe>, ++ <&CLK_xtali>, ++ <&CLK_xtali_12m>, ++ <&CLK_xtali_12m_div12>, ++ <&CLK_xtali_12m_div128>, ++ <&CLK_xtali_12m_div16>, ++ <&CLK_xtali_12m_div2>, ++ <&CLK_xtali_12m_div4>, ++ <&CLK_xtali_12m_div40>, ++ <&CLK_xtali_12m_div64>, ++ <&CLK_xtali_12m_div8>, ++ <&CLK_xtali_24m>, ++ <&CLK_xtali_sc_gp>; ++ clock-count = <182>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity6-fpga.dts b/arch/arm/boot/dts/infinity6-fpga.dts +new file mode 100755 +index 000000000000..a26623640af9 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-fpga.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6-fpga.dtsi" ++ ++/ { ++ model = "INFINITY6 FPGA"; ++ compatible = "sstar,infinity6"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6-fpga.dtsi b/arch/arm/boot/dts/infinity6-fpga.dtsi +new file mode 100755 +index 000000000000..6a8979f19b96 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-fpga.dtsi +@@ -0,0 +1,475 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity6/irqs.h> ++#include <../../../../drivers/sstar/include/infinity6/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ ++ venc{ ++ compatible = "sstar,venc"; ++ reg = <0x1F264800 0x100>, <0x1F264A00 0x100>, <0x1F264C00 0x100>, ++ <0x1F264E00 0x100>, <0x1F265000 0x100>, ++ <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; ++ reg-names = "mhe-0", "mhe-1", "mhe-2", "mfe-0", "mfe-1", "ven-0", "ven-1", "ven-2", "ven-3"; ++ interrupts = , ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq", "mfe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_miu_vhe>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_vhe_gp>; ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,sclhvsp1_i6"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "sstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "sstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sigmastar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ disp: disp { ++ compatible = "sigmastar,disp"; ++ status = "ok"; ++ interrupts = , , , ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ clocks = <&CLK_dip>; ++ status = "ok"; ++ }; ++ ++/* ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ status = "ok"; ++ }; ++*/ ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++ // reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x00000000 0x000>; ++ pad = <0x1F203C3C 0x0004 0x0004>; // pad selection from 0x0001 ++ phy-handle = <&phy0>; ++ max-speed = <10>; ++ mdio_path = <0>; // force internal mdio ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ // phy-mode = "rmii"; ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "disabled"; ++ }; ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++ status = "ok"; ++ clock-frequency-index = <5>; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ status = "ok"; ++ }; ++ ++ vif: vif { ++ compatible = "sigma,vif"; ++ status = "ok"; ++ reg = <0x1F263200 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F203C00 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>; ++ clocks = <&CLK_sr_mclk>; ++ interrupts = ; ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <2>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <2>; ++ vif_sr0_rst_mode = <2>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sigma,sensorif"; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ sound { ++ compatible = "sstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ clocks = <&CLK_aesdma>; ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>; ++ status = "ok"; ++ }; ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <11>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6/reg_clks.h> ++ #include "infinity6-clks.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity6-spinand-ssc009a-s01a-lh.dts b/arch/arm/boot/dts/infinity6-spinand-ssc009a-s01a-lh.dts +new file mode 100755 +index 000000000000..a9de1abaf6dc +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-spinand-ssc009a-s01a-lh.dts +@@ -0,0 +1,96 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6.dtsi" ++ ++/ { ++ model = "INFINITY6 SSC009A-S01A QFN88 LH"; ++ compatible = "sstar,infinity6"; ++ ++ memory { ++ reg = <0x20000000 0x05400000>; ++ }; ++ ++ chosen { ++ /*rootfs in mtd:ubi:ubifs*/ ++ bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1"; ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 loglevel=2 initcall_debug=1";*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 loglevel=2";*/ ++ ++ /*rootfs in mtd:squashfs*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=/dev/mtdblock8 rootfstype=squashfs ro init=/linuxrc rootwait=1 loglevel=2";*/ ++ /*bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc";*/ ++ ++ /*initrd*/ ++ /* bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc rootwait"; ++ linux,initrd-start = <0x20E00000>; ++ linux,initrd-end = <0x20F80000>;*/ ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <4>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <3>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ }; ++ }; ++ ++}; ++ ++&emac0 { ++ pad_led = <0x00000000 0x0000 0x0000>; ++ status = "ok"; ++}; +diff --git a/arch/arm/boot/dts/infinity6-ssc009a-s01a-lh.dts b/arch/arm/boot/dts/infinity6-ssc009a-s01a-lh.dts +new file mode 100755 +index 000000000000..038952a1c360 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-ssc009a-s01a-lh.dts +@@ -0,0 +1,82 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#define __DTS_DUALOS__ ++#include "infinity6.dtsi" ++ ++/ { ++ model = "INFINITY6 SSC009A-S01A QFN88 LH"; ++ compatible = "sstar,infinity6"; ++ ++ memory { ++ reg = <0x20000000 0x05400000>; ++ }; ++ ++ chosen { ++ /*rootfs in mtd:ubi:ubifs*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1";*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 loglevel=2 initcall_debug=1";*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 loglevel=2";*/ ++ ++ /*rootfs in mtd:squashfs*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=/dev/mtdblock8 rootfstype=squashfs ro init=/linuxrc rootwait=1 loglevel=2";*/ ++ /*bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc";*/ ++ ++ /*initrd*/ ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc rootwait"; ++ linux,initrd-start = <0x20E00000>; ++ linux,initrd-end = <0x20F00000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ }; ++ ++ flashisp { ++ status = "disabled"; ++ }; ++ }; ++ ++}; ++ ++&emac0 { ++ pad_led = <0x00000000 0x0000 0x0000>; ++ status = "ok"; ++}; +diff --git a/arch/arm/boot/dts/infinity6-ssc009a-s01a.dts b/arch/arm/boot/dts/infinity6-ssc009a-s01a.dts +new file mode 100755 +index 000000000000..60617b984ac6 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-ssc009a-s01a.dts +@@ -0,0 +1,95 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6.dtsi" ++#include <../../../../drivers/sstar/include/infinity6/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ model = "INFINITY6 SSC009A-S01A QFN88"; ++ compatible = "sstar,infinity6"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x07E00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <4>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <3>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <2>; ++ ++ }; ++ ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ }; ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ , ++ ; ++ // status = "ok"; // ok or disable ++ status = "disable"; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6-ssc009b-s01a-lh.dts b/arch/arm/boot/dts/infinity6-ssc009b-s01a-lh.dts +new file mode 100755 +index 000000000000..aa77d620cb75 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-ssc009b-s01a-lh.dts +@@ -0,0 +1,101 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#define __DTS_DUALOS__ ++#include "infinity6.dtsi" ++ ++/ { ++ model = "INFINITY6 SSC009B-S01A QFN128 LH"; ++ compatible = "sstar,infinity6"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x0FE00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ /*rootfs in mtd:ubi:ubifs*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1";*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 loglevel=2 initcall_debug=1";*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 loglevel=2";*/ ++ ++ /*rootfs in mtd:squashfs*/ ++ /*bootargs = "console=ttyS0 ubi.mtd=10,2048 root=/dev/mtdblock8 rootfstype=squashfs ro init=/linuxrc rootwait=1 loglevel=2";*/ ++ /*bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc";*/ ++ ++ /*initrd*/ ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc rootwait"; ++ linux,initrd-start = <0x20E00000>; ++ linux,initrd-end = <0x20F00000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <2>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <1>; ++ }; ++ ++ core_voltage { ++ vid_width = <2>; ++ vid_gpios = ; ++ vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 ++ }; ++ ++ sdmmc { ++ slotnum = <2>; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6-ssc009b-s01a.dts b/arch/arm/boot/dts/infinity6-ssc009b-s01a.dts +new file mode 100755 +index 000000000000..073bbc4cc14c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-ssc009b-s01a.dts +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6.dtsi" ++ ++/ { ++ model = "INFINITY6 SSC009B-S01A QFN128"; ++ compatible = "sstar,infinity6"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x0FE00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <2>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <1>; ++ }; ++ ++ core_voltage { ++ vid_width = <2>; ++ vid_gpios = ; ++ vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 ++ }; ++ ++ sdmmc { ++ slotnum = <2>; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6-ut-ssc009b-s01a.dts b/arch/arm/boot/dts/infinity6-ut-ssc009b-s01a.dts +new file mode 100755 +index 000000000000..64b2bf8d529f +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6-ut-ssc009b-s01a.dts +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6.dtsi" ++ ++/ { ++ model = "INFINITY6 SSC009B-S01A QFN128"; ++ compatible = "sstar,infinity6"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x0FE00000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=40m"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x3000000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <2>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <1>; ++ }; ++ ++ core_voltage { ++ vid_width = <2>; ++ vid_gpios = ; ++ vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 ++ }; ++ ++ sdmmc { ++ slotnum = <2>; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6.dtsi b/arch/arm/boot/dts/infinity6.dtsi +new file mode 100755 +index 000000000000..565c45b19e88 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6.dtsi +@@ -0,0 +1,755 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity6/irqs.h> ++#include <../../../../drivers/sstar/include/infinity6/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++#include <../../../../include/generated/autoconf.h> ++#ifdef CONFIG_CAM_CLK ++#include <../../../../drivers/sstar/include/infinity6/camclk.h> ++#endif ++ ++/ { ++ camclk: camclkinit { ++ compatible = "camdriver,camclkinit"; ++ status = "ok"; ++ }; ++ camclk { ++ compatible = "camdriver,camclk"; ++ status = "ok"; ++ }; ++ camclkut { ++ compatible = "camdriver,camclkut"; ++ status = "ok"; ++ }; ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++#ifndef CONFIG_CAM_CLK ++ clocks = <&CLK_cpupll_clk>; ++#endif ++ reg = <0x0>; ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 1000000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++*/ ++#ifndef __DTS_DUALOS__ ++ venc{ ++ compatible = "sstar,venc"; ++ reg = <0x1F264800 0x100>, <0x1F264A00 0x100>, <0x1F264C00 0x100>, ++ <0x1F264E00 0x100>, <0x1F265000 0x100>, ++ <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; ++ reg-names = "mhe-0", "mhe-1", "mhe-2", "mfe-0", "mfe-1", "ven-0", "ven-1", "ven-2", "ven-3"; ++ interrupts = , ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq", "mfe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_miu_vhe>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_vhe_gp>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ vpe: vpe { ++ compatible = "sigmastar,vpe"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ DigitalZoom-Dropmode = <1>; ++ interrupts = , , , ; ++ }; ++ ++ scl: scl { ++ compatible = "sstar,scl"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ ++ pnl: pnl { ++ compatible = "sigmastar,pnl"; ++ status = "ok"; ++ ttl-mode = <1>; ++ jtag-mode = <0>; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ disp: disp { ++ compatible = "sigmastar,disp"; ++ status = "ok"; ++ //Reg = <0x1F224000 0x200>; ++ interrupts = , , , ; ++ }; ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ clock-frequency-index = <5>; ++ //clk-pad = ; ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ //isp-flag = <0>; ++ }; ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1202>,<0x1203>,<0x1204>,<0x1038>,<0x101e>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ vif: vif { ++ compatible = "sigma,vif"; ++ status = "ok"; ++ reg = <0x1F263200 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F203C00 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>; ++ clocks = <&CLK_sr_mclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ,; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sigma,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_miu_ive>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sigmastar,gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&CLK_dip>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ clocks = <&CLK_dip>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++#endif ++ uart0: uart0@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ dma = <1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; ++ pad = <0x1F203C3C 0x0004 0x0000>; ++ phy-handle = <&phy0>; ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ quadread = <0>; ++ status = "ok"; ++ }; ++/* ++ nandflash { ++ compatible = "ms-nand"; ++ clocks = <&CLK_VOID>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks = <&CLK_VOID>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++*/ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ Sstar-udc { ++ compatible = "sstar,infinity-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ spi0_mode = <1>; ++ spi1_mode = <1>; ++ status = "disabled"; ++ }; ++ ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ ++ /* ++ 0: OFF ++ 1: PAD_GPIO4 ~ PAD_GPIO6 ++ 2: PAD_SD1_IO4 ~ PAD_SD1_IO6 ++ 3: PAD_SD1_IO8, PAD_UART0_RX, PAD_UART0_TX ++ */ ++ digmic-padmux = <1>; ++ ++ /* ++ 0: OFF ++ 1: PAD_GPIO0 ~ PAD_GPIO3 ++ 2: PAD_SD1_IO0 ~ PAD_SD1_IO3 ++ 3: PAD_SPI1_CZ, PAD_SPI1_CK, PAD_SPI1_DI, PAD_SPI1_DO ++ */ ++ i2s-padmux = <1>; ++ ++ keep-i2s-clk = <0>; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; // IP_SD: IP_SDIO: ++#else ++ clocks =<&CLK_sd>; // IP_SD:<&CLK_sd> IP_SDIO:<&CLK_sdio> ++#endif ++ ip-select = <0>; // 0:IP_SD 1:IP_SDIO ++ pad-select = <0>; // 0:PAD_SD 1:PAD_SD1 ++ interrupts = ; ++ bus-width = <4>; ++ max-clks = <2>; // 0:48M 1:43M 2:40M 3:36M 4:32M 5:20M 6:12M 7:300K ++ clk-driving = <0>; ++ cmd-driving = <0>; ++ data-driving = <0>; ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <1>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; // 0:IP_SD 1:IP_SDIO ++ slot-pad-orders = <0>,<1>,<2>; // 0:PAD_SD 1:PAD_SD1 ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-cdzs-gpios = ,,<0>; ++ slot-pwr-gpios = ,,<0>; ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ ++ interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_FCIE IRQ_TYPE_LEVEL_HIGH>, // No need to change. ++ <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, // No need to change. ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>, // CDZ int for Slot 0, default is for PAD_PM_SD_CDZ ++ <&ms_gpi_intc 42>, // CDZ int for Slot 1, default is for PAD_SD1_IO6 ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>; // CDZ int for Slot 2, None. ++ interrupt-names = "mie0_irq", "mie1_irq", "cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"; // No need to change. ++ clocks = <&CLK_sd>,<&CLK_sdio>,<&CLK_VOID>; // No need to change. ++ ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ interrupts=; ++ clocks = <&CLK_aesdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ rtcpwc { ++ compatible = "sstar,infinity-rtcpwc"; ++ reg = <0x1F006800 0x200>; ++ interrupts=; //need to check ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++#if 0 ++ tm_sec; /*¬í - ¨ú­È°Ï¶¡¬°[0, 59]*/ ++ tm_min; /*¤À - ¨ú­È°Ï¶¡¬°[0, 59]*/ ++ tm_hour; /*®É - ¨ú­È°Ï¶¡¬°[0, 23]*/ ++ tm_mday; /*¤é - ¨ú­È°Ï¶¡¬°[1, 31]*/ ++ tm_mon; /*¤ë¥÷ - ¨ú­È°Ï¶¡¬°[0, 11]*/ ++ tm_year; /*¦~¥÷ - ¨ä­È¬°1900¦~¦Ü¤µ¦~¼Æ*/ ++ tm_wday; /*¬P´Á - ¨ú­È°Ï¶¡[0, 6]¡A0¥Nªí¬P´Á¤Ñ¡A1¥Nªí¬P´Á1¡A¥H¦¹Ãþ±À*/ ++ tm_yday; /*±q¨C¦~ªº1¤ë1¤é¶}©lªº¤Ñ¼Æ-¨ú­È°Ï¶¡¬°[0, 365]¡A0¥Nªí1¤ë1¤é*/ ++ default_date = <0 0 0 5 10 83 6 0>; ++#endif ++ status = "ok"; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "ok"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "ok"; ++ }; ++ ++ ircut { ++ compatible = "sstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <11>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6/reg_clks.h> ++#ifndef __DTS_DUALOS__ ++ #include "infinity6-clks.dtsi" ++#else ++ #include "infinity6-clks_simple.dtsi" ++#endif ++ ++}; ++ +diff --git a/arch/arm/boot/dts/infinity6b0-clks.dtsi b/arch/arm/boot/dts/infinity6b0-clks.dtsi +new file mode 100755 +index 000000000000..90514061ab9c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-clks.dtsi +@@ -0,0 +1,1825 @@ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I6b0/iNfinity6b0_Clock_Table_SW.xls */ ++/* REG FILENAME: I6b0/iNfinity6b0_reg_CLKGEN.xls, I6b0/iNfinity6b0_reg_pm_sleep.xls, I6b0/iNfinity6b0_reg_block.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi_480m: CLK_utmi_480m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_mpll_345m: CLK_mpll_345m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <345000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div2: CLK_lpll_clk_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div4: CLK_lpll_clk_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_lpll_clk_div8: CLK_lpll_clk_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_lpll_clk>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_armpll_37p125m: CLK_armpll_37p125m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_432m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_pm>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_isp_p: CLK_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_isp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk2_p: CLK_fclk2_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp: CLK_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe: CLK_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfeh: CLK_miu_mfeh { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfe: CLK_miu_mfe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe1: CLK_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe0: CLK_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bach: CLK_miu_bach { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_file: CLK_miu_file { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_uhc0: CLK_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_emac: CLK_miu_emac { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_cmdq: CLK_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dnr: CLK_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_rot: CLK_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dma: CLK_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_sta: CLK_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_gop: CLK_miu_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr: CLK_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_crop: CLK_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_frm: CLK_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snp: CLK_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snpi: CLK_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_dbg: CLK_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_frm: CLK_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_snpi: CLK_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc3_frm: CLK_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_fcie: CLK_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sdio: CLK_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_ive: CLK_miu_ive { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_nogating: CLK_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_vhe_gp: CLK_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck: CLK_tck { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_tck_buf>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop0: CLK_gop0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop1: CLK_gop1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop2: CLK_gop2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <3>; ++ clock-mult = <30>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_xtali_24m>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_csi_mac>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_upll_320m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_pwr_ctl: CLK_pwr_ctl { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_PWR_CTL_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_PWR_CTL_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr_mclk: CLK_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_clk_div2>,<&CLK_lpll_clk_div4>,<&CLK_lpll_clk_div8>,<&CLK_armpll_37p125m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <4>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_mpll_345m>,<&CLK_upll_384m>,<&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET ++}; ++ ++CLK_vhe_vpu: CLK_vhe_vpu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_mpll_345m>,<&CLK_upll_384m>,<&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_VPU_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_VHE_VPU_OFFSET ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_sd: CLK_sd { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SD_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_SD_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_172m>,<&CLK_utmi_192m>,<&CLK_utmi_240m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_mpll_172m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++}; ++ ++CLK_fclk2: CLK_fclk2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++}; ++ ++CLK_dip: CLK_dip { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DIP_OFFSET ++ mux-width = <3>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_DIP_OFFSET ++}; ++ ++CLK_ive: CLK_ive { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_288m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_IVE_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <8>; //0+REG_CKG_IVE_OFFSET ++}; ++ ++CLK_nlm: CLK_nlm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++}; ++ ++CLK_csi_mac: CLK_csi_mac { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET ++}; ++ ++CLK_mac_lptx: CLK_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET ++}; ++ ++CLK_ns: CLK_ns { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_NS_OFFSET ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET ++ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++ auto-enable = <1>; ++}; ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, ++ <&CLK_VOID>, ++ <&CLK_aesdma>, ++ <&CLK_armpll_37p125m>, ++ <&CLK_axi2x>, ++ <&CLK_bdma>, ++ <&CLK_bist>, ++ <&CLK_bist_sc_gp>, ++ <&CLK_bist_vhe_gp>, ++ <&CLK_ccir_in_clk>, ++ <&CLK_cpupll_clk>, ++ <&CLK_csi2_mac_p>, ++ <&CLK_csi_mac>, ++ <&CLK_ddr_syn>, ++ <&CLK_ddrpll_clk>, ++ <&CLK_dip>, ++ <&CLK_emac_ahb>, ++ <&CLK_emac_rx>, ++ <&CLK_emac_rx_ref>, ++ <&CLK_emac_testrx125_in_lan>, ++ <&CLK_emac_tx>, ++ <&CLK_emac_tx_ref>, ++ <&CLK_eth_buf>, ++ <&CLK_fclk1>, ++ <&CLK_fclk1_p>, ++ <&CLK_fclk2>, ++ <&CLK_fclk2_p>, ++ <&CLK_fuart>, ++ <&CLK_fuart0_synth_in>, ++ <&CLK_fuart0_synth_out>, ++ <&CLK_gop0>, ++ <&CLK_gop1>, ++ <&CLK_gop2>, ++ <&CLK_hemcu_216m>, ++ <&CLK_imi>, ++ <&CLK_ir>, ++ <&CLK_isp>, ++ <&CLK_isp_p>, ++ <&CLK_ive>, ++ <&CLK_jpe>, ++ <&CLK_live>, ++ <&CLK_live_pm>, ++ <&CLK_lpll_clk>, ++ <&CLK_lpll_clk_div2>, ++ <&CLK_lpll_clk_div4>, ++ <&CLK_lpll_clk_div8>, ++ <&CLK_mac_lptx>, ++ <&CLK_mcu>, ++ <&CLK_mcu_p>, ++ <&CLK_mcu_pm>, ++ <&CLK_mcu_pm_p>, ++ <&CLK_miic0>, ++ <&CLK_miic1>, ++ <&CLK_miu>, ++ <&CLK_miu2x>, ++ <&CLK_miu2x_p>, ++ <&CLK_miu_bach>, ++ <&CLK_miu_bdma>, ++ <&CLK_miu_cmdq>, ++ <&CLK_miu_dig>, ++ <&CLK_miu_emac>, ++ <&CLK_miu_fcie>, ++ <&CLK_miu_ff>, ++ <&CLK_miu_file>, ++ <&CLK_miu_gop>, ++ <&CLK_miu_isp_dma>, ++ <&CLK_miu_isp_dnr>, ++ <&CLK_miu_isp_rot>, ++ <&CLK_miu_isp_sta>, ++ <&CLK_miu_ive>, ++ <&CLK_miu_jpe0>, ++ <&CLK_miu_jpe1>, ++ <&CLK_miu_mfeh>, ++ <&CLK_miu_p>, ++ <&CLK_miu_rec>, ++ <&CLK_miu_sc1_dbg>, ++ <&CLK_miu_sc1_frm>, ++ <&CLK_miu_sc1_snp>, ++ <&CLK_miu_sc1_snpi>, ++ <&CLK_miu_sc2_frm>, ++ <&CLK_miu_sc2_snpi>, ++ <&CLK_miu_sc3_frm>, ++ <&CLK_miu_sc_crop>, ++ <&CLK_miu_sc_dnr>, ++ <&CLK_miu_sc_dnr_sad>, ++ <&CLK_miu_sc_gp>, ++ <&CLK_miu_sc_gp_p>, ++ <&CLK_miu_sdio>, ++ <&CLK_miu_uhc0>, ++ <&CLK_miu_urdma>, ++ <&CLK_miu_vhe>, ++ <&CLK_miu_vhe_gp>, ++ <&CLK_miu_vhe_gp_p>, ++ <&CLK_miu_xd2miu>, ++ <&CLK_miupll_clk>, ++ <&CLK_mpll_123m>, ++ <&CLK_mpll_123m_div2>, ++ <&CLK_mpll_144m>, ++ <&CLK_mpll_144m_div2>, ++ <&CLK_mpll_144m_div4>, ++ <&CLK_mpll_172m>, ++ <&CLK_mpll_216m>, ++ <&CLK_mpll_216m_div2>, ++ <&CLK_mpll_216m_div4>, ++ <&CLK_mpll_216m_div8>, ++ <&CLK_mpll_288m>, ++ <&CLK_mpll_288m_div2>, ++ <&CLK_mpll_288m_div4>, ++ <&CLK_mpll_288m_div8>, ++ <&CLK_mpll_345m>, ++ <&CLK_mpll_432m>, ++ <&CLK_mpll_86m>, ++ <&CLK_mpll_86m_div16>, ++ <&CLK_mpll_86m_div2>, ++ <&CLK_mpll_86m_div4>, ++ <&CLK_mspi>, ++ <&CLK_mspi0>, ++ <&CLK_mspi0_p>, ++ <&CLK_mspi1>, ++ <&CLK_mspi1_p>, ++ <&CLK_nlm>, ++ <&CLK_ns>, ++ <&CLK_odclk>, ++ <&CLK_pad2isp_sr_pclk>, ++ <&CLK_pm_riu_w_clk_in>, ++ <&CLK_pm_sleep>, ++ <&CLK_pwr_ctl>, ++ <&CLK_riu>, ++ <&CLK_riu_hemcu_gp>, ++ <&CLK_riu_mcu_if>, ++ <&CLK_riu_mipi_gp>, ++ <&CLK_riu_nogating>, ++ <&CLK_riu_pm>, ++ <&CLK_riu_sc_gp>, ++ <&CLK_riu_vhe_gp>, ++ <&CLK_riu_w_clk_hemcu_gp>, ++ <&CLK_riu_w_clk_in>, ++ <&CLK_riu_w_clk_mcu_if_gp>, ++ <&CLK_riu_w_clk_mipi_if_gp>, ++ <&CLK_riu_w_clk_sc_gp>, ++ <&CLK_riu_w_clk_top>, ++ <&CLK_riu_w_clk_vhe_gp>, ++ <&CLK_riubrdg>, ++ <&CLK_rmii_buf>, ++ <&CLK_rtc>, ++ <&CLK_rtc_32k>, ++ <&CLK_rtc_32k_div4>, ++ <&CLK_sar>, ++ <&CLK_sd>, ++ <&CLK_sdio>, ++ <&CLK_sdio_p>, ++ <&CLK_spi>, ++ <&CLK_spi_pm>, ++ <&CLK_sr_mclk>, ++ <&CLK_tck>, ++ <&CLK_tck_buf>, ++ <&CLK_uart0>, ++ <&CLK_uart1>, ++ <&CLK_upll>, ++ <&CLK_upll_320m>, ++ <&CLK_upll_384m>, ++ <&CLK_utmi>, ++ <&CLK_utmi_160m>, ++ <&CLK_utmi_160m_div4>, ++ <&CLK_utmi_160m_div5>, ++ <&CLK_utmi_160m_div8>, ++ <&CLK_utmi_192m>, ++ <&CLK_utmi_192m_div4>, ++ <&CLK_utmi_240m>, ++ <&CLK_utmi_480m>, ++ <&CLK_vhe>, ++ <&CLK_vhe_vpu>, ++ <&CLK_xtali>, ++ <&CLK_xtali_12m>, ++ <&CLK_xtali_12m_div12>, ++ <&CLK_xtali_12m_div128>, ++ <&CLK_xtali_12m_div16>, ++ <&CLK_xtali_12m_div2>, ++ <&CLK_xtali_12m_div4>, ++ <&CLK_xtali_12m_div40>, ++ <&CLK_xtali_12m_div64>, ++ <&CLK_xtali_12m_div8>, ++ <&CLK_xtali_24m>, ++ <&CLK_xtali_sc_gp>; ++ clock-count = <184>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity6b0-clks_simple.dtsi b/arch/arm/boot/dts/infinity6b0-clks_simple.dtsi +new file mode 100755 +index 000000000000..d02516b0ff31 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-clks_simple.dtsi +@@ -0,0 +1,651 @@ ++/* generated manually for fast booting */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi_480m: CLK_utmi_480m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_mpll_345m: CLK_mpll_345m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <345000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_xtali_24m>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++ auto-enable = <1>; ++}; ++ ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_sd: CLK_sd { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SD_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SD_OFFSET ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++}; ++ ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++ auto-enable = <1>; ++}; ++ ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, ++ <&CLK_VOID>, ++ <&CLK_aesdma>, ++ <&CLK_armpll_37p125m>, ++ <&CLK_axi2x>, ++ <&CLK_bdma>, ++ <&CLK_bist>, ++ <&CLK_bist_sc_gp>, ++ <&CLK_bist_vhe_gp>, ++ <&CLK_ccir_in_clk>, ++ <&CLK_cpupll_clk>, ++ <&CLK_csi2_mac_p>, ++ <&CLK_csi_mac>, ++ <&CLK_ddr_syn>, ++ <&CLK_ddrpll_clk>, ++ <&CLK_dip>, ++ <&CLK_emac_ahb>, ++ <&CLK_emac_rx>, ++ <&CLK_emac_rx_ref>, ++ <&CLK_emac_testrx125_in_lan>, ++ <&CLK_emac_tx>, ++ <&CLK_emac_tx_ref>, ++ <&CLK_eth_buf>, ++ <&CLK_fclk1>, ++ <&CLK_fclk1_p>, ++ <&CLK_fclk2>, ++ <&CLK_fclk2_p>, ++ <&CLK_fuart>, ++ <&CLK_fuart0_synth_in>, ++ <&CLK_fuart0_synth_out>, ++ <&CLK_gop0>, ++ <&CLK_gop1>, ++ <&CLK_gop2>, ++ <&CLK_hemcu_216m>, ++ <&CLK_imi>, ++ <&CLK_ir>, ++ <&CLK_isp>, ++ <&CLK_isp_p>, ++ <&CLK_jpe>, ++ <&CLK_live>, ++ <&CLK_live_pm>, ++ <&CLK_lpll_clk>, ++ <&CLK_lpll_clk_div2>, ++ <&CLK_lpll_clk_div4>, ++ <&CLK_lpll_clk_div8>, ++ <&CLK_mac_lptx>, ++ <&CLK_mcu>, ++ <&CLK_mcu_p>, ++ <&CLK_mcu_pm>, ++ <&CLK_mcu_pm_p>, ++ <&CLK_miic0>, ++ <&CLK_miic1>, ++ <&CLK_miu>, ++ <&CLK_miu2x>, ++ <&CLK_miu2x_p>, ++ <&CLK_miu_bach>, ++ <&CLK_miu_bdma>, ++ <&CLK_miu_cmdq>, ++ <&CLK_miu_dig>, ++ <&CLK_miu_emac>, ++ <&CLK_miu_fcie>, ++ <&CLK_miu_ff>, ++ <&CLK_miu_file>, ++ <&CLK_miu_gop>, ++ <&CLK_miu_isp_dma>, ++ <&CLK_miu_isp_dnr>, ++ <&CLK_miu_isp_rot>, ++ <&CLK_miu_isp_sta>, ++ <&CLK_miu_ive>, ++ <&CLK_miu_jpe0>, ++ <&CLK_miu_jpe1>, ++ <&CLK_miu_mfeh>, ++ <&CLK_miu_p>, ++ <&CLK_miu_rec>, ++ <&CLK_miu_sc1_dbg>, ++ <&CLK_miu_sc1_frm>, ++ <&CLK_miu_sc1_snp>, ++ <&CLK_miu_sc1_snpi>, ++ <&CLK_miu_sc2_frm>, ++ <&CLK_miu_sc2_snpi>, ++ <&CLK_miu_sc3_frm>, ++ <&CLK_miu_sc_crop>, ++ <&CLK_miu_sc_dnr>, ++ <&CLK_miu_sc_dnr_sad>, ++ <&CLK_miu_sc_gp>, ++ <&CLK_miu_sc_gp_p>, ++ <&CLK_miu_sdio>, ++ <&CLK_miu_uhc0>, ++ <&CLK_miu_urdma>, ++ <&CLK_miu_vhe>, ++ <&CLK_miu_vhe_gp>, ++ <&CLK_miu_vhe_gp_p>, ++ <&CLK_miu_xd2miu>, ++ <&CLK_miupll_clk>, ++ <&CLK_mpll_123m>, ++ <&CLK_mpll_123m_div2>, ++ <&CLK_mpll_144m>, ++ <&CLK_mpll_144m_div2>, ++ <&CLK_mpll_144m_div4>, ++ <&CLK_mpll_172m>, ++ <&CLK_mpll_216m>, ++ <&CLK_mpll_216m_div2>, ++ <&CLK_mpll_216m_div4>, ++ <&CLK_mpll_216m_div8>, ++ <&CLK_mpll_288m>, ++ <&CLK_mpll_288m_div2>, ++ <&CLK_mpll_288m_div4>, ++ <&CLK_mpll_288m_div8>, ++ <&CLK_mpll_345m>, ++ <&CLK_mpll_432m>, ++ <&CLK_mpll_86m>, ++ <&CLK_mpll_86m_div16>, ++ <&CLK_mpll_86m_div2>, ++ <&CLK_mpll_86m_div4>, ++ <&CLK_mspi>, ++ <&CLK_mspi0>, ++ <&CLK_mspi0_p>, ++ <&CLK_mspi1>, ++ <&CLK_mspi1_p>, ++ <&CLK_nlm>, ++ <&CLK_ns>, ++ <&CLK_odclk>, ++ <&CLK_pad2isp_sr_pclk>, ++ <&CLK_pm_riu_w_clk_in>, ++ <&CLK_pm_sleep>, ++ <&CLK_pwr_ctl>, ++ <&CLK_riu>, ++ <&CLK_riu_hemcu_gp>, ++ <&CLK_riu_mcu_if>, ++ <&CLK_riu_mipi_gp>, ++ <&CLK_riu_nogating>, ++ <&CLK_riu_pm>, ++ <&CLK_riu_sc_gp>, ++ <&CLK_riu_vhe_gp>, ++ <&CLK_riu_w_clk_hemcu_gp>, ++ <&CLK_riu_w_clk_in>, ++ <&CLK_riu_w_clk_mcu_if_gp>, ++ <&CLK_riu_w_clk_mipi_if_gp>, ++ <&CLK_riu_w_clk_sc_gp>, ++ <&CLK_riu_w_clk_top>, ++ <&CLK_riu_w_clk_vhe_gp>, ++ <&CLK_riubrdg>, ++ <&CLK_rmii_buf>, ++ <&CLK_rtc>, ++ <&CLK_rtc_32k>, ++ <&CLK_rtc_32k_div4>, ++ <&CLK_sar>, ++ <&CLK_sd>, ++ <&CLK_sdio>, ++ <&CLK_sdio_p>, ++ <&CLK_spi>, ++ <&CLK_spi_pm>, ++ <&CLK_sr_mclk>, ++ <&CLK_tck>, ++ <&CLK_tck_buf>, ++ <&CLK_uart0>, ++ <&CLK_uart1>, ++ <&CLK_upll>, ++ <&CLK_upll_320m>, ++ <&CLK_upll_384m>, ++ <&CLK_utmi>, ++ <&CLK_utmi_160m>, ++ <&CLK_utmi_160m_div4>, ++ <&CLK_utmi_160m_div5>, ++ <&CLK_utmi_160m_div8>, ++ <&CLK_utmi_192m>, ++ <&CLK_utmi_192m_div4>, ++ <&CLK_utmi_240m>, ++ <&CLK_utmi_480m>, ++ <&CLK_vhe>, ++ <&CLK_vhe_vpu>, ++ <&CLK_xtali>, ++ <&CLK_xtali_12m>, ++ <&CLK_xtali_12m_div12>, ++ <&CLK_xtali_12m_div128>, ++ <&CLK_xtali_12m_div16>, ++ <&CLK_xtali_12m_div2>, ++ <&CLK_xtali_12m_div4>, ++ <&CLK_xtali_12m_div40>, ++ <&CLK_xtali_12m_div64>, ++ <&CLK_xtali_12m_div8>, ++ <&CLK_xtali_24m>, ++ <&CLK_xtali_sc_gp>; ++ clock-count = <184>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity6b0-fpga.dts b/arch/arm/boot/dts/infinity6b0-fpga.dts +new file mode 100755 +index 000000000000..0aa892a93ed4 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-fpga.dts +@@ -0,0 +1,89 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6b0-fpga.dtsi" ++ ++/ { ++ model = "INFINITY6B0 FPGA"; ++ compatible = "sstar,infinity6b0"; ++ ++ /* memory { ++ reg = <0x20000000 0x06000000>; ++ }; */ ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0xfee0000 mma_heap=mma_heap_name0,miu=0,sz=0x5000000,max_start_off=0x28000000 mma_memblock_remove=1"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x00800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ rootfsp { ++ reg= <0x27000000 0x00400000>; ++ no-map; ++ }; ++ datap { ++ reg= <0x27400000 0x00400000>; ++ no-map; ++ }; ++ extp { ++ reg= <0x27800000 0x00800000>; ++ no-map; ++ }; ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6b0-fpga.dtsi b/arch/arm/boot/dts/infinity6b0-fpga.dtsi +new file mode 100755 +index 000000000000..bfa0b1457c53 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-fpga.dtsi +@@ -0,0 +1,518 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity6b0/irqs.h> ++#include <../../../../drivers/sstar/include/infinity6b0/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ ++ vpe: vpe { ++ compatible = "sigmastar,vpe"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ DigitalZoom-Dropmode = <1>; ++ interrupts = , , , ; ++ }; ++ ++ venc { ++ compatible = "sstar,venc"; ++ reg = <0x1F345200 0x800>, <0x1F226A00 0x100>, <0x1F203C00 0x100>, <0x1F207800 0x100>; ++ reg-names = "vpu-bit", "venc-brige", "hw-uart0", "hw-uart1"; ++ interrupts = ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_vhe_vpu>; ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "sstar,sclhvsp1_i6"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "sstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "sstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "sstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "sstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "sstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "sstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ interrupts = , , , ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ clocks = <&CLK_dip>; ++ status = "ok"; ++ }; ++ ++/* ++ emac { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ status = "ok"; ++ }; ++*/ ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++ // reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x00000000 0x000>; ++ pad = <0x1F203C3C 0x0004 0x0004>; // pad selection from 0x0001 ++ phy-handle = <&phy0>; ++ max-speed = <10>; ++ mdio_path = <0>; // force internal mdio ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ // phy-mode = "rmii"; ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "disabled"; ++ }; ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++ status = "ok"; ++ clock-frequency-index = <5>; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ status = "ok"; ++ }; ++ ++ vif: vif { ++ compatible = "sstar,vif"; ++ status = "ok"; ++ reg = <0x1F260800 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F207800 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>, <0x1F203C00 0x200>; ++ clocks = <&CLK_sr_mclk>; ++ interrupts = ; ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <2>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <2>; ++ vif_sr0_rst_mode = <2>; ++ vif_sr0_hvsync_mode = <1>; ++ vif_sr0_pck_mode = <1>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F2C4000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F2C4000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "sstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++ status = "ok"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ clocks = <&CLK_aesdma>; ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sigmastar,gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&CLK_dip>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>; ++ status = "ok"; ++ }; ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ interrupts = ; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <11>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ Sstar-udc { ++ compatible = "sstar,infinity-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6b0/reg_clks.h> ++ #include "infinity6b0-clks.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity6b0-ssc009a-s01a.dts b/arch/arm/boot/dts/infinity6b0-ssc009a-s01a.dts +new file mode 100755 +index 000000000000..7c089f96281a +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-ssc009a-s01a.dts +@@ -0,0 +1,85 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6b0.dtsi" ++ ++/ { ++ model = "INFINITY6B0 SSC009A-S01A QFN88"; ++ compatible = "sstar,infinity6b0"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ soc { ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <4>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <3>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <0>; ++ vif_sr0_pck_mode = <0>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <2>; ++ ++ }; ++ ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6b0-ssc009b-s01a.dts b/arch/arm/boot/dts/infinity6b0-ssc009b-s01a.dts +new file mode 100755 +index 000000000000..41d023833cbf +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-ssc009b-s01a.dts +@@ -0,0 +1,93 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6b0.dtsi" ++ ++/ { ++ model = "INFINITY6B0 SSC009B-S01A QFN128"; ++ compatible = "sstar,infinity6b0"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ soc { ++ ++ rtcpwc { ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <2>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <0>; ++ vif_sr0_pck_mode = <0>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <1>; ++ }; ++ ++ core_voltage { ++ vid_width = <2>; ++ vid_gpios = ; ++ vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 ++ }; ++ ++ sdmmc { ++ slotnum = <2>; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6b0-ssc009d-s01a.dts b/arch/arm/boot/dts/infinity6b0-ssc009d-s01a.dts +new file mode 100755 +index 000000000000..52b9b70f26f9 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0-ssc009d-s01a.dts +@@ -0,0 +1,90 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity6b0.dtsi" ++ ++/ { ++ model = "INFINITY6B0 SSC009D-S01A QFN88"; ++ compatible = "sstar,infinity6b0"; ++ ++ /* memory setting will be replaced with LX_MEM*/ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ /* this cmdline will be replaced with uboot bootargs*/ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc cma=16m"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /*cma0 { ++ compatible = "shared-dma-pool"; ++ size = <0x400000>; ++ reusable; ++ alignment = <0x1000>; ++ linux,cma-default; ++ };*/ ++ }; ++ ++ soc { ++ ++ rtcpwc { ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ }; ++ ++ vif { ++ vif_sr0_par_mode = <4>; ++ vif_sr0_mipi_mode = <2>; ++ vif_sr0_bt656_mode = <3>; ++ vif_sr0_mclk_mode = <1>; ++ vif_sr0_pdn_mode = <1>; ++ vif_sr0_rst_mode = <1>; ++ vif_sr0_parallel_rst_mode = <2>; ++ vif_sr0_parallel_pdn_mode = <2>; ++ vif_sr0_mipi_rst_mode = <1>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_hvsync_mode = <0>; ++ vif_sr0_pck_mode = <0>; ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <2>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <2>; ++ }; ++ ++ csi { ++ sr0_mipi_mode = <2>; ++ ++ }; ++ ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6b0.dtsi b/arch/arm/boot/dts/infinity6b0.dtsi +new file mode 100755 +index 000000000000..46c274e26f66 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6b0.dtsi +@@ -0,0 +1,788 @@ ++/* ++* infinity6b0.dtsi- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity6b0/irqs.h> ++#include <../../../../drivers/sstar/include/infinity6b0/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++#include <../../../../include/generated/autoconf.h> ++#ifdef CONFIG_CAM_CLK ++#include <../../../../drivers/sstar/include/infinity6b0/camclk.h> ++#endif ++ ++/ { ++ camclk: camclkinit { ++ compatible = "camdriver,camclkinit"; ++ status = "ok"; ++ }; ++ camclk { ++ compatible = "camdriver,camclk"; ++ status = "ok"; ++ }; ++ camclkut { ++ compatible = "camdriver,camclkut"; ++ status = "ok"; ++ }; ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++#ifndef CONFIG_CAM_CLK ++ clocks = <&CLK_cpupll_clk>; ++#endif ++ reg = <0x0>; ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 1000000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "sstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++*/ ++#ifndef __DTS_DUALOS__ ++ venc { ++ compatible = "sstar,venc"; ++ reg = <0x1F345200 0x800>, <0x1F2C5200 0x100>, <0x1F203C00 0x100>, <0x1F207800 0x100>; ++ reg-names = "vpu-bit", "venc-brige", "hw-uart0", "hw-uart1"; ++ interrupts = ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_vhe_vpu>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ vpe: vpe { ++ compatible = "sigmastar,vpe"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ DigitalZoom-Dropmode = <1>; ++ interrupts = , , , ; ++ }; ++ ++ vip: vip { ++ compatible = "sstar,vip"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ttl-mode = <1>; ++ jtag-mode = <0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#else ++ clocks = <&CLK_odclk>; ++#endif ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ //Reg = <0x1F224000 0x200>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#else ++ clocks = <&CLK_odclk>; ++#endif ++ interrupts = , , , ; ++ }; ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ clock-frequency-index = <5>; ++ //clk-pad = ; ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ //isp-flag = <0>; ++ }; ++ csi: csi { ++ compatible = "sstar,csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1202>,<0x1203>,<0x1204>,<0x1038>,<0x101e>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ vif: vif { ++ compatible = "sstar,vif"; ++ status = "ok"; ++ reg = <0x1F260800 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F207800 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>, <0x1F203C00 0x200>; ++ clocks = <&CLK_sr_mclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ,; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ }; ++ ++ jpe0: jpe@0x1F2C4000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F2C4000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sigmastar,gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&CLK_dip>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ ++ dip { ++ compatible = "sstar,dip"; ++ clocks = <&CLK_dip>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++#endif ++ uart0: uart0@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++ dma = <1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; //for MII & RMII ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; //for MII ++ //reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0 0>; // for RMII ++ pad = <0x1F203DD4 0x0100 0x0100>; ++ phy-handle = <&phy0>; ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ phy-mode = "mii"; //for MII ++ //phy-mode = "rmii";//for RMII ++ }; ++ }; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ quadread = <0>; ++ status = "ok"; ++ }; ++/* ++ nandflash { ++ compatible = "ms-nand"; ++ clocks = <&CLK_VOID>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks = <&CLK_VOID>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++*/ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ Sstar-udc { ++ compatible = "sstar,infinity-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ spi0@0{ ++ compatible = "sstar,mspi"; ++ mspi-group = <0>; ++ #ifdef CONFIG_CAM_CLK ++ camclk = ,; ++ #else ++ clocks = <&CLK_mspi0>,<&CLK_mspi>; ++ #endif ++ reg = <0x1F222000 0x200>; ++ interrupts = ; ++ use-dma = <1>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ spi1@1{ ++ compatible = "sstar,mspi"; ++ mspi-group = <1>; ++ #ifdef CONFIG_CAM_CLK ++ camclk = ,; ++ #else ++ clocks = <&CLK_mspi1>,<&CLK_mspi>; ++ #endif ++ reg = <0x1F222200 0x200>; ++ interrupts = ; ++ use-dma = <0>; ++ //pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++ interrupts=; ++ amp-gpio = ; // QFN88: PAD_FUART_TX QFN128: PAD_PM_GPIO0 ++ clocks = <&CLK_upll_384m>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ ++ /* ++ 0: OFF ++ 1: PAD_GPIO4 ~ PAD_GPIO6 (QFN128) ++ 2: PAD_SD1_IO4 ~ PAD_SD1_IO6 ++ 3: PAD_SD1_IO8, PAD_UART0_RX, PAD_UART0_TX ++ */ ++ digmic-padmux = <1>; ++ ++ /* ++ 0: OFF ++ 1: PAD_GPIO0 ~ PAD_GPIO3 (QFN128) ++ 2: PAD_SD1_IO0 ~ PAD_SD1_IO3 ++ 3: PAD_SPI1_CZ, PAD_SPI1_CK, PAD_SPI1_DI, PAD_SPI1_DO ++ */ ++ i2s-padmux = <1>; ++ ++ keep-i2s-clk = <0>; ++ dmic-bck-mode = <0>; //0:4M, 1:2M ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; // IP_SD: IP_SDIO: ++#else ++ clocks =<&CLK_sd>; // IP_SD:<&CLK_sd> IP_SDIO:<&CLK_sdio> ++#endif ++ ip-select = <0>; // 0:IP_SD 1:IP_SDIO ++ pad-select = <0>; // 0:PAD_SD 1:PAD_SD1 ++ interrupts = ; ++ bus-width = <4>; ++ max-clks = <2>; // 0:48M 1:43M 2:40M 3:36M 4:32M 5:20M 6:12M 7:300K ++ clk-driving = <0>; ++ cmd-driving = <0>; ++ data-driving = <0>; ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <1>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; // 0:IP_SD 1:IP_SDIO ++ slot-pad-orders = <0>,<1>,<2>; // 0:PAD_SD 1:PAD_SD1 ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-cdzs-gpios = ,,<0>; ++ slot-pwr-gpios = ,,<0>; ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ ++ interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_FCIE IRQ_TYPE_LEVEL_HIGH>, // No need to change. ++ <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, // No need to change. ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>, // CDZ int for Slot 0, default is for PAD_PM_SD_CDZ ++ <&ms_gpi_intc 42>, // CDZ int for Slot 1, default is for PAD_SD1_IO6 ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>; // CDZ int for Slot 2, None. ++ interrupt-names = "mie0_irq", "mie1_irq", "cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"; // No need to change. ++ clocks = <&CLK_sd>,<&CLK_sdio>,<&CLK_VOID>; // No need to change. ++ ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ interrupts=; ++ clocks = <&CLK_aesdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_miu_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "disabled"; ++ }; ++ ++ rtc { ++ compatible = "sstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ rtcpwc { ++ compatible = "sstar,infinity-rtcpwc"; ++ reg = <0x1F006800 0x200>; ++ interrupts=; //need to check ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++#if 0 ++ tm_sec; /*¬í - ¨ú­È°Ï¶¡¬°[0, 59]*/ ++ tm_min; /*¤À - ¨ú­È°Ï¶¡¬°[0, 59]*/ ++ tm_hour; /*®É - ¨ú­È°Ï¶¡¬°[0, 23]*/ ++ tm_mday; /*¤é - ¨ú­È°Ï¶¡¬°[1, 31]*/ ++ tm_mon; /*¤ë¥÷ - ¨ú­È°Ï¶¡¬°[0, 11]*/ ++ tm_year; /*¦~¥÷ - ¨ä­È¬°1900¦~¦Ü¤µ¦~¼Æ*/ ++ tm_wday; /*¬P´Á - ¨ú­È°Ï¶¡[0, 6]¡A0¥Nªí¬P´Á¤Ñ¡A1¥Nªí¬P´Á1¡A¥H¦¹Ãþ±À*/ ++ tm_yday; /*±q¨C¦~ªº1¤ë1¤é¶}©lªº¤Ñ¼Æ-¨ú­È°Ï¶¡¬°[0, 365]¡A0¥Nªí1¤ë1¤é*/ ++ default_date = <0 0 0 5 10 83 6 0>; ++#endif ++ status = "disabled"; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "ok"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "ok"; ++ }; ++ ++ ircut { ++ compatible = "sstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pm_intc>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F003400 0x600>; ++ interrupts = ; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <11>; ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ gpioi2c { ++ compatible = "sstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "ok"; ++ }; ++ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6b0/reg_clks.h> ++#ifndef __DTS_DUALOS__ ++ #include "infinity6b0-clks.dtsi" ++#else ++ #include "infinity6b0-clks_simple.dtsi" ++#endif ++ ++}; ++ +diff --git a/arch/arm/boot/dts/infinity6e-alkaid-fpga-256.dts b/arch/arm/boot/dts/infinity6e-alkaid-fpga-256.dts +new file mode 100755 +index 000000000000..35cc4def3212 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-alkaid-fpga-256.dts +@@ -0,0 +1,89 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e-fpga.dtsi" ++ ++/ { ++ model = "INFINITY6E FPGA"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x0F000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0xfee0000 mma_heap=mma_heap_name0,miu=0,sz=0xA000000,max_start_off=0x28000000 mma_memblock_remove=1; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++}; ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ rootfsp { ++ reg= <0x27000000 0x00400000>; ++ no-map; ++ }; ++ datap { ++ reg= <0x27400000 0x00400000>; ++ no-map; ++ }; ++ extp { ++ reg= <0x27800000 0x00800000>; ++ no-map; ++ }; ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +\ No newline at end of file +diff --git a/arch/arm/boot/dts/infinity6e-alkaid-fpga.dts b/arch/arm/boot/dts/infinity6e-alkaid-fpga.dts +new file mode 100755 +index 000000000000..ab5c99e30e92 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-alkaid-fpga.dts +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e-fpga.dtsi" ++ ++/ { ++ model = "INFINITY6E FPGA"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-amp.dts b/arch/arm/boot/dts/infinity6e-amp.dts +new file mode 100755 +index 000000000000..b7b48519b008 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-amp.dts +@@ -0,0 +1,63 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#define __DTS_AMP__ ++ ++#include "infinity6e.dtsi" ++ ++/ { ++ model = "INFINITY6E FPGA"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x05000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc initrd=0x20E00000,0x96000 rootwait=1 LX_MEM=0x5000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000,mem=80m,maxcpus=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ /*!! wait correct info to enable this feature. ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ vid_default = <1>; //2b'00 ++ };*/ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-cardv-banya-DR0011.dts b/arch/arm/boot/dts/infinity6e-cardv-banya-DR0011.dts +new file mode 100755 +index 000000000000..48c337ce6dd1 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-cardv-banya-DR0011.dts +@@ -0,0 +1,255 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++ ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E BANYA-DR0011"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 950000 ++ 1100000 950000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 4lane setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <0 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ /* mipi0 4lane setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <0>; ++ vif_sr1_mclk_mode = <2>; ++ vif_sr1_rst_mode = <2>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <0>; ++ sensorif_grp2_i2c = <1>; ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <2>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ * 2 -> PAD_GPIO0, PAD_GPIO1 ++ * 3 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ i2c-speed = <2>; ++ /* ++ * padmux: 1 -> PAD_SR1_IO18, PAD_SR1_IO19 ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 4 -> PAD_PM_I2CM_SCL, PAD_PM_I2CM_SDA ++ * 5 -> PAD_PM_GPIO0, PAD_PM_GPIO1 ++ */ ++ i2c-padmux = <4>; ++ Injoinic@30 { ++ compatible = "Injoinic,ip6303"; ++ reg = <0x30>; ++ //interrupts = <1>; ++ //interrupt-parent = <&intcmux4>; ++ pmu_irq_gpio = ; ++ DC1_VSET = <1000>;/* corepower */ ++ DC2_VSET = <1500>;/* ddram3 */ ++ DC3_VSET = <3300>;/* VDD_3V3 */ ++ LDO2_VSET = <1250>;/* AHD1V2 */ ++ LDO3_VSET = <3300>;/* AHD3V3 */ ++ LDO4_VSET = <1200>;/* unused */ ++ LDO5_VSET = <1800>;/* VDD_1V8 */ ++ //interrupt-controller; ++ //#interrupt-cells = <1>; ++ //maxim,tsc-irq = <0>; ++ }; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++ amp-gpio = ; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<1>,<0>; ++ slot-pad-orders = <0>,<2>,<2>; ++ slot-sdio-use = <0>,<1>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ #io-channel-cells = <1>; ++ status = "ok"; ++ }; ++ ++ /* ++ adc0: adc@4003b000 { ++ compatible = "fsl,vf610-adc"; ++ reg = <0x4003b000 0x1000>; ++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clks VF610_CLK_ADC0>; ++ clock-names = "adc"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ fsl,adck-max-frequency = <30000000>, <40000000>,<20000000>; ++ }; ++ */ ++ ++ #include ++ adc-keys { ++ compatible = "adc-keys"; ++ //io-channels = <&sar 0>; ++ io-channels = <0>; ++ io-channel-names = "buttons"; ++ poll-interval=<100>; ++ keyup-threshold-microvolt = <1024000>; ++ ++ button-up { ++ label = "Volume Up"; ++ linux,code = ; ++ press-threshold-microvolt = <512000>; ++ }; ++ ++ button-down { ++ label = "Volume Down"; ++ linux,code = ; ++ press-threshold-microvolt = <870000>; ++ }; ++ ++ button-enter { ++ label = "Enter"; ++ linux,code = ; ++ press-threshold-microvolt = <960000>; ++ }; ++ button-menu { ++ label = "Menu"; ++ linux,code = ; ++ press-threshold-microvolt = <990000>; ++ }; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6e/reg_clks.h> ++ CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ auto-enable = <1>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-cardv-demo-board.dts b/arch/arm/boot/dts/infinity6e-cardv-demo-board.dts +new file mode 100755 +index 000000000000..65b3eb2d1773 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-cardv-demo-board.dts +@@ -0,0 +1,276 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++ ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux-cardv.dtsi" ++#define SNR_PAD_24PIN_IMX415 0 ++ ++/ { ++ model = "INFINITY6E CARDV DEMO"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 950000 ++ 1100000 950000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 4lane setting */ ++ #if SNR_PAD_24PIN_IMX415 ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ #else ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 1 3 0 4>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ #endif ++ ++ /* mipi0 4lane setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <2>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <0>; ++ vif_sr1_mclk_mode = <2>; ++ vif_sr1_rst_mode = <2>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <0>; ++ sensorif_grp2_i2c = <1>; ++ }; ++ ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ ttl-16bit-mode = <3>; //1~4 mode ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ power-enable-pad = ; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <2>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ * 2 -> PAD_GPIO0, PAD_GPIO1 ++ * 3 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ i2c-speed = <2>; ++ /* ++ * padmux: 1 -> PAD_SR1_IO18, PAD_SR1_IO19 ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 4 -> PAD_PM_I2CM_SCL, PAD_PM_I2CM_SDA ++ * 5 -> PAD_PM_GPIO0, PAD_PM_GPIO1 ++ */ ++ i2c-padmux = <4>; ++ Injoinic@30 { ++ compatible = "Injoinic,ip6303"; ++ reg = <0x30>; ++ //interrupts = <1>; ++ //interrupt-parent = <&intcmux4>; ++ pmu_irq_gpio = ; ++ DC1_VSET = <1000>;/* corepower */ ++ DC2_VSET = <1500>;/* ddram3 */ ++ DC3_VSET = <3300>;/* VDD_3V3 */ ++ LDO2_VSET = <1250>;/* AHD1V2 */ ++ LDO3_VSET = <3300>;/* AHD3V3 */ ++ LDO4_VSET = <1200>;/* unused */ ++ LDO5_VSET = <1800>;/* VDD_1V8 */ ++ //interrupt-controller; ++ //#interrupt-cells = <1>; ++ //maxim,tsc-irq = <0>; ++ }; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++ amp-gpio = ; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<1>,<0>; ++ slot-pad-orders = <0>,<2>,<2>; ++ slot-sdio-use = <0>,<1>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ #io-channel-cells = <1>; ++ status = "ok"; ++ }; ++ ++ #include ++ adc-keys { ++ compatible = "adc-keys"; ++ //io-channels = <&sar 0>; ++ io-channels = <0>; ++ io-channel-names = "buttons"; ++ poll-interval=<100>; ++ keyup-threshold-microvolt = <3100000>; ++ ++ button-up { ++ label = "Up"; ++ linux,code = ; ++ press-threshold-microvolt = <2475000>; ++ }; ++ ++ button-down { ++ label = "Down"; ++ linux,code = ; ++ press-threshold-microvolt = <1980000>; ++ }; ++ button-left { ++ label = "LEFT"; ++ linux,code = ; ++ press-threshold-microvolt = <1570000>; ++ }; ++ ++ button-right { ++ label = "RIGHT"; ++ linux,code = ; ++ press-threshold-microvolt = <1050000>; ++ }; ++ button-menu { ++ label = "Menu"; ++ linux,code = ; ++ press-threshold-microvolt = <500000>; ++ }; ++ button-enter { ++ label = "OK"; ++ linux,code = ; ++ press-threshold-microvolt = <000000>; ++ }; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6e/reg_clks.h> ++ CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ auto-enable = <1>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-clks.dtsi b/arch/arm/boot/dts/infinity6e-clks.dtsi +new file mode 100755 +index 000000000000..2ccee6cad968 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-clks.dtsi +@@ -0,0 +1,1662 @@ ++/* generated by CLK_DT_GEN_5.1 */ ++/* CLK FILENAME: I6e/iNfinity6e_Clock_Table_0903.xls */ ++/* REG FILENAME: I6e/iNfinity6e_reg_CLKGEN.xls, I6e/iNfinity6e_reg_pm_sleep.xls, I6e/iNfinity6e_reg_block.xls, I6e/iNfinity6e_reg_chiptop.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi_480m: CLK_utmi_480m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <384000000>; ++}; ++ ++CLK_mpll_345m: CLK_mpll_345m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <345000000>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <320000000>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <240000000>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <192000000>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172800000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <160000000>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123400000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86400000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <108000000>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <400000000>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <2133000000>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <100000000>; ++}; ++ ++CLK_ven_pll: CLK_ven_pll { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++CLK_ven_pll_div6: CLK_ven_pll_div6 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <104000000>; ++}; ++ ++CLK_lpll_div2: CLK_lpll_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++}; ++ ++CLK_lpll_div4: CLK_lpll_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++}; ++ ++CLK_lpll_div8: CLK_lpll_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12500000>; ++}; ++ ++CLK_armpll_37p125m: CLK_armpll_37p125m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <37500000>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi0_p: CLK_mspi0_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mspi1_p: CLK_mspi1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mspi1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++/* ++CLK_fclk2_p: CLK_fclk2_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++*/ ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++}; ++ ++/* ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++*/ ++CLK_gop0: CLK_gop0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++/* ++CLK_gop1: CLK_gop1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop2: CLK_gop2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++*/ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++}; ++ ++CLK_fro: CLK_fro { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <48000000>; ++}; ++ ++CLK_fro_div2: CLK_fro_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fro>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_fro_div8: CLK_fro_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fro>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_fro_div16: CLK_fro_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fro>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "sstar,complex-clock"; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "sstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_bach: CLK_bach { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_384m>; ++ reg = ; ++ //mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ //mux-width = <2>; ++ gate-shift = <7>; //0+REG_CKG_MIU_OFFSET ++ //glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ //auto-enable = <0>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_miu_boot: CLK_miu_boot { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_miu>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_spi_arb: CLK_spi_arb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_miu_p>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_ARB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_ARB_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_ARB_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_flash: CLK_spi_flash { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div8>,<&CLK_ven_pll_div6>,<&CLK_mpll_216m_div4>,<&CLK_mpll_288m_div4>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_FLASH_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SPI_FLASH_OFFSET ++ glitch-shift = <5>; //5+REG_CKG_SPI_FLASH_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pwm: CLK_pwm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_PWM_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_PWM_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++ auto-enable = <0>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++ auto-enable = <0>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++ auto-enable = <0>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_mspi: CLK_mspi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET ++ mux-width = <1>; ++ gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++ auto-enable = <0>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++ auto-enable = <0>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_miic2: CLK_miic2 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MIIC2_OFFSET ++ mux-width = <2>; ++ gate-shift = <12>; //0+REG_CKG_MIIC2_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_pwr_ctl: CLK_pwr_ctl { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_PWR_CTL_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_PWR_CTL_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr00_mclk: CLK_sr00_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_div2>,<&CLK_lpll_div4>,<&CLK_lpll_div8>,<&CLK_armpll_37p125m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR00_MCLK_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SR00_MCLK_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_sr01_mclk: CLK_sr01_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_div2>,<&CLK_lpll_div4>,<&CLK_lpll_div8>,<&CLK_armpll_37p125m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SR01_MCLK_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_SR01_MCLK_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_sr1_mclk: CLK_sr1_mclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_288m_div8>,<&CLK_xtali_24m>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_lpll_clk>,<&CLK_lpll_div2>,<&CLK_lpll_div4>,<&CLK_lpll_div8>,<&CLK_armpll_37p125m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR1_MCLK_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SR1_MCLK_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_bist_pm: CLK_bist_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_bist_ipu_gp: CLK_bist_ipu_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_IPU_GP_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_BIST_IPU_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ipu: CLK_ipu { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_IPU_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_IPU_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_ipuff: CLK_ipuff { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_utmi_240m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_IPUFF_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_IPUFF_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_bist_usb30_gp: CLK_bist_usb30_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_USB30_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_USB30_GP_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_csi_mac_lptx_top_i_m00: CLK_csi_mac_lptx_top_i_m00 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_LPTX_TOP_I_M00_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_LPTX_TOP_I_M00_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_csi_mac_top_i_m00: CLK_csi_mac_top_i_m00 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_CSI_MAC_TOP_I_M00_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_CSI_MAC_TOP_I_M00_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_ns_top_i_m00: CLK_ns_top_i_m00 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_TOP_I_M00_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_NS_TOP_I_M00_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_csi_mac_lptx_top_i_m01: CLK_csi_mac_lptx_top_i_m01 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_CSI_MAC_LPTX_TOP_I_M01_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_CSI_MAC_LPTX_TOP_I_M01_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_csi_mac_top_i_m01: CLK_csi_mac_top_i_m01 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_TOP_I_M01_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_TOP_I_M01_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_ns_top_i_m01: CLK_ns_top_i_m01 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NS_TOP_I_M01_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_NS_TOP_I_M01_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_csi_mac_lptx_top_i_m1: CLK_csi_mac_lptx_top_i_m1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_LPTX_TOP_I_M1_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_LPTX_TOP_I_M1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_csi_mac_top_i_m1: CLK_csi_mac_top_i_m1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_CSI_MAC_TOP_I_M1_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_CSI_MAC_TOP_I_M1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_ns_top_i_m1: CLK_ns_top_i_m1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_86m>,<&CLK_utmi_160m_div4>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_TOP_I_M1_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_NS_TOP_I_M1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_mipi1_tx_csi: CLK_mipi1_tx_csi { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_lpll_clk>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m>,<&CLK_utmi_240m>,<&CLK_mpll_288m>,<&CLK_upll_320m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIPI1_TX_CSI_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MIPI1_TX_CSI_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_ven_pll>,<&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <3>; ++ gate-shift = <7>; //0+REG_CKG_VHE_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_mfe: CLK_mfe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_ven_pll>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++ auto-enable = <0>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_sd: CLK_sd { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SD_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SD_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_ecc: CLK_ecc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET ++ mux-width = <2>; ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_288m_div4>,<&CLK_upll_384m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_345m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_dip: CLK_dip { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DIP_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_DIP_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++}; ++ ++CLK_ive: CLK_ive { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m>,<&CLK_upll_320m>,<&CLK_upll_384m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_IVE_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_IVE_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_ldcfeye: CLK_ldcfeye { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_utmi_480m>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_86m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_LDCFEYE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_LDCFEYE_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <0>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <0>; //0+REG_CKG_LIVE_PM_OFFSET ++ mux-width = <2>; ++ auto-enable = <0>; ++}; ++ ++CLK_mcu_pm_p1: CLK_mcu_pm_p1 { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_fro_div8>,<&CLK_rtc_32k>,<&CLK_fro_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_P1_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_P1_OFFSET ++ auto-enable = <1>; ++}; ++ ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_fro>,<&CLK_rtc_32k>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m>,<&CLK_fro_div2>,<&CLK_xtali_24m>,<&CLK_mpll_216m_div4>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <13>; //5+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miic_pm: CLK_miic_pm { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_xtali_12m>,<&CLK_fro_div2>,<&CLK_rtc_32k>; ++ reg = ; ++ mux-shift = <14>; //2+REG_CKG_MIIC_OFFSET ++ mux-width = <2>; ++ gate-shift = <12>; //0+REG_CKG_MIIC_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_fro_div2>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //0+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <2>; ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++#ifdef CONFIG_CAM_CLK ++ ignore = <1>; ++#endif ++ auto-enable = <1>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <2>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pir: CLK_pir { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_fro_div16>,<&CLK_fro_div8>,<&CLK_fro_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_PIR_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_PIR_OFFSET ++ auto-enable = <0>; ++}; ++ ++CLK_pm_uart: CLK_pm_uart { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_PM_UART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_PM_UART_OFFSET ++ auto-enable = <1>; ++}; ++#ifdef CONFIG_MS_USCLK ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, ++ <&CLK_VOID>, ++ <&CLK_aesdma>, ++ <&CLK_armpll_37p125m>, ++ <&CLK_bdma>, ++ <&CLK_bist>, ++ <&CLK_bist_ipu_gp>, ++ <&CLK_bist_pm>, ++ <&CLK_bist_sc_gp>, ++ <&CLK_bist_usb30_gp>, ++ <&CLK_bist_vhe_gp>, ++ <&CLK_cpupll_clk>, ++ <&CLK_csi_mac_lptx_top_i_m00>, ++ <&CLK_csi_mac_lptx_top_i_m01>, ++ <&CLK_csi_mac_lptx_top_i_m1>, ++ <&CLK_csi_mac_top_i_m00>, ++ <&CLK_csi_mac_top_i_m01>, ++ <&CLK_csi_mac_top_i_m1>, ++ <&CLK_ddr_syn>, ++ <&CLK_ddrpll_clk>, ++ <&CLK_dip>, ++ <&CLK_emac_ahb>, ++ <&CLK_emac_testrx125_in_lan>, ++ <&CLK_eth_buf>, ++ <&CLK_fclk1>, ++ <&CLK_fclk1_p>, ++ <&CLK_fro>, ++ <&CLK_fro_div16>, ++ <&CLK_fro_div2>, ++ <&CLK_fro_div8>, ++ <&CLK_fuart>, ++ <&CLK_fuart0_synth_in>, ++ <&CLK_fuart0_synth_out>, ++ <&CLK_ipu>, ++ <&CLK_ipuff>, ++ <&CLK_isp>, ++ <&CLK_ive>, ++ <&CLK_jpe>, ++ <&CLK_ldcfeye>, ++ <&CLK_live>, ++ <&CLK_live_pm>, ++ <&CLK_lpll_clk>, ++ <&CLK_lpll_div2>, ++ <&CLK_lpll_div4>, ++ <&CLK_lpll_div8>, ++ <&CLK_mcu>, ++ <&CLK_mcu_p>, ++ <&CLK_mcu_pm_p1>, ++ <&CLK_mfe>, ++ <&CLK_miic0>, ++ <&CLK_miic1>, ++ <&CLK_miic2>, ++ <&CLK_miic_pm>, ++ <&CLK_mipi1_tx_csi>, ++ <&CLK_miu>, ++ <&CLK_miu_boot>, ++ <&CLK_miu_p>, ++ <&CLK_miu_rec>, ++ <&CLK_miu_sc_gp_p>, ++ <&CLK_miu_vhe_gp_p>, ++ <&CLK_miupll_clk>, ++ <&CLK_mpll_123m>, ++ <&CLK_mpll_123m_div2>, ++ <&CLK_mpll_172m>, ++ <&CLK_mpll_216m>, ++ <&CLK_mpll_216m_div2>, ++ <&CLK_mpll_216m_div4>, ++ <&CLK_mpll_216m_div8>, ++ <&CLK_mpll_288m>, ++ <&CLK_mpll_288m_div2>, ++ <&CLK_mpll_288m_div4>, ++ <&CLK_mpll_288m_div8>, ++ <&CLK_mpll_432m>, ++ <&CLK_mpll_345m>, ++ <&CLK_mpll_86m>, ++ <&CLK_mpll_86m_div16>, ++ <&CLK_mpll_86m_div2>, ++ <&CLK_mpll_86m_div4>, ++ <&CLK_mspi>, ++ <&CLK_mspi0>, ++ <&CLK_mspi0_p>, ++ <&CLK_mspi1>, ++ <&CLK_mspi1_p>, ++ <&CLK_ns_top_i_m00>, ++ <&CLK_ns_top_i_m01>, ++ <&CLK_ns_top_i_m1>, ++ <&CLK_odclk>, ++ <&CLK_pir>, ++ <&CLK_pm_riu_w_clk_in>, ++ <&CLK_pm_sleep>, ++ <&CLK_pm_uart>, ++ <&CLK_pwm>, ++ <&CLK_pwr_ctl>, ++ <&CLK_riu_w_clk_hemcu_gp>, ++ <&CLK_riu_w_clk_in>, ++ <&CLK_riu_w_clk_mcu_if_gp>, ++ <&CLK_riu_w_clk_mipi_if_gp>, ++ <&CLK_riu_w_clk_sc_gp>, ++ <&CLK_riu_w_clk_top>, ++ <&CLK_riu_w_clk_vhe_gp>, ++ <&CLK_riubrdg>, ++ <&CLK_rmii_buf>, ++ <&CLK_rtc>, ++ <&CLK_rtc_32k>, ++ <&CLK_sar>, ++ <&CLK_sd>, ++ <&CLK_sdio>, ++ <&CLK_sdio_p>, ++ <&CLK_spi_arb>, ++ <&CLK_spi_flash>, ++ <&CLK_spi_pm>, ++ <&CLK_sr00_mclk>, ++ <&CLK_sr01_mclk>, ++ <&CLK_sr1_mclk>, ++ <&CLK_tck_buf>, ++ <&CLK_uart0>, ++ <&CLK_uart1>, ++ <&CLK_upll_320m>, ++ <&CLK_upll_384m>, ++ <&CLK_utmi>, ++ <&CLK_utmi_160m>, ++ <&CLK_utmi_160m_div4>, ++ <&CLK_utmi_160m_div5>, ++ <&CLK_utmi_160m_div8>, ++ <&CLK_utmi_192m>, ++ <&CLK_utmi_192m_div4>, ++ <&CLK_utmi_240m>, ++ <&CLK_utmi_480m>, ++ <&CLK_ven_pll>, ++ <&CLK_ven_pll_div6>, ++ <&CLK_vhe>, ++ <&CLK_xtali>, ++ <&CLK_xtali_12m>, ++ <&CLK_xtali_12m_div128>, ++ <&CLK_xtali_12m_div16>, ++ <&CLK_xtali_12m_div2>, ++ <&CLK_xtali_12m_div4>, ++ <&CLK_xtali_12m_div40>, ++ <&CLK_xtali_12m_div64>, ++ <&CLK_xtali_12m_div8>, ++ <&CLK_xtali_24m>, ++ <&CLK_xtali_sc_gp>; ++ clock-count = <142>; ++}; ++#endif +diff --git a/arch/arm/boot/dts/infinity6e-fpga-256.dts b/arch/arm/boot/dts/infinity6e-fpga-256.dts +new file mode 100755 +index 000000000000..5dcba6455b79 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-fpga-256.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e-fpga.dtsi" ++ ++/ { ++ model = "INFINITY6E FPGA"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x0F000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x2F000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x2F400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x2F800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-fpga.dts b/arch/arm/boot/dts/infinity6e-fpga.dts +new file mode 100755 +index 000000000000..124d80fd20c7 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-fpga.dts +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e-fpga.dtsi" ++ ++/ { ++ model = "INFINITY6E FPGA"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc"; ++ }; ++ ++ rootfsp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "ROOTFS"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x0400000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27800000 0x0800000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-fpga.dtsi b/arch/arm/boot/dts/infinity6e-fpga.dtsi +new file mode 100755 +index 000000000000..0beeae021137 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-fpga.dtsi +@@ -0,0 +1,488 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity6e/irqs.h> ++#include <../../../../drivers/sstar/include/infinity6e/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ reg = <0x0>; ++ }; ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ reg = <0x1>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ }; ++ ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++ venc { ++ compatible = "sstar,venc"; ++ reg = <0x1F345200 0x800>, <0x1F2C5200 0x100>, <0x1F203C00 0x100>, <0x1F207800 0x100>; ++ reg-names = "vpu-bit", "venc-brige", "hw-uart0", "hw-uart1"; ++ interrupts = ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_mfe>; ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ clocks = <&CLK_dip>; ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++ status = "ok"; ++ clock-frequency-index = <5>; ++ }; ++ ++ csi: csi { ++ compatible = "sstar,csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x120b>,<0x120c>,<0x120d>,<0x1208>,<0x1209>,<0x120a>,<0x1202>,<0x1203>,<0x1204>,<0x1038>; ++ interrupts= ; ++ clocks = <&CLK_csi_mac_lptx_top_i_m00>,<&CLK_csi_mac_top_i_m00>,<&CLK_ns_top_i_m00>,<&CLK_csi_mac_lptx_top_i_m1>,<&CLK_csi_mac_top_i_m1>,<&CLK_ns_top_i_m1>,<&CLK_csi_mac_lptx_top_i_m01>,<&CLK_csi_mac_top_i_m01>,<&CLK_ns_top_i_m01>; ++ status = "ok"; ++ /* Config max lane number */ ++ csi_sr0_lane_num = <4>; ++ csi_sr1_lane_num = <4>; ++ csi_sr2_lane_num = <2>; ++ /* Config lane selection */ ++ csi_sr0_lane_select = <1 2 0 3 4>; ++ csi_sr1_lane_select = <1 2 0 3 4>; ++ csi_sr2_lane_select = <1 0 2>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr2_lane_pn_swap = <1 1 1>; ++ }; ++ ++ vif: vif { ++ compatible = "sstar,vif"; ++ status = "ok"; ++ reg = <0x1F260800 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F207800 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>, <0x1F203C00 0x200>; ++ clocks = <&CLK_sr00_mclk>,<&CLK_sr1_mclk>,<&CLK_sr01_mclk>; ++ interrupts = ; ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <0>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ vif_sr0_rst_mode = <0>; ++ vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <0>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ /* Config mclk 37.125MHz supported */ ++ vif_sr0_mclk_37p125 = <1>; ++ vif_sr1_mclk_37p125 = <1>; ++ vif_sr2_mclk_37p125 = <1>; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <2>; ++ sensorif_grp2_i2c = <1>; //ToDo? ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F2c4000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F207800 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <1>; ++ interrupts=; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F207800 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ * 2 -> PAD_GPIO0, PAD_GPIO1 ++ * 3 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ */ ++ i2c-padmux = <1>; ++ interrupts=; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223400 0x200>,<0x1F207800 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <2>; ++ /* ++ * padmux: 1 -> PAD_SR1_IO18, PAD_SR1_IO19 ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 4 -> PAD_PM_I2CM_SCL, PAD_PM_I2CM_SDA ++ * 5 -> PAD_PM_GPIO0, PAD_PM_GPIO1 ++ */ ++ i2c-padmux = <1>; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ clocks = <&xtal>; //for timeout tick ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ ldc: ldc { ++ compatible = "sstar,ldc"; ++ reg = <0x1F287800 0x100>, <0x1F287A00 0x100>; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ scl: scl { ++ compatible = "sstar,scl"; ++ status = "ok"; ++ }; ++ ++ vpe: vpe { ++ compatible = "sigmastar,vpe"; ++ status = "ok"; ++ interrupts = , , , ; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks =<&CLK_sd>, <&CLK_ecc>; ++ interrupts = ; ++ bus-width = <8>; ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <1>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-pwr-gpios = ,<0>,<0>; ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ ++ interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_SD IRQ_TYPE_LEVEL_HIGH>,//was INT_IRQ_SDIO ++ <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ_0 IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_gpi_intc 42>, ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ_0 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "mie0_irq", "mie1_irq", "cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"; ++ clocks = <&CLK_sd>,<&CLK_sdio>,<&CLK_sd>; ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++ status = "ok"; ++ }; ++ ++ gop{ ++ compatible = "sstar,gop"; ++ clocks = <&CLK_VOID>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "sstar,gop1"; ++ clocks = <&CLK_VOID>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "sstar,gop2"; ++ clocks = <&CLK_VOID>,<&CLK_VOID>; ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>; ++ status = "ok"; ++ }; ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x00000000 0x000>; ++ pad = <0x1F203C3C 0x0004 0x0004>; // pad selection from 0x0001 ++ phy-handle = <&phy0>; ++ max-speed = <10>; ++ mdio_path = <0>; // force internal mdio ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ // phy-mode = "rmii"; ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ //reg = <0x1F003400 0x200>; /* PM-PWM(BK:x1A) */ ++ //npwm = <1>; ++ reg = <0x1F203200 0x400>; /* NonPM-PWM(BK:x1019 and x101A) */ ++ npwm = <10>; ++ clocks = <&CLK_xtali_12m>; ++ interrupts=; //Only4i6e; Others, pls check hold0 int supporting. ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ mmu { ++ compatible = "sstar,mmu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6e/reg_clks.h> ++ #include "infinity6e-clks.dtsi" ++}; +diff --git a/arch/arm/boot/dts/infinity6e-padmux-cardv.dtsi b/arch/arm/boot/dts/infinity6e-padmux-cardv.dtsi +new file mode 100644 +index 000000000000..55bc6b07bbf4 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-padmux-cardv.dtsi +@@ -0,0 +1,93 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity6e/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ , ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ ++ //, //Reserved for sensor I2C ++ //, //Reserved for sensor I2C ++ //, //Reserved for sensor reset ++ , ++ , ++ , ++ , ++ ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ #if 1 //BGA ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ #else //QFN ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ #endif ++ , ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ ; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-padmux-qfn.dtsi b/arch/arm/boot/dts/infinity6e-padmux-qfn.dtsi +new file mode 100755 +index 000000000000..e86ff08faaba +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-padmux-qfn.dtsi +@@ -0,0 +1,86 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity6e/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ ++ , ++ , //Reserved for sensor reset ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ //QFN ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ //, ++ //, ++ //, ++ , ++ //, ++ //, ++ ; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-padmux.dtsi b/arch/arm/boot/dts/infinity6e-padmux.dtsi +new file mode 100755 +index 000000000000..1d54e51d1b9b +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-padmux.dtsi +@@ -0,0 +1,97 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity6e/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ ++ //, //Reserved for sensor I2C ++ //, //Reserved for sensor I2C ++ ++ , ++ , ++ ++ , //Reserved for sensor reset ++ , ++ , ++ , ++ , ++ ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ #if 1 //BGA ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ #else //QFN ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ #endif ++ , ++ , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ ; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-panel-padmux-qfn.dtsi b/arch/arm/boot/dts/infinity6e-panel-padmux-qfn.dtsi +new file mode 100755 +index 000000000000..ca99020ba913 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-panel-padmux-qfn.dtsi +@@ -0,0 +1,137 @@ ++/* ++* infinity2m-scc010a-s01a-padmux.dts - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include <../../../../drivers/sstar/include/infinity6e/padmux.h> ++#include <../../../../drivers/sstar/include/mdrv_puse.h> ++ ++/ { ++ soc { ++ padmux { ++ compatible = "sstar-padmux"; ++ schematic = ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ ++ //, //Reserved for sensor I2C ++ //, //Reserved for sensor I2C ++ , //Reserved for sensor reset ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ , ++ //QFN ++#if 0 ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++#endif ++ ++ #if 0 ++ //for TTL 16bit mode 1 ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ #endif ++ #if 1 ++ //for TTL 16bit mode 4 ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ++ #endif ++ ++ ++// , ++// , ++ //, ++ //, ++ //, ++ //, ++ //, ++ //, ++ ; ++ status = "ok"; // ok or disable ++ //status = "disable"; ++ }; ++ ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc012b-s01a-2+2mipi-panel.dts b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-2+2mipi-panel.dts +new file mode 100755 +index 000000000000..17552bcfd3d0 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-2+2mipi-panel.dts +@@ -0,0 +1,148 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-panel-padmux-qfn.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC012B-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 2+2 setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 1 0 3 4>; ++ csi_sr1_lane_select = <0 0 0 0 0>; ++ csi_sr2_lane_select = <2 1 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <1 1 1>; ++ }; ++ ++ /* mipi0 2+2 setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <3>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <0>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <0>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <1>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <1>; ++ vif_sr2_rst_mode = <0>; ++ ++ vif_sr_gpio_puse_0 = ; /* MDRV_PUSE_NA */ ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //QFN-CFG ++ slot-pad-orders = <0>,<2>,<1>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ power-enable-pad = ; ++ status = "ok"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc012b-s01a-2+2mipi.dts b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-2+2mipi.dts +new file mode 100755 +index 000000000000..08ea2ecd7402 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-2+2mipi.dts +@@ -0,0 +1,143 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux-qfn.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC012B-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 2+2 setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 1 0 3 4>; ++ csi_sr1_lane_select = <0 0 0 0 0>; ++ csi_sr2_lane_select = <2 1 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <1 1 1>; ++ }; ++ ++ /* mipi0 2+2 setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <3>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <0>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <0>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <1>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <1>; ++ vif_sr2_rst_mode = <0>; ++ ++ vif_sr_gpio_puse_0 = ; /* MDRV_PUSE_NA */ ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //QFN-CFG ++ slot-pad-orders = <0>,<2>,<1>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc012b-s01a-amp.dts b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-amp.dts +new file mode 100755 +index 000000000000..b9468998bd31 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-amp.dts +@@ -0,0 +1,151 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#define __DTS_AMP__ ++ ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux-qfn.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC012B-S01A-AMP"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc initrd=0x20E00000,0x96000 rootwait=1 LX_MEM=0x5000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000,mem=80m,maxcpus=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0400000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ /* Disable linux side I2C1 for RTK */ ++ i2c1@1{ ++ status = "disabled"; ++ }; ++ ++ /* Disable linux side I2C2 for RTK */ ++ i2c2@2{ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //QFN-CFG ++ slot-pad-orders = <0>,<2>,<1>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++ ++ /*!! wait correct info to enable this feature. ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ vid_default = <1>; //2b'00 ++ };*/ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc012b-s01a-panel.dts b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-panel.dts +new file mode 100755 +index 000000000000..4d337ec6366b +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-panel.dts +@@ -0,0 +1,143 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-panel-padmux-qfn.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC012B-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 2+2 setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 1 0 3 4>; ++ csi_sr1_lane_select = <0 0 0 0 0>; ++ csi_sr2_lane_select = <2 1 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <1 1 1>; ++ }; ++ ++ /* mipi0 2+2 setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <3>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <0>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <0>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <1>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <1>; ++ vif_sr2_rst_mode = <0>; ++ ++ vif_sr_gpio_puse_0 = ; /* MDRV_PUSE_NA */ ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //QFN-CFG ++ slot-pad-orders = <0>,<2>,<1>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc012b-s01a-smplh.dts b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-smplh.dts +new file mode 100755 +index 000000000000..554ad9594677 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc012b-s01a-smplh.dts +@@ -0,0 +1,149 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux-qfn.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC012B-S01A-SMPLH"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc initrd=0x20E00000,0x96000 rootwait=1 LX_MEM=0x5000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000,mem=80m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0400000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ /* Disable linux side I2C1 for RTK */ ++ i2c1@1{ ++ status = "disabled"; ++ }; ++ ++ /* Disable linux side I2C2 for RTK */ ++ i2c2@2{ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //QFN-CFG ++ slot-pad-orders = <0>,<2>,<1>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++ ++ /*!! wait correct info to enable this feature. ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ vid_default = <1>; //2b'00 ++ };*/ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc012b-s01a.dts b/arch/arm/boot/dts/infinity6e-ssc012b-s01a.dts +new file mode 100755 +index 000000000000..fc9479b31895 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc012b-s01a.dts +@@ -0,0 +1,155 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux-qfn.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC012B-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 4lane setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <0 0 0 0 0>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ /* mipi0 4lane setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <2>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //QFN-CFG ++ slot-pad-orders = <0>,<2>,<1>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ ++ ipu { ++ compatible = "sstar,ipu"; ++ operating-points = < ++ /* kHz uV */ ++ 900000 1000000 ++ 800000 1000000 ++ 600000 900000 ++ 500000 900000 ++ 400000 900000 ++ 300000 900000 ++ >; ++ status = "ok"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc013a-s01a-2+2mipi.dts b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-2+2mipi.dts +new file mode 100755 +index 000000000000..066c260d73cf +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-2+2mipi.dts +@@ -0,0 +1,141 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC013A-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 950000 ++ 1100000 950000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 2+2 setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 1 0 3 4>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <2 1 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <1 1 1>; ++ }; ++ ++ /* mipi0 2+2 setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <3>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <1>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <1>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //BGA-CFG ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc013a-s01a-amp.dts b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-amp.dts +new file mode 100755 +index 000000000000..20a9da82e635 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-amp.dts +@@ -0,0 +1,152 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#define __DTS_AMP__ ++ ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC013A-S01A-AMP"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc initrd=0x20E00000,0x96000 rootwait=1 LX_MEM=0x5000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000,mem=80m,maxcpus=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0400000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 950000 ++ 1100000 950000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ /* Disable linux side I2C1 for RTK */ ++ i2c1@1{ ++ status = "disabled"; ++ }; ++ ++ /* Disable linux side I2C2 for RTK */ ++ i2c2@2{ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //BGA-CFG ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++ ++ /*!! wait correct info to enable this feature. ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ vid_default = <1>; //2b'00 ++ };*/ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc013a-s01a-cardv.dts b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-cardv.dts +new file mode 100755 +index 000000000000..54fb3948881f +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-cardv.dts +@@ -0,0 +1,186 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++ ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux-cardv.dtsi" ++ ++/ { ++ model = "INFINITY6E CARDV"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 950000 ++ 1100000 950000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 4lane setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ /* mipi0 4lane setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <2>; ++ sensorif_grp2_i2c = <1>; ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ * 2 -> PAD_GPIO0, PAD_GPIO1 ++ * 3 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_SR1_IO18, PAD_SR1_IO19 ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 4 -> PAD_PM_I2CM_SCL, PAD_PM_I2CM_SDA ++ * 5 -> PAD_PM_GPIO0, PAD_PM_GPIO1 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ sound { ++ compatible = "sstar,audio"; ++ amp-gpio = ; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<1>,<0>; ++ //BGA-CFG ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<1>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6e/reg_clks.h> ++ CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "sstar,composite-clock"; ++ auto-enable = <1>; ++ }; ++}; +\ No newline at end of file +diff --git a/arch/arm/boot/dts/infinity6e-ssc013a-s01a-smplh.dts b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-smplh.dts +new file mode 100755 +index 000000000000..aa4e8daf2a09 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc013a-s01a-smplh.dts +@@ -0,0 +1,150 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC013A-S01A-SMPLH"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rdinit=/linuxrc initrd=0x20E00000,0x96000 rootwait=1 LX_MEM=0x5000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000,mem=80m"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0400000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 950000 ++ 1100000 950000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <1>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ /* Disable linux side I2C1 for RTK */ ++ i2c1@1{ ++ status = "disabled"; ++ }; ++ ++ /* Disable linux side I2C2 for RTK */ ++ i2c2@2{ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <3>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //BGA-CFG ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ }; ++ ++ /*!! wait correct info to enable this feature. ++ core_voltage { ++ vid_width = <1>; ++ vid_gpios = ; ++ vid_voltages = <900 1000>; //2b'00 2b'01 ++ vid_default = <1>; //2b'00 ++ };*/ ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc013a-s01a.dts b/arch/arm/boot/dts/infinity6e-ssc013a-s01a.dts +new file mode 100755 +index 000000000000..7187f0f551c4 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc013a-s01a.dts +@@ -0,0 +1,158 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC013A-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 4lane setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ /* mipi0 4lane setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //BGA-CFG ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ ++ ipu { ++ compatible = "sstar,ipu"; ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 1000000 ++ 900000 1000000 ++ 800000 900000 ++ 600000 900000 ++ 500000 900000 ++ 400000 900000 ++ 300000 900000 ++ >; ++ status = "ok"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e-ssc015a-s01a.dts b/arch/arm/boot/dts/infinity6e-ssc015a-s01a.dts +new file mode 100755 +index 000000000000..9fd98b17bdc8 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e-ssc015a-s01a.dts +@@ -0,0 +1,158 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E SSC015A-S01A"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++ cpus { ++ cpu@0 { ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 900000 ++ 900000 900000 ++ 800000 900000 ++ 600000 900000 ++ 400000 900000 ++ >; ++ }; ++ }; ++ soc { ++ /* mipi0 4lane setting */ ++ csi { ++ /* Config lane selection */ ++ csi_sr0_lane_select = <2 4 3 1 0>; ++ csi_sr1_lane_select = <2 0 1 3 4>; ++ csi_sr2_lane_select = <0 0 0>; ++ /* Config lane P/N swap */ ++ csi_sr0_lane_pn_swap = <1 1 1 1 1>; ++ csi_sr1_lane_pn_swap = <0 0 0 0 0>; ++ csi_sr2_lane_pn_swap = <0 0 0>; ++ }; ++ ++ /* mipi0 4lane setting */ ++ vif { ++ /* Config sensor 0 pad mux */ ++ vif_sr0_par_mode = <1>; ++ vif_sr0_mipi_mode = <1>; ++ vif_sr0_bt656_mode = <1>; ++ vif_sr0_mclk_mode = <0>; ++ //vif_sr0_rst_mode = <0>; ++ //vif_sr0_pdn_mode = <0>; ++ vif_sr0_parallel_rst_mode = <0>; ++ vif_sr0_parallel_pdn_mode = <0>; ++ vif_sr0_mipi_rst_mode = <0>; ++ vif_sr0_mipi_pdn_mode = <0>; ++ vif_sr0_mipi_ctrl_mode = <1>; ++ //vif_sr0_hvsync_mode = <0>; /* Not used in I6E */ ++ //vif_sr0_pck_mode = <0>; /* Not used in I6E */ ++ /* Config sensor 1 pad mux */ ++ vif_sr1_par_mode = <0>; ++ vif_sr1_mipi_mode = <1>; ++ vif_sr1_bt656_mode = <0>; ++ vif_sr1_mipi_ctrl_mode = <1>; ++ vif_sr1_mclk_mode = <0>; ++ vif_sr1_rst_mode = <0>; ++ /* Config sensor 2 pad mux */ ++ vif_sr2_mipi_mode = <0>; /* MIPI sensor only */ ++ vif_sr2_mipi_ctrl_mode = <0>; ++ vif_sr2_mclk_mode = <0>; ++ vif_sr2_rst_mode = <0>; ++ }; ++ ++ iopower { ++ pm_sar_atop_vddp1 = <0>; /* 0: 1.8V 1: 3.3V */ ++ pm_sar_atop_pmspi = <0>; /* 0: 1.8V 1: 3.3V */ ++ status = "disabled"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ slot-fakecdzs = <0>,<0>,<0>; ++ //BGA-CFG ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-cdzs-gpios = ,,; ++ slot-sdio-use = <0>,<0>,<0>; ++ slot-removable = <1>,<1>,<1>; ++ }; ++ ++ ipu { ++ compatible = "sstar,ipu"; ++ operating-points = < ++ /* kHz uV */ ++ 1200000 1000000 ++ 1100000 1000000 ++ 1000000 1000000 ++ 900000 1000000 ++ 800000 900000 ++ 600000 900000 ++ 500000 900000 ++ 400000 900000 ++ 300000 900000 ++ >; ++ status = "ok"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity6e.dts b/arch/arm/boot/dts/infinity6e.dts +new file mode 100755 +index 000000000000..5285afdd8f9e +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e.dts +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity6e.dtsi" ++#include "infinity6e-padmux.dtsi" ++ ++/ { ++ model = "INFINITY6E ASIC"; ++ compatible = "sstar,infinity6e"; ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x3ee0000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000 mma_memblock_remove=1"; ++ }; ++ ++ /*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ /* ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x04000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ */ ++}; +diff --git a/arch/arm/boot/dts/infinity6e.dtsi b/arch/arm/boot/dts/infinity6e.dtsi +new file mode 100755 +index 000000000000..0f5f91589661 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity6e.dtsi +@@ -0,0 +1,859 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/sstar/include/infinity6e/irqs.h> ++#include <../../../../drivers/sstar/include/infinity6e/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++#include <../../../../include/generated/autoconf.h> ++#ifdef CONFIG_CAM_CLK ++#include <../../../../drivers/sstar/include/infinity6e/camclk.h> ++#endif ++ ++/ { ++ camclk: camclkinit { ++ compatible = "camdriver,camclkinit"; ++ status = "ok"; ++ }; ++ camclk { ++ compatible = "camdriver,camclk"; ++ status = "ok"; ++ }; ++ camclkut { ++ compatible = "camdriver,camclkut"; ++ status = "ok"; ++ }; ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clock-frequency = <1000000000>; ++#ifndef CONFIG_CAM_CLK ++ clocks = <&CLK_cpupll_clk>; ++#endif ++ reg = <0x0>; ++ }; ++#ifndef __DTS_AMP__ ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clock-frequency = <1000000000>; ++#ifndef CONFIG_CAM_CLK ++ clocks = <&CLK_cpupll_clk>; ++#endif ++ reg = <0x1>; ++ }; ++#endif ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ serial3 = &pm_uart; ++ }; ++ ++ phy: phy { ++ compatible = "sstar,infinity6e-sata-phy"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1523>,<0x1524>,<0x1525>; ++ reg = <0x1f2a4600 0x300>; ++ #phy-cells = <0>; ++ phy_type = "utmi"; ++ status = "ok"; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&ms_main_intc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: gic@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_main_intc: ms_main_intc { ++ compatible = "sstar,main-intc"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ms_pm_intc: ms_pm_intc { ++ compatible = "sstar,pm-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ ms_gpi_intc: ms_gpi_intc { ++ compatible = "sstar,gpi-intc"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&ms_main_intc>; ++ interrupt-controller; ++ interrupts = ; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ always-on; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupt-parent=<&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++ venc { ++ compatible = "sstar,venc"; ++ reg = <0x1F345200 0x800>, <0x1F2C5200 0x100>, <0x1F203C00 0x100>, <0x1F207800 0x100>; ++ reg-names = "vpu-bit", "venc-brige", "hw-uart0", "hw-uart1"; ++ interrupts = ; ++ interrupt-parent = <&ms_main_intc>; ++ interrupt-names = "mhe-irq"; ++ clocks = <&CLK_vhe>, <&CLK_mfe>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_venc"; ++ status = "ok"; ++ }; ++ ++ dip { ++ compatible = "sstar,dip"; ++ interrupts=; ++ clocks = <&CLK_dip>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ dla { ++ compatible = "sstar,dla"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ gop { ++ compatible = "sigmastar,gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&CLK_dip>,<&CLK_ldcfeye>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>; ++ interrupts = ; ++ clocks = <&CLK_isp>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ clock-frequency-index = <0>; ++ }; ++ ++ csi: csi { ++ compatible = "sstar,csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x120b>,<0x120c>,<0x120d>,<0x1208>,<0x1209>,<0x120a>,<0x1202>,<0x1203>,<0x1204>,<0x1038>,<0x120e>; ++ interrupts= ; ++ clocks = <&CLK_csi_mac_lptx_top_i_m00>,<&CLK_csi_mac_top_i_m00>,<&CLK_ns_top_i_m00>,<&CLK_csi_mac_lptx_top_i_m1>,<&CLK_csi_mac_top_i_m1>,<&CLK_ns_top_i_m1>,<&CLK_csi_mac_lptx_top_i_m01>,<&CLK_csi_mac_top_i_m01>,<&CLK_ns_top_i_m01>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ /* Config max lane number */ ++ csi_sr0_lane_num = <4>; ++ csi_sr1_lane_num = <4>; ++ csi_sr2_lane_num = <2>; ++ }; ++ pnl: pnl { ++ compatible = "sstar,pnl"; ++ status = "ok"; ++ ttl-24bit-mode = <0>; //only 1 mode ++ ttl-16bit-mode = <1>; //1~4 mode ++ jtag-mode = <1>; ++ clocks = <&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_odclk"; ++ interrupts = ; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ disp: disp { ++ compatible = "sstar,disp"; ++ status = "ok"; ++ clocks = <&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_odclk"; ++ //Reg = <0x1F224000 0x200>; ++ interrupts = , , , ; ++ }; ++ mipitx_csi: mipitx_csi { ++ compatible = "sstar,mipitx"; ++ status = "ok"; ++ clocks = <&CLK_mipi1_tx_csi>; ++ clock-names = "CLK_mipi1_tx_csi"; ++ interrupts = ; ++ }; ++ sound { ++ compatible = "sstar,audio"; ++ interrupts=; ++ amp-gpio = ; ++ clocks = <&CLK_bach>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ digmic-padmux = <6>; //1~6 ++ i2s-trx-shared-padmux = <1>; //for 4-wired mode panmux ++ i2s-tx-padmux = <0>; //6-wired mode ++ i2s-rx-padmux = <0>; //6-wired mode ++ i2smck-padmux = <1>; // ++ i2smod-padmux = <0>; //0:i2s tdm, 1:i2s normal ++ keep-i2s-clk = <0>; ++ ++ //I2S RX TDM ++ i2s-rx-tdm-ws-pgm = <0>; // 0: OFF 1: ON ++ i2s-rx-tdm-ws-width = <0>; // value: 0~31 (width = value + 1) ++ i2s-rx-tdm-ch-swap = <0 0>; // 0: OFF 1: ON ++ ++ //I2S TX TDM ++ i2s-tx-tdm-ws-pgm = <0>; // 0: OFF 1: ON ++ i2s-tx-tdm-ws-width = <0>; // value: 0~31 (width = value + 1) ++ i2s-tx-tdm-ch-swap = <0 0>; // 0: OFF 1: ON ++ i2s-tx-tdm-active-slot = <0x03>; // value: 0x00 ~ 0xFF (bit0->slot0, bit1->slot1, ... ) ++ ++ //dmic bck mode ++ dmic-bck-mode = <0>; //0:4M, 1:2M ++ ++ status = "ok"; ++ }; ++ vif: vif { ++ compatible = "sstar,vif"; ++ status = "ok"; ++ reg = <0x1F260800 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F207800 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>, <0x1F203C00 0x200>; ++ clocks = <&CLK_sr00_mclk>,<&CLK_sr1_mclk>,<&CLK_sr01_mclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ /* Config mclk 37.125MHz supported */ ++ vif_sr0_mclk_37p125 = <1>; ++ vif_sr1_mclk_37p125 = <1>; ++ vif_sr2_mclk_37p125 = <1>; ++ }; ++ ++ ispalgo: ispalgo { ++ compatible = "sstar,ispalgo"; ++ status = "ok"; ++ }; ++ ++ ispmid: ispmid { ++ compatible = "sstar,ispmid"; ++ status = "ok"; ++ }; ++ ++ sensorif: sensorif { ++ compatible = "sstar,sensorif"; ++ status = "ok"; ++ sensorif_grp0_i2c = <1>; ++ sensorif_grp1_i2c = <2>; ++ sensorif_grp2_i2c = <1>; //ToDo? ++ }; ++ ++ jpe0: jpe@0x1F2c4000 { ++ compatible = "sstar,cedric-jpe"; ++ reg = <0x1F2c4000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ spi: spi { ++ compatible = "sstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x103C>; ++ interrupts = ,; ++ spi0_mode = <1>; ++ spi1_mode = <3>; ++ status = "disabled"; ++ }; ++ ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ ++ spi0@0{ ++ compatible = "sstar,mspi"; ++ mspi-group = <0>; ++ #ifdef CONFIG_CAM_CLK ++ camclk = ,; ++ #else ++ clocks = <&CLK_mspi0>,<&CLK_mspi>; ++ #endif ++ reg = <0x1F222000 0x200>; ++ interrupts = ; ++ use-dma = <1>; ++ status = "ok"; ++ }; ++ ++ spi1@1{ ++ compatible = "sstar,mspi"; ++ mspi-group = <1>; ++ #ifdef CONFIG_CAM_CLK ++ camclk = ,; ++ #else ++ clocks = <&CLK_mspi1>,<&CLK_mspi>; ++ #endif ++ reg = <0x1F222200 0x200>; ++ interrupts = ; ++ use-dma = <1>; ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F207800 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <0>; ++ i2c-en-dma = <1>; // 0: disable; 1: enable; ++ status = "ok"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 3 -> PAD_GPIO6, PAD_GPIO7 ++ * 4 -> PAD_SR1_IO00, PAD_SR1_IO01 ++ * 5 -> PAD_GPIO12, PAD_GPIO13 ++ */ ++ //i2c-padmux = <3>; ++ interrupts=; ++ goodix_gt911@5D{ //EVB i2c-padmux=2 SSD201_SZ_DEMO_BOARD i2c-padmux=1 ++ compatible = "goodix,gt911"; ++ reg = <0x5D>; ++ goodix_rst = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO1 EVB PAD_GPIO0 ++ goodix_int = ; //SSD201_SZ_DEMO_BOARD PAD_GPIO13 EVB PAD_GPIO1 ++ interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_PAD_GPIO5>; ++ interrupt-names = "goodix_int"; ++ }; ++ }; ++ ++ i2c1@1{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F207800 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <1>; ++ i2c-en-dma = <1>; // 0: disable; 1: enable; ++ /* ++ * padmux: 1 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ * 2 -> PAD_GPIO0, PAD_GPIO1 ++ * 3 -> PAD_SR0_IO18, PAD_SR0_IO19 ++ */ ++ i2c-padmux = <1>; ++ interrupts=; ++ status = "ok"; ++// 24c512@54 { ++// compatible = "sstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ i2c2@2{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F223400 0x200>,<0x1F207800 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic2>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <2>; ++ i2c-en-dma = <1>; // 0: disable; 1: enable; ++ /* ++ * padmux: 1 -> PAD_SR1_IO18, PAD_SR1_IO19 ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_ETH_LED0, PAD_ETH_LED1 ++ * 4 -> PAD_PM_I2CM_SCL, PAD_PM_I2CM_SDA ++ * 5 -> PAD_PM_GPIO0, PAD_PM_GPIO1 ++ */ ++ i2c-padmux = <1>; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ i2c3@3{ ++ compatible = "sstar,i2c"; ++ reg = <0x1F007C00 0x200>,<0x1F007E00 0x200>,<0x1F001C00 0x200>; ++ clocks = <&CLK_miic_pm>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ i2c-group = <3>; ++ i2c-en-dma = <0>; // 0: disable; 1: enable; ++ i2c-padmux = <0>; ++ i2c-speed = <3>; ++ //interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq0 { ++ compatible = "sstar,cmdq0"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq1 { ++ compatible = "sstar,cmdq1"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq2 { ++ compatible = "sstar,cmdq2"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ cmdq3 { ++ compatible = "sstar,cmdq3"; ++ clocks = <&CLK_mcu>; //for timeout tick ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ ldc: ldc { ++ compatible = "sstar,ldc"; ++ reg = <0x1F287800 0x100>, <0x1F287A00 0x100>; ++ interrupts=; ++ clocks = <&CLK_ldcfeye>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_ldcfeye"; ++ clk-select = <1>; // 0: 480MHz 1: 432MHz 2: 384MHz 3: 320MHz 4: 288MHz 5: 216MHz 6: 86MHz ++ status = "ok"; ++ }; ++ ++ scl: scl { ++ compatible = "sstar,scl"; ++ status = "ok"; ++ }; ++ ++ vpe: vpe { ++ compatible = "sigmastar,vpe"; ++ reg = <0x1F242000 0x100>; ++ interrupts = , , , ; ++ clocks = <&CLK_fclk1>,<&CLK_odclk>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ clock-names = "CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ clk-select = <2>; ++ status = "ok"; ++ }; ++ ++ uart0: uart0@1F221000 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&CLK_uart0>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "sstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "sstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ sctp_enable = <1>;//rts cts enable is 1 ++ dma = <1>; ++ pad = ;//fuart mode3 ++ //pad = ;//fuart mode6 ++ //pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ ++ pm_uart: pm_uart@1F006A00 { ++ compatible = "sstar,uart"; ++ reg = <0x1f006A00 0x100>; ++ interrupts = ; ++ clocks = <&CLK_pm_uart>; ++ pm_uart = <1>; ++ pad = ; ++ status = "ok"; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "sstar_mci"; ++ clocks =<&CLK_sd>, <&CLK_ecc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ bus-width = <4>; ++ status = "ok"; ++ }; ++ ++ sdmmc { ++ compatible = "sstar,sdmmc"; ++ ++ slotnum = <2>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<0>; ++ slot-pwr-gpios = ,,; ++ slot-pwr-off-delay = <30>,<30>,<30>; ++ ++ interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_SD IRQ_TYPE_LEVEL_HIGH>,//was INT_IRQ_SDIO ++ <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ_0 IRQ_TYPE_LEVEL_HIGH>, ++ <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ_1 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "mie0_irq", "mie1_irq", "cdz_slot0_irq", "cdz_slot1_irq"; ++ clocks = <&CLK_sd>,<&CLK_sdio>,<&CLK_VOID>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma0 { ++ compatible = "sstar,bdma0"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma1 { ++ compatible = "sstar,bdma1"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ bdma2 { ++ compatible = "sstar,bdma2"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++/* ++ bdma3 { ++ compatible = "sstar,bdma3"; ++ interrupts=; ++ clocks = <&CLK_bdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++*/ ++ movdma { ++ compatible = "sstar,movdma"; ++ interrupts=; ++ clocks = <&CLK_miu>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ cpufreq { ++ compatible = "sstar,infinity-cpufreq"; ++ status = "ok"; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ ++ }; ++ ++ watchdog: watchdog { ++ compatible = "sstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "ok"; ++ }; ++ ++ sar: sar { ++ compatible = "sstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "ok"; ++ }; ++ ++ rtcpwc { ++ compatible = "sstar,infinity-rtcpwc"; ++ reg = <0x1F006800 0x200>; ++ interrupts=; //need to check ++ clocks = <&CLK_rtc>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "sstar,infinity-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ emac0: emac0 { ++ compatible = "sstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>,<&CLK_emac_tx_ref>,<&CLK_emac_rx_ref>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F2A2800 0x600>; ++ //reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x00000000 0x000>; // for RMII ++ pad = <0x1F2079B8 0x0001 0x0001>; // for RMII ++ pad_led = <0x1F20798C 0x0077 0x0021>; ++ phy-handle = <&phy0>; ++ status = "ok"; ++ mdio-bus { ++ phy0: ethernet-phy@0 { ++ phy-mode = "mii"; ++ }; ++ }; ++ }; ++ ++ gpio:gpio{ ++ compatible = "sstar,gpio"; ++ }; ++ ++ pwm { ++ compatible = "sstar,infinity-pwm"; ++ reg = <0x1F203200 0x400>; /* NonPM-PWM(BK:x1019 and x101A) */ ++ npwm = <11>; ++ pm_group_base = <0x1F003400>; ++ clocks = <&CLK_pwm>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts=; //Only4i6e; Others, pls check hold0 int supporting. ++ pad-ctrl = ; ++ status = "ok"; ++ }; ++ ++ aesdma { ++ compatible = "sstar,infinity-aes"; ++ interrupts=; ++ clocks = <&CLK_aesdma>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ status = "ok"; ++ }; ++ ++ miu { ++ compatible = "sstar,miu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ mmu { ++ compatible = "sstar,mmu"; ++ interrupts=; ++ status = "ok"; ++ }; ++ ++ timer { ++ compatible = "sstar,timer"; ++ reg = <0x1F006040 0x40>, <0x1F006080 0x40>, <0x1F0060C0 0x40>; ++ interrupts = , , ; ++ status = "ok"; ++ }; ++ ++ core_voltage { ++ vid_width = <2>; ++ vid_gpios = ; ++ vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 ++ }; ++ ++ Sstar-ehci-1 { ++ compatible = "Sstar-ehci-1"; ++ clocks = <&CLK_utmi>; ++#ifdef CONFIG_CAM_CLK ++ camclk = ; ++#endif ++ interrupts = ; ++ dpdm_swap=<0>; ++ power-enable-pad = ; ++ status = "ok"; ++ }; ++ ++ Sstar-udc { ++ compatible = "sstar,infinity-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ dwc3: dwc3 { ++ compatible = "snps,dwc3"; ++ reg = <0x1F344200 0xcfff>; ++ clocks = <&CLK_ns_top_i_m00>; ++ clock-names = "ss_clk"; ++ maximum-speed = "super-speed"; ++ interrupts = ; ++ interrupt-names = "dwc_usb3"; ++ phy_type = "utmi_wide"; ++ phys = <&phy>, <&phy>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; ++ }; ++ ++ iopower { ++ compatible = "sstar-iopower"; ++ reg = <0x1F002800 0x64>; ++ status = "disabled"; ++ }; ++ ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/sstar/include/infinity6e/reg_clks.h> ++ #include "infinity6e-clks.dtsi" ++}; +diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile +old mode 100644 +new mode 100755 +index 27f23b15b1ea..49858038ef68 +--- a/arch/arm/common/Makefile ++++ b/arch/arm/common/Makefile +@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o + obj-$(CONFIG_SHARP_LOCOMO) += locomo.o + obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o + obj-$(CONFIG_SHARP_SCOOP) += scoop.o ++obj-$(CONFIG_ARCH_SSTAR) += secure_cntvoff.o + obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o + obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o + CFLAGS_REMOVE_mcpm_entry.o = -pg +diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S +new file mode 100644 +index 000000000000..ab8126a408b5 +--- /dev/null ++++ b/arch/arm/common/secure_cntvoff.S +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2014 Renesas Electronics Corporation ++ * ++ * Initialization of CNTVOFF register from secure mode ++ * ++ */ ++ ++#include ++#include ++ ++ENTRY(secure_cntvoff_init) ++ .arch armv7-a ++ /* ++ * CNTVOFF has to be initialized either from non-secure Hypervisor ++ * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled ++ * then it should be handled by the secure code. The CPU must implement ++ * the virtualization extensions. ++ */ ++ cps #0x00000016 ++ mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ ++ orr r0, r1, #1 ++ mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ ++ isb ++ mov r0, #0 ++ mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ ++ isb ++ mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ ++ isb ++ cps #SVC_MODE ++ ret lr ++ENDPROC(secure_cntvoff_init) +diff --git a/arch/arm/configs/infinity2_ssc006a_s01a-s_defconfig b/arch/arm/configs/infinity2_ssc006a_s01a-s_defconfig +new file mode 100755 +index 000000000000..f630ca25d4c6 +--- /dev/null ++++ b/arch/arm/configs/infinity2_ssc006a_s01a-s_defconfig +@@ -0,0 +1,2786 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0x21000000 ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_INFINITY2=y ++# CONFIG_ARCH_MULTIPLATFORM is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2-msc006a-s01a-s" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_L2X0_PATCH=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++# CONFIG_SS_PROFILING_TIME is not set ++CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS=y ++CONFIG_MP_GLOBAL_TIMER_CLK=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0_PMU is not set ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_ARM_HEAVY_MB=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_458693 is not set ++# CONFIG_ARM_ERRATA_460075 is not set ++# CONFIG_ARM_ERRATA_742230 is not set ++# CONFIG_ARM_ERRATA_742231 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_743622 is not set ++# CONFIG_ARM_ERRATA_751472 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_SCU=y ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++CONFIG_MEMORY_START_ADDRESS=0x20000000 ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_XHCI_HCD=y ++# CONFIG_USB_XHCI_PLATFORM is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++# CONFIG_ARM_TIMER_SP804 is not set ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MSYS_PERF_TEST=y ++CONFIG_MSYS_BENCH_MEMORY_FUNC=y ++CONFIG_MSYS_MIU_PROTECT=y ++CONFIG_MSYS_DMEM_SYSFS_ALL=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_IVE=y ++# CONFIG_MS_WARP is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_VCORE_DVFS=y ++CONFIG_SSTAR_CEVAXM6=y ++# CONFIG_MS_GMAC is not set ++CONFIG_MS_NOE=y ++ ++# ++# SStar Network Offload Engine ++# ++CONFIG_NOE=y ++CONFIG_NOE_NO_CHECK_ACTIVE_SETMAC=y ++CONFIG_GE1_GMII_AN_EXTPHY=y ++CONFIG_MAC_TO_GIGAPHY_MODE_ADDR=0x1 ++CONFIG_NOE_GMAC2=y ++CONFIG_GE2_GMII_AN_EXTPHY=y ++CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2=0x3 ++# CONFIG_MDIO_IC1819 is not set ++CONFIG_NOE_RGMII_TX_DELAY_2NS=y ++# CONFIG_NOE_NETWORK_TASKLET_BH is not set ++# CONFIG_NOE_NETWORK_WORKQUEUE_BH is not set ++CONFIG_NOE_NAPI=y ++CONFIG_NOE_CHECKSUM_OFFLOAD=y ++CONFIG_NOE_HW_LRO=y ++CONFIG_NOE_HW_VLAN_TX=y ++# CONFIG_NOE_HW_VLAN_RX is not set ++CONFIG_NOE_TSO=y ++# CONFIG_NOE_ETHTOOL is not set ++CONFIG_NOE_QDMA=y ++# CONFIG_ESW_DOUBLE_VLAN_TAG is not set ++CONFIG_ETH_SKB_ALLOC_SELECT=y ++CONFIG_ETH_SLAB_ALLOC_SKB=y ++# CONFIG_ETH_PAGE_ALLOC_SKB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_SATA_HOST_1=m ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_0_readme_defconfig b/arch/arm/configs/infinity2m_0_readme_defconfig +new file mode 100755 +index 000000000000..447d53bfbe63 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_0_readme_defconfig +@@ -0,0 +1,21 @@ ++infinity2m_defconfig ++- FPGA: Not maintained anymore for FPGA ++ - infinity2m_fpga_defconfig ++- SPINAND ++ infinity2m_spinand_ssc010a_s01a_2Gb_defconfig ++ - DCDO ++ infinity2m_spinand_ssc010a_s01a_dcdo_defconfig: default DCDO ++ infinity2m_spinand_ssc010a_s01a_dcdo_test_defconfig: Temp developing for DCDO ramdisk ++ infinity2m_spinand_ssc010a_s01a_defconfig ++ infinity2m_spinand_ssc010a_ssr623_s01a_defconfig:??? ++ infinity2m_spinand_ssc011a_s01a_defconfig ++ infinity2m_spinand_ssc011a_s01a_minigui_defconfig:???? ++ infinity2m_spinand_ssc011a_s01a_minigui_fastboot ++- SPINOR ++ infinity2m_ssc010a_s01a_2Gb_defconfig ++ infinity2m_ssc010a_s01a_bench_defconfig ++ infinity2m_ssc010a_s01a_defconfig ++ infinity2m_ssc010a_ssr623_s01a_defconfig ++ infinity2m_ssc011a_s01a_defconfig ++ infinity2m_ssc011a_s01a_fastboot_defconfig ++ infinity2m_ssc011a_s01a_minigui_defconfig +diff --git a/arch/arm/configs/infinity2m_defconfig b/arch/arm/configs/infinity2m_defconfig +new file mode 100755 +index 000000000000..7ca2bfc2a884 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_defconfig +@@ -0,0 +1,2605 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_GPIO is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_RTC is not set ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_fpga_defconfig b/arch/arm/configs/infinity2m_fpga_defconfig +new file mode 100755 +index 000000000000..7eb00787f6f9 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_fpga_defconfig +@@ -0,0 +1,2533 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++# CONFIG_ARCH_INFINITY5 is not set ++# CONFIG_ARCH_INFINITY6 is not set ++CONFIG_ARCH_INFINITY2M=y ++CONFIG_INFINITY2M_FPGA=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++# CONFIG_SMP_ON_UP is not set ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_SSTAR_PHY is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++CONFIG_FPGA=y ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMAC is not set ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_GPIO is not set ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++# CONFIG_MS_CRYPTO is not set ++# CONFIG_MS_CPU_FREQ is not set ++# CONFIG_MS_PM is not set ++# CONFIG_MS_ISRCB_INFINITY6 is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++# CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_2Gb_defconfig b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_2Gb_defconfig +new file mode 100755 +index 000000000000..1d41df4ad045 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_2Gb_defconfig +@@ -0,0 +1,2841 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc010a-s01a-2Gb" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_amp_defconfig b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_amp_defconfig +new file mode 100755 +index 000000000000..99624c1d8c8c +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_amp_defconfig +@@ -0,0 +1,2745 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc010a-s01a-amp" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=m ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=m ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=m ++CONFIG_RC_MAP=m ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=m ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=m ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=m ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=m ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_SATA_HOST is not set ++CONFIG_MS_IR=m ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_defconfig b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_defconfig +new file mode 100755 +index 000000000000..40f5470fe70f +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_defconfig +@@ -0,0 +1,2841 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc010a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_swtoe_defconfig b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_swtoe_defconfig +new file mode 100755 +index 000000000000..e038665dcd4f +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc010a_s01a_swtoe_defconfig +@@ -0,0 +1,2747 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc010a-s01a-amp" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=m ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=m ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=m ++CONFIG_RC_MAP=m ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=m ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=m ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=m ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++# CONFIG_MS_EMAC is not set ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_SATA_HOST is not set ++CONFIG_MS_IR=m ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_SWTOE=y ++CONFIG_MS_EMAC_TOE=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc010a_ssr623_s01a_defconfig b/arch/arm/configs/infinity2m_spinand_ssc010a_ssr623_s01a_defconfig +new file mode 100755 +index 000000000000..7a5132053d24 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc010a_ssr623_s01a_defconfig +@@ -0,0 +1,2845 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc010a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_defconfig b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_defconfig +new file mode 100755 +index 000000000000..d22e2fdf7afe +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_defconfig +@@ -0,0 +1,2804 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_display_for_mipi_defconfig b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_display_for_mipi_defconfig +new file mode 100755 +index 000000000000..32a458ca67cc +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_display_for_mipi_defconfig +@@ -0,0 +1,2804 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-display_for_mipi" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_minigui_defconfig b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_minigui_defconfig +new file mode 100755 +index 000000000000..aa430b1dfd58 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_minigui_defconfig +@@ -0,0 +1,2990 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=y ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SUR40 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_RC_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=y ++CONFIG_VIDEOBUF2_MEMOPS=y ++CONFIG_VIDEOBUF2_VMALLOC=y ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_MEDIA_USB_SUPPORT=y ++ ++# ++# Webcam devices ++# ++CONFIG_SS_HOST_UVC=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++# CONFIG_USB_GSPCA is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++ ++# ++# Webcam, TV (analog/digital) USB devices ++# ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++CONFIG_UHID=y ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_RTC is not set ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_minigui_fastboot_defconfig b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_minigui_fastboot_defconfig +new file mode 100755 +index 000000000000..dd336d8f801d +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_minigui_fastboot_defconfig +@@ -0,0 +1,2801 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++CONFIG_RD_BZIP2=y ++CONFIG_RD_LZMA=y ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++CONFIG_RD_LZ4=y ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=m ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=m ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=m ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=m ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++CONFIG_UHID=y ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=m ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_SATA_HOST is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_RTC is not set ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=m ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_LZ4_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_BZIP2=y ++CONFIG_DECOMPRESS_LZMA=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_DECOMPRESS_LZ4=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_rgb565-rmii_defconfig b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_rgb565-rmii_defconfig +new file mode 100755 +index 000000000000..2522e244dc5c +--- /dev/null ++++ b/arch/arm/configs/infinity2m_spinand_ssc011a_s01a_rgb565-rmii_defconfig +@@ -0,0 +1,2804 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-rgb565-rmii" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc010a_s01a_2Gb_defconfig b/arch/arm/configs/infinity2m_ssc010a_s01a_2Gb_defconfig +new file mode 100755 +index 000000000000..1944a6a9c7cb +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc010a_s01a_2Gb_defconfig +@@ -0,0 +1,2817 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc010a-s01a-2Gb" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc010a_s01a_bench_defconfig b/arch/arm/configs/infinity2m_ssc010a_s01a_bench_defconfig +new file mode 100755 +index 000000000000..1c85296a0fa5 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc010a_s01a_bench_defconfig +@@ -0,0 +1,2842 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc010a-s01a-bench" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=y ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc010a_s01a_defconfig b/arch/arm/configs/infinity2m_ssc010a_s01a_defconfig +new file mode 100755 +index 000000000000..5f7313a04df4 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc010a_s01a_defconfig +@@ -0,0 +1,2817 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc010a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc010a_ssr623_s01a_defconfig b/arch/arm/configs/infinity2m_ssc010a_ssr623_s01a_defconfig +new file mode 100755 +index 000000000000..07dd14e8de9d +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc010a_ssr623_s01a_defconfig +@@ -0,0 +1,2876 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc010a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc011a_s01a_defconfig b/arch/arm/configs/infinity2m_ssc011a_s01a_defconfig +new file mode 100755 +index 000000000000..33cc3d3bccc5 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc011a_s01a_defconfig +@@ -0,0 +1,2840 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc011a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc011a_s01a_display_for_mipi_defconfig b/arch/arm/configs/infinity2m_ssc011a_s01a_display_for_mipi_defconfig +new file mode 100755 +index 000000000000..c04af64db0be +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc011a_s01a_display_for_mipi_defconfig +@@ -0,0 +1,2840 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc011a-s01a-display_for_mipi" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc011a_s01a_fastboot_defconfig b/arch/arm/configs/infinity2m_ssc011a_s01a_fastboot_defconfig +new file mode 100755 +index 000000000000..b33d2a611237 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc011a_s01a_fastboot_defconfig +@@ -0,0 +1,2766 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc011a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=4 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++# CONFIG_MTD_UBI is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=m ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=m ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=m ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=m ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=m ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=m ++CONFIG_ICPLUS_PHY=m ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=m ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++# CONFIG_ANDROID is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=m ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=m ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=m ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=m ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=m ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++# CONFIG_SQUASHFS_ZLIB is not set ++# CONFIG_SQUASHFS_LZ4 is not set ++# CONFIG_SQUASHFS_LZO is not set ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc011a_s01a_minigui_defconfig b/arch/arm/configs/infinity2m_ssc011a_s01a_minigui_defconfig +new file mode 100755 +index 000000000000..4498a61453a9 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc011a_s01a_minigui_defconfig +@@ -0,0 +1,2955 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc011a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=y ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_RC_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=y ++CONFIG_VIDEOBUF2_MEMOPS=y ++CONFIG_VIDEOBUF2_VMALLOC=y ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_MEDIA_USB_SUPPORT=y ++ ++# ++# Webcam devices ++# ++CONFIG_SS_HOST_UVC=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++# CONFIG_USB_GSPCA is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++ ++# ++# Webcam, TV (analog/digital) USB devices ++# ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc011a_s01a_minigui_shrink b/arch/arm/configs/infinity2m_ssc011a_s01a_minigui_shrink +new file mode 100644 +index 000000000000..52a7db4e8235 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc011a_s01a_minigui_shrink +@@ -0,0 +1,2645 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++# CONFIG_KALLSYMS is not set ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc011a-s01a-display" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++# CONFIG_ANALOG_PD_HDMI_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_ATOP is not set ++# CONFIG_ANALOG_PD_IDAC_LPLL is not set ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++# CONFIG_ANALOG_PD_SATA_ATOP is not set ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_CRYPTO is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_SATA_HOST is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_UBIFS_FS is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++# CONFIG_SQUASHFS_LZO is not set ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++# CONFIG_SG_POOL is not set ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity2m_ssc011a_s01a_rgb565-rmii_defconfig b/arch/arm/configs/infinity2m_ssc011a_s01a_rgb565-rmii_defconfig +new file mode 100755 +index 000000000000..2f40d48f9891 +--- /dev/null ++++ b/arch/arm/configs/infinity2m_ssc011a_s01a_rgb565-rmii_defconfig +@@ -0,0 +1,2840 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity2m-ssc011a-s01a-rgb565-rmii" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity2m" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY2M=y ++# CONFIG_INFINITY2M_FPGA is not set ++# CONFIG_ANALOG_PD_AUDIO is not set ++# CONFIG_ANALOG_PD_EMAC is not set ++CONFIG_ANALOG_PD_HDMI_ATOP=y ++CONFIG_ANALOG_PD_IDAC_ATOP=y ++CONFIG_ANALOG_PD_IDAC_LPLL=y ++# CONFIG_ANALOG_PD_DISP_LPLL is not set ++# CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP is not set ++CONFIG_ANALOG_PD_SATA_ATOP=y ++# CONFIG_ANALOG_PD_UPLL_0 is not set ++# CONFIG_ANALOG_PD_UPLL_1 is not set ++# CONFIG_ANALOG_PD_USB20_P1 is not set ++# CONFIG_ANALOG_PD_USB20_P2 is not set ++# CONFIG_ANALOG_PD_USB20_P3 is not set ++# CONFIG_SS_PROFILING_TIME is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++CONFIG_ATA_SFF=y ++ ++# ++# SFF controllers with custom DMA interface ++# ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# ++ ++# ++# PATA SFF controllers with BMDMA ++# ++ ++# ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_PLATFORM is not set ++ ++# ++# Generic fallback / legacy drivers ++# ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++CONFIG_ICPLUS_PHY=y ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++# CONFIG_CONSOLE_TRANSLATIONS is not set ++# CONFIG_VT_CONSOLE is not set ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++CONFIG_RC_MAP=y ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++# CONFIG_MS_SDMMC_TCARD is not set ++# CONFIG_MS_SDMMC_REVWP is not set ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++# CONFIG_MS_SDMMC1_INTCDZ is not set ++# CONFIG_MS_SDMMC1_FAKECDZ is not set ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++# CONFIG_MS_SDMMC2_INTCDZ is not set ++# CONFIG_MS_SDMMC2_FAKECDZ is not set ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_INTCDZ is not set ++# CONFIG_MS_SDMMC3_FAKECDZ is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++CONFIG_SS_SATA_HOST=y ++ ++# ++# Support Linux Ahci Platfrom Driver ++# ++CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y ++ ++# ++# Select Sata Host Port ++# ++CONFIG_SATA_HOST_0=m ++CONFIG_MS_IR=y ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity3_defconfig b/arch/arm/configs/infinity3_defconfig +new file mode 100755 +index 000000000000..a60df45fcdfc +--- /dev/null ++++ b/arch/arm/configs/infinity3_defconfig +@@ -0,0 +1,2455 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++CONFIG_ARCH_INFINITY3=y ++# CONFIG_ARCH_INFINITY5 is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity3" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++# CONFIG_PHYLIB is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++# CONFIG_MS_USB_INFINITY3 is not set ++# CONFIG_MS_EMAC is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY3=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++# CONFIG_MS_WATCHDOG is not set ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY3=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=m ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++# CONFIG_MS_IVE is not set ++# CONFIG_MS_NOTIFY is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity3_uvc_defconfig b/arch/arm/configs/infinity3_uvc_defconfig +new file mode 100755 +index 000000000000..490b6d0a71ea +--- /dev/null ++++ b/arch/arm/configs/infinity3_uvc_defconfig +@@ -0,0 +1,2530 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.30 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_RESOURCE_COUNTERS is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++# CONFIG_TIMERFD is not set ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++CONFIG_ARCH_INFINITY3=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity3" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++# CONFIG_ARM_VIRT_EXT is not set ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++# CONFIG_CMA_BUFFER_LIST is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPUFREQ_DT is not set ++ ++# ++# ARM CPU frequency scaling drivers ++# ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++CONFIG_INET_LRO=y ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_REG_DEBUG is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++# CONFIG_PHYLIB is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_ATH_CARDS is not set ++# CONFIG_BRCMFMAC is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_LIBERTAS is not set ++# CONFIG_WL_TI is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_MT7601U=m ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2_SUBDEV_API=y ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++CONFIG_USB_PHY=y ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++CONFIG_MS_OTG_ENABLE=y ++CONFIG_USB_MS_OTG=m ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++CONFIG_USB_GADGET_MSB250X=m ++CONFIG_USB_MSB250X=m ++CONFIG_USB_MSB250X_DMA=m ++# CONFIG_USB_MSB250X_DEBUG is not set ++# CONFIG_USB_MSB250X_PROC is not set ++# CONFIG_USB_MSB250X_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_G_ANDROID is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12057 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_XGENE is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++# CONFIG_LINE6_USB is not set ++# CONFIG_BCM_WIMAX is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=m ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++# CONFIG_ASHMEM is not set ++CONFIG_ANDROID_LOGGER=y ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ANDROID_INTF_ALARM_DEV is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_USB_WPAN_HCD is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_TI_CMEM=m ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_USCLK=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY3=y ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_INFINITY3=y ++CONFIG_MS_USB_INFINITY3=m ++CONFIG_MS_FB=y ++CONFIG_MS_FB_INFINITY3=y ++CONFIG_MS_FB1_INFINITY3=y ++CONFIG_MS_FB2_INFINITY3=y ++CONFIG_MS_SCL=y ++CONFIG_MS_SCL_INFINITY3=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++CONFIG_ETHERNET_ALBANY=y ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY3=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MS_IRCUT=y ++CONFIG_MS_VHE=y ++CONFIG_MS_MFEV5=y ++CONFIG_MS_RTC=y ++CONFIG_MS_JPE=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY3=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=m ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++CONFIG_CRYPTO_SEQIV=y ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_ZLIB=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_defconfig b/arch/arm/configs/infinity5_defconfig +new file mode 100755 +index 000000000000..6f8c876bd6ee +--- /dev/null ++++ b/arch/arm/configs/infinity5_defconfig +@@ -0,0 +1,2722 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-BGA128M" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=m ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=m ++CONFIG_SND_PCM=m ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=m ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=m ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_CAM_DRIVERS=y ++CONFIG_MS_CMDQ=m ++# CONFIG_MS_USE_AUTOMODE is not set ++CONFIG_MS_VENC=y ++CONFIG_MS_VENC_INFINITY5=m ++CONFIG_MS_VIF=y ++CONFIG_MS_VIF_INFINITY5=m ++CONFIG_MS_CSI=y ++CONFIG_MS_CSI_INFINITY5=m ++CONFIG_MS_SCL=m ++# CONFIG_MS_SCL_USBCAM is not set ++CONFIG_MS_SCL_INFINITY5=m ++CONFIG_MS_RGN=m ++CONFIG_MS_RGN_INFINITY5=m ++CONFIG_MS_ISPALGO=m ++CONFIG_MS_ISPALGO_INFINITY5=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY5=m ++CONFIG_MS_ISP_MID=y ++CONFIG_MS_ISP_MIDDLEWARE_INFINITY5=m ++CONFIG_MS_MLOAD=y ++CONFIG_MS_MLOAD_INFINITY5=m ++CONFIG_MS_SENSORIF=y ++CONFIG_MS_SENSORIF_INFINITY5=m ++CONFIG_MS_SENSORDRIVER=y ++CONFIG_MS_SENSORDRIVER_INFINITY=m ++# CONFIG_MS_MIDDLE is not set ++CONFIG_MS_DIP=m ++# CONFIG_MS_DIP_INFINITY5 is not set ++CONFIG_MS_AIO=m ++CONFIG_MS_AIO_INFINITY5=m ++CONFIG_MS_LDC=m ++CONFIG_MS_DSPY=m ++CONFIG_MS_PNL=m ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_dev_defconfig b/arch/arm/configs/infinity5_dev_defconfig +new file mode 100755 +index 000000000000..b1560be29e1f +--- /dev/null ++++ b/arch/arm/configs/infinity5_dev_defconfig +@@ -0,0 +1,2488 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++CONFIG_INFINITY5_FPGA=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-alkaid" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++# CONFIG_RTC_SYSTOHC is not set ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++# CONFIG_RTC_INTF_SYSFS is not set ++# CONFIG_RTC_INTF_PROC is not set ++# CONFIG_RTC_INTF_DEV is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++# CONFIG_MS_GPIO is not set ++CONFIG_MS_WATCHDOG=m ++CONFIG_MS_SAR=m ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=m ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_MS_CPU_FREQ is not set ++CONFIG_MS_PWM=m ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=m ++# CONFIG_MS_PM is not set ++# CONFIG_MS_IVE is not set ++CONFIG_SS_ISP_ISRCB=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_fpga_defconfig b/arch/arm/configs/infinity5_fpga_defconfig +new file mode 100755 +index 000000000000..67c01f66d639 +--- /dev/null ++++ b/arch/arm/configs/infinity5_fpga_defconfig +@@ -0,0 +1,2480 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++CONFIG_INFINITY5_FPGA=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-fpga" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++# CONFIG_PHYLIB is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++# CONFIG_RTC_SYSTOHC is not set ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++# CONFIG_RTC_INTF_SYSFS is not set ++# CONFIG_RTC_INTF_PROC is not set ++# CONFIG_RTC_INTF_DEV is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_ETHERNET_ALBANY is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++# CONFIG_MS_GPIO is not set ++CONFIG_MS_WATCHDOG=m ++CONFIG_MS_SAR=m ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=m ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_MS_CPU_FREQ is not set ++CONFIG_MS_PWM=m ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=m ++# CONFIG_MS_PM is not set ++# CONFIG_MS_IVE is not set ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_CAM_DRIVERS=y ++CONFIG_MS_CMDQ=m ++# CONFIG_MS_USE_AUTOMODE is not set ++CONFIG_MS_VENC=y ++CONFIG_MS_VENC_INFINITY5=m ++CONFIG_MS_VIF=y ++CONFIG_MS_VIF_INFINITY5=m ++CONFIG_MS_CSI=y ++CONFIG_MS_CSI_INFINITY5=m ++CONFIG_MS_SCL=m ++# CONFIG_MS_SCL_USBCAM is not set ++CONFIG_MS_SCL_INFINITY5=m ++CONFIG_MS_GOP=y ++CONFIG_MS_GOP_INFINITY5=m ++CONFIG_MS_COVER=y ++CONFIG_MS_COVER_INFINITY5=m ++CONFIG_MS_RGN=y ++CONFIG_MS_RGN_INFINITY5=m ++CONFIG_MS_ISPALGO=m ++CONFIG_MS_ISPALGO_INFINITY5=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY5=m ++CONFIG_MS_ISP_MID=y ++CONFIG_MS_ISP_MIDDLEWARE_INFINITY5=m ++CONFIG_MS_MLOAD=y ++CONFIG_MS_MLOAD_INFINITY5=m ++CONFIG_MS_SENSORIF=y ++CONFIG_MS_SENSORIF_INFINITY5=m ++# CONFIG_MS_MIDDLE is not set ++CONFIG_MS_DIP=m ++CONFIG_MS_AIO=m ++CONFIG_MS_AIO_INFINITY5=m ++CONFIG_MS_LDC=m ++# CONFIG_MS_PNL is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_spinand_defconfig b/arch/arm/configs/infinity5_spinand_defconfig +new file mode 100755 +index 000000000000..d4747067d065 +--- /dev/null ++++ b/arch/arm/configs/infinity5_spinand_defconfig +@@ -0,0 +1,2721 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-BGA128M" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=m ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=m ++CONFIG_SND_PCM=m ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=m ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=m ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_CAM_DRIVERS=y ++CONFIG_MS_CMDQ=m ++# CONFIG_MS_USE_AUTOMODE is not set ++CONFIG_MS_VENC=y ++CONFIG_MS_VENC_INFINITY5=m ++CONFIG_MS_VIF=y ++CONFIG_MS_VIF_INFINITY5=m ++CONFIG_MS_CSI=y ++CONFIG_MS_CSI_INFINITY5=m ++CONFIG_MS_SCL=m ++# CONFIG_MS_SCL_USBCAM is not set ++CONFIG_MS_SCL_INFINITY5=m ++CONFIG_MS_RGN=m ++CONFIG_MS_RGN_INFINITY5=m ++CONFIG_MS_ISPALGO=m ++CONFIG_MS_ISPALGO_INFINITY5=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY5=m ++CONFIG_MS_ISP_MID=y ++CONFIG_MS_ISP_MIDDLEWARE_INFINITY5=m ++CONFIG_MS_MLOAD=y ++CONFIG_MS_MLOAD_INFINITY5=m ++CONFIG_MS_SENSORIF=y ++CONFIG_MS_SENSORIF_INFINITY5=m ++CONFIG_MS_SENSORDRIVER=y ++CONFIG_MS_SENSORDRIVER_INFINITY=m ++# CONFIG_MS_MIDDLE is not set ++CONFIG_MS_DIP=m ++# CONFIG_MS_DIP_INFINITY5 is not set ++CONFIG_MS_AIO=m ++CONFIG_MS_AIO_INFINITY5=m ++CONFIG_MS_LDC=m ++CONFIG_MS_DSPY=m ++CONFIG_MS_PNL=m ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_at520d_s01a_spinand_defconfig b/arch/arm/configs/infinity5_ssc007a_at520d_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..79c0963733a6 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_at520d_s01a_spinand_defconfig +@@ -0,0 +1,2689 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-at520d-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_s01a_coprocessor_defconfig b/arch/arm/configs/infinity5_ssc007a_s01a_coprocessor_defconfig +new file mode 100755 +index 000000000000..9a53ffa43911 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_s01a_coprocessor_defconfig +@@ -0,0 +1,2737 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++CONFIG_USB_GADGET_MSB250X=m ++CONFIG_USB_MSB250X=m ++CONFIG_USB_MSB250X_DMA=m ++# CONFIG_USB_MSB250X_DEBUG is not set ++# CONFIG_USB_MSB250X_PROC is not set ++# CONFIG_USB_MSB250X_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_USB_F_BI_DIRECTION=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_BI_DIRECTION=m ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_s01a_defconfig b/arch/arm/configs/infinity5_ssc007a_s01a_defconfig +new file mode 100755 +index 000000000000..8393143cac38 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_s01a_defconfig +@@ -0,0 +1,2689 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_s01a_spinand_coprocessor_defconfig b/arch/arm/configs/infinity5_ssc007a_s01a_spinand_coprocessor_defconfig +new file mode 100755 +index 000000000000..6bdb05d25a02 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_s01a_spinand_coprocessor_defconfig +@@ -0,0 +1,2737 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++CONFIG_USB_GADGET_MSB250X=m ++CONFIG_USB_MSB250X=m ++CONFIG_USB_MSB250X_DMA=m ++# CONFIG_USB_MSB250X_DEBUG is not set ++# CONFIG_USB_MSB250X_PROC is not set ++# CONFIG_USB_MSB250X_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_USB_F_BI_DIRECTION=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_BI_DIRECTION=m ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_s01a_spinand_defconfig b/arch/arm/configs/infinity5_ssc007a_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..4a2a854a72b7 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_s01a_spinand_defconfig +@@ -0,0 +1,2690 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_s01a_spinand_uvc_defconfig b/arch/arm/configs/infinity5_ssc007a_s01a_spinand_uvc_defconfig +new file mode 100755 +index 000000000000..66ffa4b62d8c +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_s01a_spinand_uvc_defconfig +@@ -0,0 +1,2836 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++CONFIG_USB_GADGET_MSB250X=m ++CONFIG_USB_MSB250X=m ++CONFIG_USB_MSB250X_DMA=m ++# CONFIG_USB_MSB250X_DEBUG is not set ++# CONFIG_USB_MSB250X_PROC is not set ++# CONFIG_USB_MSB250X_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007a_s01a_uvc_defconfig b/arch/arm/configs/infinity5_ssc007a_s01a_uvc_defconfig +new file mode 100755 +index 000000000000..0b274527faa2 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007a_s01a_uvc_defconfig +@@ -0,0 +1,2829 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_UAC is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01a_defconfig b/arch/arm/configs/infinity5_ssc007b_s01a_defconfig +new file mode 100755 +index 000000000000..9309cd19d19f +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01a_defconfig +@@ -0,0 +1,2688 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01a_spinand_defconfig b/arch/arm/configs/infinity5_ssc007b_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..cdfe1b9952b2 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01a_spinand_defconfig +@@ -0,0 +1,2688 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01a_spinand_uvc_defconfig b/arch/arm/configs/infinity5_ssc007b_s01a_spinand_uvc_defconfig +new file mode 100755 +index 000000000000..caada0fd992b +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01a_spinand_uvc_defconfig +@@ -0,0 +1,2827 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_UAC is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01a_uvc_defconfig b/arch/arm/configs/infinity5_ssc007b_s01a_uvc_defconfig +new file mode 100755 +index 000000000000..ee8806d3a286 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01a_uvc_defconfig +@@ -0,0 +1,2785 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++# CONFIG_PHYLIB is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_UAC is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01b_defconfig b/arch/arm/configs/infinity5_ssc007b_s01b_defconfig +new file mode 100755 +index 000000000000..4465c6888e6e +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01b_defconfig +@@ -0,0 +1,2688 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01b" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01b_spinand_defconfig b/arch/arm/configs/infinity5_ssc007b_s01b_spinand_defconfig +new file mode 100755 +index 000000000000..106192185bb1 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01b_spinand_defconfig +@@ -0,0 +1,2688 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++# CONFIG_ARCH_INFINITY3 is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01b" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY5=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY5=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01b_spinand_uvc_defconfig b/arch/arm/configs/infinity5_ssc007b_s01b_spinand_uvc_defconfig +new file mode 100755 +index 000000000000..4ca9f70ebc10 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01b_spinand_uvc_defconfig +@@ -0,0 +1,2827 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01b" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_UAC is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity5_ssc007b_s01b_uvc_defconfig b/arch/arm/configs/infinity5_ssc007b_s01b_uvc_defconfig +new file mode 100755 +index 000000000000..a8517ff1ada3 +--- /dev/null ++++ b/arch/arm/configs/infinity5_ssc007b_s01b_uvc_defconfig +@@ -0,0 +1,2827 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity5-ssc007b-s01b" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity5" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY5=y ++# CONFIG_INFINITY5_FPGA is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARM_MODULE_PLTS=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_PCM=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_PCM_TIMER is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_AC97_CODEC is not set ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_RT5677_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_SIMPLE_SCU_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++CONFIG_USB_AUDIO=m ++CONFIG_GADGET_UAC1=y ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_UAC is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_PWRSEQ_EMMC is not set ++# CONFIG_PWRSEQ_SIMPLE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_MSYS_LOG=y ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_defconfig b/arch/arm/configs/infinity6_defconfig +new file mode 100755 +index 000000000000..f297403d2a0d +--- /dev/null ++++ b/arch/arm/configs/infinity6_defconfig +@@ -0,0 +1,2537 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_CRYPTO=y ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_spinand_defconfig b/arch/arm/configs/infinity6_spinand_defconfig +new file mode 100755 +index 000000000000..24bed31cbe35 +--- /dev/null ++++ b/arch/arm/configs/infinity6_spinand_defconfig +@@ -0,0 +1,2544 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_MP_IRQ_TRACE=y ++# CONFIG_DISABLE_DTS_DEBUGNODE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_spinand_uvc_defconfig b/arch/arm/configs/infinity6_spinand_uvc_defconfig +new file mode 100755 +index 000000000000..5d6b7653de86 +--- /dev/null ++++ b/arch/arm/configs/infinity6_spinand_uvc_defconfig +@@ -0,0 +1,2776 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009a_s01a_lh_defconfig b/arch/arm/configs/infinity6_ssc009a_s01a_lh_defconfig +new file mode 100755 +index 000000000000..05a99303fcfc +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009a_s01a_lh_defconfig +@@ -0,0 +1,2563 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++CONFIG_LH_RTOS=y ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a-lh" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_MORE_SYSFS=y ++CONFIG_DEFERRED_CREATE_DTS_SYSNODE=y ++CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=m ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MSTAR_MMAHEAP is not set ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009a_s01a_spinand_lh_defconfig b/arch/arm/configs/infinity6_ssc009a_s01a_spinand_lh_defconfig +new file mode 100755 +index 000000000000..f98f6db349a6 +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009a_s01a_spinand_lh_defconfig +@@ -0,0 +1,2558 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++CONFIG_LH_RTOS=y ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-spinand-ssc009a-s01a-lh" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MSTAR_MMAHEAP is not set ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009b_s01a_defconfig b/arch/arm/configs/infinity6_ssc009b_s01a_defconfig +new file mode 100755 +index 000000000000..ded4c4616da0 +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009b_s01a_defconfig +@@ -0,0 +1,2537 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_MS_CRYPTO=y ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009b_s01a_lh_defconfig b/arch/arm/configs/infinity6_ssc009b_s01a_lh_defconfig +new file mode 100755 +index 000000000000..2f28c100e084 +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009b_s01a_lh_defconfig +@@ -0,0 +1,2563 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++CONFIG_LH_RTOS=y ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009b-s01a-lh" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_MORE_SYSFS=y ++CONFIG_DEFERRED_CREATE_DTS_SYSNODE=y ++CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=m ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MSTAR_MMAHEAP is not set ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009b_s01a_lowpower_noether_defconfig b/arch/arm/configs/infinity6_ssc009b_s01a_lowpower_noether_defconfig +new file mode 100755 +index 000000000000..45a0164bd7b9 +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009b_s01a_lowpower_noether_defconfig +@@ -0,0 +1,2612 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_LH_RTOS=y ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009b-s01a-lh" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_MORE_SYSFS=y ++CONFIG_DEFERRED_CREATE_DTS_SYSNODE=y ++CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++CONFIG_NET_IP_TUNNEL=y ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_NET_FOU_IP_TUNNELS is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++CONFIG_INET_TUNNEL=y ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_INET_DIAG_DESTROY is not set ++CONFIG_TCP_CONG_ADVANCED=y ++CONFIG_TCP_CONG_BIC=m ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_TCP_CONG_WESTWOOD=m ++CONFIG_TCP_CONG_HTCP=m ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=y ++# CONFIG_IPV6_ROUTER_PREF is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++# CONFIG_INET6_XFRM_TUNNEL is not set ++# CONFIG_INET6_TUNNEL is not set ++CONFIG_INET6_XFRM_MODE_TRANSPORT=y ++CONFIG_INET6_XFRM_MODE_TUNNEL=y ++CONFIG_INET6_XFRM_MODE_BEET=y ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++# CONFIG_IPV6_VTI is not set ++CONFIG_IPV6_SIT=y ++# CONFIG_IPV6_SIT_6RD is not set ++CONFIG_IPV6_NDISC_NODETYPE=y ++# CONFIG_IPV6_TUNNEL is not set ++# CONFIG_IPV6_FOU is not set ++# CONFIG_IPV6_FOU_TUNNEL is not set ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_6LOWPAN is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++# CONFIG_CFG80211 is not set ++# CONFIG_LIB80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++CONFIG_DST_CACHE=y ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_NET_CORE=y ++# CONFIG_BONDING is not set ++# CONFIG_DUMMY is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_TEAM is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_VXLAN is not set ++# CONFIG_MACSEC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_TUN is not set ++# CONFIG_TUN_VNET_CROSS_LE is not set ++# CONFIG_VETH is not set ++# CONFIG_NLMON is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++CONFIG_ETHERNET=y ++# CONFIG_ALTERA_TSE is not set ++CONFIG_NET_VENDOR_AMAZON=y ++CONFIG_NET_VENDOR_ARC=y ++# CONFIG_ARC_EMAC is not set ++# CONFIG_NET_VENDOR_AURORA is not set ++CONFIG_NET_CADENCE=y ++# CONFIG_MACB is not set ++CONFIG_NET_VENDOR_BROADCOM=y ++# CONFIG_B44 is not set ++# CONFIG_BCMGENET is not set ++# CONFIG_SYSTEMPORT is not set ++CONFIG_NET_VENDOR_CIRRUS=y ++# CONFIG_CS89x0 is not set ++# CONFIG_DM9000 is not set ++# CONFIG_DNET is not set ++CONFIG_NET_VENDOR_EZCHIP=y ++# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set ++CONFIG_NET_VENDOR_FARADAY=y ++# CONFIG_FTMAC100 is not set ++# CONFIG_FTGMAC100 is not set ++CONFIG_NET_VENDOR_HISILICON=y ++# CONFIG_HIX5HD2_GMAC is not set ++# CONFIG_HISI_FEMAC is not set ++# CONFIG_HIP04_ETH is not set ++# CONFIG_HNS is not set ++# CONFIG_HNS_DSAF is not set ++# CONFIG_HNS_ENET is not set ++CONFIG_NET_VENDOR_INTEL=y ++CONFIG_NET_VENDOR_I825XX=y ++CONFIG_NET_VENDOR_MARVELL=y ++# CONFIG_MVMDIO is not set ++# CONFIG_MVNETA_BM is not set ++CONFIG_NET_VENDOR_MICREL=y ++# CONFIG_KS8851 is not set ++# CONFIG_KS8851_MLL is not set ++CONFIG_NET_VENDOR_MICROCHIP=y ++# CONFIG_ENC28J60 is not set ++# CONFIG_ENCX24J600 is not set ++CONFIG_NET_VENDOR_NATSEMI=y ++CONFIG_NET_VENDOR_NETRONOME=y ++CONFIG_NET_VENDOR_8390=y ++# CONFIG_AX88796 is not set ++# CONFIG_ETHOC is not set ++CONFIG_NET_VENDOR_QUALCOMM=y ++# CONFIG_QCA7000 is not set ++# CONFIG_QCOM_EMAC is not set ++CONFIG_NET_VENDOR_RENESAS=y ++CONFIG_NET_VENDOR_ROCKER=y ++CONFIG_NET_VENDOR_SAMSUNG=y ++# CONFIG_SXGBE_ETH is not set ++CONFIG_NET_VENDOR_SEEQ=y ++CONFIG_NET_VENDOR_SMSC=y ++# CONFIG_SMC91X is not set ++# CONFIG_SMC911X is not set ++# CONFIG_SMSC911X is not set ++CONFIG_NET_VENDOR_STMICRO=y ++# CONFIG_STMMAC_ETH is not set ++CONFIG_NET_VENDOR_SYNOPSYS=y ++# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set ++CONFIG_NET_VENDOR_VIA=y ++# CONFIG_VIA_RHINE is not set ++# CONFIG_VIA_VELOCITY is not set ++CONFIG_NET_VENDOR_WIZNET=y ++# CONFIG_WIZNET_W5100 is not set ++# CONFIG_WIZNET_W5300 is not set ++# CONFIG_PHYLIB is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++CONFIG_IOT=y ++CONFIG_IOT_MTK=y ++ ++# ++# MTK IoT device drivers ++# ++CONFIG_MT7682=y ++# CONFIG_IOT_MTK_ONLY_WAKEUP_BY_GPIO is not set ++CONFIG_MTK_IOT_USE_SDIO=y ++CONFIG_IOT_NUM_TX_QUEUE_THRESHOLD=200 ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=m ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++# CONFIG_MS_EMAC is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MSTAR_MMAHEAP is not set ++# CONFIG_SSTAR_NETPHY is not set ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++# CONFIG_NFS_FS is not set ++# CONFIG_NFSD is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009b_s01a_spinand_defconfig b/arch/arm/configs/infinity6_ssc009b_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..ca416a7ecf3e +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009b_s01a_spinand_defconfig +@@ -0,0 +1,2544 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_MP_IRQ_TRACE=y ++# CONFIG_DISABLE_DTS_DEBUGNODE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ssc009b_s01a_spinand_quad_defconfig b/arch/arm/configs/infinity6_ssc009b_s01a_spinand_quad_defconfig +new file mode 100755 +index 000000000000..d3fffceb0570 +--- /dev/null ++++ b/arch/arm/configs/infinity6_ssc009b_s01a_spinand_quad_defconfig +@@ -0,0 +1,2541 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_SSTAR_PHY is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++CONFIG_NAND_QUAL_READ=y ++# CONFIG_AUTO_DETECT is not set ++CONFIG_NAND_QUAL_WRITE=y ++# CONFIG_AUTO_DETECT_WRITE is not set ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=y ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=y ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++# CONFIG_MS_PADMUX is not set ++# CONFIG_MS_WATCHDOG is not set ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_test_fb_initrd_defconfig b/arch/arm/configs/infinity6_test_fb_initrd_defconfig +new file mode 100755 +index 000000000000..2135254da81c +--- /dev/null ++++ b/arch/arm/configs/infinity6_test_fb_initrd_defconfig +@@ -0,0 +1,2561 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=16 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a-lh" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS=y ++CONFIG_DEFERRED_INIICALLS_MORE_SYSFS=y ++CONFIG_DEFERRED_CREATE_DTS_SYSNODE=y ++CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD=y ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PHYSMAP_OF is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=m ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=m ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=m ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=m ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=y ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=32000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=32000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=32000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_EMAC=m ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++CONFIG_RTC_INNER=m ++# CONFIG_RTCPWC_INNER is not set ++CONFIG_MS_CRYPTO=m ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++CONFIG_MS_SAR=m ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=m ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_ut_ssc009b_s01a_defconfig b/arch/arm/configs/infinity6_ut_ssc009b_s01a_defconfig +new file mode 100755 +index 000000000000..4ecf5d26cd46 +--- /dev/null ++++ b/arch/arm/configs/infinity6_ut_ssc009b_s01a_defconfig +@@ -0,0 +1,2582 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ut-ssc009b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_SSTAR_SHORT_NAME="" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_CAM_DRIVERS=y ++CONFIG_MS_CMDQ=y ++# CONFIG_MS_IMI_HEAP is not set ++CONFIG_MS_VENC=y ++CONFIG_MS_VENC_INFINITY6=m ++CONFIG_MS_VIF=y ++CONFIG_MS_VIF_INFINITY6=m ++CONFIG_MS_CSI=y ++CONFIG_MS_CSI_INFINITY6=m ++CONFIG_MS_SCL=m ++# CONFIG_MS_SCL_MI_TEST is not set ++CONFIG_MS_RGN=m ++CONFIG_MS_RGN_INFINITY6=m ++CONFIG_MS_RGN_SUPPORT_SYSFS=m ++CONFIG_MS_ISPALGO=y ++CONFIG_MS_ISPALGO_INFINITY6=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY6=m ++CONFIG_MS_ISP_MID=y ++CONFIG_MS_ISP_MIDDLEWARE_INFINITY6=m ++CONFIG_MS_MLOAD=y ++CONFIG_MS_MLOAD_INFINITY6x=m ++CONFIG_MS_SENSORIF=y ++CONFIG_MS_SENSORIF_INFINITY6=m ++# CONFIG_MS_SENSOR_EARLYINIT is not set ++CONFIG_MS_SENSORDRIVER=y ++CONFIG_MS_SENSORDRIVER_INFINITY=m ++CONFIG_MS_DIP=m ++# CONFIG_MS_DIP_PROC is not set ++# CONFIG_MS_DIP_MI_TEST is not set ++CONFIG_MS_DIP_RIUMODE_TEST=m ++CONFIG_MS_AIO=m ++CONFIG_MS_AIO_INFINITY6=m ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++CONFIG_NFS_V3=m ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_uvc_defconfig b/arch/arm/configs/infinity6_uvc_defconfig +new file mode 100755 +index 000000000000..3a95d502c2b3 +--- /dev/null ++++ b/arch/arm/configs/infinity6_uvc_defconfig +@@ -0,0 +1,2777 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++# CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET is not set ++# CONFIG_USB_SSTAR_DEBUG is not set ++# CONFIG_USB_SSTAR_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6_uvc_fastboot_defconfig b/arch/arm/configs/infinity6_uvc_fastboot_defconfig +new file mode 100755 +index 000000000000..2814dbb8f975 +--- /dev/null ++++ b/arch/arm/configs/infinity6_uvc_fastboot_defconfig +@@ -0,0 +1,2803 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6-ssc009a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6" ++CONFIG_SSTAR_SHORT_NAME="" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++# CONFIG_SCHED_HRTICK is not set ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=m ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++CONFIG_MS_SPI_INFINITY=m ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=m ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=m ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=m ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++CONFIG_MS_SAR=m ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=m ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_fpga_camdriver_defconfig b/arch/arm/configs/infinity6b0_fpga_camdriver_defconfig +new file mode 100755 +index 000000000000..0b687b97eeba +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_fpga_camdriver_defconfig +@@ -0,0 +1,2377 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++# CONFIG_SS_DCDO is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-fpga" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++# CONFIG_MS_CRYPTO is not set ++# CONFIG_MS_CPU_FREQ is not set ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_fpga_defconfig b/arch/arm/configs/infinity6b0_fpga_defconfig +new file mode 100755 +index 000000000000..0b687b97eeba +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_fpga_defconfig +@@ -0,0 +1,2377 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++# CONFIG_SS_DCDO is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-fpga" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++# CONFIG_MS_CRYPTO is not set ++# CONFIG_MS_CPU_FREQ is not set ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++# CONFIG_SS_VOLTAGE_CTRL is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009a_s01a_defconfig b/arch/arm/configs/infinity6b0_ssc009a_s01a_defconfig +new file mode 100755 +index 000000000000..3c70b4fb4948 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009a_s01a_defconfig +@@ -0,0 +1,2539 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009a_s01a_fastboot_defconfig b/arch/arm/configs/infinity6b0_ssc009a_s01a_fastboot_defconfig +new file mode 100755 +index 000000000000..4e3d66c2f4e8 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009a_s01a_fastboot_defconfig +@@ -0,0 +1,2564 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_defconfig b/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..8bffbb11c627 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_defconfig +@@ -0,0 +1,2539 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009a-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig b/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig +new file mode 100755 +index 000000000000..1306f26840d6 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig +@@ -0,0 +1,2564 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig b/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig +new file mode 100755 +index 000000000000..85da1cb48a7f +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig +@@ -0,0 +1,2799 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009a_s01a_usbcam_defconfig b/arch/arm/configs/infinity6b0_ssc009a_s01a_usbcam_defconfig +new file mode 100755 +index 000000000000..7ed6f1a79594 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009a_s01a_usbcam_defconfig +@@ -0,0 +1,2813 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++CONFIG_MODULES_AREA_SIZE=0x00800000 ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_U_ETHER=m ++CONFIG_USB_U_AUDIO=m ++CONFIG_USB_F_RNDIS=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++# CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE is not set ++# CONFIG_UVC_STREAM_ERR_SUPPORT is not set ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_UAC1_LEGACY is not set ++CONFIG_USB_WEBCAM_RNDIS=y ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_PWM_NEW is not set ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_SPI_INT_CALL is not set ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_EMAC_PHY_RESTART_AN is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++# CONFIG_SS_RNG is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009b_s01a_defconfig b/arch/arm/configs/infinity6b0_ssc009b_s01a_defconfig +new file mode 100755 +index 000000000000..76580bacb860 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009b_s01a_defconfig +@@ -0,0 +1,2538 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009b_s01a_fastboot_defconfig b/arch/arm/configs/infinity6b0_ssc009b_s01a_fastboot_defconfig +new file mode 100755 +index 000000000000..227377e6a0b8 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009b_s01a_fastboot_defconfig +@@ -0,0 +1,2564 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_defconfig b/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..497606cb769f +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_defconfig +@@ -0,0 +1,2539 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009b-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig b/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig +new file mode 100755 +index 000000000000..4956a0f006c1 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig +@@ -0,0 +1,2564 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig b/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig +new file mode 100755 +index 000000000000..a0fdcc8cea06 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig +@@ -0,0 +1,2799 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009b_s01a_usbcam_defconfig b/arch/arm/configs/infinity6b0_ssc009b_s01a_usbcam_defconfig +new file mode 100755 +index 000000000000..be61eb30fb7c +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009b_s01a_usbcam_defconfig +@@ -0,0 +1,2813 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++CONFIG_MODULES_AREA_SIZE=0x00800000 ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_PROC_FS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=m ++CONFIG_USB_U_ETHER=m ++CONFIG_USB_U_AUDIO=m ++CONFIG_USB_F_RNDIS=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++# CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE is not set ++# CONFIG_UVC_STREAM_ERR_SUPPORT is not set ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_UAC1_LEGACY is not set ++CONFIG_USB_WEBCAM_RNDIS=y ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_PWM_NEW is not set ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_SPI_INT_CALL is not set ++# CONFIG_CAM_CLK is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_EMAC_PHY_RESTART_AN is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_SW_RST_OFF is not set ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++# CONFIG_SS_RNG is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009d_s01a_defconfig b/arch/arm/configs/infinity6b0_ssc009d_s01a_defconfig +new file mode 100755 +index 000000000000..1e922f0e67b0 +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009d_s01a_defconfig +@@ -0,0 +1,2539 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009d-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6b0_ssc009d_s01a_spinand_defconfig b/arch/arm/configs/infinity6b0_ssc009d_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..2865fc32008a +--- /dev/null ++++ b/arch/arm/configs/infinity6b0_ssc009d_s01a_spinand_defconfig +@@ -0,0 +1,2539 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6b0-ssc009d-s01a" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6b0" ++CONFIG_SSTAR_SHORT_NAME="I6B0" ++# CONFIG_MP_IRQ_TRACE is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6B0=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++# CONFIG_MS_I2C_INT_ISR is not set ++CONFIG_MS_GPIO=y ++CONFIG_MS_SW_I2C=y ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_alkaid_fpga_256_defconfig b/arch/arm/configs/infinity6e_alkaid_fpga_256_defconfig +new file mode 100755 +index 000000000000..0c9197ba3afa +--- /dev/null ++++ b/arch/arm/configs/infinity6e_alkaid_fpga_256_defconfig +@@ -0,0 +1,2537 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-alkaid-fpga-256" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_alkaid_fpga_defconfig b/arch/arm/configs/infinity6e_alkaid_fpga_defconfig +new file mode 100755 +index 000000000000..64daecd46113 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_alkaid_fpga_defconfig +@@ -0,0 +1,2537 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-alkaid-fpga" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_defconfig b/arch/arm/configs/infinity6e_defconfig +new file mode 100755 +index 000000000000..b244f5eecbc5 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_defconfig +@@ -0,0 +1,2559 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_emmc_defconfig b/arch/arm/configs/infinity6e_emmc_defconfig +new file mode 100755 +index 000000000000..4ae8f44bd8a2 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_emmc_defconfig +@@ -0,0 +1,2586 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_AIX_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++# CONFIG_CMDLINE_PARTITION is not set ++CONFIG_EMMC_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++#CONFIG_MS_FLASH_ISP_MXP_PARTS is not set ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++CONFIG_MS_EMMC=y ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++# CONFIG_SS_ISP_ISRCB is not set ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT2=y ++# CONFIG_EXT4_FS_POSIX_ACL is not set ++# CONFIG_EXT4_FS_SECURITY is not set ++# CONFIG_EXT4_ENCRYPTION is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++CONFIG_FUSE_FS=y ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_fpga_256_defconfig b/arch/arm/configs/infinity6e_fpga_256_defconfig +new file mode 100755 +index 000000000000..50406e376d78 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_fpga_256_defconfig +@@ -0,0 +1,2537 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-fpga-256" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_fpga_defconfig b/arch/arm/configs/infinity6e_fpga_defconfig +new file mode 100755 +index 000000000000..ec7fbda962b4 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_fpga_defconfig +@@ -0,0 +1,2537 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_LH_RTOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-fpga" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++# CONFIG_MS_WATCHDOG is not set ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_msdc_defconfig b/arch/arm/configs/infinity6e_msdc_defconfig +new file mode 100644 +index 000000000000..b3409479b7fe +--- /dev/null ++++ b/arch/arm/configs/infinity6e_msdc_defconfig +@@ -0,0 +1,2622 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_GADGET_SSTAR_DEVICE is not set ++CONFIG_USB_LIBCOMPOSITE=y ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_MASS_STORAGE=y ++CONFIG_USB_CONFIGFS=y ++# CONFIG_USB_CONFIGFS_SERIAL is not set ++# CONFIG_USB_CONFIGFS_ACM is not set ++# CONFIG_USB_CONFIGFS_OBEX is not set ++# CONFIG_USB_CONFIGFS_NCM is not set ++# CONFIG_USB_CONFIGFS_ECM is not set ++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set ++# CONFIG_USB_CONFIGFS_RNDIS is not set ++# CONFIG_USB_CONFIGFS_EEM is not set ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++# CONFIG_USB_CONFIGFS_F_LB_SS is not set ++# CONFIG_USB_CONFIGFS_F_FS is not set ++# CONFIG_USB_CONFIGFS_F_HID is not set ++# CONFIG_USB_CONFIGFS_F_PRINTER is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++CONFIG_USB_MASS_STORAGE=m ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++# CONFIG_USB_G_WEBCAM is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_spinand_amp_defconfig b/arch/arm/configs/infinity6e_spinand_amp_defconfig +new file mode 100755 +index 000000000000..aa1ec354e669 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_spinand_amp_defconfig +@@ -0,0 +1,2547 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-amp" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_spinand_defconfig b/arch/arm/configs/infinity6e_spinand_defconfig +new file mode 100755 +index 000000000000..7ac23c539369 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_spinand_defconfig +@@ -0,0 +1,2563 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE is not set ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_defconfig +new file mode 100755 +index 000000000000..536a10320749 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_defconfig +@@ -0,0 +1,2582 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-2+2mipi" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_panel_spinand_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_panel_spinand_defconfig +new file mode 100755 +index 000000000000..49831be7fccc +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_panel_spinand_defconfig +@@ -0,0 +1,2588 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-2+2mipi-panel" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++CONFIG_FUSE_FS=y ++# CONFIG_CUSE is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_spinand_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_spinand_defconfig +new file mode 100755 +index 000000000000..c08a51d2bcd3 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_spinand_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-2+2mipi" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_spinand_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_spinand_usbcam_defconfig +new file mode 100755 +index 000000000000..d6fceb77e3e2 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_spinand_usbcam_defconfig +@@ -0,0 +1,2853 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-2+2mipi" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_usbcam_defconfig +new file mode 100755 +index 000000000000..80dd8c5017bb +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_2+2mipi_usbcam_defconfig +@@ -0,0 +1,2848 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-2+2mipi" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_defconfig +new file mode 100755 +index 000000000000..68e0ac639a62 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_defconfig +@@ -0,0 +1,2583 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_SS_MSPI=y ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_fastboot_defconfig +new file mode 100644 +index 000000000000..69f82bf6a985 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_fastboot_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_panel_spinand_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_panel_spinand_defconfig +new file mode 100755 +index 000000000000..4c938c6678b2 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_panel_spinand_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-panel" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_amp_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_amp_defconfig +new file mode 100755 +index 000000000000..3f6a01353258 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_amp_defconfig +@@ -0,0 +1,2547 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-amp" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_amp_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_amp_usbcam_defconfig +new file mode 100644 +index 000000000000..233e8c4914f9 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_amp_usbcam_defconfig +@@ -0,0 +1,2770 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-amp" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..fc658288df3b +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_fastboot_defconfig +new file mode 100644 +index 000000000000..87ef33dcf82a +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_fastboot_defconfig +@@ -0,0 +1,2592 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_smplh_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_smplh_defconfig +new file mode 100755 +index 000000000000..7247661aa6c3 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_smplh_defconfig +@@ -0,0 +1,2581 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++CONFIG_LH_RTOS=y ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a-smplh" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_MS_IOPOWER=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_usbcam_defconfig +new file mode 100644 +index 000000000000..9efa881fee7c +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_usbcam_defconfig +@@ -0,0 +1,2866 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++CONFIG_MODULES_AREA_SIZE=0x00800000 ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SS_GIC_SET_MULTI_CPUS=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_U_ETHER=m ++CONFIG_USB_U_AUDIO=m ++CONFIG_USB_F_RNDIS=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++# CONFIG_UVC_STREAM_ERR_SUPPORT is not set ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_UAC1_LEGACY is not set ++CONFIG_USB_WEBCAM_RNDIS=y ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++# CONFIG_PWM_NEW is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_SS_MSPI is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_EMAC_PHY_RESTART_AN is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++# CONFIG_SS_RNG is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_OSC=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig +new file mode 100755 +index 000000000000..a290583cee25 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig +@@ -0,0 +1,2861 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_usbcam_defconfig +new file mode 100644 +index 000000000000..36e191308e5a +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_usbcam_defconfig +@@ -0,0 +1,2861 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++CONFIG_MODULES_AREA_SIZE=0x00800000 ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SS_GIC_SET_MULTI_CPUS=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_U_ETHER=m ++CONFIG_USB_U_AUDIO=m ++CONFIG_USB_F_RNDIS=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++# CONFIG_UVC_STREAM_ERR_SUPPORT is not set ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_UAC1_LEGACY is not set ++CONFIG_USB_WEBCAM_RNDIS=y ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_PWM_NEW is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_SS_MSPI is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_EMAC_PHY_RESTART_AN is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++# CONFIG_SS_RNG is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_OSC=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig +new file mode 100755 +index 000000000000..2afbb7dc3b12 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig +@@ -0,0 +1,2856 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc012b-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_2+2mipi_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_2+2mipi_defconfig +new file mode 100755 +index 000000000000..9fdae360a093 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_2+2mipi_defconfig +@@ -0,0 +1,2582 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a-2+2mipi" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_2+2mipi_spinand_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_2+2mipi_spinand_defconfig +new file mode 100755 +index 000000000000..afa69951ac30 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_2+2mipi_spinand_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a-2+2mipi" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_defconfig +new file mode 100755 +index 000000000000..7cb6ddc509ef +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_defconfig +@@ -0,0 +1,2582 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_fastboot_defconfig +new file mode 100644 +index 000000000000..37df0356ceea +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_fastboot_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_miniGUI_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_miniGUI_defconfig +new file mode 100644 +index 000000000000..03333953e5df +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_miniGUI_defconfig +@@ -0,0 +1,3175 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-cardv-demo-board" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++CONFIG_INPUT_POLLDEV=y ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADC is not set ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=m ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_GENERIC_ADC_BATTERY is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++CONFIG_BATTERY_IP6303=m ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24190 is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_CHARGER_RT9455 is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++CONFIG_UHID=y ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# IIO staging drivers ++# ++ ++# ++# Accelerometers ++# ++# CONFIG_ADIS16201 is not set ++# CONFIG_ADIS16203 is not set ++# CONFIG_ADIS16209 is not set ++# CONFIG_ADIS16240 is not set ++ ++# ++# Analog to digital converters ++# ++# CONFIG_AD7606 is not set ++# CONFIG_AD7780 is not set ++# CONFIG_AD7816 is not set ++# CONFIG_AD7192 is not set ++# CONFIG_AD7280 is not set ++ ++# ++# Analog digital bi-direction converters ++# ++# CONFIG_ADT7316 is not set ++ ++# ++# Capacitance to digital converters ++# ++# CONFIG_AD7150 is not set ++# CONFIG_AD7152 is not set ++# CONFIG_AD7746 is not set ++ ++# ++# Direct Digital Synthesis ++# ++# CONFIG_AD9832 is not set ++# CONFIG_AD9834 is not set ++ ++# ++# Digital gyroscope sensors ++# ++# CONFIG_ADIS16060 is not set ++ ++# ++# Network Analyzer, Impedance Converters ++# ++# CONFIG_AD5933 is not set ++ ++# ++# Light sensors ++# ++# CONFIG_SENSORS_ISL29018 is not set ++# CONFIG_SENSORS_ISL29028 is not set ++# CONFIG_TSL2583 is not set ++# CONFIG_TSL2x7x is not set ++ ++# ++# Active energy metering IC ++# ++# CONFIG_ADE7753 is not set ++# CONFIG_ADE7754 is not set ++# CONFIG_ADE7758 is not set ++# CONFIG_ADE7759 is not set ++# CONFIG_ADE7854 is not set ++ ++# ++# Resolver to digital converters ++# ++# CONFIG_AD2S90 is not set ++# CONFIG_AD2S1200 is not set ++# CONFIG_AD2S1210 is not set ++ ++# ++# Triggers - standalone ++# ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++CONFIG_IIO=y ++# CONFIG_IIO_BUFFER is not set ++# CONFIG_IIO_CONFIGFS is not set ++# CONFIG_IIO_TRIGGER is not set ++# CONFIG_IIO_SW_DEVICE is not set ++# CONFIG_IIO_SW_TRIGGER is not set ++ ++# ++# Accelerometers ++# ++# CONFIG_BMA180 is not set ++# CONFIG_BMA220 is not set ++# CONFIG_BMC150_ACCEL is not set ++# CONFIG_DMARD06 is not set ++# CONFIG_DMARD09 is not set ++# CONFIG_IIO_ST_ACCEL_3AXIS is not set ++# CONFIG_KXSD9 is not set ++# CONFIG_KXCJK1013 is not set ++# CONFIG_MC3230 is not set ++# CONFIG_MMA7455_I2C is not set ++# CONFIG_MMA7455_SPI is not set ++# CONFIG_MMA7660 is not set ++# CONFIG_MMA8452 is not set ++# CONFIG_MMA9551 is not set ++# CONFIG_MMA9553 is not set ++# CONFIG_MXC4005 is not set ++# CONFIG_MXC6255 is not set ++# CONFIG_STK8312 is not set ++# CONFIG_STK8BA50 is not set ++ ++# ++# Analog to digital converters ++# ++# CONFIG_AD7266 is not set ++# CONFIG_AD7291 is not set ++# CONFIG_AD7298 is not set ++# CONFIG_AD7476 is not set ++# CONFIG_AD7791 is not set ++# CONFIG_AD7793 is not set ++# CONFIG_AD7887 is not set ++# CONFIG_AD7923 is not set ++# CONFIG_AD799X is not set ++# CONFIG_HI8435 is not set ++# CONFIG_INA2XX_ADC is not set ++# CONFIG_LTC2485 is not set ++# CONFIG_MAX1027 is not set ++# CONFIG_MAX1363 is not set ++# CONFIG_MCP320X is not set ++# CONFIG_MCP3422 is not set ++# CONFIG_NAU7802 is not set ++# CONFIG_TI_ADC081C is not set ++# CONFIG_TI_ADC0832 is not set ++# CONFIG_TI_ADC12138 is not set ++# CONFIG_TI_ADC128S052 is not set ++# CONFIG_TI_ADC161S626 is not set ++# CONFIG_TI_ADS1015 is not set ++# CONFIG_TI_ADS8688 is not set ++# CONFIG_VF610_ADC is not set ++ ++# ++# Amplifiers ++# ++# CONFIG_AD8366 is not set ++ ++# ++# Chemical Sensors ++# ++# CONFIG_ATLAS_PH_SENSOR is not set ++# CONFIG_IAQCORE is not set ++# CONFIG_VZ89X is not set ++ ++# ++# Hid Sensor IIO Common ++# ++ ++# ++# SSP Sensor Common ++# ++# CONFIG_IIO_SSP_SENSORHUB is not set ++ ++# ++# Digital to analog converters ++# ++# CONFIG_AD5064 is not set ++# CONFIG_AD5360 is not set ++# CONFIG_AD5380 is not set ++# CONFIG_AD5421 is not set ++# CONFIG_AD5446 is not set ++# CONFIG_AD5449 is not set ++# CONFIG_AD5592R is not set ++# CONFIG_AD5593R is not set ++# CONFIG_AD5504 is not set ++# CONFIG_AD5624R_SPI is not set ++# CONFIG_AD5686 is not set ++# CONFIG_AD5755 is not set ++# CONFIG_AD5761 is not set ++# CONFIG_AD5764 is not set ++# CONFIG_AD5791 is not set ++# CONFIG_AD7303 is not set ++# CONFIG_AD8801 is not set ++# CONFIG_M62332 is not set ++# CONFIG_MAX517 is not set ++# CONFIG_MAX5821 is not set ++# CONFIG_MCP4725 is not set ++# CONFIG_MCP4922 is not set ++# CONFIG_VF610_DAC is not set ++ ++# ++# IIO dummy driver ++# ++ ++# ++# Frequency Synthesizers DDS/PLL ++# ++ ++# ++# Clock Generator/Distribution ++# ++# CONFIG_AD9523 is not set ++ ++# ++# Phase-Locked Loop (PLL) frequency synthesizers ++# ++# CONFIG_ADF4350 is not set ++ ++# ++# Digital gyroscope sensors ++# ++# CONFIG_ADIS16080 is not set ++# CONFIG_ADIS16130 is not set ++# CONFIG_ADIS16136 is not set ++# CONFIG_ADIS16260 is not set ++# CONFIG_ADXRS450 is not set ++# CONFIG_BMG160 is not set ++# CONFIG_IIO_ST_GYRO_3AXIS is not set ++# CONFIG_ITG3200 is not set ++ ++# ++# Health Sensors ++# ++ ++# ++# Heart Rate Monitors ++# ++# CONFIG_AFE4403 is not set ++# CONFIG_AFE4404 is not set ++# CONFIG_MAX30100 is not set ++ ++# ++# Humidity sensors ++# ++# CONFIG_AM2315 is not set ++# CONFIG_DHT11 is not set ++# CONFIG_HDC100X is not set ++# CONFIG_HTU21 is not set ++# CONFIG_SI7005 is not set ++# CONFIG_SI7020 is not set ++ ++# ++# Inertial measurement units ++# ++# CONFIG_ADIS16400 is not set ++# CONFIG_ADIS16480 is not set ++# CONFIG_BMI160_I2C is not set ++# CONFIG_BMI160_SPI is not set ++# CONFIG_KMX61 is not set ++# CONFIG_INV_MPU6050_I2C is not set ++# CONFIG_INV_MPU6050_SPI is not set ++ ++# ++# Light sensors ++# ++# CONFIG_ADJD_S311 is not set ++# CONFIG_AL3320A is not set ++# CONFIG_APDS9300 is not set ++# CONFIG_APDS9960 is not set ++# CONFIG_BH1750 is not set ++# CONFIG_BH1780 is not set ++# CONFIG_CM32181 is not set ++# CONFIG_CM3232 is not set ++# CONFIG_CM3323 is not set ++# CONFIG_CM36651 is not set ++# CONFIG_GP2AP020A00F is not set ++# CONFIG_ISL29125 is not set ++# CONFIG_JSA1212 is not set ++# CONFIG_RPR0521 is not set ++# CONFIG_LTR501 is not set ++# CONFIG_MAX44000 is not set ++# CONFIG_OPT3001 is not set ++# CONFIG_PA12203001 is not set ++# CONFIG_SI1145 is not set ++# CONFIG_STK3310 is not set ++# CONFIG_TCS3414 is not set ++# CONFIG_TCS3472 is not set ++# CONFIG_SENSORS_TSL2563 is not set ++# CONFIG_TSL4531 is not set ++# CONFIG_US5182D is not set ++# CONFIG_VCNL4000 is not set ++# CONFIG_VEML6070 is not set ++ ++# ++# Magnetometer sensors ++# ++# CONFIG_AK8974 is not set ++# CONFIG_AK8975 is not set ++# CONFIG_AK09911 is not set ++# CONFIG_BMC150_MAGN_I2C is not set ++# CONFIG_BMC150_MAGN_SPI is not set ++# CONFIG_MAG3110 is not set ++# CONFIG_MMC35240 is not set ++# CONFIG_IIO_ST_MAGN_3AXIS is not set ++# CONFIG_SENSORS_HMC5843_I2C is not set ++# CONFIG_SENSORS_HMC5843_SPI is not set ++ ++# ++# Inclinometer sensors ++# ++ ++# ++# Digital potentiometers ++# ++# CONFIG_DS1803 is not set ++# CONFIG_MAX5487 is not set ++# CONFIG_MCP4131 is not set ++# CONFIG_MCP4531 is not set ++# CONFIG_TPL0102 is not set ++ ++# ++# Pressure sensors ++# ++# CONFIG_BMP280 is not set ++# CONFIG_HP03 is not set ++# CONFIG_MPL115_I2C is not set ++# CONFIG_MPL115_SPI is not set ++# CONFIG_MPL3115 is not set ++# CONFIG_MS5611 is not set ++# CONFIG_MS5637 is not set ++# CONFIG_IIO_ST_PRESS is not set ++# CONFIG_T5403 is not set ++# CONFIG_HP206C is not set ++# CONFIG_ZPA2326 is not set ++ ++# ++# Lightning sensors ++# ++# CONFIG_AS3935 is not set ++ ++# ++# Proximity sensors ++# ++# CONFIG_LIDAR_LITE_V2 is not set ++# CONFIG_SX9500 is not set ++ ++# ++# Temperature sensors ++# ++# CONFIG_MAXIM_THERMOCOUPLE is not set ++# CONFIG_MLX90614 is not set ++# CONFIG_TMP006 is not set ++# CONFIG_TSYS01 is not set ++# CONFIG_TSYS02D is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MS_SARKEY=m ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_miniGUI_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_miniGUI_fastboot_defconfig +new file mode 100644 +index 000000000000..4a9257b56b57 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_miniGUI_fastboot_defconfig +@@ -0,0 +1,3191 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-cardv-demo-board" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++CONFIG_INPUT_POLLDEV=y ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADC is not set ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=m ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_GENERIC_ADC_BATTERY is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++CONFIG_BATTERY_IP6303=m ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24190 is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_CHARGER_RT9455 is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++CONFIG_UHID=y ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# IIO staging drivers ++# ++ ++# ++# Accelerometers ++# ++# CONFIG_ADIS16201 is not set ++# CONFIG_ADIS16203 is not set ++# CONFIG_ADIS16209 is not set ++# CONFIG_ADIS16240 is not set ++ ++# ++# Analog to digital converters ++# ++# CONFIG_AD7606 is not set ++# CONFIG_AD7780 is not set ++# CONFIG_AD7816 is not set ++# CONFIG_AD7192 is not set ++# CONFIG_AD7280 is not set ++ ++# ++# Analog digital bi-direction converters ++# ++# CONFIG_ADT7316 is not set ++ ++# ++# Capacitance to digital converters ++# ++# CONFIG_AD7150 is not set ++# CONFIG_AD7152 is not set ++# CONFIG_AD7746 is not set ++ ++# ++# Direct Digital Synthesis ++# ++# CONFIG_AD9832 is not set ++# CONFIG_AD9834 is not set ++ ++# ++# Digital gyroscope sensors ++# ++# CONFIG_ADIS16060 is not set ++ ++# ++# Network Analyzer, Impedance Converters ++# ++# CONFIG_AD5933 is not set ++ ++# ++# Light sensors ++# ++# CONFIG_SENSORS_ISL29018 is not set ++# CONFIG_SENSORS_ISL29028 is not set ++# CONFIG_TSL2583 is not set ++# CONFIG_TSL2x7x is not set ++ ++# ++# Active energy metering IC ++# ++# CONFIG_ADE7753 is not set ++# CONFIG_ADE7754 is not set ++# CONFIG_ADE7758 is not set ++# CONFIG_ADE7759 is not set ++# CONFIG_ADE7854 is not set ++ ++# ++# Resolver to digital converters ++# ++# CONFIG_AD2S90 is not set ++# CONFIG_AD2S1200 is not set ++# CONFIG_AD2S1210 is not set ++ ++# ++# Triggers - standalone ++# ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++CONFIG_IIO=y ++# CONFIG_IIO_BUFFER is not set ++# CONFIG_IIO_CONFIGFS is not set ++# CONFIG_IIO_TRIGGER is not set ++# CONFIG_IIO_SW_DEVICE is not set ++# CONFIG_IIO_SW_TRIGGER is not set ++ ++# ++# Accelerometers ++# ++# CONFIG_BMA180 is not set ++# CONFIG_BMA220 is not set ++# CONFIG_BMC150_ACCEL is not set ++# CONFIG_DMARD06 is not set ++# CONFIG_DMARD09 is not set ++# CONFIG_IIO_ST_ACCEL_3AXIS is not set ++# CONFIG_KXSD9 is not set ++# CONFIG_KXCJK1013 is not set ++# CONFIG_MC3230 is not set ++# CONFIG_MMA7455_I2C is not set ++# CONFIG_MMA7455_SPI is not set ++# CONFIG_MMA7660 is not set ++# CONFIG_MMA8452 is not set ++# CONFIG_MMA9551 is not set ++# CONFIG_MMA9553 is not set ++# CONFIG_MXC4005 is not set ++# CONFIG_MXC6255 is not set ++# CONFIG_STK8312 is not set ++# CONFIG_STK8BA50 is not set ++ ++# ++# Analog to digital converters ++# ++# CONFIG_AD7266 is not set ++# CONFIG_AD7291 is not set ++# CONFIG_AD7298 is not set ++# CONFIG_AD7476 is not set ++# CONFIG_AD7791 is not set ++# CONFIG_AD7793 is not set ++# CONFIG_AD7887 is not set ++# CONFIG_AD7923 is not set ++# CONFIG_AD799X is not set ++# CONFIG_HI8435 is not set ++# CONFIG_INA2XX_ADC is not set ++# CONFIG_LTC2485 is not set ++# CONFIG_MAX1027 is not set ++# CONFIG_MAX1363 is not set ++# CONFIG_MCP320X is not set ++# CONFIG_MCP3422 is not set ++# CONFIG_NAU7802 is not set ++# CONFIG_TI_ADC081C is not set ++# CONFIG_TI_ADC0832 is not set ++# CONFIG_TI_ADC12138 is not set ++# CONFIG_TI_ADC128S052 is not set ++# CONFIG_TI_ADC161S626 is not set ++# CONFIG_TI_ADS1015 is not set ++# CONFIG_TI_ADS8688 is not set ++# CONFIG_VF610_ADC is not set ++ ++# ++# Amplifiers ++# ++# CONFIG_AD8366 is not set ++ ++# ++# Chemical Sensors ++# ++# CONFIG_ATLAS_PH_SENSOR is not set ++# CONFIG_IAQCORE is not set ++# CONFIG_VZ89X is not set ++ ++# ++# Hid Sensor IIO Common ++# ++ ++# ++# SSP Sensor Common ++# ++# CONFIG_IIO_SSP_SENSORHUB is not set ++ ++# ++# Digital to analog converters ++# ++# CONFIG_AD5064 is not set ++# CONFIG_AD5360 is not set ++# CONFIG_AD5380 is not set ++# CONFIG_AD5421 is not set ++# CONFIG_AD5446 is not set ++# CONFIG_AD5449 is not set ++# CONFIG_AD5592R is not set ++# CONFIG_AD5593R is not set ++# CONFIG_AD5504 is not set ++# CONFIG_AD5624R_SPI is not set ++# CONFIG_AD5686 is not set ++# CONFIG_AD5755 is not set ++# CONFIG_AD5761 is not set ++# CONFIG_AD5764 is not set ++# CONFIG_AD5791 is not set ++# CONFIG_AD7303 is not set ++# CONFIG_AD8801 is not set ++# CONFIG_M62332 is not set ++# CONFIG_MAX517 is not set ++# CONFIG_MAX5821 is not set ++# CONFIG_MCP4725 is not set ++# CONFIG_MCP4922 is not set ++# CONFIG_VF610_DAC is not set ++ ++# ++# IIO dummy driver ++# ++ ++# ++# Frequency Synthesizers DDS/PLL ++# ++ ++# ++# Clock Generator/Distribution ++# ++# CONFIG_AD9523 is not set ++ ++# ++# Phase-Locked Loop (PLL) frequency synthesizers ++# ++# CONFIG_ADF4350 is not set ++ ++# ++# Digital gyroscope sensors ++# ++# CONFIG_ADIS16080 is not set ++# CONFIG_ADIS16130 is not set ++# CONFIG_ADIS16136 is not set ++# CONFIG_ADIS16260 is not set ++# CONFIG_ADXRS450 is not set ++# CONFIG_BMG160 is not set ++# CONFIG_IIO_ST_GYRO_3AXIS is not set ++# CONFIG_ITG3200 is not set ++ ++# ++# Health Sensors ++# ++ ++# ++# Heart Rate Monitors ++# ++# CONFIG_AFE4403 is not set ++# CONFIG_AFE4404 is not set ++# CONFIG_MAX30100 is not set ++ ++# ++# Humidity sensors ++# ++# CONFIG_AM2315 is not set ++# CONFIG_DHT11 is not set ++# CONFIG_HDC100X is not set ++# CONFIG_HTU21 is not set ++# CONFIG_SI7005 is not set ++# CONFIG_SI7020 is not set ++ ++# ++# Inertial measurement units ++# ++# CONFIG_ADIS16400 is not set ++# CONFIG_ADIS16480 is not set ++# CONFIG_BMI160_I2C is not set ++# CONFIG_BMI160_SPI is not set ++# CONFIG_KMX61 is not set ++# CONFIG_INV_MPU6050_I2C is not set ++# CONFIG_INV_MPU6050_SPI is not set ++ ++# ++# Light sensors ++# ++# CONFIG_ADJD_S311 is not set ++# CONFIG_AL3320A is not set ++# CONFIG_APDS9300 is not set ++# CONFIG_APDS9960 is not set ++# CONFIG_BH1750 is not set ++# CONFIG_BH1780 is not set ++# CONFIG_CM32181 is not set ++# CONFIG_CM3232 is not set ++# CONFIG_CM3323 is not set ++# CONFIG_CM36651 is not set ++# CONFIG_GP2AP020A00F is not set ++# CONFIG_ISL29125 is not set ++# CONFIG_JSA1212 is not set ++# CONFIG_RPR0521 is not set ++# CONFIG_LTR501 is not set ++# CONFIG_MAX44000 is not set ++# CONFIG_OPT3001 is not set ++# CONFIG_PA12203001 is not set ++# CONFIG_SI1145 is not set ++# CONFIG_STK3310 is not set ++# CONFIG_TCS3414 is not set ++# CONFIG_TCS3472 is not set ++# CONFIG_SENSORS_TSL2563 is not set ++# CONFIG_TSL4531 is not set ++# CONFIG_US5182D is not set ++# CONFIG_VCNL4000 is not set ++# CONFIG_VEML6070 is not set ++ ++# ++# Magnetometer sensors ++# ++# CONFIG_AK8974 is not set ++# CONFIG_AK8975 is not set ++# CONFIG_AK09911 is not set ++# CONFIG_BMC150_MAGN_I2C is not set ++# CONFIG_BMC150_MAGN_SPI is not set ++# CONFIG_MAG3110 is not set ++# CONFIG_MMC35240 is not set ++# CONFIG_IIO_ST_MAGN_3AXIS is not set ++# CONFIG_SENSORS_HMC5843_I2C is not set ++# CONFIG_SENSORS_HMC5843_SPI is not set ++ ++# ++# Inclinometer sensors ++# ++ ++# ++# Digital potentiometers ++# ++# CONFIG_DS1803 is not set ++# CONFIG_MAX5487 is not set ++# CONFIG_MCP4131 is not set ++# CONFIG_MCP4531 is not set ++# CONFIG_TPL0102 is not set ++ ++# ++# Pressure sensors ++# ++# CONFIG_BMP280 is not set ++# CONFIG_HP03 is not set ++# CONFIG_MPL115_I2C is not set ++# CONFIG_MPL115_SPI is not set ++# CONFIG_MPL3115 is not set ++# CONFIG_MS5611 is not set ++# CONFIG_MS5637 is not set ++# CONFIG_IIO_ST_PRESS is not set ++# CONFIG_T5403 is not set ++# CONFIG_HP206C is not set ++# CONFIG_ZPA2326 is not set ++ ++# ++# Lightning sensors ++# ++# CONFIG_AS3935 is not set ++ ++# ++# Proximity sensors ++# ++# CONFIG_LIDAR_LITE_V2 is not set ++# CONFIG_SX9500 is not set ++ ++# ++# Temperature sensors ++# ++# CONFIG_MAXIM_THERMOCOUPLE is not set ++# CONFIG_MLX90614 is not set ++# CONFIG_TMP006 is not set ++# CONFIG_TSYS01 is not set ++# CONFIG_TSYS02D is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MS_SARKEY=m ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_amp_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_amp_defconfig +new file mode 100755 +index 000000000000..95a4c4fbe777 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_amp_defconfig +@@ -0,0 +1,2547 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a-amp" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_amp_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_amp_usbcam_defconfig +new file mode 100644 +index 000000000000..8d6fadf581b7 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_amp_usbcam_defconfig +@@ -0,0 +1,2770 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++# CONFIG_LH_RTOS is not set ++CONFIG_SS_AMP=y ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a-amp" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..1c356161d4a9 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_fastboot_defconfig +new file mode 100644 +index 000000000000..39ddc58e3c31 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_fastboot_defconfig +@@ -0,0 +1,2592 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_smplh_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_smplh_defconfig +new file mode 100644 +index 000000000000..953ecfeab5f1 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_smplh_defconfig +@@ -0,0 +1,2581 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++CONFIG_SS_DUALOS=y ++CONFIG_LH_RTOS=y ++# CONFIG_SS_AMP is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a-smplh" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON is not set ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_MS_IOPOWER=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_usbcam_defconfig +new file mode 100644 +index 000000000000..3114e2cbc700 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_usbcam_defconfig +@@ -0,0 +1,2866 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++CONFIG_MODULES_AREA_SIZE=0x00800000 ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SS_GIC_SET_MULTI_CPUS=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_U_ETHER=m ++CONFIG_USB_U_AUDIO=m ++CONFIG_USB_F_RNDIS=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++# CONFIG_UVC_STREAM_ERR_SUPPORT is not set ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_UAC1_LEGACY is not set ++CONFIG_USB_WEBCAM_RNDIS=y ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++# CONFIG_PWM_NEW is not set ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_SS_MSPI is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_EMAC_PHY_RESTART_AN is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++# CONFIG_SS_RNG is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_OSC=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_usbcam_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_usbcam_fastboot_defconfig +new file mode 100755 +index 000000000000..d814458e3535 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_spinand_usbcam_fastboot_defconfig +@@ -0,0 +1,2861 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_usbcam_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_usbcam_defconfig +new file mode 100644 +index 000000000000..5278f96ab816 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_usbcam_defconfig +@@ -0,0 +1,2861 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++CONFIG_MODULES_AREA_SIZE=0x00800000 ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SS_GIC_SET_MULTI_CPUS=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_U_ETHER=m ++CONFIG_USB_U_AUDIO=m ++CONFIG_USB_F_RNDIS=m ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++# CONFIG_UVC_STREAM_ERR_SUPPORT is not set ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_UAC1_LEGACY is not set ++CONFIG_USB_WEBCAM_RNDIS=y ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_PWM_NEW is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_SS_MSPI is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_EMAC_PHY_RESTART_AN is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++# CONFIG_SS_RNG is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_OSC=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc013a_s01a_usbcam_fastboot_defconfig b/arch/arm/configs/infinity6e_ssc013a_s01a_usbcam_fastboot_defconfig +new file mode 100755 +index 000000000000..580692120486 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc013a_s01a_usbcam_fastboot_defconfig +@@ -0,0 +1,2856 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc013a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++ ++# ++# Fast boot ++# ++# CONFIG_SS_BUILTIN_UNFDT is not set ++# CONFIG_FB_DTS_SKIP_CRC is not set ++# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set ++# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++CONFIG_VIDEOBUF2_DMA_SG=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++ ++# ++# I2C Encoders, decoders, sensors and other helper chips ++# ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# SPI helper chips ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_AU8522=m ++CONFIG_DVB_AU8522_V4L=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++CONFIG_USB_GADGET_SSTAR_DEVICE=m ++CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET=y ++# CONFIG_USB_DEBUG_MESSAGE is not set ++# CONFIG_USB_FPGA_VERIFICATION is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_ENABLE_UPLL is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UAC1=m ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++CONFIG_MULTI_STREAM_FUNC_NUM=1 ++CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE=y ++CONFIG_USB_WEBCAM_UAC=y ++# CONFIG_USB_WEBCAM_RNDIS is not set ++# CONFIG_USB_WEBCAM_DFU is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_CAM_CLK is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++# CONFIG_MS_SARKEY is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++CONFIG_SS_VOLTAGE_CTRL_WITH_SIDD=y ++CONFIG_MS_IOPOWER=y ++# CONFIG_SS_SWTOE is not set ++# CONFIG_MS_EMAC_TOE is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc015a_s01a_defconfig b/arch/arm/configs/infinity6e_ssc015a_s01a_defconfig +new file mode 100755 +index 000000000000..f2979110ae27 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc015a_s01a_defconfig +@@ -0,0 +1,2582 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc015a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_ssc015a_s01a_spinand_defconfig b/arch/arm/configs/infinity6e_ssc015a_s01a_spinand_defconfig +new file mode 100755 +index 000000000000..a8ff14bfc690 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_ssc015a_s01a_spinand_defconfig +@@ -0,0 +1,2587 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INFINITY2 is not set ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e-ssc015a-s01a" ++CONFIG_SS_BUILTIN_DTB=y ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++# CONFIG_MS_FLASH_ISP is not set ++CONFIG_MS_PWM=y ++CONFIG_MS_SPINAND=y ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_uvc_defconfig b/arch/arm/configs/infinity6e_uvc_defconfig +new file mode 100644 +index 000000000000..1787116d9709 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_uvc_defconfig +@@ -0,0 +1,2708 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++# CONFIG_HOTPLUG_CPU is not set ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_OPP=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_GADGET_SSTAR_DEVICE is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_PWM=y ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++CONFIG_MS_RTC=y ++# CONFIG_RTC_INNER is not set ++CONFIG_RTCPWC_INNER=y ++CONFIG_RTCPWC_SW_RST_OFF=y ++CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity6e_uvc_str_defconfig b/arch/arm/configs/infinity6e_uvc_str_defconfig +new file mode 100644 +index 000000000000..ece28db4f681 +--- /dev/null ++++ b/arch/arm/configs/infinity6e_uvc_str_defconfig +@@ -0,0 +1,2728 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 4.9.84 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_PGTABLE_LEVELS=2 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_EXPEDITE_BOOT is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_NMI_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_PERF is not set ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++# CONFIG_USERFAULTFD is not set ++CONFIG_MEMBARRIER=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_DATA_VERIFICATION is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_STATIC_KEYS_SELFTEST is not set ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_OPTPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGINS is not set ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_HAVE_EXIT_THREAD=y ++CONFIG_ARCH_MMAP_RND_BITS_MIN=8 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=16 ++CONFIG_ARCH_MMAP_RND_BITS=8 ++# CONFIG_HAVE_ARCH_HASH is not set ++# CONFIG_ISA_BUS_API is not set ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++# CONFIG_CPU_NO_EFFICIENT_FFS is not set ++# CONFIG_HAVE_ARCH_VMAP_STACK is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_ARTPEC is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_DIGICOLOR is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_SSTAR=y ++# CONFIG_SS_DUALOS is not set ++ ++# ++# Options ++# ++CONFIG_SS_DTB_NAME="infinity6e" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_SSTAR_CHIP_NAME="infinity6e" ++CONFIG_SSTAR_SHORT_NAME="" ++CONFIG_MP_IRQ_TRACE=y ++CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y ++CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y ++CONFIG_DEFERRED_INIICALLS=y ++# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set ++# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set ++# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set ++# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set ++CONFIG_ARCH_INFINITY6E=y ++CONFIG_SS_PROFILING_TIME=y ++CONFIG_SS_MIU_ARBITRATION=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TANGO is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_VDSO=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++# CONFIG_DEBUG_RODATA is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++CONFIG_ARM_ERRATA_643719=y ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_798181 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++# CONFIG_ARM_ERRATA_818325_852422 is not set ++# CONFIG_ARM_ERRATA_821420 is not set ++# CONFIG_ARM_ERRATA_825619 is not set ++# CONFIG_ARM_ERRATA_852421 is not set ++# CONFIG_ARM_ERRATA_852423 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++# CONFIG_MCPM is not set ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_3G_OPT is not set ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_ARM_PATCH_IDIV=y ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_CPU_SW_DOMAIN_PAN=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++# CONFIG_ARM_MODULE_PLTS is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_IDLE_PAGE_TRACKING is not set ++# CONFIG_FRAME_VECTOR=y ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_EFI is not set ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++# CONFIG_CPUFREQ_DT is not set ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_FLAT is not set ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++CONFIG_PM_WAKELOCKS=y ++CONFIG_PM_WAKELOCKS_LIMIT=100 ++CONFIG_PM_WAKELOCKS_GC=y ++CONFIG_PM=y ++CONFIG_PM_DEBUG=y ++CONFIG_PM_ADVANCED_DEBUG=y ++CONFIG_PM_TEST_SUSPEND=y ++CONFIG_PM_SLEEP_DEBUG=y ++CONFIG_APM_EMULATION=y ++CONFIG_PM_OPP=y ++CONFIG_PM_CLK=y ++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_NV is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++# CONFIG_TCP_CONG_CDG is not set ++# CONFIG_TCP_CONG_BBR is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_SOCK_CGROUP_DATA is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_STREAM_PARSER is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_LWTUNNEL is not set ++# CONFIG_DST_CACHE is not set ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++CONFIG_HAVE_CBPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=2 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCI400_PMU is not set ++# CONFIG_ARM_CCI5xx_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_SS_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_NAND_HISI504 is not set ++# CONFIG_MTD_NAND_MTK is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++# CONFIG_CXL_AFU_DRIVER_OPS is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++# CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MDIO bus device drivers ++# ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++CONFIG_WLAN_VENDOR_ADMTEK=y ++CONFIG_WLAN_VENDOR_ATH=y ++# CONFIG_ATH_DEBUG is not set ++# CONFIG_ATH6KL is not set ++CONFIG_WLAN_VENDOR_ATMEL=y ++CONFIG_WLAN_VENDOR_BROADCOM=y ++# CONFIG_BRCMFMAC is not set ++CONFIG_WLAN_VENDOR_CISCO=y ++CONFIG_WLAN_VENDOR_INTEL=y ++CONFIG_WLAN_VENDOR_INTERSIL=y ++# CONFIG_HOSTAP is not set ++CONFIG_WLAN_VENDOR_MARVELL=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_WLAN_VENDOR_MEDIATEK=y ++CONFIG_WLAN_VENDOR_RALINK=y ++CONFIG_WLAN_VENDOR_REALTEK=y ++CONFIG_WLAN_VENDOR_RSI=y ++CONFIG_WLAN_VENDOR_ST=y ++CONFIG_WLAN_VENDOR_TI=y ++CONFIG_WLAN_VENDOR_ZYDAS=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVMEM=y ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_BCM63XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_SERIAL_STM32 is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_GPIOLIB=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_GPIO_MPC8XXX is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_ZX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# CONFIG_GPIO_TS4900 is not set ++ ++# ++# MFD GPIO expanders ++# ++# CONFIG_HTC_EGPIO is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++ ++# ++# SPI or I2C GPIO expanders ++# ++# CONFIG_GPIO_MCP23S08 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_POWER_RESET is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++# CONFIG_WATCHDOG_SYSFS is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_EXYNOS_LPASS is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=m ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2=m ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEOBUF2_CORE=m ++CONFIG_VIDEOBUF2_MEMOPS=m ++CONFIG_VIDEOBUF2_VMALLOC=m ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++# CONFIG_MEDIA_USB_SUPPORT is not set ++# CONFIG_V4L_PLATFORM_DRIVERS is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_SUSPEND_PORT is not set ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=m ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++# CONFIG_USB_DWC3_DUAL_ROLE is not set ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_OF_SIMPLE=m ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_GADGET_SSTAR_DEVICE is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_SS_GADGET=y ++CONFIG_USB_F_UVC=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_BI_DIRECTION is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++CONFIG_USB_G_WEBCAM=m ++CONFIG_USB_WEBCAM_UVC=y ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++CONFIG_SS_FAST_MMC=y ++# CONFIG_MMC_DEBUG is not set ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_EDAC_ATOMIC_SCRUB=y ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_UIO_PRUSS is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ION is not set ++# CONFIG_STAGING_BOARD is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LNET is not set ++# CONFIG_GS_FPGABOOT is not set ++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set ++# CONFIG_FB_TFT is not set ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_MOST is not set ++# CONFIG_KS7010 is not set ++# CONFIG_GREYBUS is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_NXP is not set ++CONFIG_COMMON_CLK_PWM=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_PIC32 is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_CLKSRC_PROBE=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ARM_TIMER_SP804 is not set ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# CONFIG_SUNXI_SRAM is not set ++# CONFIG_SOC_TI is not set ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++CONFIG_PHY_SSTAR_INFINITY6E=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++CONFIG_ARM_PMU=y ++# CONFIG_RAS is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++# CONFIG_ANDROID_BINDER_IPC is not set ++CONFIG_NVMEM=m ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++ ++# ++# FPGA Configuration Support ++# ++# CONFIG_FPGA is not set ++CONFIG_MSTAR_DRIVERS=y ++# CONFIG_CAM_DRIVERS is not set ++# CONFIG_DLA_DRIVER is not set ++# CONFIG_MS_PIU_TIMER is not set ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++# CONFIG_MS_MSYS_LOG is not set ++# CONFIG_MSYS_PERF_TEST is not set ++# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set ++# CONFIG_MSYS_MIU_PROTECT is not set ++# CONFIG_MSYS_DMEM_SYSFS_ALL is not set ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_USCLK is not set ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++# CONFIG_MS_PWM is not set ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++CONFIG_MS_EMMC=m ++CONFIG_MS_EMMC_UNIFY_DRIVER=y ++CONFIG_MS_SDMMC=m ++# CONFIG_MS_EMAC is not set ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++# CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IRCUT is not set ++# CONFIG_MS_RTC is not set ++# CONFIG_RTC_INNER is not set ++# CONFIG_RTCPWC_INNER=y ++# CONFIG_RTCPWC_INNER_EHHE=y ++CONFIG_MS_CRYPTO=y ++# CONFIG_SS_AESDMA_INTR is not set ++CONFIG_CRYPTODEV=m ++CONFIG_MS_CPU_FREQ=y ++# CONFIG_MS_IVE is not set ++CONFIG_MS_NOTIFY=y ++CONFIG_SS_ISP_ISRCB=y ++CONFIG_MSTAR_MIU=y ++CONFIG_SSC007A_S01A=y ++CONFIG_MS_BDMA=y ++# CONFIG_MS_BDMA_LINE_OFFSET_ON=y ++CONFIG_MS_MOVE_DMA=y ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INT_ISR=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_PADMUX=y ++CONFIG_MS_WATCHDOG=y ++# CONFIG_MS_SAR is not set ++CONFIG_MSTAR_MMAHEAP=y ++CONFIG_SSTAR_NETPHY=y ++CONFIG_SS_VOLTAGE_CTRL=y ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++# CONFIG_GDB_SCRIPTS is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHED_INFO is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_PROVE_RCU is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_PTDUMP is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_8250 is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++# CONFIG_CORESIGHT is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y ++# CONFIG_HARDENED_USERCOPY is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_SEQIV=y ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_ARM_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++# CONFIG_SG_SPLIT is not set ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h +old mode 100644 +new mode 100755 +diff --git a/arch/arm/include/asm/kasan.h b/arch/arm/include/asm/kasan.h +new file mode 100644 +index 000000000000..303c35df3135 +--- /dev/null ++++ b/arch/arm/include/asm/kasan.h +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * arch/arm/include/asm/kasan.h ++ * ++ * Copyright (c) 2015 Samsung Electronics Co., Ltd. ++ * Author: Andrey Ryabinin ++ * ++ */ ++ ++#ifndef __ASM_KASAN_H ++#define __ASM_KASAN_H ++ ++#ifdef CONFIG_KASAN ++ ++#include ++ ++#define KASAN_SHADOW_SCALE_SHIFT 3 ++ ++/* ++ * The compiler uses a shadow offset assuming that addresses start ++ * from 0. Kernel addresses don't start from 0, so shadow ++ * for kernel really starts from 'compiler's shadow offset' + ++ * ('kernel address space start' >> KASAN_SHADOW_SCALE_SHIFT) ++ */ ++ ++asmlinkage void kasan_early_init(void); ++extern void kasan_init(void); ++ ++#else ++static inline void kasan_init(void) { } ++#endif ++ ++#endif +diff --git a/arch/arm/include/asm/kasan_def.h b/arch/arm/include/asm/kasan_def.h +new file mode 100644 +index 000000000000..5739605aa7cf +--- /dev/null ++++ b/arch/arm/include/asm/kasan_def.h +@@ -0,0 +1,81 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * arch/arm/include/asm/kasan_def.h ++ * ++ * Copyright (c) 2018 Huawei Technologies Co., Ltd. ++ * ++ * Author: Abbott Liu ++ */ ++ ++#ifndef __ASM_KASAN_DEF_H ++#define __ASM_KASAN_DEF_H ++ ++#ifdef CONFIG_KASAN ++ ++/* ++ * Define KASAN_SHADOW_OFFSET,KASAN_SHADOW_START and KASAN_SHADOW_END for ++ * the Arm kernel address sanitizer. We are "stealing" lowmem (the 4GB ++ * addressable by a 32bit architecture) out of the virtual address ++ * space to use as shadow memory for KASan as follows: ++ * ++ * +----+ 0xffffffff ++ * | | \ ++ * | | |-> Static kernel image (vmlinux) BSS and page table ++ * | |/ ++ * +----+ PAGE_OFFSET ++ * | | \ ++ * | | |-> Loadable kernel modules virtual address space area ++ * | |/ ++ * +----+ MODULES_VADDR = KASAN_SHADOW_END ++ * | | \ ++ * | | |-> The shadow area of kernel virtual address. ++ * | |/ ++ * +----+-> TASK_SIZE (start of kernel space) = KASAN_SHADOW_START the ++ * | |\ shadow address of MODULES_VADDR ++ * | | | ++ * | | | ++ * | | |-> The user space area in lowmem. The kernel address ++ * | | | sanitizer do not use this space, nor does it map it. ++ * | | | ++ * | | | ++ * | | | ++ * | | | ++ * | |/ ++ * ------ 0 ++ * ++ * 1) KASAN_SHADOW_START ++ * This value begins with the MODULE_VADDR's shadow address. It is the ++ * start of kernel virtual space. Since we have modules to load, we need ++ * to cover also that area with shadow memory so we can find memory ++ * bugs in modules. ++ * ++ * 2) KASAN_SHADOW_END ++ * This value is the 0x100000000's shadow address: the mapping that would ++ * be after the end of the kernel memory at 0xffffffff. It is the end of ++ * kernel address sanitizer shadow area. It is also the start of the ++ * module area. ++ * ++ * 3) KASAN_SHADOW_OFFSET: ++ * This value is used to map an address to the corresponding shadow ++ * address by the following formula: ++ * ++ * shadow_addr = (address >> 3) + KASAN_SHADOW_OFFSET; ++ * ++ * As you would expect, >> 3 is equal to dividing by 8, meaning each ++ * byte in the shadow memory covers 8 bytes of kernel memory, so one ++ * bit shadow memory per byte of kernel memory is used. ++ * ++ * The KASAN_SHADOW_OFFSET is provided in a Kconfig option depending ++ * on the VMSPLIT layout of the system: the kernel and userspace can ++ * split up lowmem in different ways according to needs, so we calculate ++ * the shadow offset depending on this. ++ */ ++ ++#define KASAN_SHADOW_SCALE_SHIFT 3 ++#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL) ++#define KASAN_SHADOW_END ((UL(1) << (32 - KASAN_SHADOW_SCALE_SHIFT)) \ ++ + KASAN_SHADOW_OFFSET) ++#define KASAN_SHADOW_START ((KASAN_SHADOW_END >> 3) + KASAN_SHADOW_OFFSET) ++ ++#endif ++#endif +diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h +index 76cbd9c674df..07bf5602bb2e 100644 +--- a/arch/arm/include/asm/memory.h ++++ b/arch/arm/include/asm/memory.h +@@ -21,6 +21,7 @@ + #ifdef CONFIG_NEED_MACH_MEMORY_H + #include + #endif ++#include + + /* + * Allow for constants defined here to be used from assembly code +@@ -37,7 +38,11 @@ + * TASK_SIZE - the maximum size of a user space task. + * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area + */ ++#ifndef CONFIG_KASAN + #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M)) ++#else ++#define TASK_SIZE (KASAN_SHADOW_START) ++#endif + #define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M) + + /* +@@ -53,8 +58,12 @@ + #define MODULES_VADDR (PAGE_OFFSET - SZ_16M) + #else + /* smaller range for Thumb-2 symbols relocation (2^24)*/ ++#ifdef CONFIG_MODULES_AREA_SIZE ++#define MODULES_VADDR (PAGE_OFFSET - CONFIG_MODULES_AREA_SIZE) ++#else + #define MODULES_VADDR (PAGE_OFFSET - SZ_8M) + #endif ++#endif + + #if TASK_SIZE > MODULES_VADDR + #error Top of user space clashes with start of module space +diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h +old mode 100644 +new mode 100755 +index c2bf24f40177..7e99421696ee +--- a/arch/arm/include/asm/outercache.h ++++ b/arch/arm/include/asm/outercache.h +@@ -39,6 +39,9 @@ struct outer_cache_fns { + /* This is an ARM L2C thing */ + void (*write_sec)(unsigned long, unsigned); + void (*configure)(const struct l2x0_regs *); ++#ifdef CONFIG_MS_L2X0_PATCH ++ void (*flush_MIU_pipe)(void); ++#endif + }; + + extern struct outer_cache_fns outer_cache; +diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h +index a89b4076cde4..72821b4721ad 100644 +--- a/arch/arm/include/asm/percpu.h ++++ b/arch/arm/include/asm/percpu.h +@@ -16,6 +16,8 @@ + #ifndef _ASM_ARM_PERCPU_H_ + #define _ASM_ARM_PERCPU_H_ + ++#include ++ + /* + * Same as asm-generic/percpu.h, except that we store the per cpu offset + * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7 +diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h +index b2902a5cd780..0f5646c51d7a 100644 +--- a/arch/arm/include/asm/pgalloc.h ++++ b/arch/arm/include/asm/pgalloc.h +@@ -26,6 +26,7 @@ + #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) + + #ifdef CONFIG_ARM_LPAE ++#define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) + + static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) + { +@@ -44,14 +45,19 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) + } + + #else /* !CONFIG_ARM_LPAE */ ++#define PGD_SIZE (PAGE_SIZE << 2) + + /* + * Since we have only two-level page tables, these are trivial + */ + #define pmd_alloc_one(mm,addr) ({ BUG(); ((pmd_t *)2); }) + #define pmd_free(mm, pmd) do { } while (0) ++#ifdef CONFIG_KASAN ++/* The KASan core unconditionally calls pud_populate() on all architectures */ ++#define pud_populate(mm,pmd,pte) do { } while (0) ++#else + #define pud_populate(mm,pmd,pte) BUG() +- ++#endif + #endif /* CONFIG_ARM_LPAE */ + + extern pgd_t *pgd_alloc(struct mm_struct *mm); +diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h +new file mode 100644 +index 000000000000..1f93aee1f630 +--- /dev/null ++++ b/arch/arm/include/asm/secure_cntvoff.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef __ASMARM_ARCH_CNTVOFF_H ++#define __ASMARM_ARCH_CNTVOFF_H ++ ++extern void secure_cntvoff_init(void); ++ ++#endif +diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h +index cf4f3aad0fc1..d6e1abb3149b 100644 +--- a/arch/arm/include/asm/string.h ++++ b/arch/arm/include/asm/string.h +@@ -4,6 +4,9 @@ + /* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. ++ * ++ * The __underscore versions of some functions are for KASan to be able ++ * to replace them with instrumented versions. + */ + + #define __HAVE_ARCH_STRRCHR +@@ -14,28 +17,37 @@ extern char * strchr(const char * s, int c); + + #define __HAVE_ARCH_MEMCPY + extern void * memcpy(void *, const void *, __kernel_size_t); ++extern void *__memcpy(void *dest, const void *src, __kernel_size_t n); + + #define __HAVE_ARCH_MEMMOVE + extern void * memmove(void *, const void *, __kernel_size_t); ++extern void *__memmove(void *dest, const void *src, __kernel_size_t n); + + #define __HAVE_ARCH_MEMCHR + extern void * memchr(const void *, int, __kernel_size_t); + + #define __HAVE_ARCH_MEMSET + extern void * memset(void *, int, __kernel_size_t); ++extern void *__memset(void *s, int c, __kernel_size_t n); + +-extern void __memzero(void *ptr, __kernel_size_t n); +- +-#define memset(p,v,n) \ +- ({ \ +- void *__p = (p); size_t __n = n; \ +- if ((__n) != 0) { \ +- if (__builtin_constant_p((v)) && (v) == 0) \ +- __memzero((__p),(__n)); \ +- else \ +- memset((__p),(v),(__n)); \ +- } \ +- (__p); \ +- }) ++/* ++ * For files that are not instrumented (e.g. mm/slub.c) we ++ * must use non-instrumented versions of the mem* ++ * functions named __memcpy() etc. All such kernel code has ++ * been tagged with KASAN_SANITIZE_file.o = n, which means ++ * that the address sanitization argument isn't passed to the ++ * compiler, and __SANITIZE_ADDRESS__ is not set. As a result ++ * these defines kick in. ++ */ ++#if defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__) ++#define memcpy(dst, src, len) __memcpy(dst, src, len) ++#define memmove(dst, src, len) __memmove(dst, src, len) ++#define memset(s, c, n) __memset(s, c, n) ++ ++#ifndef __NO_FORTIFY ++#define __NO_FORTIFY /* FORTIFY_SOURCE uses __builtin_memcpy, etc. */ ++#endif ++ ++#endif + + #endif +diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h +index 776757d1604a..37cb802ae8fa 100644 +--- a/arch/arm/include/asm/thread_info.h ++++ b/arch/arm/include/asm/thread_info.h +@@ -16,7 +16,15 @@ + #include + #include + ++#ifdef CONFIG_KASAN ++/* ++ * KASan uses a lot of extra stack space so the thread size order needs to ++ * be increased. ++ */ ++#define THREAD_SIZE_ORDER 2 ++#else + #define THREAD_SIZE_ORDER 1 ++#endif + #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) + #define THREAD_START_SP (THREAD_SIZE - 8) + +diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile +old mode 100644 +new mode 100755 +index ad325a8c7e1e..6d6123d4c374 +--- a/arch/arm/kernel/Makefile ++++ b/arch/arm/kernel/Makefile +@@ -2,6 +2,8 @@ + # Makefile for the linux kernel. + # + ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ + CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) + AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) + +@@ -20,6 +22,9 @@ obj-y := elf.o entry-common.o irq.o opcodes.o \ + setup.o signal.o sigreturn_codes.o \ + stacktrace.o sys_arm.o time.o traps.o + ++KASAN_SANITIZE_stacktrace.o := n ++KASAN_SANITIZE_traps.o := n ++ + obj-$(CONFIG_ATAGS) += atags_parse.o + obj-$(CONFIG_ATAGS_PROC) += atags_proc.o + obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o +diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c +index 8e8d20cdbce7..da100c70faf0 100644 +--- a/arch/arm/kernel/armksyms.c ++++ b/arch/arm/kernel/armksyms.c +@@ -90,7 +90,6 @@ EXPORT_SYMBOL(memset); + EXPORT_SYMBOL(memcpy); + EXPORT_SYMBOL(memmove); + EXPORT_SYMBOL(memchr); +-EXPORT_SYMBOL(__memzero); + + EXPORT_SYMBOL(mmioset); + EXPORT_SYMBOL(mmiocpy); +diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c +old mode 100644 +new mode 100755 +index f676febbb270..5a02de1c646b +--- a/arch/arm/kernel/devtree.c ++++ b/arch/arm/kernel/devtree.c +@@ -28,6 +28,9 @@ + #include + #include + ++#ifdef CONFIG_SS_BUILTIN_DTB ++extern void *builtin_dtb_start; ++#endif + + #ifdef CONFIG_SMP + extern struct of_cpu_method __cpu_method_of_table[]; +@@ -208,7 +211,52 @@ static const void * __init arch_get_next_mach(const char *const **match) + *match = m->dt_compat; + return m; + } ++#ifdef CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT ++__initdata int gb_ATAG_CMDLINE_found = 0; ++__initdata int gb_ATAG_INITRD2_found = 0; + ++int early_atags_to_data(void *atag_list) ++{ ++ struct tag *atag = atag_list; ++ /* In the case of 64 bits memory size, need to reserve 2 cells for ++ * address and size for each bank */ ++ ++ /* make sure we've got an aligned pointer */ ++ if ((u32)atag_list & 0x3) ++ return 1; ++ ++ ++ /* validate the ATAG */ ++ if (atag->hdr.tag != ATAG_CORE || ++ (atag->hdr.size != tag_size(tag_core) && ++ atag->hdr.size != 2)) ++ return 1; ++ ++ ++ for_each_tag(atag, atag_list) { ++ if (atag->hdr.tag == ATAG_CMDLINE) ++ { ++ strcpy(boot_command_line, atag->u.cmdline.cmdline); ++ gb_ATAG_CMDLINE_found = 1; ++ } ++ else if (atag->hdr.tag == ATAG_INITRD2) ++ { ++ /* 1 if it is not an error if initrd_start < memory_start */ ++ extern int initrd_below_start_ok; ++ ++ /* free_initrd_mem always gets called with the next two as arguments.. */ ++ extern unsigned long initrd_start, initrd_end; ++ ++ initrd_start = (unsigned long)__va(atag->u.initrd.start); ++ initrd_end = (unsigned long)__va(atag->u.initrd.start+atag->u.initrd.size); ++ initrd_below_start_ok = 1; ++ gb_ATAG_INITRD2_found = 1; ++ } ++ } ++ ++ return 0; ++} ++#endif + /** + * setup_machine_fdt - Machine setup when an dtb was passed to the kernel + * @dt_phys: physical address of dt blob +@@ -230,7 +278,32 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) + #endif + + if (!dt_phys || !early_init_dt_verify(phys_to_virt(dt_phys))) +- return NULL; ++ { ++#ifdef CONFIG_SS_BUILTIN_DTB ++ if(early_init_dt_verify(builtin_dtb_start)) ++ { ++#ifdef CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT ++ if((!dt_phys ) || (!early_atags_to_data(phys_to_virt(dt_phys)))) ++ { ++ early_print("early_atags_to_data() success\n"); ++ } ++ ++#else ++ extern int early_atags_to_fdt(void *atag_list, void *fdt, int total_space); ++ extern u32 builtin_dtb_size; ++ if((!dt_phys ) || (!early_atags_to_fdt(phys_to_virt(dt_phys),builtin_dtb_start,builtin_dtb_size))) ++ { ++ early_print("early_atags_to_fdt() success\n"); ++ } ++#endif ++ ++ } ++ else ++#endif ++ { ++ return NULL; ++ } ++ } + + mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach); + +diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S +index 9f157e7c51e7..eea979ee561d 100644 +--- a/arch/arm/kernel/entry-armv.S ++++ b/arch/arm/kernel/entry-armv.S +@@ -187,7 +187,7 @@ ENDPROC(__und_invalid) + + get_thread_info tsk + ldr r0, [tsk, #TI_ADDR_LIMIT] +- mov r1, #TASK_SIZE ++ ldr r1, =TASK_SIZE + str r1, [tsk, #TI_ADDR_LIMIT] + str r0, [sp, #SVC_ADDR_LIMIT] + +@@ -441,7 +441,8 @@ ENDPROC(__fiq_abt) + @ if it was interrupted in a critical region. Here we + @ perform a quick test inline since it should be false + @ 99.9999% of the time. The rest is done out of line. +- cmp r4, #TASK_SIZE ++ ldr r0, =TASK_SIZE ++ cmp r4, r0 + blhs kuser_cmpxchg64_fixup + #endif + #endif +diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S +old mode 100644 +new mode 100755 +index 10c3283d6c19..72817169f70b +--- a/arch/arm/kernel/entry-common.S ++++ b/arch/arm/kernel/entry-common.S +@@ -32,6 +32,7 @@ + * features make this path too inefficient. + */ + ret_fast_syscall: ++__ret_fast_syscall: + UNWIND(.fnstart ) + UNWIND(.cantunwind ) + disable_irq_notrace @ disable interrupts +@@ -57,6 +58,7 @@ fast_work_pending: + * r0 first to avoid needing to save registers around each C function call. + */ + ret_fast_syscall: ++__ret_fast_syscall: + UNWIND(.fnstart ) + UNWIND(.cantunwind ) + str r0, [sp, #S_R0 + S_OFF]! @ save returned r0 +@@ -224,7 +226,7 @@ local_restart: + bne __sys_trace + + cmp scno, #NR_syscalls @ check upper syscall limit +- badr lr, ret_fast_syscall @ return address ++ badr lr, __ret_fast_syscall @ return address + ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + + add r1, sp, #S_OFF +@@ -246,7 +248,7 @@ local_restart: + 9001: + sub lr, lr, #4 + str lr, [sp, #S_PC] +- b ret_fast_syscall ++ b __ret_fast_syscall + #endif + ENDPROC(vector_swi) + +diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S +index 8733012d231f..8f35aee9950b 100644 +--- a/arch/arm/kernel/head-common.S ++++ b/arch/arm/kernel/head-common.S +@@ -101,6 +101,9 @@ __mmap_switched: + str r2, [r6] @ Save atags pointer + cmp r7, #0 + strne r0, [r7] @ Save control register values ++#ifdef CONFIG_KASAN ++ bl kasan_early_init ++#endif + b start_kernel + ENDPROC(__mmap_switched) + +diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c +index 4f14b5ce6535..ddbe55856765 100644 +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -40,8 +40,15 @@ + #ifdef CONFIG_MMU + void *module_alloc(unsigned long size) + { +- void *p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, +- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, ++ gfp_t gfp_mask = GFP_KERNEL; ++ void *p; ++ ++ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) { ++ /* Silence the initial allocation */ ++ gfp_mask |= __GFP_NOWARN; ++ } ++ p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, ++ gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, + __builtin_return_address(0)); + if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p) + return p; +diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c +old mode 100644 +new mode 100755 +index f4e54503afa9..8c748f61f4a4 +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -62,6 +62,7 @@ + #include + #include + #include ++#include + + #include "atags.h" + +@@ -1058,6 +1059,7 @@ void __init hyp_mode_check(void) + #endif + } + ++void __init prom_meminit(void); + void __init setup_arch(char **cmdline_p) + { + const struct machine_desc *mdesc; +@@ -1086,7 +1088,9 @@ void __init setup_arch(char **cmdline_p) + early_ioremap_init(); + + parse_early_param(); +- ++#ifdef CONFIG_ARCH_SSTAR ++ prom_meminit(); ++#endif + #ifdef CONFIG_MMU + early_paging_init(mdesc); + #endif +@@ -1105,6 +1109,7 @@ void __init setup_arch(char **cmdline_p) + early_ioremap_reset(); + + paging_init(mdesc); ++ kasan_init(); + request_standard_resources(mdesc); + + if (mdesc->restart) +@@ -1211,10 +1216,13 @@ static const char *hwcap2_str[] = { + NULL + }; + ++extern unsigned int get_cpufreq_testout(void); ++ + static int c_show(struct seq_file *m, void *v) + { + int i, j; + u32 cpuid; ++ u32 cpu_mhz; + + for_each_online_cpu(i) { + /* +@@ -1227,6 +1235,10 @@ static int c_show(struct seq_file *m, void *v) + seq_printf(m, "model name\t: %s rev %d (%s)\n", + cpu_name, cpuid & 15, elf_platform); + ++ cpu_mhz = get_cpufreq_testout(); ++ seq_printf(m, "cpu MHz\t\t: %d.%03d\n", ++ cpu_mhz/1000000, (cpu_mhz/1000)%1000); ++ + #if defined(CONFIG_SMP) + seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", + per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ), +diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c +old mode 100644 +new mode 100755 +index 7dd14e8395e6..0e292ea61428 +--- a/arch/arm/kernel/smp.c ++++ b/arch/arm/kernel/smp.c +@@ -51,6 +51,10 @@ + #define CREATE_TRACE_POINTS + #include + ++#ifdef CONFIG_LH_RTOS ++#include "drv_dualos.h" ++#endif ++ + /* + * as from 2.5, kernels no longer have an init_tasks structure + * so we need some other way of telling a new secondary core +@@ -78,6 +82,10 @@ enum ipi_msg_type { + * not be usable by the kernel. Please keep the above limited + * to at most 8 entries. + */ ++#ifdef CONFIG_LH_RTOS ++ IPI_RTOS_2_LINUX_NBLK_CALL_REQ = IPI_NR_RTOS_2_LINUX_NBLK_CALL_REQ, ++ IPI_REROUTE_SMC = IPI_NR_REROUTE_SMC, ++#endif + }; + + static DECLARE_COMPLETION(cpu_running); +@@ -651,6 +659,38 @@ void handle_IPI(int ipinr, struct pt_regs *regs) + printk_nmi_exit(); + break; + ++#ifdef CONFIG_LH_RTOS ++ /* 8/9/10 are compatible for old MI ack */ ++ case 8: ++ case 9: ++ case 10: ++ { ++ void handle_rsq(int); ++ irq_enter(); ++ handle_rsq(ipinr); ++ irq_exit(); ++ break; ++ } ++ ++#if ENABLE_NBLK_CALL ++ case IPI_RTOS_2_LINUX_NBLK_CALL_REQ: ++ { ++ irq_enter(); ++ handle_interos_nblk_call_req(); ++ irq_exit(); ++ break; ++ } ++#endif ++ ++ case IPI_REROUTE_SMC: ++ { ++ irq_enter(); ++ handle_reroute_smc(); ++ irq_exit(); ++ break; ++ } ++#endif ++ + default: + pr_crit("CPU%u: Unknown IPI message 0x%x\n", + cpu, ipinr); +diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c +old mode 100644 +new mode 100755 +index 1b304897aa12..61e6d4b44b12 +--- a/arch/arm/kernel/traps.c ++++ b/arch/arm/kernel/traps.c +@@ -245,6 +245,9 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) + dump_backtrace(NULL, tsk); + barrier(); + } ++#ifdef CONFIG_ARCH_SSTAR ++EXPORT_SYMBOL(show_stack); ++#endif + + #ifdef CONFIG_PREEMPT + #define S_PREEMPT " PREEMPT" +diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c +index 0bee233fef9a..1597008a1289 100644 +--- a/arch/arm/kernel/unwind.c ++++ b/arch/arm/kernel/unwind.c +@@ -249,7 +249,11 @@ static int unwind_pop_register(struct unwind_ctrl_block *ctrl, + if (*vsp >= (unsigned long *)ctrl->sp_high) + return -URC_FAILURE; + +- ctrl->vrs[reg] = *(*vsp)++; ++ /* Use READ_ONCE_NOCHECK here to avoid this memory access ++ * from being tracked by KASAN. ++ */ ++ ctrl->vrs[reg] = READ_ONCE_NOCHECK(*(*vsp)); ++ (*vsp)++; + return URC_OK; + } + +diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile +index 27f4d96258a2..6889e7e498ad 100644 +--- a/arch/arm/lib/Makefile ++++ b/arch/arm/lib/Makefile +@@ -7,7 +7,7 @@ + lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ + csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ + delay.o delay-loop.o findbit.o memchr.o memcpy.o \ +- memmove.o memset.o memzero.o setbit.o \ ++ memmove.o memset.o setbit.o \ + strchr.o strrchr.o \ + testchangebit.o testclearbit.o testsetbit.o \ + ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ +diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S +index 64111bd4440b..79a83f82e174 100644 +--- a/arch/arm/lib/memcpy.S ++++ b/arch/arm/lib/memcpy.S +@@ -61,6 +61,8 @@ + + /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ + ++.weak memcpy ++ENTRY(__memcpy) + ENTRY(mmiocpy) + ENTRY(memcpy) + +@@ -68,3 +70,4 @@ ENTRY(memcpy) + + ENDPROC(memcpy) + ENDPROC(mmiocpy) ++ENDPROC(__memcpy) +diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S +index 69a9d47fc5ab..313db6c6d37f 100644 +--- a/arch/arm/lib/memmove.S ++++ b/arch/arm/lib/memmove.S +@@ -27,12 +27,14 @@ + * occurring in the opposite direction. + */ + ++.weak memmove ++ENTRY(__memmove) + ENTRY(memmove) + UNWIND( .fnstart ) + + subs ip, r0, r1 + cmphi r2, ip +- bls memcpy ++ bls __memcpy + + stmfd sp!, {r0, r4, lr} + UNWIND( .fnend ) +@@ -225,3 +227,4 @@ ENTRY(memmove) + 18: backward_copy_shift push=24 pull=8 + + ENDPROC(memmove) ++ENDPROC(__memmove) +diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S +index 3c65e3bd790f..7b4c97a9eb63 100644 +--- a/arch/arm/lib/memset.S ++++ b/arch/arm/lib/memset.S +@@ -16,6 +16,8 @@ + .text + .align 5 + ++.weak memset ++ENTRY(__memset) + ENTRY(mmioset) + ENTRY(memset) + UNWIND( .fnstart ) +@@ -135,3 +137,4 @@ UNWIND( .fnstart ) + UNWIND( .fnend ) + ENDPROC(memset) + ENDPROC(mmioset) ++ENDPROC(__memset) +diff --git a/arch/arm/mach-sstar/Kconfig b/arch/arm/mach-sstar/Kconfig +new file mode 100755 +index 000000000000..80b234308995 +--- /dev/null ++++ b/arch/arm/mach-sstar/Kconfig +@@ -0,0 +1,144 @@ ++menuconfig ARCH_SSTAR ++ bool "SStar ARM SoCs" ++ ++if ARCH_SSTAR ++ ++config SS_DUALOS ++ bool "SStar Dual-OS" ++ ++choice ++ prompt "Select types of SStar Dual-OS" ++ depends on SS_DUALOS ++ ++ config LH_RTOS ++ bool "Enable Hypervisor" if ARCH_MULTI_V7 ++ help ++ Enable LH + RTOS. ++ ++ config SS_AMP ++ bool "Enable SStar AMP" if ARCH_MULTI_V7 ++ help ++ Enable SStar AMP. ++endchoice ++ ++config MODULES_AREA_SIZE ++ hex "Modules area size" ++ depends on MMU && THUMB2_KERNEL ++ default 0x00800000 ++ help ++ Config memory use for modules install. Because ARM can only branch relatively within +/- 32MB. ++ If the difference between the lowest module address and the highest of .text is greater than ++ 32MB, it's impossible to load modules they will fail to link. ++ ++comment "Options" ++config SS_DTB_NAME ++ string "Sstar DTB NAME" ++ default "" ++ depends on SS_BUILTIN_DTB ++ ++config SS_BUILTIN_DTB ++ bool "Sstar Builtin DTB" ++ default y ++ ++config MS_L2X0_PATCH ++ bool "L2X0 patch" ++ depends on CACHE_L2X0 ++ default y ++ ++config MS_KERNEL_TYPE ++ string ++ default "" ++ ++config MS_ARMV7_XIP ++ bool ++ default y ++ depends on XIP_KERNEL ++ ++ ++config SSTAR_CHIP_FOLDER ++ string ++ option env="SSTAR_CHIP_MODEL" ++ ++config SSTAR_CHIP_NAME ++ string ++ default SSTAR_CHIP_FOLDER ++ ++config SSTAR_SHORT_NAME ++ string "Short Name" ++ default "" ++ ++config MP_IRQ_TRACE ++ bool "MP_IRQ_TRACE" ++ default n ++ ++config SS_GIC_SET_MULTI_CPUS ++ bool "Set GIC affinity to multiple CPUs according to affinity_hint" ++ depends on SMP ++ default y ++ ++config SKIP_SQUASHFS_BAD_BLOCK ++ bool "Skip squashfs bad block" ++ depends on MTD ++ default y ++ ++menu "Fast boot" ++config SS_BUILTIN_UNFDT ++ bool "FB_DTS: Builtin unflatted device tree" ++ depends on SS_BUILTIN_DTB ++ default n ++ ++config FB_DTS_SKIP_CRC ++ bool "FB_DTS: Skip check DTB CRC " ++ default n ++ ++config FB_DTS_SCAN_MEMORY_ONCE ++ bool "FB_DTS: Only search once for memory node" ++ default n ++ ++config FB_DTS_SKIP_ATAGS_TO_FDT ++ bool "FB_DTS: Search ATAG_INITRD2 and ATAG_CMDLINE from atags instead of early_atags_to_fdt" ++ default n ++ ++config DISABLE_CLK_DEBUGFS_SUPPORT ++ bool "Do not create the debugfs clk directory" ++ default y ++ ++config DEFERRED_INIICALLS ++ bool "Support deferred initcalls" ++ default y ++ ++config DEFERRED_INIICALLS_SLAB_SYSFS ++ bool "defer slab_sysfs_init" ++ depends on DEFERRED_INIICALLS ++ default n ++ ++config DEFERRED_INIICALLS_PARAM_SYSFS ++ bool "defer param_sysfs_init" ++ depends on DEFERRED_INIICALLS ++ default n ++ ++config DEFERRED_INIICALLS_PPERF_SYSFS ++ bool "defer perf_event_sysfs_init" ++ depends on DEFERRED_INIICALLS ++ default n ++ ++config DEFERRED_INIICALLS_MORE_SYSFS ++ bool "defer irq_sysfs_init, init_clocksource_sysfs,clockevents_init_sysfs" ++ depends on DEFERRED_INIICALLS ++ default n ++ ++config DEFERRED_CREATE_DTS_SYSNODE ++ bool "defer of_core_init" ++ depends on DEFERRED_INIICALLS ++ default n ++ ++config CRYPTO_MANAGER_NO_TESTS_THREAD ++ bool "Do not create cryto test thread" ++ depends on CRYPTO_MANAGER_DISABLE_TESTS ++ default n ++endmenu ++ ++source "arch/arm/mach-sstar/$SSTAR_CHIP_NAME/Kconfig" ++ ++endif ++ +diff --git a/arch/arm/mach-sstar/Makefile b/arch/arm/mach-sstar/Makefile +new file mode 100755 +index 000000000000..998c41ae72a5 +--- /dev/null ++++ b/arch/arm/mach-sstar/Makefile +@@ -0,0 +1,9 @@ ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += ms_chip.o atags_to_fdt.o ++obj-$(CONFIG_TI_CMEM_STUB) += cmemk_stub.o ++obj-y += $(CONFIG_SSTAR_CHIP_NAME)/ ++obj-$(CONFIG_SS_PROFILING_TIME) += prof.o +diff --git a/arch/arm/mach-sstar/Makefile.boot b/arch/arm/mach-sstar/Makefile.boot +new file mode 100755 +index 000000000000..e69de29bb2d1 +diff --git a/arch/arm/mach-sstar/atags_to_fdt.c b/arch/arm/mach-sstar/atags_to_fdt.c +new file mode 100755 +index 000000000000..4de55a1ebeb0 +--- /dev/null ++++ b/arch/arm/mach-sstar/atags_to_fdt.c +@@ -0,0 +1,218 @@ ++/* ++* atags_to_fdt.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "libfdt.h" ++ ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) ++#define do_extend_cmdline 1 ++#else ++#define do_extend_cmdline 0 ++#endif ++ ++#define NR_BANKS 16 ++ ++static int node_offset(void *fdt, const char *node_path) ++{ ++ int offset = fdt_path_offset(fdt, node_path); ++ if (offset == -FDT_ERR_NOTFOUND) ++ offset = fdt_add_subnode(fdt, 0, node_path); ++ return offset; ++} ++#if 0 ++static int setprop(void *fdt, const char *node_path, const char *property, ++ uint32_t *val_array, int size) ++{ ++ int offset = node_offset(fdt, node_path); ++ if (offset < 0) ++ return offset; ++ return fdt_setprop(fdt, offset, property, val_array, size); ++} ++#endif ++ ++static int setprop_string(void *fdt, const char *node_path, ++ const char *property, const char *string) ++{ ++ int offset = node_offset(fdt, node_path); ++ if (offset < 0) ++ return offset; ++ return fdt_setprop_string(fdt, offset, property, string); ++} ++ ++static int setprop_cell(void *fdt, const char *node_path, ++ const char *property, uint32_t val) ++{ ++ int offset = node_offset(fdt, node_path); ++ if (offset < 0) ++ return offset; ++ return fdt_setprop_cell(fdt, offset, property, val); ++} ++ ++static const void *getprop(const void *fdt, const char *node_path, ++ const char *property, int *len) ++{ ++ int offset = fdt_path_offset(fdt, node_path); ++ ++ if (offset == -FDT_ERR_NOTFOUND) ++ return NULL; ++ ++ return fdt_getprop(fdt, offset, property, len); ++} ++#if 0 ++static uint32_t get_cell_size(const void *fdt) ++{ ++ int len; ++ uint32_t cell_size = 1; ++ const uint32_t *size_len = getprop(fdt, "/", "#size-cells", &len); ++ ++ if (size_len) ++ cell_size = fdt32_to_cpu(*size_len); ++ return cell_size; ++} ++#endif ++static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) ++{ ++ char cmdline[COMMAND_LINE_SIZE]; ++ const char *fdt_bootargs; ++ char *ptr = cmdline; ++ int len = 0; ++ ++ /* copy the fdt command line into the buffer */ ++ fdt_bootargs = getprop(fdt, "/chosen", "bootargs", &len); ++ if (fdt_bootargs) ++ if (len < COMMAND_LINE_SIZE) { ++ memcpy(ptr, fdt_bootargs, len); ++ /* len is the length of the string ++ * including the NULL terminator */ ++ ptr += len - 1; ++ } ++ ++ /* and append the ATAG_CMDLINE */ ++ if (fdt_cmdline) { ++ len = strlen(fdt_cmdline); ++ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { ++ *ptr++ = ' '; ++ memcpy(ptr, fdt_cmdline, len); ++ ptr += len; ++ } ++ } ++ *ptr = '\0'; ++ ++ setprop_string(fdt, "/chosen", "bootargs", cmdline); ++} ++ ++/* ++ * Convert and fold provided ATAGs into the provided FDT. ++ * ++ * REturn values: ++ * = 0 -> pretend success ++ * = 1 -> bad ATAG (may retry with another possible ATAG pointer) ++ * < 0 -> error from libfdt ++ */ ++int early_atags_to_fdt(void *atag_list, void *fdt, int total_space) ++{ ++ struct tag *atag = atag_list; ++ /* In the case of 64 bits memory size, need to reserve 2 cells for ++ * address and size for each bank */ ++#if 0 /* Ignore memory atag, always use dtb */ ++ uint32_t mem_reg_property[2 * 2 * NR_BANKS]; ++ int memcount = 0, memsize; ++#endif ++ int ret; ++ ++ /* make sure we've got an aligned pointer */ ++ if ((u32)atag_list & 0x3) ++ return 1; ++ ++ /* if we get a DTB here we're done already */ ++ if (*(u32 *)atag_list == fdt32_to_cpu(FDT_MAGIC)) ++ return 0; ++ ++ /* validate the ATAG */ ++ if (atag->hdr.tag != ATAG_CORE || ++ (atag->hdr.size != tag_size(tag_core) && ++ atag->hdr.size != 2)) ++ return 1; ++ ++ /* let's give it all the room it could need */ ++ ret = fdt_open_into(fdt, fdt, total_space); ++ if (ret < 0) ++ return ret; ++ ++ for_each_tag(atag, atag_list) { ++ if (atag->hdr.tag == ATAG_CMDLINE) { ++ /* Append the ATAGS command line to the device tree ++ * command line. ++ * NB: This means that if the same parameter is set in ++ * the device tree and in the tags, the one from the ++ * tags will be chosen. ++ */ ++ if (do_extend_cmdline) ++ merge_fdt_bootargs(fdt, ++ atag->u.cmdline.cmdline); ++ else ++ setprop_string(fdt, "/chosen", "bootargs", ++ atag->u.cmdline.cmdline); ++ } ++#if 0 /* Ignore memory atag, always use dtb */ ++ else if (atag->hdr.tag == ATAG_MEM) { ++ if (memcount >= sizeof(mem_reg_property)/4) ++ continue; ++ if (!atag->u.mem.size) ++ continue; ++ memsize = get_cell_size(fdt); ++ ++ if (memsize == 2) { ++ /* if memsize is 2, that means that ++ * each data needs 2 cells of 32 bits, ++ * so the data are 64 bits */ ++ uint64_t *mem_reg_prop64 = ++ (uint64_t *)mem_reg_property; ++ if (memcount >= (sizeof(mem_reg_property)/4)*2*2) ++ continue; ++ mem_reg_prop64[memcount++] = ++ cpu_to_fdt64(atag->u.mem.start); ++ mem_reg_prop64[memcount++] = ++ cpu_to_fdt64(atag->u.mem.size); ++ } else { ++ mem_reg_property[memcount++] = ++ cpu_to_fdt32(atag->u.mem.start); ++ mem_reg_property[memcount++] = ++ cpu_to_fdt32(atag->u.mem.size); ++ } ++ ++ } ++#endif ++ else if (atag->hdr.tag == ATAG_INITRD2) { ++ uint32_t initrd_start, initrd_size; ++ initrd_start = atag->u.initrd.start; ++ initrd_size = atag->u.initrd.size; ++ setprop_cell(fdt, "/chosen", "linux,initrd-start", ++ initrd_start); ++ setprop_cell(fdt, "/chosen", "linux,initrd-end", ++ initrd_start + initrd_size); ++ } ++ } ++#if 0 ++ if (memcount) { ++ setprop(fdt, "/memory", "reg", mem_reg_property, ++ 4 * memcount * memsize); ++ } ++#endif ++ ++ return fdt_pack(fdt); ++} +diff --git a/arch/arm/mach-sstar/fdt.h b/arch/arm/mach-sstar/fdt.h +new file mode 100755 +index 000000000000..74bbc1e5d5c9 +--- /dev/null ++++ b/arch/arm/mach-sstar/fdt.h +@@ -0,0 +1,77 @@ ++/* ++* fdt.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _FDT_H ++#define _FDT_H ++ ++#ifndef __ASSEMBLY__ ++ ++struct fdt_header { ++ uint32_t magic; /* magic word FDT_MAGIC */ ++ uint32_t totalsize; /* total size of DT block */ ++ uint32_t off_dt_struct; /* offset to structure */ ++ uint32_t off_dt_strings; /* offset to strings */ ++ uint32_t off_mem_rsvmap; /* offset to memory reserve map */ ++ uint32_t version; /* format version */ ++ uint32_t last_comp_version; /* last compatible version */ ++ ++ /* version 2 fields below */ ++ uint32_t boot_cpuid_phys; /* Which physical CPU id we're ++ booting on */ ++ /* version 3 fields below */ ++ uint32_t size_dt_strings; /* size of the strings block */ ++ ++ /* version 17 fields below */ ++ uint32_t size_dt_struct; /* size of the structure block */ ++}; ++ ++struct fdt_reserve_entry { ++ uint64_t address; ++ uint64_t size; ++}; ++ ++struct fdt_node_header { ++ uint32_t tag; ++ char name[0]; ++}; ++ ++struct fdt_property { ++ uint32_t tag; ++ uint32_t len; ++ uint32_t nameoff; ++ char data[0]; ++}; ++ ++#endif /* !__ASSEMBLY */ ++ ++#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ ++#define FDT_TAGSIZE sizeof(uint32_t) ++ ++#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ ++#define FDT_END_NODE 0x2 /* End node */ ++#define FDT_PROP 0x3 /* Property: name off, ++ size, content */ ++#define FDT_NOP 0x4 /* nop */ ++#define FDT_END 0x9 ++ ++#define FDT_V1_SIZE (7*sizeof(uint32_t)) ++#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t)) ++#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t)) ++#define FDT_V16_SIZE FDT_V3_SIZE ++#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t)) ++ ++#endif /* _FDT_H */ +diff --git a/arch/arm/mach-sstar/include/mach/uncompress.h b/arch/arm/mach-sstar/include/mach/uncompress.h +new file mode 100755 +index 000000000000..0e2949b0fae9 +--- /dev/null ++++ b/arch/arm/mach-sstar/include/mach/uncompress.h +@@ -0,0 +1,7 @@ ++#ifdef CONFIG_DEBUG_UNCOMPRESS ++extern void putc(int c); ++#else ++static inline void putc(int c) {} ++#endif ++static inline void flush(void) {} ++static inline void arch_decomp_setup(void) {} +diff --git a/arch/arm/mach-sstar/infinity2/Kconfig b/arch/arm/mach-sstar/infinity2/Kconfig +new file mode 100755 +index 000000000000..3276f88baa00 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/Kconfig +@@ -0,0 +1,25 @@ ++config ARCH_INFINITY2 ++ bool "SoC iNfinity2 (ARCH_MULTI_V7)" ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ select HAVE_ARM_SCU if SMP ++ select ARM_GLOBAL_TIMER ++ select CACHE_L2X0 ++ help ++ Support for iNfinity2 SoC ++ ++config SS_PROFILING_TIME ++ bool "Record timestamp in sram" ++ default n ++ ++config MP_PLATFORM_GIC_SET_MULTIPLE_CPUS ++ bool "MP_PLATFORM_GIC_SET_MULTIPLE_CPUS" ++ depends on SMP ++ default y ++config MP_GLOBAL_TIMER_CLK ++ bool "MP_GLOBAL_TIMER_CLK" ++ default y +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity2/Makefile b/arch/arm/mach-sstar/infinity2/Makefile +new file mode 100755 +index 000000000000..a5994f0f7f61 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/Makefile +@@ -0,0 +1,8 @@ ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ ++obj-y += soc.o ++obj-y += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o ++obj-$(CONFIG_SMP) += smp_platform.o smp_head.o cache.o +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity2/cache.S b/arch/arm/mach-sstar/infinity2/cache.S +new file mode 100755 +index 000000000000..977d3dceb772 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/cache.S +@@ -0,0 +1,153 @@ ++//* ++//* $Id: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/boot.S#3 $ ++//* $Header: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/boot.S#3 $ ++//* $Date: 2015/06/16 $ ++//* $DateTime: 2015/06/16 15:12:51 $ ++//* $Change: 1258698 $ ++//* $File: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/boot.S $ ++//* $Revision: #3 $ ++//* ++ ++//#include "include/platform.h" ++//#include "include/arm.include" ++//#include "include/macro.include" ++//#include "drv_arm.inc" ++ ++.text ++.arm ++ ++////// CODE ++ ++cpu_start_init_cache: .global cpu_start_init_cache ++ ++ mov r0, #0 ++ mcr p15, 0, r0, c8, c7, 0 ++ // Invalidate Inst TLB and Data TLB ++ mcr p15, 0, r0, c7, c5, 0 ++ // Invalidate I Cache ++ // Invalidate D-cache by set/way ++ // Note: for Cortex-A9, there is no instruction for invalidating ++ // the whole D-cache. Need to invalidate line by line. ++ // Read cache size from the Cache Size Identification Register ++ mrc p15, 1, r3, c0, c0, 0 // Read current Cache Size Identification Register ++ mov r1, #0x200 ++ sub r1, r1, #1 ++ ++ and r3, r1, r3, LSR #13 // r3 = (number of sets - 1) ++ mov r0, #0 // r0 -> way counter ++ 150: ++ mov r1, #0 // r1 -> set counter ++ 152: ++ mov r2, r0, LSL #30 ++ orr r2, r2, r1, LSL #5 // r2 -> set/way cache-op format ++ mcr p15, 0, r2, c7, c6, 2 // Invalidate line described by r2 ++ add r1, r1, #1 // Increment set counter ++ cmp r1, r3 // Check if the last set is reached... ++ ble 152b // ...if not, continue the set_loop... ++ add r0, r0, #1 // ...else, Increment way counter ++ cmp r0, #4 // Check if the last way is reached... ++ blt 150b // ...if not, continue the way_loop ++ @//Enable dcaches @//D-cache is controlled by bit 2 ++ mrc p15, 0, r0, c1, c0, 0 @//read CP15 register 1 ++ orr r0, r0, #(0x1 <<2) @//enable D Cache ++ mcr p15, 0, r0, c1, c0, 0 @//write CP15 register 1 ++ ++ // Enable Program Flow Prediction ++ // Branch prediction is controlled by the System Control Register: ++ // Set Bit 11 to enable branch prediciton and return stack ++ // Turning on branch prediction requires a general enable ++ // CP15, c1. Control Register ++ // Bit 11 [Z] bit Program flow prediction: ++ // 0 = Program flow prediction disabled ++ // 1 = Program flow prediction enabled. ++ mrc p15, 0, r0, c1, c0, 0 // Read System Control Register ++ orr r0, r0, #(0x1 <<11) ++ mcr p15, 0, r0, c1, c0, 0 // Write System Control Register ++ ++ // Enable D-side prefetch ++ // Bit 2 [DP] Dside prefetch: ++ // 0 = Dside prefetch disabled ++ // 1 = Dside prefetch enabled. ++ mrc p15, 0, r0, c1, c0, 1 // Read Auxiliary Control Register ++ orr r0, r0, #(0x1 <<2) // Enable Dside prefetch ++ mcr p15, 0, r0, c1, c0, 1 // Write Auxiliary Control Register ++ ++ bx lr ++ ++invalidate_v7_cache: .global invalidate_v7_cache ++ ++ mov r0, #0 ++ mcr p15, 0, r0, c8, c7, 0 // Invalidate Inst TLB and Data TLB ++ mcr p15, 0, r0, c7, c5, 0 // Invalidate I Cache ++ ++ // Must iterate over the caches in order to synthesise a complete clean ++ // of data/unified cache ++ mrc p15, 1, r0, c0, c0, 1 // read Cache Level ID register (clidr) ++ ands r3, r0, #0x7000000 // extract level of coherency from clidr ++ mov r3, r3, lsr #23 // left align level of coherency bit field ++ beq 124f // if loc is 0, then no need to clean ++ ++ mov r10, #0 // start clean at cache level 0 (in r10) ++ 92: ++ add r2, r10, r10, lsr #1 // work out 3x current cache level ++ mov r1, r0, lsr r2 // extract cache type bits from clidr ++ and r1, r1, #7 // mask of the bits for current cache only ++ cmp r1, #2 // see what cache we have at this level ++ blt 119f // skip if no cache, or just i-cache ++ mcr p15, 2, r10, c0, c0, 0 // select current cache level in cssr ++ mov r1, #0 ++ mcr p15, 0, r1, c7, c5, 4 // prefetchflush to synch the new cssr&csidr ++ mrc p15, 1, r1, c0, c0, 0 // read the new csidr ++ and r2, r1, #7 // extract the length of the cache lines ++ add r2, r2, #4 // add 4 (line length offset) ++ ldr r6, =0x3ff ++ ands r6, r6, r1, lsr #3 // find maximum number on the way size ++ .WORD 0xE16F5F16 //DCI 0xE16F5F16 @CLZ r5, r6 @ find bit position of way size increment ++ ldr r7, =0x7fff ++ ands r7, r7, r1, lsr #13 // extract max number of the index size ++ 109: ++ mov r8, r6 // create working copy of max way size ++ 111: ++ orr r11, r10, r8, lsl r5 // factor way and cache number into r11 ++ orr r11, r11, r7, lsl r2 // factor index number into r11 ++ mcr p15, 0, r11, c7, c6, 2 // invalidate by set/way ++ subs r8, r8, #1 // decrement the way ++ bge 111b ++ subs r7, r7, #1 // decrement the index ++ bge 109b ++ 119: ++ add r10, r10, #2 // increment cache number ++ cmp r3, r10 ++ bgt 92b ++ ++ 124: ++ ++ // ++ // If Cortex A Class handle secondary cores ++ // ++// mrc p15, 0, r0, c0, c0, 5 ++// and r0, #0x3 ++// cmp r0, #0 ++ ++// bne __secondary_a_core ++ ++ //// back to parent routine ++ bx lr ++ ++ ++invalidate_SCU: .global invalidate_SCU ++ ++ /*set scu enable bit in scu*/ ++ ldr r7, =0x16000000 ++ ldr r0, [r7] ++ orr r0, r0, #0x1 ++ str r0, [r7] ++ ++ /*invalidate scu*/ ++ ldr r7, =0x1600000c ++ ldr r6, =0xffff ++ str r6, [r7] ++ bx lr ++ ++ ++ +diff --git a/arch/arm/mach-sstar/infinity2/miu_bw.c b/arch/arm/mach-sstar/infinity2/miu_bw.c +new file mode 100755 +index 000000000000..d7560bb97893 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/miu_bw.c +@@ -0,0 +1,613 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "infinity3/gpio.h" ++#include "infinity3/registers.h" ++#include "infinity3/mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client{ ++ char* name; ++ short bw_client_id; ++ short bw_enabled; ++ short bw_max; ++ short bw_avg; ++ short effi_avg; ++ short effi_min; ++}; ++ ++static struct miu_client miu0_clients[] = { ++{"OVERALL",0x00,1,0,0}, ++{"CEVAXM6",0x01,0,0,0}, ++{"CEVAXM6",0x02,0,0,0}, ++{"VD_R2",0x03,0,0,0}, ++{"VD_R2_SUBSYS",0x04,0,0,0}, ++{"VD_R2",0x05,0,0,0}, ++{"CEVAXM6",0x06,0,0,0}, ++{"CEVAXM6",0x07,0,0,0}, ++{"audio",0x08,0,0,0}, ++{"audio",0x09,0,0,0}, ++{"audio",0x0A,0,0,0}, ++{"CMDQ",0x0B,0,0,0}, ++{"MCU_IF",0x0C,0,0,0}, ++{"MCU_IF",0x0D,0,0,0}, ++{"MCU_IF",0x0E,0,0,0}, ++{"NA",0x0F,0,0,0}, ++{"SC1(CROP/LD)",0x10,0,0,0}, ++{"ISP_GOP1",0x11,0,0,0}, ++{"CMQ",0x12,0,0,0}, ++{"NOE",0x13,0,0,0}, ++{"USB30",0x14,0,0,0}, ++{"ISP(statics)",0x15,0,0,0}, ++{"ISP(af)",0x16,0,0,0}, ++{"ISP_GOP2",0x17,0,0,0}, ++{"EMAC",0x18,0,0,0}, ++{"ive_top",0x19,0,0,0}, ++{"ISP_GOP3",0x1A,0,0,0}, ++{"MIIC",0x1B,0,0,0}, ++{"MIIC",0x1C,0,0,0}, ++{"MIIC",0x1D,0,0,0}, ++{"SC1(dbg)",0x1E,0,0,0}, ++{"CMDQ",0x1F,0,0,0}, ++{"SDIO30",0x20,0,0,0}, ++{"USB30",0x21,0,0,0}, ++{"USB30",0x22,0,0,0}, ++{"SD30",0x23,0,0,0}, ++{"JPE",0x24,0,0,0}, ++{"JPE",0x25,0,0,0}, ++{"U3DEV",0x26,0,0,0}, ++{"JPD",0x27,0,0,0}, ++{"GMAC",0x28,0,0,0}, ++{"FCIE5",0x29,0,0,0}, ++{"SECGMAC",0x2a,0,0,0}, ++{"USB30",0x2b,0,0,0}, ++{"SATA",0x2c,0,0,0}, ++{"SATA",0x2d,0,0,0}, ++{"USB20",0x2e,0,0,0}, ++{"USB20",0x2f,0,0,0}, ++{"ISP_GOP4",0x30,0,0,0}, ++{"SC1(DNR)",0x31,0,0,0}, ++{"CMDQ",0x32,0,0,0}, ++{"ISP_GOP0",0x33,0,0,0}, ++{"SC1(frame)",0x34,0,0,0}, ++{"SC1(snap)",0x35,0,0,0}, ++{"SC2(frame)",0x36,0,0,0}, ++{"CMDQ",0x37,0,0,0}, ++{"MFE",0x38,0,0,0}, ++{"MFE",0x39,0,0,0}, ++{"SC3(frame)",0x3a,0,0,0}, ++{"NA",0x3b,0,0,0}, ++{"NA",0x3c,0,0,0}, ++{"MFE",0x3d,0,0,0}, ++{"MFE",0x3e,0,0,0}, ++{"ISP(mload)",0x3f,0,0,0}, ++{"VE",0x40,0,0,0}, ++{"EVD",0x41,0,0,0}, ++{"MGWIN",0x42,0,0,0}, ++{"MGWIN",0x43,0,0,0}, ++{"HVD",0x44,0,0,0}, ++{"HVD",0x45,0,0,0}, ++{"DDI_0",0x46,0,0,0}, ++{"EVD",0x47,0,0,0}, ++{"MFDEC",0x48,0,0,0}, ++{"ISPSC_DMAG",0x49,0,0,0}, ++{"EVD",0x4a,0,0,0}, ++{"HVD",0x4b,0,0,0}, ++{"SC1_IPM",0x4c,0,0,0}, ++{"SC1_OPM",0x4d,0,0,0}, ++{"MFDEC",0x4e,0,0,0}, ++{"LDC_FEYE",0x4f,0,0,0}, ++{"GOP",0x50,0,0,0}, ++{"GOP",0x51,0,0,0}, ++{"AUTO_DL",0x52,0,0,0}, ++{"DIP",0x53,0,0,0}, ++{"MVOP",0x54,0,0,0}, ++{"MVOP",0x55,0,0,0}, ++{"IPM",0x56,0,0,0}, ++{"IPS",0x57,0,0,0}, ++{"OPM",0x58,0,0,0}, ++{"MDWIN",0x59,0,0,0}, ++{"MFDEC",0x5a,0,0,0}, ++{"MFDEC",0x5b,0,0,0}, ++{"MDWIN",0x5c,0,0,0}, ++{"SYN_SCL",0x5d,0,0,0}, ++{"VE",0x5e,0,0,0}, ++{"GE",0x5f,0,0,0}, ++{"ISP(RAW)",0x60,0,0,0}, ++{"ISP(RAW)",0x61,0,0,0}, ++{"ISP(RAW)",0x62,0,0,0}, ++{"ISP(RAW)",0x63,0,0,0}, ++{"ISP(RAW)",0x64,0,0,0}, ++{"ISP(RAW)",0x65,0,0,0}, ++{"ISP(RAW)",0x66,0,0,0}, ++{"ISP(RAW)",0x67,0,0,0}, ++{"ISP(RAW)",0x68,0,0,0}, ++{"DMA_GNRL",0x69,0,0,0}, ++{"SC1(DNR)",0x6a,0,0,0}, ++{"NA",0x6b,0,0,0}, ++{"MHE",0x6c,0,0,0}, ++{"MHE",0x6d,0,0,0}, ++{"MHE",0x6e,0,0,0}, ++{"MHE",0x6f,0,0,0}, ++{"CPU",0x70,0,0,0}, ++}; ++ ++ ++static struct miu_device miu0; ++ ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++//static struct task_struct *pBWmonitorThread=NULL; ++//struct mutex bw_monitor_mutex; ++ ++int gmonitor_interval = 14; ++int gmonitor_duration = 1800; ++int gmonitor_output_kmsg = 1; ++ ++ ++ ++/* ++int BW_measure(short bwclientid) ++{ ++ short BW_val=0; ++ mutex_lock(&bw_monitor_mutex); ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x50)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ mdelay(300); ++ BW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ ++ mutex_unlock(&bw_monitor_mutex); ++ ++ return BW_val; ++} ++ ++static int BW_monitor(void *arg) ++{ ++ int i=0; ++ short tempBW_val=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ ++ if(miu0_clients[i].bw_enabled) ++ { ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x50)) ;//reset ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ //mdelay(300); ++ //tempBW_val=0; ++ //tempBW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ tempBW_val=BW_measure(miu0_clients[i].bw_client_id); ++ ++ if(miu0_clients[i].bw_val_thread= (sizeof(miu0_clients)/sizeof(miu0_clients[0])) ) return -EINVAL; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ miu0_clients[idx].bw_enabled=enabled; ++ } ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if(!strncmp(buf, "all",strlen("all"))) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_enabled=1; ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev,opt,n,1); ++ } ++ kfree(pt); ++ return n; ++} ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if(!strncmp(buf, "all",strlen("all"))) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_enabled=0; ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev,opt,n,0); ++ } ++ kfree(pt); ++ return n; ++ ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ str += scnprintf(str, end - str, "%3d:%-*s[0x%02X][%d]\n",(short)i, 12, miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%-*s[0x%02X][%d]\n",(short)i,12,miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_interval = input; ++ return count; ++} ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gmonitor_interval); ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_duration = input; ++ return count; ++} ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gmonitor_duration); ++} ++ ++ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_output_kmsg = input; ++ return count; ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ int id; ++ short temp_val=0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_29),0) ; ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].effi_min=0x3ff; ++ miu0_clients[i].effi_avg=0; ++ miu0_clients[i].bw_avg=0; ++ miu0_clients[i].bw_max=0; ++ } ++ if(gmonitor_output_kmsg) ++ { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "\nNum:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ id = miu0_clients[i].bw_client_id; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_15),(id&0x40)? 0x80:0x00); ++ id = id &0x3f; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((id << 8) & 0xFF00) | 0x30)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((id << 8) & 0xFF00) | 0x35)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ msleep(gmonitor_interval); ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].effi_min>temp_val) ++ { ++ miu0_clients[i].effi_min=temp_val; ++ } ++ temp_loop_time++; ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ miu0_clients[i].effi_avg=total_temp/temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time=0; ++ id = miu0_clients[i].bw_client_id; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_15),(id&0x40)? 0x80:0x00); ++ id = id &0x3f; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((id << 8) & 0xFF00) | 0x40)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((id << 8) & 0xFF00) | 0x41)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ msleep(gmonitor_interval); //mdelay(gmonitor_interval); ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].bw_max buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++/* ++static int set_bw_thread_enable(struct device *dev, const char *buf, size_t n) ++{ ++ long idx=-1; ++ int i=0; ++ int ret; ++ ++ if (kstrtol(buf, 10, &idx) != 0 || idx<0 || idx >= 2 ) return -EINVAL; ++ ++ if(idx==1)//enable thread ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) //reset all bandwidth value ++ { ++ miu0_clients[i].bw_val_thread=0; ++ } ++ ++ if(pBWmonitorThread==NULL) ++ { ++ pBWmonitorThread = kthread_create(BW_monitor,(void *)&pBWmonitorThread,"BW Monitor"); ++ if (IS_ERR(pBWmonitorThread)) ++ { ++ ret = PTR_ERR(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ return ret; ++ } ++ wake_up_process(pBWmonitorThread); ++ } ++ } ++ else if (idx==0 && (pBWmonitorThread!=NULL))//disable thread ++ { ++ kthread_stop(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ } ++ return n; ++} ++ ++ ++static ssize_t bw_thread_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return set_bw_thread_enable(dev,buf,n); ++} ++ ++ ++static ssize_t bw_thread_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ //read from bw register and saved back to bw_val ++ str += scnprintf(str, end - str, "%2d:%s[0x%04X] BW_val_thread=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id,miu0_clients[i].bw_val_thread,miu0_clients[i].bw_val_thread*100/1024, ++ (miu0_clients[i].bw_val_thread*10000/1024)%100); ++ ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++DEVICE_ATTR(bw_thread, 0644, bw_thread_show, bw_thread_store); ++*/ ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++//DEVICE_ATTR(measure_max_bandwidth, 0444, measure_bandwidth_MAX_show, NULL); ++//DEVICE_ATTR(measure_avg_bandwidth, 0444, measure_bandwidth_AVG_show, NULL); ++//DEVICE_ATTR(measure_avg_efficiency, 0444, measure_efficiency_AVG_show, NULL); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++ ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret; ++ ++ miu0.index=0; ++ miu0.dev.kobj.name="miu0"; ++ miu0.dev.bus=&miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ++ ret=device_register(&miu0.dev); ++ ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_disable); ++ //device_create_file(&miu0.dev, &dev_attr_bw_thread); ++ ++ //device_create_file(&miu0.dev, &dev_attr_measure_max_bandwidth); ++ //device_create_file(&miu0.dev, &dev_attr_measure_avg_bandwidth); ++ //device_create_file(&miu0.dev, &dev_attr_measure_avg_efficiency); ++ device_create_file(&miu0.dev, &dev_attr_measure_all); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_duration_ms); ++ ++ //mutex_init(&bw_monitor_mutex); ++} +diff --git a/arch/arm/mach-sstar/infinity2/pm.c b/arch/arm/mach-sstar/infinity2/pm.c +new file mode 100755 +index 000000000000..8de83b750914 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/pm.c +@@ -0,0 +1,69 @@ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++#ifdef CONFIG_PM ++extern void infinity_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&infinity_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++#endif ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++#ifdef CONFIG_PM ++ .enter = mstar_suspend_enter, ++#endif ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++#ifdef CONFIG_PM ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++#endif ++ ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity2/reset.S b/arch/arm/mach-sstar/infinity2/reset.S +new file mode 100755 +index 000000000000..09edd2494fd6 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/reset.S +@@ -0,0 +1,21 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++ ++ .align 5 ++.globl cedric_reset_cpu ++cedric_reset_cpu: ++ ++ mov r3, #0x0000 ++ ldr r1, =0xFD005C80 ++ str r3, [r1] ++ mov r3, #0x0079 ++ ldr r1, =0xFD005CB8 ++ str r3, [r1] ++ nop ++ nop ++ nop ++ nop ++ ++_loop_forever: ++ b _loop_forever +diff --git a/arch/arm/mach-sstar/infinity2/smp_head.S b/arch/arm/mach-sstar/infinity2/smp_head.S +new file mode 100755 +index 000000000000..3f2a00a3ff00 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/smp_head.S +@@ -0,0 +1,52 @@ ++/* ++* smp_head.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++ ++/* __CPUINIT*/ ++ ++/* ++ * Realview/Versatile Express specific entry point for secondary CPUs. ++ * This provides a "holding pen" into which all secondary cores are held ++ * until we're ready for them to initialise. ++ */ ++ENTRY(infinity2_secondary_startup) ++ /* hard code --be carefully here */ ++ bl v7_invalidate_l1 ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ /* ++ * we've been released from the holding pen: secondary_stack ++ * should now contain the SVC stack for this core ++ */ ++ b secondary_startup ++ ++ ++ .align 2 ++1: .long . ++ .long pen_release ++ENDPROC(infinity2_secondary_startup) +diff --git a/arch/arm/mach-sstar/infinity2/smp_platform.c b/arch/arm/mach-sstar/infinity2/smp_platform.c +new file mode 100755 +index 000000000000..5e17830f1f9a +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/smp_platform.c +@@ -0,0 +1,370 @@ ++/* ++* smp_platform.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++ ++extern int infinity2_platform_cpu_kill(unsigned int cpu); ++extern void infinity2_platform_cpu_die(unsigned int cpu); ++extern int infinity2_platform_cpu_disable(unsigned int cpu); ++ ++//extern volatile int __cpuinitdata pen_release; ++extern volatile int pen_release; ++extern void Chip_Flush_CacheAll(void); ++ ++//#define SCU_PHYS 0x16000000 /*Cedric*/ ++#define SCU_PHYS 0x16000000 /*MACAN*/ // SCU PA = 0x16004000 ++ ++ ++ ++static inline void cpu_enter_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk("ms_hotplug.c cpu_enter_lowpower: in\n"); ++ ++ flush_cache_all(); ++ asm volatile( ++ " mcr p15, 0, %1, c7, c5, 0\n" ++ " mcr p15, 0, %1, c7, c10, 4\n" ++ /* ++ * Turn off coherency ++ */ ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " bic %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ " mrc p15, 0, %0, c1, c0, 0\n" ++ " bic %0, %0, %2\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ : "=&r" (v) ++ : "r" (0), "Ir" (CR_C) ++ : "cc"); ++ ++ printk("ms_hotplug.c cpu_enter_lowpower: out\n"); ++} ++ ++static inline void cpu_leave_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk("ms_hotplug.c cpu_leave_lowpower: in\n"); ++ ++ asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" ++ " orr %0, %0, %1\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " orr %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ : "=&r" (v) ++ : "Ir" (CR_C) ++ : "cc"); ++ ++ printk("ms_hotplug.c cpu_leave_lowpower: out\n"); ++} ++ ++static inline void platform_do_lowpower(unsigned int cpu, int *spurious) ++{ ++ //printk("ms_hotplug.c platform_do_lowpower: before %d cpu go into WFI, spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * there is no power-control hardware on this platform, so all ++ * we can do is put the core into WFI; this is safe as the calling ++ * code will have already disabled interrupts ++ */ ++ for (;;) { ++ /* ++ * here's the WFI ++ */ ++ asm(".word 0xe320f003\n" ++ : ++ : ++ : "memory", "cc"); ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up, spurious =%d \n", cpu, *spurious); ++ ++ if (pen_release == cpu_logical_map(cpu)) { ++ /* ++ * OK, proper wakeup, we're done ++ */ ++ break; ++ } ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up error(cpuID != pen_release), spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * Getting here, means that we have come out of WFI without ++ * having been woken up - this shouldn't happen ++ * ++ * Just note it happening - when we're woken, we can report ++ * its occurrence. ++ */ ++ (*spurious)++; ++ } ++} ++ ++int infinity2_platform_cpu_kill(unsigned int cpu) ++{ ++ return 1; ++} ++ ++/* ++ * platform-specific code to shutdown a CPU ++ * ++ * Called with IRQs disabled ++ */ ++void __ref infinity2_platform_cpu_die(unsigned int cpu) ++{ ++ int spurious = 0; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ ++ //printk("ms_hotplug.c platform_cpu_die: in cpu = %d \n", cpu); ++ ++ Chip_Flush_CacheAll(); ++ ++ /* ++ * we're ready for shutdown now, so do it ++ */ ++ //cpu_enter_lowpower(); ++ platform_do_lowpower(cpu, &spurious); ++ ++ /* ++ * bring this CPU back into the world of cache ++ * coherency, and then restore interrupts ++ */ ++ //cpu_leave_lowpower(); ++ ++ printk("ms_hotplug.c platform_cpu_die: out cpu = %d \n", cpu); ++ ++ if (spurious) ++ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); ++} ++ ++int infinity2_platform_cpu_disable(unsigned int cpu) ++{ ++ /* ++ * we don't allow CPU 0 to be shutdown (it is still too special ++ * e.g. clock tick interrupts) ++ */ ++ ++ printk("ms_hotplug.c platform_cpu_disable: in cpu = %d \n", cpu); ++ return cpu == 0 ? -EPERM : 0; ++} ++ ++ ++/* ++ * control for which core is the next to come out of the secondary ++ * boot "holding pen" ++ */ ++//volatile int __cpuinitdata pen_release = -1; ++ ++static void __iomem *scu_base_addr(void) ++{ ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ return (void __iomem *)(IO_ADDRESS(SCU_PHYS)); ++} ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++static void write_pen_release(int val) ++{ ++ pen_release = val; ++ smp_wmb(); ++ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); ++ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); ++} ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++void infinity2_secondary_init(unsigned int cpu) ++{ ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ ++ /* ++ * if any interrupts are already enabled for the primary ++ * core (e.g. timer irq), then they will not have been enabled ++ * for us: do so ++ */ ++ //gic_secondary_init(0); ++ ++ /* ++ * let the primary processor know we're out of the ++ * pen, then head off into the C entry point ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++#define SECOND_START_ADDR_HI 0x1F203A4C ++#define SECOND_START_ADDR_LO 0x1F203A50 ++#define SECOND_MAGIC_NUMBER_ADDR 0x1F203A58 ++ ++int infinity2_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ ++ unsigned long timeout; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ /* ++ * Set synchronisation state between this boot processor ++ * and the secondary one ++ */ ++ spin_lock(&boot_lock); ++ ++ /* ++ * This is really belt and braces; we hold unintended secondary ++ * CPUs in the holding pen until we're ready for them. However, ++ * since we haven't sent them a soft interrupt, they shouldn't ++ * be there. ++ */ ++ write_pen_release(cpu_logical_map(cpu)); ++ ++ do{ ++ OUTREG16(SECOND_MAGIC_NUMBER_ADDR, 0xBABE); ++ }while(INREG16(SECOND_MAGIC_NUMBER_ADDR)!=0xBABE); ++ /* ++ * Send the secondary CPU a soft interrupt, thereby causing ++ * the boot monitor to read the system wide flags register, ++ * and branch to the address found there. ++ */ ++ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ /* ++ * now the secondary core is starting up let it run its ++ * calibrations, then wait for it to finish ++ */ ++ spin_unlock(&boot_lock); ++ ++ return pen_release != -1 ? -ENOSYS : 0; ++} ++ ++ ++#include ++#include ++ ++extern void infinity2_secondary_startup(void); ++ ++#define SCU_CTRL 0x00 ++ ++void __init infinity2_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ int i; ++// u32 scu_ctrl; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ /* ++ * Initialise the present map, which describes the set of CPUs ++ * actually populated at the present time. ++ */ ++ for (i = 0; i < max_cpus; i++) ++ { ++ set_cpu_present(i, true); ++ } ++ ++#if defined(CONFIG_CEDRIC_MASTER0_ONLY_PATCH) ++ __raw_writel(0xe0000000, scu_base_addr() + 0x40); ++ __raw_writel(0xe0100000, scu_base_addr() + 0x44); ++ scu_ctrl = __raw_readl(scu_base_addr() + SCU_CTRL); ++ scu_ctrl |= 0x02; ++ __raw_writel(scu_ctrl, scu_base_addr() + SCU_CTRL); ++ printk(KERN_WARNING"SCU: Filter to Master0 only\n"); ++#endif ++ ++ scu_enable(scu_base_addr()); // SCU PA = 0x16000000 ++ ++// printk("[306]!! scu_enable\n"); ++ ++ /* ++ * Write the address of secondary startup into the ++ * system-wide flags register. The boot monitor waits ++ * until it receives a soft interrupt, and then the ++ * secondary CPU branches to this address. ++ */ ++ do{ ++ OUTREG16(SECOND_START_ADDR_LO,(virt_to_phys(infinity2_secondary_startup) & 0xFFFF)); ++ }while(INREG16(SECOND_START_ADDR_LO)!=(virt_to_phys(infinity2_secondary_startup) & 0xFFFF)); ++ ++ do{ ++ OUTREG16(SECOND_START_ADDR_HI,(virt_to_phys(infinity2_secondary_startup)>>16)); ++ }while(INREG16(SECOND_START_ADDR_HI)!=(virt_to_phys(infinity2_secondary_startup)>>16)); ++ ++ __cpuc_flush_kern_all(); ++} ++ ++void __init infinity2_smp_init_cpus(void) ++{ ++ ++ void __iomem *scu_base =scu_base_addr(); ++ unsigned int i, ncores; ++// printk("[%s]\n",__FUNCTION__); ++ ncores = scu_base ? scu_get_core_count(scu_base) : 1; ++ ++ for (i = 0; i < 2; i++) ++ { ++ set_cpu_possible(i, true); ++ } ++} ++ ++ ++struct smp_operations __initdata infinity2_smp_ops = { ++ .smp_init_cpus = infinity2_smp_init_cpus, ++ .smp_prepare_cpus = infinity2_smp_prepare_cpus, ++ .smp_secondary_init = infinity2_secondary_init, ++ .smp_boot_secondary = infinity2_boot_secondary, ++ ++#ifdef CONFIG_HOTPLUG_CPU ++ .cpu_kill = infinity2_platform_cpu_kill, ++ .cpu_die = infinity2_platform_cpu_die, ++ .cpu_disable = infinity2_platform_cpu_disable, ++#endif ++}; ++ +diff --git a/arch/arm/mach-sstar/infinity2/soc.c b/arch/arm/mach-sstar/infinity2/soc.c +new file mode 100755 +index 000000000000..aa25d426b560 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/soc.c +@@ -0,0 +1,793 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "infinity2/gpio.h" ++#include "infinity2/registers.h" ++#include "infinity2/mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++ ++#define L2_LINEFILL 1 ++#define L2_PREFETCH 1 ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {CEVA_VIRT, __phys_to_pfn(CEVA_PHYS), CEVA_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++#ifdef CONFIG_MS_DUAL_OS_SUPPORT ++ {IPC_MEM_VIRT, __phys_to_pfn(IPC_MEM_PHYS), IPC_MEM_SIZE, MT_MEMORY_RW}, ++#endif ++}; ++ ++void __iomem * l2x0_base = (void __iomem *)(L2_CACHE_ADDRESS(L2_CACHE_PHYS)); ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "sstar,infinity2", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++//#define PLATFORM_NAME PLATFORM_NAME_INFINITY2 ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init ms_irq_of_init(void); ++//extern void infinity_restart(enum reboot_mode mode, const char *cmd); ++//extern struct timecounter *arch_timer_get_timecounter(void); ++extern void chip_init_timer(void ); ++ ++//static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++//static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ //unsigned long dwLockFlag = 0; ++ volatile unsigned short dwReadData = 0; ++ static atomic_t bRetryCount = ATOMIC_INIT(0); ++ volatile int s32RetryCount; ++ ++ s32RetryCount = atomic_inc_return(&bRetryCount); ++ ++ //spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ while(1) ++ { ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD203114) &= ~(0x0001); //Write 0x1018_45[0] = 0, flush fire disable ++ *(volatile unsigned short *)(0xFD203114) |= 0x0001; // Write 0x1018_45[0] = 1, flush fire trigger ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xfd203140);//Read 0x1018_50[12] = 1, flush all finish ++ dwReadData &= (BIT12); //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ *(volatile unsigned short *)(0xFD203114) &= ~(0x0001);//Write 0x1018_45[0] = 0, flush fire disable ++ ++ //spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ if (s32RetryCount > 1) ++ { ++ //we are the next flush and one or more previous flush is on processing simultaneously ++ //there exists risk that my data my not be flushed out so we need to try again ++ s32RetryCount =0; ++ continue; ++ } ++ break; ++ } ++ atomic_dec (&bRetryCount); ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ wmb();//#define wmb() do { dsb(st); outer_sync(); } while (0) ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++static int mstar_outer_cache_is_enable(void) ++{ ++ ++ return (readl_relaxed(l2x0_base + L2X0_CTRL) & 1); ++} ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++ ++//#define STORAGE_USB 0 // ++//#define STORAGE_SPI_NAND 1 //BIT0 ++//#define STORAGE_SPI_NOR 2 //BIT1 ++//#define STORAGE_SD_3 3 //BIT1|BIT0 ++//#define STORAGE_EMMC 4 //BIT2 ++//#define STORAGE_P_NAND 5 //BIT2|BIT0 ++//#define SBUS 6 //BIT2|BIT1 ++//#define DBUS 7 //BIT2|BIT1|BIT0 ++//#define UART_UPGRADE 0 // ++ ++ U8 type = (INREG16((BASE_REG_CHIPTOP_PA + 0x65*4))) & 0x0F; ++ ++ if(5 == type) ++ return (int)MS_STORAGE_NAND; ++ else if(2 == type) ++ return (int)MS_STORAGE_NOR; ++ else if(4 == type) ++ return (int)MS_STORAGE_EMMC; ++ else if(1 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++ ++ ++} ++ ++static int mstar_get_package_type(void) ++{ ++ ++ if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC005A-S01A")) ++ return MS_I2_PACKAGE_BGA_1GB; ++// else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S02A-256M") || !strcmp(&mstar_soc_dev_attr.machine[10], "MSC250C")) ++// return MS_I3_PACKAGE_DDR3_1866_256MB; ++// else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S04A")) ++// return MS_I3_PACKAGE_QFN_DDR3_128MB; ++// else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S03A-64M")) ++// return MS_I3_PACKAGE_QFN_DDR2_64MB; ++// else if(!strcmp(&mstar_soc_dev_attr.machine[10], "FPGA")) ++// return MS_I3_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I2_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]="I2"; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ int power_en_voltage, power_dis_voltage; ++ ++ struct device_node *np; ++ int pin_data, voltage_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>2)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Mstar-ehci-1"); ++ } ++ else if(1 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Mstar-ehci-2"); ++ } ++ else if(2 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Mstar-ehci-3"); ++ } ++ else if(3 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Mstar-ehci-4"); ++ } ++ else ++ { ++ printk(KERN_ERR "[%s] port_num invalid:%d \n", __FUNCTION__, port_num); ++ return -EINVAL; ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ power_en_gpio = PAD_GPIO0; ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", power_en_gpio); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-voltage", &voltage_data)) ++ { ++ printk(KERN_ERR "Get power-enable-voltage from DTS voltage(%d)\n", voltage_data); ++ power_en_voltage = (unsigned char)voltage_data; ++ } ++ else ++ { ++ power_en_voltage = 1; ++ printk(KERN_ERR "Can't get power-enable-voltage from DTS, set default voltage(%d)\n", power_en_voltage); ++ } ++ ++ power_dis_voltage = power_en_voltage?0:1; ++ ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, power_dis_voltage); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, power_en_voltage); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++ ++//extern u32 arch_timer_get_rate(void); ++//static cycle_t us_ticks_cycle_offset=0; ++//static u64 us_ticks_factor=1; ++/* ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ const struct cyclecounter *arch_cc=arch_timer_get_timecounter()->cc; ++ u64 cycles=(arch_cc->read(arch_cc)-us_ticks_cycle_offset); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ const struct cyclecounter *arch_cc=arch_timer_get_timecounter()->cc; ++ us_ticks_cycle_offset=arch_cc->read(arch_cc); ++} ++*/ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++// case CHIP_FUNC_MCM_DISABLE_ID: ++// mcm_rw(param, 0, 1); ++// break; ++// case CHIP_FUNC_MCM_ENABLE_ID: ++// mcm_rw(param, 15, 1); ++// break; ++ default: ++ printk(KERN_ERR "Unsupport CHIP_FUNCTION!! ID=%d\n",function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++// static void __iomem * l2x0_base = (void __iomem *)(IO_ADDRESS(L2_CACHE_PHYS)); ++ ++ ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD203114) = 0x10;/*TBD@@@@*/ ++ ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsb ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->cache_outer_is_enabled=mstar_outer_cache_is_enable; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ // chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++ ++} ++extern struct outer_cache_fns outer_cache; ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++#ifdef CONFIG_CACHE_L2X0 ++ int val = 0; ++#endif ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ // mstar_reset_us_ticks_cycle_offset(); ++// us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++//#ifdef CONFIG_MS_L2X0_PATCH ++// outer_cache.flush_MIU_pipe=&mstar_chip_flush_miu_pipe; ++//#endif ++ ++#ifdef CONFIG_CACHE_L2X0 ++ { ++ //void __iomem * l2x0_base = (void __iomem *)(IO_ADDRESS(L2_CACHE_PHYS)); ++#if L2_LINEFILL ++ val = L2_CACHE_read( L2_CACHE_PHYS + PREFETCH_CTL_REG ); ++ L2_CACHE_write(( val | DOUBLE_LINEFILL_ENABLE | LINEFILL_WRAP_DISABLE ), L2_CACHE_PHYS + PREFETCH_CTL_REG); ++#endif ++ ++#if L2_PREFETCH ++ val = L2_CACHE_read( L2_CACHE_PHYS + PREFETCH_CTL_REG ); ++ L2_CACHE_write(( val | I_PREFETCH_ENABLE | D_PREFETCH_ENABLE | PREFETCH_OFFSET ), L2_CACHE_PHYS + PREFETCH_CTL_REG ); ++#endif ++ ++ /* set RAM latencies to 1 cycle for this core tile. */ ++ writel(0x121, l2x0_base + L310_TAG_LATENCY_CTRL); ++ writel(0x121, l2x0_base + L310_DATA_LATENCY_CTRL); ++ /* BOX_Macan*/ ++ /* latency settings are given by hardware designer */ ++ /*writel(0x121, l2x0_base + L2X0_TAG_LATENCY_CTRL); ++ writel(0x121, l2x0_base + L2X0_DATA_LATENCY_CTRL); ++ */ ++ #ifdef CONFIG_MP_ACP_L2 ++ l2x0_init(l2x0_base, 0x00000000, 0xfe0fffff); ++ #else ++ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); ++ #endif ++ } ++#endif ++ *(volatile unsigned short *)(0xfd200200) = 0x1 ; ++ *(volatile unsigned short *)(0xfd200250) = 0xFFFF ; ++ *(volatile unsigned short *)(0xfd200254) = 0xFFFF ; ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++//struct mcm_client{ ++// char* name; ++// short index; ++// short slow_down_ratio; ++//}; ++ ++#if 0 ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, 0}, ++ {"VHE", MCM_ID_VHE, 0}, ++ {"MFE", MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, 0}, ++ {"AESDMA", MCM_ID_AESDMA, 0}, ++ {"UHC", MCM_ID_UHC, 0}, ++ {"EMAC", MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, 0}, ++ {"GOP", MCM_ID_GOP, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, 0}, ++ {"*ALL_CLIENTS*", MCM_ID_ALL, 0} //use carefully ++}; ++ ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ return 0; ++ } ++ else if(index == MCM_ID_MCU51) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x0; ++ else if (index == MCM_ID_URDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x1; ++ else if (index == MCM_ID_BDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x4; ++ else if (index == MCM_ID_VHE) ++ addr = BASE_REG_MCM_VHE_GP_PA + 0x0; ++ else if (index == MCM_ID_MFE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x0; ++ else if (index == MCM_ID_JPE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1; ++ else if (index == MCM_ID_BACH) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x4; ++ else if (index == MCM_ID_AESDMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x5; ++ else if (index == MCM_ID_UHC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x8; ++ else if (index == MCM_ID_EMAC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x9; ++ else if (index == MCM_ID_CMDQ) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xC; ++ else if (index == MCM_ID_ISP_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xD; ++ else if (index == MCM_ID_ISP_DMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x10; ++ else if (index == MCM_ID_GOP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x11; ++ else if (index == MCM_ID_SC_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x14; ++ else if (index == MCM_ID_SC_DNR_SAD) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x15; ++ else if (index == MCM_ID_SC_CROP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x18; ++ else if (index == MCM_ID_SC1_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x19; ++ else if (index == MCM_ID_SC1_SNP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1C; ++ else if (index == MCM_ID_SC1_DBG) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1D; ++ else if (index == MCM_ID_SC2_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x20; ++ else if (index == MCM_ID_SC3_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x21; ++ else if (index == MCM_ID_FCIE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x24; ++ else if (index == MCM_ID_SDIO) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x25; ++ else if (index == MCM_ID_SC1_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x28; ++ else if (index == MCM_ID_SC2_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x29; ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++#endif ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++ mstar_pm_init(); ++ mstar_create_MIU_node(); ++// mstar_create_MCM_node(); ++} ++ ++static void infinity_restart(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++ ++ ++#ifdef CONFIG_SMP ++extern struct smp_operations infinity2_smp_ops; ++#endif ++ ++EXPORT_SYMBOL(walk_page_range); ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = ms_irq_of_init, ++ .init_late = mstar_init_late, ++ .restart = infinity_restart, //in reset.S ++#ifdef CONFIG_SMP ++ .smp = smp_ops(infinity2_smp_ops), ++#endif ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity2/sram.S b/arch/arm/mach-sstar/infinity2/sram.S +new file mode 100755 +index 000000000000..6014d6de889f +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2/sram.S +@@ -0,0 +1,174 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl infinity_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(infinity_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(infinity_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity2m/Kconfig b/arch/arm/mach-sstar/infinity2m/Kconfig +new file mode 100755 +index 000000000000..80fc85adffe7 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/Kconfig +@@ -0,0 +1,100 @@ ++config ARCH_INFINITY2M ++ bool "SoC iNfinity2m (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity2m SoC ++ ++config INFINITY2M_FPGA ++ bool "iNfinity2m FPGA environment" if ARCH_INFINITY2M ++ depends on ARCH_INFINITY2M ++ help ++ Support for iNfinity2m FPGA environment ++ ++#config ANALOG_PD_XINDIGPLL ++# bool "Power down xindigpll at boot" ++# help ++# Turn off xindigpll at kerenl boot procedure ++ ++#config ANALOG_PD_ARMPLL ++# bool "Power down armpll at boot" ++# help ++# Turn off armpll at kerenl boot procedure ++ ++config ANALOG_PD_AUDIO ++ bool "Power down audio at boot" ++ help ++ Turn off AUDIO at kerenl boot procedure ++ ++config ANALOG_PD_EMAC ++ bool "Power down EMAC at boot" ++ help ++ Turn off EMAC at kerenl boot procedure ++ ++config ANALOG_PD_HDMI_ATOP ++ bool "Power down HDMI_ATOP at boot" ++ help ++ Turn off HDMI_ATOP at kerenl boot procedure ++ ++config ANALOG_PD_IDAC_ATOP ++ bool "Power down IDAC_ATOP at boot" ++ help ++ Turn off IDAC_ATOP at kerenl boot procedure ++ ++config ANALOG_PD_IDAC_LPLL ++ bool "Power down IDAC_LPLL at boot" ++ help ++ Turn off IDAC_LPLL at kerenl boot procedure ++ ++config ANALOG_PD_DISP_LPLL ++ bool "Power down DISP_LPLL at boot" ++ help ++ Turn off DISP_LPLL at kerenl boot procedure ++ ++config ANALOG_PD_MIPI_DPHY_TX_TOP ++ bool "Power down MIPI_DPHY_TX_TOP at boot" ++ help ++ Turn off MIPI_DPHY_TX_TOP at kerenl boot procedure ++ ++#config ANALOG_PD_MPLL ++# bool "Power down MPLL at boot" ++# help ++# Turn off MPLL at kerenl boot procedure ++ ++config ANALOG_PD_SATA_ATOP ++ bool "Power down SATA_ATOP at boot" ++ help ++ Turn off SATA_ATOP at kerenl boot procedure ++ ++config ANALOG_PD_UPLL_0 ++ bool "Power down UPLL_0 at boot" ++ help ++ Turn off UPLL_0 at kerenl boot procedure ++ ++config ANALOG_PD_UPLL_1 ++ bool "Power down UPLL_1 at boot" ++ help ++ Turn off UPLL_1 at kerenl boot procedure ++ ++config ANALOG_PD_USB20_P1 ++ bool "Power down USB20_P1 at boot" ++ help ++ Turn off USB20_P1 at kerenl boot procedure ++ ++config ANALOG_PD_USB20_P2 ++ bool "Power down USB20_P2 at boot" ++ help ++ Turn off USB20_P2 at kerenl boot procedure ++ ++config ANALOG_PD_USB20_P3 ++ bool "Power down USB20_P3 at boot" ++ help ++ Turn off USB20_P3 at kerenl boot procedure ++ ++config SS_PROFILING_TIME ++ bool "Record timestamp in sram" ++ default n +diff --git a/arch/arm/mach-sstar/infinity2m/Makefile b/arch/arm/mach-sstar/infinity2m/Makefile +new file mode 100755 +index 000000000000..a7e8e6b2b2e3 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/Makefile +@@ -0,0 +1,9 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += soc.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o ++obj-$(CONFIG_SMP) += smp_platform.o smp_head.o +diff --git a/arch/arm/mach-sstar/infinity2m/miu_bw.c b/arch/arm/mach-sstar/infinity2m/miu_bw.c +new file mode 100755 +index 000000000000..177fa1798893 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/miu_bw.c +@@ -0,0 +1,1356 @@ ++/* ++* miu_bw.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++#ifndef MIU_NUM ++#define MIU_NUM (1) ++#endif ++ ++#define MIU0_CLIENT_NUM sizeof(miu0_clients)/sizeof(miu0_clients[0]) ++#define MIU1_CLIENT_NUM sizeof(miu1_clients)/sizeof(miu1_clients[0]) ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client { ++ char* name; ++ short bw_client_id; ++ short bw_rsvd; ++ short bw_enabled; ++ short bw_dump_en; ++ short bw_filter_en; ++ short bw_max; ++ short bw_avg; ++ short bw_min; ++ short effi_avg; ++ short effi_min; ++ short effi_max; ++ short bw_max_div_effi; ++ short bw_avg_div_effi; ++}; ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_client miu0_clients[] = ++{ ++ {"OVERALL ",0x00,0,1,0,0}, ++ {"MIIC0 ",0x01,0,0,0,0}, ++ {"MIIC1 ",0x02,0,0,0,0}, ++ {"JPE_R ",0x04,0,0,0,0}, ++ {"JPE_W ",0x05,0,0,0,0}, ++ {"BACH_RW ",0x06,0,0,0,0}, ++ {"AESDMA_RW ",0x07,0,0,0,0}, ++ {"MCU51_RW ",0x0A,0,0,0,0}, ++ {"URDMA_RW ",0x0B,0,0,0,0}, ++ {"BDMA_RW ",0x0C,0,0,0,0}, ++ {"MOVDMA0_RW",0x0D,0,0,0,0}, ++ {"CMDQ_R ",0x10,0,0,0,0}, ++ {"SATA ",0x11,0,0,0,0}, ++ {"EMAC ",0x12,0,0,0,0}, ++ {"EMAC1 ",0x13,0,0,0,0}, ++ {"USB20_1 ",0x17,0,0,0,0}, ++ {"USE20_2 ",0x18,0,0,0,0}, ++ {"USB20_3 ",0x19,0,0,0,0}, ++ {"GE ",0x1A,0,0,0,0}, ++ {"SDIO30_RW ",0x1F,0,0,0,0}, ++ {"DIP0_R ",0x20,0,0,0,0}, ++ {"DIP0_W ",0x21,0,0,0,0}, ++ {"GOP0 ",0x22,0,0,0,0}, ++ {"GOP1 ",0x23,0,0,0,0}, ++ {"MOPROT0_Y ",0x24,0,0,0,0}, ++ {"MOPROT0_C ",0x25,0,0,0,0}, ++ {"MOPROT1_Y ",0x26,0,0,0,0}, ++ {"MOPROT1_C ",0x27,0,0,0,0}, ++ {"MOPS_Y ",0x28,0,0,0,0}, ++ {"MOPS_C ",0x29,0,0,0,0}, ++ {"MOPG_Y ",0x2A,0,0,0,0}, ++ {"MOPG_C ",0x2B,0,0,0,0}, ++ {"WAVE511 ",0x2E,0,0,0,0}, ++ {"CPU ",0x70,0,0,0,0}, ++}; ++ ++#if MIU_NUM > 1 ++static struct miu_client miu1_clients[] = ++{ ++ {"OVERALL ",0x00,0,1,0,0}, ++}; ++#endif ++ ++static struct miu_device miu0; ++#if MIU_NUM > 1 ++static struct miu_device miu1; ++#endif ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++static int gmonitor_interval[MIU_NUM] = {4};//{14}; ++static int gmonitor_duration[MIU_NUM] = {2000};//{1800}; ++static int gmonitor_output_kmsg[MIU_NUM] = {1}; ++ ++static char m_bOutputFilePath[128] = "/mnt/dump_miu_bw.txt"; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++ ++static struct file *miu_bw_open_file(char *path, int flag, int mode) ++{ ++ struct file *filp = NULL; ++ mm_segment_t oldfs; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ filp = filp_open(path, flag, mode); ++ ++ set_fs(oldfs); ++ if (IS_ERR(filp)) { ++ return NULL; ++ } ++ return filp; ++} ++ ++static int miu_bw_write_file(struct file *fp, char *buf, int writelen) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_write(fp, buf, writelen, &fp->f_pos); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++static int miu_bw_close_file(struct file *fp) ++{ ++ filp_close(fp, NULL); ++ return 0; ++} ++ ++const char* miu_client_id_to_name(U16 id) ++{ ++ int i = 0; ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_client_id == id) { ++ return miu0_clients[i].name; ++ } ++ } ++ return NULL; ++} ++ ++static int set_miu_client_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_enabled = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_enabled = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static int set_miu_client_dump_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_dump_en = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_dump_en = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static int set_miu_client_filter_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_filter_en = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_filter_en = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_enabled = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_enabled = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_enabled); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_enabled); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_enabled = 0; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_enabled = 0; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 0); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_enabled); ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_enabled); ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_interval[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_interval[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ if ('0'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_interval[0]); ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_interval[1]); ++#endif ++ else ++ return 0; ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_duration[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_duration[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ if ('0'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_duration[0]); ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_duration[1]); ++#endif ++ else ++ return 0; ++} ++ ++static ssize_t monitor_client_dump_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_dump_en = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_dump_en = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_dump_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_dump_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_dump_en); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_dump_en); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_filter_abnormal_value_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_filter_en = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_filter_en = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_filter_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_filter_abnormal_value_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_filter_en); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_filter_en); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_output_kmsg[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_output_kmsg[1] = input; ++#endif ++ ++ return count; ++} ++ ++#define DUMP_FILE_TEMP_BUF_SZ (PAGE_SIZE*10) ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0, temp_loop_time = 0; ++ int id; ++ int iMiuClientNum = 0; ++ int iMonitorInterval = 0; ++ int iMonitorDuration = 0; ++ int iMonitorOutputKmsg = 1; ++ int iMonitorDumpToFile = 0; ++ int iMiuBankAddr = 0; ++ struct miu_client *pstMiuClient = NULL; ++ ++ short temp_val = 0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ char* u8Buf = NULL; ++ char* u8Ptr = NULL; ++ char* u8PtrEnd = NULL; ++ struct file *pstOutFd = NULL; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU0_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[0]; ++ iMonitorDuration = gmonitor_duration[0]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[0]; ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ pstMiuClient = &miu0_clients[0]; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU1_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[1]; ++ iMonitorDuration = gmonitor_duration[1]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[1]; ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ pstMiuClient = &miu1_clients[0]; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) { ++ (pstMiuClient + i)->effi_min = 0x3FF; ++ (pstMiuClient + i)->effi_avg = 0; ++ (pstMiuClient + i)->bw_avg = 0; ++ (pstMiuClient + i)->bw_max = 0; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ iMonitorDumpToFile = 1; ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ u8Buf = kmalloc(DUMP_FILE_TEMP_BUF_SZ, GFP_KERNEL); ++ u8Ptr = u8Buf; ++ u8PtrEnd = u8Buf + (DUMP_FILE_TEMP_BUF_SZ); ++ ++ pstOutFd = miu_bw_open_file(m_bOutputFilePath, O_WRONLY | O_CREAT, 0644); ++ } ++ ++ if (iMonitorOutputKmsg) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) ++ { ++ if ((pstMiuClient + i)->bw_enabled && (pstMiuClient + i)->bw_rsvd == 0) ++ { ++ unsigned long diff = 0; ++ short last; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ id = (pstMiuClient + i)->bw_client_id; ++ OUTREG16((iMiuBankAddr+REG_ID_15), (id & 0x40) ? 0x80 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); // set to read efficiency ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ if (iMonitorInterval > 10) ++ msleep(iMonitorInterval); ++ else ++ mdelay(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (temp_loop_time) { ++ diff += (temp_val > last) ? (temp_val - last) : (last - temp_val); ++ } ++ last = temp_val; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] Efficiency\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->effi_min > temp_val) { ++ (pstMiuClient + i)->effi_min = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->effi_avg = total_temp / temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read bandwidth ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ if (iMonitorInterval > 10) ++ msleep(iMonitorInterval); ++ else ++ mdelay(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (iMonitorDumpToFile && (pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] BandWidth\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->bw_max < temp_val) { ++ (pstMiuClient + i)->bw_max = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->bw_avg = total_temp / temp_loop_time; ++ ++ // client effiency never changes and total BW is zero ++ if ((diff == 0) && (total_temp == 0)) { ++ (pstMiuClient + i)->effi_avg = 0x3FF; ++ } ++ ++ if (iMonitorOutputKmsg) ++ { ++ printk("%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)(pstMiuClient + i)->bw_client_id, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_avg*10000/(pstMiuClient + i)->effi_avg)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_avg*10000/(pstMiuClient + i)->effi_avg)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ if (pstOutFd) { ++ miu_bw_write_file(pstOutFd, u8Buf, u8Ptr - u8Buf); ++ miu_bw_close_file(pstOutFd); ++ } ++ ++ kfree(u8Buf); ++ } ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_hw_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0, temp_loop_time = 0; ++ int id; ++ int iMiuClientNum = 0; ++ int iMonitorInterval = 0; ++ int iMonitorDuration = 0; ++ int iMonitorOutputKmsg = 1; ++ int iMonitorDumpToFile = 0; ++ int iMiuBankAddr = 0; ++ struct miu_client *pstMiuClient = NULL; ++ ++ short temp_val = 0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ char* u8Buf = NULL; ++ char* u8Ptr = NULL; ++ char* u8PtrEnd = NULL; ++ struct file *pstOutFd = NULL; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU0_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[0]; ++ iMonitorDuration = gmonitor_duration[0]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[0]; ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ pstMiuClient = &miu0_clients[0]; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU1_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[1]; ++ iMonitorDuration = gmonitor_duration[1]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[1]; ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ pstMiuClient = &miu1_clients[0]; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) { ++ (pstMiuClient + i)->effi_min = 0x3FF; ++ (pstMiuClient + i)->effi_avg = 0; ++ (pstMiuClient + i)->effi_max = 0; ++ (pstMiuClient + i)->bw_avg = 0; ++ (pstMiuClient + i)->bw_max = 0; ++ (pstMiuClient + i)->bw_min = 0x3FF; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ iMonitorDumpToFile = 1; ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ u8Buf = kmalloc(DUMP_FILE_TEMP_BUF_SZ, GFP_KERNEL); ++ u8Ptr = u8Buf; ++ u8PtrEnd = u8Buf + (DUMP_FILE_TEMP_BUF_SZ); ++ ++ pstOutFd = miu_bw_open_file(m_bOutputFilePath, O_WRONLY | O_CREAT, 0644); ++ } ++ ++ if (iMonitorOutputKmsg) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) ++ { ++ if ((pstMiuClient + i)->bw_enabled && (pstMiuClient + i)->bw_rsvd == 0) ++ { ++ unsigned long diff = 0; ++ short last; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ id = (pstMiuClient + i)->bw_client_id; ++ OUTREG16((iMiuBankAddr+REG_ID_15), (id & 0x40) ? 0x80 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0333); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); // set to read efficiency ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ msleep(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (temp_loop_time) { ++ diff += (temp_val > last) ? (temp_val - last) : (last - temp_val); ++ } ++ last = temp_val; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] Efficiency\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->effi_min > temp_val) { ++ (pstMiuClient + i)->effi_min = temp_val; ++ } ++ else if ((pstMiuClient + i)->effi_max < temp_val) { ++ (pstMiuClient + i)->effi_max = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->effi_avg = total_temp / temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read bandwidth ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ msleep(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (iMonitorDumpToFile && (pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] BandWidth\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->bw_max < temp_val) { ++ (pstMiuClient + i)->bw_max = temp_val; ++ } ++ else if ((pstMiuClient + i)->bw_min > temp_val) { ++ (pstMiuClient + i)->bw_min = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->bw_avg = total_temp / temp_loop_time; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x60)) ;//reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x61)) ;//set to read peak ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ do{ ++ msleep(iMonitorDuration); ++ } while (!time_after_eq(jiffies, deadline)); ++ (pstMiuClient + i)->bw_max_div_effi=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x20)) ;//reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x21)) ;//set to read peak ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ do{ ++ msleep(iMonitorDuration); ++ } while (!time_after_eq(jiffies, deadline)); ++ (pstMiuClient + i)->bw_avg_div_effi=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ // client effiency never changes and total BW is zero ++ if ((diff == 0) && (total_temp == 0)) { ++ (pstMiuClient + i)->effi_avg = 0x3FF; ++ } ++ ++ if (iMonitorOutputKmsg) ++ { ++ printk("%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)(pstMiuClient + i)->bw_client_id, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_avg_div_effi*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_avg_div_effi*10000/1024)%100, ++ (pstMiuClient + i)->bw_max_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_max_div_effi*10000/1024)%100); ++ } ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ if (pstOutFd) { ++ miu_bw_write_file(pstOutFd, u8Buf, u8Ptr - u8Buf); ++ miu_bw_close_file(pstOutFd); ++ } ++ ++ kfree(u8Buf); ++ } ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int iMiupllBankAddr = 0; ++ unsigned int dram_type = 0; ++ unsigned int ddfset = 0; ++ unsigned int dram_freq = 0; ++ unsigned int miupll_freq = 0; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ iAtopBankAddr = BASE_REG_ATOP1_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ddfset = (INREGMSK16(iAtopBankAddr + REG_ID_19, 0x00FF) << 16) + INREGMSK16(iAtopBankAddr + REG_ID_18, 0xFFFF); ++ dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ miupll_freq = 24 * INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x00FF) / ((INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x0700) >> 8) + 2); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", dram_freq); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", miupll_freq); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++DEVICE_ATTR(monitor_client_dump_enable, 0644, monitor_client_dump_enable_show, monitor_client_dump_enable_store); ++DEVICE_ATTR(monitor_client_filter_enable, 0644, monitor_filter_abnormal_value_show, monitor_filter_abnormal_value_store); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++DEVICE_ATTR(measure_all_hw, 0644, measure_all_hw_show, measure_all_store); ++DEVICE_ATTR(dram_info, 0444, dram_info_show, NULL); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret = 0; ++ ++ miu0.index = 0; ++ miu0.dev.kobj.name = "miu0"; ++ miu0.dev.bus = &miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&miu0.dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu0.dev, &dev_attr_measure_all); ++ device_create_file(&miu0.dev, &dev_attr_measure_all_hw); ++ device_create_file(&miu0.dev, &dev_attr_dram_info); ++ ++#if MIU_NUM > 1 ++ miu1.index = 0; ++ miu1.dev.kobj.name = "miu1"; ++ miu1.dev.bus = &miu_subsys; ++ ++#if 0 // Don't register again ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++#endif ++ ++ ret = device_register(&miu1.dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu1 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu1.dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu1.dev, &dev_attr_measure_all); ++ device_create_file(&miu1.dev, &dev_attr_measure_all_hw); ++ device_create_file(&miu1.dev, &dev_attr_dram_info); ++#endif ++} +diff --git a/arch/arm/mach-sstar/infinity2m/pm.c b/arch/arm/mach-sstar/infinity2m/pm.c +new file mode 100644 +index 000000000000..670e07bed98f +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/pm.c +@@ -0,0 +1,80 @@ ++/* ++* pm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void infinity_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&infinity_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity2m/smp_head.S b/arch/arm/mach-sstar/infinity2m/smp_head.S +new file mode 100755 +index 000000000000..0656903f5816 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/smp_head.S +@@ -0,0 +1,106 @@ ++/* ++* smp_head.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++ ++/* __CPUINIT */ ++ ++#define ACTLR_SMP_ENABLE 0x0040 ++#define ACTLR_DODMBS_DISABLE 0x0400 ++#define ACTLR_L2RADIS_DISABLE 0x0800 ++#define ACTLR_L1RADIS_DISABLE 0x1000 ++#define ACTLR_L1PCTL_3_PREFETCH 0x6000 ++#define ACTLR_DDVM_DISABLE 0x8000 ++ ++#define NSACR_CP11 0x0800 ++#define NSACR_CP10 0x0400 ++ ++#define CPACR_CP11_FULL 0x00C00000 ++#define CPACR_CP10_FULL 0x00300000 ++ ++.extern infinity2m_secondary_gic ++ ++/* ++ * Realview/Versatile Express specific entry point for secondary CPUs. ++ * This provides a "holding pen" into which all secondary cores are held ++ * until we're ready for them to initialise. ++ */ ++ENTRY(infinity2m_secondary_startup) ++#ifdef CONFIG_LH_RTOS ++ ldr r0, =0xA0001000 ++ mov sp, r0 ++ ++ bl secure_cntvoff_init ++ ++ bl infinity2m_secondary_gic ++ ++ //ACTLR ++ mrc p15, 0, r0, c1, c0, 1 ++ orr r0, r0, #(ACTLR_DDVM_DISABLE) ++ orr r0, r0, #(ACTLR_L1PCTL_3_PREFETCH) ++ orr r0, r0, #(ACTLR_L1RADIS_DISABLE) ++ orr r0, r0, #(ACTLR_L2RADIS_DISABLE) ++ orr r0, r0, #(ACTLR_DODMBS_DISABLE) ++ orr r0, r0, #(ACTLR_SMP_ENABLE) ++ mcr p15, 0, r0, c1, c0, 1 ++ isb ++ ++ //NSACR ++ mrc p15, 0, r0, c1, c1, 2 ++ orr r0, r0, #(NSACR_CP11) ++ orr r0, r0, #(NSACR_CP10) ++ mcr p15, 0, r0, c1, c1, 2 ++ isb ++ ++ //switch to NS ++ mrc p15, 0, r1, c1, c1, 0 ++ orr r0, r1, #1 ++ mcr p15, 0, r0, c1, c1, 0 ++ isb ++ ++ //CPACR ++ mrc p15, 0, r0, c1, c0, 2 ++ orr r0, r0, #(CPACR_CP11_FULL) ++ orr r0, r0, #(CPACR_CP10_FULL) ++ mcr p15, 0, r0, c1, c0, 2 ++ isb ++#endif ++ ++ /* Native ARMv7 L1 invalide function */ ++ bl v7_invalidate_l1 ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ /* ++ * we've been released from the holding pen: secondary_stack ++ * should now contain the SVC stack for this core ++ */ ++ b secondary_startup ++ ++ ++ .align 2 ++1: .long . ++ .long pen_release ++ENDPROC(infinity2m_secondary_startup) +diff --git a/arch/arm/mach-sstar/infinity2m/smp_platform.c b/arch/arm/mach-sstar/infinity2m/smp_platform.c +new file mode 100755 +index 000000000000..2400107e9777 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/smp_platform.c +@@ -0,0 +1,408 @@ ++/* ++* smp_platform.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * cedric_smp.c ++ * ++ * Created on: 2015�~4��30�� ++ * Author: Administrator ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++ ++extern int infinity2m_platform_cpu_kill(unsigned int cpu); ++extern void infinity2m_platform_cpu_die(unsigned int cpu); ++extern int infinity2m_platform_cpu_disable(unsigned int cpu); ++ ++//extern volatile int __cpuinitdata pen_release; ++extern volatile int pen_release; ++extern void Chip_Flush_CacheAll(void); ++ ++//#define SCU_PHYS 0x16000000 /*Cedric*/ ++#define SCU_PHYS 0x16000000 /*MACAN*/ // SCU PA = 0x16004000 ++ ++ ++ ++static inline void cpu_enter_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk("ms_hotplug.c cpu_enter_lowpower: in\n"); ++ ++ flush_cache_all(); ++ asm volatile( ++ " mcr p15, 0, %1, c7, c5, 0\n" ++ " mcr p15, 0, %1, c7, c10, 4\n" ++ /* ++ * Turn off coherency ++ */ ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " bic %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ " mrc p15, 0, %0, c1, c0, 0\n" ++ " bic %0, %0, %2\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ : "=&r" (v) ++ : "r" (0), "Ir" (CR_C) ++ : "cc"); ++ ++ printk("ms_hotplug.c cpu_enter_lowpower: out\n"); ++} ++ ++static inline void cpu_leave_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk("ms_hotplug.c cpu_leave_lowpower: in\n"); ++ ++ asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" ++ " orr %0, %0, %1\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " orr %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ : "=&r" (v) ++ : "Ir" (CR_C) ++ : "cc"); ++ ++ printk("ms_hotplug.c cpu_leave_lowpower: out\n"); ++} ++ ++static inline void platform_do_lowpower(unsigned int cpu, int *spurious) ++{ ++ //printk("ms_hotplug.c platform_do_lowpower: before %d cpu go into WFI, spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * there is no power-control hardware on this platform, so all ++ * we can do is put the core into WFI; this is safe as the calling ++ * code will have already disabled interrupts ++ */ ++ for (;;) { ++ /* ++ * here's the WFI ++ */ ++ asm(".word 0xe320f003\n" ++ : ++ : ++ : "memory", "cc"); ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up, spurious =%d \n", cpu, *spurious); ++ ++ if (pen_release == cpu_logical_map(cpu)) { ++ /* ++ * OK, proper wakeup, we're done ++ */ ++ break; ++ } ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up error(cpuID != pen_release), spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * Getting here, means that we have come out of WFI without ++ * having been woken up - this shouldn't happen ++ * ++ * Just note it happening - when we're woken, we can report ++ * its occurrence. ++ */ ++ (*spurious)++; ++ } ++} ++ ++int infinity2m_platform_cpu_kill(unsigned int cpu) ++{ ++ return 1; ++} ++ ++/* ++ * platform-specific code to shutdown a CPU ++ * ++ * Called with IRQs disabled ++ */ ++void __ref infinity2m_platform_cpu_die(unsigned int cpu) ++{ ++ int spurious = 0; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ ++ //printk("ms_hotplug.c platform_cpu_die: in cpu = %d \n", cpu); ++ ++ Chip_Flush_CacheAll(); ++ ++ /* ++ * we're ready for shutdown now, so do it ++ */ ++ //cpu_enter_lowpower(); ++ platform_do_lowpower(cpu, &spurious); ++ ++ /* ++ * bring this CPU back into the world of cache ++ * coherency, and then restore interrupts ++ */ ++ //cpu_leave_lowpower(); ++ ++ printk("ms_hotplug.c platform_cpu_die: out cpu = %d \n", cpu); ++ ++ if (spurious) ++ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); ++} ++ ++int infinity2m_platform_cpu_disable(unsigned int cpu) ++{ ++ /* ++ * we don't allow CPU 0 to be shutdown (it is still too special ++ * e.g. clock tick interrupts) ++ */ ++ ++ printk("ms_hotplug.c platform_cpu_disable: in cpu = %d \n", cpu); ++ return cpu == 0 ? -EPERM : 0; ++} ++ ++ ++/* ++ * control for which core is the next to come out of the secondary ++ * boot "holding pen" ++ */ ++//volatile int __cpuinitdata pen_release = -1; ++ ++static void __iomem *scu_base_addr(void) ++{ ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ return (void __iomem *)(IO_ADDRESS(SCU_PHYS)); ++} ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++//static void __cpuinit write_pen_release(int val) ++static void write_pen_release(int val) ++{ ++ pen_release = val; ++ smp_wmb(); ++ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); ++ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); ++} ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++//void __cpuinit infinity2m_secondary_init(unsigned int cpu) ++void infinity2m_secondary_init(unsigned int cpu) ++{ ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ ++ /* ++ * if any interrupts are already enabled for the primary ++ * core (e.g. timer irq), then they will not have been enabled ++ * for us: do so ++ */ ++ //gic_secondary_init(0); ++ ++ /* ++ * let the primary processor know we're out of the ++ * pen, then head off into the C entry point ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++#define SECOND_START_ADDR_HI 0x1F20404C ++#define SECOND_START_ADDR_LO 0x1F204050 ++#define SECOND_MAGIC_NUMBER_ADDR 0x1F204058 ++ ++//int __cpuinit infinity2m_boot_secondary(unsigned int cpu, struct task_struct *idle) ++int infinity2m_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ ++ unsigned long timeout; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ /* ++ * Set synchronisation state between this boot processor ++ * and the secondary one ++ */ ++ spin_lock(&boot_lock); ++ ++ /* ++ * This is really belt and braces; we hold unintended secondary ++ * CPUs in the holding pen until we're ready for them. However, ++ * since we haven't sent them a soft interrupt, they shouldn't ++ * be there. ++ */ ++ write_pen_release(cpu_logical_map(cpu)); ++ ++ do{ ++ OUTREG16(SECOND_MAGIC_NUMBER_ADDR, 0xBABE); ++ }while(INREG16(SECOND_MAGIC_NUMBER_ADDR)!=0xBABE); ++ /* ++ * Send the secondary CPU a soft interrupt, thereby causing ++ * the boot monitor to read the system wide flags register, ++ * and branch to the address found there. ++ */ ++ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ /* ++ * now the secondary core is starting up let it run its ++ * calibrations, then wait for it to finish ++ */ ++ spin_unlock(&boot_lock); ++ ++ return pen_release != -1 ? -ENOSYS : 0; ++} ++ ++ ++#include ++#include ++ ++extern void infinity2m_secondary_startup(void); ++ ++#define SCU_CTRL 0x00 ++ ++void __init infinity2m_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ int i; ++// u32 scu_ctrl; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ /* ++ * Initialise the present map, which describes the set of CPUs ++ * actually populated at the present time. ++ */ ++ for (i = 0; i < max_cpus; i++) ++ { ++ set_cpu_present(i, true); ++ } ++ ++#if defined(CONFIG_CEDRIC_MASTER0_ONLY_PATCH) ++ __raw_writel(0xe0000000, scu_base_addr() + 0x40); ++ __raw_writel(0xe0100000, scu_base_addr() + 0x44); ++ scu_ctrl = __raw_readl(scu_base_addr() + SCU_CTRL); ++ scu_ctrl |= 0x02; ++ __raw_writel(scu_ctrl, scu_base_addr() + SCU_CTRL); ++ printk(KERN_WARNING"SCU: Filter to Master0 only\n"); ++#endif ++ ++ scu_enable(scu_base_addr()); // SCU PA = 0x16000000 ++ ++// printk("[306]!! scu_enable\n"); ++ ++ /* ++ * Write the address of secondary startup into the ++ * system-wide flags register. The boot monitor waits ++ * until it receives a soft interrupt, and then the ++ * secondary CPU branches to this address. ++ */ ++ do{ ++ OUTREG16(SECOND_START_ADDR_LO,(virt_to_phys(infinity2m_secondary_startup) & 0xFFFF)); ++ }while(INREG16(SECOND_START_ADDR_LO)!=(virt_to_phys(infinity2m_secondary_startup) & 0xFFFF)); ++ ++ do{ ++ OUTREG16(SECOND_START_ADDR_HI,(virt_to_phys(infinity2m_secondary_startup)>>16)); ++ }while(INREG16(SECOND_START_ADDR_HI)!=(virt_to_phys(infinity2m_secondary_startup)>>16)); ++ ++ __cpuc_flush_kern_all(); ++} ++ ++void __init infinity2m_smp_init_cpus(void) ++{ ++ ++ void __iomem *scu_base =scu_base_addr(); ++ unsigned int i, ncores; ++// printk("[%s]\n",__FUNCTION__); ++ ncores = scu_base ? scu_get_core_count(scu_base) : 1; ++ ++ for (i = 0; i < 2; i++) ++ { ++ set_cpu_possible(i, true); ++ } ++} ++ ++#ifdef CONFIG_LH_RTOS ++#define GICD_IGROUPR 0x080 ++ ++#define GICC_CTLR 0x00 ++#define GICC_PMR 0x04 ++#define GICC_BPR 0x08 ++ ++#define GICD_BASE 0x16001000 ++#define GICC_BASE 0x16002000 ++ ++#define GICD_WRITEL(a,v) (*(volatile unsigned int *)(u32)(GICD_BASE + a) = (v)) ++#define GICC_WRITEL(a,v) (*(volatile unsigned int *)(u32)(GICC_BASE + a) = (v)) ++ ++void infinity2m_secondary_gic(void) ++{ ++ /* Diable GICC */ ++ GICC_WRITEL(GICC_CTLR,0x00000000); ++ ++ /* set interrupt priority mask level = 15, if the interrupt priority is larger than this value, it will be sent to CPU*/ ++ GICC_WRITEL(GICC_PMR , 0xf0); ++ ++ /* enable group priority */ ++ GICC_WRITEL(GICC_BPR , 3); ++ ++ /* LH: Set all interrupts are Grp 1 for IRQ */ ++ GICD_WRITEL(GICD_IGROUPR , ~0x0); ++ ++ /* LH: run in Secure Mode to Enable Grp1, Ackctl and FIQEn */ ++ GICC_WRITEL(GICC_CTLR,0x000001EA); //non-shared ++} ++#endif ++ ++struct smp_operations __initdata infinity2m_smp_ops = { ++ .smp_init_cpus = infinity2m_smp_init_cpus, ++ .smp_prepare_cpus = infinity2m_smp_prepare_cpus, ++ .smp_secondary_init = infinity2m_secondary_init, ++ .smp_boot_secondary = infinity2m_boot_secondary, ++ ++#ifdef CONFIG_HOTPLUG_CPU ++ .cpu_kill = infinity2m_platform_cpu_kill, ++ .cpu_die = infinity2m_platform_cpu_die, ++ .cpu_disable = infinity2m_platform_cpu_disable, ++#endif ++}; +diff --git a/arch/arm/mach-sstar/infinity2m/soc.c b/arch/arm/mach-sstar/infinity2m/soc.c +new file mode 100755 +index 000000000000..ca49d113e789 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/soc.c +@@ -0,0 +1,977 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Joe.Su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++#ifdef CONFIG_SS_AMP ++ {IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++ {IPC_MEM_VIRT, __phys_to_pfn(IPC_MEM_PHYS), IPC_MEM_SIZE, MT_DEVICE}, ++#endif ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "sstar,infinity2m", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++ ++ ++//extern struct timecounter *arch_timer_get_timecounter(void); ++ ++ ++static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Sstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ volatile unsigned long dwLockFlag = 0; ++ volatile unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ dsb(); ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++/*//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NAND BIT2 ++#define STORAGE_SPI_NAND_SKIPSD BIT3 ++#define STORAGE_SPI_NOR_SKIPSD BIT4 ++#define STORAGE_SPI_NOR BIT5 ++*/ ++ u8 type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & 0x3C); ++ ++ if(BIT3 == type || BIT2 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else if(BIT5 == type || BIT4 == type) ++ return (int)MS_STORAGE_NOR; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int mstar_get_package_type(void) ++{ ++ //printk("BOARD name [%s] \n", &mstar_soc_dev_attr.machine[11]); ++ ++ if(!strcmp(&mstar_soc_dev_attr.machine[11], "SSC010A-S01A-S")) ++ return MS_I2M_PACKAGE_QFN_DDR3_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[11], "FPGA")) ++ return MS_I2M_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I2M_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]="I2M"; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else if (1 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-3"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ } ++ ++ if (power_en_gpio >= 0) ++ { ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ } ++ return 0; ++} ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ u64 cycles=arch_timer_read_counter(); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ us_ticks_cycle_offset=arch_timer_read_counter(); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++ default: ++ printk(KERN_ERR "Unsupport CHIP_FUNCTION!! ID=%d\n",function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsb ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++} ++ ++static void mstar_analog_ip_powerdown(void) ++{ ++#ifdef CONFIG_ANALOG_PD_XINDIGPLL ++ // reg_miu_128bus_pll_pd BANK 1031, 16bit OFFSET 0x01[8] ++ SETREG16(BASE_REG_MIUPLL_PA + REG_ID_01, BIT8); ++#endif ++#ifdef CONFIG_ANALOG_PD_ARMPLL ++ // reg_mipspll_pd BANK 1032, 16bit OFFSET 0x11[8] ++ SETREG16(BASE_REG_ARMPLL_PA + REG_ID_11, BIT8); ++#endif ++#ifdef CONFIG_ANALOG_PD_AUDIO ++ // BANK 1034, 16bit OFFSET 0x00[1:0]: reg_en_byp_inmux ++ // 0xffffffffffffffff[2]: reg_en_chop_adc0 ++ // 0x00[7:4]: reg_en_ck_dac ++ // 0x00[8]: reg_en_dac_disch ++ // 0x00[9]: reg_en_itest_dac ++ // 0x00[10]: reg_en_itest_dac ++ // 0x00[11]: reg_en_msp ++ OUTREG16(BASE_REG_AUSDM_PA + REG_ID_00, 0x0000); ++ // BANK 1034, 16bit OFFSET 0x01[1:0]: reg_en_mute_inmux ++ // 0x01[2]: reg_en_mute_mic_stg1_l ++ // 0x01[3]: reg_en_mute_mic_stg1_r ++ // 0x01[4]: reg_en_qs_ldo_adc ++ // 0x01[5]: reg_en_qs_ldo_dac ++ // 0x01[6]: reg_en_shrt_l_adc0 ++ // 0x01[7]: reg_en_shrt_r_adc0 ++ // 0x01[9:8]: reg_en_tst_ibias_adc ++ // 0x01[10]: reg_en_vref_disch ++ // 0x01[12:10]: reg_en_vref_sftdch ++ OUTREG16(BASE_REG_AUSDM_PA + REG_ID_01, 0x0000); ++ // BANK 1034, 16bit OFFSET 0x03[0]: reg_pd_adc0 ++ // 0x03[1]: reg_pd_bias_dac ++ // 0x03[3:2]: reg_pd_inmux ++ // 0x03[4]: reg_pd_l0_dac ++ // 0x03[5]: reg_pd_ldo_adc ++ // 0x03[6]: reg_pd_ldo_dac ++ // 0x03[7]: reg_pd_mic_stg1_l ++ // 0x03[8]: reg_pd_mic_stg1_r ++ // 0x03[9]: reg_pd_r0_dac ++ // 0x03[10]: reg_pd_ref_dac ++ // 0x03[11]: reg_pd_vi ++ // 0x03[12]: reg_pd_vref ++ OUTREG16(BASE_REG_AUSDM_PA + REG_ID_03, 0x1FFF); ++#endif ++#ifdef CONFIG_ANALOG_PD_EMAC ++ // BANK 33, 16bit OFFSET 0x79[7] ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_79, BIT7); ++ // BANK 33, 16bit OFFSET 0x79[11:8] ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_79, BIT8 | BIT9 | BIT10 | BIT11); ++ // BANK 32, 16bit OFFSET 0x1F[14]: reg_analog_testen ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_1F, BIT14); ++ // BANK 32, 16bit OFFSET 0x5D[14]: reg_gcr_test_clk_en/PD_REF ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_5D, BIT14); ++ // BANK 32, 16bit OFFSET 0x66[3]: reg_gc_adcpl_ccpd1 ++ //SETREG16(BASE_REG_LANTOP1_PA + REG_ID_66, BIT3); ++ // BANK 32, 16bit OFFSET 0x66[4]: reg_pd_adcpl_reg ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_66, BIT4); ++ // BANK 32, 16bit OFFSET 0x5B[12]: reg_adc_pd ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_5B, BIT12); ++ // BANK 32, 16bit OFFSET 0x7E[1]: PD_REG25 ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_7E, BIT1); ++ // BANK 32, 16bit OFFSET 0x7E[8]: PD_LDO11 ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_7E, BIT11); ++ // BANK 32, 16bit OFFSET 0x69[14]: reg_atop_rx_inoff, 0x69[15]: reg_atop_tx_outoff ++ SETREG16(BASE_REG_LANTOP1_PA + REG_ID_69, BIT14 | BIT15); ++ // BANK 33, 16bit OFFSET 0x44[4]: RX_OFF ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_44, BIT4); ++ // BANK 33, 16bit OFFSET 0x50[12]: reg_pd_vbuf ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_50, BIT12); ++ // BANK 33, 16bit OFFSET 0x50[13]: reg_pd_sadc ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_50, BIT13); ++ // BANK 33, 16bit OFFSET 0x1D[0]: reg_pd_tx_ld ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_1D, BIT0); ++ // BANK 33, 16bit OFFSET 0x1D[1]: reg_pd_tx_idac ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_1D, BIT1); ++ // BANK 33, 16bit OFFSET 0x78[10]: reg_pd_tx_vbgr ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_78, BIT10); ++ // BANK 33, 16bit OFFSET 0x78[11]: reg_pd_tx_trimming_dac ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_78, BIT11); ++ // BANK 33, 16bit OFFSET 0x78[12]: reg_pd_tx_ld_dio ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_78, BIT12); ++ // BANK 33, 16bit OFFSET 0x78[13]: reg_pd_tx_ldo ++ SETREG16(BASE_REG_LANTOP2_PA + REG_ID_78, BIT13); ++#endif ++#ifdef CONFIG_ANALOG_PD_HDMI_ATOP ++ // BANK 1126, 16bit OFFSET 0x16[3:0]: reg_din_en_pstdrv_tap0_ch ++ // 0x16[7:4]: reg_din_en_pstdrv_tap1_ch ++ // 0x16[11:8]: reg_din_en_pstdrv_tap2_ch ++ OUTREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_16, 0x0); ++ // BANK 1126, 16bit OFFSET 0x1B[1]: reg_gcr_en_hdmitxpll_xtal ++ CLRREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_1B, BIT0); ++ // BANK 1126, 16bit OFFSET 0x30[3:0]: reg_pd_pstdrv_tap0_ch ++ // 0x30[7:4]: reg_pd_pstdrv_tap1_ch ++ // 0x30[11:8]: reg_pd_pstdrv_tap2_ch ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_30, BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | ++ BIT8 | BIT9 | BIT10 | BIT11); ++ // BANK 1126, 16bit OFFSET 0x31[3:0]: reg_pd_predrv_tap0_ch ++ // 0x31[7:4]: reg_pd_predrv_tap1_ch ++ // 0x31[11:8]: reg_pd_predrv_tap2_ch ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_31, BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | ++ BIT8 | BIT9 | BIT10 | BIT11); ++ // BANK 1126, 16bit OFFSET 0x32[3:0]: reg_pd_rterm_ch ++ // 0x32[7:4]: reg_pd_ldo_predrv_ch ++ // 0x32[11:8]: reg_pd_ldo_mux_ch ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_32, BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | ++ BIT8 | BIT9 | BIT10 | BIT11); ++ // BANK 1126, 16bit OFFSET 0x33[0]: reg_pd_ldo_clktree ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_33, BIT0); ++ // BANK 1126, 16bit OFFSET 0x34[0]: reg_pd_hdmitxpll ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_34, BIT0); ++ // BANK 1126, 16bit OFFSET 0x35[3:0]: reg_pd_drv_biasgen_ch, 0x35[4]: reg_pd_biasgen ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_35, BIT0 | BIT1 | BIT2 | BIT3 | BIT4); ++#endif ++#ifdef CONFIG_ANALOG_PD_IDAC_ATOP ++ // BANK 1127, 16bit OFFSET 0x15[0]: reg_en_idac_b ++ // 0x15[1]: reg_en_idac_g ++ // 0x15[2]: reg_en_idac_r ++ OUTREG16(BASE_REG_DAC_ATOP_PA + REG_ID_15, 0x0); ++ // BANK 1127, 16bit OFFSET 0x16[0]: reg_en_idac_ref ++ OUTREG16(BASE_REG_DAC_ATOP_PA + REG_ID_16, 0x0); ++ // BANK 1127, 16bit OFFSET 0x14[0]: reg_en_hd_dac_b_det ++ // 0x14[1]: reg_en_hd_dac_g_det ++ // 0x14[2]: reg_en_hd_dac_r_det ++ OUTREG16(BASE_REG_DAC_ATOP_PA + REG_ID_14, 0x0); ++ // BANK 1127, 16bit OFFSET 0x1F[0]: reg_pd_idac_ldo ++ OUTREG16(BASE_REG_DAC_ATOP_PA + REG_ID_1F, 0x1); ++ // BANK 1127, 16bit OFFSET 0x10[0]: reg_gpio_en_pad_out_b ++ // 0x10[1]: reg_gpio_en_pad_out_g ++ // 0x10[2]: reg_gpio_en_pad_out_r ++ OUTREG16(BASE_REG_DAC_ATOP_PA + REG_ID_10, 0x0); ++#endif ++#ifdef CONFIG_ANALOG_PD_IDAC_LPLL ++ // BANK 1127, 16bit OFFSET 0x36[0]: reg_emmcpll_pd ++ SETREG16(BASE_REG_HDMI_TX_ATOP_PA + REG_ID_36, BIT0); ++#endif ++#ifdef CONFIG_ANALOG_PD_DISP_LPLL ++ // BANK 1133, 16bit OFFSET 0x40[15]: reg_lpll_ext_pd ++ SETREG16(BASE_REG_DISP_LPLL_PA + REG_ID_40, BIT15); ++#endif ++#ifdef CONFIG_ANALOG_PD_MIPI_DPHY_TX_TOP ++ // BANK 1528, 16bit OFFSET 0x00[6]: reg_pd_ldo ++ SETREG16(BASE_REG_DPHY_DSI_PA + REG_ID_00, BIT6); ++ // BANK 1528, 16bit OFFSET 0x04[4]: reg_sw_lptx_en0 ++ // 0x04[6]: reg_sw_lprx_en0 ++ // 0x04[9:8]: reg_sw_outconf_ch0_bit ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_04, BIT4 | BIT6 | BIT8 | BIT9); ++ // BANK 1528, 16bit OFFSET 0x08[4]: reg_sw_lptx_en1 ++ // 0x08[6]: reg_sw_lprx_en1 ++ // 0x08[9:8]: reg_sw_outconf_ch1_bit ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_08, BIT4 | BIT6 | BIT8 | BIT9); ++ // BANK 1528, 16bit OFFSET 0x0c[4]: reg_sw_lptx_en2 ++ // 0x0c[6]: reg_sw_lprx_en2 ++ // 0x0c[9:8]: reg_sw_outconf_ch2_bit ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_0C, BIT4 | BIT6 | BIT8 | BIT9); ++ // BANK 1528, 16bit OFFSET 0x20[4]: reg_sw_lptx_en3 ++ // 0x20[6]: reg_sw_lprx_en3 ++ // 0x20[9:8]: reg_sw_outconf_ch3_bit ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_20, BIT4 | BIT6 | BIT8 | BIT9); ++ // BANK 1528, 16bit OFFSET 0x23[4]: reg_sw_lptx_en4 ++ // 0x23[6]: reg_sw_lprx_en4 ++ // 0x23[9:8]: reg_sw_outconf_ch4_bit ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_23, BIT4 | BIT6 | BIT8 | BIT9); ++ // BANK 1528, 16bit OFFSET 0x05[10]: reg_sw_hsrx_en_ch0 ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_05, BIT10); ++ // BANK 1528, 16bit OFFSET 0x09[10]: reg_sw_hsrx_en_ch1 ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_09, BIT10); ++ // BANK 1528, 16bit OFFSET 0x0D[10]: reg_sw_hsrx_en_ch2 ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_0D, BIT10); ++ // BANK 1528, 16bit OFFSET 0x21[10]: reg_sw_hsrx_en_ch3 ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_21, BIT10); ++ // BANK 1528, 16bit OFFSET 0x24[10]: reg_sw_hsrx_en_ch4 ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_24, BIT10); ++ // BANK 1528, 16bit OFFSET 0x03[0]: reg_sw_dphy_cken ++ CLRREG16(BASE_REG_DPHY_DSI_PA + REG_ID_03, BIT0); ++#endif ++#ifdef CONFIG_ANALOG_PD_MPLL ++ // BANK 1030, 16bit OFFSET 0x01[8]: reg_pd_mpll ++ // 0x01[9]: reg_pd_mpll_clk_adc_vco_div2 ++ // 0x01[10]: reg_pd_mpll_clk_adc_vco_div2_2 ++ // 0x01[11]: reg_pd_mpll_clk_adc_vco_div2_3 ++ // 0x01[12]: reg_pd_digclk ++ SETREG16(BASE_REG_MPLL_PA + REG_ID_01, BIT8 | BIT9 | BIT10 | BIT11 | BIT12); ++ // BANK 1030, 16bit OFFSET 0x02[0]: reg_en_mpll_rst ++ CLRREG16(BASE_REG_MPLL_PA + REG_ID_02, BIT0); ++ // BANK 1030, 16bit OFFSET 0x04[0]: reg_en_mpll_test ++ // 0x04[1]: reg_en_mpll_ov_sw ++ // 0x04[10]: reg_en_mpll_xtal ++ // 0x04[15]: reg_en_mpll_prdt ++ CLRREG16(BASE_REG_MPLL_PA + REG_ID_04, BIT0 | BIT1 | BIT10 | BIT15); ++#endif ++#ifdef CONFIG_ANALOG_PD_SATA_ATOP ++ // BANK 1525, 16bit OFFSET 0x00 ++ OUTREG16(BASE_REG_SATA_MAC_PA + REG_ID_00, 0x0000); ++ // BANK 1527, 16bit OFFSET 0x20[0]: reg_pd_sata_txpll ++ SETREG16(BASE_REG_SATA_ATOP_PA + REG_ID_20, BIT0); ++ // BANK 1527, 16bit OFFSET 0x30[0]: reg_pd_sata_rxpll ++ SETREG16(BASE_REG_SATA_ATOP_PA + REG_ID_30, BIT0); ++ // BANK 1527, 16bit OFFSET 0x31[10]: reg_pd_sata_rxpll_cdr ++ SETREG16(BASE_REG_SATA_ATOP_PA + REG_ID_31, BIT10); ++ // BANK 1526, 16bit OFFSET 0x08[15:0] ++ OUTREG16(BASE_REG_SATA_PHY_PA + REG_ID_08, 0xFFFF); ++ // BANK 1526, 16bit OFFSET 0x00[15:0] ++ OUTREG16(BASE_REG_SATA_PHY_PA + REG_ID_00, 0x105B); ++ // BANK 1526, 16bit OFFSET 0x01[5]: reg_ssusb_pll_ssc_en ++ // 0x01[6]: reg_ssusb_rx_impcalib_en ++ CLRREG16(BASE_REG_SATA_PHY_PA + REG_ID_00, BIT5 | BIT6); ++#endif ++#ifdef CONFIG_ANALOG_PD_UPLL_0 ++ // BANK 1420, 16bit OFFSET 0x00[1]: reg_upll_pd ++ // 0x00[4]: reg_upll_enddisc ++ // 0x00[5]: reg_upll_enfrun ++ SETREG16(BASE_REG_UPLL0_PA + REG_ID_00, BIT1 | BIT4 | BIT5); ++ // BANK 1420, 16bit OFFSET 0x00[7]: reg_upll_enxtal ++ CLRREG16(BASE_REG_UPLL0_PA + REG_ID_00, BIT7); ++ // BANK 1420, 16bit OFFSET 0x01[7]: reg_upll_en_prdt ++ CLRREG16(BASE_REG_UPLL0_PA + REG_ID_01, BIT7); ++ // BANK 1420, 16bit OFFSET 0x02[15:0]: reg_upll_test ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_02, 0x0000); ++ // BANK 1420, 16bit OFFSET 0x07[0]: reg_clk0_upll_384_en ++ // 0x07[1]: reg_upll_en_prdt2 ++ // 0x07[2]: reg_en_clk_upll_192m ++ CLRREG16(BASE_REG_UPLL0_PA + REG_ID_07, BIT0 | BIT1 | BIT2); ++ // BANK 1420, 16bit OFFSET 0x07[3]: reg_pd_clk0_audio ++ SETREG16(BASE_REG_UPLL0_PA + REG_ID_07, BIT3); ++#endif ++#ifdef CONFIG_ANALOG_PD_UPLL_1 ++ // BANK 141F, 16bit OFFSET 0x00[1]: reg_upll_pd ++ // 0x00[4]: reg_upll_enddisc ++ // 0x00[5]: reg_upll_enfrun ++ SETREG16(BASE_REG_UPLL1_PA + REG_ID_00, BIT1 | BIT4 | BIT5); ++ // BANK 141F, 16bit OFFSET 0x00[7]: reg_upll_enxtal ++ CLRREG16(BASE_REG_UPLL1_PA + REG_ID_00, BIT7); ++ // BANK 141F, 16bit OFFSET 0x01[7]: reg_upll_en_prdt ++ CLRREG16(BASE_REG_UPLL1_PA + REG_ID_01, BIT7); ++ // BANK 141F, 16bit OFFSET 0x02[15:0]: reg_upll_test ++ OUTREG16(BASE_REG_UPLL1_PA + REG_ID_02, 0x0000); ++ // BANK 141F, 16bit OFFSET 0x07[0]: reg_clk0_upll_384_en ++ // 0x07[1]: reg_upll_en_prdt2 ++ // 0x07[2]: reg_en_clk_upll_192m ++ CLRREG16(BASE_REG_UPLL1_PA + REG_ID_07, BIT0 | BIT1 | BIT2); ++ // BANK 141F, 16bit OFFSET 0x07[3]: reg_pd_clk0_audio ++ SETREG16(BASE_REG_UPLL1_PA + REG_ID_07, BIT3); ++#endif ++#ifdef CONFIG_ANALOG_PD_USB20_P1 ++ // BANK 1421, 16bit OFFSET 0x00[2]: reg_ref_pdn ++ // 0x00[6]: reg_r_dp_pden ++ // 0x00[7]: reg_r_dm_pden ++ // 0x00[8]: reg_hs_dm_pdn ++ // 0x00[9]: reg_pll_pdn ++ // 0x00[10]: reg_hs_ted_pdn ++ // 0x00[11]: reg_hs_preamp_pdn ++ // 0x00[12]: reg_fl_xcvr_pdn ++ // 0x00[13]: reg_vbusdet_pdn ++ // 0x00[14]: reg_iref_pdn ++ // 0x00[15]: reg_reg_pdn ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT2 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | ++ BIT11 | BIT12 | BIT13 | BIT14 | BIT15); ++ // BANK 1421, 16bit OFFSET 0x04[7]: reg_clk_extra_0_ena/PD_BG_CURRENT ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0080); ++ // BANK 1421, 16bit OFFSET 0x05[6]: reg_clktest_inv/HS_TXSER_EN ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_05, BIT6); ++#endif ++#ifdef CONFIG_ANALOG_PD_USB20_P2 ++ // BANK 1425, 16bit OFFSET 0x00[2]: reg_ref_pdn ++ // 0x00[6]: reg_r_dp_pden ++ // 0x00[7]: reg_r_dm_pden ++ // 0x00[8]: reg_hs_dm_pdn ++ // 0x00[9]: reg_pll_pdn ++ // 0x00[10]: reg_hs_ted_pdn ++ // 0x00[11]: reg_hs_preamp_pdn ++ // 0x00[12]: reg_fl_xcvr_pdn ++ // 0x00[13]: reg_vbusdet_pdn ++ // 0x00[14]: reg_iref_pdn ++ // 0x00[15]: reg_reg_pdn ++ SETREG16(BASE_REG_UTMI1_PA + REG_ID_00, BIT2 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | ++ BIT11 | BIT12 | BIT13 | BIT14 | BIT15); ++ // BANK 1425, 16bit OFFSET 0x04[7]: reg_clk_extra_0_ena/PD_BG_CURRENT ++ OUTREG16(BASE_REG_UTMI1_PA + REG_ID_04, 0x0080); ++ // BANK 1425, 16bit OFFSET 0x05[6]: reg_clktest_inv/HS_TXSER_EN ++ CLRREG16(BASE_REG_UTMI1_PA + REG_ID_05, BIT6); ++#endif ++#ifdef CONFIG_ANALOG_PD_USB20_P3 ++ // BANK 1429, 16bit OFFSET 0x00[2]: reg_ref_pdn ++ // 0x00[6]: reg_r_dp_pden ++ // 0x00[7]: reg_r_dm_pden ++ // 0x00[8]: reg_hs_dm_pdn ++ // 0x00[9]: reg_pll_pdn ++ // 0x00[10]: reg_hs_ted_pdn ++ // 0x00[11]: reg_hs_preamp_pdn ++ // 0x00[12]: reg_fl_xcvr_pdn ++ // 0x00[13]: reg_vbusdet_pdn ++ // 0x00[14]: reg_iref_pdn ++ // 0x00[15]: reg_reg_pdn ++ SETREG16(BASE_REG_UTMI2_PA + REG_ID_00, BIT2 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | ++ BIT11 | BIT12 | BIT13 | BIT14 | BIT15); ++ // BANK 1429, 16bit OFFSET 0x04[7]: reg_clk_extra_0_ena/PD_BG_CURRENT ++ OUTREG16(BASE_REG_UTMI2_PA + REG_ID_04, 0x0080); ++ // BANK 1429, 16bit OFFSET 0x05[6]: reg_clktest_inv/HS_TXSER_EN ++ CLRREG16(BASE_REG_UTMI2_PA + REG_ID_05, BIT6); ++#endif ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++ ++ // power down analog IP here ++ mstar_analog_ip_powerdown(); ++} ++ ++struct mcm_client{ ++ char* name; ++ short index; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, 0}, ++ {"VHE", MCM_ID_VHE, 0}, ++ {"MFE", MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, 0}, ++ {"AESDMA", MCM_ID_AESDMA, 0}, ++ {"UHC", MCM_ID_UHC, 0}, ++ {"EMAC", MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, 0}, ++ {"GOP", MCM_ID_GOP, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, 0}, ++ {"*ALL_CLIENTS*", MCM_ID_ALL, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ return 0; ++ } ++ else if(index == MCM_ID_MCU51) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x0; ++ else if (index == MCM_ID_URDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x1; ++ else if (index == MCM_ID_BDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x4; ++ else if (index == MCM_ID_VHE) ++ addr = BASE_REG_MCM_VHE_GP_PA + 0x0; ++ else if (index == MCM_ID_MFE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x0; ++ else if (index == MCM_ID_JPE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1; ++ else if (index == MCM_ID_BACH) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x4; ++ else if (index == MCM_ID_AESDMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x5; ++ else if (index == MCM_ID_UHC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x8; ++ else if (index == MCM_ID_EMAC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x9; ++ else if (index == MCM_ID_CMDQ) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xC; ++ else if (index == MCM_ID_ISP_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xD; ++ else if (index == MCM_ID_ISP_DMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x10; ++ else if (index == MCM_ID_GOP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x11; ++ else if (index == MCM_ID_SC_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x14; ++ else if (index == MCM_ID_SC_DNR_SAD) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x15; ++ else if (index == MCM_ID_SC_CROP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x18; ++ else if (index == MCM_ID_SC1_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x19; ++ else if (index == MCM_ID_SC1_SNP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1C; ++ else if (index == MCM_ID_SC1_DBG) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1D; ++ else if (index == MCM_ID_SC2_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x20; ++ else if (index == MCM_ID_SC3_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x21; ++ else if (index == MCM_ID_FCIE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x24; ++ else if (index == MCM_ID_SDIO) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x25; ++ else if (index == MCM_ID_SC1_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x28; ++ else if (index == MCM_ID_SC2_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x29; ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++ ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++ mstar_create_MCM_node(); ++} ++ ++static void global_reset(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++#ifdef CONFIG_SMP ++extern struct smp_operations infinity2m_smp_ops; ++#endif ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = global_reset, ++#ifdef CONFIG_SMP ++ .smp = smp_ops(infinity2m_smp_ops), ++#endif ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity2m/sram.S b/arch/arm/mach-sstar/infinity2m/sram.S +new file mode 100755 +index 000000000000..13a598e79752 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity2m/sram.S +@@ -0,0 +1,191 @@ ++/* ++* sram.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl sram_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(sram_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(sram_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity3/Kconfig b/arch/arm/mach-sstar/infinity3/Kconfig +new file mode 100644 +index 000000000000..931ee09b48f4 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity3/Kconfig +@@ -0,0 +1,10 @@ ++config ARCH_INFINITY3 ++ bool "SoC iNfinity3 (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity3 SoC +diff --git a/arch/arm/mach-sstar/infinity3/Makefile b/arch/arm/mach-sstar/infinity3/Makefile +new file mode 100755 +index 000000000000..5a6b88f5cce9 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity3/Makefile +@@ -0,0 +1,8 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += soc.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity3/miu_bw.c b/arch/arm/mach-sstar/infinity3/miu_bw.c +new file mode 100755 +index 000000000000..a8d60c31317e +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity3/miu_bw.c +@@ -0,0 +1,745 @@ ++/* ++* miu_bw.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client{ ++ char* name; ++ short bw_client_id; ++ short bw_enabled; ++ short bw_max; ++ short bw_avg; ++ short effi_avg; ++ short effi_min; ++// short bw_val_thread; ++}; ++ ++static struct miu_client miu0_clients[] = { ++ {"OVERALL ",0x00,1,0,0}, ++ {"MFE(F) ",0x01,0,0,0}, ++ {"MFE(B) ",0x02,0,0,0}, ++ {"VHE ",0x03,0,0,0}, ++ {"JPE1 ",0x04,0,0,0}, ++ {"JPE0 ",0x05,0,0,0}, ++ {"BACH ",0x06,0,0,0}, ++ {"AESDMA ",0x07,0,0,0}, ++ {"UHC0 ",0x08,0,0,0}, ++ {"EMAC ",0x09,0,0,0}, ++ {"MCU51 ",0x0A,0,0,0}, ++ {"URDMA ",0x0B,0,0,0}, ++ {"BDMA ",0x0C,0,0,0}, ++ {"NA ",0x0D,0,0,0}, ++ {"NA ",0x0E,0,0,0}, ++ {"MBIST ",0x0F,0,0,0}, ++ {"CMDQ ",0x10,0,0,0}, ++ {"ISP_DNR ",0x11,0,0,0}, ++ {"ISP_ROT ",0x12,0,0,0}, ++ {"ISP_STA ",0x13,0,0,0}, ++ {"ISP_MNL ",0x14,0,0,0}, ++ {"GOP0 ",0x15,0,0,0}, ++ {"SC_DNR ",0x16,0,0,0}, ++ {"SC_DNR_SAD",0x17,0,0,0}, ++ {"SC_CROP ",0x18,0,0,0}, ++ {"SC1_FRM ",0x19,0,0,0}, ++ {"SC1_SNP ",0x1A,0,0,0}, ++ {"SC1_DBG ",0x1B,0,0,0}, ++ {"SC2_FRM ",0x1C,0,0,0}, ++ {"SC3_FRM ",0x1D,0,0,0}, ++ {"FCIE ",0x1E,0,0,0}, ++ {"SDIO ",0x1F,0,0,0}, ++ {"CMDQ1 ",0x20,0,0,0}, ++ {"CMDQ2 ",0x21,0,0,0}, ++ {"NA ",0x22,0,0,0}, ++ {"ISP_STA1 ",0x23,0,0,0}, ++ {"GOP1 ",0x24,0,0,0}, ++ {"GOP2 ",0x25,0,0,0}, ++ {"UHC1 ",0x26,0,0,0}, ++ {"IVE ",0x27,0,0,0}, ++ {"MIIC1 ",0x28,0,0,0}, ++ {"CPU ",0x70,0,0,0}, ++ ++}; ++ ++ ++static struct miu_device miu0; ++ ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++//static struct task_struct *pBWmonitorThread=NULL; ++//struct mutex bw_monitor_mutex; ++ ++int gmonitor_interval = 14; ++int gmonitor_duration = 1800; ++int gmonitor_output_kmsg = 1; ++ ++ ++ ++/* ++int BW_measure(short bwclientid) ++{ ++ short BW_val=0; ++ mutex_lock(&bw_monitor_mutex); ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x50)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ mdelay(300); ++ BW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ ++ mutex_unlock(&bw_monitor_mutex); ++ ++ return BW_val; ++} ++ ++static int BW_monitor(void *arg) ++{ ++ int i=0; ++ short tempBW_val=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ ++ if(miu0_clients[i].bw_enabled) ++ { ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x50)) ;//reset ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ //mdelay(300); ++ //tempBW_val=0; ++ //tempBW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ tempBW_val=BW_measure(miu0_clients[i].bw_client_id); ++ ++ if(miu0_clients[i].bw_val_thread= (sizeof(miu0_clients)/sizeof(miu0_clients[0])) ) return -EINVAL; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ miu0_clients[idx].bw_enabled=enabled; ++ } ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if(!strncmp(buf, "all",strlen("all"))) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_enabled=1; ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev,opt,n,1); ++ } ++ kfree(pt); ++ return n; ++} ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if(!strncmp(buf, "all",strlen("all"))) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_enabled=0; ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev,opt,n,0); ++ } ++ kfree(pt); ++ return n; ++ ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i,miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i,miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_interval = input; ++ return count; ++} ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gmonitor_interval); ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_duration = input; ++ return count; ++} ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gmonitor_duration); ++} ++ ++/* ++static ssize_t measure_bandwidth_MAX_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int ip_loop_time=1; ++ int i=0, temp_loop_time=0; ++ short tempBW_val=0; ++ ++ //reset all bw value ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_max=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ for (temp_loop_time=0;temp_loop_time buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++ ++static ssize_t measure_bandwidth_AVG_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ short temp_val=0; ++ ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ //reset all bw value ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_avg=0; ++ miu0_clients[i].bw_max=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x40)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x41)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ if(gmonitor_interval>10) ++ msleep(gmonitor_interval); ++ else ++ mdelay(gmonitor_interval); ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].bw_max buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_efficiency_AVG_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ ++ short temp_val=0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].effi_min=0x3ff; ++ miu0_clients[i].effi_avg=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x30)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x35)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ if(gmonitor_interval>10) ++ msleep(gmonitor_interval); ++ else ++ mdelay(gmonitor_interval); ++ ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].effi_min>temp_val) ++ { ++ miu0_clients[i].effi_min=temp_val; ++ } ++ temp_loop_time++; ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ miu0_clients[i].effi_avg=total_temp/temp_loop_time; ++ ++ //str += scnprintf(str, end - str, "%2d:%s[0x%02X] EFFI_avg=%4d,%3d.%02d%% EFFI_min=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ printk( "%2d:%s[0x%02X] EFFI_avg=%4d,%3d.%02d%% EFFI_min=%4d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id, ++ miu0_clients[i].effi_avg, ++ miu0_clients[i].effi_avg*100/1024, ++ (miu0_clients[i].effi_avg*10000/1024)%100, ++ miu0_clients[i].effi_min, ++ miu0_clients[i].effi_min*100/1024, ++ (miu0_clients[i].effi_min*10000/1024)%100); ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++*/ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_output_kmsg = input; ++ return count; ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ ++ short temp_val=0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].effi_min=0x3ff; ++ miu0_clients[i].effi_avg=0; ++ miu0_clients[i].bw_avg=0; ++ miu0_clients[i].bw_max=0; ++ } ++ if(gmonitor_output_kmsg) ++ { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x30)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x35)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ if(gmonitor_interval>10) ++ msleep(gmonitor_interval); ++ else ++ mdelay(gmonitor_interval); ++ ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].effi_min>temp_val) ++ { ++ miu0_clients[i].effi_min=temp_val; ++ } ++ temp_loop_time++; ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ miu0_clients[i].effi_avg=total_temp/temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x40)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x41)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ msleep(gmonitor_interval); //mdelay(gmonitor_interval); ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].bw_max buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++/* ++static int set_bw_thread_enable(struct device *dev, const char *buf, size_t n) ++{ ++ long idx=-1; ++ int i=0; ++ int ret; ++ ++ if (kstrtol(buf, 10, &idx) != 0 || idx<0 || idx >= 2 ) return -EINVAL; ++ ++ if(idx==1)//enable thread ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) //reset all bandwidth value ++ { ++ miu0_clients[i].bw_val_thread=0; ++ } ++ ++ if(pBWmonitorThread==NULL) ++ { ++ pBWmonitorThread = kthread_create(BW_monitor,(void *)&pBWmonitorThread,"BW Monitor"); ++ if (IS_ERR(pBWmonitorThread)) ++ { ++ ret = PTR_ERR(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ return ret; ++ } ++ wake_up_process(pBWmonitorThread); ++ } ++ } ++ else if (idx==0 && (pBWmonitorThread!=NULL))//disable thread ++ { ++ kthread_stop(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ } ++ return n; ++} ++ ++ ++static ssize_t bw_thread_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return set_bw_thread_enable(dev,buf,n); ++} ++ ++ ++static ssize_t bw_thread_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ //read from bw register and saved back to bw_val ++ str += scnprintf(str, end - str, "%2d:%s[0x%04X] BW_val_thread=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id,miu0_clients[i].bw_val_thread,miu0_clients[i].bw_val_thread*100/1024, ++ (miu0_clients[i].bw_val_thread*10000/1024)%100); ++ ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++DEVICE_ATTR(bw_thread, 0644, bw_thread_show, bw_thread_store); ++*/ ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++//DEVICE_ATTR(measure_max_bandwidth, 0444, measure_bandwidth_MAX_show, NULL); ++//DEVICE_ATTR(measure_avg_bandwidth, 0444, measure_bandwidth_AVG_show, NULL); ++//DEVICE_ATTR(measure_avg_efficiency, 0444, measure_efficiency_AVG_show, NULL); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++ ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret; ++ ++ miu0.index=0; ++ miu0.dev.kobj.name="miu0"; ++ miu0.dev.bus=&miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ++ ret=device_register(&miu0.dev); ++ ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_disable); ++ //device_create_file(&miu0.dev, &dev_attr_bw_thread); ++ ++ //device_create_file(&miu0.dev, &dev_attr_measure_max_bandwidth); ++ //device_create_file(&miu0.dev, &dev_attr_measure_avg_bandwidth); ++ //device_create_file(&miu0.dev, &dev_attr_measure_avg_efficiency); ++ device_create_file(&miu0.dev, &dev_attr_measure_all); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_duration_ms); ++ ++ //mutex_init(&bw_monitor_mutex); ++} +diff --git a/arch/arm/mach-sstar/infinity3/pm.c b/arch/arm/mach-sstar/infinity3/pm.c +new file mode 100755 +index 000000000000..9537114f8e15 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity3/pm.c +@@ -0,0 +1,80 @@ ++/* ++* pm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void sram_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&sram_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity3/soc.c b/arch/arm/mach-sstar/infinity3/soc.c +new file mode 100755 +index 000000000000..2e3b1f1336f0 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity3/soc.c +@@ -0,0 +1,659 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ //{IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "mstar,infinity3", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++ ++ ++//extern struct timecounter *arch_timer_get_timecounter(void); ++ ++ ++static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ volatile unsigned long dwLockFlag = 0; ++ volatile unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ dsb(); ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++/*//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NAND BIT2 ++#define STORAGE_EMMC BIT3 ++#define STORAGE_P_NAND BIT4 ++#define STORAGE_SPI_NOR BIT5 ++*/ ++ u8 type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & 0x3C); ++ ++ if(BIT4 == type) ++ return (int)MS_STORAGE_NAND; ++ else if(BIT5 == type) ++ return (int)MS_STORAGE_NOR; ++ else if(BIT3 == type) ++ return (int)MS_STORAGE_EMMC; ++ else if(BIT2 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int mstar_get_package_type(void) ++{ ++ if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S01A")) ++ return MS_I3_PACKAGE_BGA_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S02A-256M") || !strcmp(&mstar_soc_dev_attr.machine[10], "MSC250C")) ++ return MS_I3_PACKAGE_DDR3_1866_256MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S04A")) ++ return MS_I3_PACKAGE_QFN_DDR3_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S03A-64M")) ++ return MS_I3_PACKAGE_QFN_DDR2_64MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "FPGA")) ++ return MS_I3_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I3_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]="I3"; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ static int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ if(param<0 || param>1) ++ { ++ printk(KERN_ERR "[%s] param invalid\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ np = of_find_node_by_path("/soc/Mstar-ehci-1"); ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == param) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == param) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ u64 cycles=arch_timer_read_counter(); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ us_ticks_cycle_offset=arch_timer_read_counter(); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++ default: ++ printk(KERN_ERR "Unsupport CHIP_FUNCTION!! ID=%d\n",function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsbchip->phys_to_miu=mstar_phys_to_MIU; ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++struct mcm_client{ ++ char* name; ++ short index; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, 0}, ++ {"VHE", MCM_ID_VHE, 0}, ++ {"MFE", MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, 0}, ++ {"AESDMA", MCM_ID_AESDMA, 0}, ++ {"UHC", MCM_ID_UHC, 0}, ++ {"EMAC", MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, 0}, ++ {"GOP", MCM_ID_GOP, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, 0}, ++ {"*ALL_CLIENTS*", MCM_ID_ALL, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ return 0; ++ } ++ else if(index == MCM_ID_MCU51) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x0; ++ else if (index == MCM_ID_URDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x1; ++ else if (index == MCM_ID_BDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x4; ++ else if (index == MCM_ID_VHE) ++ addr = BASE_REG_MCM_VHE_GP_PA + 0x0; ++ else if (index == MCM_ID_MFE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x0; ++ else if (index == MCM_ID_JPE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1; ++ else if (index == MCM_ID_BACH) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x4; ++ else if (index == MCM_ID_AESDMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x5; ++ else if (index == MCM_ID_UHC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x8; ++ else if (index == MCM_ID_EMAC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x9; ++ else if (index == MCM_ID_CMDQ) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xC; ++ else if (index == MCM_ID_ISP_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xD; ++ else if (index == MCM_ID_ISP_DMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x10; ++ else if (index == MCM_ID_GOP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x11; ++ else if (index == MCM_ID_SC_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x14; ++ else if (index == MCM_ID_SC_DNR_SAD) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x15; ++ else if (index == MCM_ID_SC_CROP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x18; ++ else if (index == MCM_ID_SC1_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x19; ++ else if (index == MCM_ID_SC1_SNP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1C; ++ else if (index == MCM_ID_SC1_DBG) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1D; ++ else if (index == MCM_ID_SC2_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x20; ++ else if (index == MCM_ID_SC3_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x21; ++ else if (index == MCM_ID_FCIE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x24; ++ else if (index == MCM_ID_SDIO) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x25; ++ else if (index == MCM_ID_SC1_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x28; ++ else if (index == MCM_ID_SC2_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x29; ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++ ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++ mstar_create_MCM_node(); ++} ++ ++static void global_reset(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = global_reset, ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity3/sram.S b/arch/arm/mach-sstar/infinity3/sram.S +new file mode 100755 +index 000000000000..464b0fa4a07d +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity3/sram.S +@@ -0,0 +1,191 @@ ++/* ++* sram.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl sram_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(sram_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(sram_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity5/Kconfig b/arch/arm/mach-sstar/infinity5/Kconfig +new file mode 100644 +index 000000000000..dac4bc605e84 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/Kconfig +@@ -0,0 +1,16 @@ ++config ARCH_INFINITY5 ++ bool "SoC iNfinity5 (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity5 SoC ++ ++config INFINITY5_FPGA ++ bool "iNfinity5 FPGA environment" if ARCH_INFINITY5 ++ depends on ARCH_INFINITY5 ++ help ++ Support for iNfinity5 FPGA environment +diff --git a/arch/arm/mach-sstar/infinity5/Makefile b/arch/arm/mach-sstar/infinity5/Makefile +new file mode 100755 +index 000000000000..19aab88cff94 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/Makefile +@@ -0,0 +1,8 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += soc.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o miu_arb.o +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity5/miu_arb.c b/arch/arm/mach-sstar/infinity5/miu_arb.c +new file mode 100755 +index 000000000000..b9d30d881b3e +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/miu_arb.c +@@ -0,0 +1,1163 @@ ++/* ++* miu_arb.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Alterman.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "miu_bw.h" ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_burst { ++ short len; ++ short idx; ++}; ++ ++struct miu_policy { ++ char *name; ++ char idx; ++}; ++ ++struct miu_reg_addr { ++ u32 flowctrl0; ++ u32 flowctrl1; ++ u32 priority0; ++ u32 priority1; ++ u32 nolimit; ++ u32 burst0; ++ u32 burst1; ++ u32 ctrl; ++ u32 promote; ++}; ++ ++struct miu_reg_val { ++ u32 flowctrl; ++ u32 priority; ++ u32 burst; ++ u16 nolimit; ++ u16 ctrl; ++ u16 promote; ++}; ++ ++struct miu_policy_tbl { ++ struct miu_reg_val val[MIU_NUM][MIU_GRP_NUM]; ++}; ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_device miu_arb_dev[MIU_NUM]; ++static struct miu_arb arb_policy[MIU_NUM]; ++const static struct miu_burst burst_map[MIU_ARB_BURST_OPT] = ++{ ++ // keep the last option for no limit, length 0 means no limit ++ {8, 0}, {16, 1}, {32, 2}, {64, 3}, {0, MIU_ARB_BURST_NOLIM} ++}; ++static int _cur_policy = 0; ++const static struct miu_policy policy_map[MIU_ARB_POLICY_NUM] = ++{ ++ {"round-robin", MIU_ARB_POLICY_RR}, ++ {"real-time", MIU_ARB_POLICY_RT}, ++}; ++const static struct miu_reg_addr reg_tbl[MIU_GRP_NUM] = ++{ ++ {(REG_ID_0A),(REG_ID_0B),(REG_ID_0C),(REG_ID_0D),(REG_ID_0E),(REG_ID_12),(REG_ID_13),(REG_ID_18),(REG_ID_1C)}, ++ {(REG_ID_2A),(REG_ID_2B),(REG_ID_2C),(REG_ID_2D),(REG_ID_2E),(REG_ID_32),(REG_ID_33),(REG_ID_38),(REG_ID_3C)}, ++ {(REG_ID_4A),(REG_ID_4B),(REG_ID_4C),(REG_ID_4D),(REG_ID_4E),(REG_ID_52),(REG_ID_53),(REG_ID_58),(REG_ID_5C)}, ++ {(REG_ID_6A),(REG_ID_6B),(REG_ID_6C),(REG_ID_6D),(REG_ID_6E),(REG_ID_72),(REG_ID_73),(REG_ID_78),(REG_ID_7C)}, ++}; ++// round-robin policy ++static struct miu_policy_tbl policy_rr = ++{ ++ { ++ // miu0 ++ { ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ }, ++ // miu1 ++ { ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ {0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x0000, 0xC005, 0xFFFF}, ++ }, ++ } ++}; ++// real-time path policy ++static struct miu_policy_tbl policy_rt = ++{ ++ { ++ // miu0 ++ { ++ {0x8021FF99, 0xA0AEA2BE, 0xAAA2AA82, 0x3020, 0xC305, 0xFDF9}, ++ {0x0000FFCC, 0xABEAA8A2, 0xA82AAAAE, 0x0002, 0xC105, 0xE7FF}, ++ {0x00000000, 0xAAB80A0A, 0xAA8ABAFA, 0x01CC, 0xC005, 0xFBFF}, ++ {0x10324800, 0xAAAAAAF3, 0xAAAAAA0C, 0x0002, 0xC305, 0xFFF0}, ++ }, ++ // miu1 ++ { ++ {0x8021FF99, 0xA0AEA2BE, 0xAAA2AA82, 0x3020, 0xC305, 0xFDF9}, ++ {0x0000FFCC, 0xABEAA8A2, 0xA82AAAAE, 0x0002, 0xC105, 0xE7FF}, ++ {0x00000000, 0xAAB80A0A, 0xAA8ABAFA, 0x01CC, 0xC005, 0xFBFF}, ++ {0x10324800, 0xAAAAAAF3, 0xAAAAAA0C, 0x0002, 0xC305, 0xFFF0}, ++ }, ++ } ++}; ++static struct miu_policy_tbl *arb_setting[MIU_ARB_POLICY_NUM] = ++{ ++ &policy_rr, &policy_rt ++}; ++ ++static struct miu_policy_tbl policy_cur; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++ ++static void _set_priority(unsigned char miu, int client, char pri) ++{ ++ int base; ++ int g, c, ofst; ++ struct miu_reg_val *val; ++ ++ // update reg ++ g = client / MIU_GRP_CLIENT_NUM; ++ c = client % MIU_GRP_CLIENT_NUM; ++ ofst = c << 1; ++ val = &(policy_cur.val[miu][g]); ++ val->priority = (val->priority & ~(0x3 << ofst)) | (pri << ofst); ++ ++ base = (miu == 0) ? BASE_REG_MIU_ARB_E_PA : BASE_REG_MIU1_ARB_E_PA; ++ OUTREG16((base+reg_tbl[g].priority0), val->priority & 0xFFFF); ++ OUTREG16((base+reg_tbl[g].priority1), val->priority >> 16); ++} ++ ++static void _set_burst(unsigned char miu, int client, char burst) ++{ ++ int base; ++ int g, c, ofst, i = 0, idx = 0; ++ struct miu_reg_val *val; ++ ++ do { ++ if (burst_map[i].len == burst) ++ { ++ idx = burst_map[i].idx; ++ break; ++ } ++ i++; ++ } while(i < MIU_ARB_BURST_OPT); ++ ++ // update reg ++ g = client / MIU_GRP_CLIENT_NUM; ++ c = client % MIU_GRP_CLIENT_NUM; ++ ofst = c << 1; ++ val = &(policy_cur.val[miu][g]); ++ if (idx == MIU_ARB_BURST_NOLIM) ++ { ++ val->burst = (val->burst & ~(0x3 << ofst)); ++ val->nolimit |= (1 << c); ++ } ++ else { ++ val->burst = (val->burst & ~(0x3 << ofst)) | (idx << ofst); ++ val->nolimit &= ~(1 << c); ++ } ++ ++ base = (miu == 0) ? BASE_REG_MIU_ARB_E_PA : BASE_REG_MIU1_ARB_E_PA; ++ OUTREG16((base+reg_tbl[g].burst0), val->burst & 0xFFFF); ++ OUTREG16((base+reg_tbl[g].burst1), val->burst >> 16); ++ OUTREG16((base+reg_tbl[g].nolimit), val->nolimit); ++} ++ ++static void _set_promote(unsigned char miu, int client, char promote) ++{ ++ int base; ++ int g, c; ++ struct miu_reg_val *val; ++ ++ // update reg ++ g = client / MIU_GRP_CLIENT_NUM; ++ c = client % MIU_GRP_CLIENT_NUM; ++ val = &(policy_cur.val[miu][g]); ++ if (promote) ++ { ++ val->promote |= (1 << c); ++ } ++ else { ++ val->promote &= ~(1 << c); ++ } ++ ++ base = (miu == 0) ? BASE_REG_MIU_ARB_E_PA : BASE_REG_MIU1_ARB_E_PA; ++ OUTREG16((base+reg_tbl[g].promote), val->promote); ++} ++ ++static void _set_flowctrl(unsigned char miu, int grp, struct arb_flowctrl *fctrl) ++{ ++ int base; ++ struct miu_reg_val *val; ++ ++ val = &(policy_cur.val[miu][grp]); ++ ++ // if only ID1 enabled, swap ID0 & ID1 ++ if (MIU_ARB_GET_CNT_EN(fctrl->cnt0_enable)) ++ { ++ if (!MIU_ARB_GET_CNT_ID0_EN(fctrl->cnt0_enable)) ++ { ++ MIU_ARB_SET_CNT_ID0(fctrl->cnt0_id, MIU_ARB_GET_CNT_ID1(fctrl->cnt0_id)); ++ MIU_ARB_SET_CNT_ID0_EN(fctrl->cnt0_enable, 1); ++ MIU_ARB_SET_CNT_ID1_EN(fctrl->cnt0_enable, 0); ++ } ++ if (!MIU_ARB_GET_CNT_ID1_EN(fctrl->cnt0_enable)) ++ { ++ // only ID0 enabled, set ID1 as ID0 ++ MIU_ARB_SET_CNT_ID1(fctrl->cnt0_id, MIU_ARB_GET_CNT_ID0(fctrl->cnt0_id)); ++ } ++ val->flowctrl = (val->flowctrl & ~(0xFFFF)) | fctrl->cnt0_id | (fctrl->cnt0_period << 8); ++ } ++ if (MIU_ARB_GET_CNT_EN(fctrl->cnt1_enable)) ++ { ++ if (!MIU_ARB_GET_CNT_ID0_EN(fctrl->cnt1_enable)) ++ { ++ MIU_ARB_SET_CNT_ID0(fctrl->cnt1_id, MIU_ARB_GET_CNT_ID1(fctrl->cnt1_id)); ++ MIU_ARB_SET_CNT_ID0_EN(fctrl->cnt1_enable, 1); ++ MIU_ARB_SET_CNT_ID1_EN(fctrl->cnt1_enable, 0); ++ } ++ if (!MIU_ARB_GET_CNT_ID1_EN(fctrl->cnt1_enable)) ++ { ++ // only ID0 enabled, set ID1 as ID0 ++ MIU_ARB_SET_CNT_ID1(fctrl->cnt1_id, MIU_ARB_GET_CNT_ID0(fctrl->cnt1_id)); ++ } ++ val->flowctrl = (val->flowctrl & ~(0xFFFF0000)) | (fctrl->cnt1_id << 16) | (fctrl->cnt1_period << 24); ++ } ++ ++ // update reg ++ base = (miu == 0) ? BASE_REG_MIU_ARB_E_PA : BASE_REG_MIU1_ARB_E_PA; ++ OUTREG16((base+reg_tbl[grp].flowctrl0), val->flowctrl & 0xFFFF); ++ OUTREG16((base+reg_tbl[grp].flowctrl1), val->flowctrl >> 16); ++ val->ctrl &= ~(0x0300); ++ if (MIU_ARB_GET_CNT_EN(fctrl->cnt0_enable)) ++ { ++ val->ctrl |= 0x0100; ++ } ++ if (MIU_ARB_GET_CNT_EN(fctrl->cnt1_enable)) ++ { ++ val->ctrl |= 0x0200; ++ } ++ OUTREG16((base+reg_tbl[grp].ctrl), val->ctrl); ++} ++ ++static bool _flowctrl_is_enable(unsigned char miu, short client, unsigned char *period) ++{ ++ int g, i; ++ struct arb_flowctrl *f; ++ ++ g = client / MIU_GRP_CLIENT_NUM; ++ i = client % MIU_GRP_CLIENT_NUM; ++ f = &arb_policy[miu].fctrl[g]; ++ ++ *period = 0; ++ if (MIU_ARB_GET_CNT_ID0_EN(f->cnt0_enable) && (MIU_ARB_GET_CNT_ID0(f->cnt0_id) == i)) ++ { ++ *period = f->cnt0_period; ++ return 1; ++ } ++ else if (MIU_ARB_GET_CNT_ID1_EN(f->cnt0_enable) && (MIU_ARB_GET_CNT_ID1(f->cnt0_id) == i)) ++ { ++ *period = f->cnt0_period; ++ return 1; ++ } ++ else if (MIU_ARB_GET_CNT_ID0_EN(f->cnt1_enable) && (MIU_ARB_GET_CNT_ID0(f->cnt1_id) == i)) ++ { ++ *period = f->cnt1_period; ++ return 1; ++ } ++ else if (MIU_ARB_GET_CNT_ID1_EN(f->cnt1_enable) && (MIU_ARB_GET_CNT_ID1(f->cnt1_id) == i)) ++ { ++ *period = f->cnt1_period; ++ return 1; ++ } ++ return 0; ++} ++ ++static bool _flowctrl_enable(unsigned char miu, short client, bool enable, char period) ++{ ++ int g, i; ++ struct arb_flowctrl *f; ++ ++ g = client / MIU_GRP_CLIENT_NUM; ++ i = client % MIU_GRP_CLIENT_NUM; ++ f = &arb_policy[miu].fctrl[g]; ++ ++ if (enable) ++ { ++ do { ++ // enabled group flow control cnt0 has the same period ++ if (MIU_ARB_GET_CNT_EN(f->cnt0_enable) && (f->cnt0_period == period)) ++ { ++ if (!MIU_ARB_GET_CNT_ID0_EN(f->cnt0_enable)) ++ { ++ //id0 not used ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt0_enable, 1); ++ MIU_ARB_SET_CNT_ID0(f->cnt0_id, i); ++ break; ++ } ++ else if (!MIU_ARB_GET_CNT_ID1_EN(f->cnt0_enable)) ++ { ++ //id1 not used ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt0_enable, 1); ++ MIU_ARB_SET_CNT_ID1(f->cnt0_id, i); ++ break; ++ } ++ } ++ // enabled group flow control cnt1 has the same period ++ if (MIU_ARB_GET_CNT_EN(f->cnt1_enable) && (f->cnt1_period == period)) ++ { ++ if (!MIU_ARB_GET_CNT_ID0_EN(f->cnt1_enable)) ++ { ++ //id0 not used ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt1_enable, 1); ++ MIU_ARB_SET_CNT_ID0(f->cnt1_id, i); ++ break; ++ } ++ else if (!MIU_ARB_GET_CNT_ID1_EN(f->cnt1_enable)) ++ { ++ //id1 not used ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt1_enable, 1); ++ MIU_ARB_SET_CNT_ID1(f->cnt1_id, i); ++ break; ++ } ++ } ++ if (!MIU_ARB_GET_CNT_EN(f->cnt0_enable)) ++ { ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt0_enable, 1); ++ f->cnt0_period = period; ++ MIU_ARB_SET_CNT_ID0(f->cnt0_id, i); ++ break; ++ } ++ if (!MIU_ARB_GET_CNT_EN(f->cnt1_enable)) ++ { ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt1_enable, 1); ++ f->cnt1_period = period; ++ MIU_ARB_SET_CNT_ID0(f->cnt1_id, i); ++ break; ++ } ++ return 1; // not free one, failed ++ ++ } while(1); ++ } ++ else ++ { ++ // disable client flow control ++ if (MIU_ARB_GET_CNT_ID0_EN(f->cnt0_enable) && (MIU_ARB_GET_CNT_ID0(f->cnt0_id) == i)) ++ { ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt0_enable, 0); ++ } ++ else if (MIU_ARB_GET_CNT_ID1_EN(f->cnt0_enable) && (MIU_ARB_GET_CNT_ID1(f->cnt0_id) == i)) ++ { ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt0_enable, 0); ++ } ++ else if (MIU_ARB_GET_CNT_ID0_EN(f->cnt1_enable) && (MIU_ARB_GET_CNT_ID0(f->cnt1_id) == i)) ++ { ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt1_enable, 0); ++ } ++ else if (MIU_ARB_GET_CNT_ID1_EN(f->cnt1_enable) && (MIU_ARB_GET_CNT_ID1(f->cnt1_id) == i)) ++ { ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt1_enable, 0); ++ } ++ else ++ { ++ //nothing changed ++ return 0; ++ } ++ } ++ _set_flowctrl(miu, g, f); ++ ++ return 0; ++} ++ ++static char *_dump_as_text(char *str, char *end, unsigned char miu) ++{ ++ int c; ++ unsigned char period; ++ ++ str += scnprintf(str, end - str, "Num:IP_name [pri][burst][promote][ctrlflow]\n"); ++ for(c = 1; c < MIU_ARB_CLIENT_NUM; c++) // skip client 0 ++ { ++ if (!miu_client_reserved(c)) ++ { ++ if (!_flowctrl_is_enable(miu, c, &period)) ++ { ++ str += scnprintf(str, end - str, "%3d:%s %d %2d %d\n", ++ c, miu_client_id_to_name(c), ++ arb_policy[miu].priority[c], ++ arb_policy[miu].burst[c], ++ arb_policy[miu].promote[c]); ++ } ++ else { ++ str += scnprintf(str, end - str, "%3d:%s %d %2d %d 0x%02X\n", ++ c, miu_client_id_to_name(c), ++ arb_policy[miu].priority[c], ++ arb_policy[miu].burst[c], ++ arb_policy[miu].promote[c], ++ period); ++ } ++ } ++ } ++ return str; ++} ++ ++static char *_dump_as_reg(char *str, char *end, unsigned char miu) ++{ ++ int g; ++ struct miu_reg_val *val; ++ ++ // miu0 ++ str += scnprintf(str, end - str, " // miu%d\n", miu); ++ str += scnprintf(str, end - str, " {\n"); ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ val = &(policy_cur.val[miu][g]); ++ str += scnprintf(str, end - str, ++ " {0x%08X, 0x%08X, 0x%08X, 0x%04X, 0x%04X, 0x%04X},\n", ++ val->flowctrl, val->priority, val->burst, val->nolimit, val->ctrl, val->promote); ++ } ++ str += scnprintf(str, end - str, " },\n"); ++ ++ return str; ++} ++ ++static void _load_miu_arb(int miu, int grp, struct miu_reg_val *val) ++{ ++ int c, i; ++ struct arb_flowctrl *f; ++ ++ c = grp * MIU_GRP_CLIENT_NUM; ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ arb_policy[miu].priority[c] = (val->priority >> (i<<1)) & 0x3; ++ if (val->nolimit & (1 << i)) ++ { ++ arb_policy[miu].burst[c] = 0; ++ } ++ else { ++ arb_policy[miu].burst[c] = burst_map[(val->burst >> (i<<1)) & 0x3].len; ++ } ++ if (val->promote & (1 << i)) ++ { ++ arb_policy[miu].promote[c] = 1; ++ } ++ else { ++ arb_policy[miu].promote[c] = 0; ++ } ++ c++; ++ } ++ f = &arb_policy[miu].fctrl[grp]; ++ if (val->ctrl & 0x0100) ++ { ++ f->cnt0_id = val->flowctrl & 0xFF; ++ f->cnt0_period = (val->flowctrl >> 8) & 0xFF; ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt0_enable, 1); ++ // ID1 is identical with ID0 ++ if ((MIU_ARB_GET_CNT_ID0(f->cnt0_id)) == (MIU_ARB_GET_CNT_ID1(f->cnt0_id))) ++ { ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt0_enable, 0); ++ } ++ else { ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt0_enable, 1); ++ } ++ } ++ else { ++ MIU_ARB_SET_CNT_ID0(f->cnt0_id, 0); ++ MIU_ARB_SET_CNT_ID1(f->cnt0_id, 0); ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt0_enable, 0); ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt0_enable, 0); ++ f->cnt0_period = 0x00; ++ } ++ if (val->ctrl & 0x0200) ++ { ++ f->cnt1_id = (val->flowctrl >> 16) & 0xFF; ++ f->cnt1_period = (val->flowctrl >> 24) & 0xFF; ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt1_enable, 1); ++ if ((MIU_ARB_GET_CNT_ID0(f->cnt1_id)) == (MIU_ARB_GET_CNT_ID1(f->cnt1_id))) ++ { ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt1_enable, 0); ++ } ++ else { ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt1_enable, 1); ++ } ++ } ++ else { ++ MIU_ARB_SET_CNT_ID0(f->cnt1_id, 0); ++ MIU_ARB_SET_CNT_ID1(f->cnt1_id, 0); ++ MIU_ARB_SET_CNT_ID0_EN(f->cnt1_enable, 0); ++ MIU_ARB_SET_CNT_ID1_EN(f->cnt1_enable, 0); ++ f->cnt1_period = 0x00; ++ } ++} ++ ++static void _load_policy(int idx) ++{ ++ int base; ++ int m, g; ++ struct miu_reg_val *val; ++ ++ if (idx >= MIU_ARB_POLICY_NUM) ++ { ++ return; ++ } ++ memcpy(&policy_cur, arb_setting[idx], sizeof(struct miu_policy_tbl)); ++ ++ for(m = 0; m < MIU_NUM; m++) ++ { ++ base = (m == 0) ? BASE_REG_MIU_ARB_E_PA : BASE_REG_MIU1_ARB_E_PA; ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ // register settings ++ val = &(policy_cur.val[m][g]); ++ OUTREG16((base+reg_tbl[g].flowctrl0), val->flowctrl & 0xFFFF); ++ OUTREG16((base+reg_tbl[g].flowctrl1), val->flowctrl >> 16); ++ OUTREG16((base+reg_tbl[g].priority0), val->priority & 0xFFFF); ++ OUTREG16((base+reg_tbl[g].priority1), val->priority >> 16); ++ OUTREG16((base+reg_tbl[g].burst0), val->burst & 0xFFFF); ++ OUTREG16((base+reg_tbl[g].burst1), val->burst >> 16); ++ OUTREG16((base+reg_tbl[g].nolimit), val->nolimit); ++ OUTREG16((base+reg_tbl[g].ctrl), val->ctrl); ++ OUTREG16((base+reg_tbl[g].promote), val->promote); ++ // update readable info ++ _load_miu_arb(m, g, val); ++ } ++ } ++ _cur_policy = idx; ++} ++ ++static ssize_t client_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ u32 input = 0; ++ ++ if(!strncmp(buf, "all", strlen("all"))) ++ { ++ arb_policy[m].client_selected = MIU_ARB_CLIENT_ALL; ++ return count; ++ } ++ ++ input = simple_strtoul(buf, NULL, 10); ++ if (input < MIU_ARB_CLIENT_NUM) ++ { ++ arb_policy[m].client_selected = input; ++ } ++ else ++ { ++ printk(KERN_ERR "Invalid client %d\n", input); ++ return count; ++ } ++ return count; ++} ++ ++static ssize_t client_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int c, g, i; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name "); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + i; ++ if (c != arb_policy[m].client_selected) ++ { ++ if (!miu_client_reserved(c)) ++ { ++ str += scnprintf(str, end - str, "%3d:%s ", c, miu_client_id_to_name(c)); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%3d: ", c); ++ } ++ } ++ else { ++ str += scnprintf(str, end - str, ASCII_COLOR_GREEN"%3d:%s "ASCII_COLOR_END, c, miu_client_id_to_name(c)); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(client, 0644, client_show, client_store); ++ ++static ssize_t priority_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c; ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ if (input > MIU_ARB_PRIO_4TH) ++ { ++ printk(KERN_ERR "Invalid priority %d\n", input); ++ return count; ++ } ++ c = arb_policy[m].client_selected; ++ if (c != MIU_ARB_CLIENT_ALL) ++ { ++ if (!miu_client_reserved(c)) ++ { ++ arb_policy[m].priority[c] = input; ++ _set_priority(m, c, input); ++ } ++ } ++ else ++ { ++ // all clients set to the same priority ++ for (c = 0; c < MIU_ARB_CLIENT_NUM; c++) ++ { ++ arb_policy[m].priority[c] = input; ++ _set_priority(m, c, input); ++ } ++ } ++ return count; ++} ++ ++static ssize_t priority_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int c; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Priority (highest -> lowest):\n"); ++ str += scnprintf(str, end - str, "0, 1, 2, 3\n\n"); ++ ++ c = arb_policy[m].client_selected; ++ if (c != MIU_ARB_CLIENT_ALL) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [pri]\n"); ++ str += scnprintf(str, end - str, "%3d:%s[ %d]\n", c, miu_client_id_to_name(c), arb_policy[m].priority[c]); ++ } ++ else ++ { ++ int g, i; ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name "); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + i; ++ if (!miu_client_reserved(c)) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[%d] ", c, miu_client_id_to_name(c), arb_policy[m].priority[c]); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%3d: ", c); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(priority, 0644, priority_show, priority_store); ++ ++static ssize_t burst_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c, i = 0, burst = 0xFFFF; ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ do { ++ if (burst_map[i].len == input) ++ { ++ burst = input; ++ break; ++ } ++ } while(++i < MIU_ARB_BURST_OPT); ++ if (burst == 0xFFFF) ++ { ++ printk(KERN_ERR "Invalid burst %d\n", input); ++ return count; ++ } ++ ++ c = arb_policy[m].client_selected; ++ printk(KERN_ERR "set client %d burst %d\n", c, input); ++ if (c != MIU_ARB_CLIENT_ALL) ++ { ++ if (!miu_client_reserved(c)) ++ { ++ arb_policy[m].burst[c] = burst; ++ _set_burst(m, c, burst); ++ } ++ } ++ else ++ { ++ // all clients set to the same burst ++ for (c = 0; c < MIU_ARB_CLIENT_NUM; c++) ++ { ++ arb_policy[m].burst[c] = burst; ++ _set_burst(m, c, burst); ++ } ++ } ++ return count; ++} ++ ++static ssize_t burst_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i, c; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Burst Option:\n"); ++ for(i = 0; i < MIU_ARB_BURST_NOLIM; i++) ++ { ++ str += scnprintf(str, end - str, " %d,", burst_map[i].len); ++ } ++ str += scnprintf(str, end - str, " %d(No Limited)\n\n", burst_map[MIU_ARB_BURST_NOLIM].len); ++ ++ c = arb_policy[m].client_selected; ++ if (c != MIU_ARB_CLIENT_ALL) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [burst]\n"); ++ if (arb_policy[m].burst[c] == burst_map[MIU_ARB_BURST_NOLIM].len) ++ { ++ str += scnprintf(str, end - str, "%3d:%s"ASCII_COLOR_RED"[ %2d]"ASCII_COLOR_END, ++ c, miu_client_id_to_name(c), arb_policy[m].burst[c]); ++ } ++ else { ++ str += scnprintf(str, end - str, "%3d:%s[ %2d]", c, miu_client_id_to_name(c), arb_policy[m].burst[c]); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ else ++ { ++ int g; ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name "); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + i; ++ if (!miu_client_reserved(c)) ++ { ++ if (arb_policy[m].burst[c] != burst_map[MIU_ARB_BURST_NOLIM].len) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[ %2d] ", ++ c, miu_client_id_to_name(c), arb_policy[m].burst[c]); ++ } ++ else { ++ str += scnprintf(str, end - str, "%3d:%s"ASCII_COLOR_RED"[ %2d] "ASCII_COLOR_END, ++ c, miu_client_id_to_name(c), arb_policy[m].burst[c]); ++ } ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%3d: ", c); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(burst, 0644, burst_show, burst_store); ++ ++static ssize_t promote_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c; ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ input = input ? 1 : 0; ++ ++ c = arb_policy[m].client_selected; ++ if (c != MIU_ARB_CLIENT_ALL) ++ { ++ if (!miu_client_reserved(c)) ++ { ++ arb_policy[m].promote[c] = input; ++ _set_promote(m, c, input); ++ } ++ } ++ else ++ { ++ // all clients set to the same promote ++ for (c = 0; c < MIU_ARB_CLIENT_NUM; c++) ++ { ++ arb_policy[m].promote[c] = input; ++ _set_promote(m, c, input); ++ } ++ } ++ return count; ++} ++ ++static ssize_t promote_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int c; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Promote Setting:\n"); ++ str += scnprintf(str, end - str, "0 -> disable\n"); ++ str += scnprintf(str, end - str, "1 -> enable\n\n"); ++ ++ c = arb_policy[m].client_selected; ++ if (c != MIU_ARB_CLIENT_ALL) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [promote]\n"); ++ str += scnprintf(str, end - str, "%3d:%s[ %d]\n", c, miu_client_id_to_name(c), arb_policy[m].promote[c]); ++ } ++ else ++ { ++ int i, g; ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name "); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + i; ++ if (!miu_client_reserved(c)) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[%d] ", c, miu_client_id_to_name(c), arb_policy[m].promote[c]); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%3d: ", c); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(promote, 0644, promote_show, promote_store); ++ ++static ssize_t flowctrl_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c; ++ ssize_t ret = count; ++ u32 enable, period, en_tmp; ++ unsigned char peri_tmp; ++ char *pt, *opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ c = arb_policy[m].client_selected; ++ if ((c == MIU_ARB_CLIENT_ALL) || (c >= MIU_ARB_CLIENT_NUM) || miu_client_reserved(c)) ++ return count; ++ ++ // check input parameters ++ do { ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ if ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ enable = simple_strtoul(opt, NULL, 10); ++ if (enable) ++ { ++ if ((opt = strsep(&pt, ";, ")) == NULL) ++ { ++ ret = 0; ++ break; ++ } ++ period = simple_strtoul(opt, NULL, 10); ++ if (!period || (period > MIU_ARB_CNT_PERIOD_MAX)) ++ { ++ printk(KERN_ERR "Invalid period %d (1-%d)\n", period, MIU_ARB_CNT_PERIOD_MAX); ++ ret = 0; ++ break; ++ } ++ } ++ } ++ else { ++ ret = 0; ++ } ++ break; ++ }while(1); ++ ++ kfree(pt); ++ if (ret == 0) ++ { ++ printk(KERN_ERR "Usage: echo [0/1] [period] > flowctrl\n"); ++ return count; ++ } ++ ++ if (enable) ++ { ++ // to keep the original setting ++ en_tmp = _flowctrl_is_enable(m, c, &peri_tmp); ++ _flowctrl_enable(m, c, 0, 0); ++ // restore the original settings if failed ++ if (_flowctrl_enable(m, c, enable, period) && en_tmp) ++ { ++ _flowctrl_enable(m, c, en_tmp, peri_tmp); ++ } ++ } ++ else ++ { ++ // disable client flow control ++ _flowctrl_enable(m, c, 0, 0); ++ } ++ ++ return count; ++} ++ ++static ssize_t flowctrl_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int c, g; ++ struct arb_flowctrl *f; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Flow Control:\n"); ++ str += scnprintf(str, end - str, "echo [id] > client\n"); ++ str += scnprintf(str, end - str, "enable: echo 1 [period] > flowctrl\n"); ++ str += scnprintf(str, end - str, "disable: echo 0 > flowctrl\n"); ++ ++ str += scnprintf(str, end - str, "\nNum:IP_name [period]\n"); ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ f = &arb_policy[m].fctrl[g]; ++ if (MIU_ARB_GET_CNT_EN(f->cnt0_enable) || MIU_ARB_GET_CNT_EN(f->cnt1_enable)) ++ { ++ if (MIU_ARB_GET_CNT_ID0_EN(f->cnt0_enable)) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + MIU_ARB_GET_CNT_ID0(f->cnt0_id); ++ str += scnprintf(str, end - str, "%3d:%s[ 0x%02X]\n", c, miu_client_id_to_name(c), f->cnt0_period); ++ } ++ if (MIU_ARB_GET_CNT_ID1_EN(f->cnt0_enable)) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + MIU_ARB_GET_CNT_ID1(f->cnt0_id); ++ str += scnprintf(str, end - str, "%3d:%s[ 0x%02X]\n", c, miu_client_id_to_name(c), f->cnt0_period); ++ } ++ if (MIU_ARB_GET_CNT_ID0_EN(f->cnt1_enable)) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + MIU_ARB_GET_CNT_ID0(f->cnt1_id); ++ str += scnprintf(str, end - str, "%3d:%s[ 0x%02X]\n", c, miu_client_id_to_name(c), f->cnt1_period); ++ } ++ if (MIU_ARB_GET_CNT_ID1_EN(f->cnt1_enable)) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + MIU_ARB_GET_CNT_ID1(f->cnt1_id); ++ str += scnprintf(str, end - str, "%3d:%s[ 0x%02X]\n", c, miu_client_id_to_name(c), f->cnt1_period); ++ } ++ } ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(flowctrl, 0644, flowctrl_show, flowctrl_store); ++ ++static ssize_t dump_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ if (input >= MIU_ARB_DUMP_MAX) ++ { ++ printk(KERN_ERR "Invalid dump mode %d (0: text; 1: reg)\n", input); ++ return count; ++ } ++ arb_policy[m].dump = input; ++ return count; ++} ++ ++static ssize_t dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Dump Settings:\n"); ++ str += scnprintf(str, end - str, "text: echo 0 > dump\n"); ++ str += scnprintf(str, end - str, "reg : echo 1 > dump\n"); ++ str += scnprintf(str, end - str, "cat dump\n\n"); ++ ++ switch(arb_policy[m].dump) { ++ case MIU_ARB_DUMP_TEXT: ++ str = _dump_as_text(str, end, m); ++ break; ++ case MIU_ARB_DUMP_REG: ++ str = _dump_as_reg(str, end, m); ++ break; ++ default: ++ return 0; ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(dump, 0644, dump_show, dump_store); ++ ++static ssize_t policy_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ u32 input = 0, i; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ if (input >= MIU_ARB_POLICY_NUM) ++ { ++ printk(KERN_ERR "Invalid policy %d\n", input); ++ for(i = 0; i < MIU_ARB_POLICY_NUM; i++) ++ { ++ printk(KERN_ERR "%d: %s\n", policy_map[i].idx, policy_map[i].name); ++ } ++ return count; ++ } ++ _load_policy(input); ++ ++ return count; ++} ++ ++static ssize_t policy_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i; ++ ++ str += scnprintf(str, end - str, "Policy:\n"); ++ for(i = 0; i < MIU_ARB_POLICY_NUM; i++) ++ { ++ if (i == _cur_policy) ++ { ++ str += scnprintf(str, end - str, ASCII_COLOR_GREEN"%d: %s\n"ASCII_COLOR_END, policy_map[i].idx, policy_map[i].name); ++ } ++ else { ++ str += scnprintf(str, end - str, "%d: %s\n", policy_map[i].idx, policy_map[i].name); ++ } ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(policy, 0644, policy_show, policy_store); ++ ++void create_miu_bw_node(struct bus_type *miu_subsys) ++{ ++ int ret = 0, i; ++ ++ memset(arb_policy, 0, sizeof(arb_policy)); ++ ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ strcpy(arb_policy[i].name, "miu_arb0"); ++ arb_policy[i].name[7] += i; ++ ++ miu_arb_dev[i].index = 0; ++ miu_arb_dev[i].dev.kobj.name = (const char *)arb_policy[i].name; ++ miu_arb_dev[i].dev.bus = miu_subsys; ++ ++ ret = device_register(&miu_arb_dev[i].dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register %s device!! %d\n",miu_arb_dev[i].dev.kobj.name,ret); ++ return; ++ } ++ ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_client); ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_priority); ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_burst); ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_promote); ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_flowctrl); ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_dump); ++ device_create_file(&miu_arb_dev[i].dev, &dev_attr_policy); ++ } ++ _load_policy(MIU_ARB_POLICY_RT); ++ ++ //adjust group 3 to lowest priority, all groups have same burst length ++ OUTREG16(BASE_REG_MIU_ARB_B_PA + REG_ID_27, 0xC0); ++ OUTREG16(BASE_REG_MIU_ARB_B_PA + REG_ID_31, 0x8080); ++ OUTREG16(BASE_REG_MIU_ARB_B_PA + REG_ID_32, 0xAA); ++ OUTREG16(BASE_REG_MIU_ARB_B_PA + REG_ID_2E, 0x00); ++ OUTREG16(BASE_REG_MIU1_ARB_B_PA + REG_ID_27, 0xC0); ++ OUTREG16(BASE_REG_MIU1_ARB_B_PA + REG_ID_31, 0x8080); ++ OUTREG16(BASE_REG_MIU1_ARB_B_PA + REG_ID_32, 0xAA); ++ OUTREG16(BASE_REG_MIU1_ARB_B_PA + REG_ID_2E, 0x00); ++ //VEN_W high priority enable ++ OUTREG16(BASE_REG_MIU_ARB_E_PA + REG_ID_64, 0xFFFD); ++ OUTREG16(BASE_REG_MIU1_ARB_E_PA + REG_ID_64, 0xFFFD); ++} +diff --git a/arch/arm/mach-sstar/infinity5/miu_bw.c b/arch/arm/mach-sstar/infinity5/miu_bw.c +new file mode 100755 +index 000000000000..7a02f683404e +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/miu_bw.c +@@ -0,0 +1,807 @@ ++/* ++* miu_bw.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "miu_bw.h" ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_client miu_clients[MIU_CLIENT_NUM] = ++{ ++ {"OVERALL ",0x00,0}, ++ {"DIP0_R ",0x01,0}, ++ {"DIP0_W ",0x02,0}, ++ {"LDC_R ",0x03,0}, ++ {"SC2_FRM_W ",0x04,0}, ++ {"SC3_FRM ",0x05,0}, ++ {"RSC_R ",0x06,0}, ++ {"SC1_DBG_R ",0x07,0}, ++ {"CMDQ0_R ",0x08,0}, ++ {"MOVDMA0 ",0x09,0}, ++ {"EMAC ",0x0A,0}, ++ {"2DGE ",0x0B,0}, ++ {"3DNR0_R ",0x0C,0}, ++ {"3DNR0_W ",0x0D,0}, ++ {"GOP4_R ",0x0E,0}, ++ {"RSVD ",0x0F,1}, ++ {"ISP_DMAG0 ",0x10,0}, ++ {"ISP_DMAG1 ",0x11,0}, ++ {"ISP_DMAG2 ",0x12,0}, ++ {"GOP2_R ",0x13,0}, ++ {"GOP3_R ",0x14,0}, ++ {"ISP_DMAG ",0x15,0}, ++ {"ISP_STA ",0x16,0}, ++ {"ISP_STA1_W",0x17,0}, ++ {"CMDQ1_R ",0x18,0}, ++ {"MOVDMA1 ",0x19,0}, ++ {"MCU51 ",0x1A,0}, ++ {"DLA ",0x1B,0}, ++ {"IVE ",0x1C,0}, ++ {"RSVD ",0x1D,1}, ++ {"RSVD ",0x1E,1}, ++ {"RSVD ",0x1F,1}, ++ {"RSVD ",0x20,1}, ++ {"SC_ROT_R ",0x21,0}, ++ {"SC_AIP_W ",0x22,0}, ++ {"SC0_FRM_W ",0x23,0}, ++ {"SC0_SNP_W ",0x24,0}, ++ {"SC1_FRM_W ",0x25,0}, ++ {"GOP0_R ",0x26,0}, ++ {"3DNR1_R ",0x27,0}, ++ {"3DNR1_W ",0x28,0}, ++ {"CMDQ2_R ",0x29,0}, ++ {"BDMA ",0x2A,0}, ++ {"AESDMA ",0x2B,0}, ++ {"USB20 ",0x2C,0}, ++ {"USB20_H ",0x2D,0}, ++ {"MIIC1 ",0x2E,0}, ++ {"URDMA ",0x2F,0}, ++ {"VEN_R ",0x30,0}, ++ {"VEN_W ",0x31,0}, ++ {"JPE_W ",0x32,0}, ++ {"JPE_R ",0x33,0}, ++ {"DIP1_R ",0x34,0}, ++ {"DIP1_W ",0x35,0}, ++ {"GOP1_R ",0x36,0}, ++ {"BACH0 ",0x37,0}, ++ {"BACH1 ",0x38,0}, ++ {"CMDQ3_R ",0x39,0}, ++ {"SDIO ",0x3A,0}, ++ {"FCIE ",0x3B,0}, ++ {"MIIC2 ",0x3C,0}, ++ {"MIIC3 ",0x3D,0}, ++ {"RSVD ",0x3E,1}, ++ {"RSVD ",0x3F,1}, ++ {"CPU ",CPU_CLIENT_ID,0}, ++}; ++ ++static char miu_devname[MIU_NUM][5]; ++static struct miu_client_bw miu_clients_bw[MIU_NUM][MIU_CLIENT_NUM]; ++static struct miu_device miu[MIU_NUM]; ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++static int gmonitor_interval[MIU_NUM] = {4, 4};//{14, 14}; ++static int gmonitor_duration[MIU_NUM] = {2000, 2000};//{1800, 1800}; ++static int gmonitor_output_kmsg[MIU_NUM] = {1, 1}; ++ ++static char m_bOutputFilePath[128] = "/mnt/dump_miu_bw.txt"; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++ ++static struct file *miu_bw_open_file(char *path, int flag, int mode) ++{ ++ struct file *filp = NULL; ++ mm_segment_t oldfs; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ filp = filp_open(path, flag, mode); ++ ++ set_fs(oldfs); ++ if (IS_ERR(filp)) { ++ return NULL; ++ } ++ return filp; ++} ++ ++static int miu_bw_write_file(struct file *fp, char *buf, int writelen) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_write(fp, buf, writelen, &fp->f_pos); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++static int miu_bw_close_file(struct file *fp) ++{ ++ filp_close(fp, NULL); ++ return 0; ++} ++ ++short miu_client_reserved(U16 id) ++{ ++ if (id < MIU_CLIENT_NUM) ++ { ++ return miu_clients[id].rsvd; ++ } ++ else if (id == CPU_CLIENT_ID) ++ { ++ return miu_clients[MIU_CLIENT_NUM - 1].rsvd; ++ } ++ return 1; ++} ++ ++const char* miu_client_id_to_name(U16 id) ++{ ++ if (id < MIU_CLIENT_NUM) ++ { ++ return miu_clients[id].name; ++ } ++ else if (id == CPU_CLIENT_ID) ++ { ++ return miu_clients[MIU_CLIENT_NUM - 1].name; ++ } ++ return NULL; ++} ++ ++static int set_miu_client_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ if (miu_clients[idx].rsvd == 0) ++ { ++ miu_clients_bw[m][idx].enabled = enabled; ++ } ++ ++ return n; ++} ++ ++static int set_miu_client_dump_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ if (miu_clients[idx].rsvd == 0) ++ { ++ miu_clients_bw[m][idx].dump_en = enabled; ++ } ++ ++ return n; ++} ++ ++static int set_miu_client_filter_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ if (miu_clients[idx].rsvd == 0) ++ { ++ miu_clients_bw[m][idx].filter_en = enabled; ++ } ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if(!strncmp(buf, "all", strlen("all"))) ++ { ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ if (miu_clients[i].rsvd == 0) ++ { ++ miu_clients_bw[m][i].enabled = 1; ++ } ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n", ++ i, ++ miu_clients[i].name, ++ miu_clients[i].id, ++ miu_clients_bw[m][i].enabled); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ if (miu_clients[i].rsvd == 0) ++ { ++ miu_clients_bw[m][i].enabled = 0; ++ } ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 0); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n", ++ i, ++ miu_clients[i].name, ++ miu_clients[i].id, ++ miu_clients_bw[m][i].enabled); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_interval[m] = input; ++ ++ return count; ++} ++ ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ return sprintf(buf, "%d\n", gmonitor_interval[m]); ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_duration[m] = input; ++ ++ return count; ++} ++ ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ return sprintf(buf, "%d\n", gmonitor_duration[m]); ++} ++ ++static ssize_t monitor_client_dump_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ if (miu_clients[i].rsvd == 0) ++ { ++ miu_clients_bw[m][i].dump_en = 1; ++ } ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_dump_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_dump_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n", ++ i, ++ miu_clients[i].name, ++ miu_clients[i].id, ++ miu_clients_bw[m][i].dump_en); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_filter_abnormal_value_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ if (miu_clients[i].rsvd == 0) ++ { ++ miu_clients_bw[m][i].filter_en = 1; ++ } ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_filter_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_filter_abnormal_value_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n", ++ i, ++ miu_clients[i].name, ++ miu_clients[i].id, ++ miu_clients_bw[m][i].filter_en); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_output_kmsg[m] = input; ++ ++ return count; ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#define DUMP_FILE_TEMP_BUF_SZ (PAGE_SIZE*10) ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0, temp_loop_time = 0; ++ int id; ++ int iMonitorDumpToFile = 0; ++ int iMiuBankAddr = 0; ++ short temp_val = 0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ char* u8Buf = NULL; ++ char* u8Ptr = NULL; ++ char* u8PtrEnd = NULL; ++ struct file *pstOutFd = NULL; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (m == 0) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ } ++ else if (m == 1) { ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ } ++ else { ++ return 0; ++ } ++ ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ miu_clients_bw[m][i].effi_min = 0x3FF; ++ miu_clients_bw[m][i].effi_avg = 0; ++ miu_clients_bw[m][i].avg = 0; ++ miu_clients_bw[m][i].max = 0; ++ ++ if (miu_clients_bw[m][i].dump_en) { ++ iMonitorDumpToFile = 1; ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ u8Buf = kmalloc(DUMP_FILE_TEMP_BUF_SZ, GFP_KERNEL); ++ u8Ptr = u8Buf; ++ u8PtrEnd = u8Buf + (DUMP_FILE_TEMP_BUF_SZ); ++ ++ pstOutFd = miu_bw_open_file(m_bOutputFilePath, O_WRONLY | O_CREAT, 0644); ++ } ++ ++ if (gmonitor_output_kmsg[m]) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ if (miu_clients_bw[m][i].enabled && (miu_clients[i].rsvd == 0)) ++ { ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ id = miu_clients[i].id; ++ OUTREG16((iMiuBankAddr+REG_ID_2B), (id & 0x40) ? 0x01 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); // set to read efficiency ++ ++ deadline = jiffies + gmonitor_duration[m]*HZ/1000; ++ ++ do { ++ if (gmonitor_interval[m] > 10) ++ msleep(gmonitor_interval[m]); ++ else ++ mdelay(gmonitor_interval[m]); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if (miu_clients_bw[m][i].filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (miu_clients_bw[m][i].dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] Efficiency\n", (short)i, miu_clients[i].name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if (miu_clients_bw[m][i].effi_min > temp_val) { ++ miu_clients_bw[m][i].effi_min = temp_val; ++ } ++ ++ if (miu_clients_bw[m][i].filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ miu_clients_bw[m][i].effi_avg = total_temp / temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read bandwidth ++ ++ deadline = jiffies + gmonitor_duration[m]*HZ/1000; ++ ++ do { ++ if (gmonitor_interval[m] > 10) ++ msleep(gmonitor_interval[m]); ++ else ++ mdelay(gmonitor_interval[m]); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if (miu_clients_bw[m][i].filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (iMonitorDumpToFile && miu_clients_bw[m][i].dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] BandWidth\n", (short)i, miu_clients[i].name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if (miu_clients_bw[m][i].max < temp_val) { ++ miu_clients_bw[m][i].max = temp_val; ++ } ++ ++ if (miu_clients_bw[m][i].filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ miu_clients_bw[m][i].avg = total_temp / temp_loop_time; ++ ++ if (gmonitor_output_kmsg[m]) ++ { ++ printk("%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ miu_clients[i].name, ++ miu_clients_bw[m][i].effi_avg*100/1024, ++ (miu_clients_bw[m][i].effi_avg*10000/1024)%100, ++ miu_clients_bw[m][i].avg*100/1024, ++ (miu_clients_bw[m][i].avg*10000/1024)%100, ++ miu_clients_bw[m][i].max*100/1024, ++ (miu_clients_bw[m][i].max*10000/1024)%100, ++ miu_clients_bw[m][i].avg*100/miu_clients_bw[m][i].effi_avg, ++ (miu_clients_bw[m][i].avg*10000/miu_clients_bw[m][i].effi_avg)%100, ++ miu_clients_bw[m][i].max*100/miu_clients_bw[m][i].effi_avg, ++ (miu_clients_bw[m][i].max*10000/miu_clients_bw[m][i].effi_avg)%100); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ miu_clients[i].name, ++ miu_clients_bw[m][i].effi_avg*100/1024, ++ (miu_clients_bw[m][i].effi_avg*10000/1024)%100, ++ miu_clients_bw[m][i].avg*100/1024, ++ (miu_clients_bw[m][i].avg*10000/1024)%100, ++ miu_clients_bw[m][i].max*100/1024, ++ (miu_clients_bw[m][i].max*10000/1024)%100, ++ miu_clients_bw[m][i].avg*100/miu_clients_bw[m][i].effi_avg, ++ (miu_clients_bw[m][i].avg*10000/miu_clients_bw[m][i].effi_avg)%100, ++ miu_clients_bw[m][i].max*100/miu_clients_bw[m][i].effi_avg, ++ (miu_clients_bw[m][i].max*10000/miu_clients_bw[m][i].effi_avg)%100); ++ } ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ if (pstOutFd) { ++ miu_bw_write_file(pstOutFd, u8Buf, u8Ptr - u8Buf); ++ miu_bw_close_file(pstOutFd); ++ } ++ ++ kfree(u8Buf); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++DEVICE_ATTR(monitor_client_dump_enable, 0644, monitor_client_dump_enable_show, monitor_client_dump_enable_store); ++DEVICE_ATTR(monitor_client_filter_enable, 0644, monitor_filter_abnormal_value_show, monitor_filter_abnormal_value_store); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret = 0, i; ++ ++ //initialize MIU client table ++ memset(miu_clients_bw, 0, sizeof(miu_clients)); ++ //OVERALL client monitor enable ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ miu_clients_bw[i][0].enabled = 1; ++ miu_devname[i][0] = 'm'; miu_devname[i][1] = 'i'; miu_devname[i][2] = 'u'; miu_devname[i][3] = '0' + i; ++ } ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ miu[i].index = 0; ++ miu[i].dev.kobj.name = (const char *)miu_devname[i]; ++ miu[i].dev.bus = &miu_subsys; ++ ++ ret = device_register(&miu[i].dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register %s device!! %d\n",miu[i].dev.kobj.name,ret); ++ return; ++ } ++ ++ device_create_file(&miu[i].dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu[i].dev, &dev_attr_measure_all); ++ } ++ create_miu_bw_node(&miu_subsys); ++} +diff --git a/arch/arm/mach-sstar/infinity5/miu_bw.h b/arch/arm/mach-sstar/infinity5/miu_bw.h +new file mode 100755 +index 000000000000..eeb18b96ab71 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/miu_bw.h +@@ -0,0 +1,131 @@ ++/* ++* miu_bw.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Alterman.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++#ifndef MIU_NUM ++#define MIU_NUM (2) ++#endif ++ ++#define CPU_CLIENT_ID (0x70) ++#define MIU_GRP_CLIENT_NUM (0x10) ++#define MIU_GRP_NUM (4) ++#define MIU_CLIENT_NUM (0x41) // CPU + (16 clients per group, total 4 groups) ++ ++#define MIU_ARB_CLIENT_NUM (0x40) // MIU_CLIENT_NUM - CPU ++#define MIU_ARB_CLIENT_ALL (0) // Client 0 means all clients ++ ++#define MIU_IDX(c) (((c - '0') > MIU_NUM) ? 0 : c - '0') ++ ++// priority ++#define MIU_ARB_PRIO_1ST 0 ++#define MIU_ARB_PRIO_2ND 1 ++#define MIU_ARB_PRIO_3RD 2 ++#define MIU_ARB_PRIO_4TH 3 ++ ++// burst ++#define MIU_ARB_BURST_NOLIM 4 ++#define MIU_ARB_BURST_OPT 5 // no limit + 4 different burst length option ++ ++// group flow control ++#define MIU_ARB_CNT_PERIOD_MAX (0xFF) ++#define MIU_ARB_GET_CNT_EN(en) (en&0xFF) ++#define MIU_ARB_GET_CNT_ID0(id) (id&0x0F) ++#define MIU_ARB_GET_CNT_ID1(id) ((id>>4)&0x0F) ++#define MIU_ARB_GET_CNT_ID0_EN(en) (en&0x0F) ++#define MIU_ARB_GET_CNT_ID1_EN(en) ((en>>4)&0x0F) ++#define MIU_ARB_SET_CNT_ID0(id, i) id = ((id&0xF0)|i) ++#define MIU_ARB_SET_CNT_ID1(id, i) id = ((id&0x0F)|(i<<4)) ++#define MIU_ARB_SET_CNT_ID0_EN(en, e) en = ((en&0xF0)|e) ++#define MIU_ARB_SET_CNT_ID1_EN(en, e) en = ((en&0x0F)|(e<<4)) ++ ++// dump ++#define MIU_ARB_DUMP_TEXT 0 ++#define MIU_ARB_DUMP_REG 1 ++#define MIU_ARB_DUMP_MAX 2 ++ ++// policy ++#define MIU_ARB_POLICY_RR 0 ++#define MIU_ARB_POLICY_RT 1 ++#define MIU_ARB_POLICY_NUM 2 ++ ++// log output ++#define ASCII_COLOR_RED "\033[1;31m" ++#define ASCII_COLOR_WHITE "\033[1;37m" ++#define ASCII_COLOR_YELLOW "\033[1;33m" ++#define ASCII_COLOR_BLUE "\033[1;36m" ++#define ASCII_COLOR_GREEN "\033[1;32m" ++#define ASCII_COLOR_END "\033[0m" ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++// common for all MIU ++struct miu_client { ++ const char *name; ++ const short id; ++ const short rsvd; ++}; ++ ++// dedicated for each MIU ++struct miu_client_bw { ++ short enabled; ++ short dump_en; ++ short filter_en; ++ short max; ++ short avg; ++ short effi_avg; ++ short effi_min; ++}; ++ ++struct arb_flowctrl { ++ unsigned char cnt0_id; // client ID, bit[3:0]: ID0, bit[7:4]: ID1 ++ unsigned char cnt0_period; // mask period, (max. 255) ++ unsigned char cnt0_enable; // client enable, bit[3:0]: ID0, bit[7:4]: ID1 ++ unsigned char cnt1_id; // client ID, bit[3:0]: ID0, bit[7:4]: ID1 ++ unsigned char cnt1_period; // mask period, (max. 255) ++ unsigned char cnt1_enable; // client enable, bit[3:0]: ID0, bit[7:4]: ID1 ++}; ++ ++struct miu_arb { ++ char name[12]; // device name (miu_arbx) ++ char priority[MIU_ARB_CLIENT_NUM]; // client priority (0/1/2/3) ++ char burst[MIU_ARB_CLIENT_NUM]; // client burst length (8/16/32/64), 0 => no limit ++ char promote[MIU_ARB_CLIENT_NUM]; // client promote enable/disable ++ struct arb_flowctrl fctrl[MIU_GRP_NUM]; // flow control, mask request for a period ++ char dump; // dump mode: readable text, register table ++ short client_selected; ++}; ++ ++/*=============================================================*/ ++// Export Functions ++/*=============================================================*/ ++ ++extern const char* miu_client_id_to_name(U16 id); ++extern short miu_client_reserved(U16 id); ++extern void create_miu_bw_node(struct bus_type *miu_subsys); ++ +diff --git a/arch/arm/mach-sstar/infinity5/pm.c b/arch/arm/mach-sstar/infinity5/pm.c +new file mode 100755 +index 000000000000..12b1bfbb7a3e +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/pm.c +@@ -0,0 +1,80 @@ ++/* ++* pm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void sram_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&sram_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0x1FC10000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity5/soc.c b/arch/arm/mach-sstar/infinity5/soc.c +new file mode 100755 +index 000000000000..806a93ad6faa +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/soc.c +@@ -0,0 +1,644 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ //{IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "sstar,infinity5", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++ ++ ++//extern struct timecounter *arch_timer_get_timecounter(void); ++ ++ ++static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5 | BIT6); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1 | BIT2); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ volatile unsigned long dwLockFlag = 0; ++ volatile unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ dsb(); ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++/*//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NAND BIT2 ++#define STORAGE_EMMC BIT3 ++#define STORAGE_P_NAND BIT4 ++#define STORAGE_SPI_NOR BIT5 ++*/ ++ u8 type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & 0x3C); ++ ++ if(BIT4 == type) ++ return (int)MS_STORAGE_NAND; ++ else if(BIT5 == type) ++ return (int)MS_STORAGE_NOR; ++ else if(BIT3 == type) ++ return (int)MS_STORAGE_EMMC; ++ else if(BIT2 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int mstar_get_package_type(void) ++{ ++ static MS_I5_PACKAGE_TYPE pkg_type = MS_I5_PACKAGE_UNKNOWN; ++ ++ if (pkg_type != MS_I5_PACKAGE_UNKNOWN) ++ return pkg_type; ++ ++ if(!strcmp(&mstar_soc_dev_attr.machine[10], "SSC007A-S01A")) ++ { ++ pkg_type = MS_I5_PACKAGE_BGA_13X13; ++ } ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "SSC007B-S01A") || !strcmp(&mstar_soc_dev_attr.machine[10], "SSC007B-S01B")) ++ { ++ pkg_type = MS_I5_PACKAGE_QFN; ++ } ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "FPGA")) ++ { ++ pkg_type = MS_I5_PACKAGE_FPGA_128MB; ++ } ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ } ++ ++ return pkg_type; ++} ++static char mstar_platform_name[]="I5"; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ u64 cycles=arch_timer_read_counter(); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ us_ticks_cycle_offset=arch_timer_read_counter(); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++ default: ++ printk(KERN_ERR "Unsupport CHIP_FUNCTION!! ID=%d\n",function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsbchip->phys_to_miu=mstar_phys_to_MIU; ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++struct mcm_client{ ++ char* name; ++ unsigned int reg; ++ short slow_down_ratio; ++}; ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", REG_MCM_MCU51, 0}, ++ {"URDMA", REG_MCM_URDMA, 0}, ++ {"BDMA", REG_MCM_BDMA, 0}, ++ {"DIP_R", REG_MCM_DIP_R, 0}, ++ {"DIP_W", REG_MCM_DIP_W, 0}, ++ {"LDC", REG_MCM_LDC, 0}, ++ {"SC2_FRM", REG_MCM_SC2_FRM, 0}, ++ {"SC3_FRM", REG_MCM_SC3_FRM, 0}, ++ {"RSC", REG_MCM_RSC, 0}, ++ {"SC1_DBG", REG_MCM_SC1_DBG, 0}, ++ {"CMDQ0", REG_MCM_CMDQ0, 0}, ++ {"MOVDMA0", REG_MCM_MOVDMA0, 0}, ++ {"EMAC", REG_MCM_EMAC, 0}, ++ {"3DNR0_R", REG_MCM_3DNR0_R, 0}, ++ {"3DNR0_W", REG_MCM_3DNR0_W, 0}, ++ {"GOP4", REG_MCM_GOP4, 0}, ++ {"ISP_DMAG0", REG_MCM_ISP_DMAG0, 0}, ++ {"ISP_DMAG1", REG_MCM_ISP_DMAG1, 0}, ++ {"ISP_DMAG2", REG_MCM_ISP_DMAG2, 0}, ++ {"GOP2", REG_MCM_GOP2, 0}, ++ {"GOP3", REG_MCM_GOP3, 0}, ++ {"ISP_DMAG", REG_MCM_ISP_DMAG, 0}, ++ {"ISP_STA", REG_MCM_ISP_STA, 0}, ++ {"ISP_STA1", REG_MCM_ISP_STA1, 0}, ++ {"CMDQ1", REG_MCM_CMDQ1, 0}, ++ {"MOVDMA1", REG_MCM_MOVDMA1, 0}, ++ {"IVE", REG_MCM_IVE, 0}, ++ {"SC_ROT_R", REG_MCM_SC_ROT_R, 0}, ++ {"SC_AIP_W", REG_MCM_SC_AIP_W, 0}, ++ {"SC0_FRM", REG_MCM_SC0_FRM, 0}, ++ {"SC0_SNP", REG_MCM_SC0_SNP, 0}, ++ {"SC1_FRM", REG_MCM_SC1_FRM, 0}, ++ {"GOP0", REG_MCM_GOP0, 0}, ++ {"3DNR1_R", REG_MCM_3DNR1_R, 0}, ++ {"3DNR1_W", REG_MCM_3DNR1_W, 0}, ++ {"CMDQ2", REG_MCM_CMDQ2, 0}, ++ {"AESDMA", REG_MCM_AESDMA, 0}, ++ {"USB20", REG_MCM_USB20, 0}, ++ {"USB20_H", REG_MCM_USB20_H, 0}, ++ {"JPE", REG_MCM_JPE, 0}, ++ {"GOP1", REG_MCM_GOP1, 0}, ++ {"BACH", REG_MCM_BACH, 0}, ++ {"CMDQ3", REG_MCM_CMDQ3, 0}, ++ {"SDIO", REG_MCM_SDIO, 0}, ++ {"FCIE", REG_MCM_FCIE, 0}, ++ {"VEN", REG_MCM_VEN, 0}, ++ ++ {"*ALL_CLIENTS",0, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr, cnt; ++ ++ cnt = sizeof(mcm_clients)/sizeof(mcm_clients[0]); ++ if((index == MCM_ID_ALL) && write) ++ { ++ for(i=0; i> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", i, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", i, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++ mstar_create_MCM_node(); ++} ++ ++static void global_reset(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if not nor-flash ++ break; ++ } while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = global_reset, ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity5/sram.S b/arch/arm/mach-sstar/infinity5/sram.S +new file mode 100755 +index 000000000000..464b0fa4a07d +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity5/sram.S +@@ -0,0 +1,191 @@ ++/* ++* sram.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl sram_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(sram_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(sram_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6/Kconfig b/arch/arm/mach-sstar/infinity6/Kconfig +new file mode 100755 +index 000000000000..934d0f3a8ff4 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6/Kconfig +@@ -0,0 +1,14 @@ ++config ARCH_INFINITY6 ++ bool "SoC iNfinity6 (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity6 SoC ++ ++config SS_PROFILING_TIME ++ bool "Record timestamp in sram" ++ default y +diff --git a/arch/arm/mach-sstar/infinity6/Makefile b/arch/arm/mach-sstar/infinity6/Makefile +new file mode 100755 +index 000000000000..5a6b88f5cce9 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6/Makefile +@@ -0,0 +1,8 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += soc.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6/miu_bw.c b/arch/arm/mach-sstar/infinity6/miu_bw.c +new file mode 100755 +index 000000000000..8f0739d4f264 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6/miu_bw.c +@@ -0,0 +1,1107 @@ ++/* ++* miu_bw.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_CAM_CLK ++#include "camclk.h" ++#include "drv_camclk_Api.h" ++#endif ++#include "cam_os_wrapper.h" ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++#ifndef MIU_NUM ++#define MIU_NUM (1) ++#endif ++ ++#define MIU0_CLIENT_NUM sizeof(miu0_clients)/sizeof(miu0_clients[0]) ++#define MIU1_CLIENT_NUM sizeof(miu1_clients)/sizeof(miu1_clients[0]) ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client { ++ char* name; ++ short bw_client_id; ++ short bw_rsvd; ++ short bw_enabled; ++ short bw_dump_en; ++ short bw_filter_en; ++ short bw_max; ++ short bw_avg; ++ short effi_avg; ++ short effi_min; ++}; ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_client miu0_clients[] = ++{ ++ {"OVERALL ",0x00,0,1,0,0}, ++ {"VEN_R ",0x01,0,0,0,0}, ++ {"VEN_W ",0x02,0,0,0,0}, ++ {"RSVD ",0x03,1,0,0,0}, ++ {"JPE_R ",0x04,0,0,0,0}, ++ {"JPE_W ",0x05,0,0,0,0}, ++ {"BACH_RW ",0x06,0,0,0,0}, ++ {"AESDMA_RW ",0x07,0,0,0,0}, ++ {"USB20_RW ",0x08,0,0,0,0}, ++ {"EMAC_RW ",0x09,0,0,0,0}, ++ {"MCU51_RW ",0x0A,0,0,0,0}, ++ {"URDMA_RW ",0x0B,0,0,0,0}, ++ {"BDMA_RW ",0x0C,0,0,0,0}, ++ {"MOVDMA0_RW",0x0D,0,0,0,0}, ++ {"RSVD ",0x0E,1,0,0,0}, ++ {"RSVD ",0x0F,1,0,0,0}, ++ {"CMDQ0_R ",0x10,0,0,0,0}, ++ {"ISP_DMA_W ",0x11,0,0,0,0}, ++ {"ISP_DMA_R ",0x12,0,0,0,0}, ++ {"ISP_ROT_R ",0x13,0,0,0,0}, ++ {"ISP_MLOAD ",0x14,0,0,0,0}, ++ {"GOP ",0x15,0,0,0,0}, ++ {"RSVD ",0x16,1,0,0,0}, ++ {"DIP0_R ",0x17,0,0,0,0}, ++ {"DIP0_W ",0x18,0,0,0,0}, ++ {"SC0_FRAME ",0x19,0,0,0,0}, ++ {"RSVD ",0x1A,1,0,0,0}, ++ {"SC0_DBG_R ",0x1B,0,0,0,0}, ++ {"SC1_FRAME ",0x1C,0,0,0,0}, ++ {"SC2_FRAME ",0x1D,0,0,0,0}, ++ {"SD30_RW ",0x1E,0,0,0,0}, ++ {"SDIO30_RW ",0x1F,0,0,0,0}, ++ {"CMDQ1_R ",0x20,0,0,0,0}, ++ {"CMDQ2_R ",0x21,0,0,0,0}, ++ {"RSVD ",0x22,1,0,0,0}, ++ {"ISP_DMAG ",0x23,0,0,0,0}, ++ {"GOP1_R ",0x24,0,0,0,0}, ++ {"GOP2_R ",0x25,0,0,0,0}, ++ {"USB20_H_RW",0x26,0,0,0,0}, ++ {"RSVD ",0x27,1,0,0,0}, ++ {"MIIC1_RW ",0x28,0,0,0,0}, ++ {"3DNR0_W ",0x29,0,0,0,0}, ++ {"3DNR0_R ",0x2A,0,0,0,0}, ++ {"CPU ",0x70,0,0,0,0}, ++}; ++ ++#if MIU_NUM > 1 ++static struct miu_client miu1_clients[] = ++{ ++ {"OVERALL ",0x00,0,1,0,0}, ++}; ++#endif ++ ++static struct miu_device miu0; ++#if MIU_NUM > 1 ++static struct miu_device miu1; ++#endif ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++static int gmonitor_interval[MIU_NUM] = {4};//{14}; ++static int gmonitor_duration[MIU_NUM] = {2000};//{1800}; ++static int gmonitor_output_kmsg[MIU_NUM] = {1}; ++ ++static char m_bOutputFilePath[128] = "/mnt/dump_miu_bw.txt"; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++ ++static struct file *miu_bw_open_file(char *path, int flag, int mode) ++{ ++ struct file *filp = NULL; ++ mm_segment_t oldfs; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ filp = filp_open(path, flag, mode); ++ ++ set_fs(oldfs); ++ if (IS_ERR(filp)) { ++ return NULL; ++ } ++ return filp; ++} ++ ++static int miu_bw_write_file(struct file *fp, char *buf, int writelen) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_write(fp, buf, writelen, &fp->f_pos); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++static int miu_bw_close_file(struct file *fp) ++{ ++ filp_close(fp, NULL); ++ return 0; ++} ++ ++const char* miu_client_id_to_name(U16 id) ++{ ++ int i = 0; ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_client_id == id) { ++ return miu0_clients[i].name; ++ } ++ } ++ return NULL; ++} ++ ++static int set_miu_client_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_enabled = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_enabled = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static int set_miu_client_dump_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_dump_en = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_dump_en = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static int set_miu_client_filter_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_filter_en = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_filter_en = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_enabled = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_enabled = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_enabled); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_enabled); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_enabled = 0; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_enabled = 0; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 0); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_enabled); ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_enabled); ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_interval[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_interval[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ if ('0'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_interval[0]); ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_interval[1]); ++#endif ++ else ++ return 0; ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_duration[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_duration[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ if ('0'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_duration[0]); ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_duration[1]); ++#endif ++ else ++ return 0; ++} ++ ++static ssize_t monitor_client_dump_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_dump_en = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_dump_en = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_dump_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_dump_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_dump_en); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_dump_en); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_filter_abnormal_value_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_filter_en = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_filter_en = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_filter_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_filter_abnormal_value_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_filter_en); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_filter_en); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_output_kmsg[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_output_kmsg[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#define DUMP_FILE_TEMP_BUF_SZ (PAGE_SIZE*10) ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0, temp_loop_time = 0; ++ int id; ++ int iMiuClientNum = 0; ++ int iMonitorInterval = 0; ++ int iMonitorDuration = 0; ++ int iMonitorOutputKmsg = 1; ++ int iMonitorDumpToFile = 0; ++ int iMiuBankAddr = 0; ++ struct miu_client *pstMiuClient = NULL; ++ ++ short temp_val = 0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ char* u8Buf = NULL; ++ char* u8Ptr = NULL; ++ char* u8PtrEnd = NULL; ++ struct file *pstOutFd = NULL; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU0_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[0]; ++ iMonitorDuration = gmonitor_duration[0]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[0]; ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ pstMiuClient = &miu0_clients[0]; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU1_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[1]; ++ iMonitorDuration = gmonitor_duration[1]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[1]; ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ pstMiuClient = &miu1_clients[0]; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) { ++ (pstMiuClient + i)->effi_min = 0x3FF; ++ (pstMiuClient + i)->effi_avg = 0; ++ (pstMiuClient + i)->bw_avg = 0; ++ (pstMiuClient + i)->bw_max = 0; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ iMonitorDumpToFile = 1; ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ u8Buf = kmalloc(DUMP_FILE_TEMP_BUF_SZ, GFP_KERNEL); ++ u8Ptr = u8Buf; ++ u8PtrEnd = u8Buf + (DUMP_FILE_TEMP_BUF_SZ); ++ ++ pstOutFd = miu_bw_open_file(m_bOutputFilePath, O_WRONLY | O_CREAT, 0644); ++ } ++ ++ if (iMonitorOutputKmsg) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) ++ { ++ if ((pstMiuClient + i)->bw_enabled && (pstMiuClient + i)->bw_rsvd == 0) ++ { ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ id = (pstMiuClient + i)->bw_client_id; ++ OUTREG16((iMiuBankAddr+REG_ID_15), (id & 0x40) ? 0x80 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); // set to read efficiency ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ if (iMonitorInterval > 10) ++ msleep(iMonitorInterval); ++ else ++ mdelay(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] Efficiency\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->effi_min > temp_val) { ++ (pstMiuClient + i)->effi_min = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->effi_avg = total_temp / temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read bandwidth ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ if (iMonitorInterval > 10) ++ msleep(iMonitorInterval); ++ else ++ mdelay(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (iMonitorDumpToFile && (pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] BandWidth\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->bw_max < temp_val) { ++ (pstMiuClient + i)->bw_max = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->bw_avg = total_temp / temp_loop_time; ++ ++ if (iMonitorOutputKmsg) ++ { ++ printk("%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)(pstMiuClient + i)->bw_client_id, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_avg*10000/(pstMiuClient + i)->effi_avg)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_avg*10000/(pstMiuClient + i)->effi_avg)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ if (pstOutFd) { ++ miu_bw_write_file(pstOutFd, u8Buf, u8Ptr - u8Buf); ++ miu_bw_close_file(pstOutFd); ++ } ++ ++ kfree(u8Buf); ++ } ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++#ifdef CONFIG_CAM_CLK ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int dram_type = 0; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ iAtopBankAddr = BASE_REG_ATOP1_PA; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", CamClkRateGet(CAMCLK_ddrpll_clk) / 1000000); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", CamClkRateGet(CAMCLK_miupll_clk) / 1000000); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ str += scnprintf(str, end - str, "SSC: %s\n", (INREGMSK16(iAtopBankAddr + REG_ID_14, 0xC000)==0x8000)? "OFF" : "ON"); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++#else //CONFIG_CAM_CLK ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int iMiupllBankAddr = 0; ++ unsigned int dram_type = 0; ++ unsigned int ddfset = 0; ++ unsigned int dram_freq = 0; ++ unsigned int miupll_freq = 0; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ iAtopBankAddr = BASE_REG_ATOP1_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ddfset = (INREGMSK16(iAtopBankAddr + REG_ID_19, 0x00FF) << 16) + INREGMSK16(iAtopBankAddr + REG_ID_18, 0xFFFF); ++ dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ miupll_freq = 24 * INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x00FF) / ((INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x0700) >> 8) + 2); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", dram_freq); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", miupll_freq); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ str += scnprintf(str, end - str, "SSC: %s\n", (INREGMSK16(iAtopBankAddr + REG_ID_14, 0xC000)==0x8000)? "OFF" : "ON"); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++#endif ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++DEVICE_ATTR(monitor_client_dump_enable, 0644, monitor_client_dump_enable_show, monitor_client_dump_enable_store); ++DEVICE_ATTR(monitor_client_filter_enable, 0644, monitor_filter_abnormal_value_show, monitor_filter_abnormal_value_store); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++DEVICE_ATTR(dram_info, 0444, dram_info_show, NULL); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret = 0; ++ ++ miu0.index = 0; ++ miu0.dev.kobj.name = "miu0"; ++ miu0.dev.bus = &miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&miu0.dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu0.dev, &dev_attr_measure_all); ++ device_create_file(&miu0.dev, &dev_attr_dram_info); ++ ++#if MIU_NUM > 1 ++ miu1.index = 0; ++ miu1.dev.kobj.name = "miu1"; ++ miu1.dev.bus = &miu_subsys; ++ ++#if 0 // Don't register again ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++#endif ++ ++ ret = device_register(&miu1.dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu1 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu1.dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu1.dev, &dev_attr_measure_all); ++ device_create_file(&miu1.dev, &dev_attr_dram_info); ++#endif ++} +diff --git a/arch/arm/mach-sstar/infinity6/pm.c b/arch/arm/mach-sstar/infinity6/pm.c +new file mode 100755 +index 000000000000..9537114f8e15 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6/pm.c +@@ -0,0 +1,80 @@ ++/* ++* pm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void sram_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&sram_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity6/soc.c b/arch/arm/mach-sstar/infinity6/soc.c +new file mode 100755 +index 000000000000..668d36d41fcc +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6/soc.c +@@ -0,0 +1,645 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++//#define CONFIG_SS_MCM ++#define CONFIG_CHIP_FUNC_USB_VBUS_CONTROL ++//#define CONFIG_CHIP_FUNC_IR_ENABLE ++//#define CONFIG_CHIP_FUNC_UART_LINE ++ ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ {IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "sstar,infinity6", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++ ++ ++//extern struct timecounter *arch_timer_get_timecounter(void); ++ ++#ifdef CONFIG_SS_MCM ++ ++static int mcm_rw(int index, int ratio, int write); ++#endif ++ ++/************************************* ++* Sstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++#ifdef CONFIG_CHIP_FUNC_UART_LINE ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++#endif ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ volatile unsigned long dwLockFlag = 0; ++ volatile unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ dsb(); ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++/*//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NAND BIT2 ++#define STORAGE_SPI_NAND_SKIPSD BIT3 ++#define STORAGE_SPI_NOR_SKIPSD BIT4 ++#define STORAGE_SPI_NOR BIT5 ++*/ ++ u8 type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & 0x3C); ++ ++ if(BIT3 == type || BIT2 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else if(BIT5 == type || BIT4 == type) ++ return (int)MS_STORAGE_NOR; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int mstar_get_package_type(void) ++{ ++ if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S01A")) ++ return MS_I6_PACKAGE_BGA_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S02A-256M") || !strcmp(&mstar_soc_dev_attr.machine[10], "MSC250C")) ++ return MS_I6_PACKAGE_DDR3_1866_256MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S04A")) ++ return MS_I6_PACKAGE_QFN_DDR3_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S03A-64M")) ++ return MS_I6_PACKAGE_QFN_DDR2_64MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "FPGA")) ++ return MS_I6_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I6_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]="I6"; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++#ifdef CONFIG_CHIP_FUNC_IR_ENABLE ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++#endif ++#ifdef CONFIG_CHIP_FUNC_USB_VBUS_CONTROL ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ //printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ //printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++#endif ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ u64 cycles=arch_timer_read_counter(); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ us_ticks_cycle_offset=arch_timer_read_counter(); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++#ifdef CONFIG_CHIP_FUNC_UART_LINE ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++#endif ++#ifdef CONFIG_CHIP_FUNC_IR_ENABLE ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++#endif ++#ifdef CONFIG_CHIP_FUNC_USB_VBUS_CONTROL ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++#endif ++#ifdef CONFIG_SS_MCM ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++#endif ++ default: ++ BUG(); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsbchip->phys_to_miu=mstar_phys_to_MIU; ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++#ifdef CONFIG_SS_MCM ++struct mcm_client{ ++ char* name; ++ short index; ++ unsigned int reg; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, OFFSET_MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, OFFSET_MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, OFFSET_MCM_ID_BDMA, 0}, ++ {"MFE", MCM_ID_MFE, OFFSET_MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, OFFSET_MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, OFFSET_MCM_ID_BACH, 0}, ++ {"FILE", MCM_ID_FILE, OFFSET_MCM_ID_FILE, 0}, ++ {"UHC0", MCM_ID_UHC0, OFFSET_MCM_ID_UHC0, 0}, ++ {"EMAC", MCM_ID_EMAC, OFFSET_MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, OFFSET_MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, OFFSET_MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, OFFSET_MCM_ID_ISP_DMA, 0}, ++ {"GOP0", MCM_ID_GOP0, OFFSET_MCM_ID_GOP0, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, OFFSET_MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, OFFSET_MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, OFFSET_MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, OFFSET_MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, OFFSET_MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, OFFSET_MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, OFFSET_MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, OFFSET_MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, OFFSET_MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, OFFSET_MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, OFFSET_MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, OFFSET_MCM_ID_SC2_SNPI, 0}, ++ {"CMDQ1", MCM_ID_CMDQ1, OFFSET_MCM_ID_CMDQ1, 0}, ++ {"CMDQ2", MCM_ID_CMDQ2, OFFSET_MCM_ID_CMDQ2, 0}, ++ {"GOP1", MCM_ID_GOP1, OFFSET_MCM_ID_GOP1, 0}, ++ {"GOP2", MCM_ID_GOP2, OFFSET_MCM_ID_GOP2, 0}, ++ {"UHC1", MCM_ID_UHC1, OFFSET_MCM_ID_UHC1, 0}, ++ {"IVE", MCM_ID_IVE, OFFSET_MCM_ID_IVE, 0}, ++ {"VHE", MCM_ID_VHE, OFFSET_MCM_ID_VHE, 0}, ++ {"*ALL_CLIENTS",MCM_ID_ALL, 0, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ ++ return 0; ++ } ++ ++ if((index >= MCM_ID_START) &&(index < MCM_ID_END)) ++ { ++ addr = mcm_clients[index].reg; ++ } ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++#endif ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++#ifdef CONFIG_SS_MCM ++ mstar_create_MCM_node(); ++#endif ++} ++ ++static void global_reset(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = global_reset, ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity6/sram.S b/arch/arm/mach-sstar/infinity6/sram.S +new file mode 100755 +index 000000000000..464b0fa4a07d +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6/sram.S +@@ -0,0 +1,191 @@ ++/* ++* sram.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl sram_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(sram_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(sram_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6b0/Kconfig b/arch/arm/mach-sstar/infinity6b0/Kconfig +new file mode 100755 +index 000000000000..6ead9e24190c +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6b0/Kconfig +@@ -0,0 +1,14 @@ ++config ARCH_INFINITY6B0 ++ bool "SoC iNfinity6b0 (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity6b0 SoC ++ ++config SS_PROFILING_TIME ++ bool "Record timestamp in sram" ++ default y +diff --git a/arch/arm/mach-sstar/infinity6b0/Makefile b/arch/arm/mach-sstar/infinity6b0/Makefile +new file mode 100755 +index 000000000000..5a6b88f5cce9 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6b0/Makefile +@@ -0,0 +1,8 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += soc.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6b0/miu_bw.c b/arch/arm/mach-sstar/infinity6b0/miu_bw.c +new file mode 100755 +index 000000000000..7b2ba5d54522 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6b0/miu_bw.c +@@ -0,0 +1,1306 @@ ++/* ++* miu_bw.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_CAM_CLK ++#include "camclk.h" ++#include "drv_camclk_Api.h" ++#endif ++#include "cam_os_wrapper.h" ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++#ifndef MIU_NUM ++#define MIU_NUM (1) ++#endif ++ ++#define MIU0_CLIENT_NUM sizeof(miu0_clients)/sizeof(miu0_clients[0]) ++#define MIU1_CLIENT_NUM sizeof(miu1_clients)/sizeof(miu1_clients[0]) ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client { ++ char* name; ++ short bw_client_id; ++ short bw_rsvd; ++ short bw_enabled; ++ short bw_dump_en; ++ short bw_filter_en; ++ short bw_max; ++ short bw_avg; ++ short bw_min; ++ short effi_avg; ++ short effi_min; ++ short effi_max; ++ short bw_max_div_effi; ++ short bw_avg_div_effi; ++}; ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_client miu0_clients[] = ++{ ++ {"OVERALL ",0x00,0,1,0,0}, ++ {"VEN_R ",0x01,0,0,0,0}, ++ {"VEN_W ",0x02,0,0,0,0}, ++ {"RSVD ",0x03,1,0,0,0}, ++ {"JPE_R ",0x04,0,0,0,0}, ++ {"JPE_W ",0x05,0,0,0,0}, ++ {"BACH_RW ",0x06,0,0,0,0}, ++ {"AESDMA_RW ",0x07,0,0,0,0}, ++ {"USB20_RW ",0x08,0,0,0,0}, ++ {"EMAC_RW ",0x09,0,0,0,0}, ++ {"MCU51_RW ",0x0A,0,0,0,0}, ++ {"URDMA_RW ",0x0B,0,0,0,0}, ++ {"BDMA_RW ",0x0C,0,0,0,0}, ++ {"MOVDMA0_RW",0x0D,0,0,0,0}, ++ {"GOP3_R ",0x0E,0,0,0,0}, ++ {"RSVD ",0x0F,1,0,0,0}, ++ {"CMDQ_R ",0x10,0,0,0,0}, ++ {"ISP_DMA_W ",0x11,0,0,0,0}, ++ {"ISP_DMA_R ",0x12,0,0,0,0}, ++ {"ISP_ROT_R ",0x13,0,0,0,0}, ++ {"ISP_MLOAD ",0x14,0,0,0,0}, ++ {"GOP ",0x15,0,0,0,0}, ++ {"RSVD ",0x16,1,0,0,0}, ++ {"DIP0_R ",0x17,0,0,0,0}, ++ {"DIP0_W ",0x18,0,0,0,0}, ++ {"SC0_FRAME ",0x19,0,0,0,0}, ++ {"RSVD ",0x1A,1,0,0,0}, ++ {"SC0_DBG_R ",0x1B,0,0,0,0}, ++ {"SC1_FRAME ",0x1C,0,0,0,0}, ++ {"SC2_FRAME ",0x1D,0,0,0,0}, ++ {"SD30_RW ",0x1E,0,0,0,0}, ++ {"SDIO30_RW ",0x1F,0,0,0,0}, ++ {"RSVD ",0x20,1,0,0,0}, ++ {"RSVD ",0x21,1,0,0,0}, ++ {"RSVD ",0x22,1,0,0,0}, ++ {"RSVD ",0x23,1,0,0,0}, ++ {"GOP1_R ",0x24,0,0,0,0}, ++ {"GOP2_R ",0x25,0,0,0,0}, ++ {"USB20_H_RW",0x26,0,0,0,0}, ++ {"IVE_RW ",0x27,0,0,0,0}, ++ {"MIIC1_RW ",0x28,0,0,0,0}, ++ {"3DNR0_W ",0x29,0,0,0,0}, ++ {"3DNR0_R ",0x2A,0,0,0,0}, ++ {"CPU ",0x70,0,0,0,0}, ++}; ++ ++#if MIU_NUM > 1 ++static struct miu_client miu1_clients[] = ++{ ++ {"OVERALL ",0x00,0,1,0,0}, ++}; ++#endif ++ ++static struct miu_device miu0; ++#if MIU_NUM > 1 ++static struct miu_device miu1; ++#endif ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++static int gmonitor_interval[MIU_NUM] = {4};//{14}; ++static int gmonitor_duration[MIU_NUM] = {2000};//{1800}; ++static int gmonitor_output_kmsg[MIU_NUM] = {1}; ++ ++static char m_bOutputFilePath[128] = "/mnt/dump_miu_bw.txt"; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++ ++static struct file *miu_bw_open_file(char *path, int flag, int mode) ++{ ++ struct file *filp = NULL; ++ mm_segment_t oldfs; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ filp = filp_open(path, flag, mode); ++ ++ set_fs(oldfs); ++ if (IS_ERR(filp)) { ++ return NULL; ++ } ++ return filp; ++} ++ ++static int miu_bw_write_file(struct file *fp, char *buf, int writelen) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_write(fp, buf, writelen, &fp->f_pos); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++static int miu_bw_close_file(struct file *fp) ++{ ++ filp_close(fp, NULL); ++ return 0; ++} ++ ++const char* miu_client_id_to_name(U16 id) ++{ ++ int i = 0; ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_client_id == id) { ++ return miu0_clients[i].name; ++ } ++ } ++ return NULL; ++} ++ ++static int set_miu_client_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_enabled = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_enabled = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static int set_miu_client_dump_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_dump_en = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_dump_en = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static int set_miu_client_filter_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU0_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu0_clients[idx].bw_rsvd == 0) ++ miu0_clients[idx].bw_filter_en = enabled; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU1_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ ++ if (miu1_clients[idx].bw_rsvd == 0) ++ miu1_clients[idx].bw_filter_en = enabled; ++ } ++#endif ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_enabled = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_enabled = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_enabled); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_enabled); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_enabled = 0; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_enabled = 0; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 0); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_enabled); ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_enabled); ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_interval[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_interval[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ if ('0'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_interval[0]); ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_interval[1]); ++#endif ++ else ++ return 0; ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_duration[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_duration[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ if ('0'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_duration[0]); ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ return sprintf(buf, "%d\n", gmonitor_duration[1]); ++#endif ++ else ++ return 0; ++} ++ ++static ssize_t monitor_client_dump_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_dump_en = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_dump_en = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_dump_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_dump_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_dump_en); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Dump Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_dump_en); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_filter_abnormal_value_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ if ('0'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) { ++ if (miu0_clients[i].bw_rsvd == 0) ++ miu0_clients[i].bw_filter_en = 1; ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) { ++ if (miu1_clients[i].bw_rsvd == 0) ++ miu1_clients[i].bw_filter_en = 1; ++ } ++ } ++#endif ++ ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_filter_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_filter_abnormal_value_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ ++ if ('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU0_CLIENT_NUM; i++) ++ { ++ //if (miu0_clients[i].bw_enabled && !miu0_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu0_clients[i].name, (short)miu0_clients[i].bw_client_id, (char)miu0_clients[i].bw_filter_en); ++ } ++ } ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Filter Enable(1)/Disable(0)]\n"); ++ ++ for (i = 0; i < MIU1_CLIENT_NUM; i++) ++ { ++ //if (miu1_clients[i].bw_enabled && !miu1_clients[i].bw_rsvd) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i, miu1_clients[i].name, (short)miu1_clients[i].bw_client_id, (char)miu1_clients[i].bw_filter_en); ++ } ++ } ++ } ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if ('0'== (dev->kobj.name[3])) ++ gmonitor_output_kmsg[0] = input; ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) ++ gmonitor_output_kmsg[1] = input; ++#endif ++ ++ return count; ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#define DUMP_FILE_TEMP_BUF_SZ (PAGE_SIZE*10) ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0, temp_loop_time = 0; ++ int id; ++ int iMiuClientNum = 0; ++ int iMonitorInterval = 0; ++ int iMonitorDuration = 0; ++ int iMonitorOutputKmsg = 1; ++ int iMonitorDumpToFile = 0; ++ int iMiuBankAddr = 0; ++ struct miu_client *pstMiuClient = NULL; ++ ++ short temp_val = 0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ char* u8Buf = NULL; ++ char* u8Ptr = NULL; ++ char* u8PtrEnd = NULL; ++ struct file *pstOutFd = NULL; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU0_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[0]; ++ iMonitorDuration = gmonitor_duration[0]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[0]; ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ pstMiuClient = &miu0_clients[0]; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU1_CLIENT_NUM; ++ iMonitorInterval = gmonitor_interval[1]; ++ iMonitorDuration = gmonitor_duration[1]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[1]; ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ pstMiuClient = &miu1_clients[0]; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) { ++ (pstMiuClient + i)->effi_min = 0x3FF; ++ (pstMiuClient + i)->effi_avg = 0; ++ (pstMiuClient + i)->bw_avg = 0; ++ (pstMiuClient + i)->bw_max = 0; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ iMonitorDumpToFile = 1; ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ u8Buf = kmalloc(DUMP_FILE_TEMP_BUF_SZ, GFP_KERNEL); ++ u8Ptr = u8Buf; ++ u8PtrEnd = u8Buf + (DUMP_FILE_TEMP_BUF_SZ); ++ ++ pstOutFd = miu_bw_open_file(m_bOutputFilePath, O_WRONLY | O_CREAT, 0644); ++ } ++ ++ if (iMonitorOutputKmsg) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) ++ { ++ if ((pstMiuClient + i)->bw_enabled && (pstMiuClient + i)->bw_rsvd == 0) ++ { ++ unsigned long diff = 0; ++ short last; ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ id = (pstMiuClient + i)->bw_client_id; ++ OUTREG16((iMiuBankAddr+REG_ID_15), (id & 0x40) ? 0x80 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); // set to read efficiency ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ if (iMonitorInterval > 10) ++ msleep(iMonitorInterval); ++ else ++ mdelay(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (temp_loop_time) { ++ diff += (temp_val > last) ? temp_val - last : last - temp_val; ++ } ++ last = temp_val; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] Efficiency\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->effi_min > temp_val) { ++ (pstMiuClient + i)->effi_min = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->effi_avg = total_temp / temp_loop_time; ++ ++ total_temp = 0; ++ temp_loop_time = 0; ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0000); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read bandwidth ++ ++ deadline = jiffies + iMonitorDuration*HZ/1000; ++ ++ do { ++ if (iMonitorInterval > 10) ++ msleep(iMonitorInterval); ++ else ++ mdelay(iMonitorInterval); ++ ++ temp_val = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ total_temp += temp_val; ++ } ++ } ++ else { ++ total_temp += temp_val; ++ } ++ ++ if (iMonitorDumpToFile && (pstMiuClient + i)->bw_dump_en) { ++ if (temp_loop_time == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n----------------------------------------------------------------\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "ClientId[%d] Name[%s] BandWidth\n", (short)i, (pstMiuClient + i)->name); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t0x00\t0x01\t0x02\t0x03\t0x04\t0x05\t0x06\t0x07\n"); ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "----------------------------------------------------------------\n"); ++ } ++ ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\t%2d.%02d%%", ++ temp_val*100/1024, ++ (temp_val*10000/1024)%100); ++ if ((temp_loop_time+1) % 0x8 == 0) { ++ u8Ptr += scnprintf(u8Ptr, u8PtrEnd - u8Ptr, "\n"); ++ } ++ } ++ ++ if ((pstMiuClient + i)->bw_max < temp_val) { ++ (pstMiuClient + i)->bw_max = temp_val; ++ } ++ ++ if ((pstMiuClient + i)->bw_filter_en) { ++ if (temp_val) { ++ temp_loop_time++; ++ } ++ } ++ else { ++ temp_loop_time++; ++ } ++ ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ (pstMiuClient + i)->bw_avg = total_temp / temp_loop_time; ++ ++ // client effiency never changes and total BW is zero ++ if ((diff == 0) && (total_temp == 0)) { ++ (pstMiuClient + i)->effi_avg = 0x3FF; ++ } ++ ++ if (iMonitorOutputKmsg) ++ { ++ printk("%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)(pstMiuClient + i)->bw_client_id, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_avg*10000/(pstMiuClient + i)->effi_avg)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_avg*10000/(pstMiuClient + i)->effi_avg)%100, ++ (pstMiuClient + i)->bw_max*100/(pstMiuClient + i)->effi_avg, ++ ((pstMiuClient + i)->bw_max*10000/(pstMiuClient + i)->effi_avg)%100); ++ } ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ if (pstOutFd) { ++ miu_bw_write_file(pstOutFd, u8Buf, u8Ptr - u8Buf); ++ miu_bw_close_file(pstOutFd); ++ } ++ ++ kfree(u8Buf); ++ } ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_hw_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ int id; ++ int iMiuClientNum = 0; ++ int iMonitorDuration = 0; ++ int iMonitorOutputKmsg = 1; ++ int iMonitorDumpToFile = 0; ++ int iMiuBankAddr = 0; ++ struct miu_client *pstMiuClient = NULL; ++ ++ char* u8Buf = NULL; ++ char* u8Ptr = NULL; ++ char* u8PtrEnd = NULL; ++ struct file *pstOutFd = NULL; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU0_CLIENT_NUM; ++ iMonitorDuration = gmonitor_duration[0]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[0]; ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ pstMiuClient = &miu0_clients[0]; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuClientNum = MIU1_CLIENT_NUM; ++ iMonitorDuration = gmonitor_duration[1]; ++ iMonitorOutputKmsg = gmonitor_output_kmsg[1]; ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ pstMiuClient = &miu1_clients[0]; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) { ++ (pstMiuClient + i)->effi_min = 0x3FF; ++ (pstMiuClient + i)->effi_avg = 0; ++ (pstMiuClient + i)->effi_max = 0; ++ (pstMiuClient + i)->bw_avg = 0; ++ (pstMiuClient + i)->bw_max = 0; ++ (pstMiuClient + i)->bw_min = 0x3FF; ++ ++ if ((pstMiuClient + i)->bw_dump_en) { ++ iMonitorDumpToFile = 1; ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ u8Buf = kmalloc(DUMP_FILE_TEMP_BUF_SZ, GFP_KERNEL); ++ u8Ptr = u8Buf; ++ u8PtrEnd = u8Buf + (DUMP_FILE_TEMP_BUF_SZ); ++ ++ pstOutFd = miu_bw_open_file(m_bOutputFilePath, O_WRONLY | O_CREAT, 0644); ++ } ++ ++ if (iMonitorOutputKmsg) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < iMiuClientNum; i++) ++ { ++ if ((pstMiuClient + i)->bw_enabled && (pstMiuClient + i)->bw_rsvd == 0) ++ { ++ id = (pstMiuClient + i)->bw_client_id; ++ OUTREG16((iMiuBankAddr+REG_ID_15), (id & 0x40) ? 0x80 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0333); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); // set to read efficiency ++ msleep(iMonitorDuration); ++ (pstMiuClient + i)->effi_avg = INREG16((iMiuBankAddr+REG_ID_0E)); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read average bandwidth ++ msleep(iMonitorDuration); ++ (pstMiuClient + i)->bw_avg=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x50)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x51)); // set to read peak bandwidth ++ msleep(iMonitorDuration); ++ (pstMiuClient + i)->bw_max=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x20)) ;//reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x21)) ;//set to read average ++ msleep(iMonitorDuration); ++ (pstMiuClient + i)->bw_avg_div_effi=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x60)) ;//reset ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0303); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x61)) ;//set to read peak ++ msleep(iMonitorDuration); ++ (pstMiuClient + i)->bw_max_div_effi=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ ++ ++ // client effiency never changes and total BW is zero ++ if ((pstMiuClient + i)->bw_avg == 0 && ++ (pstMiuClient + i)->bw_max == 0 && ++ (pstMiuClient + i)->bw_avg_div_effi == 0 && ++ (pstMiuClient + i)->bw_max_div_effi == 0) ++ { ++ (pstMiuClient + i)->effi_avg = 0x3FF; ++ } ++ ++ ++ if (iMonitorOutputKmsg) ++ { ++ printk("%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)(pstMiuClient + i)->bw_client_id, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_avg_div_effi*10000/1024)%100, ++ (pstMiuClient + i)->bw_max_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_max_div_effi*10000/1024)%100); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%d:%s\t%2d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\t%02d.%02d%%\n", ++ (short)i, ++ (pstMiuClient + i)->name, ++ (pstMiuClient + i)->effi_avg*100/1024, ++ ((pstMiuClient + i)->effi_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg*100/1024, ++ ((pstMiuClient + i)->bw_avg*10000/1024)%100, ++ (pstMiuClient + i)->bw_max*100/1024, ++ ((pstMiuClient + i)->bw_max*10000/1024)%100, ++ (pstMiuClient + i)->bw_avg_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_avg_div_effi*10000/1024)%100, ++ (pstMiuClient + i)->bw_max_div_effi*100/1024, ++ ((pstMiuClient + i)->bw_max_div_effi*10000/1024)%100); ++ } ++ } ++ } ++ ++ if (iMonitorDumpToFile) { ++ if (pstOutFd) { ++ miu_bw_write_file(pstOutFd, u8Buf, u8Ptr - u8Buf); ++ miu_bw_close_file(pstOutFd); ++ } ++ ++ kfree(u8Buf); ++ } ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++#ifdef CONFIG_CAM_CLK ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int dram_type = 0; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ iAtopBankAddr = BASE_REG_ATOP1_PA; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", CamClkRateGet(CAMCLK_ddrpll_clk) / 1000000); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", CamClkRateGet(CAMCLK_miupll_clk) / 1000000); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ str += scnprintf(str, end - str, "SSC: %s\n", (INREGMSK16(iAtopBankAddr + REG_ID_14, 0xC000)==0x8000)? "OFF" : "ON"); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++#else //CONFIG_CAM_CLK ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int iMiupllBankAddr = 0; ++ unsigned int dram_type = 0; ++ unsigned int ddfset = 0; ++ unsigned int dram_freq = 0; ++ unsigned int miupll_freq = 0; ++ ++ if ('0'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#if MIU_NUM > 1 ++ else if ('1'== (dev->kobj.name[3])) { ++ iMiuBankAddr = BASE_REG_MIU1_PA; ++ iAtopBankAddr = BASE_REG_ATOP1_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#endif ++ else { ++ return 0; ++ } ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ddfset = (INREGMSK16(iAtopBankAddr + REG_ID_19, 0x00FF) << 16) + INREGMSK16(iAtopBankAddr + REG_ID_18, 0xFFFF); ++ dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ miupll_freq = 24 * INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x00FF) / ((INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x0700) >> 8) + 2); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", dram_freq); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", miupll_freq); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ str += scnprintf(str, end - str, "SSC: %s\n", (INREGMSK16(iAtopBankAddr + REG_ID_14, 0xC000)==0x8000)? "OFF" : "ON"); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++#endif ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++DEVICE_ATTR(monitor_client_dump_enable, 0644, monitor_client_dump_enable_show, monitor_client_dump_enable_store); ++DEVICE_ATTR(monitor_client_filter_enable, 0644, monitor_filter_abnormal_value_show, monitor_filter_abnormal_value_store); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++DEVICE_ATTR(measure_all_hw, 0644, measure_all_hw_show, measure_all_store); ++DEVICE_ATTR(dram_info, 0444, dram_info_show, NULL); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret = 0; ++ ++ miu0.index = 0; ++ miu0.dev.kobj.name = "miu0"; ++ miu0.dev.bus = &miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&miu0.dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu0.dev, &dev_attr_measure_all); ++ device_create_file(&miu0.dev, &dev_attr_measure_all_hw); ++ device_create_file(&miu0.dev, &dev_attr_dram_info); ++ ++#if MIU_NUM > 1 ++ miu1.index = 0; ++ miu1.dev.kobj.name = "miu1"; ++ miu1.dev.bus = &miu_subsys; ++ ++#if 0 // Don't register again ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++#endif ++ ++ ret = device_register(&miu1.dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu1 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu1.dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_dump_enable); ++ device_create_file(&miu1.dev, &dev_attr_monitor_client_filter_enable); ++ device_create_file(&miu1.dev, &dev_attr_measure_all); ++ device_create_file(&miu1.dev, &dev_attr_measure_all_hw); ++ device_create_file(&miu1.dev, &dev_attr_dram_info); ++#endif ++} +diff --git a/arch/arm/mach-sstar/infinity6b0/pm.c b/arch/arm/mach-sstar/infinity6b0/pm.c +new file mode 100755 +index 000000000000..9537114f8e15 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6b0/pm.c +@@ -0,0 +1,80 @@ ++/* ++* pm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void sram_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&sram_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity6b0/soc.c b/arch/arm/mach-sstar/infinity6b0/soc.c +new file mode 100755 +index 000000000000..31e362df3d3c +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6b0/soc.c +@@ -0,0 +1,651 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "ms_msys.h" ++ ++//#define CONFIG_SS_MCM ++#define CONFIG_CHIP_FUNC_USB_VBUS_CONTROL ++//#define CONFIG_CHIP_FUNC_IR_ENABLE ++//#define CONFIG_CHIP_FUNC_UART_LINE ++ ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ {IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "sstar,infinity6b0", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++ ++ ++//extern struct timecounter *arch_timer_get_timecounter(void); ++ ++#ifdef CONFIG_SS_MCM ++ ++static int mcm_rw(int index, int ratio, int write); ++#endif ++ ++/************************************* ++* Sstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++#ifdef CONFIG_CHIP_FUNC_UART_LINE ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++#endif ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ volatile unsigned long dwLockFlag = 0; ++ volatile unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ dsb(); ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++/*//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NAND BIT2 ++#define STORAGE_SPI_NAND_SKIPSD BIT3 ++#define STORAGE_SPI_NOR_SKIPSD BIT4 ++#define STORAGE_SPI_NOR BIT5 ++*/ ++ u8 type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & 0x3C); ++ ++ if(BIT3 == type || BIT2 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else if(BIT5 == type || BIT4 == type) ++ return (int)MS_STORAGE_NOR; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int mstar_get_package_type(void) ++{ ++ if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S01A")) ++ return MS_I6_PACKAGE_BGA_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S02A-256M") || !strcmp(&mstar_soc_dev_attr.machine[10], "MSC250C")) ++ return MS_I6_PACKAGE_DDR3_1866_256MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S04A")) ++ return MS_I6_PACKAGE_QFN_DDR3_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S03A-64M")) ++ return MS_I6_PACKAGE_QFN_DDR2_64MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "FPGA")) ++ return MS_I6_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I6_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]=CONFIG_SSTAR_SHORT_NAME; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++#ifdef CONFIG_CHIP_FUNC_IR_ENABLE ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++#endif ++#ifdef CONFIG_CHIP_FUNC_USB_VBUS_CONTROL ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ //printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ //printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++#endif ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ u64 cycles=arch_timer_read_counter(); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ us_ticks_cycle_offset=arch_timer_read_counter(); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++#ifdef CONFIG_CHIP_FUNC_UART_LINE ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++#endif ++#ifdef CONFIG_CHIP_FUNC_IR_ENABLE ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++#endif ++#ifdef CONFIG_CHIP_FUNC_USB_VBUS_CONTROL ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++#endif ++#ifdef CONFIG_SS_MCM ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++#endif ++ default: ++ BUG(); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsb ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++#ifdef CONFIG_SS_MCM ++struct mcm_client{ ++ char* name; ++ short index; ++ unsigned int reg; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, OFFSET_MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, OFFSET_MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, OFFSET_MCM_ID_BDMA, 0}, ++ {"MFE", MCM_ID_MFE, OFFSET_MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, OFFSET_MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, OFFSET_MCM_ID_BACH, 0}, ++ {"FILE", MCM_ID_FILE, OFFSET_MCM_ID_FILE, 0}, ++ {"UHC0", MCM_ID_UHC0, OFFSET_MCM_ID_UHC0, 0}, ++ {"EMAC", MCM_ID_EMAC, OFFSET_MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, OFFSET_MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, OFFSET_MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, OFFSET_MCM_ID_ISP_DMA, 0}, ++ {"GOP0", MCM_ID_GOP0, OFFSET_MCM_ID_GOP0, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, OFFSET_MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, OFFSET_MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, OFFSET_MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, OFFSET_MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, OFFSET_MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, OFFSET_MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, OFFSET_MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, OFFSET_MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, OFFSET_MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, OFFSET_MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, OFFSET_MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, OFFSET_MCM_ID_SC2_SNPI, 0}, ++ {"CMDQ1", MCM_ID_CMDQ1, OFFSET_MCM_ID_CMDQ1, 0}, ++ {"CMDQ2", MCM_ID_CMDQ2, OFFSET_MCM_ID_CMDQ2, 0}, ++ {"GOP1", MCM_ID_GOP1, OFFSET_MCM_ID_GOP1, 0}, ++ {"GOP2", MCM_ID_GOP2, OFFSET_MCM_ID_GOP2, 0}, ++ {"UHC1", MCM_ID_UHC1, OFFSET_MCM_ID_UHC1, 0}, ++ {"IVE", MCM_ID_IVE, OFFSET_MCM_ID_IVE, 0}, ++ {"VHE", MCM_ID_VHE, OFFSET_MCM_ID_VHE, 0}, ++ {"*ALL_CLIENTS",MCM_ID_ALL, 0, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ ++ return 0; ++ } ++ ++ if((index >= MCM_ID_START) &&(index < MCM_ID_END)) ++ { ++ addr = mcm_clients[index].reg; ++ } ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++#endif ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++#ifdef CONFIG_SS_MCM ++ mstar_create_MCM_node(); ++#endif ++} ++ ++static void global_reset(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ msys_set_rebootType(MSYS_REBOOT_BY_SW_RST); ++ ++ while(1) ++ { ++#if defined(CONFIG_MS_SERIAL) ++ OUTREG8(0x1f221000, 0x30+i); ++#endif ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = global_reset, ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity6b0/sram.S b/arch/arm/mach-sstar/infinity6b0/sram.S +new file mode 100755 +index 000000000000..464b0fa4a07d +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6b0/sram.S +@@ -0,0 +1,191 @@ ++/* ++* sram.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl sram_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(sram_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(sram_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6e/Kconfig b/arch/arm/mach-sstar/infinity6e/Kconfig +new file mode 100755 +index 000000000000..b5bb384b4d5d +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/Kconfig +@@ -0,0 +1,18 @@ ++config ARCH_INFINITY6E ++ bool "SoC iNfinity6E (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity6E SoC ++ ++config SS_PROFILING_TIME ++ bool "Record timestamp in sram" ++ default y ++ ++config SS_MIU_ARBITRATION ++ bool "SigmaStar MIU arbitration" ++ default y +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6e/Makefile b/arch/arm/mach-sstar/infinity6e/Makefile +new file mode 100755 +index 000000000000..f7995e4011ef +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/Makefile +@@ -0,0 +1,10 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += soc.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o ++obj-$(CONFIG_SMP) += smp_platform.o smp_head.o ++obj-$(CONFIG_SS_MIU_ARBITRATION) += miu_arb.o +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/infinity6e/miu_arb.c b/arch/arm/mach-sstar/infinity6e/miu_arb.c +new file mode 100755 +index 000000000000..3ec2a87be2d4 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/miu_arb.c +@@ -0,0 +1,1074 @@ ++/* ++* miu_arb.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Alterman.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "miu_bw.h" ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_arb_handle { ++ char name[12]; // device name (miu_arbx) ++ char dump; // dump mode: readable text, register table ++ char group_selected; // group selected, 0~(MIU_GRP_NUM-1) ++ char client_selected; // client selected, 1~(MIU_CLIENT_NUM-2) ++}; ++ ++struct miu_arb_grp_reg { ++ u16 cfg; // inner group arbitration config ++ #define REG_IGRP_CFG(g) (REG_ID_20 + BK_REG(0x10*g)) ++ #define IGCFG_ROUND_ROBIN_BIT 0x0001 // bit 0 ++ #define IGCFG_FIX_PRIO_BIT 0x0002 // bit 1 ++ #define IGCFG_MBR_LIMIT_EN_BIT 0x0004 // bit 2 ++ #define IGCFG_GRP_LIMIT_EN_BIT 0x0008 // bit 3 ++ #define IGCFG_FCTL0_EN_BIT 0x0100 // bit 8 ++ #define IGCFG_FCTL1_EN_BIT 0x0200 // bit 9 ++ u16 burst; // bit[7:0] member burst length; bit[15:8] group burst length ++ #define REG_IGRP_BURST(g) (REG_ID_21 + BK_REG(0x10*g)) ++ #define IGBURST_MBR_SHIFT 0 ++ #define IGBURST_MBR_MASK 0x00FF ++ #define IGBURST_GRP_SHIFT 8 ++ #define IGBURST_GRP_MASK 0xFF00 ++ u16 flowctrl0; ++ #define REG_IGRP_FCTL0(g) (REG_ID_2A + BK_REG(0x10*g)) ++ #define IGFCTL_ID0_SHIFT 0 ++ #define IGFCTL_ID0_MASK 0x000F ++ #define IGFCTL_ID1_SHIFT 4 ++ #define IGFCTL_ID1_MASK 0x00F0 ++ #define IGFCTL_PERIOD_SHIFT 8 ++ #define IGFCTL_PERIOD_MASK 0xFF00 ++ u16 flowctrl1; ++ #define REG_IGRP_FCTL1(g) (REG_ID_2B + BK_REG(0x10*g)) ++ u16 mbr_priority; ++ #define REG_IGRP_MBR_PRIO(g) (REG_ID_2C + BK_REG(0x10*g)) ++ #define IGMBR_PRIO(mbr,pri) (pri << mbr) ++ #define IGMBR_PRIO_MASK(mbr) (1 << mbr) ++ #define IGMBR_PRIO_SHIFT(mbr) (mbr) ++ u16 mbr_nolimit; ++ #define REG_IGRP_MBR_NOLIMIT(g) (REG_ID_2E + BK_REG(0x10*g)) ++ #define IGMBR_NOLIMIT_EN(mbr) (1 << mbr) ++}; ++ ++struct miu_arb_reg { ++ struct miu_arb_grp_reg grp[MIU_GRP_NUM]; ++ u16 cfg; // outer groups arbitration config ++ #define REG_OGRP_CFG (REG_ID_7F) ++ #define OGCFG_GRP_PRIO_SHIRT(p) (p << 1) ++ #define OGCFG_GRP_PRIO_MASK(p) (0x3 << (p << 1)) ++ #define OGCFG_FIX_PRIO_EN 0x0100 // bit 8 ++ #define OGCFG_ROUND_ROBIN_EN 0x1000 // bit 12 ++}; ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_device arb_dev[MIU_NUM]; ++static struct miu_arb_handle arb_handle[MIU_NUM]; ++// default policy ++static struct miu_arb_reg arb_policy_def = { ++ { ++ { // group 0 ++ .cfg = 0x801D, ++ .burst = 0x1008, ++ .flowctrl0 = 0x0000, ++ .flowctrl1 = 0x0000, ++ .mbr_priority = 0x1000, ++ .mbr_nolimit = 0x0000 ++ }, ++ { // group 1 ++ .cfg = 0x801D, ++ .burst = 0x2010, ++ .flowctrl0 = 0x0000, ++ .flowctrl1 = 0x0000, ++ .mbr_priority = 0x0000, ++ .mbr_nolimit = 0x0000 ++ }, ++ { // group 2 ++ .cfg = 0x801D, ++ .burst = 0x2010, ++ .flowctrl0 = 0x0000, ++ .flowctrl1 = 0x0000, ++ .mbr_priority = 0x0000, ++ .mbr_nolimit = 0x0000 ++ }, ++ }, ++ .cfg = 0x9000, ++}; ++ ++// BGA2 default policy ++static struct miu_arb_reg arb_policy_bga2_def = { ++ { ++ { // group 0 ++ .cfg = 0x800D, ++ .burst = 0x2010, ++ .flowctrl0 = 0x0000, ++ .flowctrl1 = 0x0000, ++ .mbr_priority = 0x1000, ++ .mbr_nolimit = 0x0000 ++ }, ++ { // group 1 ++ .cfg = 0x800D, ++ .burst = 0x2010, ++ .flowctrl0 = 0x0000, ++ .flowctrl1 = 0x0000, ++ .mbr_priority = 0x0180, ++ .mbr_nolimit = 0x0000 ++ }, ++ { // group 2 ++ .cfg = 0x800D, ++ .burst = 0x2010, ++ .flowctrl0 = 0x0000, ++ .flowctrl1 = 0x0000, ++ .mbr_priority = 0x0000, ++ .mbr_nolimit = 0x0000 ++ }, ++ }, ++ .cfg = 0x9000, ++}; ++ ++static struct miu_arb_reg *arb_policies[MIU_ARB_POLICY_NUM] = { ++ &arb_policy_def, &arb_policy_bga2_def, ++}; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++static int _get_reg_base(int miu) ++{ ++ if (miu == 0) { ++ return BASE_REG_MIU_PA; ++ } ++ printk(KERN_ERR "MIU%d reg base not assigend\n", miu); ++ return 0; ++} ++ ++static void _load_group_settings(struct miu_arb_grp_reg *greg, int base, int g) ++{ ++ if (greg) { ++ greg->cfg = INREG16(base+REG_IGRP_CFG(g)); ++ greg->burst = INREG16(base+REG_IGRP_BURST(g)); ++ greg->flowctrl0 = INREG16(base+REG_IGRP_FCTL0(g)); ++ greg->flowctrl1 = INREG16(base+REG_IGRP_FCTL1(g)); ++ greg->mbr_priority = INREG16(base+REG_IGRP_MBR_PRIO(g)); ++ greg->mbr_nolimit = INREG16(base+REG_IGRP_MBR_NOLIMIT(g)); ++ } ++} ++ ++static bool _is_flowctrl_enable(struct miu_arb_grp_reg *greg, int mbr, char *period) ++{ ++ *period = 0; ++ if (greg->cfg & IGCFG_FCTL0_EN_BIT) { ++ if (mbr == ((greg->flowctrl0 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT)) { ++ *period = (greg->flowctrl0 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ return 1; ++ } ++ if (mbr == ((greg->flowctrl0 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT)) { ++ *period = (greg->flowctrl0 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ return 1; ++ } ++ } ++ if (greg->cfg & IGCFG_FCTL1_EN_BIT) { ++ if (mbr == ((greg->flowctrl1 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT)) { ++ *period = (greg->flowctrl1 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ return 1; ++ } ++ if (mbr == ((greg->flowctrl1 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT)) { ++ *period = (greg->flowctrl1 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ return 1; ++ } ++ } ++ return 0; ++} ++ ++static bool _enable_flowctrl(struct miu_arb_grp_reg *greg, int mbr, bool enable, char period) ++{ ++ int id[2][2], peri[2]; ++ ++ id[0][0] = (greg->flowctrl0 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT; ++ id[0][1] = (greg->flowctrl0 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT; ++ peri[0] = (greg->flowctrl0 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ id[1][0] = (greg->flowctrl1 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT; ++ id[1][1] = (greg->flowctrl1 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT; ++ peri[1] = (greg->flowctrl1 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ ++ if (enable) ++ { ++ do { ++ // enabled group flow control cnt0 has the same period ++ if ((greg->cfg & IGCFG_FCTL0_EN_BIT) && (peri[0] == period) && (id[0][0] == id[0][1])) { ++ greg->flowctrl0 &= ~(IGFCTL_ID1_MASK); ++ greg->flowctrl0 |= (mbr << IGFCTL_ID1_SHIFT); ++ break; ++ } ++ else if ((greg->cfg & IGCFG_FCTL1_EN_BIT) && (peri[1] == period) && (id[1][0] == id[1][1])) { ++ greg->flowctrl1 &= ~(IGFCTL_ID1_MASK); ++ greg->flowctrl1 |= (mbr << IGFCTL_ID1_SHIFT); ++ break; ++ } ++ else if (!(greg->cfg & IGCFG_FCTL0_EN_BIT)) { ++ greg->flowctrl0 = (mbr << IGFCTL_ID0_SHIFT)|(mbr << IGFCTL_ID1_SHIFT)|(period << IGFCTL_PERIOD_SHIFT); ++ greg->cfg |= IGCFG_FCTL0_EN_BIT; ++ break; ++ } ++ else if (!(greg->cfg & IGCFG_FCTL1_EN_BIT)) { ++ greg->flowctrl1 = (mbr << IGFCTL_ID0_SHIFT)|(mbr << IGFCTL_ID1_SHIFT)|(period << IGFCTL_PERIOD_SHIFT); ++ greg->cfg |= IGCFG_FCTL1_EN_BIT; ++ break; ++ } ++ printk(KERN_ERR "No free flow control id for period %d\n", period); ++ return 1; // not free one, failed ++ } while(1); ++ } ++ else ++ { ++ // disable client flow control ++ if (greg->cfg & IGCFG_FCTL0_EN_BIT) { ++ if ((mbr == id[0][0]) && (id[0][0] == id[0][1])) { ++ greg->flowctrl0 &= (u16)(~(IGFCTL_ID0_MASK | IGFCTL_ID1_MASK | IGFCTL_PERIOD_MASK)); ++ greg->cfg &= ~(IGCFG_FCTL0_EN_BIT); ++ } ++ else if (mbr == id[0][0]) { ++ greg->flowctrl0 &= ~(IGFCTL_ID0_MASK); ++ greg->flowctrl0 |= (id[0][1] << IGFCTL_ID0_SHIFT); // set id0 as id1 ++ } ++ else if (mbr == id[0][1]) { ++ greg->flowctrl0 &= ~(IGFCTL_ID1_MASK); ++ greg->flowctrl0 |= (id[0][0] << IGFCTL_ID1_SHIFT); // set id1 as id0 ++ } ++ } ++ if (greg->cfg & IGCFG_FCTL1_EN_BIT) { ++ if ((mbr == id[1][0]) && (id[1][0] == id[1][1])) { ++ greg->flowctrl1 &= (u16)(~(IGFCTL_ID0_MASK | IGFCTL_ID1_MASK | IGFCTL_PERIOD_MASK)); ++ greg->cfg &= ~(IGCFG_FCTL1_EN_BIT); ++ } ++ else if (mbr == id[1][0]) { ++ greg->flowctrl1 &= ~(IGFCTL_ID0_MASK); ++ greg->flowctrl1 |= (id[1][1] << IGFCTL_ID0_SHIFT); // set id0 as id1 ++ } ++ else if (mbr == id[1][1]) { ++ greg->flowctrl1 &= ~(IGFCTL_ID1_MASK); ++ greg->flowctrl1 |= (id[1][0] << IGFCTL_ID1_SHIFT); // set id1 as id0 ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static void _load_policy(int miu, int idx) ++{ ++ int base; ++ int g; ++ struct miu_arb_reg *reg; ++ ++ if (idx >= MIU_ARB_POLICY_NUM) { ++ return; ++ } ++ ++ base = _get_reg_base(miu); ++ if (!base) { ++ return; ++ } ++ ++ reg = arb_policies[idx]; ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ OUTREG16(base+REG_IGRP_CFG(g), reg->grp[g].cfg); ++ OUTREG16(base+REG_IGRP_BURST(g), reg->grp[g].burst); ++ OUTREG16(base+REG_IGRP_FCTL0(g), reg->grp[g].flowctrl0); ++ OUTREG16(base+REG_IGRP_FCTL1(g), reg->grp[g].flowctrl1); ++ OUTREG16(base+REG_IGRP_MBR_PRIO(g), reg->grp[g].mbr_priority); ++ OUTREG16(base+REG_IGRP_MBR_NOLIMIT(g), reg->grp[g].mbr_nolimit); ++ } ++ OUTREG16((base+REG_OGRP_CFG), reg->cfg); ++} ++ ++static char *_dump_as_text(char *str, char *end, unsigned char miu) ++{ ++ int g, mbr, c, base; ++ u16 outer_cfg, mbr_burst, mbr_prio; ++ struct miu_arb_grp_reg greg; ++ ++ base = _get_reg_base(miu); ++ if (!base) { ++ return str; ++ } ++ ++ outer_cfg = INREG16(base+REG_OGRP_CFG); ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ /* Group settings */ ++ _load_group_settings(&greg, base, g); ++ str += scnprintf(str, end - str, ASCII_COLOR_BLUE"==== Group %d ================================\n"ASCII_COLOR_END, g); ++ str += scnprintf(str, end - str, " Outer-Prio: "); ++ if (outer_cfg & OGCFG_ROUND_ROBIN_EN) { ++ str += scnprintf(str, end - str, "Round-Robin\n"); ++ } ++ else if (outer_cfg & OGCFG_FIX_PRIO_EN) { ++ int p = 0; ++ while(p < MIU_ARB_OG_PRIO_NUM) { ++ if (((outer_cfg & OGCFG_GRP_PRIO_MASK(p)) >> OGCFG_GRP_PRIO_MASK(p)) == g) { ++ break; ++ } ++ p++; ++ }; ++ str += scnprintf(str, end - str, "%d\n", p); ++ } ++ str += scnprintf(str, end - str, " Inner-Prio: %s\n", (greg.cfg & IGCFG_ROUND_ROBIN_BIT) ? ++ "Round-Robin" : ++ "Fix priority"); ++ str += scnprintf(str, end - str, " Burst : %d\n", (greg.cfg & IGCFG_GRP_LIMIT_EN_BIT) ? ++ (greg.burst & IGBURST_GRP_MASK) >> IGBURST_GRP_SHIFT : ++ 0); // no limit ++ str += scnprintf(str, end - str, " FlowCtrl0 : "); ++ if (greg.cfg & IGCFG_FCTL0_EN_BIT) { ++ c = (g * MIU_GRP_CLIENT_NUM) + ((greg.flowctrl0 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT); ++ if (!miu_client_reserved(c)) { ++ str += scnprintf(str, end - str, "%s, ", miu_client_id_to_name(c)); ++ } ++ c = (g * MIU_GRP_CLIENT_NUM) + ((greg.flowctrl0 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT); ++ if (!miu_client_reserved(c)) { ++ str += scnprintf(str, end - str, "%s, ", miu_client_id_to_name(c)); ++ } ++ str += scnprintf(str, end - str, "Preiod 0x%02X\n", (greg.flowctrl0 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT); ++ } ++ else { ++ str += scnprintf(str, end - str, "None\n"); ++ } ++ str += scnprintf(str, end - str, " FlowCtrl1 : "); ++ if (greg.cfg & IGCFG_FCTL1_EN_BIT) { ++ c = (g * MIU_GRP_CLIENT_NUM) + ((greg.flowctrl1 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT); ++ if (!miu_client_reserved(c)) { ++ str += scnprintf(str, end - str, "%s, ", miu_client_id_to_name(c)); ++ } ++ c = (g * MIU_GRP_CLIENT_NUM) + ((greg.flowctrl1 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT); ++ if (!miu_client_reserved(c)) { ++ str += scnprintf(str, end - str, "%s, ", miu_client_id_to_name(c)); ++ } ++ str += scnprintf(str, end - str, "Preiod 0x%02X\n", (greg.flowctrl1 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT); ++ } ++ else { ++ str += scnprintf(str, end - str, "None\n"); ++ } ++ ++ /* Merber settings */ ++ str += scnprintf(str, end - str, ASCII_COLOR_BLUE"---------------------------------------------\n"ASCII_COLOR_END); ++ str += scnprintf(str, end - str, "Id:Client\tBurst\tPriority\n"); ++ for (mbr = 0; mbr < MIU_GRP_CLIENT_NUM; mbr++) { ++ c = (g * MIU_GRP_CLIENT_NUM) + mbr; ++ if (!miu_client_reserved(c)) { ++ if ((greg.cfg & IGCFG_MBR_LIMIT_EN_BIT) && !(greg.mbr_nolimit & IGMBR_NOLIMIT_EN(mbr))) { ++ mbr_burst = (greg.burst & IGBURST_MBR_MASK) >> IGBURST_MBR_SHIFT; ++ } ++ else { ++ mbr_burst = 0; // not limit ++ } ++ if (greg.cfg & IGCFG_ROUND_ROBIN_BIT) { ++ mbr_prio = (greg.mbr_priority & IGMBR_PRIO_MASK(mbr)) >> IGMBR_PRIO_SHIFT(mbr); ++ } ++ else { ++ mbr_prio = 0xFF; // TODO: parse ID for fixed priority ++ } ++ str += scnprintf(str, end - str, "%2d:%s\t%d\t%d\n", c, miu_client_id_to_name(c), mbr_burst, mbr_prio); ++ } ++ } ++ } ++ ++ return str; ++} ++ ++static char *_dump_as_reg(char *str, char *end, unsigned char miu) ++{ ++ int g; ++ int base; ++ struct miu_arb_grp_reg greg; ++ ++ base = _get_reg_base(miu); ++ if (!base) { ++ return str; ++ } ++ ++ // miu0 ++ str += scnprintf(str, end - str, " // miu%d\n", miu); ++ str += scnprintf(str, end - str, " {\n"); ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ _load_group_settings(&greg, base, g); ++ str += scnprintf(str, end - str, " { // group %d\n", g); ++ str += scnprintf(str, end - str, " .cfg = 0x%04X,\n", greg.cfg); ++ str += scnprintf(str, end - str, " .burst = 0x%04X,\n", greg.burst); ++ str += scnprintf(str, end - str, " .flowctrl0 = 0x%04X,\n", greg.flowctrl0); ++ str += scnprintf(str, end - str, " .flowctrl1 = 0x%04X,\n", greg.flowctrl1); ++ str += scnprintf(str, end - str, " .mbr_priority = 0x%04X,\n", greg.mbr_priority); ++ str += scnprintf(str, end - str, " .mbr_nolimit = 0x%04X,\n", greg.mbr_nolimit); ++ str += scnprintf(str, end - str, " },\n"); ++ } ++ str += scnprintf(str, end - str, " },\n"); ++ str += scnprintf(str, end - str, " .cfg = 0x%04X,\n", INREG16(base+REG_OGRP_CFG)); ++ ++ return str; ++} ++ ++static ssize_t client_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ u32 c = 0; ++ ++ c = simple_strtoul(buf, NULL, 10); ++ if (c < MIU_ARB_CLIENT_NUM) ++ { ++ if (!miu_client_reserved(c)) { ++ arb_handle[m].client_selected = c; ++ } ++ else { ++ printk(KERN_ERR "Invalid client %d\n", c); ++ } ++ } ++ else ++ { ++ printk(KERN_ERR "Invalid client %d\n", c); ++ return count; ++ } ++ return count; ++} ++ ++static ssize_t client_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int c, g, i; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ str += scnprintf(str, end - str, "ID:IP_name\t"); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + i; ++ if (c != arb_handle[m].client_selected) ++ { ++ if (!miu_client_reserved(c)) ++ { ++ str += scnprintf(str, end - str, "%2d:%s\t", c, miu_client_id_to_name(c)); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%2d: \t", c); ++ } ++ } ++ else { ++ str += scnprintf(str, end - str, ASCII_COLOR_GREEN"%3d:%s\t"ASCII_COLOR_END, c, miu_client_id_to_name(c)); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(client, 0644, client_show, client_store); ++ ++static ssize_t group_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ u32 g = 0; ++ ++ g = simple_strtoul(buf, NULL, 10); ++ if (g < MIU_GRP_NUM) ++ { ++ arb_handle[m].group_selected = g; ++ } ++ else ++ { ++ printk(KERN_ERR "Invalid group %d\n", g); ++ return count; ++ } ++ return count; ++} ++ ++static ssize_t group_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int c, g, i; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ str += scnprintf(str, end - str, "ID:IP_name\t"); ++ } ++ str += scnprintf(str, end - str, "\n"); ++ ++ for(i = 0; i < MIU_GRP_CLIENT_NUM; i++) ++ { ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ c = (g * MIU_GRP_CLIENT_NUM) + i; ++ if (g != arb_handle[m].group_selected) ++ { ++ if (!miu_client_reserved(c)) ++ { ++ str += scnprintf(str, end - str, "%2d:%s\t", c, miu_client_id_to_name(c)); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "%2d: \t", c); ++ } ++ } ++ else ++ { ++ if (!miu_client_reserved(c)) ++ { ++ str += scnprintf(str, end - str, ASCII_COLOR_GREEN"%3d:%s\t"ASCII_COLOR_END, c, miu_client_id_to_name(c)); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, ASCII_COLOR_GREEN"%3d: \t"ASCII_COLOR_END, c); ++ } ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(group, 0644, group_show, group_store); ++ ++static ssize_t group_burst_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int g, base, burst; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ burst = simple_strtoul(buf, NULL, 10); ++ g = arb_handle[m].group_selected; ++ ++ printk(KERN_ERR "Set group %d burst %d\n", g, burst); ++ if (g < MIU_GRP_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return count; ++ } ++ ++ _load_group_settings(&greg, base, g); ++ if (burst == 0) { ++ greg.cfg &= ~(IGCFG_GRP_LIMIT_EN_BIT); ++ greg.burst &= ~(IGBURST_GRP_MASK); ++ } ++ else { ++ greg.cfg |= IGCFG_GRP_LIMIT_EN_BIT; ++ greg.burst = (greg.burst & ~(IGBURST_GRP_MASK)) | (burst << IGBURST_GRP_SHIFT); ++ } ++ OUTREG16(base+REG_IGRP_CFG(g), greg.cfg); ++ OUTREG16(base+REG_IGRP_BURST(g), greg.burst); ++ } ++ return count; ++} ++ ++static ssize_t group_burst_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int base, g; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ g = arb_handle[m].group_selected; ++ if (g < MIU_GRP_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return (str - buf); ++ } ++ _load_group_settings(&greg, base, g); ++ str += scnprintf(str, end - str, "Group %d burst: %d\n", g, (greg.cfg & IGCFG_GRP_LIMIT_EN_BIT) ? ++ (greg.burst & IGBURST_GRP_MASK) >> IGBURST_GRP_SHIFT : ++ 0); // no limit ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(group_burst, 0644, group_burst_show, group_burst_store); ++ ++static ssize_t group_member_burst_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int g, base, burst; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ burst = simple_strtoul(buf, NULL, 10); ++ g = arb_handle[m].group_selected; ++ ++ printk(KERN_ERR "Set group %d member burst %d\n", g, burst); ++ if (g < MIU_GRP_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return count; ++ } ++ ++ _load_group_settings(&greg, base, g); ++ if (burst == 0) { ++ greg.cfg &= ~(IGCFG_MBR_LIMIT_EN_BIT); ++ greg.burst &= ~(IGBURST_MBR_MASK); ++ } ++ else { ++ greg.cfg |= IGCFG_MBR_LIMIT_EN_BIT; ++ greg.burst = (greg.burst & ~(IGBURST_MBR_MASK)) | (burst << IGBURST_MBR_SHIFT); ++ } ++ OUTREG16(base+REG_IGRP_CFG(g), greg.cfg); ++ OUTREG16(base+REG_IGRP_BURST(g), greg.burst); ++ } ++ return count; ++} ++ ++static ssize_t group_member_burst_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int base, g; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ g = arb_handle[m].group_selected; ++ if (g < MIU_GRP_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return (str - buf); ++ } ++ _load_group_settings(&greg, base, g); ++ str += scnprintf(str, end - str, "Group %d member burst: %d\n", g, (greg.cfg & IGCFG_MBR_LIMIT_EN_BIT) ? ++ (greg.burst & IGBURST_MBR_MASK) >> IGBURST_MBR_SHIFT : ++ 0); // no limit ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(group_member_burst, 0644, group_member_burst_show, group_member_burst_store); ++ ++static ssize_t client_nolimit_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c, g, mbr, base, nolimit; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ nolimit = simple_strtoul(buf, NULL, 10); ++ c = arb_handle[m].client_selected; ++ g = c / MIU_GRP_CLIENT_NUM; ++ mbr = c % MIU_GRP_CLIENT_NUM; ++ ++ printk(KERN_ERR "Set client %d burst length to %s\n", c, nolimit ? "no limited" : "limited"); ++ if (c < MIU_ARB_CLIENT_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return count; ++ } ++ ++ _load_group_settings(&greg, base, g); ++ if (nolimit == 0) { ++ greg.mbr_nolimit &= ~(IGMBR_NOLIMIT_EN(mbr)); ++ if (!(greg.cfg & IGCFG_MBR_LIMIT_EN_BIT)) { ++ printk(KERN_ERR "Conflict: group %d member limit is disabled\n", g); ++ } ++ } ++ else { ++ greg.mbr_nolimit |= IGMBR_NOLIMIT_EN(mbr); ++ if (!(greg.cfg & IGCFG_MBR_LIMIT_EN_BIT)) { ++ printk(KERN_ERR "NoNeed: group %d member limit is disabled already\n", g); ++ } ++ } ++ OUTREG16(base+REG_IGRP_MBR_NOLIMIT(g), greg.mbr_nolimit); ++ } ++ return count; ++} ++ ++static ssize_t client_nolimit_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int base, c, g, mbr, burst; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ c = arb_handle[m].client_selected; ++ g = c / MIU_GRP_CLIENT_NUM; ++ mbr = c % MIU_GRP_CLIENT_NUM; ++ ++ if (c < MIU_ARB_CLIENT_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return (str - buf); ++ } ++ ++ _load_group_settings(&greg, base, g); ++ if (!(greg.cfg & IGCFG_MBR_LIMIT_EN_BIT) || (greg.mbr_nolimit & IGMBR_NOLIMIT_EN(mbr))) { ++ // group member burst is no-limited or the specified member has limit mask to 1 ++ burst = 0; ++ } ++ else { ++ burst = (greg.burst & IGBURST_MBR_MASK) >> IGBURST_MBR_SHIFT; ++ } ++ str += scnprintf(str, end - str, "Client %d burst length: %d, (0: no-limited)\n", c, burst); ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(client_nolimit, 0644, client_nolimit_show, client_nolimit_store); ++ ++static ssize_t client_prioprity_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c, g, mbr, base, priority; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ priority = simple_strtoul(buf, NULL, 10); ++ c = arb_handle[m].client_selected; ++ g = c / MIU_GRP_CLIENT_NUM; ++ mbr = c % MIU_GRP_CLIENT_NUM; ++ ++ printk(KERN_ERR "Set client %d priority to %d\n", c, priority ? 1 : 0); ++ if (c < MIU_ARB_CLIENT_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return count; ++ } ++ ++ _load_group_settings(&greg, base, g); ++ greg.mbr_priority = (greg.mbr_priority & ~(IGMBR_PRIO_MASK(mbr))) | IGMBR_PRIO(mbr, (priority ? 1 : 0)); ++ OUTREG16(base+REG_IGRP_MBR_PRIO(g), greg.mbr_priority); ++ } ++ return count; ++} ++ ++static ssize_t client_prioprity_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int base, c, g, mbr; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ c = arb_handle[m].client_selected; ++ g = c / MIU_GRP_CLIENT_NUM; ++ mbr = c % MIU_GRP_CLIENT_NUM; ++ ++ if (c < MIU_ARB_CLIENT_NUM) ++ { ++ base = _get_reg_base(m); ++ if (!base) { ++ return (str - buf); ++ } ++ ++ _load_group_settings(&greg, base, g); ++ str += scnprintf(str, end - str, "Client %d priority: %d\n", c, ++ ((greg.mbr_priority & IGMBR_PRIO_MASK(mbr)) >> IGMBR_PRIO_SHIFT(mbr))); ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(client_priority, 0644, client_prioprity_show, client_prioprity_store); ++ ++static ssize_t client_flowctrl_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int c, g, mbr, base; ++ ssize_t ret = count; ++ u32 enable, period, en_tmp; ++ char peri_tmp; ++ char *pt, *opt; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ c = arb_handle[m].client_selected; ++ if ((c == OVERALL_CLIENT_ID) || (c >= MIU_ARB_CLIENT_NUM) || miu_client_reserved(c)) { ++ printk(KERN_ERR "Invalid client %d, please set client by command: echo [id] > client\n", c); ++ return count; ++ } ++ ++ // check input parameters ++ do { ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ if ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ enable = simple_strtoul(opt, NULL, 10); ++ if (enable) ++ { ++ if ((opt = strsep(&pt, ";, ")) == NULL) ++ { ++ ret = 0; ++ break; ++ } ++ period = simple_strtoul(opt, NULL, 10); ++ if (!period || (period > (IGFCTL_PERIOD_MASK >> IGFCTL_PERIOD_SHIFT))) ++ { ++ printk(KERN_ERR "Invalid period %d (1-%d)\n", period, (IGFCTL_PERIOD_MASK >> IGFCTL_PERIOD_SHIFT)); ++ ret = 0; ++ break; ++ } ++ } ++ } ++ else { ++ ret = 0; ++ } ++ break; ++ }while(1); ++ ++ kfree(pt); ++ if (ret == 0) ++ { ++ printk(KERN_ERR "Usage: echo [0/1] [period] > client_flowctrl\n"); ++ return count; ++ } ++ ++ g = c / MIU_GRP_CLIENT_NUM; ++ mbr = c % MIU_GRP_CLIENT_NUM; ++ base = _get_reg_base(m); ++ if (!base) { ++ return count; ++ } ++ _load_group_settings(&greg, base, g); ++ ++ if (enable) ++ { ++ // to keep the original setting ++ en_tmp = _is_flowctrl_enable(&greg, mbr, &peri_tmp); ++ _enable_flowctrl(&greg, mbr, 0, 0); ++ // restore the original settings if failed ++ if (_enable_flowctrl(&greg, mbr, enable, period) && en_tmp) ++ { ++ _enable_flowctrl(&greg, mbr, en_tmp, peri_tmp); ++ } ++ } ++ else ++ { ++ // disable client flow control ++ _enable_flowctrl(&greg, mbr, 0, 0); ++ } ++ ++ OUTREG16(base+REG_IGRP_CFG(g), greg.cfg); ++ OUTREG16(base+REG_IGRP_FCTL0(g), greg.flowctrl0); ++ OUTREG16(base+REG_IGRP_FCTL1(g), greg.flowctrl1); ++ ++ return count; ++} ++ ++static ssize_t client_flowctrl_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int base, c[2], g, mbr[2], period; ++ struct miu_arb_grp_reg greg; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Flow Control:\n"); ++ str += scnprintf(str, end - str, "echo [id] > client\n"); ++ str += scnprintf(str, end - str, "enable: echo 1 [period] > client_flowctrl\n"); ++ str += scnprintf(str, end - str, "disable: echo 0 > client_flowctrl\n"); ++ ++ base = _get_reg_base(m); ++ if (!base) { ++ return (str - buf); ++ } ++ ++ str += scnprintf(str, end - str, "\nNum:IP_name\t[period]\n"); ++ for(g = 0; g < MIU_GRP_NUM; g++) ++ { ++ _load_group_settings(&greg, base, g); ++ if (greg.cfg & IGCFG_FCTL0_EN_BIT) { ++ mbr[0] = (greg.flowctrl0 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT; ++ mbr[1] = (greg.flowctrl0 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT; ++ period = (greg.flowctrl0 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ c[0] = (g * MIU_GRP_CLIENT_NUM) + mbr[0]; ++ c[1] = (g * MIU_GRP_CLIENT_NUM) + mbr[1]; ++ if (!miu_client_reserved(c[0])) { ++ str += scnprintf(str, end - str, "%3d:%s\t[ 0x%02X]\n", c[0], miu_client_id_to_name(c[0]), period); ++ } ++ if (!miu_client_reserved(c[1]) && (c[1] != c[0])) { ++ str += scnprintf(str, end - str, "%3d:%s\t[ 0x%02X]\n", c[1], miu_client_id_to_name(c[1]), period); ++ } ++ } ++ if (greg.cfg & IGCFG_FCTL1_EN_BIT) { ++ mbr[0] = (greg.flowctrl1 & IGFCTL_ID0_MASK) >> IGFCTL_ID0_SHIFT; ++ mbr[1] = (greg.flowctrl1 & IGFCTL_ID1_MASK) >> IGFCTL_ID1_SHIFT; ++ period = (greg.flowctrl1 & IGFCTL_PERIOD_MASK) >> IGFCTL_PERIOD_SHIFT; ++ c[0] = (g * MIU_GRP_CLIENT_NUM) + mbr[0]; ++ c[1] = (g * MIU_GRP_CLIENT_NUM) + mbr[1]; ++ if (!miu_client_reserved(c[0])) { ++ str += scnprintf(str, end - str, "%3d:%s\t[ 0x%02X]\n", c[0], miu_client_id_to_name(c[0]), period); ++ } ++ if (!miu_client_reserved(c[1]) && (c[1] != c[0])) { ++ str += scnprintf(str, end - str, "%3d:%s\t[ 0x%02X]\n", c[1], miu_client_id_to_name(c[1]), period); ++ } ++ } ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(client_flowctrl, 0644, client_flowctrl_show, client_flowctrl_store); ++ ++static ssize_t dump_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ if (input >= MIU_ARB_DUMP_MAX) ++ { ++ printk(KERN_ERR "Invalid dump mode %d (0: text; 1: reg)\n", input); ++ return count; ++ } ++ arb_handle[m].dump = input; ++ return count; ++} ++ ++static ssize_t dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned char m = MIU_IDX(dev->kobj.name[7]); ++ ++ str += scnprintf(str, end - str, "Dump Settings:\n"); ++ str += scnprintf(str, end - str, "text: echo 0 > dump\n"); ++ str += scnprintf(str, end - str, "reg : echo 1 > dump\n\n"); ++ ++ switch(arb_handle[m].dump) { ++ case MIU_ARB_DUMP_TEXT: ++ str = _dump_as_text(str, end, m); ++ break; ++ case MIU_ARB_DUMP_REG: ++ str = _dump_as_reg(str, end, m); ++ break; ++ default: ++ return 0; ++ } ++ return (str - buf); ++} ++ ++DEVICE_ATTR(dump, 0644, dump_show, dump_store); ++ ++#ifdef CONFIG_PM_SLEEP ++void miu_arb_resume(void) ++{ ++ int i, package; ++ ++ package = Chip_Get_Package_Type(); ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ if ((package == MS_I6E_PACKAGE_BGA2_DDR3) || (package == MS_I6E_PACKAGE_BGA_LPDDR2)) { ++ _load_policy(i, MIU_ARB_POLICY_BGA2_DEF); ++ } ++ else { ++ _load_policy(i, MIU_ARB_POLICY_DEF); ++ } ++ } ++ pr_debug("miu arb resume\n"); ++} ++#endif ++ ++void create_miu_arb_node(struct bus_type *miu_subsys) ++{ ++ int ret = 0, i; ++ int package; ++ ++ package = Chip_Get_Package_Type(); ++ memset(arb_handle, 0, sizeof(arb_handle)); ++ ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ strcpy(arb_handle[i].name, "miu_arb0"); ++ arb_handle[i].name[7] += i; ++ ++ arb_dev[i].index = 0; ++ arb_dev[i].dev.kobj.name = (const char *)arb_handle[i].name; ++ arb_dev[i].dev.bus = miu_subsys; ++ ++ ret = device_register(&arb_dev[i].dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register %s device!! %d\n", arb_dev[i].dev.kobj.name, ret); ++ return; ++ } ++ ++ device_create_file(&arb_dev[i].dev, &dev_attr_client); ++ device_create_file(&arb_dev[i].dev, &dev_attr_group); ++ device_create_file(&arb_dev[i].dev, &dev_attr_group_burst); ++ device_create_file(&arb_dev[i].dev, &dev_attr_group_member_burst); ++ device_create_file(&arb_dev[i].dev, &dev_attr_client_nolimit); ++ device_create_file(&arb_dev[i].dev, &dev_attr_client_priority); ++ device_create_file(&arb_dev[i].dev, &dev_attr_client_flowctrl); ++ device_create_file(&arb_dev[i].dev, &dev_attr_dump); ++ ++ if ((package == MS_I6E_PACKAGE_BGA2_DDR3) || (package == MS_I6E_PACKAGE_BGA_LPDDR2)) { ++ _load_policy(i, MIU_ARB_POLICY_BGA2_DEF); ++ } ++ else { ++ _load_policy(i, MIU_ARB_POLICY_DEF); ++ } ++ } ++} +diff --git a/arch/arm/mach-sstar/infinity6e/miu_bw.c b/arch/arm/mach-sstar/infinity6e/miu_bw.c +new file mode 100755 +index 000000000000..fbc6547fff1f +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/miu_bw.c +@@ -0,0 +1,609 @@ ++/* ++* miu_bw.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "miu_bw.h" ++#ifdef CONFIG_CAM_CLK ++#include "camclk.h" ++#include "drv_camclk_Api.h" ++#endif ++ ++ ++/*=============================================================*/ ++// Local variable ++/*=============================================================*/ ++ ++static struct miu_client miu_clients[MIU_CLIENT_NUM] = ++{ ++ {"OVERALL ",0x00,0}, ++ {"RSVD ",0x01,1}, ++ {"VEN ",0x02,0}, ++ {"USB30 ",0x03,0}, ++ {"JPE_R ",0x04,0}, ++ {"JPE_W ",0x05,0}, ++ {"BACH ",0x06,0}, ++ {"AESDMA ",0x07,0}, ++ {"USB20 ",0x08,0}, ++ {"EMAC ",0x09,0}, ++ {"MCU51 ",0x0A,0}, ++ {"URDMA ",0x0B,0}, ++ {"BDMA ",0x0C,0}, ++ {"MOVDMA ",0x0D,0}, ++ {"LDC ",0x0E,0}, ++ {"RSVD ",0x0F,1}, ++ {"CMDQ0_R ",0x10,0}, ++ {"ISP_DMA_W",0x11,0}, ++ {"ISP_DMA_R",0x12,0}, ++ {"ISP_ROT_R",0x13,0}, ++ {"ISP_MLOAD",0x14,0}, ++ {"GOP ",0x15,0}, ++ {"RSVD ",0x16,1}, ++ {"DIP0_R ",0x17,0}, ++ {"DIP0_W ",0x18,0}, ++ {"SC0_FRM_W",0x19,0}, ++ {"SC0_FRM_R",0x1A,0}, ++ {"SC0_DBG_R",0x1B,0}, ++ {"SC1_FRM_W",0x1C,0}, ++ {"SC2_FRM_W",0x1D,0}, ++ {"SD30 ",0x1E,0}, ++ {"SDIO30 ",0x1F,0}, ++ {"RSVD ",0x20,1}, ++ {"RSVD ",0x21,1}, ++ {"CSI_TX_R ",0x22,0}, ++ {"ISP_DMAG ",0x23,0}, ++ {"GOP1_R ",0x24,0}, ++ {"GOP2_R ",0x25,0}, ++ {"USB20_H ",0x26,0}, ++ {"MIIC2 ",0x27,0}, ++ {"MIIC1 ",0x28,0}, ++ {"3DNR0_W ",0x29,0}, ++ {"3DNR0_R ",0x2A,0}, ++ {"DLA ",0x2B,0}, ++ {"RSVD ",0x2C,1}, ++ {"RSVD ",0x2D,1}, ++ {"MIIC0 ",0x2E,0}, ++ {"IVE ",0x2F,0}, ++ {"CPU ",CPU_CLIENT_ID,0}, ++ {"DLA_HIWAY",DLA_HIWAY_ID,0}, ++}; ++ ++static char miu_devname[MIU_NUM][5]; ++static struct miu_client_bw miu_clients_bw[MIU_NUM][MIU_CLIENT_NUM]; ++static struct miu_device miu[MIU_NUM]; ++#ifdef CONFIG_PM_SLEEP ++int miu_subsys_suspend(struct device *dev); ++int miu_subsys_resume(struct device *dev); ++static SIMPLE_DEV_PM_OPS(miu_pm_ops, miu_subsys_suspend, miu_subsys_resume); ++#endif ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++#ifdef CONFIG_PM_SLEEP ++ .pm = &miu_pm_ops, ++#endif ++}; ++ ++static int gmonitor_duration[MIU_NUM] = {600};//{2000}; ++static int gmonitor_output_kmsg[MIU_NUM] = {1}; ++ ++/*=============================================================*/ ++// Local function ++/*=============================================================*/ ++short miu_client_reserved(U16 id) ++{ ++ if (id < MIU_CLIENT_NUM) ++ { ++ return miu_clients[id].rsvd; ++ } ++ else if (id == CPU_CLIENT_ID) ++ { ++ return miu_clients[MIU_CLIENT_NUM - 2].rsvd; ++ } ++ else if (id == DLA_HIWAY_ID) ++ { ++ return miu_clients[MIU_CLIENT_NUM - 1].rsvd; ++ } ++ return 1; ++} ++ ++const char* miu_client_id_to_name(U16 id) ++{ ++ if (id < MIU_CLIENT_NUM) ++ { ++ return miu_clients[id].name; ++ } ++ else if (id == CPU_CLIENT_ID) ++ { ++ return miu_clients[MIU_CLIENT_NUM - 2].name; ++ } ++ else if (id == DLA_HIWAY_ID) ++ { ++ return miu_clients[MIU_CLIENT_NUM - 1].name; ++ } ++ return NULL; ++} ++ ++static int set_miu_client_enable(struct device *dev, const char *buf, size_t n, int enabled) ++{ ++ long idx = -1; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (kstrtol(buf, 10, &idx) != 0 || ++ idx < 0 || ++ idx >= MIU_CLIENT_NUM) { ++ return -EINVAL; ++ } ++ if (miu_clients[idx].rsvd == 0) ++ { ++ miu_clients_bw[m][idx].enabled = enabled; ++ } ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if(!strncmp(buf, "all", strlen("all"))) ++ { ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ if (miu_clients[i].rsvd == 0) ++ { ++ miu_clients_bw[m][i].enabled = 1; ++ } ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 1); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ str += scnprintf(str, end - str, "Num:IP_name\t[ Idx][Enable(1)/Disable(0)]\n"); ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s\t[0x%02X][%d]\n", ++ i, ++ miu_clients[i].name, ++ miu_clients[i].id, ++ miu_clients_bw[m][i].enabled); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ if (!strncmp(buf, "all", strlen("all"))) ++ { ++ for (i = 0; i < MIU_CLIENT_NUM; i++) { ++ if (miu_clients[i].rsvd == 0) ++ { ++ miu_clients_bw[m][i].enabled = 0; ++ } ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev, opt, n, 0); ++ } ++ kfree(pt); ++ ++ return n; ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ str += scnprintf(str, end - str, "Num:IP_name\t[ Idx][Enable(1)/Disable(0)]\n"); ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s\t[0x%02X][%d]\n", ++ i, ++ miu_clients[i].name, ++ miu_clients[i].id, ++ miu_clients_bw[m][i].enabled); ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_duration[m] = input; ++ ++ return count; ++} ++ ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ return sprintf(buf, "%d\n", gmonitor_duration[m]); ++} ++ ++static ssize_t measure_all_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_output_kmsg[m] = input; ++ ++ return count; ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0; ++ int id; ++ int iMiuBankAddr = 0; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ short effi = 0, effi_last = 0, bw[4] = {0, 0, 0, 0}; /* BWavg, BWmax, BWavg/EFFI, BWmax/EFFI */ ++ ++ if (m == 0) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ } ++#if MIU_NUM > 1 ++ else { ++ printk("NOT support multiple MIUs\n"); ++ return 0; ++ } ++#endif ++ ++ if (gmonitor_output_kmsg[m]) { ++ printk("Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ printk("---------------------------------------------------------\n"); ++ } ++ else { ++ str += scnprintf(str, end - str, "Num:client\tEFFI\tBWavg\tBWmax\tBWavg/E\tBWmax/E\n"); ++ str += scnprintf(str, end - str, "---------------------------------------------------------\n"); ++ } ++ ++ for (i = 0; i < MIU_CLIENT_NUM; i++) ++ { ++ if (miu_clients_bw[m][i].enabled && (miu_clients[i].rsvd == 0)) ++ { ++ id = miu_clients[i].id; ++ OUTREG16((iMiuBankAddr+REG_ID_15), (id & 0x40) ? 0x80 : 0x00); ++ id = id & 0x3F; ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0404); ++ ++ /* client utilization */ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x40)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x41)); // set to read bandwidth ++ msleep(gmonitor_duration[m]); ++ bw[0] = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ /* client peak bandwidth */ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x50)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x51)); // set to read bandwidth ++ msleep(gmonitor_duration[m]); ++ bw[1] = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ /* client utilization / efficiency */ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x20)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x21)); // set to read bandwidth ++ msleep(gmonitor_duration[m]); ++ bw[2] = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ /* client peak bandwidth / efficiency */ ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x60)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x61)); // set to read bandwidth ++ msleep(gmonitor_duration[m]); ++ bw[3] = INREG16((iMiuBankAddr+REG_ID_0E)); ++ ++ /* client efficiency */ ++ // all measured BW are all zero, set effi to 99.9% ++ if ((bw[0] + bw[1] + bw[2] + bw[3]) == 0) { ++ effi = 0x3FF; ++ } ++ else ++ { ++ OUTREG16((iMiuBankAddr+REG_ID_29), 0x0444); ++ OUTREG16((iMiuBankAddr+REG_ID_0D), 0) ; // reset all ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x30)); // reset ++ OUTREG16((iMiuBankAddr+REG_ID_0D), ((id << 8) | 0x35)); ++ msleep(gmonitor_duration[m]); ++ effi = INREG16((iMiuBankAddr+REG_ID_0E)); ++ } ++ ++ if (gmonitor_output_kmsg[m]) { ++ if (effi_last != effi) { ++ printk("%3d:%s\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\n", ++ i, miu_clients[i].name, effi*100/1024, (effi*10000/1024)%100, ++ bw[0]*100/1024, (bw[0]*10000/1024)%100, bw[1]*100/1024, (bw[1]*10000/1024)%100, ++ bw[2]*100/1024, (bw[2]*10000/1024)%100, bw[3]*100/1024, (bw[3]*10000/1024)%100); ++ } ++ else { ++ printk("%3d:%s\t"ASCII_COLOR_RED"%2d.%02d%%"ASCII_COLOR_END"\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\n", ++ i, miu_clients[i].name, effi*100/1024, (effi*10000/1024)%100, ++ bw[0]*100/1024, (bw[0]*10000/1024)%100, bw[1]*100/1024, (bw[1]*10000/1024)%100, ++ bw[2]*100/1024, (bw[2]*10000/1024)%100, bw[3]*100/1024, (bw[3]*10000/1024)%100); ++ } ++ } ++ else { ++ if (effi_last != effi) { ++ str += scnprintf(str, end - str, "%3d:%s\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\n", ++ i, miu_clients[i].name, effi*100/1024, (effi*10000/1024)%100, ++ bw[0]*100/1024, (bw[0]*10000/1024)%100, bw[1]*100/1024, (bw[1]*10000/1024)%100, ++ bw[2]*100/1024, (bw[2]*10000/1024)%100, bw[3]*100/1024, (bw[3]*10000/1024)%100); ++ } ++ else { ++ str += scnprintf(str, end - str, "%3d:%s\t"ASCII_COLOR_RED"%2d.%02d%%"ASCII_COLOR_END"\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\t%2d.%02d%%\n", ++ i, miu_clients[i].name, effi*100/1024, (effi*10000/1024)%100, ++ bw[0]*100/1024, (bw[0]*10000/1024)%100, bw[1]*100/1024, (bw[1]*10000/1024)%100, ++ bw[2]*100/1024, (bw[2]*10000/1024)%100, bw[3]*100/1024, (bw[3]*10000/1024)%100); ++ } ++ } ++ if (effi != 0x3FF) { ++ effi_last = effi; ++ } ++ } ++ } ++ ++ if (str > buf) ++ str--; ++ str += scnprintf(str, end - str, "\n"); ++ return (str - buf); ++} ++ ++#ifdef CONFIG_CAM_CLK ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int dram_type = 0; ++ ++ if (m == 0) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ } ++#if MIU_NUM > 1 ++ else { ++ printk("NOT support multiple MIUs\n"); ++ return 0; ++ } ++#endif ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", CamClkRateGet(CAMCLK_ddrpll_clk) / 1000000); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", CamClkRateGet(CAMCLK_miupll_clk) / 1000000); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ str += scnprintf(str, end - str, "SSC: %s\n", (INREGMSK16(iAtopBankAddr + REG_ID_14, 0x8000)==0x8000)? "OFF" : "ON"); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++#else ++static ssize_t dram_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned char m = MIU_IDX(dev->kobj.name[3]); ++ unsigned int iMiuBankAddr = 0; ++ unsigned int iAtopBankAddr = 0; ++ unsigned int iMiupllBankAddr = 0; ++ unsigned int dram_type = 0; ++ unsigned int ddfset = 0; ++ unsigned int dram_freq = 0; ++ unsigned int miupll_freq = 0; ++ ++ if (m == 0) { ++ iMiuBankAddr = BASE_REG_MIU_PA; ++ iAtopBankAddr = BASE_REG_ATOP_PA; ++ iMiupllBankAddr = BASE_REG_MIUPLL_PA; ++ } ++#if MIU_NUM > 1 ++ else { ++ printk("NOT support multiple MIUs\n"); ++ return 0; ++ } ++#endif ++ ++ dram_type = INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0003); ++ ddfset = (INREGMSK16(iAtopBankAddr + REG_ID_19, 0x00FF) << 16) + INREGMSK16(iAtopBankAddr + REG_ID_18, 0xFFFF); ++ dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ miupll_freq = 24 * INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x00FF) / ((INREGMSK16(iMiupllBankAddr + REG_ID_03, 0x0700) >> 8) + 2); ++ ++ str += scnprintf(str, end - str, "DRAM Type: %s\n", (dram_type==3)? "DDR3" : (dram_type==2)? "DDR2" : "Unknown"); ++ str += scnprintf(str, end - str, "DRAM Size: %dMB\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_69, 0xF000) >> 12)); ++ str += scnprintf(str, end - str, "DRAM Freq: %dMHz\n", dram_freq); ++ str += scnprintf(str, end - str, "MIUPLL Freq: %dMHz\n", miupll_freq); ++ str += scnprintf(str, end - str, "Data Rate: %dx Mode\n", 1 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x0300) >> 8)); ++ str += scnprintf(str, end - str, "Bus Width: %dbit\n", 16 << (INREGMSK16(iMiuBankAddr + REG_ID_01, 0x000C) >> 2)); ++ str += scnprintf(str, end - str, "SSC: %s\n", (INREGMSK16(iAtopBankAddr + REG_ID_14, 0x8000)==0x8000)? "OFF" : "ON"); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++#endif ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++DEVICE_ATTR(measure_all, 0644, measure_all_show, measure_all_store); ++DEVICE_ATTR(dram_info, 0444, dram_info_show, NULL); ++ ++#ifdef CONFIG_PM_SLEEP ++int miu_subsys_suspend(struct device *dev) ++{ ++ if (dev == &miu[0].dev) { ++ // keep dram size setting ++ miu[0].reg_dram_size = INREGMSK16(BASE_REG_MIU_PA + REG_ID_69, 0xF000); ++ } ++ ++ pr_debug("miu subsys suspend %s\n", dev->kobj.name); ++ return 0; ++} ++ ++int miu_subsys_resume(struct device *dev) ++{ ++ if (dev == &miu[0].dev) { ++ // restore dram size setting ++ OUTREGMSK16(BASE_REG_MIU_PA + REG_ID_69, miu[0].reg_dram_size, 0xF000); ++ } ++ else if (strncmp(dev->kobj.name, "miu_arb", 7) == 0) { ++ miu_arb_resume(); ++ } ++ ++ pr_debug("miu subsys resume %s\n", dev->kobj.name); ++ return 0; ++} ++#endif ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret = 0, i; ++ ++ //initialize MIU client table ++ memset(miu_clients_bw, 0, MIU_NUM*MIU_CLIENT_NUM); ++ //OVERALL client monitor enable ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ miu_clients_bw[i][0].enabled = 1; ++ miu_devname[i][0] = 'm'; miu_devname[i][1] = 'i'; miu_devname[i][2] = 'u'; miu_devname[i][3] = '0' + i; ++ } ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ for(i = 0; i < MIU_NUM; i++) ++ { ++ miu[i].index = 0; ++ miu[i].dev.kobj.name = (const char *)miu_devname[i]; ++ miu[i].dev.bus = &miu_subsys; ++ ++ ret = device_register(&miu[i].dev); ++ if (ret) { ++ printk(KERN_ERR "Failed to register %s device!! %d\n",miu[i].dev.kobj.name,ret); ++ return; ++ } ++ ++ device_create_file(&miu[i].dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_client_disable); ++ device_create_file(&miu[i].dev, &dev_attr_monitor_set_duration_ms); ++ device_create_file(&miu[i].dev, &dev_attr_measure_all); ++ device_create_file(&miu[i].dev, &dev_attr_dram_info); ++ } ++#if CONFIG_SS_MIU_ARBITRATION ++ create_miu_arb_node(&miu_subsys); ++#endif ++} +diff --git a/arch/arm/mach-sstar/infinity6e/miu_bw.h b/arch/arm/mach-sstar/infinity6e/miu_bw.h +new file mode 100755 +index 000000000000..49a60cf090ee +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/miu_bw.h +@@ -0,0 +1,96 @@ ++/* ++* miu_bw.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Alterman.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++#ifndef MIU_NUM ++#define MIU_NUM (1) ++#endif ++ ++#define OVERALL_CLIENT_ID (0x00) ++#define CPU_CLIENT_ID (0x70) ++#define DLA_HIWAY_ID (0x71) ++#define MIU_GRP_CLIENT_NUM (0x10) ++#define MIU_GRP_NUM (3) ++#define MIU_CLIENT_NUM (0x32) // CPU + DLA highway + (16 clients per group, total 3 groups) ++#define MIU_ARB_CLIENT_NUM (0x30) // 16 clients per group, total 3 groups ++ ++#define MIU_IDX(c) (((c - '0') > MIU_NUM) ? 0 : c - '0') ++ ++/* Bandwidth measurement related */ ++ ++/* Bandwidth adjustment related */ ++// policy ++#define MIU_ARB_POLICY_DEF 0 ++#define MIU_ARB_POLICY_BGA2_DEF 1 ++#define MIU_ARB_POLICY_NUM 2 ++// dump ++#define MIU_ARB_DUMP_TEXT 0 ++#define MIU_ARB_DUMP_REG 1 ++#define MIU_ARB_DUMP_MAX 2 ++// group priority ++#define MIU_ARB_OG_PRIO_0 0 ++#define MIU_ARB_OG_PRIO_1 1 ++#define MIU_ARB_OG_PRIO_2 2 ++#define MIU_ARB_OG_PRIO_3 3 ++#define MIU_ARB_OG_PRIO_NUM 4 ++ ++/* Log color related */ ++#define ASCII_COLOR_RED "\033[1;31m" ++#define ASCII_COLOR_WHITE "\033[1;37m" ++#define ASCII_COLOR_YELLOW "\033[1;33m" ++#define ASCII_COLOR_BLUE "\033[1;36m" ++#define ASCII_COLOR_GREEN "\033[1;32m" ++#define ASCII_COLOR_END "\033[0m" ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++ int reg_dram_size; // register setting for dram size ++}; ++ ++// common for all MIU ++struct miu_client { ++ const char *name; ++ const short id; ++ const short rsvd; ++}; ++ ++// dedicated for each MIU ++struct miu_client_bw { ++ short enabled; ++}; ++ ++/*=============================================================*/ ++// Export Functions ++/*=============================================================*/ ++ ++extern const char* miu_client_id_to_name(U16 id); ++extern short miu_client_reserved(U16 id); ++extern void create_miu_arb_node(struct bus_type *miu_subsys); ++#ifdef CONFIG_PM_SLEEP ++extern void miu_arb_resume(void); ++#endif ++ +diff --git a/arch/arm/mach-sstar/infinity6e/pm.c b/arch/arm/mach-sstar/infinity6e/pm.c +new file mode 100755 +index 000000000000..56e63f98f2ac +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/pm.c +@@ -0,0 +1,117 @@ ++/* ++* pm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include ++#include ++ ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++#define SUSPEND_WAKEUP 0 ++#define SUSPEND_SLEEP 1 ++#define STR_PASSWORD 0x5A5A55AA ++ ++typedef struct { ++ char magic[8]; ++ unsigned int resume_entry; ++ unsigned int count; ++ unsigned int status; ++ unsigned int password; ++} suspend_keep_info; ++ ++extern void sram_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++static suspend_keep_info *pStr_info; ++int suspend_status = SUSPEND_WAKEUP; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&sram_suspend_imi, 0x1000); ++ suspend_status = SUSPEND_SLEEP; ++ ++ //resume info ++ if (pStr_info) { ++ pStr_info->count++; ++ pStr_info->status = SUSPEND_SLEEP; ++ pStr_info->password = STR_PASSWORD; ++ } ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush L3 cache ++ Chip_Flush_MIU_Pipe(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ //FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ #ifdef CONFIG_SMP ++ secure_cntvoff_init(); ++ #endif ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static void mstar_suspend_wake(void) ++{ ++ if (pStr_info) { ++ pStr_info->status = SUSPEND_WAKEUP; ++ pStr_info->password = 0; ++ } ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .wake = mstar_suspend_wake, ++ .valid = suspend_valid_only_mem, ++}; ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ pStr_info = (suspend_keep_info *)__va(0x20000000); ++ memset(pStr_info, 0, sizeof(suspend_keep_info)); ++ strcpy(pStr_info->magic, "SIG_STR"); ++ pStr_info->resume_entry = resume_pbase; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ return 0; ++} +diff --git a/arch/arm/mach-sstar/infinity6e/smp_head.S b/arch/arm/mach-sstar/infinity6e/smp_head.S +new file mode 100755 +index 000000000000..da01dc5f6060 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/smp_head.S +@@ -0,0 +1,66 @@ ++/* ++* smp_head.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++ ++/* __CPUINIT */ ++ ++#define ACTLR_SMP_ENABLE 0x0040 ++#define ACTLR_DODMBS_DISABLE 0x0400 ++#define ACTLR_L2RADIS_DISABLE 0x0800 ++#define ACTLR_L1RADIS_DISABLE 0x1000 ++#define ACTLR_L1PCTL_3_PREFETCH 0x6000 ++#define ACTLR_DDVM_DISABLE 0x8000 ++ ++#define NSACR_CP11 0x0800 ++#define NSACR_CP10 0x0400 ++ ++#define CPACR_CP11_FULL 0x00C00000 ++#define CPACR_CP10_FULL 0x00300000 ++ ++.extern infinity6e_secondary_gic ++ ++/* ++ * Realview/Versatile Express specific entry point for secondary CPUs. ++ * This provides a "holding pen" into which all secondary cores are held ++ * until we're ready for them to initialise. ++ */ ++ENTRY(infinity6e_secondary_startup) ++ /* Native ARMv7 L1 invalide function */ ++ bl v7_invalidate_l1 ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ /* ++ * we've been released from the holding pen: secondary_stack ++ * should now contain the SVC stack for this core ++ */ ++ b secondary_startup ++ ++ ++ .align 2 ++1: .long . ++ .long pen_release ++ENDPROC(infinity6e_secondary_startup) +diff --git a/arch/arm/mach-sstar/infinity6e/smp_platform.c b/arch/arm/mach-sstar/infinity6e/smp_platform.c +new file mode 100755 +index 000000000000..968f295fd451 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/smp_platform.c +@@ -0,0 +1,431 @@ ++/* ++* smp_platform.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: XXXX ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * cedric_smp.c ++ * ++ * Created on: 2015�~4��30�� ++ * Author: Administrator ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++ ++extern int infinity6e_platform_cpu_kill(unsigned int cpu); ++extern void infinity6e_platform_cpu_die(unsigned int cpu); ++extern int infinity6e_platform_cpu_disable(unsigned int cpu); ++ ++extern void infinity6e_secondary_startup(void); ++void infinity6e_smp_init_cpus(void); ++void infinity6e_smp_prepare_cpus(unsigned int max_cpus); ++//extern volatile int __cpuinitdata pen_release; ++extern volatile int pen_release; ++extern void Chip_Flush_CacheAll(void); ++ ++#ifdef CONFIG_PM_SLEEP ++extern int suspend_status; ++#endif ++//#define SCU_PHYS 0x16000000 /*Cedric*/ ++#define SCU_PHYS 0x16000000 /*MACAN*/ // SCU PA = 0x16004000 ++ ++#if 0 ++#define ARM_MPIDR_READ() \ ++ ({ \ ++ int val; \ ++ asm volatile("mrc p15, 0, r0, c0, c0, 5\n"); \ ++ asm volatile("str r0, %[reg]\n" : [reg]"=m"(val)); \ ++ val; \ ++ }) ++#endif ++ ++static inline void cpu_enter_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk(KERN_INFO "ms_hotplug.c cpu_enter_lowpower: in\n"); ++ ++ flush_cache_all(); ++ asm volatile( ++ " mcr p15, 0, %1, c7, c5, 0\n" ++ " mcr p15, 0, %1, c7, c10, 4\n" ++ /* ++ * Turn off coherency ++ */ ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " bic %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ " mrc p15, 0, %0, c1, c0, 0\n" ++ " bic %0, %0, %2\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ : "=&r" (v) ++ : "r" (0), "Ir" (CR_C) ++ : "cc"); ++ ++ printk(KERN_INFO "ms_hotplug.c cpu_enter_lowpower: out\n"); ++} ++ ++static inline void cpu_leave_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk(KERN_INFO "ms_hotplug.c cpu_leave_lowpower: in\n"); ++ ++ asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" ++ " orr %0, %0, %1\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " orr %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ : "=&r" (v) ++ : "Ir" (CR_C) ++ : "cc"); ++ ++ printk(KERN_INFO "ms_hotplug.c cpu_leave_lowpower: out\n"); ++} ++ ++static inline void platform_do_lowpower(unsigned int cpu, int *spurious) ++{ ++ //printk("ms_hotplug.c platform_do_lowpower: before %d cpu go into WFI, spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * there is no power-control hardware on this platform, so all ++ * we can do is put the core into WFI; this is safe as the calling ++ * code will have already disabled interrupts ++ */ ++ for (;;) { ++ /* ++ * here's the WFI ++ */ ++ asm("wfi\n" ++ : ++ : ++ : "memory", "cc"); ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up, spurious =%d \n", cpu, *spurious); ++ ++ if (pen_release == cpu_logical_map(cpu)) { ++ /* ++ * OK, proper wakeup, we're done ++ */ ++ break; ++ } ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up error(cpuID != pen_release), spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * Getting here, means that we have come out of WFI without ++ * having been woken up - this shouldn't happen ++ * ++ * Just note it happening - when we're woken, we can report ++ * its occurrence. ++ */ ++ (*spurious)++; ++ } ++} ++ ++int infinity6e_platform_cpu_kill(unsigned int cpu) ++{ ++ return 1; ++} ++ ++/* ++ * platform-specific code to shutdown a CPU ++ * ++ * Called with IRQs disabled ++ */ ++void __ref infinity6e_platform_cpu_die(unsigned int cpu) ++{ ++ int spurious = 0; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ ++ //printk("ms_hotplug.c platform_cpu_die: in cpu = %d \n", cpu); ++ ++ Chip_Flush_CacheAll(); ++ ++ /* ++ * we're ready for shutdown now, so do it ++ */ ++ //cpu_enter_lowpower(); ++ platform_do_lowpower(cpu, &spurious); ++ ++ /* ++ * bring this CPU back into the world of cache ++ * coherency, and then restore interrupts ++ */ ++ //cpu_leave_lowpower(); ++ ++ printk(KERN_INFO "ms_hotplug.c platform_cpu_die: out cpu = %d \n", cpu); ++ ++ if (spurious) ++ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); ++} ++ ++int infinity6e_platform_cpu_disable(unsigned int cpu) ++{ ++ /* ++ * we don't allow CPU 0 to be shutdown (it is still too special ++ * e.g. clock tick interrupts) ++ */ ++ ++ printk(KERN_INFO "ms_hotplug.c platform_cpu_disable: in cpu = %d \n", cpu); ++ return cpu == 0 ? -EPERM : 0; ++} ++ ++ ++/* ++ * control for which core is the next to come out of the secondary ++ * boot "holding pen" ++ */ ++//volatile int __cpuinitdata pen_release = -1; ++ ++static void __iomem *scu_base_addr(void) ++{ ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ return (void __iomem *)(IO_ADDRESS(SCU_PHYS)); ++} ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++//static void __cpuinit write_pen_release(int val) ++static void write_pen_release(int val) ++{ ++ pen_release = val; ++ smp_wmb(); ++ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); ++ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); ++} ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++void infinity6e_secondary_init(unsigned int cpu) ++{ ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ ++ /* ++ * if any interrupts are already enabled for the primary ++ * core (e.g. timer irq), then they will not have been enabled ++ * for us: do so ++ */ ++ //gic_secondary_init(0); ++ ++ /* ++ * let the primary processor know we're out of the ++ * pen, then head off into the C entry point ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++#define SECOND_START_ADDR_HI 0x1F20404C ++#define SECOND_START_ADDR_LO 0x1F204050 ++#define SECOND_MAGIC_NUMBER_ADDR 0x1F204058 ++ ++int infinity6e_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ unsigned long timeout; ++ printk(KERN_INFO "[%s]\n",__FUNCTION__); ++ /* ++ * Set synchronisation state between this boot processor ++ * and the secondary one ++ */ ++ spin_lock(&boot_lock); ++ ++ /* ++ * This is really belt and braces; we hold unintended secondary ++ * CPUs in the holding pen until we're ready for them. However, ++ * since we haven't sent them a soft interrupt, they shouldn't ++ * be there. ++ */ ++ write_pen_release(cpu_logical_map(cpu)); ++ ++ do{ ++ OUTREG16(SECOND_MAGIC_NUMBER_ADDR, 0xBABE); ++ }while(INREG16(SECOND_MAGIC_NUMBER_ADDR)!=0xBABE); ++ ++#ifdef CONFIG_PM_SLEEP ++ if (suspend_status) { ++ infinity6e_smp_init_cpus(); ++ infinity6e_smp_prepare_cpus(2); ++ } ++#endif ++ /* ++ * Send the secondary CPU a soft interrupt, thereby causing ++ * the boot monitor to read the system wide flags register, ++ * and branch to the address found there. ++ */ ++ printk(KERN_DEBUG "[%s] ipi\n",__FUNCTION__); ++ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ /* ++ * now the secondary core is starting up let it run its ++ * calibrations, then wait for it to finish ++ */ ++ spin_unlock(&boot_lock); ++ ++#ifdef CONFIG_PM_SLEEP ++ if (suspend_status) { ++ suspend_status = 0; ++ } ++#endif ++ ++ return pen_release != -1 ? -ENOSYS : 0; ++} ++ ++ ++#include ++#include ++ ++ ++#define SCU_CTRL 0x00 ++ ++void infinity6e_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ int i; ++// u32 scu_ctrl; ++// printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ /* ++ * Initialise the present map, which describes the set of CPUs ++ * actually populated at the present time. ++ */ ++ for (i = 0; i < max_cpus; i++) ++ { ++ set_cpu_present(i, true); ++ } ++ ++#if defined(CONFIG_CEDRIC_MASTER0_ONLY_PATCH) ++ __raw_writel(0xe0000000, scu_base_addr() + 0x40); ++ __raw_writel(0xe0100000, scu_base_addr() + 0x44); ++ scu_ctrl = __raw_readl(scu_base_addr() + SCU_CTRL); ++ scu_ctrl |= 0x02; ++ __raw_writel(scu_ctrl, scu_base_addr() + SCU_CTRL); ++ printk(KERN_WARNING"SCU: Filter to Master0 only\n"); ++#endif ++ ++ scu_enable(scu_base_addr()); // SCU PA = 0x16000000 ++ ++// printk("[306]!! scu_enable\n"); ++ ++ /* ++ * Write the address of secondary startup into the ++ * system-wide flags register. The boot monitor waits ++ * until it receives a soft interrupt, and then the ++ * secondary CPU branches to this address. ++ */ ++ do{ ++ OUTREG16(SECOND_START_ADDR_LO,(virt_to_phys(infinity6e_secondary_startup) & 0xFFFF)); ++ }while(INREG16(SECOND_START_ADDR_LO)!=(virt_to_phys(infinity6e_secondary_startup) & 0xFFFF)); ++ ++ do{ ++ OUTREG16(SECOND_START_ADDR_HI,(virt_to_phys(infinity6e_secondary_startup)>>16)); ++ }while(INREG16(SECOND_START_ADDR_HI)!=(virt_to_phys(infinity6e_secondary_startup)>>16)); ++ ++ __cpuc_flush_kern_all(); ++} ++ ++void infinity6e_smp_init_cpus(void) ++{ ++ ++ void __iomem *scu_base =scu_base_addr(); ++ unsigned int i, ncores; ++ printk(KERN_INFO "[%s]\n",__FUNCTION__); ++ ncores = scu_base ? scu_get_core_count(scu_base) : 1; ++ ++ for (i = 0; i < 2; i++) ++ { ++ set_cpu_possible(i, true); ++ } ++} ++ ++#ifdef CONFIG_LH_RTOS ++#define GICD_IGROUPR 0x080 ++ ++#define GICC_CTLR 0x00 ++#define GICC_PMR 0x04 ++#define GICC_BPR 0x08 ++ ++#define GICD_BASE 0x16001000 ++#define GICC_BASE 0x16002000 ++ ++#define GICD_WRITEL(a,v) (*(volatile unsigned int *)(u32)(GICD_BASE + a) = (v)) ++#define GICC_WRITEL(a,v) (*(volatile unsigned int *)(u32)(GICC_BASE + a) = (v)) ++ ++void infinity6e_secondary_gic(void) ++{ ++ /* Diable GICC */ ++ GICC_WRITEL(GICC_CTLR,0x00000000); ++ ++ /* set interrupt priority mask level = 15, if the interrupt priority is larger than this value, it will be sent to CPU*/ ++ GICC_WRITEL(GICC_PMR , 0xf0); ++ ++ /* enable group priority */ ++ GICC_WRITEL(GICC_BPR , 3); ++ ++ /* LH: Set all interrupts are Grp 1 for IRQ */ ++ GICD_WRITEL(GICD_IGROUPR , ~0x0); ++ ++ /* LH: run in Secure Mode to Enable Grp1, Ackctl and FIQEn */ ++ GICC_WRITEL(GICC_CTLR,0x000001EA); //non-shared ++} ++#endif ++ ++struct smp_operations __initdata infinity6e_smp_ops = { ++ .smp_init_cpus = infinity6e_smp_init_cpus, ++ .smp_prepare_cpus = infinity6e_smp_prepare_cpus, ++ .smp_secondary_init = infinity6e_secondary_init, ++ .smp_boot_secondary = infinity6e_boot_secondary, ++ ++#ifdef CONFIG_HOTPLUG_CPU ++ .cpu_kill = infinity6e_platform_cpu_kill, ++ .cpu_die = infinity6e_platform_cpu_die, ++ .cpu_disable = infinity6e_platform_cpu_disable, ++#endif ++}; +diff --git a/arch/arm/mach-sstar/infinity6e/soc.c b/arch/arm/mach-sstar/infinity6e/soc.c +new file mode 100755 +index 000000000000..8bbee25b82d7 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/soc.c +@@ -0,0 +1,660 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#ifdef CONFIG_PM_SLEEP ++#include ++#endif ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "ms_msys.h" ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ {IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "sstar,infinity6e", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++ ++ ++//extern struct timecounter *arch_timer_get_timecounter(void); ++ ++ ++static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Sstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ unsigned long dwLockFlag = 0; ++ unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static void mstar_chip_flush_STB_and_miu_pipe(void) ++{ ++ dsb(); ++ mstar_chip_flush_miu_pipe(); ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NONE 0x00 ++#define STORAGE_SPI_NAND_SKIP_SD BIT2 ++#define STORAGE_SPI_NAND BIT4 ++#define STORAGE_SPI_NOR BIT5 ++#define STORAGE_SPI_NOR_SKIP_SD BIT1 ++#define STORAGE_USB BIT12 ++#define STORAGE_EMMC_8 (BIT7|BIT3) ++#define STORAGE_EMMC_4 BIT3 ++#define STORAGE_BOOT_TYPES (BIT12|BIT7|BIT5|BIT4|BIT3|BIT2|BIT1) ++ ++ u16 boot_type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & STORAGE_BOOT_TYPES); ++ ++ if(boot_type == STORAGE_SPI_NAND || boot_type == STORAGE_SPI_NAND_SKIP_SD) ++ { ++ return (int)MS_STORAGE_SPINAND_ECC; ++ } ++ else if(boot_type == STORAGE_EMMC_8 || boot_type == STORAGE_EMMC_4) ++ { ++ return (int)MS_STORAGE_EMMC; ++ } ++ else if(boot_type == STORAGE_SPI_NOR || boot_type == STORAGE_SPI_NOR_SKIP_SD) ++ { ++ return (int)MS_STORAGE_NOR; ++ } ++ else ++ { ++ return (int)MS_STORAGE_UNKNOWN; ++ } ++} ++ ++static int mstar_get_package_type(void) ++{ ++ if(!strncmp(&mstar_soc_dev_attr.machine[11], "SSC012B-S01A", 12)) ++ return MS_I6E_PACKAGE_QFN_DDR3; ++ else if(!strncmp(&mstar_soc_dev_attr.machine[11], "SSC013A-S01A", 12)) ++ return MS_I6E_PACKAGE_BGA_LPDDR2; ++ else if(!strncmp(&mstar_soc_dev_attr.machine[11], "SSC015A-S01A", 12)) ++ return MS_I6E_PACKAGE_BGA2_DDR3; ++ else if(!strncmp(&mstar_soc_dev_attr.machine[11], "FPGA", 4)) ++ return MS_I6E_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I6E_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]="I6E"; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ u64 cycles=arch_timer_read_counter(); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ us_ticks_cycle_offset=arch_timer_read_counter(); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++ default: ++ printk(KERN_ERR "Unsupport CHIP_FUNCTION!! ID=%d\n",function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_STB_and_miu_pipe;//dsb ++ chip->chip_flush_miu_pipe_nodsb=mstar_chip_flush_miu_pipe;//nodsbchip->phys_to_miu=mstar_phys_to_MIU; ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++struct mcm_client{ ++ char* name; ++ short index; ++ unsigned int reg; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, OFFSET_MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, OFFSET_MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, OFFSET_MCM_ID_BDMA, 0}, ++ {"MFE", MCM_ID_MFE, OFFSET_MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, OFFSET_MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, OFFSET_MCM_ID_BACH, 0}, ++ {"FILE", MCM_ID_FILE, OFFSET_MCM_ID_FILE, 0}, ++ {"UHC0", MCM_ID_UHC0, OFFSET_MCM_ID_UHC0, 0}, ++ {"EMAC", MCM_ID_EMAC, OFFSET_MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, OFFSET_MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, OFFSET_MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, OFFSET_MCM_ID_ISP_DMA, 0}, ++ {"GOP0", MCM_ID_GOP0, OFFSET_MCM_ID_GOP0, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, OFFSET_MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, OFFSET_MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, OFFSET_MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, OFFSET_MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, OFFSET_MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, OFFSET_MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, OFFSET_MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, OFFSET_MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, OFFSET_MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, OFFSET_MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, OFFSET_MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, OFFSET_MCM_ID_SC2_SNPI, 0}, ++ {"CMDQ1", MCM_ID_CMDQ1, OFFSET_MCM_ID_CMDQ1, 0}, ++ {"CMDQ2", MCM_ID_CMDQ2, OFFSET_MCM_ID_CMDQ2, 0}, ++ {"GOP1", MCM_ID_GOP1, OFFSET_MCM_ID_GOP1, 0}, ++ {"GOP2", MCM_ID_GOP2, OFFSET_MCM_ID_GOP2, 0}, ++ {"UHC1", MCM_ID_UHC1, OFFSET_MCM_ID_UHC1, 0}, ++ {"IVE", MCM_ID_IVE, OFFSET_MCM_ID_IVE, 0}, ++ {"VHE", MCM_ID_VHE, OFFSET_MCM_ID_VHE, 0}, ++ {"*ALL_CLIENTS",MCM_ID_ALL, 0, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ ++ return 0; ++ } ++ ++ if((index >= MCM_ID_START) &&(index < MCM_ID_END)) ++ { ++ addr = mcm_clients[index].reg; ++ } ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++ ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++ mstar_create_MCM_node(); ++} ++ ++static void global_reset(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ msys_set_rebootType(MSYS_REBOOT_BY_SW_RST); ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static void __init mstar_pm_reserve(void) ++{ ++ // reserve one page in the beginning of dram ++ memblock_reserve(MIU0_BASE, PAGE_SIZE); ++} ++#endif ++ ++#ifdef CONFIG_SMP ++extern struct smp_operations infinity6e_smp_ops; ++#endif ++ ++DT_MACHINE_START(MS_DT, "SStar Soc (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = global_reset, ++#ifdef CONFIG_PM_SLEEP ++ .reserve = mstar_pm_reserve, ++#endif ++#ifdef CONFIG_SMP ++ .smp = smp_ops(infinity6e_smp_ops), ++#endif ++MACHINE_END +diff --git a/arch/arm/mach-sstar/infinity6e/sram.S b/arch/arm/mach-sstar/infinity6e/sram.S +new file mode 100755 +index 000000000000..3ad15bef7347 +--- /dev/null ++++ b/arch/arm/mach-sstar/infinity6e/sram.S +@@ -0,0 +1,341 @@ ++/* ++* sram.S- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++#define ARCH_us(x) (6*x) ++ .align 3 ++.globl sram_suspend_imi ++.globl v7_cpu_resume ++ ++/* A macro about using arch timer to delay ++ inputs : ++ t : us to delay ++ l : For different branch naming ++*/ ++.macro arch_usdelay t, l ++ ldr r8, =ARCH_us(\t) /*delay tms*/ ++ mrrc p15, 1, r9, r10, c14 ++ add r9, r9, r8 /*Target tick*/ ++delay_retry\l: ++ isb sy ++ mrrc p15, 1, r11, r12, c14 ++ cmp r11, r9 ++ blt delay_retry\l /* jump to delay_retry in case r0 is bigger (N==1) */ ++.endm ++ ++ENTRY(sram_suspend_imi) ++ ++ // 04. LPDDR2 enter self-refresh ++ //wriu -w 0x1012e0,0x0000 ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x1011E6,0x00FE ++ //wait 20 ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0000 ++ str r0, [r2, #0xE0 << 1] ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x00FE ++ str r0, [r2, #0xE6 << 1] ++ //delay ++ arch_usdelay 1000,__LINE__ ++ ++ //Pre-charge all then one refresh ++ //wriu -w 0x101218 0x0400 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ //wriu -b 0x101200 0x30 0x20 ++ ldrb r0, [r2, #0x00] ++ and r0, r0, #0xCF ++ orr r0, r0, #0x20 ++ strb r0, [r2, #0x00] ++ //wriu -b 0x101201 0x1e 0x04 ++ ldrb r0, [r2, #0x01] ++ and r0, r0, #0xE1 ++ orr r0, r0, #0x04 ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x01 0x00 ++ ldrb r0, [r2, #0x01] ++ and r0, r0, #0xFE ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x01 0x01 ++ ldrb r0, [r2, #0x01] ++ orr r0, r0, #0x01 ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x01 0x00 ++ ldrb r0, [r2, #0x01] ++ and r0, r0, #0xFE ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x1e 0x02 ++ ldrb r0, [r2, #0x01] ++ and r0, r0, #0xE1 ++ orr r0, r0, #0x02 ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x01 0x00 ++ ldrb r0, [r2, #0x01] ++ and r0, r0, #0xFE ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x01 0x01 ++ ldrb r0, [r2, #0x01] ++ orr r0, r0, #0x01 ++ strb r0, [r2, #0x01] ++ //wriu -b 0x101201 0x01 0x00 ++ ldrb r0, [r2, #0x01] ++ and r0, r0, #0xFE ++ strb r0, [r2, #0x01] ++ //delay, DO NOT REMOVE THIS DELAY!!!! ++ arch_usdelay 1000,__LINE__ ++ ++ //wriu -w 0x101200 0x202e ++ ldr r0, =0x202e ++ str r0, [r2, #0x00 << 1] ++ //wait 10 ++ //delay ++ arch_usdelay 1000,__LINE__ ++ ++ // 05. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ //wriu -b 0x101000 0x08 0x08 ++ //wriu -b 0x101000 0x10 0x10 ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x08 ++ strb r0, [r2, #0x00 << 1] ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x10 ++ strb r0, [r2, #0x00 << 1] ++ //wriu -b 0x101054 0x70 0x70 ++ ldrb r0, [r2, #0xA8] ++ orr r0, r0, #0x70 ++ strb r0, [r2, #0xA8] ++ //wriu -b 0x101008 0x3F 0x00 ++ ldrb r0, [r2, #0x10] ++ and r0, r0, #0xC0 ++ strb r0, [r2, #0x10] ++ ++ // 06. power down ++ //wriu -w 0x00003408 0x01 ++ //wriu -w 0x00003400 0x20 ++ // Turn-on ISO flow ++ //wriu -w 0x00003406 0x01 ++ //wait 1 ++ //wriu -w 0x00003406 0x03 ++ //wait 1 ++ //wriu -w 0x00003406 0x07 ++ //wait 1 ++ //wriu -w 0x00003406 0x05 ++ //wait 1 ++ //wriu -w 0x00003406 0x01 ++ //wait 1 ++ //wriu -w 0x00003406 0x00 ++ //wait 1 ++ //wriu -w 0x00003400 0x00 ++ //wriu -w 0x0000341E 0x00 ++ // Turn-on ISO flow ++ //wriu -w 0x00003406 0x01 ++ //wait 1 ++ //wriu -w 0x00003406 0x03 ++ //wait 1 ++ //wriu -w 0x00003406 0x07 ++ //wait 1 ++ //wriu -w 0x00003406 0x05 ++ //wait 1 ++ //wriu -w 0x00003406 0x01 ++ //wait 1 ++ //wriu -w 0x00003406 0x00 ++ //wait 1 ++ //--------------------------------- ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x152400 ++ add r2, r1, r3, lsl #1 ++ ++ // timer1 DEF:x0000 (x480/32K=36 ms) ++ //ldr r0, =0x0480 ++ //str r0, [r2, #0x52 << 1] ++ ++ //[MUST] t2+t3+t4 > 55ms from scope measurment ++ // timer2 DEF:x0080 (x0080/32K=4 ms) ++ ldr r0, =0x0000 ++ str r0, [r2, #0x54 << 1] ++ ++ // timer3 DEF:x0010 (x8000/32K=1024 ms) ++ ldr r0, =0x0C80 // 100ms (64ms auto wakeup) ++ str r0, [r2, #0x56 << 1] ++ ++ // timer4 DEF:x0080 (x0080/32K=4 ms) ++ //ldr r0, =0xFFFF ++ //str r0, [r2, #0x58 << 1] ++ ++ // enter u3 mode ++ ldr r0, =0x0437 ++ str r0, [r2, #0x50 << 1] ++ ++ //---------------------------------- ++start: ++ ldr r1, =0xFD000000 ++ ldr r3, =0x003400 ++ add r2, r1, r3, lsl #1 ++ ++ // sel fro ++ //ldr r0, =0x0001 ++ //str r0, [r2, #0x50 << 1] ++ ++ // power down ++ ldr r0, =0x0000 ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x1E << 1] ++ ++rtc_iso: ++ // ISO b000 ++ ldr r0, =0x0000 ++ str r0, [r2, #0x06 << 1] ++ //delay 1ms ++ ldr r7, =0x0B ++1: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #0 ++ bne 1b ++ ++ // ISO b001 ++ ldr r0, =0x0001 ++ str r0, [r2, #0x06 << 1] ++ //delay ++ ldr r7, =0x0B ++2: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #8 ++ bne 2b ++ ++ // ISO b011 ++ ldr r0, =0x0003 ++ str r0, [r2, #0x06 << 1] ++ //delay ++ ldr r7, =0x0B ++3: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #0 ++ bne 3b ++ ++ // ISO b111 ++ ldr r0, =0x0007 ++ str r0, [r2, #0x06 << 1] ++ //delay ++ ldr r7, =0x0B ++4: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #8 ++ bne 4b ++ ++ // ISO b101 ++ ldr r0, =0x0005 ++ str r0, [r2, #0x06 << 1] ++ //delay ++ ldr r7, =0x0B ++5: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #0 ++ bne 5b ++ ++ // ISO b001 ++ ldr r0, =0x0001 ++ str r0, [r2, #0x06 << 1] ++ //delay ++ ldr r7, =0x0B ++6: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #8 ++ bne 6b ++ ++ // ISO b000 ++ ldr r0, =0x0000 ++ str r0, [r2, #0x06 << 1] ++ //delay ++ ldr r7, =0x1B ++7: ++ subs r7, r7, #1 ++ beq rtc_iso ++ arch_usdelay 100,__LINE__ ++ ++ ldr r0, [r2, #0x10 << 1] ++ and r0, r0, #0x08 ++ cmp r0, #0 ++ bne 7b ++ ++ nop ++ nop ++ nop ++ nop ++ ++ ++ENDPROC(sram_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-sstar/libfdt.h b/arch/arm/mach-sstar/libfdt.h +new file mode 100755 +index 000000000000..ea3e6df9f8ea +--- /dev/null ++++ b/arch/arm/mach-sstar/libfdt.h +@@ -0,0 +1,1495 @@ ++/* ++* libfdt.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _LIBFDT_H ++#define _LIBFDT_H ++/* ++ * libfdt - Flat Device Tree manipulation ++ * Copyright (C) 2006 David Gibson, IBM Corporation. ++ * ++ * libfdt is dual licensed: you can use it either under the terms of ++ * the GPL, or the BSD license, at your option. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public ++ * License along with this library; if not, write to the Free ++ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, ++ * MA 02110-1301 USA ++ * ++ * Alternatively, ++ * ++ * b) Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * 2. Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND ++ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, ++ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "libfdt_env.h" ++#include "fdt.h" ++ ++#define FDT_FIRST_SUPPORTED_VERSION 0x10 ++#define FDT_LAST_SUPPORTED_VERSION 0x11 ++ ++/* Error codes: informative error codes */ ++#define FDT_ERR_NOTFOUND 1 ++ /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ ++#define FDT_ERR_EXISTS 2 ++ /* FDT_ERR_EXISTS: Attemped to create a node or property which ++ * already exists */ ++#define FDT_ERR_NOSPACE 3 ++ /* FDT_ERR_NOSPACE: Operation needed to expand the device ++ * tree, but its buffer did not have sufficient space to ++ * contain the expanded tree. Use fdt_open_into() to move the ++ * device tree to a buffer with more space. */ ++ ++/* Error codes: codes for bad parameters */ ++#define FDT_ERR_BADOFFSET 4 ++ /* FDT_ERR_BADOFFSET: Function was passed a structure block ++ * offset which is out-of-bounds, or which points to an ++ * unsuitable part of the structure for the operation. */ ++#define FDT_ERR_BADPATH 5 ++ /* FDT_ERR_BADPATH: Function was passed a badly formatted path ++ * (e.g. missing a leading / for a function which requires an ++ * absolute path) */ ++#define FDT_ERR_BADPHANDLE 6 ++ /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle ++ * value. phandle values of 0 and -1 are not permitted. */ ++#define FDT_ERR_BADSTATE 7 ++ /* FDT_ERR_BADSTATE: Function was passed an incomplete device ++ * tree created by the sequential-write functions, which is ++ * not sufficiently complete for the requested operation. */ ++ ++/* Error codes: codes for bad device tree blobs */ ++#define FDT_ERR_TRUNCATED 8 ++ /* FDT_ERR_TRUNCATED: Structure block of the given device tree ++ * ends without an FDT_END tag. */ ++#define FDT_ERR_BADMAGIC 9 ++ /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a ++ * device tree at all - it is missing the flattened device ++ * tree magic number. */ ++#define FDT_ERR_BADVERSION 10 ++ /* FDT_ERR_BADVERSION: Given device tree has a version which ++ * can't be handled by the requested operation. For ++ * read-write functions, this may mean that fdt_open_into() is ++ * required to convert the tree to the expected version. */ ++#define FDT_ERR_BADSTRUCTURE 11 ++ /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt ++ * structure block or other serious error (e.g. misnested ++ * nodes, or subnodes preceding properties). */ ++#define FDT_ERR_BADLAYOUT 12 ++ /* FDT_ERR_BADLAYOUT: For read-write functions, the given ++ * device tree has it's sub-blocks in an order that the ++ * function can't handle (memory reserve map, then structure, ++ * then strings). Use fdt_open_into() to reorganize the tree ++ * into a form suitable for the read-write operations. */ ++ ++/* "Can't happen" error indicating a bug in libfdt */ ++#define FDT_ERR_INTERNAL 13 ++ /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. ++ * Should never be returned, if it is, it indicates a bug in ++ * libfdt itself. */ ++ ++#define FDT_ERR_MAX 13 ++ ++/**********************************************************************/ ++/* Low-level functions (you probably don't need these) */ ++/**********************************************************************/ ++ ++const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); ++static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) ++{ ++ return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); ++} ++ ++uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); ++ ++/**********************************************************************/ ++/* Traversal functions */ ++/**********************************************************************/ ++ ++int fdt_next_node(const void *fdt, int offset, int *depth); ++ ++/**********************************************************************/ ++/* General functions */ ++/**********************************************************************/ ++ ++#define fdt_get_header(fdt, field) \ ++ (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) ++#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) ++#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) ++#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) ++#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) ++#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) ++#define fdt_version(fdt) (fdt_get_header(fdt, version)) ++#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) ++#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) ++#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) ++#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) ++ ++#define __fdt_set_hdr(name) \ ++ static inline void fdt_set_##name(void *fdt, uint32_t val) \ ++ { \ ++ struct fdt_header *fdth = (struct fdt_header*)fdt; \ ++ fdth->name = cpu_to_fdt32(val); \ ++ } ++__fdt_set_hdr(magic); ++__fdt_set_hdr(totalsize); ++__fdt_set_hdr(off_dt_struct); ++__fdt_set_hdr(off_dt_strings); ++__fdt_set_hdr(off_mem_rsvmap); ++__fdt_set_hdr(version); ++__fdt_set_hdr(last_comp_version); ++__fdt_set_hdr(boot_cpuid_phys); ++__fdt_set_hdr(size_dt_strings); ++__fdt_set_hdr(size_dt_struct); ++#undef __fdt_set_hdr ++ ++/** ++ * fdt_check_header - sanity check a device tree or possible device tree ++ * @fdt: pointer to data which might be a flattened device tree ++ * ++ * fdt_check_header() checks that the given buffer contains what ++ * appears to be a flattened device tree with sane information in its ++ * header. ++ * ++ * returns: ++ * 0, if the buffer appears to contain a valid device tree ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings, as above ++ */ ++int fdt_check_header(const void *fdt); ++ ++/** ++ * fdt_move - move a device tree around in memory ++ * @fdt: pointer to the device tree to move ++ * @buf: pointer to memory where the device is to be moved ++ * @bufsize: size of the memory space at buf ++ * ++ * fdt_move() relocates, if possible, the device tree blob located at ++ * fdt to the buffer at buf of size bufsize. The buffer may overlap ++ * with the existing device tree blob at fdt. Therefore, ++ * fdt_move(fdt, fdt, fdt_totalsize(fdt)) ++ * should always succeed. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++int fdt_move(const void *fdt, void *buf, int bufsize); ++ ++/**********************************************************************/ ++/* Read-only functions */ ++/**********************************************************************/ ++ ++/** ++ * fdt_string - retrieve a string from the strings block of a device tree ++ * @fdt: pointer to the device tree blob ++ * @stroffset: offset of the string within the strings block (native endian) ++ * ++ * fdt_string() retrieves a pointer to a single string from the ++ * strings block of the device tree blob at fdt. ++ * ++ * returns: ++ * a pointer to the string, on success ++ * NULL, if stroffset is out of bounds ++ */ ++const char *fdt_string(const void *fdt, int stroffset); ++ ++/** ++ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries ++ * @fdt: pointer to the device tree blob ++ * ++ * Returns the number of entries in the device tree blob's memory ++ * reservation map. This does not include the terminating 0,0 entry ++ * or any other (0,0) entries reserved for expansion. ++ * ++ * returns: ++ * the number of entries ++ */ ++int fdt_num_mem_rsv(const void *fdt); ++ ++/** ++ * fdt_get_mem_rsv - retrieve one memory reserve map entry ++ * @fdt: pointer to the device tree blob ++ * @address, @size: pointers to 64-bit variables ++ * ++ * On success, *address and *size will contain the address and size of ++ * the n-th reserve map entry from the device tree blob, in ++ * native-endian format. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); ++ ++/** ++ * fdt_subnode_offset_namelen - find a subnode based on substring ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * @namelen: number of characters of name to consider ++ * ++ * Identical to fdt_subnode_offset(), but only examine the first ++ * namelen characters of name for matching the subnode name. This is ++ * useful for finding subnodes based on a portion of a larger string, ++ * such as a full path. ++ */ ++int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, ++ const char *name, int namelen); ++/** ++ * fdt_subnode_offset - find a subnode of a given node ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * ++ * fdt_subnode_offset() finds a subnode of the node at structure block ++ * offset parentoffset with the given name. name may include a unit ++ * address, in which case fdt_subnode_offset() will find the subnode ++ * with that unit address, or the unit address may be omitted, in ++ * which case fdt_subnode_offset() will find an arbitrary subnode ++ * whose name excluding unit address matches the given name. ++ * ++ * returns: ++ * structure block offset of the requested subnode (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the requested subnode does not exist ++ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); ++ ++/** ++ * fdt_path_offset - find a tree node by its full path ++ * @fdt: pointer to the device tree blob ++ * @path: full path of the node to locate ++ * ++ * fdt_path_offset() finds a node of a given path in the device tree. ++ * Each path component may omit the unit address portion, but the ++ * results of this are undefined if any such path component is ++ * ambiguous (that is if there are multiple nodes at the relevant ++ * level matching the given component, differentiated only by unit ++ * address). ++ * ++ * returns: ++ * structure block offset of the node with the requested path (>=0), on success ++ * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid ++ * -FDT_ERR_NOTFOUND, if the requested node does not exist ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_path_offset(const void *fdt, const char *path); ++ ++/** ++ * fdt_get_name - retrieve the name of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of the starting node ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_get_name() retrieves the name (including unit address) of the ++ * device tree node at structure block offset nodeoffset. If lenp is ++ * non-NULL, the length of this name is also returned, in the integer ++ * pointed to by lenp. ++ * ++ * returns: ++ * pointer to the node's name, on success ++ * If lenp is non-NULL, *lenp contains the length of that name (>=0) ++ * NULL, on error ++ * if lenp is non-NULL *lenp contains an error code (<0): ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); ++ ++/** ++ * fdt_first_property_offset - find the offset of a node's first property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of a node ++ * ++ * fdt_first_property_offset() finds the first property of the node at ++ * the given structure block offset. ++ * ++ * returns: ++ * structure block offset of the property (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the requested node has no properties ++ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_first_property_offset(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_next_property_offset - step through a node's properties ++ * @fdt: pointer to the device tree blob ++ * @offset: structure block offset of a property ++ * ++ * fdt_next_property_offset() finds the property immediately after the ++ * one at the given structure block offset. This will be a property ++ * of the same node as the given property. ++ * ++ * returns: ++ * structure block offset of the next property (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the given property is the last in its node ++ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_next_property_offset(const void *fdt, int offset); ++ ++/** ++ * fdt_get_property_by_offset - retrieve the property at a given offset ++ * @fdt: pointer to the device tree blob ++ * @offset: offset of the property to retrieve ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_get_property_by_offset() retrieves a pointer to the ++ * fdt_property structure within the device tree blob at the given ++ * offset. If lenp is non-NULL, the length of the property value is ++ * also returned, in the integer pointed to by lenp. ++ * ++ * returns: ++ * pointer to the structure representing the property ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const struct fdt_property *fdt_get_property_by_offset(const void *fdt, ++ int offset, ++ int *lenp); ++ ++/** ++ * fdt_get_property_namelen - find a property based on substring ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @namelen: number of characters of name to consider ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * Identical to fdt_get_property_namelen(), but only examine the first ++ * namelen characters of name for matching the property name. ++ */ ++const struct fdt_property *fdt_get_property_namelen(const void *fdt, ++ int nodeoffset, ++ const char *name, ++ int namelen, int *lenp); ++ ++/** ++ * fdt_get_property - find a given property in a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_get_property() retrieves a pointer to the fdt_property ++ * structure within the device tree blob corresponding to the property ++ * named 'name' of the node at offset nodeoffset. If lenp is ++ * non-NULL, the length of the property value is also returned, in the ++ * integer pointed to by lenp. ++ * ++ * returns: ++ * pointer to the structure representing the property ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_NOTFOUND, node does not have named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, ++ const char *name, int *lenp); ++static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, ++ const char *name, ++ int *lenp) ++{ ++ return (struct fdt_property *)(uintptr_t) ++ fdt_get_property(fdt, nodeoffset, name, lenp); ++} ++ ++/** ++ * fdt_getprop_by_offset - retrieve the value of a property at a given offset ++ * @fdt: pointer to the device tree blob ++ * @ffset: offset of the property to read ++ * @namep: pointer to a string variable (will be overwritten) or NULL ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_getprop_by_offset() retrieves a pointer to the value of the ++ * property at structure block offset 'offset' (this will be a pointer ++ * to within the device blob itself, not a copy of the value). If ++ * lenp is non-NULL, the length of the property value is also ++ * returned, in the integer pointed to by lenp. If namep is non-NULL, ++ * the property's namne will also be returned in the char * pointed to ++ * by namep (this will be a pointer to within the device tree's string ++ * block, not a new copy of the name). ++ * ++ * returns: ++ * pointer to the property's value ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * if namep is non-NULL *namep contiains a pointer to the property ++ * name. ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const void *fdt_getprop_by_offset(const void *fdt, int offset, ++ const char **namep, int *lenp); ++ ++/** ++ * fdt_getprop_namelen - get property value based on substring ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @namelen: number of characters of name to consider ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * Identical to fdt_getprop(), but only examine the first namelen ++ * characters of name for matching the property name. ++ */ ++const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, ++ const char *name, int namelen, int *lenp); ++ ++/** ++ * fdt_getprop - retrieve the value of a given property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_getprop() retrieves a pointer to the value of the property ++ * named 'name' of the node at offset nodeoffset (this will be a ++ * pointer to within the device blob itself, not a copy of the value). ++ * If lenp is non-NULL, the length of the property value is also ++ * returned, in the integer pointed to by lenp. ++ * ++ * returns: ++ * pointer to the property's value ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_NOTFOUND, node does not have named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const void *fdt_getprop(const void *fdt, int nodeoffset, ++ const char *name, int *lenp); ++static inline void *fdt_getprop_w(void *fdt, int nodeoffset, ++ const char *name, int *lenp) ++{ ++ return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); ++} ++ ++/** ++ * fdt_get_phandle - retrieve the phandle of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of the node ++ * ++ * fdt_get_phandle() retrieves the phandle of the device tree node at ++ * structure block offset nodeoffset. ++ * ++ * returns: ++ * the phandle of the node at nodeoffset, on success (!= 0, != -1) ++ * 0, if the node has no phandle, or another error occurs ++ */ ++uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_get_alias_namelen - get alias based on substring ++ * @fdt: pointer to the device tree blob ++ * @name: name of the alias th look up ++ * @namelen: number of characters of name to consider ++ * ++ * Identical to fdt_get_alias(), but only examine the first namelen ++ * characters of name for matching the alias name. ++ */ ++const char *fdt_get_alias_namelen(const void *fdt, ++ const char *name, int namelen); ++ ++/** ++ * fdt_get_alias - retreive the path referenced by a given alias ++ * @fdt: pointer to the device tree blob ++ * @name: name of the alias th look up ++ * ++ * fdt_get_alias() retrieves the value of a given alias. That is, the ++ * value of the property named 'name' in the node /aliases. ++ * ++ * returns: ++ * a pointer to the expansion of the alias named 'name', of it exists ++ * NULL, if the given alias or the /aliases node does not exist ++ */ ++const char *fdt_get_alias(const void *fdt, const char *name); ++ ++/** ++ * fdt_get_path - determine the full path of a node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose path to find ++ * @buf: character buffer to contain the returned path (will be overwritten) ++ * @buflen: size of the character buffer at buf ++ * ++ * fdt_get_path() computes the full path of the node at offset ++ * nodeoffset, and records that path in the buffer at buf. ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset. ++ * ++ * returns: ++ * 0, on success ++ * buf contains the absolute path of the node at ++ * nodeoffset, as a NUL-terminated string. ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) ++ * characters and will not fit in the given buffer. ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); ++ ++/** ++ * fdt_supernode_atdepth_offset - find a specific ancestor of a node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose parent to find ++ * @supernodedepth: depth of the ancestor to find ++ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_supernode_atdepth_offset() finds an ancestor of the given node ++ * at a specific depth from the root (where the root itself has depth ++ * 0, its immediate subnodes depth 1 and so forth). So ++ * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); ++ * will always return 0, the offset of the root node. If the node at ++ * nodeoffset has depth D, then: ++ * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); ++ * will return nodeoffset itself. ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset. ++ * ++ * returns: ++ ++ * structure block offset of the node at node offset's ancestor ++ * of depth supernodedepth (>=0), on success ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, ++ int supernodedepth, int *nodedepth); ++ ++/** ++ * fdt_node_depth - find the depth of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose parent to find ++ * ++ * fdt_node_depth() finds the depth of a given node. The root node ++ * has depth 0, its immediate subnodes depth 1 and so forth. ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset. ++ * ++ * returns: ++ * depth of the node at nodeoffset (>=0), on success ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_depth(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_parent_offset - find the parent of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose parent to find ++ * ++ * fdt_parent_offset() locates the parent node of a given node (that ++ * is, it finds the offset of the node which contains the node at ++ * nodeoffset as a subnode). ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset, *twice*. ++ * ++ * returns: ++ * structure block offset of the parent of the node at nodeoffset ++ * (>=0), on success ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_parent_offset(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_node_offset_by_prop_value - find nodes with a given property value ++ * @fdt: pointer to the device tree blob ++ * @startoffset: only find nodes after this offset ++ * @propname: property name to check ++ * @propval: property value to search for ++ * @proplen: length of the value in propval ++ * ++ * fdt_node_offset_by_prop_value() returns the offset of the first ++ * node after startoffset, which has a property named propname whose ++ * value is of length proplen and has value equal to propval; or if ++ * startoffset is -1, the very first such node in the tree. ++ * ++ * To iterate through all nodes matching the criterion, the following ++ * idiom can be used: ++ * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, ++ * propval, proplen); ++ * while (offset != -FDT_ERR_NOTFOUND) { ++ * // other code here ++ * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, ++ * propval, proplen); ++ * } ++ * ++ * Note the -1 in the first call to the function, if 0 is used here ++ * instead, the function will never locate the root node, even if it ++ * matches the criterion. ++ * ++ * returns: ++ * structure block offset of the located node (>= 0, >startoffset), ++ * on success ++ * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the ++ * tree after startoffset ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, ++ const char *propname, ++ const void *propval, int proplen); ++ ++/** ++ * fdt_node_offset_by_phandle - find the node with a given phandle ++ * @fdt: pointer to the device tree blob ++ * @phandle: phandle value ++ * ++ * fdt_node_offset_by_phandle() returns the offset of the node ++ * which has the given phandle value. If there is more than one node ++ * in the tree with the given phandle (an invalid tree), results are ++ * undefined. ++ * ++ * returns: ++ * structure block offset of the located node (>= 0), on success ++ * -FDT_ERR_NOTFOUND, no node with that phandle exists ++ * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); ++ ++/** ++ * fdt_node_check_compatible: check a node's compatible property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of a tree node ++ * @compatible: string to match against ++ * ++ * ++ * fdt_node_check_compatible() returns 0 if the given node contains a ++ * 'compatible' property with the given string as one of its elements, ++ * it returns non-zero otherwise, or on error. ++ * ++ * returns: ++ * 0, if the node has a 'compatible' property listing the given string ++ * 1, if the node has a 'compatible' property, but it does not list ++ * the given string ++ * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property ++ * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_check_compatible(const void *fdt, int nodeoffset, ++ const char *compatible); ++ ++/** ++ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value ++ * @fdt: pointer to the device tree blob ++ * @startoffset: only find nodes after this offset ++ * @compatible: 'compatible' string to match against ++ * ++ * fdt_node_offset_by_compatible() returns the offset of the first ++ * node after startoffset, which has a 'compatible' property which ++ * lists the given compatible string; or if startoffset is -1, the ++ * very first such node in the tree. ++ * ++ * To iterate through all nodes matching the criterion, the following ++ * idiom can be used: ++ * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); ++ * while (offset != -FDT_ERR_NOTFOUND) { ++ * // other code here ++ * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); ++ * } ++ * ++ * Note the -1 in the first call to the function, if 0 is used here ++ * instead, the function will never locate the root node, even if it ++ * matches the criterion. ++ * ++ * returns: ++ * structure block offset of the located node (>= 0, >startoffset), ++ * on success ++ * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the ++ * tree after startoffset ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_offset_by_compatible(const void *fdt, int startoffset, ++ const char *compatible); ++ ++/**********************************************************************/ ++/* Write-in-place functions */ ++/**********************************************************************/ ++ ++/** ++ * fdt_setprop_inplace - change a property's value, but not its size ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: pointer to data to replace the property value with ++ * @len: length of the property value ++ * ++ * fdt_setprop_inplace() replaces the value of a given property with ++ * the data in val, of length len. This function cannot change the ++ * size of a property, and so will only work if len is equal to the ++ * current length of the property. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the given property value, and will not alter or move any other part ++ * of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, if len is not equal to the property's current length ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, ++ const void *val, int len); ++ ++/** ++ * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 32-bit integer value to replace the property with ++ * ++ * fdt_setprop_inplace_u32() replaces the value of a given property ++ * with the 32-bit integer value in val, converting val to big-endian ++ * if necessary. This function cannot change the size of a property, ++ * and so will only work if the property already exists and has length ++ * 4. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the given property value, and will not alter or move any other part ++ * of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 64-bit integer value to replace the property with ++ * ++ * fdt_setprop_inplace_u64() replaces the value of a given property ++ * with the 64-bit integer value in val, converting val to big-endian ++ * if necessary. This function cannot change the size of a property, ++ * and so will only work if the property already exists and has length ++ * 8. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the given property value, and will not alter or move any other part ++ * of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, ++ const char *name, uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_inplace_cell - change the value of a single-cell property ++ * ++ * This is an alternative name for fdt_setprop_inplace_u32() ++ */ ++static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); ++} ++ ++/** ++ * fdt_nop_property - replace a property with nop tags ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to nop ++ * @name: name of the property to nop ++ * ++ * fdt_nop_property() will replace a given property's representation ++ * in the blob with FDT_NOP tags, effectively removing it from the ++ * tree. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the property, and will not alter or move any other part of the ++ * tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_nop_property(void *fdt, int nodeoffset, const char *name); ++ ++/** ++ * fdt_nop_node - replace a node (subtree) with nop tags ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node to nop ++ * ++ * fdt_nop_node() will replace a given node's representation in the ++ * blob, including all its subnodes, if any, with FDT_NOP tags, ++ * effectively removing it from the tree. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the node and its properties and subnodes, and will not alter or ++ * move any other part of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_nop_node(void *fdt, int nodeoffset); ++ ++/**********************************************************************/ ++/* Sequential write functions */ ++/**********************************************************************/ ++ ++int fdt_create(void *buf, int bufsize); ++int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); ++int fdt_finish_reservemap(void *fdt); ++int fdt_begin_node(void *fdt, const char *name); ++int fdt_property(void *fdt, const char *name, const void *val, int len); ++static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_property(fdt, name, &val, sizeof(val)); ++} ++static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_property(fdt, name, &val, sizeof(val)); ++} ++static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) ++{ ++ return fdt_property_u32(fdt, name, val); ++} ++#define fdt_property_string(fdt, name, str) \ ++ fdt_property(fdt, name, str, strlen(str)+1) ++int fdt_end_node(void *fdt); ++int fdt_finish(void *fdt); ++ ++/**********************************************************************/ ++/* Read-write functions */ ++/**********************************************************************/ ++ ++int fdt_create_empty_tree(void *buf, int bufsize); ++int fdt_open_into(const void *fdt, void *buf, int bufsize); ++int fdt_pack(void *fdt); ++ ++/** ++ * fdt_add_mem_rsv - add one memory reserve map entry ++ * @fdt: pointer to the device tree blob ++ * @address, @size: 64-bit values (native endian) ++ * ++ * Adds a reserve map entry to the given blob reserving a region at ++ * address address of length size. ++ * ++ * This function will insert data into the reserve map and will ++ * therefore change the indexes of some entries in the table. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new reservation entry ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); ++ ++/** ++ * fdt_del_mem_rsv - remove a memory reserve map entry ++ * @fdt: pointer to the device tree blob ++ * @n: entry to remove ++ * ++ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from ++ * the blob. ++ * ++ * This function will delete data from the reservation table and will ++ * therefore change the indexes of some entries in the table. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there ++ * are less than n+1 reserve map entries) ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_del_mem_rsv(void *fdt, int n); ++ ++/** ++ * fdt_set_name - change the name of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of a node ++ * @name: name to give the node ++ * ++ * fdt_set_name() replaces the name (including unit address, if any) ++ * of the given node with the given string. NOTE: this function can't ++ * efficiently check if the new name is unique amongst the given ++ * node's siblings; results are undefined if this function is invoked ++ * with a name equal to one of the given node's siblings. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob ++ * to contain the new name ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++int fdt_set_name(void *fdt, int nodeoffset, const char *name); ++ ++/** ++ * fdt_setprop - create or change a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: pointer to data to set the property value to ++ * @len: length of the property value ++ * ++ * fdt_setprop() sets the value of the named property in the given ++ * node to the given value and length, creating the property if it ++ * does not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_setprop(void *fdt, int nodeoffset, const char *name, ++ const void *val, int len); ++ ++/** ++ * fdt_setprop_u32 - set a property to a 32-bit integer ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 32-bit integer value for the property (native endian) ++ * ++ * fdt_setprop_u32() sets the value of the named property in the given ++ * node to the given 32-bit integer value (converting to big-endian if ++ * necessary), or creates a new property with that value if it does ++ * not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, ++ uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_u64 - set a property to a 64-bit integer ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 64-bit integer value for the property (native endian) ++ * ++ * fdt_setprop_u64() sets the value of the named property in the given ++ * node to the given 64-bit integer value (converting to big-endian if ++ * necessary), or creates a new property with that value if it does ++ * not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, ++ uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_cell - set a property to a single cell value ++ * ++ * This is an alternative name for fdt_setprop_u32() ++ */ ++static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, ++ uint32_t val) ++{ ++ return fdt_setprop_u32(fdt, nodeoffset, name, val); ++} ++ ++/** ++ * fdt_setprop_string - set a property to a string value ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @str: string value for the property ++ * ++ * fdt_setprop_string() sets the value of the named property in the ++ * given node to the given string value (using the length of the ++ * string to determine the new length of the property), or creates a ++ * new property with that value if it does not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++#define fdt_setprop_string(fdt, nodeoffset, name, str) \ ++ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) ++ ++/** ++ * fdt_appendprop - append to or create a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to append to ++ * @val: pointer to data to append to the property value ++ * @len: length of the data to append to the property value ++ * ++ * fdt_appendprop() appends the value to the named property in the ++ * given node, creating the property if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_appendprop(void *fdt, int nodeoffset, const char *name, ++ const void *val, int len); ++ ++/** ++ * fdt_appendprop_u32 - append a 32-bit integer value to a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 32-bit integer value to append to the property (native endian) ++ * ++ * fdt_appendprop_u32() appends the given 32-bit integer value ++ * (converting to big-endian if necessary) to the value of the named ++ * property in the given node, or creates a new property with that ++ * value if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_appendprop_u64 - append a 64-bit integer value to a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 64-bit integer value to append to the property (native endian) ++ * ++ * fdt_appendprop_u64() appends the given 64-bit integer value ++ * (converting to big-endian if necessary) to the value of the named ++ * property in the given node, or creates a new property with that ++ * value if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, ++ const char *name, uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_appendprop_cell - append a single cell value to a property ++ * ++ * This is an alternative name for fdt_appendprop_u32() ++ */ ++static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ return fdt_appendprop_u32(fdt, nodeoffset, name, val); ++} ++ ++/** ++ * fdt_appendprop_string - append a string to a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @str: string value to append to the property ++ * ++ * fdt_appendprop_string() appends the given string to the value of ++ * the named property in the given node, or creates a new property ++ * with that value if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ ++ fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) ++ ++/** ++ * fdt_delprop - delete a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to nop ++ * @name: name of the property to nop ++ * ++ * fdt_del_property() will delete the given property. ++ * ++ * This function will delete data from the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_delprop(void *fdt, int nodeoffset, const char *name); ++ ++/** ++ * fdt_add_subnode_namelen - creates a new node based on substring ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * @namelen: number of characters of name to consider ++ * ++ * Identical to fdt_add_subnode(), but use only the first namelen ++ * characters of name as the name of the new node. This is useful for ++ * creating subnodes based on a portion of a larger string, such as a ++ * full path. ++ */ ++int fdt_add_subnode_namelen(void *fdt, int parentoffset, ++ const char *name, int namelen); ++ ++/** ++ * fdt_add_subnode - creates a new node ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * ++ * fdt_add_subnode() creates a new node as a subnode of the node at ++ * structure block offset parentoffset, with the given name (which ++ * should include the unit address, if any). ++ * ++ * This function will insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ ++ * returns: ++ * structure block offset of the created nodeequested subnode (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the requested subnode does not exist ++ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag ++ * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of ++ * the given name ++ * -FDT_ERR_NOSPACE, if there is insufficient free space in the ++ * blob to contain the new node ++ * -FDT_ERR_NOSPACE ++ * -FDT_ERR_BADLAYOUT ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_add_subnode(void *fdt, int parentoffset, const char *name); ++ ++/** ++ * fdt_del_node - delete a node (subtree) ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node to nop ++ * ++ * fdt_del_node() will remove the given node, including all its ++ * subnodes if any, from the blob. ++ * ++ * This function will delete data from the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_del_node(void *fdt, int nodeoffset); ++ ++/**********************************************************************/ ++/* Debugging / informational functions */ ++/**********************************************************************/ ++ ++const char *fdt_strerror(int errval); ++ ++#endif /* _LIBFDT_H */ +diff --git a/arch/arm/mach-sstar/libfdt_env.h b/arch/arm/mach-sstar/libfdt_env.h +new file mode 100755 +index 000000000000..ba1cc752daaa +--- /dev/null ++++ b/arch/arm/mach-sstar/libfdt_env.h +@@ -0,0 +1,32 @@ ++/* ++* libfdt_env.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _ARM_LIBFDT_ENV_H ++#define _ARM_LIBFDT_ENV_H ++ ++#include ++#include ++#include ++ ++#define fdt16_to_cpu(x) be16_to_cpu(x) ++#define cpu_to_fdt16(x) cpu_to_be16(x) ++#define fdt32_to_cpu(x) be32_to_cpu(x) ++#define cpu_to_fdt32(x) cpu_to_be32(x) ++#define fdt64_to_cpu(x) be64_to_cpu(x) ++#define cpu_to_fdt64(x) cpu_to_be64(x) ++ ++#endif +diff --git a/arch/arm/mach-sstar/ms_chip.c b/arch/arm/mach-sstar/ms_chip.c +new file mode 100755 +index 000000000000..5e426150e8b5 +--- /dev/null ++++ b/arch/arm/mach-sstar/ms_chip.c +@@ -0,0 +1,671 @@ ++/* ++* ms_chip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++// ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++// ++//#include ++#include ++#include ++#include ++#include "mdrv_API_version.h" ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_version.h" ++#include "registers.h" ++#include ++ ++#define UNUSED(var) (void)((var) = (var)) ++ ++#ifdef CONFIG_OUTER_CACHE ++ static DEFINE_SPINLOCK(infinity_irq_L2_lock); ++#endif ++ ++DEFINE_SEMAPHORE(PfModeSem); ++DEFINE_MUTEX(FCIE3_mutex); ++EXPORT_SYMBOL(FCIE3_mutex); ++static struct ms_chip chip_funcs; ++ ++const struct MS_BIN_OPTION ms_image_size __attribute__ ((aligned (16))) = ++{ ++ {'#','I','M','G','_','S','Z','#'}, ++ {0,0,0,0,0,0,0,0} ++}; ++ ++const struct MS_BIN_OPTION ms_XIP_phys_addr __attribute__ ((aligned (16))) = ++{ ++ {'#','X','I','P','_','P','A','#'}, ++ {0,0,0,0,0,0,0,0} ++}; ++ ++ ++static char NONE_platform_name[]="NONE"; ++////const struct MS_BIN_OPTION ms_builtin_dtb_size __attribute__ ((aligned (16)))= ++////{ ++//// {'#','D','T','B','_','S','Z','#'}, ++//// {0,0,0,0,0,0,0,0} ++////}; ++// ++// ++ ++#ifdef CONFIG_SS_BUILTIN_DTB ++#define BUILTIN_DTB_SZ (64*1024) ++struct MS_BUILTIN_DTB ++{ ++ struct MS_BIN_OPTION ms_dtb; ++ u8 content[BUILTIN_DTB_SZ]; ++}; ++ ++ ++struct MS_BUILTIN_DTB builtin_dtb __attribute__ ((aligned (16)))= ++{ ++ .ms_dtb={ {'#','M','S','_','D','T','B','#'}, {0,0,0,0,0,0,0,0}}, ++}; ++void *builtin_dtb_start=(void *)builtin_dtb.content; ++const u32 builtin_dtb_size=BUILTIN_DTB_SZ; ++#endif ++ ++#ifdef CONFIG_SS_BUILTIN_UNFDT ++#define BUILTIN_UNFDT_SZ (144*1024) ++struct MS_BUILTIN_UNFDT ++{ ++ struct MS_BIN_OPTION ms_dtb; ++ u8 content[BUILTIN_UNFDT_SZ]; ++}; ++ ++struct MS_BUILTIN_UNFDT builtin_unfdt __attribute__ ((aligned (16)))= ++{ ++ .ms_dtb={ {'#','U','N','F','D','T','_','#'}, {0,0,0,0,0,0,0,0}}, ++}; ++void *builtin_unfdt_start = (void *)builtin_unfdt.content; ++void *unfdt_runtime_base =(void*) &builtin_unfdt.ms_dtb.args[0]; ++void *fdt_runtime_base =(void*) &builtin_unfdt.ms_dtb.args[4]; ++#endif ++ ++//MS_VERSION LX_VERSION = ++//{ ++// {'M','V','X'}, ++// MVXV_HEAD_VER, ++// MVXV_LIB_TYPE, //R = general release version ++// MVXV_CHIP_ID, ++// MVXV_CHANGELIST, ++// MVXV_COMP_ID, ++// {'#'}, ++// {'X','V','M'}, ++//}; ++ ++#if defined(MVXV_EXT) ++#define MVXV_V2 "MVX" MVXV_HEAD_VER MVXV_LIB_TYPE MVXV_CHIP_ID MVXV_CHANGELIST MVXV_COMP_ID MVXV_EXT "#XVM" ++#else ++#define MVXV_V2 "MVX" MVXV_HEAD_VER MVXV_LIB_TYPE MVXV_CHIP_ID MVXV_CHANGELIST MVXV_COMP_ID "#XVM" ++#endif ++const char* LX_VERSION=MVXV_V2; ++ ++const char *ms_API_version=""KL_API_VERSION; ++ ++void Chip_Flush_MIU_Pipe(void){ ++ chip_funcs.chip_flush_miu_pipe(); ++} ++ ++void Chip_Flush_MIU_Pipe_Nodsb(void){ ++ chip_funcs.chip_flush_miu_pipe_nodsb(); ++} ++ ++void Chip_Flush_Dcache_Page(struct page *page){ ++ chip_funcs.cache_flush_dcache_page(page); ++} ++ ++void Chip_Flush_Memory(void){ ++ chip_funcs.chip_flush_memory(); ++} ++ ++void Chip_Read_Memory(void){ ++ chip_funcs.chip_read_memory(); ++} ++ ++void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ chip_funcs.cache_flush_range_va_pa(u32VAddr,u32PAddr,u32Size); ++} ++ ++void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ chip_funcs.cache_clean_range_va_pa(u32VAddr,u32PAddr,u32Size); ++} ++ ++void Chip_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ chip_funcs.cache_flush_range(u32Addr,u32Size); ++} ++ ++void Chip_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ chip_funcs.cache_clean_range(u32Addr,u32Size); ++} ++ ++void Chip_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ chip_funcs.cache_invalidate_range(u32Addr,u32Size); ++} ++ ++void Chip_Flush_CacheAll(void) ++{ ++ chip_funcs.cache_flush_all(); ++} ++ ++ ++u64 Chip_Phys_to_MIU(u64 phys) ++{ ++ return chip_funcs.phys_to_miu(phys); ++} ++ ++u64 Chip_MIU_to_Phys(u64 miu) ++{ ++ return chip_funcs.miu_to_phys(miu); ++} ++ ++ ++int Chip_Get_Device_ID(void) ++{ ++ return chip_funcs.chip_get_device_id(); ++} ++ ++int Chip_Get_Revision(void) ++{ ++ return chip_funcs.chip_get_revision(); ++} ++ ++ ++int Chip_Cache_Outer_Is_Enabled(void) ++{ ++ return chip_funcs.cache_outer_is_enabled(); ++} ++ ++ ++int Chip_Boot_Get_Dev_Type(void) ++{ ++ return (int)((MS_BOOT_DEV_TYPE)chip_funcs.chip_get_boot_dev_type()); ++} ++ ++char* Chip_Get_Platform_Name(void) ++{ ++ char *name=chip_funcs.chip_get_platform_name(); ++ if(name==NULL || strlen(name) > 15 ) ++ { ++ //printk(KERN_ERR "platform name invalid!! must not be NULL & < 15 chars\n"); ++ BUG(); ++ } ++ ++ return name; ++} ++ ++const char* Chip_Get_API_Version(void) ++{ ++ return chip_funcs.chip_get_API_version(); ++} ++ ++ ++//u32 Chip_Get_Image_Size(void) ++//{ ++// return (u32)(__le32_to_cpu(*((__le64 *)((void *)&ms_.args[0])))); ++//} ++//// ++//u32 Chip_Get_DTB_Size(void) ++//{ ++// return (u32)(__le32_to_cpu(*((__le64 *)((void *)&MS_DTB_SIZE.args[0])))); ++//} ++ ++/************************************* ++* default chip function ++*************************************/ ++ ++static char* _default_Get_Platform_Name(void) ++{ ++ return NONE_platform_name; ++} ++ ++ ++static u64 _default_Phys_to_MIU(u64 phys) ++{ ++ return phys; ++} ++ ++static u64 _default_MIU_to_Phys(u64 miu) ++{ ++ return miu; ++} ++ ++static void _default_flush_miu_pipe(void) ++{ ++ ++} ++// ++ ++static void _default_Flush_Memory(void) ++{ ++ ++#ifdef CONFIG_MS_L2X0_PATCH ++ if(outer_cache.sync) ++ outer_cache.sync(); ++ else ++#endif ++ Chip_Flush_MIU_Pipe_Nodsb(); ++} ++ ++ ++static void _default_Read_Memory(void) ++{ ++ ++#ifdef CONFIG_MS_L2X0_PATCH ++ if(outer_cache.sync) ++ outer_cache.sync(); ++ else ++#endif ++ Chip_Flush_MIU_Pipe_Nodsb(); ++} ++ ++ ++//DCACHE_FLUSH function ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++void hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#if 1 ++static void _default_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ if(((void *) u32VAddr) == NULL) ++ { ++ printk("u32VAddr is invalid\n"); ++ return; ++ } ++ //Clean L1 ++ //dmac_map_area((void *)u32VAddr,u32Size,1); ++ dma_sync_single_for_cpu(NULL, virt_to_dma(NULL, (void*)u32VAddr), u32Size, DMA_TO_DEVICE); ++ ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ //Clean L2 by Way ++ outer_cache.clean_range(u32PAddr,u32PAddr + u32Size); ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe_Nodsb(); ++#endif ++} ++ ++static void _default_Flush_Dcache_Page(struct page *page) ++{ ++ flush_dcache_page(page); ++ Chip_Flush_MIU_Pipe_Nodsb(); ++} ++ ++static void _default_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ if(((void *) u32VAddr) == NULL) ++ { ++ printk("u32VAddr is invalid\n"); ++ return; ++ } ++ //Clean & Invalid L1 ++ dmac_flush_range((void *)u32VAddr, (void *)(u32VAddr + u32Size)); ++ ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ //Clean&Inv L2 by range ++ outer_cache.flush_range(u32PAddr,u32PAddr + u32Size); ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe_Nodsb(); ++#endif ++} ++#endif ++ ++static void _default_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++#ifdef CONFIG_OUTER_CACHE ++ unsigned long flags; ++#endif ++ if( u32Addr == (unsigned long) NULL ) ++ { ++ printk("u32Addr is invalid\n"); ++ return; ++ } ++ //Clean L1 & Inv L1 ++ dmac_flush_range((const void *)u32Addr,(const void *)(u32Addr + u32Size)); ++ ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1 )){ ++ //Clean&Inv L2 by Way ++ spin_lock_irqsave(&infinity_irq_L2_lock, flags); ++ outer_cache.flush_all(); ++ spin_unlock_irqrestore(&infinity_irq_L2_lock, flags);} ++ else ++ //Clean&Inv L2 by Range ++ outer_cache.flush_range(__pa(u32Addr) , __pa(u32Addr) + u32Size); ++ ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe_Nodsb(); ++#endif ++ ++} ++ ++static void _default_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ if( u32Addr ==(unsigned long) NULL ) ++ { ++ printk("u32Addr is invalid\n"); ++ return; ++ } ++ //Clean L1 ++ //dmac_map_area((const void *)u32Addr,(size_t)u32Size,1); ++ dma_sync_single_for_cpu(NULL, virt_to_dma(NULL, (void*)u32Addr), u32Size, DMA_TO_DEVICE); ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1)) ++ { ++ //Clean L2 by range ++ outer_cache.flush_all(); ++ } ++ else ++ //Clean&Inv L2 by Range ++ outer_cache.clean_range(__pa(u32Addr) , __pa(u32Addr) + u32Size); ++ } ++#endif ++ ++ #ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe_Nodsb(); ++ #endif ++} ++ ++ ++static void _default_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ if( u32Addr == (unsigned long) NULL ) ++ { ++ printk("u32Addr is invalid\n"); ++ return; ++ } ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1)) ++ { ++ printk("%s:Input VA can't be converted to PA\n",__func__); ++ } ++ else ++ { ++ //Inv L2 by range ++ outer_cache.inv_range(__pa(u32Addr) , __pa(u32Addr)+ u32Size); ++ } ++ } ++#endif ++ //Inv L1 ++ //dmac_map_area((const void *)u32Addr,(size_t)u32Size,2); ++ dma_sync_single_for_cpu(NULL, virt_to_dma(NULL, (void*)u32Addr), u32Size, DMA_FROM_DEVICE); ++ ++} ++ ++static void _default_Flush_CacheAll(void) ++{ ++ ++ __cpuc_flush_icache_all(); ++ __cpuc_flush_kern_all(); ++ __cpuc_flush_user_all(); ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ //Clean&Inv L2 by range ++ outer_cache.flush_all(); ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe_Nodsb(); ++#endif ++} ++ ++ ++static int _default_Get_Revision(void) ++{ ++ return 0; ++} ++ ++static int _default_Get_ID(void) ++{ ++ return (int)DEVICE_ID_END; ++} ++ ++ ++static int _default_Get_Boot_Dev_Type(void) ++{ ++ return (int)MS_BOOT_DEV_NONE; ++} ++ ++static int _default_get_storage_type(void) ++{ ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int _default_get_package_type(void) ++{ ++ return 0; ++} ++ ++ ++static int _default_Outer_Cache_Is_Enabled(void) ++{ ++ return 0; ++} ++ ++ ++static unsigned long long _default_Get_RIU_Phys(void) ++{ ++ return 0; ++} ++ ++static int _default_Get_RIU_Size(void) ++{ ++ return 0; ++} ++ ++static int _default_chip_function_set(int id, int param) ++{ ++ UNUSED(id); ++ UNUSED(param); ++ //printk(KERN_ERR "CHIP_FUNCTION not yet implemented\n!!"); ++ return -1; ++} ++ ++ ++static const char* _default_chip_get_API_version(void) ++{ ++ return ms_API_version; ++} ++ ++static u64 _default_chip_get_us_ticks(void) ++{ ++ return 0; ++} ++ ++struct ms_chip* ms_chip_get(void) ++{ ++ return &chip_funcs; ++} ++ ++void __init ms_chip_init_default(void) ++{ ++ chip_funcs.cache_clean_range=_default_Clean_Cache_Range; ++ chip_funcs.cache_flush_range=_default_Flush_Cache_Range; ++ chip_funcs.cache_flush_all=_default_Flush_CacheAll; ++ chip_funcs.cache_invalidate_range=_default_Inv_Cache_Range; ++ ++ chip_funcs.cache_clean_range_va_pa=_default_Clean_Cache_Range_VA_PA; ++ chip_funcs.cache_flush_range_va_pa=_default_Flush_Cache_Range_VA_PA; ++ chip_funcs.cache_flush_dcache_page=_default_Flush_Dcache_Page; ++ ++ chip_funcs.chip_flush_memory=_default_Flush_Memory; ++ chip_funcs.chip_read_memory=_default_Read_Memory; ++ chip_funcs.chip_flush_miu_pipe=_default_flush_miu_pipe; ++ ++ chip_funcs.phys_to_miu=_default_Phys_to_MIU; ++ chip_funcs.miu_to_phys=_default_MIU_to_Phys; ++ ++ chip_funcs.chip_get_device_id=_default_Get_ID; ++ chip_funcs.chip_get_revision=_default_Get_Revision; ++ ++ chip_funcs.cache_outer_is_enabled=_default_Outer_Cache_Is_Enabled; ++ ++ chip_funcs.chip_get_boot_dev_type=_default_Get_Boot_Dev_Type; ++ chip_funcs.chip_get_platform_name=_default_Get_Platform_Name; ++ ++ chip_funcs.chip_get_riu_phys=_default_Get_RIU_Phys; ++ chip_funcs.chip_get_riu_size=_default_Get_RIU_Size; ++ ++ chip_funcs.chip_function_set=_default_chip_function_set; ++ ++ chip_funcs.chip_get_API_version=_default_chip_get_API_version; ++ ++ chip_funcs.chip_get_storage_type=_default_get_storage_type; ++ chip_funcs.chip_get_package_type=_default_get_package_type; ++ ++ chip_funcs.chip_get_us_ticks=_default_chip_get_us_ticks; ++ ++} ++ ++unsigned long long Chip_Get_RIU_Phys(void) ++{ ++ return chip_funcs.chip_get_riu_phys(); ++} ++ ++int Chip_Get_RIU_Size(void) ++{ ++ return chip_funcs.chip_get_riu_size(); ++} ++ ++ ++int Chip_Function_Set(int function_id, int param) ++{ ++ return chip_funcs.chip_function_set(function_id,param); ++} ++ ++int Chip_Get_Storage_Type(void) ++{ ++ return (int)chip_funcs.chip_get_storage_type(); ++} ++ ++int Chip_Get_Package_Type(void) ++{ ++ return (int)chip_funcs.chip_get_package_type(); ++} ++ ++u64 Chip_Get_US_Ticks(void) ++{ ++ return chip_funcs.chip_get_us_ticks(); ++} ++ ++EXPORT_SYMBOL(ms_chip_get); ++ ++EXPORT_SYMBOL(Chip_Flush_MIU_Pipe); ++EXPORT_SYMBOL(Chip_Flush_Dcache_Page); ++EXPORT_SYMBOL(v7_dma_flush_range); ++EXPORT_SYMBOL(Chip_Flush_Memory); ++EXPORT_SYMBOL(Chip_Read_Memory); ++EXPORT_SYMBOL(Chip_Flush_Cache_Range_VA_PA); ++EXPORT_SYMBOL(Chip_Clean_Cache_Range_VA_PA); ++EXPORT_SYMBOL(Chip_Flush_Cache_Range); ++EXPORT_SYMBOL(Chip_Clean_Cache_Range); ++EXPORT_SYMBOL(Chip_Inv_Cache_Range); ++EXPORT_SYMBOL(Chip_Flush_CacheAll); ++EXPORT_SYMBOL(Chip_Phys_to_MIU); ++EXPORT_SYMBOL(Chip_MIU_to_Phys); ++ ++EXPORT_SYMBOL(Chip_Cache_Outer_Is_Enabled); ++ ++EXPORT_SYMBOL(Chip_Get_Device_ID); ++EXPORT_SYMBOL(Chip_Get_Revision); ++EXPORT_SYMBOL(Chip_Get_Platform_Name); ++EXPORT_SYMBOL(Chip_Boot_Get_Dev_Type); ++EXPORT_SYMBOL(Chip_Get_Storage_Type); ++EXPORT_SYMBOL(Chip_Get_Package_Type); ++ ++EXPORT_SYMBOL(Chip_Get_US_Ticks); ++ ++EXPORT_SYMBOL(Chip_Get_RIU_Phys); ++EXPORT_SYMBOL(Chip_Get_RIU_Size); ++EXPORT_SYMBOL(Chip_Function_Set); ++ ++ ++ ++ ++ +diff --git a/arch/arm/mach-sstar/prof.c b/arch/arm/mach-sstar/prof.c +new file mode 100755 +index 000000000000..b3bb1b889f29 +--- /dev/null ++++ b/arch/arm/mach-sstar/prof.c +@@ -0,0 +1,176 @@ ++/* ++* prof.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include ++ ++#if 1 ++#define RECORD_IPL_ADDR 0xF900F000 //IPL ++#define RECORD_BL_ADDR 0xF900F400 //BL ++#define RECORD_ADDR 0xF900F800 //LINUX 0XA0 ++ ++ ++#define MAX_RECORD 800 /*max:(0x18000-0xF800)/40~=870*/ ++#define MAX_LANGTH 32 ++struct timestamp { ++ unsigned int timestamp_us; /* 4 */ ++ unsigned int mark; /* 4, ex:__line__ */ ++ unsigned char name[MAX_LANGTH]; /*32, ex:__function__*/ ++}; ++struct timecrecord { ++ U32 count; ++ struct timestamp tt[MAX_RECORD]; ++}; ++ ++int g_record_inited = 0; ++void* g_addr_record_ipl = 0; ++void* g_addr_record_bl = 0; ++void* g_addr_record_kernel= 0; ++ ++void recode_timestamp_init(void) ++{ ++ g_record_inited = 0; ++} ++ ++U64 arch_counter_get_cntpct(void) ++{ ++ U64 cval; ++ asm volatile("isb " : : : "memory"); ++ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); ++ return cval; ++} ++ ++unsigned int read_timestamp(void) ++{ ++ u64 cycles=arch_counter_get_cntpct(); ++ u64 usticks=div64_u64(cycles, 6/*us_ticks_factor*/); ++ return (unsigned int) usticks; ++} ++void recode_timestamp(int mark, const char* name) ++{ ++ struct timecrecord *tc; ++ ++ tc = (struct timecrecord *) (RECORD_ADDR); ++ if(!g_record_inited) ++ { ++ tc->count = 0; ++ g_record_inited=1; ++ } ++ ++ if(tc->count < MAX_RECORD) ++ { ++ tc->tt[tc->count].timestamp_us = read_timestamp(); ++ tc->tt[tc->count].mark = mark; ++ strncpy(tc->tt[tc->count].name, name, MAX_LANGTH-1); ++ tc->count++; ++ } ++} ++EXPORT_SYMBOL(recode_timestamp); ++ ++void recode_timestamp_ext(int mark, const char* name, unsigned int timestamp) ++{ ++ struct timecrecord *tc; ++ ++ tc = (struct timecrecord *) (RECORD_ADDR); ++ if(!g_record_inited) ++ { ++ tc->count = 0; ++ g_record_inited=1; ++ } ++ ++ if(tc->count < MAX_RECORD) ++ { ++ tc->tt[tc->count].timestamp_us = timestamp; ++ tc->tt[tc->count].mark = mark; ++ strncpy(tc->tt[tc->count].name, name, MAX_LANGTH-1); ++ tc->count++; ++ } ++} ++ ++void recode_show(void) ++{ ++ struct timecrecord *tc; ++ int i=0; ++ ++ tc = (struct timecrecord *) (RECORD_IPL_ADDR); // IMI SRAM ++ if( tc->count <= MAX_RECORD && tc->count>0) ++ { ++ printk(KERN_CRIT"IPL: 0x%p\n", tc); ++ for( i=0; icount; i++) ++ { ++ tc->tt[i].name[MAX_LANGTH-1]='\0'; ++ ++ printk(KERN_CRIT"%03d time:%8u, diff:%8u, %s, %d\n", ++ i, ++ tc->tt[i].timestamp_us, ++ tc->tt[i].timestamp_us-tc->tt[i?i-1:i].timestamp_us, ++ tc->tt[i].name, ++ tc->tt[i].mark); ++ ++ } ++ printk(KERN_CRIT"Total cost:%8u(us)\n", tc->tt[tc->count-1].timestamp_us - tc->tt[0].timestamp_us ); ++ } ++ ++ Chip_Inv_Cache_Range(RECORD_BL_ADDR, RECORD_ADDR - RECORD_BL_ADDR); ++ tc = (struct timecrecord *) (RECORD_BL_ADDR); // IMI SRAM ++ if( tc->count <= MAX_RECORD && tc->count>0) ++ { ++ printk(KERN_CRIT"BL: 0x%p\n", tc); ++ for( i=0; icount; i++) ++ { ++ tc->tt[i].name[MAX_LANGTH-1]='\0'; ++ ++ printk(KERN_CRIT"%03d time:%8u, diff:%8u, %s, %d\n", ++ i, ++ tc->tt[i].timestamp_us, ++ tc->tt[i].timestamp_us-tc->tt[i?i-1:i].timestamp_us, ++ tc->tt[i].name, ++ tc->tt[i].mark); ++ ++ } ++ printk(KERN_CRIT"Total cost:%8u(us)\n", tc->tt[tc->count-1].timestamp_us - tc->tt[0].timestamp_us ); ++ } ++ ++ tc = (struct timecrecord *) (RECORD_ADDR); // IMI SRAM ++ if( tc->count <= MAX_RECORD && tc->count>0) ++ { ++ printk(KERN_CRIT"Linux:0x%p\n", tc); ++ for( i=0; icount; i++) ++ { ++ tc->tt[i].name[MAX_LANGTH-1]='\0'; ++ ++ printk(KERN_CRIT"%03d time:%8u, diff:%8u, %s, %d\n", ++ i, ++ tc->tt[i].timestamp_us, ++ tc->tt[i].timestamp_us-tc->tt[i?i-1:i].timestamp_us, ++ tc->tt[i].name, ++ tc->tt[i].mark); ++ ++ } ++ printk(KERN_CRIT"Total cost:%8u(us)\n", tc->tt[tc->count-1].timestamp_us - tc->tt[0].timestamp_us ); ++ } ++ ++} ++#else ++void recode_timestamp(int mark, const char* name){} ++void recode_show(void){} ++unsigned int read_timestamp(void){return 0;} ++void recode_timestamp_ext(int mark, const char* name, unsigned int timestamp){} ++#endif +diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile +index e8698241ece9..9794686d9644 100644 +--- a/arch/arm/mm/Makefile ++++ b/arch/arm/mm/Makefile +@@ -7,6 +7,7 @@ obj-y := dma-mapping.o extable.o fault.o init.o \ + + obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \ + mmap.o pgd.o mmu.o pageattr.o ++KASAN_SANITIZE_mmu.o := n + + ifneq ($(CONFIG_MMU),y) + obj-y += nommu.o +@@ -14,6 +15,7 @@ endif + + obj-$(CONFIG_ARM_PTDUMP) += dump.o + obj-$(CONFIG_MODULES) += proc-syms.o ++KASAN_SANITIZE_physaddr.o := n + + obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o + obj-$(CONFIG_HIGHMEM) += highmem.o +@@ -107,3 +109,6 @@ obj-$(CONFIG_CACHE_L2X0_PMU) += cache-l2x0-pmu.o + obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o + obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o + obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o ++ ++KASAN_SANITIZE_kasan_init.o := n ++obj-$(CONFIG_KASAN) += kasan_init.o +diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c +old mode 100644 +new mode 100755 +index d1870c777c6e..e496980f73b5 +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -182,6 +182,12 @@ static void l2c_resume(void) + static void __l2c210_cache_sync(void __iomem *base) + { + writel_relaxed(0, base + sync_reg_offset); ++#ifdef CONFIG_MS_L2X0_PATCH ++ if(outer_cache.flush_MIU_pipe) ++ { ++ outer_cache.flush_MIU_pipe(); ++ } ++#endif + } + + static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, +@@ -753,6 +759,12 @@ static void l2c310_disable(void) + + static void l2c310_resume(void) + { ++#if defined(CONFIG_MS_L2X0_PATCH) ++ if(outer_cache.flush_MIU_pipe) ++ { ++ outer_cache.flush_MIU_pipe(); ++ } ++#endif + l2c_resume(); + + /* Re-enable full-line-of-zeros for Cortex-A9 */ +diff --git a/arch/arm/mm/dma.h b/arch/arm/mm/dma.h +old mode 100644 +new mode 100755 +diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c +old mode 100644 +new mode 100755 +index 4c587ad8bfe3..28ca28936580 +--- a/arch/arm/mm/init.c ++++ b/arch/arm/mm/init.c +@@ -227,6 +227,10 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align) + return phys; + } + ++#ifdef CONFIG_MSTAR_MMAHEAP ++extern void deal_with_reserve_mma_heap(void); ++#endif ++ + void __init arm_memblock_init(const struct machine_desc *mdesc) + { + /* Register the kernel text, kernel data and initrd with memblock. */ +@@ -272,6 +276,12 @@ void __init arm_memblock_init(const struct machine_desc *mdesc) + early_init_fdt_reserve_self(); + early_init_fdt_scan_reserved_mem(); + ++// first reserve for mstar, ++//not place call this deal_with_reserve_mma_heap function in the end of arm_memblock_init. ++#ifdef CONFIG_MSTAR_MMAHEAP ++ deal_with_reserve_mma_heap(); ++#endif ++ + /* reserve memory for DMA contiguous allocations */ + dma_contiguous_reserve(arm_dma_limit); + +diff --git a/arch/arm/mm/kasan_init.c b/arch/arm/mm/kasan_init.c +new file mode 100644 +index 000000000000..31818f4cfcc4 +--- /dev/null ++++ b/arch/arm/mm/kasan_init.c +@@ -0,0 +1,290 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * This file contains kasan initialization code for ARM. ++ * ++ * Copyright (c) 2018 Samsung Electronics Co., Ltd. ++ * Author: Andrey Ryabinin ++ * Author: Linus Walleij ++ */ ++ ++#define pr_fmt(fmt) "kasan: " fmt ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mm.h" ++ ++static pgd_t tmp_pgd_table[PTRS_PER_PGD] __initdata __aligned(PGD_SIZE); ++ ++pmd_t tmp_pmd_table[PTRS_PER_PMD] __page_aligned_bss; ++ ++static __init void *kasan_alloc_block(size_t size) ++{ ++ return memblock_virt_alloc_try_nid(size, size, __pa(MAX_DMA_ADDRESS), ++ MEMBLOCK_ALLOC_KASAN, NUMA_NO_NODE); ++} ++ ++static void __init kasan_pte_populate(pmd_t *pmdp, unsigned long addr, ++ unsigned long end, bool early) ++{ ++ unsigned long next; ++ pte_t *ptep = pte_offset_kernel(pmdp, addr); ++ ++ do { ++ pte_t entry; ++ void *p; ++ ++ next = addr + PAGE_SIZE; ++ ++ if (!early) { ++ if (!pte_none(READ_ONCE(*ptep))) ++ continue; ++ ++ p = kasan_alloc_block(PAGE_SIZE); ++ if (!p) { ++ panic("%s failed to allocate shadow page for address 0x%lx\n", ++ __func__, addr); ++ return; ++ } ++ memset(p, KASAN_SHADOW_INIT, PAGE_SIZE); ++ entry = pfn_pte(virt_to_pfn(p), ++ __pgprot(pgprot_val(PAGE_KERNEL))); ++ } else if (pte_none(READ_ONCE(*ptep))) { ++ /* ++ * The early shadow memory is mapping all KASan ++ * operations to one and the same page in memory, ++ * "kasan_zero_page" so that the instrumentation ++ * will work on a scratch area until we can set up the ++ * proper KASan shadow memory. ++ */ ++ entry = pfn_pte(virt_to_pfn(kasan_zero_page), ++ __pgprot(_L_PTE_DEFAULT | L_PTE_DIRTY | L_PTE_XN)); ++ } else { ++ /* ++ * Early shadow mappings are PMD_SIZE aligned, so if the ++ * first entry is already set, they must all be set. ++ */ ++ return; ++ } ++ ++ set_pte_at(&init_mm, addr, ptep, entry); ++ } while (ptep++, addr = next, addr != end); ++} ++ ++/* ++ * The pmd (page middle directory) is only used on LPAE ++ */ ++static void __init kasan_pmd_populate(pud_t *pudp, unsigned long addr, ++ unsigned long end, bool early) ++{ ++ unsigned long next; ++ pmd_t *pmdp = pmd_offset(pudp, addr); ++ ++ do { ++ if (pmd_none(*pmdp)) { ++ /* ++ * We attempt to allocate a shadow block for the PMDs ++ * used by the PTEs for this address if it isn't already ++ * allocated. ++ */ ++ void *p = early ? kasan_zero_pte : ++ kasan_alloc_block(PAGE_SIZE); ++ ++ if (!p) { ++ panic("%s failed to allocate shadow block for address 0x%lx\n", ++ __func__, addr); ++ return; ++ } ++ pmd_populate_kernel(&init_mm, pmdp, p); ++ flush_pmd_entry(pmdp); ++ } ++ ++ next = pmd_addr_end(addr, end); ++ kasan_pte_populate(pmdp, addr, next, early); ++ } while (pmdp++, addr = next, addr != end); ++} ++ ++static void __init kasan_pgd_populate(unsigned long addr, unsigned long end, ++ bool early) ++{ ++ unsigned long next; ++ pgd_t *pgdp; ++ pud_t *pudp; ++ ++ pgdp = pgd_offset_k(addr); ++ ++ do { ++ /* ++ * Allocate and populate the shadow block of pud folded into ++ * into pmd if it doesn't already exist ++ */ ++ if (!early && pgd_none(*pgdp)) { ++ void *p = kasan_alloc_block(PAGE_SIZE); ++ ++ if (!p) { ++ panic("%s failed to allocate shadow block for address 0x%lx\n", ++ __func__, addr); ++ return; ++ } ++ pgd_populate(&init_mm, pgdp, p); ++ } ++ ++ next = pgd_addr_end(addr, end); ++ /* ++ * We just immediately jump over the pud page directories since ++ * we believe ARM32 will never gain four level page tables. ++ */ ++ pudp = pud_offset(pgdp, addr); ++ ++ kasan_pmd_populate(pudp, addr, next, early); ++ } while (pgdp++, addr = next, addr != end); ++} ++ ++extern struct proc_info_list *lookup_processor_type(unsigned int); ++ ++void __init kasan_early_init(void) ++{ ++ struct proc_info_list *list; ++ ++ /* ++ * locate processor in the list of supported processor ++ * types. The linker builds this table for us from the ++ * entries in arch/arm/mm/proc-*.S ++ */ ++ list = lookup_processor_type(read_cpuid_id()); ++ if (list) { ++#ifdef MULTI_CPU ++ processor = *list->proc; ++#endif ++ } ++ ++ BUILD_BUG_ON((KASAN_SHADOW_END - (1UL << 29)) != KASAN_SHADOW_OFFSET); ++ /* ++ * We walk the page table and set all of the shadow memory to point ++ * to the scratch page. ++ */ ++ kasan_pgd_populate(KASAN_SHADOW_START, KASAN_SHADOW_END, true); ++} ++ ++static void __init clear_pgds(unsigned long start, ++ unsigned long end) ++{ ++ for (; start && start < end; start += PMD_SIZE) ++ pmd_clear(pmd_off_k(start)); ++} ++ ++static int __init create_mapping(void *start, void *end) ++{ ++ void *shadow_start, *shadow_end; ++ ++ shadow_start = kasan_mem_to_shadow(start); ++ shadow_end = kasan_mem_to_shadow(end); ++ ++ pr_info("Mapping kernel virtual memory block: %px-%px at shadow: %px-%px\n", ++ start, end, shadow_start, shadow_end); ++ ++ kasan_pgd_populate((unsigned long)shadow_start & PAGE_MASK, ++ PAGE_ALIGN((unsigned long)shadow_end), false); ++ return 0; ++} ++ ++void __init kasan_init(void) ++{ ++ struct memblock_region *reg; ++ int i; ++ ++ /* ++ * We are going to perform proper setup of shadow memory. ++ * ++ * At first we should unmap early shadow (clear_pgds() call bellow). ++ * However, instrumented code can't execute without shadow memory. ++ * ++ * To keep the early shadow memory MMU tables around while setting up ++ * the proper shadow memory, we copy swapper_pg_dir (the initial page ++ * table) to tmp_pgd_table and use that to keep the early shadow memory ++ * mapped until the full shadow setup is finished. Then we swap back ++ * to the proper swapper_pg_dir. ++ */ ++ ++ memcpy(tmp_pgd_table, swapper_pg_dir, sizeof(tmp_pgd_table)); ++#ifdef CONFIG_ARM_LPAE ++ /* We need to be in the same PGD or this won't work */ ++ BUILD_BUG_ON(pgd_index(KASAN_SHADOW_START) != ++ pgd_index(KASAN_SHADOW_END)); ++ memcpy(tmp_pmd_table, ++ pgd_page_vaddr(*pgd_offset_k(KASAN_SHADOW_START)), ++ sizeof(tmp_pmd_table)); ++ set_pgd(&tmp_pgd_table[pgd_index(KASAN_SHADOW_START)], ++ __pgd(__pa(tmp_pmd_table) | PMD_TYPE_TABLE | L_PGD_SWAPPER)); ++#endif ++ cpu_switch_mm(tmp_pgd_table, &init_mm); ++ local_flush_tlb_all(); ++ ++ clear_pgds(KASAN_SHADOW_START, KASAN_SHADOW_END); ++ ++ kasan_populate_zero_shadow(kasan_mem_to_shadow((void *)VMALLOC_START), ++ kasan_mem_to_shadow((void *)-1UL) + 1); ++ ++ for_each_memblock(memory, reg) { ++ void *start = __va(reg->base); ++ void *end = __va(reg->base + reg->size); ++ ++ /* Do not attempt to shadow highmem */ ++ if (reg->base >= arm_lowmem_limit) { ++ pr_info("Skip highmem block %pap-%pap\n", ++ ®->base, ®->base + reg->size); ++ continue; ++ } ++ if (reg->base + reg->size > arm_lowmem_limit) { ++ pr_info("Truncating shadow for %pap-%pap to lowmem region\n", ++ ®->base, ®->base + reg->size); ++ end = __va(arm_lowmem_limit); ++ } ++ if (start >= end) { ++ pr_info("Skipping invalid memory block %px-%px\n", ++ start, end); ++ continue; ++ } ++ ++ create_mapping(start, end); ++ } ++ ++ /* ++ * 1. The module global variables are in MODULES_VADDR ~ MODULES_END, ++ * so we need to map this area. ++ * 2. PKMAP_BASE ~ PKMAP_BASE+PMD_SIZE's shadow and MODULES_VADDR ++ * ~ MODULES_END's shadow is in the same PMD_SIZE, so we can't ++ * use kasan_populate_zero_shadow. ++ */ ++ create_mapping((void *)MODULES_VADDR, (void *)(PKMAP_BASE + PMD_SIZE)); ++ ++ /* ++ * KAsan may reuse the contents of kasan_zero_pte directly, so ++ * we should make sure that it maps the zero page read-only. ++ */ ++ for (i = 0; i < PTRS_PER_PTE; i++) ++ set_pte_at(&init_mm, KASAN_SHADOW_START + i*PAGE_SIZE, ++ &kasan_zero_pte[i], ++ pfn_pte(virt_to_pfn(kasan_zero_page), ++ __pgprot(pgprot_val(PAGE_KERNEL) ++ | L_PTE_RDONLY))); ++ ++ cpu_switch_mm(swapper_pg_dir, &init_mm); ++ local_flush_tlb_all(); ++ ++ memset(kasan_zero_page, 0, PAGE_SIZE); ++ pr_info("Kernel address sanitizer initialized\n"); ++ init_task.kasan_depth = 0; ++} +diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c +index f7c741358f37..410c8d472bec 100644 +--- a/arch/arm/mm/mmu.c ++++ b/arch/arm/mm/mmu.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -1244,8 +1245,25 @@ static inline void prepare_page_table(void) + /* + * Clear out all the mappings below the kernel image. + */ ++#ifdef CONFIG_KASAN ++ /* ++ * KASan's shadow memory inserts itself between the TASK_SIZE ++ * and MODULES_VADDR. Do not clear the KASan shadow memory mappings. ++ */ ++ for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE) ++ pmd_clear(pmd_off_k(addr)); ++ /* ++ * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes ++ * equal to MODULES_VADDR and then we exit the pmd clearing. If we ++ * are using a thumb-compiled kernel, there there will be 8MB more ++ * to clear as KASan always offset to 16 MB below MODULES_VADDR. ++ */ ++ for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE) ++ pmd_clear(pmd_off_k(addr)); ++#else + for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) + pmd_clear(pmd_off_k(addr)); ++#endif + + #ifdef CONFIG_XIP_KERNEL + /* The XIP kernel is mapped in the module area -- skip over it */ +diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c +index c1c1a5c67da1..55faed9d990f 100644 +--- a/arch/arm/mm/pgd.c ++++ b/arch/arm/mm/pgd.c +@@ -64,7 +64,20 @@ pgd_t *pgd_alloc(struct mm_struct *mm) + new_pmd = pmd_alloc(mm, new_pud, 0); + if (!new_pmd) + goto no_pmd; +-#endif ++#ifdef CONFIG_KASAN ++ /* ++ * Copy PMD table for KASAN shadow mappings. ++ */ ++ init_pgd = pgd_offset_k(TASK_SIZE); ++ init_pud = pud_offset(init_pgd, TASK_SIZE); ++ init_pmd = pmd_offset(init_pud, TASK_SIZE); ++ new_pmd = pmd_offset(new_pud, TASK_SIZE); ++ memcpy(new_pmd, init_pmd, ++ (pmd_index(MODULES_VADDR) - pmd_index(TASK_SIZE)) ++ * sizeof(pmd_t)); ++ clean_dcache_area(new_pmd, PTRS_PER_PMD * sizeof(pmd_t)); ++#endif /* CONFIG_KASAN */ ++#endif /* CONFIG_LPAE */ + + if (!vectors_high()) { + /* +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +old mode 100644 +new mode 100755 +index d00d52c9de3e..5e94b4f6eba1 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -270,10 +270,16 @@ __v7_cr7mp_setup: + mov r10, #(1 << 0) @ Cache/TLB ops broadcasting + b 1f + __v7_ca7mp_setup: ++#ifdef CONFIG_ARCH_SSTAR ++ mrc p15, 0, r12, c1, c0, 1 ++ orr r12, r12, #(1 << 6) @ Enable SMP ++ mcr p15, 0, r12, c1, c0, 1 ++#endif + __v7_ca12mp_setup: + __v7_ca15mp_setup: + __v7_b15mp_setup: + __v7_ca17mp_setup: ++ + mov r10, #0 + 1: adr r0, __v7_setup_stack_ptr + ldr r12, [r0] +diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile +index 59a8fa7b8a3b..689dfeccecc9 100644 +--- a/arch/arm/vdso/Makefile ++++ b/arch/arm/vdso/Makefile +@@ -29,6 +29,8 @@ CFLAGS_vgettimeofday.o = -O2 + # Disable gcov profiling for VDSO code + GCOV_PROFILE := n + ++KASAN_SANITIZE := n ++ + # Force dependency + $(obj)/vdso.o : $(obj)/vdso.so + +diff --git a/arch/s390/mm/gup.c b/arch/s390/mm/gup.c +index 97fc449a7470..6593ea5ace6b 100644 +--- a/arch/s390/mm/gup.c ++++ b/arch/s390/mm/gup.c +@@ -257,8 +257,15 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, + int nr, ret; + + might_sleep(); ++ /* ++ * The FAST_GUP case requires FOLL_WRITE even for pure reads, ++ * because get_user_pages() may need to cause an early COW in ++ * order to avoid confusing the normal COW routines. So only ++ * targets that are already writable are safe to do by just ++ * looking at the page tables. ++ */ + start &= PAGE_MASK; +- nr = __get_user_pages_fast(start, nr_pages, write, pages); ++ nr = __get_user_pages_fast(start, nr_pages, 1, pages); + if (nr == nr_pages) + return nr; + +diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c +index df60b58691e7..1808c57ce161 100644 +--- a/arch/x86/events/intel/pt.c ++++ b/arch/x86/events/intel/pt.c +@@ -1117,7 +1117,7 @@ static int pt_event_addr_filters_validate(struct list_head *filters) + if (!filter->range || !filter->size) + return -EOPNOTSUPP; + +- if (!filter->inode) { ++ if (!filter->path.dentry) { + if (!valid_kernel_ip(filter->offset)) + return -EINVAL; + +@@ -1144,7 +1144,7 @@ static void pt_event_addr_filters_sync(struct perf_event *event) + return; + + list_for_each_entry(filter, &head->list, entry) { +- if (filter->inode && !offs[range]) { ++ if (filter->path.dentry && !offs[range]) { + msr_a = msr_b = 0; + } else { + /* apply the offset */ +diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h +index 5af0401ccff2..77044d2ff2b1 100644 +--- a/arch/x86/include/asm/pgtable.h ++++ b/arch/x86/include/asm/pgtable.h +@@ -188,6 +188,7 @@ static inline int pmd_large(pmd_t pte) + } + + #ifdef CONFIG_TRANSPARENT_HUGEPAGE ++/* NOTE: when predicate huge page, consider also pmd_devmap, or use pmd_large */ + static inline int pmd_trans_huge(pmd_t pmd) + { + return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; +diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c +index 1680768d392c..8fe82de3a59a 100644 +--- a/arch/x86/mm/gup.c ++++ b/arch/x86/mm/gup.c +@@ -419,7 +419,14 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, + next = pgd_addr_end(addr, end); + if (pgd_none(pgd)) + goto slow; +- if (!gup_pud_range(pgd, addr, next, write, pages, &nr)) ++ /* ++ * The FAST_GUP case requires FOLL_WRITE even for pure reads, ++ * because get_user_pages() may need to cause an early COW in ++ * order to avoid confusing the normal COW routines. So only ++ * targets that are already writable are safe to do by just ++ * looking at the page tables. ++ */ ++ if (!gup_pud_range(pgd, addr, next, 1, pages, &nr)) + goto slow; + } while (pgdp++, addr = next, addr != end); + local_irq_enable(); +diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c +index b08ccbb9393a..6cd839c1f507 100644 +--- a/block/blk-cgroup.c ++++ b/block/blk-cgroup.c +@@ -1078,10 +1078,8 @@ int blkcg_init_queue(struct request_queue *q) + if (preloaded) + radix_tree_preload_end(); + +- if (IS_ERR(blkg)) { +- blkg_free(new_blkg); ++ if (IS_ERR(blkg)) + return PTR_ERR(blkg); +- } + + q->root_blkg = blkg; + q->root_rl.blkg = blkg; +diff --git a/block/blk-core.c b/block/blk-core.c +index 23daf40be371..cf9962e8ea3e 100644 +--- a/block/blk-core.c ++++ b/block/blk-core.c +@@ -884,6 +884,7 @@ blk_init_allocated_queue(struct request_queue *q, request_fn_proc *rfn, + + fail: + blk_free_flush_queue(q->fq); ++ q->fq = NULL; + return NULL; + } + EXPORT_SYMBOL(blk_init_allocated_queue); +diff --git a/block/partitions/Kconfig b/block/partitions/Kconfig +old mode 100644 +new mode 100755 +index 9b29a996c311..16db7d730012 +--- a/block/partitions/Kconfig ++++ b/block/partitions/Kconfig +@@ -267,3 +267,11 @@ config CMDLINE_PARTITION + help + Say Y here if you want to read the partition table from bootargs. + The format for the command line is just like mtdparts. ++ ++config EMMC_PARTITION ++ bool "EMMC PARTITION table support" if PARTITION_ADVANCED ++ depends on PARTITION_ADVANCED ++ help ++ Say Y here if you would like to be able to read the hard disk ++ partition table format used by EMMC. ++ Otherwise, say N. +\ No newline at end of file +diff --git a/block/partitions/Makefile b/block/partitions/Makefile +old mode 100644 +new mode 100755 +index 37a95270503c..f154cd6cd223 +--- a/block/partitions/Makefile ++++ b/block/partitions/Makefile +@@ -20,3 +20,4 @@ obj-$(CONFIG_IBM_PARTITION) += ibm.o + obj-$(CONFIG_EFI_PARTITION) += efi.o + obj-$(CONFIG_KARMA_PARTITION) += karma.o + obj-$(CONFIG_SYSV68_PARTITION) += sysv68.o ++obj-$(CONFIG_EMMC_PARTITION) += emmc.o +\ No newline at end of file +diff --git a/block/partitions/check.c b/block/partitions/check.c +old mode 100644 +new mode 100755 +index 16118d11dbfc..d0a2b3d396bd +--- a/block/partitions/check.c ++++ b/block/partitions/check.c +@@ -35,6 +35,8 @@ + #include "karma.h" + #include "sysv68.h" + #include "cmdline.h" ++#include "emmc.h" ++ + + int warn_no_part = 1; /*This is ugly: should make genhd removable media aware*/ + +@@ -108,6 +110,10 @@ static int (*check_part[])(struct parsed_partitions *) = { + #ifdef CONFIG_SYSV68_PARTITION + sysv68_partition, + #endif ++#if defined (CONFIG_EMMC_PARTITION) ++ emmc_partition, ++#endif ++ + NULL + }; + +diff --git a/block/partitions/emmc.c b/block/partitions/emmc.c +new file mode 100755 +index 000000000000..a2db0356d79d +--- /dev/null ++++ b/block/partitions/emmc.c +@@ -0,0 +1,76 @@ ++/* ++ * fs/partitions/emmc.c ++ * ++ * Code extracted from drivers/block/genhd.c ++ * Copyright (C) 1991-1998 Linus Torvalds ++ * Re-organised Feb 1998 Russell King ++ */ ++ ++#include ++#include "check.h" ++#include "emmc.h" ++ ++int emmc_partition(struct parsed_partitions *state) ++{ ++ int slot = 1; ++ Sector sect; ++ unsigned char *data; ++ int blk, blocks_in_map; ++ unsigned secsize; ++ struct emmc_partition *part; ++ struct emmc_driver_desc *md; ++ printk("emmc_partition()\n"); ++ /* Get 0th block and look at the first partition map entry. */ ++ md = read_part_sector(state, 0, §); ++ if (!md) ++ return -1; ++ ++ if (md->signature != EMMC_DRIVER_MAGIC) { ++ //can not found the partiton map! ++ printk("0x%x\n",md->signature); ++ put_dev_sector(sect); ++ return 0; ++ } ++ ++ if(md->version == EMMC_PARTITIONTABLE_VERSION2 || md->version == EMMC_PARTITIONTABLE_VERSION3) ++ blocks_in_map = md->drvr_cnt; ++ else ++ blocks_in_map = EMMC_RESERVED_FOR_MAP; ++ ++// secsize = be16_to_cpu(md->block_size); ++ secsize = 512; ++ put_dev_sector(sect); ++ data = read_part_sector(state, secsize/512, §); ++ if (!data) ++ return -1; ++ part = (struct emmc_partition *) (data + secsize%512); ++ if (part->signature != EMMC_PARTITION_MAGIC) { ++ put_dev_sector(sect); ++ return 0; /* not a emmc disk */ ++ } ++ printk(" [emmc]"); ++ for (blk = 1; blk <= blocks_in_map; ++blk) { ++ int pos = blk * secsize; ++ put_dev_sector(sect); ++ data = read_part_sector(state, pos/512, §); ++ if (!data) ++ return -1; ++ part = (struct emmc_partition *) (data + pos%512); ++ if (part->signature != EMMC_PARTITION_MAGIC) ++ break; ++ printk("Start_block=%d, block_count=%d\n",part->start_block,part->block_count); ++ put_partition(state, slot, ++ (part->start_block) * (secsize/512), ++ (part->block_count) * (secsize/512)); ++ strcpy(state->parts[slot].info.volname, part->name); /* put parsed partition name into state */ ++ ++ if (!strncasecmp(part->type, "Linux_RAID", 10)) ++ state->parts[slot].flags = ADDPART_FLAG_RAID; ++ ++ ++slot; ++ } ++ ++ put_dev_sector(sect); ++ printk("\n"); ++ return 1; ++} +diff --git a/block/partitions/emmc.h b/block/partitions/emmc.h +new file mode 100755 +index 000000000000..a9aa933f94cb +--- /dev/null ++++ b/block/partitions/emmc.h +@@ -0,0 +1,53 @@ ++/* ++ * fs/partitions/emmc.h ++ */ ++ ++#define EMMC_PARTITION_MAGIC 0x5840 ++#define EMMC_RESERVED_FOR_MAP 64 //keep the same with uboot ++ ++/* type field value for A/UX or other Unix partitions */ ++//#define APPLE_AUX_TYPE "Apple_UNIX_SVR2" ++ ++struct emmc_partition { ++ __be16 signature; /* expected to be MAC_PARTITION_MAGIC */ ++ __be16 res1; ++ __be32 map_count; /* # blocks in partition map */ ++ __be32 start_block; /* absolute starting block # of partition */ ++ __be32 block_count; /* number of blocks in partition */ ++ char name[32]; /* partition name */ ++ char type[32]; /* string type description */ ++ __be32 data_start; /* rel block # of first data block */ ++ __be32 data_count; /* number of data blocks */ ++ __be32 status; /* partition status bits */ ++ __be32 boot_start; ++ __be32 boot_size; ++ __be32 boot_load; ++ __be32 boot_load2; ++ __be32 boot_entry; ++ __be32 boot_entry2; ++ __be32 boot_cksum; ++ char processor[16]; /* identifies ISA of boot */ ++ /* there is more stuff after this that we don't need */ ++}; ++ ++#define EMMC_STATUS_BOOTABLE 8 /* partition is bootable */ ++ ++#define EMMC_DRIVER_MAGIC 0x1630 ++#define EMMC_PARTITIONTABLE_VERSION2 0x2000 ++#define EMMC_PARTITIONTABLE_VERSION3 0x4000 ++ ++ ++/* Driver descriptor structure, in block 0 */ ++struct emmc_driver_desc { ++ __be16 signature; /* expected to be EMMC_DRIVER_MAGIC */ ++ __be16 block_size; /* block size of device */ ++ __be32 block_count; /* number of blocks on device */ ++ __be16 dev_type; /* device type */ ++ __be16 dev_id; /* device id */ ++ __be32 data; /* reserved */ ++ __be16 version; /* version number of partition table */ ++ __be16 drvr_cnt; /* number of blocks reserved for partition table */ ++ /* ... more stuff */ ++}; ++ ++int emmc_partition(struct parsed_partitions *state); +diff --git a/crypto/algboss.c b/crypto/algboss.c +old mode 100644 +new mode 100755 +index 6e39d9c05b98..4c523003c171 +--- a/crypto/algboss.c ++++ b/crypto/algboss.c +@@ -235,7 +235,10 @@ static int cryptomgr_schedule_test(struct crypto_alg *alg) + struct task_struct *thread; + struct crypto_test_param *param; + u32 type; +- ++#ifdef CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD ++ crypto_alg_tested(alg->cra_driver_name, 0); ++ return NOTIFY_STOP; ++#endif + if (!try_module_get(THIS_MODULE)) + goto err; + +@@ -247,13 +250,11 @@ static int cryptomgr_schedule_test(struct crypto_alg *alg) + memcpy(param->alg, alg->cra_name, sizeof(param->alg)); + type = alg->cra_flags; + +- /* This piece of crap needs to disappear into per-type test hooks. */ +- if (!((type ^ CRYPTO_ALG_TYPE_BLKCIPHER) & +- CRYPTO_ALG_TYPE_BLKCIPHER_MASK) && !(type & CRYPTO_ALG_GENIV) && +- ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == +- CRYPTO_ALG_TYPE_BLKCIPHER ? alg->cra_blkcipher.ivsize : +- alg->cra_ablkcipher.ivsize)) +- type |= CRYPTO_ALG_TESTED; ++ /* Do not test internal algorithms. */ ++ if (type & CRYPTO_ALG_INTERNAL) ++ { ++ type |= CRYPTO_ALG_TESTED; ++ } + + param->type = type; + +diff --git a/crypto/crypto_user.c b/crypto/crypto_user.c +index 1c5705481c69..260eb8369be1 100644 +--- a/crypto/crypto_user.c ++++ b/crypto/crypto_user.c +@@ -266,8 +266,10 @@ static int crypto_report(struct sk_buff *in_skb, struct nlmsghdr *in_nlh, + drop_alg: + crypto_mod_put(alg); + +- if (err) ++ if (err) { ++ kfree_skb(skb); + return err; ++ } + + return nlmsg_unicast(crypto_nlsk, skb, NETLINK_CB(in_skb).portid); + } +diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c +old mode 100644 +new mode 100755 +index 2a07341aca46..4dde4ef80a98 +--- a/crypto/tcrypt.c ++++ b/crypto/tcrypt.c +@@ -548,8 +548,13 @@ static int test_ahash_jiffies_digest(struct ahash_request *req, int blen, + return ret; + } + ++#ifdef CONFIG_ARCH_SSTAR ++ printk("%6u opers/sec, %3lu.%03lu MBytes/sec\n", ++ bcount / secs, ((long)bcount * blen) / secs/1024/1024, ((((long)bcount * blen) / secs)%1048576)*1000/1048576); ++#else + printk("%6u opers/sec, %9lu bytes/sec\n", + bcount / secs, ((long)bcount * blen) / secs); ++#endif + + return 0; + } +@@ -580,8 +585,13 @@ static int test_ahash_jiffies(struct ahash_request *req, int blen, + return ret; + } + ++#ifdef CONFIG_ARCH_SSTAR ++ pr_cont("%6u opers/sec, %3lu.%03lu MBytes/sec\n", ++ bcount / secs, ((long)bcount * blen) / secs/1024/1024, ((((long)bcount * blen) / secs)%1048576)*1000/1048576); ++#else + pr_cont("%6u opers/sec, %9lu bytes/sec\n", + bcount / secs, ((long)bcount * blen) / secs); ++#endif + + return 0; + } +@@ -801,9 +811,20 @@ static int test_acipher_jiffies(struct skcipher_request *req, int enc, + if (ret) + return ret; + } +- ++#ifdef CONFIG_ARCH_SSTAR ++ { ++ u64 throughput_int,throughput_decimal, rem; ++ throughput_int = bcount * blen; ++ rem = do_div(throughput_int, secs*1024*1024 ); ++ throughput_decimal = rem * 1000; ++ rem = do_div(throughput_decimal, secs*1024*1024 ); ++ pr_cont("%8d operations in %d seconds (%3lld.%03lld Mps)\n", ++ bcount, secs, throughput_int, throughput_decimal); ++ } ++#else + pr_cont("%d operations in %d seconds (%ld bytes)\n", + bcount, secs, (long)bcount * blen); ++#endif + return 0; + } + +@@ -909,7 +930,7 @@ static void test_skcipher_speed(const char *algo, int enc, unsigned int secs, + goto out_free_req; + } + +- pr_info("test %u (%d bit key, %d byte blocks): ", i, ++ pr_info("test %2u (%d bit key, %4d byte blocks): ", i, + *keysize * 8, *b_size); + + memset(tvmem[0], 0xff, PAGE_SIZE); +diff --git a/drivers/Kconfig b/drivers/Kconfig +old mode 100644 +new mode 100755 +index e1e2066cecdb..07a1aa85f040 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -188,6 +188,8 @@ source "drivers/ras/Kconfig" + + source "drivers/thunderbolt/Kconfig" + ++source "drivers/tty/Kconfig" ++ + source "drivers/android/Kconfig" + + source "drivers/nvdimm/Kconfig" +@@ -202,4 +204,5 @@ source "drivers/hwtracing/intel_th/Kconfig" + + source "drivers/fpga/Kconfig" + ++source "drivers/sstar/Kconfig" + endmenu +diff --git a/drivers/Makefile b/drivers/Makefile +old mode 100644 +new mode 100755 +index 7c3d58dcf6b3..ca6351e74be6 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -175,3 +175,4 @@ obj-$(CONFIG_STM) += hwtracing/stm/ + obj-$(CONFIG_ANDROID) += android/ + obj-$(CONFIG_NVMEM) += nvmem/ + obj-$(CONFIG_FPGA) += fpga/ ++obj-$(CONFIG_MSTAR_DRIVERS) += sstar/ +\ No newline at end of file +diff --git a/drivers/android/binder.c b/drivers/android/binder.c +index 3b6ac80b2127..a874747d4b97 100644 +--- a/drivers/android/binder.c ++++ b/drivers/android/binder.c +@@ -569,6 +569,12 @@ static int binder_update_page_range(struct binder_proc *proc, int allocate, + + if (mm) { + down_write(&mm->mmap_sem); ++ if (!mmget_still_valid(mm)) { ++ if (allocate == 0) ++ goto free_range; ++ goto err_no_vma; ++ } ++ + vma = proc->vma; + if (vma && mm != proc->vma_vm_mm) { + pr_err("%d: vma mm and task mm mismatch\n", +diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h +old mode 100644 +new mode 100755 +index 0cc08f892fea..62e4e6331d89 +--- a/drivers/ata/ahci.h ++++ b/drivers/ata/ahci.h +@@ -52,6 +52,7 @@ + #define EM_MSG_LED_VALUE_OFF 0xfff80000 + #define EM_MSG_LED_VALUE_ON 0x00010000 + ++#if !defined(CONFIG_ARCH_INFINITY2) + enum { + AHCI_MAX_PORTS = 32, + AHCI_MAX_CLKS = 5, +@@ -279,6 +280,236 @@ enum { + EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ + }; + ++#else ++enum { ++ AHCI_MAX_PORTS = 32, ++ AHCI_MAX_CLKS = 5, ++ AHCI_MAX_SG = 168, /* hardware max is 64K */ ++ AHCI_DMA_BOUNDARY = 0xffffffff, ++ AHCI_MAX_CMDS = 32, ++ AHCI_CMD_SZ = 32, ++ AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, /*32 * 32 */ ++ AHCI_RX_FIS_SZ = 256, ++ AHCI_CMD_TBL_CDB = 0x40, ++ AHCI_CMD_TBL_HDR_SZ = 0x80, ++ AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), ++ AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, ++ AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ/*1024*/ + AHCI_CMD_TBL_AR_SZ/*2816*/ + ++ AHCI_RX_FIS_SZ/*256*/, ++ AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + ++ AHCI_CMD_TBL_AR_SZ + ++ (AHCI_RX_FIS_SZ * 16), ++ AHCI_IRQ_ON_SG = (1 << 31), ++ AHCI_CMD_ATAPI = (1 << 5), ++ AHCI_CMD_WRITE = (1 << 6), ++ AHCI_CMD_PREFETCH = (1 << 7), ++ AHCI_CMD_RESET = (1 << 8), ++ AHCI_CMD_CLR_BUSY = (1 << 10), ++ ++ RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ ++ RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ ++ RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ ++ RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ ++ ++ /* global controller registers */ ++ HOST_CAP = 0x00, /* host capabilities */ ++ HOST_CTL = (0x04 << 1), /* global host control */ ++ HOST_IRQ_STAT = (0x08 << 1), /* interrupt status */ ++ HOST_PORTS_IMPL = (0x0c << 1), /* bitmap of implemented ports */ ++ HOST_VERSION = (0x10 << 1), /* AHCI spec. version compliancy */ ++ HOST_EM_LOC = (0x1c << 1), /* Enclosure Management location */ ++ HOST_EM_CTL = (0x20 << 1), /* Enclosure Management Control */ ++ HOST_CAP2 = (0x24 << 1), /* host capabilities, extended */ ++ ++ /* HOST_CTL bits */ ++ HOST_RESET = ((1 << 0)), /* reset controller; self-clear */ ++ HOST_IRQ_EN = ((1 << 1)), /* global IRQ enable */ ++ HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ ++ HOST_AHCI_EN = ((1 << 31)), /* AHCI enabled */ ++ ++ /* HOST_CAP bits */ ++ HOST_CAP_SXS = ((1 << 5)), /* Supports External SATA */ ++ HOST_CAP_EMS = ((1 << 6)), /* Enclosure Management support */ ++ HOST_CAP_CCC = ((1 << 7)), /* Command Completion Coalescing */ ++ HOST_CAP_PART = ((1 << 13)), /* Partial state capable */ ++ HOST_CAP_SSC = ((1 << 14)), /* Slumber state capable */ ++ HOST_CAP_PIO_MULTI = ((1 << 15)), /* PIO multiple DRQ support */ ++ HOST_CAP_FBS = ((1 << 16)), /* FIS-based switching support */ ++ HOST_CAP_PMP = ((1 << 17)), /* Port Multiplier support */ ++ HOST_CAP_ONLY = ((1 << 18)), /* Supports AHCI mode only */ ++ HOST_CAP_CLO = ((1 << 24)), /* Command List Override support */ ++ HOST_CAP_LED = ((1 << 25)), /* Supports activity LED */ ++ HOST_CAP_ALPM = ((1 << 26)), /* Aggressive Link PM support */ ++ HOST_CAP_SSS = ((1 << 27)), /* Staggered Spin-up */ ++ HOST_CAP_MPS = ((1 << 28)), /* Mechanical presence switch */ ++ HOST_CAP_SNTF = ((1 << 29)), /* SNotification register */ ++ HOST_CAP_NCQ = ((1 << 30)), /* Native Command Queueing */ ++ HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ ++ ++ ++ /* HOST_CAP2 bits */ ++ HOST_CAP2_BOH = ((1 << 0)), /* BIOS/OS handoff supported */ ++ HOST_CAP2_NVMHCI = ((1 << 1)), /* NVMHCI supported */ ++ HOST_CAP2_APST = ((1 << 2)), /* Automatic partial to slumber */ ++ HOST_CAP2_SDS = ((1 << 3)), /* Support device sleep */ ++ HOST_CAP2_SADM = ((1 << 4)), /* Support aggressive DevSlp */ ++ HOST_CAP2_DESO = ((1 << 5)), /* DevSlp from slumber only */ ++ ++ /* registers for each SATA port */ ++ PORT_LST_ADDR = (0x00 << 1), /* command list DMA addr */ ++ PORT_LST_ADDR_HI = (0x04 << 1), /* command list DMA addr hi */ ++ PORT_FIS_ADDR = (0x08 << 1), /* FIS rx buf addr */ ++ PORT_FIS_ADDR_HI = (0x0c << 1), /* FIS rx buf addr hi */ ++ PORT_IRQ_STAT = (0x10 << 1), /* interrupt status */ ++ PORT_IRQ_MASK = (0x14 << 1), /* interrupt enable/disable mask */ ++ PORT_CMD = (0x18 << 1), /* port command */ ++ PORT_TFDATA = (0x20 << 1), /* taskfile data */ ++ PORT_CMD_ESP = (1 << 21), /* External Sata Port */ ++ PORT_SIG = (0x24 << 1), /* device TF signature */ ++ PORT_CMD_ISSUE = (0x38 << 1), /* command issue */ ++ PORT_SCR_STAT = (0x28 << 1), /* SATA phy register: SStatus */ ++ PORT_SCR_CTL = (0x2c << 1), /* SATA phy register: SControl */ ++ PORT_SCR_ERR = (0x30 << 1), /* SATA phy register: SError */ ++ PORT_SCR_ACT = (0x34 << 1), /* SATA phy register: SActive */ ++ PORT_SCR_NTF = (0x3c << 1), /* SATA phy register: SNotification */ ++ PORT_FBS = (0x40 <<1), /* FIS-based Switching */ ++ PORT_DEVSLP = (0x44 <<1), /* device sleep */ ++ ++ /* PORT_IRQ_{STAT,MASK} bits */ ++ PORT_IRQ_COLD_PRES = ((1 << 31)), /* cold presence detect */ ++ PORT_IRQ_TF_ERR = ((1 << 30)), /* task file error */ ++ PORT_IRQ_HBUS_ERR = ((1 << 29)), /* host bus fatal error */ ++ PORT_IRQ_HBUS_DATA_ERR = ((1 << 28)), /* host bus data error */ ++ PORT_IRQ_IF_ERR = ((1 << 27)), /* interface fatal error */ ++ PORT_IRQ_IF_NONFATAL = ((1 << 26)), /* interface non-fatal error */ ++ PORT_IRQ_OVERFLOW = ((1 << 24)), /* xfer exhausted available S/G */ ++ PORT_IRQ_BAD_PMP = ((1 << 23)), /* incorrect port multiplier */ ++ ++ PORT_IRQ_PHYRDY = ((1 << 22)), /* PhyRdy changed */ ++ PORT_IRQ_DEV_ILCK = ((1 << 7)), /* device interlock */ ++ PORT_IRQ_CONNECT = ((1 << 6)), /* port connect change status */ ++ PORT_IRQ_SG_DONE = ((1 << 5)), /* descriptor processed */ ++ PORT_IRQ_UNK_FIS = ((1 << 4)), /* unknown FIS rx'd */ ++ PORT_IRQ_SDB_FIS = ((1 << 3)), /* Set Device Bits FIS rx'd */ ++ PORT_IRQ_DMAS_FIS = ((1 << 2)), /* DMA Setup FIS rx'd */ ++ PORT_IRQ_PIOS_FIS = ((1 << 1)), /* PIO Setup FIS rx'd */ ++ PORT_IRQ_D2H_REG_FIS = ((1 << 0)), /* D2H Register FIS rx'd */ ++ ++ PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | ++ PORT_IRQ_IF_ERR | ++ PORT_IRQ_CONNECT | ++ PORT_IRQ_PHYRDY | ++ PORT_IRQ_UNK_FIS | ++ PORT_IRQ_BAD_PMP, ++ PORT_IRQ_ERROR = PORT_IRQ_FREEZE | ++ PORT_IRQ_TF_ERR | ++ PORT_IRQ_HBUS_DATA_ERR, ++ DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | ++ PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | ++ PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, ++ ++ /* PORT_CMD bits */ ++ PORT_CMD_ASP = ((1 << 27)), /* Aggressive Slumber/Partial */ ++ PORT_CMD_ALPE = ((1 << 26)), /* Aggressive Link PM enable */ ++ PORT_CMD_ATAPI = ((1 << 24)), /* Device is ATAPI */ ++ PORT_CMD_FBSCP = ((1 << 22)), /* FBS Capable Port */ ++ PORT_CMD_PMP = ((1 << 17)), /* PMP attached */ ++ PORT_CMD_LIST_ON = ((1 << 15)), /* cmd list DMA engine running */ ++ PORT_CMD_FIS_ON = ((1 << 14)), /* FIS DMA engine running */ ++ PORT_CMD_FIS_RX = ((1 << 4)), /* Enable FIS receive DMA engine */ ++ PORT_CMD_CLO = ((1 << 3)), /* Command list override */ ++ PORT_CMD_POWER_ON = ((1 << 2)), /* Power up device */ ++ PORT_CMD_SPIN_UP = ((1 << 1)), /* Spin up device */ ++ PORT_CMD_START = ((1 << 0)), /* Enable port DMA engine */ ++ ++ PORT_CMD_ICC_MASK = ((0xf << 28)), /* i/f ICC state mask */ ++ PORT_CMD_ICC_ACTIVE = ((0x1 << 28)), /* Put i/f in active state */ ++ PORT_CMD_ICC_PARTIAL = ((0x2 << 28)), /* Put i/f in partial state */ ++ PORT_CMD_ICC_SLUMBER = ((0x6 << 28)), /* Put i/f in slumber state */ ++ ++ /* PORT_FBS bits */ ++ PORT_FBS_DWE_OFFSET = (16), /* FBS device with error offset */ ++ PORT_FBS_ADO_OFFSET = (12), /* FBS active dev optimization offset */ ++ PORT_FBS_DEV_OFFSET = (8), /* FBS device to issue offset */ ++ PORT_FBS_DEV_MASK = ((0xf << PORT_FBS_DEV_OFFSET)), /* FBS.DEV */ ++ PORT_FBS_SDE = ((1 << 2)), /* FBS single device error */ ++ PORT_FBS_DEC = ((1 << 1)), /* FBS device error clear */ ++ PORT_FBS_EN = ((1 << 0)), /* Enable FBS */ ++ ++ /* PORT_DEVSLP bits */ ++ PORT_DEVSLP_DM_OFFSET = (25), /* DITO multiplier offset */ ++ PORT_DEVSLP_DM_MASK = ((0xf << 25)), /* DITO multiplier mask */ ++ PORT_DEVSLP_DITO_OFFSET = (15), /* DITO offset */ ++ PORT_DEVSLP_MDAT_OFFSET = (10), /* Minimum assertion time */ ++ PORT_DEVSLP_DETO_OFFSET = (2), /* DevSlp exit timeout */ ++ PORT_DEVSLP_DSP = ((1 << 1)), /* DevSlp present */ ++ PORT_DEVSLP_ADSE = ((1 << 0)), /* Aggressive DevSlp enable */ ++ ++ /* hpriv->flags bits */ ++ ++#define AHCI_HFLAGS(flags) .private_data = (void *)(flags) ++ ++ AHCI_HFLAG_NO_NCQ = ((1 << 0)), ++ AHCI_HFLAG_IGN_IRQ_IF_ERR = ((1 << 1)), /* ignore IRQ_IF_ERR */ ++ AHCI_HFLAG_IGN_SERR_INTERNAL = ((1 << 2)), /* ignore SERR_INTERNAL */ ++ AHCI_HFLAG_32BIT_ONLY = ((1 << 3)), /* force 32bit */ ++ AHCI_HFLAG_MV_PATA = ((1 << 4)), /* PATA port */ ++ AHCI_HFLAG_NO_MSI = ((1 << 5)), /* no PCI MSI */ ++ AHCI_HFLAG_NO_PMP = ((1 << 6)), /* no PMP */ ++ AHCI_HFLAG_SECT255 = ((1 << 8)), /* max 255 sectors */ ++ AHCI_HFLAG_YES_NCQ = ((1 << 9)), /* force NCQ cap on */ ++ AHCI_HFLAG_NO_SUSPEND = ((1 << 10)), /* don't suspend */ ++ AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = ((1 << 11)), /* treat SRST timeout as ++ link offline */ ++ AHCI_HFLAG_NO_SNTF = ((1 << 12)), /* no sntf */ ++ AHCI_HFLAG_NO_FPDMA_AA = ((1 << 13)), /* no FPDMA AA */ ++ AHCI_HFLAG_YES_FBS = ((1 << 14)), /* force FBS cap on */ ++ AHCI_HFLAG_DELAY_ENGINE = ((1 << 15)), /* do not start engine on ++ port start (wait until ++ error-handling stage) */ ++ AHCI_HFLAG_MULTI_MSI = ((1 << 16)), /* multiple PCI MSIs */ ++ AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ ++ AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ ++ ++ /* ap->flags bits */ ++ AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ++ ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, ++ #ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ SATA_KA9_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ++ ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | ATA_FLAG_NCQ, ++ ++ SATA_SSTAR_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ++ ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | ATA_FLAG_NCQ, ++#endif ++ ICH_MAP = 0x90, /* ICH MAP register */ ++ ++ AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */ ++ ++ /* em constants */ ++ EM_MAX_SLOTS = 8, ++ EM_MAX_RETRY = 5, ++ ++ /* em_ctl bits */ ++ EM_CTL_RST = ((1 << 9)), /* Reset */ ++ EM_CTL_TM = ((1 << 8)), /* Transmit Message */ ++ EM_CTL_MR = ((1 << 0)), /* Message Received */ ++ EM_CTL_ALHD = ((1 << 26)), /* Activity LED */ ++ EM_CTL_XMT = ((1 << 25)), /* Transmit Only */ ++ EM_CTL_SMB = ((1 << 24)), /* Single Message Buffer */ ++ EM_CTL_SGPIO = ((1 << 19)), /* SGPIO messages supported */ ++ EM_CTL_SES = ((1 << 18)), /* SES-2 messages supported */ ++ EM_CTL_SAFTE = ((1 << 17)), /* SAF-TE messages supported */ ++ EM_CTL_LED = ((1 << 16)), /* LED messages supported */ ++ ++ /* em message type */ ++ EM_MSG_TYPE_LED = ((1 << 0)), /* LED */ ++ EM_MSG_TYPE_SAFTE = ((1 << 1)), /* SAF-TE */ ++ EM_MSG_TYPE_SES2 = ((1 << 2)), /* SES-2 */ ++ EM_MSG_TYPE_SGPIO = ((1 << 3)), /* SGPIO */ ++}; ++#endif ++//Command Header ++ + struct ahci_cmd_hdr { + __le32 opts; + __le32 status; +@@ -352,6 +583,7 @@ struct ahci_host_priv { + unsigned nports; /* Number of ports */ + void *plat_data; /* Other platform data */ + unsigned int irq; /* interrupt line */ ++ unsigned int bFirstOOB; + /* + * Optional ahci_start_engine override, if not set this gets set to the + * default ahci_start_engine during ahci_save_initial_config, this can +@@ -363,6 +595,9 @@ struct ahci_host_priv { + /* only required for per-port MSI(-X) support */ + int (*get_irq_vector)(struct ata_host *host, + int port); ++ #ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ int phy_mode ; ++ #endif + }; + + extern int ahci_ignore_sss; +@@ -419,7 +654,11 @@ static inline void __iomem *__ahci_port_base(struct ata_host *host, + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *mmio = hpriv->mmio; + ++#if defined(CONFIG_ARCH_INFINITY2) ++ return mmio + 0x200 + (port_no * 0x80);//0x100 ++#else + return mmio + 0x100 + (port_no * 0x80); ++#endif + } + + static inline void __iomem *ahci_port_base(struct ata_port *ap) +diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c +old mode 100644 +new mode 100755 +diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c +old mode 100644 +new mode 100755 +index 0d028ead99e8..05bda0f08f7d +--- a/drivers/ata/libahci.c ++++ b/drivers/ata/libahci.c +@@ -47,6 +47,22 @@ + #include "ahci.h" + #include "libata.h" + ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++#endif ++ ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++extern void Chip_Flush_MIU_Pipe(void); // avoid to modify driver\ata\makefile ++#endif ++ + static int ahci_skip_host_reset; + int ahci_ignore_sss; + EXPORT_SYMBOL_GPL(ahci_ignore_sss); +@@ -200,6 +216,38 @@ static int devslp_idle_timeout __read_mostly = 1000; + module_param(devslp_idle_timeout, int, 0644); + MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); + ++#if defined(CONFIG_ARCH_INFINITY2) ++u32 ahci_reg_read(void __iomem * p_reg_addr) ++{ ++ u32 data; ++ phys_addr_t reg_addr = (phys_addr_t)p_reg_addr; ++ ++#if defined(CONFIG_ARM64) ++ data = (readw(reg_addr + 0x04) << 16) + readw(reg_addr); ++#else ++ data = (ioread16((void __iomem *)(reg_addr + 0x04))<<16) + ioread16((void __iomem *)reg_addr); ++#endif ++ return data; ++} ++EXPORT_SYMBOL(ahci_reg_read); ++ ++void ahci_reg_write(u32 data, void __iomem * p_reg_addr) ++{ ++ phys_addr_t reg_addr = (phys_addr_t)p_reg_addr; ++ ++#if defined(CONFIG_ARM64) ++ writew(data & 0xFFFF, reg_addr); ++ writew((data >> 16) & 0xFFFF, (reg_addr + 0x04)); ++ ++#else ++ iowrite16(data&0xFFFF, (void __iomem *)reg_addr); ++ iowrite16((data >> 16)&0xFFFF,(void __iomem *)(reg_addr + 0x04)); ++#endif ++} ++EXPORT_SYMBOL(ahci_reg_write); ++ ++#endif ++ + static void ahci_enable_ahci(void __iomem *mmio) + { + int i; +@@ -1280,6 +1328,9 @@ void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, + pp->cmd_slot[tag].status = 0; + pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); + pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ Chip_Flush_MIU_Pipe(); ++#endif + } + EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); + +@@ -1718,6 +1769,9 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) + * link. There's no active qc on NCQ errors. It will + * be determined by EH by reading log page 10h. + */ ++#if defined(CONFIG_ARCH_INFINITY2) ++ printk("TF_ERR\n"); ++#endif + if (active_qc) + active_qc->err_mask |= AC_ERR_DEV; + else +@@ -1770,7 +1824,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) + /* okay, let's hand over to EH */ + + if (irq_stat & PORT_IRQ_FREEZE) +- ata_port_freeze(ap); ++ ata_port_freeze(ap); // for pmp clues + else if (fbs_need_dec) { + ata_link_abort(link); + ahci_fbs_dec_intr(ap); +@@ -1799,7 +1853,7 @@ static void ahci_handle_port_interrupt(struct ata_port *ap, + + if (unlikely(status & PORT_IRQ_ERROR)) { + ahci_error_intr(ap, status); +- return; ++ return;// for pmp clues + } + + if (status & PORT_IRQ_SDB_FIS) { +diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c +old mode 100644 +new mode 100755 +diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c +old mode 100644 +new mode 100755 +index aee39524375c..74dc16872276 +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -78,6 +78,8 @@ + + #include "libata.h" + #include "libata-transport.h" ++#include "ahci.h" ++#include + + /* debounce timing parameters in msecs { interval, duration, timeout } */ + const unsigned long sata_deb_timing_normal[] = { 5, 100, 2000 }; +@@ -177,6 +179,44 @@ MODULE_LICENSE("GPL"); + MODULE_VERSION(DRV_VERSION); + + ++#ifdef CONFIG_ARCH_INFINITY2M ++ ++#define SATA_GHC_0 0x1A2800 ++#define SATA_GHC_0_PHY_ANA 0x152700 ++#define REG_SATA_PHYA_REG_50 (SATA_GHC_0_PHY_ANA + (0x50<<1)) ++#define SSTAR_SATA_PHY_OFFSET ((SATA_GHC_0-SATA_GHC_0_PHY_ANA )<<1) ++#define REG_SATA_OFFSET_PHYA_REG_50 (0x50<<2) ++ ++int ahci_port_phy_fsm_reset(struct ata_link *link) ++{ ++ u16 u16Temp =0; ++ struct ata_host *host = link->ap->host; ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++ uintptr_t mmio = (uintptr_t)hpriv->mmio; ++ ++ if((hpriv->phy_mode == 0) || (hpriv->phy_mode == 1)) ++ { ++ //printk("%s , mmio = 0x%p \n", __func__ , hpriv->mmio ); ++ ++ //*** Bank 0x1527 h0050 bit15 => 0x0 ++ u16Temp = readw((volatile void *)(mmio - SSTAR_SATA_PHY_OFFSET + REG_SATA_OFFSET_PHYA_REG_50 ) ); ++ u16Temp = u16Temp & ( ~(0x01<<15)); ++ writew(u16Temp, (volatile void *)(mmio - SSTAR_SATA_PHY_OFFSET + REG_SATA_OFFSET_PHYA_REG_50 ) ); ++ ++ ndelay(1000); ++ ++ //*** Bank 0x1527 h0050 bit15 => 0x1 ++ u16Temp = readw((volatile void *)(mmio - SSTAR_SATA_PHY_OFFSET + REG_SATA_OFFSET_PHYA_REG_50 ) ); ++ u16Temp = u16Temp | (0x01<<15); ++ writew(u16Temp, (volatile void *)(mmio - SSTAR_SATA_PHY_OFFSET + REG_SATA_OFFSET_PHYA_REG_50 ) ); ++ } ++ ++ return 0; ++} ++ ++#endif ++ + static bool ata_sstatus_online(u32 sstatus) + { + return (sstatus & 0xf) == 0x3; +@@ -3943,6 +3983,8 @@ int ata_std_prereset(struct ata_link *link, unsigned long deadline) + * RETURNS: + * 0 on success, -errno otherwise. + */ ++ ++#ifndef CONFIG_ARCH_INFINITY2M + int sata_link_hardreset(struct ata_link *link, const unsigned long *timing, + unsigned long deadline, + bool *online, int (*check_ready)(struct ata_link *)) +@@ -4031,6 +4073,127 @@ int sata_link_hardreset(struct ata_link *link, const unsigned long *timing, + return rc; + } + ++#else ++int sata_link_hardreset(struct ata_link *link, const unsigned long *timing, ++ unsigned long deadline, ++ bool *online, int (*check_ready)(struct ata_link *)) ++{ ++ u32 scontrol; ++ int rc; ++ struct ata_host *host = link->ap->host; ++ struct ahci_host_priv *hpriv = host->private_data; ++ int resetAgain = 1; ++ ++DO_AGAIN: ++ ++ DPRINTK("ENTER\n"); ++ ++ if (online) ++ *online = false; ++ ++ //printk("%s , hpriv->bFirstOOB = %d \n", __func__ , hpriv->bFirstOOB ); ++ ++ if (sata_set_spd_needed(link)) { ++ /* SATA spec says nothing about how to reconfigure ++ * spd. To be on the safe side, turn off phy during ++ * reconfiguration. This works for at least ICH7 AHCI ++ * and Sil3124. ++ */ ++ if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol))) ++ goto out; ++ ++ scontrol = (scontrol & 0x0f0) | 0x304; ++ ++ if ((rc = sata_scr_write(link, SCR_CONTROL, scontrol))) ++ goto out; ++ ++ sata_set_spd(link); ++ //printk("%s , sata_set_spd \n", __func__ ); ++ } ++ ++ ++#ifdef CONFIG_ARCH_INFINITY2M ++ if(ata_is_host_link(link) && ((hpriv->bFirstOOB == 0) || (hpriv->phy_mode > 0)) ) ++ { ++ ahci_port_phy_fsm_reset(link); ++ } ++#endif ++ ++ if( (0 == hpriv->bFirstOOB) || (hpriv->phy_mode > 0)) ++ { ++ //printk("%s , 2nd OOB \n", __func__ ); ++ /* issue phy wake/reset */ ++ if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol))) ++ goto out; ++ ++ scontrol = (scontrol & 0x0f0) | 0x301; ++ ++ if ((rc = sata_scr_write_flush(link, SCR_CONTROL, scontrol))) ++ goto out; ++ } ++ else if(hpriv->phy_mode == 0) ++ { ++ hpriv->bFirstOOB = 0 ; ++ } ++ ++ /* Couldn't find anything in SATA I/II specs, but AHCI-1.1 ++ * 10.4.2 says at least 1 ms. ++ */ ++ ata_msleep(link->ap, 1); ++ ++ /* bring link back */ ++ rc = sata_link_resume(link, timing, deadline); ++ if (rc) ++ goto out; ++ /* if link is offline nothing more to do */ ++ if (ata_phys_link_offline(link)) ++ goto out; ++ ++ /* Link is online. From this point, -ENODEV too is an error. */ ++ if (online) ++ *online = true; ++ ++ if (sata_pmp_supported(link->ap) && ata_is_host_link(link)) { ++ /* If PMP is supported, we have to do follow-up SRST. ++ * Some PMPs don't send D2H Reg FIS after hardreset if ++ * the first port is empty. Wait only for ++ * ATA_TMOUT_PMP_SRST_WAIT. ++ */ ++ if (check_ready) { ++ unsigned long pmp_deadline; ++ ++ pmp_deadline = ata_deadline(jiffies, ++ ATA_TMOUT_PMP_SRST_WAIT); ++ if (time_after(pmp_deadline, deadline)) ++ pmp_deadline = deadline; ++ ata_wait_ready(link, pmp_deadline, check_ready); ++ } ++ rc = -EAGAIN; ++ goto out; ++ } ++ ++ rc = 0; ++ if (check_ready) ++ rc = ata_wait_ready(link, deadline, check_ready); ++ out: ++ if (rc && rc != -EAGAIN) { ++ /* online is set iff link is online && reset succeeded */ ++ if (online) ++ *online = false; ++ ata_link_err(link, "COMRESET failed (errno=%d)\n", rc); ++ } ++ DPRINTK("EXIT, rc=%d\n", rc); ++ ++ if(rc==0 && resetAgain > 0) ++ { ++ resetAgain--; ++ goto DO_AGAIN; ++ } ++ return rc; ++} ++#endif ++ ++ + /** + * sata_std_hardreset - COMRESET w/o waiting or classification + * @link: link to reset +diff --git a/drivers/base/core.c b/drivers/base/core.c +old mode 100644 +new mode 100755 +index 03a82d017cf1..8ec7d845df41 +--- a/drivers/base/core.c ++++ b/drivers/base/core.c +@@ -870,14 +870,26 @@ static int device_add_class_symlinks(struct device *dev) + { + struct device_node *of_node = dev_of_node(dev); + int error; +- ++#ifdef CONFIG_DEFERRED_CREATE_DTS_SYSNODE ++ extern struct device **deferred_dts_node_dev; ++ extern int deferred_dts_node_dev_cnt; ++ if(!deferred_dts_node_dev) ++ { ++ deferred_dts_node_dev = kzalloc((sizeof(struct device *) * 128), GFP_KERNEL); ++ memset (deferred_dts_node_dev, 0, (sizeof(struct device *) * 128)); ++ } ++ if (of_node) { ++ deferred_dts_node_dev[deferred_dts_node_dev_cnt] = dev; ++ deferred_dts_node_dev_cnt++; ++ } ++#else + if (of_node) { + error = sysfs_create_link(&dev->kobj, &of_node->kobj,"of_node"); + if (error) + dev_warn(dev, "Error %d creating of_node link\n",error); + /* An error here doesn't warrant bringing down the device */ + } +- ++#endif + if (!dev->class) + return 0; + +diff --git a/drivers/base/init.c b/drivers/base/init.c +old mode 100644 +new mode 100755 +index 48c0e220acc0..7505ab5662ee +--- a/drivers/base/init.c ++++ b/drivers/base/init.c +@@ -35,5 +35,7 @@ void __init driver_init(void) + cpu_dev_init(); + memory_dev_init(); + container_dev_init(); ++#ifndef CONFIG_DEFERRED_CREATE_DTS_SYSNODE + of_core_init(); ++#endif + } +diff --git a/drivers/block/xen-blkback/xenbus.c b/drivers/block/xen-blkback/xenbus.c +index 5dfe6e8af140..ea88b4dc8a84 100644 +--- a/drivers/block/xen-blkback/xenbus.c ++++ b/drivers/block/xen-blkback/xenbus.c +@@ -254,6 +254,7 @@ static int xen_blkif_disconnect(struct xen_blkif *blkif) + + if (ring->xenblkd) { + kthread_stop(ring->xenblkd); ++ ring->xenblkd = NULL; + wake_up(&ring->shutdown_wq); + } + +diff --git a/drivers/char/random.c b/drivers/char/random.c +index 08d1dd58c0d2..997d98440964 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -1148,6 +1148,7 @@ void add_interrupt_randomness(int irq, int irq_flags) + + fast_mix(fast_pool); + add_interrupt_bench(cycles); ++ this_cpu_add(net_rand_state.s1, fast_pool->pool[cycles & 3]); + + if (!crng_ready()) { + if ((fast_pool->count >= 64) && +diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c +old mode 100644 +new mode 100755 +index 0fb39fe217d1..bd574776b4dc +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -796,7 +796,12 @@ unlock_out: + clk_core_disable_unprepare(core->parent); + } + ++#if defined(CONFIG_LH_RTOS) || defined(CONFIG_SS_AMP) ++/* for dual OS system, not to off clocks that may be used in RTOS. */ ++static bool clk_ignore_unused = true; ++#else + static bool clk_ignore_unused; ++#endif + static int __init clk_ignore_unused_setup(char *__unused) + { + clk_ignore_unused = true; +@@ -1979,7 +1984,7 @@ EXPORT_SYMBOL_GPL(clk_is_match); + + /*** debugfs support ***/ + +-#ifdef CONFIG_DEBUG_FS ++#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT) + #include + + static struct dentry *rootdir; +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +old mode 100644 +new mode 100755 +index a2503db7e533..bf60527c3ee6 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -31,6 +31,7 @@ + #include + + #include ++#include + + #define CNTTIDR 0x08 + #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) +@@ -478,6 +479,13 @@ static int arch_timer_starting_cpu(unsigned int cpu) + struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); + u32 flags; + ++#if defined(CONFIG_ARCH_SSTAR) && !defined(CONFIG_SS_DUALOS) ++ /* PATCH from Kernel 5.1: ++ * https://patchwork.kernel.org/patch/10353743/ ++ */ ++ secure_cntvoff_init(); ++#endif ++ + __arch_timer_setup(ARCH_CP15_TIMER, clk); + + flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); +@@ -489,6 +497,7 @@ static int arch_timer_starting_cpu(unsigned int cpu) + } + + arch_counter_set_user_access(); ++ + if (evtstrm_enable) + arch_timer_configure_evtstream(); + +diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c +old mode 100644 +new mode 100755 +index 8da03298f844..86854ce7cff3 +--- a/drivers/clocksource/arm_global_timer.c ++++ b/drivers/clocksource/arm_global_timer.c +@@ -259,7 +259,9 @@ static int __init global_timer_of_register(struct device_node *np) + { + struct clk *gt_clk; + int err = 0; +- ++#if defined(CONFIG_MP_GLOBAL_TIMER_CLK) ++ int msClock = 0; ++#endif + /* + * In A9 r2p0 the comparators for each processor with the global timer + * fire when the timer value is greater than or equal to. In previous +@@ -295,6 +297,20 @@ static int __init global_timer_of_register(struct device_node *np) + } + + gt_clk_rate = clk_get_rate(gt_clk); ++#if defined(CONFIG_MP_GLOBAL_TIMER_CLK) ++ //over write gt_clk_rate ++ msClock =(*(volatile unsigned short *)(0xfd221584) <<16) | (*(volatile unsigned short *)(0xfd221580) <<0); ++ ++ if (0x451EB7 == msClock) //800Mhz ++ gt_clk_rate = 400000000; ++ else if (0x2e147a == msClock) //1.2Ghz ++ gt_clk_rate = 600000000; ++ else if (0x277F44 == msClock) //1.4Ghz ++ gt_clk_rate = 700000000; ++ else //default 1Ghz ++ gt_clk_rate = 500000000; ++ printk("gt_clk_rate: %d\n", (int)gt_clk_rate); ++#endif + gt_evt = alloc_percpu(struct clock_event_device); + if (!gt_evt) { + pr_warn("global-timer: can't allocate memory\n"); +diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile +old mode 100644 +new mode 100755 +index 0a9b6a093646..91b021566442 +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -1,3 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ + # CPUfreq core + obj-$(CONFIG_CPU_FREQ) += cpufreq.o freq_table.o + +diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c +old mode 100644 +new mode 100755 +index 35e34c0e0429..05906d4c9c52 +--- a/drivers/cpufreq/cpufreq.c ++++ b/drivers/cpufreq/cpufreq.c +@@ -31,6 +31,10 @@ + #include + #include + ++#ifdef CONFIG_LH_RTOS ++#include "drv_dualos.h" ++#endif ++ + static LIST_HEAD(cpufreq_policy_list); + + static inline bool policy_is_inactive(struct cpufreq_policy *policy) +@@ -148,6 +152,7 @@ static inline u64 get_cpu_idle_time_jiffy(unsigned int cpu, u64 *wall) + return cputime_to_usecs(idle_time); + } + ++#ifndef CONFIG_LH_RTOS + u64 get_cpu_idle_time(unsigned int cpu, u64 *wall, int io_busy) + { + u64 idle_time = get_cpu_idle_time_us(cpu, io_busy ? wall : NULL); +@@ -159,6 +164,28 @@ u64 get_cpu_idle_time(unsigned int cpu, u64 *wall, int io_busy) + + return idle_time; + } ++#else ++u64 get_cpu_idle_time(unsigned int cpu, u64 *wall, int io_busy) ++{ ++ u64 idle_time = get_cpu_idle_time_us(cpu, io_busy ? wall : NULL); ++ u64 idle_in_rtos_time; ++ rtkinfo_t *rtk; ++ ++ rtk = get_rtkinfo(); ++ if (rtk) ++ { ++ idle_in_rtos_time = rtk->linux_idle_in_rtos_time; ++ } ++ ++ if (idle_time == -1ULL) ++ return get_cpu_idle_time_jiffy(cpu, wall) - RTK_TIME_TO_US(idle_in_rtos_time); ++ else if (!io_busy) ++ idle_time += get_cpu_iowait_time_us(cpu, wall); ++ ++ return idle_time - RTK_TIME_TO_US(idle_in_rtos_time); ++} ++#endif ++ + EXPORT_SYMBOL_GPL(get_cpu_idle_time); + + /* +diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c +index ab0fb804fb1e..4502b143fd8b 100644 +--- a/drivers/dma/imx-dma.c ++++ b/drivers/dma/imx-dma.c +@@ -765,7 +765,7 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan) + desc = kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) + break; +- __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); ++ memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor)); + dma_async_tx_descriptor_init(&desc->desc, chan); + desc->desc.tx_submit = imxdma_tx_submit; + /* txd.flags will be overwritten in prep funcs */ +diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c +index c6f780f5abc9..dc729c78ffe3 100644 +--- a/drivers/gpu/drm/i915/i915_gem_userptr.c ++++ b/drivers/gpu/drm/i915/i915_gem_userptr.c +@@ -654,6 +654,14 @@ i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) + return -ENOMEM; + } + ++ /* ++ * Using __get_user_pages_fast() with a read-only ++ * access is questionable. A read-only page may be ++ * COW-broken, and then this might end up giving ++ * the wrong side of the COW.. ++ * ++ * We may or may not care. ++ */ + pinned = __get_user_pages_fast(obj->userptr.ptr, num_pages, + !obj->userptr.read_only, pvec); + } +diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c +index 611b6b9bb3cb..67ea2ce03a23 100644 +--- a/drivers/gpu/drm/udl/udl_fb.c ++++ b/drivers/gpu/drm/udl/udl_fb.c +@@ -158,10 +158,15 @@ static int udl_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) + { + unsigned long start = vma->vm_start; + unsigned long size = vma->vm_end - vma->vm_start; +- unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ unsigned long offset; + unsigned long page, pos; + +- if (offset + size > info->fix.smem_len) ++ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) ++ return -EINVAL; ++ ++ offset = vma->vm_pgoff << PAGE_SHIFT; ++ ++ if (offset > info->fix.smem_len || size > info->fix.smem_len - offset) + return -EINVAL; + + pos = (unsigned long)info->fix.smem_start + offset; +diff --git a/drivers/hid/hid-debug.c b/drivers/hid/hid-debug.c +index acfb522a432a..29423691c105 100644 +--- a/drivers/hid/hid-debug.c ++++ b/drivers/hid/hid-debug.c +@@ -1152,6 +1152,8 @@ copy_rest: + goto out; + if (list->tail > list->head) { + len = list->tail - list->head; ++ if (len > count) ++ len = count; + + if (copy_to_user(buffer + ret, &list->hid_debug_buf[list->head], len)) { + ret = -EFAULT; +@@ -1161,6 +1163,8 @@ copy_rest: + list->head += len; + } else { + len = HID_DEBUG_BUFSIZE - list->head; ++ if (len > count) ++ len = count; + + if (copy_to_user(buffer, &list->hid_debug_buf[list->head], len)) { + ret = -EFAULT; +@@ -1168,7 +1172,9 @@ copy_rest: + } + list->head = 0; + ret += len; +- goto copy_rest; ++ count -= len; ++ if (count > 0) ++ goto copy_rest; + } + + } +diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c +index c41c8d0a4ac0..d243c7f29ad8 100644 +--- a/drivers/infiniband/hw/mlx4/main.c ++++ b/drivers/infiniband/hw/mlx4/main.c +@@ -1168,7 +1168,9 @@ static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) + /* need to protect from a race on closing the vma as part of + * mlx4_ib_vma_close(). + */ +- down_read(&owning_mm->mmap_sem); ++ down_write(&owning_mm->mmap_sem); ++ if (!mmget_still_valid(owning_mm)) ++ goto skip_mm; + for (i = 0; i < HW_BAR_COUNT; i++) { + vma = context->hw_bar_info[i].vma; + if (!vma) +@@ -1185,8 +1187,8 @@ static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) + /* context going to be destroyed, should not access ops any more */ + context->hw_bar_info[i].vma->vm_ops = NULL; + } +- +- up_read(&owning_mm->mmap_sem); ++skip_mm: ++ up_write(&owning_mm->mmap_sem); + mmput(owning_mm); + put_task_struct(owning_process); + } +diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c +index 5e29fbd3a5a0..e0e24c8d0858 100644 +--- a/drivers/infiniband/hw/mlx5/main.c ++++ b/drivers/infiniband/hw/mlx5/main.c +@@ -1313,7 +1313,9 @@ static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) + /* need to protect from a race on closing the vma as part of + * mlx5_ib_vma_close. + */ +- down_read(&owning_mm->mmap_sem); ++ down_write(&owning_mm->mmap_sem); ++ if (!mmget_still_valid(owning_mm)) ++ goto skip_mm; + list_for_each_entry_safe(vma_private, n, &context->vma_private_list, + list) { + vma = vma_private->vma; +@@ -1327,7 +1329,8 @@ static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) + list_del(&vma_private->list); + kfree(vma_private); + } +- up_read(&owning_mm->mmap_sem); ++skip_mm: ++ up_write(&owning_mm->mmap_sem); + mmput(owning_mm); + put_task_struct(owning_process); + } +diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c +old mode 100644 +new mode 100755 +index 9b8079ca0fb4..f3c268b221f5 +--- a/drivers/input/keyboard/gpio_keys.c ++++ b/drivers/input/keyboard/gpio_keys.c +@@ -33,6 +33,11 @@ + #include + #include + ++ ++#ifdef CONFIG_ARCH_SSTAR ++int key_status; ++#endif ++ + struct gpio_button_data { + const struct gpio_keys_button *button; + struct input_dev *input; +@@ -368,7 +373,26 @@ static void gpio_keys_gpio_report_event(struct gpio_button_data *bdata) + "failed to get gpio state: %d\n", state); + return; + } ++#ifdef CONFIG_ARCH_SSTAR ++ if(key_status==state) ++ { ++ pr_debug("false trigger"); ++ return; ++ } ++ key_status = state; ++ ++ if(key_status) ++ { ++ irq_set_irq_type(bdata->irq,IRQF_TRIGGER_RISING); ++ } ++ else ++ { ++ irq_set_irq_type(bdata->irq,IRQF_TRIGGER_FALLING); ++ ++ } + ++ pr_debug("gpio_keys_gpio_report_event: code = %d state=%d\r\n", button->code, state); ++#endif + if (type == EV_ABS) { + if (state) + input_event(input, type, button->code, button->value); +@@ -529,8 +553,22 @@ static int gpio_keys_setup_key(struct platform_device *pdev, + INIT_DELAYED_WORK(&bdata->work, gpio_keys_gpio_work_func); + + isr = gpio_keys_gpio_isr; +- irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; ++#ifdef CONFIG_ARCH_SSTAR ++ key_status = gpiod_get_value_cansleep(bdata->gpiod); ++ if (key_status < 0) { ++ dev_err(input->dev.parent, ++ "failed to get gpio state: %d\n", key_status); ++ return key_status; ++ } ++ ++ if(key_status) ++ irqflags = IRQF_TRIGGER_RISING; ++ else ++ irqflags = IRQF_TRIGGER_FALLING; + ++#else ++ irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; ++#endif + } else { + if (!button->irq) { + dev_err(dev, "No IRQ specified\n"); +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index efca0133e266..3d6898c42302 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -331,6 +331,8 @@ config TOUCHSCREEN_GOODIX + tristate "Goodix I2C touchscreen" + depends on I2C + depends on GPIOLIB || COMPILE_TEST ++ select FW_LOADER ++ select INPUT_EVDEV + help + Say Y here if you have the Goodix touchscreen (such as one + installed in Onda v975w tablets) connected to your +diff --git a/drivers/input/touchscreen/goodix.c b/drivers/input/touchscreen/goodix.c +index 240b16f3ee97..8ef33efa3cca 100644 +--- a/drivers/input/touchscreen/goodix.c ++++ b/drivers/input/touchscreen/goodix.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -29,7 +30,11 @@ + #include + #include + #include ++#include ++#include + #include ++#include ++#include + + struct goodix_ts_data { + struct i2c_client *client; +@@ -51,8 +56,8 @@ struct goodix_ts_data { + unsigned long irq_flags; + }; + +-#define GOODIX_GPIO_INT_NAME "irq" +-#define GOODIX_GPIO_RST_NAME "reset" ++#define GOODIX_GPIO_INT_NAME "goodix_int" ++#define GOODIX_GPIO_RST_NAME "goodix_rst" + + #define GOODIX_MAX_HEIGHT 4096 + #define GOODIX_MAX_WIDTH 4096 +@@ -121,7 +126,6 @@ static int goodix_i2c_read(struct i2c_client *client, + struct i2c_msg msgs[2]; + u16 wbuf = cpu_to_be16(reg); + int ret; +- + msgs[0].flags = 0; + msgs[0].addr = client->addr; + msgs[0].len = 2; +@@ -131,7 +135,6 @@ static int goodix_i2c_read(struct i2c_client *client, + msgs[1].addr = client->addr; + msgs[1].len = len; + msgs[1].buf = buf; +- + ret = i2c_transfer(client->adapter, msgs, 2); + return ret < 0 ? ret : (ret != ARRAY_SIZE(msgs) ? -EIO : 0); + } +@@ -397,29 +400,36 @@ static int goodix_int_sync(struct goodix_ts_data *ts) + static int goodix_reset(struct goodix_ts_data *ts) + { + int error; ++ unsigned gpio_rst; ++ unsigned gpio_int; ++ gpio_rst = desc_to_gpio(ts->gpiod_rst); ++ gpio_int = desc_to_gpio(ts->gpiod_int); ++ ++ gpio_request(gpio_rst, GOODIX_GPIO_INT_NAME); ++ gpio_request(gpio_int, GOODIX_GPIO_RST_NAME); + + /* begin select I2C slave addr */ +- error = gpiod_direction_output(ts->gpiod_rst, 0); ++ error = gpio_direction_output(gpio_rst, 0); + if (error) + return error; + + msleep(20); /* T2: > 10ms */ + + /* HIGH: 0x28/0x29, LOW: 0xBA/0xBB */ +- error = gpiod_direction_output(ts->gpiod_int, ts->client->addr == 0x14); ++ error = gpio_direction_output(gpio_int, ts->client->addr == 0x14); + if (error) + return error; + + usleep_range(100, 2000); /* T3: > 100us */ + +- error = gpiod_direction_output(ts->gpiod_rst, 1); ++ error = gpio_direction_output(gpio_rst, 1); + if (error) + return error; + + usleep_range(6000, 10000); /* T4: > 5ms */ + + /* end select I2C slave addr */ +- error = gpiod_direction_input(ts->gpiod_rst); ++ error = gpio_direction_input(gpio_rst); + if (error) + return error; + +@@ -435,6 +445,7 @@ static int goodix_reset(struct goodix_ts_data *ts) + * + * @ts: goodix_ts_data pointer + */ ++/* + static int goodix_get_gpio_config(struct goodix_ts_data *ts) + { + int error; +@@ -445,7 +456,7 @@ static int goodix_get_gpio_config(struct goodix_ts_data *ts) + return -EINVAL; + dev = &ts->client->dev; + +- /* Get the interrupt GPIO pin number */ ++ //Get the interrupt GPIO pin number + gpiod = devm_gpiod_get_optional(dev, GOODIX_GPIO_INT_NAME, GPIOD_IN); + if (IS_ERR(gpiod)) { + error = PTR_ERR(gpiod); +@@ -454,10 +465,9 @@ static int goodix_get_gpio_config(struct goodix_ts_data *ts) + GOODIX_GPIO_INT_NAME, error); + return error; + } +- + ts->gpiod_int = gpiod; + +- /* Get the reset line GPIO pin number */ ++ //Get the reset line GPIO pin number + gpiod = devm_gpiod_get_optional(dev, GOODIX_GPIO_RST_NAME, GPIOD_IN); + if (IS_ERR(gpiod)) { + error = PTR_ERR(gpiod); +@@ -471,7 +481,7 @@ static int goodix_get_gpio_config(struct goodix_ts_data *ts) + + return 0; + } +- ++*/ + /** + * goodix_read_config - Read the embedded configuration of the panel + * +@@ -678,7 +688,6 @@ static void goodix_config_cb(const struct firmware *cfg, void *ctx) + if (error) + goto err_release_cfg; + } +- + goodix_configure_dev(ts); + + err_release_cfg: +@@ -686,11 +695,140 @@ err_release_cfg: + complete_all(&ts->firmware_loading_complete); + } + ++ssize_t gtcfg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ int ret = 0; ++ char *srcbuf = NULL; ++ char tmpbuf[256] = {0}; ++ struct goodix_ts_data *ts; ++ ++ ts = (struct goodix_ts_data*)dev_get_drvdata(dev); ++ if(!ts){ ++ dev_err(dev,"no driver data\n"); ++ return -EINVAL; ++ } ++ srcbuf = (char*)kzalloc(256*5,GFP_KERNEL); ++ if(!srcbuf){ ++ dev_err(dev,"kzalloc tmpbuf failed\n"); ++ return -ENOMEM; ++ } ++ sprintf(tmpbuf,"ts_irqnum:%d\n",ts->client->irq); ++ strcat(srcbuf,tmpbuf); ++ sprintf(tmpbuf,"ts_intpin:%d\n",desc_to_gpio(ts->gpiod_int)); ++ strcat(srcbuf,tmpbuf); ++ sprintf(tmpbuf,"ts_rstpin:%d\n",desc_to_gpio(ts->gpiod_rst)); ++ strcat(srcbuf,tmpbuf); ++ ++ ret = sprintf(buf,"%s",srcbuf); ++ kfree(srcbuf); ++ ++ return ret; ++} ++ ++ssize_t gtcfg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ long ret = 0; ++ char filepath[256]; ++ char *str = NULL; ++ char *tmpbuf = NULL; ++ struct file* filp = NULL; ++ struct path p; ++ struct kstat ks; ++ unsigned long filesize = 0; ++ unsigned long long offset = 0; ++ mm_segment_t oldfs; ++ struct firmware cfg; ++ struct goodix_ts_data *ts; ++ ++ ts = (struct goodix_ts_data*)dev_get_drvdata(dev); ++ if(!ts){ ++ dev_err(dev,"no driver data\n"); ++ return -EINVAL; ++ } ++ if(buf){ ++ strcpy(filepath,buf); ++ str = filepath; ++ while((*str != ' ') && (*str != '\r') && (*str != '\n')) ++ str++; ++ *str = '\0'; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ filp = filp_open(filepath, O_RDONLY, 0); ++ if(IS_ERR(filp)) ++ { ++ dev_err(dev,"Open File fail [%s]\n",filepath); ++ ret = PTR_ERR(filp); ++ set_fs(oldfs); ++ return ret; ++ } ++ kern_path(filepath, 0, &p); ++ vfs_getattr(&p, &ks); ++ filesize = ks.size; ++ if(filesize != GOODIX_CONFIG_911_LENGTH){ ++ dev_err(dev,"file size Invalid [%s]\n",filepath); ++ filp_close(filp,NULL); ++ set_fs(oldfs); ++ return -EINVAL; ++ } ++ set_fs(oldfs); ++ ++ tmpbuf = (char*)kzalloc(filesize,GFP_KERNEL); ++ if(!tmpbuf){ ++ dev_err(dev,"alloc failed\n"); ++ filp_close(filp,NULL); ++ set_fs(oldfs); ++ return -ENOMEM; ++ } ++ else{ ++ cfg.data = tmpbuf; ++ cfg.size = filesize; ++ } ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_read(filp, tmpbuf, filesize, &offset); ++ if(ret == cfg.size){ ++ goodix_send_cfg(ts,&cfg); ++ } ++ filp_close(filp,NULL); ++ set_fs(oldfs); ++ ++ kfree(tmpbuf); ++ printk("config done\n"); ++ ++ return count; ++ } ++ return 0; ++} ++ ++DEVICE_ATTR(gtcfg,0664,gtcfg_show,gtcfg_store); ++ ++static int goodix_ts_sysfs_init(struct goodix_ts_data *ts) ++{ ++ int ret = 0; ++ ++ ret = device_create_file(&ts->client->dev, &dev_attr_gtcfg); ++ if(ret){ ++ dev_err(&ts->client->dev,"gt911 device create file failed\n"); ++ return ret; ++ } ++ return ret; ++} ++ ++static void goodix_ts_sysfs_deinit(struct goodix_ts_data *ts) ++{ ++ device_remove_file(&ts->client->dev, &dev_attr_gtcfg); ++} ++ + static int goodix_ts_probe(struct i2c_client *client, + const struct i2c_device_id *id) + { + struct goodix_ts_data *ts; + int error; ++ u32 gpio_rst; ++ u32 gpio_int; + + dev_dbg(&client->dev, "I2C Address: 0x%02x\n", client->addr); + +@@ -707,10 +845,20 @@ static int goodix_ts_probe(struct i2c_client *client, + i2c_set_clientdata(client, ts); + init_completion(&ts->firmware_loading_complete); + ++ if(0 != of_property_read_u32(client->dev.of_node, GOODIX_GPIO_RST_NAME, &gpio_rst)) ++ return -EINVAL; ++ ts->gpiod_rst = gpio_to_desc(gpio_rst); ++ if(0 != of_property_read_u32(client->dev.of_node, GOODIX_GPIO_INT_NAME, &gpio_int)) ++ return -EINVAL; ++ ts->gpiod_int = gpio_to_desc(gpio_int); ++ ++ ts->client->irq = of_irq_get_byname(client->dev.of_node, GOODIX_GPIO_INT_NAME); ++ dev_dbg(&client->dev, "goodix_irq_num:%d\n",ts->client->irq); ++ /* + error = goodix_get_gpio_config(ts); + if (error) + return error; +- ++ */ + if (ts->gpiod_int && ts->gpiod_rst) { + /* reset the controller */ + error = goodix_reset(ts); +@@ -750,13 +898,15 @@ static int goodix_ts_probe(struct i2c_client *client, + error); + return error; + } ++ } else { ++ error = goodix_configure_dev(ts); ++ if (error) ++ return error; ++ } + +- return 0; +- } else { +- error = goodix_configure_dev(ts); +- if (error) +- return error; +- } ++ if(goodix_ts_sysfs_init(ts)){ ++ dev_err(&client->dev,"gt911 sysfs init failed\n"); ++ } + + return 0; + } +@@ -765,6 +915,7 @@ static int goodix_ts_remove(struct i2c_client *client) + { + struct goodix_ts_data *ts = i2c_get_clientdata(client); + ++ goodix_ts_sysfs_deinit(ts); + if (ts->gpiod_int && ts->gpiod_rst) + wait_for_completion(&ts->firmware_loading_complete); + +diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile +old mode 100644 +new mode 100755 +index e4dbfc85abdb..212a48dd5b04 +--- a/drivers/irqchip/Makefile ++++ b/drivers/irqchip/Makefile +@@ -1,3 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ + obj-$(CONFIG_IRQCHIP) += irqchip.o + + obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o +diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c +old mode 100644 +new mode 100755 +index d6c404b3584d..6004db625991 +--- a/drivers/irqchip/irq-gic.c ++++ b/drivers/irqchip/irq-gic.c +@@ -50,6 +50,10 @@ + + #include "irq-gic-common.h" + ++#ifdef CONFIG_SS_AMP ++#include "drv_dualos.h" ++#endif ++ + #ifdef CONFIG_ARM64 + #include + +@@ -328,6 +332,9 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, + unsigned int cpu, shift = (gic_irq(d) % 4) * 8; + u32 val, mask, bit; + unsigned long flags; ++#ifdef CONFIG_SS_GIC_SET_MULTI_CPUS ++ struct irq_desc *desc = irq_to_desc(d->irq); ++#endif + + if (!force) + cpu = cpumask_any_and(mask_val, cpu_online_mask); +@@ -341,6 +348,13 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, + mask = 0xff << shift; + bit = gic_cpu_map[cpu] << shift; + val = readl_relaxed(reg) & ~mask; ++#ifdef CONFIG_SS_GIC_SET_MULTI_CPUS ++ if (desc && desc->affinity_hint) { ++ struct cpumask mask_hint; ++ if (cpumask_and(&mask_hint, desc->affinity_hint, mask_val)) ++ val |= (*cpumask_bits(&mask_hint) << shift) & mask; ++ } ++#endif + writel_relaxed(val | bit, reg); + gic_unlock_irqrestore(flags); + +@@ -348,16 +362,24 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, + } + #endif + ++#if defined(CONFIG_MP_IRQ_TRACE) ++extern void ms_records_irq_count(int); ++#endif ++ + static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) + { + u32 irqstat, irqnr; + struct gic_chip_data *gic = &gic_data[0]; + void __iomem *cpu_base = gic_data_cpu_base(gic); ++ + + do { + irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); + irqnr = irqstat & GICC_IAR_INT_ID_MASK; +- ++ ++#if defined(CONFIG_MP_IRQ_TRACE) ++ ms_records_irq_count(irqnr); ++#endif + if (likely(irqnr > 15 && irqnr < 1020)) { + if (static_key_true(&supports_deactivate)) + writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); +@@ -378,6 +400,41 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) + */ + smp_rmb(); + handle_IPI(irqnr, regs); ++#elif defined(CONFIG_LH_RTOS) ++ { ++ void handle_rsq(int); ++ irq_enter(); ++ handle_rsq(irqnr); ++ irq_exit(); ++ } ++#elif defined(CONFIG_SS_AMP) ++ { ++ extern void handle_interos_call_req(void); ++ extern void handle_interos_call_resp(void); ++#if ENABLE_NBLK_CALL ++ extern void handle_interos_nblk_call_req(void); ++#endif ++ ++ switch (irqnr) { ++ case IPI_NR_RTOS_2_LINUX_CALL_REQ: ++ irq_enter(); ++ handle_interos_call_req(); ++ irq_exit(); ++ break; ++ case IPI_NR_LINUX_2_RTOS_CALL_RESP: ++ irq_enter(); ++ handle_interos_call_resp(); ++ irq_exit(); ++ break; ++#if ENABLE_NBLK_CALL ++ case IPI_NR_RTOS_2_LINUX_NBLK_CALL_REQ: ++ irq_enter(); ++ handle_interos_nblk_call_req(); ++ irq_exit(); ++ break; ++#endif ++ } ++ } + #endif + continue; + } +diff --git a/drivers/media/usb/dvb-usb/technisat-usb2.c b/drivers/media/usb/dvb-usb/technisat-usb2.c +index 4706628a3ed5..10bccce22858 100644 +--- a/drivers/media/usb/dvb-usb/technisat-usb2.c ++++ b/drivers/media/usb/dvb-usb/technisat-usb2.c +@@ -612,10 +612,9 @@ static int technisat_usb2_frontend_attach(struct dvb_usb_adapter *a) + static int technisat_usb2_get_ir(struct dvb_usb_device *d) + { + struct technisat_usb2_state *state = d->priv; +- u8 *buf = state->buf; +- u8 *b; +- int ret; + struct ir_raw_event ev; ++ u8 *buf = state->buf; ++ int i, ret; + + buf[0] = GET_IR_DATA_VENDOR_REQUEST; + buf[1] = 0x08; +@@ -651,26 +650,25 @@ unlock: + return 0; /* no key pressed */ + + /* decoding */ +- b = buf+1; + + #if 0 + deb_rc("RC: %d ", ret); +- debug_dump(b, ret, deb_rc); ++ debug_dump(buf + 1, ret, deb_rc); + #endif + + ev.pulse = 0; +- while (1) { +- ev.pulse = !ev.pulse; +- ev.duration = (*b * FIRMWARE_CLOCK_DIVISOR * FIRMWARE_CLOCK_TICK) / 1000; +- ir_raw_event_store(d->rc_dev, &ev); +- +- b++; +- if (*b == 0xff) { ++ for (i = 1; i < ARRAY_SIZE(state->buf); i++) { ++ if (buf[i] == 0xff) { + ev.pulse = 0; + ev.duration = 888888*2; + ir_raw_event_store(d->rc_dev, &ev); + break; + } ++ ++ ev.pulse = !ev.pulse; ++ ev.duration = (buf[i] * FIRMWARE_CLOCK_DIVISOR * ++ FIRMWARE_CLOCK_TICK) / 1000; ++ ir_raw_event_store(d->rc_dev, &ev); + } + + ir_raw_event_handle(d->rc_dev); +diff --git a/drivers/media/usb/uvc/Kconfig b/drivers/media/usb/uvc/Kconfig +index 6ed85efabcaa..99b1f853cafe 100644 +--- a/drivers/media/usb/uvc/Kconfig ++++ b/drivers/media/usb/uvc/Kconfig +@@ -1,7 +1,11 @@ ++config SS_HOST_UVC ++ tristate ++ + config USB_VIDEO_CLASS + tristate "USB Video Class (UVC)" + depends on VIDEO_V4L2 + select VIDEOBUF2_VMALLOC ++ select SS_HOST_UVC + ---help--- + Support for the USB Video Class (UVC). Currently only video + input devices, such as webcams, are supported. +diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c +index cde43b63c3da..3e02d4528c1f 100644 +--- a/drivers/media/usb/uvc/uvc_driver.c ++++ b/drivers/media/usb/uvc/uvc_driver.c +@@ -143,6 +143,13 @@ static struct uvc_format_desc uvc_fmts[] = { + .guid = UVC_GUID_FORMAT_BGR3, + .fcc = V4L2_PIX_FMT_BGR24, + }, ++#if defined(CONFIG_SS_HOST_UVC) || defined(CONFIG_SS_HOST_UVC_MODULE) ++ { ++ .name = "H.265", ++ .guid = UVC_GUID_FORMAT_H265, ++ .fcc = V4L2_PIX_FMT_H265, ++ }, ++#endif + { + .name = "H.264", + .guid = UVC_GUID_FORMAT_H264, +diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h +index 7e4d3eea371b..e6f5188126f4 100644 +--- a/drivers/media/usb/uvc/uvcvideo.h ++++ b/drivers/media/usb/uvc/uvcvideo.h +@@ -115,7 +115,11 @@ + #define UVC_GUID_FORMAT_M420 \ + { 'M', '4', '2', '0', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +- ++#if defined(CONFIG_SS_HOST_UVC) || defined(CONFIG_SS_HOST_UVC_MODULE) ++#define UVC_GUID_FORMAT_H265 \ ++ { 'H', '2', '6', '5', 0x00, 0x00, 0x10, 0x00, \ ++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} ++#endif + #define UVC_GUID_FORMAT_H264 \ + { 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index 4510e8a37244..cb7a57a77651 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1258,6 +1258,9 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_PIX_FMT_JPEG: descr = "JFIF JPEG"; break; + case V4L2_PIX_FMT_DV: descr = "1394"; break; + case V4L2_PIX_FMT_MPEG: descr = "MPEG-1/2/4"; break; ++#if defined(CONFIG_SS_HOST_UVC) || defined(CONFIG_SS_HOST_UVC_MODULE) ++ case V4L2_PIX_FMT_H265: descr = "H.265"; break; ++#endif + case V4L2_PIX_FMT_H264: descr = "H.264"; break; + case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; + case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; +diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c +index 9ccf7f5e0e2e..1167226a0396 100644 +--- a/drivers/media/v4l2-core/videobuf2-core.c ++++ b/drivers/media/v4l2-core/videobuf2-core.c +@@ -32,6 +32,12 @@ + static int debug; + module_param(debug, int, 0644); + ++#if defined(CONFIG_SS_GADGET) || defined(CONFIG_SS_GADGET_MODULE) ++int userptr_mode_use_mi_buf = 0; ++module_param_named(use_mi_buf, userptr_mode_use_mi_buf, int, 0644); ++EXPORT_SYMBOL(userptr_mode_use_mi_buf); ++#endif ++ + #define dprintk(level, fmt, arg...) \ + do { \ + if (debug >= level) \ +@@ -1578,6 +1584,21 @@ static void __vb2_dqbuf(struct vb2_buffer *vb) + call_void_memop(vb, unmap_dmabuf, vb->planes[i].mem_priv); + vb->planes[i].dbuf_mapped = 0; + } ++ ++#if defined(CONFIG_SS_GADGET) || defined(CONFIG_SS_GADGET_MODULE) ++ /* Should umap before user put buf to mi sys */ ++ if (userptr_mode_use_mi_buf && q->memory == VB2_MEMORY_USERPTR) ++ for (i = 0; i < vb->num_planes; ++i) { ++ if (vb->planes[i].mem_priv) { ++ call_void_memop(vb, put_userptr, vb->planes[i].mem_priv); ++ } ++ vb->planes[i].mem_priv = NULL; ++ vb->planes[i].bytesused = 0; ++ vb->planes[i].length = 0; ++ vb->planes[i].m.userptr = 0; ++ vb->planes[i].data_offset = 0; ++ } ++#endif + } + + int vb2_core_dqbuf(struct vb2_queue *q, unsigned int *pindex, void *pb, +@@ -2028,6 +2049,7 @@ unsigned int vb2_core_poll(struct vb2_queue *q, struct file *file, + if (q->is_output && !(req_events & (POLLOUT | POLLWRNORM))) + return 0; + ++ poll_wait(file, &q->done_wq, wait); + /* + * Start file I/O emulator only if streaming API has not been used yet. + */ +@@ -2080,7 +2102,6 @@ unsigned int vb2_core_poll(struct vb2_queue *q, struct file *file, + if (q->last_buffer_dequeued) + return POLLIN | POLLRDNORM; + +- poll_wait(file, &q->done_wq, wait); + } + + /* +diff --git a/drivers/media/v4l2-core/videobuf2-memops.c b/drivers/media/v4l2-core/videobuf2-memops.c +index 1cd322e939c7..ddb9853aa25b 100644 +--- a/drivers/media/v4l2-core/videobuf2-memops.c ++++ b/drivers/media/v4l2-core/videobuf2-memops.c +@@ -22,6 +22,10 @@ + #include + #include + ++#if defined(CONFIG_SS_GADGET) || defined(CONFIG_SS_GADGET_MODULE) ++extern int userptr_mode_use_mi_buf; ++#endif ++ + /** + * vb2_create_framevec() - map virtual addresses to pfns + * @start: Virtual user address where we start mapping +@@ -57,10 +61,19 @@ struct frame_vector *vb2_create_framevec(unsigned long start, + if (ret < 0) + goto out_destroy; + /* We accept only complete set of PFNs */ ++#if defined(CONFIG_SS_GADGET) || defined(CONFIG_SS_GADGET_MODULE) ++ if (!userptr_mode_use_mi_buf) ++ { ++#endif + if (ret != nr) { + ret = -EFAULT; + goto out_release; + } ++#if defined(CONFIG_SS_GADGET) || defined(CONFIG_SS_GADGET_MODULE) ++ } else { ++ vec->nr_frames = ret; ++ } ++#endif + return vec; + out_release: + put_vaddr_frames(vec); +diff --git a/drivers/media/v4l2-core/videobuf2-v4l2.c b/drivers/media/v4l2-core/videobuf2-v4l2.c +index 52ef8833f6b6..dba9cd5e0ff5 100644 +--- a/drivers/media/v4l2-core/videobuf2-v4l2.c ++++ b/drivers/media/v4l2-core/videobuf2-v4l2.c +@@ -673,16 +673,14 @@ EXPORT_SYMBOL_GPL(vb2_queue_release); + unsigned int vb2_poll(struct vb2_queue *q, struct file *file, poll_table *wait) + { + struct video_device *vfd = video_devdata(file); +- unsigned long req_events = poll_requested_events(wait); + unsigned int res = 0; + + if (test_bit(V4L2_FL_USES_V4L2_FH, &vfd->flags)) { + struct v4l2_fh *fh = file->private_data; + ++ poll_wait(file, &fh->wait, wait); + if (v4l2_event_pending(fh)) + res = POLLPRI; +- else if (req_events & POLLPRI) +- poll_wait(file, &fh->wait, wait); + } + + return res | vb2_core_poll(q, file, wait); +diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig +index f2eeb38efa65..ba8e097387e0 100644 +--- a/drivers/mmc/Kconfig ++++ b/drivers/mmc/Kconfig +@@ -12,6 +12,13 @@ menuconfig MMC + If you want MMC/SD/SDIO support, you should say Y here and + also to your specific host controller driver. + ++config SS_FAST_MMC ++ bool ++ default y ++ depends on MMC != n ++ help ++ This make insert module faster with busy waiting on 100Hz system. ++ + config MMC_DEBUG + bool "MMC debugging" + depends on MMC != n +diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c +old mode 100644 +new mode 100755 +index 2553d903a82b..cd4689d6901d +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1723,7 +1723,8 @@ int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr) + } + + /* Keep clock gated for at least 10 ms, though spec only says 5 ms */ +- mmc_delay(10); ++ mmc_delay(10); ++ + host->ios.clock = clock; + mmc_set_ios(host); + +@@ -1833,7 +1834,11 @@ void mmc_power_up(struct mmc_host *host, u32 ocr) + * This delay should be sufficient to allow the power supply + * to reach the minimum voltage. + */ ++#if CONFIG_SS_FAST_MMC ++ mmc_delay(1);//reduced from 10 to 1 for faster booting. ++#else + mmc_delay(10); ++#endif + + mmc_pwrseq_post_power_on(host); + +@@ -1846,7 +1851,11 @@ void mmc_power_up(struct mmc_host *host, u32 ocr) + * This delay must be at least 74 clock sizes, or 1 ms, or the + * time required to reach a stable voltage. + */ ++#if CONFIG_SS_FAST_MMC ++ mmc_delay(1);//reduced from 10 to 1 for faster booting ++#else + mmc_delay(10); ++#endif + } + + void mmc_power_off(struct mmc_host *host) +diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c +index bd44ba8116d1..f59391c47e29 100644 +--- a/drivers/mmc/core/sdio.c ++++ b/drivers/mmc/core/sdio.c +@@ -561,7 +561,6 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, + /* to query card if 1.8V signalling is supported */ + if (mmc_host_uhs(host)) + ocr |= R4_18V_PRESENT; +- + try_again: + if (!retries) { + pr_warn("%s: Skipping voltage switch\n", mmc_hostname(host)); +diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig +old mode 100644 +new mode 100755 +index e83a279f1217..52e71c0111db +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -23,6 +23,17 @@ config MTD_TESTS + WARNING: some of the tests will ERASE entire MTD device which they + test. Do not use these tests unless you really know what you do. + ++if MTD_TESTS ++config MTD_SS_TESTS ++ bool "Special Tweak MTD tests" ++ default "0" ++ depends on MTD_TESTS ++ help ++ Add special functionality of standard MTD test. ++ For example, Add speed measurement for pagetest. ++ ++endif #MTD_TESTS ++ + config MTD_REDBOOT_PARTS + tristate "RedBoot partition table parsing" + ---help--- +diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c +old mode 100644 +new mode 100755 +index 3fad35942895..939fd865080b +--- a/drivers/mtd/maps/physmap_of.c ++++ b/drivers/mtd/maps/physmap_of.c +@@ -287,7 +287,18 @@ static int of_flash_probe(struct platform_device *dev) + &info->list[i].map); + } + mtd_list[i] = info->list[i].mtd; +- ++#ifdef CONFIG_MSTAR_DRIVERS ++ { ++ int erasesieze=0; ++ if(!of_property_read_u32(dp, "erase-size", &erasesieze)) ++ { ++ mtd_list[i]->erasesize = erasesieze; ++ printk( "[Physmap] %s search erase-size 0x%x on DTS\n", info->list[i].map.name, erasesieze ); ++ }else{ ++ printk( "[Physmap] %s not search erase-size on DTS, default is 0x%x\n",info->list[i].map.name, mtd_list[i]->erasesize ); ++ } ++ } ++#endif + err = -ENXIO; + if (!info->list[i].mtd) { + dev_err(&dev->dev, "do_map_probe() failed\n"); +diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c +old mode 100644 +new mode 100755 +index fccdd49bb964..50b52679c1de +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -54,6 +54,178 @@ static inline struct mtd_part *mtd_to_part(const struct mtd_info *mtd) + return container_of(mtd, struct mtd_part, mtd); + } + ++#ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++#include ++#define MAX_PARTITION_MAPPING 4 ++ ++struct part_map{ ++ struct mtd_info *part_mtd; /* Mapping partition mtd */ ++ unsigned *map_table; /* Mapping from logic block to phys block */ ++ unsigned nBlock; /* Logic block number */ ++}; ++ ++static struct part_map *part_mapping[MAX_PARTITION_MAPPING]; ++static int part_mapping_count = -1; ++ ++static loff_t ajust_offset(struct mtd_info *mtd, loff_t from) ++{ ++ struct mtd_part *part = mtd_to_part(mtd); ++ struct nand_chip *this = part->master->priv; ++ unsigned logic_b, phys_b; ++ unsigned index; ++ ++ if(part_mapping_count <= 0) ++ return from; ++ ++ for( index = 0; index < MAX_PARTITION_MAPPING; index++ ) ++ { ++ if(!part_mapping[index] || part_mapping[index]->part_mtd != mtd) ++ continue; ++ ++ /* remap from logic block to physical block */ ++ logic_b = from >> this->bbt_erase_shift; ++ if ( logic_b < part_mapping[index]->nBlock ) ++ { ++ phys_b = part_mapping[index]->map_table[logic_b]; ++ from = phys_b << this->bbt_erase_shift | (from&(mtd->erasesize-1)); ++ break; ++ } ++ } ++ ++ return from; ++} ++ ++static int part_create_partition_mapping ( struct mtd_info *part_mtd ) ++{ ++ struct mtd_part *part = mtd_to_part(part_mtd); ++ struct nand_chip *this = part->master->priv; ++ struct part_map *map_part; ++ int index; ++ unsigned offset; ++ int logical_b, phys_b; ++ ++ if (!part_mtd || !this || part_mtd->type == MTD_NORFLASH) ++ { ++ printk("null mtd or it is no nand chip!"); ++ return -1; ++ } ++ ++ if ( part_mapping_count < 0 ) ++ { ++ /* Init the part mapping table when this function called first time */ ++ memset(part_mapping, 0, sizeof(struct part_map *)*MAX_PARTITION_MAPPING); ++ part_mapping_count = 0; ++ } ++ ++ for ( index = 0; index < MAX_PARTITION_MAPPING; index++ ) ++ { ++ if ( part_mapping[index] == NULL ) ++ break; ++ } ++ ++ if ( index >= MAX_PARTITION_MAPPING ) ++ { ++ printk("partition mapping is full!"); ++ return -1; ++ } ++ ++ map_part = kmalloc(sizeof(struct part_map), GFP_KERNEL); ++ if ( !map_part ) ++ { ++ printk ("memory allocation error while creating partitions mapping for %s/n", ++ part_mtd->name); ++ return -1; ++ } ++ ++ map_part->map_table = kmalloc(sizeof(unsigned)*(part_mtd->size>>this->bbt_erase_shift), ++ GFP_KERNEL); ++ if ( !map_part->map_table ) ++ { ++ printk ("memory allocation error while creating partitions mapping for %s/n", part_mtd->name); ++ kfree(map_part); ++ return -1; ++ } ++ memset(map_part->map_table, 0xFF, sizeof(unsigned)*(part_mtd->size>>this->bbt_erase_shift)); ++ ++ /* Create partition mapping table */ ++ logical_b = 0; ++ for ( offset=0; offsetsize; offset+=part_mtd->erasesize ) ++ { ++ if ( part_mtd->_block_isbad && ++ part_mtd->_block_isbad(part_mtd, offset) ) ++ continue; ++ ++ phys_b = offset >> this->bbt_erase_shift; ++ map_part->map_table[logical_b] = phys_b; ++ //printk("part[%s]: logic[%u]=phys[%u]\n",part_mtd->name, logical_b, phys_b); ++ logical_b++; ++ } ++ map_part->nBlock = logical_b; ++ map_part->part_mtd = part_mtd; ++ ++ part_mapping[index] = map_part; ++ part_mapping_count++; ++ ++ return 0; ++} ++ ++static void part_del_partition_mapping( struct mtd_info *part_mtd ) ++{ ++ int index; ++ struct part_map *map_part; ++ ++ if (part_mapping_count <= 0) ++ return; ++ ++ for (index = 0; index < MAX_PARTITION_MAPPING; index++ ) ++ { ++ map_part = part_mapping[index]; ++ ++ if(!map_part || map_part->part_mtd != part_mtd) ++ continue; ++ ++ kfree(map_part->map_table); ++ kfree(map_part); ++ part_mapping[index] = NULL; ++ part_mapping_count--; ++ } ++} ++ ++static int part_is_squashfs( struct mtd_info *part_mtd ) ++{ ++ struct mtd_part *part = mtd_to_part(part_mtd); ++ struct nand_chip *this = part->master->priv; ++ ++ u_char buf[16]; ++ size_t retlen; ++ unsigned offset; ++ ++ if (!part_mtd || !this || part_mtd->type == MTD_NORFLASH) ++ { ++ //printk("null mtd or it is no nand chip!"); ++ return 0; ++ } ++ ++ for (offset=0; offseterasesize*2; offset+=part_mtd->erasesize) ++ { ++ if (part_mtd->_block_isbad && ++ part_mtd->_block_isbad(part_mtd, offset)) ++ continue; ++ ++ if(part_mtd->_read) ++ { ++ part_mtd->_read(part_mtd, offset, 16, &retlen, buf); ++ if(!memcmp(buf, "hsqs", 4)) ++ { ++ //printk("%s:%d partition is squashfs\n", __func__, __LINE__); ++ return 1; ++ } ++ } ++ } ++ ++ return 0; ++} ++#endif + + /* + * MTD methods which simply translate the effective address and pass through +@@ -67,6 +239,10 @@ static int part_read(struct mtd_info *mtd, loff_t from, size_t len, + struct mtd_ecc_stats stats; + int res; + ++ #ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++ from = ajust_offset(mtd, from); ++ #endif ++ + stats = part->master->ecc_stats; + res = part->master->_read(part->master, from + part->offset, len, + retlen, buf); +@@ -113,6 +289,10 @@ static int part_read_oob(struct mtd_info *mtd, loff_t from, + struct mtd_part *part = mtd_to_part(mtd); + int res; + ++ #ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++ from = ajust_offset(mtd, from); ++ #endif ++ + if (from >= mtd->size) + return -EINVAL; + if (ops->datbuf && from + ops->len > mtd->size) +@@ -368,6 +548,9 @@ int del_mtd_partitions(struct mtd_info *master) + mutex_lock(&mtd_partitions_mutex); + list_for_each_entry_safe(slave, next, &mtd_partitions, list) + if (slave->master == master) { ++ #ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++ part_del_partition_mapping(&slave->mtd); ++ #endif + ret = del_mtd_device(&slave->mtd); + if (ret < 0) { + err = ret; +@@ -649,9 +832,14 @@ int mtd_add_partition(struct mtd_info *master, const char *name, + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); +- ++ + mtd_add_partition_attrs(new); + ++ #ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++ if(part_is_squashfs(&new->mtd)) ++ part_create_partition_mapping(&new->mtd); ++ #endif ++ + return ret; + } + EXPORT_SYMBOL_GPL(mtd_add_partition); +@@ -667,6 +855,11 @@ int mtd_del_partition(struct mtd_info *master, int partno) + (slave->mtd.index == partno)) { + sysfs_remove_files(&slave->mtd.dev.kobj, + mtd_partition_attrs); ++ ++ #ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++ part_del_partition_mapping(&slave->mtd); ++ #endif ++ + ret = del_mtd_device(&slave->mtd); + if (ret < 0) + break; +@@ -714,6 +907,11 @@ int add_mtd_partitions(struct mtd_info *master, + add_mtd_device(&slave->mtd); + mtd_add_partition_attrs(slave); + ++ #ifdef CONFIG_SKIP_SQUASHFS_BAD_BLOCK ++ if(part_is_squashfs(&slave->mtd)) ++ part_create_partition_mapping(&slave->mtd); ++ #endif ++ + cur_offset = slave->offset + slave->mtd.size; + } + +@@ -891,3 +1089,7 @@ uint64_t mtd_get_device_size(const struct mtd_info *mtd) + return mtd_to_part(mtd)->master->size; + } + EXPORT_SYMBOL_GPL(mtd_get_device_size); ++#if defined(CONFIG_MS_NAND) || defined(CONFIG_MS_NAND_MODULE) || defined(CONFIG_MS_SPINAND)|| defined(CONFIG_MS_SPINAND_MODULE) ++EXPORT_SYMBOL_GPL(parse_mtd_partitions); ++EXPORT_SYMBOL_GPL(add_mtd_partitions); ++#endif +diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c +index 21c03086bb7f..33d6dd352fb9 100644 +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -47,6 +47,18 @@ + #include + #include + ++#if defined(CONFIG_MS_NAND) || defined(CONFIG_MS_NAND_MODULE) ++#include "../../sstar/include/ms_types.h" ++#include "../../sstar/unfd/inc/common/drvNAND.h" ++#define HERE //printk(KERN_ERR"[%s]%d\n",__FILE__,__LINE__) ++#endif ++ ++#if defined(CONFIG_MS_SPINAND) || defined(CONFIG_MS_SPINAND_MODULE) ++// #include "../../sstar/include/ms_types.h" ++#include "../../sstar/spinand/drv/mdrv_spinand.h" ++#define HERE //printk(KERN_ERR"[%s]%d\n",__FILE__,__LINE__) ++#endif ++ + static int nand_get_device(struct mtd_info *mtd, int new_state); + + static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, +@@ -1105,7 +1117,8 @@ static int nand_setup_data_interface(struct nand_chip *chip) + err: + return ret; + } +- ++#if defined(CONFIG_MS_NAND) || defined(CONFIG_MS_NAND_MODULE) || defined(CONFIG_MS_SPINAND)|| defined(CONFIG_MS_SPINAND_MODULE)//ENABLE_MODULE_NAND_FLASH == 1 ++#else + /** + * nand_init_data_interface - find the best data interface and timings + * @chip: The NAND chip +@@ -1162,7 +1175,7 @@ static int nand_init_data_interface(struct nand_chip *chip) + + return 0; + } +- ++#endif + static void nand_release_data_interface(struct nand_chip *chip) + { + kfree(chip->data_interface); +@@ -4410,6 +4423,33 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, + /* Set the default functions */ + nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); + ++#if defined(CONFIG_MS_NAND) || defined(CONFIG_MS_NAND_MODULE) || defined(CONFIG_MS_SPINAND)|| defined(CONFIG_MS_SPINAND_MODULE)//ENABLE_MODULE_NAND_FLASH == 1 ++ if(chip->mtd_param_init != NULL) ++ { ++ int err; ++ err = chip->mtd_param_init(mtd, chip, &nand_maf_id, &nand_dev_id, table); ++ type = ERR_PTR(err); ++ HERE; ++ if(IS_ERR(type) && type != 0) ++ { ++ HERE; ++ type = nand_get_flash_type(mtd, chip, &nand_maf_id, &nand_dev_id, table); ++ HERE; ++ if (IS_ERR(type)) ++ { ++ HERE; ++ chip->select_chip(mtd, -1); ++ HERE; ++ return PTR_ERR(type); ++ } ++ } ++ else ++ chip->erase = single_erase; ++ } ++ i = 1; ++ HERE; ++#else ++ + /* Read the flash type */ + type = nand_get_flash_type(mtd, chip, &nand_maf_id, + &nand_dev_id, table); +@@ -4458,7 +4498,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, + } + if (i > 1) + pr_info("%d chips detected\n", i); +- ++#endif + /* Store the number of chips and calc total size for mtd */ + chip->numchips = i; + mtd->size = i * chip->chipsize; +diff --git a/drivers/mtd/tests/Makefile b/drivers/mtd/tests/Makefile +index 937a829bb701..cb9e67e06d29 100644 +--- a/drivers/mtd/tests/Makefile ++++ b/drivers/mtd/tests/Makefile +@@ -7,9 +7,11 @@ obj-$(CONFIG_MTD_TESTS) += mtd_subpagetest.o + obj-$(CONFIG_MTD_TESTS) += mtd_torturetest.o + obj-$(CONFIG_MTD_TESTS) += mtd_nandecctest.o + obj-$(CONFIG_MTD_TESTS) += mtd_nandbiterrs.o ++obj-$(CONFIG_MTD_TESTS) += mtd_walking1.o + + mtd_oobtest-objs := oobtest.o mtd_test.o + mtd_pagetest-objs := pagetest.o mtd_test.o ++mtd_walking1-objs := walking1.o mtd_test.o + mtd_readtest-objs := readtest.o mtd_test.o + mtd_speedtest-objs := speedtest.o mtd_test.o + mtd_stresstest-objs := stresstest.o mtd_test.o +diff --git a/drivers/mtd/tests/readtest.c b/drivers/mtd/tests/readtest.c +old mode 100644 +new mode 100755 +index 58df07acdbdb..610ef754ecde +--- a/drivers/mtd/tests/readtest.c ++++ b/drivers/mtd/tests/readtest.c +@@ -122,6 +122,36 @@ static void dump_eraseblock(int ebnum) + } + } + ++#ifdef CONFIG_MTD_SS_TESTS ++static ktime_t start, finish; ++//static int goodebcnt; ++static inline void start_timing(void) ++{ ++ start = ktime_get(); ++} ++ ++static inline void stop_timing(void) ++{ ++ finish = ktime_get(); ++} ++ ++static long calc_speed(void) ++{ ++ uint64_t k; ++ long ms; ++ ++ ms = ktime_ms_delta(finish, start); ++ if (ms == 0) ++ return 0; ++// k = (uint64_t)goodebcnt * (mtd->erasesize / 1024) * 1000; ++ k = (uint64_t)ebcnt * (mtd->erasesize); ++//pr_info("goodebcnt:%d\n", ebcnt); ++//pr_info("erase size:%d\n", mtd->erasesize); ++ do_div(k, ms); ++ return k; ++} ++#endif ++ + static int __init mtd_readtest_init(void) + { + uint64_t tmp; +@@ -179,6 +209,10 @@ static int __init mtd_readtest_init(void) + + /* Read all eraseblocks 1 page at a time */ + pr_info("testing page read\n"); ++#ifdef CONFIG_MTD_SS_TESTS ++ start_timing(); ++#endif ++ + for (i = 0; i < ebcnt; ++i) { + int ret; + +@@ -202,6 +236,14 @@ static int __init mtd_readtest_init(void) + pr_info("finished with errors\n"); + else + pr_info("finished\n"); ++#ifdef CONFIG_MTD_SS_TESTS ++ { ++ long speed; ++ stop_timing(); ++ speed = calc_speed(); ++ pr_info("read speed is %ld KB/s\n", speed); ++ } ++#endif + + out: + +diff --git a/drivers/mtd/tests/walking1.c b/drivers/mtd/tests/walking1.c +new file mode 100644 +index 000000000000..23e44895121f +--- /dev/null ++++ b/drivers/mtd/tests/walking1.c +@@ -0,0 +1,526 @@ ++/* ++ * Copyright (C) 2006-2008 Nokia Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; see the file COPYING. If not, write to the Free Software ++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Test page read and write on MTD device. ++ * ++ * Author: Adrian Hunter ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mtd_test.h" ++ ++static int dev = -EINVAL; ++module_param(dev, int, S_IRUGO); ++MODULE_PARM_DESC(dev, "MTD device number to use"); ++ ++static struct mtd_info *mtd; ++static unsigned char *twopages; ++static unsigned char *writebuf; ++static unsigned char *boundary; ++static unsigned char *bbt; ++ ++static int pgsize; ++static int bufsize; ++static int ebcnt; ++static int pgcnt; ++static int errcnt; ++static struct rnd_state rnd_state; ++ ++//#define FILL_PATTERN(state, buf, size) prandom_bytes_state(state, buf, size) ++#define FILL_PATTERN(state, buf, size) fill_walking_1(buf, size) ++ ++void fill_walking_1(unsigned char* buf, int size) ++{ ++ int i; ++ unsigned char pat[8] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; ++ //pr_info("Preparing %d bytes walking 1 pattern\n", size); ++ for (i = 0; i < size; ++i) { ++ buf[i] = pat[i%8]; ++ } ++} ++ ++void hex_dump(unsigned char* buf, int size, loff_t offset) ++{ ++ int i; ++ char line[256]; ++ char *p; ++ ++ i = 0; ++ p = line; ++ do ++ { ++ if(i % 16 == 0) ++ { ++ if(p != line) ++ { ++ printk(line); ++ p = line; ++ } ++ p += sprintf(p, "\n%08X ", (unsigned int)offset + i); ++ } ++ p += sprintf(p, "%02X ", buf[i]); ++ i++; ++ } while (i < size); ++ if(p != line) ++ { ++ printk(line); ++ p = line; ++ } ++ printk("\n"); ++} ++ ++static int write_eraseblock(int ebnum) ++{ ++ loff_t addr = (loff_t)ebnum * mtd->erasesize; ++ ++ FILL_PATTERN(&rnd_state, writebuf, mtd->erasesize); ++ cond_resched(); ++ return mtdtest_write(mtd, addr, mtd->erasesize, writebuf); ++} ++ ++static int verify_eraseblock(int ebnum) ++{ ++ uint32_t j; ++ int err = 0, i; ++ loff_t addr0, addrn; ++ loff_t addr = (loff_t)ebnum * mtd->erasesize; ++ ++ addr0 = 0; ++ for (i = 0; i < ebcnt && bbt[i]; ++i) ++ addr0 += mtd->erasesize; ++ ++ addrn = mtd->size; ++ for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i) ++ addrn -= mtd->erasesize; ++ ++ FILL_PATTERN(&rnd_state, writebuf, mtd->erasesize); ++ for (j = 0; j < pgcnt - 1; ++j, addr += pgsize) { ++ /* Do a read to set the internal dataRAMs to different data */ ++ err = mtdtest_read(mtd, addr0, bufsize, twopages); ++ if (err) ++ return err; ++ err = mtdtest_read(mtd, addrn - bufsize, bufsize, twopages); ++ if (err) ++ return err; ++ memset(twopages, 0, bufsize); ++ err = mtdtest_read(mtd, addr, bufsize, twopages); ++ if (err) ++ break; ++ if (memcmp(twopages, writebuf + (j * pgsize), bufsize)) { ++ pr_err("error: verify failed at %#llx\n", ++ (long long)addr); ++ hex_dump(twopages, 512, addr); ++ errcnt += 1; ++ } ++ } ++ /* Check boundary between eraseblocks */ ++ if (addr <= addrn - pgsize - pgsize && !bbt[ebnum + 1]) { ++ struct rnd_state old_state = rnd_state; ++ ++ /* Do a read to set the internal dataRAMs to different data */ ++ err = mtdtest_read(mtd, addr0, bufsize, twopages); ++ if (err) ++ return err; ++ err = mtdtest_read(mtd, addrn - bufsize, bufsize, twopages); ++ if (err) ++ return err; ++ memset(twopages, 0, bufsize); ++ err = mtdtest_read(mtd, addr, bufsize, twopages); ++ if (err) ++ return err; ++ memcpy(boundary, writebuf + mtd->erasesize - pgsize, pgsize); ++ FILL_PATTERN(&rnd_state, boundary + pgsize, pgsize); ++ if (memcmp(twopages, boundary, bufsize)) { ++ pr_err("error: verify failed at %#llx\n", ++ (long long)addr); ++ hex_dump(twopages, 512, addr); ++ errcnt += 1; ++ } ++ rnd_state = old_state; ++ } ++ return err; ++} ++ ++static int crosstest(void) ++{ ++ int err = 0, i; ++ loff_t addr, addr0, addrn; ++ unsigned char *pp1, *pp2, *pp3, *pp4; ++ ++ pr_info("crosstest\n"); ++ pp1 = kzalloc(pgsize * 4, GFP_KERNEL); ++ if (!pp1) ++ return -ENOMEM; ++ pp2 = pp1 + pgsize; ++ pp3 = pp2 + pgsize; ++ pp4 = pp3 + pgsize; ++ ++ addr0 = 0; ++ for (i = 0; i < ebcnt && bbt[i]; ++i) ++ addr0 += mtd->erasesize; ++ ++ addrn = mtd->size; ++ for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i) ++ addrn -= mtd->erasesize; ++ ++ /* Read 2nd-to-last page to pp1 */ ++ addr = addrn - pgsize - pgsize; ++ err = mtdtest_read(mtd, addr, pgsize, pp1); ++ if (err) { ++ kfree(pp1); ++ return err; ++ } ++ ++ /* Read 3rd-to-last page to pp1 */ ++ addr = addrn - pgsize - pgsize - pgsize; ++ err = mtdtest_read(mtd, addr, pgsize, pp1); ++ if (err) { ++ kfree(pp1); ++ return err; ++ } ++ ++ /* Read first page to pp2 */ ++ addr = addr0; ++ pr_info("reading page at %#llx\n", (long long)addr); ++ err = mtdtest_read(mtd, addr, pgsize, pp2); ++ if (err) { ++ kfree(pp1); ++ return err; ++ } ++ ++ /* Read last page to pp3 */ ++ addr = addrn - pgsize; ++ pr_info("reading page at %#llx\n", (long long)addr); ++ err = mtdtest_read(mtd, addr, pgsize, pp3); ++ if (err) { ++ kfree(pp1); ++ return err; ++ } ++ ++ /* Read first page again to pp4 */ ++ addr = addr0; ++ pr_info("reading page at %#llx\n", (long long)addr); ++ err = mtdtest_read(mtd, addr, pgsize, pp4); ++ if (err) { ++ kfree(pp1); ++ return err; ++ } ++ ++ /* pp2 and pp4 should be the same */ ++ pr_info("verifying pages read at %#llx match\n", ++ (long long)addr0); ++ if (memcmp(pp2, pp4, pgsize)) { ++ pr_err("verify failed!\n"); ++ hex_dump(twopages, 512, addr); ++ errcnt += 1; ++ } else if (!err) ++ pr_info("crosstest ok\n"); ++ kfree(pp1); ++ return err; ++} ++ ++static int erasecrosstest(void) ++{ ++ int err = 0, i, ebnum, ebnum2; ++ loff_t addr0; ++ char *readbuf = twopages; ++ ++ pr_info("erasecrosstest\n"); ++ ++ ebnum = 0; ++ addr0 = 0; ++ for (i = 0; i < ebcnt && bbt[i]; ++i) { ++ addr0 += mtd->erasesize; ++ ebnum += 1; ++ } ++ ++ ebnum2 = ebcnt - 1; ++ while (ebnum2 && bbt[ebnum2]) ++ ebnum2 -= 1; ++ ++ pr_info("erasing block %d\n", ebnum); ++ err = mtdtest_erase_eraseblock(mtd, ebnum); ++ if (err) ++ return err; ++ ++ pr_info("writing 1st page of block %d\n", ebnum); ++ FILL_PATTERN(&rnd_state, writebuf, pgsize); ++ strcpy(writebuf, "There is no data like this!"); ++ err = mtdtest_write(mtd, addr0, pgsize, writebuf); ++ if (err) ++ return err; ++ ++ pr_info("reading 1st page of block %d\n", ebnum); ++ memset(readbuf, 0, pgsize); ++ err = mtdtest_read(mtd, addr0, pgsize, readbuf); ++ if (err) ++ return err; ++ ++ pr_info("verifying 1st page of block %d\n", ebnum); ++ if (memcmp(writebuf, readbuf, pgsize)) { ++ pr_err("verify failed!\n"); ++ hex_dump(twopages, 512, addr0); ++ errcnt += 1; ++ return -1; ++ } ++ ++ pr_info("erasing block %d\n", ebnum); ++ err = mtdtest_erase_eraseblock(mtd, ebnum); ++ if (err) ++ return err; ++ ++ pr_info("writing 1st page of block %d\n", ebnum); ++ FILL_PATTERN(&rnd_state, writebuf, pgsize); ++ strcpy(writebuf, "There is no data like this!"); ++ err = mtdtest_write(mtd, addr0, pgsize, writebuf); ++ if (err) ++ return err; ++ ++ pr_info("erasing block %d\n", ebnum2); ++ err = mtdtest_erase_eraseblock(mtd, ebnum2); ++ if (err) ++ return err; ++ ++ pr_info("reading 1st page of block %d\n", ebnum); ++ memset(readbuf, 0, pgsize); ++ err = mtdtest_read(mtd, addr0, pgsize, readbuf); ++ if (err) ++ return err; ++ ++ pr_info("verifying 1st page of block %d\n", ebnum); ++ if (memcmp(writebuf, readbuf, pgsize)) { ++ pr_err("verify failed!\n"); ++ hex_dump(twopages, 512, addr0); ++ errcnt += 1; ++ return -1; ++ } ++ ++ if (!err) ++ pr_info("erasecrosstest ok\n"); ++ return err; ++} ++ ++static int erasetest(void) ++{ ++ int err = 0, i, ebnum, ok = 1; ++ loff_t addr0; ++ ++ pr_info("erasetest\n"); ++ ++ ebnum = 0; ++ addr0 = 0; ++ for (i = 0; i < ebcnt && bbt[i]; ++i) { ++ addr0 += mtd->erasesize; ++ ebnum += 1; ++ } ++ ++ pr_info("erasing block %d\n", ebnum); ++ err = mtdtest_erase_eraseblock(mtd, ebnum); ++ if (err) ++ return err; ++ ++ pr_info("writing 1st page of block %d\n", ebnum); ++ FILL_PATTERN(&rnd_state, writebuf, pgsize); ++ err = mtdtest_write(mtd, addr0, pgsize, writebuf); ++ if (err) ++ return err; ++ ++ pr_info("erasing block %d\n", ebnum); ++ err = mtdtest_erase_eraseblock(mtd, ebnum); ++ if (err) ++ return err; ++ ++ pr_info("reading 1st page of block %d\n", ebnum); ++ err = mtdtest_read(mtd, addr0, pgsize, twopages); ++ if (err) ++ return err; ++ ++ pr_info("verifying 1st page of block %d is all 0xff\n", ++ ebnum); ++ for (i = 0; i < pgsize; ++i) ++ if (twopages[i] != 0xff) { ++ pr_err("verifying all 0xff failed at %d\n", ++ i); ++ errcnt += 1; ++ ok = 0; ++ break; ++ } ++ ++ if (ok && !err) ++ pr_info("erasetest ok\n"); ++ ++ return err; ++} ++ ++static int __init mtd_pagetest_init(void) ++{ ++ int err = 0; ++ uint64_t tmp; ++ uint32_t i; ++ ++ printk(KERN_INFO "\n"); ++ printk(KERN_INFO "=================================================\n"); ++ ++ if (dev < 0) { ++ pr_info("Please specify a valid mtd-device via module parameter\n"); ++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n"); ++ return -EINVAL; ++ } ++ ++ pr_info("MTD device: %d\n", dev); ++ ++ mtd = get_mtd_device(NULL, dev); ++ if (IS_ERR(mtd)) { ++ err = PTR_ERR(mtd); ++ pr_err("error: cannot get MTD device\n"); ++ return err; ++ } ++ ++ if (!mtd_type_is_nand(mtd)) { ++ pr_info("this test requires NAND flash\n"); ++ goto out; ++ } ++ ++ tmp = mtd->size; ++ do_div(tmp, mtd->erasesize); ++ ebcnt = tmp; ++ pgcnt = mtd->erasesize / mtd->writesize; ++ pgsize = mtd->writesize; ++ ++ pr_info("MTD device size %llu, eraseblock size %u, " ++ "page size %u, count of eraseblocks %u, pages per " ++ "eraseblock %u, OOB size %u\n", ++ (unsigned long long)mtd->size, mtd->erasesize, ++ pgsize, ebcnt, pgcnt, mtd->oobsize); ++ ++ err = -ENOMEM; ++ bufsize = pgsize * 2; ++ writebuf = kmalloc(mtd->erasesize, GFP_KERNEL); ++ if (!writebuf) ++ goto out; ++ twopages = kmalloc(bufsize, GFP_KERNEL); ++ if (!twopages) ++ goto out; ++ boundary = kmalloc(bufsize, GFP_KERNEL); ++ if (!boundary) ++ goto out; ++ ++ bbt = kzalloc(ebcnt, GFP_KERNEL); ++ if (!bbt) ++ goto out; ++ err = mtdtest_scan_for_bad_eraseblocks(mtd, bbt, 0, ebcnt); ++ if (err) ++ goto out; ++ ++ /* Erase all eraseblocks */ ++ pr_info("erasing whole device\n"); ++ err = mtdtest_erase_good_eraseblocks(mtd, bbt, 0, ebcnt); ++ if (err) ++ goto out; ++ pr_info("erased %u eraseblocks\n", ebcnt); ++ ++ /* Write all eraseblocks */ ++ prandom_seed_state(&rnd_state, 1); ++ pr_info("writing whole device\n"); ++ ++ for (i = 0; i < ebcnt; ++i) { ++ if (bbt[i]) ++ continue; ++ err = write_eraseblock(i); ++ if (err) ++ goto out; ++ if (i % 256 == 0) ++ pr_info("written up to eraseblock %u\n", i); ++ ++ err = mtdtest_relax(); ++ if (err) ++ goto out; ++ } ++ pr_info("written %u eraseblocks\n", i); ++ ++ /* Check all eraseblocks */ ++ prandom_seed_state(&rnd_state, 1); ++ pr_info("verifying all eraseblocks\n"); ++ for (i = 0; i < ebcnt; ++i) { ++ if (bbt[i]) ++ continue; ++ err = verify_eraseblock(i); ++ if (err) ++ goto out; ++ if (i % 256 == 0) ++ pr_info("verified up to eraseblock %u\n", i); ++ ++ err = mtdtest_relax(); ++ if (err) ++ goto out; ++ } ++ pr_info("verified %u eraseblocks\n", i); ++ ++ err = crosstest(); ++ if (err) ++ goto out; ++#if 0 //skip this step so that the pattern could be read back later in UBOOT. erasecrosstest() is done in pagetest anyway. ++ err = erasecrosstest(); ++ if (err) ++ goto out; ++ ++ err = erasetest(); ++ if (err) ++ goto out; ++#else ++ if (err) ++ goto will_not_happened; ++#endif ++ ++ pr_info("finished with %d errors\n", errcnt); ++out: ++ ++ kfree(bbt); ++ kfree(boundary); ++ kfree(twopages); ++ kfree(writebuf); ++ put_mtd_device(mtd); ++ if (err) ++ pr_info("error %d occurred\n", err); ++ printk(KERN_INFO "=================================================\n"); ++ return err; ++will_not_happened: ++ err = erasecrosstest(); ++ err = erasetest(); ++ return err; ++} ++module_init(mtd_pagetest_init); ++ ++static void __exit mtd_pagetest_exit(void) ++{ ++ return; ++} ++module_exit(mtd_pagetest_exit); ++ ++MODULE_DESCRIPTION("NAND walking 1"); ++MODULE_AUTHOR("Adrian Hunter"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c +index 85d54f37e28f..741876991886 100644 +--- a/drivers/mtd/ubi/build.c ++++ b/drivers/mtd/ubi/build.c +@@ -876,7 +876,11 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, + if (ubi && mtd->index == ubi->mtd->index) { + pr_err("ubi: mtd%d is already attached to ubi%d", + mtd->index, i); ++#if defined(CONFIG_MS_NAND) || defined(CONFIG_MS_NAND_MODULE) || defined(CONFIG_MS_SPINAND) || defined(CONFIG_MS_SPINAND_MODULE) ++ return ubi->ubi_num; ++#else + return -EEXIST; ++#endif + } + } + +diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c +index 5d5012337d9e..014b9ae3dc17 100644 +--- a/drivers/net/can/usb/gs_usb.c ++++ b/drivers/net/can/usb/gs_usb.c +@@ -632,6 +632,7 @@ static int gs_can_open(struct net_device *netdev) + rc); + + usb_unanchor_urb(urb); ++ usb_free_urb(urb); + break; + } + +diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.c b/drivers/net/ethernet/hisilicon/hns/hns_enet.c +index c06845b7b666..a7a7e18a776b 100644 +--- a/drivers/net/ethernet/hisilicon/hns/hns_enet.c ++++ b/drivers/net/ethernet/hisilicon/hns/hns_enet.c +@@ -299,9 +299,9 @@ static void fill_tso_desc(struct hnae_ring *ring, void *priv, + mtu); + } + +-int hns_nic_net_xmit_hw(struct net_device *ndev, +- struct sk_buff *skb, +- struct hns_nic_ring_data *ring_data) ++netdev_tx_t hns_nic_net_xmit_hw(struct net_device *ndev, ++ struct sk_buff *skb, ++ struct hns_nic_ring_data *ring_data) + { + struct hns_nic_priv *priv = netdev_priv(ndev); + struct hnae_ring *ring = ring_data->ring; +@@ -360,6 +360,10 @@ int hns_nic_net_xmit_hw(struct net_device *ndev, + dev_queue = netdev_get_tx_queue(ndev, skb->queue_mapping); + netdev_tx_sent_queue(dev_queue, skb->len); + ++ netif_trans_update(ndev); ++ ndev->stats.tx_bytes += skb->len; ++ ndev->stats.tx_packets++; ++ + wmb(); /* commit all data before submit */ + assert(skb->queue_mapping < priv->ae_handle->q_num); + hnae_queue_xmit(priv->ae_handle->qs[skb->queue_mapping], buf_num); +@@ -1407,17 +1411,11 @@ static netdev_tx_t hns_nic_net_xmit(struct sk_buff *skb, + struct net_device *ndev) + { + struct hns_nic_priv *priv = netdev_priv(ndev); +- int ret; + + assert(skb->queue_mapping < ndev->ae_handle->q_num); +- ret = hns_nic_net_xmit_hw(ndev, skb, +- &tx_ring_data(priv, skb->queue_mapping)); +- if (ret == NETDEV_TX_OK) { +- netif_trans_update(ndev); +- ndev->stats.tx_bytes += skb->len; +- ndev->stats.tx_packets++; +- } +- return (netdev_tx_t)ret; ++ ++ return hns_nic_net_xmit_hw(ndev, skb, ++ &tx_ring_data(priv, skb->queue_mapping)); + } + + static int hns_nic_change_mtu(struct net_device *ndev, int new_mtu) +diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.h b/drivers/net/ethernet/hisilicon/hns/hns_enet.h +index 5b412de350aa..7bc6a6ecd666 100644 +--- a/drivers/net/ethernet/hisilicon/hns/hns_enet.h ++++ b/drivers/net/ethernet/hisilicon/hns/hns_enet.h +@@ -91,8 +91,8 @@ void hns_ethtool_set_ops(struct net_device *ndev); + void hns_nic_net_reset(struct net_device *ndev); + void hns_nic_net_reinit(struct net_device *netdev); + int hns_nic_init_phy(struct net_device *ndev, struct hnae_handle *h); +-int hns_nic_net_xmit_hw(struct net_device *ndev, +- struct sk_buff *skb, +- struct hns_nic_ring_data *ring_data); ++netdev_tx_t hns_nic_net_xmit_hw(struct net_device *ndev, ++ struct sk_buff *skb, ++ struct hns_nic_ring_data *ring_data); + + #endif /**__HNS_ENET_H */ +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +old mode 100644 +new mode 100755 +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +old mode 100644 +new mode 100755 +diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c +old mode 100644 +new mode 100755 +index e5f251b91578..1ce6cbc386d1 +--- a/drivers/net/phy/icplus.c ++++ b/drivers/net/phy/icplus.c +@@ -179,6 +179,20 @@ static int ip101a_g_config_init(struct phy_device *phydev) + c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); + c |= IP101A_G_APS_ON; + ++#if (defined (CONFIG_ARCH_INFINITY6E) || defined (CONFIG_ARCH_INFINITY6B0)) ++ if(1) ++ { ++ int saved_page; ++ ++ printk("[PHY] Increased Tx CLK driving for daughter board... %s ## %d \n", __func__, __LINE__); ++ saved_page = phy_read(phydev, 20); ++ ++ phy_write(phydev, 20, 4); ++ phy_write(phydev, 22, 0xa000); ++ phy_write(phydev, 20, saved_page); ++ } ++#endif ++ + return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); + } + +diff --git a/drivers/net/wireless/ath/ath6kl/wmi.c b/drivers/net/wireless/ath/ath6kl/wmi.c +index 3fd1cc98fd2f..55609fc4e50e 100644 +--- a/drivers/net/wireless/ath/ath6kl/wmi.c ++++ b/drivers/net/wireless/ath/ath6kl/wmi.c +@@ -1178,6 +1178,10 @@ static int ath6kl_wmi_pstream_timeout_event_rx(struct wmi *wmi, u8 *datap, + return -EINVAL; + + ev = (struct wmi_pstream_timeout_event *) datap; ++ if (ev->traffic_class >= WMM_NUM_AC) { ++ ath6kl_err("invalid traffic class: %d\n", ev->traffic_class); ++ return -EINVAL; ++ } + + /* + * When the pstream (fat pipe == AC) timesout, it means there were +@@ -1519,6 +1523,10 @@ static int ath6kl_wmi_cac_event_rx(struct wmi *wmi, u8 *datap, int len, + return -EINVAL; + + reply = (struct wmi_cac_event *) datap; ++ if (reply->ac >= WMM_NUM_AC) { ++ ath6kl_err("invalid AC: %d\n", reply->ac); ++ return -EINVAL; ++ } + + if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) && + (reply->status_code != IEEE80211_TSPEC_STATUS_ADMISS_ACCEPTED)) { +@@ -2635,7 +2643,7 @@ int ath6kl_wmi_delete_pstream_cmd(struct wmi *wmi, u8 if_idx, u8 traffic_class, + u16 active_tsids = 0; + int ret; + +- if (traffic_class > 3) { ++ if (traffic_class >= WMM_NUM_AC) { + ath6kl_err("invalid traffic class: %d\n", traffic_class); + return -EINVAL; + } +diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c +index 9c16e2a6d185..d640f406e554 100644 +--- a/drivers/net/wireless/ath/ath9k/wmi.c ++++ b/drivers/net/wireless/ath/ath9k/wmi.c +@@ -337,6 +337,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, + ath_dbg(common, WMI, "Timeout waiting for WMI command: %s\n", + wmi_cmd_to_name(cmd_id)); + mutex_unlock(&wmi->op_mutex); ++ kfree_skb(skb); + return -ETIMEDOUT; + } + +diff --git a/drivers/net/wireless/marvell/libertas/cfg.c b/drivers/net/wireless/marvell/libertas/cfg.c +index 7ff2efadceca..3eab802c7d3f 100644 +--- a/drivers/net/wireless/marvell/libertas/cfg.c ++++ b/drivers/net/wireless/marvell/libertas/cfg.c +@@ -272,6 +272,10 @@ add_ie_rates(u8 *tlv, const u8 *ie, int *nrates) + int hw, ap, ap_max = ie[1]; + u8 hw_rate; + ++ if (ap_max > MAX_RATES) { ++ lbs_deb_assoc("invalid rates\n"); ++ return tlv; ++ } + /* Advance past IE header */ + ie += 2; + +@@ -1789,6 +1793,9 @@ static int lbs_ibss_join_existing(struct lbs_private *priv, + struct cmd_ds_802_11_ad_hoc_join cmd; + u8 preamble = RADIO_PREAMBLE_SHORT; + int ret = 0; ++ int hw, i; ++ u8 rates_max; ++ u8 *rates; + + lbs_deb_enter(LBS_DEB_CFG80211); + +@@ -1849,9 +1856,12 @@ static int lbs_ibss_join_existing(struct lbs_private *priv, + if (!rates_eid) { + lbs_add_rates(cmd.bss.rates); + } else { +- int hw, i; +- u8 rates_max = rates_eid[1]; +- u8 *rates = cmd.bss.rates; ++ rates_max = rates_eid[1]; ++ if (rates_max > MAX_RATES) { ++ lbs_deb_join("invalid rates"); ++ goto out; ++ } ++ rates = cmd.bss.rates; + for (hw = 0; hw < ARRAY_SIZE(lbs_rates); hw++) { + u8 hw_rate = lbs_rates[hw].bitrate / 5; + for (i = 0; i < rates_max; i++) { +diff --git a/drivers/net/wireless/marvell/mwifiex/ie.c b/drivers/net/wireless/marvell/mwifiex/ie.c +index c488c3068abc..7bac333b65e9 100644 +--- a/drivers/net/wireless/marvell/mwifiex/ie.c ++++ b/drivers/net/wireless/marvell/mwifiex/ie.c +@@ -240,6 +240,9 @@ static int mwifiex_update_vs_ie(const u8 *ies, int ies_len, + } + + vs_ie = (struct ieee_types_header *)vendor_ie; ++ if (le16_to_cpu(ie->ie_length) + vs_ie->len + 2 > ++ IEEE_MAX_IE_SIZE) ++ return -EINVAL; + memcpy(ie->ie_buffer + le16_to_cpu(ie->ie_length), + vs_ie, vs_ie->len + 2); + le16_add_cpu(&ie->ie_length, vs_ie->len + 2); +diff --git a/drivers/net/wireless/marvell/mwifiex/scan.c b/drivers/net/wireless/marvell/mwifiex/scan.c +index 78d59a67f7e1..674ad3405646 100644 +--- a/drivers/net/wireless/marvell/mwifiex/scan.c ++++ b/drivers/net/wireless/marvell/mwifiex/scan.c +@@ -1236,6 +1236,8 @@ int mwifiex_update_bss_desc_with_ie(struct mwifiex_adapter *adapter, + } + switch (element_id) { + case WLAN_EID_SSID: ++ if (element_len > IEEE80211_MAX_SSID_LEN) ++ return -EINVAL; + bss_entry->ssid.ssid_len = element_len; + memcpy(bss_entry->ssid.ssid, (current_ptr + 2), + element_len); +@@ -1245,6 +1247,8 @@ int mwifiex_update_bss_desc_with_ie(struct mwifiex_adapter *adapter, + break; + + case WLAN_EID_SUPP_RATES: ++ if (element_len > MWIFIEX_SUPPORTED_RATES) ++ return -EINVAL; + memcpy(bss_entry->data_rates, current_ptr + 2, + element_len); + memcpy(bss_entry->supported_rates, current_ptr + 2, +diff --git a/drivers/net/wireless/marvell/mwifiex/uap_cmd.c b/drivers/net/wireless/marvell/mwifiex/uap_cmd.c +index a7e9f544f219..f2ef1464e20c 100644 +--- a/drivers/net/wireless/marvell/mwifiex/uap_cmd.c ++++ b/drivers/net/wireless/marvell/mwifiex/uap_cmd.c +@@ -287,6 +287,8 @@ mwifiex_set_uap_rates(struct mwifiex_uap_bss_param *bss_cfg, + + rate_ie = (void *)cfg80211_find_ie(WLAN_EID_SUPP_RATES, var_pos, len); + if (rate_ie) { ++ if (rate_ie->len > MWIFIEX_SUPPORTED_RATES) ++ return; + memcpy(bss_cfg->rates, rate_ie + 1, rate_ie->len); + rate_len = rate_ie->len; + } +@@ -294,8 +296,11 @@ mwifiex_set_uap_rates(struct mwifiex_uap_bss_param *bss_cfg, + rate_ie = (void *)cfg80211_find_ie(WLAN_EID_EXT_SUPP_RATES, + params->beacon.tail, + params->beacon.tail_len); +- if (rate_ie) ++ if (rate_ie) { ++ if (rate_ie->len > MWIFIEX_SUPPORTED_RATES - rate_len) ++ return; + memcpy(bss_cfg->rates + rate_len, rate_ie + 1, rate_ie->len); ++ } + + return; + } +@@ -413,6 +418,8 @@ mwifiex_set_wmm_params(struct mwifiex_private *priv, + params->beacon.tail_len); + if (vendor_ie) { + wmm_ie = (struct ieee_types_header *)vendor_ie; ++ if (*(vendor_ie + 1) > sizeof(struct mwifiex_types_wmm_info)) ++ return; + memcpy(&bss_cfg->wmm_info, wmm_ie + 1, + sizeof(bss_cfg->wmm_info)); + priv->wmm_enabled = 1; +diff --git a/drivers/of/base.c b/drivers/of/base.c +old mode 100644 +new mode 100755 +index a0bccb54a9bd..45f0c6353862 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -219,6 +219,43 @@ void __init of_core_init(void) + proc_symlink("device-tree", NULL, "/sys/firmware/devicetree/base"); + } + ++#ifdef CONFIG_DEFERRED_CREATE_DTS_SYSNODE ++#include ++struct device **deferred_dts_node_dev =0; ++int deferred_dts_node_dev_cnt=0; ++ ++static int __init deferred_of_core_init(void) ++{ ++ struct device_node *np; ++ struct device *dev; ++ int error; ++ int i; ++ ++ of_core_init(); ++ ++ //Create symlinks for device_add_class_symlinks() ++ for(i=0 ; ifull_name); ++ ++ if (np) { ++ error = sysfs_create_link(&dev->kobj, &np->kobj,"of_node"); ++ if (error) ++ dev_warn(dev, "Error %d creating of_node link\n",error); ++ /* An error here doesn't warrant bringing down the device */ ++ } ++ ++ } ++ kfree(deferred_dts_node_dev); ++ ++ return 0; ++} ++deferred_module_init(deferred_of_core_init); ++#endif ++ + static struct property *__of_find_property(const struct device_node *np, + const char *name, int *lenp) + { +diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c +old mode 100644 +new mode 100755 +index 502f5547a1f2..84149e123b6d +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -573,7 +573,9 @@ void *initial_boot_params; + + #ifdef CONFIG_OF_EARLY_FLATTREE + ++#ifndef CONFIG_FB_DTS_SKIP_CRC + static u32 of_fdt_crc32; ++#endif + + /** + * res_mem_reserve_reg() - reserve all memory described in 'reg' property +@@ -1057,8 +1059,14 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname, + early_init_dt_add_memory_arch(base, size); + } + ++#ifdef CONFIG_FB_DTS_SCAN_MEMORY_ONCE ++ return 1; ++#endif ++ + return 0; + } ++extern __initdata int gb_ATAG_CMDLINE_found; ++extern __initdata int gb_ATAG_INITRD2_found; + + int __init early_init_dt_scan_chosen(unsigned long node, const char *uname, + int depth, void *data) +@@ -1071,8 +1079,25 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname, + if (depth != 1 || !data || + (strcmp(uname, "chosen") != 0 && strcmp(uname, "chosen@0") != 0)) + return 0; ++#ifdef CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT ++ if(!gb_ATAG_INITRD2_found) ++ { ++ early_init_dt_check_for_initrd(node); ++ } ++#else ++ early_init_dt_check_for_initrd(node); ++#endif ++ + +- early_init_dt_check_for_initrd(node); ++ ++#ifdef CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT ++ if(gb_ATAG_CMDLINE_found) ++ { ++ pr_debug("Command line is: %s\n", (char*)data); ++ /* break now */ ++ return 1; ++ } ++#endif + + /* Retrieve command line */ + p = of_get_flat_dt_prop(node, "bootargs", &l); +@@ -1200,8 +1225,10 @@ bool __init early_init_dt_verify(void *params) + + /* Setup flat device-tree pointer */ + initial_boot_params = params; ++#ifndef CONFIG_FB_DTS_SKIP_CRC + of_fdt_crc32 = crc32_be(~0, initial_boot_params, + fdt_totalsize(initial_boot_params)); ++#endif + return true; + } + +@@ -1230,6 +1257,154 @@ bool __init early_init_dt_scan(void *params) + return true; + } + ++#ifdef CONFIG_SS_BUILTIN_UNFDT ++ ++extern void *builtin_unfdt_start; ++extern void *builtin_dtb_start; ++extern void *unfdt_runtime_base; ++extern void *fdt_runtime_base; ++void *undft_old_addr=0; ++void *dfb_old_addr=0; ++ ++void show_unfdt(struct device_node *dad) ++{ ++ struct device_node *np; ++ struct property *pp; ++ printk("+++++++++++++++++++++++++++++++++++++++++++++++++++++\n"); ++ ++ //revise root all of trees ++ for (np = dad; np; np = __of_find_all_nodes(np)) ++ { ++ printk("\nnp: %p \n", np); ++ if(np->name) printk("name :%p %s\n", np->name, np->name); ++ if(np->phandle) printk("phandle :%x\n", np->phandle); ++ if(np->type) printk("type :%p %s \n", np->type, np->type); ++ if(np->full_name) printk("full_name :%p %s\n", np->full_name,np->full_name); ++ if(np->deadprops) printk("deadprops :%p\n", np->deadprops); ++ if(np->parent) printk("parent :%p\n", np->parent); ++ if(np->child) printk("child :%p\n", np->child); ++ if(np->sibling) printk("sibling :%p\n", np->sibling); ++ if(np->data) printk("data :%p\n", np->data); ++ if(np->_flags) printk("_flags :0x%lx\n", np->_flags); ++ if(np->properties) printk("properties:%p\n", np->properties); ++ ++ if(np->properties) { ++ for_each_property_of_node(np, pp) { ++#if 0 ++ //printk(">> pp:%p name:%p value:%p len:(%2d) next:%p (%s) [%s]\n", pp, pp->name, pp->value,pp->length, pp->next, pp->name, (char*) pp->value); ++ printk(">> pp:%p name:%p value:%p len:(%2d) next:%p (%s) flag(%ld) id(%d)\n", pp, pp->name, pp->value,pp->length, pp->next, pp->name, pp->_flags, pp->unique_id); ++#else ++ if(!strcmp(pp->name ,"compatible")) ++ printk(">> pp:%p len:(%2d) (%s)\t[%s]\n", pp, pp->length, pp->name,(char*) pp->value); ++ else if(!pp->length) ++ printk(">> pp:%p len:(%2d) (%s)\n", pp, pp->length, pp->name); ++ else if( pp->length==4 ) ++ printk(">> pp:%p len:(%2d) (%s)\t[%08x]\n", pp, pp->length, pp->name, __be32_to_cpu( *(int*)pp->value)); ++ else if( pp->length==8 ) ++ printk(">> pp:%p len:(%2d) (%s)\t[%08x %08x]\n", pp, pp->length, pp->name, __be32_to_cpu(*(int*)pp->value),__be32_to_cpu( *(int*)(pp->value+4))); ++ else if( !(pp->length%4) ) ++ printk(">> pp:%p len:(%2d) (%s)\t[%08x %08x %08x]\n", pp, pp->length, pp->name, __be32_to_cpu(*(int*)pp->value),__be32_to_cpu( *(int*)(pp->value+4)), __be32_to_cpu(*(int*)(pp->value+8))); ++ else ++ printk(">> pp:%p len:(%2d) (%s)\t[%s]\n", pp, pp->length, pp->name,(char*) pp->value); ++ if(pp->attr.attr.name) printk(" >>pp->attr.attr.name:%p\n",pp->attr.attr.name); ++ if(pp->attr.write) printk(" >>pp->attr.write:%p\n", pp->attr.write); ++ if(pp->attr.private) printk(" >>pp->attr.private:%p\n", pp->attr.private); ++ if(pp->attr.read) printk(" >>pp->attr.read:%p\n", pp->attr.read); ++ if(pp->attr.mmap) printk(" >>pp->attr.mmap:%p\n", pp->attr.mmap); ++#endif ++ } ++ } ++ } ++ printk("+++++++++++++++++++++++++++++++++++++++++++++++++++++\n"); ++} ++ ++//#define DEBUG_SHOW_UNFDT_NP_B ++//#define DEBUG_SHOW_UNFDT_NP ++//#define DEBUG_SHOW_UNFDT_PP ++void revise_unfdt(struct device_node **mynodes) ++{ ++ struct device_node *np; ++ struct property *pp; ++ //int i=0; ++ int undft_offset = builtin_unfdt_start-undft_old_addr; ++ int dfb_offset = builtin_dtb_start-dfb_old_addr; ++ ++ //revise root all of trees ++ for (np = (struct device_node *) builtin_unfdt_start; np; np = __of_find_all_nodes(np)) ++ { ++#ifdef DEBUG_SHOW_UNFDT_NP_B ++ printk("\n before np: %p \n", np); ++ if(np->name) printk("name :%p\n", np->name); ++ if(np->phandle) printk("phandle :%x\n", np->phandle); ++ if(np->type) printk("type :%p\n", np->type); ++ if(np->full_name) printk("full_name :%p\n", np->full_name); ++ if(np->deadprops) printk("deadprops :%p\n", np->deadprops); ++ if(np->parent) printk("parent :%p\n", np->parent); ++ if(np->child) printk("child :%p\n", np->child); ++ if(np->sibling) printk("sibling :%p\n", np->sibling); ++ if(np->data) printk("data :%p\n", np->data); ++ if(np->properties) printk("properties:%p\n", np->properties); ++#endif ++ ++ //if(i++>10) break; ++ if(np->name) np->name += undft_offset; ++ np->type = ""; //const char *type; ++ //phandle phandle; ++ if(np->full_name) np->full_name += undft_offset; ++ if(np->properties) np->properties = (struct property *)((int)np->properties + undft_offset); ++ if(np->deadprops) np->deadprops = (struct property *)((int)np->deadprops + undft_offset); ++ if(np->parent) np->parent = (struct device_node *)((int)np->parent + undft_offset); ++ if(np->child) np->child = (struct device_node *)((int)np->child + undft_offset); ++ if(np->sibling) np->sibling = (struct device_node *)((int)np->sibling + undft_offset); ++ //np->_flags = 0; ++ //np->kobj.state_initialized=0; ++ of_node_init(np);//struct kobject kobj; //struct fwnode_handle fwnode; ++ ++#ifdef DEBUG_SHOW_UNFDT_NP ++ printk("\nnp: %p \n", np); ++ if(np->name) printk("name :%p %s\n", np->name, np->name); ++ if(np->phandle) printk("phandle :%x\n", np->phandle); ++ if(np->type) printk("type :%p %s \n", np->type, np->type); ++ if(np->full_name) printk("full_name :%p %s\n", np->full_name,np->full_name); ++ if(np->deadprops) printk("deadprops :%p\n", np->deadprops); ++ if(np->parent) printk("parent :%p\n", np->parent); ++ if(np->child) printk("child :%p\n", np->child); ++ if(np->sibling) printk("sibling :%p\n", np->sibling); ++ if(np->data) printk("data :%p\n", np->data); ++ if(np->properties) printk("properties:%p\n", np->properties); ++#endif ++ if(np->properties) { ++ for_each_property_of_node(np, pp) { ++ if(pp->next) pp->next = (struct property *)((int)pp->next + undft_offset); ++ if(pp->value && pp->next) pp->value = (void *)((int)pp->value + dfb_offset); ++ if(pp->name && pp->next) pp->name += dfb_offset; ++ if(!pp->next) { ++ pp->name = "name"; ++ pp->value = (void *)np->name; ++ } ++ if (!strcmp(pp->name, "device_type")){ ++ np->type = pp->value; ++ printk("pp->name, pp->value %s have changed\n",(char*) pp->value); ++ } ++#ifdef DEBUG_SHOW_UNFDT_PP ++ //printk(" >> properties:%p name:%p value:%p next:%p (%s)\n", pp, pp->name, pp->value, pp->next, pp->name); ++ printk(" >> properties:%p name:%p value:%p next:%p (%s) [%s]\n", pp, pp->name, pp->value, pp->next, pp->name,(char*) pp->value); ++ if(pp->attr.attr.name) printk(" >>pp->attr.attr.name:%p\n",pp->attr.attr.name); ++ if(pp->attr.write) printk(" >>pp->attr.write:%p\n", pp->attr.write); ++ if(pp->attr.private) printk(" >>pp->attr.private:%p\n", pp->attr.private); ++ if(pp->attr.read) printk(" >>pp->attr.read:%p\n", pp->attr.read); ++ if(pp->attr.mmap) printk(" >>pp->attr.mmap:%p\n", pp->attr.mmap); ++#endif ++ ++ } ++ } ++ } ++ ++ if (mynodes) ++ *mynodes = (struct device_node *) builtin_unfdt_start; ++} ++#endif ++ + /** + * unflatten_device_tree - create tree of device_nodes from flat blob + * +@@ -1238,10 +1413,23 @@ bool __init early_init_dt_scan(void *params) + * pointers of the nodes so the normal device-tree walking functions + * can be used. + */ ++ + void __init unflatten_device_tree(void) + { ++ ++#ifndef CONFIG_SS_BUILTIN_UNFDT + __unflatten_device_tree(initial_boot_params, NULL, &of_root, + early_init_dt_alloc_memory_arch, false); ++#else ++ undft_old_addr = (void *) *(u32 *)unfdt_runtime_base; ++ dfb_old_addr = (void *) *(u32 *)fdt_runtime_base; ++ revise_unfdt(&of_root); ++ pr_debug("+++++ of_root :%p\n", of_root); ++ pr_debug("+++++ builtin_unfdt_start:%p\n", builtin_unfdt_start); ++ pr_debug("+++++ builtin_dtb_start :%p\n", builtin_dtb_start); ++ pr_debug("+++++ undft_old_addr :%p\n", undft_old_addr); ++ pr_debug("+++++ dfb_old_addr :%p\n", dfb_old_addr); ++#endif + + /* Get pointer to "/chosen" and "/aliases" nodes for use everywhere */ + of_alias_scan(early_init_dt_alloc_memory_arch); +@@ -1295,12 +1483,13 @@ static int __init of_fdt_raw_init(void) + + if (!initial_boot_params) + return 0; +- ++#ifndef CONFIG_FB_DTS_SKIP_CRC + if (of_fdt_crc32 != crc32_be(~0, initial_boot_params, + fdt_totalsize(initial_boot_params))) { + pr_warn("not creating '/sys/firmware/fdt': CRC check failed\n"); + return 0; + } ++#endif + of_fdt_raw_attr.size = fdt_totalsize(initial_boot_params); + return sysfs_create_bin_file(firmware_kobj, &of_fdt_raw_attr); + } +diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c +index 53c83d66eb7e..f104aa0383db 100644 +--- a/drivers/of/unittest.c ++++ b/drivers/of/unittest.c +@@ -923,6 +923,7 @@ static int __init unittest_data_add(void) + of_fdt_unflatten_tree(unittest_data, NULL, &unittest_data_node); + if (!unittest_data_node) { + pr_warn("%s: No tree to attach; not running tests\n", __func__); ++ kfree(unittest_data); + return -ENODATA; + } + of_node_set_flag(unittest_data_node, OF_DETACHED); +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 7dc726d7fbde..cf8abba83a5c 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -490,4 +490,16 @@ config PHY_NS2_PCIE + help + Enable this to support the Broadcom Northstar2 PCIe PHY. + If unsure, say N. ++ ++config PHY_SSTAR_INFINITY6E ++ tristate "Sigmastar USB PHY Driver" ++ depends on ARCH_INFINITY6E ++ select GENERIC_PHY ++ default ARCH_INFINITY6E ++ help ++ Enable this to support Sigmastar USB PHY driver for Sigmastar ++ SoC. This driver will do the PHY initialization and shutdown. ++ The PHY driver will be used by Sigmastar USB3.0 driver. ++ ++ To compile this driver as a module, choose M here. + endmenu +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index a534cf5be07d..8df2620d3d27 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o + obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o + obj-$(CONFIG_ARCH_TEGRA) += tegra/ + obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o ++obj-$(CONFIG_PHY_SSTAR_INFINITY6E) += phy-infinity6e-sata.o +diff --git a/drivers/phy/phy-infinity6e-sata.c b/drivers/phy/phy-infinity6e-sata.c +new file mode 100755 +index 000000000000..5a09047cca55 +--- /dev/null ++++ b/drivers/phy/phy-infinity6e-sata.c +@@ -0,0 +1,421 @@ ++/* ++ * Copyright (c) 2014 Linaro Ltd. ++ * Copyright (c) 2014 Hisilicon Limited. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../drivers/sstar/include/ms_platform.h" ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define MS_IO_OFFSET 0xDE000000 ++ ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define GET_REG16_ADDR(x, y) ((x) + ((y) << 2)) ++#define GET_REG8_ADDR(x, y) ((x) + ((y) << 1) - ((y) & 1)) ++ ++#define RIU_BASE 0x1F200000 ++#define UTMI_BASE_ADDR GET_BASE_ADDR_BY_BANK(RIU_BASE, 0x42100) //utmi0 BK:x1421 ++/* macro to get at MMIO space when running virtually */ ++#define IO_ADDRESS(x) ( (u32)(x) + MS_IO_OFFSET ) ++ ++/* read register by word */ ++#define ms_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++ ++/* write register by word */ ++#define ms_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++ ++#define INREG16(x) ms_readw(x) ++#define OUTREG16(x, y) ms_writew((u16)(y), x) ++ ++#define DEBUG_BUS 0 ++#define MAX_TX_VOL_OPT 9 ++ ++struct infinity6e_priv { ++ void __iomem *base; ++}; ++ ++enum phy_speed_mode { ++ SPEED_MODE_GEN1 = 0, ++ SPEED_MODE_GEN2 = 1, ++ SPEED_MODE_GEN3 = 2, ++}; ++ ++struct tx_voltage_settings { ++ u16 reg_biasi; ++ u16 reg_drv; ++ u16 reg_dem; ++ char *descript; ++}; ++ ++static struct tx_voltage_settings tx_voltage_array[MAX_TX_VOL_OPT] = { ++ {0x0B, 0x22, 0x0E, "Va0.80_Vb0.53_De_m3.5dB"}, /* Va 0.80, Vb 0.53, De-emphasis -3.5dB */ ++ {0x0D, 0x26, 0x0F, "Va0.90_Vb0.60_De_m3.5dB"}, /* Va 0.90, Vb 0.60, De-emphasis -3.5dB */ ++ {0x0F, 0x2A, 0x11, "Va1.00_Vb0.67_De_m3.5dB"}, /* Va 1.00, Vb 0.67, De-emphasis -3.5dB (recommended) */ ++ {0x0F, 0x2E, 0x13, "Va1.10_Vb0.65_De_m3.5dB"}, /* Va 1.10, Vb 0.65, De-emphasis -3.5dB (recommended, default) */ ++ {0x0F, 0x2B, 0x13, "Va1.05_Vb0.67_De_m3.9dB"}, /* Va 1.05, Vb 0.67, De-emphasis -3.9dB (recommended) */ ++ {0x0F, 0x2C, 0x15, "Va1.09_Vb0.67_De_m4.2dB"}, /* Va 1.09, Vb 0.67, De-emphasis -4.2dB (recommended) */ ++ {0x0F, 0x29, 0x13, "Va1.00_Vb0.63_De_m4.0dB"}, /* Va 1.00, Vb 0.63, De-emphasis -4.0dB */ ++ {0x0F, 0x28, 0x15, "Va1.00_Vb0.59_De_m4.6dB"}, /* Va 1.00, Vb 0.59, De-emphasis -4.6dB */ ++ {0x0F, 0x32, 0x14, "Va1.20_Vb0.60_De_m3.5dB"}, /* Va 1.20, Vb 0.60, De-emphasis -3.5dB (NOT recommended) */ ++}; ++static u8 m_TxVoltageIdx = 3; /* Va 1.10, Vb 0.65, De-emphasis -3.5dB (recommended, default) */ ++ ++static ssize_t tx_voltage_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 index = 0; ++ ++ index = simple_strtoul(buf, NULL, 10); ++ if (index < MAX_TX_VOL_OPT) { ++ m_TxVoltageIdx = index; ++ } ++ else { ++ dev_err(dev, "invalid index for tx voltage %d\n", index); ++ } ++ ++ return count; ++} ++ ++static ssize_t tx_voltage_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i; ++ ++ for (i = 0; i < MAX_TX_VOL_OPT; i++) ++ { ++ if (i != m_TxVoltageIdx) { ++ str += scnprintf(str, end - str, "%2d:%s\n", i, tx_voltage_array[i].descript); ++ } ++ else { ++ str += scnprintf(str, end - str, "%2d:%s <= current\n", i, tx_voltage_array[i].descript); ++ } ++ } ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(tx_voltage, 0644, tx_voltage_show, tx_voltage_store); ++ ++static void trim_ic_verify(void) ++{ ++ u16 val, tmp; ++ ++ val = (INREG16(GET_REG16_ADDR(0x1f203000, 0x5D)) >> 11 ) & 0x001F; ++ tmp = INREG16(GET_REG16_ADDR(0x1f203000, 0x5E)) & 0x0001; ++ val = val | (tmp << 5); ++ ++ if (val != ((INREG16(0x1f2a4600 + 0x50*4) & 0xfc00) >> 10)) { ++ goto not_trim; ++ } ++ ++ val = (INREG16(GET_REG16_ADDR(0x1f203000, 0x5D)) >> 6 ) & 0x001F; ++ ++ if (val != ((INREG16(0x1f2a4600 + 0x3c*4) & 0x01f0) >> 4)) { ++ goto not_trim; ++ } ++ ++ val = (INREG16(GET_REG16_ADDR(0x1f203000, 0x5D)) >> 1 ) & 0x001F; ++ ++ if (val != ((INREG16(0x1f2a4600 + 0x2a*4) & 0x0f80) >> 7)) { ++ goto not_trim; ++ } ++ ++ printk("IC is Trim\n"); ++ return; ++not_trim: ++ printk("IC is not Trim, apply default setting\n"); ++ CLRREG16(0x1f2a4600 + 0x2a*4, 0x1f << 7); ++ SETREG16(0x1f2a4600 + 0x2a*4, 0x800); ++ ++ CLRREG16(0x1f2a4600 + 0x3c*4, 0x1f << 4); ++ SETREG16(0x1f2a4600 + 0x3c*4, 0x100); ++ ++ CLRREG16(0x1f2a4600 + 0x50*4, 0x3f << 10); ++ SETREG16(0x1f2a4600 + 0x50*4, 0x8000); ++} ++ ++void phy_utmi_reset(void) ++{ ++ SETREG16(0x1f28420c, 0x0103); // bit0: RX sw reset; bit1: Tx sw reset; bit8: Tx FSM sw reset; ++ SETREG16(0x1f284220, 0x1000); // bit12: pwr good reset ++ mdelay(1); ++ // clear reset ++ CLRREG16(0x1f28420c, 0x0103); // bit0: RX sw reset; bit1: Tx sw reset; bit8: Tx FSM sw reset; ++ CLRREG16(0x1f284220, 0x1000); // bit12: pwr good reset ++} ++EXPORT_SYMBOL(phy_utmi_reset); ++ ++static void phy_utmi_deinit(struct phy *phy) ++{ ++ phy_utmi_reset(); ++ // power down utmi ++ OUTREG16(0x1f284200, 0x7F03); ++ mdelay(5); ++} ++ ++static int phy_infinity6e_sata_init(struct phy *phy) ++{ ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4phy_bank[3]; ++ unsigned int dphy_base, aphy_base0, aphy_base1; ++ ++ of_property_read_u32(phy->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(phy->dev.of_node, "banks", (unsigned int*)u4phy_bank, 3); ++ ++ dphy_base = BANK_TO_ADDR32(u4phy_bank[0])+u4IO_PHY_BASE ; ++ aphy_base0 = BANK_TO_ADDR32(u4phy_bank[1])+u4IO_PHY_BASE ; ++ aphy_base1 = BANK_TO_ADDR32(u4phy_bank[2])+u4IO_PHY_BASE ; ++ ++ printk("Infinity6e PHY init, d-phy:%x, a-phy0:%x, a-phy1:%x\n", dphy_base, aphy_base0, aphy_base1); ++ printk("-Tx cur[%d]: %s\n", m_TxVoltageIdx, tx_voltage_array[m_TxVoltageIdx].descript); ++ ++ phy_utmi_deinit(phy); ++ ++ // For debug test ++#if DEBUG_BUS ++ OUTREG32((BANK_TO_ADDR32(0x1a21)+u4IO_PHY_BASE) + 0x1c*4, 0x40000); ++ SETREG16(aphy_base0 + 0x0d*4, 0x100); ++ ////SETREG16(aphy_base0 + 0x0c*4, 0x2); ++ SETREG16(dphy_base + 0x44*4, 0x80); ++ SETREG16(dphy_base + 0x25*4, 0x10); ++ SETREG16((BANK_TO_ADDR32(0x1436)+u4IO_PHY_BASE) + 0x1*4, 0x8); ++ SETREG16((BANK_TO_ADDR32(0x1433)+u4IO_PHY_BASE) + 0x20*4, 0x7); ++ SETREG16((BANK_TO_ADDR32(0x101e)+u4IO_PHY_BASE) + 0x75*4, 0x4000); ++ SETREG16((BANK_TO_ADDR32(0x101e)+u4IO_PHY_BASE) + 0x77*4, 0x1b); ++ SETREG16((BANK_TO_ADDR32(0x101e)+u4IO_PHY_BASE) + 0x12*4, 0x10); ++ // Done for debug test ++ ++ // ck debug ++ //SETREG16((BANK_TO_ADDR32(0x1436)+u4IO_PHY_BASE) + 0x1*4, 0x8); ++ //SETREG16((BANK_TO_ADDR32(0x1433)+u4IO_PHY_BASE) + 0x20*4, 0x7); ++#endif ++ ++ CLRREG16(0x1F284204, 0x80); ++ SETREG16(0x1F284224, 0x8000); ++ // Unmask USB30_gp2top interrupt ++ CLRREG16(0x1F286684, 0x02); ++ ++ /* Sigmastar Infinity6e USB3.0 PHY initialization */ ++ trim_ic_verify(); ++ /* Trim items provided by Dylan */ ++ // 1. TX R50 ++ SETREG16(dphy_base + 0x0b*4, 0x10); // rg_force_tx_imp_sel ++ // 2. RX R50 ++ SETREG16(dphy_base + 0x0e*4, 0x04); // rg_force_rx_imp_sel ++ // 3. BGR INTR ++ SETREG16(dphy_base + 0x46*4, 0x2000); // rg_force_iext_intr_ctrl ++ ++ CLRREG16(dphy_base + 0x26*4, 0x0E); ++ SETREG16(dphy_base + 0x26*4, tx_voltage_array[m_TxVoltageIdx].reg_biasi); ++ ++ CLRREG16(aphy_base0 + 0x44*4, 0x01); ++ mdelay(1); ++ CLRREG16(aphy_base0 + 0x40*4, 0xffff); ++ SETREG16(aphy_base0 + 0x40*4, 0xb6a7); ++ CLRREG16(aphy_base0 + 0x41*4, 0xff); ++ SETREG16(aphy_base0 + 0x41*4, 0x1b); ++ CLRREG16(aphy_base0 + 0x42*4, 0xfff); ++ SETREG16(aphy_base0 + 0x42*4, 0x4); ++ CLRREG16(aphy_base0 + 0x43*4, 0x7fff); ++ SETREG16(aphy_base0 + 0x43*4, 0x3ee); ++ SETREG16(aphy_base0 + 0x44*4, 0x110); ++ mdelay(1); ++ SETREG16(aphy_base0 + 0x44*4, 0x01); ++ ++ CLRREG16(dphy_base + 0x34*4, 0x4000); // RG_SSUSB_LFPS_PWD[14] = 0 // temp add here ++ SETREG16(aphy_base1 + 0x20*4, 0x04); ++ CLRREG16(aphy_base1 + 0x25*4, 0xffff); ++ // Enable ECO ++ CLRREG16(aphy_base0 + 0x03*4, 0x0f); ++ SETREG16(aphy_base0 + 0x03*4, 0x0d); ++ // Turn on TX PLL ++ CLRREG16(aphy_base0 + 0x20*4, 0x01); // reg_sata_pd_txpll[0] = 0 ++ // Turn on RX PLL ++ CLRREG16(aphy_base0 + 0x30*4, 0x01); // reg_sata_pd_rxpll[0] = 0 ++ mdelay(1); ++ // De-assert USB PHY reset ++ SETREG16(aphy_base1 + 0x00*4, 0x10); // reg_ssusb_phy_swrst[4] = 1 ++ // Toggle synthesizer to turn on PLL reference clock input ++ SETREG16(aphy_base0 + 0x44*4, 0x01); // reg_sata_phy_synth_sld[0] = 1 ++ // Diable RXPLL frequency lock detection hardware mode ++ OUTREG16(dphy_base + 0x40*4, ((tx_voltage_array[m_TxVoltageIdx].reg_dem & 0x0F) << 12) | ++ (tx_voltage_array[m_TxVoltageIdx].reg_drv << 6) | 0x19); ++ OUTREG16(dphy_base + 0x41*4, ((tx_voltage_array[m_TxVoltageIdx].reg_dem & 0x30) >> 4) | 0x2188); ++ SETREG16(dphy_base + 0xa*4, 0x1a); // force DA_SSUSB_TX_BIASI, DA_SSUSB_IDRV_3P5DB, DA_SSUSB_IDEM_3P5DB value ++ ++ CLRREG16(aphy_base0 + 0x54*4, 0xf); // The continue lock number to judge rxpll frequency is lock or not ++ CLRREG16(aphy_base0 + 0x73*4, 0xff); // PLL State : ++ // The lock threshold distance between predict counter number and real counter number of rxpll ++ CLRREG16(aphy_base0 + 0x77*4, 0xff); // CDR State : ++ // The lock threshold distance between predict counter number and real counter number of rxpll ++ CLRREG16(aphy_base0 + 0x56*4, 0xffff); ++ SETREG16(aphy_base0 + 0x56*4, 0x5dc0); // the time out reset reserve for PLL unlock for cdr_pd fsm PLL_MODE state waiting time ++ // default : 20us (24MHz base : 480 * 41.667ns) ++ ++ CLRREG16(aphy_base0 + 0x57*4, 0xffff); ++ SETREG16(aphy_base0 + 0x57*4, 0x1e0); // the time out reset reserve for CDR unlock ++ ++ CLRREG16(aphy_base0 + 0x70*4, 0x04); // reg_sata_phy_rxpll_det_hw_mode_always[2] = 0 ++ // Enable RXPLL frequency lock detection ++ SETREG16(aphy_base0 + 0x70*4, 0x02); // reg_sata_phy_rxpll_det_sw_enable_always[1] = 1 ++ // Enable TXPLL frequency lock detection ++ SETREG16(aphy_base0 + 0x60*4, 0x02); // reg_sata_phy_txpll_det_sw_enable_always[1] = 1 ++ // Tx polarity inverse ++ CLRREG16(aphy_base1 + 0x49*4, 0x200); ++ SETREG16(aphy_base1 + 0x49*4, 0xc4e); // reg_rx_lfps_t_burst_gap = 3150 ++ SETREG16(dphy_base + 0x12*4, 0x1000); // RG_TX_POLARITY_INV[12] = 1 ++ ++ ms_writew(0x0C2F, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x4)); ++#ifdef USB_ENABLE_UPLL ++ ms_writew(0x6BC3, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); // Turn on UPLL, reg_pdn: bit<9> reg_pdn: bit<15>, bit <2> ref_pdn ++ mdelay(1); ++ ms_writeb(0x69, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); // Turn on UPLL, reg_pdn: bit<9> ++ mdelay(2); ++ ms_writew(0x0001, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); // Turn all (including hs_current) use override mode ++ // Turn on UPLL, reg_pdn: bit<9> ++ mdelay(3); ++#else ++ // Turn on UTMI if it was powered down ++ if (0x0001 != ms_readw(GET_REG16_ADDR(UTMI_BASE_ADDR, 0))) ++ { ++ ms_writew(0x0001, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); // Turn all (including hs_current) use override mode ++ mdelay(3); ++ } ++#endif ++ ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x1E)) | 0x01), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x1E)); // set CA_START as 1 ++ mdelay(10); ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x1E)) & ~0x01), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x1E)); // release CA_START ++ while (0 == (ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x1E)) & 0x02)); // polling bit <1> (CA_END) ++ ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03)) & 0x9F) | 0x40, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03)); //reg_tx_force_hs_current_enable ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x01) + 1) | 0x28), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x01) + 1); //Disconnect window select ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x01) + 1) & 0xef), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x01) + 1); //Disconnect window select ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03) + 1) & 0xfd), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03) + 1); //Disable improved CDR ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x04) + 1) | 0x81), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x04) + 1); // UTMI RX anti-dead-loc, ISI effect improvement ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x0A) + 1) | 0x20), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x0A) + 1); // Chirp signal source select ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x05) + 1) | 0x80), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x05) + 1); // set reg_ck_inv_reserved[6] to solve timing problem ++ ++ ms_writew(0x0290, GET_REG_ADDR(UTMI_BASE_ADDR, 0x16)); ++ ms_writew(0x0110, GET_REG_ADDR(UTMI_BASE_ADDR, 0x17)); ++ ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x02)) | 0x80), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x02)); //avoid glitch ++ ++ //2020_0810: Chiyun.liu and TY request. ++ SETREG16(0x1F000000+(0x1524<<9)+(0x11<<2), 0x0020); //bit5] = 1'b1 CDR JTOL Improvement (Improve BBPD of CDR if 16'h11 bit[5] = 1'b1. Default with MTK phyA mode. ++ CLRREG16(0x1F000000+(0x1523<<9)+(0x67<<2), 0x00C0); //bit[7:6] = 2'b00 ++ SETREG16(0x1F000000+(0x1523<<9)+(0x67<<2), 0x0080); //bit[7] = 1'b1 ++ SETREG16(0x1F000000+(0x1524<<9)+(0x14<<2), 0x6000); //bit[14:13] = 2'b11 ++ //LPFS filter threshold by CK ++ SETREG16(0x1F000000+(0x1523<<9)+(0x29<<2), 0x07C0); //bit[10:6] = 5'b11111 LPFS filter threshold ++ ++ return 0; ++} ++ ++static int phy_infinity6e_sata_exit(struct phy *phy) ++{ ++ // return back the UTMI ownership ++ SETREG16(0x1F284204, 0x80); ++ phy_utmi_deinit(phy); ++ return 0; ++} ++ ++static int phy_infinity6e_sata_power_on(struct phy *phy) ++{ ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4phy_bank[3]; ++ unsigned int dphy_base, aphy_base0, aphy_base1; ++ ++ of_property_read_u32(phy->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(phy->dev.of_node, "banks", (unsigned int*)u4phy_bank, 3); ++ ++ dphy_base = BANK_TO_ADDR32(u4phy_bank[0])+u4IO_PHY_BASE ; ++ aphy_base0 = BANK_TO_ADDR32(u4phy_bank[1])+u4IO_PHY_BASE ; ++ aphy_base1 = BANK_TO_ADDR32(u4phy_bank[2])+u4IO_PHY_BASE ; ++ ++ // Tx polarity inverse ++ SETREG16(dphy_base + 0x12*4, 0x1000); // RG_TX_POLARITY_INV[12] = 1 ++ ++ return 0; ++} ++ ++static int phy_infinity6e_reset(struct phy *phy) ++{ ++ CLRREG16(0x1F000000+(0x1525<<9)+(0x00<<2), 0x0010); // reg_ssusb_phy_swrst[4] = 0 ++ SETREG16(0x1F000000+(0x1525<<9)+(0x00<<2), 0x0010); // reg_ssusb_phy_swrst[4] = 1 ++ ++ return 0; ++} ++ ++static const struct phy_ops phy_infinity6e_sata_ops = { ++ .init = phy_infinity6e_sata_init, ++ .exit = phy_infinity6e_sata_exit, ++ .power_on = phy_infinity6e_sata_power_on, ++ .reset = phy_infinity6e_reset, ++ .owner = THIS_MODULE, ++}; ++ ++static int phy_infinity6e_sata_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ struct phy *phy; ++ struct infinity6e_priv *priv; ++ ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ priv->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ ++ printk("Infinity6e PHY probe, base:%x\n", (unsigned int)priv->base); ++ ++ ++ phy = devm_phy_create(dev, NULL, &phy_infinity6e_sata_ops); ++ if (IS_ERR(phy)) { ++ dev_err(dev, "failed to create PHY\n"); ++ return PTR_ERR(phy); ++ } ++ ++ phy_set_drvdata(phy, priv); ++ device_create_file(&pdev->dev, &dev_attr_tx_voltage); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id phy_infinity6e_sata_of_match[] = { ++ {.compatible = "sstar,infinity6e-sata-phy",}, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, phy_infinity6e_sata_of_match); ++ ++static struct platform_driver phy_infinity6e_sata_driver = { ++ .probe = phy_infinity6e_sata_probe, ++ .driver = { ++ .name = "phy", ++ .of_match_table = phy_infinity6e_sata_of_match, ++ } ++}; ++module_platform_driver(phy_infinity6e_sata_driver); ++ ++MODULE_AUTHOR("Jiang Ann "); ++MODULE_DESCRIPTION("INFINITY6E SATA PHY driver"); ++MODULE_ALIAS("platform:phy-infinity6e-sata"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig +index 76806a0be820..3b706bd79983 100644 +--- a/drivers/power/supply/Kconfig ++++ b/drivers/power/supply/Kconfig +@@ -110,6 +110,14 @@ config BATTERY_DS2781 + + If you are unsure, say N. + ++config BATTERY_IP6303 ++ tristate "Injoinic IP6303 Fuel Gauge" ++ depends on I2C ++ help ++ IP6303 is fuel-gauge systems for lithium-ion (Li+) batteries ++ in handheld and portable equipment. The IP6303 is configured ++ to operate with a single lithium cell ++ + config BATTERY_DS2782 + tristate "DS2782/DS2786 standalone gas-gauge" + depends on I2C +diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile +index 36c599d9a495..26a8152d1704 100644 +--- a/drivers/power/supply/Makefile ++++ b/drivers/power/supply/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_PDA_POWER) += pda_power.o + obj-$(CONFIG_APM_POWER) += apm_power.o + obj-$(CONFIG_AXP20X_POWER) += axp20x_usb_power.o + obj-$(CONFIG_MAX8925_POWER) += max8925_power.o ++obj-$(CONFIG_BATTERY_IP6303) += ip6303_battery.o + obj-$(CONFIG_WM831X_BACKUP) += wm831x_backup.o + obj-$(CONFIG_WM831X_POWER) += wm831x_power.o + obj-$(CONFIG_WM8350_POWER) += wm8350_power.o +diff --git a/drivers/power/supply/ip6303_battery.c b/drivers/power/supply/ip6303_battery.c +new file mode 100644 +index 000000000000..7c8ddf2c0948 +--- /dev/null ++++ b/drivers/power/supply/ip6303_battery.c +@@ -0,0 +1,879 @@ ++/* ++ * ip6303_battery.c ++ * fuel-gauge systems for lithium-ion (Li+) batteries ++ * ++ * Copyright (C) 2019 SStar ++ * lei.qin ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include <../../../drivers/sstar/include/infinity6e/irqs.h> ++#include ++//#include <../../../drivers/sstar/include/infinity6e/gpio.h> ++ ++#define IP6303_VCELL_MSB 0x02 ++#define IP6303_VCELL_LSB 0x03 ++#define IP6303_SOC_MSB 0x04 ++#define IP6303_SOC_LSB 0x05 ++#define IP6303_MODE_MSB 0x06 ++#define IP6303_MODE_LSB 0x07 ++#define IP6303_VER_MSB 0x08 ++#define IP6303_VER_LSB 0x09 ++#define IP6303_RCOMP_MSB 0x0C ++#define IP6303_RCOMP_LSB 0x0D ++#define IP6303_CMD_MSB 0xFE ++#define IP6303_CMD_LSB 0xFF ++ ++#define IP6303_DELAY 1000 ++//#define IP6303_POWEROFF_DELAY 500 ++ ++#define IP6303_BATTERY_FULL 95 ++ ++#define IP6303_MAX_V 4300 ++#define IP6303_PF_NOTIFY 4000 //poweroff notify ++#define IP6303_MIN_V 3600 ++#define IP6303_POFF_PERC 50 //less than 40% ++#define IP6303_CHK_CNT 2 //above 2 times in less than 40% ++ ++struct ip6303_chip { ++ struct i2c_client *client; ++ struct delayed_work work; ++ struct power_supply *battery; ++ struct ip6303_platform_data *pdata; ++ unsigned int irq; // IRQ number ++ ++ /* State Of Connect */ ++ int online; ++ /* battery voltage */ ++ int vcell; ++ /* battery capacity */ ++ int soc; ++ /* State Of Charge */ ++ int status; ++ /* State Of Charge Enable */ ++ int chargEn; ++ /* check Of battery exit */ ++ int assembleBat; ++ /* force to update all status */ ++ int updateAll; ++ /* long press status */ ++ int longPress; ++ ++ int BatLowLoopCnt; ++}; ++ ++struct ip6303_chip *g_chip; ++ ++static int ip6303_write_reg(struct i2c_client *client, int reg, u8 value) ++{ ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, reg, value); ++ ++ if (ret < 0) ++ dev_err(&client->dev, "%s: err %d\n", __func__, ret); ++ ++ return ret; ++} ++ ++static int ip6303_read_reg(struct i2c_client *client, int reg) ++{ ++ int ret; ++ ++ ret = i2c_smbus_read_byte_data(client, reg); ++ ++ if (ret < 0) ++ dev_err(&client->dev, "%s: err %d\n", __func__, ret); ++ ++ return ret; ++} ++ ++static void ip6303_reset(struct i2c_client *client) ++{ ++#if defined(IP_PMU_WATCH_DOG_ENABLE) && (IP_PMU_WATCH_DOG_ENABLE) ++ int returnvalue; ++ IP6303WDogCtl_U uWDogCtl; ++ ++ uWDogCtl.uData = (unsigned int)ip6303_read_reg(client,WDOG_CTL); ++ ++ uWDogCtl.tFlag.bIsWDogEn = 0; ++ uWDogCtl.tFlag.bTimerClr = 1; ++ ip6303_write_reg(client,WDOG_CTL, (u8)uWDogCtl.uData); ++ ++ uWDogCtl.tFlag.uTimerType = 0; ++ uWDogCtl.tFlag.bTimerClr = 0; ++ uWDogCtl.tFlag.bIsWDogEn = 1; ++ returnvalue = ip6303_write_reg(client,WDOG_CTL, (u8)uWDogCtl.uData); ++ printk(KERN_NOTICE "%s: uWDogCtl.uData= %d\n", __func__, uWDogCtl.uData); ++ ++#endif ++} ++ ++void IP6303_Initialize(struct i2c_client *client) ++{ ++ IpIntsCtl_U uIntsCtl = {0}; ++ IpIntrMask0_U uIntrMask0 = {0}; ++ IpChgDigCtl3_U uChgDigCtl3 = {0}; ++ IpAdcAnaCtl0_U uAdcAnaCtl0 = {0}; ++ unsigned int stu0,stu1,stu2; ++ u8 u8PwrEn, u8val, i; ++ int err; ++ u32 val; ++ char nam[16]={0}; ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ stu0 = ip6303_read_reg(client,PWROFF_REC0); ++ stu1 = ip6303_read_reg(client,PWROFF_REC1); ++ stu2 = ip6303_read_reg(client,PWROFF_REC2); ++ printk(KERN_NOTICE "%s,PWROFF_REC[0x%02x,0x%02x,0x%02x]\n", __func__,stu0,stu1,stu2); ++ ++ //OK_SET=4.3V,VBUSOCH_SET>=2A ++ ip6303_write_reg(client,PROTECT_CTL4, 0x3C); ++ ++ uIntsCtl.uData = (unsigned int)ip6303_read_reg(client,INTS_CTL); ++ uIntsCtl.tFlag.bIrqPolHighValid = PMU_IRQ_ACT_LEVEL; ++ ip6303_write_reg(client,INTS_CTL, uIntsCtl.uData); ++ ++ //Intr Cfg -- INTR MASK ++ uIntrMask0.uData = 0xFF; ++ uIntrMask0.tFlag.bShortPressOnOff = IP_PMU_INTR_UNMASK; ++ uIntrMask0.tFlag.bLongPressOnOff = IP_PMU_INTR_UNMASK; ++ uIntrMask0.tFlag.bVBusIn = IP_PMU_INTR_UNMASK; ++ uIntrMask0.tFlag.bVBusOut = IP_PMU_INTR_UNMASK; ++ uIntrMask0.tFlag.bLowBat = IP_PMU_INTR_UNMASK; ++ ip6303_write_reg(client,INTR_MASK_0, uIntrMask0.uData); ++ ++ for(i = 1; i <= 3; i++){ ++ sprintf(nam,"DC%d_VSET",i); ++ err = of_property_read_u32(client->dev.of_node, nam, &val); ++ if((err < 0) && (val < 3600) && (val > 600)){ ++ dev_err(&client->dev, "dts can't find %s\n",nam); ++ }else{ ++ u8val = (u8)((val-600)*10/125 & 0xff);//0.6V~3.6V=>0000_0000~1111_0000,step=12.5mv ++ printk(KERN_NOTICE "dts find %s=%dmV,0x%02x\n",nam,val,u8val); ++ ip6303_write_reg(client,DC1_VSET+(i-1)*5, u8val); ++ } ++ } ++ ++ memset(nam,0,sizeof(nam)); ++ for(i = 2; i <= 5; i++){ ++ sprintf(nam,"LDO%d_VSET",i); ++ err = of_property_read_u32(client->dev.of_node, nam, &val); ++ if((err < 0) && (val < 3400) && (val > 700)){ ++ dev_err(&client->dev, "dts can't find %s\n",nam); ++ }else{ ++ u8val = (u8)(((val-700)/25) & 0xff);//0.7V~3.4V=>0000_0000~0110_1100,step=25mv ++ printk(KERN_NOTICE "dts find %s=%dmV,0x%02x\n",nam,val,u8val); ++ ip6303_write_reg(client,LDO2_VSET+i-2, u8val); ++ u8PwrEn |= (1 << i); ++ } ++ } ++ //dev_err(&client->dev, "LDO_EN =0x%02x\n",u8PwrEn); ++ //ENABLE:LDO2&LDO3&LDO4&LDO5 ++ ip6303_write_reg(client,LDO_EN, u8PwrEn); ++ ++ ip6303_write_reg(client,CHG_ANA_CTL0, 0X21); //fast charge:28mV EN_ISTOP=enable ++ ip6303_write_reg(client,PSTATE_SET, 0X80); //S2S3_DELAY=8mS ++ ++ //clear all irq status ++ ip6303_write_reg(client,INTR_FLAG_0, 0xFF); ++ ++ //enable voltage ADC ++ uAdcAnaCtl0.uData = (unsigned int)ip6303_read_reg(client,ADC_ANA_CTL0); ++ uAdcAnaCtl0.tFlag.bEnVBatAdc = 1; ++ ip6303_write_reg(client,ADC_ANA_CTL0, (u8)uAdcAnaCtl0.uData); ++ msleep(10); ++ ++ //enable charging ++ uChgDigCtl3.uData = (unsigned int)ip6303_read_reg(client,CHG_DIG_CTL3); ++ uChgDigCtl3.tFlag.bEnChg = 1; ++ chip->chargEn = 1; ++ ip6303_write_reg(client,CHG_DIG_CTL3, (u8)uChgDigCtl3.uData); ++ ++ #if defined(IP_PMU_WATCH_DOG_ENABLE) && (IP_PMU_WATCH_DOG_ENABLE) ++ { ++ //´ò¿ª¿´ÃŹ· ++ IP6303WDogCtl_U uWDogCtl = {0}; ++ //returnvalue = IP_IP6303_ReadReg(WDOG_CTL, (MMP_USHORT*)&(uWDogCtl.uData)); ++ uWDogCtl.uData = (unsigned int)ip6303_read_reg(client,WDOG_CTL); ++ uWDogCtl.tFlag.uTimerType = 3; ++ uWDogCtl.tFlag.bIsWDogEn = 1; ++ //returnvalue = IP_IP6303_WriteReg(WDOG_CTL, uWDogCtl.uData); ++ ip6303_write_reg(client,WDOG_CTL, (u8)uWDogCtl.uData); ++ } ++ #endif ++} ++ ++static void ip6303_charge_en(struct i2c_client *client,bool en) ++{ ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ IpChgDigCtl3_U uChgDigCtl3 = {0}; ++ ++ chip->chargEn = en; ++ //enable charging ++ uChgDigCtl3.uData = (unsigned int)ip6303_read_reg(client,CHG_DIG_CTL3); ++ uChgDigCtl3.tFlag.bEnChg = en; ++ ip6303_write_reg(client,CHG_DIG_CTL3, (u8)uChgDigCtl3.uData); ++} ++ ++static void ip6303_power_off(struct i2c_client *client) ++{ ++ IPPStateCtl0_U uPStateCtl0 = {0}; ++ ++ ip6303_charge_en(client,0);//disable charging ++ ++ uPStateCtl0.uData = ip6303_read_reg(client,PSTATE_CTL0); ++ uPStateCtl0.tFlag.bIrqWkEn = 1; ++ uPStateCtl0.tFlag.bSOnoffWkEn = 1; //DR0010¶Ì°´²»¿ª»ú, ¶Ì°´²»¿ª»ú»áµ¼ÖÂÍ£³µ¼à¿ØÎÞ·¨¿ª»ú ++ uPStateCtl0.tFlag.bLOnoffWkEn = 1; ++ uPStateCtl0.tFlag.bPwrOffEn = 0; ++ uPStateCtl0.tFlag.bVBusWkEn = 0; ++ ip6303_write_reg(client,PSTATE_CTL0, (u8)uPStateCtl0.uData); ++ msleep(2); ++ uPStateCtl0.tFlag.bPwrOffEn = 1; ++ ++ while(1) ++ { ++ printk(KERN_NOTICE "********IP6303:SHUT DOWN*******\n\n"); ++ ip6303_write_reg(client,PSTATE_CTL0, (u8)uPStateCtl0.uData); ++ msleep(2); ++ } ++} ++ ++static void ip6303_poweroff_enter(void) ++{ ++ ip6303_power_off(g_chip->client); ++} ++ ++static void ip6303_get_vcell(struct i2c_client *client) ++{ ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ u32 ubValue, uVoltage; ++ ++ //Get VBAT,Uint:mV ++ ubValue = (u32)ip6303_read_reg(client, ADC_DATA_VBAT); ++ uVoltage = ubValue*15625 +500000+ 15625/2; ++ uVoltage /= 1000; ++ printk(KERN_INFO "\n%s dev-reg[%x,0x64],V:%dmV\n", __func__,client->addr,uVoltage); ++ chip->vcell = uVoltage; ++} ++ ++static void ip6303_get_soc(struct i2c_client *client) ++{ ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ int charging = chip->chargEn; ++ IpChgDigCtl3_U uChgDigCtl3 = {0}; ++ ++ if(chip->vcell < IP6303_MIN_V){ ++ chip->soc = 0; ++ chip->BatLowLoopCnt ++; ++ } ++ else if (chip->vcell > IP6303_MAX_V){ ++ chip->soc = 100; ++ chip->chargEn = 0; ++ chip->BatLowLoopCnt = 0; ++ } ++ else{ ++ chip->soc = (chip->vcell - IP6303_MIN_V) *100 / (IP6303_MAX_V - IP6303_MIN_V); ++ if(chip->soc < IP6303_POFF_PERC){ ++ chip->BatLowLoopCnt ++; ++ } ++ else{ ++ (chip->BatLowLoopCnt > 0)? (chip->BatLowLoopCnt--):(chip->BatLowLoopCnt = 0); ++ } ++ } ++ ++ if(charging != chip->chargEn){ ++ printk(KERN_INFO "%s chargEn=%d\n", __func__,chip->chargEn);// ++ ++ uChgDigCtl3.uData = (unsigned int)ip6303_read_reg(client,CHG_DIG_CTL3); ++ uChgDigCtl3.tFlag.bEnChg = (chip->chargEn)? 1:0; ++ ip6303_write_reg(client,CHG_DIG_CTL3, (u8)uChgDigCtl3.uData); ++ } ++} ++ ++static void ip6303_get_version(struct i2c_client *client) ++{ ++ u8 msb; ++ u8 lsb; ++ ++ msb = 0x11; ++ lsb = 0x22; ++ printk(KERN_INFO "TODO::IP6303 Fuel-Gauge Ver %d%d\n", msb, lsb); ++} ++ ++static void ip6303_get_battery_assemble(struct i2c_client *client) ++{ ++ int RegIntFlag0; ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ //enable to check ++ RegIntFlag0 = ip6303_read_reg(client, PSTATE_CTL3); ++ ip6303_write_reg(client, PSTATE_CTL3,RegIntFlag0|BIT0); ++ ++ //Get BAT ext status ++ RegIntFlag0 = ip6303_read_reg(client,CHG_DIG_CTL2); ++ if(RegIntFlag0 & BIT3) ++ chip->assembleBat = 1; ++} ++ ++static void ip6303_get_init_online(struct i2c_client *client) ++{ ++ int RegIntFlag0; ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ RegIntFlag0 = ip6303_read_reg(client, INTR_FLAG_0); ++ ip6303_write_reg(client, INTR_FLAG_0,RegIntFlag0); //clear flag ++ //printk(KERN_INFO "TODO::%s RegIntFlag0=0x%x\n", __func__, RegIntFlag0); ++ ++ if(!(RegIntFlag0 & (BIT0|BIT1))){ //long press && short press issue ++ chip->online = RegIntFlag0 & BIT3; //plug in ++ } ++ ++ //REF:IP6303_SoftwareApplication_User's_Guide_Vxxx.PDF ++ //How to judge VBUS status. ++ RegIntFlag0 = ip6303_read_reg(client,CHG_DIG_CTL1); ++ printk(KERN_INFO "TODO::%s reg0x54=0x%x\n", __func__, RegIntFlag0); ++ if(RegIntFlag0) ++ chip->online = 1; ++ ++ #if 0 ++ else{ ++ RegIntFlag0 = ip6303_read_reg(client,ADC_ANA_CTL0); ++ RegIntFlag0 |= BIT2; //enable current check ++ ip6303_write_reg(client, ADC_ANA_CTL0,RegIntFlag0); ++ RegIntFlag0 = ip6303_read_reg(client,ADC_DATA_ICHG); ++ RegIntFlag0 = (RegIntFlag0*15625-750000+15625/2)/3; ++ chip->online = 1; ++ } ++ #endif ++} ++ ++static void ip6303_get_online(struct i2c_client *client) ++{ ++ int RegIntFlag0; ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ RegIntFlag0 = ip6303_read_reg(client, INTR_FLAG_0); ++ ip6303_write_reg(client, INTR_FLAG_0,RegIntFlag0); //clear flag ++ ++ chip->online = RegIntFlag0 & BIT3;//plug in ++ if(chip->online){ ++ printk(KERN_INFO "TODO::%s online***\n", __func__); ++ } ++ ++ chip->longPress = RegIntFlag0 & (BIT1|BIT0); //power-key:short press & long press ++} ++ ++static void ip6303_get_status(struct i2c_client *client) ++{ ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ if(chip->online) { ++ if (chip->chargEn) ++ chip->status = POWER_SUPPLY_STATUS_CHARGING; ++ else ++ chip->status = POWER_SUPPLY_STATUS_NOT_CHARGING; ++ } else { ++ chip->status = POWER_SUPPLY_STATUS_DISCHARGING; ++ } ++ ++ if(chip->soc > IP6303_BATTERY_FULL) ++ chip->status = POWER_SUPPLY_STATUS_FULL; ++ ++} ++ ++static void ip6303_get_all(struct i2c_client *client) ++{ ++ ip6303_get_vcell(client); ++ ip6303_get_soc(client); ++ ip6303_get_online(client); ++ ip6303_get_status(client); ++} ++ ++static int ip6303_get_property(struct power_supply *psy, ++ enum power_supply_property psp, ++ union power_supply_propval *val) ++{ ++ struct ip6303_chip *chip = power_supply_get_drvdata(psy); ++ ++ if(chip->updateAll){ ++ chip->updateAll = 0; ++ ip6303_get_all(chip->client); ++ ++ if((chip->vcell < IP6303_PF_NOTIFY) || (chip->longPress)){ ++ chip->longPress = 0; ++ kernel_power_off(); ++ } ++ } ++ ++ switch (psp) { ++ case POWER_SUPPLY_PROP_STATUS: ++ val->intval = chip->status; ++ break; ++ case POWER_SUPPLY_PROP_ONLINE: ++ val->intval = chip->online; ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_NOW: ++ val->intval = chip->vcell; ++ break; ++ case POWER_SUPPLY_PROP_CAPACITY: ++ val->intval = chip->soc; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ printk(KERN_NOTICE "%s,psp:%d,val:%d\n",__func__,psp,val->intval); ++ return 0; ++} ++ ++static irqreturn_t ip6303_isr(int irq, void* data) ++{ ++ struct ip6303_chip *chip = (struct ip6303_chip *)data; ++ //struct i2c_client *client = chip->client; ++ ++ printk(KERN_INFO "TODO::%s[%d,0x%08x]**********\n", __func__,irq,(u32)data); ++ chip->updateAll = 1; ++ power_supply_changed(chip->battery); ++ ++ return IRQ_HANDLED; ++} ++ ++static void ip6303_work(struct work_struct *work) ++{ ++ struct ip6303_chip *chip; ++ struct i2c_client *client; ++ int oldsoc, oldchargEn,oldonline; ++ ++ chip = container_of(work, struct ip6303_chip, work.work); ++ client = chip->client; ++ oldsoc = chip->soc; ++ oldchargEn = chip->chargEn; ++ oldonline = chip->online; ++ ++ ip6303_get_vcell(client); ++ ip6303_get_soc(client); ++ //ip6303_get_online(client); ++ ip6303_get_status(client); ++ ++ if((oldsoc != chip->soc)||(oldchargEn != chip->chargEn)||(oldonline != chip->online)) ++ power_supply_changed(chip->battery); ++ ++ if((chip->soc < IP6303_POFF_PERC) && (chip->BatLowLoopCnt > IP6303_CHK_CNT)){ ++ printk(KERN_INFO "********TODO:NOTIFY SYSTEM,POWEROFF*******\n\n"); ++ kernel_power_off(); ++ } ++ ++ queue_delayed_work(system_power_efficient_wq, &chip->work,IP6303_DELAY); ++} ++ ++static u32 ip6303_getValue(struct device *dev,int reg) ++{ ++ int regValue=0; ++ u32 value=0; ++ struct i2c_client *client = to_i2c_client(dev); ++ switch(reg) ++ { ++ case DC1_VSET: ++ regValue=ip6303_read_reg(client, DC1_VSET); ++ value=(((regValue&0xff)*125/10)+600); ++ break; ++ case DC2_VSET: ++ regValue=ip6303_read_reg(client, DC2_VSET); ++ value=(((regValue&0xff)*125/10)+600); ++ break; ++ case DC3_VSET: ++ regValue=ip6303_read_reg(client, DC3_VSET); ++ value=(((regValue&0xff)*125/10)+600); ++ break; ++ case LDO2_VSET: ++ regValue=ip6303_read_reg(client, LDO2_VSET); ++ value=(((regValue&0xff)*25)+700); ++ break; ++ case LDO3_VSET: ++ regValue=ip6303_read_reg(client, LDO3_VSET); ++ value=(((regValue&0xff)*25)+700); ++ break; ++ case LDO4_VSET: ++ regValue=ip6303_read_reg(client, LDO4_VSET); ++ value=(((regValue&0xff)*25)+700); ++ break; ++ case LDO5_VSET: ++ regValue=ip6303_read_reg(client, LDO5_VSET); ++ value=(((regValue&0xff)*25)+700); ++ break; ++ default: ++ printk("reg error!!\n"); ++ } ++ ++ return value; ++} ++static ssize_t ip6303_battery_DC1_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,DC1_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_DC1_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3600) && (value < 600)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)((value-600)*10/125 & 0xff);//0.6V~3.6V=>0000_0000~1111_0000,step=12.5mv ++ ip6303_write_reg(client,DC1_VSET, u8val); ++ } ++ return count; ++} ++static ssize_t ip6303_battery_DC2_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,DC2_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_DC2_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3600) && (value < 600)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)((value-600)*10/125 & 0xff);//0.6V~3.6V=>0000_0000~1111_0000,step=12.5mv ++ ip6303_write_reg(client,DC2_VSET, u8val); ++ } ++ return count; ++} ++static ssize_t ip6303_battery_DC3_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,DC3_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_DC3_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3600) && (value < 600)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)((value-600)*10/125 & 0xff);//0.6V~3.6V=>0000_0000~1111_0000,step=12.5mv ++ ip6303_write_reg(client,DC3_VSET, u8val); ++ } ++ return count; ++} ++static ssize_t ip6303_battery_LDO2_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,LDO2_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_LDO2_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3400) && (value < 700)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)(((value-700)/25) & 0xff);//0.7V~3.4V=>0000_0000~0110_1100,step=25mv ++ ip6303_write_reg(client,LDO2_VSET, u8val); ++ } ++ return count; ++} ++static ssize_t ip6303_battery_LDO3_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,LDO3_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_LDO3_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3400) && (value < 700)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)(((value-700)/25) & 0xff);//0.7V~3.4V=>0000_0000~0110_1100,step=25mv ++ ip6303_write_reg(client,LDO3_VSET, u8val); ++ } ++ return count; ++} ++ ++static ssize_t ip6303_battery_LDO4_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,LDO4_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_LDO4_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3400) && (value < 700)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)(((value-700)/25) & 0xff);//0.7V~3.4V=>0000_0000~0110_1100,step=25mv ++ ip6303_write_reg(client,LDO4_VSET, u8val); ++ } ++ return count; ++} ++ ++static ssize_t ip6303_battery_LDO5_show(struct device *dev,struct device_attribute *attr, char *buf) ++{ ++ int ret; ++ u32 value=0; ++ value=ip6303_getValue(dev,LDO5_VSET); ++ ret = sprintf(buf, "%d\n", value); ++ return ret; ++} ++static ssize_t ip6303_battery_LDO5_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ u8 u8val; ++ int value,ret; ++ struct i2c_client *client = to_i2c_client(dev); ++ ret=kstrtoint(buf, 10, &value); ++ if((value > 3400) && (value < 700)){ ++ printk( "%d is out of range!!\n",value); ++ }else{ ++ u8val = (u8)(((value-700)/25) & 0xff);//0.7V~3.4V=>0000_0000~0110_1100,step=25mv ++ ip6303_write_reg(client,LDO5_VSET, u8val); ++ } ++ return count; ++} ++ ++ ++static DEVICE_ATTR(DC1_VSET, 0660, ip6303_battery_DC1_show, ip6303_battery_DC1_store); ++static DEVICE_ATTR(DC2_VSET, 0660, ip6303_battery_DC2_show, ip6303_battery_DC2_store); ++static DEVICE_ATTR(DC3_VSET, 0660, ip6303_battery_DC3_show, ip6303_battery_DC3_store); ++static DEVICE_ATTR(LDO2_VSET, 0660, ip6303_battery_LDO2_show, ip6303_battery_LDO2_store); ++static DEVICE_ATTR(LDO3_VSET, 0660, ip6303_battery_LDO3_show, ip6303_battery_LDO3_store); ++static DEVICE_ATTR(LDO4_VSET, 0660, ip6303_battery_LDO4_show, ip6303_battery_LDO4_store); ++static DEVICE_ATTR(LDO5_VSET, 0660, ip6303_battery_LDO5_show, ip6303_battery_LDO5_store); ++ ++static struct attribute *ip6303_attributes[] = { ++ &dev_attr_DC1_VSET.attr, ++ &dev_attr_DC2_VSET.attr, ++ &dev_attr_DC3_VSET.attr, ++ &dev_attr_LDO2_VSET.attr, ++ &dev_attr_LDO3_VSET.attr, ++ &dev_attr_LDO4_VSET.attr, ++ &dev_attr_LDO5_VSET.attr, ++ NULL ++}; ++ ++static const struct attribute_group ip6303_attr_group = { ++ .name = "ip6303", ++ .attrs = ip6303_attributes, ++}; ++ ++ ++static enum power_supply_property ip6303_battery_props[] = { ++ POWER_SUPPLY_PROP_STATUS, ++ POWER_SUPPLY_PROP_ONLINE, ++ POWER_SUPPLY_PROP_VOLTAGE_NOW, ++ POWER_SUPPLY_PROP_CAPACITY, ++}; ++ ++static const struct power_supply_desc ip6303_battery_desc = { ++ .name = "battery", ++ .type = POWER_SUPPLY_TYPE_BATTERY, ++ .get_property = ip6303_get_property, ++ .properties = ip6303_battery_props, ++ .num_properties = ARRAY_SIZE(ip6303_battery_props), ++}; ++ ++static int ip6303_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ int err; ++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); ++ struct power_supply_config psy_cfg = {}; ++ struct ip6303_chip *chip; ++ ++ printk(KERN_NOTICE "%s,%d,iic dev:%s\n",__func__,__LINE__,client->name); ++ ++ if(!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE)) ++ return -EIO; ++ ++ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); ++ if(!chip) ++ return -ENOMEM; ++ ++ chip->client = client; ++ chip->pdata = client->dev.platform_data; ++ ++ i2c_set_clientdata(client, chip); ++ psy_cfg.drv_data = chip; ++ ++ chip->battery = power_supply_register(&client->dev,&ip6303_battery_desc, &psy_cfg); ++ if(IS_ERR(chip->battery)) { ++ dev_err(&client->dev, "failed: power supply register\n"); ++ return PTR_ERR(chip->battery); ++ } ++ ++ ip6303_reset(client); ++ ip6303_get_version(client); ++ IP6303_Initialize(client); ++ ip6303_get_battery_assemble(client); ++ ip6303_get_init_online(client); ++ ++ // Retrieve IRQ ++ of_property_read_u32(client->dev.of_node, "pmu_irq_gpio", &chip->irq); ++ if (chip->irq <= 0) { ++ dev_err(&client->dev, "dts can't find IRQ, PAD_PM_LED0 is by default\n"); ++ err = -ENODEV; ++ //chip->irq = PAD_FUART_CTS;//for debug ++ } ++ else ++ { ++ int irq_num = 0; ++ printk(KERN_INFO "pmu_irq_gpio[%d] ...\n", chip->irq); ++ if (gpio_direction_input(chip->irq) < 0) { ++ dev_err(&client->dev, "gpio_direction_input[%d] failed...\n", chip->irq); ++ } ++ // Register a ISR ++ irq_num = gpio_to_irq(chip->irq); ++ err = request_irq(irq_num, ip6303_isr, IRQF_TRIGGER_HIGH/*IRQF_SHARED*/, "pmu isr", chip); ++ if (err != 0) { ++ dev_err(&client->dev, "request pmu isr failed (irq: %d, errno:%d)\n", chip->irq, err); ++ err = -ENODEV; ++ } ++ } ++ ++ /* Sys Attribute Register */ ++ err = sysfs_create_group(&client->dev.kobj, &ip6303_attr_group); ++ if (!err) { ++ dev_err(&client->dev,"create device file failed!\n"); ++ } ++ ++ g_chip = chip; ++ pm_power_off = ip6303_poweroff_enter; ++ ++ INIT_DEFERRABLE_WORK(&chip->work, ip6303_work); ++ queue_delayed_work(system_power_efficient_wq, &chip->work, IP6303_DELAY); ++ ++ return 0; ++} ++ ++static int ip6303_remove(struct i2c_client *client) ++{ ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ power_supply_unregister(chip->battery); ++ cancel_delayed_work(&chip->work); ++ sysfs_remove_group(&client->dev.kobj, &ip6303_attr_group); ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++ ++static int ip6303_suspend(struct device *dev) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ cancel_delayed_work(&chip->work); ++ return 0; ++} ++ ++static int ip6303_resume(struct device *dev) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ struct ip6303_chip *chip = i2c_get_clientdata(client); ++ ++ queue_delayed_work(system_power_efficient_wq, &chip->work, IP6303_DELAY); ++ return 0; ++} ++ ++static SIMPLE_DEV_PM_OPS(ip6303_pm_ops, ip6303_suspend, ip6303_resume); ++#define IP6303_PM_OPS (&ip6303_pm_ops) ++ ++#else ++ ++#define IP6303_PM_OPS NULL ++ ++#endif /* CONFIG_PM_SLEEP */ ++ ++static const struct i2c_device_id ip6303_id[] = { ++ { "ip6303" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, ip6303_id); ++ ++static const struct of_device_id Injoinic_of_match[] = { ++ { .compatible = "Injoinic,ip6303", }, ++ { } ++}; ++ ++static struct i2c_driver ip6303_i2c_driver = { ++ .class = I2C_CLASS_HWMON, ++ .driver = { ++ .name = "ip6303", ++ .pm = IP6303_PM_OPS, ++ .of_match_table = Injoinic_of_match, ++ }, ++ .probe = ip6303_probe, ++ .remove = ip6303_remove, ++ .id_table = ip6303_id, ++}; ++module_i2c_driver(ip6303_i2c_driver); ++ ++MODULE_AUTHOR("QinLei "); ++MODULE_DESCRIPTION("IP6303 Fuel Gauge"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c +index 86280b7e41f3..3ca9891eeeda 100644 +--- a/drivers/ptp/ptp_clock.c ++++ b/drivers/ptp/ptp_clock.c +@@ -175,10 +175,11 @@ static struct posix_clock_operations ptp_clock_ops = { + .read = ptp_read, + }; + +-static void delete_ptp_clock(struct posix_clock *pc) ++static void ptp_clock_release(struct device *dev) + { +- struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock); ++ struct ptp_clock *ptp = container_of(dev, struct ptp_clock, dev); + ++ ptp_cleanup_pin_groups(ptp); + mutex_destroy(&ptp->tsevq_mux); + mutex_destroy(&ptp->pincfg_mux); + ida_simple_remove(&ptp_clocks_map, ptp->index); +@@ -209,7 +210,6 @@ struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info, + } + + ptp->clock.ops = ptp_clock_ops; +- ptp->clock.release = delete_ptp_clock; + ptp->info = info; + ptp->devid = MKDEV(major, index); + ptp->index = index; +@@ -218,17 +218,9 @@ struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info, + mutex_init(&ptp->pincfg_mux); + init_waitqueue_head(&ptp->tsev_wq); + +- /* Create a new device in our class. */ +- ptp->dev = device_create(ptp_class, parent, ptp->devid, ptp, +- "ptp%d", ptp->index); +- if (IS_ERR(ptp->dev)) +- goto no_device; +- +- dev_set_drvdata(ptp->dev, ptp); +- +- err = ptp_populate_sysfs(ptp); ++ err = ptp_populate_pin_groups(ptp); + if (err) +- goto no_sysfs; ++ goto no_pin_groups; + + /* Register a new PPS source. */ + if (info->pps) { +@@ -239,13 +231,24 @@ struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info, + pps.owner = info->owner; + ptp->pps_source = pps_register_source(&pps, PTP_PPS_DEFAULTS); + if (!ptp->pps_source) { ++ err = -EINVAL; + pr_err("failed to register pps source\n"); + goto no_pps; + } + } + +- /* Create a posix clock. */ +- err = posix_clock_register(&ptp->clock, ptp->devid); ++ /* Initialize a new device of our class in our clock structure. */ ++ device_initialize(&ptp->dev); ++ ptp->dev.devt = ptp->devid; ++ ptp->dev.class = ptp_class; ++ ptp->dev.parent = parent; ++ ptp->dev.groups = ptp->pin_attr_groups; ++ ptp->dev.release = ptp_clock_release; ++ dev_set_drvdata(&ptp->dev, ptp); ++ dev_set_name(&ptp->dev, "ptp%d", ptp->index); ++ ++ /* Create a posix clock and link it to the device. */ ++ err = posix_clock_register(&ptp->clock, &ptp->dev); + if (err) { + pr_err("failed to create posix clock\n"); + goto no_clock; +@@ -257,10 +260,8 @@ no_clock: + if (ptp->pps_source) + pps_unregister_source(ptp->pps_source); + no_pps: +- ptp_cleanup_sysfs(ptp); +-no_sysfs: +- device_destroy(ptp_class, ptp->devid); +-no_device: ++ ptp_cleanup_pin_groups(ptp); ++no_pin_groups: + mutex_destroy(&ptp->tsevq_mux); + mutex_destroy(&ptp->pincfg_mux); + ida_simple_remove(&ptp_clocks_map, index); +@@ -279,10 +280,9 @@ int ptp_clock_unregister(struct ptp_clock *ptp) + /* Release the clock's resources. */ + if (ptp->pps_source) + pps_unregister_source(ptp->pps_source); +- ptp_cleanup_sysfs(ptp); +- device_destroy(ptp_class, ptp->devid); + + posix_clock_unregister(&ptp->clock); ++ + return 0; + } + EXPORT_SYMBOL(ptp_clock_unregister); +diff --git a/drivers/ptp/ptp_private.h b/drivers/ptp/ptp_private.h +index 9c5d41421b65..15346e840caa 100644 +--- a/drivers/ptp/ptp_private.h ++++ b/drivers/ptp/ptp_private.h +@@ -40,7 +40,7 @@ struct timestamp_event_queue { + + struct ptp_clock { + struct posix_clock clock; +- struct device *dev; ++ struct device dev; + struct ptp_clock_info *info; + dev_t devid; + int index; /* index into clocks.map */ +@@ -54,6 +54,8 @@ struct ptp_clock { + struct device_attribute *pin_dev_attr; + struct attribute **pin_attr; + struct attribute_group pin_attr_group; ++ /* 1st entry is a pointer to the real group, 2nd is NULL terminator */ ++ const struct attribute_group *pin_attr_groups[2]; + }; + + /* +@@ -94,8 +96,7 @@ uint ptp_poll(struct posix_clock *pc, + + extern const struct attribute_group *ptp_groups[]; + +-int ptp_cleanup_sysfs(struct ptp_clock *ptp); +- +-int ptp_populate_sysfs(struct ptp_clock *ptp); ++int ptp_populate_pin_groups(struct ptp_clock *ptp); ++void ptp_cleanup_pin_groups(struct ptp_clock *ptp); + + #endif +diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c +index 302e626fe6b0..731d0423c8aa 100644 +--- a/drivers/ptp/ptp_sysfs.c ++++ b/drivers/ptp/ptp_sysfs.c +@@ -46,27 +46,6 @@ PTP_SHOW_INT(n_periodic_outputs, n_per_out); + PTP_SHOW_INT(n_programmable_pins, n_pins); + PTP_SHOW_INT(pps_available, pps); + +-static struct attribute *ptp_attrs[] = { +- &dev_attr_clock_name.attr, +- &dev_attr_max_adjustment.attr, +- &dev_attr_n_alarms.attr, +- &dev_attr_n_external_timestamps.attr, +- &dev_attr_n_periodic_outputs.attr, +- &dev_attr_n_programmable_pins.attr, +- &dev_attr_pps_available.attr, +- NULL, +-}; +- +-static const struct attribute_group ptp_group = { +- .attrs = ptp_attrs, +-}; +- +-const struct attribute_group *ptp_groups[] = { +- &ptp_group, +- NULL, +-}; +- +- + static ssize_t extts_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +@@ -91,6 +70,7 @@ static ssize_t extts_enable_store(struct device *dev, + out: + return err; + } ++static DEVICE_ATTR(extts_enable, 0220, NULL, extts_enable_store); + + static ssize_t extts_fifo_show(struct device *dev, + struct device_attribute *attr, char *page) +@@ -124,6 +104,7 @@ out: + mutex_unlock(&ptp->tsevq_mux); + return cnt; + } ++static DEVICE_ATTR(fifo, 0444, extts_fifo_show, NULL); + + static ssize_t period_store(struct device *dev, + struct device_attribute *attr, +@@ -151,6 +132,7 @@ static ssize_t period_store(struct device *dev, + out: + return err; + } ++static DEVICE_ATTR(period, 0220, NULL, period_store); + + static ssize_t pps_enable_store(struct device *dev, + struct device_attribute *attr, +@@ -177,6 +159,57 @@ static ssize_t pps_enable_store(struct device *dev, + out: + return err; + } ++static DEVICE_ATTR(pps_enable, 0220, NULL, pps_enable_store); ++ ++static struct attribute *ptp_attrs[] = { ++ &dev_attr_clock_name.attr, ++ ++ &dev_attr_max_adjustment.attr, ++ &dev_attr_n_alarms.attr, ++ &dev_attr_n_external_timestamps.attr, ++ &dev_attr_n_periodic_outputs.attr, ++ &dev_attr_n_programmable_pins.attr, ++ &dev_attr_pps_available.attr, ++ ++ &dev_attr_extts_enable.attr, ++ &dev_attr_fifo.attr, ++ &dev_attr_period.attr, ++ &dev_attr_pps_enable.attr, ++ NULL ++}; ++ ++static umode_t ptp_is_attribute_visible(struct kobject *kobj, ++ struct attribute *attr, int n) ++{ ++ struct device *dev = kobj_to_dev(kobj); ++ struct ptp_clock *ptp = dev_get_drvdata(dev); ++ struct ptp_clock_info *info = ptp->info; ++ umode_t mode = attr->mode; ++ ++ if (attr == &dev_attr_extts_enable.attr || ++ attr == &dev_attr_fifo.attr) { ++ if (!info->n_ext_ts) ++ mode = 0; ++ } else if (attr == &dev_attr_period.attr) { ++ if (!info->n_per_out) ++ mode = 0; ++ } else if (attr == &dev_attr_pps_enable.attr) { ++ if (!info->pps) ++ mode = 0; ++ } ++ ++ return mode; ++} ++ ++static const struct attribute_group ptp_group = { ++ .is_visible = ptp_is_attribute_visible, ++ .attrs = ptp_attrs, ++}; ++ ++const struct attribute_group *ptp_groups[] = { ++ &ptp_group, ++ NULL ++}; + + static int ptp_pin_name2index(struct ptp_clock *ptp, const char *name) + { +@@ -235,40 +268,14 @@ static ssize_t ptp_pin_store(struct device *dev, struct device_attribute *attr, + return count; + } + +-static DEVICE_ATTR(extts_enable, 0220, NULL, extts_enable_store); +-static DEVICE_ATTR(fifo, 0444, extts_fifo_show, NULL); +-static DEVICE_ATTR(period, 0220, NULL, period_store); +-static DEVICE_ATTR(pps_enable, 0220, NULL, pps_enable_store); +- +-int ptp_cleanup_sysfs(struct ptp_clock *ptp) ++int ptp_populate_pin_groups(struct ptp_clock *ptp) + { +- struct device *dev = ptp->dev; +- struct ptp_clock_info *info = ptp->info; +- +- if (info->n_ext_ts) { +- device_remove_file(dev, &dev_attr_extts_enable); +- device_remove_file(dev, &dev_attr_fifo); +- } +- if (info->n_per_out) +- device_remove_file(dev, &dev_attr_period); +- +- if (info->pps) +- device_remove_file(dev, &dev_attr_pps_enable); +- +- if (info->n_pins) { +- sysfs_remove_group(&dev->kobj, &ptp->pin_attr_group); +- kfree(ptp->pin_attr); +- kfree(ptp->pin_dev_attr); +- } +- return 0; +-} +- +-static int ptp_populate_pins(struct ptp_clock *ptp) +-{ +- struct device *dev = ptp->dev; + struct ptp_clock_info *info = ptp->info; + int err = -ENOMEM, i, n_pins = info->n_pins; + ++ if (!n_pins) ++ return 0; ++ + ptp->pin_dev_attr = kzalloc(n_pins * sizeof(*ptp->pin_dev_attr), + GFP_KERNEL); + if (!ptp->pin_dev_attr) +@@ -292,61 +299,18 @@ static int ptp_populate_pins(struct ptp_clock *ptp) + ptp->pin_attr_group.name = "pins"; + ptp->pin_attr_group.attrs = ptp->pin_attr; + +- err = sysfs_create_group(&dev->kobj, &ptp->pin_attr_group); +- if (err) +- goto no_group; ++ ptp->pin_attr_groups[0] = &ptp->pin_attr_group; ++ + return 0; + +-no_group: +- kfree(ptp->pin_attr); + no_pin_attr: + kfree(ptp->pin_dev_attr); + no_dev_attr: + return err; + } + +-int ptp_populate_sysfs(struct ptp_clock *ptp) ++void ptp_cleanup_pin_groups(struct ptp_clock *ptp) + { +- struct device *dev = ptp->dev; +- struct ptp_clock_info *info = ptp->info; +- int err; +- +- if (info->n_ext_ts) { +- err = device_create_file(dev, &dev_attr_extts_enable); +- if (err) +- goto out1; +- err = device_create_file(dev, &dev_attr_fifo); +- if (err) +- goto out2; +- } +- if (info->n_per_out) { +- err = device_create_file(dev, &dev_attr_period); +- if (err) +- goto out3; +- } +- if (info->pps) { +- err = device_create_file(dev, &dev_attr_pps_enable); +- if (err) +- goto out4; +- } +- if (info->n_pins) { +- err = ptp_populate_pins(ptp); +- if (err) +- goto out5; +- } +- return 0; +-out5: +- if (info->pps) +- device_remove_file(dev, &dev_attr_pps_enable); +-out4: +- if (info->n_per_out) +- device_remove_file(dev, &dev_attr_period); +-out3: +- if (info->n_ext_ts) +- device_remove_file(dev, &dev_attr_fifo); +-out2: +- if (info->n_ext_ts) +- device_remove_file(dev, &dev_attr_extts_enable); +-out1: +- return err; ++ kfree(ptp->pin_attr); ++ kfree(ptp->pin_dev_attr); + } +diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c +old mode 100644 +new mode 100755 +index 172ef8245811..1b3283bb38d9 +--- a/drivers/pwm/core.c ++++ b/drivers/pwm/core.c +@@ -1,3 +1,4 @@ ++ + /* + * Generic pwmlib implementation + * +@@ -459,9 +460,10 @@ int pwm_apply_state(struct pwm_device *pwm, struct pwm_state *state) + { + int err; + +- if (!pwm || !state || !state->period || +- state->duty_cycle > state->period) ++ if (!pwm || !state || !state->period) ++// ||state->duty_cycle > state->period){ + return -EINVAL; ++// } + + if (!memcmp(state, &pwm->state, sizeof(*state))) + return 0; +diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c +index 13db3b7bc873..6bf4a7180007 100644 +--- a/drivers/scsi/bfa/bfad_attr.c ++++ b/drivers/scsi/bfa/bfad_attr.c +@@ -283,8 +283,10 @@ bfad_im_get_stats(struct Scsi_Host *shost) + rc = bfa_port_get_stats(BFA_FCPORT(&bfad->bfa), + fcstats, bfad_hcb_comp, &fcomp); + spin_unlock_irqrestore(&bfad->bfad_lock, flags); +- if (rc != BFA_STATUS_OK) ++ if (rc != BFA_STATUS_OK) { ++ kfree(fcstats); + return NULL; ++ } + + wait_for_completion(&fcomp.comp); + +diff --git a/drivers/scsi/libsas/sas_expander.c b/drivers/scsi/libsas/sas_expander.c +index 022bb6e10d98..a6a00df5cabd 100644 +--- a/drivers/scsi/libsas/sas_expander.c ++++ b/drivers/scsi/libsas/sas_expander.c +@@ -47,17 +47,16 @@ static void smp_task_timedout(unsigned long _task) + unsigned long flags; + + spin_lock_irqsave(&task->task_state_lock, flags); +- if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) ++ if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { + task->task_state_flags |= SAS_TASK_STATE_ABORTED; ++ complete(&task->slow_task->completion); ++ } + spin_unlock_irqrestore(&task->task_state_lock, flags); +- +- complete(&task->slow_task->completion); + } + + static void smp_task_done(struct sas_task *task) + { +- if (!del_timer(&task->slow_task->timer)) +- return; ++ del_timer(&task->slow_task->timer); + complete(&task->slow_task->completion); + } + +@@ -975,6 +974,8 @@ static struct domain_device *sas_ex_discover_expander( + list_del(&child->dev_list_node); + spin_unlock_irq(&parent->port->dev_list_lock); + sas_put_device(child); ++ sas_port_delete(phy->port); ++ phy->port = NULL; + return NULL; + } + list_add_tail(&child->siblings, &parent->ex_dev.children); +diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c +index 35cbd36f8d3b..8623b3f9bb06 100644 +--- a/drivers/scsi/megaraid/megaraid_sas_base.c ++++ b/drivers/scsi/megaraid/megaraid_sas_base.c +@@ -3956,6 +3956,7 @@ int megasas_alloc_cmds(struct megasas_instance *instance) + if (megasas_create_frame_pool(instance)) { + dev_printk(KERN_DEBUG, &instance->pdev->dev, "Error creating frame DMA pool\n"); + megasas_free_cmds(instance); ++ return -ENOMEM; + } + + return 0; +diff --git a/drivers/sstar/Kconfig b/drivers/sstar/Kconfig +new file mode 100755 +index 000000000000..7f1dd4aeef7c +--- /dev/null ++++ b/drivers/sstar/Kconfig +@@ -0,0 +1,53 @@ ++menuconfig MSTAR_DRIVERS ++ bool "SStar SoC platform drivers" ++ depends on ARCH_SSTAR ++ default n ++ ++menuconfig CAM_DRIVERS ++ bool "SStar Cam drivers" ++ depends on MSTAR_DRIVERS ++ default n ++if ( CAM_DRIVERS ) ++source "drivers/sstar/camdriver/Kconfig" ++endif ++ ++menuconfig DLA_DRIVER ++ bool "SStar DLA driver" ++ depends on MSTAR_DRIVERS ++ default n ++if ( DLA_DRIVER ) ++source "drivers/sstar/cambricon/Kconfig" ++endif ++ ++if ( MSTAR_DRIVERS ) ++ ++source "drivers/sstar/irqchip/Kconfig" ++source "drivers/sstar/clocksource/Kconfig" ++source "drivers/sstar/msys/Kconfig" ++source "drivers/sstar/serial/Kconfig" ++source "drivers/sstar/clk/Kconfig" ++source "drivers/sstar/flash_isp/Kconfig" ++source "drivers/sstar/pwm/Kconfig" ++source "drivers/sstar/spinand/Kconfig" ++source "drivers/sstar/spi/Kconfig" ++source "drivers/sstar/mspi/Kconfig" ++source "drivers/sstar/camclk/Kconfig" ++source "drivers/sstar/include/$SSTAR_CHIP_NAME/Kconfig" ++ ++source "drivers/sstar/ir/Kconfig" ++source "drivers/sstar/i2c/Kconfig" ++source "drivers/sstar/gpio/Kconfig" ++source "drivers/sstar/padmux/Kconfig" ++source "drivers/sstar/rtc/Kconfig" ++source "drivers/sstar/watchdog/Kconfig" ++source "drivers/sstar/sar/Kconfig" ++source "drivers/sstar/sar_key/Kconfig" ++source "drivers/sstar/mma_heap/Kconfig" ++source "drivers/sstar/netphy/Kconfig" ++source "drivers/sstar/voltage/Kconfig" ++source "drivers/sstar/iopower/Kconfig" ++source "drivers/sstar/swtoe/Kconfig" ++source "drivers/sstar/emac_toe/Kconfig" ++source "drivers/sstar/adaptor/Kconfig" ++ ++endif +diff --git a/drivers/sstar/Makefile b/drivers/sstar/Makefile +new file mode 100755 +index 000000000000..2f48fcee4fad +--- /dev/null ++++ b/drivers/sstar/Makefile +@@ -0,0 +1,56 @@ ++obj-y += irqchip/ ++obj-y += clocksource/ ++obj-y += serial/ ++obj-y += clk/ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage/ ++obj-$(CONFIG_MS_BDMA) += bdma/ ++obj-$(CONFIG_MS_MOVE_DMA) += movedma/ ++obj-y += msys/ ++obj-y += cam_os_wrapper/ ++obj-y += cam_drv_poll/ ++obj-y += cam_drv_buffer/ ++obj-y += cam_fs_wrapper/ ++obj-y += cam_sysfs/ ++obj-y += cam_clkgen/ ++obj-$(CONFIG_CAM_CLK) += camclk/ ++obj-$(CONFIG_MS_EMMC) += emmc/ ++obj-$(CONFIG_MS_SDMMC) += sdmmc/ ++obj-$(CONFIG_USB_SUPPORT) += usb/host/ ++obj-$(CONFIG_SS_SWTOE) += swtoe/ ++obj-$(CONFIG_SSTAR_NETPHY) += netphy/ ++obj-$(CONFIG_MS_EMAC) += emac/ ++obj-$(CONFIG_MS_EMAC_TOE) += emac_toe/ ++obj-$(CONFIG_MS_IR) += ir/ ++obj-$(CONFIG_MS_RTC) += rtc/ ++obj-$(CONFIG_MS_GPIO) += gpio/ ++obj-$(CONFIG_MS_PADMUX) += padmux/ ++obj-$(CONFIG_MS_WATCHDOG) += watchdog/ ++obj-$(CONFIG_MS_SAR) += sar/ ++obj-$(CONFIG_MS_SARKEY) += sar_key/ ++obj-$(CONFIG_MS_IRCUT) += ircut/ ++obj-$(CONFIG_MS_I2C) += i2c/ ++obj-$(CONFIG_MS_FLASH_ISP) += flash_isp/ ++obj-$(CONFIG_MS_XPM) += xpm/ ++obj-y += crypto/ ++obj-$(CONFIG_MS_CPU_FREQ) += cpufreq/ ++obj-$(CONFIG_MS_PWM) += pwm/ ++obj-$(CONFIG_MS_SPINAND) += spinand/ ++obj-$(CONFIG_MS_SPI_INFINITY) += spi/ ++obj-$(CONFIG_SS_MSPI) += mspi/ ++obj-$(CONFIG_MS_IVE) += ive/ ++obj-$(CONFIG_MS_WARP) += warp/ ++obj-$(CONFIG_MS_NOTIFY) += notify/ ++obj-$(CONFIG_CAM_DRIVERS) += camdriver/ ++obj-$(CONFIG_DLA_DRIVER) += cambricon/ ++obj-$(CONFIG_SS_ISP_ISRCB) += isrcb/ ++obj-$(CONFIG_MSTAR_MMAHEAP) += mma_heap/ ++obj-$(CONFIG_MSTAR_MIU) += miu/ ++obj-$(CONFIG_SS_SATA_HOST) += sata_host/ ++obj-$(CONFIG_SS_DUALOS) += dualos/ ++obj-$(CONFIG_SS_DUALOS) += adaptor/ ++obj-$(CONFIG_MS_NOE) += noe/ ++obj-$(CONFIG_SSTAR_CEVAXM6) += ceva_link/ ++obj-$(CONFIG_VCORE_DVFS) += vcore_dvfs/ ++obj-$(CONFIG_MS_IOPOWER) += iopower/ ++obj-y += cpu/ ++obj-$(CONFIG_USB_GADGET_SSTAR_DEVICE) += usb/gadget/udc/usb20/ +diff --git a/drivers/sstar/adaptor/Kconfig b/drivers/sstar/adaptor/Kconfig +new file mode 100644 +index 000000000000..69380f7dfe25 +--- /dev/null ++++ b/drivers/sstar/adaptor/Kconfig +@@ -0,0 +1,9 @@ ++config SS_RTK_MI_ADAPTOR ++depends on SS_DUALOS && !(SS_SWTOE) ++ ++boolean "SS_RTK_MI_ADAPTOR" ++default y ++ ++---help--- ++Enable compilation option for DualOS RTK MI Adaptor ++ +diff --git a/drivers/sstar/adaptor/Makefile b/drivers/sstar/adaptor/Makefile +new file mode 100755 +index 000000000000..cce7f6a995fd +--- /dev/null ++++ b/drivers/sstar/adaptor/Makefile +@@ -0,0 +1,7 @@ ++obj-$(CONFIG_SS_RTK_MI_ADAPTOR) += kdrv_adaptor.o ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++kdrv_adaptor-y += linux-rtos-adaptor.o ++ +diff --git a/drivers/sstar/adaptor/linux-rtos-adaptor.c b/drivers/sstar/adaptor/linux-rtos-adaptor.c +new file mode 100755 +index 000000000000..9e0c833fe8dd +--- /dev/null ++++ b/drivers/sstar/adaptor/linux-rtos-adaptor.c +@@ -0,0 +1,1158 @@ ++/* ++* linux-rtos-adaptor.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* All rights reserved. ++* ++* Author: ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "drv_dualos.h" ++#include "ms_platform.h" ++ ++#define E_MI_MODULE_ID_MAX 31 ++ ++#define __MI_DEVICE_PROC 0xfffffffful ++#define __MI_DEVICE_PROC_IO 0xfffffffeul ++#define __MI_DEVICE_PROC_READLOG 0xfffffffdul ++#define __MI_DEVICE_CONNECT 0 ++#define __MI_DEVICE_DISCONNECT 1 ++#define __MI_DEVICE_QUERY 2 ++#define __MI_DEVICE_POLL_CREATE 3 ++#define __MI_DEVICE_POLL_RELEASE 4 ++#define __MI_DEVICE_POLL_STATE 5 ++const unsigned int INTEROS_SC_L2R_MI_CALL_START = 0xff000000; ++const unsigned int INTEROS_SC_L2R_MI_CALL_END = 0xff000040; ++const int ALKAID_RTKTRACE = 0; ++//#define MMA_BASE (0x20000000ul+E_MMAP_ID_RTK_mma_heap_ADR) ++//#define MMA_SIZE (0x0ul+E_MMAP_ID_RTK_mma_heap_LEN) ++#define CTX_NUM 2 ++#define CTX_BASE 8 ++ ++#define FIVE_SEC (HZ*5) ++ ++typedef struct { ++ struct { ++ union { ++ void *curr_base; ++ int pid; ++ unsigned long cmd; ++ unsigned long poll_handle; ++ }; ++ long idx; ++ long devid; ++ union { ++ unsigned long mma_base; ++ unsigned long log_base; ++ }; ++ unsigned int arg_size; ++ }; ++ char __pad[64]; ++} linux_ctx __attribute__((aligned(64))); ++struct proc_dev { ++ int modid; ++ int devid; ++ int next; ++ char cmd_list[]; ++} __attribute__((aligned(64))); ++struct proc_buffer { ++ int cost; ++ char buf[]; ++}; ++#define POLL_FILE_MAX 64 ++typedef enum { ++ E_MI_COMMON_POLL_NOT_READY = (0x0) , ++ E_MI_COMMON_FRAME_READY_FOR_READ = (0x1 << 0), ++ E_MI_COMMON_BUFFER_READY_FOR_WRITE = (0x1 << 1), ++} MI_COMMON_PollFlag_e; ++ ++static int disable_os_adaptor = 0; ++module_param(disable_os_adaptor, int, 0644); ++MODULE_PARM_DESC(disable_os_adaptor, "Disable Linux-RTOS Adaptor"); ++ ++/* ++ * from ARM Architecture Reference Manual ++ * ARMv7-A and ARMv7-R edition ++ * B3.18.6 Cache maintenance operations, functional group, VMSA ++ * Table B3-49 Cache and branch predictor maintenance operations, VMSA ++ */ ++static void flush_cache_area(void *ptr, int len){ ++ const unsigned long cache_line_size = 64; ++ unsigned long iter, end; ++ iter = (unsigned long)ptr, end = (unsigned long)ptr + len; ++ iter = iter/cache_line_size*cache_line_size; ++ end = end/cache_line_size*cache_line_size; ++ asm __volatile__("dsb st":::"memory"); /* data sync barrier for store */ ++ while(iter <= end){ ++ //asm __volatile__("mcr p15, 0, %0, c7, c11, 1"::"r"(iter):"memory"); /* DCCMVAC: flush to PoU (aka last level cache) */ ++ asm __volatile__("mcr p15, 0, %0, c7, c10, 1"::"r"(iter):"memory"); /* DCCMVAU: flush to PoC (aka main memory) */ ++ iter += cache_line_size; ++ } ++} ++static void invalid_cache_area(void *ptr, int len){ ++ const unsigned long cache_line_size = 64; ++ unsigned long iter, end; ++ iter = (unsigned long)ptr, end = (unsigned long)ptr + len; ++ iter = iter/cache_line_size*cache_line_size; ++ end = end/cache_line_size*cache_line_size; ++ while(iter <= end){ ++ asm __volatile__("mcr p15, 0, %0, c7, c6, 1"::"r"(iter):"memory"); /* DCIMVAC: invalidate to PoC */ ++ iter += cache_line_size; ++ } ++} ++static void flush_and_invalid_cache_area(void *ptr, int len){ ++ const unsigned long cache_line_size = 64; ++ unsigned long iter, end; ++ iter = (unsigned long)ptr, end = (unsigned long)ptr + len; ++ iter = iter/cache_line_size*cache_line_size; ++ end = end/cache_line_size*cache_line_size; ++ asm __volatile__("dsb st":::"memory"); /* data sync barrier for store */ ++ while(iter <= end){ ++ asm __volatile__("mcr p15, 0, %0, c7, c14, 1"::"r"(iter):"memory"); /* DCCIMVAC: flush & invalid to PoC (aka main memory) */ ++ iter += cache_line_size; ++ } ++} ++ ++static struct class *device_class; ++static struct device *device_list[E_MI_MODULE_ID_MAX + 1]; ++static struct proc_dev *proc_list[E_MI_MODULE_ID_MAX]; ++static int device_major, poll_major; ++static struct semaphore device_sem[CTX_NUM]; ++static struct semaphore ctx_sem; ++static spinlock_t ctx_lock; ++static DECLARE_BITMAP(ctx_bitmap, 32); ++static atomic_t device_ref; ++static struct resource *rtk_res; ++ ++ ++// IPC_SHARE_ADDR + 0x0000 ~ IPC_SHARE_ADDR + 0x1000 ==> RSQ for basic IPC ++// IPC_SHARE_ADDR + 0x1000 ~ IPC_SHARE_ADDR + 0x5000 ==> RSQ for log ++// IPC_SHARE_ADDR + 0x5000 ~ IPC_SHARE_ADDR + 0x6000 ==> RSQ for customize settings ++ ++static unsigned long mma_base = 0x25500000; ++static unsigned long mma_size = 0x02700000; ++ ++/* ++example: ++os_adaptor=mma_base=0x25500000,mma_size=0x02700000 ++os_adaptor=mma_base=0x21F00000,mma_size=0x01D00000 ++*/ ++static bool parse_os_adaptor_config(char *cmdline, unsigned long *mma_base, unsigned long *mma_size) ++{ ++ char *option; ++ ++ if(cmdline == NULL) ++ goto INVALID_OS_ADAPTOR_CONFIG; ++ ++ option = strstr(cmdline, "mma_size="); ++ if(option == NULL) ++ goto INVALID_OS_ADAPTOR_CONFIG; ++ option = strstr(cmdline, "mma_base="); ++ if(option == NULL) ++ goto INVALID_OS_ADAPTOR_CONFIG; ++ sscanf(option, "mma_base=%lx,mma_size=%lx", mma_base, mma_size); ++ ++ return true; ++ ++INVALID_OS_ADAPTOR_CONFIG: ++ ++ return false; ++} ++ ++int __init setup_os_adaptor(char *cmdline) ++{ ++ if(!parse_os_adaptor_config(cmdline, &mma_base, &mma_size)) ++ printk(KERN_ERR "error: os_adaptor args invalid\n"); ++ ++ return 0; ++} ++early_param("os_adaptor", setup_os_adaptor); ++ ++static atomic_t ctx_cost[CTX_NUM][sizeof(unsigned long)*8] = {}; ++static atomic_t ctx_freq[CTX_NUM] = {}; ++ ++ ++static struct proc_dir_entry *debug_tools; ++static struct proc_dir_entry *proc_root; ++struct debug_tool { ++ struct proc_dir_entry *entry; ++ void *obj; ++ ssize_t (*write)(void *obj, const char **args, int count); ++ ssize_t (*read)(void *obj); ++}; ++struct debug_tool_freq { ++ struct debug_tool dt; ++ int interval; ++}; ++struct debug_tool_info { ++ struct debug_tool dt; ++ const char *version; ++}; ++static ssize_t ctx_cost_erase(void *obj, const char **args, int count){ ++ atomic_t (*cost)[sizeof(unsigned long)*8] = ctx_cost; ++ int i, j; ++ for(i = 0; i < CTX_NUM; ++i){ ++ for(j = 0; j < sizeof(unsigned long)*8; ++j){ ++ atomic_set(&cost[i][j], 0); ++ } ++ } ++ return 0; ++} ++static ssize_t ctx_cost_hist(void *obj){ ++ atomic_t (*cost)[sizeof(unsigned long)*8] = ctx_cost; ++ int i, j; ++ for(i = 0; i < CTX_NUM; ++i){ ++ for(j = 0; j < sizeof(unsigned long)*8; ++j){ ++ printk("CTX_%d|%02d:%d\n", i, j, atomic_read(&cost[i][j])); ++ } ++ printk("CTX--------------------\n"); ++ } ++ return 0; ++} ++static ssize_t ctx_cost_freq_setup(void *obj, const char **args, int count){ ++ struct debug_tool_freq *dtf = obj; ++ if(count == 1){ ++ if (kstrtoint((const char *)args[0], 0, &dtf->interval)) ++ return -EFAULT; ++ printk("freq watch interval=%dms\n", dtf->interval); ++ return count; ++ } ++ return -EINVAL; ++} ++static ssize_t ctx_cost_freq(void *obj){ ++ atomic_t *freq = ctx_freq; ++ int i; ++ for(i = 0; i < CTX_NUM; ++i){ ++ atomic_xchg(freq+i, 0); ++ } ++ while(schedule_timeout_interruptible(msecs_to_jiffies(200)) == 0){ ++ char buf[8*(CTX_NUM+1)] = {0}; ++ unsigned long rval; ++ unsigned long tmp; ++ tmp = atomic_xchg(freq, 0); ++ rval = sprintf(buf, "%8lu", tmp); ++ for(i = 1; i < CTX_NUM; ++i){ ++ tmp = atomic_xchg(freq+i, 0); ++ rval+=sprintf(buf+rval, "|%8lu", tmp); ++ } ++ printk("CTX_FREQ:%s\n", buf); ++ } ++ return 0; ++} ++ ++static ssize_t compile_version_info(void *obj){ ++ struct debug_tool_info *dti = obj; ++ printk("version string:%s\n", dti->version); ++ return 0; ++} ++ ++static struct debug_tool syscall_cost_column = { ++ .write = ctx_cost_erase, ++ .read = ctx_cost_hist, ++}; ++static struct debug_tool_freq syscall_freq_linear = { ++ { ++ .obj = &syscall_freq_linear, ++ .write = ctx_cost_freq_setup, ++ .read = ctx_cost_freq, ++ } ++}; ++static struct debug_tool_info info_tool = { ++ { ++ .obj = &info_tool, ++ .read = compile_version_info, ++ }, ++ .version = "version", ++}; ++ ++static unsigned int time_log2(ktime_t start, ktime_t end){ ++ unsigned int idx = 0; ++ unsigned long us = ktime_to_us(ktime_sub(end, start)); ++ while(us){ ++ idx = idx + 1; ++ us = us >> 1; ++ } ++ return idx; ++} ++ ++void alkaid_registe_notify(int cpu, void *notify); ++void *alkaid_unregiste_notify(int cpu); ++typedef struct { ++ wait_queue_head_t stPollHead; ++ unsigned long poll_handle; ++ struct list_head list; ++} MI_COMMON_PollFileWrapper_t; ++static LIST_HEAD(poll_task); ++static bool alkaid_notify(int idx){ ++ int mid = idx-CTX_BASE; ++ if(mid < CTX_NUM){ ++ if(down_trylock(device_sem+mid) == 0){ ++ printk("bug found at %s %d, %d\n", __func__, __LINE__, idx); ++ *(int*)0 = 0; ++ } ++ up(device_sem+mid); ++ }else{ ++ MI_COMMON_PollFileWrapper_t *f; ++ rcu_read_lock(); ++ list_for_each_entry_rcu(f, &poll_task, list){ ++ wake_up(&f->stPollHead); ++ } ++ rcu_read_unlock(); ++ } ++ return true; ++} ++static unsigned long alkaid_poll_wapper(MI_COMMON_PollFileWrapper_t *f, int cmd){ ++ unsigned long res = 0; ++ linux_ctx ctx = {.poll_handle = 0, .idx = -1,}; ++ ++ ctx.poll_handle = f ? f->poll_handle : 0; ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctx.idx = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctx.idx < CTX_NUM) { ++ set_bit(ctx.idx, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ } else { ++ ctx.idx = 0; ++ } ++ if(ctx.idx < CTX_NUM) { ++ flush_cache_area(&ctx, sizeof(ctx)); ++ Chip_Flush_MIU_Pipe(); ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d, poll handl:%ld\n", __func__, ++ __LINE__, ctx.poll_handle); ++ } ++ } ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+E_MI_MODULE_ID_MAX, __pa((long)&ctx), -1, cmd); ++ while(1) { ++ if (down_timeout(device_sem+ctx.idx, FIVE_SEC) == 0) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+E_MI_MODULE_ID_MAX, ctx.idx, -1, __MI_DEVICE_QUERY); ++ if(res != -2) { ++ break; ++ } else { ++ printk(KERN_ERR "bug found at %s %d\n", __func__, __LINE__); ++ *(int*)0 = 0; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!poll handl:%ld\n", __func__, ++ __LINE__, ctx.poll_handle); ++ } ++ } ++ clear_bit(ctx.idx, ctx_bitmap); ++ up(&ctx_sem); ++ ++ return res; ++} ++static unsigned long alkaid_poll_init(void){ ++ return alkaid_poll_wapper(NULL, __MI_DEVICE_POLL_CREATE); ++} ++static int MI_PollAdp_Open(struct inode *inode, struct file *filp) { ++ MI_COMMON_PollFileWrapper_t *fw = kmalloc(sizeof(MI_COMMON_PollFileWrapper_t), GFP_KERNEL); ++ if(fw){ ++ init_waitqueue_head(&fw->stPollHead); ++ fw->poll_handle = 0; ++ INIT_LIST_HEAD(&fw->list); ++ filp->private_data = fw; ++ return 0; ++ } ++ return -ENOMEM; ++} ++ ++static int MI_PollAdp_Release(struct inode *inode, struct file *filp) { ++ MI_COMMON_PollFileWrapper_t *f = filp->private_data; ++ ++ list_del_rcu(&f->list); ++ alkaid_poll_wapper(f, __MI_DEVICE_POLL_RELEASE); ++ kfree(f); ++ ++ return 0; ++} ++ ++static long MI_PollAdp_Ioctl(struct file *filp, unsigned int cmd, unsigned long ptr) { ++ MI_COMMON_PollFileWrapper_t *f = filp->private_data; ++ f->poll_handle = ptr; ++ list_add_rcu(&f->list, &poll_task); ++ return 0; ++} ++ ++static unsigned int MI_PollAdp_Poll(struct file *filp, poll_table *wait){ ++ MI_COMMON_PollFileWrapper_t *f = filp->private_data; ++ unsigned int req_events = poll_requested_events(wait); ++ unsigned int mask = 0; ++ unsigned long ret = 0; ++ ++ poll_wait(filp, &f->stPollHead, wait); ++ ret = alkaid_poll_wapper(f, __MI_DEVICE_POLL_STATE); ++ if(ret & E_MI_COMMON_FRAME_READY_FOR_READ) ++ mask |= POLLIN; ++ if(ret & E_MI_COMMON_BUFFER_READY_FOR_WRITE) ++ mask |= POLLOUT; ++ return req_events & mask; ++} ++ ++static const struct file_operations pfops = { ++ .owner = THIS_MODULE, ++ .open = MI_PollAdp_Open, ++ .release = MI_PollAdp_Release, ++ .unlocked_ioctl = MI_PollAdp_Ioctl, ++ .poll = MI_PollAdp_Poll, ++ .llseek = noop_llseek, ++}; ++static int MI_DEVICE_Open(struct inode *inode, struct file *filp) { ++ int id = iminor(inode); ++ unsigned long res = 0; ++ linux_ctx ctx = {.pid = current->pid, .idx = -1,}; ++ ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctx.idx = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctx.idx < CTX_NUM) { ++ set_bit(ctx.idx, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ } else { ++ ctx.idx = 0; ++ } ++ if(ctx.idx < CTX_NUM) { ++ flush_cache_area(&ctx, sizeof(ctx)); ++ Chip_Flush_MIU_Pipe(); ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!\n", __func__, __LINE__); ++ } ++ } ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, __pa((long)&ctx), -1, __MI_DEVICE_CONNECT); ++ while(1) { ++ if (down_timeout(device_sem+ctx.idx, FIVE_SEC) == 0) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, ctx.idx, -1, __MI_DEVICE_QUERY); ++ if(res != -2) { ++ break; ++ } else { ++ printk(KERN_ERR "bug found at %s %d\n", __func__, __LINE__); ++ *(int*)0 = 0; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!\n", __func__, __LINE__); ++ } ++ } ++ clear_bit(ctx.idx, ctx_bitmap); ++ up(&ctx_sem); ++ /* map mma range */ ++ filp->private_data = (void*)vm_mmap(filp, 0, mma_size, PROT_READ|PROT_WRITE, MAP_SHARED, rtk_res->start); ++ if((unsigned long)filp->private_data < PAGE_OFFSET){ ++ return res; ++ } ++ ++ return (long)filp->private_data; ++} ++ ++static int MI_DEVICE_Release(struct inode *inode, struct file *filp) { ++ int id = iminor(inode); ++ unsigned long res = 0; ++ linux_ctx ctx = {.pid = current->pid, .idx = -1,}; ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctx.idx = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctx.idx < CTX_NUM) { ++ set_bit(ctx.idx, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ } else { ++ ctx.idx = 0; ++ } ++ if(ctx.idx < CTX_NUM) { ++ flush_cache_area(&ctx, sizeof(ctx)); ++ Chip_Flush_MIU_Pipe(); ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!\n", __func__, __LINE__); ++ } ++ } ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, __pa((long)&ctx), -1, __MI_DEVICE_DISCONNECT); ++ while(1) { ++ if (down_timeout(device_sem+ctx.idx, FIVE_SEC) == 0) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, ctx.idx, -1, __MI_DEVICE_QUERY); ++ if(res != -2) { ++ break; ++ } else { ++ printk(KERN_ERR "bug found at %s %d\n", __func__, __LINE__); ++ *(int*)0 = 0; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d,id=%d\n", __func__, __LINE__,id); ++ } ++ } ++ clear_bit(ctx.idx, ctx_bitmap); ++ up(&ctx_sem); ++ if(atomic_dec_return(&device_ref) == 0){ ++ alkaid_unregiste_notify(0); ++ printk("unregister notify\n"); ++ } ++ return res; ++} ++ ++static unsigned long vir2phy(struct task_struct *curr, void *ptr){ ++ unsigned long addr = (unsigned long)ptr; ++ pgd_t *pgd = pgd_offset(curr->mm,addr); ++ pud_t *pud = pud_offset(pgd,addr); ++ pmd_t *pmd = pmd_offset(pud,addr); ++ pte_t *pte = pmd_page_vaddr(*pmd)+pte_index(addr); ++ return __pfn_to_phys(pte_pfn(*pte))+(addr&~PAGE_MASK); ++} ++ ++static long MI_DEVICE_Ioctl(struct file *filp, unsigned int cmd, unsigned long ptr) { ++ int id = iminor(file_inode(filp)); ++ long rval = -EIO; ++ if(_IOC_TYPE(cmd) == 'i') { ++ unsigned long res = 0; ++ atomic_t (*cost)[sizeof(unsigned long)*8]; ++ atomic_t *freq; ++ ktime_t t1, t2; ++ t1 = ktime_get(); ++ if(ptr) { ++ linux_ctx ctx = {.curr_base = filp->private_data, .idx = -1, .mma_base = mma_base}; ++ struct { ++ int len; ++ unsigned long long ptr; ++ } tr; ++ void *arg = NULL; ++ if (copy_from_user((char *)&tr, (void*)ptr, sizeof(tr))) ++ return -EFAULT; ++ if(tr.len > _IOC_SIZE(cmd)) { ++ printk(KERN_ERR "write cmd(0x%08x) overflow!", cmd); ++ return -EINVAL; ++ } ++ ++ if(tr.len > 4096) { ++ printk(KERN_WARNING "write cmd(0x%08x) Send Big Data size(%d)!", cmd, tr.len); ++ } ++ ++ if(_IOC_DIR(cmd) & _IOC_WRITE) { ++ if(tr.len == 0) { ++ printk(KERN_ERR "write cmd(0x%08x) send null data!", cmd); ++ return -EINVAL; ++ } ++ arg = memdup_user((void*)(long)tr.ptr, tr.len); ++ if(!arg) ++ return -ENOMEM; ++ if(_IOC_DIR(cmd) & _IOC_READ) { ++ flush_and_invalid_cache_area(arg, tr.len); ++ }else{ ++ flush_cache_area(arg, tr.len); ++ } ++ } else if(_IOC_DIR(cmd) & _IOC_READ) { ++ arg = kmalloc(tr.len+sizeof(long), GFP_KERNEL); ++ if(!arg) ++ return -ENOMEM; ++ invalid_cache_area(arg, tr.len); ++ } else { ++ printk(KERN_ERR "send a buffer to cmd(0x%08x) with_IOC_TYPE_NONE!\n", cmd); ++ return -EINVAL; ++ } ++ ctx.arg_size = _IOC_SIZE(cmd); ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctx.idx = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctx.idx < CTX_NUM) { ++ set_bit(ctx.idx, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ } else { ++ ctx.idx = 0; ++ } ++ if(ctx.idx < CTX_NUM) { ++ flush_cache_area(&ctx, sizeof(ctx)); ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!dev:%d, cmd:%d\n", __func__, ++ __LINE__, id, _IOC_NR(cmd)); ++ } ++ } ++ Chip_Flush_MIU_Pipe(); ++ while(1) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, __pa((long)&ctx), cmd, __pa((unsigned long)arg)); ++ if (down_timeout(device_sem+ctx.idx, FIVE_SEC) == 0) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, __pa((long)&ctx), cmd, __pa((unsigned long)arg)); ++ if(res != -2) { ++ break; ++ } else { ++ printk(KERN_ERR "bug found at %s %d\n", __func__, __LINE__); ++ *(int*)0 = 0; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!dev:%d, cmd:%d\n", __func__, ++ __LINE__, id, _IOC_NR(cmd)); ++ } ++ } ++ clear_bit(ctx.idx, ctx_bitmap); ++ up(&ctx_sem); ++ cost = ctx_cost+ctx.idx; ++ freq = ctx_freq+ctx.idx; ++ rval = res; ++ if(_IOC_DIR(cmd) & _IOC_READ) { ++ invalid_cache_area(arg, tr.len); ++ if (copy_to_user((char*)(long)tr.ptr, arg, tr.len)) ++ return -EFAULT; ++ } ++ kfree(arg); ++ } else { ++ int ctxid; ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctxid = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctxid < CTX_NUM) { ++ set_bit(ctxid, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ if(ctxid < CTX_NUM) ++ break; ++ } else { ++ ctxid = 0; ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!dev:%d, cmd:%d\n", __func__, ++ __LINE__, id, _IOC_NR(cmd)); ++ } ++ } ++ while(1) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, ctxid, cmd, 0); ++ if (down_timeout(device_sem+ctxid, FIVE_SEC) == 0) { ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, ctxid, cmd, 0); ++ if(res != -2) { ++ break; ++ } else { ++ printk(KERN_ERR "bug found at %s %d\n", __func__, __LINE__); ++ *(int*)0 = 0; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!dev:%d, cmd:%d\n", __func__, ++ __LINE__, id, _IOC_NR(cmd)); ++ } ++ } ++ clear_bit(ctxid, ctx_bitmap); ++ up(&ctx_sem); ++ cost = ctx_cost+ctxid; ++ freq = ctx_freq+ctxid; ++ rval = res; ++ } ++ t2 = ktime_get(); ++ atomic_inc(freq); ++ atomic_inc(*cost+time_log2(t1, t2)); ++ }else{ ++ unsigned long *vir = filp->private_data+cmd; ++ unsigned long uval; ++ get_user(uval, vir); ++ printk("uva:%p,phy:%lx,off=%x,uval=%lx\n", vir, vir2phy(current, vir), cmd, uval); ++ rval = 0; ++ } ++ return rval; ++} ++static int MI_DEVICE_Mmap(struct file *file, struct vm_area_struct *vma) { ++ static const struct vm_operations_struct vma_ops = {}; ++ size_t size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff, ++ size, ++ vma->vm_page_prot); ++ ++ vma->vm_ops = &vma_ops; ++ ++ /* Remap-pfn-range will mark the range VM_IO */ ++ if (remap_pfn_range(vma, ++ vma->vm_start, ++ vma->vm_pgoff, ++ size, ++ vma->vm_page_prot)) { ++ return -EAGAIN; ++ } ++ return 0; ++} ++static const struct file_operations fops = { ++ .owner = THIS_MODULE, ++ .open = MI_DEVICE_Open, ++ .release = MI_DEVICE_Release, ++ .unlocked_ioctl = MI_DEVICE_Ioctl, ++ .mmap = MI_DEVICE_Mmap, ++ .llseek = noop_llseek, ++}; ++module_param(mma_base,ulong,0644); ++module_param(mma_size,ulong,0644); ++static unsigned long rtk_base(void){ ++ return signal_rtos(INTEROS_SC_L2R_HANDSHAKE, 0, 0, 0); ++} ++ ++static ssize_t proc_read(struct seq_file* q, void* v) ++{ ++ struct proc_dev *pd = q->private; ++ unsigned long res = 0; ++ unsigned long logpage = get_zeroed_page(GFP_KERNEL); ++ linux_ctx ctx = {.log_base = __pa(logpage), .idx = -1, .devid = pd->devid}; ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctx.idx = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctx.idx < CTX_NUM) { ++ set_bit(ctx.idx, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ } else { ++ ctx.idx = 0; ++ } ++ if(ctx.idx < CTX_NUM) { ++ flush_cache_area(&ctx, sizeof(ctx)); ++ Chip_Flush_MIU_Pipe(); ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!\n", __func__, __LINE__); ++ } ++ } ++ ++ invalid_cache_area((void*)logpage, PAGE_SIZE); ++ ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+pd->modid, __pa((long)&ctx), -1, __MI_DEVICE_PROC_IO); ++ ++ do { ++ struct proc_buffer *pb = (struct proc_buffer*)logpage; ++ down(device_sem+ctx.idx); ++ ++ if(pb->cost > 0){ ++ seq_write(q, pb->buf, pb->cost); ++ }else{ ++ printk(KERN_WARNING "wake up with nothing!\n"); ++ } ++ invalid_cache_area((void*)logpage, PAGE_SIZE); ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+pd->modid, ctx.idx, -1, __MI_DEVICE_PROC_READLOG); ++ }while(res); ++ ++ clear_bit(ctx.idx, ctx_bitmap); ++ up(&ctx_sem); ++ free_page(logpage); ++ return 0; ++} ++ ++static ssize_t proc_write(struct file* file, const char __user* user_buf, size_t count, loff_t* ppos) ++{ ++ unsigned long args[32] = {0ul}; ++ const char *lcmd; ++ int c = 0; ++ char *p, tc, *kbuf; ++ ++ struct seq_file *q = file->private_data; ++ struct proc_dev *pd = q->private; ++ ++ kbuf = memdup_user(user_buf, count); ++ if(!kbuf) ++ return -ENOMEM; ++ ++ for(p = kbuf, tc = '\0'; tc != '\n' && (c < 32); ++p){ ++ p += strspn(p, " \t\r\f\v"); ++ if(*p == '\n') ++ break; ++ args[c++] = __pa(p); ++ p += strcspn(p, " \t\n\r\f\v"); ++ tc = *p; ++ *p = '\0'; ++ } ++ lcmd = __va(args[0]); ++ ++ if(c < 32) { ++ /* search cmd and exec */ ++ char *iter = pd->cmd_list, *cmd, *end = pd->cmd_list+pd->next; ++ while(iter < end){ ++ cmd = iter; ++ while(*iter++) ++ ; ++ if(strcmp(cmd, lcmd) == 0){ ++ unsigned long res = 0; ++ unsigned long logpage = get_zeroed_page(GFP_KERNEL); ++ linux_ctx ctx = {.cmd = __pa(args), .log_base = __pa(logpage), .arg_size = c, .idx = -1, .devid = pd->devid}; ++ while(1) { ++ if(down_timeout(&ctx_sem, FIVE_SEC) == 0){ ++ if(CTX_NUM > 1){ ++ spin_lock(&ctx_lock); ++ ctx.idx = find_first_zero_bit(ctx_bitmap, 32); ++ if(ctx.idx < CTX_NUM) { ++ set_bit(ctx.idx, ctx_bitmap); ++ } ++ spin_unlock(&ctx_lock); ++ } else { ++ ctx.idx = 0; ++ } ++ if(ctx.idx < CTX_NUM) { ++ flush_cache_area(args, sizeof(long)*c); ++ flush_cache_area(kbuf, count); ++ flush_cache_area(&ctx, sizeof(ctx)); ++ Chip_Flush_MIU_Pipe(); ++ break; ++ } ++ } else { ++ printk(KERN_WARNING "dead lock check at %s %d!\n", __func__, __LINE__); ++ } ++ } ++ invalid_cache_area((void*)logpage, PAGE_SIZE); ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+pd->modid, __pa((long)&ctx), -1, __MI_DEVICE_PROC_IO); ++ do { ++ struct proc_buffer *pb = (struct proc_buffer*)logpage; ++ down(device_sem+ctx.idx); ++ if(pb->cost > 0){ ++ printk("%s", pb->buf); ++ memset(pb->buf, 0, pb->cost); ++ }else{ ++ printk(KERN_WARNING "wake up with nothing!\n"); ++ } ++ invalid_cache_area((void*)logpage, PAGE_SIZE); ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+pd->modid, ctx.idx, -1, __MI_DEVICE_PROC_READLOG); ++ } while(res); ++ ++ clear_bit(ctx.idx, ctx_bitmap); ++ up(&ctx_sem); ++ free_page(logpage); ++ kfree(kbuf); ++ return count; ++ } ++ } ++ } ++ kfree(kbuf); ++ return -EINVAL; ++} ++ ++static int proc_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, proc_read, PDE_DATA(inode)); ++} ++ ++static const struct file_operations proc_ops = { ++ .owner = THIS_MODULE, ++ .open = proc_open, ++ .read = seq_read, ++ .write = proc_write, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static void fetch_proc(int id, const char *name){ ++ unsigned long res = 0; ++ unsigned long zpage = get_zeroed_page(GFP_KERNEL); ++ struct proc_dev *pd = (struct proc_dev*)zpage; ++ invalid_cache_area(pd, PAGE_SIZE); ++ res = signal_rtos(INTEROS_SC_L2R_MI_CALL_START+id, __pa(pd), -1, __MI_DEVICE_PROC); ++ if(res != __pa(pd)){ ++ char path[32] = "mi_"; ++ struct proc_dir_entry *dir; ++ int len = res-__pa(pd); ++ proc_list[id] = pd = kmemdup(pd, len, GFP_KERNEL); ++ strcat(path, name); ++ dir = proc_mkdir(path, proc_root); ++ do{ ++ //char *iter = pd->cmd_list, *cmd, *end = pd->cmd_list+pd->next; ++ sprintf(path, "mi_%s%d", name, pd->devid); ++ proc_create_data(path, 0640, dir, &proc_ops, pd); ++ /* ++ while(iter < end){ ++ cmd = iter; ++ while(*iter++) ++ ; ++ }*/ ++ if((long)(pd->cmd_list+pd->next) != (long)proc_list[id]+len){ ++ pd = (struct proc_dev*)(pd->cmd_list+pd->next); ++ }else{ ++ break; ++ } ++ }while(1); ++ }else{ ++ proc_list[id] = NULL; ++ } ++ free_page(zpage); ++} ++ ++static ssize_t debug_tool_read(struct seq_file* q, void* v) ++{ ++ struct debug_tool *dt = q->private; ++ if(dt->read) ++ return dt->read(dt->obj); ++ return -EIO; ++} ++ ++static ssize_t debug_tool_write(struct file* file, const char __user* user_buf, size_t count, loff_t* ppos) ++{ ++ const char *args[32] = {NULL}; ++ int c = 0; ++ char *p, tc, *kbuf; ++ ++ struct seq_file *q = file->private_data; ++ struct debug_tool *dt = q->private; ++ ++ if(!dt->write) ++ return -EIO; ++ ++ kbuf = memdup_user(user_buf, count); ++ if(!kbuf) ++ return -ENOMEM; ++ ++ for(p = kbuf, tc = '\0'; tc != '\n' && (c < 32); ++p){ ++ p += strspn(p, " \t\r\f\v"); ++ if(*p == '\n') ++ break; ++ args[c++] = p; ++ p += strcspn(p, " \t\n\r\f\v"); ++ tc = *p; ++ *p = '\0'; ++ } ++ ++ if(c < 32) { ++ dt->write(dt->obj,args,c); ++ kfree(kbuf); ++ return count; ++ } ++ kfree(kbuf); ++ return -EINVAL; ++} ++ ++static int debug_tool_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debug_tool_read, PDE_DATA(inode)); ++} ++ ++static const struct file_operations debug_tool_ops = { ++ .owner = THIS_MODULE, ++ .open = debug_tool_open, ++ .read = seq_read, ++ .write = debug_tool_write, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static bool debug_tool_create(const char *name, struct debug_tool *dt){ ++ dt->entry = proc_create_data(name, 0640, debug_tools, &debug_tool_ops, dt); ++ if (!dt->entry) ++ { ++ printk(KERN_ERR "failed to create procfs file %s.\n",name); ++ return false; ++ } ++ return true; ++} ++ ++static void debug_tool_delete(struct debug_tool *dt){ ++ proc_remove(dt->entry); ++} ++ ++static void linux_adp_SyncPreloadStatus(void) ++{ ++ /* ++ * Fixme, always create "dualos/audio_init" and "dualos/video_init" here, ++ * need design a mechanism to sync preload status inside mi_sys. ++ */ ++ proc_mkdir("dualos/audio_init", NULL); ++ proc_mkdir("dualos/video_init", NULL); ++} ++ ++static int __init linux_adaptor_init(void) { ++ const char *dev_list[] = { ++ "ive", /* 0 */ ++ "vdf", /* 1 */ ++ "venc", /* 2 */ ++ "rgn", /* 3 */ ++ "ai", /* 4 */ ++ "ao", /* 5 */ ++ "vif", /* 6 */ ++ "vpe", /* 7 */ ++ "vdec", /* 8 */ ++ "sys", /* 9 */ ++ "fb", /* 10 */ ++ "hdmi", /* 11 */ ++ "divp", /* 12 */ ++ "gfx", /* 13 */ ++ "vdisp", /* 14 */ ++ "disp", /* 15 */ ++ "os", /* 16 */ ++ "iae", /* 17 */ ++ "md", /* 18 */ ++ "od", /* 19 */ ++ "shadow", /* 20 */ ++ "warp", /* 21 */ ++ "uac", /* 22 */ ++ "ldc", /* 23 */ ++ "sd", /* 24 */ ++ "panel", /* 25 */ ++ "cipher", /* 26 */ ++ "sensor", /* 27 */ ++ "wlan", /* 28 */ ++ "ipu", /* 29 */ ++ "mipitx", /* 30 */ ++ }; ++ int err = 0, i; ++ ++ if (disable_os_adaptor) ++ return 0; ++ ++ if(E_MI_MODULE_ID_MAX < sizeof(dev_list)/sizeof(*dev_list)){ ++ return -EINVAL; ++ } ++ err = -EIO; ++ device_major = register_chrdev(0, "rtos-adaptor", &fops); ++ if(device_major <= 0) ++ goto fail_register_chrdev; ++ ++ device_class = class_create(THIS_MODULE, "rtos-adaptor"); ++ err = PTR_ERR(device_class); ++ if (IS_ERR(device_class)) ++ goto fail_class_create; ++ ++ proc_root = proc_mkdir("mi_modules", NULL); ++ for(i = 0; i < E_MI_MODULE_ID_MAX; ++i){ ++ device_list[i] = device_create(device_class, ++ NULL, ++ MKDEV(device_major, i), ++ device_list+i, ++ "mi_%s", ++ dev_list[i]); ++ fetch_proc(i, dev_list[i]); ++ } ++ poll_major = register_chrdev(0, "poll-dev", &pfops); ++ if(poll_major <= 0) ++ goto fail_register_chrdev2; ++ ++ device_list[E_MI_MODULE_ID_MAX] = device_create(device_class, ++ NULL, ++ MKDEV(poll_major, 0), ++ device_list+E_MI_MODULE_ID_MAX, ++ "mi_poll"); ++ ++ if(device_list[E_MI_MODULE_ID_MAX] == NULL) ++ goto fail_create_poll_dev; ++ ++ for(i = 0; i < CTX_NUM; ++i) ++ sema_init(device_sem+i, 0); ++ sema_init(&ctx_sem, CTX_NUM); ++ atomic_set(&device_ref, 0); ++ spin_lock_init(&ctx_lock); ++ for(i = 0; i < 32; ++i) ++ clear_bit(i, ctx_bitmap); ++ rtk_res = request_mem_region(mma_base, mma_size, "mma"); ++ if(!rtk_res){ ++ goto fail_mem_req; ++ } ++ printk("#map req:(0x%x,0x%x)|0x%lx\n", rtk_res->start, resource_size(rtk_res), rtk_base()); ++ debug_tools = proc_mkdir("adaptor-debug-tools", NULL); ++ if(!debug_tools) ++ goto fail_create_debug_tools; ++ ++ if(!debug_tool_create("syscall_cost", &syscall_cost_column)) ++ goto fail_create_syscall_cost; ++ ++ if(!debug_tool_create("syscall_freq", &syscall_freq_linear.dt)) ++ goto fail_create_syscall_freq; ++ ++ if(!debug_tool_create("info_tool", &info_tool.dt)) ++ goto fail_create_info_tool; ++ ++ linux_adp_SyncPreloadStatus(); ++ ++ alkaid_registe_notify(0, alkaid_notify); ++ printk("register notify\n"); ++ ++ alkaid_poll_init(); ++ printk("poll init dev\n"); ++ ++ printk("linux-adaptor init success!(%s)\n", __TIME__); ++ return 0; ++ ++fail_create_info_tool: ++ printk(KERN_ERR "create info tool failed!\n"); ++ debug_tool_delete(&syscall_freq_linear.dt); ++fail_create_syscall_freq: ++ printk(KERN_ERR "create syscall freq analyzer failed!\n"); ++ debug_tool_delete(&syscall_cost_column); ++fail_create_syscall_cost: ++ printk(KERN_ERR "create syscall cost analyzer failed!\n"); ++ proc_remove(debug_tools); ++fail_create_debug_tools: ++ printk(KERN_ERR "proc mkdir failed!\n"); ++ release_mem_region(rtk_res->start, mma_size); ++fail_mem_req: ++ printk(KERN_ERR "request mem failed\n"); ++ device_destroy(device_class, MKDEV(poll_major, 0)); ++fail_create_poll_dev: ++ printk(KERN_ERR "create poll dev failed\n"); ++ unregister_chrdev(poll_major, "poll-dev"); ++fail_register_chrdev2: ++ printk(KERN_ERR "unable to get mi device\n"); ++ for(i = 0; i < E_MI_MODULE_ID_MAX; ++i){ ++ if(device_list[i]) ++ device_destroy(device_class, MKDEV(device_major, i)); ++ } ++ unregister_chrdev(device_major, "rtos-adaptor"); ++fail_class_create: ++ printk(KERN_ERR "fail create class\n"); ++fail_register_chrdev: ++ printk(KERN_ERR "unable to get mi device\n"); ++ class_destroy(device_class); ++ return err; ++} ++module_init(linux_adaptor_init) ++ ++static void __exit linux_adaptor_exit(void) { ++ int i; ++ debug_tool_delete(&info_tool.dt); ++ debug_tool_delete(&syscall_freq_linear.dt); ++ debug_tool_delete(&syscall_cost_column); ++ proc_remove(debug_tools); ++ release_mem_region(rtk_res->start, mma_size); ++ device_destroy(device_class, MKDEV(poll_major, 0)); ++ unregister_chrdev(poll_major, "poll-dev"); ++ for(i = 0; i < E_MI_MODULE_ID_MAX; ++i){ ++ if(device_list[i]) ++ device_destroy(device_class, MKDEV(device_major, i)); ++ } ++ unregister_chrdev(device_major, "rtos-adaptor"); ++ class_destroy(device_class); ++} ++module_exit(linux_adaptor_exit) ++ ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/bdma/Kconfig b/drivers/sstar/bdma/Kconfig +new file mode 100755 +index 000000000000..88628feac85a +--- /dev/null ++++ b/drivers/sstar/bdma/Kconfig +@@ -0,0 +1,10 @@ ++config MS_BDMA ++ bool "Mstar BDMA driver" ++ default n ++ help ++ ++config MS_BDMA_LINE_OFFSET_ON ++ bool "BDMA Line-Offset Enable" ++ depends on MS_BDMA ++ default n ++ help +diff --git a/drivers/sstar/bdma/Makefile b/drivers/sstar/bdma/Makefile +new file mode 100644 +index 000000000000..448f768021d2 +--- /dev/null ++++ b/drivers/sstar/bdma/Makefile +@@ -0,0 +1,3 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++obj-y += $(CONFIG_SSTAR_CHIP_NAME)/ +diff --git a/drivers/sstar/bdma/infinity2/Makefile b/drivers/sstar/bdma/infinity2/Makefile +new file mode 100755 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity2/hal_bdma.c b/drivers/sstar/bdma/infinity2/hal_bdma.c +new file mode 100755 +index 000000000000..c99701c3d928 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2/hal_bdma.c +@@ -0,0 +1,353 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_replace_miu = 0x0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++// g_ptKeBdma->reg_ch0_src_dw = ptBdmaParam->eSrcDataWidth; ++// g_ptKeBdma->reg_ch0_dst_dw = ptBdmaParam->eDstDataWidth; ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++EXPORT_SYMBOL(HalBdma_Transfer); ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity2/hal_bdma.h b/drivers/sstar/bdma/infinity2/hal_bdma.h +new file mode 100755 +index 000000000000..3914645d46e4 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2/hal_bdma.h +@@ -0,0 +1,101 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity2/kernel_bdma.h b/drivers/sstar/bdma/infinity2/kernel_bdma.h +new file mode 100755 +index 000000000000..ad5bf26c4b0b +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2/kernel_bdma.h +@@ -0,0 +1,130 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 ++ #define REG_BDMA_SRC_MEM_FILL 4 ++ #define REG_BDMA_SRC_SPI 5 ++ #define REG_BDMA_SRC_TSP_SRAM 10 ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++ ++ ++#endif // __KERNEL_BDMA_H__ +\ No newline at end of file +diff --git a/drivers/sstar/bdma/infinity2m/Makefile b/drivers/sstar/bdma/infinity2m/Makefile +new file mode 100644 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2m/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity2m/hal_bdma.c b/drivers/sstar/bdma/infinity2m/hal_bdma.c +new file mode 100644 +index 000000000000..f4348bcf32be +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2m/hal_bdma.c +@@ -0,0 +1,551 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++#endif ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++volatile KeBdma_t * const g_ptKeBdma2 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA2_PA); ++volatile KeBdma_t * const g_ptKeBdma3 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA3_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE, TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL, NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0, 0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma2_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma2->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma2->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[2] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[2]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[2]) { ++ m_pfBdmaTxDoneCBFunc[2](2); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma3_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma3->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma3->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[3] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[3]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[3]) { ++ m_pfBdmaTxDoneCBFunc[3](3); ++ } ++ return IRQ_HANDLED; ++} ++ ++void _HalBdmaPowerOn(struct device_node *dev_node) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0, i; ++ u32 BdmaClk; ++ void *pvBdmaclk = NULL; ++ u32 BdmaParentCnt = 1; ++#else ++ struct clk **bdma_clks; ++ struct clk *clk_parent; ++ int num_parents, i; ++#endif ++ // If any channel of BDMA is initialized, the power is already turn on ++ for (i = 0; i < HAL_BDMA_CH_NUM; i++) ++ { ++ if (m_bBdmaInited[i]) ++ return; ++ } ++#ifdef CONFIG_CAM_CLK ++ if(of_find_property(dev_node,"camclk",&BdmaParentCnt)) ++ { ++ BdmaParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(BdmaParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, BdmaParentCnt); ++ return; ++ } ++ for(u32clknum = 0; u32clknum < BdmaParentCnt; u32clknum++) ++ { ++ BdmaClk = 0; ++ of_property_read_u32_index(dev_node,"camclk", u32clknum,&(BdmaClk)); ++ if (!BdmaClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("BDMA",BdmaClk,&(pvBdmaclk)); ++ CamClkSetOnOff(pvBdmaclk,1); ++ CamClkUnregister(pvBdmaclk); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#else ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev_node); ++ if(num_parents > 0) ++ { ++ bdma_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(bdma_clks == NULL) ++ { ++ printk( "[BDMA]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ bdma_clks[i] = of_clk_get(dev_node, i); ++ if (IS_ERR(bdma_clks[i])) ++ { ++ printk( "Fail to get BDMA clk!\n" ); ++ clk_put(bdma_clks[i]); ++ kfree(bdma_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(bdma_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(bdma_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ printk( "[BDMA]can't get parent clock\n" ); ++ clk_put(bdma_clks[i]); ++ kfree(bdma_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(bdma_clks[i], clk_parent); ++ clk_prepare_enable(bdma_clks[i]); ++ clk_put(bdma_clks[i]); ++ } ++ kfree(bdma_clks); ++ } ++#endif ++#endif ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ ++ _HalBdmaPowerOn(dev_node); ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ case HAL_BDMA_CH2: ++ pfIrqHandler = HalBdma2_ISR; ++ break; ++ case HAL_BDMA_CH3: ++ pfIrqHandler = HalBdma3_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity2m/hal_bdma.h b/drivers/sstar/bdma/infinity2m/hal_bdma.h +new file mode 100644 +index 000000000000..5800afa3c97f +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2m/hal_bdma.h +@@ -0,0 +1,104 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH2, ++ HAL_BDMA_CH3, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ ++ +diff --git a/drivers/sstar/bdma/infinity2m/kernel_bdma.h b/drivers/sstar/bdma/infinity2m/kernel_bdma.h +new file mode 100644 +index 000000000000..027f7ed92ae6 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity2m/kernel_bdma.h +@@ -0,0 +1,133 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes ++ #define REG_BDMA_SRC_MEM_FILL 4 //4 bytes ++ #define REG_BDMA_SRC_SPI 5 //8 bytes ++ #define REG_BDMA_SRC_TSP_SRAM 10 //1 byte ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ #define REG_BDMA_SDT_FSP 11 //4 byte ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++extern volatile KeBdma_t* const g_ptKeBdma2; ++extern volatile KeBdma_t* const g_ptKeBdma3; ++ ++#endif // __KERNEL_BDMA_H__ ++ +diff --git a/drivers/sstar/bdma/infinity3/Makefile b/drivers/sstar/bdma/infinity3/Makefile +new file mode 100644 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity3/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity3/hal_bdma.c b/drivers/sstar/bdma/infinity3/hal_bdma.c +new file mode 100644 +index 000000000000..f3f6f8a86f85 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity3/hal_bdma.c +@@ -0,0 +1,447 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++volatile KeBdma_t * const g_ptKeBdma2 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA2_PA); ++volatile KeBdma_t * const g_ptKeBdma3 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA3_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE, TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL, NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0, 0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma2_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma2->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma2->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[2] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[2]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[2]) { ++ m_pfBdmaTxDoneCBFunc[2](2); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma3_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma3->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma3->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[3] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[3]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[3]) { ++ m_pfBdmaTxDoneCBFunc[3](3); ++ } ++ return IRQ_HANDLED; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ case HAL_BDMA_CH2: ++ pfIrqHandler = HalBdma2_ISR; ++ break; ++ case HAL_BDMA_CH3: ++ pfIrqHandler = HalBdma3_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity3/hal_bdma.h b/drivers/sstar/bdma/infinity3/hal_bdma.h +new file mode 100644 +index 000000000000..017f73db8b7a +--- /dev/null ++++ b/drivers/sstar/bdma/infinity3/hal_bdma.h +@@ -0,0 +1,103 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH2, ++ HAL_BDMA_CH3, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity3/kernel_bdma.h b/drivers/sstar/bdma/infinity3/kernel_bdma.h +new file mode 100644 +index 000000000000..876579f145e8 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity3/kernel_bdma.h +@@ -0,0 +1,132 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes ++ #define REG_BDMA_SRC_MEM_FILL 4 //4 bytes ++ #define REG_BDMA_SRC_SPI 5 //8 bytes ++ #define REG_BDMA_SRC_TSP_SRAM 10 //1 byte ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ #define REG_BDMA_SDT_FSP 11 //4 byte ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++extern volatile KeBdma_t* const g_ptKeBdma2; ++extern volatile KeBdma_t* const g_ptKeBdma3; ++ ++#endif // __KERNEL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity5/Makefile b/drivers/sstar/bdma/infinity5/Makefile +new file mode 100644 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity5/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity5/hal_bdma.c b/drivers/sstar/bdma/infinity5/hal_bdma.c +new file mode 100644 +index 000000000000..f3f6f8a86f85 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity5/hal_bdma.c +@@ -0,0 +1,447 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++volatile KeBdma_t * const g_ptKeBdma2 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA2_PA); ++volatile KeBdma_t * const g_ptKeBdma3 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA3_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE, TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL, NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0, 0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma2_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma2->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma2->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[2] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[2]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[2]) { ++ m_pfBdmaTxDoneCBFunc[2](2); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma3_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma3->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma3->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[3] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[3]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[3]) { ++ m_pfBdmaTxDoneCBFunc[3](3); ++ } ++ return IRQ_HANDLED; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ case HAL_BDMA_CH2: ++ pfIrqHandler = HalBdma2_ISR; ++ break; ++ case HAL_BDMA_CH3: ++ pfIrqHandler = HalBdma3_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity5/hal_bdma.h b/drivers/sstar/bdma/infinity5/hal_bdma.h +new file mode 100644 +index 000000000000..017f73db8b7a +--- /dev/null ++++ b/drivers/sstar/bdma/infinity5/hal_bdma.h +@@ -0,0 +1,103 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH2, ++ HAL_BDMA_CH3, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity5/kernel_bdma.h b/drivers/sstar/bdma/infinity5/kernel_bdma.h +new file mode 100755 +index 000000000000..876579f145e8 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity5/kernel_bdma.h +@@ -0,0 +1,132 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes ++ #define REG_BDMA_SRC_MEM_FILL 4 //4 bytes ++ #define REG_BDMA_SRC_SPI 5 //8 bytes ++ #define REG_BDMA_SRC_TSP_SRAM 10 //1 byte ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ #define REG_BDMA_SDT_FSP 11 //4 byte ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++extern volatile KeBdma_t* const g_ptKeBdma2; ++extern volatile KeBdma_t* const g_ptKeBdma3; ++ ++#endif // __KERNEL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity6/Makefile b/drivers/sstar/bdma/infinity6/Makefile +new file mode 100644 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity6/hal_bdma.c b/drivers/sstar/bdma/infinity6/hal_bdma.c +new file mode 100644 +index 000000000000..f3f6f8a86f85 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6/hal_bdma.c +@@ -0,0 +1,447 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++volatile KeBdma_t * const g_ptKeBdma2 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA2_PA); ++volatile KeBdma_t * const g_ptKeBdma3 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA3_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE, TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL, NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0, 0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma2_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma2->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma2->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[2] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[2]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[2]) { ++ m_pfBdmaTxDoneCBFunc[2](2); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma3_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma3->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma3->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[3] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[3]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[3]) { ++ m_pfBdmaTxDoneCBFunc[3](3); ++ } ++ return IRQ_HANDLED; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ case HAL_BDMA_CH2: ++ pfIrqHandler = HalBdma2_ISR; ++ break; ++ case HAL_BDMA_CH3: ++ pfIrqHandler = HalBdma3_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity6/hal_bdma.h b/drivers/sstar/bdma/infinity6/hal_bdma.h +new file mode 100644 +index 000000000000..017f73db8b7a +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6/hal_bdma.h +@@ -0,0 +1,103 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH2, ++ HAL_BDMA_CH3, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity6/kernel_bdma.h b/drivers/sstar/bdma/infinity6/kernel_bdma.h +new file mode 100755 +index 000000000000..876579f145e8 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6/kernel_bdma.h +@@ -0,0 +1,132 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes ++ #define REG_BDMA_SRC_MEM_FILL 4 //4 bytes ++ #define REG_BDMA_SRC_SPI 5 //8 bytes ++ #define REG_BDMA_SRC_TSP_SRAM 10 //1 byte ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ #define REG_BDMA_SDT_FSP 11 //4 byte ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++extern volatile KeBdma_t* const g_ptKeBdma2; ++extern volatile KeBdma_t* const g_ptKeBdma3; ++ ++#endif // __KERNEL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity6b0/Makefile b/drivers/sstar/bdma/infinity6b0/Makefile +new file mode 100755 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6b0/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity6b0/hal_bdma.c b/drivers/sstar/bdma/infinity6b0/hal_bdma.c +new file mode 100755 +index 000000000000..f3f6f8a86f85 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6b0/hal_bdma.c +@@ -0,0 +1,447 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++volatile KeBdma_t * const g_ptKeBdma2 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA2_PA); ++volatile KeBdma_t * const g_ptKeBdma3 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA3_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE, TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL, NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0, 0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma2_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma2->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma2->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[2] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[2]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[2]) { ++ m_pfBdmaTxDoneCBFunc[2](2); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma3_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma3->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma3->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[3] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[3]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[3]) { ++ m_pfBdmaTxDoneCBFunc[3](3); ++ } ++ return IRQ_HANDLED; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ case HAL_BDMA_CH2: ++ pfIrqHandler = HalBdma2_ISR; ++ break; ++ case HAL_BDMA_CH3: ++ pfIrqHandler = HalBdma3_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity6b0/hal_bdma.h b/drivers/sstar/bdma/infinity6b0/hal_bdma.h +new file mode 100755 +index 000000000000..017f73db8b7a +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6b0/hal_bdma.h +@@ -0,0 +1,103 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH2, ++ HAL_BDMA_CH3, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity6b0/kernel_bdma.h b/drivers/sstar/bdma/infinity6b0/kernel_bdma.h +new file mode 100755 +index 000000000000..876579f145e8 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6b0/kernel_bdma.h +@@ -0,0 +1,132 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes ++ #define REG_BDMA_SRC_MEM_FILL 4 //4 bytes ++ #define REG_BDMA_SRC_SPI 5 //8 bytes ++ #define REG_BDMA_SRC_TSP_SRAM 10 //1 byte ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ #define REG_BDMA_SDT_FSP 11 //4 byte ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++extern volatile KeBdma_t* const g_ptKeBdma2; ++extern volatile KeBdma_t* const g_ptKeBdma3; ++ ++#endif // __KERNEL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity6e/Makefile b/drivers/sstar/bdma/infinity6e/Makefile +new file mode 100644 +index 000000000000..e390cde67af3 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6e/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_bdma.o +diff --git a/drivers/sstar/bdma/infinity6e/hal_bdma.c b/drivers/sstar/bdma/infinity6e/hal_bdma.c +new file mode 100644 +index 000000000000..fc1667d822a1 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6e/hal_bdma.c +@@ -0,0 +1,758 @@ ++/* ++* hal_bdma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_bdma.h" ++#include "hal_bdma.h" ++#include "cam_os_wrapper.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global variable ++//////////////////////////////////////////////////////////////////////////////// ++ ++volatile KeBdma_t * const g_ptKeBdma0 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA0_PA); ++volatile KeBdma_t * const g_ptKeBdma1 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA1_PA); ++volatile KeBdma_t * const g_ptKeBdma2 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA2_PA); ++volatile KeBdma_t * const g_ptKeBdma3 = (KeBdma_t *)IO_ADDRESS(BASE_REG_BDMA3_PA); ++ ++static bool m_bBdmaFree[HAL_BDMA_CH_NUM] = {TRUE, TRUE, TRUE, TRUE}; ++static HalBdmaTxCb m_pfBdmaTxDoneCBFunc[HAL_BDMA_CH_NUM] = {NULL, NULL, NULL, NULL}; ++static bool m_bBdmaInited[HAL_BDMA_CH_NUM] = {0, 0, 0, 0}; ++static CamOsTsem_t m_stBdmaSemID[HAL_BDMA_CH_NUM]; ++ ++/*=============================================================*/ ++// Local function definition ++/*=============================================================*/ ++ ++static u32 _HalBdmaVA2MiuA(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ return HalUtilPHY2MIUAddr(phyAddr); ++#endif ++} ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++static irqreturn_t HalBdma0_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma0->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma0->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[0] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[0]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[0]) { ++ m_pfBdmaTxDoneCBFunc[0](0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma1_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma1->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma1->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[1] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[1]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[1]) { ++ m_pfBdmaTxDoneCBFunc[1](1); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma2_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma2->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma2->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[2] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[2]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[2]) { ++ m_pfBdmaTxDoneCBFunc[2](2); ++ } ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t HalBdma3_ISR(int irq, void* priv) ++{ ++ g_ptKeBdma3->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma3->reg_ch0_int_en = 0x0; ++ ++ m_bBdmaFree[3] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[3]); ++ ++ if (NULL != m_pfBdmaTxDoneCBFunc[3]) { ++ m_pfBdmaTxDoneCBFunc[3](3); ++ } ++ return IRQ_HANDLED; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : _HalBdma_EnClkOnce ++// Description : ++//------------------------------------------------------------------------------ ++static void _HalBdma_EnClkOnce(struct device_node *dev_node) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0, i; ++ u32 BdmaClk; ++ void *pvBdmaclk = NULL; ++ u32 BdmaParentCnt = 1; ++#else ++ struct clk **bdma_clks; ++ int num_parents, i; ++#endif ++ ++ // If any channel of BDMA is initialized, the power is already turn on ++ for (i = 0; i < HAL_BDMA_CH_NUM; i++) ++ { ++ if (m_bBdmaInited[i]) ++ return; ++ } ++ ++#ifdef CONFIG_CAM_CLK ++ if(of_find_property(dev_node,"camclk",&BdmaParentCnt)) ++ { ++ BdmaParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(BdmaParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, BdmaParentCnt); ++ return; ++ } ++ for(u32clknum = 0; u32clknum < BdmaParentCnt; u32clknum++) ++ { ++ BdmaClk = 0; ++ of_property_read_u32_index(dev_node,"camclk", u32clknum,&(BdmaClk)); ++ if (!BdmaClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("BDMA",BdmaClk,&(pvBdmaclk)); ++ CamClkSetOnOff(pvBdmaclk,1); ++ CamClkUnregister(pvBdmaclk); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#else ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev_node); ++ if(num_parents > 0) ++ { ++ bdma_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(bdma_clks == NULL) ++ { ++ printk( "[BDMA]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ bdma_clks[i] = of_clk_get(dev_node, i); ++ if (IS_ERR(bdma_clks[i])) ++ { ++ printk( "Fail to get BDMA clk!\n" ); ++ clk_put(bdma_clks[i]); ++ kfree(bdma_clks); ++ return; ++ } ++ else { ++ /* Set clock parent */ ++ clk_prepare_enable(bdma_clks[i]); ++ clk_put(bdma_clks[i]); ++ } ++ } ++ kfree(bdma_clks); ++ } ++#endif ++#endif ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh) ++{ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,bdma%d", u8DmaCh); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ return HAL_BDMA_ERROR; ++ } ++ /* Enable clock */ ++ _HalBdma_EnClkOnce(dev_node); ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ pfIrqHandler = HalBdma0_ISR; ++ break; ++ case HAL_BDMA_CH1: ++ pfIrqHandler = HalBdma1_ISR; ++ break; ++ case HAL_BDMA_CH2: ++ pfIrqHandler = HalBdma2_ISR; ++ break; ++ case HAL_BDMA_CH3: ++ pfIrqHandler = HalBdma3_ISR; ++ break; ++ default: ++ return HAL_BDMA_ERROR; ++ break; ++ } ++ ++ if (0 != request_irq(iIrqNum, pfIrqHandler, 0, "BdmaIsr", NULL)) { ++ CamOsPrintf("[BDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_BDMA_ERROR; ++ } ++ else { ++ //CamOsPrintf("[BDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stBdmaSemID[u8DmaCh], 1); ++ ++ m_bBdmaInited[u8DmaCh] = 1; ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ // Disable LineOffset ++ g_ptKeBdma->reg_ch0_offset_en = 0; ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_Transfer_LineOffset ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA starts to transfer data ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_Transfer_LineOffset(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma = g_ptKeBdma0; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ CamOsTsemDown(&m_stBdmaSemID[u8DmaCh]); ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ m_bBdmaFree[u8DmaCh] = FALSE; ++ ++ m_pfBdmaTxDoneCBFunc[u8DmaCh] = (HalBdmaTxCb)ptBdmaParam->pfTxCbFunc; ++ ++ g_ptKeBdma->reg_ch0_busy = 0x1; ++ g_ptKeBdma->reg_ch0_int_bdma = 0x1; ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ switch(ptBdmaParam->ePathSel) ++ { ++ case HAL_BDMA_MIU0_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU0_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU0 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MIU1_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_MIU1 | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_IMI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MIU_IMI_CH0; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH0_IMI | REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_MEM_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_MEM_FILL; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_4BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU0: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU0; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_MIU1: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_MIU1; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ case HAL_BDMA_SPI_TO_IMI: ++ g_ptKeBdma->reg_ch0_src_sel = REG_BDMA_SRC_SPI; ++ g_ptKeBdma->reg_ch0_dst_sel = REG_BDMA_SRC_MIU_IMI_CH1; ++ g_ptKeBdma->reg_ch0_replace_miu = REG_BDMA_CH1_IMI; ++ g_ptKeBdma->reg_ch0_src_dw = REG_BDMA_DATA_DEPTH_8BYTE; ++ g_ptKeBdma->reg_ch0_dst_dw = REG_BDMA_DATA_DEPTH_16BYTE; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Set Source / Destination Address ++ if ((HAL_BDMA_MEM_TO_MIU0 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_MIU1 == ptBdmaParam->ePathSel) || ++ (HAL_BDMA_MEM_TO_IMI == ptBdmaParam->ePathSel)) { ++ g_ptKeBdma->reg_ch0_cmd0_low = (U16)(ptBdmaParam->u32Pattern & 0xFFFF); ++ g_ptKeBdma->reg_ch0_cmd0_high = (U16)(ptBdmaParam->u32Pattern >> 16); ++ } ++ else { ++ g_ptKeBdma->reg_ch0_src_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pSrcAddr) >> 16); ++ } ++ ++ g_ptKeBdma->reg_ch0_dst_a0 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_a1 = (U16)(_HalBdmaVA2MiuA(ptBdmaParam->pDstAddr) >> 16); ++ ++ // Set Transfer Size ++ g_ptKeBdma->reg_ch0_size0 = (U16)(ptBdmaParam->u32TxCount & 0xFFFF); ++ g_ptKeBdma->reg_ch0_size1 = (U16)(ptBdmaParam->u32TxCount >> 16); ++ ++ /* Set LineOffset Attribute */ ++ if (ptBdmaParam->bEnLineOfst == TRUE) { ++ g_ptKeBdma->reg_ch0_src_width_low = (U16)(ptBdmaParam->pstLineOfst->u32SrcWidth & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_width_high = (U16)(ptBdmaParam->pstLineOfst->u32SrcWidth >> 16); ++ g_ptKeBdma->reg_ch0_src_offset_low = (U16)(ptBdmaParam->pstLineOfst->u32SrcOffset & 0xFFFF); ++ g_ptKeBdma->reg_ch0_src_offset_high = (U16)(ptBdmaParam->pstLineOfst->u32SrcOffset >> 16); ++ g_ptKeBdma->reg_ch0_dst_width_low = (U16)(ptBdmaParam->pstLineOfst->u32DstWidth & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_width_high = (U16)(ptBdmaParam->pstLineOfst->u32DstWidth >> 16); ++ g_ptKeBdma->reg_ch0_dst_offset_low = (U16)(ptBdmaParam->pstLineOfst->u32DstOffset & 0xFFFF); ++ g_ptKeBdma->reg_ch0_dst_offset_high = (U16)(ptBdmaParam->pstLineOfst->u32DstOffset >> 16); ++ g_ptKeBdma->reg_ch0_offset_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_offset_en = 0; ++ } ++ ++ ++ // Set Interrupt Enable ++ if (ptBdmaParam->bIntMode) { ++ g_ptKeBdma->reg_ch0_int_en = 1; ++ } ++ else { ++ g_ptKeBdma->reg_ch0_int_en = 0; ++ } ++ ++ // Trigger ++ g_ptKeBdma->reg_ch0_trig = 0x1; ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ HalBdma_WaitTransferDone(u8DmaCh, ptBdmaParam); ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} ++ ++ ++//------------------------------------------------------------------------------ ++// Function : HalBdma_WaitTransferDone ++// Description : ++//------------------------------------------------------------------------------ ++/** ++ * @brief BDMA wait transfer data done ++ * ++ * @param [in] ptBdmaParam BDMA configuration parameter ++ * ++ * @return HalBdmaErr_e BDMA error code ++ */ ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam) ++{ ++ volatile KeBdma_t* g_ptKeBdma; ++ U32 u32TimeOut = 0x00FFFFFF; ++ bool bRet = FALSE; ++ ++ if (!m_bBdmaInited[u8DmaCh]) { ++ return HAL_BDMA_PROC_DONE; ++ } ++ ++ switch(u8DmaCh) { ++ case HAL_BDMA_CH0: ++ g_ptKeBdma = g_ptKeBdma0; ++ break; ++ case HAL_BDMA_CH1: ++ g_ptKeBdma = g_ptKeBdma1; ++ break; ++ case HAL_BDMA_CH2: ++ g_ptKeBdma = g_ptKeBdma2; ++ break; ++ case HAL_BDMA_CH3: ++ g_ptKeBdma = g_ptKeBdma3; ++ break; ++ default: ++ return HAL_BDMA_PROC_DONE; ++ break; ++ } ++ ++ // Polling mode ++ if (!ptBdmaParam->bIntMode) { ++ ++ while(--u32TimeOut) ++ { ++ // Check done ++ if (g_ptKeBdma->reg_ch0_done == 0x1) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ ++ // Clear done ++ g_ptKeBdma->reg_ch0_done = 0x1; ++ ++ m_bBdmaFree[u8DmaCh] = TRUE; ++ CamOsTsemUp(&m_stBdmaSemID[u8DmaCh]); ++ ++ if (bRet == FALSE) { ++ CamOsPrintf("Wait BDMA Done Fail\r\n"); ++ return HAL_BDMA_POLLING_TIMEOUT; ++ } ++ } ++ else { ++ // Interrupt mode ++ } ++ ++ return HAL_BDMA_PROC_DONE; ++} +diff --git a/drivers/sstar/bdma/infinity6e/hal_bdma.h b/drivers/sstar/bdma/infinity6e/hal_bdma.h +new file mode 100644 +index 000000000000..6c99c2402d8c +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6e/hal_bdma.h +@@ -0,0 +1,115 @@ ++/* ++* hal_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __HAL_BDMA_H__ ++#define __HAL_BDMA_H__ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++typedef enum ++{ ++ HAL_BDMA_PROC_DONE = 0, ++ HAL_BDMA_ERROR = -1, ++ HAL_BDMA_POLLING_TIMEOUT = -2 ++} HalBdmaErr_e; ++ ++typedef enum ++{ ++ HAL_BDMA_CH0 = 0, ++ HAL_BDMA_CH1, ++ HAL_BDMA_CH2, ++ HAL_BDMA_CH3, ++ HAL_BDMA_CH_NUM ++} HalBdmaCh_e; ++ ++typedef enum ++{ ++ HAL_BDMA_MIU0_TO_MIU0 = 0x0, ++ HAL_BDMA_MIU0_TO_MIU1, ++ HAL_BDMA_MIU1_TO_MIU0, ++ HAL_BDMA_MIU1_TO_MIU1, ++ HAL_BDMA_MIU0_TO_IMI, ++ HAL_BDMA_MIU1_TO_IMI, ++ HAL_BDMA_IMI_TO_MIU0, ++ HAL_BDMA_IMI_TO_MIU1, ++ HAL_BDMA_IMI_TO_IMI, ++ HAL_BDMA_MEM_TO_MIU0, ++ HAL_BDMA_MEM_TO_MIU1, ++ HAL_BDMA_MEM_TO_IMI, ++ HAL_BDMA_SPI_TO_MIU0, ++ HAL_BDMA_SPI_TO_MIU1, ++ HAL_BDMA_SPI_TO_IMI ++} HalBdmaPathSel_e; ++ ++typedef enum ++{ ++ HAL_BDMA_DATA_BYTE_1 = 0x0, ++ HAL_BDMA_DATA_BYTE_2 = 0x1, ++ HAL_BDMA_DATA_BYTE_4 = 0x2, ++ HAL_BDMA_DATA_BYTE_8 = 0x3, ++ HAL_BDMA_DATA_BYTE_16 = 0x4 ++} HalBdmaDataWidth_e; ++ ++typedef enum ++{ ++ HAL_BDMA_ADDR_INC = 0x0, ++ HAL_BDMA_ADDR_DEC = 0x1 ++} HalBdmaAddrMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void (* HalBdmaTxCb)(u32); ++ ++typedef struct { ++ u32 u32SrcWidth; ///< Width of source ++ u32 u32SrcOffset; ///< Line-to-line offset of source ++ u32 u32DstWidth; ///< Width of destination ++ u32 u32DstOffset; ///< Line-to-line offset of destination ++} HalBdmaLineOfst_t; ++ ++typedef struct { ++ bool bIntMode; ++ HalBdmaPathSel_e ePathSel; ++ HalBdmaDataWidth_e eSrcDataWidth; ++ HalBdmaDataWidth_e eDstDataWidth; ++ HalBdmaAddrMode_e eDstAddrMode; ++ u32 u32TxCount; ++ u32 u32Pattern; ++ void *pSrcAddr; ++ void *pDstAddr; ++ u32 bEnLineOfst; ++ HalBdmaLineOfst_t *pstLineOfst; ++ HalBdmaTxCb pfTxCbFunc; ++} HalBdmaParam_t; ++ ++ ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalBdmaErr_e HalBdma_Initialize(u8 u8DmaCh); ++HalBdmaErr_e HalBdma_Transfer(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_Transfer_LineOffset(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++HalBdmaErr_e HalBdma_WaitTransferDone(u8 u8DmaCh, HalBdmaParam_t *ptBdmaParam); ++ ++#endif // __HAL_BDMA_H__ +diff --git a/drivers/sstar/bdma/infinity6e/kernel_bdma.h b/drivers/sstar/bdma/infinity6e/kernel_bdma.h +new file mode 100644 +index 000000000000..f2eef5d810e8 +--- /dev/null ++++ b/drivers/sstar/bdma/infinity6e/kernel_bdma.h +@@ -0,0 +1,163 @@ ++/* ++* kernel_bdma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_bdma.h ++ *-------------------------------------------------------------------------- ++ * Scope: BDMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_BDMA_H__ ++#define __KERNEL_BDMA_H__ ++ ++#include "cam_os_wrapper.h" ++ ++/****************************************************************************/ ++/* BDMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeBdma_s ++{ ++ // 0x0 ++ u32 reg_ch0_trig :1; ++ u32 :3; ++ u32 reg_ch0_stop :1; ++ u32 :3; ++ u32 reg_src_tlb :1; ++ u32 reg_dst_tlb :1; ++ u32 :22; ++ // 0x1 ++ u32 reg_ch0_queued :1; ++ u32 reg_ch0_busy :1; ++ u32 reg_ch0_int_bdma :1; ++ u32 reg_ch0_done :1; ++ u32 reg_ch0_result0 :1; ++ u32 reg_xiu_bdma_ns :1; ++ u32 :26; ++ // 0x2 ++ u32 reg_ch0_src_sel :4; ++ #define REG_BDMA_SRC_MIU_IMI_CH0 0 //16 bytes ++ #define REG_BDMA_SRC_MIU_IMI_CH1 1 //16 bytes ++ #define REG_BDMA_SRC_MEM_FILL 4 //4 bytes ++ #define REG_BDMA_SRC_SPI 5 //8 bytes ++ #define REG_BDMA_SRC_TSP_SRAM 10 //1 byte ++ u32 reg_ch0_src_dw :3; ++ #define REG_BDMA_DATA_DEPTH_1BYTE 0 ++ #define REG_BDMA_DATA_DEPTH_2BYTE 1 ++ #define REG_BDMA_DATA_DEPTH_4BYTE 2 ++ #define REG_BDMA_DATA_DEPTH_8BYTE 3 ++ #define REG_BDMA_DATA_DEPTH_16BYTE 4 ++ u32 :1; ++ u32 reg_ch0_dst_sel :4; ++ #define REG_BDMA_DST_MIU_IMI_CH0 0 ++ #define REG_BDMA_DST_MIU_IMI_CH1 1 ++ #define REG_BDMA_DST_PM51 6 ++ #define REG_BDMA_DST_SEC51 9 ++ #define REG_BDMA_DST_TSP_SRAM 10 ++ #define REG_BDMA_SDT_FSP 11 //4 byte ++ u32 reg_ch0_dst_dw :3; ++ u32 :17; ++ // 0x3 ++ u32 reg_ch0_dec :1; ++ u32 reg_ch0_int_en :1; ++ u32 :2; ++ u32 reg_ch0_cfg :4; ++ u32 reg_ch0_flush_wd :4; ++ u32 reg_ch0_replace_miu :4; ++ #define REG_BDMA_CH0_MIU0 0 ++ #define REG_BDMA_CH0_MIU1 1 ++ #define REG_BDMA_CH0_IMI 2 ++ #define REG_BDMA_CH1_MIU0 0 ++ #define REG_BDMA_CH1_MIU1 4 ++ #define REG_BDMA_CH1_IMI 8 ++ u32 :16; ++ // 0x4 ++ u32 reg_ch0_src_a0 :16; ++ u32 :16; ++ // 0x5 ++ u32 reg_ch0_src_a1 :16; ++ u32 :16; ++ // 0x6 ++ u32 reg_ch0_dst_a0 :16; ++ u32 :16; ++ // 0x7 ++ u32 reg_ch0_dst_a1 :16; ++ u32 :16; ++ // 0x8 ++ u32 reg_ch0_size0 :16; ++ u32 :16; ++ // 0x9 ++ u32 reg_ch0_size1 :16; ++ u32 :16; ++ // 0xA ++ u32 reg_ch0_cmd0_low :16; ++ u32 :16; ++ // 0xB ++ u32 reg_ch0_cmd0_high :16; ++ u32 :16; ++ // 0xC ++ u32 reg_ch0_cmd1_low :16; ++ u32 :16; ++ // 0xD ++ u32 reg_ch0_cmd1_high :16; ++ u32 :16; ++ // 0xE ++ u32 reg_ch0_cmd2_low :16; ++ u32 :16; ++ // 0xF ++ u32 reg_ch0_cmd2_high :16; ++ u32 :16; ++ // 0x10 ++ u32 reg_ch0_offset_en :1; ++ u32 :31; ++ // 0x11 ++ u32 :32; ++ // 0x12 ++ u32 reg_ch0_src_width_low :16; ++ u32 :16; ++ // 0x13 ++ u32 reg_ch0_src_width_high :16; ++ u32 :16; ++ // 0x14 ++ u32 reg_ch0_src_offset_low :16; ++ u32 :16; ++ // 0x15 ++ u32 reg_ch0_src_offset_high :16; ++ u32 :16; ++ // 0x16 ++ u32 reg_ch0_dst_width_low :16; ++ u32 :16; ++ // 0x17 ++ u32 reg_ch0_dst_width_high :16; ++ u32 :16; ++ // 0x18 ++ u32 reg_ch0_dst_offset_low :16; ++ u32 :16; ++ // 0x19 ++ u32 reg_ch0_dst_offset_high :16; ++ u32 :16; ++ ++ ++} KeBdma_t; ++ ++extern volatile KeBdma_t* const g_ptKeBdma0; ++extern volatile KeBdma_t* const g_ptKeBdma1; ++extern volatile KeBdma_t* const g_ptKeBdma2; ++extern volatile KeBdma_t* const g_ptKeBdma3; ++ ++#endif // __KERNEL_BDMA_H__ +diff --git a/drivers/sstar/cam_clkgen/Makefile b/drivers/sstar/cam_clkgen/Makefile +new file mode 100755 +index 000000000000..6324b1505e78 +--- /dev/null ++++ b/drivers/sstar/cam_clkgen/Makefile +@@ -0,0 +1,3 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++obj-y += cam_clkgen.o +\ No newline at end of file +diff --git a/drivers/sstar/cam_clkgen/cam_clkgen.c b/drivers/sstar/cam_clkgen/cam_clkgen.c +new file mode 100755 +index 000000000000..07e6fcc931fe +--- /dev/null ++++ b/drivers/sstar/cam_clkgen/cam_clkgen.c +@@ -0,0 +1,226 @@ ++/* ++* mdrv_sar.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++unsigned long CamClkGetRate(struct clk *clk) ++{ ++ return clk_get_rate(clk); ++} ++ ++unsigned long CamClkHwGetNumParents(const struct clk_hw *hw) ++{ ++ return clk_hw_get_num_parents(hw); ++} ++ ++struct clk_hw *CamClkGetParentByIndex(const struct clk_hw *hw, unsigned int index) ++{ ++ return clk_hw_get_parent_by_index(hw, index); ++} ++ ++int CamClkPrepare(struct clk *clk) ++{ ++ return clk_prepare(clk); ++} ++ ++int CamClkEnable(struct clk *clk) ++{ ++ return clk_enable(clk); ++} ++ ++void CamClkUnprepare(struct clk *clk) ++{ ++ clk_unprepare(clk); ++} ++ ++void CamClkDisable(struct clk *clk) ++{ ++ clk_disable(clk); ++} ++ ++/* clk_disable_unprepare helps cases using clk_disable in non-atomic context. */ ++static inline void CamClkDisableUnprepare(struct clk *clk) ++{ ++ CamClkDisable(clk); ++ CamClkUnprepare(clk); ++} ++ ++int CamClkSetRate(struct clk *clk, unsigned long rate) ++{ ++ return clk_set_rate(clk, rate); ++} ++ ++int CamClkSetParent(struct clk *clk, struct clk *parent) ++{ ++ return clk_set_parent(clk, parent); ++} ++ ++long CamClkRoundRate(struct clk *clk, unsigned long rate) ++{ ++ return clk_round_rate(clk, rate); ++} ++ ++struct clk_hw *__CamClkGetHw(struct clk *clk) ++{ ++ return __clk_get_hw(clk); ++} ++ ++/** ++ * of_clk_get_parent_count() - Count the number of clocks a device node has ++ * @np: device node to count ++ * ++ * Returns: The number of clocks that are possible parents of this node ++ */ ++unsigned int CamOfClkGetParentCount(struct device_node *np) ++{ ++ int count; ++ ++ count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); ++ if (count < 0) ++ return 0; ++ ++ return count; ++} ++ ++const char *CamOfClkGetParentName(struct device_node *np, int index) ++{ ++ return of_clk_get_parent_name(np, index); ++} ++ ++ ++/** ++ * of_address_to_resource - Translate device tree address and return as resource ++ * ++ * Note that if your address is a PIO address, the conversion will fail if ++ * the physical address can't be internally converted to an IO token with ++ * pci_address_to_pio(), that is because it's either called to early or it ++ * can't be matched to any host bridge IO space ++ */ ++int msys_of_address_to_resource(struct device_node *dev, int index, ++ struct resource *r) ++{ ++ return of_address_to_resource(dev, index, r); ++} ++ ++int msys_of_irq_to_resource(struct device_node *dev, int index, ++ struct resource *r) ++{ ++ return of_irq_to_resource(dev, index, r); ++} ++ ++int msys_of_property_read_u32_index(const struct device_node *np, ++ const char *propname, ++ u32 index, u32 *out_value) ++{ ++ return of_property_read_u32_index(np, propname, index, out_value); ++} ++ ++int msys_of_property_read_variable_u32_array(const struct device_node *np, ++ const char *propname, u32 *out_values, ++ size_t sz_min, size_t sz_max) ++{ ++ return of_property_read_variable_u32_array(np, propname, out_values, sz_min, sz_max); ++} ++/** ++ * platform_get_resource - get a resource for a device ++ * @dev: platform device ++ * @type: resource type ++ * @num: resource index ++ */ ++struct resource *msys_platform_get_resource(struct platform_device *dev, ++ unsigned int type, unsigned int num) ++{ ++ return platform_get_resource(dev, type, num); ++} ++ ++/** ++ * platform_driver_unregister - unregister a driver for platform-level devices ++ * @drv: platform driver structure ++ */ ++void msys_platform_driver_unregister(struct platform_driver *drv) ++{ ++ platform_driver_unregister(drv); ++} ++ ++ ++/** ++ * platform_get_irq_byname - get an IRQ for a device by name ++ * @dev: platform device ++ * @name: IRQ name ++ */ ++int msys_platform_get_irq_byname(struct platform_device *dev, const char *name) ++{ ++ return platform_get_irq_byname(dev, name); ++} ++ ++int __must_check msys_sysfs_create_file(struct kobject *kobj, const struct attribute * attr) ++{ ++ return sysfs_create_file_ns(kobj, attr, NULL); ++} ++ ++int msys_sysfs_create_files(struct kobject *kobj, const struct attribute **ptr) ++{ ++ return sysfs_create_files(kobj, ptr); ++} ++ ++int msys_sysfs_create_link(struct kobject *kobj, struct kobject *target, const char *name) ++{ ++ return sysfs_create_link(kobj, target, name); ++} ++ ++void msys_sysfs_remove_file(struct kobject *kobj, const struct attribute *attr, const void *ns) ++{ ++ sysfs_remove_file_ns(kobj, attr, NULL); ++} ++ ++void msys_sysfs_remove_files(struct kobject *kobj, const struct attribute **attr) ++{ ++ sysfs_remove_files(kobj, attr); ++} ++ ++EXPORT_SYMBOL(msys_sysfs_remove_files); ++EXPORT_SYMBOL(msys_sysfs_remove_file); ++EXPORT_SYMBOL(msys_sysfs_create_link); ++EXPORT_SYMBOL(msys_sysfs_create_files); ++EXPORT_SYMBOL(msys_sysfs_create_file); ++EXPORT_SYMBOL(msys_platform_get_irq_byname); ++EXPORT_SYMBOL(msys_platform_driver_unregister); ++EXPORT_SYMBOL(msys_platform_get_resource); ++EXPORT_SYMBOL(msys_of_property_read_variable_u32_array); ++EXPORT_SYMBOL(msys_of_property_read_u32_index); ++EXPORT_SYMBOL(msys_of_irq_to_resource); ++EXPORT_SYMBOL(msys_of_address_to_resource); ++EXPORT_SYMBOL(CamOfClkGetParentName); ++EXPORT_SYMBOL(CamOfClkGetParentCount); ++EXPORT_SYMBOL(__CamClkGetHw); ++EXPORT_SYMBOL(CamClkRoundRate); ++EXPORT_SYMBOL(CamClkSetParent); ++EXPORT_SYMBOL(CamClkSetRate); ++EXPORT_SYMBOL(CamClkPrepare); ++EXPORT_SYMBOL(CamClkDisable); ++EXPORT_SYMBOL(CamClkEnable); ++EXPORT_SYMBOL(CamClkUnprepare); ++EXPORT_SYMBOL(CamClkGetParentByIndex); ++EXPORT_SYMBOL(CamClkHwGetNumParents); ++EXPORT_SYMBOL(CamClkGetRate); ++ +diff --git a/drivers/sstar/cam_dev_wrapper/Makefile b/drivers/sstar/cam_dev_wrapper/Makefile +new file mode 100755 +index 000000000000..3c8ce9189916 +--- /dev/null ++++ b/drivers/sstar/cam_dev_wrapper/Makefile +@@ -0,0 +1,97 @@ ++CROSS_COMPILE ?=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++STRIP = $(CROSS_COMPILE)strip ++BUILD_DIR := .build ++LIB_NAME=cam_dev_wrapper ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++#LINUX_KERNEL_PATH ?= ../../../linux-3.18 ++LINUX_KERNEL_PATH ?= ../../kernel/API ++KL_API_INCLUDE ?= $(LINUX_KERNEL_PATH)/drivers/sstar/include ++ ++CFLAGS := -Wall -Werror -g -O2 -ffunction-sections -funwind-tables -fstack-protector ++CFLAGS += -fPIC -DPIC -DCONFIG_DEBUG_LEVEL=32 ++ ++CFLAGS += -DTEST_THREAD_ID_DETECTION ++CFLAGS += -DCAM_OS_LINUX_USER ++#CFLAGS += -D__USE_GNU ++LDFLAGS += -O2 -Bdirect -Wl,--hash-style=gnu ++LIBS := -ldl -lpthread ++ ++ ++CAM_DEV_WRAPPER_LIB_C_SRCS := \ ++ ./src/cam_dev_wrapper.c \ ++ ++CINCLUDES := \ ++ -I$(KL_API_INCLUDE) \ ++ -I./pub \ ++ -I./inc \ ++ -I../cam_os_wrapper/pub \ ++ ++LIB_HEADERS := \ ++ ./pub/cam_dev_wrapper.h \ ++ ./pub/cam_dev_scl.h \ ++ ++CAM_DEV_WRAPPER_LIB_C_OBJS := $(patsubst %.c, %.c.so.o, $(CAM_DEV_WRAPPER_LIB_C_SRCS)) ++ ++ ++.PHONY: clean prepare lib$(LIB_NAME) ++ ++all: prepare lib$(LIB_NAME) ++ ++prepare: ++ @echo ++ @echo ">>>>========================================================" ++ @echo ++ @echo " LIB_NAME = ${LIB_NAME}" ++ @echo " PWD = $(shell pwd)" ++ @echo " CC = $(CC)" ++ @echo " BRANCH_ID = $(BRANCH_ID)" ++ @echo ++ @mkdir -p $(BUILD_DIR) ++ @echo " Copying headers to '$(BUILD_DIR)/include'..." ++ @echo ++ @mkdir -p $(BUILD_DIR)/include ++ @cp -f $(LIB_HEADERS) $(BUILD_DIR)/include ++ ++install: ++ @echo " INSTALL $(LIB_NAME) to $(INSTALLDIR)" ++ @rm -Rf $(INSTALLDIR) ++ @mkdir -p $(INSTALLDIR) ++ @cp -Rf $(BUILD_DIR)/lib $(INSTALLDIR) ++ @cp -Rf $(BUILD_DIR)/include $(INSTALLDIR) ++ ++clean: ++ @rm -Rf $(CAM_DEV_WRAPPER_LIB_C_OBJS) ++ @rm -Rf $(BUILD_DIR) ++ ++ ++ ++lib$(LIB_NAME): prepare $(CAM_DEV_WRAPPER_LIB_C_OBJS) ++ @mkdir -p $(BUILD_DIR)/lib ++ @echo " LD $(BUILD_DIR)/lib/$@.so" ++ @$(CC) -shared $(LDFLAGS) -o $(BUILD_DIR)/lib/$@.so $(CAM_DEV_WRAPPER_LIB_C_OBJS) ${LIBS} ++ @echo ++ @echo "<<<<========================================================" ++ @echo ++ ++ ++ ++ ++%.c.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ ++ ++%.c.test.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++ @$(CC) $(CFLAGS) $(TEST_CINCLUDES) -c $< -o $@ ++ ++%.c.so.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ +diff --git a/drivers/sstar/cam_dev_wrapper/cam_dev_wrapper.mak b/drivers/sstar/cam_dev_wrapper/cam_dev_wrapper.mak +new file mode 100755 +index 000000000000..bb39d0922f86 +--- /dev/null ++++ b/drivers/sstar/cam_dev_wrapper/cam_dev_wrapper.mak +@@ -0,0 +1,23 @@ ++ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_cam_dev_wrapper)/src \ ++ $(PATH_cam_dev_wrapper)/test ++ ++PATH_H +=\ ++ $(PATH_cam_os_wrapper)/pub \ ++ $(PATH_cam_dev_wrapper)/pub \ ++ $(PATH_cam_dev_wrapper)/inc \ ++ $(PATH_cam_drv_poll)/pub \ ++ $(PATH_cam_drv_poll)/sample_driver/pub \ ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ cam_dev_wrapper.c \ ++# cam_dev_wrapper_test.c \ +diff --git a/drivers/sstar/cam_dev_wrapper/inc/cam_dev_pollsample.h b/drivers/sstar/cam_dev_wrapper/inc/cam_dev_pollsample.h +new file mode 100755 +index 000000000000..3f18cc0f9de1 +--- /dev/null ++++ b/drivers/sstar/cam_dev_wrapper/inc/cam_dev_pollsample.h +@@ -0,0 +1,27 @@ ++/* ++* cam_dev_pollsample.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __CAM_DEV_POLLSAMPLE_H__ ++#define __CAM_DEV_POLLSAMPLE_H__ ++ ++int CamDevPollsampleOpen(char* name); ++int CamDevPollsampleClose(int nFd); ++int CamDevPollsampleIoctl(int nFd, unsigned long request, void *param); ++int CamDevPollsamplePoll(s32 nFd, s16 nEvent, s16* pnRevent, s32 nTimeout); ++ ++#endif /* __CAM_DEV_POLLSAMPLE_H__ */ +diff --git a/drivers/sstar/cam_dev_wrapper/pub/cam_dev_wrapper.h b/drivers/sstar/cam_dev_wrapper/pub/cam_dev_wrapper.h +new file mode 100755 +index 000000000000..d05e01c1123d +--- /dev/null ++++ b/drivers/sstar/cam_dev_wrapper/pub/cam_dev_wrapper.h +@@ -0,0 +1,83 @@ ++/* ++* cam_dev_wrapper.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __CAM_DEV_WRAPPER_H__ ++#define __CAM_DEV_WRAPPER_H__ ++ ++#define CAM_DEV_WRAPPER_VERSION "v1.0.2" ++ ++ ++#ifdef CAM_OS_RTK /*start RTK part*/ ++#include "cam_drv_poll.h" ++ ++struct pollfd { ++ int fd; ++ short events; ++ short revents; ++}; ++ ++#define _IOC(dir,type,nr,size) \ ++ (((dir) << 0) | \ ++ ((type) << 8) | \ ++ ((nr) << 16) | \ ++ ((size) << 24)) ++ ++#define _IOC_TYPECHECK(t) (sizeof(t)) ++ ++/* used to create numbers */ ++#define _IO(type,nr) _IOC(0,(type),(nr),0) ++#define _IOR(type,nr,size) _IOC(1,(type),(nr),(_IOC_TYPECHECK(size))) ++#define _IOW(type,nr,size) _IOC(2,(type),(nr),(_IOC_TYPECHECK(size))) ++#define _IOWR(type,nr,size) _IOC(3,(type),(nr),(_IOC_TYPECHECK(size))) ++ ++#define FILL_VERCHK_TYPE(var, var_ver, var_size, version) \ ++({ \ ++ var_ver = ((version & 0xffffffff)); \ ++ var_size = sizeof(var); \ ++ var; \ ++}) ++ ++int CamDevOpen(char* name); ++int CamDevClose(int fd); ++int CamDevIoctl(int fd, unsigned long request, void *param); ++int CamDevPoll(struct pollfd *fds, int nfds, int timeout); ++void* CamDevMmap(int length,int fd,int offset); ++int CamDevMunmap(int fd,void* start,int length); ++int CamDevRead(int fd, void *buf, unsigned int count); ++int CamDevWrite(int fd, const void *buf, unsigned int count); ++ ++#else // For linux user space ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define CamDevOpen(a) open(a, O_RDWR) ++#define CamDevClose(a) close(a) ++#define CamDevIoctl(a, b, c) ioctl(a, b, c) ++#define CamDevPoll(a, b, c) poll(a, b, c) ++#define CamDevMmap(a, b, c) mmap(0, a, PROT_READ | PROT_WRITE, MAP_SHARED, b, c) ++#define CamDevMunmap(a, b, c) munmap(b, c) ++#define CamDevRead(a, b, c) read(a, b, c) ++#define CamDevWrite(a, b, c) write(a, b, c) ++ ++#endif ++ ++#endif // __CAM_DEV_WRAPPER_H__ +diff --git a/drivers/sstar/cam_dev_wrapper/src/cam_dev_pollsample.c b/drivers/sstar/cam_dev_wrapper/src/cam_dev_pollsample.c +new file mode 100755 +index 000000000000..fad920fd6a70 +--- /dev/null ++++ b/drivers/sstar/cam_dev_wrapper/src/cam_dev_pollsample.c +@@ -0,0 +1,78 @@ ++/* ++* cam_dev_pollsample.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include "cam_os_wrapper.h" ++#include "cam_dev_wrapper.h" ++#include ++#include ++ ++ ++//============================================================================= ++int CamDevPollsampleOpen(char* name) ++{ ++ struct file *filp; ++ ++ if(name){} ++ ++ filp = (struct file *)CamOsMemCalloc(1, sizeof(struct file)); ++ if (pollsamp_open(filp) == 0) /* success */ ++ { ++ return (int)filp; ++ } ++ else ++ { ++ CamOsMemRelease(filp); ++ return -1; ++ } ++} ++ ++int CamDevPollsampleClose(int nFd) ++{ ++ struct file *filp = (struct file *)nFd; ++ ++ pollsamp_release(filp); ++ CamOsMemRelease(filp); ++ ++ return CAM_OS_OK; ++} ++ ++int CamDevPollsampleIoctl(int nFd, unsigned long request, void *param) ++{ ++ int nRet = CAM_OS_OK; ++ struct file *filp = (struct file *)nFd; ++ ++ if (pollsamp_ioctl(filp, request, (unsigned long)param) != 0) ++ { ++ nRet = CAM_OS_FAIL; ++ } ++ ++ return nRet; ++} ++ ++int CamDevPollsamplePoll(s32 nFd, s16 nEvent, s16* pnRevent, s32 nTimeout) ++{ ++ struct file *filp = (struct file *)nFd; ++ u32 nEventKept, nRevent; ++ ++ filp->nPollTimeout = nTimeout; ++ nRevent = pollsamp_poll(filp, NULL); ++ ++ *pnRevent = nRevent & nEvent; ++ CamOsPrintf("%s: revent=0x%x\n",__func__, *pnRevent); ++ return (*pnRevent != 0) ? 1 : 0; ++} +diff --git a/drivers/sstar/cam_dev_wrapper/src/cam_dev_wrapper.c b/drivers/sstar/cam_dev_wrapper/src/cam_dev_wrapper.c +new file mode 100755 +index 000000000000..0a28f0f9871e +--- /dev/null ++++ b/drivers/sstar/cam_dev_wrapper/src/cam_dev_wrapper.c +@@ -0,0 +1,1177 @@ ++/* ++* cam_dev_wrapper.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include "cam_os_wrapper.h" ++#include "cam_dev_wrapper.h" ++ ++#ifdef CAM_OS_RTK ++#include ++#include "cam_os_util_list.h" ++#include "sys_sys.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#include "sys_MsWrapper_cus_os_util.h" ++#include "sys_sys_isw_uart.h" ++#include "cam_dev_pollsample.h" ++ ++typedef int (*PfnCamPoll)(int fdt, short nEvents, short *reqEvents ,int ntimeout); ++ ++typedef struct __CamDevFuncMap_t ++{ ++ char * szName; ++ int (*pOpen)(char* szName); ++ int (*pClose)(int fdt); ++ int (*pIoctl)(int fdt, unsigned long request, void *param); ++ void* (*pMmap)(void* start,int length,int fdt,int offset); ++ int (*pMunmap)(void* start,int length); ++ int (*pPoll)( int fdt, short nEvents, short *reqEvents ,int ntimeout); ++ int (*pRead)(int fdt, void *buf, unsigned int count); ++ int (*pWrite)(int fdt, const void *buf, unsigned int count); ++} CamDevFuncMap_t; ++ ++typedef struct __CamDevFD_t ++{ ++ struct CamOsListHead_t list; ++ int nDevFD; ++ int nDrvFD; ++ int nValid; ++ CamDevFuncMap_t * pDevMapFunc; ++} CamDevFD_t; ++ ++static unsigned int _gCamDevFD = 1; ++static unsigned int _gInitFDone = 0; ++static unsigned int _gInitMutexDone = 0; ++static unsigned int _gFileCnt = 0; ++static CamDevFD_t _gCamDevFDList; ++static CamOsMutex_t _gFDLock; ++ ++static void _CamDevPollNodeFree(int fd); ++int AlkaidPollAdpOpen(char* szName); ++int AlkaidPollAdpRelease(int fdt); ++int AlkaidPollAdpIoctl(int fdt, unsigned long request, void *param); ++int AlkaidPollAdpPoll( int fdt, short nEvents, short *reqEvents ,int ntimeout); ++ ++static CamDevFuncMap_t _gDevMapTable[] = ++{ ++ {"alkaidpoll", AlkaidPollAdpOpen, AlkaidPollAdpRelease, AlkaidPollAdpIoctl, NULL, NULL, AlkaidPollAdpPoll, NULL, NULL} ++}; ++ ++#define DEVMAPTABLE_SZ (sizeof(_gDevMapTable)/sizeof(CamDevFuncMap_t)) ++ ++static CamDevFuncMap_t* _CamDevFindDevMapTable(char* name) ++{ ++ int i; ++ ++ for(i=0; inValid) ++ { ++ tmp->nDrvFD = ndrvfd; ++ tmp->pDevMapFunc = pfuncmap; ++ tmp->nValid = 1; ++ CamOsMutexUnlock(&_gFDLock); ++ return tmp; ++ } ++ } ++ ++ tmp = CamOsMemAlloc(sizeof(CamDevFD_t)); ++ ++ if(tmp == NULL) ++ { ++ CamOsPrintf("%s : can't allocate memory\n\r", __FUNCTION__); ++ CamOsMutexUnlock(&_gFDLock); ++ return NULL; ++ ++ } ++ ++ tmp->nDevFD = _gCamDevFD++; ++ tmp->nDrvFD = ndrvfd; ++ tmp->nValid = 1; ++ tmp->pDevMapFunc = pfuncmap; ++ ++ CAM_OS_INIT_LIST_HEAD(&tmp->list); ++ CAM_OS_LIST_ADD_TAIL(&tmp->list,&_gCamDevFDList.list); ++ CamOsMutexUnlock(&_gFDLock); ++ ++ return tmp; ++} ++ ++static int _CamDevCloseFD(int nFd) ++{ ++ struct CamOsListHead_t *pos, *q; ++ CamDevFD_t *tmp; ++ ++ CamOsMutexLock(&_gFDLock); ++ ++ CAM_OS_LIST_FOR_EACH_SAFE(pos, q, &_gCamDevFDList.list) ++ { ++ tmp = CAM_OS_LIST_ENTRY(pos, CamDevFD_t, list); ++ ++ if(tmp->nValid && tmp->nDevFD == nFd) ++ { ++ tmp->nValid = 0; ++ CamOsMutexUnlock(&_gFDLock); ++ return CAM_OS_OK; ++ } ++ } ++ ++ CamOsMutexUnlock(&_gFDLock); ++ ++ return CAM_OS_FAIL; ++} ++ ++static CamDevFD_t* _CamDevFindFD(int nFd) ++{ ++ struct CamOsListHead_t *pos, *q; ++ CamDevFD_t *tmp; ++ ++ CamOsMutexLock(&_gFDLock); ++ ++ CAM_OS_LIST_FOR_EACH_SAFE(pos, q, &_gCamDevFDList.list) ++ { ++ tmp = CAM_OS_LIST_ENTRY(pos, CamDevFD_t, list); ++ ++ if(tmp->nValid && tmp->nDevFD == nFd) ++ { ++ CamOsMutexUnlock(&_gFDLock); ++ return tmp; ++ } ++ } ++ ++ CamOsMutexUnlock(&_gFDLock); ++ ++ return NULL; ++} ++ ++/** ++ * purpose : open device file. ++ * param : ++ * return : ++ */ ++int CamDevOpen(char* name) ++{ ++ CamDevFuncMap_t *pdevfunc; ++ CamDevFD_t *pfd; ++ int nfd; ++ ++ if(!_gInitMutexDone) ++ { ++ _gInitMutexDone = 1; ++ if(CAM_OS_OK != CamOsMutexInit(&_gFDLock)) ++ { ++ _gInitFDone = 1; ++ CamOsPrintf("%s : Init mutex fail\n\r", __FUNCTION__); ++ return CAM_OS_FAIL; ++ } ++ ++ } ++ ++ CamOsMutexLock(&_gFDLock); ++ if(!_gInitFDone) ++ { ++ _gInitFDone = 1; ++ memset(&_gCamDevFDList, 0, sizeof(CamDevFD_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gCamDevFDList.list); ++ } ++ CamOsMutexUnlock(&_gFDLock); ++ ++ if((pdevfunc = _CamDevFindDevMapTable(name)) == NULL) ++ { ++ CamOsPrintf("%s : can't find %s in dev table\n\r", __FUNCTION__,name); ++ return CAM_OS_FAIL; ++ } ++ ++ if(!pdevfunc->pOpen) ++ { ++ CamOsPrintf("%s : %s no open function\n\r", __FUNCTION__,name); ++ return CAM_OS_FAIL; ++ } ++ ++ nfd = pdevfunc->pOpen(name); ++ ++ if(nfd < 0) ++ { ++ CamOsPrintf("%s : %s open fail 0x%x\n\r", __FUNCTION__,name,nfd); ++ return CAM_OS_FAIL; ++ } ++ ++ if((pfd = _CamDevAllocFD(nfd, pdevfunc)) == NULL) ++ { ++ CamOsPrintf("%s : %s _CamDevAllocFD fail %d\n\r", __FUNCTION__,name,nfd); ++ return CAM_OS_FAIL; ++ } ++ ++ CamOsMutexLock(&_gFDLock); ++ _gFileCnt++; ++ CamOsMutexUnlock(&_gFDLock); ++ ++ return pfd->nDevFD; ++} ++ ++/** ++ * purpose : close device file. ++ * param : ++ * return : ++ */ ++int CamDevClose(int fd) ++{ ++ CamDevFD_t* ptmpfd; ++ struct CamOsListHead_t *pos, *q; ++ ++ if((ptmpfd = _CamDevFindFD(fd)) == NULL) ++ { ++ CamOsPrintf("%s : %s find fd fail %d\n\r", __FUNCTION__,fd); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ if(ptmpfd->pDevMapFunc->pPoll) ++ { ++ _CamDevPollNodeFree(fd); ++ } ++ ++ if(ptmpfd->pDevMapFunc->pClose) ++ { ++ ptmpfd->pDevMapFunc->pClose(ptmpfd->nDrvFD); ++ } ++ ++ if(_CamDevCloseFD(fd)!=CAM_OS_OK) ++ { ++ CamOsPrintf("%s : %s close fail %d\n\r", __FUNCTION__,fd); ++ return CAM_OS_FAIL; ++ } ++ ++ CamOsMutexLock(&_gFDLock); ++ _gFileCnt--; ++ ++ if(_gFileCnt <= 0) ++ { ++ _gFileCnt = 0; ++ ++ CAM_OS_LIST_FOR_EACH_SAFE(pos, q, &_gCamDevFDList.list) ++ { ++ ptmpfd = CAM_OS_LIST_ENTRY(pos, CamDevFD_t, list); ++ ++ if(ptmpfd->nValid) ++ { ++ CamOsPrintf(" %s maybe user not use close function\n\r", ptmpfd->pDevMapFunc->szName); ++ } ++ CAM_OS_LIST_DEL(&ptmpfd->list); ++ CamOsMemRelease((void*)ptmpfd); ++ } ++ _gInitFDone = 0; ++ _gCamDevFD = 1; ++ ++ } ++ CamOsMutexUnlock(&_gFDLock); ++ ++ return CAM_OS_OK; ++} ++ ++/** ++ * purpose : ++ * param : ++ * return : ++ */ ++int CamDevIoctl(int fd, unsigned long request, void *param) ++{ ++ int ret; ++ CamDevFD_t* ptmpfd; ++ ++ if((ptmpfd = _CamDevFindFD(fd)) == NULL) ++ { ++ CamOsPrintf("%s : %s find fd fail %d\n\r", __FUNCTION__,fd); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ if(ptmpfd->pDevMapFunc->pIoctl) ++ { ++ ret = ptmpfd->pDevMapFunc->pIoctl(ptmpfd->nDrvFD,request,param); ++ } ++ else ++ { ++ CamOsPrintf("%s : no support ioctl\n\r", ptmpfd->pDevMapFunc->szName); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ return ret; ++} ++ ++/** ++ * purpose : ++ * param : ++ * return : ++ */ ++void* CamDevMmap(int length,int fd,int offset) ++{ ++ CamDevFD_t* ptmpfd; ++ ++ if((ptmpfd = _CamDevFindFD(fd)) == NULL) ++ { ++ CamOsPrintf("%s : %s find fd fail %d\n\r", __FUNCTION__,fd); ++ return NULL; ++ ++ } ++ ++ if(ptmpfd->pDevMapFunc->pMmap) ++ { ++ return ptmpfd->pDevMapFunc->pMmap(0,length,ptmpfd->nDrvFD,offset); ++ } ++ ++ CamOsPrintf("%s : no support MMAP\n\r", ptmpfd->pDevMapFunc->szName); ++ return NULL; ++} ++ ++/** ++ * purpose : ++ * param : ++ * return : ++ */ ++int CamDevMunmap(int fd,void* start,int length) ++{ ++ CamDevFD_t* ptmpfd; ++ ++ if((ptmpfd = _CamDevFindFD(fd)) == NULL) ++ { ++ CamOsPrintf("%s : %s find fd fail %d\n\r", __FUNCTION__,fd); ++ return CAM_OS_FAIL; ++ } ++ ++ if(ptmpfd->pDevMapFunc->pMunmap) ++ { ++ return ptmpfd->pDevMapFunc->pMunmap(start,length); ++ } ++ ++ CamOsPrintf("%s : no support Munmap\n\r", ptmpfd->pDevMapFunc->szName); ++ return CAM_OS_FAIL; ++} ++ ++/** ++ * purpose : ++ * param : ++ * return : ++ */ ++int CamDevRead(int fd, void *buf, unsigned int count) ++{ ++ int ret; ++ CamDevFD_t* ptmpfd; ++ ++ if((ptmpfd = _CamDevFindFD(fd)) == NULL) ++ { ++ CamOsPrintf("%s : %s find fd fail %d\n\r", __FUNCTION__,fd); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ if(ptmpfd->pDevMapFunc->pRead) ++ { ++ ret = ptmpfd->pDevMapFunc->pRead(ptmpfd->nDrvFD, buf, count); ++ } ++ else ++ { ++ CamOsPrintf("%s : no support read\n\r", ptmpfd->pDevMapFunc->szName); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ return ret; ++} ++ ++/** ++ * purpose : ++ * param : ++ * return : ++ */ ++int CamDevWrite(int fd, const void *buf, unsigned int count) ++{ ++ int ret; ++ CamDevFD_t* ptmpfd; ++ ++ if((ptmpfd = _CamDevFindFD(fd)) == NULL) ++ { ++ CamOsPrintf("%s : %s find fd fail %d\n\r", __FUNCTION__,fd); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ if(ptmpfd->pDevMapFunc->pWrite) ++ { ++ ret = ptmpfd->pDevMapFunc->pWrite(ptmpfd->nDrvFD, buf, count); ++ } ++ else ++ { ++ CamOsPrintf("%s : no support write\n\r", ptmpfd->pDevMapFunc->szName); ++ return CAM_OS_FAIL; ++ ++ } ++ ++ return ret; ++} ++ ++/*============================================================================= ++ * ++ * CamDevPoll Implementation ++ * ++ *===========================================================================*/ ++#define POLL_DBG_LV_0 0 ++#define POLL_DBG_LV_1 0 ++#define POLL_DBG_LV_2 0 ++#define POLL_DBG_LV_3 0 ++#define POLL_DBG_TIMEOUT 0 ++ ++#define CAM_POLL_DBG(dbglv, _fmt, _args...) \ ++ if(dbglv) { \ ++ CamOsPrintf(_fmt, ## _args); \ ++ } ++ ++#define CAM_POLL_ERR(_fmt, _args...) CamOsPrintf(_fmt, ## _args); ++ ++#define CAM_DEV_POLL_PANIC() { CamOsPrintf("CAM_DEV_POLL_PANIC\n\r"); \ ++ while (1) { CamOsMsSleep(5000); } \ ++ } ++ ++#define _WITH_SYSTEM_THREAD 1 /* If enabled, RTK init.c should init 5 system threads for CamDevPollThread */ ++ ++//============================================================================= ++ ++#define MAX_POLL_FD_A_BATCH 3 /* max number of fds in a poll */ ++#define CAM_DEV_POLL_STACKSIZE 8192 /* stack size of poll threads */ ++ ++#if _WITH_SYSTEM_THREAD ++#define NUM_SYSTEM_POOLTHD 5 ++#else ++#define NUM_SYSTEM_POOLTHD 0 ++#endif ++ ++/* We crate dymaic poll threads if no poll threads is available for a coming poll */ ++#define NUM_DYNAMIC_POOLTHD_A_BATCH 5 /* number if poll threads created in a batch */ ++#define MAX_POOL_ENTRY_NUM 20 /* The total number of poll threads allowed */ ++ ++#define MAX_POLL_ENTRY_NUM 20 /* The total number of poll table entries */ ++ ++/* ++ * Poll thread pool table entry. ++ * The pool table implements the thread pool concept and is used to manage the ++ * poll threads. Each fd-poll is executed by a poll thread, and that thread is ++ * reused for that specific fd-poll until fd is closed. ++ */ ++typedef struct ++{ ++ int nUsed; /* the thread is used by a fd-poll or not */ ++ int nSuspend; /* the thread is suspend or running-->invoking a driver poll or not */ ++ ++ int nPollThdId; /* ID of this poll thread */ ++ CamOsTsem_t tActiveTsem; /* the suspend/resume flag for the poll thread */ ++ void *pUserData; /* the data passed from poll requests. It is the poll table entrynow. */ ++} CamDevPollThreadPool_t; ++ ++static CamDevPollThreadPool_t _gThdPoolTable[MAX_POOL_ENTRY_NUM]; // = {-1}; /* pollThd Pool table */ ++static CamOsMutex_t _gThdPoolMutex; // = { 0 }; /* protect poll table from being simultaneously accessed */ ++static int _gInitPoolMutexDone = 0; ++static int _gInitThdPoolDone = 0; ++static int _gNumPoolEntry = NUM_SYSTEM_POOLTHD; /*number of the current poll threads */ ++ ++ ++/* ++ * Poll table entry. ++ * Each fd in a poll corresponds to a poll table entry which is reused for that specific fd-poll. ++ * The poll table entry is released on fd close. ++ */ ++typedef struct ++{ ++ int nValid; /* Is this entry used by a fd-poll ? */ ++ ++ int nTid; /* ID of the thread issuing this poll */ ++ int nDevFD; /* device fd */ ++ int nDrvFD; /* driver fd */ ++ Ms_Flag_t *pFlag; /* flag used to wait on drv poll events or timeout */ ++ Ms_flag_value_t tFlagBit; ++ short nEvents; /* requested events */ ++ short nRevents; /* returned events */ ++ int nTimeout; /* timeout setting of this poll */ ++ ++ int nPoolIndex; /* the index of the pool table entry which provides poll thread for this fd-poll */ ++ PfnCamPoll pfnDrvPoll; /* the actual poll function corresponding to this fd */ ++} CamDevPollNode_t; ++ ++static CamDevPollNode_t _gPollTable[MAX_POLL_ENTRY_NUM]; /* Poll table */ ++static CamOsMutex_t _gPollMutex; /* protect poll table from being simultaneously accessed */ ++static s32 _gInitPollDone = 0; ++ ++ ++/*============================================================================= ++ * ++ * pollThread Pool Management ++ * ++ *===========================================================================*/ ++ ++void CamDevPollThread(void); ++static CamOsRet_e _CamDevPollThreadPoolInit() ++{ ++ int i; ++ CamDevPollThreadPool_t *pPoolNode; ++ ++ if(!_gInitPoolMutexDone) ++ { ++ if(CAM_OS_OK != CamOsMutexInit(&_gThdPoolMutex)) ++ { ++ CAM_POLL_ERR("%s : Init mutex fail\n\r", __FUNCTION__); ++ return CAM_OS_FAIL; ++ } ++ _gInitPoolMutexDone = 1; ++ } ++ ++ CamOsMutexLock(&_gThdPoolMutex); ++ if (!_gInitThdPoolDone) ++ { ++ for (i = 0; i < MAX_POOL_ENTRY_NUM; i++) ++ { ++ pPoolNode = &_gThdPoolTable[i]; ++ ++ CamOsTsemInit(&pPoolNode->tActiveTsem, 0); ++ pPoolNode->nPollThdId = -1; ++ pPoolNode->pUserData = NULL; ++ pPoolNode->nUsed = 0; ++ pPoolNode->nSuspend = 0; ++ } ++ _gInitThdPoolDone = 1; ++ } ++ CAM_POLL_DBG(POLL_DBG_LV_0, "%s: done \n\r", __FUNCTION__); ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ return CAM_OS_OK; ++} ++ ++static CamOsRet_e _DynPollThreadPoolCreate() ++{ ++ int i; ++ CamOsThreadAttrb_t attr; ++ CamOsRet_e eRet = CAM_OS_OK; ++ CamOsThread thread; ++ int nToCreate = NUM_DYNAMIC_POOLTHD_A_BATCH; ++ ++ if ( _gNumPoolEntry >= MAX_POOL_ENTRY_NUM ) ++ { ++ return CAM_OS_FAIL; ++ } ++ else if ( (_gNumPoolEntry + nToCreate) > MAX_POOL_ENTRY_NUM ) ++ { ++ nToCreate = MAX_POOL_ENTRY_NUM - _gNumPoolEntry; ++ } ++ ++ attr.nPriority = 100; ++ attr.nStackSize = CAM_DEV_POLL_STACKSIZE; ++ ++ for (i = 0; i < nToCreate; i++) ++ { ++ eRet = CamOsThreadCreate(&thread, &attr, (void *)CamDevPollThread, NULL); ++ if (CAM_OS_OK != eRet) ++ { ++ CAM_POLL_ERR("%s : Create poll thread fail\n\r", __FUNCTION__); ++ break; ++ } ++ CamOsThreadSetName(thread, "CamDevWrp"); ++ } ++ ++ CamOsMutexLock(&_gThdPoolMutex); ++ _gNumPoolEntry += i; ++ ++ CAM_POLL_DBG(POLL_DBG_LV_0,"%s : add %d, total=%d \n\r", __FUNCTION__, i, _gNumPoolEntry); ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ return (i > 0) ? CAM_OS_OK : CAM_OS_FAIL; ++} ++ ++static int _PollThreadPoolAdd(u32 nTid) ++{ ++ int i; ++ CamDevPollThreadPool_t *pPool; ++ ++ while (1) ++ { ++ CamOsMutexLock(&_gThdPoolMutex); ++ for (i = 0; i < _gNumPoolEntry; i++) ++ { ++ pPool = &_gThdPoolTable[i]; ++ if(-1 == pPool->nPollThdId) ++ { ++ pPool->nPollThdId = nTid; ++ break; ++ } ++ } ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ if (i < _gNumPoolEntry) /* found */ ++ { ++ //CamOsPrintf("%s[%d] : add to %d-entry\n\r", __FUNCTION__, nTid, i); ++ return i; ++ } ++ else ++ { ++ CAM_POLL_ERR("%s[%d] : pool full \n\r", __FUNCTION__, nTid); ++ return -1; ++ } ++ } ++} ++ ++// return: -1 if out of resource; otherwise: index of the entry ++static int _CamDevPollThreadPoolAlloc(CamDevPollNode_t* pNode) ++{ ++ int i; ++ int nStart = 0; ++ CamDevPollThreadPool_t *pPool = NULL; ++ ++ while (1) ++ { ++ CamOsMutexLock(&_gThdPoolMutex); ++ for (i = nStart; i < _gNumPoolEntry; i++) ++ { ++ pPool = &_gThdPoolTable[i]; ++ ++ if ((-1 != pPool->nPollThdId) && !pPool->nUsed) ++ { ++ /* associate with a poolThd and not alloc to any poll */ ++ pPool->nUsed = 1; ++ pPool->pUserData = (void*)pNode; ++ break; ++ } ++ } ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ if (pPool && (i < _gNumPoolEntry)) /* found */ ++ { ++ CamOsMutexLock(&_gPollMutex); ++ pNode->nPoolIndex = i; ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[pool:%d] : alloc tid=%d \n\r", __FUNCTION__, i, pPool->nPollThdId); ++ CamOsMutexUnlock(&_gPollMutex); ++ ++ CamOsTsemUp(&pPool->tActiveTsem); ++ return i; ++ } ++ else ++ { ++ if (CAM_OS_OK != _DynPollThreadPoolCreate()) ++ { ++ return -1; ++ } ++ CamOsMsSleep(100); /* Fix me: wait until the thread initialized */ ++ nStart = i; ++ } ++ } ++ ++ return -1; ++} ++ ++static CamOsRet_e _CamDevPollThreadPoolWakeup(int nPoolIndex, int nTimeout) ++{ ++ //TODO... check sync issue ++ if (!_gThdPoolTable[nPoolIndex].nSuspend) ++ { ++ CAM_POLL_DBG(POLL_DBG_LV_1,"%s[pool:%d] : already running(timeout=%d)\n\r", __FUNCTION__, nPoolIndex, nTimeout); ++ return CAM_OS_OK; ++ } ++ ++ CamOsTsemUp(&_gThdPoolTable[nPoolIndex].tActiveTsem); ++ ++ return CAM_OS_OK; ++} ++ ++static int _CamDevPollThreadPoolFree(int nPoolIndex) ++{ ++ CamDevPollThreadPool_t *pPool; ++ ++ CamOsMutexLock(&_gThdPoolMutex); ++ pPool = &_gThdPoolTable[nPoolIndex]; ++ if( (nPoolIndex < _gNumPoolEntry) && pPool->nUsed ) ++ { ++ pPool->nUsed = 0; ++ pPool->pUserData = NULL; ++ } ++ CAM_POLL_DBG(POLL_DBG_LV_1,"%s[pool:%d] used=%d, tid=%d\n\r", __FUNCTION__, nPoolIndex, pPool->nUsed, pPool->nPollThdId); ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ return CAM_OS_OK; ++} ++ ++/*============================================================================= ++ * ++ * poll Table Management ++ * ++ *===========================================================================*/ ++static CamOsRet_e _CamDevPollInit() ++{ ++ if(!_gInitPollDone) ++ { ++ _gInitPollDone = 1; ++ ++ ++ if (CAM_OS_OK != CamOsMutexInit(&_gPollMutex)) ++ { ++ CAM_POLL_ERR("%s : Init _gPollMutex fail\n\r", __FUNCTION__); ++ _gInitPollDone = 0; ++ return CAM_OS_FAIL; ++ } ++ ++#if (!_WITH_SYSTEM_THREAD) ++ if (CAM_OS_OK != _DynPollThreadPoolCreate()) ++ { ++ return CAM_OS_FAIL; ++ } ++ #endif ++ } ++ ++ return CAM_OS_OK; ++} ++ ++#if 0 ++static CamOsRet_e _CamDevPollDeInit() ++{ ++ CamOsMutexDestroy(&_gPollMutex); ++ CamOsMutexDestroy(&_gThdPoolMutex); ++ ++ _gInitPollDone = 0; ++ ++ _gInitPoolMutexDone = 0; ++ _gInitThdPoolDone = 0; ++ /* destroy task */ ++ ++ return CAM_OS_OK; ++} ++#endif ++ ++static CamDevPollNode_t* _CamDevPollNodeAlloc(u32 nTid, int nFd, short nEvents, int nTimeout, ++ CamDevFD_t *pFdNode, ++ Ms_Flag_t *pFlag, Ms_flag_value_t tFlagBit) ++{ ++ int i; ++ CamDevPollNode_t *pNode = NULL; ++ ++ CamOsMutexLock(&_gPollMutex); ++ ++ for (i = 0; i < MAX_POLL_ENTRY_NUM; i++) ++ { ++ pNode = &(_gPollTable[i]); ++ ++ if(!pNode->nValid) ++ { ++ pNode->nTid = nTid; ++ pNode->nDevFD = nFd; ++ ++ pNode->pfnDrvPoll = pFdNode->pDevMapFunc->pPoll; ++ pNode->nDrvFD = pFdNode->nDrvFD; ++ pNode->nEvents = nEvents; ++ pNode->nRevents = 0; ++ pNode->nTimeout = nTimeout; ++ ++ pNode->pFlag = pFlag; ++ pNode->tFlagBit = tFlagBit; ++ pNode->nValid = 1; ++ break; ++ } ++ } ++ ++ CamOsMutexUnlock(&_gPollMutex); ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[tid=%d,fd=%d,flagBit%x] : done\n\r", __FUNCTION__, nTid, nFd, tFlagBit); ++ return pNode; ++} ++ ++/* free all the node with nDevFD==nFd */ ++static void _CamDevPollNodeFree(int nFd) ++{ ++ int i; ++ CamDevPollNode_t *pNode = NULL; ++ Ms_Flag_t *pFlag = NULL; ++ ++ ++ CamOsMutexLock(&_gPollMutex); ++ ++ for (i = 0; i < MAX_POLL_ENTRY_NUM; i++) ++ { ++ pNode = &(_gPollTable[i]); ++ ++ if(pNode->nValid && pNode->nDevFD == nFd) ++ { ++ pNode->nValid = 0; ++ if (pNode->pFlag) ++ { ++ pFlag = pNode->pFlag; ++ CamOsMemRelease((void*)pNode->pFlag); ++ pNode->pFlag = NULL; ++ } ++ _CamDevPollThreadPoolFree(pNode->nPoolIndex); ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[fd=%d,pool:%d] : \n\r", __FUNCTION__, nFd, pNode->nPoolIndex); ++ break; ++ } ++ } ++ ++ if (pFlag) ++ { ++ for (i = 0; i < MAX_POLL_ENTRY_NUM; i++) ++ { ++ pNode = &(_gPollTable[i]); ++ ++ if(pNode->nValid && pNode->pFlag == pFlag) ++ { ++ pNode->pFlag = NULL; ++ } ++ } ++ } ++ ++ CamOsMutexUnlock(&_gPollMutex); ++} ++ ++/* nFd<0: don't care fd */ ++static CamDevPollNode_t* _CamDevPollNodeFind(u32 nTid, int nFd) ++{ ++ int i; ++ CamDevPollNode_t *pNode; ++ ++ CamOsMutexLock(&_gPollMutex); ++ ++ for (i = 0; i < MAX_POLL_ENTRY_NUM; i++) ++ { ++ pNode = &(_gPollTable[i]); ++ ++ if(pNode->nValid && pNode->nTid == nTid && (nFd < 0 || pNode->nDevFD == nFd)) ++ { ++ CamOsMutexUnlock(&_gPollMutex); ++ return pNode; ++ } ++ } ++ ++ CamOsMutexUnlock(&_gPollMutex); ++ ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s : done\n\r", __FUNCTION__); ++ return NULL; ++} ++ ++static CamDevPollNode_t* _CamDevPollNodeFindAndUpdate(u32 nTid, int nFd, short nEvents) ++{ ++ int i; ++ CamDevPollNode_t *pNode; ++ ++ CamOsMutexLock(&_gPollMutex); ++ ++ for (i = 0; i < MAX_POLL_ENTRY_NUM; i++) ++ { ++ pNode = &(_gPollTable[i]); ++ ++ if(pNode->nValid && pNode->nTid == nTid && pNode->nDevFD == nFd) ++ { ++ pNode->nEvents = nEvents; ++ CamOsMutexUnlock(&_gPollMutex); ++ return pNode; ++ } ++ } ++ ++ CamOsMutexUnlock(&_gPollMutex); ++ ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s : done\n\r", __FUNCTION__); ++ return NULL; ++} ++ ++static Ms_Flag_t* _CamDevPollGetOrAllocFlag(u32 nTid) ++{ ++ Ms_Flag_t *pFlag = NULL; ++ CamDevPollNode_t* pNode = _CamDevPollNodeFind(nTid, -1); ++ ++ /* PollTable[tid] exist? */ ++ if (NULL == pNode) ++ { ++ if(!(pFlag = (Ms_Flag_t*)CamOsMemCalloc(1, sizeof(Ms_Flag_t)))) ++ { ++ CAM_POLL_ERR("%s : Allocate flag fail\n\r", __FUNCTION__); ++ return NULL; ++ } ++ ++ memset(pFlag, 0, sizeof(Ms_Flag_t)); ++ MsFlagInit(pFlag); ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[tid:%d] : alloc flag=%x \n\r", __FUNCTION__, nTid, pFlag); ++ } ++ else ++ { ++ pFlag = pNode->pFlag; ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[tid:%d] : found flag=%x \n\r", __FUNCTION__, nTid, pFlag); ++ } ++ return pFlag; ++} ++ ++static int _CamDevPollNodeGetAndClearReventsAndFlag(u32 nTid, int nFd, short nEventsAskedfor) ++{ ++ int nRevents = 0; ++ CamDevPollNode_t* pNode = _CamDevPollNodeFind(nTid, nFd); ++ ++ if (NULL == pNode) ++ { ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[tid=%d, devfd=%d] : not found\n\r", __FUNCTION__, nTid, nFd); ++ return 0; ++ } ++ else ++ { ++ CamOsMutexLock(&_gPollMutex); //???? ++ nRevents = pNode->nRevents & nEventsAskedfor; ++ pNode->nRevents = 0; ++ MsFlagMaskbits(pNode->pFlag, pNode->tFlagBit); ++ CamOsMutexUnlock(&_gPollMutex); ++ CAM_POLL_DBG(POLL_DBG_LV_3,"%s[tid=%d, devfd=%d] : revents=%d (tblEvent=0x%x)\n\r", __FUNCTION__, nTid, nFd, nRevents,pNode->nRevents); ++ return nRevents; ++ } ++} ++ ++/*============================================================================= ++ * ++ * CamDevPollThread: Each fd-poll serviced by a CamDevPollThread. ++ * CamDevPollThread will call driver poll function. ++ * ++ *===========================================================================*/ ++void CamDevPollThread(void) ++{ ++ u32 nTid; ++ int i; ++ /* int nRet; */ ++ CamDevPollNode_t* pNode; ++ CamDevPollThreadPool_t *pPoolNode; ++ short nRevents; ++ ++ _CamDevPollThreadPoolInit(); ++ ++ nTid = CamOsThreadGetID(); ++ i = _PollThreadPoolAdd(nTid); ++ if ( i < 0 ) ++ { ++ CAM_DEV_POLL_PANIC(); ++ } ++ ++ pPoolNode = &_gThdPoolTable[i]; ++ ++ while (1) ++ { ++ CamOsMutexLock(&_gThdPoolMutex); ++ pPoolNode->nSuspend = 1; ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ CAM_POLL_DBG(POLL_DBG_LV_2,"%s[%d, pool:%d] : suspend \n\r", __FUNCTION__, nTid, i); ++ CamOsTsemDown(&pPoolNode->tActiveTsem); ++ CAM_POLL_DBG(POLL_DBG_LV_2,"%s[%d, pool:%d] : running \n\r", __FUNCTION__, nTid, i); ++ CamOsMutexLock(&_gThdPoolMutex); ++ pPoolNode->nSuspend = 0; ++ CamOsMutexUnlock(&_gThdPoolMutex); ++ ++ if (pPoolNode->nUsed) ++ { ++ pNode = (CamDevPollNode_t *)pPoolNode->pUserData; ++ if (NULL == pNode) ++ { ++ CAM_POLL_ERR("%s[%d] : userdata NULL \n\r", __FUNCTION__, i); ++ continue; ++ } ++ /* nRet = */ (*pNode->pfnDrvPoll)(pNode->nDrvFD, pNode->nEvents, &nRevents, pNode->nTimeout); ++ /* if (pNode->nRevents != 0) : we have to return timeout status. So, don't do this. */ ++ { ++ CAM_POLL_DBG(POLL_DBG_LV_0,"%s[pool:%d;tid:%d] : fd=dev:%d. drv:%d event(%d) wakeup bit %x \n\r", __FUNCTION__, i, ++ nTid, pNode->nDevFD, pNode->nDrvFD, pNode->nRevents, pNode->tFlagBit); ++ ++ CamOsMutexLock(&_gPollMutex); ++ pNode->nRevents = nRevents; ++ MsFlagSetbits(pNode->pFlag, pNode->tFlagBit); ++ CamOsMutexUnlock(&_gPollMutex); ++ } ++ } ++ } ++} ++ ++/*============================================================================= ++ * ++ * CamDevPoll: the API emulating linux poll() function ++ * ++ *===========================================================================*/ ++int CamDevPoll(struct pollfd *tFds, int nFds, int nTimeout) ++{ ++ int i; ++ int nRetfd = 0; ++ ++ Ms_Flag_t *pFlag; ++ CamDevPollNode_t* pNode; ++ int nPoolIndex; ++ Ms_flag_value_t tFlagBit, tFlagBitAll=0; ++ ++ u32 nTid = CamOsThreadGetID(); ++ CamDevFD_t *pFdNode[MAX_POLL_FD_A_BATCH] = {NULL}; ++ ++ int nRetFd; ++ ++ CAM_POLL_DBG(POLL_DBG_LV_1,"%s[%d] : in\n\r", __FUNCTION__, nTid); ++ ++ /* 0: CamDevPollInit */ ++ if (CAM_OS_OK != _CamDevPollInit()) ++ { ++ return -1; ++ } ++ ++ /*----------------- poll with single fd -----------------------*/ ++ #if 1 ++ if (1 == nFds) ++ { ++ nRetFd = -1; ++ if(NULL == (pFdNode[0]=_CamDevFindFD(tFds->fd))) ++ { ++ CAM_POLL_ERR("%s : %d find fd fail %d\n\r", __FUNCTION__,tFds->fd); ++ return -1; ++ } ++ CAM_POLL_DBG(POLL_DBG_LV_1,"%s[devfd=%d,drvfd=%d] : call _CamDevFindFD %s done %x\n\r", __FUNCTION__, tFds->fd, pFdNode[0]->nDrvFD, ++ pFdNode[0]->pDevMapFunc->szName, pFdNode[0]->pDevMapFunc->pPoll); ++ ++ if (NULL == pFdNode[0]->pDevMapFunc->pPoll) ++ { ++ CAM_POLL_ERR("%s : no support poll\n\r", pFdNode[0]->pDevMapFunc->szName); ++ return -1; ++ } ++ ++ nRetFd = (*pFdNode[0]->pDevMapFunc->pPoll)(pFdNode[0]->nDrvFD, tFds->events, &tFds->revents, nTimeout); ++ ++ CAM_POLL_DBG(POLL_DBG_LV_0,"%s[tid=%d,nfd=1] : nRetfd=%d\n\r", __FUNCTION__, nTid, nRetfd); ++ return nRetFd; ++ } ++#endif ++ ++ /*--------------- poll with multiple fds ----------------*/ ++ ++ for (i=0; i < nFds; i++) ++ { ++ pFdNode[i] = _CamDevFindFD(tFds[i].fd); ++ if (NULL == pFdNode[i]) ++ { ++ return -1; ++ } ++ ++ if (NULL == pFdNode[i]->pDevMapFunc->pPoll) ++ { ++ CAM_POLL_ERR("%s : no support poll\n\r", pFdNode[0]->pDevMapFunc->szName); ++ return -1; ++ } ++ } ++ ++ /* 1: get revents from poll table, return if there are some events */ ++ for (i=0; i < nFds; i++) ++ { ++ tFds[i].revents = _CamDevPollNodeGetAndClearReventsAndFlag(nTid, tFds[i].fd, tFds[i].events); /* fix me: convert to driverFD */ ++ if (0 != tFds[i].revents) ++ { ++ nRetfd++; ++ } ++ } ++ if (nRetfd > 0) ++ { ++ return nRetfd; ++ } ++ ++ /* 2: Create / resume thread */ ++ ++ /* PollTable[nTid] exist? */ ++ pFlag = _CamDevPollGetOrAllocFlag(nTid); ++ if (NULL == pFlag) ++ { ++ return -1; ++ } ++ ++ for (i=0; i < nFds; i++) ++ { ++ tFlagBit = (1 << i); ++ tFlagBitAll |= tFlagBit; ++ ++ /* if exist, resume PollThread */ ++ pNode = _CamDevPollNodeFindAndUpdate(nTid, tFds[i].fd, tFds[i].events); ++ if (NULL != pNode) ++ { ++ CamOsMutexLock(&_gPollMutex); ++ nPoolIndex = pNode->nPoolIndex; ++ CamOsMutexUnlock(&_gPollMutex); ++ _CamDevPollThreadPoolWakeup(nPoolIndex, nTimeout); ++ } ++ /* if not exist, addPollWaitJob and create pollThread */ ++ else ++ { ++ pNode = _CamDevPollNodeAlloc(nTid, tFds[i].fd, tFds[i].events, nTimeout, pFdNode[i], ++ pFlag, tFlagBit); ++ nPoolIndex = _CamDevPollThreadPoolAlloc(pNode); ++ if (nPoolIndex < 0) ++ { ++ CAM_POLL_ERR("%s[%d,%d] : _CamDevPollThreadCreate failed \n\r", __FUNCTION__, nTid, tFds[i].fd); ++ return -1; //Fix me: error handling ++ ++ } ++ } ++ } ++ ++ CAM_POLL_DBG(POLL_DBG_LV_1,"%s : MsFlagTimedWait waiting\n\r", __FUNCTION__); ++ if (nTimeout >= 0) ++ { ++ tFlagBit = MsFlagTimedWait(pFlag, tFlagBitAll, MS_FLAG_WAITMODE_OR, RTK_MS_TO_TICK(nTimeout)); ++ } ++ else ++ { ++ tFlagBit = MsFlagWait(pFlag, tFlagBitAll, MS_FLAG_WAITMODE_OR|MS_FLAG_WAITMODE_CLR); ++ } ++ ++ CAM_POLL_DBG(POLL_DBG_LV_0,"%s : MsFlagWait wakeup %d\n\r", __FUNCTION__, tFlagBit); ++ if (0 == tFlagBit) // timeout ++ { ++ CAM_POLL_DBG(POLL_DBG_LV_0,"%s[%d] : timeout\n\r", __FUNCTION__,nTid); ++ return 0; ++ } ++ else ++ { ++ for (i = 0; i < nFds; i++) ++ { ++ //if (tFlagBit & (1< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include "vm_types.ht" ++#include "sys_traces.ho" ++ ++#include "sys_sys_isw_cli.h" ++#include "sys_sys_isw_uart.h" ++#include "sys_sys_core.h" ++ ++#include "cam_os_wrapper.h" ++#include "cam_dev_wrapper.h" ++ ++ ++static void _TestCamDevPollThread_scl1_scl2(void *arg) ++{ ++ int i; ++ int handle[2]; ++ struct pollfd fds[2]; ++ int nRetFd = -1; ++ ++ memset(fds, 0, sizeof(fds)); ++ handle[0] = CamDevOpen("/dev/mscldma1"); ++ if (handle[0] == CAM_OS_FAIL) ++ { ++ CamOsPrintf("CamDevOpen /dev/mscldma1 failed\n\r"); ++ return; ++ } ++ ++ handle[1] = CamDevOpen("/dev/mscldma2"); ++ if (handle[1] == CAM_OS_FAIL) ++ { ++ CamOsPrintf("CamDevOpen /dev/mscldma2 failed\n\r"); ++ return; ++ } ++ ++ CamOsPrintf("_TestCamDevPoll: CamDevOpen devfd=%d, %d\n\r", handle[0], handle[1]); ++ ++ for (i = 0; i < 2; i++) ++ { ++ fds[i].fd = handle[i]; ++ fds[i].events = POLLIN; ++ } ++ ++ for (i=0; i < 10; i++) ++ { ++ ++ if ((nRetFd = CamDevPoll(fds, 2, 200)) < 0) ++ { ++ CamOsPrintf("CamDevPoll failed\n\r"); ++ return; ++ } ++ CamOsPrintf("CamDevPoll Loop(%d) nRetFd=%d\n\r", i, nRetFd); ++ CamOsMsSleep(10); ++ } ++ ++ CamDevClose(handle[0]); ++ CamDevClose(handle[1]); ++ ++} ++ ++static void _TestCamDevPollThread_1(void *arg) ++{ ++ int i; ++ int handle = *((int*)arg); ++ struct pollfd fds[1]; ++ int nRetFd = -1; ++ static int nTimeout = 200; ++ ++ memset(fds, 0, sizeof(fds)); ++ fds[0].fd = handle; ++ fds[0].events = POLLIN; ++ ++ for (i=0; i < 10; i++) ++ { ++ ++ if ((nRetFd = CamDevPoll(fds, 1, 500)) < 0) ++ { ++ CamOsPrintf("CamDevPoll failed\n\r"); ++ return; ++ } ++ CamOsPrintf("_TestCamDevPollThread[%d] Loop(%d) nRetFd=%d\n\r", handle, i, nRetFd); ++ CamOsMsSleep(nTimeout); ++ } ++ nTimeout += 100; ++} ++ ++ ++/* a single poll with 2 fds: scl1 & scl2 */ ++static void _TestCamDevPoll_case1() ++{ ++ CamOsThreadAttrb_t attr; ++ CamOsThread thread; ++ CamOsRet_e eRet; ++ ++ attr.nPriority = 50; ++ attr.nStackSize = 4096; ++ eRet = CamOsThreadCreate(&thread, &attr, (void *)_TestCamDevPollThread_scl1_scl2, NULL); ++ if (CAM_OS_OK != eRet) ++ { ++ CamOsPrintf("%s : Create poll thread fail\n\r", __FUNCTION__); ++ } ++ CamOsThreadJoin(thread); ++} ++ ++/* two polls for the same fd */ ++static void _TestCamDevPoll_case2() ++{ ++ CamOsThreadAttrb_t attr; ++ CamOsThread thread1, thread2; ++ CamOsRet_e eRet; ++ int handle; ++ ++ handle = CamDevOpen("/dev/mscldma1"); ++ if (handle == CAM_OS_FAIL) ++ { ++ CamOsPrintf("CamDevOpen /dev/mscldma1 failed\n\r"); ++ return; ++ } ++ ++ CamOsPrintf("_TestCamDevPoll: poll devfd=%d\n\r", handle); ++ ++ attr.nPriority = 50; ++ attr.nStackSize = 4096; ++ eRet = CamOsThreadCreate(&thread1, &attr, (void *)_TestCamDevPollThread_1, &handle); ++ if (CAM_OS_OK != eRet) ++ { ++ CamOsPrintf("%s : Create poll thread fail\n\r", __FUNCTION__); ++ } ++ eRet = CamOsThreadCreate(&thread2, &attr, (void *)_TestCamDevPollThread_1, &handle); ++ if (CAM_OS_OK != eRet) ++ { ++ CamOsPrintf("%s : Create poll thread fail\n\r", __FUNCTION__); ++ } ++ ++ CamOsThreadJoin(thread1); ++ CamOsThreadJoin(thread2); ++ CamDevClose(handle); ++} ++ ++//============================================================================= ++extern void TestCamDrvPoll_byCamDev(void); ++extern void TestCamDrvPoll_Self(void); ++ ++s32 CamDevIoWrapperTest(CLI_t *pCli, char *p) ++{ ++ int i, ParamCnt,ret = -1; ++ u32 case_num = 0; ++ char *pEnd; ++ /* char * value[10]; */ ++ ++ ++ ParamCnt = CliTokenCount(pCli); ++ ++ if (ParamCnt < 1) ++ { ++ return eCLI_PARSE_INPUT_ERROR; ++ } ++ ++ for(i=0;itokenLvl++; ++ p = CliTokenPop(pCli); ++ if(i == 0){ ++ //CLIDEBUG(("p: %s, len: %d\n", p, strlen(p))); ++ //*pV = _strtoul(p, &pEnd, base); ++ case_num= strtoul(p, &pEnd, 10); ++ //CLIDEBUG(("*pEnd = %d\n", *pEnd)); ++ if (p == pEnd || *pEnd) ++ { ++ cliPrintf("Invalid input\n"); ++ return eCLI_PARSE_ERROR; ++ } ++ } ++ /* else{ ++ value[i-1] = p; ++ }*/ ++ ++ } ++ ++ switch (case_num){ ++ case 1: ++ _TestCamDevPoll_case1(); ++ break; ++ case 2: ++ _TestCamDevPoll_case2(); ++ break; ++ case 3: ++ TestCamDrvPoll_byCamDev(); ++ break; ++ case 4: ++ TestCamDrvPoll_Self(); ++ break; ++ default: ++ ret = -1; ++ } ++ ++ if(ret < 0) ++ return eCLI_PARSE_ERROR; ++ ++ return eCLI_PARSE_OK; ++} +diff --git a/drivers/sstar/cam_drv_buffer/HISTORY b/drivers/sstar/cam_drv_buffer/HISTORY +new file mode 100644 +index 000000000000..ae4d6ced79b9 +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/HISTORY +@@ -0,0 +1,6 @@ ++=============================================================================== ++= cam_drv_buffer change log = ++=============================================================================== ++ ++v0.0.1 - 2018-3-23 ++ - code base bring up +diff --git a/drivers/sstar/cam_drv_buffer/Makefile b/drivers/sstar/cam_drv_buffer/Makefile +new file mode 100644 +index 000000000000..f9b3033722a8 +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/Makefile +@@ -0,0 +1,19 @@ ++# ++# Makefile for MStar cam_drv_buffer driver. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/cam_drv_buffer ++EXTRA_CFLAGS += -Idrivers/sstar/cam_drv_buffer/pub ++ ++ ++# specific options ++ ++# files ++obj-y += src/cam_drv_buffer.o src/cam_drv_export.o ++ ++# export header files ++EXPORT_H_FILES += cam_drv_buffer.h +diff --git a/drivers/sstar/cam_drv_buffer/Makefile_Linux_user b/drivers/sstar/cam_drv_buffer/Makefile_Linux_user +new file mode 100644 +index 000000000000..2e923b9a31dc +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/Makefile_Linux_user +@@ -0,0 +1,93 @@ ++CROSS_COMPILE ?=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++STRIP = $(CROSS_COMPILE)strip ++BUILD_DIR := .build ++LIB_NAME=cam_drv_buffer ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++LINUX_KERNEL_PATH ?= $(PWD)/../../../ ++KL_API_INCLUDE ?= $(LINUX_KERNEL_PATH)/drivers/sstar/include ++ ++CFLAGS := -Wall -Werror -g -O2 -ffunction-sections -funwind-tables -fstack-protector ++CFLAGS += -fPIC -DPIC ++ ++CFLAGS += -DTEST_THREAD_ID_DETECTION ++CFLAGS += -DCAM_OS_LINUX_USER ++ ++#CFLAGS += -D__USE_GNU ++LDFLAGS += -O2 -Bdirect -Wl,--hash-style=gnu ++LIBS := -ldl -lpthread ++ ++CORE_LIB_C_SRCS := \ ++ ./src/cam_drv_buffer.c ++ ++CINCLUDES := \ ++ -I$(KL_API_INCLUDE) \ ++ -I./pub \ ++ -I./inc ++ ++LIB_HEADERS := \ ++ ./pub/cam_drv_buffer.h \ ++ ./pub/cam_os_util.h \ ++ ./pub/cam_os_util_list.h \ ++ ./pub/cam_os_util_hash.h \ ++ ./pub/cam_os_util_bitmap.h \ ++ ./pub/cam_os_util_bug.h \ ++ ./pub/cam_os_util_ioctl.h ++ ++CORE_LIB_C_OBJS := $(patsubst %.c, %.c.so.o, $(CORE_LIB_C_SRCS)) ++ ++.PHONY: clean prepare lib$(LIB_NAME) ++ ++all: prepare lib$(LIB_NAME) ++ ++prepare: ++ @echo ++ @echo ">>>>========================================================" ++ @echo ++ @echo " LIB_NAME = ${LIB_NAME}" ++ @echo " PWD = $(shell pwd)" ++ @echo " CC = $(CC)" ++ @echo " BRANCH_ID = $(BRANCH_ID)" ++ @echo ++ @mkdir -p $(BUILD_DIR) ++ @echo " Copying headers to '$(BUILD_DIR)/include'..." ++ @echo ++ @mkdir -p $(BUILD_DIR)/include ++ @cp -f $(LIB_HEADERS) $(BUILD_DIR)/include ++ ++install: ++ @echo " INSTALL $(LIB_NAME) to $(INSTALLDIR)" ++ @rm -Rf $(INSTALLDIR) ++ @mkdir -p $(INSTALLDIR) ++ @cp -Rf $(BUILD_DIR)/lib $(INSTALLDIR) ++ @cp -Rf $(BUILD_DIR)/include $(INSTALLDIR) ++ ++clean: ++ @rm -Rf $(CORE_LIB_C_OBJS) ++ @rm -Rf $(BUILD_DIR) ++ ++lib$(LIB_NAME): prepare $(CORE_LIB_C_OBJS) ++ @mkdir -p $(BUILD_DIR)/lib ++ @echo " LD $(BUILD_DIR)/lib/$@.so" ++ @$(CC) -shared $(LDFLAGS) -o $(BUILD_DIR)/lib/$@.so $(CORE_LIB_C_OBJS) ${LIBS} ++ @echo ++ @echo "<<<<========================================================" ++ @echo ++ ++%.c.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ ++%.c.test.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++ @$(CC) $(CFLAGS) $(TEST_CINCLUDES) -c $< -o $@ ++ ++%.c.so.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ +\ No newline at end of file +diff --git a/drivers/sstar/cam_drv_buffer/cam_drv_buffer.mak b/drivers/sstar/cam_drv_buffer/cam_drv_buffer.mak +new file mode 100644 +index 000000000000..adca5892fbbc +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/cam_drv_buffer.mak +@@ -0,0 +1,19 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_cam_drv_buffer)/src \ ++ $(PATH_cam_drv_buffer)/test ++ ++PATH_H +=\ ++ $(PATH_cam_drv_buffer)/pub \ ++ $(PATH_cam_drv_buffer)/inc ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ cam_drv_buffer.c \ ++ cam_drv_buffer_test.c +\ No newline at end of file +diff --git a/drivers/sstar/cam_drv_buffer/pub/cam_drv_buffer.h b/drivers/sstar/cam_drv_buffer/pub/cam_drv_buffer.h +new file mode 100644 +index 000000000000..e63c916b415c +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/pub/cam_drv_buffer.h +@@ -0,0 +1,219 @@ ++/* ++* cam_drv_buffer.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_drv_buffer.h ++/// @brief Cam Drv Buffer Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_DRV_BUFFER_H__ ++#define __CAM_DRV_BUFFER_H__ ++ ++#define CAM_DRV_BUFFER_VERSION "v0.0.1" ++ ++#include "cam_os_wrapper.h" ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++typedef enum ++{ ++ CAM_DRV_OK = 0, ++ CAM_DRV_NULL_PTR = 1, ++ CAM_DRV_FREE_ERROR = 2, ++ CAM_DRV_QUEUE_EMPTY = 3, ++ CAM_DRV_QUEUE_FULL = 4, ++ CAM_DRV_THREAD_RACE = 5, ++ CAM_DRV_OUT_OF_RANGE = 6, ++ CAM_DRV_FAIL = 7, ++} CamDrvRet_e; ++ ++typedef struct CamDrvQueueNode_s CamDrvQueueNode_t; ++ ++struct CamDrvQueueNode_s ++{ ++ void * pData; ++ CamDrvQueueNode_t* pNext; ++} ; ++ ++typedef struct CamDrvQueue_s ++{ ++ CamDrvQueueNode_t* pHead; ++ CamDrvQueueNode_t* pTail; ++ CamOsAtomic_t count; ++} CamDrvQueue_t; ++ ++typedef struct QueueOps_s ++{ ++ u32 nBufferSize; ++ u32 nThreadSize; ++ CamDrvQueueNode_t *pInsertNode; ++ CamDrvQueue_t* pInvalidHandle; ++ CamDrvQueue_t* pValidHandle; ++ CamDrvQueue_t* pFillHandle; ++ CamDrvQueue_t* pReadyHandle; ++} QueueOps_t; ++ ++//============================================================================= ++// Description: ++// Queue handle initialization ++// Parameters: ++// param[in] max_consumer: Maximum consumer thread count ++// Return: ++// Queue handle pointer ++//============================================================================= ++CamDrvQueue_t* CamDrvQueueInit(u32 nMaxConsumer); ++ ++//============================================================================= ++// Description: ++// Queue handle Release ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvQueueDeinit(CamDrvQueue_t* ptQueue); ++ ++//============================================================================= ++// Description: ++// Enqueue one block buffer ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// param[in] ptPushNode: Push node into queue. If ptPushNode == NULL , will use the memory allocation ++// param[in] ptData: input data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvQueuePush(CamDrvQueue_t* ptQueue, CamDrvQueueNode_t* ptPushNode, void* ptData); ++ ++//============================================================================= ++// Description: ++// Dequeue one block buffer ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// Return: ++// Queue node pointer ++//============================================================================= ++CamDrvQueueNode_t* CamDrvQueuePop(CamDrvQueue_t* ptQueue); ++ ++//============================================================================= ++// Description: ++// Query single buffer info ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// param[out] count: How many node inside ptQueue. ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvQueueQuery(CamDrvQueue_t* ptQueue, s32* ptCount); ++ ++//============================================================================= ++// Description: ++// Buffer handle initialization ++// Parameters: ++// param[in] Buffer_size: The node size of Invalid linked list ++// param[in] max_consumer: Maximum consumer thread count ++// Return: ++// Buffer handle pointer ++//============================================================================= ++QueueOps_t* CamDrvBuffInit(u32 nBufferSize, u32 nMaxConsumer); ++ ++//============================================================================= ++// Description: ++// Buffer handle Release ++// Parameters: ++// param[in] ptBuff: Buffer handle ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffDeinit(QueueOps_t* ptBuff); ++ ++//============================================================================= ++// Description: ++// Add new buffer into valid linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: input data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffAdd(QueueOps_t* ptBuff, void* ptData); ++ ++//============================================================================= ++// Description: ++// Query buffer info for specific linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] size: the number of new buffer ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffQuery(QueueOps_t* ptBuff, s32* ptInvalidSize, s32* ptValidSize, s32* ptFillSize, s32* ptReadySize); ++ ++//============================================================================= ++// Description: ++// Get buffer from ready linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffGet(QueueOps_t* ptBuff, void** pptData); ++ ++//============================================================================= ++// Description: ++// Fill buffer from valid into filling linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffFill(QueueOps_t* ptBuff, void** pptData); ++ ++//============================================================================= ++// Description: ++// Recycle unused buffer from valid into invalid linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffRecycle(QueueOps_t* ptBuff, void** pptData); ++ ++//============================================================================= ++// Description: ++// Extract buffer from fill into ready linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffDone(QueueOps_t* ptBuff); ++ ++#endif /* __CAM_DRV_BUFFER_H__ */ +diff --git a/drivers/sstar/cam_drv_buffer/src/cam_drv_buffer.c b/drivers/sstar/cam_drv_buffer/src/cam_drv_buffer.c +new file mode 100644 +index 000000000000..a437b37f4278 +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/src/cam_drv_buffer.c +@@ -0,0 +1,476 @@ ++/* ++* cam_drv_buffer.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_drv_buffer.c ++/// @brief Cam Drv Buffer Source File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#ifdef CAM_OS_RTK ++#error Cam_Drv_Buffer is unsupport RTK OS now! ++#elif defined(CAM_OS_LINUX_USER) ++#error Cam_Drv_Buffer is unsupport kernel user space now! ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_drv_buffer.h" ++#endif ++ ++#define MAXFREE 150 ++ ++CamDrvQueue_t* CamDrvQueueInit(u32 nMaxConsumer) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamDrvQueue_t* pQueue; ++ u32 nMaxHpSize; ++ ++ pQueue = CamOsMemCalloc(1, sizeof(CamDrvQueue_t)); ++ ++ if(!pQueue) ++ { ++ CamOsPrintf("%s alloc mem fail\n", __FUNCTION__,__LINE__); ++ } ++ ++ do ++ { ++ nMaxHpSize = nMaxConsumer; ++ pQueue->pHead = NULL; ++ pQueue->pTail = NULL; ++ CamOsAtomicSet(&pQueue->count, 0); ++ }while(0); ++ ++ return pQueue; ++#endif ++} ++ ++CamDrvRet_e CamDrvQueueDeinit(CamDrvQueue_t* ptQueue) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptQueue) ++ { ++ CamOsMemRelease(ptQueue); ++ } ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvQueuePush(CamDrvQueue_t* ptQueue, CamDrvQueueNode_t* ptPushNode, void* ptData) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamDrvQueueNode_t* p; ++ ++ if(ptPushNode == NULL) ++ return CAM_DRV_NULL_PTR; ++ ++ ptPushNode->pNext = NULL; ++ ptPushNode->pData = ptData; ++ CamOsSmpMemoryBarrier(); ++ do ++ { ++ p = ptQueue->pTail; ++ }while(!CamOsAtomicCompareAndSwap((CamOsAtomic_t *)&ptQueue->pTail, (s32)p, (s32)ptPushNode)); ++ ++ if(!CamOsAtomicRead(&ptQueue->count)) ++ ptQueue->pHead = ptQueue->pTail; ++ else ++ p->pNext = ptPushNode; ++ ++ CamOsAtomicIncReturn(&ptQueue->count); ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvQueueNode_t* CamDrvQueuePop(CamDrvQueue_t* ptQueue) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamDrvQueueNode_t* p = NULL; ++ CamDrvQueueNode_t* pn = NULL; ++ ++ if(!CamOsAtomicRead(&ptQueue->count)) ++ return NULL; ++ ++ do ++ { ++ p = ptQueue->pHead; ++ CamOsSmpMemoryBarrier(); ++ if(p != ptQueue->pHead) ++ continue; ++ pn = p->pNext; ++ if(pn != p->pNext) ++ return NULL; ++ } while(!CamOsAtomicCompareAndSwap((CamOsAtomic_t *)&ptQueue->pHead, (s32)p, (s32)pn)); ++ ++ CamOsAtomicDecReturn(&ptQueue->count); ++ if(!CamOsAtomicRead(&ptQueue->count)) ++ { ++ ptQueue->pHead = NULL; ++ ptQueue->pTail = NULL; ++ } ++ ++ return p; ++#endif ++} ++ ++CamDrvRet_e CamDrvQueueQuery(CamDrvQueue_t* ptQueue, s32* ptCount) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ *ptCount = CamOsAtomicRead(&ptQueue->count); ++ return CAM_DRV_OK; ++#endif ++} ++ ++QueueOps_t* CamDrvBuffInit(u32 nBufferSize, u32 nMaxConsumer) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ QueueOps_t* pOps; ++ u32 i; ++ ++ pOps = CamOsMemCalloc(1, sizeof(QueueOps_t)); ++ if(pOps == NULL) ++ goto exit; ++ ++ pOps->nBufferSize = nBufferSize; ++ pOps->pInsertNode = CamOsMemCalloc(pOps->nBufferSize, sizeof(CamDrvQueueNode_t)); ++ if(pOps->pInsertNode == NULL) ++ goto exit; ++ ++ do ++ { ++ pOps->nThreadSize = nMaxConsumer; ++ pOps->pInvalidHandle = CamDrvQueueInit(pOps->nThreadSize); ++ pOps->pValidHandle = CamDrvQueueInit(pOps->nThreadSize); ++ pOps->pFillHandle = CamDrvQueueInit(pOps->nThreadSize); ++ pOps->pReadyHandle = CamDrvQueueInit(pOps->nThreadSize); ++ ++ if(!(pOps->pInvalidHandle && pOps->pValidHandle && pOps->pFillHandle && pOps->pReadyHandle)) ++ { ++ if(pOps->pInvalidHandle) ++ { ++ if(CamDrvQueueDeinit(pOps->pInvalidHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ pOps->pInvalidHandle = NULL; ++ } ++ ++ if(pOps->pValidHandle) ++ { ++ if(CamDrvQueueDeinit(pOps->pValidHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ pOps->pValidHandle = NULL; ++ } ++ ++ if(pOps->pFillHandle) ++ { ++ if(CamDrvQueueDeinit(pOps->pFillHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ pOps->pFillHandle = NULL; ++ } ++ ++ if(pOps->pReadyHandle) ++ { ++ if(CamDrvQueueDeinit(pOps->pReadyHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ pOps->pReadyHandle = NULL; ++ } ++ ++ break; ++ } ++ ++ for(i=0; inBufferSize; i++) ++ { ++ if(CamDrvQueuePush(pOps->pInvalidHandle, &pOps->pInsertNode[i], NULL)) ++ goto exit; ++ } ++ ++ return pOps; ++ } while(0); ++ ++exit: ++ ++ if(pOps->pInsertNode) ++ { ++ CamOsMemRelease(pOps->pInsertNode); ++ pOps->pInsertNode = NULL; ++ } ++ ++ if(pOps) ++ { ++ CamOsMemRelease(pOps); ++ pOps = NULL; ++ } ++ ++ return pOps; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffDeinit(QueueOps_t* ptBuff) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptBuff->pInvalidHandle) ++ { ++ if(CamDrvQueueDeinit(ptBuff->pInvalidHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ ptBuff->pInvalidHandle = NULL; ++ } ++ ++ if(ptBuff->pValidHandle) ++ { ++ if(CamDrvQueueDeinit(ptBuff->pValidHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ ptBuff->pValidHandle = NULL; ++ } ++ ++ if(ptBuff->pFillHandle) ++ { ++ if(CamDrvQueueDeinit(ptBuff->pFillHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ ptBuff->pFillHandle = NULL; ++ } ++ ++ if(ptBuff->pReadyHandle) ++ { ++ if(CamDrvQueueDeinit(ptBuff->pReadyHandle)) ++ CamOsPrintf("%s:%d free mem fail\n\r", __FUNCTION__,__LINE__); ++ else ++ ptBuff->pReadyHandle = NULL; ++ } ++ ++ if(ptBuff->pInsertNode) ++ { ++ CamOsMemRelease(ptBuff->pInsertNode); ++ ptBuff->pInsertNode = NULL; ++ } ++ ++ if(ptBuff) ++ { ++ CamOsMemRelease(ptBuff); ++ ptBuff = NULL; ++ } ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffAdd(QueueOps_t* ptBuff, void* ptData) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nCount; ++ CamDrvQueueNode_t* pTempNode; ++ ++ CamDrvQueueQuery(ptBuff->pInvalidHandle, &nCount); ++ if(nCount == 0) ++ return CAM_DRV_OUT_OF_RANGE; ++ ++ pTempNode = CamDrvQueuePop(ptBuff->pInvalidHandle); ++ if(pTempNode == NULL) ++ return CAM_DRV_FAIL; ++ if(CamDrvQueuePush(ptBuff->pValidHandle, pTempNode, ptData)) ++ return CAM_DRV_FAIL; ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffFill(QueueOps_t* ptBuff, void** pptData) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nCount; ++ CamDrvQueueNode_t* pTempNode = NULL; ++ ++ CamDrvQueueQuery(ptBuff->pValidHandle, &nCount); ++ if(nCount == 0) ++ return CAM_DRV_OUT_OF_RANGE; ++ ++ pTempNode = CamDrvQueuePop(ptBuff->pValidHandle); ++ if(pTempNode == NULL) ++ return CAM_DRV_FAIL; ++ *pptData = pTempNode->pData; ++ if(CamDrvQueuePush(ptBuff->pFillHandle, pTempNode, pTempNode->pData)) ++ return CAM_DRV_FAIL; ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffDone(QueueOps_t* ptBuff) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nCount; ++ CamDrvQueueNode_t* pTempNode = NULL; ++ ++ CamDrvQueueQuery(ptBuff->pFillHandle, &nCount); ++ if(nCount == 0) ++ return CAM_DRV_OUT_OF_RANGE; ++ ++ pTempNode = CamDrvQueuePop(ptBuff->pFillHandle); ++ if(pTempNode == NULL) ++ return CAM_DRV_FAIL; ++ if(CamDrvQueuePush(ptBuff->pReadyHandle, pTempNode, pTempNode->pData)) ++ return CAM_DRV_FAIL; ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffGet(QueueOps_t* ptBuff, void** pptData) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nCount; ++ CamDrvQueueNode_t* pTempNode = NULL; ++ ++ CamDrvQueueQuery(ptBuff->pReadyHandle, &nCount); ++ if(nCount == 0) ++ return CAM_DRV_OUT_OF_RANGE; ++ ++ pTempNode = CamDrvQueuePop(ptBuff->pReadyHandle); ++ if(pTempNode == NULL) ++ return CAM_DRV_FAIL; ++ *pptData = pTempNode->pData; ++ if(CamDrvQueuePush(ptBuff->pInvalidHandle, pTempNode, NULL)) ++ return CAM_DRV_FAIL; ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffRecycle(QueueOps_t* ptBuff, void** pptData) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nCount; ++ CamDrvQueueNode_t* pTempNode = NULL; ++ ++ CamDrvQueueQuery(ptBuff->pValidHandle, &nCount); ++ if(nCount == 0) ++ return CAM_DRV_OUT_OF_RANGE; ++ ++ pTempNode = CamDrvQueuePop(ptBuff->pValidHandle); ++ if(pTempNode == NULL) ++ return CAM_DRV_FAIL; ++ *pptData = pTempNode->pData; ++ if(CamDrvQueuePush(ptBuff->pInvalidHandle, pTempNode, NULL)) ++ return CAM_DRV_FAIL; ++ ++ return CAM_DRV_OK; ++#endif ++} ++ ++CamDrvRet_e CamDrvBuffQuery(QueueOps_t* ptBuff, s32* ptInvalidSize, s32* ptValidSize, s32* ptFillSize, s32* ptReadySize) ++{ ++ // query buffer(data) or linked-list size ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nCount; ++ ++ CamDrvQueueQuery(ptBuff->pInvalidHandle, &nCount); ++ *ptInvalidSize = nCount; ++ CamDrvQueueQuery(ptBuff->pValidHandle, &nCount); ++ *ptValidSize = nCount; ++ CamDrvQueueQuery(ptBuff->pFillHandle, &nCount); ++ *ptFillSize = nCount; ++ CamDrvQueueQuery(ptBuff->pReadyHandle, &nCount); ++ *ptReadySize = nCount; ++ ++ return CAM_DRV_OK; ++#endif ++} +diff --git a/drivers/sstar/cam_drv_buffer/src/cam_drv_export.c b/drivers/sstar/cam_drv_buffer/src/cam_drv_export.c +new file mode 100644 +index 000000000000..d461ae9966a7 +--- /dev/null ++++ b/drivers/sstar/cam_drv_buffer/src/cam_drv_export.c +@@ -0,0 +1,42 @@ ++/* ++* cam_drv_export.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_drv_export.c ++/// @brief Cam Drv Export Symbol Source File for Linux Kernel Space ++/// Only Include This File in Linux Kernel ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include "cam_drv_buffer.h" ++ ++MODULE_LICENSE("GPL"); ++ ++EXPORT_SYMBOL(CamDrvQueueInit); ++EXPORT_SYMBOL(CamDrvQueueDeinit); ++EXPORT_SYMBOL(CamDrvQueuePush); ++EXPORT_SYMBOL(CamDrvQueuePop); ++EXPORT_SYMBOL(CamDrvQueueQuery); ++ ++EXPORT_SYMBOL(CamDrvBuffInit); ++EXPORT_SYMBOL(CamDrvBuffDeinit); ++EXPORT_SYMBOL(CamDrvBuffAdd); ++EXPORT_SYMBOL(CamDrvBuffGet); ++EXPORT_SYMBOL(CamDrvBuffRecycle); ++EXPORT_SYMBOL(CamDrvBuffFill); ++EXPORT_SYMBOL(CamDrvBuffQuery); ++EXPORT_SYMBOL(CamDrvBuffDone); +diff --git a/drivers/sstar/cam_drv_poll/Makefile b/drivers/sstar/cam_drv_poll/Makefile +new file mode 100644 +index 000000000000..5a965666f7b8 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for SigmaStar cam_drv_poll driver. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/cam_drv_poll/pub ++ ++ ++# specific options ++ ++# files ++obj-y += src/cam_drv_poll.o ++ ++# export header files ++EXPORT_H_FILES += cam_drv_poll.h +diff --git a/drivers/sstar/cam_drv_poll/cam_drv_poll.mak b/drivers/sstar/cam_drv_poll/cam_drv_poll.mak +new file mode 100644 +index 000000000000..c7f8cac6538b +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/cam_drv_poll.mak +@@ -0,0 +1,26 @@ ++ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_cam_drv_poll)/src \ ++# $(PATH_cam_drv_poll)/sample_driver/src/drv/common \ ++# $(PATH_cam_drv_poll)/sample_driver/src/drv/rtk \ ++# $(PATH_cam_drv_poll)/sample_driver/test/camdrvpolltest ++ ++PATH_H +=\ ++ $(PATH_cam_os_wrapper)/pub \ ++ $(PATH_cam_drv_poll)/pub \ ++# $(PATH_cam_drv_poll)/sample_driver/inc \ ++# $(PATH_cam_drv_poll)/sample_driver/pub ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ cam_drv_poll.c \ ++# drv_pollsample_dev.c \ ++# drv_pollsample_module.c \ ++# cam_drv_poll_test.c +diff --git a/drivers/sstar/cam_drv_poll/pub/cam_drv_poll.h b/drivers/sstar/cam_drv_poll/pub/cam_drv_poll.h +new file mode 100644 +index 000000000000..c7794ef86dfe +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/pub/cam_drv_poll.h +@@ -0,0 +1,55 @@ ++/* ++* cam_drv_poll.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __CAM_DRV_POLL_H__ ++#define __CAM_DRV_POLL_H__ ++ ++#define CAM_DRV_POLL_VERSION "v1.0.1" ++ ++#include ++ ++#ifdef CAM_OS_RTK ++ ++#ifndef POLLIN ++#define POLLIN 0x1 ++#define POLLPRI 0x2 ++#define POLLOUT 0x4 ++#define POLLERR 0x8 ++#define POLLRDNORM 0x40 ++#endif ++ ++struct file ++{ ++ //u8 nPollval; // the event to be polled ++ s32 nPollTimeout; // used internally by poll ++ void *private_data; // for drivers’ private use ++}; ++ ++typedef void poll_table; ++#elif defined(__KERNEL__) ++#include ++#include ++#endif ++ ++s32 CamDrvPollRegEventGrp(void); ++void CamDrvPollDeRegEventGrp(u32 nEventID); ++void CamDrvPollSetEvent(u32 nEventID, u32 nEventBits); ++s32 CamDrvPollEvent(u32 nEventID, u32 nWaitBits, struct file *filp, poll_table *tPoll); ++ ++ ++#endif /* __CAM_DRV_POLL_H__ */ +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/Makefile b/drivers/sstar/cam_drv_poll/sample_driver/Makefile +new file mode 100644 +index 000000000000..1dbc49067f60 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/Makefile +@@ -0,0 +1,18 @@ ++obj-m := pollsample.o ++pollsample-objs := src/drv/linux/drv_pollsample_module.o \ ++ src/drv/linux/drv_pollsample_export.o \ ++ src/drv/common/drv_pollsample_dev.o ++ ++export ARCH=arm ++export CROSS_COMPILE=arm-linux-gnueabihf- ++ ++KERNEL_PATH = /home/david.tsai/I2/linux-3.18 ++CC = $(CROSS_COMPILE)gcc ++EXTRA_CFLAGS += -I$(KERNEL_PATH)/drivers/sstar/cam_drv_poll/sample_driver/pub/ \ ++ -I$(KERNEL_PATH)/drivers/sstar/cam_drv_poll/sample_driver/inc \ ++ -I$(KERNEL_PATH)/drivers/sstar/include/ ++ ++all: ++ make modules -C $(KERNEL_PATH) M=`pwd` ++clean: ++ make modules clean -C $(KERNEL_PATH) M=`pwd` +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/inc/mdrv_pollsample_module.h b/drivers/sstar/cam_drv_poll/sample_driver/inc/mdrv_pollsample_module.h +new file mode 100644 +index 000000000000..6140a4856272 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/inc/mdrv_pollsample_module.h +@@ -0,0 +1,45 @@ ++/* ++* mdrv_pollsample_module.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __MDRV_POLLSAMPLE_MODULE_H__ ++#define __MDRV_POLLSAMPLE_MODULE_H__ ++ ++#include "cam_os_wrapper.h" ++#include "cam_drv_poll.h" ++ ++#if defined(__KERNEL__) ++#include ++#endif ++ ++typedef struct ++{ ++#if defined(__KERNEL__) ++ struct cdev m_cdev; // character device ++#else ++ void* m_cdev; ++#endif ++ // Device private data ++ int nTestNum; ++} PollSampleDev_t; ++ ++int pollsamp_open(struct inode *inode, struct file *filp); ++int pollsamp_release(struct inode *inode, struct file *filp); ++long pollsamp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++unsigned int pollsamp_poll(struct file *filp, poll_table *tpoll); ++ ++#endif /* __MDRV_POLLSAMPLE_MODULE_H__ */ +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/pub/mdrv_pollsample_io.h b/drivers/sstar/cam_drv_poll/sample_driver/pub/mdrv_pollsample_io.h +new file mode 100644 +index 000000000000..4ad3db085fa3 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/pub/mdrv_pollsample_io.h +@@ -0,0 +1,34 @@ ++/* ++* mdrv_pollsample_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __MDRV_POLLSAMPLE_IO_H__ ++#define __MDRV_POLLSAMPLE_IO_H__ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++#include ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++#define MAGIC_POLLSAMPLE ('p') ++#define IOCTL_POLLSAMPLE_START_TIMER CAM_OS_IOR(MAGIC_POLLSAMPLE, 0, unsigned int) ++#define IOCTL_POLLSAMPLE_GET_TIME CAM_OS_IOR(MAGIC_POLLSAMPLE, 1, unsigned int) ++ ++#endif//__MDRV_POLLSAMPLE_IO_H__ +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/src/drv/common/drv_pollsample_dev.c b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/common/drv_pollsample_dev.c +new file mode 100644 +index 000000000000..ecb72df0bc45 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/common/drv_pollsample_dev.c +@@ -0,0 +1,209 @@ ++/* ++* drv_pollsample_dev.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#define _WITH_CAM_DRV_POLL 1 // This option only can disable in Linux ++ ++#ifndef EFAULT ++#define EFAULT 14 // for non-Linux OS ++#endif ++ ++#if !_WITH_CAM_DRV_POLL ++#include ++#include ++#include ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++#define EVENT_TIMER1 0x00000001 ++#define EVENT_TIMER2 0x00000002 ++ ++struct _driver_private_data; ++typedef struct _timer_cb_param ++{ ++ u32 timer_event_id; ++ u32 timer_event_bit; ++ u32 timer_msec; ++ struct _driver_private_data *dpd; ++} timer_cb_param; ++ ++typedef struct _driver_private_data ++{ ++ u32 eventGrp_id; ++ timer_cb_param event_timer1_param; ++ timer_cb_param event_timer2_param; ++ CamOsTimer_t event_timer1; ++ CamOsTimer_t event_timer2; ++#if !_WITH_CAM_DRV_POLL ++ s32 flag; ++ wait_queue_head_t wait; ++#endif ++} driver_private_data; ++ ++ ++static void MyTimerFunction(unsigned long data) ++{ ++ driver_private_data *dpd; ++ timer_cb_param *tcbp = (timer_cb_param *)data; ++ ++ if(tcbp) ++ { ++ dpd = tcbp->dpd; ++#if _WITH_CAM_DRV_POLL ++ CamDrvPollSetEvent(tcbp->timer_event_id, tcbp->timer_event_bit); ++#else ++ dpd->flag |= tcbp->timer_event_bit; ++ wake_up_interruptible(&dpd->wait); ++#endif ++ CamOsPrintf("time_callback triggered(event=%d,bits=0x%x)\n", tcbp->timer_event_id, tcbp->timer_event_bit); ++ ++ if(tcbp->timer_event_bit == EVENT_TIMER1) ++ { ++ CamOsTimerModify(&dpd->event_timer1, tcbp->timer_msec); ++ } ++ else if(tcbp->timer_event_bit == EVENT_TIMER2) ++ { ++ CamOsTimerModify(&dpd->event_timer2, tcbp->timer_msec); ++ } ++ } ++} ++ ++int pollsamp_open(struct inode *inode, struct file *filp) ++{ ++ PollSampleDev_t *pPollSampleDev = CAM_OS_CONTAINER_OF(inode->i_cdev,PollSampleDev_t,m_cdev); ++ driver_private_data *dpd; ++ ++ CamOsPrintf("%s: nTestNum = %d\n", __FUNCTION__, pPollSampleDev->nTestNum); ++ ++ dpd = (driver_private_data *)filp->private_data; ++ if(!dpd) ++ { ++ dpd = (driver_private_data *)CamOsMemCalloc(1, sizeof(driver_private_data)); ++ filp->private_data = dpd; ++ ++ CamOsTimerInit(&dpd->event_timer1); ++ CamOsTimerInit(&dpd->event_timer2); ++ ++#if _WITH_CAM_DRV_POLL ++ dpd->eventGrp_id = CamDrvPollRegEventGrp(); ++#else ++ dpd->flag = 0; ++ init_waitqueue_head(&dpd->wait); ++#endif ++ CamOsPrintf("%s: eventId=%d\n", __func__, dpd->eventGrp_id); ++ } ++ return 0; ++} ++ ++int pollsamp_release(struct inode *inode, struct file *filp) ++{ ++ driver_private_data *dpd; ++ ++ CamOsPrintf("pollsample release!\n"); ++ dpd = (driver_private_data *)filp->private_data; ++#if _WITH_CAM_DRV_POLL ++ CamDrvPollDeRegEventGrp(dpd->eventGrp_id); ++#endif ++ CamOsTimerDelete(&dpd->event_timer1); ++ CamOsTimerDelete(&dpd->event_timer2); ++ return 0; ++} ++ ++long pollsamp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ driver_private_data *dpd = (driver_private_data*)filp->private_data; ++ int err = 0; ++ s32 expire; ++ ++ // Should we do that? ++ if(dpd == NULL) ++ { ++ CamOsPrintf("dpd NULL !!\n"); ++ return -EFAULT; ++ } ++ ++ switch(cmd) ++ { ++ case IOCTL_POLLSAMPLE_START_TIMER: ++ CamOsCopyFromUpperLayer(&expire, (void*)arg, sizeof(expire)); ++ if(expire < 0) ++ { ++ CamOsPrintf("get user data Failed !!\n"); ++ err = -EFAULT; ++ break; ++ } ++ CamOsPrintf("IOCTL_POLLSAMPLE_START_TIMER: get expire=%d msec\n", expire); ++ dpd->event_timer1_param.timer_event_id = dpd->eventGrp_id; ++ dpd->event_timer1_param.timer_event_bit = EVENT_TIMER1; ++ dpd->event_timer1_param.timer_msec = expire; ++ dpd->event_timer1_param.dpd = dpd; ++ CamOsTimerAdd(&dpd->event_timer1, expire, (void *)&dpd->event_timer1_param, MyTimerFunction); ++ dpd->event_timer2_param.timer_event_id = dpd->eventGrp_id; ++ dpd->event_timer2_param.timer_event_bit = EVENT_TIMER2; ++ dpd->event_timer2_param.timer_msec = expire + 500; ++ dpd->event_timer2_param.dpd = dpd; ++ CamOsTimerAdd(&dpd->event_timer2, (expire+500), (void *)&dpd->event_timer2_param, MyTimerFunction); ++ break; ++ ++ default: ++ err = -EFAULT; ++ break; ++ } ++ ++ return err; ++} ++ ++unsigned int pollsamp_poll(struct file *filp, poll_table *tpoll) ++{ ++ driver_private_data *dpd = filp->private_data; ++ unsigned int mask = 0; ++ ++#if _WITH_CAM_DRV_POLL ++ u32 eventBits; ++ ++ eventBits = CamDrvPollEvent(dpd->eventGrp_id, EVENT_TIMER1 | EVENT_TIMER2, filp, tpoll); ++ if((eventBits & EVENT_TIMER1) != 0) ++ { ++ CamOsPrintf("pollsamp_poll: got event bits=0x%x\n", eventBits); ++ mask |= POLLIN; ++ } ++ if((eventBits & EVENT_TIMER2) != 0) ++ { ++ CamOsPrintf("pollsamp_poll: got event bits=0x%x\n", eventBits); ++ mask |= POLLPRI; ++ } ++#else ++ if (dpd) ++ { ++ poll_wait(filp, &dpd->wait, tpoll); ++ if (dpd->flag) ++ { ++ if (dpd->flag & EVENT_TIMER1) ++ mask |= POLLIN; ++ if (dpd->flag & EVENT_TIMER2) ++ mask |= POLLPRI; ++ dpd->flag=0; ++ } ++ } ++#endif ++ return mask; ++} +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/src/drv/linux/drv_pollsample_export.c b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/linux/drv_pollsample_export.c +new file mode 100644 +index 000000000000..29ca8ae47bcd +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/linux/drv_pollsample_export.c +@@ -0,0 +1,21 @@ ++/* ++* drv_pollsample_export.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++//EXPORT_SYMBOL([functions needed to be exported]); +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/src/drv/linux/drv_pollsample_module.c b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/linux/drv_pollsample_module.c +new file mode 100644 +index 000000000000..53eb6c9bc9b3 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/linux/drv_pollsample_module.c +@@ -0,0 +1,113 @@ ++/* ++* drv_pollsample_module.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include "mdrv_pollsample_module.h" ++ ++static struct file_operations pollsample_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = pollsamp_open, ++ .release = pollsamp_release, ++ .unlocked_ioctl = pollsamp_ioctl, ++ .poll = pollsamp_poll, ++}; ++ ++#define CHRDEV_NAME "pollsample" ++static struct class *chrdev_class = NULL; ++static struct device *chrdev_device = NULL; ++static dev_t chrdev_devno; ++ ++PollSampleDev_t tPollSampleDev; ++ ++static __init int pollsample_init(void) ++{ ++ int ret = 0, err = 0; ++ ++ printk(KERN_ALERT "pollsample_init!\n"); ++ ++ // alloc character device number ++ ret = alloc_chrdev_region(&chrdev_devno, 0, 1, CHRDEV_NAME); ++ if(ret) ++ { ++ printk(KERN_ALERT " alloc_chrdev_region failed!\n"); ++ goto PROBE_ERR; ++ } ++ printk(KERN_ALERT " major:%d minor:%d\n", MAJOR(chrdev_devno), MINOR(chrdev_devno)); ++ ++ tPollSampleDev.nTestNum = 12345; ++ ++ cdev_init(&tPollSampleDev.m_cdev, &pollsample_fops); ++ tPollSampleDev.m_cdev.owner = THIS_MODULE; ++ // add a character device ++ err = cdev_add(&tPollSampleDev.m_cdev, chrdev_devno, 1); ++ if(err) ++ { ++ printk(KERN_ALERT " cdev_add failed!\n"); ++ goto PROBE_ERR; ++ } ++ ++ // create the device class ++ chrdev_class = class_create(THIS_MODULE, CHRDEV_NAME); ++ if(IS_ERR(chrdev_class)) ++ { ++ printk(KERN_ALERT " class_create failed!\n"); ++ goto PROBE_ERR; ++ } ++ ++ // create the device node in /dev ++ chrdev_device = device_create(chrdev_class, NULL, chrdev_devno, ++ NULL, CHRDEV_NAME); ++ if(NULL == chrdev_device) ++ { ++ printk(KERN_ALERT " device_create failed!\n"); ++ goto PROBE_ERR; ++ } ++ ++ printk(KERN_ALERT " pollsample_init ok!\n"); ++ return 0; ++ ++PROBE_ERR: ++ if(err) ++ cdev_del(&tPollSampleDev.m_cdev); ++ if(ret) ++ unregister_chrdev_region(chrdev_devno, 1); ++ return -1; ++} ++ ++static __exit void pollsample_exit(void) ++{ ++ printk(KERN_ALERT " pollsample_exit!\n"); ++ ++ cdev_del(&tPollSampleDev.m_cdev); ++ unregister_chrdev_region(chrdev_devno, 1); ++ ++ device_destroy(chrdev_class, chrdev_devno); ++ class_destroy(chrdev_class); ++ //return 0; ++} ++ ++module_init(pollsample_init); ++module_exit(pollsample_exit); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("pollsample driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/src/drv/rtk/drv_pollsample_module.c b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/rtk/drv_pollsample_module.c +new file mode 100644 +index 000000000000..b430c2f0b969 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/src/drv/rtk/drv_pollsample_module.c +@@ -0,0 +1,119 @@ ++/* ++* drv_pollsample_module.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include "mdrv_pollsample_module.h" ++ ++#define DRV_POLL_SAMPLE "/dev/pollsample" ++ ++int CamDevPollSampleOpen(struct inode *pInode); ++int CamDevPollSampleClose(int nFd, struct inode *pInode); ++int CamDevPollSampleIoctl(int nFd, unsigned long nRequest, void *pParam); ++int CamDevPollSamplePoll(int nFd, short nEvents, short *pnRevent ,int nTimeout); ++ ++PollSampleDev_t tPollSampleDev; ++ ++static CamDevFuncMap_t tPollSampleFuncMap = { ++ .szName = DRV_POLL_SAMPLE, ++ .pOpen = CamDevPollSampleOpen, ++ .pClose = CamDevPollSampleClose, ++ .pIoctl = CamDevPollSampleIoctl, ++ .pPoll = CamDevPollSamplePoll, ++ .pInode = NULL, ++}; ++ ++int CamDevPollSampleOpen(struct inode *pInode) ++{ ++ struct file *filp; ++ ++ filp = (struct file *)CamOsMemCalloc(1, sizeof(struct file)); ++ ++ if (pollsamp_open(pInode, filp) == 0) /* success */ ++ { ++ return (int)filp; ++ } ++ else ++ { ++ CamOsMemRelease(filp); ++ return CAM_OS_FAIL; ++ } ++} ++ ++int CamDevPollSampleClose(int nFd, struct inode *pInode) ++{ ++ struct file *filp = (struct file *)nFd; ++ ++ pollsamp_release(pInode, filp); ++ CamOsMemRelease(filp); ++ ++ return CAM_OS_OK; ++} ++ ++int CamDevPollSampleIoctl(int nFd, unsigned long nRequest, void *pParam) ++{ ++ int nRet = CAM_OS_OK; ++ struct file *filp = (struct file *)nFd; ++ ++ if (pollsamp_ioctl(filp, nRequest, (unsigned long)pParam) != 0) ++ { ++ nRet = CAM_OS_FAIL; ++ } ++ ++ return nRet; ++} ++ ++int CamDevPollSamplePoll(int nFd, short nEvents, short *pnRevent ,int nTimeout) ++{ ++ struct file *filp = (struct file *)nFd; ++ u32 nRevent; ++ ++ filp->nPollTimeout = nTimeout; ++ nRevent = pollsamp_poll(filp, NULL); ++ ++ *pnRevent = nRevent & nEvents; ++ CamOsPrintf("%s: revent=0x%x\n",__func__, *pnRevent); ++ return (*pnRevent != 0) ? 1 : 0; ++} ++ ++int CamDevPollSampleInit(void) ++{ ++ tPollSampleDev.nTestNum = 12345; ++ if ((tPollSampleFuncMap.pInode = CamOsMemAlloc(sizeof(struct inode))) == NULL) ++ { ++ CamOsPrintf("%s: memory allocate fail!\r\n", __FUNCTION__); ++ return -1; ++ } ++ ++ tPollSampleFuncMap.pInode->i_cdev = (void *)&tPollSampleDev.m_cdev; ++ ++ if (CAM_OS_OK == CamDevRegister(&tPollSampleFuncMap)) ++ return 0; ++ else ++ return -1; ++} ++ ++void CamDevPollSampleRelease(void) ++{ ++ CamDevUnregister(DRV_POLL_SAMPLE); ++ ++ if (tPollSampleFuncMap.pInode) ++ { ++ CamOsMemRelease(tPollSampleFuncMap.pInode); ++ tPollSampleFuncMap.pInode = NULL; ++ } ++} +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/test/camdrvpolltest/Makefile b/drivers/sstar/cam_drv_poll/sample_driver/test/camdrvpolltest/Makefile +new file mode 100644 +index 000000000000..947871000461 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/test/camdrvpolltest/Makefile +@@ -0,0 +1,52 @@ ++PLATFORM_NAME := "\#" #This is a multi platform component ++CHIP_ID := "\#" ++ ++LOCAL_MODULE_NAME=cam_drv_poll_test ++LOCAL_MODULE_TYPE=BIN ++#LINUX_KERNEL_PATH ?= ../../../../kernel/API ++LINUX_KERNEL_PATH = /home/david.tsai/I2/linux-3.18/ ++LIB_PATH = /home/david.tsai/I3/ ++ ++KL_API_INCLUDE ?= $(LINUX_KERNEL_PATH)/drivers/sstar/include ++ ++LOCAL_CINCLUDES += -I$(KL_API_INCLUDE) ++LOCAL_CINCLUDES += -I../../pub -I$(LINUX_KERNEL_PATH)/drivers/sstar/cam_drv_poll/pub ++LOCAL_CINCLUDES += -I$(LIB_PATH)/cam_os_wrapper/pub -I$(LIB_PATH)/cam_dev_wrapper/pub ++LOCAL_LDFLAGS += -L$(LIB_PATH)/cam_os_wrapper/.build/lib -L$(LIB_PATH)/cam_dev_wrapper/.build/lib ++LOCAL_LIBS += -lcam_os_wrapper -lcam_dev_wrapper ++ ++ ++#LOCAL_CSRCS=$(wildcard ./*.c) ++LOCAL_CSRCS=cam_drv_poll_test.c ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++#include ../../../rules.mk ++CROSS_COMPILE ?=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++STRIP ?= $(CROSS_COMPILE)strip ++ ++CFLAGS = -Wall -Werror -O2 -fPIC -DPIC -g -ffunction-sections -funwind-tables -fstack-protector ++CFLAGS += -DCAM_OS_LINUX_USER ++ ++OMX_TOP_DIR=../../../ ++LOCAL_BUILD_DIR ?= .build ++LOCAL_COBJS = $(patsubst %.c, %.c.o, $(LOCAL_CSRCS)) ++LIBS = -ldl -lpthread -lrt -lm ++LDFLAGS = -O2 -Bdirect -Wl,--hash-style=gnu ++ ++$(LOCAL_MODULE_NAME): $(LOCAL_COBJS) ++ @mkdir -p $(LOCAL_BUILD_DIR)/bin ++ @echo " LD $(LOCAL_BUILD_DIR)/bin/$@" ++ @$(CC) $(LDFLAGS) $(LOCAL_LDFLAGS) -o $(LOCAL_BUILD_DIR)/bin/$@ $(LOCAL_COBJS) $(LIBS) $(LOCAL_LIBS) ++ @echo ++ ++clean: ++ @echo " CLEAN $(shell pwd)" ++ @rm -Rf $(COBJS) ++ @rm -Rf $(LOCAL_COBJS) ++ @rm -Rf $(LOCAL_BUILD_DIR) ++ ++%.c.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++ $(CC) $(CFLAGS) $(LOCAL_CFLAGS) $(LOCAL_CINCLUDES) -c $< -o $@ +diff --git a/drivers/sstar/cam_drv_poll/sample_driver/test/camdrvpolltest/cam_drv_poll_test.c b/drivers/sstar/cam_drv_poll/sample_driver/test/camdrvpolltest/cam_drv_poll_test.c +new file mode 100644 +index 000000000000..3e395ef8f84a +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/sample_driver/test/camdrvpolltest/cam_drv_poll_test.c +@@ -0,0 +1,209 @@ ++/* ++* cam_drv_poll_test.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#ifdef CAM_OS_RTK ++#include "sys_sys_core.h" ++#include "sys_sys_isw_cli.h" ++#endif ++#define POLL_LOOP_CNT 10 ++ ++static void _CamDrvPollShowTestMenu(void) ++{ ++ CamOsPrintf("cam_drv_poll test menu: \n"); ++ CamOsPrintf("\t0) Poll sample test\r\n"); ++} ++ ++static void _TestCamDrvPollThread(void *arg) ++{ ++ int handle[1]; ++ struct pollfd fds[1]; ++ int nRetFd = -1; ++ int nTime = 2000; /* msec */ ++ int cnt = 0, timeoutCnt = 0; ++ ++ memset(fds, 0, sizeof(fds)); ++ handle[0] = CamDevOpen("/dev/pollsample"); ++ if (handle[0] == CAM_OS_FAIL) ++ { ++ CamOsPrintf("CamDevOpen /dev/pollsample failed\n\r"); ++ return; ++ } ++ CamOsPrintf("CamDevOpen /dev/pollsample fd=%d\n\r", handle[0]); ++ ++ ++ if (0 != CamDevIoctl(handle[0], IOCTL_POLLSAMPLE_START_TIMER, (void*)&nTime)) ++ { ++ CamOsPrintf("IOCTL_POLLSAMPLE_START_TIMER failed\n\r"); ++ CamDevClose(handle[0]); ++ return; ++ } ++ ++ do { ++ fds[0].fd = handle[0]; ++ fds[0].events = POLLOUT; //POLLPRI; ++ if ((nRetFd = CamDevPoll(&fds[0], 1, 5000)) < 0) ++ { ++ CamOsPrintf("CamDevPoll failed\n\r"); ++ } ++ ++ CamOsPrintf("CamDevPoll(POLLPRI) done nRetFd=%d, events=0x%x\n\r", nRetFd, fds[0].revents); ++ if (nRetFd != 0) ++ { ++ ++cnt; ++ } ++ else ++ { ++ ++timeoutCnt; ++ } ++ } while ((cnt < 2) && (timeoutCnt < 2)); ++ ++ do { ++ fds[0].fd = handle[0]; ++ fds[0].events = POLLIN | POLLPRI; ++ if ((nRetFd = CamDevPoll(&fds[0], 1, 10000)) < 0) ++ { ++ CamOsPrintf("CamDevPoll failed\n\r"); ++ } ++ ++ CamOsPrintf("CamDevPoll done nRetFd=%d, events=0x%x\n\r", nRetFd, fds[0].revents); ++ if (fds[0].revents & POLLIN) ++ { ++ CamOsPrintf("CamDevPoll got POLLIN\n\r"); ++ } ++ if (fds[0].revents & POLLPRI) ++ { ++ CamOsPrintf("CamDevPoll got POLLPRI\n\r"); ++ } ++ } while ((++cnt < POLL_LOOP_CNT) && nRetFd > 0); ++ ++ CamDevClose(handle[0]); ++} ++ ++void TestCamDrvPoll_byCamDev(void) ++{ ++ CamOsThread thread; ++ CamOsRet_e eRet = CAM_OS_OK; ++ ++ eRet = CamOsThreadCreate(&thread, NULL, (void *)_TestCamDrvPollThread, NULL); ++ if (CAM_OS_OK != eRet) ++ { ++ CamOsPrintf("%s : Create poll thread fail(err=%d)\n\r", __FUNCTION__, (int)eRet); ++ } ++ CamOsThreadJoin(thread); ++} ++ ++#ifdef CAM_OS_RTK ++extern int CamDevPollSampleInit(void); ++extern void CamDevPollSampleRelease(void); ++ ++void TestCamDrvPoll_Rtk(void) ++{ ++ CamDevPollSampleInit(); ++ TestCamDrvPoll_byCamDev(); ++ CamDevPollSampleRelease(); ++} ++ ++int CamDrvPollTest(CLI_t *pCli, char *p) ++{ ++ int i, ParamCnt, ret = 0; ++ u32 case_num = 0; ++ char *pEnd; ++ ++ ParamCnt = CliTokenCount(pCli); ++ ++ if(ParamCnt < 1) ++ { ++ _CamDrvPollShowTestMenu(); ++ return eCLI_PARSE_INPUT_ERROR; ++ } ++ ++ for(i = 0; i < ParamCnt; i++) ++ { ++ pCli->tokenLvl++; ++ p = CliTokenPop(pCli); ++ if(i == 0) ++ { ++ //CLIDEBUG(("p: %s, len: %d\n", p, strlen(p))); ++ //*pV = _strtoul(p, &pEnd, base); ++ case_num = strtoul(p, &pEnd, 10); ++ //CLIDEBUG(("*pEnd = %d\n", *pEnd)); ++ if(p == pEnd || *pEnd) ++ { ++ cliPrintf("Invalid input\n"); ++ return eCLI_PARSE_ERROR; ++ } ++ } ++ /* else{ ++ value[i-1] = p; ++ }*/ ++ ++ } ++ ++ switch(case_num) ++ { ++ case 0: ++ TestCamDrvPoll_Rtk(); ++ break; ++ default: ++ _CamDrvPollShowTestMenu(); ++ ret = -1; ++ break; ++ } ++ ++ if(ret < 0) ++ return eCLI_PARSE_ERROR; ++ ++ return eCLI_PARSE_OK; ++} ++#else // Linux ++int main(int argc, char *argv[]) ++{ ++ int ret=0; ++ ++ if (argc != 2) ++ { ++ _CamDrvPollShowTestMenu(); ++ return -1; ++ } ++ ++ switch (atoi(argv[1])) ++ { ++ case 0: ++ TestCamDrvPoll_byCamDev(); ++ break; ++ default: ++ ret = -1; ++ break; ++ } ++ ++ if (ret < 0) ++ { ++ _CamDrvPollShowTestMenu(); ++ return -1; ++ } ++ ++ return 0; ++} ++#endif +diff --git a/drivers/sstar/cam_drv_poll/src/cam_drv_poll.c b/drivers/sstar/cam_drv_poll/src/cam_drv_poll.c +new file mode 100644 +index 000000000000..3930ef535212 +--- /dev/null ++++ b/drivers/sstar/cam_drv_poll/src/cam_drv_poll.c +@@ -0,0 +1,229 @@ ++/* ++* cam_drv_poll.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++ ++#ifdef CAM_OS_RTK ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#else ++#include ++#include ++#include ++#include ++#endif ++ ++ ++//============================================================================= ++ ++#define CAMDRVPOLL_EVENTGROUP_MAX 100 ++ ++#ifndef TRUE ++#define TRUE 1 ++#define FALSE 0 ++#endif ++ ++#ifdef CAM_OS_RTK ++typedef struct ++{ ++ u8 bUsed; ++ u32 nEventGroup; // event ++ Ms_Flag_t tWait; ++ Ms_Mutex_t tMutexEvent; ++ u32 nWaitflag; //reserved ++} CamDrvPollEventInfo_t; ++ ++static Ms_Mutex_t _camPollEventGroup_Mutex; ++#define EVENTABLE_MUTEX_LOCK() MsMutexLock(&_camPollEventGroup_Mutex) ++#define EVENTABLE_MUTEX_UNLOCK() MsMutexUnlock(&_camPollEventGroup_Mutex) ++ ++#define EVENTLOCK_INIT MsInitMutex ++#define EVENTLOCK_LOCK MsMutexLock ++#define EVENTLOCK_UNLOCK MsMutexUnlock ++#define WAKEFLAG_INIT MsFlagInit ++#define WAKEFLAG_DEINIT(x) MsFlagDestroy(x) ++#define WAKEFLAG_WAKEUP(x,y) MsFlagSetbits(x,y) ++#else ++typedef struct ++{ ++ u8 bUsed; ++ u32 nEventGroup; // event ++ wait_queue_head_t tWait; ++ spinlock_t tMutexEvent; ++ ++} CamDrvPollEventInfo_t; ++ ++static DEFINE_SPINLOCK(_camPollEventGroup_Mutex); ++#define EVENTABLE_MUTEX_LOCK() spin_lock(&_camPollEventGroup_Mutex) ++#define EVENTABLE_MUTEX_UNLOCK() spin_unlock(&_camPollEventGroup_Mutex) ++ ++#define EVENTLOCK_INIT spin_lock_init ++#define EVENTLOCK_LOCK spin_lock ++#define EVENTLOCK_UNLOCK spin_unlock ++#define WAKEFLAG_INIT init_waitqueue_head ++#define WAKEFLAG_DEINIT(x) ++#define WAKEFLAG_WAKEUP(x,y) wake_up_interruptible(x) ++#endif ++ ++CamDrvPollEventInfo_t _camPollEventGroup_Info[CAMDRVPOLL_EVENTGROUP_MAX]; ++ ++ ++#define LOCK_EVENT(i) EVENTLOCK_LOCK(&_camPollEventGroup_Info[i].tMutexEvent) ++#define UNLOCK_EVENT(i) EVENTLOCK_UNLOCK(&_camPollEventGroup_Info[i].tMutexEvent) ++#define WAKE_UP(i,bits) WAKEFLAG_WAKEUP(&_camPollEventGroup_Info[i].tWait, bits) ++ ++ ++#define _CamDrvPollGetEvent(nEventID) (_camPollEventGroup_Info[nEventID].nEventGroup) ++ ++#define _CamDrvPollCheckEventExist(nEventID) if ( (nEventID >= CAMDRVPOLL_EVENTGROUP_MAX) || \ ++ !_camPollEventGroup_Info[nEventID].bUsed ) \ ++ { return -1; } ++ ++ ++//============================================================================= ++s32 CamDrvPollRegEventGrp(void) ++{ ++ int i; ++ ++ //alloc an entry in the event table ++ EVENTABLE_MUTEX_LOCK(); ++ for (i = 0; i < CAMDRVPOLL_EVENTGROUP_MAX; i++) ++ { ++ if (!_camPollEventGroup_Info[i].bUsed) ++ { ++ _camPollEventGroup_Info[i].bUsed = TRUE; ++ _camPollEventGroup_Info[i].nEventGroup= 0; ++ break; ++ } ++ } ++ EVENTABLE_MUTEX_UNLOCK(); ++ ++ if (i == CAMDRVPOLL_EVENTGROUP_MAX) ++ { ++ return -1; ++ } ++ ++ EVENTLOCK_INIT(&_camPollEventGroup_Info[i].tMutexEvent); ++ WAKEFLAG_INIT(&_camPollEventGroup_Info[i].tWait); ++ ++ return i; ++} ++ ++ ++void CamDrvPollDeRegEventGrp(u32 nEventID) ++{ ++ EVENTABLE_MUTEX_LOCK(); ++ WAKEFLAG_DEINIT(&_camPollEventGroup_Info[nEventID].tWait); ++ _camPollEventGroup_Info[nEventID].bUsed = FALSE; ++ EVENTABLE_MUTEX_UNLOCK(); ++} ++ ++ ++void CamDrvPollSetEvent(u32 nEventID, u32 nEventBits) ++{ ++ //set event bits in the corresponding event entry ++ LOCK_EVENT(nEventID); ++ _camPollEventGroup_Info[nEventID].nEventGroup |= nEventBits; ++ UNLOCK_EVENT(nEventID); ++ ++ WAKE_UP(nEventID, nEventBits); ++} ++ ++s32 _CamDrvPollGetAndClearEvent(u32 nEventID, u32 nWaitBits) ++{ ++ u32 eventBits; ++ ++ LOCK_EVENT(nEventID); ++ eventBits = _camPollEventGroup_Info[nEventID].nEventGroup & nWaitBits; ++ if (eventBits != 0) ++ { ++ _camPollEventGroup_Info[nEventID].nEventGroup &= ~eventBits; ++ } ++ UNLOCK_EVENT(nEventID); ++ ++ return eventBits; ++} ++ ++ ++#ifdef CAM_OS_RTK ++s32 _CamDrvPollWaitEvent(u32 nEventID, u32 nWaitBits, s32 nTimeout) ++{ ++ Ms_flag_value_t tFlagBit; ++ s32 eventBits = 0; ++ ++ if (0 > nTimeout) /* TIME_INFINITY */ ++ { ++ do { ++ MsFlagWait(&_camPollEventGroup_Info[nEventID].tWait, ++ (Ms_flag_value_t)nWaitBits, ++ MS_FLAG_WAITMODE_OR|MS_FLAG_WAITMODE_CLR); ++ eventBits = _CamDrvPollGetAndClearEvent(nEventID, nWaitBits); ++ } while (0 == eventBits); ++ } ++ else ++ { ++ do { ++ tFlagBit = MsFlagTimedWait(&_camPollEventGroup_Info[nEventID].tWait, ++ (Ms_flag_value_t)nWaitBits, ++ MS_FLAG_WAITMODE_OR|MS_FLAG_WAITMODE_CLR, ++ RTK_MS_TO_TICK(nTimeout)); ++ if (tFlagBit == 0) /* timeout */ ++ { ++ break; ++ } ++ eventBits = _CamDrvPollGetAndClearEvent(nEventID, nWaitBits); ++ } while (0 == eventBits); ++ } ++ ++ return eventBits; ++} ++#endif ++ ++s32 CamDrvPollEvent(u32 nEventID, u32 nWaitBits, struct file *filp, poll_table *tPoll) ++{ ++ u32 eventBits; ++ ++#ifdef CAM_OS_RTK ++ u32 nTimeout = filp->nPollTimeout; ++ ++ _CamDrvPollCheckEventExist(nEventID); ++ ++ eventBits = _CamDrvPollGetAndClearEvent(nEventID, nWaitBits); ++ if (0 >= eventBits) ++ { ++ eventBits = _CamDrvPollWaitEvent(nEventID, nWaitBits, nTimeout); ++ } ++#else ++ ++ _CamDrvPollCheckEventExist(nEventID); ++ ++ poll_wait(filp, &_camPollEventGroup_Info[nEventID].tWait, tPoll); ++ ++ eventBits = _CamDrvPollGetAndClearEvent(nEventID, nWaitBits); ++#endif ++ ++ return eventBits; ++} ++ ++#ifndef CAM_OS_RTK ++EXPORT_SYMBOL(CamDrvPollRegEventGrp); ++EXPORT_SYMBOL(CamDrvPollDeRegEventGrp); ++EXPORT_SYMBOL(CamDrvPollSetEvent); ++EXPORT_SYMBOL(CamDrvPollEvent); ++#endif +diff --git a/drivers/sstar/cam_fs_wrapper/HISTORY b/drivers/sstar/cam_fs_wrapper/HISTORY +new file mode 100755 +index 000000000000..d657ec86bb97 +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/HISTORY +@@ -0,0 +1,31 @@ ++=============================================================================== ++= cam_fs_wrapper change log = ++=============================================================================== ++ ++v0.0.6 - 2020-02-18 ++ Changed ++ - uboot env type access (path start with "/env/") no longer supported. ++ ++v0.0.5 - 2019-10-31 ++ Added ++ - Support linux user space. ++ ++v0.0.4 - 2019-09-02 ++ Added ++ - Support CamFsSeek API. ++ ++v0.0.3 - 2019-05-03 ++ Fixed ++ - CamFsRead for RTK read NAND flash by block number. ++ ++v0.0.2 - 2019-04-26 ++ Fixed ++ - Handle file position in CamFsRead / CamFsWrite. ++ ++v0.0.1 - 2019-04-26 ++ First version support linux kernel space and RTK. ++ Added ++ - CamFsOpen ++ - CamFsClose ++ - CamFsRead ++ - CamFsWrite +diff --git a/drivers/sstar/cam_fs_wrapper/Makefile b/drivers/sstar/cam_fs_wrapper/Makefile +new file mode 100755 +index 000000000000..4b6bfa492b27 +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for SStar cam_os_wrapper driver. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/cam_fs_wrapper ++EXTRA_CFLAGS += -Idrivers/sstar/cam_fs_wrapper/pub ++ ++ ++# specific options ++ ++# files ++obj-y += src/cam_fs_wrapper.o src/cam_fs_export.o ++ ++# export header files ++EXPORT_H_FILES += cam_fs_wrapper.h +diff --git a/drivers/sstar/cam_fs_wrapper/Makefile_lib b/drivers/sstar/cam_fs_wrapper/Makefile_lib +new file mode 100755 +index 000000000000..d2075a67598e +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/Makefile_lib +@@ -0,0 +1,71 @@ ++CROSS_COMPILE ?=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++AR = $(CROSS_COMPILE)ar ++STRIP = $(CROSS_COMPILE)strip ++BUILD_DIR := .build ++LIB_NAME=cam_fs_wrapper ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++LINUX_KERNEL_PATH ?= $(PWD)/../../../ ++KL_API_INCLUDE ?= $(LINUX_KERNEL_PATH)/drivers/sstar/include ++ ++CFLAGS := -Wall -Werror -O2 -ffunction-sections -funwind-tables -fstack-protector ++CFLAGS += -fPIC -DPIC ++ ++CFLAGS += -DCAM_OS_LINUX_USER ++ ++#CFLAGS += -D__USE_GNU ++LDFLAGS += -O2 -Bdirect -Wl,--hash-style=gnu ++LIBS := -ldl -lpthread ++ ++CORE_LIB_C_SRCS := \ ++ ./src/cam_fs_wrapper.c ++ ++CINCLUDES := \ ++ -I$(KL_API_INCLUDE) \ ++ -I./pub \ ++ -I./inc ++ ++LIB_HEADERS := \ ++ ./pub/cam_fs_wrapper.h ++ ++CORE_LIB_C_OBJS := $(patsubst %.c, %.c.o, $(CORE_LIB_C_SRCS)) ++ ++.PHONY: clean prepare lib$(LIB_NAME) ++ ++all: prepare lib$(LIB_NAME) ++ ++prepare: ++ @echo ++ @echo ">>>>========================================================" ++ @echo ++ @echo " LIB_NAME = ${LIB_NAME}" ++ @echo " PWD = $(shell pwd)" ++ @echo " CC = $(CC)" ++ @echo " BRANCH_ID = $(BRANCH_ID)" ++ @echo ++ @mkdir -p $(BUILD_DIR) ++ @echo " Copying headers to '$(BUILD_DIR)/include'..." ++ @echo ++ @mkdir -p $(BUILD_DIR)/include ++ @cp -f $(LIB_HEADERS) $(BUILD_DIR)/include ++ ++clean: ++ @rm -Rf $(CORE_LIB_C_OBJS) ++ @rm -Rf $(BUILD_DIR) ++ ++lib$(LIB_NAME): prepare $(CORE_LIB_C_OBJS) ++ @mkdir -p $(BUILD_DIR)/lib ++ @echo " LD $(BUILD_DIR)/lib/$@.so" ++ @$(CC) -shared $(LDFLAGS) -o $(BUILD_DIR)/lib/$@.so $(CORE_LIB_C_OBJS) ${LIBS} ++ @echo " AR $(BUILD_DIR)/lib/$@.a" ++ @$(AR) -crs $(BUILD_DIR)/lib/$@.a $(CORE_LIB_C_OBJS) ++ @echo ++ @echo "<<<<========================================================" ++ @echo ++ ++%.c.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ +diff --git a/drivers/sstar/cam_fs_wrapper/cam_fs_wrapper.mak b/drivers/sstar/cam_fs_wrapper/cam_fs_wrapper.mak +new file mode 100644 +index 000000000000..cc899c2f75db +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/cam_fs_wrapper.mak +@@ -0,0 +1,19 @@ ++ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_cam_fs_wrapper)/src ++ ++PATH_H +=\ ++ $(PATH_cam_fs_wrapper)/pub\ ++ $(PATH_spinand)/inc\ ++ $(PATH_spinand_hal)/inc ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ cam_fs_wrapper.c +diff --git a/drivers/sstar/cam_fs_wrapper/pub/cam_fs_wrapper.h b/drivers/sstar/cam_fs_wrapper/pub/cam_fs_wrapper.h +new file mode 100755 +index 000000000000..ee071393044a +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/pub/cam_fs_wrapper.h +@@ -0,0 +1,187 @@ ++/* ++* cam_fs_wrapper.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_fs_wrapper.h ++/// @brief Cam FS Wrapper Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_FS_WRAPPER_H__ ++#define __CAM_FS_WRAPPER_H__ ++ ++#define CAM_FS_WRAPPER_VERSION "v0.0.6" ++ ++#include "cam_os_wrapper.h" ++ ++#ifndef O_CLOEXEC ++#define O_CLOEXEC 02000000 ++#endif ++#ifndef O_NOATIME ++#define O_NOATIME 01000000 ++#endif ++#ifndef O_NOFOLLOW ++#define O_NOFOLLOW 00400000 ++#endif ++#ifndef O_DIRECTORY ++#define O_DIRECTORY 00200000 ++#endif ++#ifndef O_LARGEFILE ++#define O_LARGEFILE 00100000 ++#endif ++#ifndef O_DIRECT ++#define O_DIRECT 00040000 ++#endif ++#ifndef FASYNC ++#define FASYNC 00020000 ++#endif ++#ifndef O_DSYNC ++#define O_DSYNC 00010000 ++#endif ++#ifndef O_NONBLOCK ++#define O_NONBLOCK 00004000 ++#endif ++#ifndef O_APPEND ++#define O_APPEND 00002000 ++#endif ++#ifndef O_TRUNC ++#define O_TRUNC 00001000 ++#endif ++#ifndef O_NOCTTY ++#define O_NOCTTY 00000400 ++#endif ++#ifndef O_EXCL ++#define O_EXCL 00000200 ++#endif ++#ifndef O_CREAT ++#define O_CREAT 00000100 ++#endif ++#ifndef O_PATH ++#define O_PATH 010000000 ++#endif ++#ifndef O_RDWR ++#define O_RDWR 00000002 ++#endif ++#ifndef O_WRONLY ++#define O_WRONLY 00000001 ++#endif ++#ifndef O_RDONLY ++#define O_RDONLY 00000000 ++#endif ++#ifndef O_ACCMODE ++#define O_ACCMODE 00000003 ++#endif ++#ifndef O_SYNC ++#define __O_SYNC 04000000 ++#define O_SYNC (__O_SYNC|O_DSYNC) ++#endif ++ ++#ifndef SEEK_SET ++#define SEEK_SET 0 ++#endif ++#ifndef SEEK_CUR ++#define SEEK_CUR 1 ++#endif ++#ifndef SEEK_END ++#define SEEK_END 2 ++#endif ++ ++typedef enum ++{ ++ CAM_FS_OK = 0, ++ CAM_FS_FAIL = -1, ++} CamFsRet_e; ++ ++typedef void * CamFsFd; ++ ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] ptFd: Pointer to file descriptor. ++// [in] szPath: Point to a pathname naming the file. ++// [in] nFlag: File status flags. ++// [in] nMode: File access modes. ++// Return: ++// CAM_FS_OK on success. On error, CAM_FS_FAIL is returned. ++//============================================================================= ++CamFsRet_e CamFsOpen(CamFsFd *ptFd, const char *szPath, u32 nFlag, u32 nMode); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] tFd: File descriptor. ++// Return: ++// CAM_FS_OK on success. On error, CAM_FS_FAIL is returned. ++//============================================================================= ++CamFsRet_e CamFsClose(CamFsFd tFd); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] tFd: File descriptor. ++// [in] pBuf: Pointer to the buffer start address. ++// [in] nByte: Read up to nCount bytes from file descriptor nFd. ++// Return: ++// On success, the number of bytes read is returned. On error, -1 is returned. ++//============================================================================= ++s32 CamFsRead(CamFsFd tFd, void *pBuf, u32 nCount); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] tFd: File descriptor. ++// [in] pBuf: Pointer to the buffer start address. ++// [in] nByte: Write up to nCount bytes to the file referred to by the file ++// descriptor nFd. ++// Return: ++// On success, the number of bytes written is returned (zero indicates nothing ++// was written). On error, -1 is returned. ++//============================================================================= ++s32 CamFsWrite(CamFsFd tFd, const void *pBuf, u32 nCount); ++ ++//============================================================================= ++// Description: ++// Reposition read/write file offset ++// Parameters: ++// [in] tFd: File descriptor. ++// [in] nOffset: Number of bytes to offset from nWhence. ++// [in] nWhence: Position used as reference for the offset. ++// --------------------------------------------------- ++// | Constant | Reference position | ++// --------------------------------------------------- ++// | SEEK_SET | Beginning of file | ++// --------------------------------------------------- ++// | SEEK_CUR | Current position of the file pointer | ++// --------------------------------------------------- ++// | SEEK_END | End of file | ++// --------------------------------------------------- ++// Return: ++// On success, returns the resulting offset location as measured in bytes ++// from the beginning of the file. On error, -1 is returned. ++//============================================================================= ++s32 CamFsSeek(CamFsFd tFd, u32 nOffset, u32 nWhence); ++ ++#endif /* __CAM_FS_WRAPPER_H__ */ +diff --git a/drivers/sstar/cam_fs_wrapper/src/cam_fs_export.c b/drivers/sstar/cam_fs_wrapper/src/cam_fs_export.c +new file mode 100755 +index 000000000000..cf97d8bba658 +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/src/cam_fs_export.c +@@ -0,0 +1,33 @@ ++/* ++* cam_fs_export.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_fs_export.c ++/// @brief Cam FS Export Symbol Source File for Linux Kernel Space ++/// Only Include This File in Linux Kernel ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include "cam_fs_wrapper.h" ++ ++EXPORT_SYMBOL(CamFsOpen); ++EXPORT_SYMBOL(CamFsClose); ++EXPORT_SYMBOL(CamFsRead); ++EXPORT_SYMBOL(CamFsWrite); ++EXPORT_SYMBOL(CamFsSeek); +diff --git a/drivers/sstar/cam_fs_wrapper/src/cam_fs_wrapper.c b/drivers/sstar/cam_fs_wrapper/src/cam_fs_wrapper.c +new file mode 100644 +index 000000000000..566999084b09 +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/src/cam_fs_wrapper.c +@@ -0,0 +1,412 @@ ++/* ++* cam_fs_wrapper.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_fs_wrapper.c ++/// @brief Cam FS Wrapper Source File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#ifdef CAM_OS_RTK ++#include "stdio.h" ++#include "sys_sys.h" ++#include "drv_spinand.h" ++#include "sys_MsWrapper_cus_os_mem.h" ++#include "cam_os_wrapper.h" ++#include "cam_fs_wrapper.h" ++ ++#define FD_TYPE_BLOCK 1 ++#define FD_TYPE_LWFS 2 ++ ++typedef struct ++{ ++ union { ++ u32 nFdType:8; // FD_TYPE_BLOCK or FD_TYPE_LWFS ++ struct { ++ u32 nFdType:8; ++ u32 nBlkNo:24; ++ } tBlkType; ++ struct { ++ u32 nFdType:8; ++ u32 nPartNo:8; ++ u32 nPartOffset:16; ++ } tPartType; ++ }; ++ u32 nSize; ++} CamFsFdRtk_t, *pCamFsFdRtk_t; ++ ++#elif defined(CAM_OS_LINUX_USER) ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_fs_wrapper.h" ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_fs_wrapper.h" ++#endif ++ ++#define FLASH_ACCESS_UNIT 131072 ++ ++typedef struct ++{ ++ u32 magic; ++ u32 ver; ++ u32 size; ++ u32 align_unit; ++ u32 file_num; ++ u8 dummy[44]; ++} LwFsPartitionInfo_t; ++ ++typedef struct ++{ ++ char name[32]; ++ u32 offset; ++ u32 length; ++ u32 padding; ++ u32 crc32; ++ u32 compressed; ++ u8 dummy[12]; ++} LwFsFileInfo_t; ++ ++#define LWFS_MNT_PATH "/mnt/" ++#define LWFS_HEADER_FIRST_READ 2048 ++ ++CamFsRet_e CamFsOpen(CamFsFd *ptFd, const char *szPath, u32 nFlag, u32 nMode) ++{ ++#ifdef CAM_OS_RTK ++ /* ++ There is no file system in RTK now, CamFs will access spinand device ++ directly. CamFsOpen will use PBA number instead file descriptor. ++ */ ++ CamFsFdRtk_t *ptFdRtk; ++ char *pEnd = NULL; ++ void *flash_buf = NULL; ++ char partition_name[64] = {0}; ++ char file_name[64] = {0}; ++ u32 i = 0;; ++ LwFsPartitionInfo_t *p_info; ++ LwFsFileInfo_t *f_info; ++ u32 lwfs_header_size = 0; ++ u32 nPartNo; ++ CamFsRet_e eRet = CAM_FS_FAIL; ++ ++ if (strncmp(szPath,"/blk/",5) == 0) ++ { ++ ptFdRtk = (CamFsFdRtk_t *)CamOsMemCalloc(1, sizeof(CamFsFdRtk_t)); ++ ptFdRtk->nFdType = FD_TYPE_BLOCK; ++ ptFdRtk->tBlkType.nBlkNo = strtoul(szPath + 5, &pEnd, 10); ++ ptFdRtk->nSize = 0; ++ *ptFd = (CamFsFd *)ptFdRtk; ++ eRet = CAM_FS_OK; ++ } ++ else if (strncmp(szPath, LWFS_MNT_PATH, strlen(LWFS_MNT_PATH)) == 0) ++ { ++ i = 0; ++ while(*((szPath+strlen(LWFS_MNT_PATH))+i) != '/' && *((szPath+strlen(LWFS_MNT_PATH))+i) != 0) ++ { ++ i++; ++ } ++ if (!i || *((szPath+strlen(LWFS_MNT_PATH))+i) == 0) ++ { ++ return CAM_FS_FAIL; ++ } ++ strncpy(partition_name, szPath+strlen(LWFS_MNT_PATH), CAM_OS_MIN(sizeof(partition_name)-1, i)); ++ partition_name[sizeof(partition_name)-1] = '\0'; ++ strncpy(file_name, szPath+strlen(LWFS_MNT_PATH)+i+1, sizeof(file_name)-1); ++ file_name[sizeof(file_name)-1] = '\0'; ++ ++ // Allocate 64 byte aligned buffer for cache flush operation ++ flash_buf = MsGetHeapMemoryExt(LWFS_HEADER_FIRST_READ, 6, 0); ++ if (!flash_buf) ++ { ++ CamOsPrintf("%s: alloc buf fail\n", __FUNCTION__); ++ eRet = CAM_FS_FAIL; ++ goto cam_fs_open_lwfs_end; ++ } ++ ++ DrvSpinandProbe(); ++ nPartNo = DrvSpinand_FindPartTypeByName(partition_name); ++ MDrv_SPINAND_LoadBL((u8 *)flash_buf, LWFS_HEADER_FIRST_READ, nPartNo, 0); ++ CamOsMemInvalidate(flash_buf, LWFS_HEADER_FIRST_READ); ++ ++ p_info = flash_buf; ++ f_info = flash_buf + sizeof(LwFsPartitionInfo_t); ++ ++ if (p_info->magic != 0x5346574C) ++ { ++ CamOsPrintf("%s: %s not in LWFS format\n", __FUNCTION__, partition_name); ++ eRet = CAM_FS_FAIL; ++ goto cam_fs_open_lwfs_end; ++ } ++ ++ lwfs_header_size = p_info->size; ++ ++ if (lwfs_header_size > LWFS_HEADER_FIRST_READ) ++ { ++ /* If LWFS header size greater than LWFS_HEADER_FIRST_READ, ++ realloc and reload header. */ ++ MsReleaseHeapMemory(flash_buf); ++ flash_buf = NULL; ++ ++ // Allocate 64 byte aligned buffer for cache flush operation ++ flash_buf = MsGetHeapMemoryExt(lwfs_header_size, 6, 0); ++ if (!flash_buf) ++ { ++ CamOsPrintf("%s: alloc buf fail\n", __FUNCTION__); ++ eRet = CAM_FS_FAIL; ++ goto cam_fs_open_lwfs_end; ++ } ++ ++ DrvSpinandProbe(); ++ nPartNo = DrvSpinand_FindPartTypeByName(partition_name); ++ MDrv_SPINAND_LoadBL((u8 *)flash_buf, lwfs_header_size, nPartNo, 0); ++ CamOsMemInvalidate(flash_buf, lwfs_header_size); ++ ++ p_info = flash_buf; ++ f_info = flash_buf + sizeof(LwFsPartitionInfo_t); ++ } ++ ++ for (i=0; ifile_num; i++) ++ { ++ if (strncmp(f_info[i].name, file_name, sizeof(f_info[i].name)) == 0) ++ break; ++ } ++ ++ if (i == p_info->file_num) ++ { ++ eRet = CAM_FS_FAIL; ++ goto cam_fs_open_lwfs_end; ++ } ++ ++ ptFdRtk = (CamFsFdRtk_t *)CamOsMemCalloc(1, sizeof(CamFsFdRtk_t)); ++ if (!ptFdRtk) ++ { ++ CamOsPrintf("%s: alloc buf fail\n", __FUNCTION__); ++ eRet = CAM_FS_FAIL; ++ goto cam_fs_open_lwfs_end; ++ } ++ ptFdRtk->nFdType = FD_TYPE_LWFS; ++ ptFdRtk->tPartType.nPartNo = nPartNo; ++ ptFdRtk->tPartType.nPartOffset = f_info[i].offset/FLASH_ACCESS_UNIT; ++ ptFdRtk->nSize = f_info[i].length; ++ *ptFd = (CamFsFd *)ptFdRtk; ++ eRet = CAM_FS_OK; ++ ++cam_fs_open_lwfs_end: ++ if (flash_buf) ++ { ++ MsReleaseHeapMemory(flash_buf); ++ flash_buf = NULL; ++ } ++ } ++ ++ return eRet; ++#elif defined(CAM_OS_LINUX_USER) ++ if ((*ptFd = (CamFsFd *)open(szPath, nFlag, nMode)) >= 0) ++ return CAM_FS_OK; ++ else ++ return CAM_FS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct file *ptFp = NULL; ++ mm_segment_t tFs; ++ ++ tFs = get_fs(); ++ set_fs(get_ds()); ++ ptFp = filp_open(szPath, nFlag, nMode); ++ set_fs(tFs); ++ ++ if(IS_ERR(ptFp)) ++ { ++ *ptFd = NULL; ++ return CAM_FS_FAIL; ++ } ++ else ++ { ++ *ptFd = (CamFsFd)ptFp; ++ return CAM_FS_OK; ++ } ++#endif ++} ++ ++CamFsRet_e CamFsClose(CamFsFd tFd) ++{ ++#ifdef CAM_OS_RTK ++ if (tFd) ++ { ++ CamOsMemRelease(tFd); ++ return CAM_FS_OK; ++ } ++ else ++ { ++ return CAM_FS_FAIL; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if (!close((int)tFd)) ++ return CAM_FS_OK; ++ else ++ return CAM_FS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct file *ptFp = (struct file *)tFd; ++ ++ if (ptFp) ++ { ++ return (!filp_close(ptFp, NULL))? CAM_FS_OK : CAM_FS_FAIL; ++ } ++ else ++ { ++ return CAM_FS_FAIL; ++ } ++#endif ++} ++ ++s32 CamFsRead(CamFsFd tFd, void *pBuf, u32 nCount) ++{ ++#ifdef CAM_OS_RTK ++ CamFsFdRtk_t *ptFdRtk = (CamFsFdRtk_t *)tFd; ++ ++ DrvSpinandProbe(); ++ ++ if (ptFdRtk == NULL) ++ { ++ return 0; ++ } ++ ++ if (ptFdRtk->nFdType == FD_TYPE_BLOCK) ++ { ++ //DrvSpinand_ReadBlockPba((u8 *)pBuf, ptFdRtk->tBlkType.nBlkNo, nCount); ++ } ++ else if (ptFdRtk->nFdType == FD_TYPE_LWFS) ++ { ++ MDrv_SPINAND_LoadBL((u8 *)pBuf, nCount, ptFdRtk->tPartType.nPartNo, ptFdRtk->tPartType.nPartOffset); ++ } ++ else ++ { ++ return 0; ++ } ++ ++ return nCount; ++#elif defined(CAM_OS_LINUX_USER) ++ return read((int)tFd, pBuf, nCount); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct file *ptFp = (struct file *)tFd; ++ mm_segment_t tFs; ++ loff_t tPos; ++ s32 nRet; ++ ++ if (ptFp) ++ { ++ tFs = get_fs(); ++ set_fs(get_ds()); ++ tPos = ptFp->f_pos; ++ nRet = vfs_read(ptFp, pBuf, nCount, &tPos); ++ ptFp->f_pos = tPos; ++ set_fs(tFs); ++ return nRet; ++ } ++ else ++ { ++ return -1; ++ } ++#endif ++} ++ ++s32 CamFsWrite(CamFsFd tFd, const void *pBuf, u32 nCount) ++{ ++#ifdef CAM_OS_RTK ++ return 0; ++#elif defined(CAM_OS_LINUX_USER) ++ return write((int)tFd, pBuf, nCount); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct file *ptFp = (struct file *)tFd; ++ mm_segment_t tFs; ++ loff_t tPos; ++ s32 nRet; ++ ++ if (ptFp) ++ { ++ tFs = get_fs(); ++ set_fs(get_ds()); ++ tPos = ptFp->f_pos; ++ nRet = vfs_write(ptFp, pBuf, nCount, &tPos); ++ ptFp->f_pos = tPos; ++ set_fs(tFs); ++ return nRet; ++ } ++ else ++ { ++ return -1; ++ } ++#endif ++} ++ ++s32 CamFsSeek(CamFsFd tFd, u32 nOffset, u32 nWhence) ++{ ++#ifdef CAM_OS_RTK ++ CamFsFdRtk_t *ptFdRtk = (CamFsFdRtk_t *)tFd; ++ s32 nRet = 0; ++ ++ if (tFd) ++ { ++ switch (nWhence) ++ { ++ case SEEK_SET: ++ nRet = 0; // Do nothing ++ break; ++ case SEEK_CUR: ++ nRet = 0; // Do nothing ++ break; ++ case SEEK_END: ++ nRet = ptFdRtk->nSize; ++ break; ++ default: ++ nRet = 0; ++ break; ++ } ++ } ++ else ++ { ++ nRet = -1; ++ } ++ ++ return nRet; ++#elif defined(CAM_OS_LINUX_USER) ++ return lseek((int)tFd, nOffset, nWhence); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct file *ptFp = (struct file *)tFd; ++ return vfs_llseek(ptFp, nOffset, nWhence); ++#endif ++} +diff --git a/drivers/sstar/cam_fs_wrapper/test/Makefile b/drivers/sstar/cam_fs_wrapper/test/Makefile +new file mode 100755 +index 000000000000..1cd539f8bca8 +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/test/Makefile +@@ -0,0 +1,20 @@ ++obj-m := cam_fs_test.o ++cam_fs_test-objs := ../src/cam_fs_wrapper.o cam_fs_linux_kernel_test.o ++ ++export ARCH=arm ++export CROSS_COMPILE=arm-linux-gnueabihf- ++ ++KERNEL = $(PWD)/../../../../ ++CC = $(CROSS_COMPILE)gcc ++APP = cam_fs_linux_user_test ++EXTRA_CFLAGS := -I$(KERNEL)/drivers/sstar/include/ -I$(KERNEL)/include/ ++USER_CFLAGS := -Wall -Werror -g -O2 -ffunction-sections -funwind-tables -fstack-protector -I../pub/ -I$(KERNEL)/drivers/sstar/include/ ++USER_LDFLAGS := -L$(PWD)/../.build/lib -lcam_fs_wrapper ++ ++all: ++ make modules -C $(KERNEL) M=`pwd` ++ $(CC) $(USER_CFLAGS) $(USER_LDFLAGS) $(APP).c -o $(APP) ++ ++clean: ++ make modules clean -C $(KERNEL) M=`pwd` ++ rm -rf $(APP) +diff --git a/drivers/sstar/cam_fs_wrapper/test/cam_fs_linux_kernel_test.c b/drivers/sstar/cam_fs_wrapper/test/cam_fs_linux_kernel_test.c +new file mode 100755 +index 000000000000..6f78295cf245 +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/test/cam_fs_linux_kernel_test.c +@@ -0,0 +1,71 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_fs_linux_kernel_test.c ++/// @brief Cam FS Wrapper Test Code for Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_fs_wrapper.h" ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("SStar CamFS Linux Kernel Test"); ++MODULE_LICENSE("GPL"); ++ ++static char *filename = ""; ++module_param(filename, charp, 0660); ++ ++static int __init KernelTestInit(void) ++{ ++ CamFsFd tFD; ++ void *pBuf = NULL; ++ u32 nReadRet = 0; ++ s32 filelen; ++ ++ CamOsPrintf("Test CamFs Start\n"); ++ ++ if (CAM_FS_OK != CamFsOpen(&tFD, filename, O_RDONLY, 0)) ++ { ++ CamOsPrintf("Open %s FAIL\n", filename); ++ } ++ else ++ { ++ CamOsPrintf("Open %s SUCCESS\n", filename); ++ ++ filelen = CamFsSeek(tFD, 0, SEEK_END); ++ CamOsPrintf("file len: %d\n", filelen); ++ CamFsSeek(tFD, 0, SEEK_SET); ++ pBuf = CamOsMemAlloc(filelen); ++ nReadRet = CamFsRead(tFD, pBuf, filelen); ++ CamOsHexdump(pBuf, filelen); ++ CamOsMemRelease(pBuf); ++ ++ CamFsClose(tFD); ++ } ++ ++ CamOsPrintf("Test CamFs End\n"); ++ return 0; ++} ++ ++static void __exit KernelTestExit(void) ++{ ++ CamOsPrintf(KERN_INFO "Goodbye\n"); ++} ++ ++module_init(KernelTestInit); ++module_exit(KernelTestExit); +diff --git a/drivers/sstar/cam_fs_wrapper/test/cam_fs_linux_user_test.c b/drivers/sstar/cam_fs_wrapper/test/cam_fs_linux_user_test.c +new file mode 100755 +index 000000000000..4565b5d26dff +--- /dev/null ++++ b/drivers/sstar/cam_fs_wrapper/test/cam_fs_linux_user_test.c +@@ -0,0 +1,62 @@ ++/* ++* cam_os_wrapper_test.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int main(int argc, char *args[]) ++{ ++ char buff[1024]; ++ CamFsFd fd1, fd2; ++ int i; ++ int baksize = sizeof(args[1]) + 7; ++ char bakfile[baksize]; ++ ++ if (argc != 2) ++ { ++ printf("Input one file a time!\n"); ++ exit(1); ++ } ++ ++ strcpy(bakfile, args[1]); ++ strcat(bakfile, ".backup"); ++ ++ if (CamFsOpen(&fd1, args[1], O_RDONLY, 0644) != CAM_FS_OK) ++ { ++ printf("Open Error!Check if the file is exist and you have the permission!\n"); ++ exit(1); ++ } ++ if (CamFsOpen(&fd2, bakfile, O_RDWR | O_CREAT | O_TRUNC, 755) != CAM_FS_OK) ++ { ++ printf("Open Error!Check if the file is exist and you have the permission!\n"); ++ exit(1); ++ } ++ ++ while ((i = CamFsRead(fd1, buff, sizeof(buff))) > 0) ++ { ++ CamFsWrite(fd2, buff, i); ++ } ++ CamFsClose(fd1); ++ CamFsClose(fd2); ++ printf("Backup done!\n"); ++ exit(0); ++} +diff --git a/drivers/sstar/cam_os_wrapper/HISTORY b/drivers/sstar/cam_os_wrapper/HISTORY +new file mode 100755 +index 000000000000..97dbae1e07a7 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/HISTORY +@@ -0,0 +1,268 @@ ++=============================================================================== ++= cam_os_wrapper change log = ++=============================================================================== ++ ++v1.0.35 - 2020-06-24 ++ Add ++ - Support CamOsMemAllocAtomic / CamOsMemCallocAtomic / CamOsMemReallocAtomic / ++ CamOsMemCacheAllocAtomic for memory allocate without sleep. ++ ++v1.0.27 - 2020-03-23 ++ Add ++ - Support CamOsTimerDeleteSync for SMP Linux. ++ ++v1.0.26 - 2020-03-12 ++ Add ++ - Support CamOsMemFlushExt for inner and outer cache flush. ++ Changed ++ - Refine CamOsMemFlush. ++ ++v1.0.25 - 2020-01-10 ++ Changed ++ - Change CamOsMsSleep/CamOsUsSleep implement. ++ In Linux, CamOsMsSleep for larger msecs sleep(10ms+), ++ adn CamOsUsSleep for ~usecs or small msecs sleep(10us~20ms). ++ ++v1.0.24 - 2019-12-27 ++ Added ++ - Support CamOsDramInfo and CamOsChipRevision. ++ ++v1.0.23 - 2019-12-11 ++ Added ++ - Support CamOsMemoryBarrier. ++ ++v1.0.22 - 2019-12-09 ++ Added ++ - Support CamOsIdrInitEx for create IDR with maximum entry number. ++ ++v1.0.21 - 2019-08-09 ++ Added ++ - Support CamOsThreadChangePriority. ++ ++v1.0.20 - 2019-08-02 ++ Changed ++ - cam_os_util_list.h enable CAM_OS_HLIST_EMPTY again, it will cause ABICC ++ check g++ build fail. ++ ++v1.0.19 - 2019-08-01 ++ Changed ++ - Change parameter order of following atomic function for alignment API style ++ CamOsAtomicAddReturn ++ CamOsAtomicSubReturn ++ CamOsAtomicSubAndTest ++ CamOsAtomicAddNegative ++ ++v1.0.18 - 2019-08-01 ++ Added ++ - CamOsAtomicAndFetch / CamOsAtomicFetchAnd for AND operation. ++ - CamOsAtomicNandFetch / CamOsAtomicFetchNand for NAND operation. ++ - CamOsAtomicOrFetch / CamOsAtomicFetchOr for OR operation. ++ - CamOsAtomicXorFetch / CamOsAtomicFetchXor for XOR operation. ++ ++v1.0.17 - 2019-05-16 ++ Enhanced ++ - CamOsGetTimeOfDay and CamOsSetTimeOfDay support nanosecond field in RTK. ++ ++v1.0.16 - 2019-05-10 ++ Fixed ++ - cam_os_util_list.h cause ABICC check g++ build fail. ++ ++v1.0.15 - 2019-05-06 ++ Added ++ - Add CamOsMemInvalidate for invalidate data in cache. ++ ++v1.0.14 - 2019-04-10 ++ Fixed ++ - CamOsSetTimeOfDay, _TestCamOsSystemTime ++ Fix coverity issue - "Memory - illegal accesses". ++ ++v1.0.13 - 2019-03-05 ++ Added ++ - CamOsIrq### ++ Support interrupt handler setup and control. ++ ++v1.0.12 - 2019-02-01 ++ Fixed ++ - CamOsMutex_t and other CamOs### strust may cause alignment exception issue ++ in Linux. ++ ++v1.0.11 - 2019-01-24 ++ Changed ++ - CamOsGetMonotonicTime sourcing from arch in RTK. ++ - Update Software Copyright. ++ ++v1.0.10 - 2019-01-16 ++ Added ++ - CamOsMiuPipeFlush ++ Flush MIU write buffer. ++ Changed ++ - CamOsSpinLockIrq and CamOsSpinUnlockIrq are no longer supported. ++ ++v1.0.9 - 2018-12-27 ++ Added ++ - CamOsPrintString ++ Writes the C string pointed without format to the standard output. ++ Fixed ++ - CamOsPrintf ++ Fix system crash if print more than 256 characters in RTK. ++ ++v1.0.8 - 2018-12-20 ++ Added ++ - In kernel space, redirect atoi and qsort to linux kernel's implement. ++ Fixed ++ - In RTK and user space, CamOsAtomicIncReturn AND CamOsAtomicDecReturn will ++ return the value that before add or sub. ++ ++v1.0.7 - 2018-12-11 ++ Added ++ - CamOsMsDelay / CamOsUsDelay ++ - CamOsSpin### ++ Support spinlock synchronization. ++ Fixed ++ - Replace __always_inline with FORCE_INLINE to avoid warnings in RTK. ++ ++v1.0.6 - 2018-09-13 ++ Added ++ - CamOsHexdump ++ Print memory data in hex format. ++ - CamOsUsSleep ++ Suspend execution for microsecond intervals. ++ - CamOsTimeDiff ++ Returns the difference between two CamOsTimespec_t. ++ - CamOsMemFlush ++ Clean and invalidate cache. ++ - CamOsAtomicCompareAndSwap ++ An atomic instruction used in multithreading to achieve synchronization. ++ It compares the contents of a memory location with a given value and, only ++ if they are the same, modifies the contents of that memory location to a ++ new given value. ++ Changed ++ - CamOsThreadAttrb_t ++ Add szName field and support set name while thread created. ++ - CamOsTsemDownInterruptible ++ Change prototype define, it will return CamOsRet_e now. ++ - CamOsTcondWaitInterruptible ++ Change prototype define, it will return CamOsRet_e now. ++ ++v1.0.5 - 2017-12-18 ++ Added ++ - CAM_OS_MAX_INT ++ - Makefile_Linux_user ++ Add Makefile for shared library build(make -f Makefile_Linux_user). ++ Changed ++ - CamOsTsemInit ++ In RTK, use MsCreateDynSemExtend to set nVal to current value, and set ++ init value to (CAM_OS_MAX_INT - 1). Because MsCreateDynSem sets nVal to ++ current value and init value and current value is larger than init value ++ will trigger exception. ++ - CAM_OS_MAX_TIMEOUT ++ Use u32 max value as CAM_OS_MAX_TIMEOUT ++ ++v1.0.4 - 2017-12-06 ++ Changed ++ - Move offsetof definition to cam_os_util.h and add definition without ++ size_t to avoid compile error if stddef.h not be included. ++ Fixed ++ - In RTK, if timer has stopped, CamOsTimerModify start a new timer and ++ don't release the old timer. ++ ++v1.0.3 - 2017-11-30 ++ Changed ++ - Integrate all header files into cam_os_wrapper.h. All functions could be ++ used just include cam_os_wrapper.h. ++ - CamOsTcond### ++ Replace wait queue with completion for Linux kernel to simplify control ++ flow. ++ ++v1.0.2 - 2017-11-24 ++ Added ++ - CAM_OS_LIST_LAST_ENTRY ++ Support "list last entry" in cam_os_util_list.h ++ - NO_MDRV_MSYS ++ Support disable relative functions for msys ++ (add -DNO_MDRV_MSYS in Makefile) ++ Changed ++ - CamOsMemAlloc / CamOsMemCalloc ++ Use kzalloc when requested size <= 2KB(half of page size), and use vzalloc ++ when requested size > 2KB to improve memory usage ++ Fixed ++ - CamOsThreadSchedule / CamOsThreadWakeUp ++ Fix schedule and wakeup function in RTK ++ - CamOsRwsem### ++ Fix read write semaphore function in RTK ++ - CamOsTimer### ++ Fix timer function in RTK ++ ++v1.0.1 - 2017-11-20 ++ Added ++ - CamOsTsemDownInterruptible ++ Add prototype define in cam_os_wrapper.h ++ - CamOsListSort ++ Add symbol to cam_os_export.c ++ Changed ++ - Support CamOsPhyMemMap/CamOsPhyMemUnMap in Linux user space ++ - Mutex can be used without initialization. It will be inited automatically. ++ - Support CamOsThreadStop/CamOsThreadShouldStop in RTK ++ - uint8_t/int8_t/uint16_t/int16_t/uint32_t/int32_t/uint64_t ++ /int64_t. Use u8/s8/u16/s16/u32/s32/u64/s64 to keep portability ++ - Remove bool(replace with u8) to keep portability ++ ++v1.0.0 - 2017-11-03 ++ Added ++ - CamOsThreadSchedule/CamOsThreadWakeUp ++ Control thread to idle and wake up. ++ - CamOsMutexTryLock ++ Try lock the mutex, and return as non-blocking mode. ++ - CamOsRwsem### ++ Support read-write semaphore operation. ++ - CamOsPhyMemMap/CamOsPhyMemUnMap ++ Map and unmap physical memory to virtual address. ++ - CamOsMemCache### ++ Create a memory cache(memory pool) and allocate with specified size to ++ ignore internal fragmentation. ++ - CamOsTimer### ++ Support timer operation. ++ - CamOsIdr### ++ Support data record with IDR data structure. In Linux user space and RTK, ++ it is implemented with informal IDR(bitmap and array). ++ - CamOsInInterrupt ++ Check if current function runs in ISR. ++ - CamOsSmpMemoryBarrier ++ Symmetric multiprocessing memory barrier. ++ - CamOsStrError ++ Return string describing error number. ++ - CamOsPanic ++ Put system into panic. ++ - CamOsStrtol/CamOsStrtoul/CamOsStrtoull ++ Convert C string to long, unsigned long, unsigned long long. ++ - cam_os_util_bug.h ++ Support error handle function: CAM_OS_BUG, CAM_OS_BUG_ON, ++ CAM_OS_IS_ERR_VALUE, ... ++ - cam_os_util_ioctl.h ++ Support ioctl number function: CAM_OS_IO, CAM_OS_IOW, ... ++ Changed ++ - Replace u8/s8/u16/s16/u32/s32/u64/s64 with uint8_t/int8_t/uint16_t/int16_t ++ uint32_t/int32_t/uint64_t/int64_t. ++ - CamOsThreadSetName/CamOsThreadGetName ++ Only support to access name by thread self in uclibc. ++ ++v0.1.2 - 2017-10-27 ++ Added ++ - CamOsTcond### ++ Condition wait functions, please reference to cam_os_wrapper.h. ++ - CAM_OS_HASH_### ++ Hash table operation functions, please reference to cam_os_hash.h. ++ - CAM_OS_BITMAP_### ++ Bitmap opration functions, please reference to cam_os_bitmap.h. ++ - CAM_OS_LIKELY, CAM_OS_UNLIKELY, and CAM_OS_ARRAY_SIZE ++ Changed ++ - Use native semaphore of operation system. Original functions comprise ++ one mutex and one counter(CamOsTsem###). ++ - Supplement list operation functions, please reference cam_os_list.h. ++ Removed ++ - Remove CamOsTsemGetValue and CamOsTsemReset because this two APIs do not ++ fit general semaphore usage. ++ ++v0.1.1 - 2017-10-23 ++ Added ++ - CamOsSnprintf +diff --git a/drivers/sstar/cam_os_wrapper/Makefile b/drivers/sstar/cam_os_wrapper/Makefile +new file mode 100755 +index 000000000000..f43f0149d9a9 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/Makefile +@@ -0,0 +1,19 @@ ++# ++# Makefile for SStar cam_os_wrapper driver. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/cam_os_wrapper ++EXTRA_CFLAGS += -Idrivers/sstar/cam_os_wrapper/pub ++EXTRA_CFLAGS += -Wno-sync-nand ++ ++# specific options ++ ++# files ++obj-y += src/cam_os_wrapper.o src/cam_os_export.o src/cam_os_informal_idr.o ++ ++# export header files ++EXPORT_H_FILES += cam_os_wrapper.h +diff --git a/drivers/sstar/cam_os_wrapper/Makefile_lib b/drivers/sstar/cam_os_wrapper/Makefile_lib +new file mode 100755 +index 000000000000..2d8b2d921600 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/Makefile_lib +@@ -0,0 +1,79 @@ ++CROSS_COMPILE ?=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++AR = $(CROSS_COMPILE)ar ++STRIP = $(CROSS_COMPILE)strip ++BUILD_DIR := .build ++LIB_NAME=cam_os_wrapper ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++LINUX_KERNEL_PATH ?= $(PWD)/../../../ ++KL_API_INCLUDE ?= $(LINUX_KERNEL_PATH)/drivers/sstar/include ++ ++CFLAGS := -Wall -Werror -Wno-sync-nand -O2 -ffunction-sections -funwind-tables -fstack-protector ++CFLAGS += -fPIC -DPIC ++ ++CFLAGS += -DCAM_OS_LINUX_USER ++ ++#CFLAGS += -D__USE_GNU ++LDFLAGS += -O2 -Bdirect -Wl,--hash-style=gnu ++LIBS := -ldl -lpthread ++ ++CORE_LIB_C_SRCS := \ ++ ./src/cam_os_wrapper.c \ ++ ./src/cam_os_informal_idr.c ++ ++CINCLUDES := \ ++ -I$(KL_API_INCLUDE) \ ++ -I./pub \ ++ -I./inc ++ ++LIB_HEADERS := \ ++ ./pub/cam_os_wrapper.h \ ++ ./pub/cam_os_util.h \ ++ ./pub/cam_os_util_list.h \ ++ ./pub/cam_os_util_hash.h \ ++ ./pub/cam_os_util_bitmap.h \ ++ ./pub/cam_os_util_bug.h \ ++ ./pub/cam_os_util_ioctl.h \ ++ ./pub/cam_os_util_string.h ++ ++CORE_LIB_C_OBJS := $(patsubst %.c, %.c.o, $(CORE_LIB_C_SRCS)) ++ ++.PHONY: clean prepare lib$(LIB_NAME) ++ ++all: prepare lib$(LIB_NAME) ++ ++prepare: ++ @echo ++ @echo ">>>>========================================================" ++ @echo ++ @echo " LIB_NAME = ${LIB_NAME}" ++ @echo " PWD = $(shell pwd)" ++ @echo " CC = $(CC)" ++ @echo " BRANCH_ID = $(BRANCH_ID)" ++ @echo ++ @mkdir -p $(BUILD_DIR) ++ @echo " Copying headers to '$(BUILD_DIR)/include'..." ++ @echo ++ @mkdir -p $(BUILD_DIR)/include ++ @cp -f $(LIB_HEADERS) $(BUILD_DIR)/include ++ ++clean: ++ @rm -Rf $(CORE_LIB_C_OBJS) ++ @rm -Rf $(BUILD_DIR) ++ ++lib$(LIB_NAME): prepare $(CORE_LIB_C_OBJS) ++ @mkdir -p $(BUILD_DIR)/lib ++ @echo " LD $(BUILD_DIR)/lib/$@.so" ++ @$(CC) -shared $(LDFLAGS) -o $(BUILD_DIR)/lib/$@.so $(CORE_LIB_C_OBJS) ${LIBS} ++ @echo " AR $(BUILD_DIR)/lib/$@.a" ++ @$(AR) -crs $(BUILD_DIR)/lib/$@.a $(CORE_LIB_C_OBJS) ++ @echo ++ @echo "<<<<========================================================" ++ @echo ++ ++%.c.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ +diff --git a/drivers/sstar/cam_os_wrapper/cam_os_wrapper.mak b/drivers/sstar/cam_os_wrapper/cam_os_wrapper.mak +new file mode 100755 +index 000000000000..c6e9827a61bc +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/cam_os_wrapper.mak +@@ -0,0 +1,20 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_cam_os_wrapper)/src \ ++ $(PATH_cam_os_wrapper)/test ++ ++PATH_H +=\ ++ $(PATH_cam_os_wrapper)/pub \ ++ $(PATH_cam_os_wrapper)/inc ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ cam_os_wrapper.c \ ++ cam_os_informal_idr.c \ ++ cam_os_wrapper_test.c +\ No newline at end of file +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_condition.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_condition.h +new file mode 100755 +index 000000000000..605c99f57146 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_condition.h +@@ -0,0 +1,184 @@ ++/* ++* cam_os_condition.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_CONDITION_H__ ++#define __CAM_OS_CONDITION_H__ ++ ++#include "cam_os_wrapper.h" ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#if defined(CAM_OS_RTK) ++#include "sys_MsWrapper_cus_os_sem.h" ++typedef Ms_DynSemaphor_t CamOsCondition_t; ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include "linux/wait.h" ++typedef wait_queue_head_t CamOsCondition_t; ++#else // CAM_OS_LINUX_USER ++#include "pthread.h" ++typedef struct ++{ ++ pthread_mutex_t tMutex; ++ pthread_cond_t tCondition; ++} CamOsCondition_t; ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionInit(ptCondition) \ ++ MsCreateDynSem(ptCondition, 0); ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionInit(ptCondition) \ ++ init_waitqueue_head(ptCondition); ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionInit(ptCondition) \ ++({ \ ++ pthread_condattr_t cattr; \ ++ pthread_condattr_init(&cattr); \ ++ pthread_condattr_setclock(&cattr, CLOCK_MONOTONIC); \ ++ pthread_cond_init(ptCondition.tCondition, &cattr); \ ++ pthread_mutex_init(ptCondition.tMutex, NULL); \ ++}) ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionDeinit(ptCondition) \ ++ MsDestroyDynSem(ptCondition) ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionDeinit(ptCondition) ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionDeinit(ptCondition) \ ++({ \ ++ pthread_cond_destroy(ptCondition.tCondition); \ ++ pthread_mutex_destroy(ptCondition.tMutex); \ ++}) ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionWakeUpAll(ptCondition) \ ++ MsProduceSafeDynSem(ptCondition, 1); ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionWakeUpAll(ptCondition) \ ++ wake_up_all(ptCondition); ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionWakeUpAll(ptCondition) \ ++({ \ ++ pthread_mutex_lock(ptCondition.tMutex); \ ++ pthread_cond_broadcast(ptCondition.tCondition); \ ++ pthread_mutex_unlock(ptCondition.tMutex); \ ++}) ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionWait(ptCondition, condition) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ while (!(condition)) \ ++ MsConsumeDynSem(ptCondition); \ ++ __eRet; \ ++}) ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionWait(ptCondition, condition) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ wait_event((*(ptCondition)), condition); \ ++ __eRet; \ ++}) ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionWait(ptCondition, condition) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ pthread_mutex_lock(ptCondition.tMutex); \ ++ while (!(condition)) \ ++ pthread_cond_wait(ptCondition.tCondition, ptCondition.tMutex); \ ++ pthread_mutex_unlock(ptCondition.tMutex); \ ++ __eRet; \ ++}) ++#endif ++ ++#if defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionTimedWait(ptCondition, condition, nMsec) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ if (!wait_event_timeout((*(ptCondition)), condition, \ ++ msecs_to_jiffies(nMsec))) \ ++ { \ ++ __eRet = CAM_OS_TIMEOUT; \ ++ } \ ++ __eRet; \ ++}) ++#elif defined(CAM_OS_RTK) ++#define __CamOsConditionTimedWait(ptCondition, condition, timeout_ms) \ ++({ \ ++ unsigned long __ret = timeout_ms; \ ++ unsigned long long __target_time = CamOsGetTimeInMs() + timeout_ms; \ ++ while (!(condition)) \ ++ { \ ++ if (MS_NO_MESSAGE == MsConsumeDynSemDelay(ptCondition, __ret)) { \ ++ __ret = (condition); \ ++ break; \ ++ } \ ++ __ret = (unsigned long)(__target_time - CamOsGetTimeInMs()); \ ++ } \ ++ __ret; \ ++}) ++ ++#define CamOsConditionTimedWait(ptCondition, condition, nMsec) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ if(!__CamOsConditionTimedWait(ptCondition, condition, nMsec)) \ ++ { \ ++ __eRet = CAM_OS_TIMEOUT; \ ++ } \ ++ __eRet; \ ++}) ++#else // CAM_OS_LINUX_USER ++#define __CamOsConditionTimedWait(ptCondition, condition, timeout_ms) \ ++({ \ ++ int __ret = 1; \ ++ struct timespec max_wait; \ ++ s64 nano_sec = 0; \ ++ clock_gettime(CLOCK_MONOTONIC, &max_wait); \ ++ nano_sec = (timeout_ms * 1000000LL) + max_wait.tv_nsec; \ ++ max_wait.tv_sec += (nano_sec / 1000000000LL); \ ++ max_wait.tv_nsec = nano_sec % 1000000000LL; \ ++ pthread_mutex_lock(ptCondition.tMutex); \ ++ while (!(condition)) { \ ++ if (0 != pthread_cond_timedwait(ptCondition.tCondition, \ ++ ptCondition.tMutex, &max_wait)) { \ ++ __ret = (condition); \ ++ break; \ ++ } \ ++ } \ ++ pthread_mutex_unlock(ptCondition.tMutex); \ ++ __ret; \ ++}) ++ ++#define CamOsConditionTimedWait(ptCondition, condition, nMsec) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ if(!__CamOsConditionTimedWait(ptCondition, condition, nMsec)) \ ++ { \ ++ __eRet = CAM_OS_TIMEOUT; \ ++ } \ ++ __eRet; \ ++}) ++#endif ++ ++#endif //__CAM_OS_CONDITION_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util.h +new file mode 100644 +index 000000000000..42c46c665b7d +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util.h +@@ -0,0 +1,144 @@ ++/* ++* cam_os_util.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_H__ ++#define __CAM_OS_UTIL_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define FORCE_INLINE __attribute__((always_inline)) inline ++ ++#ifndef offsetof ++#ifdef __compiler_offsetof ++#define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) ++#else ++#ifdef size_t ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++#else ++#define offsetof(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) ++#endif ++#endif ++#endif ++ ++#define CAM_OS_CONTAINER_OF(ptr, type, member) ({ \ ++ void *__mptr = (void *)(ptr); \ ++ ((type *)(__mptr - offsetof(type, member))); }) ++ ++#ifndef likely ++#define CAM_OS_LIKELY(x) __builtin_expect(!!(x), 1) ++#else ++#define CAM_OS_LIKELY(x) likely(x) ++#endif ++ ++#ifndef unlikely ++#define CAM_OS_UNLIKELY(x) __builtin_expect(!!(x), 0) ++#else ++#define CAM_OS_UNLIKELY(x) unlikely(x) ++#endif ++ ++static FORCE_INLINE s32 CAM_OS_FLS(s32 x) ++{ ++ int r = 32; ++ ++ if (!x) ++ return 0; ++ if (!(x & 0xffff0000u)) { ++ x <<= 16; ++ r -= 16; ++ } ++ if (!(x & 0xff000000u)) { ++ x <<= 8; ++ r -= 8; ++ } ++ if (!(x & 0xf0000000u)) { ++ x <<= 4; ++ r -= 4; ++ } ++ if (!(x & 0xc0000000u)) { ++ x <<= 2; ++ r -= 2; ++ } ++ if (!(x & 0x80000000u)) { ++ x <<= 1; ++ r -= 1; ++ } ++ return r; ++} ++ ++#if CAM_OS_BITS_PER_LONG == 32 ++static FORCE_INLINE s32 CAM_OS_FLS64(u64 x) ++{ ++ u32 h = x >> 32; ++ if (h) ++ return CAM_OS_FLS(h) + 32; ++ return CAM_OS_FLS(x); ++} ++#elif CAM_OS_BITS_PER_LONG == 64 ++static FORCE_INLINE s32 _CAM_OS_FLS(u64 word) ++{ ++ s32 num = CAM_OS_BITS_PER_LONG - 1; ++ ++//#if CAM_OS_BITS_PER_LONG == 64 ++ if (!(word & (~0ul << 32))) { ++ num -= 32; ++ word <<= 32; ++ } ++//#endif ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-16)))) { ++ num -= 16; ++ word <<= 16; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-8)))) { ++ num -= 8; ++ word <<= 8; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-4)))) { ++ num -= 4; ++ word <<= 4; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-2)))) { ++ num -= 2; ++ word <<= 2; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-1)))) ++ num -= 1; ++ return num; ++} ++ ++static FORCE_INLINE s32 CAM_OS_FLS64(u64 x) ++{ ++ if (x == 0) ++ return 0; ++ return _CAM_OS_FLS(x) + 1; ++} ++#else ++#error CAM_OS_BITS_PER_LONG not 32 or 64 ++#endif ++ ++#define CAM_OS_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#define CAM_OS_MIN(a,b) (((a)<(b))?(a):(b)) ++#define CAM_OS_MAX(a,b) (((a)>(b))?(a):(b)) ++ ++#endif //__CAM_OS_UTIL_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util_bitmap.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_bitmap.h +new file mode 100644 +index 000000000000..9b9b1a181086 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_bitmap.h +@@ -0,0 +1,121 @@ ++/* ++* cam_os_util_bitmap.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_BITMAP_H__ ++#define __CAM_OS_UTIL_BITMAP_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define CAM_OS_BIT_MASK(nr) (1UL << ((nr) % CAM_OS_BITS_PER_LONG)) ++#define CAM_OS_BIT_WORD(nr) ((nr) / CAM_OS_BITS_PER_LONG) ++#define CAM_OS_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#define CAM_OS_BITS_TO_LONGS(nr) CAM_OS_DIV_ROUND_UP(nr, CAM_OS_BITS_PER_LONG) ++ ++#define CAM_OS_DECLARE_BITMAP(name,bits) \ ++ unsigned long name[CAM_OS_BITS_TO_LONGS(bits)] ++ ++#define CAM_OS_BITMAP_CLEAR(name) do { \ ++ memset((name), 0, sizeof(name)); \ ++} while (0) ++ ++unsigned long _CamOsFindFirstZeroBit(unsigned long *pAddr, unsigned long nSize, ++ unsigned long nOffset); ++#define CAM_OS_FIND_FIRST_ZERO_BIT(p,sz) _CamOsFindFirstZeroBit(p,sz,0) ++#define CAM_OS_FIND_NEXT_ZERO_BIT(p,sz,of) _CamOsFindFirstZeroBit(p,sz,of) ++ ++static inline int CAM_OS_FFS(unsigned long x) ++{ ++ return CAM_OS_FLS(x & -x); ++} ++ ++static inline unsigned long _CAM_OS_FFS(unsigned long x) ++{ ++ return CAM_OS_FFS(x) - 1; ++} ++ ++#define CAM_OS_FFZ(x) _CAM_OS_FFS( ~(x) ) ++ ++/* WARNING: bitmap operation is non atomic */ ++static inline void CAM_OS_SET_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ ++ *p |= mask; ++} ++ ++static inline void CAM_OS_CLEAR_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ ++ *p &= ~mask; ++} ++ ++static inline void CAM_OS_CHANGE_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ ++ *p ^= mask; ++} ++ ++static inline s32 CAM_OS_TEST_AND_SET_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ volatile unsigned long old = *p; ++ ++ *p = old | mask; ++ return (old & mask) != 0; ++} ++ ++static inline s32 CAM_OS_TEST_AND_CLEAR_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ volatile unsigned long old = *p; ++ ++ *p = old & ~mask; ++ return (old & mask) != 0; ++} ++ ++static inline s32 CAM_OS_TEST_AND_CHANGE_BIT(s32 nr, ++ volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ volatile unsigned long old = *p; ++ ++ *p = old ^ mask; ++ return (old & mask) != 0; ++} ++ ++static inline s32 CAM_OS_TEST_BIT(s32 nr, const volatile unsigned long *addr) ++{ ++ return 1UL & (addr[CAM_OS_BIT_WORD(nr)] >> (nr & (CAM_OS_BITS_PER_LONG-1))); ++} ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_BITMAP_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util_bug.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_bug.h +new file mode 100644 +index 000000000000..e537778b3684 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_bug.h +@@ -0,0 +1,47 @@ ++/* ++* cam_os_util_bug.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_BUG_H__ ++#define __CAM_OS_UTIL_BUG_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define CAM_OS_BUG() do { \ ++ CamOsPrintf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ ++ CamOsPanic("BUG!"); \ ++} while (0) ++ ++#define CAM_OS_BUG_ON(condition) do { if (unlikely(condition)) CAM_OS_BUG(); } while (0) ++ ++#define CAM_OS_MAX_ERRNO 4096 ++#define CAM_OS_IS_ERR_VALUE(x) CAM_OS_UNLIKELY((x) >= (unsigned long)-CAM_OS_MAX_ERRNO) ++ ++#define CAM_OS_ERR_PTR(x) (void *)(x) ++ ++#define CAM_OS_PTR_ERR(x) (long)(x) ++ ++#define CAM_OS_IS_ERR(x) CAM_OS_IS_ERR_VALUE((unsigned long)(x)) ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_BUG_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util_hash.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_hash.h +new file mode 100644 +index 000000000000..1359f6eb839d +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_hash.h +@@ -0,0 +1,98 @@ ++/* ++* cam_os_util_hash.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_HASH_H__ ++#define __CAM_OS_UTIL_HASH_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++static inline __attribute__((const)) ++s32 _CAM_OS_ILOG2_U32(u32 n) ++{ ++ return CAM_OS_FLS(n) - 1; ++} ++ ++static inline __attribute__((const)) ++s32 _CAM_OS_ILOG2_U64(u64 n) ++{ ++ return CAM_OS_FLS64(n) - 1; ++} ++ ++#define CAM_OS_ILOG2(n) \ ++( \ ++ __builtin_constant_p(n) ? ( \ ++ (n) < 1 ? 0 : \ ++ (n) & (1ULL << 63) ? 63 : (n) & (1ULL << 62) ? 62 : (n) & (1ULL << 61) ? 61 : (n) & (1ULL << 60) ? 60 : \ ++ (n) & (1ULL << 59) ? 59 : (n) & (1ULL << 58) ? 58 : (n) & (1ULL << 57) ? 57 : (n) & (1ULL << 56) ? 56 : \ ++ (n) & (1ULL << 55) ? 55 : (n) & (1ULL << 54) ? 54 : (n) & (1ULL << 53) ? 53 : (n) & (1ULL << 52) ? 52 : \ ++ (n) & (1ULL << 51) ? 51 : (n) & (1ULL << 50) ? 50 : (n) & (1ULL << 49) ? 49 : (n) & (1ULL << 48) ? 48 : \ ++ (n) & (1ULL << 47) ? 47 : (n) & (1ULL << 46) ? 46 : (n) & (1ULL << 45) ? 45 : (n) & (1ULL << 44) ? 44 : \ ++ (n) & (1ULL << 43) ? 43 : (n) & (1ULL << 42) ? 42 : (n) & (1ULL << 41) ? 41 : (n) & (1ULL << 40) ? 40 : \ ++ (n) & (1ULL << 39) ? 39 : (n) & (1ULL << 38) ? 38 : (n) & (1ULL << 37) ? 37 : (n) & (1ULL << 36) ? 36 : \ ++ (n) & (1ULL << 35) ? 35 : (n) & (1ULL << 34) ? 34 : (n) & (1ULL << 33) ? 33 : (n) & (1ULL << 32) ? 32 : \ ++ (n) & (1ULL << 31) ? 31 : (n) & (1ULL << 30) ? 30 : (n) & (1ULL << 29) ? 29 : (n) & (1ULL << 28) ? 28 : \ ++ (n) & (1ULL << 27) ? 27 : (n) & (1ULL << 26) ? 26 : (n) & (1ULL << 25) ? 25 : (n) & (1ULL << 24) ? 24 : \ ++ (n) & (1ULL << 23) ? 23 : (n) & (1ULL << 22) ? 22 : (n) & (1ULL << 21) ? 21 : (n) & (1ULL << 20) ? 20 : \ ++ (n) & (1ULL << 19) ? 19 : (n) & (1ULL << 18) ? 18 : (n) & (1ULL << 17) ? 17 : (n) & (1ULL << 16) ? 16 : \ ++ (n) & (1ULL << 15) ? 15 : (n) & (1ULL << 14) ? 14 : (n) & (1ULL << 13) ? 13 : (n) & (1ULL << 12) ? 12 : \ ++ (n) & (1ULL << 11) ? 11 : (n) & (1ULL << 10) ? 10 : (n) & (1ULL << 9) ? 9 : (n) & (1ULL << 8) ? 8 : \ ++ (n) & (1ULL << 7) ? 7 : (n) & (1ULL << 6) ? 6 : (n) & (1ULL << 5) ? 5 : (n) & (1ULL << 4) ? 4 : \ ++ (n) & (1ULL << 3) ? 3 : (n) & (1ULL << 2) ? 2 : (n) & (1ULL << 1) ? 1 : (n) & (1ULL << 0) ? 0 : \ ++ 0) : \ ++ (sizeof(n) <= 4) ? \ ++ _CAM_OS_ILOG2_U32(n) : \ ++ _CAM_OS_ILOG2_U64(n) \ ++ ) ++ ++#define CAM_OS_HASH_SIZE(name) (CAM_OS_ARRAY_SIZE(name)) ++ ++#define CAM_OS_HASH_BITS(name) CAM_OS_ILOG2(CAM_OS_HASH_SIZE(name)) ++ ++#define CAM_OS_DEFINE_HASHTABLE(name, bits) \ ++ struct CamOsHListHead_t name[1 << (bits)] = \ ++ { [0 ... ((1 << (bits)) - 1)] = CAM_OS_HLIST_HEAD_INIT } ++ ++static inline void _CAM_OS_HASH_INIT(struct CamOsHListHead_t *ht, unsigned int sz) ++{ ++ u32 i; ++ ++ for (i = 0; i < sz; i++) ++ CAM_OS_INIT_HLIST_HEAD(&ht[i]); ++} ++ ++#define CAM_OS_HASH_INIT(hashtable) _CAM_OS_HASH_INIT(hashtable, CAM_OS_HASH_SIZE(hashtable)) ++ ++#define CAM_OS_HASH_ADD(hashtable, node, key) \ ++ CAM_OS_HLIST_ADD_HEAD(node, &hashtable[CAM_OS_HASH_MIN(key, CAM_OS_HASH_BITS(hashtable))]) ++ ++#define CAM_OS_HASH_FOR_EACH_POSSIBLE(name, obj, member, key) \ ++ CAM_OS_HLIST_FOR_EACH_ENTRY(obj, &name[CAM_OS_HASH_MIN(key, CAM_OS_HASH_BITS(name))], member) ++ ++static inline void CAM_OS_HASH_DEL(struct CamOsHListNode_t *node) ++{ ++ CAM_OS_HLIST_DEL_INIT(node); ++} ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_HASH_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util_ioctl.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_ioctl.h +new file mode 100644 +index 000000000000..8eebabdcaeec +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_ioctl.h +@@ -0,0 +1,83 @@ ++/* ++* cam_os_util_ioctl.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_IOCTL_H__ ++#define __CAM_OS_UTIL_IOCTL_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define CAM_OS_IOC_NRBITS 8 ++#define CAM_OS_IOC_TYPEBITS 8 ++ ++#define CAM_OS_IOC_SIZEBITS 14 ++ ++#define CAM_OS_IOC_DIRBITS 2 ++ ++#define CAM_OS_IOC_NRMASK ((1 << CAM_OS_IOC_NRBITS)-1) ++#define CAM_OS_IOC_TYPEMASK ((1 << CAM_OS_IOC_TYPEBITS)-1) ++#define CAM_OS_IOC_SIZEMASK ((1 << CAM_OS_IOC_SIZEBITS)-1) ++#define CAM_OS_IOC_DIRMASK ((1 << CAM_OS_IOC_DIRBITS)-1) ++ ++#define CAM_OS_IOC_NRSHIFT 0 ++#define CAM_OS_IOC_TYPESHIFT (CAM_OS_IOC_NRSHIFT+CAM_OS_IOC_NRBITS) ++#define CAM_OS_IOC_SIZESHIFT (CAM_OS_IOC_TYPESHIFT+CAM_OS_IOC_TYPEBITS) ++#define CAM_OS_IOC_DIRSHIFT (CAM_OS_IOC_SIZESHIFT+CAM_OS_IOC_SIZEBITS) ++ ++#define CAM_OS_IOC_NONE 0U ++#define CAM_OS_IOC_WRITE 1U ++#define CAM_OS_IOC_READ 2U ++ ++#define CAM_OS_IOC(dir,type,nr,size) \ ++ (((dir) << CAM_OS_IOC_DIRSHIFT) | \ ++ ((type) << CAM_OS_IOC_TYPESHIFT) | \ ++ ((nr) << CAM_OS_IOC_NRSHIFT) | \ ++ ((size) << CAM_OS_IOC_SIZESHIFT)) ++ ++#define CAM_OS_IOC_TYPECHECK(t) (sizeof(t)) ++ ++/* used to create numbers */ ++#define CAM_OS_IO(type,nr) CAM_OS_IOC(CAM_OS_IOC_NONE,(type),(nr),0) ++#define CAM_OS_IOR(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ,(type),(nr),(CAM_OS_IOC_TYPECHECK(size))) ++#define CAM_OS_IOW(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_WRITE,(type),(nr),(CAM_OS_IOC_TYPECHECK(size))) ++#define CAM_OS_IOWR(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ|CAM_OS_IOC_WRITE,(type),(nr),(CAM_OS_IOC_TYPECHECK(size))) ++#define CAM_OS_IOR_BAD(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ,(type),(nr),sizeof(size)) ++#define CAM_OS_IOW_BAD(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_WRITE,(type),(nr),sizeof(size)) ++#define CAM_OS_IOWR_BAD(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ|CAM_OS_IOC_WRITE,(type),(nr),sizeof(size)) ++ ++/* used to decode ioctl numbers.. */ ++#define CAM_OS_IOC_DIR(nr) (((nr) >> CAM_OS_IOC_DIRSHIFT) & CAM_OS_IOC_DIRMASK) ++#define CAM_OS_IOC_TYPE(nr) (((nr) >> CAM_OS_IOC_TYPESHIFT) & CAM_OS_IOC_TYPEMASK) ++#define CAM_OS_IOC_NR(nr) (((nr) >> CAM_OS_IOC_NRSHIFT) & CAM_OS_IOC_NRMASK) ++#define CAM_OS_IOC_SIZE(nr) (((nr) >> CAM_OS_IOC_SIZESHIFT) & CAM_OS_IOC_SIZEMASK) ++ ++/* ...and for the drivers/sound files... */ ++ ++#define CAM_OS_IOC_IN (CAM_OS_IOC_WRITE << CAM_OS_IOC_DIRSHIFT) ++#define CAM_OS_IOC_OUT (CAM_OS_IOC_READ << CAM_OS_IOC_DIRSHIFT) ++#define CAM_OS_IOC_INOUT ((CAM_OS_IOC_WRITE|CAM_OS_IOC_READ) << CAM_OS_IOC_DIRSHIFT) ++#define CAM_OS_IOCSIZE_MASK (CAM_OS_IOC_SIZEMASK << CAM_OS_IOC_SIZESHIFT) ++#define CAM_OS_IOCSIZE_SHIFT (CAM_OS_IOC_SIZESHIFT) ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_IOCTL_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util_list.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_list.h +new file mode 100755 +index 000000000000..e8f8eb234b9a +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_list.h +@@ -0,0 +1,308 @@ ++/* ++* cam_os_util_list.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_LIST_H__ ++#define __CAM_OS_UTIL_LIST_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++// List API ++struct CamOsListHead_t ++{ ++ struct CamOsListHead_t *pNext, *pPrev; ++}; ++ ++ ++#define CAM_OS_POISON_POINTER_DELTA 0 ++#define CAM_OS_LIST_POISON1 (void *)(0x00100100 + CAM_OS_POISON_POINTER_DELTA) ++#define CAM_OS_LIST_POISON2 (void *)(0x00200200 + CAM_OS_POISON_POINTER_DELTA) ++ ++#define CAM_OS_LIST_HEAD_INIT(name) { &(name), &(name) } ++ ++#define CAM_OS_LIST_HEAD(name) \ ++ struct CamOsListHead_t name = CAM_OS_LIST_HEAD_INIT(name) ++ ++#define CAM_OS_LIST_ENTRY(ptr, type, member) \ ++ CAM_OS_CONTAINER_OF(ptr, type, member) ++ ++#define CAM_OS_LIST_FOR_EACH(pos, head) \ ++ for (pos = (head)->pNext; pos != (head); pos = pos->pNext) ++ ++#define CAM_OS_LIST_FOR_EACH_SAFE(pos, n, head) \ ++ for (pos = (head)->pNext, n = pos->pNext; pos != (head); \ ++ pos = n, n = pos->pNext) ++ ++#define CAM_OS_LIST_FIRST_ENTRY(ptr, type, member) \ ++ CAM_OS_LIST_ENTRY((ptr)->pNext, type, member) ++ ++#define CAM_OS_LIST_LAST_ENTRY(ptr, type, member) \ ++ CAM_OS_LIST_ENTRY((ptr)->pPrev, type, member) ++ ++#define CAM_OS_LIST_NEXT_ENTRY(pos, member) \ ++ CAM_OS_LIST_ENTRY((pos)->member.pNext, __typeof__(*(pos)), member) ++ ++#define CAM_OS_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member) \ ++ for (pos = CAM_OS_LIST_FIRST_ENTRY(head, __typeof__(*pos), member), \ ++ n = CAM_OS_LIST_NEXT_ENTRY(pos, member); \ ++ &pos->member != (head); \ ++ pos = n, n = CAM_OS_LIST_NEXT_ENTRY(n, member)) ++ ++#define CAM_OS_LIST_FOR_EACH_ENTRY(pos, head, member) \ ++ for (pos = CAM_OS_LIST_FIRST_ENTRY(head, __typeof__(*pos), member); \ ++ &pos->member != (head); \ ++ pos = CAM_OS_LIST_NEXT_ENTRY(pos, member)) ++ ++ ++ static inline void CAM_OS_INIT_LIST_HEAD(struct CamOsListHead_t *pList) ++ { ++ pList->pNext = pList; ++ pList->pPrev = pList; ++ } ++ ++ static inline void _CAM_OS_LIST_ADD(struct CamOsListHead_t *pNew, ++ struct CamOsListHead_t *pPrev, ++ struct CamOsListHead_t *pNext) ++ { ++ pNext->pPrev = pNew; ++ pNew->pNext = pNext; ++ pNew->pPrev = pPrev; ++ pPrev->pNext = pNew; ++ } ++ ++ static inline void CAM_OS_LIST_ADD(struct CamOsListHead_t *pNew, struct CamOsListHead_t *head) ++ { ++ _CAM_OS_LIST_ADD(pNew, head, head->pNext); ++ } ++ ++ ++ static inline void CAM_OS_LIST_ADD_TAIL(struct CamOsListHead_t *pNew, struct CamOsListHead_t *head) ++ { ++ _CAM_OS_LIST_ADD(pNew, head->pPrev, head); ++ } ++ ++ static inline void _CAM_OS_LIST_DEL(struct CamOsListHead_t * pPrev, struct CamOsListHead_t * pNext) ++ { ++ pNext->pPrev = pPrev; ++ pPrev->pNext = pNext; ++ } ++ ++ static inline void _CAM_OS_LIST_DEL_ENTRY(struct CamOsListHead_t *entry) ++ { ++ _CAM_OS_LIST_DEL(entry->pPrev, entry->pNext); ++ } ++ ++ ++ static inline void CAM_OS_LIST_DEL(struct CamOsListHead_t *pEntry) ++ { ++ _CAM_OS_LIST_DEL(pEntry->pPrev, pEntry->pNext); ++ pEntry->pNext = (struct CamOsListHead_t *)CAM_OS_LIST_POISON1; ++ pEntry->pPrev = (struct CamOsListHead_t *)CAM_OS_LIST_POISON2; ++ } ++ ++ static inline void CAM_OS_LIST_DEL_INIT(struct CamOsListHead_t *entry) ++ { ++ _CAM_OS_LIST_DEL_ENTRY(entry); ++ CAM_OS_INIT_LIST_HEAD(entry); ++ } ++ ++ static inline int CAM_OS_LIST_IS_LAST(const struct CamOsListHead_t *list, ++ const struct CamOsListHead_t *head) ++ { ++ return list->pNext == head; ++ } ++ ++ static inline int CAM_OS_LIST_EMPTY(const struct CamOsListHead_t *head) ++ { ++ return head->pNext == head; ++ } ++ ++ static inline int CAM_OS_LIST_EMPTY_CAREFUL(const struct CamOsListHead_t *head) ++ { ++ struct CamOsListHead_t *pNext = head->pNext; ++ return (pNext == head) && (pNext == head->pPrev); ++ } ++ ++ ++void CamOsListSort(void *priv, struct CamOsListHead_t *head, ++ int (*cmp)(void *priv, struct CamOsListHead_t *a, ++ struct CamOsListHead_t *b)); ++ ++#pragma GCC diagnostic push ++#pragma GCC diagnostic ignored "-Wcast-qual" ++// HList API ++static FORCE_INLINE ++void _CAM_OS_READ_ONCE_SIZE(const volatile void *p, void *res, int size) ++{ ++ switch (size) { ++ case 1: *(u8 *)res = *(volatile u8 *)p; break; ++ case 2: *(u16 *)res = *(volatile u16 *)p; break; ++ case 4: *(u32 *)res = *(volatile u32 *)p; break; ++ case 8: *(u64 *)res = *(volatile u64 *)p; break; ++ default: ++ asm volatile("": : :"memory"); // barrier() ++ __builtin_memcpy((void *)res, (const void *)p, size); ++ asm volatile("": : :"memory"); // barrier() ++ } ++} ++#pragma GCC diagnostic pop ++ ++#define CAM_OS_READ_ONCE(x) \ ++({ \ ++ union { __typeof__(x) __val; char __c[1]; } __u = {0}; \ ++ _CAM_OS_READ_ONCE_SIZE(&(x), __u.__c, sizeof(x)); \ ++ __u.__val; \ ++}) ++ ++#pragma GCC diagnostic push ++#pragma GCC diagnostic ignored "-Wcast-qual" ++static FORCE_INLINE void _CAM_OS_WRITE_ONCE_SIZE(volatile void *p, void *res, int size) ++{ ++ switch (size) { ++ case 1: *(volatile u8 *)p = *(u8 *)res; break; ++ case 2: *(volatile u16 *)p = *(u16 *)res; break; ++ case 4: *(volatile u32 *)p = *(u32 *)res; break; ++ case 8: *(volatile u64 *)p = *(u64 *)res; break; ++ default: ++ asm volatile("": : :"memory"); // barrier() ++ __builtin_memcpy((void *)p, (const void *)res, size); ++ asm volatile("": : :"memory"); // barrier() ++ } ++} ++#pragma GCC diagnostic pop ++ ++#define CAM_OS_WRITE_ONCE(x, val) \ ++({ \ ++ union { struct CamOsHListNode_t * __val; char __c[1]; } __u = \ ++ { .__val = (struct CamOsHListNode_t *) (val) }; \ ++ _CAM_OS_WRITE_ONCE_SIZE(&(x), __u.__c, sizeof(x)); \ ++ __u.__val; \ ++}) ++ ++/* 2^31 + 2^29 - 2^25 + 2^22 - 2^19 - 2^16 + 1 */ ++#define CAM_OS_GOLDEN_RATIO_PRIME_32 0x9e370001UL ++/* 2^63 + 2^61 - 2^57 + 2^54 - 2^51 - 2^18 + 1 */ ++#define CAM_OS_GOLDEN_RATIO_PRIME_64 0x9e37fffffffc0001UL ++ ++#if CAM_OS_BITS_PER_LONG == 32 ++static inline u32 CAM_OS_HASH_32(u32 val, u32 bits) ++{ ++ /* On some cpus multiply is faster, on others gcc will do shifts */ ++ u32 hash = val * CAM_OS_GOLDEN_RATIO_PRIME_32; ++ ++ /* High bits are more random, so use them. */ ++ return hash >> (32 - bits); ++} ++ ++#define CAM_OS_GOLDEN_RATIO_PRIME CAM_OS_GOLDEN_RATIO_PRIME_32 ++#define CAM_OS_HASH_LONG(val, bits) CAM_OS_HASH_32(val, bits) ++#elif CAM_OS_BITS_PER_LONG == 64 ++static FORCE_INLINE uint64_t CAM_OS_HASH_64(u64 val, u32 bits) ++{ ++ u64 hash = val; ++ ++ hash = hash * CAM_OS_GOLDEN_RATIO_PRIME_64; ++ ++ /* High bits are more random, so use them. */ ++ return hash >> (64 - bits); ++} ++ ++#define CAM_OS_HASH_LONG(val, bits) CAM_OS_HASH_64(val, bits) ++#define CAM_OS_GOLDEN_RATIO_PRIME CAM_OS_GOLDEN_RATIO_PRIME_64 ++#else ++#error CAM_OS_BITS_PER_LONG not 32 or 64 ++#endif ++ ++struct CamOsHListHead_t { ++ struct CamOsHListNode_t *pFirst; ++}; ++ ++struct CamOsHListNode_t { ++ struct CamOsHListNode_t *pNext, **ppPrev; ++}; ++ ++#define CAM_OS_HLIST_HEAD_INIT { .pFirst = NULL } ++#define CAM_OS_HLIST_HEAD(name) struct CamOsHListHead_t name = { .pFirst = NULL } ++#define CAM_OS_INIT_HLIST_HEAD(ptr) ((ptr)->pFirst = NULL) ++ ++#define CAM_OS_HASH_MIN(val, bits) \ ++ (sizeof(val) <= 4 ? CAM_OS_HASH_32(val, bits) : CAM_OS_HASH_LONG(val, bits)) ++ ++static inline void CAM_OS_INIT_HLIST_NODE(struct CamOsHListNode_t *h) ++{ ++ h->pNext = NULL; ++ h->ppPrev = NULL; ++} ++ ++static inline int CAM_OS_HLIST_UNHASHED(const struct CamOsHListNode_t *h) ++{ ++ return !h->ppPrev; ++} ++ ++static inline int CAM_OS_HLIST_EMPTY(const struct CamOsHListHead_t *h) ++{ ++ return !CAM_OS_READ_ONCE(h->pFirst); ++} ++ ++static inline void _CAM_OS_HLIST_DEL(struct CamOsHListNode_t *n) ++{ ++ struct CamOsHListNode_t *pNext = n->pNext; ++ struct CamOsHListNode_t **ppPrev = n->ppPrev; ++ ++ CAM_OS_WRITE_ONCE(*ppPrev, pNext); ++ if (pNext) ++ pNext->ppPrev = ppPrev; ++} ++ ++static inline void CAM_OS_HLIST_DEL_INIT(struct CamOsHListNode_t *n) ++{ ++ if (!CAM_OS_HLIST_UNHASHED(n)) { ++ _CAM_OS_HLIST_DEL(n); ++ CAM_OS_INIT_HLIST_NODE(n); ++ } ++} ++ ++static inline void CAM_OS_HLIST_ADD_HEAD(struct CamOsHListNode_t *n, struct CamOsHListHead_t *h) ++{ ++ struct CamOsHListNode_t *pFirst = h->pFirst; ++ n->pNext = pFirst; ++ if (pFirst) ++ pFirst->ppPrev = &n->pNext; ++ h->pFirst = n; ++ n->ppPrev = &h->pFirst; ++} ++ ++#define CAM_OS_HLIST_ENTRY(ptr, type, member) CAM_OS_CONTAINER_OF(ptr,type,member) ++ ++#define CAM_OS_HLIST_ENTRY_SAFE(ptr, type, member) \ ++ ({ __typeof__(ptr) ____ptr = (ptr); \ ++ ____ptr ? CAM_OS_HLIST_ENTRY(____ptr, type, member) : NULL; \ ++ }) ++ ++#define CAM_OS_HLIST_FOR_EACH_ENTRY(pos, head, member) \ ++ for (pos = CAM_OS_HLIST_ENTRY_SAFE((head)->pFirst, __typeof__(*(pos)), member);\ ++ pos; \ ++ pos = CAM_OS_HLIST_ENTRY_SAFE((pos)->member.pNext, __typeof__(*(pos)), member)) ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_LIST_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_util_string.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_string.h +new file mode 100755 +index 000000000000..3e1b3883c435 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_util_string.h +@@ -0,0 +1,82 @@ ++/* ++* cam_os_util_string.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_STRING_H__ ++#define __CAM_OS_UTIL_STRING_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#if defined(__KERNEL__) ++#include "linux/kernel.h" ++#include "linux/string.h" ++#include "linux/sort.h" ++#else ++#include "string.h" ++#include "stdlib.h" ++#include "stdio.h" ++#endif ++ ++#if defined(__KERNEL__) ++#define atoi(s) simple_strtol(s, NULL, 10) ++#define qsort(b,n,s,c) sort(b,n,s,c,NULL) ++#endif ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#ifndef KERN_SOH ++#define KERN_SOH "\001" /* ASCII Start Of Header */ ++#endif ++ ++#ifndef KERN_EMERG ++#define KERN_EMERG KERN_SOH "0" /* system is unusable */ ++#endif ++ ++#ifndef KERN_ALERT ++#define KERN_ALERT KERN_SOH "1" /* action must be taken immediately */ ++#endif ++ ++#ifndef KERN_CRIT ++#define KERN_CRIT KERN_SOH "2" /* critical conditions */ ++#endif ++ ++#ifndef KERN_ERR ++#define KERN_ERR KERN_SOH "3" /* error conditions */ ++#endif ++ ++#ifndef KERN_WARNING ++#define KERN_WARNING KERN_SOH "4" /* warning conditions */ ++#endif ++ ++#ifndef KERN_NOTICE ++#define KERN_NOTICE KERN_SOH "5" /* normal but significant condition */ ++#endif ++ ++#ifndef KERN_INFO ++#define KERN_INFO KERN_SOH "6" /* informational */ ++#endif ++ ++#ifndef KERN_DEBUG ++#define KERN_DEBUG KERN_SOH "7" /* debug-level messages */ ++#endif ++ ++#endif //__CAM_OS_UTIL_STRING_H__ +diff --git a/drivers/sstar/cam_os_wrapper/pub/cam_os_wrapper.h b/drivers/sstar/cam_os_wrapper/pub/cam_os_wrapper.h +new file mode 100755 +index 000000000000..e1a591a844c2 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/pub/cam_os_wrapper.h +@@ -0,0 +1,1779 @@ ++/* ++* cam_os_wrapper.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.h ++/// @brief Cam OS Wrapper Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_OS_WRAPPER_H__ ++#define __CAM_OS_WRAPPER_H__ ++ ++#define CAM_OS_WRAPPER_VERSION "v1.0.35" ++ ++#if defined(__aarch64__) ++#define CAM_OS_BITS_PER_LONG 64 ++#else ++#define CAM_OS_BITS_PER_LONG 32 ++#endif ++ ++#ifndef NULL ++#define NULL 0 ++#endif ++ ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++#include "cam_os_util.h" ++#include "cam_os_util_list.h" ++#include "cam_os_util_bug.h" ++#include "cam_os_util_hash.h" ++#include "cam_os_util_bitmap.h" ++#include "cam_os_util_ioctl.h" ++#include "cam_os_util_string.h" ++ ++#define CAM_OS_MAX_TIMEOUT ((u32)(~0U)) ++#define CAM_OS_MAX_INT ((s32)(~0U>>1)) ++ ++typedef enum ++{ ++ CAM_OS_OK = 0, ++ CAM_OS_FAIL = -1, ++ CAM_OS_PARAM_ERR = -2, ++ CAM_OS_ALLOCMEM_FAIL = -3, ++ CAM_OS_TIMEOUT = -4, ++ CAM_OS_RESOURCE_BUSY = -5, ++ CAM_OS_INTERRUPTED = -6, ++} CamOsRet_e; ++ ++typedef enum ++{ ++ CAM_OS_MEM_1MB = 0, ++ CAM_OS_MEM_2MB = 1, ++ CAM_OS_MEM_4MB = 2, ++ CAM_OS_MEM_8MB = 3, ++ CAM_OS_MEM_16MB = 4, ++ CAM_OS_MEM_32MB = 5, ++ CAM_OS_MEM_64MB = 6, ++ CAM_OS_MEM_128MB = 7, ++ CAM_OS_MEM_256MB = 8, ++ CAM_OS_MEM_512MB = 9, ++ CAM_OS_MEM_1024MB = 10, ++ CAM_OS_MEM_UNKNOWN = 99, ++} CamOsMemSize_e; ++ ++typedef enum ++{ ++ CAM_OS_TIME_DIFF_SEC = 0, ++ CAM_OS_TIME_DIFF_MS = 1, ++ CAM_OS_TIME_DIFF_US = 2, ++ CAM_OS_TIME_DIFF_NS = 3, ++} CamOsTimeDiffUnit_e; ++ ++typedef struct ++{ ++ u32 nPriv[11]; ++} CamOsMutex_t; ++ ++typedef struct ++{ ++ u32 nPriv[16]; ++} CamOsTsem_t; ++ ++typedef struct ++{ ++ u32 nPriv[20]; ++} CamOsRwsem_t; ++ ++typedef struct ++{ ++ u32 nPriv[20]; ++} CamOsTcond_t; ++ ++typedef struct ++{ ++ u32 nPriv[6]; ++}CamOsSpinlock_t; ++ ++typedef struct ++{ ++ u32 nSec; ++ u32 nNanoSec; ++} CamOsTimespec_t; ++ ++typedef struct ++{ ++ u32 nPriority; /* From 1(lowest) to 99(highest), use OS default priority if set 0 */ ++ u32 nStackSize; /* If nStackSize is zero, use OS default value */ ++ char *szName; ++} CamOsThreadAttrb_t, *pCamOsThreadAttrb; ++ ++typedef struct ++{ ++ u32 nPriv[8]; ++} CamOsTimer_t; ++ ++typedef struct ++{ ++ u32 nPriv[2]; ++} CamOsMemCache_t; ++ ++typedef struct ++{ ++ volatile s32 nCounter; ++} CamOsAtomic_t; ++ ++typedef struct ++{ ++ u32 nPriv[20]; ++} CamOsIdr_t; ++ ++typedef struct ++{ ++ u32 nBytes; ++ u16 nType; ++ u16 nBusWidth; ++} CamOsDramInfo_t; ++ ++typedef void * CamOsThread; ++ ++typedef void (*CamOsIrqHandler)(u32 nIrq, void *pDevId); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// N/A ++// Return: ++// C string type of version information. ++//============================================================================= ++char *CamOsVersion(void); ++ ++//============================================================================= ++// Description: ++// Writes the C string pointed by format to the standard output. ++// Parameters: ++// [in] szFmt: C string that contains the text to be written, it can ++// optionally contain embedded format specifiers. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPrintf(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Writes the C string pointed without format to the standard output. ++// Parameters: ++// [in] szStr: C string that contains the text to be written. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPrintString(const char *szStr); ++ ++//============================================================================= ++// Description: ++// Reads data from stdin and stores them according to the parameter format ++// into the locations pointed by the additional arguments. ++// Parameters: ++// [in] szFmt: C string that contains the text to be parsing, it can ++// optionally contain embedded format specifiers. ++// Return: ++// The number of items of the argument list successfully filled. ++//============================================================================= ++s32 CamOsScanf(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Returns the next character from the standard input. ++// Parameters: ++// N/A ++// Return: ++// the character read is returned. ++//============================================================================= ++s32 CamOsGetChar(void); ++ ++//============================================================================= ++// Description: ++// Reads data from stdin and stores them according to the parameter format ++// into the locations pointed by the additional arguments. ++// Parameters: ++// [in] szBuf: Pointer to a buffer where the resulting C-string is stored. ++// The buffer should have a size of at least nSize characters. ++// [in] nSize: Maximum number of bytes to be used in the buffer. ++// The generated string has a length of at most nSize-1, ++// leaving space for the additional terminating null character. ++// [in] szFmt: C string that contains a format string, it can optionally ++// contain embedded format specifiers. ++// Return: ++// The number of items of the argument list successfully filled. ++//============================================================================= ++s32 CamOsSnprintf(char *szBuf, u32 nSize, const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Display the input offset in hexadecimal ++// Parameters: ++// [in] szBuf: Pointer to a buffer. ++// [in] nSize: Interpret only length bytes of input. ++// Return: ++// N/A ++//============================================================================= ++void CamOsHexdump(char *szBuf, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Suspend execution for millisecond intervals. ++// In Linux, sleeping for larger msecs(10ms+). ++// Parameters: ++// [in] nMsec: Millisecond to suspend. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMsSleep(u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Suspend execution for microsecond intervals. ++// In Linux, sleeping for ~usecs or small msecs(10us~20ms). ++// Parameters: ++// [in] nUsec: Microsecond to suspend. ++// Return: ++// N/A ++//============================================================================= ++void CamOsUsSleep(u32 nUsec); ++ ++//============================================================================= ++// Description: ++// Busy-delay execution for millisecond intervals. ++// Parameters: ++// [in] nMsec: Millisecond to busy-delay. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMsDelay(u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Busy-delay execution for microsecond intervals. ++// Parameters: ++// [in] nUsec: Microsecond to busy-delay. ++// Return: ++// N/A ++//============================================================================= ++void CamOsUsDelay(u32 nUsec); ++ ++//============================================================================= ++// Description: ++// Get the number of seconds and nanoseconds since the Epoch. ++// Parameters: ++// [out] ptRes: A pointer to a CamOsTimespec_t structure where ++// CamOsGetTimeOfDay() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetTimeOfDay(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Set the number of seconds and nanoseconds since the Epoch. ++// Parameters: ++// [in] ptRes: A pointer to a CamOsTimespec_t structure. ++// Return: ++// N/A ++//============================================================================= ++void CamOsSetTimeOfDay(const CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Gets the current time of the clock specified, and puts it into the ++// buffer pointed to by ptRes. ++// Parameters: ++// [out] ptRes: A pointer to a CamOsTimespec_t structure where ++// CamOsGetMonotonicTime() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Subtracts ptEnd from ptStart ++// Parameters: ++// [in] ptStart: A pointer to a CamOsTimespec_t structure store the start time. ++// [in] ptEnd: A pointer to a CamOsTimespec_t structure store the end time. ++// [in] eUnit: result unit in second, millisecond, microsecond or nanosecond. ++// Return: ++// Difference of ptEnd and ptStart, or return 0 if giving invalid parameter. ++//============================================================================= ++s64 CamOsTimeDiff(CamOsTimespec_t *ptStart, CamOsTimespec_t *ptEnd, CamOsTimeDiffUnit_e eUnit); ++ ++//============================================================================= ++// Description: ++// The CamOsThreadCreate() function is used to create a new thread/task, ++// with attributes specified by ptAttrb. If ptAttrb is NULL, the default ++// attributes are used. ++// Parameters: ++// [out] ptThread: A successful call to CamOsThreadCreate() stores the handle ++// of the new thread. ++// [in] ptAttrb: Argument points to a CamOsThreadAttrb_t structure whose ++// contents are used at thread creation time to determine ++// thread priority, stack size and thread name. Thread ++// priority range from 1(lowest) to 99(highest), use OS ++// default priority if set 0. ++// ------------------------------------------------------------------------ ++// |nPriority| 1 ~ 49 | 50 | 51 ~ 70 | 71 ~ 94 | 95 ~ 99 | ++// ------------------------------------------------------------------------ ++// | Linux |SCHED_OTHER|SCHED_OTHER|SCHED_OTHER| SCHED_RR | SCHED_RR | ++// | | NICE 19~1 | NICE 0 |NICE -1~-20|RTPRIO 1~94|RTPRIO 95~99| ++// ------------------------------------------------------------------------ ++// [in] pfnStartRoutine(): The new thread starts execution by invoking it. ++// [in] pArg: It is passed as the sole argument of pfnStartRoutine(). ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadCreate(CamOsThread *ptThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg); ++ ++//============================================================================= ++// Description: ++// Change priority of a thread created by CamOsThreadCreate. ++// Parameters: ++// [in] pThread: Handle of target thread. ++// [in] nPriority: New priority of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadChangePriority(CamOsThread pThread, u32 nPriority); ++ ++//============================================================================= ++// Description: ++// Schedule out a thread created by CamOsThreadCreate. ++// Parameters: ++// [in] bInterruptible: Setup if schedule method with timeout is ++// interruptible. This parameter is only applicable ++// to Linux kernel space. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadSchedule(u8 bInterruptible, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Wake up the thread specified by pThread to run. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadWakeUp(CamOsThread tThread); ++ ++//============================================================================= ++// Description: ++// Waits for the thread specified by tThread to terminate. If that thread ++// has already terminated, then CamOsThreadJoin() returns immediately. This ++// function is not applicable to Linux kernel space. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadJoin(CamOsThread tThread); ++ ++//============================================================================= ++// Description: ++// Stop a thread created by CamOsThreadCreate in Linux kernel space. This ++// function is not applicable to Linux user space. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadStop(CamOsThread tThread); ++ ++//============================================================================= ++// Description: ++// When someone calls CamOsThreadStop, it will be woken and this will ++// return true. You should then return from the thread. This function is ++// not applicable to Linux user space. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadShouldStop(void); ++ ++//============================================================================= ++// Description: ++// Set the name of a thread. The thread name is a meaningful C language ++// string, whose length is restricted to 16 characters, including the ++// terminating null byte ('\0'). ++// Parameters: ++// [in] tThread: Handle of target thread. ++// [in] szName: specifies the new name. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadSetName(CamOsThread tThread, const char *szName); ++ ++//============================================================================= ++// Description: ++// Get the name of a thread. The buffer specified by name should be at ++// least 16 characters in length. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// [out] szName: Buffer used to return the thread name. ++// [in] nLen: Specifies the number of bytes available in szName ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadGetName(CamOsThread tThread, char *szName, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Get thread identification. ++// Parameters: ++// N/A ++// Return: ++// On success, returns the thread ID of the calling process. ++//============================================================================= ++u32 CamOsThreadGetID(void); ++ ++//============================================================================= ++// Description: ++// Initializes the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Destroys the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Lock the mutex, if mutex isn't initialized, this API will init it ++// automatically. ++// Parameters: ++// [in] ptMutex: The mutex to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Try lock the mutex, and return as non-blocking mode. If mutex isn't ++// initialized, this API will init itautomatically. ++// Parameters: ++// [in] ptMutex: The mutex to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexTryLock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Unlock the mutex, if mutex isn't initialized, this API will init it ++// automatically. ++// Parameters: ++// [in] ptMutex: The mutex to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Initializes the semaphore at a given value. ++// Parameters: ++// [in] ptTsem: The semaphore to initialize. ++// [in] nVal: the initial value of the semaphore. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal); ++ ++//============================================================================= ++// Description: ++// Destroy the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Increases the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to increase. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemUp(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemDown(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. This function is interruptible in Linux kernel. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// N/A ++//============================================================================= ++CamOsRet_e CamOsTsemDownInterruptible(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if down successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Always return as non-blocking mode. Decreases the value of the semaphore ++// if it is bigger than zero. If the semaphore value is less than or equal ++// to zero, return directly. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// CAM_OS_OK is returned if down successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTryDown(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Initializes the rw semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemInit(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Destroys the read-write semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemDeinit(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Unlock the read semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to unlock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemUpRead(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Unlock the write semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to unlock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemUpWrite(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Lock the read semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemDownRead(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Lock the write semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemDownWrite(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Try lock the read semaphore, and return as non-blocking mode. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemTryDownRead(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Try lock the write semaphore, and return as non-blocking mode. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemTryDownWrite(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Initializes the condition. ++// Parameters: ++// [in] ptTcond: The condition to Initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondInit(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Destroys the condition. ++// Parameters: ++// [in] ptTcond: The condition to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondDeinit(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Signal the condition, if anyone waiting. ++// Parameters: ++// [in] ptTcond: The condition to signal ++// Return: ++// N/A ++//============================================================================= ++void CamOsTcondSignal(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Signal the condition for all waitings totally. ++// Parameters: ++// [in] ptTcond: The condition to signal ++// Return: ++// N/A ++//============================================================================= ++void CamOsTcondSignalAll(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTcondWait(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if wait successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondTimedWait(CamOsTcond_t *ptTcond, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Wait on the condition(it's interruptible). ++// This API is the same with CamOsTcondSignal in RTK and Linux user space. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// Return: ++// If a signal was received while waiting it will return CAM_OS_INTERRUPTED; ++// CAM_OS_OK is returned if wait successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondWaitInterruptible(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Wait on the condition with time limitation(it's interruptible). ++// This API is the same with CamOsTcondSignal in RTK and Linux user space. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If a signal was received it will return CAM_OS_INTERRUPTED; otherwise ++// it returns CAM_OS_TIMEOUT if the completion timed out or CAM_OS_OK if ++// completion occurred. ++//============================================================================= ++CamOsRet_e CamOsTcondTimedWaitInterruptible(CamOsTcond_t *ptTcond, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Check if any task wait for this condition. ++// This API is not supported to Linux user space. ++// Parameters: ++// [in] ptTcond: The condition to check. ++// Return: ++// If any task waits for this condition, CAM_OS_OK is returned. ++// CAM_OS_FAIL is returned if no one waits; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondWaitActive(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Initializes the spinlock. ++// Parameters: ++// [in] ptSpinlock: The spinlock to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinInit(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Lock the spinlock, if spinlock isn't initialized, this API will init it ++// automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinLock(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Unlock the spinlock, if spinlock isn't initialized, this API will init ++// it automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinUnlock(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Lock the spinlock and save IRQ status, if spinlock isn't initialized, ++// this API will init it automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinLockIrqSave(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Unlock the spinlock and restore IRQ status, if spinlock isn't initialized, ++// this API will init it automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinUnlockIrqRestore(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of memory, returning a pointer to the ++// beginning of the block. ++// Parameters: ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemAlloc(u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of memory without sleep, returning a ++// pointer to the beginning of the block. ++// Parameters: ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemAllocAtomic(u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of memory for an array of nNum elements, each of them ++// nSize bytes long, and initializes all its bits to zero. ++// Parameters: ++// [in] nNum: Number of elements to allocate. ++// [in] nSize: Size of each element. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemCalloc(u32 nNum, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of memory for an array of nNum elements without sleep, ++// each of them nSize bytes long, and initializes all its bits to zero. ++// Parameters: ++// [in] nNum: Number of elements to allocate. ++// [in] nSize: Size of each element. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemCallocAtomic(u32 nNum, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Changes the size of the memory block pointed to by pPtr. The function ++// may move the memory block to a new location (whose address is returned ++// by the function). ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// [in] nSize: New size for the memory block, in bytes. ++// Return: ++// A pointer to the reallocated memory block, which may be either the same ++// as pPtr or a new location. ++//============================================================================= ++void* CamOsMemRealloc(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Changes the size of the memory block pointed to by pPtr without sleep. ++// The function may move the memory block to a new location (whose address ++// is returned by the function). ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// [in] nSize: New size for the memory block, in bytes. ++// Return: ++// A pointer to the reallocated memory block, which may be either the same ++// as pPtr or a new location. ++//============================================================================= ++void* CamOsMemReallocAtomic(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Flush data in cache ++// Parameters: ++// [in] pPtr: Virtual start address ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemFlush(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Flush data in inner and outer cache ++// Parameters: ++// [in] pVa: Virtual start address ++// [in] pPa: Physical start address ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemFlushExt(void* pVa, void* pPA, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Invalidate data in cache ++// Parameters: ++// [in] pPtr: Virtual start address ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemInvalidate(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsMemAlloc, ++// CamOsMemCalloc or CamOsMemRealloc is deallocated, making it available ++// again for further allocations. If pPtr is a null pointer, the function ++// does nothing. ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemRelease(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Flush MIU write buffer. ++// Parameters: ++// N/A ++// Return: ++// N/A ++//============================================================================= ++void CamOsMiuPipeFlush(void); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of direct memory (non-cached memory), ++// returning three pointer for different address domain to the beginning ++// of the block. ++// Parameters: ++// [in] szName: Name of the memory block, whose length is restricted to ++// 16 characters. ++// [in] nSize: Size of the memory block, in bytes. ++// [out] ppVirtPtr: Virtual address pointer to the memory block. ++// [out] ppPhysPtr: Physical address pointer to the memory block. ++// [out] ppMiuPtr: Memory Interface Unit address pointer to the memory block. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppVirtPtr, ++ void** ppPhysPtr, ++ void** ppMiuPtr); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsDirectMemAlloc, ++// is deallocated, making it available again for further allocations. ++// Parameters: ++// [in] pPtr: Physical or Virtual address pointer to a memory block ++// previously allocated with CamOsDirectMemAlloc. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemRelease(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Flush chche of a block of memory previously allocated by a call to ++// CamOsDirectMemAlloc. ++// Parameters: ++// [in] pPtr: Physical or Virtual address pointer to a memory block ++// previously allocated with CamOsDirectMemAlloc. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemFlush(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Print all allocated direct memory information to the standard output. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemStat(void); ++ ++//============================================================================= ++// Description: ++// Transfer Physical address to MIU address. ++// Parameters: ++// [in] pPtr: Physical address. ++// Return: ++// MIU address. ++//============================================================================= ++void* CamOsDirectMemPhysToMiu(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Transfer MIU address to Physical address. ++// Parameters: ++// [in] pPtr: MIU address. ++// Return: ++// Physical address. ++//============================================================================= ++void* CamOsDirectMemMiuToPhys(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Transfer Physical address to Virtual address. ++// Parameters: ++// [in] pPtr: Physical address. ++// Return: ++// Virtual address. ++//============================================================================= ++void* CamOsDirectMemPhysToVirt(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Transfer Virtual address to Physical address. ++// Parameters: ++// [in] pPtr: Virtual address. ++// Return: ++// Physical address. ++//============================================================================= ++void* CamOsDirectMemVirtToPhys(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Map Physical address to Virtual address. ++// Parameters: ++// [in] pPhyPtr: Physical address. ++// [in] nSize: Size of the memory block, in bytes. ++// [in] bNonCache: Map to cache or non-cache area. ++// Return: ++// Virtual address. ++//============================================================================= ++void* CamOsPhyMemMap(void* pPhyPtr, u32 nSize, u8 bNonCache); ++ ++//============================================================================= ++// Description: ++// Unmap Virtual address that was mapped by CamOsPhyMemMap. ++// Parameters: ++// [in] pVirtPtr: Virtual address. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPhyMemUnMap(void* pVirtPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Map physical address to virtual address. ++// Parameters: ++// [in] pPhyPtr: Physical address. ++// [in] nSize: Size of the memory block, in bytes. ++// [in] bCache: Map to cache or non-cache area. ++// Return: ++// Virtual address. ++//============================================================================= ++void* CamOsMemMap(void* pPhyPtr, u32 nSize, u8 bCache); ++ ++//============================================================================= ++// Description: ++// Unmap virtual address that was mapped by CamOsMemMap. ++// Parameters: ++// [in] pVirtPtr: Virtual address. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemUnmap(void* pVirtPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Create a memory cache(memory pool) and allocate with specified size ++// to ignore internal fragmentation. ++// Parameters: ++// [out] ptMemCache: Get memory cache information if create successfully. ++// [in] szName: A string which is used in /proc/slabinfo to identify ++// this cache(It's significant only in linux kernel). ++// [in] nSize: Object size in this cache. ++// [in] bHwCacheAlign: Align objs on cache lines(Only for Linux) ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMemCacheCreate(CamOsMemCache_t *ptMemCache, char *szName, u32 nSize, u8 bHwCacheAlign); ++ ++//============================================================================= ++// Description: ++// Destroy the memory cache. ++// Parameters: ++// [in] ptMemCache: The cache to destroy. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemCacheDestroy(CamOsMemCache_t *ptMemCache); ++ ++//============================================================================= ++// Description: ++// Allocate a memory block(object) from this memory cache. ++// Parameters: ++// [in] ptMemCache: The cache to be allocated. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void *CamOsMemCacheAlloc(CamOsMemCache_t *ptMemCache); ++ ++//============================================================================= ++// Description: ++// Allocate a memory block(object) from this memory cache without sleep. ++// Parameters: ++// [in] ptMemCache: The cache to be allocated. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void *CamOsMemCacheAllocAtomic(CamOsMemCache_t *ptMemCache); ++ ++//============================================================================= ++// Description: ++// Release a memory block(object) to this memory cache. ++// Parameters: ++// [in] ptMemCache: The cache to be released to. ++// [in] pObjPtr: Pointer to a memory block(object) previously allocated by ++// CamOsMemCacheAlloc. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemCacheFree(CamOsMemCache_t *ptMemCache, void *pObjPtr); ++ ++//============================================================================= ++// Description: ++// Set property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [in] szValue: Value if property. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue); ++ ++//============================================================================= ++// Description: ++// Get property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [out] szValue: Value if property. ++// [in] szDefaultValue: If the property read fails or returns an empty ++// value, the default value is used ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertyGet(const char *szkey, char *szValue, const char *szDefaultValue); ++ ++//============================================================================= ++// Description: ++// Unsigned 64bit divide with Unsigned 64bit divisor with remainder. ++// Parameters: ++// [in] nDividend: Dividend. ++// [in] nDivisor: Divisor. ++// [out] pRemainder: Pointer to the remainder. This parameter can also be ++// a null pointer, in which case it is not used. ++// Return: ++// Quotient of division. ++//============================================================================= ++u64 CamOsMathDivU64(u64 nDividend, u64 nDivisor, u64 *pRemainder); ++ ++//============================================================================= ++// Description: ++// Signed 64bit divide with signed 64bit divisor with remainder. ++// Parameters: ++// [in] nDividend: Dividend. ++// [in] nDivisor: Divisor. ++// [out] pRemainder: Pointer to the remainder. This parameter can also be ++// a null pointer, in which case it is not used. ++// Return: ++// Quotient of division. ++//============================================================================= ++s64 CamOsMathDivS64(s64 nDividend, s64 nDivisor, s64 *pRemainder); ++ ++//============================================================================= ++// Description: ++// Copy a block of data from user space in Linux kernel space, it just ++// memory copy in RTOS. ++// Parameters: ++// [in] pTo: Destination address, in kernel space. ++// [in] pFrom: Source address, in user space. ++// [in] nLen: Number of bytes to copy. ++// Return: ++// Number of bytes that could not be copied. On success, this will be zero. ++//============================================================================= ++u32 CamOsCopyFromUpperLayer(void *pTo, const void *pFrom, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Copy a block of data into user space in Linux kernel space, it just ++// memory copy in RTOS. ++// Parameters: ++// [in] pTo: Destination address, in user space. ++// [in] pFrom: Source address, in kernel space. ++// [in] nLen: Number of bytes to copy. ++// Return: ++// Number of bytes that could not be copied. On success, this will be zero. ++//============================================================================= ++u32 CamOsCopyToUpperLayer(void *pTo, const void * pFrom, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Init timer. ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTimerInit(CamOsTimer_t *ptTimer); ++ ++//============================================================================= ++// Description: ++// Deactivates a timer ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// Return: ++// 0 is returned if timer has expired; otherwise, returns 1. ++//============================================================================= ++u32 CamOsTimerDelete(CamOsTimer_t *ptTimer); ++ ++//============================================================================= ++// Description: ++// Deactivates a timer and wait for the handler to finish. This function ++// only differs from del_timer on SMP ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// Return: ++// 0 is returned if timer has expired; otherwise, returns 1. ++//============================================================================= ++u32 CamOsTimerDeleteSync(CamOsTimer_t *ptTimer); ++ ++//============================================================================= ++// Description: ++// Start timer. ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// [in] nMsec: The value of timer for the timeout. ++// [in] pDataPtr: Pointer of user data for callback function. ++// [in] pfnFunc: Pointer of callback function. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTimerAdd(CamOsTimer_t *ptTimer, u32 nMsec, void *pDataPtr, void (*pfnFunc)(unsigned long nDataAddr)); ++ ++//============================================================================= ++// Description: ++// Restart timer that has been added with new timeout value. ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// [in] nMsec: The value of timer for the timeout. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTimerModify(CamOsTimer_t *ptTimer, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Read atomic variable. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicRead(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Set atomic variable. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Required value. ++// Return: ++// N/A ++//============================================================================= ++void CamOsAtomicSet(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Add to the atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to add. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicAddReturn(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Subtract the atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to subtract. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicSubReturn(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Subtract value from variable and test result. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to subtract. ++// Return: ++// Returns true if the result is zero, or false for all other cases. ++//============================================================================= ++s32 CamOsAtomicSubAndTest(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Increment atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicIncReturn(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// decrement atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicDecReturn(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Increment and test result. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// Returns true if the result is zero, or false for all other cases. ++//============================================================================= ++s32 CamOsAtomicIncAndTest(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Decrement and test result. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// Returns true if the result is zero, or false for all other cases. ++//============================================================================= ++s32 CamOsAtomicDecAndTest(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Add to the atomic variable and test if negative. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to subtract. ++// Return: ++// Returns true if the result is negative, or false when result is greater ++// than or equal to zero. ++//============================================================================= ++s32 CamOsAtomicAddNegative(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Read the 32-bit value (referred to as nOldValue) stored at location pointed by ptAtomic. ++// Compute (nOldValue == cmp) ? val : nOldValue and store result at location pointed by ptAtomic. The function returns nOldValue ++// Parameters: ++// [in] ptr: Pointer of type void ++// [in] nOldValue: old value. ++// [in] nNewValue : new value ++ ++// Return: ++// Returns true if the val is changed into new value ++//============================================================================= ++s32 CamOsAtomicCompareAndSwap(CamOsAtomic_t *ptAtomic, s32 nOldValue, s32 nNewValue); ++ ++//============================================================================= ++// Description: ++// AND operation with the atomic variable and return the new value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to AND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicAndFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// AND operation with the atomic variable and returns the value that had ++// previously been in memory. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to AND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchAnd(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// NAND operation with the atomic variable and return the new value. ++// GCC 4.4 and later implement NAND as "~(ptAtomic & nValue)" instead of ++// "~ptAtomic & nValue". ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to NAND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicNandFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// NAND operation with the atomic variable and returns the value that had ++// previously been in memory. GCC 4.4 and later implement NAND as ++// "~(ptAtomic & nValue)" instead of "~ptAtomic & nValue". ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to NAND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchNand(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// OR operation with the atomic variable and return the new value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to OR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicOrFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// OR operation with the atomic variable and returns the value that had ++// previously been in memory. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to OR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchOr(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// XOR operation with the atomic variable and return the new value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to XOR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicXorFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// XOR operation with the atomic variable and returns the value that had ++// previously been in memory. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to XOR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchXor(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Init IDR data structure. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsIdrInit(CamOsIdr_t *ptIdr); ++ ++//============================================================================= ++// Description: ++// Init IDR data structure with maximum entry number. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] nEntryNum: Maximum number of entries. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsIdrInitEx(CamOsIdr_t *ptIdr, u32 nEntryNum); ++ ++//============================================================================= ++// Description: ++// Destroy the IDR data structure. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIdrDestroy(CamOsIdr_t *ptIdr); ++ ++//============================================================================= ++// Description: ++// Increment atomic variable and return value. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] pPtr: Pointer of the data to store in IDR structure. ++// [in] nStart: Start number of requested ID range. ++// [in] nEnd: End number of requested ID range. ++// Return: ++// The allocated ID number. If allocation fail, negative integer will ++// be returned. ++//============================================================================= ++s32 CamOsIdrAlloc(CamOsIdr_t *ptIdr, void *pPtr, s32 nStart, s32 nEnd); ++ ++//============================================================================= ++// Description: ++// Remove data from the IDR structure by ID. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] nId: Data ID number. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIdrRemove(CamOsIdr_t *ptIdr, s32 nId); ++ ++//============================================================================= ++// Description: ++// Find data from the IDR structure by ID. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] nId: Data ID number. ++// Return: ++// On success, a pointer to the data stored in IDR structure. If ++// failed to find, a null pointer is returned. ++//============================================================================= ++void *CamOsIdrFind(CamOsIdr_t *ptIdr, s32 nId); ++ ++//============================================================================= ++// Description: ++// Get physical memory size of system. ++// Parameters: ++// N/A ++// Return: ++// Enumeration of memory size. ++//============================================================================= ++CamOsMemSize_e CamOsPhysMemSize(void); ++ ++//============================================================================= ++// Description: ++// Get physical memory size of system. ++// Parameters: ++// [out] ptInfo: A pointer to a CamOsDramInfo_t structure where ++// CamOsDramInfo() can store the information. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDramInfo(CamOsDramInfo_t *ptInfo); ++ ++//============================================================================= ++// Description: ++// Get Chip ID. ++// Parameters: ++// N/A ++// Return: ++// Chip ID. ++//============================================================================= ++u32 CamOsChipId(void); ++ ++//============================================================================= ++// Description: ++// Get Chip Revision. ++// Parameters: ++// N/A ++// Return: ++// Chip revision. ++//============================================================================= ++u32 CamOsChipRevision(void); ++ ++//============================================================================= ++// Description: ++// Free an interrupt allocated with request_irq. ++// Parameters: ++// [in] nIrq: Interrupt line to allocate. ++// [in] pfnHandler: Function to be called when the IRQ occurs. ++// [in] szName: An ascii name for the claiming device. ++// [in] pDevId: A cookie passed back to the handler function. ++// Return: ++// N/A ++//============================================================================= ++CamOsRet_e CamOsIrqRequest(u32 nIrq, CamOsIrqHandler pfnHandler, const char *szName, void *pDevId); ++ ++//============================================================================= ++// Description: ++// Free an interrupt allocated with request_irq. ++// Parameters: ++// [in] nIrq: Interrupt line to free. ++// [in] pDevId: Device identity to free. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIrqFree(u32 nIrq, void *pDevId); ++ ++//============================================================================= ++// Description: ++// Enable handling of an irq. ++// Parameters: ++// [in] nIrq: Interrupt to enable. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIrqEnable(u32 nIrq); ++ ++//============================================================================= ++// Description: ++// Disable an irq and wait for completion. ++// Parameters: ++// [in] nIrq: Interrupt to disable. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIrqDisable(u32 nIrq); ++ ++//============================================================================= ++// Description: ++// Check if current function runs in ISR. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if in ISR; otherwise, returns CAM_OS_FAIL. ++//============================================================================= ++CamOsRet_e CamOsInInterrupt(void); ++ ++//============================================================================= ++// Description: ++// Memory barrier. ++// Parameters: ++// N/A ++// Return: ++// N/A. ++//============================================================================= ++void CamOsMemoryBarrier(void); ++ ++//============================================================================= ++// Description: ++// Symmetric multiprocessing memory barrier. ++// Parameters: ++// N/A ++// Return: ++// N/A. ++//============================================================================= ++void CamOsSmpMemoryBarrier(void); ++ ++//============================================================================= ++// Description: ++// Return string describing error number. ++// Parameters: ++// [in] nErrNo: Error number to be converted. ++// Return: ++// Character pointer to string of description. ++//============================================================================= ++char *CamOsStrError(s32 nErrNo); ++ ++//============================================================================= ++// Description: ++// Put system into panic. ++// Parameters: ++// [in] szMessage: message to output in console. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPanic(const char *szMessage); ++ ++//============================================================================= ++// Description: ++// Convert string to long integer with specific base. ++// Parameters: ++// [in] szStr: String beginning with the representation of ++// an integral number. ++// [in] szEndptr: Reference to an object of type char*, whose value ++// is set by the function to the next character in szStr ++// after the numerical value. ++// This parameter can also be a null pointer, in which ++// case it is not used. ++// [in] nBase: Numerical base (radix) that determines the valid characters ++// and their interpretation. If this is 0, the base used is ++// determined by the format in the sequence (see above). ++// Return: ++// Converted long integer. ++//============================================================================= ++long CamOsStrtol(const char *szStr, char** szEndptr, s32 nBase); ++ ++//============================================================================= ++// Description: ++// Convert string to unsigned long integer with specific base. ++// Parameters: ++// [in] szStr: String beginning with the representation of ++// an integral number. ++// [in] szEndptr: Reference to an object of type char*, whose value ++// is set by the function to the next character in szStr ++// after the numerical value. ++// This parameter can also be a null pointer, in which ++// case it is not used. ++// [in] nBase: Numerical base (radix) that determines the valid characters ++// and their interpretation. If this is 0, the base used is ++// determined by the format in the sequence (see above). ++// Return: ++// Converted long integer. ++//============================================================================= ++unsigned long CamOsStrtoul(const char *szStr, char** szEndptr, s32 nBase); ++ ++//============================================================================= ++// Description: ++// Convert string to unsigned long long integer with specific base. ++// Parameters: ++// [in] szStr: String beginning with the representation of ++// an integral number. ++// [in] szEndptr: Reference to an object of type char*, whose value ++// is set by the function to the next character in szStr ++// after the numerical value. ++// This parameter can also be a null pointer, in which ++// case it is not used. ++// [in] nBase: Numerical base (radix) that determines the valid characters ++// and their interpretation. If this is 0, the base used is ++// determined by the format in the sequence (see above). ++// Return: ++// Converted long integer. ++//============================================================================= ++unsigned long long CamOsStrtoull(const char *szStr, char** szEndptr, s32 nBase); ++ ++#endif /* __CAM_OS_WRAPPER_H__ */ +diff --git a/drivers/sstar/cam_os_wrapper/src/cam_os_export.c b/drivers/sstar/cam_os_wrapper/src/cam_os_export.c +new file mode 100644 +index 000000000000..844109d9762e +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/src/cam_os_export.c +@@ -0,0 +1,168 @@ ++/* ++* cam_os_export.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_export.c ++/// @brief Cam OS Export Symbol Source File for Linux Kernel Space ++/// Only Include This File in Linux Kernel ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include "cam_os_wrapper.h" ++ ++EXPORT_SYMBOL(CamOsVersion); ++EXPORT_SYMBOL(CamOsPrintf); ++EXPORT_SYMBOL(CamOsPrintString); ++EXPORT_SYMBOL(CamOsScanf); ++EXPORT_SYMBOL(CamOsGetChar); ++EXPORT_SYMBOL(CamOsSnprintf); ++EXPORT_SYMBOL(CamOsHexdump); ++EXPORT_SYMBOL(CamOsMsSleep); ++EXPORT_SYMBOL(CamOsUsSleep); ++EXPORT_SYMBOL(CamOsMsDelay); ++EXPORT_SYMBOL(CamOsUsDelay); ++EXPORT_SYMBOL(CamOsGetTimeOfDay); ++EXPORT_SYMBOL(CamOsSetTimeOfDay); ++EXPORT_SYMBOL(CamOsGetMonotonicTime); ++EXPORT_SYMBOL(CamOsTimeDiff); ++EXPORT_SYMBOL(CamOsThreadCreate); ++EXPORT_SYMBOL(CamOsThreadChangePriority); ++EXPORT_SYMBOL(CamOsThreadSchedule); ++EXPORT_SYMBOL(CamOsThreadWakeUp); ++EXPORT_SYMBOL(CamOsThreadJoin); ++EXPORT_SYMBOL(CamOsThreadStop); ++EXPORT_SYMBOL(CamOsThreadShouldStop); ++EXPORT_SYMBOL(CamOsThreadSetName); ++EXPORT_SYMBOL(CamOsThreadGetName); ++EXPORT_SYMBOL(CamOsThreadGetID); ++EXPORT_SYMBOL(CamOsMutexInit); ++EXPORT_SYMBOL(CamOsMutexDestroy); ++EXPORT_SYMBOL(CamOsMutexLock); ++EXPORT_SYMBOL(CamOsMutexTryLock); ++EXPORT_SYMBOL(CamOsMutexUnlock); ++EXPORT_SYMBOL(CamOsTsemInit); ++EXPORT_SYMBOL(CamOsTsemDeinit); ++EXPORT_SYMBOL(CamOsTsemUp); ++EXPORT_SYMBOL(CamOsTsemDown); ++EXPORT_SYMBOL(CamOsTsemDownInterruptible); ++EXPORT_SYMBOL(CamOsTsemTimedDown); ++EXPORT_SYMBOL(CamOsTsemTryDown); ++EXPORT_SYMBOL(CamOsRwsemInit); ++EXPORT_SYMBOL(CamOsRwsemDeinit); ++EXPORT_SYMBOL(CamOsRwsemUpRead); ++EXPORT_SYMBOL(CamOsRwsemUpWrite); ++EXPORT_SYMBOL(CamOsRwsemDownRead); ++EXPORT_SYMBOL(CamOsRwsemDownWrite); ++EXPORT_SYMBOL(CamOsRwsemTryDownRead); ++EXPORT_SYMBOL(CamOsRwsemTryDownWrite); ++EXPORT_SYMBOL(CamOsTcondInit); ++EXPORT_SYMBOL(CamOsTcondDeinit); ++EXPORT_SYMBOL(CamOsTcondSignal); ++EXPORT_SYMBOL(CamOsTcondSignalAll); ++EXPORT_SYMBOL(CamOsTcondWait); ++EXPORT_SYMBOL(CamOsTcondTimedWait); ++EXPORT_SYMBOL(CamOsTcondWaitInterruptible); ++EXPORT_SYMBOL(CamOsTcondTimedWaitInterruptible); ++EXPORT_SYMBOL(CamOsTcondWaitActive); ++EXPORT_SYMBOL(CamOsSpinInit); ++EXPORT_SYMBOL(CamOsSpinLock); ++EXPORT_SYMBOL(CamOsSpinUnlock); ++EXPORT_SYMBOL(CamOsSpinLockIrqSave); ++EXPORT_SYMBOL(CamOsSpinUnlockIrqRestore); ++EXPORT_SYMBOL(CamOsMemAlloc); ++EXPORT_SYMBOL(CamOsMemAllocAtomic); ++EXPORT_SYMBOL(CamOsMemCalloc); ++EXPORT_SYMBOL(CamOsMemCallocAtomic); ++EXPORT_SYMBOL(CamOsMemRealloc); ++EXPORT_SYMBOL(CamOsMemReallocAtomic); ++EXPORT_SYMBOL(CamOsMemFlush); ++EXPORT_SYMBOL(CamOsMemFlushExt); ++EXPORT_SYMBOL(CamOsMemInvalidate); ++EXPORT_SYMBOL(CamOsMemRelease); ++EXPORT_SYMBOL(CamOsMiuPipeFlush); ++EXPORT_SYMBOL(CamOsDirectMemAlloc); ++EXPORT_SYMBOL(CamOsDirectMemRelease); ++EXPORT_SYMBOL(CamOsDirectMemFlush); ++EXPORT_SYMBOL(CamOsDirectMemStat); ++EXPORT_SYMBOL(CamOsDirectMemPhysToMiu); ++EXPORT_SYMBOL(CamOsDirectMemMiuToPhys); ++EXPORT_SYMBOL(CamOsDirectMemPhysToVirt); ++EXPORT_SYMBOL(CamOsDirectMemVirtToPhys); ++EXPORT_SYMBOL(CamOsPhyMemMap); ++EXPORT_SYMBOL(CamOsPhyMemUnMap); ++EXPORT_SYMBOL(CamOsMemMap); ++EXPORT_SYMBOL(CamOsMemUnmap); ++EXPORT_SYMBOL(CamOsMemCacheCreate); ++EXPORT_SYMBOL(CamOsMemCacheDestroy); ++EXPORT_SYMBOL(CamOsMemCacheAlloc); ++EXPORT_SYMBOL(CamOsMemCacheAllocAtomic); ++EXPORT_SYMBOL(CamOsMemCacheFree); ++EXPORT_SYMBOL(CamOsPropertySet); ++EXPORT_SYMBOL(CamOsPropertyGet); ++EXPORT_SYMBOL(CamOsMathDivU64); ++EXPORT_SYMBOL(CamOsMathDivS64); ++EXPORT_SYMBOL(CamOsCopyFromUpperLayer); ++EXPORT_SYMBOL(CamOsCopyToUpperLayer); ++EXPORT_SYMBOL(CamOsTimerInit); ++EXPORT_SYMBOL(CamOsTimerDelete); ++EXPORT_SYMBOL(CamOsTimerDeleteSync); ++EXPORT_SYMBOL(CamOsTimerAdd); ++EXPORT_SYMBOL(CamOsTimerModify); ++EXPORT_SYMBOL(CamOsAtomicRead); ++EXPORT_SYMBOL(CamOsAtomicSet); ++EXPORT_SYMBOL(CamOsAtomicAddReturn); ++EXPORT_SYMBOL(CamOsAtomicSubReturn); ++EXPORT_SYMBOL(CamOsAtomicSubAndTest); ++EXPORT_SYMBOL(CamOsAtomicIncReturn); ++EXPORT_SYMBOL(CamOsAtomicDecReturn); ++EXPORT_SYMBOL(CamOsAtomicIncAndTest); ++EXPORT_SYMBOL(CamOsAtomicDecAndTest); ++EXPORT_SYMBOL(CamOsAtomicAddNegative); ++EXPORT_SYMBOL(CamOsAtomicCompareAndSwap); ++EXPORT_SYMBOL(CamOsAtomicAndFetch); ++EXPORT_SYMBOL(CamOsAtomicFetchAnd); ++EXPORT_SYMBOL(CamOsAtomicNandFetch); ++EXPORT_SYMBOL(CamOsAtomicFetchNand); ++EXPORT_SYMBOL(CamOsAtomicOrFetch); ++EXPORT_SYMBOL(CamOsAtomicFetchOr); ++EXPORT_SYMBOL(CamOsAtomicXorFetch); ++EXPORT_SYMBOL(CamOsAtomicFetchXor); ++EXPORT_SYMBOL(CamOsIdrInit); ++EXPORT_SYMBOL(CamOsIdrInitEx); ++EXPORT_SYMBOL(CamOsIdrDestroy); ++EXPORT_SYMBOL(CamOsIdrAlloc); ++EXPORT_SYMBOL(CamOsIdrRemove); ++EXPORT_SYMBOL(CamOsIdrFind); ++EXPORT_SYMBOL(CamOsPhysMemSize); ++EXPORT_SYMBOL(CamOsDramInfo); ++EXPORT_SYMBOL(CamOsChipId); ++EXPORT_SYMBOL(CamOsChipRevision); ++EXPORT_SYMBOL(CamOsIrqRequest); ++EXPORT_SYMBOL(CamOsIrqFree); ++EXPORT_SYMBOL(CamOsIrqEnable); ++EXPORT_SYMBOL(CamOsIrqDisable); ++EXPORT_SYMBOL(CamOsInInterrupt); ++EXPORT_SYMBOL(CamOsMemoryBarrier); ++EXPORT_SYMBOL(CamOsSmpMemoryBarrier); ++EXPORT_SYMBOL(CamOsStrError); ++EXPORT_SYMBOL(CamOsPanic); ++EXPORT_SYMBOL(CamOsStrtol); ++EXPORT_SYMBOL(CamOsStrtoul); ++EXPORT_SYMBOL(CamOsStrtoull); ++EXPORT_SYMBOL(CamOsListSort); +diff --git a/drivers/sstar/cam_os_wrapper/src/cam_os_informal_idr.c b/drivers/sstar/cam_os_wrapper/src/cam_os_informal_idr.c +new file mode 100644 +index 000000000000..cb5e24286729 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/src/cam_os_informal_idr.c +@@ -0,0 +1,132 @@ ++/* ++* cam_os_informal_idr.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_informal_idr.c ++/// @brief Cam OS Informal IDR Source File for Linux User Space and RTK. ++/// It's Not A Standard IDR Algorithm. ++/////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_os_util_bitmap.h" ++ ++#define IDR_ENTRY_NUM 0x4000 ++ ++typedef struct ++{ ++ void **ppEntryPtr; ++ unsigned long *pBitmap; ++ unsigned long entry_num; ++} CamOsInformalIdr_t, *pCamOsInformalIdr; ++ ++CamOsRet_e _CamOsIdrInit(CamOsIdr_t *ptIdr, u32 nEntryNum) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ CamOsInformalIdr_t *pInformalIdr = (CamOsInformalIdr_t *)ptIdr; ++ ++ if (pInformalIdr) ++ { ++ pInformalIdr->entry_num = (nEntryNum)? nEntryNum : IDR_ENTRY_NUM; ++ ++ if (NULL == (pInformalIdr->ppEntryPtr = CamOsMemAlloc(sizeof(void *)*pInformalIdr->entry_num))) ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ ++ if (NULL == (pInformalIdr->pBitmap = CamOsMemAlloc(sizeof(unsigned long)*CAM_OS_BITS_TO_LONGS(pInformalIdr->entry_num)))) ++ { ++ CamOsMemRelease(pInformalIdr->ppEntryPtr); ++ pInformalIdr->ppEntryPtr = NULL; ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ } ++ ++ memset(pInformalIdr->ppEntryPtr, 0, sizeof(void *)*pInformalIdr->entry_num); ++ memset(pInformalIdr->pBitmap, 0, sizeof(unsigned long)*CAM_OS_BITS_TO_LONGS(pInformalIdr->entry_num)); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++ ++ return eRet; ++} ++ ++void _CamOsIdrDestroy(CamOsIdr_t *ptIdr) ++{ ++ CamOsInformalIdr_t *pInformalIdr = (CamOsInformalIdr_t *)ptIdr; ++ ++ if (pInformalIdr) ++ { ++ if (pInformalIdr->ppEntryPtr) ++ CamOsMemRelease(pInformalIdr->ppEntryPtr); ++ ++ if (pInformalIdr->pBitmap) ++ CamOsMemRelease(pInformalIdr->pBitmap); ++ } ++} ++ ++s32 _CamOsIdrAlloc(CamOsIdr_t *ptIdr, void *pDataPtr, s32 nStart, s32 nEnd) ++{ ++ CamOsInformalIdr_t *pInformalIdr = (CamOsInformalIdr_t *)ptIdr; ++ s32 nEmptyID=-1; ++ ++ if (pInformalIdr && pDataPtr && pInformalIdr->ppEntryPtr) ++ { ++ if (nEnd < nStart || nEnd == 0) ++ nEnd = pInformalIdr->entry_num - 1; ++ ++ nEmptyID = CAM_OS_FIND_NEXT_ZERO_BIT(pInformalIdr->pBitmap, pInformalIdr->entry_num, nStart); ++ ++ if (nEmptyID < nStart || nEmptyID > nEnd) ++ nEmptyID = -1; ++ else ++ { ++ pInformalIdr->ppEntryPtr[nEmptyID] = pDataPtr; ++ CAM_OS_SET_BIT(nEmptyID, pInformalIdr->pBitmap); ++ } ++ } ++ ++ return nEmptyID; ++} ++ ++void _CamOsIdrRemove(CamOsIdr_t *ptIdr, s32 nId) ++{ ++ CamOsInformalIdr_t *pInformalIdr = (CamOsInformalIdr_t *)ptIdr; ++ ++ if (pInformalIdr && pInformalIdr->ppEntryPtr) ++ { ++ pInformalIdr->ppEntryPtr[nId] = NULL; ++ CAM_OS_CLEAR_BIT(nId, pInformalIdr->pBitmap); ++ } ++} ++ ++void *_CamOsIdrFind(CamOsIdr_t *ptIdr, s32 nId) ++{ ++ CamOsInformalIdr_t *pInformalIdr = (CamOsInformalIdr_t *)ptIdr; ++ ++ if (pInformalIdr && pInformalIdr->ppEntryPtr) ++ { ++ if (CAM_OS_TEST_BIT(nId, pInformalIdr->pBitmap)) ++ { ++ return pInformalIdr->ppEntryPtr[nId]; ++ } ++ } ++ ++ return NULL; ++} ++#endif +diff --git a/drivers/sstar/cam_os_wrapper/src/cam_os_wrapper.c b/drivers/sstar/cam_os_wrapper/src/cam_os_wrapper.c +new file mode 100755 +index 000000000000..ccadd11afa8c +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/src/cam_os_wrapper.c +@@ -0,0 +1,6061 @@ ++/* ++* cam_os_wrapper.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.c ++/// @brief Cam OS Wrapper Source File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#ifdef CAM_OS_RTK ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "sys_sys.h" ++#include "sys_sys_math64.h" ++#include "sys_sys_tools.h" ++#include "sys_sys_core.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#include "sys_MsWrapper_cus_os_util.h" ++#include "sys_MsWrapper_cus_os_timer.h" ++#include "sys_sys_isw_uart.h" ++#include "sys_rtk_hp.h" ++#include "hal_drv_util.h" ++#include "sys_time.h" ++#include "sys_arch_timer.h" ++#include "drv_bus_axi.h" ++#include "drv_int_ctrl_pub_api.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util.h" ++#include "cam_os_util_list.h" ++#include "cam_os_util_bitmap.h" ++ ++#define OS_NAME "RTK" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef void *CamOsThreadEntry_t(void *); ++ ++typedef struct ++{ ++ MsTaskId_e eHandleObj; ++ CamOsThreadEntry_t *pfnEntry; ++ void *pArg; ++ Ms_Flag_t tExitFlag; ++ void *pStack; ++} CamOsThreadHandleRtk_t, *pCamOsThreadHandleRtk; ++ ++typedef struct ++{ ++ u32 nInited; ++ Ms_Mutex_t tMutex; ++} CamOsMutexRtk_t, *pCamOsMutexRtk; ++ ++typedef struct ++{ ++ u32 nInited; ++ Ms_DynSemaphor_t Tsem; ++} CamOsTsemRtk_t, *pCamOsTsemRtk; ++ ++typedef struct ++{ ++ u32 nInited; ++ u32 nReadCount; ++ Ms_Mutex_t tRMutex; ++ Ms_DynSemaphor_t WTsem; ++} CamOsRwsemRtk_t, *pCamOsRwsemRtk; ++ ++typedef struct ++{ ++ u32 nInited; ++ Ms_DynSemaphor_t Tsem; ++} CamOsTcondRtk_t, *pCamOsTcondRtk; ++ ++typedef struct ++{ ++ unsigned long nFlags; ++} CamOsSpinlockRtk_t, *pCamOsSpinlockRtk; ++ ++typedef struct ++{ ++ MsTimerId_e eTimerID; ++ void (*pfnCallback)(unsigned long); ++ void *pDataPtr; ++} CamOsTimerRtk_t, *pCamOsTimerRtk; ++ ++typedef struct ++{ ++ u8 nPoolID; ++ u32 nObjSize; ++} CamOsMemCacheRtk_t, *pCamOsMemCacheRtk; ++ ++static Ms_Mutex_t _gtSelfInitLock = {0}; ++static Ms_Mutex_t _gtMemLock = {0}; ++ ++static u32 _gTimeOfDayOffsetSec = 0; ++static u32 _gTimeOfDayOffsetNanoSec = 0; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(Ms_Flag_t) + 4, "CamOsMutex_t size define not enough!"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemRtk_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsRwsem_t) >= sizeof(CamOsRwsemRtk_t), "CamOsRwsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTcond_t) >= sizeof(CamOsTcondRtk_t), "CamOsTcond_t size define not enough!"); ++_Static_assert(sizeof(CamOsSpinlock_t) >= sizeof(CamOsSpinlockRtk_t), "CamOsSpinlock_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimer_t) >= sizeof(CamOsTimerRtk_t), "CamOsTimer_t size define not enough!"); ++_Static_assert(sizeof(CamOsMemCache_t) >= sizeof(CamOsMemCacheRtk_t), "CamOsMemCache_t size define not enough!"); ++ ++CAM_OS_DECLARE_BITMAP(aThreadStopBitmap, RTK_MAX_TASKS); ++static u8 nThreadStopBitmapInited=0; ++ ++#elif defined(CAM_OS_LINUX_USER) ++#define _GNU_SOURCE ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifndef NO_MDRV_MSYS ++#include ++#include ++#include "mdrv_verchk.h" ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util.h" ++#include "cam_os_util_list.h" ++#include "cam_os_util_bitmap.h" ++ ++#define OS_NAME "LINUX USER" ++ ++typedef void *CamOsThreadEntry_t(void *); ++ ++typedef struct ++{ ++ pthread_t tThreadHandle; ++ CamOsThreadEntry_t *pfnEntry; ++ void *pArg; ++ u32 nPid; ++ CamOsTsem_t tEntryIn; ++} CamOsThreadHandleLinuxUser_t, *pCamOsThreadHandleLinuxUser; ++ ++typedef struct ++{ ++ u32 nInited; ++ pthread_mutex_t tMutex; ++} CamOsMutexLU_t, *pCamOsMutexLU; ++ ++typedef struct ++{ ++ u32 nInited; ++ sem_t tSem; ++} CamOsTsemLU_t, *pCamOsTsemLU; ++ ++typedef struct ++{ ++ u32 nInited; ++ pthread_rwlock_t tRwsem; ++} CamOsRwsemLU_t, *pCamOsRwsemLU; ++ ++typedef struct ++{ ++ u32 nInited; ++ pthread_mutex_t tMutex; ++ pthread_cond_t tCondition; ++} CamOsTcondLU_t, *pCamOsTcondLU; ++ ++typedef struct ++{ ++ u32 nInited; ++ pthread_spinlock_t tLock; ++} CamOsSpinlockLU_t, *pCamOsSpinlockLU; ++ ++typedef struct ++{ ++ timer_t tTimerID; ++} CamOsTimerLU_t, *pCamOsTimerLU; ++ ++typedef struct ++{ ++ u32 nIdrSize; ++ void *pEntryPtr; ++} CamOsIdrLU_t, *pCamOsIdrLU; ++ ++static pthread_mutex_t _gtSelfInitLock = PTHREAD_MUTEX_INITIALIZER; ++static pthread_mutex_t _gtMemLock = PTHREAD_MUTEX_INITIALIZER; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(pthread_mutex_t) + 4, "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLU_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsRwsem_t) >= sizeof(CamOsRwsemLU_t), "CamOsRwsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTcond_t) >= sizeof(CamOsTcondLU_t), "CamOsTcond_t size define not enough!"); ++_Static_assert(sizeof(CamOsSpinlock_t) >= sizeof(CamOsSpinlockLU_t), "CamOsSpinlock_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimer_t) >= sizeof(CamOsTimerLU_t), "CamOsTimer_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++_Static_assert(sizeof(CamOsIdr_t) >= sizeof(CamOsIdrLU_t), "CamOsIdr_t size define not enough!"); ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_miu.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util.h" ++#include "cam_os_util_list.h" ++#include "cam_os_util_bitmap.h" ++ ++#define OS_NAME "LINUX KERNEL" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++#define KMALLOC_THRESHOLD_SIZE (PAGE_SIZE >> 1) ++#define LOG_MAX_TRACE_LEN 256 ++#define LINUX_KERNEL_MAX_IRQ 256 ++ ++typedef struct ++{ ++ u32 nInited; ++ struct mutex tMutex; ++} CamOsMutexLK_t, *pCamOsMutexLK; ++ ++typedef struct ++{ ++ u32 nInited; ++ struct semaphore tSem; ++} CamOsTsemLK_t, *pCamOsTsemLK; ++ ++typedef struct ++{ ++ u32 nInited; ++ struct rw_semaphore tRwsem; ++} CamOsRwsemLK_t, *pCamOsRwsemLK; ++ ++typedef struct ++{ ++ u32 nInited; ++ struct completion tCompletion; ++} CamOsTcondLK_t, *pCamOsTcondLK; ++ ++typedef struct ++{ ++ u32 nInited; ++ spinlock_t tLock; ++ unsigned long nFlags; ++} CamOsSpinlockLK_t, *pCamOsSpinlockLK; ++ ++typedef struct ++{ ++ struct timer_list tTimerID; ++} CamOsTimerLK_t, *pCamOsTimerLK; ++ ++typedef struct ++{ ++ struct kmem_cache *ptKmemCache; ++} CamOsMemCacheLK_t, *pCamOsMemCacheLK; ++ ++typedef struct ++{ ++ struct idr tIdr; ++} CamOsIdrLK_t, *pCamOsIdrLK; ++ ++typedef s32 CamOsThreadEntry_t(void *); ++ ++static CamOsIrqHandler CamOsIrqHandlerList[LINUX_KERNEL_MAX_IRQ] = {0}; ++ ++static irqreturn_t CamOsIrqCommonHandler(u32 nIrq, void *pDevId) ++{ ++ if (nIrq < LINUX_KERNEL_MAX_IRQ && CamOsIrqHandlerList[nIrq] != NULL) ++ { ++ (CamOsIrqHandlerList[nIrq])(nIrq, pDevId); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++extern int msys_find_dmem_by_phys(unsigned long long phys, MSYS_DMEM_INFO* pdmem); ++ ++static DEFINE_MUTEX(_gtSelfInitLock); ++static DEFINE_MUTEX(_gtMemLock); ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(struct mutex) + 4, "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLK_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsRwsem_t) >= sizeof(CamOsRwsemLK_t), "CamOsRwsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTcond_t) >= sizeof(CamOsTcondLK_t), "CamOsTcond_t size define not enough!"); ++_Static_assert(sizeof(CamOsSpinlock_t) >= sizeof(CamOsSpinlockLK_t), "CamOsSpinlock_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++_Static_assert(sizeof(CamOsTimer_t) >= sizeof(CamOsTimerLK_t), "CamOsTimer_t size define not enough!"); ++_Static_assert(sizeof(CamOsMemCache_t) >= sizeof(CamOsMemCacheLK_t), "CamOsMemCache_t size define not enough!"); ++_Static_assert(sizeof(CamOsAtomic_t) == sizeof(atomic_t), "CamOsAtomic_t size define not enough!"); ++_Static_assert(sizeof(CamOsIdr_t) >= sizeof(CamOsIdrLK_t), "CamOsIdr_t size define not enough!"); ++ ++#endif ++ ++#define ASSIGN_POINTER_VALUE(a, b) if((a))*(a)=(b) ++ ++#define INIT_MAGIC_NUM 0x55AA5AA5 ++ ++#define CAM_OS_MAX_LIST_LENGTH_BITS 20 ++ ++#define CAM_OS_WARN_TRACE_LR ++#ifdef CAM_OS_WARN_TRACE_LR ++#define CAM_OS_WARN(x) CamOsPrintf("%s "x", LR:0x%08X\n", __FUNCTION__, __builtin_return_address(0)) ++#else ++#define CAM_OS_WARN(x) CamOsPrintf("%s "x"\n", __FUNCTION__) ++#endif ++ ++typedef struct MemoryList_t ++{ ++ struct CamOsListHead_t tList; ++ void *pPhysPtr; ++ void *pVirtPtr; ++ void *pMemifoPtr; ++ char *szName; ++ u32 nSize; ++} MemoryList_t; ++ ++static MemoryList_t _gtMemList; ++ ++static s32 _gnDmemDbgListInited = 0; ++ ++char *CamOsVersion(void) ++{ ++ return CAM_OS_WRAPPER_VERSION; ++} ++ ++void CamOsPrintf(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ va_list tArgs; ++ unsigned int u32MsgLen = 0; ++ char nLineStr[256] = {0}; ++ ++ va_start(tArgs, szFmt); ++ u32MsgLen = vsnprintf(nLineStr, sizeof(nLineStr), szFmt, tArgs); ++ if (u32MsgLen >= sizeof(nLineStr)) ++ { ++ nLineStr[sizeof(nLineStr)-1] = '\0'; /* even the 'vsnprintf' commond will do it */ ++ nLineStr[sizeof(nLineStr)-2] = '\n'; ++ nLineStr[sizeof(nLineStr)-3] = '.'; ++ nLineStr[sizeof(nLineStr)-4] = '.'; ++ nLineStr[sizeof(nLineStr)-5] = '.'; ++ } ++ send_msg(nLineStr); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_USER) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vfprintf(stderr, szFmt, tArgs); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_KERNEL) ++#if defined(CONFIG_MS_MSYS_LOG) ++ va_list tArgs; ++ unsigned int u32MsgLen = 0; ++ char szLogStr[LOG_MAX_TRACE_LEN]={'a'}; ++ va_start(tArgs, szFmt); ++ u32MsgLen = vsnprintf(szLogStr, LOG_MAX_TRACE_LEN, szFmt, tArgs); ++ va_end(tArgs); ++ if (u32MsgLen >= LOG_MAX_TRACE_LEN) ++ { ++ szLogStr[LOG_MAX_TRACE_LEN-1] = '\0'; /* even the 'vsnprintf' commond will do it */ ++ szLogStr[LOG_MAX_TRACE_LEN-2] = '\n'; ++ szLogStr[LOG_MAX_TRACE_LEN-3] = '.'; ++ szLogStr[LOG_MAX_TRACE_LEN-4] = '.'; ++ szLogStr[LOG_MAX_TRACE_LEN-5] = '.'; ++ } ++ msys_prints(szLogStr, u32MsgLen); ++#else ++ va_list tArgs; ++ va_start(tArgs, szFmt); ++ vprintk(szFmt, tArgs); ++ va_end(tArgs); ++#endif ++#endif ++} ++ ++void CamOsPrintString(const char *szStr) ++{ ++#ifdef CAM_OS_RTK ++ send_msg((char *)szStr); ++#elif defined(CAM_OS_LINUX_USER) ++ printf(szStr); ++#elif defined(CAM_OS_LINUX_KERNEL) ++#if defined(CONFIG_MS_MSYS_LOG) ++ msys_prints(szStr, strlen(szStr)); ++#else ++ printk(szStr); ++#endif ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static char* _CamOsAdvance(char* pBuf) ++{ ++ ++ char* pNewBuf = pBuf; ++ ++ /* Skip over nonwhite space */ ++ while((*pNewBuf != ' ') && (*pNewBuf != '\t') && ++ (*pNewBuf != '\n') && (*pNewBuf != '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ /* Skip white space */ ++ while((*pNewBuf == ' ') || (*pNewBuf == '\t') || ++ (*pNewBuf == '\n') || (*pNewBuf == '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ return pNewBuf; ++} ++ ++static s32 _CamOsVsscanf(char* szBuf, char* szFmt, va_list tArgp) ++{ ++ char* pFmt; ++ char* pBuf; ++ char* pnSval; ++ u32* pnU32Val; ++ s32* pnS32Val; ++ u64* pnU64Val; ++ s64* pnS64Val; ++ double* pdbDval; ++ float* pfFval; ++ s32 nCount = 0; ++ ++ pBuf = szBuf; ++ ++ for(pFmt = szFmt; *pFmt; pFmt++) ++ { ++ if(*pFmt == '%') ++ { ++ pFmt++; ++ if(strncmp(pFmt, "u", 1) == 0) ++ { ++ pnU32Val = va_arg(tArgp, u32 *); ++ sscanf(pBuf, "%u", pnU32Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if(strncmp(pFmt, "d", 1) == 0) ++ { ++ pnS32Val = va_arg(tArgp, s32 *); ++ sscanf(pBuf, "%d", pnS32Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if(strncmp(pFmt, "llu", 3) == 0) ++ { ++ pnU64Val = va_arg(tArgp, u64 *); ++ sscanf(pBuf, "%llu", pnU64Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if(strncmp(pFmt, "lld", 3) == 0) ++ { ++ pnS64Val = va_arg(tArgp, s64 *); ++ sscanf(pBuf, "%lld", pnS64Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if(strncmp(pFmt, "f", 1) == 0) ++ { ++ pfFval = va_arg(tArgp, float *); ++ sscanf(pBuf, "%f", pfFval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if(strncmp(pFmt, "lf", 2) == 0) ++ { ++ pdbDval = va_arg(tArgp, double *); ++ sscanf(pBuf, "%lf", pdbDval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if(strncmp(pFmt, "s", 1) == 0) ++ { ++ pnSval = va_arg(tArgp, char *); ++ sscanf(pBuf, "%s", pnSval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else ++ { ++ CamOsPrintf("%s error: unsupported format (\%%s)\n", __FUNCTION__, pFmt); ++ } ++ } ++ } ++ ++ return nCount; ++} ++ ++static s32 _CamOsGetString(char* szBuf, s32 nMaxLen, s32 nEcho) ++{ ++ s32 nLen; ++ static char ch = '\0'; ++ ++ nLen = 0; ++ while(1) ++ { ++ szBuf[nLen] = get_char(); ++ ++ // To ignore one for (\r,\n) or (\n, \r) pair ++ if((szBuf[nLen] == '\n' && ch == '\r') || (szBuf[nLen] == '\r' && ch == '\n')) ++ { ++ ch = '\0'; ++ continue; ++ } ++ ch = szBuf[nLen]; ++ if(ch == '\n' || ch == '\r') ++ { ++ if(nEcho) ++ CamOsPrintf("\n"); ++ break; ++ } ++ if(nLen < (nMaxLen - 1)) ++ { ++ if(ch == '\b') /* Backspace? */ ++ { ++ if(nLen <= 0) ++ CamOsPrintf("\007"); ++ else ++ { ++ CamOsPrintf("\b \b"); ++ nLen --; ++ } ++ continue; ++ } ++ nLen++; ++ } ++ if(nEcho) ++ CamOsPrintf("%c", ch); ++ } ++ szBuf[nLen] = '\0'; ++ return nLen; ++} ++ ++static s32 _CamOsVfscanf(const char *szFmt, va_list tArgp) ++{ ++ s32 nCount; ++ char szCommandBuf[128]; ++ ++ _CamOsGetString(szCommandBuf, sizeof(szCommandBuf), 1); ++ ++ nCount = _CamOsVsscanf(szCommandBuf, (char *)szFmt, tArgp); ++ return nCount; ++} ++#endif ++ ++s32 CamOsScanf(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start(tArgp, szFmt); ++ nCount = _CamOsVfscanf(szFmt, tArgp); ++ va_end(tArgp); ++ return nCount; ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start(tArgp, szFmt); ++ nCount = vfscanf(stdin, szFmt, tArgp); ++ va_end(tArgp); ++ return nCount; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++} ++ ++s32 CamOsGetChar(void) ++{ ++#ifdef CAM_OS_RTK ++ s32 Ret; ++ Ret = get_char(); ++ CamOsPrintf("\n"); ++ return Ret; ++#elif defined(CAM_OS_LINUX_USER) ++ return getchar(); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++} ++ ++s32 CamOsSnprintf(char *szBuf, u32 nSize, const char *szFmt, ...) ++{ ++ va_list tArgs; ++ s32 i; ++ ++ va_start(tArgs, szFmt); ++ i = vsnprintf(szBuf, nSize, szFmt, tArgs); ++ va_end(tArgs); ++ ++ return i; ++} ++ ++void CamOsHexdump(char *szBuf, u32 nSize) ++{ ++ int i, j; ++ int cx = 0; ++ char szLine[80] = {0}; ++ ++ CamOsPrintf("\nOffset(h) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\n" ++ "-----------------------------------------------------------\n"); ++ ++ if ((u32)szBuf % 16) ++ { ++ cx = 0; ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, "%08X ", (u32)szBuf & 0xFFFFFFF0); ++ ++ for (i = 0; i < (u32)szBuf % 16; i++) ++ { ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, " "); ++ szLine[i + 62] = ' '; ++ if (i % 8 == 0) ++ { ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, " "); ++ } ++ } ++ } ++ ++ for (i = 0; i < nSize; i++) ++ { ++ if ((i + (u32)szBuf) % 16 == 0) ++ { ++ cx = 0; ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, "%08X ", (u32)szBuf + i); ++ } ++ if ((i + (u32)szBuf) % 8 == 0) ++ { ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, " "); ++ } ++ ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, "%02X ", szBuf[i]); ++ ++ if (((unsigned char*)szBuf)[i] >= ' ' && ((unsigned char*)szBuf)[i] <= '~') ++ { ++ szLine[(i + (u32)szBuf) % 16 + 62] = ((unsigned char*)szBuf)[i]; ++ } ++ else ++ { ++ szLine[(i + (u32)szBuf) % 16 + 62] = '.'; ++ } ++ ++ if ((i + (u32)szBuf) % 16 == 15) ++ { ++ szLine[59] = ' '; ++ szLine[60] = ' '; ++ szLine[61] = '|'; ++ szLine[78] = '|'; ++ szLine[79] = 0; ++ CamOsPrintf("%s\n", szLine); ++ } ++ else if (i == nSize-1) ++ { ++ for (j = ((i + (u32)szBuf) + 1) % 16; j < 16; j++) ++ { ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, " "); ++ szLine[j + 62] = ' '; ++ } ++ if (((i + (u32)szBuf) + 1) % 16 <= 8) ++ { ++ cx += snprintf(szLine + cx, sizeof(szLine) - cx, " "); ++ } ++ szLine[59] = ' '; ++ szLine[60] = ' '; ++ szLine[61] = '|'; ++ szLine[78] = '|'; ++ szLine[79] = 0; ++ CamOsPrintf("%s\n", szLine); ++ } ++ } ++ CamOsPrintf("\n"); ++} ++ ++void CamOsMsSleep(u32 nMsec) ++{ ++#ifdef CAM_OS_RTK ++ MsSleep(RTK_MS_TO_TICK(nMsec)); ++#elif defined(CAM_OS_LINUX_USER) ++#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) ++#define MS_SLEEP_ACCURACY 10 ++ usleep((useconds_t)DIV_ROUND_UP(nMsec, MS_SLEEP_ACCURACY)*MS_SLEEP_ACCURACY*1000); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ msleep(nMsec); ++#endif ++} ++ ++void CamOsUsSleep(u32 nUsec) ++{ ++#ifdef CAM_OS_RTK ++ MsSleep(RTK_MS_TO_TICK(nUsec / 1000)); ++#elif defined(CAM_OS_LINUX_USER) ++ usleep((useconds_t)nUsec); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ usleep_range(nUsec, nUsec + 10); ++#endif ++} ++ ++void CamOsMsDelay(u32 nMsec) ++{ ++#ifdef CAM_OS_RTK ++ u64 nTicks = sys_arch_timer_get_counter(); ++ ++ while (((sys_arch_timer_get_counter() - nTicks) / (sys_arch_timer_get_cntfrq() / 1000)) < nMsec) {} ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTimespec_t tTvStart = {0}, tTvEnd = {0}; ++ CamOsGetMonotonicTime(&tTvStart); ++ do ++ { ++ CamOsGetMonotonicTime(&tTvEnd); ++ } ++ while (CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_MS) < nMsec); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ mdelay(nMsec); ++#endif ++} ++ ++void CamOsUsDelay(u32 nUsec) ++{ ++#ifdef CAM_OS_RTK ++ u64 nTicks = sys_arch_timer_get_counter(); ++ ++ while (((sys_arch_timer_get_counter() - nTicks) / (sys_arch_timer_get_cntfrq() / 1000000)) < nUsec) {} ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTimespec_t tTvStart = {0}, tTvEnd = {0}; ++ CamOsGetMonotonicTime(&tTvStart); ++ do ++ { ++ CamOsGetMonotonicTime(&tTvEnd); ++ } ++ while (CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_US) < nUsec); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ udelay(nUsec); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static void TimeNormalise(u32 *nSec, s32 *nNanoSec) ++{ ++ while(*nNanoSec >= 1000000000) ++ { ++ ++(*nSec); ++ *nNanoSec -= 1000000000; ++ } ++ ++ while(*nNanoSec <= 0) ++ { ++ --(*nSec); ++ *nNanoSec += 1000000000; ++ } ++ ++ return; ++} ++#endif ++ ++void CamOsGetTimeOfDay(CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ u32 nCurrSec = 0; ++ u32 nCurrNanoSec = 0; ++ ++ if(ptRes) ++ { ++ CamOsGetMonotonicTime(ptRes); ++ nCurrSec = ptRes->nSec + _gTimeOfDayOffsetSec; ++ nCurrNanoSec = ptRes->nNanoSec + _gTimeOfDayOffsetNanoSec; ++ TimeNormalise(&nCurrSec, (s32 *)&nCurrNanoSec); ++ ptRes->nSec = nCurrSec; ++ ptRes->nNanoSec = nCurrNanoSec; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ struct timeval tTV; ++ if(ptRes) ++ { ++ gettimeofday(&tTV, NULL); ++ ptRes->nSec = tTV.tv_sec; ++ ptRes->nNanoSec = tTV.tv_usec * 1000; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct timeval tTv; ++ if(ptRes) ++ { ++ do_gettimeofday(&tTv); ++ ptRes->nSec = tTv.tv_sec; ++ ptRes->nNanoSec = tTv.tv_usec * 1000; ++ } ++#endif ++} ++ ++void CamOsSetTimeOfDay(const CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTimespec_t tCurr = {0}; ++ if(ptRes) ++ { ++ // Calculate time offset ++ CamOsGetMonotonicTime(&tCurr); ++ _gTimeOfDayOffsetSec = ptRes->nSec - tCurr.nSec; ++ _gTimeOfDayOffsetNanoSec = ptRes->nNanoSec - tCurr.nNanoSec; ++ ++ // Save time to RTC ++ DrvRtcInit(); ++ DrvRtcSetSecondCount(ptRes->nSec); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ struct timeval tTV; ++ if(ptRes) ++ { ++ tTV.tv_sec = ptRes->nSec; ++ tTV.tv_usec = ptRes->nNanoSec / 1000; ++ settimeofday(&tTV, NULL); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct timespec tTs; ++ if(ptRes) ++ { ++ tTs.tv_sec = ptRes->nSec; ++ tTs.tv_nsec = ptRes->nNanoSec; ++ do_settimeofday(&tTs); ++ } ++#endif ++} ++ ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ u64 nTicks = sys_arch_timer_get_counter(); ++ ptRes->nSec = nTicks / sys_arch_timer_get_cntfrq(); ++ ptRes->nNanoSec = (u32)((nTicks % sys_arch_timer_get_cntfrq()) * 1000000000 / sys_arch_timer_get_cntfrq()); ++#elif defined(CAM_OS_LINUX_USER) ++ clock_gettime(CLOCK_MONOTONIC, (struct timespec *)ptRes); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ getrawmonotonic((struct timespec *)ptRes); ++#endif ++} ++ ++s64 CamOsTimeDiff(CamOsTimespec_t *ptStart, CamOsTimespec_t *ptEnd, CamOsTimeDiffUnit_e eUnit) ++{ ++ if (ptStart && ptEnd) ++ { ++ switch (eUnit) ++ { ++ case CAM_OS_TIME_DIFF_SEC: ++ return (s64)ptEnd->nSec - ptStart->nSec; ++ case CAM_OS_TIME_DIFF_MS: ++ return ((s64)ptEnd->nSec - ptStart->nSec)*1000 + ((s64)ptEnd->nNanoSec - ptStart->nNanoSec)/1000000; ++ case CAM_OS_TIME_DIFF_US: ++ return ((s64)ptEnd->nSec - ptStart->nSec)*1000000 + ((s64)ptEnd->nNanoSec - ptStart->nNanoSec)/1000; ++ case CAM_OS_TIME_DIFF_NS: ++ return ((s64)ptEnd->nSec - ptStart->nSec)*1000000000 + ((s64)ptEnd->nNanoSec - ptStart->nNanoSec); ++ default: ++ return 0; ++ } ++ } ++ else ++ return 0; ++} ++ ++#ifdef CAM_OS_RTK ++static void _CamOSThreadEntry(void *pEntryData) ++{ ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)pEntryData; ++ ++ if (ptTaskHandle->pfnEntry) ++ { ++ ptTaskHandle->pfnEntry(ptTaskHandle->pArg); ++ } ++ ++ MsFlagSetbits(&ptTaskHandle->tExitFlag, 0x00000001); ++} ++ ++static void _CamOsThreadEmptyParser(vm_msg_t *ptMessage) ++{ ++ ++} ++#elif defined(CAM_OS_LINUX_USER) ++static void _CamOSThreadEntry(void *pEntryData) ++{ ++ CamOsThreadHandleLinuxUser_t *ptTaskHandle = (CamOsThreadHandleLinuxUser_t *)pEntryData; ++ ++ ptTaskHandle->nPid = CamOsThreadGetID(); ++ CamOsTsemUp(&ptTaskHandle->tEntryIn); ++ ++ if (ptTaskHandle->pfnEntry) ++ { ++ ptTaskHandle->pfnEntry(ptTaskHandle->pArg); ++ } ++} ++#endif ++ ++CamOsRet_e CamOsThreadCreate(CamOsThread *ptThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = NULL; ++ MsTaskCreateArgs_t tTaskArgs = {0}; ++ u32 nPrio = 100; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ ++ if (!nThreadStopBitmapInited) ++ { ++ CAM_OS_BITMAP_CLEAR(aThreadStopBitmap); ++ nThreadStopBitmapInited = 1; ++ } ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority > 0) && (ptAttrb->nPriority < 100)) ++ { ++ nPrio = ptAttrb->nPriority * 2; ++ } ++ nStkSz = (ptAttrb->nStackSize) ? ptAttrb->nStackSize : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ } ++ ++ *ptThread = (void*) - 1; ++ do ++ { ++ if(!(ptTaskHandle = MsCallocateMem(sizeof(CamOsThreadHandleRtk_t)))) ++ { ++ CAM_OS_WARN("alloc handle fail"); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ ptTaskHandle->pfnEntry = pfnStartRoutine; ++ ptTaskHandle->pArg = pArg; ++ if(!(ptTaskHandle->pStack = MsAllocateMem((nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT))) ++ { ++ CAM_OS_WARN("alloc stack fail"); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ memset(&ptTaskHandle->tExitFlag, 0, sizeof(Ms_Flag_t)); ++ MsFlagInit(&ptTaskHandle->tExitFlag); ++ //VEN_TEST_CHECK_RESULT((pTaskHandle->exit_flag.FlagId >> 0) && (pTaskHandle->exit_flag.FlagState == RTK_FLAG_INITIALIZED)); ++ ++ tTaskArgs.Priority = (nPrio >= 0 && nPrio <= 200) ? nPrio : 100; ++ tTaskArgs.StackSize = (nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ tTaskArgs.pStackTop = (u32*)ptTaskHandle->pStack; ++ tTaskArgs.AppliInit = &_CamOSThreadEntry; ++ tTaskArgs.AppliParser = _CamOsThreadEmptyParser; ++ tTaskArgs.pInitArgs = ptTaskHandle; ++ tTaskArgs.TaskId = &ptTaskHandle->eHandleObj; ++ tTaskArgs.ImmediatelyStart = TRUE; ++ tTaskArgs.TimeSliceMax = 10; ++ tTaskArgs.TimeSliceLeft = 10; ++ strncpy(tTaskArgs.TaskName, (ptAttrb && ptAttrb->szName)? ptAttrb->szName : "CamOsWrp", sizeof(tTaskArgs.TaskName)); ++ ++ if(MS_OK != MsCreateTask(&tTaskArgs)) ++ { ++ CAM_OS_WARN("create fail"); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *ptThread = ptTaskHandle; ++ } ++ while(0); ++ ++ if(!*ptThread) ++ { ++ if(ptTaskHandle) ++ { ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsReleaseMemory(ptTaskHandle); ++ } ++ } ++ ++ //CamOsPrintf("%s get taskid: %d(%s) priority: %d\n", __FUNCTION__, (u32)ptTaskHandle->eHandleObj, tTaskArgs.TaskName, tTaskArgs.Priority); ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsThreadHandleLinuxUser_t *ptTaskHandle = NULL; ++ struct sched_param tSched; ++ pthread_attr_t tAttr; ++ s32 nNiceVal = 0; ++ ++ *ptThread = NULL; ++ do ++ { ++ if(!(ptTaskHandle = CamOsMemCalloc(sizeof(CamOsThreadHandleLinuxUser_t), 1))) ++ { ++ CAM_OS_WARN("alloc handle fail"); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ ptTaskHandle->pfnEntry = pfnStartRoutine; ++ ptTaskHandle->pArg = pArg; ++ ptTaskHandle->nPid = 0; ++ CamOsTsemInit(&ptTaskHandle->tEntryIn, 0); ++ ++ if(ptAttrb != NULL) ++ { ++ do ++ { ++ pthread_attr_init(&tAttr); ++ ++ // Set SCHED_RR priority before thread created. ++ if((ptAttrb->nPriority > 70) && (ptAttrb->nPriority <= 100)) ++ { ++ pthread_attr_getschedparam(&tAttr, &tSched); ++ pthread_attr_setinheritsched(&tAttr, PTHREAD_EXPLICIT_SCHED); ++ pthread_attr_setschedpolicy(&tAttr, SCHED_RR); ++ if (ptAttrb->nPriority < 95) // nPriority 71~94 mapping to Linux PrioRT 1~94 ++ tSched.sched_priority = (ptAttrb->nPriority - 71) * 93 / 23 + 1; ++ else // nPriority 95~99 mapping to Linux PrioRT 95~99 ++ tSched.sched_priority = (ptAttrb->nPriority < 100)? ptAttrb->nPriority : 99; ++ if(0 != pthread_attr_setschedparam(&tAttr, &tSched)) ++ { ++ CAM_OS_WARN("set priority fail"); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ } ++ ++ if(0 != ptAttrb->nStackSize) ++ { ++ if(0 != pthread_attr_setstacksize(&tAttr, (size_t) ptAttrb->nStackSize)) ++ { ++ eRet = CAM_OS_FAIL; ++ CAM_OS_WARN("set stack size fail"); ++ break; ++ } ++ } ++ pthread_create(&ptTaskHandle->tThreadHandle, &tAttr, (void *)_CamOSThreadEntry, ptTaskHandle); ++ } ++ while(0); ++ pthread_attr_destroy(&tAttr); ++ } ++ else ++ { ++ pthread_create(&ptTaskHandle->tThreadHandle, NULL, (void *)_CamOSThreadEntry, ptTaskHandle); ++ } ++ ++ if (ptAttrb && ptAttrb->szName) ++ { ++ CamOsThreadSetName((CamOsThread *)ptTaskHandle, ptAttrb->szName); ++ } ++ ++ // Set SCHED_OTHER priority after thread created. ++ if(ptAttrb && (ptAttrb->nPriority > 0) && (ptAttrb->nPriority <= 70)) ++ { ++ if (CamOsTsemTimedDown(&ptTaskHandle->tEntryIn, 1000) == CAM_OS_OK && ptTaskHandle->nPid != 0) ++ { ++ if (ptAttrb->nPriority <= 50) ++ { ++ nNiceVal = 19 - ptAttrb->nPriority * 19 / 50; ++ } ++ else ++ { ++ nNiceVal = 50 - ptAttrb->nPriority; ++ } ++ ++ setpriority(PRIO_PROCESS, ptTaskHandle->nPid, nNiceVal); ++ } ++ else ++ { ++ CAM_OS_WARN("set priority fail"); ++ } ++ } ++ ++ *ptThread = (CamOsThread *)ptTaskHandle; ++ } ++ while(0); ++ ++ if(!*ptThread) ++ { ++ if(ptTaskHandle) ++ { ++ CamOsMemRelease(ptTaskHandle); ++ } ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle; ++ struct sched_param tSched = { .sched_priority = 0 }; ++ s32 nNiceVal = 0; ++ ++ tpThreadHandle = kthread_run((CamOsThreadEntry_t *)pfnStartRoutine, pArg, (ptAttrb && ptAttrb->szName)? ptAttrb->szName : "CAMOS"); ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority > 0) && (ptAttrb->nPriority <= 70)) ++ { ++ if (ptAttrb->nPriority <= 50) ++ { ++ nNiceVal = 19 - ptAttrb->nPriority * 19 / 50; ++ } ++ else ++ { ++ nNiceVal = 50 - ptAttrb->nPriority; ++ } ++ ++ set_user_nice(tpThreadHandle, nNiceVal); ++ } ++ else if((ptAttrb->nPriority > 70) && (ptAttrb->nPriority <= 100)) ++ { ++ if (ptAttrb->nPriority < 95) // nPriority 71~94 mapping to Linux PrioRT 1~94 ++ tSched.sched_priority = (ptAttrb->nPriority - 71) * 93 / 23 + 1; ++ else // nPriority 95~99 mapping to Linux PrioRT 95~99 ++ tSched.sched_priority = (ptAttrb->nPriority < 100)? ptAttrb->nPriority : 99; ++ if(sched_setscheduler(tpThreadHandle, SCHED_RR, &tSched) != 0) ++ { ++ CAM_OS_WARN("set priority fail"); ++ } ++ } ++ } ++ ++ *ptThread = (CamOsThread *)tpThreadHandle; ++#endif ++ ++ // coverity[leaked_storage] ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadChangePriority(CamOsThread tThread, u32 nPriority) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)tThread; ++ u32 nPrio = 100; ++ if(ptTaskHandle) ++ { ++ if(nPriority > 0 && nPriority < 100) ++ { ++ nPrio = nPriority * 2; ++ } ++ MsChangeTaskPriority(ptTaskHandle->eHandleObj, (nPrio >= 0 && nPrio <= 200) ? nPrio : 100); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsThreadHandleLinuxUser_t *ptTaskHandle = (CamOsThreadHandleLinuxUser_t *)tThread; ++ struct sched_param tSched = { .sched_priority = 0 }; ++ s32 nNiceVal = 0; ++ ++ if(ptTaskHandle && (nPriority >= 0) && (nPriority <= 70)) ++ { ++ nPriority = nPriority? nPriority : 50; ++ if (nPriority <= 50) ++ { ++ nNiceVal = 19 - nPriority * 19 / 50; ++ } ++ else ++ { ++ nNiceVal = 50 - nPriority; ++ } ++ ++ setpriority(PRIO_PROCESS, ptTaskHandle->nPid, nNiceVal); ++ tSched.sched_priority = 0; ++ if(pthread_setschedparam(ptTaskHandle->tThreadHandle, SCHED_OTHER, &tSched) != 0) ++ { ++ CAM_OS_WARN("set priority fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else if(ptTaskHandle && (nPriority > 70) && (nPriority <= 100)) ++ { ++ if (nPriority < 95) // nPriority 71~94 mapping to Linux PrioRT 1~94 ++ tSched.sched_priority = (nPriority - 71) * 93 / 23 + 1; ++ else // nPriority 95~99 mapping to Linux PrioRT 95~99 ++ tSched.sched_priority = (nPriority < 100)? nPriority : 99; ++ if(pthread_setschedparam(ptTaskHandle->tThreadHandle, SCHED_RR, &tSched) != 0) ++ { ++ CAM_OS_WARN("set priority fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle = (struct task_struct *)tThread; ++ struct sched_param tSched = { .sched_priority = 0 }; ++ s32 nNiceVal = 0; ++ ++ if(tpThreadHandle && (nPriority >= 0) && (nPriority <= 70)) ++ { ++ nPriority = nPriority? nPriority : 50; ++ if (nPriority <= 50) ++ { ++ nNiceVal = 19 - nPriority * 19 / 50; ++ } ++ else ++ { ++ nNiceVal = 50 - nPriority; ++ } ++ ++ set_user_nice(tpThreadHandle, nNiceVal); ++ tSched.sched_priority = 0; ++ if(sched_setscheduler(tpThreadHandle, SCHED_NORMAL, &tSched) != 0) ++ { ++ CAM_OS_WARN("set priority fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else if(tpThreadHandle && (nPriority > 70) && (nPriority <= 100)) ++ { ++ if (nPriority < 95) // nPriority 71~94 mapping to Linux PrioRT 1~94 ++ tSched.sched_priority = (nPriority - 71) * 93 / 23 + 1; ++ else // nPriority 95~99 mapping to Linux PrioRT 95~99 ++ tSched.sched_priority = (nPriority < 100)? nPriority : 99; ++ if(sched_setscheduler(tpThreadHandle, SCHED_RR, &tSched) != 0) ++ { ++ CAM_OS_WARN("set priority fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadSchedule(u8 bInterruptible, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ if(nMsec == CAM_OS_MAX_TIMEOUT) ++ { ++ // Avoid u32 overflow, put nMsec to MsSleep without convert ++ if(CAM_OS_OK != MsSleep(nMsec)) ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else if(nMsec > 0) ++ { ++ if(CAM_OS_OK != MsSleep(RTK_MS_TO_TICK(nMsec))) ++ eRet = CAM_OS_TIMEOUT; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(nMsec == CAM_OS_MAX_TIMEOUT) ++ { ++ if(bInterruptible) ++ set_current_state(TASK_INTERRUPTIBLE); ++ else ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ ++ schedule(); ++ } ++ else if(nMsec > 0) ++ { ++ if(bInterruptible) ++ { ++ if(0 == schedule_timeout(msecs_to_jiffies(nMsec) + 1)) ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else ++ { ++ schedule_timeout_uninterruptible(msecs_to_jiffies(nMsec) + 1); ++ } ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadWakeUp(CamOsThread tThread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)tThread; ++ if(ptTaskHandle) ++ { ++ RtkWakeUpTask(ptTaskHandle->eHandleObj); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle = (struct task_struct *)tThread; ++ if(tpThreadHandle) ++ { ++ wake_up_process(tpThreadHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadJoin(CamOsThread tThread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)tThread; ++ if(ptTaskHandle) ++ { ++ MsFlagWait(&ptTaskHandle->tExitFlag, 0x00000001, RTK_FLAG_WAITMODE_AND | RTK_FLAG_WAITMODE_CLR); ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsDeleteTask(ptTaskHandle->eHandleObj); ++ ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsReleaseMemory(ptTaskHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsThreadHandleLinuxUser_t *ptTaskHandle = (CamOsThreadHandleLinuxUser_t *)tThread; ++ if(ptTaskHandle) ++ { ++ if(ptTaskHandle->tThreadHandle) ++ { ++ pthread_join(ptTaskHandle->tThreadHandle, NULL); ++ } ++ CamOsMemRelease(ptTaskHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadStop(CamOsThread tThread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)tThread; ++ if(ptTaskHandle) ++ { ++ MsTaskId_e eHandleObj = ptTaskHandle->eHandleObj; ++ CAM_OS_SET_BIT(ptTaskHandle->eHandleObj, aThreadStopBitmap); ++ CamOsThreadJoin(tThread); ++ CAM_OS_CLEAR_BIT(eHandleObj, aThreadStopBitmap); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle = (struct task_struct *)tThread; ++ s32 nErr; ++ if(tpThreadHandle) ++ { ++ if(0 != (nErr = kthread_stop(tpThreadHandle))) ++ { ++ CAM_OS_WARN("stop fail"); ++ CamOsPrintf("%s Err=%d\n", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadShouldStop(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ if (!CAM_OS_TEST_BIT(MsCurrTask(), aThreadStopBitmap)) ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(kthread_should_stop()) ++ { ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_FAIL; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadSetName(CamOsThread tThread, const char *szName) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)tThread; ++ if(ptTaskHandle && szName) ++ { ++ MsSetTaskName(ptTaskHandle->eHandleObj, szName); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsThreadHandleLinuxUser_t *ptTaskHandle = (CamOsThreadHandleLinuxUser_t *)tThread; ++ if(ptTaskHandle && ptTaskHandle->tThreadHandle) ++ { ++ if(strlen(szName) >= 16) // Linux limitation ++ return CAM_OS_PARAM_ERR; ++#if defined(__GLIBC__) && defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 12) ++ if(pthread_setname_np(ptTaskHandle->tThreadHandle, szName) != 0) ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#else ++ if(ptTaskHandle->tThreadHandle == pthread_self()) ++ { ++ if(prctl(PR_SET_NAME, szName) != 0) ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ else ++ { ++ CAM_OS_WARN("not support set by other thread (in uclibc?)"); ++ } ++#endif ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadGetName(CamOsThread tThread, char *szName, u32 nLen) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)tThread; ++ if(ptTaskHandle && szName) ++ { ++ MsGetTaskName(ptTaskHandle->eHandleObj, szName, nLen); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsThreadHandleLinuxUser_t *ptTaskHandle = (CamOsThreadHandleLinuxUser_t *)tThread; ++ if(ptTaskHandle && ptTaskHandle->tThreadHandle) ++ { ++ if(nLen < 16) // Linux limitation ++ return CAM_OS_PARAM_ERR; ++#if defined(__GLIBC__) && defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 12) ++ if(pthread_getname_np(ptTaskHandle->tThreadHandle, szName, nLen) != 0) ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#else ++ if(ptTaskHandle->tThreadHandle == pthread_self()) ++ { ++ if(prctl(PR_GET_NAME, szName) != 0) ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ else ++ { ++ CAM_OS_WARN("not support set by other thread (in uclibc?)"); ++ } ++#endif ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#endif ++ return eRet; ++} ++ ++u32 CamOsThreadGetID() ++{ ++#ifdef CAM_OS_RTK ++ return MsCurrTask(); ++#elif defined(CAM_OS_LINUX_USER) ++ return (u32)syscall(__NR_gettid); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return current->tgid; ++#endif ++} ++ ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsMutexRtk_t *ptHandle = (CamOsMutexRtk_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ MsMutexLock(&_gtSelfInitLock); ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ if(CUS_OS_OK != MsInitMutex(&ptHandle->tMutex)) ++ { ++ CAM_OS_WARN("init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ MsMutexUnlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsMutexLU_t *ptHandle = (CamOsMutexLU_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ pthread_mutex_lock(&_gtSelfInitLock); ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ if(0 != pthread_mutex_init(&ptHandle->tMutex, NULL)) ++ { ++ CAM_OS_WARN("init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ pthread_mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMutexLK_t *ptHandle = (CamOsMutexLK_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ mutex_lock(&_gtSelfInitLock); ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ mutex_init(&ptHandle->tMutex); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsMutexRtk_t *ptHandle = (CamOsMutexRtk_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsMutexLU_t *ptHandle = (CamOsMutexLU_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ pthread_mutex_destroy(&ptHandle->tMutex); ++ ptHandle->nInited = 0; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMutexLK_t *ptHandle = (CamOsMutexLK_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsMutexRtk_t *ptHandle = (CamOsMutexRtk_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(CUS_OS_OK != MsMutexLock(&ptHandle->tMutex)) ++ { ++ CAM_OS_WARN("lock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ CamOsMutexLU_t *ptHandle = (CamOsMutexLU_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(0 != (nErr = pthread_mutex_lock(&ptHandle->tMutex))) ++ { ++ CAM_OS_WARN("lock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMutexLK_t *ptHandle = (CamOsMutexLK_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ mutex_lock(&ptHandle->tMutex); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexTryLock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsMutexRtk_t *ptHandle = (CamOsMutexRtk_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(CUS_OS_UNIT_NOAVAIL == MsMutexTryLock(&ptHandle->tMutex)) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ CamOsMutexLU_t *ptHandle = (CamOsMutexLU_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(0 != (nErr = pthread_mutex_trylock(&ptHandle->tMutex))) ++ { ++ if(nErr == EAGAIN) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ else ++ { ++ CAM_OS_WARN("lock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMutexLK_t *ptHandle = (CamOsMutexLK_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(0 != mutex_trylock(&ptHandle->tMutex)) ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsMutexRtk_t *ptHandle = (CamOsMutexRtk_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(CUS_OS_OK != MsMutexUnlock(&ptHandle->tMutex)) ++ { ++ CAM_OS_WARN("unlock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ CamOsMutexLU_t *ptHandle = (CamOsMutexLU_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ if(0 != (nErr = pthread_mutex_unlock(&ptHandle->tMutex))) ++ { ++ CAM_OS_WARN("unlock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMutexLK_t *ptHandle = (CamOsMutexLK_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsMutexInit(ptMutex); ++ } ++ ++ mutex_unlock(&ptHandle->tMutex); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ MsMutexLock(&_gtSelfInitLock); ++ ++ if(CUS_OS_OK != MsCreateDynSemExtend(&ptHandle->Tsem, CAM_OS_MAX_INT - 1, nVal)) ++ { ++ CAM_OS_WARN("init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ MsMutexUnlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ pthread_mutex_lock(&_gtSelfInitLock); ++ ++ if(0 != sem_init(&ptHandle->tSem, 1, nVal)) ++ { ++ CAM_OS_WARN("init fail"); ++ CamOsPrintf("err: %d\n", errno); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ pthread_mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ mutex_lock(&_gtSelfInitLock); ++ ++ sema_init(&ptHandle->tSem, nVal); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ MsDestroyDynSem(&ptHandle->Tsem); ++ ptHandle->nInited = 0; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(0 != sem_destroy(&ptHandle->tSem)) ++ { ++ ptHandle->nInited = 0; ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemUp(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsProduceDynSem(&ptHandle->Tsem); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ sem_post(&ptHandle->tSem); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemDown(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsConsumeDynSem(&ptHandle->Tsem); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ sem_wait(&ptHandle->tSem); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ down(&ptHandle->tSem); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemDownInterruptible(CamOsTsem_t *ptTsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ MsConsumeDynSem(&ptHandle->Tsem); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ sem_wait(&ptHandle->tSem); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ if(-EINTR == down_interruptible(&ptHandle->tSem)) ++ { ++ eRet = CAM_OS_INTERRUPTED; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(CUS_OS_NO_MESSAGE == MsConsumeDynSemDelay(&ptHandle->Tsem, RTK_MS_TO_TICK(nMsec))) ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ struct timespec tFinalTime; ++ s64 nNanoDelay = 0; ++ ++ if(ptHandle) ++ { ++ if(clock_gettime(CLOCK_REALTIME, &tFinalTime) == -1) ++ CAM_OS_WARN("clock_gettime fail"); ++ ++ nNanoDelay = (nMsec * 1000000LL) + tFinalTime.tv_nsec; ++ tFinalTime.tv_sec += (nNanoDelay / 1000000000LL); ++ tFinalTime.tv_nsec = nNanoDelay % 1000000000LL; ++ ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(0 != sem_timedwait(&ptHandle->tSem, &tFinalTime)) ++ { ++ if(errno == ETIMEDOUT) ++ { ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else ++ { ++ CAM_OS_WARN("down fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(0 != down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec))) ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemTryDown(CamOsTsem_t *ptTsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(CUS_OS_UNIT_NOAVAIL == MsPollDynSem(&ptHandle->Tsem)) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(0 != sem_trywait(&ptHandle->tSem)) ++ { ++ if(errno == EAGAIN) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ else ++ { ++ CAM_OS_WARN("down fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(0 != (nErr = down_trylock(&ptHandle->tSem))) ++ { ++ CAM_OS_WARN("down fail"); ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsRwsemInit(CamOsRwsem_t *ptRwsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ if(CUS_OS_OK != MsInitMutex(&ptHandle->tRMutex) || ++ CUS_OS_OK != MsCreateDynSem(&ptHandle->WTsem, 1)) ++ { ++ CAM_OS_WARN("init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ ptHandle->nReadCount = 0; ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ pthread_mutex_lock(&_gtSelfInitLock); ++ ++ if(0 != pthread_rwlock_init(&ptHandle->tRwsem, NULL)) ++ { ++ CAM_OS_WARN("init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ pthread_mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ mutex_lock(&_gtSelfInitLock); ++ ++ init_rwsem(&ptHandle->tRwsem); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsRwsemDeinit(CamOsRwsem_t *ptRwsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ MsDestroyDynSem(&ptHandle->WTsem); ++ ptHandle->nInited = 0; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(0 != pthread_rwlock_destroy(&ptHandle->tRwsem)) ++ { ++ ptHandle->nInited = 0; ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsRwsemUpRead(CamOsRwsem_t *ptRwsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ MsMutexLock(&ptHandle->tRMutex); ++ ptHandle->nReadCount--; ++ if(ptHandle->nReadCount == 0) ++ MsProduceDynSem(&ptHandle->WTsem); ++ MsMutexUnlock(&ptHandle->tRMutex); ++ } ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ pthread_rwlock_unlock(&ptHandle->tRwsem); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ up_read(&ptHandle->tRwsem); ++ } ++#endif ++} ++ ++void CamOsRwsemUpWrite(CamOsRwsem_t *ptRwsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsProduceDynSem(&ptHandle->WTsem); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ pthread_rwlock_unlock(&ptHandle->tRwsem); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ up_write(&ptHandle->tRwsem); ++ } ++#endif ++} ++ ++void CamOsRwsemDownRead(CamOsRwsem_t *ptRwsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ MsMutexLock(&ptHandle->tRMutex); ++ ptHandle->nReadCount++; ++ if(ptHandle->nReadCount == 1) ++ MsConsumeDynSem(&ptHandle->WTsem); ++ MsMutexUnlock(&ptHandle->tRMutex); ++ } ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ pthread_rwlock_rdlock(&ptHandle->tRwsem); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ down_read(&ptHandle->tRwsem); ++ } ++#endif ++} ++ ++void CamOsRwsemDownWrite(CamOsRwsem_t *ptRwsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsConsumeDynSem(&ptHandle->WTsem); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ pthread_rwlock_wrlock(&ptHandle->tRwsem); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ down_write(&ptHandle->tRwsem); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsRwsemTryDownRead(CamOsRwsem_t *ptRwsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else if(CUS_OS_UNIT_NOAVAIL == MsMutexTryLock(&ptHandle->tRMutex)) ++ eRet = CAM_OS_RESOURCE_BUSY; ++ else ++ { ++ ptHandle->nReadCount++; ++ if(ptHandle->nReadCount == 1) ++ { ++ if(CUS_OS_UNIT_NOAVAIL == MsPollDynSem(&ptHandle->WTsem)) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ ptHandle->nReadCount--; ++ } ++ } ++ MsMutexUnlock(&ptHandle->tRMutex); ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ s32 nErr; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else if(0 != (nErr = pthread_rwlock_tryrdlock(&ptHandle->tRwsem))) ++ { ++ if(nErr == EBUSY) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ else ++ { ++ CAM_OS_WARN("lock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ s32 nErr; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else if(1 != (nErr = down_read_trylock(&ptHandle->tRwsem))) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsRwsemTryDownWrite(CamOsRwsem_t *ptRwsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsRwsemRtk_t *ptHandle = (CamOsRwsemRtk_t *)ptRwsem; ++ ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else if(CUS_OS_UNIT_NOAVAIL == MsPollDynSem(&ptHandle->WTsem)) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsRwsemLU_t *ptHandle = (CamOsRwsemLU_t *)ptRwsem; ++ s32 nErr; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else if(0 != (nErr = pthread_rwlock_trywrlock(&ptHandle->tRwsem))) ++ { ++ if(nErr == EBUSY) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ else ++ { ++ CAM_OS_WARN("lock fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsRwsemLK_t *ptHandle = (CamOsRwsemLK_t *)ptRwsem; ++ s32 nErr; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else if(1 != (nErr = down_write_trylock(&ptHandle->tRwsem))) ++ { ++ eRet = CAM_OS_RESOURCE_BUSY; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTcondInit(CamOsTcond_t *ptTcond) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ MsMutexLock(&_gtSelfInitLock); ++ ++ if(CUS_OS_OK != MsCreateDynSem(&ptHandle->Tsem, 0)) ++ { ++ CAM_OS_WARN("create fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ MsMutexUnlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondLU_t *ptHandle = (CamOsTcondLU_t *)ptTcond; ++ pthread_condattr_t cattr; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ pthread_mutex_lock(&_gtSelfInitLock); ++ ++ if(0 != pthread_condattr_init(&cattr) || ++ 0 != pthread_condattr_setclock(&cattr, CLOCK_MONOTONIC)) ++ { ++ CAM_OS_WARN("pthread_condattr_init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ ++ if(0 != pthread_cond_init(&ptHandle->tCondition, &cattr)) ++ { ++ CAM_OS_WARN("pthread_cond_init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ if(0 != pthread_mutex_init(&ptHandle->tMutex, NULL)) ++ { ++ CAM_OS_WARN("pthread_mutex_init fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ pthread_mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ mutex_lock(&_gtSelfInitLock); ++ ++ init_completion(&ptHandle->tCompletion); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ ++ mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTcondDeinit(CamOsTcond_t *ptTcond) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ MsDestroyDynSem(&ptHandle->Tsem); ++ ptHandle->nInited = 0; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondLU_t *ptHandle = (CamOsTcondLU_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ pthread_cond_destroy(&ptHandle->tCondition); ++ pthread_mutex_destroy(&ptHandle->tMutex); ++ ptHandle->nInited = 0; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ ptHandle->nInited = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTcondSignal(CamOsTcond_t *ptTcond) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsProduceSafeDynSem(&ptHandle->Tsem, 0); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondLU_t *ptHandle = (CamOsTcondLU_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ complete(&ptHandle->tCompletion); ++ } ++#endif ++} ++ ++void CamOsTcondSignalAll(CamOsTcond_t *ptTcond) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsProduceSafeDynSem(&ptHandle->Tsem, 1); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondLU_t *ptHandle = (CamOsTcondLU_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_broadcast(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ complete_all(&ptHandle->tCompletion); ++ } ++ } ++#endif ++} ++ ++void CamOsTcondWait(CamOsTcond_t *ptTcond) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ MsConsumeAllDynSem(&ptHandle->Tsem); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondLU_t *ptHandle = (CamOsTcondLU_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ CAM_OS_WARN("not inited"); ++ else ++ { ++ reinit_completion(&ptHandle->tCompletion); ++ wait_for_completion(&ptHandle->tCompletion); ++ } ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTcondTimedWait(CamOsTcond_t *ptTcond, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else if(CUS_OS_NO_MESSAGE == MsConsumeAllDynSemDelay(&ptHandle->Tsem, RTK_MS_TO_TICK(nMsec))) ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondLU_t *ptHandle = (CamOsTcondLU_t *)ptTcond; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ s64 nNanoDelay = 0; ++ ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ if(clock_gettime(CLOCK_MONOTONIC, &tFinalTime) == -1) ++ CAM_OS_WARN("clock_gettime fail"); ++ ++ nNanoDelay = (nMsec * 1000000LL) + tFinalTime.tv_nsec; ++ tFinalTime.tv_sec += (nNanoDelay / 1000000000LL); ++ tFinalTime.tv_nsec = nNanoDelay % 1000000000LL; ++ ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ { ++ eRet = CAM_OS_OK; ++ } ++ else if(nErr == ETIMEDOUT) ++ { ++ eRet = CAM_OS_TIMEOUT; ++ } ++ else ++ { ++ CAM_OS_WARN("pthread_cond_timedwait fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ reinit_completion(&ptHandle->tCompletion); ++ if(!wait_for_completion_timeout(&ptHandle->tCompletion, msecs_to_jiffies(nMsec))) ++ { ++ eRet = CAM_OS_TIMEOUT; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTcondWaitInterruptible(CamOsTcond_t *ptTcond) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTcondWait(ptTcond); ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTcondWait(ptTcond); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ reinit_completion(&ptHandle->tCompletion); ++ if (-ERESTARTSYS == wait_for_completion_interruptible(&ptHandle->tCompletion)) ++ eRet = CAM_OS_INTERRUPTED; ++ } ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTcondTimedWaitInterruptible(CamOsTcond_t *ptTcond, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ eRet = CamOsTcondTimedWait(ptTcond, nMsec); ++#elif defined(CAM_OS_LINUX_USER) ++ eRet = CamOsTcondTimedWait(ptTcond, nMsec); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ s32 nWaitRet; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ reinit_completion(&ptHandle->tCompletion); ++ nWaitRet = wait_for_completion_interruptible_timeout(&ptHandle->tCompletion, msecs_to_jiffies(nMsec)); ++ if (nWaitRet == -ERESTARTSYS) ++ { ++ eRet = CAM_OS_INTERRUPTED; ++ } ++ else if (nWaitRet == 0) ++ { ++ eRet = CAM_OS_TIMEOUT; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTcondWaitActive(CamOsTcond_t *ptTcond) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTcondRtk_t *ptHandle = (CamOsTcondRtk_t *)ptTcond; ++ s16 nSemCount; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ if(CUS_OS_OK == MsGetDynSemCount(&ptHandle->Tsem, &nSemCount)) ++ { ++ if(nSemCount == 0) ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTcondLK_t *ptHandle = (CamOsTcondLK_t *)ptTcond; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("not inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ if(!completion_done(&ptHandle->tCompletion)) ++ { ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsSpinInit(CamOsSpinlock_t *ptSpinlock) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsSpinlockRtk_t *ptHandle = (CamOsSpinlockRtk_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ ptHandle->nFlags = 0; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsSpinlockLU_t *ptHandle = (CamOsSpinlockLU_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ pthread_mutex_lock(&_gtSelfInitLock); ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ pthread_spin_init(&ptHandle->tLock, 0); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ pthread_mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsSpinlockLK_t *ptHandle = (CamOsSpinlockLK_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ if (CamOsInInterrupt() != CAM_OS_OK) ++ { ++ mutex_lock(&_gtSelfInitLock); ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ spin_lock_init(&ptHandle->tLock); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ mutex_unlock(&_gtSelfInitLock); ++ } ++ else ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ spin_lock_init(&ptHandle->tLock); ++ ptHandle->nInited = INIT_MAGIC_NUM; ++ } ++ } ++ } ++ else ++ { ++ CAM_OS_WARN("already inited"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsSpinLock(CamOsSpinlock_t *ptSpinlock) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsSpinlockRtk_t *ptHandle = (CamOsSpinlockRtk_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ RtkEnterRegion(); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsSpinlockLU_t *ptHandle = (CamOsSpinlockLU_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsSpinInit(ptSpinlock); ++ } ++ ++ pthread_spin_lock(&ptHandle->tLock); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsSpinlockLK_t *ptHandle = (CamOsSpinlockLK_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsSpinInit(ptSpinlock); ++ } ++ ++ spin_lock(&ptHandle->tLock); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsSpinUnlock(CamOsSpinlock_t *ptSpinlock) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsSpinlockRtk_t *ptHandle = (CamOsSpinlockRtk_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ RtkLeaveRegion(); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsSpinlockLU_t *ptHandle = (CamOsSpinlockLU_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsSpinInit(ptSpinlock); ++ } ++ ++ pthread_spin_unlock(&ptHandle->tLock); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsSpinlockLK_t *ptHandle = (CamOsSpinlockLK_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsSpinInit(ptSpinlock); ++ } ++ ++ spin_unlock(&ptHandle->tLock); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsSpinLockIrqSave(CamOsSpinlock_t *ptSpinlock) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsSpinlockRtk_t *ptHandle = (CamOsSpinlockRtk_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ RtkEnterRegionSaveIrq(&ptHandle->nFlags); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsSpinlockLK_t *ptHandle = (CamOsSpinlockLK_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsSpinInit(ptSpinlock); ++ } ++ ++ spin_lock_irqsave(&ptHandle->tLock, ptHandle->nFlags); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsSpinUnlockIrqRestore(CamOsSpinlock_t *ptSpinlock) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsSpinlockRtk_t *ptHandle = (CamOsSpinlockRtk_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ RtkLeaveRegionRestoreIrq(&ptHandle->nFlags); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsSpinlockLK_t *ptHandle = (CamOsSpinlockLK_t *)ptSpinlock; ++ if(ptHandle) ++ { ++ if(ptHandle->nInited != INIT_MAGIC_NUM) ++ { ++ CamOsSpinInit(ptSpinlock); ++ } ++ ++ spin_unlock_irqrestore(&ptHandle->tLock, ptHandle->nFlags); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void* CamOsMemAlloc(u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsGetHeapMemory(nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return malloc(nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if (nSize > KMALLOC_THRESHOLD_SIZE) ++ return vzalloc(nSize); ++ else ++ return kzalloc(nSize, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemAllocAtomic(u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsGetCHeapMemory(nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return malloc(nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if (nSize > KMALLOC_THRESHOLD_SIZE) ++ return NULL; ++ else ++ return kzalloc(nSize, GFP_ATOMIC); ++#endif ++} ++ ++void* CamOsMemCalloc(u32 nNum, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsGetCHeapMemory(nNum * nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return calloc(nNum, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if ((nNum * nSize) > KMALLOC_THRESHOLD_SIZE) ++ return vzalloc(nNum * nSize); ++ else ++ return kzalloc(nNum * nSize, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemCallocAtomic(u32 nNum, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsGetCHeapMemory(nNum * nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return calloc(nNum, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if ((nNum * nSize) > KMALLOC_THRESHOLD_SIZE) ++ return NULL; ++ else ++ return kzalloc(nNum * nSize, GFP_ATOMIC); ++#endif ++} ++ ++void* CamOsMemRealloc(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsHeapRealloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return realloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ void *pAddr; ++ ++ if (nSize > KMALLOC_THRESHOLD_SIZE) ++ pAddr = vzalloc(nSize); ++ else ++ pAddr = kzalloc(nSize, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ ++ if(pPtr && pAddr) ++ { ++ memcpy(pAddr, pPtr, nSize); ++ kvfree(pPtr); ++ } ++ return pAddr; ++#endif ++} ++ ++void* CamOsMemReallocAtomic(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsHeapRealloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return realloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ void *pAddr; ++ ++ if (nSize > KMALLOC_THRESHOLD_SIZE) ++ pAddr = NULL; ++ else ++ pAddr = kzalloc(nSize, GFP_ATOMIC); ++ ++ if(pPtr && pAddr) ++ { ++ memcpy(pAddr, pPtr, nSize); ++ kvfree(pPtr); ++ } ++ return pAddr; ++#endif ++} ++ ++void CamOsMemRelease(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ if(pPtr) ++ { ++ MsReleaseMemory(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(pPtr) ++ { ++ free(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(pPtr) ++ { ++ kvfree(pPtr); ++ } ++#endif ++} ++ ++void CamOsMemFlush(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ sys_flush_data_cache_buffer((u32)pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement cache flush in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ Chip_Flush_Cache_Range((unsigned long)pPtr, nSize); ++#endif ++} ++ ++void CamOsMemFlushExt(void* pVa, void* pPA, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement cache flush in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ Chip_Flush_Cache_Range_VA_PA((unsigned long)pVa, (unsigned long)pPA, nSize); ++#endif ++} ++ ++void CamOsMemInvalidate(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ sys_Invalidate_data_cache_buffer((u32)pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement cache flush in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ Chip_Inv_Cache_Range((unsigned long)pPtr, nSize); ++#endif ++} ++ ++void CamOsMiuPipeFlush(void) ++{ ++#ifdef CAM_OS_RTK ++ DrvChipFlushMiuPipe(); ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ Chip_Flush_MIU_Pipe(); ++#endif ++} ++ ++static s32 _CheckDmemInfoListInited(void) ++{ ++#ifdef CAM_OS_RTK ++ MsMutexLock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_lock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ mutex_lock(&_gtMemLock); ++#endif ++ if(!_gnDmemDbgListInited) ++ { ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#ifdef CAM_OS_RTK ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_unlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ mutex_unlock(&_gtMemLock); ++#endif ++ ++ return 0; ++} ++ ++// Porting from stdint.h for Linux user space ++#ifdef CAM_OS_LINUX_USER ++/* ++ * GCC doesn't provide an appropriate macro for [u]intptr_t ++ * For now, use __PTRDIFF_TYPE__ ++ */ ++#if defined(__PTRDIFF_TYPE__) ++typedef signed __PTRDIFF_TYPE__ intptr_t; ++typedef unsigned __PTRDIFF_TYPE__ uintptr_t; ++#else ++/* ++ * Fallback to hardcoded values, ++ * should be valid on cpu's with 32bit int/32bit void* ++ */ ++typedef signed long intptr_t; ++typedef unsigned long uintptr_t; ++#endif ++#endif ++ ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppVirtPtr, ++ void** ppPhysPtr, ++ void** ppMiuPtr) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ u8 nAllocSucc = TRUE; ++ void *pNonCachePtr = NULL; ++ ++ pNonCachePtr = MsAllocateNonCacheMemExt(nSize, 12); ++ nAllocSucc &= MsIsHeapMemory(pNonCachePtr); ++ ++ if((u32)pNonCachePtr & ((1 << 6) - 1)) ++ { ++ nAllocSucc &= FALSE; ++ MsReleaseMemory(pNonCachePtr); ++ } ++ ++ if(nAllocSucc == TRUE) ++ { ++ ASSIGN_POINTER_VALUE(ppVirtPtr, pNonCachePtr); ++ ASSIGN_POINTER_VALUE(ppPhysPtr, MsVA2PA(pNonCachePtr)); ++ ASSIGN_POINTER_VALUE(ppMiuPtr, (void *)HalUtilPHY2MIUAddr((u32)*ppPhysPtr)); ++ ++ /*CamOsPrintf("%s 0x%08X 0x%08X 0x%08X\n", ++ __FUNCTION__, ++ (u32)*ppVirtPtr, ++ (u32)*ppPhysPtr, ++ (u32)*ppMiuPtr);*/ ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ MemoryList_t* ptNewEntry = (MemoryList_t*) MsAllocateMem(sizeof(MemoryList_t)); ++ ptNewEntry->pPhysPtr = *ppPhysPtr; ++ ptNewEntry->pVirtPtr = *ppVirtPtr; ++ ptNewEntry->pMemifoPtr = NULL; ++ ptNewEntry->szName = (char *)MsAllocateMem(strlen(szName) + 1); ++ if(ptNewEntry->szName) ++ strncpy(ptNewEntry->szName, szName, strlen(szName)); ++ ptNewEntry->nSize = nSize; ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ MsMutexUnlock(&_gtMemLock); ++ } ++ else ++ { ++ ASSIGN_POINTER_VALUE(ppVirtPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppPhysPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppMiuPtr, NULL); ++ eRet = CAM_OS_FAIL; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++#ifndef NO_MDRV_MSYS ++ s32 nMsysFd = -1; ++ s32 nMemFd = -1; ++ MSYS_DMEM_INFO * ptMsysMem = NULL; ++ unsigned char* pMmapPtr = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr && ptTmp->pVirtPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ fprintf(stderr, "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ ASSIGN_POINTER_VALUE(ppVirtPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppPhysPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppMiuPtr, NULL); ++ break; ++ } ++ ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/mem failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ ptMsysMem = (MSYS_DMEM_INFO *) malloc(sizeof(MSYS_DMEM_INFO)); ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ FILL_VERCHK_TYPE(*ptMsysMem, ptMsysMem->VerChk_Version, ++ ptMsysMem->VerChk_Size, IOCTL_MSYS_VERSION); ++ ++ ptMsysMem->length = nSize; ++ snprintf(ptMsysMem->name, sizeof(ptMsysMem->name), "%s", szName); ++ ++ if(ioctl(nMsysFd, IOCTL_MSYS_REQUEST_DMEM, ptMsysMem)) ++ { ++ ptMsysMem->length = 0; ++ fprintf(stderr, "%s [%s][%d]Request Direct Memory Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(ptMsysMem->length < nSize) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s [%s]Request Direct Memory Failed!! because dmem size <%d>smaller than <%d>\n", ++ __FUNCTION__, szName, ptMsysMem->length, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ tAddrInfo.addr = ptMsysMem->phys; ++ ASSIGN_POINTER_VALUE(ppPhysPtr, (void *)(uintptr_t)ptMsysMem->phys); ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s [%s][%d]IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ASSIGN_POINTER_VALUE(ppMiuPtr, (void *)(uintptr_t)tAddrInfo.addr); ++ pMmapPtr = mmap(0, ptMsysMem->length, PROT_READ | PROT_WRITE, MAP_SHARED, ++ nMemFd, ptMsysMem->phys); ++ if(pMmapPtr == (void *) - 1) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s failed!! physAddr<0x%x> size<0x%x> errno<%d, %s> \n", ++ __FUNCTION__, ++ (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length, errno, strerror(errno)); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ASSIGN_POINTER_VALUE(ppVirtPtr, pMmapPtr); ++ ++ fprintf(stderr, "%s <%s> physAddr<0x%x> size<%d>\n", ++ __FUNCTION__, ++ szName, (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ MemoryList_t* ptNewEntry = (MemoryList_t*) malloc(sizeof(MemoryList_t)); ++ ptNewEntry->pPhysPtr = *ppPhysPtr; ++ ptNewEntry->pVirtPtr = *ppVirtPtr; ++ ptNewEntry->pMemifoPtr = (void *) ptMsysMem; ++ ptNewEntry->szName = strdup(szName); ++ ptNewEntry->nSize = ptMsysMem->length; ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++ if(nMemFd >= 0) ++ { ++ close(nMemFd); ++ } ++#else ++ _CheckDmemInfoListInited(); ++#endif ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *ptDmem = NULL; ++ MemoryList_t* ptNewEntry = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ ASSIGN_POINTER_VALUE(ppVirtPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppPhysPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppMiuPtr, NULL); ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr && ptTmp->pVirtPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ printk(KERN_WARNING "%s name conflict: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ ASSIGN_POINTER_VALUE(ppVirtPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppPhysPtr, NULL); ++ ASSIGN_POINTER_VALUE(ppMiuPtr, NULL); ++ break; ++ } ++ ++ if(0 == (ptDmem = (MSYS_DMEM_INFO *)kzalloc(sizeof(MSYS_DMEM_INFO), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s alloc DMEM INFO fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ snprintf(ptDmem->name, 15, szName); ++ ptDmem->length = nSize; ++ ++ if(0 != msys_request_dmem(ptDmem)) ++ { ++ printk(KERN_WARNING "%s request dmem fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ ASSIGN_POINTER_VALUE(ppVirtPtr, (void *)(uintptr_t)ptDmem->kvirt); ++ ASSIGN_POINTER_VALUE(ppMiuPtr, (void *)(uintptr_t)Chip_Phys_to_MIU(ptDmem->phys)); ++ ASSIGN_POINTER_VALUE(ppPhysPtr, (void *)(uintptr_t)ptDmem->phys); ++ ++ printk(KERN_INFO "%s <%s> physAddr<0x%08X> size<%d>\n", ++ __FUNCTION__, ++ szName, ++ (u32)ptDmem->phys, ++ (u32)ptDmem->length); ++ ++ mutex_lock(&_gtMemLock); ++ if(0 == (ptNewEntry = (MemoryList_t*) kzalloc(sizeof(MemoryList_t), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s alloc entry fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ptNewEntry->pPhysPtr = *ppPhysPtr; ++ ptNewEntry->pVirtPtr = *ppVirtPtr; ++ ptNewEntry->pMemifoPtr = (void *) ptDmem; ++ if(0 == (ptNewEntry->szName = (char *)kzalloc(strlen(szName) + 1, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s alloc entry name fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ strncpy(ptNewEntry->szName, szName, strlen(szName)); ++ ptNewEntry->nSize = ptDmem->length; ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(eRet == CAM_OS_FAIL) ++ { ++ if(ptDmem) ++ { ++ if(ptDmem->phys) ++ { ++ msys_release_dmem(ptDmem); ++ } ++ kfree(ptDmem); ++ } ++ ++ if(ptNewEntry) ++ { ++ if(ptNewEntry->szName) ++ { ++ kfree(ptNewEntry->szName); ++ } ++ kfree(ptNewEntry); ++ } ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemRelease(void* pPtr, u32 nSize) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ if(pPtr) ++ { ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr == pPtr || ptTmp->pVirtPtr == pPtr) ++ { ++ if(ptTmp->szName) ++ MsReleaseMemory(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ MsReleaseMemory(ptTmp); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++ ++ MsReleaseMemory(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++#ifndef NO_MDRV_MSYS ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ s32 nMsysfd = -1; ++ s32 nErr = 0; ++ MSYS_DMEM_INFO *pMsysMem = NULL; ++ ++ if(pPtr) ++ { ++ do ++ { ++ if(0 > (nMsysfd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr == pPtr || ptTmp->pVirtPtr == pPtr) ++ { ++ pMsysMem = (MSYS_DMEM_INFO *) ptTmp->pMemifoPtr; ++ break; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(pMsysMem == NULL) ++ { ++ fprintf(stderr, "%s find Msys_DMEM_Info node failed!! <0x%08X>\n", __FUNCTION__, (u32)pPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(nSize != pMsysMem->length) ++ { ++ nErr = munmap((void *)ptTmp->pVirtPtr, pMsysMem->length); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <0x%08X> size<%d> err<%d> errno<%d, %s>\n", ++ __FUNCTION__, (u32)ptTmp->pVirtPtr, (u32)pMsysMem->length, nErr, errno, strerror(errno)); ++ } ++ } ++ else ++ { ++ nErr = munmap((void *)ptTmp->pVirtPtr, nSize); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <0x%08X> size<%d> err<%d> errno<%d, %s>\n", ++ __FUNCTION__, (u32)ptTmp->pVirtPtr, (u32)nSize, nErr, errno, strerror(errno)); ++ } ++ } ++ ++ if(ioctl(nMsysfd, IOCTL_MSYS_RELEASE_DMEM, pMsysMem)) ++ { ++ fprintf(stderr, "%s : IOCTL_MSYS_RELEASE_DMEM error physAddr<0x%x>\n", __FUNCTION__, (u32)pMsysMem->phys); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ if(pMsysMem) ++ { ++ free(pMsysMem); ++ pMsysMem = NULL; ++ } ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr == pPtr || ptTmp->pVirtPtr == pPtr) ++ { ++ if(ptTmp->szName) ++ free(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ free(ptTmp); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysfd >= 0) ++ { ++ close(nMsysfd); ++ } ++ } ++#endif ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *tpDmem = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ if(pPtr) ++ { ++ do ++ { ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ //printk("search tmp->ptr: %08X %s\n", (u32)ptTmp->pVirtPtr, ptTmp->szName); ++ ++ if(ptTmp->pPhysPtr == pPtr || ptTmp->pVirtPtr == pPtr) ++ { ++ tpDmem = ptTmp->pMemifoPtr; ++ //printk("search(2) pdmem->name: %s\n", tpDmem->name); ++ break; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(tpDmem == NULL) ++ { ++ printk(KERN_WARNING "%s find node fail <0x%08X>\n", __FUNCTION__, (u32)ptTmp->pVirtPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ msys_release_dmem(tpDmem); ++ ++ if(tpDmem) ++ { ++ kfree(tpDmem); ++ tpDmem = NULL; ++ } ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr == pPtr || ptTmp->pVirtPtr == pPtr) ++ { ++ if(ptTmp->szName) ++ kfree(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ kfree(ptTmp); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemFlush(void* pPtr) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ if(pPtr) ++ { ++ eRet = CAM_OS_FAIL; ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPhysPtr == pPtr || ptTmp->pVirtPtr == pPtr) ++ { ++ eRet = CAM_OS_OK; ++ sys_flush_data_cache_buffer((u32)MsVA2PA(ptTmp->pVirtPtr), ptTmp->nSize); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++#ifndef NO_MDRV_MSYS ++ s32 nMsysFd = -1; ++ ++ do ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(ioctl(nMsysFd, IOCTL_MSYS_FLUSH_MEMORY, 1)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_FLUSH_MEMORY Failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++#endif ++#elif defined(CAM_OS_LINUX_KERNEL) ++ flush_cache_all(); ++ Chip_Flush_Memory(); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemStat(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pVirtPtr) ++ { ++ CamOsPrintf("%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pVirtPtr, ptTmp->szName); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++#ifndef NO_MDRV_MSYS ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pVirtPtr) ++ { ++ fprintf(stderr, "%s memory allocated 0x%08X %s\n", __FUNCTION__, (u32)ptTmp->pVirtPtr, ptTmp->szName); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++#endif ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pVirtPtr) ++ { ++ printk(KERN_WARNING "%s allocated 0x%08X %s\n", __FUNCTION__, (u32)ptTmp->pVirtPtr, ptTmp->szName); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++#endif ++ return eRet; ++} ++ ++void* CamOsDirectMemPhysToMiu(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ return (void *)HalUtilPHY2MIUAddr((u32)pPtr); ++#elif defined(CAM_OS_LINUX_USER) ++ void *nMiuAddr = 0; ++#ifndef NO_MDRV_MSYS ++ s32 nMsysFd = -1; ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ ++ do ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ ++ tAddrInfo.addr = (uintptr_t)pPtr; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__); ++ break; ++ } ++ nMiuAddr = (void *)(uintptr_t)tAddrInfo.addr; ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++#endif ++ return nMiuAddr; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return (void *)(uintptr_t)Chip_Phys_to_MIU((uintptr_t)pPtr); ++#endif ++} ++ ++void* CamOsDirectMemMiuToPhys(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ return (void *)HalUtilMIU2PHYAddr((u32)pPtr); ++#elif defined(CAM_OS_LINUX_USER) ++ void *nPhysAddr = 0; ++#ifndef NO_MDRV_MSYS ++ s32 nMsysFd = -1; ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ ++ do ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ ++ tAddrInfo.addr = (uintptr_t)pPtr; ++ if(ioctl(nMsysFd, IOCTL_MSYS_MIU_TO_PHYS, &tAddrInfo)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_MIU_TO_PHYS Failed!!\n", __FUNCTION__); ++ break; ++ } ++ nPhysAddr = (void *)(uintptr_t)tAddrInfo.addr; ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++#endif ++ return nPhysAddr; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return (void *)(uintptr_t)Chip_MIU_to_Phys((uintptr_t)pPtr); ++#endif ++} ++ ++void* CamOsDirectMemPhysToVirt(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ return MsPA2VA(pPtr); ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement PhysToVirt in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ return NULL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++#if 0 ++ return (void *)phys_to_virt((unsigned long)pPtr); ++#else ++ MSYS_DMEM_INFO dmem; ++ u64 kptr = 0; ++ if(0 == msys_find_dmem_by_phys((u64)(u32)pPtr, &dmem)) ++ { ++ kptr = dmem.kvirt; ++ kptr += ((u64)(u32)pPtr - dmem.phys); ++ } ++ else ++ { ++ CamOsPrintf("CamOs WARNING: PhysToVirt not found 0x%08X in msys\n", (u32)pPtr); ++ } ++ ++ return (void*)(u32)kptr; ++#endif ++#endif ++} ++ ++void* CamOsDirectMemVirtToPhys(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ return MsVA2PA(pPtr); ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement VirtToPhys in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ return NULL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return (void *)virt_to_phys(pPtr); ++#endif ++} ++ ++void* CamOsPhyMemMap(void* pPhyPtr, u32 nSize, u8 bNonCache) ++{ ++#ifdef CAM_OS_RTK ++ if (bNonCache) ++ { ++ return MsPA2VA(pPhyPtr); ++ } ++ else ++ { ++ return pPhyPtr; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ void* pMmapPtr = NULL; ++#ifndef NO_MDRV_MSYS ++ s32 nMsysFd = -1; ++ s32 nMemFd = -1; ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ unsigned long long nCpuBusAddr; ++ ++ if((u32)pPhyPtr & 0xF0000000) ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ return NULL; ++ } ++ ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ ++ tAddrInfo.addr = (uintptr_t)pPhyPtr; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__); ++ close(nMsysFd); ++ return NULL; ++ } ++ nCpuBusAddr = (uintptr_t)tAddrInfo.addr; ++ ++ close(nMsysFd); ++ } ++ else ++ { ++ CAM_OS_WARN("wrong addr"); ++ CamOsPrintf("%s input MIU addr 0x%08X\n", __FUNCTION__, (u32)pPhyPtr); ++ return NULL; ++ } ++ ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/mem failed!!\n", __FUNCTION__); ++ return NULL; ++ } ++ ++ pMmapPtr = mmap(0, nSize, PROT_READ | PROT_WRITE, MAP_SHARED, nMemFd, nCpuBusAddr); ++ ++ if(nMemFd >= 0) ++ close(nMemFd); ++ ++ if(pMmapPtr == (void *) - 1) ++ return NULL; ++#endif ++ return pMmapPtr; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ unsigned long long nCpuBusAddr; ++ void *pVirtPtr = NULL; ++ int nRet, i, j, k; ++ struct sg_table *pSgTable; ++ struct scatterlist *pScatterList; ++ int nPageCount = 0; ++ struct page **ppPages; ++ pgprot_t tPgProt; ++ ++ if(!nSize) ++ return NULL; ++ ++ if(bNonCache) ++ tPgProt = pgprot_writecombine(PAGE_KERNEL); ++ else ++ tPgProt = PAGE_KERNEL; ++ ++ pSgTable = kmalloc(sizeof(struct sg_table), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ if(!pSgTable) ++ { ++ CAM_OS_WARN("kmalloc fail"); ++ return NULL; ++ } ++ ++ nRet = sg_alloc_table(pSgTable, 1, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ ++ if(unlikely(nRet)) ++ { ++ CAM_OS_WARN("sg_alloc_table fail"); ++ kfree(pSgTable); ++ return NULL; ++ } ++ ++ if((u32)pPhyPtr & 0xF0000000) ++ { ++ nCpuBusAddr = (uintptr_t)Chip_Phys_to_MIU((uintptr_t)pPhyPtr); ++ } ++ else ++ { ++ CAM_OS_WARN("wrong addr"); ++ CamOsPrintf("%s input MIU addr 0x%08X\n", __FUNCTION__, (u32)pPhyPtr); ++ } ++ ++ sg_set_page(pSgTable->sgl, pfn_to_page(__phys_to_pfn(nCpuBusAddr)), PAGE_ALIGN(nSize), 0); ++ ++ for_each_sg(pSgTable->sgl, pScatterList, pSgTable->nents, i) ++ { ++ nPageCount += pScatterList->length / PAGE_SIZE; ++ } ++ ++ ppPages = vmalloc(sizeof(struct page*)*nPageCount); ++ ++ if(ppPages == NULL) ++ { ++ CAM_OS_WARN("vmalloc fail"); ++ sg_free_table(pSgTable); ++ kfree(pSgTable); ++ return NULL; ++ } ++ ++ for_each_sg(pSgTable->sgl, pScatterList, pSgTable->nents, k) ++ { ++ nPageCount = PAGE_ALIGN(pScatterList->length) / PAGE_SIZE; ++ for(j = 0; j < nPageCount; j++) ++ ppPages[i + j] = sg_page(pScatterList) + j; ++ i += nPageCount; ++ } ++ pVirtPtr = vmap(ppPages, i, VM_MAP, tPgProt); ++ ++ vfree(ppPages); ++ sg_free_table(pSgTable); ++ kfree(pSgTable); ++ ++ return pVirtPtr; ++#endif ++} ++ ++void CamOsPhyMemUnMap(void* pVirtPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr; ++ ++ nErr = munmap(pVirtPtr, nSize); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <0x%08X> size<%d> err<%d> errno<%d, %s>\n", ++ __FUNCTION__, (u32)pVirtPtr, nSize, nErr, errno, strerror(errno)); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ vunmap(pVirtPtr); ++#endif ++} ++ ++void* CamOsMemMap(void* pPhyPtr, u32 nSize, u8 bCache) ++{ ++#ifdef CAM_OS_RTK ++ if (bCache) ++ return pPhyPtr; ++ else ++ return MsPA2VA(pPhyPtr); ++#elif defined(CAM_OS_LINUX_USER) ++ void* pMmapPtr = NULL; ++#ifndef NO_MDRV_MSYS ++ s32 nMsysFd = -1; ++ s32 nMemFd = -1; ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ unsigned long long nCpuBusAddr; ++ ++ if((u32)pPhyPtr & 0xF0000000) ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ return NULL; ++ } ++ ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ ++ tAddrInfo.addr = (uintptr_t)pPhyPtr; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__); ++ close(nMsysFd); ++ return NULL; ++ } ++ nCpuBusAddr = (uintptr_t)tAddrInfo.addr; ++ ++ close(nMsysFd); ++ } ++ else ++ { ++ CAM_OS_WARN("wrong addr"); ++ CamOsPrintf("%s input MIU addr 0x%08X\n", __FUNCTION__, (u32)pPhyPtr); ++ return NULL; ++ } ++ ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/mem failed!!\n", __FUNCTION__); ++ return NULL; ++ } ++ ++ pMmapPtr = mmap(0, nSize, PROT_READ | PROT_WRITE, MAP_SHARED, nMemFd, nCpuBusAddr); ++ ++ if(nMemFd >= 0) ++ close(nMemFd); ++ ++ if(pMmapPtr == (void *) - 1) ++ return NULL; ++#endif ++ return pMmapPtr; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ unsigned long long nCpuBusAddr = 0; ++ void *pVirtPtr = NULL; ++ int nRet, i, j; ++ struct sg_table *pSgTable; ++ struct scatterlist *pScatterList; ++ int nPageCount = 0; ++ int nPageTotal = 0; ++ struct page **ppPages; ++ pgprot_t tPgProt; ++ ++ if(!nSize) ++ return NULL; ++ ++ if(bCache) ++ tPgProt = PAGE_KERNEL; ++ else ++ tPgProt = pgprot_writecombine(PAGE_KERNEL); ++ ++ pSgTable = kmalloc(sizeof(struct sg_table), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ if(!pSgTable) ++ { ++ CAM_OS_WARN("kmalloc fail"); ++ return NULL; ++ } ++ ++ nRet = sg_alloc_table(pSgTable, 1, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ ++ if(unlikely(nRet)) ++ { ++ CAM_OS_WARN("sg_alloc_table fail"); ++ kfree(pSgTable); ++ return NULL; ++ } ++ ++ nCpuBusAddr = (uintptr_t)pPhyPtr; ++ ++ sg_set_page(pSgTable->sgl, pfn_to_page(__phys_to_pfn(nCpuBusAddr)), PAGE_ALIGN(nSize), 0); ++ ++ for_each_sg(pSgTable->sgl, pScatterList, pSgTable->nents, i) ++ { ++ nPageCount += pScatterList->length / PAGE_SIZE; ++ } ++ ++ ppPages = vmalloc(sizeof(struct page*)*nPageCount); ++ ++ if(ppPages == NULL) ++ { ++ CAM_OS_WARN("vmalloc fail"); ++ sg_free_table(pSgTable); ++ kfree(pSgTable); ++ return NULL; ++ } ++ ++ for_each_sg(pSgTable->sgl, pScatterList, pSgTable->nents, i) ++ { ++ nPageCount = PAGE_ALIGN(pScatterList->length) / PAGE_SIZE; ++ for(j = 0; j < nPageCount; j++) ++ ppPages[nPageTotal + j] = sg_page(pScatterList) + j; ++ nPageTotal += nPageCount; ++ } ++ pVirtPtr = vmap(ppPages, nPageTotal, VM_MAP, tPgProt); ++ ++ vfree(ppPages); ++ sg_free_table(pSgTable); ++ kfree(pSgTable); ++ ++ return pVirtPtr; ++#endif ++} ++ ++void CamOsMemUnmap(void* pVirtPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr; ++ ++ nErr = munmap(pVirtPtr, nSize); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <0x%08X> size<%d> err<%d> errno<%d, %s>\n", ++ __FUNCTION__, (u32)pVirtPtr, nSize, nErr, errno, strerror(errno)); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ vunmap(pVirtPtr); ++#endif ++} ++ ++CamOsRet_e CamOsMemCacheCreate(CamOsMemCache_t *ptMemCache, char *szName, u32 nSize, u8 bHwCacheAlign) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsMemCacheRtk_t *ptHandle = (CamOsMemCacheRtk_t *)ptMemCache; ++ ++ if(ptHandle) ++ { ++ if(RTK_OK == MsFindBestPool(nSize, &ptHandle->nPoolID)) ++ { ++ ptHandle->nObjSize = nSize; ++ } ++ else ++ { ++ CAM_OS_WARN("no satisfactory mem pool"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct kmem_cache *ptKmemCache; ++ CamOsMemCacheLK_t *ptHandle = (CamOsMemCacheLK_t *)ptMemCache; ++ ++ if(ptHandle) ++ { ++ ptKmemCache = kmem_cache_create(szName, nSize, 0, bHwCacheAlign ? SLAB_HWCACHE_ALIGN : 0, NULL); ++ ++ if(ptKmemCache) ++ { ++ ptHandle->ptKmemCache = ptKmemCache; ++ } ++ else ++ { ++ ptHandle->ptKmemCache = NULL; ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#endif ++ return eRet; ++} ++ ++void CamOsMemCacheDestroy(CamOsMemCache_t *ptMemCache) ++{ ++#ifdef CAM_OS_RTK ++ CamOsMemCacheRtk_t *ptHandle = (CamOsMemCacheRtk_t *)ptMemCache; ++ ++ if(ptHandle) ++ memset(ptHandle, 0, sizeof(CamOsMemCacheRtk_t)); ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMemCacheLK_t *ptHandle = (CamOsMemCacheLK_t *)ptMemCache; ++ ++ if(ptHandle && ptHandle->ptKmemCache) ++ { ++ kmem_cache_destroy(ptHandle->ptKmemCache); ++ ptHandle->ptKmemCache = NULL; ++ } ++#endif ++} ++ ++void *CamOsMemCacheAlloc(CamOsMemCache_t *ptMemCache) ++{ ++#ifdef CAM_OS_RTK ++ CamOsMemCacheRtk_t *ptHandle = (CamOsMemCacheRtk_t *)ptMemCache; ++ ++ if(ptHandle) ++ return MsGetPoolMemory(ptHandle->nObjSize); ++ else ++ return NULL; ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ return NULL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMemCacheLK_t *ptHandle = (CamOsMemCacheLK_t *)ptMemCache; ++ ++ if(ptHandle && ptHandle->ptKmemCache) ++ return kmem_cache_alloc(ptHandle->ptKmemCache, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ else ++ return NULL; ++#endif ++} ++ ++void *CamOsMemCacheAllocAtomic(CamOsMemCache_t *ptMemCache) ++{ ++#ifdef CAM_OS_RTK ++ CamOsMemCacheRtk_t *ptHandle = (CamOsMemCacheRtk_t *)ptMemCache; ++ ++ if(ptHandle) ++ return MsGetPoolMemory(ptHandle->nObjSize); ++ else ++ return NULL; ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++ return NULL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMemCacheLK_t *ptHandle = (CamOsMemCacheLK_t *)ptMemCache; ++ ++ if(ptHandle && ptHandle->ptKmemCache) ++ return kmem_cache_alloc(ptHandle->ptKmemCache, GFP_ATOMIC); ++ else ++ return NULL; ++#endif ++} ++ ++void CamOsMemCacheFree(CamOsMemCache_t *ptMemCache, void *pObjPtr) ++{ ++#ifdef CAM_OS_RTK ++ MsReleaseMemory(pObjPtr); ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMemCacheLK_t *ptHandle = (CamOsMemCacheLK_t *)ptMemCache; ++ ++ if(ptHandle && ptHandle->ptKmemCache) ++ kmem_cache_free(ptHandle->ptKmemCache, pObjPtr); ++#endif ++} ++ ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_set)(const char *szKey, const char *szValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set = dlsym(pLibHandle, "property_set"); ++ if(NULL == dlsym_property_set) ++ { ++ fprintf(stderr, "%s : dlsym property_set failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set(szKey, szValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsPropertyGet(const char *szKey, char *szValue, const char *szDefaultValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_get)(const char *szKey, char *szValue, const char *szDefaultValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ dlsym_property_get = dlsym(pLibHandle, "property_get"); ++ if(NULL == dlsym_property_get) ++ { ++ fprintf(stderr, "%s : dlsym property_get failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_get(szKey, szValue, szDefaultValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++u64 CamOsMathDivU64(u64 nDividend, u64 nDivisor, u64 *pRemainder) ++{ ++#ifdef CAM_OS_RTK ++ return (pRemainder)? ss_div64_u64_rem(nDividend, nDivisor, pRemainder) : ss_div64_u64(nDividend, nDivisor); ++#elif defined(CAM_OS_LINUX_USER) ++ if (pRemainder) ++ *pRemainder = nDividend % nDivisor; ++ return nDividend / nDivisor; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return (pRemainder)? div64_u64_rem(nDividend, nDivisor, pRemainder) : div64_u64(nDividend, nDivisor); ++#endif ++} ++ ++s64 CamOsMathDivS64(s64 nDividend, s64 nDivisor, s64 *pRemainder) ++{ ++#ifdef CAM_OS_RTK ++ s64 nQuotient = ss_div64_s64(nDividend, nDivisor); ++ if (pRemainder) ++ *pRemainder = nDividend - nDivisor * nQuotient; ++ return nQuotient; ++#elif defined(CAM_OS_LINUX_USER) ++ if (pRemainder) ++ *pRemainder = nDividend % nDivisor; ++ return nDividend / nDivisor; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s64 nQuotient = div64_s64(nDividend, nDivisor); ++ if (pRemainder) ++ *pRemainder = nDividend - nDivisor * nQuotient; ++ return nQuotient; ++#endif ++} ++ ++u32 CamOsCopyFromUpperLayer(void *pTo, const void *pFrom, u32 nLen) ++{ ++#ifdef CAM_OS_RTK ++ memcpy(pTo, pFrom, nLen); ++ return 0; ++#elif defined(CAM_OS_LINUX_USER) ++ memcpy(pTo, pFrom, nLen); ++ return 0; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return copy_from_user(pTo, pFrom, nLen); ++#endif ++} ++ ++u32 CamOsCopyToUpperLayer(void *pTo, const void * pFrom, u32 nLen) ++{ ++#ifdef CAM_OS_RTK ++ memcpy(pTo, pFrom, nLen); ++ return 0; ++#elif defined(CAM_OS_LINUX_USER) ++ memcpy(pTo, pFrom, nLen); ++ return 0; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return copy_to_user(pTo, pFrom, nLen); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++void _CamOsTimerCallback(MsTimerId_e eTimerID, u32 nHandleAddr) ++{ ++ CamOsTimerRtk_t *ptHandle = (CamOsTimerRtk_t *)nHandleAddr; ++ ++ //CamOsPrintf("%s: eTimerID = 0x%x\n", __FUNCTION__, eTimerID); ++ ++ if(ptHandle) ++ { ++ ptHandle->pfnCallback((u32)ptHandle->pDataPtr); ++ } ++} ++#endif ++ ++CamOsRet_e CamOsTimerInit(CamOsTimer_t *ptTimer) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTimerRtk_t *ptHandle = (CamOsTimerRtk_t *)ptTimer; ++ unsigned long flags = 0; ++ ++ if(ptHandle) ++ { ++ RtkEnterRegionSaveIrq(&flags); ++ if(ptHandle->eTimerID != INIT_MAGIC_NUM && MsIsTimerActive(ptHandle->eTimerID)) ++ { ++ MsStopTimer(ptHandle->eTimerID); ++ } ++ ptHandle->eTimerID = INIT_MAGIC_NUM; ++ RtkLeaveRegionRestoreIrq(&flags); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement timer in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTimerLK_t *ptHandle = (CamOsTimerLK_t *)ptTimer; ++ if(ptHandle) ++ { ++ init_timer(&ptHandle->tTimerID); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#endif ++ return eRet; ++} ++ ++u32 CamOsTimerDelete(CamOsTimer_t *ptTimer) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTimerRtk_t *ptHandle = (CamOsTimerRtk_t *)ptTimer; ++ unsigned long flags = 0; ++ unsigned long nRet = 0; ++ ++ if(ptHandle) ++ { ++ // MsStopTimer return the number of remain ticks, 1 means timeout ++ RtkEnterRegionSaveIrq(&flags); ++ nRet = (MsStopTimer(ptHandle->eTimerID) > 1) ? 1 : 0; ++ RtkLeaveRegionRestoreIrq(&flags); ++ return nRet; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement timer in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ return 0; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTimerLK_t *ptHandle = (CamOsTimerLK_t *)ptTimer; ++ if(ptHandle) ++ { ++ return del_timer(&ptHandle->tTimerID); ++ } ++#endif ++ return 0; ++} ++ ++u32 CamOsTimerDeleteSync(CamOsTimer_t *ptTimer) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTimerRtk_t *ptHandle = (CamOsTimerRtk_t *)ptTimer; ++ unsigned long flags = 0; ++ unsigned long nRet = 0; ++ ++ if(ptHandle) ++ { ++ // MsStopTimer return the number of remain ticks, 1 means timeout ++ RtkEnterRegionSaveIrq(&flags); ++ nRet = (MsStopTimer(ptHandle->eTimerID) > 1) ? 1 : 0; ++ RtkLeaveRegionRestoreIrq(&flags); ++ return nRet; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement timer in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ return 0; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTimerLK_t *ptHandle = (CamOsTimerLK_t *)ptTimer; ++ if(ptHandle) ++ { ++ return del_timer_sync(&ptHandle->tTimerID); ++ } ++#endif ++ return 0; ++} ++ ++CamOsRet_e CamOsTimerAdd(CamOsTimer_t *ptTimer, u32 nMsec, void *pDataPtr, ++ void (*pfnFunc)(unsigned long nDataAddr)) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTimerRtk_t *ptHandle = (CamOsTimerRtk_t *)ptTimer; ++ unsigned long flags = 0; ++ unsigned long nRet = 0; ++ ++ if(ptHandle) ++ { ++ if(ptHandle->eTimerID != INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("init timer first"); ++ eRet = CAM_OS_FAIL; ++ } ++ ++ RtkEnterRegionSaveIrq(&flags); ++ ptHandle->pfnCallback = pfnFunc; ++ ptHandle->pDataPtr = pDataPtr; ++ nRet = MsStartCbTimerMs(&ptHandle->eTimerID, _CamOsTimerCallback, (u32)ptHandle, nMsec, 0); ++ RtkLeaveRegionRestoreIrq(&flags); ++ ++ if(nRet != CUS_OS_OK) ++ { ++ CAM_OS_WARN("start timer fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement timer in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTimerLK_t *ptHandle = (CamOsTimerLK_t *)ptTimer; ++ if(ptHandle) ++ { ++ ptHandle->tTimerID.expires = jiffies + msecs_to_jiffies(nMsec); ++ ptHandle->tTimerID.function = pfnFunc; ++ ptHandle->tTimerID.data = (unsigned long)pDataPtr; ++ add_timer(&ptHandle->tTimerID); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTimerModify(CamOsTimer_t *ptTimer, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTimerRtk_t *ptHandle = (CamOsTimerRtk_t *)ptTimer; ++ unsigned long flags = 0; ++ unsigned long nRet = 0; ++ ++ if(ptHandle) ++ { ++ if(ptHandle->eTimerID == INIT_MAGIC_NUM) ++ { ++ CAM_OS_WARN("add timer first"); ++ eRet = CAM_OS_FAIL; ++ } ++ ++ RtkEnterRegionSaveIrq(&flags); ++ MsStopTimer(ptHandle->eTimerID); ++ nRet = MsStartCbTimerMs(&ptHandle->eTimerID, _CamOsTimerCallback, (u32)ptHandle, nMsec, 0); ++ RtkLeaveRegionRestoreIrq(&flags); ++ ++ if(nRet != CUS_OS_OK) ++ { ++ CAM_OS_WARN("start timer fail"); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#elif defined(CAM_OS_LINUX_USER) ++ // TODO: implement timer in linux user space. ++ CAM_OS_WARN("not support in "OS_NAME); ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTimerLK_t *ptHandle = (CamOsTimerLK_t *)ptTimer; ++ if(ptHandle) ++ { ++ mod_timer(&ptHandle->tTimerID, jiffies + msecs_to_jiffies(nMsec)); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#endif ++ return eRet; ++} ++ ++s32 CamOsAtomicRead(CamOsAtomic_t *ptAtomic) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return ptAtomic->nCounter; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return ptAtomic->nCounter; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_read((atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++void CamOsAtomicSet(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ ptAtomic->nCounter = nValue; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ ptAtomic->nCounter = nValue; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ atomic_set((atomic_t *)ptAtomic, nValue); ++ } ++#endif ++} ++ ++s32 CamOsAtomicAddReturn(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return __sync_add_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return __sync_add_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_add_return(nValue, (atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicSubReturn(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return __sync_sub_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return __sync_sub_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_sub_return(nValue, (atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicSubAndTest(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return !(__sync_sub_and_fetch(&ptAtomic->nCounter, nValue)); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return !(__sync_sub_and_fetch(&ptAtomic->nCounter, nValue)); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_sub_and_test(nValue, (atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicIncReturn(CamOsAtomic_t *ptAtomic) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return __sync_add_and_fetch(&ptAtomic->nCounter, 1); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return __sync_add_and_fetch(&ptAtomic->nCounter, 1); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_inc_return((atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicDecReturn(CamOsAtomic_t *ptAtomic) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return __sync_sub_and_fetch(&ptAtomic->nCounter, 1); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return __sync_sub_and_fetch(&ptAtomic->nCounter, 1); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_dec_return((atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicIncAndTest(CamOsAtomic_t *ptAtomic) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return !(__sync_add_and_fetch(&ptAtomic->nCounter, 1)); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return !(__sync_add_and_fetch(&ptAtomic->nCounter, 1)); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_inc_and_test((atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicDecAndTest(CamOsAtomic_t *ptAtomic) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return !(__sync_sub_and_fetch(&ptAtomic->nCounter, 1)); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return !(__sync_sub_and_fetch(&ptAtomic->nCounter, 1)); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_dec_and_test((atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicAddNegative(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return (__sync_add_and_fetch(&ptAtomic->nCounter, nValue) < 0); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return (__sync_add_and_fetch(&ptAtomic->nCounter, nValue) < 0); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_add_negative(nValue, (atomic_t *)ptAtomic); ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicCompareAndSwap(CamOsAtomic_t *ptAtomic, s32 nOldValue, s32 nNewValue) ++{ ++#ifdef CAM_OS_RTK ++ if(ptAtomic) ++ { ++ return __sync_bool_compare_and_swap(&ptAtomic->nCounter, nOldValue, nNewValue); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(ptAtomic) ++ { ++ return __sync_bool_compare_and_swap(&ptAtomic->nCounter, nOldValue, nNewValue); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(ptAtomic) ++ { ++ return atomic_cmpxchg( (atomic_t *)ptAtomic, nOldValue, nNewValue); // return TRUE: CAS doing, ++ } ++#endif ++ return 0; ++} ++ ++s32 CamOsAtomicAndFetch(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_and_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicFetchAnd(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_fetch_and_and(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicNandFetch(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_nand_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicFetchNand(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_fetch_and_nand(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicOrFetch(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_or_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicFetchOr(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_fetch_and_or(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicXorFetch(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_xor_and_fetch(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++s32 CamOsAtomicFetchXor(CamOsAtomic_t *ptAtomic, s32 nValue) ++{ ++ if(ptAtomic) ++ { ++ return __sync_fetch_and_xor(&ptAtomic->nCounter, nValue); ++ } ++ else ++ { ++ CAM_OS_WARN("null atomic handle"); ++ return 0; ++ } ++} ++ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++extern CamOsRet_e _CamOsIdrInit(CamOsIdr_t *ptIdr, u32 nEntryNum); ++extern void _CamOsIdrDestroy(CamOsIdr_t *ptIdr); ++extern s32 _CamOsIdrAlloc(CamOsIdr_t *ptIdr, void *pPtr, s32 nStart, s32 nEnd); ++extern void _CamOsIdrRemove(CamOsIdr_t *ptIdr, s32 nId); ++extern void *_CamOsIdrFind(CamOsIdr_t *ptIdr, s32 nId); ++#endif ++ ++CamOsRet_e CamOsIdrInit(CamOsIdr_t *ptIdr) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ eRet = _CamOsIdrInit(ptIdr, 0); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsIdrLK_t *ptHandle = (CamOsIdrLK_t *)ptIdr; ++ ++ if(ptHandle) ++ { ++ idr_init(&ptHandle->tIdr); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsIdrInitEx(CamOsIdr_t *ptIdr, u32 nEntryNum) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ eRet = _CamOsIdrInit(ptIdr, nEntryNum); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsIdrLK_t *ptHandle = (CamOsIdrLK_t *)ptIdr; ++ ++ if(ptHandle) ++ { ++ idr_init(&ptHandle->tIdr); ++ } ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#endif ++ return eRet; ++} ++ ++void CamOsIdrDestroy(CamOsIdr_t *ptIdr) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ _CamOsIdrDestroy(ptIdr); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsIdrLK_t *ptHandle = (CamOsIdrLK_t *)ptIdr; ++ ++ if(ptHandle) ++ { ++ idr_destroy(&ptHandle->tIdr); ++ } ++#endif ++} ++ ++s32 CamOsIdrAlloc(CamOsIdr_t *ptIdr, void *pPtr, s32 nStart, s32 nEnd) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ return _CamOsIdrAlloc(ptIdr, pPtr, nStart, nEnd); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsIdrLK_t *ptHandle = (CamOsIdrLK_t *)ptIdr; ++ ++ if(ptHandle) ++ { ++ return idr_alloc(&ptHandle->tIdr, pPtr, nStart, nEnd, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ } ++ else ++ return -1; ++#endif ++} ++ ++void CamOsIdrRemove(CamOsIdr_t *ptIdr, s32 nId) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ _CamOsIdrRemove(ptIdr, nId); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsIdrLK_t *ptHandle = (CamOsIdrLK_t *)ptIdr; ++ ++ if(ptHandle) ++ { ++ idr_remove(&ptHandle->tIdr, nId); ++ } ++#endif ++} ++ ++void *CamOsIdrFind(CamOsIdr_t *ptIdr, s32 nId) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ return _CamOsIdrFind(ptIdr, nId); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsIdrLK_t *ptHandle = (CamOsIdrLK_t *)ptIdr; ++ ++ if(ptHandle) ++ { ++ return idr_find(&ptHandle->tIdr, nId); ++ } ++ else ++ return NULL; ++#endif ++} ++ ++ ++CamOsMemSize_e CamOsPhysMemSize(void) ++{ ++ CamOsDramInfo_t tInfo = {0}; ++ u32 i = 0; ++ u32 nMegaBytes = 0; ++ ++ CamOsDramInfo(&tInfo); ++ nMegaBytes = tInfo.nBytes >> 20; ++ while (nMegaBytes >>= 1) ++i; ++ ++ return i; ++} ++ ++CamOsRet_e CamOsDramInfo(CamOsDramInfo_t *ptInfo) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ if (ptInfo) ++ sys_GetDramInfo(&ptInfo->nBytes, &ptInfo->nType, &ptInfo->nBusWidth); ++ else ++ eRet = CAM_OS_PARAM_ERR; ++#elif defined(CAM_OS_LINUX_USER) ++ int fd; ++ char buf[512]; ++ int dram_freq, miupll_freq, data_rate; ++ ++ if (ptInfo) ++ { ++ fd = open("/sys/devices/system/miu/miu0/dram_info", O_RDONLY); ++ if (fd >= 0) ++ { ++ read(fd, buf, sizeof(buf)); ++ sscanf (buf, "DRAM Type: DDR%hd\n" ++ "DRAM Size: %dMB\n" ++ "DRAM Freq: %dMHz\n" ++ "MIUPLL Freq: %dMHz\n" ++ "Data Rate: %dx Mode\n" ++ "Bus Width: %hdbit", ++ &ptInfo->nType, ++ &ptInfo->nBytes, ++ &dram_freq, ++ &miupll_freq, ++ &data_rate, ++ &ptInfo->nBusWidth); ++ close(fd); ++ ++ ptInfo->nBytes = (ptInfo->nBytes << 20); ++ } ++ else ++ { ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MIU_DramInfo stDramInfo; ++ MDrv_MIU_Info(&stDramInfo); ++ ptInfo->nBytes = stDramInfo.size; ++ ptInfo->nType = stDramInfo.type; ++ ptInfo->nBusWidth = stDramInfo.bus_width; ++#endif ++ return eRet; ++} ++ ++u32 CamOsChipId(void) ++{ ++#ifdef CAM_OS_RTK ++ return sys_GetChipId(); ++#elif defined(CAM_OS_LINUX_USER) ++ int fd; ++ char buf[32]; ++ u32 id = 0; ++ ++ fd = open("/sys/devices/virtual/mstar/msys/CHIP_ID", O_RDONLY); ++ if (fd >= 0) ++ { ++ read(fd, buf, sizeof(buf)); ++ sscanf (buf, "Chip_ID: 0x%X", &id); ++ close(fd); ++ } ++ ++ return id; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return Chip_Get_Device_ID(); ++#endif ++} ++ ++u32 CamOsChipRevision(void) ++{ ++#ifdef CAM_OS_RTK ++ return sys_GetChipRevisionId(); ++#elif defined(CAM_OS_LINUX_USER) ++ int fd; ++ char buf[32]; ++ u32 rev = 0; ++ ++ fd = open("/sys/devices/virtual/mstar/msys/CHIP_VERSION", O_RDONLY); ++ if (fd >= 0) ++ { ++ read(fd, buf, sizeof(buf)); ++ sscanf (buf, "Chip_Version: %u", &rev); ++ rev += 1; // 1:U01, 2:U02 ... ++ close(fd); ++ } ++ ++ return rev; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return Chip_Get_Revision();; ++#endif ++} ++ ++CamOsRet_e CamOsIrqRequest(u32 nIrq, CamOsIrqHandler pfnHandler, const char *szName, void *pDevId) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ IntInitParam_u uInitParam = {{0}}; ++ uInitParam.intc.eMap = INTC_MAP_IRQ; ++ uInitParam.intc.ePriority = INTC_PRIORITY_7; ++ uInitParam.intc.pfnIsr = pfnHandler; ++ uInitParam.intc.pDevId = pDevId; ++ DrvInitInterrupt(&uInitParam, nIrq); ++ DrvUnmaskInterrupt(nIrq); ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s32 nResult = 0; ++ ++ if (nIrq < LINUX_KERNEL_MAX_IRQ) ++ { ++ CamOsIrqHandlerList[nIrq] = pfnHandler; ++ if ((nResult = request_irq(nIrq, (irq_handler_t)CamOsIrqCommonHandler, IRQF_SHARED | IRQF_ONESHOT, szName, pDevId))) ++ { ++ CAM_OS_WARN("request_irq fail"); ++ CamOsPrintf("%s irq(%d) err(%d)\n", __FUNCTION__ , nIrq, nResult); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_FAIL; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsIrqFree(u32 nIrq, void *pDevId) ++{ ++#ifdef CAM_OS_RTK ++ return; ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ free_irq(nIrq, pDevId); ++#endif ++} ++ ++void CamOsIrqEnable(u32 nIrq) ++{ ++#ifdef CAM_OS_RTK ++ DrvUnmaskInterrupt(nIrq); ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ enable_irq(nIrq); ++#endif ++} ++ ++void CamOsIrqDisable(u32 nIrq) ++{ ++#ifdef CAM_OS_RTK ++ DrvMaskInterrupt(nIrq); ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ disable_irq(nIrq); ++#endif ++} ++ ++CamOsRet_e FORCE_INLINE CamOsInInterrupt(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ if(!RtkRunInIsrContext()) ++ eRet = CAM_OS_FAIL; ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(!in_interrupt()) ++ eRet = CAM_OS_FAIL; ++#endif ++ return eRet; ++} ++ ++void FORCE_INLINE CamOsMemoryBarrier(void) ++{ ++ asm volatile("": : :"memory"); ++} ++ ++void FORCE_INLINE CamOsSmpMemoryBarrier(void) ++{ ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ CAM_OS_WARN("not support in "OS_NAME); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ smp_mb(); ++#endif ++} ++ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_KERNEL) ++char _szErrStrBuf[128]; ++#endif ++ ++char *CamOsStrError(s32 nErrNo) ++{ ++#ifdef CAM_OS_RTK ++ sprintf(_szErrStrBuf, "errno: %d", nErrNo); ++ return _szErrStrBuf; ++#elif defined(CAM_OS_LINUX_USER) ++ return strerror(nErrNo); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ sprintf(_szErrStrBuf, "errno: %d", nErrNo); ++ return _szErrStrBuf; ++#endif ++} ++ ++void CamOsPanic(const char *szMessage) ++{ ++#ifdef CAM_OS_RTK ++ CamOsPrintf("%s: %s\n", __FUNCTION__, szMessage); ++ RtkExceptionRoutine(240, 0); // SYSTEM_ASSERT = 240 ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsPrintf("%s: %s\n", __FUNCTION__, szMessage); ++ abort(); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ panic(szMessage); ++#endif ++} ++ ++long CamOsStrtol(const char *szStr, char** szEndptr, s32 nBase) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ return strtol(szStr, szEndptr, nBase); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return simple_strtol(szStr, szEndptr, nBase); ++#endif ++} ++ ++unsigned long CamOsStrtoul(const char *szStr, char** szEndptr, s32 nBase) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ return strtoul(szStr, szEndptr, nBase); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return simple_strtoul(szStr, szEndptr, nBase); ++#endif ++} ++ ++unsigned long long CamOsStrtoull(const char *szStr, char** szEndptr, s32 nBase) ++{ ++#if defined(CAM_OS_RTK) || defined(CAM_OS_LINUX_USER) ++ return strtoull(szStr, szEndptr, nBase); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return simple_strtoull(szStr, szEndptr, nBase); ++#endif ++} ++ ++unsigned long _CamOsFindFirstZeroBit(unsigned long *pAddr, unsigned long nSize, ++ unsigned long nOffset) ++{ ++ unsigned long *pLongBitmap = pAddr + (nOffset / CAM_OS_BITS_PER_LONG); ++ unsigned long nResult = nOffset & ~(CAM_OS_BITS_PER_LONG - 1), nTemp; ++ ++ if(nOffset >= nSize) ++ return nSize; ++ ++ nSize -= nResult; ++ nOffset %= CAM_OS_BITS_PER_LONG; ++ if(nOffset) ++ { ++ nTemp = *(pLongBitmap++); ++ nTemp |= ~0UL >> (CAM_OS_BITS_PER_LONG - nOffset); ++ if(nSize < CAM_OS_BITS_PER_LONG) ++ goto IN_FIRST_BIT; ++ ++ if(~nTemp) ++ goto IN_OTHER_BIT; ++ ++ nSize -= CAM_OS_BITS_PER_LONG; ++ nResult += CAM_OS_BITS_PER_LONG; ++ } ++ ++ //while (nSize > CAM_OS_BITS_PER_LONG) ++ while(nSize & ~(CAM_OS_BITS_PER_LONG - 1)) ++ { ++ if(~(nTemp = *pLongBitmap)) ++ goto IN_OTHER_BIT; ++ ++ nResult += CAM_OS_BITS_PER_LONG; ++ nSize -= CAM_OS_BITS_PER_LONG; ++ pLongBitmap++; ++ } ++ ++ if(!nSize) ++ return nResult; ++ ++ nTemp = *pLongBitmap; ++ ++IN_FIRST_BIT: ++ nTemp |= ~0UL << nSize; ++ if(nTemp == ~0UL) ++ return nResult + nSize; ++ ++IN_OTHER_BIT: ++ return nResult + CAM_OS_FFZ(nTemp); ++} ++ ++static struct CamOsListHead_t *_CamOsListMerge(void *priv, ++ int (*cmp)(void *priv, struct CamOsListHead_t *a, ++ struct CamOsListHead_t *b), ++ struct CamOsListHead_t *a, struct CamOsListHead_t *b) ++{ ++ struct CamOsListHead_t head, *tail = &head; ++ ++ while(a && b) ++ { ++ /* if equal, take 'a' -- important for sort stability */ ++ if((*cmp)(priv, a, b) <= 0) ++ { ++ tail->pNext = a; ++ a = a->pNext; ++ } ++ else ++ { ++ tail->pNext = b; ++ b = b->pNext; ++ } ++ tail = tail->pNext; ++ } ++ tail->pNext = a ? : b; ++ return head.pNext; ++} ++ ++static void _CamOsListMergeAndRestoreBackLinks(void *priv, ++ int (*cmp)(void *priv, struct CamOsListHead_t *a, ++ struct CamOsListHead_t *b), ++ struct CamOsListHead_t *head, ++ struct CamOsListHead_t *a, struct CamOsListHead_t *b) ++{ ++ struct CamOsListHead_t *tail = head; ++ u8 count = 0; ++ ++ while(a && b) ++ { ++ /* if equal, take 'a' -- important for sort stability */ ++ if((*cmp)(priv, a, b) <= 0) ++ { ++ tail->pNext = a; ++ a->pPrev = tail; ++ a = a->pNext; ++ } ++ else ++ { ++ tail->pNext = b; ++ b->pPrev = tail; ++ b = b->pNext; ++ } ++ tail = tail->pNext; ++ } ++ tail->pNext = a ? : b; ++ ++ do ++ { ++ /* ++ * In worst cases this loop may run many iterations. ++ * Continue callbacks to the client even though no ++ * element comparison is needed, so the client's cmp() ++ * routine can invoke cond_resched() periodically. ++ */ ++ if(!(++count)) ++ (*cmp)(priv, tail->pNext, tail->pNext); ++ ++ tail->pNext->pPrev = tail; ++ tail = tail->pNext; ++ } ++ while(tail->pNext); ++ ++ tail->pNext = head; ++ head->pPrev = tail; ++} ++ ++void CamOsListSort(void *priv, struct CamOsListHead_t *head, ++ int (*cmp)(void *priv, struct CamOsListHead_t *a, ++ struct CamOsListHead_t *b)) ++{ ++ struct CamOsListHead_t *part[CAM_OS_MAX_LIST_LENGTH_BITS + 1]; /* sorted partial lists ++ -- last slot is a sentinel */ ++ int lev; /* index into part[] */ ++ int max_lev = 0; ++ struct CamOsListHead_t *list; ++ ++ if(CAM_OS_LIST_EMPTY(head)) ++ return; ++ ++ memset(part, 0, sizeof(part)); ++ ++ head->pPrev->pNext = NULL; ++ list = head->pNext; ++ ++ while(list) ++ { ++ struct CamOsListHead_t *cur = list; ++ list = list->pNext; ++ cur->pNext = NULL; ++ ++ for(lev = 0; part[lev]; lev++) ++ { ++ cur = _CamOsListMerge(priv, cmp, part[lev], cur); ++ part[lev] = NULL; ++ } ++ if(lev > max_lev) ++ { ++ if(lev >= CAM_OS_ARRAY_SIZE(part) - 1) ++ { ++ CAM_OS_WARN("list too long"); ++ lev--; ++ } ++ max_lev = lev; ++ } ++ part[lev] = cur; ++ } ++ ++ for(lev = 0; lev < max_lev; lev++) ++ if(part[lev]) ++ list = _CamOsListMerge(priv, cmp, part[lev], list); ++ ++ _CamOsListMergeAndRestoreBackLinks(priv, cmp, head, part[max_lev], list); ++} +diff --git a/drivers/sstar/cam_os_wrapper/test/Makefile b/drivers/sstar/cam_os_wrapper/test/Makefile +new file mode 100755 +index 000000000000..d1405a16135f +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/test/Makefile +@@ -0,0 +1,23 @@ ++obj-m := linux_ktest.o ++linux_ktest-objs := ../src/cam_os_wrapper.o cam_os_wrapper_linux_kernel_test.o ++ ++export ARCH=arm ++export CROSS_COMPILE=arm-linux-gnueabihf- ++ ++KERNEL = $(PWD)/../../../../ ++CC = $(CROSS_COMPILE)gcc ++APP = cam_os_wrapper_test ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS := -I$(KERNEL)/drivers/sstar/include/ -I$(KERNEL)/drivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++USER_CFLAGS := -Wall -Werror -Wno-sync-nand -g -O2 -ffunction-sections -funwind-tables -fstack-protector -I../pub/ -I$(KERNEL)/drivers/sstar/include/ ++USER_LDFLAGS := -L$(PWD)/../.build/lib -lcam_os_wrapper ++ ++all: ++ make modules -C $(KERNEL) M=`pwd` ++ #$(CROSS_COMPILE)strip -g cam_os_wrapper_linux_ktest.ko ++ $(CC) $(USER_CFLAGS) $(USER_LDFLAGS) $(APP).c -o $(APP) ++ ++clean: ++ make modules clean -C $(KERNEL) M=`pwd` ++ rm -rf $(APP) ++ +diff --git a/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_linux_kernel_test.c b/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_linux_kernel_test.c +new file mode 100755 +index 000000000000..44623428908c +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_linux_kernel_test.c +@@ -0,0 +1,1523 @@ ++/* ++* cam_os_wrapper_linux_kernel_test.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper_linux_kernel_test.c ++/// @brief Cam OS Wrapper Test Code for Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("SStar Kernel Wrapper Test"); ++MODULE_LICENSE("GPL"); ++ ++//#define TEST_TIME_AND_SLEEP ++//#define TEST_DIRECT_MEMORY ++//#define TEST_PHY_MAP_VIRT ++//#define TEST_CACHE_ALLOC ++//#define TEST_IDR ++//#define TEST_THREAD ++//#define TEST_THREAD_PRIORITY ++//#define TEST_SEMAPHORE ++//#define TEST_RW_SEMAPHORE ++//#define TEST_MUTEX ++//#define TEST_CONDITION_WAIT ++//#define TEST_DIV64 ++//#define TEST_SYSTEM_TIME ++//#define TEST_MEM_SIZE ++//#define TEST_CHIP_ID ++//#define TEST_ATOMIC_OPERATION ++//#define TEST_BITMAP ++//#define TEST_HASH ++//#define TEST_TIMER ++//#define TEST_SPINLOCK ++ ++#ifdef TEST_TIME_AND_SLEEP ++CamOsThread tTimeThread0; ++static int ThreadTestTimeSleep(void *pUserData) ++{ ++ CamOsTimespec_t tTimeStart = {0}; ++ CamOsTimespec_t tTimeEnd = {0}; ++ u32 nTestCounter=0; ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsMsSleep(1000); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 1000 ms, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsMsSleep(100); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 100 ms, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsMsSleep(10); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 10 ms, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsMsSleep(1); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 1 ms, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsUsSleep(1000); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 1000 us, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsUsSleep(100); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 100 us, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsUsSleep(10); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 10 us, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsUsSleep(1); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set sleep 1 us, real sleep %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsMsDelay(1); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set delay 1 ms, real delay %lld us\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nTestCounter = 0; nTestCounter < 10; nTestCounter++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTimeStart); ++ CamOsUsDelay(1); ++ CamOsGetMonotonicTime(&tTimeEnd); ++ CamOsPrintf("%s set delay 1 us, real delay %lld ns\n", __FUNCTION__, CamOsTimeDiff(&tTimeStart, &tTimeEnd, CAM_OS_TIME_DIFF_NS)); ++ } ++ ++ while (1) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) ++ break; ++ ++ CamOsMsSleep(1000); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_THREAD ++CamOsAtomic_t _gtThreadAtomic; ++CamOsThreadAttrb_t tThreadAttr; ++CamOsThread tThread0, tThread1; ++static int ThreadTest1(void *pUserData) ++{ ++ int32_t nTestCounter=0; ++ ++ CamOsMsSleep(10); ++ ++ while (nTestCounter < 10000) ++ { ++ nTestCounter++; ++ if ((nTestCounter % 500) == 0) ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ } ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 3) ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s free run end\n", __FUNCTION__); ++ ++ while (CAM_OS_OK != CamOsThreadShouldStop()) ++ { ++ if (CamOsAtomicRead(&_gtThreadAtomic) == 3) ++ { ++ CamOsPrintf("%s enter CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsThreadSchedule(0, 2000); ++ CamOsPrintf("%s leave CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ } ++ ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ CamOsMsSleep(300); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int ThreadTest2(void *pUserData) ++{ ++ int32_t nTestCounter=0; ++ ++ CamOsMsSleep(10); ++ ++ while (nTestCounter < 10000) ++ { ++ nTestCounter++; ++ if ((nTestCounter % 500) == 0) ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ } ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 3) ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s free run end\n", __FUNCTION__); ++ ++ while (CAM_OS_OK != CamOsThreadShouldStop()) ++ { ++ if (CamOsAtomicRead(&_gtThreadAtomic) == 4) ++ { ++ CamOsPrintf("%s enter CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsThreadSchedule(1, CAM_OS_MAX_TIMEOUT); ++ CamOsPrintf("%s leave CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ } ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ CamOsMsSleep(300); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_THREAD_PRIORITY ++#define THREAD_PRIORITY_TEST_NUM 100 ++CamOsThreadAttrb_t tThreadAttrPrio; ++CamOsThread tThreadPrio[THREAD_PRIORITY_TEST_NUM]; ++static int ThreadTestPrio(void *pUserData) ++{ ++ CamOsPrintf("%s create\n", __FUNCTION__); ++ ++ while (CAM_OS_OK != CamOsThreadShouldStop()) ++ { ++ CamOsMsSleep(10); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_SEMAPHORE ++static uint32_t _gTsemTestCnt = 0; ++CamOsTsem_t tSem; ++CamOsThread tTsemThread0, tTsemThread1; ++static int ThreadTestTsem1(void *pUserData) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(1000); ++ ++ _gTsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTsemTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTsemTestCnt=%d)\n", __FUNCTION__, _gTsemTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(300); ++ ++ _gTsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(5000); ++ ++ _gTsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (_gTsemTestCnt != 5) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTsemTestCnt=%d)\n", __FUNCTION__, _gTsemTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ _gTsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 5000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (eRet != CAM_OS_OK) ++ { ++ CamOsPrintf("%s: step 3 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int ThreadTestTsem2(void *pUserData) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTsemTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTsemTestCnt=%d)\n", __FUNCTION__, _gTsemTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ _gTsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTsemTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTsemTestCnt=%d)\n", __FUNCTION__, _gTsemTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTsemTestCnt != 4) ++ { ++ CamOsPrintf("%s: step 3 fail!(_gTsemTestCnt=%d)\n", __FUNCTION__, _gTsemTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ _gTsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (_gTsemTestCnt != 6) ++ { ++ CamOsPrintf("%s: step 4 fail!(_gTsemTestCnt=%d)\n", __FUNCTION__, _gTsemTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (eRet != CAM_OS_TIMEOUT) ++ { ++ CamOsPrintf("%s: step 5 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_RW_SEMAPHORE ++static uint32_t _gRwsemTestCnt = 0; ++CamOsRwsem_t tCamOsRwsem; ++CamOsThread tRwsemThread0, tRwsemThread1, tRwsemThread2; ++ ++static int CamOsRwsemTestEntry0(void *pUserData) ++{ ++ CamOsRwsem_t *tpRwsem = (CamOsRwsem_t *)pUserData; ++ ++ CamOsPrintf("%s CamOsRwsemDownRead start\n", __FUNCTION__); ++ CamOsRwsemDownRead(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownRead end\n", __FUNCTION__); ++ ++ CamOsMsSleep(2000); ++ ++ if (_gRwsemTestCnt != 0) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gRwsemTestCnt=%d)\n", __FUNCTION__, _gRwsemTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemUpRead\n", __FUNCTION__); ++ CamOsRwsemUpRead(tpRwsem); ++ ++ CamOsMsSleep(50); ++ ++ if (_gRwsemTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gRwsemTestCnt=%d)\n", __FUNCTION__, _gRwsemTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemDownWrite start\n", __FUNCTION__); ++ CamOsRwsemDownWrite(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownWrite end\n", __FUNCTION__); ++ ++ CamOsMsSleep(1500); ++ ++ _gRwsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsRwsemUpWrite\n", __FUNCTION__); ++ CamOsRwsemUpWrite(tpRwsem); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int CamOsRwsemTestEntry1(void *pUserData) ++{ ++ CamOsRwsem_t *tpRwsem = (CamOsRwsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(20); ++ CamOsPrintf("%s CamOsRwsemTryDownRead start\n", __FUNCTION__); ++ if (CAM_OS_OK != (eRet = CamOsRwsemTryDownRead(tpRwsem))) ++ { ++ CamOsPrintf("%s: step 1 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsRwsemTryDownRead end\n", __FUNCTION__); ++ ++ CamOsMsSleep(2000); ++ ++ if (_gRwsemTestCnt != 0) ++ { ++ CamOsPrintf("%s: step 2 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemUpRead\n", __FUNCTION__); ++ CamOsRwsemUpRead(tpRwsem); ++ ++ CamOsMsSleep(50); ++ ++ if (_gRwsemTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 3 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ CamOsPrintf("%s CamOsRwsemDownWrite start\n", __FUNCTION__); ++ CamOsRwsemDownWrite(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownWrite end\n", __FUNCTION__); ++ ++ if (_gRwsemTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 4 fail!(_gRwsemTestCnt=%d)\n", __FUNCTION__, _gRwsemTestCnt); ++ return -1; ++ } ++ ++ _gRwsemTestCnt++; ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsRwsemUpWrite\n", __FUNCTION__); ++ CamOsRwsemUpWrite(tpRwsem); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int CamOsRwsemTestEntry2(void *pUserData) ++{ ++ CamOsRwsem_t *tpRwsem = (CamOsRwsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(50); ++ ++ CamOsPrintf("%s CamOsRwsemTryDownWrite start\n", __FUNCTION__); ++ if (CAM_OS_RESOURCE_BUSY != (eRet = CamOsRwsemTryDownWrite(tpRwsem))) ++ { ++ CamOsPrintf("%s: step 1 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsRwsemTryDownWrite end\n", __FUNCTION__); ++ ++ CamOsPrintf("%s CamOsRwsemDownWrite start\n", __FUNCTION__); ++ CamOsRwsemDownWrite(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownWrite end\n", __FUNCTION__); ++ ++ _gRwsemTestCnt++; ++ ++ CamOsPrintf("%s CamOsRwsemUpWrite\n", __FUNCTION__); ++ CamOsRwsemUpWrite(tpRwsem); ++ ++ CamOsMsSleep(200); ++ ++ CamOsPrintf("%s CamOsRwsemDownRead start\n", __FUNCTION__); ++ CamOsRwsemDownRead(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownRead end\n", __FUNCTION__); ++ ++ if (_gRwsemTestCnt != 2 && _gRwsemTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gRwsemTestCnt=%d)\n", __FUNCTION__, _gRwsemTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemUpRead\n", __FUNCTION__); ++ CamOsRwsemUpRead(tpRwsem); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_MUTEX ++static uint32_t _gMutexTestCnt = 0; ++CamOsThreadAttrb_t tMutexThreadAttr; ++CamOsMutex_t tCamOsMutex; ++CamOsThread tMutexThread0, tMutexThread1, tMutexThread2; ++static void CamOsMutexTestEntry0(void *pUserData) ++{ ++ CamOsMutex_t *tpMutex = (CamOsMutex_t *)pUserData; ++ unsigned int i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMutexLock(tpMutex); ++ _gMutexTestCnt++; ++ CamOsPrintf("%s start count: %d\n\r", __FUNCTION__, _gMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsPrintf("%s end count: %d\n\r", __FUNCTION__, _gMutexTestCnt); ++ CamOsMutexUnlock(tpMutex); ++ CamOsMsSleep(1); ++ } ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++} ++ ++static void CamOsMutexTestEntry1(void *pUserData) ++{ ++ CamOsMutex_t *tpMutex = (CamOsMutex_t *)pUserData; ++ unsigned int i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMutexLock(tpMutex); ++ _gMutexTestCnt++; ++ CamOsPrintf("%s start count: %d\n\r", __FUNCTION__, _gMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsPrintf("%s end count: %d\n\r", __FUNCTION__, _gMutexTestCnt); ++ CamOsMutexUnlock(tpMutex); ++ CamOsMsSleep(1); ++ } ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++} ++ ++static void CamOsMutexTestEntry2(void *pUserData) ++{ ++ CamOsMutex_t *tpMutex = (CamOsMutex_t *)pUserData; ++ unsigned int i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMutexLock(tpMutex); ++ _gMutexTestCnt++; ++ CamOsPrintf("%s start count: %d\n\r", __FUNCTION__, _gMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsPrintf("%s end count: %d\n\r", __FUNCTION__, _gMutexTestCnt); ++ CamOsMutexUnlock(tpMutex); ++ CamOsMsSleep(1); ++ } ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++} ++ ++#endif ++ ++#ifdef TEST_CONDITION_WAIT ++static uint32_t _gCondTestCnt = 0; ++CamOsTcond_t tCamOsTcond; ++CamOsThread tTcondThread0, tTcondThread1, tTcondThread2; ++static int32_t CamOsTcondTestEntry0(void *pUserData) ++{ ++ CamOsTcond_t *pCond = (CamOsTcond_t *)pUserData; ++ ++ CamOsMsSleep(300); ++ ++ _gCondTestCnt++; ++ ++ CamOsPrintf("%s CamOsTcondSignal\n", __FUNCTION__); ++ CamOsTcondSignal(pCond); ++ ++ ++ CamOsPrintf("%s CamOsTcondSignal\n", __FUNCTION__); ++ CamOsTcondSignal(pCond); ++ ++ CamOsMsSleep(50); ++ ++ _gCondTestCnt++; ++ ++ CamOsPrintf("%s CamOsTcondSignalAll\n", __FUNCTION__); ++ CamOsTcondSignalAll(pCond); ++ ++ CamOsMsSleep(50); ++ ++ CamOsPrintf("%s CamOsTcondTimedWait start\n", __FUNCTION__); ++ if (CamOsTcondTimedWait(pCond, 500) != CAM_OS_TIMEOUT) ++ { ++ CamOsPrintf("%s: step 1 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsTcondTimedWait end(timeout)\n", __FUNCTION__); ++ ++ CamOsMsSleep(2000); ++ ++ _gCondTestCnt++; ++ ++ CamOsPrintf("%s CamOsTcondSignal\n", __FUNCTION__); ++ CamOsTcondSignal(pCond); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int32_t CamOsTcondTestEntry1(void *pUserData) ++{ ++ CamOsTcond_t *pCond = (CamOsTcond_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gCondTestCnt != 1 && _gCondTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gCondTestCnt=%d)\n", __FUNCTION__, _gCondTestCnt); ++ return -1; ++ } ++ ++ _gCondTestCnt++; ++ ++ CamOsMsSleep(30); ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gCondTestCnt != 4) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gCondTestCnt=%d)\n", __FUNCTION__, _gCondTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(30); ++ ++ CamOsPrintf("%s CamOsTcondTimedWait start\n", __FUNCTION__); ++ eRet = CamOsTcondTimedWait(pCond, 1000); ++ if (eRet != CAM_OS_TIMEOUT || _gCondTestCnt != 4) ++ { ++ CamOsPrintf("%s: step 3 fail!(_gCondTestCnt=%d)\n", __FUNCTION__, _gCondTestCnt); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsTcondTimedWait end(timeout)\n", __FUNCTION__); ++ ++ _gCondTestCnt++; ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int32_t CamOsTcondTestEntry2(void *pUserData) ++{ ++ CamOsRet_e eRet; ++ ++ CamOsTcond_t *pCond = (CamOsTcond_t *)pUserData; ++ ++ CamOsMsSleep(10); ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gCondTestCnt != 1 && _gCondTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gCondTestCnt=%d)\n", __FUNCTION__, _gCondTestCnt); ++ return -1; ++ } ++ ++ _gCondTestCnt++; ++ ++ CamOsMsSleep(30); ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gCondTestCnt != 4) ++ { ++ CamOsPrintf("%s: step 2 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ CamOsMsSleep(30); ++ ++ CamOsPrintf("%s CamOsTcondTimedWait start\n", __FUNCTION__); ++ eRet = CamOsTcondTimedWait(pCond, 5000); ++ if (eRet != CAM_OS_OK || _gCondTestCnt != 6) ++ { ++ CamOsPrintf("%s: step 3 fail!(_gCondTestCnt=%d)\n", __FUNCTION__, _gCondTestCnt); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsTcondTimedWait end(wakend)\n", __FUNCTION__); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_HASH ++struct HashTableElement_t ++{ ++ struct CamOsHListNode_t tHentry; ++ uint32_t nKey; ++ uint32_t nData; ++}; ++#endif ++ ++#ifdef TEST_TIMER ++static void _TimerCallback(unsigned long nDataAddr) ++{ ++ unsigned long *pnTimerMs = (unsigned long *)nDataAddr; ++ ++ CamOsPrintf("%s: timer ms=%lu\n", __FUNCTION__, *pnTimerMs); ++} ++#endif ++ ++#ifdef TEST_SPINLOCK ++static void _CamOsThreadTestSpinlock0(void *pUserdata) ++{ ++ s32 i = 0; ++ ++ for (i=0; i<500; i++) ++ { ++ CamOsPrintf("%s(%d)\n", __FUNCTION__, i); ++ } ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++} ++ ++static void _CamOsThreadTestSpinlock1(void *pUserdata) ++{ ++ s32 i = 0; ++ CamOsSpinlock_t stSpinlock; ++ ++ CamOsSpinInit(&stSpinlock); ++ ++ CamOsSpinLock(&stSpinlock); ++ //CamOsSpinLockIrqSave(&stSpinlock); ++ ++ ++ for (i=0; i<100; i++) ++ { ++ CamOsPrintf("\033[1;34m%s in Spinlock (%d)\033[m\n", __FUNCTION__, i); ++ } ++ ++ CamOsSpinUnlock(&stSpinlock); ++ //CamOsSpinUnlockIrqRestore(&stSpinlock); ++ ++ for (i=100; i<500; i++) ++ { ++ CamOsPrintf("%s(%d)\n", __FUNCTION__, i); ++ } ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++} ++#endif ++ ++static int __init KernelTestInit(void) ++{ ++// Variables Declaration ++#ifdef TEST_THREAD_PRIORITY ++ uint32_t nThreadPrioCnt; ++ char szThreadName[16]; ++#endif ++#ifdef TEST_DIV64 ++ uint64_t nDividendU64 = 0, nDivisorU64 = 0, nResultU64 = 0, nRemainderU64 = 0; ++ int64_t nDividendS64 = 0, nDivisorS64 = 0, nResultS64 = 0, nRemainderS64 = 0; ++#endif ++#ifdef TEST_SYSTEM_TIME ++ int32_t nCnt = 0; ++ CamOsTimespec_t tTs; ++ struct rtc_time tTm; ++#endif ++#ifdef TEST_DIRECT_MEMORY ++ void *pVirtPtr1 = 0, *pVirtPtr2 = 0, *pVirtPtr3 = 0; ++ void *nMiuPtr1 = 0, *nMiuPtr2 = 0, *nMiuPtr3 = 0; ++ void *nPhysPtr1 = 0, *nPhysPtr2 = 0, *nPhysPtr3 = 0; ++#endif ++#ifdef TEST_PHY_MAP_VIRT ++ void *pVirtPtr; ++#endif ++#ifdef TEST_CACHE_ALLOC ++ CamOsMemCache_t tMemCache; ++ void *pMemCacheObj1, *pMemCacheObj2, *pMemCacheObj3; ++#endif ++#ifdef TEST_MEM_SIZE ++ CamOsMemSize_e eMemSize; ++ CamOsDramInfo_t Info = {0}; ++#endif ++ ++#ifdef TEST_ATOMIC_OPERATION ++ CamOsAtomic_t tAtomic; ++#endif ++ ++#ifdef TEST_BITMAP ++ const uint32_t nBitNum=128; ++ CAM_OS_DECLARE_BITMAP(aBitmap, nBitNum); ++#endif ++ ++#ifdef TEST_HASH ++ uint32_t nItemNum; ++ CAM_OS_DEFINE_HASHTABLE(aHashTable, 8); ++ struct HashTableElement_t tHListNode0, tHListNode1, tHListNode2, tHListNode3, tHListNode4, *ptHListNode; ++#endif ++ ++#ifdef TEST_IDR ++ CamOsIdr_t tIdr; ++ uint32_t nIdrData1=11111, nIdrData2=22222, nIdrData3=33333, *pnIdrDataPtr; ++ int32_t nIdrId1, nIdrId2, nIdrId3; ++#endif ++ ++#ifdef TEST_TIMER ++ CamOsTimer_t tTimer; ++ unsigned long nTimerMs; ++#endif ++ ++#ifdef TEST_SPINLOCK ++ CamOsThread SpinlockTaskHandle0, SpinlockTaskHandle1; ++#endif ++ ++// Test Function ++#ifdef TEST_DIRECT_MEMORY ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test direct memory\n"); ++ CamOsPrintf("=================================\n"); ++ ++ CamOsPrintf(KERN_INFO "Test DirectMem start\n"); ++ CamOsDirectMemAlloc("AAAAA", 1024, &pVirtPtr1, &nPhysPtr1, &nMiuPtr1); ++ CamOsPrintf(KERN_INFO " VirtAddr: 0x%08X\n", (uint32_t)pVirtPtr1); ++ CamOsPrintf(KERN_INFO " PhysAddr: 0x%08X\n", (uint32_t)CamOsDirectMemMiuToPhys(nMiuPtr1)); ++ CamOsPrintf(KERN_INFO " MiuAddr: 0x%08X\n", (uint32_t)CamOsDirectMemPhysToMiu(nPhysPtr1)); ++ ++ CamOsDirectMemAlloc("BBBBB", 2048, &pVirtPtr2, &nPhysPtr2, &nMiuPtr2); ++ CamOsPrintf(KERN_INFO " VirtAddr: 0x%08X\n", (uint32_t)pVirtPtr2); ++ CamOsPrintf(KERN_INFO " PhysAddr: 0x%08X\n", (uint32_t)CamOsDirectMemMiuToPhys(nMiuPtr2)); ++ CamOsPrintf(KERN_INFO " MiuAddr: 0x%08X\n", (uint32_t)CamOsDirectMemPhysToMiu(nPhysPtr2)); ++ ++ CamOsDirectMemAlloc("CCCCC", 2048, &pVirtPtr3, &nPhysPtr3, &nMiuPtr3); ++ CamOsPrintf(KERN_INFO " VirtAddr: 0x%08X\n", (uint32_t)pVirtPtr3); ++ CamOsPrintf(KERN_INFO " PhysAddr: 0x%08X\n", (uint32_t)CamOsDirectMemMiuToPhys(nMiuPtr3)); ++ CamOsPrintf(KERN_INFO " MiuAddr: 0x%08X\n", (uint32_t)CamOsDirectMemPhysToMiu(nPhysPtr3)); ++ ++ CamOsPrintf(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsPrintf(KERN_INFO "Release DMEM BBBBB\n"); ++ CamOsDirectMemRelease(pVirtPtr2, 2048); ++ ++ CamOsPrintf(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsPrintf(KERN_INFO "Release DMEM AAAAA\n"); ++ CamOsDirectMemRelease(pVirtPtr1, 1024); ++ ++ CamOsPrintf(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsPrintf(KERN_INFO "Release DMEM CCCCC\n"); ++ CamOsDirectMemRelease(pVirtPtr3, 2048); ++ ++ CamOsPrintf(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsPrintf(KERN_INFO "Test DirectMem end\n"); ++#endif ++ ++#ifdef TEST_TIME_AND_SLEEP ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test time and sleep\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsThreadCreate(&tTimeThread0, NULL, (void *)ThreadTestTimeSleep, NULL); ++ CamOsMsSleep(15000); ++ CamOsThreadStop(tTimeThread0); ++#endif ++ ++#ifdef TEST_PHY_MAP_VIRT ++ #define TEST_PHY_MEM_ADDR 0X20200000 ++ #define TEST_PHY_MEM_SIZE 0x100000 ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test phy mem map to virtual addr\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test non-cache mapping:\n"); ++ pVirtPtr = CamOsPhyMemMap((void *)TEST_PHY_MEM_ADDR, TEST_PHY_MEM_SIZE, 0); ++ CamOsPrintf(" PhysAddr: 0x%08X\n", TEST_PHY_MEM_ADDR); ++ CamOsPrintf(" VirtAddr: 0x%08X\n", (uint32_t)pVirtPtr); ++ CamOsPhyMemUnMap(pVirtPtr, TEST_PHY_MEM_SIZE); ++ CamOsPrintf("Test cache mapping:\n"); ++ pVirtPtr = CamOsPhyMemMap((void *)TEST_PHY_MEM_ADDR, TEST_PHY_MEM_SIZE, 1); ++ CamOsPrintf(" PhysAddr: 0x%08X\n", TEST_PHY_MEM_ADDR); ++ CamOsPrintf(" VirtAddr: 0x%08X\n", (uint32_t)pVirtPtr); ++ CamOsPhyMemUnMap(pVirtPtr, TEST_PHY_MEM_SIZE); ++#endif ++ ++#ifdef TEST_CACHE_ALLOC ++ #define MEMORY_CACHE_OBJECT_SIZE 0x50 ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test memory cache\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test non-HW cache alignment mapping:\n"); ++ if (CAM_OS_OK == CamOsMemCacheCreate(&tMemCache, "MemCacheTest", MEMORY_CACHE_OBJECT_SIZE, 0)) ++ { ++ pMemCacheObj1 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object1 address: 0x%08X\n", pMemCacheObj1); ++ pMemCacheObj2 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object2 address: 0x%08X\n", pMemCacheObj2); ++ pMemCacheObj3 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object3 address: 0x%08X\n", pMemCacheObj3); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj1); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj2); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj3); ++ CamOsMemCacheDestroy(&tMemCache); ++ } ++ else ++ CamOsPrintf("CamOsMemCacheCreate fail!\n"); ++ ++ CamOsPrintf("Test HW cache alignment mapping:\n"); ++ if (CAM_OS_OK == CamOsMemCacheCreate(&tMemCache, "MemCacheTest", MEMORY_CACHE_OBJECT_SIZE, 1)) ++ { ++ pMemCacheObj1 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object1 address: 0x%08X\n", pMemCacheObj1); ++ pMemCacheObj2 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object2 address: 0x%08X\n", pMemCacheObj2); ++ pMemCacheObj3 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object3 address: 0x%08X\n", pMemCacheObj3); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj1); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj2); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj3); ++ CamOsMemCacheDestroy(&tMemCache); ++ } ++ else ++ CamOsPrintf("CamOsMemCacheCreate fail!\n"); ++#endif ++ ++#ifdef TEST_THREAD ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test thread\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsAtomicSet(&_gtThreadAtomic, 0); ++ CamOsPrintf("### Priority: ThreadTest1 < ThreadTest2\n"); ++ tThreadAttr.nPriority = 1; ++ tThreadAttr.nStackSize = 3072; ++ CamOsThreadCreate(&tThread0, &tThreadAttr, (void *)ThreadTest1, NULL); ++ tThreadAttr.nPriority = 10; ++ tThreadAttr.nStackSize = 3072; ++ CamOsThreadCreate(&tThread1, &tThreadAttr, (void *)ThreadTest2, NULL); ++ ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 2) ++ CamOsMsSleep(100); ++ ++ CamOsMsSleep(1000); ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 4) ++ CamOsMsSleep(100); ++ ++ CamOsMsSleep(2000); ++ ++ CamOsPrintf("### Wake up ThreadTest2\n"); ++ CamOsThreadWakeUp(tThread1); ++ ++ CamOsMsSleep(1000); ++ ++ CamOsThreadStop(tThread0); ++ CamOsThreadStop(tThread1); ++#endif ++ ++#ifdef TEST_THREAD_PRIORITY ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test thread Priority\n"); ++ CamOsPrintf("=================================\n"); ++ ++ for (nThreadPrioCnt=0; nThreadPrioCnt %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm.tm_year+1900, ++ tTm.tm_mon+1, ++ tTm.tm_mday, ++ tTm.tm_wday, ++ tTm.tm_hour, ++ tTm.tm_min, ++ tTm.tm_sec); ++ ++ tTs.nSec += 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++ ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ rtc_time_to_tm(tTs.nSec, &tTm); ++ CamOsPrintf("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm.tm_year+1900, ++ tTm.tm_mon+1, ++ tTm.tm_mday, ++ tTm.tm_wday, ++ tTm.tm_hour, ++ tTm.tm_min, ++ tTm.tm_sec); ++ ++ tTs.nSec -= 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++#endif ++ ++#ifdef TEST_MEM_SIZE ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test memory size\n"); ++ CamOsPrintf("=================================\n"); ++ eMemSize = CamOsPhysMemSize(); ++ CamOsPrintf("System has %dMB physical memory\n", 1<<(uint32_t)eMemSize); ++ CamOsDramInfo(&Info); ++ CamOsPrintf("DRAM Info: Size %d Type %d Bus %d\n", Info.nBytes, Info.nType, Info.nBusWidth); ++#endif ++ ++#ifdef TEST_CHIP_ID ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test chip ID\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Chip ID: 0x%X Revision: 0x%X\n", CamOsChipId(), CamOsChipRevision()); ++#endif ++ ++#ifdef TEST_ATOMIC_OPERATION ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test atomic operation\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("AtomicSet 10\n"); ++ CamOsAtomicSet(&tAtomic, 10); ++ CamOsPrintf("AtomicRead : %d\n", CamOsAtomicRead(&tAtomic)); ++ CamOsPrintf("CamOsAtomicAddReturn (5) : %d\n", CamOsAtomicAddReturn(&tAtomic, 5)); ++ CamOsPrintf("CamOsAtomicSubReturn (3) : %d\n", CamOsAtomicSubReturn(&tAtomic, 3)); ++ CamOsPrintf("CamOsAtomicSubAndTest (2) : %d\n", CamOsAtomicSubAndTest(&tAtomic, 2)); ++ CamOsPrintf("CamOsAtomicSubAndTest (10) : %d\n", CamOsAtomicSubAndTest(&tAtomic, 10)); ++ CamOsPrintf("CamOsAtomicIncReturn : %d\n", CamOsAtomicIncReturn(&tAtomic)); ++ CamOsPrintf("CamOsAtomicDecReturn : %d\n", CamOsAtomicDecReturn(&tAtomic)); ++ CamOsPrintf("CamOsAtomicDecReturn : %d\n", CamOsAtomicDecReturn(&tAtomic)); ++ CamOsPrintf("CamOsAtomicIncAndTest : %d\n", CamOsAtomicIncAndTest(&tAtomic)); ++ CamOsPrintf("CamOsAtomicIncAndTest : %d\n", CamOsAtomicIncAndTest(&tAtomic)); ++ CamOsPrintf("CamOsAtomicDecAndTest : %d\n", CamOsAtomicDecAndTest(&tAtomic)); ++ CamOsPrintf("CamOsAtomicDecAndTest : %d\n", CamOsAtomicDecAndTest(&tAtomic)); ++ CamOsPrintf("CamOsAtomicAddNegative (1) : %d\n", CamOsAtomicAddNegative(&tAtomic, 1)); ++ CamOsPrintf("CamOsAtomicAddNegative (1) : %d\n", CamOsAtomicAddNegative(&tAtomic, 1)); ++ CamOsPrintf("CamOsAtomicAddNegative (-3) : %d\n", CamOsAtomicAddNegative(&tAtomic, -3)); ++#endif ++ ++#ifdef TEST_BITMAP ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test bitmap operation\n"); ++ CamOsPrintf("=================================\n"); ++ CAM_OS_BITMAP_CLEAR(aBitmap); ++ CamOsPrintf("Set bit 0, 1, 2, 37, 98\n"); ++ CAM_OS_SET_BIT(0, aBitmap); ++ CAM_OS_SET_BIT(1, aBitmap); ++ CAM_OS_SET_BIT(2, aBitmap); ++ CAM_OS_SET_BIT(37, aBitmap); ++ CAM_OS_SET_BIT(98, aBitmap); ++ CamOsPrintf("\ttest bit 0: %d\n", CAM_OS_TEST_BIT(0, aBitmap)); ++ CamOsPrintf("\ttest bit 1: %d\n", CAM_OS_TEST_BIT(1, aBitmap)); ++ CamOsPrintf("\ttest bit 2: %d\n", CAM_OS_TEST_BIT(2, aBitmap)); ++ CamOsPrintf("\ttest bit 3: %d\n", CAM_OS_TEST_BIT(3, aBitmap)); ++ CamOsPrintf("\ttest bit 30: %d\n", CAM_OS_TEST_BIT(30, aBitmap)); ++ CamOsPrintf("\ttest bit 37: %d\n", CAM_OS_TEST_BIT(37, aBitmap)); ++ CamOsPrintf("\ttest bit 80: %d\n", CAM_OS_TEST_BIT(80, aBitmap)); ++ CamOsPrintf("\ttest bit 98: %d\n", CAM_OS_TEST_BIT(98, aBitmap)); ++ CamOsPrintf("\ttest bit 127: %d\n", CAM_OS_TEST_BIT(127, aBitmap)); ++ CamOsPrintf("\tfirst zero bit: %u\n", CAM_OS_FIND_FIRST_ZERO_BIT(aBitmap, nBitNum)); ++ CamOsPrintf("Clear bit 2, 98\n"); ++ CAM_OS_CLEAR_BIT(2, aBitmap); ++ CAM_OS_CLEAR_BIT(98, aBitmap); ++ CamOsPrintf("\ttest bit 2: %d\n", CAM_OS_TEST_BIT(2, aBitmap)); ++ CamOsPrintf("\ttest bit 98: %d\n", CAM_OS_TEST_BIT(98, aBitmap)); ++ CamOsPrintf("\tfirst zero bit: %u\n", CAM_OS_FIND_FIRST_ZERO_BIT(aBitmap, nBitNum)); ++#endif ++ ++#ifdef TEST_HASH ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test hash operation\n"); ++ CamOsPrintf("=================================\n"); ++ tHListNode0.nKey = 102; ++ tHListNode0.nData = 1021; ++ tHListNode1.nKey = 1872; ++ tHListNode1.nData = 18721; ++ tHListNode2.nKey = 102; ++ tHListNode2.nData = 1022; ++ tHListNode3.nKey = 1872; ++ tHListNode3.nData = 18722; ++ tHListNode4.nKey = 102; ++ tHListNode4.nData = 1023; ++ CamOsPrintf("Add 3 items with key 102 and 2 items with key 1872.\n"); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode0.tHentry, tHListNode0.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode1.tHentry, tHListNode1.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode2.tHentry, tHListNode2.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode3.tHentry, tHListNode3.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode4.tHentry, tHListNode4.nKey); ++ CamOsPrintf("Get items with key 102: \n"); ++ nItemNum = 0; ++ CAM_OS_HASH_FOR_EACH_POSSIBLE(aHashTable, ptHListNode, tHentry, 102) ++ { ++ CamOsPrintf("\titem %u: data=%u\n", nItemNum, ptHListNode->nData); ++ nItemNum++; ++ } ++ ++ CamOsPrintf("Get items with key 1872: \n"); ++ nItemNum = 0; ++ CAM_OS_HASH_FOR_EACH_POSSIBLE(aHashTable, ptHListNode, tHentry, 1872) ++ { ++ CamOsPrintf("\titem %u: data=%u\n", nItemNum, ptHListNode->nData); ++ nItemNum++; ++ } ++ ++ CamOsPrintf("Delete one items with key 1872.\n"); ++ CAM_OS_HASH_DEL(&tHListNode3.tHentry); ++ CamOsPrintf("Get items with key 1872: \n"); ++ nItemNum = 0; ++ CAM_OS_HASH_FOR_EACH_POSSIBLE(aHashTable, ptHListNode, tHentry, 1872) ++ { ++ CamOsPrintf("\titem %u: data=%u\n", nItemNum, ptHListNode->nData); ++ nItemNum++; ++ } ++#endif ++ ++#ifdef TEST_IDR ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test IDR operation\n"); ++ CamOsPrintf("=================================\n"); ++ if (CAM_OS_OK == CamOsIdrInit(&tIdr)) ++ { ++ CamOsPrintf("Alloc data1(=%u) in 100~200\n", nIdrData1); ++ nIdrId1 = CamOsIdrAlloc(&tIdr, (void *)&nIdrData1, 100, 200); ++ CamOsPrintf("Alloc data2(=%u) in 100~200\n", nIdrData2); ++ nIdrId2 = CamOsIdrAlloc(&tIdr, (void *)&nIdrData2, 100, 200); ++ CamOsPrintf("Alloc data3(=%u) in 500~\n", nIdrData3); ++ nIdrId3 = CamOsIdrAlloc(&tIdr, (void *)&nIdrData3, 500, 0); ++ pnIdrDataPtr = (uint32_t*)CamOsIdrFind(&tIdr, nIdrId1); ++ CamOsPrintf("ID1 = %d, find data = %u\n", nIdrId1, *pnIdrDataPtr); ++ pnIdrDataPtr = (uint32_t*)CamOsIdrFind(&tIdr, nIdrId2); ++ CamOsPrintf("ID2 = %d, find data = %u\n", nIdrId2, *pnIdrDataPtr); ++ pnIdrDataPtr = (uint32_t*)CamOsIdrFind(&tIdr, nIdrId3); ++ CamOsPrintf("ID3 = %d, find data = %u\n", nIdrId3, *pnIdrDataPtr); ++ ++ CamOsPrintf("Remove ID3(=%d) ... ", nIdrId3); ++ CamOsIdrRemove(&tIdr, nIdrId3); ++ if (NULL == CamOsIdrFind(&tIdr, nIdrId3)) ++ CamOsPrintf("success!\n"); ++ else ++ CamOsPrintf("fail!\n"); ++ ++ CamOsIdrDestroy(&tIdr); ++ } ++ else ++ CamOsPrintf("CamOsIdrInit fail!\n"); ++#endif ++ ++#ifdef TEST_TIMER ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test timer operation\n"); ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("[Step 1] add timer to 2000ms, then sleep 2100ms ... \n"); ++ CamOsTimerInit(&tTimer); ++ nTimerMs = 2000; ++ CamOsTimerAdd(&tTimer, nTimerMs, (void*)&nTimerMs, _TimerCallback); ++ CamOsMsSleep(2100); ++ if (CamOsTimerDelete(&tTimer)) ++ CamOsPrintf("fail!\n\n"); ++ else ++ CamOsPrintf("success!\n\n"); ++ ++ CamOsPrintf("[Step 2] add timer to 1000ms, modify to 1500ms in 300ms, then sleep 1600ms ... \n"); ++ CamOsTimerInit(&tTimer); ++ nTimerMs = 1000; ++ CamOsTimerAdd(&tTimer, nTimerMs, (void*)&nTimerMs, _TimerCallback); ++ CamOsMsSleep(300); ++ nTimerMs = 1500; ++ CamOsTimerModify(&tTimer, nTimerMs); ++ CamOsMsSleep(1600); ++ if (CamOsTimerDelete(&tTimer)) ++ CamOsPrintf("fail!\n\n"); ++ else ++ CamOsPrintf("success!\n\n"); ++ ++ CamOsPrintf("[Step 3] add timer to 3000ms, sleep 1000ms, then delete timer ... \n"); ++ CamOsTimerInit(&tTimer); ++ nTimerMs = 3000; ++ CamOsTimerAdd(&tTimer, nTimerMs, (void*)&nTimerMs, _TimerCallback); ++ CamOsMsSleep(1000); ++ if (!CamOsTimerDelete(&tTimer)) ++ CamOsPrintf("fail!\n\n"); ++ else ++ CamOsPrintf("success!\n\n"); ++#endif ++ ++#ifdef TEST_SPINLOCK ++ CamOsPrintf("=================================\n"); ++ CamOsPrintf("Test Spinlock\n"); ++ CamOsPrintf("=================================\n"); ++ ++ CamOsThreadCreate(&SpinlockTaskHandle0, NULL, (void *)_CamOsThreadTestSpinlock0, NULL); ++ CamOsThreadCreate(&SpinlockTaskHandle1, NULL, (void *)_CamOsThreadTestSpinlock1, NULL); ++ ++ CamOsMsSleep(20000); ++ ++ CamOsThreadStop(SpinlockTaskHandle0); ++ CamOsThreadStop(SpinlockTaskHandle1); ++#endif ++ ++ return 0; ++} ++ ++static void __exit KernelTestExit(void) ++{ ++ CamOsPrintf(KERN_INFO "Goodbye\n"); ++} ++ ++module_init(KernelTestInit); ++module_exit(KernelTestExit); +diff --git a/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_test.c b/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_test.c +new file mode 100755 +index 000000000000..d8b2d1ca589a +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_test.c +@@ -0,0 +1,1564 @@ ++/* ++* cam_os_wrapper_test.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++ ++#ifdef CAM_OS_RTK ++#include "sys_sys_core.h" ++#include "sys_sys_isw_cli.h" ++#endif ++ ++static u32 _gMutexTestCnt = 0; ++static u32 _gTestCnt = 0; ++static void _TestCamOsThread(void); ++static void _TestCamOsThreadPriority(void); ++static void _TestCamOsMutex(void); ++static void _TestCamOsDmem(void); ++static void _TestCamOsMem(void); ++static void _TestCamOsPhyMapVirt(void); ++static void _TestCamOsTimer(void); ++static void _TestCamOsTsem(void); ++static void _TestCamOsRwsem(void); ++static void _TestCamOsDiv64(void); ++static void _TestCamOsSystemTime(void); ++static void _TestCamOsPhysMemSize(void); ++static void _TestCamOsChipId(void); ++static void _TestCamOsTcond(void); ++static void _TestCamOsBitmap(void); ++static void _TestCamOsHash(void); ++static void _TestCamOsIdr(void); ++#ifdef CAM_OS_RTK ++static void _TestCamOsTimerCallback(void); ++static void _TestCamOsCacheAlloc(void); ++#endif ++static void _TestCamOsPanic(void); ++static void _TestCamOsSpinlock(void); ++ ++typedef void (*_TEST_FUNC_PTR)(void); ++ ++typedef struct ++{ ++ _TEST_FUNC_PTR pFnTest; ++ u8 *pTestDesc; ++} CamOsWrapperTestItem_t, *pCamOsWrapperTestItem; ++ ++static const CamOsWrapperTestItem_t aCamOsWrapperTestItemTbl[] = ++{ ++ {_TestCamOsThread, (u8*)"test thread function"}, ++ {_TestCamOsThreadPriority, (u8*)"test thread priority function"}, ++ {_TestCamOsMutex, (u8*)"test mutex function"}, ++ {_TestCamOsDmem, (u8*)"test direct memory allocation"}, ++ {_TestCamOsMem, (u8*)"test memory allocation"}, ++ {_TestCamOsPhyMapVirt, (u8*)"test physical memory map to virtual address"}, ++ {_TestCamOsTimer, (u8*)"test timer function"}, ++ {_TestCamOsTsem, (u8*)"test thread semaphore function"}, ++ {_TestCamOsRwsem, (u8*)"test rw semaphore function"}, ++ {_TestCamOsTcond, (u8*)"test thread condition wait function"}, ++ {_TestCamOsBitmap, (u8*)"test bitmap operation"}, ++ {_TestCamOsHash, (u8*)"test hash operation"}, ++ {_TestCamOsIdr, (u8*)"test IDR operation"}, ++ {_TestCamOsDiv64, (u8*)"test 64-bit division"}, ++ {_TestCamOsSystemTime, (u8*)"test system time function"}, ++ {_TestCamOsPhysMemSize, (u8*)"test physical memory size"}, ++ {_TestCamOsChipId, (u8*)"test chip ID"}, ++#ifdef CAM_OS_RTK ++ {_TestCamOsTimerCallback, (u8*)"test timer callback function"}, ++ {_TestCamOsCacheAlloc, (u8*)"test cache memory allocation"}, ++#endif ++ {_TestCamOsPanic, (u8*)"test panic"}, ++ {_TestCamOsSpinlock, (u8*)"test spinlock"}, ++ {NULL, (u8*)"test all function"}, ++}; ++ ++#define TEST_ITEM_NUM (sizeof(aCamOsWrapperTestItemTbl)/sizeof(CamOsWrapperTestItem_t)) ++ ++static void _CamOsWrapperShowTestMenu(void) ++{ ++ s32 i; ++ ++ CamOsPrintf("cam_os_wrapper test menu: \n"); ++ ++ for (i = 0; i < TEST_ITEM_NUM; i++) ++ { ++ CamOsPrintf("\t%2d) %s\r\n", i, aCamOsWrapperTestItemTbl[i].pTestDesc); ++ } ++} ++ ++#ifdef CAM_OS_RTK ++s32 CamOsWrapperTest(CLI_t *pCli, char *p) ++{ ++ s32 i, nParamCnt; ++ u32 nCaseNum = 0; ++ char *pEnd; ++ ++ ++ nParamCnt = CliTokenCount(pCli); ++ ++ if(nParamCnt < 1) ++ { ++ _CamOsWrapperShowTestMenu(); ++ return eCLI_PARSE_INPUT_ERROR; ++ } ++ ++ for(i = 0; i < nParamCnt; i++) ++ { ++ pCli->tokenLvl++; ++ p = CliTokenPop(pCli); ++ if(i == 0) ++ { ++ //CLIDEBUG(("p: %s, len: %d\n", p, strlen(p))); ++ //*pV = _strtoul(p, &pEnd, base); ++ nCaseNum = strtoul(p, &pEnd, 10); ++ //CLIDEBUG(("*pEnd = %d\n", *pEnd)); ++ if(p == pEnd || *pEnd) ++ { ++ CamOsPrintf("Invalid input\n"); ++ return eCLI_PARSE_ERROR; ++ } ++ } ++ } ++ ++ if (nCaseNum < TEST_ITEM_NUM) ++ { ++ if (nCaseNum == (TEST_ITEM_NUM - 1)) ++ { ++ for (i = 0; i < TEST_ITEM_NUM; i++) ++ { ++ if (aCamOsWrapperTestItemTbl[i].pFnTest) ++ { ++ CamOsPrintf("===============================================\r\n"); ++ CamOsPrintf("%s\r\n", aCamOsWrapperTestItemTbl[i].pTestDesc); ++ CamOsPrintf("===============================================\r\n"); ++ aCamOsWrapperTestItemTbl[i].pFnTest(); ++ CamOsPrintf("\r\n"); ++ } ++ } ++ } ++ else ++ { ++ if (aCamOsWrapperTestItemTbl[nCaseNum].pFnTest) ++ { ++ CamOsPrintf("===============================================\r\n"); ++ CamOsPrintf("%s\r\n", aCamOsWrapperTestItemTbl[nCaseNum].pTestDesc); ++ CamOsPrintf("===============================================\r\n"); ++ aCamOsWrapperTestItemTbl[nCaseNum].pFnTest(); ++ } ++ } ++ } ++ else ++ { ++ _CamOsWrapperShowTestMenu(); ++ return eCLI_PARSE_ERROR; ++ } ++ ++ return eCLI_PARSE_OK; ++} ++#else ++int main(int argc, char *argv[]) ++{ ++ u32 nCaseNum = 0; ++ s32 i; ++ ++ if(argc < 2) ++ { ++ _CamOsWrapperShowTestMenu(); ++ return -1; ++ } ++ ++ nCaseNum = atoi(argv[1]); ++ ++ if (nCaseNum < TEST_ITEM_NUM) ++ { ++ if (nCaseNum == (TEST_ITEM_NUM - 1)) ++ { ++ for (i = 0; i < TEST_ITEM_NUM; i++) ++ { ++ if (aCamOsWrapperTestItemTbl[i].pFnTest) ++ { ++ CamOsPrintf("===============================================\r\n"); ++ CamOsPrintf("%s\r\n", aCamOsWrapperTestItemTbl[i].pTestDesc); ++ CamOsPrintf("===============================================\r\n"); ++ aCamOsWrapperTestItemTbl[i].pFnTest(); ++ CamOsPrintf("\r\n"); ++ } ++ } ++ } ++ else ++ { ++ if (aCamOsWrapperTestItemTbl[nCaseNum].pFnTest) ++ { ++ CamOsPrintf("===============================================\r\n"); ++ CamOsPrintf("%s\r\n", aCamOsWrapperTestItemTbl[nCaseNum].pTestDesc); ++ CamOsPrintf("===============================================\r\n"); ++ aCamOsWrapperTestItemTbl[nCaseNum].pFnTest(); ++ } ++ } ++ } ++ else ++ { ++ _CamOsWrapperShowTestMenu(); ++ return -1; ++ } ++ ++ return 0; ++} ++#endif ++ ++CamOsAtomic_t _gtThreadAtomic; ++ ++static void _CamOsThreadTestEntry0(void *pUserdata) ++{ ++ s32 *pnArg = (s32 *)pUserdata; ++ s32 i = 0; ++ ++ for(i = 0; i < 5; i++) ++ { ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry0 (sleep %dms) count: %d\n", __LINE__, *pnArg, i); ++ CamOsMsSleep(*pnArg); ++ } ++} ++ ++static int _CamOsThreadTestEntry1(void *pUserData) ++{ ++ s32 nTestCounter=0; ++ ++ CamOsMsSleep(10); ++ ++ while (nTestCounter < 10000) ++ { ++ nTestCounter++; ++ if ((nTestCounter % 500) == 0) ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ } ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 3) ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s free run end\n", __FUNCTION__); ++#ifdef CAM_OS_RTK ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 4) ++ { ++ if (CamOsAtomicRead(&_gtThreadAtomic) == 3) ++ { ++ CamOsPrintf("%s enter CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsThreadSchedule(0, 2000); ++ CamOsPrintf("%s leave CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ } ++ ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ CamOsMsSleep(300); ++ } ++#endif ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int _CamOsThreadTestEntry2(void *pUserData) ++{ ++ s32 nTestCounter=0; ++ ++ CamOsMsSleep(10); ++ ++ while (nTestCounter < 10000) ++ { ++ nTestCounter++; ++ if ((nTestCounter % 500) == 0) ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ } ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 3) ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s free run end\n", __FUNCTION__); ++#ifdef CAM_OS_RTK ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 6) ++ { ++ if (CamOsAtomicRead(&_gtThreadAtomic) == 4) ++ { ++ CamOsPrintf("%s enter CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsThreadSchedule(1, CAM_OS_MAX_TIMEOUT); ++ CamOsPrintf("%s leave CamOsThreadSchedule\n", __FUNCTION__); ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++ } ++ CamOsPrintf("%s run...\n", __FUNCTION__); ++ CamOsMsSleep(300); ++ } ++#endif ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static void _TestCamOsThread(void) ++{ ++ CamOsThread TaskHandle0, TaskHandle1; ++ CamOsThreadAttrb_t tAttr = {0}; ++ s32 nTaskArg0 = 1000, nTaskArg1 = 1500; ++ char szTaskName0[32], szTaskName1[32]; ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle0, &tAttr, (void *)_CamOsThreadTestEntry0, (void *)&nTaskArg0); ++ //CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread get taskid: %d\n", __LINE__, TaskHandle0.eHandleObj); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle1, &tAttr, (void *)_CamOsThreadTestEntry0, (void *)&nTaskArg1); ++ //CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread get taskid: %d\n", __LINE__, TaskHandle1.eHandleObj); ++ ++ CamOsMsSleep(1000); ++ CamOsThreadGetName(TaskHandle0, szTaskName0, sizeof(szTaskName0)); ++ CamOsThreadGetName(TaskHandle1, szTaskName1, sizeof(szTaskName1)); ++ CamOsPrintf("Test Get Name: %s %s\n", szTaskName0, szTaskName1); ++ ++ CamOsMsSleep(1000); ++ CamOsThreadSetName(TaskHandle0, "ABCDEFGHIJKLMNO"); ++ CamOsThreadSetName(TaskHandle1, "abcdefghijklmno"); ++ ++ CamOsMsSleep(1000); ++ CamOsThreadGetName(TaskHandle0, szTaskName0, sizeof(szTaskName0)); ++ CamOsThreadGetName(TaskHandle1, szTaskName1, sizeof(szTaskName1)); ++ CamOsPrintf("Test Get Name: %s %s\n", szTaskName0, szTaskName1); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ ++ CamOsAtomicSet(&_gtThreadAtomic, 0); ++ CamOsPrintf("### Priority: ThreadTest1 < ThreadTest2\n"); ++ tAttr.nPriority = 20; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle0, &tAttr, (void *)_CamOsThreadTestEntry1, NULL); ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle1, &tAttr, (void *)_CamOsThreadTestEntry2, NULL); ++ ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 2) ++ CamOsMsSleep(100); ++ ++ CamOsMsSleep(1000); ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++#ifdef CAM_OS_RTK ++ while (CamOsAtomicRead(&_gtThreadAtomic) < 4) ++ CamOsMsSleep(100); ++ ++ CamOsMsSleep(2000); ++ ++ CamOsPrintf("### Wake up _CamOsThreadTestEntry2\n"); ++ CamOsThreadWakeUp(TaskHandle1); ++ ++ CamOsMsSleep(1000); ++ ++ CamOsAtomicIncReturn(&_gtThreadAtomic); ++#endif ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread delete task\n", __LINE__); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread test end!!!\n", __LINE__); ++} ++ ++static int _CamOsThreadPrioTest(void *pUserData) ++{ ++ u32 *nThreadId = (u32 *)pUserData; ++ u32 i; ++ ++ CamOsPrintf("%s start Thread%d\n", __FUNCTION__, *nThreadId); ++ for (i = 0; i < 10; i++) ++ { ++ CamOsPrintf("Thread%d running\n", *nThreadId); ++ CamOsMsSleep(1000); ++ } ++ CamOsPrintf("%s break ThreadId%d\n", __FUNCTION__, *nThreadId); ++ ++ return 0; ++} ++ ++static void _TestCamOsThreadPriority(void) ++{ ++#define THREAD_PRIORITY_TEST_NUM 100 ++ CamOsThread TaskHandle[THREAD_PRIORITY_TEST_NUM]; ++ s32 nTaskArg[THREAD_PRIORITY_TEST_NUM]; ++ CamOsThreadAttrb_t tAttr = {0}; ++ u32 nThreadPrioCnt; ++ char szThreadName[16]; ++ ++ for (nThreadPrioCnt=0; nThreadPrioCnt 0x%08X\n", (u32)pPhysAddr, (u32)CamOsDirectMemPhysToMiu((void *)pPhysAddr)); ++ CamOsPrintf(" MiuToPhys 0x%08X -> 0x%08X\n", (u32)pMiuAddr, (u32)CamOsDirectMemMiuToPhys((void *)pMiuAddr)); ++ CamOsPrintf(" PhysToVirt 0x%08X -> 0x%08X\n", (u32)pPhysAddr, (u32)CamOsDirectMemPhysToVirt((void *)pPhysAddr)); ++ CamOsPrintf(" VirtToPhys 0x%08X -> 0x%08X\n", (u32)pVirtPtr, (u32)CamOsDirectMemVirtToPhys((void *)pVirtPtr)); ++ ++ CamOsPrintf("\nTest Cache / Noncache Access\n"); ++ CamOsPrintf(" write cached ptr=0x%08x, value = 0x%08x\n", (u32)pPhysAddr, 0x12345678); ++ *(u32 *)pPhysAddr = 0x12345678; ++ CamOsPrintf(" read cached ptr=0x%08x, value = 0x%08x\n", (u32)pPhysAddr, *(u32 *)pPhysAddr); ++ ++ CamOsPrintf(" read uncached ptr=0x%08x, value = 0x%08x\n", (u32)pVirtPtr, *(u32 *)pVirtPtr); ++ ++ CamOsPrintf(" write uncached ptr=0x%08x, value = 0x%08x\n", (u32)pVirtPtr, 0x87654321); ++ *(u32 *)pVirtPtr = 0x87654321; ++ CamOsPrintf(" read cached ptr=0x%08x, value = 0x%08x\n", (u32)pPhysAddr, *(u32 *)pPhysAddr); ++ CamOsPrintf(" read uncached ptr=0x%08x, value = 0x%08x\n", (u32)pVirtPtr, *(u32 *)pVirtPtr); ++ ++ CamOsPrintf(" flush cached ptr=0x%08x\n", (u32)pPhysAddr); ++ CamOsDirectMemFlush(pVirtPtr); ++ CamOsPrintf(" read cached ptr=0x%08x, value = 0x%08x\n", (u32)pPhysAddr, *(u32 *)pPhysAddr); ++ CamOsPrintf(" read uncached ptr=0x%08x, value = 0x%08x\n", (u32)pVirtPtr, *(u32 *)pVirtPtr); ++ ++ CamOsDirectMemRelease((u8 *)pVirtPtr, 1025); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem test end!!!\n", __LINE__); ++#else ++ void *pVirtPtr = NULL; ++ void *pMiuAddr = NULL; ++ ++ CamOsDirectMemAlloc("TESTDMEM", 1025, &pVirtPtr, NULL, &pMiuAddr); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsDirectMemAlloc get addr: pVirtPtr 0x%08X pMiuAddr 0x%08X\n", ++ __LINE__, (u32)pVirtPtr, (u32)pMiuAddr); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pVirtPtr, *(u32 *)pVirtPtr); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: write uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pVirtPtr, 0x87654321); ++ *(u32 *)pVirtPtr = 0x87654321; ++ ++ CamOsDirectMemFlush(pVirtPtr); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pVirtPtr, *(u32 *)pVirtPtr); ++ ++ CamOsDirectMemRelease((u8 *)pVirtPtr, 1025); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d]_TestCamOsDmem test end!!!\n", __LINE__); ++#endif ++} ++ ++static void _TestCamOsMem(void) ++{ ++ void *pUserPtr = NULL; ++ ++ // test CamOsMemAlloc ++ pUserPtr = CamOsMemAlloc(2048); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMemAlloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ memset(pUserPtr, 0x5A, 2048); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] value in address 0x%08X is 0x%08X\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsMemRelease(pUserPtr); ++ pUserPtr = NULL; ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRelease free buffer\n", __LINE__); ++ ++ // test CamOsMemCalloc ++ pUserPtr = CamOsMemCalloc(2048, 1); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMemCalloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] value in address 0x%08X is 0x%08X\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsMemRelease(pUserPtr); ++ pUserPtr = NULL; ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRelease free buffer\n", __LINE__); ++ ++ // test CamOsMemRealloc ++ pUserPtr = CamOsMemAlloc(2048); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CAM_OS_MemMalloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ pUserPtr = CamOsMemRealloc(pUserPtr, 4096); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRealloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ CamOsMemRelease(pUserPtr); ++ pUserPtr = NULL; ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRelease free buffer\n", __LINE__); ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsMem test end!!!\n", __LINE__); ++} ++ ++static void _TestCamOsPhyMapVirt(void) ++{ ++ void *pVirtPtr; ++ #define TEST_PHY_MEM_ADDR 0X20200000 ++ #define TEST_PHY_MEM_SIZE 0x100000 ++ CamOsPrintf("Test cache mapping:\n"); ++ pVirtPtr = CamOsPhyMemMap((void *)TEST_PHY_MEM_ADDR, TEST_PHY_MEM_SIZE, 1); ++ CamOsPrintf(" PhysAddr: 0x%08X\n", TEST_PHY_MEM_ADDR); ++ CamOsPrintf(" VirtAddr: 0x%08X\n", (u32)pVirtPtr); ++ CamOsPhyMemUnMap(pVirtPtr, TEST_PHY_MEM_SIZE); ++} ++ ++static void _TestCamOsTimer(void) ++{ ++ s32 nCnt = 0; ++ CamOsTimespec_t tTvStart = {0}, tTvEnd = {0}; ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTvStart); ++ CamOsMsSleep(1000); ++ CamOsGetMonotonicTime(&tTvEnd); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMsSleep(1000) Now: %d.%09d Diff: %dms\n", __LINE__, tTvEnd.nSec, tTvEnd.nNanoSec, ++ (s32)CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_MS)); ++ } ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTvStart); ++ CamOsMsSleep(1); ++ CamOsGetMonotonicTime(&tTvEnd); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMsSleep(1) Now: %d.%09d Diff: %dms\n", __LINE__, tTvEnd.nSec, tTvEnd.nNanoSec, ++ (s32)CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_MS)); ++ } ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTvStart); ++ CamOsUsSleep(100); ++ CamOsGetMonotonicTime(&tTvEnd); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsUsSleep(100) Now: %d.%09d Diff: %dus\n", __LINE__, tTvEnd.nSec, tTvEnd.nNanoSec, ++ (s32)CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTvStart); ++ CamOsUsSleep(1); ++ CamOsGetMonotonicTime(&tTvEnd); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsUsSleep(1) Now: %d.%09d Diff: %dus\n", __LINE__, tTvEnd.nSec, tTvEnd.nNanoSec, ++ (s32)CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTvStart); ++ CamOsMsDelay(1); ++ CamOsGetMonotonicTime(&tTvEnd); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsMsDelay(1) Now: %d.%09d Diff: %dus\n", __LINE__, tTvEnd.nSec, tTvEnd.nNanoSec, ++ (s32)CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_US)); ++ } ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTvStart); ++ CamOsUsDelay(1); ++ CamOsGetMonotonicTime(&tTvEnd); ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] CamOsUsDelay(1) Now: %d.%09d Diff: %dns\n", __LINE__, tTvEnd.nSec, tTvEnd.nNanoSec, ++ (s32)CamOsTimeDiff(&tTvStart, &tTvEnd, CAM_OS_TIME_DIFF_NS)); ++ } ++} ++ ++static s32 _CamOsTsemTestEntry0(void *pUserData) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(1000); ++ ++ _gTestCnt++;//1 ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(10); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(300); ++ ++ _gTestCnt++;//3 ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ _gTestCnt++;//4 ++ ++ CamOsMsSleep(5000); ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(10); ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (_gTestCnt != 5) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ _gTestCnt++;//6 ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(10); ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 5000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (eRet != CAM_OS_OK) ++ { ++ CamOsPrintf("%s: step 3 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsTsemTestEntry1(void *pUserData) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ _gTestCnt++;//2 ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsPrintf("%s CamOsTsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsPrintf("%s CamOsTsemDown end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 4) ++ { ++ CamOsPrintf("%s: step 3 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ _gTestCnt++;//5 ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (_gTestCnt != 6) ++ { ++ CamOsPrintf("%s: step 4 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsPrintf("%s CamOsTsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ if (eRet != CAM_OS_TIMEOUT) ++ { ++ CamOsPrintf("%s: step 5 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsRwsemTestEntry0(void *pUserData) ++{ ++ CamOsRwsem_t *tpRwsem = (CamOsRwsem_t *)pUserData; ++ ++ CamOsPrintf("%s CamOsRwsemDownRead start\n", __FUNCTION__); ++ CamOsRwsemDownRead(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownRead end\n", __FUNCTION__); ++ ++ CamOsMsSleep(2000); ++ ++ if (_gTestCnt != 0) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemUpRead\n", __FUNCTION__); ++ CamOsRwsemUpRead(tpRwsem); ++ ++ CamOsMsSleep(50); ++ ++ if (_gTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemDownWrite start\n", __FUNCTION__); ++ CamOsRwsemDownWrite(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownWrite end\n", __FUNCTION__); ++ ++ CamOsMsSleep(1500); ++ ++ _gTestCnt++; ++ ++ CamOsPrintf("%s CamOsRwsemUpWrite\n", __FUNCTION__); ++ CamOsRwsemUpWrite(tpRwsem); ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsRwsemTestEntry1(void *pUserData) ++{ ++ CamOsRwsem_t *tpRwsem = (CamOsRwsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(20); ++ CamOsPrintf("%s CamOsRwsemTryDownRead start\n", __FUNCTION__); ++ if (CAM_OS_OK != (eRet = CamOsRwsemTryDownRead(tpRwsem))) ++ { ++ CamOsPrintf("%s: step 1 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsRwsemTryDownRead end\n", __FUNCTION__); ++ ++ CamOsMsSleep(2000); ++ ++ if (_gTestCnt != 0) ++ { ++ CamOsPrintf("%s: step 2 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemUpRead\n", __FUNCTION__); ++ CamOsRwsemUpRead(tpRwsem); ++ ++ CamOsMsSleep(50); ++ ++ if (_gTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 3 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ CamOsMsSleep(1000); ++ ++ CamOsPrintf("%s CamOsRwsemDownWrite start\n", __FUNCTION__); ++ CamOsRwsemDownWrite(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownWrite end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 4 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ _gTestCnt++; ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsRwsemUpWrite\n", __FUNCTION__); ++ CamOsRwsemUpWrite(tpRwsem); ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsRwsemTestEntry2(void *pUserData) ++{ ++ CamOsRwsem_t *tpRwsem = (CamOsRwsem_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(50); ++ ++ CamOsPrintf("%s CamOsRwsemTryDownWrite start\n", __FUNCTION__); ++ if (CAM_OS_RESOURCE_BUSY != (eRet = CamOsRwsemTryDownWrite(tpRwsem))) ++ { ++ CamOsPrintf("%s: step 1 fail!(eRet=%d)\n", __FUNCTION__, eRet); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsRwsemTryDownWrite end\n", __FUNCTION__); ++ ++ CamOsPrintf("%s CamOsRwsemDownWrite start\n", __FUNCTION__); ++ CamOsRwsemDownWrite(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownWrite end\n", __FUNCTION__); ++ ++ _gTestCnt++; ++ ++ CamOsPrintf("%s CamOsRwsemUpWrite\n", __FUNCTION__); ++ CamOsRwsemUpWrite(tpRwsem); ++ ++ CamOsMsSleep(200); ++ ++ CamOsPrintf("%s CamOsRwsemDownRead start\n", __FUNCTION__); ++ CamOsRwsemDownRead(tpRwsem); ++ CamOsPrintf("%s CamOsRwsemDownRead end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 2 && _gTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsRwsemUpRead\n", __FUNCTION__); ++ CamOsRwsemUpRead(tpRwsem); ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static void _TestCamOsTsem(void) ++{ ++ static CamOsThread TaskHandle0, TaskHandle1; ++ CamOsTsem_t tSem; ++ ++ _gTestCnt = 0; ++ ++ CamOsTsemInit(&tSem, 0); ++ CamOsThreadCreate(&TaskHandle0, NULL, (void *)_CamOsTsemTestEntry0, &tSem); ++ CamOsThreadCreate(&TaskHandle1, NULL, (void *)_CamOsTsemTestEntry1, &tSem); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ ++ CamOsTsemDeinit(&tSem); ++} ++ ++static void _TestCamOsRwsem(void) ++{ ++ static CamOsThread TaskHandle0, TaskHandle1, TaskHandle2; ++ CamOsRwsem_t tRwsem; ++ ++ _gTestCnt = 0; ++ ++ CamOsRwsemInit(&tRwsem); ++ CamOsThreadCreate(&TaskHandle0, NULL, (void *)_CamOsRwsemTestEntry0, &tRwsem); ++ CamOsThreadCreate(&TaskHandle1, NULL, (void *)_CamOsRwsemTestEntry1, &tRwsem); ++ CamOsThreadCreate(&TaskHandle2, NULL, (void *)_CamOsRwsemTestEntry2, &tRwsem); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ CamOsThreadJoin(TaskHandle2); ++ ++ CamOsRwsemDeinit(&tRwsem); ++} ++ ++static void _TestCamOsDiv64(void) ++{ ++ u64 nDividendU64 = 0, nDivisorU64 = 0, nResultU64 = 0, nRemainderU64 = 0; ++ s64 nDividendS64 = 0, nDivisorS64 = 0, nResultS64 = 0, nRemainderS64 = 0; ++ ++ CamOsPrintf("Unsigned 64 bit dividend:"); ++ CamOsScanf("%llu", &nDividendU64); ++ CamOsPrintf("Unsigned 64 bit divisor:"); ++ CamOsScanf("%llu", &nDivisorU64); ++ ++ CamOsPrintf("Directly: %llu / %llu = %llu remaind %llu\n", nDividendU64, nDivisorU64, nDividendU64 / nDivisorU64, nDividendU64 % nDivisorU64); ++ nResultU64 = CamOsMathDivU64(nDividendU64, nDivisorU64, &nRemainderU64); ++ CamOsPrintf("By Div64: %llu / %llu = %llu remaind %llu\n", nDividendU64, nDivisorU64, nResultU64, nRemainderU64); ++ ++ ++ CamOsPrintf("Signed 64 bit dividend:"); ++ CamOsScanf("%lld", &nDividendS64); ++ CamOsPrintf("Signed 64 bit divisor:"); ++ CamOsScanf("%lld", &nDivisorS64); ++ ++ CamOsPrintf("Directly: %lld / %lld = %lld remaind %lld\n", nDividendS64, nDivisorS64, nDividendS64 / nDivisorS64, nDividendS64 % nDivisorS64); ++ nResultS64 = CamOsMathDivS64(nDividendS64, nDivisorS64, &nRemainderS64); ++ CamOsPrintf("By Div64: %lld / %lld = %lld remaind %lld\n", nDividendS64, nDivisorS64, nResultS64, nRemainderS64); ++} ++ ++static void _TestCamOsSystemTime(void) ++{ ++ s32 nCnt = 0; ++ CamOsTimespec_t tTs; ++ struct tm * tTm; ++ time_t nRawTime; ++ ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ nRawTime = (time_t)tTs.nSec; ++ tTm = localtime (&nRawTime); ++ CamOsPrintf("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm->tm_year+1900, ++ tTm->tm_mon+1, ++ tTm->tm_mday, ++ tTm->tm_wday, ++ tTm->tm_hour, ++ tTm->tm_min, ++ tTm->tm_sec); ++ ++ tTs.nSec += 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++ ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ nRawTime = (time_t)tTs.nSec; ++ tTm = localtime (&nRawTime); ++ CamOsPrintf("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm->tm_year+1900, ++ tTm->tm_mon+1, ++ tTm->tm_mday, ++ tTm->tm_wday, ++ tTm->tm_hour, ++ tTm->tm_min, ++ tTm->tm_sec); ++ ++ tTs.nSec -= 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++} ++ ++static void _TestCamOsPhysMemSize(void) ++{ ++ CamOsMemSize_e eMemSize; ++ eMemSize = CamOsPhysMemSize(); ++ CamOsPrintf("System has %dMB physical memory\n", 1<<(u32)eMemSize); ++} ++ ++static void _TestCamOsChipId(void) ++{ ++ CamOsDramInfo_t Info = {0}; ++ CamOsDramInfo(&Info); ++ CamOsPrintf("DRAM Info: Size %d Type %d Bus %d\n", Info.nBytes, Info.nType, Info.nBusWidth); ++ CamOsPrintf("Chip ID: 0x%X Revision: 0x%X\n", CamOsChipId(), CamOsChipRevision()); ++} ++ ++static s32 _CamOsTcondTestEntry0(void *pUserData) ++{ ++ CamOsTcond_t *pCond = (CamOsTcond_t *)pUserData; ++ ++ CamOsMsSleep(300); ++ ++ _gTestCnt++;//1 ++ ++ CamOsPrintf("%s CamOsTcondSignal\n", __FUNCTION__); ++ CamOsTcondSignal(pCond); ++ ++ CamOsMsSleep(100); ++ ++ CamOsPrintf("%s CamOsTcondSignal\n", __FUNCTION__); ++ CamOsTcondSignal(pCond); ++ ++ CamOsMsSleep(100); ++ ++ _gTestCnt++;//3 ++ ++ CamOsPrintf("%s CamOsTcondSignalAll\n", __FUNCTION__); ++ CamOsTcondSignalAll(pCond); ++ ++ CamOsPrintf("%s CamOsTcondTimedWait start\n", __FUNCTION__); ++ if (CamOsTcondTimedWait(pCond, 500) != CAM_OS_TIMEOUT) ++ { ++ CamOsPrintf("%s: step 1 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsTcondTimedWait end(timeout)\n", __FUNCTION__); ++ ++ CamOsMsSleep(2000); ++ ++ _gTestCnt++; ++ ++ CamOsPrintf("%s CamOsTcondSignal\n", __FUNCTION__); ++ CamOsTcondSignal(pCond); ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsTcondTestEntry1(void *pUserData) ++{ ++ CamOsTcond_t *pCond = (CamOsTcond_t *)pUserData; ++ CamOsRet_e eRet; ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 1) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ _gTestCnt++;//2 ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 2 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTcondTimedWait start\n", __FUNCTION__); ++ eRet = CamOsTcondTimedWait(pCond, 1000); ++ if (eRet != CAM_OS_TIMEOUT || _gTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 3 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsTcondTimedWait end(timeout)\n", __FUNCTION__); ++ ++ _gTestCnt++; ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsTcondTestEntry2(void *pUserData) ++{ ++ CamOsRet_e eRet; ++ ++ CamOsTcond_t *pCond = (CamOsTcond_t *)pUserData; ++ ++ CamOsMsSleep(10); ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 2) ++ { ++ CamOsPrintf("%s: step 1 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTcondWait start\n", __FUNCTION__); ++ CamOsTcondWait(pCond); ++ CamOsPrintf("%s CamOsTcondWait end\n", __FUNCTION__); ++ ++ if (_gTestCnt != 3) ++ { ++ CamOsPrintf("%s: step 2 fail!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ CamOsPrintf("%s CamOsTcondTimedWait start\n", __FUNCTION__); ++ eRet = CamOsTcondTimedWait(pCond, 5000); ++ if (eRet != CAM_OS_OK || _gTestCnt != 5) ++ { ++ CamOsPrintf("%s: step 3 fail!(_gTestCnt=%d)\n", __FUNCTION__, _gTestCnt); ++ return -1; ++ } ++ CamOsPrintf("%s CamOsTcondTimedWait end(wakend)\n", __FUNCTION__); ++ ++ CamOsPrintf("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static void _TestCamOsTcond(void) ++{ ++ static CamOsThread TaskHandle0, TaskHandle1, TaskHandle2; ++ CamOsTcond_t tCond; ++ ++ _gTestCnt = 0; ++ CamOsTcondInit(&tCond); ++ ++ CamOsThreadCreate(&TaskHandle0, NULL, (void *)_CamOsTcondTestEntry0, &tCond); ++ CamOsThreadCreate(&TaskHandle1, NULL, (void *)_CamOsTcondTestEntry1, &tCond); ++ CamOsThreadCreate(&TaskHandle2, NULL, (void *)_CamOsTcondTestEntry2, &tCond); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ CamOsThreadJoin(TaskHandle2); ++ ++ CamOsTcondDeinit(&tCond); ++} ++ ++static void _TestCamOsBitmap(void) ++{ ++ #define BITMAP_BITS 128 ++ CAM_OS_DECLARE_BITMAP(aBitmap, BITMAP_BITS); ++ ++ CAM_OS_BITMAP_CLEAR(aBitmap); ++ CamOsPrintf("Set bit 0, 1, 2, 37, 98\n"); ++ CAM_OS_SET_BIT(0, aBitmap); ++ CAM_OS_SET_BIT(1, aBitmap); ++ CAM_OS_SET_BIT(2, aBitmap); ++ CAM_OS_SET_BIT(37, aBitmap); ++ CAM_OS_SET_BIT(98, aBitmap); ++ CamOsPrintf("\ttest bit 0: %d\n", CAM_OS_TEST_BIT(0, aBitmap)); ++ CamOsPrintf("\ttest bit 1: %d\n", CAM_OS_TEST_BIT(1, aBitmap)); ++ CamOsPrintf("\ttest bit 2: %d\n", CAM_OS_TEST_BIT(2, aBitmap)); ++ CamOsPrintf("\ttest bit 3: %d\n", CAM_OS_TEST_BIT(3, aBitmap)); ++ CamOsPrintf("\ttest bit 30: %d\n", CAM_OS_TEST_BIT(30, aBitmap)); ++ CamOsPrintf("\ttest bit 37: %d\n", CAM_OS_TEST_BIT(37, aBitmap)); ++ CamOsPrintf("\ttest bit 80: %d\n", CAM_OS_TEST_BIT(80, aBitmap)); ++ CamOsPrintf("\ttest bit 98: %d\n", CAM_OS_TEST_BIT(98, aBitmap)); ++ CamOsPrintf("\ttest bit 127: %d\n", CAM_OS_TEST_BIT(127, aBitmap)); ++ ++ CamOsPrintf("\tfirst zero bit: %u\n", CAM_OS_FIND_FIRST_ZERO_BIT(aBitmap, BITMAP_BITS)); ++ CamOsPrintf("Clear bit 2, 98\n"); ++ CAM_OS_CLEAR_BIT(2, aBitmap); ++ CAM_OS_CLEAR_BIT(98, aBitmap); ++ CamOsPrintf("\ttest bit 2: %d\n", CAM_OS_TEST_BIT(2, aBitmap)); ++ CamOsPrintf("\ttest bit 98: %d\n", CAM_OS_TEST_BIT(98, aBitmap)); ++ CamOsPrintf("\tfirst zero bit: %u\n", CAM_OS_FIND_FIRST_ZERO_BIT(aBitmap, BITMAP_BITS)); ++} ++ ++struct HashTableElement_t ++{ ++ struct CamOsHListNode_t tHentry; ++ u32 nKey; ++ u32 nData; ++}; ++ ++static void _TestCamOsHash(void) ++{ ++ u32 nItemNum; ++ CAM_OS_DEFINE_HASHTABLE(aHashTable, 8); ++ struct HashTableElement_t tHListNode0, tHListNode1, tHListNode2, tHListNode3, tHListNode4, *ptHListNode; ++ ++ tHListNode0.nKey = 102; ++ tHListNode0.nData = 1021; ++ tHListNode1.nKey = 1872; ++ tHListNode1.nData = 18721; ++ tHListNode2.nKey = 102; ++ tHListNode2.nData = 1022; ++ tHListNode3.nKey = 1872; ++ tHListNode3.nData = 18722; ++ tHListNode4.nKey = 102; ++ tHListNode4.nData = 1023; ++ CamOsPrintf("Add 3 items with key 102 and 2 items with key 1872\r\n"); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode0.tHentry, tHListNode0.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode1.tHentry, tHListNode1.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode2.tHentry, tHListNode2.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode3.tHentry, tHListNode3.nKey); ++ CAM_OS_HASH_ADD(aHashTable, &tHListNode4.tHentry, tHListNode4.nKey); ++ CamOsPrintf("Get items with key 102: \r\n"); ++ nItemNum = 0; ++ CAM_OS_HASH_FOR_EACH_POSSIBLE(aHashTable, ptHListNode, tHentry, 102) ++ { ++ CamOsPrintf("\titem %u: data=%u\r\n", nItemNum, ptHListNode->nData); ++ nItemNum++; ++ } ++ ++ CamOsPrintf("Get items with key 1872: \r\n"); ++ nItemNum = 0; ++ CAM_OS_HASH_FOR_EACH_POSSIBLE(aHashTable, ptHListNode, tHentry, 1872) ++ { ++ CamOsPrintf("\titem %u: data=%u\r\n", nItemNum, ptHListNode->nData); ++ nItemNum++; ++ } ++ ++ CamOsPrintf("Delete one items with key 1872.\r\n"); ++ CAM_OS_HASH_DEL(&tHListNode3.tHentry); ++ CamOsPrintf("Get items with key 1872: \r\n"); ++ nItemNum = 0; ++ CAM_OS_HASH_FOR_EACH_POSSIBLE(aHashTable, ptHListNode, tHentry, 1872) ++ { ++ CamOsPrintf("\titem %u: data=%u\n", nItemNum, ptHListNode->nData); ++ nItemNum++; ++ } ++} ++ ++static void _TestCamOsIdr(void) ++{ ++ CamOsIdr_t tIdr; ++ u32 nIdrData1=11111, nIdrData2=22222, nIdrData3=33333, *pnIdrDataPtr; ++ s32 nIdrId1, nIdrId2, nIdrId3; ++ ++ if (CAM_OS_OK == CamOsIdrInit(&tIdr)) ++ { ++ CamOsPrintf("Alloc data1(=%u) in 100~200\r\n", nIdrData1); ++ nIdrId1 = CamOsIdrAlloc(&tIdr, (void *)&nIdrData1, 100, 200); ++ CamOsPrintf("Alloc data2(=%u) in 100~200\r\n", nIdrData2); ++ nIdrId2 = CamOsIdrAlloc(&tIdr, (void *)&nIdrData2, 100, 200); ++ CamOsPrintf("Alloc data3(=%u) in 500~\r\n", nIdrData3); ++ nIdrId3 = CamOsIdrAlloc(&tIdr, (void *)&nIdrData3, 500, 0); ++ pnIdrDataPtr = (u32*)CamOsIdrFind(&tIdr, nIdrId1); ++ CamOsPrintf("ID1 = %d, find data = %u\r\n", nIdrId1, *pnIdrDataPtr); ++ pnIdrDataPtr = (u32*)CamOsIdrFind(&tIdr, nIdrId2); ++ CamOsPrintf("ID2 = %d, find data = %u\r\n", nIdrId2, *pnIdrDataPtr); ++ pnIdrDataPtr = (u32*)CamOsIdrFind(&tIdr, nIdrId3); ++ CamOsPrintf("ID3 = %d, find data = %u\r\n", nIdrId3, *pnIdrDataPtr); ++ ++ CamOsPrintf("Remove ID3(=%d) ... ", nIdrId3); ++ CamOsIdrRemove(&tIdr, nIdrId3); ++ if (NULL == CamOsIdrFind(&tIdr, nIdrId3)) ++ CamOsPrintf("success!\n"); ++ else ++ CamOsPrintf("fail!\n"); ++ ++ CamOsIdrDestroy(&tIdr); ++ } ++ else ++ CamOsPrintf("CamOsIdrInit fail!\n"); ++} ++ ++#ifdef CAM_OS_RTK ++static void _TimerCallback(unsigned long nDataAddr) ++{ ++ unsigned long *pnTimerMs = (unsigned long *)nDataAddr; ++ ++ CamOsPrintf("%s: timer ms=%lu\n", __FUNCTION__, *pnTimerMs); ++} ++ ++static void _TestCamOsTimerCallback(void) ++{ ++ CamOsTimer_t tTimer; ++ unsigned long nTimerMs; ++ ++ CamOsPrintf("[Step 1] add timer to 2000ms, then sleep 2100ms ... \n"); ++ CamOsTimerInit(&tTimer); ++ nTimerMs = 2000; ++ CamOsTimerAdd(&tTimer, nTimerMs, (void*)&nTimerMs, _TimerCallback); ++ CamOsMsSleep(2100); ++ if (CamOsTimerDelete(&tTimer)) ++ CamOsPrintf("fail!\n\n"); ++ else ++ CamOsPrintf("success!\n\n"); ++ ++ CamOsPrintf("[Step 2] add timer to 1000ms, modify to 1500ms in 300ms, then sleep 1600ms ... \n"); ++ CamOsTimerInit(&tTimer); ++ nTimerMs = 1000; ++ CamOsTimerAdd(&tTimer, nTimerMs, (void*)&nTimerMs, _TimerCallback); ++ CamOsMsSleep(300); ++ nTimerMs = 1500; ++ CamOsTimerModify(&tTimer, nTimerMs); ++ CamOsMsSleep(1600); ++ if (CamOsTimerDelete(&tTimer)) ++ CamOsPrintf("fail!\n\n"); ++ else ++ CamOsPrintf("success!\n\n"); ++ ++ CamOsPrintf("[Step 3] add timer to 3000ms, sleep 1000ms, then delete timer ... \n"); ++ CamOsTimerInit(&tTimer); ++ nTimerMs = 3000; ++ CamOsTimerAdd(&tTimer, nTimerMs, (void*)&nTimerMs, _TimerCallback); ++ CamOsMsSleep(1000); ++ if (!CamOsTimerDelete(&tTimer)) ++ CamOsPrintf("fail!\n\n"); ++ else ++ CamOsPrintf("success!\n\n"); ++} ++ ++#define MEMORY_CACHE_OBJECT_SIZE 0x50 ++static void _TestCamOsCacheAlloc(void) ++{ ++ CamOsMemCache_t tMemCache; ++ void *pMemCacheObj1, *pMemCacheObj2, *pMemCacheObj3; ++ ++ CamOsPrintf("Test non-HW cache alignment mapping:\n"); ++ if (CAM_OS_OK == CamOsMemCacheCreate(&tMemCache, "MemCacheTest", MEMORY_CACHE_OBJECT_SIZE, 0)) ++ { ++ pMemCacheObj1 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object1 address: 0x%08X\n", pMemCacheObj1); ++ pMemCacheObj2 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object2 address: 0x%08X\n", pMemCacheObj2); ++ pMemCacheObj3 = CamOsMemCacheAlloc(&tMemCache); ++ CamOsPrintf("Object3 address: 0x%08X\n", pMemCacheObj3); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj1); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj2); ++ CamOsMemCacheFree(&tMemCache, pMemCacheObj3); ++ CamOsMemCacheDestroy(&tMemCache); ++ } ++ else ++ CamOsPrintf("CamOsMemCacheCreate fail!\n"); ++} ++#endif ++ ++static void _TestCamOsPanic(void) ++{ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] Test CamOsPanic\n", __LINE__); ++ CamOsPanic("Test OS Panic..."); ++} ++ ++static void _CamOsThreadTestSpinlock0(void *pUserdata) ++{ ++ s32 i = 0; ++ ++ for (i=0; i<500; i++) ++ { ++ CamOsPrintf("Thread0 (%d)\n", i); ++ } ++} ++ ++static void _CamOsThreadTestSpinlock1(void *pUserdata) ++{ ++ s32 i = 0; ++ u32 *SpinlockTestMode = (u32 *)pUserdata; ++#ifdef CAM_OS_RTK ++ MsIntMask_e mask = 0; ++#endif ++ CamOsSpinlock_t stSpinlock; ++ ++ for (i=0; i<100; i++) ++ { ++ CamOsPrintf("Thread1 (%d)\n", i); ++ } ++ ++ CamOsSpinInit(&stSpinlock); ++ switch (*SpinlockTestMode) ++ { ++ case 0: ++ CamOsSpinLock(&stSpinlock); ++ break; ++ case 1: ++ CamOsSpinLockIrqSave(&stSpinlock); ++ break; ++ case 2: ++#ifdef CAM_OS_RTK ++ mask = MsDisableInterrupt(); ++#endif ++ CamOsSpinLockIrqSave(&stSpinlock); ++ break; ++ default: ++ break; ++ } ++ ++ for (i=100; i<200; i++) ++ { ++ CamOsPrintf("\033[1;34mThread1 in Spinlock (%d)\033[m\n", i); ++ } ++ ++ switch (*SpinlockTestMode) ++ { ++ case 0: ++ CamOsSpinUnlock(&stSpinlock); ++ break; ++ case 1: ++ case 2: ++ CamOsSpinUnlockIrqRestore(&stSpinlock); ++ break; ++ default: ++ break; ++ } ++ ++ for (i=200; i<500; i++) ++ { ++ CamOsPrintf("Thread1 (%d)\n", i); ++ } ++ ++#ifdef CAM_OS_RTK ++ if (*SpinlockTestMode == 2) ++ MsEnableInterrupt(mask); ++#endif ++} ++ ++static void _TestCamOsSpinlock(void) ++{ ++ CamOsThread TaskHandle0, TaskHandle1; ++ CamOsThreadAttrb_t tAttr = {0}; ++ u32 SpinlockTestMode = 2; // 0: CamOsSpinLock. ++ // 1: CamOsSpinLockIrqSave. ++ // 2: CamOsSpinLockIrqSave after disable system interrupt. ++ ++ CamOsPrintf("[CAM_OS_WRAPPER_TEST:%d] Test CamOsSpinlock\n", __LINE__); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle0, &tAttr, (void *)_CamOsThreadTestSpinlock0, NULL); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle1, &tAttr, (void *)_CamOsThreadTestSpinlock1, (void *)&SpinlockTestMode); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++} +diff --git a/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_test.h b/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_test.h +new file mode 100755 +index 000000000000..2b3568e19d44 +--- /dev/null ++++ b/drivers/sstar/cam_os_wrapper/test/cam_os_wrapper_test.h +@@ -0,0 +1,35 @@ ++/* ++* cam_os_wrapper_test.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_WRAPPER_TEST_H__ ++#define __CAM_OS_WRAPPER_TEST_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#ifdef CAM_OS_RTK ++s32 CamOsWrapperTest(CLI_t *pCli, char *p); ++#endif ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_WRAPPER_TEST_H__ +diff --git a/drivers/sstar/cam_sysfs/Makefile b/drivers/sstar/cam_sysfs/Makefile +new file mode 100755 +index 000000000000..ae2d15bed412 +--- /dev/null ++++ b/drivers/sstar/cam_sysfs/Makefile +@@ -0,0 +1,3 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++obj-y += cam_sysfs.o +\ No newline at end of file +diff --git a/drivers/sstar/cam_sysfs/cam_sysfs.c b/drivers/sstar/cam_sysfs/cam_sysfs.c +new file mode 100755 +index 000000000000..a994f914d2d9 +--- /dev/null ++++ b/drivers/sstar/cam_sysfs/cam_sysfs.c +@@ -0,0 +1,245 @@ ++/* ++* cam_sysfs.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++/** ++ * of_address_to_resource - Translate device tree address and return as resource ++ * ++ * Note that if your address is a PIO address, the conversion will fail if ++ * the physical address can't be internally converted to an IO token with ++ * pci_address_to_pio(), that is because it's either called to early or it ++ * can't be matched to any host bridge IO space ++ */ ++int CamOfAddressToResource(struct device_node *dev, int index, ++ struct resource *r) ++{ ++ return of_address_to_resource(dev, index, r); ++} ++ ++int CamOfIrqToResource(struct device_node *dev, int index, ++ struct resource *r) ++{ ++ return of_irq_to_resource(dev, index, r); ++} ++ ++int CamOfPropertyReadU32Index(const struct device_node *np, ++ const char *propname, ++ u32 index, u32 *out_value) ++{ ++ return of_property_read_u32_index(np, propname, index, out_value); ++} ++ ++int CamOfPropertyReadVariableU32Array(const struct device_node *np, ++ const char *propname, u32 *out_values, ++ size_t sz_min, size_t sz_max) ++{ ++ return of_property_read_variable_u32_array(np, propname, out_values, sz_min, sz_max); ++} ++/** ++ * platform_get_resource - get a resource for a device ++ * @dev: platform device ++ * @type: resource type ++ * @num: resource index ++ */ ++struct resource *CamPlatformGetResource(struct platform_device *dev, ++ unsigned int type, unsigned int num) ++{ ++ return platform_get_resource(dev, type, num); ++} ++ ++int CamPlatformDriverRegister(struct platform_driver *drv) ++{ ++ return platform_driver_register(drv); ++} ++ ++/** ++ * platform_driver_unregister - unregister a driver for platform-level devices ++ * @drv: platform driver structure ++ */ ++void CamPlatformDriverUnregister(struct platform_driver *drv) ++{ ++ platform_driver_unregister(drv); ++} ++ ++/** ++ * platform_get_irq_byname - get an IRQ for a device by name ++ * @dev: platform device ++ * @name: IRQ name ++ */ ++int CamPlatformGetIrqByname(struct platform_device *dev, const char *name) ++{ ++ return platform_get_irq_byname(dev, name); ++} ++ ++int __must_check CamSysfsCreateFile(struct kobject *kobj, const struct attribute * attr) ++{ ++ return sysfs_create_file_ns(kobj, attr, NULL); ++} ++ ++int CamSysfsCreateFiles(struct kobject *kobj, const struct attribute **ptr) ++{ ++ return sysfs_create_files(kobj, ptr); ++} ++ ++int CamSysfsCreateLink(struct kobject *kobj, struct kobject *target, const char *name) ++{ ++ return sysfs_create_link(kobj, target, name); ++} ++ ++void CamSysfsRemoveFile(struct kobject *kobj, const struct attribute *attr, const void *ns) ++{ ++ sysfs_remove_file_ns(kobj, attr, NULL); ++} ++ ++void CamSysfsRemoveFiles(struct kobject *kobj, const struct attribute **attr) ++{ ++ sysfs_remove_files(kobj, attr); ++} ++ ++struct device *CamDeviceCreate(struct class *class, struct device *parent, ++ dev_t devt, void *drvdata, const char *fmt, ...) ++{ ++ va_list vargs; ++ struct device *dev; ++ ++ va_start(vargs, fmt); ++ dev = device_create_vargs(class, parent, devt, drvdata, fmt, vargs); ++ va_end(vargs); ++ return dev; ++} ++ ++int CamDeviceCreateFile(struct device *dev, ++ const struct device_attribute *attr) ++{ ++ return device_create_file(dev, attr); ++} ++ ++void CamDeviceDestroy(struct class *class, dev_t devt) ++{ ++ return device_destroy(class, devt); ++} ++ ++void CamDeviceRemoveFile(struct device *dev, ++ const struct device_attribute *attr) ++{ ++ return device_remove_file(dev, attr); ++} ++ ++void CamDeviceUnregister(struct device *dev) ++{ ++ return device_unregister(dev); ++} ++ ++struct kobject *CamKobjectCreateAndAdd(const char *name, struct kobject *parent) ++{ ++ return kobject_create_and_add(name, parent); ++} ++ ++struct class * __must_check CamClassCreate(struct module *owner, ++ const char *name) ++{ ++ return class_create(owner, name); ++} ++ ++void CamClassDestroy(struct class *cls) ++{ ++ class_destroy(cls); ++} ++ ++int CamIoremapPageRange(unsigned long addr, ++ unsigned long end, phys_addr_t phys_addr, pgprot_t prot) ++{ ++ return ioremap_page_range(addr, end, phys_addr, prot); ++} ++ ++void CamDevmKfree(struct device *dev, void *p) ++{ ++ devm_kfree(dev, p); ++} ++ ++void * CamDevmKmalloc(struct device *dev, size_t size, gfp_t gfp) ++{ ++ return devm_kmalloc(dev, size, gfp); ++} ++ ++int CamOfPropertyReadU32Array(const struct device_node *np, ++ const char *propname, u32 *out_values, ++ size_t sz) ++{ ++ return of_property_read_u32_array(np, propname, out_values, sz); ++} ++ ++int CamGpioRequest(unsigned gpio, const char *label) ++{ ++ return gpio_request(gpio, label); ++} ++ ++unsigned int CamIrqOfParseAndMap(struct device_node *dev, int index) ++{ ++ return irq_of_parse_and_map(dev, index); ++} ++ ++int CamofPropertyReadU32(const struct device_node *np, ++ const char *propname, ++ u32 *out_value) ++{ ++ return of_property_read_u32(np, propname, out_value); ++} ++ ++struct workqueue_struct* CamCreatesiglethreadWorkqueue(const char *fmt) ++{ ++ return create_singlethread_workqueue(fmt); ++} ++ ++ ++EXPORT_SYMBOL(CamCreatesiglethreadWorkqueue); ++EXPORT_SYMBOL(CamofPropertyReadU32); ++EXPORT_SYMBOL(CamIrqOfParseAndMap); ++EXPORT_SYMBOL(CamGpioRequest); ++EXPORT_SYMBOL(CamDevmKmalloc); ++EXPORT_SYMBOL(CamDevmKfree); ++EXPORT_SYMBOL(CamIoremapPageRange); ++EXPORT_SYMBOL(CamClassDestroy); ++EXPORT_SYMBOL(CamClassCreate); ++EXPORT_SYMBOL(CamKobjectCreateAndAdd); ++EXPORT_SYMBOL(CamDeviceUnregister); ++EXPORT_SYMBOL(CamDeviceRemoveFile); ++EXPORT_SYMBOL(CamDeviceDestroy); ++EXPORT_SYMBOL(CamDeviceCreateFile); ++EXPORT_SYMBOL(CamDeviceCreate); ++EXPORT_SYMBOL(CamSysfsRemoveFiles); ++EXPORT_SYMBOL(CamSysfsRemoveFile); ++EXPORT_SYMBOL(CamSysfsCreateLink); ++EXPORT_SYMBOL(CamSysfsCreateFiles); ++EXPORT_SYMBOL(CamSysfsCreateFile); ++EXPORT_SYMBOL(CamPlatformDriverRegister); ++EXPORT_SYMBOL(CamPlatformGetIrqByname); ++EXPORT_SYMBOL(CamPlatformDriverUnregister); ++EXPORT_SYMBOL(CamPlatformGetResource); ++EXPORT_SYMBOL(CamOfPropertyReadVariableU32Array); ++EXPORT_SYMBOL(CamOfPropertyReadU32Index); ++EXPORT_SYMBOL(CamOfIrqToResource); ++EXPORT_SYMBOL(CamOfAddressToResource); ++EXPORT_SYMBOL(CamOfPropertyReadU32Array); +diff --git a/drivers/sstar/cambricon/Kconfig b/drivers/sstar/cambricon/Kconfig +new file mode 100644 +index 000000000000..e69de29bb2d1 +diff --git a/drivers/sstar/cambricon/Makefile b/drivers/sstar/cambricon/Makefile +new file mode 100644 +index 000000000000..e69de29bb2d1 +diff --git a/drivers/sstar/camclk/Kconfig b/drivers/sstar/camclk/Kconfig +new file mode 100644 +index 000000000000..806c4aca5975 +--- /dev/null ++++ b/drivers/sstar/camclk/Kconfig +@@ -0,0 +1,17 @@ ++config CAM_CLK ++ boolean "CamClk driver driver" ++ default n ++ help ++ ++config CAM_CLK_SYSFS ++ boolean "CamClk support for sysfs" ++ depends on CAM_CLK ++ ++config CAMCLK_AUTOENABLE ++ boolean "CamClk support for auto enable all clk" ++ depends on CAM_CLK ++ ++config CAM_CLK_PROFILING ++ boolean "CamClk support for initial profiling" ++ depends on CAM_CLK ++ depends on SS_PROFILING_TIME +diff --git a/drivers/sstar/camclk/Makefile b/drivers/sstar/camclk/Makefile +new file mode 100644 +index 000000000000..ee85c4c0f181 +--- /dev/null ++++ b/drivers/sstar/camclk/Makefile +@@ -0,0 +1,31 @@ ++# ++# Makefile for Camdriver dip device drivers. ++MS_ARCH_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++#----------------------- drv ----------------------- ++EXTRA_CFLAGS += -Idrivers/sstar/camclk ++EXTRA_CFLAGS += -Idrivers/sstar/camclk/drv/inc ++EXTRA_CFLAGS += -Idrivers/sstar/camclk/drv/pub ++#----------------------- hal ----------------------- ++EXTRA_CFLAGS += -Idrivers/sstar/camclk/hal/common ++EXTRA_CFLAGS += -Idrivers/sstar/camclk/hal/$(MS_ARCH_NAME)/inc ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(MS_ARCH_NAME)/ ++# specific options ++EXTRA_CFLAGS += ++ ++ccflags-y += -Dcamclk_IO_OFFSET -DCONFIG_NOTTOGATED ++ifdef CONFIG_CAM_CLK_SYSFS ++ccflags-y += -DCAM_CLK_SYSFS ++endif ++#--------------------- sources --------------------- ++obj-$(CONFIG_CAM_CLK) += camclk.o ++camclk-y := \ ++ hal/$(MS_ARCH_NAME)/src/hal_camclk_complex.o \ ++ hal/$(MS_ARCH_NAME)/src/hal_camclk_tbl.o \ ++ drv/src/linux/drv_camclk_module.o\ ++ drv/src/linux/drv_camclk_sysfs.o\ ++ drv/src/linux/drv_camclk_os.o\ ++ drv/src/drv_camclk_impl.o\ ++ drv/src/drv_camclk.o\ ++ drv/src/drv_camclk_debug.o +diff --git a/drivers/sstar/camclk/drv/camclk.mak b/drivers/sstar/camclk/drv/camclk.mak +new file mode 100644 +index 000000000000..1a2916a2aabc +--- /dev/null ++++ b/drivers/sstar/camclk/drv/camclk.mak +@@ -0,0 +1,37 @@ ++#------------------------------------------------------------------------------ ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------ ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++#------------------------------------------------------------------------------ ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------ ++ ++PATH_C += \ ++ $(PATH_camclk)\ ++ $(PATH_camclk)/src\ ++ $(PATH_camclk)/src/rtk\ ++ $(PATH_camclk)/verify\ ++ ++PATH_H += $(PATH_camclk_hal)/common\ ++ $(PATH_camclk_hal)/inc\ ++ $(PATH_camclk)/inc\ ++ $(PATH_camclk)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_cam_os_wrapper)/inc\ ++ ++PP_OPT_COMMON += CONFIG_NOTTOGATED ++PP_OPT_COMMON += CONFIG_NOTTOAUTOENABLE ++ ++PP_OPT_COMMON += CAMCLK_RTK_UNITTEST ++PP_OPT_COMMON += CONFIG_CAM_CLK_SYSFS ++PP_OPT_COMMON += CONFIG_CAM_CLK_PROFILING ++ifneq (FALSE, $(strip $(DUALOS_SUPPORT))) ++PP_OPT_COMMON += CONFIG_SS_DUALOS ++endif ++SRC_C_LIST += drv_camclk.c\ ++ drv_camclk_debug.c \ ++ drv_camclk_impl.c \ ++ drv_camclk_module.c \ ++ clk_ut.c \ ++ drv_camclk_os.c +diff --git a/drivers/sstar/camclk/drv/inc/drv_camclk.h b/drivers/sstar/camclk/drv/inc/drv_camclk.h +new file mode 100755 +index 000000000000..e2e23d987919 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/inc/drv_camclk.h +@@ -0,0 +1,80 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __DRV_CAMCLK_H__ ++#define __DRV_CAMCLK_H__ ++#include "drv_camclk_DataType.h" ++#include "drv_camclk_st.h" ++#include "camclk_id.h" ++ ++extern CamOsTsem_t gstTsem; ++#define CAM_CLK_REF_CNT_SIZE (sizeof(HalCamClkTopClk_t)*HAL_CAMCLK_SRC_Id_MAX) ++#ifdef CONFIG_SS_DUALOS ++#define CAM_CLK_INVALIDATE(addr) (CamOsMemInvalidate((void*)addr,CAM_CLK_REF_CNT_SIZE)) ++#define CAM_CLK_FLUSH(addr) (CamOsMemFlush((void*)addr,CAM_CLK_REF_CNT_SIZE)) ++#else ++#define CAM_CLK_INVALIDATE(addr) ++#define CAM_CLK_FLUSH(addr) ++#endif ++#define CAM_CLK_LOCK_SEM() CamOsTsemDown(&gstTsem) ++#define CAM_CLK_UNLOCK_SEM() CamOsTsemUp(&gstTsem) ++#define CAM_CLK_INTEROS_PREFIX (0x434C4B00) //CLK ++#define CAM_CLK_INTEROS_SHAREMEM (CAM_CLK_INTEROS_PREFIX|0x1) ++ ++ ++#ifdef CONFIG_CAM_CLK_PROFILING ++extern void DrvCamClkOsProf(int mark, const char* name); ++#define CAM_CLK_RECORD(name) DrvCamClkOsProf(0,name) ++#else ++#define CAM_CLK_RECORD(name) ++#endif ++//------------------------------------------------------------------------------ ++/// @brief Init Clk Hardware ++/// @param[in] Void. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkInit(void); ++ ++//------------------------------------------------------------------------------ ++/// @brief deInit Clk Hardware ++/// @param[in] Void. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkDeinit(void); ++CAMCLK_RET_e DrvCamClkImplInit(void); ++CAMCLK_RET_e DrvCamClkImplDeinit(void); ++CAMCLK_RET_e DrvCamClkImplGetIdAllParent(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplGetClk(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplGetRate(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplGetRoundRateParent(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplSetOnOff(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplSetParent(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplGetOnOff(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplGetHwOnOff(HalCamClkSrcId_e u32Id, u8 *p8bEn); ++CAMCLK_RET_e DrvCamClkImplGetParent(void *pCfg); ++CAMCLK_RET_e DrvCamClkImplGetHwSelect(HalCamClkSrcId_e u32Id, u16 *p16Select); ++u32 DrvCamclkDebugHandlerShow(char *buf); ++u32 DrvCamclkDebugClkShow(char *buf); ++u32 DrvCamclkDebugDebugLvlShow(char *buf); ++void DrvCamclkDebugDebugLvlStore(const char *buf); ++void DrvCamClkDebugInit(void); ++void DrvCamClkSysfsInit(void *device); ++CAMCLK_RET_e DrvCamClkOsGetShareMemory(DrvCamClkShareMemoryType_e enType); ++void DrvCamClkOsPrepareShareMemory(DrvCamClkShareMemoryType_e enType); ++int DrvCamClkImplDisableUnuseClk(void); ++CAMCLK_RET_e DrvCamClkImplGetAdjustRoundRate(DrvCamClkGetRoundRateParent_t *pstCfg); ++CAMCLK_RET_e DrvCamClkImplSetAdjustRate(DrvCamClkSetAdjRoundRate_t *pstCfg); ++CAMCLK_RET_e DrvCamClkResume(void); ++CAMCLK_RET_e DrvCamClkImplRestoreClk(void); ++#endif +diff --git a/drivers/sstar/camclk/drv/inc/drv_camclk_st.h b/drivers/sstar/camclk/drv/inc/drv_camclk_st.h +new file mode 100644 +index 000000000000..a140aed0f7e2 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/inc/drv_camclk_st.h +@@ -0,0 +1,85 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __DRV_CAMCLK_ST_H__ ++#define __DRV_CAMCLK_ST_H__ ++#include "camclk_id.h" ++#include "hal_camclk_if_st.h" ++#include "drv_camclk_DataType.h" ++typedef enum ++{ ++ DRV_CAMCLK_SHOW_CLK_COM = 0, ++ DRV_CAMCLK_SHOW_CLK_ALL, ++ DRV_CAMCLK_SHOW_CLK_MAX, ++} DrvCamClkShowId_e; ++ ++typedef enum ++{ ++ DRV_CAMCLK_SHAREMEM_TOPCURRENT = 0, ++ DRV_CAMCLK_SHAREMEM_TYPE, ++} DrvCamClkShareMemoryType_e; ++ ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ u32 u32Freq; ++ u32 u32RetFreq; ++ HalCamClkSrcId_e u32ParentId; ++ CAMCLK_ROUNDRATE_TYPE_e enType; ++} DrvCamClkGetRoundRateParent_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ u32 u32Freq; ++ u32 u32ParentFreq; ++ HalCamClkSrcId_e u32ParentId; ++} DrvCamClkSetAdjRoundRate_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ HalCamClkSrcId_e u32ParentId; ++} DrvCamClkGetParent_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ HalCamClkSrcId_e u32ParentId[MAX_CLK_SRC_PARENT_NODE_CNT]; ++ u32 u32ParentCount; ++} DrvCamClkGetAllParent_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ HalCamClkSrcId_e u32ParentId; ++ u32 u32ParentFreq; ++} DrvCamClkSetParent_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ u32 u32Freq; ++} DrvCamClkGetRate_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ u8 *pbEn; ++} DrvCamClkGetOnOff_t; ++typedef struct ++{ ++ HalCamClkSrcId_e u32Id; ++ u8 bEn; ++} DrvCamClkSetOnOff_t; ++typedef struct ++{ ++ u8 bLess; ++ u32 u32diff; ++} DrvCamClkRateDiff_t; ++#endif +diff --git a/drivers/sstar/camclk/drv/pub/drv_camclk_Api.h b/drivers/sstar/camclk/drv/pub/drv_camclk_Api.h +new file mode 100644 +index 000000000000..1aae816202ea +--- /dev/null ++++ b/drivers/sstar/camclk/drv/pub/drv_camclk_Api.h +@@ -0,0 +1,82 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __DRV_CAMCLKAPI_H__ ++#define __DRV_CAMCLKAPI_H__ ++#include "drv_camclk_DataType.h" ++ ++ ++//------------------------------------------------------------------------------ ++/// @brief Clk Register. ++/// @param[in] pCfg: Clk handler register. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkRegister(u8 *pDevName,u32 u32ClkId,void **pvHandlerId); ++CAMCLK_RET_e CamClkUnregister(void *pvHandlerId); ++//------------------------------------------------------------------------------ ++/// @brief Get Clk Rate. ++/// @param[in] u32ClkId: composite clk id.(from DrvCamClkGetClk) ++/// @param[out] pCfg;: config of attribute. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkAttrGet(void *pvHandlerId, CAMCLK_Get_Attribute *pCfg); ++//------------------------------------------------------------------------------ ++/// @brief Get Clk OnOff. ++/// @param[in] u32ClkId: composite clk id.(from DrvCamClkGetClk) ++/// @param[out] pbEn: clk OnOff. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkGetOnOff(void *pvHandlerId, u8 *pbEn); ++//------------------------------------------------------------------------------ ++/// @brief Set Clk parent Attribute. ++/// @param[in] pCfg;: config of attribute. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkAttrSet(void *pvHandlerId,CAMCLK_Set_Attribute *pCfg); ++ ++//------------------------------------------------------------------------------ ++/// @brief Set Clk On/Off ++/// @param[in] u32ClkId: composite clk id.(from DrvCamClkGetClk) ++/// @param[in] bEn: On/Off. ++/// @return DRV_CAMCLK_RET_e ++//------------------------------------------------------------------------------ ++CAMCLK_RET_e CamClkSetOnOff(void *pvHandlerId, u8 bEn); ++u32 CamClkRateGet(u32 u32ClkId); ++#define CAMCLK_SETRATE_ROUNDUP(stCfg,freq) \ ++do{ \ ++ stCfg.eRoundType = CAMCLK_ROUNDRATE_UP; \ ++ stCfg.eSetType = CAMCLK_SET_ATTR_RATE; \ ++ stCfg.attribute.u32Rate = freq; \ ++} while (0) ++ ++#define CAMCLK_SETRATE_ROUNDDOWN(stCfg,freq) \ ++do{ \ ++ stCfg.eRoundType = CAMCLK_ROUNDRATE_DOWN; \ ++ stCfg.eSetType = CAMCLK_SET_ATTR_RATE; \ ++ stCfg.attribute.u32Rate = freq; \ ++} while (0) ++ ++#define CAMCLK_SETRATE_ROUND(stCfg,freq) \ ++do{ \ ++ stCfg.eRoundType = CAMCLK_ROUNDRATE_ROUND; \ ++ stCfg.eSetType = CAMCLK_SET_ATTR_RATE; \ ++ stCfg.attribute.u32Rate = freq; \ ++} while (0) ++ ++#define CAMCLK_SETPARENT(stCfg,parent) \ ++do{ \ ++ stCfg.eSetType = CAMCLK_SET_ATTR_PARENT; \ ++ stCfg.attribute.u32Parent = parent; \ ++} while (0) ++#endif +diff --git a/drivers/sstar/camclk/drv/pub/drv_camclk_DataType.h b/drivers/sstar/camclk/drv/pub/drv_camclk_DataType.h +new file mode 100644 +index 000000000000..aa3eb75647e0 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/pub/drv_camclk_DataType.h +@@ -0,0 +1,79 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __DRV_CAMCLKDATATYPE_H__ ++#define __DRV_CAMCLKDATATYPE_H__ ++#include "cam_os_wrapper.h" ++ ++typedef enum ++{ ++ CAMCLK_RET_OK = 0, ++ CAMCLK_RET_RATEERR, ++ CAMCLK_RET_NOTSUPPORT, ++ CAMCLK_RET_FAIL, ++} CAMCLK_RET_e; ++typedef enum ++{ ++ CAMCLK_DEV_Id_SCL = 0, ++ CAMCLK_DEV_Id_DIP, ++ CAMCLK_DEV_Id_GOP, ++ CAMCLK_DEV_Id_MAX ++} CAMCLK_DEV_Id_e; ++typedef enum ++{ ++ CAMCLK_SET_ATTR_PARENT = 0x1, ++ CAMCLK_SET_ATTR_RATE = 0x2, ++ CAMCLK_SET_ATTR_MAX ++} CAMCLK_Set_Attr_e; ++typedef enum ++{ ++ CAMCLK_ROUNDRATE_DOWN = 0, ++ CAMCLK_ROUNDRATE_UP, ++ CAMCLK_ROUNDRATE_ROUND, ++ CAMCLK_ROUNDRATE_TYPE, ++} CAMCLK_ROUNDRATE_TYPE_e; ++ ++typedef struct ++{ ++ CAMCLK_ROUNDRATE_TYPE_e eRoundType; ++ CAMCLK_Set_Attr_e eSetType; ++ union ++ { ++ u32 u32Rate; ++ u32 u32Parent; ++ } attribute; ++} CAMCLK_Set_Attribute; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32CurrentParent; ++ u32 u32Parent[16]; ++ u32 u32NodeCount; ++} CAMCLK_Get_Attribute; ++typedef struct ++{ ++ struct CamOsListHead_t stList; ++ u32 u32ClkId; ++ u8 pDevName[16]; ++ u8 bEnable; ++ u32 u32HandlerId; ++ u32 u32RoundRate; ++ u32 u32CurrentParent; ++ union ++ { ++ u32 u32Rate; ++ u32 u32Parent; ++ } attribute; ++} CAMCLK_Handler; ++#endif +diff --git a/drivers/sstar/camclk/drv/src/drv_camclk.c b/drivers/sstar/camclk/drv/src/drv_camclk.c +new file mode 100755 +index 000000000000..7d95b82e2b18 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/src/drv_camclk.c +@@ -0,0 +1,357 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define DRV_CAMCLK_C ++#include "cam_os_wrapper.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "drv_camclk_Api.h" ++#include "hal_camclk_if.h" ++#include "camclk_dbg.h" ++ ++#define CID_HANDLER_MUGIC 0x28520000 ++#define CAMCLK_HANDLER_ENTRY_SIZE (sizeof(CAMCLK_Handler)) ++u16 gu16HandlerCnt; ++CAM_OS_LIST_HEAD(gstClkListHead); ++CamOsMemCache_t gstPoolCfg = {{0,0}}; ++HalCamClkTopClk_t gstCamClkTopCurrent[HAL_CAMCLK_SRC_Id_MAX]; ++HalCamClkTopClk_t *gCamClkTopCurrent=gstCamClkTopCurrent; ++ ++void _DrvCamClkCheckUnregisterHandler(void) ++{ ++ struct CamOsListHead_t *pos; ++ CAMCLK_Handler *pCfg; ++ ++ CAM_OS_LIST_FOR_EACH(pos,&gstClkListHead) ++ { ++ pCfg = CAM_OS_LIST_ENTRY(pos,CAMCLK_Handler,stList); ++ CAMCLKERR("[%s @ %d] %s Clk_Id:%d bEn:%hhd\n", __FUNCTION__, __LINE__,pCfg->pDevName,pCfg->u32ClkId,pCfg->bEnable); ++ CamClkUnregister((void *)pCfg); ++ } ++ ++} ++ ++//================================================================================ ++CAMCLK_RET_e CamClkInit(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ ++ CAMCLKINFO("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ if(CamOsMemCacheCreate(&gstPoolCfg,"CAMCLK_POOL",CAMCLK_HANDLER_ENTRY_SIZE,0)) ++ { ++ CAMCLKERR("[%s @ %d] ALLOCATE Handler pool fail.\n", __FUNCTION__, __LINE__); ++ return CAMCLK_RET_FAIL; ++ } ++ DrvCamClkImplInit(); ++ gu16HandlerCnt = 0; ++ return enRet; ++} ++CAMCLK_RET_e CamClkDeinit(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ CAMCLKINFO("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ DrvCamClkImplDeinit(); ++ if(gstPoolCfg.nPriv[0] || gstPoolCfg.nPriv[1]) ++ { ++ if(gu16HandlerCnt!=0) ++ { ++ CAMCLKERR("[%s @ %d] There are ctx w/o Unregister!!. Maybe Memory leak.\n", __FUNCTION__, __LINE__); ++ _DrvCamClkCheckUnregisterHandler(); ++ } ++ CamOsMemCacheDestroy(&gstPoolCfg); ++ } ++ return enRet; ++} ++u32 CamClkParentGet(u32 u32ClkId) ++{ ++ DrvCamClkGetParent_t stParentCfg; ++ ++ stParentCfg.u32Id = u32ClkId; ++ DrvCamClkImplGetParent((void *)&stParentCfg); ++ return (u32)stParentCfg.u32ParentId; ++} ++CAMCLK_RET_e DrvCamClkResume(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ struct CamOsListHead_t *pos; ++ CAMCLK_Handler *pCfg; ++ DrvCamClkSetParent_t stCfg; ++ DrvCamClkSetAdjRoundRate_t stAdjCfg; ++ ++ CAM_OS_LIST_FOR_EACH(pos,&gstClkListHead) ++ { ++ pCfg = CAM_OS_LIST_ENTRY(pos,CAMCLK_Handler,stList); ++ if(gCamClkSrcNode[pCfg->u32ClkId].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ stAdjCfg.u32Id = pCfg->u32ClkId; ++ stAdjCfg.u32Freq = pCfg->u32RoundRate; ++ stAdjCfg.u32ParentId = pCfg->u32CurrentParent; ++ enRet = DrvCamClkImplSetAdjustRate(&stAdjCfg); ++ } ++ else if(gCamClkSrcNode[pCfg->u32ClkId].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ stCfg.u32Id = pCfg->u32ClkId; ++ stCfg.u32ParentId = pCfg->u32CurrentParent; ++ stCfg.u32ParentFreq = 0; ++ enRet = DrvCamClkImplSetParent(&stCfg); ++ } ++ } ++ DrvCamClkImplRestoreClk(); ++ return enRet; ++} ++CAMCLK_RET_e CamClkRegister(u8 *pDevName,u32 u32ClkId,void **pvHandlerId) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ static u8 u8RollNum = 0; ++ CAMCLK_Handler *pCfg; ++ ++ CAMCLKINFO("[%s @ %d] Dev:%s CID:%d\n", __FUNCTION__, __LINE__,pDevName,u32ClkId); ++ if(gCamClkTopCurrent) ++ { ++ pCfg = CamOsMemCacheAlloc(&gstPoolCfg); ++ if(pCfg) ++ { ++ gu16HandlerCnt++; ++ *pvHandlerId = (void *)pCfg; ++ pCfg->u32HandlerId = (CID_HANDLER_MUGIC |u8RollNum | (pCfg->u32ClkId<<8)) ; ++ u8RollNum++; ++ pCfg->u32ClkId = u32ClkId; ++ strcpy((char *)pCfg->pDevName,(char *)pDevName); ++ pCfg->bEnable = 0; ++ pCfg->u32RoundRate = CamClkRateGet(u32ClkId); ++ pCfg->u32CurrentParent = CamClkParentGet(u32ClkId); ++ pCfg->attribute.u32Parent = 0; ++ CAM_CLK_LOCK_SEM(); ++ CAM_OS_LIST_ADD_TAIL(&(pCfg->stList),&gstClkListHead); ++ CAM_CLK_UNLOCK_SEM(); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ *pvHandlerId = 0; ++ CAMCLKERR("[%s @ %d] ALLOCATE Handler pool fail.\n", __FUNCTION__, __LINE__); ++ } ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ *pvHandlerId = 0; ++ CAMCLKERR("[%s @ %d] W/O Init!!.\n", __FUNCTION__, __LINE__); ++ } ++ return enRet; ++} ++CAMCLK_RET_e CamClkUnregister(void *pvHandlerId) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ CAMCLK_Handler *pCtx = (CAMCLK_Handler *)pvHandlerId; ++ ++ if(pCtx &&((pCtx->u32HandlerId &CID_HANDLER_MUGIC) ==CID_HANDLER_MUGIC)) ++ { ++ pCtx->u32HandlerId = 0; ++ if(pCtx->bEnable) ++ { ++ CAMCLKWARN("[%s @ %d] W/O Disable Dev:%s CID:%d\n", __FUNCTION__, __LINE__,pCtx->pDevName,pCtx->u32ClkId); ++ } ++ else ++ { ++ CAMCLKINFO("[%s @ %d] Dev:%s CID:%d\n", __FUNCTION__, __LINE__,pCtx->pDevName,pCtx->u32ClkId); ++ } ++ CAM_CLK_LOCK_SEM(); ++ CAM_OS_LIST_DEL(&(pCtx->stList)); ++ CAM_CLK_UNLOCK_SEM(); ++ CamOsMemCacheFree(&gstPoolCfg,pCtx); ++ if(gu16HandlerCnt) ++ { ++ gu16HandlerCnt--; ++ } ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ CAMCLKERR("[%s @ %d] Handler Not exist.\n", __FUNCTION__, __LINE__); ++ } ++ return enRet; ++} ++ ++CAMCLK_RET_e CamClkAttrGet(void *pvHandlerId, CAMCLK_Get_Attribute *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkGetAllParent_t stParent; ++ CAMCLK_Handler *pCtx = (CAMCLK_Handler *)pvHandlerId; ++ ++ if(pCtx &&((pCtx->u32HandlerId &CID_HANDLER_MUGIC) ==CID_HANDLER_MUGIC)) ++ { ++ if(pCtx->attribute.u32Parent == 0) ++ { ++ pCfg->u32Rate = CamClkRateGet(pCtx->u32ClkId); ++ pCfg->u32CurrentParent = CamClkParentGet(pCtx->u32ClkId); ++ } ++ else ++ { ++ pCfg->u32Rate = pCtx->u32RoundRate; ++ pCfg->u32CurrentParent = pCtx->u32CurrentParent; ++ } ++ CAMCLKINFO("[%s @ %d] ClkId = %d Rate:%lu\n", __FUNCTION__, __LINE__,(u32)pvHandlerId,pCfg->u32Rate); ++ stParent.u32Id = pCtx->u32ClkId; ++ DrvCamClkImplGetIdAllParent(&stParent); ++ pCfg->u32NodeCount = stParent.u32ParentCount; ++ memcpy(pCfg->u32Parent,stParent.u32ParentId,pCfg->u32NodeCount*sizeof(HalCamClkSrcId_e)); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ CAMCLKERR("[%s @ %d] Handler Not exist.\n", __FUNCTION__, __LINE__); ++ } ++ return enRet; ++} ++CAMCLK_RET_e CamClkGetOnOff(void *pvHandlerId, u8 *pbEn) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ CAMCLK_Handler *pCtx = (CAMCLK_Handler *)pvHandlerId; ++ ++ if(pCtx &&((pCtx->u32HandlerId &CID_HANDLER_MUGIC) ==CID_HANDLER_MUGIC)) ++ { ++ *pbEn = pCtx->bEnable; ++ CAMCLKINFO("[%s @ %d] ClkId = %d OnOff:%hhu\n", __FUNCTION__, __LINE__,(u32)pvHandlerId,*pbEn); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ CAMCLKERR("[%s @ %d] Handler Not exist.\n", __FUNCTION__, __LINE__); ++ } ++ return enRet; ++} ++CAMCLK_RET_e CamClkAttrSet(void *pvHandlerId,CAMCLK_Set_Attribute *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkSetParent_t stCfg; ++ DrvCamClkGetRoundRateParent_t stRoundCfg; ++ DrvCamClkSetAdjRoundRate_t stAdjCfg; ++ CAMCLK_Handler *pCtx = (CAMCLK_Handler *)pvHandlerId; ++ if(pCtx &&((pCtx->u32HandlerId &CID_HANDLER_MUGIC) ==CID_HANDLER_MUGIC)) ++ { ++ CAM_CLK_LOCK_SEM(); ++ CAM_OS_LIST_DEL(&(pCtx->stList)); ++ CAM_OS_LIST_ADD_TAIL(&(pCtx->stList),&gstClkListHead); ++ CAM_CLK_UNLOCK_SEM(); ++ if(pCfg->eSetType == CAMCLK_SET_ATTR_RATE) ++ { ++ CAMCLKINFO("[%s @ %d] HandlerId = %p RoundType:%d Rate=%lu\n", __FUNCTION__, __LINE__, pvHandlerId, pCfg->eRoundType, pCfg->attribute.u32Rate); ++ stRoundCfg.u32Freq = pCfg->attribute.u32Rate; ++ stRoundCfg.u32Id = pCtx->u32ClkId; ++ stRoundCfg.enType = pCfg->eRoundType; ++ if(gCamClkSrcNode[pCtx->u32ClkId].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ DrvCamClkImplGetAdjustRoundRate(&stRoundCfg); ++ } ++ else ++ { ++ enRet = DrvCamClkImplGetRoundRateParent(&stRoundCfg); ++ } ++ ++ if(enRet) ++ { ++ CAMCLKERR("[%s @ %d] GetRoundRate FAIL.\n", __FUNCTION__, __LINE__); ++ goto ReturnBack; ++ } ++ } ++ stCfg.u32Id = pCtx->u32ClkId; ++ if(pCfg->eSetType == CAMCLK_SET_ATTR_RATE) ++ { ++ if(gCamClkSrcNode[pCtx->u32ClkId].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ stAdjCfg.u32Id = pCtx->u32ClkId; ++ pCtx->u32RoundRate = stAdjCfg.u32Freq = stRoundCfg.u32RetFreq; ++ pCtx->u32CurrentParent = stAdjCfg.u32ParentId = stRoundCfg.u32ParentId; ++ enRet = DrvCamClkImplSetAdjustRate(&stAdjCfg); ++ goto ReturnBack; ++ } ++ else ++ { ++ pCtx->u32CurrentParent = stCfg.u32ParentId = stRoundCfg.u32ParentId; ++ pCtx->attribute.u32Rate = pCfg->attribute.u32Rate; ++ pCtx->u32RoundRate = stCfg.u32ParentFreq = stRoundCfg.u32RetFreq; ++ CAMCLKINFO("[%s @ %d] ClkId = %d New Parent:%d\n", __FUNCTION__, __LINE__, pCtx->u32ClkId, stCfg.u32ParentId); ++ } ++ } ++ else ++ { ++ CAMCLKINFO("[%s @ %d] ClkId = %d Parent:%d\n", __FUNCTION__, __LINE__, pCtx->u32ClkId, pCfg->attribute.u32Parent); ++ pCtx->attribute.u32Parent = stCfg.u32ParentId = pCfg->attribute.u32Parent; ++ stCfg.u32ParentFreq = 0; ++ } ++ enRet = DrvCamClkImplSetParent(&stCfg); ++ if(enRet==CAMCLK_RET_OK && pCfg->eSetType == CAMCLK_SET_ATTR_PARENT) ++ { ++ pCtx->u32RoundRate = CamClkRateGet(pCtx->u32ClkId); ++ pCtx->u32CurrentParent = CamClkParentGet(pCtx->u32ClkId); ++ } ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ CAMCLKERR("[%s @ %d] Handler Not exist.\n", __FUNCTION__, __LINE__); ++ } ++ ReturnBack: ++ return enRet; ++} ++CAMCLK_RET_e CamClkSetOnOff(void *pvHandlerId, u8 bEn) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkSetOnOff_t stCfg; ++ CAMCLK_Handler *pCtx = (CAMCLK_Handler *)pvHandlerId; ++ ++ CAMCLKINFO("[%s @ %d] Handler = %p bEn = %hhd\n", __FUNCTION__, __LINE__, (u32)pvHandlerId, bEn); ++ if(pCtx &&((pCtx->u32HandlerId &CID_HANDLER_MUGIC) ==CID_HANDLER_MUGIC)) ++ { ++ if((bEn==0 && pCtx->bEnable == 0)||(bEn==1 && pCtx->bEnable == 1)) ++ { ++ enRet = CAMCLK_RET_FAIL; ++ if((bEn==0 && pCtx->bEnable == 0)) ++ { ++ CAMCLKERR("[%s @ %d] %s Handler not enable once.\n", __FUNCTION__, __LINE__,pCtx->pDevName); ++ } ++ else ++ { ++ CAMCLKERR("[%s @ %d] %s Handler already enable.\n", __FUNCTION__, __LINE__,pCtx->pDevName); ++ } ++ } ++ else ++ { ++ CAM_CLK_LOCK_SEM(); ++ CAM_OS_LIST_DEL(&(pCtx->stList)); ++ CAM_OS_LIST_ADD_TAIL(&(pCtx->stList),&gstClkListHead); ++ CAM_CLK_UNLOCK_SEM(); ++ pCtx->bEnable = stCfg.bEn = bEn; ++ stCfg.u32Id = pCtx->u32ClkId; ++ enRet = DrvCamClkImplSetOnOff(&stCfg); ++ } ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ CAMCLKERR("[%s @ %d] Handler Not exist.\n", __FUNCTION__, __LINE__); ++ } ++ return enRet; ++} ++u32 CamClkRateGet(u32 u32ClkId) ++{ ++ DrvCamClkGetRate_t stCfg; ++ ++ stCfg.u32Id = u32ClkId; ++ DrvCamClkImplGetRate(&stCfg); ++ CAMCLKINFO("[%s @ %d] ClkId = %d Rate:%lu\n", __FUNCTION__, __LINE__,u32ClkId,stCfg.u32Freq); ++ ++ return stCfg.u32Freq; ++} +diff --git a/drivers/sstar/camclk/drv/src/drv_camclk_debug.c b/drivers/sstar/camclk/drv/src/drv_camclk_debug.c +new file mode 100755 +index 000000000000..e2df9a5e7f77 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/src/drv_camclk_debug.c +@@ -0,0 +1,116 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define DRV_CAMCLK_DEBUG_C ++#include "cam_os_wrapper.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "drv_camclk_Api.h" ++#include "hal_camclk_if.h" ++#include "camclk_dbg.h" ++#ifndef PAGE_SIZE ++#define PAGE_SIZE 4096 ++#endif ++u32 gCAMCLKDbgLvl = 0x0; ++#ifdef CONFIG_CAM_CLK_SYSFS ++DrvCamClkShowId_e gCAMCLKDbgShowType = DRV_CAMCLK_SHOW_CLK_ALL; ++u32 u32gclkshowtempidx = 0; ++ ++void DrvCamClkDebugInit(void) ++{ ++ ++} ++u32 DrvCamclkDebugHandlerShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE*2; ++ struct CamOsListHead_t *pos; ++ CAMCLK_Handler *pCfg; ++ ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Debug Handler ========================\n"); ++ str += CamOsSnprintf(str, end - str, "Clk Handler Count: %hd\n",gu16HandlerCnt); ++ str += CamOsSnprintf(str, end - str, "Name Handler Num CID Enable RoundRate CurPar SetRate/Parent\n"); ++ if(gu16HandlerCnt) ++ { ++ CAM_OS_LIST_FOR_EACH(pos,&gstClkListHead) ++ { ++ pCfg = CAM_OS_LIST_ENTRY(pos,CAMCLK_Handler,stList); ++ str += CamOsSnprintf(str, end - str, "%-16s %8p %-3u %-3u %1hhd %-9u %-6u %-u\n", ++ pCfg->pDevName,pCfg,pCfg->u32HandlerId&0xFF,pCfg->u32ClkId,pCfg->bEnable,pCfg->u32RoundRate,pCfg->u32CurrentParent,pCfg->attribute); ++ } ++ } ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Debug Handler ========================\n"); ++ return (str - buf); ++} ++u32 DrvCamclkDebugClkShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u32 u32idx; ++ u16 u16Select; ++ u8 u8bEn; ++ DrvCamClkGetParent_t stCfg; ++ DrvCamClkGetRate_t stRateCfg; ++ ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Debug Clk ========================\n"); ++ str += CamOsSnprintf(str, end - str, "CId Type Enable RefCnt Select Parent Freq\n"); ++ //CamOsPrintf("======================== CamClk Debug Clk ========================\n"); ++ //CamOsPrintf("Clk CId Type Enable Select Parent Freq\n"); ++ for(u32idx=u32gclkshowtempidx;u32idx=PAGE_SIZE) ++ { ++ u32gclkshowtempidx = u32idx+1; ++ break; ++ } ++ if(u32idx == HAL_CAMCLK_SRC_Id_MAX-1) ++ { ++ u32gclkshowtempidx = 0; ++ break; ++ } ++ } ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Debug Clk ========================\n"); ++ ++ ++ return (str - buf); ++} ++void DrvCamclkDebugDebugLvlStore(const char *buf) ++{ ++ char *str = (char *)buf; ++ gCAMCLKDbgLvl = CamOsStrtol(str, NULL, 16); ++ ++} ++u32 DrvCamclkDebugDebugLvlShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Debug Message Level ========================\n"); ++ str += CamOsSnprintf(str, end - str, "Debug log level : %lu\n",gCAMCLKDbgLvl); ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Debug Message Level ========================\n"); ++ ++ return (str - buf); ++} ++#endif ++#undef DRV_CAMCLK_DEBUG_C +diff --git a/drivers/sstar/camclk/drv/src/drv_camclk_impl.c b/drivers/sstar/camclk/drv/src/drv_camclk_impl.c +new file mode 100644 +index 000000000000..0e7bdc9ef05e +--- /dev/null ++++ b/drivers/sstar/camclk/drv/src/drv_camclk_impl.c +@@ -0,0 +1,906 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLK_C ++#include "hal_camclk_if.h" ++#include "hal_camclk.h" ++#include "hal_camclk_lpll_tbl.h" ++#include "camclk_dbg.h" ++#include "hal_camclk_util.h" ++#include "drv_camclk.h" ++CamOsTsem_t gstTsem; ++#define CAMCLK_1M 1000000 ++ ++ ++CAMCLK_RET_e _DrvCamClkImplSwInit(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ memset(gCamClkTopCurrent, 0, sizeof(HalCamClkTopClk_t)*HAL_CAMCLK_SRC_Id_MAX); ++ CamOsTsemInit(&gstTsem, 1); ++ return enRet; ++} ++CAMCLK_RET_e _DrvCamClkImplSwDeinit(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ CamOsTsemDeinit(&gstTsem); ++ return enRet; ++} ++ ++CAMCLK_RET_e _DrvCamClkImplSetAutoEnable(HalCamClkSrcId_e u32Id) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++#ifndef CONFIG_NOTTOAUTOENABLE ++ DrvCamClkSetOnOff_t stCfg; ++ ++ if(gCamClkSrcNode[u32Id].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++#ifndef CONFIG_CAMCLK_AUTOENABLE ++ if(gCamClkSrcNode[u32Id].attribute.stComposite.u8auto && (gCamClkTopCurrent[u32Id].u8RefCnt == 0)) ++#else ++ if(gCamClkTopCurrent[u32Id].u8RefCnt == 0) ++#endif ++ { ++ stCfg.bEn = 1; ++ stCfg.u32Id = u32Id; ++ DrvCamClkImplSetOnOff(&stCfg); ++ } ++ } ++ #endif ++ return enRet; ++} ++CAMCLK_RET_e _DrvCamClkImplHwInit(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ HalCamClkSrcId_e u32Id; ++ ++ for(u32Id=0;u32IdPfnSetAdjInit) ++ { ++ gCamClkSrcNode[u32Id].attribute.stComplex.ptOps->PfnSetAdjInit(NULL); ++ } ++ } ++ } ++ return enRet; ++} ++CAMCLK_RET_e _DrvCamClkImplHwDeinit(void) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ HalCamClkSrcId_e u32Id; ++ //ToDo: disable all clock. ++ for(u32Id=0;u32IdPfnSetAdjDeInit) ++ { ++ gCamClkSrcNode[u32Id].attribute.stComplex.ptOps->PfnSetAdjDeInit(NULL); ++ } ++ } ++ } ++ return enRet; ++} ++ ++u32 _DrvCamClkImplGetParentCount(HalCamClkSrcId_e u32Id) ++{ ++ u32 u32ParentCount = 1; ++ u32 idx; ++ ++ if(gCamClkSrcNode[u32Id].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ if((gCamClkSrcNode[u32Id].attribute.stComposite.u8SelectWidth)>0) ++ { ++ for(idx=0;idx<(gCamClkSrcNode[u32Id].attribute.stComposite.u8SelectWidth);idx++) ++ { ++ u32ParentCount *= 2; ++ } ++ } ++ } ++ ++ return u32ParentCount; ++} ++ ++CAMCLK_RET_e _DrvCamClkImplGetAllParentId(HalCamClkSrcId_e u32Id, HalCamClkSrcId_e *u32ParentId,u32 u32Count) ++{ ++ u32 u32idx; ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ ++ if(gCamClkSrcNode[u32Id].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ for(u32idx=0;u32idxPfnGetAdjOnOff) ++ { ++ gCamClkSrcNode[u32Id].attribute.stComplex.ptOps->PfnGetAdjOnOff(&stCfg); ++ *p8bEn = stCfg.bEn; ++ } ++ else ++ { ++ *p8bEn = 0; ++ enRet = CAMCLK_RET_FAIL; ++ } ++ } ++ else ++ { ++ u16off = gCamClkSrcNode[u32Id].attribute.stComposite.u16Gated; ++ if(u16off) ++ { ++ *p8bEn = (R2BYTE(gCamClkSrcNode[u32Id].attribute.stComposite.u32Reg) & u16off) ? 0 : 1; ++ } ++ else ++ { ++ *p8bEn = 2; ++ } ++ } ++ ++ return enRet; ++} ++CAMCLK_RET_e _DrvCamClkImplGetSelect(DrvCamClkSetParent_t *pCfg, u16 *p16Select) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ u8 u8idx; ++ u8 u8off,u8wid; ++ if(gCamClkSrcNode[pCfg->u32Id].u8ClkType!=HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ enRet = CAMCLK_RET_FAIL; ++ } ++ else ++ { ++ *p16Select = 0; ++ u8off = gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u8SelectShift; ++ u8wid =1; ++ if((gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u8SelectWidth)>0) ++ { ++ for(u8idx=0;u8idx<(gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u8SelectWidth);u8idx++) ++ { ++ u8wid *= 2; ++ } ++ } ++ else ++ { ++ enRet = CAMCLK_RET_NOTSUPPORT; ++ goto ReturnBack; ++ } ++ for(u8idx=0;u8idxu32ParentId == gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u8parent[u8idx]) ++ { ++ *p16Select = (u8idx<>(gCamClkSrcNode[u32Id].attribute.stComposite.u8SelectShift)); ++ } ++ else ++ { ++ *p16Select = 0; ++ enRet = CAMCLK_RET_NOTSUPPORT; ++ } ++ return enRet; ++} ++CAMCLK_RET_e DrvCamClkImplGetParent(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkGetParent_t *pstCfg = pCfg; ++ u16 u16Select; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id); ++ if(pstCfg->u32Id < HAL_CAMCLK_SRC_Id_MAX) ++ { ++ if(gCamClkSrcNode[pstCfg->u32Id].u8ClkType == HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ DrvCamClkImplGetHwSelect(pstCfg->u32Id,&u16Select); ++ pstCfg->u32ParentId = gCamClkSrcNode[pstCfg->u32Id].attribute.stComposite.u8parent[u16Select]; ++ } ++ else ++ { ++ _DrvCamClkImplGetAllParentId(pstCfg->u32Id,&pstCfg->u32ParentId,1); ++ } ++ ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ } ++ return enRet; ++} ++// For Horizontal ++CAMCLK_RET_e DrvCamClkImplGetIdAllParent(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkGetAllParent_t *pstCfg = pCfg; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id); ++ if(pstCfg->u32Id < HAL_CAMCLK_SRC_Id_MAX) ++ { ++ pstCfg->u32ParentCount = _DrvCamClkImplGetParentCount(pstCfg->u32Id); ++ _DrvCamClkImplGetAllParentId(pstCfg->u32Id,pstCfg->u32ParentId,pstCfg->u32ParentCount); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ } ++ return enRet; ++} ++// For Vertical ++CAMCLK_RET_e _DrvCamClkImplGetAllParentList(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkGetAllParent_t *pstCfg = pCfg; ++ HalCamClkSrcId_e u32ParentId; ++ DrvCamClkGetParent_t stParentCfg; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id); ++ u32ParentId = pstCfg->u32Id; ++ if(pstCfg->u32Id < HAL_CAMCLK_SRC_Id_MAX) ++ { ++ pstCfg->u32ParentCount = 1; ++ pstCfg->u32ParentId[0] = pstCfg->u32Id; ++ while(1) ++ { ++ if(u32ParentId!=HAL_CAMCLK_SRC_CLK_VOID) ++ { ++ if(pstCfg->u32ParentCount>=MAX_CLK_SRC_PARENT_NODE_CNT) ++ { ++ enRet = CAMCLK_RET_FAIL; ++ CAMCLKERR("[%s @ %d] ParentList > MAX\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ stParentCfg.u32Id = u32ParentId; ++ DrvCamClkImplGetParent((void *)&stParentCfg); ++ u32ParentId = stParentCfg.u32ParentId; ++ pstCfg->u32ParentId[pstCfg->u32ParentCount] = u32ParentId; ++ pstCfg->u32ParentCount++; ++ } ++ else ++ { ++ break; ++ } ++ ++ } ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ } ++ return enRet; ++} ++void _DrvCamClkImplGetParentFreq(HalCamClkSrcId_e u32Id,u32 *p32Freq) ++{ ++ DrvCamClkGetRate_t stRateCfg; ++ DrvCamClkGetParent_t stPCfg; ++ ++ stPCfg.u32Id = u32Id; ++ DrvCamClkImplGetParent(&stPCfg); ++ stRateCfg.u32Id = stPCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ *p32Freq = stRateCfg.u32Freq; ++} ++void _DrvCamClkImplGetHeaderFreq(DrvCamClkGetAllParent_t *pCfg,u32 *u32Freq) ++{ ++ u32 u32Idx; ++ HalCamClkGetComplexRate_t stPllCfg; ++ ++ for(u32Idx=0;u32Idxu32ParentCount;u32Idx++) ++ { ++ if(gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ if(gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].attribute.stComplex.ptOps->PfnGetAdjRate) ++ { ++ _DrvCamClkImplGetParentFreq(pCfg->u32ParentId[u32Idx],&stPllCfg.u32ParentRate); ++ gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].attribute.stComplex.ptOps->PfnGetAdjRate(&stPllCfg); ++ *u32Freq = stPllCfg.u32Rate; ++ break; ++ } ++ ++ } ++ if(gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].u8ClkType==HAL_CAMCLK_TYPE_FIXED) ++ { ++ *u32Freq = gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].attribute.stFixed.u32Freq; ++ break; ++ } ++ } ++} ++void _DrvCamClkImplGetMultDiv(DrvCamClkGetAllParent_t *pCfg,u32 *u32Mult,u32 *u32Div) ++{ ++ u32 u32Idx; ++ *u32Mult = 1; ++ *u32Div = 1; ++ for(u32Idx=0;u32Idxu32ParentCount;u32Idx++) ++ { ++ if(gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].u8ClkType==HAL_CAMCLK_TYPE_FIXED_FACTOR) ++ { ++ *u32Mult *= gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].attribute.stFixedFac.u8Mult; ++ *u32Div *= gCamClkSrcNode[pCfg->u32ParentId[u32Idx]].attribute.stFixedFac.u8Div; ++ } ++ } ++} ++void _DrvCamClkImplCalClkFreq(DrvCamClkGetAllParent_t *pCfg, DrvCamClkGetRate_t *pstCfg) ++{ ++ u32 u32Mult,u32Div; ++ _DrvCamClkImplGetHeaderFreq(pCfg,&pstCfg->u32Freq); ++ _DrvCamClkImplGetMultDiv(pCfg,&u32Mult,&u32Div); ++ pstCfg->u32Freq = (pstCfg->u32Freq/u32Div) * u32Mult; ++} ++ ++void _DrvCamClkImplGetRateDiff(u32 u32Freq,u32 u32ParentFreq,DrvCamClkRateDiff_t *pDiff) ++{ ++ if(u32ParentFreq >= u32Freq) ++ { ++ pDiff->bLess = 0; ++ pDiff->u32diff = u32ParentFreq - u32Freq; ++ } ++ else ++ { ++ pDiff->bLess = 1; ++ pDiff->u32diff = u32Freq - u32ParentFreq; ++ } ++ ++} ++void _DrvCamClkImplGetRoundRateParent(DrvCamClkGetRoundRateParent_t *pstCfg, DrvCamClkGetAllParent_t *pCfg, DrvCamClkRateDiff_t *pstDiff) ++{ ++ u8 bGood = 0; // if condition match,first priority. ++ u32 u32idx,u32TempIdx; ++ u32 u32Diff = 0xFFFFFFFF; ++ u32TempIdx = 0; ++ ++ for(u32idx=0;u32idxu32ParentCount;u32idx++) ++ { ++ if(pCfg->u32ParentId[u32idx]==HAL_CAMCLK_SRC_CLK_VOID) ++ { ++ continue; ++ } ++ if(pstDiff[u32idx].u32diff==0) ++ { ++ u32Diff = pstDiff[u32idx].u32diff; ++ u32TempIdx = u32idx; ++ if(gCamClkSrcNode[pCfg->u32ParentId[u32idx]].u8ClkType!=HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ break; ++ } ++ } ++ else if(pstDiff[u32idx].u32diffenType==CAMCLK_ROUNDRATE_DOWN) ++ { ++ if(!pstDiff[u32idx].bLess && bGood) ++ { ++ //if already find down rate,pass this up rate. ++ continue; ++ } ++ if(pstDiff[u32idx].bLess) ++ { ++ bGood = 1; ++ } ++ } ++ if(pstCfg->enType==CAMCLK_ROUNDRATE_UP) ++ { ++ if(pstDiff[u32idx].bLess && bGood) ++ { ++ //if already find up rate,pass this down rate. ++ continue; ++ } ++ if(!pstDiff[u32idx].bLess) ++ { ++ bGood = 1; ++ } ++ } ++ u32Diff = pstDiff[u32idx].u32diff; ++ u32TempIdx = u32idx; ++ } ++ ++ } ++ pstCfg->u32ParentId = pCfg->u32ParentId[u32TempIdx]; ++ pstCfg->u32RetFreq = (pstDiff[u32TempIdx].bLess) ? (pstCfg->u32Freq - u32Diff) : (pstCfg->u32Freq +u32Diff) ; ++} ++ ++CAMCLK_RET_e DrvCamClkImplGetAdjustRoundRate(DrvCamClkGetRoundRateParent_t *pstCfg) ++{ ++ // ToDo:complex pll roundrate ops ++ HalCamClkGetComplexRoundRate_t stCfg; ++ CAMCLKDBG("[%s @ %d] Id :%d input Freq:%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id,pstCfg->u32Freq); ++ if((gCamClkSrcNode[pstCfg->u32Id].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) && ++ gCamClkSrcNode[pstCfg->u32Id].attribute.stComplex.ptOps->PfnGetAdjRoundRate) ++ { ++ stCfg.u32Rate = pstCfg->u32Freq; ++ gCamClkSrcNode[pstCfg->u32Id].attribute.stComplex.ptOps->PfnGetAdjRoundRate((void *)&stCfg); ++ pstCfg->u32RetFreq = stCfg.u32RoundRate; ++ pstCfg->u32ParentId = gCamClkSrcNode[pstCfg->u32Id].attribute.stComplex.eParent; ++ return CAMCLK_RET_OK; ++ } ++ else ++ { ++ pstCfg->u32RetFreq = pstCfg->u32Freq; ++ pstCfg->u32ParentId = gCamClkSrcNode[pstCfg->u32Id].attribute.stComplex.eParent; ++ } ++ return CAMCLK_RET_NOTSUPPORT; ++} ++CAMCLK_RET_e DrvCamClkImplSetAdjustRate(DrvCamClkSetAdjRoundRate_t *pstCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ HalCamClkSetComplexRate_t stCfg; ++ CAMCLKDBG("[%s @ %d] Id :%d input Freq:%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id,pstCfg->u32Freq); ++ if((gCamClkSrcNode[pstCfg->u32Id].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) && ++ gCamClkSrcNode[pstCfg->u32Id].attribute.stComplex.ptOps->PfnSetAdjRate) ++ { ++ _DrvCamClkImplGetParentFreq(pstCfg->u32Id,&stCfg.u32ParentRate); ++ stCfg.u32Rate = (pstCfg->u32Freq) ? pstCfg->u32Freq : stCfg.u32ParentRate; ++ gCamClkSrcNode[pstCfg->u32Id].attribute.stComplex.ptOps->PfnSetAdjRate((void *)&stCfg); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_NOTSUPPORT; ++ } ++ return enRet; ++} ++ ++CAMCLK_RET_e _DrvCamClkImplSetParent(DrvCamClkSetParent_t *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ u16 u16SelectMsk = 0; ++ u16 u16Select = 0; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d ParentId :%d\n", __FUNCTION__, __LINE__,pCfg->u32Id,pCfg->u32ParentId); ++ enRet = _DrvCamClkImplGetSelectMsk(pCfg->u32Id,&u16SelectMsk); ++ enRet = _DrvCamClkImplGetSelect(pCfg,&u16Select); ++ if(enRet) ++ { ++ if(enRet==CAMCLK_RET_FAIL) ++ { ++ CAMCLKERR("[%s @ %d] Get HW InfoFail\n", __FUNCTION__, __LINE__); ++ } ++ goto ReturnBack; ++ } ++ else ++ { ++ CAMCLKDBG("[%s @ %d] u16Select :%hx u16SelectMsk :%hx\n", __FUNCTION__, __LINE__,u16Select,u16SelectMsk); ++ } ++ if(gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u16Glitch) ++ { ++ W2BYTEMSK(gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u32Reg, 0,gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u16Glitch); ++ } ++ W2BYTEMSK(gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u32Reg, u16Select , u16SelectMsk); ++ if(gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u16Glitch) ++ { ++ W2BYTEMSK(gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u32Reg, gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u16Glitch,gCamClkSrcNode[pCfg->u32Id].attribute.stComposite.u16Glitch); ++ } ++ ReturnBack: ++ return enRet; ++} ++void _DrvCamClkImplSetRefCnt(HalCamClkSrcId_e eId,u8 bEn) ++{ ++ //CAM_CLK_LOCK_SEM(); ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++ if(bEn) ++ { ++ ++ gCamClkTopCurrent[eId].u8RefCnt+=bEn; ++ } ++ else ++ { ++ if(gCamClkTopCurrent[eId].u8RefCnt) ++ { ++ gCamClkTopCurrent[eId].u8RefCnt--; ++ } ++ } ++ CAM_CLK_FLUSH((void*)gCamClkTopCurrent); ++ //CAM_CLK_UNLOCK_SEM(); ++} ++u32 _DrvCamClkImplCheckRefCnt(HalCamClkSrcId_e eId,u8 bEn) ++{ ++ u32 Ret = bEn; ++ HalCamClkComplexOnOff_t stCfg; ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++ if(gCamClkTopCurrent[eId].u8RefCnt==0 && bEn) ++ { ++ if(gCamClkSrcNode[eId].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ if(!(R2BYTE(gCamClkSrcNode[eId].attribute.stComposite.u32Reg) & gCamClkSrcNode[eId].attribute.stComposite.u16Gated)) ++ { ++ Ret = 2; ++ } ++ } ++ else if(gCamClkSrcNode[eId].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ if(gCamClkSrcNode[eId].attribute.stComplex.ptOps->PfnGetAdjOnOff) ++ { ++ gCamClkSrcNode[eId].attribute.stComplex.ptOps->PfnGetAdjOnOff(&stCfg); ++ if(stCfg.bEn) ++ { ++ Ret = 2; ++ } ++ } ++ } ++ } ++ return Ret; ++} ++void _DrvCamClkImplSetGated(HalCamClkSrcId_e eId,u8 bEn) ++{ ++ HalCamClkComplexOnOff_t stCfg; ++#ifdef CONFIG_NOTTOGATED ++ if(bEn==0) ++ { ++ return; ++ } ++#endif ++ if(gCamClkSrcNode[eId].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ if(gCamClkSrcNode[eId].attribute.stComposite.u16Glitch) ++ { ++ W2BYTEMSK(gCamClkSrcNode[eId].attribute.stComposite.u32Reg, 0,gCamClkSrcNode[eId].attribute.stComposite.u16Glitch); ++ } ++ if(gCamClkSrcNode[eId].attribute.stComposite.u16Gated) ++ { ++ W2BYTEMSK(gCamClkSrcNode[eId].attribute.stComposite.u32Reg, bEn ? 0 :gCamClkSrcNode[eId].attribute.stComposite.u16Gated,gCamClkSrcNode[eId].attribute.stComposite.u16Gated); ++ } ++ if(gCamClkSrcNode[eId].attribute.stComposite.u16Glitch) ++ { ++ W2BYTEMSK(gCamClkSrcNode[eId].attribute.stComposite.u32Reg, gCamClkSrcNode[eId].attribute.stComposite.u16Glitch,gCamClkSrcNode[eId].attribute.stComposite.u16Glitch); ++ } ++ } ++ else if(gCamClkSrcNode[eId].u8ClkType==HAL_CAMCLK_TYPE_COMPLEX) ++ { ++ stCfg.bEn = bEn; ++ if(gCamClkSrcNode[eId].attribute.stComplex.ptOps->PfnSetAdjOnOff) ++ { ++ //CAM_CLK_LOCK_SEM(); ++ gCamClkSrcNode[eId].attribute.stComplex.ptOps->PfnSetAdjOnOff(&stCfg); ++ //CAM_CLK_UNLOCK_SEM(); ++ } ++ } ++} ++void _DrvCamClkImplExecGated(HalCamClkSrcId_e eId,u8 bEn) ++{ ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++ if(!((gCamClkTopCurrent[eId].u8RefCnt>=1 && bEn) || (gCamClkTopCurrent[eId].u8RefCnt==0 && !bEn))) ++ { ++ return ; ++ } ++ _DrvCamClkImplSetGated(eId,bEn); ++} ++ ++CAMCLK_RET_e _DrvCamClkImplResetRefCnt(DrvCamClkSetParent_t *pCfg) ++{ ++ DrvCamClkGetAllParent_t stCfg,stCfgori; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u8 u8RefCnt = 0,idx,idy,idz; ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++ if(gCamClkTopCurrent[pCfg->u32Id].u8RefCnt) ++ { ++ stCfg.u32Id = pCfg->u32ParentId; ++ stCfgori.u32Id = pCfg->u32Id; ++ _DrvCamClkImplGetAllParentList(&stCfg); ++ _DrvCamClkImplGetAllParentList(&stCfgori); ++ if(pCfg->u32ParentId != stCfgori.u32ParentId[1]) ++ { ++ //change parent ++ CAMCLKDBG("[%s @ %d] Clk Source change,need to reset ref count\n", __FUNCTION__, __LINE__); ++ u8RefCnt = gCamClkTopCurrent[pCfg->u32Id].u8RefCnt; ++ for(idx=0;idxu32Id < HAL_CAMCLK_SRC_Id_MAX) ++ { ++ stCfg.u32Id = pstCfg->u32Id; ++ pstCfg->u32Freq = 0; ++ enRet = _DrvCamClkImplGetAllParentList((void *)&stCfg); ++ if(enRet) ++ { ++ goto ReturnBack; ++ } ++ _DrvCamClkImplCalClkFreq(&stCfg,pstCfg); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ goto ReturnBack; ++ } ++ CAMCLKDBG("[%s @ %d] Id :%d Freq:%u\n", __FUNCTION__, __LINE__,pstCfg->u32Id,(u32)(pstCfg->u32Freq)); ++ ReturnBack: ++ return enRet; ++} ++CAMCLK_RET_e DrvCamClkImplGetRoundRateParent(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkGetRoundRateParent_t *pstCfg = pCfg; ++ DrvCamClkGetAllParent_t stCfg; ++ DrvCamClkGetRate_t stRateCfg; ++ DrvCamClkRateDiff_t stDiff[MAX_CLK_SRC_PARENT_NODE_CNT]; ++ u32 u32idx; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d input Freq:%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id,pstCfg->u32Freq); ++ stCfg.u32Id = pstCfg->u32Id; ++ DrvCamClkImplGetIdAllParent((void *)&stCfg); ++ if(stCfg.u32ParentCount>0) ++ { ++ for(u32idx = 0;u32idxu32Freq,stRateCfg.u32Freq,&stDiff[u32idx]); ++ } ++ _DrvCamClkImplGetRoundRateParent(pstCfg,&stCfg,stDiff); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ } ++ return enRet; ++} ++CAMCLK_RET_e _DrvCamClkImplCheckParent(DrvCamClkSetParent_t *pstCfg) ++{ ++ u8 idx; ++ for(idx=0;idxu32Id].attribute.stComposite.u8parent[idx]==pstCfg->u32ParentId) ++ { ++ return CAMCLK_RET_OK; ++ } ++ } ++ return CAMCLK_RET_FAIL; ++} ++CAMCLK_RET_e DrvCamClkImplSetParent(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkSetParent_t *pstCfg = pCfg; ++ // ToDo: to control switch clk source,it need to reduce/add ref count. ++ CAMCLKDBG("[%s @ %d] Id :%d Parent Freq: %lu Parent Id :%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id,pstCfg->u32ParentFreq,pstCfg->u32ParentId); ++ if(gCamClkSrcNode[pstCfg->u32Id].u8ClkType==HAL_CAMCLK_TYPE_COMPOSITE) ++ { ++ if(_DrvCamClkImplCheckParent(pstCfg)) ++ { ++ return CAMCLK_RET_FAIL; ++ } ++ CAM_CLK_LOCK_SEM(); ++ _DrvCamClkImplResetRefCnt(pstCfg); ++ _DrvCamClkImplSetParent(pstCfg); ++ CAM_CLK_UNLOCK_SEM(); ++ } ++ else ++ { ++ enRet = CAMCLK_RET_FAIL; ++ } ++ return enRet; ++} ++CAMCLK_RET_e DrvCamClkImplGetOnOff(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkGetOnOff_t *pstCfg = pCfg; ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++ if(gCamClkTopCurrent[pstCfg->u32Id].u8RefCnt) ++ { ++ *pstCfg->pbEn = 1; ++ } ++ CAMCLKDBG("[%s @ %d] Id :%d En:%hhd\n", __FUNCTION__, __LINE__,pstCfg->u32Id,*pstCfg->pbEn); ++ return enRet; ++} ++CAMCLK_RET_e DrvCamClkImplSetOnOff(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkSetOnOff_t *pstCfg = pCfg; ++ DrvCamClkGetAllParent_t stCfg; ++ u32 u32idx; ++ u32 u32AddRefCnt; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id,pstCfg->bEn); ++ if(pstCfg->u32Id < HAL_CAMCLK_SRC_Id_MAX) ++ { ++ stCfg.u32Id = pstCfg->u32Id; ++ enRet = _DrvCamClkImplGetAllParentList((void *)&stCfg); ++ if(enRet) ++ { ++ goto ReturnBack; ++ } ++ //u32AddRefCnt = _DrvCamClkImplCheckRefCnt(pstCfg->u32Id,pstCfg->bEn); ++ u32AddRefCnt = pstCfg->bEn; ++ CAM_CLK_LOCK_SEM(); ++ for(u32idx=0;u32idxbEn); ++ } ++ CAM_CLK_UNLOCK_SEM(); ++ } ++ ReturnBack: ++ return enRet; ++} ++CAMCLK_RET_e DrvCamClkImplSetForceOnOff(void *pCfg) ++{ ++ CAMCLK_RET_e enRet = CAMCLK_RET_OK; ++ DrvCamClkSetOnOff_t *pstCfg = pCfg; ++ DrvCamClkGetAllParent_t stCfg; ++ u32 u32idx; ++ ++ CAMCLKDBG("[%s @ %d] Id :%d\n", __FUNCTION__, __LINE__,pstCfg->u32Id,pstCfg->bEn); ++ if(pstCfg->u32Id < HAL_CAMCLK_SRC_Id_MAX) ++ { ++ stCfg.u32Id = pstCfg->u32Id; ++ enRet = _DrvCamClkImplGetAllParentList((void *)&stCfg); ++ if(enRet) ++ { ++ goto ReturnBack; ++ } ++ for(u32idx=0;u32idxbEn); ++ } ++ } ++ ReturnBack: ++ return enRet; ++} ++CAMCLK_RET_e DrvCamClkImplRestoreClk(void) ++{ ++ HalCamClkSrcId_e u32Id; ++ u8 u8En; ++ DrvCamClkSetOnOff_t stCfg; ++ ++ CAM_CLK_LOCK_SEM(); ++ CAM_CLK_INVALIDATE((void*)gCamClkTopCurrent); ++ for(u32Id=0;u32Id ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "irqs.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "cam_sysfs.h" ++#include "cam_os_wrapper.h" ++#include "drv_camclk_Api.h" ++#include "drv_camclk_DataType.h" ++#include "drv_camclk.h" ++#include "camclk_dbg.h" ++//------------------------------------------------------------------------------------------------- ++// Define & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define DRV_CAMCLK_DEVICE_COUNT 1 ++#define DRV_CAMCLK_DEVICE_NAME "camclk" ++#define DRV_CAMCLK_DEVICE_MAJOR 0x8a ++#define DRV_CAMCLK_DEVICE_MINOR 0x0 ++#define DRV_CAMCLK_DEVICE_NODE "camdriver,camclk" ++#define DRV_CAMCLK_DEVICEINIT_NODE "camdriver,camclkinit" ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++static int DrvCamClkModuleProbe(struct platform_device *pdev); ++static int DrvCamClkModuleRemove(struct platform_device *pdev); ++static int DrvCamClkModuleSuspend(struct platform_device *pdev, pm_message_t state); ++static int DrvCamClkModuleResume(struct platform_device *pdev); ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ int binit; ++ struct cdev cdev; ++ struct file_operations fops; ++ struct device *devicenode; ++ ++} DrvCamClkModuleDevice_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++static DrvCamClkModuleDevice_t m_stCamClkDevice = ++{ ++ .s32Major = 0, ++ .s32Minor = DRV_CAMCLK_DEVICE_MINOR, ++ .refCnt = 0, ++ .binit = 0, ++ .devicenode = NULL, ++ .cdev = ++ { ++ .kobj = {.name = DRV_CAMCLK_DEVICE_NAME, }, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct class* m_pstCamClkClass = NULL; ++ ++static const struct of_device_id m_stCamClkMatchTable[] = ++{ ++ { .compatible = DRV_CAMCLK_DEVICE_NODE}, ++ {} ++}; ++ ++static struct platform_driver m_stCamClkPlatformDriver = ++{ ++ .probe = DrvCamClkModuleProbe, ++ .remove = DrvCamClkModuleRemove, ++ .suspend = DrvCamClkModuleSuspend, ++ .resume = DrvCamClkModuleResume, ++ .driver = ++ { ++ .name = DRV_CAMCLK_DEVICE_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(m_stCamClkMatchTable), ++ }, ++}; ++ ++static struct platform_device m_stDrvCamClkPlatformDevice = ++{ ++ .name = DRV_CAMCLK_DEVICE_NAME, ++ .id = 0, ++ .dev = ++ { ++ .of_node = NULL, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++void _DrvCamClkModuleInit(void) ++{ ++#ifdef CONFIG_CAM_CLK_SYSFS ++ dev_t dev = 0; ++#endif ++ if (m_stCamClkDevice.refCnt == 0) ++ { ++ m_stCamClkDevice.refCnt++; ++#ifdef CONFIG_CAM_CLK_SYSFS ++ m_pstCamClkClass = msys_get_sysfs_class(); ++ ++ if (IS_ERR(m_pstCamClkClass)) ++ { ++ CAMCLKERR("[%s @ %d] msys_get_sysfs_class() fail. \n", ++ __FUNCTION__, __LINE__); ++ } ++ ++ if (m_stCamClkDevice.devicenode == NULL && m_pstCamClkClass) ++ { ++ // Creates a device and registers it with sysfs ++ m_stCamClkDevice.devicenode = CamDeviceCreate(m_pstCamClkClass, NULL, dev, NULL, DRV_CAMCLK_DEVICE_NAME); ++ ++ if (NULL == m_stCamClkDevice.devicenode) ++ { ++ CAMCLKERR("[%s @ %d] device_create() fail\n", __FUNCTION__, __LINE__); ++ } ++ } ++#endif ++ if(m_stCamClkDevice.binit==0) ++ { ++ CamClkInit(); ++ } ++ DrvCamClkOsGetShareMemory(DRV_CAMCLK_SHAREMEM_TOPCURRENT); ++ DrvCamClkSysfsInit(m_stCamClkDevice.devicenode); ++ } ++ else ++ { ++ m_stCamClkDevice.refCnt++; ++ } ++ ++} ++ ++void _DrvCamClkModuleDeInit(void) ++{ ++ if (m_stCamClkDevice.refCnt) ++ { ++ m_stCamClkDevice.refCnt--; ++ } ++ ++ if (m_stCamClkDevice.refCnt == 0) ++ { ++ CAMCLKERR("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ CamClkDeinit(); ++ m_stDrvCamClkPlatformDevice.dev.of_node = NULL; ++ m_pstCamClkClass = NULL; ++ ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++static int DrvCamClkModuleProbe(struct platform_device *pdev) ++{ ++ CAMCLKINFO("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ CAM_CLK_RECORD("CamClkProbe+"); ++ // Create device ++ m_stDrvCamClkPlatformDevice.dev.of_node = pdev->dev.of_node; ++ _DrvCamClkModuleInit(); ++ CAM_CLK_RECORD("CamClkProbe-"); ++ return 0; ++} ++ ++static int DrvCamClkModuleRemove(struct platform_device *pdev) ++{ ++ CAMCLKINFO( "[%s @ %d]\n", __FUNCTION__, __LINE__); ++ _DrvCamClkModuleDeInit(); ++ CamDeviceUnregister(m_stCamClkDevice.devicenode); ++ ++ return 0; ++} ++ ++static int DrvCamClkModuleSuspend(struct platform_device *dev, pm_message_t state) ++{ ++ CAMCLKDBG("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ ++ return 0; ++} ++ ++static int DrvCamClkModuleResume(struct platform_device *dev) ++{ ++ CAMCLKDBG("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ DrvCamClkResume(); ++ return 0; ++} ++/* ++int _MDrv_CamClk_ModuleInit(void) ++{ ++ int ret = 0; ++ //CAM_CLK_PROFILE_INIT(); ++ CAM_CLK_RECORD("ClkInit+"); ++ CAMCLKDBG("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ ++ // Register a driver for platform-level devices ++ ret = CamPlatformDriverRegister(&m_stCamClkPlatformDriver); ++ ++ if (!ret) ++ { ++ CAMCLKDBG("[%s] CamPlatformDriverRegister() success\n", __FUNCTION__); ++ } ++ else ++ { ++ CAMCLKERR("[%s @ %d] CamPlatformDriverRegister() fail\n", __FUNCTION__, __LINE__); ++ CamPlatformDriverUnregister(&m_stCamClkPlatformDriver); ++ } ++ //CAM_CLK_PROFILE_DONE(); ++ CAM_CLK_RECORD("ClkInit-"); ++ return ret; ++} ++ ++ ++void _MDrv_CamClk_ModuleExit(void) ++{ ++ CamPlatformDriverUnregister(&m_stCamClkPlatformDriver); ++} ++*/ ++void __init CamClk_init(struct device_node *node) ++{ ++ CAM_CLK_RECORD("ClkPreInit+"); ++ CAMCLKDBG("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ CamClkInit(); ++ m_stCamClkDevice.binit = 1; ++ CAM_CLK_RECORD("ClkPreInit-"); ++} ++builtin_platform_driver(m_stCamClkPlatformDriver); ++//early_initcall(_MDrv_CamClk_ModuleInit); ++//fs_initcall_sync(_MDrv_CamClk_ModuleInit); ++CLK_OF_DECLARE(CamClk,DRV_CAMCLK_DEVICEINIT_NODE,CamClk_init); ++//module_init(_MDrv_CamClk_ModuleInit); ++//module_exit(_MDrv_CamClk_ModuleExit); ++late_initcall_sync(DrvCamClkImplDisableUnuseClk); ++//CLK_OF_DECLARE(CamClk,DRV_CAMCLK_DEVICE_NODE,DrvCamClkInit); ++//CLK_OF_DECLARE(ms_clk_composite, "sstar,composite-clock", ms_clk_composite_init); ++MODULE_AUTHOR("CAMDRIVER"); ++MODULE_DESCRIPTION("CLK driver"); ++EXPORT_SYMBOL(CamClkAttrGet); ++EXPORT_SYMBOL(CamClkAttrSet); ++EXPORT_SYMBOL(CamClkSetOnOff); ++EXPORT_SYMBOL(CamClkGetOnOff); ++EXPORT_SYMBOL(CamClkRegister); ++EXPORT_SYMBOL(CamClkUnregister); ++EXPORT_SYMBOL(CamClkRateGet); ++EXPORT_SYMBOL(gCAMCLKDbgLvl); +diff --git a/drivers/sstar/camclk/drv/src/linux/drv_camclk_os.c b/drivers/sstar/camclk/drv/src/linux/drv_camclk_os.c +new file mode 100644 +index 000000000000..8b1081f26a71 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/src/linux/drv_camclk_os.c +@@ -0,0 +1,112 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define DRV_CAMCLK_C ++#include "cam_os_wrapper.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "drv_camclk_Api.h" ++#include "hal_camclk_if.h" ++#include "camclk_dbg.h" ++//================================== ++#include ++#include ++#ifdef CONFIG_SS_DUALOS ++void _DrvCamClkOsGetShareMemorySize(DrvCamClkShareMemoryType_e enType, u32 *u32Size) ++{ ++ if(enType == DRV_CAMCLK_SHAREMEM_TOPCURRENT) ++ { ++ *u32Size = CAM_CLK_REF_CNT_SIZE; ++ } ++ else ++ { ++ *u32Size = 0; ++ } ++} ++unsigned long signal_rtos(u32 type, u32 arg1, u32 arg2, u32 arg3); ++void _DrvCamClkOsGetShareMemoryAddr(void **pMem,u32 u32Size) ++{ ++ static struct resource *_rtkres; ++ // *pMem = XX(); ++ CAMCLKDBG("[%s @ %d]id:%lx\n", __FUNCTION__, __LINE__,CAM_CLK_INTEROS_SHAREMEM); ++ *pMem = (void *)signal_rtos(CAM_CLK_INTEROS_SHAREMEM, 0, 0,0); ++ if(*pMem && (u32)(*pMem)!=-1) ++ { ++ CAMCLKDBG("[%s @ %d]addr :%p\n", __FUNCTION__, __LINE__,*pMem); ++ //*pMem = CamOsPhyMemMap(*pMem,u32Size,0); ++ _rtkres = request_mem_region((u32)*pMem, u32Size, "camclkcur"); ++ *pMem = ioremap(_rtkres->start, resource_size(_rtkres)); ++ CAMCLKDBG("[%s @ %d]addr :%p\n", __FUNCTION__, __LINE__,*pMem); ++ CAM_CLK_INVALIDATE(*pMem); ++ } ++} ++void _DrvCamClkOsSyncShareMemory(void *pMem) ++{ ++ HalCamClkSrcId_e eId; ++ HalCamClkTopClk_t *pstTopCurrent = pMem; ++ CAMCLKDBG("[%s @ %d]addr :%p\n", __FUNCTION__, __LINE__,pMem); ++ ++ if(pMem) ++ { ++ //DUALOS_LOCK_INIT; ++ //DUALOS_LOCK; ++ CAM_CLK_LOCK_SEM(); ++ for(eId = 0;eId ++#include ++#include ++#include ++#include ++ ++#include "cam_sysfs.h" ++#include "cam_clkgen.h" ++#include "cam_sysfs.h" ++#include "cam_os_wrapper.h" ++#include "drv_camclk_Api.h" ++#include "drv_camclk_DataType.h" ++#include "drv_camclk.h" ++#include "camclk_dbg.h" ++#include "drv_camclk.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Internal function ++//------------------------------------------------------------------------------------------------- ++ ++#ifdef CONFIG_CAM_CLK_SYSFS ++ ++static ssize_t Camclk_handlerinfo_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if (NULL != buf) ++ { ++ ++ ++ return n; ++ } ++ ++ return 0; ++} ++ ++static ssize_t Camclk_handlerinfo_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return DrvCamclkDebugHandlerShow(buf); ++} ++ ++static DEVICE_ATTR(handlerinfo, 0644, Camclk_handlerinfo_show, Camclk_handlerinfo_store); ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++static ssize_t Camclk_debuglvl_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if (NULL != buf) ++ { ++ DrvCamclkDebugDebugLvlStore(buf); ++ return n; ++ } ++ ++ return 0; ++} ++ ++static ssize_t Camclk_debuglvl_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return DrvCamclkDebugDebugLvlShow(buf); ++} ++ ++static DEVICE_ATTR(debuglvl, 0644, Camclk_debuglvl_show, Camclk_debuglvl_store); ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++static ssize_t Camclk_clkinfo_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if (NULL != buf) ++ { ++ return n; ++ } ++ ++ return 0; ++} ++ ++static ssize_t Camclk_clkinfo_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return DrvCamclkDebugClkShow(buf); ++} ++ ++static DEVICE_ATTR(clkinfo, 0644, Camclk_clkinfo_show, Camclk_clkinfo_store); ++#endif ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++void DrvCamClkSysfsInit(void *device) ++{ ++#ifdef CONFIG_CAM_CLK_SYSFS ++ DrvCamClkDebugInit(); ++ ++ // Create device attribute ++ if(CamDeviceCreateFile((struct device *)device, &dev_attr_handlerinfo)) ++ { ++ CAMCLKERR("[%s @ %d] Sysfs Create Fail.\n", __FUNCTION__, __LINE__); ++ } ++ CamDeviceCreateFile((struct device *)device, &dev_attr_debuglvl); ++ CamDeviceCreateFile((struct device *)device, &dev_attr_clkinfo); ++#endif ++} ++ ++#undef __CAMCLK_SYSFS_C__ +diff --git a/drivers/sstar/camclk/drv/src/rtk/drv_camclk_module.c b/drivers/sstar/camclk/drv/src/rtk/drv_camclk_module.c +new file mode 100644 +index 000000000000..5cfccfdfee90 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/src/rtk/drv_camclk_module.c +@@ -0,0 +1,205 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++ ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "cam_os_wrapper.h" ++#include "drv_camclk_Api.h" ++#include "drv_camclk_DataType.h" ++#include "drv_camclk.h" ++#include "camclk_dbg.h" ++#include "sys_sys_isw_cli.h" ++//------------------------------------------------------------------------------------------------- ++// Define & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define DRV_CAMCLK_DEVICE_COUNT 1 ++#define DRV_CAMCLK_DEVICE_NAME "camclk" ++#define DRV_CAMCLK_DEVICE_MAJOR 0x8a ++#define DRV_CAMCLK_DEVICE_MINOR 0x0 ++#define DRV_CAMCLK_DEVICE_NODE "camdriver,camclk" ++#define DRV_CAMCLK_DEVICEINIT_NODE "camdriver,camclkinit" ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ int argc; ++ char **argv; ++} CamclkStringConfig_t; ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++u8 u8init = 0; ++ ++void DrvCamclkUtCaseC(const char *buf, u32 n); ++void DrvCamclkUtCaseD(const char *buf, u32 n); ++void DrvCamclkUtCaseE(const char *buf, u32 n); ++void DrvCamclkUtCaseF(const char *buf, u32 n); ++void DrvCamclkUtCaseG(const char *buf, u32 n); ++void DrvCamclkUtCaseS(const char *buf, u32 n); ++void CamClkPrintInfo(char *buf) ++{ ++ char *cur = buf; ++ char *token = NULL; ++ char del[] = "\n"; ++ do ++ { ++ token = strsep(&cur, del); ++ CamOsPrintf("%s\n",token); ++ } ++ while(token); ++} ++void CamClkGetDebuginfo(CamclkStringConfig_t *pstStrCfg) ++{ ++#ifdef CONFIG_CAM_CLK_SYSFS ++ char *str; ++ ++ str = CamOsMemAlloc(4096); ++ if(!strcmp(pstStrCfg->argv[0],"clkinfo")) ++ { ++ DrvCamclkDebugClkShow(str); ++ } ++ else if(!strcmp(pstStrCfg->argv[0],"handlerinfo")) ++ { ++ DrvCamclkDebugHandlerShow(str); ++ } ++ CamClkPrintInfo(str); ++ CamOsMemRelease(str); ++#endif ++} ++ ++void CamClkCliParser(CamclkStringConfig_t *pstStrCfg) ++{ ++#ifdef CAMCLK_RTK_UNITTEST ++ u8 u8level; ++ char str[128]; ++ char* strstart = 0; ++ //char blank = ' '; ++ char cmd; ++#endif ++ if(NULL!=pstStrCfg) ++ { ++#ifdef CONFIG_CAM_CLK_SYSFS ++ if(pstStrCfg->argc == 1) ++ { ++ CamClkGetDebuginfo(pstStrCfg); ++ return; ++ } ++#endif ++#ifdef CAMCLK_RTK_UNITTEST ++ memset(str,' ',128); ++ strstart = str; ++ for(u8level = 0;u8levelargc;u8level++) ++ { ++ CAMCLKERR("%s\n",pstStrCfg->argv[u8level]); ++ if(u8level > 0) ++ { ++ CAMCLKERR("strstart:%p\n",strstart); ++ strstart += CamOsSnprintf(strstart, 128, "%s ",pstStrCfg->argv[u8level]); ++ CAMCLKERR("%s\n",str); ++ } ++ } ++ cmd = pstStrCfg->argv[0][0]; ++ switch(cmd) ++ { ++ case 'C': ++ DrvCamclkUtCaseC(str,0); ++ break; ++ case 'D': ++ DrvCamclkUtCaseD(str,0); ++ break; ++ case 'E': ++ DrvCamclkUtCaseE(str,0); ++ break; ++ case 'F': ++ DrvCamclkUtCaseF(str,0); ++ break; ++ case 'G': ++ DrvCamclkUtCaseG(str,0); ++ break; ++ case 'S': ++ DrvCamclkUtCaseS(str,0); ++ break; ++ default: ++ CAMCLKERR("RGN UT CMD NOT SUPPORT:%c\n", pstStrCfg->argv[0]); ++ break; ++ } ++#endif ++ } ++} ++static char _szCamClkCliAHelpTxt[] = "camclk:clkinfo/Handlerinfo\n"; ++static char _szCamClkCliAUsageTxt[] = "echo C/E/F/...\n"; ++/*=============================================================*/ ++// Global Variable definition ++/*=============================================================*/ ++int _CamClkCli(CLI_t *pCli, char *p); ++ ++CliParseToken_t g_atCamclkMenuTbl[] = ++{ ++ {"echo", _szCamClkCliAHelpTxt, _szCamClkCliAUsageTxt,_CamClkCli, NULL}, ++ PARSE_TOKEN_DELIMITER ++}; ++int _CamClkCli(CLI_t *pvCli, char *p) ++{ ++ u32 idx; ++ CLI_t *pCli = pvCli; ++ CamclkStringConfig_t stTest; ++ char **ppargv = CamOsMemAlloc(320 * sizeof(char *)); ++ ++ stTest.argv = ppargv; ++ stTest.argc = CliTokenCount(pCli); ++ for(idx=0;idxtokenLvl++; ++ stTest.argv[idx] = CliTokenPop(pCli); ++ } ++ CamClkCliParser(&stTest); ++ CamOsMemRelease(ppargv); ++ return 0; ++} ++ ++void _DrvCamClkModuleInit(void) ++{ ++ ++ if (u8init == 0) ++ { ++ CamClkInit(); ++ DrvCamClkOsPrepareShareMemory(DRV_CAMCLK_SHAREMEM_TOPCURRENT); ++ } ++ ++} ++ ++void _DrvCamClkModuleDeInit(void) ++{ ++ if (u8init) ++ { ++ CAMCLKERR("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ CamClkDeinit(); ++ } ++} ++ ++void CamClk_init(void *p) ++{ ++ CAM_CLK_RECORD("CamClkInit+"); ++ CAMCLKDBG("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ _DrvCamClkModuleInit(); ++ u8init = 1; ++ CAM_CLK_RECORD("CamClkInit-"); ++} +diff --git a/drivers/sstar/camclk/drv/src/rtk/drv_camclk_os.c b/drivers/sstar/camclk/drv/src/rtk/drv_camclk_os.c +new file mode 100644 +index 000000000000..f12fb8b64994 +--- /dev/null ++++ b/drivers/sstar/camclk/drv/src/rtk/drv_camclk_os.c +@@ -0,0 +1,58 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define DRV_CAMCLK_C ++#include "cam_os_wrapper.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "drv_camclk_Api.h" ++#include "hal_camclk_if.h" ++#include "camclk_dbg.h" ++//================================== ++#include "drv_dualos.h" ++ ++//====================================== ++//extern void recode_timestamp(int mark, const char* name); ++#ifdef CONFIG_CAM_CLK_PROFILING ++extern void BootTimestampRecord(int mark, const char* name); ++void DrvCamClkOsProf(int mark, const char* name) ++{ ++ BootTimestampRecord(mark,name); ++} ++#endif ++#ifdef CONFIG_SS_DUALOS ++ ++u32 DrvCamClkOsRTKGetShareMemAddrCurrent(u32 arg0, u32 arg1, u32 arg2, u32 arg3) ++{ ++ CAM_CLK_RECORD("RTKGetShareMemAddr+"); ++ CAMCLKDBG("[%s @ %d] ShareAddr:%p id:%lx\n", __FUNCTION__, __LINE__,gCamClkTopCurrent,arg0); ++ if(arg0==CAM_CLK_INTEROS_SHAREMEM) ++ { ++ CAM_CLK_FLUSH((void*)gCamClkTopCurrent); ++ CAM_CLK_RECORD("RTKGetShareMemAddr-"); ++ return (u32)gCamClkTopCurrent; ++ } ++ ++ return 0; ++} ++#endif ++void DrvCamClkOsPrepareShareMemory(DrvCamClkShareMemoryType_e enType) ++{ ++#ifdef CONFIG_SS_DUALOS ++ if(enType==DRV_CAMCLK_SHAREMEM_TOPCURRENT) ++ { ++ interos_sc_reg(CAM_CLK_INTEROS_SHAREMEM, DrvCamClkOsRTKGetShareMemAddrCurrent, "SHARECURRENT"); ++ } ++#endif ++} +diff --git a/drivers/sstar/camclk/hal/common/camclk_dbg.h b/drivers/sstar/camclk/hal/common/camclk_dbg.h +new file mode 100644 +index 000000000000..d2e2efea22fe +--- /dev/null ++++ b/drivers/sstar/camclk/hal/common/camclk_dbg.h +@@ -0,0 +1,58 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_DBG_H ++#define _CAMCLK_DBG_H ++#include "cam_os_wrapper.h" ++#ifndef KERN_SOH ++#define KERN_SOH "\001" /* ASCII Start Of Header */ ++#define KERN_SOH_ASCII '\001' ++ ++#define KERN_EMERG KERN_SOH "0" /* system is unusable */ ++#define KERN_ALERT KERN_SOH "1" /* action must be taken immediately */ ++#define KERN_CRIT KERN_SOH "2" /* critical conditions */ ++#define KERN_ERR KERN_SOH "3" /* error conditions */ ++#define KERN_WARNING KERN_SOH "4" /* warning conditions */ ++#define KERN_NOTICE KERN_SOH "5" /* normal but significant condition */ ++#define KERN_INFO KERN_SOH "6" /* informational */ ++#define KERN_DEBUG KERN_SOH "7" /* debug-level messages */ ++ ++#endif ++ ++#define ASCII_COLOR_RED "\033[1;31m" ++#define ASCII_COLOR_WHITE "\033[1;37m" ++#define ASCII_COLOR_YELLOW "\033[1;33m" ++#define ASCII_COLOR_BLUE "\033[1;36m" ++#define ASCII_COLOR_GREEN "\033[1;32m" ++#define ASCII_COLOR_END "\033[0m" ++extern u32 gCAMCLKDbgLvl; ++typedef enum ++{ ++ CAMCLK_DBG_NONE = 0, ++ CAMCLK_DBG_LVL0 = 0x1, ++ CAMCLK_DBG_LVL1 = 0x2, ++ CAMCLK_DBG_LVL2 = 0x4, ++ CAMCLK_DBG_LVL3 = 0x8, ++} DrvCAMCLKDbgLvl_e; ++ ++ ++#define CAMCLK_DEBUG (gCAMCLKDbgLvl) ++#define CAMCLK_DEBUG_DEFAULT KERN_DEBUG ++#define CAMCLKERR(_fmt, _args...) CamOsPrintf(ASCII_COLOR_RED _fmt ASCII_COLOR_END, ## _args) ++#define CAMCLKWARN(_fmt, _args...) CamOsPrintf(CAMCLK_DEBUG_DEFAULT _fmt, ## _args) ++#define CAMCLKINFO(_fmt, _args...) ((CAMCLK_DEBUG&CAMCLK_DBG_LVL0) ? CamOsPrintf(CAMCLK_DEBUG_DEFAULT _fmt, ## _args) : CAMCLK_DEBUG) ++#define CAMCLKDBGERR(fmt, args...) ((CAMCLK_DEBUG&CAMCLK_DBG_LVL1) ? CamOsPrintf(CAMCLK_DEBUG_DEFAULT fmt, ## args) : CAMCLK_DEBUG) ++#define CAMCLKDBG(fmt, args...) ((CAMCLK_DEBUG&CAMCLK_DBG_LVL2) ? CamOsPrintf(CAMCLK_DEBUG_DEFAULT fmt, ## args) : CAMCLK_DEBUG) ++#define CAMCLKREGDUMP(fmt, args...) ((CAMCLK_DEBUG&CAMCLK_DBG_LVL3) ? CamOsPrintf(CAMCLK_DEBUG_DEFAULT fmt, ## args) : CAMCLK_DEBUG) ++#endif /* _CAMCLK_DBG_H */ +diff --git a/drivers/sstar/camclk/hal/common/hal_camclk_if.h b/drivers/sstar/camclk/hal/common/hal_camclk_if.h +new file mode 100644 +index 000000000000..d860757871ad +--- /dev/null ++++ b/drivers/sstar/camclk/hal/common/hal_camclk_if.h +@@ -0,0 +1,21 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_IF_H__ ++#define __HAL_CAMCLK_IF_H__ ++#include "hal_camclk.h" ++#include "drv_camclk_DataType.h" ++#include "hal_camclk_if_st.h" ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/common/hal_camclk_if_st.h b/drivers/sstar/camclk/hal/common/hal_camclk_if_st.h +new file mode 100644 +index 000000000000..7a203d37b21c +--- /dev/null ++++ b/drivers/sstar/camclk/hal/common/hal_camclk_if_st.h +@@ -0,0 +1,86 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_IF_ST_H__ ++#define __HAL_CAMCLK_IF_ST_H__ ++#include "camclk_id.h" ++#include "hal_camclk_st.h" ++#include "drv_camclk_DataType.h" ++#define MAX_CLK_SRC_PARENT_NODE_CNT 16 ++typedef enum ++{ ++ HAL_CAMCLK_TYPE_FIXED = 0, ++ HAL_CAMCLK_TYPE_FIXED_FACTOR, ++ HAL_CAMCLK_TYPE_COMPLEX, ++ HAL_CAMCLK_TYPE_COMPOSITE, ++ HAL_CAMCLK_TYPE_MAX ++} HalCamClkType_e; ++ ++ ++ ++//============================================ ++typedef struct ++{ ++ CAMCLK_RET_e (*PfnSetAdjInit)(void *pCfg); ++ CAMCLK_RET_e (*PfnSetAdjDeInit)(void *pCfg); ++ CAMCLK_RET_e (*PfnSetAdjRate)(void *pCfg); ++ CAMCLK_RET_e (*PfnGetAdjRate)(void *pCfg); ++ CAMCLK_RET_e (*PfnGetAdjRoundRate)(void *pCfg); ++ CAMCLK_RET_e (*PfnSetAdjOnOff)(void *pCfg); ++ CAMCLK_RET_e (*PfnGetAdjOnOff)(void *pCfg); ++} HalCamClkAdjOps_t; ++typedef struct ++{ ++ u32 u32Freq; ++} HalCamClkFixedClk_t; ++typedef struct ++{ ++ HalCamClkSrcId_e eParent; ++ u8 u8Div; ++ u8 u8Mult; ++} HalCamClkFixedFactorClk_t; ++typedef struct ++{ ++ HalCamClkSrcId_e eParent; ++ HalCamClkAdjOps_t *ptOps; ++} HalCamClkComplexClk_t; ++typedef struct ++{ ++ u8 u8parent[MAX_CLK_SRC_PARENT_NODE_CNT]; ++ u32 u32Reg; ++ u16 u16Gated; ++ u16 u16Glitch; ++ u8 u8SelectWidth; ++ u8 u8SelectShift; ++ u8 u8auto; ++} HalCamClkCompositeClt_t; ++ ++typedef struct ++{ ++ u8 u8RefCnt; // be enable ++} HalCamClkTopClk_t; ++typedef struct ++{ ++ u8 u8Id; ++ u8 u8ClkType; ++ union ++ { ++ HalCamClkCompositeClt_t stComposite; ++ HalCamClkComplexClk_t stComplex; ++ HalCamClkFixedFactorClk_t stFixedFac; ++ HalCamClkFixedClk_t stFixed; ++ } attribute; ++} HalCamClkNode_t; ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/common/hal_camclk_util.h b/drivers/sstar/camclk/hal/common/hal_camclk_util.h +new file mode 100644 +index 000000000000..3814d4e0d0c9 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/common/hal_camclk_util.h +@@ -0,0 +1,121 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _HAL_CAMCLK_UTIL_H_ ++#define _HAL_CAMCLK_UTIL_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define CAMCLK_BANK_SIZE 512 ++#ifdef camclk_IO_OFFSET ++#undef camclk_IO_OFFSET ++#define camclk_IO_OFFSET 0xDE000000 ++#else ++#define camclk_IO_OFFSET 0x0 ++#endif ++/* macro to get at MMIO space when running virtually */ ++#define CAMCLK_IO_ADDRESS(x) ((u32)(x) + camclk_IO_OFFSET) ++ ++/* read register by byte */ ++#define camclk_readb(a) (*(volatile unsigned char *)CAMCLK_IO_ADDRESS(a)) ++ ++/* read register by word */ ++#define camclk_readw(a) (*(volatile unsigned short *)CAMCLK_IO_ADDRESS(a)) ++ ++/* read register by long */ ++#define camclk_readl(a) (*(volatile unsigned int *)CAMCLK_IO_ADDRESS(a)) ++ ++/* write register by byte */ ++#define camclk_writeb(a, v) (*(volatile unsigned char *)CAMCLK_IO_ADDRESS(a) = (v)) ++ ++/* write register by word */ ++#define camclk_writew(a, v) (*(volatile unsigned short *)CAMCLK_IO_ADDRESS(a) = (v)) ++ ++/* write register by long */ ++#define camclk_writel(a, v) (*(volatile unsigned int *)CAMCLK_IO_ADDRESS(a) = (v)) ++ ++////////////////////////////////////////////////////////////////////////////////// ++ ++#define READ_BYTE(x) camclk_readb(x) ++#define READ_WORD(x) camclk_readw(x) ++#define READ_LONG(x) camclk_readl(x) ++#define WRITE_BYTE(x, y) camclk_writeb(x, (u8)(y)) ++#define WRITE_WORD(x, y) camclk_writew(x, (u16)(y)) ++#define WRITE_LONG(x, y) camclk_writel(x, (u32)(y)) ++ ++#define RIU_READ_BYTE(addr) (READ_BYTE( (addr))) ++#define RIU_READ_2BYTE(addr) (READ_WORD( (addr))) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE(( (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( (addr), val) ++ ++////////////////////////////////////////////////////////////////////////////////// ++ ++#define RBYTE(u32Reg) RIU_READ_BYTE((u32Reg)) ++ ++#define R2BYTE(u32Reg) RIU_READ_2BYTE((u32Reg)) ++ ++#define R2BYTEMSK(u32Reg, u16mask) (( RIU_READ_2BYTE( (u32Reg)) & u16mask )) ++ ++////////////////////////////////////////////////////////////////////////////////// ++ ++#define WBYTE(u32Reg, u8Val) RIU_WRITE_BYTE(((u32Reg)), u8Val) ++ ++#define WBYTEMSK(u32Reg, u8Val, u8Mask) \ ++ RIU_WRITE_BYTE( (((u32Reg)) - ((u32Reg>>1) & 1)), ( RIU_READ_BYTE( (((u32Reg)) - ((u32Reg>>1) & 1)) ) & ~(u8Mask)) | ((u8Val) & (u8Mask)) ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE((u32Reg) , u16Val) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg), (RIU_READ_2BYTE((u32Reg)) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++ ++ ++////////////////////////////////////////////////////////////////////////////////// ++ ++#define camclk_BIT0 0x00000001 ++#define camclk_BIT1 0x00000002 ++#define camclk_BIT2 0x00000004 ++#define camclk_BIT3 0x00000008 ++#define camclk_BIT4 0x00000010 ++#define camclk_BIT5 0x00000020 ++#define camclk_BIT6 0x00000040 ++#define camclk_BIT7 0x00000080 ++#define camclk_BIT8 0x00000100 ++#define camclk_BIT9 0x00000200 ++#define camclk_BIT10 0x00000400 ++#define camclk_BIT11 0x00000800 ++#define camclk_BIT12 0x00001000 ++#define camclk_BIT13 0x00002000 ++#define camclk_BIT14 0x00004000 ++#define camclk_BIT15 0x00008000 ++#define camclk_BIT16 0x00010000 ++#define camclk_BIT17 0x00020000 ++#define camclk_BIT18 0x00040000 ++#define camclk_BIT19 0x00080000 ++#define camclk_BIT20 0x00100000 ++#define camclk_BIT21 0x00200000 ++#define camclk_BIT22 0x00400000 ++#define camclk_BIT23 0x00800000 ++#define camclk_BIT24 0x01000000 ++#define camclk_BIT25 0x02000000 ++#define camclk_BIT26 0x04000000 ++#define camclk_BIT27 0x08000000 ++#define camclk_BIT28 0x10000000 ++#define camclk_BIT29 0x20000000 ++#define camclk_BIT30 0x40000000 ++#define camclk_BIT31 0x80000000 ++ ++#endif // _HAL_camclk_UTIL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity2m/camclk_hal.mak b/drivers/sstar/camclk/hal/infinity2m/camclk_hal.mak +new file mode 100644 +index 000000000000..64e6264a364d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/camclk_hal.mak +@@ -0,0 +1,20 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++ ++PATH_C += \ ++ $(PATH_camclk_hal)/src ++ ++PATH_H += $(PATH_camclk_hal)/common\ ++ $(PATH_camclk_hal)/inc\ ++ $(PATH_camclk_hal)/pub\ ++ $(PATH_camclk)/inc\ ++ $(PATH_camclk)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_cam_os_wrapper)/inc\ ++ ++SRC_C_LIST += hal_camclk_complex.c\ ++ hal_camclk_tbl.c ++ +diff --git a/drivers/sstar/camclk/hal/infinity2m/inc/camclk_id.h b/drivers/sstar/camclk/hal/infinity2m/inc/camclk_id.h +new file mode 100644 +index 000000000000..073b247a4f10 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/inc/camclk_id.h +@@ -0,0 +1,188 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_ID_H__ ++#define __CAMCLK_ID_H__ ++typedef enum ++{ ++ HAL_CAMCLK_SRC_CLK_VOID, ++ HAL_CAMCLK_SRC_CLK_utmi_480m, ++ HAL_CAMCLK_SRC_CLK_mpll_432m, ++ HAL_CAMCLK_SRC_CLK_upll_384m, ++ HAL_CAMCLK_SRC_CLK_upll_320m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m, ++ HAL_CAMCLK_SRC_CLK_utmi_240m, ++ HAL_CAMCLK_SRC_CLK_mpll_216m, ++ HAL_CAMCLK_SRC_CLK_utmi_192m, ++ HAL_CAMCLK_SRC_CLK_mpll_172m, ++ HAL_CAMCLK_SRC_CLK_utmi_160m, ++ HAL_CAMCLK_SRC_CLK_mpll_123m, ++ HAL_CAMCLK_SRC_CLK_mpll_86m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div32, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_123m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div16, ++ HAL_CAMCLK_SRC_CLK_utmi_192m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div5, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div16, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div40, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div64, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div128, ++ HAL_CAMCLK_SRC_CLK_xtali_24m, ++ HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, ++ HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div2, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div4, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div8, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_top, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_dec_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, ++ HAL_CAMCLK_SRC_CLK_miu_p, ++ HAL_CAMCLK_SRC_CLK_mspi0_p, ++ HAL_CAMCLK_SRC_CLK_mspi1_p, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu2x_p, ++ HAL_CAMCLK_SRC_CLK_mcu_p, ++ HAL_CAMCLK_SRC_CLK_mcu_pm_p, ++ HAL_CAMCLK_SRC_CLK_sdio_p, ++ HAL_CAMCLK_SRC_CLK_fcie_p, ++ HAL_CAMCLK_SRC_CLK_tck_buf, ++ HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, ++ HAL_CAMCLK_SRC_CLK_csi2_mac_p, ++ HAL_CAMCLK_SRC_CLK_mipi_tx_dsi_p, ++ HAL_CAMCLK_SRC_CLK_sc_pixel_p, ++ HAL_CAMCLK_SRC_CLK_ccir_in_clk, ++ HAL_CAMCLK_SRC_CLK_eth_buf, ++ HAL_CAMCLK_SRC_CLK_rmii_buf, ++ HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, ++ HAL_CAMCLK_SRC_CLK_armpll_37p125m, ++ HAL_CAMCLK_SRC_CLK_hdmi_in, ++ HAL_CAMCLK_SRC_CLK_dac_in, ++ HAL_CAMCLK_SRC_CLK_miu_ff, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_miu_dec_gp, ++ HAL_CAMCLK_SRC_CLK_miu_dig, ++ HAL_CAMCLK_SRC_CLK_miu_urdma, ++ HAL_CAMCLK_SRC_CLK_miu_miic0, ++ HAL_CAMCLK_SRC_CLK_miu_miic1, ++ HAL_CAMCLK_SRC_CLK_miu_dma0, ++ HAL_CAMCLK_SRC_CLK_riu, ++ HAL_CAMCLK_SRC_CLK_riu_nogating, ++ HAL_CAMCLK_SRC_CLK_riu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_dec_gp, ++ HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mipi_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mcu_if, ++ HAL_CAMCLK_SRC_CLK_miu2x, ++ HAL_CAMCLK_SRC_CLK_axi2x, ++ HAL_CAMCLK_SRC_CLK_mpll_144m, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div2, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div12, ++ HAL_CAMCLK_SRC_CLK_rtc_32k, ++ HAL_CAMCLK_SRC_CLK_rtc_32k_div4, ++ HAL_CAMCLK_SRC_CLK_live_pm, ++ HAL_CAMCLK_SRC_CLK_mcu_pm, ++ HAL_CAMCLK_SRC_CLK_riu_pm, ++ HAL_CAMCLK_SRC_CLK_miupll_clk, ++ HAL_CAMCLK_SRC_CLK_ddrpll_clk, ++ HAL_CAMCLK_SRC_CLK_lpll_clk, ++ HAL_CAMCLK_SRC_CLK_cpupll_clk, ++ HAL_CAMCLK_SRC_CLK_utmi, ++ HAL_CAMCLK_SRC_CLK_upll, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_out, ++ HAL_CAMCLK_SRC_CLK_miu, ++ HAL_CAMCLK_SRC_CLK_miu_xd2miu, ++ HAL_CAMCLK_SRC_CLK_bdma, ++ HAL_CAMCLK_SRC_CLK_ddr_syn, ++ HAL_CAMCLK_SRC_CLK_miu_rec, ++ HAL_CAMCLK_SRC_CLK_mcu, ++ HAL_CAMCLK_SRC_CLK_riubrdg, ++ HAL_CAMCLK_SRC_CLK_spi, ++ HAL_CAMCLK_SRC_CLK_uart0, ++ HAL_CAMCLK_SRC_CLK_uart1, ++ HAL_CAMCLK_SRC_CLK_uart2, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_in, ++ HAL_CAMCLK_SRC_CLK_fuart, ++ HAL_CAMCLK_SRC_CLK_mspi0, ++ HAL_CAMCLK_SRC_CLK_mspi1, ++ HAL_CAMCLK_SRC_CLK_mspi, ++ HAL_CAMCLK_SRC_CLK_miic0, ++ HAL_CAMCLK_SRC_CLK_miic1, ++ HAL_CAMCLK_SRC_CLK_bist, ++ HAL_CAMCLK_SRC_CLK_pwr_ctl, ++ HAL_CAMCLK_SRC_CLK_xtali, ++ HAL_CAMCLK_SRC_CLK_live_c, ++ HAL_CAMCLK_SRC_CLK_live, ++ HAL_CAMCLK_SRC_CLK_sata_phy_108, ++ HAL_CAMCLK_SRC_CLK_sata_phy_432, ++ HAL_CAMCLK_SRC_CLK_disp_432, ++ HAL_CAMCLK_SRC_CLK_bist_dec_gp, ++ HAL_CAMCLK_SRC_CLK_dec_pclk, ++ HAL_CAMCLK_SRC_CLK_dec_aclk, ++ HAL_CAMCLK_SRC_CLK_dec_bclk, ++ HAL_CAMCLK_SRC_CLK_dec_cclk, ++ HAL_CAMCLK_SRC_CLK_xtali_sc_gp, ++ HAL_CAMCLK_SRC_CLK_bist_sc_gp, ++ HAL_CAMCLK_SRC_CLK_emac_ahb, ++ HAL_CAMCLK_SRC_CLK_jpe, ++ HAL_CAMCLK_SRC_CLK_aesdma, ++ HAL_CAMCLK_SRC_CLK_sdio, ++ HAL_CAMCLK_SRC_CLK_dip, ++ HAL_CAMCLK_SRC_CLK_ge, ++ HAL_CAMCLK_SRC_CLK_mop, ++ HAL_CAMCLK_SRC_CLK_disp_216, ++ HAL_CAMCLK_SRC_CLK_sc_pixel, ++ HAL_CAMCLK_SRC_CLK_sata_pm, ++ HAL_CAMCLK_SRC_CLK_sata_axi, ++ HAL_CAMCLK_SRC_CLK_mipi_tx_dsi, ++ HAL_CAMCLK_SRC_CLK_mipi_tx_dsi_apb, ++ HAL_CAMCLK_SRC_CLK_hdmi, ++ HAL_CAMCLK_SRC_CLK_dac, ++ HAL_CAMCLK_SRC_CLK_emac1_tx, ++ HAL_CAMCLK_SRC_CLK_emac1_rx, ++ HAL_CAMCLK_SRC_CLK_emac1_tx_ref, ++ HAL_CAMCLK_SRC_CLK_emac1_rx_ref, ++ HAL_CAMCLK_SRC_CLK_emac_tx, ++ HAL_CAMCLK_SRC_CLK_emac_rx, ++ HAL_CAMCLK_SRC_CLK_emac_tx_ref, ++ HAL_CAMCLK_SRC_CLK_emac_rx_ref, ++ HAL_CAMCLK_SRC_CLK_hemcu_216m, ++ HAL_CAMCLK_SRC_CLK_spi_pm, ++ HAL_CAMCLK_SRC_CLK_pm_sleep, ++ HAL_CAMCLK_SRC_CLK_pwm, ++ HAL_CAMCLK_SRC_CLK_sar, ++ HAL_CAMCLK_SRC_CLK_rtc, ++ HAL_CAMCLK_SRC_CLK_ir, ++ HAL_CAMCLK_SRC_Id_MAX ++} HalCamClkSrcId_e; ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk.h b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk.h +new file mode 100644 +index 000000000000..dd27fd24a52d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk.h +@@ -0,0 +1,26 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_H__ ++#define __HAL_CAMCLK_H__ ++#include "drv_camclk_DataType.h" ++#include "hal_camclk_st.h" ++#include "hal_camclk_if_st.h" ++ ++const extern HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX]; ++extern HalCamClkTopClk_t *gCamClkTopCurrent; ++extern u16 gu16HandlerCnt; ++extern struct CamOsListHead_t gstClkListHead; ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_complex.h b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_complex.h +new file mode 100644 +index 000000000000..3c36d0dd43d0 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_complex.h +@@ -0,0 +1,20 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include "hal_camclk_if_st.h" ++extern HalCamClkAdjOps_t gMiupllOps; ++extern HalCamClkAdjOps_t gDdrpllOps; ++extern HalCamClkAdjOps_t gLpllOps; ++extern HalCamClkAdjOps_t gCpupllOps; ++extern HalCamClkAdjOps_t gFuart0Ops; +diff --git a/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_lpll_tbl.h b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_lpll_tbl.h +new file mode 100644 +index 000000000000..47f5bdc4b74f +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_lpll_tbl.h +@@ -0,0 +1,75 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_LPLL_TBL_H_ ++#define _CAMCLK_LPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define HAL_CAMCLK_LPLL_REG_NUM 6 ++ ++#define DATA_LANE_9MHZ (9000000) ++#define DATA_LANE_9_5MHZ (9500000) ++#define DATA_LANE_12_5MHZ (12500000) ++#define DATA_LANE_25MHZ (25000000) ++#define DATA_LANE_50MHZ (50000000) ++#define DATA_LANE_100MHZ (100000000) ++#define DATA_LANE_187_5MHZ (187500000) ++#define DATA_LANE_200MHZ (200000000) ++#define DATA_LANE_400MHZ (400000000) ++#define DATA_LANE_800MHZ (800000000) ++#define DATA_LANE_1500MHZ (1500000000) ++ ++#define IS_DATA_LANE_LESS_100M(bps) ( bps <= DATA_LANE_100MHZ ) ++#define IS_DATA_LANE_BPS_100M_TO_200M(bps) ( (bps > DATA_LANE_100MHZ) && (bps <= DATA_LANE_200MHZ ) ) ++#define IS_DATA_LANE_BPS_200M_TO_400M(bps) ( (bps > DATA_LANE_200MHZ) && (bps <= DATA_LANE_400MHZ ) ) ++#define IS_DATA_LANE_BPS_400M_TO_800M(bps) ( (bps > DATA_LANE_400MHZ) && (bps <= DATA_LANE_800MHZ ) ) ++#define IS_DATA_LANE_BPS_800M_TO_15000M(bps) ( (bps > DATA_LANE_800MHZ) && (bps <= DATA_LANE_1500MHZ ) ) ++ ++#define IS_DATA_LANE_LESS_9M(bps) ( bps < DATA_LANE_9MHZ ) ++#define IS_DATA_LANE_BPS_9M_TO_9_5M(bps) ( (bps >= DATA_LANE_9MHZ) && (bps < DATA_LANE_9_5MHZ ) ) ++#define IS_DATA_LANE_BPS_12_5M_TO_25M(bps) ( (bps > DATA_LANE_12_5MHZ) && (bps <= DATA_LANE_25MHZ ) ) ++#define IS_DATA_LANE_BPS_25M_TO_50M(bps) ( (bps > DATA_LANE_25MHZ) && (bps <= DATA_LANE_50MHZ ) ) ++#define IS_DATA_LANE_BPS_50M_TO_100M(bps) ( (bps > DATA_LANE_50MHZ) && (bps <= DATA_LANE_100MHZ ) ) ++#define REG_LPLL_BASE 0x103300UL ++#define REG_LPLL_48_L (REG_LPLL_BASE + 0x90) ++#define REG_LPLL_48_H (REG_LPLL_BASE + 0x91) ++#define REG_LPLL_49_L (REG_LPLL_BASE + 0x92) ++#define REG_LPLL_49_H (REG_LPLL_BASE + 0x93) ++ ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ, //0 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ, //1 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ, //2 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ, //3 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_MAX, //4 ++} HalCamClkLpllType_e; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 address; ++ u16 value; ++}HalCamClkLpllTbl_t; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_st.h b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_st.h +new file mode 100644 +index 000000000000..ca2c85a0aeb5 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/inc/hal_camclk_st.h +@@ -0,0 +1,38 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_ST_H__ ++#define __HAL_CAMCLK_ST_H__ ++ ++ ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkSetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkGetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32RoundRate; ++}HalCamClkGetComplexRoundRate_t; ++typedef struct ++{ ++ u8 bEn; ++}HalCamClkComplexOnOff_t; ++#endif /* MHAL_DIP_H */ +diff --git a/drivers/sstar/camclk/hal/infinity2m/pub/camclk.h b/drivers/sstar/camclk/hal/infinity2m/pub/camclk.h +new file mode 100644 +index 000000000000..eef5168553c9 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/pub/camclk.h +@@ -0,0 +1,185 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_upll_384m 3 ++#define CAMCLK_upll_320m 4 ++#define CAMCLK_mpll_288m 5 ++#define CAMCLK_utmi_240m 6 ++#define CAMCLK_mpll_216m 7 ++#define CAMCLK_utmi_192m 8 ++#define CAMCLK_mpll_172m 9 ++#define CAMCLK_utmi_160m 10 ++#define CAMCLK_mpll_123m 11 ++#define CAMCLK_mpll_86m 12 ++#define CAMCLK_mpll_288m_div2 13 ++#define CAMCLK_mpll_288m_div4 14 ++#define CAMCLK_mpll_288m_div8 15 ++#define CAMCLK_mpll_288m_div32 16 ++#define CAMCLK_mpll_216m_div2 17 ++#define CAMCLK_mpll_216m_div4 18 ++#define CAMCLK_mpll_216m_div8 19 ++#define CAMCLK_mpll_123m_div2 20 ++#define CAMCLK_mpll_86m_div2 21 ++#define CAMCLK_mpll_86m_div4 22 ++#define CAMCLK_mpll_86m_div16 23 ++#define CAMCLK_utmi_192m_div4 24 ++#define CAMCLK_utmi_160m_div4 25 ++#define CAMCLK_utmi_160m_div5 26 ++#define CAMCLK_utmi_160m_div8 27 ++#define CAMCLK_xtali_12m 28 ++#define CAMCLK_xtali_12m_div8 29 ++#define CAMCLK_xtali_12m_div16 30 ++#define CAMCLK_xtali_12m_div40 31 ++#define CAMCLK_xtali_12m_div64 32 ++#define CAMCLK_xtali_12m_div128 33 ++#define CAMCLK_xtali_24m 34 ++#define CAMCLK_RTC_CLK_32K 35 ++#define CAMCLK_pm_riu_w_clk_in 36 ++#define CAMCLK_lpll_clk_div2 37 ++#define CAMCLK_lpll_clk_div4 38 ++#define CAMCLK_lpll_clk_div8 39 ++#define CAMCLK_riu_w_clk_in 40 ++#define CAMCLK_riu_w_clk_top 41 ++#define CAMCLK_riu_w_clk_sc_gp 42 ++#define CAMCLK_riu_w_clk_vhe_gp 43 ++#define CAMCLK_riu_w_clk_dec_gp 44 ++#define CAMCLK_riu_w_clk_hemcu_gp 45 ++#define CAMCLK_riu_w_clk_mipi_if_gp 46 ++#define CAMCLK_riu_w_clk_mcu_if_gp 47 ++#define CAMCLK_miu_p 48 ++#define CAMCLK_mspi0_p 49 ++#define CAMCLK_mspi1_p 50 ++#define CAMCLK_miu_sc_gp_p 51 ++#define CAMCLK_miu2x_p 52 ++#define CAMCLK_mcu_p 53 ++#define CAMCLK_mcu_pm_p 54 ++#define CAMCLK_sdio_p 55 ++#define CAMCLK_fcie_p 56 ++#define CAMCLK_tck_buf 57 ++#define CAMCLK_pad2isp_sr_pclk 58 ++#define CAMCLK_csi2_mac_p 59 ++#define CAMCLK_mipi_tx_dsi_p 60 ++#define CAMCLK_sc_pixel_p 61 ++#define CAMCLK_ccir_in_clk 62 ++#define CAMCLK_eth_buf 63 ++#define CAMCLK_rmii_buf 64 ++#define CAMCLK_emac_testrx125_in_lan 65 ++#define CAMCLK_armpll_37p125m 66 ++#define CAMCLK_hdmi_in 67 ++#define CAMCLK_dac_in 68 ++#define CAMCLK_miu_ff 69 ++#define CAMCLK_miu_sc_gp 70 ++#define CAMCLK_miu_dec_gp 71 ++#define CAMCLK_miu_dig 72 ++#define CAMCLK_miu_urdma 73 ++#define CAMCLK_miu_miic0 74 ++#define CAMCLK_miu_miic1 75 ++#define CAMCLK_miu_dma0 76 ++#define CAMCLK_riu 77 ++#define CAMCLK_riu_nogating 78 ++#define CAMCLK_riu_sc_gp 79 ++#define CAMCLK_riu_dec_gp 80 ++#define CAMCLK_riu_hemcu_gp 81 ++#define CAMCLK_riu_mipi_gp 82 ++#define CAMCLK_riu_mcu_if 83 ++#define CAMCLK_miu2x 84 ++#define CAMCLK_axi2x 85 ++#define CAMCLK_mpll_144m 86 ++#define CAMCLK_mpll_144m_div2 87 ++#define CAMCLK_mpll_144m_div4 88 ++#define CAMCLK_xtali_12m_div2 89 ++#define CAMCLK_xtali_12m_div4 90 ++#define CAMCLK_xtali_12m_div12 91 ++#define CAMCLK_rtc_32k 92 ++#define CAMCLK_rtc_32k_div4 93 ++#define CAMCLK_live_pm 94 ++#define CAMCLK_mcu_pm 95 ++#define CAMCLK_riu_pm 96 ++#define CAMCLK_miupll_clk 97 ++#define CAMCLK_ddrpll_clk 98 ++#define CAMCLK_lpll_clk 99 ++#define CAMCLK_cpupll_clk 100 ++#define CAMCLK_utmi 101 ++#define CAMCLK_upll 102 ++#define CAMCLK_fuart0_synth_out 103 ++#define CAMCLK_miu 104 ++#define CAMCLK_miu_xd2miu 105 ++#define CAMCLK_bdma 106 ++#define CAMCLK_ddr_syn 107 ++#define CAMCLK_miu_rec 108 ++#define CAMCLK_mcu 109 ++#define CAMCLK_riubrdg 110 ++#define CAMCLK_spi 111 ++#define CAMCLK_uart0 112 ++#define CAMCLK_uart1 113 ++#define CAMCLK_uart2 114 ++#define CAMCLK_fuart0_synth_in 115 ++#define CAMCLK_fuart 116 ++#define CAMCLK_mspi0 117 ++#define CAMCLK_mspi1 118 ++#define CAMCLK_mspi 119 ++#define CAMCLK_miic0 120 ++#define CAMCLK_miic1 121 ++#define CAMCLK_bist 122 ++#define CAMCLK_pwr_ctl 123 ++#define CAMCLK_xtali 124 ++#define CAMCLK_live_c 125 ++#define CAMCLK_live 126 ++#define CAMCLK_sata_phy_108 127 ++#define CAMCLK_sata_phy_432 128 ++#define CAMCLK_disp_432 129 ++#define CAMCLK_bist_dec_gp 130 ++#define CAMCLK_dec_pclk 131 ++#define CAMCLK_dec_aclk 132 ++#define CAMCLK_dec_bclk 133 ++#define CAMCLK_dec_cclk 134 ++#define CAMCLK_xtali_sc_gp 135 ++#define CAMCLK_bist_sc_gp 136 ++#define CAMCLK_emac_ahb 137 ++#define CAMCLK_jpe 138 ++#define CAMCLK_aesdma 139 ++#define CAMCLK_sdio 140 ++#define CAMCLK_dip 141 ++#define CAMCLK_ge 142 ++#define CAMCLK_mop 143 ++#define CAMCLK_disp_216 144 ++#define CAMCLK_sc_pixel 145 ++#define CAMCLK_sata_pm 146 ++#define CAMCLK_sata_axi 147 ++#define CAMCLK_mipi_tx_dsi 148 ++#define CAMCLK_mipi_tx_dsi_apb 149 ++#define CAMCLK_hdmi 150 ++#define CAMCLK_dac 151 ++#define CAMCLK_emac1_tx 152 ++#define CAMCLK_emac1_rx 153 ++#define CAMCLK_emac1_tx_ref 154 ++#define CAMCLK_emac1_rx_ref 155 ++#define CAMCLK_emac_tx 156 ++#define CAMCLK_emac_rx 157 ++#define CAMCLK_emac_tx_ref 158 ++#define CAMCLK_emac_rx_ref 159 ++#define CAMCLK_hemcu_216m 160 ++#define CAMCLK_spi_pm 161 ++#define CAMCLK_pm_sleep 162 ++#define CAMCLK_pwm 163 ++#define CAMCLK_sar 164 ++#define CAMCLK_rtc 165 ++#define CAMCLK_ir 166 ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity2m/pub/reg_clks.h b/drivers/sstar/camclk/hal/infinity2m/pub/reg_clks.h +new file mode 100644 +index 000000000000..77db2ee1c218 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/pub/reg_clks.h +@@ -0,0 +1,444 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I2m/iNfinity2m_Clock_Table_20190226_SW.xls */ ++/* REG FILENAME: I2m/iNfinity2m_reg_CLKGEN.xls, I2m/iNfinity2m_reg_pm_sleep.xls, I2m/iNfinity2m_reg_block.xls, I2m/iNfinity2m_reg_chiptop.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++#define REG_CHIPTOP_BASE 0x1F203C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CHIPTOP_DUMMY_0_BASE (REG_CHIPTOP_BASE+0x20*4) ++#define REG_CHIPTOP_DUMMY_0_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_1_BASE (REG_CHIPTOP_BASE+0x21*4) ++#define REG_CHIPTOP_DUMMY_1_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_2_BASE (REG_CHIPTOP_BASE+0x22*4) ++#define REG_CHIPTOP_DUMMY_2_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_3_BASE (REG_CHIPTOP_BASE+0x23*4) ++#define REG_CHIPTOP_DUMMY_3_OFFSET (0) ++ ++#define REG_CHIPTOP_RESERVED_BASE (REG_CHIPTOP_BASE+0x7B*4) ++#define REG_CHIPTOP_RESERVED_OFFSET (0) ++ ++#define REG_CKG_DAC_BASE (REG_SC_GP_CTRL_BASE+0x36*4) ++#define REG_CKG_DAC_OFFSET (0) ++ ++#define REG_CKG_EMAC1_RX_BASE (REG_SC_GP_CTRL_BASE+0x33*4) ++#define REG_CKG_EMAC1_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC1_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x33*4) ++#define REG_CKG_EMAC1_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC1_TX_BASE (REG_SC_GP_CTRL_BASE+0x34*4) ++#define REG_CKG_EMAC1_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC1_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x34*4) ++#define REG_CKG_EMAC1_TX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_HDMI_BASE (REG_SC_GP_CTRL_BASE+0x35*4) ++#define REG_CKG_HDMI_OFFSET (0) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_MIPI_TX_DSI_APB_BASE (REG_SC_GP_CTRL_BASE+0x37*4) ++#define REG_CKG_MIPI_TX_DSI_APB_OFFSET (0) ++ ++#define REG_CKG_SD_BASE (REG_SC_GP_CTRL_BASE+0x25*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++#define REG_SRAM_SD_EN_BASE (REG_SC_GP_CTRL_BASE+0x12*4) ++#define REG_SRAM_SD_EN_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_TMP_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_TMP_OFFSET (0) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PWM_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SPI_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_DEC_GP_BASE (REG_CKG_BASE+0x57*4) ++#define REG_CKG_BIST_DEC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DEC_ACLK_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_DEC_ACLK_OFFSET (8) ++ ++#define REG_CKG_DEC_BCLK_BASE (REG_CKG_BASE+0x56*4) ++#define REG_CKG_DEC_BCLK_OFFSET (0) ++ ++#define REG_CKG_DEC_CCLK_BASE (REG_CKG_BASE+0x56*4) ++#define REG_CKG_DEC_CCLK_OFFSET (8) ++ ++#define REG_CKG_DEC_PCLK_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_DEC_PCLK_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_DISP_216_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_DISP_216_OFFSET (8) ++ ++#define REG_CKG_DISP_432_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_DISP_432_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GE_BASE (REG_CKG_BASE+0x51*4) ++#define REG_CKG_GE_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIPI_TX_DSI_BASE (REG_CKG_BASE+0x6F*4) ++#define REG_CKG_MIPI_TX_DSI_OFFSET (0) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MOP_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_MOP_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SATA_AXI_BASE (REG_CKG_BASE+0x6E*4) ++#define REG_CKG_SATA_AXI_OFFSET (0) ++ ++#define REG_CKG_SATA_PHY_108_BASE (REG_CKG_BASE+0x46*4) ++#define REG_CKG_SATA_PHY_108_OFFSET (0) ++ ++#define REG_CKG_SATA_PHY_432_BASE (REG_CKG_BASE+0x46*4) ++#define REG_CKG_SATA_PHY_432_OFFSET (8) ++ ++#define REG_CKG_SATA_PM_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_SATA_PM_OFFSET (8) ++ ++#define REG_CKG_SC_PIXEL_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_SC_PIXEL_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_TMP_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_TMP_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_UART2_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART2_OFFSET (12) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity2m/src/hal_camclk_complex.c b/drivers/sstar/camclk/hal/infinity2m/src/hal_camclk_complex.c +new file mode 100644 +index 000000000000..2e294eb1879b +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/src/hal_camclk_complex.c +@@ -0,0 +1,460 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_LPLL_C ++#include "camclk_dbg.h" ++#include "hal_camclk_if_st.h" ++#include "hal_camclk_lpll_tbl.h" ++#include "hal_camclk_util.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "registers.h" ++#include "ms_platform.h" ++ ++ ++HalCamClkLpllTbl_t gCamClkLPLLSettingTBL[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX][HAL_CAMCLK_LPLL_REG_NUM]= ++{ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0041}, ++ {0x103386, 0x0000}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0042}, ++ {0x103386, 0x0001}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0043}, ++ {0x103386, 0x0002}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0083}, ++ {0x103386, 0x0003}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++}; ++#define PLL_REG_GET(address) (0x1F000000 + ((address)<<1)) ++u16 u16LoopGain[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX]= ++{ ++ 16, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ 8, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ 4, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ 2, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++}; ++u32 u16gLpllDiv = 8; ++u8 bLook = 0; ++void HalCamClkGetLpllIdxFromHw(u16 *pu16Idx) ++{ ++ u16 u16Val; ++ u8 idx; ++ u16Val = R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][2].address)); ++ for(idx =0 ;idx> 16); ++ W2BYTE(PLL_REG_GET(REG_LPLL_48_L), u16LpllSet_Lo); // @suppress("Symbol is not resolved") ++ W2BYTE(PLL_REG_GET(REG_LPLL_49_L), u16LpllSet_Hi); // @suppress("Symbol is not resolved") ++} ++void HalCamClkGetLpllSet(u32 *u32LpllSet) ++{ ++ u16 u16LpllSet_Lo, u16LpllSet_Hi; ++ ++ u16LpllSet_Lo = R2BYTE(PLL_REG_GET(REG_LPLL_48_L)); ++ u16LpllSet_Hi = R2BYTE(PLL_REG_GET(REG_LPLL_49_L)); ++ *u32LpllSet = (u16LpllSet_Lo | ((u32)u16LpllSet_Hi<<16)); ++} ++CAMCLK_RET_e HalCamClkSetLpllRate(void *pCfg) ++{ ++ u16 u16LpllIdx; ++ u16 u16Div; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ HalCamClkSetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ if(bLook) ++ { ++ Ret = CAMCLK_RET_FAIL; ++ CAMCLKERR("%s %d, LPLL Locked:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ else ++ { ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate, &u16LpllIdx, &u16Div)) ++ { ++ if(u16LpllIdx != E_HAL_CAMCLK_SUPPORTED_LPLL_MAX) ++ { ++ u16LoopGain = HalCamClkGetLpllGain(u16LpllIdx); ++ u64Dividen = (pLpllCfg->u32ParentRate); ++ u64Dividen = (u64)(u64Dividen * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16Div,NULL); ++ u32Divisor = pLpllCfg->u32Rate; ++ u32LplLSet = (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ CAMCLKDBG("[CAMCLK]%s %d:: Idx:%d, LoopGain:%d, LoopDiv:%d, dclk=%ld, Divden:0x%llx, Divisor:0x%lx, LpllSe:0x%lx\n", ++ __FUNCTION__, __LINE__, u16LpllIdx, ++ u16LoopGain, u16Div, pLpllCfg->u32Rate, ++ u64Dividen, u32Divisor, u32LplLSet); ++ ++ HalCamClkDumpLpllSetting(u16LpllIdx); ++ HalCamClkSetLpllSet(u32LplLSet); ++ u16gLpllDiv = u16Div; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u16 u16idx; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ ++ HalCamClkGetLpllIdxFromHw(&u16idx); ++ u16LoopGain = HalCamClkGetLpllGain(u16idx); ++ HalCamClkGetLpllSet(&u32LplLSet); ++ u64Dividen = pLpllCfg->u32ParentRate; ++ u64Dividen = (u64)((u64Dividen) * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16gLpllDiv,NULL); ++ u32Divisor = u32LplLSet; ++ pLpllCfg->u32Rate= (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pLpllCfg = pCfg; ++ u16 u16Temp; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate,&u16Temp,&u16Temp)) ++ { ++ pLpllCfg->u32RoundRate = pLpllCfg->u32Rate; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ if(pLpllCfg->u32Rateu32RoundRate = DATA_LANE_12_5MHZ; ++ } ++ else ++ { ++ pLpllCfg->u32RoundRate = DATA_LANE_1500MHZ; ++ } ++ } ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pLpllCfg->bEn = (R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address))&camclk_BIT13)>>13; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address), pLpllCfg->bEn ? camclk_BIT13 : 0 , camclk_BIT13); ++ bLook = pLpllCfg->bEn; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetMiupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pMiupllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_miupll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pMiupllCfg->u32Rate = (u32)CamOsMathDivU64((u64)stRateCfg.u32Freq * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF), (u64)((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2), NULL); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetDdrpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pDdrpllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_ddrpll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pDdrpllCfg->u32Rate = (u32)CamOsMathDivU64(((u64)stRateCfg.u32Freq * 4 * 4) << 19, (u64)((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF)), NULL); ++ ++ return Ret; ++} ++static void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++CAMCLK_RET_e HalCamClkSetCpupllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pCpupllCfg = pCfg; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //CamOsPrintf("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (pCpupllCfg->u32Rate >= 800000000) ++ post_div = 2; ++ else if (pCpupllCfg->u32Rate >= 400000000) ++ post_div = 4; ++ else if (pCpupllCfg->u32Rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, (pCpupllCfg->u32Rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pCpupllCfg = pCfg; ++ u32 lpf_value; ++ u32 post_div; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ //CamOsPrintf("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ pCpupllCfg->u32Rate = (div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ //CamOsPrintf("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", pCpupllCfg->u32Rate, pCpupllCfg->u32ParentRate); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pCpupllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pCpupllCfg->u32Rate < 100000000) // 100MHz ++ { ++ pCpupllCfg->u32RoundRate = 100000000; ++ } ++ else if(pCpupllCfg->u32Rate > 1400000000) // 1.4GHz ++ { ++ pCpupllCfg->u32RoundRate = 1400000000; ++ } ++ else ++ { ++ pCpupllCfg->u32RoundRate = pCpupllCfg->u32Rate; ++ } ++ ++ return Ret; ++} ++HalCamClkAdjOps_t gLpllOps={0,0,HalCamClkSetLpllRate,HalCamClkGetLpllRate,HalCamClkGetLpllRoundRate,HalCamClkSetLpllOnOff,HalCamClkGetLpllOnOff}; ++HalCamClkAdjOps_t gDdrpllOps={0,0,0,HalCamClkGetDdrpllRate,0,0,0}; ++HalCamClkAdjOps_t gMiupllOps={0,0,0,HalCamClkGetMiupllRate,0,0,0}; ++HalCamClkAdjOps_t gCpupllOps={0,0,HalCamClkSetCpupllRate,HalCamClkGetCpupllRate,HalCamClkGetCpupllRoundRate,0,0}; ++HalCamClkAdjOps_t gFuart0Ops={0,0,0,0,0,0,0}; ++#undef HAL_CAMCLKTBL_LPLL_C +diff --git a/drivers/sstar/camclk/hal/infinity2m/src/hal_camclk_tbl.c b/drivers/sstar/camclk/hal/infinity2m/src/hal_camclk_tbl.c +new file mode 100644 +index 000000000000..a354f859c915 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity2m/src/hal_camclk_tbl.c +@@ -0,0 +1,192 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_C ++#include "hal_camclk_if.h" ++#include "hal_camclk_complex.h" ++#include "reg_clks.h" ++#include "hal_camclk_util.h" ++ ++const HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX] = ++{ ++ {HAL_CAMCLK_SRC_CLK_VOID, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_480m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_432m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll_384m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,5,4}}, ++ {HAL_CAMCLK_SRC_CLK_upll_320m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,3,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={288000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_240m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={216000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,5,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_172m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={172800000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,3,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={123400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={86400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div32, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,32,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_123m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_192m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div5, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,5,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={12000000}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div40, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,40,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div64, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,64,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div128, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,128,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_24m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={24000000}}, ++ {HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_top, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_dec_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi0,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_sdio_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_sdio,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fcie_p, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_tck_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_csi2_mac_p, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_mipi_tx_dsi_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mipi_tx_dsi,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_sc_pixel_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_sc_pixel,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_ccir_in_clk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_eth_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_rmii_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_armpll_37p125m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_hdmi_in, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_dac_in, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ff, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_dec_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_dig, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_urdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_miic0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_miic1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_dma0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_top,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_nogating, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_dec_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_dec_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mipi_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mcu_if, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_ddrpll_clk,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_axi2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={144000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div12, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,12,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32768}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_rtc_32k,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_live_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_24m,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m,&gMiupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_ddrpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_ddr_syn,&gDdrpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gLpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_cpupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gCpupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_utmi, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_out, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_fuart0_synth_in,&gFuart0Ops}}, ++ {HAL_CAMCLK_SRC_CLK_miu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_ddrpll_clk,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_miupll_clk,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_MIU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_xd2miu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu},REG_CHIPTOP_DUMMY_1_BASE,camclk_BIT0,0,0,0,1}}, ++ {HAL_CAMCLK_SRC_CLK_bdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_BDMA_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ddr_syn, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DDR_SYN_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_rec, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div64,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div128},REG_CKG_MIU_REC_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mcu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_MCU_BASE,camclk_BIT0,camclk_BIT5,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_riubrdg, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mcu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RIUBRDG_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SPI_BASE,camclk_BIT8,0,3,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_uart0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart2, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART2_BASE,camclk_BIT12,0,2,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_in, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FUART0_SYNTH_IN_BASE,camclk_BIT4,0,2,6,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fuart0_synth_out},REG_CKG_FUART_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mspi0_p,(u8)HAL_CAMCLK_SRC_CLK_mspi1_p},REG_CKG_MSPI_BASE,camclk_BIT12,0,1,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_pwr_ctl, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PWR_CTL_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_live_c, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_live, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_sata_phy_108, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SATA_PHY_108_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sata_phy_432, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SATA_PHY_432_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_disp_432, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DISP_432_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_bist_dec_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_DEC_GP_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_dec_pclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DEC_PCLK_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_dec_aclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_DEC_ACLK_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_dec_bclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CLKGEN0_RESERVED0_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_dec_cclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CLKGEN0_RESERVED0_BASE,camclk_BIT8,0,3,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_SC_GP_BASE,camclk_BIT4,0,2,6,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_SC_GP_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_ahb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan},REG_CKG_EMAC_AHB_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_jpe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_JPE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_aesdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_AESDMA_BASE,camclk_BIT0,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sdio, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SDIO_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_dip, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DIP_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ge, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_GE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mop, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m},REG_CKG_MOP_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_disp_216, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_DISP_216_BASE,camclk_BIT8,0,1,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_sc_pixel, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div32},REG_CKG_SC_PIXEL_BASE,camclk_BIT0,0,4,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sata_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_SATA_PM_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_sata_axi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SATA_AXI_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mipi_tx_dsi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIPI_TX_DSI_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mipi_tx_dsi_apb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mcu_p,(u8)HAL_CAMCLK_SRC_CLK_mipi_tx_dsi_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIPI_TX_DSI_APB_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_hdmi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_hdmi_in,(u8)HAL_CAMCLK_SRC_CLK_sc_pixel_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_HDMI_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_dac, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_dac_in,(u8)HAL_CAMCLK_SRC_CLK_hdmi_in,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DAC_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac1_tx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC1_TX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac1_rx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC1_RX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac1_tx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC1_TX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac1_rx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC1_RX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_TX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_RX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_TX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_RX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_hemcu_216m, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_HEMCU_216M_BASE,camclk_BIT0,0,0,0,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m},REG_CKG_SPI_BASE,camclk_BIT8,camclk_BIT14,4,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_pm_sleep, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_PM_SLEEP_BASE,0,0,3,12,1}}, ++ {HAL_CAMCLK_SRC_CLK_pwm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_PWM_BASE,0,0,3,12,0}}, ++ {HAL_CAMCLK_SRC_CLK_sar, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_SAR_BASE,camclk_BIT5,0,3,7,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RTC_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ir, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_IR_BASE,camclk_BIT5,0,3,7,0}}, ++}; ++ ++#undef HAL_CAMCLKTBL_C +diff --git a/drivers/sstar/camclk/hal/infinity5/camclk_hal.mak b/drivers/sstar/camclk/hal/infinity5/camclk_hal.mak +new file mode 100644 +index 000000000000..64e6264a364d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/camclk_hal.mak +@@ -0,0 +1,20 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++ ++PATH_C += \ ++ $(PATH_camclk_hal)/src ++ ++PATH_H += $(PATH_camclk_hal)/common\ ++ $(PATH_camclk_hal)/inc\ ++ $(PATH_camclk_hal)/pub\ ++ $(PATH_camclk)/inc\ ++ $(PATH_camclk)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_cam_os_wrapper)/inc\ ++ ++SRC_C_LIST += hal_camclk_complex.c\ ++ hal_camclk_tbl.c ++ +diff --git a/drivers/sstar/camclk/hal/infinity5/inc/camclk_id.h b/drivers/sstar/camclk/hal/infinity5/inc/camclk_id.h +new file mode 100644 +index 000000000000..0c4db95d4185 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/inc/camclk_id.h +@@ -0,0 +1,213 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_ID_H__ ++#define __CAMCLK_ID_H__ ++typedef enum ++{ ++ HAL_CAMCLK_SRC_CLK_VOID, ++ HAL_CAMCLK_SRC_CLK_mpll_432m, ++ HAL_CAMCLK_SRC_CLK_upll_384m, ++ HAL_CAMCLK_SRC_CLK_upll_320m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m, ++ HAL_CAMCLK_SRC_CLK_utmi_240m, ++ HAL_CAMCLK_SRC_CLK_mpll_216m, ++ HAL_CAMCLK_SRC_CLK_utmi_192m, ++ HAL_CAMCLK_SRC_CLK_mpll_172m, ++ HAL_CAMCLK_SRC_CLK_utmi_160m, ++ HAL_CAMCLK_SRC_CLK_mpll_123m, ++ HAL_CAMCLK_SRC_CLK_mpll_86m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_123m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div16, ++ HAL_CAMCLK_SRC_CLK_utmi_192m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div5, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div16, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div40, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div64, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div128, ++ HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, ++ HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_top, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, ++ HAL_CAMCLK_SRC_CLK_miu_p, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu2x_p, ++ HAL_CAMCLK_SRC_CLK_mcu_p, ++ HAL_CAMCLK_SRC_CLK_mcu_pm_p, ++ HAL_CAMCLK_SRC_CLK_isp_p, ++ HAL_CAMCLK_SRC_CLK_fclk1_p, ++ HAL_CAMCLK_SRC_CLK_fclk2_p, ++ HAL_CAMCLK_SRC_CLK_sdio_p, ++ HAL_CAMCLK_SRC_CLK_fcie_p, ++ HAL_CAMCLK_SRC_CLK_tck_buf, ++ HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, ++ HAL_CAMCLK_SRC_CLK_ccir_in_clk, ++ HAL_CAMCLK_SRC_CLK_eth_buf, ++ HAL_CAMCLK_SRC_CLK_rmii_buf, ++ HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, ++ HAL_CAMCLK_SRC_CLK_miu_ff, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_miu_dig, ++ HAL_CAMCLK_SRC_CLK_miu_xd2miu, ++ HAL_CAMCLK_SRC_CLK_miu_urdma, ++ HAL_CAMCLK_SRC_CLK_miu_bdma, ++ HAL_CAMCLK_SRC_CLK_miu_vhe, ++ HAL_CAMCLK_SRC_CLK_miu_jpe1, ++ HAL_CAMCLK_SRC_CLK_miu_jpe0, ++ HAL_CAMCLK_SRC_CLK_miu_bach, ++ HAL_CAMCLK_SRC_CLK_miu_file, ++ HAL_CAMCLK_SRC_CLK_miu_uhc0, ++ HAL_CAMCLK_SRC_CLK_miu_emac, ++ HAL_CAMCLK_SRC_CLK_miu_cmdq, ++ HAL_CAMCLK_SRC_CLK_miu_isp_dnr, ++ HAL_CAMCLK_SRC_CLK_miu_isp_rot, ++ HAL_CAMCLK_SRC_CLK_miu_isp_dma, ++ HAL_CAMCLK_SRC_CLK_miu_isp_sta, ++ HAL_CAMCLK_SRC_CLK_miu_gop, ++ HAL_CAMCLK_SRC_CLK_miu_sc_dnr, ++ HAL_CAMCLK_SRC_CLK_miu_sc_dnr_sad, ++ HAL_CAMCLK_SRC_CLK_miu_sc_crop, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_frm, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_snp, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_snpi, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_dbg, ++ HAL_CAMCLK_SRC_CLK_miu_sc2_frm, ++ HAL_CAMCLK_SRC_CLK_miu_sc2_snpi, ++ HAL_CAMCLK_SRC_CLK_miu_sc3_frm, ++ HAL_CAMCLK_SRC_CLK_miu_fcie, ++ HAL_CAMCLK_SRC_CLK_miu_sdio, ++ HAL_CAMCLK_SRC_CLK_miu_ive, ++ HAL_CAMCLK_SRC_CLK_riu, ++ HAL_CAMCLK_SRC_CLK_riu_nogating, ++ HAL_CAMCLK_SRC_CLK_riu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mipi_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mcu_if, ++ HAL_CAMCLK_SRC_CLK_miu2x, ++ HAL_CAMCLK_SRC_CLK_axi2x, ++ HAL_CAMCLK_SRC_CLK_tck, ++ HAL_CAMCLK_SRC_CLK_imi, ++ HAL_CAMCLK_SRC_CLK_gop0, ++ HAL_CAMCLK_SRC_CLK_gop1, ++ HAL_CAMCLK_SRC_CLK_gop2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_24m, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div2, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div12, ++ HAL_CAMCLK_SRC_CLK_rtc_32k, ++ HAL_CAMCLK_SRC_CLK_rtc_32k_div4, ++ HAL_CAMCLK_SRC_CLK_live_pm, ++ HAL_CAMCLK_SRC_CLK_riu_pm, ++ HAL_CAMCLK_SRC_CLK_miupll_clk, ++ HAL_CAMCLK_SRC_CLK_ddrpll_clk, ++ HAL_CAMCLK_SRC_CLK_lpll_clk, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div2, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div4, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div8, ++ HAL_CAMCLK_SRC_CLK_cpupll_clk, ++ HAL_CAMCLK_SRC_CLK_ipupll_clk, ++ HAL_CAMCLK_SRC_CLK_venpll_clk, ++ HAL_CAMCLK_SRC_CLK_utmi, ++ HAL_CAMCLK_SRC_CLK_upll, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_out, ++ HAL_CAMCLK_SRC_CLK_csi2_mac_p, ++ HAL_CAMCLK_SRC_CLK_miu, ++ HAL_CAMCLK_SRC_CLK_ddr_syn, ++ HAL_CAMCLK_SRC_CLK_miu_rec, ++ HAL_CAMCLK_SRC_CLK_mcu, ++ HAL_CAMCLK_SRC_CLK_riubrdg, ++ HAL_CAMCLK_SRC_CLK_bdma, ++ HAL_CAMCLK_SRC_CLK_spi, ++ HAL_CAMCLK_SRC_CLK_uart0, ++ HAL_CAMCLK_SRC_CLK_uart1, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_in, ++ HAL_CAMCLK_SRC_CLK_fuart, ++ HAL_CAMCLK_SRC_CLK_mspi0, ++ HAL_CAMCLK_SRC_CLK_mspi1, ++ HAL_CAMCLK_SRC_CLK_miic0, ++ HAL_CAMCLK_SRC_CLK_miic1, ++ HAL_CAMCLK_SRC_CLK_bist, ++ HAL_CAMCLK_SRC_CLK_xtali, ++ HAL_CAMCLK_SRC_CLK_live, ++ HAL_CAMCLK_SRC_CLK_sr_mclk, ++ HAL_CAMCLK_SRC_CLK_sr_mclk1, ++ HAL_CAMCLK_SRC_CLK_bist_pm, ++ HAL_CAMCLK_SRC_CLK_pwr_ctl, ++ HAL_CAMCLK_SRC_CLK_ipu, ++ HAL_CAMCLK_SRC_CLK_bist_ipu_gp, ++ HAL_CAMCLK_SRC_CLK_miic2, ++ HAL_CAMCLK_SRC_CLK_miic3, ++ HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_0, ++ HAL_CAMCLK_SRC_CLK_csi_mac_top_i_0, ++ HAL_CAMCLK_SRC_CLK_csi_ns_top_i_0, ++ HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_1, ++ HAL_CAMCLK_SRC_CLK_csi_mac_top_i_1, ++ HAL_CAMCLK_SRC_CLK_csi_ns_top_i_1, ++ HAL_CAMCLK_SRC_CLK_bist_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_vhe, ++ HAL_CAMCLK_SRC_CLK_xtali_sc_gp, ++ HAL_CAMCLK_SRC_CLK_bist_sc_gp, ++ HAL_CAMCLK_SRC_CLK_emac_ahb, ++ HAL_CAMCLK_SRC_CLK_jpe, ++ HAL_CAMCLK_SRC_CLK_aesdma, ++ HAL_CAMCLK_SRC_CLK_sdio, ++ HAL_CAMCLK_SRC_CLK_fcie, ++ HAL_CAMCLK_SRC_CLK_ecc, ++ HAL_CAMCLK_SRC_CLK_sr, ++ HAL_CAMCLK_SRC_CLK_isp, ++ HAL_CAMCLK_SRC_CLK_idclk, ++ HAL_CAMCLK_SRC_CLK_fclk1, ++ HAL_CAMCLK_SRC_CLK_fclk2, ++ HAL_CAMCLK_SRC_CLK_odclk, ++ HAL_CAMCLK_SRC_CLK_ive, ++ HAL_CAMCLK_SRC_CLK_dip, ++ HAL_CAMCLK_SRC_CLK_emac_tx, ++ HAL_CAMCLK_SRC_CLK_emac_rx, ++ HAL_CAMCLK_SRC_CLK_emac_tx_ref, ++ HAL_CAMCLK_SRC_CLK_emac_rx_ref, ++ HAL_CAMCLK_SRC_CLK_hemcu_216m, ++ HAL_CAMCLK_SRC_CLK_csi_mac, ++ HAL_CAMCLK_SRC_CLK_mac_lptx, ++ HAL_CAMCLK_SRC_CLK_ns, ++ HAL_CAMCLK_SRC_CLK_mcu_pm, ++ HAL_CAMCLK_SRC_CLK_spi_pm, ++ HAL_CAMCLK_SRC_CLK_pm_sleep, ++ HAL_CAMCLK_SRC_CLK_sar, ++ HAL_CAMCLK_SRC_CLK_rtc, ++ HAL_CAMCLK_SRC_Id_MAX ++} HalCamClkSrcId_e; ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk.h b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk.h +new file mode 100644 +index 000000000000..dd27fd24a52d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk.h +@@ -0,0 +1,26 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_H__ ++#define __HAL_CAMCLK_H__ ++#include "drv_camclk_DataType.h" ++#include "hal_camclk_st.h" ++#include "hal_camclk_if_st.h" ++ ++const extern HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX]; ++extern HalCamClkTopClk_t *gCamClkTopCurrent; ++extern u16 gu16HandlerCnt; ++extern struct CamOsListHead_t gstClkListHead; ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_complex.h b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_complex.h +new file mode 100644 +index 000000000000..11146093fe57 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_complex.h +@@ -0,0 +1,23 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include "hal_camclk_if_st.h" ++extern HalCamClkAdjOps_t gMiupllOps; ++extern HalCamClkAdjOps_t gDdrpllOps; ++extern HalCamClkAdjOps_t gLpllOps; ++extern HalCamClkAdjOps_t gCpupllOps; ++extern HalCamClkAdjOps_t gIpupllOps; ++extern HalCamClkAdjOps_t gVenpllOps; ++extern HalCamClkAdjOps_t gFuart0Ops; ++extern HalCamClkAdjOps_t gCsi2Ops; +diff --git a/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_lpll_tbl.h b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_lpll_tbl.h +new file mode 100644 +index 000000000000..47f5bdc4b74f +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_lpll_tbl.h +@@ -0,0 +1,75 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_LPLL_TBL_H_ ++#define _CAMCLK_LPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define HAL_CAMCLK_LPLL_REG_NUM 6 ++ ++#define DATA_LANE_9MHZ (9000000) ++#define DATA_LANE_9_5MHZ (9500000) ++#define DATA_LANE_12_5MHZ (12500000) ++#define DATA_LANE_25MHZ (25000000) ++#define DATA_LANE_50MHZ (50000000) ++#define DATA_LANE_100MHZ (100000000) ++#define DATA_LANE_187_5MHZ (187500000) ++#define DATA_LANE_200MHZ (200000000) ++#define DATA_LANE_400MHZ (400000000) ++#define DATA_LANE_800MHZ (800000000) ++#define DATA_LANE_1500MHZ (1500000000) ++ ++#define IS_DATA_LANE_LESS_100M(bps) ( bps <= DATA_LANE_100MHZ ) ++#define IS_DATA_LANE_BPS_100M_TO_200M(bps) ( (bps > DATA_LANE_100MHZ) && (bps <= DATA_LANE_200MHZ ) ) ++#define IS_DATA_LANE_BPS_200M_TO_400M(bps) ( (bps > DATA_LANE_200MHZ) && (bps <= DATA_LANE_400MHZ ) ) ++#define IS_DATA_LANE_BPS_400M_TO_800M(bps) ( (bps > DATA_LANE_400MHZ) && (bps <= DATA_LANE_800MHZ ) ) ++#define IS_DATA_LANE_BPS_800M_TO_15000M(bps) ( (bps > DATA_LANE_800MHZ) && (bps <= DATA_LANE_1500MHZ ) ) ++ ++#define IS_DATA_LANE_LESS_9M(bps) ( bps < DATA_LANE_9MHZ ) ++#define IS_DATA_LANE_BPS_9M_TO_9_5M(bps) ( (bps >= DATA_LANE_9MHZ) && (bps < DATA_LANE_9_5MHZ ) ) ++#define IS_DATA_LANE_BPS_12_5M_TO_25M(bps) ( (bps > DATA_LANE_12_5MHZ) && (bps <= DATA_LANE_25MHZ ) ) ++#define IS_DATA_LANE_BPS_25M_TO_50M(bps) ( (bps > DATA_LANE_25MHZ) && (bps <= DATA_LANE_50MHZ ) ) ++#define IS_DATA_LANE_BPS_50M_TO_100M(bps) ( (bps > DATA_LANE_50MHZ) && (bps <= DATA_LANE_100MHZ ) ) ++#define REG_LPLL_BASE 0x103300UL ++#define REG_LPLL_48_L (REG_LPLL_BASE + 0x90) ++#define REG_LPLL_48_H (REG_LPLL_BASE + 0x91) ++#define REG_LPLL_49_L (REG_LPLL_BASE + 0x92) ++#define REG_LPLL_49_H (REG_LPLL_BASE + 0x93) ++ ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ, //0 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ, //1 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ, //2 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ, //3 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_MAX, //4 ++} HalCamClkLpllType_e; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 address; ++ u16 value; ++}HalCamClkLpllTbl_t; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_st.h b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_st.h +new file mode 100644 +index 000000000000..ca2c85a0aeb5 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_st.h +@@ -0,0 +1,38 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_ST_H__ ++#define __HAL_CAMCLK_ST_H__ ++ ++ ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkSetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkGetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32RoundRate; ++}HalCamClkGetComplexRoundRate_t; ++typedef struct ++{ ++ u8 bEn; ++}HalCamClkComplexOnOff_t; ++#endif /* MHAL_DIP_H */ +diff --git a/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_venpll.h b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_venpll.h +new file mode 100644 +index 000000000000..8b645f759b16 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/inc/hal_camclk_venpll.h +@@ -0,0 +1,35 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_VENPLL_TBL_H_ ++#define _CAMCLK_VENPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define REG_VENPLL_BASE 0x103600UL ++#define REG_VENPLL_00_L (REG_VENPLL_BASE + 0x00) ++#define REG_VENPLL_01_L (REG_VENPLL_BASE + 0x02) ++#define REG_VENPLL_03_L (REG_VENPLL_BASE + 0x06) ++#define REG_VENPLL_04_L (REG_VENPLL_BASE + 0x08) ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++#endif //_CAMCLK_VENPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity5/pub/camclk.h b/drivers/sstar/camclk/hal/infinity5/pub/camclk.h +new file mode 100644 +index 000000000000..1028447a4b63 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/pub/camclk.h +@@ -0,0 +1,210 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_mpll_432m 1 ++#define CAMCLK_upll_384m 2 ++#define CAMCLK_upll_320m 3 ++#define CAMCLK_mpll_288m 4 ++#define CAMCLK_utmi_240m 5 ++#define CAMCLK_mpll_216m 6 ++#define CAMCLK_utmi_192m 7 ++#define CAMCLK_mpll_172m 8 ++#define CAMCLK_utmi_160m 9 ++#define CAMCLK_mpll_123m 10 ++#define CAMCLK_mpll_86m 11 ++#define CAMCLK_mpll_288m_div2 12 ++#define CAMCLK_mpll_288m_div4 13 ++#define CAMCLK_mpll_288m_div8 14 ++#define CAMCLK_mpll_216m_div2 15 ++#define CAMCLK_mpll_216m_div4 16 ++#define CAMCLK_mpll_216m_div8 17 ++#define CAMCLK_mpll_123m_div2 18 ++#define CAMCLK_mpll_86m_div2 19 ++#define CAMCLK_mpll_86m_div4 20 ++#define CAMCLK_mpll_86m_div16 21 ++#define CAMCLK_utmi_192m_div4 22 ++#define CAMCLK_utmi_160m_div4 23 ++#define CAMCLK_utmi_160m_div5 24 ++#define CAMCLK_utmi_160m_div8 25 ++#define CAMCLK_xtali_12m 26 ++#define CAMCLK_xtali_12m_div8 27 ++#define CAMCLK_xtali_12m_div16 28 ++#define CAMCLK_xtali_12m_div40 29 ++#define CAMCLK_xtali_12m_div64 30 ++#define CAMCLK_xtali_12m_div128 31 ++#define CAMCLK_RTC_CLK_32K 32 ++#define CAMCLK_pm_riu_w_clk_in 33 ++#define CAMCLK_riu_w_clk_in 34 ++#define CAMCLK_riu_w_clk_top 35 ++#define CAMCLK_riu_w_clk_sc_gp 36 ++#define CAMCLK_riu_w_clk_vhe_gp 37 ++#define CAMCLK_riu_w_clk_hemcu_gp 38 ++#define CAMCLK_riu_w_clk_mipi_if_gp 39 ++#define CAMCLK_riu_w_clk_mcu_if_gp 40 ++#define CAMCLK_miu_p 41 ++#define CAMCLK_miu_vhe_gp_p 42 ++#define CAMCLK_miu_sc_gp_p 43 ++#define CAMCLK_miu2x_p 44 ++#define CAMCLK_mcu_p 45 ++#define CAMCLK_mcu_pm_p 46 ++#define CAMCLK_isp_p 47 ++#define CAMCLK_fclk1_p 48 ++#define CAMCLK_fclk2_p 49 ++#define CAMCLK_sdio_p 50 ++#define CAMCLK_fcie_p 51 ++#define CAMCLK_tck_buf 52 ++#define CAMCLK_pad2isp_sr_pclk 53 ++#define CAMCLK_ccir_in_clk 54 ++#define CAMCLK_eth_buf 55 ++#define CAMCLK_rmii_buf 56 ++#define CAMCLK_emac_testrx125_in_lan 57 ++#define CAMCLK_miu_ff 58 ++#define CAMCLK_miu_sc_gp 59 ++#define CAMCLK_miu_vhe_gp 60 ++#define CAMCLK_miu_dig 61 ++#define CAMCLK_miu_xd2miu 62 ++#define CAMCLK_miu_urdma 63 ++#define CAMCLK_miu_bdma 64 ++#define CAMCLK_miu_vhe 65 ++#define CAMCLK_miu_jpe1 66 ++#define CAMCLK_miu_jpe0 67 ++#define CAMCLK_miu_bach 68 ++#define CAMCLK_miu_file 69 ++#define CAMCLK_miu_uhc0 70 ++#define CAMCLK_miu_emac 71 ++#define CAMCLK_miu_cmdq 72 ++#define CAMCLK_miu_isp_dnr 73 ++#define CAMCLK_miu_isp_rot 74 ++#define CAMCLK_miu_isp_dma 75 ++#define CAMCLK_miu_isp_sta 76 ++#define CAMCLK_miu_gop 77 ++#define CAMCLK_miu_sc_dnr 78 ++#define CAMCLK_miu_sc_dnr_sad 79 ++#define CAMCLK_miu_sc_crop 80 ++#define CAMCLK_miu_sc1_frm 81 ++#define CAMCLK_miu_sc1_snp 82 ++#define CAMCLK_miu_sc1_snpi 83 ++#define CAMCLK_miu_sc1_dbg 84 ++#define CAMCLK_miu_sc2_frm 85 ++#define CAMCLK_miu_sc2_snpi 86 ++#define CAMCLK_miu_sc3_frm 87 ++#define CAMCLK_miu_fcie 88 ++#define CAMCLK_miu_sdio 89 ++#define CAMCLK_miu_ive 90 ++#define CAMCLK_riu 91 ++#define CAMCLK_riu_nogating 92 ++#define CAMCLK_riu_sc_gp 93 ++#define CAMCLK_riu_vhe_gp 94 ++#define CAMCLK_riu_hemcu_gp 95 ++#define CAMCLK_riu_mipi_gp 96 ++#define CAMCLK_riu_mcu_if 97 ++#define CAMCLK_miu2x 98 ++#define CAMCLK_axi2x 99 ++#define CAMCLK_tck 100 ++#define CAMCLK_imi 101 ++#define CAMCLK_gop0 102 ++#define CAMCLK_gop1 103 ++#define CAMCLK_gop2 104 ++#define CAMCLK_mpll_144m 105 ++#define CAMCLK_mpll_144m_div2 106 ++#define CAMCLK_mpll_144m_div4 107 ++#define CAMCLK_xtali_24m 108 ++#define CAMCLK_xtali_12m_div2 109 ++#define CAMCLK_xtali_12m_div4 110 ++#define CAMCLK_xtali_12m_div12 111 ++#define CAMCLK_rtc_32k 112 ++#define CAMCLK_rtc_32k_div4 113 ++#define CAMCLK_live_pm 114 ++#define CAMCLK_riu_pm 115 ++#define CAMCLK_miupll_clk 116 ++#define CAMCLK_ddrpll_clk 117 ++#define CAMCLK_lpll_clk 118 ++#define CAMCLK_lpll_clk_div2 119 ++#define CAMCLK_lpll_clk_div4 120 ++#define CAMCLK_lpll_clk_div8 121 ++#define CAMCLK_cpupll_clk 122 ++#define CAMCLK_ipupll_clk 123 ++#define CAMCLK_venpll_clk 124 ++#define CAMCLK_utmi 125 ++#define CAMCLK_upll 126 ++#define CAMCLK_fuart0_synth_out 127 ++#define CAMCLK_csi2_mac_p 128 ++#define CAMCLK_miu 129 ++#define CAMCLK_ddr_syn 130 ++#define CAMCLK_miu_rec 131 ++#define CAMCLK_mcu 132 ++#define CAMCLK_riubrdg 133 ++#define CAMCLK_bdma 134 ++#define CAMCLK_spi 135 ++#define CAMCLK_uart0 136 ++#define CAMCLK_uart1 137 ++#define CAMCLK_fuart0_synth_in 138 ++#define CAMCLK_fuart 139 ++#define CAMCLK_mspi0 140 ++#define CAMCLK_mspi1 141 ++#define CAMCLK_miic0 142 ++#define CAMCLK_miic1 143 ++#define CAMCLK_bist 144 ++#define CAMCLK_xtali 145 ++#define CAMCLK_live 146 ++#define CAMCLK_sr_mclk 147 ++#define CAMCLK_sr_mclk1 148 ++#define CAMCLK_bist_pm 149 ++#define CAMCLK_pwr_ctl 150 ++#define CAMCLK_ipu 151 ++#define CAMCLK_bist_ipu_gp 152 ++#define CAMCLK_miic2 153 ++#define CAMCLK_miic3 154 ++#define CAMCLK_csi_mac_lptx_top_i_0 155 ++#define CAMCLK_csi_mac_top_i_0 156 ++#define CAMCLK_csi_ns_top_i_0 157 ++#define CAMCLK_csi_mac_lptx_top_i_1 158 ++#define CAMCLK_csi_mac_top_i_1 159 ++#define CAMCLK_csi_ns_top_i_1 160 ++#define CAMCLK_bist_vhe_gp 161 ++#define CAMCLK_vhe 162 ++#define CAMCLK_xtali_sc_gp 163 ++#define CAMCLK_bist_sc_gp 164 ++#define CAMCLK_emac_ahb 165 ++#define CAMCLK_jpe 166 ++#define CAMCLK_aesdma 167 ++#define CAMCLK_sdio 168 ++#define CAMCLK_fcie 169 ++#define CAMCLK_ecc 170 ++#define CAMCLK_sr 171 ++#define CAMCLK_isp 172 ++#define CAMCLK_idclk 173 ++#define CAMCLK_fclk1 174 ++#define CAMCLK_fclk2 175 ++#define CAMCLK_odclk 176 ++#define CAMCLK_ive 177 ++#define CAMCLK_dip 178 ++#define CAMCLK_emac_tx 179 ++#define CAMCLK_emac_rx 180 ++#define CAMCLK_emac_tx_ref 181 ++#define CAMCLK_emac_rx_ref 182 ++#define CAMCLK_hemcu_216m 183 ++#define CAMCLK_csi_mac 184 ++#define CAMCLK_mac_lptx 185 ++#define CAMCLK_ns 186 ++#define CAMCLK_mcu_pm 187 ++#define CAMCLK_spi_pm 188 ++#define CAMCLK_pm_sleep 189 ++#define CAMCLK_sar 190 ++#define CAMCLK_rtc 191 ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity5/pub/reg_clks.h b/drivers/sstar/camclk/hal/infinity5/pub/reg_clks.h +new file mode 100644 +index 000000000000..0be1b7bb1db9 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/pub/reg_clks.h +@@ -0,0 +1,488 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_OFFSET (10) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BIST_IPU_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_IPU_GP_OFFSET (12) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP0_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP0_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP1_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP1_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_TOP0_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_CSI_MAC_TOP0_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_TOP1_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_CSI_MAC_TOP1_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCIE_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_FCIE_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_ISPSC_LDC_FEYE_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_IPU_BASE (REG_CKG_BASE+0x50*4) ++#define REG_CKG_IPU_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIIC2_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_MIIC2_OFFSET (0) ++ ++#define REG_CKG_MIIC3_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_MIIC3_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_NS_TOP0_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_NS_TOP0_OFFSET (0) ++ ++#define REG_CKG_NS_TOP1_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_NS_TOP1_OFFSET (8) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_SR_MCLK1_BASE (REG_CKG_BASE+0x56*4) ++#define REG_CKG_SR_MCLK1_OFFSET (0) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity5/src/hal_camclk_complex.c b/drivers/sstar/camclk/hal/infinity5/src/hal_camclk_complex.c +new file mode 100644 +index 000000000000..5ffd77fcc808 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/src/hal_camclk_complex.c +@@ -0,0 +1,520 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_LPLL_C ++#include "camclk_dbg.h" ++#include "hal_camclk_if_st.h" ++#include "hal_camclk_lpll_tbl.h" ++#include "hal_camclk_venpll.h" ++#include "hal_camclk_util.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "registers.h" ++#include "ms_platform.h" ++ ++ ++HalCamClkLpllTbl_t gCamClkLPLLSettingTBL[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX][HAL_CAMCLK_LPLL_REG_NUM]= ++{ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0041}, ++ {0x103386, 0x0000}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0042}, ++ {0x103386, 0x0001}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0043}, ++ {0x103386, 0x0002}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0083}, ++ {0x103386, 0x0003}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++}; ++#define PLL_REG_GET(address) (0x1F000000 + ((address)<<1)) ++u16 u16LoopGain[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX]= ++{ ++ 16, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ 8, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ 4, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ 2, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++}; ++u32 u16gLpllDiv = 8; ++u8 bLook = 0; ++void HalCamClkGetLpllIdxFromHw(u16 *pu16Idx) ++{ ++ u16 u16Val; ++ u8 idx; ++ u16Val = R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][2].address)); ++ for(idx =0 ;idx> 16); ++ W2BYTE(PLL_REG_GET(REG_LPLL_48_L), u16LpllSet_Lo); // @suppress("Symbol is not resolved") ++ W2BYTE(PLL_REG_GET(REG_LPLL_49_L), u16LpllSet_Hi); // @suppress("Symbol is not resolved") ++} ++void HalCamClkGetLpllSet(u32 *u32LpllSet) ++{ ++ u16 u16LpllSet_Lo, u16LpllSet_Hi; ++ ++ u16LpllSet_Lo = R2BYTE(PLL_REG_GET(REG_LPLL_48_L)); ++ u16LpllSet_Hi = R2BYTE(PLL_REG_GET(REG_LPLL_49_L)); ++ *u32LpllSet = (u16LpllSet_Lo | ((u32)u16LpllSet_Hi<<16)); ++} ++CAMCLK_RET_e HalCamClkSetLpllRate(void *pCfg) ++{ ++ u16 u16LpllIdx; ++ u16 u16Div; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ HalCamClkSetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ if(bLook) ++ { ++ Ret = CAMCLK_RET_FAIL; ++ CAMCLKERR("%s %d, LPLL Locked:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ else ++ { ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate, &u16LpllIdx, &u16Div)) ++ { ++ if(u16LpllIdx != E_HAL_CAMCLK_SUPPORTED_LPLL_MAX) ++ { ++ u16LoopGain = HalCamClkGetLpllGain(u16LpllIdx); ++ u64Dividen = (pLpllCfg->u32ParentRate); ++ u64Dividen = (u64)(u64Dividen * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16Div,NULL); ++ u32Divisor = pLpllCfg->u32Rate; ++ u32LplLSet = (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ CAMCLKDBG("[CAMCLK]%s %d:: Idx:%d, LoopGain:%d, LoopDiv:%d, dclk=%ld, Divden:0x%llx, Divisor:0x%lx, LpllSe:0x%lx\n", ++ __FUNCTION__, __LINE__, u16LpllIdx, ++ u16LoopGain, u16Div, pLpllCfg->u32Rate, ++ u64Dividen, u32Divisor, u32LplLSet); ++ ++ HalCamClkDumpLpllSetting(u16LpllIdx); ++ HalCamClkSetLpllSet(u32LplLSet); ++ u16gLpllDiv = u16Div; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u16 u16idx; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ ++ HalCamClkGetLpllIdxFromHw(&u16idx); ++ u16LoopGain = HalCamClkGetLpllGain(u16idx); ++ HalCamClkGetLpllSet(&u32LplLSet); ++ u64Dividen = pLpllCfg->u32ParentRate; ++ u64Dividen = (u64)((u64Dividen) * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16gLpllDiv,NULL); ++ u32Divisor = u32LplLSet; ++ pLpllCfg->u32Rate= (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pLpllCfg = pCfg; ++ u16 u16Temp; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate,&u16Temp,&u16Temp)) ++ { ++ pLpllCfg->u32RoundRate = pLpllCfg->u32Rate; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ if(pLpllCfg->u32Rateu32RoundRate = DATA_LANE_12_5MHZ; ++ } ++ else ++ { ++ pLpllCfg->u32RoundRate = DATA_LANE_1500MHZ; ++ } ++ } ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pLpllCfg->bEn = (R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address))&camclk_BIT13)>>13; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address), pLpllCfg->bEn ? camclk_BIT13 : 0 , camclk_BIT13); ++ bLook = pLpllCfg->bEn; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetVenpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_01_L), pVenpllCfg->bEn ? 0 : camclk_BIT8 , camclk_BIT8); ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetVenpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pVenpllCfg->bEn = (R2BYTE(PLL_REG_GET(REG_VENPLL_01_L))&camclk_BIT8) ? 0 : 1; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetVenpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pVenpllCfg->u32Rate = pVenpllCfg->u32ParentRate * RBYTE(PLL_REG_GET(REG_VENPLL_03_L)) / 2; ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetVenpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pVenpllCfg->u32Rate <= 504000000) ++ { ++ pVenpllCfg->u32RoundRate = 504000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 528000000) ++ { ++ pVenpllCfg->u32RoundRate = 528000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 552000000) ++ { ++ pVenpllCfg->u32RoundRate = 552000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 576000000) ++ { ++ pVenpllCfg->u32RoundRate = 576000000; ++ } ++ else{ ++ pVenpllCfg->u32RoundRate = 600000000; ++ } ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetVenpllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u32 val; ++ ++ if ( (pVenpllCfg->u32Rate == 504000000) || ++ (pVenpllCfg->u32Rate == 528000000) || ++ (pVenpllCfg->u32Rate == 552000000) || ++ (pVenpllCfg->u32Rate == 576000000) || ++ (pVenpllCfg->u32Rate == 300000000)) ++ { ++ val = pVenpllCfg->u32Rate * 2 / 24000000; ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_03_L), val , 0xFF); ++ } ++ else if((pVenpllCfg->u32Rate == 600000000)) ++ { ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_03_L), 0x32 , 0xFF); ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_00_L), 0x10 , 0xFFFF); ++ // [0]: reg_ven_pll_test_en = 1'b1 ++ // [6:4]: reg_ven_pll_icp_ictrl = 3'b001 (default) ++ // Ibias current control ++ // 000 for 0.83uA, ++ // 001 for 1.66uA, ++ // 011 for 2.5uA, ++ // 111 for 3.32uA ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_04_L), 0x11 , 0xFF); ++ } ++ else ++ { ++ CAMCLKERR("\nunsupported venpll rate %lu\n\n", pVenpllCfg->u32Rate); ++ Ret = CAMCLK_RET_RATEERR; ++ } ++ return Ret; ++} ++ ++static void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++CAMCLK_RET_e HalCamClkSetCpupllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pCpupllCfg = pCfg; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //CamOsPrintf("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (pCpupllCfg->u32Rate >= 800000000) ++ post_div = 2; ++ else if (pCpupllCfg->u32Rate >= 400000000) ++ post_div = 4; ++ else if (pCpupllCfg->u32Rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, (pCpupllCfg->u32Rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pCpupllCfg = pCfg; ++ u32 lpf_value; ++ u32 post_div; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ //CamOsPrintf("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ pCpupllCfg->u32Rate = (div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ //CamOsPrintf("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", pCpupllCfg->u32Rate, pCpupllCfg->u32ParentRate); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pCpupllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pCpupllCfg->u32Rate < 100000000) // 100MHz ++ { ++ pCpupllCfg->u32RoundRate = 100000000; ++ } ++ else if(pCpupllCfg->u32Rate > 1400000000) // 1.4GHz ++ { ++ pCpupllCfg->u32RoundRate = 1400000000; ++ } ++ else ++ { ++ pCpupllCfg->u32RoundRate = pCpupllCfg->u32Rate; ++ } ++ ++ return Ret; ++} ++HalCamClkAdjOps_t gLpllOps={0,0,HalCamClkSetLpllRate,HalCamClkGetLpllRate,HalCamClkGetLpllRoundRate,HalCamClkSetLpllOnOff,HalCamClkGetLpllOnOff}; ++HalCamClkAdjOps_t gDdrpllOps={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gCpupllOps={0,0,HalCamClkSetCpupllRate,HalCamClkGetCpupllRate,HalCamClkGetCpupllRoundRate,0,0}; ++HalCamClkAdjOps_t gFuart0Ops={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gCsi2Ops={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gMiupllOps={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gIpupllOps={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gVenpllOps={0,0,HalCamClkSetVenpllRate,HalCamClkGetVenpllRate,HalCamClkGetVenpllRoundRate,HalCamClkSetVenpllOnOff,HalCamClkGetVenpllOnOff}; ++#undef HAL_CAMCLKTBL_LPLL_C +diff --git a/drivers/sstar/camclk/hal/infinity5/src/hal_camclk_tbl.c b/drivers/sstar/camclk/hal/infinity5/src/hal_camclk_tbl.c +new file mode 100644 +index 000000000000..cd00fd0ef35e +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity5/src/hal_camclk_tbl.c +@@ -0,0 +1,217 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_C ++#include "hal_camclk_if.h" ++#include "hal_camclk_complex.h" ++#include "reg_clks.h" ++#include "hal_camclk_util.h" ++ ++const HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX] = ++{ ++ {HAL_CAMCLK_SRC_CLK_VOID, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_432m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll_384m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,5,4}}, ++ {HAL_CAMCLK_SRC_CLK_upll_320m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,3,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={288000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_240m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={216000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,5,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_172m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={172000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,3,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={123000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={86000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_123m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_192m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div5, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,5,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={12000000}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div40, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,40,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div64, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,64,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div128, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,128,1}}, ++ {HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_top, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_vhe_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu_pm,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_isp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_isp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk2_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk2,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_sdio_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_sdio,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fcie_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fcie,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_ccir_in_clk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_eth_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_rmii_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ff, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_dig, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_xd2miu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_urdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_bdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_jpe1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_jpe0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_bach, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_file, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_uhc0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_emac, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_cmdq, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_dnr, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_rot, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_dma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_sta, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_gop, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_dnr, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_dnr_sad, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_crop, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_snp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_snpi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_dbg, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc2_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc2_snpi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc3_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_fcie, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sdio, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ive, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_top,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_nogating, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mipi_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mcu_if, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_ddrpll_clk,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_axi2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_tck_buf,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_imi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk2_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={144000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_24m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={24000000}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div12, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,12,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_rtc_32k,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_live_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_24m,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m,&gMiupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_ddrpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_ddr_syn,&gDdrpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gLpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_cpupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gCpupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_ipupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gIpupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_venpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m,&gVenpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_utmi, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_out, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_fuart0_synth_in,&gFuart0Ops}}, ++ {HAL_CAMCLK_SRC_CLK_csi2_mac_p, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_csi_mac,&gCsi2Ops}}, ++ {HAL_CAMCLK_SRC_CLK_miu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_miupll_clk,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ddr_syn, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DDR_SYN_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_rec, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div64,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div128},REG_CKG_MIU_REC_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_MCU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_riubrdg, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mcu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RIUBRDG_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_bdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_BDMA_BASE,camclk_BIT0,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_spi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4},REG_CKG_SPI_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_uart0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_in, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FUART0_SYNTH_IN_BASE,camclk_BIT4,0,2,6,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fuart0_synth_out},REG_CKG_FUART_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MSPI0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MSPI1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_live, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_sr_mclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div8,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SR_MCLK_BASE,camclk_BIT8,0,4,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_sr_mclk1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div8,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SR_MCLK1_BASE,camclk_BIT0,0,4,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_PM_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_pwr_ctl, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PWR_CTL_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ipu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_ipupll_clk,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_IPU_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_ipu_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_IPU_GP_BASE,camclk_BIT12,0,2,14,1}}, ++ {HAL_CAMCLK_SRC_CLK_miic2, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC2_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic3, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC3_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_LPTX_TOP0_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_top_i_0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_TOP0_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_ns_top_i_0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_TOP0_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_LPTX_TOP1_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_top_i_1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_TOP1_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_ns_top_i_1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_TOP1_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_vhe_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_VHE_GP_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_vhe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_venpll_clk,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_VHE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_SC_GP_BASE,camclk_BIT4,0,2,6,1}}, ++ {HAL_CAMCLK_SRC_CLK_bist_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_SC_GP_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_ahb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan},REG_CKG_EMAC_AHB_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_jpe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8},REG_CKG_JPE_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_aesdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_AESDMA_BASE,camclk_BIT0,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sdio, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SDIO_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_fcie, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FCIE_BASE,camclk_BIT0,camclk_BIT6,4,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ecc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_ECC_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sr, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk,(u8)HAL_CAMCLK_SRC_CLK_csi2_mac_p,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m},REG_CKG_SR_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_isp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_ISP_BASE,camclk_BIT8,0,4,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_idclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_isp_p,(u8)HAL_CAMCLK_SRC_CLK_ccir_in_clk,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_IDCLK_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m},REG_CKG_FCLK1_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk2, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m},REG_CKG_ISPSC_LDC_FEYE_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_odclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk},REG_CKG_ODCLK_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ive, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_IVE_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_dip, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DIP_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_TX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_RX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_TX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_RX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_hemcu_216m, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_HEMCU_216M_BASE,camclk_BIT0,0,0,0,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mac_lptx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MAC_LPTX_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ns, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_MCU_PM_BASE,camclk_BIT0,camclk_BIT7,4,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m},REG_CKG_SPI_PM_BASE,camclk_BIT8,camclk_BIT15,4,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_pm_sleep, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_PM_SLEEP_BASE,0,0,3,12,1}}, ++ {HAL_CAMCLK_SRC_CLK_sar, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_SAR_BASE,camclk_BIT5,0,3,7,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RTC_BASE,camclk_BIT0,0,3,2,1}}, ++}; ++ ++#undef HAL_CAMCLKTBL_C +diff --git a/drivers/sstar/camclk/hal/infinity6/camclk_hal.mak b/drivers/sstar/camclk/hal/infinity6/camclk_hal.mak +new file mode 100644 +index 000000000000..64e6264a364d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/camclk_hal.mak +@@ -0,0 +1,20 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++ ++PATH_C += \ ++ $(PATH_camclk_hal)/src ++ ++PATH_H += $(PATH_camclk_hal)/common\ ++ $(PATH_camclk_hal)/inc\ ++ $(PATH_camclk_hal)/pub\ ++ $(PATH_camclk)/inc\ ++ $(PATH_camclk)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_cam_os_wrapper)/inc\ ++ ++SRC_C_LIST += hal_camclk_complex.c\ ++ hal_camclk_tbl.c ++ +diff --git a/drivers/sstar/camclk/hal/infinity6/inc/camclk_id.h b/drivers/sstar/camclk/hal/infinity6/inc/camclk_id.h +new file mode 100644 +index 000000000000..d481be434556 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/inc/camclk_id.h +@@ -0,0 +1,204 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_ID_H__ ++#define __CAMCLK_ID_H__ ++typedef enum ++{ ++ HAL_CAMCLK_SRC_CLK_VOID, ++ HAL_CAMCLK_SRC_CLK_utmi_480m, ++ HAL_CAMCLK_SRC_CLK_mpll_432m, ++ HAL_CAMCLK_SRC_CLK_upll_384m, ++ HAL_CAMCLK_SRC_CLK_upll_320m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m, ++ HAL_CAMCLK_SRC_CLK_utmi_240m, ++ HAL_CAMCLK_SRC_CLK_mpll_216m, ++ HAL_CAMCLK_SRC_CLK_utmi_192m, ++ HAL_CAMCLK_SRC_CLK_mpll_172m, ++ HAL_CAMCLK_SRC_CLK_utmi_160m, ++ HAL_CAMCLK_SRC_CLK_mpll_123m, ++ HAL_CAMCLK_SRC_CLK_mpll_86m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_123m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div16, ++ HAL_CAMCLK_SRC_CLK_utmi_192m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div5, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div16, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div40, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div64, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div128, ++ HAL_CAMCLK_SRC_CLK_xtali_24m, ++ HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, ++ HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div2, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div4, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div8, ++ HAL_CAMCLK_SRC_CLK_armpll_37p125m, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_top, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, ++ HAL_CAMCLK_SRC_CLK_miu_p, ++ HAL_CAMCLK_SRC_CLK_mspi0_p, ++ HAL_CAMCLK_SRC_CLK_mspi1_p, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu2x_p, ++ HAL_CAMCLK_SRC_CLK_mcu_p, ++ HAL_CAMCLK_SRC_CLK_mcu_pm_p, ++ HAL_CAMCLK_SRC_CLK_isp_p, ++ HAL_CAMCLK_SRC_CLK_fclk1_p, ++ HAL_CAMCLK_SRC_CLK_fclk2_p, ++ HAL_CAMCLK_SRC_CLK_sdio_p, ++ HAL_CAMCLK_SRC_CLK_tck_buf, ++ HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, ++ HAL_CAMCLK_SRC_CLK_ccir_in_clk, ++ HAL_CAMCLK_SRC_CLK_eth_buf, ++ HAL_CAMCLK_SRC_CLK_rmii_buf, ++ HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, ++ HAL_CAMCLK_SRC_CLK_miu_ff, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_miu_dig, ++ HAL_CAMCLK_SRC_CLK_miu_xd2miu, ++ HAL_CAMCLK_SRC_CLK_miu_urdma, ++ HAL_CAMCLK_SRC_CLK_miu_bdma, ++ HAL_CAMCLK_SRC_CLK_miu_vhe, ++ HAL_CAMCLK_SRC_CLK_miu_mfeh, ++ HAL_CAMCLK_SRC_CLK_miu_mfe, ++ HAL_CAMCLK_SRC_CLK_miu_jpe1, ++ HAL_CAMCLK_SRC_CLK_miu_jpe0, ++ HAL_CAMCLK_SRC_CLK_miu_bach, ++ HAL_CAMCLK_SRC_CLK_miu_file, ++ HAL_CAMCLK_SRC_CLK_miu_uhc0, ++ HAL_CAMCLK_SRC_CLK_miu_emac, ++ HAL_CAMCLK_SRC_CLK_miu_cmdq, ++ HAL_CAMCLK_SRC_CLK_miu_isp_dnr, ++ HAL_CAMCLK_SRC_CLK_miu_isp_rot, ++ HAL_CAMCLK_SRC_CLK_miu_isp_dma, ++ HAL_CAMCLK_SRC_CLK_miu_isp_sta, ++ HAL_CAMCLK_SRC_CLK_miu_gop, ++ HAL_CAMCLK_SRC_CLK_miu_sc_dnr, ++ HAL_CAMCLK_SRC_CLK_miu_sc_dnr_sad, ++ HAL_CAMCLK_SRC_CLK_miu_sc_crop, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_frm, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_snp, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_snpi, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_dbg, ++ HAL_CAMCLK_SRC_CLK_miu_sc2_frm, ++ HAL_CAMCLK_SRC_CLK_miu_sc2_snpi, ++ HAL_CAMCLK_SRC_CLK_miu_sc3_frm, ++ HAL_CAMCLK_SRC_CLK_miu_fcie, ++ HAL_CAMCLK_SRC_CLK_miu_sdio, ++ HAL_CAMCLK_SRC_CLK_miu_ive, ++ HAL_CAMCLK_SRC_CLK_riu, ++ HAL_CAMCLK_SRC_CLK_riu_nogating, ++ HAL_CAMCLK_SRC_CLK_riu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mipi_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mcu_if, ++ HAL_CAMCLK_SRC_CLK_miu2x, ++ HAL_CAMCLK_SRC_CLK_axi2x, ++ HAL_CAMCLK_SRC_CLK_tck, ++ HAL_CAMCLK_SRC_CLK_imi, ++ HAL_CAMCLK_SRC_CLK_gop0, ++ HAL_CAMCLK_SRC_CLK_gop1, ++ HAL_CAMCLK_SRC_CLK_gop2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div2, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div12, ++ HAL_CAMCLK_SRC_CLK_rtc_32k, ++ HAL_CAMCLK_SRC_CLK_rtc_32k_div4, ++ HAL_CAMCLK_SRC_CLK_live_pm, ++ HAL_CAMCLK_SRC_CLK_riu_pm, ++ HAL_CAMCLK_SRC_CLK_miupll_clk, ++ HAL_CAMCLK_SRC_CLK_ddrpll_clk, ++ HAL_CAMCLK_SRC_CLK_lpll_clk, ++ HAL_CAMCLK_SRC_CLK_cpupll_clk, ++ HAL_CAMCLK_SRC_CLK_utmi, ++ HAL_CAMCLK_SRC_CLK_upll, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_out, ++ HAL_CAMCLK_SRC_CLK_csi2_mac_p, ++ HAL_CAMCLK_SRC_CLK_miu, ++ HAL_CAMCLK_SRC_CLK_ddr_syn, ++ HAL_CAMCLK_SRC_CLK_miu_rec, ++ HAL_CAMCLK_SRC_CLK_mcu, ++ HAL_CAMCLK_SRC_CLK_riubrdg, ++ HAL_CAMCLK_SRC_CLK_bdma, ++ HAL_CAMCLK_SRC_CLK_spi, ++ HAL_CAMCLK_SRC_CLK_uart0, ++ HAL_CAMCLK_SRC_CLK_uart1, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_in, ++ HAL_CAMCLK_SRC_CLK_fuart, ++ HAL_CAMCLK_SRC_CLK_mspi0, ++ HAL_CAMCLK_SRC_CLK_mspi1, ++ HAL_CAMCLK_SRC_CLK_mspi, ++ HAL_CAMCLK_SRC_CLK_miic0, ++ HAL_CAMCLK_SRC_CLK_miic1, ++ HAL_CAMCLK_SRC_CLK_bist, ++ HAL_CAMCLK_SRC_CLK_pwr_ctl, ++ HAL_CAMCLK_SRC_CLK_xtali, ++ HAL_CAMCLK_SRC_CLK_live, ++ HAL_CAMCLK_SRC_CLK_sr_mclk, ++ HAL_CAMCLK_SRC_CLK_bist_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_vhe, ++ HAL_CAMCLK_SRC_CLK_mfe, ++ HAL_CAMCLK_SRC_CLK_xtali_sc_gp, ++ HAL_CAMCLK_SRC_CLK_bist_sc_gp, ++ HAL_CAMCLK_SRC_CLK_emac_ahb, ++ HAL_CAMCLK_SRC_CLK_jpe, ++ HAL_CAMCLK_SRC_CLK_aesdma, ++ HAL_CAMCLK_SRC_CLK_sdio, ++ HAL_CAMCLK_SRC_CLK_sd, ++ HAL_CAMCLK_SRC_CLK_isp, ++ HAL_CAMCLK_SRC_CLK_fclk1, ++ HAL_CAMCLK_SRC_CLK_fclk2, ++ HAL_CAMCLK_SRC_CLK_odclk, ++ HAL_CAMCLK_SRC_CLK_dip, ++ HAL_CAMCLK_SRC_CLK_nlm, ++ HAL_CAMCLK_SRC_CLK_emac_tx, ++ HAL_CAMCLK_SRC_CLK_emac_rx, ++ HAL_CAMCLK_SRC_CLK_emac_tx_ref, ++ HAL_CAMCLK_SRC_CLK_emac_rx_ref, ++ HAL_CAMCLK_SRC_CLK_hemcu_216m, ++ HAL_CAMCLK_SRC_CLK_csi_mac, ++ HAL_CAMCLK_SRC_CLK_mac_lptx, ++ HAL_CAMCLK_SRC_CLK_ns, ++ HAL_CAMCLK_SRC_CLK_mcu_pm, ++ HAL_CAMCLK_SRC_CLK_spi_pm, ++ HAL_CAMCLK_SRC_CLK_pm_sleep, ++ HAL_CAMCLK_SRC_CLK_sar, ++ HAL_CAMCLK_SRC_CLK_rtc, ++ HAL_CAMCLK_SRC_CLK_ir, ++ HAL_CAMCLK_SRC_Id_MAX ++} HalCamClkSrcId_e; ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk.h b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk.h +new file mode 100755 +index 000000000000..dd27fd24a52d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk.h +@@ -0,0 +1,26 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_H__ ++#define __HAL_CAMCLK_H__ ++#include "drv_camclk_DataType.h" ++#include "hal_camclk_st.h" ++#include "hal_camclk_if_st.h" ++ ++const extern HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX]; ++extern HalCamClkTopClk_t *gCamClkTopCurrent; ++extern u16 gu16HandlerCnt; ++extern struct CamOsListHead_t gstClkListHead; ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_complex.h b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_complex.h +new file mode 100644 +index 000000000000..d385cfa4c897 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_complex.h +@@ -0,0 +1,21 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include "hal_camclk_if_st.h" ++extern HalCamClkAdjOps_t gLpllOps; ++extern HalCamClkAdjOps_t gDdrpllOps; ++extern HalCamClkAdjOps_t gMiupllOps; ++extern HalCamClkAdjOps_t gCpupllOps; ++extern HalCamClkAdjOps_t gFuart0Ops; ++extern HalCamClkAdjOps_t gCsi2Ops; +diff --git a/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_lpll_tbl.h b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_lpll_tbl.h +new file mode 100644 +index 000000000000..47f5bdc4b74f +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_lpll_tbl.h +@@ -0,0 +1,75 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_LPLL_TBL_H_ ++#define _CAMCLK_LPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define HAL_CAMCLK_LPLL_REG_NUM 6 ++ ++#define DATA_LANE_9MHZ (9000000) ++#define DATA_LANE_9_5MHZ (9500000) ++#define DATA_LANE_12_5MHZ (12500000) ++#define DATA_LANE_25MHZ (25000000) ++#define DATA_LANE_50MHZ (50000000) ++#define DATA_LANE_100MHZ (100000000) ++#define DATA_LANE_187_5MHZ (187500000) ++#define DATA_LANE_200MHZ (200000000) ++#define DATA_LANE_400MHZ (400000000) ++#define DATA_LANE_800MHZ (800000000) ++#define DATA_LANE_1500MHZ (1500000000) ++ ++#define IS_DATA_LANE_LESS_100M(bps) ( bps <= DATA_LANE_100MHZ ) ++#define IS_DATA_LANE_BPS_100M_TO_200M(bps) ( (bps > DATA_LANE_100MHZ) && (bps <= DATA_LANE_200MHZ ) ) ++#define IS_DATA_LANE_BPS_200M_TO_400M(bps) ( (bps > DATA_LANE_200MHZ) && (bps <= DATA_LANE_400MHZ ) ) ++#define IS_DATA_LANE_BPS_400M_TO_800M(bps) ( (bps > DATA_LANE_400MHZ) && (bps <= DATA_LANE_800MHZ ) ) ++#define IS_DATA_LANE_BPS_800M_TO_15000M(bps) ( (bps > DATA_LANE_800MHZ) && (bps <= DATA_LANE_1500MHZ ) ) ++ ++#define IS_DATA_LANE_LESS_9M(bps) ( bps < DATA_LANE_9MHZ ) ++#define IS_DATA_LANE_BPS_9M_TO_9_5M(bps) ( (bps >= DATA_LANE_9MHZ) && (bps < DATA_LANE_9_5MHZ ) ) ++#define IS_DATA_LANE_BPS_12_5M_TO_25M(bps) ( (bps > DATA_LANE_12_5MHZ) && (bps <= DATA_LANE_25MHZ ) ) ++#define IS_DATA_LANE_BPS_25M_TO_50M(bps) ( (bps > DATA_LANE_25MHZ) && (bps <= DATA_LANE_50MHZ ) ) ++#define IS_DATA_LANE_BPS_50M_TO_100M(bps) ( (bps > DATA_LANE_50MHZ) && (bps <= DATA_LANE_100MHZ ) ) ++#define REG_LPLL_BASE 0x103300UL ++#define REG_LPLL_48_L (REG_LPLL_BASE + 0x90) ++#define REG_LPLL_48_H (REG_LPLL_BASE + 0x91) ++#define REG_LPLL_49_L (REG_LPLL_BASE + 0x92) ++#define REG_LPLL_49_H (REG_LPLL_BASE + 0x93) ++ ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ, //0 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ, //1 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ, //2 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ, //3 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_MAX, //4 ++} HalCamClkLpllType_e; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 address; ++ u16 value; ++}HalCamClkLpllTbl_t; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_st.h b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_st.h +new file mode 100644 +index 000000000000..ca2c85a0aeb5 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/inc/hal_camclk_st.h +@@ -0,0 +1,38 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_ST_H__ ++#define __HAL_CAMCLK_ST_H__ ++ ++ ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkSetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkGetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32RoundRate; ++}HalCamClkGetComplexRoundRate_t; ++typedef struct ++{ ++ u8 bEn; ++}HalCamClkComplexOnOff_t; ++#endif /* MHAL_DIP_H */ +diff --git a/drivers/sstar/camclk/hal/infinity6/pub/camclk.h b/drivers/sstar/camclk/hal/infinity6/pub/camclk.h +new file mode 100644 +index 000000000000..2e47c8f657f8 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/pub/camclk.h +@@ -0,0 +1,201 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_upll_384m 3 ++#define CAMCLK_upll_320m 4 ++#define CAMCLK_mpll_288m 5 ++#define CAMCLK_utmi_240m 6 ++#define CAMCLK_mpll_216m 7 ++#define CAMCLK_utmi_192m 8 ++#define CAMCLK_mpll_172m 9 ++#define CAMCLK_utmi_160m 10 ++#define CAMCLK_mpll_123m 11 ++#define CAMCLK_mpll_86m 12 ++#define CAMCLK_mpll_288m_div2 13 ++#define CAMCLK_mpll_288m_div4 14 ++#define CAMCLK_mpll_288m_div8 15 ++#define CAMCLK_mpll_216m_div2 16 ++#define CAMCLK_mpll_216m_div4 17 ++#define CAMCLK_mpll_216m_div8 18 ++#define CAMCLK_mpll_123m_div2 19 ++#define CAMCLK_mpll_86m_div2 20 ++#define CAMCLK_mpll_86m_div4 21 ++#define CAMCLK_mpll_86m_div16 22 ++#define CAMCLK_utmi_192m_div4 23 ++#define CAMCLK_utmi_160m_div4 24 ++#define CAMCLK_utmi_160m_div5 25 ++#define CAMCLK_utmi_160m_div8 26 ++#define CAMCLK_xtali_12m 27 ++#define CAMCLK_xtali_12m_div8 28 ++#define CAMCLK_xtali_12m_div16 29 ++#define CAMCLK_xtali_12m_div40 30 ++#define CAMCLK_xtali_12m_div64 31 ++#define CAMCLK_xtali_12m_div128 32 ++#define CAMCLK_xtali_24m 33 ++#define CAMCLK_RTC_CLK_32K 34 ++#define CAMCLK_pm_riu_w_clk_in 35 ++#define CAMCLK_lpll_clk_div2 36 ++#define CAMCLK_lpll_clk_div4 37 ++#define CAMCLK_lpll_clk_div8 38 ++#define CAMCLK_armpll_37p125m 39 ++#define CAMCLK_riu_w_clk_in 40 ++#define CAMCLK_riu_w_clk_top 41 ++#define CAMCLK_riu_w_clk_sc_gp 42 ++#define CAMCLK_riu_w_clk_vhe_gp 43 ++#define CAMCLK_riu_w_clk_hemcu_gp 44 ++#define CAMCLK_riu_w_clk_mipi_if_gp 45 ++#define CAMCLK_riu_w_clk_mcu_if_gp 46 ++#define CAMCLK_miu_p 47 ++#define CAMCLK_mspi0_p 48 ++#define CAMCLK_mspi1_p 49 ++#define CAMCLK_miu_vhe_gp_p 50 ++#define CAMCLK_miu_sc_gp_p 51 ++#define CAMCLK_miu2x_p 52 ++#define CAMCLK_mcu_p 53 ++#define CAMCLK_mcu_pm_p 54 ++#define CAMCLK_isp_p 55 ++#define CAMCLK_fclk1_p 56 ++#define CAMCLK_fclk2_p 57 ++#define CAMCLK_sdio_p 58 ++#define CAMCLK_tck_buf 59 ++#define CAMCLK_pad2isp_sr_pclk 60 ++#define CAMCLK_ccir_in_clk 61 ++#define CAMCLK_eth_buf 62 ++#define CAMCLK_rmii_buf 63 ++#define CAMCLK_emac_testrx125_in_lan 64 ++#define CAMCLK_miu_ff 65 ++#define CAMCLK_miu_sc_gp 66 ++#define CAMCLK_miu_vhe_gp 67 ++#define CAMCLK_miu_dig 68 ++#define CAMCLK_miu_xd2miu 69 ++#define CAMCLK_miu_urdma 70 ++#define CAMCLK_miu_bdma 71 ++#define CAMCLK_miu_vhe 72 ++#define CAMCLK_miu_mfeh 73 ++#define CAMCLK_miu_mfe 74 ++#define CAMCLK_miu_jpe1 75 ++#define CAMCLK_miu_jpe0 76 ++#define CAMCLK_miu_bach 77 ++#define CAMCLK_miu_file 78 ++#define CAMCLK_miu_uhc0 79 ++#define CAMCLK_miu_emac 80 ++#define CAMCLK_miu_cmdq 81 ++#define CAMCLK_miu_isp_dnr 82 ++#define CAMCLK_miu_isp_rot 83 ++#define CAMCLK_miu_isp_dma 84 ++#define CAMCLK_miu_isp_sta 85 ++#define CAMCLK_miu_gop 86 ++#define CAMCLK_miu_sc_dnr 87 ++#define CAMCLK_miu_sc_dnr_sad 88 ++#define CAMCLK_miu_sc_crop 89 ++#define CAMCLK_miu_sc1_frm 90 ++#define CAMCLK_miu_sc1_snp 91 ++#define CAMCLK_miu_sc1_snpi 92 ++#define CAMCLK_miu_sc1_dbg 93 ++#define CAMCLK_miu_sc2_frm 94 ++#define CAMCLK_miu_sc2_snpi 95 ++#define CAMCLK_miu_sc3_frm 96 ++#define CAMCLK_miu_fcie 97 ++#define CAMCLK_miu_sdio 98 ++#define CAMCLK_miu_ive 99 ++#define CAMCLK_riu 100 ++#define CAMCLK_riu_nogating 101 ++#define CAMCLK_riu_sc_gp 102 ++#define CAMCLK_riu_vhe_gp 103 ++#define CAMCLK_riu_hemcu_gp 104 ++#define CAMCLK_riu_mipi_gp 105 ++#define CAMCLK_riu_mcu_if 106 ++#define CAMCLK_miu2x 107 ++#define CAMCLK_axi2x 108 ++#define CAMCLK_tck 109 ++#define CAMCLK_imi 110 ++#define CAMCLK_gop0 111 ++#define CAMCLK_gop1 112 ++#define CAMCLK_gop2 113 ++#define CAMCLK_mpll_144m 114 ++#define CAMCLK_mpll_144m_div2 115 ++#define CAMCLK_mpll_144m_div4 116 ++#define CAMCLK_xtali_12m_div2 117 ++#define CAMCLK_xtali_12m_div4 118 ++#define CAMCLK_xtali_12m_div12 119 ++#define CAMCLK_rtc_32k 120 ++#define CAMCLK_rtc_32k_div4 121 ++#define CAMCLK_live_pm 122 ++#define CAMCLK_riu_pm 123 ++#define CAMCLK_miupll_clk 124 ++#define CAMCLK_ddrpll_clk 125 ++#define CAMCLK_lpll_clk 126 ++#define CAMCLK_cpupll_clk 127 ++#define CAMCLK_utmi 128 ++#define CAMCLK_upll 129 ++#define CAMCLK_fuart0_synth_out 130 ++#define CAMCLK_csi2_mac_p 131 ++#define CAMCLK_miu 132 ++#define CAMCLK_ddr_syn 133 ++#define CAMCLK_miu_rec 134 ++#define CAMCLK_mcu 135 ++#define CAMCLK_riubrdg 136 ++#define CAMCLK_bdma 137 ++#define CAMCLK_spi 138 ++#define CAMCLK_uart0 139 ++#define CAMCLK_uart1 140 ++#define CAMCLK_fuart0_synth_in 141 ++#define CAMCLK_fuart 142 ++#define CAMCLK_mspi0 143 ++#define CAMCLK_mspi1 144 ++#define CAMCLK_mspi 145 ++#define CAMCLK_miic0 146 ++#define CAMCLK_miic1 147 ++#define CAMCLK_bist 148 ++#define CAMCLK_pwr_ctl 149 ++#define CAMCLK_xtali 150 ++#define CAMCLK_live 151 ++#define CAMCLK_sr_mclk 152 ++#define CAMCLK_bist_vhe_gp 153 ++#define CAMCLK_vhe 154 ++#define CAMCLK_mfe 155 ++#define CAMCLK_xtali_sc_gp 156 ++#define CAMCLK_bist_sc_gp 157 ++#define CAMCLK_emac_ahb 158 ++#define CAMCLK_jpe 159 ++#define CAMCLK_aesdma 160 ++#define CAMCLK_sdio 161 ++#define CAMCLK_sd 162 ++#define CAMCLK_isp 163 ++#define CAMCLK_fclk1 164 ++#define CAMCLK_fclk2 165 ++#define CAMCLK_odclk 166 ++#define CAMCLK_dip 167 ++#define CAMCLK_nlm 168 ++#define CAMCLK_emac_tx 169 ++#define CAMCLK_emac_rx 170 ++#define CAMCLK_emac_tx_ref 171 ++#define CAMCLK_emac_rx_ref 172 ++#define CAMCLK_hemcu_216m 173 ++#define CAMCLK_csi_mac 174 ++#define CAMCLK_mac_lptx 175 ++#define CAMCLK_ns 176 ++#define CAMCLK_mcu_pm 177 ++#define CAMCLK_spi_pm 178 ++#define CAMCLK_pm_sleep 179 ++#define CAMCLK_sar 180 ++#define CAMCLK_rtc 181 ++#define CAMCLK_ir 182 ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6/pub/reg_clks.h b/drivers/sstar/camclk/hal/infinity6/pub/reg_clks.h +new file mode 100644 +index 000000000000..aea7f0c63eff +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/pub/reg_clks.h +@@ -0,0 +1,463 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I6/iNfinity6_Clock_Table_1022_SW.xls */ ++/* REG FILENAME: I6/iNfinity6_reg_CLKGEN.xls, I6/iNfinity6_reg_pm_sleep.xls, I6/iNfinity6_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_CKG_SNR0_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR0_OFFSET (0) ++ ++#define REG_CKG_SNR1_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR1_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PWM_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_BT656_0_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_BT656_0_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FCLK2_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SD_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6/src/hal_camclk_complex.c b/drivers/sstar/camclk/hal/infinity6/src/hal_camclk_complex.c +new file mode 100644 +index 000000000000..4ddb8a448ecc +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/src/hal_camclk_complex.c +@@ -0,0 +1,472 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_LPLL_C ++#include "camclk_dbg.h" ++#include "hal_camclk_if_st.h" ++#include "hal_camclk_lpll_tbl.h" ++#include "hal_camclk_util.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "registers.h" ++#include "ms_platform.h" ++ ++ ++HalCamClkLpllTbl_t gCamClkLPLLSettingTBL[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX][HAL_CAMCLK_LPLL_REG_NUM]= ++{ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0041}, ++ {0x103386, 0x0000}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0042}, ++ {0x103386, 0x0001}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0043}, ++ {0x103386, 0x0002}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0083}, ++ {0x103386, 0x0003}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++}; ++#define PLL_REG_GET(address) (0x1F000000 + ((address)<<1)) ++u16 u16LoopGain[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX]= ++{ ++ 16, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ 8, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ 4, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ 2, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++}; ++u32 u16gLpllDiv = 8; ++u8 bLook = 0; ++ ++void HalCamClkGetLpllIdxFromHw(u16 *pu16Idx) ++{ ++ u16 u16Val; ++ u8 idx; ++ u16Val = R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][2].address)); ++ for(idx =0 ;idx> 16); ++ W2BYTE(PLL_REG_GET(REG_LPLL_48_L), u16LpllSet_Lo); // @suppress("Symbol is not resolved") ++ W2BYTE(PLL_REG_GET(REG_LPLL_49_L), u16LpllSet_Hi); // @suppress("Symbol is not resolved") ++} ++ ++void HalCamClkGetLpllSet(u32 *u32LpllSet) ++{ ++ u16 u16LpllSet_Lo, u16LpllSet_Hi; ++ ++ u16LpllSet_Lo = R2BYTE(PLL_REG_GET(REG_LPLL_48_L)); ++ u16LpllSet_Hi = R2BYTE(PLL_REG_GET(REG_LPLL_49_L)); ++ *u32LpllSet = (u16LpllSet_Lo | ((u32)u16LpllSet_Hi<<16)); ++} ++ ++CAMCLK_RET_e HalCamClkSetLpllRate(void *pCfg) ++{ ++ u16 u16LpllIdx; ++ u16 u16Div; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ HalCamClkSetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ if(bLook) ++ { ++ Ret = CAMCLK_RET_FAIL; ++ CAMCLKERR("%s %d, LPLL Locked:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ else ++ { ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate, &u16LpllIdx, &u16Div)) ++ { ++ if(u16LpllIdx != E_HAL_CAMCLK_SUPPORTED_LPLL_MAX) ++ { ++ u16LoopGain = HalCamClkGetLpllGain(u16LpllIdx); ++ u64Dividen = (pLpllCfg->u32ParentRate); ++ u64Dividen = (u64)(u64Dividen * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16Div,NULL); ++ u32Divisor = pLpllCfg->u32Rate; ++ u32LplLSet = (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ CAMCLKDBG("[CAMCLK]%s %d:: Idx:%d, LoopGain:%d, LoopDiv:%d, dclk=%ld, Divden:0x%llx, Divisor:0x%lx, LpllSe:0x%lx\n", ++ __FUNCTION__, __LINE__, u16LpllIdx, ++ u16LoopGain, u16Div, pLpllCfg->u32Rate, ++ u64Dividen, u32Divisor, u32LplLSet); ++ ++ HalCamClkDumpLpllSetting(u16LpllIdx); ++ HalCamClkSetLpllSet(u32LplLSet); ++ u16gLpllDiv = u16Div; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetLpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u16 u16idx; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ ++ HalCamClkGetLpllIdxFromHw(&u16idx); ++ u16LoopGain = HalCamClkGetLpllGain(u16idx); ++ HalCamClkGetLpllSet(&u32LplLSet); ++ u64Dividen = pLpllCfg->u32ParentRate; ++ u64Dividen = (u64)((u64Dividen) * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16gLpllDiv,NULL); ++ u32Divisor = u32LplLSet; ++ pLpllCfg->u32Rate= (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetLpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pLpllCfg = pCfg; ++ u16 u16Temp; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate,&u16Temp,&u16Temp)) ++ { ++ pLpllCfg->u32RoundRate = pLpllCfg->u32Rate; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ if(pLpllCfg->u32Rateu32RoundRate = DATA_LANE_12_5MHZ; ++ } ++ else ++ { ++ pLpllCfg->u32RoundRate = DATA_LANE_1500MHZ; ++ } ++ } ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pLpllCfg->bEn = (R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address))&camclk_BIT13)>>13; ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkSetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address), pLpllCfg->bEn ? camclk_BIT13 : 0 , camclk_BIT13); ++ bLook = pLpllCfg->bEn; ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetMiupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pMiupllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_miupll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pMiupllCfg->u32Rate = (u32)CamOsMathDivU64((u64)stRateCfg.u32Freq * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF), (u64)((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2), NULL); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetDdrpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pDdrpllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_ddrpll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pDdrpllCfg->u32Rate = (u32)CamOsMathDivU64(((u64)stRateCfg.u32Freq * 4 * 4) << 19, (u64)((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF)), NULL); ++ ++ return Ret; ++} ++ ++static void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++CAMCLK_RET_e HalCamClkSetCpupllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pCpupllCfg = pCfg; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //CamOsPrintf("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (pCpupllCfg->u32Rate >= 800000000) ++ post_div = 2; ++ else if (pCpupllCfg->u32Rate >= 400000000) ++ post_div = 4; ++ else if (pCpupllCfg->u32Rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, (pCpupllCfg->u32Rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pCpupllCfg = pCfg; ++ u32 lpf_value; ++ u32 post_div; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ //CamOsPrintf("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ pCpupllCfg->u32Rate = (div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ //CamOsPrintf("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", pCpupllCfg->u32Rate, pCpupllCfg->u32ParentRate); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pCpupllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pCpupllCfg->u32Rate < 100000000) // 100MHz ++ { ++ pCpupllCfg->u32RoundRate = 100000000; ++ } ++ else if(pCpupllCfg->u32Rate > 1400000000) // 1.4GHz ++ { ++ pCpupllCfg->u32RoundRate = 1400000000; ++ } ++ else ++ { ++ pCpupllCfg->u32RoundRate = pCpupllCfg->u32Rate; ++ } ++ ++ return Ret; ++} ++ ++HalCamClkAdjOps_t gMiupllOps={0,0,0,HalCamClkGetMiupllRate,0,0,0}; ++HalCamClkAdjOps_t gDdrpllOps={0,0,0,HalCamClkGetDdrpllRate,0,0,0}; ++HalCamClkAdjOps_t gLpllOps={0,0,HalCamClkSetLpllRate,HalCamClkGetLpllRate,HalCamClkGetLpllRoundRate,HalCamClkSetLpllOnOff,HalCamClkGetLpllOnOff}; ++HalCamClkAdjOps_t gCpupllOps={0,0,HalCamClkSetCpupllRate,HalCamClkGetCpupllRate,HalCamClkGetCpupllRoundRate,0,0}; ++HalCamClkAdjOps_t gFuart0Ops={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gCsi2Ops={0,0,0,0,0,0,0}; ++#undef HAL_CAMCLKTBL_LPLL_C +diff --git a/drivers/sstar/camclk/hal/infinity6/src/hal_camclk_tbl.c b/drivers/sstar/camclk/hal/infinity6/src/hal_camclk_tbl.c +new file mode 100644 +index 000000000000..34bb4ad54d50 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6/src/hal_camclk_tbl.c +@@ -0,0 +1,208 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_C ++#include "hal_camclk_if.h" ++#include "hal_camclk_complex.h" ++#include "reg_clks.h" ++#include "hal_camclk_util.h" ++ ++const HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX] = ++{ ++ {HAL_CAMCLK_SRC_CLK_VOID, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_480m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_432m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll_384m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,5,4}}, ++ {HAL_CAMCLK_SRC_CLK_upll_320m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,3,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={288000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_240m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={216000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,5,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_172m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={172800000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,3,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={123400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={86400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_123m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_192m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div5, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,5,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={12000000}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div40, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,40,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div64, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,64,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div128, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,128,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_24m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={24000000}}, ++ {HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_armpll_37p125m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_432m,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_top, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi0,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_vhe_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu_pm,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_isp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_isp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk2_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk2,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_sdio_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_sdio,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_ccir_in_clk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_eth_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_rmii_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ff, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_dig, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_xd2miu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_urdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_bdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_mfeh, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_mfe, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_jpe1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_jpe0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_bach, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_file, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_uhc0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_emac, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_cmdq, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_dnr, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_rot, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_dma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_sta, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_gop, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_dnr, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_dnr_sad, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_crop, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_snp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_snpi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_dbg, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc2_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc2_snpi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc3_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_fcie, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sdio, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ive, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_top,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_nogating, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mipi_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mcu_if, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_ddrpll_clk,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_axi2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_tck_buf,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_imi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk2_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={144000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div12, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,12,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_rtc_32k,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_live_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_24m,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m, &gMiupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_ddrpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_ddr_syn,&gDdrpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gLpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_cpupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gCpupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_utmi, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_out, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_fuart0_synth_in,&gFuart0Ops}}, ++ {HAL_CAMCLK_SRC_CLK_csi2_mac_p, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_csi_mac,&gCsi2Ops}}, ++ {HAL_CAMCLK_SRC_CLK_miu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_ddrpll_clk,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_miupll_clk,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_MIU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ddr_syn, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DDR_SYN_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_rec, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div64,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div128},REG_CKG_MIU_REC_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_MCU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_riubrdg, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mcu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RIUBRDG_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_bdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_BDMA_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_spi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4},REG_CKG_SPI_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_uart0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_in, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FUART0_SYNTH_IN_BASE,camclk_BIT4,0,2,6,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fuart0_synth_out},REG_CKG_FUART_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mspi0_p,(u8)HAL_CAMCLK_SRC_CLK_mspi1_p},REG_CKG_MSPI_BASE,camclk_BIT12,0,1,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_pwr_ctl, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PWR_CTL_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_live, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_sr_mclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div8,(u8)HAL_CAMCLK_SRC_CLK_armpll_37p125m},REG_CKG_SR_MCLK_BASE,camclk_BIT8,0,4,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_vhe_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_VHE_GP_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_vhe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_VHE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mfe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m},REG_CKG_MFE_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_SC_GP_BASE,camclk_BIT4,0,2,6,1}}, ++ {HAL_CAMCLK_SRC_CLK_bist_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_SC_GP_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_ahb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan},REG_CKG_EMAC_AHB_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_jpe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_JPE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_aesdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_AESDMA_BASE,camclk_BIT0,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sdio, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SDIO_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sd, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SD_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_isp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m},REG_CKG_ISP_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m},REG_CKG_FCLK1_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_fclk2, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FCLK2_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_odclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk},REG_CKG_ODCLK_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_dip, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DIP_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_nlm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_fclk1_p},REG_CKG_NLM_BASE,camclk_BIT8,0,1,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_TX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_RX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_TX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_RX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_hemcu_216m, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_HEMCU_216M_BASE,camclk_BIT0,0,0,0,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mac_lptx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MAC_LPTX_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ns, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_MCU_PM_BASE,camclk_BIT0,camclk_BIT7,4,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m},REG_CKG_SPI_PM_BASE,camclk_BIT8,camclk_BIT14,4,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_pm_sleep, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_PM_SLEEP_BASE,0,0,3,12,0}}, ++ {HAL_CAMCLK_SRC_CLK_sar, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_SAR_BASE,camclk_BIT5,0,3,7,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RTC_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ir, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_IR_BASE,camclk_BIT5,0,3,7,1}}, ++}; ++ ++#undef HAL_CAMCLKTBL_C +diff --git a/drivers/sstar/camclk/hal/infinity6b0/inc/camclk_id.h b/drivers/sstar/camclk/hal/infinity6b0/inc/camclk_id.h +new file mode 100644 +index 000000000000..8fe260ead106 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/inc/camclk_id.h +@@ -0,0 +1,206 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_ID_H__ ++#define __CAMCLK_ID_H__ ++typedef enum ++{ ++ HAL_CAMCLK_SRC_CLK_VOID, ++ HAL_CAMCLK_SRC_CLK_utmi_480m, ++ HAL_CAMCLK_SRC_CLK_mpll_432m, ++ HAL_CAMCLK_SRC_CLK_mpll_345m, ++ HAL_CAMCLK_SRC_CLK_upll_384m, ++ HAL_CAMCLK_SRC_CLK_upll_320m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m, ++ HAL_CAMCLK_SRC_CLK_utmi_240m, ++ HAL_CAMCLK_SRC_CLK_mpll_216m, ++ HAL_CAMCLK_SRC_CLK_utmi_192m, ++ HAL_CAMCLK_SRC_CLK_mpll_172m, ++ HAL_CAMCLK_SRC_CLK_utmi_160m, ++ HAL_CAMCLK_SRC_CLK_mpll_123m, ++ HAL_CAMCLK_SRC_CLK_mpll_86m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_123m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div16, ++ HAL_CAMCLK_SRC_CLK_utmi_192m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div5, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div16, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div40, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div64, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div128, ++ HAL_CAMCLK_SRC_CLK_xtali_24m, ++ HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, ++ HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div2, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div4, ++ HAL_CAMCLK_SRC_CLK_lpll_clk_div8, ++ HAL_CAMCLK_SRC_CLK_armpll_37p125m, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_top, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, ++ HAL_CAMCLK_SRC_CLK_miu_p, ++ HAL_CAMCLK_SRC_CLK_mspi0_p, ++ HAL_CAMCLK_SRC_CLK_mspi1_p, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu2x_p, ++ HAL_CAMCLK_SRC_CLK_mcu_p, ++ HAL_CAMCLK_SRC_CLK_mcu_pm_p, ++ HAL_CAMCLK_SRC_CLK_isp_p, ++ HAL_CAMCLK_SRC_CLK_fclk1_p, ++ HAL_CAMCLK_SRC_CLK_fclk2_p, ++ HAL_CAMCLK_SRC_CLK_sdio_p, ++ HAL_CAMCLK_SRC_CLK_tck_buf, ++ HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, ++ HAL_CAMCLK_SRC_CLK_ccir_in_clk, ++ HAL_CAMCLK_SRC_CLK_eth_buf, ++ HAL_CAMCLK_SRC_CLK_rmii_buf, ++ HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, ++ HAL_CAMCLK_SRC_CLK_miu_ff, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_miu_dig, ++ HAL_CAMCLK_SRC_CLK_miu_xd2miu, ++ HAL_CAMCLK_SRC_CLK_miu_urdma, ++ HAL_CAMCLK_SRC_CLK_miu_bdma, ++ HAL_CAMCLK_SRC_CLK_miu_vhe, ++ HAL_CAMCLK_SRC_CLK_miu_mfeh, ++ HAL_CAMCLK_SRC_CLK_miu_mfe, ++ HAL_CAMCLK_SRC_CLK_miu_jpe1, ++ HAL_CAMCLK_SRC_CLK_miu_jpe0, ++ HAL_CAMCLK_SRC_CLK_miu_bach, ++ HAL_CAMCLK_SRC_CLK_miu_file, ++ HAL_CAMCLK_SRC_CLK_miu_uhc0, ++ HAL_CAMCLK_SRC_CLK_miu_emac, ++ HAL_CAMCLK_SRC_CLK_miu_cmdq, ++ HAL_CAMCLK_SRC_CLK_miu_isp_dnr, ++ HAL_CAMCLK_SRC_CLK_miu_isp_rot, ++ HAL_CAMCLK_SRC_CLK_miu_isp_dma, ++ HAL_CAMCLK_SRC_CLK_miu_isp_sta, ++ HAL_CAMCLK_SRC_CLK_miu_gop, ++ HAL_CAMCLK_SRC_CLK_miu_sc_dnr, ++ HAL_CAMCLK_SRC_CLK_miu_sc_dnr_sad, ++ HAL_CAMCLK_SRC_CLK_miu_sc_crop, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_frm, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_snp, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_snpi, ++ HAL_CAMCLK_SRC_CLK_miu_sc1_dbg, ++ HAL_CAMCLK_SRC_CLK_miu_sc2_frm, ++ HAL_CAMCLK_SRC_CLK_miu_sc2_snpi, ++ HAL_CAMCLK_SRC_CLK_miu_sc3_frm, ++ HAL_CAMCLK_SRC_CLK_miu_fcie, ++ HAL_CAMCLK_SRC_CLK_miu_sdio, ++ HAL_CAMCLK_SRC_CLK_miu_ive, ++ HAL_CAMCLK_SRC_CLK_riu, ++ HAL_CAMCLK_SRC_CLK_riu_nogating, ++ HAL_CAMCLK_SRC_CLK_riu_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mipi_gp, ++ HAL_CAMCLK_SRC_CLK_riu_mcu_if, ++ HAL_CAMCLK_SRC_CLK_miu2x, ++ HAL_CAMCLK_SRC_CLK_axi2x, ++ HAL_CAMCLK_SRC_CLK_tck, ++ HAL_CAMCLK_SRC_CLK_imi, ++ HAL_CAMCLK_SRC_CLK_gop0, ++ HAL_CAMCLK_SRC_CLK_gop1, ++ HAL_CAMCLK_SRC_CLK_gop2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_144m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div2, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div12, ++ HAL_CAMCLK_SRC_CLK_rtc_32k, ++ HAL_CAMCLK_SRC_CLK_rtc_32k_div4, ++ HAL_CAMCLK_SRC_CLK_live_pm, ++ HAL_CAMCLK_SRC_CLK_riu_pm, ++ HAL_CAMCLK_SRC_CLK_miupll_clk, ++ HAL_CAMCLK_SRC_CLK_ddrpll_clk, ++ HAL_CAMCLK_SRC_CLK_lpll_clk, ++ HAL_CAMCLK_SRC_CLK_cpupll_clk, ++ HAL_CAMCLK_SRC_CLK_utmi, ++ HAL_CAMCLK_SRC_CLK_upll, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_out, ++ HAL_CAMCLK_SRC_CLK_csi2_mac_p, ++ HAL_CAMCLK_SRC_CLK_miu, ++ HAL_CAMCLK_SRC_CLK_ddr_syn, ++ HAL_CAMCLK_SRC_CLK_miu_rec, ++ HAL_CAMCLK_SRC_CLK_mcu, ++ HAL_CAMCLK_SRC_CLK_riubrdg, ++ HAL_CAMCLK_SRC_CLK_bdma, ++ HAL_CAMCLK_SRC_CLK_spi, ++ HAL_CAMCLK_SRC_CLK_uart0, ++ HAL_CAMCLK_SRC_CLK_uart1, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_in, ++ HAL_CAMCLK_SRC_CLK_fuart, ++ HAL_CAMCLK_SRC_CLK_mspi0, ++ HAL_CAMCLK_SRC_CLK_mspi1, ++ HAL_CAMCLK_SRC_CLK_mspi, ++ HAL_CAMCLK_SRC_CLK_miic0, ++ HAL_CAMCLK_SRC_CLK_miic1, ++ HAL_CAMCLK_SRC_CLK_bist, ++ HAL_CAMCLK_SRC_CLK_pwr_ctl, ++ HAL_CAMCLK_SRC_CLK_xtali, ++ HAL_CAMCLK_SRC_CLK_live, ++ HAL_CAMCLK_SRC_CLK_sr_mclk, ++ HAL_CAMCLK_SRC_CLK_bist_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_vhe, ++ HAL_CAMCLK_SRC_CLK_vhe_vpu, ++ HAL_CAMCLK_SRC_CLK_xtali_sc_gp, ++ HAL_CAMCLK_SRC_CLK_bist_sc_gp, ++ HAL_CAMCLK_SRC_CLK_emac_ahb, ++ HAL_CAMCLK_SRC_CLK_jpe, ++ HAL_CAMCLK_SRC_CLK_aesdma, ++ HAL_CAMCLK_SRC_CLK_sdio, ++ HAL_CAMCLK_SRC_CLK_sd, ++ HAL_CAMCLK_SRC_CLK_isp, ++ HAL_CAMCLK_SRC_CLK_fclk1, ++ HAL_CAMCLK_SRC_CLK_fclk2, ++ HAL_CAMCLK_SRC_CLK_odclk, ++ HAL_CAMCLK_SRC_CLK_dip, ++ HAL_CAMCLK_SRC_CLK_ive, ++ HAL_CAMCLK_SRC_CLK_nlm, ++ HAL_CAMCLK_SRC_CLK_emac_tx, ++ HAL_CAMCLK_SRC_CLK_emac_rx, ++ HAL_CAMCLK_SRC_CLK_emac_tx_ref, ++ HAL_CAMCLK_SRC_CLK_emac_rx_ref, ++ HAL_CAMCLK_SRC_CLK_hemcu_216m, ++ HAL_CAMCLK_SRC_CLK_csi_mac, ++ HAL_CAMCLK_SRC_CLK_mac_lptx, ++ HAL_CAMCLK_SRC_CLK_ns, ++ HAL_CAMCLK_SRC_CLK_mcu_pm, ++ HAL_CAMCLK_SRC_CLK_spi_pm, ++ HAL_CAMCLK_SRC_CLK_pm_sleep, ++ HAL_CAMCLK_SRC_CLK_sar, ++ HAL_CAMCLK_SRC_CLK_rtc, ++ HAL_CAMCLK_SRC_CLK_ir, ++ HAL_CAMCLK_SRC_Id_MAX ++} HalCamClkSrcId_e; ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk.h b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk.h +new file mode 100644 +index 000000000000..dd27fd24a52d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk.h +@@ -0,0 +1,26 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_H__ ++#define __HAL_CAMCLK_H__ ++#include "drv_camclk_DataType.h" ++#include "hal_camclk_st.h" ++#include "hal_camclk_if_st.h" ++ ++const extern HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX]; ++extern HalCamClkTopClk_t *gCamClkTopCurrent; ++extern u16 gu16HandlerCnt; ++extern struct CamOsListHead_t gstClkListHead; ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_complex.h b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_complex.h +new file mode 100644 +index 000000000000..478c01ee7271 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_complex.h +@@ -0,0 +1,21 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include "hal_camclk_if_st.h" ++extern HalCamClkAdjOps_t gMiupllOps; ++extern HalCamClkAdjOps_t gDdrpllOps; ++extern HalCamClkAdjOps_t gLpllOps; ++extern HalCamClkAdjOps_t gCpupllOps; ++extern HalCamClkAdjOps_t gFuart0Ops; ++extern HalCamClkAdjOps_t gCsi2Ops; +diff --git a/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_lpll_tbl.h b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_lpll_tbl.h +new file mode 100644 +index 000000000000..47f5bdc4b74f +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_lpll_tbl.h +@@ -0,0 +1,75 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_LPLL_TBL_H_ ++#define _CAMCLK_LPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define HAL_CAMCLK_LPLL_REG_NUM 6 ++ ++#define DATA_LANE_9MHZ (9000000) ++#define DATA_LANE_9_5MHZ (9500000) ++#define DATA_LANE_12_5MHZ (12500000) ++#define DATA_LANE_25MHZ (25000000) ++#define DATA_LANE_50MHZ (50000000) ++#define DATA_LANE_100MHZ (100000000) ++#define DATA_LANE_187_5MHZ (187500000) ++#define DATA_LANE_200MHZ (200000000) ++#define DATA_LANE_400MHZ (400000000) ++#define DATA_LANE_800MHZ (800000000) ++#define DATA_LANE_1500MHZ (1500000000) ++ ++#define IS_DATA_LANE_LESS_100M(bps) ( bps <= DATA_LANE_100MHZ ) ++#define IS_DATA_LANE_BPS_100M_TO_200M(bps) ( (bps > DATA_LANE_100MHZ) && (bps <= DATA_LANE_200MHZ ) ) ++#define IS_DATA_LANE_BPS_200M_TO_400M(bps) ( (bps > DATA_LANE_200MHZ) && (bps <= DATA_LANE_400MHZ ) ) ++#define IS_DATA_LANE_BPS_400M_TO_800M(bps) ( (bps > DATA_LANE_400MHZ) && (bps <= DATA_LANE_800MHZ ) ) ++#define IS_DATA_LANE_BPS_800M_TO_15000M(bps) ( (bps > DATA_LANE_800MHZ) && (bps <= DATA_LANE_1500MHZ ) ) ++ ++#define IS_DATA_LANE_LESS_9M(bps) ( bps < DATA_LANE_9MHZ ) ++#define IS_DATA_LANE_BPS_9M_TO_9_5M(bps) ( (bps >= DATA_LANE_9MHZ) && (bps < DATA_LANE_9_5MHZ ) ) ++#define IS_DATA_LANE_BPS_12_5M_TO_25M(bps) ( (bps > DATA_LANE_12_5MHZ) && (bps <= DATA_LANE_25MHZ ) ) ++#define IS_DATA_LANE_BPS_25M_TO_50M(bps) ( (bps > DATA_LANE_25MHZ) && (bps <= DATA_LANE_50MHZ ) ) ++#define IS_DATA_LANE_BPS_50M_TO_100M(bps) ( (bps > DATA_LANE_50MHZ) && (bps <= DATA_LANE_100MHZ ) ) ++#define REG_LPLL_BASE 0x103300UL ++#define REG_LPLL_48_L (REG_LPLL_BASE + 0x90) ++#define REG_LPLL_48_H (REG_LPLL_BASE + 0x91) ++#define REG_LPLL_49_L (REG_LPLL_BASE + 0x92) ++#define REG_LPLL_49_H (REG_LPLL_BASE + 0x93) ++ ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ, //0 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ, //1 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ, //2 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ, //3 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_MAX, //4 ++} HalCamClkLpllType_e; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 address; ++ u16 value; ++}HalCamClkLpllTbl_t; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_st.h b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_st.h +new file mode 100644 +index 000000000000..ca2c85a0aeb5 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/inc/hal_camclk_st.h +@@ -0,0 +1,38 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_ST_H__ ++#define __HAL_CAMCLK_ST_H__ ++ ++ ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkSetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkGetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32RoundRate; ++}HalCamClkGetComplexRoundRate_t; ++typedef struct ++{ ++ u8 bEn; ++}HalCamClkComplexOnOff_t; ++#endif /* MHAL_DIP_H */ +diff --git a/drivers/sstar/camclk/hal/infinity6b0/src/hal_camclk_complex.c b/drivers/sstar/camclk/hal/infinity6b0/src/hal_camclk_complex.c +new file mode 100644 +index 000000000000..4ddb8a448ecc +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/src/hal_camclk_complex.c +@@ -0,0 +1,472 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_LPLL_C ++#include "camclk_dbg.h" ++#include "hal_camclk_if_st.h" ++#include "hal_camclk_lpll_tbl.h" ++#include "hal_camclk_util.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "registers.h" ++#include "ms_platform.h" ++ ++ ++HalCamClkLpllTbl_t gCamClkLPLLSettingTBL[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX][HAL_CAMCLK_LPLL_REG_NUM]= ++{ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0041}, ++ {0x103386, 0x0000}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0042}, ++ {0x103386, 0x0001}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0043}, ++ {0x103386, 0x0002}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0083}, ++ {0x103386, 0x0003}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++}; ++#define PLL_REG_GET(address) (0x1F000000 + ((address)<<1)) ++u16 u16LoopGain[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX]= ++{ ++ 16, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ 8, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ 4, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ 2, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++}; ++u32 u16gLpllDiv = 8; ++u8 bLook = 0; ++ ++void HalCamClkGetLpllIdxFromHw(u16 *pu16Idx) ++{ ++ u16 u16Val; ++ u8 idx; ++ u16Val = R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][2].address)); ++ for(idx =0 ;idx> 16); ++ W2BYTE(PLL_REG_GET(REG_LPLL_48_L), u16LpllSet_Lo); // @suppress("Symbol is not resolved") ++ W2BYTE(PLL_REG_GET(REG_LPLL_49_L), u16LpllSet_Hi); // @suppress("Symbol is not resolved") ++} ++ ++void HalCamClkGetLpllSet(u32 *u32LpllSet) ++{ ++ u16 u16LpllSet_Lo, u16LpllSet_Hi; ++ ++ u16LpllSet_Lo = R2BYTE(PLL_REG_GET(REG_LPLL_48_L)); ++ u16LpllSet_Hi = R2BYTE(PLL_REG_GET(REG_LPLL_49_L)); ++ *u32LpllSet = (u16LpllSet_Lo | ((u32)u16LpllSet_Hi<<16)); ++} ++ ++CAMCLK_RET_e HalCamClkSetLpllRate(void *pCfg) ++{ ++ u16 u16LpllIdx; ++ u16 u16Div; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ HalCamClkSetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ if(bLook) ++ { ++ Ret = CAMCLK_RET_FAIL; ++ CAMCLKERR("%s %d, LPLL Locked:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ else ++ { ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate, &u16LpllIdx, &u16Div)) ++ { ++ if(u16LpllIdx != E_HAL_CAMCLK_SUPPORTED_LPLL_MAX) ++ { ++ u16LoopGain = HalCamClkGetLpllGain(u16LpllIdx); ++ u64Dividen = (pLpllCfg->u32ParentRate); ++ u64Dividen = (u64)(u64Dividen * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16Div,NULL); ++ u32Divisor = pLpllCfg->u32Rate; ++ u32LplLSet = (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ CAMCLKDBG("[CAMCLK]%s %d:: Idx:%d, LoopGain:%d, LoopDiv:%d, dclk=%ld, Divden:0x%llx, Divisor:0x%lx, LpllSe:0x%lx\n", ++ __FUNCTION__, __LINE__, u16LpllIdx, ++ u16LoopGain, u16Div, pLpllCfg->u32Rate, ++ u64Dividen, u32Divisor, u32LplLSet); ++ ++ HalCamClkDumpLpllSetting(u16LpllIdx); ++ HalCamClkSetLpllSet(u32LplLSet); ++ u16gLpllDiv = u16Div; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetLpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u16 u16idx; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ ++ HalCamClkGetLpllIdxFromHw(&u16idx); ++ u16LoopGain = HalCamClkGetLpllGain(u16idx); ++ HalCamClkGetLpllSet(&u32LplLSet); ++ u64Dividen = pLpllCfg->u32ParentRate; ++ u64Dividen = (u64)((u64Dividen) * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16gLpllDiv,NULL); ++ u32Divisor = u32LplLSet; ++ pLpllCfg->u32Rate= (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetLpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pLpllCfg = pCfg; ++ u16 u16Temp; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate,&u16Temp,&u16Temp)) ++ { ++ pLpllCfg->u32RoundRate = pLpllCfg->u32Rate; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ if(pLpllCfg->u32Rateu32RoundRate = DATA_LANE_12_5MHZ; ++ } ++ else ++ { ++ pLpllCfg->u32RoundRate = DATA_LANE_1500MHZ; ++ } ++ } ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pLpllCfg->bEn = (R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address))&camclk_BIT13)>>13; ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkSetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address), pLpllCfg->bEn ? camclk_BIT13 : 0 , camclk_BIT13); ++ bLook = pLpllCfg->bEn; ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetMiupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pMiupllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_miupll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pMiupllCfg->u32Rate = (u32)CamOsMathDivU64((u64)stRateCfg.u32Freq * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF), (u64)((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2), NULL); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetDdrpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pDdrpllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_ddrpll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pDdrpllCfg->u32Rate = (u32)CamOsMathDivU64(((u64)stRateCfg.u32Freq * 4 * 4) << 19, (u64)((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF)), NULL); ++ ++ return Ret; ++} ++ ++static void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++CAMCLK_RET_e HalCamClkSetCpupllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pCpupllCfg = pCfg; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //CamOsPrintf("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (pCpupllCfg->u32Rate >= 800000000) ++ post_div = 2; ++ else if (pCpupllCfg->u32Rate >= 400000000) ++ post_div = 4; ++ else if (pCpupllCfg->u32Rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, (pCpupllCfg->u32Rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pCpupllCfg = pCfg; ++ u32 lpf_value; ++ u32 post_div; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ //CamOsPrintf("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ pCpupllCfg->u32Rate = (div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ //CamOsPrintf("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", pCpupllCfg->u32Rate, pCpupllCfg->u32ParentRate); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pCpupllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pCpupllCfg->u32Rate < 100000000) // 100MHz ++ { ++ pCpupllCfg->u32RoundRate = 100000000; ++ } ++ else if(pCpupllCfg->u32Rate > 1400000000) // 1.4GHz ++ { ++ pCpupllCfg->u32RoundRate = 1400000000; ++ } ++ else ++ { ++ pCpupllCfg->u32RoundRate = pCpupllCfg->u32Rate; ++ } ++ ++ return Ret; ++} ++ ++HalCamClkAdjOps_t gMiupllOps={0,0,0,HalCamClkGetMiupllRate,0,0,0}; ++HalCamClkAdjOps_t gDdrpllOps={0,0,0,HalCamClkGetDdrpllRate,0,0,0}; ++HalCamClkAdjOps_t gLpllOps={0,0,HalCamClkSetLpllRate,HalCamClkGetLpllRate,HalCamClkGetLpllRoundRate,HalCamClkSetLpllOnOff,HalCamClkGetLpllOnOff}; ++HalCamClkAdjOps_t gCpupllOps={0,0,HalCamClkSetCpupllRate,HalCamClkGetCpupllRate,HalCamClkGetCpupllRoundRate,0,0}; ++HalCamClkAdjOps_t gFuart0Ops={0,0,0,0,0,0,0}; ++HalCamClkAdjOps_t gCsi2Ops={0,0,0,0,0,0,0}; ++#undef HAL_CAMCLKTBL_LPLL_C +diff --git a/drivers/sstar/camclk/hal/infinity6b0/src/hal_camclk_tbl.c b/drivers/sstar/camclk/hal/infinity6b0/src/hal_camclk_tbl.c +new file mode 100644 +index 000000000000..6967c3b755ec +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6b0/src/hal_camclk_tbl.c +@@ -0,0 +1,210 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_C ++#include "hal_camclk_if.h" ++#include "hal_camclk_complex.h" ++#include "reg_clks.h" ++#include "hal_camclk_util.h" ++ ++const HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX] = ++{ ++ {HAL_CAMCLK_SRC_CLK_VOID, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_480m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_432m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_345m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={345000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll_384m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,5,4}}, ++ {HAL_CAMCLK_SRC_CLK_upll_320m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_upll,3,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={288000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_240m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={216000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,5,2}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_172m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={172800000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi,3,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={123400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={86400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_123m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_192m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div5, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,5,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={12000000}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div40, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,40,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div64, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,64,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div128, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,128,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_24m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={24000000}}, ++ {HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_lpll_clk,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_armpll_37p125m, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_432m,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_top, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi0,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_vhe_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu_pm,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_isp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_isp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk2_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk2,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_sdio_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_sdio,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_pad2isp_sr_pclk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_ccir_in_clk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_eth_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_rmii_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ff, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_dig, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_xd2miu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_urdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_bdma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_mfeh, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_mfe, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_jpe1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_jpe0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_bach, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_file, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_uhc0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_emac, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_cmdq, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_dnr, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_rot, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_dma, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_isp_sta, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_gop, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_dnr, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_dnr_sad, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_crop, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_snp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_snpi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc1_dbg, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc2_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc2_snpi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc3_frm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_fcie, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sdio, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_ive, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_sc_gp_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_top,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_nogating, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mipi_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_mcu_if, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_ddrpll_clk,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_axi2x, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu2x_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_tck_buf,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_imi, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop1, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_gop2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk2_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={144000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_144m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_144m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div12, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,12,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_rtc_32k,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_live_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_24m,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_pm, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m, &gMiupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_ddrpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_ddr_syn,&gDdrpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gLpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_cpupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gCpupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_utmi, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_out, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_fuart0_synth_in,&gFuart0Ops}}, ++ {HAL_CAMCLK_SRC_CLK_csi2_mac_p, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_csi_mac,&gCsi2Ops}}, ++ {HAL_CAMCLK_SRC_CLK_miu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_ddrpll_clk,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_miupll_clk,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_MIU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ddr_syn, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DDR_SYN_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_rec, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div64,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div128},REG_CKG_MIU_REC_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_MCU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_riubrdg, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mcu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RIUBRDG_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_bdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_BDMA_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_spi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4},REG_CKG_SPI_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_uart0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_in, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FUART0_SYNTH_IN_BASE,camclk_BIT4,0,2,6,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fuart0_synth_out},REG_CKG_FUART_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mspi0_p,(u8)HAL_CAMCLK_SRC_CLK_mspi1_p},REG_CKG_MSPI_BASE,camclk_BIT12,0,1,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_pwr_ctl, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PWR_CTL_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_live, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_sr_mclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk_div8,(u8)HAL_CAMCLK_SRC_CLK_armpll_37p125m},REG_CKG_SR_MCLK_BASE,camclk_BIT8,0,4,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_vhe_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_VHE_GP_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_vhe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_345m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_VHE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_vhe_vpu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_345m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_VHE_VPU_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_SC_GP_BASE,camclk_BIT4,0,2,6,1}}, ++ {HAL_CAMCLK_SRC_CLK_bist_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_SC_GP_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_ahb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan},REG_CKG_EMAC_AHB_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_jpe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_JPE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_aesdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_AESDMA_BASE,camclk_BIT0,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sdio, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SDIO_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sd, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SD_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_isp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m},REG_CKG_ISP_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m},REG_CKG_FCLK1_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_fclk2, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FCLK2_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_odclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk},REG_CKG_ODCLK_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_dip, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DIP_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ive, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m},REG_CKG_IVE_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_nlm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_fclk1_p},REG_CKG_NLM_BASE,camclk_BIT8,0,1,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_TX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_RX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_TX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_RX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_hemcu_216m, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m},REG_CKG_HEMCU_216M_BASE,camclk_BIT0,0,0,0,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mac_lptx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MAC_LPTX_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ns, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_MCU_PM_BASE,camclk_BIT0,camclk_BIT7,4,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_144m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m},REG_CKG_SPI_PM_BASE,camclk_BIT8,camclk_BIT14,4,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_pm_sleep, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_PM_SLEEP_BASE,0,0,3,12,0}}, ++ {HAL_CAMCLK_SRC_CLK_sar, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_SAR_BASE,camclk_BIT5,0,3,7,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RTC_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ir, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div12,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4},REG_CKG_IR_BASE,camclk_BIT5,0,3,7,1}}, ++}; ++ ++#undef HAL_CAMCLKTBL_C +diff --git a/drivers/sstar/camclk/hal/infinity6e/camclk_hal.mak b/drivers/sstar/camclk/hal/infinity6e/camclk_hal.mak +new file mode 100644 +index 000000000000..64e6264a364d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/camclk_hal.mak +@@ -0,0 +1,20 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++ ++PATH_C += \ ++ $(PATH_camclk_hal)/src ++ ++PATH_H += $(PATH_camclk_hal)/common\ ++ $(PATH_camclk_hal)/inc\ ++ $(PATH_camclk_hal)/pub\ ++ $(PATH_camclk)/inc\ ++ $(PATH_camclk)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_cam_os_wrapper)/inc\ ++ ++SRC_C_LIST += hal_camclk_complex.c\ ++ hal_camclk_tbl.c ++ +diff --git a/drivers/sstar/camclk/hal/infinity6e/inc/camclk_id.h b/drivers/sstar/camclk/hal/infinity6e/inc/camclk_id.h +new file mode 100644 +index 000000000000..1601199e1276 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/inc/camclk_id.h +@@ -0,0 +1,170 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_ID_H__ ++#define __CAMCLK_ID_H__ ++typedef enum ++{ ++ HAL_CAMCLK_SRC_CLK_VOID, ++ HAL_CAMCLK_SRC_CLK_utmi_480m, ++ HAL_CAMCLK_SRC_CLK_mpll_432m, ++ HAL_CAMCLK_SRC_CLK_upll_384m, ++ HAL_CAMCLK_SRC_CLK_mpll_345m, ++ HAL_CAMCLK_SRC_CLK_upll_320m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m, ++ HAL_CAMCLK_SRC_CLK_utmi_240m, ++ HAL_CAMCLK_SRC_CLK_mpll_216m, ++ HAL_CAMCLK_SRC_CLK_utmi_192m, ++ HAL_CAMCLK_SRC_CLK_mpll_172m, ++ HAL_CAMCLK_SRC_CLK_utmi_160m, ++ HAL_CAMCLK_SRC_CLK_mpll_123m, ++ HAL_CAMCLK_SRC_CLK_mpll_86m, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_288m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_216m_div8, ++ HAL_CAMCLK_SRC_CLK_mpll_123m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div2, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div4, ++ HAL_CAMCLK_SRC_CLK_mpll_86m_div16, ++ HAL_CAMCLK_SRC_CLK_utmi_192m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div4, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div5, ++ HAL_CAMCLK_SRC_CLK_utmi_160m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div2, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div4, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div8, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div16, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div40, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div64, ++ HAL_CAMCLK_SRC_CLK_xtali_12m_div128, ++ HAL_CAMCLK_SRC_CLK_xtali_24m, ++ HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, ++ HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_miupll_clk, ++ HAL_CAMCLK_SRC_CLK_ddrpll_clk, ++ HAL_CAMCLK_SRC_CLK_lpll_clk, ++ HAL_CAMCLK_SRC_CLK_ven_pll, ++ HAL_CAMCLK_SRC_CLK_ven_pll_div6, ++ HAL_CAMCLK_SRC_CLK_lpll_div2, ++ HAL_CAMCLK_SRC_CLK_lpll_div4, ++ HAL_CAMCLK_SRC_CLK_lpll_div8, ++ HAL_CAMCLK_SRC_CLK_armpll_37p125m, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_in, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_top, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, ++ HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_out, ++ HAL_CAMCLK_SRC_CLK_miu_p, ++ HAL_CAMCLK_SRC_CLK_mspi0_p, ++ HAL_CAMCLK_SRC_CLK_mspi1_p, ++ HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, ++ HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, ++ HAL_CAMCLK_SRC_CLK_mcu_p, ++ HAL_CAMCLK_SRC_CLK_fclk1_p, ++ HAL_CAMCLK_SRC_CLK_sdio_p, ++ HAL_CAMCLK_SRC_CLK_tck_buf, ++ HAL_CAMCLK_SRC_CLK_eth_buf, ++ HAL_CAMCLK_SRC_CLK_rmii_buf, ++ HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, ++ HAL_CAMCLK_SRC_CLK_gop0, ++ HAL_CAMCLK_SRC_CLK_rtc_32k, ++ HAL_CAMCLK_SRC_CLK_fro, ++ HAL_CAMCLK_SRC_CLK_fro_div2, ++ HAL_CAMCLK_SRC_CLK_fro_div8, ++ HAL_CAMCLK_SRC_CLK_fro_div16, ++ HAL_CAMCLK_SRC_CLK_cpupll_clk, ++ HAL_CAMCLK_SRC_CLK_utmi, ++ HAL_CAMCLK_SRC_CLK_bach, ++ HAL_CAMCLK_SRC_CLK_miu, ++ HAL_CAMCLK_SRC_CLK_miu_boot, ++ HAL_CAMCLK_SRC_CLK_ddr_syn, ++ HAL_CAMCLK_SRC_CLK_miu_rec, ++ HAL_CAMCLK_SRC_CLK_mcu, ++ HAL_CAMCLK_SRC_CLK_riubrdg, ++ HAL_CAMCLK_SRC_CLK_bdma, ++ HAL_CAMCLK_SRC_CLK_spi_arb, ++ HAL_CAMCLK_SRC_CLK_spi_flash, ++ HAL_CAMCLK_SRC_CLK_pwm, ++ HAL_CAMCLK_SRC_CLK_uart0, ++ HAL_CAMCLK_SRC_CLK_uart1, ++ HAL_CAMCLK_SRC_CLK_fuart0_synth_in, ++ HAL_CAMCLK_SRC_CLK_fuart, ++ HAL_CAMCLK_SRC_CLK_mspi0, ++ HAL_CAMCLK_SRC_CLK_mspi1, ++ HAL_CAMCLK_SRC_CLK_mspi, ++ HAL_CAMCLK_SRC_CLK_miic0, ++ HAL_CAMCLK_SRC_CLK_miic1, ++ HAL_CAMCLK_SRC_CLK_miic2, ++ HAL_CAMCLK_SRC_CLK_bist, ++ HAL_CAMCLK_SRC_CLK_pwr_ctl, ++ HAL_CAMCLK_SRC_CLK_xtali, ++ HAL_CAMCLK_SRC_CLK_live, ++ HAL_CAMCLK_SRC_CLK_sr00_mclk, ++ HAL_CAMCLK_SRC_CLK_sr01_mclk, ++ HAL_CAMCLK_SRC_CLK_sr1_mclk, ++ HAL_CAMCLK_SRC_CLK_bist_pm, ++ HAL_CAMCLK_SRC_CLK_bist_ipu_gp, ++ HAL_CAMCLK_SRC_CLK_ipu, ++ HAL_CAMCLK_SRC_CLK_ipuff, ++ HAL_CAMCLK_SRC_CLK_bist_usb30_gp, ++ HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_m00, ++ HAL_CAMCLK_SRC_CLK_csi_mac_top_i_m00, ++ HAL_CAMCLK_SRC_CLK_ns_top_i_m00, ++ HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_m01, ++ HAL_CAMCLK_SRC_CLK_csi_mac_top_i_m01, ++ HAL_CAMCLK_SRC_CLK_ns_top_i_m01, ++ HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_m1, ++ HAL_CAMCLK_SRC_CLK_csi_mac_top_i_m1, ++ HAL_CAMCLK_SRC_CLK_ns_top_i_m1, ++ HAL_CAMCLK_SRC_CLK_mipi1_tx_csi, ++ HAL_CAMCLK_SRC_CLK_bist_vhe_gp, ++ HAL_CAMCLK_SRC_CLK_vhe, ++ HAL_CAMCLK_SRC_CLK_mfe, ++ HAL_CAMCLK_SRC_CLK_xtali_sc_gp, ++ HAL_CAMCLK_SRC_CLK_bist_sc_gp, ++ HAL_CAMCLK_SRC_CLK_emac_ahb, ++ HAL_CAMCLK_SRC_CLK_jpe, ++ HAL_CAMCLK_SRC_CLK_aesdma, ++ HAL_CAMCLK_SRC_CLK_sdio, ++ HAL_CAMCLK_SRC_CLK_sd, ++ HAL_CAMCLK_SRC_CLK_ecc, ++ HAL_CAMCLK_SRC_CLK_isp, ++ HAL_CAMCLK_SRC_CLK_fclk1, ++ HAL_CAMCLK_SRC_CLK_odclk, ++ HAL_CAMCLK_SRC_CLK_dip, ++ HAL_CAMCLK_SRC_CLK_emac_tx, ++ HAL_CAMCLK_SRC_CLK_emac_rx, ++ HAL_CAMCLK_SRC_CLK_emac_tx_ref, ++ HAL_CAMCLK_SRC_CLK_emac_rx_ref, ++ HAL_CAMCLK_SRC_CLK_ive, ++ HAL_CAMCLK_SRC_CLK_ldcfeye, ++ HAL_CAMCLK_SRC_CLK_live_pm, ++ HAL_CAMCLK_SRC_CLK_mcu_pm_p1, ++ HAL_CAMCLK_SRC_CLK_spi_pm, ++ HAL_CAMCLK_SRC_CLK_miic_pm, ++ HAL_CAMCLK_SRC_CLK_pm_sleep, ++ HAL_CAMCLK_SRC_CLK_rtc, ++ HAL_CAMCLK_SRC_CLK_sar, ++ HAL_CAMCLK_SRC_CLK_pir, ++ HAL_CAMCLK_SRC_CLK_pm_uart, ++ HAL_CAMCLK_SRC_Id_MAX ++} HalCamClkSrcId_e; ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk.h b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk.h +new file mode 100644 +index 000000000000..dd27fd24a52d +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk.h +@@ -0,0 +1,26 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_H__ ++#define __HAL_CAMCLK_H__ ++#include "drv_camclk_DataType.h" ++#include "hal_camclk_st.h" ++#include "hal_camclk_if_st.h" ++ ++const extern HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX]; ++extern HalCamClkTopClk_t *gCamClkTopCurrent; ++extern u16 gu16HandlerCnt; ++extern struct CamOsListHead_t gstClkListHead; ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_complex.h b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_complex.h +new file mode 100644 +index 000000000000..1e7f1aa518bc +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_complex.h +@@ -0,0 +1,20 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include "hal_camclk_if_st.h" ++extern HalCamClkAdjOps_t gMiupllOps; ++extern HalCamClkAdjOps_t gDdrpllOps; ++extern HalCamClkAdjOps_t gLpllOps; ++extern HalCamClkAdjOps_t gVenOps; ++extern HalCamClkAdjOps_t gCpupllOps; +diff --git a/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_lpll_tbl.h b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_lpll_tbl.h +new file mode 100644 +index 000000000000..47f5bdc4b74f +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_lpll_tbl.h +@@ -0,0 +1,75 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_LPLL_TBL_H_ ++#define _CAMCLK_LPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define HAL_CAMCLK_LPLL_REG_NUM 6 ++ ++#define DATA_LANE_9MHZ (9000000) ++#define DATA_LANE_9_5MHZ (9500000) ++#define DATA_LANE_12_5MHZ (12500000) ++#define DATA_LANE_25MHZ (25000000) ++#define DATA_LANE_50MHZ (50000000) ++#define DATA_LANE_100MHZ (100000000) ++#define DATA_LANE_187_5MHZ (187500000) ++#define DATA_LANE_200MHZ (200000000) ++#define DATA_LANE_400MHZ (400000000) ++#define DATA_LANE_800MHZ (800000000) ++#define DATA_LANE_1500MHZ (1500000000) ++ ++#define IS_DATA_LANE_LESS_100M(bps) ( bps <= DATA_LANE_100MHZ ) ++#define IS_DATA_LANE_BPS_100M_TO_200M(bps) ( (bps > DATA_LANE_100MHZ) && (bps <= DATA_LANE_200MHZ ) ) ++#define IS_DATA_LANE_BPS_200M_TO_400M(bps) ( (bps > DATA_LANE_200MHZ) && (bps <= DATA_LANE_400MHZ ) ) ++#define IS_DATA_LANE_BPS_400M_TO_800M(bps) ( (bps > DATA_LANE_400MHZ) && (bps <= DATA_LANE_800MHZ ) ) ++#define IS_DATA_LANE_BPS_800M_TO_15000M(bps) ( (bps > DATA_LANE_800MHZ) && (bps <= DATA_LANE_1500MHZ ) ) ++ ++#define IS_DATA_LANE_LESS_9M(bps) ( bps < DATA_LANE_9MHZ ) ++#define IS_DATA_LANE_BPS_9M_TO_9_5M(bps) ( (bps >= DATA_LANE_9MHZ) && (bps < DATA_LANE_9_5MHZ ) ) ++#define IS_DATA_LANE_BPS_12_5M_TO_25M(bps) ( (bps > DATA_LANE_12_5MHZ) && (bps <= DATA_LANE_25MHZ ) ) ++#define IS_DATA_LANE_BPS_25M_TO_50M(bps) ( (bps > DATA_LANE_25MHZ) && (bps <= DATA_LANE_50MHZ ) ) ++#define IS_DATA_LANE_BPS_50M_TO_100M(bps) ( (bps > DATA_LANE_50MHZ) && (bps <= DATA_LANE_100MHZ ) ) ++#define REG_LPLL_BASE 0x103300UL ++#define REG_LPLL_48_L (REG_LPLL_BASE + 0x90) ++#define REG_LPLL_48_H (REG_LPLL_BASE + 0x91) ++#define REG_LPLL_49_L (REG_LPLL_BASE + 0x92) ++#define REG_LPLL_49_H (REG_LPLL_BASE + 0x93) ++ ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ, //0 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ, //1 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ, //2 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ, //3 ++ E_HAL_CAMCLK_SUPPORTED_LPLL_MAX, //4 ++} HalCamClkLpllType_e; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 address; ++ u16 value; ++}HalCamClkLpllTbl_t; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_st.h b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_st.h +new file mode 100644 +index 000000000000..ca2c85a0aeb5 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_st.h +@@ -0,0 +1,38 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __HAL_CAMCLK_ST_H__ ++#define __HAL_CAMCLK_ST_H__ ++ ++ ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkSetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32ParentRate; ++}HalCamClkGetComplexRate_t; ++typedef struct ++{ ++ u32 u32Rate; ++ u32 u32RoundRate; ++}HalCamClkGetComplexRoundRate_t; ++typedef struct ++{ ++ u8 bEn; ++}HalCamClkComplexOnOff_t; ++#endif /* MHAL_DIP_H */ +diff --git a/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_venpll.h b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_venpll.h +new file mode 100644 +index 000000000000..dd3137c74a6c +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/inc/hal_camclk_venpll.h +@@ -0,0 +1,33 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef _CAMCLK_VENPLL_TBL_H_ ++#define _CAMCLK_VENPLL_TBL_H_ ++#include "drv_camclk_DataType.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define REG_VENPLL_BASE 0x103600UL ++#define REG_VENPLL_01_L (REG_VENPLL_BASE + 0x02) ++#define REG_VENPLL_03_L (REG_VENPLL_BASE + 0x06) ++//------------------------------------------------------------------------------------------------- ++// structure & Enum ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++#endif //_CAMCLK_VENPLL_TBL_H_ +diff --git a/drivers/sstar/camclk/hal/infinity6e/pub/camclk.h b/drivers/sstar/camclk/hal/infinity6e/pub/camclk.h +new file mode 100644 +index 000000000000..fdfd17ec4551 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/pub/camclk.h +@@ -0,0 +1,167 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_upll_384m 3 ++#define CAMCLK_mpll_345m 4 ++#define CAMCLK_upll_320m 5 ++#define CAMCLK_mpll_288m 6 ++#define CAMCLK_utmi_240m 7 ++#define CAMCLK_mpll_216m 8 ++#define CAMCLK_utmi_192m 9 ++#define CAMCLK_mpll_172m 10 ++#define CAMCLK_utmi_160m 11 ++#define CAMCLK_mpll_123m 12 ++#define CAMCLK_mpll_86m 13 ++#define CAMCLK_mpll_288m_div2 14 ++#define CAMCLK_mpll_288m_div4 15 ++#define CAMCLK_mpll_288m_div8 16 ++#define CAMCLK_mpll_216m_div2 17 ++#define CAMCLK_mpll_216m_div4 18 ++#define CAMCLK_mpll_216m_div8 19 ++#define CAMCLK_mpll_123m_div2 20 ++#define CAMCLK_mpll_86m_div2 21 ++#define CAMCLK_mpll_86m_div4 22 ++#define CAMCLK_mpll_86m_div16 23 ++#define CAMCLK_utmi_192m_div4 24 ++#define CAMCLK_utmi_160m_div4 25 ++#define CAMCLK_utmi_160m_div5 26 ++#define CAMCLK_utmi_160m_div8 27 ++#define CAMCLK_xtali_12m 28 ++#define CAMCLK_xtali_12m_div2 29 ++#define CAMCLK_xtali_12m_div4 30 ++#define CAMCLK_xtali_12m_div8 31 ++#define CAMCLK_xtali_12m_div16 32 ++#define CAMCLK_xtali_12m_div40 33 ++#define CAMCLK_xtali_12m_div64 34 ++#define CAMCLK_xtali_12m_div128 35 ++#define CAMCLK_xtali_24m 36 ++#define CAMCLK_RTC_CLK_32K 37 ++#define CAMCLK_pm_riu_w_clk_in 38 ++#define CAMCLK_miupll_clk 39 ++#define CAMCLK_ddrpll_clk 40 ++#define CAMCLK_lpll_clk 41 ++#define CAMCLK_ven_pll 42 ++#define CAMCLK_ven_pll_div6 43 ++#define CAMCLK_lpll_div2 44 ++#define CAMCLK_lpll_div4 45 ++#define CAMCLK_lpll_div8 46 ++#define CAMCLK_armpll_37p125m 47 ++#define CAMCLK_riu_w_clk_in 48 ++#define CAMCLK_riu_w_clk_top 49 ++#define CAMCLK_riu_w_clk_sc_gp 50 ++#define CAMCLK_riu_w_clk_vhe_gp 51 ++#define CAMCLK_riu_w_clk_hemcu_gp 52 ++#define CAMCLK_riu_w_clk_mipi_if_gp 53 ++#define CAMCLK_riu_w_clk_mcu_if_gp 54 ++#define CAMCLK_fuart0_synth_out 55 ++#define CAMCLK_miu_p 56 ++#define CAMCLK_mspi0_p 57 ++#define CAMCLK_mspi1_p 58 ++#define CAMCLK_miu_vhe_gp_p 59 ++#define CAMCLK_miu_sc_gp_p 60 ++#define CAMCLK_mcu_p 61 ++#define CAMCLK_fclk1_p 62 ++#define CAMCLK_sdio_p 63 ++#define CAMCLK_tck_buf 64 ++#define CAMCLK_eth_buf 65 ++#define CAMCLK_rmii_buf 66 ++#define CAMCLK_emac_testrx125_in_lan 67 ++#define CAMCLK_gop0 68 ++#define CAMCLK_rtc_32k 69 ++#define CAMCLK_fro 70 ++#define CAMCLK_fro_div2 71 ++#define CAMCLK_fro_div8 72 ++#define CAMCLK_fro_div16 73 ++#define CAMCLK_cpupll_clk 74 ++#define CAMCLK_utmi 75 ++#define CAMCLK_bach 76 ++#define CAMCLK_miu 77 ++#define CAMCLK_miu_boot 78 ++#define CAMCLK_ddr_syn 79 ++#define CAMCLK_miu_rec 80 ++#define CAMCLK_mcu 81 ++#define CAMCLK_riubrdg 82 ++#define CAMCLK_bdma 83 ++#define CAMCLK_spi_arb 84 ++#define CAMCLK_spi_flash 85 ++#define CAMCLK_pwm 86 ++#define CAMCLK_uart0 87 ++#define CAMCLK_uart1 88 ++#define CAMCLK_fuart0_synth_in 89 ++#define CAMCLK_fuart 90 ++#define CAMCLK_mspi0 91 ++#define CAMCLK_mspi1 92 ++#define CAMCLK_mspi 93 ++#define CAMCLK_miic0 94 ++#define CAMCLK_miic1 95 ++#define CAMCLK_miic2 96 ++#define CAMCLK_bist 97 ++#define CAMCLK_pwr_ctl 98 ++#define CAMCLK_xtali 99 ++#define CAMCLK_live 100 ++#define CAMCLK_sr00_mclk 101 ++#define CAMCLK_sr01_mclk 102 ++#define CAMCLK_sr1_mclk 103 ++#define CAMCLK_bist_pm 104 ++#define CAMCLK_bist_ipu_gp 105 ++#define CAMCLK_ipu 106 ++#define CAMCLK_ipuff 107 ++#define CAMCLK_bist_usb30_gp 108 ++#define CAMCLK_csi_mac_lptx_top_i_m00 109 ++#define CAMCLK_csi_mac_top_i_m00 110 ++#define CAMCLK_ns_top_i_m00 111 ++#define CAMCLK_csi_mac_lptx_top_i_m01 112 ++#define CAMCLK_csi_mac_top_i_m01 113 ++#define CAMCLK_ns_top_i_m01 114 ++#define CAMCLK_csi_mac_lptx_top_i_m1 115 ++#define CAMCLK_csi_mac_top_i_m1 116 ++#define CAMCLK_ns_top_i_m1 117 ++#define CAMCLK_mipi1_tx_csi 118 ++#define CAMCLK_bist_vhe_gp 119 ++#define CAMCLK_vhe 120 ++#define CAMCLK_mfe 121 ++#define CAMCLK_xtali_sc_gp 122 ++#define CAMCLK_bist_sc_gp 123 ++#define CAMCLK_emac_ahb 124 ++#define CAMCLK_jpe 125 ++#define CAMCLK_aesdma 126 ++#define CAMCLK_sdio 127 ++#define CAMCLK_sd 128 ++#define CAMCLK_ecc 129 ++#define CAMCLK_isp 130 ++#define CAMCLK_fclk1 131 ++#define CAMCLK_odclk 132 ++#define CAMCLK_dip 133 ++#define CAMCLK_emac_tx 134 ++#define CAMCLK_emac_rx 135 ++#define CAMCLK_emac_tx_ref 136 ++#define CAMCLK_emac_rx_ref 137 ++#define CAMCLK_ive 138 ++#define CAMCLK_ldcfeye 139 ++#define CAMCLK_live_pm 140 ++#define CAMCLK_mcu_pm_p1 141 ++#define CAMCLK_spi_pm 142 ++#define CAMCLK_miic_pm 143 ++#define CAMCLK_pm_sleep 144 ++#define CAMCLK_rtc 145 ++#define CAMCLK_sar 146 ++#define CAMCLK_pir 147 ++#define CAMCLK_pm_uart 148 ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6e/pub/reg_clks.h b/drivers/sstar/camclk/hal/infinity6e/pub/reg_clks.h +new file mode 100644 +index 000000000000..91aa755ca250 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/pub/reg_clks.h +@@ -0,0 +1,591 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5.1 */ ++/* CLK FILENAME: I6e/iNfinity6e_Clock_Table_0903.xls */ ++/* REG FILENAME: I6e/iNfinity6e_reg_CLKGEN.xls, I6e/iNfinity6e_reg_pm_sleep.xls, I6e/iNfinity6e_reg_block.xls, I6e/iNfinity6e_reg_chiptop.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++#define REG_CHIPTOP_BASE 0x1F203C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CHIPTOP_DUMMY_0_BASE (REG_CHIPTOP_BASE+0x20*4) ++#define REG_CHIPTOP_DUMMY_0_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_1_BASE (REG_CHIPTOP_BASE+0x21*4) ++#define REG_CHIPTOP_DUMMY_1_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_2_BASE (REG_CHIPTOP_BASE+0x22*4) ++#define REG_CHIPTOP_DUMMY_2_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_3_BASE (REG_CHIPTOP_BASE+0x23*4) ++#define REG_CHIPTOP_DUMMY_3_OFFSET (0) ++ ++#define REG_CHIPTOP_RESERVED_BASE (REG_CHIPTOP_BASE+0x7B*4) ++#define REG_CHIPTOP_RESERVED_OFFSET (0) ++ ++#define REG_CKG_BT656_0_FIXME_BASE (REG_SC_GP_CTRL_BASE+0x27*4) ++#define REG_CKG_BT656_0_FIXME_OFFSET (0) ++ ++#define REG_CKG_BT656_1_FIXME_BASE (REG_SC_GP_CTRL_BASE+0x27*4) ++#define REG_CKG_BT656_1_FIXME_OFFSET (8) ++ ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_CKG_ODCLK_FIXME_BASE (REG_SC_GP_CTRL_BASE+0x24*4) ++#define REG_CKG_ODCLK_FIXME_OFFSET (8) ++ ++#define REG_CKG_SD_FIXME2_BASE (REG_SC_GP_CTRL_BASE+0x25*4) ++#define REG_CKG_SD_FIXME2_OFFSET (0) ++ ++#define REG_CKG_SNR0_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR0_OFFSET (0) ++ ++#define REG_CKG_SNR1_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR1_OFFSET (8) ++ ++#define REG_CKG_SNR2_BASE (REG_SC_GP_CTRL_BASE+0x29*4) ++#define REG_CKG_SNR2_OFFSET (0) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++#define REG_SRAM_SD_EN_BASE (REG_SC_GP_CTRL_BASE+0x10*4) ++#define REG_SRAM_SD_EN_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_LIVE_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x34*4) ++#define REG_CKG_LIVE_PM_OFFSET (0) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (7) ++ ++#define REG_CKG_MCU_PM_P1_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_P1_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PIR_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_PIR_OFFSET (8) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PM_UART_BASE (REG_PM_SLEEP_CKG_BASE+0x25*4) ++#define REG_CKG_PM_UART_OFFSET (0) ++ ++#define REG_CKG_PWM_FIXME_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_FIXME_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_FIXME_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_FIXME_OFFSET (10) ++ ++#define REG_CKG_SPI_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_384M_2BACH_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_384M_2BACH_OFFSET (7) ++ ++#define REG_CKG_432M_2BACH_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_432M_2BACH_OFFSET (6) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_IPU_GP_BASE (REG_CKG_BASE+0x05*4) ++#define REG_CKG_BIST_IPU_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_USB30_GP_BASE (REG_CKG_BASE+0x05*4) ++#define REG_CKG_BIST_USB30_GP_OFFSET (8) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_BT656_0_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_BT656_0_OFFSET (0) ++ ++#define REG_CKG_BT656_1_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_BT656_1_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M00_BASE (REG_CKG_BASE+0x58*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M00_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M01_BASE (REG_CKG_BASE+0x59*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M01_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M1_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M1_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_TOP_I_M00_BASE (REG_CKG_BASE+0x58*4) ++#define REG_CKG_CSI_MAC_TOP_I_M00_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_TOP_I_M01_BASE (REG_CKG_BASE+0x5A*4) ++#define REG_CKG_CSI_MAC_TOP_I_M01_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_TOP_I_M1_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_CSI_MAC_TOP_I_M1_OFFSET (8) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_BACH_384M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_BACH_384M_OFFSET (7) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_IPU_BASE (REG_CKG_BASE+0x50*4) ++#define REG_CKG_IPU_OFFSET (0) ++ ++#define REG_CKG_IPUFF_BASE (REG_CKG_BASE+0x50*4) ++#define REG_CKG_IPUFF_OFFSET (8) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_JPE_GATE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_GATE_OFFSET (7) ++ ++#define REG_CKG_LDCFEYE_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_LDCFEYE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIIC2_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC2_OFFSET (12) ++ ++#define REG_CKG_MIPI1_TX_CSI_BASE (REG_CKG_BASE+0x5C*4) ++#define REG_CKG_MIPI1_TX_CSI_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_NS_TOP_I_M00_BASE (REG_CKG_BASE+0x59*4) ++#define REG_CKG_NS_TOP_I_M00_OFFSET (0) ++ ++#define REG_CKG_NS_TOP_I_M01_BASE (REG_CKG_BASE+0x5A*4) ++#define REG_CKG_NS_TOP_I_M01_OFFSET (8) ++ ++#define REG_CKG_NS_TOP_I_M1_BASE (REG_CKG_BASE+0x5C*4) ++#define REG_CKG_NS_TOP_I_M1_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWM_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_PWM_OFFSET (8) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SD_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_ARB_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_ARB_OFFSET (0) ++ ++#define REG_CKG_SPI_FLASH_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_SPI_FLASH_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR00_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR00_MCLK_OFFSET (8) ++ ++#define REG_CKG_SR01_MCLK_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_SR01_MCLK_OFFSET (0) ++ ++#define REG_CKG_SR1_MCLK_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_SR1_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_VHE_GATE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_GATE_OFFSET (7) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x35*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/camclk/hal/infinity6e/src/hal_camclk_complex.c b/drivers/sstar/camclk/hal/infinity6e/src/hal_camclk_complex.c +new file mode 100644 +index 000000000000..ebc8c5f2a7b5 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/src/hal_camclk_complex.c +@@ -0,0 +1,540 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_LPLL_C ++#include "camclk_dbg.h" ++#include "hal_camclk_if_st.h" ++#include "hal_camclk_lpll_tbl.h" ++#include "hal_camclk_venpll.h" ++#include "hal_camclk_util.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "registers.h" ++#include "ms_platform.h" ++ ++ ++HalCamClkLpllTbl_t gCamClkLPLLSettingTBL[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX][HAL_CAMCLK_LPLL_REG_NUM]= ++{ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0041}, ++ {0x103386, 0x0000}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0042}, ++ {0x103386, 0x0001}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0043}, ++ {0x103386, 0x0002}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++ ++ { //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++ //Address,Value ++ {0x103380, 0x0201}, ++ {0x103382, 0x0420}, ++ {0x103384, 0x0083}, ++ {0x103386, 0x0003}, ++ {0x103394, 0x0001}, ++ {0x103396, 0x0000}, ++ }, ++}; ++#define PLL_REG_GET(address) (0x1F000000 + ((address)<<1)) ++u16 u16LoopGain[E_HAL_CAMCLK_SUPPORTED_LPLL_MAX]= ++{ ++ 16, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_100TO187D5MHZ NO.0 ++ 8, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_50TO100MHZ NO.1 ++ 4, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_25TO50MHZ NO.2 ++ 2, //E_HAL_CAMCLK_SUPPORTED_LPLL_HS_CH_12D5TO25MHZ NO.3 ++}; ++u32 u16gLpllDiv = 8; ++u8 bLook = 0; ++void HalCamClkGetLpllIdxFromHw(u16 *pu16Idx) ++{ ++ u16 u16Val; ++ u8 idx; ++ u16Val = R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][2].address)); ++ for(idx =0 ;idx> 16); ++ W2BYTE(PLL_REG_GET(REG_LPLL_48_L), u16LpllSet_Lo); // @suppress("Symbol is not resolved") ++ W2BYTE(PLL_REG_GET(REG_LPLL_49_L), u16LpllSet_Hi); // @suppress("Symbol is not resolved") ++} ++void HalCamClkGetLpllSet(u32 *u32LpllSet) ++{ ++ u16 u16LpllSet_Lo, u16LpllSet_Hi; ++ ++ u16LpllSet_Lo = R2BYTE(PLL_REG_GET(REG_LPLL_48_L)); ++ u16LpllSet_Hi = R2BYTE(PLL_REG_GET(REG_LPLL_49_L)); ++ *u32LpllSet = (u16LpllSet_Lo | ((u32)u16LpllSet_Hi<<16)); ++} ++CAMCLK_RET_e HalCamClkSetLpllRate(void *pCfg) ++{ ++ u16 u16LpllIdx; ++ u16 u16Div; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ HalCamClkSetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ if(bLook) ++ { ++ Ret = CAMCLK_RET_FAIL; ++ CAMCLKERR("%s %d, LPLL Locked:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ else ++ { ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate, &u16LpllIdx, &u16Div)) ++ { ++ if(u16LpllIdx != E_HAL_CAMCLK_SUPPORTED_LPLL_MAX) ++ { ++ u16LoopGain = HalCamClkGetLpllGain(u16LpllIdx); ++ u64Dividen = (pLpllCfg->u32ParentRate); ++ u64Dividen = (u64)(u64Dividen * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16Div,NULL); ++ u32Divisor = pLpllCfg->u32Rate; ++ u32LplLSet = (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ CAMCLKDBG("[CAMCLK]%s %d:: Idx:%d, LoopGain:%d, LoopDiv:%d, dclk=%ld, Divden:0x%llx, Divisor:0x%lx, LpllSe:0x%lx\n", ++ __FUNCTION__, __LINE__, u16LpllIdx, ++ u16LoopGain, u16Div, pLpllCfg->u32Rate, ++ u64Dividen, u32Divisor, u32LplLSet); ++ ++ HalCamClkDumpLpllSetting(u16LpllIdx); ++ HalCamClkSetLpllSet(u32LplLSet); ++ u16gLpllDiv = u16Div; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ CAMCLKERR("%s %d, DCLK Out of Range:%ld\n", __FUNCTION__, __LINE__, pLpllCfg->u32Rate); ++ } ++ } ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u16 u16idx; ++ u16 u16LoopGain; ++ u32 u32LplLSet,u32Divisor; ++ u64 u64Dividen; ++ ++ HalCamClkGetLpllIdxFromHw(&u16idx); ++ u16LoopGain = HalCamClkGetLpllGain(u16idx); ++ HalCamClkGetLpllSet(&u32LplLSet); ++ u64Dividen = pLpllCfg->u32ParentRate; ++ u64Dividen = (u64)((u64Dividen) * (u32)524288 * (u32)u16LoopGain); ++ u64Dividen = CamOsMathDivU64(u64Dividen,u16gLpllDiv,NULL); ++ u32Divisor = u32LplLSet; ++ pLpllCfg->u32Rate= (u32)CamOsMathDivU64(u64Dividen,u32Divisor,NULL); ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pLpllCfg = pCfg; ++ u16 u16Temp; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(HalCamClkGetLpllIdx(pLpllCfg->u32Rate,&u16Temp,&u16Temp)) ++ { ++ pLpllCfg->u32RoundRate = pLpllCfg->u32Rate; ++ } ++ else ++ { ++ Ret = CAMCLK_RET_RATEERR; ++ if(pLpllCfg->u32Rateu32RoundRate = DATA_LANE_12_5MHZ; ++ } ++ else ++ { ++ pLpllCfg->u32RoundRate = DATA_LANE_1500MHZ; ++ } ++ } ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pLpllCfg->bEn = (R2BYTE(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address))&camclk_BIT13)>>13; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetLpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pLpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(gCamClkLPLLSettingTBL[0][0].address), pLpllCfg->bEn ? camclk_BIT13 : 0 , camclk_BIT13); ++ bLook = pLpllCfg->bEn; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetVenpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_01_L), pVenpllCfg->bEn ? 0 : camclk_BIT8 , camclk_BIT8); ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetVenpllOnOff(void *pCfg) ++{ ++ HalCamClkComplexOnOff_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pVenpllCfg->bEn = (R2BYTE(PLL_REG_GET(REG_VENPLL_01_L))&camclk_BIT8) ? 0 : 1; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetVenpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ pVenpllCfg->u32Rate = pVenpllCfg->u32ParentRate * RBYTE(PLL_REG_GET(REG_VENPLL_03_L)) / 2; ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkGetVenpllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pVenpllCfg->u32Rate <= 300000000) ++ { ++ pVenpllCfg->u32RoundRate = 300000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 312000000) ++ { ++ pVenpllCfg->u32RoundRate = 312000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 324000000) ++ { ++ pVenpllCfg->u32RoundRate = 324000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 336000000) ++ { ++ pVenpllCfg->u32RoundRate = 336000000; ++ } ++ else if(pVenpllCfg->u32Rate <= 348000000) ++ { ++ pVenpllCfg->u32RoundRate = 348000000; ++ } ++ else{ ++ pVenpllCfg->u32RoundRate = 348000000; ++ } ++ ++ return Ret; ++} ++CAMCLK_RET_e HalCamClkSetVenpllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pVenpllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ u32 val; ++ ++ if ( (pVenpllCfg->u32Rate == 348000000) || ++ (pVenpllCfg->u32Rate == 336000000) || ++ (pVenpllCfg->u32Rate == 324000000) || ++ (pVenpllCfg->u32Rate == 312000000) || ++ (pVenpllCfg->u32Rate == 300000000)) ++ { ++ val = pVenpllCfg->u32Rate * 2 / 24000000; ++ W2BYTEMSK(PLL_REG_GET(REG_VENPLL_03_L), val , 0xFF); ++ } ++ else ++ { ++ CAMCLKERR("\nunsupported venpll rate %lu\n\n", pVenpllCfg->u32Rate); ++ Ret = CAMCLK_RET_RATEERR; ++ } ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetMiupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pMiupllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_miupll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pMiupllCfg->u32Rate = (u32)CamOsMathDivU64((u64)stRateCfg.u32Freq * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF), (u64)((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2), NULL); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetDdrpllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pDdrpllCfg = pCfg; ++ DrvCamClkGetParent_t stParentCfg = {0}; ++ DrvCamClkGetRate_t stRateCfg = {0}; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ stParentCfg.u32Id = HAL_CAMCLK_SRC_CLK_ddrpll_clk; ++ DrvCamClkImplGetParent(&stParentCfg); ++ stRateCfg.u32Id = stParentCfg.u32ParentId; ++ DrvCamClkImplGetRate(&stRateCfg); ++ pDdrpllCfg->u32Rate = (u32)CamOsMathDivU64(((u64)stRateCfg.u32Freq * 4 * 4) << 19, (u64)((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF)), NULL); ++ ++ return Ret; ++} ++ ++static void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++CAMCLK_RET_e HalCamClkSetCpupllRate(void *pCfg) ++{ ++ HalCamClkSetComplexRate_t *pCpupllCfg = pCfg; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //CamOsPrintf("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (pCpupllCfg->u32Rate >= 800000000) ++ post_div = 2; ++ else if (pCpupllCfg->u32Rate >= 400000000) ++ post_div = 4; ++ else if (pCpupllCfg->u32Rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, (pCpupllCfg->u32Rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRate(void *pCfg) ++{ ++ HalCamClkGetComplexRate_t *pCpupllCfg = pCfg; ++ u32 lpf_value; ++ u32 post_div; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ //CamOsPrintf("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ pCpupllCfg->u32Rate = (div64_u64((u64)pCpupllCfg->u32ParentRate * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ //CamOsPrintf("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", pCpupllCfg->u32Rate, pCpupllCfg->u32ParentRate); ++ ++ return Ret; ++} ++ ++CAMCLK_RET_e HalCamClkGetCpupllRoundRate(void *pCfg) ++{ ++ HalCamClkGetComplexRoundRate_t *pCpupllCfg = pCfg; ++ CAMCLK_RET_e Ret = CAMCLK_RET_OK; ++ ++ if(pCpupllCfg->u32Rate < 100000000) // 100MHz ++ { ++ pCpupllCfg->u32RoundRate = 100000000; ++ } ++ else if(pCpupllCfg->u32Rate > 1400000000) // 1.4GHz ++ { ++ pCpupllCfg->u32RoundRate = 1400000000; ++ } ++ else ++ { ++ pCpupllCfg->u32RoundRate = pCpupllCfg->u32Rate; ++ } ++ ++ return Ret; ++} ++ ++HalCamClkAdjOps_t gMiupllOps={0,0,0,HalCamClkGetMiupllRate,0,0,0}; ++HalCamClkAdjOps_t gDdrpllOps={0,0,0,HalCamClkGetDdrpllRate,0,0,0}; ++HalCamClkAdjOps_t gLpllOps={0,0,HalCamClkSetLpllRate,HalCamClkGetLpllRate,HalCamClkGetLpllRoundRate,HalCamClkSetLpllOnOff,HalCamClkGetLpllOnOff}; ++HalCamClkAdjOps_t gCpupllOps={0,0,HalCamClkSetCpupllRate,HalCamClkGetCpupllRate,HalCamClkGetCpupllRoundRate,0,0}; ++HalCamClkAdjOps_t gVenOps={0,0,HalCamClkSetVenpllRate,HalCamClkGetVenpllRate,HalCamClkGetVenpllRoundRate,HalCamClkSetVenpllOnOff,HalCamClkGetVenpllOnOff}; ++#undef HAL_CAMCLKTBL_LPLL_C +diff --git a/drivers/sstar/camclk/hal/infinity6e/src/hal_camclk_tbl.c b/drivers/sstar/camclk/hal/infinity6e/src/hal_camclk_tbl.c +new file mode 100644 +index 000000000000..24be1a4da303 +--- /dev/null ++++ b/drivers/sstar/camclk/hal/infinity6e/src/hal_camclk_tbl.c +@@ -0,0 +1,174 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#define HAL_CAMCLKTBL_C ++#include "hal_camclk_if.h" ++#include "hal_camclk_complex.h" ++#include "reg_clks.h" ++#include "hal_camclk_util.h" ++ ++const HalCamClkNode_t gCamClkSrcNode[HAL_CAMCLK_SRC_Id_MAX] = ++{ ++ {HAL_CAMCLK_SRC_CLK_VOID, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_480m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_432m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll_384m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={384000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_345m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={345000000}}, ++ {HAL_CAMCLK_SRC_CLK_upll_320m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={320000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={288000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_240m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={240000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={216000000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={192000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_172m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={172800000}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={160000000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={123400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={86400000}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_288m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_288m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_216m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_216m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_123m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_123m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_mpll_86m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mpll_86m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_192m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_192m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div5, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,5,1}}, ++ {HAL_CAMCLK_SRC_CLK_utmi_160m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_utmi_160m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={12000000}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div4, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,4,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div40, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,40,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div64, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,64,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_12m_div128, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_xtali_12m,128,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_24m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={24000000}}, ++ {HAL_CAMCLK_SRC_CLK_RTC_CLK_32K, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32000}}, ++ {HAL_CAMCLK_SRC_CLK_pm_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={108000000}}, ++ {HAL_CAMCLK_SRC_CLK_miupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m, &gMiupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_ddrpll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_ddr_syn,&gDdrpllOps}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_clk, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={100000000}}, ++ {HAL_CAMCLK_SRC_CLK_ven_pll, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_xtali_24m,&gVenOps}}, ++ {HAL_CAMCLK_SRC_CLK_ven_pll_div6, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={104000000}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_div2, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={50000000}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_div4, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={25000000}}, ++ {HAL_CAMCLK_SRC_CLK_lpll_div8, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={12500000}}, ++ {HAL_CAMCLK_SRC_CLK_armpll_37p125m, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={37500000}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_in, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_top, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_sc_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_vhe_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_hemcu_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mipi_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_riu_w_clk_mcu_if_gp, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_out, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={432000000}}, ++ {HAL_CAMCLK_SRC_CLK_miu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi0,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mspi1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_vhe_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_sc_gp_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_miu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_mcu,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_sdio_p, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_sdio,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_tck_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={50000000}}, ++ {HAL_CAMCLK_SRC_CLK_eth_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={125000000}}, ++ {HAL_CAMCLK_SRC_CLK_rmii_buf, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={125000000}}, ++ {HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={125000000}}, ++ {HAL_CAMCLK_SRC_CLK_gop0, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fclk1_p,1,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc_32k, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={32768}}, ++ {HAL_CAMCLK_SRC_CLK_fro, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={48000000}}, ++ {HAL_CAMCLK_SRC_CLK_fro_div2, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fro,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_fro_div8, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fro,8,1}}, ++ {HAL_CAMCLK_SRC_CLK_fro_div16, HAL_CAMCLK_TYPE_FIXED_FACTOR, .attribute.stFixedFac={HAL_CAMCLK_SRC_CLK_fro,16,1}}, ++ {HAL_CAMCLK_SRC_CLK_cpupll_clk, HAL_CAMCLK_TYPE_COMPLEX, .attribute.stComplex={HAL_CAMCLK_SRC_CLK_mpll_432m,&gCpupllOps}}, ++ {HAL_CAMCLK_SRC_CLK_utmi, HAL_CAMCLK_TYPE_FIXED, .attribute.stFixed={480000000}}, ++ {HAL_CAMCLK_SRC_CLK_bach, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_384m},REG_CKG_BACH_384M_BASE,camclk_BIT7,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_miupll_clk,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_boot, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_miu},REG_CKG_MIU_BASE,camclk_BIT0,0,1,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ddr_syn, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_DDR_SYN_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_miu_rec, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div64,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div128},REG_CKG_MIU_REC_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_mcu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_MCU_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_riubrdg, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mcu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RIUBRDG_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_bdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_miu_p,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_BDMA_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_spi_arb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_miu_p},REG_CKG_SPI_ARB_BASE,camclk_BIT0,camclk_BIT4,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi_flash, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_ven_pll_div6,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2},REG_CKG_SPI_FLASH_BASE,camclk_BIT0,camclk_BIT5,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_pwm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PWM_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_uart1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_UART1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart0_synth_in, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_FUART0_SYNTH_IN_BASE,camclk_BIT4,0,2,6,0}}, ++ {HAL_CAMCLK_SRC_CLK_fuart, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fuart0_synth_out},REG_CKG_FUART_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2},REG_CKG_MSPI1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_mspi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mspi0_p,(u8)HAL_CAMCLK_SRC_CLK_mspi1_p},REG_CKG_MSPI_BASE,camclk_BIT12,0,1,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic0, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC0_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC1_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_miic2, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_MIIC2_BASE,camclk_BIT12,0,2,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_pwr_ctl, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div16,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PWR_CTL_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_xtali, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_live, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_BASE,camclk_BIT8,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_sr00_mclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_div8,(u8)HAL_CAMCLK_SRC_CLK_armpll_37p125m},REG_CKG_SR00_MCLK_BASE,camclk_BIT8,0,4,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_sr01_mclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_div8,(u8)HAL_CAMCLK_SRC_CLK_armpll_37p125m},REG_CKG_SR01_MCLK_BASE,camclk_BIT0,0,4,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sr1_mclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div16,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_lpll_div2,(u8)HAL_CAMCLK_SRC_CLK_lpll_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_div8,(u8)HAL_CAMCLK_SRC_CLK_armpll_37p125m},REG_CKG_SR1_MCLK_BASE,camclk_BIT8,0,4,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_PM_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_ipu_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_IPU_GP_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_ipu, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_IPU_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ipuff, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m},REG_CKG_IPUFF_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_usb30_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_USB30_GP_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_m00, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_LPTX_TOP_I_M00_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_top_i_m00, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_TOP_I_M00_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ns_top_i_m00, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_TOP_I_M00_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_m01, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_LPTX_TOP_I_M01_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_top_i_m01, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_TOP_I_M01_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ns_top_i_m01, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_TOP_I_M01_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_lptx_top_i_m1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_LPTX_TOP_I_M1_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_csi_mac_top_i_m1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_CSI_MAC_TOP_I_M1_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ns_top_i_m1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_NS_TOP_I_M1_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mipi1_tx_csi, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_lpll_clk,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m},REG_CKG_MIPI1_TX_CSI_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_bist_vhe_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_VHE_GP_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_vhe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_ven_pll,(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_VHE_BASE,camclk_BIT7,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_mfe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_ven_pll},REG_CKG_MFE_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_xtali_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_XTALI_SC_GP_BASE,camclk_BIT4,0,2,6,1}}, ++ {HAL_CAMCLK_SRC_CLK_bist_sc_gp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_BIST_SC_GP_BASE,camclk_BIT0,0,3,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_emac_ahb, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_emac_testrx125_in_lan},REG_CKG_EMAC_AHB_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_jpe, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_JPE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_aesdma, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_AESDMA_BASE,camclk_BIT0,camclk_BIT4,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sdio, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SDIO_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_sd, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_192m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div4,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div8,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div5,(u8)HAL_CAMCLK_SRC_CLK_utmi_160m_div8,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m_div40},REG_CKG_SD_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_ecc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_160m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m},REG_CKG_ECC_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_isp, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_utmi_192m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m_div4,(u8)HAL_CAMCLK_SRC_CLK_upll_384m},REG_CKG_ISP_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_fclk1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_345m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_FCLK1_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_odclk, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m_div4,(u8)HAL_CAMCLK_SRC_CLK_lpll_clk},REG_CKG_ODCLK_BASE,camclk_BIT0,0,2,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_dip, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_utmi_240m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m},REG_CKG_DIP_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_TX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_eth_buf,(u8)HAL_CAMCLK_SRC_CLK_rmii_buf},REG_CKG_EMAC_RX_BASE,camclk_BIT0,0,1,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_tx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_TX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_emac_rx_ref, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_rmii_buf,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_EMAC_RX_REF_BASE,camclk_BIT8,0,1,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ive, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_172m,(u8)HAL_CAMCLK_SRC_CLK_mpll_123m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_IVE_BASE,camclk_BIT8,0,3,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_ldcfeye, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_utmi_480m,(u8)HAL_CAMCLK_SRC_CLK_mpll_432m,(u8)HAL_CAMCLK_SRC_CLK_upll_384m,(u8)HAL_CAMCLK_SRC_CLK_upll_320m,(u8)HAL_CAMCLK_SRC_CLK_mpll_288m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LDCFEYE_BASE,camclk_BIT0,0,3,2,0}}, ++ {HAL_CAMCLK_SRC_CLK_live_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_LIVE_PM_BASE,0,0,2,0,0}}, ++ {HAL_CAMCLK_SRC_CLK_mcu_pm_p1, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fro_div8,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_fro_div2},REG_CKG_MCU_PM_P1_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_spi_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_fro,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fro_div2,(u8)HAL_CAMCLK_SRC_CLK_xtali_24m,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div4},REG_CKG_SPI_BASE,camclk_BIT8,camclk_BIT13,3,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_miic_pm, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_mpll_86m,(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fro_div2,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k},REG_CKG_MIIC_BASE,camclk_BIT12,0,2,14,0}}, ++ {HAL_CAMCLK_SRC_CLK_pm_sleep, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_fro_div2,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_PM_SLEEP_BASE,0,0,2,10,1}}, ++ {HAL_CAMCLK_SRC_CLK_rtc, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_RTC_BASE,camclk_BIT0,0,2,2,1}}, ++ {HAL_CAMCLK_SRC_CLK_sar, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_VOID,(u8)HAL_CAMCLK_SRC_CLK_VOID},REG_CKG_SAR_BASE,camclk_BIT5,0,2,7,1}}, ++ {HAL_CAMCLK_SRC_CLK_pir, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_fro_div16,(u8)HAL_CAMCLK_SRC_CLK_fro_div8,(u8)HAL_CAMCLK_SRC_CLK_fro_div2},REG_CKG_PIR_BASE,camclk_BIT8,0,2,10,0}}, ++ {HAL_CAMCLK_SRC_CLK_pm_uart, HAL_CAMCLK_TYPE_COMPOSITE, .attribute.stComposite={{(u8)HAL_CAMCLK_SRC_CLK_xtali_12m,(u8)HAL_CAMCLK_SRC_CLK_rtc_32k,(u8)HAL_CAMCLK_SRC_CLK_mpll_216m_div2,(u8)HAL_CAMCLK_SRC_CLK_mpll_86m},REG_CKG_PM_UART_BASE,camclk_BIT0,0,2,2,1}}, ++}; ++ ++#undef HAL_CAMCLKTBL_C +diff --git a/drivers/sstar/camclk/verify/Makefile b/drivers/sstar/camclk/verify/Makefile +new file mode 100755 +index 000000000000..9485fc4e9069 +--- /dev/null ++++ b/drivers/sstar/camclk/verify/Makefile +@@ -0,0 +1,45 @@ ++# ++# Makefile for kernel test ++# ++PWD ?= $(shell pwd) ++DIR_PATH := $(PWD)/../ ++KVERSION := $(shell uname -r) ++ ++MODULE_NAME = CamclkUt ++ ++SRC_PATH := $(DIR_PATH) ++ ++CHIP_DIR=infinity6 ++ ++KERNEL_DIR ?= $(PWD)/../../../../ ++ ++INC_PATH := -I$(DIR_PATH) ++INC_PATH += -I$(DIR_PATH)/../include ++INC_PATH += -I$(DIR_PATH)/../common ++INC_PATH += -I$(KERNEL_DIR)/drivers/sstar/include ++INC_PATH += -I$(KERNEL_DIR)/drivers/sstar/include/$(CHIP_DIR) ++ ++ ++INC_PATH += -I$(DIR_PATH)//drv/inc ++INC_PATH += -I$(DIR_PATH)//drv/inc/linux ++INC_PATH += -I$(DIR_PATH)//drv/pub ++INC_PATH += -I$(DIR_PATH)//hal/common ++INC_PATH += -I$(DIR_PATH)//hal/$(CHIP_DIR)/inc ++INC_PATH += -I$(DIR_PATH)//hal/$(CHIP_DIR) ++ ++ ++EXTRA_CFLAGS += $(INC_PATH) ++ ++obj-m := $(MODULE_NAME).o ++ ++$(MODULE_NAME)-objs += .//clk_ut_module.o ++$(MODULE_NAME)-objs += .//clk_ut.o ++ ++all: ++ @echo EXTRA_CFLAGS=$(EXTRA_CFLAGS) ++ @echo KERNEL_DIR = $(KERNEL_DIR) ++ @echo DIR=$(DIR_PATH) ++ make -C $(KERNEL_DIR) M=$(PWD) modules ++ ++clean: ++ make -C $(KERNEL_DIR) M=$(PWD) clean +diff --git a/drivers/sstar/camclk/verify/clk_ut.c b/drivers/sstar/camclk/verify/clk_ut.c +new file mode 100644 +index 000000000000..c87c836bc2a2 +--- /dev/null ++++ b/drivers/sstar/camclk/verify/clk_ut.c +@@ -0,0 +1,214 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++//============================================================================== ++// ++// INCLUDE FILES ++// ++//============================================================================== ++ ++#include "cam_os_wrapper.h" ++#include "drv_camclk_st.h" ++#include "drv_camclk.h" ++#include "drv_camclk_Api.h" ++#include "hal_camclk_if.h" ++#include "camclk_dbg.h" ++#define MAX_CTX_CNT 64 ++#define PAGE_SIZE 4096 ++u32 gu32HandlerCnt = 0; ++void DrvCamclkUtCaseS(const char *buf, u32 n) ++{ ++ int u32para[2]; ++ void *phandler = NULL; ++ long Temp; ++ const char *str = buf; ++ CAMCLK_Set_Attribute stCfg; ++ ++ sscanf(str, "%d %d %lx", &u32para[0],&u32para[1],&Temp); ++ CAMCLKINFO("CAMCLK UT S CID:%d Select:%d Create/ID:%x\n", ++ u32para[0],u32para[1],Temp); ++ ++ if(Temp==0) ++ { ++ CamClkRegister((u8 *)"Temp",u32para[0],&phandler); ++ } ++ else ++ { ++ phandler = (void *)Temp; ++ } ++ stCfg.eSetType = CAMCLK_SET_ATTR_PARENT; ++ stCfg.attribute.u32Parent = u32para[1]; ++ CamClkAttrSet(phandler,&stCfg); ++ if((Temp==0)) ++ { ++ CamClkUnregister(phandler); ++ } ++} ++ ++void DrvCamclkUtCaseE(const char *buf, u32 n) ++{ ++ int u32para[2]; ++ const char *str = buf; ++ void *phandler = NULL; ++ long Temp; ++ sscanf(str, "%d %d %lx", &u32para[0],&u32para[1],&Temp); ++ CAMCLKINFO("CAMCLK UT E CID:%d enable:%d Create/ID:%x\n", ++ u32para[0],u32para[1],Temp); ++ if(Temp==0) ++ { ++ CamClkRegister((u8 *)"Temp",u32para[0],&phandler); ++ } ++ else ++ { ++ phandler = (void *)Temp; ++ } ++ CamClkSetOnOff(phandler,(u8)u32para[1]); ++ if((Temp==0)) ++ { ++ CamClkUnregister(phandler); ++ } ++} ++void DrvCamclkUtCaseF(const char *buf, u32 n) ++{ ++ int u32para[3]; ++ void *phandler = NULL; ++ long Temp; ++ const char *str = buf; ++ CAMCLK_Set_Attribute stCfg; ++ ++ sscanf(str, "%d %d %d %lx", &u32para[0],&u32para[1],&u32para[2],&Temp); ++ CAMCLKINFO("CAMCLK UT F CID:%d Freq:%d Type:%d Create/ID:%x\n", ++ u32para[0],u32para[1],u32para[2],Temp); ++ if(Temp==0) ++ { ++ CamClkRegister((u8 *)"Temp",u32para[0],&phandler); ++ } ++ else ++ { ++ phandler = (void *)Temp; ++ } ++ stCfg.eRoundType = u32para[2]; ++ stCfg.eSetType = CAMCLK_SET_ATTR_RATE; ++ stCfg.attribute.u32Rate = u32para[1]; ++ CamClkAttrSet(phandler,&stCfg); ++ if((Temp==0)) ++ { ++ CamClkUnregister(phandler); ++ } ++} ++void DrvCamclkUtCaseG(const char *buf, u32 n) ++{ ++ void *phandler = NULL; ++ long Temp; ++ const char *str = buf; ++ CAMCLK_Get_Attribute stCfg; ++ int idx; ++ ++ sscanf(str, "%lx", &Temp); ++ phandler = (void *)Temp; ++ CAMCLKINFO("CAMCLK UT G DID:%p\n",phandler); ++ CamClkAttrGet(phandler,&stCfg); ++ CAMCLKERR("CAMCLK Freq:%d Parent cnt:%d ",stCfg.u32Rate,stCfg.u32NodeCount); ++ for(idx=0;idx=MAX_CTX_CNT) ++ { ++ CAMCLKERR("Ctx > 64\n"); ++ return; ++ } ++ CamClkRegister((u8 *)hname,u32para,&pv); ++ CAMCLKERR("Ctx = %p Cnt= %d\n",pv,gu32HandlerCnt); ++ gu32HandlerCnt++; ++} ++void DrvCamclkUtCaseD(const char *buf, u32 n) ++{ ++ void *phandler = NULL; ++ long Temp; ++ const char *str = buf; ++ ++ sscanf(str, "%lx", &Temp); ++ //sscanf(str, "%p", &phandler); ++ phandler = (void *)Temp; ++ CAMCLKINFO("CAMCLK UT D DID:%p\n",phandler); ++ if(phandler) ++ { ++ CamClkUnregister(phandler); ++ gu32HandlerCnt--; ++ } ++} ++void DrvCamclkUtCmdParser(const char *buf, u32 n) ++{ ++ char cmd; ++ int u32size = 0; ++ const char *str = buf; ++ //1.choose cmd ++ //2.parser buf ++ u32size +=sscanf(str, "%c", &cmd); ++ str+=(u32size+1); ++ CAMCLKINFO("CAMCLK UT CMD:%c u32size:%d n:%d @%x\n", cmd,u32size,n,(u32)str); ++ switch(cmd) ++ { ++ case 'C': ++ DrvCamclkUtCaseC(str,n-(u32size+1)); ++ break; ++ case 'D': ++ DrvCamclkUtCaseD(str,n-(u32size+1)); ++ break; ++ case 'E': ++ DrvCamclkUtCaseE(str,n-(u32size+1)); ++ break; ++ case 'F': ++ DrvCamclkUtCaseF(str,n-(u32size+1)); ++ break; ++ case 'G': ++ DrvCamclkUtCaseG(str,n-(u32size+1)); ++ break; ++ case 'S': ++ DrvCamclkUtCaseS(str,n-(u32size+1)); ++ break; ++ default: ++ CAMCLKINFO("RGN UT CMD NOT SUPPORT:%c\n", cmd); ++ break; ++ } ++} ++u32 DrvCamclkUtShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Ut ========================\n"); ++ str += CamOsSnprintf(str, end - str, "Case CMD Description\n"); ++ str += CamOsSnprintf(str, end - str, "create echo C (CID) (NAME) > test Create instance\n"); ++ str += CamOsSnprintf(str, end - str, "destroy echo D (HandleID) > test Destroy instance\n"); ++ str += CamOsSnprintf(str, end - str, "On/Off echo E (CID) 0/1 (Create/ID) > test On/Off Clock \n"); ++ str += CamOsSnprintf(str, end - str, "Freq echo F (CID) (Freq) (Type) (Create/ID) > test Set Clock Freq\n"); ++ str += CamOsSnprintf(str, end - str, "Get echo G (Handle ID) > test Get Attr\n"); ++ str += CamOsSnprintf(str, end - str, "Sel echo S (CID) (sel) (Create/ID) > test Set Clock Parent\n"); ++ str += CamOsSnprintf(str, end - str, "======================== CamClk Ut ========================\n"); ++ return (str - buf); ++} +diff --git a/drivers/sstar/camclk/verify/clk_ut_module.c b/drivers/sstar/camclk/verify/clk_ut_module.c +new file mode 100755 +index 000000000000..b132e0ad4c37 +--- /dev/null ++++ b/drivers/sstar/camclk/verify/clk_ut_module.c +@@ -0,0 +1,298 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "irqs.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "cam_sysfs.h" ++#include "cam_os_wrapper.h" ++#include "drv_camclk_Api.h" ++#include "drv_camclk_DataType.h" ++#include "drv_camclk.h" ++#include "camclk_dbg.h" ++//------------------------------------------------------------------------------------------------- ++// Define & Macro ++//------------------------------------------------------------------------------------------------- ++ ++#define DRV_CAMCLKUT_DEVICE_COUNT 1 ++#define DRV_CAMCLKUT_DEVICE_NAME "camclkut" ++#define DRV_CAMCLKUT_DEVICE_MAJOR 0x8a ++#define DRV_CAMCLKUT_DEVICE_MINOR 0x0 ++#define DRV_CAMCLKUT_DEVICE_NODE "camdriver,camclkut" ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++static int DrvCamClkUtModuleProbe(struct platform_device *pdev); ++static int DrvCamClkUtModuleRemove(struct platform_device *pdev); ++u32 DrvCamclkUtShow(char *buf); ++void DrvCamclkUtCmdParser(const char *buf, u32 n); ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ int binit; ++ struct cdev cdev; ++ struct file_operations fops; ++ struct device *devicenode; ++} DrvCamClkUtModuleDevice_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++static DrvCamClkUtModuleDevice_t m_stCamClkUtDevice = ++{ ++ .s32Major = DRV_CAMCLKUT_DEVICE_MAJOR, ++ .s32Minor = DRV_CAMCLKUT_DEVICE_MINOR, ++ .refCnt = 0, ++ .binit = 0, ++ .devicenode = NULL, ++ .cdev = ++ { ++ .kobj = {.name = DRV_CAMCLKUT_DEVICE_NAME, }, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct class* m_pstCamClkUtClass = NULL; ++ ++static const struct of_device_id m_stCamClkUtMatchTable[] = ++{ ++ { .compatible = DRV_CAMCLKUT_DEVICE_NODE}, ++ {} ++}; ++ ++static struct platform_driver m_stCamClkUtPlatformDriver = ++{ ++ .probe = DrvCamClkUtModuleProbe, ++ .remove = DrvCamClkUtModuleRemove, ++ .driver = ++ { ++ .name = DRV_CAMCLKUT_DEVICE_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(m_stCamClkUtMatchTable), ++ }, ++}; ++ ++static struct platform_device m_stDrvCamClkUtPlatformDevice = ++{ ++ .name = DRV_CAMCLKUT_DEVICE_NAME, ++ .id = 0, ++ .dev = ++ { ++ .of_node = NULL, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++static ssize_t Camclk_test_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if (NULL != buf) ++ { ++ DrvCamclkUtCmdParser(buf,n); ++ return n; ++ } ++ ++ return 0; ++} ++ ++static ssize_t Camclk_test_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return DrvCamclkUtShow(buf); ++} ++ ++static DEVICE_ATTR(test, 0644, Camclk_test_show, Camclk_test_store); ++void _DrvCamClkUtModuleInit(void) ++{ ++ int s32Ret = 0; ++ dev_t dev; ++ ++ if (m_stCamClkUtDevice.refCnt == 0) ++ { ++ m_stCamClkUtDevice.refCnt++; ++ ++ CAMCLKINFO("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ s32Ret = alloc_chrdev_region(&dev, m_stCamClkUtDevice.s32Minor, DRV_CAMCLKUT_DEVICE_COUNT, DRV_CAMCLKUT_DEVICE_NAME); ++ m_stCamClkUtDevice.s32Major = MAJOR(dev); ++ ++ //dev = MKDEV(m_stCamClkUtDevice.s32Major, m_stCamClkUtDevice.s32Minor); ++ ++ if (IS_ERR(m_pstCamClkUtClass)) ++ { ++ CAMCLKERR("[%s @ %d] class_create() fail. \n", ++ __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ // Initialize a cdev structure ++ cdev_init(&m_stCamClkUtDevice.cdev, &m_stCamClkUtDevice.fops); ++ ++ // Add a char device to the system ++ if (0 != (s32Ret = cdev_add(&m_stCamClkUtDevice.cdev, dev, DRV_CAMCLKUT_DEVICE_COUNT))) ++ { ++ CAMCLKERR(" [%s @ %d] cdev_add() fail\n", __FUNCTION__, __LINE__); ++ } ++ } ++ ++ if (m_stCamClkUtDevice.devicenode == NULL && m_pstCamClkUtClass) ++ { ++ // Creates a device and registers it with sysfs ++ m_stCamClkUtDevice.devicenode = CamDeviceCreate(m_pstCamClkUtClass, NULL, dev, NULL, DRV_CAMCLKUT_DEVICE_NAME); ++ ++ if (NULL == m_stCamClkUtDevice.devicenode) ++ { ++ CAMCLKERR("[%s @ %d] device_create() fail\n", __FUNCTION__, __LINE__); ++ } ++ } ++ ++ // Initialize platform device of_node ++ if (m_stDrvCamClkUtPlatformDevice.dev.of_node == NULL) ++ { ++ m_stDrvCamClkUtPlatformDevice.dev.of_node = of_find_compatible_node(NULL, NULL, DRV_CAMCLKUT_DEVICE_NODE); ++ } ++ if (m_stDrvCamClkUtPlatformDevice.dev.of_node == NULL) ++ { ++ CAMCLKERR("[%s @ %d] Get device node fail\n", __FUNCTION__, __LINE__); ++ } ++ CamDeviceCreateFile((struct device *)m_stCamClkUtDevice.devicenode, &dev_attr_test); ++ } ++ else ++ { ++ m_stCamClkUtDevice.refCnt++; ++ } ++ ++} ++ ++void _DrvCamClkUtModuleDeInit(void) ++{ ++ if (m_stCamClkUtDevice.refCnt) ++ { ++ m_stCamClkUtDevice.refCnt--; ++ } ++ ++ if (m_stCamClkUtDevice.refCnt == 0) ++ { ++ CAMCLKERR("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ if (m_stCamClkUtDevice.cdev.count) ++ { ++ // Remove a cdev from the system ++ cdev_del(&m_stCamClkUtDevice.cdev); ++ } ++ m_stDrvCamClkUtPlatformDevice.dev.of_node = NULL; ++ m_pstCamClkUtClass = NULL; ++ ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++static int DrvCamClkUtModuleProbe(struct platform_device *pdev) ++{ ++ int s32Ret = 0; ++ dev_t dev; ++ ++ CAMCLKINFO("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ ++ if (m_stCamClkUtDevice.s32Major == 0) ++ { ++ // Register a range of char device numbers ++ s32Ret = alloc_chrdev_region(&dev, m_stCamClkUtDevice.s32Minor, DRV_CAMCLKUT_DEVICE_COUNT, DRV_CAMCLKUT_DEVICE_NAME); ++ m_stCamClkUtDevice.s32Major = MAJOR(dev); ++ } ++ ++ m_pstCamClkUtClass = msys_get_sysfs_class(); ++ ++ if (IS_ERR(m_pstCamClkUtClass)) ++ { ++ CAMCLKERR("[%s @ %d] msys_get_sysfs_class() fail. \n", ++ __FUNCTION__, __LINE__); ++ } ++ ++ m_stDrvCamClkUtPlatformDevice.dev.of_node = pdev->dev.of_node; ++ ++ // Create device ++ _DrvCamClkUtModuleInit(); ++ return 0; ++} ++ ++static int DrvCamClkUtModuleRemove(struct platform_device *pdev) ++{ ++ CAMCLKINFO( "[%s @ %d]\n", __FUNCTION__, __LINE__); ++ _DrvCamClkUtModuleDeInit(); ++ CamDeviceUnregister(m_stCamClkUtDevice.devicenode); ++ ++ return 0; ++} ++ ++ ++int _MDrv_CamClkUt_ModuleInit(void) ++{ ++ int ret = 0; ++ CAMCLKDBG("[%s @ %d]\n", __FUNCTION__, __LINE__); ++ ++ // Register a driver for platform-level devices ++ ret = CamPlatformDriverRegister(&m_stCamClkUtPlatformDriver); ++ ++ if (!ret) ++ { ++ CAMCLKDBG("[%s] CamPlatformDriverRegister() success\n", __FUNCTION__); ++ } ++ else ++ { ++ CAMCLKERR("[%s @ %d] CamPlatformDriverRegister() fail\n", __FUNCTION__, __LINE__); ++ CamPlatformDriverUnregister(&m_stCamClkUtPlatformDriver); ++ } ++ ++ return ret; ++} ++ ++ ++void _MDrv_CamClkUt_ModuleExit(void) ++{ ++ CamPlatformDriverUnregister(&m_stCamClkUtPlatformDriver); ++} ++module_init(_MDrv_CamClkUt_ModuleInit); ++module_exit(_MDrv_CamClkUt_ModuleExit); ++MODULE_AUTHOR("CAMDRIVER"); ++MODULE_DESCRIPTION("CLK driver UT"); +diff --git a/drivers/sstar/camdriver/Kconfig b/drivers/sstar/camdriver/Kconfig +new file mode 100644 +index 000000000000..e69de29bb2d1 +diff --git a/drivers/sstar/camdriver/Makefile b/drivers/sstar/camdriver/Makefile +new file mode 100644 +index 000000000000..e69de29bb2d1 +diff --git a/drivers/sstar/ceva_link/Kconfig b/drivers/sstar/ceva_link/Kconfig +new file mode 100644 +index 000000000000..e6dc585ef972 +--- /dev/null ++++ b/drivers/sstar/ceva_link/Kconfig +@@ -0,0 +1,3 @@ ++config SSTAR_CEVAXM6 ++ tristate "XM6 driver" ++ help +diff --git a/drivers/sstar/ceva_link/Makefile b/drivers/sstar/ceva_link/Makefile +new file mode 100755 +index 000000000000..fb7ad9346ee2 +--- /dev/null ++++ b/drivers/sstar/ceva_link/Makefile +@@ -0,0 +1,38 @@ ++# ++# Makefile for MStar Infinity3 IVE device drivers. ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++#EXTRA_CFLAGS += -Idrivers/mstar/ceva_linkdrv ++#EXTRA_CFLAGS += -Idrivers/mstar/include ++#EXTRA_CFLAGS += -Idrivers/mstar/gpio ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/bdma/$(CONFIG_SSTAR_CHIP_NAME)/ ++ ++ ++#ccflags-$(CONFIG_SSTAR_CEVAXM6) += -DMSOS_TYPE_LINUX_KERNEL ++ ++# files ++#obj-$(CONFIG_SSTAR_CEVAXM6) += ceva_link.o ++#ceva_link-y += ceva_link.o ++ ++#a ++#ceva_link-y := ceva_linkdrv_xm6.o \ ++# ceva_linkdrv.o \ ++# protected_mem_db.o \ ++# hal_ceva.o \ ++# hal_timer.o \ ++# hal_cpm.o \ ++# boot_loader.o \ ++# ceva_linkdrv_proc.o \ ++# file_access.o ++ ++obj-$(CONFIG_SSTAR_CEVAXM6) += ceva_linkdrv_xm6.o \ ++ ceva_linkdrv.o \ ++ protected_mem_db.o \ ++ hal_ceva.o \ ++ hal_timer.o \ ++ hal_cpm.o \ ++ boot_loader.o \ ++ ceva_linkdrv_proc.o \ ++ file_access.o +\ No newline at end of file +diff --git a/drivers/sstar/ceva_link/boot_loader.c b/drivers/sstar/ceva_link/boot_loader.c +new file mode 100644 +index 000000000000..01e1275fbfac +--- /dev/null ++++ b/drivers/sstar/ceva_link/boot_loader.c +@@ -0,0 +1,566 @@ ++#include "boot_loader.h" ++#include "drv_debug.h" ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#ifdef _Measure_BootUp_Time_ ++#include ++#endif //_Measure_BootUp_Time_ ++#include "file_access.h" ++ ++#define DETECT_DSP_CHECK ++ ++#define ALIGN_XM6(a) (((long)(a) + 0xFFF) & ~0xFFF) ++ ++ ++#ifndef _FAST_DMA_BOOT_ ++typedef struct { ++ u8 boot_copier_binary[0x200 - sizeof(phys_addr_t)*4]; ++ phys_addr_t dummy; ++ phys_addr_t pdma_buff_addr; ++ phys_addr_t image_start_addr; ++ phys_addr_t entry_point_addr; ++} boot_copier_t; ++ ++static const u8 boot_copier_binary[0x200] = ++{ ++ 0xCC, 0xC0, 0xD4, 0x8A, 0xFC, 0x7F, 0xBC, 0x53, 0x6B, 0xC8, 0x30, 0x70, 0x91, 0xC3, 0x56, 0x88, ++ 0000, 0000, 0xEF, 0x97, 0x1C, 0x36, 0x75, 0x88, 0x41, 0x33, 0x1C, 0xF2, 0x05, 0xCE, 0x01, 0x70, ++ 0000, 0xFE, 0x7C, 0000, 0x64, 0x80, 0xC0, 0x64, 0x40, 0000, 0000, 0xF8, 0000, 0000, 0xEF, 0x97, ++ 0x3A, 0x68, 0x05, 0x88, 0x5C, 0x81, 0x1C, 0xD8, 0x01, 0x64, 0xDC, 0x80, 0x61, 0x80, 0x02, 0x06, ++ 0x20, 0x30, 0000, 0x5F, 0x60, 0x03, 0x68, 0x95, 0000, 0000, 0000, 0xF8, 0000, 0000, 0xEF, 0x97, ++ 0x3A, 0x68, 0x05, 0x88, 0x5C, 0x81, 0x1C, 0xD8, 0x01, 0x64, 0x1E, 0x78, 0x05, 0x88, 0000, 0x74, ++ 0x5E, 0x80, 0x3C, 0x80, 0000, 0000, 0000, 0xFE, 0x1E, 0x05, 0x05, 0xC8, 0000, 0000, 0xEF, 0x97, ++ 0000, 0000, 0000, 0xF8, 0x5E, 0xF8, 0x0C, 0x88, 0x1E, 0x79, 0x05, 0x88, 0x8C, 0x44, 0x02, 0000, ++ 0xE1, 0xFE, 0x81, 0x90, 0xFF, 0xFF, 0xFF, 0xF8, 0000, 0000, 0xEF, 0x97, 0xB1, 0x06, 0x64, 0x95, ++ 0x6C, 0x88, 0x40, 0x1E, 0xC0, 0xFA, 0x5C, 0x81, 0x1C, 0xD8, 0x01, 0x64, 0000, 0000, 0xEF, 0x97, ++ 0000, 0000, 0xEF, 0x97, 0x5C, 0x81, 0x1C, 0x98, 0x01, 0x64, 0xF0, 0x01, 0xC9, 0xD7, 0xBA, 0x71, ++ 0x0B, 0xE8, 0x7D, 0x88, 0x02, 0x68, 0x03, 0x70, 0x6C, 0xC8, 0000, 0x71, 0xBD, 0x43, 0x83, 0xCE, ++ 0x02, 0x70, 0x6C, 0xC8, 0000, 0x71, 0x0D, 0xE4, 0x7D, 0x88, 0x02, 0x68, 0xA3, 0x8F, 0x1F, 0xC8, ++ 0x82, 0x43, 0000, 0000, 0xEF, 0x97, 0xA3, 0000, 0xA2, 0x01, 0x80, 0xD0, 0000, 0000, 0000, 0xF8, ++ 0xC5, 0xA0, 0x1B, 0x98, 0x1C, 0x45, 0x9F, 0x34, 0xC0, 0x20, 0x3D, 0xC0, 0x85, 0x5D, 0x84, 0x51, ++ 0xC8, 0x44, 0x80, 0x5D, 0000, 0000, 0xEF, 0x97, 0xA2, 0xFF, 0x81, 0x90, 0xFF, 0xFF, 0xFF, 0xF8, ++ 0x05, 0x88, 0x40, 0x70, 0000, 0xC1, 0x6C, 0xC8, 0x10, 0x70, 0x01, 0000, 0xEE, 0x97, 0x32, 0x37, ++ 0x10, 0x70, 0x01, 0x04, 0x05, 0x88, 0x40, 0x70, 0x81, 0xC1, 0x6C, 0xC8, 0x10, 0x70, 0000, 0000, ++ 0x02, 0000, 0x02, 0000, 0xB0, 0x53, 0x6B, 0x88, 0x20, 0x70, 0x03, 0000, 0x02, 0xC2, 0x6C, 0x88, ++ 0x81, 0x90, 0xFF, 0xFF, 0xFF, 0xF8, 0000, 0000, 0xEF, 0x97, 0x3D, 0x90, 0xFE, 0x8E, 0000, 0x78, ++ 0xEF, 0x97, 0xC0, 0xFD, 0x81, 0x90, 0xFF, 0xFF, 0xFF, 0xF8, 0000, 0000, 0xEF, 0x97, 0x61, 0xFF, ++ 0xFF, 0xF8, 0x60, 0xA0, 0x1B, 0x98, 0x9C, 0x44, 0x5F, 0x34, 0x61, 0x20, 0x3D, 0xC0, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0x04, 0000, 0000, 0000, 0xEF, 0x97, 0xA2, 0xFF, 0x81, 0x90, 0xFF, 0xFF, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ++ 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000 ++}; ++#else //_FAST_DMA_BOOT_ ++typedef struct { ++ u8 boot_copier_binary[0x200]; ++ #if 0 ++ phys_addr_t dummy; ++ phys_addr_t pdma_buff_addr; ++ phys_addr_t image_start_addr; ++ phys_addr_t entry_point_addr; ++ #endif ++} boot_copier_t; ++ ++static const u8 boot_copier_binary[0x200] = ++{ ++0x01, 0x70, 0x00, 0x00, 0xEF, 0x97, 0xCC, 0xC0, 0xD4, 0x8A, 0xFC, 0x7F, 0x91, 0xC3, 0x56, 0x88, ++0x64, 0x80, 0xC0, 0x64, 0x00, 0x00, 0xEF, 0x97, 0x00, 0x00, 0xEF, 0x97, 0x1C, 0xF3, 0x05, 0x8E, ++0x6C, 0x88, 0xCC, 0x70, 0xDC, 0x00, 0x64, 0x80, 0xC0, 0x64, 0x40, 0x00, 0x00, 0xF8, 0x7C, 0x00, ++0x10, 0x70, 0x82, 0x5D, 0x00, 0xEE, 0x7F, 0x88, 0x02, 0xC5, 0x6C, 0x88, 0x14, 0x70, 0x62, 0x76, ++0x82, 0xC1, 0x6C, 0x88, 0x10, 0x70, 0x40, 0x30, 0x00, 0xEE, 0x7F, 0x88, 0x02, 0xC1, 0x6C, 0x88, ++0x02, 0xC2, 0x6C, 0x88, 0x10, 0x70, 0x02, 0x70, 0x6C, 0x88, 0x00, 0x71, 0x00, 0xEE, 0x7F, 0x88, ++0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0xB0, 0x53, 0x6B, 0x88, 0x20, 0x70, 0x00, 0xEE, 0x7F, 0x88, ++0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, ++0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x0D, 0xB4, 0x7C, 0x88, 0x90, 0x64, 0x00, 0xB0, ++0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0xA1, 0xFE, 0x01, 0x90, 0xFF, 0xFF, 0xFF, 0xF8, ++0x00, 0x71, 0x43, 0x03, 0x00, 0x90, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0x34, 0xE8, 0x44, 0x63, 0x30, ++0x7F, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0x02, 0xC2, 0x6C, 0x88, 0x10, 0x70, 0x02, 0x70, 0x6C, 0x88, ++0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0xB0, 0x53, 0x6B, 0x88, 0x20, 0x70, 0x00, 0xEE, ++0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, ++0xFF, 0xF8, 0x00, 0xB0, 0x14, 0x80, 0x0D, 0xB4, 0x7C, 0x88, 0x90, 0x64, 0x00, 0xB0, 0x14, 0x80, ++0xFF, 0xF8, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0xA1, 0xFE, 0x01, 0x90, 0xFF, 0xFF, ++0x0B, 0x70, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x20, 0xFD, 0x01, 0x90, 0xFF, 0xFF, ++0x6C, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0x16, 0x75, 0x6C, 0x88, 0x18, 0x70, 0x17, 0x70, 0x6C, 0xC8, ++0x7F, 0x88, 0x17, 0x5F, 0x16, 0x70, 0x6C, 0xC8, 0x1A, 0x70, 0x00, 0xEE, 0x7F, 0x88, 0xD7, 0xCE, ++0x94, 0x70, 0x6C, 0xC8, 0x1A, 0x70, 0x00, 0xEE, 0x7F, 0x88, 0xD7, 0xCE, 0x6C, 0x88, 0x00, 0xEE, ++0x00, 0xF8, 0x00, 0xEE, 0x7F, 0x88, 0x95, 0xCE, 0x6C, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0xA0, 0x32, ++0x00, 0xEE, 0x7F, 0x88, 0x16, 0x73, 0x6C, 0x88, 0x19, 0x70, 0x17, 0x70, 0x6C, 0xC8, 0x00, 0x20, ++0x1A, 0x70, 0x17, 0x74, 0x6C, 0xC8, 0x03, 0x70, 0x00, 0xEE, 0x7F, 0x88, 0xD7, 0xCE, 0x6C, 0x88, ++0x00, 0xEE, 0x7F, 0x88, 0xD7, 0xCE, 0x6C, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0x96, 0x71, 0x6C, 0x88, ++0x00, 0xEE, 0x7F, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0x00, 0xEE, 0x7F, 0x88, ++0x00, 0xB0, 0x14, 0x80, 0x17, 0x74, 0x6C, 0x88, 0x03, 0x70, 0xAC, 0x53, 0x6B, 0x88, 0x34, 0x70, ++0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, ++0xFF, 0xFF, 0xFF, 0xF8, 0x00, 0xB0, 0x14, 0x80, 0xFD, 0xD6, 0x68, 0x88, 0x00, 0xB0, 0x14, 0x80, ++0x6C, 0xC8, 0x18, 0x70, 0x00, 0xB0, 0x14, 0x80, 0x00, 0xB0, 0x14, 0x80, 0xA1, 0xFE, 0x01, 0x90, ++0x2A, 0xCC, 0x6C, 0x88, 0x00, 0xEE, 0x7F, 0x88, 0xEA, 0x75, 0x6C, 0x88, 0xFB, 0x72, 0x81, 0x74, ++0x00, 0xEE, 0x7F, 0x88, 0x00, 0x00, 0x80, 0x95, 0x00, 0xEE, 0x7F, 0x88, 0x00, 0xEE, 0x7F, 0x88, ++0x00, 0xEE, 0x7F, 0x88, 0x00, 0x00, 0x80, 0x95, 0x00, 0xEE, 0x7F, 0x88, 0x00, 0xEE, 0x7F, 0x88, ++}; ++ ++#endif //_FAST_DMA_BOOT_ ++ ++typedef enum ++{ ++ E_REG_STATE_UNKNOWN = 0, /**< Undefined state */ ++ E_REG_STATE_IN_PROGRESS, /**< DSP registration in progress */ ++ E_REG_STATE_DONE /**< DSP registration complete */ ++}dsp_reg_state_enum; ++ ++typedef struct ++{ ++ u32 dsp_id; /**< The DSP ID */ ++ dsp_reg_state_enum dsp_reg_state; /**< The DSP registration state */ ++}dsp_info_struct; ++ ++extern void SetUpDSPTimeSlot(unsigned int SetValue); ++ ++#ifdef _Measure_BootUp_Time_ ++struct timeval start_time; ++struct timeval end_time; ++struct timeval DMA_start_time; ++struct timeval DMA_end_time; ++ ++unsigned int Cacu_time(struct timeval *pStart,struct timeval *pEnd) ++{ ++ unsigned int ret=0; ++ unsigned int start,end; ++ ++ start=pStart->tv_sec * 1000000 + pStart->tv_usec; ++ end=pEnd->tv_sec * 1000000 + pEnd->tv_usec; ++ ret=end-start; ++ ++ return ret; ++} ++#endif //_Measure_BootUp_Time_ ++ ++static long detect_dsp_acting(ceva_hal_handle *handle, u8 *buffer_virt) ++{ ++ dsp_info_struct *dsp_info = (dsp_info_struct*)buffer_virt; ++ int retry = 50; ++ #ifdef _Measure_BootUp_Time_ ++ unsigned int process_time; ++ #endif //_Measure_BootUp_Time_ ++ ++ // delay 10 ms to ensure to share memory is clean by DSP ++ mdelay(10); ++ ++ while (retry--) ++ { ++ if (dsp_info->dsp_id == 0 && dsp_info->dsp_reg_state == E_REG_STATE_DONE) ++ { ++ #ifdef _Measure_BootUp_Time_ ++ do_gettimeofday(&end_time); ++ process_time=Cacu_time(&start_time,&end_time); ++ printk("DSP WakeUp time : %08d us \n",process_time); ++ #endif //_Measure_BootUp_Time_ ++ XM6_MSG(XM6_MSG_DBG, "DSP is ready\n"); ++ return 0; ++ } ++ //mdelay(500); ++ mdelay(30); ++ XM6_MSG(XM6_MSG_DBG, "DSP is not ready (%d, %d), dummy = 0x%x\n", dsp_info->dsp_id, dsp_info->dsp_reg_state, dsp_ceva_hal_read_dummy_data(handle, 0)); ++ } ++ dsp_ceva_hal_check_bodary_status(handle); ++ return -EIO; ++} ++ ++#ifdef _FAST_DMA_BOOT_ ++ ++#include "ms_platform.h" ++#include "hal_bdma.h" ++#include "infinity2/registers.h" ++#include "ms_types.h" ++ ++static void Add_DSP_Copier_Address(u8 *Data,phys_addr_t Dsp_Data_Image_Addr,phys_addr_t Dsp_Code_Image_Addr) ++{ ++ unsigned int tmp=(unsigned int)Dsp_Data_Image_Addr; ++ ++ printk("Dsp_Code_Image_Addr :0x%x Dsp_Data_Image_Addr:0x%x \n", Dsp_Code_Image_Addr, Dsp_Data_Image_Addr); ++ ++ *(Data+0)=((tmp>>0)&0xff); ++ *(Data+1)=((tmp>>8)&0xff); ++ *(Data+2)=((tmp>>16)&0xff); ++ *(Data+3)=((tmp>>24)&0xff); ++ ++ tmp=(unsigned int)Dsp_Code_Image_Addr; ++ *(Data+4)=((tmp>>0)&0xff); ++ *(Data+5)=((tmp>>8)&0xff); ++ *(Data+6)=((tmp>>16)&0xff); ++ *(Data+7)=((tmp>>24)&0xff); ++ ++ return; ++} ++ ++int dsp_dma_transfer(phys_addr_t src_addr, phys_addr_t dst_addr, u32 size,u8 *src_virt) ++{ ++#if 1 ++ HalBdmaParam_t stBdmaParam; ++ u8 u8DmaCh = HAL_BDMA_CH1; ++ #ifdef _Measure_BootUp_Time_ ++ unsigned int process_time; ++ #endif //_Measure_BootUp_Time_ ++ ++ stBdmaParam.ePathSel = HAL_BDMA_MIU0_TO_MIU0; ++ stBdmaParam.eSrcDataWidth = HAL_BDMA_DATA_BYTE_16; ++ stBdmaParam.eDstDataWidth = HAL_BDMA_DATA_BYTE_16; ++ stBdmaParam.bIntMode = 0; ++ stBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ stBdmaParam.u32TxCount = size; ++ stBdmaParam.pSrcAddr = (void *)(src_addr - MIU0_BASE); ++ stBdmaParam.pDstAddr = (void *)(dst_addr - MIU0_BASE); ++ stBdmaParam.pfTxCbFunc = NULL; ++ ++ #if 0 ++ printk("[Jesse]%s %d src addr=%p dest addr=%p size=%x\n", __FUNCTION__, __LINE__, ++ stBdmaParam.pSrcAddr, stBdmaParam.pDstAddr, stBdmaParam.u32TxCount); ++ #endif ++ ++ #ifdef _Measure_BootUp_Time_ ++ do_gettimeofday(&DMA_start_time); ++ #endif //_Measure_BootUp_Time_ ++ ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &stBdmaParam)) { ++ return -1; ++ } ++ #ifdef _Measure_BootUp_Time_ ++ do_gettimeofday(&DMA_end_time); ++ process_time=Cacu_time(&DMA_start_time,&DMA_end_time); ++ printk("ARM BDMA process time : %08d us \n",process_time); ++ #endif //_Measure_BootUp_Time_ ++#else ++ void *dst_virt_addr; ++ ++ dst_virt_addr = ioremap_nocache(dst_addr, size); ++ if (dst_virt_addr == NULL) ++ { ++ XM6_MSG(XM6_MSG_DBG, "dsp_dma_transfer dst_virt_addr error:0x%p \n",dst_virt_addr); ++ return -ENOMEM; ++ } ++ ++ XM6_MSG(XM6_MSG_DBG, "%s %d dst_virt_addr=0x%p src_virt_addr=0x%p size:0x%x \n", __FUNCTION__, __LINE__,dst_virt_addr,src_virt,size); ++ memcpy(dst_virt_addr,src_virt,size); ++ iounmap(dst_virt_addr); ++ ++#endif ++ return 0; ++} ++ ++#if 0 ++#define CODE_EXT_NAME "/mnt/CODE_EXT.bin" ++#define DATA_EXT_NAME "/mnt/DATA_EXT.bin" ++#define TEST_SIZE 32*1024 ++ ++int Log_Bin_File(phys_addr_t dst_phy_addr,unsigned int Size,unsigned int Idx,phys_addr_t src_phy_addr) ++{ ++ int ret=0; ++ void *dst_virt_addr; ++ char *pName; ++ struct file *pFile; ++ int wsize=0; ++ unsigned int ii=0; ++ /* ++ void *src_virt_addr; ++ unsigned int ii=0; ++ unsigned char tmp0,tmp1;*/ ++ ++ //struct resource *physical_region=NULL; ++ ++ printk("Log_Bin_File aaaaaa Idx:%d Size:0x%x \n",Idx,Size); ++ ++ #if 0 ++ physical_region = request_mem_region(dst_phy_addr, Size, "BDMA_MOVE_1"); ++ if(physical_region == NULL){ ++ printk("physical_region NULL \n"); ++ } ++ printk("Log_Bin_File physical_region ->start:0x%x resource_size:0x%x \n",physical_region ->start,resource_size(physical_region)); ++ dst_virt_addr = (void *)ioremap(physical_region ->start, resource_size(physical_region)); ++ #endif ++ ++ ++ dst_virt_addr = ioremap_nocache(dst_phy_addr, Size); ++ //printk("Log_Bin_File Idx:%d dst_phy_addr:0x%llx dst_virt_addr:0x%x \n",Idx,dst_phy_addr,dst_virt_addr); ++ printk("Log_Bin_File Idx:%d dst_virt_addr:0x%p \n",Idx,dst_virt_addr); ++ if (dst_virt_addr == NULL) ++ { ++ XM6_MSG(XM6_MSG_DBG, "Log_Bin_File dst_virt_addr error\n"); ++ return -ENOMEM; ++ } ++ for(ii=0;ii<16;ii++){ ++ XM6_MSG(XM6_MSG_DBG, "Log_Bin_File dst_virt_addr:0x%p +%d : 0x%x \n",dst_virt_addr,ii,*((unsigned char *)dst_virt_addr+ii)); ++ } ++ ++ pName=(Idx==0)?CODE_EXT_NAME:DATA_EXT_NAME; ++ ++ pFile=OpenFile(pName,O_CREAT|O_SYNC|O_RDWR,S_IWUSR|S_IWGRP|S_IWOTH); ++ if (pFile == NULL) ++ { ++ XM6_MSG(XM6_MSG_DBG, "Log_Bin_File pFile open fail\n"); ++ return -ENOMEM; ++ } ++ //wsize=WriteFile(pFile,dst_virt_addr,Size); ++ wsize=WriteFile(pFile,dst_virt_addr,TEST_SIZE); ++ XM6_MSG(XM6_MSG_DBG, "write file:0x%p size 0x%x wsize:0x%x \n",pFile,Size,wsize); ++ CloseFile(pFile); ++ ++ #if 0 ++ src_virt_addr = ioremap_nocache(src_phy_addr, Size); ++ //printk("Log_Bin_File Idx:%d dst_phy_addr:0x%llx dst_virt_addr:0x%x \n",Idx,dst_phy_addr,dst_virt_addr); ++ printk("Log_Bin_File 222 Idx:%d src_virt_addr:0x%p \n",Idx,src_virt_addr); ++ if (src_virt_addr == NULL) ++ { ++ XM6_MSG(XM6_MSG_DBG, "Log_Bin_File src_virt_addr error\n"); ++ return -ENOMEM; ++ } ++ for(ii=0;iicustom_info & 0x1) ++ { ++ dsp_ceva_hal_reset_xm6(handle); ++ dsp_ceva_hal_set_PLL(handle,1); ++ } ++ SetUpDSPTimeSlot((dsp_mem_info->custom_info >> 16)&0xffff); ++ ++ XM6_MSG(XM6_MSG_DBG, "boot_image.addr = 0x%x, size = %d\n", dsp_mem_info->boot_image.addr, dsp_mem_info->boot_image.size); ++ XM6_MSG(XM6_MSG_DBG, "share_mem.addr = 0x%x, size = %d\n", dsp_mem_info->share_mem.addr, dsp_mem_info->share_mem.size); ++ XM6_MSG(XM6_MSG_DBG, "ext_heap.addr = 0x%x, size = %d\n", dsp_mem_info->ext_heap.addr, dsp_mem_info->ext_heap.size); ++ XM6_MSG(XM6_MSG_DBG, "hprintf_buf.addr = 0x%x, size = %d\n", dsp_mem_info->hprintf_buf.addr, dsp_mem_info->hprintf_buf.size); ++ XM6_MSG(XM6_MSG_DBG, "dsp_log_buf.addr = 0x%x, size = %d\n", dsp_mem_info->dsp_log_buf.addr, dsp_mem_info->dsp_log_buf.size); ++ XM6_MSG(XM6_MSG_DBG, "work_buffer.addr = 0x%x, size = %d\n", dsp_mem_info->work_buffer.addr, dsp_mem_info->work_buffer.size); ++ ++ size = sizeof(boot_copier_t) + sizeof(dsp_mem_info_t); ++ copier_virt = (boot_copier_t*)ALIGN_XM6(copier_buf->virt); ++ copier_phys = ALIGN_XM6(copier_buf->phys); ++ offset = (u8*)copier_virt - copier_buf->virt; ++ if ((copier_buf->size - offset) < size) { ++ XM6_MSG(XM6_MSG_ERR, "copier buffer is too small\n"); ++ return -EINVAL; ++ } ++ ++ // info is next to copier ++ info_virt = (dsp_mem_info_t*)(copier_virt+1); ++ info_phys = copier_phys + sizeof(boot_copier_t); ++ ++ XM6_MSG(XM6_MSG_DBG, "copier_buf = %p (0x%X), size = %d\n", copier_virt, copier_phys, sizeof(boot_copier_t)); ++ XM6_MSG(XM6_MSG_DBG, "info_buf = %p (0x%X)\n", info_virt, info_phys); ++ ++ // copy copier binary and sett relative data ++ memcpy(copier_virt->boot_copier_binary, boot_copier_binary, sizeof(copier_virt->boot_copier_binary)); ++ #ifdef _FAST_DMA_BOOT_ ++ Add_DSP_Copier_Address(copier_virt->boot_copier_binary+0x1F8,dsp_mem_info->boot_image.addr,dsp_mem_info->boot_image.addr+0x40000); ++ #else ++ copier_virt->pdma_buff_addr = 0; ++ copier_virt->image_start_addr = dsp_mem_info->boot_image.addr; ++ copier_virt->entry_point_addr = 0; ++ XM6_MSG(XM6_MSG_DBG, "boot_copier_binary = 0x%02x (@ 0x%p)\n", copier_virt->boot_copier_binary[0], &copier_virt->boot_copier_binary); ++ XM6_MSG(XM6_MSG_DBG, "pdma_buff_addr = 0x%08x (@ 0x%p)\n", copier_virt->pdma_buff_addr, &copier_virt->pdma_buff_addr); ++ XM6_MSG(XM6_MSG_DBG, "image_start_addr = 0x%08x (@ 0x%p)\n", copier_virt->image_start_addr, &copier_virt->image_start_addr); ++ XM6_MSG(XM6_MSG_DBG, "entry_point_addr = 0x%08x (@ 0x%p)\n", copier_virt->entry_point_addr, &copier_virt->entry_point_addr); ++ #endif ++ ++ XM6_MSG(XM6_MSG_DBG, "endian check %02x %02x %02x %02x = %08x\n", copier_virt->boot_copier_binary[0], copier_virt->boot_copier_binary[1], copier_virt->boot_copier_binary[2], copier_virt->boot_copier_binary[3], *(u32*)(&copier_virt->boot_copier_binary[0])); ++ ++ dsp_ceva_hal_check_bodary_status(handle); ++ ++ // copy boot info ++ memcpy(info_virt, dsp_mem_info, sizeof(dsp_mem_info_t)); ++ ++ // wirte boot info address to dummy register, and DSP would read after boot up ++ dsp_ceva_hal_write_dummy_data(handle, 0, info_phys); ++ ++ XM6_MSG(XM6_MSG_DBG, "dummy 0 = 0x%x\n", info_phys); ++ ++ // wait memory barrier ++ wmb(); ++ ++ // start DSP ++ dsp_ceva_hal_reset_xm6(handle); ++ #ifdef _Measure_BootUp_Time_ ++ do_gettimeofday(&start_time); ++ #endif //_Measure_BootUp_Time_ ++ dsp_ceva_hal_enable_xm6(handle); ++ dsp_ceva_hal_bootup_xm6(handle, copier_phys); ++ dsp_timer_hal_init(); ++ ++ return detect_dsp_acting(handle, share_mem_virt); ++} ++ ++void dsp_shut_down(ceva_hal_handle *handle) ++{ ++ dsp_ceva_hal_reset_xm6(handle); ++ dsp_ceva_hal_set_PLL(handle,0); ++ return; ++} ++ ++#if 0 ++#include "file_access.h" ++ ++void MemoryClear(phys_addr_t pa_addr,unsigned int size) ++{ ++ void *virt_addr; ++ ++ virt_addr = ioremap_nocache(pa_addr, size); ++ memset(virt_addr,0,size); ++ iounmap(virt_addr); ++ ++ printk("MemoryClear virt_addr:%p pa_addr:0x%x sz:%d\n",virt_addr,pa_addr,size); ++ ++ return; ++} ++ ++void Write_Memory_to_File(phys_addr_t pa_addr,unsigned int size,struct file *PDump) ++{ ++ void *virt_addr; ++ ++ virt_addr = ioremap_nocache(pa_addr, size); ++ WriteFile(PDump, virt_addr, size); ++ iounmap(virt_addr); ++ ++ printk("Write_Memory_to_File PDump:%p virt_addr:%p pa_addr:0x%x sz:%d\n", PDump, virt_addr,pa_addr,size); ++ ++ return; ++} ++void dump_memory(void) ++{ ++ //void *dst_virt_addr; ++ struct file *PDump; ++ ++ ++ PDump=OpenFile("/mnt/dump_code_ext.bin",O_RDWR | O_CREAT | O_SYNC,0644); ++ if(IS_ERR(PDump)) ++ { ++ printk("file open fail 111 %p!", PDump); ++ return; ++ } ++ Write_Memory_to_File(pCode_ext_Buf->phys,pCode_ext_Buf->size,PDump); ++ CloseFile(PDump); ++ ++ PDump=OpenFile("/mnt/dump_data_ext.bin",O_RDWR | O_CREAT | O_SYNC,0644); ++ if(IS_ERR(PDump)) ++ { ++ printk("file open fail 222 %p!", PDump); ++ return; ++ } ++ Write_Memory_to_File(pData_ext_Buf->phys,pData_ext_Buf->size,PDump); ++ CloseFile(PDump); ++ ++ return; ++} ++ ++#endif +diff --git a/drivers/sstar/ceva_link/boot_loader.h b/drivers/sstar/ceva_link/boot_loader.h +new file mode 100644 +index 000000000000..e53b979e5cae +--- /dev/null ++++ b/drivers/sstar/ceva_link/boot_loader.h +@@ -0,0 +1,25 @@ ++#ifndef _BOOT_LOADER_H_ ++#define _BOOT_LOADER_H_ ++ ++#include ++#include "ceva_linkdrv_xm6.h" ++#include "hal_ceva.h" ++#include "hal_timer.h" ++#include "ceva_linkdrv-generic.h" ++ ++int dsp_boot_up(ceva_hal_handle *handle, dev_dsp_buf *copier_buf, void *share_mem_virt, dsp_mem_info_t *dsp_mem_info); ++void dsp_shut_down(ceva_hal_handle *handle); ++//int dsp_dma_image_ext_transfer(struct boot_config_t boot_config); ++int dsp_dma_image_ext_transfer(struct boot_config_t boot_config,u8 *image_virt); ++ ++#if 0 ++void MemoryClear(phys_addr_t pa_addr,unsigned int size); ++#endif ++ ++#define _FAST_DMA_BOOT_ ++//#undef _FAST_DMA_BOOT_ ++ ++//#define _Measure_BootUp_Time_ ++#undef _Measure_BootUp_Time_ ++ ++#endif // _BOOT_LOADER_H_ +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv-generic.h b/drivers/sstar/ceva_link/ceva_linkdrv-generic.h +new file mode 100644 +index 000000000000..1de3c871ed32 +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv-generic.h +@@ -0,0 +1,197 @@ ++/* ++ * ceva_linkdrv-generic.h ++ * ++ * Created on: Nov 13, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#ifndef CEVA_LINKDRV_GENERIC_H_ ++#define CEVA_LINKDRV_GENERIC_H_ ++ ++#include ++#include ++#include ++#include "ms_version.h" ++ ++/*! ++ * Device name for kernel registration ++ */ ++#define CEVA_PCIDEV_DEVICE_NAME "ceva_linkdrv_xm6_" ++/*! ++ * kfifo max size ++ */ ++#define CEVA_LINKDRV_FIFO_MAX_EVENTS (128) ++ ++/*! ++ * Device name for shared memory driver ++ */ ++#define CEVA_PROT_MEM_DRV_NAME "protected_mem_db" ++ ++/*! ++ * debug statistics information ++ */ ++struct ceva_linkdrv_debug_info_s{ ++ unsigned long int bypass_interrupts_success; ++ unsigned long int bypass_interrupts_failed; ++ unsigned long int events_recieved; ++ unsigned long int fifo_full; ++ unsigned long int generated_interrupts; ++ unsigned long int generate_interrupt_failures; ++ unsigned long int unhandled_irq; ++ unsigned long int handled_irq; ++ unsigned long int fifo_in_err; ++}; ++ ++/*! ++ * container class for debug statistics ++ * ++ * we wrap the statistics with the union in order to allow developers ++ * to modify the driver code, yet without updating any user code which ++ * aligned to older structure. ++ * user should allocate with the size of union ceva_linkdrv_debug_info, ++ * but actual data copied will be at the size of actual data. ++ */ ++union ceva_linkdrv_debug_info { ++ struct ceva_linkdrv_debug_info_s data; ++ unsigned long int raw[250]; ++}; ++ ++ ++/*! ++ * data structure for boot loader ++ */ ++struct boot_buffer_t { ++ __u64 phys; ++ __u64 miu; ++ __u32 size; ++}; ++ ++typedef struct { ++ __u32 code_int_size; ++ __u32 data_int_size; ++ __u32 code_ext_size; ++ __u32 data_ext_size; ++} dsp_dma_image_info_t; ++ ++struct boot_config_t { ++ struct boot_buffer_t boot_image; // address of boot_image is virtual address ++ struct boot_buffer_t ext_heap; // address of ext_heap is physical address ++ struct boot_buffer_t share_mem; // address of share memory is physical address ++ struct boot_buffer_t work_buffer; // address of work_buffer is physical address ++ __u32 custom_info; ++ __u32 dsp_code_addr; ++ __u32 dsp_code_size; ++ __u32 dsp_data_addr; ++ __u32 dsp_data_size; ++ __u32 dsp_log_addr; ++ __u32 dsp_log_size; ++ __u32 log_enable; ++ dsp_dma_image_info_t dsp_dma_image_info; ++}; ++ ++/*! ++ * bypass definitions ++ */ ++#define CEVADEV_BYPASS__IN_BUF_OFFSET (0x0) ++#define CEVADEV_BYPASS__OUT_BUF_OFFSET (0x1000) ++#define CEVADEV_BYPASS__BUF_LEN (0x1000) ++#define CEVADEV_BYPASS__EVENT (0x10) ++ ++/*! ++ * struct to maintain read and write operations ++ * ++ * read/write operations from user include offset variable ++ * to read from (or write to). the read/write user functions ++ * will pass an object of this struct as it's in/out buffer. ++ * driver will first read the offset field (using copy_from_user) ++ * and then perform the r/w from/to the passed buffer address ++ */ ++struct RWBuffer { ++ unsigned long offset; ++ void *buf; ++}; ++ ++/* ++ * ioctl commands ++ */ ++#define IOC_CEVADRV_MAGIC (0xFB) ++ ++#define IOC_CEVADRV_PRINT_DMA _IOR(IOC_CEVADRV_MAGIC, 1, int) ++#define IOC_CEVADRV_BYPASS_REQ _IOW(IOC_CEVADRV_MAGIC, 2, int) ++#define IOC_CEVADRV_READ_DEBUG _IOWR(IOC_CEVADRV_MAGIC, 3, union ceva_linkdrv_debug_info) ++#define IOC_CEVADRV_GENERATE_INT _IOW(IOC_CEVADRV_MAGIC, 4, int) ++#define IOC_CEVADRV_GET_PID_PROCID _IOR(IOC_CEVADRV_MAGIC, 5, unsigned long) ++#define IOC_CEVADRV_BOOT_UP _IOR(IOC_CEVADRV_MAGIC, 6, struct boot_config_t) ++#define IOC_CEVADRV_SHUT_DOWN _IOWR(IOC_CEVADRV_MAGIC, 7, int) ++#define IOC_CEVADRV_BOOT_CHECK _IOWR(IOC_CEVADRV_MAGIC, 8, int) ++#define IOC_CEVADRV_MIU_2_PHYS _IOWR(IOC_CEVADRV_MAGIC, 9, __u64) ++#define IOC_CEVADRV_PHYS_2_MIU _IOWR(IOC_CEVADRV_MAGIC, 10, __u64) ++#define IOC_CEVADRV_VERSION_CHECK _IOWR(IOC_CEVADRV_MAGIC, 11, struct Version_Info) ++ ++#define IOC_CEVADRV_MAXNR 11 ++ ++/* ++ * log macros ++ * ENABLE_DEBUG and ENABLE_TRACE are defined in the makefile ++ */ ++ ++#define CEVA_LOG_PREFIX "ceva_link" ++ ++#ifdef __KERNEL__ ++/* This one if debugging is on, and kernel space */ ++# define PDLOGF printk ++# define CEVA_TRACE KERN_DEBUG "[" CEVA_LOG_PREFIX "] T " ++# define CEVA_DEBUG KERN_DEBUG "[" CEVA_LOG_PREFIX "] D " ++# define CEVA_INFO KERN_INFO "[" CEVA_LOG_PREFIX "] I " ++# define CEVA_WARN KERN_WARNING "[" CEVA_LOG_PREFIX "] W " ++# define CEVA_ERR KERN_ERR "[" CEVA_LOG_PREFIX "] E " ++#else ++/* This one for user space */ ++# define PDLOGF printf ++# define CEVA_TRACE "[" CEVA_LOG_PREFIX "] T " ++# define CEVA_DEBUG "[" CEVA_LOG_PREFIX "] D " ++# define CEVA_INFO "[" CEVA_LOG_PREFIX "] I " ++# define CEVA_WARN "[" CEVA_LOG_PREFIX "] W " ++# define CEVA_ERR "[" CEVA_LOG_PREFIX "] E " ++#endif /* kernel/user */ ++ ++#ifdef ENABLE_DEBUG ++#define TRACE() PDLOGF(CEVA_TRACE "%s:%d", __FUNCTION__, __LINE__) ++# define LOG_D(fmt, args...) PDLOGF(CEVA_DEBUG fmt "\n", ## args) ++# define LOG_I(fmt, args...) PDLOGF(CEVA_INFO fmt "\n", ## args) ++# define LOG_W(fmt, args...) PDLOGF(CEVA_WARN fmt "\n", ## args) ++# define LOG_E(fmt, args...) PDLOGF(CEVA_ERR fmt "\n", ## args) ++#else /* ENABLE_DEBUG */ ++# define TRACE() ++# define LOG_D(fmt, args...) ++# define LOG_I(fmt, args...) ++# define LOG_W(fmt, args...) ++# define LOG_E(fmt, args...) ++#endif /* ENABLE_DEBUG */ ++ ++#undef PDEBUG /* undef it, just in case */ ++#define PDEBUG LOG_D ++ ++#ifdef ENABLE_TRACE /* PDEBUG must be defined for this to work */ ++#define FUNCTION_ENTRY() PDEBUG("in %s\n", __PRETTY_FUNCTION__) ++#define FUNCTION_EXIT() PDEBUG("leaving %s\n", __PRETTY_FUNCTION__) ++#else /* ENABLE_TRACE */ ++#define FUNCTION_ENTRY() ++#define FUNCTION_EXIT() ++#endif /* ENABLE_TRACE */ ++ ++#endif /* CEVA_LINKDRV_GENERIC_H_ */ +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv.c b/drivers/sstar/ceva_link/ceva_linkdrv.c +new file mode 100644 +index 000000000000..40d493eb9f45 +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv.c +@@ -0,0 +1,898 @@ ++/* ++ * ceva_linkdrv.c ++ * ++ * Created on: Nov 11, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ceva_linkdrv-generic.h" ++#include "ceva_linkdrv_xm6.h" ++#include "ceva_linkdrv.h" ++ ++#include "drv_debug.h" ++ ++MODULE_AUTHOR("Ido Reis "); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION("1.0.1"); ++MODULE_DESCRIPTION("cevalink logical driver"); ++ ++#define MODULE_NAME "ceva_linkdrv" ++#define LINKDRV_PFD_PROC_NAME_MAX_SIZE (16) ++#define CEVA_LINKDRV_PROC_EVENTS_NAME "events" ++#define CANCEL_READ_MAX_RELAX_TRIES (100) ++#define UNBLOCKED_BY_USER ((CEVA_LINKDRV_FIFO_MAX_EVENTS+1)*(-1)) ++ ++/*! ++ * container class for ceva_linkdrv's operations for a specific process ++ */ ++struct ceva_linkdrv_pfd { ++ struct ceva_linkdrv *owner; /*!< ceva_linkdrv object that owns this obj */ ++ struct list_head list_node; /*!< list_node for maintenance */ ++ pid_t pid; /*!< process id that has opened the device */ ++ struct proc_dir_entry *dir; /*!< root dir for procfs entry */ ++ struct proc_dir_entry *events; /*!< procfs entry dedicated to process */ ++ DECLARE_KFIFO_PTR(fifo, ceva_event_t); /*!< kfifo to receive events */ ++ int *blocked; /*!< used to wakeup by workqueue */ ++ int events_ref_count; /*!< ref count for open */ ++}; ++ ++static int _ceva_linkdrv_proc_open(struct inode *, struct file *); ++static int _ceva_linkdrv_proc_release(struct inode *, struct file *); ++static ssize_t _ceva_linkdrv_proc_read(struct file *, char __user *, ++ size_t, loff_t *); ++static int _ceva_linkdrv_proc_read_break(struct ceva_linkdrv *link); ++static struct ceva_linkdrv_pfd *_get_linkdrv_pfd(struct ceva_linkdrv *link, ++ pid_t pid); ++static struct ceva_linkdrv_pfd *_create_linkdrv_pfd(struct ceva_linkdrv *link, ++ pid_t pid); ++static void _destroy_linkdrv_pfd(struct ceva_linkdrv_pfd *pfd); ++ ++static int _ceva_link_debug_proc_init(struct ceva_linkdrv *link); ++static void _ceva_link_debug_proc_deinit(void); ++ ++/*! ++ * procfs fops ++ */ ++static struct file_operations ceva_linkdrv_proc_events_fops = { ++ .owner = THIS_MODULE, ++ .read = _ceva_linkdrv_proc_read, ++ .open = _ceva_linkdrv_proc_open, ++ .release = _ceva_linkdrv_proc_release, ++}; ++ ++/*! ++ * handler for procfs directory (general) ++ * @see ceva_linkdrv_init() ++ */ ++static struct proc_dir_entry* ceva_linkdrv_proc_dir = NULL; ++extern void Dump_ARMDSP_HndShakeInfo(void); ++#define DEFAULT_TIMESLOT 200 ++unsigned int DSPTimeOutSlot=DEFAULT_TIMESLOT; ++ ++void SetUpDSPTimeSlot(unsigned int SetValue) ++{ ++ DSPTimeOutSlot=(SetValue==0)?DEFAULT_TIMESLOT:SetValue; ++ printk("SetUpDSPTimeSlot DSPTimeOutSlot:%d \n",DSPTimeOutSlot); ++ return; ++} ++ ++/*! ++ * search for existing pfd within the link's database (helper function) ++ * ++ * the key for each pfd is it's process id. ++ * this functions searches the list for a pfd that matches the pid ++ * @param [in] link ceva_linkdrv object ++ * @param [in] pid process id to be used as a key to search for a pfd ++ * @return valid struct ceva_linkdrv_pfd address if found, NULL if not ++ */ ++static struct ceva_linkdrv_pfd *_get_linkdrv_pfd(struct ceva_linkdrv *link, ++ pid_t pid) { ++ struct list_head *pos; ++ struct ceva_linkdrv_pfd * i; ++ list_for_each(pos, &link->pfd_list) { ++ i = (struct ceva_linkdrv_pfd *) list_entry(pos, ++ struct ceva_linkdrv_pfd, list_node); ++ if (!i) { ++ XM6_MSG(XM6_MSG_WRN, "%s -> iterator is null\n", __FUNCTION__); ++ continue; ++ } ++ if (i->pid == pid) { ++ return i; ++ } ++ } ++ return NULL; ++} ++ ++/*! ++ * create a ceva_linkdrv_pfd object (helper function) ++ * ++ * this function allocates and creates a ceva_linkdrv_pfd object to be used ++ * by a specific process. it creates a procfs entry based on the caller ++ * process id. ++ * the created object should be added to the link's pfd list for maintenance. ++ * @param [in/out] link owner of this object ++ * @param [in] pid id of the caller/owner process ++ * @return valid ceva_linkdrv_pfd object for success, NULL for failure ++ * @see ceva_linkdrv_open_cb(), _destroy_linkdrv_pfd() ++ */ ++static struct ceva_linkdrv_pfd *_create_linkdrv_pfd(struct ceva_linkdrv *link, ++ pid_t pid) { ++ struct ceva_linkdrv_pfd* pfd; ++ char proc_name[LINKDRV_PFD_PROC_NAME_MAX_SIZE]; ++ ++ if (!link) { ++ return NULL; ++ } ++ pfd = kzalloc(sizeof(struct ceva_linkdrv_pfd), GFP_KERNEL); ++ if (!pfd) { ++ goto err_alloc; ++ } ++ if (kfifo_alloc(&pfd->fifo, CEVA_LINKDRV_FIFO_MAX_EVENTS, GFP_KERNEL)) { ++ goto err_fifo; ++ } ++ ++ sprintf(proc_name, "%d", pid); ++ /* create directory */ ++ pfd->dir = proc_mkdir(proc_name, ceva_linkdrv_proc_dir); ++ if (pfd->dir == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "could not create procfs dir (%s)\n", proc_name); ++ goto err_procfs_dir; ++ } ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)) ++ pfd->dir->owner = THIS_MODULE; ++#endif /* KERNEL_VERSION(2,6,29) */ ++ XM6_MSG(XM6_MSG_DBG, "procfs dir for process %s created\n", proc_name); ++ ++ /* create procfs entry for events */ ++ pfd->events = proc_create_data( ++ CEVA_LINKDRV_PROC_EVENTS_NAME, /* name */ ++ S_IWUSR | S_IRUSR | S_IRGRP | S_IROTH, /* mode */ ++ pfd->dir, /* parent */ ++ &ceva_linkdrv_proc_events_fops, /* fops */ ++ pfd); /* data */ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)) ++ pfd->events->owner = THIS_MODULE; ++#endif /* KERNEL_VERSION(2,6,29) */ ++ if (!pfd->events) { ++ XM6_MSG(XM6_MSG_ERR, "could not create procfs entry\n"); ++ goto err_procfs_entry; ++ } ++ XM6_MSG(XM6_MSG_DBG, "created new procfs entry in /proc/%s/%s/%s\n", ++ MODULE_NAME, proc_name, ++ CEVA_LINKDRV_PROC_EVENTS_NAME); ++ pfd->owner = link; ++ pfd->pid = pid; ++ pfd->blocked = NULL; ++ pfd->events_ref_count = 0; ++ INIT_LIST_HEAD(&pfd->list_node); ++ return pfd; ++ ++err_procfs_entry: ++ remove_proc_entry(proc_name, ceva_linkdrv_proc_dir); ++err_procfs_dir: ++ kfifo_free(&pfd->fifo); ++err_fifo: ++ kfree(pfd); ++err_alloc: ++ return NULL; ++} ++ ++/*! ++ * destroys a ceva_linkdrv_pfd object (helper function) ++ * ++ * this function deletes and frees a ceva_linkdrv_pfd object. ++ * it deletes the procfs entry created for this object. ++ * the created object should be removed from the link's pfd list ++ * before executing this function. ++ * @param [in] pfd object to delete ++ * @see ceva_linkdrv_release_cb(), _create_linkdrv_pfd() ++ */ ++static void _destroy_linkdrv_pfd(struct ceva_linkdrv_pfd *pfd) { ++ char proc_name[LINKDRV_PFD_PROC_NAME_MAX_SIZE]; ++ ++ if (!pfd) { ++ return; ++ } ++ ++ sprintf(proc_name, "%d", pfd->pid); ++ ++ XM6_MSG(XM6_MSG_DBG, "destorying pfd %p, for process %s\n", pfd, proc_name); ++ remove_proc_entry(CEVA_LINKDRV_PROC_EVENTS_NAME, pfd->dir); ++ remove_proc_entry(proc_name, ceva_linkdrv_proc_dir); ++ kfifo_free(&pfd->fifo); ++ pfd->owner = NULL; ++ pfd->pid = -1; ++ pfd->blocked = NULL; ++ kfree(pfd); ++ XM6_MSG(XM6_MSG_DBG, "destoryed"); ++} ++ ++/*! ++ * unblock user read operation on a procfs entry (not irq safe) ++ * ++ * used to cancel the read during release_cb, or deinit of the module ++ * @param [in] pfd ceva_linkdrv_pfd object ++ * @return zero for success, nonzero for failure ++ * @note blocking function, as this function puts the caller thread/process ++ * to sleep to allow the read process to be unlocked ++ */ ++static int _cancel_linkdrv_pfd_read(struct ceva_linkdrv_pfd *pfd) { ++ ++ int i; ++ ++ if (pfd->blocked) { ++ *pfd->blocked = UNBLOCKED_BY_USER; ++ wake_up_interruptible_all(&pfd->owner->wq); ++ /* ++ * give up the cpu to allow the read execution to receive the ++ * event once the event will wake up the correct pfd it will reset ++ * the blocked variable to NULL and exits with EPIPE. ++ * other read executions might wake up, but it will continue to ++ * wait as the blocked variable is only reset to 'this' pfd ++ * blocked variable ++ */ ++ for (i = 0; pfd->blocked && i < CANCEL_READ_MAX_RELAX_TRIES; i++) { ++ msleep(0); ++ } ++ if (i == CANCEL_READ_MAX_RELAX_TRIES) { ++ XM6_MSG(XM6_MSG_ERR, "%s:: unable to break read execution of process %d\n", ++ __FUNCTION__, pfd->pid); ++ return -EBUSY; ++ } ++ } ++ return 0; ++} ++ ++/*! ++ * unblock user read operation on a procfs entry (irq safe) ++ * ++ * used to cancel the read during release_cb, or deinit of the module ++ * @param [in] pfd ceva_linkdrv_pfd object ++ * @return zero for success, nonzero for failure ++ * @note blocking function, as this function puts the caller thread/process ++ * to sleep to allow the read process to be unlocked ++ */ ++static int _cancel_linkdrv_pfd_read_irqsafe(struct ceva_linkdrv_pfd *pfd) { ++ ++ struct ceva_linkdrv *link = pfd->owner; ++ unsigned long flags; ++ int i; ++ ++ if(!link || !pfd){ ++ XM6_MSG(XM6_MSG_ERR, "%s pfd:0x%p or link:0x%p is NULL\n",__FUNCTION__,pfd,link); ++ return -EINVAL; ++ } ++ spin_lock_irqsave(&link->waiting_lock, flags); ++ if (pfd->blocked) { ++ *pfd->blocked = UNBLOCKED_BY_USER; ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ wake_up_interruptible_all(&link->wq); ++ /* ++ * see above comment in _cancel_linkdrv_pfd_read ++ */ ++ for (i = 0; pfd->blocked && i < CANCEL_READ_MAX_RELAX_TRIES; i++) { ++ mdelay(1); ++ } ++ if(pfd->blocked == NULL){ ++ XM6_MSG(XM6_MSG_ERR, "%s pfd->blocked is NULL\n",__FUNCTION__); ++ return 0; ++ } ++ else{ ++ XM6_MSG(XM6_MSG_ERR, "%s:: unable to break read execution of process %d pfd->blocked:0x%p \n",__FUNCTION__, pfd->pid,pfd->blocked); ++ return -EBUSY; ++ } ++ if (i == CANCEL_READ_MAX_RELAX_TRIES) { ++ XM6_MSG(XM6_MSG_ERR, "%s:: unable to break read execution of process %d\n",__FUNCTION__, pfd->pid); ++ return -EBUSY; ++ } ++ } else { ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ } ++ return 0; ++} ++ ++/*! ++ * callback function for opening a ceva device ++ * ++ * called by the owner of this module (usually the PCIe device driver) ++ * creates a ceva_linkdrv_pfd object (if the first time 'open' was called by ++ * this process) and adds it to the maintained list. ++ * @param [in] link 'this' module object ++ * @return zero for success, nonzero for failure ++ */ ++int ceva_linkdrv_open_cb(struct ceva_linkdrv *link) { ++ struct ceva_linkdrv_pfd *pfd; ++ pid_t pid = task_tgid_vnr(current); ++ unsigned long flags; ++ int ret = 0; ++ ++ if (mutex_lock_interruptible(&link->mux)) { ++ ret = -EINTR; ++ goto out; ++ } ++ if (_get_linkdrv_pfd(link, pid) != NULL) { ++ XM6_MSG(XM6_MSG_WRN, "this process already opened the device\n"); ++ ret = -EBUSY; ++ goto out; ++ } ++ pfd = _create_linkdrv_pfd(link, pid); ++ if (!pfd) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ spin_lock_irqsave(&link->waiting_lock, flags); ++ list_add_tail(&pfd->list_node, &link->pfd_list); ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ ++out: ++ mutex_unlock(&link->mux); ++ return 0; ++} ++ ++/*! ++ * callback function for closing a ceva device ++ * ++ * called by the owner of this module (usualy the PCIe device driver) ++ * destroys the ceva_linkdrv_pfd object (if the ref count reaches zero) ++ * and removes it from the maintained list. ++ * @param [in] link 'this' module object ++ * @return zero for success, nonzero for failure ++ */ ++int ceva_linkdrv_release_cb(struct ceva_linkdrv *link) { ++ struct ceva_linkdrv_pfd *pfd; ++ pid_t pid; ++ unsigned long flags; ++ int ret = 0; ++ ++ if (mutex_lock_interruptible(&link->mux)) { ++ ret = -EINTR; ++ goto out; ++ } ++ pid = task_tgid_vnr(current); ++ pfd = _get_linkdrv_pfd(link, pid); ++ if (pfd == NULL) { ++ pid_t tid = task_pid_nr(current); ++ XM6_MSG(XM6_MSG_ERR, "this process did not opened the device (p%d/t%d)\n", pid, tid); ++ ret = -ESRCH; ++ goto out; ++ } ++ ++ if (pfd->events_ref_count) { ++ XM6_MSG(XM6_MSG_DBG, "%s executed before the entry has been released, ref = %d\n", ++ __FUNCTION__, pfd->events_ref_count); ++ } ++ ++ // release read executions before removing from list ++ if (_cancel_linkdrv_pfd_read(pfd)) { ++ XM6_MSG(XM6_MSG_ERR, "unable to release %d/%s since read is still in progress\n", ++ pid, CEVA_LINKDRV_PROC_EVENTS_NAME); ++ return -EBUSY; ++ } ++ // remove from list ++ spin_lock_irqsave(&link->waiting_lock, flags); ++ list_del_init(&pfd->list_node); ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ // destroy object ++ _destroy_linkdrv_pfd(pfd); ++ ++out: ++ mutex_unlock(&link->mux); ++ return 0; ++} ++ ++/*! ++ * special commands executer ++ * ++ * @param [in] link 'this' module object ++ * @param [in] cmd command to execute ++ * @param [in] arg additional argument (differ for each command) ++ * @return zero for success, nonzero for failure ++ * @see IOC_CEVADRV_BYPASS_REQ, IOC_CEVADRV_READ_DEBUG ++ */ ++long ceva_linkdrv_ioctl(struct ceva_linkdrv *link, ++ unsigned int cmd, ++ unsigned long arg) { ++ long ret; ++ void *buf; ++ ceva_event_t event; ++ unsigned int __user *ubuf = (unsigned int __user *) arg; ++#if defined(CEVA_LINKDRV_DEBUG) ++ char __user *cbuf = (char __user *) arg; ++#endif // defined(CEVA_LINKDRV_DEBUG) ++ ++ switch (cmd) { ++ case IOC_CEVADRV_BYPASS_REQ: ++ buf = link->owner->dma_buf.cpu_addr; ++ XM6_MSG(XM6_MSG_DBG, "BYPASS command received," ++ " coping from offset %u to offset %u" ++ " and generate event %02x\n", ++ CEVADEV_BYPASS__OUT_BUF_OFFSET, ++ CEVADEV_BYPASS__IN_BUF_OFFSET, ++ CEVADEV_BYPASS__EVENT); ++ memcpy(buf + CEVADEV_BYPASS__OUT_BUF_OFFSET, ++ buf + CEVADEV_BYPASS__IN_BUF_OFFSET, ++ CEVADEV_BYPASS__BUF_LEN); ++ event = CEVADEV_BYPASS__EVENT; ++ ret = ceva_linkdrv_broadcast_events(link, &event, 1); ++ if (!ret) { ++ DEBUG_INFO_INC(link, bypass_interrupts_success); ++ } else { ++ DEBUG_INFO_INC(link, bypass_interrupts_failed); ++ } ++ break; ++ case IOC_CEVADRV_READ_DEBUG: ++#if defined(CEVA_LINKDRV_DEBUG) ++ ret = copy_to_user(cbuf, &link->debug.data, ++ sizeof(struct ceva_linkdrv_debug_info_s)); ++#else ++ ret = -EINVAL; ++#endif ++ break; ++ case IOC_CEVADRV_GET_PID_PROCID: { ++ pid_t pid = task_tgid_vnr(current); ++ struct ceva_linkdrv_pfd *i = _get_linkdrv_pfd(link, pid); ++ if (!i) { ++ ret = -ESRCH;//ENODEV; ++ break; ++ } ++ XM6_MSG(XM6_MSG_DBG, "found, copying id #%02d to user\n", i->pid); ++ ret = copy_to_user(ubuf, &i->pid, sizeof(int)); ++ break; ++ } ++ default: ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/*! ++ * consumer open callback ++ * ++ * keeps ref count for number of times the entry was opened ++ * @param [in] inode ++ * @param [in] filp ceva_linkdrv_pfd handler associated with the procfs ++ * @return zero for success, nonzero for failure ++ */ ++static int _ceva_linkdrv_proc_open(struct inode *inode, struct file *filp) { ++ ++ struct ceva_linkdrv_pfd *pfd = PDE_DATA(filp->f_path.dentry->d_inode); ++ pid_t pid, tid; ++ ++ if (!pfd) { ++ XM6_MSG(XM6_MSG_ERR, "%s :: null pfd descriptor\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ pid = task_tgid_vnr(current); ++ tid = task_pid_nr(current); ++ ++ pfd->events_ref_count++; ++ XM6_MSG(XM6_MSG_ERR, "%d/%s was opened (by p%d/t%d), open descriptor value: %d\n", pid, CEVA_LINKDRV_PROC_EVENTS_NAME, pid, tid, pfd->events_ref_count); ++ ++ return 0; ++} ++ ++/*! ++ * consumer close callback ++ * ++ * in case close was called while user was still blocked in read this ++ * function cancels the read, and releases the user context. ++ * @param [in] inode ++ * @param [in] filp ceva_linkdrv_pfd handler associated with the procfs ++ * @return zero for success, nonzero for failure ++ * @see _cancel_linkdrv_pfd_read_irqsafe() ++ */ ++static int _ceva_linkdrv_proc_release(struct inode *inode, struct file *filp){ ++ ++ struct ceva_linkdrv_pfd *pfd = PDE_DATA(filp->f_path.dentry->d_inode); ++ pid_t pid, tid; ++ ++ if (!pfd) { ++ Dump_ARMDSP_HndShakeInfo(); ++ XM6_MSG(XM6_MSG_ERR, "%s :: null pfd descriptor\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ pid = task_tgid_vnr(current); ++ tid = task_pid_nr(current); ++ ++ if (pfd->events_ref_count == 1) { ++ int ret = _cancel_linkdrv_pfd_read_irqsafe(pfd); ++ if (ret) { ++ Dump_ARMDSP_HndShakeInfo(); ++ XM6_MSG(XM6_MSG_ERR, "unable to cancel the read operation on %d/%s (p%d/t%d)\n", ++ pid, CEVA_LINKDRV_PROC_EVENTS_NAME, pid, tid); ++ return ret; ++ } ++ /* ++ * keep the pdf descriptor in the list, as we'll need it ++ * later on for deletion of the object ++ */ ++ } ++ ++ pfd->events_ref_count--; ++ Dump_ARMDSP_HndShakeInfo(); ++ XM6_MSG(XM6_MSG_ERR, "%d/%s was closed (by p%d/t%d), open descriptor value: %d\n", pid, CEVA_LINKDRV_PROC_EVENTS_NAME, pid, tid, pfd->events_ref_count); ++ ++ return 0; ++} ++ ++ ++/*! ++ * consumer read callback ++ * ++ * user is reading data from its relative procfs entry (created during open). ++ * data is delivered using a kfifo object, and copied to the user's buffer. ++ * this function blocks the user call until events are received from the CEVA ++ * device. ++ * @param [in] filp ceva_linkdrv_pfd handler associated with the procfs ++ * @param [out] buf user buffer ++ * @param [in] count number of bytes to read from kfifo ++ * @param [in] ppos not used ++ * @return number of bytes read, negative value for errors ++ * @see ceva_linkdrv_broadcast_events(), _cancel_linkdrv_pfd_read(), ++ * _cancel_linkdrv_pfd_read_irqsafe() ++ */ ++static ssize_t _ceva_linkdrv_proc_read(struct file *filp, char __user *buf, ++ size_t count, loff_t *ppos) { ++ ++ struct ceva_linkdrv_pfd *pfd = PDE_DATA(filp->f_path.dentry->d_inode); ++ struct ceva_linkdrv *link = pfd->owner; ++ unsigned long flags; ++ int items, events_to_read, waiting, blocked, ret; ++ pid_t pid; ++ ++ if (!pfd || !link ) { ++ XM6_MSG(XM6_MSG_ERR, "pfd or link is NULL\n"); ++ return -EINVAL; ++ } ++ ++ if (!link->online) { ++ XM6_MSG(XM6_MSG_ERR, "link is not online\n"); ++ return -EPIPE; ++ } ++ ++ /* ++ * check if insufficient memory was provided to store the event's data, ++ * the buffer size should be for at least one event ++ */ ++ events_to_read = (count/sizeof(ceva_event_t)); ++ if (events_to_read <= 0) { ++ XM6_MSG(XM6_MSG_ERR, "count is not correct\n"); ++ return -EINVAL; ++ } ++ ++ spin_lock_irqsave(&link->waiting_lock, flags); ++ // block caller thread for incoming events (if fifo is empty) ++ if (kfifo_is_empty(&pfd->fifo)) { ++ /* ++ * we use a local variable here to allow this operation to be break'ed ++ * in case the driver is unloaded, and the pfd object is no longer ++ * valid we still want the user to get the EPIPE, this could be done ++ * only if the driver will signal using a valid object (while the ++ * actual pfd is deleted) ++ */ ++ blocked = 0; ++ // TODO: should we spinlock here? ++ //spin_lock_irqsave(&link->waiting_lock, flags); ++ pfd->blocked = &blocked; ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ ret = wait_event_interruptible_timeout(link->wq, blocked != 0,DSPTimeOutSlot); ++ /* ++ * we must reset the blocked pointer, as its a local variable ++ * no need to protect this part from irq as we are already not ++ * blocked, next read will check the kfifo anyhow ++ */ ++ pfd->blocked = NULL; ++ if(ret== -ERESTARTSYS){ ++ pid = task_tgid_vnr(current); ++ XM6_MSG(XM6_MSG_ERR, "read %d/%s was breake'd by signal (kill)\n", pid, CEVA_LINKDRV_PROC_EVENTS_NAME); ++ Dump_ARMDSP_HndShakeInfo(); ++ return -ERESTARTSYS; ++ } ++ else if(ret == 0){ ++ pid = task_tgid_vnr(current); ++ XM6_MSG(XM6_MSG_ERR, "read %d/%s was breake'd by TimeOut:%d \n", pid, CEVA_LINKDRV_PROC_EVENTS_NAME,DSPTimeOutSlot); ++ Dump_ARMDSP_HndShakeInfo(); ++ return DSPTimeOutSlot; ++ } ++ else{ ++ pid = task_tgid_vnr(current); ++ XM6_MSG(XM6_MSG_DBG, "read %d/%s Success remain jfifs :%d \n", pid, CEVA_LINKDRV_PROC_EVENTS_NAME,ret); ++ } ++ if (blocked < 0) { ++ pid = task_tgid_vnr(current); ++ XM6_MSG(XM6_MSG_ERR, "read %d/%s was breake'd by user (broken pipe)\n", pid, CEVA_LINKDRV_PROC_EVENTS_NAME); ++ Dump_ARMDSP_HndShakeInfo(); ++ if (!link->online) { ++ goto breaked_by_deinit; ++ } ++ return -EPIPE; ++ } ++ } ++ else{ ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ } ++ ++ waiting = kfifo_len(&pfd->fifo); ++ items = min(events_to_read, waiting); ++ if (!items) { ++ Dump_ARMDSP_HndShakeInfo(); ++ XM6_MSG(XM6_MSG_WRN, "events read was unblocked, but kfifo is empty\n"); ++ return 0; ++ } ++ XM6_MSG(XM6_MSG_DBG, "%d events waiting from device, coping to user %d events\n", waiting, items); ++ ret = kfifo_to_user(&pfd->fifo, buf, items*sizeof(ceva_event_t), &items); ++ return ret ? ret : items; ++ ++breaked_by_deinit: ++ // remove current entry from the list ++ list_del_init(&pfd->list_node); ++ // delete pfd object ++ _destroy_linkdrv_pfd(pfd); ++ return -EPIPE; ++} ++ ++/*! ++ * producer data generation callback ++ * ++ * this function is called from the physical driver module to notify user ++ * of CEVA device events. it pushed events data to each of the consumenrs ++ * kfifo object, and releases blocked read operations. ++ * @param [in] link 'this' module object ++ * @param [in] events array of events to push ++ * @param [in] sz number of events waiting in 'events' ++ * @return zero for success, nonzero for failure ++ */ ++int ceva_linkdrv_broadcast_events(struct ceva_linkdrv* link, ++ ceva_event_t* events, int sz) { ++ struct list_head *pos; ++ struct ceva_linkdrv_pfd *i; ++ int avail, ret; ++ unsigned long flags; ++ ++ XM6_MSG(XM6_MSG_DBG, "broadcast events\n"); ++ ++ if (!link->online) { ++ XM6_MSG(XM6_MSG_ERR, "link is not online\n"); ++ return -EPIPE; ++ } ++ ++ DEBUG_INFO_ADD(link, events_recieved, sz); ++ list_for_each(pos, &link->pfd_list) { ++ i = list_entry(pos, struct ceva_linkdrv_pfd, list_node); ++ if (!i) { ++ XM6_MSG(XM6_MSG_WRN, "list entry is NULL\n"); ++ continue; ++ } ++ link=i->owner; ++ // copy event data to the link's consumers ++ avail = kfifo_avail(&i->fifo); ++ if (!avail) { ++ DEBUG_INFO_INC(link, fifo_full); ++ XM6_MSG(XM6_MSG_WRN, "no available space for %s kfifo, %d missed\n", CEVA_LINKDRV_PROC_EVENTS_NAME,sz); ++ continue; ++ } ++ spin_lock_irqsave(&link->waiting_lock, flags); ++ ret = kfifo_in(&i->fifo, events, min(sz, avail)); ++ if (!ret) { ++ /* ++ * should we continue here? ++ * fifo is full, but perhaps user is blocked from some reason ++ * we should increment blocked anyway for the benefit of the doubt ++ */ ++ DEBUG_INFO_INC(link, fifo_in_err); ++ XM6_MSG(XM6_MSG_WRN, "unable to insert more data to descriptor %s's kfifo, " ++ "kfifo_avail returned with %d\n", CEVA_LINKDRV_PROC_EVENTS_NAME, avail); ++ } ++ /* ++ * check if user us waiting on events ++ */ ++ if (i->blocked) { ++ (*i->blocked)++; ++ } ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ } ++ // broadcast 'stop wait' for all waiting threads ++ wake_up_interruptible_all(&link->wq); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(ceva_linkdrv_broadcast_events); ++ ++/*! ++ * cancel any read operations blocked on the link's device (all entries) ++ * ++ * called by the module deinit function ++ * @param [in] link 'this' module object ++ * @return zero for success, nonzero for failure ++ * @see ceva_linkdrv_deinit ++ */ ++static int _ceva_linkdrv_proc_read_break(struct ceva_linkdrv *link) { ++ ++ struct list_head *pos; ++ struct ceva_linkdrv_pfd* i; ++ int j; ++ unsigned long flags; ++ ++ XM6_MSG(XM6_MSG_DBG, "canceling read on all events entries\n"); ++ spin_lock_irqsave(&link->waiting_lock, flags); ++ // drop all waiting receivers from link ++ list_for_each(pos, &link->pfd_list) { ++ // get iterator ++ i = list_entry(pos, struct ceva_linkdrv_pfd, list_node); ++ /* ++ * ensure blocked get negative value (irq might increment it ++ * after function exits) ++ */ ++ if (i->blocked) { ++ *(i->blocked) = UNBLOCKED_BY_USER; ++ } else { ++ // remove current entry from the list ++ list_del_init(&i->list_node); ++ // delete pfd object ++ _destroy_linkdrv_pfd(i); ++ } ++ } ++ spin_unlock_irqrestore(&link->waiting_lock, flags); ++ // broadcast 'stop wait' for all waiting threads ++ wake_up_interruptible_all(&link->wq); ++ ++ /* ++ * now we have to wait for all remaining pfds that are blocked, ++ * as we can't release the waitqueue until they stopped waiting on it ++ */ ++ for (j = 0; (j < CANCEL_READ_MAX_RELAX_TRIES && ++ !list_empty(&link->pfd_list)); j++) { ++ msleep(0); ++ } ++ if (j == CANCEL_READ_MAX_RELAX_TRIES) { ++ XM6_MSG(XM6_MSG_ERR, "unable to break all waiting read executions\n"); ++ return -EAGAIN; ++ } ++ return 0; ++} ++ ++#ifdef ENABLE_DEBUG ++ ++#define CEVA_LINKDRV_PROC_DEBUG "debug" ++static struct proc_dir_entry *ceva_linkdrv_proc_entry_debug; ++ ++static int _ceva_link_debug_proc_write_cb(struct file *file, ++ const char __user *buffer, unsigned long count, void *data) { ++ struct ceva_linkdrv *link = (struct ceva_linkdrv *) data; ++ char str[] = { "ABCD" }; ++ ceva_event_t event; ++ memcpy(&event, str, sizeof(ceva_event_t)); ++ ++ XM6_MSG(XM6_MSG_DBG, "sending event\n"); ++ ++ ceva_linkdrv_broadcast_events(link, &event, 1); ++ ++ return count; ++} ++ ++static int _ceva_link_debug_proc_init(struct ceva_linkdrv *link) ++{ ++ ++ ceva_linkdrv_proc_entry_debug = create_proc_read_entry( ++ CEVA_LINKDRV_PROC_DEBUG, /* name */ ++ S_IWUSR | S_IRUSR | S_IRGRP | S_IROTH, /* mode */ ++ ceva_linkdrv_proc_dir, /* parent */ ++ NULL, /* read */ ++ link); /* data */ ++ ++ if (!ceva_linkdrv_proc_entry_debug) ++ return -ENOMEM; ++ ++ ceva_linkdrv_proc_entry_debug->write_proc = ++ _ceva_link_debug_proc_write_cb; ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)) ++ ceva_linkdrv_proc_entry_debug->owner = THIS_MODULE; ++#endif /* KERNEL_VERSION(2,6,29) */ ++ ++ return 0; ++} ++ ++static void _ceva_link_debug_proc_deinit() ++{ ++ remove_proc_entry(CEVA_LINKDRV_PROC_DEBUG, ceva_linkdrv_proc_dir); ++} ++ ++#else ++ ++static int _ceva_link_debug_proc_init(struct ceva_linkdrv *link) { return 0; } ++static void _ceva_link_debug_proc_deinit() {} ++ ++#endif ++ ++/*! ++ * init module ++ * @param [in/out] link 'this' module object ++ * @return zero for success, nonzero for failure ++ */ ++int ceva_linkdrv_init(struct ceva_linkdrv *link, struct xm6_dev_data *owner) { ++ ++ int ret = 0; ++ ++ link->owner = owner; ++ mutex_init(&link->mux); ++ spin_lock_init(&link->waiting_lock); ++ INIT_LIST_HEAD(&link->pfd_list); ++ init_waitqueue_head(&link->wq); ++ ++ /* create directory */ ++ ceva_linkdrv_proc_dir = proc_mkdir(MODULE_NAME, NULL); ++ if(ceva_linkdrv_proc_dir == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)) ++ ceva_linkdrv_proc_dir->owner = THIS_MODULE; ++#endif /* KERNEL_VERSION(2,6,29) */ ++ XM6_MSG(XM6_MSG_DBG, "procfs dir created: %s\n", MODULE_NAME); ++ ++ if (_ceva_link_debug_proc_init(link) != 0) { ++ ret = -ENOMEM; ++ goto no_debug; ++ } ++ link->online = 1; ++ return 0; ++ ++no_debug: ++ remove_proc_entry(MODULE_NAME, NULL); ++out: ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ceva_linkdrv_init); ++ ++/*! ++ * deinit module ++ * ++ * @param [in/out] link 'this' module object ++ */ ++void ceva_linkdrv_deinit(struct ceva_linkdrv *link) { ++ ++ XM6_MSG(XM6_MSG_ERR, "ceva_linkdrv_deinit\n"); ++ Dump_ARMDSP_HndShakeInfo(); ++ link->online = 0; ++ _ceva_linkdrv_proc_read_break(link); ++ _ceva_link_debug_proc_deinit(); ++ remove_proc_entry(MODULE_NAME, NULL); ++ mutex_destroy(&link->mux); ++} ++EXPORT_SYMBOL_GPL(ceva_linkdrv_deinit); +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv.h b/drivers/sstar/ceva_link/ceva_linkdrv.h +new file mode 100644 +index 000000000000..00ff2a945b9a +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv.h +@@ -0,0 +1,79 @@ ++/* ++ * ceva_linkdrv.h ++ * ++ * Created on: Nov 12, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#ifndef CEVA_LINKDRV_H_ ++#define CEVA_LINKDRV_H_ ++ ++#include ++#include ++#include ++ ++#include "ceva_linkdrv-generic.h" ++ ++struct ceva_pcidev; ++ ++/*! ++ * type for CEVA event (32 bit) ++ */ ++typedef u32 ceva_event_t; ++ ++/*! ++ * logical module of ceva_linkdrv's ++ */ ++struct ceva_linkdrv { ++ int online; /*! indicates driver state */ ++ struct xm6_dev_data *owner; /*!< physical driver owner */ ++ spinlock_t waiting_lock; /*!< spin for critical sections */ ++ struct list_head pfd_list; /*!< private descriptors list */ ++ wait_queue_head_t wq; /*!< waitqueue for synchronization */ ++ struct mutex mux; /*!< internal mutex object */ ++#if defined(CEVA_LINKDRV_DEBUG) ++ union ceva_linkdrv_debug_info debug; /*!< debug statistics */ ++#endif ++}; ++ ++#if defined(CEVA_LINKDRV_DEBUG) ++#define DEBUG_INFO_INC(link, name) \ ++ do { (link)->debug.data.name++; } while( 0 ) ++#define DEBUG_INFO_DEC(link, name) \ ++ do { (link)->debug.data.name--; } while( 0 ) ++#define DEBUG_INFO_ADD(link, name, val) \ ++ do { (link)->debug.data.name += val; } while( 0 ) ++#define DEBUG_INFO_SUB(link, name, val) \ ++ do { (link)->debug.data.name -= val; } while( 0 ) ++#else ++#define DEBUG_INFO_INC(link, val) ++#define DEBUG_INFO_DEC(link, val) ++#define DEBUG_INFO_ADD(link, name, val) ++#define DEBUG_INFO_SUB(link, name, val) ++#endif ++ ++extern int ceva_linkdrv_broadcast_events(struct ceva_linkdrv* link, ++ ceva_event_t* events, int sz); ++extern int ceva_linkdrv_open_cb(struct ceva_linkdrv *link); ++extern int ceva_linkdrv_release_cb(struct ceva_linkdrv *link); ++extern long ceva_linkdrv_ioctl(struct ceva_linkdrv *link, unsigned int cmd, ++ unsigned long arg); ++extern int ceva_linkdrv_init(struct ceva_linkdrv* link, ++ struct xm6_dev_data *owner); ++extern void ceva_linkdrv_deinit(struct ceva_linkdrv* link); ++ ++#endif /* CEVA_LINKDRV_H_ */ +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv_proc.c b/drivers/sstar/ceva_link/ceva_linkdrv_proc.c +new file mode 100644 +index 000000000000..3262d411421c +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv_proc.c +@@ -0,0 +1,422 @@ ++#include ++#include ++#include /* Necessary because we use proc fs */ ++#include /* for seq_file */ ++#include ++#include ++#include ++ ++#include "ceva_linkdrv_xm6.h" ++#include "ceva_linkdrv_proc.h" ++#include "ms_platform.h" ++ ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++ ++static struct proc_dir_entry *proc_dir; ++ ++static u32 host_log_index = 0; ++static u32 host_log_size = 0; ++static u32 host_log_head = 0; ++static u32 host_log_tail = 0; ++static u8 *p_host_log_buf = NULL; ++ ++static u32 dsp_log_index = 0; ++static u32 dsp_log_size = 0; ++static u32 dsp_log_head = 0; ++static u32 dsp_log_tail = 0; ++static dsp_info_buf *p_dsp_info_buf = NULL; ++ ++static bool host_log_inited = false; ++static bool dsp_log_inited = false; ++static spinlock_t host_log_lock; ++static struct xm6_dev_data *p_dev_data = NULL; ++ ++static void* host_log_seq_start(struct seq_file *s, loff_t *pos) ++{ ++ if (host_log_size == 0) ++ { ++ return NULL; ++ } ++ ++ if ((*pos) == 0) ++ { ++ //seq_printf(s, "head = %d, tail=%d, size=%d, index=%d\n", host_log_head, host_log_tail, host_log_size, host_log_index); ++ *pos = host_log_index; ++ return (void *)(p_host_log_buf + host_log_index * HOST_LOG_LINE_SIZE); ++ } ++ ++ return NULL; ++} ++ ++static void* host_log_seq_next(struct seq_file *s, void *v, loff_t *pos) ++{ ++ int n = *pos; ++ ++ if (n < host_log_index) ++ { ++ n += HOST_LOG_MAX_LINE; ++ } ++ ++ if (n - host_log_index + 1 >= host_log_size) ++ { ++ return NULL; ++ } ++ ++ (*pos)++; ++ ++ if ((*pos) >= HOST_LOG_MAX_LINE) ++ { ++ *pos = 0; ++ } ++ ++ return (void *)(p_host_log_buf + (*pos) * HOST_LOG_LINE_SIZE); ++} ++ ++static void host_log_seq_stop(struct seq_file *s, void *v) ++{ ++ ++} ++ ++static int host_log_seq_show(struct seq_file *s, void *v) ++{ ++ seq_printf(s, "%s", (char *)v); ++ return 0; ++} ++ ++static struct seq_operations host_log_seq_ops = { ++ .start = host_log_seq_start, ++ .next = host_log_seq_next, ++ .stop = host_log_seq_stop, ++ .show = host_log_seq_show ++}; ++ ++static void* dsp_log_seq_start(struct seq_file *s, loff_t *pos) ++{ ++ if (p_dsp_info_buf == NULL) ++ { ++ return NULL; ++ } ++ ++ dsp_log_index = p_dsp_info_buf->dsp_log_index; ++ dsp_log_size = p_dsp_info_buf->dsp_log_size; ++ dsp_log_head = p_dsp_info_buf->dsp_log_head; ++ dsp_log_tail = p_dsp_info_buf->dsp_log_tail; ++ ++ if (dsp_log_size == 0) ++ { ++ return NULL; ++ } ++ ++ if ((*pos) == 0) ++ { ++ /* seq_printf(s, "head = %d, tail=%d, size=%d, index=%d\n", ++ dsp_log_head, ++ dsp_log_tail, ++ dsp_log_size, ++ dsp_log_index); */ ++ *pos = dsp_log_index; ++ return (void *)(&(p_dsp_info_buf->dsp_log_buf[0]) + dsp_log_index * DSP_LOG_LINE_SIZE); ++ } ++ ++ return NULL; ++} ++ ++static void* dsp_log_seq_next(struct seq_file *s, void *v, loff_t *pos) ++{ ++ int n = *pos; ++ ++ if (n < dsp_log_index) ++ { ++ n += DSP_LOG_MAX_LINE; ++ } ++ ++ if (n - dsp_log_index + 1 >= dsp_log_size) ++ { ++ return NULL; ++ } ++ ++ (*pos)++; ++ ++ if ((*pos) >= DSP_LOG_MAX_LINE) ++ { ++ *pos = 0; ++ } ++ ++ return (void *)(&(p_dsp_info_buf->dsp_log_buf[0]) + (*pos) * DSP_LOG_LINE_SIZE); ++} ++ ++static void dsp_log_seq_stop(struct seq_file *s, void *v) ++{ ++ ++} ++ ++static int dsp_log_seq_show(struct seq_file *s, void *v) ++{ ++ seq_printf(s, "%s", (char *)v); ++ return 0; ++} ++ ++static struct seq_operations dsp_log_seq_ops = { ++ .start = dsp_log_seq_start, ++ .next = dsp_log_seq_next, ++ .stop = dsp_log_seq_stop, ++ .show = dsp_log_seq_show ++}; ++ ++static int proc_host_log_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &host_log_seq_ops); ++} ++ ++static struct file_operations proc_host_log_ops = { ++ .owner = THIS_MODULE, // system ++ .open = proc_host_log_open, ++ .read = seq_read, // system ++ .llseek = seq_lseek, // system ++ .release = seq_release // system ++}; ++ ++static int proc_dsp_log_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &dsp_log_seq_ops); ++} ++ ++static struct file_operations proc_dsp_log_ops = { ++ .owner = THIS_MODULE, // system ++ .open = proc_dsp_log_open, ++ .read = seq_read, // system ++ .llseek = seq_lseek, // system ++ .release = seq_release // system ++}; ++ ++static int proc_reg_show(struct seq_file *m, void *v) ++{ ++ seq_printf(m, "ceva_sys0 regs:\n"); ++ seq_printf(m, "0x00 ~ 0x07: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x00), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x01), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x02), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x03), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x04), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x05), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x06), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x07) ++ ); ++ ++ seq_printf(m, "0x08 ~ 0x0F: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x08), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x09), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x0A), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x0B), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x0C), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x0D), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x0E), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x0F) ++ ); ++ ++ seq_printf(m, "0x10 ~ 0x17: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x10), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x11), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x12), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x13), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x14), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x15), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x16), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x17) ++ ); ++ ++ seq_printf(m, "0x18 ~ 0x1F: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x18), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x19), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x1A), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x1B), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x1C), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x1D), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x1E), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x1F) ++ ); ++ ++ seq_printf(m, "0x20 ~ 0x22: 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x20), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x21), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x22) ++ ); ++ ++ seq_printf(m, "0x40 ~ 0x44: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x40), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x41), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x42), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x43), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x44) ++ ); ++ ++ seq_printf(m, "0x60 ~ 0x63: 0x%04x 0x%04x 0x%04x 0x%04x\n", ++ REGR(p_dev_data->ceva_hal.base_sys, 0x60), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x61), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x62), ++ REGR(p_dev_data->ceva_hal.base_sys, 0x63) ++ ); ++ return 0; ++} ++ ++static int proc_reg_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, proc_reg_show, NULL); ++} ++ ++static struct file_operations proc_reg_ops = { ++ .owner = THIS_MODULE, // system ++ .open = proc_reg_open, ++ .read = seq_read, // system ++ .llseek = seq_lseek, // system ++ .release = seq_release // system ++}; ++ ++int host_log_init(void) ++{ ++ if (host_log_inited == true) ++ { ++ return 0; ++ } ++ ++ p_host_log_buf = kmalloc(HOST_LOG_BUF_MEM_SIZE, GFP_KERNEL); ++ if (p_host_log_buf == NULL) ++ { ++ return -ENOMEM; ++ } ++ ++ memset(p_host_log_buf, 0, HOST_LOG_BUF_MEM_SIZE); ++ spin_lock_init(&host_log_lock); ++ host_log_inited = true; ++ ++ return 0; ++} ++ ++void host_log_add(const char *fmt, ...) ++{ ++ char buf[HOST_LOG_LINE_SIZE]; ++ va_list args; ++ unsigned long flags; ++ ++ if (p_host_log_buf == NULL) ++ { ++ return; ++ } ++ ++ spin_lock_irqsave(&host_log_lock, flags); ++ ++ va_start(args, fmt); ++ vsnprintf(buf, HOST_LOG_LINE_SIZE, fmt, args); ++ va_end(args); ++ ++ buf[HOST_LOG_LINE_SIZE - 2] = '\n'; ++ buf[HOST_LOG_LINE_SIZE - 1] = '\0'; ++ memcpy((void *)(p_host_log_buf + host_log_head * HOST_LOG_LINE_SIZE), (void *)buf, HOST_LOG_LINE_SIZE); ++ ++ host_log_head++; ++ if (host_log_head >= HOST_LOG_MAX_LINE) ++ { ++ host_log_head = 0; ++ } ++ ++ host_log_tail = host_log_head + HOST_LOG_MAX_LINE - 1; ++ if (host_log_tail >= HOST_LOG_MAX_LINE) ++ { ++ host_log_tail = host_log_tail - HOST_LOG_MAX_LINE; ++ } ++ ++ host_log_size++; ++ if (host_log_size >= HOST_LOG_MAX_LINE) ++ { ++ host_log_size = HOST_LOG_MAX_LINE; ++ } ++ ++ if (host_log_tail >= host_log_size - 1) ++ { ++ host_log_index = host_log_tail - host_log_size + 1; ++ } ++ else ++ { ++ host_log_index = host_log_tail + HOST_LOG_MAX_LINE - host_log_size + 1; ++ } ++ ++ spin_unlock_irqrestore(&host_log_lock, flags); ++} ++ ++int dsp_log_init(phys_addr_t phy_addr, u32 size) ++{ ++ void *virt_addr; ++ ++ if (dsp_log_inited == true) ++ { ++ return 0; ++ } ++ ++ if (request_mem_region(phy_addr, size, "dsp_log_buf") == NULL) ++ { ++ return -ENOMEM; ++ } ++ ++ virt_addr = ioremap_nocache(phy_addr, size); ++ if (virt_addr == NULL) ++ { ++ return -ENOMEM; ++ } ++ ++ p_dsp_info_buf = (dsp_info_buf *)(virt_addr); ++ memset(p_dsp_info_buf, 0, size); ++ Chip_Flush_MIU_Pipe(); ++ dsp_log_inited = true; ++ ++ return 0; ++} ++ ++int ceva_linkdrv_proc_init(struct xm6_dev_data *p_data) ++{ ++ struct proc_dir_entry *pde; ++ ++ proc_dir = proc_mkdir("ceva_link", NULL); ++ if (!proc_dir) ++ { ++ return -1; ++ } ++ ++ pde = proc_create("host_log", S_IRUGO, proc_dir, &proc_host_log_ops); ++ if (!pde) ++ { ++ goto out_ceva_link; ++ } ++ ++ pde = proc_create("dsp_log", S_IRUGO, proc_dir, &proc_dsp_log_ops); ++ if (!pde) ++ { ++ goto out_host_log; ++ } ++ ++ pde = proc_create("reg", S_IRUGO, proc_dir, &proc_reg_ops); ++ if (!pde) ++ { ++ goto out_dsp_log; ++ } ++ ++ p_dev_data = p_data; ++ ++ return 0; ++ ++out_dsp_log: ++ remove_proc_entry("dsp_log", proc_dir); ++out_host_log: ++ remove_proc_entry("host_log", proc_dir); ++out_ceva_link: ++ remove_proc_entry("ceva_link", NULL); ++ ++ return -1; ++} ++ ++void ceva_linkdrv_proc_exit(void) ++{ ++ remove_proc_entry("reg", proc_dir); ++ remove_proc_entry("dsp_log", proc_dir); ++ remove_proc_entry("host_log", proc_dir); ++ remove_proc_entry("ceva_link", NULL); ++} +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv_proc.h b/drivers/sstar/ceva_link/ceva_linkdrv_proc.h +new file mode 100644 +index 000000000000..25f65d09181b +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv_proc.h +@@ -0,0 +1,37 @@ ++#ifndef CEVA_LINKDRV_PROC_H_ ++#define CEVA_LINKDRV_PROC_H_ ++ ++#define HOST_LOG_ENABLE 1 ++#define HOST_LOG_BUF_MEM_SIZE (1 * 4096) ++#define INVALID_DSP_LOG_ADDR 0xFFFFFFFF ++ ++#define HOST_LOG_MAX_LINE 30 ++#define HOST_LOG_LINE_SIZE 128 ++#define DSP_LOG_MAX_LINE 30 ++#define DSP_LOG_LINE_SIZE 128 ++ ++#define HOST_LOG_TITLE "[%s] " ++#define HOST_LOG_FUNC __func__ ++ ++#if HOST_LOG_ENABLE ++#define HOST_LOG(_fmt, _args...) \ ++ host_log_add(HOST_LOG_TITLE _fmt, HOST_LOG_FUNC, ## _args); ++#else ++#define HOST_LOG(_fmt, _args...) ++#endif ++ ++typedef struct { ++ u32 dsp_log_head; ++ u32 dsp_log_tail; ++ u32 dsp_log_size; ++ u32 dsp_log_index; ++ u8 dsp_log_buf[DSP_LOG_MAX_LINE * DSP_LOG_LINE_SIZE]; ++} dsp_info_buf; ++ ++extern int host_log_init(void); ++extern void host_log_add(const char *fmt, ...); ++extern int dsp_log_init(phys_addr_t phy_addr, u32 size); ++extern int ceva_linkdrv_proc_init(struct xm6_dev_data *p_data); ++extern void ceva_linkdrv_proc_exit(void); ++ ++#endif /* CEVA_LINKDRV_PROC_H_ */ +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv_shared_process_protected_db_def_copy.h b/drivers/sstar/ceva_link/ceva_linkdrv_shared_process_protected_db_def_copy.h +new file mode 100644 +index 000000000000..adaca2cc9bac +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv_shared_process_protected_db_def_copy.h +@@ -0,0 +1,20 @@ ++#ifndef CEVA_LINKDRV_SHARED_PROCESS_PROTECTED_DB_DEF_H_ ++#define CEVA_LINKDRV_SHARED_PROCESS_PROTECTED_DB_DEF_H_ ++ ++#define PROTECTED_MEM_DB_FILENAME "/dev/protected_mem_db" ++ ++ ++#define CEVALINK_MAX_CLIENT (0x10) ++ ++typedef struct { ++ int client_list[CEVALINK_MAX_CLIENT]; ++} ceva_linkdrv_shared_process_protected_db; ++ ++#define IOC_CEVADRV_PROTMEM_MAGIC (0xFB) ++ ++#define IOC_CEVADRV_PROTMEM_LOCK _IOW(IOC_CEVADRV_PROTMEM_MAGIC, 1, int) ++#define IOC_CEVADRV_PROTMEM_UNLOCK _IOW(IOC_CEVADRV_PROTMEM_MAGIC, 2, int) ++ ++#define IOC_CEVADRV_PROTMEM_MAXNR 2 ++ ++#endif /* CEVA_LINKDRV_SHARED_PROCESS_PROTECTED_DB_DEF_H_ */ +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv_xm6.c b/drivers/sstar/ceva_link/ceva_linkdrv_xm6.c +new file mode 100644 +index 000000000000..487ffe06e027 +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv_xm6.c +@@ -0,0 +1,1637 @@ ++/* ++ * ceva_linkdrv_xm6.c ++ * ++ * Created on: Sep 12, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ceva_linkdrv-generic.h" ++#include "protected_mem_db.h" ++#include "ceva_linkdrv.h" ++#include "ceva_linkdrv_xm6.h" ++#include "drv_debug.h" ++#include "ceva_linkdrv_proc.h" ++ ++#include "boot_loader.h" ++#include "ms_platform.h" ++#include "mstar_chip.h" ++//#include "ms_version.h" ++ ++ ++#define XM6_DRV_DEVICE_COUNT (1) // How many device will be installed ++#define XM6_DRV_NAME "mstar_dsp" ++#define XM6_DRV_MINOR (0) ++#define XM6_DRV_CLASS_NAME "mstar_dsp_class" ++ ++#define HPRINTF_MEM_SIZE (16*4096) ++// #define HPRINTF_DUMP_AFTER_RELEASE ++ ++#define MCCI_LINK_EVENT_FROM_HOST 0 ++#define MCCI_LINK_EVENT_FROM_DSP 1 ++#define MCCI_PRINT_FROM_DSP 2 ++#define MCCI_IRQ_UNEXPECT 0xFFFFFFF9 // only bit 1 & 2 will be trigger ++ ++MODULE_AUTHOR("Ido Reis "); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION("1.0.1"); ++MODULE_DESCRIPTION("mapped pci character device driver"); ++ ++//#define FUNC_SHOULD_REMOVE ++ ++static int xm6_drv_open(struct inode *inode, struct file *filp); ++static int xm6_drv_release(struct inode *inode, struct file *filp); ++static ssize_t xm6_drv_read(struct file *filp, char __user *buf, size_t count, loff_t *pos); ++static ssize_t xm6_drv_write(struct file *filp, const char __user *buf, size_t count, loff_t *pos); ++static long xm6_drv_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++static void xm6_drv_dma_vma_open(struct vm_area_struct *vma); ++static void xm6_drv_dma_vma_close(struct vm_area_struct *vma); ++static int xm6_drv_mmap_dma(struct xm6_dev_data *dev_data, struct vm_area_struct *vma); ++static int xm6_drv_mmap(struct file *filp, struct vm_area_struct *vma); ++static void xm6_drv_cleanup_module(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++static int xm6_drv_setup_cdev(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++static int ceva_linkdrv_init_module(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++static void xm6_drv_dump_dsp_log(struct xm6_dev_data *dev_data); ++//static u8 xm6_drv_get_revision(struct platform_device *plat_dev); ++//static u8 xm6_drv_get_irq(struct platform_device *plat_dev); ++//static struct platform_device* find_upstream_dev(struct platform_device *plat_dev); ++//static void retrain_gen2(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++//static int probe_enable_pci_dev(struct platform_device *plat_dev); ++//static void remove_disable_pci_dev(struct platform_device *plat_dev); ++static int probe_get_hw_prop(struct platform_device* plat_dev, struct xm6_dev_data *dev_data); ++static int ceva_link_generate_irq(struct xm6_dev_data *dev_data, ceva_event_t e); ++//static int scan_bars(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++//static int map_bars(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++//static void free_bars(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++//static int probe_map_bars(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++//static void probe_map_dma(struct xm6_dev_data *dev_data); ++static irqreturn_t ceva_linkdrv_interrupt(int irq, void *dev_id); ++static int probe_init_irq(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++static void remove_deinit_irq(struct platform_device *plat_dev, struct xm6_dev_data *dev_data); ++static int xm6_drv_probe(struct platform_device *plat_dev); ++static s32 xm6_drv_remove(struct platform_device *plat_dev); ++int __init xm6_drv_init_module(void); ++void __exit xm6_drv_exit_module(void); ++static void Init_XM6FW_VerInfo(void); ++static void dump_XM6VerInfo(struct Version_Info *pVerInfo); ++ ++static ceva_hal_handle *pGceva_hal; ++ ++static unsigned int SendDSPCount=0; ++static unsigned int GotDSPCount=0; ++ ++/*! ++ * ops for dma mapped memory ++ */ ++static struct vm_operations_struct xm6_drv_dma_vma_ops = { ++ .open = xm6_drv_dma_vma_open, ++ .close = xm6_drv_dma_vma_close ++}; ++ ++/*! ++ * fops for this driver's device ++ */ ++static struct file_operations xm6_drv_fops = { ++ .owner = THIS_MODULE, ++ .read = xm6_drv_read, ++ .write = xm6_drv_write, ++ .open = xm6_drv_open, ++ .release = xm6_drv_release, ++ .unlocked_ioctl = xm6_drv_ioctl, ++ .llseek = no_llseek, /* This driver doesn't support llseek */ ++ .mmap = xm6_drv_mmap, ++}; ++ ++/*! ++ * xm6 driver module fops ++ */ ++static const struct of_device_id xm6_drv_match[] = { ++ { ++ .compatible = "sstar,infinity2-xm6", ++ /*.data = NULL,*/ ++ }, ++ {}, ++}; ++ ++static struct platform_driver xm6_drv_driver = { ++ .probe = xm6_drv_probe, ++ .remove = xm6_drv_remove, ++ // .suspend = xm6_drv_suspend, ++ // .resume = xm6_drv_resume, ++ ++ .driver = { ++ .of_match_table = of_match_ptr(xm6_drv_match), ++ .name = "sstar_xm6", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++/* Use a struct to gather all global variable when registering a char device*/ ++static struct ++{ ++ int major; // cdev major number ++ int minor_star; // begining of cdev minor number ++ int reg_count; // registered count ++ struct class *class; // class pointer ++} xm6_drv_data = {0, 0, 0, NULL}; ++ ++static struct Version_Info *pVerInfo; ++static struct Version_Info VerInfo; ++ ++static void dump_XM6VerInfo(struct Version_Info *pVerInfo) ++{ ++ XM6_MSG(XM6_MSG_DBG, "Version_Info CEVA_VInfo Main.Second.Sub : %d.%d.%d \n", pVerInfo->CEVA_VInfo.Main,pVerInfo->CEVA_VInfo.Second,pVerInfo->CEVA_VInfo.Sub); ++ XM6_MSG(XM6_MSG_DBG, "Version_Info FormalReleaseFlg: %d \n", pVerInfo->FormalReleaseFlg); ++ XM6_MSG(XM6_MSG_DBG, "Version_Info GitBranch: %s \n", pVerInfo->GitBranch); ++ XM6_MSG(XM6_MSG_DBG, "Version_Info GitVersion: %s \n", pVerInfo->GitVersion); ++ XM6_MSG(XM6_MSG_DBG, "Version_Info BuildCodeData: %s \n", pVerInfo->BuildCodeData); ++ return; ++} ++ ++static void Init_XM6FW_VerInfo(void) ++{ ++ pVerInfo=&VerInfo; ++ ++ memset(pVerInfo,0,sizeof(struct Version_Info)); ++ ++ pVerInfo->CEVA_VInfo.Main=CEVA_SRC_VERSION; ++ pVerInfo->CEVA_VInfo.Second=CEVA_LOCAL_LIB_VERSION; ++ pVerInfo->CEVA_VInfo.Sub=CEVA_SUBVERSION; ++ ++ pVerInfo->FormalReleaseFlg=SERVER_BUILD; ++ memcpy(pVerInfo->GitBranch,CEVA_XM6_GIT_BRANCH,strlen(CEVA_XM6_GIT_BRANCH)); ++ memcpy(pVerInfo->GitVersion,CEVA_XM6_GIT_VERSION,strlen(CEVA_XM6_GIT_VERSION)); ++ memcpy(pVerInfo->BuildCodeData,CEVA_XM6_BUILD_DATE,strlen(CEVA_XM6_BUILD_DATE)); ++ ++ dump_XM6VerInfo(pVerInfo); ++ return; ++} ++ ++void Dump_ARMDSP_HndShakeInfo(void) ++{ ++ unsigned int GPOut=0; ++ ++ XM6_MSG(XM6_MSG_ERR, "%s \n",__FUNCTION__); ++ XM6_MSG(XM6_MSG_ERR, "ARM Side View: SendDSPCount:0x%x GotDSPCount:0x%x \n",SendDSPCount,GotDSPCount); ++ GPOut=dsp_ceva_hal_read_gpout(pGceva_hal); ++ XM6_MSG(XM6_MSG_ERR, "DSP Side View: DSPStatus:0x%x DSPProcessCount:0x%x \n",((GPOut>>24)&0xff),(GPOut&0xffffff)); ++ return; ++} ++ ++ ++/*! ++ * open handler ++ * ++ * called when user opens the device. ++ * each open call increment the ref_count variable. ++ * when opened for the first time (e.g ref_count = 1) it initializes the ++ * ceva_linkdrv logic module. ++ * for each call, it also executes the ceva_linkdrv_open_cb to notify the ++ * logical module of the user operation. ++ * @param [in] inode ++ * @param [in] filp ++ * @return zero for success, nonzero for failure ++ * @see ceva_linkdrv_init(), ceva_linkdrv_open_cb() ++ */ ++static int xm6_drv_open(struct inode *inode, struct file *filp) { ++ int ret = 0; ++#if 0 ++ unsigned int mj = imajor(inode); ++ unsigned int mn = iminor(inode); ++#endif ++ struct xm6_dev_data *dev_data = NULL; ++ ++#if 0 ++ if (mj != xm6_drv_major || mn < 0 || ++ mn >= CEVA_PCIDEV_NUMBER_OF_DEVICES) { ++ XM6_MSG(XM6_MSG_DBG, "No device found with minor=%d and major=%d", ++ mj, mn); ++ ret = -ENODEV; /* No such device */ ++ goto exit; ++ } ++#endif ++ ++ /* store a pointer to struct cfake_dev here for other methods */ ++ dev_data = container_of(inode->i_cdev, struct xm6_dev_data, cdev); ++ filp->private_data = dev_data; ++ ++ XM6_MSG(XM6_MSG_DBG, "open filp %p, device %p\n", filp, dev_data); ++ ++ if (inode->i_cdev != &dev_data->cdev) { ++ XM6_MSG(XM6_MSG_WRN, "open: internal error\n"); ++ ret = -ENODEV; /* No such device */ ++ goto exit; ++ } ++ /* This method can't fail, so no need to check for return value */ ++ nonseekable_open(inode, filp); ++ ++ if (mutex_lock_interruptible(&dev_data->dev_mutex)) { ++ return -EINTR; ++ } ++ ++ if (dev_data->count == 0) { ++ ret = ceva_linkdrv_init(&dev_data->linkdrv, dev_data); ++ } ++ ++ if (!ret) { ++ ret = ceva_linkdrv_open_cb(&dev_data->linkdrv); ++ if (!ret) { ++ dev_data->count++; ++ } else { ++ if (dev_data->count == 0) { ++ ceva_linkdrv_deinit(&dev_data->linkdrv); ++ } ++ } ++ } ++ ++ mutex_unlock(&dev_data->dev_mutex); ++ ++exit: ++ return ret; ++} ++ ++/*! ++ * close handler ++ * ++ * called when user closes the device. ++ * each open call decrement the ref_count variable. ++ * for each call, it executes the ceva_linkdrv_release_cb to notify the ++ * logical module of the user operation. ++ * when closed for the last time (e.g ref_count = 0) it deinitializes the ++ * ceva_linkdrv logic module. ++ * @param [in] inode ++ * @param [in] filp ++ * @return zero for success, nonzero for failure ++ * @see ceva_linkdrv_deinit(), ceva_linkdrv_release_cb() ++ */ ++static int xm6_drv_release(struct inode *inode, struct file *filp) { ++ int ret; ++ struct xm6_dev_data *dev_data = (struct xm6_dev_data *) filp->private_data; ++ ++ XM6_MSG(XM6_MSG_DBG, "release filp %p, device %p\n", filp, dev_data); ++ ++ xm6_drv_dump_dsp_log(dev_data); ++ ++ if (mutex_lock_interruptible(&dev_data->dev_mutex)) { ++ return -EINTR; ++ } ++ ret = ceva_linkdrv_release_cb(&dev_data->linkdrv); ++ if (dev_data->count) ++ dev_data->count--; ++ if (!dev_data->count) { ++ ceva_linkdrv_deinit(&dev_data->linkdrv); ++ } ++ mutex_unlock(&dev_data->dev_mutex); ++ ++ return ret; ++} ++ ++/*! ++ * read handler ++ * ++ * reads data from bar0 of the pci device, from a relative offset. ++ * as the user interface does not include an offset argument, the user ++ * has to write the offset value into the buf. the driver first read from ++ * buf the offset value and user actual buffer address, and then reads ++ * the data into the forwarded user supplied address. ++ * @param [in] filp device handler ++ * @param [in/out] buf output buffer to read data to ++ * @param [in] count number of bytes to read ++ * @param [in] pos offset (not used) ++ * @return number of bytes read from bar0, negative values for errors ++ * @see struct RWBuffer, xm6_drv_write() ++ */ ++static ssize_t xm6_drv_read(struct file *filp, char __user *buf, size_t count, loff_t *pos) { ++ struct xm6_dev_data *dev_data = (struct xm6_dev_data *) filp->private_data; ++ struct RWBuffer rwbuf; ++ ssize_t ret = 0; ++ ++ XM6_MSG(XM6_MSG_DBG, "read filp %p, device %p\n", filp, dev_data); ++ ++ if (!count) { ++ return 0; ++ } ++ ++ if (!access_ok(VERIFY_WRITE, buf, count)) { ++ XM6_MSG(XM6_MSG_ERR, "access error\n"); ++ return -EFAULT; ++ } ++ ++ if (mutex_lock_interruptible(&dev_data->dev_mutex)) { ++ XM6_MSG(XM6_MSG_ERR, "unable to lock mutex\n"); ++ return -EINTR; ++ } ++ ++ // read offset from buf ++ if (copy_from_user(&rwbuf, buf, sizeof(rwbuf)) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "could not read from user buffer\n"); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++#if 0 // ORIGINAL_PCI_BAR ++ // read content of bar 0 to buf ++ if (copy_to_user(rwbuf.buf, ++ ((char *)dev_data->bar[0]) + rwbuf.offset, count) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "%s -> copy to user failed", __FUNCTION__); ++ ret = -EFAULT; ++ goto out; ++ } ++#else ++ XM6_MSG(XM6_MSG_ERR, "copy_to_user bar[0], offset %lu, size %d\n", rwbuf.offset, count); ++#endif ++ *pos += ret; ++ ret = count; ++out: ++ mutex_unlock(&dev_data->dev_mutex); ++ return ret; ++} ++ ++/*! ++ * write handler ++ * ++ * writes data to bar0 of the pci device, to a relative offset. ++ * as the user interface does not include an offset argument, the user ++ * has to write the offset value into the buf. the driver first read from ++ * buf the offset value and user actual buffer address, and then writes ++ * the data from the user buffer to bar0 base address plus the offset. ++ * @param [in] filp device handler ++ * @param [in] buf output buffer to read data to ++ * @param [in] count number of bytes to read ++ * @param [in] pos offset (not used) ++ * @return number of bytes read from bar0, negative values for errors ++ * @see struct RWBuffer, xm6_drv_read() ++ */ ++static ssize_t xm6_drv_write(struct file *filp, const char __user *buf, size_t count, loff_t *pos) { ++ struct xm6_dev_data *dev_data = (struct xm6_dev_data *) filp->private_data; ++ struct RWBuffer rwbuf; ++ ssize_t ret = 0; ++ ++ XM6_MSG(XM6_MSG_DBG, "write filp %p, device %p\n", filp, dev_data); ++ ++ if (!count) { ++ return 0; ++ } ++ ++ if (!access_ok(VERIFY_READ, buf, count)) { ++ XM6_MSG(XM6_MSG_ERR, "access error\n"); ++ return -EFAULT; ++ } ++ ++ if (mutex_lock_interruptible(&dev_data->dev_mutex)) { ++ XM6_MSG(XM6_MSG_ERR, "unable to lock mutex\n"); ++ return -EINTR; ++ } ++ ++ // read offset from buf ++ if (copy_from_user(&rwbuf, buf, sizeof(rwbuf)) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "could not read from user buffer\n"); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++#if 0 // ORIGINAL_PCI_BAR ++ // write content of buf to bar 0 ++ if (copy_from_user(((char *)dev_data->bar[0]) + rwbuf.offset, ++ rwbuf.buf, count) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "%s -> copy from user failed", __FUNCTION__); ++ ret = -EFAULT; ++ goto out; ++ } ++#else ++ XM6_MSG(XM6_MSG_ERR, "copy_from_user bar[0], offset %lu, size %d\n", rwbuf.offset, count); ++#endif ++ ++ *pos += count; ++ ret = count; ++ ++out: ++ mutex_unlock(&dev_data->dev_mutex); ++ return ret; ++} ++ ++static phys_addr_t xm6_drv_miu2phys(u64 miu_addr) ++{ ++ if(miu_addr >= (u64)ARM_MIU2_BASE_ADDR) ++ { ++ return (phys_addr_t)(miu_addr + ARM_MIU2_BUS_BASE - ARM_MIU2_BASE_ADDR); ++ } ++ else if(miu_addr >= (u64)ARM_MIU1_BASE_ADDR) ++ { ++ return (phys_addr_t)(miu_addr + ARM_MIU1_BUS_BASE - ARM_MIU1_BASE_ADDR); ++ } ++ else if(miu_addr >= (u64)ARM_MIU0_BASE_ADDR) ++ { ++ return (phys_addr_t)(miu_addr + ARM_MIU0_BUS_BASE - ARM_MIU0_BASE_ADDR); ++ } ++ ++ return (phys_addr_t)-1; ++} ++ ++static u64 xm6_drv_phys2miu(phys_addr_t phys_addr) ++{ ++ if(phys_addr >= (phys_addr_t)ARM_MIU2_BUS_BASE) ++ { ++ return (u64)(phys_addr - ARM_MIU2_BUS_BASE+ARM_MIU2_BASE_ADDR); ++ } ++ else if(phys_addr >= (phys_addr_t)ARM_MIU1_BUS_BASE) ++ { ++ return (u64)(phys_addr - ARM_MIU1_BUS_BASE+ARM_MIU1_BASE_ADDR); ++ } ++ else if(phys_addr >= (phys_addr_t)ARM_MIU0_BUS_BASE) ++ { ++ return (u64)(phys_addr - ARM_MIU0_BUS_BASE+ARM_MIU0_BASE_ADDR); ++ } ++ ++ return (u64)-1ULL; ++} ++ ++static void* xm6_drv_ioremap(phys_addr_t phys, int size) ++{ ++ unsigned long aligned_size, start, end; ++ struct vm_struct *area; ++ void *addr; ++ int err; ++ ++ aligned_size = PAGE_ALIGN(size); ++ ++ XM6_MSG(XM6_MSG_DBG, "phys: 0x%x, size: %d, aligned_size: %ld (%ld)\n", phys, size, aligned_size, PAGE_SIZE); ++ ++ area = get_vm_area(aligned_size, /*VM_USERMAP*//*VM_MAP*/VM_IOREMAP); ++ if(!area) ++ { ++ XM6_MSG(XM6_MSG_ERR, "get_vm_area_caller failed\n"); ++ return NULL; ++ } ++ ++ area->phys_addr = phys; // ? ++ addr = area->addr; ++ ++ start = (unsigned long)addr; ++ end = start + aligned_size; ++ ++ XM6_MSG(XM6_MSG_DBG, "area->phys_addr: 0x%lx, area->addr: %p, start: 0x%lx, end: 0x%lx\n", (unsigned long)area->phys_addr, area->addr, start, end); ++ ++ err = ioremap_page_range(start, end, area->phys_addr, pgprot_writecombine(PAGE_KERNEL)/*PAGE_KERNEL*/); ++ if(err) ++ { ++ vunmap(addr); ++ XM6_MSG(XM6_MSG_ERR, "ioremap_page_range failed\n"); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++static void xm6_drv_iounmap(void *virt) ++{ ++ vunmap(virt); ++} ++ ++static int xm6_drv_assign_dsp_buffer(dev_dsp_buf *dev_buf, struct boot_buffer_t *boot_buf, int need_virt) ++{ ++ memset(dev_buf, 0, sizeof(dev_dsp_buf)); ++ ++ if (boot_buf->size == 0 ) ++ return -ENOMEM; ++ ++ // From physical ++ if (boot_buf->phys != 0) { ++ dev_buf->is_from_miu = 0; ++ dev_buf->size = boot_buf->size; ++ dev_buf->phys = boot_buf->phys; ++ ++ // When user assign the physical address, it means the memory is from Linux managed heap. ++ // So we can get the virtual address via phys_to_virt() directly and ioremap() does not work in this case. ++ // Please refer https://stackoverflow.com/questions/43127794/why-shouldnt-i-use-ioremap-on-system-memory-for-armv6 ++ if (need_virt) ++ dev_buf->virt = phys_to_virt(dev_buf->phys); ++ ++ // From MIU ++ } else if (boot_buf->miu != 0) { ++ dev_buf->is_from_miu = 1; ++ dev_buf->size = boot_buf->size; ++ dev_buf->phys = xm6_drv_miu2phys(boot_buf->miu); ++ ++ // When user assign the miu buffer, it means memory is out of Linux management. ++ // So we get the virtual address from ioremap(), and phys_to_virt() does not work in this case. ++ if (need_virt) ++ dev_buf->virt = xm6_drv_ioremap(dev_buf->phys, dev_buf->size); ++ ++ } else { ++ return -ENOMEM; ++ } ++ ++ dev_buf->size = boot_buf->size; ++ ++ return 0; ++} ++ ++static int xm6_drv_init_dsp_buffer(struct xm6_dev_data *dev_data, struct boot_config_t *boot_config) ++{ ++ // share memory size check ++ if (boot_config->share_mem.size <= HPRINTF_MEM_SIZE) ++ { ++ XM6_MSG(XM6_MSG_ERR, "share memory is too small.\n"); ++ return -ENOMEM; ++ } ++ ++ // boot_image ++ if (xm6_drv_assign_dsp_buffer(&dev_data->boot_image, &boot_config->boot_image, 0) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "boot image is not assigned.\n"); ++ return -ENOMEM; ++ } ++ ++ // ext_heap ++ if (xm6_drv_assign_dsp_buffer(&dev_data->ext_heap, &boot_config->ext_heap, 0) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "external heap is not assigned.\n"); ++ return -ENOMEM; ++ } ++ ++ // work_buffer, it could be NULL ++ xm6_drv_assign_dsp_buffer(&dev_data->work_buffer, &boot_config->work_buffer, 0); ++ ++ // share_mem ++ if (xm6_drv_assign_dsp_buffer(&dev_data->share_mem, &boot_config->share_mem, 1) != 0) { ++ XM6_MSG(XM6_MSG_ERR, "share memory is not assigned.\n"); ++ return -ENOMEM; ++ } ++ ++ // Check virtual address of share_mem ++ if (dev_data->share_mem.virt == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "can't get virtual address for share memory.\n"); ++ return -EINVAL; ++ } ++ ++ XM6_MSG(XM6_MSG_DBG, "share memory: miu: 0x%llx, phys: 0x%x, virt: %p\n", boot_config->share_mem.miu, (int)dev_data->share_mem.phys, dev_data->share_mem.virt); ++ ++ // Reset share_mem ++ memset(dev_data->share_mem.virt, 0, dev_data->share_mem.size); ++ ++ // The sahre memory is seperated into 2 part, share (DMA) memory and hprintf buffer, both are shared between DSP and host. ++ ++ // Assign hprintf buffer, we put hprintf buffer first because this is also used for boot copier and it must page-alignment ++ dev_data->hprintf_buf.virt = dev_data->share_mem.virt; ++ dev_data->hprintf_buf.phys = dev_data->share_mem.phys; ++ dev_data->hprintf_buf.size = HPRINTF_MEM_SIZE; ++ dev_data->hprintf_buf.is_from_miu = dev_data->share_mem.is_from_miu; ++ ++ // Assign DMA buffer ++ dev_data->dma_buf.size = dev_data->share_mem.size - HPRINTF_MEM_SIZE; ++ dev_data->dma_buf.priv_data = dev_data; ++ dev_data->dma_buf.dma_addr = (dma_addr_t)dev_data->share_mem.phys + HPRINTF_MEM_SIZE; ++ dev_data->dma_buf.cpu_addr = dev_data->share_mem.virt + HPRINTF_MEM_SIZE; ++ ++ return 0; ++} ++ ++#ifdef HPRINTF_DUMP_AFTER_RELEASE ++static char* xm6_drv_dump_and_get_next_dsp_log(char *log) ++{ ++ int i; ++ ++ for (i = 0; log[i] != '\0' && log[i] != '\n'; i++) ++ { ++ if (log[i] == '\r') ++ log[i] = ' '; ++ } ++ ++ if (log[i] == '\0') ++ { ++ return NULL; ++ } ++ ++ log[i] = '\0'; ++ printk("%p: %s\n", log, log); ++ log[i] = '\n'; ++ ++ return log + i + 1; ++} ++#endif // HPRINTF_DUMP_AFTER_RELEASE ++ ++static void xm6_drv_dump_dsp_log(struct xm6_dev_data *dev_data) ++{ ++#ifdef HPRINTF_DUMP_AFTER_RELEASE ++ int i; ++ char *log = dev_data->hprintf_buf.virt; ++ ++ if (log == NULL) ++ return; ++ ++ printk("==== Dump DSP last log (from %p) ====\n", log); ++ ++ // Find the first half log ++ for (i = 0; log[i] != '\0'; i++){} ++ log += i + 1; ++ ++ printk("fist half: %p, %d\n", log, i); ++ ++ // Dump the first half log ++ while (log != NULL) ++ { ++ log = xm6_drv_dump_and_get_next_dsp_log(log); ++ } ++ ++ printk("second half: %p\n", dev_data->hprintf_buf.virt); ++ ++ // Dump the second half log ++ log = dev_data->hprintf_buf.virt; ++ while (log != NULL) ++ { ++ log = xm6_drv_dump_and_get_next_dsp_log(log); ++ } ++ ++ printk("==== Dump DSP last log ====\n"); ++#endif // HPRINTF_DUMP_AFTER_RELEASE ++} ++ ++static void xm6_drv_deinit_dsp_buffer(struct xm6_dev_data *dev_data) ++{ ++ xm6_drv_dump_dsp_log(dev_data); ++ ++ if (dev_data->share_mem.is_from_miu) { ++ xm6_drv_iounmap(dev_data->share_mem.virt); ++ } ++ ++ memset(&dev_data->boot_image, 0, sizeof(dev_dsp_buf)); ++ memset(&dev_data->ext_heap, 0, sizeof(dev_dsp_buf)); ++ memset(&dev_data->share_mem, 0, sizeof(dev_dsp_buf)); ++ memset(&dev_data->hprintf_buf, 0, sizeof(dev_dsp_buf)); ++ memset(&dev_data->work_buffer, 0, sizeof(dev_dsp_buf)); ++ ++ memset(&dev_data->dma_buf, 0, sizeof(xm6_dev_dma_buf)); ++} ++ ++static int xm6_drv_dsp_boot_up(struct xm6_dev_data *dev_data, struct boot_config_t *boot_config) ++{ ++ int ret; ++ dsp_mem_info_t dsp_mem_info; ++ dev_dsp_buf copier_buf; ++ u8 *image_virt=NULL; ++ ++ if (dev_data->is_dsp_boot_up) ++ { ++ XM6_MSG(XM6_MSG_ERR, "DSP is boot up already\n"); ++ return -EISCONN; ++ } ++ ++ // backup data ++ memcpy(&dev_data->boot_config, boot_config, sizeof(dev_data->boot_config)); ++ ++ // init all dsp buffers ++ ret = xm6_drv_init_dsp_buffer(dev_data, boot_config); ++ if (unlikely(ret != 0)) { ++ XM6_MSG(XM6_MSG_ERR, "probe_init_dsp_buffer() failed\n"); ++ return -EISCONN; ++ } ++ image_virt=dev_data->boot_image.virt; ++ ++ //if (dev_data->boot_config.log_enable != 0) ++ if(0) ++ { ++ ret = host_log_init(); ++ if (unlikely(ret != 0)) { ++ XM6_MSG(XM6_MSG_ERR, "host_log_init() failed\n"); ++ return -ENOMEM; ++ } ++ ++ ret = dsp_log_init(dev_data->boot_config.dsp_log_addr, ++ dev_data->boot_config.dsp_log_size); ++ if (unlikely(ret != 0)) { ++ XM6_MSG(XM6_MSG_ERR, "dsp_log_init() failed\n"); ++ return -ENOMEM; ++ } ++ } ++ else ++ { ++ dev_data->boot_config.dsp_log_addr = INVALID_DSP_LOG_ADDR; ++ } ++ ++ memset(&dsp_mem_info, 0, sizeof(dsp_mem_info)); ++ dsp_mem_info.boot_image.addr = dev_data->boot_image.phys; ++ dsp_mem_info.boot_image.size = dev_data->boot_image.size; ++ dsp_mem_info.share_mem.addr = dev_data->dma_buf.dma_addr; ++ dsp_mem_info.share_mem.size = dev_data->dma_buf.size; ++ dsp_mem_info.ext_heap.addr = dev_data->ext_heap.phys; ++ dsp_mem_info.ext_heap.size = dev_data->ext_heap.size; ++ dsp_mem_info.hprintf_buf.addr = dev_data->hprintf_buf.phys; ++ dsp_mem_info.hprintf_buf.size = dev_data->hprintf_buf.size; ++ dsp_mem_info.dsp_log_buf.addr = dev_data->boot_config.dsp_log_addr; ++ dsp_mem_info.dsp_log_buf.size = dev_data->boot_config.dsp_log_size; ++ dsp_mem_info.work_buffer.addr = dev_data->work_buffer.phys; ++ dsp_mem_info.work_buffer.size = dev_data->work_buffer.size; ++ dsp_mem_info.custom_info = boot_config->custom_info; ++ ++ XM6_MSG(XM6_MSG_WRN, "custom_info = %d\n", boot_config->custom_info); ++ ++ // create copier from ext_heap, we use copier only in boot stage ++ copier_buf.virt = dev_data->hprintf_buf.virt; ++ copier_buf.phys = dev_data->hprintf_buf.phys; ++ copier_buf.size = dev_data->hprintf_buf.size; ++ copier_buf.is_from_miu = dev_data->hprintf_buf.is_from_miu; ++ ++#ifdef _FAST_DMA_BOOT_ ++ ret = dsp_dma_image_ext_transfer(dev_data->boot_config,image_virt); ++ if (unlikely(ret != 0)) { ++ XM6_MSG(XM6_MSG_ERR, "dsp_dma_image_ext_transfer() failed\n"); ++ return ret; ++ } ++#endif ++ ++ ++ // boot up ++ ret = dsp_boot_up(&dev_data->ceva_hal, &copier_buf, dev_data->dma_buf.cpu_addr, &dsp_mem_info); ++ ++ if (ret == 0) ++ { ++ dev_data->is_dsp_boot_up = 1; ++ } ++ else ++ { ++ XM6_MSG(XM6_MSG_ERR, "can't boot DSP, err: %d\n", ret); ++ } ++ ++ return ret; ++} ++ ++static int xm6_drv_dsp_shut_down(struct xm6_dev_data *dev_data) ++{ ++ if (!dev_data->is_dsp_boot_up) ++ { ++ XM6_MSG(XM6_MSG_ERR, "DSP does not boot up yet\n"); ++ return -ENOTCONN; ++ } ++ ++ XM6_MSG(XM6_MSG_DBG, "shut down DSP\n"); ++ ++ dsp_shut_down(&dev_data->ceva_hal); ++ ++ xm6_drv_deinit_dsp_buffer(dev_data); ++ ++ dev_data->is_dsp_boot_up = 0; ++ ++ return 0; ++} ++ ++static void dump_dbg_message(unsigned int cmd) ++{ ++ if(IOC_CEVADRV_GET_PID_PROCID != cmd) ++ { ++ XM6_MSG(XM6_MSG_ERR, "IOCTL Error cmd:0x%x \n",cmd); ++ ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_PRINT_DMA: 0x%x \n",IOC_CEVADRV_PRINT_DMA); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_BYPASS_REQ: 0x%x \n",IOC_CEVADRV_BYPASS_REQ); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_READ_DEBUG: 0x%x \n",IOC_CEVADRV_READ_DEBUG); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_GENERATE_INT: 0x%x \n",IOC_CEVADRV_GENERATE_INT); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_GET_PID_PROCID:0x%x \n",IOC_CEVADRV_GET_PID_PROCID); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_BOOT_UP: 0x%x \n",IOC_CEVADRV_BOOT_UP); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_SHUT_DOWN: 0x%x \n",IOC_CEVADRV_SHUT_DOWN); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_BOOT_CHECK: 0x%x \n",IOC_CEVADRV_BOOT_CHECK); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_MIU_2_PHYS: 0x%x \n",IOC_CEVADRV_MIU_2_PHYS); ++ XM6_MSG(XM6_MSG_ERR, " IOC_CEVADRV_PHYS_2_MIU: 0x%x \n",IOC_CEVADRV_PHYS_2_MIU); ++ } ++ ++ return; ++} ++/*! ++ * ioctl handler ++ * ++ * special commands executer. ++ * in case the command is not supported by this module, it forwards it ++ * to the ceva_linkdrv module to handle. ++ * @param [in] filp device handler ++ * @param [in] cmd command to execute ++ * @param [in] arg additional argument (differ for each command) ++ * @return zero for success, nonzero for failures ++ * @see IOC_CEVADRV_GENERATE_INT, IOC_CEVADRV_PRINT_DMA, ceva_linkdrv_ioctl() ++ */ ++static long xm6_drv_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { ++ int ret = 0; ++ struct xm6_dev_data *dev_data = (struct xm6_dev_data *) filp->private_data; ++ struct ceva_linkdrv* linkdrv = &dev_data->linkdrv; ++ ++ XM6_MSG(XM6_MSG_DBG, "ioctl filp %p, device %p, cmd 0x%x\n", filp, dev_data, cmd); ++ ++ /* don't even decode wrong cmds: better returning ENOTTY than EFAULT */ ++ if (_IOC_TYPE(cmd) != IOC_CEVADRV_MAGIC || _IOC_NR(cmd) > IOC_CEVADRV_MAXNR) { ++ return -ENOTTY; ++ } ++ ++ switch (cmd) { ++ case IOC_CEVADRV_GENERATE_INT: ++ /* use arg as raw data for interrupt */ ++ XM6_MSG(XM6_MSG_DBG, "generating interrupt %lx\n", arg); ++ ret = ceva_link_generate_irq(dev_data, arg); ++ if (!ret) { ++ DEBUG_INFO_INC(linkdrv, generated_interrupts); ++ } else { ++ DEBUG_INFO_INC(linkdrv, generate_interrupt_failures); ++ } ++ break; ++ ++ case IOC_CEVADRV_PRINT_DMA: { ++#ifdef ENABLE_DEBUG ++ xm6_dev_dma_buf *dma_buf = &dev_data->dma_buf; ++ int off = (int)arg; ++ int* addr = (int*)arg; ++ int* p = dma_buf->cpu_addr; ++ ++ XM6_MSG(XM6_MSG_DBG, "IOC_CEVADRV_PRINT_DMA :: dma address @ 0x%p -> 0x%x\n", addr, p[off]); ++#endif // ENABLE_DEBUG ++ } ++ break; ++ ++ case IOC_CEVADRV_BOOT_UP: { ++ struct boot_config_t boot_config; ++ ++ // copy and reassign boot info from user argument ++ ret = copy_from_user(&boot_config, (void*)arg, sizeof(boot_config)); ++ ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "can't copy data from user space (%d copied %d)\n", sizeof(boot_config), ret); ++ return -ENOMEM; ++ } ++ ++ return xm6_drv_dsp_boot_up(dev_data, &boot_config); ++ } ++ ++ case IOC_CEVADRV_SHUT_DOWN: { ++ ret = copy_to_user((void*)arg, &dev_data->boot_config, sizeof(struct boot_config_t)); ++ if (ret != 0) { ++ return ret; ++ } ++ ++ ret = xm6_drv_dsp_shut_down(dev_data); ++ if (ret != 0) { ++ return ret; ++ } ++ ++ return 0; ++ } ++ ++ case IOC_CEVADRV_BOOT_CHECK: { ++ ret = copy_to_user((void*)arg, &dev_data->is_dsp_boot_up, sizeof(dev_data->is_dsp_boot_up)); ++ if (ret != 0) { ++ return ret; ++ } ++ ++ return 0; ++ } ++ ++ case IOC_CEVADRV_MIU_2_PHYS: { ++ u64 miu, phys; ++ ret = copy_from_user(&miu, (void*)arg, sizeof(miu)); ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "can't copy data from user space (%d copied %d)\n", sizeof(miu), ret); ++ return -ENOMEM; ++ } ++ ++ phys = xm6_drv_miu2phys(miu); ++ ++ XM6_MSG(XM6_MSG_DBG, "miu: 0x%llx ==> phys: 0x%llx\n", miu, phys); ++ ++ ret = copy_to_user((void*)arg, &phys, sizeof(phys)); ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "can't copy data to user space (%d copied %d)\n", sizeof(phys), ret); ++ return -ENOMEM; ++ } ++ ++ return 0; ++ } ++ ++ case IOC_CEVADRV_PHYS_2_MIU: { ++ u64 miu, phys; ++ ret = copy_from_user(&phys, (void*)arg, sizeof(phys)); ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "can't copy data from user space (%d copied %d)\n", sizeof(miu), ret); ++ return -ENOMEM; ++ } ++ ++ miu = xm6_drv_phys2miu(phys); ++ ++ XM6_MSG(XM6_MSG_DBG, "phys: 0x%llx ==> miu: 0x%llx\n", phys, miu); ++ ++ ret = copy_to_user((void*)arg, &miu, sizeof(miu)); ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "can't copy data to user space (%d copied %d)\n", sizeof(miu), ret); ++ return -ENOMEM; ++ } ++ ++ return 0; ++ } ++ ++ case IOC_CEVADRV_VERSION_CHECK: { ++ XM6_MSG(XM6_MSG_INIT, "IOC_CEVADRV_VERSION_CHECK \n"); ++ dump_XM6VerInfo(pVerInfo); ++ ret = copy_to_user((void*)arg, pVerInfo, sizeof(struct Version_Info)); ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "can't copy data to user space (%d copied %d)\n", sizeof(struct Version_Info), ret); ++ return -ENOMEM; ++ } ++ return 0; ++ } ++ ++ default: ++ dump_dbg_message(cmd); ++ ret = ceva_linkdrv_ioctl(linkdrv, cmd, arg); ++ } ++ ++ return ret; ++} ++ ++static void xm6_drv_dma_vma_open(struct vm_area_struct *vma) { ++ xm6_dev_dma_buf* dma_buf; ++ struct xm6_dev_data *dev_data; ++ ++ XM6_MSG(XM6_MSG_DBG, "xm6_drv_dma_vma_open: virt 0x%lx, phys 0x%lx\n", vma->vm_start, vma->vm_pgoff << PAGE_SHIFT); ++ ++ dma_buf = vma->vm_private_data; ++ dev_data = dma_buf->priv_data; ++} ++ ++static void xm6_drv_dma_vma_close(struct vm_area_struct *vma) { ++ xm6_dev_dma_buf* dma_buf; ++ struct xm6_dev_data *dev_data; ++ ++ dma_buf = vma->vm_private_data; ++ dev_data = dma_buf->priv_data; ++} ++ ++/*! ++ * mmap handler for dma memory ++ * ++ * this function remap the internal dma memory that was mapped during ++ * probe function to userland. ++ * @param [in] dev_data device driver object ++ * @param [in] vma vma object ++ * @return zero for success, nonzero for failures ++ * @see xm6_drv_probe() ++ */ ++static int xm6_drv_mmap_dma(struct xm6_dev_data *dev_data, struct vm_area_struct *vma) { ++ xm6_dev_dma_buf *dma_buf = &dev_data->dma_buf; ++ unsigned long pfn, size; ++ ++#ifdef ENABLE_DEBUG ++ static int count = 0; ++#endif // ENABLE_DEBUG ++ ++ XM6_MSG(XM6_MSG_DBG, "setting vma\n"); ++ ++ vma->vm_ops = &xm6_drv_dma_vma_ops; ++ vma->vm_private_data = dma_buf; ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ xm6_drv_dma_vma_open(vma); ++ ++#ifdef ENABLE_DEBUG ++ XM6_MSG(XM6_MSG_DBG, "enter #%d\n", ++count); ++#endif ++ ++ pfn = vmalloc_to_pfn(dma_buf->cpu_addr); ++ size = vma->vm_end - vma->vm_start; ++ ++ XM6_MSG(XM6_MSG_DBG, "remap started, vm_start =0x%lx, cpu_addr = 0x%p, dma_addr = 0x%lx, pfn = 0x%lx, size = %lu\n", ++ vma->vm_start, dma_buf->cpu_addr, (unsigned long)dma_buf->dma_addr, pfn, size); ++ ++ if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) { ++ XM6_MSG(XM6_MSG_ERR, "remap failed\n"); ++ return -EAGAIN; ++ } ++ ++ XM6_MSG(XM6_MSG_DBG, "remap succeeded\n"); ++ return 0; ++} ++ ++/*! ++ * mmap handler ++ * ++ * wrapper function for mapping dma to user. ++ * @param [in] filp device handler ++ * @param [in] vma vma object ++ * @return zero for success, nonzero for failures ++ * @note the wrapper was implemented to allow mapping of pci memory in ++ * future versions (if needed) ++ * @see xm6_drv_mmap_dma() ++ */ ++static int xm6_drv_mmap(struct file *filp, struct vm_area_struct *vma) { ++ struct xm6_dev_data *dev_data = (struct xm6_dev_data *) filp->private_data; ++ ++ XM6_MSG(XM6_MSG_DBG, "mmap filp %p, device %p\n", filp, dev_data); ++ return xm6_drv_mmap_dma(dev_data, vma); ++} ++ ++/*! ++ * cleanup logical part of this module ++ * ++ * this function deletes any non-pci related driver's objects (the chardev ++ * properties). ++ * @param [in] dev_data device handler ++ */ ++static void xm6_drv_cleanup_module(struct platform_device *plat_dev, struct xm6_dev_data *dev_data) { ++ device_destroy(xm6_drv_data.class, dev_data->cdev.dev); ++ cdev_del(&dev_data->cdev); ++ ++ mutex_destroy(&dev_data->dev_mutex); ++} ++ ++/*! ++ * buildup the char device of this module ++ * ++ * this function handles the creation and setup of the char device ++ * @param [in] dev_data device handler ++ * @return negative error code is returned on failure ++ * @see ceva_linkdrv_init_module() ++ */ ++static int xm6_drv_setup_cdev(struct platform_device *plat_dev, struct xm6_dev_data *dev_data) { ++ int ret; ++ struct device *device = NULL; ++ int dev_count, dev_no; ++ ++ dev_count = xm6_drv_data.minor_star + xm6_drv_data.reg_count; ++ dev_no = MKDEV(xm6_drv_data.major, dev_count); ++ ++ cdev_init(&dev_data->cdev, &xm6_drv_fops); ++ dev_data->cdev.owner = THIS_MODULE; ++ ret = cdev_add(&dev_data->cdev, dev_no, 1); ++ /* Fail gracefully if need be */ ++ if (ret < 0) { ++ XM6_MSG(XM6_MSG_ERR, "setup_cdev: Error %d adding device\n", dev_no); ++ goto exit; ++ } ++ ++ device = device_create( ++ xm6_drv_data.class, /* class */ ++ NULL, /* no parent device */ ++ dev_no, ++ dev_data, ++ CEVA_PCIDEV_DEVICE_NAME "%d", ++ dev_count); ++ ++ if (IS_ERR(device)) { ++ ret = PTR_ERR(device); ++ XM6_MSG(XM6_MSG_ERR, "setup_cdev: Error %d while trying to create %s%d\n", ++ ret, ++ CEVA_PCIDEV_DEVICE_NAME, ++ dev_count); ++ cdev_del(&dev_data->cdev); ++ } ++ ++ dev_data->count = 0; ++ ++ // Increase registered count ++ xm6_drv_data.reg_count++; ++ ++ dev_set_drvdata(&plat_dev->dev, dev_data); ++ ++exit: ++ return ret; ++ ++} ++ ++/*! ++ * initialize logical part of this module ++ * ++ * this function allocate and setup all non-pci related driver's objects ++ * (the chardev properties). ++ * @param [in] dev_data device handler ++ * @return zero for success, nonzero for failures ++ * @see xm6_drv_setup_cdev() ++ */ ++static int ceva_linkdrv_init_module(struct platform_device *plat_dev, struct xm6_dev_data *dev_data) { ++ int ret; ++ ++ mutex_init(&dev_data->dev_mutex); ++ ++ ret = xm6_drv_setup_cdev(plat_dev, dev_data); ++ if (ret < 0) { ++ goto fail; ++ } ++ ++ return 0; ++ ++fail: ++ xm6_drv_cleanup_module(plat_dev, dev_data); ++ return ret; ++} ++ ++/*! ++ * get PCIe hardware properties (irq, revision) ++ * @param [in] plat_dev PCIe device handler ++ * @param [in] dev_data device handler ++ * @return zero for success, nonzero for failures ++ * @see xm6_drv_probe() ++ */ ++static inline int probe_get_hw_prop(struct platform_device* plat_dev, struct xm6_dev_data *dev_data) { ++ struct resource *res = NULL; ++ ++ dev_data->hw_irq_id = irq_of_parse_and_map(plat_dev->dev.of_node, 0); ++ if (dev_data->hw_irq_id == 0) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IRQ ID\n"); ++ return -ENODEV; ++ } ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IO addr 0\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_xm6 = res->start; ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 1); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IO addr 0\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_sys = res->start; ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 2); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IO addr 1\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_axi2miu0 = res->start; ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 3); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IO addr 2\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_axi2miu1 = res->start; ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 4); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IO addr 3\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_axi2miu2 = res->start; ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 5); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get IO addr 4\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_axi2miu3 = res->start; ++ ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 6); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get CPM addr\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_cpm = res->start; ++ ++ #if 1 ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 7); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get hw_addr_cevatopctl addr\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_cevatopctl = res->start; ++ ++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 8); ++ if (res == NULL) { ++ XM6_MSG(XM6_MSG_ERR, "Can't get hw_addr_cevapllpower addr\n"); ++ return -ENODEV; ++ } ++ dev_data->hw_addr_cevapllpower = res->start; ++ #endif ++ ++ XM6_MSG(XM6_MSG_DBG, "irq id: %d, hw addr: %x, %x %x, %x, %x, %x, %x ,%x \n", ++ dev_data->hw_irq_id, dev_data->hw_addr_sys, ++ dev_data->hw_addr_axi2miu0, dev_data->hw_addr_axi2miu1, ++ dev_data->hw_addr_axi2miu2, dev_data->hw_addr_axi2miu3, ++ dev_data->hw_addr_cpm,dev_data->hw_addr_cevatopctl,dev_data->hw_addr_cevapllpower); ++ return 0; ++} ++ ++/*! ++ * generates an interrupt over the device ++ * ++ * this function checks for device's availability to receive new interrupts ++ * and then writes the new interrupt data to the predefined address in bar0 ++ * @param dev_data device handler ++ * @param e interrupt id to generate ++ * @return zero for success, -EBUSY if device's fifo is full ++ * @see xm6_drv_ioctl(), IOC_CEVADRV_GENERATE_INT ++ */ ++static int ceva_link_generate_irq(struct xm6_dev_data *dev_data, ceva_event_t e) { ++ u32 state; ++ ++ XM6_MSG(XM6_MSG_DBG, "send IRQ MCCI_LINK_EVENT_FROM_HOST to DSP\n"); ++ HOST_LOG("MCCI_LINK_EVENT_FROM_HOST\n"); ++ ++ // disable MCCI IRQ temporarily ++ dsp_ceva_hal_disable_irq(&dev_data->ceva_hal, CEVA_HAL_IRQ_TARGET_ARM, CEVA_HAL_IRQ_MCCI_RD); ++ HOST_LOG("disable MCCI RD intr\n"); ++ ++ // write MCCI_0 to pass data ++ cmp_hal_mcci_write(&dev_data->cpm_hal, MCCI_LINK_EVENT_FROM_HOST, e); ++ HOST_LOG("write MIIC 0 data=0x%x\n", e); ++ ++ // wait DSP response via MCCI_0 ++ state = dsp_ceva_hal_check_mcci_irq(&dev_data->ceva_hal, MCCI_LINK_EVENT_FROM_HOST); ++ while (state == 0) { ++ // delay ? ++ // ndelay(10); ++ ++ dsp_ceva_hal_read_dummy_data(&dev_data->ceva_hal, 1); ++ ++ state = dsp_ceva_hal_check_mcci_irq(&dev_data->ceva_hal, MCCI_LINK_EVENT_FROM_HOST); ++ } ++ HOST_LOG("read MCCI IRQ state 0x%x\n", state); ++ ++ // clear MCCI_0 status to avoid a interrupt ++ dsp_ceva_hal_clear_mcci_irq(&dev_data->ceva_hal, 0); ++ ++ XM6_MSG(XM6_MSG_DBG, "clear MCCI read IRQ, 0x%X\n", state); ++ HOST_LOG("clear MCCI read IRQ 0x%x\n", state); ++ ++ // enable MCCI interrupt ++ dsp_ceva_hal_enable_irq(&dev_data->ceva_hal, CEVA_HAL_IRQ_TARGET_ARM, CEVA_HAL_IRQ_MCCI_RD); ++ HOST_LOG("enable MCCI RD intr\n"); ++ ++ SendDSPCount++; ++ ++ return 0; ++} ++ ++/*! ++ * interrupt routine ++ * ++ * this function handles the device's interrupts. ++ * it first reads from the device irq status register in order to tell ++ * which interrupts where sent to the device (there up to 16), and then ++ * reads the interrupts data, and forward it to the logical module to ++ * handle. ++ * @param [in] irq irq id ++ * @param [in] dev_id device handler ++ * @return IRQ_HANDLED for success, IRQ_NONE for error ++ * @see ceva_linkdrv_broadcast_events() ++ */ ++static irqreturn_t ceva_linkdrv_interrupt(int irq, void *dev_id) { ++ struct xm6_dev_data *dev_data = (struct xm6_dev_data *) dev_id; ++ u32 dsp_data; ++ irqreturn_t ret = IRQ_NONE; ++ CEVA_HAL_IRQ id; ++ ++ // printk("ISR\n"); ++ HOST_LOG("enter intr\n"); ++ ++ id = dsp_ceva_hal_get_irq_status(&dev_data->ceva_hal); ++ HOST_LOG("IRQ status = 0x%x\n", id); ++ id &= dsp_ceva_hal_get_irq_mask(&dev_data->ceva_hal, CEVA_HAL_IRQ_TARGET_ARM); ++ if ((id & CEVA_HAL_IRQ_MCCI_RD) == 0) ++ { ++ HOST_LOG("Not MCCI RD intr\n"); ++ return ret; ++ } ++ ++ // MCCI_1 is for link ++ if (dsp_ceva_hal_check_mcci_irq(&dev_data->ceva_hal, MCCI_LINK_EVENT_FROM_DSP)) ++ { ++ HOST_LOG("MCCI_LINK_EVENT_FROM_DSP\n"); ++ ++ // read out ++ dsp_data = dsp_ceva_hal_read_dummy_data(&dev_data->ceva_hal, 0); ++ ++ XM6_MSG(XM6_MSG_DBG, "receive data 0x%08x from DSP\n", dsp_data); ++ HOST_LOG("recv 0x%x from DSP\n", dsp_data); ++ ++ // clear interrupt ++ dsp_ceva_hal_clear_mcci_irq(&dev_data->ceva_hal, MCCI_LINK_EVENT_FROM_DSP); ++ ++ // change dummy register to notify DSP that data is read ++ dsp_ceva_hal_write_dummy_data(&dev_data->ceva_hal, 0, dsp_data-1); ++ HOST_LOG("write dummy reg 0x%x\n", dsp_data - 1); ++ ++ // send to linkdrv layer ++ ceva_linkdrv_broadcast_events(&dev_data->linkdrv, &dsp_data, 1); ++ ++ GotDSPCount++; ++ ++ ret = IRQ_HANDLED; ++ } ++ ++ // MCCI_2 is for printf ++ else if(dsp_ceva_hal_check_mcci_irq(&dev_data->ceva_hal, MCCI_PRINT_FROM_DSP)) ++ { ++ HOST_LOG("MCCI_PRINT_FROM_DSP\n"); ++ ++ // read out ++ dsp_data = dsp_ceva_hal_read_dummy_data(&dev_data->ceva_hal, 0); ++ ++ XM6_MSG(XM6_MSG_DBG, "receive data 0x%08x from DSP\n", dsp_data); ++ HOST_LOG("recv data 0x%08x from DSP\n", dsp_data); ++ ++ // ++ printk(dev_data->hprintf_buf.virt); ++ ++ // clear interrupt ++ dsp_ceva_hal_clear_mcci_irq(&dev_data->ceva_hal, MCCI_PRINT_FROM_DSP); ++ ++ // change dummy register to notify DSP that data is read ++ dsp_ceva_hal_write_dummy_data(&dev_data->ceva_hal, 0, dsp_data-1); ++ HOST_LOG("write dummy reg 0x%08x\n", dsp_data - 1); ++ ++ ret = IRQ_HANDLED; ++ } ++ ++ // JBox may trigger other mcci pins ++ else ++ { ++ dsp_data = dsp_ceva_hal_get_mcci_irq(&dev_data->ceva_hal); ++ dsp_data &= MCCI_IRQ_UNEXPECT; ++ if(dsp_data != 0) ++ { ++ XM6_MSG(XM6_MSG_DBG, "unexpect MCCI IRQ 0x%x (0x%X)\n", dsp_data, dsp_ceva_hal_read_dummy_data(&dev_data->ceva_hal, 1)); ++ HOST_LOG("unexpect MCCI IRQ 0x%x (0x%X)\n", dsp_data, dsp_ceva_hal_read_dummy_data(&dev_data->ceva_hal, 1)); ++ ++ // clear interrupt ++ dsp_ceva_hal_clear_mcci_irq_ex(&dev_data->ceva_hal, dsp_data); ++ ++ ret = IRQ_HANDLED; ++ } ++ } ++ ++ HOST_LOG("exit intr\n"); ++ return ret; ++} ++ ++/*! ++ * enable PCIe irq ++ * @param [in] plat_dev PCIe device handler ++ * @param [in] dev_data device handler ++ * @return zero for success, nonzero for failures ++ * @see xm6_drv_probe() ++ */ ++static int probe_init_irq(struct platform_device *plat_dev, struct xm6_dev_data *dev_data) { ++ int ret = request_irq(dev_data->hw_irq_id, ++ ceva_linkdrv_interrupt, ++ 0, ++ DRIVER_NAME, dev_data); ++ if (ret != 0) { ++ XM6_MSG(XM6_MSG_ERR, "Could not request IRQ #%d, error %d\n", dev_data->hw_irq_id, ret); ++ return -EIO; ++ } ++ ++ // Enable MCCI interrupt (read/write) is used as a trigger signal between ARM and DSP ++ dsp_ceva_hal_enable_irq(&dev_data->ceva_hal, CEVA_HAL_IRQ_TARGET_ARM, CEVA_HAL_IRQ_MCCI_RD); ++ dsp_ceva_hal_enable_irq(&dev_data->ceva_hal, CEVA_HAL_IRQ_TARGET_XM6_INT0, CEVA_HAL_IRQ_MCCI_MES); ++ ++ XM6_MSG(XM6_MSG_DBG, "Successfully requested IRQ #%d\n", dev_data->hw_irq_id); ++ return 0; ++} ++ ++/*! ++ * disable PCIe irq ++ * @param [in] plat_dev PCIe device handler ++ * @param [in] dev_data device handler ++ * @see xm6_drv_remove() ++ */ ++static void remove_deinit_irq(struct platform_device *plat_dev, struct xm6_dev_data *dev_data) { ++ free_irq(dev_data->hw_irq_id, dev_data); ++ XM6_MSG(XM6_MSG_DBG, "irq freed"); ++} ++ ++/*! ++ * XM6 probe function ++ * ++ * this function enables and starts CEVA PCIe device ++ * @param [in/out] plat_dev PCIe device handler ++ * @param [in] id not used ++ * @return zero for success, nonzero for failures ++ * @see find_upstream_dev(), retrain_gen2(), probe_get_hw_prop(), ++ * probe_map_bars(), probe_map_dma(), probe_enable_msi(),probe_init_irq(), ++ * ceva_linkdrv_init_module(), xm6_drv_remove() ++ */ ++static int xm6_drv_probe(struct platform_device *plat_dev) { ++ struct xm6_dev_data *dev_data = NULL; ++ int ret = 0; ++ ++ XM6_MSG(XM6_MSG_DBG, "device probed (dev_data = 0x%p)\n", plat_dev); ++ ++ dev_data = devm_kcalloc(&plat_dev->dev, 1, sizeof(struct xm6_dev_data), GFP_KERNEL); ++ if (unlikely(!dev_data)) { ++ ret = -ENOMEM; ++ XM6_MSG(XM6_MSG_ERR, "probe: allocation error\n"); ++ goto alloc_fail; ++ } ++ ++ dev_data->plat_dev = plat_dev; ++ ++ /* ++ * get hardware properties ++ */ ++ ret = probe_get_hw_prop(plat_dev, dev_data); ++ if (unlikely(ret != 0)) { ++ goto enable_fail; ++ } ++ ++ /* Init ceva wrapper hal */ ++ dsp_ceva_hal_init(&dev_data->ceva_hal, dev_data->hw_addr_sys, dev_data->hw_addr_axi2miu0, dev_data->hw_addr_axi2miu1, dev_data->hw_addr_axi2miu2, dev_data->hw_addr_axi2miu3); ++ dsp_ceva_hal_init_cevatop(&dev_data->ceva_hal, dev_data->hw_addr_cevatopctl, dev_data->hw_addr_cevapllpower); ++ ++ /* Init ceva cpm hal */ ++ cmp_hal_init(&dev_data->cpm_hal, dev_data->hw_addr_cpm); ++ cmp_hal_init(&dev_data->cevatopctl_hal, dev_data->hw_addr_cevatopctl); ++ cmp_hal_init(&dev_data->cevapllpower_hal, dev_data->hw_addr_cevapllpower); ++ ++ /* Get Init VCore */ ++ dev_data->InitVCore=dsp_ceva_hal_read_current_vcore(); ++ dsp_ceva_hal_init_VCore(&dev_data->ceva_hal, dev_data->InitVCore); ++ XM6_MSG(XM6_MSG_DBG, "probe: InitVCore: %d \n",dev_data->InitVCore); ++ ++ pGceva_hal=&dev_data->ceva_hal; ++ ++ /* ++ * request irq ++ */ ++ ret = probe_init_irq(plat_dev, dev_data); ++ if (unlikely(ret != 0)) { ++ goto enable_fail; ++ } ++ ++ /* ++ * logical module init ++ */ ++ ret = ceva_linkdrv_init_module(plat_dev, dev_data); ++ if (unlikely(ret != 0)) { ++ XM6_MSG(XM6_MSG_ERR, "probe: failed init logic module\n"); ++ goto logic_fail; ++ } ++ ++ // Increase registered count ++ xm6_drv_data.reg_count++; ++ ++ ret = ceva_linkdrv_proc_init(dev_data); ++ if (ret != 0) { ++ goto proc_fail; ++ } ++ ++ /* ++ * probed successfully ++ */ ++ ++ XM6_MSG(XM6_MSG_DBG, "CEVA device probed\n"); ++ ++ return 0; ++ ++proc_fail: ++logic_fail: ++ remove_deinit_irq(plat_dev, dev_data); ++ ++enable_fail: ++ devm_kfree(&dev_data->plat_dev->dev, dev_data); ++ ++alloc_fail: ++ XM6_MSG(XM6_MSG_ERR, "probe: failed (ret=%d)\n", ret); ++ ++ return ret; ++} ++ ++/*! ++ * XM6 remove function ++ * ++ * this function stops and disables the CEVA PCIe device ++ * @param [in/out] plat_dev PCIe device handler ++ * @see xm6_drv_cleanup_module(), remove_deinit_irq(), pci_disable_msi(), ++ * free_bars(), remove_disable_pci_dev(), xm6_drv_probe() ++ */ ++static s32 xm6_drv_remove(struct platform_device *plat_dev) { ++ struct xm6_dev_data *dev_data; ++ ++ dev_data = (struct xm6_dev_data *)dev_get_drvdata(&plat_dev->dev); ++ if (unlikely(!dev_data)) { ++ XM6_MSG(XM6_MSG_DBG, "device data is NULL.\n"); ++ return -ENODEV; ++ } ++ ++ xm6_drv_cleanup_module(plat_dev, dev_data); ++ dev_set_drvdata(&plat_dev->dev, NULL); ++ ++ /* ++ * disable interrupt ++ */ ++ remove_deinit_irq(plat_dev, dev_data); ++ ++ devm_kfree(&plat_dev->dev, dev_data); ++ ++ XM6_MSG(XM6_MSG_DBG, "Removed device\n"); ++ ++ return 0; ++} ++ ++/*! ++ * driver't init function ++ * ++ * this function register the CEVA's supported PCI ids with ++ * this driver. ++ * it also inits the protected shared memory module. ++ * @see xm6_drv_exit_module ++ */ ++int __init xm6_drv_init_module(void) { ++ int err; ++ dev_t dev; ++ ++ XM6_MSG(XM6_MSG_DBG, "Moudle Init\n"); ++ ++ if (protected_mem_db_init() != 0) { ++ XM6_MSG(XM6_MSG_ERR, "failed to init protected memory db\n"); ++ return -ENODEV; ++ } ++ ++ // Allocate cdev id ++ err = alloc_chrdev_region(&dev, XM6_DRV_MINOR, XM6_DRV_DEVICE_COUNT, XM6_DRV_NAME); ++ if (err) { ++ XM6_MSG(XM6_MSG_ERR, "Unable allocate cdev id\n"); ++ return err; ++ } ++ ++ xm6_drv_data.major = MAJOR(dev); ++ xm6_drv_data.minor_star = MINOR(dev); ++ xm6_drv_data.reg_count = 0; ++ ++ XM6_MSG(XM6_MSG_DBG, "allocate char dev: %d, %d\n", xm6_drv_data.major, xm6_drv_data.minor_star); ++ ++ // Register device class ++ xm6_drv_data.class = class_create(THIS_MODULE, XM6_DRV_CLASS_NAME); ++ if (IS_ERR(xm6_drv_data.class)) { ++ XM6_MSG(XM6_MSG_ERR, "Failed at class_create().Please exec [mknod] before operate the device\n"); ++ err = PTR_ERR(xm6_drv_data.class); ++ goto ERR_RETURN_1; ++ } ++ ++ // Register platform driver ++ err = platform_driver_register(&xm6_drv_driver); ++ if (err != 0) { ++ goto ERR_RETURN_2; ++ } ++ Init_XM6FW_VerInfo(); ++ ++ return 0; ++ ++ERR_RETURN_2: ++ class_destroy(xm6_drv_data.class); ++ ++ERR_RETURN_1: ++ unregister_chrdev_region(MKDEV(xm6_drv_data.major, xm6_drv_data.minor_star), XM6_DRV_DEVICE_COUNT); ++ ++ return err; ++} ++ ++/*! ++ * driver's deinit function ++ * ++ * this function unregister the CEVA's supported PCI ids with ++ * this driver. ++ * it also de-inits the protected shared memory module. ++ * @see xm6_drv_init_module ++ */ ++void __exit xm6_drv_exit_module(void) { ++ XM6_MSG(XM6_MSG_DBG, "Modules Exit\n"); ++ ++ ceva_linkdrv_proc_exit(); ++ ++ protected_mem_db_deinit(); ++ ++ platform_driver_unregister(&xm6_drv_driver); ++ class_destroy(xm6_drv_data.class); ++ unregister_chrdev_region(MKDEV(xm6_drv_data.major, xm6_drv_data.minor_star), XM6_DRV_DEVICE_COUNT); ++} ++ ++module_init(xm6_drv_init_module); ++module_exit(xm6_drv_exit_module); +diff --git a/drivers/sstar/ceva_link/ceva_linkdrv_xm6.h b/drivers/sstar/ceva_link/ceva_linkdrv_xm6.h +new file mode 100644 +index 000000000000..994a57348ab7 +--- /dev/null ++++ b/drivers/sstar/ceva_link/ceva_linkdrv_xm6.h +@@ -0,0 +1,150 @@ ++/* ++ * ceva_linkdrv_xm6.h ++ * ++ * Created on: Aug 14, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#ifndef CEVA_LINKDRV_XM6_H_ ++#define CEVA_LINKDRV_XM6_H_ ++ ++#include ++#include "ceva_linkdrv.h" ++#include "hal_ceva.h" ++#include "hal_cpm.h" ++ ++/* ++ * driver name ++ */ ++#define DRIVER_NAME "ceva_linkdrv" ++ ++/* ++ * By default, the numbering of the minor devices starts at 0 ++ */ ++#define CEVA_PCIDEV_DEFAULT_MINOR_START 0 ++ ++/* ++ * This ensures no warnings in IDE for unresolved symbol. ++ * Actually, this macro is injected by the Makefile ++ */ ++#ifndef CEVA_PCIDEV_NUMBER_OF_DEVICES ++#define CEVA_PCIDEV_NUMBER_OF_DEVICES 1 ++#endif ++ ++#define PCI_DEVICE_ID_CEVA 0x7011 ++#define PCI_VENDOR_ID_CEVA 0x10EE ++ ++/* ++ * number of PCIe bars ++ */ ++#define ACL_PCI_NUM_BARS 4 ++ ++/*! ++ * dma mapped buffer container ++ * ++ * we used this structure as a container for the mapped dma space ++ * its used by the pci driver as container class ++ */ ++typedef struct { ++ void *cpu_addr; /*!< virtual address */ ++ size_t size; /*!< size of mapped space */ ++ dma_addr_t dma_addr; /*!< physical address */ ++ void *priv_data; /*!< owner driver address */ ++} xm6_dev_dma_buf; ++ ++typedef struct { ++ phys_addr_t phys; ++ u8 *virt; ++ u32 size; ++ u8 is_from_miu; ++} dev_dsp_buf; ++ ++typedef struct { ++ __u32 addr; ++ __u32 size; ++} dsp_buffer_t; ++ ++typedef struct { ++ dsp_buffer_t boot_image; // address of boot_image is virtual address ++ dsp_buffer_t share_mem; // address of share_mem is physical address ++ dsp_buffer_t ext_heap; // address of ext_heap is physical address ++ dsp_buffer_t hprintf_buf; // address of log buffer for printf from DSP ++ dsp_buffer_t dsp_log_buf; // address of log buffer for printf from DSP ++ dsp_buffer_t work_buffer; // address of work_buffer is physical address ++ __u32 custom_info; ++} dsp_mem_info_t; ++ ++ ++/*! ++ * PCIe device driver private structure ++ * ++ * this class is public to allow access for the logical driver module ++ * otherwise, it should be within the c file ++ */ ++struct xm6_dev_data { ++ /* ++ * general driver's variables ++ */ ++ unsigned int count; /*!< number of open calls */ ++ struct mutex dev_mutex; /*!< internal driver mutex */ ++ struct ceva_linkdrv linkdrv; /*!< logical ceva driver module */ ++ struct cdev cdev; /*!< char device handler */ ++ ++ /* ++ * PCIe related variables ++ */ ++ struct platform_device *plat_dev; /*!< PCIe device (kernel's) */ ++ int pci_gen; /*!< PCI generation */ ++ int pci_num_lanes; /*!< number of PCIe lanes */ ++ struct pci_dev *upstream; /*!< upstream root node */ ++ unsigned int msis; /*!< number of supported msi */ ++ unsigned char hw_irq_id; /*!< hardware irq number */ ++ phys_addr_t hw_addr_xm6; ++ phys_addr_t hw_addr_sys; ++ phys_addr_t hw_addr_axi2miu0; ++ phys_addr_t hw_addr_axi2miu1; ++ phys_addr_t hw_addr_axi2miu2; ++ phys_addr_t hw_addr_axi2miu3; ++ phys_addr_t hw_addr_cpm; ++ ceva_hal_handle ceva_hal; ++ cpm_hal_handle cpm_hal; ++ ++ cpm_hal_handle cevatopctl_hal; ++ phys_addr_t hw_addr_cevatopctl; ++ ++ cpm_hal_handle cevapllpower_hal; ++ phys_addr_t hw_addr_cevapllpower; ++ ++ CEVA_VCORE InitVCore; ++ ++ // dsp_mem_info_t dsp_mem_info; ++ ++ xm6_dev_dma_buf dma_buf; /*!< dma container */ ++ ++ struct boot_config_t boot_config; ++ ++ dev_dsp_buf boot_image; ++ dev_dsp_buf ext_heap; ++ dev_dsp_buf share_mem; ++ dev_dsp_buf hprintf_buf; ++ dev_dsp_buf dsp_log_buf; ++ dev_dsp_buf work_buffer; ++ ++ int is_dsp_boot_up; ++}; ++ ++#endif /* CEVA_LINKDRV_XM6_H_ */ +diff --git a/drivers/sstar/ceva_link/drv_debug.h b/drivers/sstar/ceva_link/drv_debug.h +new file mode 100644 +index 000000000000..9eb7f1369d9f +--- /dev/null ++++ b/drivers/sstar/ceva_link/drv_debug.h +@@ -0,0 +1,50 @@ ++#ifndef _CEVA_LINKDRV_MSG_H_ ++#define _CEVA_LINKDRV_MSG_H_ ++ ++#include ++#include ++ ++// Defines reference kern levels of printfk ++#define XM6_MSG_INIT 3 ++#define XM6_MSG_ERR 3 ++#define XM6_MSG_WRN 4 ++#define XM6_MSG_DBG 5 ++ ++#define XM6_MSG_LEVL XM6_MSG_WRN ++ ++#define XM6_MSG_ENABLE ++ ++#if defined(XM6_MSG_ENABLE) ++#define XM6_MSG_FUNC_ENABLE ++ ++#define XM6_STRINGIFY(x) #x ++#define XM6_TOSTRING(x) XM6_STRINGIFY(x) ++ ++#if defined(XM6_MSG_FUNC_ENABLE) ++#define XM6_MSG_TITLE "[XM6, %s] " ++#define XM6_MSG_FUNC __func__ ++#else // NOT defined(XM6_MSG_FUNC_ENABLE) ++#define XM6_MSG_TITLE "[XM6] %s" ++#define XM6_MSG_FUNC "" ++#endif // NOT defined(XM6_MSG_FUNC_ENABLE) ++ ++#define XM6_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define XM6_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= XM6_MSG_LEVL) { \ ++ printk(KERN_SOH XM6_TOSTRING(dbglv) XM6_MSG_TITLE _fmt, XM6_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++#else // NOT defined(XM6_MSG_ENABLE) ++#define XM6_ASSERT(arg) ++#define XM6_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(XM6_MSG_ENABLE) ++ ++#endif //_CEVA_LINKDRV_MSG_H_ +diff --git a/drivers/sstar/ceva_link/file_access.c b/drivers/sstar/ceva_link/file_access.c +new file mode 100644 +index 000000000000..8ae0d6f996e4 +--- /dev/null ++++ b/drivers/sstar/ceva_link/file_access.c +@@ -0,0 +1,73 @@ ++/* ++ * file_access.c ++ * ++ * Created on: Nov 28, 2017 ++ * Author: giggs.huang ++ */ ++#if defined(CONFIG_ARCH_INFINITY2) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "file_access.h" ++ ++mm_segment_t oldfs; ++ ++void InitKernelEnv(void) ++{ ++ oldfs = get_fs(); ++ set_fs(KERNEL_DS); ++} ++ ++struct file *OpenFile(char *path,int flag,int mode) ++{ ++ struct file *fp; ++ ++ InitKernelEnv(); ++ ++ fp=filp_open(path, flag, mode); ++ if (fp) return fp; ++ else return NULL; ++} ++ ++int ReadFile(struct file *fp,char *buf,int readlen) ++{ ++ if (fp->f_op && fp->f_op->read) ++ return fp->f_op->read(fp,buf,readlen, &fp->f_pos); ++ else ++ return -1; ++} ++int WriteFile(struct file *fp,char *buf,int writelen) ++{ ++ ssize_t writeBytes = 0; ++ ++ writeBytes = vfs_write(fp, (char*)buf, writelen, &fp->f_pos); ++ ++ return (int)writeBytes; ++ ++} ++int CloseFile(struct file *fp) ++{ ++ filp_close(fp,NULL); ++ set_fs(oldfs); ++ return 0; ++} ++ ++int GetFileAttr(struct file *fp, finfo_t* finfop) ++{ ++ if(finfop && fp && fp->f_inode) ++ { ++ finfop->file_size = fp->f_inode->i_size; ++ return 0; ++ } ++ return -1; ++} ++ ++#endif +diff --git a/drivers/sstar/ceva_link/file_access.h b/drivers/sstar/ceva_link/file_access.h +new file mode 100644 +index 000000000000..017c72ced853 +--- /dev/null ++++ b/drivers/sstar/ceva_link/file_access.h +@@ -0,0 +1,25 @@ ++/* ++ * file_access.h ++ * ++ * Created on: Nov 28, 2017 ++ * Author: giggs.huang ++ */ ++ ++#ifndef DRV_TEST_KERNEL_UT_FILE_ACCESS_H_ ++#define DRV_TEST_KERNEL_UT_FILE_ACCESS_H_ ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++#include ++ ++typedef struct finfo_s ++{ ++ uint file_size; ++} finfo_t; ++ ++struct file *OpenFile(char *path,int flag,int mode); ++int ReadFile(struct file *fp,char *buf,int readlen); ++int WriteFile(struct file *fp,char *buf,int writelen); ++int CloseFile(struct file *fp); ++int GetFileAttr(struct file *fp, finfo_t* finfop); ++#endif ++#endif /* DRV_TEST_KERNEL_UT_FILE_ACCESS_H_ */ +diff --git a/drivers/sstar/ceva_link/hal_ceva.c b/drivers/sstar/ceva_link/hal_ceva.c +new file mode 100644 +index 000000000000..30a6d1368447 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_ceva.c +@@ -0,0 +1,676 @@ ++#include "hal_ceva.h" ++#include "hal_debug.h" ++ ++#include "ms_platform.h" ++#include ++ ++#include ++#include ++#include ++ ++ ++#include "infinity2/gpio.h" ++#include "mdrv_gpio.h" ++ ++ ++// #define ENABLE_JTAG ++ ++#ifdef ENABLE_JTAG ++#define RIU_BASE_ADDR (0x1F000000) ++#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR)) ++#define BANK_GOP (BANK_CAL(0x1026)) ++#endif // ENABLE_JTAG ++ ++#define LOW_U16(value) (((u32)(value))&0x0000FFFF) ++#define HIGH_U16(value) ((((u32)(value))&0xFFFF0000)>>16) ++ ++#define MAKE_U32(high, low) ((((u32)high)<<16) | low) ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++void dsp_ceva_hal_init(ceva_hal_handle *handle, phys_addr_t base_sys, phys_addr_t base_axi2miu0, phys_addr_t base_axi2miu1, phys_addr_t base_axi2miu2, phys_addr_t base_axi2miu3) ++{ ++ HAL_MSG(HAL_MSG_DBG, "init 0x%p, 0x%X, 0x%X, 0x%X, 0x%X, 0x%X\n", handle, base_sys, base_axi2miu0, base_axi2miu1, base_axi2miu2, base_axi2miu3); ++ ++ memset(handle, 0, sizeof(ceva_hal_handle)); ++ handle->base_sys = base_sys; ++ handle->base_axi2miu0 = base_axi2miu0; ++ handle->base_axi2miu1 = base_axi2miu1; ++ handle->base_axi2miu2 = base_axi2miu2; ++ handle->base_axi2miu3 = base_axi2miu3; ++} ++ ++void dsp_ceva_hal_init_cevatop(ceva_hal_handle *handle, phys_addr_t hw_addr_cevatopctl, phys_addr_t hw_addr_cevapllpower) ++{ ++ HAL_MSG(HAL_MSG_DBG, "init cevatop 0x%p, 0x%X, 0x%X\n", handle, hw_addr_cevatopctl, hw_addr_cevapllpower); ++ ++ handle->hw_addr_cevatopctl = hw_addr_cevatopctl; ++ handle->hw_addr_cevapllpower = hw_addr_cevapllpower; ++} ++ ++void dsp_ceva_hal_init_VCore(ceva_hal_handle *handle, CEVA_VCORE InitVCore) ++{ ++ HAL_MSG(HAL_MSG_DBG, "init InitVCore 0x%p, 0x%X \n", handle, InitVCore); ++ ++ if((InitVCore !=CEVA_VCORE_095_VOLT)&&(InitVCore !=CEVA_VCORE_100_VOLT)) ++ { ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: InitVCore:0x%d X\n",InitVCore); ++ } ++ handle->InitVCore = InitVCore; ++ return; ++} ++ ++void dsp_ceva_hal_disable_irq(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target, CEVA_HAL_IRQ irq) ++{ ++ u16 irq0 = LOW_U16(irq); ++ u16 irq1 = HIGH_U16(irq); ++ ++ switch(target) ++ { ++ case CEVA_HAL_IRQ_TARGET_ARM: ++ handle->reg_sys.reg03 = REGR(handle->base_sys, 0x03); ++ handle->reg_sys.reg_ceva2riu_int_en &= ~irq0; ++ REGW(handle->base_sys, 0x03, handle->reg_sys.reg03); ++ ++ handle->reg_sys.reg04 = REGR(handle->base_sys, 0x04); ++ handle->reg_sys.reg_ceva2riu_int_en2 &= ~irq1; ++ REGW(handle->base_sys, 0x04, handle->reg_sys.reg04); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT0: ++ handle->reg_sys.reg05 = REGR(handle->base_sys, 0x05); ++ handle->reg_sys.reg_ceva_int0_en &= ~irq0; ++ REGW(handle->base_sys, 0x05, handle->reg_sys.reg05); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT1: ++ handle->reg_sys.reg06 = REGR(handle->base_sys, 0x06); ++ handle->reg_sys.reg_ceva_int1_en &= ~irq0; ++ REGW(handle->base_sys, 0x06, handle->reg_sys.reg06); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT2: ++ handle->reg_sys.reg07 = REGR(handle->base_sys, 0x07); ++ handle->reg_sys.reg_ceva_int2_en &= ~irq0; ++ REGW(handle->base_sys, 0x07, handle->reg_sys.reg07); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_NMI: ++ handle->reg_sys.reg08 = REGR(handle->base_sys, 0x08); ++ handle->reg_sys.reg_ceva_nmi_en &= ~irq0; ++ REGW(handle->base_sys, 0x08, handle->reg_sys.reg08); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_VINT: ++ handle->reg_sys.reg09 = REGR(handle->base_sys, 0x09); ++ handle->reg_sys.reg_ceva_vint_en &= ~irq0; ++ REGW(handle->base_sys, 0x09, handle->reg_sys.reg09); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++void dsp_ceva_hal_enable_irq(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target, CEVA_HAL_IRQ irq) ++{ ++ u16 irq0 = LOW_U16(irq); ++ u16 irq1 = HIGH_U16(irq); ++ ++ switch(target) ++ { ++ case CEVA_HAL_IRQ_TARGET_ARM: ++ handle->reg_sys.reg03 = REGR(handle->base_sys, 0x03); ++ handle->reg_sys.reg_ceva2riu_int_en |= irq0; ++ REGW(handle->base_sys, 0x03, handle->reg_sys.reg03); ++ ++ handle->reg_sys.reg04 = REGR(handle->base_sys, 0x04); ++ handle->reg_sys.reg_ceva2riu_int_en2 |= irq1; ++ REGW(handle->base_sys, 0x04, handle->reg_sys.reg04); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT0: ++ handle->reg_sys.reg05 = REGR(handle->base_sys, 0x05); ++ handle->reg_sys.reg_ceva_int0_en |= irq0; ++ REGW(handle->base_sys, 0x05, handle->reg_sys.reg05); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT1: ++ handle->reg_sys.reg06 = REGR(handle->base_sys, 0x06); ++ handle->reg_sys.reg_ceva_int1_en |= irq0; ++ REGW(handle->base_sys, 0x06, handle->reg_sys.reg06); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT2: ++ handle->reg_sys.reg07 = REGR(handle->base_sys, 0x07); ++ handle->reg_sys.reg_ceva_int2_en |= irq0; ++ REGW(handle->base_sys, 0x07, handle->reg_sys.reg07); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_NMI: ++ handle->reg_sys.reg08 = REGR(handle->base_sys, 0x08); ++ handle->reg_sys.reg_ceva_nmi_en |= irq0; ++ REGW(handle->base_sys, 0x08, handle->reg_sys.reg08); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_VINT: ++ handle->reg_sys.reg09 = REGR(handle->base_sys, 0x09); ++ handle->reg_sys.reg_ceva_vint_en |= irq0; ++ REGW(handle->base_sys, 0x09, handle->reg_sys.reg09); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++CEVA_HAL_IRQ dsp_ceva_hal_get_irq_mask(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target) ++{ ++ u32 enable = 0; ++ ++ switch(target) ++ { ++ case CEVA_HAL_IRQ_TARGET_ARM: ++ handle->reg_sys.reg03 = REGR(handle->base_sys, 0x03); ++ handle->reg_sys.reg04 = REGR(handle->base_sys, 0x04); ++ enable = MAKE_U32(handle->reg_sys.reg_ceva2riu_int_en2, handle->reg_sys.reg_ceva2riu_int_en); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT0: ++ handle->reg_sys.reg05 = REGR(handle->base_sys, 0x05); ++ enable = MAKE_U32(0, handle->reg_sys.reg_ceva_int0_en); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT1: ++ handle->reg_sys.reg06 = REGR(handle->base_sys, 0x06); ++ enable = MAKE_U32(0, handle->reg_sys.reg_ceva_int1_en); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT2: ++ handle->reg_sys.reg07 = REGR(handle->base_sys, 0x07); ++ enable = MAKE_U32(0, handle->reg_sys.reg_ceva_int2_en); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_NMI: ++ handle->reg_sys.reg08 = REGR(handle->base_sys, 0x08); ++ enable = MAKE_U32(0, handle->reg_sys.reg_ceva_nmi_en); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_VINT: ++ handle->reg_sys.reg09 = REGR(handle->base_sys, 0x09); ++ enable = MAKE_U32(0, handle->reg_sys.reg_ceva_vint_en); ++ break; ++ ++ default: ++ break; ++ } ++ ++ return enable; ++} ++ ++ ++CEVA_HAL_IRQ dsp_ceva_hal_get_irq_status(ceva_hal_handle *handle) ++{ ++ u32 irq; ++ ++ handle->reg_sys.reg18 = REGR(handle->base_sys, 0x18); ++ handle->reg_sys.reg19 = REGR(handle->base_sys, 0x19); ++ irq = MAKE_U32(handle->reg_sys.reg_ceva_is2, handle->reg_sys.reg_ceva_is); ++ ++ return irq; ++} ++ ++void dsp_ceva_hal_reset_xm6(ceva_hal_handle *handle) ++{ ++ handle->reg_sys.reg02 = REGR(handle->base_sys, 0x02); ++ ++ handle->reg_sys.reg_rstz_ceva_core = 0; ++ handle->reg_sys.reg_rstz_ceva_sys = 0; ++ handle->reg_sys.reg_rstz_ceva_ocem = 0; ++ handle->reg_sys.reg_rstz_ceva_global = 0; ++ handle->reg_sys.reg_rstz_miu = 0; ++ handle->reg_sys.reg_rstz_mcu = 0; ++ handle->reg_sys.reg_rstz_mcu2ceva = 0; ++ handle->reg_sys.reg_rstz_isp2ceva = 0; ++ REGW(handle->base_sys, 0x02, handle->reg_sys.reg02); ++ ++ udelay(1); ++} ++ ++void dsp_ceva_hal_enable_xm6(ceva_hal_handle *handle) ++{ ++ handle->reg_sys.reg02 = REGR(handle->base_sys, 0x02); ++ handle->reg_sys.reg15 = REGR(handle->base_sys, 0x15); ++ ++#ifdef ENABLE_JTAG ++ // set JTAG pin out ++ REGW(BANK_GOP, 0x04, 0x0300); ++#endif // ENABLE_JTAG ++ ++ ++ handle->reg_sys.reg_ceva_boot = 1; ++ // handle->reg_sys.reg_ceva_csysreq = 0; // not sure... ++ REGW(handle->base_sys, 0x15, handle->reg_sys.reg15); ++ ++ handle->reg_sys.reg_rstz_ceva_sys = 1; ++ handle->reg_sys.reg_rstz_ceva_ocem = 1; ++ handle->reg_sys.reg_rstz_ceva_global = 1; ++ handle->reg_sys.reg_rstz_miu = 1; ++ handle->reg_sys.reg_rstz_mcu = 1; ++ handle->reg_sys.reg_rstz_mcu2ceva = 1; ++ handle->reg_sys.reg_rstz_isp2ceva = 1; ++ REGW(handle->base_sys, 0x02, handle->reg_sys.reg02); ++ ++ udelay(1); ++} ++ ++void dsp_ceva_hal_bootup_xm6(ceva_hal_handle *handle, u32 boot_addr) ++{ ++ handle->reg_sys.reg02 = REGR(handle->base_sys, 0x02); ++ ++ // Set boot up address ++ handle->reg_sys.reg_ceva_vector_low = LOW_U16(boot_addr); ++ handle->reg_sys.reg_ceva_vector_high = HIGH_U16(boot_addr); ++ REGW(handle->base_sys, 0x16, handle->reg_sys.reg16); ++ REGW(handle->base_sys, 0x17, handle->reg_sys.reg17); ++ ++ handle->reg_sys.reg_rstz_ceva_core = 1; ++ REGW(handle->base_sys, 0x02, handle->reg_sys.reg02); ++ ++ udelay(1); ++ ++ // Set reset vector as default (0) because ICE may reset again ++ handle->reg_sys.reg_ceva_vector_low = 0; ++ handle->reg_sys.reg_ceva_vector_high = 0; ++ REGW(handle->base_sys, 0x16, handle->reg_sys.reg16); ++ REGW(handle->base_sys, 0x17, handle->reg_sys.reg17); ++} ++ ++void dsp_ceva_hal_reset_warp(ceva_hal_handle *handle) ++{ ++ ++ handle->reg_sys.reg_rstz_warp = 0; // ~CEVA_HAL_RESET_WARP_ALL ++ REGW(handle->base_sys, 0x42, handle->reg_sys.reg42); ++ ++ // delay 1us ++ udelay(1); ++} ++ ++void dsp_ceva_hal_enable_warp(ceva_hal_handle *handle) ++{ ++ ++ handle->reg_sys.reg_rstz_warp = 0; ++ REGW(handle->base_sys, 0x42, handle->reg_sys.reg42); ++ ++ // delay 1us ++ udelay(1); ++ ++ // handle->reg_sys.reg_rstz_warp = 0xFFFF; ++ handle->reg_sys.reg42 = CEVA_HAL_RESET_WARP_ALL; ++ REGW(handle->base_sys, 0x42, handle->reg_sys.reg42); ++ ++ // delay 1us ++ udelay(1); ++} ++ ++void dsp_ceva_hal_set_axi2miu(ceva_hal_handle *handle) ++{ ++ unsigned short axi2miu2_data = 0; ++ unsigned short axi2miu3_data = 0; ++ ++ axi2miu2_data = REGR(handle->base_axi2miu2, 0x02); ++ axi2miu3_data = REGR(handle->base_axi2miu3, 0x02); ++ ++ axi2miu2_data = axi2miu2_data | 0x0001; ++ axi2miu3_data = axi2miu3_data | 0x0001; ++ ++ REGW(handle->base_axi2miu2, 0x02, axi2miu2_data); ++ REGW(handle->base_axi2miu3, 0x02, axi2miu2_data); ++ ++ REGW(handle->base_axi2miu2, 0x01, 0x1010); ++ REGW(handle->base_axi2miu3, 0x01, 0x1010); ++} ++ ++void dsp_ceva_hal_write_dummy_data(ceva_hal_handle *handle, u32 index, u32 data) ++{ ++ switch (index) ++ { ++ case 0: ++ handle->reg_sys.reg_dummy_0 = LOW_U16(data); ++ handle->reg_sys.reg_dummy_1 = HIGH_U16(data); ++ REGW(handle->base_sys, 0x60, handle->reg_sys.reg60); ++ REGW(handle->base_sys, 0x61, handle->reg_sys.reg61); ++ break; ++ ++ case 1: ++ handle->reg_sys.reg_dummy_2 = LOW_U16(data); ++ handle->reg_sys.reg_dummy_3 = HIGH_U16(data); ++ REGW(handle->base_sys, 0x62, handle->reg_sys.reg62); ++ REGW(handle->base_sys, 0x63, handle->reg_sys.reg63); ++ break; ++ ++ default: ++ HAL_MSG(HAL_MSG_ERR, "Only index 0 ~3 are available\n"); ++ ++ } ++} ++ ++u32 dsp_ceva_hal_read_dummy_data(ceva_hal_handle *handle, u32 index) ++{ ++ switch (index) ++ { ++ case 0: ++ handle->reg_sys.reg60 = REGR(handle->base_sys, 0x60); ++ handle->reg_sys.reg61 = REGR(handle->base_sys, 0x61); ++ return MAKE_U32(handle->reg_sys.reg_dummy_1, handle->reg_sys.reg_dummy_0); ++ ++ case 1: ++ handle->reg_sys.reg62 = REGR(handle->base_sys, 0x62); ++ handle->reg_sys.reg63 = REGR(handle->base_sys, 0x63); ++ return MAKE_U32(handle->reg_sys.reg_dummy_3, handle->reg_sys.reg_dummy_2); ++ ++ default: ++ HAL_MSG(HAL_MSG_ERR, "Only index 0 ~3 are available\n"); ++ } ++ ++ return 0; ++} ++ ++u32 dsp_ceva_hal_get_mcci_irq(ceva_hal_handle *handle) ++{ ++ handle->reg_sys.reg0d = REGR(handle->base_sys, 0x0d); ++ handle->reg_sys.reg0e = REGR(handle->base_sys, 0x0e); ++ HAL_MSG(HAL_MSG_DBG, "status %04x %04x\n", handle->reg_sys.reg0e, handle->reg_sys.reg0d); ++ ++ return MAKE_U32(handle->reg_sys.reg0e, handle->reg_sys.reg0d); ++} ++ ++u32 dsp_ceva_hal_check_mcci_irq(ceva_hal_handle *handle, u32 index) ++{ ++ handle->reg_sys.reg0d = REGR(handle->base_sys, 0x0d); ++ handle->reg_sys.reg0e = REGR(handle->base_sys, 0x0e); ++ HAL_MSG(HAL_MSG_DBG, "mcci state %04x-%04x\n", handle->reg_sys.reg0e, handle->reg_sys.reg0d); ++ ++ HAL_MSG(HAL_MSG_DBG, "int state %04x-%04x\n", REGR(handle->base_sys, 0x19), REGR(handle->base_sys, 0x18)); ++ HAL_MSG(HAL_MSG_DBG, "int enable %04x-%04x, %04x, %04x, %04x\n", REGR(handle->base_sys, 0x04), REGR(handle->base_sys, 0x03), REGR(handle->base_sys, 0x05), REGR(handle->base_sys, 0x06), REGR(handle->base_sys, 0x07) ); ++ ++ if (index < 16) { ++ return handle->reg_sys.reg_mcci_rd_ind_low & (1 << index); ++ } else if (index < 32) { ++ return (handle->reg_sys.reg_mcci_rd_ind_high & (1 << index)) << 16; ++ } else { ++ HAL_MSG(HAL_MSG_ERR, "Incorrect index %d\n", index); ++ } ++ ++ return 0; ++} ++ ++void dsp_ceva_hal_clear_mcci_irq(ceva_hal_handle *handle, u32 index) ++{ ++ u16 value; ++ ++ handle->reg_sys.reg0d = REGR(handle->base_sys, 0x0d); ++ handle->reg_sys.reg0e = REGR(handle->base_sys, 0x0e); ++ handle->reg_sys.reg0b = REGR(handle->base_sys, 0x0b); ++ handle->reg_sys.reg0c = REGR(handle->base_sys, 0x0c); ++ ++ HAL_MSG(HAL_MSG_DBG, "status %04x %04x\n", handle->reg_sys.reg0e, handle->reg_sys.reg0d); ++ ++ if (index < 16) { ++ value = 1 << index; ++ value = value|handle->reg_sys.reg0b; ++ handle->reg_sys.reg_mcci_rd_wc_low = value; ++ REGW(handle->base_sys, 0x0b, handle->reg_sys.reg0b); ++ } else if (index < 32) { ++ value = 1 << (index-16); ++ value = value|handle->reg_sys.reg0c; ++ handle->reg_sys.reg_mcci_rd_wc_high = value; ++ REGW(handle->base_sys, 0x0c, handle->reg_sys.reg0c); ++ } else { ++ HAL_MSG(HAL_MSG_ERR, "Incorrect index %d\n", index); ++ } ++ ++ handle->reg_sys.reg0d = REGR(handle->base_sys, 0x0d); ++ handle->reg_sys.reg0e = REGR(handle->base_sys, 0x0e); ++ HAL_MSG(HAL_MSG_DBG, "status %04x %04x\n", handle->reg_sys.reg0e, handle->reg_sys.reg0d); ++} ++ ++void dsp_ceva_hal_clear_mcci_irq_ex(ceva_hal_handle *handle, u32 mask) ++{ ++ handle->reg_sys.reg_mcci_rd_wc_low = LOW_U16(mask); ++ REGW(handle->base_sys, 0x0b, handle->reg_sys.reg0b); ++ ++ handle->reg_sys.reg_mcci_rd_wc_high = HIGH_U16(mask); ++ REGW(handle->base_sys, 0x0c, handle->reg_sys.reg0c); ++} ++ ++void dsp_ceva_hal_check_bodary_status(ceva_hal_handle *handle) ++{ ++ u16 value=0; ++ ++ value=REGR(handle->hw_addr_cevatopctl, 0x24); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x101E Offset:0x24 :0x%04X\n",value); ++ ++ value=REGR(handle->hw_addr_cevapllpower, 0x11); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x162E Offset:0x11 :0x%04X\n",value); ++ ++ value=REGR(handle->hw_addr_cevapllpower, 0x60); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x162E Offset:0x60 :0x%04X\n",value); ++ ++ value=REGR(handle->hw_addr_cevapllpower, 0x61); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x162E Offset:0x61 :0x%04X\n",value); ++ ++ value=REGR(handle->hw_addr_cevapllpower, 0x62); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x162E Offset:0x62 :0x%04X\n",value); ++ ++ value=REGR(handle->base_sys, 0x00); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x1128 Offset:0x0 :0x%04X\n",value); ++ ++ value=REGR(handle->base_sys, 0x40); ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: Bank:0x1128 Offset:0x40 :0x%04X\n",value); ++ ++ return; ++} ++ ++CEVA_VCORE dsp_ceva_hal_read_current_vcore(void) ++{ ++#if 1 ++ CEVA_VCORE Vcore=CEVA_VCORE_XXX_VOLT; ++ U8 VGPIO7=GPIO_LOW; ++ U8 VGPIO8=GPIO_LOW; ++ ++ VGPIO7=MDrv_GPIO_Pad_Read(PAD_PM_GPIO7); ++ VGPIO8=MDrv_GPIO_Pad_Read(PAD_PM_GPIO8); ++ ++ if(VGPIO7 == GPIO_LOW) ++ { ++ Vcore=(VGPIO8==GPIO_LOW)? CEVA_VCORE_090_VOLT : CEVA_VCORE_100_VOLT; ++ } ++ else{ ++ Vcore=(VGPIO8==GPIO_LOW)? CEVA_VCORE_095_VOLT : CEVA_VCORE_105_VOLT; ++ } ++ ++ return Vcore; ++#else ++ CEVA_VCORE Vcore=CEVA_VCORE_095_VOLT; ++ ++ return Vcore; ++#endif ++} ++ ++void hal_set_DVFS(u32 FastMood) ++{ ++ struct device_node *np = NULL; ++ struct clk *clk; ++ unsigned int Freq=0; ++ unsigned int errFlg=0; ++ ++ np = of_find_node_by_name(NULL, "xm6"); ++ ++ if (np == NULL) ++ { ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: DVFS get node error\n"); ++ errFlg=1; ++ } ++ ++ clk = of_clk_get(np, 0); ++ ++ if (clk == NULL) ++ { ++ HAL_MSG(HAL_MSG_ERR, "CEVA Error: DVFS get clk error\n"); ++ errFlg=1; ++ } ++ ++ if(!errFlg){ ++ Freq=(FastMood==1)?600000000:500000000; ++ clk_set_rate(clk, Freq); ++ } ++ ++ return; ++} ++ ++void dsp_ceva_hal_set_PLL(ceva_hal_handle *handle,u32 FastMood) ++{ ++ u16 value=0; ++ ++ hal_set_DVFS(FastMood); ++ ++ HAL_MSG(HAL_MSG_WRN, "dsp_ceva_hal_set_PLL FastMood %d\n", FastMood); ++ ++ value=REGR(handle->hw_addr_cevapllpower, 0x60); ++ HAL_MSG(HAL_MSG_WRN, "CEVA: Bank:0x162E Offset:0x60 :0x%04X\n",value); ++ ++ value=REGR(handle->hw_addr_cevapllpower, 0x61); ++ HAL_MSG(HAL_MSG_WRN, "CEVA: Bank:0x162E Offset:0x61 :0x%04X\n",value); ++ ++ return; ++} ++ ++unsigned int dsp_ceva_hal_read_gpout(ceva_hal_handle *handle) ++{ ++ u16 tmp0=0; ++ u16 tmp1=0; ++ unsigned int ret=0; ++ ++ handle->reg_sys.reg1e = REGR(handle->base_sys, 0x1e); ++ tmp0=handle->reg_sys.reg_ceva_gpout_low; ++ //printk("reg_ceva_gpout_low:0x%x ",tmp); ++ ++ handle->reg_sys.reg1f = REGR(handle->base_sys, 0x1f); ++ tmp1=handle->reg_sys.reg_ceva_gpout_high; ++ //printk("reg_ceva_gpout_high:0x%x \n",tmp); ++ ret=(tmp0&0xffff)|((tmp1&0xffff)<<16); ++ ++ return ret; ++} ++ ++#if 0 ++ ++void dsp_ceva_hal_set_new_vcore(CEVA_VCORE NewV) ++{ ++ MDrv_GPIO_Pad_Set(PAD_PM_GPIO7); ++ MDrv_GPIO_Pad_Set(PAD_PM_GPIO8); ++ ++ switch (NewV) ++ { ++ case CEVA_VCORE_090_VOLT: ++ MDrv_GPIO_Set_Low(PAD_PM_GPIO7); ++ MDrv_GPIO_Set_Low(PAD_PM_GPIO8); ++ break; ++ case CEVA_VCORE_095_VOLT: ++ MDrv_GPIO_Set_High(PAD_PM_GPIO7); ++ MDrv_GPIO_Set_Low(PAD_PM_GPIO8); ++ break; ++ case CEVA_VCORE_100_VOLT: ++ MDrv_GPIO_Set_Low(PAD_PM_GPIO7); ++ MDrv_GPIO_Set_High(PAD_PM_GPIO8); ++ break; ++ case CEVA_VCORE_105_VOLT: ++ MDrv_GPIO_Set_High(PAD_PM_GPIO7); ++ MDrv_GPIO_Set_High(PAD_PM_GPIO8); ++ break; ++ default: ++ MDrv_GPIO_Set_Low(PAD_PM_GPIO7); ++ MDrv_GPIO_Set_Low(PAD_PM_GPIO8); ++ break; ++ } ++ mdelay(1); ++ HAL_MSG(HAL_MSG_DBG, "dsp_ceva_hal_set_new_vcore %d\n", NewV); ++ return; ++} ++ ++void dsp_ceva_hal_check_irq(ceva_hal_handle *handle) ++{ ++ handle->reg_sys.reg03 = REGR(handle->base_sys, 0x03); ++ handle->reg_sys.reg03 &= 0xB000; ++ REGW(handle->base_sys, 0x03, handle->reg_sys.reg03); ++ ++ return; ++} ++ ++void dsp_ceva_hal_test(ceva_hal_handle *handle) ++{ ++ u16 tmp=0; ++ ++ dsp_ceva_hal_reset_xm6(handle); ++ ++ handle->reg_sys.reg15 = REGR(handle->base_sys, 0x15); ++ handle->reg_sys.reg_ceva_boot = 0; ++ REGW(handle->base_sys, 0x15, handle->reg_sys.reg15); ++ ++ handle->reg_sys.reg_ceva_vector_low = 0; ++ handle->reg_sys.reg_ceva_vector_high = 0; ++ REGW(handle->base_sys, 0x16, handle->reg_sys.reg16); ++ REGW(handle->base_sys, 0x17, handle->reg_sys.reg17); ++ ++ handle->reg_sys.reg_rstz_ceva_sys = 1; ++ handle->reg_sys.reg_rstz_ceva_ocem = 1; ++ handle->reg_sys.reg_rstz_ceva_global = 1; ++ handle->reg_sys.reg_rstz_miu = 1; ++ handle->reg_sys.reg_rstz_mcu = 1; ++ handle->reg_sys.reg_rstz_mcu2ceva = 1; ++ handle->reg_sys.reg_rstz_isp2ceva = 1; ++ REGW(handle->base_sys, 0x02, handle->reg_sys.reg02); ++ ++ udelay(1); ++ ++ handle->reg_sys.reg_rstz_ceva_sys = 1; ++ handle->reg_sys.reg_rstz_ceva_ocem = 1; ++ handle->reg_sys.reg_rstz_ceva_global = 1; ++ handle->reg_sys.reg_rstz_miu = 1; ++ handle->reg_sys.reg_rstz_mcu = 1; ++ handle->reg_sys.reg_rstz_mcu2ceva = 1; ++ handle->reg_sys.reg_rstz_isp2ceva = 1; ++ handle->reg_sys.reg_rstz_ceva_core = 1; ++ REGW(handle->base_sys, 0x02, handle->reg_sys.reg02); ++ ++ ++ handle->reg_sys.reg02 = REGR(handle->base_sys, 0x02); ++ tmp=handle->reg_sys.reg02; ++ printk("reg02:0x%x ",tmp); ++ ++ handle->reg_sys.reg15 = REGR(handle->base_sys, 0x15); ++ tmp=handle->reg_sys.reg15; ++ printk("reg15:0x%x ",tmp); ++ ++ handle->reg_sys.reg16 = REGR(handle->base_sys, 0x16); ++ tmp=handle->reg_sys.reg16; ++ printk("reg16:0x%x ",tmp); ++ ++ handle->reg_sys.reg17 = REGR(handle->base_sys, 0x17); ++ tmp=handle->reg_sys.reg17; ++ printk("reg17:0x%x \n",tmp); ++ ++ dump_bank_register(0x0030); ++ dump_bank_register(0x1019); ++ dsp_ceva_hal_check_bodary_status(handle); ++ ++ return; ++} ++#endif +diff --git a/drivers/sstar/ceva_link/hal_ceva.h b/drivers/sstar/ceva_link/hal_ceva.h +new file mode 100644 +index 000000000000..ca91add4203c +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_ceva.h +@@ -0,0 +1,137 @@ ++#ifndef HAL_CEVA_H ++#define HAL_CEVA_H ++ ++#include "hal_ceva_reg.h" ++#include ++ ++typedef enum ++{ ++ CEVA_HAL_XM6_PWR_DISABLE = 0x0, ++ CEVA_HAL_XM6_PWR_ENABLE = 0x1 ++} CEVA_HAL_XM6_PWR; ++ ++typedef enum ++{ ++ CEVA_HAL_RESET_WARP_SYS = 0x01, ++ CEVA_HAL_RESET_WARP_MIU = 0x02, ++ CEVA_HAL_RESET_WARP_MCU = 0x04, ++ CEVA_HAL_RESET_WARP_ALL = 0x07, ++} CEVA_HAL_RESET_WARP; ++ ++typedef enum ++{ ++ CEVA_HAL_IRQ_GVI = 0x00000001, // General Violation Indication ++ CEVA_HAL_IRQ_UOP = 0x00000002, // Undefined Opcode Interrupt ++ CEVA_HAL_IRQ_PI = 0x00000004, // Permission Interrupt ++ CEVA_HAL_IRQ_MAPV = 0x00000008, // Access Protection Violation ++ CEVA_HAL_IRQ_EDP_WDOG = 0x00000010, // EDP Watchdog Timeout ++ CEVA_HAL_IRQ_IOP_WDOG = 0x00000020, // I/O Port Watchdog Timeout ++ CEVA_HAL_IRQ_EPP_WDOG = 0x00000040, // EPP Watchdog timeout ++ CEVA_HAL_IRQ_SNOOP0 = 0x00000080, // Snooping Interrupt 0 ++ CEVA_HAL_IRQ_SNOOP1 = 0x00000100, // Snooping Interrupt 1 ++ CEVA_HAL_IRQ_MCCI_MES = 0x00000200, // Multicore Messaging Interface Interrupt ++ CEVA_HAL_IRQ_DDMA_DBG_MATCH = 0x00000400, // External Acknowledge for DDMA debug match ++ CEVA_HAL_IRQ_QMAN = 0x00008000, // QMAN Violation Indications Interrupt ++ CEVA_HAL_IRQ_WARP = 0x00001000, // WARP Accelerator Output Interrupt ++ CEVA_HAL_IRQ_MCCI_RD = 0x00002000, // Multicore Messaging Interface read indication ++ CEVA_HAL_IRQ_ISP2CEVA_INT = 0x00004000, // Interrupt Signal from MStar side = 0x0000, // such as timer interrpt ++ CEVA_HAL_IRQ_INT0 = 0x00010000, // XM6 Maskable interrupt 0 ++ CEVA_HAL_IRQ_INT1 = 0x00020000, // XM6 Maskable interrupt 1 ++ CEVA_HAL_IRQ_INT2 = 0x00040000, // XM6 Maskable interrupt 2 ++ CEVA_HAL_IRQ_INT3 = 0x00080000, // XM6 Maskable interrupt 3 ++ CEVA_HAL_IRQ_INT4 = 0x00100000, // XM6 Maskable interrupt 4 ++ CEVA_HAL_IRQ_BP = 0x00200000, // XM6 Emulation software interrupt / Breakpoint interrupt ++ CEVA_HAL_IRQ_NMI = 0x00400000, // XM6 Non-maskable interrupt ++ CEVA_HAL_IRQ_VINT = 0x00800000, // XM6 Vectored interrupt ++ CEVA_HAL_IRQ_TRP_SRV = 0x01000000, // XM6 Software interrupt ++ CEVA_HAL_IRQ_GPOUT_31 = 0x02000000, // XM6 General-purpose output pin 31 ++ CEVA_HAL_IRQ_OCM_GPOUT_3 = 0x04000000, // XM6 OCM General-purpose output pin 3 ++} CEVA_HAL_IRQ; ++ ++typedef enum ++{ ++ CEVA_HAL_IRQ_TARGET_ARM = 0, ++ CEVA_HAL_IRQ_TARGET_XM6_INT0 = 1, ++ CEVA_HAL_IRQ_TARGET_XM6_INT1 = 2, ++ CEVA_HAL_IRQ_TARGET_XM6_INT2 = 3, ++ CEVA_HAL_IRQ_TARGET_XM6_NMI = 4, ++ CEVA_HAL_IRQ_TARGET_XM6_VINT = 5, ++} CEVA_HAL_IRQ_TARGET; ++ ++typedef enum ++{ ++ CEVA_VCORE_090_VOLT = 0, ++ CEVA_VCORE_095_VOLT = 1, ++ CEVA_VCORE_100_VOLT = 2, ++ CEVA_VCORE_105_VOLT = 3, ++ CEVA_VCORE_XXX_VOLT = 4, ++} CEVA_VCORE; ++ ++typedef struct ++{ ++ phys_addr_t base_sys; ++ ceva_hal_reg_sys reg_sys; ++ ++ phys_addr_t base_axi2miu0; ++ ceva_hal_reg_bus reg_axi2miu0; ++ ++ phys_addr_t base_axi2miu1; ++ ceva_hal_reg_bus reg_axi2miu1; ++ ++ phys_addr_t base_axi2miu2; ++ ceva_hal_reg_bus reg_axi2miu2; ++ ++ phys_addr_t base_axi2miu3; ++ ceva_hal_reg_bus reg_axi2miu3; ++ ++ phys_addr_t hw_addr_cevatopctl; ++ ceva_hal_reg_bus reg_cevatopctl; ++ ++ phys_addr_t hw_addr_cevapllpower; ++ ceva_hal_reg_bus reg_cevapllpower; ++ ++ CEVA_VCORE InitVCore; ++} ceva_hal_handle; ++ ++ ++ ++#define GPIO_LOW 0 ++#define GPIO_HIGH 1 ++ ++void dsp_ceva_hal_init(ceva_hal_handle *handle, phys_addr_t base_sys, phys_addr_t base_axi2miu0, phys_addr_t base_axi2miu1, phys_addr_t base_axi2miu2, phys_addr_t base_axi2miu3); ++void dsp_ceva_hal_init_cevatop(ceva_hal_handle *handle, phys_addr_t hw_addr_cevatopctl, phys_addr_t hw_addr_cevapllpower); ++void dsp_ceva_hal_init_VCore(ceva_hal_handle *handle, CEVA_VCORE InitVCore); ++void dsp_ceva_hal_enable_irq(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target, CEVA_HAL_IRQ irq); ++void dsp_ceva_hal_disable_irq(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target, CEVA_HAL_IRQ irq); ++CEVA_HAL_IRQ dsp_ceva_hal_get_irq_mask(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target); ++CEVA_HAL_IRQ dsp_ceva_hal_get_irq_status(ceva_hal_handle *handle); ++ ++void dsp_ceva_hal_reset_xm6(ceva_hal_handle *handle); ++void dsp_ceva_hal_enable_xm6(ceva_hal_handle *handle); ++void dsp_ceva_hal_bootup_xm6(ceva_hal_handle *handle, u32 boot_addr); ++ ++void dsp_ceva_hal_reset_warp(ceva_hal_handle *handle); ++void dsp_ceva_hal_enable_warp(ceva_hal_handle *handle); ++void dsp_ceva_hal_set_axi2miu(ceva_hal_handle *handle); ++ ++void dsp_ceva_hal_write_dummy_data(ceva_hal_handle *handle, u32 index, u32 data); ++u32 dsp_ceva_hal_read_dummy_data(ceva_hal_handle *handle, u32 index); ++ ++u32 dsp_ceva_hal_get_mcci_irq(ceva_hal_handle *handle); ++u32 dsp_ceva_hal_check_mcci_irq(ceva_hal_handle *handle, u32 index); ++void dsp_ceva_hal_clear_mcci_irq(ceva_hal_handle *handle, u32 index); ++void dsp_ceva_hal_clear_mcci_irq_ex(ceva_hal_handle *handle, u32 mask); ++ ++void dsp_ceva_hal_check_bodary_status(ceva_hal_handle *handle); ++CEVA_VCORE dsp_ceva_hal_read_current_vcore(void); ++void dsp_ceva_hal_set_PLL(ceva_hal_handle *handle,u32 FastMood); ++unsigned int dsp_ceva_hal_read_gpout(ceva_hal_handle *handle); ++ ++#if 0 ++void dsp_ceva_hal_test(ceva_hal_handle *handle); ++void dsp_ceva_hal_check_irq(ceva_hal_handle *handle); ++void dsp_ceva_hal_get_irq(ceva_hal_handle *handle,u32 idx); ++void dsp_ceva_hal_set_new_vcore(CEVA_VCORE NewV); ++#endif ++ ++#endif // HAL_CEVA_H +diff --git a/drivers/sstar/ceva_link/hal_ceva_reg.h b/drivers/sstar/ceva_link/hal_ceva_reg.h +new file mode 100644 +index 000000000000..1e52c5365792 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_ceva_reg.h +@@ -0,0 +1,2342 @@ ++#ifndef __HAL_CEVA_REG_H__ ++#define __HAL_CEVA_REG_H__ ++ ++#include ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_forbidden:1; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_div_num_bus:4; ++ u16 reg_div_num_wdog:4; ++ u16 reg_div_num_warp:4; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rstz_ceva_core:1; ++ u16 reg_rstz_ceva_sys:1; ++ u16 reg_rstz_ceva_ocem:1; ++ u16 reg_rstz_ceva_global:1; ++ u16 reg_rstz_miu:1; ++ u16 reg_rstz_mcu:1; ++ u16 reg_rstz_mcu2ceva:1; ++ u16 reg_rstz_isp2ceva:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva2riu_int_en:16; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva2riu_int_en2:16; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_int0_en:16; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_int1_en:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_int2_en:16; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_nmi_en:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_vint_en:16; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_uop_int_wc:1; ++ }; ++ u16 reg0a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_wc_low:16; ++ }; ++ u16 reg0b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_wc_high:16; ++ }; ++ u16 reg0c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_ind_low:16; ++ }; ++ u16 reg0d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_ind_high:16; ++ }; ++ u16 reg0e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_warp_r1_sel:1; ++ u16 reg_warp_r2_sel:1; ++ u16 reg_warp_w1_sel:1; ++ u16 reg_warp_w1_sel2:1; ++ u16 reg_rq_mask_miu:4; ++ u16 reg_rq_mask_imi:4; ++ }; ++ u16 reg0f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_dbus_low:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_dbus_high:8; ++ u16 reg_ceva_dbus_sel:8; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clktest_in:8; ++ u16 reg_clktest_out:8; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva2mcu_ldz_en:1; ++ u16 reg_ceva2isp_ldz_en:1; ++ u16 reg_ceva_eflag_wc:1; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mi02ceva_last_done_z:1; ++ u16 reg_mi12ceva_last_done_z:1; ++ u16 reg_mi22ceva_last_done_z:1; ++ u16 reg_mi32ceva_last_done_z:1; ++ u16 reg_imi02ceva_last_done_z:1; ++ u16 reg_imi12ceva_last_done_z:1; ++ u16 reg_imi22ceva_last_done_z:1; ++ u16 reg_imi32ceva_last_done_z:1; ++ u16 reg_ceva2mcu_last_done_z:1; ++ u16 reg_ceva2isp_last_done_z:1; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_boot:1; ++ u16 reg_ceva_csysreq:1; ++ u16 reg_ceva_core_rcvr:1; ++ u16 reg_ceva_external_wait:1; ++ u16 reg_ceva_mcache_invalidate_strap:1; ++ u16 reg_ceva_acu_lock:1; ++ u16 reg_ceva_acu_slv_acc:1; ++ u16 reg_ceva_ddma_dbg_match_ack:1; ++ u16 reg_ceva_next_ddma:1; ++ u16 reg_ceva_bs_reg_tdo:1; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_vector_low:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_vector_high:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_is:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_is2:16; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_psu_dsp_idle:1; ++ u16 reg_ceva_psu_core_idle:1; ++ u16 reg_ceva_psu_core_wait:1; ++ u16 reg_ceva_psu_cactive:1; ++ u16 reg_ceva_psu_csysack:1; ++ u16 reg_ceva_epp_aps:1; ++ u16 reg_ceva_iop_aps:1; ++ u16 reg_ceva_edp_aps:1; ++ }; ++ u16 reg1a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_ocm_gp_out:4; ++ u16 reg_ceva_ocm_jtag_state:4; ++ u16 reg_ceva_ocm_core_rst:1; ++ u16 reg_ceva_ocm_debug:1; ++ u16 reg_ceva_cverbit:1; ++ u16 reg_ceva_seq_eotbit:1; ++ u16 reg_ceva_seq_om:2; ++ }; ++ u16 reg1b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpin_low:16; ++ }; ++ u16 reg1c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpin_high:16; ++ }; ++ u16 reg1d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpout_low:16; ++ }; ++ u16 reg1e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpout_high:16; ++ }; ++ u16 reg1f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_qman_desc_en:8; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_xiu_be_err:1; ++ u16 reg_ceva2mcu_bresp:1; ++ u16 reg_ceva2mcu_rresp:1; ++ u16 reg_ceva2mcu_wstrb:1; ++ u16 reg_ceva2isp_bresp:1; ++ u16 reg_ceva2isp_rresp:1; ++ u16 reg_ceva2isp_wstrb:1; ++ u16 reg_epp_awlen:1; ++ u16 reg_epp_arlen:1; ++ u16 reg_edp_awlen:1; ++ u16 reg_edp_arlen:1; ++ u16 reg_axir1_arlen:1; ++ u16 reg_axir2_arlen:1; ++ u16 reg_axiw1_awlen:1; ++ u16 reg_apb_pslverr:1; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_axi_maxlen:8; ++ u16 reg_ceva_apbs_paddr:3; ++ u16 reg_ceva_jt_ap:1; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_forbidden_1:1; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rstz_warp:3; ++ }; ++ u16 reg42; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_warp2cmdq_trig_en:16; ++ }; ++ u16 reg43; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_warp2cmdq_trig_en2:16; ++ }; ++ u16 reg44; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_0:16; ++ }; ++ u16 reg60; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_1:16; ++ }; ++ u16 reg61; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_2:16; ++ }; ++ u16 reg62; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_3:16; ++ }; ++ u16 reg63; ++ }; ++ ++}ceva_hal_reg_sys; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg0b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg0c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg0d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg0e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg0f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg1a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg1b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg1c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg1d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg1e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg1f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg26; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg37; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg38; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg3a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg3b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg3c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg3d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg3e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg3f; ++ }; ++#if 1 ++}ceva_hal_reg_bus; ++#else ++// Maybe we can use a single structure for all axi2miu buses, maybe not... ++}ceva_hal_reg_bus_axi2miu0; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg41; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg42; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg43; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg44; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg45; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg46; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg47; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg48; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg49; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg4b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg4c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg4d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg4e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg4f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg50; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg51; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg52; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg53; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg54; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg55; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg56; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg57; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg58; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg59; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg5a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg5b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg5c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg5d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg5e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg5f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg60; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg61; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg62; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg63; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg64; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg65; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg66; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg77; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg78; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg7a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg7b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg7c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg7d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg7e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg7f; ++ }; ++}ceva_hal_reg_bus_axi2miu1; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg0b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg0c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg0d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg0e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg0f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg1a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg1b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg1c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg1d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg1e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg1f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg26; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg37; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg38; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg3a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg3b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg3c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg3d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg3e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg3f; ++ }; ++}ceva_hal_reg_bus_axi2miu2; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg41; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg42; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg43; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg44; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg45; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg46; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg47; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg48; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg49; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg4b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg4c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg4d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg4e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg4f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg50; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg51; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg52; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg53; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg54; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg55; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg56; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg57; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg58; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg59; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg5a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg5b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg5c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg5d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg5e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg5f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg60; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg61; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg62; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg63; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg64; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg65; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg66; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg77; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg78; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg7a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg7b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg7c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg7d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg7e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg7f; ++ }; ++}ceva_hal_reg_bus_axi2miu3; ++#endif ++#endif // __HAL_CEVA_REG_H__ +diff --git a/drivers/sstar/ceva_link/hal_cpm.c b/drivers/sstar/ceva_link/hal_cpm.c +new file mode 100644 +index 000000000000..1897c33fb6ca +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_cpm.c +@@ -0,0 +1,46 @@ ++#include "hal_cpm.h" ++#include "ms_platform.h" ++#include ++#include ++#include ++ ++#include "hal_debug.h" ++ ++ ++#define LOW_U16(value) (((u32)(value))&0x0000FFFF) ++#define HIGH_U16(value) ((((u32)(value))&0xFFFF0000)>>16) ++ ++#define MAKE_U32(high, low) ((((u32)high)<<16) || low) ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) *((volatile u32*)((u32)(base)+(idx))) ++#define REGW(base,idx,val) do{*((volatile u32*)((u32)(base)+(idx))) = (val);} while(0) ++#else ++#define REGR(base,idx) *((volatile u32*)((uint)(base)+(idx))) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)(base)+(idx)), val); *((volatile u32*)((uint)(base)+(idx))) = (val);} while(0) ++#endif ++ ++void cmp_hal_init(cpm_hal_handle *handle, phys_addr_t base_addr) ++ ++{ ++ memset(handle, 0, sizeof(handle[0])); ++ handle->base_addr = (phys_addr_t)ioremap_nocache(base_addr, 0x100); ++ ++ HAL_MSG(HAL_MSG_DBG, "base addr 0x%X, remapped 0x%X\n", base_addr, handle->base_addr); ++} ++ ++void cmp_hal_mcci_write(cpm_hal_handle *handle, u32 index, u32 value) ++{ ++ index *= 4; ++ ++ REGW(handle->base_addr, index, value); ++} ++ ++u16 cmp_hal_mcci_read(cpm_hal_handle *handle, u32 index) ++{ ++ u16 ret=0; ++ index *= 4; ++ ++ ret=REGR(handle->base_addr, index); ++ return ret; ++} +\ No newline at end of file +diff --git a/drivers/sstar/ceva_link/hal_cpm.h b/drivers/sstar/ceva_link/hal_cpm.h +new file mode 100644 +index 000000000000..8bed4124e8c7 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_cpm.h +@@ -0,0 +1,15 @@ ++#ifndef _HAL_CMP_H_ ++#define _HAL_CMP_H_ ++ ++#include ++ ++typedef struct ++{ ++ phys_addr_t base_addr; ++} cpm_hal_handle; ++ ++void cmp_hal_init(cpm_hal_handle *handle, phys_addr_t base_addr); ++void cmp_hal_mcci_write(cpm_hal_handle *handle, u32 index, u32 value); ++u16 cmp_hal_mcci_read(cpm_hal_handle *handle, u32 index); ++ ++#endif // _HAL_CMP_H_ +diff --git a/drivers/sstar/ceva_link/hal_debug.h b/drivers/sstar/ceva_link/hal_debug.h +new file mode 100644 +index 000000000000..5fcbd47df134 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_debug.h +@@ -0,0 +1,38 @@ ++#ifndef __HAL_DEBUG_H__ ++#define __HAL_DEBUG_H__ ++ ++#include ++ ++// Defines debug message levels of HAL_MSG ++#define HAL_MSG_ERR 3 ++#define HAL_MSG_WRN 4 ++#define HAL_MSG_DBG 5 ++ ++#define HAL_MSG_LEVL HAL_MSG_WRN ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#define HAL_MSG_ENABLE // enable/disable message ++#define HAL_MSG_FUNC_ENABLE // enable/disable function name dump ++ ++#if defined(HAL_MSG_ENABLE) ++ ++#define HAL_STRINGIFY(x) #x ++#define HAL_TOSTRING(x) HAL_STRINGIFY(x) ++ ++#if defined(HAL_MSG_FUNC_ENABLE) ++#define HAL_MSG_TITLE "[HAL, %s] " ++#define HAL_MSG_FUNC __func__ ++#else // NOT defined(HAL_MSG_FUNC_ENABLE) ++#define HAL_MSG_TITLE "[HAL] %s" ++#define HAL_MSG_FUNC "" ++#endif // NOT defined(HAL_MSG_FUNC_ENABLE) ++ ++#define HAL_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= HAL_MSG_LEVL) { \ ++ printk(KERN_SOH HAL_TOSTRING(dbglv) HAL_MSG_TITLE _fmt, HAL_MSG_FUNC, ## _args); \ ++ } while(0) ++#else // NOT defined(HAL_MSG_ENABLE) ++#define HAL_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(HAL_MSG_ENABLE) ++ ++#endif // __HAL_DEBUG_H__ +diff --git a/drivers/sstar/ceva_link/hal_intr_ctrl.c b/drivers/sstar/ceva_link/hal_intr_ctrl.c +new file mode 100644 +index 000000000000..2281210c29b7 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_intr_ctrl.c +@@ -0,0 +1,29 @@ ++#include "hal_intr_ctrl.h" ++#include "ms_platform.h" ++#include ++ ++#define LOW_U16(value) (((u32)(value))&0x0000FFFF) ++#define HIGH_U16(value) ((((u32)(value))&0xFFFF0000)>>16) ++ ++#define MAKE_U32(high, low) ((((u32)high)<<16) || low) ++ ++#if 1 ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{IVE_MSG(IVE_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++void intr_ctrl_hal_init(intr_ctrl_hal_handle *handle, phys_addr_t base_addr) ++{ ++ memset(handle, 0, sizeof(handle[0])); ++ handle->base_addr = base_addr; ++} ++ ++void intr_ctrl_hal_software_interrupt(intr_ctrl_hal_handle *handle, INTR_CTRL_HAL_SOFT_INTERRUPT interrupt) ++{ ++ handle->register.reg22 = REGR(handle->base_sys, 0x22); ++ handle->register.reg_hst1_fiq_force_47_32 |= interrupt; ++ REGW(handle->base_addr, 0x22, handle->register.reg22); ++} +diff --git a/drivers/sstar/ceva_link/hal_intr_ctrl.h b/drivers/sstar/ceva_link/hal_intr_ctrl.h +new file mode 100644 +index 000000000000..cc5f24c432af +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_intr_ctrl.h +@@ -0,0 +1,36 @@ ++#ifndef HAL_INTR_CTRL_1_H ++#define HAL_INTR_CTRL_1_H ++ ++#include "hal_intr_ctrl_reg.h" ++ ++typedef enum { ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_0_TO_HOST_3 = 0x00000010, // 36 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_0_TO_HOST_2 = 0x00000020, // 37 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_0_TO_HOST_1 = 0x00000040, // 38 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_0_TO_HOST_4 = 0x00000080, // 39 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_1_TO_HOST_3 = 0x00000100, // 40 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_1_TO_HOST_2 = 0x00000200, // 41 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_1_TO_HOST_0 = 0x00000400, // 42 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_1_TO_HOST_4 = 0x00000800, // 43 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_2_TO_HOST_3 = 0x00001000, // 44 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_2_TO_HOST_1 = 0x00002000, // 45 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_2_TO_HOST_0 = 0x00004000, // 46 ++ /* ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_2_TO_HOST_4 = 0x00008000, // 47 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_3_TO_HOST_2 = 0x00010000, // 48 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_3_TO_HOST_1 = 0x00020000, // 49 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_3_TO_HOST_0 = 0x00040000, // 50 ++ INTR_CTRL_HAL_SOFT_INTERRUPT_HOST_3_TO_HOST_4 = 0x00080000, // 51 ++ */ ++} INTR_CTRL_HAL_SOFT_INTERRUPT; ++ ++typedef struct ++{ ++ phys_addr_t base_addr; ++ int_ctl_hal_reg register; ++} intr_ctrl_hal_handle; ++ ++void intr_ctrl_hal_init(intr_ctrl_hal_handle *handle, phys_addr_t base_addr); ++void intr_ctrl_hal_software_interrupt(intr_ctrl_hal_handle *handle, INTR_CTRL_HAL_SOFT_INTERRUPT interrupt); ++ ++#endif // HAL_INTR_CTRL_1_H +diff --git a/drivers/sstar/ceva_link/hal_intr_ctrl_reg.h b/drivers/sstar/ceva_link/hal_intr_ctrl_reg.h +new file mode 100644 +index 000000000000..15a2b7100131 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_intr_ctrl_reg.h +@@ -0,0 +1,19 @@ ++#ifndef HAL_INTR_CTRL_1_REG_H ++#define HAL_INTR_CTRL_1_REG_H ++ ++#include ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_hst1_fiq_force_47_32:16; ++ }; ++ u16 reg22; ++ }; ++ ++} int_ctl_hal_reg; ++#endif ++#endif //HAL_INTR_CTRL_1_REG_H +\ No newline at end of file +diff --git a/drivers/sstar/ceva_link/hal_timer.c b/drivers/sstar/ceva_link/hal_timer.c +new file mode 100644 +index 000000000000..4b86ca59b61b +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_timer.c +@@ -0,0 +1,89 @@ ++#include "hal_timer.h" ++#include "hal_debug.h" ++ ++#define RIU_BASE_ADDR (0x1F000000) ++#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR)) ++ ++#define BANK_TIMER (BANK_CAL(0x0030)) ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++/******************************************************************************************************************* ++ * dsp_timer_hal_init ++ * init device timer ++ * ++ * Parameters: ++ * RIU_BASE_ADDR: RIU base address ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++#define BANK_IRQ (BANK_CAL(0x1019)) ++ ++ ++int dsp_timer_hal_init(void) ++{ ++ int err_state = 0; ++ ++ //REGW(BANK_IRQ, 0x2C, 0x0001); //LSB period, (1ms, 12*1000) ++#if 1 ++ #if 0 ++ //set timer 0 ++ REGW(BANK_TIMER, 0x12, 0x2EE0); //LSB period, (1ms, 12*1000) ++ REGW(BANK_TIMER, 0x13, 0x0000); //MSB ++ ++ REGW(BANK_TIMER, 0x10, 0x0101); //enable timer 0 ++ #endif ++ ++ #if 0 ++ //set timer 1 ++ REGW(BANK_TIMER, 0x22, 0x2EE0); //LSB period, (1ms, 12*1000) ++ REGW(BANK_TIMER, 0x23, 0x0000); //MSB ++ ++ REGW(BANK_TIMER, 0x20, 0x0101); //enable timer 0 ++ #endif ++ ++ #if 1 ++ //set timer 2 ++ REGW(BANK_TIMER, 0x32, 0x2EE0); //LSB period, (1ms, 12*1000) ++ REGW(BANK_TIMER, 0x33, 0x0000); //MSB ++ ++ REGW(BANK_TIMER, 0x30, 0x0101); //enable timer 0 ++ #endif ++ ++#endif ++ return err_state; ++} ++ ++void dump_bank_register(unsigned int Bank) ++{ ++ unsigned int tmp=0; ++ unsigned int xx=0; ++ unsigned int int_bank; ++ ++ int_bank=BANK_CAL(Bank); ++ ++ printk("CEVA dump_bank_register: Bank:0x%04X\n",Bank); ++ ++ for(xx=0;xx<0x80;xx++) ++ { ++ tmp=REGR(int_bank,xx); ++ if(xx%8 == 0) ++ { ++ printk("%02X ",xx); ++ } ++ printk("%04X ",tmp&0xffff); ++ if(xx%8 == 7) ++ { ++ printk("\n"); ++ } ++ } ++ printk("\n"); ++ ++} +\ No newline at end of file +diff --git a/drivers/sstar/ceva_link/hal_timer.h b/drivers/sstar/ceva_link/hal_timer.h +new file mode 100644 +index 000000000000..f9d6b93592c7 +--- /dev/null ++++ b/drivers/sstar/ceva_link/hal_timer.h +@@ -0,0 +1,9 @@ ++#ifndef HAL_TIMER_H ++#define HAL_TIMER_H ++ ++#include "ms_platform.h" ++#include ++int dsp_timer_hal_init(void); ++ ++void dump_bank_register(unsigned int Bank); ++#endif +diff --git a/drivers/sstar/ceva_link/jni/test.c b/drivers/sstar/ceva_link/jni/test.c +new file mode 100644 +index 000000000000..2d628bfc38f9 +--- /dev/null ++++ b/drivers/sstar/ceva_link/jni/test.c +@@ -0,0 +1,391 @@ ++/* ++ * test.c ++ * ++ * Created on: Aug 16, 2013 ++ * Author: Ido Reis ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define FILENAME "/dev/" CEVA_PCIDEV_DEVICE_NAME "0" ++ ++#define LOG(fmt, args...) printf(fmt "\n", ## args) ++ ++static void SIGIO_handler(int i) { ++ LOG("IO alert, read is possible without blocking :)\n"); ++} ++ ++typedef struct exec_cmd_arg_t { ++ const char* name; ++ const char* description; ++} exec_cmd_arg_t; ++ ++typedef struct exec_cmd_t { ++ const char *name; ++ const char *description; ++ const exec_cmd_arg_t *argv; ++ int argc; ++ int (*exec_func)(int argc, char *argv[]); ++} exec_cmd_t; ++ ++static int do_stat(int argc, char *argv[]); ++static int do_bypass(int argc, char *argv[]); ++static int do_write(int argc, char *argv[]); ++static int do_read(int argc, char *argv[]); ++static int do_geni(int argc, char *argv[]); ++static int do_dma_w(int argc, char *argv[]); ++static int do_dma_r(int argc, char *argv[]); ++static int do_help(int argc, char *argv[]); ++ ++const exec_cmd_arg_t write_args[] = { ++ { "offset ", "bar0 offset to write data" }, ++ { "data ", "32 bit data in hexadeciaml format" }, ++}; ++ ++const exec_cmd_arg_t read_args[] = { ++ { "offset ", "bar0 offset to write data" }, ++}; ++ ++const exec_cmd_arg_t dma_w_args[] = { ++ { "offset ", "offset within the dma buffer" }, ++ { "size ", "number of bytes to write" }, ++ { "file name ", "file content will be written into the dma buffer" }, ++}; ++ ++const exec_cmd_arg_t dma_r_args[] = { ++ { "offset ", "offset within the dma buffer" }, ++ { "size ", "number of bytes to write" }, ++ { "file name ", "dma buffer content will be read into the file" }, ++}; ++ ++const exec_cmd_arg_t geni_args[] = { ++ { "interrupt ", "interrupt to generate" }, ++}; ++ ++static exec_cmd_t commands[] = { ++ { "stat", "retrieve and print statistics data from driver", NULL, 0, do_stat }, ++ { "bypass", "perform bypass test", NULL, 0, do_bypass }, ++ { "read", "read data from bar0", read_args, 1, do_read }, ++ { "write", "write data to bar0", write_args, 2, do_write }, ++ { "geni", "generate interrupt on device", geni_args, 1, do_geni }, ++ { "dmar", "read data from dma buffer to a file", dma_r_args, 3, do_dma_r }, ++ { "dmaw", "write data from file to dma buffer", dma_w_args, 3, do_dma_w }, ++ { "info", "print this message", NULL, 0, do_help }, ++}; ++ ++int fd_dev = -1; ++int fd_events = -1; ++char *dma = NULL; ++unsigned long dma_len = (32*1024*1024); ++ ++int main (int argc, char *argv[]) ++{ ++ int ret = 0; ++ int proc_ext; ++ char proc_filename[128]; ++ int i; ++ ++ /* Register SIGIO Handler */ ++ signal(SIGIO, SIGIO_handler); ++ ++ fd_dev = open(FILENAME, O_RDWR); ++ if (fd_dev < 0) ++ { ++ LOG_E("%s-> error open device\n", __FUNCTION__); ++ ret = 1; ++ goto err_open_dev; ++ } ++ ++ if (ioctl(fd_dev, IOC_CEVADRV_GET_PID_PROCID, &proc_ext)) { ++ LOG_E("%s-> error get device name (pid)\n", __FUNCTION__); ++ goto err_open_events; ++ } ++ ++ sprintf(proc_filename, "/proc/ceva_linkdrv/%d/events", proc_ext); ++ fd_events = open(proc_filename, O_RDONLY); ++ if (fd_events < 0) ++ { ++ LOG_E("%s-> error open events\n", __FUNCTION__); ++ ret = 2; ++ goto err_open_events; ++ } ++ ++ dma = mmap(NULL, dma_len, PROT_READ | PROT_WRITE, MAP_SHARED, fd_dev, 0); ++ if (!dma) ++ { ++ LOG_E("%s-> error mapping dma\n", __FUNCTION__); ++ ret = 3; ++ goto err_map; ++ } ++ ++ argc--; ++ argv = &argv[1]; ++ ++ if (!argc) ++ { ++ goto print_info; ++ } ++ ++ for (i = 0; i < sizeof(commands)/sizeof(exec_cmd_t); i++) ++ { ++ if (!strcmp(commands[i].name, argv[0])) ++ { ++ if (argc < commands[i].argc) ++ { ++ LOG_E("wrong number of arguments, expected %d, see 'info'", commands[i].argc); ++ goto exit; ++ } ++ if (!commands[i].exec_func) ++ { ++ LOG_E("not supported, see 'info'"); ++ goto exit; ++ } ++ argc--; ++ argv = &argv[1]; ++ ret = commands[i].exec_func(argc, argv); ++ break; ++ } ++ } ++ if (i != sizeof(commands)/sizeof(exec_cmd_t)) ++ { ++ goto exit; ++ } ++ ++print_info: ++ ret = do_help(0, NULL); ++ ++exit: ++ munmap(dma, dma_len); ++err_map: ++ if (fd_events != -1) ++ close(fd_events); ++err_open_events: ++ if (fd_dev != -1) ++ close(fd_dev); ++err_open_dev: ++ return ret; ++} ++ ++static int do_stat(int argc, char *argv[]) ++{ ++ union ceva_linkdrv_debug_info debug; ++ ++ if (ioctl(fd_dev, IOC_CEVADRV_READ_DEBUG, &debug) != 0) ++ { ++ LOG_E("%s-> error debug ioctl", __FUNCTION__); ++ return -1; ++ } ++ LOG("debug info retrieved:\n" ++ " bypass_interrupts_success = %lu\n" ++ " bypass_interrupts_failed = %lu\n" ++ " events_recieved = %lu\n" ++ " fifo_full = %lu\n" ++ " generated_interrupts = %lu\n" ++ " generate_interrupt_failures = %lu\n", ++ debug.data.bypass_interrupts_success, ++ debug.data.bypass_interrupts_failed, ++ debug.data.events_recieved, ++ debug.data.fifo_full, ++ debug.data.generated_interrupts, ++ debug.data.generate_interrupt_failures); ++ return 0; ++} ++ ++static void* test_bypass_event_thread(void* fd_dev) { ++ int n, ret; ++ ++ for (n = 0; n < 3; n++) { ++ usleep(1500*1000); ++ ret = ioctl((int) fd_dev, IOC_CEVADRV_BYPASS_REQ, 0); ++ if (ret != 0) ++ { ++ LOG_E("%s-> error ioctl\n", __FUNCTION__); ++ return (void*) -EPIPE; ++ } ++ LOG("%s-> bypass command sent\n", __FUNCTION__); ++ usleep(1500*1000); ++ } ++ return 0; ++} ++ ++static void* test_bypass_read_thread(void* fd_events) { ++ int read_bytes; ++ unsigned long buf[10]; ++ ++ while(1) { ++ read_bytes = read((int) fd_events, buf, sizeof(buf)); ++ LOG("%d bytes read, %d events, data: %lx\n", read_bytes, read_bytes / 4, buf[0]); ++ if (read_bytes < 0) ++ { ++ LOG_E("%s-> invalid bytes read from procfs entry\n", __FUNCTION__); ++ break; ++ } ++ } ++ return 0; ++} ++ ++static int do_bypass(int argc, char *argv[]) ++{ ++ pthread_t thread1, thread2; ++ pthread_attr_t attr1, attr2; ++ ++ pthread_attr_init(&attr1); ++ pthread_attr_init(&attr2); ++ pthread_create(&thread1, &attr1, test_bypass_event_thread, (void*) fd_dev); ++ pthread_create(&thread2, &attr2, test_bypass_read_thread, (void*) fd_events); ++ ++ pthread_join(thread1, NULL); ++ ++ close(fd_dev); ++ fd_dev = -1; ++ pthread_join(thread2, NULL); ++ return 0; ++} ++ ++static int do_write(int argc, char *argv[]) ++{ ++ struct RWBuffer rwbuf; ++ unsigned long offset, data; ++ ++ sscanf(argv[0], "%lx", &offset); ++ sscanf(argv[1], "%lx", &data); ++ ++ rwbuf.offset = offset; ++ rwbuf.buf = &data; ++ ++ LOG("writing to bar0, offset: 0x%0lx, data: 0x%0lx", offset, data); ++ if (write(fd_dev, &rwbuf, sizeof(unsigned long)) != sizeof(unsigned long)) ++ { ++ LOG_E("write execution failed"); ++ return -1; ++ } ++ LOG("success!"); ++ return 0; ++} ++ ++static int do_read(int argc, char *argv[]) ++{ ++ struct RWBuffer rwbuf; ++ unsigned long offset, data; ++ ++ sscanf(argv[0], "%lx", &offset); ++ ++ rwbuf.offset = offset; ++ rwbuf.buf = &data; ++ ++ LOG("reading from bar0, offset: 0x%0lx", offset); ++ if (read(fd_dev, &rwbuf, sizeof(unsigned long)) != sizeof(unsigned long)) ++ { ++ LOG_E("read execution failed"); ++ return -1; ++ } ++ LOG("success!, data: 0x%0lx", data); ++ return 0; ++} ++ ++static int do_geni(int argc, char *argv[]) ++{ ++ unsigned long int_val; ++ ++ sscanf(argv[0], "%lx", &int_val); ++ ++ if (ioctl(fd_dev, IOC_CEVADRV_GENERATE_INT, int_val) != 0) ++ { ++ LOG_E("error ioctl IOC_CEVADRV_GENERATE_INT"); ++ return -1; ++ } ++ LOG("success!"); ++ return 0; ++} ++ ++static int do_dma_r(int argc, char *argv[]) ++{ ++ FILE *fd; ++ char filename[128]; ++ unsigned long offset, size; ++ int ret; ++ ++ sscanf(argv[0], "%lx", &offset); ++ sscanf(argv[1], "%lx", &size); ++ sscanf(argv[2], "%s", filename); ++ ++ fd = fopen(filename, "wb"); ++ if (!fd) { ++ LOG_E("unable to open file"); ++ return -1; ++ } ++ ++ ret = fwrite(dma + offset, 1, size, fd); ++ if (ret != size) ++ { ++ LOG_E("fwrite failed, bytes written: %d", ret); ++ return -2; ++ } ++ LOG("success!"); ++ ++ return 0; ++} ++ ++static int do_dma_w(int argc, char *argv[]) ++{ ++ FILE *fd; ++ char filename[128]; ++ unsigned long offset, size; ++ int ret; ++ ++ sscanf(argv[0], "%lx", &offset); ++ sscanf(argv[1], "%lx", &size); ++ sscanf(argv[2], "%s", filename); ++ ++ fd = fopen(filename, "rb"); ++ if (!fd) { ++ LOG_E("unable to open file"); ++ return -1; ++ } ++ ++ ret = fread(dma + offset, 1, size, fd); ++ if (ret != size) ++ { ++ LOG_E("fread failed, read bytes: %d", ret); ++ return -2; ++ } ++ LOG("success!"); ++ ++ return 0; ++} ++ ++static int do_help(int argc, char *argv[]) ++{ ++ int i; ++ ++ LOG("command\t\tdescription"); ++ LOG("--------------------------------------------------------------------------------"); ++ for (i = 0; i < sizeof(commands)/sizeof(exec_cmd_t); i++) ++ { ++ int j; ++ LOG(" %s\t\t%s", commands[i].name, commands[i].description); ++ if (commands[i].argc) ++ { ++// LOG(" arguments:"); ++ } ++ for (j = 0; j < commands[i].argc; j++) ++ { ++ LOG(" %s\t%s", ++ commands[i].argv[j].name, ++ commands[i].argv[j].description); ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/ceva_link/protected_mem_db.c b/drivers/sstar/ceva_link/protected_mem_db.c +new file mode 100644 +index 000000000000..b61bdc41ac1c +--- /dev/null ++++ b/drivers/sstar/ceva_link/protected_mem_db.c +@@ -0,0 +1,372 @@ ++/* ++ * protected_mem_db.c ++ * ++ * Simple miscellaneous shared memory driver ++ * The driver implements a shared memory for Ceva DB structure ++ * ++ * Linux kernel module ++ * simple single misc device file (miscdevice, misc_register) ++ * file_operations: ++ * read/write ++ * ioctl: lock and unlock ++ * Created on: Sep 12, 2013 ++ * Author: Tal Halpern ++ * Modified: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ceva_linkdrv-generic.h" ++#include "ceva_linkdrv_shared_process_protected_db_def_copy.h" ++#include "protected_mem_db.h" ++ ++#include "drv_debug.h" ++ ++/*! ++ * struct protected_mem_db_data - the driver data ++ * @dev_mutex: a mutex that protects the shared memory access ++ * @lock_pid: an atomic variable to hold the last pid of the ++ * thread which called the PROTECTED_MEM_DB_LOCK ioctl. ++ * ++ */ ++struct protected_mem_db_data { ++ struct mutex dev_mutex; ++ atomic_t lock_pid; ++}; ++ ++static int protected_mem_db_open(struct inode *inode, struct file *file); ++static int protected_mem_db_release(struct inode *inode, struct file *file); ++static ssize_t protected_mem_db_read(struct file *file, char __user *buf, ++ size_t count, loff_t *ppos); ++static ssize_t protected_mem_db_write(struct file *file, ++ const char __user *buf, size_t count, loff_t *ppos); ++static long protected_mem_db_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg); ++static struct protected_mem_db_data *protected_mem_db_data_init(void); ++ ++/* driver data object */ ++static struct protected_mem_db_data *drvdata; ++ ++/* the shared memory array statically allocated*/ ++static char shmp[sizeof(ceva_linkdrv_shared_process_protected_db)]; ++ ++static const struct file_operations protected_mem_db_fops = { ++ .owner = THIS_MODULE, ++ .open = protected_mem_db_open, ++ .release = protected_mem_db_release, ++ .read = protected_mem_db_read, ++ .write = protected_mem_db_write, ++ .unlocked_ioctl = protected_mem_db_ioctl, ++}; ++ ++static struct miscdevice protected_mem_db_dev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = CEVA_PROT_MEM_DRV_NAME, ++ .fops = &protected_mem_db_fops, ++}; ++ ++/*! ++ * open function ++ * @param [in] inode not used by this module ++ * @param [in] file not used by this module ++ * @return always zero ++ */ ++static int protected_mem_db_open(struct inode *inode, struct file *file) ++{ ++ /* client related data can be allocated here and ++ stored in file->private_data */ ++ file->private_data = drvdata; ++ ++ XM6_MSG(XM6_MSG_DBG, "%s :: device opened by process %d\n", ++ __FUNCTION__, task_tgid_vnr(current)); ++ ++ return 0; ++} ++ ++/*! ++ * release function ++ * ++ * released the shared memory in case closing task is still locking it ++ * could be due to software bug, abnormal application exit (SEG signal), etc ++ * @param [in] inode not used by this module ++ * @param [in] file not used by this module ++ * @return always zero ++ */ ++static int protected_mem_db_release(struct inode *inode, struct file *file) ++{ ++ /* client related data can be retrieved from file->private_data ++ and released here */ ++ ++ if (atomic_read(&(drvdata->lock_pid)) == task_tgid_vnr(current)) { ++ atomic_set(&(drvdata->lock_pid), -1); ++ mutex_unlock(&drvdata->dev_mutex); ++ } ++ ++ /* ++ * place additional code here for closing a device ++ */ ++ XM6_MSG(XM6_MSG_DBG, "%s :: device closed by process %d\n", ++ __FUNCTION__, task_tgid_vnr(current)); ++ return 0; ++} ++ ++/*! ++ * read handler ++ * ++ * reads data from the shared memory with a relative offset. ++ * as the user interface does not include an offset argument, the user ++ * has to write the offset value into the buf. the driver first read from ++ * buf the offset value and user actual buffer address, and then reads ++ * the data into the forwarded user supplied address. ++ * @param [in] file not used by this module ++ * @param [in/out] buf output buffer to read data to ++ * @param [in] count number of bytes to read ++ * @param [in] ppos not used by this module ++ * @return number of bytes read from shared memory, negative values for errors ++ * @see struct RWBuffer, protected_mem_db_write() ++ */ ++static ssize_t protected_mem_db_read(struct file *file, char __user *buf, ++ size_t count, loff_t *ppos) { ++ struct RWBuffer to; ++ struct protected_mem_db_data * dev; ++ pid_t pid; ++ ++ if (!count) { ++ return 0; ++ } ++ if (!access_ok(VERIFY_WRITE, buf, count)) { ++ return -EFAULT; ++ } ++ ++ dev = (struct protected_mem_db_data *) file->private_data; ++ pid = task_tgid_vnr(current); ++ ++ if (atomic_read(&(drvdata->lock_pid)) != pid) { ++ if (mutex_lock_interruptible(&dev->dev_mutex)) { ++ return -EINTR; ++ } ++ } ++ if (copy_from_user(&to, buf, sizeof(to)) != 0) { ++ return -EFAULT; ++ } ++ if (to.offset + count > sizeof(ceva_linkdrv_shared_process_protected_db)) { ++ return -EINVAL; ++ } ++ if (copy_to_user(to.buf, shmp + to.offset, count) != 0) { ++ return -EFAULT; ++ } ++ *ppos += count; ++ if (atomic_read(&(drvdata->lock_pid)) != pid) { ++ mutex_unlock(&dev->dev_mutex); ++ } ++ ++ return count; ++} ++ ++/*! ++ * write handler ++ * ++ * writes data from user to a relative offset within the shared memory. ++ * as the user interface does not include an offset argument, the user ++ * has to write the offset value into the buf. the driver first read from ++ * buf the offset value and user actual buffer address, and then reads ++ * the data into the forwarded user supplied address. ++ * @param [in] file not used by this module ++ * @param [in] buf output buffer to read data to ++ * @param [in] count number of bytes to write ++ * @param [in] ppos not used by this module ++ * @return number of bytes written to shared memory, negative values for errors ++ * @see struct RWBuffer, protected_mem_db_read() ++ */ ++static ssize_t protected_mem_db_write(struct file *file, ++ const char __user *buf, size_t count, loff_t *ppos) ++{ ++ struct RWBuffer from; ++ struct protected_mem_db_data * dev; ++ pid_t pid; ++ ++ if (!count) { ++ return 0; ++ } ++ if (!access_ok(VERIFY_READ, buf, count)) { ++ return -EFAULT; ++ } ++ ++ dev = (struct protected_mem_db_data *) file->private_data; ++ pid = task_tgid_vnr(current); ++ ++ if (atomic_read(&(drvdata->lock_pid)) != pid) { ++ if (mutex_lock_interruptible(&dev->dev_mutex)) { ++ return -EINTR; ++ } ++ } ++ /* copy the offset to local */ ++ if (copy_from_user(&from, buf, sizeof(from)) != 0) { ++ return -EFAULT; ++ } ++ if (from.offset + count > sizeof(ceva_linkdrv_shared_process_protected_db)) { ++ return -EINVAL; ++ } ++ if (copy_from_user(shmp + from.offset, from.buf, count) != 0) { ++ return -EFAULT; ++ } ++ *ppos += count; ++ if (atomic_read(&(drvdata->lock_pid)) != pid) { ++ mutex_unlock(&dev->dev_mutex); ++ } ++ return count; ++} ++ ++/*! ++ * ioctl handler ++ * ++ * special commands executer. ++ * this module allows single lock/unlock of the shared memory region ++ * @param [in] filp device handler ++ * @param [in] cmd command to execute (lock/unlock) ++ * @param [in] arg currently not used by this module ++ * @return zero for success, nonzero for failures ++ */ ++long protected_mem_db_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ struct protected_mem_db_data *dev; ++ pid_t pid; ++ int ret = 0; ++ ++ /* ++ * don't even decode wrong cmds: better returning EINVAL than EFAULT ++ */ ++ if (_IOC_TYPE(cmd) != IOC_CEVADRV_MAGIC || ++ _IOC_NR(cmd) > IOC_CEVADRV_MAXNR) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ dev = (struct protected_mem_db_data *) file->private_data; ++ pid = task_tgid_vnr(current); ++ ++ switch (cmd) { ++ case IOC_CEVADRV_PROTMEM_LOCK: ++ XM6_MSG(XM6_MSG_DBG, "IOC_CEVADRV_PROTMEM_LOCK ioctl\n"); ++ if (mutex_lock_interruptible(&dev->dev_mutex)) { ++ XM6_MSG(XM6_MSG_ERR, "%s :: unable to lock mutex\n", __FUNCTION__); ++ ret = -EINTR; ++ goto exit; ++ } ++ atomic_set(&(drvdata->lock_pid), pid); ++ XM6_MSG(XM6_MSG_DBG, "device locked by process %d\n", pid); ++ break; ++ ++ case IOC_CEVADRV_PROTMEM_UNLOCK: ++ XM6_MSG(XM6_MSG_DBG, "IOC_CEVADRV_PROTMEM_UNLOCK ioctl\n"); ++ if (atomic_read(&(drvdata->lock_pid)) != pid) { ++ XM6_MSG(XM6_MSG_ERR, "process %d did not locked the device\n", pid); ++ ret = -EPERM; ++ goto exit; ++ } ++ atomic_set(&(drvdata->lock_pid), -1); ++ mutex_unlock(&dev->dev_mutex); ++ XM6_MSG(XM6_MSG_DBG, "device unlocked\n"); ++ break; ++ ++ default: ++ ret = -EINVAL; ++ } ++exit: ++ return ret; ++} ++ ++/* ++ * Initialization and cleanup section ++ */ ++ ++/*! ++ * deinit function ++ * ++ * releases any allocated memory done by this module ++ */ ++void protected_mem_db_deinit(void) ++{ ++ if (protected_mem_db_dev.this_device) { ++ misc_deregister(&protected_mem_db_dev); ++ } ++ mutex_destroy(&drvdata->dev_mutex); ++ kfree(drvdata); ++} ++ ++/*! ++ * helper function for init ++ * @return valid object address for success, NULL for failures ++ */ ++static struct protected_mem_db_data *protected_mem_db_data_init(void) ++{ ++ struct protected_mem_db_data *drv; ++ ++ drv = kzalloc(sizeof(struct protected_mem_db_data), GFP_KERNEL); ++ if (!drv) { ++ return NULL; ++ } ++ ++ mutex_init(&drv->dev_mutex); ++ atomic_set(&drv->lock_pid, -1); ++ /* initialize the shared memory*/ ++ memset(shmp, 0, sizeof(ceva_linkdrv_shared_process_protected_db)); ++ ++ return drv; ++} ++ ++/*! ++ * init function ++ * ++ * initializes the module ++ * @return zero for success, nonzero for failures ++ */ ++int protected_mem_db_init(void) ++{ ++ int ret = 0; ++ ++ drvdata = protected_mem_db_data_init(); ++ if (!drvdata) { ++ XM6_MSG(XM6_MSG_ERR, "protected_mem_db_data_init failed\n"); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ ret = misc_register(&protected_mem_db_dev); ++ if (ret < 0) { ++ XM6_MSG(XM6_MSG_ERR, "misc_register failed\n"); ++ goto exit; ++ } ++ ++ return 0; ++ ++exit: ++ protected_mem_db_deinit(); ++ return ret; ++} ++ ++MODULE_DESCRIPTION("protected_mem_db Simple misc device driver"); ++MODULE_AUTHOR("Tal Halpern"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/ceva_link/protected_mem_db.h b/drivers/sstar/ceva_link/protected_mem_db.h +new file mode 100644 +index 000000000000..001eaecceb81 +--- /dev/null ++++ b/drivers/sstar/ceva_link/protected_mem_db.h +@@ -0,0 +1,28 @@ ++/* ++ * protected_mem_db.h ++ * ++ * Created on: Nov 28, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#ifndef PROTECTED_MEM_DB_H_ ++#define PROTECTED_MEM_DB_H_ ++ ++extern int protected_mem_db_init(void); ++extern void protected_mem_db_deinit(void); ++ ++#endif /* PROTECTED_MEM_DB_H_ */ +diff --git a/drivers/sstar/clk/Kconfig b/drivers/sstar/clk/Kconfig +new file mode 100755 +index 000000000000..92e78adfae07 +--- /dev/null ++++ b/drivers/sstar/clk/Kconfig +@@ -0,0 +1,2 @@ ++config MS_USCLK ++ tristate "MS_USCLK extended sysfs interfaces for CLKs" +\ No newline at end of file +diff --git a/drivers/sstar/clk/Makefile b/drivers/sstar/clk/Makefile +new file mode 100755 +index 000000000000..4c9b494326fe +--- /dev/null ++++ b/drivers/sstar/clk/Makefile +@@ -0,0 +1,7 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += ms_composite_clk.o ++obj-$(CONFIG_MS_USCLK)=ms_usclk.o ++obj-y += $(CONFIG_SSTAR_CHIP_NAME)/ +diff --git a/drivers/sstar/clk/cedric/Makefile b/drivers/sstar/clk/cedric/Makefile +new file mode 100755 +index 000000000000..b7129b37d454 +--- /dev/null ++++ b/drivers/sstar/clk/cedric/Makefile +@@ -0,0 +1,5 @@ ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += clk.o +diff --git a/drivers/sstar/clk/cedric/clk.c b/drivers/sstar/clk/cedric/clk.c +new file mode 100755 +index 000000000000..341f352d2f87 +--- /dev/null ++++ b/drivers/sstar/clk/cedric/clk.c +@@ -0,0 +1,198 @@ ++/* ++* clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * ms_clk-cedric.c ++ * ++ * Created on: 2015�~5��4�� ++ * Author: Administrator ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cedric/irqs.h" ++#include "ms_platform.h" ++ ++ ++ ++#define PERI_PHYS 0x16000000 ++ ++ ++ ++static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) ++{ ++ ++ return (parent_rate>>1)*ms_readl(0x1F22184C); ++} ++ ++static const struct clk_ops clk_cpu_ops = { ++ .recalc_rate = clk_cpu_recalc_rate, ++// .round_rate = clk_cpu_round_rate, ++// .set_rate = clk_cpu_set_rate, ++}; ++ ++ ++ ++ ++#if defined(CONFIG_HAVE_ARM_TWD) ++#include ++DEFINE_TWD_LOCAL_TIMER(twd_local_timer, (PERI_PHYS+0x0600), GIC_ID_LOCAL_TIMER_IRQ); ++#endif ++ ++ ++static struct clk_onecell_data clk_cpu_data; ++static struct clk_hw clk_cpu_hw; ++static void __init ms_clk_cpu_of_init(struct device_node *node) ++{ ++ ++ struct clk_init_data init; ++ const char *parent_name; ++ ++ clk_cpu_data.clk_num=2; ++ clk_cpu_data.clks = kzalloc(clk_cpu_data.clk_num*sizeof(struct clk *),GFP_KERNEL); ++ BUG_ON(!clk_cpu_data.clks); ++ ++ parent_name = of_clk_get_parent_name(node, 0); ++ ++ clk_cpu_hw.init = &init; ++ init.ops = &clk_cpu_ops; ++ init.name=node->name; ++ init.parent_names = parent_name ? &parent_name : NULL; ++ init.num_parents = parent_name ? 1 : 0; ++ init.flags = (parent_name)? 0 : CLK_IS_ROOT; ++ ++ ++ clk_cpu_data.clks[0]=clk_register(NULL, &clk_cpu_hw);; ++ BUG_ON(IS_ERR(clk_cpu_data.clks[0])); ++ ++ ++ clk_cpu_data.clks[1]=clk_register_fixed_factor(NULL, "periclk", node->name, 0, 1, 2); ++ BUG_ON(IS_ERR(clk_cpu_data.clks[1])); ++ ++ ++ of_clk_add_provider(node, of_clk_src_onecell_get, &clk_cpu_data); ++ ++ ++// since we are not using GIC, need to register TWD manually ++#if defined(CONFIG_HAVE_ARM_TWD) ++ { ++ clk_register_clkdev(clk_cpu_data.clks[1], NULL, "smp_twd"); ++ ++ if (twd_local_timer_register(&twd_local_timer)) ++ { ++ pr_err("twd_local_timer_register failed!!!\n"); ++ } ++ else ++ { ++ pr_err("twd_local_timer_register success... \n"); ++ } ++ } ++ ++#endif ++} ++ ++static void __init ms_clk_uart_of_init(struct device_node *node) ++{ ++ struct clk *clk; ++ const char *clk_name = node->name; ++ int num_parents; ++ const char **parent_names; ++ struct clk_mux *mux = NULL; ++ struct clk_gate *gate = NULL; ++ void __iomem *reg; ++ unsigned int mux_width; ++ int i = 0; ++ ++ pr_info("%s: %s", __func__, clk_name); ++ ++ num_parents = of_clk_get_parent_count(node); ++ if (num_parents < 2) { ++ pr_err("%s: %s must have at least 2 parents\n", __func__, node->name); ++ return; ++ } ++ ++ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); ++ mux = kzalloc(sizeof(*mux), GFP_KERNEL); ++ gate = kzalloc(sizeof(*gate), GFP_KERNEL); ++ ++ if (!parent_names || !mux || !gate) ++ { ++ pr_err("%s: failed to allocate memory\n", __func__); ++ goto fail; ++ } ++ ++ for (i = 0; i < num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ reg = of_iomap(node, 0); ++ if (!reg) { ++ pr_err("%s: could not map region\n", __func__); ++ goto fail; ++ } ++ ++ mux->reg = reg; ++ if(of_property_read_u32(node, "mux-shift", (unsigned int *)&mux->shift)) ++ { ++ pr_err("%s: failed to read mux-shift\n", __func__); ++ mux->shift = 0; ++ } ++ if(of_property_read_u32(node, "mux-width", &mux_width)) ++ { ++ pr_err("%s: failed to read mux-width\n", __func__); ++ mux_width = 3; ++ } ++ mux->mask = BIT(mux_width) - 1; ++ //mux->flags = CLK_SET_RATE_PARENT; ++ ++ gate->reg = reg; ++ if(of_property_read_u32(node, "gate-shift", (unsigned int *)&gate->bit_idx)) ++ { ++ pr_err("%s: failed to read gate-shift\n", __func__); ++ gate->bit_idx = 0; ++ } ++ ++ pr_debug("%s: mux->reg=0x%08X\nmux->shift=%d\nmux->mask=0x%08X\n", __func__, (unsigned int)mux->reg, mux->shift, mux->mask); ++ ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ &mux->hw, &clk_mux_ops, ++ NULL, NULL, ++ &gate->hw, &clk_gate_ops, ++ 0); ++ ++ if (IS_ERR(clk)) ++ { ++ pr_err("%s: failed to register clock %s\n", __func__, clk_name); ++ goto fail; ++ } ++ ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, clk_name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(mux); ++ kfree(gate); ++ return; ++} ++ ++CLK_OF_DECLARE(cedric_uart_clk, "sstar,cedric-uartclk", ms_clk_uart_of_init); ++CLK_OF_DECLARE(cedric_cpu_clk, "sstar,cedric-cpuclk",ms_clk_cpu_of_init); +diff --git a/drivers/sstar/clk/infinity/Makefile b/drivers/sstar/clk/infinity/Makefile +new file mode 100755 +index 000000000000..5cf91d093653 +--- /dev/null ++++ b/drivers/sstar/clk/infinity/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity/ms_complex_clk.c b/drivers/sstar/clk/infinity/ms_complex_clk.c +new file mode 100755 +index 000000000000..b397e28aa7a4 +--- /dev/null ++++ b/drivers/sstar/clk/infinity/ms_complex_clk.c +@@ -0,0 +1,484 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity/registers.h" ++ ++#if defined (CONFIG_MS_CPU_FREQ) && defined (CONFIG_MS_GPIO) ++extern u8 enable_scaling_voltage; ++#include "infinity/gpio.h" ++#include "mdrv_gpio.h" ++int bga_vid_0 = PAD_PM_GPIO7; ++int bga_vid_1 = PAD_PM_GPIO8; ++int qfp_vid_0 = PAD_SAR_GPIO3; ++/* */ ++/* for CUSTOMER */ ++/* _ _ _ _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | BGA(MHz)| VID_1 | VID_0 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 400-500 | 0 | 0 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 500-700 | 0 | 1 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 700-800 | 1 | 0 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 800-1000| 1 | 1 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++#else ++u8 enable_scaling_voltage=0; ++#define MDrv_GPIO_Set_High(x) {} ++#define MDrv_GPIO_Set_Low(x) {} ++#define MDrv_GPIO_Pad_Set(x) {} ++int bga_vid_0 = -1; ++int bga_vid_1 = -1; ++int qfp_vid_0 = -1; ++#endif ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++static unsigned int ms_get_ddr_scl(void) ++{ ++ CLK_DBG("ms_get_ddr_scl = (0x%04X,0x%04X)\n", INREG16(0x1F206580), INREG16(0x1F206584)); ++ return (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate <= 500000000) //request 400M-500M=400M ++ return 400000000; ++ else if(rate <= 700000000) //request 500M-700M=600M ++ return 600000000; ++ else if(rate <= 800000000) //request 700M-800M=800M ++ return 800000000; ++ else //request 800M-1000M=1000M ++ return 1000000000; ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) * 12 * 524288; ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu\n", rate); ++ ++ return rate; ++} ++ ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ MS_PACKAGE_TYPE package = Chip_Get_Package_Type(); ++ ++// if(abs(rate - __clk_get_rate(clk_hw->clk)) < 100000000) //if it's the same setting, just return to save time ++// return 0; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ if(rate == 400000000) ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_Low(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_Low(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_Low(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0xAE14); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0067); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0xAE14); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0067); ++ } ++ else if(rate == 600000000) ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_High(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_Low(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_Low(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0x1EB8); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0045); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0x1EB8); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0045); ++ ++ } ++ else if(rate == 800000000) ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_Low(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_High(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_High(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0xD70A); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0033); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0xD70A); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0033); ++ ++ } ++ else ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_High(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_High(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_High(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0x78D4); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0029); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0x78D4); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0029); ++ ++ } ++ ++ return ret; ++} ++ ++void ms_cpuclk_dvfs_disable(void) ++{ ++ MS_PACKAGE_TYPE package = Chip_Get_Package_Type(); ++ ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_Low(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_Low(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_Low(qfp_vid_0); ++ } ++ } ++} ++EXPORT_SYMBOL(ms_cpuclk_dvfs_disable); ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++}; ++ ++static int ms_upll_utmi_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_enable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x00C0); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x01); ++ ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=0 ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=0 ++ return 0; ++} ++ ++static void ms_upll_utmi_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_disable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x01B2); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x02); ++ ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=1 ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=1 ++} ++ ++static int ms_upll_utmi_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UPLL0_PA + REG_ID_07) & BIT0); ++} ++ ++static unsigned long ms_upll_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ CLK_DBG("\nms_upll_utmi_recalc_rate, parent_rate=%d\n\n", parent_rate); ++ return (parent_rate * 40); ++} ++ ++ ++struct clk_ops ms_upll_utmi_ops = { ++ .enable = ms_upll_utmi_enable, ++ .disable = ms_upll_utmi_disable, ++ .is_enabled = ms_upll_utmi_is_enabled, ++ .recalc_rate = ms_upll_utmi_recalc_rate, ++}; ++ ++static int ms_usb_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_enable\n\n"); ++ ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0C2F); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x040F); //utmi0 ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x7F05); ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x0A); //Disable MAC initial suspend, Reset UHC ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x28); //Release UHC reset, enable UHC and OTG XIU function ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_11, 0x2088); //PLL_TEST[30:28]: 3'b101 for IBIAS current select ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_10, 0x8051); //PLL_TEST[15]: Bypass 480MHz clock divider ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_01, 0x2084); //Enable CLK12_SEL bit <2> for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity2/Makefile b/drivers/sstar/clk/infinity2/Makefile +new file mode 100755 +index 000000000000..48eec4acb21e +--- /dev/null ++++ b/drivers/sstar/clk/infinity2/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity2/ms_complex_clk.c b/drivers/sstar/clk/infinity2/ms_complex_clk.c +new file mode 100755 +index 000000000000..9f3902a9e576 +--- /dev/null ++++ b/drivers/sstar/clk/infinity2/ms_complex_clk.c +@@ -0,0 +1,540 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity2/registers.h" ++ ++#include "vcore_dvfs.h" ++ ++#if defined (CONFIG_MS_CPU_FREQ) && defined (CONFIG_MS_GPIO) ++extern u8 enable_scaling_voltage; ++#include "infinity2/gpio.h" ++#include "../../gpio/mdrv_gpio.h" ++int vid_0 = -1; ++int vid_1 = -1; ++#else ++u8 enable_scaling_voltage=0; ++#define MDrv_GPIO_Set_High(x) {} ++#define MDrv_GPIO_Set_Low(x) {} ++#define MDrv_GPIO_Pad_Set(x) {} ++int vid_0 = -1; ++int vid_1 = -1; ++#endif ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++extern int vcore_dvfs_register(vcore_dvfs_demander_e demander, struct vcore_dvfs_init_data *init_data); ++//extern int vcore_dvfs_unregister(vcore_dvfs_demander_e demander); ++//extern int vcore_dvfs_clk_enable(vcore_dvfs_demander_e demander, clk_enable_hw clk_enable_hw); ++//extern int vcore_dvfs_clk_set_rate(vcore_dvfs_demander_e demander, unsigned long rate, set_rate_hw set_rate_hw); ++//extern int vcore_dvfs_clk_disable(vcore_dvfs_demander_e demander, clk_disable_hw clk_disable_hw); ++ ++static unsigned int ms_get_ddr_scl(void) ++{ ++ unsigned int factor = INREG16(BASE_REG_RIU_PA + (0x1032A0 << 1)) | (((INREG16(BASE_REG_RIU_PA + (0x1032A2 << 1)) & 0xFF) <<16)); ++ ++ if(!factor) ++ factor = (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++ ++ CLK_DBG("ms_get_ddr_scl = 0x%X\n", factor); ++ return factor; ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate <= 450000000) //request 400M-450M=400M ++ { ++ return 400000000; ++ } ++ else if(rate <= 650000000) //request 450M-650M=600M ++ { ++ return 600000000; ++ } ++ else if(rate <= 850000000) //request 650M-850M=800M ++ { ++ return 800000000; ++ } ++ else //request 850M-1000M=1000M ++ { ++ return 1000000000; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) << 23; ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetSet) ++{ ++/*TBD*/ ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetSet&0xFFFF); //set target freq to LPF high ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetSet>>16)&0xFFFF); ++// OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++// OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++// OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++// SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++// while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetSet&0xFFFF); //store freq to LPF low ++// OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetSet>>16)&0xFFFF); ++} ++ ++ ++ ++#define VOLTAGE_CORE_850 850 ++#define VOLTAGE_CORE_900 900 ++#define VOLTAGE_CORE_950 950 ++#define VOLTAGE_CORE_1000 1000 ++int g_sCurrentTemp = 35; ++int g_sCurrentTempThreshLo=35; ++int g_sCurrentTempThreshHi=50; ++int g_sCurrentVoltageCore=VOLTAGE_CORE_1000; ++void set_core_voltage (int vcore) ++{ ++#if 0 ++ if(enable_scaling_voltage) ++ { ++ switch (vcore) ++ { ++ case VOLTAGE_CORE_850: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_850; ++ break; ++ ++ case VOLTAGE_CORE_900: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_900; ++ break; ++ ++ case VOLTAGE_CORE_950: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_950; ++ break; ++ ++ case VOLTAGE_CORE_1000: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_1000; ++ break; ++ ++ } ++ } ++ ++ CLK_DBG("CurrentVoltageCore = %d\n", g_sCurrentVoltageCore); ++ #endif ++ printk("TBD set_core_voltage\n"); ++} ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++// if(abs(rate - __clk_get_rate(clk_hw->clk)) < 100000000) //if it's the same setting, just return to save time ++// return 0; ++ ++ CLK_DBG("TBD ms_cpuclk_set_rate = %lu\n", rate); ++#if 0 ++ if(rate == 1000000000) ++ { ++ set_core_voltage(VOLTAGE_CORE_1000); ++ cpu_dvfs(0x374BC7); ++ } ++ else ++ { ++ CLK_DBG("ms_get_temp = %d\n", g_sCurrentTemp); ++ #if 0 ++ if(g_sCurrentVoltageCore==VOLTAGE_CORE_1000 && g_sCurrentTemp>g_sCurrentTempThreshHi ) ++ set_core_voltage(VOLTAGE_CORE_900); ++ if(g_sCurrentVoltageCore==VOLTAGE_CORE_900 && g_sCurrentTemp= 600000000) ++ { ++ return 600000000; ++ } ++ ++ return 500000000; ++} ++ ++static unsigned long ms_ceva_pll_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = ceva_pll_recalc_rate(); ++ ++ CLK_DBG("%s rate=%lu, prate=%lu\n", __FUNCTION__, rate, parent_rate); ++ ++ return rate; ++} ++ ++static int ms_ceva_pll_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++ printk("TBD_EDIE: sms_ceva_pll_set_rate = %lu\n", rate); ++ ++// vcore_dvfs_clk_set_rate(VCORE_DVFS_DEMANDER_CEVA_PLL, rate, ceva_pll_set_rate); ++ ++ return ret; ++} ++ ++struct clk_ops ms_ceva_pll_ops = { ++ .round_rate = ms_ceva_pll_round_rate, ++ .recalc_rate = ms_ceva_pll_recalc_rate, ++ .set_rate = ms_ceva_pll_set_rate, ++}; ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ struct vcore_dvfs_init_data init_data; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else if(!strcmp(node->name, "CLK_cevapll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_ceva_pll_ops\n", node->name); ++ init->ops = &ms_ceva_pll_ops; ++ ++ // Vcore DVFS ++ init_data.rate = ceva_pll_recalc_rate(); ++ init_data.active = true; ++ vcore_dvfs_register(VCORE_DVFS_DEMANDER_CEVA_PLL, &init_data); ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s must have at least one parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register successfully\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity2m/Makefile b/drivers/sstar/clk/infinity2m/Makefile +new file mode 100644 +index 000000000000..48eec4acb21e +--- /dev/null ++++ b/drivers/sstar/clk/infinity2m/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity2m/ms_complex_clk.c b/drivers/sstar/clk/infinity2m/ms_complex_clk.c +new file mode 100755 +index 000000000000..c9cda49fbc27 +--- /dev/null ++++ b/drivers/sstar/clk/infinity2m/ms_complex_clk.c +@@ -0,0 +1,245 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++ ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_DEBUG fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate < 200000000) ++ { ++ return 200000000; ++ } ++ else if(rate > 1400000000) ++ { ++ return 1400000000; ++ } ++ else ++ { ++ return rate; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ U32 lpf_value; ++ U32 post_div; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ CLK_DBG("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ rate = (div64_u64(432000000llu * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return ret; ++} ++ ++void ms_cpuclk_init(struct clk_hw *clk_hw) ++{ ++ return; ++} ++ ++ ++void ms_cpuclk_dvfs_disable(void) ++{ ++ return; ++} ++EXPORT_SYMBOL(ms_cpuclk_dvfs_disable); ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++ .init = ms_cpuclk_init, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity3/Makefile b/drivers/sstar/clk/infinity3/Makefile +new file mode 100755 +index 000000000000..5cf91d093653 +--- /dev/null ++++ b/drivers/sstar/clk/infinity3/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity3/ms_complex_clk.c b/drivers/sstar/clk/infinity3/ms_complex_clk.c +new file mode 100755 +index 000000000000..255dfea2cd5c +--- /dev/null ++++ b/drivers/sstar/clk/infinity3/ms_complex_clk.c +@@ -0,0 +1,442 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity3/registers.h" ++ ++#if defined (CONFIG_MS_CPU_FREQ) && defined (CONFIG_MS_GPIO) ++extern u8 enable_scaling_voltage; ++#include "infinity3/gpio.h" ++#include "mdrv_gpio.h" ++int vid_0 = -1; ++int vid_1 = -1; ++#else ++u8 enable_scaling_voltage=0; ++#define MDrv_GPIO_Set_High(x) {} ++#define MDrv_GPIO_Set_Low(x) {} ++#define MDrv_GPIO_Pad_Set(x) {} ++int vid_0 = -1; ++int vid_1 = -1; ++#endif ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++static unsigned int ms_get_ddr_scl(void) ++{ ++ unsigned int factor = INREG16(BASE_REG_RIU_PA + (0x1032A0 << 1)) | (((INREG16(BASE_REG_RIU_PA + (0x1032A2 << 1)) & 0xFF) <<16)); ++ ++ if(!factor) ++ factor = (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++ ++ CLK_DBG("ms_get_ddr_scl = 0x%X\n", factor); ++ return factor; ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate <= 450000000) //request 400M-450M=400M ++ { ++ return 400000000; ++ } ++ else if(rate <= 650000000) //request 450M-650M=600M ++ { ++ return 600000000; ++ } ++ else if(rate <= 850000000) //request 650M-850M=800M ++ { ++ return 800000000; ++ } ++ else //request 850M-1000M=1000M ++ { ++ return 1000000000; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) << 23; ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetSet) ++{ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetSet&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetSet>>16)&0xFFFF); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetSet&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetSet>>16)&0xFFFF); ++} ++ ++ ++ ++#define VOLTAGE_CORE_850 850 ++#define VOLTAGE_CORE_900 900 ++#define VOLTAGE_CORE_950 950 ++#define VOLTAGE_CORE_1000 1000 ++int g_sCurrentTemp = 35; ++int g_sCurrentTempThreshLo=35; ++int g_sCurrentTempThreshHi=50; ++int g_sCurrentVoltageCore=VOLTAGE_CORE_1000; ++void set_core_voltage (int vcore) ++{ ++ if(enable_scaling_voltage) ++ { ++ switch (vcore) ++ { ++ case VOLTAGE_CORE_850: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_850; ++ break; ++ ++ case VOLTAGE_CORE_900: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_900; ++ break; ++ ++ case VOLTAGE_CORE_950: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_950; ++ break; ++ ++ case VOLTAGE_CORE_1000: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_1000; ++ break; ++ ++ } ++ } ++ CLK_DBG("CurrentVoltageCore = %d\n", g_sCurrentVoltageCore); ++} ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++// if(abs(rate - __clk_get_rate(clk_hw->clk)) < 100000000) //if it's the same setting, just return to save time ++// return 0; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ if(rate == 1000000000) ++ { ++ set_core_voltage(VOLTAGE_CORE_1000); ++ cpu_dvfs(0x374BC7); ++ } ++ else ++ { ++ CLK_DBG("ms_get_temp = %d\n", g_sCurrentTemp); ++ #if 0 ++ if(g_sCurrentVoltageCore==VOLTAGE_CORE_1000 && g_sCurrentTemp>g_sCurrentTempThreshHi ) ++ set_core_voltage(VOLTAGE_CORE_900); ++ if(g_sCurrentVoltageCore==VOLTAGE_CORE_900 && g_sCurrentTemp for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity5/Makefile b/drivers/sstar/clk/infinity5/Makefile +new file mode 100644 +index 000000000000..5cf91d093653 +--- /dev/null ++++ b/drivers/sstar/clk/infinity5/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity5/ms_complex_clk.c b/drivers/sstar/clk/infinity5/ms_complex_clk.c +new file mode 100755 +index 000000000000..c68f3b1c351b +--- /dev/null ++++ b/drivers/sstar/clk/infinity5/ms_complex_clk.c +@@ -0,0 +1,545 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity5/registers.h" ++ ++#if defined (CONFIG_MS_CPU_FREQ) && defined (CONFIG_MS_GPIO) ++extern u8 enable_scaling_voltage; ++#include "infinity5/gpio.h" ++#include "mdrv_gpio.h" ++int vid_0 = -1; ++int vid_1 = -1; ++#else ++u8 enable_scaling_voltage=0; ++#define MDrv_GPIO_Set_High(x) {} ++#define MDrv_GPIO_Set_Low(x) {} ++#define MDrv_GPIO_Pad_Set(x) {} ++int vid_0 = -1; ++int vid_1 = -1; ++#endif ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_DEBUG fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#ifndef CONFIG_CAM_CLK ++static unsigned int ms_get_ddr_scl(void) ++{ ++ unsigned int factor = INREG16(BASE_REG_RIU_PA + (0x1032A0 << 1)) | (((INREG16(BASE_REG_RIU_PA + (0x1032A2 << 1)) & 0xFF) <<16)); ++ ++ if(!factor) ++ factor = (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++ ++ //CLK_DBG("ms_get_ddr_scl = 0x%X\n", factor); ++ return factor; ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate <= 250000000) //request 200M-250M=200M ++ { ++ return 200000000; ++ } ++ else if(rate <= 450000000) //request 400M-450M=400M ++ { ++ return 400000000; ++ } ++ else if(rate <= 650000000) //request 450M-650M=600M ++ { ++ return 600000000; ++ } ++ else if(rate <= 850000000) //request 650M-850M=800M ++ { ++ return 800000000; ++ } ++ else if(rate <= 1000000000) //request 800M-1000M=1000M ++ { ++ return 1000000000; ++ } ++ else if(rate <= 1100000000) //request 1000M-1100M=1100M ++ { ++ return 1100000000; ++ } ++ else //request 1100M-1200M=1200M ++ { ++ return 1200000000; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) << 23; ++ ++ //CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103230 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103230 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while(!(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0)); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103230 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++#endif ++ ++ ++#define VOLTAGE_CORE_850 850 ++#define VOLTAGE_CORE_900 900 ++#define VOLTAGE_CORE_950 950 ++#define VOLTAGE_CORE_1000 1000 ++int g_sCurrentTemp = 35; ++int g_sCurrentTempThreshLo=40; // T < 40C : VDD = 1.0V ++int g_sCurrentTempThreshHi=60; // T > 60C : VDD= 0.9V ++int g_sCurrentVoltageCore=VOLTAGE_CORE_1000; ++void set_core_voltage(int vcore) ++{ ++ if(enable_scaling_voltage) ++ { ++ if(g_sCurrentVoltageCore == vcore) { ++ return; ++ } ++ ++ switch (vcore) ++ { ++ case VOLTAGE_CORE_850: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_850; ++ break; ++ ++ case VOLTAGE_CORE_900: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_900; ++ break; ++ ++ case VOLTAGE_CORE_950: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_950; ++ break; ++ ++ case VOLTAGE_CORE_1000: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_1000; ++ break; ++ ++ } ++ CLK_DBG("CurrentVoltageCore = %d\n", g_sCurrentVoltageCore); ++ } ++} ++ ++void ms_core_voltage_init(void) ++{ ++ struct device_node *np; ++ u32 val; ++ ++ if((np=of_find_node_by_name(NULL, "cpufreq"))) ++ { ++ if(!of_property_read_u32(np, "vid0-gpio", &val)) ++ vid_0 = val; ++ else ++ vid_0 = -1; ++ ++ if(!of_property_read_u32(np, "vid1-gpio", &val)) ++ vid_1 = val; ++ else ++ vid_1 = -1; ++ if(vid_0!=-1 || vid_1!=-1) ++ CLK_ERR("[%s] get dvfs gpio %s %s\n", __func__, (vid_0 != -1)?"vid_0":"", (vid_1 != -1)?"vid_1":""); ++ } ++ else ++ { ++ vid_0 = -1; ++ vid_1 = -1; ++ CLK_ERR("[%s] can't get cpufreq node for dvfs\n", __func__); ++ } ++} ++ ++#ifndef CONFIG_CAM_CLK ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return ret; ++} ++ ++void ms_cpuclk_init(struct clk_hw *clk_hw) ++{ ++ ms_core_voltage_init(); ++} ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++ .init = ms_cpuclk_init, ++}; ++#endif ++ ++static int ms_upll_utmi_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_enable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x00C0); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x01); ++ ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=0 ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=0 ++ return 0; ++} ++ ++static void ms_upll_utmi_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_disable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x01B2); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x02); ++ ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=1 ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=1 ++} ++ ++static int ms_upll_utmi_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UPLL0_PA + REG_ID_07) & BIT0); ++} ++ ++static unsigned long ms_upll_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ CLK_DBG("\nms_upll_utmi_recalc_rate, parent_rate=%lu\n\n", parent_rate); ++ return (parent_rate * 40); ++} ++ ++ ++struct clk_ops ms_upll_utmi_ops = { ++ .enable = ms_upll_utmi_enable, ++ .disable = ms_upll_utmi_disable, ++ .is_enabled = ms_upll_utmi_is_enabled, ++ .recalc_rate = ms_upll_utmi_recalc_rate, ++}; ++ ++static int ms_usb_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_enable\n\n"); ++ ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0C2F); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x040F); //utmi0 ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x7F05); ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x0A); //Disable MAC initial suspend, Reset UHC ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x28); //Release UHC reset, enable UHC and OTG XIU function ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_11, 0x2088); //PLL_TEST[30:28]: 3'b101 for IBIAS current select ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_10, 0x8051); //PLL_TEST[15]: Bypass 480MHz clock divider ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_01, 0x2084); //Enable CLK12_SEL bit <2> for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++static int ms_venpll_enable(struct clk_hw *hw) ++{ ++ CLRREG16(BASE_REG_VENPLL_PA + REG_ID_01, BIT8); //reg_ven_pll_pd=0 ++ return 0; ++} ++ ++static void ms_venpll_disable(struct clk_hw *hw) ++{ ++ SETREG16(BASE_REG_VENPLL_PA + REG_ID_01, BIT8); //reg_ven_pll_pd=1 ++} ++ ++static int ms_venpll_is_enabled(struct clk_hw *hw) ++{ ++ return ((INREG16(BASE_REG_VENPLL_PA + REG_ID_01) & 0x0100) == 0x0000); ++} ++ ++static unsigned long ms_venpll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ return (parent_rate * INREG8(BASE_REG_VENPLL_PA + REG_ID_03) / 2); ++} ++ ++static long ms_venpll_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ if(rate <= 504000000) ++ { ++ return 504000000; ++ } ++ else if(rate <= 528000000) ++ { ++ return 528000000; ++ } ++ else if(rate <= 552000000) ++ { ++ return 552000000; ++ } ++ else if(rate <= 576000000) ++ { ++ return 576000000; ++ }else{ ++ return 600000000; ++ } ++} ++ ++static int ms_venpll_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ if((rate == 504000000) || (rate == 576000000) || (rate == 528000000) || (rate == 552000000)){ ++ int val = rate * 2 / 24000000; ++ OUTREG8(BASE_REG_VENPLL_PA + REG_ID_03, val);//reg_ven_pll_loop_div_second ++ }else if(rate == 600000000){ ++ OUTREG8(BASE_REG_VENPLL_PA + REG_ID_03, 0x32);//reg_ven_pll_loop_div_second ++ OUTREG16(BASE_REG_VENPLL_PA + REG_ID_00, 0x10);//reg_ven_pll_test ++ ++ // [0]: reg_ven_pll_test_en = 1'b1 ++ // [6:4]: reg_ven_pll_icp_ictrl = 3'b001 (default) ++ // Ibias current control ++ // 000 for 0.83uA, ++ // 001 for 1.66uA, ++ // 011 for 2.5uA, ++ // 111 for 3.32uA ++ OUTREG8(BASE_REG_VENPLL_PA + REG_ID_04, 0x11); ++ }else{ ++ CLK_ERR("\nunsupported venpll rate %lu\n\n", rate); ++ return -1; ++ } ++ return 0; ++} ++ ++struct clk_ops ms_venpll_ops = { ++ .enable = ms_venpll_enable, ++ .disable = ms_venpll_disable, ++ .is_enabled = ms_venpll_is_enabled, ++ .round_rate = ms_venpll_round_rate, ++ .recalc_rate = ms_venpll_recalc_rate, ++ .set_rate = ms_venpll_set_rate, ++}; ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++#ifndef CONFIG_CAM_CLK ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++#endif ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else if(!strcmp(node->name, "CLK_venpll_clk")) ++ { ++ CLK_DBG("Find %s, hook ms_venpll_ops\n", node->name); ++ init->ops = &ms_venpll_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity6/Makefile b/drivers/sstar/clk/infinity6/Makefile +new file mode 100755 +index 000000000000..8087c0ea4927 +--- /dev/null ++++ b/drivers/sstar/clk/infinity6/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity6/ms_complex_clk.c b/drivers/sstar/clk/infinity6/ms_complex_clk.c +new file mode 100755 +index 000000000000..a735d0b4c4c6 +--- /dev/null ++++ b/drivers/sstar/clk/infinity6/ms_complex_clk.c +@@ -0,0 +1,337 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#ifndef CONFIG_CAM_CLK ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate < 100000000) ++ { ++ return 100000000; ++ } ++ else if(rate > 1400000000) ++ { ++ return 1400000000; ++ } ++ else ++ { ++ return rate; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ U32 lpf_value; ++ U32 post_div; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ CLK_DBG("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ rate = (div64_u64(432000000llu * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return ret; ++} ++ ++void ms_cpuclk_init(struct clk_hw *clk_hw) ++{ ++ return; ++} ++ ++ ++void ms_cpuclk_dvfs_disable(void) ++{ ++ return; ++} ++EXPORT_SYMBOL(ms_cpuclk_dvfs_disable); ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++ .init = ms_cpuclk_init, ++}; ++#endif ++ ++static int ms_upll_utmi_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_enable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x00C0); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x01); ++ ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=0 ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=0 ++ return 0; ++} ++ ++static void ms_upll_utmi_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_disable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x01B2); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x02); ++ ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=1 ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=1 ++} ++ ++static int ms_upll_utmi_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UPLL0_PA + REG_ID_07) & BIT0); ++} ++ ++static unsigned long ms_upll_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ CLK_DBG("\nms_upll_utmi_recalc_rate, parent_rate=%lu\n\n", parent_rate); ++ return (parent_rate * 40); ++} ++ ++ ++struct clk_ops ms_upll_utmi_ops = { ++ .enable = ms_upll_utmi_enable, ++ .disable = ms_upll_utmi_disable, ++ .is_enabled = ms_upll_utmi_is_enabled, ++ .recalc_rate = ms_upll_utmi_recalc_rate, ++}; ++ ++static int ms_usb_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_enable\n\n"); ++ ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0C2F); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x040F); //utmi0 ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x7F05); ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x0A); //Disable MAC initial suspend, Reset UHC ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x28); //Release UHC reset, enable UHC and OTG XIU function ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_11, 0x2088); //PLL_TEST[30:28]: 3'b101 for IBIAS current select ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_10, 0x8051); //PLL_TEST[15]: Bypass 480MHz clock divider ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_01, 0x2084); //Enable CLK12_SEL bit <2> for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++#ifndef CONFIG_CAM_CLK ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++#endif ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity6b0/Makefile b/drivers/sstar/clk/infinity6b0/Makefile +new file mode 100755 +index 000000000000..8087c0ea4927 +--- /dev/null ++++ b/drivers/sstar/clk/infinity6b0/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity6b0/ms_complex_clk.c b/drivers/sstar/clk/infinity6b0/ms_complex_clk.c +new file mode 100755 +index 000000000000..a735d0b4c4c6 +--- /dev/null ++++ b/drivers/sstar/clk/infinity6b0/ms_complex_clk.c +@@ -0,0 +1,337 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#ifndef CONFIG_CAM_CLK ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate < 100000000) ++ { ++ return 100000000; ++ } ++ else if(rate > 1400000000) ++ { ++ return 1400000000; ++ } ++ else ++ { ++ return rate; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ U32 lpf_value; ++ U32 post_div; ++ ++ //get LPF high ++ lpf_value = INREG16(BASE_REG_RIU_PA + (0x1032A4 << 1)) + ++ (INREG16(BASE_REG_RIU_PA + (0x1032A6 << 1)) << 16); ++ post_div = INREG16(BASE_REG_RIU_PA + (0x103232 << 1)) + 1; ++ ++ if(lpf_value == 0) // special handling for 1st time aquire after system boot ++ { ++ lpf_value= (INREG8(BASE_REG_RIU_PA + (0x1032C2 << 1)) << 16) + ++ (INREG8(BASE_REG_RIU_PA + (0x1032C1 << 1)) << 8) + ++ INREG8(BASE_REG_RIU_PA + (0x1032C0 << 1)); ++ CLK_DBG("lpf_value = %u, post_div=%u\n", lpf_value, post_div); ++ } ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ rate = (div64_u64(432000000llu * 524288, lpf_value ) * 2 / post_div * 32 / 2); ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return ret; ++} ++ ++void ms_cpuclk_init(struct clk_hw *clk_hw) ++{ ++ return; ++} ++ ++ ++void ms_cpuclk_dvfs_disable(void) ++{ ++ return; ++} ++EXPORT_SYMBOL(ms_cpuclk_dvfs_disable); ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++ .init = ms_cpuclk_init, ++}; ++#endif ++ ++static int ms_upll_utmi_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_enable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x00C0); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x01); ++ ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=0 ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=0 ++ return 0; ++} ++ ++static void ms_upll_utmi_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_disable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x01B2); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x02); ++ ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=1 ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=1 ++} ++ ++static int ms_upll_utmi_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UPLL0_PA + REG_ID_07) & BIT0); ++} ++ ++static unsigned long ms_upll_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ CLK_DBG("\nms_upll_utmi_recalc_rate, parent_rate=%lu\n\n", parent_rate); ++ return (parent_rate * 40); ++} ++ ++ ++struct clk_ops ms_upll_utmi_ops = { ++ .enable = ms_upll_utmi_enable, ++ .disable = ms_upll_utmi_disable, ++ .is_enabled = ms_upll_utmi_is_enabled, ++ .recalc_rate = ms_upll_utmi_recalc_rate, ++}; ++ ++static int ms_usb_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_enable\n\n"); ++ ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0C2F); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x040F); //utmi0 ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x7F05); ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x0A); //Disable MAC initial suspend, Reset UHC ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x28); //Release UHC reset, enable UHC and OTG XIU function ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_11, 0x2088); //PLL_TEST[30:28]: 3'b101 for IBIAS current select ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_10, 0x8051); //PLL_TEST[15]: Bypass 480MHz clock divider ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_01, 0x2084); //Enable CLK12_SEL bit <2> for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++#ifndef CONFIG_CAM_CLK ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++#endif ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/infinity6e/Makefile b/drivers/sstar/clk/infinity6e/Makefile +new file mode 100644 +index 000000000000..8087c0ea4927 +--- /dev/null ++++ b/drivers/sstar/clk/infinity6e/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/sstar/clk/infinity6e/ms_complex_clk.c b/drivers/sstar/clk/infinity6e/ms_complex_clk.c +new file mode 100644 +index 000000000000..8230e5e3c7a8 +--- /dev/null ++++ b/drivers/sstar/clk/infinity6e/ms_complex_clk.c +@@ -0,0 +1,402 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++ ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#ifndef CONFIG_CAM_CLK ++static unsigned int ms_get_ddr_scl(void) ++{ ++ unsigned int factor = INREG16(BASE_REG_RIU_PA + (0x1032A0 << 1)) | (((INREG16(BASE_REG_RIU_PA + (0x1032A2 << 1)) & 0xFF) <<16)); ++ ++ if(!factor) ++ factor = (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++ ++ CLK_DBG("ms_get_ddr_scl = 0x%X\n", factor); ++ return factor; ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate < 100000000) ++ { ++ return 100000000; ++ } ++ else if(rate > 1400000000) ++ { ++ return 1400000000; ++ } ++ else ++ { ++ return rate; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) << 23; ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv) ++{ ++ U32 u32CurrentPostDiv = 0; ++ U32 u32TempPostDiv = 0; ++ ++ u32CurrentPostDiv = INREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), 0x000F) + 1; ++ ++ if (u32TargetPostDiv > u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv<<1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //reg_lpf_enable = 0 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x000F); //reg_lpf_update_cnt = 32 ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetLpf&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetLpf>>16)&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); //reg_lpf_enable = 1 ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetLpf&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetLpf>>16)&0xFFFF); //store freq to LPF low ++ ++ if (u32TargetPostDiv < u32CurrentPostDiv) ++ { ++ u32TempPostDiv = u32CurrentPostDiv; ++ while (u32TempPostDiv != u32TargetPostDiv) ++ { ++ u32TempPostDiv = u32TempPostDiv>>1; ++ OUTREGMSK16(BASE_REG_RIU_PA + (0x103232 << 1), u32TempPostDiv-1, 0x000F); ++ } ++ } ++} ++ ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++ ++ return ret; ++} ++ ++void ms_cpuclk_init(struct clk_hw *clk_hw) ++{ ++ return; ++} ++ ++ ++void ms_cpuclk_dvfs_disable(void) ++{ ++ return; ++} ++EXPORT_SYMBOL(ms_cpuclk_dvfs_disable); ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++ .init = ms_cpuclk_init, ++}; ++#endif ++ ++static int ms_upll_utmi_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_enable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x00C0); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x01); ++ ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=0 ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=0 ++ return 0; ++} ++ ++static void ms_upll_utmi_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_disable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x01B2); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x02); ++ ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=1 ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=1 ++} ++ ++static int ms_upll_utmi_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UPLL0_PA + REG_ID_07) & BIT0); ++} ++ ++static unsigned long ms_upll_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ CLK_DBG("\nms_upll_utmi_recalc_rate, parent_rate=%lu\n\n", parent_rate); ++ return (parent_rate * 40); ++} ++ ++ ++struct clk_ops ms_upll_utmi_ops = { ++ .enable = ms_upll_utmi_enable, ++ .disable = ms_upll_utmi_disable, ++ .is_enabled = ms_upll_utmi_is_enabled, ++ .recalc_rate = ms_upll_utmi_recalc_rate, ++}; ++ ++static int ms_usb_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_enable\n\n"); ++ ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0C2F); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x040F); //utmi0 ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x7F05); ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x0A); //Disable MAC initial suspend, Reset UHC ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x28); //Release UHC reset, enable UHC and OTG XIU function ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_11, 0x2088); //PLL_TEST[30:28]: 3'b101 for IBIAS current select ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_10, 0x8051); //PLL_TEST[15]: Bypass 480MHz clock divider ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_01, 0x2084); //Enable CLK12_SEL bit <2> for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++static int ms_venpll_enable(struct clk_hw *hw) ++{ ++ CLRREG16(BASE_REG_VENPLL_PA + REG_ID_01, BIT8); //reg_ven_pll_pd=0 ++ return 0; ++} ++ ++static void ms_venpll_disable(struct clk_hw *hw) ++{ ++ SETREG16(BASE_REG_VENPLL_PA + REG_ID_01, BIT8); //reg_ven_pll_pd=1 ++} ++ ++static int ms_venpll_is_enabled(struct clk_hw *hw) ++{ ++ return ((INREG16(BASE_REG_VENPLL_PA + REG_ID_01) & 0x0100) == 0x0000); ++} ++ ++static unsigned long ms_venpll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ return (parent_rate * INREG8(BASE_REG_VENPLL_PA + REG_ID_03) / 2); ++} ++ ++static long ms_venpll_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ if(rate <= 300000000) ++ { ++ return 300000000; ++ } ++ else if(rate <= 312000000) ++ { ++ return 312000000; ++ } ++ else if(rate <= 324000000) ++ { ++ return 324000000; ++ } ++ else if(rate <= 336000000) ++ { ++ return 336000000; ++ } ++ else if(rate <= 348000000) ++ { ++ return 348000000; ++ } ++ else{ ++ return 348000000; ++ } ++} ++ ++static int ms_venpll_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ if ((rate == 348000000) || (rate == 336000000) || (rate == 324000000) || (rate == 312000000) || (rate == 300000000)) { ++ int val = rate * 2 / 24000000; ++ OUTREG8(BASE_REG_VENPLL_PA + REG_ID_03, val);//reg_ven_pll_loop_div_second ++ } else { ++ CLK_ERR("\nunsupported venpll rate %lu\n\n", rate); ++ return -1; ++ } ++ return 0; ++} ++ ++struct clk_ops ms_venpll_ops = { ++ .enable = ms_venpll_enable, ++ .disable = ms_venpll_disable, ++ .is_enabled = ms_venpll_is_enabled, ++ .round_rate = ms_venpll_round_rate, ++ .recalc_rate = ms_venpll_recalc_rate, ++ .set_rate = ms_venpll_set_rate, ++}; ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++#ifndef CONFIG_CAM_CLK ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++#endif ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else if(!strcmp(node->name, "CLK_ven_pll")) ++ { ++ CLK_ERR("Find %s, hook ms_venpll_ops\n", node->name); ++ init->ops = &ms_venpll_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s have no parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register success\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "sstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/sstar/clk/ms_composite_clk.c b/drivers/sstar/clk/ms_composite_clk.c +new file mode 100755 +index 000000000000..c75b7e6b69ba +--- /dev/null ++++ b/drivers/sstar/clk/ms_composite_clk.c +@@ -0,0 +1,365 @@ ++/* ++* ms_composite_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_PM_SLEEP ++#include ++#endif ++#include "ms_types.h" ++#include "ms_platform.h" ++ ++struct ms_clk_mux { ++ struct clk_hw hw; ++ void __iomem *reg; ++ u32 *table; ++ u32 mask; ++ u8 shift; ++ u8 flags; ++ u8 glitch; //this is specific usage for MSTAR ++ spinlock_t *lock; ++#ifdef CONFIG_PM_SLEEP ++ //u8 parent; //store parent index for resume ++ struct clk_gate *gate; ++ struct list_head list; ++#endif ++}; ++ ++#ifdef CONFIG_PM_SLEEP ++static u8 _is_syscore_register = 0; ++LIST_HEAD(ms_clk_mux_list); ++#endif ++ ++#define to_ms_clk_mux(_hw) container_of(_hw, struct ms_clk_mux, hw) ++ ++static u8 ms_clk_mux_get_parent(struct clk_hw *hw) ++{ ++ struct ms_clk_mux *mux = to_ms_clk_mux(hw); ++ int num_parents = clk_hw_get_num_parents(hw); ++ u32 val; ++ ++ val = clk_readl(mux->reg) >> mux->shift; ++ val &= mux->mask; ++ ++ if (val >= num_parents) ++ return -EINVAL; ++ ++ return val; ++} ++ ++static int ms_clk_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct ms_clk_mux *mux = to_ms_clk_mux(hw); ++ u32 val; ++ unsigned long flags = 0; ++ ++ if (mux->table) ++ index = mux->table[index]; ++ else ++ { ++ if (mux->flags & CLK_MUX_INDEX_BIT) ++ index = (1 << ffs(index)); ++ ++ if (mux->flags & CLK_MUX_INDEX_ONE) ++ index++; ++ } ++ ++ if (mux->lock) ++ spin_lock_irqsave(mux->lock, flags); ++ ++ if (mux->flags & CLK_MUX_HIWORD_MASK) ++ { ++ val = mux->mask << (mux->shift + 16); ++ } ++ else ++ { ++ val = clk_readl(mux->reg); ++ val &= ~(mux->mask << mux->shift); ++ } ++ ++ //switch to glitch-free mux(set 0) ++ if (mux->glitch) ++ { ++ val &= ~(1 << mux->glitch); ++ clk_writel(val, mux->reg); ++ } ++ ++ val |= index << mux->shift; ++ clk_writel(val, mux->reg); ++ ++ //switch back to original mux(set 1) ++ if (mux->glitch) ++ { ++ val |= 1 << mux->glitch; ++ clk_writel(val, mux->reg); ++ } ++ ++ if (mux->lock) ++ spin_unlock_irqrestore(mux->lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long ms_clk_mux_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct ms_clk_mux *mux = to_ms_clk_mux(hw); ++ ++ if (mux->glitch) ++ { ++ if(clk_readl(mux->reg) & (1 << mux->glitch)) ++ { ++ pr_debug("\n <%s> parent_rate=%lu, glitch-mux=1\n\n", hw->init->name, parent_rate); ++ return parent_rate; ++ } ++ else ++ { ++ pr_debug("\n <%s> parent_rate=%lu, glitch-mux=0\n\n", hw->init->name, parent_rate); ++ return 12000000; ++ } ++ } ++ ++ pr_debug("\n <%s> parent_rate=%lu, no glitch-mux\n\n", hw->init->name, parent_rate); ++ return parent_rate; ++ ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int ms_clk_mux_suspend(void) ++{ ++ struct ms_clk_mux *mux; ++ //struct clk *clk; ++ ++ //keep parent index for restoring clocks in resume ++ list_for_each_entry(mux, &ms_clk_mux_list, list) ++ { ++ /* ++ if (mux && mux->hw.clk) { ++ clk = mux->hw.clk; ++ pr_err("clk %s cnt %d parnet %d\n", __clk_get_name(clk), ++ __clk_get_enable_count(clk), ++ ms_clk_mux_get_parent(&mux->hw)); ++ mux->parent = ms_clk_mux_get_parent(&mux->hw); ++ } ++ */ ++ if (mux && mux->gate) { ++ //clock already disabled, not need to restore it in resume ++ if (clk_gate_ops.is_enabled(&mux->gate->hw) == 0) { ++ mux->gate = NULL; ++ } ++ } ++ } ++ //pr_debug("ms_clk_mux_suspend\n"); ++ ++ return 0; ++} ++ ++static void ms_clk_mux_resume(void) ++{ ++ struct ms_clk_mux *mux; ++ ++ //restore auto-enable clocks in list ++ list_for_each_entry(mux, &ms_clk_mux_list, list) ++ { ++ /* ++ if (mux) { ++ //ms_clk_mux_set_parent(&mux->hw, mux->parent); ++ if (clk_gate_ops.enable && mux->gate) { ++ clk_gate_ops.enable(&mux->gate->hw); ++ } ++ pr_err("clk %s cnt %d parnet %d\n", __clk_get_name(mux->hw.clk), ++ __clk_get_enable_count(mux->hw.clk), ++ mux->parent); ++ } ++ */ ++ if (mux && mux->gate) { ++ clk_gate_ops.enable(&mux->gate->hw); ++ } ++ } ++ //pr_debug("ms_clk_mux_resume\n"); ++} ++ ++struct syscore_ops ms_clk_mux_syscore_ops = { ++ .suspend = ms_clk_mux_suspend, ++ .resume = ms_clk_mux_resume, ++}; ++#endif ++ ++struct clk_ops ms_clk_mux_ops = { ++ .get_parent = ms_clk_mux_get_parent, ++ .set_parent = ms_clk_mux_set_parent, ++ .determine_rate = __clk_mux_determine_rate, ++ .recalc_rate = ms_clk_mux_recalc_rate, ++}; ++ ++ ++static void __init ms_clk_composite_init(struct device_node *node) ++{ ++ const char *clk_name = node->name; ++ int num_parents; ++ const char **parent_names; ++ struct ms_clk_mux *mux = NULL; ++ struct clk_gate *gate = NULL; ++ void __iomem *reg; ++ u32 i, mux_shift, mux_width, mux_glitch, bit_idx, auto_enable,ignore; ++ struct clk *clk; ++ unsigned int flag = 0; ++ ++ num_parents = of_clk_get_parent_count(node); ++ if(num_parents<0) ++ num_parents = 0; ++ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); ++ mux = kzalloc(sizeof(*mux), GFP_KERNEL); ++ gate = kzalloc(sizeof(*gate), GFP_KERNEL); ++ ++ if (!parent_names || !mux || !gate) ++ { ++ pr_err("<%s> allocate mem fail\n", clk_name); ++ goto fail; ++ } ++ ++ reg = of_iomap(node, 0); ++ if (!reg) ++ { ++ pr_err("<%s> map region fail\n", clk_name); ++ goto fail; ++ } ++ ++ for (i = 0; i < num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ mux->reg = reg; ++ gate->reg = reg; ++ gate->flags = CLK_GATE_SET_TO_DISABLE; ++ ++ //flag = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED; //remove ignore_unused flag when all drivers use clk framework, so some clks will be gated ++ if(!of_property_read_u32(node, "ignore", &ignore)) ++ { ++ if(ignore) ++ { ++ pr_debug("<%s> ignore gate clock\n",clk_name); ++ flag = CLK_IGNORE_UNUSED; ++ } ++ } ++ if(of_property_read_u32(node, "mux-shift", &mux_shift)) ++ { ++ pr_debug("<%s> no mux-shift, treat as gate clock\n", clk_name); ++ mux->shift = 0xFF; ++ } ++ else ++ mux->shift = (u8)mux_shift; ++ ++ if(of_property_read_u32(node, "mux-width", &mux_width)) ++ { ++ pr_debug("<%s> no mux-width, set to default 2 bits\n", clk_name); ++ mux->mask = BIT(2) - 1; ++ } ++ else ++ mux->mask = BIT((u8)mux_width) - 1; ++ ++ if(of_property_read_u32(node, "glitch-shift", &mux_glitch)) ++ { ++ mux->glitch = 0; ++ } ++ else ++ mux->glitch = (u8)mux_glitch; ++ ++ if(of_property_read_u32(node, "gate-shift", &bit_idx)) ++ { ++ pr_debug("<%s> no gate-shift, can not be gated\n", clk_name); ++ gate->bit_idx = 0xFF; ++ } ++ else ++ gate->bit_idx = (u8)bit_idx; ++ ++ pr_debug("[%s]\nmux->reg=0x%08X\nmux->shift=%d\nmux->width=%d\nmux->glitch=%d\ngate->bit_idx=%d\n", ++ clk_name, (unsigned int)mux->reg, mux->shift, mux_width, mux->glitch, gate->bit_idx); ++ ++ if(mux->shift != 0xFF && gate->bit_idx != 0xFF) ++ { ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ &mux->hw, &ms_clk_mux_ops, ++ &mux->hw, &ms_clk_mux_ops, ++ &gate->hw, &clk_gate_ops, flag); ++ } ++ else if(mux->shift != 0xFF) ++ { ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ &mux->hw, &ms_clk_mux_ops, ++ &mux->hw, &ms_clk_mux_ops, ++ NULL, NULL, flag); ++ kfree(gate); ++ gate = NULL; ++ } ++ else if(gate->bit_idx != 0xFF) ++ { ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ NULL, NULL, ++ NULL, NULL, ++ &gate->hw, &clk_gate_ops, flag); ++ kfree(mux); ++ } ++ else ++ { ++ pr_err("clock <%s> info err\n", clk_name); ++ goto fail; ++ } ++ ++ if (IS_ERR(clk)) ++ { ++ pr_err("%s: register clock <%s> fail\n", __func__, clk_name); ++ goto fail; ++ } ++ ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, clk_name, NULL); ++ ++ if(!of_property_read_u32(node, "auto-enable", &auto_enable)) ++ { ++ if (auto_enable) ++ { ++ clk_prepare_enable(clk); ++#ifdef CONFIG_PM_SLEEP ++ //keep auto-enable clocks into list for restoring clock in resume ++ mux->gate = gate; ++ list_add(&mux->list, &ms_clk_mux_list); ++#endif ++ pr_debug("clk_prepare_enable <%s>\n", clk_name); ++ } ++ } ++ ++#ifdef CONFIG_PM_SLEEP ++ if (!_is_syscore_register) { ++ register_syscore_ops(&ms_clk_mux_syscore_ops); ++ _is_syscore_register = 1; ++ } ++#endif ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(mux); ++ kfree(gate); ++ return; ++} ++ ++CLK_OF_DECLARE(ms_clk_composite, "sstar,composite-clock", ms_clk_composite_init); +diff --git a/drivers/sstar/clk/ms_usclk.c b/drivers/sstar/clk/ms_usclk.c +new file mode 100755 +index 000000000000..d7fa720d5cc7 +--- /dev/null ++++ b/drivers/sstar/clk/ms_usclk.c +@@ -0,0 +1,252 @@ ++/* ++* ms_usclk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * /sys/class/clk ++ * usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&foo 15>, <&bar>; ++ clock-count = <2>; ++ }; ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "usclk" ++ ++struct usclk_data { ++ struct clk* clk; ++ struct clk_hw *hw; ++ int enabled; ++}; ++ ++struct usclk_data *g_pdata; ++struct class *g_clk_class; ++struct device **g_dev; ++u32 g_clock_count; ++ ++static ssize_t enable_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ if(!pdata->hw->init->ops->is_enabled) ++ return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled); ++ else ++ return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->hw->init->ops->is_enabled(pdata->hw)); ++} ++ ++static ssize_t enable_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long enable; ++ int ret; ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &enable); ++ if (ret) ++ return -EINVAL; ++ ++ enable = !!enable; ++ ++ if (enable) ++ pdata->hw->init->ops->enable(pdata->hw); ++ else ++ pdata->hw->init->ops->disable(pdata->hw); ++ ++ pdata->enabled = enable; ++ ++ return count; ++} ++ ++static DEVICE_ATTR(enable, 0644, enable_show, enable_store); ++ ++static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_hw_get_rate(pdata->hw)); ++} ++ ++static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int ret = 0; ++ unsigned long rate; ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &rate); ++ if (ret) ++ { ++ return -EINVAL; ++ } ++ ++ rate = clk_hw_round_rate(pdata->hw, rate); ++ ret = clk_set_rate(pdata->hw->clk, rate); ++ if (ret) ++ { ++ return -EBUSY; ++ } ++ else ++ { ++ pr_info("round rate to %lu\n", rate); ++ } ++ ++ return count; ++} ++ ++static DEVICE_ATTR(rate, 0644, set_rate_show, set_rate_store); ++ ++static const struct attribute *usclk_attrs[] = { ++ &dev_attr_enable.attr, ++ &dev_attr_rate.attr, ++ NULL ++}; ++ ++static const struct attribute_group usclk_attr_grp = { ++ .attrs = (struct attribute **)usclk_attrs, ++}; ++ ++static int usclk_setup(void) ++{ ++ int ret; ++ int i; ++ struct device_node *np = of_find_compatible_node(NULL, NULL, "usclk"); ++ ++ ++// printk(KERN_INFO"setup ms_usclk interface\n"); ++ ret = of_property_read_u32(np, "clock-count", &g_clock_count); ++ if (ret || !g_clock_count) ++ return ret; ++ ++ g_pdata = kzalloc(g_clock_count * sizeof(*g_pdata), GFP_KERNEL); ++ if (!g_pdata) ++ return -ENOMEM; ++ ++ g_dev = kzalloc(g_clock_count * sizeof(struct dev*), GFP_KERNEL); ++ if (!g_dev) ++ return -ENOMEM; ++ ++ g_clk_class = class_create(THIS_MODULE, "usclk"); ++ if (!g_clk_class) { ++ pr_err("create class fail\n"); ++ goto err_free; ++ } ++ ++ ++ ++ for (i = 0; i < g_clock_count; i++) { ++ ++ g_pdata[i].clk = of_clk_get(np, i); ++ if (IS_ERR(g_pdata[i].clk)) ++ { ++ continue; ++ } ++ g_pdata[i].hw = __clk_get_hw(g_pdata[i].clk); ++ if (IS_ERR(g_pdata[i].hw)) { ++ pr_warn("input clock #%u not found\n", i); ++ clk_put(g_pdata[i].clk); ++ continue; ++ } ++ ++ g_dev[i] = device_create(g_clk_class, NULL, MKDEV(0, 0), NULL, ++ of_clk_get_parent_name(np, i)); ++ ++ if (!g_dev[i]) { ++ pr_warn("unable to create device #%d\n", i); ++ continue; ++ } ++ ++ dev_set_drvdata(g_dev[i], &g_pdata[i]); ++ if(0!=sysfs_create_group(&g_dev[i]->kobj, &usclk_attr_grp)) ++ { ++ pr_warn("create device #%d failed...\n", i); ++ } ++ } ++ ++ printk(KERN_WARNING "ms_usclk: initialized\n"); ++ return 0; ++ ++err_free: ++ if(g_pdata) ++ kfree(g_pdata); ++ ++ if(g_dev) ++ kfree(g_dev); ++ ++ return ret; ++} ++// ++ ++#ifdef CONFIG_MS_USCLK_MODULE ++ ++static int __init ms_usclk_module_init(void) ++{ ++// int retval=0; ++// retval = platform_driver_register(&ms_ir_driver); ++ ++ return usclk_setup(); ++// return retval; ++} ++ ++static void __exit ms_usclk_module_exit(void) ++{ ++ int i; ++// platform_driver_unregis.ter(&ms_ir_driver); ++ ++ for (i = 0; i < g_clock_count; i++) { ++ if(g_dev[i]) ++ { ++ sysfs_remove_group(&g_dev[i]->kobj, &usclk_attr_grp); ++ device_destroy(g_clk_class, g_dev[i]->devt); ++ } ++ if (!IS_ERR(g_pdata[i].clk)) ++ { ++ clk_put(g_pdata[i].clk); ++ } ++ } ++ ++ if(g_clk_class) ++ class_destroy(g_clk_class); ++ ++ if(g_pdata) ++ kfree(g_pdata); ++ ++ if(g_dev) ++ kfree(g_dev); ++ ++} ++ ++ ++module_init(ms_usclk_module_init); ++module_exit(ms_usclk_module_exit); ++ ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("usclk driver"); ++MODULE_LICENSE("GPL"); ++ ++#else ++late_initcall(usclk_setup); ++#endif +diff --git a/drivers/sstar/clocksource/Kconfig b/drivers/sstar/clocksource/Kconfig +new file mode 100755 +index 000000000000..d773bdc24670 +--- /dev/null ++++ b/drivers/sstar/clocksource/Kconfig +@@ -0,0 +1,7 @@ ++config MS_CA9_GT_CLOCKSOURCE ++ bool "ARM CA9 GT Timer for clocksource" ++ depends on ARCH_CEDRIC ++ depends on ARM_GLOBAL_TIMER ++ ++config MS_PIU_TIMER ++ bool "PIU Timer driver" +\ No newline at end of file +diff --git a/drivers/sstar/clocksource/Makefile b/drivers/sstar/clocksource/Makefile +new file mode 100755 +index 000000000000..5f38a9eaa53f +--- /dev/null ++++ b/drivers/sstar/clocksource/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/clocksource ++ ++obj-$(CONFIG_MS_CA9_GT_CLOCKSOURCE) += ms_arm_gt_clocksource.o ++obj-$(CONFIG_MS_PIU_TIMER) += ms_piu_timer.o +\ No newline at end of file +diff --git a/drivers/sstar/clocksource/ms_arm_gt_clocksource.c b/drivers/sstar/clocksource/ms_arm_gt_clocksource.c +new file mode 100755 +index 000000000000..945179cb7c3c +--- /dev/null ++++ b/drivers/sstar/clocksource/ms_arm_gt_clocksource.c +@@ -0,0 +1,176 @@ ++/* ++* ms_arm_gt_clocksource.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define GT_COUNTER0 0x00 ++#define GT_COUNTER1 0x04 ++ ++#define GT_CONTROL 0x08 ++#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ ++#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ ++#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ ++#define GT_CONTROL_AUTO_INC BIT(3) /* banked */ ++ ++#define GT_INT_STATUS 0x0c ++#define GT_INT_STATUS_EVENT_FLAG BIT(0) ++ ++#define GT_COMP0 0x10 ++#define GT_COMP1 0x14 ++#define GT_AUTO_INC 0x18 ++ ++/* ++ * We are expecting to be clocked by the ARM peripheral clock. ++ * ++ * Note: it is assumed we are using a prescaler value of zero, so this is ++ * the units for all operations. ++ */ ++static void __iomem *gt_base; ++static unsigned long gt_clk_rate; ++ ++ ++/* ++ * To get the value from the Global Timer Counter register proceed as follows: ++ * 1. Read the upper 32-bit timer counter register ++ * 2. Read the lower 32-bit timer counter register ++ * 3. Read the upper 32-bit timer counter register again. If the value is ++ * different to the 32-bit upper value read previously, go back to step 2. ++ * Otherwise the 64-bit timer counter value is correct. ++ */ ++static u64 gt_counter_read(void) ++{ ++ u64 counter; ++ u32 lower; ++ u32 upper, old_upper; ++ ++ upper = readl_relaxed(gt_base + GT_COUNTER1); ++ do { ++ old_upper = upper; ++ lower = readl_relaxed(gt_base + GT_COUNTER0); ++ upper = readl_relaxed(gt_base + GT_COUNTER1); ++ } while (upper != old_upper); ++ ++ counter = upper; ++ counter <<= 32; ++ counter |= lower; ++ return counter; ++} ++ ++ ++static cycle_t gt_clocksource_read(struct clocksource *cs) ++{ ++ return gt_counter_read(); ++} ++ ++static struct clocksource gt_clocksource = { ++ .name = "arm_global_timer", ++ .rating = 300, ++ .read = gt_clocksource_read, ++ .mask = CLOCKSOURCE_MASK(64), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++#if 1//def CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK ++static u64 notrace gt_sched_clock_read(void) ++{ ++ return gt_counter_read(); ++} ++#endif ++ ++static void __init gt_clocksource_init(void) ++{ ++ writel(0, gt_base + GT_CONTROL); ++ writel(0, gt_base + GT_COUNTER0); ++ writel(0, gt_base + GT_COUNTER1); ++ /* enables timer on all the cores */ ++ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); ++ ++#if 1//def CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK ++ sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate); ++#endif ++ clocksource_register_hz(>_clocksource, gt_clk_rate); ++} ++ ++ ++static void __init ms_gt_clocksource_of_init(struct device_node *np) ++{ ++ struct clk *gt_clk; ++ int err = 0; ++ ++ /* ++ * In A9 r2p0 the comparators for each processor with the global timer ++ * fire when the timer value is greater than or equal to. In previous ++ * revisions the comparators fired when the timer value was equal to. ++ */ ++ if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9 ++ && (read_cpuid_id() & 0xf0000f) < 0x200000) { ++ pr_warn("global-timer: non support for this cpu version.\n"); ++ return; ++ } ++ ++ gt_base = of_iomap(np, 0); ++ if (!gt_base) { ++ pr_warn("global-timer: invalid base address\n"); ++ return; ++ } ++ ++ gt_clk = of_clk_get(np, 0); ++ if (!IS_ERR(gt_clk)) { ++ err = clk_prepare_enable(gt_clk); ++ if (err) ++ goto out_unmap; ++ } else { ++ pr_warn("global-timer: clk not found\n"); ++ err = -EINVAL; ++ goto out_unmap; ++ } ++ ++ gt_clk_rate = clk_get_rate(gt_clk); ++ ++ /* Immediately configure the timer on the boot CPU */ ++ gt_clocksource_init(); ++ ++ if (!IS_ERR(gt_clk)) { ++ clk_put(gt_clk) ++ } ++ ++ return; ++ ++out_unmap: ++ if (!IS_ERR(gt_clk)) { ++ clk_put(gt_clk) ++ } ++ iounmap(gt_base); ++ WARN(err, "ARM Global timer register failed (%d)\n", err); ++} ++ ++/* Only tested on r2p2 and r3p0 */ ++CLOCKSOURCE_OF_DECLARE(arm_gt_clocksource, "sstar,arm-gt-clocksource", ms_gt_clocksource_of_init); +diff --git a/drivers/sstar/clocksource/ms_piu_timer.c b/drivers/sstar/clocksource/ms_piu_timer.c +new file mode 100755 +index 000000000000..423e09965711 +--- /dev/null ++++ b/drivers/sstar/clocksource/ms_piu_timer.c +@@ -0,0 +1,434 @@ ++/* ++* ms_piu_timer.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++ ++#include "ms_platform.h" ++ ++ ++//------------------------------------------------------------------------------ ++// Macros ++//------------------------------------------------------------------------------ ++#define COPY_RTC_CNT 0 ++#define USE_ARM_GT 0 //# for better schedule resolution ++ ++#if COPY_RTC_CNT ++ ++#define TIMER_RTC_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x000900) ++#define CHIPTOP_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x080F00) ++#define CPY_RTC_TIMER_INTERVAL 1000 / HZ ++ ++//volatile PREG_TIMER_st g_pTimer2Regs = NULL; ++volatile PREG_CHIPTOP_st g_pCHIPTOPReg = NULL; ++volatile PREG_RTC_st g_pRTCReg = NULL; ++ ++struct timer_list cpy_rtc_timer; ++ ++extern DEVINFO_RTK_FLAG ms_devinfo_rtk_flag(void); ++#endif ++ ++ ++extern unsigned long XTAL_CLK; ++ ++#ifdef __arm__ ++void cap_delay_t(u32 tick) ++{ ++ __asm__ __volatile__( ++"1: nop\n" ++" subs %0, %0, #1\n" ++" bne 1b" ++ : ++ : "r" (tick)); ++} ++#endif ++ ++#define TIMER_ENABLE (0x1) ++#define TIMER_TRIG (0x2) ++#define TIMER_INTERRUPT (0x100) ++#define TIMER_CLEAR (0x4) ++#define TIMER_CAPTURE (0x8) ++#define ADDR_TIMER_MAX_LOW (0x2<<2) ++#define ADDR_TIMER_MAX_HIGH (0x3<<2) ++ ++ ++struct ms_piu_timer { ++ void __iomem *base; ++ unsigned long freq; ++ int irq; ++}; ++ ++struct ms_piu_timer_clockevent { ++ struct clock_event_device event; ++ struct ms_piu_timer timer; ++ struct irqaction irqaction; ++}; ++ ++struct ms_piu_timer_clocksource { ++ struct ms_piu_timer timer; ++ struct clocksource source; ++}; ++ ++ ++static int timer_set_next_event(unsigned long next, struct clock_event_device *evt); ++static int timer_set_state_periodic(struct clock_event_device *evt); ++static int timer_set_state_oneshot(struct clock_event_device *evt); ++static int timer_set_oneshot_stopped(struct clock_event_device *evt); ++static int timer_set_state_shutdown(struct clock_event_device *evt); ++ ++static inline struct ms_piu_timer_clockevent *to_ms_clockevent(struct clock_event_device *evt) ++{ ++ return container_of(evt, struct ms_piu_timer_clockevent, event); ++} ++ ++static inline struct ms_piu_timer_clocksource *to_ms_clocksource(struct clocksource *cs) ++{ ++ return container_of(cs, struct ms_piu_timer_clocksource, source); ++} ++ ++ ++static cycle_t timer_read(struct clocksource *cs) ++{ ++ ++ struct ms_piu_timer_clocksource *ms_cs=to_ms_clocksource(cs); ++#if 0 ++ unsigned int high=INREG16(ms_cs->timer.base+(0x5<<2)); ++ unsigned int low0=INREG16(ms_cs->timer.base+(0x4<<2)); ++ unsigned int low1=INREG16(ms_cs->timer.base+(0x4<<2)); ++ if(low0>low1) ++ { ++ high=INREG16(ms_cs->timer.base+(0x5<<2)); ++ } ++#else ++ //hardware capture ++ unsigned int low0=INREG16(ms_cs->timer.base+(0x4<<2)); ++ unsigned int high=INREG16(ms_cs->timer.base+(0x5<<2)); ++#endif ++ return ((high&0xffff)<<16) + (low0&0xffff) ; ++ ++} ++ ++ ++ ++static struct ms_piu_timer_clocksource* sched_clocksource=NULL; ++static u64 notrace timer_read_sched_clock(void) ++{ ++ if(sched_clocksource) ++ { ++ return timer_read(&sched_clocksource->source); ++ } ++ return 0; ++} ++ ++static int __init ms_piu_timer_clocksource_of_init(struct device_node *np) ++{ ++ ++ struct clk *clk; ++ struct resource res; ++ ++ struct ms_piu_timer_clocksource *ms_cs = kzalloc(sizeof(*ms_cs), GFP_KERNEL); ++ BUG_ON(ms_cs==NULL); ++ BUG_ON(of_address_to_resource(np, 0, &res)); ++ ++ clk = of_clk_get(np, 0); ++ BUG_ON(IS_ERR(clk)); ++ ++ ++ ms_cs->timer.base=(void *)res.start; ++ ++ ms_cs->timer.freq=clk_get_rate(clk); ++ ++ clk_put(clk); ++ ++ ms_cs->source.name = "timer_clksrc"; ++ ms_cs->source.rating = 200; ++ ms_cs->source.read = timer_read; ++ ms_cs->source.mask = CLOCKSOURCE_MASK(32); ++ ms_cs->source.flags = CLOCK_SOURCE_IS_CONTINUOUS; ++ ++ ++ /* setup timer 2 as free-running clocksource */ ++ //make sure timer 2 is disable ++ CLRREG16(ms_cs->timer.base, TIMER_ENABLE); ++ ++ //set max period ++ OUTREG16(ms_cs->timer.base+(0x2<<2),0xffff); ++ OUTREG16(ms_cs->timer.base+(0x3<<2),0xffff); ++ ++ //enable timer 2 ++ SETREG16(ms_cs->timer.base, TIMER_ENABLE); ++ ++ ++ clocksource_register_hz(&ms_cs->source, ms_cs->timer.freq); ++ ++ sched_clocksource=ms_cs; ++ sched_clock_register(timer_read_sched_clock, 32, ms_cs->timer.freq); ++ ++ return 0; ++ ++ ++} ++ ++ ++static int timer_set_state_periodic(struct clock_event_device *evt) ++{ ++ unsigned short ctl=TIMER_INTERRUPT; ++ unsigned long interval; ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ ++ interval = (ms_ce->timer.freq / HZ) ; ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_LOW, (interval &0xffff)); ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_HIGH, (interval >>16)); ++ ctl|=TIMER_ENABLE; ++ SETREG16(ms_ce->timer.base, ctl); ++ ++ return 0; ++} ++ ++static int timer_set_state_oneshot(struct clock_event_device *evt) ++{ ++ unsigned short ctl=TIMER_INTERRUPT; ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ ++ /* period set, and timer enabled in 'next_event' hook */ ++ ctl|=TIMER_TRIG; ++ SETREG16(ms_ce->timer.base, ctl); ++ ++ return 0; ++} ++ ++static int timer_set_oneshot_stopped(struct clock_event_device *evt) ++{ ++ unsigned short ctl=TIMER_INTERRUPT; ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ ++ /* period set, and timer enabled in 'next_event' hook */ ++ ctl&=~TIMER_TRIG; ++ SETREG16(ms_ce->timer.base, ctl); ++ ++ return 0; ++} ++ ++static int timer_set_state_shutdown(struct clock_event_device *evt) ++{ ++ unsigned short ctl=TIMER_INTERRUPT; ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ ++ ctl|=TIMER_ENABLE; ++ CLRREG16(ms_ce->timer.base, ctl); ++ ++ return 0; ++} ++ ++static int timer_set_next_event(unsigned long next, struct clock_event_device *evt) ++{ ++ ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ //stop timer ++ //OUTREG16(clkevt_base, 0x0); ++ ++ //set period ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_LOW, (next &0xffff)); ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_HIGH, (next >>16)); ++ ++ //enable timer ++ SETREG16(ms_ce->timer.base, TIMER_TRIG|TIMER_INTERRUPT);//default ++ ++ return 0; ++} ++ ++ ++//static DEFINE_SPINLOCK(hw_sys_timer_lock); ++#if COPY_RTC_CNT ++ ++#define RTC_FREQ 32768 ++static void ms_copy_rtc_cnt(unsigned long dummy) ++{ ++ u32 rtc0, rtc1, secl, sech; ++ u32 u32RTCCounts; ++ static u32 dtmr = 0, drtc = 0; ++ ++ //rtc freq 32k ++ rtc0 = INREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_H) << 16; ++ rtc0 += INREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_L); ++ rtc0 = rtc0 * RTC_FREQ + INREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT); ++ ++ secl = INREG16(&g_pRTCReg->RTC_RAW_SEC_CNT_L); ++ sech = INREG16(&g_pRTCReg->RTC_RAW_SEC_CNT_H); ++ u32RTCCounts = INREG16(&g_pRTCReg->RTC_RAW_SUB_CNT); ++ ++ // Lock mutex ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT, 0x8000); ++ ++ // Update RTC sec in CHIPTOP dummy register for GPS ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_L, secl); ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_H, sech); ++ ++ // Reset Timer2 ++ //OUTREG16(&g_pTimer2Regs->TIMER_MAX_L, 0x0); ++ ++ // Update RTC sub cnt in CHIPTOP dummy register for GPS ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT, u32RTCCounts); ++ ++ // Calculate tmr to rtc ratio ++ rtc1 = (sech << 16) + secl; ++ rtc1 = rtc1 * RTC_FREQ + u32RTCCounts; ++ drtc += (rtc1 - rtc0); ++ dtmr += timer_read(&clocksource_timer) - dtmr; ++ ++ if (drtc > RTC_FREQ) // accumulate for 1 sec ++ { ++ OUTREG16(&g_pCHIPTOPReg->REG_CHIPTOP_1F, (dtmr / drtc)); ++ dtmr = drtc = 0; ++ } ++ ++ cpy_rtc_timer.expires = jiffies + msecs_to_jiffies(CPY_RTC_TIMER_INTERVAL); ++ add_timer(&cpy_rtc_timer); ++} ++ ++static void ms_copy_rtc_cnt_init(void) ++{ ++ g_pRTCReg = (PREG_RTC_st)(TIMER_RTC_BASE); ++ //g_pTimer2Regs = (PREG_TIMER_st)(TIMER_CLKSRC_BASE); ++ g_pCHIPTOPReg = (PREG_CHIPTOP_st)(CHIPTOP_BASE); ++ ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_L, INREG16(&g_pRTCReg->RTC_SECOND_CNT_L)); ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_H, INREG16(&g_pRTCReg->RTC_SECOND_CNT_H)); ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT, INREG16(&g_pRTCReg->RTC_SUB_CNT)); ++ ++ init_timer(&cpy_rtc_timer); ++ cpy_rtc_timer.expires = jiffies + msecs_to_jiffies(CPY_RTC_TIMER_INTERVAL); ++ cpy_rtc_timer.data = 0; ++ cpy_rtc_timer.function = ms_copy_rtc_cnt; ++ add_timer(&cpy_rtc_timer); ++ ++ //call right now here ++ ms_copy_rtc_cnt(0); ++} ++#endif ++ ++static irqreturn_t ms_timer_interrupt(int irq, void *dev_id) ++{ ++ ++ struct clock_event_device *evt = dev_id; ++#if defined(CONFIG_MSTAR_CEDRIC) && defined(CONFIG_PROFILING) && defined(CONFIG_OPROFILE) ++ int cpu = smp_processor_id(); ++ extern u32 armpmu_enable_flag[]; ++#endif ++ ++ evt->event_handler(evt); ++ ++/* Mantis 212633 oprofile can't work */ ++#if defined(CONFIG_MSTAR_CEDRIC) && defined(CONFIG_PROFILING) && defined(CONFIG_OPROFILE) ++ /* local_timer call pmu_handle_irq instead of PMU interrupt can't raise by itself. */ ++ if (armpmu_enable_flag[cpu]) { ++ extern irqreturn_t armpmu_handle_irq(int irq_num, void *dev); ++ armpmu_handle_irq(cpu, NULL); ++ } ++#endif ++ ++ ++ return IRQ_HANDLED; ++ ++} ++ ++ ++ ++static int __init ms_piu_timer_clockevent_of_init(struct device_node *np) ++{ ++ struct ms_piu_timer_clockevent *ms_ce = kzalloc(sizeof(*ms_ce), GFP_KERNEL); ++ ++ struct clk *clk; ++ struct resource res; ++ ++ BUG_ON(ms_ce==NULL); ++ BUG_ON(of_address_to_resource(np, 0, &res)); ++ ++ clk = of_clk_get(np, 0); ++ BUG_ON(IS_ERR(clk)); ++ ++ ms_ce->timer.base=(void *)res.start; ++ ++ ms_ce->timer.freq=clk_get_rate(clk); ++ ++ clk_put(clk); ++ ++ ms_ce->timer.irq =irq_of_parse_and_map(np, 0); ++ printk("%s: irq %d", __func__, ms_ce->timer.irq); ++ if (ms_ce->timer.irq == 0) ++ { ++ panic("No IRQ for clock event timer"); ++ } ++ ++ ms_ce->event.name = "timer_clkevt"; ++ ms_ce->event.shift = 32; ++ ms_ce->event.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; ++#if 1 ++ ms_ce->event.set_state_periodic = timer_set_state_periodic; ++ ms_ce->event.set_state_oneshot = timer_set_state_oneshot; ++ ms_ce->event.set_state_oneshot_stopped = timer_set_oneshot_stopped; ++ ms_ce->event.set_state_shutdown = timer_set_state_shutdown; ++#else ++ ms_ce->event.set_mode = timer_set_mode; ++#endif ++ ms_ce->event.set_next_event = timer_set_next_event; ++ ms_ce->event.rating = 200; ++ ms_ce->event.cpumask = cpu_all_mask; ++ ms_ce->event.irq=ms_ce->timer.irq; ++ ++ ms_ce->irqaction.name = "MS Timer Tick"; ++ ms_ce->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL; ++ ms_ce->irqaction.handler = ms_timer_interrupt; ++ ms_ce->irqaction.dev_id = &ms_ce->event; ++ ++ ++ ++ ++ clockevents_calc_mult_shift(&ms_ce->event,ms_ce->timer.freq,5); ++ ms_ce->event.max_delta_ns = clockevent_delta2ns(0xffffffff, &ms_ce->event); ++ ms_ce->event.min_delta_ns = clockevent_delta2ns(0xf, &ms_ce->event); ++ BUG_ON( setup_irq(ms_ce->event.irq, &ms_ce->irqaction) ); ++ ++ clockevents_register_device( &ms_ce->event); ++ ++ ++#if COPY_RTC_CNT ++ //put it last, because it will use the clock event device ++ if (DEVINFO_RTK_FLAG_1 == ms_devinfo_rtk_flag()) ++ ms_copy_rtc_cnt_init(); ++#endif ++ ++ ++ return 0; ++} ++ ++ ++CLOCKSOURCE_OF_DECLARE(ms_piu_timer_cs, "sstar,piu-clocksource", ms_piu_timer_clocksource_of_init); ++CLOCKSOURCE_OF_DECLARE(ms_piu_timer_ce, "sstar,piu-clockevent", ms_piu_timer_clockevent_of_init); +diff --git a/drivers/sstar/cpu/Makefile b/drivers/sstar/cpu/Makefile +new file mode 100755 +index 000000000000..43bdfc62e9af +--- /dev/null ++++ b/drivers/sstar/cpu/Makefile +@@ -0,0 +1,11 @@ ++# ++# Makefile for CPU LX size drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/cpu ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++# files ++obj-y += mem-ory.o ++mem-ory-objs += memory.o +diff --git a/drivers/sstar/cpu/memory.c b/drivers/sstar/cpu/memory.c +new file mode 100755 +index 000000000000..3f341266db64 +--- /dev/null ++++ b/drivers/sstar/cpu/memory.c +@@ -0,0 +1,1149 @@ ++/* ++* memory.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++//#include // #include "../titania2/board/Board.h" ++/*#define DEBUG*/ ++//#include ++#include ++//#include ++ ++#include ++ ++#ifdef CONFIG_ARM_LPAE ++#include ++#endif ++#include "mdrv_types.h" ++ ++ ++ ++//__aeabi_uldivmod ++unsigned long long __aeabi_uldivmod(unsigned long long n, unsigned long long d) ++{ ++ return div64_u64(n, d); ++} ++ ++EXPORT_SYMBOL(__aeabi_uldivmod); ++ ++ ++//__aeabi_ldivmod ++long long __aeabi_ldivmod(long long n, long long d) ++{ ++ return div64_s64(n, d); ++} ++ ++EXPORT_SYMBOL(__aeabi_ldivmod); ++ ++static char coredump_path[CORENAME_MAX_SIZE]={0}; ++static int __init Coredump_setup(char *str) ++{ ++ if( str != NULL) ++ { ++ strncpy(coredump_path, str, CORENAME_MAX_SIZE-1); ++ } ++ else ++ { ++ printk("depend on core pattern\n"); ++ } ++ return 0; ++} ++early_param("CORE_DUMP_PATH", Coredump_setup); ++#if 0 ++ ++enum yamon_memtypes { ++ yamon_dontuse, ++ yamon_prom, ++ yamon_free, ++}; ++//static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; ++ ++#ifdef DEBUG ++static char *mtypes[3] = { ++ "Dont use memory", ++ "YAMON PROM memory", ++ "Free memmory", ++}; ++#endif ++ ++/* determined physical memory size, not overridden by command line args */ ++unsigned long physical_memsize = 0L; ++ ++#endif ++ ++ ++#if 0 ++static struct prom_pmemblock * __init prom_getmdesc(void) ++{ ++ char *memsize_str; ++ unsigned int memsize; ++ char cmdline[CL_SIZE], *ptr; ++ ++ /* otherwise look in the environment */ ++ memsize_str = prom_getenv("memsize"); ++ if (!memsize_str) { ++ printk(KERN_WARNING ++ "memsize not set in boot prom, set to default (32Mb)\n"); ++ physical_memsize = 0x02000000; ++ } else { ++#ifdef DEBUG ++ pr_debug("prom_memsize = %s\n", memsize_str); ++#endif ++ physical_memsize = simple_strtol(memsize_str, NULL, 0); ++ } ++ ++#ifdef CONFIG_CPU_BIG_ENDIAN ++ /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last ++ word of physical memory */ ++ physical_memsize -= PAGE_SIZE; ++#endif ++ ++ /* Check the command line for a memsize directive that overrides ++ the physical/default amount */ ++ strcpy(cmdline, arcs_cmdline); ++ ptr = strstr(cmdline, "memsize="); ++ if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) ++ ptr = strstr(ptr, " memsize="); ++ ++ if (ptr) ++ memsize = memparse(ptr + 8, &ptr); ++ else ++ memsize = physical_memsize; ++ ++ memset(mdesc, 0, sizeof(mdesc)); ++ ++ mdesc[0].type = yamon_dontuse; ++ mdesc[0].base = 0x00000000; ++ mdesc[0].size = 0x00001000; ++ ++ mdesc[1].type = yamon_prom; ++ mdesc[1].base = 0x00001000; ++ mdesc[1].size = 0x000ef000; ++ ++#ifdef CONFIG_MIPS_MALTA ++ /* ++ * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the ++ * south bridge and PCI access always forwarded to the ISA Bus and ++ * BIOSCS# is always generated. ++ * This mean that this area can't be used as DMA memory for PCI ++ * devices. ++ */ ++ mdesc[2].type = yamon_dontuse; ++ mdesc[2].base = 0x000f0000; ++ mdesc[2].size = 0x00010000; ++#else ++ mdesc[2].type = yamon_prom; ++ mdesc[2].base = 0x000f0000; ++ mdesc[2].size = 0x00010000; ++#endif ++ ++ mdesc[3].type = yamon_dontuse; ++ mdesc[3].base = 0x00100000; ++ mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; ++ ++ mdesc[4].type = yamon_free; ++ mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); ++ mdesc[4].size = memsize - mdesc[4].base; ++ ++ return &mdesc[0]; ++} ++ ++static int __init prom_memtype_classify(unsigned int type) ++{ ++ switch (type) { ++ case yamon_free: ++ return BOOT_MEM_RAM; ++ case yamon_prom: ++ return BOOT_MEM_ROM_DATA; ++ default: ++ return BOOT_MEM_RESERVED; ++ } ++} ++#endif ++ ++ ++ ++//DRAMlen is the length of DRAM mapping area,not the actual length of DRAM ++static unsigned long LXmem=0,LXmem2Size=0,EMACmem=0, DRAMlen=0/*, BBAddr=0*/; ++ ++//static unsigned long G3Dmem0Addr=0, G3Dmem0Len=0, G3Dmem1Addr=0, G3Dmem1Len=0, G3DCmdQAddr=0, G3DCmdQLen=0; ++ ++static unsigned long LXmem3Size=0; ++#if 0 ++static unsigned long GMACmemAddr=0,GMACmemLen=0; ++static unsigned long Miu01_adj=0; ++static char coredump_path[CORENAME_MAX_SIZE]={0}; ++#endif ++ ++#ifdef CONFIG_ARM_LPAE ++static phys_addr_t LXmem3Addr=0,LXmem2Addr=0; ++#else ++static unsigned long LXmem3Addr=0,LXmem2Addr=0; ++#endif ++ ++#if 0 ++#ifdef CONFIG_MSTAR_STR_CRC ++static unsigned int str_crc=0; ++#endif ++#ifdef CONFIG_MP_R2_STR_ENABLE ++static volatile unsigned long R2TEE_STR_HANDSHAKE_addr=0; ++#endif ++#endif ++ ++extern int DTS_DRAM_start; ++ ++ ++#ifdef CONFIG_ARM_LPAE ++ ++ #ifdef CONFIG_ARM_PATCH_PHYS_VIRT ++ phys_addr_t lx_mem_addr = 0xFFFFFFFFUL;//UL(CONFIG_PHYS_OFFSET);//UL(CONFIG_MEMORY_START_ADDRESS); ++ #else ++ phys_addr_t lx_mem_addr = UL(CONFIG_PHYS_OFFSET);//UL(CONFIG_MEMORY_START_ADDRESS); ++ #endif ++phys_addr_t lx_mem2_addr = 0xFFFFFFFFUL; //default setting ++phys_addr_t lx_mem3_addr = 0xFFFFFFFFUL; //default setting ++ ++#else ++ ++ #ifdef CONFIG_ARM_PATCH_PHYS_VIRT ++ unsigned long lx_mem_addr = 0xFFFFFFFFUL;//UL(CONFIG_PHYS_OFFSET);//UL(CONFIG_MEMORY_START_ADDRESS); ++ #else ++ unsigned long lx_mem_addr = UL(CONFIG_PHYS_OFFSET);//UL(CONFIG_MEMORY_START_ADDRESS); ++ #endif ++unsigned long lx_mem2_addr = 0xFFFFFFFFUL; //default setting ++unsigned long lx_mem3_addr = 0xFFFFFFFFUL; //default setting ++#endif ++unsigned long lx_mem_size = 0xFFFFFFFFUL; //default setting ++unsigned long lx_mem2_size = 0xFFFFFFFFUL; //default setting ++unsigned long lx_mem3_size = 0xFFFFFFFFUL; //default setting ++ ++unsigned long lx_mem_left_size = 0xFFFFFFFF; // to avoid overflow in va2pa ++unsigned long lx_mem2_left_size = 0xFFFFFFFF; // to avoid overflow in va2pa ++#if 0 ++unsigned long miu01_adj = 0x0; //default setting ++unsigned long ulPM_GPIO_NUM=0; ++unsigned long ulSD_PAD_NUM=0; ++unsigned long ulSD_CONFIG_NUM=0; ++unsigned long ulSDIO_CONFIG_NUM=0; ++char UTOPIA_MODE[10]; ++int TEEINFO_TYPTE =0; ++#endif ++ ++EXPORT_SYMBOL(lx_mem_addr); ++EXPORT_SYMBOL(lx_mem_size); ++EXPORT_SYMBOL(lx_mem2_addr); ++EXPORT_SYMBOL(lx_mem2_size); ++EXPORT_SYMBOL(lx_mem3_addr); ++EXPORT_SYMBOL(lx_mem3_size); ++ ++EXPORT_SYMBOL(lx_mem_left_size); ++EXPORT_SYMBOL(lx_mem2_left_size); ++#if 0 ++ ++EXPORT_SYMBOL(miu01_adj); ++EXPORT_SYMBOL(ulPM_GPIO_NUM); ++EXPORT_SYMBOL(ulSD_PAD_NUM); ++EXPORT_SYMBOL(ulSD_CONFIG_NUM); ++EXPORT_SYMBOL(ulSDIO_CONFIG_NUM); ++EXPORT_SYMBOL(UTOPIA_MODE); ++EXPORT_SYMBOL(TEEINFO_TYPTE); ++#endif ++ ++ ++#ifdef CONFIG_MP_MM_MALI_RESERVE ++unsigned long mali_reserve_size_miu0 = 0; ++unsigned long mali_reserve_size_miu1 = 0; ++ ++//extern unsigned long mali_reserve_level; ++#endif ++ ++ ++# define NR_BANKS 8 ++ ++struct membank { ++ unsigned long start; ++ unsigned long size; ++ unsigned int highmem; ++}; ++struct meminfo { ++ int nr_banks; ++ struct membank bank[NR_BANKS]; ++}; ++ ++/*extern*/ struct meminfo meminfo; ++#if 0 ++ ++static int SD_CONFIG_NUM_setup(char *str) ++{ ++ printk("SD_CONFIG_NUM = %s\n", str); ++ if( str != NULL ) ++ { ++ sscanf(str,"%ld",&ulSD_CONFIG_NUM); ++ } ++ else ++ { ++ printk("\nSD_CONFIG_NUM not set, and it will be zero.\n"); ++ } ++ return 0; ++} ++ ++ ++static int SDIO_CONFIG_NUM_setup(char *str) ++{ ++ printk("SDIO_CONFIG_NUM = %s\n", str); ++ if( str != NULL ) ++ { ++ sscanf(str,"%ld",&ulSDIO_CONFIG_NUM); ++ } ++ else ++ { ++ printk("\nSDIO_CONFIG_NUM not set, and it will be zero.\n"); ++ } ++ return 0; ++} ++ ++ ++ ++#ifdef CONFIG_ARM_LPAE ++static void __init Check_MIU_BUS(phys_addr_t *addr) ++{ ++ if(*addr>=ARM_MIU1_BASE_L && *addr<(ARM_MIU1_BASE_L+ARM_MIU1_SIZE_L)) ++ *addr = *addr - ARM_MIU1_BASE_L + ARM_MIU1_BASE; ++} ++#endif ++#endif ++#if 0 ++/* User can over-ride above with "mem=nnn[KkMm]" in cmdline */ ++static int __init MEM_setup(char *str) ++{ ++ if( str != NULL ) ++ { ++// sscanf(str,"%lx",&LXmem); ++ LXmem = memparse(str, NULL) & PAGE_MASK; ++ ++ meminfo.nr_banks = 0; ++ lx_mem_size = LXmem; ++ } ++ else ++ { ++ printk("\nLX_MEM not set\n"); ++ } ++ return 0; ++} ++#endif ++static int __init LX_MEM_setup(char *str) ++{ ++ ++ if( str != NULL ) ++ { ++ sscanf(str,"%lx",&LXmem); ++ meminfo.nr_banks = 0; ++ lx_mem_size = LXmem; ++ } ++ else ++ { ++ printk("\nLX_MEM not set\n"); ++ } ++ return 0; ++} ++#if 0 ++static int MIU01_ADJ_setup(char *str) ++{ ++ printk("MIU01_ADJ = %s\n", str); ++ if( str != NULL ) ++ { ++ sscanf(str,"%ld",&Miu01_adj); ++ miu01_adj = Miu01_adj * 1024 * 1024; ++ } ++ else ++ { ++ printk("\nMIU01_ADJ not set, and it will be zero.\n"); ++ } ++ return 0; ++} ++ ++static int PM_GPIO_NUM_setup(char *str) ++{ ++ printk("PM_GPIO_NUM = %s\n", str); ++ if( str != NULL ) ++ { ++ sscanf(str,"%ld",&ulPM_GPIO_NUM); ++ } ++ else ++ { ++ printk("\nPM_GPIO_NUM not set, and it will be zero.\n"); ++ } ++ return 0; ++} ++ ++static int SD_PAD_NUM_setup(char *str) ++{ ++ printk("SD_PAD_NUM_setup = %s\n", str); ++ if( str != NULL ) ++ { ++ sscanf(str,"%ld",&ulSD_PAD_NUM); ++ } ++ else ++ { ++ printk("\nSD_PAD_NUM not set, and it will be zero.\n"); ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_MP_R2_STR_ENABLE ++static int __init R2TEE_STR_ADDR_setup(char *str) ++{ ++ if( str != NULL ) ++ { ++ sscanf(str,"%lx",&R2TEE_STR_HANDSHAKE_addr); ++ printk("\nR2TEE STR handshake_addr = 0x%lx\n",R2TEE_STR_HANDSHAKE_addr); ++ } ++ else ++ { ++ printk("\nR2TEE STR handshake_addr not set\n"); ++ } ++ return 0; ++} ++#endif ++ ++int __init TEE_MODE_INFO_setup(char *cmdline) ++{ ++ ++ if(cmdline == NULL) ++ { ++ printk("Warning: tee_mode setup error\n"); ++ }else ++ { ++ strncpy(UTOPIA_MODE, cmdline, strlen(cmdline)); ++ if(!strcmp(UTOPIA_MODE,"optee")) ++ { ++ TEEINFO_TYPTE = SECURITY_TEEINFO_OSTYPE_OPTEE; ++ } ++ else if(!strcmp(UTOPIA_MODE,"nuttx")) ++ { ++ TEEINFO_TYPTE = SECURITY_TEEINFO_OSTYPE_NUTTX; ++ } ++ else if(!strcmp(UTOPIA_MODE,"secarm")) ++ { ++ TEEINFO_TYPTE = SECURITY_TEEINFO_OSTYPE_SECARM; ++ } ++ else ++ { ++ TEEINFO_TYPTE = SECURITY_TEEINFO_OSTYPE_NOTEE; ++ } ++ } ++ return 0; ++} ++ ++#endif ++ ++ ++ ++static int __init LX_MEM2_setup(char *str) ++{ ++ //printk("LX_MEM2= %s\n", str); ++ if( str != NULL ) ++ { ++#ifdef CONFIG_ARM_LPAE ++ sscanf(str,"%llx,%lx",&LXmem2Addr,&LXmem2Size); ++ Check_MIU_BUS(&LXmem2Addr); ++#else ++ sscanf(str,"%lx,%lx",&LXmem2Addr,&LXmem2Size); ++#endif ++ } ++ else ++ { ++ printk("\nLX_MEM2 not set\n"); ++ } ++ return 0; ++} ++ ++static int __init LX_MEM3_setup(char *str) ++{ ++ //printk("LX_MEM3= %s\n", str); ++ if( str != NULL ) ++ { ++#ifdef CONFIG_ARM_LPAE ++ sscanf(str,"%llx,%lx",&LXmem3Addr,&LXmem3Size); ++ Check_MIU_BUS(&LXmem3Addr); ++#else ++ sscanf(str,"%lx,%lx",&LXmem3Addr,&LXmem3Size); ++#endif ++ } ++ else ++ { ++ printk("\nLX_MEM3 not set\n"); ++ } ++ return 0; ++} ++ ++#if 0 ++static int __init G3D_MEM_setup(char *str) ++{ ++ if( str != NULL ) ++ { ++ sscanf(str,"%lx,%lx,%lx,%lx,%lx,%lx", ++ &G3Dmem0Addr,&G3Dmem0Len,&G3Dmem1Addr,&G3Dmem1Len, ++ &G3DCmdQAddr,&G3DCmdQLen); ++ } ++ else ++ { ++ printk("\nG3D_MEM not set\n"); ++ } ++ return 0; ++} ++ ++ ++ ++ ++ ++static int __init Coredump_setup(char *str) ++{ ++ if( str != NULL) ++ { ++ strncpy(coredump_path, str, CORENAME_MAX_SIZE); ++ } ++ else ++ { ++ printk("depend on core pattern\n"); ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_MSTAR_STR_CRC ++static int __init str_crc_setup(char *str) ++{ ++ if( str != NULL ) ++ { ++ str_crc = simple_strtol(str, NULL, 16); ++ } ++ else ++ { ++ printk("\nstr_crc is disable\n"); ++ } ++ printk("\nstr_crc = %d\n", str_crc); ++ return 0; ++} ++#endif ++ ++ ++#ifdef CONFIG_MP_MM_MALI_RESERVE ++static int MALI_MIU0_RESERVE_setup(char *str) ++{ ++ printk("MALI_RESERVE_IN_MIU0_SIZE = %s\n", str); ++ if( str != NULL ) ++ { ++ int ret = -1; ++ ret = strict_strtol(str,0,&mali_reserve_size_miu0); ++ //mali_reserve_size_miu0 = mali_reserve_size_miu0 *1024 * 1024; ++ } ++ else ++ { ++ printk("\nMALI_RESERVE_IN_MIU0_SIZE not set, and it will be zero.\n"); ++ } ++ //mali_reserve_size_miu0 = 0x6400000; ++ printk("MALI_RESERVE_IN_MIU0_SIZE = %s, mali_reserve_size_miu0 = %lx \n", str,mali_reserve_size_miu0); ++ ++ return 0; ++} ++ ++static int MALI_MIU1_RESERVE_setup(char *str) ++{ ++ if( str != NULL ) ++ { ++ int ret = -1; ++ ret = strict_strtol(str,0,&mali_reserve_size_miu1); ++ printk("ret=%d,mali_reserve_size_miu1 = %ld \n",ret,mali_reserve_size_miu1); ++ ++ //mali_reserve_size_miu1 = mali_reserve_size_miu1 *1024 * 1024; ++ } ++ else ++ { ++ printk("\nMALI_RESERVE_IN_MIU1_SIZE not set, and it will be zero.\n"); ++ } ++ //mali_reserve_size_miu1 = 0x10000000; ++ //mali_reserve_size_miu1 = 0; ++ //mali_reserve_size_miu0 = 0x6400000; ++ printk("MALI_RESERVE_IN_MIU1_SIZE = %s, mali_reserve_size_miu1 = %lx \n", str,mali_reserve_size_miu1); ++ ++ return 0; ++} ++ ++static int MALI_RESERVE_migrate(char *str) ++{ ++ //printk("%s, disable migrate!\n", str); ++ if( str != NULL ) ++ { ++ //int ret = -1; ++ //ret = strict_strtol(str,0,&mali_reserve_level); ++ //printk("mali_reserve_level = %ld \n",mali_reserve_level); ++ } ++ else ++ { ++ printk("MALI_RESERVE_migrate not set, and it will be true.\n"); ++ //mali_reserve_level = 1; ++ } ++ return 0; ++} ++#endif ++#endif ++ ++#if !defined(CONFIG_ARM_PATCH_PHYS_VIRT) ++/* ++ * Pick out the reserved memory size. We look for reserve_mem=size, ++ * where start and size are "size[M]" ++ */ ++ ++#include "registers.h" ++ ++int reserveMemSize = 0; ++int addToSystemRAMSize = 0; ++static int __init early_reserve_mem(char *p) ++{ ++ ++ sscanf(p,"%dM",&reserveMemSize); ++ reserveMemSize *= SZ_1M; // 1 MB alignment ++ addToSystemRAMSize = __pa(PAGE_OFFSET)- MIU0_BASE - reserveMemSize; ++ pr_info("[%s]: reserveMemSize=%#x, addToSystemRAMSize=%#x, \n",__func__, reserveMemSize, addToSystemRAMSize); ++ return 0; ++} ++early_param("reserve_mem", early_reserve_mem); ++#endif ++ ++ ++//early_param("mem", MEM_setup); ++early_param("LX_MEM", LX_MEM_setup); ++early_param("LX_MEM2", LX_MEM2_setup); ++early_param("LX_MEM3", LX_MEM3_setup); ++#if 0 ++early_param("G3D_MEM", G3D_MEM_setup); ++early_param("MIU01_ADJ", MIU01_ADJ_setup); ++early_param("PM_GPIO_NUM", PM_GPIO_NUM_setup); ++early_param("SD_PAD_NUM", SD_PAD_NUM_setup); ++#ifdef CONFIG_MP_R2_STR_ENABLE ++early_param("FSTR", R2TEE_STR_ADDR_setup); ++#endif ++ ++#ifdef CONFIG_MP_MM_MALI_RESERVE ++early_param("MALI_RESERVE_IN_MIU0_SIZE", MALI_MIU0_RESERVE_setup); ++early_param("MALI_RESERVE_IN_MIU1_SIZE", MALI_MIU1_RESERVE_setup); ++early_param("MALI_RESERVE_MIGRATE", MALI_RESERVE_migrate); ++#endif ++early_param("CORE_DUMP_PATH", Coredump_setup); ++#ifdef CONFIG_MSTAR_STR_CRC ++early_param("str_crc", str_crc_setup); ++#endif ++ ++early_param("SD_CONFIG", SD_CONFIG_NUM_setup); ++early_param("SDIO_CONFIG", SDIO_CONFIG_NUM_setup); ++early_param("tee_mode", TEE_MODE_INFO_setup); ++#endif ++ ++ ++static char bUseDefMMAP=0; ++#if 0 ++ ++static void check_boot_mem_info(void) ++{ ++ if( LXmem==0 || EMACmem==0 || DRAMlen==0 ) ++ { ++ bUseDefMMAP = 1; ++ } ++} ++#endif ++#if 0 ++#if defined(CONFIG_MSTAR_OFFSET_FOR_SBOOT) ++#define SBOOT_LINUX_MEM_START 0x00400000 //4M ++#define SBOOT_LINUX_MEM_LEN 0x01400000 //20M ++#define SBOOT_EMAC_MEM_LEN 0x100000 //1M ++#define SBOOT_GMAC_MEM_LEN 0x100000 //1M ++void get_boot_mem_info_sboot(BOOT_MEM_INFO type, phys_addr_t *addr, phys_addr_t *len) ++{ ++ switch (type) ++ { ++ case LINUX_MEM: ++ *addr = SBOOT_LINUX_MEM_START; ++ *len = SBOOT_LINUX_MEM_LEN; ++ break; ++ ++ case EMAC_MEM: ++ *addr = SBOOT_LINUX_MEM_START+SBOOT_LINUX_MEM_LEN; ++ *len = SBOOT_EMAC_MEM_LEN; ++ break; ++ ++ case GMAC_MEM: ++ *addr = SBOOT_LINUX_MEM_START + SBOOT_LINUX_MEM_LEN + SBOOT_EMAC_MEM_LEN; ++ *len = SBOOT_GMAC_MEM_LEN; ++ break; ++ ++ case MPOOL_MEM: ++ *addr = SBOOT_LINUX_MEM_START + SBOOT_LINUX_MEM_LEN + SBOOT_EMAC_MEM_LEN; ++ *len = 256*1024*1024; ++ break; ++ ++ case LINUX_MEM2: ++ *addr = 0; ++ *len = 0; ++ break; ++ ++ case LINUX_MEM3: ++ *addr = 0; ++ *len = 0; ++ break; ++ ++ default: ++ *addr = 0; ++ *len = 0; ++ break; ++ } ++} ++#endif//CONFIG_MSTAR_OFFSET_FOR_SBOOT ++ ++#endif ++ ++void get_boot_mem_info(BOOT_MEM_INFO type, phys_addr_t *addr, phys_addr_t *len) ++{ ++#if defined(CONFIG_MSTAR_OFFSET_FOR_SBOOT) ++ get_boot_mem_info_sboot(type, addr, len); ++ printk("!!!!!!!!!!SBOOT memory type=%x addr=%x, len=%x!!!!!!!!!!\n",type, *addr, *len); ++ return; ++#endif//CONFIG_MSTAR_OFFSET_FOR_SBOOT ++ ++ if (bUseDefMMAP == 0) ++ { ++ switch (type) ++ { ++ case LINUX_MEM: ++ *addr = PHYS_OFFSET; ++ *len = LXmem; ++ break; ++ case EMAC_MEM: ++ *addr = PHYS_OFFSET + LXmem; ++ *len = EMACmem; ++ break; ++#if 0 ++ case MPOOL_MEM: ++ *addr = LINUX_MEM_BASE_ADR + LXmem + EMACmem; ++ *len = DRAMlen - *addr; ++ break; ++#endif ++ case LINUX_MEM2: ++ if (LXmem2Addr!=0 && LXmem2Size!=0) ++ { ++ *addr = LXmem2Addr; ++ *len = LXmem2Size; ++ } ++ else ++ { ++ *addr = 0; ++ *len = 0; ++ } ++ break; ++ case LINUX_MEM3: ++ if (LXmem3Addr!=0 && LXmem3Size!=0) ++ { ++ *addr = LXmem3Addr; ++ *len = LXmem3Size; ++ } ++ else ++ { ++ *addr = 0; ++ *len = 0; ++ } ++ break; ++#if 0 ++ case G3D_MEM0: ++ *addr = G3Dmem0Addr; ++ *len = G3Dmem0Len; ++ break; ++ ++ case G3D_MEM1: ++ *addr = G3Dmem1Addr; ++ *len = G3Dmem1Len; ++ break; ++ case G3D_CMDQ: ++ *addr = G3DCmdQAddr; ++ *len = G3DCmdQLen; ++ break; ++ case DRAM: ++ *addr = 0; ++ *len = DRAMlen; ++ break; ++ case BB: ++ *addr = BBAddr; ++ *len = 0; ++ break; ++ case GMAC_MEM: ++ *addr = GMACmemAddr; ++ *len = GMACmemLen; ++ break; ++#endif ++ default: ++ *addr = 0; ++ *len = 0; ++ break; ++ } ++ } ++ else ++ { ++#if 1 ++ printk("!!!!!!!!!not supported by camera chip!!!!!!!\n"); ++#else ++ switch (type) ++ { ++ case LINUX_MEM: ++ *addr =PHYS_OFFSET; ++ *len = LINUX_MEM_LEN; ++ break; ++ ++ case EMAC_MEM: ++ *addr = EMAC_MEM_ADR; ++ *len = EMAC_MEM_LEN; ++ break; ++ ++ case MPOOL_MEM: ++ *addr = MPOOL_ADR; ++ *len = MPOOL_LEN; ++ break; ++ ++ case LINUX_MEM2: ++ if (LXmem2Addr!=0 && LXmem2Size!=0) ++ { ++ *addr = LXmem2Addr; ++ *len = LXmem2Size; ++ } ++ else ++ { ++ #ifdef LINUX_MEM2_BASE_ADR // reserved miu1 memory for linux ++ *addr = LINUX_MEM2_BASE_ADR; ++ *len = LINUX_MEM2_LEN; ++ #else ++ *addr = 0; ++ *len = 0; ++ #endif ++ } ++ break; ++ case LINUX_MEM3: ++ if (LXmem3Addr!=0 && LXmem3Size!=0) ++ { ++ *addr = LXmem3Addr; ++ *len = LXmem3Size; ++ } ++ else ++ { ++ *addr = 0; ++ *len = 0; ++ } ++ break; ++ case G3D_MEM0: ++ *addr = G3Dmem0Addr; ++ *len = G3Dmem0Len; ++ break; ++ case G3D_MEM1: ++ *addr = G3Dmem1Addr; ++ *len = G3Dmem1Len; ++ break; ++ case G3D_CMDQ: ++ *addr = G3DCmdQAddr; ++ *len = G3DCmdQLen; ++ break; ++ case DRAM: ++ *addr = 0; ++ *len = DRAMlen; ++ break; ++ case BB: ++ *addr = BBAddr; ++ *len = 0; ++ break; ++ case GMAC_MEM: ++ *addr = GMACmemAddr; ++ *len = GMACmemLen; ++ break; ++ default: ++ *addr = 0; ++ *len = 0; ++ break; ++ } ++ ++#endif ++ ++ } ++} ++EXPORT_SYMBOL(get_boot_mem_info); ++#if 0 ++#ifdef CONFIG_CMA ++extern phys_addr_t arm_lowmem_limit; ++void __init dumpMemInfo(unsigned long start, unsigned long size) ++{ ++ unsigned long va_arm_lowmem_limit = __phys_to_virt((unsigned long )(arm_lowmem_limit)); ++ ++ if(start >= va_arm_lowmem_limit) ++ return; ++ ++ if((start+size) > va_arm_lowmem_limit) ++ size = va_arm_lowmem_limit - start; ++ ++ printk(KERN_NOTICE " lowmem : 0x%08lx - 0x%08lx (%6ld kB)\n", ++ start, start+size, (size >> 10)); ++} ++ ++void __init lowMemInfo(void) ++{ ++ if(PHYS_OFFSET != INVALID_PHY_ADDR) ++ dumpMemInfo(PAGE_OFFSET, lx_mem_size); ++ ++ if(lx_mem2_addr != INVALID_PHY_ADDR) ++ dumpMemInfo(PAGE_OFFSET1, lx_mem2_size); ++ ++ if(lx_mem3_addr != INVALID_PHY_ADDR) ++ dumpMemInfo(PAGE_OFFSET2, lx_mem3_size); ++ ++ printk(KERN_NOTICE " va_arm_lowmem_limit : 0x%X\n", (unsigned int)__va(arm_lowmem_limit)); ++} ++#endif ++#endif ++ ++extern int __init arm_add_memory(u64 start, u64 size); ++ ++ ++void __init prom_meminit(void) ++{ ++ ++ phys_addr_t linux_memory_address = 0, linux_memory_length = 0; ++ phys_addr_t linux_memory2_address = 0, linux_memory2_length = 0; ++ phys_addr_t linux_memory3_address = 0, linux_memory3_length = 0; ++ u64 size = 0; ++ u64 start = 0; ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ if(PHYS_OFFSET>MIU0_BASE) ++ { ++ memblock_reserve(MIU0_BASE, PHYS_OFFSET-MIU0_BASE); ++ } ++#endif ++ ++ //check_boot_mem_info(); ++ get_boot_mem_info(LINUX_MEM, &linux_memory_address, &linux_memory_length); ++ get_boot_mem_info(LINUX_MEM2, &linux_memory2_address, &linux_memory2_length); ++ get_boot_mem_info(LINUX_MEM3, &linux_memory3_address, &linux_memory3_length); ++ ++ if ((linux_memory_address | linux_memory_length | linux_memory2_address | linux_memory2_length ++ | linux_memory3_address | linux_memory3_length) & (0x100000-1)) ++ { ++ //printk("[ERR] LX_MEM, LX_MEM2, LX_MEM3 not 1MB aligned\n"); ++ //while(1); can't block it, it will cause printk message not output ++ } ++ ++ /* ++ * if you use cma_buffer, you must ensure having PMD_SIZE alignment ++ */ ++#ifdef CONFIG_CMA ++#ifdef CONFIG_MP_CMA_PATCH_LX_MEMORY_ALIGN_TO_8K_CHECK ++ //align to 8K which is MIU protect unit ++ if ((linux_memory_address | linux_memory_length | linux_memory2_address | linux_memory2_length ++ | linux_memory3_address | linux_memory3_length) & (0x2000-1)) ++ { ++ printk("[ERR] LX_MEM, LX_MEM2, LX_MEM3 not 8K aligned\n"); ++ //while(1); can't block it, it will cause printk message not output ++ } ++#endif ++#endif ++ ++ printk("LXmem is 0x%llx PHYS_OFFSET is 0x%llx\n", (u64)LXmem, (u64)PHYS_OFFSET); ++ ++ if (linux_memory_length != 0) ++ { ++#if defined(CONFIG_OF) ++ /* clear all memblock.memory that DTS declared*/ ++ static int usermem = 0; ++ if (usermem == 0) ++ { ++ usermem = 1; ++ memblock_remove(memblock_start_of_DRAM(), ++ memblock_end_of_DRAM() - memblock_start_of_DRAM()); ++ } ++#endif ++ lx_mem_addr = start = (linux_memory_address > PHYS_OFFSET) ? (linux_memory_address) : (PHYS_OFFSET); ++ lx_mem_size = size = linux_memory_length + linux_memory_address - start; ++ printk("Add mem start 0x%llx size 0x%llx!!!!\n", start, size); ++ arm_add_memory(start, size); ++ } ++ ++ if (linux_memory2_length != 0) ++ { ++ lx_mem2_addr = start = linux_memory2_address; ++ lx_mem2_size = size = linux_memory2_length; ++ printk("Add mem start 0x%llx size 0x%llx!!!!\n", start, size); ++ arm_add_memory(start, size); ++ } ++ ++ if (linux_memory3_length != 0) ++ { ++ lx_mem3_addr = start = linux_memory3_address; ++ lx_mem3_size = size = linux_memory3_length; ++ printk("Add mem start 0x%llx size 0x%llx!!!!\n", start, size); ++ arm_add_memory(start, size); ++ } ++ ++ printk("\n"); ++#ifdef CONFIG_ARM_LPAE ++ printk("LX_MEM = 0x%llx, 0x%llx\n", linux_memory_address,linux_memory_length); ++ printk("LX_MEM2 = 0x%llx, 0x%llx\n",linux_memory2_address, linux_memory2_length); ++ printk("LX_MEM3 = 0x%llx, 0x%llx\n",linux_memory3_address, linux_memory3_length); ++#else ++ printk("LX_MEM = 0x%zx, 0x%zx\n", linux_memory_address,linux_memory_length); ++ printk("LX_MEM2 = 0x%zx, 0x%zx\n",linux_memory2_address, linux_memory2_length); ++ printk("LX_MEM3 = 0x%zx, 0x%zx\n",linux_memory3_address, linux_memory3_length); ++#endif ++ printk("EMAC_LEN= 0x%lX\n", EMACmem); ++ printk("DRAM_LEN= 0x%lX\n", DRAMlen); ++ ++ /* prevent overflow while converting pa to va for linux memory */ ++ if(linux_memory_length > (0xFFFFFFFF - PAGE_OFFSET)) ++ { ++ lx_mem_left_size = 0xFFFFFFFF - PAGE_OFFSET; ++ lx_mem2_left_size = 0; ++ } ++ else ++ { ++ lx_mem_left_size = lx_mem_size; ++ if(linux_memory2_length > (0xFFFFFFFF - PAGE_OFFSET - lx_mem_left_size)) ++ { ++ lx_mem2_left_size = 0xFFFFFFFF - PAGE_OFFSET - lx_mem_left_size; ++ } ++ else ++ { ++ lx_mem2_left_size = lx_mem2_size; ++ } ++ } ++ ++ if(lx_mem_left_size != lx_mem_size) ++ { ++ printk("\033[31mLX_LEFT_MEM_SIZE = 0x%X\033[m\n", (unsigned int)lx_mem_left_size); ++ printk("\033[31mLX2_LEFT_MEM_SIZE = 0x%X\033[m\n", (unsigned int)lx_mem2_left_size); ++ } ++ ++ if(lx_mem2_left_size != lx_mem2_size) ++ { ++ printk("\033[31mLX2_LEFT_MEM_SIZE = 0x%X\033[m\n", (unsigned int)lx_mem2_left_size); ++ } ++} ++ ++ ++char* get_coredump_path(void) ++{ ++ return coredump_path; ++} ++EXPORT_SYMBOL(get_coredump_path); ++#if 0 ++ ++ ++ ++ ++ ++ ++ ++inline unsigned long get_BBAddr(void) ++{ ++ return BBAddr; ++} ++ ++//void __init prom_free_prom_memory(void) ++//{ ++// unsigned long addr; ++// int i; ++// ++// for (i = 0; i < boot_mem_map.nr_map; i++) { ++// if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) ++// continue; ++// ++// addr = boot_mem_map.map[i].addr; ++// free_init_pages("prom memory", ++// addr, addr + boot_mem_map.map[i].size); ++// } ++//} ++ ++char* get_coredump_path(void) ++{ ++ return coredump_path; ++} ++EXPORT_SYMBOL(get_coredump_path); ++#ifdef CONFIG_MSTAR_STR_CRC ++int get_str_crc(void) ++{ ++ return str_crc; ++} ++EXPORT_SYMBOL(get_str_crc); ++#endif ++ ++#ifdef CONFIG_MP_R2_STR_ENABLE ++unsigned long get_str_handshake_addr(void) ++{ ++ return R2TEE_STR_HANDSHAKE_addr; ++} ++EXPORT_SYMBOL(get_str_handshake_addr); ++#endif ++ ++#if (MP_CHECKPT_BOOT == 1) ++#define piu_timer1_cap_low 0x1f006090 ++#define piu_timer1_cap_high 0x1f006094 ++int Mstar_Timer1_GetMs(void) ++{ ++ int timer_value = 0; ++ timer_value = reg_readw(piu_timer1_cap_low); ++ timer_value += (reg_readw(piu_timer1_cap_high) << 16); ++ timer_value = timer_value / 12000; ++ return timer_value; ++} ++#endif // MP_CHECKPT_BOOT ++ ++ ++ ++#ifdef CONFIG_MP_PLATFORM_VERIFY_LX_MEM_ALIGN ++void mstar_lx_mem_alignment_check(void) ++{ ++ phys_addr_t linux_memory_address = 0, linux_memory_length = 0; ++ phys_addr_t linux_memory2_address = 0, linux_memory2_length = 0; ++ phys_addr_t linux_memory3_address = 0, linux_memory3_length = 0; ++ ++ //check_boot_mem_info(); ++ get_boot_mem_info(LINUX_MEM, &linux_memory_address, &linux_memory_length); ++ get_boot_mem_info(LINUX_MEM2, &linux_memory2_address, &linux_memory2_length); ++ get_boot_mem_info(LINUX_MEM3, &linux_memory3_address, &linux_memory3_length); ++ ++ if ((linux_memory_address | linux_memory_length | linux_memory2_address | linux_memory2_length ++ | linux_memory3_address | linux_memory3_length) & (0x100000-1)) ++ { ++ printk("[ERR] LX_MEM, LX_MEM2, LX_MEM3 not 1MB aligned\n"); ++ while(1); ++ } ++} ++#endif //#ifdef CONFIG_MP_PLATFORM_VERIFY_LX_MEM_ALIGN ++ ++#endif ++ +diff --git a/drivers/sstar/cpufreq/Kconfig b/drivers/sstar/cpufreq/Kconfig +new file mode 100755 +index 000000000000..f23a8e640a01 +--- /dev/null ++++ b/drivers/sstar/cpufreq/Kconfig +@@ -0,0 +1,8 @@ ++config MS_CPU_FREQ ++ tristate "Mstar CPU frequency scaling driver" ++ select CPU_FREQ ++ select CPU_FREQ_STAT_DETAILS ++ select CPU_FREQ_GOV_POWERSAVE ++ select CPU_FREQ_GOV_ONDEMAND ++ select CPU_FREQ_GOV_USERSPACE ++ select PM_OPP +\ No newline at end of file +diff --git a/drivers/sstar/cpufreq/Makefile b/drivers/sstar/cpufreq/Makefile +new file mode 100755 +index 000000000000..144c2ac02dec +--- /dev/null ++++ b/drivers/sstar/cpufreq/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++obj-y += $(CONFIG_SSTAR_CHIP_NAME)/cpufreq.o +diff --git a/drivers/sstar/cpufreq/infinity/cpufreq.c b/drivers/sstar/cpufreq/infinity/cpufreq.c +new file mode 100755 +index 000000000000..bb64f869ab7c +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity/cpufreq.c +@@ -0,0 +1,251 @@ ++/* ++* infinity-cpufreq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity/registers.h" ++ ++u8 enable_scaling_voltage = 1; ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++ ++extern void ms_cpuclk_dvfs_disable(void); ++extern int bga_vid_0; ++extern int bga_vid_1; ++extern int qfp_vid_0; ++ ++static int ms_cpufreq_verify(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu) ++ return -EINVAL; ++ ++ cpufreq_verify_within_cpu_limits(policy); ++ return 0; ++} ++ ++static int ms_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++{ ++ struct cpufreq_freqs freqs; ++ int ret; ++ ++ freqs.old = policy->cur; ++ freqs.new = target_freq; ++ ++ if (freqs.old == freqs.new) ++ return 0; ++ ++ cpufreq_freq_transition_begin(policy, &freqs); ++ ret = clk_set_rate(policy->clk, target_freq * 1000); ++ cpufreq_freq_transition_end(policy, &freqs, ret); ++ ++ return ret; ++} ++ ++static ssize_t show_scaling_voltage(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", enable_scaling_voltage); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_scaling_voltage(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ sscanf(buf, "%d", &enable); ++ if(enable) ++ { ++ enable_scaling_voltage=1; ++ pr_info("[CPUFREQ] voltage-scaling ON\n"); ++ } ++ else ++ { ++ enable_scaling_voltage=0; ++ pr_info("[CPUFREQ] voltage-scaling OFF\n"); ++ } ++ return count; ++} ++define_one_global_rw(scaling_voltage); ++ ++unsigned int get_cpufreq_testout(void) ++{ ++ u16 reg_value = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ return reg_value * 48000; ++} ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ freq = (reg_value * 4000)/83333; ++ ++ str += scnprintf(str, end - str, "CPU freq = %d MHz\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ sscanf(buf, "%d", &enable); ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Freq testout On\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++ ++static ssize_t show_vid_gpio_map(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "\nBGA_VID_0=%d, BGA_VID_1=%d, QFP_VID_0=%d\n", bga_vid_0, bga_vid_1, qfp_vid_0); ++ ++ return (str - buf); ++} ++define_one_global_ro(vid_gpio_map); ++ ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int reg, sidd; ++ MS_PACKAGE_TYPE package; ++ ++ package = Chip_Get_Package_Type(); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ ++ policy->min = 400000; ++ policy->max = 800000; ++ policy->cpuinfo.min_freq = 400000; ++ policy->cpuinfo.max_freq = 1000000; ++ policy->cpuinfo.transition_latency = 100000; ++ policy->clk = of_clk_get(of_find_node_by_type(NULL, "cpu"), 0); ++ ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), INREG16(BASE_REG_RIU_PA + (0x1032C0 << 1))); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), INREG16(BASE_REG_RIU_PA + (0x1032C2 << 1))); ++ ++ reg = (INREG16(BASE_REG_EFUSE_PA + REG_ID_06) >> 12) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_07) & 0x3F) << 4); ++ sidd = reg * 20; // sidd = reg / 5 => multiplied by 100 => sidd_100x = reg * 20 ++ if(sidd >= sidd_th_100x) ++ { ++ enable_scaling_voltage=0; ++ pr_info("voltage-scaling OFF\n"); ++ ms_cpuclk_dvfs_disable(); ++ } ++ ++ pr_info("[%s] Current clk=%lu, sidd_100x=%d, th_100x=%d\n", __func__, __clk_get_rate(policy->clk), sidd, sidd_th_100x); ++ ++ return 0; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ if (policy && !IS_ERR(policy->clk)) ++ clk_put(policy->clk); ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = ms_cpufreq_verify, ++ .target = ms_cpufreq_target, ++ .get = cpufreq_generic_get, ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = cpufreq_sysfs_create_file(&scaling_voltage.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&vid_gpio_map.attr); ++ ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/cpufreq/infinity2m/cpufreq.c b/drivers/sstar/cpufreq/infinity2m/cpufreq.c +new file mode 100755 +index 000000000000..4d505131f1ef +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity2m/cpufreq.c +@@ -0,0 +1,367 @@ ++/* ++* infinity2m-cpufreq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++ Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++ ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++static struct device *cpu; ++static struct cpufreq_frequency_table *freq_table; ++int g_sCurrentTemp = 35; ++int g_sCurrentTempThreshLo=40; // T < 40C : VDD = 1.0V ++int g_sCurrentTempThreshHi=60; // T > 60C : VDD= 0.9V ++struct timer_list timer_temp; ++ ++extern int get_core_voltage(void); ++extern void set_core_voltage(VOLTAGE_DEMANDER_E demander, int mV) ++; ++ ++static int ms_cpufreq_target_index(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct cpufreq_freqs freqs; ++ int ret; ++ struct dev_pm_opp *opp; ++ unsigned long new_freq; ++ int opp_voltage_mV; ++ ++ freqs.old = policy->cur; ++ freqs.new = freq_table[index].frequency; ++ new_freq = freqs.new * 1000; ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu, &new_freq); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("[%s] %d not found in OPP\n", __func__, freqs.new); ++ return -EINVAL; ++ } ++ ++ opp_voltage_mV = (dev_pm_opp_get_voltage(opp)? dev_pm_opp_get_voltage(opp)/1000 : 0); ++ rcu_read_unlock(); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if (opp_voltage_mV > get_core_voltage()) ++ { ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ udelay(10); //delay 10us to wait voltage stable (from low to high). ++ ret = clk_set_rate(policy->clk, new_freq); ++ } ++ else ++ { ++ ret = clk_set_rate(policy->clk, new_freq); ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ ++ return ret; ++} ++ ++unsigned int get_cpufreq_testout(void) ++{ ++ u16 reg_value = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ return reg_value * 48000; ++} ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ //freq = (reg_value * 4000)/83333; ++ freq = reg_value * 48000; ++ ++ str += scnprintf(str, end - str, "%d\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Freq testout ON\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ } ++ else ++ { ++ pr_info("[CPUFREQ] Freq testout OFF\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++static ssize_t show_temp_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temp=%d\n", g_sCurrentTemp); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_out); ++ ++ ++static ssize_t show_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshLo); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshLo = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_lo); ++ ++static ssize_t show_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshHi); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshHi = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_hi); ++ ++int g_sEfuseTrimValue = 400; ++static ssize_t show_temp_trim_value(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sEfuseTrimValue); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_trim_value); ++ ++int ms_get_temp(void) ++{ ++ int temp; ++ ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_19, BIT6); //ch7 reference voltage select to 2.0V ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_10, BIT0); //reg_pm_dmy ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_64, BIT10); ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_2F, BIT2); ++ OUTREG16(BASE_REG_PMSAR_PA + REG_ID_00, 0xA20); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT14); ++ temp = INREG16(BASE_REG_PMSAR_PA + REG_ID_46); ++ //GF28LP equation to calculate temperature ++ return (1370 * (g_sEfuseTrimValue - temp) + 25000)/1000; ++} ++EXPORT_SYMBOL(ms_get_temp); ++ ++void monitor_temp_timer_handler(unsigned long value) ++{ ++ g_sCurrentTemp = ms_get_temp(); ++ mod_timer(&timer_temp, jiffies + HZ); ++} ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int ret; ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ ++ policy->clk = devm_clk_get(cpu, 0); ++ if (IS_ERR(policy->clk)) { ++ pr_err("[%s] get cpu clk fail\n", __func__); ++ return PTR_ERR(policy->clk); ++ } ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu, &freq_table); ++ if (ret) { ++ pr_err("[%s] init OPP fail\n", __func__); ++ return ret; ++ } ++ ++ ret = cpufreq_generic_init(policy, freq_table, 100000); ++ if (ret) { ++ pr_err("[%s] init policy fail\n", __func__); ++ goto fail; ++ } ++ ++ // TODO: use operating-points in DTS to control policy max/min range ++ //policy->min = 1000000; ++ //policy->max = 1000000; ++ ++ //create a timer for monitor temperature ++ init_timer(&timer_temp); ++ timer_temp.function = monitor_temp_timer_handler; ++ timer_temp.expires = jiffies + HZ/10; ++ ms_get_temp(); //We will update temperature after Hz/10ms. Drop first value due to one adc need cost 8ch*8.9usec. ++ add_timer(&timer_temp); ++ ++ pr_info("[%s] Current clk=%lu\n", __func__, clk_get_rate(policy->clk)); ++ ++ return ret; ++ ++fail: ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++ return ret; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = cpufreq_generic_frequency_table_verify, ++ .attr = cpufreq_generic_attr, ++ .target_index = ms_cpufreq_target_index, ++ .get = cpufreq_generic_get, ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ cpu = get_cpu_device(0); ++ if (dev_pm_opp_of_add_table(cpu)) { ++ pr_err("[%s] add OPP fail\n", __func__); ++ return -EINVAL; ++ } ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) ++ ret = cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_trim_value.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++#else ++ ret = sysfs_create_file(cpufreq_global_kobject, &cpufreq_testout.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_lo.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_hi.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_trim_value.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_out.attr); ++#endif ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/cpufreq/infinity3/cpufreq.c b/drivers/sstar/cpufreq/infinity3/cpufreq.c +new file mode 100755 +index 000000000000..9a563777e4ea +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity3/cpufreq.c +@@ -0,0 +1,384 @@ ++/* ++* infinity3-cpufreq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity3/registers.h" ++ ++u8 enable_scaling_voltage = 1; ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++extern int g_sCurrentTemp; ++extern int g_sCurrentTempThreshLo; ++extern int g_sCurrentTempThreshHi; ++struct timer_list timer_temp; ++extern int Chip_Get_Package_Type(void); ++ ++extern void ms_cpuclk_dvfs_disable(void); ++extern int vid_0; ++extern int vid_1; ++ ++static int ms_cpufreq_verify(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu) ++ return -EINVAL; ++ ++ cpufreq_verify_within_cpu_limits(policy); ++ return 0; ++} ++ ++static int ms_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++{ ++ struct cpufreq_freqs freqs; ++ int ret; ++ ++ freqs.old = policy->cur; ++ freqs.new = target_freq; ++ ++ if (freqs.old == freqs.new) ++ return 0; ++ ++ cpufreq_freq_transition_begin(policy, &freqs); ++ ret = clk_set_rate(policy->clk, target_freq * 1000); ++ cpufreq_freq_transition_end(policy, &freqs, ret); ++ ++ return ret; ++} ++ ++static ssize_t show_scaling_voltage(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", enable_scaling_voltage); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_scaling_voltage(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ enable_scaling_voltage=1; ++ pr_info("[CPUFREQ] voltage-scaling ON\n"); ++ } ++ else ++ { ++ enable_scaling_voltage=0; ++ pr_info("[CPUFREQ] voltage-scaling OFF\n"); ++ } ++ return count; ++} ++define_one_global_rw(scaling_voltage); ++ ++unsigned int get_cpufreq_testout(void) ++{ ++ u16 reg_value = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ return reg_value * 48000; ++} ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ pr_info("[CPUFREQ] Freq testout ON\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ freq = (reg_value * 4000)/83333; ++ ++ str += scnprintf(str, end - str, "CPU freq = %d MHz\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Freq testout ON\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ }else ++ { ++ pr_info("[CPUFREQ] Freq testout OFF\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++ ++static ssize_t show_vid_gpio_map(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "\nvid_0=%d, vid_1=%d\n", vid_0, vid_1); ++ ++ return (str - buf); ++} ++define_one_global_ro(vid_gpio_map); ++ ++static ssize_t show_temp_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temp=%d\n", g_sCurrentTemp); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_out); ++ ++ ++static ssize_t show_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshLo); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshLo = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_lo); ++ ++static ssize_t show_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshHi); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshHi = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_hi); ++ ++int ms_get_temp(void) ++{ ++ int temp; ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_19, BIT6); //ch7 reference voltage select to 2.0V ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_10, BIT0); //reg_pm_dmy ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_64, BIT10); ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_2F, BIT2); ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT4); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT5); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT9); ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT8); ++ mdelay(1); ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT6); ++ mdelay(1); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT14); ++ temp = INREG16(BASE_REG_PMSAR_PA + REG_ID_46); ++ //GF28LP equation to calculate temperature ++ temp = (1220 * (400 - temp) + 25000)/1000; ++ return temp; ++} ++EXPORT_SYMBOL(ms_get_temp); ++ ++void monitor_temp_timer_handler(unsigned long value) ++{ ++ g_sCurrentTemp = ms_get_temp(); ++ mod_timer(&timer_temp, jiffies + HZ); ++} ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ //int reg, sidd; ++ int package = Chip_Get_Package_Type(); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ if(package >= MS_I3_PACKAGE_EXTENDED) ++ { ++ policy->min = 400000; ++ policy->max = 1000000; ++ ++ } ++ else ++ { ++ policy->min = 400000; ++ policy->max = 800000; ++ } ++ policy->cpuinfo.min_freq = 400000; ++ policy->cpuinfo.max_freq = 1000000; ++ policy->cpuinfo.transition_latency = 100000; ++ policy->clk = of_clk_get(of_find_node_by_type(NULL, "cpu"), 0); ++ ++ /* ++ reg = (INREG16(BASE_REG_EFUSE_PA + REG_ID_06) >> 12) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_07) & 0x3F) << 4); ++ sidd = reg * 20; // sidd = reg / 5 => multiplied by 100 => sidd_100x = reg * 20 ++ if(sidd >= sidd_th_100x) ++ { ++ enable_scaling_voltage=0; ++ pr_info("voltage-scaling OFF\n"); ++ ms_cpuclk_dvfs_disable(); ++ } ++ pr_info("[%s] sidd_100x=%d, th_100x=%d\n", __func__, sidd, sidd_th_100x); ++ */ ++ ++ //create a timer for monitor temperature ++ init_timer(&timer_temp); ++ timer_temp.function = monitor_temp_timer_handler; ++ timer_temp.expires = jiffies + HZ/10; ++ add_timer(&timer_temp); ++ ++ pr_info("[%s] Current clk=%lu\n", __func__, clk_get_rate(policy->clk)); ++ ++ ++ return 0; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ if (policy && !IS_ERR(policy->clk)) ++ clk_put(policy->clk); ++ ++ //delete a timer for monitor temperature ++ del_timer_sync(&timer_temp); ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = ms_cpufreq_verify, ++ .target = ms_cpufreq_target, ++ .get = cpufreq_generic_get, ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) ++ ret = cpufreq_sysfs_create_file(&scaling_voltage.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&vid_gpio_map.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++#else ++ ret = sysfs_create_file(cpufreq_global_kobject, &scaling_voltage.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &cpufreq_testout.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &vid_gpio_map.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_lo.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_hi.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_out.attr); ++#endif ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/cpufreq/infinity5/cpufreq.c b/drivers/sstar/cpufreq/infinity5/cpufreq.c +new file mode 100755 +index 000000000000..ba2bee85f93e +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity5/cpufreq.c +@@ -0,0 +1,488 @@ ++/* ++* infinity5-cpufreq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity5/registers.h" ++#include "vcore_defs.h" ++#ifdef CONFIG_CAM_CLK ++#include "drv_camclk_Api.h" ++#include "camclk.h" ++ ++static void *pCpupll = NULL; ++#endif ++ ++u8 enable_scaling_voltage = 0; ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++extern int g_sCurrentTemp; ++extern int g_sCurrentTempThreshLo; ++extern int g_sCurrentTempThreshHi; ++struct timer_list timer_temp; ++extern int Chip_Get_Package_Type(void); ++ ++extern int vid_0; ++extern int vid_1; ++extern int g_sCurrentVoltageCore; ++extern void set_core_voltage(int vcore); ++void ms_core_voltage_init(void); ++ ++static int ms_cpufreq_verify(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu) ++ return -EINVAL; ++ ++ cpufreq_verify_within_cpu_limits(policy); ++ return 0; ++} ++ ++static int ms_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++{ ++ struct cpufreq_freqs freqs; ++ int ret; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Set_Attribute stCfg = {.eRoundType = CAMCLK_ROUNDRATE_ROUND, ++ .eSetType = CAMCLK_SET_ATTR_RATE}; ++#endif ++ ++ freqs.old = policy->cur; ++ freqs.new = target_freq; ++ ++ if (freqs.old == freqs.new) ++ return 0; ++ ++ if(target_freq >= 1000000) ++ { ++ set_core_voltage(VOLTAGE_CORE_1000); ++ udelay(10); //delay 100us to wait voltage stable (from low to high). ++ } ++ ++ cpufreq_freq_transition_begin(policy, &freqs); ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = target_freq * 1000; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1; ++ } ++#else ++ ret = clk_set_rate(policy->clk, target_freq * 1000); ++#endif ++ cpufreq_freq_transition_end(policy, &freqs, ret); ++ ++ if(target_freq < 1000000) ++ { ++ // voltage scaling adjust after CPU clock changed ++ if((g_sCurrentVoltageCore==VOLTAGE_CORE_1000) && (g_sCurrentTemp>g_sCurrentTempThreshHi)) ++ set_core_voltage(VOLTAGE_CORE_950); ++ if((g_sCurrentVoltageCore==VOLTAGE_CORE_950) && (g_sCurrentTempcpu != 0) ++ return -EINVAL; ++ if(package >= MS_I5_PACKAGE_EXTENDED) ++ { ++ policy->min = 400000; ++ policy->max = 1000000; ++ ++ } ++ else ++ { ++ policy->min = 400000; ++ policy->max = 800000; ++ } ++ policy->cpuinfo.min_freq = 400000; ++ policy->cpuinfo.max_freq = 1200000; ++ policy->cpuinfo.transition_latency = 100000; ++#ifndef CONFIG_CAM_CLK ++ policy->clk = of_clk_get(of_find_node_by_type(NULL, "cpu"), 0); ++#endif ++ ++ /* ++ reg = (INREG16(BASE_REG_EFUSE_PA + REG_ID_06) >> 12) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_07) & 0x3F) << 4); ++ sidd = reg * 20; // sidd = reg / 5 => multiplied by 100 => sidd_100x = reg * 20 ++ if(sidd >= sidd_th_100x) ++ { ++ enable_scaling_voltage=0; ++ pr_info("voltage-scaling OFF\n"); ++ ms_cpuclk_dvfs_disable(); ++ } ++ pr_info("[%s] sidd_100x=%d, th_100x=%d\n", __func__, sidd, sidd_th_100x); ++ */ ++ ++ //create a timer for monitor temperature ++ init_timer(&timer_temp); ++ timer_temp.function = monitor_temp_timer_handler; ++ timer_temp.expires = jiffies + HZ/10; ++ ms_get_temp(); //We will update temperature after Hz/10ms. Drop first value due to one adc need cost 8ch*8.9usec. ++ add_timer(&timer_temp); ++ ++#ifdef CONFIG_CAM_CLK ++ pr_info("[%s] Current clk=%d\n", __func__, ms_cpufreq_get(0)); ++#else ++ pr_info("[%s] Current clk=%lu\n", __func__, clk_get_rate(policy->clk)); ++#endif ++ ++ return 0; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ CamClkUnregister(pCpupll); ++ pCpupll = NULL; ++ } ++#else ++ if (policy && !IS_ERR(policy->clk)) ++ clk_put(policy->clk); ++#endif ++ ++ //delete a timer for monitor temperature ++ del_timer_sync(&timer_temp); ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = ms_cpufreq_verify, ++ .target = ms_cpufreq_target, ++#ifdef CONFIG_CAM_CLK ++ .get = ms_cpufreq_get, ++#else ++ .get = cpufreq_generic_get, ++#endif ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++#ifdef CONFIG_CAM_CLK ++ u32 clk_id = 0; ++ ++ ms_core_voltage_init(); ++ ++ of_property_read_u32_index(pdev->dev.of_node, "camclk", 0, &clk_id); ++ if (!clk_id) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("CPUPLL", clk_id, &pCpupll); ++ } ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) ++ ret = cpufreq_sysfs_create_file(&scaling_voltage.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&vid_gpio_map.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++ ret |= cpufreq_sysfs_create_file(&core_voltage.attr); ++#else ++ ret = sysfs_create_file(cpufreq_global_kobject, &scaling_voltage.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &cpufreq_testout.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &vid_gpio_map.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_lo.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_hi.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_out.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &core_voltage.attr); ++#endif ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/cpufreq/infinity6/cpufreq.c b/drivers/sstar/cpufreq/infinity6/cpufreq.c +new file mode 100755 +index 000000000000..0c49b7fbbce7 +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity6/cpufreq.c +@@ -0,0 +1,513 @@ ++/* ++* infinity6-cpufreq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++#ifdef CONFIG_CAM_CLK ++#include "drv_camclk_Api.h" ++#include "camclk.h" ++ ++void *pCpupll = NULL; ++#endif ++ ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++static struct device *cpu; ++static struct cpufreq_frequency_table *freq_table; ++int g_sCurrentTemp = 35; ++/* Please confirm the high and low temperature thresholds applicable to each chip with CAE, and ++ ensure that the tsensor formula(ms_get_temp) has been corrected for the chip */ ++static int g_sCurrentTempThreshLo = 10; ++static int g_sCurrentTempThreshHi = 30; ++struct timer_list timer_temp; ++ ++#ifndef CONFIG_CAM_CLK ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv); ++#endif ++ ++static int ms_cpufreq_target_index(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct cpufreq_freqs freqs; ++ int ret = -1; ++ struct dev_pm_opp *opp; ++ unsigned long new_freq; ++ int opp_voltage_mV; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Set_Attribute stCfg = {.eRoundType = CAMCLK_ROUNDRATE_ROUND, ++ .eSetType = CAMCLK_SET_ATTR_RATE}; ++#endif ++ ++ freqs.old = policy->cur; ++ freqs.new = freq_table[index].frequency; ++ new_freq = freqs.new * 1000; ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu, &new_freq); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("[%s] %d not found in OPP\n", __func__, freqs.new); ++ return -EINVAL; ++ } ++ rcu_read_unlock(); ++ ++ opp_voltage_mV = (dev_pm_opp_get_voltage(opp)? dev_pm_opp_get_voltage(opp)/1000 : 0); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if (opp_voltage_mV > get_core_voltage()) ++ { ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ udelay(10); //delay 10us to wait voltage stable (from low to high). ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = new_freq; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1;; ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ } ++ else ++ { ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = new_freq; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1; ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ ++ return ret; ++} ++ ++#ifdef CONFIG_CAM_CLK ++static unsigned int ms_cpufreq_get(unsigned int cpu) ++{ ++ CAMCLK_Get_Attribute stCfg = {0}; ++ ++ if (pCpupll) ++ { ++ CamClkAttrGet(pCpupll, &stCfg); ++ } ++ ++ return stCfg.u32Rate / 1000; ++} ++#endif ++ ++unsigned int get_cpufreq_testout(void) ++{ ++ u16 reg_value = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ return reg_value * 48000; ++} ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ //freq = (reg_value * 4000)/83333; ++ freq = reg_value * 48000; ++ ++ str += scnprintf(str, end - str, "%d\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Freq testout ON\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ } ++ else ++ { ++ pr_info("[CPUFREQ] Freq testout OFF\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++static ssize_t show_cpufreq_force(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_force(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 rate; ++ CAMCLK_Set_Attribute stCfg = {.eRoundType = CAMCLK_ROUNDRATE_ROUND, ++ .eSetType = CAMCLK_SET_ATTR_RATE}; ++ ++ if (sscanf(buf, "%d", &rate)<=0) ++ return 0; ++ ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = rate; ++ CamClkAttrSet(pCpupll, &stCfg); ++ } ++#else ++ u32 rate; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ if (sscanf(buf, "%d", &rate)<=0) ++ return 0; ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++#endif ++ ++ return count; ++} ++define_one_global_rw(cpufreq_force); ++ ++static ssize_t show_temp_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temp=%d\n", g_sCurrentTemp); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_out); ++ ++ ++static ssize_t show_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshLo); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshLo = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_lo); ++ ++static ssize_t show_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshHi); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshHi = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_hi); ++ ++int ms_get_temp(void) ++{ ++ int vbe_code_ft; ++ int vbe_code; ++ ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_19, BIT6); //ch7 reference voltage select to 2.0V ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_10, BIT0); //reg_pm_dmy ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_64, BIT10); ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_2F, BIT2); ++ OUTREG16(BASE_REG_PMSAR_PA + REG_ID_00, 0xA20); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT14); ++ vbe_code = INREG16(BASE_REG_PMSAR_PA + REG_ID_46); ++ CLRREG16(BASE_REG_EFUSE_PA + REG_ID_03, BIT8); // read subbank 2,3 ++ vbe_code_ft = INREGMSK16(BASE_REG_EFUSE_PA + REG_ID_09, 0x3FF); ++ ++ if (vbe_code_ft == 0) // if no trim info ++ vbe_code_ft = 400; ++ ++ //GF28LP equation to calculate temperature ++ return (1270 * (vbe_code_ft - vbe_code) + 29000)/1000; ++} ++EXPORT_SYMBOL(ms_get_temp); ++ ++static int monitor_temp_thread_handler(void *data) ++{ ++ while (!kthread_should_stop()) ++ { ++ msleep_interruptible(1000); ++ ++ g_sCurrentTemp = ms_get_temp(); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if(get_core_voltage() > VOLTAGE_CORE_900 && g_sCurrentTemp > g_sCurrentTempThreshHi ) ++ set_core_voltage(VOLTAGE_DEMANDER_TEMPERATURE, VOLTAGE_CORE_900); ++ if(get_core_voltage() < VOLTAGE_CORE_1000 && g_sCurrentTemp < g_sCurrentTempThreshLo ) ++ set_core_voltage(VOLTAGE_DEMANDER_TEMPERATURE, VOLTAGE_CORE_1000); ++#endif ++ } ++ ++ return 0; ++} ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int ret; ++ struct task_struct *thr = NULL; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Get_Attribute stCfg = {0}; ++#endif ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ ++#ifndef CONFIG_CAM_CLK ++ policy->clk = devm_clk_get(cpu, 0); ++ if (IS_ERR(policy->clk)) { ++ pr_err("[%s] get cpu clk fail\n", __func__); ++ return PTR_ERR(policy->clk); ++ } ++#endif ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu, &freq_table); ++ if (ret) { ++ pr_err("[%s] init OPP fail\n", __func__); ++ return ret; ++ } ++ ++ ret = cpufreq_generic_init(policy, freq_table, 100000); ++ if (ret) { ++ pr_err("[%s] init policy fail\n", __func__); ++ goto fail; ++ } ++ ++ policy->min = 800000; ++ policy->max = 800000; ++ ++ //create a thread for monitor temperature ++ ms_get_temp(); //We will update temperature after 1sec. Drop first value due to one adc need cost 8ch*8.9usec. ++ thr = kthread_run(monitor_temp_thread_handler, NULL, "monitor_temp"); ++ if (!thr) { ++ pr_info("kthread_run fail"); ++ } ++ ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ CamClkAttrGet(pCpupll, &stCfg); ++ } ++ pr_info("[%s] Current clk=%u\n", __func__, stCfg.u32Rate); ++#else ++ pr_info("[%s] Current clk=%lu\n", __func__, clk_get_rate(policy->clk)); ++#endif ++ ++ return ret; ++ ++fail: ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++ return ret; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++#ifdef CONFIG_CAM_CLK ++ CamClkUnregister(pCpupll); ++ pCpupll = NULL; ++#endif ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = cpufreq_generic_frequency_table_verify, ++ .attr = cpufreq_generic_attr, ++ .target_index = ms_cpufreq_target_index, ++#ifdef CONFIG_CAM_CLK ++ .get = ms_cpufreq_get, ++#else ++ .get = cpufreq_generic_get, ++#endif ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++#ifdef CONFIG_CAM_CLK ++ u32 clk_id = 0; ++ ++ of_property_read_u32_index(pdev->dev.of_node, "camclk", 0, &clk_id); ++ if (!clk_id) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("CPUPLL", clk_id, &pCpupll); ++ } ++#endif ++ ++ cpu = get_cpu_device(0); ++ if (dev_pm_opp_of_add_table(cpu)) { ++ pr_err("[%s] add OPP fail\n", __func__); ++ return -EINVAL; ++ } ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) ++ ret = cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_force.attr); ++#else ++ ret = sysfs_create_file(cpufreq_global_kobject, &cpufreq_testout.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_lo.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_hi.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_out.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &cpufreq_force.attr); ++#endif ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/cpufreq/infinity6b0/cpufreq.c b/drivers/sstar/cpufreq/infinity6b0/cpufreq.c +new file mode 100755 +index 000000000000..69ddade8e3aa +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity6b0/cpufreq.c +@@ -0,0 +1,513 @@ ++/* ++* infinity6-cpufreq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++#ifdef CONFIG_CAM_CLK ++#include "drv_camclk_Api.h" ++#include "camclk.h" ++ ++void *pCpupll = NULL; ++#endif ++ ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++static struct device *cpu; ++static struct cpufreq_frequency_table *freq_table; ++int g_sCurrentTemp = 35; ++/* Please confirm the high and low temperature thresholds applicable to each chip with CAE, and ++ ensure that the tsensor formula(ms_get_temp) has been corrected for the chip */ ++static int g_sCurrentTempThreshLo = 10; ++static int g_sCurrentTempThreshHi = 30; ++struct timer_list timer_temp; ++ ++#ifndef CONFIG_CAM_CLK ++void cpu_dvfs(U32 u32TargetLpf, U32 u32TargetPostDiv); ++#endif ++ ++static int ms_cpufreq_target_index(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct cpufreq_freqs freqs; ++ int ret = -1; ++ struct dev_pm_opp *opp; ++ unsigned long new_freq; ++ int opp_voltage_mV; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Set_Attribute stCfg = {.eRoundType = CAMCLK_ROUNDRATE_ROUND, ++ .eSetType = CAMCLK_SET_ATTR_RATE}; ++#endif ++ ++ freqs.old = policy->cur; ++ freqs.new = freq_table[index].frequency; ++ new_freq = freqs.new * 1000; ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu, &new_freq); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("[%s] %d not found in OPP\n", __func__, freqs.new); ++ return -EINVAL; ++ } ++ ++ opp_voltage_mV = (dev_pm_opp_get_voltage(opp)? dev_pm_opp_get_voltage(opp)/1000 : 0); ++ rcu_read_unlock(); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if (opp_voltage_mV > get_core_voltage()) ++ { ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ udelay(10); //delay 10us to wait voltage stable (from low to high). ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = new_freq; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1;; ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ } ++ else ++ { ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = new_freq; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1; ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ ++ return ret; ++} ++ ++#ifdef CONFIG_CAM_CLK ++static unsigned int ms_cpufreq_get(unsigned int cpu) ++{ ++ CAMCLK_Get_Attribute stCfg = {0}; ++ ++ if (pCpupll) ++ { ++ CamClkAttrGet(pCpupll, &stCfg); ++ } ++ ++ return stCfg.u32Rate / 1000; ++} ++#endif ++ ++unsigned int get_cpufreq_testout(void) ++{ ++ u16 reg_value = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ return reg_value * 48000; ++} ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ //freq = (reg_value * 4000)/83333; ++ freq = reg_value * 48000; ++ ++ str += scnprintf(str, end - str, "%d\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Freq testout ON\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ } ++ else ++ { ++ pr_info("[CPUFREQ] Freq testout OFF\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++static ssize_t show_cpufreq_force(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_force(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 rate; ++ CAMCLK_Set_Attribute stCfg = {.eRoundType = CAMCLK_ROUNDRATE_ROUND, ++ .eSetType = CAMCLK_SET_ATTR_RATE}; ++ ++ if (sscanf(buf, "%d", &rate)<=0) ++ return 0; ++ ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = rate; ++ CamClkAttrSet(pCpupll, &stCfg); ++ } ++#else ++ u32 rate; ++ unsigned int lpf_value; ++ unsigned int post_div = 2; ++ ++ if (sscanf(buf, "%d", &rate)<=0) ++ return 0; ++ ++ /* ++ * The default of post_div is 2, choose appropriate post_div by CPU clock. ++ */ ++ if (rate >= 800000000) ++ post_div = 2; ++ else if (rate >= 400000000) ++ post_div = 4; ++ else if (rate >= 200000000) ++ post_div = 8; ++ else ++ post_div = 16; ++ ++ /* ++ * Calculate LPF value for DFS ++ * LPF_value(5.19) = (432MHz / Ref_clk) * 2^19 => it's for post_div=2 ++ * Ref_clk = CPU_CLK * 2 / 32 ++ */ ++ ++ lpf_value = (U32)(div64_u64(432000000llu * 524288, (rate*2/32) * post_div / 2)); ++ ++ cpu_dvfs(lpf_value, post_div); ++#endif ++ ++ return count; ++} ++define_one_global_rw(cpufreq_force); ++ ++static ssize_t show_temp_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temp=%d\n", g_sCurrentTemp); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_out); ++ ++ ++static ssize_t show_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshLo); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshLo = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_lo); ++ ++static ssize_t show_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshHi); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshHi = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_hi); ++ ++int ms_get_temp(void) ++{ ++ int vbe_code_ft; ++ int vbe_code; ++ ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_19, BIT6); //ch7 reference voltage select to 2.0V ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_10, BIT0); //reg_pm_dmy ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_64, BIT10); ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_2F, BIT2); ++ OUTREG16(BASE_REG_PMSAR_PA + REG_ID_00, 0xA20); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT14); ++ vbe_code = INREG16(BASE_REG_PMSAR_PA + REG_ID_46); ++ CLRREG16(BASE_REG_EFUSE_PA + REG_ID_03, BIT8); // read subbank 2,3 ++ vbe_code_ft = INREGMSK16(BASE_REG_EFUSE_PA + REG_ID_09, 0x3FF); ++ ++ if (vbe_code_ft == 0) // if no trim info ++ vbe_code_ft = 400; ++ ++ //GF28LP equation to calculate temperature ++ return (1270 * (vbe_code_ft - vbe_code) + 29000)/1000; ++} ++EXPORT_SYMBOL(ms_get_temp); ++ ++static int monitor_temp_thread_handler(void *data) ++{ ++ while (!kthread_should_stop()) ++ { ++ msleep_interruptible(1000); ++ ++ g_sCurrentTemp = ms_get_temp(); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if(get_core_voltage() > VOLTAGE_CORE_900 && g_sCurrentTemp > g_sCurrentTempThreshHi ) ++ set_core_voltage(VOLTAGE_DEMANDER_TEMPERATURE, VOLTAGE_CORE_900); ++ if(get_core_voltage() < VOLTAGE_CORE_1000 && g_sCurrentTemp < g_sCurrentTempThreshLo ) ++ set_core_voltage(VOLTAGE_DEMANDER_TEMPERATURE, VOLTAGE_CORE_1000); ++#endif ++ } ++ ++ return 0; ++} ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int ret; ++ struct task_struct *thr = NULL; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Get_Attribute stCfg = {0}; ++#endif ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ ++#ifndef CONFIG_CAM_CLK ++ policy->clk = devm_clk_get(cpu, 0); ++ if (IS_ERR(policy->clk)) { ++ pr_err("[%s] get cpu clk fail\n", __func__); ++ return PTR_ERR(policy->clk); ++ } ++#endif ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu, &freq_table); ++ if (ret) { ++ pr_err("[%s] init OPP fail\n", __func__); ++ return ret; ++ } ++ ++ ret = cpufreq_generic_init(policy, freq_table, 100000); ++ if (ret) { ++ pr_err("[%s] init policy fail\n", __func__); ++ goto fail; ++ } ++ ++ policy->min = 800000; ++ policy->max = 800000; ++ ++ //create a thread for monitor temperature ++ ms_get_temp(); //We will update temperature after 1sec. Drop first value due to one adc need cost 8ch*8.9usec. ++ thr = kthread_run(monitor_temp_thread_handler, NULL, "monitor_temp"); ++ if (!thr) { ++ pr_info("kthread_run fail"); ++ } ++ ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ CamClkAttrGet(pCpupll, &stCfg); ++ } ++ pr_info("[%s] Current clk=%u\n", __func__, stCfg.u32Rate); ++#else ++ pr_info("[%s] Current clk=%lu\n", __func__, clk_get_rate(policy->clk)); ++#endif ++ ++ return ret; ++ ++fail: ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++ return ret; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++#ifdef CONFIG_CAM_CLK ++ CamClkUnregister(pCpupll); ++ pCpupll = NULL; ++#endif ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = cpufreq_generic_frequency_table_verify, ++ .attr = cpufreq_generic_attr, ++ .target_index = ms_cpufreq_target_index, ++#ifdef CONFIG_CAM_CLK ++ .get = ms_cpufreq_get, ++#else ++ .get = cpufreq_generic_get, ++#endif ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++#ifdef CONFIG_CAM_CLK ++ u32 clk_id = 0; ++ ++ of_property_read_u32_index(pdev->dev.of_node, "camclk", 0, &clk_id); ++ if (!clk_id) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("CPUPLL", clk_id, &pCpupll); ++ } ++#endif ++ ++ cpu = get_cpu_device(0); ++ if (dev_pm_opp_of_add_table(cpu)) { ++ pr_err("[%s] add OPP fail\n", __func__); ++ return -EINVAL; ++ } ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) ++ ret = cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_force.attr); ++#else ++ ret = sysfs_create_file(cpufreq_global_kobject, &cpufreq_testout.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_lo.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_hi.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_out.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &cpufreq_force.attr); ++#endif ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/cpufreq/infinity6e/cpufreq.c b/drivers/sstar/cpufreq/infinity6e/cpufreq.c +new file mode 100755 +index 000000000000..29dee9f7b181 +--- /dev/null ++++ b/drivers/sstar/cpufreq/infinity6e/cpufreq.c +@@ -0,0 +1,501 @@ ++/* ++* cpufreq.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "voltage_ctrl.h" ++#ifdef CONFIG_CAM_CLK ++#include "drv_camclk_Api.h" ++#include "camclk.h" ++ ++void *pCpupll = NULL; ++#endif ++ ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++static struct device *cpu; ++static struct cpufreq_frequency_table *freq_table; ++int g_sCurrentTemp = 35; ++static int g_sCurrentTempThreshLo = 40; ++static int g_sCurrentTempThreshHi = 60; ++struct timer_list timer_temp; ++static int g_SIDD = 0; ++static int g_OSC = 0; ++static int g_OSCThreshold = 468; ++static int g_VID_enable = 0; //QFN don't need to enale vid flow. Only BGA1/BGA2 support. ++static int ms_cpufreq_target_index(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct cpufreq_freqs freqs; ++ int ret = -1; ++ struct dev_pm_opp *opp; ++ unsigned long new_freq; ++ int opp_voltage_mV; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Set_Attribute stCfg = {.eRoundType = CAMCLK_ROUNDRATE_ROUND, ++ .eSetType = CAMCLK_SET_ATTR_RATE}; ++#endif ++ ++ freqs.old = policy->cur; ++ freqs.new = freq_table[index].frequency; ++ new_freq = freqs.new * 1000; ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu, &new_freq); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("[%s] %d not found in OPP\n", __func__, freqs.new); ++ return -EINVAL; ++ } ++ opp_voltage_mV = (dev_pm_opp_get_voltage(opp)? dev_pm_opp_get_voltage(opp)/1000 : 0); ++ rcu_read_unlock(); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if (opp_voltage_mV > get_core_voltage()) ++ { ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ udelay(10); //delay 10us to wait voltage stable (from low to high). ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = new_freq; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1;; ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ } ++ else ++ { ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ stCfg.attribute.u32Rate = new_freq; ++ ret = (CamClkAttrSet(pCpupll, &stCfg) == CAMCLK_RET_OK)? 0 : -1;; ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ set_core_voltage(VOLTAGE_DEMANDER_CPUFREQ, opp_voltage_mV); ++ } ++#else ++ ret = clk_set_rate(policy->clk, new_freq); ++#endif ++ ++ return ret; ++} ++ ++#ifdef CONFIG_CAM_CLK ++static unsigned int ms_cpufreq_get(unsigned int cpu) ++{ ++ CAMCLK_Get_Attribute stCfg = {0}; ++ ++ if (pCpupll) ++ { ++ CamClkAttrGet(pCpupll, &stCfg); ++ } ++ ++ return stCfg.u32Rate / 1000; ++} ++#endif ++ ++unsigned int get_cpufreq_testout(void) ++{ ++ u16 reg_value = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ return reg_value * 48000; ++} ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ //freq = (reg_value * 4000)/83333; ++ freq = reg_value * 48000; ++ ++ str += scnprintf(str, end - str, "%d\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Freq testout ON\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ } ++ else ++ { ++ pr_info("[CPUFREQ] Freq testout OFF\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++static ssize_t show_temp_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temp=%d\n", g_sCurrentTemp); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_out); ++ ++ ++static ssize_t show_sidd_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_SIDD); ++ ++ return (str - buf); ++} ++define_one_global_ro(sidd_out); ++ ++static ssize_t show_osc_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_OSC); ++ ++ return (str - buf); ++} ++define_one_global_ro(osc_out); ++ ++static ssize_t show_osc_threshold(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_OSCThreshold); ++ ++ return (str - buf); ++} ++define_one_global_ro(osc_threshold); ++ ++ ++static ssize_t show_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshLo); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshLo = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_lo); ++ ++static ssize_t show_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshHi); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshHi = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_hi); ++ ++int ms_get_temp(void) ++{ ++ int vbe_code_ft; ++ int vbe_code; ++ ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_19, BIT6); //ch7 reference voltage select to 2.0V ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_10, BIT0); //reg_pm_dmy ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_64, BIT10); ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_2F, BIT2); ++ OUTREG16(BASE_REG_PMSAR_PA + REG_ID_00, 0xA20); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT14); ++ vbe_code = INREG16(BASE_REG_PMSAR_PA + REG_ID_46); ++ vbe_code_ft = (INREG16(BASE_REG_OTP_PA + REG_ID_59)>>6) & 0x3FF; //read bit[15:6] ++ ++ if (vbe_code_ft == 0) // if no trim info ++ vbe_code_ft = 400; ++ ++ //calculate temperature ++ return (1370 * (vbe_code_ft - vbe_code))/1000 + 27; //25->27 ++} ++EXPORT_SYMBOL(ms_get_temp); ++ ++static int monitor_temp_thread_handler(void *data) ++{ ++ int resync = 0; ++ ++ while (!kthread_should_stop()) ++ { ++ msleep_interruptible(1000); ++ ++ g_sCurrentTemp = ms_get_temp(); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL ++ if (g_VID_enable) ++ { ++ if(g_OSC >= g_OSCThreshold && g_sCurrentTemp > g_sCurrentTempThreshHi) ++ { ++ resync = sync_core_voltage_with_OSC_and_TEMP(0); ++ if (resync) ++ set_core_voltage(VOLTAGE_DEMANDER_TEMPERATURE, 0); ++ } ++ if(g_OSC >= g_OSCThreshold && g_sCurrentTemp < g_sCurrentTempThreshLo) ++ { ++ resync = sync_core_voltage_with_OSC_and_TEMP(1); ++ if (resync) ++ set_core_voltage(VOLTAGE_DEMANDER_TEMPERATURE, 0); ++ } ++ } ++#endif ++ } ++ ++ return 0; ++} ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int ret; ++ struct task_struct *thr = NULL; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Get_Attribute stCfg = {0}; ++#endif ++ ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ ++#ifndef CONFIG_CAM_CLK ++ policy->clk = devm_clk_get(cpu, 0); ++ if (IS_ERR(policy->clk)) { ++ pr_err("[%s] get cpu clk fail\n", __func__); ++ return PTR_ERR(policy->clk); ++ } ++#endif ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu, &freq_table); ++ if (ret) { ++ pr_err("[%s] init OPP fail\n", __func__); ++ return ret; ++ } ++ ++ ret = cpufreq_generic_init(policy, freq_table, 100000); ++ if (ret) { ++ pr_err("[%s] init policy fail\n", __func__); ++ goto fail; ++ } ++ ++ policy->min = 800000; ++ policy->max = 800000; ++ ++ g_SIDD = INREG16(BASE_REG_OTP_PA + REG_ID_42) & 0x3FF; //read bit[9:0] ++ g_OSC = INREG16(BASE_REG_OTP_PA + REG_ID_43) & 0x3FF; //read bit[9:0] ++ g_VID_enable = 1;//(INREG16(BASE_REG_CHIPTOP_PA + REG_ID_48) & (BIT5))>>5; //Only BGA1/2 need to enable VID flow ++ ++ //create a thread for monitor temperature ++ ms_get_temp(); //We will update temperature after 1sec. Drop first value due to one adc need cost 8ch*8.9usec. ++ thr = kthread_run(monitor_temp_thread_handler, NULL, "monitor_temp"); ++ if (!thr) { ++ pr_info("kthread_run fail"); ++ } ++ ++#ifdef CONFIG_CAM_CLK ++ if (pCpupll) ++ { ++ CamClkAttrGet(pCpupll, &stCfg); ++ } ++ pr_info("[%s] Current clk=%u\n", __func__, stCfg.u32Rate); ++#else ++ pr_info("[%s] Current clk=%lu\n", __func__, clk_get_rate(policy->clk)); ++#endif ++ return ret; ++ ++fail: ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++ ++ return ret; ++} ++ ++static int ms_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ dev_pm_opp_free_cpufreq_table(cpu, &freq_table); ++#ifdef CONFIG_CAM_CLK ++ CamClkUnregister(pCpupll); ++ pCpupll = NULL; ++#endif ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = cpufreq_generic_frequency_table_verify, ++ .attr = cpufreq_generic_attr, ++ .target_index = ms_cpufreq_target_index, ++#ifdef CONFIG_CAM_CLK ++ .get = ms_cpufreq_get, ++#else ++ .get = cpufreq_generic_get, ++#endif ++ .init = ms_cpufreq_init, ++ .exit = ms_cpufreq_exit, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++#ifdef CONFIG_CAM_CLK ++ u32 clk_id = 0; ++ ++ of_property_read_u32_index(pdev->dev.of_node, "camclk", 0, &clk_id); ++ if (!clk_id) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("CPUPLL", clk_id, &pCpupll); ++ } ++#endif ++ ++ cpu = get_cpu_device(0); ++ if (dev_pm_opp_of_add_table(cpu)) { ++ pr_err("[%s] add OPP fail\n", __func__); ++ return -EINVAL; ++ } ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) ++ ret = cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++ ret |= cpufreq_sysfs_create_file(&sidd_out.attr); ++ ret |= cpufreq_sysfs_create_file(&osc_out.attr); ++ ret |= cpufreq_sysfs_create_file(&osc_threshold.attr); ++#else ++ ret = sysfs_create_file(cpufreq_global_kobject, &cpufreq_testout.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_lo.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_adjust_threshold_hi.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &temp_out.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &sidd_out.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &osc_out.attr); ++ ret |= sysfs_create_file(cpufreq_global_kobject, &osc_threshold.attr); ++#endif ++ ++ if (ret) ++ { ++ pr_err("[%s] create file fail\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "sstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/sstar/crypto/Kconfig b/drivers/sstar/crypto/Kconfig +new file mode 100755 +index 000000000000..ee36519e1fca +--- /dev/null ++++ b/drivers/sstar/crypto/Kconfig +@@ -0,0 +1,32 @@ ++config MS_CRYPTO ++ tristate "Crypto driver" ++ select CRYPTO_AES ++ select CRYPTO_ECB ++ select CRYPTO_CBC ++ select CRYPTO_SHA256 ++ select CRYPTO_CTR ++ select CRYPTO_ALGAPI ++ ++---help--- ++ Say 'Y' here to use the sstar AES engine ++ for the CryptoAPI AES algorithm. ++ To compile this driver as a module, choose M here: the module ++ ++ ++config SS_AESDMA_INTR ++depends on MS_CRYPTO ++bool "Enable AES DMA interrupt" ++default n ++help ++ Support interrupt mode for AES operations ++ ++config SS_RNG ++ bool "HW_RANDOM Random Number Generator support" ++ select HW_RANDOM ++ depends on MS_CRYPTO ++ ++config CRYPTODEV ++tristate "Support cryptodev" ++default m ++help ++ Support \dev\crypto +diff --git a/drivers/sstar/crypto/Makefile b/drivers/sstar/crypto/Makefile +new file mode 100755 +index 000000000000..4911cca7a4b7 +--- /dev/null ++++ b/drivers/sstar/crypto/Makefile +@@ -0,0 +1,17 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++obj-$(CONFIG_MS_CRYPTO) += mdrv_crypto.o ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/crypto ++EXTRA_CFLAGS += -Idrivers/sstar/crypto/hal/$(CONFIG_SSTAR_CHIP_NAME) ++ ++mdrv_crypto-objs := mdrv_aes.o \ ++ mdrv_sha.o \ ++ mdrv_rsa.o \ ++ mdrv_cipher.o \ ++ halAESDMA.o ++ ++obj-$(CONFIG_CRYPTODEV) += cryptodev/ ++obj-$(CONFIG_SS_RNG) += char/hw_random/ +\ No newline at end of file +diff --git a/drivers/sstar/crypto/char/hw_random/Makefile b/drivers/sstar/crypto/char/hw_random/Makefile +new file mode 100755 +index 000000000000..d344fca4de42 +--- /dev/null ++++ b/drivers/sstar/crypto/char/hw_random/Makefile +@@ -0,0 +1,10 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++obj-y += mdrv_RNG.o ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/crypto ++EXTRA_CFLAGS += -Idrivers/sstar/crypto/hal/$(CONFIG_SSTAR_CHIP_NAME) ++ ++mdrv_RNG-objs := sstar-rng.o +diff --git a/drivers/sstar/crypto/char/hw_random/sstar-rng.c b/drivers/sstar/crypto/char/hw_random/sstar-rng.c +new file mode 100755 +index 000000000000..a03c537f7668 +--- /dev/null ++++ b/drivers/sstar/crypto/char/hw_random/sstar-rng.c +@@ -0,0 +1,94 @@ ++/* ++* sstar-rng.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define to_sstar_rng(p) container_of(p, struct sstar_rng, rng) ++ ++struct sstar_rng { ++ void __iomem *base; ++ struct hwrng rng; ++}; ++ ++static int sstar_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ //struct sstar_rng *hrng = to_sstar_rng(rng); ++ u16 *data = buf; ++ //printk("[%s,%d] max(%d)\n",__FUNCTION__,__LINE__, max); ++ *data = HAL_RNG_Read(); ++ return 2; ++} ++ ++int sstar_rng_probe(struct platform_device *pdev) ++{ ++ struct sstar_rng *rng; ++ //struct resource *res; ++ int ret; ++ //printk("[%s,%d]\n",__FUNCTION__,__LINE__); ++ rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL); ++ if (!rng) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, rng); ++ ++ //res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ //rng->base = devm_ioremap_resource(&pdev->dev, res); ++ //if (IS_ERR(rng->base)) ++ // return PTR_ERR(rng->base); ++ ++ ++ rng->rng.name = pdev->name; ++ rng->rng.init = NULL;; ++ rng->rng.cleanup = NULL; ++ rng->rng.read = sstar_rng_read; ++ rng->rng.quality = 500; ++ ++ ret = devm_hwrng_register(&pdev->dev, &rng->rng); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register hwrng\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++/* ++static const struct of_device_id sstar_rng_dt_ids[] = { ++ { .compatible = "sstar,rng" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, sstar_rng_dt_ids); ++ ++static struct platform_driver sstar_rng_driver = { ++ .probe = sstar_rng_probe, ++ .driver = { ++ .name = "sstar-rng", ++ .of_match_table = of_match_ptr(sstar_rng_dt_ids), ++ }, ++}; ++ ++module_platform_driver(sstar_rng_driver); ++*/ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("SStar random number generator driver"); +diff --git a/drivers/sstar/crypto/cryptodev/AUTHORS b/drivers/sstar/crypto/cryptodev/AUTHORS +new file mode 100644 +index 000000000000..6f9408ec9b7b +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/AUTHORS +@@ -0,0 +1,19 @@ ++Michal Ludvig: ++ Initial implementation for linux 2.6.8 ++ ++Nikos Mavrogiannopoulos: ++ Port to 2.6.27 and later, better compatibility ++ with OpenBSD (and FreeBSD) cryptodev and maintanance. ++ ++Michael Weiser: ++ Porting to blkcipher async API. Several hardware drivers ++ only implemented this API. ++ ++Phil Sutter: ++ Implemented a zero copy version of the internal engine. ++ ++Dmitry Kasatkin: ++ Multi-update support for hash calculation. ++ ++ ++Maintained by Nikos Mavrogiannopoulos (nmav [at] gnutls [dot] org) +diff --git a/drivers/sstar/crypto/cryptodev/COPYING b/drivers/sstar/crypto/cryptodev/COPYING +new file mode 100644 +index 000000000000..d159169d1050 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/COPYING +@@ -0,0 +1,339 @@ ++ GNU GENERAL PUBLIC LICENSE ++ Version 2, June 1991 ++ ++ Copyright (C) 1989, 1991 Free Software Foundation, Inc., ++ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA ++ Everyone is permitted to copy and distribute verbatim copies ++ of this license document, but changing it is not allowed. ++ ++ Preamble ++ ++ The licenses for most software are designed to take away your ++freedom to share and change it. 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See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License along ++ with this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ ++Also add information on how to contact you by electronic and paper mail. ++ ++If the program is interactive, make it output a short notice like this ++when it starts in an interactive mode: ++ ++ Gnomovision version 69, Copyright (C) year name of author ++ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. ++ This is free software, and you are welcome to redistribute it ++ under certain conditions; type `show c' for details. ++ ++The hypothetical commands `show w' and `show c' should show the appropriate ++parts of the General Public License. Of course, the commands you use may ++be called something other than `show w' and `show c'; they could even be ++mouse-clicks or menu items--whatever suits your program. ++ ++You should also get your employer (if you work as a programmer) or your ++school, if any, to sign a "copyright disclaimer" for the program, if ++necessary. Here is a sample; alter the names: ++ ++ Yoyodyne, Inc., hereby disclaims all copyright interest in the program ++ `Gnomovision' (which makes passes at compilers) written by James Hacker. ++ ++ , 1 April 1989 ++ Ty Coon, President of Vice ++ ++This General Public License does not permit incorporating your program into ++proprietary programs. If your program is a subroutine library, you may ++consider it more useful to permit linking proprietary applications with the ++library. If this is what you want to do, use the GNU Lesser General ++Public License instead of this License. +diff --git a/drivers/sstar/crypto/cryptodev/INSTALL b/drivers/sstar/crypto/cryptodev/INSTALL +new file mode 100644 +index 000000000000..2754c5933287 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/INSTALL +@@ -0,0 +1,32 @@ ++=== Installation instructions === ++ ++Simply run: ++$ make ++# make install ++ ++The first command compiles the code and generates the kernel module ++and the latter installs the header files and the kernel module. ++ ++After that you should set your system to load the kernel module on system ++load. In most systems this can be done as: ++# echo "cryptodev" >>/etc/modules ++ ++or in systemd-enabled systems: ++# echo "cryptodev" > /etc/modules-load.d/cryptodev.conf ++ ++=== Testing installation === ++ ++* cryptodev-linux: ++Check whether cryptodev-linux is operating as expected using the following ++command. ++$ make check ++ ++* OpenSSL: ++run the following commands prior and after installation and compare. ++$ openssl speed -evp aes-128-cbc ++$ openssl speed -evp sha1 ++ ++* GnuTLS 3.x: ++run the following command prior and after installation and compare. ++$ gnutls-cli --benchmark-ciphers ++ +diff --git a/drivers/sstar/crypto/cryptodev/Makefile b/drivers/sstar/crypto/cryptodev/Makefile +new file mode 100755 +index 000000000000..62e1a95673fe +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/Makefile +@@ -0,0 +1,67 @@ ++# ++# Since version 1.6 the asynchronous mode has been ++# disabled by default. To re-enable it uncomment the ++# corresponding CFLAG. ++# ++CRYPTODEV_CFLAGS ?= #-DENABLE_ASYNC ++KBUILD_CFLAGS += -I$(src) $(CRYPTODEV_CFLAGS) ++KERNEL_DIR ?= /lib/modules/$(shell uname -r)/build ++VERSION = 1.10(a1e738a) ++ ++prefix ?= /usr/local ++includedir = $(prefix)/include ++ ++cryptodev-objs = ioctl.o main.o cryptlib.o authenc.o zc.o util.o ++ ++obj-$(CONFIG_CRYPTODEV) += cryptodev.o ++ ++KERNEL_MAKE_OPTS := -C $(KERNEL_DIR) M=$(CURDIR) ++ifneq ($(ARCH),) ++KERNEL_MAKE_OPTS += ARCH=$(ARCH) ++endif ++ifneq ($(CROSS_COMPILE),) ++KERNEL_MAKE_OPTS += CROSS_COMPILE=$(CROSS_COMPILE) ++endif ++ ++build: version.h ++ $(MAKE) $(KERNEL_MAKE_OPTS) modules ++ ++version.h: Makefile ++ @echo "#define VERSION \"$(VERSION)\"" > version.h ++ ++install: modules_install ++ ++modules_install: ++ $(MAKE) $(KERNEL_MAKE_OPTS) modules_install ++ install -m 644 -D crypto/cryptodev.h $(DESTDIR)/$(includedir)/crypto/cryptodev.h ++ ++clean: ++ $(MAKE) $(KERNEL_MAKE_OPTS) clean ++ rm -f $(hostprogs) *~ ++ CFLAGS=$(CRYPTODEV_CFLAGS) KERNEL_DIR=$(KERNEL_DIR) $(MAKE) -C tests clean ++ ++check: ++ CFLAGS=$(CRYPTODEV_CFLAGS) KERNEL_DIR=$(KERNEL_DIR) $(MAKE) -C tests check ++ ++CPOPTS = ++ifneq ($(SHOW_TYPES),) ++CPOPTS += --show-types ++endif ++ifneq ($(IGNORE_TYPES),) ++CPOPTS += --ignore $(IGNORE_TYPES) ++endif ++ ++checkpatch: ++ $(KERNEL_DIR)/scripts/checkpatch.pl $(CPOPTS) --file *.c *.h ++ ++VERSIONTAG = refs/tags/cryptodev-linux-$(VERSION) ++FILEBASE = cryptodev-linux-$(VERSION) ++OUTPUT = $(FILEBASE).tar.gz ++ ++dist: clean ++ @echo Packing ++ @rm -f *.tar.gz ++ @git archive --format=tar.gz --prefix=$(FILEBASE)/ --output=$(OUTPUT) $(VERSIONTAG) ++ @echo Signing $(OUTPUT) ++ @gpg --output $(OUTPUT).sig -sb $(OUTPUT) ++ @gpg --verify $(OUTPUT).sig $(OUTPUT) +diff --git a/drivers/sstar/crypto/cryptodev/NEWS b/drivers/sstar/crypto/cryptodev/NEWS +new file mode 100644 +index 000000000000..e5255d4f2833 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/NEWS +@@ -0,0 +1,252 @@ ++Version 1.10 (released 2018-12-20) ++ ++* Fix compilation issues against Linux kernel >= 4.11 and gcc >= 5 ++* Add CIOCCPHASH ioctl ++* Fix tests build for OpenSSL 1.1 ++* Convert to new AEAD kernel crypto interface ++* A variety of bug fixes ++ ++Version 1.9 (released 2017-04-22) ++ ++* fix benchmarks linking ++ ++* fix Makefile to allow parallel make with -j option ++ ++* use Linux kernel conventions for Makefile variables ++ ++* for consistency, use $(...) instead of ${...} in makefiles ++ ++* fix clean-up on error path for crypto_create_session ++ ++* remove code duplication in cryptodev_hash_init ++ ++* add separate target for building tests ++ ++* fix destination for staged installs ++ ++* add install target for tests ++ ++* fix comment typo ++ ++* avoid calls to kmalloc on hotpaths ++ ++* avoid redundant checks in cryptodev_hash_deinit ++ ++* Fix test compile time warnings ++ ++* Support skcipher in addition to ablkcipher API ++ ++* Adjust to recent user page API changes ++ ++* Adjust to another change in the user page API ++ ++* fix issues with install target ++ ++* setting KERNEL_DIR is not necessary to build tests ++ ++* fix ignored SIGALRM signals on some platforms ++ ++* fix incorrect return code in case of error from openssl_cioccrypt ++ ++* remove not used local variables ++ ++* fix warnings of "implicit declaration of function" in async_speed ++ ++* rename header file to clarify purpose ++ ++* use buf_align macro to reduce code duplication ++ ++* avoid implicit conversion between signed and unsigned char ++ ++* do more strict code checking to avoid maintenance issues ++ ++* adjust to API changes in kernel >=4.10 ++ ++* zc: Use the power of #elif ++ ++* Fix ablkcipher algorithms usage in v4.8+ kernels ++ ++Version 1.8 (released 2015-11-28) ++ ++* Fixed compilation against linux-3.19. ++ ++* Tests: cixed arg passing to CC in implicit rule. ++ ++* Fix tag printing in cipher-gcm test by Fridolin Pokorny. ++ ++* Fix compilation against linux 4.3 by Gustavo Zacarias. ++ ++Version 1.7 (released 2015-02-07) ++ ++* Added support for composite AEAD keys by Cristian Stoica. ++ ++* Added support for sysctl to modify verbosity by Nikolaos Tsakalakis. ++ ++* Several bugfixes by Cristian Stoica. ++ ++* When a driver requires aligned data but unaligned are provided, then ++ zero copy is disabled to prevent driver failing to encrypt. ++ ++* Compatibility to kernel version 3.13 and above by Cosmin Paraschiv. ++ ++* Various checkpatch.pl fixes. ++ ++* Introduced ddebug, dinfo, dwarning and derr macros wrapping dprintk. ++ ++* Improved support for cross-compiling. ++ ++* Hmac_comp test has become more picky when checking results. ++ ++* Fixed allocated resource cleanup in error case, patch by Cristian Stoica. ++ ++* Buffer size allocation fixup for AEAD modes by Nikos Mavrogiannopoulos. ++ ++* Support for composite AEAD keys added by Cristian Stoica. ++ ++* Fixed tag and dsl_len calculation for AEAD ciphers, patch by Cristian Stoica. ++ ++* Documentation updates by Nikos Mavrogiannopoulos. ++ ++ ++Version 1.6 (released 2013-03-20) ++ ++* Added modules_install target in Makefile ++ ++* Added SHA224. Patch by Yashpal Dutta. ++ ++* Asynchronous operations will not be scheduled if zero copy is disabled. ++ ++* Asynchronous operations are disabled by default, unless -DENABLE_ASYNC ++ is enabled on Makefile. ++ ++ ++Version 1.5 (released 2012-08-04) ++ ++* Fixes in AEAD support. Patches by Jaren Johnston. ++ ++* Simplifications in memory locking. Patch by Phil Sutter. ++ ++* Allow empty plaintext and authenticated data in AEAD ciphers. ++ Patch by Jaren Johnston. ++ ++ ++Version 1.4 (released 2012-03-15) ++ ++* Correctly report hw accelerated ciphers. ++ ++ ++Version 1.3 (released 2012-02-29) ++ ++* Return EBADMSG instead of ECANCELED on tag verification failure in ++ authenc modes. ++ ++* COP_FLAG_RESET can be combined with COP_FLAG_UPDATE for efficiency. ++ ++* Added more test cases. ++ ++* Automatically set public permissions for the device ++ ++ ++Version 1.2 (released 2012-02-24) ++ ++* In kernels that do not distinguish between hw accelerated ciphers or ++ not set the SIOP_FLAG_KERNEL_DRIVER_ONLY flag based on driver name. ++ ++* camelia was renamed to camellia. ++ ++* Added COP_FLAG_RESET to allow resetting the state in multi-update. ++ ++* Corrected issue in ARM processors with mv_cesa. ++ ++ ++Version 1.1 (released 2012-02-20) ++ ++* Fixed alignment issue in speed.c ++ ++* Defined HASH_MAX_LEN in cryptodev.h ++ ++* CIOCGSESSINFO ioctl() sets the SIOP_FLAG_KERNEL_DRIVER_ONLY flag if the ++ driver is only available through kernel driver (and is not just software ++ cipher). ++ ++* Added new encryption ioctl, CIOCAUTHCRYPT, which combines authentication ++ and encryption. Operates in AEAD, TLS and SRTP modes (the API might change ++ in later versions). ++ ++ ++Version 1.0 (released 2011-04-12) ++ ++* Several fixes in the included examples. Based on patches by Vladimir ++ Zapolskiy. ++ ++ ++Version 0.9 (released 2011-02-11) ++ ++* Added additional test tools: ++ - sha_speed does performance testing of SHA1 and SHA256 ++ - hashcrypt_speed additionally encrypts with AES128 and AES256 ++ ++* Allow updating the IV in userspace via the COP_FLAG_WRITE_IV flag. ++ ++* Export the alignmask in an OCF compatible way. ++ ++* Fix for kernel crash on passing incorrect session ID. ++ ++* Added CIOCGSESSINFO to export additional information for each session. ++ ++ ++Version 0.8 (released 2010-11-06) ++ ++* Made cryptodev aware of alignment constraints. ++ ++* Added support for CRYPTO_AES_ECB. ++ ++* Added asynchronous operation support using ++ CIOCASYNCCRYPT, CIOCASYNCFETCH ioctls and poll(). ++ ++ ++Version 0.7 (released 2010-10-08) ++ ++* Added COP_FLAG_FINAL to make multi-update more efficient. ++ ++* Added CRIOGET_NOT_NEEDED definition to allow users of the API to ++ distinguish from the bare OpenBSD API that requires the CRIOGET. ++ ++ ++Version 0.6 (released 2010-09-16) ++ ++* multi-update support for hash calculation using the new flag ++ COP_FLAG_UPDATE. ++ ++* Relicensed under GPLv2. ++ ++* Added AES-CTR. ++ ++* Corrected fallback to non-zero copy when referenced pages were ++ not writable. ++ ++ ++Version 0.5 (released 2010-07-06) ++ ++* Corrected issue with zero copy on multiple pages. ++ ++* Fallback to normal operation if user pages cannot be mapped. ++ ++ ++Version 0.4 (released 2010-07-03) ++ ++* Internal engine supports operations with zero copy from user space. ++ ++ ++Version 0.3 (released 2010-06-19) ++ ++* Corrected bug when initializing unsupported algorithms. ++ ++ ++Version 0.2 (released 2010-06-18) ++ ++* Added compat_ioctl() to allow working on systems where userspace is 32bits ++ and kernel is operating in 64bit mode (Phil Sutter) ++ ++* Added several sanity checks to input. ++ +diff --git a/drivers/sstar/crypto/cryptodev/README b/drivers/sstar/crypto/cryptodev/README +new file mode 100644 +index 000000000000..eb192046eaed +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/README +@@ -0,0 +1,40 @@ ++This is a /dev/crypto device driver, equivalent to those in OpenBSD or ++FreeBSD. The main idea is to access of existing ciphers in kernel space ++from userspace, thus enabling the re-use of a hardware implementation of a ++cipher. ++ ++For questions and suggestions please use the mailing lists at: ++http://cryptodev-linux.org/lists.html ++ ++ ++=== How to combine with cryptographic libraries === ++ ++* GnuTLS: ++ ++GnuTLS needs to be compiled with --enable-cryptodev in order to take ++advantage of /dev/crypto. GnuTLS 3.0.14 or later is recommended. ++ ++* OpenSSL: ++ ++Note that OpenSSL's cryptodev implementation is outdated, and there ++are issues with it. For that we recommend to use the patches ++below, that we have provided to the openssl project. ++ ++http://rt.openssl.org/Ticket/Display.html?id=2770&user=guest&pass=guest ++ ++After applying the patches you can add cryptodev support by using the ++-DHAVE_CRYPTODEV and -DUSE_CRYPTODEV_DIGESTS flags during compilation. ++Note that the latter flag (digests) may induce a performance penalty ++in some systems. ++ ++ ++=== Modifying and viewing verbosity at runtime === ++ ++For debugging often the verbosity of the driver needs to be adjusted. ++The sysctl tool can be used for that. ++ ++# sysctl ioctl.cryptodev_verbosity ++ioctl.cryptodev_verbosity = 0 ++ ++# sysctl ioctl.cryptodev_verbosity=3 ++ioctl.cryptodev_verbosity = 3 +diff --git a/drivers/sstar/crypto/cryptodev/authenc.c b/drivers/sstar/crypto/cryptodev/authenc.c +new file mode 100644 +index 000000000000..7c236cf6ad34 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/authenc.c +@@ -0,0 +1,849 @@ ++/* ++ * Driver for /dev/crypto device (aka CryptoDev) ++ * ++ * Copyright (c) 2011, 2012 OpenSSL Software Foundation, Inc. ++ * ++ * Author: Nikos Mavrogiannopoulos ++ * ++ * This file is part of linux cryptodev. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++/* ++ * This file handles the AEAD part of /dev/crypto. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cryptodev_int.h" ++#include "zc.h" ++#include "util.h" ++#include "cryptlib.h" ++#include "version.h" ++ ++ ++/* make caop->dst available in scatterlist. ++ * (caop->src is assumed to be equal to caop->dst) ++ */ ++static int get_userbuf_tls(struct csession *ses, struct kernel_crypt_auth_op *kcaop, ++ struct scatterlist **dst_sg) ++{ ++ int pagecount = 0; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ int rc; ++ ++ if (caop->dst == NULL) ++ return -EINVAL; ++ ++ if (ses->alignmask) { ++ if (!IS_ALIGNED((unsigned long)caop->dst, ses->alignmask + 1)) ++ dwarning(2, "careful - source address %p is not %d byte aligned", ++ caop->dst, ses->alignmask + 1); ++ } ++ ++ if (kcaop->dst_len == 0) { ++ dwarning(1, "Destination length cannot be zero"); ++ return -EINVAL; ++ } ++ ++ pagecount = PAGECOUNT(caop->dst, kcaop->dst_len); ++ ++ ses->used_pages = pagecount; ++ ses->readonly_pages = 0; ++ ++ rc = adjust_sg_array(ses, pagecount); ++ if (rc) ++ return rc; ++ ++ rc = __get_userbuf(caop->dst, kcaop->dst_len, 1, pagecount, ++ ses->pages, ses->sg, kcaop->task, kcaop->mm); ++ if (unlikely(rc)) { ++ derr(1, "failed to get user pages for data input"); ++ return -EINVAL; ++ } ++ ++ (*dst_sg) = ses->sg; ++ ++ return 0; ++} ++ ++ ++#define MAX_SRTP_AUTH_DATA_DIFF 256 ++ ++/* Makes caop->auth_src available as scatterlist. ++ * It also provides a pointer to caop->dst, which however, ++ * is assumed to be within the caop->auth_src buffer. If not ++ * (if their difference exceeds MAX_SRTP_AUTH_DATA_DIFF) it ++ * returns error. ++ */ ++static int get_userbuf_srtp(struct csession *ses, struct kernel_crypt_auth_op *kcaop, ++ struct scatterlist **auth_sg, struct scatterlist **dst_sg) ++{ ++ int pagecount, diff; ++ int auth_pagecount = 0; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ int rc; ++ ++ if (caop->dst == NULL && caop->auth_src == NULL) { ++ derr(1, "dst and auth_src cannot be both null"); ++ return -EINVAL; ++ } ++ ++ if (ses->alignmask) { ++ if (!IS_ALIGNED((unsigned long)caop->dst, ses->alignmask + 1)) ++ dwarning(2, "careful - source address %p is not %d byte aligned", ++ caop->dst, ses->alignmask + 1); ++ if (!IS_ALIGNED((unsigned long)caop->auth_src, ses->alignmask + 1)) ++ dwarning(2, "careful - source address %p is not %d byte aligned", ++ caop->auth_src, ses->alignmask + 1); ++ } ++ ++ if (unlikely(kcaop->dst_len == 0 || caop->auth_len == 0)) { ++ dwarning(1, "Destination length cannot be zero"); ++ return -EINVAL; ++ } ++ ++ /* Note that in SRTP auth data overlap with data to be encrypted (dst) ++ */ ++ ++ auth_pagecount = PAGECOUNT(caop->auth_src, caop->auth_len); ++ diff = (int)(caop->src - caop->auth_src); ++ if (diff > MAX_SRTP_AUTH_DATA_DIFF || diff < 0) { ++ dwarning(1, "auth_src must overlap with src (diff: %d).", diff); ++ return -EINVAL; ++ } ++ ++ pagecount = auth_pagecount; ++ ++ rc = adjust_sg_array(ses, pagecount*2); /* double pages to have pages for dst(=auth_src) */ ++ if (rc) { ++ derr(1, "cannot adjust sg array"); ++ return rc; ++ } ++ ++ rc = __get_userbuf(caop->auth_src, caop->auth_len, 1, auth_pagecount, ++ ses->pages, ses->sg, kcaop->task, kcaop->mm); ++ if (unlikely(rc)) { ++ derr(1, "failed to get user pages for data input"); ++ return -EINVAL; ++ } ++ ++ ses->used_pages = pagecount; ++ ses->readonly_pages = 0; ++ ++ (*auth_sg) = ses->sg; ++ ++ (*dst_sg) = ses->sg + auth_pagecount; ++ sg_init_table(*dst_sg, auth_pagecount); ++ sg_copy(ses->sg, (*dst_sg), caop->auth_len); ++ (*dst_sg) = sg_advance(*dst_sg, diff); ++ if (*dst_sg == NULL) { ++ release_user_pages(ses); ++ derr(1, "failed to get enough pages for auth data"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Return tag (digest) length for authenticated encryption ++ * If the cipher and digest are separate, hdata.init is set - just return ++ * digest length. Otherwise return digest length for aead ciphers ++ */ ++static int cryptodev_get_tag_len(struct csession *ses_ptr) ++{ ++ if (ses_ptr->hdata.init) ++ return ses_ptr->hdata.digestsize; ++ else ++ return cryptodev_cipher_get_tag_size(&ses_ptr->cdata); ++} ++ ++/* ++ * Calculate destination buffer length for authenticated encryption. The ++ * expectation is that user-space code allocates exactly the same space for ++ * destination buffer before calling cryptodev. The result is cipher-dependent. ++ */ ++static int cryptodev_get_dst_len(struct crypt_auth_op *caop, struct csession *ses_ptr) ++{ ++ int dst_len = caop->len; ++ if (caop->op == COP_DECRYPT) ++ return dst_len; ++ ++ dst_len += caop->tag_len; ++ ++ /* for TLS always add some padding so the total length is rounded to ++ * cipher block size */ ++ if (caop->flags & COP_FLAG_AEAD_TLS_TYPE) { ++ int bs = ses_ptr->cdata.blocksize; ++ dst_len += bs - (dst_len % bs); ++ } ++ ++ return dst_len; ++} ++ ++static int fill_kcaop_from_caop(struct kernel_crypt_auth_op *kcaop, struct fcrypt *fcr) ++{ ++ struct crypt_auth_op *caop = &kcaop->caop; ++ struct csession *ses_ptr; ++ int ret; ++ ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, caop->ses); ++ if (unlikely(!ses_ptr)) { ++ derr(1, "invalid session ID=0x%08X", caop->ses); ++ return -EINVAL; ++ } ++ ++ if (caop->flags & COP_FLAG_AEAD_TLS_TYPE || caop->flags & COP_FLAG_AEAD_SRTP_TYPE) { ++ if (caop->src != caop->dst) { ++ derr(1, "Non-inplace encryption and decryption is not efficient and not implemented"); ++ ret = -EINVAL; ++ goto out_unlock; ++ } ++ } ++ ++ if (caop->tag_len == 0) ++ caop->tag_len = cryptodev_get_tag_len(ses_ptr); ++ ++ kcaop->ivlen = caop->iv ? ses_ptr->cdata.ivsize : 0; ++ kcaop->dst_len = cryptodev_get_dst_len(caop, ses_ptr); ++ kcaop->task = current; ++ kcaop->mm = current->mm; ++ ++ if (caop->iv) { ++ ret = copy_from_user(kcaop->iv, caop->iv, kcaop->ivlen); ++ if (unlikely(ret)) { ++ derr(1, "error copying IV (%d bytes), copy_from_user returned %d for address %p", ++ kcaop->ivlen, ret, caop->iv); ++ ret = -EFAULT; ++ goto out_unlock; ++ } ++ } ++ ++ ret = 0; ++ ++out_unlock: ++ crypto_put_session(ses_ptr); ++ return ret; ++ ++} ++ ++static int fill_caop_from_kcaop(struct kernel_crypt_auth_op *kcaop, struct fcrypt *fcr) ++{ ++ int ret; ++ ++ kcaop->caop.len = kcaop->dst_len; ++ ++ if (kcaop->ivlen && kcaop->caop.flags & COP_FLAG_WRITE_IV) { ++ ret = copy_to_user(kcaop->caop.iv, ++ kcaop->iv, kcaop->ivlen); ++ if (unlikely(ret)) { ++ derr(1, "Error in copying to userspace"); ++ return -EFAULT; ++ } ++ } ++ return 0; ++} ++ ++ ++int kcaop_from_user(struct kernel_crypt_auth_op *kcaop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ if (unlikely(copy_from_user(&kcaop->caop, arg, sizeof(kcaop->caop)))) { ++ derr(1, "Error in copying from userspace"); ++ return -EFAULT; ++ } ++ ++ return fill_kcaop_from_caop(kcaop, fcr); ++} ++ ++int kcaop_to_user(struct kernel_crypt_auth_op *kcaop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ int ret; ++ ++ ret = fill_caop_from_kcaop(kcaop, fcr); ++ if (unlikely(ret)) { ++ derr(1, "fill_caop_from_kcaop"); ++ return ret; ++ } ++ ++ if (unlikely(copy_to_user(arg, &kcaop->caop, sizeof(kcaop->caop)))) { ++ derr(1, "Error in copying to userspace"); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static void copy_tls_hash(struct scatterlist *dst_sg, int len, void *hash, int hash_len) ++{ ++ scatterwalk_map_and_copy(hash, dst_sg, len, hash_len, 1); ++} ++ ++static void read_tls_hash(struct scatterlist *dst_sg, int len, void *hash, int hash_len) ++{ ++ scatterwalk_map_and_copy(hash, dst_sg, len - hash_len, hash_len, 0); ++} ++ ++static int pad_record(struct scatterlist *dst_sg, int len, int block_size) ++{ ++ uint8_t pad[block_size]; ++ int pad_size = block_size - (len % block_size); ++ ++ memset(pad, pad_size - 1, pad_size); ++ ++ scatterwalk_map_and_copy(pad, dst_sg, len, pad_size, 1); ++ ++ return pad_size; ++} ++ ++static int verify_tls_record_pad(struct scatterlist *dst_sg, int len, int block_size) ++{ ++ uint8_t pad[256]; /* the maximum allowed */ ++ uint8_t pad_size; ++ int i; ++ ++ scatterwalk_map_and_copy(&pad_size, dst_sg, len - 1, 1, 0); ++ ++ if (pad_size + 1 > len) { ++ derr(1, "Pad size: %d", pad_size); ++ return -EBADMSG; ++ } ++ ++ scatterwalk_map_and_copy(pad, dst_sg, len - pad_size - 1, pad_size + 1, 0); ++ ++ for (i = 0; i < pad_size; i++) ++ if (pad[i] != pad_size) { ++ derr(1, "Pad size: %u, pad: %d", pad_size, pad[i]); ++ return -EBADMSG; ++ } ++ ++ return pad_size + 1; ++} ++ ++/* Authenticate and encrypt the TLS way (also perform padding). ++ * During decryption it verifies the pad and tag and returns -EBADMSG on error. ++ */ ++static int ++tls_auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop, ++ struct scatterlist *auth_sg, uint32_t auth_len, ++ struct scatterlist *dst_sg, uint32_t len) ++{ ++ int ret, fail = 0; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ uint8_t vhash[AALG_MAX_RESULT_LEN]; ++ uint8_t hash_output[AALG_MAX_RESULT_LEN]; ++ ++ /* TLS authenticates the plaintext except for the padding. ++ */ ++ if (caop->op == COP_ENCRYPT) { ++ if (ses_ptr->hdata.init != 0) { ++ if (auth_len > 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ auth_sg, auth_len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_update: %d", ret); ++ return ret; ++ } ++ } ++ ++ if (len > 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ dst_sg, len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_update: %d", ret); ++ return ret; ++ } ++ } ++ ++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_final: %d", ret); ++ return ret; ++ } ++ ++ copy_tls_hash(dst_sg, len, hash_output, caop->tag_len); ++ len += caop->tag_len; ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ if (ses_ptr->cdata.blocksize > 1) { ++ ret = pad_record(dst_sg, len, ses_ptr->cdata.blocksize); ++ len += ret; ++ } ++ ++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, ++ dst_sg, dst_sg, len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_cipher_encrypt: %d", ret); ++ return ret; ++ } ++ } ++ } else { ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, ++ dst_sg, dst_sg, len); ++ ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_cipher_decrypt: %d", ret); ++ return ret; ++ } ++ ++ if (ses_ptr->cdata.blocksize > 1) { ++ ret = verify_tls_record_pad(dst_sg, len, ses_ptr->cdata.blocksize); ++ if (unlikely(ret < 0)) { ++ derr(2, "verify_record_pad: %d", ret); ++ fail = 1; ++ } else { ++ len -= ret; ++ } ++ } ++ } ++ ++ if (ses_ptr->hdata.init != 0) { ++ if (unlikely(caop->tag_len > sizeof(vhash) || caop->tag_len > len)) { ++ derr(1, "Illegal tag len size"); ++ return -EINVAL; ++ } ++ ++ read_tls_hash(dst_sg, len, vhash, caop->tag_len); ++ len -= caop->tag_len; ++ ++ if (auth_len > 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ auth_sg, auth_len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_update: %d", ret); ++ return ret; ++ } ++ } ++ ++ if (len > 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ dst_sg, len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_update: %d", ret); ++ return ret; ++ } ++ } ++ ++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_final: %d", ret); ++ return ret; ++ } ++ ++ if (memcmp(vhash, hash_output, caop->tag_len) != 0 || fail != 0) { ++ derr(2, "MAC verification failed (tag_len: %d)", caop->tag_len); ++ return -EBADMSG; ++ } ++ } ++ } ++ kcaop->dst_len = len; ++ return 0; ++} ++ ++/* Authenticate and encrypt the SRTP way. During decryption ++ * it verifies the tag and returns -EBADMSG on error. ++ */ ++static int ++srtp_auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop, ++ struct scatterlist *auth_sg, uint32_t auth_len, ++ struct scatterlist *dst_sg, uint32_t len) ++{ ++ int ret, fail = 0; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ uint8_t vhash[AALG_MAX_RESULT_LEN]; ++ uint8_t hash_output[AALG_MAX_RESULT_LEN]; ++ ++ /* SRTP authenticates the encrypted data. ++ */ ++ if (caop->op == COP_ENCRYPT) { ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, ++ dst_sg, dst_sg, len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_cipher_encrypt: %d", ret); ++ return ret; ++ } ++ } ++ ++ if (ses_ptr->hdata.init != 0) { ++ if (auth_len > 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ auth_sg, auth_len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_update: %d", ret); ++ return ret; ++ } ++ } ++ ++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_final: %d", ret); ++ return ret; ++ } ++ ++ if (unlikely(copy_to_user(caop->tag, hash_output, caop->tag_len))) ++ return -EFAULT; ++ } ++ ++ } else { ++ if (ses_ptr->hdata.init != 0) { ++ if (unlikely(caop->tag_len > sizeof(vhash) || caop->tag_len > len)) { ++ derr(1, "Illegal tag len size"); ++ return -EINVAL; ++ } ++ ++ if (unlikely(copy_from_user(vhash, caop->tag, caop->tag_len))) ++ return -EFAULT; ++ ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ auth_sg, auth_len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_update: %d", ret); ++ return ret; ++ } ++ ++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_hash_final: %d", ret); ++ return ret; ++ } ++ ++ if (memcmp(vhash, hash_output, caop->tag_len) != 0 || fail != 0) { ++ derr(2, "MAC verification failed"); ++ return -EBADMSG; ++ } ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, ++ dst_sg, dst_sg, len); ++ ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_cipher_decrypt: %d", ret); ++ return ret; ++ } ++ } ++ ++ } ++ kcaop->dst_len = len; ++ return 0; ++} ++ ++/* Typical AEAD (i.e. GCM) encryption/decryption. ++ * During decryption the tag is verified. ++ */ ++static int ++auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop, ++ struct scatterlist *auth_sg, uint32_t auth_len, ++ struct scatterlist *src_sg, ++ struct scatterlist *dst_sg, uint32_t len) ++{ ++ int ret; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ int max_tag_len; ++ ++ max_tag_len = cryptodev_cipher_get_tag_size(&ses_ptr->cdata); ++ if (unlikely(caop->tag_len > max_tag_len)) { ++ derr(0, "Illegal tag length: %d", caop->tag_len); ++ return -EINVAL; ++ } ++ ++ if (caop->tag_len) ++ cryptodev_cipher_set_tag_size(&ses_ptr->cdata, caop->tag_len); ++ else ++ caop->tag_len = max_tag_len; ++ ++ cryptodev_cipher_auth(&ses_ptr->cdata, auth_sg, auth_len); ++ ++ if (caop->op == COP_ENCRYPT) { ++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, ++ src_sg, dst_sg, len); ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_cipher_encrypt: %d", ret); ++ return ret; ++ } ++ kcaop->dst_len = len + caop->tag_len; ++ caop->tag = caop->dst + len; ++ } else { ++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, ++ src_sg, dst_sg, len); ++ ++ if (unlikely(ret)) { ++ derr(0, "cryptodev_cipher_decrypt: %d", ret); ++ return ret; ++ } ++ kcaop->dst_len = len - caop->tag_len; ++ caop->tag = caop->dst + len - caop->tag_len; ++ } ++ ++ return 0; ++} ++ ++static int crypto_auth_zc_srtp(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) ++{ ++ struct scatterlist *dst_sg, *auth_sg; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ int ret; ++ ++ if (unlikely(ses_ptr->cdata.init != 0 && ++ (ses_ptr->cdata.stream == 0 || ses_ptr->cdata.aead != 0))) { ++ derr(0, "Only stream modes are allowed in SRTP mode (but not AEAD)"); ++ return -EINVAL; ++ } ++ ++ ret = get_userbuf_srtp(ses_ptr, kcaop, &auth_sg, &dst_sg); ++ if (unlikely(ret)) { ++ derr(1, "get_userbuf_srtp(): Error getting user pages."); ++ return ret; ++ } ++ ++ ret = srtp_auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len, ++ dst_sg, caop->len); ++ ++ release_user_pages(ses_ptr); ++ ++ return ret; ++} ++ ++static int crypto_auth_zc_tls(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) ++{ ++ struct crypt_auth_op *caop = &kcaop->caop; ++ struct scatterlist *dst_sg, *auth_sg; ++ unsigned char *auth_buf = NULL; ++ struct scatterlist tmp; ++ int ret; ++ ++ if (unlikely(caop->auth_len > PAGE_SIZE)) { ++ derr(1, "auth data len is excessive."); ++ return -EINVAL; ++ } ++ ++ auth_buf = (char *)__get_free_page(GFP_KERNEL); ++ if (unlikely(!auth_buf)) { ++ derr(1, "unable to get a free page."); ++ return -ENOMEM; ++ } ++ ++ if (caop->auth_src && caop->auth_len > 0) { ++ if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) { ++ derr(1, "unable to copy auth data from userspace."); ++ ret = -EFAULT; ++ goto free_auth_buf; ++ } ++ ++ sg_init_one(&tmp, auth_buf, caop->auth_len); ++ auth_sg = &tmp; ++ } else { ++ auth_sg = NULL; ++ } ++ ++ ret = get_userbuf_tls(ses_ptr, kcaop, &dst_sg); ++ if (unlikely(ret)) { ++ derr(1, "get_userbuf_tls(): Error getting user pages."); ++ goto free_auth_buf; ++ } ++ ++ ret = tls_auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len, ++ dst_sg, caop->len); ++ release_user_pages(ses_ptr); ++ ++free_auth_buf: ++ free_page((unsigned long)auth_buf); ++ return ret; ++} ++ ++static int crypto_auth_zc_aead(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) ++{ ++ struct scatterlist *dst_sg; ++ struct scatterlist *src_sg; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ unsigned char *auth_buf = NULL; ++ int ret; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) ++ struct scatterlist tmp; ++ struct scatterlist *auth_sg; ++#else ++ struct scatterlist auth1[2]; ++ struct scatterlist auth2[2]; ++#endif ++ ++ if (unlikely(ses_ptr->cdata.init == 0 || ++ (ses_ptr->cdata.stream == 0 && ses_ptr->cdata.aead == 0))) { ++ derr(0, "Only stream and AEAD ciphers are allowed for authenc"); ++ return -EINVAL; ++ } ++ ++ if (unlikely(caop->auth_len > PAGE_SIZE)) { ++ derr(1, "auth data len is excessive."); ++ return -EINVAL; ++ } ++ ++ auth_buf = (char *)__get_free_page(GFP_KERNEL); ++ if (unlikely(!auth_buf)) { ++ derr(1, "unable to get a free page."); ++ return -ENOMEM; ++ } ++ ++ ret = get_userbuf(ses_ptr, caop->src, caop->len, caop->dst, kcaop->dst_len, ++ kcaop->task, kcaop->mm, &src_sg, &dst_sg); ++ if (unlikely(ret)) { ++ derr(1, "get_userbuf(): Error getting user pages."); ++ goto free_auth_buf; ++ } ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) ++ if (caop->auth_src && caop->auth_len > 0) { ++ if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) { ++ derr(1, "unable to copy auth data from userspace."); ++ ret = -EFAULT; ++ goto free_pages; ++ } ++ ++ sg_init_one(&tmp, auth_buf, caop->auth_len); ++ auth_sg = &tmp; ++ } else { ++ auth_sg = NULL; ++ } ++ ++ ret = auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len, ++ src_sg, dst_sg, caop->len); ++#else ++ if (caop->auth_src && caop->auth_len > 0) { ++ if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) { ++ derr(1, "unable to copy auth data from userspace."); ++ ret = -EFAULT; ++ goto free_pages; ++ } ++ ++ sg_init_table(auth1, 2); ++ sg_set_buf(auth1, auth_buf, caop->auth_len); ++ sg_chain(auth1, 2, src_sg); ++ ++ if (src_sg == dst_sg) { ++ src_sg = auth1; ++ dst_sg = auth1; ++ } else { ++ sg_init_table(auth2, 2); ++ sg_set_buf(auth2, auth_buf, caop->auth_len); ++ sg_chain(auth2, 2, dst_sg); ++ src_sg = auth1; ++ dst_sg = auth2; ++ } ++ } ++ ++ ret = auth_n_crypt(ses_ptr, kcaop, NULL, caop->auth_len, ++ src_sg, dst_sg, caop->len); ++#endif ++ ++free_pages: ++ release_user_pages(ses_ptr); ++ ++free_auth_buf: ++ free_page((unsigned long)auth_buf); ++ ++ return ret; ++} ++ ++static int ++__crypto_auth_run_zc(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) ++{ ++ struct crypt_auth_op *caop = &kcaop->caop; ++ int ret; ++ ++ if (caop->flags & COP_FLAG_AEAD_SRTP_TYPE) { ++ ret = crypto_auth_zc_srtp(ses_ptr, kcaop); ++ } else if (caop->flags & COP_FLAG_AEAD_TLS_TYPE && ++ ses_ptr->cdata.aead == 0) { ++ ret = crypto_auth_zc_tls(ses_ptr, kcaop); ++ } else if (ses_ptr->cdata.aead) { ++ ret = crypto_auth_zc_aead(ses_ptr, kcaop); ++ } else { ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++ ++int crypto_auth_run(struct fcrypt *fcr, struct kernel_crypt_auth_op *kcaop) ++{ ++ struct csession *ses_ptr; ++ struct crypt_auth_op *caop = &kcaop->caop; ++ int ret; ++ ++ if (unlikely(caop->op != COP_ENCRYPT && caop->op != COP_DECRYPT)) { ++ ddebug(1, "invalid operation op=%u", caop->op); ++ return -EINVAL; ++ } ++ ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, caop->ses); ++ if (unlikely(!ses_ptr)) { ++ derr(1, "invalid session ID=0x%08X", caop->ses); ++ return -EINVAL; ++ } ++ ++ if (unlikely(ses_ptr->cdata.init == 0)) { ++ derr(1, "cipher context not initialized"); ++ ret = -EINVAL; ++ goto out_unlock; ++ } ++ ++ /* If we have a hash/mac handle reset its state */ ++ if (ses_ptr->hdata.init != 0) { ++ ret = cryptodev_hash_reset(&ses_ptr->hdata); ++ if (unlikely(ret)) { ++ derr(1, "error in cryptodev_hash_reset()"); ++ goto out_unlock; ++ } ++ } ++ ++ cryptodev_cipher_set_iv(&ses_ptr->cdata, kcaop->iv, ++ min(ses_ptr->cdata.ivsize, kcaop->ivlen)); ++ ++ ret = __crypto_auth_run_zc(ses_ptr, kcaop); ++ if (unlikely(ret)) { ++ derr(1, "error in __crypto_auth_run_zc()"); ++ goto out_unlock; ++ } ++ ++ ret = 0; ++ ++ cryptodev_cipher_get_iv(&ses_ptr->cdata, kcaop->iv, ++ min(ses_ptr->cdata.ivsize, kcaop->ivlen)); ++ ++out_unlock: ++ crypto_put_session(ses_ptr); ++ return ret; ++} +diff --git a/drivers/sstar/crypto/cryptodev/cipherapi.h b/drivers/sstar/crypto/cryptodev/cipherapi.h +new file mode 100644 +index 000000000000..b6ed6c279350 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/cipherapi.h +@@ -0,0 +1,56 @@ ++#ifndef CIPHERAPI_H ++# define CIPHERAPI_H ++ ++#include ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)) ++# include ++ ++typedef struct crypto_ablkcipher cryptodev_crypto_blkcipher_t; ++typedef struct ablkcipher_request cryptodev_blkcipher_request_t; ++ ++# define cryptodev_crypto_alloc_blkcipher crypto_alloc_ablkcipher ++# define cryptodev_crypto_blkcipher_blocksize crypto_ablkcipher_blocksize ++# define cryptodev_crypto_blkcipher_ivsize crypto_ablkcipher_ivsize ++# define cryptodev_crypto_blkcipher_alignmask crypto_ablkcipher_alignmask ++# define cryptodev_crypto_blkcipher_setkey crypto_ablkcipher_setkey ++ ++static inline void cryptodev_crypto_free_blkcipher(cryptodev_crypto_blkcipher_t *c) { ++ if (c) ++ crypto_free_ablkcipher(c); ++} ++ ++# define cryptodev_blkcipher_request_alloc ablkcipher_request_alloc ++# define cryptodev_blkcipher_request_set_callback ablkcipher_request_set_callback ++ ++static inline void cryptodev_blkcipher_request_free(cryptodev_blkcipher_request_t *r) { ++ if (r) ++ ablkcipher_request_free(r); ++} ++ ++# define cryptodev_blkcipher_request_set_crypt ablkcipher_request_set_crypt ++# define cryptodev_crypto_blkcipher_encrypt crypto_ablkcipher_encrypt ++# define cryptodev_crypto_blkcipher_decrypt crypto_ablkcipher_decrypt ++# define cryptodev_crypto_blkcipher_tfm crypto_ablkcipher_tfm ++#else ++#include ++ ++typedef struct crypto_skcipher cryptodev_crypto_blkcipher_t; ++typedef struct skcipher_request cryptodev_blkcipher_request_t; ++ ++# define cryptodev_crypto_alloc_blkcipher crypto_alloc_skcipher ++# define cryptodev_crypto_blkcipher_blocksize crypto_skcipher_blocksize ++# define cryptodev_crypto_blkcipher_ivsize crypto_skcipher_ivsize ++# define cryptodev_crypto_blkcipher_alignmask crypto_skcipher_alignmask ++# define cryptodev_crypto_blkcipher_setkey crypto_skcipher_setkey ++# define cryptodev_crypto_free_blkcipher crypto_free_skcipher ++# define cryptodev_blkcipher_request_alloc skcipher_request_alloc ++# define cryptodev_blkcipher_request_set_callback skcipher_request_set_callback ++# define cryptodev_blkcipher_request_free skcipher_request_free ++# define cryptodev_blkcipher_request_set_crypt skcipher_request_set_crypt ++# define cryptodev_crypto_blkcipher_encrypt crypto_skcipher_encrypt ++# define cryptodev_crypto_blkcipher_decrypt crypto_skcipher_decrypt ++# define cryptodev_crypto_blkcipher_tfm crypto_skcipher_tfm ++#endif ++ ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/cryptlib.c b/drivers/sstar/crypto/cryptodev/cryptlib.c +new file mode 100644 +index 000000000000..4a8703788eb8 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/cryptlib.c +@@ -0,0 +1,489 @@ ++/* ++ * Driver for /dev/crypto device (aka CryptoDev) ++ * ++ * Copyright (c) 2010,2011 Nikos Mavrogiannopoulos ++ * Portions Copyright (c) 2010 Michael Weiser ++ * Portions Copyright (c) 2010 Phil Sutter ++ * ++ * This file is part of linux cryptodev. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cryptodev_int.h" ++#include "cipherapi.h" ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) ++extern const struct crypto_type crypto_givcipher_type; ++#endif ++ ++static void cryptodev_complete(struct crypto_async_request *req, int err) ++{ ++ struct cryptodev_result *res = req->data; ++ ++ if (err == -EINPROGRESS) ++ return; ++ ++ res->err = err; ++ complete(&res->completion); ++} ++ ++int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop, ++ int aead) ++{ ++ /* ++ * For blockciphers (AES-CBC) or non-composite aead ciphers (like AES-GCM), ++ * the key length is simply the cipher keylen obtained from userspace. If ++ * the cipher is composite aead, the keylen is the sum of cipher keylen, ++ * hmac keylen and a key header length. This key format is the one used in ++ * Linux kernel for composite aead ciphers (crypto/authenc.c) ++ */ ++ unsigned int klen = sop->keylen; ++ ++ if (unlikely(sop->keylen > CRYPTO_CIPHER_MAX_KEY_LEN)) ++ return -EINVAL; ++ ++ if (aead && sop->mackeylen) { ++ if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) ++ return -EINVAL; ++ klen += sop->mackeylen; ++ klen += RTA_SPACE(sizeof(struct crypto_authenc_key_param)); ++ } ++ ++ *keylen = klen; ++ return 0; ++} ++ ++int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead) ++{ ++ /* ++ * Get cipher key from user-space. For blockciphers just copy it from ++ * user-space. For composite aead ciphers combine it with the hmac key in ++ * the format used by Linux kernel in crypto/authenc.c: ++ * ++ * [[AUTHENC_KEY_HEADER + CIPHER_KEYLEN] [AUTHENTICATION KEY] [CIPHER KEY]] ++ */ ++ struct crypto_authenc_key_param *param; ++ struct rtattr *rta; ++ int ret = 0; ++ ++ if (aead && sop->mackeylen) { ++ /* ++ * Composite aead ciphers. The first four bytes are the header type and ++ * header length for aead keys ++ */ ++ rta = (void *)key; ++ rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM; ++ rta->rta_len = RTA_LENGTH(sizeof(*param)); ++ ++ /* ++ * The next four bytes hold the length of the encryption key ++ */ ++ param = RTA_DATA(rta); ++ param->enckeylen = cpu_to_be32(sop->keylen); ++ ++ /* Advance key pointer eight bytes and copy the hmac key */ ++ key += RTA_SPACE(sizeof(*param)); ++ if (unlikely(copy_from_user(key, sop->mackey, sop->mackeylen))) { ++ ret = -EFAULT; ++ goto error; ++ } ++ /* Advance key pointer past the hmac key */ ++ key += sop->mackeylen; ++ } ++ /* now copy the blockcipher key */ ++ if (unlikely(copy_from_user(key, sop->key, sop->keylen))) ++ ret = -EFAULT; ++ ++error: ++ return ret; ++} ++ ++/* Was correct key length supplied? */ ++static int check_key_size(size_t keylen, const char *alg_name, ++ unsigned int min_keysize, unsigned int max_keysize) ++{ ++ if (max_keysize > 0 && unlikely((keylen < min_keysize) || ++ (keylen > max_keysize))) { ++ ddebug(1, "Wrong keylen '%zu' for algorithm '%s'. Use %u to %u.", ++ keylen, alg_name, min_keysize, max_keysize); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name, ++ uint8_t *keyp, size_t keylen, int stream, int aead) ++{ ++ int ret; ++ ++ if (aead == 0) { ++ unsigned int min_keysize, max_keysize; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) ++ struct crypto_tfm *tfm; ++#else ++ struct ablkcipher_alg *alg; ++#endif ++ ++ out->async.s = cryptodev_crypto_alloc_blkcipher(alg_name, 0, 0); ++ if (unlikely(IS_ERR(out->async.s))) { ++ ddebug(1, "Failed to load cipher %s", alg_name); ++ return -EINVAL; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) ++ tfm = crypto_skcipher_tfm(out->async.s); ++ if ((tfm->__crt_alg->cra_type == &crypto_ablkcipher_type) ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) ++ || (tfm->__crt_alg->cra_type == &crypto_givcipher_type) ++#endif ++ ) { ++ struct ablkcipher_alg *alg; ++ ++ alg = &tfm->__crt_alg->cra_ablkcipher; ++ min_keysize = alg->min_keysize; ++ max_keysize = alg->max_keysize; ++ } else { ++ struct skcipher_alg *alg; ++ ++ alg = crypto_skcipher_alg(out->async.s); ++ min_keysize = alg->min_keysize; ++ max_keysize = alg->max_keysize; ++ } ++#else ++ alg = crypto_ablkcipher_alg(out->async.s); ++ min_keysize = alg->min_keysize; ++ max_keysize = alg->max_keysize; ++#endif ++ ret = check_key_size(keylen, alg_name, min_keysize, ++ max_keysize); ++ if (ret) ++ goto error; ++ ++ out->blocksize = cryptodev_crypto_blkcipher_blocksize(out->async.s); ++ out->ivsize = cryptodev_crypto_blkcipher_ivsize(out->async.s); ++ out->alignmask = cryptodev_crypto_blkcipher_alignmask(out->async.s); ++ ++ ret = cryptodev_crypto_blkcipher_setkey(out->async.s, keyp, keylen); ++ } else { ++ out->async.as = crypto_alloc_aead(alg_name, 0, 0); ++ if (unlikely(IS_ERR(out->async.as))) { ++ ddebug(1, "Failed to load cipher %s", alg_name); ++ return -EINVAL; ++ } ++ ++ out->blocksize = crypto_aead_blocksize(out->async.as); ++ out->ivsize = crypto_aead_ivsize(out->async.as); ++ out->alignmask = crypto_aead_alignmask(out->async.as); ++ ++ ret = crypto_aead_setkey(out->async.as, keyp, keylen); ++ } ++ ++ if (unlikely(ret)) { ++ ddebug(1, "Setting key failed for %s-%zu.", alg_name, keylen*8); ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ out->stream = stream; ++ out->aead = aead; ++ ++ init_completion(&out->async.result.completion); ++ ++ if (aead == 0) { ++ out->async.request = cryptodev_blkcipher_request_alloc(out->async.s, GFP_KERNEL); ++ if (unlikely(!out->async.request)) { ++ derr(1, "error allocating async crypto request"); ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ cryptodev_blkcipher_request_set_callback(out->async.request, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, ++ cryptodev_complete, &out->async.result); ++ } else { ++ out->async.arequest = aead_request_alloc(out->async.as, GFP_KERNEL); ++ if (unlikely(!out->async.arequest)) { ++ derr(1, "error allocating async crypto request"); ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ aead_request_set_callback(out->async.arequest, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, ++ cryptodev_complete, &out->async.result); ++ } ++ ++ out->init = 1; ++ return 0; ++error: ++ if (aead == 0) { ++ cryptodev_blkcipher_request_free(out->async.request); ++ cryptodev_crypto_free_blkcipher(out->async.s); ++ } else { ++ if (out->async.arequest) ++ aead_request_free(out->async.arequest); ++ if (out->async.as) ++ crypto_free_aead(out->async.as); ++ } ++ ++ return ret; ++} ++ ++void cryptodev_cipher_deinit(struct cipher_data *cdata) ++{ ++ if (cdata->init) { ++ if (cdata->aead == 0) { ++ cryptodev_blkcipher_request_free(cdata->async.request); ++ cryptodev_crypto_free_blkcipher(cdata->async.s); ++ } else { ++ if (cdata->async.arequest) ++ aead_request_free(cdata->async.arequest); ++ if (cdata->async.as) ++ crypto_free_aead(cdata->async.as); ++ } ++ ++ cdata->init = 0; ++ } ++} ++ ++static inline int waitfor(struct cryptodev_result *cr, ssize_t ret) ++{ ++ switch (ret) { ++ case 0: ++ break; ++ case -EINPROGRESS: ++ case -EBUSY: ++ wait_for_completion(&cr->completion); ++ /* At this point we known for sure the request has finished, ++ * because wait_for_completion above was not interruptible. ++ * This is important because otherwise hardware or driver ++ * might try to access memory which will be freed or reused for ++ * another request. */ ++ ++ if (unlikely(cr->err)) { ++ derr(0, "error from async request: %d", cr->err); ++ return cr->err; ++ } ++ ++ break; ++ default: ++ return ret; ++ } ++ ++ return 0; ++} ++ ++ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata, ++ const struct scatterlist *src, struct scatterlist *dst, ++ size_t len) ++{ ++ int ret; ++ ++ reinit_completion(&cdata->async.result.completion); ++ ++ if (cdata->aead == 0) { ++ cryptodev_blkcipher_request_set_crypt(cdata->async.request, ++ (struct scatterlist *)src, dst, ++ len, cdata->async.iv); ++ ret = cryptodev_crypto_blkcipher_encrypt(cdata->async.request); ++ } else { ++ aead_request_set_crypt(cdata->async.arequest, ++ (struct scatterlist *)src, dst, ++ len, cdata->async.iv); ++ ret = crypto_aead_encrypt(cdata->async.arequest); ++ } ++ ++ return waitfor(&cdata->async.result, ret); ++} ++ ++ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata, ++ const struct scatterlist *src, struct scatterlist *dst, ++ size_t len) ++{ ++ int ret; ++ ++ reinit_completion(&cdata->async.result.completion); ++ if (cdata->aead == 0) { ++ cryptodev_blkcipher_request_set_crypt(cdata->async.request, ++ (struct scatterlist *)src, dst, ++ len, cdata->async.iv); ++ ret = cryptodev_crypto_blkcipher_decrypt(cdata->async.request); ++ } else { ++ aead_request_set_crypt(cdata->async.arequest, ++ (struct scatterlist *)src, dst, ++ len, cdata->async.iv); ++ ret = crypto_aead_decrypt(cdata->async.arequest); ++ } ++ ++ return waitfor(&cdata->async.result, ret); ++} ++ ++/* Hash functions */ ++ ++int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name, ++ int hmac_mode, void *mackey, size_t mackeylen) ++{ ++ int ret; ++ ++ hdata->async.s = crypto_alloc_ahash(alg_name, 0, 0); ++ if (unlikely(IS_ERR(hdata->async.s))) { ++ ddebug(1, "Failed to load transform for %s", alg_name); ++ return -EINVAL; ++ } ++ ++ /* Copy the key from user and set to TFM. */ ++ if (hmac_mode != 0) { ++ ret = crypto_ahash_setkey(hdata->async.s, mackey, mackeylen); ++ if (unlikely(ret)) { ++ ddebug(1, "Setting hmac key failed for %s-%zu.", ++ alg_name, mackeylen*8); ++ ret = -EINVAL; ++ goto error; ++ } ++ } ++ ++ hdata->digestsize = crypto_ahash_digestsize(hdata->async.s); ++ hdata->alignmask = crypto_ahash_alignmask(hdata->async.s); ++ ++ init_completion(&hdata->async.result.completion); ++ ++ hdata->async.request = ahash_request_alloc(hdata->async.s, GFP_KERNEL); ++ if (unlikely(!hdata->async.request)) { ++ derr(0, "error allocating async crypto request"); ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ ahash_request_set_callback(hdata->async.request, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, ++ cryptodev_complete, &hdata->async.result); ++ hdata->init = 1; ++ return 0; ++ ++error: ++ crypto_free_ahash(hdata->async.s); ++ return ret; ++} ++ ++void cryptodev_hash_deinit(struct hash_data *hdata) ++{ ++ if (hdata->init) { ++ ahash_request_free(hdata->async.request); ++ crypto_free_ahash(hdata->async.s); ++ hdata->init = 0; ++ } ++} ++ ++int cryptodev_hash_reset(struct hash_data *hdata) ++{ ++ int ret; ++ ++ ret = crypto_ahash_init(hdata->async.request); ++ if (unlikely(ret)) { ++ derr(0, "error in crypto_hash_init()"); ++ return ret; ++ } ++ ++ return 0; ++ ++} ++ ++ssize_t cryptodev_hash_update(struct hash_data *hdata, ++ struct scatterlist *sg, size_t len) ++{ ++ int ret; ++ ++ reinit_completion(&hdata->async.result.completion); ++ ahash_request_set_crypt(hdata->async.request, sg, NULL, len); ++ ++ ret = crypto_ahash_update(hdata->async.request); ++ ++ return waitfor(&hdata->async.result, ret); ++} ++ ++int cryptodev_hash_final(struct hash_data *hdata, void *output) ++{ ++ int ret; ++ ++ reinit_completion(&hdata->async.result.completion); ++ ahash_request_set_crypt(hdata->async.request, NULL, output, 0); ++ ++ ret = crypto_ahash_final(hdata->async.request); ++ ++ return waitfor(&hdata->async.result, ret); ++} ++ ++#ifdef CIOCCPHASH ++/* import the current hash state of src to dst */ ++int cryptodev_hash_copy(struct hash_data *dst, struct hash_data *src) ++{ ++ int ret, statesize; ++ void *statedata = NULL; ++ struct crypto_tfm *tfm; ++ ++ if (unlikely(src == NULL || dst == NULL)) { ++ return -EINVAL; ++ } ++ ++ reinit_completion(&src->async.result.completion); ++ ++ statesize = crypto_ahash_statesize(src->async.s); ++ if (unlikely(statesize <= 0)) { ++ return -EINVAL; ++ } ++ ++ statedata = kzalloc(statesize, GFP_KERNEL); ++ if (unlikely(statedata == NULL)) { ++ return -ENOMEM; ++ } ++ ++ ret = crypto_ahash_export(src->async.request, statedata); ++ if (unlikely(ret < 0)) { ++ if (unlikely(ret == -ENOSYS)) { ++ tfm = crypto_ahash_tfm(src->async.s); ++ derr(0, "cryptodev_hash_copy: crypto_ahash_export not implemented for " ++ "alg='%s', driver='%s'", crypto_tfm_alg_name(tfm), ++ crypto_tfm_alg_driver_name(tfm)); ++ } ++ goto out; ++ } ++ ++ ret = crypto_ahash_import(dst->async.request, statedata); ++ if (unlikely(ret == -ENOSYS)) { ++ tfm = crypto_ahash_tfm(dst->async.s); ++ derr(0, "cryptodev_hash_copy: crypto_ahash_import not implemented for " ++ "alg='%s', driver='%s'", crypto_tfm_alg_name(tfm), ++ crypto_tfm_alg_driver_name(tfm)); ++ } ++out: ++ kfree(statedata); ++ return ret; ++} ++#endif /* CIOCCPHASH */ +diff --git a/drivers/sstar/crypto/cryptodev/cryptlib.h b/drivers/sstar/crypto/cryptodev/cryptlib.h +new file mode 100644 +index 000000000000..9330ff5710ae +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/cryptlib.h +@@ -0,0 +1,109 @@ ++#ifndef CRYPTLIB_H ++# define CRYPTLIB_H ++ ++#include ++ ++struct cryptodev_result { ++ struct completion completion; ++ int err; ++}; ++ ++#include "cipherapi.h" ++ ++struct cipher_data { ++ int init; /* 0 uninitialized */ ++ int blocksize; ++ int aead; ++ int stream; ++ int ivsize; ++ int alignmask; ++ struct { ++ /* block ciphers */ ++ cryptodev_crypto_blkcipher_t *s; ++ cryptodev_blkcipher_request_t *request; ++ ++ /* AEAD ciphers */ ++ struct crypto_aead *as; ++ struct aead_request *arequest; ++ ++ struct cryptodev_result result; ++ uint8_t iv[EALG_MAX_BLOCK_LEN]; ++ } async; ++}; ++ ++int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name, ++ uint8_t *key, size_t keylen, int stream, int aead); ++void cryptodev_cipher_deinit(struct cipher_data *cdata); ++int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead); ++int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop, ++ int aead); ++ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata, ++ const struct scatterlist *sg1, ++ struct scatterlist *sg2, size_t len); ++ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata, ++ const struct scatterlist *sg1, ++ struct scatterlist *sg2, size_t len); ++ ++/* AEAD */ ++static inline void cryptodev_cipher_auth(struct cipher_data *cdata, ++ struct scatterlist *sg1, size_t len) ++{ ++ /* for some reason we _have_ to call that even for zero length sgs */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)) ++ aead_request_set_assoc(cdata->async.arequest, len ? sg1 : NULL, len); ++#else ++ aead_request_set_ad(cdata->async.arequest, len); ++#endif ++} ++ ++static inline void cryptodev_cipher_set_tag_size(struct cipher_data *cdata, int size) ++{ ++ if (likely(cdata->aead != 0)) ++ crypto_aead_setauthsize(cdata->async.as, size); ++} ++ ++static inline int cryptodev_cipher_get_tag_size(struct cipher_data *cdata) ++{ ++ if (likely(cdata->init && cdata->aead != 0)) ++ return crypto_aead_authsize(cdata->async.as); ++ else ++ return 0; ++} ++ ++static inline void cryptodev_cipher_set_iv(struct cipher_data *cdata, ++ void *iv, size_t iv_size) ++{ ++ memcpy(cdata->async.iv, iv, min(iv_size, sizeof(cdata->async.iv))); ++} ++ ++static inline void cryptodev_cipher_get_iv(struct cipher_data *cdata, ++ void *iv, size_t iv_size) ++{ ++ memcpy(iv, cdata->async.iv, min(iv_size, sizeof(cdata->async.iv))); ++} ++ ++/* Hash */ ++struct hash_data { ++ int init; /* 0 uninitialized */ ++ int digestsize; ++ int alignmask; ++ struct { ++ struct crypto_ahash *s; ++ struct cryptodev_result result; ++ struct ahash_request *request; ++ } async; ++}; ++ ++int cryptodev_hash_final(struct hash_data *hdata, void *output); ++ssize_t cryptodev_hash_update(struct hash_data *hdata, ++ struct scatterlist *sg, size_t len); ++int cryptodev_hash_reset(struct hash_data *hdata); ++void cryptodev_hash_deinit(struct hash_data *hdata); ++int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name, ++ int hmac_mode, void *mackey, size_t mackeylen); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++int cryptodev_hash_copy(struct hash_data *dst, struct hash_data *src); ++#endif ++ ++ ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/crypto/cryptodev.h b/drivers/sstar/crypto/cryptodev/crypto/cryptodev.h +new file mode 100644 +index 000000000000..c09cce8e3ebc +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/crypto/cryptodev.h +@@ -0,0 +1,315 @@ ++/* This is a source compatible implementation with the original API of ++ * cryptodev by Angelos D. Keromytis, found at openbsd cryptodev.h. ++ * Placed under public domain */ ++ ++#ifndef L_CRYPTODEV_H ++#define L_CRYPTODEV_H ++ ++#include ++#include ++#ifndef __KERNEL__ ++#define __user ++#endif ++ ++/* API extensions for linux */ ++#define CRYPTO_HMAC_MAX_KEY_LEN 512 ++#define CRYPTO_CIPHER_MAX_KEY_LEN 64 ++ ++/* All the supported algorithms ++ */ ++enum cryptodev_crypto_op_t { ++ CRYPTO_DES_CBC = 1, ++ CRYPTO_3DES_CBC = 2, ++ CRYPTO_BLF_CBC = 3, ++ CRYPTO_CAST_CBC = 4, ++ CRYPTO_SKIPJACK_CBC = 5, ++ CRYPTO_MD5_HMAC = 6, ++ CRYPTO_SHA1_HMAC = 7, ++ CRYPTO_RIPEMD160_HMAC = 8, ++ CRYPTO_MD5_KPDK = 9, ++ CRYPTO_SHA1_KPDK = 10, ++ CRYPTO_RIJNDAEL128_CBC = 11, ++ CRYPTO_AES_CBC = CRYPTO_RIJNDAEL128_CBC, ++ CRYPTO_ARC4 = 12, ++ CRYPTO_MD5 = 13, ++ CRYPTO_SHA1 = 14, ++ CRYPTO_DEFLATE_COMP = 15, ++ CRYPTO_NULL = 16, ++ CRYPTO_LZS_COMP = 17, ++ CRYPTO_SHA2_256_HMAC = 18, ++ CRYPTO_SHA2_384_HMAC = 19, ++ CRYPTO_SHA2_512_HMAC = 20, ++ CRYPTO_AES_CTR = 21, ++ CRYPTO_AES_XTS = 22, ++ CRYPTO_AES_ECB = 23, ++ CRYPTO_AES_GCM = 50, ++ ++ CRYPTO_CAMELLIA_CBC = 101, ++ CRYPTO_RIPEMD160, ++ CRYPTO_SHA2_224, ++ CRYPTO_SHA2_256, ++ CRYPTO_SHA2_384, ++ CRYPTO_SHA2_512, ++ CRYPTO_SHA2_224_HMAC, ++ CRYPTO_ALGORITHM_ALL, /* Keep updated - see below */ ++}; ++ ++#define CRYPTO_ALGORITHM_MAX (CRYPTO_ALGORITHM_ALL - 1) ++ ++/* Values for ciphers */ ++#define DES_BLOCK_LEN 8 ++#define DES3_BLOCK_LEN 8 ++#define RIJNDAEL128_BLOCK_LEN 16 ++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN ++#define CAMELLIA_BLOCK_LEN 16 ++#define BLOWFISH_BLOCK_LEN 8 ++#define SKIPJACK_BLOCK_LEN 8 ++#define CAST128_BLOCK_LEN 8 ++ ++/* the maximum of the above */ ++#define EALG_MAX_BLOCK_LEN 16 ++ ++/* Values for hashes/MAC */ ++#define AALG_MAX_RESULT_LEN 64 ++ ++/* maximum length of verbose alg names (depends on CRYPTO_MAX_ALG_NAME) */ ++#define CRYPTODEV_MAX_ALG_NAME 64 ++ ++#define HASH_MAX_LEN 64 ++ ++/* input of CIOCGSESSION */ ++struct session_op { ++ /* Specify either cipher or mac ++ */ ++ __u32 cipher; /* cryptodev_crypto_op_t */ ++ __u32 mac; /* cryptodev_crypto_op_t */ ++ ++ __u32 keylen; ++ __u8 __user *key; ++ __u32 mackeylen; ++ __u8 __user *mackey; ++ ++ __u32 ses; /* session identifier */ ++}; ++ ++struct session_info_op { ++ __u32 ses; /* session identifier */ ++ ++ /* verbose names for the requested ciphers */ ++ struct alg_info { ++ char cra_name[CRYPTODEV_MAX_ALG_NAME]; ++ char cra_driver_name[CRYPTODEV_MAX_ALG_NAME]; ++ } cipher_info, hash_info; ++ ++ __u16 alignmask; /* alignment constraints */ ++ __u32 flags; /* SIOP_FLAGS_* */ ++}; ++ ++/* If this flag is set then this algorithm uses ++ * a driver only available in kernel (software drivers, ++ * or drivers based on instruction sets do not set this flag). ++ * ++ * If multiple algorithms are involved (as in AEAD case), then ++ * if one of them is kernel-driver-only this flag will be set. ++ */ ++#define SIOP_FLAG_KERNEL_DRIVER_ONLY 1 ++ ++#define COP_ENCRYPT 0 ++#define COP_DECRYPT 1 ++ ++/* input of CIOCCRYPT */ ++struct crypt_op { ++ __u32 ses; /* session identifier */ ++ __u16 op; /* COP_ENCRYPT or COP_DECRYPT */ ++ __u16 flags; /* see COP_FLAG_* */ ++ __u32 len; /* length of source data */ ++ __u8 __user *src; /* source data */ ++ __u8 __user *dst; /* pointer to output data */ ++ /* pointer to output data for hash/MAC operations */ ++ __u8 __user *mac; ++ /* initialization vector for encryption operations */ ++ __u8 __user *iv; ++}; ++ ++/* input of CIOCAUTHCRYPT */ ++struct crypt_auth_op { ++ __u32 ses; /* session identifier */ ++ __u16 op; /* COP_ENCRYPT or COP_DECRYPT */ ++ __u16 flags; /* see COP_FLAG_AEAD_* */ ++ __u32 len; /* length of source data */ ++ __u32 auth_len; /* length of auth data */ ++ __u8 __user *auth_src; /* authenticated-only data */ ++ ++ /* The current implementation is more efficient if data are ++ * encrypted in-place (src==dst). */ ++ __u8 __user *src; /* data to be encrypted and authenticated */ ++ __u8 __user *dst; /* pointer to output data. Must have ++ * space for tag. For TLS this should be at least ++ * len + tag_size + block_size for padding */ ++ ++ __u8 __user *tag; /* where the tag will be copied to. TLS mode ++ * doesn't use that as tag is copied to dst. ++ * SRTP mode copies tag there. */ ++ __u32 tag_len; /* the length of the tag. Use zero for digest size or max tag. */ ++ ++ /* initialization vector for encryption operations */ ++ __u8 __user *iv; ++ __u32 iv_len; ++}; ++ ++/* In plain AEAD mode the following are required: ++ * flags : 0 ++ * iv : the initialization vector (12 bytes) ++ * auth_len: the length of the data to be authenticated ++ * auth_src: the data to be authenticated ++ * len : length of data to be encrypted ++ * src : the data to be encrypted ++ * dst : space to hold encrypted data. It must have ++ * at least a size of len + tag_size. ++ * tag_size: the size of the desired authentication tag or zero to use ++ * the maximum tag output. ++ * ++ * Note tag isn't being used because the Linux AEAD interface ++ * copies the tag just after data. ++ */ ++ ++/* In TLS mode (used for CBC ciphers that required padding) ++ * the following are required: ++ * flags : COP_FLAG_AEAD_TLS_TYPE ++ * iv : the initialization vector ++ * auth_len: the length of the data to be authenticated only ++ * len : length of data to be encrypted ++ * auth_src: the data to be authenticated ++ * src : the data to be encrypted ++ * dst : space to hold encrypted data (preferably in-place). It must have ++ * at least a size of len + tag_size + blocksize. ++ * tag_size: the size of the desired authentication tag or zero to use ++ * the default mac output. ++ * ++ * Note that the padding used is the minimum padding. ++ */ ++ ++/* In SRTP mode the following are required: ++ * flags : COP_FLAG_AEAD_SRTP_TYPE ++ * iv : the initialization vector ++ * auth_len: the length of the data to be authenticated. This must ++ * include the SRTP header + SRTP payload (data to be encrypted) + rest ++ * ++ * len : length of data to be encrypted ++ * auth_src: pointer the data to be authenticated. Should point at the same buffer as src. ++ * src : pointer to the data to be encrypted. ++ * dst : This is mandatory to be the same as src (in-place only). ++ * tag_size: the size of the desired authentication tag or zero to use ++ * the default mac output. ++ * tag : Pointer to an address where the authentication tag will be copied. ++ */ ++ ++ ++/* struct crypt_op flags */ ++ ++#define COP_FLAG_NONE (0 << 0) /* totally no flag */ ++#define COP_FLAG_UPDATE (1 << 0) /* multi-update hash mode */ ++#define COP_FLAG_FINAL (1 << 1) /* multi-update final hash mode */ ++#define COP_FLAG_WRITE_IV (1 << 2) /* update the IV during operation */ ++#define COP_FLAG_NO_ZC (1 << 3) /* do not zero-copy */ ++#define COP_FLAG_AEAD_TLS_TYPE (1 << 4) /* authenticate and encrypt using the ++ * TLS protocol rules */ ++#define COP_FLAG_AEAD_SRTP_TYPE (1 << 5) /* authenticate and encrypt using the ++ * SRTP protocol rules */ ++#define COP_FLAG_RESET (1 << 6) /* multi-update reset the state. ++ * should be used in combination ++ * with COP_FLAG_UPDATE */ ++ ++ ++/* Stuff for bignum arithmetic and public key ++ * cryptography - not supported yet by linux ++ * cryptodev. ++ */ ++ ++#define CRYPTO_ALG_FLAG_SUPPORTED 1 ++#define CRYPTO_ALG_FLAG_RNG_ENABLE 2 ++#define CRYPTO_ALG_FLAG_DSA_SHA 4 ++ ++struct crparam { ++ __u8 *crp_p; ++ __u32 crp_nbits; ++}; ++ ++#define CRK_MAXPARAM 8 ++ ++/* input of CIOCKEY */ ++struct crypt_kop { ++ __u32 crk_op; /* cryptodev_crk_op_t */ ++ __u32 crk_status; ++ __u16 crk_iparams; ++ __u16 crk_oparams; ++ __u32 crk_pad1; ++ struct crparam crk_param[CRK_MAXPARAM]; ++}; ++ ++enum cryptodev_crk_op_t { ++ CRK_MOD_EXP = 0, ++ CRK_MOD_EXP_CRT = 1, ++ CRK_DSA_SIGN = 2, ++ CRK_DSA_VERIFY = 3, ++ CRK_DH_COMPUTE_KEY = 4, ++ CRK_ALGORITHM_ALL ++}; ++ ++/* input of CIOCCPHASH ++ * dst_ses : destination session identifier ++ * src_ses : source session identifier ++ * dst_ses must have been created with CIOGSESSION first ++ */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++struct cphash_op { ++ __u32 dst_ses; ++ __u32 src_ses; ++}; ++#endif ++ ++#define CRK_ALGORITHM_MAX (CRK_ALGORITHM_ALL-1) ++ ++/* features to be queried with CIOCASYMFEAT ioctl ++ */ ++#define CRF_MOD_EXP (1 << CRK_MOD_EXP) ++#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) ++#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) ++#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) ++#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) ++ ++ ++/* ioctl's. Compatible with old linux cryptodev.h ++ */ ++#define CRIOGET _IOWR('c', 101, __u32) ++#define CIOCGSESSION _IOWR('c', 102, struct session_op) ++#define CIOCFSESSION _IOW('c', 103, __u32) ++#define CIOCCRYPT _IOWR('c', 104, struct crypt_op) ++#define CIOCKEY _IOWR('c', 105, struct crypt_kop) ++#define CIOCASYMFEAT _IOR('c', 106, __u32) ++#define CIOCGSESSINFO _IOWR('c', 107, struct session_info_op) ++ ++/* to indicate that CRIOGET is not required in linux ++ */ ++#define CRIOGET_NOT_NEEDED 1 ++ ++/* additional ioctls for AEAD */ ++#define CIOCAUTHCRYPT _IOWR('c', 109, struct crypt_auth_op) ++ ++/* additional ioctls for asynchronous operation. ++ * These are conditionally enabled since version 1.6. ++ */ ++#define CIOCASYNCCRYPT _IOW('c', 110, struct crypt_op) ++#define CIOCASYNCFETCH _IOR('c', 111, struct crypt_op) ++ ++/* additional ioctl for copying of hash/mac session state data ++ * between sessions. ++ * The cphash_op parameter should contain the session id of ++ * the source and destination sessions. Both sessions ++ * must have been created with CIOGSESSION. ++ */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ++#define CIOCCPHASH _IOW('c', 112, struct cphash_op) ++#endif ++ ++#endif /* L_CRYPTODEV_H */ +diff --git a/drivers/sstar/crypto/cryptodev/cryptodev_int.h b/drivers/sstar/crypto/cryptodev/cryptodev_int.h +new file mode 100755 +index 000000000000..d7660fac5344 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/cryptodev_int.h +@@ -0,0 +1,145 @@ ++/* cipher stuff */ ++#ifndef CRYPTODEV_INT_H ++# define CRYPTODEV_INT_H ++ ++#include ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)) ++# define reinit_completion(x) INIT_COMPLETION(*(x)) ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFX "cryptodev: " ++#define dprintk(level, severity, format, a...) \ ++ do { \ ++ if (level <= cryptodev_verbosity) \ ++ printk(severity PFX "%s[%u] (%s:%u): " format "\n", \ ++ current->comm, current->pid, \ ++ __func__, __LINE__, \ ++ ##a); \ ++ } while (0) ++#define derr(level, format, a...) dprintk(level, KERN_ERR, format, ##a) ++#define dwarning(level, format, a...) dprintk(level, KERN_WARNING, format, ##a) ++#define dinfo(level, format, a...) dprintk(level, KERN_INFO, format, ##a) ++#define ddebug(level, format, a...) dprintk(level, KERN_DEBUG, format, ##a) ++ ++ ++extern int cryptodev_verbosity; ++ ++struct fcrypt { ++ struct list_head list; ++ struct mutex sem; ++}; ++ ++/* compatibility stuff */ ++#ifdef CONFIG_COMPAT ++#include ++ ++/* input of CIOCGSESSION */ ++struct compat_session_op { ++ /* Specify either cipher or mac ++ */ ++ uint32_t cipher; /* cryptodev_crypto_op_t */ ++ uint32_t mac; /* cryptodev_crypto_op_t */ ++ ++ uint32_t keylen; ++ compat_uptr_t key; /* pointer to key data */ ++ uint32_t mackeylen; ++ compat_uptr_t mackey; /* pointer to mac key data */ ++ ++ uint32_t ses; /* session identifier */ ++}; ++ ++/* input of CIOCCRYPT */ ++struct compat_crypt_op { ++ uint32_t ses; /* session identifier */ ++ uint16_t op; /* COP_ENCRYPT or COP_DECRYPT */ ++ uint16_t flags; /* see COP_FLAG_* */ ++ uint32_t len; /* length of source data */ ++ compat_uptr_t src; /* source data */ ++ compat_uptr_t dst; /* pointer to output data */ ++ compat_uptr_t mac;/* pointer to output data for hash/MAC operations */ ++ compat_uptr_t iv;/* initialization vector for encryption operations */ ++}; ++ ++/* compat ioctls, defined for the above structs */ ++#define COMPAT_CIOCGSESSION _IOWR('c', 102, struct compat_session_op) ++#define COMPAT_CIOCCRYPT _IOWR('c', 104, struct compat_crypt_op) ++#define COMPAT_CIOCASYNCCRYPT _IOW('c', 107, struct compat_crypt_op) ++#define COMPAT_CIOCASYNCFETCH _IOR('c', 108, struct compat_crypt_op) ++ ++#endif /* CONFIG_COMPAT */ ++ ++/* kernel-internal extension to struct crypt_op */ ++struct kernel_crypt_op { ++ struct crypt_op cop; ++ ++ int ivlen; ++ __u8 iv[EALG_MAX_BLOCK_LEN]; ++ ++ int digestsize; ++ uint8_t hash_output[AALG_MAX_RESULT_LEN]; ++ ++ struct task_struct *task; ++ struct mm_struct *mm; ++}; ++ ++struct kernel_crypt_auth_op { ++ struct crypt_auth_op caop; ++ ++ int dst_len; /* based on src_len + pad + tag */ ++ int ivlen; ++ __u8 iv[EALG_MAX_BLOCK_LEN]; ++ ++ struct task_struct *task; ++ struct mm_struct *mm; ++}; ++ ++/* auth */ ++ ++int kcaop_from_user(struct kernel_crypt_auth_op *kcop, ++ struct fcrypt *fcr, void __user *arg); ++int kcaop_to_user(struct kernel_crypt_auth_op *kcaop, ++ struct fcrypt *fcr, void __user *arg); ++int crypto_auth_run(struct fcrypt *fcr, struct kernel_crypt_auth_op *kcaop); ++int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop); ++ ++#include ++ ++/* other internal structs */ ++struct csession { ++ struct list_head entry; ++ struct mutex sem; ++ struct cipher_data cdata; ++ struct hash_data hdata; ++ uint32_t sid; ++ uint32_t alignmask; ++ ++ unsigned int array_size; ++ unsigned int used_pages; /* the number of pages that are used */ ++ /* the number of pages marked as NOT-writable; they preceed writeables */ ++ unsigned int readonly_pages; ++ struct page **pages; ++ struct scatterlist *sg; ++}; ++ ++struct csession *crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid); ++ ++static inline void crypto_put_session(struct csession *ses_ptr) ++{ ++ mutex_unlock(&ses_ptr->sem); ++} ++int adjust_sg_array(struct csession *ses, int pagecount); ++ ++#endif /* CRYPTODEV_INT_H */ +diff --git a/drivers/sstar/crypto/cryptodev/examples/aes-gcm.c b/drivers/sstar/crypto/cryptodev/examples/aes-gcm.c +new file mode 100755 +index 000000000000..6791f4eb13b0 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/aes-gcm.c +@@ -0,0 +1,139 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "aes-gcm.h" ++ ++int aes_gcm_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) ++{ ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->cfd = cfd; ++ ++ ctx->sess.cipher = CRYPTO_AES_GCM; ++ ctx->sess.keylen = key_size; ++ ctx->sess.key = (void*)key; ++ if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return -1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = ctx->sess.ses; ++ if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return -1; ++ } ++ printf("Got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { ++ printf("Note: This is not an accelerated cipher\n"); ++ } ++ /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ ++ ctx->alignmask = siop.alignmask; ++#endif ++ return 0; ++} ++ ++void aes_gcm_ctx_deinit(struct cryptodev_ctx* ctx) ++{ ++ if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++} ++ ++int ++aes_gcm_encrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ const void* plaintext, void* ciphertext, size_t size) ++{ ++ struct crypt_auth_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_ENCRYPT; ++ cryp.auth_len = auth_size; ++ cryp.auth_src = (void*)auth; ++ cryp.len = size; ++ cryp.src = (void*)plaintext; ++ cryp.dst = ciphertext; ++ if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { ++ perror("ioctl(CIOCAUTHCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int ++aes_gcm_decrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ const void* ciphertext, void* plaintext, size_t size) ++{ ++ struct crypt_auth_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_DECRYPT; ++ cryp.auth_len = auth_size; ++ cryp.auth_src = (void*)auth; ++ cryp.len = size; ++ cryp.src = (void*)ciphertext; ++ cryp.dst = plaintext; ++ if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { ++ perror("ioctl(CIOCAUTHCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/examples/aes-gcm.h b/drivers/sstar/crypto/cryptodev/examples/aes-gcm.h +new file mode 100755 +index 000000000000..1ddc5fe464fc +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/aes-gcm.h +@@ -0,0 +1,28 @@ ++#ifndef AES_H ++# define AES_H ++ ++#include ++ ++struct cryptodev_ctx { ++ int cfd; ++ struct session_op sess; ++ uint16_t alignmask; ++}; ++ ++#define AES_BLOCK_SIZE 16 ++ ++int aes_gcm_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); ++void aes_gcm_ctx_deinit(); ++ ++/* Note that encryption assumes that ciphertext has enough size ++ * for the tag to be appended. In decryption the tag is assumed ++ * to be the last bytes of ciphertext. ++ */ ++int aes_gcm_encrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ const void* plaintext, void* ciphertext, size_t size); ++int aes_gcm_decrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ const void* ciphertext, void* plaintext, size_t size); ++ ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/examples/aes-sha1.c b/drivers/sstar/crypto/cryptodev/examples/aes-sha1.c +new file mode 100755 +index 000000000000..e93e3c4461b2 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/aes-sha1.c +@@ -0,0 +1,139 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "aes-sha1.h" ++ ++/* This is the TLS version of AES-CBC with HMAC-SHA1. ++ */ ++ ++int aes_sha1_ctx_init(struct cryptodev_ctx* ctx, int cfd, ++ const uint8_t *key, unsigned int key_size, ++ const uint8_t *mac_key, unsigned int mac_key_size) ++{ ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->cfd = cfd; ++ ++ ctx->sess.cipher = CRYPTO_AES_CBC; ++ ctx->sess.keylen = key_size; ++ ctx->sess.key = (void*)key; ++ ++ ctx->sess.mac = CRYPTO_SHA1_HMAC; ++ ctx->sess.mackeylen = mac_key_size; ++ ctx->sess.mackey = (void*)mac_key; ++ ++ if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return -1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = ctx->sess.ses; ++ if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return -1; ++ } ++ printf("Got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { ++ printf("Note: This is not an accelerated cipher\n"); ++ } ++ /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ ++ ctx->alignmask = siop.alignmask; ++#endif ++ return 0; ++} ++ ++void aes_sha1_ctx_deinit(struct cryptodev_ctx* ctx) ++{ ++ if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++} ++ ++int ++aes_sha1_encrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ void* plaintext, size_t size) ++{ ++ struct crypt_auth_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_ENCRYPT; ++ cryp.auth_len = auth_size; ++ cryp.auth_src = (void*)auth; ++ cryp.len = size; ++ cryp.src = (void*)plaintext; ++ cryp.dst = plaintext; ++ cryp.flags = COP_FLAG_AEAD_TLS_TYPE; ++ if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { ++ perror("ioctl(CIOCAUTHCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int ++aes_sha1_decrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ void* ciphertext, size_t size) ++{ ++ struct crypt_auth_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_DECRYPT; ++ cryp.auth_len = auth_size; ++ cryp.auth_src = (void*)auth; ++ cryp.len = size; ++ cryp.src = (void*)ciphertext; ++ cryp.dst = ciphertext; ++ cryp.flags = COP_FLAG_AEAD_TLS_TYPE; ++ if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { ++ perror("ioctl(CIOCAUTHCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/examples/aes-sha1.h b/drivers/sstar/crypto/cryptodev/examples/aes-sha1.h +new file mode 100755 +index 000000000000..a07334cf3a4a +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/aes-sha1.h +@@ -0,0 +1,31 @@ ++#ifndef AES_H ++# define AES_H ++ ++#include ++ ++struct cryptodev_ctx { ++ int cfd; ++ struct session_op sess; ++ uint16_t alignmask; ++}; ++ ++#define AES_BLOCK_SIZE 16 ++ ++int aes_sha1_ctx_init(struct cryptodev_ctx* ctx, int cfd, ++ const uint8_t *key, unsigned int key_size, ++ const uint8_t *mac_key, unsigned int mac_key_size); ++void aes_sha1_ctx_deinit(); ++ ++/* Note that encryption assumes that ciphertext has enough size ++ * for the tag and padding to be appended. ++ * ++ * Only in-place encryption and decryption are supported. ++ */ ++int aes_sha1_encrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ void* plaintext, size_t size); ++int aes_sha1_decrypt(struct cryptodev_ctx* ctx, const void* iv, ++ const void* auth, size_t auth_size, ++ void* ciphertext, size_t size); ++ ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/examples/aes-sstar-unique.c b/drivers/sstar/crypto/cryptodev/examples/aes-sstar-unique.c +new file mode 100755 +index 000000000000..30aacc13759e +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/aes-sstar-unique.c +@@ -0,0 +1,233 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "aes.h" ++ ++#define KEY_SIZE 16 ++ ++ ++int aes_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) ++{ ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->cfd = cfd; ++ ++ ctx->sess.cipher = CRYPTO_AES_CBC; ++ ctx->sess.keylen = key_size; ++ ctx->sess.key = (void*)key; ++ if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return -1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ memset(&siop, 0, sizeof(siop)); ++ ++ siop.ses = ctx->sess.ses; ++ if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return -1; ++ } ++ printf("Got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { ++ printf("Note: This is not an accelerated cipher\n"); ++ } ++ /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ ++ ctx->alignmask = siop.alignmask; ++#endif ++ return 0; ++} ++ ++void aes_ctx_deinit(struct cryptodev_ctx* ctx) ++{ ++ if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++} ++ ++int ++aes_encrypt(struct cryptodev_ctx* ctx, const void* iv, const void* plaintext, void* ciphertext, size_t size) ++{ ++ struct crypt_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.len = size; ++ cryp.src = (void*)plaintext; ++ cryp.dst = ciphertext; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int ++aes_decrypt(struct cryptodev_ctx* ctx, const void* iv, const void* ciphertext, void* plaintext, size_t size) ++{ ++ struct crypt_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.len = size; ++ cryp.src = (void*)ciphertext; ++ cryp.dst = plaintext; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_DECRYPT; ++ if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++char __attribute__ ((aligned (64))) ciphertext1[AES_BLOCK_SIZE] = {0}; ++char __attribute__ ((aligned (64))) decrypttext1[AES_BLOCK_SIZE] = {0}; ++ ++static int test_aes(int cfd) ++{ ++ char plaintext1_raw[AES_BLOCK_SIZE + 63], *plaintext1; ++ ++ char iv1[AES_BLOCK_SIZE]; ++ uint8_t key1[KEY_SIZE] = { 'S', 'S', 't', 'a', 'r', 'U', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ int i; ++ struct cryptodev_ctx ctx; ++ ++ aes_ctx_init(&ctx, cfd, key1, sizeof(key1)); ++ printf("key:\n"); ++ for(i=0; i ++#include ++#include ++#include ++#include ++#include ++#include "aes.h" ++ ++#define KEY_SIZE 16 ++ ++ ++int aes_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) ++{ ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->cfd = cfd; ++ ++ ctx->sess.cipher = CRYPTO_AES_CBC; ++ ctx->sess.keylen = key_size; ++ ctx->sess.key = (void*)key; ++ if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return -1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ memset(&siop, 0, sizeof(siop)); ++ ++ siop.ses = ctx->sess.ses; ++ if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return -1; ++ } ++ printf("Got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { ++ printf("Note: This is not an accelerated cipher\n"); ++ } ++ /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ ++ ctx->alignmask = siop.alignmask; ++#endif ++ return 0; ++} ++ ++void aes_ctx_deinit(struct cryptodev_ctx* ctx) ++{ ++ if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++} ++ ++int ++aes_encrypt(struct cryptodev_ctx* ctx, const void* iv, const void* plaintext, void* ciphertext, size_t size) ++{ ++ struct crypt_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.len = size; ++ cryp.src = (void*)plaintext; ++ cryp.dst = ciphertext; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int ++aes_decrypt(struct cryptodev_ctx* ctx, const void* iv, const void* ciphertext, void* plaintext, size_t size) ++{ ++ struct crypt_op cryp; ++ void* p; ++ ++ /* check plaintext and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); ++ if (plaintext != p) { ++ fprintf(stderr, "plaintext is not aligned\n"); ++ return -1; ++ } ++ ++ p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); ++ if (ciphertext != p) { ++ fprintf(stderr, "ciphertext is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.len = size; ++ cryp.src = (void*)ciphertext; ++ cryp.dst = plaintext; ++ cryp.iv = (void*)iv; ++ cryp.op = COP_DECRYPT; ++ if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static int test_aes(int cfd) ++{ ++ char plaintext1_raw[AES_BLOCK_SIZE + 63], *plaintext1; ++ char ciphertext1[AES_BLOCK_SIZE] = { 0xdf, 0x55, 0x6a, 0x33, 0x43, 0x8d, 0xb8, 0x7b, 0xc4, 0x1b, 0x17, 0x52, 0xc5, 0x5e, 0x5e, 0x49 }; ++ char iv1[AES_BLOCK_SIZE]; ++ uint8_t key1[KEY_SIZE] = { 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ char plaintext2_data[AES_BLOCK_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00 }; ++ char plaintext2_raw[AES_BLOCK_SIZE + 63], *plaintext2; ++ char ciphertext2[AES_BLOCK_SIZE] = { 0xb7, 0x97, 0x2b, 0x39, 0x41, 0xc4, 0x4b, 0x90, 0xaf, 0xa7, 0xb2, 0x64, 0xbf, 0xba, 0x73, 0x87 }; ++ char iv2[AES_BLOCK_SIZE]; ++ uint8_t key2[KEY_SIZE]; ++ struct cryptodev_ctx ctx; ++ ++ aes_ctx_init(&ctx, cfd, key1, sizeof(key1)); ++ ++ if (ctx.alignmask) ++ plaintext1 = (char *)(((unsigned long)plaintext1_raw + ctx.alignmask) & ~ctx.alignmask); ++ else ++ plaintext1 = plaintext1_raw; ++ ++ memset(plaintext1, 0x0, AES_BLOCK_SIZE); ++ memset(iv1, 0x0, sizeof(iv1)); ++ ++ aes_encrypt(&ctx, iv1, plaintext1, plaintext1, AES_BLOCK_SIZE); ++ ++ /* Verify the result */ ++ if (memcmp(plaintext1, ciphertext1, AES_BLOCK_SIZE) != 0) { ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ return -1; ++ } ++ ++ aes_ctx_deinit(&ctx); ++ ++ /* Test 2 */ ++ ++ memset(key2, 0x0, sizeof(key2)); ++ memset(iv2, 0x0, sizeof(iv2)); ++ ++ aes_ctx_init(&ctx, cfd, key2, sizeof(key2)); ++ ++ if (ctx.alignmask) { ++ plaintext2 = (char *)(((unsigned long)plaintext2_raw + ctx.alignmask) & ~ctx.alignmask); ++ } else { ++ plaintext2 = plaintext2_raw; ++ } ++ memcpy(plaintext2, plaintext2_data, AES_BLOCK_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ aes_encrypt(&ctx, iv2, plaintext2, plaintext2, AES_BLOCK_SIZE); ++ ++ /* Verify the result */ ++ if (memcmp(plaintext2, ciphertext2, AES_BLOCK_SIZE) != 0) { ++ int i; ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ printf("plaintext:"); ++ for (i = 0; i < AES_BLOCK_SIZE; i++) { ++ printf("%02x ", plaintext2[i]); ++ } ++ printf("ciphertext:"); ++ for (i = 0; i < AES_BLOCK_SIZE; i++) { ++ printf("%02x ", ciphertext2[i]); ++ } ++ printf("\n"); ++ return 1; ++ } ++ ++ aes_ctx_deinit(&ctx); ++ ++ printf("AES Test passed\n"); ++ ++ return 0; ++} ++ ++int ++main() ++{ ++ int cfd = -1; ++ ++ /* Open the crypto device */ ++ cfd = open("/dev/crypto", O_RDWR, 0); ++ if (cfd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ /* Run the test itself */ ++ if (test_aes(cfd)) ++ return 1; ++ ++ /* Close the original descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/examples/aes.h b/drivers/sstar/crypto/cryptodev/examples/aes.h +new file mode 100755 +index 000000000000..ade90c92b58c +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/aes.h +@@ -0,0 +1,19 @@ ++#ifndef AES_H ++# define AES_H ++ ++#include ++ ++struct cryptodev_ctx { ++ int cfd; ++ struct session_op sess; ++ uint16_t alignmask; ++}; ++ ++#define AES_BLOCK_SIZE 16 ++ ++int aes_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); ++void aes_ctx_deinit(); ++int aes_encrypt(struct cryptodev_ctx* ctx, const void* iv, const void* plaintext, void* ciphertext, size_t size); ++int aes_decrypt(struct cryptodev_ctx* ctx, const void* iv, const void* ciphertext, void* plaintext, size_t size); ++ ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/examples/readme b/drivers/sstar/crypto/cryptodev/examples/readme +new file mode 100755 +index 000000000000..4359fff42c67 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/readme +@@ -0,0 +1,8 @@ ++${CROSS_COMPILE}gcc -static aes.c -o aes -I.. ++${CROSS_COMPILE}strip aes ++${CROSS_COMPILE}gcc -static sha.c -o sha -I.. ++${CROSS_COMPILE}strip sha ++${CROSS_COMPILE}gcc -static sha-copy.c -o sha-copy -I.. ++${CROSS_COMPILE}strip sha-copy ++${CROSS_COMPILE}gcc -static aes-sstar-unique.c -o aes-sstar-unique -I.. ++${CROSS_COMPILE}strip aes-sstar-unique +\ No newline at end of file +diff --git a/drivers/sstar/crypto/cryptodev/examples/sha-copy.c b/drivers/sstar/crypto/cryptodev/examples/sha-copy.c +new file mode 100755 +index 000000000000..6bf8d2f8451b +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/sha-copy.c +@@ -0,0 +1,240 @@ ++/* ++ * Demo on how to use /dev/crypto device for calculating a hash ++ * at once, using init->hash, and compare it to using: ++ * using init->update->final, and init->update->copy-> update -> final ++ * init->----\> update -> final ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "sha-copy.h" ++ ++int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) ++{ ++ struct session_info_op siop; ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->cfd = cfd; ++ ++ if (key == NULL) ++ ctx->sess.mac = CRYPTO_SHA1; ++ else { ++ ctx->sess.mac = CRYPTO_SHA1_HMAC; ++ ctx->sess.mackeylen = key_size; ++ ctx->sess.mackey = (void*)key; ++ } ++ if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return -1; ++ } ++#ifdef DEBUG ++ fprintf(stderr, "sha_ctx_init: cfd=%d, ses=%04x\n", ctx->cfd, ctx->sess.ses); ++#endif ++ ++ siop.ses = ctx->sess.ses; ++ if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return -1; ++ } ++ printf("Got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { ++ printf("Note: This is not an accelerated cipher\n"); ++ } ++ return 0; ++} ++ ++static int sha_call_crypt(struct cryptodev_ctx* ctx, const void* text, ++ size_t size, void *digest, unsigned int flags) ++{ ++ struct crypt_op cryp; ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Fill out the fields with text, size, digest result and flags */ ++ cryp.ses = ctx->sess.ses; ++ cryp.len = size; ++ cryp.src = (void*)text; ++ cryp.mac = digest; ++ cryp.flags = flags; ++#ifdef DEBUG ++ fprintf(stderr, "sha_call_crypt: cfd=%d, ses=%04x, CIOCCRYPT(len=%d, src='%s', flags=%04x)\n", ++ ctx->cfd, ctx->sess.ses, cryp.len, (char *)cryp.src, cryp.flags); ++#endif ++ return ioctl(ctx->cfd, CIOCCRYPT, &cryp); ++} ++ ++int sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) ++{ ++#ifdef DEBUG ++ fprintf(stderr, "sha_hash: cfd=%d, ses=%04x, text='%s', size=%ld\n", ++ ctx->cfd, ctx->sess.ses, (char *) text, size); ++#endif ++ if (sha_call_crypt(ctx, text, size, digest, 0)) { ++ perror("sha_hash: ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int sha_update(struct cryptodev_ctx* ctx, const void* text, size_t size) ++{ ++#ifdef DEBUG ++ fprintf(stderr, "sha_update: cfd=%d, ses=%04x, text='%s', size=%ld\n", ++ ctx->cfd, ctx->sess.ses, (char *) text, size); ++#endif ++ if (sha_call_crypt(ctx, text, size, NULL, COP_FLAG_UPDATE)) { ++ perror("sha_update: ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int sha_copy(struct cryptodev_ctx* to_ctx, const struct cryptodev_ctx* from_ctx) ++{ ++ struct cphash_op cphash; ++ ++#ifdef DEBUG ++ fprintf(stderr, "sha_copy: from= cfd=%d, ses=%04x\n" ++ " to= cfd=%d, ses=%04x\n", ++ from_ctx->cfd, from_ctx->sess.ses, to_ctx->cfd, to_ctx->sess.ses); ++#endif ++ memset(&cphash, 0, sizeof(cphash)); ++ ++ cphash.src_ses = from_ctx->sess.ses; ++ cphash.dst_ses = to_ctx->sess.ses; ++ if (ioctl(to_ctx->cfd, CIOCCPHASH, &cphash)) { ++ perror("ioctl(CIOCCPHASH)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int sha_final(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) ++{ ++#ifdef DEBUG ++ fprintf(stderr, "sha_final: cfd=%d, ses=%04x, text='%s', size=%ld\n", ++ ctx->cfd, ctx->sess.ses, (char *) text, size); ++#endif ++ if (sha_call_crypt(ctx, text, size, digest, COP_FLAG_FINAL)) { ++ perror("sha_final: ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++void sha_ctx_deinit(struct cryptodev_ctx* ctx) ++{ ++#ifdef DEBUG ++ fprintf(stderr, "sha_ctx_deinit: cfd=%d, ses=%04x\n", ctx->cfd, ctx->sess.ses); ++#endif ++ if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++} ++ ++static int print_digest(uint8_t *digest, uint8_t *expected) ++{ ++ int i; ++ ++ if (memcmp(digest, expected, 20) != 0) { ++ fprintf(stderr, "SHA1 hashing failed\n"); ++ } ++ ++ printf("digest: "); ++ for (i = 0; i < 20; i++) { ++ printf("%02x:", *digest); ++ digest++; ++ } ++ printf("\n"); ++} ++ ++int ++main() ++{ ++ int cfd = -1; ++ struct cryptodev_ctx ctx1, ctx2; ++ uint8_t digest[20]; ++ char text[] = "The quick brown fox jumps over the lazy dog"; ++ char text1[] = "The quick brown fox"; ++ char text2[] = " jumps over the lazy dog"; ++ char text3[] = " jumps over the lazy dogs"; ++ uint8_t expected[] = "\x2f\xd4\xe1\xc6\x7a\x2d\x28\xfc\xed\x84\x9e\xe1\xbb\x76\xe7\x39\x1b\x93\xeb\x12"; ++ uint8_t expected2[] = "\xf8\xc3\xc5\x41\x25\x7a\x6c\x31\xf6\xfb\xc6\x97\xa5\x0f\x46\xd9\xfc\x8b\xcc\x30"; ++ ++ /* Open the crypto device */ ++ cfd = open("/dev/crypto", O_RDWR, 0); ++ if (cfd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ printf("Computing digest in one operation\n"); ++ sha_ctx_init(&ctx1, cfd, NULL, 0); ++ sha_hash(&ctx1, text, strlen(text), digest); ++ sha_ctx_deinit(&ctx1); ++ print_digest(digest, expected); ++ ++ printf("\n\nComputing digest using update/final\n"); ++ sha_ctx_init(&ctx1, cfd, NULL, 0); ++ sha_update(&ctx1, text1, strlen(text1)); ++ sha_final(&ctx1, text2, strlen(text2), digest); ++ sha_ctx_deinit(&ctx1); ++ print_digest(digest, expected); ++ ++ printf("\n\nComputing digest using update/copy/final\n"); ++ sha_ctx_init(&ctx1, cfd, NULL, 0); ++ sha_update(&ctx1, text1, strlen(text1)); ++ sha_ctx_init(&ctx2, cfd, NULL, 0); ++ sha_copy(&ctx2, &ctx1); ++ printf("\nOriginal operation:\n"); ++ sha_update(&ctx1, text2, strlen(text2)); ++ sha_final(&ctx1, NULL, 0, digest); ++ print_digest(digest, expected); ++ printf("\nCopied operation:\n"); ++ sha_final(&ctx2, text2, strlen(text2), digest); ++ sha_ctx_deinit(&ctx1); ++ sha_ctx_deinit(&ctx2); ++ print_digest(digest, expected); ++ ++ printf("\n\nComputing digest using update/copy/final with different texts\n"); ++ sha_ctx_init(&ctx1, cfd, NULL, 0); ++ sha_update(&ctx1, text1, strlen(text1)); ++ sha_ctx_init(&ctx2, cfd, NULL, 0); ++ sha_copy(&ctx2, &ctx1); ++ printf("\nOriginal operation, with original text:\n"); ++ sha_update(&ctx1, text2, strlen(text2)); ++ sha_final(&ctx1, NULL, 0, digest); ++ print_digest(digest, expected); ++ printf("\nCopied operation, with different text:\n"); ++ sha_update(&ctx2, text3, strlen(text3)); ++ sha_final(&ctx2, NULL, 0, digest); ++ sha_ctx_deinit(&ctx1); ++ sha_ctx_deinit(&ctx2); ++ print_digest(digest, expected2); ++ ++ /* Close the original descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/examples/sha-copy.h b/drivers/sstar/crypto/cryptodev/examples/sha-copy.h +new file mode 100755 +index 000000000000..8b2114e6702c +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/sha-copy.h +@@ -0,0 +1,18 @@ ++#ifndef SHA_COPY_H ++#define SHA_COPY_H ++ ++#include ++ ++struct cryptodev_ctx { ++ int cfd; ++ struct session_op sess; ++}; ++ ++int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); ++int sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); ++int sha_update(struct cryptodev_ctx* ctx, const void* text, size_t size); ++int sha_copy(struct cryptodev_ctx* to_ctx, const struct cryptodev_ctx* from_ctx); ++int sha_final(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); ++void sha_ctx_deinit(struct cryptodev_ctx* ctx); ++ ++#endif /* SHA_COPY_H */ +diff --git a/drivers/sstar/crypto/cryptodev/examples/sha.c b/drivers/sstar/crypto/cryptodev/examples/sha.c +new file mode 100755 +index 000000000000..4f45a6b01a50 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/sha.c +@@ -0,0 +1,137 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "sha.h" ++ ++int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) ++{ ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->cfd = cfd; ++ ++ if (key == NULL) ++ ctx->sess.mac = CRYPTO_SHA1; ++ else { ++ ctx->sess.mac = CRYPTO_SHA1_HMAC; ++ ctx->sess.mackeylen = key_size; ++ ctx->sess.mackey = (void*)key; ++ } ++ if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return -1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = ctx->sess.ses; ++ if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return -1; ++ } ++ printf("Got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { ++ printf("Note: This is not an accelerated cipher\n"); ++ } ++ /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask);*/ ++ ctx->alignmask = siop.alignmask; ++#endif ++ return 0; ++} ++ ++void sha_ctx_deinit(struct cryptodev_ctx* ctx) ++{ ++ if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++} ++ ++int ++sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) ++{ ++ struct crypt_op cryp; ++ void* p; ++ ++ /* check text and ciphertext alignment */ ++ if (ctx->alignmask) { ++ p = (void*)(((unsigned long)text + ctx->alignmask) & ~ctx->alignmask); ++ if (text != p) { ++ fprintf(stderr, "text is not aligned\n"); ++ return -1; ++ } ++ } ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = ctx->sess.ses; ++ cryp.len = size; ++ cryp.src = (void*)text; ++ cryp.mac = digest; ++ if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int ++main() ++{ ++ int cfd = -1, i; ++ struct cryptodev_ctx ctx; ++ uint8_t digest[20]; ++ char text[] = "The quick brown fox jumps over the lazy dog"; ++ uint8_t expected[] = "\x2f\xd4\xe1\xc6\x7a\x2d\x28\xfc\xed\x84\x9e\xe1\xbb\x76\xe7\x39\x1b\x93\xeb\x12"; ++ ++ /* Open the crypto device */ ++ cfd = open("/dev/crypto", O_RDWR, 0); ++ if (cfd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ sha_ctx_init(&ctx, cfd, NULL, 0); ++ ++ sha_hash(&ctx, text, strlen(text), digest); ++ ++ sha_ctx_deinit(&ctx); ++ ++ printf("digest: "); ++ for (i = 0; i < 20; i++) { ++ printf("%02x:", digest[i]); ++ } ++ printf("\n"); ++ ++ if (memcmp(digest, expected, 20) != 0) { ++ fprintf(stderr, "SHA1 hashing failed\n"); ++ return 1; ++ } ++ ++ /* Close the original descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/examples/sha.h b/drivers/sstar/crypto/cryptodev/examples/sha.h +new file mode 100755 +index 000000000000..ed0b8cee4252 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/examples/sha.h +@@ -0,0 +1,16 @@ ++#ifndef SHA_H ++# define SHA_H ++ ++#include ++ ++struct cryptodev_ctx { ++ int cfd; ++ struct session_op sess; ++ uint16_t alignmask; ++}; ++ ++int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); ++void sha_ctx_deinit(); ++int sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); ++ ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/ioctl.c b/drivers/sstar/crypto/cryptodev/ioctl.c +new file mode 100755 +index 000000000000..92ee007f37c8 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/ioctl.c +@@ -0,0 +1,1220 @@ ++/* ++ * Driver for /dev/crypto device (aka CryptoDev) ++ * ++ * Copyright (c) 2004 Michal Ludvig , SuSE Labs ++ * Copyright (c) 2009,2010,2011 Nikos Mavrogiannopoulos ++ * Copyright (c) 2010 Phil Sutter ++ * ++ * This file is part of linux cryptodev. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++/* ++ * Device /dev/crypto provides an interface for ++ * accessing kernel CryptoAPI algorithms (ciphers, ++ * hashes) from userspace programs. ++ * ++ * /dev/crypto interface was originally introduced in ++ * OpenBSD and this module attempts to keep the API. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "cryptodev_int.h" ++#include "zc.h" ++#include "version.h" ++#include "cipherapi.h" ++ ++MODULE_AUTHOR("Nikos Mavrogiannopoulos "); ++MODULE_DESCRIPTION("CryptoDev driver"); ++MODULE_LICENSE("GPL"); ++ ++#define FIX_ALIGNMASK 63 ++ ++/* ====== Compile-time config ====== */ ++ ++/* Default (pre-allocated) and maximum size of the job queue. ++ * These are free, pending and done items all together. */ ++#define DEF_COP_RINGSIZE 16 ++#define MAX_COP_RINGSIZE 64 ++ ++/* ====== Module parameters ====== */ ++ ++int cryptodev_verbosity; ++module_param(cryptodev_verbosity, int, 0644); ++MODULE_PARM_DESC(cryptodev_verbosity, "0: normal, 1: verbose, 2: debug"); ++ ++/* ====== CryptoAPI ====== */ ++struct todo_list_item { ++ struct list_head __hook; ++ struct kernel_crypt_op kcop; ++ int result; ++}; ++ ++struct locked_list { ++ struct list_head list; ++ struct mutex lock; ++}; ++ ++struct crypt_priv { ++ struct fcrypt fcrypt; ++ struct locked_list free, todo, done; ++ int itemcount; ++ struct work_struct cryptask; ++ wait_queue_head_t user_waiter; ++}; ++ ++#define FILL_SG(sg, ptr, len) \ ++ do { \ ++ (sg)->page = virt_to_page(ptr); \ ++ (sg)->offset = offset_in_page(ptr); \ ++ (sg)->length = len; \ ++ (sg)->dma_address = 0; \ ++ } while (0) ++ ++/* cryptodev's own workqueue, keeps crypto tasks from disturbing the force */ ++static struct workqueue_struct *cryptodev_wq; ++ ++/* Prepare session for future use. */ ++static int ++crypto_create_session(struct fcrypt *fcr, struct session_op *sop) ++{ ++ struct csession *ses_new = NULL, *ses_ptr; ++ int ret = 0; ++ const char *alg_name = NULL; ++ const char *hash_name = NULL; ++ int hmac_mode = 1, stream = 0, aead = 0; ++ /* ++ * With composite aead ciphers, only ckey is used and it can cover all the ++ * structure space; otherwise both keys may be used simultaneously but they ++ * are confined to their spaces ++ */ ++ struct { ++ uint8_t ckey[CRYPTO_CIPHER_MAX_KEY_LEN]; ++ uint8_t mkey[CRYPTO_HMAC_MAX_KEY_LEN]; ++ /* padding space for aead keys */ ++ uint8_t pad[RTA_SPACE(sizeof(struct crypto_authenc_key_param))]; ++ } keys; ++ ++ /* Does the request make sense? */ ++ if (unlikely(!sop->cipher && !sop->mac)) { ++ ddebug(1, "Both 'cipher' and 'mac' unset."); ++ return -EINVAL; ++ } ++ ++ switch (sop->cipher) { ++ case 0: ++ break; ++ case CRYPTO_DES_CBC: ++ alg_name = "cbc(des)"; ++ break; ++ case CRYPTO_3DES_CBC: ++ alg_name = "cbc(des3_ede)"; ++ break; ++ case CRYPTO_BLF_CBC: ++ alg_name = "cbc(blowfish)"; ++ break; ++ case CRYPTO_AES_CBC: ++ alg_name = "cbc(aes)"; ++ break; ++ case CRYPTO_AES_ECB: ++ alg_name = "ecb(aes)"; ++ break; ++ case CRYPTO_CAMELLIA_CBC: ++ alg_name = "cbc(camellia)"; ++ break; ++ case CRYPTO_AES_CTR: ++ alg_name = "ctr(aes)"; ++ stream = 1; ++ break; ++ case CRYPTO_AES_GCM: ++ alg_name = "gcm(aes)"; ++ stream = 1; ++ aead = 1; ++ break; ++ case CRYPTO_NULL: ++ alg_name = "ecb(cipher_null)"; ++ stream = 1; ++ break; ++ default: ++ ddebug(1, "bad cipher: %d", sop->cipher); ++ return -EINVAL; ++ } ++ ++ switch (sop->mac) { ++ case 0: ++ break; ++ case CRYPTO_MD5_HMAC: ++ hash_name = "hmac(md5)"; ++ break; ++ case CRYPTO_RIPEMD160_HMAC: ++ hash_name = "hmac(rmd160)"; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ hash_name = "hmac(sha1)"; ++ break; ++ case CRYPTO_SHA2_224_HMAC: ++ hash_name = "hmac(sha224)"; ++ break; ++ ++ case CRYPTO_SHA2_256_HMAC: ++ hash_name = "hmac(sha256)"; ++ break; ++ case CRYPTO_SHA2_384_HMAC: ++ hash_name = "hmac(sha384)"; ++ break; ++ case CRYPTO_SHA2_512_HMAC: ++ hash_name = "hmac(sha512)"; ++ break; ++ ++ /* non-hmac cases */ ++ case CRYPTO_MD5: ++ hash_name = "md5"; ++ hmac_mode = 0; ++ break; ++ case CRYPTO_RIPEMD160: ++ hash_name = "rmd160"; ++ hmac_mode = 0; ++ break; ++ case CRYPTO_SHA1: ++ hash_name = "sha1"; ++ hmac_mode = 0; ++ break; ++ case CRYPTO_SHA2_224: ++ hash_name = "sha224"; ++ hmac_mode = 0; ++ break; ++ case CRYPTO_SHA2_256: ++ hash_name = "sha256"; ++ hmac_mode = 0; ++ break; ++ case CRYPTO_SHA2_384: ++ hash_name = "sha384"; ++ hmac_mode = 0; ++ break; ++ case CRYPTO_SHA2_512: ++ hash_name = "sha512"; ++ hmac_mode = 0; ++ break; ++ default: ++ ddebug(1, "bad mac: %d", sop->mac); ++ return -EINVAL; ++ } ++ ++ /* Create a session and put it to the list. Zeroing the structure helps ++ * also with a single exit point in case of errors */ ++ ses_new = kzalloc(sizeof(*ses_new), GFP_KERNEL); ++ if (!ses_new) ++ return -ENOMEM; ++ ++ /* Set-up crypto transform. */ ++ if (alg_name) { ++ unsigned int keylen; ++ ret = cryptodev_get_cipher_keylen(&keylen, sop, aead); ++ if (unlikely(ret < 0)) { ++ ddebug(1, "Setting key failed for %s-%zu.", ++ alg_name, (size_t)sop->keylen*8); ++ goto session_error; ++ } ++ ++ ret = cryptodev_get_cipher_key(keys.ckey, sop, aead); ++ if (unlikely(ret < 0)) ++ goto session_error; ++ ++ ret = cryptodev_cipher_init(&ses_new->cdata, alg_name, keys.ckey, ++ keylen, stream, aead); ++ if (ret < 0) { ++ ddebug(1, "Failed to load cipher for %s", alg_name); ++ ret = -EINVAL; ++ goto session_error; ++ } ++ } ++ ++ if (hash_name && aead == 0) { ++ if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) { ++ ddebug(1, "Setting key failed for %s-%zu.", ++ hash_name, (size_t)sop->mackeylen*8); ++ ret = -EINVAL; ++ goto session_error; ++ } ++ ++ if (sop->mackey && unlikely(copy_from_user(keys.mkey, sop->mackey, ++ sop->mackeylen))) { ++ ret = -EFAULT; ++ goto session_error; ++ } ++ ++ ret = cryptodev_hash_init(&ses_new->hdata, hash_name, hmac_mode, ++ keys.mkey, sop->mackeylen); ++ if (ret != 0) { ++ ddebug(1, "Failed to load hash for %s", hash_name); ++ ret = -EINVAL; ++ goto session_error; ++ } ++ ++ ret = cryptodev_hash_reset(&ses_new->hdata); ++ if (ret != 0) { ++ goto session_error; ++ } ++ } ++ ++ // ses_new->alignmask = max(ses_new->cdata.alignmask, ++ // ses_new->hdata.alignmask); ++ ses_new->alignmask = FIX_ALIGNMASK; ++ ddebug(2, "got alignmask %d", ses_new->alignmask); ++ ++ ses_new->array_size = DEFAULT_PREALLOC_PAGES; ++ ddebug(2, "preallocating for %d user pages", ses_new->array_size); ++ ses_new->pages = kzalloc(ses_new->array_size * ++ sizeof(struct page *), GFP_KERNEL); ++ ses_new->sg = kzalloc(ses_new->array_size * ++ sizeof(struct scatterlist), GFP_KERNEL); ++ if (ses_new->sg == NULL || ses_new->pages == NULL) { ++ ddebug(0, "Memory error"); ++ ret = -ENOMEM; ++ goto session_error; ++ } ++ ++ /* put the new session to the list */ ++ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); ++ mutex_init(&ses_new->sem); ++ ++ mutex_lock(&fcr->sem); ++restart: ++ list_for_each_entry(ses_ptr, &fcr->list, entry) { ++ /* Check for duplicate SID */ ++ if (unlikely(ses_new->sid == ses_ptr->sid)) { ++ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); ++ /* Unless we have a broken RNG this ++ shouldn't loop forever... ;-) */ ++ goto restart; ++ } ++ } ++ ++ list_add(&ses_new->entry, &fcr->list); ++ mutex_unlock(&fcr->sem); ++ ++ /* Fill in some values for the user. */ ++ sop->ses = ses_new->sid; ++ return 0; ++ ++ /* We count on ses_new to be initialized with zeroes ++ * Since hdata and cdata are embedded within ses_new, it follows that ++ * hdata->init and cdata->init are either zero or one as they have been ++ * initialized or not */ ++session_error: ++ cryptodev_hash_deinit(&ses_new->hdata); ++ cryptodev_cipher_deinit(&ses_new->cdata); ++ kfree(ses_new->sg); ++ kfree(ses_new->pages); ++ kfree(ses_new); ++ return ret; ++} ++ ++/* Everything that needs to be done when removing a session. */ ++static inline void ++crypto_destroy_session(struct csession *ses_ptr) ++{ ++ if (!mutex_trylock(&ses_ptr->sem)) { ++ ddebug(2, "Waiting for semaphore of sid=0x%08X", ses_ptr->sid); ++ mutex_lock(&ses_ptr->sem); ++ } ++ ddebug(2, "Removed session 0x%08X", ses_ptr->sid); ++ cryptodev_cipher_deinit(&ses_ptr->cdata); ++ cryptodev_hash_deinit(&ses_ptr->hdata); ++ ddebug(2, "freeing space for %d user pages", ses_ptr->array_size); ++ kfree(ses_ptr->pages); ++ kfree(ses_ptr->sg); ++ mutex_unlock(&ses_ptr->sem); ++ mutex_destroy(&ses_ptr->sem); ++ kfree(ses_ptr); ++} ++ ++/* Look up a session by ID and remove. */ ++static int ++crypto_finish_session(struct fcrypt *fcr, uint32_t sid) ++{ ++ struct csession *tmp, *ses_ptr; ++ struct list_head *head; ++ int ret = 0; ++ ++ mutex_lock(&fcr->sem); ++ head = &fcr->list; ++ list_for_each_entry_safe(ses_ptr, tmp, head, entry) { ++ if (ses_ptr->sid == sid) { ++ list_del(&ses_ptr->entry); ++ crypto_destroy_session(ses_ptr); ++ break; ++ } ++ } ++ ++ if (unlikely(!ses_ptr)) { ++ derr(1, "Session with sid=0x%08X not found!", sid); ++ ret = -ENOENT; ++ } ++ mutex_unlock(&fcr->sem); ++ ++ return ret; ++} ++ ++/* Remove all sessions when closing the file */ ++static int ++crypto_finish_all_sessions(struct fcrypt *fcr) ++{ ++ struct csession *tmp, *ses_ptr; ++ struct list_head *head; ++ ++ mutex_lock(&fcr->sem); ++ ++ head = &fcr->list; ++ list_for_each_entry_safe(ses_ptr, tmp, head, entry) { ++ list_del(&ses_ptr->entry); ++ crypto_destroy_session(ses_ptr); ++ } ++ mutex_unlock(&fcr->sem); ++ ++ return 0; ++} ++ ++/* Look up session by session ID. The returned session is locked. */ ++struct csession * ++crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid) ++{ ++ struct csession *ses_ptr, *retval = NULL; ++ ++ if (unlikely(fcr == NULL)) ++ return NULL; ++ ++ mutex_lock(&fcr->sem); ++ list_for_each_entry(ses_ptr, &fcr->list, entry) { ++ if (ses_ptr->sid == sid) { ++ mutex_lock(&ses_ptr->sem); ++ retval = ses_ptr; ++ break; ++ } ++ } ++ mutex_unlock(&fcr->sem); ++ ++ return retval; ++} ++ ++#ifdef CIOCCPHASH ++/* Copy the hash state from one session to another */ ++static int ++crypto_copy_hash_state(struct fcrypt *fcr, uint32_t dst_sid, uint32_t src_sid) ++{ ++ struct csession *src_ses, *dst_ses; ++ int ret; ++ ++ src_ses = crypto_get_session_by_sid(fcr, src_sid); ++ if (unlikely(src_ses == NULL)) { ++ derr(1, "Session with sid=0x%08X not found!", src_sid); ++ return -ENOENT; ++ } ++ ++ dst_ses = crypto_get_session_by_sid(fcr, dst_sid); ++ if (unlikely(dst_ses == NULL)) { ++ derr(1, "Session with sid=0x%08X not found!", dst_sid); ++ crypto_put_session(src_ses); ++ return -ENOENT; ++ } ++ ++ ret = cryptodev_hash_copy(&dst_ses->hdata, &src_ses->hdata); ++ crypto_put_session(src_ses); ++ crypto_put_session(dst_ses); ++ return ret; ++} ++#endif /* CIOCCPHASH */ ++ ++static void cryptask_routine(struct work_struct *work) ++{ ++ struct crypt_priv *pcr = container_of(work, struct crypt_priv, cryptask); ++ struct todo_list_item *item; ++ LIST_HEAD(tmp); ++ ++ /* fetch all pending jobs into the temporary list */ ++ mutex_lock(&pcr->todo.lock); ++ list_cut_position(&tmp, &pcr->todo.list, pcr->todo.list.prev); ++ mutex_unlock(&pcr->todo.lock); ++ ++ /* handle each job locklessly */ ++ list_for_each_entry(item, &tmp, __hook) { ++ item->result = crypto_run(&pcr->fcrypt, &item->kcop); ++ if (unlikely(item->result)) ++ derr(0, "crypto_run() failed: %d", item->result); ++ } ++ ++ /* push all handled jobs to the done list at once */ ++ mutex_lock(&pcr->done.lock); ++ list_splice_tail(&tmp, &pcr->done.list); ++ mutex_unlock(&pcr->done.lock); ++ ++ /* wake for POLLIN */ ++ wake_up_interruptible(&pcr->user_waiter); ++} ++ ++/* ====== /dev/crypto ====== */ ++ ++static int ++cryptodev_open(struct inode *inode, struct file *filp) ++{ ++ struct todo_list_item *tmp, *tmp_next; ++ struct crypt_priv *pcr; ++ int i; ++ ++ pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); ++ if (!pcr) ++ return -ENOMEM; ++ filp->private_data = pcr; ++ ++ mutex_init(&pcr->fcrypt.sem); ++ mutex_init(&pcr->free.lock); ++ mutex_init(&pcr->todo.lock); ++ mutex_init(&pcr->done.lock); ++ ++ INIT_LIST_HEAD(&pcr->fcrypt.list); ++ INIT_LIST_HEAD(&pcr->free.list); ++ INIT_LIST_HEAD(&pcr->todo.list); ++ INIT_LIST_HEAD(&pcr->done.list); ++ ++ INIT_WORK(&pcr->cryptask, cryptask_routine); ++ ++ init_waitqueue_head(&pcr->user_waiter); ++ ++ for (i = 0; i < DEF_COP_RINGSIZE; i++) { ++ tmp = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL); ++ if (!tmp) ++ goto err_ringalloc; ++ pcr->itemcount++; ++ ddebug(2, "allocated new item at %p", tmp); ++ list_add(&tmp->__hook, &pcr->free.list); ++ } ++ ++ ddebug(2, "Cryptodev handle initialised, %d elements in queue", ++ DEF_COP_RINGSIZE); ++ return 0; ++ ++/* In case of errors, free any memory allocated so far */ ++err_ringalloc: ++ list_for_each_entry_safe(tmp, tmp_next, &pcr->free.list, __hook) { ++ list_del(&tmp->__hook); ++ kfree(tmp); ++ } ++ mutex_destroy(&pcr->done.lock); ++ mutex_destroy(&pcr->todo.lock); ++ mutex_destroy(&pcr->free.lock); ++ mutex_destroy(&pcr->fcrypt.sem); ++ kfree(pcr); ++ filp->private_data = NULL; ++ return -ENOMEM; ++} ++ ++static int ++cryptodev_release(struct inode *inode, struct file *filp) ++{ ++ struct crypt_priv *pcr = filp->private_data; ++ struct todo_list_item *item, *item_safe; ++ int items_freed = 0; ++ ++ if (!pcr) ++ return 0; ++ ++ cancel_work_sync(&pcr->cryptask); ++ ++ list_splice_tail(&pcr->todo.list, &pcr->free.list); ++ list_splice_tail(&pcr->done.list, &pcr->free.list); ++ ++ list_for_each_entry_safe(item, item_safe, &pcr->free.list, __hook) { ++ ddebug(2, "freeing item at %p", item); ++ list_del(&item->__hook); ++ kfree(item); ++ items_freed++; ++ } ++ ++ if (items_freed != pcr->itemcount) { ++ derr(0, "freed %d items, but %d should exist!", ++ items_freed, pcr->itemcount); ++ } ++ ++ crypto_finish_all_sessions(&pcr->fcrypt); ++ ++ mutex_destroy(&pcr->done.lock); ++ mutex_destroy(&pcr->todo.lock); ++ mutex_destroy(&pcr->free.lock); ++ mutex_destroy(&pcr->fcrypt.sem); ++ ++ kfree(pcr); ++ filp->private_data = NULL; ++ ++ ddebug(2, "Cryptodev handle deinitialised, %d elements freed", ++ items_freed); ++ return 0; ++} ++ ++static int ++clonefd(struct file *filp) ++{ ++ int ret; ++ ret = get_unused_fd_flags(0); ++ if (ret >= 0) { ++ get_file(filp); ++ fd_install(ret, filp); ++ } ++ ++ return ret; ++} ++ ++#ifdef ENABLE_ASYNC ++/* enqueue a job for asynchronous completion ++ * ++ * returns: ++ * -EBUSY when there are no free queue slots left ++ * (and the number of slots has reached it MAX_COP_RINGSIZE) ++ * -EFAULT when there was a memory allocation error ++ * 0 on success */ ++static int crypto_async_run(struct crypt_priv *pcr, struct kernel_crypt_op *kcop) ++{ ++ struct todo_list_item *item = NULL; ++ ++ if (unlikely(kcop->cop.flags & COP_FLAG_NO_ZC)) ++ return -EINVAL; ++ ++ mutex_lock(&pcr->free.lock); ++ if (likely(!list_empty(&pcr->free.list))) { ++ item = list_first_entry(&pcr->free.list, ++ struct todo_list_item, __hook); ++ list_del(&item->__hook); ++ } else if (pcr->itemcount < MAX_COP_RINGSIZE) { ++ pcr->itemcount++; ++ } else { ++ mutex_unlock(&pcr->free.lock); ++ return -EBUSY; ++ } ++ mutex_unlock(&pcr->free.lock); ++ ++ if (unlikely(!item)) { ++ item = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL); ++ if (unlikely(!item)) ++ return -EFAULT; ++ dinfo(1, "increased item count to %d", pcr->itemcount); ++ } ++ ++ memcpy(&item->kcop, kcop, sizeof(struct kernel_crypt_op)); ++ ++ mutex_lock(&pcr->todo.lock); ++ list_add_tail(&item->__hook, &pcr->todo.list); ++ mutex_unlock(&pcr->todo.lock); ++ ++ queue_work(cryptodev_wq, &pcr->cryptask); ++ return 0; ++} ++ ++/* get the first completed job from the "done" queue ++ * ++ * returns: ++ * -EBUSY if no completed jobs are ready (yet) ++ * the return value of crypto_run() otherwise */ ++static int crypto_async_fetch(struct crypt_priv *pcr, ++ struct kernel_crypt_op *kcop) ++{ ++ struct todo_list_item *item; ++ int retval; ++ ++ mutex_lock(&pcr->done.lock); ++ if (list_empty(&pcr->done.list)) { ++ mutex_unlock(&pcr->done.lock); ++ return -EBUSY; ++ } ++ item = list_first_entry(&pcr->done.list, struct todo_list_item, __hook); ++ list_del(&item->__hook); ++ mutex_unlock(&pcr->done.lock); ++ ++ memcpy(kcop, &item->kcop, sizeof(struct kernel_crypt_op)); ++ retval = item->result; ++ ++ mutex_lock(&pcr->free.lock); ++ list_add_tail(&item->__hook, &pcr->free.list); ++ mutex_unlock(&pcr->free.lock); ++ ++ /* wake for POLLOUT */ ++ wake_up_interruptible(&pcr->user_waiter); ++ ++ return retval; ++} ++#endif ++ ++/* this function has to be called from process context */ ++static int fill_kcop_from_cop(struct kernel_crypt_op *kcop, struct fcrypt *fcr) ++{ ++ struct crypt_op *cop = &kcop->cop; ++ struct csession *ses_ptr; ++ int rc; ++ ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); ++ if (unlikely(!ses_ptr)) { ++ derr(1, "invalid session ID=0x%08X", cop->ses); ++ return -EINVAL; ++ } ++ kcop->ivlen = cop->iv ? ses_ptr->cdata.ivsize : 0; ++ kcop->digestsize = 0; /* will be updated during operation */ ++ ++ crypto_put_session(ses_ptr); ++ ++ kcop->task = current; ++ kcop->mm = current->mm; ++ ++ if (cop->iv) { ++ rc = copy_from_user(kcop->iv, cop->iv, kcop->ivlen); ++ if (unlikely(rc)) { ++ derr(1, "error copying IV (%d bytes), copy_from_user returned %d for address %p", ++ kcop->ivlen, rc, cop->iv); ++ return -EFAULT; ++ } ++ } ++ ++ return 0; ++} ++ ++/* this function has to be called from process context */ ++static int fill_cop_from_kcop(struct kernel_crypt_op *kcop, struct fcrypt *fcr) ++{ ++ int ret; ++ ++ if (kcop->digestsize) { ++ ret = copy_to_user(kcop->cop.mac, ++ kcop->hash_output, kcop->digestsize); ++ if (unlikely(ret)) ++ return -EFAULT; ++ } ++ if (kcop->ivlen && kcop->cop.flags & COP_FLAG_WRITE_IV) { ++ ret = copy_to_user(kcop->cop.iv, ++ kcop->iv, kcop->ivlen); ++ if (unlikely(ret)) ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static int kcop_from_user(struct kernel_crypt_op *kcop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ if (unlikely(copy_from_user(&kcop->cop, arg, sizeof(kcop->cop)))) ++ return -EFAULT; ++ ++ return fill_kcop_from_cop(kcop, fcr); ++} ++ ++static int kcop_to_user(struct kernel_crypt_op *kcop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ int ret; ++ ++ ret = fill_cop_from_kcop(kcop, fcr); ++ if (unlikely(ret)) { ++ derr(1, "Error in fill_cop_from_kcop"); ++ return ret; ++ } ++ ++ if (unlikely(copy_to_user(arg, &kcop->cop, sizeof(kcop->cop)))) { ++ derr(1, "Cannot copy to userspace"); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static inline void tfm_info_to_alg_info(struct alg_info *dst, struct crypto_tfm *tfm) ++{ ++ snprintf(dst->cra_name, CRYPTODEV_MAX_ALG_NAME, ++ "%s", crypto_tfm_alg_name(tfm)); ++ snprintf(dst->cra_driver_name, CRYPTODEV_MAX_ALG_NAME, ++ "%s", crypto_tfm_alg_driver_name(tfm)); ++} ++ ++#ifndef CRYPTO_ALG_KERN_DRIVER_ONLY ++static unsigned int is_known_accelerated(struct crypto_tfm *tfm) ++{ ++ const char *name = crypto_tfm_alg_driver_name(tfm); ++ ++ if (name == NULL) ++ return 1; /* assume accelerated */ ++ ++ /* look for known crypto engine names */ ++ if (strstr(name, "-talitos") || ++ !strncmp(name, "mv-", 3) || ++ !strncmp(name, "atmel-", 6) || ++ strstr(name, "geode") || ++ strstr(name, "hifn") || ++ strstr(name, "-ixp4xx") || ++ strstr(name, "-omap") || ++ strstr(name, "-picoxcell") || ++ strstr(name, "-s5p") || ++ strstr(name, "-ppc4xx") || ++ strstr(name, "-caam") || ++ strstr(name, "-n2")) ++ return 1; ++ ++ return 0; ++} ++#endif ++ ++static int get_session_info(struct fcrypt *fcr, struct session_info_op *siop) ++{ ++ struct csession *ses_ptr; ++ struct crypto_tfm *tfm; ++ ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, siop->ses); ++ if (unlikely(!ses_ptr)) { ++ derr(1, "invalid session ID=0x%08X", siop->ses); ++ return -EINVAL; ++ } ++ ++ siop->flags = 0; ++ ++ if (ses_ptr->cdata.init) { ++ if (ses_ptr->cdata.aead == 0) ++ tfm = cryptodev_crypto_blkcipher_tfm(ses_ptr->cdata.async.s); ++ else ++ tfm = crypto_aead_tfm(ses_ptr->cdata.async.as); ++ tfm_info_to_alg_info(&siop->cipher_info, tfm); ++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY ++ if (tfm->__crt_alg->cra_flags & CRYPTO_ALG_KERN_DRIVER_ONLY) ++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; ++#else ++ if (is_known_accelerated(tfm)) ++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; ++#endif ++ } ++ if (ses_ptr->hdata.init) { ++ tfm = crypto_ahash_tfm(ses_ptr->hdata.async.s); ++ tfm_info_to_alg_info(&siop->hash_info, tfm); ++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY ++ if (tfm->__crt_alg->cra_flags & CRYPTO_ALG_KERN_DRIVER_ONLY) ++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; ++#else ++ if (is_known_accelerated(tfm)) ++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; ++#endif ++ } ++ ++ siop->alignmask = ses_ptr->alignmask; ++ ++ crypto_put_session(ses_ptr); ++ return 0; ++} ++ ++static long ++cryptodev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg_) ++{ ++ void __user *arg = (void __user *)arg_; ++ int __user *p = arg; ++ struct session_op sop; ++ struct kernel_crypt_op kcop; ++ struct kernel_crypt_auth_op kcaop; ++ struct crypt_priv *pcr = filp->private_data; ++ struct fcrypt *fcr; ++ struct session_info_op siop; ++#ifdef CIOCCPHASH ++ struct cphash_op cphop; ++#endif ++ uint32_t ses; ++ int ret, fd; ++ ++ if (unlikely(!pcr)) ++ BUG(); ++ ++ fcr = &pcr->fcrypt; ++ ++ switch (cmd) { ++ case CIOCASYMFEAT: ++ return put_user(0, p); ++ case CRIOGET: ++ fd = clonefd(filp); ++ ret = put_user(fd, p); ++ if (unlikely(ret)) { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)) ++ sys_close(fd); ++#else ++ ksys_close(fd); ++#endif ++ return ret; ++ } ++ return ret; ++ case CIOCGSESSION: ++ if (unlikely(copy_from_user(&sop, arg, sizeof(sop)))) ++ return -EFAULT; ++ ++ ret = crypto_create_session(fcr, &sop); ++ if (unlikely(ret)) ++ return ret; ++ ret = copy_to_user(arg, &sop, sizeof(sop)); ++ if (unlikely(ret)) { ++ crypto_finish_session(fcr, sop.ses); ++ return -EFAULT; ++ } ++ return ret; ++ case CIOCFSESSION: ++ ret = get_user(ses, (uint32_t __user *)arg); ++ if (unlikely(ret)) ++ return ret; ++ ret = crypto_finish_session(fcr, ses); ++ return ret; ++ case CIOCGSESSINFO: ++ if (unlikely(copy_from_user(&siop, arg, sizeof(siop)))) ++ return -EFAULT; ++ ++ ret = get_session_info(fcr, &siop); ++ if (unlikely(ret)) ++ return ret; ++ return copy_to_user(arg, &siop, sizeof(siop)); ++#ifdef CIOCCPHASH ++ case CIOCCPHASH: ++ if (unlikely(copy_from_user(&cphop, arg, sizeof(cphop)))) ++ return -EFAULT; ++ return crypto_copy_hash_state(fcr, cphop.dst_ses, cphop.src_ses); ++#endif /* CIOCPHASH */ ++ case CIOCCRYPT: ++ if (unlikely(ret = kcop_from_user(&kcop, fcr, arg))) { ++ dwarning(1, "Error copying from user"); ++ return ret; ++ } ++ ++ ret = crypto_run(fcr, &kcop); ++ if (unlikely(ret)) { ++ dwarning(1, "Error in crypto_run"); ++ return ret; ++ } ++ ++ return kcop_to_user(&kcop, fcr, arg); ++ case CIOCAUTHCRYPT: ++ if (unlikely(ret = kcaop_from_user(&kcaop, fcr, arg))) { ++ dwarning(1, "Error copying from user"); ++ return ret; ++ } ++ ++ ret = crypto_auth_run(fcr, &kcaop); ++ if (unlikely(ret)) { ++ dwarning(1, "Error in crypto_auth_run"); ++ return ret; ++ } ++ return kcaop_to_user(&kcaop, fcr, arg); ++#ifdef ENABLE_ASYNC ++ case CIOCASYNCCRYPT: ++ if (unlikely(ret = kcop_from_user(&kcop, fcr, arg))) ++ return ret; ++ ++ return crypto_async_run(pcr, &kcop); ++ case CIOCASYNCFETCH: ++ ret = crypto_async_fetch(pcr, &kcop); ++ if (unlikely(ret)) ++ return ret; ++ ++ return kcop_to_user(&kcop, fcr, arg); ++#endif ++ default: ++ return -EINVAL; ++ } ++} ++ ++/* compatibility code for 32bit userlands */ ++#ifdef CONFIG_COMPAT ++ ++static inline void ++compat_to_session_op(struct compat_session_op *compat, struct session_op *sop) ++{ ++ sop->cipher = compat->cipher; ++ sop->mac = compat->mac; ++ sop->keylen = compat->keylen; ++ ++ sop->key = compat_ptr(compat->key); ++ sop->mackeylen = compat->mackeylen; ++ sop->mackey = compat_ptr(compat->mackey); ++ sop->ses = compat->ses; ++} ++ ++static inline void ++session_op_to_compat(struct session_op *sop, struct compat_session_op *compat) ++{ ++ compat->cipher = sop->cipher; ++ compat->mac = sop->mac; ++ compat->keylen = sop->keylen; ++ ++ compat->key = ptr_to_compat(sop->key); ++ compat->mackeylen = sop->mackeylen; ++ compat->mackey = ptr_to_compat(sop->mackey); ++ compat->ses = sop->ses; ++} ++ ++static inline void ++compat_to_crypt_op(struct compat_crypt_op *compat, struct crypt_op *cop) ++{ ++ cop->ses = compat->ses; ++ cop->op = compat->op; ++ cop->flags = compat->flags; ++ cop->len = compat->len; ++ ++ cop->src = compat_ptr(compat->src); ++ cop->dst = compat_ptr(compat->dst); ++ cop->mac = compat_ptr(compat->mac); ++ cop->iv = compat_ptr(compat->iv); ++} ++ ++static inline void ++crypt_op_to_compat(struct crypt_op *cop, struct compat_crypt_op *compat) ++{ ++ compat->ses = cop->ses; ++ compat->op = cop->op; ++ compat->flags = cop->flags; ++ compat->len = cop->len; ++ ++ compat->src = ptr_to_compat(cop->src); ++ compat->dst = ptr_to_compat(cop->dst); ++ compat->mac = ptr_to_compat(cop->mac); ++ compat->iv = ptr_to_compat(cop->iv); ++} ++ ++static int compat_kcop_from_user(struct kernel_crypt_op *kcop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ struct compat_crypt_op compat_cop; ++ ++ if (unlikely(copy_from_user(&compat_cop, arg, sizeof(compat_cop)))) ++ return -EFAULT; ++ compat_to_crypt_op(&compat_cop, &kcop->cop); ++ ++ return fill_kcop_from_cop(kcop, fcr); ++} ++ ++static int compat_kcop_to_user(struct kernel_crypt_op *kcop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ int ret; ++ struct compat_crypt_op compat_cop; ++ ++ ret = fill_cop_from_kcop(kcop, fcr); ++ if (unlikely(ret)) { ++ dwarning(1, "Error in fill_cop_from_kcop"); ++ return ret; ++ } ++ crypt_op_to_compat(&kcop->cop, &compat_cop); ++ ++ if (unlikely(copy_to_user(arg, &compat_cop, sizeof(compat_cop)))) { ++ dwarning(1, "Error copying to user"); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static long ++cryptodev_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg_) ++{ ++ void __user *arg = (void __user *)arg_; ++ struct crypt_priv *pcr = file->private_data; ++ struct fcrypt *fcr; ++ struct session_op sop; ++ struct compat_session_op compat_sop; ++ struct kernel_crypt_op kcop; ++ int ret; ++ ++ if (unlikely(!pcr)) ++ BUG(); ++ ++ fcr = &pcr->fcrypt; ++ ++ switch (cmd) { ++ case CIOCASYMFEAT: ++ case CRIOGET: ++ case CIOCFSESSION: ++ case CIOCGSESSINFO: ++ return cryptodev_ioctl(file, cmd, arg_); ++ ++ case COMPAT_CIOCGSESSION: ++ if (unlikely(copy_from_user(&compat_sop, arg, ++ sizeof(compat_sop)))) ++ return -EFAULT; ++ compat_to_session_op(&compat_sop, &sop); ++ ++ ret = crypto_create_session(fcr, &sop); ++ if (unlikely(ret)) ++ return ret; ++ ++ session_op_to_compat(&sop, &compat_sop); ++ ret = copy_to_user(arg, &compat_sop, sizeof(compat_sop)); ++ if (unlikely(ret)) { ++ crypto_finish_session(fcr, sop.ses); ++ return -EFAULT; ++ } ++ return ret; ++ ++ case COMPAT_CIOCCRYPT: ++ ret = compat_kcop_from_user(&kcop, fcr, arg); ++ if (unlikely(ret)) ++ return ret; ++ ++ ret = crypto_run(fcr, &kcop); ++ if (unlikely(ret)) ++ return ret; ++ ++ return compat_kcop_to_user(&kcop, fcr, arg); ++#ifdef ENABLE_ASYNC ++ case COMPAT_CIOCASYNCCRYPT: ++ if (unlikely(ret = compat_kcop_from_user(&kcop, fcr, arg))) ++ return ret; ++ ++ return crypto_async_run(pcr, &kcop); ++ case COMPAT_CIOCASYNCFETCH: ++ ret = crypto_async_fetch(pcr, &kcop); ++ if (unlikely(ret)) ++ return ret; ++ ++ return compat_kcop_to_user(&kcop, fcr, arg); ++#endif ++ default: ++ return -EINVAL; ++ } ++} ++ ++#endif /* CONFIG_COMPAT */ ++ ++static unsigned int cryptodev_poll(struct file *file, poll_table *wait) ++{ ++ struct crypt_priv *pcr = file->private_data; ++ unsigned int ret = 0; ++ ++ poll_wait(file, &pcr->user_waiter, wait); ++ ++ if (!list_empty_careful(&pcr->done.list)) ++ ret |= POLLIN | POLLRDNORM; ++ if (!list_empty_careful(&pcr->free.list) || pcr->itemcount < MAX_COP_RINGSIZE) ++ ret |= POLLOUT | POLLWRNORM; ++ ++ return ret; ++} ++ ++static const struct file_operations cryptodev_fops = { ++ .owner = THIS_MODULE, ++ .open = cryptodev_open, ++ .release = cryptodev_release, ++ .unlocked_ioctl = cryptodev_ioctl, ++#ifdef CONFIG_COMPAT ++ .compat_ioctl = cryptodev_compat_ioctl, ++#endif /* CONFIG_COMPAT */ ++ .poll = cryptodev_poll, ++}; ++ ++static struct miscdevice cryptodev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "crypto", ++ .fops = &cryptodev_fops, ++ .mode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH, ++}; ++ ++static int __init ++cryptodev_register(void) ++{ ++ int rc; ++ ++ rc = misc_register(&cryptodev); ++ if (unlikely(rc)) { ++ pr_err(PFX "registration of /dev/crypto failed\n"); ++ return rc; ++ } ++ ++ return 0; ++} ++ ++static void __exit ++cryptodev_deregister(void) ++{ ++ misc_deregister(&cryptodev); ++} ++ ++/* ====== Module init/exit ====== */ ++static struct ctl_table verbosity_ctl_dir[] = { ++ { ++ .procname = "cryptodev_verbosity", ++ .data = &cryptodev_verbosity, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec, ++ }, ++ {}, ++}; ++ ++static struct ctl_table verbosity_ctl_root[] = { ++ { ++ .procname = "ioctl", ++ .mode = 0555, ++ .child = verbosity_ctl_dir, ++ }, ++ {}, ++}; ++static struct ctl_table_header *verbosity_sysctl_header; ++static int __init init_cryptodev(void) ++{ ++ int rc; ++ ++ cryptodev_wq = create_workqueue("cryptodev_queue"); ++ if (unlikely(!cryptodev_wq)) { ++ pr_err(PFX "failed to allocate the cryptodev workqueue\n"); ++ return -EFAULT; ++ } ++ ++ rc = cryptodev_register(); ++ if (unlikely(rc)) { ++ destroy_workqueue(cryptodev_wq); ++ return rc; ++ } ++ ++ verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root); ++ ++ pr_info(PFX "driver %s loaded.\n", VERSION); ++ ++ return 0; ++} ++ ++static void __exit exit_cryptodev(void) ++{ ++ flush_workqueue(cryptodev_wq); ++ destroy_workqueue(cryptodev_wq); ++ ++ if (verbosity_sysctl_header) ++ unregister_sysctl_table(verbosity_sysctl_header); ++ ++ cryptodev_deregister(); ++ pr_info(PFX "driver unloaded.\n"); ++} ++ ++module_init(init_cryptodev); ++module_exit(exit_cryptodev); ++ +diff --git a/drivers/sstar/crypto/cryptodev/main.c b/drivers/sstar/crypto/cryptodev/main.c +new file mode 100755 +index 000000000000..b2e28dd53698 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/main.c +@@ -0,0 +1,267 @@ ++/* ++ * Driver for /dev/crypto device (aka CryptoDev) ++ * ++ * Copyright (c) 2004 Michal Ludvig , SuSE Labs ++ * Copyright (c) 2009-2013 Nikos Mavrogiannopoulos ++ * ++ * This file is part of linux cryptodev. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++/* ++ * Device /dev/crypto provides an interface for ++ * accessing kernel CryptoAPI algorithms (ciphers, ++ * hashes) from userspace programs. ++ * ++ * /dev/crypto interface was originally introduced in ++ * OpenBSD and this module attempts to keep the API. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cryptodev_int.h" ++#include "zc.h" ++#include "cryptlib.h" ++#include "version.h" ++ ++/* This file contains the traditional operations of encryption ++ * and hashing of /dev/crypto. ++ */ ++ ++static int ++hash_n_crypt(struct csession *ses_ptr, struct crypt_op *cop, ++ struct scatterlist *src_sg, struct scatterlist *dst_sg, ++ uint32_t len) ++{ ++ int ret; ++ ++ /* Always hash before encryption and after decryption. Maybe ++ * we should introduce a flag to switch... TBD later on. ++ */ ++ if (cop->op == COP_ENCRYPT) { ++ if (ses_ptr->hdata.init != 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ src_sg, len); ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, ++ src_sg, dst_sg, len); ++ ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ } else { ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, ++ src_sg, dst_sg, len); ++ ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ ++ if (ses_ptr->hdata.init != 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ dst_sg, len); ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ } ++ return 0; ++out_err: ++ derr(0, "CryptoAPI failure: %d", ret); ++ return ret; ++} ++ ++/* This is the main crypto function - feed it with plaintext ++ and get a ciphertext (or vice versa :-) */ ++static int ++__crypto_run_std(struct csession *ses_ptr, struct crypt_op *cop) ++{ ++ char *data; ++ char __user *src, *dst; ++ struct scatterlist sg; ++ size_t nbytes, bufsize; ++ int ret = 0; ++ ++ nbytes = cop->len; ++ data = (char *)__get_free_page(GFP_KERNEL); ++ ++ if (unlikely(!data)) { ++ derr(1, "Error getting free page."); ++ return -ENOMEM; ++ } ++ ++ bufsize = PAGE_SIZE < nbytes ? PAGE_SIZE : nbytes; ++ ++ src = cop->src; ++ dst = cop->dst; ++ ++ while (nbytes > 0) { ++ size_t current_len = nbytes > bufsize ? bufsize : nbytes; ++ ++ if (unlikely(copy_from_user(data, src, current_len))) { ++ derr(1, "Error copying %zu bytes from user address %p.", current_len, src); ++ ret = -EFAULT; ++ break; ++ } ++ ++ sg_init_one(&sg, data, current_len); ++ ++ ret = hash_n_crypt(ses_ptr, cop, &sg, &sg, current_len); ++ ++ if (unlikely(ret)) { ++ derr(1, "hash_n_crypt failed."); ++ break; ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ if (unlikely(copy_to_user(dst, data, current_len))) { ++ derr(1, "could not copy to user."); ++ ret = -EFAULT; ++ break; ++ } ++ } ++ ++ dst += current_len; ++ nbytes -= current_len; ++ src += current_len; ++ } ++ ++ free_page((unsigned long)data); ++ return ret; ++} ++ ++ ++ ++/* This is the main crypto function - zero-copy edition */ ++static int ++__crypto_run_zc(struct csession *ses_ptr, struct kernel_crypt_op *kcop) ++{ ++ struct scatterlist *src_sg, *dst_sg; ++ struct crypt_op *cop = &kcop->cop; ++ int ret = 0; ++ ++ ret = get_userbuf(ses_ptr, cop->src, cop->len, cop->dst, cop->len, ++ kcop->task, kcop->mm, &src_sg, &dst_sg); ++ if (unlikely(ret)) { ++ derr(1, "Error getting user pages. Falling back to non zero copy."); ++ return __crypto_run_std(ses_ptr, cop); ++ } ++ ++ ret = hash_n_crypt(ses_ptr, cop, src_sg, dst_sg, cop->len); ++ ++ release_user_pages(ses_ptr); ++ return ret; ++} ++ ++int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop) ++{ ++ struct csession *ses_ptr; ++ struct crypt_op *cop = &kcop->cop; ++ int ret = 0; ++ ++ if (unlikely(cop->op != COP_ENCRYPT && cop->op != COP_DECRYPT)) { ++ ddebug(1, "invalid operation op=%u", cop->op); ++ return -EINVAL; ++ } ++ ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); ++ if (unlikely(!ses_ptr)) { ++ derr(1, "invalid session ID=0x%08X", cop->ses); ++ return -EINVAL; ++ } ++ ++ if (ses_ptr->hdata.init != 0 && (cop->flags == 0 || cop->flags & COP_FLAG_RESET)) { ++ ret = cryptodev_hash_reset(&ses_ptr->hdata); ++ if (unlikely(ret)) { ++ derr(1, "error in cryptodev_hash_reset()"); ++ goto out_unlock; ++ } ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ int blocksize = ses_ptr->cdata.blocksize; ++ ++ if (unlikely(cop->len % blocksize)) { ++ derr(1, "data size (%u) isn't a multiple of block size (%u)", ++ cop->len, blocksize); ++ ret = -EINVAL; ++ goto out_unlock; ++ } ++ ++ cryptodev_cipher_set_iv(&ses_ptr->cdata, kcop->iv, ++ min(ses_ptr->cdata.ivsize, kcop->ivlen)); ++ } ++ ++ if (likely(cop->len)) { ++ if (!(cop->flags & COP_FLAG_NO_ZC)) { ++ if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->src, ses_ptr->alignmask + 1))) { ++ dwarning(2, "source address %p is not %d byte aligned - disabling zero copy", ++ cop->src, ses_ptr->alignmask + 1); ++ cop->flags |= COP_FLAG_NO_ZC; ++ } ++ ++ if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->dst, ses_ptr->alignmask + 1))) { ++ dwarning(2, "destination address %p is not %d byte aligned - disabling zero copy", ++ cop->dst, ses_ptr->alignmask + 1); ++ cop->flags |= COP_FLAG_NO_ZC; ++ } ++ } ++ ++ if (cop->flags & COP_FLAG_NO_ZC) ++ ret = __crypto_run_std(ses_ptr, &kcop->cop); ++ else ++ ret = __crypto_run_zc(ses_ptr, kcop); ++ if (unlikely(ret)) ++ goto out_unlock; ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ cryptodev_cipher_get_iv(&ses_ptr->cdata, kcop->iv, ++ min(ses_ptr->cdata.ivsize, kcop->ivlen)); ++ } ++ ++ if (ses_ptr->hdata.init != 0 && ++ ((cop->flags & COP_FLAG_FINAL) || ++ (!(cop->flags & COP_FLAG_UPDATE) || cop->len == 0))) { ++ ++ ret = cryptodev_hash_final(&ses_ptr->hdata, kcop->hash_output); ++ if (unlikely(ret)) { ++ derr(0, "CryptoAPI failure: %d", ret); ++ goto out_unlock; ++ } ++ kcop->digestsize = ses_ptr->hdata.digestsize; ++ } ++ ++out_unlock: ++ crypto_put_session(ses_ptr); ++ return ret; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/Makefile b/drivers/sstar/crypto/cryptodev/tests/Makefile +new file mode 100755 +index 000000000000..7a99cd8192f4 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/Makefile +@@ -0,0 +1,49 @@ ++CFLAGS += -I.. $(CRYPTODEV_CFLAGS) -Wall -Werror ++ ++CC := $(CROSS_COMPILE)gcc ++ ++comp_progs := cipher_comp hash_comp hmac_comp ++ ++hostprogs := cipher cipher-aead hmac speed async_cipher async_hmac \ ++ async_speed sha_speed hashcrypt_speed fullspeed cipher-gcm \ ++ cipher-aead-srtp $(comp_progs) ++ ++cipher-objs := cipher.o ++cipher-aead-objs := cipher-aead.o ++hmac-objs := hmac.o ++speed-objs := speed.c ++fullspeed-objs := fullspeed.c ++sha-speed-objs := sha_speed.c ++async-cipher-objs := async_cipher.o ++async-hmac-objs := async_hmac.o ++async-speed-objs := async_speed.o ++hashcrypt-speed-objs := hashcrypt_speed.c ++ ++prefix ?= /usr/local ++execprefix ?= $(prefix) ++bindir = $(execprefix)/bin ++ ++all: $(hostprogs) ++ ++check: $(hostprogs) ++ ./cipher ++ ./hmac ++ ./async_cipher ++ ./async_hmac ++ ./cipher-aead-srtp ++ ./cipher-gcm ++ ./cipher-aead ++ ++install: ++ install -d $(DESTDIR)/$(bindir) ++ for prog in $(hostprogs); do \ ++ install -m 755 $$prog $(DESTDIR)/$(bindir); \ ++ done ++ ++clean: ++ rm -f *.o *~ $(hostprogs) ++ ++${comp_progs}: LDLIBS += -lssl -lcrypto ++${comp_progs}: %: %.o openssl_wrapper.o ++ ++.PHONY: all clean check install +diff --git a/drivers/sstar/crypto/cryptodev/tests/async_cipher.c b/drivers/sstar/crypto/cryptodev/tests/async_cipher.c +new file mode 100755 +index 000000000000..7a184e5acec2 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/async_cipher.c +@@ -0,0 +1,339 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "asynchelper.h" ++#include "testhelper.h" ++ ++#ifdef ENABLE_ASYNC ++ ++static int debug = 0; ++ ++#define DATA_SIZE 8*1024 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++ ++static int ++test_crypto(int cfd) ++{ ++ uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; ++ uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; ++ uint8_t iv[BLOCK_SIZE]; ++ uint8_t key[KEY_SIZE]; ++ ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ struct crypt_op cryp; ++ ++ if (debug) printf("running %s\n", __func__); ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ memset(key, 0x33, sizeof(key)); ++ memset(iv, 0x03, sizeof(iv)); ++ ++ /* Get crypto session for AES128 */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ if (debug) printf("%s: got the session\n", __func__); ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ plaintext = buf_align(plaintext_raw, siop.alignmask); ++ ciphertext = buf_align(ciphertext_raw, siop.alignmask); ++#else ++ plaintext = plaintext_raw; ++ ciphertext = ciphertext_raw; ++#endif ++ memset(plaintext, 0x15, DATA_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = DATA_SIZE; ++ cryp.src = plaintext; ++ cryp.dst = ciphertext; ++ cryp.iv = iv; ++ cryp.op = COP_ENCRYPT; ++ ++ DO_OR_DIE(do_async_crypt(cfd, &cryp), 0); ++ DO_OR_DIE(do_async_fetch(cfd, &cryp), 0); ++ ++ if (debug) printf("%s: data encrypted\n", __func__); ++ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ if (debug) printf("%s: session finished\n", __func__); ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ if (debug) printf("%s: got new session\n", __func__); ++ ++ /* Decrypt data.encrypted to data.decrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = DATA_SIZE; ++ cryp.src = ciphertext; ++ cryp.dst = ciphertext; ++ cryp.iv = iv; ++ cryp.op = COP_DECRYPT; ++ ++ DO_OR_DIE(do_async_crypt(cfd, &cryp), 0); ++ DO_OR_DIE(do_async_fetch(cfd, &cryp), 0); ++ ++ if (debug) printf("%s: data encrypted\n", __func__); ++ ++ /* Verify the result */ ++ if (memcmp(plaintext, ciphertext, DATA_SIZE) != 0) { ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ return 1; ++ } else if (debug) ++ printf("Test passed\n"); ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int test_aes(int cfd) ++{ ++ uint8_t plaintext1_raw[BLOCK_SIZE + 63], *plaintext1; ++ uint8_t ciphertext1[BLOCK_SIZE] = { 0xdf, 0x55, 0x6a, 0x33, 0x43, 0x8d, 0xb8, 0x7b, 0xc4, 0x1b, 0x17, 0x52, 0xc5, 0x5e, 0x5e, 0x49 }; ++ uint8_t iv1[BLOCK_SIZE]; ++ uint8_t key1[KEY_SIZE] = { 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ uint8_t plaintext2_data[BLOCK_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00 }; ++ uint8_t plaintext2_raw[BLOCK_SIZE + 63], *plaintext2; ++ uint8_t ciphertext2[BLOCK_SIZE] = { 0xb7, 0x97, 0x2b, 0x39, 0x41, 0xc4, 0x4b, 0x90, 0xaf, 0xa7, 0xb2, 0x64, 0xbf, 0xba, 0x73, 0x87 }; ++ uint8_t iv2[BLOCK_SIZE]; ++ uint8_t key2[KEY_SIZE]; ++ ++ struct session_op sess1, sess2; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop1, siop2; ++#endif ++ struct crypt_op cryp1, cryp2; ++ ++ memset(&sess1, 0, sizeof(sess1)); ++ memset(&sess2, 0, sizeof(sess2)); ++ memset(&cryp1, 0, sizeof(cryp1)); ++ memset(&cryp2, 0, sizeof(cryp2)); ++ ++ /* Get crypto session for AES128 */ ++ sess1.cipher = CRYPTO_AES_CBC; ++ sess1.keylen = KEY_SIZE; ++ sess1.key = key1; ++ if (ioctl(cfd, CIOCGSESSION, &sess1)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop1.ses = sess1.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop1)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ plaintext1 = buf_align(plaintext1_raw, siop1.alignmask); ++#else ++ plaintext1 = plaintext1_raw; ++#endif ++ memset(plaintext1, 0x0, BLOCK_SIZE); ++ ++ memset(iv1, 0x0, sizeof(iv1)); ++ memset(key2, 0x0, sizeof(key2)); ++ ++ /* Get second crypto session for AES128 */ ++ sess2.cipher = CRYPTO_AES_CBC; ++ sess2.keylen = KEY_SIZE; ++ sess2.key = key2; ++ if (ioctl(cfd, CIOCGSESSION, &sess2)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop2.ses = sess2.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop2)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ plaintext2 = buf_align(plaintext2_raw, siop2.alignmask); ++#else ++ plaintext2 = plaintext2_raw; ++#endif ++ memcpy(plaintext2, plaintext2_data, BLOCK_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp1.ses = sess1.ses; ++ cryp1.len = BLOCK_SIZE; ++ cryp1.src = plaintext1; ++ cryp1.dst = plaintext1; ++ cryp1.iv = iv1; ++ cryp1.op = COP_ENCRYPT; ++ ++ DO_OR_DIE(do_async_crypt(cfd, &cryp1), 0); ++ if (debug) printf("cryp1 written out\n"); ++ ++ memset(iv2, 0x0, sizeof(iv2)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp2.ses = sess2.ses; ++ cryp2.len = BLOCK_SIZE; ++ cryp2.src = plaintext2; ++ cryp2.dst = plaintext2; ++ cryp2.iv = iv2; ++ cryp2.op = COP_ENCRYPT; ++ ++ DO_OR_DIE(do_async_crypt(cfd, &cryp2), 0); ++ if (debug) printf("cryp2 written out\n"); ++ ++ DO_OR_DIE(do_async_fetch(cfd, &cryp1), 0); ++ DO_OR_DIE(do_async_fetch(cfd, &cryp2), 0); ++ if (debug) printf("cryp1 + cryp2 successfully read\n"); ++ ++ /* Verify the result */ ++ if (memcmp(plaintext1, ciphertext1, BLOCK_SIZE) != 0) { ++ int i; ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ printf("plaintext:"); ++ for (i = 0; i < BLOCK_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", plaintext1[i]); ++ } ++ printf("ciphertext:"); ++ for (i = 0; i < BLOCK_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", ciphertext1[i]); ++ } ++ printf("\n"); ++ return 1; ++ } else { ++ if (debug) printf("result 1 passed\n"); ++ } ++ ++ /* Test 2 */ ++ ++ /* Verify the result */ ++ if (memcmp(plaintext2, ciphertext2, BLOCK_SIZE) != 0) { ++ int i; ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ printf("plaintext:"); ++ for (i = 0; i < BLOCK_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", plaintext2[i]); ++ } ++ printf("ciphertext:"); ++ for (i = 0; i < BLOCK_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", ciphertext2[i]); ++ } ++ printf("\n"); ++ return 1; ++ } else { ++ if (debug) printf("result 2 passed\n"); ++ } ++ ++ if (debug) printf("AES Test passed\n"); ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess1.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ if (ioctl(cfd, CIOCFSESSION, &sess2.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++int ++main(int argc, char** argv) ++{ ++ int fd = -1, cfd = -1; ++ ++ if (argc > 1) debug = 1; ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Clone file descriptor */ ++ if (ioctl(fd, CRIOGET, &cfd)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ /* Run the test itself */ ++ if (test_aes(cfd)) ++ return 1; ++ ++ if (test_crypto(cfd)) ++ return 1; ++ ++ /* Close cloned descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ /* Close the original descriptor */ ++ if (close(fd)) { ++ perror("close(fd)"); ++ return 1; ++ } ++ ++ return 0; ++} ++#else ++int ++main(int argc, char** argv) ++{ ++ return (0); ++} ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/tests/async_hmac.c b/drivers/sstar/crypto/cryptodev/tests/async_hmac.c +new file mode 100755 +index 000000000000..014b8ed7e32d +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/async_hmac.c +@@ -0,0 +1,301 @@ ++/* ++ * Demo on how to use /dev/crypto device for HMAC. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "asynchelper.h" ++ ++#ifdef ENABLE_ASYNC ++ ++static int debug = 0; ++ ++#define DATA_SIZE 4096 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++#define SHA1_HASH_LEN 20 ++ ++static int ++test_crypto(int cfd) ++{ ++ struct { ++ uint8_t in[DATA_SIZE], ++ encrypted[DATA_SIZE], ++ decrypted[DATA_SIZE], ++ iv[BLOCK_SIZE], ++ key[KEY_SIZE]; ++ } data; ++ struct session_op sess; ++ struct crypt_op cryp; ++ uint8_t mac[AALG_MAX_RESULT_LEN]; ++ uint8_t oldmac[AALG_MAX_RESULT_LEN]; ++ uint8_t md5_hmac_out[] = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7\x38"; ++ uint8_t sha1_out[] = "\x8f\x82\x03\x94\xf9\x53\x35\x18\x20\x45\xda\x24\xf3\x4d\xe5\x2b\xf8\xbc\x34\x32"; ++ int i; ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Use the garbage that is on the stack :-) */ ++ /* memset(&data, 0, sizeof(data)); */ ++ ++ /* SHA1 plain test */ ++ memset(mac, 0, sizeof(mac)); ++ ++ sess.cipher = 0; ++ sess.mac = CRYPTO_SHA1; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ cryp.ses = sess.ses; ++ cryp.len = sizeof("what do ya want for nothing?")-1; ++ cryp.src = (uint8_t *)"what do ya want for nothing?"; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ ++ DO_OR_DIE(do_async_crypt(cfd, &cryp), 0); ++ DO_OR_DIE(do_async_fetch(cfd, &cryp), 0); ++ ++ if (memcmp(mac, sha1_out, 20)!=0) { ++ printf("mac: "); ++ for (i=0;i ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef ENABLE_ASYNC ++ ++static double udifftimeval(struct timeval start, struct timeval end) ++{ ++ return (double)(end.tv_usec - start.tv_usec) + ++ (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; ++} ++ ++static volatile int must_finish; ++static struct pollfd pfd; ++ ++static void alarm_handler(int signo) ++{ ++ must_finish = 1; ++ pfd.events = POLLIN; ++} ++ ++static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; ++ ++static void value2human(double bytes, double time, double* data, double* speed,char* metric) ++{ ++ int unit = 0; ++ ++ *data = bytes; ++ while (*data > 1024 && units[unit + 1]) { ++ *data /= 1024; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", units[unit]); ++} ++ ++ ++int encrypt_data(struct session_op *sess, int fdc, int chunksize, int alignmask) ++{ ++ struct crypt_op cop; ++ char *buffer[64], iv[32]; ++ static int val = 23; ++ struct timeval start, end; ++ double total = 0; ++ double secs, ddata, dspeed; ++ char metric[16]; ++ int rc, wqueue = 0, bufidx = 0; ++ ++ memset(iv, 0x23, 32); ++ ++ printf("\tEncrypting in chunks of %d bytes: ", chunksize); ++ fflush(stdout); ++ ++ for (rc = 0; rc < 64; rc++) { ++ if (alignmask) { ++ if (posix_memalign((void **)(buffer + rc), alignmask + 1, chunksize)) { ++ printf("posix_memalign() failed!\n"); ++ return 1; ++ } ++ } else { ++ if (!(buffer[rc] = malloc(chunksize))) { ++ perror("malloc()"); ++ return 1; ++ } ++ } ++ memset(buffer[rc], val++, chunksize); ++ } ++ pfd.fd = fdc; ++ pfd.events = POLLOUT | POLLIN; ++ ++ must_finish = 0; ++ alarm(5); ++ ++ gettimeofday(&start, NULL); ++ do { ++ if ((rc = poll(&pfd, 1, 100)) < 0) { ++ if (errno & (ERESTART | EINTR)) ++ continue; ++ fprintf(stderr, "errno = %d ", errno); ++ perror("poll()"); ++ return 1; ++ } ++ ++ if (pfd.revents & POLLOUT) { ++ memset(&cop, 0, sizeof(cop)); ++ cop.ses = sess->ses; ++ cop.len = chunksize; ++ cop.iv = (unsigned char *)iv; ++ cop.op = COP_ENCRYPT; ++ cop.src = cop.dst = (unsigned char *)buffer[bufidx]; ++ bufidx = (bufidx + 1) % 64; ++ ++ if (ioctl(fdc, CIOCASYNCCRYPT, &cop)) { ++ perror("ioctl(CIOCASYNCCRYPT)"); ++ return 1; ++ } ++ wqueue++; ++ } ++ if (pfd.revents & POLLIN) { ++ if (ioctl(fdc, CIOCASYNCFETCH, &cop)) { ++ perror("ioctl(CIOCASYNCFETCH)"); ++ return 1; ++ } ++ wqueue--; ++ total += cop.len; ++ } ++ } while(!must_finish || wqueue); ++ gettimeofday(&end, NULL); ++ ++ secs = udifftimeval(start, end)/ 1000000.0; ++ ++ value2human(total, secs, &ddata, &dspeed, metric); ++ printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); ++ printf ("%.2f %s/sec\n", dspeed, metric); ++ ++ for (rc = 0; rc < 64; rc++) ++ free(buffer[rc]); ++ return 0; ++} ++ ++int main(void) ++{ ++ int fd, i, fdc = -1, alignmask = 0; ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ char keybuf[32]; ++ ++ signal(SIGALRM, alarm_handler); ++ ++ if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { ++ perror("open()"); ++ return 1; ++ } ++ if (ioctl(fd, CRIOGET, &fdc)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ fprintf(stderr, "Testing NULL cipher: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_NULL; ++ sess.keylen = 0; ++ sess.key = (unsigned char *)keybuf; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ alignmask = siop.alignmask; ++#endif ++ ++ for (i = 256; i <= (64 * 4096); i *= 2) { ++ if (encrypt_data(&sess, fdc, i, alignmask)) ++ break; ++ } ++ ++ fprintf(stderr, "\nTesting AES-128-CBC cipher: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = 16; ++ memset(keybuf, 0x42, 16); ++ sess.key = (unsigned char *)keybuf; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ alignmask = siop.alignmask; ++#endif ++ ++ for (i = 256; i <= (64 * 1024); i *= 2) { ++ if (encrypt_data(&sess, fdc, i, alignmask)) ++ break; ++ } ++ ++ close(fdc); ++ close(fd); ++ return 0; ++} ++ ++#else ++int ++main(int argc, char** argv) ++{ ++ return (0); ++} ++#endif +diff --git a/drivers/sstar/crypto/cryptodev/tests/asynchelper.h b/drivers/sstar/crypto/cryptodev/tests/asynchelper.h +new file mode 100755 +index 000000000000..b5ab16c8fd72 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/asynchelper.h +@@ -0,0 +1,54 @@ ++#ifndef __ASYNCHELPER_H ++#define __ASYNCHELPER_H ++ ++/* poll until POLLOUT, then call CIOCASYNCCRYPT */ ++inline int do_async_crypt(int cfd, struct crypt_op *cryp) ++{ ++ struct pollfd pfd; ++ ++ pfd.fd = cfd; ++ pfd.events = POLLOUT; ++ ++ if (poll(&pfd, 1, -1) < 1) { ++ perror("poll()"); ++ return 1; ++ } ++ ++ if (ioctl(cfd, CIOCASYNCCRYPT, cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ return 0; ++} ++ ++/* poll until POLLIN, then call CIOCASYNCFETCH */ ++inline int do_async_fetch(int cfd, struct crypt_op *cryp) ++{ ++ struct pollfd pfd; ++ ++ pfd.fd = cfd; ++ pfd.events = POLLIN; ++ ++ if (poll(&pfd, 1, -1) < 1) { ++ perror("poll()"); ++ return 1; ++ } ++ ++ if (ioctl(cfd, CIOCASYNCFETCH, cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ return 0; ++} ++ ++/* Check return value of stmt for identity with goodval. If they ++ * don't match, call return with the value of stmt. */ ++#define DO_OR_DIE(stmt, goodval) { \ ++ int __rc_val; \ ++ if ((__rc_val = stmt) != goodval) { \ ++ perror("DO_OR_DIE(" #stmt "," #goodval ")"); \ ++ return __rc_val; \ ++ } \ ++} ++ ++#endif /* __ASYNCHELPER_H */ +diff --git a/drivers/sstar/crypto/cryptodev/tests/cipher-aead-srtp.c b/drivers/sstar/crypto/cryptodev/tests/cipher-aead-srtp.c +new file mode 100755 +index 000000000000..b1b0a219a1d6 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/cipher-aead-srtp.c +@@ -0,0 +1,595 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "testhelper.h" ++ ++#define DATA_SIZE (8*1024) ++#define HEADER_SIZE 193 ++#define PLAINTEXT_SIZE 1021 ++#define FOOTER_SIZE 15 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++ ++#define MAC_SIZE 20 /* SHA1 */ ++ ++static int debug = 0; ++ ++static int ++get_sha1_hmac(int cfd, void* key, int key_size, void* data, int data_size, void* mac) ++{ ++ struct session_op sess; ++ struct crypt_op cryp; ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ sess.cipher = 0; ++ sess.mac = CRYPTO_SHA1_HMAC; ++ sess.mackeylen = key_size; ++ sess.mackey = key; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = data_size; ++ cryp.src = data; ++ cryp.dst = NULL; ++ cryp.iv = NULL; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void print_buf(char* desc, unsigned char* buf, int size) ++{ ++int i; ++ fputs(desc, stderr); ++ for (i=0;i 1) debug = 1; ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Clone file descriptor */ ++ if (ioctl(fd, CRIOGET, &cfd)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ /* Run the test itself */ ++ ++ if (test_crypto(cfd)) ++ return 1; ++ ++ if (test_encrypt_decrypt(cfd)) ++ return 1; ++ ++ if (test_encrypt_decrypt_error(cfd,0)) ++ return 1; ++ ++ if (test_encrypt_decrypt_error(cfd,1)) ++ return 1; ++ ++ /* Close cloned descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ /* Close the original descriptor */ ++ if (close(fd)) { ++ perror("close(fd)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/tests/cipher-aead.c b/drivers/sstar/crypto/cryptodev/tests/cipher-aead.c +new file mode 100755 +index 000000000000..305b7206f872 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/cipher-aead.c +@@ -0,0 +1,575 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "testhelper.h" ++ ++#define DATA_SIZE (8*1024) ++#define AUTH_SIZE 31 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++ ++#define MAC_SIZE 20 /* SHA1 */ ++ ++static int debug = 0; ++ ++static int ++get_sha1_hmac(int cfd, void* key, int key_size, void* data1, int data1_size, void* data2, int data2_size, void* mac) ++{ ++ struct session_op sess; ++ struct crypt_op cryp; ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ sess.cipher = 0; ++ sess.mac = CRYPTO_SHA1_HMAC; ++ sess.mackeylen = key_size; ++ sess.mackey = key; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = data1_size; ++ cryp.src = data1; ++ cryp.dst = NULL; ++ cryp.iv = NULL; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ cryp.flags = COP_FLAG_UPDATE; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ cryp.ses = sess.ses; ++ cryp.len = data2_size; ++ cryp.src = data2; ++ cryp.dst = NULL; ++ cryp.iv = NULL; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ cryp.flags = COP_FLAG_FINAL; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void print_buf(char* desc, unsigned char* buf, int size) ++{ ++int i; ++ fputs(desc, stdout); ++ for (i=0;i ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "testhelper.h" ++ ++#define DATA_SIZE (8*1024) ++#define AUTH_SIZE 31 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++ ++#define my_perror(x) {fprintf(stderr, "%s: %d\n", __func__, __LINE__); perror(x); } ++ ++static int debug = 0; ++ ++static void print_buf(char *desc, const unsigned char *buf, int size) ++{ ++ int i; ++ fputs(desc, stdout); ++ for (i = 0; i < size; i++) { ++ printf("%.2x", (uint8_t) buf[i]); ++ } ++ fputs("\n", stdout); ++} ++ ++struct aes_gcm_vectors_st { ++ const uint8_t *key; ++ const uint8_t *auth; ++ int auth_size; ++ const uint8_t *plaintext; ++ int plaintext_size; ++ const uint8_t *iv; ++ const uint8_t *ciphertext; ++ const uint8_t *tag; ++}; ++ ++struct aes_gcm_vectors_st aes_gcm_vectors[] = { ++ { ++ .key = (uint8_t *) ++ "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", ++ .auth = NULL, ++ .auth_size = 0, ++ .plaintext = (uint8_t *) ++ "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", ++ .plaintext_size = 16, ++ .ciphertext = (uint8_t *) ++ "\x03\x88\xda\xce\x60\xb6\xa3\x92\xf3\x28\xc2\xb9\x71\xb2\xfe\x78", ++ .iv = (uint8_t *)"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", ++ .tag = (uint8_t *) ++ "\xab\x6e\x47\xd4\x2c\xec\x13\xbd\xf5\x3a\x67\xb2\x12\x57\xbd\xdf" ++ }, ++ { ++ .key = (uint8_t *) ++ "\xfe\xff\xe9\x92\x86\x65\x73\x1c\x6d\x6a\x8f\x94\x67\x30\x83\x08", ++ .auth = NULL, ++ .auth_size = 0, ++ .plaintext = (uint8_t *) ++ "\xd9\x31\x32\x25\xf8\x84\x06\xe5\xa5\x59\x09\xc5\xaf\xf5\x26\x9a\x86\xa7\xa9\x53\x15\x34\xf7\xda\x2e\x4c\x30\x3d\x8a\x31\x8a\x72\x1c\x3c\x0c\x95\x95\x68\x09\x53\x2f\xcf\x0e\x24\x49\xa6\xb5\x25\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57\xba\x63\x7b\x39\x1a\xaf\xd2\x55", ++ .plaintext_size = 64, ++ .ciphertext = (uint8_t *) ++ "\x42\x83\x1e\xc2\x21\x77\x74\x24\x4b\x72\x21\xb7\x84\xd0\xd4\x9c\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0\x35\xc1\x7e\x23\x29\xac\xa1\x2e\x21\xd5\x14\xb2\x54\x66\x93\x1c\x7d\x8f\x6a\x5a\xac\x84\xaa\x05\x1b\xa3\x0b\x39\x6a\x0a\xac\x97\x3d\x58\xe0\x91\x47\x3f\x59\x85", ++ .iv = (uint8_t *)"\xca\xfe\xba\xbe\xfa\xce\xdb\xad\xde\xca\xf8\x88", ++ .tag = (uint8_t *)"\x4d\x5c\x2a\xf3\x27\xcd\x64\xa6\x2c\xf3\x5a\xbd\x2b\xa6\xfa\xb4" ++ }, ++ { ++ .key = (uint8_t *) ++ "\xfe\xff\xe9\x92\x86\x65\x73\x1c\x6d\x6a\x8f\x94\x67\x30\x83\x08", ++ .auth = (uint8_t *) ++ "\xfe\xed\xfa\xce\xde\xad\xbe\xef\xfe\xed\xfa\xce\xde\xad\xbe\xef\xab\xad\xda\xd2", ++ .auth_size = 20, ++ .plaintext = (uint8_t *) ++ "\xd9\x31\x32\x25\xf8\x84\x06\xe5\xa5\x59\x09\xc5\xaf\xf5\x26\x9a\x86\xa7\xa9\x53\x15\x34\xf7\xda\x2e\x4c\x30\x3d\x8a\x31\x8a\x72\x1c\x3c\x0c\x95\x95\x68\x09\x53\x2f\xcf\x0e\x24\x49\xa6\xb5\x25\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57\xba\x63\x7b\x39", ++ .plaintext_size = 60, ++ .ciphertext = (uint8_t *) ++ "\x42\x83\x1e\xc2\x21\x77\x74\x24\x4b\x72\x21\xb7\x84\xd0\xd4\x9c\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0\x35\xc1\x7e\x23\x29\xac\xa1\x2e\x21\xd5\x14\xb2\x54\x66\x93\x1c\x7d\x8f\x6a\x5a\xac\x84\xaa\x05\x1b\xa3\x0b\x39\x6a\x0a\xac\x97\x3d\x58\xe0\x91", ++ .iv = (uint8_t *)"\xca\xfe\xba\xbe\xfa\xce\xdb\xad\xde\xca\xf8\x88", ++ .tag = (uint8_t *) ++ "\x5b\xc9\x4f\xbc\x32\x21\xa5\xdb\x94\xfa\xe9\x5a\xe7\x12\x1a\x47" ++ } ++}; ++ ++ ++/* Test against AES-GCM test vectors. ++ */ ++static int test_crypto(int cfd) ++{ ++ int i; ++ uint8_t tmp[128]; ++ ++ struct session_op sess; ++ struct crypt_auth_op cao; ++ ++ /* Get crypto session for AES128 */ ++ ++ if (debug) { ++ fprintf(stdout, "Tests on AES-GCM vectors: "); ++ fflush(stdout); ++ } ++ for (i = 0; ++ i < sizeof(aes_gcm_vectors) / sizeof(aes_gcm_vectors[0]); ++ i++) { ++ memset(&sess, 0, sizeof(sess)); ++ memset(tmp, 0, sizeof(tmp)); ++ ++ sess.cipher = CRYPTO_AES_GCM; ++ sess.keylen = 16; ++ sess.key = (void *) aes_gcm_vectors[i].key; ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ my_perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ memset(&cao, 0, sizeof(cao)); ++ ++ cao.ses = sess.ses; ++ cao.dst = tmp; ++ cao.iv = (void *) aes_gcm_vectors[i].iv; ++ cao.iv_len = 12; ++ cao.op = COP_ENCRYPT; ++ cao.flags = 0; ++ ++ if (aes_gcm_vectors[i].auth_size > 0) { ++ cao.auth_src = (void *) aes_gcm_vectors[i].auth; ++ cao.auth_len = aes_gcm_vectors[i].auth_size; ++ } ++ ++ if (aes_gcm_vectors[i].plaintext_size > 0) { ++ cao.src = (void *) aes_gcm_vectors[i].plaintext; ++ cao.len = aes_gcm_vectors[i].plaintext_size; ++ } ++ ++ if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { ++ my_perror("ioctl(CIOCAUTHCRYPT)"); ++ return 1; ++ } ++ ++ if (aes_gcm_vectors[i].plaintext_size > 0) ++ if (memcmp ++ (tmp, aes_gcm_vectors[i].ciphertext, ++ aes_gcm_vectors[i].plaintext_size) != 0) { ++ fprintf(stderr, ++ "AES-GCM test vector %d failed!\n", ++ i); ++ ++ print_buf("Cipher: ", tmp, aes_gcm_vectors[i].plaintext_size); ++ print_buf("Expected: ", aes_gcm_vectors[i].ciphertext, aes_gcm_vectors[i].plaintext_size); ++ return 1; ++ } ++ ++ if (memcmp ++ (&tmp[cao.len - cao.tag_len], aes_gcm_vectors[i].tag, ++ 16) != 0) { ++ fprintf(stderr, ++ "AES-GCM test vector %d failed (tag)!\n", ++ i); ++ ++ print_buf("Tag: ", &tmp[cao.len - cao.tag_len], cao.tag_len); ++ print_buf("Expected tag: ", ++ aes_gcm_vectors[i].tag, 16); ++ return 1; ++ } ++ ++ } ++ ++ if (debug) { ++ fprintf(stdout, "ok\n"); ++ fprintf(stdout, "\n"); ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ my_perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/* Checks if encryption and subsequent decryption ++ * produces the same data. ++ */ ++static int test_encrypt_decrypt(int cfd) ++{ ++ uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; ++ uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; ++ uint8_t iv[BLOCK_SIZE]; ++ uint8_t key[KEY_SIZE]; ++ uint8_t auth[AUTH_SIZE]; ++ int enc_len; ++ ++ struct session_op sess; ++ struct crypt_auth_op cao; ++ struct session_info_op siop; ++ ++ if (debug) { ++ fprintf(stdout, "Tests on AES-GCM encryption/decryption: "); ++ fflush(stdout); ++ } ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cao, 0, sizeof(cao)); ++ ++ memset(key, 0x33, sizeof(key)); ++ memset(iv, 0x03, sizeof(iv)); ++ memset(auth, 0xf1, sizeof(auth)); ++ ++ /* Get crypto session for AES128 */ ++ sess.cipher = CRYPTO_AES_GCM; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ my_perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ my_perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++// printf("requested cipher CRYPTO_AES_CBC/HMAC-SHA1, got %s with driver %s\n", ++// siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ ++ plaintext = (uint8_t *)buf_align(plaintext_raw, siop.alignmask); ++ ciphertext = (uint8_t *)buf_align(ciphertext_raw, siop.alignmask); ++ ++ memset(plaintext, 0x15, DATA_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cao.ses = sess.ses; ++ cao.auth_src = auth; ++ cao.auth_len = sizeof(auth); ++ cao.len = DATA_SIZE; ++ cao.src = plaintext; ++ cao.dst = ciphertext; ++ cao.iv = iv; ++ cao.iv_len = 12; ++ cao.op = COP_ENCRYPT; ++ cao.flags = 0; ++ ++ if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { ++ my_perror("ioctl(CIOCAUTHCRYPT)"); ++ return 1; ++ } ++ ++ enc_len = cao.len; ++ //printf("Original plaintext size: %d, ciphertext: %d\n", DATA_SIZE, enc_len); ++ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ my_perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ /* Get crypto session for AES128 */ ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_AES_GCM; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ my_perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ /* Decrypt data.encrypted to data.decrypted */ ++ cao.ses = sess.ses; ++ cao.auth_src = auth; ++ cao.auth_len = sizeof(auth); ++ cao.len = enc_len; ++ cao.src = ciphertext; ++ cao.dst = ciphertext; ++ cao.iv = iv; ++ cao.iv_len = 12; ++ cao.op = COP_DECRYPT; ++ cao.flags = 0; ++ ++ if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { ++ my_perror("ioctl(CIOCAUTHCRYPT)"); ++ return 1; ++ } ++ ++ if (cao.len != DATA_SIZE) { ++ fprintf(stderr, "decrypted data size incorrect!\n"); ++ return 1; ++ } ++ ++ /* Verify the result */ ++ if (memcmp(plaintext, ciphertext, DATA_SIZE) != 0) { ++ int i; ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ printf("plaintext:"); ++ for (i = 0; i < DATA_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", plaintext[i]); ++ } ++ printf("ciphertext:"); ++ for (i = 0; i < DATA_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", ciphertext[i]); ++ } ++ printf("\n"); ++ return 1; ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ my_perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ if (debug) { ++ fprintf(stdout, "ok\n"); ++ fprintf(stdout, "\n"); ++ } ++ ++ return 0; ++} ++ ++static int test_encrypt_decrypt_error(int cfd, int err) ++{ ++ uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; ++ uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; ++ uint8_t iv[BLOCK_SIZE]; ++ uint8_t key[KEY_SIZE]; ++ uint8_t auth[AUTH_SIZE]; ++ int enc_len; ++ ++ struct session_op sess; ++ struct crypt_op co; ++ struct crypt_auth_op cao; ++ struct session_info_op siop; ++ ++ if (debug) { ++ fprintf(stdout, "Tests on AES-GCM tag verification: "); ++ fflush(stdout); ++ } ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cao, 0, sizeof(cao)); ++ memset(&co, 0, sizeof(co)); ++ ++ memset(key, 0x33, sizeof(key)); ++ memset(iv, 0x03, sizeof(iv)); ++ memset(auth, 0xf1, sizeof(auth)); ++ ++ /* Get crypto session for AES128 */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ ++ sess.mac = CRYPTO_SHA1_HMAC; ++ sess.mackeylen = 16; ++ sess.mackey = ++ (uint8_t *) ++ "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"; ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ my_perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ my_perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++// printf("requested cipher CRYPTO_AES_CBC/HMAC-SHA1, got %s with driver %s\n", ++// siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ ++ plaintext = (uint8_t *)buf_align(plaintext_raw, siop.alignmask); ++ ciphertext = (uint8_t *)buf_align(ciphertext_raw, siop.alignmask); ++ ++ memset(plaintext, 0x15, DATA_SIZE); ++ memcpy(ciphertext, plaintext, DATA_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cao.ses = sess.ses; ++ cao.auth_src = auth; ++ cao.auth_len = sizeof(auth); ++ cao.len = DATA_SIZE; ++ cao.src = ciphertext; ++ cao.dst = ciphertext; ++ cao.iv = iv; ++ cao.op = COP_ENCRYPT; ++ cao.flags = COP_FLAG_AEAD_TLS_TYPE; ++ ++ if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { ++ my_perror("ioctl(CIOCAUTHCRYPT)"); ++ return 1; ++ } ++ ++ enc_len = cao.len; ++ //printf("Original plaintext size: %d, ciphertext: %d\n", DATA_SIZE, enc_len); ++ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ my_perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ /* Get crypto session for AES128 */ ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ sess.mac = CRYPTO_SHA1_HMAC; ++ sess.mackeylen = 16; ++ sess.mackey = ++ (uint8_t *) ++ "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"; ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ my_perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ if (err == 0) ++ auth[2]++; ++ else ++ ciphertext[4]++; ++ ++ /* Decrypt data.encrypted to data.decrypted */ ++ cao.ses = sess.ses; ++ cao.auth_src = auth; ++ cao.auth_len = sizeof(auth); ++ cao.len = enc_len; ++ cao.src = ciphertext; ++ cao.dst = ciphertext; ++ cao.iv = iv; ++ cao.op = COP_DECRYPT; ++ cao.flags = COP_FLAG_AEAD_TLS_TYPE; ++ if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ my_perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ if (debug) { ++ fprintf(stdout, "ok\n"); ++ fprintf(stdout, "\n"); ++ } ++ return 0; ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ my_perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ ++ fprintf(stderr, "Modification to ciphertext was not detected\n"); ++ return 1; ++} ++ ++int main(int argc, char** argv) ++{ ++ int fd = -1, cfd = -1; ++ ++ if (argc > 1) debug = 1; ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ my_perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Clone file descriptor */ ++ if (ioctl(fd, CRIOGET, &cfd)) { ++ my_perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ my_perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ /* Run the test itself */ ++ ++ if (test_crypto(cfd)) ++ return 1; ++ ++ if (test_encrypt_decrypt(cfd)) ++ return 1; ++ ++ if (test_encrypt_decrypt_error(cfd, 0)) ++ return 1; ++ ++ if (test_encrypt_decrypt_error(cfd, 1)) ++ return 1; ++ ++ /* Close cloned descriptor */ ++ if (close(cfd)) { ++ my_perror("close(cfd)"); ++ return 1; ++ } ++ ++ /* Close the original descriptor */ ++ if (close(fd)) { ++ my_perror("close(fd)"); ++ return 1; ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/cipher.c b/drivers/sstar/crypto/cryptodev/tests/cipher.c +new file mode 100755 +index 000000000000..fab3de6bdbd2 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/cipher.c +@@ -0,0 +1,327 @@ ++/* ++ * Demo on how to use /dev/crypto device for ciphering. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "testhelper.h" ++ ++static int debug = 0; ++ ++#define DATA_SIZE 8*1024 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++ ++static int ++test_crypto(int cfd) ++{ ++ uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; ++ uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; ++ uint8_t iv[BLOCK_SIZE]; ++ uint8_t key[KEY_SIZE]; ++ ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ struct crypt_op cryp; ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ memset(key, 0x33, sizeof(key)); ++ memset(iv, 0x03, sizeof(iv)); ++ ++ /* Get crypto session for AES128 */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ if (debug) ++ printf("requested cipher CRYPTO_AES_CBC, got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ ++ plaintext = buf_align(plaintext_raw, siop.alignmask); ++ ciphertext = buf_align(ciphertext_raw, siop.alignmask); ++#else ++ plaintext = plaintext_raw; ++ ciphertext = ciphertext_raw; ++#endif ++ memset(plaintext, 0x15, DATA_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = DATA_SIZE; ++ cryp.src = plaintext; ++ cryp.dst = ciphertext; ++ cryp.iv = iv; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ if (debug) ++ printf("requested cipher CRYPTO_AES_CBC, got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++#endif ++ ++ /* Decrypt data.encrypted to data.decrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = DATA_SIZE; ++ cryp.src = ciphertext; ++ cryp.dst = ciphertext; ++ cryp.iv = iv; ++ cryp.op = COP_DECRYPT; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ /* Verify the result */ ++ if (memcmp(plaintext, ciphertext, DATA_SIZE) != 0) { ++ int i; ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ printf("plaintext:"); ++ for (i = 0; i < DATA_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", plaintext[i]); ++ } ++ printf("ciphertext:"); ++ for (i = 0; i < DATA_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", ciphertext[i]); ++ } ++ printf("\n"); ++ return 1; ++ } else if (debug) ++ printf("Test passed\n"); ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static int test_aes(int cfd) ++{ ++ uint8_t plaintext1_raw[BLOCK_SIZE + 63], *plaintext1; ++ uint8_t ciphertext1[BLOCK_SIZE] = { 0xdf, 0x55, 0x6a, 0x33, 0x43, 0x8d, 0xb8, 0x7b, 0xc4, 0x1b, 0x17, 0x52, 0xc5, 0x5e, 0x5e, 0x49 }; ++ uint8_t iv1[BLOCK_SIZE]; ++ uint8_t key1[KEY_SIZE] = { 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ uint8_t plaintext2_data[BLOCK_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00 }; ++ uint8_t plaintext2_raw[BLOCK_SIZE + 63], *plaintext2; ++ uint8_t ciphertext2[BLOCK_SIZE] = { 0xb7, 0x97, 0x2b, 0x39, 0x41, 0xc4, 0x4b, 0x90, 0xaf, 0xa7, 0xb2, 0x64, 0xbf, 0xba, 0x73, 0x87 }; ++ uint8_t iv2[BLOCK_SIZE]; ++ uint8_t key2[KEY_SIZE]; ++ ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ struct crypt_op cryp; ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Get crypto session for AES128 */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key1; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ plaintext1 = buf_align(plaintext1_raw, siop.alignmask); ++#else ++ plaintext1 = plaintext1_raw; ++#endif ++ memset(plaintext1, 0x0, BLOCK_SIZE); ++ memset(iv1, 0x0, sizeof(iv1)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = BLOCK_SIZE; ++ cryp.src = plaintext1; ++ cryp.dst = plaintext1; ++ cryp.iv = iv1; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ /* Verify the result */ ++ if (memcmp(plaintext1, ciphertext1, BLOCK_SIZE) != 0) { ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ return 1; ++ } ++ ++ /* Test 2 */ ++ ++ memset(key2, 0x0, sizeof(key2)); ++ memset(iv2, 0x0, sizeof(iv2)); ++ ++ /* Get crypto session for AES128 */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key2; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ if (debug) ++ printf("requested cipher CRYPTO_AES_CBC, got %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); ++ ++ plaintext2 = buf_align(plaintext2_raw, siop.alignmask); ++#else ++ plaintext2 = plaintext2_raw; ++#endif ++ memcpy(plaintext2, plaintext2_data, BLOCK_SIZE); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess.ses; ++ cryp.len = BLOCK_SIZE; ++ cryp.src = plaintext2; ++ cryp.dst = plaintext2; ++ cryp.iv = iv2; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ /* Verify the result */ ++ if (memcmp(plaintext2, ciphertext2, BLOCK_SIZE) != 0) { ++ int i; ++ fprintf(stderr, ++ "FAIL: Decrypted data are different from the input data.\n"); ++ printf("plaintext:"); ++ for (i = 0; i < BLOCK_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", plaintext2[i]); ++ } ++ printf("ciphertext:"); ++ for (i = 0; i < BLOCK_SIZE; i++) { ++ if ((i % 30) == 0) ++ printf("\n"); ++ printf("%02x ", ciphertext2[i]); ++ } ++ printf("\n"); ++ return 1; ++ } ++ ++ if (debug) printf("AES Test passed\n"); ++ ++ /* Finish crypto session */ ++ if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++int ++main(int argc, char** argv) ++{ ++ int fd = -1, cfd = -1; ++ ++ if (argc > 1) debug = 1; ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Clone file descriptor */ ++ if (ioctl(fd, CRIOGET, &cfd)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ /* Run the test itself */ ++ if (test_aes(cfd)) ++ return 1; ++ ++ if (test_crypto(cfd)) ++ return 1; ++ ++ /* Close cloned descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ /* Close the original descriptor */ ++ if (close(fd)) { ++ perror("close(fd)"); ++ return 1; ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/tests/cipher_comp.c b/drivers/sstar/crypto/cryptodev/tests/cipher_comp.c +new file mode 100755 +index 000000000000..dbf9977852bb +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/cipher_comp.c +@@ -0,0 +1,159 @@ ++/* ++ * Compare encryption results with ones from openssl. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "openssl_wrapper.h" ++ ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++#define MAX_DATALEN (64 * 1024) ++ ++ ++static int ++test_crypto(int cfd, struct session_op *sess, int datalen) ++{ ++ uint8_t *data, *encrypted; ++ uint8_t *encrypted_comp; ++ ++ uint8_t iv_in[BLOCK_SIZE]; ++ uint8_t iv[BLOCK_SIZE]; ++ uint8_t iv_comp[BLOCK_SIZE]; ++ ++ struct crypt_op cryp; ++ ++ int ret = 0; ++ ++ data = malloc(datalen); ++ encrypted = malloc(datalen); ++ encrypted_comp = malloc(datalen); ++ memset(data, datalen & 0xff, datalen); ++ memset(encrypted, 0x27, datalen); ++ memset(encrypted_comp, 0x41, datalen); ++ ++ memset(iv_in, 0x23, sizeof(iv_in)); ++ memcpy(iv, iv_in, sizeof(iv)); ++ memcpy(iv_comp, iv_in, sizeof(iv_comp)); ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess->ses; ++ cryp.len = datalen; ++ cryp.src = data; ++ cryp.dst = encrypted; ++ cryp.iv = iv; ++ cryp.op = COP_ENCRYPT; ++ cryp.flags = COP_FLAG_WRITE_IV; ++ if ((ret = ioctl(cfd, CIOCCRYPT, &cryp))) { ++ perror("ioctl(CIOCCRYPT)"); ++ goto out; ++ } ++ ++ cryp.dst = encrypted_comp; ++ cryp.iv = iv_comp; ++ ++ if ((ret = openssl_cioccrypt(sess, &cryp))) { ++ fprintf(stderr, "openssl_cioccrypt() failed!\n"); ++ goto out; ++ } ++ ++ if ((ret = memcmp(encrypted, encrypted_comp, cryp.len))) { ++ printf("fail for datalen %d, cipher texts do not match!\n", datalen); ++ } ++ if ((ret = memcmp(iv, iv_comp, BLOCK_SIZE))) { ++ printf("fail for datalen %d, IVs do not match!\n", datalen); ++ } ++out: ++ free(data); ++ free(encrypted); ++ free(encrypted_comp); ++ return ret; ++} ++ ++#define max(a, b) ((a) > (b) ? (a) : (b)) ++#define min(a, b) ((a) < (b) ? (a) : (b)) ++ ++int ++main(int argc, char **argv) ++{ ++ int fd; ++ struct session_op sess; ++ uint8_t key[KEY_SIZE]; ++ int datalen = BLOCK_SIZE; ++ int datalen_end = MAX_DATALEN; ++ int i; ++ ++ if (argc > 1) { ++ datalen = min(max(atoi(argv[1]), BLOCK_SIZE), MAX_DATALEN); ++ datalen_end = datalen; ++ } ++ if (argc > 2) { ++ datalen_end = min(atoi(argv[2]), MAX_DATALEN); ++ if (datalen_end < datalen) ++ datalen_end = datalen; ++ } ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ for (i = 0; i < KEY_SIZE; i++) ++ key[i] = i & 0xff; ++ memset(&sess, 0, sizeof(sess)); ++ ++ /* encryption test */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ if (ioctl(fd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ { ++ struct session_info_op siop = { ++ .ses = sess.ses, ++ }; ++ ++ if (ioctl(fd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ } else { ++ printf("requested cipher CRYPTO_AES_CBC and mac CRYPTO_SHA1_HMAC," ++ " got cipher %s with driver %s and hash %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name, ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ } ++ } ++#endif ++ ++ for (; datalen <= datalen_end; datalen += BLOCK_SIZE) { ++ if (test_crypto(fd, &sess, datalen)) { ++ printf("test_crypto() failed for datalen of %d\n", datalen); ++ return 1; ++ } ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(fd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++ ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/fullspeed.c b/drivers/sstar/crypto/cryptodev/tests/fullspeed.c +new file mode 100755 +index 000000000000..4e97965f9f4c +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/fullspeed.c +@@ -0,0 +1,185 @@ ++/* cryptodev_test - simple benchmark tool for cryptodev ++ * ++ * Copyright (C) 2010 by Phil Sutter ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static int si = 1; /* SI by default */ ++ ++static double udifftimeval(struct timeval start, struct timeval end) ++{ ++ return (double)(end.tv_usec - start.tv_usec) + ++ (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; ++} ++ ++static int must_finish = 0; ++ ++static void alarm_handler(int signo) ++{ ++ must_finish = 1; ++} ++ ++static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; ++static char *si_units[] = { "", "K", "M", "G", "T", 0}; ++ ++static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) ++{ ++ int unit = 0; ++ ++ *data = bytes; ++ ++ if (si) { ++ while (*data > 1000 && si_units[unit + 1]) { ++ *data /= 1000; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", si_units[unit]); ++ } else { ++ while (*data > 1024 && units[unit + 1]) { ++ *data /= 1024; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", units[unit]); ++ } ++} ++ ++#define MAX(x,y) ((x)>(y)?(x):(y)) ++ ++int encrypt_data(int algo, void* keybuf, int key_size, int fdc, int chunksize) ++{ ++ struct crypt_op cop; ++ uint8_t *buffer, iv[32]; ++ static int val = 23; ++ struct timeval start, end; ++ double total = 0; ++ double secs, ddata, dspeed; ++ char metric[16]; ++ struct session_op sess; ++ ++ if (posix_memalign((void **)&buffer, 16, chunksize)) { ++ printf("posix_memalign() failed! (mask %x, size: %d)\n", 16, chunksize); ++ return 1; ++ } ++ ++ memset(iv, 0x23, 32); ++ ++ printf("\tEncrypting in chunks of %d bytes: ", chunksize); ++ fflush(stdout); ++ ++ memset(buffer, val++, chunksize); ++ ++ must_finish = 0; ++ alarm(5); ++ ++ gettimeofday(&start, NULL); ++ do { ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = algo; ++ sess.keylen = key_size; ++ sess.key = keybuf; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++ memset(&cop, 0, sizeof(cop)); ++ cop.ses = sess.ses; ++ cop.len = chunksize; ++ cop.iv = (unsigned char *)iv; ++ cop.op = COP_ENCRYPT; ++ cop.src = (unsigned char *)buffer; ++ cop.dst = buffer; ++ ++ if (ioctl(fdc, CIOCCRYPT, &cop)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ ioctl(fdc, CIOCFSESSION, &sess.ses); ++ ++ total+=chunksize; ++ } while(must_finish==0); ++ gettimeofday(&end, NULL); ++ ++ secs = udifftimeval(start, end)/ 1000000.0; ++ ++ value2human(si, total, secs, &ddata, &dspeed, metric); ++ printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); ++ printf ("%.2f %s/sec\n", dspeed, metric); ++ ++ free(buffer); ++ return 0; ++} ++ ++int main(int argc, char** argv) ++{ ++ int fd, i, fdc = -1; ++ char keybuf[32]; ++ ++ signal(SIGALRM, alarm_handler); ++ ++ if (argc > 1) { ++ if (strcmp(argv[1], "--help") == 0 || strcmp(argv[1], "-h") == 0) { ++ printf("Usage: speed [--kib]\n"); ++ exit(0); ++ } ++ if (strcmp(argv[1], "--kib") == 0) { ++ si = 0; ++ } ++ } ++ ++ if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { ++ perror("open()"); ++ return 1; ++ } ++ if (ioctl(fd, CRIOGET, &fdc)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ fprintf(stderr, "Testing NULL cipher: \n"); ++ ++ for (i = 512; i <= (64 * 1024); i *= 2) { ++ if (encrypt_data(CRYPTO_NULL, keybuf, 0, fdc, i)) ++ break; ++ } ++ ++ fprintf(stderr, "\nTesting AES-128-CBC cipher: \n"); ++ memset(keybuf, 0x42, 16); ++ ++ for (i = 512; i <= (64 * 1024); i *= 2) { ++ if (encrypt_data(CRYPTO_AES_CBC, keybuf, 16, fdc, i)) ++ break; ++ } ++ ++ close(fdc); ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/hash_comp.c b/drivers/sstar/crypto/cryptodev/tests/hash_comp.c +new file mode 100755 +index 000000000000..73f85edef7a1 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/hash_comp.c +@@ -0,0 +1,147 @@ ++/* ++ * Compare digest results with ones from openssl. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "openssl_wrapper.h" ++ ++#define BLOCK_SIZE 16 ++#define MAX_DATALEN (64 * 1024) ++ ++static void printhex(unsigned char *buf, int buflen) ++{ ++ while (buflen-- > 0) { ++ printf("\\x%.2x", *(buf++)); ++ } ++ printf("\n"); ++} ++ ++static int ++test_crypto(int cfd, struct session_op *sess, int datalen) ++{ ++ uint8_t *data; ++ uint8_t mac[AALG_MAX_RESULT_LEN]; ++ uint8_t mac_comp[AALG_MAX_RESULT_LEN]; ++ ++ struct crypt_op cryp; ++ ++ int ret = 0; ++ ++ data = malloc(datalen); ++ memset(data, datalen & 0xff, datalen); ++ ++ memset(mac, 0, sizeof(mac)); ++ memset(mac_comp, 0, sizeof(mac_comp)); ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess->ses; ++ cryp.len = datalen; ++ cryp.src = data; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ if ((ret = ioctl(cfd, CIOCCRYPT, &cryp))) { ++ perror("ioctl(CIOCCRYPT)"); ++ goto out; ++ } ++ ++ cryp.mac = mac_comp; ++ ++ if ((ret = openssl_cioccrypt(sess, &cryp))) { ++ fprintf(stderr, "openssl_cioccrypt() failed!\n"); ++ goto out; ++ } ++ ++ if (memcmp(mac, mac_comp, AALG_MAX_RESULT_LEN)) { ++ printf("fail for datalen %d, MACs do not match!\n", datalen); ++ ret = 1; ++ printf("wrong mac: "); ++ printhex(mac, 20); ++ printf("right mac: "); ++ printhex(mac_comp, 20); ++ } ++ ++out: ++ free(data); ++ return ret; ++} ++ ++#define max(a, b) ((a) > (b) ? (a) : (b)) ++#define min(a, b) ((a) < (b) ? (a) : (b)) ++ ++int ++main(int argc, char **argv) ++{ ++ int fd; ++ struct session_op sess; ++ int datalen = BLOCK_SIZE; ++ int datalen_end = MAX_DATALEN; ++ ++ if (argc > 1) { ++ datalen = min(max(atoi(argv[1]), BLOCK_SIZE), MAX_DATALEN); ++ datalen_end = datalen; ++ } ++ if (argc > 2) { ++ datalen_end = min(atoi(argv[2]), MAX_DATALEN); ++ if (datalen_end < datalen) ++ datalen_end = datalen; ++ } ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ memset(&sess, 0, sizeof(sess)); ++ ++ /* Hash test */ ++ sess.mac = CRYPTO_SHA1; ++ if (ioctl(fd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ { ++ struct session_info_op siop = { ++ .ses = sess.ses, ++ }; ++ ++ if (ioctl(fd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ } else { ++ printf("requested mac CRYPTO_SHA1, got hash %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ } ++ } ++#endif ++ ++ for (; datalen <= datalen_end; datalen += BLOCK_SIZE) { ++ if (test_crypto(fd, &sess, datalen)) { ++ printf("test_crypto() failed for datalen of %d\n", datalen); ++ return 1; ++ } ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(fd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++ ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/hashcrypt_speed.c b/drivers/sstar/crypto/cryptodev/tests/hashcrypt_speed.c +new file mode 100755 +index 000000000000..2b49f2b64338 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/hashcrypt_speed.c +@@ -0,0 +1,207 @@ ++/* hashcrypt_speed - simple SHA+AES benchmark tool for cryptodev ++ * ++ * Copyright (C) 2011 by Phil Sutter ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAX(x,y) ((x)>(y)?(x):(y)) ++ ++static double udifftimeval(struct timeval start, struct timeval end) ++{ ++ return (double)(end.tv_usec - start.tv_usec) + ++ (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; ++} ++ ++static int must_finish = 0; ++ ++static void alarm_handler(int signo) ++{ ++ must_finish = 1; ++} ++ ++static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; ++static char *si_units[] = { "", "K", "M", "G", "T", 0}; ++ ++static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) ++{ ++ int unit = 0; ++ ++ *data = bytes; ++ ++ if (si) { ++ while (*data > 1000 && si_units[unit + 1]) { ++ *data /= 1000; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", si_units[unit]); ++ } else { ++ while (*data > 1024 && units[unit + 1]) { ++ *data /= 1024; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", units[unit]); ++ } ++} ++ ++ ++int hash_data(struct session_op *sess, int fdc, int chunksize, int align) ++{ ++ struct crypt_op cop; ++ char *buffer; ++ static int val = 23; ++ struct timeval start, end; ++ double total = 0; ++ double secs, ddata, dspeed; ++ char metric[16]; ++ uint8_t mac[AALG_MAX_RESULT_LEN]; ++ ++ if (align) { ++ if (posix_memalign((void **)&buffer, align, chunksize)) { ++ printf("posix_memalign() failed, align: %d, size: %d!\n", align, chunksize); ++ return 1; ++ } ++ } else { ++ if (!(buffer = malloc(chunksize))) { ++ perror("malloc()"); ++ return 1; ++ } ++ } ++ ++ printf("\tEncrypting in chunks of %d bytes: ", chunksize); ++ fflush(stdout); ++ ++ memset(buffer, val++, chunksize); ++ ++ must_finish = 0; ++ alarm(5); ++ ++ gettimeofday(&start, NULL); ++ do { ++ memset(&cop, 0, sizeof(cop)); ++ cop.ses = sess->ses; ++ cop.len = chunksize; ++ cop.op = COP_ENCRYPT; ++ cop.src = cop.dst = (unsigned char *)buffer; ++ cop.mac = mac; ++ ++ if (ioctl(fdc, CIOCCRYPT, &cop)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ total+=chunksize; ++ } while(must_finish==0); ++ gettimeofday(&end, NULL); ++ ++ secs = udifftimeval(start, end)/ 1000000.0; ++ ++ value2human(1, total, secs, &ddata, &dspeed, metric); ++ printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); ++ printf ("%.2f %s/sec\n", dspeed, metric); ++ ++ free(buffer); ++ return 0; ++} ++ ++int main(void) ++{ ++ int fd, i, fdc = -1, align = 0; ++ struct session_op sess; ++ char keybuf[32]; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ signal(SIGALRM, alarm_handler); ++ ++ if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { ++ perror("open()"); ++ return 1; ++ } ++ if (ioctl(fd, CRIOGET, &fdc)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ fprintf(stderr, "Testing AES128 with SHA1 Hash: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = 16; ++ memset(keybuf, 0x42, 32); ++ sess.key = (unsigned char *)keybuf; ++ sess.mac = CRYPTO_SHA1; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ printf("requested hash CRYPTO_SHA1, got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ align = MAX(sizeof(void*), siop.alignmask+1); ++#endif ++ ++ for (i = 256; i <= (64 * 1024); i *= 4) { ++ if (hash_data(&sess, fdc, i, align)) ++ break; ++ } ++ ++ fprintf(stderr, "\nTesting AES256 with SHA256 Hash: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = 32; ++ sess.key = (unsigned char *)keybuf; ++ sess.mac = CRYPTO_SHA2_256; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ printf("requested hash CRYPTO_SHA2_256, got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ align = MAX(sizeof(void*), siop.alignmask+1); ++#endif ++ ++ for (i = 256; i <= (64 * 1024); i *= 4) { ++ if (hash_data(&sess, fdc, i, align)) ++ break; ++ } ++ ++ close(fdc); ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/hmac.c b/drivers/sstar/crypto/cryptodev/tests/hmac.c +new file mode 100755 +index 000000000000..8d6492e1d769 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/hmac.c +@@ -0,0 +1,336 @@ ++/* ++ * Demo on how to use /dev/crypto device for HMAC. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static int debug = 0; ++ ++#define DATA_SIZE 4096 ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++#define SHA1_HASH_LEN 20 ++ ++static int ++test_crypto(int cfd) ++{ ++ struct { ++ uint8_t in[DATA_SIZE], ++ encrypted[DATA_SIZE], ++ decrypted[DATA_SIZE], ++ iv[BLOCK_SIZE], ++ key[KEY_SIZE]; ++ } data; ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ struct crypt_op cryp; ++ uint8_t mac[AALG_MAX_RESULT_LEN]; ++ uint8_t oldmac[AALG_MAX_RESULT_LEN]; ++ uint8_t md5_hmac_out[] = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7\x38"; ++ uint8_t sha1_out[] = "\x8f\x82\x03\x94\xf9\x53\x35\x18\x20\x45\xda\x24\xf3\x4d\xe5\x2b\xf8\xbc\x34\x32"; ++ int i; ++ ++ memset(&sess, 0, sizeof(sess)); ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Use the garbage that is on the stack :-) */ ++ /* memset(&data, 0, sizeof(data)); */ ++ ++ /* SHA1 plain test */ ++ memset(mac, 0, sizeof(mac)); ++ ++ sess.cipher = 0; ++ sess.mac = CRYPTO_SHA1; ++ if (ioctl(cfd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(cfd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ if (debug) printf("requested mac CRYPTO_SHA1, got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++#endif ++ ++ cryp.ses = sess.ses; ++ cryp.len = sizeof("what do ya want for nothing?")-1; ++ cryp.src = (uint8_t *)"what do ya want for nothing?"; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ if (ioctl(cfd, CIOCCRYPT, &cryp)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ ++ if (memcmp(mac, sha1_out, 20)!=0) { ++ printf("mac: "); ++ for (i=0;i 1) debug = 1; ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ /* Clone file descriptor */ ++ if (ioctl(fd, CRIOGET, &cfd)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ /* Set close-on-exec (not really neede here) */ ++ if (fcntl(cfd, F_SETFD, 1) == -1) { ++ perror("fcntl(F_SETFD)"); ++ return 1; ++ } ++ ++ /* Run the test itself */ ++ if (test_crypto(cfd)) ++ return 1; ++ ++ if (test_extras(cfd)) ++ return 1; ++ ++ /* Close cloned descriptor */ ++ if (close(cfd)) { ++ perror("close(cfd)"); ++ return 1; ++ } ++ ++ /* Close the original descriptor */ ++ if (close(fd)) { ++ perror("close(fd)"); ++ return 1; ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/hmac_comp.c b/drivers/sstar/crypto/cryptodev/tests/hmac_comp.c +new file mode 100755 +index 000000000000..a8709cbbc3fb +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/hmac_comp.c +@@ -0,0 +1,187 @@ ++/* ++ * Compare HMAC results with ones from openssl. ++ * ++ * Placed under public domain. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "openssl_wrapper.h" ++ ++#define BLOCK_SIZE 16 ++#define KEY_SIZE 16 ++#define MACKEY_SIZE 20 ++#define MAX_DATALEN (64 * 1024) ++ ++static void printhex(unsigned char *buf, int buflen) ++{ ++ while (buflen-- > 0) { ++ printf("\\x%.2x", *(buf++)); ++ } ++ printf("\n"); ++} ++ ++static int ++test_crypto(int cfd, struct session_op *sess, int datalen) ++{ ++ unsigned char *data, *encrypted; ++ unsigned char *encrypted_comp; ++ ++ unsigned char iv[BLOCK_SIZE]; ++ unsigned char mac[AALG_MAX_RESULT_LEN]; ++ ++ unsigned char iv_comp[BLOCK_SIZE]; ++ unsigned char mac_comp[AALG_MAX_RESULT_LEN]; ++ ++ struct crypt_op cryp; ++ ++ int ret = 0; ++ ++ data = malloc(datalen); ++ encrypted = malloc(datalen); ++ encrypted_comp = malloc(datalen); ++ memset(data, datalen & 0xff, datalen); ++ memset(encrypted, 0x27, datalen); ++ memset(encrypted_comp, 0x28, datalen); ++ ++ memset(iv, 0x23, sizeof(iv)); ++ memset(iv_comp, 0x23, sizeof(iv)); ++ memset(mac, 0, sizeof(mac)); ++ memset(mac_comp, 1, sizeof(mac_comp)); ++ ++ memset(&cryp, 0, sizeof(cryp)); ++ ++ /* Encrypt data.in to data.encrypted */ ++ cryp.ses = sess->ses; ++ cryp.len = datalen; ++ cryp.src = data; ++ cryp.dst = encrypted; ++ cryp.iv = iv; ++ cryp.mac = mac; ++ cryp.op = COP_ENCRYPT; ++ cryp.flags = COP_FLAG_WRITE_IV; ++ if ((ret = ioctl(cfd, CIOCCRYPT, &cryp))) { ++ perror("ioctl(CIOCCRYPT)"); ++ goto out; ++ } ++ ++ cryp.dst = encrypted_comp; ++ cryp.mac = mac_comp; ++ cryp.iv = iv_comp; ++ ++ if ((ret = openssl_cioccrypt(sess, &cryp))) { ++ fprintf(stderr, "openssl_cioccrypt() failed!\n"); ++ goto out; ++ } ++ ++ if ((ret = memcmp(encrypted, encrypted_comp, cryp.len))) { ++ printf("fail for datalen %d, cipher texts do not match!\n", datalen); ++ } ++ if ((ret = memcmp(iv, iv_comp, BLOCK_SIZE))) { ++ printf("fail for datalen %d, updated IVs do not match!\n", datalen); ++ } ++ if ((ret = memcmp(mac, mac_comp, AALG_MAX_RESULT_LEN))) { ++ printf("fail for datalen 0x%x, MACs do not match!\n", datalen); ++ printf("wrong mac: "); ++ printhex(mac, 20); ++ printf("right mac: "); ++ printhex(mac_comp, 20); ++ ++ } ++ ++out: ++ free(data); ++ free(encrypted); ++ free(encrypted_comp); ++ return ret; ++} ++ ++#define max(a, b) ((a) > (b) ? (a) : (b)) ++#define min(a, b) ((a) < (b) ? (a) : (b)) ++ ++int ++main(int argc, char **argv) ++{ ++ int fd; ++ struct session_op sess; ++ unsigned char key[KEY_SIZE], mackey[MACKEY_SIZE]; ++ int datalen = BLOCK_SIZE; ++ int datalen_end = MAX_DATALEN; ++ int i; ++ ++ if (argc > 1) { ++ datalen = min(max(atoi(argv[1]), BLOCK_SIZE), MAX_DATALEN); ++ datalen_end = datalen; ++ } ++ if (argc > 2) { ++ datalen_end = min(atoi(argv[2]), MAX_DATALEN); ++ if (datalen_end < datalen) ++ datalen_end = datalen; ++ } ++ ++ /* Open the crypto device */ ++ fd = open("/dev/crypto", O_RDWR, 0); ++ if (fd < 0) { ++ perror("open(/dev/crypto)"); ++ return 1; ++ } ++ ++ for (i = 0; i < KEY_SIZE; i++) ++ key[i] = i & 0xff; ++ for (i = 0; i < MACKEY_SIZE; i++) ++ mackey[i] = i & 0xff; ++ ++ memset(&sess, 0, sizeof(sess)); ++ ++ /* Hash and encryption in one step test */ ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.mac = CRYPTO_SHA1_HMAC; ++ sess.keylen = KEY_SIZE; ++ sess.key = key; ++ sess.mackeylen = MACKEY_SIZE; ++ sess.mackey = mackey; ++ if (ioctl(fd, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++ ++#ifdef CIOCGSESSINFO ++ { ++ struct session_info_op siop = { ++ .ses = sess.ses, ++ }; ++ ++ if (ioctl(fd, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ } else { ++ printf("requested cipher CRYPTO_AES_CBC and mac CRYPTO_SHA1_HMAC," ++ " got cipher %s with driver %s and hash %s with driver %s\n", ++ siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name, ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ } ++ } ++#endif ++ ++ for (; datalen <= datalen_end; datalen += BLOCK_SIZE) { ++ if (test_crypto(fd, &sess, datalen)) { ++ printf("test_crypto() failed for datalen of %d\n", datalen); ++ return 1; ++ } ++ } ++ ++ /* Finish crypto session */ ++ if (ioctl(fd, CIOCFSESSION, &sess.ses)) { ++ perror("ioctl(CIOCFSESSION)"); ++ } ++ ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/openssl_wrapper.c b/drivers/sstar/crypto/cryptodev/tests/openssl_wrapper.c +new file mode 100755 +index 000000000000..dea2496df658 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/openssl_wrapper.c +@@ -0,0 +1,300 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#define DEBUG ++ ++#ifdef DEBUG ++# define dbgp(...) { \ ++ fprintf(stderr, "%s:%d: ", __FILE__, __LINE__); \ ++ fprintf(stderr, __VA_ARGS__); \ ++ fprintf(stderr, "\n"); \ ++} ++#else ++# define dbgp(...) /* nothing */ ++#endif ++ ++enum ctx_type { ++ ctx_type_none = 0, ++ ctx_type_hmac, ++ ctx_type_md, ++}; ++ ++#if OPENSSL_VERSION_NUMBER >= 0x10100000L ++union openssl_ctx { ++ HMAC_CTX *hmac; ++ EVP_MD_CTX *md; ++}; ++#else ++union openssl_ctx { ++ HMAC_CTX hmac; ++ EVP_MD_CTX md; ++}; ++#endif ++ ++struct ctx_mapping { ++ __u32 ses; ++ enum ctx_type type; ++ union openssl_ctx ctx; ++}; ++ ++static struct ctx_mapping ctx_map[512]; ++ ++static struct ctx_mapping *find_mapping(__u32 ses) ++{ ++ int i; ++ ++ for (i = 0; i < 512; i++) { ++ if (ctx_map[i].ses == ses) ++ return &ctx_map[i]; ++ } ++ return NULL; ++} ++ ++static struct ctx_mapping *new_mapping(void) ++{ ++ return find_mapping(0); ++} ++ ++static void remove_mapping(__u32 ses) ++{ ++ struct ctx_mapping *mapping; ++ ++ if (!(mapping = find_mapping(ses))) { ++ printf("%s: failed to find mapping for session %d\n", __func__, ses); ++ return; ++ } ++ switch (mapping->type) { ++ case ctx_type_none: ++ break; ++#if OPENSSL_VERSION_NUMBER >= 0x10100000L ++ case ctx_type_hmac: ++ dbgp("%s: calling HMAC_CTX_free\n", __func__); ++ HMAC_CTX_free(mapping->ctx.hmac); ++ break; ++ case ctx_type_md: ++ dbgp("%s: calling EVP_MD_CTX_free\n", __func__); ++ EVP_MD_CTX_free(mapping->ctx.md); ++ break; ++#else ++ case ctx_type_hmac: ++ dbgp("%s: calling HMAC_CTX_cleanup\n", __func__); ++ HMAC_CTX_cleanup(&mapping->ctx.hmac); ++ break; ++ case ctx_type_md: ++ dbgp("%s: calling EVP_MD_CTX_cleanup\n", __func__); ++ EVP_MD_CTX_cleanup(&mapping->ctx.md); ++ break; ++#endif ++ } ++ memset(mapping, 0, sizeof(*mapping)); ++} ++ ++static union openssl_ctx *__ses_to_ctx(__u32 ses) ++{ ++ struct ctx_mapping *mapping; ++ ++ if (!(mapping = find_mapping(ses))) ++ return NULL; ++ return &mapping->ctx; ++} ++ ++static HMAC_CTX *ses_to_hmac(__u32 ses) { return (HMAC_CTX *)__ses_to_ctx(ses); } ++static EVP_MD_CTX *ses_to_md(__u32 ses) { return (EVP_MD_CTX *)__ses_to_ctx(ses); } ++ ++static const EVP_MD *sess_to_evp_md(struct session_op *sess) ++{ ++ switch (sess->mac) { ++#ifndef OPENSSL_NO_MD5 ++ case CRYPTO_MD5_HMAC: return EVP_md5(); ++#endif ++#ifndef OPENSSL_NO_SHA ++ case CRYPTO_SHA1_HMAC: ++ case CRYPTO_SHA1: ++ return EVP_sha1(); ++#endif ++#ifndef OPENSSL_NO_RIPEMD ++ case CRYPTO_RIPEMD160_HMAC: return EVP_ripemd160(); ++#endif ++#ifndef OPENSSL_NO_SHA256 ++ case CRYPTO_SHA2_256_HMAC: return EVP_sha256(); ++#endif ++#ifndef OPENSSL_NO_SHA512 ++ case CRYPTO_SHA2_384_HMAC: return EVP_sha384(); ++ case CRYPTO_SHA2_512_HMAC: return EVP_sha512(); ++#endif ++ default: ++ printf("%s: failed to get an EVP, things will be broken!\n", __func__); ++ return NULL; ++ } ++} ++ ++static int openssl_hmac(struct session_op *sess, struct crypt_op *cop) ++{ ++ HMAC_CTX *ctx = ses_to_hmac(sess->ses); ++ ++ if (!ctx) { ++ struct ctx_mapping *mapping = new_mapping(); ++ if (!mapping) { ++ printf("%s: failed to get new mapping\n", __func__); ++ return 1; ++ } ++ ++ mapping->ses = sess->ses; ++ mapping->type = ctx_type_hmac; ++#if OPENSSL_VERSION_NUMBER >= 0x10100000L ++ ctx = mapping->ctx.hmac; ++ ++ dbgp("calling HMAC_CTX_new"); ++ ctx = HMAC_CTX_new(); ++#else ++ ctx = &mapping->ctx.hmac; ++ ++ dbgp("calling HMAC_CTX_init"); ++ HMAC_CTX_init(ctx); ++#endif ++ dbgp("calling HMAC_Init_ex"); ++ if (!HMAC_Init_ex(ctx, sess->mackey, sess->mackeylen, ++ sess_to_evp_md(sess), NULL)) { ++ printf("%s: HMAC_Init_ex failed\n", __func__); ++ return 1; ++ } ++ } ++ ++ if (cop->len) { ++ dbgp("calling HMAC_Update"); ++ if (!HMAC_Update(ctx, cop->src, cop->len)) { ++ printf("%s: HMAC_Update failed\n", __func__); ++ return 1; ++ } ++ } ++ if (cop->flags & COP_FLAG_FINAL || ++ (cop->len && !(cop->flags & COP_FLAG_UPDATE))) { ++ dbgp("calling HMAC_Final"); ++ if (!HMAC_Final(ctx, cop->mac, 0)) { ++ printf("%s: HMAC_Final failed\n", __func__); ++ remove_mapping(sess->ses); ++ return 1; ++ } ++ remove_mapping(sess->ses); ++ } ++ return 0; ++} ++ ++static int openssl_md(struct session_op *sess, struct crypt_op *cop) ++{ ++ EVP_MD_CTX *ctx = ses_to_md(sess->ses); ++ ++ if (!ctx) { ++ struct ctx_mapping *mapping = new_mapping(); ++ if (!mapping) { ++ printf("%s: failed to get new mapping\n", __func__); ++ return 1; ++ } ++ ++ mapping->ses = sess->ses; ++ mapping->type = ctx_type_md; ++#if OPENSSL_VERSION_NUMBER >= 0x10100000L ++ ctx = mapping->ctx.md; ++ ++ dbgp("calling EVP_MD_CTX_new"); ++ ctx = EVP_MD_CTX_new(); ++#else ++ ctx = &mapping->ctx.md; ++ ++ dbgp("calling EVP_MD_CTX_init"); ++ EVP_MD_CTX_init(ctx); ++#endif ++ dbgp("calling EVP_DigestInit"); ++ EVP_DigestInit(ctx, sess_to_evp_md(sess)); ++ } ++ ++ if (cop->len) { ++ dbgp("calling EVP_DigestUpdate"); ++ EVP_DigestUpdate(ctx, cop->src, cop->len); ++ } ++ if (cop->flags & COP_FLAG_FINAL || ++ (cop->len && !(cop->flags & COP_FLAG_UPDATE))) { ++ dbgp("calling EVP_DigestFinal"); ++ EVP_DigestFinal(ctx, cop->mac, 0); ++ remove_mapping(sess->ses); ++ } ++ ++ return 0; ++} ++ ++static int openssl_aes(struct session_op *sess, struct crypt_op *cop) ++{ ++ AES_KEY key; ++ int i, enc; ++ unsigned char ivec[AES_BLOCK_SIZE]; ++ ++ if (cop->len % AES_BLOCK_SIZE) { ++ printf("%s: illegal length passed, " ++ "not a multiple of AES_BLOCK_SIZE\n", __func__); ++ return 1; ++ } ++ ++ switch (cop->op) { ++ case COP_ENCRYPT: ++ AES_set_encrypt_key(sess->key, sess->keylen * 8, &key); ++ enc = 1; ++ break; ++ case COP_DECRYPT: ++ AES_set_decrypt_key(sess->key, sess->keylen * 8, &key); ++ enc = 0; ++ break; ++ default: ++ printf("%s: unknown cop->op received!\n", __func__); ++ return 1; ++ } ++ ++ switch (sess->cipher) { ++ case CRYPTO_AES_CBC: ++ memcpy(ivec, cop->iv, AES_BLOCK_SIZE); ++ AES_cbc_encrypt(cop->src, cop->dst, cop->len, &key, ivec, enc); ++ if (cop->flags & COP_FLAG_WRITE_IV) ++ memcpy(cop->iv, ivec, AES_BLOCK_SIZE); ++ break; ++#if 0 ++ /* XXX: TODO: implement this stuff */ ++ case CRYPTO_AES_CTR: ++ AES_ctr128_encrypt(cop->src, cop->dst, &key, cop->iv, ++ case CRYPTO_AES_XTS: ++#endif ++ case CRYPTO_AES_ECB: ++ for (i = 0; i < cop->len; i += AES_BLOCK_SIZE) ++ AES_ecb_encrypt(cop->src + i, cop->dst + i, &key, enc); ++ break; ++ } ++ return 0; ++} ++ ++int openssl_cioccrypt(struct session_op *sess, struct crypt_op *cop) ++{ ++ if (sess->mac && sess->mackey && sess->mackeylen) ++ openssl_hmac(sess, cop); ++ else if (sess->mac) ++ openssl_md(sess, cop); ++ ++ switch (sess->cipher) { ++ case CRYPTO_AES_CBC: ++ case CRYPTO_AES_CTR: ++ case CRYPTO_AES_XTS: ++ case CRYPTO_AES_ECB: ++ openssl_aes(sess, cop); ++ break; ++ case 0: ++ /* no encryption wanted, everythings fine */ ++ break; ++ default: ++ printf("%s: unknown cipher passed!\n", __func__); ++ break; ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/openssl_wrapper.h b/drivers/sstar/crypto/cryptodev/tests/openssl_wrapper.h +new file mode 100755 +index 000000000000..5f1f5162b674 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/openssl_wrapper.h +@@ -0,0 +1,6 @@ ++#ifndef __OPENSSL_WRAPPER_H ++#define __OPENSSL_WRAPPER_H ++ ++int openssl_cioccrypt(struct session_op *, struct crypt_op *); ++ ++#endif /* __OPENSSL_WRAPPER_H */ +diff --git a/drivers/sstar/crypto/cryptodev/tests/sha_speed.c b/drivers/sstar/crypto/cryptodev/tests/sha_speed.c +new file mode 100755 +index 000000000000..1e672603126e +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/sha_speed.c +@@ -0,0 +1,198 @@ ++/* sha_speed - simple SHA benchmark tool for cryptodev ++ * ++ * Copyright (C) 2011 by Phil Sutter ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static double udifftimeval(struct timeval start, struct timeval end) ++{ ++ return (double)(end.tv_usec - start.tv_usec) + ++ (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; ++} ++ ++static int must_finish = 0; ++ ++static void alarm_handler(int signo) ++{ ++ must_finish = 1; ++} ++ ++static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; ++static char *si_units[] = { "", "K", "M", "G", "T", 0}; ++ ++static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) ++{ ++ int unit = 0; ++ ++ *data = bytes; ++ ++ if (si) { ++ while (*data > 1000 && si_units[unit + 1]) { ++ *data /= 1000; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", si_units[unit]); ++ } else { ++ while (*data > 1024 && units[unit + 1]) { ++ *data /= 1024; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", units[unit]); ++ } ++} ++ ++ ++int hash_data(struct session_op *sess, int fdc, int chunksize, int alignmask) ++{ ++ struct crypt_op cop; ++ char *buffer; ++ static int val = 23; ++ struct timeval start, end; ++ double total = 0; ++ double secs, ddata, dspeed; ++ char metric[16]; ++ uint8_t mac[AALG_MAX_RESULT_LEN]; ++ ++ if (alignmask) { ++ if (posix_memalign((void **)&buffer, alignmask + 1, chunksize)) { ++ printf("posix_memalign() failed!\n"); ++ return 1; ++ } ++ } else { ++ if (!(buffer = malloc(chunksize))) { ++ perror("malloc()"); ++ return 1; ++ } ++ } ++ ++ printf("\tEncrypting in chunks of %d bytes: ", chunksize); ++ fflush(stdout); ++ ++ memset(buffer, val++, chunksize); ++ ++ must_finish = 0; ++ alarm(5); ++ ++ gettimeofday(&start, NULL); ++ do { ++ memset(&cop, 0, sizeof(cop)); ++ cop.ses = sess->ses; ++ cop.len = chunksize; ++ cop.op = COP_ENCRYPT; ++ cop.src = (unsigned char *)buffer; ++ cop.mac = mac; ++ ++ if (ioctl(fdc, CIOCCRYPT, &cop)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ total+=chunksize; ++ } while(must_finish==0); ++ gettimeofday(&end, NULL); ++ ++ secs = udifftimeval(start, end)/ 1000000.0; ++ ++ value2human(1, total, secs, &ddata, &dspeed, metric); ++ printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); ++ printf ("%.2f %s/sec\n", dspeed, metric); ++ ++ free(buffer); ++ return 0; ++} ++ ++int main(void) ++{ ++ int fd, i, fdc = -1, alignmask = 0; ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ ++ signal(SIGALRM, alarm_handler); ++ ++ if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { ++ perror("open()"); ++ return 1; ++ } ++ if (ioctl(fd, CRIOGET, &fdc)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ fprintf(stderr, "Testing SHA1 Hash: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.mac = CRYPTO_SHA1; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ printf("requested hash CRYPTO_SHA1, got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ alignmask = siop.alignmask; ++#endif ++ ++ for (i = 256; i <= (64 * 1024); i *= 4) { ++ if (hash_data(&sess, fdc, i, alignmask)) ++ break; ++ } ++ ++ fprintf(stderr, "\nTesting SHA256 Hash: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.mac = CRYPTO_SHA2_256; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ printf("requested hash CRYPTO_SHA2_256, got %s with driver %s\n", ++ siop.hash_info.cra_name, siop.hash_info.cra_driver_name); ++ alignmask = siop.alignmask; ++#endif ++ ++ for (i = 256; i <= (64 * 1024); i *= 4) { ++ if (hash_data(&sess, fdc, i, alignmask)) ++ break; ++ } ++ ++ close(fdc); ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/speed.c b/drivers/sstar/crypto/cryptodev/tests/speed.c +new file mode 100755 +index 000000000000..951ae096c95f +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/speed.c +@@ -0,0 +1,213 @@ ++/* cryptodev_test - simple benchmark tool for cryptodev ++ * ++ * Copyright (C) 2010 by Phil Sutter ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static int si = 1; /* SI by default */ ++ ++static double udifftimeval(struct timeval start, struct timeval end) ++{ ++ return (double)(end.tv_usec - start.tv_usec) + ++ (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; ++} ++ ++static volatile int must_finish; ++ ++static void alarm_handler(int signo) ++{ ++ must_finish = 1; ++} ++ ++static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; ++static char *si_units[] = { "", "K", "M", "G", "T", 0}; ++ ++static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) ++{ ++ int unit = 0; ++ ++ *data = bytes; ++ ++ if (si) { ++ while (*data > 1000 && si_units[unit + 1]) { ++ *data /= 1000; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", si_units[unit]); ++ } else { ++ while (*data > 1024 && units[unit + 1]) { ++ *data /= 1024; ++ unit++; ++ } ++ *speed = *data / time; ++ sprintf(metric, "%sB", units[unit]); ++ } ++} ++ ++#define MAX(x,y) ((x)>(y)?(x):(y)) ++ ++int encrypt_data(struct session_op *sess, int fdc, int chunksize, int alignmask) ++{ ++ struct crypt_op cop; ++ char *buffer, iv[32]; ++ static int val = 23; ++ struct timeval start, end; ++ double total = 0; ++ double secs, ddata, dspeed; ++ char metric[16]; ++ ++ if (alignmask) { ++ if (posix_memalign((void **)&buffer, MAX(alignmask + 1, sizeof(void*)), chunksize)) { ++ printf("posix_memalign() failed! (mask %x, size: %d)\n", alignmask+1, chunksize); ++ return 1; ++ } ++ } else { ++ if (!(buffer = malloc(chunksize))) { ++ perror("malloc()"); ++ return 1; ++ } ++ } ++ ++ memset(iv, 0x23, 32); ++ ++ printf("\tEncrypting in chunks of %d bytes: ", chunksize); ++ fflush(stdout); ++ ++ memset(buffer, val++, chunksize); ++ ++ must_finish = 0; ++ alarm(5); ++ ++ gettimeofday(&start, NULL); ++ do { ++ memset(&cop, 0, sizeof(cop)); ++ cop.ses = sess->ses; ++ cop.len = chunksize; ++ cop.iv = (unsigned char *)iv; ++ cop.op = COP_ENCRYPT; ++ cop.src = cop.dst = (unsigned char *)buffer; ++ ++ if (ioctl(fdc, CIOCCRYPT, &cop)) { ++ perror("ioctl(CIOCCRYPT)"); ++ return 1; ++ } ++ total+=chunksize; ++ } while(must_finish==0); ++ gettimeofday(&end, NULL); ++ ++ secs = udifftimeval(start, end)/ 1000000.0; ++ ++ value2human(si, total, secs, &ddata, &dspeed, metric); ++ printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); ++ printf ("%.2f %s/sec\n", dspeed, metric); ++ ++ free(buffer); ++ return 0; ++} ++ ++int main(int argc, char** argv) ++{ ++ int fd, i, fdc = -1, alignmask = 0; ++ struct session_op sess; ++#ifdef CIOCGSESSINFO ++ struct session_info_op siop; ++#endif ++ char keybuf[32]; ++ ++ signal(SIGALRM, alarm_handler); ++ ++ if (argc > 1) { ++ if (strcmp(argv[1], "--help") == 0 || strcmp(argv[1], "-h") == 0) { ++ printf("Usage: speed [--kib]\n"); ++ exit(0); ++ } ++ if (strcmp(argv[1], "--kib") == 0) { ++ si = 0; ++ } ++ } ++ ++ if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { ++ perror("open()"); ++ return 1; ++ } ++ if (ioctl(fd, CRIOGET, &fdc)) { ++ perror("ioctl(CRIOGET)"); ++ return 1; ++ } ++ ++ fprintf(stderr, "Testing NULL cipher: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_NULL; ++ sess.keylen = 0; ++ sess.key = (unsigned char *)keybuf; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ alignmask = siop.alignmask; ++#endif ++ ++ for (i = 512; i <= (64 * 1024); i *= 2) { ++ if (encrypt_data(&sess, fdc, i, alignmask)) ++ break; ++ } ++ ++ fprintf(stderr, "\nTesting AES-128-CBC cipher: \n"); ++ memset(&sess, 0, sizeof(sess)); ++ sess.cipher = CRYPTO_AES_CBC; ++ sess.keylen = 16; ++ memset(keybuf, 0x42, 16); ++ sess.key = (unsigned char *)keybuf; ++ if (ioctl(fdc, CIOCGSESSION, &sess)) { ++ perror("ioctl(CIOCGSESSION)"); ++ return 1; ++ } ++#ifdef CIOCGSESSINFO ++ siop.ses = sess.ses; ++ if (ioctl(fdc, CIOCGSESSINFO, &siop)) { ++ perror("ioctl(CIOCGSESSINFO)"); ++ return 1; ++ } ++ alignmask = siop.alignmask; ++#endif ++ ++ for (i = 512; i <= (64 * 1024); i *= 2) { ++ if (encrypt_data(&sess, fdc, i, alignmask)) ++ break; ++ } ++ ++ close(fdc); ++ close(fd); ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/tests/testhelper.h b/drivers/sstar/crypto/cryptodev/tests/testhelper.h +new file mode 100755 +index 000000000000..800d10db2f08 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/tests/testhelper.h +@@ -0,0 +1,9 @@ ++/* ++ * Some helper stuff shared between the sample programs. ++ */ ++#ifndef __TESTHELPER_H ++#define __TESTHELPER_H ++ ++#define buf_align(buf, align) (void *)(((unsigned long)(buf) + (align)) & ~(align)) ++ ++#endif /* __TESTHELPER_H */ +diff --git a/drivers/sstar/crypto/cryptodev/util.c b/drivers/sstar/crypto/cryptodev/util.c +new file mode 100644 +index 000000000000..9eba4836ba6a +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/util.c +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (c) 2011 Maxim Levitsky ++ * ++ * This file is part of linux cryptodev. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++#include ++#include ++#include "util.h" ++ ++/* These were taken from Maxim Levitsky's patch to lkml. ++ */ ++struct scatterlist *sg_advance(struct scatterlist *sg, int consumed) ++{ ++ while (consumed >= sg->length) { ++ consumed -= sg->length; ++ ++ sg = sg_next(sg); ++ if (!sg) ++ break; ++ } ++ ++ WARN_ON(!sg && consumed); ++ ++ if (!sg) ++ return NULL; ++ ++ sg->offset += consumed; ++ sg->length -= consumed; ++ ++ if (sg->offset >= PAGE_SIZE) { ++ struct page *page = ++ nth_page(sg_page(sg), sg->offset / PAGE_SIZE); ++ sg_set_page(sg, page, sg->length, sg->offset % PAGE_SIZE); ++ } ++ ++ return sg; ++} ++ ++/** ++ * sg_copy - copies sg entries from sg_from to sg_to, such ++ * as sg_to covers first 'len' bytes from sg_from. ++ */ ++int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len) ++{ ++ while (len > sg_from->length) { ++ len -= sg_from->length; ++ ++ sg_set_page(sg_to, sg_page(sg_from), ++ sg_from->length, sg_from->offset); ++ ++ sg_to = sg_next(sg_to); ++ sg_from = sg_next(sg_from); ++ ++ if (len && (!sg_from || !sg_to)) ++ return -ENOMEM; ++ } ++ ++ if (len) ++ sg_set_page(sg_to, sg_page(sg_from), ++ len, sg_from->offset); ++ sg_mark_end(sg_to); ++ return 0; ++} ++ +diff --git a/drivers/sstar/crypto/cryptodev/util.h b/drivers/sstar/crypto/cryptodev/util.h +new file mode 100644 +index 000000000000..204de7584c25 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/util.h +@@ -0,0 +1,2 @@ ++int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len); ++struct scatterlist *sg_advance(struct scatterlist *sg, int consumed); +diff --git a/drivers/sstar/crypto/cryptodev/version.h b/drivers/sstar/crypto/cryptodev/version.h +new file mode 100644 +index 000000000000..4adf5a93e7cf +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/version.h +@@ -0,0 +1 @@ ++#define VERSION "1.10(a1e738a)" +diff --git a/drivers/sstar/crypto/cryptodev/zc.c b/drivers/sstar/crypto/cryptodev/zc.c +new file mode 100644 +index 000000000000..ae464ff69992 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/zc.c +@@ -0,0 +1,220 @@ ++/* ++ * Driver for /dev/crypto device (aka CryptoDev) ++ * ++ * Copyright (c) 2009-2013 Nikos Mavrogiannopoulos ++ * Copyright (c) 2010 Phil Sutter ++ * Copyright (c) 2011, 2012 OpenSSL Software Foundation, Inc. ++ * ++ * This file is part of linux cryptodev. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cryptodev_int.h" ++#include "zc.h" ++#include "version.h" ++ ++/* Helper functions to assist zero copy. ++ * This needs to be redesigned and moved out of the session. --nmav ++ */ ++ ++/* offset of buf in it's first page */ ++#define PAGEOFFSET(buf) ((unsigned long)buf & ~PAGE_MASK) ++ ++/* fetch the pages addr resides in into pg and initialise sg with them */ ++int __get_userbuf(uint8_t __user *addr, uint32_t len, int write, ++ unsigned int pgcount, struct page **pg, struct scatterlist *sg, ++ struct task_struct *task, struct mm_struct *mm) ++{ ++ int ret, pglen, i = 0; ++ struct scatterlist *sgp; ++ ++ if (unlikely(!pgcount || !len || !addr)) { ++ sg_mark_end(sg); ++ return 0; ++ } ++ ++ down_read(&mm->mmap_sem); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0)) ++ ret = get_user_pages(task, mm, ++ (unsigned long)addr, pgcount, write, 0, pg, NULL); ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) ++ ret = get_user_pages_remote(task, mm, ++ (unsigned long)addr, pgcount, write, 0, pg, NULL); ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)) ++ ret = get_user_pages_remote(task, mm, ++ (unsigned long)addr, pgcount, write ? FOLL_WRITE : 0, ++ pg, NULL); ++#else ++ ret = get_user_pages_remote(task, mm, ++ (unsigned long)addr, pgcount, write ? FOLL_WRITE : 0, ++ pg, NULL, NULL); ++#endif ++ up_read(&mm->mmap_sem); ++ if (ret != pgcount) ++ return -EINVAL; ++ ++ sg_init_table(sg, pgcount); ++ ++ pglen = min((ptrdiff_t)(PAGE_SIZE - PAGEOFFSET(addr)), (ptrdiff_t)len); ++ sg_set_page(sg, pg[i++], pglen, PAGEOFFSET(addr)); ++ ++ len -= pglen; ++ for (sgp = sg_next(sg); len; sgp = sg_next(sgp)) { ++ pglen = min((uint32_t)PAGE_SIZE, len); ++ sg_set_page(sgp, pg[i++], pglen, 0); ++ len -= pglen; ++ } ++ sg_mark_end(sg_last(sg, pgcount)); ++ return 0; ++} ++ ++int adjust_sg_array(struct csession *ses, int pagecount) ++{ ++ struct scatterlist *sg; ++ struct page **pages; ++ int array_size; ++ ++ for (array_size = ses->array_size; array_size < pagecount; ++ array_size *= 2) ++ ; ++ ddebug(0, "reallocating from %d to %d pages", ++ ses->array_size, array_size); ++ pages = krealloc(ses->pages, array_size * sizeof(struct page *), ++ GFP_KERNEL); ++ if (unlikely(!pages)) ++ return -ENOMEM; ++ ses->pages = pages; ++ sg = krealloc(ses->sg, array_size * sizeof(struct scatterlist), ++ GFP_KERNEL); ++ if (unlikely(!sg)) ++ return -ENOMEM; ++ ses->sg = sg; ++ ses->array_size = array_size; ++ ++ return 0; ++} ++ ++void release_user_pages(struct csession *ses) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ses->used_pages; i++) { ++ if (!PageReserved(ses->pages[i])) ++ SetPageDirty(ses->pages[i]); ++ ++ if (ses->readonly_pages == 0) ++ flush_dcache_page(ses->pages[i]); ++ else ++ ses->readonly_pages--; ++ ++ put_page(ses->pages[i]); ++ } ++ ses->used_pages = 0; ++} ++ ++/* make src and dst available in scatterlists. ++ * dst might be the same as src. ++ */ ++int get_userbuf(struct csession *ses, ++ void *__user src, unsigned int src_len, ++ void *__user dst, unsigned int dst_len, ++ struct task_struct *task, struct mm_struct *mm, ++ struct scatterlist **src_sg, ++ struct scatterlist **dst_sg) ++{ ++ int src_pagecount, dst_pagecount; ++ int rc; ++ ++ /* Empty input is a valid option to many algorithms & is tested by NIST/FIPS */ ++ /* Make sure NULL input has 0 length */ ++ if (!src && src_len) ++ src_len = 0; ++ ++ /* I don't know that null output is ever useful, but we can handle it gracefully */ ++ /* Make sure NULL output has 0 length */ ++ if (!dst && dst_len) ++ dst_len = 0; ++ ++ src_pagecount = PAGECOUNT(src, src_len); ++ dst_pagecount = PAGECOUNT(dst, dst_len); ++ ++ ses->used_pages = (src == dst) ? max(src_pagecount, dst_pagecount) ++ : src_pagecount + dst_pagecount; ++ ++ ses->readonly_pages = (src == dst) ? 0 : src_pagecount; ++ ++ if (ses->used_pages > ses->array_size) { ++ rc = adjust_sg_array(ses, ses->used_pages); ++ if (rc) ++ return rc; ++ } ++ ++ if (src == dst) { /* inplace operation */ ++ /* When we encrypt for authenc modes we need to write ++ * more data than the ones we read. */ ++ if (src_len < dst_len) ++ src_len = dst_len; ++ rc = __get_userbuf(src, src_len, 1, ses->used_pages, ++ ses->pages, ses->sg, task, mm); ++ if (unlikely(rc)) { ++ derr(1, "failed to get user pages for data IO"); ++ return rc; ++ } ++ (*src_sg) = (*dst_sg) = ses->sg; ++ return 0; ++ } ++ ++ *src_sg = NULL; /* default to no input */ ++ *dst_sg = NULL; /* default to ignore output */ ++ ++ if (likely(src)) { ++ rc = __get_userbuf(src, src_len, 0, ses->readonly_pages, ++ ses->pages, ses->sg, task, mm); ++ if (unlikely(rc)) { ++ derr(1, "failed to get user pages for data input"); ++ return rc; ++ } ++ *src_sg = ses->sg; ++ } ++ ++ if (likely(dst)) { ++ const unsigned int writable_pages = ++ ses->used_pages - ses->readonly_pages; ++ struct page **dst_pages = ses->pages + ses->readonly_pages; ++ *dst_sg = ses->sg + ses->readonly_pages; ++ ++ rc = __get_userbuf(dst, dst_len, 1, writable_pages, ++ dst_pages, *dst_sg, task, mm); ++ if (unlikely(rc)) { ++ derr(1, "failed to get user pages for data output"); ++ release_user_pages(ses); /* FIXME: use __release_userbuf(src, ...) */ ++ return rc; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/crypto/cryptodev/zc.h b/drivers/sstar/crypto/cryptodev/zc.h +new file mode 100644 +index 000000000000..666c4a54a609 +--- /dev/null ++++ b/drivers/sstar/crypto/cryptodev/zc.h +@@ -0,0 +1,25 @@ ++#ifndef ZC_H ++# define ZC_H ++ ++/* For zero copy */ ++int __get_userbuf(uint8_t __user *addr, uint32_t len, int write, ++ unsigned int pgcount, struct page **pg, struct scatterlist *sg, ++ struct task_struct *task, struct mm_struct *mm); ++void release_user_pages(struct csession *ses); ++ ++int get_userbuf(struct csession *ses, ++ void *__user src, unsigned int src_len, ++ void *__user dst, unsigned int dst_len, ++ struct task_struct *task, struct mm_struct *mm, ++ struct scatterlist **src_sg, ++ struct scatterlist **dst_sg); ++ ++/* buflen ? (last page - first page + 1) : 0 */ ++#define PAGECOUNT(buf, buflen) ((buflen) \ ++ ? ((((unsigned long)(buf + buflen - 1)) >> PAGE_SHIFT) - \ ++ (((unsigned long)(buf )) >> PAGE_SHIFT) + 1) \ ++ : 0) ++ ++#define DEFAULT_PREALLOC_PAGES 32 ++ ++#endif +diff --git a/drivers/sstar/crypto/hal/infinity2m/halAESDMA.h b/drivers/sstar/crypto/hal/infinity2m/halAESDMA.h +new file mode 100755 +index 000000000000..c8b4865ff7de +--- /dev/null ++++ b/drivers/sstar/crypto/hal/infinity2m/halAESDMA.h +@@ -0,0 +1,214 @@ ++/* ++* halAESDMA.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++#define CONFIG_SRAM_DUMMY_ACCESS_RSA ++//#define CONFIG_SRAM_DUMMY_ACCESS_SHA ++ ++#define CONFIG_MS_CRYPTO_SUPPORT_AES256 1 ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++#define SHARNG_CTRL_SHA_INIT_HASH 0x2000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_ReadOut(U32 u32Buf); ++void HAL_SHA_SetInitHashMode(U8 uMode); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++U16 HAL_RNG_Read(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/hal/infinity3/halAESDMA.h b/drivers/sstar/crypto/hal/infinity3/halAESDMA.h +new file mode 100755 +index 000000000000..6cd2378f1087 +--- /dev/null ++++ b/drivers/sstar/crypto/hal/infinity3/halAESDMA.h +@@ -0,0 +1,211 @@ ++/* ++* halAESDMA.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++ ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++#define SHARNG_CTRL_SHA_INIT_HASH 0x2000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_ReadOut(U32 u32Buf); ++void HAL_SHA_SetInitHashMode(U8 uMode); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++U16 HAL_RNG_Read(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/hal/infinity5/halAESDMA.h b/drivers/sstar/crypto/hal/infinity5/halAESDMA.h +new file mode 100755 +index 000000000000..6cd2378f1087 +--- /dev/null ++++ b/drivers/sstar/crypto/hal/infinity5/halAESDMA.h +@@ -0,0 +1,211 @@ ++/* ++* halAESDMA.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++ ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++#define SHARNG_CTRL_SHA_INIT_HASH 0x2000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_ReadOut(U32 u32Buf); ++void HAL_SHA_SetInitHashMode(U8 uMode); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++U16 HAL_RNG_Read(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/hal/infinity6/halAESDMA.h b/drivers/sstar/crypto/hal/infinity6/halAESDMA.h +new file mode 100755 +index 000000000000..84884ae4280a +--- /dev/null ++++ b/drivers/sstar/crypto/hal/infinity6/halAESDMA.h +@@ -0,0 +1,211 @@ ++/* ++* halAESDMA.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++#define CONFIG_MS_CRYPTO_SUPPORT_AES256 1 ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++#define SHARNG_CTRL_SHA_INIT_HASH 0x2000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_ReadOut(U32 u32Buf); ++void HAL_SHA_SetInitHashMode(U8 uMode); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++U16 HAL_RNG_Read(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/hal/infinity6b0/halAESDMA.h b/drivers/sstar/crypto/hal/infinity6b0/halAESDMA.h +new file mode 100755 +index 000000000000..c8b4865ff7de +--- /dev/null ++++ b/drivers/sstar/crypto/hal/infinity6b0/halAESDMA.h +@@ -0,0 +1,214 @@ ++/* ++* halAESDMA.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++#define CONFIG_SRAM_DUMMY_ACCESS_RSA ++//#define CONFIG_SRAM_DUMMY_ACCESS_SHA ++ ++#define CONFIG_MS_CRYPTO_SUPPORT_AES256 1 ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++#define SHARNG_CTRL_SHA_INIT_HASH 0x2000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_ReadOut(U32 u32Buf); ++void HAL_SHA_SetInitHashMode(U8 uMode); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++U16 HAL_RNG_Read(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/hal/infinity6e/halAESDMA.h b/drivers/sstar/crypto/hal/infinity6e/halAESDMA.h +new file mode 100644 +index 000000000000..84884ae4280a +--- /dev/null ++++ b/drivers/sstar/crypto/hal/infinity6e/halAESDMA.h +@@ -0,0 +1,211 @@ ++/* ++* halAESDMA.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++#define CONFIG_MS_CRYPTO_SUPPORT_AES256 1 ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++#define SHARNG_CTRL_SHA_INIT_HASH 0x2000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_ReadOut(U32 u32Buf); ++void HAL_SHA_SetInitHashMode(U8 uMode); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++U16 HAL_RNG_Read(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/halAESDMA.c b/drivers/sstar/crypto/halAESDMA.c +new file mode 100755 +index 000000000000..b2b24c0735a5 +--- /dev/null ++++ b/drivers/sstar/crypto/halAESDMA.c +@@ -0,0 +1,700 @@ ++/* ++* halAESDMA.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include "ms_platform.h" ++ ++#ifndef _HAL_AESDMA_H_ ++#include "halAESDMA.h" ++#include "mstar_chip.h" ++#endif ++#include ++#if 0 ++void HAL_AESDMA_DisableXIUSelectCA9(void) ++{ ++ //disable AESDMA XIU select CA9 ++ RIU[(AESDMA_BASE_ADDR+(0x5F<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5F<<1))])&(~AESDMA_CTRL_XIU_SEL_CA9)); ++} ++ ++void HAL_AESDMA_WB2DMADisable(void) ++{ ++ // WB2DMA read & write disable ++ RIU[(DMA_SECURE_BASE_ADDR+(0x79<<1))]= ((RIU[(DMA_SECURE_BASE_ADDR+(0x79<<1))])&(~(DMA_SECURE_CTRL_WB2DMA_R_EN|DMA_SECURE_CTRL_WB2DMA_W_EN))); ++} ++ ++void HAL_AESDMA_ShaFromOutput(void) ++{ ++ // SHA from AESDMA output(XIU) ++ RIU[(AESDMA_BASE_ADDR+(0x5F<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5F<<1))])|(AESDMA_CTRL_SHA_FROM_OUT)); ++} ++ ++void HAL_AESDMA_ShaFromInput(void) ++{ ++ // SHA from AESDMA input(XIU) ++ RIU[(AESDMA_BASE_ADDR+(0x5F<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5F<<1))])|(AESDMA_CTRL_SHA_FROM_IN)); ++} ++#endif ++void HAL_AESDMA_INTMASK(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]) | (1<<7)); ++} ++ ++void HAL_AESDMA_INTDISABLE(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]) & ~(1<<7)); ++} ++ ++ ++void HAL_AESDMA_SetXIULength(U32 u32Size) ++{ ++ // AESDMA XIU length (byte):54~55 ++ RIU[(AESDMA_BASE_ADDR+(0x54<<1))]= (U16)((0x0000ffff)&(u32Size)); ++ RIU[(AESDMA_BASE_ADDR+(0x55<<1))]= (U16)(((0xffff0000)&(u32Size))>>16); ++} ++ ++void HAL_AESDMA_UseHwKey(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))]= (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_HW_KEY); ++} ++ ++void HAL_AESDMA_UseEfuseKey(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))]= (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_EFUSE_KEY); ++} ++ ++void HAL_AESDMA_UseCipherKey(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))]= (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_CIPHER_KEY); ++} ++ ++void HAL_AESDMA_CipherEncrypt(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))]) & (~AESDMA_CTRL_CIPHER_DECRYPT)); ++} ++ ++void HAL_AESDMA_CipherDecrypt(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))])|(AESDMA_CTRL_CIPHER_DECRYPT)); ++} ++ ++void HAL_AESDMA_Enable(U16 u16engine) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))]) | u16engine); ++} ++ ++void HAL_AESDMA_Disable(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))])&(~AESDMA_CTRL_AES_EN)); ++} ++ ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable) ++{ ++ // AESDMA fout_en ++ if(u8FileOutEnable==1) ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))]) | AESDMA_CTRL_FOUT_EN); ++ /*MCM*/ ++ //RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))]) | 0x1000); ++ //RIU[(AESDMA_BASE_ADDR+(0x77<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x77<<1))]) | 0x003F); ++ } ++ else ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])&(~AESDMA_CTRL_FOUT_EN)); ++ } ++} ++ ++void HAL_AESDMA_SetFileinAddr(U32 u32addr) ++{ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(AESDMA_BASE_ADDR+(0x52<<1))]= (U16)((0x0000ffff)&(u32addr)); ++ RIU[(AESDMA_BASE_ADDR+(0x53<<1))]= (U16)(((0xffff0000)&(u32addr))>>16); ++} ++ ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size) ++{ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(AESDMA_BASE_ADDR+(0x56<<1))]= (U16)((0x0000ffff)&(u32addr)); ++ RIU[(AESDMA_BASE_ADDR+(0x57<<1))]= (U16)(((0xffff0000)&(u32addr))>>16); ++ ++ RIU[(AESDMA_BASE_ADDR+(0x58<<1))]= (U16)((0x0000ffff)&(u32addr+u32Size-1)); ++ RIU[(AESDMA_BASE_ADDR+(0x59<<1))]= (U16)(((0xffff0000)&(u32addr+u32Size-1))>>16); ++} ++ ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key) ++{ ++ int i; ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] =((pu16Key[i] & 0x00FF)<<8)|((pu16Key[i] & 0xFF00)>>8); ++ } ++} ++ ++#define OFFSET_REG_ENG3_CTRL_S 0x77 ++#define KEY_LEN_AES128 0 ++#define KEY_LEN_AES192 0x00001000 ++#define KEY_LEN_AES256 0x00002000 ++#define KEY_LEN_MASK 0x00003000 ++#define BASE_RIU_ADDR_AESDMA (0x1F000000+AESDMA_BASE_ADDR*2) ++ ++void HAL_AESDMA_SetCipherKey2(U16 *pu16Key, U32 len) ++{ ++ int i; ++ ++ if(len==16) ++ OUTREGMSK16(BASE_RIU_ADDR_AESDMA+((OFFSET_REG_ENG3_CTRL_S)<<2), KEY_LEN_AES128, KEY_LEN_MASK ); ++ else if(len==24) ++ OUTREGMSK16(BASE_RIU_ADDR_AESDMA+((OFFSET_REG_ENG3_CTRL_S)<<2), KEY_LEN_AES192, KEY_LEN_MASK ); ++ else if(len==32) ++ OUTREGMSK16(BASE_RIU_ADDR_AESDMA+((OFFSET_REG_ENG3_CTRL_S)<<2), KEY_LEN_AES256, KEY_LEN_MASK ); ++ ++ CLRREG16(BASE_RIU_ADDR_AESDMA+((OFFSET_REG_ENG3_CTRL_S)<<2), 0x800 ); ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] =((pu16Key[i] & 0x00FF)<<8)|((pu16Key[i] & 0xFF00)>>8); ++ } ++ ++ if(len==24) ++ { ++ SETREG16(BASE_RIU_ADDR_AESDMA+((OFFSET_REG_ENG3_CTRL_S)<<2), 0x800 ); ++ for(i=0;i<4;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] =((pu16Key[i+8] & 0x00FF)<<8)|((pu16Key[i+8] & 0xFF00)>>8); ++ } ++ } ++ else if(len==32) ++ { ++ SETREG16(BASE_RIU_ADDR_AESDMA+((OFFSET_REG_ENG3_CTRL_S)<<2), 0x800 ); ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] =((pu16Key[i+8] & 0x00FF)<<8)|((pu16Key[i+8] & 0xFF00)>>8); ++ } ++ } ++} ++ ++void HAL_AESDMA_SetIV(U16 *pu16IV) ++{ ++ int i; ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x6F-i)<<1))] = ((pu16IV[i] & 0x00FF)<<8)|((pu16IV[i] & 0xFF00)>>8); ++ } ++} ++ ++void HAL_AESDMA_SetChainModeECB(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = (RIU[(AESDMA_BASE_ADDR+(0x51<<1))] & AESDMA_CTRL_CHAINMODE_CLEAR) | AESDMA_CTRL_CHAINMODE_ECB; ++} ++ ++void HAL_AESDMA_SetChainModeCTR(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = (RIU[(AESDMA_BASE_ADDR+(0x51<<1))] & AESDMA_CTRL_CHAINMODE_CLEAR) | AESDMA_CTRL_CHAINMODE_CTR; ++} ++ ++void HAL_AESDMA_SetChainModeCBC(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = (RIU[(AESDMA_BASE_ADDR+(0x51<<1))] & AESDMA_CTRL_CHAINMODE_CLEAR) | AESDMA_CTRL_CHAINMODE_CBC; ++} ++ ++void HAL_AESDMA_Reset(void) ++{ ++ int i; ++ ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))] = AESDMA_CTRL_SW_RST; ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x52<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x53<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x54<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x55<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x56<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x57<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x58<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x59<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))] = (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_CIPHER_KEY); ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] = 0; ++ } ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x6F-i)<<1))] = 0; ++ } ++} ++ ++void HAL_AESDMA_Start(U8 u8AESDMAStart) ++{ ++ // AESDMA file start ++ if(u8AESDMAStart==1) ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])|(AESDMA_CTRL_FILE_ST)); ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])&(~AESDMA_CTRL_FILE_ST)); ++ } ++ else ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])&(~AESDMA_CTRL_FILE_ST)); ++ } ++} ++ ++U16 HAL_AESDMA_GetStatus(void) ++{ ++ return RIU[(AESDMA_BASE_ADDR+(0x7F<<1))]; ++} ++ ++void HAL_RSA_ClearInt(void) ++{ ++ //RSA interrupt clear ++ RIU[(RSA_BASE_ADDR+(0x27<<1))]= ((RIU[(RSA_BASE_ADDR+(0x27<<1))])|(RSA_INT_CLR)); ++} ++ ++void HAL_RSA_Reset(void) ++{ ++ //RSA Rst ++ RIU[(RSA_BASE_ADDR+(0x28<<1))]= ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(RSA_CTRL_RSA_RST)); ++ RIU[(RSA_BASE_ADDR+(0x28<<1))]= ((RIU[(RSA_BASE_ADDR+(0x28<<1))])&(~RSA_CTRL_RSA_RST)); ++} ++ ++void HAL_RSA_Ind32Ctrl(U8 u8dirction) ++{ ++ //[1] reg_ind32_direction 0: Read. 1: Write ++ if(u8dirction==1) ++ { ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])|(RSA_IND32_CTRL_DIRECTION_WRITE)); ++ } ++ else ++ { ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])&(~RSA_IND32_CTRL_DIRECTION_WRITE)); ++ } ++ //[2] reg_addr_auto_inc : Set 1 to enable address auto-increment after finishing read/write ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])|(RSA_IND32_CTRL_ADDR_AUTO_INC)); ++ ++ //[3] Set 1 to enable access auto-start after writing Data[31:16] ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])|(RSA_IND32_CTRL_ACCESS_AUTO_START)); ++} ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh) ++{ ++ // RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_E+i))>>8)&0xFF00)|(((*(ptr_E+i))>>24)&0xFF); ++ // RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_E+i))>>8)&0xFF)|(((*(ptr_E+i))<<8)&0xFF00); ++ U32 i; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ U16 dummy; ++#endif ++ U8 lentgh = u8Signlentgh; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_A_BASE_ADDR; //RSA A addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ for( i = 0; i < lentgh ; i++ ) ++ { ++ //RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_Sign+63-i))>>8)&0xFF00)|(((*(ptr_Sign+63-i))>>24)&0xFF); ++ //RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_Sign+63-i))>>8)&0xFF)|(((*(ptr_Sign+63-i))<<8)&0xFF00); ++ ++// RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_Sign + i))>>8)&0xFF00)|(((*(ptr_Sign + i))>>24)&0xFF); ++// RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_Sign + i))>>8)&0xFF)|(((*(ptr_Sign + i))<<8)&0xFF00); ++ ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_Sign + (lentgh-1) - i))>>8)&0xFF00)|(((*(ptr_Sign + (lentgh-1) - i))>>24)&0xFF); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x23<<1))]; ++#endif ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_Sign + (lentgh-1) - i))>>8)&0xFF)|(((*(ptr_Sign + (lentgh-1) - i))<<8)&0xFF00); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x24<<1))]; ++#endif ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++/* ++void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign) ++{ ++ ++ S32 i; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_A_BASE_ADDR; //RSA A addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ for( i = 127; i >= 0; i -= 2 ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)( ((*(ptr_Sign+i) << 8) & 0xFF00) | ((*(ptr_Sign+i) >> 8) & 0xFF) ); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)( ((*(ptr_Sign+i-1) << 8) & 0xFF00) | ((*(ptr_Sign+i-1) >> 8) & 0xFF) ); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++}*/ ++ ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh) ++{ ++ U32 i; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_E_BASE_ADDR; //RSA E addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xA<<1))]=(U16)((0x0000ffff)&(U32)(ptr_E)); //write ptr_E addr to por_status(0x10050A) ++ ++ for( i = 0; i < u8Elentgh ; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_E + i))>>8)&0xFF00)|(((*(ptr_E + i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_E + i))>>8)&0xFF)|(((*(ptr_E + i))<<8)&0xFF00); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++ ++void HAL_RSA_LoadKeyN(U32 *ptr_N ,U8 u8Nlentgh) ++{ ++ U32 i; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_N_BASE_ADDR; //RSA N addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xB<<1))]=(U16)((0x0000ffff)&(U32)(ptr_N)); //write ptr_N addr to por_status(0x10050B) ++ ++ for( i = 0; i < u8Nlentgh; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_N+i))>>8)&0xFF00)|(((*(ptr_N+i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_N+i))>>8)&0xFF)|(((*(ptr_N+i))<<8)&0xFF00); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++ ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N,U8 u8Nlentgh) ++{ ++ U32 i; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ U16 dummy; ++#endif ++ U8 lentgh = u8Nlentgh; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_N_BASE_ADDR; //RSA N addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xB<<1))]=(U16)((0x0000ffff)&(U32)(ptr_N)); //write ptr_N addr to por_status(0x10050B) ++ ++ for( i = 0; i < lentgh; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_N + (lentgh-1) - i))>>8)&0xFF00)|(((*(ptr_N + (lentgh-1) - i))>>24)&0xFF); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x23<<1))]; ++#endif ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_N + (lentgh-1) - i))>>8)&0xFF)|(((*(ptr_N + (lentgh-1) - i))<<8)&0xFF00); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x24<<1))]; ++#endif ++ } ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++ ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_E,U8 u8Elentgh) ++{ ++ U32 i; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ U16 dummy; ++#endif ++ U8 lentgh = u8Elentgh; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_E_BASE_ADDR; ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xB<<1))]=(U16)((0x0000ffff)&(U32)(ptr_N)); //write ptr_N addr to por_status(0x10050B) ++ ++ for( i = 0; i < lentgh; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_E + (lentgh-1) - i))>>8)&0xFF00)|(((*(ptr_E + (lentgh-1) - i))>>24)&0xFF); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x23<<1))]; ++#endif ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_E + (lentgh-1) - i))>>8)&0xFF)|(((*(ptr_E + (lentgh-1) - i))<<8)&0xFF00); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x24<<1))]; ++#endif ++ } ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++ ++} ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen) ++{ ++ //[13:8] n_len_e: key length, if hardware key set, this register is ignored and hardware internal using 3f ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(u16keylen<<8)); ++} ++ ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey) ++{ ++ //[1] hw_key_e : 0 : software key, 1: hardware key ++ //[2] e_pub_e : 0: pvivate key, 1: public key ++ if(u8hwkey==1) ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(RSA_SEL_HW_KEY)); ++ } ++ else ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])&(~RSA_SEL_HW_KEY)); ++ } ++ ++ if(u8pubkey==1) ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(RSA_SEL_PUBLIC_KEY)); ++ } ++ else ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])&(~RSA_SEL_PUBLIC_KEY)); ++ } ++ ++} ++ ++void HAL_RSA_ExponetialStart(void) ++{ ++ //RSA exp start ++ RIU[(RSA_BASE_ADDR+(0x27<<1))] = ((RIU[(RSA_BASE_ADDR+(0x27<<1))])|(RSA_EXP_START)); ++} ++ ++U16 HAL_RSA_GetStatus(void) ++{ ++ return RIU[(RSA_BASE_ADDR+(0x29<<1))]; ++} ++ ++void HAL_RSA_FileOutStart(void) ++{ ++ //RSA ind32_start ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); ++} ++ ++void HAL_RSA_FileOutEnd(void) ++{ ++ //RSA ind32_start ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); ++} ++ ++void HAL_RSA_SetFileOutAddr(U32 u32offset) ++{ ++ //RSA ind32_addr ++ RIU[(RSA_BASE_ADDR+(0x22<<1))] = (U16)(RSA_Z_BASE_ADDR + u32offset); ++} ++ ++U32 HAL_RSA_FileOut(void) ++{ ++ U32 output; ++ U32 dummy; ++ //output = (U16)(((RIU[(RSA_BASE_ADDR+(0x26<<1))] >>8 )& 0xff )|((RIU[(RSA_BASE_ADDR+(0x26<<1))] << 8 )& 0xff00 )) ; ++ //output = output | ((((RIU[(RSA_BASE_ADDR+(0x25<<1))]>>8)& 0xff)|((RIU[(RSA_BASE_ADDR+(0x25<<1))]<<8)& 0xff00)) << 16); ++ dummy = RIU[(RSA_BASE_ADDR+(0x26<<1))]; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x26<<1))]; ++#endif ++ output = (U16)(((dummy >> 8) & 0xFF) | ((dummy << 8) & 0xFF00)); ++ ++ dummy = RIU[(RSA_BASE_ADDR+(0x25<<1))]; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_RSA ++ dummy = RIU[(RSA_BASE_ADDR+(0x25<<1))]; ++#endif ++ output = output | ((((dummy >> 8) & 0xFF) | ((dummy << 8) & 0xFF00)) << 16); ++ ++ return output; ++} ++ ++void HAL_SHA_Reset(void) ++{ ++ //SHA_Reset ++ RIU[SHARNG_BASE_ADDR+(0x08<<1)]= (RIU[SHARNG_BASE_ADDR+(0x08<<1)]|(SHARNG_CTRL_SHA_RST)); ++ RIU[SHARNG_BASE_ADDR+(0x08<<1)]= (RIU[SHARNG_BASE_ADDR+(0x08<<1)]&(~SHARNG_CTRL_SHA_RST)); ++ ++ //Clear reg_dma4_ctrl_s ++ RIU[SHARNG_BASE_ADDR+(0x5d<<1)]= 0; ++} ++ ++void HAL_SHA_SetAddress(U32 u32Address) ++{ ++ /**/ ++ if (u32Address < ARM_MIU1_BASE_ADDR) { ++ RIU[(SHARNG_BASE_ADDR+(0x0E<<1))]= 0x80; ++ } ++ else { ++ RIU[(SHARNG_BASE_ADDR+(0x0E<<1))]= 0x20; ++ } ++ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(SHARNG_BASE_ADDR+(0x0A<<1))]= (U16)((0x0000ffff)&(u32Address)); ++ RIU[(SHARNG_BASE_ADDR+(0x0B<<1))]= (U16)(((0xffff0000)&(u32Address))>>16); ++ ++ // Bypass scatter & gather address ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(1<<11)); ++} ++ ++void HAL_SHA_SetLength(U32 u32Size) ++{ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(SHARNG_BASE_ADDR+(0x0C<<1))]= (U16)((0x0000ffff)&(u32Size)); ++ RIU[(SHARNG_BASE_ADDR+(0x0D<<1))]= (U16)(((0xffff0000)&(u32Size))>>16); ++} ++ ++void HAL_SHA_SelMode(U8 u8sha256) ++{ ++ //SHA_SelMode:58~59(sha_ctrl & sha_scattergather_size) ++ if(u8sha256==1) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_SEL_SHA256)); ++ } ++ else ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_SEL_SHA256)); ++ } ++} ++ ++void HAL_SHA_ManualMode(U8 bManualMode) ++{ ++ if(bManualMode==1) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_WORK_MODE_MANUAL)); ++ } ++ else ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_WORK_MODE_MANUAL)); ++ } ++} ++ ++U16 HAL_SHA_GetStatus(void) ++{ ++ return (RIU[(SHARNG_BASE_ADDR+(0x0F<<1))]); ++} ++ ++void HAL_SHA_Clear(void) ++{ ++ //Set "1" to idle state after reg_read_sha_ready = 1 ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_FIRE_ONCE)); ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_CLR)); ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_CLR)); ++ ++ RIU[(SHARNG_BASE_ADDR+(0x0F<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x0F<<1))])&(~SHARNG_CTRL_SHA_BUSY)); ++} ++ ++void HAL_SHA_Start(void) ++{ ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_FIRE_ONCE)); ++} ++ ++void HAL_SHA_Out(U32 u32Buf) ++{ ++ U32 index; ++ ++// output = (U16)(((RIU[(RSA_BASE_ADDR+(0x26<<1))] >>8 )& 0xff )|((RIU[(RSA_BASE_ADDR+(0x26<<1))] << 8 )& 0xff00 )) ; ++// output = output | ((((RIU[(RSA_BASE_ADDR+(0x25<<1))]>>8)& 0xff)|((RIU[(RSA_BASE_ADDR+(0x25<<1))]<<8)& 0xff00)) << 16); ++ ++ //SHA_Out ++ for( index = 0; index < 16; index++ ) ++ { ++ *((U16 *)u32Buf +(15-index)) = (U16)(RIU[(SHARNG_BASE_ADDR + (0x10<<1) + index*2)]>>8&0xff)|(U16)(RIU[(SHARNG_BASE_ADDR + (0x10<<1) + index*2)]<<8&0xff00); ++ } ++} ++void HAL_SHA_Write_InitValue_BE(U32 u32Buf) ++{ ++ U32 index; ++ ++ for( index = 0; index < 16; index++ ) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x10<<1)+index*2)] = __cpu_to_be16(*((U16 *)u32Buf + (15-index))); ++ } ++} ++ ++void HAL_SHA_ReadOut(U32 u32Buf) ++{ ++ U32 index; ++ ++ //SHA_Out ++ for( index = 0; index < 16; index++ ) ++ { ++ *((U16 *)u32Buf + index) = RIU[(SHARNG_BASE_ADDR+(0x10<<1)+index*2)]; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_SHA ++ *((U16 *)u32Buf + index) = RIU[(SHARNG_BASE_ADDR+(0x10<<1)+index*2)]; ++#endif ++ } ++} ++ ++void HAL_SHA_SetInitHashMode(U8 uMode) ++{ ++ if(uMode) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_INIT_HASH)); ++ } ++ else ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_INIT_HASH)); ++ } ++} ++ ++void HAL_SHA_Write_InitValue(U32 u32Buf) ++{ ++ U32 index; ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_SHA ++ U16 dummy; ++#endif ++ ++ //SHA_Out ++ for( index = 0; index < 16; index++ ) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x10<<1)+index*2)] = *((U16 *)u32Buf + index); ++#ifdef CONFIG_SRAM_DUMMY_ACCESS_SHA ++ dummy = RIU[(SHARNG_BASE_ADDR+(0x10<<1)+index*2)]; ++#endif ++ } ++} ++ ++U32 HAL_SHA_ReadWordCnt(void) ++{ ++ return RIU[(SHARNG_BASE_ADDR+(0x2E<<1))] | (RIU[(SHARNG_BASE_ADDR+(0x2F<<1))] << 16); ++} ++ ++void HAL_SHA_WriteWordCnt(U32 u32Val) ++{ ++ RIU[(SHARNG_BASE_ADDR+(0x2E<<1))] = (U16)(u32Val & 0xFFFF); ++ RIU[(SHARNG_BASE_ADDR+(0x2F<<1))] = (U16)(u32Val >> 16); ++} ++void HAL_MCM(U32 u32Val) ++{ ++ RIU[(0x113200+(0x01<<1))]= (U16)u32Val; ++} ++ ++U16 HAL_RNG_Read(void) ++{ ++ u8 try_count = 20; ++ u16 rng = 0xFFFF; ++ ++ if (((RIU[(RSA_BASE_ADDR+(0x00<<1))]) & 0x80) == 0) ++ { ++ RIU[(RSA_BASE_ADDR+(0x00<<1))] = ((RIU[(RSA_BASE_ADDR+(0x00<<1))])|(0x80)); ++ } ++ do { ++ if ((RIU[(RSA_BASE_ADDR+(0x03<<1))]) & 0x1) ++ { ++ rng = RIU[(RSA_BASE_ADDR+(0x02<<1))]; ++ break; ++ } ++ } while(try_count--); ++ ++ if (rng == 0xFFFF) ++ { ++ rng = RIU[(RSA_BASE_ADDR+(0x02<<1))]; ++ } ++ ++ return rng; ++} ++ +diff --git a/drivers/sstar/crypto/mdrv_aes.c b/drivers/sstar/crypto/mdrv_aes.c +new file mode 100755 +index 000000000000..62a5300e1a5e +--- /dev/null ++++ b/drivers/sstar/crypto/mdrv_aes.c +@@ -0,0 +1,1414 @@ ++/* ++* mdrv_aes.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#if 1 ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "halAESDMA.h" ++#include "mdrv_aes.h" ++#include ++#include "mdrv_cipher.h" ++#include "drv_camclk_Api.h" ++#else ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#ifdef CONFIG_MS_CRYPTO_SUPPORT_AES256 ++int gbSupportAES256 = 1; ++#else ++int gbSupportAES256 = 0; ++#endif ++ ++#define AESDMA_DEBUG (0) ++#if (AESDMA_DEBUG == 1) ++#define AESDMA_DBG(fmt, arg...) printk(KERN_ALERT fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define AESDMA_DBG(fmt, arg...) ++#endif ++#if defined(CONFIG_SS_AESDMA_INTR) && CONFIG_SS_AESDMA_INTR ++#define AESDMA_ISR ++#endif ++ ++#define AESDMA_DES (0) ++#define LOOP_CNT 100 //100ms ++ ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++#define MS_ASSERT(a) ++#define CRYPTO_MUTEX_WAIT_TIME 3000 ++ ++struct mutex _mtcrypto_lock; ++struct platform_device *psg_mdrv_aesdma; ++struct aesdma_alloc_dmem ALLOC_DMEM = {0, 0, "AESDMA_ENG", "AESDMA_ENG1", 0, 0}; ++#ifdef AESDMA_ISR ++static bool _isr_requested = 0; ++static struct completion _mdmadone; ++#endif ++#ifdef CONFIG_CAM_CLK ++void **pvaesclkhandler; ++#endif ++extern int infinity_sha_create(void); ++extern int infinity_sha_destroy(void); ++extern struct miscdevice rsadev; ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr ) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++void _ms_aes_mem_free(void) ++{ ++ //aesdma_vir_SHABuf_addr ++ if(ALLOC_DMEM.aesdma_vir_addr != 0){ ++ //printk( "%s mem free \n",ALLOC_DMEM.DMEM_AES_ENG_INPUT); ++ free_dmem(ALLOC_DMEM.DMEM_AES_ENG_INPUT,AESDMA_ALLOC_MEMSIZE,ALLOC_DMEM.aesdma_vir_addr,ALLOC_DMEM.aesdma_phy_addr); ++ ALLOC_DMEM.aesdma_vir_addr = 0; ++ ALLOC_DMEM.aesdma_phy_addr = 0; ++ } ++ if(ALLOC_DMEM.aesdma_vir_SHABuf_addr != 0){ ++ //printk( "%s mem free \n",ALLOC_DMEM.DMEM_AES_ENG_SHABUF); ++ free_dmem(ALLOC_DMEM.DMEM_AES_ENG_SHABUF,AESDMA_ALLOC_MEMSIZE_TEMP,ALLOC_DMEM.aesdma_vir_SHABuf_addr,ALLOC_DMEM.aesdma_phy_SHABuf_addr); ++ ALLOC_DMEM.aesdma_vir_SHABuf_addr = 0; ++ ALLOC_DMEM.aesdma_phy_SHABuf_addr = 0; ++ } ++} ++void enableClock(void) ++{ ++#ifdef CONFIG_CAM_CLK ++ int num_parents, i; ++ int *aes_clks; ++ ++ if(of_find_property(psg_mdrv_aesdma->dev.of_node,"camclk",&num_parents)) ++ { ++ num_parents /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(num_parents < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, num_parents); ++ return; ++ } ++ aes_clks = kzalloc((sizeof(int) * num_parents), GFP_KERNEL); ++ pvaesclkhandler = kzalloc((sizeof(void *) * num_parents), GFP_KERNEL); ++ if(!aes_clks){ ++ return; ++ } ++ for(i = 0; i < num_parents; i++) ++ { ++ aes_clks[i] = 0; ++ of_property_read_u32_index(psg_mdrv_aesdma->dev.of_node,"camclk", i,&aes_clks[i]); ++ if (!aes_clks[i]) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("aesdma",aes_clks[i],&pvaesclkhandler[i]); ++ CamClkSetOnOff(pvaesclkhandler[i],1); ++ } ++ } ++ kfree(aes_clks); ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#else ++ int num_parents = 0, i = 0; ++ struct clk **aesdma_clks; ++ ++ num_parents = of_clk_get_parent_count(psg_mdrv_aesdma->dev.of_node); ++ ++ if(num_parents > 0) ++ { ++ aesdma_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if (aesdma_clks == NULL) ++ { ++ printk( "[AESDMA] -ENOMEM\n" ); ++ return; ++ } ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ aesdma_clks[i] = of_clk_get(psg_mdrv_aesdma->dev.of_node, i); ++ ++ if (IS_ERR(aesdma_clks[i])) ++ { ++ printk( "[AESDMA] Fail to get clk!\n" ); ++ kfree(aesdma_clks); ++ return; ++ } ++ else ++ { ++ clk_prepare_enable(aesdma_clks[i]); ++ } ++ clk_put(aesdma_clks[i]); ++ } ++ kfree(aesdma_clks); ++ } ++#endif ++} ++ ++void disableClock(void) ++{ ++#ifdef CONFIG_CAM_CLK ++ int num_parents, i; ++ int *aes_clks; ++ if(of_find_property(psg_mdrv_aesdma->dev.of_node,"camclk",&num_parents)) ++ { ++ num_parents /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(num_parents < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, num_parents); ++ return; ++ } ++ aes_clks = kzalloc((sizeof(int) * num_parents), GFP_KERNEL); ++ if(!aes_clks){ ++ return; ++ } ++ for(i = 0; i < num_parents; i++) ++ { ++ of_property_read_u32_index(psg_mdrv_aesdma->dev.of_node,"camclk", i,&aes_clks[i]); ++ if (!aes_clks[i]) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkSetOnOff(pvaesclkhandler[i],0); ++ CamClkUnregister(pvaesclkhandler[i]); ++ } ++ } ++ kfree(aes_clks); ++ kfree(pvaesclkhandler); ++ pvaesclkhandler = NULL; ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#else ++ int num_parents = 0, i = 0; ++ ++ struct clk **aesdma_clks; ++ ++ num_parents = of_clk_get_parent_count(psg_mdrv_aesdma->dev.of_node); ++ if(num_parents > 0) ++ { ++ aesdma_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ if (aesdma_clks == NULL) ++ { ++ printk( "[AESDMA] -ENOMEM\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ aesdma_clks[i] = of_clk_get(psg_mdrv_aesdma->dev.of_node, i); ++ if (IS_ERR(aesdma_clks[i])) ++ { ++ printk( "[AESDMA] Fail to get clk!\n" ); ++ kfree(aesdma_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(aesdma_clks[i]); ++ } ++ clk_put(aesdma_clks[i]); ++ } ++ kfree(aesdma_clks); ++ } ++#endif ++} ++ ++void allocMem(U32 len) ++{ ++ if (!(ALLOC_DMEM.aesdma_vir_addr = alloc_dmem(ALLOC_DMEM.DMEM_AES_ENG_INPUT, ++ len,//AESDMA_ALLOC_MEMSIZE, ++ &ALLOC_DMEM.aesdma_phy_addr))){ ++ printk("[input]unable to allocate aesdma memory\n"); ++ } ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, len);//AESDMA_ALLOC_MEMSIZE); ++} ++ ++#ifdef AESDMA_ISR ++static irqreturn_t aes_dma_interrupt(int irq, void *argu) ++{ ++ int status = 0; ++ ++ status = HAL_AESDMA_GetStatus(); ++ if(status & AESDMA_CTRL_DMA_DONE) ++ { ++ complete(&_mdmadone); ++ HAL_AESDMA_INTDISABLE(); ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++int infinity_aes_crypt_pub(struct infinity_aes_op *op, u32 in_addr, u32 out_addr) ++{ ++ unsigned long start = 0, err = 0; ++ unsigned long timeout; ++ unsigned int wait_min = 0, wait_max = 0; ++ int bIn_atomic=0; ++ bIn_atomic = in_atomic(); ++ ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ Chip_Flush_MIU_Pipe(); ++ HAL_AESDMA_Reset(); ++ ++ HAL_AESDMA_SetFileinAddr(Chip_Phys_to_MIU(in_addr)); ++ HAL_AESDMA_SetXIULength(op->len); ++ HAL_AESDMA_SetFileoutAddr(Chip_Phys_to_MIU(out_addr), op->len); ++ ++ if(op->key[0]=='S' && op->key[1]=='S' && op->key[2]=='t' && op->key[3]=='a' && op->key[4]=='r' && op->key[5]=='U') //SStarU ++ { ++ AESDMA_DBG("%s %d, use AES unique key\n", __FUNCTION__, __LINE__); ++ HAL_AESDMA_UseEfuseKey(); ++ } ++ else if(op->keylen==1 && op->key[0]==E_AES_KEY_SRC_INT_CONST) ++ { ++ HAL_AESDMA_UseHwKey(); ++ } ++ else ++ { ++ HAL_AESDMA_UseCipherKey(); ++ HAL_AESDMA_SetCipherKey2((U16*)op->key, op->keylen); ++ } ++ ++ if ((op->mode == AES_MODE_CBC) || (op->mode == AES_MODE_CTR)) ++ { ++ HAL_AESDMA_SetIV((U16*)op->iv); ++ } ++ ++ HAL_AESDMA_Enable(AESDMA_CTRL_AES_EN); ++ switch(op->mode) { ++ case AES_MODE_ECB: ++ HAL_AESDMA_SetChainModeECB(); ++ break; ++ case AES_MODE_CBC: ++ HAL_AESDMA_SetChainModeCBC(); ++ break; ++ case AES_MODE_CTR: ++ HAL_AESDMA_SetChainModeCTR(); ++ break; ++ default: ++ return -1; ++ } ++ ++ if(op->dir == AES_DIR_DECRYPT) ++ { ++ HAL_AESDMA_CipherDecrypt(); ++ } ++ ++ HAL_AESDMA_FileOutEnable(1); ++#ifdef AESDMA_ISR ++ /* CAUTION: In tcrypt.ko test self, someone use atomic operation that make BUG()*/ ++ if(_isr_requested && !bIn_atomic) ++ { ++ reinit_completion(&_mdmadone); ++ HAL_AESDMA_INTMASK(); ++ } ++#endif ++ HAL_AESDMA_Start(1); ++ ++ start = jiffies; ++#ifdef AESDMA_ISR ++ if(_isr_requested && !bIn_atomic) ++ { ++ if(!wait_for_completion_timeout(&_mdmadone, msecs_to_jiffies(LOOP_CNT))) ++ { ++ err = -1; ++ } ++ } ++ else ++#endif ++ { ++ timeout = start + msecs_to_jiffies(LOOP_CNT); ++ ++ // Wait for ready. ++ wait_min = (op->len * 8) >> 10; ++ wait_max = (op->len * 10) >> 10; ++ if(!bIn_atomic && wait_min >= 10) ++ { ++ usleep_range(wait_min, wait_max); ++ } ++ ++ while((HAL_AESDMA_GetStatus() & AESDMA_CTRL_DMA_DONE) != AESDMA_CTRL_DMA_DONE) ++ { ++ if (time_after_eq(jiffies, timeout)) ++ { ++ err = -1; ++ break; ++ } ++ /* CAUTION: In crypto test self task, crypto_ecb_crypt use atomic operation kmap_atomic that make BUG()*/ ++ if(!bIn_atomic) ++ { ++ schedule(); ++ } ++ } ++ } ++ ++ AESDMA_DBG("Elapsed time: %lu jiffies\n", jiffies - start); ++ ++ Chip_Flush_MIU_Pipe(); ++ HAL_AESDMA_Reset(); ++ if (err<0) ++ { ++ printk("AES timeout\n"); ++ return err; ++ } ++ return op->len; ++} ++ ++// return: op length ++static unsigned int infinity_aes_crypt(struct infinity_aes_op *op) ++{ ++ int ret = 0; ++ ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, op->len); ++ memcpy(ALLOC_DMEM.aesdma_vir_addr, op->src, op->len); ++ ++ ret = infinity_aes_crypt_pub(op, ALLOC_DMEM.aesdma_phy_addr, ALLOC_DMEM.aesdma_phy_addr); ++ if (ret < 0) ++ { ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, op->len); ++ } ++ memcpy(op->dst, ALLOC_DMEM.aesdma_vir_addr, op->len); ++ ++ return ret; ++} ++ ++/* CRYPTO-API Functions */ ++static int infinity_setkey_cip(struct crypto_tfm *tfm, const u8 *key, unsigned int len) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ int ret; ++ ret=0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ if( gbSupportAES256 || len == AES_KEYSIZE_128) ++ { ++ op->keylen = len; ++ memcpy(op->key, key, len); ++ return 0; ++ } ++ ++ /* ++ * The requested key size is not supported by HW, do a fallback ++ */ ++ op->keylen = len; ++ op->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; ++ op->fallback.cip->base.crt_flags |= (tfm->crt_flags & CRYPTO_TFM_REQ_MASK); ++ ++ ret = crypto_cipher_setkey(op->fallback.cip, key, len); ++ if (ret) { ++ tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; ++ tfm->crt_flags |= (op->fallback.cip->base.crt_flags & CRYPTO_TFM_RES_MASK); ++ } ++ return ret; ++ ++} ++ ++static int infinity_setkey_blk(struct crypto_tfm *tfm, const u8 *key, unsigned int len) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ int ret; ++ ret=0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ if (gbSupportAES256 || len == AES_KEYSIZE_128) ++ { ++ op->keylen = len; ++ memcpy(op->key, key, len); ++ return 0; ++ } ++ ++ /* ++ * The requested key size is not supported by HW, do a fallback ++ */ ++ op->keylen = len; ++ op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; ++ op->fallback.blk->base.crt_flags |= (tfm->crt_flags & CRYPTO_TFM_REQ_MASK); ++ ++ ret = crypto_blkcipher_setkey(op->fallback.blk, key, len); ++ if (ret) { ++ tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; ++ tfm->crt_flags |= (op->fallback.blk->base.crt_flags & CRYPTO_TFM_RES_MASK); ++ } ++ return ret; ++ ++} ++ ++static int fallback_blk_dec(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ unsigned int ret = 0; ++ struct crypto_blkcipher *tfm; ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ ++ tfm = desc->tfm; ++ desc->tfm = op->fallback.blk; ++ ++ ret = crypto_blkcipher_decrypt_iv(desc, dst, src, nbytes); ++ ++ desc->tfm = tfm; ++ return ret; ++} ++static int fallback_blk_enc(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ unsigned int ret = 0; ++ struct crypto_blkcipher *tfm; ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ ++ tfm = desc->tfm; ++ desc->tfm = op->fallback.blk; ++ ++ ret = crypto_blkcipher_encrypt_iv(desc, dst, src, nbytes); ++ ++ desc->tfm = tfm; ++ return ret; ++} ++ ++ ++static void infinity_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ int ret=0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ crypto_cipher_encrypt_one(op->fallback.cip, out, in); ++ return; ++ } ++ ++ op->src = (void *) in; ++ op->dst = (void *) out; ++ op->mode = AES_MODE_ECB; ++ op->flags = 0; ++ op->len = AES_BLOCK_SIZE; ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ printk("[AESDMA][%s] infinity_aes_crypt return err:%d!\n", __FUNCTION__, ret); ++ } ++ ++} ++ ++ ++static void infinity_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ int ret=0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ crypto_cipher_decrypt_one(op->fallback.cip, out, in); ++ return; ++ } ++ ++ op->src = (void *) in; ++ op->dst = (void *) out; ++ op->mode = AES_MODE_ECB; ++ op->flags = 0; ++ op->len = AES_BLOCK_SIZE; ++ op->dir = AES_DIR_DECRYPT; ++ ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ printk("[AESDMA][%s] infinity_aes_crypt return err:%d!\n", __FUNCTION__, ret); ++ } ++ ++} ++ ++static int fallback_init_cip(struct crypto_tfm *tfm) ++{ ++ const char *name = crypto_tfm_alg_name(tfm); ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ op->fallback.cip = crypto_alloc_cipher(name, 0, ++ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); ++ ++ if (IS_ERR(op->fallback.cip)) { ++ return PTR_ERR(op->fallback.cip); ++ } ++ return 0; ++} ++static void fallback_exit_cip(struct crypto_tfm *tfm) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ ++ crypto_free_cipher(op->fallback.cip); ++ op->fallback.cip = NULL; ++} ++ ++static int fallback_init_blk(struct crypto_tfm *tfm) ++{ ++ const char *name = crypto_tfm_alg_name(tfm); ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ op->fallback.blk = crypto_alloc_blkcipher(name, 0, ++ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); ++ ++ if (IS_ERR(op->fallback.blk)) { ++ return PTR_ERR(op->fallback.blk); ++ } ++ return 0; ++} ++ ++static void fallback_exit_blk(struct crypto_tfm *tfm) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ ++ crypto_free_blkcipher(op->fallback.blk); ++ op->fallback.blk = NULL; ++} ++ ++static int infinity_cbc_decrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0, ret = 0; ++ U8 ivTemp[16]={0}; ++ ++ ++ memset(&walk, 0, sizeof(walk)); ++ ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ } ++ ++ mutex_lock(&_mtcrypto_lock); ++ ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++ op->iv = walk.iv; ++// AESDMA_DBG(" 1%s %d\n",__FUNCTION__,nbytes); ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CBC; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ memcpy(ivTemp, op->src+(op->len)-16, 16); ++ op->dir = AES_DIR_DECRYPT; ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ printk("[AESDMA][%s] infinity_aes_crypt return err:%d!\n", __FUNCTION__, ret); ++ err=ret; ++ goto finish; ++ } ++ ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA][%s] blkcipher_walk_done return err:%d!\n", __FUNCTION__, ret); ++ goto finish; ++ } ++ memcpy(walk.iv, ivTemp, 16); ++ } ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++static int infinity_cbc_encrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0, ret = 0; ++ memset(&walk, 0, sizeof(walk)); ++ ++ ++ ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ } ++ ++ mutex_lock(&_mtcrypto_lock); ++ ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++ op->iv = walk.iv; ++// AESDMA_DBG(" 1%s %d\n",__FUNCTION__,nbytes); ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CBC; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ printk("[AESDMA][%s] infinity_aes_crypt return err:%d!\n", __FUNCTION__, ret); ++ err=ret; ++ goto finish; ++ } ++ ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA][%s] blkcipher_walk_done return err:%d!\n", __FUNCTION__, ret); ++ goto finish; ++ } ++ ++ if (walk.nbytes > 0) ++ memcpy(walk.iv,(op->dst+(op->len)-16),16); ++ } ++ ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++static int infinity_ecb_decrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0 , ret = 0; ++ memset(&walk, 0, sizeof(walk)); ++ ++ ++ ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ } ++ ++ mutex_lock(&_mtcrypto_lock); ++ ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_ECB; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_DECRYPT; ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ printk("[AESDMA][%s] infinity_aes_crypt return err:%d!\n", __FUNCTION__, ret); ++ err=ret; ++ goto finish; ++ } ++ ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA][%s] blkcipher_walk_done return err:%d!\n", __FUNCTION__, ret); ++ goto finish; ++ } ++ } ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++static int infinity_ecb_encrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0, ret = 0; ++ ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ return fallback_blk_enc(desc, dst, src, nbytes); ++ } ++ ++ mutex_lock(&_mtcrypto_lock); ++ memset(&walk, 0, sizeof(walk)); ++ ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ while ((nbytes = walk.nbytes)) { ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_ECB; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ printk("[AESDMA][%s] infinity_aes_crypt return err:%d!\n", __FUNCTION__, ret); ++ err=ret; ++ goto finish; ++ } ++ ++ nbytes -= ret; ++ ret = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (ret != 0) ++ { ++ printk("[AESDMA][%s] blkcipher_walk_done return err:%d!\n", __FUNCTION__, ret); ++ err=ret; ++ goto finish; ++ } ++ } ++ ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++ ++} ++ ++/*ctr decrypt=encrypt*/ ++static int infinity_ctr_encrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err=0, ret=0; ++ int counter=0, n = 0; ++ ++ AESDMA_DBG("%s name %s nbytes(%d)\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name, nbytes); ++ ++ ++ if (!gbSupportAES256 && op->keylen != AES_KEYSIZE_128) { ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ } ++ ++ mutex_lock(&_mtcrypto_lock); ++ memset(&walk, 0, sizeof(walk)); ++ ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE); ++ ++ ++ while (walk.nbytes >= AES_BLOCK_SIZE) { ++ U8 *pdata; ++ op->iv = walk.iv; ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CTR; ++ op->len = walk.nbytes - (walk.nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_ENCRYPT; ++ ++ pdata = ( U8 *)walk.src.virt.addr; ++ ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ err=ret; ++ goto finish; ++ } ++ nbytes = walk.nbytes - ret; //the remain data ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ counter = op->len >> 4; ++ for (n = 0; n < counter; n++) ++ { ++ crypto_inc((U8*)op->iv, AES_BLOCK_SIZE); ++ } ++ } ++ ++ ++ if (walk.nbytes) { ++ op->iv = walk.iv; ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CTR; ++ op->len = walk.nbytes; ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op); ++ if (ret < 0) ++ { ++ err=ret; ++ goto finish; ++ } ++ nbytes = walk.nbytes - ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ crypto_inc((U8*)op->iv, AES_BLOCK_SIZE); ++ } ++ ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++u32 infinity_random(void) ++{ ++ return HAL_RNG_Read(); ++} ++ ++#if 0 ++static struct crypto_alg infinity_tdes_alg = { ++ .cra_name = "tdes", ++ .cra_driver_name = "tdes-generic", ++ .cra_priority = 400, ++ .cra_alignmask = 15, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_cip, ++ .cra_exit = fallback_exit_cip, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = infinity_setkey_cip, ++ .cia_encrypt = infinity_encrypt, ++ .cia_decrypt = infinity_decrypt ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_des_alg = { ++ .cra_name = "des", ++ .cra_driver_name = "infinity-des", ++ .cra_priority = 50, ++ .cra_alignmask = 15, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_cip, ++ .cra_exit = fallback_exit_cip, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = infinity_setkey_cip, ++ .cia_encrypt = infinity_encrypt, ++ .cia_decrypt = infinity_decrypt ++ } ++ } ++}; ++#endif ++ ++static struct crypto_alg infinity_alg = { ++ .cra_name = "aes", ++ .cra_driver_name = "infinity-aes", ++ .cra_priority = 300, ++ .cra_alignmask = 15, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_cip, ++ .cra_exit = fallback_exit_cip, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = infinity_setkey_cip, ++ .cia_encrypt = infinity_encrypt, ++ .cia_decrypt = infinity_decrypt ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_cbc_alg = { ++ .cra_name = "cbc(aes)", ++ .cra_driver_name = "cbc-aes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_cbc_encrypt, ++ .decrypt = infinity_cbc_decrypt, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_ecb_alg = { ++ .cra_name = "ecb(aes)", ++ .cra_driver_name = "ecb-aes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ecb_encrypt, ++ .decrypt = infinity_ecb_decrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_ctr_alg = { ++ .cra_name = "ctr(aes)", ++ .cra_driver_name = "ctr-aes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = 1, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ctr_encrypt, ++ .decrypt = infinity_ctr_encrypt, ++ } ++ } ++}; ++ ++#if 0 ++static struct crypto_alg infinity_des_cbc_alg = { ++ .cra_name = "cbc(des)12", ++ .cra_driver_name = "cbc-des-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_cbc_encrypt, ++ .decrypt = infinity_cbc_decrypt, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_des_ecb_alg = { ++ .cra_name = "ecb(des)12", ++ .cra_driver_name = "ecb-des-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ecb_encrypt, ++ .decrypt = infinity_ecb_decrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_des_ctr_alg = { ++ .cra_name = "ctr(des)12", ++ .cra_driver_name = "ctr-des-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ctr_encrypt, ++ .decrypt = infinity_ctr_encrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_tdes_cbc_alg = { ++ .cra_name = "cbc(tdes)", ++ .cra_driver_name = "cbc(tdes-generic)", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_cbc_encrypt, ++ .decrypt = infinity_cbc_decrypt, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_tdes_ecb_alg = { ++ .cra_name = "ecb(tdes)", ++ .cra_driver_name = "ecb-tdes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ecb_encrypt, ++ .decrypt = infinity_ecb_decrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_tdes_ctr_alg = { ++ .cra_name = "ctr(tdes)", ++ .cra_driver_name = "ctr-tdes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ctr_encrypt, ++ .decrypt = infinity_ctr_encrypt, ++ } ++ } ++}; ++#endif ++ ++#ifdef CONFIG_PM_SLEEP ++static int infinity_aes_resume(struct platform_device *pdev) ++{ ++ enableClock(); ++ return 0; ++} ++ ++static int infinity_aes_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ disableClock(); ++ return 0; ++} ++#endif ++ ++static int infinity_aes_remove(struct platform_device *pdev) ++{ ++ crypto_unregister_alg(&infinity_alg); ++ crypto_unregister_alg(&infinity_ecb_alg); ++ crypto_unregister_alg(&infinity_cbc_alg); ++ disableClock(); ++ infinity_sha_destroy(); ++ misc_deregister(&rsadev); ++ _ms_aes_mem_free(); ++ return 0; ++} ++ ++static int infinity_aes_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++#ifdef AESDMA_ISR ++ int irq; ++#endif ++ ++ mutex_init(&_mtcrypto_lock); ++ psg_mdrv_aesdma = pdev; ++ enableClock(); ++ allocMem(4096); ++ ++#if 0 ++ ret = crypto_register_alg(&infinity_des_alg); ++ if (ret) ++ goto eiomap; ++ ret = crypto_register_alg(&infinity_tdes_alg); ++ if (ret) ++ goto eiomap; ++#endif ++ ret = crypto_register_alg(&infinity_alg); ++ if (ret) ++ goto eiomap; ++ ++ ret = crypto_register_alg(&infinity_ecb_alg); ++ if (ret) ++ goto eecb; ++ ++ ret = crypto_register_alg(&infinity_cbc_alg); ++ if (ret) ++ goto ecbc; ++ ++ ret = crypto_register_alg(&infinity_ctr_alg); ++ if (ret) ++ goto ectr; ++#if 0 ++ ret = crypto_register_alg(&infinity_des_ecb_alg); ++ if (ret) ++ goto edesecb; ++ ++ ret = crypto_register_alg(&infinity_des_cbc_alg); ++ if (ret) ++ goto edescbc; ++ ++ ret = crypto_register_alg(&infinity_des_ctr_alg); ++ if (ret) ++ goto edesctr; ++ ++ ret = crypto_register_alg(&infinity_tdes_ecb_alg); ++ if (ret) ++ goto etdesecb; ++ ++ ret = crypto_register_alg(&infinity_tdes_cbc_alg); ++ if (ret) ++ goto etdescbc; ++ ++ ret = crypto_register_alg(&infinity_tdes_ctr_alg); ++ if (ret) ++ goto etdesctr; ++#endif ++ ++ infinity_sha_create(); ++ misc_register(&rsadev); ++ dev_dbg(&pdev->dev, "SSTAR AES engine enabled.\n"); ++#ifdef AESDMA_ISR ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (request_irq(irq, aes_dma_interrupt, 0, "aes interrupt", NULL) == 0) ++ { ++ init_completion(&_mdmadone); ++ AESDMA_DBG("sstar AES interrupt registered\n"); ++ _isr_requested = 1; ++ } ++ else ++ { ++ pr_err("sstar AES interrupt failed\n"); ++ _isr_requested = 0; ++ } ++#endif ++ ++#if defined(CONFIG_SS_RNG) ++ { ++ extern int sstar_rng_probe(struct platform_device *pdev); ++ sstar_rng_probe(pdev); ++ } ++#endif ++ return 0; ++ ++ectr: ++ crypto_unregister_alg(&infinity_ctr_alg); ++ecbc: ++ crypto_unregister_alg(&infinity_cbc_alg); ++eecb: ++ crypto_unregister_alg(&infinity_ecb_alg); ++ ++#if 0 ++ edesecb: ++ crypto_unregister_alg(&infinity_des_ecb_alg); ++ edescbc: ++ crypto_unregister_alg(&infinity_des_cbc_alg); ++ edesctr: ++ crypto_unregister_alg(&infinity_des_ctr_alg); ++ etdesecb: ++ printk("!!!infinity_tdes_ecb_alg initialization failed.\n"); ++ crypto_unregister_alg(&infinity_tdes_ecb_alg); ++ etdescbc: ++ printk("!!!infinity_tdes_cbc_alg initialization failed.\n"); ++ crypto_unregister_alg(&infinity_tdes_cbc_alg); ++ etdesctr: ++ printk("!!!infinity_tdes_ctr_alg initialization failed.\n"); ++ crypto_unregister_alg(&infinity_tdes_ctr_alg); ++#endif ++ eiomap: ++ crypto_unregister_alg(&infinity_alg); ++ ++ pr_err("SSTAR AES initialization failed.\n"); ++ return ret; ++} ++ ++static const struct of_device_id infinity_aes_dt_ids[] = ++{ ++ { .compatible = "sstar,infinity-aes" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, infinity_aes_dt_ids); ++ ++static struct platform_driver infinity_aes_driver = { ++ .probe = infinity_aes_probe, ++ .remove = infinity_aes_remove, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = infinity_aes_suspend, ++ .resume = infinity_aes_resume, ++#endif ++ .driver = { ++ .name = "infinity_aes", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(infinity_aes_dt_ids), ++ }, ++}; ++ ++ ++module_platform_driver(infinity_aes_driver); ++ ++ ++MODULE_DESCRIPTION("iNfinity AES hw acceleration support."); ++ ++// // MODULE_ALIAS_CRYPTO("ctr(des)"); ++// MODULE_ALIAS_CRYPTO("tdes"); ++// MODULE_ALIAS_CRYPTO("tdes-generic"); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("SSTAR"); +diff --git a/drivers/sstar/crypto/mdrv_aes.h b/drivers/sstar/crypto/mdrv_aes.h +new file mode 100755 +index 000000000000..c0668c03a2b0 +--- /dev/null ++++ b/drivers/sstar/crypto/mdrv_aes.h +@@ -0,0 +1,72 @@ ++/* ++* mdrv_aes.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MSTAR_AES_H_ ++#define _MSTAR_AES_H_ ++ ++/* driver logic flags */ ++#define AES_MODE_ECB 0 ++#define AES_MODE_CBC 1 ++#define AES_MODE_CTR 2 ++#define AES_DIR_DECRYPT 0 ++#define AES_DIR_ENCRYPT 1 ++#define AESDMA_ALLOC_MEMSIZE (16) //1MB 1024*1024 ++#define AESDMA_ALLOC_MEMSIZE_TEMP (16) //64byte for SHA ++ ++struct infinity_aes_op ++{ ++ void *src; ++ void *dst;//16 ++ u32 mode; ++ u32 dir; ++ u32 flags; ++ u32 keylen;//24 ++ int len; ++ u8 *iv;//8 ++ u8 key[AES_KEYSIZE_256]; ++ union { ++ struct crypto_blkcipher *blk; ++ struct crypto_cipher *cip; ++ } fallback; ++ u16 engine; ++ ++}; ++ ++ ++struct aesdma_alloc_dmem ++{ ++ dma_addr_t aesdma_phy_addr ; ++ dma_addr_t aesdma_phy_SHABuf_addr; ++ const char* DMEM_AES_ENG_INPUT; ++ const char* DMEM_AES_ENG_SHABUF; ++ u8 *aesdma_vir_addr; ++ u8 *aesdma_vir_SHABuf_addr; ++}; ++ ++extern struct platform_device *psg_mdrv_aesdma; ++ ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++int infinity_aes_crypt_pub(struct infinity_aes_op *op, u32 in_addr, u32 out_addr); ++u32 infinity_random(void); ++ ++#endif +diff --git a/drivers/sstar/crypto/mdrv_cipher.c b/drivers/sstar/crypto/mdrv_cipher.c +new file mode 100755 +index 000000000000..5316511f12f0 +--- /dev/null ++++ b/drivers/sstar/crypto/mdrv_cipher.c +@@ -0,0 +1,402 @@ ++/* ++* mdrv_cipher.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_aes.h" ++#include "mdrv_rsa.h" ++#include "mdrv_cipher.h" ++ ++/* ++ * Options ++ */ ++#define CIPHER_DEBUG (1) ++#if (CIPHER_DEBUG == 1) ++#define CIPHER_DBG(fmt, arg...) printk(KERN_ALERT fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define CIPHER_DBG(fmt, arg...) ++#endif ++ ++/* ++ * Data types ++ */ ++typedef enum ++{ ++ E_AES_DIR_DECRYPT = 0, ++ E_AES_DIR_ENCRYPT, ++} AES_DIR; ++ ++/* ++ * External ++ */ ++extern int infinity_sha_init(u8 sha256_mode); ++extern int infinity_sha_update(u32 *in, u32 len, u32 *state, u32 count, u8 once); ++extern int infinity_sha_final(void); ++ ++/* ++ * Local ++ */ ++static struct mutex _mtcipher_lock; ++static u8 _u8AesRefcnt = 0; ++ ++/********************************************************/ ++/* */ ++/* AES functions */ ++/* */ ++/********************************************************/ ++int cipher_aes_init(void) ++{ ++ if (_u8AesRefcnt == 0) ++ { ++ mutex_init(&_mtcipher_lock); ++ _u8AesRefcnt++; ++ } ++ return 0; ++} ++ ++EXPORT_SYMBOL(cipher_aes_init); ++ ++int cipher_aes_uninit(void) ++{ ++ if (_u8AesRefcnt) ++ { ++ _u8AesRefcnt--; ++ if (_u8AesRefcnt == 0) ++ { ++ mutex_destroy(&_mtcipher_lock); ++ } ++ } ++ return 0; ++} ++ ++EXPORT_SYMBOL(cipher_aes_uninit); ++ ++static int cipher_aes_crypto(MDRV_AES_HANDLE *handle, AES_DIR dir) ++{ ++ int ret = 0; ++ u32 in, out; ++ struct infinity_aes_op op; ++ ++ in = (u32)__pa(handle->in); ++ out = (u32)__pa(handle->out); ++ op.len = handle->len; ++ op.dir = (dir == E_AES_DIR_DECRYPT) ? AES_DIR_DECRYPT : AES_DIR_ENCRYPT; ++ op.iv = handle->iv; ++ memcpy(op.key, handle->key, handle->keylen); ++ op.keylen = handle->keylen; ++ switch(handle->mode) { ++ case E_AES_ALGO_ECB: ++ op.mode = AES_MODE_ECB; ++ break; ++ case E_AES_ALGO_CBC: ++ op.mode = AES_MODE_CBC; ++ break; ++ case E_AES_ALGO_CTR: ++ op.mode = AES_MODE_CTR; ++ break; ++ } ++ Chip_Flush_Cache_Range((unsigned long)handle->in, handle->len); ++ Chip_Inv_Cache_Range((unsigned long)handle->out, handle->len); ++ ret = infinity_aes_crypt_pub(&op, in, out); ++ if (ret != handle->len) ++ { ++ CIPHER_DBG("aes crypto failed %d\n", ret); ++ } ++ return ret; ++} ++ ++/* [ecb] no iv */ ++static int cipher_ecb_crypto(MDRV_AES_HANDLE *handle, AES_DIR dir) ++{ ++ int ret = 0; ++ u32 left = handle->len; ++ ++ while (left) ++ { ++ handle->len = left - (left % AES_BLOCK_SIZE); ++ ret = cipher_aes_crypto(handle, dir); ++ if (ret < 0) ++ { ++ CIPHER_DBG("[AES] ecb crypto err %d\n", ret); ++ return ret; ++ } ++ left -= ret; ++ } ++ return 0; ++} ++ ++/* [cbc] encrypt */ ++static int cipher_cbc_encrypt(MDRV_AES_HANDLE *handle) ++{ ++ int ret = 0; ++ u32 left = handle->len; ++ ++ while (left) ++ { ++ handle->len = left - (left % AES_BLOCK_SIZE); ++ ret = cipher_aes_crypto(handle, E_AES_DIR_ENCRYPT); ++ if (ret < 0) ++ { ++ CIPHER_DBG("[AES] cbc encrypt err %d\n", ret); ++ return ret; ++ } ++ else if (ret > 0) { ++ memcpy(handle->iv, (handle->out+(handle->len)-16), 16); ++ left -= ret; ++ } ++ } ++ return 0; ++} ++ ++/* [cbc] decrypt */ ++static int cipher_cbc_decrypt(MDRV_AES_HANDLE *handle) ++{ ++ int ret = 0; ++ u32 left = handle->len; ++ u8 temp_iv[AES_BLOCK_SIZE]; ++ ++ while (left) ++ { ++ handle->len = left - (left % AES_BLOCK_SIZE); ++ memcpy(temp_iv, handle->in+(handle->len)-16, 16); ++ ret = cipher_aes_crypto(handle, E_AES_DIR_DECRYPT); ++ if (ret < 0) ++ { ++ CIPHER_DBG("[AES] cbc decrypt err %d\n", ret); ++ return ret; ++ } ++ else if (ret > 0) ++ { ++ memcpy(handle->iv, temp_iv, 16); ++ left -= ret; ++ } ++ } ++ return 0; ++} ++ ++/* [ctr] decrypt = encrypt */ ++static int cipher_ctr_crypto(MDRV_AES_HANDLE *handle) ++{ ++ int ret = 0; ++ int counter = 0, n = 0; ++ u32 left = handle->len; ++ u32 temp_iv[AES_KEYSIZE_128 >> 2]; ++ ++ while (left) ++ { ++ handle->len = left - (left % AES_BLOCK_SIZE); ++ ret = cipher_aes_crypto(handle, E_AES_DIR_ENCRYPT); ++ if (ret < 0) ++ { ++ CIPHER_DBG("[AES] ctr crypto err %d\n", ret); ++ return ret; ++ } ++ else if (ret > 0) ++ { ++ memcpy(temp_iv, handle->iv, AES_BLOCK_SIZE); ++ for (n = 0; n <= 3; n++) ++ { ++ temp_iv[n] = be32_to_cpu(temp_iv[n]); ++ } ++ counter = handle->len >> 4; ++ // iv=iv+1; ++ while(counter) ++ { ++ temp_iv[3] = temp_iv[3] + 1; ++ if (temp_iv[3] == 0x0) ++ { ++ temp_iv[2] = temp_iv[2] + 1; ++ if (temp_iv[2] == 0x0) ++ { ++ temp_iv[1] = temp_iv[1] + 1; ++ if (temp_iv[1] == 0x0) ++ { ++ temp_iv[0] = temp_iv[0] + 1; ++ if (temp_iv[0] == 0x0) ++ { ++ CIPHER_DBG("IV counter overflow!\n"); ++ } ++ } ++ } ++ } ++ counter--; ++ } ++ for (n = 0; n <= 3; n++) ++ { ++ temp_iv[n] = cpu_to_be32(temp_iv[n]); ++ } ++ memcpy(handle->iv, temp_iv, AES_BLOCK_SIZE); ++ } ++ left -= ret; ++ } ++ return 0; ++} ++ ++int cipher_aes_encrypt(MDRV_AES_HANDLE *handle) ++{ ++ int ret = 0; ++ ++ mutex_lock(&_mtcipher_lock); ++ switch(handle->mode) { ++ case E_AES_ALGO_ECB: ++ ret = cipher_ecb_crypto(handle, AES_DIR_ENCRYPT); ++ break; ++ case E_AES_ALGO_CBC: ++ ret = cipher_cbc_encrypt(handle); ++ break; ++ case E_AES_ALGO_CTR: ++ ret = cipher_ctr_crypto(handle); ++ break; ++ } ++ mutex_unlock(&_mtcipher_lock); ++ return ret; ++} ++ ++EXPORT_SYMBOL(cipher_aes_encrypt); ++ ++int cipher_aes_decrypt(MDRV_AES_HANDLE *handle) ++{ ++ int ret = 0; ++ ++ mutex_lock(&_mtcipher_lock); ++ switch(handle->mode) { ++ case E_AES_ALGO_ECB: ++ ret = cipher_ecb_crypto(handle, AES_DIR_DECRYPT); ++ break; ++ case E_AES_ALGO_CBC: ++ ret = cipher_cbc_decrypt(handle); ++ break; ++ case E_AES_ALGO_CTR: ++ ret = cipher_ctr_crypto(handle); ++ break; ++ } ++ mutex_unlock(&_mtcipher_lock); ++ return ret; ++} ++ ++EXPORT_SYMBOL(cipher_aes_decrypt); ++ ++/********************************************************/ ++/* */ ++/* RSA functions */ ++/* */ ++/********************************************************/ ++int cipher_rsa_crypto(MDRV_RSA_HANDLE *handle) ++{ ++ struct rsa_config op; ++ ++ if (!handle->exp || !handle->modulus || !handle->in || !handle->out) ++ { ++ CIPHER_DBG("[RSA] invalid input\n"); ++ return -1; ++ } ++ if ((handle->mod_len != 0x10) && (handle->mod_len != 0x20) && (handle->mod_len != 0x40)) { ++ CIPHER_DBG("[RSA] KenNLen %d unsupported\n", handle->mod_len); ++ return -1; ++ } ++ ++ op.pu32RSA_KeyE = handle->exp; ++ op.pu32RSA_KeyN = handle->modulus; ++ op.u32RSA_KeyELen = handle->exp_len; ++ op.u32RSA_KeyNLen = handle->mod_len; ++ op.pu32RSA_Output = handle->out; ++ op.pu32RSA_Sig = handle->in; ++ op.u32RSA_SigLen = handle->len; ++ return rsa_crypto(&op); ++} ++ ++EXPORT_SYMBOL(cipher_rsa_crypto); ++ ++/********************************************************/ ++/* */ ++/* SHA functions */ ++/* */ ++/********************************************************/ ++int cipher_sha_init(MDRV_SHA_HANDLE *handle) ++{ ++ u8 sha256 = 1; ++ ++ if ((handle->mode < E_SHA_1) && (handle->mode >= E_SHA_MODE_NUM)) ++ { ++ CIPHER_DBG("[SHA] Unsupported mode\n"); ++ return -1; ++ } ++ ++ handle->ctx.count = 0; ++ if ((handle->mode == E_SHA_1) || (handle->mode == E_SHA_1_ONCE)) ++ { ++ sha256 = 0; ++ } ++ return infinity_sha_init(sha256); ++} ++ ++EXPORT_SYMBOL(cipher_sha_init); ++ ++int cipher_sha_update(MDRV_SHA_HANDLE *handle) ++{ ++ int ret; ++ u8 once = 0; // do SHA for whole message once ++ ++ if ((handle->mode == E_SHA_1_ONCE) || (handle->mode == E_SHA_256_ONCE)) ++ { ++ once = 1; ++ } ++ ret = infinity_sha_update((u32 *)handle->u32DataPhy, handle->u32DataLen, handle->ctx.state, handle->ctx.count, once); ++ if (ret == 0) ++ { ++ handle->ctx.count += handle->u32DataLen; ++ } ++ ++ return ret; ++} ++ ++EXPORT_SYMBOL(cipher_sha_update); ++ ++int cipher_sha_final(MDRV_SHA_HANDLE *handle) ++{ ++ u8 i = 0, count = 32; ++ u8 *hash = (u8 *)handle->u32ShaVal; ++ u8 *state = (u8 *)handle->ctx.state; ++ ++ if ((handle->mode == E_SHA_1) || (handle->mode == E_SHA_1_ONCE)) ++ { ++ count = 20; ++ } ++ for(i = 0; i < count; i++) ++ { ++ hash[i] = state[31 - i]; ++ } ++ return infinity_sha_final(); ++} ++ ++EXPORT_SYMBOL(cipher_sha_final); ++ ++u32 cipher_random_num(void) ++{ ++ return infinity_random(); ++} ++ ++EXPORT_SYMBOL(cipher_random_num); +diff --git a/drivers/sstar/crypto/mdrv_rsa.c b/drivers/sstar/crypto/mdrv_rsa.c +new file mode 100755 +index 000000000000..62cb67772e60 +--- /dev/null ++++ b/drivers/sstar/crypto/mdrv_rsa.c +@@ -0,0 +1,392 @@ ++/* ++* mdrv_rsa.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include <../drivers/sstar/include/ms_msys.h> ++#include <../drivers/sstar/include/ms_platform.h> ++#include <../drivers/sstar/include/mdrv_hvsp_io_st.h> ++#include <../drivers/sstar/include/mdrv_hvsp_io.h> ++#include ++#include "mdrv_rsa.h" ++#include "halAESDMA.h" ++#include ++#include ++#include ++#include ++ ++#define RSA_DEBUG_FLAG (0) ++#if (RSA_DEBUG_FLAG == 1) ++#define RSA_DBG(fmt, arg...) printk(fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define RSA_DBG(fmt, arg...) ++#endif ++ ++#define DRIVER_NAME "rsa" ++//static unsigned int test_ioctl_major = 0; ++//static unsigned int num_of_dev = 1; ++//static struct cdev test_ioctl_cdev; ++//static int ioctl_num = 0; ++ ++ ++//static const char* DMEM_RSA_ENG_INPUT="RSA_ENG_IN"; ++ ++struct rsaConfig{ ++ U32 *pu32RSA_Sig; ++ U32 *pu32RSA_KeyN; ++ U32 *pu32RSA_KeyE; ++ U32 *pu32RSA_Output; ++ U8 u8RSA_KeyNLen; ++ U8 u8RSA_SigLen; ++ U8 u8RSA_KeyELen; ++ U8 u8RSAPublicKey; ++}; ++ ++int rsa_crypto(struct rsa_config *op) ++{ ++ int out_size = 32, i = 0; ++ unsigned long timeout; ++ ++ HAL_RSA_Reset(); ++ msleep(1); ++ HAL_RSA_SetKeyLength((op->u32RSA_KeyNLen-1) & 0x3F); ++ HAL_RSA_SetKeyType(FALSE, FALSE); ++ ++ HAL_RSA_Ind32Ctrl(1); //write ++ HAL_RSA_LoadSignInverse((U32 *)op->pu32RSA_Sig, (U8)op->u32RSA_SigLen); ++ HAL_RSA_LoadKeyNInverse((U32 *)op->pu32RSA_KeyN, (U8)op->u32RSA_KeyNLen); ++ HAL_RSA_LoadKeyEInverse((U32 *)op->pu32RSA_KeyE, (U8)op->u32RSA_KeyELen); ++ ++ HAL_RSA_ExponetialStart(); ++ ++#if (RSA_DEBUG_FLAG) ++ RSA_DBG("IN:\n"); ++ for(i = 0; i < op->u32RSA_SigLen; i+=4) ++ { ++ RSA_DBG(" x%08X x%08X x%08X x%08X\n", *(op->pu32RSA_Sig+i), *(op->pu32RSA_Sig+i+1),*(op->pu32RSA_Sig+i+2), *(op->pu32RSA_Sig+i+3)); ++ } ++ RSA_DBG("\n\n"); ++#endif ++ ++ timeout = jiffies + msecs_to_jiffies(5000); ++ while((HAL_RSA_GetStatus() & RSA_STATUS_RSA_DONE) != RSA_STATUS_RSA_DONE) ++ { ++ if (time_after_eq(jiffies, timeout)) ++ { ++ printk("rsa timeout!!!\n"); ++ goto err; ++ } ++ ++ } ++ ++ if(op->u32RSA_KeyNLen == 0x40) ++ { ++ out_size = 64; ++ } ++ ++ HAL_RSA_Ind32Ctrl(0); //read ++ for(i = 0; i < out_size; i++) ++ { ++ HAL_RSA_SetFileOutAddr(i); ++ HAL_RSA_FileOutStart(); ++ *(op->pu32RSA_Output + (out_size - 1) - i) = HAL_RSA_FileOut(); ++ } ++ ++#if (RSA_DEBUG_FLAG) ++ RSA_DBG("OUT:\n"); ++ for(i = 0; i < out_size; i+=4) ++ { ++ RSA_DBG(" x%08X x%08X x%08X x%08X\n", *(op->pu32RSA_Output+i), *(op->pu32RSA_Output+i+1),*(op->pu32RSA_Output+i+2), *(op->pu32RSA_Output+i+3)); ++ } ++ RSA_DBG("\n\n"); ++#endif ++ ++ HAL_RSA_FileOutEnd(); ++err: ++ HAL_RSA_ClearInt(); ++ HAL_RSA_Reset(); ++ ++ return 0; ++} ++ ++static long rsa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ struct rsaConfig *ioctl_data = filp->private_data; ++ int retval = 0; ++ struct rsa_config data; ++ int nOutSize = 0; ++ int i = 0; ++ bool bRSAHwKey = FALSE; ++ unsigned long timeout; ++ ++// unsigned char* val; ++ memset(&data, 0, sizeof(data)); ++ ++ switch (cmd) { ++ ++ case MDrv_RSA_Reset: ++ HAL_RSA_Reset(); ++ goto done; ++ break; ++ ++ case MDrv_RSA_Setmode: ++ memset(&data, 0, sizeof(data)); ++ if (copy_from_user(&data, (int __user *)arg, sizeof(data))) { ++ retval = -EFAULT; ++ goto done; ++ } ++// write_lock(&ioctl_data->lock); ++ ioctl_data->u8RSA_KeyNLen = data.u32RSA_KeyNLen; ++// write_unlock(&ioctl_data->lock); ++ if (ioctl_data->u8RSA_KeyNLen != 0x10 && ioctl_data->u8RSA_KeyNLen != 0x20 && ioctl_data->u8RSA_KeyNLen != 0x40){ ++ retval = -EFAULT; ++ printk("[RSAERR] Mode error\n"); ++ printk("[RSAERR] KenNLen != 0x10 or 0x20 or 0x40\n"); ++ goto done; ++ } ++ ++ HAL_RSA_SetKeyLength(((ioctl_data->u8RSA_KeyNLen)-1) & 0x3F); ++ HAL_RSA_SetKeyType(bRSAHwKey, FALSE); ++ break; ++ ++ case MDrv_RSA_Calculate: ++ memset(&data, 0, sizeof(data)); ++ if (copy_from_user(&data, (int __user *)arg, sizeof(data))) { ++ retval = -EFAULT; ++ goto done; ++ } ++// write_lock(&ioctl_data->lock); ++ ioctl_data->pu32RSA_Sig = (U32 *)data.pu32RSA_Sig; ++ ioctl_data->pu32RSA_Output = (U32 *)data.pu32RSA_Output; ++ ioctl_data->pu32RSA_KeyN = (U32 *)data.pu32RSA_KeyN; ++ ioctl_data->pu32RSA_KeyE = (U32 *)data.pu32RSA_KeyE; ++ ioctl_data->u8RSA_KeyELen = (U8)(data.u32RSA_KeyELen & 0xFF); ++ ioctl_data->u8RSA_KeyNLen = (U8)(data.u32RSA_KeyNLen & 0xFF); ++ ioctl_data->u8RSA_SigLen = (U8)(data.u32RSA_SigLen & 0xFF); ++// write_unlock(&ioctl_data->lock); ++ ++ if ((ioctl_data->u8RSA_SigLen < 1) || (ioctl_data->u8RSA_SigLen > 0xFF)) { ++ retval = -EFAULT; ++ printk("[RSAERR] SigLen is invalid\n"); ++ goto done; ++ } ++ ++ if ((ioctl_data->u8RSA_KeyELen < 1) || (ioctl_data->u8RSA_KeyELen > 0xFF)) ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] KeyELen is invalid\n"); ++ goto done; ++ } ++ ++ if ((ioctl_data->u8RSA_KeyNLen < 1) || (ioctl_data->u8RSA_KeyNLen > 0xFF)) ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] KeyNLen is invalid\n"); ++ goto done; ++ } ++ ++ if (!((ioctl_data->pu32RSA_Sig) && (ioctl_data->pu32RSA_Output) && (ioctl_data->pu32RSA_KeyN))) { ++ retval = -EFAULT; ++ printk("[RSAERR] null pointer = 0 \n"); ++ goto done; ++ } ++ ++ HAL_RSA_Ind32Ctrl(1);//1:write ++ ++ if((!bRSAHwKey) && (ioctl_data->pu32RSA_Sig)) ++ { ++ HAL_RSA_LoadSignInverse(ioctl_data->pu32RSA_Sig, ioctl_data->u8RSA_SigLen); ++ } ++ else ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] RSA_Sig = NULL\n"); ++ goto done; ++ } ++ ++ if((!bRSAHwKey) && (ioctl_data->pu32RSA_KeyN)) ++ { ++ HAL_RSA_LoadKeyNInverse(ioctl_data->pu32RSA_KeyN, ioctl_data->u8RSA_KeyNLen); ++ } ++ else ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] RSA_KeyN = NULL\n"); ++ goto done; ++ } ++ ++ if((!bRSAHwKey) && (ioctl_data->pu32RSA_KeyE)) ++ { ++ HAL_RSA_LoadKeyEInverse(ioctl_data->pu32RSA_KeyE, ioctl_data->u8RSA_KeyELen); //65535 ++ } ++ else ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] RSA_KeyE = NULL\n"); ++ goto done; ++ } ++ ++ HAL_RSA_ExponetialStart(); ++ ++ timeout = jiffies + msecs_to_jiffies(1000); ++ while((HAL_RSA_GetStatus() & RSA_STATUS_RSA_DONE) != RSA_STATUS_RSA_DONE) ++ { ++ if (time_after_eq(jiffies, timeout)) ++ { ++ printk("rsa timeout!!!\n"); ++ break; ++ } ++ } ++ ++ if((bRSAHwKey) || (ioctl_data->u8RSA_KeyNLen == 64)) ++ { ++ nOutSize = 64; ++ } ++ else ++ { ++ nOutSize = 32; ++ } ++ ++ HAL_RSA_Ind32Ctrl(0); ++ ++ for( i = 0; ipu32RSA_Output + (nOutSize-1) - i) = HAL_RSA_FileOut(); ++ } ++ ++ HAL_RSA_FileOutEnd(); ++ HAL_RSA_Reset(); ++ ++// read_lock(&ioctl_data->lock); ++ ++ data.pu32RSA_Output = (unsigned int*)ioctl_data->pu32RSA_Output; ++ ++// read_unlock(&ioctl_data->lock); ++ ++ if (copy_to_user((int __user *)arg, &data, sizeof(data)) ) { ++ retval = -EFAULT; ++ goto done; ++ } ++ break; ++ ++ default: ++ retval = -ENOTTY; ++ } ++ ++ done: ++ ++ return retval; ++} ++ ++//ssize_t test_ioctl_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos) ++//{ ++// struct rsaConfig *ioctl_data = filp->private_data; ++// unsigned char val; ++// int retval; ++// int i = 0; ++ ++// read_lock(&ioctl_data->lock); ++// val = ioctl_data->val; ++// read_unlock(&ioctl_data->lock); ++ ++// for (;i < count ;i++) { ++// if (copy_to_user(&buf[i], &val, 1)) { ++// retval = -EFAULT; ++// goto out; ++// } ++// } ++ ++// retval = count; ++ ++//out: ++// return retval; ++//} ++ ++static int rsa_ioctl_close(struct inode *inode, struct file *filp) ++{ ++// printk(KERN_ALERT "%s call.\n", __func__); ++ if (filp->private_data) { ++ kfree(filp->private_data); ++ filp->private_data = NULL; ++ } ++ ++ return 0; ++} ++ ++static int rsa_ioctl_open(struct inode *inode, struct file *filp) ++{ ++ ++ struct rsaConfig *ioctl_data; ++// printk(KERN_ALERT "%s call.\n", __func__); ++ ++ ioctl_data = kmalloc(sizeof(struct rsaConfig), GFP_KERNEL); ++ if (ioctl_data == NULL) ++ return -ENOMEM; ++ ++// rwlock_init(&ioctl_data->lock); ++ ++ ++ filp->private_data = ioctl_data; ++ ++ return 0; ++} ++ ++struct file_operations rsa_fops = { ++ .owner = THIS_MODULE, ++ .open = rsa_ioctl_open, ++ .release = rsa_ioctl_close, ++ .unlocked_ioctl = rsa_ioctl, ++}; ++ ++struct miscdevice rsadev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "rsa", ++ .fops = &rsa_fops, ++ .mode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH, ++}; ++ ++//#define PFX "rsadev: " ++ ++//static int __init rsa_ioctl_init(void) ++//{ ++ ++//int rc; ++// rc = misc_register(&rsadev); ++// if (unlikely(rc)) { ++// pr_err(PFX "registration of /dev/crypto failed\n"); ++// return rc; ++// } ++ ++// return 0; ++//} ++ ++//static void __exit rsa_ioctl_exit(void) ++//{ ++// misc_deregister(&rsadev); ++//} ++ ++//module_init(rsa_ioctl_init); ++//module_exit(rsa_ioctl_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("This is test_ioctl module."); +diff --git a/drivers/sstar/crypto/mdrv_rsa.h b/drivers/sstar/crypto/mdrv_rsa.h +new file mode 100755 +index 000000000000..2e5374436b4d +--- /dev/null ++++ b/drivers/sstar/crypto/mdrv_rsa.h +@@ -0,0 +1,47 @@ ++/* ++* mdrv_rsa.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef _IOCTL_TEST_H ++#define _IOCTL_TEST_H ++ ++#include ++ ++struct rsa_config { ++unsigned int *pu32RSA_Sig; ++unsigned int *pu32RSA_KeyN; ++unsigned int *pu32RSA_KeyE; ++unsigned int *pu32RSA_Output; ++unsigned int u32RSA_KeyNLen; ++unsigned int u32RSA_KeyELen; ++unsigned int u32RSA_SigLen; ++}; ++ ++ ++ ++ ++/* ocumentation/ioctl/ioctl-number.txt */ ++#define IOC_MAGIC '\x66' ++ ++#define MDrv_RSA_Reset _IO(IOC_MAGIC, 0x92) ++#define MDrv_RSA_Setmode _IO(IOC_MAGIC, 0x93) ++#define MDrv_RSA_Calculate _IO(IOC_MAGIC, 0x94) ++ ++int rsa_crypto(struct rsa_config *op); ++ ++#endif +\ No newline at end of file +diff --git a/drivers/sstar/crypto/mdrv_sha.c b/drivers/sstar/crypto/mdrv_sha.c +new file mode 100755 +index 000000000000..0532d8abee6a +--- /dev/null ++++ b/drivers/sstar/crypto/mdrv_sha.c +@@ -0,0 +1,375 @@ ++/* ++* mdrv_sha.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "halAESDMA.h" ++#include ++ ++#define LOOP_CNT 10000 ++#define INFINITY_SHA_BUFFER_SIZE 1024 ++ ++#define SHA_DEBUG_FLAG (0) ++ ++#if (SHA_DEBUG_FLAG == 1) ++#define SHA_DBG(fmt, arg...) printk(KERN_ERR fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define SHA_DBG(fmt, arg...) ++#endif ++ ++//memory probe from aes.c ++extern struct aesdma_alloc_dmem ++{ ++ dma_addr_t aesdma_phy_addr ; ++ dma_addr_t aesdma_phy_SHABuf_addr; ++ const char* DMEM_AES_ENG_INPUT; ++ const char* DMEM_AES_ENG_SHABUF; ++ u8 *aesdma_vir_addr; ++ u8 *aesdma_vir_SHABuf_addr; ++}ALLOC_DMEM; ++ ++extern struct platform_device *psg_mdrv_aesdma; ++extern void enableClock(void); ++extern void disableClock(void); ++extern void allocMem(U32 len); ++extern void _ms_aes_mem_free(void); ++ ++extern void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr ); ++static u8 gu8WorkMode=0; ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++void allocTempMem(U32 len) ++{ ++ if (!(ALLOC_DMEM.aesdma_vir_SHABuf_addr = alloc_dmem(ALLOC_DMEM.DMEM_AES_ENG_SHABUF, ++ len, ++ &ALLOC_DMEM.aesdma_phy_SHABuf_addr))){ ++ printk("[input]unable to allocate aesdma memory\n"); ++ } ++ memset(ALLOC_DMEM.aesdma_vir_SHABuf_addr, 0, len); ++} ++ ++struct infinity_sha256_ctx ++{ ++ u8 digest[SHA256_DIGEST_SIZE]; ++ u32 u32digest_len; ++ u32 u32Bufcnt; ++}; ++ ++static int infinity_sha256_init(struct shash_desc *desc) ++{ ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ ++ ++ SHA_DBG(" %s,#%d \n",__FUNCTION__,__LINE__); ++ ++ HAL_SHA_Reset(); ++ ++ HAL_SHA_SelMode(1); ++ ++ gu8WorkMode = 0; ++ infinity_ctx->u32Bufcnt =0; ++ memset(sctx, 0, sizeof(struct sha256_state)); ++ return 0; ++} ++ ++/*static void hexdump(unsigned char *buf, unsigned int len) ++{ ++ print_hex_dump(KERN_CONT, "", DUMP_PREFIX_OFFSET, ++ 16, 1, ++ buf, len, false); ++}*/ ++ ++static int infinity_sha256_update(struct shash_desc *desc, const u8 *data, unsigned int len) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ u64 leftover = 0; ++ u32 u32InputCopied = 0; ++ u32 u32loopCnt; ++ ++ SHA_DBG("\t %s,#%d sctx->count:%llu len:%d\n", __FUNCTION__, __LINE__, sctx->count, len); ++ ++ leftover = infinity_ctx->u32Bufcnt + len; ++ while(leftover >= SHA256_BLOCK_SIZE) ++ { ++ int estimate_size = leftover - leftover%SHA256_BLOCK_SIZE; ++ SHA_DBG("\t\t %s,#%d leftover:%llu infinity_ctx->u32Bufcnt(%d) \n",__FUNCTION__, __LINE__, leftover, infinity_ctx->u32Bufcnt); ++ ++ memcpy(ALLOC_DMEM.aesdma_vir_SHABuf_addr + infinity_ctx->u32Bufcnt, data+u32InputCopied, estimate_size-infinity_ctx->u32Bufcnt); ++ ++ if (sctx->count) ++ { ++ HAL_SHA_Write_InitValue_BE((U32)sctx->state); ++ HAL_SHA_SetInitHashMode(1); ++ } ++ else ++ { ++ HAL_SHA_SetInitHashMode(0); ++ } ++ ++ Chip_Flush_MIU_Pipe(); ++ HAL_SHA_SetAddress(Chip_Phys_to_MIU(ALLOC_DMEM.aesdma_phy_SHABuf_addr)); ++ HAL_SHA_SetLength(estimate_size); ++ HAL_SHA_ManualMode(1); ++ ++ HAL_SHA_Start(); ++ ++ udelay(1); //sha256 cost about 1~1.4us ++ u32loopCnt = 0; ++ while(((HAL_SHA_GetStatus() & SHARNG_CTRL_SHA_READY) != SHARNG_CTRL_SHA_READY) ) ++ { ++ u32loopCnt++; ++ ++ if(u32loopCnt>LOOP_CNT) ++ { ++ printk("ERROR!! %s %d %d \n",__FUNCTION__, __LINE__, estimate_size); ++ break; ++ } ++ } ++ ++ HAL_SHA_Out((U32)sctx->state); ++ ++ HAL_SHA_Clear(); ++ u32InputCopied += estimate_size; ++ leftover -= estimate_size; ++ infinity_ctx->u32Bufcnt = 0; ++ sctx->count += estimate_size; ++ } ++ ++ if (leftover) ++ { ++ memcpy(ALLOC_DMEM.aesdma_vir_SHABuf_addr+infinity_ctx->u32Bufcnt, data+u32InputCopied, leftover); ++ infinity_ctx->u32Bufcnt = leftover; ++ } ++ ++ return 0; ++} ++ ++static const u8 padding[64+56] = { 0x80, }; ++ ++static int infinity_sha256_final(struct shash_desc *desc, u8 *out) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ int index, padlen; ++ __be64 bits; ++ ++ SHA_DBG("\t %s,#%d %llu \n", __FUNCTION__, __LINE__, sctx->count ); ++ bits = cpu_to_be64((sctx->count+infinity_ctx->u32Bufcnt) << 3); ++ ++ /* Pad out to 56 mod 64 */ ++ index = infinity_ctx->u32Bufcnt; ++ padlen = (index < 56) ? (56 - index) : ((64+56) - index); ++ infinity_sha256_update(desc, padding, padlen); ++ ++ /* Append length field bytes */ ++ infinity_sha256_update(desc, (const u8 *)&bits, sizeof(bits)); ++ ++ //HAL_SHA_Out((U32)sctx->state); ++ //hexdump((unsigned char *)sctx->state, SHA256_DIGEST_SIZE); ++ memcpy(out, sctx->state, SHA256_DIGEST_SIZE); ++ HAL_SHA_Reset(); ++ ++ return 0; ++} ++ ++static int infinity_sha256_export(struct shash_desc *desc, void *out) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ struct sha256_state *octx = out; ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ octx->count = sctx->count + infinity_ctx->u32digest_len; ++ memcpy(octx->buf, sctx->buf, sizeof(octx->buf)); ++ /* if no data has been processed yet, we need to export SHA256's ++ * initial data, in case this context gets imported into a software ++ * context */ ++ if(infinity_ctx->u32digest_len) ++ { ++ memcpy(octx->state, infinity_ctx->digest, SHA256_DIGEST_SIZE); ++ } ++ else ++ { ++ memset(octx->state, 0, SHA256_DIGEST_SIZE); ++ } ++ ++ return 0; ++} ++ ++static int infinity_sha256_import(struct shash_desc *desc, const void *in) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ const struct sha256_state *ictx = in; ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf)); ++ sctx->count = ictx->count & 0x3f; ++ infinity_ctx->u32digest_len = sctx->count; ++ if (infinity_ctx->u32digest_len) { ++ memcpy(infinity_ctx->digest, ictx->state, SHA256_DIGEST_SIZE); ++ } ++ return 0; ++} ++ ++int infinity_sha_init(u8 sha256_mode) ++{ ++ HAL_SHA_Reset(); ++ ++ if (sha256_mode) ++ { ++ HAL_SHA_SelMode(1); ++ } ++ else ++ { ++ HAL_SHA_SelMode(0); ++ } ++ ++ return 0; ++} ++ ++int infinity_sha_update(u32 *in, u32 len, u32 *state, u32 count, u8 once) ++{ ++ u32 loop = 0; ++ U32 msg_cnt = 0; ++ ++ SHA_DBG(" %s len %d count %d\n",__FUNCTION__, len, count); ++ if (count) ++ { ++ HAL_SHA_Write_InitValue((U32)state); ++ HAL_SHA_WriteWordCnt(count >> 2); // in unit of 4-bytes ++ HAL_SHA_SetInitHashMode(1); ++ } ++ else ++ { ++ HAL_SHA_SetInitHashMode(0); ++ } ++ ++ Chip_Flush_MIU_Pipe(); ++ HAL_SHA_SetAddress((U32)in); ++ HAL_SHA_SetLength(len); ++ if (once) ++ { ++ HAL_SHA_ManualMode(0); ++ } ++ else { ++ HAL_SHA_ManualMode(1); ++ } ++ ++ HAL_SHA_Start(); ++ udelay(1); //sha256 cost about 1~1.4us ++ ++ while(((HAL_SHA_GetStatus() & SHARNG_CTRL_SHA_READY) != SHARNG_CTRL_SHA_READY) && (loop < LOOP_CNT)) ++ { ++ loop++; ++ //usleep_range(20, 80); ++ } ++ HAL_SHA_ReadOut((U32)state); ++ msg_cnt = HAL_SHA_ReadWordCnt() << 2; ++ SHA_DBG("msg calculated %d -> %d\n", count, (u32)msg_cnt); ++ SHA_DBG("x%x, x%x, x%x, x%x, x%x, x%x, x%x, x%x\n", state[0], state[1], state[2], state[3], state[4], state[5], state[6], state[7]); ++ HAL_SHA_Clear(); ++ return 0; ++} ++ ++int infinity_sha_final(void) ++{ ++ HAL_SHA_Reset(); ++ ++ return 0; ++} ++ ++struct shash_alg infinity_shash_sha256_alg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .init = infinity_sha256_init, ++ .update = infinity_sha256_update, ++ .final = infinity_sha256_final, ++ .export = infinity_sha256_export, ++ .import = infinity_sha256_import, ++ .descsize = sizeof(struct sha256_state), ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha256", ++ .cra_driver_name = "sha256-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_SHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_module = THIS_MODULE, ++ .cra_ctxsize = sizeof(struct infinity_sha256_ctx), ++ } ++}; ++ ++ ++ ++int infinity_sha_create(void) ++{ ++ int ret = -1; ++ ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ ++ allocTempMem(4096); ++ ++ ret = crypto_register_shash(&infinity_shash_sha256_alg); ++ ++ return ret; ++} ++ ++int infinity_sha_destroy(void) ++{ ++ _ms_aes_mem_free(); ++ ++// crypto_unregister_alg(&infinity_shash_sha256_alg); ++ return 0; ++} +diff --git a/drivers/sstar/dualos/Makefile b/drivers/sstar/dualos/Makefile +new file mode 100755 +index 000000000000..9e787d10e851 +--- /dev/null ++++ b/drivers/sstar/dualos/Makefile +@@ -0,0 +1,12 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ifdef CONFIG_MSTAR_PROJECT_NAME ++ CONFIG_MSTAR_PROJECT_NAME := $(subst ",,$(CONFIG_MSTAR_PROJECT_NAME)) ++endif ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux -D_LINUX_ -Wno-unused-function ++ ++obj-y += drv_dualos.o ++obj-y += rsq.o ++obj-y += sw_sem.o +diff --git a/drivers/sstar/dualos/drv_dualos.c b/drivers/sstar/dualos/drv_dualos.c +new file mode 100755 +index 000000000000..a5859f055350 +--- /dev/null ++++ b/drivers/sstar/dualos/drv_dualos.c +@@ -0,0 +1,822 @@ ++/* ++* ipc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Canlet.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * drv_dualos.c ++ * ipc rsq with LH/RTOS ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "linux/arm-smccc.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "drv_dualos.h" ++#include "interos_call.h" ++#include "rsq.h" ++#include "sw_sem.h" ++#include "lock.h" ++ ++/* proc */ ++#include ++#include ++#include ++#include ++#include ++ ++static int disable_rtos = 0; ++module_param(disable_rtos, int, 0644); ++MODULE_PARM_DESC(disable_rtos, "Disable RTOS IPC"); ++ ++static struct file *file_open(const char *path, int flags, int rights); ++static void file_close(struct file *file); ++static int file_write(struct file *file, unsigned long long offset, unsigned char *data, unsigned int size); ++static int file_read(struct file *file, unsigned long long offset, unsigned char *data, unsigned int size); ++static int file_sync(struct file *file); ++/* */ ++struct sstream { ++ reservoir_t *rvr; ++ struct resource *res; ++ unsigned int id; ++ void *private; ++}; ++ ++#define SHARE_SIZE (0x1000) ++static rtkinfo_t *_rtklin; ++static struct sstream _sstr[8] = { { 0 } }; ++ ++static struct resource *_rtkres; ++unsigned int _ipi[8] = { 0 }; ++#ifdef CONFIG_SS_AMP ++struct semaphore _interos_call_mbox; ++struct semaphore _interos_call_resp; ++struct semaphore _interos_call_req; ++static int _interos_call_pid; ++static int _signal_1st_using_mbox = 1; ++#endif ++#if ENABLE_NBLK_CALL ++struct semaphore _interos_nblk_call_req; ++static int _interos_nblk_call_pid; ++#endif ++ ++struct rsqcb { ++ struct list_head list; ++ int (*rsqproc)(void *param, void *buf, int size, slot_t* slot); ++ void *private; ++}; ++ ++LIST_HEAD(_rsqcblst); ++struct rsqcb rec_rsq; ++struct rsqrec { ++ struct rsqcb cb; ++ char file[32]; ++ reservoir_t *rvr; ++ unsigned int frms; ++ struct file *fp; ++ long long off; ++}; ++ ++#ifdef CONFIG_SMP ++static reroute_smc_info_t _reroute_smc_info; ++#endif ++ ++static int c_logshow(struct seq_file *m, void *v) ++{ ++ reservoir_t *rv; ++ unsigned int rs; ++ char msg[256]; ++ slot_t slot; ++ ++ rv = m->private; ++ if (!rv) { ++ seq_printf(m, "not available\n"); ++ return 0; ++ } ++/* for debug ++ seq_printf(m, "Reservoir - %s(%p) size %dK\n", rv->name, rv, rv->size >> 10); ++ seq_printf(m, "\tCurrent available frame NO.\t: %d~%d\n", rv->ns.rdno, rv->slotno); ++ seq_printf(m, "\treset id \t: %d~%d\n", rv->ss.reset_id, rv->ns.reset_id); ++ seq_printf(m, "\tDrop Count/Frms\t: %u/%u\n", rv->dropcnt, rv->dropfrms); ++ seq_printf(m, "\tReservoir Reset\t: %u\n", rv->resetcnt); ++ seq_printf(m, "\tHot sync\t: %u\n", rv->synccnt); ++*/ ++ do { ++ DUALOS_LOCK_INIT; ++ DUALOS_LOCK; ++ rs = rcvr_de_rsqslot(rv, msg, sizeof(msg), (slot_t*)&slot); ++ DUALOS_UNLOCK; ++ if (!rs) break; ++ seq_printf(m, msg); ++ } while (m->size >= (m->count + sizeof(msg))); ++ ++ seq_printf(m, "\n"); ++ ++ return 0; ++} ++ ++static void *c_start(struct seq_file *m, loff_t *pos) ++{ ++ return *pos < 1 ? (void *)1 : NULL; ++} ++ ++static void *c_next(struct seq_file *m, void *v, loff_t *pos) ++{ ++ ++*pos; ++ return NULL; ++} ++ ++static void c_stop(struct seq_file *m, void *v) ++{ ++} ++ ++const struct seq_operations rsqlog_op = { ++ .start = c_start, ++ .next = c_next, ++ .stop = c_stop, ++ .show = c_logshow ++}; ++ ++static int rsqinfo_open(struct inode *inode, struct file *file) ++{ ++ int res = -ENOMEM; ++ int i; ++ struct seq_file *seq; ++ ++ res = seq_open(file, NULL); ++ if (res) ++ return res; ++ seq = file->private_data; ++ for (i = 0; i < sizeof(_sstr) / sizeof(struct sstream); i++) { ++ if (!_sstr[i].rvr) continue; ++ if (!strncmp(file->f_path.dentry->d_iname, ++ _sstr[i].rvr->name, sizeof(_sstr[i].rvr->name))) { ++ seq->private = _sstr[i].rvr; ++ break; ++ } ++ } ++ if (i == (sizeof(_sstr) / sizeof(struct sstream))) ++ return -ENOMEM; ++ seq->op = _sstr[i].private; ++ return res; ++} ++ ++static ssize_t rsqinfo_write(struct file *file, const char __user *buf, size_t len, loff_t *pos) ++{ ++ char code[32]; ++ reservoir_t *rv; ++ ++ rv = (reservoir_t*)((struct seq_file *)file->private_data)->private; ++ if (!rv) return len; ++ if (copy_from_user(code, buf, 32)) ++ return -EFAULT; ++ if (strncmp(rv->name, "log", 3) == 0) { ++ signal_rtos(INTEROS_SC_L2R_RTK_LOG, 0, 0, 0); ++ } ++ ++ return len; ++} ++ ++#define TTM(s) (((s) + 3000) / 6000) ++static u64 _spent = 0, _lifet = 0; ++static u64 _spent_hyp = 0, _spent_sc = 0; ++static int c_show_rtk(struct seq_file *m, void *v) ++{ ++ rtkinfo_t *rtk; ++ int i; ++ int s; ++ u64 cs, cl; ++ int sh, sc; ++ u64 ch, cc; ++ ++ rtk = m->private; ++ if (!rtk) { ++ seq_printf(m, "not avaliable\n"); ++ return 0; ++ } ++ /* reset cpu usage after present */ ++ cs = rtk->spent; ++ cl = rtk->lifet; ++ ch = rtk->spent_hyp; ++ cc = rtk->spent_sc; ++ ++ s = (int)div64_u64((cs - _spent) * 1000, (cl - _lifet)); ++ if (ch && cc) // It means __ADV_HYP_PROF__ enabled in rtos ++ { ++ sh = (int)div64_u64((ch - _spent_hyp) * 1000, (cl - _lifet)); ++ sc = (int)div64_u64((cc - _spent_sc) * 1000, (cl - _lifet)); ++ } ++ ++ seq_printf(m, "RTOS: %s\n", rtk->version); ++ ++ if (ch && cc) // It means __ADV_HYP_PROF__ enabled in rtos ++ { ++ seq_printf(m, "\tcpu usage(hyp/sc/rtos): %u.%u%% (%llu/%llu)\n", s / 10, s % 10, cs - _spent, cl - _lifet); ++ seq_printf(m, "\tcpu usage(hyp): %u.%u%% (%llu/%llu)\n", sh / 10, sh % 10, ch - _spent_hyp, cl - _lifet); ++ seq_printf(m, "\tcpu usage(sc): %u.%u%% (%llu/%llu)\n", sc / 10, sc % 10, cc - _spent_sc, cl - _lifet); ++ } ++ else ++ { ++ seq_printf(m, "\tcpu usage: %u.%u%% (%llu/%llu)\n", s / 10, s % 10, cs - _spent, cl - _lifet); ++ } ++ seq_printf(m, "\tttff(isp): %u ms\n", TTM(rtk->ttff_isp)); ++ seq_printf(m, "\tttff(scl): %u ms\n", TTM(rtk->ttff_scl)); ++ seq_printf(m, "\tttff(mfe): %u ms\n", TTM(rtk->ttff_mfe)); ++ seq_printf(m, "\tload ns : %u ms\n", TTM(rtk->ldns_ts)); ++ seq_printf(m, "\tfiq count: %u\n", rtk->fiq_cnt); ++ seq_printf(m, "\tsyscall : %llu\n", rtk->syscall_cnt); ++ for (i = 0; i < 8; i++) ++ if (_ipi[i]) seq_printf(m, "\tipi%02d count: %u\n", i + 8, _ipi[i]); ++ _spent = cs; _lifet = cl; ++ if (ch && cc) // It means __ADV_HYP_PROF__ enabled in rtk ++ { ++ _spent_hyp = ch; ++ _spent_sc = cc; ++ } ++ ++ return 0; ++} ++ ++static ssize_t rtkinfo_write(struct file *file, const char __user *buf, size_t len, loff_t *pos) ++{ ++ char code[128]; ++ rtkinfo_t *rtk; ++ ++ rtk = (rtkinfo_t*)((struct seq_file *)file->private_data)->private; ++ if (!rtk) return len; ++ if (copy_from_user(code, buf, sizeof(code))) ++ return -EFAULT; ++ // rtkinfo simple command parser ++ // cli - ++ if (!strncmp(code, "cli", 3)) { ++ char *ptr; ++ // strip return and space in tail and head. ++ ptr = strrchr(code, 0x0a); ++ if (ptr) *ptr = '\0'; ++ for (ptr = code + 4; *ptr == ' ' || *ptr == '\t'; ptr++); ++ // copy command to share buffer and send to S ++ strncpy(rtk->sbox, ptr, 127); ++ signal_rtos(INTEROS_SC_L2R_RTK_CLI, (u32)rtk, (u32)rtk->diff, 0); ++ } else if (!strncmp(code, "reset", 4)) { ++ } ++ return len; ++} ++ ++const struct seq_operations rtkinfo_op = { ++ .start = c_start, ++ .next = c_next, ++ .stop = c_stop, ++ .show = c_show_rtk ++}; ++ ++static int rtkinfo_open(struct inode *inode, struct file *file) ++{ ++ int res = -ENOMEM; ++ struct seq_file *seq; ++ ++ res = seq_open(file, &rtkinfo_op); ++ if (res) ++ return res; ++ seq = file->private_data; ++ seq->private = (void*)_rtklin; ++ return res; ++} ++ ++static const struct file_operations proc_rsqinfo_operations = { ++ .open = rsqinfo_open, ++ .read = seq_read, ++ .write = rsqinfo_write, ++ .llseek = seq_lseek, ++ .release = seq_release, ++}; ++ ++static const struct file_operations proc_rtkinfo_operations = { ++ .open = rtkinfo_open, ++ .read = seq_read, ++ .write = rtkinfo_write, ++ .llseek = seq_lseek, ++ .release = seq_release, ++}; ++ ++static bool alkaid_notify_nop(int no){ ++ return false; ++} ++static bool (*alkaid_notify[1])(int no) = {alkaid_notify_nop}; ++void alkaid_registe_notify(int cpu, void *notify){ ++ alkaid_notify[cpu] = notify; ++} ++EXPORT_SYMBOL(alkaid_registe_notify); ++void *alkaid_unregiste_notify(int cpu){ ++ void *notify = alkaid_notify[cpu]; ++ alkaid_notify[cpu] = alkaid_notify_nop; ++ return notify; ++} ++EXPORT_SYMBOL(alkaid_unregiste_notify); ++ ++/* call from gic_handle_irq (gic-irq.c) */ ++void handle_rsq(unsigned int irqnr) ++{ ++ if (alkaid_notify[0](irqnr)) ++ { ++ return; ++ } ++ _ipi[irqnr - 8]++; ++} ++ ++#ifdef CONFIG_SS_AMP ++unsigned long do_interos_call(u32 type, u32 arg1, u32 arg2, u32 arg3) ++{ ++ u32 ret = 0; ++ ++ switch (type) { ++ case INTEROS_SC_R2L_MI_NOTIFY: ++ if (alkaid_notify[0](arg1)) ++ { ++ ret = 0; ++ } ++ break; ++#ifdef CONFIG_SS_SWTOE ++ case INTEROS_SC_L2R_SWTOE: ++ { ++ extern int drv_swtoe_cb_hdl(u32 arg0, u32 arg1, u32 arg2, u32 arg3); ++ drv_swtoe_cb_hdl(type, arg1, arg2, arg3); ++ } ++#endif ++ default: ++ break; ++ } ++ ++ return ret; ++} ++ ++void handle_interos_call_req(void) ++{ ++ up(&_interos_call_req); ++} ++ ++void handle_interos_call_resp(void) ++{ ++ up(&_interos_call_resp); ++} ++ ++static int interos_call_receiver(void *unused) ++{ ++ struct task_struct *tsk = current; ++ u32 arg0, arg1, arg2, arg3, ret; ++ int signal_1st_using_mbox; ++ ++ interos_call_mbox_args_t *ptr_mbox_args; ++ interos_call_args_t *ptr_args; ++ struct arm_smccc_res res; ++ ++ /* Setup a clean context for our children to inherit. */ ++ set_task_comm(tsk, "interos_call_receiver"); ++ sema_init(&_interos_call_req, 0); ++ while (1) { ++ down(&_interos_call_req); ++ signal_1st_using_mbox = _signal_1st_using_mbox; ++ ++ if (signal_1st_using_mbox) ++ { ++ ptr_mbox_args = (interos_call_mbox_args_t *)(BASE_REG_MAILBOX_PA+BK_REG(0x50)+IO_OFFSET); ++ arg0 = (ptr_mbox_args->arg0_h << 16) + ptr_mbox_args->arg0_l; ++ arg1 = (ptr_mbox_args->arg1_h << 16) + ptr_mbox_args->arg1_l; ++ arg2 = (ptr_mbox_args->arg2_h << 16) + ptr_mbox_args->arg2_l; ++ arg3 = (ptr_mbox_args->arg3_h << 16) + ptr_mbox_args->arg3_l; ++ } ++ else ++ { ++ ptr_args = (interos_call_args_t *)((u32)_rtklin + INTEROS_CALL_SHMEM_OFFSET_RX); ++ arg0 = ptr_args->arg0; ++ arg1 = ptr_args->arg1; ++ arg2 = ptr_args->arg2; ++ arg3 = ptr_args->arg3; ++ } ++ ++ /* process here */ ++ ret = do_interos_call(arg0, arg1, arg2, arg3); ++ if (signal_1st_using_mbox) ++ { ++ ptr_mbox_args->ret_l = ret & 0xFFFF; ++ ptr_mbox_args->ret_h = ret >> 16; ++ } ++ else ++ { ++ ptr_args->ret = ret; ++ } ++ arm_smccc_smc(INTEROS_SC_L2R_CALL, TARGET_BITS_CORE0, NSATT_BITS_GROUP0, SGIINTID_BITS_09, 0, 0, 0, 0, &res); ++ } ++ return 0; ++} ++#endif ++ ++#if ENABLE_NBLK_CALL ++void handle_interos_nblk_call_req(void) ++{ ++ up(&_interos_nblk_call_req); ++} ++ ++void do_interos_nblk_call(u32 type, u32 arg1, u32 arg2, u32 arg3) ++{ ++} ++ ++static int interos_nblk_call_receiver(void *unused) ++{ ++ struct task_struct *tsk = current; ++ ++ reservoir_t *rv; ++ unsigned int rs; ++ char msg[32]; ++ slot_t slot; ++ u32 arg0, arg1, arg2, arg3; ++ int i; ++ ++ for (i = 0; i < 8; i++) ++ { ++ if (_sstr[i].rvr != NULL && strncmp(_sstr[i].rvr->name, "nblk_call", 9) == 0) ++ { ++ rv = _sstr[i].rvr; ++ break; ++ } ++ } ++ ++ if (rv == NULL) ++ { ++ printk(KERN_ERR "Error!! interos nblk call rsq\n"); ++ *(int *)0 = 0; ++ } ++ ++ /* Setup a clean context for our children to inherit. */ ++ set_task_comm(tsk, "interos_nblk_call_receiver"); ++ sema_init(&_interos_nblk_call_req, 0); ++ while (1) { ++ down(&_interos_nblk_call_req); ++ do { ++ rs = rcvr_de_rsqslot(rv, msg, sizeof(msg), (slot_t*)&slot); ++ if (!rs) break; ++ arg0 = *((u32 *)msg); ++ arg1 = *((u32 *)(msg + 4)); ++ arg2 = *((u32 *)(msg + 8)); ++ arg3 = *((u32 *)(msg + 12)); ++ ++ /* process here */ ++ do_interos_nblk_call(arg0, arg1, arg2, arg3); ++ } while (1); ++ } ++ return 0; ++} ++#endif ++ ++static int __init epoch_init(void) ++{ ++ char proc[32]; ++ long share; ++ struct rlink_head *rl; ++#ifdef CONFIG_SMP ++ int cpu = smp_processor_id(); ++#endif ++ ++ if (disable_rtos) ++ { ++ return 0; ++ } ++ ++#ifdef CONFIG_SMP ++ if (cpu != 0) ++ return 0; ++ ++ sema_init(&(_reroute_smc_info.mbox_sem), 1); ++ sema_init(&(_reroute_smc_info.resp_sem), 0); ++#endif ++ ++ proc_mkdir("dualos", NULL); ++ ++#ifdef CONFIG_SS_AMP ++ sema_init(&_interos_call_mbox, 1); ++ sema_init(&_interos_call_resp, 0); ++#endif ++ ++ /* get RTOS info */ ++ share = (long)signal_rtos(INTEROS_SC_L2R_HANDSHAKE, (u32)0, (u32)0, (u32)0); ++#ifdef CONFIG_SS_AMP ++ _signal_1st_using_mbox = 0; ++#endif ++ _rtkres = request_mem_region(share, SHARE_SIZE, "dualos"); ++ _rtklin = (rtkinfo_t*)ioremap(_rtkres->start, resource_size(_rtkres)); ++ ++#if defined(CONFIG_SS_AMP) || (defined(CONFIG_LH_RTOS) && defined(CONFIG_SMP)) ++ intercore_sem_init((u32)_rtklin + SHARE_SIZE - sizeof(intercore_sem_t)); ++#endif ++ ++ if (INTEROS_CALL_SHMEM_PARAM_SIZE < sizeof(interos_call_args_t)) { ++ printk(KERN_ERR "Error!! interos shmem param address\n"); ++ *(int *)0 = 0; ++ } ++ ++ if (!_rtklin || ++ _rtklin->size != sizeof(*_rtklin) || ++ _rtklin->verid != RSQ_VERSION_ID) { ++ proc_create("dualos/version_not_match", 0, NULL, &proc_rtkinfo_operations); ++ printk(KERN_ERR "Error!! RTOS version not match\n"); ++ _rtklin = NULL; ++ return 0; ++ } ++ snprintf(proc, sizeof(proc), "dualos/%s", _rtklin->name); ++ proc_create(proc, 0, NULL, &proc_rtkinfo_operations); ++ /* */ ++ for (rl = &(_rtklin->root); rl->nphys && rl->nsize;) { ++ struct sstream sst; ++ ++ sst.res = request_mem_region((long)rl->nphys, rl->nsize, "rsq"); ++ sst.rvr = (reservoir_t*)ioremap(sst.res->start, resource_size(sst.res)); ++ rename_region(sst.res, sst.rvr->name); ++ init_rsq_rcvr(sst.rvr); ++ snprintf(proc, sizeof(proc), "dualos/%s", sst.rvr->name); ++ proc_create(proc, 0, NULL, &proc_rsqinfo_operations); ++ sst.id = sst.rvr->iid; ++ if (strncmp(sst.rvr->name, "log", 3) == 0) ++ sst.private = (void*)&rsqlog_op; // set log read op ++ _sstr[sst.id] = sst; ++ rl = &(sst.rvr->link); ++ } ++ _rtklin->diff = (unsigned int)share - (unsigned int)_rtklin; // offset for address transfer ++ ++#ifdef CONFIG_SS_AMP ++ /* create a thread to get interos call */ ++ _interos_call_pid = kernel_thread(interos_call_receiver, NULL, CLONE_FS | CLONE_FILES); ++#endif ++ ++#if ENABLE_NBLK_CALL ++ _interos_nblk_call_pid = kernel_thread(interos_nblk_call_receiver, NULL, CLONE_FS | CLONE_FILES); ++#endif ++ ++ /* for debug */ ++ signal_rtos(INTEROS_SC_L2R_RSQ_INIT, (u32)_rtklin, _rtklin->diff, 0); ++ return 0; ++} ++ ++/* ++ * kerenl file I/O ++ */ ++struct file *file_open(const char *path, int flags, int rights) ++{ ++ struct file *filp = NULL; ++ mm_segment_t oldfs; ++ int err = 0; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ filp = filp_open(path, flags, rights); ++ set_fs(oldfs); ++ if (IS_ERR(filp)) { ++ err = PTR_ERR(filp); ++ return NULL; ++ } ++ return filp; ++} ++ ++void file_close(struct file *file) ++{ ++ filp_close(file, NULL); ++} ++ ++int file_read(struct file *file, unsigned long long offset, unsigned char *data, unsigned int size) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ ret = vfs_read(file, data, size, &offset); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++int file_write(struct file *file, unsigned long long offset, unsigned char *data, unsigned int size) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ ret = vfs_write(file, data, size, &offset); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++int file_sync(struct file *file) ++{ ++ vfs_fsync(file, 0); ++ return 0; ++} ++ ++rtkinfo_t* get_rtkinfo(void) ++{ ++ return _rtklin; ++} ++ ++#define GICD_SGIR 0x0F00 ++#define GICD_BASE 0xF4001000 ++#define GICD_WRITEL(a,v) (*(volatile unsigned int *)(u32)(GICD_BASE + a) = (v)) ++ ++static void hal_send_SGI(int cpu, int no) ++{ ++ GICD_WRITEL(GICD_SGIR, (1 << (cpu + 16)) | (1 << 15) | no); ++} ++ ++/* call to RTOS */ ++#ifdef CONFIG_SS_AMP ++unsigned long signal_rtos(u32 type, u32 arg1, u32 arg2, u32 arg3) ++{ ++ interos_call_mbox_args_t *ptr_mbox_args; ++ interos_call_args_t *ptr_args; ++ struct arm_smccc_res res; ++ u32 ret; ++ int signal_1st_using_mbox; ++ ++ if (disable_rtos) ++ { ++ return -1; ++ } ++ ++ down(&_interos_call_mbox); ++ ++ signal_1st_using_mbox = _signal_1st_using_mbox; ++ ++ if (signal_1st_using_mbox) ++ { ++ ptr_mbox_args = (interos_call_mbox_args_t *)(BASE_REG_MAILBOX_PA+BK_REG(0x60)+IO_OFFSET); ++ ptr_mbox_args->arg0_l = type & 0xFFFF; ++ ptr_mbox_args->arg0_h = type >> 16; ++ ptr_mbox_args->arg1_l = arg1 & 0xFFFF; ++ ptr_mbox_args->arg1_h = arg1 >> 16; ++ ptr_mbox_args->arg2_l = arg2 & 0xFFFF; ++ ptr_mbox_args->arg2_h = arg2 >> 16; ++ ptr_mbox_args->arg3_l = arg3 & 0xFFFF; ++ ptr_mbox_args->arg3_h = arg3 >> 16; ++ ptr_mbox_args->ret_l = 0; ++ ptr_mbox_args->ret_h = 0; ++ } ++ else ++ { ++ ptr_args = (interos_call_args_t *)((u32)_rtklin + INTEROS_CALL_SHMEM_OFFSET_TX); ++ ptr_args->arg0 = type; ++ ptr_args->arg1 = arg1; ++ ptr_args->arg2 = arg2; ++ ptr_args->arg3 = arg3; ++ ptr_args->ret = 0; ++ } ++ ++ arm_smccc_smc(INTEROS_SC_L2R_CALL, TARGET_BITS_CORE0, NSATT_BITS_GROUP0, SGIINTID_BITS_10, 0, 0, 0, 0, &res); ++ ++ down(&_interos_call_resp); ++ ++ if (signal_1st_using_mbox) ++ { ++ ret = (ptr_mbox_args->ret_h << 16) + ptr_mbox_args->ret_l; ++ } ++ else ++ { ++ ret = ptr_args->ret; ++ } ++ ++ up(&_interos_call_mbox); ++ ++ return ret; ++} ++#endif ++#ifdef CONFIG_LH_RTOS ++#ifndef CONFIG_SMP ++unsigned long signal_rtos(u32 type, u32 arg1, u32 arg2, u32 arg3) ++{ ++ struct arm_smccc_res res; ++ ++ if (disable_rtos) ++ { ++ return -1; ++ } ++ ++ arm_smccc_smc(type, arg1, arg2, arg3, ++ 0, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++#else ++#include ++unsigned long signal_rtos(u32 type, u32 arg1, u32 arg2, u32 arg3) ++{ ++ struct arm_smccc_res res; ++ int cpu, cpu_v; ++ long ret; ++ struct cpumask old_mask, new_mask; ++ ++ if (disable_rtos) ++ { ++ return -1; ++ } ++ ++ down(&(_reroute_smc_info.mbox_sem)); ++ ++ _reroute_smc_info.type = type; ++ _reroute_smc_info.arg1 = arg1; ++ _reroute_smc_info.arg2 = arg2; ++ _reroute_smc_info.arg3 = arg3; ++ ++ cpu = get_cpu(); ++ ret = sched_getaffinity(0, &old_mask); ++ if (ret != 0) ++ { ++ printk(KERN_CRIT "get affinity error at %s %d, ret:%ld\n", ++ __FUNCTION__, __LINE__, ret); ++ } ++ cpumask_clear(&new_mask); ++ cpumask_set_cpu(cpu, &new_mask); ++ ret = sched_setaffinity(0, &new_mask); ++ if (ret != 0) ++ { ++ printk(KERN_CRIT "set affinity error at %s %d, ret:%ld\n", ++ __FUNCTION__, __LINE__, ret); ++ } ++ put_cpu(); ++ ++ if (cpu != 0) ++ { ++ cpu_v = get_cpu(); ++ if (cpu_v == 0) ++ { ++ printk(KERN_CRIT "%s %d: cpu_v:%d\n", __FUNCTION__, __LINE__, cpu_v); ++ asm("b ."); ++ } ++ put_cpu(); ++ ++ hal_send_SGI(0, IPI_NR_REROUTE_SMC); ++ down(&(_reroute_smc_info.resp_sem)); ++ res.a0 = _reroute_smc_info.ret; ++ } ++ else ++ { ++ cpu_v = get_cpu(); ++ if (cpu_v != 0) ++ { ++ printk(KERN_CRIT "%s %d: cpu_v:%d\n", __FUNCTION__, __LINE__, cpu_v); ++ asm("b ."); ++ } ++ put_cpu(); ++ ++ arm_smccc_smc(_reroute_smc_info.type, ++ _reroute_smc_info.arg1, ++ _reroute_smc_info.arg2, ++ _reroute_smc_info.arg3, ++ 0, 0, 0, 0, &res); ++ } ++ ++ ret = sched_setaffinity(0, &old_mask); ++ if (ret != 0) ++ { ++ printk(KERN_CRIT "set affinity error at %s %d, ret=%ld\n", __FUNCTION__, __LINE__, ret); ++ } ++ up(&(_reroute_smc_info.mbox_sem)); ++ ++ return res.a0; ++} ++ ++void handle_reroute_smc(void) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(_reroute_smc_info.type, ++ _reroute_smc_info.arg1, ++ _reroute_smc_info.arg2, ++ _reroute_smc_info.arg3, ++ 0, 0, 0, 0, &res); ++ _reroute_smc_info.ret = res.a0; ++ up(&(_reroute_smc_info.resp_sem)); ++} ++#endif ++#endif ++ ++fs_initcall(epoch_init); +diff --git a/drivers/sstar/dualos/interos_call.h b/drivers/sstar/dualos/interos_call.h +new file mode 100755 +index 000000000000..2e67910114ca +--- /dev/null ++++ b/drivers/sstar/dualos/interos_call.h +@@ -0,0 +1,83 @@ ++/* ++* syscall.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Canlet.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * syscall.h ++ */ ++#ifndef __DUALOS_SYSCALL_H__ ++#define __DUALOS_SYSCALL_H__ ++ ++#ifdef __linux__ ++#include ++#endif ++#include "drv_dualos.h" ++ ++#define TARGET_BITS_CORE0 (1 << 16) ++#define TARGET_BITS_CORE1 (1 << 17) ++#define NSATT_BITS_GROUP0 (0 << 15) ++#define NSATT_BITS_GROUP1 (1 << 15) ++#define SGIINTID_BITS_08 (8) ++#define SGIINTID_BITS_09 (9) ++#define SGIINTID_BITS_10 (10) ++#define SGIINTID_BITS_11 (11) ++ ++#define INTEROS_CALL_SHMEM_PARAM_SIZE 0x80 ++ ++#define INTEROS_CALL_SHMEM_OFFSET_RX 0x800 ++#define INTEROS_CALL_SHMEM_OFFSET_TX (INTEROS_CALL_SHMEM_OFFSET_RX + INTEROS_CALL_SHMEM_PARAM_SIZE) ++ ++#define CORE_RTK 0 ++#define CORE_LINUX 1 ++ ++#define RSQ_VERSION_ID (0x100) ++ ++typedef struct { ++ unsigned int arg0_l; ++ unsigned int arg0_h; ++ unsigned int arg1_l; ++ unsigned int arg1_h; ++ unsigned int arg2_l; ++ unsigned int arg2_h; ++ unsigned int arg3_l; ++ unsigned int arg3_h; ++ unsigned int ret_l; ++ unsigned int ret_h; ++} interos_call_mbox_args_t; ++ ++typedef struct { ++ unsigned int arg0; ++ unsigned int arg1; ++ unsigned int arg2; ++ unsigned int arg3; ++ unsigned int ret; ++} interos_call_args_t; ++ ++#ifdef __linux__ ++typedef struct { ++ u32 type; ++ u32 arg1; ++ u32 arg2; ++ u32 arg3; ++ u32 ret; ++ struct semaphore mbox_sem; ++ struct semaphore resp_sem; ++} reroute_smc_info_t; ++#endif ++ ++u64 _getsysts(void); ++void init_interos_call(void *share, int size); ++#endif // __DUALOS_SYSCALL_H__ +diff --git a/drivers/sstar/dualos/lock.h b/drivers/sstar/dualos/lock.h +new file mode 100755 +index 000000000000..111e7eb5d427 +--- /dev/null ++++ b/drivers/sstar/dualos/lock.h +@@ -0,0 +1,50 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifdef _LINUX_ ++ #ifdef CONFIG_SS_AMP ++ #define DUALOS_LOCK_INIT AMP_LOCK_INIT() ++ #define DUALOS_LOCK AMP_LOCK() ++ #define DUALOS_UNLOCK AMP_UNLOCK() ++ #endif ++ #ifdef CONFIG_LH_RTOS ++ #include ++ #ifdef CONFIG_SMP ++ #define DUALOS_LOCK_INIT AMP_LOCK_INIT() ++ #define DUALOS_LOCK if (get_cpu() == 0) { \ ++ local_fiq_disable(); \ ++ } \ ++ AMP_LOCK() ++ #define DUALOS_UNLOCK AMP_UNLOCK(); \ ++ if (smp_processor_id() == 0) { \ ++ local_fiq_enable(); \ ++ put_cpu(); \ ++ } ++ #else ++ #define DUALOS_LOCK_INIT ++ #define DUALOS_LOCK local_fiq_disable() ++ #define DUALOS_UNLOCK local_fiq_enable() ++ #endif ++ #endif ++#else //RTOS ++ #ifdef __ENABLE_AMP__ ++ #define DUALOS_LOCK_INIT AMP_LOCK_INIT() ++ #define DUALOS_LOCK AMP_LOCK() ++ #define DUALOS_UNLOCK AMP_UNLOCK() ++ #else ++ #define DUALOS_LOCK_INIT ++ #define DUALOS_LOCK ++ #define DUALOS_UNLOCK ++ #endif ++#endif +diff --git a/drivers/sstar/dualos/rlink.h b/drivers/sstar/dualos/rlink.h +new file mode 100755 +index 000000000000..ce6004da3d02 +--- /dev/null ++++ b/drivers/sstar/dualos/rlink.h +@@ -0,0 +1,68 @@ ++/* ++* rlink.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Canlet.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * rlink.h ++ */ ++#ifndef __RLINK_H__ ++#define __RLINK_H__ ++ ++#include "drv_dualos.h" ++ ++static inline void init_rlink(struct rlink_head *head) ++{ ++ head->next = head; ++ head->prev = head; ++} ++ ++static inline int rlink_empty(const struct rlink_head *head) ++{ ++ return head->next == head; ++} ++ ++/* ++ * Insert a new entry between two known consecutive entries. ++ * ++ * This is only for internal rlink manipulation where we know ++ * the prev/next entries already! ++ */ ++static inline void __rlink_add(struct rlink_head *_new, ++ struct rlink_head *prev, ++ struct rlink_head *next, ++ unsigned int nsize) ++{ ++ next->prev = _new; ++ _new->next = next; ++ _new->prev = prev; ++ prev->next = _new; ++ prev->nsize = nsize; ++} ++ ++/** ++ * rlink_add_tail - add a new entry ++ * @new: new entry to be added ++ * @head: rlink head to add it before ++ * ++ * Insert a new entry before the specified head. ++ * This is useful for implementing queues. ++ */ ++static inline void rlink_add_tail(struct rlink_head *_new, struct rlink_head *head, unsigned int nsize) ++{ ++ __rlink_add(_new, head->prev, head, nsize); ++} ++ ++#endif // __RLINK_H__ +diff --git a/drivers/sstar/dualos/rsq.c b/drivers/sstar/dualos/rsq.c +new file mode 100755 +index 000000000000..48d48cae2d66 +--- /dev/null ++++ b/drivers/sstar/dualos/rsq.c +@@ -0,0 +1,403 @@ ++/* ++* rsq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Canlet.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * rsq.c ++ */ ++#include "rsq.h" ++#include "string.h" ++#include "cam_os_wrapper.h" ++#include "ms_platform.h" ++ ++#define RQ_TAG (0xfeeffe2f) ++ ++/* ++ **NOTE**: RQ_ALIGN size should be larger or equal than sizeof(slot_t)!! ++ */ ++ ++ ++/* rsq/int usage map, ++ * each rsq with an interrupt (SGI/IPI) to send irq to NS. ++ * bit is 0 for free, 1 is occupied. ++ * Total number of SGI is 16 for CA7, linux occupied 0~7. ++ * RSQ can use 8~15 ++ */ ++static int _rsqid_ = 0x00ffffff; ++/* ++ * init_rsq_sndr ++ */ ++void *init_rsq_sndr(void* rqbuf, unsigned int size, unsigned int oobsize, char *name, int datatype) ++{ ++ reservoir_t *rvr; ++ rsq_t *prsq; ++ ++ if (rqbuf == NULL || size == 0 || _rsqid_ == -1) ++ return NULL; ++ /* share memory needs locate at 4K boundary */ ++ rvr = (reservoir_t*)ALIGN4K(rqbuf); ++ rvr->size = size - ((u32)rvr - (u32)rqbuf); ++ if (rvr->size < (SIZEOF_RESERVIOR + oobsize)) ++ return NULL; ++ rvr->me = rvr; ++ rvr->slotno = 0; ++ rvr->headno = 0; ++ rvr->dropcnt = 0; ++ rvr->dropfrms = 0; ++ rvr->corrfrms = 0; ++ rvr->sloterr = 0; ++ rvr->synccnt = 0; ++ rvr->resetcnt = 0; ++ rvr->datatype = datatype; ++ rvr->iid = 8 - __builtin_clz(_rsqid_); ++ _rsqid_ |= (1 << (24 + rvr->iid)); ++ memset(rvr->name, 0, sizeof(rvr->name)); ++ strncpy(rvr->name, name, sizeof(rvr->name) - 1); ++ init_rlink(&(rvr->link)); ++ /* init ring buffer */ ++ prsq = &(rvr->rsq); ++ prsq->woff = 0; ++ prsq->sndr_sbuf = (unsigned char*)rvr + SIZEOF_RESERVIOR; ++ prsq->sndr_end = (unsigned char*)rvr + rvr->size; ++ prsq->sndr_oob = prsq->sndr_end - oobsize; ++ /* init write and read pointer */ ++ prsq->sndr_wp = prsq->sndr_sbuf; ++ prsq->sndr_rp = prsq->sndr_sbuf; ++ ++ prsq->wrno = ++ prsq->rdno = rvr->slotno; ++ prsq->head = ++ prsq->tail = NULL; ++ return rvr; ++} ++ ++#define SNDR_2_RCVR_PTR(prsq, sp) (typeof(sp))((sp) + (prsq)->woff) ++#define RCVR_2_SNDR_PTR(prsq, rp) (typeof(rp))((rp) - (prsq)->woff) ++ ++void init_rsq_rcvr(reservoir_t *rvr) ++{ ++ rsq_t *prsq; ++ ++ prsq = &(rvr->rsq); ++ prsq->woff = (void*)rvr - (void*)rvr->me; ++ ++ prsq->rcvr_sbuf = SNDR_2_RCVR_PTR(prsq, prsq->sndr_sbuf); ++ prsq->rcvr_wp = SNDR_2_RCVR_PTR(prsq, prsq->sndr_wp); ++ prsq->rcvr_rp = SNDR_2_RCVR_PTR(prsq, prsq->sndr_rp); ++ prsq->rcvr_oob = SNDR_2_RCVR_PTR(prsq, prsq->sndr_oob); ++ prsq->rcvr_end = SNDR_2_RCVR_PTR(prsq, prsq->sndr_end); ++} ++ ++void reset_rsq(reservoir_t *rvr) ++{ ++ rsq_t *prsq; ++ slot_t *slot; ++ ++ prsq = &(rvr->rsq); ++ prsq->head = ++ prsq->tail = NULL; ++ ++ /* init write and read pointer */ ++ prsq->sndr_wp = prsq->sndr_sbuf; ++ prsq->sndr_rp = prsq->sndr_sbuf; ++ prsq->wrno = ++ prsq->rdno = rvr->slotno; ++ ++ /* init sequeuce slot queue */ ++ slot = (slot_t*)prsq->sndr_wp; ++ slot->tag = 0; ++ rvr->resetcnt++; ++} ++ ++unsigned int check_rsqslot(reservoir_t *rvr, unsigned int expect) ++{ ++ rsq_t *prsq; ++ unsigned int nws; ++ unsigned char *rp; ++ unsigned char *ptr; ++ ++ if (!rvr) ++ return 0; ++ Chip_Inv_Cache_Range((unsigned long)rvr, sizeof(reservoir_t)); ++ prsq = &(rvr->rsq); ++ ++ rp = prsq->sndr_rp; ++ ptr = prsq->sndr_wp; ++ ++ /* need total written size */ ++ nws = SIZEOF_SLOTHEADER + expect; ++ ++ if ((ptr <= rp) && (prsq->rdno != prsq->wrno) && ((rp - ptr) < nws)) ++ return 0; //full ++ else ++ return 1; //available ++} ++ ++unsigned int gc_rsqslot(reservoir_t *rvr, unsigned int expect) ++{ ++ rsq_t *prsq; ++ slot_t *slot; ++ unsigned int nws; ++ unsigned char *rp; ++ unsigned char *ptr; ++ unsigned char *p; ++ unsigned char *pns; ++ ++ if (!rvr) ++ return 0; ++ Chip_Inv_Cache_Range((unsigned long)rvr, sizeof(reservoir_t)); ++ prsq = &(rvr->rsq); ++ ++ rp = prsq->sndr_rp; ++ ptr = prsq->sndr_wp; ++ ++ /* need total written size */ ++ nws = SIZEOF_SLOTHEADER + expect; ++ slot = (slot_t*)rp; ++ ++ if ((ptr <= rp) && (prsq->rdno != prsq->wrno) && ((rp - ptr) < nws)) { ++ /* |-------WsssssRss----O----------| */ ++ /* sbuf ptr oob */ ++ /* FULL!! TODO: drop a group slots */ ++ unsigned int df = 0; ++ rvr->dropcnt++; ++ do { ++ slot_t *s = (slot_t*)(prsq->sndr_rp); ++ ++ p = rp + SIZEOF_SLOTHEADER + slot->bs; ++ if (p >= prsq->sndr_oob) { ++ /* |--R---------------WdOddddp-----| */ ++ /* data in oob, wrap to head of buffer*/ ++ pns = prsq->sndr_sbuf; ++ } else { ++ /* |--R--------Wddddp-R-O----------| */ ++ pns = p; ++ } ++ ++ rp = prsq->sndr_rp = pns; ++ slot = (slot_t*)rp; ++ /* for check only */ ++ if (slot->tag != RQ_TAG) { ++ CamOsPrintf(KERN_ERR "DO DROP 0x%x mark %d to 0x%x %s\n", ++ (unsigned int)s, s->mark, (unsigned int)prsq->sndr_rp, ++ slot->tag == RQ_TAG? "OK" : "BAD"); ++ } ++ ++ df += (slot->no - s->no); ++ prsq->rdno = ++ rvr->headno = slot->no; /* oldest no. in rvr */ ++ ++ if (ptr >= rp || (rp - ptr) >= nws) { ++ rvr->dropfrms += df; ++ break; ++ } ++ // CamOsPrintf(KERN_ERR "%s %d new - rp %x\n", __FUNCTION__, __LINE__, (unsigned int)prsq->rp); ++ } while (1); ++ } ++ ++ // flush to physical storage ++ Chip_Flush_Cache_Range((unsigned long)rvr, sizeof(reservoir_t)); ++ ++ return 1; ++} ++ ++void *begin_rsqslot(reservoir_t *rvr, unsigned int expect) ++{ ++ rsq_t *prsq; ++ slot_t *slot; ++ unsigned char *ptr; ++ ++ if (!rvr) ++ return NULL; ++ Chip_Inv_Cache_Range((unsigned long)rvr, sizeof(reservoir_t)); ++ prsq = &(rvr->rsq); ++ ++ ptr = prsq->sndr_wp; ++ ++ slot = (slot_t*)(prsq->sndr_wp); ++ Chip_Inv_Cache_Range((unsigned long)slot, sizeof(slot_t)); ++ slot->rese = rvr; ++ Chip_Flush_Cache_Range((unsigned long)slot, sizeof(slot_t)); ++ /* |-------Wssssssss-R--O----------| */ ++ /* sbuf ptr ^ oob end */ ++ ++ /* |----R---Wsssssss----O----------| */ ++ /* sbuf ^ ptr oob end */ ++ ptr += SIZEOF_SLOTHEADER; ++ ++ return ptr; ++} ++ ++/* trim slot size after data in el */ ++unsigned int end_rsqslot(void* wp, unsigned int ws, unsigned int mark, unsigned int ts) ++{ ++ reservoir_t *rvr; ++ rsq_t *prsq; ++ slot_t *slot; ++ unsigned char *ptr; ++ ++ if (!wp) return 0; ++ ptr = wp; ++ slot = (slot_t*)(ptr - SIZEOF_SLOTHEADER); ++ ++ Chip_Inv_Cache_Range((unsigned long)slot, sizeof(slot_t)); ++ rvr = slot->rese; ++ Chip_Inv_Cache_Range((unsigned long)rvr, sizeof(reservoir_t)); ++ prsq = &(rvr->rsq); ++ ++ /* for debug/verify only */ ++ if ((void*)slot != prsq->sndr_wp) { ++ /* wp is invalid */ ++ CamOsPrintf(KERN_ERR "ERROR: %s %d\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ slot->tag = RQ_TAG; /* a tag for allocated */ ++ slot->no = rvr->slotno; ++ slot->dc = ws; /* real size of data */ ++ slot->bs = ALIGN32(ws); /* the slot allocated size */ ++ slot->sc = SIZEOF_SLOTHEADER; /* slot header size */ ++ slot->next = NULL; ++ slot->mark = mark; ++ slot->ts = ts; ++ ptr += slot->bs; /* move write pointer for next writting */ ++ if (/* this is made sure by begin_rsqslot() */ ++ /* (prsq->sndr_wp < prsq->sndr_rp && ptr > prsq->sndr_rp) || */ ++ (ptr > prsq->sndr_end)) { ++ /* |-----------WdddRddp-O----------| */ ++ /* |----------------WdddOdddddddddddp */ ++ /* overwrite!! */ ++ /* TODO: expect in begin_rsqslot too small !! */ ++ CamOsPrintf(KERN_ERR "%s %d RSQ OVERWRITE!!\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ /* update write pointer */ ++ if (ptr >= prsq->sndr_oob) { ++ /* |--R---------------WdOddddp-----| */ ++ /* data in oob, wrap to head of buffer*/ ++ prsq->sndr_wp = prsq->sndr_sbuf; ++ } else { ++ /* |--R--------Wddddp-R-O----------| */ ++ prsq->sndr_wp = ptr; ++ } ++ ++ prsq->wrno = slot->no + 1; ++ rvr->slotno++; ++ // flush to pyhsical storage ++ Chip_Flush_Cache_Range((unsigned long)rvr, sizeof(reservoir_t)); ++ Chip_Flush_Cache_Range((unsigned long)slot, sizeof(slot_t)); ++ return ws; ++} ++ ++/* ++ * rvr should be a noncache port (device memory) ++ */ ++unsigned int rcvr_de_rsqslot(reservoir_t *rvr, void *buf, unsigned int size, slot_t *out) ++{ ++ rsq_t *prsq; ++ unsigned char *rp; ++ ++ prsq = &(rvr->rsq); ++ ++ /* sync with sender */ ++ prsq->rcvr_rp = SNDR_2_RCVR_PTR(prsq, prsq->sndr_rp); ++ ++ if (prsq->rdno == prsq->wrno) { ++ out->buf = prsq->rcvr_sbuf + out->sc; ++ return 0; //empty!! ++ } ++ ++ memcpy(out, prsq->rcvr_rp, sizeof(slot_t)); ++ rp = prsq->rcvr_rp + out->sc; ++ ++ /* for debuging, can remove!! */ ++ if (out->tag != RQ_TAG) { ++ // CamOsPrintf(KERN_ERR "Not Slot header 0x%08x\n", (int)prsq->rp); ++ rvr->sloterr++; ++ out->buf = NULL; ++ return 0; ++ } ++ ++ if (buf && size > out->dc) { ++ /* enough to copy */ ++ memcpy(buf, rp, out->dc); ++ rp += out->bs; ++ prsq->rcvr_rp = (rp >= prsq->rcvr_oob) ? prsq->rcvr_sbuf : rp; ++ ++ /* sync with sender */ ++ prsq->sndr_rp = RCVR_2_SNDR_PTR(prsq, prsq->rcvr_rp); ++ } else { ++ CamOsPrintf(KERN_ERR "buffer size %x is less than data size %x\n", size, out->dc); ++ return 0; ++ } ++ ++ prsq->rdno = out->no + 1; ++ ++ return out->dc; ++} ++ ++/* ++ * rvr should be a noncache port (device memory) ++ */ ++unsigned int sndr_de_rsqslot(reservoir_t *rvr, void *buf, unsigned int size, slot_t *out) ++{ ++ rsq_t *prsq; ++ unsigned char *rp; ++ ++ prsq = &(rvr->rsq); ++ ++ if (prsq->rdno == prsq->wrno) { ++ out->buf = prsq->sndr_sbuf + out->sc; ++ return 0; //empty!! ++ } ++ ++ memcpy(out, prsq->sndr_rp, sizeof(slot_t)); ++ rp = prsq->sndr_rp + out->sc; ++ ++ /* for debuging, can remove!! */ ++ if (out->tag != RQ_TAG) { ++ // CamOsPrintf(KERN_ERR "Not Slot header 0x%08x\n", (int)prsq->rp); ++ rvr->sloterr++; ++ out->buf = NULL; ++ return 0; ++ } ++ ++ if (buf && size > out->dc) { ++ /* enough to copy */ ++ memcpy(buf, rp, out->dc); ++ rp += out->bs; ++ prsq->sndr_rp = (rp >= prsq->sndr_oob) ? prsq->sndr_sbuf : rp; ++ ++ /* sync with receiver */ ++ prsq->rcvr_rp = RCVR_2_SNDR_PTR(prsq, prsq->sndr_rp); ++ } else { ++ CamOsPrintf(KERN_ERR "buffer size %x is less than data size %x\n", size, out->dc); ++ return 0; ++ } ++ ++ prsq->rdno = out->no + 1; ++ ++ return out->dc; ++} ++ ++slot_t *get_rsqslot(void *databuf) ++{ ++ slot_t* slot; ++ ++ slot = (slot_t*)((unsigned char*)databuf - SIZEOF_SLOTHEADER); ++ if (slot->tag == RQ_TAG) ++ return slot; ++ return NULL; ++} +diff --git a/drivers/sstar/dualos/rsq.h b/drivers/sstar/dualos/rsq.h +new file mode 100755 +index 000000000000..f571f6d37f77 +--- /dev/null ++++ b/drivers/sstar/dualos/rsq.h +@@ -0,0 +1,130 @@ ++/* ++* rsq.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Canlet.Lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * rq.h ++ * ring queue header ++ */ ++#ifndef __RSQ_H__ ++#define __RSQ_H__ ++ ++#include "rlink.h" ++ ++typedef struct _slot_t { ++ unsigned int tag; /* for check */ ++ unsigned int no; ++ unsigned int sc; /* slot size */ ++ unsigned int dc; /* data size */ ++ unsigned int bs; /* size of buffer allocated */ ++ unsigned int mark; /* for groupping */ ++ unsigned int ts; /* time stamp */ ++ void *rese; ++ void *buf; /* data address */ ++ unsigned int wrap; /* wrapping */ ++ struct _slot_t *next; /* link */ ++} slot_t; ++ ++typedef struct ghost_slot_t { ++ slot_t copy; ++ slot_t *ghost; ++} gslot_t; ++ ++typedef struct _rsq_t { ++ unsigned char *sndr_sbuf; ++ unsigned char *sndr_oob; /* out of bound */ ++ unsigned char *sndr_end; /* bottom of ring buffer */ ++ unsigned char *sndr_wp; ++ unsigned char *sndr_rp; ++ ++ unsigned char *rcvr_sbuf; ++ unsigned char *rcvr_oob; /* out of bound */ ++ unsigned char *rcvr_end; /* bottom of ring buffer */ ++ unsigned char *rcvr_wp; ++ unsigned char *rcvr_rp; ++ ++ unsigned int woff; ++ unsigned int reset_id; ++ unsigned int wrno; /* newest slot no */ ++ unsigned int rdno; /* read slot no */ ++ slot_t *head; /* oldest slot */ ++ slot_t *tail; /* newest slot */ ++} rsq_t; ++ ++#define RVR_NAME_SIZE (16) ++#define DATATYPE_VIDEO 0 ++#define DATATYPE_STILL 1 ++#define DATATYPE_AUDIO 2 ++#define DATATYPE_LOG 3 ++typedef struct _reservoir_ { ++ struct rlink_head link; // must be first ++ char name[RVR_NAME_SIZE]; ++ rsq_t rsq; ++ void *me; // for recognition. ++ int iid; ++ unsigned int size; ++ unsigned int slotno; // current written no. ++ unsigned int headno; // oldest no. after dropping. ++ unsigned int dropcnt; ++ unsigned int dropfrms; ++ unsigned int sloterr; ++ unsigned int corrfrms; // corrupted frames ++ unsigned int synccnt; ++ unsigned int resetcnt; ++ unsigned int timestamp; // last update ++ int datatype; // video stream or still data ++ void *ext; ++} reservoir_t; ++ ++#define RQ_ALIGN(s) ((((u32)(a) + 15) >> 4) << 4) ++#define ALIGN32(s) ((((u32)(s) + 31) >> 5) << 5) ++#define ALIGN4K(s) ((((u32)(s) + 4095) >> 12) << 12) ++#define SIZEOF_RESERVIOR (((sizeof(reservoir_t) + 4095) >> 12) << 12) ++#define SIZEOF_SLOTHEADER ALIGN32(sizeof(slot_t)) ++#define SIZEOF_RVR_HEADER (SIZEOF_RESERVIOR + SIZEOF_SLOTHEADER) ++#define SIZEOF_RSQ (1024) ++#define RSQ_VIDEO0 0 ++#define RSQ_AUDIO0 80 ++ ++/* */ ++void *get_rvr(int HANDLE); ++void set_rvrint(int en); ++int get_rvrint(void); ++void corrupted_frame(void *p); ++void cnt_rsqerr(void *p); ++ ++/* rtk functions */ ++void add_rsqstream(void*, unsigned int size); /* should be struct rlink* */ ++/* rsq functions */ ++void *init_rsq_sndr(void *rqbuf, unsigned int size, unsigned int oobsize, char *name, int datatype); ++void init_rsq_rcvr(reservoir_t *rvr); ++/* slot/oob functions */ ++unsigned int check_rsqslot(reservoir_t *rvr, unsigned int expect); ++unsigned int gc_rsqslot(reservoir_t *rvr, unsigned int expect); ++void *begin_rsqslot(reservoir_t *rvr, unsigned int expect); ++unsigned int end_rsqslot(void* wp, unsigned int ws, unsigned int mark, unsigned int ts); ++unsigned int rcvr_de_rsqslot(reservoir_t *rvr, void *buf, unsigned int size, slot_t *out); ++unsigned int sndr_de_rsqslot(reservoir_t *rvr, void *buf, unsigned int size, slot_t *out); ++slot_t *get_rsqslot(void *databuf); ++ ++#define IPI_LINUX_USED 8 ++static inline int sgi_rsqslot(void *p) ++{ ++ reservoir_t *rvr = (reservoir_t*)p; ++ return rvr->iid + IPI_LINUX_USED; ++} ++ ++#endif // __RSQ_H__ +diff --git a/drivers/sstar/dualos/sw_sem.c b/drivers/sstar/dualos/sw_sem.c +new file mode 100755 +index 000000000000..748f3ff1458f +--- /dev/null ++++ b/drivers/sstar/dualos/sw_sem.c +@@ -0,0 +1,42 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#include "sw_sem.h" ++ ++static intercore_sem_t *intercore_sem; ++ ++void intercore_sem_init(unsigned int addr) ++{ ++ intercore_sem = (intercore_sem_t *)(addr); ++} ++ ++void intercore_sem_lock(void) ++{ ++ volatile char *p, *q; ++ intercore_sem->nesting++; ++ if (intercore_sem->nesting != 1) { ++ //printk("Nesting %d\n", intercore_sem->nesting); ++ } ++ intercore_sem->flag[CORE1] = 1; ++ intercore_sem->turn = CORE0; ++ q = &intercore_sem->flag[CORE0]; ++ p = &intercore_sem->turn; ++ while (*q == 1 && *p == 0) ; ++} ++ ++void intercore_sem_unlock(void) ++{ ++ intercore_sem->nesting--; ++ intercore_sem->flag[CORE1] = 0; ++} +diff --git a/drivers/sstar/dualos/sw_sem.h b/drivers/sstar/dualos/sw_sem.h +new file mode 100755 +index 000000000000..5f1ec9ead610 +--- /dev/null ++++ b/drivers/sstar/dualos/sw_sem.h +@@ -0,0 +1,45 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++/* for RTK2_DISABLE_K()/RTK2_ENABLE_K() */ ++//#include "rtkincl.h" ++ ++#define AMP_OS_CS_INIT() unsigned long cpu_sr = 0 ++#define AMP_OS_CS_ENTER() local_irq_save(cpu_sr) ++#define AMP_OS_CS_EXIT() local_irq_restore(cpu_sr) ++ ++#define AMP_CORE_LOCK() intercore_sem_lock() ++#define AMP_CORE_UNLOCK() intercore_sem_unlock() ++ ++#define AMP_LOCK_INIT() AMP_OS_CS_INIT() ++ ++#define AMP_LOCK() AMP_OS_CS_ENTER(); \ ++ AMP_CORE_LOCK() ++ ++#define AMP_UNLOCK() AMP_CORE_UNLOCK(); \ ++ AMP_OS_CS_EXIT() ++ ++#define CORE0 (0) ++#define CORE1 (1) ++ ++typedef struct ++{ ++ char flag[2]; ++ char turn; ++ char nesting; ++} intercore_sem_t; ++ ++void intercore_sem_init(unsigned int addr); ++void intercore_sem_lock(void); ++void intercore_sem_unlock(void); +diff --git a/drivers/sstar/emac/Kconfig b/drivers/sstar/emac/Kconfig +new file mode 100755 +index 000000000000..8ad7a07e5efe +--- /dev/null ++++ b/drivers/sstar/emac/Kconfig +@@ -0,0 +1,58 @@ ++config MS_EMAC ++select NET ++select NET_ETHERNET ++select MII ++select PACKET ++select USE_POLICY_FWD ++select INET ++select NETDEVICES ++ ++tristate "EMAC" ++default n ++ ++---help--- ++Enable compilation option for driver EMAC ++ ++if MS_EMAC ++config EMAC_SUPPLY_RNG ++bool "Supply to random number generator device" ++default n ++help ++ Supply to random number generator device ++ ++config MSTAR_HW_TX_CHECKSUM ++bool "Supply to hardware TX checksum" ++default n ++help ++ Supply to hardware TX checksum ++ ++config K3_RX_SWPATCH ++bool "Supply to K3 RX SW Patch" ++default n ++help ++ Supply to K3 RX frame drop due to padding 4 bytes issue ++ ++config DISCONNECT_DELAY_S ++int "Disconnect delay in second" ++default 1 ++help ++ Disconnect delay in second ++ ++config MSTAR_EEE ++bool "Supply to EEE function" ++default n ++help ++ Supply to EEE function ++ ++config EMAC_PHY_RESTART_AN ++bool "Supply to phy restart AN" ++default n ++help ++ Supply to phy restart AN ++ ++config EMAC_DPHY_REINIT ++bool "Supply to digital phy reinit" ++default n ++help ++ Supply to digital phy reinit ++endif +diff --git a/drivers/sstar/emac/Makefile b/drivers/sstar/emac/Makefile +new file mode 100755 +index 000000000000..37c55218ba04 +--- /dev/null ++++ b/drivers/sstar/emac/Makefile +@@ -0,0 +1,21 @@ ++# ++# Makefile for MStar EMAC device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/emac ++EXTRA_CFLAGS += -Idrivers/sstar/emac/hal/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++EXTRA_CFLAGS += -Idrivers/sstar/bdma/ ++ ++EXTRA_CFLAGS += -DKERNEL_PHY=1 ++ ++# specific options ++# EXTRA_CFLAGS += -DRED_LION ++# files ++obj-$(CONFIG_MS_EMAC) := kdrv_emac.o ++kdrv_emac-y := mdrv_emac.o ++kdrv_emac-y += hal/$(CONFIG_SSTAR_CHIP_NAME)/mhal_emac.o +\ No newline at end of file +diff --git a/drivers/sstar/emac/hal/infinity2/mhal_emac.c b/drivers/sstar/emac/hal/infinity2/mhal_emac.c +new file mode 100755 +index 000000000000..39b117808cd8 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity2/mhal_emac.c +@@ -0,0 +1,2511 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++// #define TX_QUEUE_SIZE_NEW (127) ++// #define TX_QUEUE_CNT_SCHE (0) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++//#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++//#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++//#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++//#define JULIAN_104_VAL (0x30010000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u8, u32); ++ int (*phy_read)(void*, u8, u8, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u8 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u8 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u8 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u8 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++#define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ if (PHY_INTERFACE_MODE_RMII != pHal->phy_mode) ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#ifdef RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ #if 0 ++ int num_parents, i; ++ ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++#endif ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if 0 ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00);/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++// _MHal_EMAC_Clk(hal, 1); ++#endif ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++//#if (TX_QUEUE_SIZE != 4) ++// mhal_emac_t* pHal = (mhal_emac_t*) hal; ++// u8 xval; ++// xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++// xval = (xval&(~BIT7)) | BIT7; ++// MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++//#else ++// hal = hal; ++//#endif ++} ++ ++int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++ ++//#if (TX_QUEUE_CNT_SCHE == 3) ++// { ++// mhal_emac_t* pHal = (mhal_emac_t*) hal; ++// u8 xval; ++// xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++// xval |= (0x1 << 4); ++// MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++// } ++//#endif ++ ++//#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++// { ++// /*patch:*/ ++// int i=0, ertry=0; ++// u8 read_val, xval; ++// mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++// xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++// do ++// { ++// read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++// if(xval==read_val) ++// { ++// i++; ++// }else ++// { ++// i=0; ++// xval = read_val; ++// ertry++; ++// } ++// }while(i<2); ++// return xval; ++// } ++//#endif ++//#if (2 == TX_QUEUE_CNT_SCHE) ++// int xval; ++// mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++// xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++// xval |= TXQUEUE_CNT_LATCH; ++// MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++// xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++// return xval; ++//#endif ++ ++ hal = hal; ++ printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++// return TX_QUEUE_SIZE; ++ return 0; ++} ++ ++static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret=0; ++//#if (4 == TX_QUEUE_SIZE) ++// ret = MHal_EMAC_QueueFree_4(hal); ++//#elif (1 == TX_QUEUE_CNT_SCHE) ++// ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++//#else ++// #if TX_QUEUE_SIZE_NEW ++// ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++// #else ++// ret = MHal_EMAC_QueueFree_4(hal); ++// #endif ++//#endif ++ ++ printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return ret; ++} ++ ++static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret=0; ++ ++//#if (4 == TX_QUEUE_SIZE) ++// ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++//#elif (1 == TX_QUEUE_CNT_SCHE) ++// ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++//#else ++// ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++//#endif ++ printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return ret; ++} ++ ++static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u8 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u8 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u8 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u8 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} +diff --git a/drivers/sstar/emac/hal/infinity2/mhal_emac.h b/drivers/sstar/emac/hal/infinity2/mhal_emac.h +new file mode 100755 +index 000000000000..73293a566649 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity2/mhal_emac.h +@@ -0,0 +1,476 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ( "MStar Confidential Information" ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file EMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief EMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_EMAC__ ++#define __DRV_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++//#define RX_CHECKSUM ++#define CHIP_FLUSH_READ ++//#define LAN_ESD_CARRIER_INTERRUPT ++//#define SOFTWARE_TX_FLOW_CONTROL ++//#define HARDWARE_DISCONNECT_DELAY ++//#define DISABLE_SOFTWARE_LED ++/*** RX Configuration ***/ ++#define INT_JULIAN_D ++//#define ISR_BOTTOM_HALF ++//#define MSTAR_EMAC_NAPI ++#define RX_ZERO_COPY ++ ++/*** TX Configuration ***/ ++#define TX_QUEUE_4 ++//#define TX_SOFTWARE_QUEUE ++#define TX_SKB_PTR ++//#define TX_SW_QUEUE ++//#define NEW_TX_QUEUE_128 //I3E new ++//#define NEW_TX_QUEUE_INTERRUPT_THRESHOLD //I3E new ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++ ++#if defined (TX_QUEUE_4) ++#if defined(NEW_TX_QUEUE_128) ++#define NEW_TX_QUEUE_SIZE (127) //max is 0xffffff ++#define TX_RING_SIZE (NEW_TX_QUEUE_SIZE+4) ++#else ++#define TX_RING_SIZE (4) //effected size = TX_RING_SIZE - 1 ++#endif ++#else ++#define TX_RING_SIZE (2) //effected size = TX_RING_SIZE - 1 ++#endif ++ ++#ifdef TX_SW_QUEUE ++#define TX_SW_QUEUE_SIZE (256) //effected size = TX_RING_SIZE - 1 ++#define TX_DESC_CLEARED 0 ++#define TX_DESC_WROTE 1 ++#define TX_DESC_READ 2 ++#define TX_FIFO_SIZE TX_RING_SIZE //HW FIFO size ++#endif ++ ++ ++ ++ ++// Compiler Switches ++#define REG_BIT_MAP ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_EMAC0 0x0 //0x1020 ++#define REG_BANK_EMAC1 0x1 //0x1021 ++//#define REG_BACK_EMAC2 0x1512 //0x1022 ++//#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A21 ++//#define REG_BANK_X32_EMAC2 0x1A1F ++//#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#define REG_BANK_PMSLEEP 0x000E ++ ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++#define EMAC_SPEED_10 10 ++#define EMAC_SPEED_100 100 ++ ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++#define EMAC_MAX_TX_QUEUE 1000 ++ ++// Base address here: ++#define MIU0_BUS_BASE 0x20000000 ++#define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#define RBQP_LENG 0x100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/hal/infinity2m/mhal_emac.c b/drivers/sstar/emac/hal/infinity2m/mhal_emac.c +new file mode 100755 +index 000000000000..eb5c50b95cb7 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity2m/mhal_emac.c +@@ -0,0 +1,2620 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Pipe_Line_Delay(void* hal, int enable) ++{ ++ u32 j100; //1511 0x00 bit[5:4], default h01 ++ u32 j146; //1511 0x23 bit[15], default h1 ++ ++ if(enable) ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 |= PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 |= EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++ else ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 &= ~PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 &= ~EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++} ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 1); ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ ++ // PATCH for rx receive 256 byte packet only SPEED_10 ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 0); ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++#ifndef CONFIG_CAM_CLK ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x66, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x67, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x68, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x69, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x66, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x67, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x68, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x69, 0x01); ++ } ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++#endif ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#ifndef CONFIG_CAM_CLK ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++ // workaround for clock gen support no clock selection ++ if (PHY_INTERFACE_MODE_RMII == pHal->phy_mode) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x66, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x67, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x68, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x69, 0x00); ++ } ++ ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++#endif ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++#endif ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++#define INTERNAL_MDIO_ADDR 0 ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++/* ++ if (0 != phy_addr) ++ return -1; ++*/ ++ if (INTERNAL_MDIO_ADDR != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++/* ++ if (0 != phy_addr) ++ return 0xffff; ++*/ ++ if (INTERNAL_MDIO_ADDR != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} +diff --git a/drivers/sstar/emac/hal/infinity2m/mhal_emac.h b/drivers/sstar/emac/hal/infinity2m/mhal_emac.h +new file mode 100755 +index 000000000000..a9d2ccc877c7 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity2m/mhal_emac.h +@@ -0,0 +1,502 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/hal/infinity3/mhal_emac.c b/drivers/sstar/emac/hal/infinity3/mhal_emac.c +new file mode 100755 +index 000000000000..bf8c7fce7f5d +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity3/mhal_emac.c +@@ -0,0 +1,2500 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (0) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x30010000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u8, u32); ++ int (*phy_read)(void*, u8, u8, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u8 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u8 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u8 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u8 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ if (PHY_INTERFACE_MODE_RMII != pHal->phy_mode) ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#ifdef RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++ ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#endif ++ return ret; ++} ++ ++static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u8 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u8 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u8 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u8 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} +diff --git a/drivers/sstar/emac/hal/infinity3/mhal_emac.h b/drivers/sstar/emac/hal/infinity3/mhal_emac.h +new file mode 100755 +index 000000000000..8fcfd35185da +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity3/mhal_emac.h +@@ -0,0 +1,496 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/hal/infinity5/mhal_emac.c b/drivers/sstar/emac/hal/infinity5/mhal_emac.c +new file mode 100755 +index 000000000000..ec8dd8b3a5e5 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity5/mhal_emac.c +@@ -0,0 +1,2592 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (63) ++ #define TX_QUEUE_CNT_SCHE (1) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (1) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Pipe_Line_Delay(void* hal, int enable) ++{ ++ u32 j100; //1511 0x00 bit[5:4], default h01 ++ u32 j146; //1511 0x23 bit[15], default h1 ++ ++ if(enable) ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 |= PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 |= EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++ else ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 &= ~PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 &= ~EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++} ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++// #if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++// #endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 1); ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ ++ // PATCH for rx receive 256 byte packet only SPEED_10 ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 0); ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++#ifndef CONFIG_CAM_CLK ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++#endif ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#ifndef CONFIG_CAM_CLK ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++#endif ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++#endif ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} +diff --git a/drivers/sstar/emac/hal/infinity5/mhal_emac.h b/drivers/sstar/emac/hal/infinity5/mhal_emac.h +new file mode 100755 +index 000000000000..a9d2ccc877c7 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity5/mhal_emac.h +@@ -0,0 +1,502 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/hal/infinity6/mhal_emac.c b/drivers/sstar/emac/hal/infinity6/mhal_emac.c +new file mode 100755 +index 000000000000..a5559681057b +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity6/mhal_emac.c +@@ -0,0 +1,2604 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Pipe_Line_Delay(void* hal, int enable) ++{ ++ u32 j100; //1511 0x00 bit[5:4], default h01 ++ u32 j146; //1511 0x23 bit[15], default h1 ++ ++ if(enable) ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 |= PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 |= EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++ else ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 &= ~PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 &= ~EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++} ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 1); ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ ++ // PATCH for rx receive 256 byte packet only SPEED_10 ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 0); ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++#ifndef CONFIG_CAM_CLK ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++#endif ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#ifndef CONFIG_CAM_CLK ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++#endif ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++#endif ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} ++ ++void MHal_EMAC_Phy_Restart_An(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->phyRIU, REG_BANK_ALBANY0, 0x00, 0x0000); ++ udelay( 1 ); ++ MHal_EMAC_WritReg16(pHal->phyRIU, REG_BANK_ALBANY0, 0x00, 0x1000); ++} +\ No newline at end of file +diff --git a/drivers/sstar/emac/hal/infinity6/mhal_emac.h b/drivers/sstar/emac/hal/infinity6/mhal_emac.h +new file mode 100755 +index 000000000000..2183fae351d7 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity6/mhal_emac.h +@@ -0,0 +1,504 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/hal/infinity6b0/mhal_emac.c b/drivers/sstar/emac/hal/infinity6b0/mhal_emac.c +new file mode 100755 +index 000000000000..7744d425aac8 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity6b0/mhal_emac.c +@@ -0,0 +1,2655 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//#define FPGA_PADMUX_PORTED ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++#ifdef CONFIG_EMAC_DPHY_REINIT ++static int _MHal_EMAC_DPHY_REINIT(void* hal); ++#endif ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_EMAC_DPHY_REINIT ++int old_speed = 0; ++int old_duplex = 0; ++#endif ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ //if (PHY_INTERFACE_MODE_RMII != pHal->phy_mode) //for Realtek ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Pipe_Line_Delay(void* hal, int enable) ++{ ++ u32 j100; //1511 0x00 bit[5:4], default h01 ++ u32 j146; //1511 0x23 bit[15], default h1 ++ ++ if(enable) ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 |= PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 |= EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++ else ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 &= ~PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 &= ~EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++} ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++#ifdef CONFIG_EMAC_DPHY_REINIT ++static int _MHal_EMAC_DPHY_REINIT(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal_04; ++ ++ uRegVal_04 = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04); ++ uRegVal_04 = uRegVal_04 | 0x08; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, uRegVal_04); //1515 02 ++ mdelay(1); ++ uRegVal_04 = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04); ++ uRegVal_04 = uRegVal_04 & ~0x08; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, uRegVal_04); //1515 02 ++ mdelay(100); ++ printk("[EMAC] EMAC_DPHY_REINIT \n"); ++ return 0; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++#ifdef CONFIG_EMAC_DPHY_REINIT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#endif ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 1); ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ ++ // PATCH for rx receive 256 byte packet only SPEED_10 ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 0); ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++ ++ printk("[%s] speed: %d , duplex: %d\n",__FUNCTION__, speed, duplex); ++ ++#ifdef CONFIG_EMAC_DPHY_REINIT ++ if( ((old_speed != speed)||(old_duplex != duplex)) && (pHal->phy_mode!=PHY_INTERFACE_MODE_RMII) ) ++ { ++ _MHal_EMAC_DPHY_REINIT(hal); ++ } ++ old_speed = speed; ++ old_duplex = duplex; ++#endif ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++#ifndef CONFIG_CAM_CLK ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); //[2]:0 clk_emac_rx_in 0x4 clk emac ref / 2 ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); //[2]:0 clk_emac_tx_in 0x4 clk emac ref / 2 ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++#endif ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#ifndef CONFIG_CAM_CLK ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++ ++ if (PHY_INTERFACE_MODE_RMII == pHal->phy_mode) ++ { ++ // workaround for clock gen support no clock selection ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ ++ } ++ ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++#endif ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++#endif ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #if defined(CONFIG_MS_PADMUX) && defined(FPGA_PADMUX_PORTED) ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #if defined(CONFIG_MS_PADMUX) && defined(FPGA_PADMUX_PORTED) ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if defined(CONFIG_MS_PADMUX) && defined(FPGA_PADMUX_PORTED) ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} ++ ++void MHal_EMAC_Phy_Restart_An(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->phyRIU, REG_BANK_ALBANY0, 0x00, 0x0000); ++ udelay( 1 ); ++ MHal_EMAC_WritReg16(pHal->phyRIU, REG_BANK_ALBANY0, 0x00, 0x1000); ++} +\ No newline at end of file +diff --git a/drivers/sstar/emac/hal/infinity6b0/mhal_emac.h b/drivers/sstar/emac/hal/infinity6b0/mhal_emac.h +new file mode 100755 +index 000000000000..2183fae351d7 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity6b0/mhal_emac.h +@@ -0,0 +1,504 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/hal/infinity6e/mhal_emac.c b/drivers/sstar/emac/hal/infinity6e/mhal_emac.c +new file mode 100755 +index 000000000000..1051f26f832a +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity6e/mhal_emac.c +@@ -0,0 +1,2729 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "cam_os_wrapper.h" ++ ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++static int _MHal_EMAC_DPHY_REINIT(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ // val = (val_h & 0xFFFF0000) | val; ++ val = (val_h & 0xFFFF00C0) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Pipe_Line_Delay(void* hal, int enable) ++{ ++ u32 j100; //1511 0x00 bit[5:4], default h01 ++ u32 j146; //1511 0x23 bit[15], default h1 ++ ++ if(enable) ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 |= PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 |= EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++ else ++ { ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j100 &= ~PIPE_LINE_DELAY; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++ ++ j146 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0146); ++ j146 &= ~EMAC_PATCH_LOCK; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0146, j146); ++ } ++} ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++static int _MHal_EMAC_DPHY_REINIT(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ int i = 0; ++ u8 uRegVal_7E; ++ u8 uRegVal_A5; ++ u8 uRegVal_8C, uRegVal_8D; ++ s16 uRegVal_8x; ++ u8 uRegVal_04; ++ u8 cntGood = 0, cntBad = 0; ++ ++ for(i=0; i<200; i++) ++ { ++ mdelay(15); ++ uRegVal_7E = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x7E); //1515 3f ++ uRegVal_7E = uRegVal_7E & 0x0F; ++ uRegVal_A5 = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xA5); //1515 52 ++ uRegVal_A5 = uRegVal_A5 & 0x07; ++ ++ if(uRegVal_7E == 0x08 && uRegVal_A5 == 0x07) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x88, 0x00); //1515 44 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x60); ++ ++ uRegVal_8C = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8C); //1515 46 ++ uRegVal_8D = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8D); //1515 46 ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x88, 0x00); //1515 44 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ ++ uRegVal_8x = uRegVal_8D << 8 | uRegVal_8C; ++ if((uRegVal_8x & 0x0400) != 0) ++ uRegVal_8x = uRegVal_8x | 0xF800; ++ ++ if(uRegVal_8x > -64 && uRegVal_8x < 64) ++ { ++ cntGood++; ++ cntBad = 0; ++ if(cntGood > 5) ++ { ++ cntBad = 0; ++ cntGood = 0; ++ break; ++ } ++ mdelay(1); ++ } ++ else ++ { ++ cntBad++; ++ cntGood = 0; ++ if(cntBad > 5) ++ { ++ cntBad = 0; ++ cntGood = 0; ++ uRegVal_04 = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04); ++ uRegVal_04 = uRegVal_04 | 0x08; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, uRegVal_04); //1515 02 ++ mdelay(1); ++ uRegVal_04 = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04); ++ uRegVal_04 = uRegVal_04 & ~0x08; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, uRegVal_04); //1515 02 ++ mdelay(100); ++ } ++ mdelay(1); ++ } ++ } ++ } ++ ++ return i; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ ++ // ++ if((CamOsChipRevision()==0x1) && (pHal->phy_mode!=PHY_INTERFACE_MODE_RMII)) ++ { ++ int reinit_cnt; ++ reinit_cnt = _MHal_EMAC_DPHY_REINIT(hal); ++ //printk("[EMAC] DPHY retrain %d times \n", reinit_cnt); ++ } ++ ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 1); ++ ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ ++ // PATCH for rx receive 256 byte packet only SPEED_10 ++ MHal_EMAC_Set_Pipe_Line_Delay(hal, 0); ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++#ifndef CONFIG_CAM_CLK ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++#endif ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#ifndef CONFIG_CAM_CLK ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++ ++ if (PHY_INTERFACE_MODE_RMII == pHal->phy_mode) ++ { ++ // workaround for clock gen support no clock selection ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ ++ // workaround for padmux conflict ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PADTOP, 0xc0, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PADTOP, 0xc1, 0x00); ++ } ++ ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++#endif ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++#ifndef CONFIG_CAM_CLK ++ int num_parents, i; ++ struct clk **emac_clks; ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++#endif ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++#define INTERNAL_MDIO_ADDR 0 ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++/* ++ if (0 != phy_addr) ++ return -1; ++*/ ++ if (INTERNAL_MDIO_ADDR != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++/* ++ if (0 != phy_addr) ++ return 0xffff; ++*/ ++ if (INTERNAL_MDIO_ADDR != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++ //set scale factor of LMS & LPF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x10, 0x46); //1515 08 ++ ++ if(CamOsChipRevision() == 0x1) ++ { ++ //set scale factor of LMS & LPF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x10, 0x53); //1515 08 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x11, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x16, 0x00); //1515 0b ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x17, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x18, 0x00); //1515 0c ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x19, 0x10); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x1A, 0x00); //1515 0d ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x1B, 0x01); ++ } ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++void MHal_EMAC_MIU_Protect_RX(void* hal, u32 start, u32 end) ++{ ++ u32 j100, j11c, j120, j124; ++ ++ if ((0xF & start) || (0xF& end)) ++ { ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ printk("[%s][%d] warning for protection area without 16 byte alignment (start, end) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, start, end); ++ } ++ start >>= 4; ++ end >>= 4; ++ ++ j100 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ j11c = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_011C); ++ j120 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0120); ++ j124 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0124); ++ ++ j11c = ((j11c & 0x0000ffff) | ((end & 0x0000ffff) << 16)); ++ j120 = ((j120 & 0x0000e000) | ((end & 0x1fff0000) >> 16) | ((start & 0x0000ffff) << 16) ); ++ j124 = ((j124 & 0xffffe000) | ((start & 0x1fff0000) >> 16) ); ++ j100 |= 0x40; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_011C, j11c); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0120, j120); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0124, j124); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, j100); ++} ++ ++void MHal_EMAC_Phy_Restart_An(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->phyRIU, REG_BANK_ALBANY0, 0x00, 0x0000); ++ udelay( 1 ); ++ MHal_EMAC_WritReg16(pHal->phyRIU, REG_BANK_ALBANY0, 0x00, 0x1000); ++} +\ No newline at end of file +diff --git a/drivers/sstar/emac/hal/infinity6e/mhal_emac.h b/drivers/sstar/emac/hal/infinity6e/mhal_emac.h +new file mode 100755 +index 000000000000..d3461d39f086 +--- /dev/null ++++ b/drivers/sstar/emac/hal/infinity6e/mhal_emac.h +@@ -0,0 +1,504 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++#define REG_BANK_PADTOP 0x103C ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac/mdrv_emac.c b/drivers/sstar/emac/mdrv_emac.c +new file mode 100755 +index 000000000000..c5b383e61e66 +--- /dev/null ++++ b/drivers/sstar/emac/mdrv_emac.c +@@ -0,0 +1,5413 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#endif ++ ++#include "mdrv_types.h" ++//#include "mst_platform.h" ++//#include "mdrv_system.h" ++//#include "chip_int.h" ++#include "ms_msys.h" ++#include "mhal_emac.h" ++#include "mdrv_emac.h" ++#include "ms_platform.h" ++#include "registers.h" ++ ++#ifdef CONFIG_EMAC_SUPPLY_RNG ++#include ++#include ++#include "mhal_rng_reg.h" ++#endif ++ ++// #include "mdrv_msys_io_st.h" ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "gpio.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#include "mdrv_puse.h" ++#endif ++ ++#include "cam_os_wrapper.h" ++#include "drv_camclk_Api.h" ++#ifdef CONFIG_MS_GPIO ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); ++#else ++#define MDrv_GPIO_Set_Low(x) ++#define MDrv_GPIO_Set_High(x) ++#define MDrv_GPIO_Pad_Set(x) ++#endif ++ ++#define INFINITY6E_CHIP_ID 0xF1 ++///////////////////////////////// ++// to be refined ++///////////////////////////////// ++#define TXD_NUM 0 ++// #define TXQ_NUM_SW 256 ++#define TXQ_NUM_SW 0 ++ ++#define RX_DESC_API 0 ++ ++#if EXT_PHY_PATCH ++#define IS_EXT_PHY(hemac) (0 == (hemac)->phyRIU) ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// helper definition ++//-------------------------------------------------------------------------------------------------- ++#define CLR_BITS(a, bits) ((a) & (~(bits))) ++#define SET_BITS(a, bits) ((a) | (bits)) ++ ++#define PA2BUS(a) ((a) - (MIU0_BUS_BASE)) ++#define BUS2PA(a) ((a) + (MIU0_BUS_BASE)) ++ ++#define BUS2VIRT(a) phys_to_virt(BUS2PA((a))) ++#define VIRT2BUS(a) PA2BUS(virt_to_phys((a))) ++ ++#define VIRT2PA(a) virt_to_phys((a)) ++ ++#if RX_DESC_API ++#define RX_DESC_MAKE(desc, bus, wrap) \ ++{ \ ++ if ((bus) & 0x3) \ ++ printk("[%s][%d] bad RX buffer address 0x%08x\n", __FUNCTION__, __LINE__, (bus)); \ ++ ((desc)->addr = (((bus) << 2) & 0xFFFFFFFC) | (wrap)); \ ++} ++#define RX_ADDR_GET(desc) BUS2VIRT(((((desc)->addr) & 0xFFFFFFFC)>> 2)) ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#if MSTAR_EMAC_NAPI ++#define EMAC_NAPI_WEIGHT 32 ++#endif ++ ++#define RX_DESC_NUM 0x100 ++#define RX_DESC_SIZE (sizeof(struct rbf_t)) ++#define RX_DESC_QUEUE_SIZE (RX_DESC_NUM * RX_DESC_SIZE) ++ ++#define EMAC_PACKET_SIZE_MAX 0x600 ++ ++#if EMAC_SG ++ #define FEATURES_EMAC_SG (NETIF_F_SG) ++#else ++ #define FEATURES_EMAC_SG (0) ++#endif ++ ++#if (EMAC_GSO) ++ #define FEATURES_EMAC_GSO ((NETIF_F_GSO) | (NETIF_F_GRO)) ++#else ++ #define FEATURES_EMAC_GSO (0) ++#endif ++ ++#if RX_CHECKSUM ++ #define FEATURES_EMAC_CSUM_RX (NETIF_F_RXCSUM) ++#else ++ #define FEATURES_EMAC_CSUM_RX (0) ++#endif ++ ++#if TX_CHECKSUM ++ #define FEATURES_EMAC_CSUM_TX (NETIF_F_HW_CSUM) ++#else ++ #define FEATURES_EMAC_CSUM_TX (0) ++#endif ++ ++#define EMAC_FEATURES (FEATURES_EMAC_SG | FEATURES_EMAC_GSO | FEATURES_EMAC_CSUM_RX | FEATURES_EMAC_CSUM_TX) ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++// #define EMAC_RX_TMR (0) ++// #define EMAC_LINK_TMR (1) ++// #define EMAC_FLOW_CTL_TMR (2) ++ ++// #define TIMER_EMAC_DYNAMIC_RX (1) ++// #define TIMER_EMAC_FLOW_TX (2) ++ ++#define EMAC_CHECK_LINK_TIME (HZ) ++ ++#define IDX_CNT_INT_DONE (0) ++#define IDX_CNT_INT_RCOM (1) ++#define IDX_CNT_INT_RBNA (2) ++#define IDX_CNT_INT_TOVR (3) ++#define IDX_CNT_INT_TUND (4) ++#define IDX_CNT_INT_RTRY (5) ++#define IDX_CNT_INT_TBRE (6) ++#define IDX_CNT_INT_TCOM (7) ++#define IDX_CNT_INT_TIDLE (8) ++#define IDX_CNT_INT_LINK (9) ++#define IDX_CNT_INT_ROVR (10) ++#define IDX_CNT_INT_HRESP (11) ++#define IDX_CNT_JULIAN_D (12) ++#define IDX_CNT_INT_TXQUEUE_THRESHOLD (24) // (EMAC)(I3E) ++#define IDX_CNT_INT_TXQUEUE_EMPTY (25) // (EMAC)(I3E) ++#define IDX_CNT_INT_TXQUEUE_DROP (26) // (EMAC)(I3E) ++ ++#if 0 ++u32 gu32CheckLinkTime = HZ; ++u32 gu32CheckLinkTimeDis = 100; ++u32 gu32intrEnable; ++u32 irq_count[32]={0}; ++u32 gu32PhyResetCount1=0; ++u32 gu32PhyResetCount2=0; ++u32 gu32PhyResetCount3=0; ++u32 gu32PhyResetCount4=0; ++u32 gu32PhyResetCount=0; ++ ++static u32 skb_tx_send = 0; ++static u32 skb_tx_free = 0; ++ ++static u64 data_done = 0; ++static u32 txPkt = 0; ++static u32 txInt = 0; ++static struct timespec data_time_last = { 0 }; ++static DEFINE_SPINLOCK(emac_data_done_lock); ++#endif ++ ++// #define RTL_8210 (0x1CUL) ++ ++#define RX_THROUGHPUT_TEST 0 ++#define TX_THROUGHPUT_TEST 0 ++ ++#ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++#define PACKET_THRESHOLD 260 ++#define TXCOUNT_THRESHOLD 10 ++#endif ++ ++#if EMAC_FLOW_CONTROL_TX ++#define MAC_CONTROL_TYPE 0x8808 ++#define MAC_CONTROL_OPCODE 0x0001 ++#define PAUSE_QUANTA_TIME_10M ((1000000*10)/500) ++#define PAUSE_QUANTA_TIME_100M ((1000000*100)/500) ++#define PAUSE_TIME_DIVISOR_10M (PAUSE_QUANTA_TIME_10M/HZ) ++#define PAUSE_TIME_DIVISOR_100M (PAUSE_QUANTA_TIME_100M/HZ) ++#endif // #if EMAC_FLOW_CONTROL_TX ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++// u32 contiROVR = 0; ++// u32 initstate= 0; ++// u8 txidx =0; ++// u32 txcount = 0; ++// spinlock_t emac_lock; ++ ++// 0x78c9: link is down. ++// static u32 phy_status_register = 0x78c9UL; ++ ++static dev_t gEthDev; ++static u8 _u8Minor = MINOR_EMAC_NUM; ++struct sk_buff *pseudo_packet; ++ ++#if TX_THROUGHPUT_TEST ++unsigned char packet_content[] = { ++0xa4, 0xba, 0xdb, 0x95, 0x25, 0x29, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x08, 0x00, 0x45, 0x00, ++0x05, 0xda, 0x69, 0x0a, 0x40, 0x00, 0x40, 0x11, 0xbe, 0x94, 0xac, 0x10, 0x5a, 0xe3, 0xac, 0x10, ++0x5a, 0x70, 0x92, 0x7f, 0x13, 0x89, 0x05, 0xc6, 0x0c, 0x5b, 0x00, 0x00, 0x03, 0x73, 0x00, 0x00, ++0x00, 0x65, 0x00, 0x06, 0xe1, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++0x13, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x18, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39 ++}; ++#endif ++ ++static unsigned int max_rx_packet_count=0; ++static unsigned int max_tx_packet_count=0; ++static unsigned int min_tx_fifo_idle_count=0xffff; ++static unsigned int tx_bytes_per_timerbak=0; ++static unsigned int tx_bytes_per_timer=0; ++// u32 RAM_ALLOC_SIZE=0; ++ ++// static unsigned int gu32GatingRxIrqTimes=0; ++ ++ ++int rx_packet_cnt = 0; ++#if MSTAR_EMAC_NAPI ++int napi_enable_flag = 0; ++#endif ++ ++static struct timespec rx_time_last = { 0 }; ++static int rx_duration_max = 0; ++ ++static int _phyReset = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++// static struct timer_list EMAC_timer, hemac->timer_link; ++// static struct timer_list hemac->timer_link; ++#if RX_THROUGHPUT_TEST ++static struct timer_list RX_timer; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Function ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_tx (struct sk_buff *skb, struct net_device *dev); ++static int MDev_EMAC_SwReset(struct net_device *dev); ++static void MDev_EMAC_dts(struct net_device*); ++#if EMAC_FLOW_CONTROL_TX ++static int _MDrv_EMAC_Pause_TX(struct net_device* emac_dev, struct sk_buff* skb, unsigned char* p_recv); ++static void _MDev_EMAC_FlowTX_CB(unsigned long data); ++#endif ++#if REDUCE_CPU_FOR_RBNA ++static void _MDev_EMAC_IntRX_CB(unsigned long data); ++#endif // #if REDUCE_CPU_FOR_RBNA ++ ++// static void MDev_EMAC_timer_callback( unsigned long value ); ++// static void MDev_EMAC_timer_LinkStatus(unsigned long data); ++ ++static void free_rx_skb(struct emac_handle *hemac) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ int i = 0; ++ // unsigned long flags; ++ ++ if (NULL == rxinfo->skb_arr) ++ return; ++ ++ // spin_lock_irqsave(&hemac->mutexRXD, flags); ++ for (i = 0; i < rxinfo->num_desc; i ++) ++ { ++ if (rxinfo->skb_arr[i]) ++ kfree_skb(rxinfo->skb_arr[i]); ++ } ++ // spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++} ++ ++// unsigned long oldTime; ++// unsigned long PreLinkStatus; ++#if MSTAR_EMAC_NAPI ++static int MDev_EMAC_napi_poll(struct napi_struct *napi, int budget); ++#endif ++ ++#ifdef CONFIG_MSTAR_EEE ++static int MDev_EMAC_IS_TX_IDLE(void); ++#endif //CONFIG_MSTAR_EEE ++ ++ ++//!!!! PACKET_DUMP has not been tested as they are not used. 2016/07/18 ++#if defined(PACKET_DUMP) ++extern struct file* msys_kfile_open(const char* path, int flags, int rights); ++extern void msys_kfile_close(struct file* fp); ++extern int msys_kfile_write(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size); ++ ++static int txDumpCtrl=0; ++static int rxDumpCtrl=0; ++static int txDumpFileLength=0; ++static int rxDumpFileLength=0; ++static char txDumpFileName[32]={0}; ++static char rxDumpFileName[32]={0}; ++static struct file* txDumpFile=NULL; ++static struct file* rxDumpFile=NULL; ++ ++static ssize_t tx_dump_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ txDumpCtrl = simple_strtoul(buf, NULL, 10); ++ if(1==txDumpCtrl) ++ { ++ strcpy(txDumpFileName,"/tmp/emac/tx_dump"); ++ txDumpFile=msys_kfile_open(rxDumpFileName, O_RDWR | O_CREAT, 0644); ++ if(NULL!=txDumpFile) ++ { ++ txDumpFileLength=0; ++ // printk(KERN_WARNING"success to open emac tx_dump file, '%s'...\n",txDumpFileName); ++ } ++ else ++ { ++ // printk(KERN_WARNING"failed to open emac tx_dump file, '%s'!!\n",txDumpFileName); ++ } ++ } ++ else if(0==txDumpCtrl && txDumpFile!=NULL) ++ { ++ ++ msys_kfile_close(txDumpFile); ++ txDumpFile=NULL; ++ } ++ return count; ++} ++static ssize_t tx_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", txDumpCtrl); ++} ++DEVICE_ATTR(tx_dump, 0644, tx_dump_show, tx_dump_store); ++ ++static ssize_t rx_dump_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ rxDumpCtrl = simple_strtoul(buf, NULL, 10); ++ if(1==rxDumpCtrl) ++ { ++ strcpy(rxDumpFileName,"/tmp/emac/rx_dump"); ++ rxDumpFile=msys_kfile_open(rxDumpFileName, O_RDWR | O_CREAT, 0644); ++ if(NULL!=rxDumpFile) ++ { ++ rxDumpFileLength=0; ++ // printk(KERN_WARNING"success to open emac rx_dump file, '%s'...\n",rxDumpFileName); ++ } ++ else ++ { ++ // printk(KERN_WARNING"failed to open emac rx_dump file, '%s'!!\n",rxDumpFileName); ++ } ++ } ++ else if(0==rxDumpCtrl) ++ { ++ if(rxDumpFile!=NULL) ++ { ++ msys_kfile_close(rxDumpFile); ++ rxDumpFile=NULL; ++ } ++ } ++ return count; ++} ++static ssize_t rx_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", rxDumpCtrl); ++} ++DEVICE_ATTR(rx_dump, 0644, rx_dump_show, rx_dump_store); ++#endif ++ ++static unsigned long getCurMs(void) ++{ ++ struct timeval tv; ++ unsigned long curMs; ++ ++ do_gettimeofday(&tv); ++ curMs = tv.tv_usec/1000; ++ curMs += tv.tv_sec * 1000; ++ return curMs; ++} ++ ++#if RX_THROUGHPUT_TEST ++int receive_bytes = 0; ++static void RX_timer_callback( unsigned long value){ ++ int get_bytes = receive_bytes; ++ int cur_speed; ++ receive_bytes = 0; ++ ++ cur_speed = get_bytes*8/20/1024; ++ printk(" %dkbps",cur_speed); ++ RX_timer.expires = jiffies + 20*EMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// skb_queue implementation ++//------------------------------------------------------------------------------------------------- ++#define SKBQ_SANITY 0 ++static int skb_queue_create(skb_queue* skb_q, int size, int size1) ++{ ++ if ((NULL == skb_q) || (0 == size)) ++ return 0; ++ // skb_q->size = size + 1; ++ skb_q->size[0] = size + 1; ++ skb_q->size[1] = size1 + 1; ++ if (NULL == (skb_q->skb_info_arr = kzalloc(skb_q->size[1]*sizeof(skb_info), GFP_KERNEL))) ++ return 0; ++ skb_q->read = skb_q->write = skb_q->rw = 0; ++ return 1; ++} ++ ++static int skb_queue_reset(skb_queue* skb_q) ++{ ++ int i; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ ++ for (i = 0; i < skb_q->size[1]; i++) ++ { ++ if (!skb_q->skb_info_arr[i].skb) ++ { ++ continue; ++ } ++ if (0xFFFFFFFF == (int)skb_q->skb_info_arr[i].skb) ++ { ++ void* p = BUS2VIRT(skb_q->skb_info_arr[i].skb_phys); ++ kfree(p); ++ continue; ++ } ++ dev_kfree_skb_any(skb_q->skb_info_arr[i].skb); ++ hemac->skb_tx_free++; ++ } ++ memset(skb_q->skb_info_arr, 0, skb_q->size[1]*sizeof(skb_info)); ++ skb_q->read = skb_q->write = skb_q->rw = 0; ++ return 1; ++} ++ ++static int skb_queue_destroy(skb_queue* skb_q) ++{ ++#if 0 ++ int i; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ for (i = 0; i < skb_q->size[1]; i++) ++ { ++ if (skb_q->skb_info_arr[i].skb) ++ { ++ dev_kfree_skb_any(skb_q->skb_info_arr[i].skb); ++ hemac->skb_tx_free++; ++ } ++ } ++ kfree(skb_q->skb_info_arr); ++ skb_q->skb_info_arr = NULL; ++ skb_q->size[0] = skb_q->size[1] = skb_q->read = skb_q->write = skb_q->rw = 0; ++#else ++ skb_queue_reset(skb_q); ++ kfree(skb_q->skb_info_arr); ++ skb_q->skb_info_arr = NULL; ++ skb_q->size[0] = skb_q->size[1] = 0; ++#endif ++ return 1; ++} ++ ++#define QUEUE_USED(size, read, write) ((write) >= (read))? ((write) - (read)) : ((size) - (read) + (write)) ++#define QUEUE_FREE(size, read, write) ((write) >= (read))? ((size) - (write) + (read) - 1) : ((read) - (write) - 1) ++/* ++static int skb_queue_used(skb_queue* skb_q, int idx, int idx_size) ++{ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++#endif ++ if (2 == idx) ++ return QUEUE_USED(skb_q->size[1], skb_q->rw, skb_q->write); ++ return (0 == idx) ? ++ QUEUE_USED(skb_q->size[idx_size], skb_q->read, skb_q->rw) : ++ QUEUE_USED(skb_q->size[idx_size], skb_q->read, skb_q->write); ++} ++*/ ++inline static int skb_queue_used(skb_queue* skb_q, int idx) ++{ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++#endif ++ if (2 == idx) ++ return QUEUE_USED(skb_q->size[1], skb_q->rw, skb_q->write); ++ return (0 == idx) ? ++ QUEUE_USED(skb_q->size[1], skb_q->read, skb_q->rw) : ++ QUEUE_USED(skb_q->size[1], skb_q->read, skb_q->write); ++} ++ ++inline static int skb_queue_free(skb_queue* skb_q, int idx) ++{ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++#endif ++ // return skb_q->size[idx] - skb_queue_used(skb_q, idx) - 1; ++ if (2 == idx) ++ return QUEUE_FREE(skb_q->size[1], skb_q->rw, skb_q->write); ++ return (0 == idx) ? ++ QUEUE_FREE(skb_q->size[1], skb_q->read, skb_q->rw) : ++ QUEUE_FREE(skb_q->size[1], skb_q->read, skb_q->write); ++} ++ ++inline static int skb_queue_remove(skb_queue* skb_q, struct sk_buff** pskb, dma_addr_t* pphys, int bSkbFree, int idx) ++{ ++ skb_info* pskb_info; ++ int read; ++ int len; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ if (0 == skb_queue_used(skb_q, idx)) ++ { ++ printk("[%s][%d] why\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ read = skb_q->read; ++ pskb_info = &(skb_q->skb_info_arr[read]); ++#if SKBQ_SANITY ++ if ((!pskb_info->skb) && (!pskb_info->skb_phys)) ++ { ++ printk("[%s][%d] strange remove\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++#endif ++ len = pskb_info->skb_len; ++ ++ // printk("[%s][%d] (skb, addr, len) = (0x%08x, 0x%08x, %d)\n", __FUNCTION__, __LINE__, (int)pskb_info->skb, VIRT2BUS(pskb_info->skb->data), len); ++ ++ hemac->skb_tx_free++; ++ if (bSkbFree) ++ { ++ if (pskb_info->skb) ++ { ++ if (0xFFFFFFFF == (int)pskb_info->skb) ++ { ++ void* p = BUS2VIRT(pskb_info->skb_phys); ++ kfree(p); ++ } ++ else ++ { ++ dev_kfree_skb_any(pskb_info->skb); ++ } ++ pskb_info->skb = NULL; ++ // hemac->skb_tx_free++; ++ } ++ } ++ else ++ { ++ *pskb = pskb_info->skb; ++ *pphys = pskb_info->skb_phys; ++ } ++ pskb_info->skb_phys = 0; ++ pskb_info->skb_len = 0; ++ ++ skb_q->read++; ++ if (skb_q->read >= skb_q->size[1]) ++ skb_q->read -= skb_q->size[1]; ++ return len; ++} ++ ++inline static int skb_queue_insert(skb_queue* skb_q, struct sk_buff* skb, dma_addr_t phys, int skb_len, int idx) ++{ ++ skb_info* pskb_info; ++ int* pwrite = NULL; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ if (0 == skb_queue_free(skb_q, idx)) ++ { ++ printk("[%s][%d] why\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ pwrite = (0 == idx) ? &skb_q->rw : &skb_q->write; ++ pskb_info = &(skb_q->skb_info_arr[*pwrite]); ++ // if ((pskb_info->used) || (pskb_info->skb)) ++ // if (pskb_info->used) ++#if SKBQ_SANITY ++ if ((pskb_info->skb) || (pskb_info->skb_phys)) ++ { ++ printk("[%s][%d] strange insert\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++#endif ++ // if (skb) ++ hemac->skb_tx_send++; ++ // pskb_info->used = 1; ++ pskb_info->skb_phys = phys; ++ pskb_info->skb_len = skb_len; ++ pskb_info->skb = skb; ++ (*pwrite)++; ++ if (*pwrite >= skb_q->size[1]) ++ (*pwrite) -= skb_q->size[1]; ++ return 1; ++} ++ ++inline static int skb_queue_head_inc(skb_queue* skb_q, struct sk_buff** skb, dma_addr_t* pphys, int* plen, int idx) ++{ ++ skb_info* pskb_info; ++ int* pwrite = NULL; ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ if (0 == skb_queue_free(skb_q, idx)) ++ { ++ printk("[%s][%d] why\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ *skb = NULL; ++ *pphys = 0; ++ pwrite = (0 == idx) ? &skb_q->rw : &skb_q->write; ++ pskb_info = &(skb_q->skb_info_arr[*pwrite]); ++#if SKBQ_SANITY ++ // if ((!pskb_info->skb) || (!pskb_info->skb_phys)) ++ if ((!pskb_info->skb_phys)) ++ { ++ printk("[%s][%d] strange head inc\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ *skb = pskb_info->skb; ++ *pphys = pskb_info->skb_phys; ++ *plen = pskb_info->skb_len; ++ (*pwrite)++; ++ if (*pwrite >= skb_q->size[1]) ++ (*pwrite) -= skb_q->size[1]; ++ return 1; ++} ++ ++/* ++static int skb_queue_emtpy(skb_queue* skb_q) ++{ ++ return (skb_queue_used(skb_q))? 0 : 1; ++} ++*/ ++ ++inline static int skb_queue_full(skb_queue* skb_q, int idx) ++{ ++ return (skb_queue_free(skb_q, idx))? 0 : 1; ++} ++ ++/* ++static int skb_queue_size(skb_queue* skb_q, int idx) ++{ ++ return skb_q->size[idx] - 1; ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// PHY MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Access the PHY to determine the current Link speed and Mode, and update the ++// MAC accordingly. ++// If no link or auto-negotiation is busy, then no changes are made. ++// Returns: 0 : OK ++// -1 : No link ++// -2 : AutoNegotiation still in progress ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_update_linkspeed (struct net_device *dev) ++{ ++ u32 bmsr, bmcr, adv, lpa, neg; ++ u32 speed, duplex; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ u32 hcd_link_st_ok, an_100t_link_st = 0; ++ static unsigned int phy_restart_cnt = 0; ++ u32 an_state = 0; ++ u32 an_state2 = 0; ++ u32 an_state3 = 0; ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ #ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE(); ++ ++ if (hemac->PreLinkStatus == 1) ++ { ++ MHal_EMAC_Reset_EEE(); ++ } ++ #endif ++ ++ hemac->PreLinkStatus = 0; ++ ++ return -1; //no link // ++ } ++ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ //EMAC_DBG("==> AutoNegotiation still in progress\n"); ++ return -2; ++ } ++ ++ /* Get Link partner and advertisement from the PHY not from the MAC */ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_ADVERTISE, &adv); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_LPA, &lpa); ++ ++ /* For Link Parterner adopts force mode and EPHY used, ++ * EPHY LPA reveals all zero value. ++ * EPHY would be forced to Full-Duplex mode. ++ */ ++ if (!lpa) ++ { ++ /* 100Mbps Full-Duplex */ ++ if (bmcr & BMCR_SPEED100) ++ lpa |= LPA_100FULL; ++ else /* 10Mbps Full-Duplex */ ++ lpa |= LPA_10FULL; ++ } ++ ++ neg = adv & lpa; ++ ++ if (neg & LPA_100FULL) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_100HALF) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if (neg & LPA_10FULL) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_10HALF) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ EMAC_DBG("%s: No speed and mode found (LPA=0x%x, ADV=0x%x)\n", __FUNCTION__, lpa, adv); ++ } ++ ++ } ++ else ++ { ++ speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ // Update the MAC // ++ MHal_EMAC_update_speed_duplex(hemac->hal, speed,duplex); ++ ++#ifdef CONFIG_MSTAR_EEE ++ /*TX idle, enable EEE*/ ++ if((MDev_EMAC_IS_TX_IDLE()) && (speed == SPEED_100) && (duplex == DUPLEX_FULL)) ++ { ++ if (hemac->PreLinkStatus == 0) ++ { ++ MHal_EMAC_Enable_EEE(300); ++ } ++ else ++ { ++ MHal_EMAC_Enable_EEE(0); ++ } ++ } ++#endif ++ ++ hemac->PreLinkStatus = 1; ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ if (speed == SPEED_100) { ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x21, &hcd_link_st_ok); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x22, &an_100t_link_st); ++ if ( (!(hcd_link_st_ok & 0x100) && ((an_100t_link_st & 0x300) == 0x200))) { ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount1++; ++ EMAC_ERR("hcd_link_st_ok:0x%x, an_100t_link_st:0x%x\n", hcd_link_st_ok, an_100t_link_st); ++ if (phy_restart_cnt > 10) { ++ EMAC_DBG("MDev_EMAC_update_linkspeed: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ else if (((hcd_link_st_ok & 0x100) && !(an_100t_link_st & 0x300)) ) { ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount2++; ++ EMAC_ERR("hcd_link_st_ok:0x%x, an_100t_link_st:0x%x\n", hcd_link_st_ok, an_100t_link_st); ++ if (phy_restart_cnt > 10) { ++ EMAC_DBG("MDev_EMAC_update_linkspeed: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ ++ /* Monitor AN state*/ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x2e, &an_state); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x2e, &an_state2); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x2e, &an_state3); ++ if ((an_state != an_state2) || (an_state != an_state3)) ++ { ++ EMAC_ERR("an_state 1:0x%x, 2:0x%x, 3:0x%x\n", an_state, an_state2, an_state3); ++ return 0; ++ } ++ ++ if ((an_state & 0xf000) == 0x3000) ++ { ++ EMAC_ERR("an_state=0x%x\n", an_state); ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount3++; ++ if (phy_restart_cnt > 10){ ++ EMAC_DBG("PHY_AN_monitor_timer_callback: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ else if ((an_state & 0xf000) == 0x2000) ++ { ++ EMAC_ERR("an_state=0x%x\n", an_state); ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount4++; ++ if (phy_restart_cnt > 10){ ++ EMAC_DBG("PHY_AN_monitor_timer_callback: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ // else{ ++ // phy_restart_cnt = 0; ++ // } ++ } ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++ return 0; ++} ++#endif ++ ++#if 0 ++static int MDev_EMAC_get_info(struct net_device *dev) ++{ ++ u32 bmsr, bmcr, LocPtrA; ++ u32 uRegStatus =0; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_NO_LINK; //no link // ++ } ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_AUTO_NEGOTIATION; //AutoNegotiation // ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_LINK_SUCCESS; //link success // ++ } ++ ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ uRegStatus |= ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ uRegStatus |= ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ else ++ { ++ if(bmcr & BMCR_SPEED100) ++ { ++ uRegStatus |= ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if(bmcr & BMCR_FULLDPLX) ++ { ++ uRegStatus |= ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ ++ return uRegStatus; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//Program the hardware MAC address from dev->dev_addr. ++//------------------------------------------------------------------------------------------------- ++void MDev_EMAC_update_mac_address (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 value; ++ value = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) |(dev->dev_addr[0]); ++ MHal_EMAC_Write_SA1L(hemac->hal, value); ++ value = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]); ++ MHal_EMAC_Write_SA1H(hemac->hal, value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// ADDRESS MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Set the ethernet MAC address in dev->dev_addr ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_get_mac_address (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_EMAC_get_SA1H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA1L_addr(hemac->hal); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_EMAC_get_SA2H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA2L_addr(hemac->hal); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++} ++ ++#ifdef URANUS_ETHER_ADDR_CONFIGURABLE ++//------------------------------------------------------------------------------------------------- ++// Store the new hardware address in dev->dev_addr, and update the MAC. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_set_mac_address (struct net_device *dev, void *addr) ++{ ++ struct sockaddr *address = addr; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (!is_valid_ether_addr (address->sa_data)) ++ return -EADDRNOTAVAIL; ++ spin_lock(&hemac->mutexPhy); ++ memcpy (dev->dev_addr, address->sa_data, dev->addr_len); ++ MDev_EMAC_update_mac_address (dev); ++ spin_unlock(&hemac->mutexPhy); ++ return 0; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Mstar Multicast hash rule ++//------------------------------------------------------------------------------------------------- ++//Hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] ++//Hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] ++//Hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] ++//Hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] ++//Hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] ++//Hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] ++//------------------------------------------------------------------------------------------------- ++ ++static void MDev_EMAC_sethashtable(struct net_device *dev, unsigned char *addr) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 mc_filter[2]; ++ u32 uHashIdxBit; ++ u32 uHashValue; ++ u32 i; ++ u32 tmpcrc; ++ u32 uSubIdx; ++ u64 macaddr; ++ u64 mac[6]; ++ ++ uHashValue = 0; ++ macaddr = 0; ++ ++ // Restore mac // ++ for(i = 0; i < 6; i++) ++ { ++ mac[i] =(u64)addr[i]; ++ } ++ ++ // Truncate mac to u64 container // ++ macaddr |= mac[0] | (mac[1] << 8) | (mac[2] << 16); ++ macaddr |= (mac[3] << 24) | (mac[4] << 32) | (mac[5] << 40); ++ ++ // Caculate the hash value // ++ for(uHashIdxBit = 0; uHashIdxBit < 6; uHashIdxBit++) ++ { ++ tmpcrc = (macaddr & (0x1UL << uHashIdxBit)) >> uHashIdxBit; ++ for(i = 1; i < 8; i++) ++ { ++ uSubIdx = uHashIdxBit + (i * 6); ++ tmpcrc = tmpcrc ^ ((macaddr >> uSubIdx) & 0x1); ++ } ++ uHashValue |= (tmpcrc << uHashIdxBit); ++ } ++ ++ mc_filter[0] = MHal_EMAC_ReadReg32(hemac->hal, REG_ETH_HSL); ++ mc_filter[1] = MHal_EMAC_ReadReg32(hemac->hal, REG_ETH_HSH); ++ ++ // Set the corrsponding bit according to the hash value // ++ if(uHashValue < 32) ++ { ++ mc_filter[0] |= (0x1UL << uHashValue); ++ MHal_EMAC_WritReg32(hemac->hal, REG_ETH_HSL, mc_filter[0] ); ++ } ++ else ++ { ++ mc_filter[1] |= (0x1UL << (uHashValue - 32)); ++ MHal_EMAC_WritReg32(hemac->hal, REG_ETH_HSH, mc_filter[1] ); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Enable/Disable promiscuous and multicast modes. ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_set_rx_mode (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ struct netdev_hw_addr *ha; ++ ++ uRegVal = MHal_EMAC_Read_CFG(hemac->hal); ++ ++ if (dev->flags & IFF_PROMISC) ++ { ++ // Enable promiscuous mode // ++ uRegVal |= EMAC_CAF; ++ } ++ else if (dev->flags & (~IFF_PROMISC)) ++ { ++ // Disable promiscuous mode // ++ uRegVal &= ~EMAC_CAF; ++ } ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++ ++ if (dev->flags & IFF_ALLMULTI) ++ { ++ // Enable all multicast mode // ++ MHal_EMAC_update_HSH(hemac->hal, -1,-1); ++ uRegVal |= EMAC_MTI; ++ } ++ else if (dev->flags & IFF_MULTICAST) ++ { ++ // Enable specific multicasts// ++ MHal_EMAC_update_HSH(hemac->hal, 0,0); ++ netdev_for_each_mc_addr(ha, dev) ++ { ++ MDev_EMAC_sethashtable(dev, ha->addr); ++ } ++ uRegVal |= EMAC_MTI; ++ } ++ else if (dev->flags & ~(IFF_ALLMULTI | IFF_MULTICAST)) ++ { ++ // Disable all multicast mode// ++ MHal_EMAC_update_HSH(hemac->hal, 0,0); ++ uRegVal &= ~EMAC_MTI; ++ } ++ ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++} ++//------------------------------------------------------------------------------------------------- ++// IOCTL ++//------------------------------------------------------------------------------------------------- ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable MDIO ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_mdio_read (struct net_device *dev, int phy_id, int location) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 value; ++ MHal_EMAC_read_phy (hemac->hal, phy_id, location, &value); ++ return value; ++} ++ ++static void MDev_EMAC_mdio_write (struct net_device *dev, int phy_id, int location, int value) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ MHal_EMAC_write_phy (hemac->hal, phy_id, location, value); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//ethtool support. ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static int MDev_EMAC_ethtool_ioctl (struct net_device *dev, void *useraddr) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 ethcmd; ++ int res = 0; ++ ++ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ switch (ethcmd) ++ { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ res = mii_ethtool_gset (&hemac->mii, &ecmd); ++ if (copy_to_user (useraddr, &ecmd, sizeof (ecmd))) ++ res = -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd ecmd; ++ if (copy_from_user (&ecmd, useraddr, sizeof (ecmd))) ++ res = -EFAULT; ++ else ++ res = mii_ethtool_sset (&hemac->mii, &ecmd); ++ break; ++ } ++ case ETHTOOL_NWAY_RST: ++ { ++ res = mii_nway_restart (&hemac->mii); ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ edata.data = mii_link_ok (&hemac->mii); ++ if (copy_to_user (useraddr, &edata, sizeof (edata))) ++ res = -EFAULT; ++ break; ++ } ++ default: ++ res = -EOPNOTSUPP; ++ } ++ return res; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// User-space ioctl interface. ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static int MDev_EMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ struct mii_ioctl_data *data = if_mii(rq); ++ u32 value; ++ if (!netif_running(dev)) ++ { ++ rq->ifr_metric = ETHERNET_TEST_INIT_FAIL; ++ } ++ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ data->phy_id = (hemac->phyaddr & 0x1FUL); ++ return 0; ++ ++ case SIOCDEVPRIVATE: ++ rq->ifr_metric = (MDev_EMAC_get_info(dev)|hemac->initstate); ++ return 0; ++/* ++ case SIOCDEVON: ++ MHal_EMAC_Power_On_Clk(); ++ return 0; ++ ++ case SIOCDEVOFF: ++ MHal_EMAC_Power_Off_Clk(); ++ return 0; ++*/ ++ case SIOCGMIIREG: ++ // check PHY's register 1. ++ if((data->reg_num & 0x1fUL) == 0x1UL) ++ { ++ // PHY's register 1 value is set by timer callback function. ++ spin_lock(&hemac->mutexPhy); ++ data->val_out = hemac->phy_status_register; ++ spin_unlock(&hemac->mutexPhy); ++ } ++ else ++ { ++ MHal_EMAC_read_phy(hemac->hal, (hemac->phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), (u32 *)&(value)); ++ data->val_out = value; ++ } ++ return 0; ++ ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ MHal_EMAC_write_phy(hemac->hal, (hemac->phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), data->val_in); ++ return 0; ++ ++ case SIOCETHTOOL: ++ return MDev_EMAC_ethtool_ioctl (dev, (void *) rq->ifr_data); ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++#else ++static int MDev_EMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(dev->phydev, rq, cmd); ++ default: ++ break; ++ } ++ return -EOPNOTSUPP; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// MAC ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and start the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_start (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ ++ // Enable Receive and Transmit // ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal |= (EMAC_RE | EMAC_TE); ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Stop the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_stop (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ ++ // Disable Receive and Transmit // ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal &= ~(EMAC_TE | EMAC_RE); ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Open the ethernet interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_open (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ // unsigned long flags; ++ ++#if MSTAR_EMAC_NAPI ++ napi_enable(&hemac->napi); ++ napi_enable_flag = 1; ++#endif ++ ++ spin_lock(&hemac->mutexPhy); ++ if (!is_valid_ether_addr (dev->dev_addr)) ++ { ++ spin_unlock(&hemac->mutexPhy); ++ return -EADDRNOTAVAIL; ++ } ++ spin_unlock(&hemac->mutexPhy); ++ ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(dev); ++#endif ++ //ato EMAC_SYS->PMC_PCER = 1 << EMAC_ID_EMAC; //Re-enable Peripheral clock // ++ //MHal_EMAC_Power_On_Clk(dev->dev); ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal |= EMAC_CSR; ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++ // Enable PHY interrupt // ++ MHal_EMAC_enable_phyirq(hemac->hal); ++ ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ hemac->gu32intrEnable = EMAC_INT_RBNA|EMAC_INT_TUND|EMAC_INT_RTRY|EMAC_INT_ROVR|EMAC_INT_HRESP; ++#if !DYNAMIC_INT_TX ++ hemac->gu32intrEnable |= EMAC_INT_TCOM; ++#endif ++ hemac->gu32intrEnable |= EMAC_INT_RCOM; ++ MHal_EMAC_IntEnable(hemac->hal, hemac->gu32intrEnable, 1); ++ ++ hemac->ep_flag |= EP_FLAG_OPEND; ++ ++ MDev_EMAC_start(dev); ++ phy_start(dev->phydev); ++ netif_start_queue(dev); ++ ++ // init_timer( &hemac->timer_link ); ++ ++#if 0 ++ hemac->timer_link.data = (unsigned long)dev; ++ hemac->timer_link.function = MDev_EMAC_timer_LinkStatus; ++ ++ hemac->timer_link.expires = jiffies + EMAC_CHECK_LINK_TIME; ++ add_timer(&hemac->timer_link); ++#endif ++ ++#if 0 ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ // MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ // MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1000UL); ++ //MHal_EMAC_write_phy(hemac->phyaddr, MII_BMCR, 0x1200UL); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); ++#else ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x9000UL); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1000UL); ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++#endif ++ ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ if(hemac->phy_mode != PHY_INTERFACE_MODE_RMII) ++ MHal_EMAC_Phy_Restart_An(hemac->hal); ++#endif ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Close the interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_close (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ unsigned long flags; ++ ++#if MSTAR_EMAC_NAPI ++ if(napi_enable_flag == 1) ++ napi_disable(&hemac->napi); ++ napi_enable_flag = 0; ++#endif ++ ++ spin_lock(&hemac->mutexPhy); ++ //Disable Receiver and Transmitter // ++ MDev_EMAC_stop(dev); ++ ++ // Disable PHY interrupt // ++ MHal_EMAC_disable_phyirq(hemac->hal); ++ spin_unlock(&hemac->mutexPhy); ++ ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ netif_stop_queue (dev); ++ netif_carrier_off(dev); ++ phy_stop(dev->phydev); ++ // del_timer(&hemac->timer_link); ++ // MHal_EMAC_Power_Off_Clk(dev->dev); ++ // hemac->ThisBCE.connected = 0; ++ hemac->ep_flag &= (~EP_FLAG_OPEND); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return 0; ++} ++u8 MDev_EMAC_ClkDisable(struct emac_handle *hemac) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0; ++ ++ for(u32clknum = 0; u32clknum < hemac->EmacParentCnt; u32clknum++) ++ { ++ if (hemac->pvclk[u32clknum]) ++ { ++ CamClkSetOnOff(hemac->pvclk[u32clknum],0); ++ } ++ } ++#endif ++ return 1; ++} ++u8 MDev_EMAC_ClkEnable(struct emac_handle *hemac) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0; ++ CAMCLK_Set_Attribute stSetCfg; ++ CAMCLK_Get_Attribute stGetCfg; ++ ++ for(u32clknum = 0; u32clknum < hemac->EmacParentCnt; u32clknum++) ++ { ++ if (hemac->pvclk[u32clknum]) ++ { ++ CamClkAttrGet(hemac->pvclk[u32clknum],&stGetCfg); ++ CAMCLK_SETPARENT(stSetCfg,stGetCfg.u32Parent[0]); ++ CamClkAttrSet(hemac->pvclk[u32clknum],&stSetCfg); ++ CamClkSetOnOff(hemac->pvclk[u32clknum],1); ++ } ++ } ++ ++#endif ++ return 1; ++} ++u8 MDev_EMAC_ClkRegister(struct emac_handle *hemac, struct device *dev) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum; ++ u32 EmacClk; ++ u8 str[8]; ++ ++ if(of_find_property(dev->of_node,"camclk",&hemac->EmacParentCnt)) ++ { ++ hemac->EmacParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(hemac->EmacParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, hemac->EmacParentCnt); ++ return 0; ++ } ++ hemac->pvclk = kzalloc((sizeof(void *) * hemac->EmacParentCnt), GFP_KERNEL); ++ if(!hemac->pvclk){ ++ return 0; ++ } ++ for(u32clknum = 0; u32clknum < hemac->EmacParentCnt; u32clknum++) ++ { ++ EmacClk = 0; ++ of_property_read_u32_index(dev->of_node,"camclk", u32clknum,&(EmacClk)); ++ if (!EmacClk) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamOsSnprintf(str, 8, "emac_%d ",u32clknum); ++ CamClkRegister(str,EmacClk,&(hemac->pvclk[u32clknum])); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#endif ++ return 1; ++} ++u8 MDev_EMAC_ClkUnregister(struct emac_handle *hemac) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum; ++ ++ for(u32clknum=0;u32clknumEmacParentCnt;u32clknum++) ++ { ++ if(hemac->pvclk[u32clknum]) ++ { ++ printk(KERN_DEBUG "[%s] %p\n", __func__,hemac->pvclk[u32clknum]); ++ CamClkUnregister(hemac->pvclk[u32clknum]); ++ hemac->pvclk[u32clknum] = NULL; ++ } ++ } ++ kfree(hemac->pvclk); ++#endif ++ return 1; ++} ++//------------------------------------------------------------------------------------------------- ++// Update the current statistics from the internal statistics registers. ++//------------------------------------------------------------------------------------------------- ++static struct net_device_stats * MDev_EMAC_stats (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ int ale, lenerr, seqe, lcol, ecol; ++ ++ // spin_lock_irq (hemac->lock); ++ ++ if (netif_running (dev)) ++ { ++ hemac->stats.rx_packets += MHal_EMAC_Read_OK(hemac->hal); /* Good frames received */ ++ ale = MHal_EMAC_Read_ALE(hemac->hal); ++ hemac->stats.rx_frame_errors += ale; /* Alignment errors */ ++ lenerr = MHal_EMAC_Read_ELR(hemac->hal); ++ hemac->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ ++ seqe = MHal_EMAC_Read_SEQE(hemac->hal); ++ hemac->stats.rx_crc_errors += seqe; /* CRC error */ ++ hemac->stats.rx_fifo_errors += MHal_EMAC_Read_ROVR(hemac->hal); ++ hemac->stats.rx_errors += ale + lenerr + seqe + MHal_EMAC_Read_SE(hemac->hal) + MHal_EMAC_Read_RJB(hemac->hal); ++ hemac->stats.tx_packets += MHal_EMAC_Read_FRA(hemac->hal); /* Frames successfully transmitted */ ++ hemac->stats.tx_fifo_errors += MHal_EMAC_Read_TUE(hemac->hal); /* Transmit FIFO underruns */ ++ hemac->stats.tx_carrier_errors += MHal_EMAC_Read_CSE(hemac->hal); /* Carrier Sense errors */ ++ hemac->stats.tx_heartbeat_errors += MHal_EMAC_Read_SQEE(hemac->hal); /* Heartbeat error */ ++ lcol = MHal_EMAC_Read_LCOL(hemac->hal); ++ ecol = MHal_EMAC_Read_ECOL(hemac->hal); ++ hemac->stats.tx_window_errors += lcol; /* Late collisions */ ++ hemac->stats.tx_aborted_errors += ecol; /* 16 collisions */ ++ hemac->stats.collisions += MHal_EMAC_Read_SCOL(hemac->hal) + MHal_EMAC_Read_MCOL(hemac->hal) + lcol + ecol; ++ } ++ ++ // spin_unlock_irq (hemac->lock); ++ ++ return &hemac->stats; ++} ++ ++static int MDev_EMAC_TxReset(struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 val = MHal_EMAC_Read_CTL(hemac->hal) & 0x000001FFUL; ++ ++ MHal_EMAC_Write_CTL(hemac->hal, (val & ~EMAC_TE)); ++ ++ val = MHal_EMAC_Read_CTL(hemac->hal) & 0x000001FFUL; ++ EMAC_ERR ("MAC0_CTL:0x%08x\n", val); ++ //MHal_EMAC_Write_TCR(0); ++ mdelay(1); ++ MHal_EMAC_Write_CTL(hemac->hal, (MHal_EMAC_Read_CTL(hemac->hal) | EMAC_TE)); ++ val = MHal_EMAC_Read_CTL(hemac->hal) & 0x000001FFUL; ++ EMAC_ERR ("MAC0_CTL:0x%08x\n", val); ++ return 0; ++} ++ ++#ifdef CONFIG_MSTAR_EEE ++static int MDev_EMAC_IS_TX_IDLE(void) ++{ ++ u32 check; ++ u32 tsrval = 0; ++ ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++#ifdef TX_QUEUE_4 ++ for (check = 0; check < EMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_EMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval == 8) ++ return 1; ++ } ++#endif ++ ++ return 0; ++} ++#endif //CONFIG_MSTAR_EEE ++ ++ ++#if 0 ++void MDrv_EMAC_DumpMem(phys_addr_t addr, u32 len) ++{ ++ u8 *ptr = (u8 *)addr; ++ u32 i; ++ ++ printk("\n ===== Dump %lx =====\n", (long unsigned int)ptr); ++ for (i=0; ihal) & 0x000001FFUL; ++ ++ //Disable Rx ++ MHal_EMAC_Write_CTL(hemac->hal, (val & ~EMAC_RE)); // why RX ++ memcpy(&hemac->pu8PausePkt[6], dev->dev_addr, 6); ++ Chip_Flush_Cache_Range((size_t)hemac->pu8PausePkt, hemac->u8PausePktSize); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ hemac->isPausePkt = 1; ++ // skb_queue_insert(&(hemac->skb_queue_tx), NULL, VIRT2BUS(hemac->pu8PausePkt), hemac->u8PausePktSize, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ MHal_EMAC_Write_CTL(hemac->hal, (MHal_EMAC_Read_CTL(hemac->hal) | EMAC_RE)); // why RX ++} ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++//------------------------------------------------------------------------------------------------- ++//Patch for losing small-size packet when running SMARTBIT ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++static void MDev_EMAC_Period_Retry(struct sk_buff *skb, struct net_device* dev) ++{ ++ u32 xval; ++ u32 uRegVal; ++ ++ xval = MHal_EMAC_ReadReg32(hemac->hal,REG_ETH_CFG); ++ ++ if((skb->len <= PACKET_THRESHOLD) && !(xval & EMAC_SPD) && !(xval & EMAC_FD)) ++ { ++ txcount++; ++ } ++ else ++ { ++ txcount = 0; ++ } ++ ++ if(txcount > TXCOUNT_THRESHOLD) ++ { ++ uRegVal = MHal_EMAC_Read_CFG(hemac->hal); ++ uRegVal |= 0x00001000UL; ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++ } ++ else ++ { ++ uRegVal = MHal_EMAC_Read_CFG(hemac->hal); ++ uRegVal &= ~(0x00001000UL); ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++ } ++} ++#endif ++ ++#if 0 ++static int _MDev_EMAC_tx_free(struct emac_handle *hemac) ++{ ++ // int pkt_num = 0; ++ // int byte_num = 0; ++ int txUsedCnt; ++ int txUsedCntSW; ++ int i; ++ unsigned long flags; ++ int len; ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ txUsedCnt = MHal_EMAC_TXQ_Used(hemac->hal); ++ txUsedCntSW = skb_queue_used(&hemac->skb_queue_tx, 0); ++ if (txUsedCntSW < txUsedCnt) ++ { ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return 0; ++ } ++ for (i = txUsedCnt; i < txUsedCntSW; i++) ++ { ++ len = skb_queue_remove(&hemac->skb_queue_tx, NULL, NULL, 1, 0); ++ // if (len < 0) ++ // return 0; ++ hemac->stats.tx_bytes += len; ++ // pkt_num++; ++ // byte_num+= len; ++ tx_bytes_per_timer += len; ++ // skb_tx_free++; ++ } ++/* ++ if (pkt_num) ++ { ++ // netdev_completed_queue(dev, pkt_num, byte_num); ++ } ++*/ ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return 1; ++} ++#else ++static int _MDev_EMAC_tx_pump(struct emac_handle *hemac, int bFree, int bPump) ++{ ++ int txUsedCnt; ++ int txUsedCntSW; ++ int i; ++ unsigned long flags; ++ unsigned long flags1; ++ int len; ++ struct sk_buff* skb = NULL; ++ dma_addr_t skb_addr; ++ int nPkt; ++ int txFreeCnt; ++ int txPendCnt; ++ int ret = 0; ++ ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ if (bFree) ++ { ++ txUsedCnt = MHal_EMAC_TXQ_Used(hemac->hal); ++ txUsedCntSW = skb_queue_used(&hemac->skb_queue_tx, 0); ++ ret = txUsedCntSW - txUsedCnt; ++ for (i = txUsedCnt; i < txUsedCntSW; i++) ++ { ++ // MHal_EMAC_TXQ_Remove(); ++ len = skb_queue_remove(&hemac->skb_queue_tx, NULL, NULL, 1, 0); ++ spin_lock_irqsave(&hemac->emac_data_done_lock, flags1); ++ hemac->data_done += len; ++ spin_unlock_irqrestore(&hemac->emac_data_done_lock, flags1); ++ ++ hemac->stats.tx_bytes += len; ++ tx_bytes_per_timer += len; ++ } ++ } ++ ++ if (bPump) ++ { ++ int skb_len; ++ txFreeCnt = skb_queue_free(&hemac->skb_queue_tx, 0); ++ txPendCnt = skb_queue_used(&hemac->skb_queue_tx, 2); ++ nPkt = (txFreeCnt < txPendCnt) ? txFreeCnt : txPendCnt; ++ for (i = 0; i < nPkt; i++) ++ { ++ skb_queue_head_inc(&hemac->skb_queue_tx, &skb, &skb_addr, &skb_len, 0); ++ if (skb_addr) ++ { ++ MHal_EMAC_TXQ_Insert(hemac->hal, skb_addr, skb_len); ++ } ++ } ++ } ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return ret; ++} ++#endif ++ ++static int MDev_EMAC_tx(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ dma_addr_t skb_addr; ++ // int txIdleCount=0; ++ // int txIdleCntSW = 0; ++ unsigned long flags; ++ unsigned long flag1; ++ int ret = NETDEV_TX_OK; ++ ++ spin_lock_irqsave(&hemac->mutexNetIf, flag1); ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ ++#ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE_TX(); ++#endif ++ ++ if (netif_queue_stopped(dev)){ ++ EMAC_ERR("netif_queue_stopped\n"); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ if (!netif_carrier_ok(dev)){ ++ // EMAC_ERR("netif_carrier_off\n"); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ if (skb->len > EMAC_MTU) ++ { ++ // EMAC_ERR("Something wrong (mtu, tx_len) = (%d, %d)\n", dev->mtu, skb->len); ++ // ret = NETDEV_TX_BUSY; ++ dev_kfree_skb_any(skb); ++ dev->stats.tx_dropped++; ++ goto out_unlock; ++ } ++#if defined(PACKET_DUMP) ++ if(1==txDumpCtrl && NULL!=txDumpFile) ++ { ++ txDumpFileLength+=msys_kfile_write(txDumpFile,txDumpFileLength,skb->data,skb->len); ++ } ++ else if(2==txDumpCtrl && NULL!=txDumpFile) ++ { ++ msys_kfile_close(txDumpFile); ++ txDumpFile=NULL; ++ printk(KERN_WARNING"close emac tx_dump file '%s', len=0x%08X...\n",txDumpFileName,txDumpFileLength); ++ } ++#endif ++ //if buffer remains one space, notice upperr layer to block transmition. ++ // if (MHal_EMAC_TXQ_Full() || skb_queue_full(&(hemac->skb_queue_tx))) ++ // if (MHal_EMAC_TXQ_Full()) ++ if (skb_queue_full(&hemac->skb_queue_tx, 1)) ++ { ++ netif_stop_queue(dev); ++#if DYNAMIC_INT_TX ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 1); ++#endif ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ ++#if EMAC_FLOW_CONTROL_RX ++ if (hemac->isPausePkt) ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), NULL, VIRT2BUS(hemac->pu8PausePkt), hemac->u8PausePktSize, 1); ++ hemac->isPausePkt = 0; ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++#if EMAC_SG ++ { ++ int i; ++ int nr_frags = skb_shinfo(skb)->nr_frags; ++ int len; ++ ++ // dma_unmap_single(NULL, VIRT2PA(start), EMAC_MTU, DMA_TO_DEVICE); ++ if (nr_frags) ++ { ++ char* start = kmalloc(ALIGN(EMAC_MTU,256), GFP_ATOMIC); ++ char* p = start; ++ ++ if (!start) ++ { ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ ++ memcpy(p, skb->data, skb_headlen(skb)); ++ p += skb_headlen(skb); ++ len = skb_headlen(skb); ++ for (i = 0; i < nr_frags; i++) ++ { ++ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; ++#if EMAC_SG_BDMA ++ { ++ MSYS_DMA_COPY stDmaCopyCfg; ++ ++ Chip_Flush_Cache_Range((size_t)skb_frag_address(frag), skb_frag_size(frag)); ++ stDmaCopyCfg.phyaddr_src = (unsigned long long)VIRT2BUS(skb_frag_address(frag)); ++ stDmaCopyCfg.phyaddr_dst = (unsigned long long)VIRT2BUS(p); ++ stDmaCopyCfg.length = skb_frag_size(frag); ++ xx_msys_dma_copy(&stDmaCopyCfg); ++ } ++#else ++ memcpy(p, skb_frag_address(frag), skb_frag_size(frag)); ++#endif ++ p += skb_frag_size(frag); ++ len += skb_frag_size(frag); ++ } ++/* ++ if (len != skb->len) ++ printk("[%s][%d] strange ??? (len, skb->len) = (%d, %d)\n", __FUNCTION__, __LINE__, len, skb->len); ++*/ ++ if (EMAC_SG_BUF_CACHE) ++ Chip_Flush_Cache_Range((size_t)start, skb->len); ++ skb_addr = VIRT2BUS(start); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), (struct sk_buff*)0xFFFFFFFF, (dma_addr_t)skb_addr, skb->len, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ dev_kfree_skb_any(skb); ++ } ++ else ++ { ++ { ++ struct sk_buff* skb_tmp = skb_clone(skb, GFP_ATOMIC); ++ if (!skb_tmp) ++ { ++ printk("[%s][%d] skb_clone fail\n", __FUNCTION__, __LINE__); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ dev_kfree_skb_any(skb); ++ skb = skb_tmp; ++ } ++ skb_addr = VIRT2BUS(skb->data); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), skb, skb_addr, skb->len, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ Chip_Flush_Cache_Range((size_t)skb->data, skb->len); ++ } ++ if (nr_frags >= hemac->maxSG) ++ hemac->maxSG = nr_frags + 1; ++ } ++#else // #if #if EMAC_SG ++ ++#if DYNAMIC_INT_TX_TIMER ++ if ((DYNAMIC_INT_TX) && (0 == hemac->timerTxWdtPeriod)) ++#else ++ if (DYNAMIC_INT_TX) ++#endif ++ { ++ struct sk_buff* skb_tmp = skb_clone(skb, GFP_ATOMIC); ++ if (!skb_tmp) ++ { ++ printk("[%s][%d] skb_clone fail\n", __FUNCTION__, __LINE__); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ dev_kfree_skb_any(skb); ++ // kfree_skb(skb); ++ skb = skb_tmp; ++ } ++ skb_addr = VIRT2BUS(skb->data); ++ if (unlikely(0 == skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ // kfree_skb(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ goto out_unlock; ++ } ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), skb, skb_addr, skb->len, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ++ //set DMA address and trigger DMA ++ Chip_Flush_Cache_Range((size_t)skb->data, skb->len); ++#endif // #if #if EMAC_SG ++ ++ // txIdleCount = skb_queue_free(&hemac->skb_queue_tx, 0); ++ // if(min_tx_fifo_idle_count>txIdleCount) min_tx_fifo_idle_count=txIdleCount; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ netif_trans_update(dev); ++#else ++ dev->trans_start = jiffies; ++#endif ++out_unlock: ++ { ++/* ++ int bSkbFree = ((hemac->skb_tx_send & 0x0f) == 0) ? 1 : 0; ++ _MDev_EMAC_tx_pump(hemac, bSkbFree, 1); ++*/ ++ _MDev_EMAC_tx_pump(hemac, 1, 1); ++ } ++ ++/* ++#if DYNAMIC_INT_TX ++ // if ((hemac->skb_tx_send - hemac->skb_tx_free) > 32) ++ // if ((hemac->skb_tx_send & 0x0f) == 0) ++ // if ((hemac->skb_tx_send - hemac->skb_tx_free) >= DYNAMIC_INT_TX_TH) ++ if ((hemac->skb_tx_send - hemac->skb_tx_free) >= 64) ++ { ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 1); ++ } ++#endif ++*/ ++ spin_unlock_irqrestore(&hemac->mutexNetIf, flag1); ++ return ret; ++} ++ ++#if 0 //ajtest ++static int ajtest_recv_count=0; ++static ssize_t ajtest_recv_count_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ int val = simple_strtoul(buf, NULL, 10); ++ if(0==val) ++ { ++ ++ ajtest_recv_count=0; ++ } ++ return count; ++} ++static ssize_t ajtest_recv_count_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", ajtest_recv_count); ++} ++DEVICE_ATTR(ajtest_recv_count, 0644, ajtest_recv_count_show, ajtest_recv_count_store); ++ ++ ++unsigned int aj_checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++ ++static int aj_check(char *pData, int pktlen, int flag) ++{ ++ int res=0; ++ if(pktlen>32) ++ { ++ char *dbuf=(pData+0x36); ++ ++ if(0x51==dbuf[0] && 0x58==dbuf[1] && 0x91==dbuf[2] && 0x58==dbuf[3]) ++ { ++ int dlen=0; ++ int pktid=0; ++ int pktcs=0;//((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ int cs=0; ++ unsigned char *buf=(unsigned char *)(dbuf+8); ++ ++ dlen=(dbuf[7]<<24) + (dbuf[6]<<16)+(dbuf[5]<<8) + (dbuf[4]); ++ pktid=(dbuf[11]<<24) + (dbuf[10]<<16)+(dbuf[9]<<8) + (dbuf[8]); ++ ++// printf("pktCount: %08d\n",pktCount); ++ pktcs=((buf[dlen-1])<<24) + (buf[dlen-2]<<16)+(buf[dlen-3]<<8) + (buf[dlen-4]); ++ cs=aj_checksum(buf,dlen-4); ++ if(pktcs!=cs) ++ { ++// int j=0; ++// unsigned int lc=0; ++ printk(KERN_WARNING"<[!! AJ_ERR %d, %d: 0x%08X, 0x%08X, %d ]>\n\n",ajtest_recv_count,pktid,cs,pktcs,flag); ++ res=-1; ++// for(j=0;j\n",ajss_recv_count,pktid,cs,pktcs,flag); ++// } ++ ++ ajtest_recv_count++; ++ } ++ } ++ return res; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Disable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_rx(struct net_device *dev, int budget) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 received=0; ++ struct sk_buff *skb; ++ struct sk_buff *clean_skb; ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ // unsigned long flags; ++ ++ if (0 == budget) ++ return 0; ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ ++ // spin_lock_irqsave(&hemac->mutexRXD, flags); ++ // If any Ownership bit is 1, frame received. ++ do ++ { ++ char* pData; ++ struct rbf_t* desc = &(rxinfo->desc[rxinfo->idx]); ++ ++ // if(!((dlist->descriptors[hemac->rxBuffIndex].addr) & EMAC_DESC_DONE)) ++ if (!(desc->addr & EMAC_DESC_DONE)) ++ { ++ break; ++ } ++ // p_recv = (char *) ((((dlist->descriptors[hemac->rxBuffIndex].addr) & 0xFFFFFFFFUL) + RAM_VA_PA_OFFSET + MIU0_BUS_BASE) &~(EMAC_DESC_DONE | EMAC_DESC_WRAP)); ++ ++#if RX_DESC_API ++ p_recv = RX_ADDR_GET(desc); ++#else ++ p_recv = BUS2VIRT(CLR_BITS(desc->addr, EMAC_DESC_DONE | EMAC_DESC_WRAP)); ++#endif ++ pktlen = desc->size & 0x7ffUL; /* Length of frame including FCS */ ++ ++ #if RX_THROUGHPUT_TEST ++ receive_bytes += pktlen; ++ #endif ++ ++ if (unlikely(((pktlen > EMAC_MTU) || (pktlen < 64)))) ++ { ++ EMAC_ERR("drop packet!!(pktlen = %d)", pktlen); ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ Chip_Flush_MIU_Pipe(); ++ rxinfo->idx++; ++ if (rxinfo->idx >= rxinfo->num_desc) ++ rxinfo->idx = 0; ++ hemac->stats.rx_length_errors++; ++ hemac->stats.rx_errors++; ++ hemac->stats.rx_dropped++; ++ continue; ++ } ++ ++ if (unlikely(!(clean_skb = alloc_skb (EMAC_PACKET_SIZE_MAX, GFP_ATOMIC)))) ++ { ++ // printk(KERN_ERR"Can't alloc skb.[%s]%d\n",__FUNCTION__,__LINE__);; ++ goto jmp_rx_exit; ++ // return -ENOMEM; ++ } ++ skb = rxinfo->skb_arr[rxinfo->idx]; ++ #if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ dma_unmap_single(NULL, VIRT2PA(p_recv), pktlen, DMA_FROM_DEVICE); ++ memcpy(skb->data, p_recv, pktlen); ++ pktlen -= 4; /* Remove FCS */ ++ pData = skb_put(skb, pktlen); ++ } ++ else ++ #endif ++ { ++ pktlen -= 4; /* Remove FCS */ ++ pData = skb_put(skb, pktlen); ++ dma_unmap_single(NULL, VIRT2PA(pData), pktlen, DMA_FROM_DEVICE); ++ } ++ ++ //ajtest ++ /* below code is used to find the offset of ajtest header in incoming packet ++ for(cidx=0;cidx=pktlen) ++ { ++ break; ++ } ++ if(0x51==pData[cidx] && 0x58==pData[cidx+1] && 0x91==pData[cidx+2] && 0x58==pData[cidx+3]) ++ { ++ printk(KERN_WARNING"cidx: 0x%08X\n",cidx); ++ break; ++ } ++ } ++ */ ++#if defined(PACKET_DUMP) ++ if(1==rxDumpCtrl && NULL!=rxDumpFile) ++ { ++ rxDumpFileLength+=msys_kfile_write(rxDumpFile,rxDumpFileLength,pData,pktlen); ++ } ++ else if(2==rxDumpCtrl && NULL!=rxDumpFile) ++ { ++ msys_kfile_close(rxDumpFile); ++ rxDumpFile=NULL; ++ printk(KERN_WARNING"close emac rx_dump file '%s', len=0x%08X...\n",rxDumpFileName,rxDumpFileLength); ++ } ++#endif ++ ++ skb->dev = dev; ++ skb->protocol = eth_type_trans (skb, dev); ++ //skb->len = pktlen; ++ dev->last_rx = jiffies; ++ hemac->stats.rx_bytes += pktlen; ++#if EMAC_FLOW_CONTROL_TX ++ if (0 == MHal_EMAC_FlowControl_TX(hemac)) ++ { ++ _MDrv_EMAC_Pause_TX(dev, skb, p_recv); ++ } ++#endif // #if EMAC_FLOW_CONTROL_TX ++ #if RX_THROUGHPUT_TEST ++ kfree_skb(skb); ++ #else ++ ++ #if RX_CHECKSUM ++ if (((desc->size & EMAC_DESC_TCP) || (desc->size & EMAC_DESC_UDP)) && ++ (desc->size & EMAC_DESC_IP_CSUM) && ++ (desc->size & EMAC_DESC_TCP_UDP_CSUM)) ++ { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ skb->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ #ifdef ISR_BOTTOM_HALF ++ netif_rx_ni(skb); ++ #elif MSTAR_EMAC_NAPI ++ #if (EMAC_GSO) ++ napi_gro_receive(&hemac->napi, skb); ++ #else ++ netif_receive_skb(skb); ++ #endif ++ #else ++ netif_rx (skb); ++ #endif ++ ++ received++; ++ #endif/*RX_THROUGHPUT_TEST*/ ++ ++ // if (dlist->descriptors[hemac->rxBuffIndex].size & EMAC_MULTICAST) ++ if (desc->size & EMAC_MULTICAST) ++ { ++ hemac->stats.multicast++; ++ } ++ ++ //fill clean_skb into RX descriptor ++ rxinfo->skb_arr[rxinfo->idx] = clean_skb; ++ ++#if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ if (rxinfo->idx == (rxinfo->num_desc-1)) ++ desc->addr = VIRT2BUS(p_recv) | EMAC_DESC_DONE | EMAC_DESC_WRAP; ++ else ++ desc->addr = VIRT2BUS(p_recv) | EMAC_DESC_DONE; ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ dma_map_single(NULL, p_recv, EMAC_PACKET_SIZE_MAX, DMA_FROM_DEVICE); ++ } ++ else ++#endif ++ { ++#if RX_DESC_API ++ RX_DESC_MAKE(desc, VIRT2BUS(skb->data), (rxinfo->idx == (rxinfo->num_desc-1)) ? EMAC_DESC_WRAP : 0); ++#else ++ if (rxinfo->idx == (rxinfo->num_desc-1)) ++ desc->addr = VIRT2BUS(clean_skb->data) | EMAC_DESC_DONE | EMAC_DESC_WRAP; ++ else ++ desc->addr = VIRT2BUS(clean_skb->data) | EMAC_DESC_DONE; ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++#endif ++ dma_map_single(NULL, clean_skb->data, EMAC_PACKET_SIZE_MAX, DMA_FROM_DEVICE); ++ } ++ Chip_Flush_MIU_Pipe(); ++ ++ rxinfo->idx++; ++ if (rxinfo->idx >= rxinfo->num_desc) ++ rxinfo->idx = 0; ++ ++#if MSTAR_EMAC_NAPI ++ // if(received >= EMAC_NAPI_WEIGHT) { ++ if(received >= budget) { ++ break; ++ } ++#endif ++ ++ } while(1); ++ ++jmp_rx_exit: ++ // spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++ if(received>max_rx_packet_count)max_rx_packet_count=received; ++ rx_packet_cnt += received; ++ return received; ++} ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++//MAC interrupt handler ++//(Interrupt delay enable) ++//------------------------------------------------------------------------------------------------- ++static int RBNA_detailed=0; ++ ++static u32 _MDrv_EMAC_ISR_RBNA(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = NULL; ++ int empty=0; ++ int idx; ++ rx_desc_queue_t* rxinfo; ++ ++ if (0 == (intstatus & EMAC_INT_RBNA)) ++ return 0; ++ ++ hemac = (struct emac_handle*) netdev_priv(dev); ++ rxinfo = &(hemac->rx_desc_queue); ++ ++ hemac->stats.rx_missed_errors++; ++ ++ //write 1 clear ++ MHal_EMAC_Write_RSR(hemac->hal, EMAC_BNA); ++ if(RBNA_detailed>0) ++ { ++ // u32 u32RBQP_Addr = MHal_EMAC_Read_RBQP(hemac->hal)- VIRT2BUS(rxinfo->desc); ++ for(idx=0;idxnum_desc;idx++) ++ { ++ // if(!((dlist->descriptors[idx].addr) & EMAC_DESC_DONE)) ++ if (!(rxinfo->desc[idx].addr & EMAC_DESC_DONE)) ++ { ++ empty++; ++ } ++ else ++ { ++ printk(KERN_ERR"RBNA: [0x%X]\n",idx); ++ } ++ ++ } ++ // printk(KERN_ERR"RBNA: empty=0x%X, rxBuffIndex=0x%X, rx_missed_errors=%ld RBQP_offset=0x%x\n",empty, rxinfo->idx, hemac->stats.rx_missed_errors,u32RBQP_Addr); ++ } ++#if 0 ++ if (1) ++ { ++ struct rbf_t* desc = NULL; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexRXD, flags); ++ for (idx=0;idxnum_desc;idx++) ++ { ++ desc = &(rxinfo->desc[idx]); ++ if (idx == (rxinfo->num_desc-1)) ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE) | EMAC_DESC_WRAP; ++ else ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ desc->size = 0; ++ } ++ spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++ Chip_Flush_MIU_Pipe(); ++ } ++#endif ++ ++ hemac->irq_count[IDX_CNT_INT_RBNA]++; ++ //printk("RBNA\n"); ++#if REDUCE_CPU_FOR_RBNA ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexIntRX, flags); ++ if (0 == timer_pending(&hemac->timerIntRX)) ++ { ++ MHal_EMAC_RX_ParamSet(hemac->hal, 0xff, 0xff); ++ hemac->timerIntRX.expires = jiffies + HZ; ++ add_timer(&hemac->timerIntRX); ++ } ++ spin_unlock_irqrestore(&hemac->mutexIntRX, flags); ++ } ++#endif // #if REDUCE_CPU_FOR_RBNA ++ // gu32GatingRxIrqTimes = 1; ++ return 1; ++} ++ ++static u32 _MDrv_EMAC_ISR_TCOM(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = NULL; ++ ++ if (0 == (intstatus & EMAC_INT_TCOM)) ++ return 0; ++ ++ hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_High(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ hemac->tx_irqcnt++; ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (EMAC_INT_TUND | EMAC_INT_RTRY)) ++ { ++ hemac->stats.tx_errors += 1; ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ // MHal_EMAC_Write_TSR(EMAC_UND); ++ ++ //Reset TX engine ++ MDev_EMAC_TxReset(dev); ++ EMAC_ERR ("Transmit TUND error, TX reset\n"); ++ hemac->irq_count[IDX_CNT_INT_TUND]++; ++ } ++ hemac->irq_count[IDX_CNT_INT_RTRY]++; ++ } ++ ++ #if TX_THROUGHPUT_TEST ++ MDev_EMAC_tx(pseudo_packet, dev); ++ #endif ++ ++#if 0 ++ // _MDev_EMAC_tx_free(hemac); ++ _MDev_EMAC_tx_pump(hemac, 1, 0); ++ ++ // if (netif_queue_stopped (dev) && skb_queue_free(&hemac->skb_queue_tx, 1)) // ?? ++ if (netif_queue_stopped (dev) && skb_queue_free(&hemac->skb_queue_tx, 0)) // 35% ++ // if (netif_queue_stopped (dev) && (skb_queue_free(&hemac->skb_queue_tx, 0)> 80)) // 27.5% ++ // if (netif_queue_stopped (dev) && (skb_queue_free(&hemac->skb_queue_tx, 0) > (skb_queue_size(&hemac->skb_queue_tx, 0) >> 1))) // 29.7% ++ // if (((skb_queue_size(&hemac->skb_queue_tx, 1)>>1) < skb_queue_free(&hemac->skb_queue_tx, 1)) && netif_queue_stopped (dev)) // 45% ++ // if (netif_queue_stopped (dev) && (skb_queue_free(&hemac->skb_queue_tx, 0) > (skb_queue_size(&hemac->skb_queue_tx, 0)/3))) // 28.3% ++ { ++#if DYNAMIC_INT_TX ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 0); ++#endif ++#if EMAC_FLOW_CONTROL_TX ++ // if (0 == hemac->isPauseTX) ++ if (0 == timer_pending(&hemac->timerFlowTX)) ++ netif_wake_queue(dev); ++#else // #if EMAC_FLOW_CONTROL_TX ++ netif_wake_queue(dev); ++#endif ++ } ++#endif ++ hemac->irq_count[IDX_CNT_INT_TCOM]++; ++ return 1; ++} ++ ++static u32 _MDrv_EMAC_ISR_DONE(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle* hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (0 == (intstatus&EMAC_INT_DONE)) ++ return 0; ++ hemac->irq_count[IDX_CNT_INT_DONE]++; ++ return 1; ++} ++ ++static u32 _MDrv_EMAC_ISR_ROVR(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++#if EMAC_FLOW_CONTROL_RX ++#if EMAC_FLOW_CONTROL_RX_TEST ++ { ++ static int cnt = 0; ++ cnt++; ++ ++ if (0 == (cnt & 0xF)) ++ _MDrv_EMAC_PausePkt_Send(dev); ++ return 0; ++ } ++#endif ++#endif ++ ++ if (0 == (intstatus & EMAC_INT_ROVR)) ++ { ++ hemac->contiROVR = 0; ++ return 0; ++ } ++ ++ hemac->stats.rx_over_errors++; ++ hemac->contiROVR++; ++ //write 1 clear ++ MHal_EMAC_Write_RSR(hemac->hal, EMAC_RSROVR); ++#if EMAC_FLOW_CONTROL_RX ++ if (hemac->contiROVR < 3) ++ { ++ _MDrv_EMAC_PausePkt_Send(dev); ++ } ++ else ++ { ++ MDev_EMAC_SwReset(dev); ++ } ++#endif ++ hemac->irq_count[IDX_CNT_INT_ROVR]++; ++ return 0; ++} ++ ++static u32 _MDrv_EMAC_ISR_RCOM(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = NULL; ++ ++ hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (intstatus & EMAC_INT_RCOM_DELAY) ++ { ++ hemac->irq_count[IDX_CNT_JULIAN_D]++; ++ } ++ else if (intstatus & EMAC_INT_RCOM) ++ { ++ intstatus |= EMAC_INT_RCOM_DELAY; ++ hemac->irq_count[IDX_CNT_INT_RCOM]++; ++ } ++ ++ // Receive complete // ++ if (intstatus & EMAC_INT_RCOM_DELAY) ++ { ++ if ((0 == rx_time_last.tv_sec) && (0 == rx_time_last.tv_nsec)) ++ { ++ getnstimeofday(&rx_time_last); ++ } ++ else ++ { ++ struct timespec ct; ++ int duration; ++ ++ getnstimeofday(&ct); ++ duration = (ct.tv_sec - rx_time_last.tv_sec)*1000 + (ct.tv_nsec - rx_time_last.tv_nsec)/1000000; ++ rx_duration_max = (rx_duration_max < duration) ? duration : rx_duration_max; ++ rx_time_last = ct; ++ } ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_High(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ #if MSTAR_EMAC_NAPI ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ if (napi_schedule_prep(&hemac->napi)) ++ { ++ // MDEV_EMAC_DISABLE_RX_REG(); ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_RCOM, 0); ++ __napi_schedule(&hemac->napi); ++ } ++ else ++ { ++ // printk("[%s][%d] NAPI RX cannot be scheduled\n", __FUNCTION__, __LINE__); ++ } ++ #elif defined ISR_BOTTOM_HALF ++ /*Triger rx_task*/ ++ schedule_work(&hemac->rx_task); ++ #else ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexRXInt, flags); ++ MDev_EMAC_rx(dev, 0x0FFFFFFF); ++ spin_unlock_irqrestore(&hemac->mutexRXInt, flags); ++ } ++ #endif ++ } ++ return intstatus; ++} ++ ++irqreturn_t MDev_EMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 intstatus=0; ++ ++ hemac->irqcnt++; ++ hemac->oldTime = getCurMs(); ++ _MDev_EMAC_tx_pump(hemac, 1, 0); ++ while ((intstatus = MHal_EMAC_IntStatus(hemac->hal))) ++ { ++ _MDrv_EMAC_ISR_RBNA(dev, intstatus); ++ _MDrv_EMAC_ISR_TCOM(dev, intstatus); ++ _MDrv_EMAC_ISR_DONE(dev, intstatus); ++ _MDrv_EMAC_ISR_ROVR(dev, intstatus); ++ _MDrv_EMAC_ISR_RCOM(dev, intstatus); ++ } ++ ++ if (netif_queue_stopped (dev) && skb_queue_free(&hemac->skb_queue_tx, 0)) ++ { ++#if DYNAMIC_INT_TX ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 0); ++#endif ++#if EMAC_FLOW_CONTROL_TX ++ if (0 == timer_pending(&hemac->timerFlowTX)) ++ netif_wake_queue(dev); ++#else // #if EMAC_FLOW_CONTROL_TX ++ netif_wake_queue(dev); ++#endif ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++#if DYNAMIC_INT_RX ++#define emac_time_elapse(start) \ ++({ \ ++ unsigned long delta; \ ++ struct timespec ct; \ ++ getnstimeofday(&ct); \ ++ delta = (ct.tv_sec - (start).tv_sec)*1000 + (ct.tv_nsec - (start).tv_nsec)/1000000; \ ++ (delta); \ ++}) ++#endif // #if DYNAMIC_INT_RX ++ ++#if MSTAR_EMAC_NAPI ++static int MDev_EMAC_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct emac_handle *hemac = container_of(napi, struct emac_handle,napi); ++ struct net_device *dev = hemac->netdev; ++ int work_done = 0; ++ int budget_rmn = budget; ++#if DYNAMIC_INT_RX ++ unsigned long elapse = 0; ++ unsigned long packets = 0; ++#endif // #if DYNAMIC_INT_RX ++ ++// rx_poll_again: ++ work_done = MDev_EMAC_rx(dev, budget_rmn); ++ ++ if (work_done) ++ { ++ // budget_rmn -= work_done; ++ // goto rx_poll_again; ++ } ++#if DYNAMIC_INT_RX ++ if (hemac->rx_stats_enable) ++ { ++ if (0xFFFFFFFF == hemac->rx_stats_packet) ++ { ++ getnstimeofday(&hemac->rx_stats_time); ++ hemac->rx_stats_packet = 0; ++ } ++ hemac->rx_stats_packet += work_done; ++ if ((elapse = emac_time_elapse(hemac->rx_stats_time))>= 1000) ++ { ++ packets = hemac->rx_stats_packet; ++ packets *= 1000; ++ packets /= elapse; ++ ++#if REDUCE_CPU_FOR_RBNA ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexIntRX, flags); ++ if (0 == timer_pending(&hemac->timerIntRX)) ++ { ++#endif // #if REDUCE_CPU_FOR_RBNA ++ // printk("[%s][%d] packet for delay number (elapse, current, packet) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, (int)elapse, (int)hemac->rx_stats_packet, (int)packets); ++ // MHal_EMAC_RX_ParamSet(hemac->hal, packets/200 + 2, 0xFFFFFFFF); ++ MHal_EMAC_RX_ParamSet(hemac->hal, packets/200 + 1, 0xFFFFFFFF); ++#if REDUCE_CPU_FOR_RBNA ++ } ++ spin_unlock_irqrestore(&hemac->mutexIntRX, flags); ++ } ++#endif // #if REDUCE_CPU_FOR_RBNA ++ hemac->rx_stats_packet = 0; ++ getnstimeofday(&hemac->rx_stats_time); ++ } ++ } ++#endif ++ ++/* ++ if (work_done == budget_rmn) ++ return budget; ++*/ ++ ++ napi_gro_flush(napi, false); ++ ++#if 1 ++ /* If budget not fully consumed, exit the polling mode */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_RCOM, 1); ++ } ++ return work_done; ++#else ++ napi_complete(napi); ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_RCOM, 1); ++ return budget + work_done - budget_rmn; ++#endif ++} ++#endif ++ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++irqreturn_t MDev_EMAC_interrupt_cable_unplug(int irq,void *dev_instance) ++{ ++ struct net_device* dev = (struct net_device*)dev_instance; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ unsigned long flags; ++ ++ if (netif_carrier_ok(dev)) ++ netif_carrier_off(dev); ++ if (!netif_queue_stopped(dev)) ++ netif_stop_queue(dev); ++ hemac->ThisBCE.connected = 0; ++ ++ #ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(dev); ++ #endif ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ MDrv_GPIO_Set_Low(hemac->led_green); ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++void MDev_EMAC_HW_init(struct net_device* dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 word_ETH_CTL = 0x00000000UL; ++ // u32 word_ETH_CFG = 0x00000800UL; ++ // u32 uNegPhyVal = 0; ++ u32 idxRBQP = 0; ++ // u32 RBQP_offset = 0; ++ struct sk_buff *skb = NULL; ++ // u32 RBQP_rx_skb_addr = 0; ++ // unsigned long flags; ++ ++ // (20071026_CHARLES) Disable TX, RX and MDIO: (If RX still enabled, the RX buffer will be overwrited) ++ MHal_EMAC_Write_CTL(hemac->hal, word_ETH_CTL); ++ MHal_EMAC_Write_BUFF(hemac->hal, 0x00000000UL); ++ // Set MAC address ------------------------------------------------------ ++ MHal_EMAC_Write_SA1_MAC_Address(hemac->hal, hemac->sa[0][0], hemac->sa[0][1], hemac->sa[0][2], hemac->sa[0][3], hemac->sa[0][4], hemac->sa[0][5]); ++ MHal_EMAC_Write_SA2_MAC_Address(hemac->hal, hemac->sa[1][0], hemac->sa[1][1], hemac->sa[1][2], hemac->sa[1][3], hemac->sa[1][4], hemac->sa[1][5]); ++ MHal_EMAC_Write_SA3_MAC_Address(hemac->hal, hemac->sa[2][0], hemac->sa[2][1], hemac->sa[2][2], hemac->sa[2][3], hemac->sa[2][4], hemac->sa[2][5]); ++ MHal_EMAC_Write_SA4_MAC_Address(hemac->hal, hemac->sa[3][0], hemac->sa[3][1], hemac->sa[3][2], hemac->sa[3][3], hemac->sa[3][4], hemac->sa[3][5]); ++ ++ // spin_lock_irqsave(&hemac->mutexRXD, flags); ++ { ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(dev); ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++#if EXT_PHY_PATCH ++ char* p = hemac->pu8RXBuf; ++#endif ++ ++ // Initialize Receive Buffer Descriptors ++ memset(rxinfo->desc, 0x00, rxinfo->size_desc_queue); ++ ++ for(idxRBQP = 0; idxRBQP < rxinfo->num_desc; idxRBQP++) ++ { ++ struct rbf_t* desc = &(rxinfo->desc[idxRBQP]); ++ ++ if (!(skb = alloc_skb (EMAC_PACKET_SIZE_MAX, GFP_ATOMIC))) { ++ // printk("%s %d: alloc skb failed!\n",__func__, __LINE__); ++ panic("can't alloc skb"); ++ } ++ rxinfo->skb_arr[idxRBQP] = skb; ++#if RX_DESC_API ++ RX_DESC_MAKE(desc, VIRT2BUS(skb->data), (idxRBQP < (rxinfo->num_desc- 1)) ? 0 : EMAC_DESC_WRAP); ++#else ++ #if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ if(idxRBQP < (rxinfo->num_desc- 1)) ++ desc->addr = VIRT2BUS(p); ++ else ++ desc->addr = VIRT2BUS(p) | EMAC_DESC_WRAP; ++ p += EMAC_PACKET_SIZE_MAX; ++ } ++ else ++ #endif ++ { ++ if(idxRBQP < (rxinfo->num_desc- 1)) ++ desc->addr = VIRT2BUS(skb->data); ++ else ++ desc->addr = VIRT2BUS(skb->data) | EMAC_DESC_WRAP; ++ } ++#endif ++ } ++ Chip_Flush_MIU_Pipe(); ++ // Initialize "Receive Buffer Queue Pointer" ++ MHal_EMAC_Write_RBQP(hemac->hal, VIRT2BUS(rxinfo->desc)); ++ } ++ // spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++ ++#if 0 ++ if (!hemac->ThisUVE.initedEMAC) ++ { ++#if 0 // should move to phy driver ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_SW) ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_ADVERTISE, 0xDE1UL); //BIT0|BIT5~8|BIT10|BIT11 //pause disable transmit, enable receive ++#endif ++#endif ++ // MHal_EMAC_Write_JULIAN_0100(hemac->hal, JULIAN_100_VAL); ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, 0); ++ ++ hemac->ThisUVE.flagPowerOn = 1; ++ hemac->ThisUVE.initedEMAC = 1; ++ } ++#endif ++ MHal_EMAC_HW_init(hemac->hal); ++} ++ ++static void* MDev_EMAC_RX_Desc_Init(struct emac_handle *hemac, void* p) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ rxinfo->num_desc = RX_DESC_NUM; ++ rxinfo->size_desc_queue = RX_DESC_QUEUE_SIZE; ++#if 0 ++ mem_info.length = rxinfo->size_desc_queue; ++ strcpy(mem_info.name, "EMAC_BUFF"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ panic("unable to locate DMEM for EMAC alloRAM!! %d\n", rxinfo->size_desc_queue); ++ } ++ // rxinfo->descPhys = (dma_addr_t)mem_info.phys; ++#endif ++ rxinfo->desc = (struct rbf_t*)p; ++ ++ // EMAC_DBG("alloRAM_VA_BASE=0x%zx alloRAM_PA_BASE=0x%zx\n alloRAM_SIZE=0x%zx\n", (size_t) rxinfo->desc,(size_t) rxinfo->descPhys,(size_t)rxinfo->size_desc_queue); ++ BUG_ON(!rxinfo->desc); ++ ++ rxinfo->idx = 0; ++ memset(rxinfo->desc, 0x00, rxinfo->size_desc_queue); ++ Chip_Flush_MIU_Pipe(); ++ ++ rxinfo->skb_arr = kzalloc(rxinfo->num_desc*sizeof(struct sk_buff*), GFP_KERNEL); ++ BUG_ON(!rxinfo->skb_arr); ++ ++ EMAC_DBG("RAM_VA_BASE=0x%08x\n", rxinfo->desc); ++ EMAC_DBG("RAM_PA_BASE=0x%08x\n", VIRT2PA(rxinfo->desc)); ++ EMAC_DBG("RAM_VA_PA_OFFSET=0x%08x\n", rxinfo->off_va_pa); ++ EMAC_DBG("RBQP_BASE=0x%08x size=0x%x\n", VIRT2BUS(rxinfo->desc), rxinfo->size_desc_queue); ++ return (void*)(((int)p)+RX_DESC_QUEUE_SIZE); ++} ++ ++static void MDev_EMAC_RX_Desc_Free(struct emac_handle *hemac) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ if (rxinfo->skb_arr) ++ { ++ kfree(rxinfo->skb_arr); ++ rxinfo->skb_arr = NULL; ++ } ++ ++ rxinfo->desc = NULL; ++ rxinfo->idx = 0; ++ rxinfo->num_desc = 0; ++ rxinfo->size_desc_queue = 0; ++} ++ ++static void MDev_EMAC_RX_Desc_Reset(struct emac_handle *hemac) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ rxinfo->idx = 0; ++ memset(rxinfo->desc, 0x00, rxinfo->size_desc_queue); ++ Chip_Flush_MIU_Pipe(); ++} ++ ++static void MDev_EMAC_MemFree(struct emac_handle *hemac) ++{ ++ if (hemac->mem_info.length) ++ { ++ msys_release_dmem(&hemac->mem_info); ++ memset(&hemac->mem_info, 0, sizeof(hemac->mem_info)); ++ } ++} ++ ++static void* MDev_EMAC_MemAlloc(struct emac_handle *hemac, u32 size) ++{ ++ int ret; ++ ++ hemac->mem_info.length = size; ++ // strcpy(hemac->mem_info.name, "EMAC_BUFF"); ++ sprintf(hemac->mem_info.name, "%s_buff", hemac->name); ++ if((ret=msys_request_dmem(&hemac->mem_info))) ++ { ++ memset(&hemac->mem_info, 0, sizeof(hemac->mem_info)); ++ panic("unable to locate DMEM for EMAC alloRAM!! %d\n", size); ++ return NULL; ++ } ++ return (void*)((size_t)hemac->mem_info.kvirt); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC init Variable ++//------------------------------------------------------------------------------------------------- ++// extern phys_addr_t memblock_start_of_DRAM(void); ++// extern phys_addr_t memblock_size_of_first_region(void); ++ ++static void* MDev_EMAC_VarInit(struct emac_handle *hemac) ++{ ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ int txd_len; ++ void* p = NULL; ++#if EMAC_FLOW_CONTROL_RX ++ static u8 pause_pkt[] = ++ { ++ //DA - multicast ++ 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01, ++ //SA ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ //Len-Type ++ 0x88, 0x08, ++ //Ctrl code ++ 0x00, 0x01, ++ //Ctrl para 8192 ++ 0x20, 0x00 ++ }; ++ int pausePktSize = sizeof(pause_pkt); ++ static u8 ETH_PAUSE_FRAME_DA_MAC[6] = { 0x01UL, 0x80UL, 0xC2UL, 0x00UL, 0x00UL, 0x01UL }; ++#else ++ int pausePktSize = 0; ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++/* ++#if EMAC_SG ++ int txBufSize = MHal_EMAC_TXQ_Size(hemac->hal) * EMAC_MTU; ++#else ++ int txBufSize = 0; ++#endif ++*/ ++ ++ // TXD init ++ txd_len = MHal_EMAC_TXD_Cfg(hemac->hal, hemac->txd_num); ++#if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ #if (EMAC_SG && EMAC_SG_BUF_CACHE) ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + (RX_DESC_NUM * EMAC_PACKET_SIZE_MAX) + txd_len + pausePktSize); ++ #else ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + (RX_DESC_NUM * EMAC_PACKET_SIZE_MAX) + txd_len + pausePktSize + txBufSize); ++ #endif ++ } ++ else ++#endif // #if EXT_PHY_PATCH ++ { ++ #if (EMAC_SG && EMAC_SG_BUF_CACHE) ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + txd_len + pausePktSize); ++ #else ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + txd_len + pausePktSize + txBufSize); ++ #endif ++ } ++ if (NULL == p) ++ { ++ printk("[%s][%d] alloc memory fail %d\n", __FUNCTION__, __LINE__, RX_DESC_QUEUE_SIZE + txd_len); ++ return NULL; ++ } ++/* ++#if (EMAC_SG && EMAC_SG_BUF_CACHE) ++ if (NULL == (hemac->pTxBuf = kmalloc(txBufSize, GFP_KERNEL))) ++ { ++ printk("[%s][%d] kmalloc fail %d\n", __FUNCTION__, __LINE__, txBufSize); ++ MDev_EMAC_MemFree(hemac); ++ return NULL; ++ } ++#endif ++*/ ++ if (txd_len) ++ { ++ MHal_EMAC_TXD_Buf(hemac->hal, p, VIRT2BUS(p), txd_len); ++ p = (void*)(((size_t)p) + txd_len); ++ } ++ ++#if EXT_PHY_PATCH ++ { ++ int start, end; ++ start = (int) p; ++ p = MDev_EMAC_RX_Desc_Init(hemac, p); ++ if (IS_EXT_PHY(hemac)) ++ { ++ hemac->pu8RXBuf = (char*)p; ++ p = (void*) (hemac->pu8RXBuf + (RX_DESC_NUM * EMAC_PACKET_SIZE_MAX)); ++ end = (int) p; ++ MHal_EMAC_MIU_Protect_RX(hemac->hal, VIRT2BUS((void*)start), VIRT2BUS((void*)end)); ++ } ++ else ++ { ++ hemac->pu8RXBuf = NULL; ++ } ++ } ++#else ++ p = MDev_EMAC_RX_Desc_Init(hemac, p); ++#endif ++ ++#if EMAC_FLOW_CONTROL_RX ++ hemac->isPausePkt = 0; ++ hemac->u8PausePktSize = pausePktSize; ++ hemac->pu8PausePkt = (pausePktSize) ? p : NULL; ++ if (pausePktSize) ++ { ++ memcpy(hemac->pu8PausePkt, pause_pkt, pausePktSize); ++ } ++ p = (void*)(((char*)p) + pausePktSize); ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++#if EMAC_SG ++/* ++ if (NULL == hemac->pTxBuf) ++ hemac->pTxBuf = (txBufSize) ? (char*)p : NULL; ++ hemac->TxBufIdx = 0; ++*/ ++ hemac->maxSG = 0; ++#endif // #if EMAC_SG ++ ++ memset(hemac->sa, 0, sizeof(hemac->sa)); ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_EMAC_get_SA1H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA1L_addr(hemac->hal); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy(&hemac->sa[0][0], &addr, 6); ++ } ++ else ++ { ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_EMAC_get_SA2H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA2L_addr(hemac->hal); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy(&hemac->sa[0][0], &addr, 6); ++ } ++ else ++ { ++ memcpy(&hemac->sa[0][0], MY_MAC, 6); ++ } ++ } ++#if EMAC_FLOW_CONTROL_RX ++ memcpy(&hemac->sa[1][0], ETH_PAUSE_FRAME_DA_MAC, 6); ++#endif ++ return p; ++} ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void MDev_EMAC_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ MDev_EMAC_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++#if KERNEL_PHY ++static void emac_phy_link_adjust(struct net_device *dev) ++{ ++ int cam = 0; // 0:No CAM, 1:Yes ++ int rcv_bcast = 1; // 0:No, 1:Yes ++ int rlf = 0; ++ u32 word_ETH_CFG = 0x00000800UL; ++ struct emac_handle* hemac =(struct emac_handle*) netdev_priv(dev); ++ unsigned long flag1; ++ ++ spin_lock_irqsave(&hemac->mutexNetIf, flag1); ++ if (!hemac->bEthCfg) ++ { ++ // ETH_CFG Register ----------------------------------------------------- ++ // (20070808) IMPORTANT: REG_ETH_CFG:bit1(FD), 1:TX will halt running RX frame, 0:TX will not halt running RX frame. ++ // If always set FD=0, no CRC error will occur. But throughput maybe need re-evaluate. ++ // IMPORTANT: (20070809) NO_MANUAL_SET_DUPLEX : The real duplex is returned by "negotiation" ++ word_ETH_CFG = 0x00000800UL; // Init: CLK = 0x2 ++ if (SPEED_100 == dev->phydev->speed) ++ word_ETH_CFG |= 0x00000001UL; ++ if (DUPLEX_FULL == dev->phydev->duplex) ++ word_ETH_CFG |= 0x00000002UL; ++ if (cam) ++ word_ETH_CFG |= 0x00000200UL; ++ if (0 == rcv_bcast) ++ word_ETH_CFG |= 0x00000020UL; ++ if (1 == rlf) ++ word_ETH_CFG |= 0x00000100UL; ++ ++ MHal_EMAC_Write_CFG(hemac->hal, word_ETH_CFG); ++ hemac->bEthCfg = 1; ++ } ++ ++ if (dev->phydev->link) ++ { ++ MHal_EMAC_update_speed_duplex(hemac->hal, dev->phydev->speed, dev->phydev->duplex); ++ netif_carrier_on(dev); ++ netif_start_queue(dev); ++ printk("[%s] EMAC Link Up \n", __FUNCTION__); ++ } ++ else ++ { ++ // unsigned long flags; ++ ++ if (!netif_queue_stopped(dev)) ++ netif_stop_queue(dev); ++ if (netif_carrier_ok(dev)) ++ netif_carrier_off(dev); ++ // spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ // skb_queue_reset(&(hemac->skb_queue_tx)); ++ // spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ printk("[%s] EMAC Link Down \n", __FUNCTION__); ++ } ++ spin_unlock_irqrestore(&hemac->mutexNetIf, flag1); ++ ++#if 0 ++ printk("[%s][%d] adjust phy (link, speed, duplex) = (%d, %d, %d, %d)\n", __FUNCTION__, __LINE__, ++ dev->phydev->link, dev->phydev->speed, dev->phydev->duplex, dev->phydev->autoneg); ++#endif ++} ++ ++static int emac_phy_connect(struct net_device* netdev) ++{ ++ struct emac_handle* hemac =(struct emac_handle*) netdev_priv(netdev); ++ struct device_node* np = NULL; ++ struct phy_device *phydev; ++ ++ np = of_parse_phandle(netdev->dev.of_node, "phy-handle", 0); ++ if (!np && of_phy_is_fixed_link(netdev->dev.of_node)) ++ if (!of_phy_register_fixed_link(netdev->dev.of_node)) ++ np = of_node_get(netdev->dev.of_node); ++ if (!np) ++ { ++ printk("[%s][%d] can not find phy-handle in dts\n", __FUNCTION__, __LINE__); ++ return -ENODEV; ++ } ++ ++#if 0 ++ if (0 > (phy_mode = of_get_phy_mode(np))) ++ { ++ printk("[%s][%d] incorrect phy-mode %d\n", __FUNCTION__, __LINE__, phy_mode); ++ goto jmp_err_connect; ++ } ++#endif ++#if 0 ++ printk("[%s][%d] phy_mode = %d\n", __FUNCTION__, __LINE__, hemac->phy_mode); ++ printk("[%s][%d] of_phy_connect (netdev, np, emac_phy_link_adjust) = (0x%08x, 0x%08x, 0x%08x)\n", ++ __FUNCTION__, __LINE__, ++ (int)netdev, (int)np, (int)emac_phy_link_adjust); ++#endif ++ if (!(phydev = of_phy_connect(netdev, np, emac_phy_link_adjust, 0, hemac->phy_mode))) ++ { ++ printk("[%s][%d] could not connect to PHY\n", __FUNCTION__, __LINE__); ++ goto jmp_err_connect; ++ } ++ ++ phy_init_hw(phydev); ++ ++ printk("[%s][%d] connected mac %s to PHY at %s [uid=%08x, driver=%s]\n", __FUNCTION__, __LINE__, ++ hemac->name, phydev_name(phydev), phydev->phy_id, phydev->drv->name); ++ ++ netdev->phydev->autoneg = AUTONEG_ENABLE; ++ netdev->phydev->speed = 0; ++ netdev->phydev->duplex = 0; ++#if 0 ++ if (of_phy_is_fixed_link(netdev->dev.of_node)) ++ dev->phydev->supported |= ++ SUPPORTED_Pause | SUPPORTED_Asym_Pause; ++#endif ++#if 0 ++ dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause; ++#endif ++ ++ // the speed has to be limited to 10 MBits/sec in FPGA ++ { ++ u32 max_speed = 0; ++ if (!of_property_read_u32(netdev->dev.of_node, "max-speed", &max_speed)) ++ { ++ switch (max_speed) ++ { ++ case 10: ++ phy_set_max_speed(phydev, SPEED_10); ++ break; ++ case 100: ++ phy_set_max_speed(phydev, SPEED_100); ++ break; ++ default: ++ break; ++ } ++ } ++ } ++#if (EMAC_FLOW_CONTROL_TX || EMAC_FLOW_CONTROL_RX) ++ netdev->phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause); ++#else ++ netdev->phydev->supported &= PHY_BASIC_FEATURES; ++#endif ++ netdev->phydev->advertising = netdev->phydev->supported | ADVERTISED_Autoneg; ++ if (0 > phy_start_aneg(netdev->phydev)) ++ { ++ printk("[%s][%d] phy_start_aneg fail\n", __FUNCTION__, __LINE__); ++ } ++ of_node_put(np); ++ return 0; ++ ++jmp_err_connect: ++ if (of_phy_is_fixed_link(netdev->dev.of_node)) ++ of_phy_deregister_fixed_link(netdev->dev.of_node); ++ of_node_put(np); ++ printk("[%s][%d]: invalid phy\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++} ++#endif ++ ++static int __init MDev_EMAC_ndo_init(struct net_device *dev) ++{ ++#if KERNEL_PHY ++ emac_phy_connect(dev); ++#endif ++ return 0; ++} ++ ++static void MDev_EMAC_ndo_uninit(struct net_device *dev) ++{ ++#if KERNEL_PHY ++ phy_disconnect(dev->phydev); ++#endif ++} ++ ++/* ++static void MDev_EMAC_ndo_tx_timeout(struct net_device *dev) ++{ ++} ++*/ ++ ++int MDev_EMAC_ndo_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ if ((new_mtu < 68) || (new_mtu > EMAC_MTU)) ++ { ++ printk("[%s][%d] not support mtu size %d\n", __FUNCTION__, __LINE__, new_mtu); ++ return -EINVAL; ++ } ++ printk("[%s][%d] change mtu size from %d to %d\n", __FUNCTION__, __LINE__, dev->mtu, new_mtu); ++ dev->mtu = new_mtu; ++ return 0; ++} ++ ++static int sstar_emac_get_link_ksettings(struct net_device *ndev, ++ struct ethtool_link_ksettings *cmd) ++{ ++ return phy_ethtool_ksettings_get(ndev->phydev, cmd); ++} ++ ++static int sstar_emac_set_link_ksettings(struct net_device *ndev, ++ const struct ethtool_link_ksettings *cmd) ++{ ++ return phy_ethtool_ksettings_set(ndev->phydev, cmd); ++} ++ ++static int sstar_emac_nway_reset(struct net_device *dev) ++{ ++ return genphy_restart_aneg(dev->phydev); ++} ++ ++static u32 sstar_emac_get_link(struct net_device *dev) ++{ ++ int err; ++ ++ err = genphy_update_link(dev->phydev); ++ if (err) ++ return ethtool_op_get_link(dev); ++ return dev->phydev->link; ++} ++ ++static int MDev_EMAC_set_features(struct net_device *netdev, ++ netdev_features_t features) ++{ ++/* ++printk("[%s][%d] ##################################\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] set features = 0x%08x\n", __FUNCTION__, __LINE__, (int)features); ++printk("[%s][%d] ##################################\n", __FUNCTION__, __LINE__); ++*/ ++ netdev->features = features; ++ return 0; ++} ++ ++static netdev_features_t MDev_EMAC_fix_features( ++ struct net_device *netdev, netdev_features_t features) ++{ ++/* ++printk("[%s][%d] ##################################\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] fix features = 0x%08x 0x%08x \n", __FUNCTION__, __LINE__, (int)features, (int)(features & (EMAC_FEATURES))); ++printk("[%s][%d] ##################################\n", __FUNCTION__, __LINE__); ++*/ ++ return (features & EMAC_FEATURES); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Initialize the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++static const struct net_device_ops mstar_lan_netdev_ops = { ++ .ndo_init = MDev_EMAC_ndo_init, ++ .ndo_uninit = MDev_EMAC_ndo_uninit, ++ // .ndo_tx_timeout = MDev_EMAC_ndo_tx_timeout, ++ .ndo_change_mtu = MDev_EMAC_ndo_change_mtu, ++ .ndo_open = MDev_EMAC_open, ++ .ndo_stop = MDev_EMAC_close, ++ .ndo_start_xmit = MDev_EMAC_tx, ++ .ndo_set_mac_address = MDev_EMAC_set_mac_address, ++ .ndo_set_rx_mode = MDev_EMAC_set_rx_mode, ++ .ndo_do_ioctl = MDev_EMAC_ioctl, ++ .ndo_get_stats = MDev_EMAC_stats, ++ .ndo_set_features = MDev_EMAC_set_features, ++ .ndo_fix_features = MDev_EMAC_fix_features, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = MDev_EMAC_netpoll, ++#endif ++ ++}; ++ ++static const struct ethtool_ops sstar_emac_ethtool_ops = { ++ .get_link_ksettings = sstar_emac_get_link_ksettings, ++ .set_link_ksettings = sstar_emac_set_link_ksettings, ++ // .get_drvinfo = sstar_emac_get_drvinfo, ++ // .get_msglevel = sstar_emac_get_msglevel, ++ // .set_msglevel = sstar_emac_set_msglevel, ++ .nway_reset = sstar_emac_nway_reset, ++ .get_link = sstar_emac_get_link, ++ // .get_strings = sstar_emac_get_strings, ++ // .get_sset_count = sstar_emac_get_sset_count, ++ // .get_ethtool_stats = sstar_emac_get_ethtool_stats, ++ // .get_rxnfc = sstar_emac_get_rxnfc, ++ // .set_rxnfc = sstar_emac_set_rxnfc, ++}; ++ ++#if 0 ++static int MDev_EMAC_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct emac_handle *hemac =(struct emac_handle *) netdev_priv(dev); ++ ++ mii_ethtool_gset (&hemac->mii, cmd); ++ ++ return 0; ++} ++ ++static int MDev_EMAC_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct emac_handle *hemac =(struct emac_handle *) netdev_priv(dev); ++ ++ mii_ethtool_sset (&hemac->mii, cmd); ++ ++ return 0; ++} ++ ++static int MDev_EMAC_nway_reset(struct net_device *dev) ++{ ++ struct emac_handle *hemac =(struct emac_handle *) netdev_priv(dev); ++ ++ mii_nway_restart (&hemac->mii); ++ ++ return 0; ++} ++ ++static u32 MDev_EMAC_get_link(struct net_device *dev) ++{ ++ u32 u32data; ++ struct emac_handle *hemac =(struct emac_handle *) netdev_priv(dev); ++ ++ u32data = mii_link_ok (&hemac->mii); ++ ++ return u32data; ++} ++ ++static const struct ethtool_ops ethtool_ops = { ++ .get_settings = MDev_EMAC_get_settings, ++ .set_settings = MDev_EMAC_set_settings, ++ .nway_reset = MDev_EMAC_nway_reset, ++ .get_link = MDev_EMAC_get_link, ++}; ++#endif ++ ++#endif ++ ++static ssize_t dlist_info_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ int idx=0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if(0==input) ++ { ++ RBNA_detailed=0; ++ } ++ else if(1==input) ++ { ++ RBNA_detailed=1; ++ } ++ else if(2==input) ++ { ++ max_rx_packet_count=0; ++ max_tx_packet_count=0; ++ min_tx_fifo_idle_count=0xffff; ++ } ++ else if(3==input) ++ { ++ for(idx=0; idxirq_count)/sizeof(u32); idx++) ++ hemac->irq_count[idx]=0; ++ } ++ ++ return count; ++} ++ ++static ssize_t dlist_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int idx=0; ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ int empty=0; ++ int max= rxinfo->num_desc; ++ u32 u32RBQP_Addr=0; ++ char descriptor_maps[RX_DESC_NUM]; ++ ++ for(idx=0;idxnum_desc;idx++) ++ { ++ // if(!((dlist->descriptors[idx].addr) & EMAC_DESC_DONE)) ++ if(!((rxinfo->desc[idx].addr) & EMAC_DESC_DONE)) ++ { ++ empty++; ++ descriptor_maps[idx]=1; ++ } ++ else ++ { ++ descriptor_maps[idx]=0; ++ } ++ } ++ // u32RBQP_Addr =( MHal_EMAC_Read_RBQP()-(RBQP_BASE - MIU0_BUS_BASE))/RBQP_HW_BYTES; ++ u32RBQP_Addr = BUS2PA(MHal_EMAC_Read_RBQP(hemac->hal))/RX_DESC_SIZE; ++ str += scnprintf(str, end - str, "%s=0x%x\n", "RBQP_size", max); ++ str += scnprintf(str, end - str, "empty=0x%x, hemac->rxBuffIndex=0x%x, u32RBQP_Addr=0x%x\n", ++ // empty, hemac->rxBuffIndex, u32RBQP_Addr); ++ empty, rxinfo->idx, u32RBQP_Addr); ++ #define CHANGE_LINE_LENG 0x20 ++ for(idx=0;idxnum_desc;idx++) ++ { ++ if(idx%CHANGE_LINE_LENG==0x0) ++ str += scnprintf(str, end - str, "0x%03x: ", idx); ++ ++ str += scnprintf(str, end - str, "%d", descriptor_maps[idx]); ++ ++ if(idx%0x10==(0xF)) ++ str += scnprintf(str, end - str, " "); ++ ++ if(idx%CHANGE_LINE_LENG==(CHANGE_LINE_LENG-1)) ++ str += scnprintf(str, end - str, "\n"); ++ } ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "max_rx_packet_count", max_rx_packet_count); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_DONE", hemac->irq_count[IDX_CNT_INT_DONE]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_RCOM", hemac->irq_count[IDX_CNT_INT_RCOM]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_RBNA", hemac->irq_count[IDX_CNT_INT_RBNA]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_TOVR", hemac->irq_count[IDX_CNT_INT_TOVR]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_TUND", hemac->irq_count[IDX_CNT_INT_TUND]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_RTRY", hemac->irq_count[IDX_CNT_INT_RTRY]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_TCOM", hemac->irq_count[IDX_CNT_INT_TCOM]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_ROVR", hemac->irq_count[IDX_CNT_INT_ROVR]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_JULIAN_D", hemac->irq_count[IDX_CNT_JULIAN_D]); ++/* ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates1", hemac->gu32PhyResetCount1); ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates2", hemac->gu32PhyResetCount2); ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates3", hemac->gu32PhyResetCount3); ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates4", hemac->gu32PhyResetCount4); ++ str += scnprintf(str, end - str, "%s=%d\n", "RESET count", hemac->gu32PhyResetCount); ++*/ ++ str += scnprintf(str, end - str, "%s=%d\n", "skb_tx_send", hemac->skb_tx_send); ++ str += scnprintf(str, end - str, "%s=%d\n", "skb_tx_free", hemac->skb_tx_free); ++ str += scnprintf(str, end - str, "%s=%d\n", "rx_duration_max", rx_duration_max); ++ str += scnprintf(str, end - str, "%s=%d\n", "rx_packet_cnt", rx_packet_cnt); ++ ++/* ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_hw", MHal_EMAC_TXQ_Used(hemac->hal)); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_free_hw", MHal_EMAC_TXQ_Free()); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_0", skb_queue_used(&hemac->skb_queue_tx, 0)); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_free_0", skb_queue_free(&hemac->skb_queue_tx, 0)); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_1", skb_queue_used(&hemac->skb_queue_tx, 1)); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_free_1", skb_queue_free(&hemac->skb_queue_tx, 1)); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_2", skb_queue_used(&hemac->skb_queue_tx, 2)); ++ ++ str += scnprintf(str, end - str, "(size0, size1) = (%d, %d)\n", hemac->skb_queue_tx.size[0], hemac->skb_queue_tx.size[1]); ++ str += scnprintf(str, end - str, "read = %d\n", hemac->skb_queue_tx.read); ++ str += scnprintf(str, end - str, "rw = %d\n", hemac->skb_queue_tx.rw); ++ str += scnprintf(str, end - str, "write = %d\n", hemac->skb_queue_tx.write); ++*/ ++ { ++ struct timespec ct; ++ int duration; ++ u64 data_done_ct; ++ unsigned long flags; ++ u32 txPkt_ct = hemac->skb_tx_send; ++ u32 txInt_ct = hemac->irq_count[IDX_CNT_INT_TCOM]; ++ ++ getnstimeofday(&ct); ++ duration = (ct.tv_sec - hemac->data_time_last.tv_sec)*1000 + (ct.tv_nsec - hemac->data_time_last.tv_nsec)/1000000; ++ spin_lock_irqsave(&hemac->emac_data_done_lock, flags); ++ data_done_ct = hemac->data_done; ++ hemac->data_done = 0; ++ spin_unlock_irqrestore(&hemac->emac_data_done_lock, flags); ++ ++ // tx_duration_max = (tx_duration_max < duration) ? duration : tx_duration_max; ++ hemac->data_time_last = ct; ++ str += scnprintf(str, end - str, "%s=%lld\n", "data_done", data_done_ct); ++ str += scnprintf(str, end - str, "%s=%d\n", "data_duration", duration); ++ do_div(data_done_ct, duration); ++ str += scnprintf(str, end - str, "%s=%lld\n", "data_average", data_done_ct); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_pkt (duration)", txPkt_ct - hemac->txPkt); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_int (duration)", txInt_ct - hemac->txInt); ++ hemac->txPkt = txPkt_ct; ++ hemac->txInt = txInt_ct; ++ } ++ str += scnprintf(str, end - str, "%s=%d\n", "MHal_EMAC_TXQ_Mode", MHal_EMAC_TXQ_Mode(hemac->hal)); ++#if EMAC_SG ++ str += scnprintf(str, end - str, "%s=%d\n", "maxSG", hemac->maxSG); ++#endif // #if #if EMAC_SG ++ return (str - buf); ++} ++DEVICE_ATTR(dlist_info, 0644, dlist_info_show, dlist_info_store); ++ ++static ssize_t info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ // str += scnprintf(str, end - str, "%s %s\n", __DATE__, __TIME__); ++ str += scnprintf(str, end - str, "RAM_ALLOC_SIZE=0x%08x\n", rxinfo->size_desc_queue); ++ str += scnprintf(str, end - str, "RAM_VA_BASE=0x%08x\n", (int)rxinfo->desc); ++ str += scnprintf(str, end - str, "RAM_PA_BASE=0x%08x\n", (int)VIRT2PA(rxinfo->desc)); ++ ++#if MSTAR_EMAC_NAPI ++ str += scnprintf(str, end - str, "NAPI enabled, NAPI_weight=%d\n", EMAC_NAPI_WEIGHT); ++#endif ++ str += scnprintf(str, end - str, "ZERO_COPY enabled\n"); ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++ str += scnprintf(str, end - str, "NEW_TX_QUEUE_INTERRUPT_THRESHOLD enabled\n"); ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++DEVICE_ATTR(info, 0444, info_show, NULL); ++ ++ ++//struct timeval proc_read_time; ++static ssize_t tx_sw_queue_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int idleCount=0; ++ ++ idleCount= MHal_EMAC_TXQ_Free(hemac->hal); ++ str += scnprintf(str, end - str, ++ "netif_queue_stopped=%d \n idleCount=%d \n irqcnt=%d, tx_irqcnt=%d \n tx_bytes_per_timerbak=%d \n min_tx_fifo_idle_count=%d \n", ++ netif_queue_stopped(netdev), ++ idleCount, hemac->irqcnt, hemac->tx_irqcnt, ++ tx_bytes_per_timerbak, ++ min_tx_fifo_idle_count); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(tx_sw_queue_info, 0444, tx_sw_queue_info_show, NULL); ++ ++ ++static ssize_t reverse_led_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ MHal_EMAC_Set_Reverse_LED(hemac->hal, input); ++ return count; ++} ++static ssize_t reverse_led_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u8 u8reg=0; ++ u8reg = MHal_EMAC_Get_Reverse_LED(hemac->hal); ++ return sprintf(buf, "%d\n", u8reg); ++} ++DEVICE_ATTR(reverse_led, 0644, reverse_led_show, reverse_led_store); ++ ++ ++static ssize_t check_link_time_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ hemac->gu32CheckLinkTime = input; ++ return count; ++} ++static ssize_t check_link_time_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++ return sprintf(buf, "%d\n", hemac->gu32CheckLinkTime); ++} ++DEVICE_ATTR(check_link_time, 0644, check_link_time_show, check_link_time_store); ++ ++static ssize_t check_link_timedis_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ hemac->gu32CheckLinkTimeDis = input; ++ return count; ++} ++static ssize_t check_link_timedis_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ return sprintf(buf, "%d\n", hemac->gu32CheckLinkTimeDis); ++} ++DEVICE_ATTR(check_link_timedis, 0644, check_link_timedis_show, check_link_timedis_store); ++ ++static ssize_t sw_led_flick_speed_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ hemac->led_flick_speed = input; ++ return count; ++} ++static ssize_t sw_led_flick_speed_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++ return sprintf(buf, "LED flick speed, the smaller the faster\n%d\n", hemac->led_flick_speed); ++} ++DEVICE_ATTR(sw_led_flick_speed, 0644, sw_led_flick_speed_show, sw_led_flick_speed_store); ++ ++#if DYNAMIC_INT_TX_TIMER ++#if DYNAMIC_INT_TX_TIMER_HR ++static enum hrtimer_restart _MDev_EMAC_TxWdt_CB(struct hrtimer *timer) ++{ ++ struct emac_handle *hemac = container_of(timer, struct emac_handle, timerTxWdt); ++ ++ if (!hemac->timerTxWdtPeriod) ++ return HRTIMER_NORESTART; ++ ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 1); ++ hrtimer_forward_now(&hemac->timerTxWdt, ns_to_ktime(hemac->timerTxWdtPeriod*1000)); ++ return HRTIMER_RESTART; ++} ++#else ++static void _MDev_EMAC_TxWdt_CB(unsigned long data) ++{ ++ struct emac_handle *hemac = (struct emac_handle*)data; ++ ++ if (!hemac->timerTxWdtPeriod) ++ return; ++ ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 1); ++ hemac->timerTxWdt.expires = jiffies + ((hemac->timerTxWdtPeriod)*HZ)/1000000; ++ add_timer(&hemac->timerTxWdt); ++} ++#endif ++#endif ++ ++extern void MHal_EMAC_phy_trunMax(void*); ++// extern void MHal_EMAC_trim_phy(void*); ++static ssize_t turndrv_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ // u32 input; ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++#if 0 ++ if(!strncmp(buf, "0",strlen("0"))) ++ { ++ MHal_EMAC_trim_phy(hemac->hal); ++ return count; ++ } ++#endif ++ ++ if(!strncmp(buf, "max",strlen("max"))) ++ { ++ MHal_EMAC_phy_trunMax(hemac->hal); ++ return count; ++ } ++ ++ if(!strncmp(buf, "f10t",strlen("10t"))) ++ { ++/* ++ //force to set 10M on FPGA ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_ADVERTISE, 0x0061UL); ++ mdelay(10); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++*/ ++ phy_set_max_speed(netdev->phydev, SPEED_10); ++ return count; ++ } ++ if(!strncmp(buf, "an",strlen("an"))) ++ { ++/* ++ //force to set 10M on FPGA ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_ADVERTISE, 0x01e1UL); ++ mdelay(10); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++*/ ++ netdev->phydev->advertising = netdev->phydev->supported | ADVERTISED_Autoneg; ++ phy_start_aneg(netdev->phydev); ++ return count; ++ } ++#if DYNAMIC_INT_RX ++ if(!strncmp(buf, "dir_on", strlen("dir_on"))) ++ { ++ hemac->rx_stats_enable = 1; ++ } ++ if(!strncmp(buf, "dir_off", strlen("dir_off"))) ++ { ++ hemac->rx_stats_enable = 0; ++ } ++#endif ++ ++#if DYNAMIC_INT_TX_TIMER ++ { ++ unsigned char cmd[16]; ++ int param; ++ if (2 == sscanf(buf, "%s %d", cmd, ¶m)) ++ { ++ if (0 == strcasecmp(cmd, "tx_int")) ++ { ++#if DYNAMIC_INT_TX_TIMER_HR ++ hemac->timerTxWdtPeriod = param; ++ hrtimer_try_to_cancel(&hemac->timerTxWdt); ++ hrtimer_start(&hemac->timerTxWdt, ns_to_ktime(hemac->timerTxWdtPeriod*1000), HRTIMER_MODE_REL); ++#else ++ int prev = hemac->timerTxWdtPeriod; ++ unsigned long expires; ++ ++ hemac->timerTxWdtPeriod = param; ++ expires = jiffies + ((hemac->timerTxWdtPeriod)*HZ)/1000000; ++ if (hemac->timerTxWdtPeriod) ++ { ++ if (!prev) ++ { ++ hemac->timerTxWdt.expires = expires; ++ add_timer(&hemac->timerTxWdt); ++ } ++ } ++#endif ++ // printk("[%s][%d] timer %d\n", __FUNCTION__, __LINE__, hemac->timerTxWdtPeriod); ++ } ++ } ++ } ++#endif ++ ++ { ++ unsigned char cmd[16]; ++ int param; ++ ++ if (2 == sscanf(buf, "%s %d", cmd, ¶m)) ++ { ++ if (!strncmp(cmd, "swing_100",strlen("swing_100"))) ++ { ++ u32 val; ++ int tmp; ++ MHal_EMAC_read_phy(hemac->hal, 0, 0x142, &val); ++ tmp = ((val >> 8) & 0x1f); ++ ++#if 0 ++ if (tmp & 0x10) ++ { ++ param = -param; ++ } ++ tmp = ((tmp + param) & 0x1f) << 8; ++#else ++ if (tmp & 0x10) ++ { ++ tmp = tmp & 0xf; ++ tmp ++; ++ tmp = -tmp; ++ } ++ tmp += param; ++ if (tmp > 15) ++ tmp = 15; ++ if (tmp < -16) ++ tmp = -16; ++ if (tmp < 0) ++ { ++ tmp = -tmp; ++ tmp --; ++ tmp = tmp | 0x10; ++ } ++ tmp = tmp << 8; ++#endif ++ val = (val & ~0x1f00) | tmp; ++ MHal_EMAC_write_phy(hemac->hal, 0, 0x142, val); ++ } ++ } ++ } ++ ++ // input = simple_strtoul(buf, NULL, 10); ++ return count; ++} ++ ++static ssize_t turndrv_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return 0; ++} ++ ++DEVICE_ATTR(turndrv, 0644, turndrv_show, turndrv_store); ++ ++static int MDev_EMAC_setup (struct net_device *dev) ++{ ++ struct emac_handle *hemac; ++ // dma_addr_t dmaaddr; ++ void* RetAddr; ++ unsigned long flags; ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ u32 retval; ++#endif ++ ++ hemac = (struct emac_handle *) netdev_priv(dev); ++ ++ if (hemac->bInit) ++ // if (already_initialized) ++ { ++ printk("[%s][%d] %s has been initiated\n", __FUNCTION__, __LINE__, hemac->name); ++ return FALSE; ++ } ++ if (hemac == NULL) ++ { ++ free_irq (dev->irq, dev); ++ EMAC_ERR("hemac fail\n"); ++ return -ENOMEM; ++ } ++ ++#if defined ISR_BOTTOM_HALF ++ /*Init tx and rx tasks*/ ++ INIT_WORK(&hemac->rx_task, MDev_EMAC_bottom_rx_task); ++#endif ++#ifdef TX_SOFTWARE_QUEUE ++ INIT_WORK(&hemac->tx_task, MDev_EMAC_bottom_tx_task); ++#endif ++ ++ hemac->netdev = dev; ++ ++ // skb_queue_create(&(hemac->skb_queue_tx), MHal_EMAC_TXQ_Size(), 256); ++ // skb_queue_create(&(hemac->skb_queue_tx), MHal_EMAC_TXQ_Size(), MHal_EMAC_TXQ_Size()); ++ // RetAddr = MDev_EMAC_VarInit(); ++ RetAddr = MDev_EMAC_VarInit(hemac); ++ if(!RetAddr) ++ { ++ EMAC_ERR("Var init fail!!\n"); ++ return FALSE; ++ } ++ ++ // dev->base_addr = (long) (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200); // seems useless ++ ++ // spin_lock_init(&hemac->mutexRXD); ++ MDev_EMAC_HW_init(dev); ++ ++ // hemac->lock = &emac_lock; ++ spin_lock_init(&hemac->mutexNetIf); ++ spin_lock_init(&hemac->mutexPhy); ++ spin_lock_init(&hemac->mutexTXQ); ++#if (0 == MSTAR_EMAC_NAPI) ++ spin_lock_init(&hemac->mutexRXInt); ++#endif ++ ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_create(&(hemac->skb_queue_tx), MHal_EMAC_TXQ_Size(hemac->hal), MHal_EMAC_TXQ_Size(hemac->hal)+ hemac->txq_num_sw); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ++#if EMAC_FLOW_CONTROL_TX ++ spin_lock_init(&hemac->mutexFlowTX); ++ init_timer(&hemac->timerFlowTX); ++ hemac->timerFlowTX.data = (unsigned long)hemac; ++ hemac->timerFlowTX.expires = jiffies; ++ hemac->timerFlowTX.function = _MDev_EMAC_FlowTX_CB; ++ // hemac->isPauseTX = 0; ++#endif ++ ++#if REDUCE_CPU_FOR_RBNA ++ spin_lock_init(&hemac->mutexIntRX); ++ init_timer(&hemac->timerIntRX); ++ hemac->timerIntRX.data = (unsigned long)hemac; ++ hemac->timerIntRX.expires = jiffies; ++ hemac->timerIntRX.function = _MDev_EMAC_IntRX_CB; ++#endif ++ ++#if DYNAMIC_INT_RX ++ // getnstimeofday(&hemac->rx_stats_time); ++ hemac->rx_stats_packet = 0xFFFFFFFF; ++ hemac->rx_stats_enable = 1; ++#endif ++ ++ ether_setup (dev); ++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,28) ++ dev->open = MDev_EMAC_open; ++ dev->stop = MDev_EMAC_close; ++ dev->hard_start_xmit = MDev_EMAC_tx; ++ dev->get_stats = MDev_EMAC_stats; ++ dev->set_multicast_list = MDev_EMAC_set_rx_mode; ++ dev->do_ioctl = MDev_EMAC_ioctl; ++ dev->set_mac_address = MDev_EMAC_set_mac_address; ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ dev->netdev_ops = &mstar_lan_netdev_ops; ++#endif ++ dev->tx_queue_len = EMAC_MAX_TX_QUEUE; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ ////SET_ETHTOOL_OPS(dev, ðtool_ops); ++ //EMAC_TODO("set Ethtool_ops\n"); ++ // netdev_set_default_ethtool_ops(dev, ðtool_ops); ++#endif ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MDev_EMAC_get_mac_address (dev); // Get ethernet address and store it in dev->dev_addr // ++ MDev_EMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ MHal_EMAC_enable_mdi(hemac->hal); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++#if 0 ++ //Support for ethtool // ++ hemac->mii.dev = dev; ++ hemac->mii.mdio_read = MDev_EMAC_mdio_read; ++ hemac->mii.mdio_write = MDev_EMAC_mdio_write; ++#endif ++ // already_initialized = 1; ++ // hemac->bInit = 1; ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ dev->features |= NETIF_F_IP_CSUM; ++#endif ++ ++ dev->features |= EMAC_FEATURES; ++ dev->vlan_features |= EMAC_FEATURES; ++ ++ ++ hemac->irqcnt=0; ++ hemac->tx_irqcnt=0; ++ ++ // printk("[%s][%d] (irq_emac, irq_lan) = (%d, %d)\n", __FUNCTION__, __LINE__, hemac->irq_emac, hemac->irq_lan); ++ // printk("[%s][%d] %d\n", __FUNCTION__, __LINE__, dev->irq); ++ dev->irq = hemac->irq_emac; ++ // dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0); ++ if (!dev->irq) ++ { ++ EMAC_ERR("Get irq number0 error from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ // printk("[%s][%d] request irq for %d %d\n", __FUNCTION__, __LINE__, dev->irq, hemac->irq_emac); ++ //Install the interrupt handler // ++ //Notes: Modify linux/kernel/irq/manage.c /* interrupt.h */ ++ if (request_irq(dev->irq, MDev_EMAC_interrupt, 0/*SA_INTERRUPT*/, dev->name, dev)) ++ return -EBUSY; ++ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ // val = irq_of_parse_and_map(dev->dev.of_node, 1); ++ val = hemac->irq_lan; ++ if (!val) ++ { ++ EMAC_ERR("Get irq number0 error from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ if (request_irq(val/*INT_FIQ_LAN_ESD+32*/, MDev_EMAC_interrupt_cable_unplug, 0/*SA_INTERRUPT*/, dev->name, dev)) ++ return -EBUSY; ++#endif ++ //Determine current link speed // ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ // MDev_EMAC_update_linkspeed (dev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++#if DYNAMIC_INT_TX_TIMER ++ ++#if DYNAMIC_INT_TX_TIMER_HR ++ hrtimer_init(&hemac->timerTxWdt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); ++ hemac->timerTxWdt.function = _MDev_EMAC_TxWdt_CB; ++#else ++ init_timer(&hemac->timerTxWdt); ++ hemac->timerTxWdt.data = (unsigned long)hemac; ++ // hemac->timerDummy.expires = jiffies + HZ/10; ++ hemac->timerTxWdt.function = _MDev_EMAC_TxWdt_CB; ++ hemac->timerTxWdtPeriod = 0; ++ // add_timer(&hemac->timerDummy); ++#endif ++ ++#endif ++ alloc_chrdev_region(&gEthDev, 0, MINOR_EMAC_NUM, "ETH"); ++ hemac->mstar_class_emac_device = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR(gEthDev), hemac->u8Minor), NULL, hemac->name); ++ dev_set_drvdata(hemac->mstar_class_emac_device, (void*)dev); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_tx_sw_queue_info); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_dlist_info); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_reverse_led); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_check_link_time); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_check_link_timedis); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_info); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_sw_led_flick_speed); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_turndrv); ++#if 0//ajtest ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_ajtest_recv_count); ++#endif ++#if defined(PACKET_DUMP) ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_tx_dump); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_rx_dump); ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Restar the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_SwReset(struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(dev); ++ u32 oldCFG, oldCTL; ++ // u32 retval; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MDev_EMAC_get_mac_address (dev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ oldCFG = MHal_EMAC_Read_CFG(hemac->hal); ++ oldCTL = MHal_EMAC_Read_CTL(hemac->hal) & ~(EMAC_TE | EMAC_RE); ++ ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ free_rx_skb(hemac); // @FIXME : how about RX descriptor ++ netif_stop_queue (dev); ++ ++ /* ++ retval = MHal_EMAC_Read_JULIAN_0100(hemac->hal); ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, retval & 0x00000FFFUL); ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, retval); ++ */ ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, 1); ++ ++ MDev_EMAC_HW_init(dev); ++ MHal_EMAC_Write_CFG(hemac->hal, oldCFG); ++ MHal_EMAC_Write_CTL(hemac->hal, oldCTL); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MHal_EMAC_enable_mdi(hemac->hal); ++ MDev_EMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ // (void)MDev_EMAC_update_linkspeed (dev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntEnable(hemac->hal, hemac->gu32intrEnable, 1); ++ ++ MDev_EMAC_start(dev); ++ MDev_EMAC_set_rx_mode(dev); ++ netif_start_queue (dev); ++ hemac->contiROVR = 0; ++ EMAC_ERR("=> Take %lu ms to reset EMAC!\n", (getCurMs() - hemac->oldTime)); ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Detect MAC and PHY and perform initialization ++//------------------------------------------------------------------------------------------------- ++#if defined (CONFIG_OF) ++static struct of_device_id mstaremac_of_device_ids[] = { ++ {.compatible = "sstar-emac"}, ++ {}, ++}; ++#endif ++ ++static int MDev_EMAC_probe (struct net_device *dev) ++{ ++ int detected; ++ /* Read the PHY ID registers - try all addresses */ ++ detected = MDev_EMAC_setup(dev); ++ return detected; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer to detect cable pluged/unplugged ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static void MDev_EMAC_timer_callback(unsigned long value) ++{ ++ int ret = 0; ++/* ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++*/ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ ++ static u32 bmsr, time_count = 0; ++ unsigned long flags; ++ ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_SW) ++ if (EMAC_FLOW_CTL_TMR == value) ++ { ++ netif_wake_queue((struct net_device *)emac_dev); ++ spin_lock_irq(&emac_flow_ctl_lock); ++ eth_pause_cmd_enable = 0; ++ spin_unlock_irq(&emac_flow_ctl_lock); ++ return; ++ } ++#endif ++ ++ if(gu32GatingRxIrqTimes) ++ { ++ MHal_EMAC_RX_Param(0x01, 0x01); ++ gu32GatingRxIrqTimes--; ++ } ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ ret = MDev_EMAC_update_linkspeed(emac_dev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++ tx_bytes_per_timerbak = tx_bytes_per_timer; ++ tx_bytes_per_timer = 0; ++ ++ if (0 == ret) ++ { ++ if (!hemac->ThisBCE.connected) ++ { ++ hemac->ThisBCE.connected = 1; ++ netif_carrier_on(emac_dev); ++ netif_start_queue(emac_dev); ++ //EMAC_ERR("connected\n"); ++ } ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Set_High(hemac->led_orange); ++ MDrv_GPIO_Set_High(hemac->led_green); ++ } ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (hemac->phyaddr, MII_BMSR, &bmsr); ++ time_count = 0; ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ phy_status_register = bmsr; ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ // Normally, time out sets 1 Sec. ++ hemac->timer_link.expires = jiffies + gu32CheckLinkTime; ++ } ++ else //no link ++ { ++ if(hemac->ThisBCE.connected) { ++ hemac->ThisBCE.connected = 0; ++ } ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ MDrv_GPIO_Set_Low(hemac->led_green); ++ } ++ ++ // If disconnected is over 3 Sec, the real value of PHY's status register will report to application. ++ if(time_count > CONFIG_DISCONNECT_DELAY_S*(HZ/gu32CheckLinkTimeDis)) { ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (hemac->phyaddr, MII_BMSR, &bmsr); ++ ++ // Report to kernel. ++ if (netif_carrier_ok(emac_dev)) ++ netif_carrier_off(emac_dev); ++ if (!netif_queue_stopped(emac_dev)) ++ netif_stop_queue(emac_dev); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ phy_status_register = bmsr; ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(emac_dev); ++#endif ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ hemac->ThisBCE.connected = 0; ++ // Normally, time out is set 1 Sec. ++ hemac->timer_link.expires = jiffies + gu32CheckLinkTime; ++ } ++ else// if(time_count <= CONFIG_DISCONNECT_DELAY_S*10) ++ { ++ time_count++; ++ // Time out is set 100ms. Quickly checks next phy status. ++ hemac->timer_link.expires = jiffies + gu32CheckLinkTimeDis; ++ //EMAC_ERR("disconnect\n"); ++ } ++ } ++ add_timer(&hemac->timer_link); ++} ++#endif ++ ++#if 0 ++static void MDev_EMAC_timer_LinkStatus(unsigned long data) ++{ ++ int ret = 0; ++ struct net_device* netdev = (struct net_device*)data; ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ static u32 bmsr, time_count = 0; ++ unsigned long flags; ++ ++ // printk("[%s][%d] aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n", __FUNCTION__, __LINE__); ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ ret = MDev_EMAC_update_linkspeed(netdev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++ tx_bytes_per_timerbak = tx_bytes_per_timer; ++ tx_bytes_per_timer = 0; ++ ++ if (0 == ret) ++ { ++ if (!hemac->ThisBCE.connected) ++ { ++ hemac->ThisBCE.connected = 1; ++ netif_carrier_on(netdev); ++ netif_start_queue(netdev); ++ //EMAC_ERR("connected\n"); ++ } ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Set_High(hemac->led_orange); ++ MDrv_GPIO_Set_High(hemac->led_green); ++ } ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ time_count = 0; ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ hemac->phy_status_register = bmsr; ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ // Normally, time out sets 1 Sec. ++ hemac->timer_link.expires = jiffies + hemac->gu32CheckLinkTime; ++ } ++ else //no link ++ { ++ if(hemac->ThisBCE.connected) { ++ hemac->ThisBCE.connected = 0; ++ } ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ MDrv_GPIO_Set_Low(hemac->led_green); ++ } ++ ++ // If disconnected is over 3 Sec, the real value of PHY's status register will report to application. ++ if(time_count > CONFIG_DISCONNECT_DELAY_S*(HZ/hemac->gu32CheckLinkTimeDis)) { ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ ++ // Report to kernel. ++ if (netif_carrier_ok(netdev)) ++ netif_carrier_off(netdev); ++ if (!netif_queue_stopped(netdev)) ++ netif_stop_queue(netdev); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ hemac->phy_status_register = bmsr; ++ ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(netdev); ++#endif ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ hemac->ThisBCE.connected = 0; ++ // Normally, time out is set 1 Sec. ++ hemac->timer_link.expires = jiffies + hemac->gu32CheckLinkTime; ++ } ++ else// if(time_count <= CONFIG_DISCONNECT_DELAY_S*10) ++ { ++ time_count++; ++ // Time out is set 100ms. Quickly checks next phy status. ++ hemac->timer_link.expires = jiffies + hemac->gu32CheckLinkTimeDis; ++ //EMAC_ERR("disconnect\n"); ++ } ++ } ++ add_timer(&hemac->timer_link); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC MACADDR Setup ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef MODULE ++ ++#define MACADDR_FORMAT "XX:XX:XX:XX:XX:XX" ++ ++static int __init macaddr_auto_config_setup(char *addrs) ++{ ++ if (strlen(addrs) == strlen(MACADDR_FORMAT) ++ && ':' == addrs[2] ++ && ':' == addrs[5] ++ && ':' == addrs[8] ++ && ':' == addrs[11] ++ && ':' == addrs[14] ++ ) ++ { ++ addrs[2] = '\0'; ++ addrs[5] = '\0'; ++ addrs[8] = '\0'; ++ addrs[11] = '\0'; ++ addrs[14] = '\0'; ++ ++ MY_MAC[0] = (u8)simple_strtoul(&(addrs[0]), NULL, 16); ++ MY_MAC[1] = (u8)simple_strtoul(&(addrs[3]), NULL, 16); ++ MY_MAC[2] = (u8)simple_strtoul(&(addrs[6]), NULL, 16); ++ MY_MAC[3] = (u8)simple_strtoul(&(addrs[9]), NULL, 16); ++ MY_MAC[4] = (u8)simple_strtoul(&(addrs[12]), NULL, 16); ++ MY_MAC[5] = (u8)simple_strtoul(&(addrs[15]), NULL, 16); ++ ++ /* set back to ':' or the environment variable would be destoried */ // REVIEW: this coding style is dangerous ++ addrs[2] = ':'; ++ addrs[5] = ':'; ++ addrs[8] = ':'; ++ addrs[11] = ':'; ++ addrs[14] = ':'; ++ } ++ ++ return 1; ++} ++ ++__setup("macaddr=", macaddr_auto_config_setup); ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC init module ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static int MDev_EMAC_ScanPhyAddr(struct net_device* netdev) ++{ ++ unsigned char addr = 0; ++ u32 value = 0; ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, JULIAN_100_VAL); ++ ++ MHal_EMAC_enable_mdi(hemac->hal); ++ do ++ { ++ MHal_EMAC_read_phy(hemac->hal, addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ ++ EMAC_DBG("[ PHY Addr:%d ] ==> :%x\n", addr, value); ++ break; ++ } ++ }while(++addr && addr < 32); ++ MHal_EMAC_disable_mdi(hemac->hal); ++ hemac->phyaddr = addr; ++ ++ if (hemac->phyaddr >= 32) ++ { ++ EMAC_ERR("Wrong PHY Addr and reset to 0\n"); ++ // hemac->phyaddr = 0; ++ hemac->phyaddr = 0xff; ++ return -1; ++ } ++ return 0; ++} ++ ++static void Rtl_Patch(struct net_device* netdev) ++{ ++ u32 val; ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 25, &val); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, 25, 0x400UL); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 25, &val); ++} ++ ++static void MDev_EMAC_Patch_PHY(struct net_device* netdev) ++{ ++ u32 val; ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 2, &val); ++ if (RTL_8210 == val) ++ Rtl_Patch(netdev); ++} ++#endif ++ ++#if KERNEL_PHY ++static int MDev_EMAC_mii_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) bus->priv; ++ int ret; ++ ++ ret = MHal_EMAC_write_phy(hemac->hal, phy_addr, phy_reg, (u32)val); ++ return ret; ++} ++ ++static int MDev_EMAC_mii_read(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val; ++ struct emac_handle *hemac = (struct emac_handle *) bus->priv; ++ int ret; ++ ++ ret = MHal_EMAC_read_phy(hemac->hal, phy_addr, phy_reg, &val); ++ return (int)val; ++} ++ ++static int MDev_EMAC_mii_init(struct net_device* emac_dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ struct device_node *mii_np = NULL; ++ int ret = 0; ++ ++ // the force internal mdio bus in FPGA ++ if (1) ++ { ++ u32 mdio_path = 0; ++ if (!of_property_read_u32(emac_dev->dev.of_node, "mdio_path", &mdio_path)) ++ { ++ MHal_EMAC_mdio_path(hemac->hal, mdio_path); ++ } ++ } ++ ++ if (!(mii_np = of_get_child_by_name(emac_dev->dev.of_node, "mdio-bus"))) ++ { ++ // printk("[%s][%d] no child node of mdio-bus is found\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ if (!of_device_is_available(mii_np)) ++ { ++ // printk("[%s][%d] mii_np is unavailable\n", __FUNCTION__, __LINE__); ++ ret = -2; ++ goto jmp_err_put_node; ++ } ++ if (!(hemac->mii_bus = devm_mdiobus_alloc(hemac->dev))) ++ { ++ // printk("[%s][%d] devm_mdiobus_alloc fail\n", __FUNCTION__, __LINE__); ++ ret = -3; ++ goto jmp_err_put_node; ++ } ++ ++ hemac->mii_bus->name = "mdio"; ++ hemac->mii_bus->read = MDev_EMAC_mii_read; ++ hemac->mii_bus->write = MDev_EMAC_mii_write; ++ hemac->mii_bus->priv = hemac; ++ hemac->mii_bus->parent = hemac->dev; ++ ++ snprintf(hemac->mii_bus->id, MII_BUS_ID_SIZE, "%s@%s", mii_np->name, hemac->name); ++ ret = of_mdiobus_register(hemac->mii_bus, mii_np); ++jmp_err_put_node: ++ of_node_put(mii_np); ++ return ret; ++} ++ ++static void MDev_EMAC_mii_uninit(struct net_device* emac_dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ if (!hemac->mii_bus) ++ return; ++ mdiobus_unregister(hemac->mii_bus); ++ devm_mdiobus_free(hemac->dev, hemac->mii_bus); ++} ++ ++#endif ++ ++static int MDev_EMAC_init(struct platform_device *pdev) ++{ ++ struct emac_handle *hemac; ++ int ret; ++ struct net_device* emac_dev = NULL; ++ unsigned long flags; ++ ++ emac_dev = alloc_etherdev(sizeof(*hemac)); ++ hemac = netdev_priv(emac_dev); ++ // printk("[%s][%d] alloc netdev = 0x%08x\n", __FUNCTION__, __LINE__, (int)emac_dev); ++ ++ if (!emac_dev) ++ { ++ EMAC_ERR( KERN_ERR "No EMAC dev mem!\n" ); ++ return -ENOMEM; ++ } ++ ++ // led gpio ++ hemac->led_orange = -1; ++ hemac->led_green = -1; ++ hemac->led_count = 0; ++ hemac->led_flick_speed = 30; ++ ++ // phy address ++ // hemac->phyaddr = 0xff; ++ ++//////////////////////////////////////////////////////////////////////////// ++ hemac->gu32CheckLinkTime = HZ; ++ hemac->gu32CheckLinkTimeDis = 100; ++ hemac->gu32intrEnable = 0; ++ memset(hemac->irq_count, 0, sizeof(hemac->irq_count)); ++ ++/* ++ hemac->gu32PhyResetCount1 = 0; ++ hemac->gu32PhyResetCount2 = 0; ++ hemac->gu32PhyResetCount3 = 0; ++ hemac->gu32PhyResetCount4 = 0; ++ hemac->gu32PhyResetCount = 0; ++*/ ++ hemac->skb_tx_send = 0; ++ hemac->skb_tx_free = 0; ++ hemac->data_done = 0; ++ memset(&hemac->data_time_last, 0, sizeof(hemac->data_time_last)); ++ spin_lock_init(&hemac->emac_data_done_lock); ++ ++ hemac->txPkt = 0; ++ hemac->txInt = 0; ++ ++ hemac->phy_status_register = 0x78c9UL; ++ ++ hemac->initstate= 0; ++ hemac->contiROVR = 0; ++ ++ hemac->oldTime = 0; ++ hemac->PreLinkStatus = 0; ++ ++ // hemac->phy_type = 0; ++ hemac->irq_emac = 0; ++ hemac->irq_lan = 0; ++ ++ hemac->name = NULL; ++ hemac->bInit = 0; ++ hemac->bEthCfg = 0; ++ ++ hemac->u8Minor = _u8Minor; ++ _u8Minor++; ++#if KERNEL_PHY ++ hemac->dev = &pdev->dev; ++#endif ++ ++//////////////////////////////////////////////////////////////////////////// ++ ++ emac_dev->dev.of_node = pdev->dev.of_node; //pass of_node to MDev_EMAC_setup() ++ ++ SET_NETDEV_DEV(emac_dev, hemac->dev); ++ // emac_dev->ethtool_ops = &sstar_emac_ethtool_ops; ++ netdev_set_default_ethtool_ops(emac_dev, &sstar_emac_ethtool_ops); ++ ++ MDev_EMAC_dts(emac_dev); ++ hemac->hal = MHal_EMAC_Alloc(hemac->emacRIU, hemac->emacX32, hemac->phyRIU); ++ MHal_EMAC_Pad(hemac->hal, hemac->pad_reg, hemac->pad_msk, hemac->pad_val); ++ MHal_EMAC_PadLed(hemac->hal, hemac->pad_led_reg, hemac->pad_led_msk, hemac->pad_led_val); ++ MHal_EMAC_PhyMode(hemac->hal, hemac->phy_mode); ++ ++ if (0 == _phyReset) ++ { ++ #if defined(CONFIG_MS_PADMUX) ++ if (mdrv_padmux_active()) ++ { ++ int gpio_no; ++ if (PAD_UNKNOWN != (gpio_no = mdrv_padmux_getpad(MDRV_PUSE_EMAC0_PHY_RESET))) ++ { ++ MDrv_GPIO_Set_High(gpio_no); ++ } ++ if (PAD_UNKNOWN != (gpio_no = mdrv_padmux_getpad(MDRV_PUSE_EMAC1_PHY_RESET))) ++ { ++ MDrv_GPIO_Set_High(gpio_no); ++ } ++ } ++ #endif ++ _phyReset = 1; ++ } ++ ++#if TX_THROUGHPUT_TEST ++ printk("==========TX_THROUGHPUT_TEST==============="); ++ pseudo_packet = alloc_skb(EMAC_PACKET_SIZE_MAX, GFP_ATOMIC); ++ memcpy(pseudo_packet->data, (void *)packet_content, sizeof(packet_content)); ++ pseudo_packet->len = sizeof(packet_content); ++#endif ++ ++#if RX_THROUGHPUT_TEST ++ printk("==========RX_THROUGHPUT_TEST==============="); ++ init_timer(&RX_timer); ++ ++ RX_timer.data = EMAC_RX_TMR; ++ RX_timer.function = RX_timer_callback; ++ RX_timer.expires = jiffies + 20*EMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++#endif ++ MDev_EMAC_ClkRegister(hemac,&pdev->dev); ++ MDev_EMAC_ClkEnable(hemac); ++ MHal_EMAC_Power_On_Clk(hemac->hal, &pdev->dev); ++ ++ // init_timer(&EMAC_timer); ++ // init_timer(&hemac->timer_link); ++ ++/* ++ if (0 > MDev_EMAC_ScanPhyAddr(emac_dev)) ++ goto end; ++ ++ MDev_EMAC_Patch_PHY(emac_dev); ++*/ ++ ++#if MSTAR_EMAC_NAPI ++ netif_napi_add(emac_dev, &hemac->napi, MDev_EMAC_napi_poll, EMAC_NAPI_WEIGHT); ++#endif ++ ++ emac_dev->netdev_ops = &mstar_lan_netdev_ops; ++ if (MDev_EMAC_probe (emac_dev)) ++ goto end; ++ ++#if KERNEL_PHY ++ MDev_EMAC_mii_init(emac_dev); ++#endif ++ ++ if ((ret = register_netdev (emac_dev))) ++ goto end; ++ ++ // printk( KERN_ERR "[EMAC]Init EMAC success! (add delay in reset)\n" ); ++ platform_set_drvdata(pdev, (void*)emac_dev); ++ hemac->bInit = 1; ++ return 0; ++ ++end: ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_destroy(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ free_netdev(emac_dev); ++ emac_dev = NULL; ++ hemac->initstate = ETHERNET_TEST_INIT_FAIL; ++ EMAC_ERR( KERN_ERR "Init EMAC error!\n" ); ++ return -1; ++} ++ ++static void MDev_EMAC_dts(struct net_device* netdev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ // const char* tmp_str = NULL; ++ unsigned int led_data; ++ // struct resource *res; ++ struct resource res; ++ u32 val[3]; ++ ++ hemac->irq_emac = irq_of_parse_and_map(netdev->dev.of_node, 0); ++ hemac->irq_lan = irq_of_parse_and_map(netdev->dev.of_node, 1); ++ ++ // printk("[%s][%d] (irq_emac, irq_lan) = (%d, %d)\n", __FUNCTION__, __LINE__, hemac->irq_emac, hemac->irq_lan); ++ ++#if 0 ++ if (!of_property_read_string(netdev->dev.of_node, "emac_phy", &tmp_str) && tmp_str) ++ { ++ hemac->phy_type = 0; ++ // printk("[%s][%d] emac dts phy name = [%s]\n", __FUNCTION__, __LINE__, tmp_str); ++ if (!strcmp("ALBANY", tmp_str)) ++ hemac->phy_type = 0; // for internal phy, ie. ALBANY ++ else if (!strcmp("EMAC_PHY_FPGA", tmp_str)) ++ hemac->phy_type = 1; // for FPGA ++ } ++ else ++ { ++ // printk("[%s][%d] emac default phy name = [%s]\n", __FUNCTION__, __LINE__, "ALBANY"); ++ hemac->phy_type = 0; ++ } ++#endif ++ ++ ++ if (of_property_read_u32(netdev->dev.of_node, "txd_num", &hemac->txd_num)) ++ { ++ hemac->txd_num = TXD_NUM; // default value ++ } ++ hemac->txd_num = (hemac->txd_num + 0xFF) & 0x100; // 256 alignment ++ if (of_property_read_u32(netdev->dev.of_node, "txq_num_sw", &hemac->txq_num_sw)) ++ { ++ hemac->txq_num_sw = TXQ_NUM_SW; // default value ++ } ++ ++ if(!of_property_read_u32(netdev->dev.of_node, "led-orange", &led_data)) ++ { ++ hemac->led_orange = (unsigned char)led_data; ++ // printk(KERN_ERR "[EMAC]Set emac_led_orange=%d\n",led_data); ++ } ++ ++ if(!of_property_read_u32(netdev->dev.of_node, "led-green", &led_data)) ++ { ++ hemac->led_green = (unsigned char)led_data; ++ // printk(KERN_ERR "[EMAC]Set emac_led_green=%d\n",led_data); ++ } ++ ++ // bank of emac & phy ++ if (!of_address_to_resource(netdev->dev.of_node, 0, &res)) ++ { ++ hemac->emacRIU = IO_ADDRESS(res.start); ++ // printk("[%s][%d] (emacRIU, start) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacRIU, res.start); ++ } ++ else ++ { ++ hemac->emacRIU = 0x1F2A2000; ++ hemac->emacRIU = IO_ADDRESS(hemac->emacRIU); ++ // printk("[%s][%d] (emacRIU) = (0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacRIU); ++ } ++ if (!of_address_to_resource(netdev->dev.of_node, 1, &res)) ++ { ++ hemac->emacX32 = IO_ADDRESS(res.start); ++ // printk("[%s][%d] (emacX32, start) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacX32, res.start); ++ } ++ else ++ { ++ hemac->emacX32 = 0x1F343C00; ++ hemac->emacX32 = IO_ADDRESS(hemac->emacX32); ++ // printk("[%s][%d] (emacX32) = (0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacX32); ++ } ++ if (!of_address_to_resource(netdev->dev.of_node, 2, &res)) ++ { ++ hemac->phyRIU = (res.start) ? IO_ADDRESS(res.start) : 0; ++ // printk("[%s][%d] (phyRIU, start) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, hemac->phyRIU, res.start); ++ } ++ else ++ { ++ if(CamOsChipId() == INFINITY6E_CHIP_ID) //I6e ++ { ++ hemac->phyRIU = 0x1F2A2800; ++ } ++ else ++ { ++ hemac->phyRIU = 0x1F006200; ++ } ++ hemac->phyRIU = IO_ADDRESS(hemac->phyRIU); ++ // printk("[%s][%d] (phyRIU) = (0x%08x)\n", __FUNCTION__, __LINE__, hemac->phyRIU); ++ } ++ ++ val[0] = val[1] = val[2] = 0; ++ if (of_property_read_u32_array(netdev->dev.of_node, "pad", val, 3)) ++ { ++ // printk("[%s][%d] parse pad mux fail\n", __FUNCTION__, __LINE__); ++ if(CamOsChipId() == INFINITY6E_CHIP_ID) //I6e ++ { ++ val[0] = 0x1F2079B8; ++ val[1] = 0x0001; ++ val[2] = 0x0001; ++ } ++ else ++ { ++ val[0] = 0x1F203C3C; ++ val[1] = 0x0004; ++ val[2] = 0x0004; ++ } ++ } ++ hemac->pad_reg = IO_ADDRESS(val[0]); ++ hemac->pad_msk = val[1]; ++ hemac->pad_val = val[2]; ++ ++ val[0] = val[1] = val[2] = 0; ++ if (of_property_read_u32_array(netdev->dev.of_node, "pad_led", val, 3)) ++ { ++ if(CamOsChipId() == INFINITY6E_CHIP_ID) //I6e ++ { ++ val[0] = 0x1F20798C; ++ val[1] = 0x0077; ++ val[2] = 0x0021; ++ } ++ else ++ { ++ val[0] = 0x1F001CA0; ++ val[1] = 0x0030; ++ val[2] = 0x0010; ++ } ++ } ++ hemac->pad_led_reg = (val[0]) ? IO_ADDRESS(val[0]) : 0; ++ hemac->pad_led_msk = val[1]; ++ hemac->pad_led_val = val[2]; ++ ++ // printk("[%s][%d] pad (reg, msk, val) = (0x%08x 0x%08x 0x%08x)\n", __FUNCTION__, __LINE__, hemac->pad_reg, hemac->pad_msk, hemac->pad_val); ++ ++ { ++ // struct device_node* np = NULL; ++ int phy_mode; ++ ++ hemac->phy_mode = PHY_INTERFACE_MODE_RMII; ++#if 0 ++ np = of_parse_phandle(netdev->dev.of_node, "phy-handle", 0); ++ if (!np && of_phy_is_fixed_link(netdev->dev.of_node)) ++ if (!of_phy_register_fixed_link(netdev->dev.of_node)) ++ np = of_node_get(netdev->dev.of_node); ++ if (!np) ++ { ++ // printk("[%s][%d] can not find phy-handle in dts\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ if (0 > (phy_mode = of_get_phy_mode(np))) ++ { ++ // printk("[%s][%d] incorrect phy-mode %d\n", __FUNCTION__, __LINE__, phy_mode); ++ } ++ else ++ { ++ hemac->phy_mode = phy_mode; ++ } ++ } ++#else ++ if (0 > (phy_mode = of_get_phy_mode(netdev->dev.of_node))) ++ { ++ struct device_node* np = NULL; ++ np = of_parse_phandle(netdev->dev.of_node, "phy-handle", 0); ++ if ((np) && (0 <= (phy_mode = of_get_phy_mode(np)))) ++ { ++ hemac->phy_mode = phy_mode; ++ } ++ if (np) ++ of_node_put(np); ++ } ++ else ++ { ++ hemac->phy_mode = phy_mode; ++ } ++#endif ++ } ++ hemac->name = netdev->dev.of_node->name; ++} ++ ++#if REDUCE_CPU_FOR_RBNA ++static void _MDev_EMAC_IntRX_CB(unsigned long data) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexIntRX, flags); ++ // MHal_EMAC_RX_Param(hemac->hal, 0x01, 0x01); ++ MHal_EMAC_RX_ParamRestore(hemac->hal); ++ spin_unlock_irqrestore(&hemac->mutexIntRX, flags); ++} ++#endif // #if REDUCE_CPU_FOR_RBNA ++ ++#if EMAC_FLOW_CONTROL_TX ++static void _MDev_EMAC_FlowTX_CB(unsigned long data) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexFlowTX, flags); ++#if 0 ++ if (1 == hemac->isPauseTX) ++ { ++ hemac->isPauseTX = 0; ++ netif_wake_queue(hemac->netdev); ++ // printk("[%s][%d] release\n", __FUNCTION__, __LINE__); ++ } ++#else ++ netif_wake_queue(hemac->netdev); ++#endif ++ spin_unlock_irqrestore(&hemac->mutexFlowTX, flags); ++} ++ ++static int _MDrv_EMAC_is_PausePkt(struct sk_buff* skb, unsigned char* p_recv) ++{ ++ unsigned int mac_ctl_opcode = 0; ++ ++ if ((MAC_CONTROL_TYPE&0xFF) != ((skb->protocol>>8)&0xFF)) ++ return 0; ++ if (((MAC_CONTROL_TYPE>>8)&0xFF) != (skb->protocol&0xFF)) ++ return 0; ++ mac_ctl_opcode = (((*(p_recv+14))<<8)&0xFF00) + ((*(p_recv+15))&0xFF); ++ return (MAC_CONTROL_OPCODE == mac_ctl_opcode) ? 1 : 0; ++} ++ ++static int _MDrv_EMAC_Pause_TX(struct net_device* dev, struct sk_buff* skb, unsigned char* p_recv) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(dev); ++ int pause_time = 0; ++ int pause_time_to_jiffies = 0; ++ unsigned long flags; ++ unsigned long expires; ++ ++#if EMAC_FLOW_CONTROL_TX_TEST ++{ ++ static unsigned int cnt = 0; ++ cnt++; ++ if ((cnt & 0xF) == 0) ++ { ++ // printk("[%s][%d] pseudo pause packet\n", __FUNCTION__, __LINE__); ++ pause_time = EMAC_FLOW_CONTROL_TX_TEST_TIME; ++ goto jump_pause_tx_test; ++ } ++} ++#endif // #if EMAC_FLOW_CONTROL_TX_TEST ++ ++ if (0 == _MDrv_EMAC_is_PausePkt(skb, p_recv)) ++ return 0; ++ ++ pause_time = (((*(p_recv+16))<<8)&0xFF00) + ((*(p_recv+17))&0xFF); ++ ++#if EMAC_FLOW_CONTROL_TX_TEST ++jump_pause_tx_test: ++#endif // #if EMAC_FLOW_CONTROL_TX_TEST ++ ++ if (SPEED_100 == dev->phydev->speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_100M)+((0==(pause_time%PAUSE_TIME_DIVISOR_100M))?0:1); ++ expires = jiffies + pause_time_to_jiffies; ++ } ++ else if (SPEED_10 == dev->phydev->speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_10M)+((0==(pause_time%PAUSE_TIME_DIVISOR_10M))?0:1); ++ expires = jiffies + pause_time_to_jiffies; ++ } ++ else ++ { ++ printk("[%s][%d] Get emac speed error : %d\n", __FUNCTION__, __LINE__, (int)dev->phydev->speed); ++ return 0; ++ } ++ spin_lock_irqsave(&hemac->mutexFlowTX, flags); ++ ++ // if (0 == hemac->isPauseTX) ++ if (0 == timer_pending(&hemac->timerFlowTX)) ++ { ++ netif_stop_queue (dev); ++ hemac->timerFlowTX.expires = expires; ++ // hemac->isPauseTX = 1; ++ add_timer(&hemac->timerFlowTX); ++ } ++ else ++ { ++ mod_timer(&hemac->timerFlowTX, expires); ++ } ++ spin_unlock_irqrestore(&hemac->mutexFlowTX, flags); ++ return 1; ++} ++#endif // #if EMAC_FLOW_CONTROL_TX ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC exit module ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_exit(struct platform_device *pdev) ++{ ++ struct net_device* emac_dev =(struct net_device*) platform_get_drvdata(pdev); ++ ++ if (emac_dev) ++ { ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ unsigned long flags; ++ ++#if EMAC_FLOW_CONTROL_TX ++ // hemac->isPauseTX = 0; ++ del_timer(&hemac->timerFlowTX); ++#endif // #if EMAC_FLOW_CONTROL_TX ++ ++#if REDUCE_CPU_FOR_RBNA ++ del_timer(&hemac->timerIntRX); ++#endif // #if REDUCE_CPU_FOR_RBNA ++ ++#if KERNEL_PHY ++ MDev_EMAC_mii_uninit(emac_dev); ++#endif ++ ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_destroy(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ++ // printk("[%s][%d] free RX memory\n", __FUNCTION__, __LINE__); ++ // mem_info.length = RBQP_SIZE; ++ // strcpy(mem_info.name, "EMAC_BUFF"); ++ // msys_release_dmem(&mem_info); ++ free_rx_skb(hemac); ++ MDev_EMAC_RX_Desc_Free(hemac); ++ MDev_EMAC_MemFree(hemac); ++#if (EMAC_SG && EMAC_SG_BUF_CACHE) ++/* ++ if (hemac->pTxBuf) ++ { ++ kfree(hemac->pTxBuf); ++ hemac->pTxBuf = NULL; ++ } ++*/ ++#endif ++ MHal_EMAC_Free(hemac->hal); ++ unregister_netdev(emac_dev); ++ free_netdev(emac_dev); ++ } ++} ++ ++static int mstar_emac_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ // struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct net_device *netdev=(struct net_device*) platform_get_drvdata(dev); ++ struct emac_handle *hemac; ++ unsigned long flags; ++ ++ // printk(KERN_INFO "mstar_emac_drv_suspend\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ ++ hemac = (struct emac_handle*) netdev_priv(netdev); ++ hemac->ep_flag |= EP_FLAG_SUSPENDING; ++ netif_stop_queue (netdev); ++ ++ disable_irq(netdev->irq); ++ //del_timer(&hemac->timer_link); ++ ++ //corresponds with resume call MDev_EMAC_open ++#if MSTAR_EMAC_NAPI ++ if(napi_enable_flag == 1) ++ napi_disable(&hemac->napi); ++ napi_enable_flag = 0; ++#endif ++ ++ //Disable Receiver and Transmitter // ++ MDev_EMAC_stop(netdev); ++ ++#ifdef TX_SW_QUEUE ++ //make sure that TX HW FIFO is empty ++ while(TX_FIFO_SIZE!= MHal_EMAC_TXQ_Free(hemac->hal)); ++#endif ++ while (!MHal_EMAC_TXQ_Empty(hemac->hal)) ++ { ++ msleep(1); ++ } ++ ++ // Disable PHY interrupt // ++ MHal_EMAC_disable_phyirq(hemac->hal); ++ ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ ++ //MDev_EMAC_SwReset(netdev); ++ MDev_EMAC_ClkDisable(hemac); ++ MHal_EMAC_Power_Off_Clk(hemac->hal, &dev->dev); ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(netdev); ++#endif ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ++ free_rx_skb(hemac); ++ ++ phy_stop(netdev->phydev); ++ ++ MDev_EMAC_RX_Desc_Reset(hemac); ++ ++ //phy_link_adjust ++ hemac->bEthCfg = 0; ++ ++ return 0; ++} ++ ++static int mstar_emac_drv_resume(struct platform_device *dev) ++{ ++ // struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct net_device *netdev=(struct net_device*) platform_get_drvdata(dev); ++ struct emac_handle *hemac; ++ unsigned long flags; ++ ++ // printk(KERN_INFO "mstar_emac_drv_resume\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ hemac = (struct emac_handle*) netdev_priv(netdev);; ++ hemac->ep_flag &= ~EP_FLAG_SUSPENDING; ++ MDev_EMAC_ClkEnable(hemac); ++ MHal_EMAC_Power_On_Clk(hemac->hal, &dev->dev); ++ ++ // MHal_EMAC_Write_JULIAN_0100(hemac->hal, JULIAN_100_VAL); ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, 0); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++/* ++ if (0 > MDev_EMAC_ScanPhyAddr(netdev)) ++ return -1; ++ ++ MDev_EMAC_Patch_PHY(netdev); ++*/ ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++ // hemac->ThisUVE.initedEMAC = 0; ++ MDev_EMAC_HW_init(netdev); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MDev_EMAC_update_mac_address (netdev); // Program ethernet address into MAC // ++ MHal_EMAC_enable_mdi(hemac->hal); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ enable_irq(netdev->irq); ++ if(hemac->ep_flag & EP_FLAG_OPEND) ++ { ++ if(0>MDev_EMAC_open(netdev)) ++ { ++ printk(KERN_WARNING "Driver Emac: open failed after resume\n"); ++ } ++ } ++ ++ MDev_EMAC_set_rx_mode(netdev); ++ ++ return 0; ++} ++ ++static int mstar_emac_drv_probe(struct platform_device *pdev) ++{ ++ int retval=0; ++ struct net_device* netdev; ++ struct emac_handle *hemac; ++ ++ if (!(pdev->name) || strcmp(pdev->name,"Sstar-emac") ++ || pdev->id!=0) ++ { ++ retval = -ENXIO; ++ } ++ ++ if ((retval = MDev_EMAC_init(pdev))) ++ return retval; ++ ++ netdev=(struct net_device*) platform_get_drvdata(pdev); ++ hemac = (struct emac_handle*) netdev_priv(netdev);; ++/* ++ if(!of_property_read_u32(pdev->dev.of_node, "led-orange", &led_data)) ++ { ++ hemac->led_orange = (unsigned char)led_data; ++ printk(KERN_ERR "[EMAC]Set emac_led_orange=%d\n",led_data); ++ } ++ ++ if(!of_property_read_u32(pdev->dev.of_node, "led-green", &led_data)) ++ { ++ hemac->led_green = (unsigned char)led_data; ++ printk(KERN_ERR "[EMAC]Set emac_led_green=%d\n",led_data); ++ } ++*/ ++ if(hemac->led_orange!=-1) ++ { ++ MDrv_GPIO_Pad_Set(hemac->led_orange); ++ } ++ if(hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Pad_Set(hemac->led_green); ++ } ++ return retval; ++} ++ ++static int mstar_emac_drv_remove(struct platform_device *pdev) ++{ ++ struct net_device* emac_dev =(struct net_device*) platform_get_drvdata(pdev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ ++ if( !(pdev->name) || strcmp(pdev->name,"Sstar-emac") ++ || pdev->id!=0) ++ { ++ return -1; ++ } ++ MDev_EMAC_exit(pdev); ++ MDev_EMAC_ClkDisable(hemac); ++ MDev_EMAC_ClkUnregister(hemac); ++ MHal_EMAC_Power_Off_Clk(hemac->hal, &pdev->dev); ++#if 0 ++ netif_napi_del(ð->tx_napi); ++ netif_napi_del(ð->rx_napi); ++ ++ netif_napi_add(emac_dev, &hemac->napi, MDev_EMAC_napi_poll, EMAC_NAPI_WEIGHT); ++ ++ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct emac_handle *hemac; ++ ++ printk(KERN_INFO "mstar_emac_drv_resume\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ hemac = (struct emac_handle*) netdev_priv(netdev);; ++ hemac->ep_flag &= ~EP_FLAG_SUSPENDING; ++#endif ++ platform_set_drvdata(pdev, NULL); ++ return 0; ++} ++ ++ ++ ++static struct platform_driver Mstar_emac_driver = { ++ .probe = mstar_emac_drv_probe, ++ .remove = mstar_emac_drv_remove, ++ .suspend = mstar_emac_drv_suspend, ++ .resume = mstar_emac_drv_resume, ++ ++ .driver = { ++ .name = "Sstar-emac", ++#if defined(CONFIG_OF) ++ .of_match_table = mstaremac_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_emac_drv_init_module(void) ++{ ++ int retval=0; ++ ++ retval = platform_driver_register(&Mstar_emac_driver); ++ if (retval) ++ { ++ // printk(KERN_INFO"Mstar_emac_driver register failed...\n"); ++ return retval; ++ } ++ ++ return retval; ++} ++ ++static void __exit mstar_emac_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_emac_driver); ++ // emac_dev=NULL; ++} ++ ++module_init(mstar_emac_drv_init_module); ++module_exit(mstar_emac_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("EMAC Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/emac/mdrv_emac.h b/drivers/sstar/emac/mdrv_emac.h +new file mode 100755 +index 000000000000..a3ea7e788fcd +--- /dev/null ++++ b/drivers/sstar/emac/mdrv_emac.h +@@ -0,0 +1,384 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __DRV_EMAC_H_ ++#define __DRV_EMAC_H_ ++ ++#define EMAC_DBG(fmt, args...) //{printk("Sstar_emac: "); printk(fmt, ##args);} ++#define EMAC_ERR(fmt, args...) {printk("Sstar_emac: "); printk(fmt, ##args);} ++#define EMAC_INFO {printk("Line:%u\n", __LINE__);} ++#define EMAC_TODO(fmt, args...) {printk("[EMAC]%d TODO:", __LINE__); printk(fmt, ##args);} ++ ++#define MINOR_EMAC_NUM 1 ++#define MAJOR_EMAC_NUM 241 ++ ++#define EXT_PHY_PATCH 1 ++ ++///////////////////////////////// ++// to be refined ++///////////////////////////////// ++ ++#define EMAC_SG 1 ++#define EMAC_SG_BDMA 0 ++#define EMAC_SG_BUF_CACHE 1 ++ ++#define EMAC_GSO 1 ++ ++// #define DYNAMIC_INT_TX_TH 64 ++#define DYNAMIC_INT_TX 1 ++#define DYNAMIC_INT_TX_TIMER 0 ++#define DYNAMIC_INT_TX_TIMER_HR 0 ++ ++#define DYNAMIC_INT_RX 1 ++#define REDUCE_CPU_FOR_RBNA 1 ++ ++#define MSTAR_EMAC_NAPI 1 ++ ++#define EMAC_FLOW_CONTROL_RX 1 ++#define EMAC_FLOW_CONTROL_RX_TEST 0 ++ ++ ++#define EMAC_FLOW_CONTROL_TX 1 ++#define EMAC_FLOW_CONTROL_TX_TEST 0 ++#define EMAC_FLOW_CONTROL_TX_TEST_TIME 0x200 ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define EMAC_MTU (1524) ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++// #define DRV_EMAC_MAX_DEV 0x1 ++ ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++/* ++phys_addr_t RAM_VA_BASE; //= 0x00000000; // After init, RAM_ADDR_BASE = EMAC_ABSO_MEM_BASE ++phys_addr_t RAM_PA_BASE; ++phys_addr_t RAM_VA_PA_OFFSET; ++phys_addr_t RBQP_BASE; //= RX_BUFFER_SIZE;//0x00004000; // IMPORTANT: lowest 13 bits as zero. ++*/ ++ ++#define ETHERNET_TEST_NO_LINK 0x00000000UL ++#define ETHERNET_TEST_AUTO_NEGOTIATION 0x00000001UL ++#define ETHERNET_TEST_LINK_SUCCESS 0x00000002UL ++#define ETHERNET_TEST_RESET_STATE 0x00000003UL ++#define ETHERNET_TEST_SPEED_100M 0x00000004UL ++#define ETHERNET_TEST_DUPLEX_FULL 0x00000008UL ++#define ETHERNET_TEST_INIT_FAIL 0x00000010UL ++ ++u8 MY_DEV[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; ++u8 MY_MAC[6] = { 0x00UL, 0x30UL, 0x1BUL, 0xBAUL, 0x02UL, 0xDBUL }; ++u8 PC_MAC[6] = { 0x00UL, 0x1AUL, 0x4BUL, 0x5CUL, 0x39UL, 0xDFUL }; ++u8 ETH_PAUSE_FRAME_DA_MAC[6] = { 0x01UL, 0x80UL, 0xC2UL, 0x00UL, 0x00UL, 0x01UL }; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct rbf_t ++{ ++ u32 addr; ++ u32 size; ++} __attribute__ ((packed)); ++ ++#define EP_FLAG_OPEND 0X00000001UL ++#define EP_FLAG_SUSPENDING 0X00000002UL ++ ++typedef struct ++{ ++ // u8 used; ++ struct sk_buff* skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_phys; /* phys addr from pci_map_single */ ++ int skb_len; ++} skb_info; ++ ++typedef struct ++{ ++ skb_info* skb_info_arr; ++ int read; ++ int write; ++ int rw; ++ int size[2]; ++} skb_queue; ++ ++typedef struct ++{ ++ // int off_va_pa; ++ // skb_queue skb_queue_rx; ++ struct rbf_t* desc; ++ // dma_addr_t descPhys; ++ struct sk_buff** skb_arr; ++ int num_desc; ++ int size_desc_queue; ++ int idx; ++} rx_desc_queue_t; ++ ++#if 0 ++struct _BasicConfigEMAC ++{ ++ u8 connected; // 0:No, 1:Yes <== (20070515) Wait for Julian's reply ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _BasicConfigEMAC BasicConfigEMAC; ++ ++struct _UtilityVarsEMAC ++{ ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ // Statistics Counters : (accumulated) ++ u32 cntREG_ETH_FRA; ++ u32 cntREG_ETH_SCOL; ++ u32 cntREG_ETH_MCOL; ++ u32 cntREG_ETH_OK; ++ u32 cntREG_ETH_SEQE; ++ u32 cntREG_ETH_ALE; ++ u32 cntREG_ETH_DTE; ++ u32 cntREG_ETH_LCOL; ++ u32 cntREG_ETH_ECOL; ++ u32 cntREG_ETH_TUE; ++ u32 cntREG_ETH_CSE; ++ u32 cntREG_ETH_RE; ++ u32 cntREG_ETH_ROVR; ++ u32 cntREG_ETH_SE; ++ u32 cntREG_ETH_ELR; ++ u32 cntREG_ETH_RJB; ++ u32 cntREG_ETH_USF; ++ u32 cntREG_ETH_SQEE; ++ // Interrupt Counter : ++ u32 cntHRESP; // Reset = 0x0000 ++ u32 cntROVR; // Reset = 0x0000 ++ u32 cntLINK; // Reset = 0x0000 ++ u32 cntTIDLE; // Reset = 0x0000 ++ u32 cntTCOM; // Reset = 0x0000 ++ u32 cntTBRE; // Reset = 0x0000 ++ u32 cntRTRY; // Reset = 0x0000 ++ u32 cntTUND; // Reset = 0x0000 ++ u32 cntTOVR; // Reset = 0x0000 ++ u32 cntRBNA; // Reset = 0x0000 ++ u32 cntRCOM; // Reset = 0x0000 ++ u32 cntDONE; // Reset = 0x0000 ++ // Flags: ++ u8 flagMacTxPermit; // 0:No,1:Permitted. Initialize as "permitted" ++ u8 flagISR_INT_RCOM; ++ u8 flagISR_INT_RBNA; ++ u8 flagISR_INT_DONE; ++ u8 flagPowerOn; // 0:Poweroff, 1:Poweron ++ u8 initedEMAC; // 0:Not initialized, 1:Initialized. ++ u8 flagRBNA; ++ // Misc Counter: ++ u32 cntRxFrames; // Reset = 0x00000000 (Counter of RX frames,no matter it's me or not) ++ u32 cntReadONE_RX; // Counter for ReadONE_RX_Frame ++ u32 cntCase20070806; ++ u32 cntChkToTransmit; ++ // Misc Variables: ++ u32 mainThreadTasks; // (20071029_CHARLES) b0=Poweroff,b1=Poweron ++}; ++typedef struct _UtilityVarsEMAC UtilityVarsEMAC; ++#endif ++ ++struct emac_handle ++{ ++ struct net_device_stats stats; ++ ++ /* PHY */ ++ // unsigned long phy_type; /* type of PHY (PHY_ID) */ ++ ++ spinlock_t mutexNetIf; ++ spinlock_t mutexTXQ; // spin_lock_bh¡]¡^ÉOspin_unlock_bh¡]¡^ ++ spinlock_t mutexPhy; ++ ++ /* Transmit */ ++ skb_queue skb_queue_tx; ++ ++ unsigned int irqcnt; ++ unsigned int tx_irqcnt; ++ ++ /* Receive */ ++ // spinlock_t mutexRXD; ++ rx_desc_queue_t rx_desc_queue; ++#if EXT_PHY_PATCH ++ char* pu8RXBuf; ++#endif ++ ++ /* Suspend and resume */ ++ unsigned long ep_flag; ++ ++ struct net_device *netdev; ++ ++ struct device *mstar_class_emac_device; ++#if MSTAR_EMAC_NAPI ++ struct napi_struct napi; ++#else ++ spinlock_t mutexRXInt; ++#endif ++ MSYS_DMEM_INFO mem_info; ++ ++ u32 txd_num; ++ u32 txq_num_sw; ++ ++ // led gpio ++ int led_orange; ++ int led_green; ++ int led_count; ++ int led_flick_speed; ++ ++ // mac address ++ u8 sa[4][6]; ++ ++ // BasicConfigEMAC ThisBCE; ++ // UtilityVarsEMAC ThisUVE; ++ ++ // struct timer_list timer_link; ++ ++ // ++ unsigned int irq_emac; ++ unsigned int irq_lan; ++ ++ // ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ // ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 phy_mode; ++ ++ // led ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ // hal handle ++ void* hal; ++ ++ //////////////// ++ u32 gu32CheckLinkTime; ++ u32 gu32CheckLinkTimeDis; ++ u32 gu32intrEnable; ++ u32 irq_count[32]; ++ ++ u32 skb_tx_send; ++ u32 skb_tx_free; ++ u64 data_done; ++ struct timespec data_time_last; ++ spinlock_t emac_data_done_lock; ++ ++ u32 txPkt; ++ u32 txInt; ++ ++ u32 phy_status_register; ++ ++ u32 initstate; ++ u32 contiROVR; ++ unsigned long oldTime; ++ unsigned long PreLinkStatus; ++ ++ // ++ const char* name; ++ u8 bInit; ++ u8 bEthCfg; ++ ++ u8 u8Minor; ++ ++#if KERNEL_PHY ++ /// phy separation ++ struct mii_bus* mii_bus; ++ struct device* dev; // don't know its useness ++#endif ++ ++#if 0 ++ // not sure about its use ++ u32 gu32PhyResetCount1; ++ u32 gu32PhyResetCount2; ++ u32 gu32PhyResetCount3; ++ u32 gu32PhyResetCount4; ++ u32 gu32PhyResetCount; ++#endif ++ ++ ++#if EMAC_FLOW_CONTROL_TX ++ // TX pause packet (TX flow control) ++ spinlock_t mutexFlowTX; ++ struct timer_list timerFlowTX; ++ // int isPauseTX; ++#endif ++ ++#if EMAC_FLOW_CONTROL_RX ++ // RX pause packet (TX flow control) ++ u8* pu8PausePkt; ++ u8 u8PausePktSize; ++ u8 isPausePkt; ++#endif ++ ++#if REDUCE_CPU_FOR_RBNA ++ spinlock_t mutexIntRX; ++ struct timer_list timerIntRX; ++#endif ++ ++#if DYNAMIC_INT_RX ++ struct timespec rx_stats_time; ++ u32 rx_stats_packet; ++ u8 rx_stats_enable; ++#endif ++ ++#if DYNAMIC_INT_TX_TIMER ++#if DYNAMIC_INT_TX_TIMER_HR ++ struct hrtimer timerTxWdt; ++#else ++ struct timer_list timerTxWdt; ++#endif ++ int timerTxWdtPeriod; ++#endif ++ ++#if EMAC_SG ++ // char* pTxBuf; ++ // int TxBufIdx; ++ int maxSG; ++#endif // #if EMAC_SG ++#ifdef CONFIG_CAM_CLK ++ void **pvclk; ++ int EmacParentCnt; ++#endif ++}; ++ ++#endif ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h End ++// ----------------------------------------------------------------------------- ++ ++ +diff --git a/drivers/sstar/emac/policy.txt b/drivers/sstar/emac/policy.txt +new file mode 100755 +index 000000000000..f06bedd4b51f +--- /dev/null ++++ b/drivers/sstar/emac/policy.txt +@@ -0,0 +1,45 @@ ++//////////////////////////////////////////// ++// What kind of test before release ++//////////////////////////////////////////// ++ ++A. Auto detection for different speed and duplex ++ 1. 10Mb Full ++ 2. 10Mb Half ++ 3. 100Mb Full ++ 4. 100Mb Half ++ ++B. Data Transfer Rate with different speed and duplex ++ 1. 10Mb Half ++ 1.1 64-byte icmp packet: greater than 7.6Mb ++ 1.2 128-byte icmp packet: greater than 7.6Mb ++ 1.3 256-byte icmp packet: greater than 7.6Mb ++ 1.4 512-byte icmp packet: greater than 7.6Mb ++ 1.5 1024-byte icmp packet: greater than 7.6Mb ++ 1.6 1280-byte icmp packet: greater than 7.6Mb ++ 1.7 1514-byte icmp packet: greater than 7.6Mb ++ 2. 10Mb Full ++ 2.1 64-byte icmp packet: greater than 7.6Mb ++ 2.2 128-byte icmp packet: greater than 7.6Mb ++ 2.3 256-byte icmp packet: greater than 7.6Mb ++ 2.4 512-byte icmp packet: greater than 7.6Mb ++ 2.5 1024-byte icmp packet: greater than 7.6Mb ++ 2.6 1280-byte icmp packet: greater than 7.6Mb ++ 2.7 1514-byte icmp packet: greater than 7.6Mb ++ 3. 100Mb Half ++ 3.1 64-byte icmp packet: greater than 7.6Mb ++ 3.2 128-byte icmp packet: greater than 10Mb ++ 3.3 256-byte icmp packet: greater than 15Mb ++ 3.4 512-byte icmp packet: greater than 30Mb ++ 3.5 1024-byte icmp packet: greater than 50Mb ++ 3.6 1280-byte icmp packet: greater than 55Mb ++ 3.7 1514-byte icmp packet: greater than 60Mb ++ 4. 100Mb Full ++ 4.1 64-byte icmp packet: greater than 7.6Mb ++ 4.2 128-byte icmp packet: greater than 10Mb ++ 4.3 256-byte icmp packet: greater than 15Mb ++ 4.4 512-byte icmp packet: greater than 30Mb ++ 4.5 1024-byte icmp packet: greater than 50Mb ++ 4.6 1280-byte icmp packet: greater than 55Mb ++ 4.7 1514-byte icmp packet: greater than 60Mb ++ ++ +\ No newline at end of file +diff --git a/drivers/sstar/emac_toe/Kconfig b/drivers/sstar/emac_toe/Kconfig +new file mode 100755 +index 000000000000..60b17ef55713 +--- /dev/null ++++ b/drivers/sstar/emac_toe/Kconfig +@@ -0,0 +1,46 @@ ++config MS_EMAC_TOE ++select NET ++select NET_ETHERNET ++select MII ++select PACKET ++select USE_POLICY_FWD ++select INET ++select NETDEVICES ++ ++tristate "EMAC_TOE" ++default n ++ ++---help--- ++Enable compilation option for driver EMAC ++ ++if MS_EMAC ++config EMAC_SUPPLY_RNG ++bool "Supply to random number generator device" ++default n ++help ++ Supply to random number generator device ++ ++config MSTAR_HW_TX_CHECKSUM ++bool "Supply to hardware TX checksum" ++default n ++help ++ Supply to hardware TX checksum ++ ++config K3_RX_SWPATCH ++bool "Supply to K3 RX SW Patch" ++default n ++help ++ Supply to K3 RX frame drop due to padding 4 bytes issue ++ ++config DISCONNECT_DELAY_S ++int "Disconnect delay in second" ++default 1 ++help ++ Disconnect delay in second ++ ++config MSTAR_EEE ++bool "Supply to EEE function" ++default n ++help ++ Supply to EEE function ++endif +diff --git a/drivers/sstar/emac_toe/Makefile b/drivers/sstar/emac_toe/Makefile +new file mode 100755 +index 000000000000..d71294271121 +--- /dev/null ++++ b/drivers/sstar/emac_toe/Makefile +@@ -0,0 +1,21 @@ ++# ++# Makefile for MStar EMAC device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/emac_toe ++EXTRA_CFLAGS += -Idrivers/sstar/emac_toe/hal/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++EXTRA_CFLAGS += -Idrivers/sstar/bdma/ ++ ++EXTRA_CFLAGS += -DKERNEL_PHY=1 ++ ++# specific options ++# EXTRA_CFLAGS += -DRED_LION ++# files ++obj-$(CONFIG_MS_EMAC_TOE) := kdrv_emac.o ++kdrv_emac-y := mdrv_emac.o ++kdrv_emac-y += hal/$(CONFIG_SSTAR_CHIP_NAME)/mhal_emac.o +diff --git a/drivers/sstar/emac_toe/hal/infinity2m/mhal_emac.c b/drivers/sstar/emac_toe/hal/infinity2m/mhal_emac.c +new file mode 100755 +index 000000000000..6ec308f03bad +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity2m/mhal_emac.c +@@ -0,0 +1,2556 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ val = (val_h & 0xFFFF0000) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x66, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x67, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x68, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x69, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x66, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x67, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x68, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x69, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++ // workaround for clock gen support no clock selection ++ if (PHY_INTERFACE_MODE_RMII == pHal->phy_mode) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x66, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x67, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x68, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x69, 0x00); ++ } ++ ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++ ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++#define INTERNAL_MDIO_ADDR 0 ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++/* ++ if (0 != phy_addr) ++ return -1; ++*/ ++ if (INTERNAL_MDIO_ADDR != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++/* ++ if (0 != phy_addr) ++ return 0xffff; ++*/ ++ if (INTERNAL_MDIO_ADDR != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ +diff --git a/drivers/sstar/emac_toe/hal/infinity2m/mhal_emac.h b/drivers/sstar/emac_toe/hal/infinity2m/mhal_emac.h +new file mode 100755 +index 000000000000..8cab061122df +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity2m/mhal_emac.h +@@ -0,0 +1,495 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac_toe/hal/infinity3/mhal_emac.c b/drivers/sstar/emac_toe/hal/infinity3/mhal_emac.c +new file mode 100755 +index 000000000000..8bcacfd5aceb +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity3/mhal_emac.c +@@ -0,0 +1,2471 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (0) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x30010000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u8, u32); ++ int (*phy_read)(void*, u8, u8, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u8 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u8 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u8 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u8 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ if (PHY_INTERFACE_MODE_RMII != pHal->phy_mode) ++ val |= 0x0004; ++ val = (val_h & 0xFFFF0000) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#ifdef RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++ ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#endif ++ return ret; ++} ++ ++static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u8 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u8 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u8 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u8 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ +diff --git a/drivers/sstar/emac_toe/hal/infinity3/mhal_emac.h b/drivers/sstar/emac_toe/hal/infinity3/mhal_emac.h +new file mode 100755 +index 000000000000..38bbf4bebb71 +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity3/mhal_emac.h +@@ -0,0 +1,494 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac_toe/hal/infinity5/mhal_emac.c b/drivers/sstar/emac_toe/hal/infinity5/mhal_emac.c +new file mode 100755 +index 000000000000..ad469f21080b +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity5/mhal_emac.c +@@ -0,0 +1,2529 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (63) ++ #define TX_QUEUE_CNT_SCHE (1) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (1) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ val = (val_h & 0xFFFF0000) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++// #if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++// #endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++ ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ +diff --git a/drivers/sstar/emac_toe/hal/infinity5/mhal_emac.h b/drivers/sstar/emac_toe/hal/infinity5/mhal_emac.h +new file mode 100755 +index 000000000000..8cab061122df +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity5/mhal_emac.h +@@ -0,0 +1,495 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac_toe/hal/infinity6/mhal_emac.c b/drivers/sstar/emac_toe/hal/infinity6/mhal_emac.c +new file mode 100755 +index 000000000000..b2898489f7ed +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity6/mhal_emac.c +@@ -0,0 +1,2531 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ val |= 0x0004; ++ val = (val_h & 0xFFFF0000) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++ ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ +diff --git a/drivers/sstar/emac_toe/hal/infinity6/mhal_emac.h b/drivers/sstar/emac_toe/hal/infinity6/mhal_emac.h +new file mode 100755 +index 000000000000..8cab061122df +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity6/mhal_emac.h +@@ -0,0 +1,495 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac_toe/hal/infinity6e/mhal_emac.c b/drivers/sstar/emac_toe/hal/infinity6e/mhal_emac.c +new file mode 100755 +index 000000000000..e59ca76f47fc +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity6e/mhal_emac.c +@@ -0,0 +1,2531 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#endif ++ ++// extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// HW configurations ++//------------------------------------------------------------------------------------------------- ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define RX_DELAY_INT 1 ++ ++ #define TX_QUEUE_SIZE_NEW (127) ++ #define TX_QUEUE_CNT_SCHE (2) // 0 : SW patch with EMAC1_0x24 ++ // 1 : EMAC0_0x6C ++ // 2 : HW latch with EMAC1_0x24 ++ // 3 : HW backward compatible with "SW patch with EMAC1_0x24" ++ #define TXD_CAP (0) ++ ++//------------------------------------------------------------------------------------------------- ++// Constant definition ++//------------------------------------------------------------------------------------------------- ++#define TX_QUEUE_SIZE (4 + TX_QUEUE_SIZE_NEW) ++#define EMAC_INT_MASK (0x80000dff) ++ ++// #define JULIAN_100_VAL (0x0000F011) ++#define JULIAN_100_VAL (0x00000011) ++ ++#if (RX_DELAY_INT) ++// #define JULIAN_104_VAL (0x01010000UL) ++// #define JULIAN_104_VAL (0x30400000UL) ++#define JULIAN_104_VAL (0x10020000UL) ++#else ++#define JULIAN_104_VAL (0x00000000UL) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define TXD_SIZE sizeof(txd_t) ++typedef struct ++{ ++ u32 addr; ++ u32 tag; ++ #define TXD_LEN_MSK (0x3FFF) ++ #define TXD_WRAP (0x1 << 14) /* bit for wrap */ ++ u32 reserve0; ++ u32 reserve1; ++} __attribute__ ((packed)) txd_t; ++ ++typedef struct ++{ ++ int (*phy_write)(void*, u8, u32, u32); ++ int (*phy_read)(void*, u8, u32, u32*); ++ void (*phy_clk_on)(void*); ++ void (*phy_clk_off)(void*); ++} phy_ops_t; ++ ++typedef struct ++{ ++ int (*txq_size)(void*); ++ int (*txq_free)(void*); ++ int (*txq_used)(void*); ++ int (*txq_empty)(void*); ++ int (*txq_full)(void*); ++ int (*txq_insert)(void*, u32 bus, u32 len); ++ int (*txq_mode)(void*); ++} txq_ops_t; ++ ++ ++typedef struct ++{ ++ txd_t* pTXD; ++ u32 TXD_num; ++ u32 TXD_write; ++ // u32 TXD_read; ++ // int phy_type; ++ txq_ops_t txq_op; ++ phy_ops_t phy_op; ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ u32 phy_mode; ++ ++#if RX_DELAY_INT ++ u8 u8RxFrameCnt; ++ u8 u8RxFrameCyc; ++#endif ++ spinlock_t lock_irq; ++} mhal_emac_t; ++ ++#define MHal_MAX_INT_COUNTER 100 ++ ++//------------------------------------------------------------------------------------------------- ++// local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// forward declaration ++//------------------------------------------------------------------------------------------------- ++static void _MHal_EMAC_TXQ_Enable(void*); ++static void _MHal_EMAC_TXD_Enable(void*); ++int MHal_EMAC_TXD_Dump(void*); ++ ++// TXQ ++static int _MHal_EMAC_TXQ_Size(void*); ++static int _MHal_EMAC_TXQ_Free(void*); ++static int _MHal_EMAC_TXQ_Used(void*); ++static int _MHal_EMAC_TXQ_Empty(void*); ++static int _MHal_EMAC_TXQ_Full(void*); ++static int _MHal_EMAC_TXQ_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXQ_Mode(void*); ++ ++// TXD ++static int _MHal_EMAC_TXD_Size(void*); ++static int _MHal_EMAC_TXD_Free(void*); ++static int _MHal_EMAC_TXD_Used(void*); ++static int _MHal_EMAC_TXD_Empty(void*); ++static int _MHal_EMAC_TXD_Full(void*); ++static int _MHal_EMAC_TXD_Insert(void*, u32 bus, u32 len); ++static int _MHal_EMAC_TXD_Mode(void*); ++ ++// phy operations for albany ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_albany_clk_on(void* hal); ++static void _MHal_EMAC_albany_clk_off(void* hal); ++ ++// phy operations for external phy ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val); ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val); ++static void _MHal_EMAC_ext_clk_on(void* hal); ++static void _MHal_EMAC_ext_clk_off(void* hal); ++ ++//------------------------------------------------------------------------------------------------- ++// Local variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8(u32 base, u32 bank, u32 reg) ++{ ++ u8 val; ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ val = *((volatile u8*) address); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8(u32 base, u32 bank, u32 reg, u8 val) ++{ ++ // u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ // u32 address = EMAC_RIU_REG_BASE + (bank << 9); ++ u32 address = base + (bank << 9) + (reg << 1) - (reg & 1); ++ *((volatile u8*) address) = val; ++} ++ ++#define MHal_EMAC_ReadReg16(base, bank, reg) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) ++#define MHal_EMAC_WritReg16(base, bank, reg, val) *((volatile u16*)((base) + ((bank) << 9) + ((reg) << 1))) = (val) ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32(void* hal, u32 xoffset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ return *(( volatile u32*)address); ++ } ++} ++ ++void MHal_EMAC_WritReg32(void* hal, u32 xoffset, u32 xval ) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_EMAC0<<9) + (xoffset<< 1); ++ u32 address = pHal->emacRIU + (xoffset<< 1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ // u32 address = EMAC_RIU_REG_BASE + (REG_BANK_X32_EMAC0<<9) + (xoffset<<1); ++ u32 address = pHal->emacX32 + (xoffset<<1); ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, w0); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, w1); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address(void* hal, u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(void* hal, u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32(hal, REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CTL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CTL, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CFG); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++/* ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR(void* hal, u32 xval ) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_RSR, xval); ++} ++ ++#if 0 ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++/* ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++*/ ++ ++u32 MHal_EMAC_IntStatus(void* hal) ++{ ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ // xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ // xReceiveNum += xoffsetValue&0xFFUL; ++ // if(xoffsetValue&0x8000UL) ++ u32 int_imr = ~MHal_EMAC_ReadReg32(hal, REG_ETH_IMR); ++ u32 intstatus = MHal_EMAC_ReadReg32(hal, REG_ETH_ISR); ++#if RX_DELAY_INT ++ u32 rx_dely_int = (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108 ) & 0x8000) ? EMAC_INT_RCOM_DELAY : 0; ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK) | rx_dely_int; ++#else ++ intstatus = (intstatus & int_imr & EMAC_INT_MASK); ++#endif ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ intstatus |= (RX_DELAY_INT) ? EMAC_INT_RCOM_DELAY : EMAC_INT_RCOM; ++ } ++ /* ++ if (intstatus & EMAC_INT_ROVR) ++ { ++ // why? ++ MHal_EMAC_WritReg32(REG_ETH_RSR, EMAC_RSROVR); ++ } ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_WritReg32(REG_ETH_TSR, EMAC_UND); ++ } ++ */ ++ return intstatus; ++} ++ ++void MHal_EMAC_IntEnable(void* hal, u32 intMsk, int bEnable) ++{ ++#if RX_DELAY_INT ++ int bRX = (intMsk & (EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM))? 1 : 0; ++#endif ++ unsigned long flags; ++ mhal_emac_t* pHal = (mhal_emac_t*)hal; ++ ++ spin_lock_irqsave(&pHal->lock_irq, flags); ++#if RX_DELAY_INT ++ if (bRX) ++ intMsk &= ~(EMAC_INT_RCOM_DELAY | EMAC_INT_RCOM); ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) | 0x00000080UL; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ if (bRX) ++ { ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104) & ~(0x00000080UL); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, val); ++ } ++ } ++#else ++ if (bEnable) ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, intMsk); ++ } ++ else ++ { ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, intMsk); ++ } ++#endif ++ spin_unlock_irqrestore(&pHal->lock_irq, flags); ++} ++ ++#if 1 ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IER); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IDR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_IMR ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_MAN, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_BUFF, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_FRA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_MCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_OK); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SEQE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ALE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_LCOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ECOL); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_TUE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_CSE); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ROVR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_ELR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_RJB); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SQEE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++#if 0 ++u32 MHal_EMAC_Read_JULIAN_0100(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100(void* hal, int bMIU_reset) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 val = JULIAN_100_VAL; // (0x00000011) ++ u32 val_h = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (!bMIU_reset) ++ val |= 0xF000; ++ if (!pHal->phyRIU) ++ val |= 0x0002; ++ if (PHY_INTERFACE_MODE_RMII != pHal->phy_mode) ++ val |= 0x0004; ++ val = (val_h & 0xFFFF0000) | val; ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0108); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0108, xval); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++#endif ++ ++#if 0 ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(hal, 0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void* hal) ++{ ++ return (MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(void* hal, u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ value &= 0x0000ffff; // unmask interrupt mask as well ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, value); ++} ++ ++#if 0 ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++#endif ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++#if 0 ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++#endif ++ ++void MHal_EMAC_Set_Miu_Highway(void* hal, u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0134, value); ++} ++ ++ ++void MHal_EMAC_HW_init(void* hal) ++{ ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 u32Julian104 = JULIAN_104_VAL; ++ ++ MHal_EMAC_Set_Miu_Priority(hal, 1); ++ MHal_EMAC_Set_Tx_JULIAN_T(hal, 4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(hal, 1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(hal, 2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(hal, 1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(hal, 1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(hal, 2); ++ #endif ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++#if 0 ++#if (EMAC_FLOW_CONTROL_TX == EMAC_FLOW_CONTROL_TX_HW) ++ { ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D); ++ xval = (xval&(~BIT0)) | BIT0; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h4D, xval); ++ } ++#endif ++#endif ++ ++/* ++ { ++#if (TX_QUEUE_CNT_SCHE == 2) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#elif (TX_QUEUE_CNT_SCHE == 3) ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++#endif ++ } ++*/ ++ ++ u32Julian104 |= SOFTWARE_DESCRIPTOR_ENABLE; ++#if RX_CHECKSUM ++ u32Julian104 |= RX_CHECKSUM_ENABLE; ++#endif ++#if TX_CHECKSUM ++ u32Julian104 |= TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, u32Julian104); ++ ++ if (pHal->pTXD) ++ _MHal_EMAC_TXD_Enable(hal); ++ else ++ _MHal_EMAC_TXQ_Enable(hal); ++ MHal_EMAC_IntEnable(hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntStatus(hal); ++ ++ MHal_EMAC_Write_JULIAN_0100(hal, 0); ++} ++ ++void MHal_EMAC_mdio_path(void* hal, int mdio_path) ++{ ++ u32 val = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0100); ++ ++ if (mdio_path) ++ val |= 0x00000002; ++ else ++ val &= 0xfffffffd; ++ ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0100, val); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi(void* hal) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(hal); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL(hal, xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_write_phy(void* hal, unsigned char phy_addr, u32 address, u32 value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_write(hal, phy_addr, address, value); ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++ u32 uRegBase = pHal->phyRIU; ++ phy_addr =0; // dummy instruction ++ ++ // *(volatile unsigned int *)(uRegBase + address*4) = value; ++ *(volatile unsigned int *)(uRegBase + (address<< 2)) = value; ++ udelay( 1 ); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++int MHal_EMAC_read_phy(void* hal, unsigned char phy_addr, u32 address, u32* value ) ++{ ++ return ((mhal_emac_t*)hal)->phy_op.phy_read(hal, phy_addr, address, value); ++ ++#if 0 ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == pHal->phy_type) ++ { ++/* ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++*/ ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + (address<<2)); ++ } ++ else ++ { ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++ *value = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ } ++#endif ++} ++ ++/* ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex(void* hal, int speed, int duplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32(hal, REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( speed == SPEED_100 ) ++ { ++ if ( duplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( duplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32(hal, REG_ETH_CFG, xval ); ++} ++ ++/* ++u8 MHal_EMAC_CalcMACHash(u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++*/ ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq(void* hal) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 uRegVal; ++ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#else ++ hal = hal; ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// #if (KERNEL_PHY == 0) ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq(void* hal) ++{ ++ hal = hal; ++#if 0 ++ ++#endif ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1H); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA1L); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2H); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr(void* hal) ++{ ++ return MHal_EMAC_ReadReg32(hal, REG_ETH_SA2L); ++} ++ ++void MHal_EMAC_Write_SA1H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1H, xval); ++} ++ ++void MHal_EMAC_Write_SA1L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA1L, xval); ++} ++ ++void MHal_EMAC_Write_SA2H(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2H, xval); ++} ++ ++void MHal_EMAC_Write_SA2L(void* hal, u32 xval) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_SA2L, xval); ++} ++ ++#if 0 ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++// #if (KERNEL_PHY == 0) ++#if 0 ++void MHal_EMAC_trim_phy(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ U16 val; ++ ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), val, 0x1F); //overwrite bit[4:0] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3384*2), (val<<8), 0x1F<<8); //overwrite bit[12:8] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3380*2), val, 0xF); //overwrite bit[3:0] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++} ++#endif ++ ++void MHal_EMAC_phy_trunMax(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++// #endif // #if (KERNEL_PHY == 0) ++ ++// clock should be set by clock tree. This function is only for the case of FPGA since clock tree is unavailable ++static void _MHal_EMAC_Clk(void* hal, int bOn) ++{ ++ if (bOn) ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x00); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x45, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x47, 0x01); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk(void* hal, struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //emac_clk gen ++ /* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++ */ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(emac_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ // printk( "[EMAC]can't get parent clock\n" ); ++ clk_put(emac_clks[i]); ++ kfree(emac_clks); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 1); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x00); ++*/ ++ _MHal_EMAC_Clk(hal, 1); ++#endif ++ ++ pHal->phy_op.phy_clk_on(hal); ++} ++ ++void MHal_EMAC_Power_Off_Clk(void* hal, struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ // printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ // printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ clk_put(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ else ++ { ++ _MHal_EMAC_Clk(hal, 0); ++ } ++#else ++/* ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_SCGPCTRL, 0x46, 0x01); ++*/ ++ _MHal_EMAC_Clk(hal, 0); ++#endif ++ ++ pHal->phy_op.phy_clk_off(hal); ++} ++ ++// #if (0 == KERNEL_PHY) ++void MHal_EMAC_Set_Reverse_LED(void* hal, u32 xval) ++{ ++ u8 u8Reg; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ u8Reg = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++ ++u8 MHal_EMAC_Get_Reverse_LED(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++// #endif // #if (0 == KERNEL_PHY) ++ ++/* ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); // useless and un-verified ++ } ++} ++*/ ++ ++static void _MHal_EMAC_TXQ_Enable(void* hal) ++{ ++#if (TX_QUEUE_SIZE != 4) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++#else ++ hal = hal; ++#endif ++} ++ ++static inline int MHal_EMAC_QueueFree_4(void* hal) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(hal); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ return avlfifoval; ++} ++ ++static inline u8 MHal_EMAC_QueueUsed_New(void* hal) ++{ ++#if (TX_QUEUE_CNT_SCHE == 3) ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= (0x1 << 4); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++#endif ++ ++#if ((0 == TX_QUEUE_CNT_SCHE) || (3 == TX_QUEUE_CNT_SCHE)) ++ { ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ return xval; ++ } ++#endif ++#if (2 == TX_QUEUE_CNT_SCHE) ++ int xval; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= TXQUEUE_CNT_LATCH; ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ ++ xval = MHal_EMAC_ReadReg8(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ return xval; ++#endif ++ hal = hal; ++ // printk("[%s][%d] this should not happened\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++///////////////// TXQ ++inline static int _MHal_EMAC_TXQ_Size(void* hal) ++{ ++ hal = hal; ++ return TX_QUEUE_SIZE; ++} ++ ++inline static int _MHal_EMAC_TXQ_Free(void* hal) ++{ ++ int ret; ++#if (4 == TX_QUEUE_SIZE) ++ ret = MHal_EMAC_QueueFree_4(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Used(hal); ++#else ++ #if TX_QUEUE_SIZE_NEW ++ ret = MHal_EMAC_QueueFree_4(hal) + TX_QUEUE_SIZE_NEW - MHal_EMAC_QueueUsed_New(hal); ++ #else ++ ret = MHal_EMAC_QueueFree_4(hal); ++ #endif ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Used(void* hal) ++{ ++ int ret; ++ ++#if (4 == TX_QUEUE_SIZE) ++ ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++#elif (1 == TX_QUEUE_CNT_SCHE) ++ ret = MHal_EMAC_ReadReg32(hal, REG_TXQUEUE_CNT); ++#else ++ // ret = TX_QUEUE_SIZE - MHal_EMAC_TXQ_Free(hal); ++ ///// ret = 4 - MHal_EMAC_QueueFree_4(hal) + MHal_EMAC_QueueUsed_New(hal); ++ ret = 4 + MHal_EMAC_QueueUsed_New(hal) - MHal_EMAC_QueueFree_4(hal); ++#endif ++ return ret; ++} ++ ++inline static int _MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Used(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXQ_Free(hal)) ? 1 : 0; ++} ++ ++inline static int _MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ MHal_EMAC_WritReg32(hal, REG_ETH_TAR, bus); ++ MHal_EMAC_WritReg32(hal, REG_ETH_TCR, len); ++ return 1; ++} ++ ++inline int _MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ hal = hal; ++ return 0; ++} ++ ++///////////////// TXD ++static int _MHal_EMAC_TXD_Size(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num; ++ // return hal_emac[0].TXD_num; ++} ++ ++static int _MHal_EMAC_TXD_Used(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_NUM_MASK; ++} ++ ++static int _MHal_EMAC_TXD_Free(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return pHal->TXD_num - _MHal_EMAC_TXD_Used(hal); ++} ++ ++static int _MHal_EMAC_TXD_Empty(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Used(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Full(void* hal) ++{ ++ return (0 == _MHal_EMAC_TXD_Free(hal)) ? 1 : 0; ++} ++ ++static int _MHal_EMAC_TXD_Insert(void* hal, u32 bus, u32 len) ++{ ++ txd_t* pTXD = NULL; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 write = pHal->TXD_write; ++ ++ if (write >= pHal->TXD_num) ++ { ++ // printk("[%s][%d] this should not happen\n", __FUNCTION__, __LINE__); ++ } ++ pTXD = &(pHal->pTXD[write]); ++ pTXD->addr = bus; ++ pTXD->tag = len; ++ pHal->TXD_write++; ++ if (pHal->TXD_write >= pHal->TXD_num) ++ { ++ pTXD->tag |= TXD_WRAP; ++ pHal->TXD_write = 0; ++ } ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ // printk("[%s][%d] (bus, len, addr, tag, tag) = (0x%08x, %d, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ // bus, len, pTXD[write].addr, pTXD[write].tag); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++/* ++#if 0 ++ if (write & 0x1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT1, 1); ++ } ++ else ++ { ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, REG_TXD_XMIT0, 1); ++ } ++#else ++ // if (0 == (MHal_EMAC_ReadReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1))) & 0x1)) ++ MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x1) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + ((write & 0x0) << 1)), 1); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 2); // Bad, but at least streamming ++ // MHal_EMAC_WritReg8(REG_BANK_EMAC0, (REG_TXD_XMIT0 + (((write & 0x3)>>1) << 1)), 1); // Bad, but at least streamming ++#endif ++*/ ++ // printk("[%s][%d] TXD used number = %d\n", __FUNCTION__, __LINE__, MHal_EMAC_TXD_Used()); ++ // if (write != MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)) ++ // printk("[%s][%d] (write, txd_ptr, read) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, write, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L), hal_emac[0].TXD_read); ++ return 1; ++} ++ ++int _MHal_EMAC_TXD_Mode(void* hal) ++{ ++ hal = hal; ++ return 1; ++} ++ ++#if 0 ++///////////////// wrapper ++int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_size(hal); ++ // return hal_emac[0].txq_op.txq_size(); ++} ++ ++int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_free(hal); ++ // return hal_emac[0].txq_op.txq_free(); ++} ++ ++int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_used(hal); ++ // return hal_emac[0].txq_op.txq_used(); ++} ++ ++int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_empty(hal); ++ // return hal_emac[0].txq_op.txq_empty(); ++} ++ ++int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_full(hal); ++ // return hal_emac[0].txq_op.txq_full(); ++} ++ ++int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_insert(hal, bus, len); ++ // return hal_emac[0].txq_op.txq_insert(bus, len); ++} ++ ++int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return ((mhal_emac_t*)hal)->txq_op.txq_mode(hal); ++ // return hal_emac[0].txq_op.txq_mode(); ++} ++#else ++inline int MHal_EMAC_TXQ_Size(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Size(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Free(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Free(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Used(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Used(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Empty(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Empty(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Full(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Full(hal); ++} ++ ++inline int MHal_EMAC_TXQ_Insert(void* hal, u32 bus, u32 len) ++{ ++ return _MHal_EMAC_TXQ_Insert(hal, bus, len); ++} ++ ++inline int MHal_EMAC_TXQ_Mode(void* hal) ++{ ++ return _MHal_EMAC_TXQ_Mode(hal); ++} ++#endif ++ ++/* ++int MHal_EMAC_TXQ_Done(void* hal) ++{ ++ u32 val; ++ { ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u16 xval; ++ ++ xval = MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23); ++ xval |= 0x0100; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC1, REG_ETH_EMAC1_h23, xval); ++ } ++ val = MHal_EMAC_ReadReg32(hal, 0x00000162); ++ return val & 0x1FFFFFFF; ++} ++*/ ++ ++u32 MHal_EMAC_RX_ParamSet(void* hal, u32 frm_num, u32 frm_cyc) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 j104; ++ ++ if (frm_num > 0x30) ++ frm_num = 0x30; ++ ++ j104 = MHal_EMAC_ReadReg32(hal, REG_EMAC_JULIAN_0104); ++ pHal->u8RxFrameCnt = (u8)((j104 >> 16) & 0xFF); ++ pHal->u8RxFrameCyc = (u8)((j104 >> 24) & 0xFF); ++ ++ // printk("[%s][%d] frame number = 0x%02x\n", __FUNCTION__, __LINE__, frm_num); ++ // upper 16 bits for julian 104 ++/* ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (frm_num & 0xFF)); ++ if (0xFFFFFFFF != frm_cyc) ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (frm_cyc & 0xFF)); ++*/ ++ if (0xFFFFFFFF == frm_cyc) ++ frm_cyc = pHal->u8RxFrameCyc; ++ j104 = (j104 & 0x0000FFFF) | ((frm_cyc & 0xFF) << 24) | ((frm_num & 0xFF) << 16); ++ MHal_EMAC_WritReg32(hal, REG_EMAC_JULIAN_0104, j104); ++#else ++ if (frm_num < 0x80) ++ MHal_EMAC_WritReg32(hal, REG_ETH_IER, EMAC_INT_RCOM); ++ else ++ MHal_EMAC_WritReg32(hal, REG_ETH_IDR, EMAC_INT_RCOM); ++#endif ++ return RX_DELAY_INT; ++} ++ ++u32 MHal_EMAC_RX_ParamRestore(void* hal) ++{ ++#if (RX_DELAY_INT) ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++/* ++ // upper 16 bits for julian 104 ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x06, (pHal->u8RxFrameCnt & 0xFF)); ++ MHal_EMAC_WritReg8(pHal->emacRIU, REG_BANK_EMAC1, 0x07, (pHal->u8RxFrameCyc & 0xFF)); ++*/ ++ MHal_EMAC_RX_ParamSet(hal, pHal->u8RxFrameCnt, pHal->u8RxFrameCyc); ++#else ++#endif ++ return RX_DELAY_INT; ++} ++ ++// int MHal_EMAC_TXD_Cfg(u32 emacId, u32 TXD_num) ++int MHal_EMAC_TXD_Cfg(void* hal, u32 TXD_num) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ if (0 == TXD_CAP) ++ return 0; ++ if (TXD_num & ~TXD_NUM_MASK) ++ { ++ // printk("[%s][%d] Invalid TXD number %d\n", __FUNCTION__, __LINE__, TXD_num); ++ return 0; ++ } ++ // hal_emac[0].TXD_num = TXD_num; ++ pHal->TXD_num = TXD_num; ++ return TXD_num * TXD_SIZE; ++} ++ ++int MHal_EMAC_TXD_Buf(void* hal, void* p, dma_addr_t bus, u32 len) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ // mhal_emac_t* pEEng = &hal_emac[0]; ++ int ret = 0; ++ ++ if (0 == TXD_CAP) ++ goto jmp_ptr_set; ++ if ((!p) || (!bus)) ++ goto jmp_ptr_set; ++ if (0 == pHal->TXD_num) ++ goto jmp_ptr_set; ++ if (len/TXD_SIZE != pHal->TXD_num) ++ goto jmp_ptr_set; ++ memset(p, 0, len); ++ wmb(); ++ Chip_Flush_MIU_Pipe(); ++ pHal->pTXD = (txd_t*)p; ++ pHal->TXD_write = 0; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, 0); ++ MHal_EMAC_WritReg32(hal, REG_TXD_BASE, bus); ++ ret = 1; ++jmp_ptr_set: ++ if (pHal->pTXD) ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXD_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXD_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXD_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXD_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXD_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXD_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXD_Mode; ++ } ++ else ++ { ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ } ++ return ret; ++} ++ ++static void _MHal_EMAC_TXD_Enable(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ MHal_EMAC_WritReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_CFG, (pHal->TXD_num & TXD_NUM_MASK) | TXD_ENABLE); ++} ++ ++#if 0 ++u32 MHal_EMAC_TXD_OVR(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ return (MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_STAT) & TXD_OVR) ? 1 : 0; ++} ++#endif ++ ++#if 0 ++int MHal_EMAC_TXD_Dump(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 used = _MHal_EMAC_TXD_Used(hal); ++ // int i; ++#if 0 ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] (p, num, used, write, read, ptr) = (0x%08x, %3d, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, pHal->TXD_read, MHal_EMAC_ReadReg16(REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#else ++ printk("[%s][%d] (p, num, used, write, ptr) = (0x%08x, %3d, %3d, %3d, %3d)\n", __FUNCTION__, __LINE__, ++ (int)pHal->pTXD, pHal->TXD_num, used, ++ pHal->TXD_write, MHal_EMAC_ReadReg16(pHal->emacRIU, REG_BANK_EMAC0, REG_TXD_PTR_L)); ++#endif ++ ++#if 0 ++ if (NULL == pHal->pTXD) ++ return 1; ++ for (i = 0; i < pHal->TXD_num; i++) ++ { ++ txd_t* pTXD = &(pHal->pTXD[i]); ++ printk("[%d] (addr, tag, reserved0, reserved1) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", i, pTXD->addr, pTXD->tag, pTXD->reserve0, pTXD->reserve1); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++void* MHal_EMAC_Alloc(u32 riu, u32 x32, u32 riu_phy) ++{ ++ mhal_emac_t* pHal = kzalloc(sizeof(mhal_emac_t), GFP_KERNEL); ++ ++ if (0 == pHal) ++ { ++ printk("[%s][%d] allocate emac hal handle fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++#if 0 ++ pHal->emacRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu); ++ pHal->emacX32 = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), x32); ++ pHal->phyRIU = GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), riu_phy); ++#else ++ pHal->emacRIU = riu; ++ pHal->emacX32 = x32; ++ pHal->phyRIU = riu_phy; ++#endif ++ pHal->pTXD = NULL; ++ pHal->TXD_num = 0; ++ pHal->TXD_write = 0; ++ // pHal->phy_type = 0; ++ pHal->txq_op.txq_size = _MHal_EMAC_TXQ_Size; ++ pHal->txq_op.txq_free = _MHal_EMAC_TXQ_Free; ++ pHal->txq_op.txq_used = _MHal_EMAC_TXQ_Used; ++ pHal->txq_op.txq_empty = _MHal_EMAC_TXQ_Empty; ++ pHal->txq_op.txq_full = _MHal_EMAC_TXQ_Full; ++ pHal->txq_op.txq_insert = _MHal_EMAC_TXQ_Insert; ++ pHal->txq_op.txq_mode = _MHal_EMAC_TXQ_Mode; ++ ++ if (pHal->phyRIU) ++ { ++#if 0 ++ // internal ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use internal phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_albany_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_albany_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_albany_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_albany_clk_off; ++ } ++ else ++ { ++#if 0 ++ // external ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] use external phy\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] ***********************************************\n", __FUNCTION__, __LINE__); ++#endif ++ pHal->phy_op.phy_write = _MHal_EMAC_ext_write; ++ pHal->phy_op.phy_read = _MHal_EMAC_ext_read; ++ pHal->phy_op.phy_clk_on = _MHal_EMAC_ext_clk_on; ++ pHal->phy_op.phy_clk_off = _MHal_EMAC_ext_clk_off; ++ } ++#if (RX_DELAY_INT) ++ pHal->u8RxFrameCnt = (JULIAN_104_VAL >> 16) & 0xFF; ++ pHal->u8RxFrameCyc = (JULIAN_104_VAL >> 24) & 0xFF; ++#endif ++ ++ // MHal_EMAC_Write_JULIAN_0100((void*)pHal, 0); ++ spin_lock_init (&pHal->lock_irq); ++ return (void*)pHal; ++} ++ ++void MHal_EMAC_Free(void* hal) ++{ ++ if (NULL == hal) ++ { ++ // printk("[%s][%d] Try to free NULL emac hal handle\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ kfree(hal); ++} ++ ++static int _MHal_EMAC_albany_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ ++ if (0 != phy_addr) ++ return -1; ++ ++ *(volatile unsigned int *)(uRegBase + (addr << 2)) = val; ++ udelay(1); ++ return 0; ++} ++ ++static int _MHal_EMAC_albany_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ u32 uRegBase = pHal->phyRIU; ++ u32 tempvalue ; ++ ++ *val = 0xffff; ++ if (0 != phy_addr) ++ return 0xffff; ++ ++ if (MII_PHYSID1 == addr) ++ { ++ *val = 0x1111; ++ return 0x1111; ++ } ++ if (MII_PHYSID2 == addr) ++ { ++ *val = 0x2222; ++ return 0x2222; ++ } ++ ++ tempvalue = *(volatile unsigned int *)(uRegBase + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(uRegBase + 0x04) = tempvalue; ++ udelay( 1 ); ++ *val = *(volatile unsigned int *)(uRegBase + (addr <<2)); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_albany_clk_on(void* hal) ++{ ++ u8 uRegVal; ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ uRegVal = MHal_EMAC_ReadReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80); ++ uRegVal = (uRegVal & 0xCF) | 0x30; ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x80, uRegVal); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++#if 0 ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0== mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk) | (pHal->pad_led_val & pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++} ++ ++static void _MHal_EMAC_albany_clk_off(void* hal) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ /* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++ */ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(pHal->phyRIU, REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++#if 0 ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_PMSLEEP, 0x50, uRegVal); ++#else ++ #ifdef CONFIG_MS_PADMUX ++ if (0 == mdrv_padmux_active()) ++ #endif ++ { ++ if (pHal->pad_led_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_led_reg); ++ u32Val = (u32Val & ~pHal->pad_led_msk); ++ *((volatile u32*)pHal->pad_led_reg) = u32Val; ++ } ++ } ++#endif ++} ++ ++#define PHY_IAC_TIMEOUT HZ ++ ++static int _MHal_EMAC_ext_busy_wait(void* hal) ++{ ++ unsigned long t_start = jiffies; ++ u32 uRegVal = 0; ++ ++ while (1) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ if (uRegVal & EMAC_IDLE) ++ return 0; ++ if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) ++ break; ++ barrier(); ++ } ++ printk("[%s][%d] mdio: MDIO timeout\n", __FUNCTION__, __LINE__); ++ return -1; ++} ++ ++static int _MHal_EMAC_ext_write(void* hal, u8 phy_addr, u32 addr, u32 val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( addr << PHY_REGADDR_OFFSET ) | (val & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++#if 0 ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ return -1; ++ } ++#endif ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, val); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ return 0; ++} ++ ++static int _MHal_EMAC_ext_read(void* hal, u8 phy_addr, u32 addr, u32* val) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ ++ *val = 0xffff; ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (addr << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(hal); ++ MHal_EMAC_enable_mdi(hal); ++ MHal_EMAC_Write_MAN(hal, uRegVal); ++ ++#if 0 ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); //Must read Low 16 bit. ++ while (!(uRegVal & EMAC_IDLE)) ++ { ++ uRegVal = MHal_EMAC_ReadReg32(hal, REG_ETH_SR); ++ barrier(); ++ } ++#else ++ if (_MHal_EMAC_ext_busy_wait(hal)) ++ { ++ printk("[%s][%d] (addr, reg) = (%d, %d) timeout\n", __FUNCTION__, __LINE__, phy_addr, addr); ++ return 0xffff; ++ } ++#endif ++ *val = (MHal_EMAC_Read_MAN(hal) & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(hal, uCTL); ++ // printk("[%s][%d] (addr, reg, val) = (%d, %d, 0x%08x) OK\n", __FUNCTION__, __LINE__, phy_addr, addr, *val); ++ // printk("[%s][%d] val = 0x%08x\n", __FUNCTION__, __LINE__, *val); ++ return *val; ++} ++ ++static void _MHal_EMAC_ext_clk_on(void* hal) ++{ ++#if 0 ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(EMAC_RIU_REG_BASE, REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#else ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++#ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ return; ++#endif ++ ++ if (pHal->pad_reg) ++ { ++ u32 u32Val; ++ ++ u32Val = *((volatile u32*)pHal->pad_reg); ++ u32Val = (u32Val & ~pHal->pad_msk) | (pHal->pad_val & pHal->pad_msk); ++ *((volatile u32*)pHal->pad_reg) = u32Val; ++ } ++#endif ++} ++ ++static void _MHal_EMAC_ext_clk_off(void* hal) ++{ ++ hal = hal; ++} ++ ++void MHal_EMAC_Pad(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_reg = reg; ++ pHal->pad_msk = msk; ++ pHal->pad_val = val; ++} ++ ++void MHal_EMAC_PadLed(void* hal, u32 reg, u32 msk, u32 val) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ ++ pHal->pad_led_reg = reg; ++ pHal->pad_led_msk = msk; ++ pHal->pad_led_val = val; ++} ++ ++void MHal_EMAC_PhyMode(void* hal, u32 phy_mode) ++{ ++ mhal_emac_t* pHal = (mhal_emac_t*) hal; ++ pHal->phy_mode = phy_mode; ++} ++ ++int MHal_EMAC_FlowControl_TX(void* hal) ++{ ++ hal = hal; ++ return 0; ++} +diff --git a/drivers/sstar/emac_toe/hal/infinity6e/mhal_emac.h b/drivers/sstar/emac_toe/hal/infinity6e/mhal_emac.h +new file mode 100755 +index 000000000000..310971590863 +--- /dev/null ++++ b/drivers/sstar/emac_toe/hal/infinity6e/mhal_emac.h +@@ -0,0 +1,494 @@ ++/* SigmaStar trade secret */ ++/* ++* mhal_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_EMAC__ ++#define __HAL_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM 1 ++#define TX_CHECKSUM 0 ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++/* ++#define EMAC_FLOW_CONTROL_TX EMAC_FLOW_CONTROL_TX_NA ++#define EMAC_FLOW_CONTROL_TX_NA 0 ++#define EMAC_FLOW_CONTROL_TX_SW 1 ++#define EMAC_FLOW_CONTROL_TX_HW 2 ++ ++#define EMAC_FLOW_CONTROL_RX 0 ++*/ ++ ++/* ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++// #define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++*/ ++ ++ ++// Compiler Switches ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++// #define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_PMSLEEP 0x000E ++ ++#if 0 ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#else ++#define REG_BANK_EMAC0 0x0000 // 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x0001 // 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x0002 // 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x0003 // 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x0000 // 0x1A1E ++#define REG_BANK_X32_EMAC2 0x0001 // 0x1A1F ++#define REG_BANK_X32_EMAC3 0x0002 // 0x1A20 ++#define REG_BANK_ALBANY0 0x0000 // 0x0031 ++#define REG_BANK_ALBANY1 0x0001 // 0x0032 ++#define REG_BANK_ALBANY2 0x0002 // 0x0033 ++#endif ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++// #define EMAC_SPEED_10 10 ++// #define EMAC_SPEED_100 100 ++ ++#if 0 ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#endif ++// #define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++// #define EMAC_RIU_REG_BASE 0xFD000000 ++ ++#if 0 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++ ++// Base address here: ++#endif ++ ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_MAX_TX_QUEUE 1000 ++#define MIU0_BUS_BASE 0x20000000 ++ ++// #define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#if 0 ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#endif ++ ++/* ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_RNG_REG_H_ ++#define _MHAL_RNG_REG_H_ ++ ++// unit: ms< --> ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/emac_toe/mdrv_emac.c b/drivers/sstar/emac_toe/mdrv_emac.c +new file mode 100755 +index 000000000000..b83fb48cc38b +--- /dev/null ++++ b/drivers/sstar/emac_toe/mdrv_emac.c +@@ -0,0 +1,4715 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_emac.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#endif ++ ++#include "mdrv_types.h" ++//#include "mst_platform.h" ++//#include "mdrv_system.h" ++//#include "chip_int.h" ++#include "ms_msys.h" ++#include "mhal_emac.h" ++#include "mdrv_emac.h" ++#include "ms_platform.h" ++#include "registers.h" ++ ++#ifdef CONFIG_EMAC_SUPPLY_RNG ++#include ++#include ++#include "mhal_rng_reg.h" ++#endif ++ ++// #include "mdrv_msys_io_st.h" ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "gpio.h" ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#include "mdrv_puse.h" ++#endif ++ ++#ifdef CONFIG_SS_SWTOE ++#include "mdrv_swtoe.h" ++#endif ++ ++#ifdef CONFIG_MS_GPIO ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); ++#else ++#define MDrv_GPIO_Set_Low(x) ++#define MDrv_GPIO_Set_High(x) ++#define MDrv_GPIO_Pad_Set(x) ++#endif ++ ++ ++///////////////////////////////// ++// to be refined ++///////////////////////////////// ++#define TXD_NUM 0 ++// #define TXQ_NUM_SW 256 ++#define TXQ_NUM_SW 0 ++ ++#if EXT_PHY_PATCH ++#define IS_EXT_PHY(hemac) (0 == (hemac)->phyRIU) ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// helper definition ++//-------------------------------------------------------------------------------------------------- ++#define CLR_BITS(a, bits) ((a) & (~(bits))) ++#define SET_BITS(a, bits) ((a) | (bits)) ++ ++#define PA2BUS(a) CLR_BITS(a, MIU0_BUS_BASE) ++#define BUS2PA(a) SET_BITS(a, MIU0_BUS_BASE) ++ ++#define BUS2VIRT(a) phys_to_virt(BUS2PA((a))) ++#define VIRT2BUS(a) PA2BUS(virt_to_phys((a))) ++ ++#define VIRT2PA(a) virt_to_phys((a)) ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#if MSTAR_EMAC_NAPI ++#define EMAC_NAPI_WEIGHT 32 ++#endif ++ ++#ifdef CONFIG_SS_SWTOE ++#define RX_DESC_NUM 0 ++#define RX_DESC_SIZE 0 ++#define RX_DESC_QUEUE_SIZE 0 ++#else ++#define RX_DESC_NUM 0x100 ++#define RX_DESC_SIZE (sizeof(struct rbf_t)) ++#define RX_DESC_QUEUE_SIZE (RX_DESC_NUM * RX_DESC_SIZE) ++#endif ++ ++#define EMAC_PACKET_SIZE_MAX 0x600 ++ ++#if EMAC_SG ++ #define FEATURES_EMAC_SG (NETIF_F_SG) ++#else ++ #define FEATURES_EMAC_SG (0) ++#endif ++ ++#if (EMAC_GSO) ++ #define FEATURES_EMAC_GSO ((NETIF_F_GSO) | (NETIF_F_GRO)) ++#else ++ #define FEATURES_EMAC_GSO (0) ++#endif ++ ++#if RX_CHECKSUM ++ #define FEATURES_EMAC_CSUM_RX (NETIF_F_RXCSUM) ++#else ++ #define FEATURES_EMAC_CSUM_RX (0) ++#endif ++ ++#if TX_CHECKSUM ++ #define FEATURES_EMAC_CSUM_TX (NETIF_F_HW_CSUM) ++#else ++ #define FEATURES_EMAC_CSUM_TX (0) ++#endif ++ ++#define EMAC_FEATURES (FEATURES_EMAC_SG | FEATURES_EMAC_GSO | FEATURES_EMAC_CSUM_RX | FEATURES_EMAC_CSUM_TX) ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++// #define EMAC_RX_TMR (0) ++// #define EMAC_LINK_TMR (1) ++// #define EMAC_FLOW_CTL_TMR (2) ++ ++// #define TIMER_EMAC_DYNAMIC_RX (1) ++// #define TIMER_EMAC_FLOW_TX (2) ++ ++#define EMAC_CHECK_LINK_TIME (HZ) ++ ++#define IDX_CNT_INT_DONE (0) ++#define IDX_CNT_INT_RCOM (1) ++#define IDX_CNT_INT_RBNA (2) ++#define IDX_CNT_INT_TOVR (3) ++#define IDX_CNT_INT_TUND (4) ++#define IDX_CNT_INT_RTRY (5) ++#define IDX_CNT_INT_TBRE (6) ++#define IDX_CNT_INT_TCOM (7) ++#define IDX_CNT_INT_TIDLE (8) ++#define IDX_CNT_INT_LINK (9) ++#define IDX_CNT_INT_ROVR (10) ++#define IDX_CNT_INT_HRESP (11) ++#define IDX_CNT_JULIAN_D (12) ++#define IDX_CNT_INT_TXQUEUE_THRESHOLD (24) // (EMAC)(I3E) ++#define IDX_CNT_INT_TXQUEUE_EMPTY (25) // (EMAC)(I3E) ++#define IDX_CNT_INT_TXQUEUE_DROP (26) // (EMAC)(I3E) ++ ++#define RX_THROUGHPUT_TEST 0 ++#define TX_THROUGHPUT_TEST 0 ++ ++#ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++#define PACKET_THRESHOLD 260 ++#define TXCOUNT_THRESHOLD 10 ++#endif ++ ++#if EMAC_FLOW_CONTROL_TX ++#define MAC_CONTROL_TYPE 0x8808 ++#define MAC_CONTROL_OPCODE 0x0001 ++#define PAUSE_QUANTA_TIME_10M ((1000000*10)/500) ++#define PAUSE_QUANTA_TIME_100M ((1000000*100)/500) ++#define PAUSE_TIME_DIVISOR_10M (PAUSE_QUANTA_TIME_10M/HZ) ++#define PAUSE_TIME_DIVISOR_100M (PAUSE_QUANTA_TIME_100M/HZ) ++#endif // #if EMAC_FLOW_CONTROL_TX ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++// u32 contiROVR = 0; ++// u32 initstate= 0; ++// u8 txidx =0; ++// u32 txcount = 0; ++// spinlock_t emac_lock; ++ ++static u8 _u8Minor = MINOR_EMAC_NUM; ++struct sk_buff *pseudo_packet; ++ ++#if TX_THROUGHPUT_TEST ++unsigned char packet_content[] = { ++0xa4, 0xba, 0xdb, 0x95, 0x25, 0x29, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x08, 0x00, 0x45, 0x00, ++0x05, 0xda, 0x69, 0x0a, 0x40, 0x00, 0x40, 0x11, 0xbe, 0x94, 0xac, 0x10, 0x5a, 0xe3, 0xac, 0x10, ++0x5a, 0x70, 0x92, 0x7f, 0x13, 0x89, 0x05, 0xc6, 0x0c, 0x5b, 0x00, 0x00, 0x03, 0x73, 0x00, 0x00, ++0x00, 0x65, 0x00, 0x06, 0xe1, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++0x13, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x18, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39 ++}; ++#endif ++ ++#ifndef CONFIG_SS_SWTOE ++static unsigned int max_rx_packet_count=0; ++static unsigned int max_tx_packet_count=0; ++static unsigned int min_tx_fifo_idle_count=0xffff; ++static unsigned int tx_bytes_per_timerbak=0; ++// static unsigned int tx_bytes_per_timer=0; ++// u32 RAM_ALLOC_SIZE=0; ++ ++// static unsigned int gu32GatingRxIrqTimes=0; ++ ++ ++int rx_packet_cnt = 0; ++ ++static struct timespec rx_time_last = { 0 }; ++static int rx_duration_max = 0; ++#endif ++ ++static int _phyReset = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++// static struct timer_list EMAC_timer, hemac->timer_link; ++// static struct timer_list hemac->timer_link; ++#if RX_THROUGHPUT_TEST ++static struct timer_list RX_timer; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Function ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_tx (struct sk_buff *skb, struct net_device *dev); ++static int MDev_EMAC_SwReset(struct net_device *dev); ++static void MDev_EMAC_dts(struct net_device*); ++#if EMAC_FLOW_CONTROL_TX ++static int _MDrv_EMAC_Pause_TX(struct net_device* emac_dev, struct sk_buff* skb, unsigned char* p_recv); ++static void _MDev_EMAC_FlowTX_CB(unsigned long data); ++#endif ++#if REDUCE_CPU_FOR_RBNA ++static void _MDev_EMAC_IntRX_CB(unsigned long data); ++#endif // #if REDUCE_CPU_FOR_RBNA ++ ++// static void MDev_EMAC_timer_callback( unsigned long value ); ++// static void MDev_EMAC_timer_LinkStatus(unsigned long data); ++ ++#ifdef CONFIG_SS_SWTOE ++#else ++static void free_rx_skb(struct emac_handle *hemac) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ int i = 0; ++ // unsigned long flags; ++ ++ if (NULL == rxinfo->skb_arr) ++ return; ++ ++ // spin_lock_irqsave(&hemac->mutexRXD, flags); ++ for (i = 0; i < rxinfo->num_desc; i ++) ++ { ++ if (rxinfo->skb_arr[i]) ++ kfree_skb(rxinfo->skb_arr[i]); ++ } ++ // spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++} ++ ++// unsigned long oldTime; ++// unsigned long PreLinkStatus; ++#if MSTAR_EMAC_NAPI ++static int MDev_EMAC_napi_poll(struct napi_struct *napi, int budget); ++#endif ++#endif // #ifdef CONFIG_SS_SWTOE ++ ++#ifdef CONFIG_MSTAR_EEE ++static int MDev_EMAC_IS_TX_IDLE(void); ++#endif //CONFIG_MSTAR_EEE ++ ++ ++//!!!! PACKET_DUMP has not been tested as they are not used. 2016/07/18 ++#if defined(PACKET_DUMP) ++extern struct file* msys_kfile_open(const char* path, int flags, int rights); ++extern void msys_kfile_close(struct file* fp); ++extern int msys_kfile_write(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size); ++ ++static int txDumpCtrl=0; ++static int rxDumpCtrl=0; ++static int txDumpFileLength=0; ++static int rxDumpFileLength=0; ++static char txDumpFileName[32]={0}; ++static char rxDumpFileName[32]={0}; ++static struct file* txDumpFile=NULL; ++static struct file* rxDumpFile=NULL; ++ ++static ssize_t tx_dump_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ txDumpCtrl = simple_strtoul(buf, NULL, 10); ++ if(1==txDumpCtrl) ++ { ++ strcpy(txDumpFileName,"/tmp/emac/tx_dump"); ++ txDumpFile=msys_kfile_open(rxDumpFileName, O_RDWR | O_CREAT, 0644); ++ if(NULL!=txDumpFile) ++ { ++ txDumpFileLength=0; ++ // printk(KERN_WARNING"success to open emac tx_dump file, '%s'...\n",txDumpFileName); ++ } ++ else ++ { ++ // printk(KERN_WARNING"failed to open emac tx_dump file, '%s'!!\n",txDumpFileName); ++ } ++ } ++ else if(0==txDumpCtrl && txDumpFile!=NULL) ++ { ++ ++ msys_kfile_close(txDumpFile); ++ txDumpFile=NULL; ++ } ++ return count; ++} ++static ssize_t tx_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", txDumpCtrl); ++} ++DEVICE_ATTR(tx_dump, 0644, tx_dump_show, tx_dump_store); ++ ++static ssize_t rx_dump_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ rxDumpCtrl = simple_strtoul(buf, NULL, 10); ++ if(1==rxDumpCtrl) ++ { ++ strcpy(rxDumpFileName,"/tmp/emac/rx_dump"); ++ rxDumpFile=msys_kfile_open(rxDumpFileName, O_RDWR | O_CREAT, 0644); ++ if(NULL!=rxDumpFile) ++ { ++ rxDumpFileLength=0; ++ // printk(KERN_WARNING"success to open emac rx_dump file, '%s'...\n",rxDumpFileName); ++ } ++ else ++ { ++ // printk(KERN_WARNING"failed to open emac rx_dump file, '%s'!!\n",rxDumpFileName); ++ } ++ } ++ else if(0==rxDumpCtrl) ++ { ++ if(rxDumpFile!=NULL) ++ { ++ msys_kfile_close(rxDumpFile); ++ rxDumpFile=NULL; ++ } ++ } ++ return count; ++} ++static ssize_t rx_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", rxDumpCtrl); ++} ++DEVICE_ATTR(rx_dump, 0644, rx_dump_show, rx_dump_store); ++#endif ++ ++static unsigned long getCurMs(void) ++{ ++ struct timeval tv; ++ unsigned long curMs; ++ ++ do_gettimeofday(&tv); ++ curMs = tv.tv_usec/1000; ++ curMs += tv.tv_sec * 1000; ++ return curMs; ++} ++ ++#if RX_THROUGHPUT_TEST ++int receive_bytes = 0; ++static void RX_timer_callback( unsigned long value){ ++ int get_bytes = receive_bytes; ++ int cur_speed; ++ receive_bytes = 0; ++ ++ cur_speed = get_bytes*8/20/1024; ++ printk(" %dkbps",cur_speed); ++ RX_timer.expires = jiffies + 20*EMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// skb_queue implementation ++//------------------------------------------------------------------------------------------------- ++#ifndef CONFIG_SS_SWTOE ++#define SKBQ_SANITY 0 ++static int skb_queue_create(skb_queue* skb_q, int size, int size1) ++{ ++ if ((NULL == skb_q) || (0 == size)) ++ return 0; ++ // skb_q->size = size + 1; ++ skb_q->size[0] = size + 1; ++ skb_q->size[1] = size1 + 1; ++ if (NULL == (skb_q->skb_info_arr = kzalloc(skb_q->size[1]*sizeof(skb_info), GFP_KERNEL))) ++ return 0; ++ skb_q->read = skb_q->write = skb_q->rw = 0; ++ return 1; ++} ++ ++static int skb_queue_destroy(skb_queue* skb_q) ++{ ++ int i; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ for (i = 0; i < skb_q->size[1]; i++) ++ { ++ if (skb_q->skb_info_arr[i].skb) ++ { ++ dev_kfree_skb_any(skb_q->skb_info_arr[i].skb); ++ hemac->skb_tx_free++; ++ } ++ } ++ kfree(skb_q->skb_info_arr); ++ skb_q->skb_info_arr = NULL; ++ skb_q->size[0] = skb_q->size[1] = skb_q->read = skb_q->write = skb_q->rw = 0; ++ return 1; ++} ++ ++static int skb_queue_reset(skb_queue* skb_q) ++{ ++ int i; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ for (i = 0; i < skb_q->size[1]; i++) ++ { ++ if (skb_q->skb_info_arr[i].skb) ++ { ++ dev_kfree_skb_any(skb_q->skb_info_arr[i].skb); ++ hemac->skb_tx_free++; ++ } ++ } ++ memset(skb_q->skb_info_arr, 0, skb_q->size[1]*sizeof(skb_info)); ++ skb_q->read = skb_q->write = skb_q->rw = 0; ++ return 1; ++} ++ ++#define QUEUE_USED(size, read, write) ((write) >= (read))? ((write) - (read)) : ((size) - (read) + (write)) ++#define QUEUE_FREE(size, read, write) ((write) >= (read))? ((size) - (write) + (read) - 1) : ((read) - (write) - 1) ++/* ++static int skb_queue_used(skb_queue* skb_q, int idx, int idx_size) ++{ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++#endif ++ if (2 == idx) ++ return QUEUE_USED(skb_q->size[1], skb_q->rw, skb_q->write); ++ return (0 == idx) ? ++ QUEUE_USED(skb_q->size[idx_size], skb_q->read, skb_q->rw) : ++ QUEUE_USED(skb_q->size[idx_size], skb_q->read, skb_q->write); ++} ++*/ ++inline static int skb_queue_used(skb_queue* skb_q, int idx) ++{ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++#endif ++ if (2 == idx) ++ return QUEUE_USED(skb_q->size[1], skb_q->rw, skb_q->write); ++ return (0 == idx) ? ++ QUEUE_USED(skb_q->size[1], skb_q->read, skb_q->rw) : ++ QUEUE_USED(skb_q->size[1], skb_q->read, skb_q->write); ++} ++ ++inline static int skb_queue_free(skb_queue* skb_q, int idx) ++{ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++#endif ++ // return skb_q->size[idx] - skb_queue_used(skb_q, idx) - 1; ++ if (2 == idx) ++ return QUEUE_FREE(skb_q->size[1], skb_q->rw, skb_q->write); ++ return (0 == idx) ? ++ QUEUE_FREE(skb_q->size[1], skb_q->read, skb_q->rw) : ++ QUEUE_FREE(skb_q->size[1], skb_q->read, skb_q->write); ++} ++ ++inline static int skb_queue_remove(skb_queue* skb_q, struct sk_buff** pskb, dma_addr_t* pphys, int bSkbFree, int idx) ++{ ++ skb_info* pskb_info; ++ int read; ++ int len; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ if (0 == skb_queue_used(skb_q, idx)) ++ { ++ printk("[%s][%d] why\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ read = skb_q->read; ++ pskb_info = &(skb_q->skb_info_arr[read]); ++#if SKBQ_SANITY ++ if ((!pskb_info->skb) && (!pskb_info->skb_phys)) ++ { ++ printk("[%s][%d] strange remove\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++#endif ++ len = pskb_info->skb_len; ++ ++ // printk("[%s][%d] (skb, addr, len) = (0x%08x, 0x%08x, %d)\n", __FUNCTION__, __LINE__, (int)pskb_info->skb, VIRT2BUS(pskb_info->skb->data), len); ++ ++ hemac->skb_tx_free++; ++ if (bSkbFree) ++ { ++ if (pskb_info->skb) ++ { ++ if (0xFFFFFFFF == (int)pskb_info->skb) ++ { ++ void* p = BUS2VIRT(pskb_info->skb_phys); ++ kfree(p); ++ } ++ else ++ { ++ dev_kfree_skb_any(pskb_info->skb); ++ } ++ pskb_info->skb = NULL; ++ // hemac->skb_tx_free++; ++ } ++ } ++ else ++ { ++ *pskb = pskb_info->skb; ++ *pphys = pskb_info->skb_phys; ++ } ++ pskb_info->skb_phys = 0; ++ pskb_info->skb_len = 0; ++ ++ skb_q->read++; ++ if (skb_q->read >= skb_q->size[1]) ++ skb_q->read -= skb_q->size[1]; ++ return len; ++} ++ ++inline static int skb_queue_insert(skb_queue* skb_q, struct sk_buff* skb, dma_addr_t phys, int skb_len, int idx) ++{ ++ skb_info* pskb_info; ++ int* pwrite = NULL; ++ struct emac_handle *hemac = container_of(skb_q, struct emac_handle, skb_queue_tx); ++ ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ if (0 == skb_queue_free(skb_q, idx)) ++ { ++ printk("[%s][%d] why\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ pwrite = (0 == idx) ? &skb_q->rw : &skb_q->write; ++ pskb_info = &(skb_q->skb_info_arr[*pwrite]); ++ // if ((pskb_info->used) || (pskb_info->skb)) ++ // if (pskb_info->used) ++#if SKBQ_SANITY ++ if ((pskb_info->skb) || (pskb_info->skb_phys)) ++ { ++ printk("[%s][%d] strange insert\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++#endif ++ // if (skb) ++ hemac->skb_tx_send++; ++ // pskb_info->used = 1; ++ pskb_info->skb_phys = phys; ++ pskb_info->skb_len = skb_len; ++ pskb_info->skb = skb; ++ (*pwrite)++; ++ if (*pwrite >= skb_q->size[1]) ++ (*pwrite) -= skb_q->size[1]; ++ return 1; ++} ++ ++inline static int skb_queue_head_inc(skb_queue* skb_q, struct sk_buff** skb, dma_addr_t* pphys, int* plen, int idx) ++{ ++ skb_info* pskb_info; ++ int* pwrite = NULL; ++#if SKBQ_SANITY ++ if (NULL == skb_q->skb_info_arr) ++ return 0; ++ if (0 == skb_queue_free(skb_q, idx)) ++ { ++ printk("[%s][%d] why\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ *skb = NULL; ++ *pphys = 0; ++ pwrite = (0 == idx) ? &skb_q->rw : &skb_q->write; ++ pskb_info = &(skb_q->skb_info_arr[*pwrite]); ++#if SKBQ_SANITY ++ // if ((!pskb_info->skb) || (!pskb_info->skb_phys)) ++ if ((!pskb_info->skb_phys)) ++ { ++ printk("[%s][%d] strange head inc\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++#endif ++ *skb = pskb_info->skb; ++ *pphys = pskb_info->skb_phys; ++ *plen = pskb_info->skb_len; ++ (*pwrite)++; ++ if (*pwrite >= skb_q->size[1]) ++ (*pwrite) -= skb_q->size[1]; ++ return 1; ++} ++ ++/* ++static int skb_queue_emtpy(skb_queue* skb_q) ++{ ++ return (skb_queue_used(skb_q))? 0 : 1; ++} ++*/ ++ ++inline static int skb_queue_full(skb_queue* skb_q, int idx) ++{ ++ return (skb_queue_free(skb_q, idx))? 0 : 1; ++} ++ ++/* ++static int skb_queue_size(skb_queue* skb_q, int idx) ++{ ++ return skb_q->size[idx] - 1; ++} ++*/ ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++//------------------------------------------------------------------------------------------------- ++// PHY MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Access the PHY to determine the current Link speed and Mode, and update the ++// MAC accordingly. ++// If no link or auto-negotiation is busy, then no changes are made. ++// Returns: 0 : OK ++// -1 : No link ++// -2 : AutoNegotiation still in progress ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_update_linkspeed (struct net_device *dev) ++{ ++ u32 bmsr, bmcr, adv, lpa, neg; ++ u32 speed, duplex; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ u32 hcd_link_st_ok, an_100t_link_st = 0; ++ static unsigned int phy_restart_cnt = 0; ++ u32 an_state = 0; ++ u32 an_state2 = 0; ++ u32 an_state3 = 0; ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ #ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE(); ++ ++ if (hemac->PreLinkStatus == 1) ++ { ++ MHal_EMAC_Reset_EEE(); ++ } ++ #endif ++ ++ hemac->PreLinkStatus = 0; ++ ++ return -1; //no link // ++ } ++ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ //EMAC_DBG("==> AutoNegotiation still in progress\n"); ++ return -2; ++ } ++ ++ /* Get Link partner and advertisement from the PHY not from the MAC */ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_ADVERTISE, &adv); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, MII_LPA, &lpa); ++ ++ /* For Link Parterner adopts force mode and EPHY used, ++ * EPHY LPA reveals all zero value. ++ * EPHY would be forced to Full-Duplex mode. ++ */ ++ if (!lpa) ++ { ++ /* 100Mbps Full-Duplex */ ++ if (bmcr & BMCR_SPEED100) ++ lpa |= LPA_100FULL; ++ else /* 10Mbps Full-Duplex */ ++ lpa |= LPA_10FULL; ++ } ++ ++ neg = adv & lpa; ++ ++ if (neg & LPA_100FULL) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_100HALF) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if (neg & LPA_10FULL) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_10HALF) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ EMAC_DBG("%s: No speed and mode found (LPA=0x%x, ADV=0x%x)\n", __FUNCTION__, lpa, adv); ++ } ++ ++ } ++ else ++ { ++ speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ // Update the MAC // ++ MHal_EMAC_update_speed_duplex(hemac->hal, speed,duplex); ++ ++#ifdef CONFIG_MSTAR_EEE ++ /*TX idle, enable EEE*/ ++ if((MDev_EMAC_IS_TX_IDLE()) && (speed == SPEED_100) && (duplex == DUPLEX_FULL)) ++ { ++ if (hemac->PreLinkStatus == 0) ++ { ++ MHal_EMAC_Enable_EEE(300); ++ } ++ else ++ { ++ MHal_EMAC_Enable_EEE(0); ++ } ++ } ++#endif ++ ++ hemac->PreLinkStatus = 1; ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ if (speed == SPEED_100) { ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x21, &hcd_link_st_ok); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x22, &an_100t_link_st); ++ if ( (!(hcd_link_st_ok & 0x100) && ((an_100t_link_st & 0x300) == 0x200))) { ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount1++; ++ EMAC_ERR("hcd_link_st_ok:0x%x, an_100t_link_st:0x%x\n", hcd_link_st_ok, an_100t_link_st); ++ if (phy_restart_cnt > 10) { ++ EMAC_DBG("MDev_EMAC_update_linkspeed: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ else if (((hcd_link_st_ok & 0x100) && !(an_100t_link_st & 0x300)) ) { ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount2++; ++ EMAC_ERR("hcd_link_st_ok:0x%x, an_100t_link_st:0x%x\n", hcd_link_st_ok, an_100t_link_st); ++ if (phy_restart_cnt > 10) { ++ EMAC_DBG("MDev_EMAC_update_linkspeed: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ ++ /* Monitor AN state*/ ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x2e, &an_state); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x2e, &an_state2); ++ MHal_EMAC_read_phy(hemac->hal, hemac->phyaddr, 0x2e, &an_state3); ++ if ((an_state != an_state2) || (an_state != an_state3)) ++ { ++ EMAC_ERR("an_state 1:0x%x, 2:0x%x, 3:0x%x\n", an_state, an_state2, an_state3); ++ return 0; ++ } ++ ++ if ((an_state & 0xf000) == 0x3000) ++ { ++ EMAC_ERR("an_state=0x%x\n", an_state); ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount3++; ++ if (phy_restart_cnt > 10){ ++ EMAC_DBG("PHY_AN_monitor_timer_callback: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ else if ((an_state & 0xf000) == 0x2000) ++ { ++ EMAC_ERR("an_state=0x%x\n", an_state); ++ phy_restart_cnt++; ++ hemac->gu32PhyResetCount4++; ++ if (phy_restart_cnt > 10){ ++ EMAC_DBG("PHY_AN_monitor_timer_callback: restart AN process\n"); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ hemac->gu32PhyResetCount++; ++ phy_restart_cnt = 0; ++ return 0; ++ } ++ } ++ // else{ ++ // phy_restart_cnt = 0; ++ // } ++ } ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++ return 0; ++} ++#endif ++ ++#if 0 ++static int MDev_EMAC_get_info(struct net_device *dev) ++{ ++ u32 bmsr, bmcr, LocPtrA; ++ u32 uRegStatus =0; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_NO_LINK; //no link // ++ } ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_AUTO_NEGOTIATION; //AutoNegotiation // ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_LINK_SUCCESS; //link success // ++ } ++ ++ MHal_EMAC_read_phy (hemac->hal, hemac->phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ uRegStatus |= ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ uRegStatus |= ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ else ++ { ++ if(bmcr & BMCR_SPEED100) ++ { ++ uRegStatus |= ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if(bmcr & BMCR_FULLDPLX) ++ { ++ uRegStatus |= ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ ++ return uRegStatus; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//Program the hardware MAC address from dev->dev_addr. ++//------------------------------------------------------------------------------------------------- ++void MDev_EMAC_update_mac_address (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 value; ++ value = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) |(dev->dev_addr[0]); ++ MHal_EMAC_Write_SA1L(hemac->hal, value); ++ value = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]); ++ MHal_EMAC_Write_SA1H(hemac->hal, value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// ADDRESS MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Set the ethernet MAC address in dev->dev_addr ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_get_mac_address (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_EMAC_get_SA1H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA1L_addr(hemac->hal); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_EMAC_get_SA2H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA2L_addr(hemac->hal); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++} ++ ++#ifdef URANUS_ETHER_ADDR_CONFIGURABLE ++//------------------------------------------------------------------------------------------------- ++// Store the new hardware address in dev->dev_addr, and update the MAC. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_set_mac_address (struct net_device *dev, void *addr) ++{ ++ struct sockaddr *address = addr; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (!is_valid_ether_addr (address->sa_data)) ++ return -EADDRNOTAVAIL; ++ spin_lock(&hemac->mutexPhy); ++ memcpy (dev->dev_addr, address->sa_data, dev->addr_len); ++ MDev_EMAC_update_mac_address (dev); ++ spin_unlock(&hemac->mutexPhy); ++ return 0; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Mstar Multicast hash rule ++//------------------------------------------------------------------------------------------------- ++//Hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] ++//Hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] ++//Hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] ++//Hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] ++//Hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] ++//Hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] ++//------------------------------------------------------------------------------------------------- ++ ++static void MDev_EMAC_sethashtable(struct net_device *dev, unsigned char *addr) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 mc_filter[2]; ++ u32 uHashIdxBit; ++ u32 uHashValue; ++ u32 i; ++ u32 tmpcrc; ++ u32 uSubIdx; ++ u64 macaddr; ++ u64 mac[6]; ++ ++ uHashValue = 0; ++ macaddr = 0; ++ ++ // Restore mac // ++ for(i = 0; i < 6; i++) ++ { ++ mac[i] =(u64)addr[i]; ++ } ++ ++ // Truncate mac to u64 container // ++ macaddr |= mac[0] | (mac[1] << 8) | (mac[2] << 16); ++ macaddr |= (mac[3] << 24) | (mac[4] << 32) | (mac[5] << 40); ++ ++ // Caculate the hash value // ++ for(uHashIdxBit = 0; uHashIdxBit < 6; uHashIdxBit++) ++ { ++ tmpcrc = (macaddr & (0x1UL << uHashIdxBit)) >> uHashIdxBit; ++ for(i = 1; i < 8; i++) ++ { ++ uSubIdx = uHashIdxBit + (i * 6); ++ tmpcrc = tmpcrc ^ ((macaddr >> uSubIdx) & 0x1); ++ } ++ uHashValue |= (tmpcrc << uHashIdxBit); ++ } ++ ++ mc_filter[0] = MHal_EMAC_ReadReg32(hemac->hal, REG_ETH_HSL); ++ mc_filter[1] = MHal_EMAC_ReadReg32(hemac->hal, REG_ETH_HSH); ++ ++ // Set the corrsponding bit according to the hash value // ++ if(uHashValue < 32) ++ { ++ mc_filter[0] |= (0x1UL << uHashValue); ++ MHal_EMAC_WritReg32(hemac->hal, REG_ETH_HSL, mc_filter[0] ); ++ } ++ else ++ { ++ mc_filter[1] |= (0x1UL << (uHashValue - 32)); ++ MHal_EMAC_WritReg32(hemac->hal, REG_ETH_HSH, mc_filter[1] ); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Enable/Disable promiscuous and multicast modes. ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_set_rx_mode (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ struct netdev_hw_addr *ha; ++ ++ uRegVal = MHal_EMAC_Read_CFG(hemac->hal); ++ ++ if (dev->flags & IFF_PROMISC) ++ { ++ // Enable promiscuous mode // ++ uRegVal |= EMAC_CAF; ++ } ++ else if (dev->flags & (~IFF_PROMISC)) ++ { ++ // Disable promiscuous mode // ++ uRegVal &= ~EMAC_CAF; ++ } ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++ ++ if (dev->flags & IFF_ALLMULTI) ++ { ++ // Enable all multicast mode // ++ MHal_EMAC_update_HSH(hemac->hal, -1,-1); ++ uRegVal |= EMAC_MTI; ++ } ++ else if (dev->flags & IFF_MULTICAST) ++ { ++ // Enable specific multicasts// ++ MHal_EMAC_update_HSH(hemac->hal, 0,0); ++ netdev_for_each_mc_addr(ha, dev) ++ { ++ MDev_EMAC_sethashtable(dev, ha->addr); ++ } ++ uRegVal |= EMAC_MTI; ++ } ++ else if (dev->flags & ~(IFF_ALLMULTI | IFF_MULTICAST)) ++ { ++ // Disable all multicast mode// ++ MHal_EMAC_update_HSH(hemac->hal, 0,0); ++ uRegVal &= ~EMAC_MTI; ++ } ++ ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++} ++//------------------------------------------------------------------------------------------------- ++// IOCTL ++//------------------------------------------------------------------------------------------------- ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable MDIO ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_mdio_read (struct net_device *dev, int phy_id, int location) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 value; ++ MHal_EMAC_read_phy (hemac->hal, phy_id, location, &value); ++ return value; ++} ++ ++static void MDev_EMAC_mdio_write (struct net_device *dev, int phy_id, int location, int value) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ MHal_EMAC_write_phy (hemac->hal, phy_id, location, value); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//ethtool support. ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static int MDev_EMAC_ethtool_ioctl (struct net_device *dev, void *useraddr) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 ethcmd; ++ int res = 0; ++ ++ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ switch (ethcmd) ++ { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ res = mii_ethtool_gset (&hemac->mii, &ecmd); ++ if (copy_to_user (useraddr, &ecmd, sizeof (ecmd))) ++ res = -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd ecmd; ++ if (copy_from_user (&ecmd, useraddr, sizeof (ecmd))) ++ res = -EFAULT; ++ else ++ res = mii_ethtool_sset (&hemac->mii, &ecmd); ++ break; ++ } ++ case ETHTOOL_NWAY_RST: ++ { ++ res = mii_nway_restart (&hemac->mii); ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ edata.data = mii_link_ok (&hemac->mii); ++ if (copy_to_user (useraddr, &edata, sizeof (edata))) ++ res = -EFAULT; ++ break; ++ } ++ default: ++ res = -EOPNOTSUPP; ++ } ++ return res; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// User-space ioctl interface. ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static int MDev_EMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ struct mii_ioctl_data *data = if_mii(rq); ++ u32 value; ++ if (!netif_running(dev)) ++ { ++ rq->ifr_metric = ETHERNET_TEST_INIT_FAIL; ++ } ++ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ data->phy_id = (hemac->phyaddr & 0x1FUL); ++ return 0; ++ ++ case SIOCDEVPRIVATE: ++ rq->ifr_metric = (MDev_EMAC_get_info(dev)|hemac->initstate); ++ return 0; ++/* ++ case SIOCDEVON: ++ MHal_EMAC_Power_On_Clk(); ++ return 0; ++ ++ case SIOCDEVOFF: ++ MHal_EMAC_Power_Off_Clk(); ++ return 0; ++*/ ++ case SIOCGMIIREG: ++ // check PHY's register 1. ++ if((data->reg_num & 0x1fUL) == 0x1UL) ++ { ++ // PHY's register 1 value is set by timer callback function. ++ spin_lock(&hemac->mutexPhy); ++ data->val_out = hemac->phy_status_register; ++ spin_unlock(&hemac->mutexPhy); ++ } ++ else ++ { ++ MHal_EMAC_read_phy(hemac->hal, (hemac->phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), (u32 *)&(value)); ++ data->val_out = value; ++ } ++ return 0; ++ ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ MHal_EMAC_write_phy(hemac->hal, (hemac->phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), data->val_in); ++ return 0; ++ ++ case SIOCETHTOOL: ++ return MDev_EMAC_ethtool_ioctl (dev, (void *) rq->ifr_data); ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++#else ++static int MDev_EMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(dev->phydev, rq, cmd); ++ default: ++ break; ++ } ++ return -EOPNOTSUPP; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// MAC ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and start the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_start (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ ++ // Enable Receive and Transmit // ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal |= (EMAC_RE | EMAC_TE); ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Open the ethernet interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_open (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 uRegVal; ++ // unsigned long flags; ++ ++#if MSTAR_EMAC_NAPI ++ napi_enable(&hemac->napi); ++#endif ++ ++ spin_lock(&hemac->mutexPhy); ++ if (!is_valid_ether_addr (dev->dev_addr)) ++ { ++ spin_unlock(&hemac->mutexPhy); ++ return -EADDRNOTAVAIL; ++ } ++ spin_unlock(&hemac->mutexPhy); ++ ++ //ato EMAC_SYS->PMC_PCER = 1 << EMAC_ID_EMAC; //Re-enable Peripheral clock // ++ //MHal_EMAC_Power_On_Clk(dev->dev); ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal |= EMAC_CSR; ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++ // Enable PHY interrupt // ++ MHal_EMAC_enable_phyirq(hemac->hal); ++ ++#ifdef CONFIG_SS_SWTOE ++ drv_swtoe_glue_en(hemac->cnx_id, 0xFFFFFFFF, 0); ++ hemac->gu32intrEnable = DRV_SWTOE_GLUE_RCOM; ++ #if !DYNAMIC_INT_TX ++ hemac->gu32intrEnable = DRV_SWTOE_GLUE_TCOM; ++ #endif ++ drv_swtoe_glue_en(hemac->cnx_id, hemac->gu32intrEnable, 1); ++#else // #ifdef CONFIG_SS_SWTOE ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ hemac->gu32intrEnable = EMAC_INT_RBNA|EMAC_INT_TUND|EMAC_INT_RTRY|EMAC_INT_ROVR|EMAC_INT_HRESP; ++#if !DYNAMIC_INT_TX ++ hemac->gu32intrEnable |= EMAC_INT_TCOM; ++#endif ++ hemac->gu32intrEnable |= EMAC_INT_RCOM; ++ MHal_EMAC_IntEnable(hemac->hal, hemac->gu32intrEnable, 1); ++#endif // #ifdef CONFIG_SS_SWTOE ++ hemac->ep_flag |= EP_FLAG_OPEND; ++ ++ MDev_EMAC_start(dev); ++ phy_start(dev->phydev); ++ netif_start_queue (dev); ++ ++ // init_timer( &hemac->timer_link ); ++ ++#if 0 ++ hemac->timer_link.data = (unsigned long)dev; ++ hemac->timer_link.function = MDev_EMAC_timer_LinkStatus; ++ ++ hemac->timer_link.expires = jiffies + EMAC_CHECK_LINK_TIME; ++ add_timer(&hemac->timer_link); ++#endif ++ ++#if 0 ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ // MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++ // MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1000UL); ++ //MHal_EMAC_write_phy(hemac->phyaddr, MII_BMCR, 0x1200UL); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); ++#else ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x9000UL); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1000UL); ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Close the interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_close (struct net_device *dev) ++{ ++ u32 uRegVal; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++#ifndef CONFIG_SS_SWTOE ++ unsigned long flags; ++#endif ++ ++#if MSTAR_EMAC_NAPI ++ napi_disable(&hemac->napi); ++#endif ++ ++ spin_lock(&hemac->mutexPhy); ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal &= ~(EMAC_TE | EMAC_RE); ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++ // Disable PHY interrupt // ++ MHal_EMAC_disable_phyirq(hemac->hal); ++ spin_unlock(&hemac->mutexPhy); ++ ++#ifdef CONFIG_SS_SWTOE ++ drv_swtoe_glue_en(hemac->cnx_id, 0xFFFFFFFF, 0); ++#else // #ifdef CONFIG_SS_SWTOE ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++#endif // #ifdef CONFIG_SS_SWTOE ++ netif_stop_queue (dev); ++ netif_carrier_off(dev); ++ phy_stop(dev->phydev); ++ // del_timer(&hemac->timer_link); ++ //MHal_EMAC_Power_Off_Clk(dev->dev); ++ // hemac->ThisBCE.connected = 0; ++ hemac->ep_flag &= (~EP_FLAG_OPEND); ++#ifndef CONFIG_SS_SWTOE ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update the current statistics from the internal statistics registers. ++//------------------------------------------------------------------------------------------------- ++static struct net_device_stats * MDev_EMAC_stats (struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ int ale, lenerr, seqe, lcol, ecol; ++ ++ // spin_lock_irq (hemac->lock); ++ ++ if (netif_running (dev)) ++ { ++ hemac->stats.rx_packets += MHal_EMAC_Read_OK(hemac->hal); /* Good frames received */ ++ ale = MHal_EMAC_Read_ALE(hemac->hal); ++ hemac->stats.rx_frame_errors += ale; /* Alignment errors */ ++ lenerr = MHal_EMAC_Read_ELR(hemac->hal); ++ hemac->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ ++ seqe = MHal_EMAC_Read_SEQE(hemac->hal); ++ hemac->stats.rx_crc_errors += seqe; /* CRC error */ ++ hemac->stats.rx_fifo_errors += MHal_EMAC_Read_ROVR(hemac->hal); ++ hemac->stats.rx_errors += ale + lenerr + seqe + MHal_EMAC_Read_SE(hemac->hal) + MHal_EMAC_Read_RJB(hemac->hal); ++ hemac->stats.tx_packets += MHal_EMAC_Read_FRA(hemac->hal); /* Frames successfully transmitted */ ++ hemac->stats.tx_fifo_errors += MHal_EMAC_Read_TUE(hemac->hal); /* Transmit FIFO underruns */ ++ hemac->stats.tx_carrier_errors += MHal_EMAC_Read_CSE(hemac->hal); /* Carrier Sense errors */ ++ hemac->stats.tx_heartbeat_errors += MHal_EMAC_Read_SQEE(hemac->hal); /* Heartbeat error */ ++ lcol = MHal_EMAC_Read_LCOL(hemac->hal); ++ ecol = MHal_EMAC_Read_ECOL(hemac->hal); ++ hemac->stats.tx_window_errors += lcol; /* Late collisions */ ++ hemac->stats.tx_aborted_errors += ecol; /* 16 collisions */ ++ hemac->stats.collisions += MHal_EMAC_Read_SCOL(hemac->hal) + MHal_EMAC_Read_MCOL(hemac->hal) + lcol + ecol; ++ } ++ ++ // spin_unlock_irq (hemac->lock); ++ ++ return &hemac->stats; ++} ++ ++#ifndef CONFIG_SS_SWTOE ++static int MDev_EMAC_TxReset(struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 val = MHal_EMAC_Read_CTL(hemac->hal) & 0x000001FFUL; ++ ++ MHal_EMAC_Write_CTL(hemac->hal, (val & ~EMAC_TE)); ++ ++ val = MHal_EMAC_Read_CTL(hemac->hal) & 0x000001FFUL; ++ EMAC_ERR ("MAC0_CTL:0x%08x\n", val); ++ //MHal_EMAC_Write_TCR(0); ++ mdelay(1); ++ MHal_EMAC_Write_CTL(hemac->hal, (MHal_EMAC_Read_CTL(hemac->hal) | EMAC_TE)); ++ val = MHal_EMAC_Read_CTL(hemac->hal) & 0x000001FFUL; ++ EMAC_ERR ("MAC0_CTL:0x%08x\n", val); ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_MSTAR_EEE ++static int MDev_EMAC_IS_TX_IDLE(void) ++{ ++ u32 check; ++ u32 tsrval = 0; ++ ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++#ifdef TX_QUEUE_4 ++ for (check = 0; check < EMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_EMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval == 8) ++ return 1; ++ } ++#endif ++ ++ return 0; ++} ++#endif //CONFIG_MSTAR_EEE ++ ++ ++#if 0 ++void MDrv_EMAC_DumpMem(phys_addr_t addr, u32 len) ++{ ++ u8 *ptr = (u8 *)addr; ++ u32 i; ++ ++ printk("\n ===== Dump %lx =====\n", (long unsigned int)ptr); ++ for (i=0; ihal) & 0x000001FFUL; ++ ++ //Disable Rx ++ MHal_EMAC_Write_CTL(hemac->hal, (val & ~EMAC_RE)); // why RX ++ memcpy(&hemac->pu8PausePkt[6], dev->dev_addr, 6); ++ Chip_Flush_Cache_Range((size_t)hemac->pu8PausePkt, hemac->u8PausePktSize); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ hemac->isPausePkt = 1; ++ // skb_queue_insert(&(hemac->skb_queue_tx), NULL, VIRT2BUS(hemac->pu8PausePkt), hemac->u8PausePktSize, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ MHal_EMAC_Write_CTL(hemac->hal, (MHal_EMAC_Read_CTL(hemac->hal) | EMAC_RE)); // why RX ++} ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++//------------------------------------------------------------------------------------------------- ++//Patch for losing small-size packet when running SMARTBIT ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++static void MDev_EMAC_Period_Retry(struct sk_buff *skb, struct net_device* dev) ++{ ++ u32 xval; ++ u32 uRegVal; ++ ++ xval = MHal_EMAC_ReadReg32(hemac->hal,REG_ETH_CFG); ++ ++ if((skb->len <= PACKET_THRESHOLD) && !(xval & EMAC_SPD) && !(xval & EMAC_FD)) ++ { ++ txcount++; ++ } ++ else ++ { ++ txcount = 0; ++ } ++ ++ if(txcount > TXCOUNT_THRESHOLD) ++ { ++ uRegVal = MHal_EMAC_Read_CFG(hemac->hal); ++ uRegVal |= 0x00001000UL; ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++ } ++ else ++ { ++ uRegVal = MHal_EMAC_Read_CFG(hemac->hal); ++ uRegVal &= ~(0x00001000UL); ++ MHal_EMAC_Write_CFG(hemac->hal, uRegVal); ++ } ++} ++#endif ++ ++#ifndef CONFIG_SS_SWTOE ++#if 0 ++static int _MDev_EMAC_tx_free(struct emac_handle *hemac) ++{ ++ // int pkt_num = 0; ++ // int byte_num = 0; ++ int txUsedCnt; ++ int txUsedCntSW; ++ int i; ++ unsigned long flags; ++ int len; ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ txUsedCnt = MHal_EMAC_TXQ_Used(hemac->hal); ++ txUsedCntSW = skb_queue_used(&hemac->skb_queue_tx, 0); ++ if (txUsedCntSW < txUsedCnt) ++ { ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return 0; ++ } ++ for (i = txUsedCnt; i < txUsedCntSW; i++) ++ { ++ len = skb_queue_remove(&hemac->skb_queue_tx, NULL, NULL, 1, 0); ++ // if (len < 0) ++ // return 0; ++ hemac->stats.tx_bytes += len; ++ // pkt_num++; ++ // byte_num+= len; ++ tx_bytes_per_timer += len; ++ // skb_tx_free++; ++ } ++/* ++ if (pkt_num) ++ { ++ // netdev_completed_queue(dev, pkt_num, byte_num); ++ } ++*/ ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return 1; ++} ++#else ++static int _MDev_EMAC_tx_pump(struct emac_handle *hemac, int bFree, int bPump) ++{ ++ int txUsedCnt; ++ int txUsedCntSW; ++ int i; ++ unsigned long flags; ++ unsigned long flags1; ++ int len; ++ struct sk_buff* skb = NULL; ++ dma_addr_t skb_addr; ++ int nPkt; ++ int txFreeCnt; ++ int txPendCnt; ++ int ret = 0; ++ ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ if (bFree) ++ { ++ txUsedCnt = MHal_EMAC_TXQ_Used(hemac->hal); ++ txUsedCntSW = skb_queue_used(&hemac->skb_queue_tx, 0); ++ ret = txUsedCntSW - txUsedCnt; ++ for (i = txUsedCnt; i < txUsedCntSW; i++) ++ { ++ // MHal_EMAC_TXQ_Remove(); ++ len = skb_queue_remove(&hemac->skb_queue_tx, NULL, NULL, 1, 0); ++ spin_lock_irqsave(&hemac->emac_data_done_lock, flags1); ++ hemac->data_done += len; ++ spin_unlock_irqrestore(&hemac->emac_data_done_lock, flags1); ++ ++ hemac->stats.tx_bytes += len; ++ /// tx_bytes_per_timer += len; ++ } ++ } ++ ++ if (bPump) ++ { ++ int skb_len; ++ txFreeCnt = skb_queue_free(&hemac->skb_queue_tx, 0); ++ txPendCnt = skb_queue_used(&hemac->skb_queue_tx, 2); ++ nPkt = (txFreeCnt < txPendCnt) ? txFreeCnt : txPendCnt; ++ for (i = 0; i < nPkt; i++) ++ { ++ skb_queue_head_inc(&hemac->skb_queue_tx, &skb, &skb_addr, &skb_len, 0); ++ if (skb_addr) ++ { ++ MHal_EMAC_TXQ_Insert(hemac->hal, skb_addr, skb_len); ++ } ++ } ++ } ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ return ret; ++} ++#endif ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++#ifdef CONFIG_SS_SWTOE ++ ++static int MDev_EMAC_tx(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ int ret = NETDEV_TX_OK; ++ struct sk_buff* skb_tmp = NULL; ++ ++ ++ if (drv_swtoe_tx_avail(hemac->cnx_id, skb_shinfo(skb)->nr_frags + 1)) ++ { ++ ret = NETDEV_TX_BUSY; ++ return ret; ++ } ++ ++ if (!(skb_tmp = skb_clone(skb, GFP_ATOMIC))) ++ { ++ printk("[%s][%d] skb_clone fail\n", __FUNCTION__, __LINE__); ++ ret = NETDEV_TX_BUSY; ++ return ret; ++ } ++ dev_kfree_skb_any(skb); ++ skb = skb_tmp; ++ ++ if (0 == drv_swtoe_tx_send(hemac->cnx_id, (void*)skb, 0, 0, SWTOE_TX_SEND_SKB)) ++ { ++ printk("[%s][%d] drop TX packets since IPC fail\n", __FUNCTION__, __LINE__); ++ dev_kfree_skb_any(skb); ++ ret = NETDEV_TX_OK; ++ return ret; ++ } ++ drv_swtoe_tx_pump(hemac->cnx_id); ++ return NETDEV_TX_OK; ++} ++#else ++static int MDev_EMAC_tx(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ dma_addr_t skb_addr; ++ // int txIdleCount=0; ++ // int txIdleCntSW = 0; ++ unsigned long flags; ++ unsigned long flag1; ++ int ret = NETDEV_TX_OK; ++ ++ spin_lock_irqsave(&hemac->mutexNetIf, flag1); ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ ++#ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE_TX(); ++#endif ++ ++ if (netif_queue_stopped(dev)){ ++ EMAC_ERR("netif_queue_stopped\n"); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ if (!netif_carrier_ok(dev)){ ++ // EMAC_ERR("netif_carrier_off\n"); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ if (skb->len > EMAC_MTU) ++ { ++ // EMAC_ERR("Something wrong (mtu, tx_len) = (%d, %d)\n", dev->mtu, skb->len); ++ // ret = NETDEV_TX_BUSY; ++ dev_kfree_skb_any(skb); ++ dev->stats.tx_dropped++; ++ goto out_unlock; ++ } ++#if defined(PACKET_DUMP) ++ if(1==txDumpCtrl && NULL!=txDumpFile) ++ { ++ txDumpFileLength+=msys_kfile_write(txDumpFile,txDumpFileLength,skb->data,skb->len); ++ } ++ else if(2==txDumpCtrl && NULL!=txDumpFile) ++ { ++ msys_kfile_close(txDumpFile); ++ txDumpFile=NULL; ++ printk(KERN_WARNING"close emac tx_dump file '%s', len=0x%08X...\n",txDumpFileName,txDumpFileLength); ++ } ++#endif ++ //if buffer remains one space, notice upperr layer to block transmition. ++ // if (MHal_EMAC_TXQ_Full() || skb_queue_full(&(hemac->skb_queue_tx))) ++ // if (MHal_EMAC_TXQ_Full()) ++ if (skb_queue_full(&hemac->skb_queue_tx, 1)) ++ { ++ netif_stop_queue(dev); ++#if DYNAMIC_INT_TX ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 1); ++#endif ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ ++#if EMAC_FLOW_CONTROL_RX ++ if (hemac->isPausePkt) ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), NULL, VIRT2BUS(hemac->pu8PausePkt), hemac->u8PausePktSize, 1); ++ hemac->isPausePkt = 0; ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++#if EMAC_SG ++ { ++ int i; ++ int nr_frags = skb_shinfo(skb)->nr_frags; ++ int len; ++ ++ // dma_unmap_single(NULL, VIRT2PA(start), EMAC_MTU, DMA_TO_DEVICE); ++ if (nr_frags) ++ { ++ char* start = kmalloc(EMAC_MTU, GFP_ATOMIC); ++ char* p = start; ++ ++ if (!start) ++ { ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ ++ memcpy(p, skb->data, skb_headlen(skb)); ++ p += skb_headlen(skb); ++ len = skb_headlen(skb); ++ for (i = 0; i < nr_frags; i++) ++ { ++ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; ++#if EMAC_SG_BDMA ++ { ++ MSYS_DMA_COPY stDmaCopyCfg; ++ ++ Chip_Flush_Cache_Range((size_t)skb_frag_address(frag), skb_frag_size(frag)); ++ stDmaCopyCfg.phyaddr_src = (unsigned long long)VIRT2BUS(skb_frag_address(frag)); ++ stDmaCopyCfg.phyaddr_dst = (unsigned long long)VIRT2BUS(p); ++ stDmaCopyCfg.length = skb_frag_size(frag); ++ xx_msys_dma_copy(&stDmaCopyCfg); ++ } ++#else ++ memcpy(p, skb_frag_address(frag), skb_frag_size(frag)); ++#endif ++ p += skb_frag_size(frag); ++ len += skb_frag_size(frag); ++ } ++/* ++ if (len != skb->len) ++ printk("[%s][%d] strange ??? (len, skb->len) = (%d, %d)\n", __FUNCTION__, __LINE__, len, skb->len); ++*/ ++ if (EMAC_SG_BUF_CACHE) ++ Chip_Flush_Cache_Range((size_t)start, skb->len); ++ skb_addr = VIRT2BUS(start); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), (struct sk_buff*)0xFFFFFFFF, (dma_addr_t)skb_addr, skb->len, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ dev_kfree_skb_any(skb); ++ } ++ else ++ { ++ { ++ struct sk_buff* skb_tmp = skb_clone(skb, GFP_ATOMIC); ++ if (!skb_tmp) ++ { ++ printk("[%s][%d] skb_clone fail\n", __FUNCTION__, __LINE__); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ dev_kfree_skb_any(skb); ++ skb = skb_tmp; ++ } ++ skb_addr = VIRT2BUS(skb->data); ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), skb, skb_addr, skb->len, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ Chip_Flush_Cache_Range((size_t)skb->data, skb->len); ++ } ++ if (nr_frags >= hemac->maxSG) ++ hemac->maxSG = nr_frags + 1; ++ } ++#else // #if #if EMAC_SG ++ ++ if (DYNAMIC_INT_TX) ++ { ++ struct sk_buff* skb_tmp = skb_clone(skb, GFP_ATOMIC); ++ if (!skb_tmp) ++ { ++ printk("[%s][%d] skb_clone fail\n", __FUNCTION__, __LINE__); ++ ret = NETDEV_TX_BUSY; ++ goto out_unlock; ++ } ++ dev_kfree_skb_any(skb); ++ // kfree_skb(skb); ++ skb = skb_tmp; ++ } ++ skb_addr = VIRT2BUS(skb->data); ++ if (unlikely(0 == skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ // kfree_skb(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ goto out_unlock; ++ } ++ spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ skb_queue_insert(&(hemac->skb_queue_tx), skb, skb_addr, skb->len, 1); ++ spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ ++ //set DMA address and trigger DMA ++ Chip_Flush_Cache_Range((size_t)skb->data, skb->len); ++#endif // #if #if EMAC_SG ++ ++ // txIdleCount = skb_queue_free(&hemac->skb_queue_tx, 0); ++ // if(min_tx_fifo_idle_count>txIdleCount) min_tx_fifo_idle_count=txIdleCount; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ netif_trans_update(dev); ++#else ++ dev->trans_start = jiffies; ++#endif ++out_unlock: ++ { ++/* ++ int bSkbFree = ((hemac->skb_tx_send & 0x0f) == 0) ? 1 : 0; ++ _MDev_EMAC_tx_pump(hemac, bSkbFree, 1); ++*/ ++ _MDev_EMAC_tx_pump(hemac, 1, 1); ++ } ++ ++/* ++#if DYNAMIC_INT_TX ++ // if ((hemac->skb_tx_send - hemac->skb_tx_free) > 32) ++ // if ((hemac->skb_tx_send & 0x0f) == 0) ++ // if ((hemac->skb_tx_send - hemac->skb_tx_free) >= DYNAMIC_INT_TX_TH) ++ if ((hemac->skb_tx_send - hemac->skb_tx_free) >= 64) ++ { ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 1); ++ } ++#endif ++*/ ++ spin_unlock_irqrestore(&hemac->mutexNetIf, flag1); ++ return ret; ++} ++#endif // #ifdef CONFIG_SS_SWTOE ++ ++#if 0 //ajtest ++static int ajtest_recv_count=0; ++static ssize_t ajtest_recv_count_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ int val = simple_strtoul(buf, NULL, 10); ++ if(0==val) ++ { ++ ++ ajtest_recv_count=0; ++ } ++ return count; ++} ++static ssize_t ajtest_recv_count_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", ajtest_recv_count); ++} ++DEVICE_ATTR(ajtest_recv_count, 0644, ajtest_recv_count_show, ajtest_recv_count_store); ++ ++ ++unsigned int aj_checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++ ++static int aj_check(char *pData, int pktlen, int flag) ++{ ++ int res=0; ++ if(pktlen>32) ++ { ++ char *dbuf=(pData+0x36); ++ ++ if(0x51==dbuf[0] && 0x58==dbuf[1] && 0x91==dbuf[2] && 0x58==dbuf[3]) ++ { ++ int dlen=0; ++ int pktid=0; ++ int pktcs=0;//((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ int cs=0; ++ unsigned char *buf=(unsigned char *)(dbuf+8); ++ ++ dlen=(dbuf[7]<<24) + (dbuf[6]<<16)+(dbuf[5]<<8) + (dbuf[4]); ++ pktid=(dbuf[11]<<24) + (dbuf[10]<<16)+(dbuf[9]<<8) + (dbuf[8]); ++ ++// printf("pktCount: %08d\n",pktCount); ++ pktcs=((buf[dlen-1])<<24) + (buf[dlen-2]<<16)+(buf[dlen-3]<<8) + (buf[dlen-4]); ++ cs=aj_checksum(buf,dlen-4); ++ if(pktcs!=cs) ++ { ++// int j=0; ++// unsigned int lc=0; ++ printk(KERN_WARNING"<[!! AJ_ERR %d, %d: 0x%08X, 0x%08X, %d ]>\n\n",ajtest_recv_count,pktid,cs,pktcs,flag); ++ res=-1; ++// for(j=0;j\n",ajss_recv_count,pktid,cs,pktcs,flag); ++// } ++ ++ ajtest_recv_count++; ++ } ++ } ++ return res; ++} ++#endif ++ ++#ifdef CONFIG_SS_SWTOE ++// do someting replace rx function ++// static int MDev_EMAC_rx(struct net_device *dev, int budget) ++#else ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Disable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_rx(struct net_device *dev, int budget) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 received=0; ++ struct sk_buff *skb; ++ struct sk_buff *clean_skb; ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ // unsigned long flags; ++ ++ if (0 == budget) ++ return 0; ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ ++ // spin_lock_irqsave(&hemac->mutexRXD, flags); ++ // If any Ownership bit is 1, frame received. ++ do ++ { ++ char* pData; ++ struct rbf_t* desc = &(rxinfo->desc[rxinfo->idx]); ++ ++ // if(!((dlist->descriptors[hemac->rxBuffIndex].addr) & EMAC_DESC_DONE)) ++ if (!(desc->addr & EMAC_DESC_DONE)) ++ { ++ break; ++ } ++ // p_recv = (char *) ((((dlist->descriptors[hemac->rxBuffIndex].addr) & 0xFFFFFFFFUL) + RAM_VA_PA_OFFSET + MIU0_BUS_BASE) &~(EMAC_DESC_DONE | EMAC_DESC_WRAP)); ++ ++ p_recv = BUS2VIRT(CLR_BITS(desc->addr, EMAC_DESC_DONE | EMAC_DESC_WRAP)); ++ pktlen = desc->size & 0x7ffUL; /* Length of frame including FCS */ ++ ++ #if RX_THROUGHPUT_TEST ++ receive_bytes += pktlen; ++ #endif ++ ++ if (unlikely(((pktlen > EMAC_MTU) || (pktlen < 64)))) ++ { ++ EMAC_ERR("drop packet!!(pktlen = %d)", pktlen); ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ Chip_Flush_MIU_Pipe(); ++ rxinfo->idx++; ++ if (rxinfo->idx >= rxinfo->num_desc) ++ rxinfo->idx = 0; ++ hemac->stats.rx_length_errors++; ++ hemac->stats.rx_errors++; ++ hemac->stats.rx_dropped++; ++ continue; ++ } ++ ++ if (unlikely(!(clean_skb = alloc_skb (EMAC_PACKET_SIZE_MAX, GFP_ATOMIC)))) ++ { ++ // printk(KERN_ERR"Can't alloc skb.[%s]%d\n",__FUNCTION__,__LINE__);; ++ goto jmp_rx_exit; ++ // return -ENOMEM; ++ } ++ skb = rxinfo->skb_arr[rxinfo->idx]; ++ #if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ dma_unmap_single(NULL, VIRT2PA(p_recv), pktlen, DMA_FROM_DEVICE); ++ memcpy(skb->data, p_recv, pktlen); ++ pktlen -= 4; /* Remove FCS */ ++ pData = skb_put(skb, pktlen); ++ } ++ else ++ #endif ++ { ++ pktlen -= 4; /* Remove FCS */ ++ pData = skb_put(skb, pktlen); ++ dma_unmap_single(NULL, VIRT2PA(pData), pktlen, DMA_FROM_DEVICE); ++ } ++ ++ //ajtest ++ /* below code is used to find the offset of ajtest header in incoming packet ++ for(cidx=0;cidx=pktlen) ++ { ++ break; ++ } ++ if(0x51==pData[cidx] && 0x58==pData[cidx+1] && 0x91==pData[cidx+2] && 0x58==pData[cidx+3]) ++ { ++ printk(KERN_WARNING"cidx: 0x%08X\n",cidx); ++ break; ++ } ++ } ++ */ ++#if defined(PACKET_DUMP) ++ if(1==rxDumpCtrl && NULL!=rxDumpFile) ++ { ++ rxDumpFileLength+=msys_kfile_write(rxDumpFile,rxDumpFileLength,pData,pktlen); ++ } ++ else if(2==rxDumpCtrl && NULL!=rxDumpFile) ++ { ++ msys_kfile_close(rxDumpFile); ++ rxDumpFile=NULL; ++ printk(KERN_WARNING"close emac rx_dump file '%s', len=0x%08X...\n",rxDumpFileName,rxDumpFileLength); ++ } ++#endif ++ ++ skb->dev = dev; ++ skb->protocol = eth_type_trans (skb, dev); ++ //skb->len = pktlen; ++ dev->last_rx = jiffies; ++ hemac->stats.rx_bytes += pktlen; ++#if EMAC_FLOW_CONTROL_TX ++ if (0 == MHal_EMAC_FlowControl_TX(hemac)) ++ { ++ _MDrv_EMAC_Pause_TX(dev, skb, p_recv); ++ } ++#endif // #if EMAC_FLOW_CONTROL_TX ++ #if RX_THROUGHPUT_TEST ++ kfree_skb(skb); ++ #else ++ ++ #if RX_CHECKSUM ++ if (((desc->size & EMAC_DESC_TCP) || (desc->size & EMAC_DESC_UDP)) && ++ (desc->size & EMAC_DESC_IP_CSUM) && ++ (desc->size & EMAC_DESC_TCP_UDP_CSUM)) ++ { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ skb->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ #ifdef ISR_BOTTOM_HALF ++ netif_rx_ni(skb); ++ #elif MSTAR_EMAC_NAPI ++ #if (EMAC_GSO) ++ napi_gro_receive(&hemac->napi, skb); ++ #else ++ netif_receive_skb(skb); ++ #endif ++ #else ++ netif_rx (skb); ++ #endif ++ ++ received++; ++ #endif/*RX_THROUGHPUT_TEST*/ ++ ++ // if (dlist->descriptors[hemac->rxBuffIndex].size & EMAC_MULTICAST) ++ if (desc->size & EMAC_MULTICAST) ++ { ++ hemac->stats.multicast++; ++ } ++ ++ //fill clean_skb into RX descriptor ++ rxinfo->skb_arr[rxinfo->idx] = clean_skb; ++ ++#if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ if (rxinfo->idx == (rxinfo->num_desc-1)) ++ desc->addr = VIRT2BUS(p_recv) | EMAC_DESC_DONE | EMAC_DESC_WRAP; ++ else ++ desc->addr = VIRT2BUS(p_recv) | EMAC_DESC_DONE; ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ dma_map_single(NULL, p_recv, EMAC_PACKET_SIZE_MAX, DMA_FROM_DEVICE); ++ } ++ else ++#endif ++ { ++ if (rxinfo->idx == (rxinfo->num_desc-1)) ++ desc->addr = VIRT2BUS(clean_skb->data) | EMAC_DESC_DONE | EMAC_DESC_WRAP; ++ else ++ desc->addr = VIRT2BUS(clean_skb->data) | EMAC_DESC_DONE; ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ dma_map_single(NULL, clean_skb->data, EMAC_PACKET_SIZE_MAX, DMA_FROM_DEVICE); ++ } ++ Chip_Flush_MIU_Pipe(); ++ ++ rxinfo->idx++; ++ if (rxinfo->idx >= rxinfo->num_desc) ++ rxinfo->idx = 0; ++ ++#if MSTAR_EMAC_NAPI ++ // if(received >= EMAC_NAPI_WEIGHT) { ++ if(received >= budget) { ++ break; ++ } ++#endif ++ ++ } while(1); ++ ++jmp_rx_exit: ++ // spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++ if(received>max_rx_packet_count)max_rx_packet_count=received; ++ rx_packet_cnt += received; ++ return received; ++} ++#endif // #ifdef CONFIG_SS_SWTOE ++ ++//------------------------------------------------------------------------------------------------- ++//MAC interrupt handler ++//(Interrupt delay enable) ++//------------------------------------------------------------------------------------------------- ++#define dbg_buf_size 8192 ++void dump_hex(char* pBuf_in, int len_in) ++{ ++ int i; ++ static char sBuf[dbg_buf_size]; ++ char* p = sBuf; ++ char* end = &sBuf[dbg_buf_size]; ++ int len; ++ char* pBuf = pBuf_in; ++ ++ while (len_in) ++ { ++ len = min_t(int, 256, len_in); ++ p = sBuf; ++ end = &sBuf[dbg_buf_size]; ++ for (i = 0; i < len; i++) ++ { ++ p += scnprintf(p, end - p, "%02x ", pBuf[i]); ++ if ((i & 0xF) == 0xF) ++ p += scnprintf(p, end - p, "\n"); ++ } ++ if ((len) && (*(p-1) != '\n')) ++ p += scnprintf(p, end - p, "\n"); ++ if (len) ++ printk("%s", sBuf); ++ len_in -= len; ++ pBuf += len; ++ } ++} ++ ++#ifdef CONFIG_SS_SWTOE ++ ++ ++static void rx_work_func(struct work_struct* work) ++{ ++ struct emac_handle *hemac = container_of(work, struct emac_handle, rx_work); ++ drv_swtoe_rx_data* p_rx_data; ++ struct sk_buff *skb = NULL; ++ ++ while (0 == drv_swtoe_rx_data_get(hemac->cnx_id, NULL, &p_rx_data)) ++ { ++ if (NULL == (skb = build_skb(p_rx_data->buf, 0))) ++ { ++ printk("[%s][%d] build_skb fail\n", __FUNCTION__, __LINE__); ++ goto next; ++ } ++ skb_reserve(skb, (int)(p_rx_data->data - p_rx_data->buf)); ++ // data_size -= 4; /* Remove FCS */ ++ skb_put(skb, p_rx_data->data_size); ++ skb->dev = hemac->netdev; ++ skb->protocol = eth_type_trans (skb, hemac->netdev); ++ hemac->netdev->last_rx = jiffies; ++ hemac->stats.rx_bytes += p_rx_data->data_size; ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ netif_receive_skb(skb); ++next: ++ drv_swtoe_rx_data_free(hemac->cnx_id, p_rx_data, 0); ++ } ++} ++ ++ ++static int _mdrv_emac_swtoe_cb(int cnx_id, int reason, void* reason_data, void* cb_data) ++{ ++ struct emac_handle *hemac = (struct emac_handle*)cb_data; ++ ++ if (hemac->cnx_id != cnx_id) ++ { ++ printk("[%s][%d] mismatch cnx_id (expect, coming) = (%d, %d)\n", __FUNCTION__, __LINE__, hemac->cnx_id, cnx_id); ++ return -1; ++ } ++ switch (reason) ++ { ++ case DRV_SWTOE_GLUE_RCOM: ++ schedule_work(&hemac->rx_work); ++ break; ++ default: ++ printk("[%s][%d] unknown reason %d\n", __FUNCTION__, __LINE__, reason); ++ break; ++ } ++ return 0; ++} ++#else ++static int RBNA_detailed=0; ++ ++static u32 _MDrv_EMAC_ISR_RBNA(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = NULL; ++ int empty=0; ++ int idx; ++ rx_desc_queue_t* rxinfo; ++ ++ if (0 == (intstatus & EMAC_INT_RBNA)) ++ return 0; ++ ++ hemac = (struct emac_handle*) netdev_priv(dev); ++ rxinfo = &(hemac->rx_desc_queue); ++ ++ hemac->stats.rx_missed_errors++; ++ ++ //write 1 clear ++ MHal_EMAC_Write_RSR(hemac->hal, EMAC_BNA); ++ if(RBNA_detailed>0) ++ { ++ // u32 u32RBQP_Addr = MHal_EMAC_Read_RBQP(hemac->hal)- VIRT2BUS(rxinfo->desc); ++ for(idx=0;idxnum_desc;idx++) ++ { ++ // if(!((dlist->descriptors[idx].addr) & EMAC_DESC_DONE)) ++ if (!(rxinfo->desc[idx].addr & EMAC_DESC_DONE)) ++ { ++ empty++; ++ } ++ else ++ { ++ printk(KERN_ERR"RBNA: [0x%X]\n",idx); ++ } ++ ++ } ++ // printk(KERN_ERR"RBNA: empty=0x%X, rxBuffIndex=0x%X, rx_missed_errors=%ld RBQP_offset=0x%x\n",empty, rxinfo->idx, hemac->stats.rx_missed_errors,u32RBQP_Addr); ++ } ++#if 0 ++ if (1) ++ { ++ struct rbf_t* desc = NULL; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexRXD, flags); ++ for (idx=0;idxnum_desc;idx++) ++ { ++ desc = &(rxinfo->desc[idx]); ++ if (idx == (rxinfo->num_desc-1)) ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE) | EMAC_DESC_WRAP; ++ else ++ desc->addr = CLR_BITS(desc->addr, EMAC_DESC_DONE); ++ desc->size = 0; ++ } ++ spin_unlock_irqrestore(&hemac->mutexRXD, flags); ++ Chip_Flush_MIU_Pipe(); ++ } ++#endif ++ ++ hemac->irq_count[IDX_CNT_INT_RBNA]++; ++ //printk("RBNA\n"); ++#if REDUCE_CPU_FOR_RBNA ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexIntRX, flags); ++ if (0 == timer_pending(&hemac->timerIntRX)) ++ { ++ MHal_EMAC_RX_ParamSet(hemac->hal, 0xff, 0xff); ++ hemac->timerIntRX.expires = jiffies + HZ; ++ add_timer(&hemac->timerIntRX); ++ } ++ spin_unlock_irqrestore(&hemac->mutexIntRX, flags); ++ } ++#endif // #if REDUCE_CPU_FOR_RBNA ++ // gu32GatingRxIrqTimes = 1; ++ return 1; ++} ++ ++static u32 _MDrv_EMAC_ISR_TCOM(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = NULL; ++ ++ if (0 == (intstatus & EMAC_INT_TCOM)) ++ return 0; ++ ++ hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_High(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ hemac->tx_irqcnt++; ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (EMAC_INT_TUND | EMAC_INT_RTRY)) ++ { ++ hemac->stats.tx_errors += 1; ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ // MHal_EMAC_Write_TSR(EMAC_UND); ++ ++ //Reset TX engine ++ MDev_EMAC_TxReset(dev); ++ EMAC_ERR ("Transmit TUND error, TX reset\n"); ++ hemac->irq_count[IDX_CNT_INT_TUND]++; ++ } ++ hemac->irq_count[IDX_CNT_INT_RTRY]++; ++ } ++ ++ #if TX_THROUGHPUT_TEST ++ MDev_EMAC_tx(pseudo_packet, dev); ++ #endif ++ ++#if 0 ++ // _MDev_EMAC_tx_free(hemac); ++ _MDev_EMAC_tx_pump(hemac, 1, 0); ++ ++ // if (netif_queue_stopped (dev) && skb_queue_free(&hemac->skb_queue_tx, 1)) // ?? ++ if (netif_queue_stopped (dev) && skb_queue_free(&hemac->skb_queue_tx, 0)) // 35% ++ // if (netif_queue_stopped (dev) && (skb_queue_free(&hemac->skb_queue_tx, 0)> 80)) // 27.5% ++ // if (netif_queue_stopped (dev) && (skb_queue_free(&hemac->skb_queue_tx, 0) > (skb_queue_size(&hemac->skb_queue_tx, 0) >> 1))) // 29.7% ++ // if (((skb_queue_size(&hemac->skb_queue_tx, 1)>>1) < skb_queue_free(&hemac->skb_queue_tx, 1)) && netif_queue_stopped (dev)) // 45% ++ // if (netif_queue_stopped (dev) && (skb_queue_free(&hemac->skb_queue_tx, 0) > (skb_queue_size(&hemac->skb_queue_tx, 0)/3))) // 28.3% ++ { ++#if DYNAMIC_INT_TX ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 0); ++#endif ++#if EMAC_FLOW_CONTROL_TX ++ // if (0 == hemac->isPauseTX) ++ if (0 == timer_pending(&hemac->timerFlowTX)) ++ netif_wake_queue(dev); ++#else // #if EMAC_FLOW_CONTROL_TX ++ netif_wake_queue(dev); ++#endif ++ } ++#endif ++ hemac->irq_count[IDX_CNT_INT_TCOM]++; ++ return 1; ++} ++ ++static u32 _MDrv_EMAC_ISR_DONE(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle* hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (0 == (intstatus&EMAC_INT_DONE)) ++ return 0; ++ hemac->irq_count[IDX_CNT_INT_DONE]++; ++ return 1; ++} ++ ++static u32 _MDrv_EMAC_ISR_ROVR(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++#if EMAC_FLOW_CONTROL_RX ++#if EMAC_FLOW_CONTROL_RX_TEST ++ { ++ static int cnt = 0; ++ cnt++; ++ ++ if (0 == (cnt & 0xF)) ++ _MDrv_EMAC_PausePkt_Send(dev); ++ return 0; ++ } ++#endif ++#endif ++ ++ if (0 == (intstatus & EMAC_INT_ROVR)) ++ { ++ hemac->contiROVR = 0; ++ return 0; ++ } ++ ++ hemac->stats.rx_over_errors++; ++ hemac->contiROVR++; ++ //write 1 clear ++ MHal_EMAC_Write_RSR(hemac->hal, EMAC_RSROVR); ++#if EMAC_FLOW_CONTROL_RX ++ if (hemac->contiROVR < 3) ++ { ++ _MDrv_EMAC_PausePkt_Send(dev); ++ } ++ else ++ { ++ MDev_EMAC_SwReset(dev); ++ } ++#endif ++ hemac->irq_count[IDX_CNT_INT_ROVR]++; ++ return 0; ++} ++ ++static u32 _MDrv_EMAC_ISR_RCOM(struct net_device *dev, u32 intstatus) ++{ ++ struct emac_handle *hemac = NULL; ++ ++ hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (intstatus & EMAC_INT_RCOM_DELAY) ++ { ++ hemac->irq_count[IDX_CNT_JULIAN_D]++; ++ } ++ else if (intstatus & EMAC_INT_RCOM) ++ { ++ intstatus |= EMAC_INT_RCOM_DELAY; ++ hemac->irq_count[IDX_CNT_INT_RCOM]++; ++ } ++ ++ // Receive complete // ++ if (intstatus & EMAC_INT_RCOM_DELAY) ++ { ++ if ((0 == rx_time_last.tv_sec) && (0 == rx_time_last.tv_nsec)) ++ { ++ getnstimeofday(&rx_time_last); ++ } ++ else ++ { ++ struct timespec ct; ++ int duration; ++ ++ getnstimeofday(&ct); ++ duration = (ct.tv_sec - rx_time_last.tv_sec)*1000 + (ct.tv_nsec - rx_time_last.tv_nsec)/1000000; ++ rx_duration_max = (rx_duration_max < duration) ? duration : rx_duration_max; ++ rx_time_last = ct; ++ } ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ if(hemac->led_count++ > hemac->led_flick_speed){ ++ MDrv_GPIO_Set_High(hemac->led_orange); ++ hemac->led_count=0; ++ } ++ } ++ #if MSTAR_EMAC_NAPI ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ if (napi_schedule_prep(&hemac->napi)) ++ { ++ // MDEV_EMAC_DISABLE_RX_REG(); ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_RCOM, 0); ++ __napi_schedule(&hemac->napi); ++ } ++ else ++ { ++ // printk("[%s][%d] NAPI RX cannot be scheduled\n", __FUNCTION__, __LINE__); ++ } ++ #else ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexRXInt, flags); ++ MDev_EMAC_rx(dev, 0x0FFFFFFF); ++ spin_unlock_irqrestore(&hemac->mutexRXInt, flags); ++ } ++ #endif ++ } ++ return intstatus; ++} ++ ++irqreturn_t MDev_EMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 intstatus=0; ++ ++ hemac->irqcnt++; ++ hemac->oldTime = getCurMs(); ++ _MDev_EMAC_tx_pump(hemac, 1, 0); ++ while ((intstatus = MHal_EMAC_IntStatus(hemac->hal))) ++ { ++ _MDrv_EMAC_ISR_RBNA(dev, intstatus); ++ _MDrv_EMAC_ISR_TCOM(dev, intstatus); ++ _MDrv_EMAC_ISR_DONE(dev, intstatus); ++ _MDrv_EMAC_ISR_ROVR(dev, intstatus); ++ _MDrv_EMAC_ISR_RCOM(dev, intstatus); ++ } ++ ++ if (netif_queue_stopped (dev) && skb_queue_free(&hemac->skb_queue_tx, 0)) ++ { ++#if DYNAMIC_INT_TX ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_TCOM, 0); ++#endif ++#if EMAC_FLOW_CONTROL_TX ++ if (0 == timer_pending(&hemac->timerFlowTX)) ++ netif_wake_queue(dev); ++#else // #if EMAC_FLOW_CONTROL_TX ++ netif_wake_queue(dev); ++#endif ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++#ifndef CONFIG_SS_SWTOE ++#if DYNAMIC_INT_RX ++#define emac_time_elapse(start) \ ++({ \ ++ unsigned long delta; \ ++ struct timespec ct; \ ++ getnstimeofday(&ct); \ ++ delta = (ct.tv_sec - (start).tv_sec)*1000 + (ct.tv_nsec - (start).tv_nsec)/1000000; \ ++ (delta); \ ++}) ++#endif // #if DYNAMIC_INT_RX ++ ++#if MSTAR_EMAC_NAPI ++static int MDev_EMAC_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct emac_handle *hemac = container_of(napi, struct emac_handle,napi); ++ struct net_device *dev = hemac->netdev; ++ int work_done = 0; ++ int budget_rmn = budget; ++#if DYNAMIC_INT_RX ++ unsigned long elapse = 0; ++ unsigned long packets = 0; ++#endif // #if DYNAMIC_INT_RX ++ ++// rx_poll_again: ++ work_done = MDev_EMAC_rx(dev, budget_rmn); ++ ++ if (work_done) ++ { ++ // budget_rmn -= work_done; ++ // goto rx_poll_again; ++ } ++#if DYNAMIC_INT_RX ++ if (hemac->rx_stats_enable) ++ { ++ if (0xFFFFFFFF == hemac->rx_stats_packet) ++ { ++ getnstimeofday(&hemac->rx_stats_time); ++ hemac->rx_stats_packet = 0; ++ } ++ hemac->rx_stats_packet += work_done; ++ if ((elapse = emac_time_elapse(hemac->rx_stats_time))>= 1000) ++ { ++ packets = hemac->rx_stats_packet; ++ packets *= 1000; ++ packets /= elapse; ++ ++#if REDUCE_CPU_FOR_RBNA ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&hemac->mutexIntRX, flags); ++ if (0 == timer_pending(&hemac->timerIntRX)) ++ { ++#endif // #if REDUCE_CPU_FOR_RBNA ++ // printk("[%s][%d] packet for delay number (elapse, current, packet) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, (int)elapse, (int)hemac->rx_stats_packet, (int)packets); ++ // MHal_EMAC_RX_ParamSet(hemac->hal, packets/200 + 2, 0xFFFFFFFF); ++ MHal_EMAC_RX_ParamSet(hemac->hal, packets/200 + 1, 0xFFFFFFFF); ++#if REDUCE_CPU_FOR_RBNA ++ } ++ spin_unlock_irqrestore(&hemac->mutexIntRX, flags); ++ } ++#endif // #if REDUCE_CPU_FOR_RBNA ++ hemac->rx_stats_packet = 0; ++ getnstimeofday(&hemac->rx_stats_time); ++ } ++ } ++#endif ++ ++/* ++ if (work_done == budget_rmn) ++ return budget; ++*/ ++ ++ napi_gro_flush(napi, false); ++ ++#if 1 ++ /* If budget not fully consumed, exit the polling mode */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_RCOM, 1); ++ } ++ return work_done; ++#else ++ napi_complete(napi); ++ MHal_EMAC_IntEnable(hemac->hal, EMAC_INT_RCOM, 1); ++ return budget + work_done - budget_rmn; ++#endif ++} ++#endif ++ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++irqreturn_t MDev_EMAC_interrupt_cable_unplug(int irq,void *dev_instance) ++{ ++ struct net_device* dev = (struct net_device*)dev_instance; ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ ++ if (netif_carrier_ok(dev)) ++ netif_carrier_off(dev); ++ if (!netif_queue_stopped(dev)) ++ netif_stop_queue(dev); ++ hemac->ThisBCE.connected = 0; ++ ++#ifndef CONFIG_SS_SWTOE ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++#endif ++ ++ if(hemac->led_orange!=-1 && hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Set_Low(hemac->led_orange); ++ MDrv_GPIO_Set_Low(hemac->led_green); ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++void MDev_EMAC_HW_init(struct net_device* dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle*) netdev_priv(dev); ++ u32 word_ETH_CTL = 0x00000000UL; ++ ++ // (20071026_CHARLES) Disable TX, RX and MDIO: (If RX still enabled, the RX buffer will be overwrited) ++ MHal_EMAC_Write_CTL(hemac->hal, word_ETH_CTL); ++ MHal_EMAC_Write_BUFF(hemac->hal, 0x00000000UL); ++ // Set MAC address ------------------------------------------------------ ++ MHal_EMAC_Write_SA1_MAC_Address(hemac->hal, hemac->sa[0][0], hemac->sa[0][1], hemac->sa[0][2], hemac->sa[0][3], hemac->sa[0][4], hemac->sa[0][5]); ++ MHal_EMAC_Write_SA2_MAC_Address(hemac->hal, hemac->sa[1][0], hemac->sa[1][1], hemac->sa[1][2], hemac->sa[1][3], hemac->sa[1][4], hemac->sa[1][5]); ++ MHal_EMAC_Write_SA3_MAC_Address(hemac->hal, hemac->sa[2][0], hemac->sa[2][1], hemac->sa[2][2], hemac->sa[2][3], hemac->sa[2][4], hemac->sa[2][5]); ++ MHal_EMAC_Write_SA4_MAC_Address(hemac->hal, hemac->sa[3][0], hemac->sa[3][1], hemac->sa[3][2], hemac->sa[3][3], hemac->sa[3][4], hemac->sa[3][5]); ++ ++#ifndef CONFIG_SS_SWTOE ++ // spin_lock_irqsave(&hemac->mutexRXD, flags); ++ { ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(dev); ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ u32 idxRBQP = 0; ++#if EXT_PHY_PATCH ++ char* p = hemac->pu8RXBuf; ++#endif ++ // Initialize Receive Buffer Descriptors ++ memset(rxinfo->desc, 0x00, rxinfo->size_desc_queue); ++ ++ for(idxRBQP = 0; idxRBQP < rxinfo->num_desc; idxRBQP++) ++ { ++ struct sk_buff *skb = NULL; ++ struct rbf_t* desc = &(rxinfo->desc[idxRBQP]); ++ ++ if (!(skb = alloc_skb (EMAC_PACKET_SIZE_MAX, GFP_ATOMIC))) { ++ // printk("%s %d: alloc skb failed!\n",__func__, __LINE__); ++ panic("can't alloc skb"); ++ } ++ rxinfo->skb_arr[idxRBQP] = skb; ++ #if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ if(idxRBQP < (rxinfo->num_desc- 1)) ++ desc->addr = VIRT2BUS(p); ++ else ++ desc->addr = VIRT2BUS(p) | EMAC_DESC_WRAP; ++ p += EMAC_PACKET_SIZE_MAX; ++ } ++ else ++ #endif ++ { ++ if(idxRBQP < (rxinfo->num_desc- 1)) ++ desc->addr = VIRT2BUS(skb->data); ++ else ++ desc->addr = VIRT2BUS(skb->data) | EMAC_DESC_WRAP; ++ } ++ } ++ Chip_Flush_MIU_Pipe(); ++ // Initialize "Receive Buffer Queue Pointer" ++ MHal_EMAC_Write_RBQP(hemac->hal, VIRT2BUS(rxinfo->desc)); ++ } ++#endif // #ifndef CONFIG_SS_SWTOE ++ MHal_EMAC_HW_init(hemac->hal); ++} ++ ++#ifndef CONFIG_SS_SWTOE ++static void* MDev_EMAC_RX_Desc_Init(struct emac_handle *hemac, void* p) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ rxinfo->num_desc = RX_DESC_NUM; ++ rxinfo->size_desc_queue = RX_DESC_QUEUE_SIZE; ++#if 0 ++ mem_info.length = rxinfo->size_desc_queue; ++ strcpy(mem_info.name, "EMAC_BUFF"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ panic("unable to locate DMEM for EMAC alloRAM!! %d\n", rxinfo->size_desc_queue); ++ } ++ // rxinfo->descPhys = (dma_addr_t)mem_info.phys; ++#endif ++ rxinfo->desc = (struct rbf_t*)p; ++ ++ // EMAC_DBG("alloRAM_VA_BASE=0x%zx alloRAM_PA_BASE=0x%zx\n alloRAM_SIZE=0x%zx\n", (size_t) rxinfo->desc,(size_t) rxinfo->descPhys,(size_t)rxinfo->size_desc_queue); ++ BUG_ON(!rxinfo->desc); ++ ++ rxinfo->idx = 0; ++ memset(rxinfo->desc, 0x00, rxinfo->size_desc_queue); ++ Chip_Flush_MIU_Pipe(); ++ ++ rxinfo->skb_arr = kzalloc(rxinfo->num_desc*sizeof(struct sk_buff*), GFP_KERNEL); ++ BUG_ON(!rxinfo->skb_arr); ++ ++ EMAC_DBG("RAM_VA_BASE=0x%08x\n", rxinfo->desc); ++ EMAC_DBG("RAM_PA_BASE=0x%08x\n", VIRT2PA(rxinfo->desc)); ++ EMAC_DBG("RAM_VA_PA_OFFSET=0x%08x\n", rxinfo->off_va_pa); ++ EMAC_DBG("RBQP_BASE=0x%08x size=0x%x\n", VIRT2BUS(rxinfo->desc), rxinfo->size_desc_queue); ++ return (void*)(((int)p)+RX_DESC_QUEUE_SIZE); ++} ++ ++static void MDev_EMAC_RX_Desc_Free(struct emac_handle *hemac) ++{ ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ if (rxinfo->skb_arr) ++ { ++ kfree(rxinfo->skb_arr); ++ rxinfo->skb_arr = NULL; ++ } ++ ++ rxinfo->desc = NULL; ++ rxinfo->idx = 0; ++ rxinfo->num_desc = 0; ++ rxinfo->size_desc_queue = 0; ++} ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++static void MDev_EMAC_MemFree(struct emac_handle *hemac) ++{ ++ if (hemac->mem_info.length) ++ { ++ msys_release_dmem(&hemac->mem_info); ++ memset(&hemac->mem_info, 0, sizeof(hemac->mem_info)); ++ } ++} ++ ++static void* MDev_EMAC_MemAlloc(struct emac_handle *hemac, u32 size) ++{ ++ int ret; ++ ++ hemac->mem_info.length = size; ++ if (0 == size) ++ return NULL; ++ // strcpy(hemac->mem_info.name, "EMAC_BUFF"); ++ sprintf(hemac->mem_info.name, "%s_buff", hemac->name); ++ if((ret=msys_request_dmem(&hemac->mem_info))) ++ { ++ memset(&hemac->mem_info, 0, sizeof(hemac->mem_info)); ++ panic("unable to locate DMEM for EMAC alloRAM!! %d\n", size); ++ return NULL; ++ } ++ return (void*)((size_t)hemac->mem_info.kvirt); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC init Variable ++//------------------------------------------------------------------------------------------------- ++static void* MDev_EMAC_VarInit(struct emac_handle *hemac) ++{ ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ int txd_len; ++ void* p = NULL; ++#if EMAC_FLOW_CONTROL_RX ++ static u8 pause_pkt[] = ++ { ++ //DA - multicast ++ 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01, ++ //SA ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ //Len-Type ++ 0x88, 0x08, ++ //Ctrl code ++ 0x00, 0x01, ++ //Ctrl para 8192 ++ 0x20, 0x00 ++ }; ++ int pausePktSize = sizeof(pause_pkt); ++ static u8 ETH_PAUSE_FRAME_DA_MAC[6] = { 0x01UL, 0x80UL, 0xC2UL, 0x00UL, 0x00UL, 0x01UL }; ++#else ++ int pausePktSize = 0; ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++ // TXD init ++ txd_len = MHal_EMAC_TXD_Cfg(hemac->hal, hemac->txd_num); ++#if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ #if (EMAC_SG && EMAC_SG_BUF_CACHE) ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + (RX_DESC_NUM * EMAC_PACKET_SIZE_MAX) + txd_len + pausePktSize); ++ #else ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + (RX_DESC_NUM * EMAC_PACKET_SIZE_MAX) + txd_len + pausePktSize); ++ #endif ++ } ++ else ++#endif // #if EXT_PHY_PATCH ++ { ++ #if (EMAC_SG && EMAC_SG_BUF_CACHE) ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + txd_len + pausePktSize); ++ #else ++ p = MDev_EMAC_MemAlloc(hemac, RX_DESC_QUEUE_SIZE + txd_len + pausePktSize); ++ #endif ++ } ++/* ++ if (NULL == p) ++ { ++ printk("[%s][%d] alloc memory fail %d\n", __FUNCTION__, __LINE__, RX_DESC_QUEUE_SIZE + txd_len); ++ return NULL; ++ } ++*/ ++ ++ if (p) ++ { ++ if (txd_len) ++ { ++ MHal_EMAC_TXD_Buf(hemac->hal, p, VIRT2BUS(p), txd_len); ++ p = (void*)(((size_t)p) + txd_len); ++ } ++#ifndef CONFIG_SS_SWTOE ++ p = MDev_EMAC_RX_Desc_Init(hemac, p); ++#endif ++#if EXT_PHY_PATCH ++ if (IS_EXT_PHY(hemac)) ++ { ++ hemac->pu8RXBuf = (char*)p; ++ p = (void*) (hemac->pu8RXBuf + (RX_DESC_NUM * EMAC_PACKET_SIZE_MAX)); ++ } ++ else ++ { ++ hemac->pu8RXBuf = NULL; ++ } ++#endif ++ } ++ ++#if EMAC_FLOW_CONTROL_RX ++ hemac->isPausePkt = 0; ++ hemac->u8PausePktSize = pausePktSize; ++ hemac->pu8PausePkt = (pausePktSize) ? p : NULL; ++ if (pausePktSize) ++ { ++ memcpy(hemac->pu8PausePkt, pause_pkt, pausePktSize); ++ } ++ p = (void*)(((char*)p) + pausePktSize); ++#endif // #if EMAC_FLOW_CONTROL_RX ++ ++#if EMAC_SG ++ hemac->maxSG = 0; ++#endif // #if EMAC_SG ++ ++ memset(hemac->sa, 0, sizeof(hemac->sa)); ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_EMAC_get_SA1H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA1L_addr(hemac->hal); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy(&hemac->sa[0][0], &addr, 6); ++ } ++ else ++ { ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_EMAC_get_SA2H_addr(hemac->hal); ++ LoAddr = MHal_EMAC_get_SA2L_addr(hemac->hal); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy(&hemac->sa[0][0], &addr, 6); ++ } ++ else ++ { ++ memcpy(&hemac->sa[0][0], MY_MAC, 6); ++ } ++ } ++#if EMAC_FLOW_CONTROL_RX ++ memcpy(&hemac->sa[1][0], ETH_PAUSE_FRAME_DA_MAC, 6); ++#endif ++ return p; ++} ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void MDev_EMAC_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ MDev_EMAC_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++#if KERNEL_PHY ++static void emac_phy_link_adjust(struct net_device *dev) ++{ ++ int cam = 0; // 0:No CAM, 1:Yes ++ int rcv_bcast = 1; // 0:No, 1:Yes ++ int rlf = 0; ++ u32 word_ETH_CFG = 0x00000800UL; ++ struct emac_handle* hemac =(struct emac_handle*) netdev_priv(dev); ++ unsigned long flag1; ++ ++ spin_lock_irqsave(&hemac->mutexNetIf, flag1); ++ if (!hemac->bEthCfg) ++ { ++ // ETH_CFG Register ----------------------------------------------------- ++ // (20070808) IMPORTANT: REG_ETH_CFG:bit1(FD), 1:TX will halt running RX frame, 0:TX will not halt running RX frame. ++ // If always set FD=0, no CRC error will occur. But throughput maybe need re-evaluate. ++ // IMPORTANT: (20070809) NO_MANUAL_SET_DUPLEX : The real duplex is returned by "negotiation" ++ word_ETH_CFG = 0x00000800UL; // Init: CLK = 0x2 ++ if (SPEED_100 == dev->phydev->speed) ++ word_ETH_CFG |= 0x00000001UL; ++ if (DUPLEX_FULL == dev->phydev->duplex) ++ word_ETH_CFG |= 0x00000002UL; ++ if (cam) ++ word_ETH_CFG |= 0x00000200UL; ++ if (0 == rcv_bcast) ++ word_ETH_CFG |= 0x00000020UL; ++ if (1 == rlf) ++ word_ETH_CFG |= 0x00000100UL; ++ ++ MHal_EMAC_Write_CFG(hemac->hal, word_ETH_CFG); ++ hemac->bEthCfg = 1; ++ } ++ ++ if (dev->phydev->link) ++ { ++ MHal_EMAC_update_speed_duplex(hemac->hal, dev->phydev->speed, dev->phydev->duplex); ++ netif_carrier_on(dev); ++ netif_start_queue(dev); ++ } ++ else ++ { ++ // unsigned long flags; ++ ++ if (!netif_queue_stopped(dev)) ++ netif_stop_queue(dev); ++ if (netif_carrier_ok(dev)) ++ netif_carrier_off(dev); ++ // spin_lock_irqsave(&hemac->mutexTXQ, flags); ++ // skb_queue_reset(&(hemac->skb_queue_tx)); ++ // spin_unlock_irqrestore(&hemac->mutexTXQ, flags); ++ } ++ spin_unlock_irqrestore(&hemac->mutexNetIf, flag1); ++ ++#if 0 ++ printk("[%s][%d] adjust phy (link, speed, duplex) = (%d, %d, %d, %d)\n", __FUNCTION__, __LINE__, ++ dev->phydev->link, dev->phydev->speed, dev->phydev->duplex, dev->phydev->autoneg); ++#endif ++} ++ ++static int emac_phy_connect(struct net_device* netdev) ++{ ++ struct emac_handle* hemac =(struct emac_handle*) netdev_priv(netdev); ++ struct device_node* np = NULL; ++ struct phy_device *phydev; ++ ++ np = of_parse_phandle(netdev->dev.of_node, "phy-handle", 0); ++ if (!np && of_phy_is_fixed_link(netdev->dev.of_node)) ++ if (!of_phy_register_fixed_link(netdev->dev.of_node)) ++ np = of_node_get(netdev->dev.of_node); ++ if (!np) ++ { ++ printk("[%s][%d] can not find phy-handle in dts\n", __FUNCTION__, __LINE__); ++ return -ENODEV; ++ } ++ ++#if 0 ++ if (0 > (phy_mode = of_get_phy_mode(np))) ++ { ++ printk("[%s][%d] incorrect phy-mode %d\n", __FUNCTION__, __LINE__, phy_mode); ++ goto jmp_err_connect; ++ } ++#endif ++#if 0 ++ printk("[%s][%d] phy_mode = %d\n", __FUNCTION__, __LINE__, hemac->phy_mode); ++ printk("[%s][%d] of_phy_connect (netdev, np, emac_phy_link_adjust) = (0x%08x, 0x%08x, 0x%08x)\n", ++ __FUNCTION__, __LINE__, ++ (int)netdev, (int)np, (int)emac_phy_link_adjust); ++#endif ++ if (!(phydev = of_phy_connect(netdev, np, emac_phy_link_adjust, 0, hemac->phy_mode))) ++ { ++ printk("[%s][%d] could not connect to PHY\n", __FUNCTION__, __LINE__); ++ goto jmp_err_connect; ++ } ++ ++ phy_init_hw(phydev); ++ ++ printk("[%s][%d] connected mac %s to PHY at %s [uid=%08x, driver=%s]\n", __FUNCTION__, __LINE__, ++ hemac->name, phydev_name(phydev), phydev->phy_id, phydev->drv->name); ++ ++ netdev->phydev->autoneg = AUTONEG_ENABLE; ++ netdev->phydev->speed = 0; ++ netdev->phydev->duplex = 0; ++#if 0 ++ if (of_phy_is_fixed_link(netdev->dev.of_node)) ++ dev->phydev->supported |= ++ SUPPORTED_Pause | SUPPORTED_Asym_Pause; ++#endif ++#if 0 ++ dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause; ++#endif ++ ++ // the speed has to be limited to 10 MBits/sec in FPGA ++ { ++ u32 max_speed = 0; ++ if (!of_property_read_u32(netdev->dev.of_node, "max-speed", &max_speed)) ++ { ++ switch (max_speed) ++ { ++ case 10: ++ phy_set_max_speed(phydev, SPEED_10); ++ break; ++ case 100: ++ phy_set_max_speed(phydev, SPEED_100); ++ break; ++ default: ++ break; ++ } ++ } ++ } ++#if (EMAC_FLOW_CONTROL_TX || EMAC_FLOW_CONTROL_RX) ++ netdev->phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause); ++#else ++ netdev->phydev->supported &= PHY_BASIC_FEATURES; ++#endif ++ netdev->phydev->advertising = netdev->phydev->supported | ADVERTISED_Autoneg; ++ if (0 > phy_start_aneg(netdev->phydev)) ++ { ++ printk("[%s][%d] phy_start_aneg fail\n", __FUNCTION__, __LINE__); ++ } ++ of_node_put(np); ++ return 0; ++ ++jmp_err_connect: ++ if (of_phy_is_fixed_link(netdev->dev.of_node)) ++ of_phy_deregister_fixed_link(netdev->dev.of_node); ++ of_node_put(np); ++ printk("[%s][%d]: invalid phy\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++} ++#endif ++ ++static int __init MDev_EMAC_ndo_init(struct net_device *dev) ++{ ++#if KERNEL_PHY ++ emac_phy_connect(dev); ++#endif ++ return 0; ++} ++ ++static void MDev_EMAC_ndo_uninit(struct net_device *dev) ++{ ++#if KERNEL_PHY ++ phy_disconnect(dev->phydev); ++#endif ++} ++ ++/* ++static void MDev_EMAC_ndo_tx_timeout(struct net_device *dev) ++{ ++} ++*/ ++ ++int MDev_EMAC_ndo_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ if ((new_mtu < 68) || (new_mtu > EMAC_MTU)) ++ { ++ printk("[%s][%d] not support mtu size %d\n", __FUNCTION__, __LINE__, new_mtu); ++ return -EINVAL; ++ } ++ printk("[%s][%d] change mtu size from %d to %d\n", __FUNCTION__, __LINE__, dev->mtu, new_mtu); ++ dev->mtu = new_mtu; ++ return 0; ++} ++ ++static int sstar_emac_get_link_ksettings(struct net_device *ndev, ++ struct ethtool_link_ksettings *cmd) ++{ ++ return phy_ethtool_ksettings_get(ndev->phydev, cmd); ++} ++ ++static int sstar_emac_set_link_ksettings(struct net_device *ndev, ++ const struct ethtool_link_ksettings *cmd) ++{ ++ return phy_ethtool_ksettings_set(ndev->phydev, cmd); ++} ++ ++static int sstar_emac_nway_reset(struct net_device *dev) ++{ ++ return genphy_restart_aneg(dev->phydev); ++} ++ ++static u32 sstar_emac_get_link(struct net_device *dev) ++{ ++ int err; ++ ++ err = genphy_update_link(dev->phydev); ++ if (err) ++ return ethtool_op_get_link(dev); ++ return dev->phydev->link; ++} ++ ++static int MDev_EMAC_set_features(struct net_device *netdev, ++ netdev_features_t features) ++{ ++ netdev->features = features; ++ return 0; ++} ++ ++static netdev_features_t MDev_EMAC_fix_features( ++ struct net_device *netdev, netdev_features_t features) ++{ ++ return (features & EMAC_FEATURES); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Initialize the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++static const struct net_device_ops mstar_lan_netdev_ops = { ++ .ndo_init = MDev_EMAC_ndo_init, ++ .ndo_uninit = MDev_EMAC_ndo_uninit, ++ .ndo_change_mtu = MDev_EMAC_ndo_change_mtu, ++ .ndo_open = MDev_EMAC_open, ++ .ndo_stop = MDev_EMAC_close, ++ .ndo_start_xmit = MDev_EMAC_tx, ++ .ndo_set_mac_address = MDev_EMAC_set_mac_address, ++ .ndo_set_rx_mode = MDev_EMAC_set_rx_mode, ++ .ndo_do_ioctl = MDev_EMAC_ioctl, ++ .ndo_get_stats = MDev_EMAC_stats, ++ .ndo_set_features = MDev_EMAC_set_features, ++ .ndo_fix_features = MDev_EMAC_fix_features, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = MDev_EMAC_netpoll, ++#endif ++ ++}; ++ ++static const struct ethtool_ops sstar_emac_ethtool_ops = { ++ .get_link_ksettings = sstar_emac_get_link_ksettings, ++ .set_link_ksettings = sstar_emac_set_link_ksettings, ++ .nway_reset = sstar_emac_nway_reset, ++ .get_link = sstar_emac_get_link, ++}; ++#endif ++ ++static ssize_t dlist_info_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return count; ++#else ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ int idx=0; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if(0==input) ++ { ++ RBNA_detailed=0; ++ } ++ else if(1==input) ++ { ++ RBNA_detailed=1; ++ } ++ else if(2==input) ++ { ++ max_rx_packet_count=0; ++ max_tx_packet_count=0; ++ min_tx_fifo_idle_count=0xffff; ++ } ++ else if(3==input) ++ { ++ for(idx=0; idxirq_count)/sizeof(u32); idx++) ++ hemac->irq_count[idx]=0; ++ } ++ return count; ++#endif ++} ++ ++static ssize_t dlist_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return 0; ++#else ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int idx=0; ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ int empty=0; ++ int max= rxinfo->num_desc; ++ u32 u32RBQP_Addr=0; ++ char descriptor_maps[RX_DESC_NUM]; ++ ++ for(idx=0;idxnum_desc;idx++) ++ { ++ if(!((rxinfo->desc[idx].addr) & EMAC_DESC_DONE)) ++ { ++ empty++; ++ descriptor_maps[idx]=1; ++ } ++ else ++ { ++ descriptor_maps[idx]=0; ++ } ++ } ++ u32RBQP_Addr = BUS2PA(MHal_EMAC_Read_RBQP(hemac->hal))/RX_DESC_SIZE; ++ str += scnprintf(str, end - str, "%s=0x%x\n", "RBQP_size", max); ++ str += scnprintf(str, end - str, "empty=0x%x, hemac->rxBuffIndex=0x%x, u32RBQP_Addr=0x%x\n", ++ empty, rxinfo->idx, u32RBQP_Addr); ++ #define CHANGE_LINE_LENG 0x20 ++ for(idx=0;idxnum_desc;idx++) ++ { ++ if(idx%CHANGE_LINE_LENG==0x0) ++ str += scnprintf(str, end - str, "0x%03x: ", idx); ++ ++ str += scnprintf(str, end - str, "%d", descriptor_maps[idx]); ++ ++ if(idx%0x10==(0xF)) ++ str += scnprintf(str, end - str, " "); ++ ++ if(idx%CHANGE_LINE_LENG==(CHANGE_LINE_LENG-1)) ++ str += scnprintf(str, end - str, "\n"); ++ } ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "max_rx_packet_count", max_rx_packet_count); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_DONE", hemac->irq_count[IDX_CNT_INT_DONE]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_RCOM", hemac->irq_count[IDX_CNT_INT_RCOM]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_RBNA", hemac->irq_count[IDX_CNT_INT_RBNA]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_TOVR", hemac->irq_count[IDX_CNT_INT_TOVR]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_TUND", hemac->irq_count[IDX_CNT_INT_TUND]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_RTRY", hemac->irq_count[IDX_CNT_INT_RTRY]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_TCOM", hemac->irq_count[IDX_CNT_INT_TCOM]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_INT_ROVR", hemac->irq_count[IDX_CNT_INT_ROVR]); ++ str += scnprintf(str, end - str, "%s=%d\n", "IDX_CNT_JULIAN_D", hemac->irq_count[IDX_CNT_JULIAN_D]); ++/* ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates1", hemac->gu32PhyResetCount1); ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates2", hemac->gu32PhyResetCount2); ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates3", hemac->gu32PhyResetCount3); ++ str += scnprintf(str, end - str, "%s=%d\n", "MonitorAnStates4", hemac->gu32PhyResetCount4); ++ str += scnprintf(str, end - str, "%s=%d\n", "RESET count", hemac->gu32PhyResetCount); ++*/ ++ str += scnprintf(str, end - str, "%s=%d\n", "skb_tx_send", hemac->skb_tx_send); ++ str += scnprintf(str, end - str, "%s=%d\n", "skb_tx_free", hemac->skb_tx_free); ++ str += scnprintf(str, end - str, "%s=%d\n", "rx_duration_max", rx_duration_max); ++ str += scnprintf(str, end - str, "%s=%d\n", "rx_packet_cnt", rx_packet_cnt); ++ ++/* ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_hw", MHal_EMAC_TXQ_Used(hemac->hal)); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_free_hw", MHal_EMAC_TXQ_Free()); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_0", skb_queue_used(&hemac->skb_queue_tx, 0)); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_free_0", skb_queue_free(&hemac->skb_queue_tx, 0)); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_1", skb_queue_used(&hemac->skb_queue_tx, 1)); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_free_1", skb_queue_free(&hemac->skb_queue_tx, 1)); ++ ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_used_2", skb_queue_used(&hemac->skb_queue_tx, 2)); ++ ++ str += scnprintf(str, end - str, "(size0, size1) = (%d, %d)\n", hemac->skb_queue_tx.size[0], hemac->skb_queue_tx.size[1]); ++ str += scnprintf(str, end - str, "read = %d\n", hemac->skb_queue_tx.read); ++ str += scnprintf(str, end - str, "rw = %d\n", hemac->skb_queue_tx.rw); ++ str += scnprintf(str, end - str, "write = %d\n", hemac->skb_queue_tx.write); ++*/ ++ { ++ struct timespec ct; ++ int duration; ++ u64 data_done_ct; ++ unsigned long flags; ++ u32 txPkt_ct = hemac->skb_tx_send; ++ u32 txInt_ct = hemac->irq_count[IDX_CNT_INT_TCOM]; ++ ++ getnstimeofday(&ct); ++ duration = (ct.tv_sec - hemac->data_time_last.tv_sec)*1000 + (ct.tv_nsec - hemac->data_time_last.tv_nsec)/1000000; ++ spin_lock_irqsave(&hemac->emac_data_done_lock, flags); ++ data_done_ct = hemac->data_done; ++ hemac->data_done = 0; ++ spin_unlock_irqrestore(&hemac->emac_data_done_lock, flags); ++ ++ // tx_duration_max = (tx_duration_max < duration) ? duration : tx_duration_max; ++ hemac->data_time_last = ct; ++ str += scnprintf(str, end - str, "%s=%lld\n", "data_done", data_done_ct); ++ str += scnprintf(str, end - str, "%s=%d\n", "data_duration", duration); ++ do_div(data_done_ct, duration); ++ str += scnprintf(str, end - str, "%s=%lld\n", "data_average", data_done_ct); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_pkt (duration)", txPkt_ct - hemac->txPkt); ++ str += scnprintf(str, end - str, "%s=%d\n", "tx_int (duration)", txInt_ct - hemac->txInt); ++ hemac->txPkt = txPkt_ct; ++ hemac->txInt = txInt_ct; ++ } ++ str += scnprintf(str, end - str, "%s=%d\n", "MHal_EMAC_TXQ_Mode", MHal_EMAC_TXQ_Mode(hemac->hal)); ++#if EMAC_SG ++ str += scnprintf(str, end - str, "%s=%d\n", "maxSG", hemac->maxSG); ++#endif // #if #if EMAC_SG ++ return (str - buf); ++#endif ++} ++DEVICE_ATTR(dlist_info, 0644, dlist_info_show, dlist_info_store); ++ ++static ssize_t info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return 0; ++#else ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ rx_desc_queue_t* rxinfo = &(hemac->rx_desc_queue); ++ ++ // str += scnprintf(str, end - str, "%s %s\n", __DATE__, __TIME__); ++ str += scnprintf(str, end - str, "RAM_ALLOC_SIZE=0x%08x\n", rxinfo->size_desc_queue); ++ str += scnprintf(str, end - str, "RAM_VA_BASE=0x%08x\n", (int)rxinfo->desc); ++ str += scnprintf(str, end - str, "RAM_PA_BASE=0x%08x\n", (int)VIRT2PA(rxinfo->desc)); ++ ++#if MSTAR_EMAC_NAPI ++ str += scnprintf(str, end - str, "NAPI enabled, NAPI_weight=%d\n", EMAC_NAPI_WEIGHT); ++#endif ++ str += scnprintf(str, end - str, "ZERO_COPY enabled\n"); ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++ str += scnprintf(str, end - str, "NEW_TX_QUEUE_INTERRUPT_THRESHOLD enabled\n"); ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++#endif ++} ++DEVICE_ATTR(info, 0444, info_show, NULL); ++ ++//struct timeval proc_read_time; ++static ssize_t tx_sw_queue_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return 0; ++#else ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int idleCount=0; ++ ++ idleCount= MHal_EMAC_TXQ_Free(hemac->hal); ++ str += scnprintf(str, end - str, ++ "netif_queue_stopped=%d \n idleCount=%d \n irqcnt=%d, tx_irqcnt=%d \n tx_bytes_per_timerbak=%d \n min_tx_fifo_idle_count=%d \n", ++ netif_queue_stopped(netdev), ++ idleCount, hemac->irqcnt, hemac->tx_irqcnt, ++ tx_bytes_per_timerbak, ++ min_tx_fifo_idle_count); ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++#endif ++} ++DEVICE_ATTR(tx_sw_queue_info, 0444, tx_sw_queue_info_show, NULL); ++ ++static ssize_t reverse_led_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return count; ++#else ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ MHal_EMAC_Set_Reverse_LED(hemac->hal, input); ++ return count; ++#endif ++} ++ ++static ssize_t reverse_led_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return 0; ++#else ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u8 u8reg=0; ++ u8reg = MHal_EMAC_Get_Reverse_LED(hemac->hal); ++ return sprintf(buf, "%d\n", u8reg); ++#endif ++} ++DEVICE_ATTR(reverse_led, 0644, reverse_led_show, reverse_led_store); ++ ++static ssize_t sw_led_flick_speed_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return count; ++#else ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ hemac->led_flick_speed = input; ++ return count; ++#endif ++} ++static ssize_t sw_led_flick_speed_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return 0; ++#else ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++ return sprintf(buf, "LED flick speed, the smaller the faster\n%d\n", hemac->led_flick_speed); ++#endif ++} ++DEVICE_ATTR(sw_led_flick_speed, 0644, sw_led_flick_speed_show, sw_led_flick_speed_store); ++ ++extern void MHal_EMAC_phy_trunMax(void*); ++// extern void MHal_EMAC_trim_phy(void*); ++static ssize_t turndrv_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++#ifdef CONFIG_SS_SWTOE ++ return count; ++#else ++ // u32 input; ++ struct net_device* netdev = (struct net_device*) dev_get_drvdata(dev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ ++#if 0 ++ if(!strncmp(buf, "0",strlen("0"))) ++ { ++ MHal_EMAC_trim_phy(hemac->hal); ++ return count; ++ } ++#endif ++ ++ if(!strncmp(buf, "max",strlen("max"))) ++ { ++ MHal_EMAC_phy_trunMax(hemac->hal); ++ return count; ++ } ++ ++ if(!strncmp(buf, "f10t",strlen("10t"))) ++ { ++ phy_set_max_speed(netdev->phydev, SPEED_10); ++ return count; ++ } ++ if(!strncmp(buf, "an",strlen("an"))) ++ { ++/* ++ //force to set 10M on FPGA ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_ADVERTISE, 0x01e1UL); ++ mdelay(10); ++ MHal_EMAC_write_phy(hemac->hal, hemac->phyaddr, MII_BMCR, 0x1200UL); ++*/ ++ netdev->phydev->advertising = netdev->phydev->supported | ADVERTISED_Autoneg; ++ phy_start_aneg(netdev->phydev); ++ return count; ++ } ++#if DYNAMIC_INT_RX ++ if(!strncmp(buf, "dir_on", strlen("dir_on"))) ++ { ++ hemac->rx_stats_enable = 1; ++ } ++ if(!strncmp(buf, "dir_off", strlen("dir_off"))) ++ { ++ hemac->rx_stats_enable = 0; ++ } ++#endif ++ ++ { ++ unsigned char cmd[16]; ++ int param; ++ ++ if (2 == sscanf(buf, "%s %d", cmd, ¶m)) ++ { ++ if (!strncmp(cmd, "swing_100",strlen("swing_100"))) ++ { ++ u32 val; ++ int tmp; ++ MHal_EMAC_read_phy(hemac->hal, 0, 0x142, &val); ++ tmp = ((val >> 8) & 0x1f); ++ ++ if (tmp & 0x10) ++ { ++ tmp = tmp & 0xf; ++ tmp ++; ++ tmp = -tmp; ++ } ++ tmp += param; ++ if (tmp > 15) ++ tmp = 15; ++ if (tmp < -16) ++ tmp = -16; ++ if (tmp < 0) ++ { ++ tmp = -tmp; ++ tmp --; ++ tmp = tmp | 0x10; ++ } ++ tmp = tmp << 8; ++ ++ val = (val & ~0x1f00) | tmp; ++ MHal_EMAC_write_phy(hemac->hal, 0, 0x142, val); ++ } ++ } ++ } ++ ++ // input = simple_strtoul(buf, NULL, 10); ++ return count; ++#endif ++} ++ ++static ssize_t turndrv_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return 0; ++} ++ ++DEVICE_ATTR(turndrv, 0644, turndrv_show, turndrv_store); ++ ++static int MDev_EMAC_setup (struct net_device *dev) ++{ ++ struct emac_handle *hemac; ++ // dma_addr_t dmaaddr; ++ void* RetAddr; ++ unsigned long flags; ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ u32 retval; ++#endif ++ ++ hemac = (struct emac_handle *) netdev_priv(dev); ++ ++ if (hemac->bInit) ++ // if (already_initialized) ++ { ++ printk("[%s][%d] %s has been initiated\n", __FUNCTION__, __LINE__, hemac->name); ++ return FALSE; ++ } ++ if (hemac == NULL) ++ { ++ free_irq (dev->irq, dev); ++ EMAC_ERR("hemac fail\n"); ++ return -ENOMEM; ++ } ++ ++ hemac->netdev = dev; ++ ++ // skb_queue_create(&(hemac->skb_queue_tx), MHal_EMAC_TXQ_Size(), 256); ++ // skb_queue_create(&(hemac->skb_queue_tx), MHal_EMAC_TXQ_Size(), MHal_EMAC_TXQ_Size()); ++ // RetAddr = MDev_EMAC_VarInit(); ++ RetAddr = MDev_EMAC_VarInit(hemac); ++#ifndef CONFIG_SS_SWTOE ++ if(!RetAddr) ++ { ++ EMAC_ERR("Var init fail!!\n"); ++ return FALSE; ++ } ++ skb_queue_create(&(hemac->skb_queue_tx), MHal_EMAC_TXQ_Size(hemac->hal), MHal_EMAC_TXQ_Size(hemac->hal)+ hemac->txq_num_sw); ++#endif ++ MDev_EMAC_HW_init(dev); ++ ++ spin_lock_init(&hemac->mutexNetIf); ++ spin_lock_init(&hemac->mutexPhy); ++ spin_lock_init(&hemac->mutexTXQ); ++#if (0 == MSTAR_EMAC_NAPI) ++ spin_lock_init(&hemac->mutexRXInt); ++#endif ++ ++#if EMAC_FLOW_CONTROL_TX ++ spin_lock_init(&hemac->mutexFlowTX); ++ init_timer(&hemac->timerFlowTX); ++ hemac->timerFlowTX.data = (unsigned long)hemac; ++ hemac->timerFlowTX.expires = jiffies; ++ hemac->timerFlowTX.function = _MDev_EMAC_FlowTX_CB; ++ // hemac->isPauseTX = 0; ++#endif ++ ++#if REDUCE_CPU_FOR_RBNA ++ spin_lock_init(&hemac->mutexIntRX); ++ init_timer(&hemac->timerIntRX); ++ hemac->timerIntRX.data = (unsigned long)hemac; ++ hemac->timerIntRX.expires = jiffies; ++ hemac->timerIntRX.function = _MDev_EMAC_IntRX_CB; ++#endif ++ ++#if DYNAMIC_INT_RX ++ hemac->rx_stats_packet = 0xFFFFFFFF; ++ hemac->rx_stats_enable = 1; ++#endif ++ ++ ether_setup (dev); ++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,28) ++ dev->open = MDev_EMAC_open; ++ dev->stop = MDev_EMAC_close; ++ dev->hard_start_xmit = MDev_EMAC_tx; ++ dev->get_stats = MDev_EMAC_stats; ++ dev->set_multicast_list = MDev_EMAC_set_rx_mode; ++ dev->do_ioctl = MDev_EMAC_ioctl; ++ dev->set_mac_address = MDev_EMAC_set_mac_address; ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ dev->netdev_ops = &mstar_lan_netdev_ops; ++#endif ++ dev->tx_queue_len = EMAC_MAX_TX_QUEUE; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ ////SET_ETHTOOL_OPS(dev, ðtool_ops); ++ //EMAC_TODO("set Ethtool_ops\n"); ++ // netdev_set_default_ethtool_ops(dev, ðtool_ops); ++#endif ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MDev_EMAC_get_mac_address (dev); // Get ethernet address and store it in dev->dev_addr // ++ MDev_EMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ MHal_EMAC_enable_mdi(hemac->hal); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ dev->features |= NETIF_F_IP_CSUM; ++#endif ++ ++ dev->features |= EMAC_FEATURES; ++ dev->vlan_features |= EMAC_FEATURES; ++ ++ ++ hemac->irqcnt=0; ++ hemac->tx_irqcnt=0; ++ ++ dev->irq = hemac->irq_emac; ++ if (!dev->irq) ++ { ++ EMAC_ERR("Get irq number0 error from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ //Install the interrupt handler // ++ //Notes: Modify linux/kernel/irq/manage.c /* interrupt.h */ ++#ifdef CONFIG_SS_SWTOE ++ drv_swtoe_glue_req(hemac->cnx_id, _mdrv_emac_swtoe_cb, (void*)hemac); ++#else ++ if (request_irq(dev->irq, MDev_EMAC_interrupt, 0/*SA_INTERRUPT*/, dev->name, dev)) ++ return -EBUSY; ++#endif ++ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ // val = irq_of_parse_and_map(dev->dev.of_node, 1); ++ val = hemac->irq_lan; ++ if (!val) ++ { ++ EMAC_ERR("Get irq number0 error from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ if (request_irq(val/*INT_FIQ_LAN_ESD+32*/, MDev_EMAC_interrupt_cable_unplug, 0/*SA_INTERRUPT*/, dev->name, dev)) ++ return -EBUSY; ++#endif ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++ hemac->mstar_class_emac_device = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR_EMAC_NUM, hemac->u8Minor), NULL, hemac->name); ++ dev_set_drvdata(hemac->mstar_class_emac_device, (void*)dev); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_tx_sw_queue_info); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_dlist_info); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_reverse_led); ++ // device_create_file(hemac->mstar_class_emac_device, &dev_attr_check_link_time); ++ // device_create_file(hemac->mstar_class_emac_device, &dev_attr_check_link_timedis); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_info); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_sw_led_flick_speed); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_turndrv); ++#if 0//ajtest ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_ajtest_recv_count); ++#endif ++#if defined(PACKET_DUMP) ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_tx_dump); ++ device_create_file(hemac->mstar_class_emac_device, &dev_attr_rx_dump); ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Restar the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_SwReset(struct net_device *dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(dev); ++ u32 oldCFG, oldCTL; ++ // u32 retval; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MDev_EMAC_get_mac_address (dev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ oldCFG = MHal_EMAC_Read_CFG(hemac->hal); ++ oldCTL = MHal_EMAC_Read_CTL(hemac->hal) & ~(EMAC_TE | EMAC_RE); ++ ++#ifndef CONFIG_SS_SWTOE ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ free_rx_skb(hemac); // @FIXME : how about RX descriptor ++#endif ++ netif_stop_queue (dev); ++ ++ /* ++ retval = MHal_EMAC_Read_JULIAN_0100(hemac->hal); ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, retval & 0x00000FFFUL); ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, retval); ++ */ ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, 1); ++ ++ MDev_EMAC_HW_init(dev); ++ MHal_EMAC_Write_CFG(hemac->hal, oldCFG); ++ MHal_EMAC_Write_CTL(hemac->hal, oldCTL); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MHal_EMAC_enable_mdi(hemac->hal); ++ MDev_EMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ // (void)MDev_EMAC_update_linkspeed (dev); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++#ifdef CONFIG_SS_SWTOE ++ drv_swtoe_glue_en(hemac->cnx_id, 0xFFFFFFFF, 0); ++ drv_swtoe_glue_en(hemac->cnx_id, hemac->gu32intrEnable, 1); ++#else ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ MHal_EMAC_IntEnable(hemac->hal, hemac->gu32intrEnable, 1); ++#endif ++ ++ MDev_EMAC_start(dev); ++ MDev_EMAC_set_rx_mode(dev); ++ netif_start_queue (dev); ++ hemac->contiROVR = 0; ++ EMAC_ERR("=> Take %lu ms to reset EMAC!\n", (getCurMs() - hemac->oldTime)); ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Detect MAC and PHY and perform initialization ++//------------------------------------------------------------------------------------------------- ++#if defined (CONFIG_OF) ++static struct of_device_id mstaremac_of_device_ids[] = { ++ {.compatible = "sstar-emac"}, ++ {}, ++}; ++#endif ++ ++static int MDev_EMAC_probe (struct net_device *dev) ++{ ++ int detected; ++ /* Read the PHY ID registers - try all addresses */ ++ detected = MDev_EMAC_setup(dev); ++ return detected; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC MACADDR Setup ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef MODULE ++ ++#define MACADDR_FORMAT "XX:XX:XX:XX:XX:XX" ++ ++static int __init macaddr_auto_config_setup(char *addrs) ++{ ++ if (strlen(addrs) == strlen(MACADDR_FORMAT) ++ && ':' == addrs[2] ++ && ':' == addrs[5] ++ && ':' == addrs[8] ++ && ':' == addrs[11] ++ && ':' == addrs[14] ++ ) ++ { ++ addrs[2] = '\0'; ++ addrs[5] = '\0'; ++ addrs[8] = '\0'; ++ addrs[11] = '\0'; ++ addrs[14] = '\0'; ++ ++ MY_MAC[0] = (u8)simple_strtoul(&(addrs[0]), NULL, 16); ++ MY_MAC[1] = (u8)simple_strtoul(&(addrs[3]), NULL, 16); ++ MY_MAC[2] = (u8)simple_strtoul(&(addrs[6]), NULL, 16); ++ MY_MAC[3] = (u8)simple_strtoul(&(addrs[9]), NULL, 16); ++ MY_MAC[4] = (u8)simple_strtoul(&(addrs[12]), NULL, 16); ++ MY_MAC[5] = (u8)simple_strtoul(&(addrs[15]), NULL, 16); ++ ++ /* set back to ':' or the environment variable would be destoried */ // REVIEW: this coding style is dangerous ++ addrs[2] = ':'; ++ addrs[5] = ':'; ++ addrs[8] = ':'; ++ addrs[11] = ':'; ++ addrs[14] = ':'; ++ } ++ ++ return 1; ++} ++ ++__setup("macaddr=", macaddr_auto_config_setup); ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC init module ++//------------------------------------------------------------------------------------------------- ++#if KERNEL_PHY ++static int MDev_EMAC_mii_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) bus->priv; ++ int ret; ++ ++ ret = MHal_EMAC_write_phy(hemac->hal, phy_addr, phy_reg, (u32)val); ++ return ret; ++} ++ ++static int MDev_EMAC_mii_read(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val; ++ struct emac_handle *hemac = (struct emac_handle *) bus->priv; ++ int ret; ++ ++ ret = MHal_EMAC_read_phy(hemac->hal, phy_addr, phy_reg, &val); ++ return (int)val; ++} ++ ++static int MDev_EMAC_mii_init(struct net_device* emac_dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ struct device_node *mii_np = NULL; ++ int ret = 0; ++ ++ // the force internal mdio bus in FPGA ++ if (1) ++ { ++ u32 mdio_path = 0; ++ if (!of_property_read_u32(emac_dev->dev.of_node, "mdio_path", &mdio_path)) ++ { ++ MHal_EMAC_mdio_path(hemac->hal, mdio_path); ++ } ++ } ++ ++ if (!(mii_np = of_get_child_by_name(emac_dev->dev.of_node, "mdio-bus"))) ++ { ++ // printk("[%s][%d] no child node of mdio-bus is found\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ if (!of_device_is_available(mii_np)) ++ { ++ // printk("[%s][%d] mii_np is unavailable\n", __FUNCTION__, __LINE__); ++ ret = -2; ++ goto jmp_err_put_node; ++ } ++ if (!(hemac->mii_bus = devm_mdiobus_alloc(hemac->dev))) ++ { ++ // printk("[%s][%d] devm_mdiobus_alloc fail\n", __FUNCTION__, __LINE__); ++ ret = -3; ++ goto jmp_err_put_node; ++ } ++ ++ hemac->mii_bus->name = "mdio"; ++ hemac->mii_bus->read = MDev_EMAC_mii_read; ++ hemac->mii_bus->write = MDev_EMAC_mii_write; ++ hemac->mii_bus->priv = hemac; ++ hemac->mii_bus->parent = hemac->dev; ++ ++ snprintf(hemac->mii_bus->id, MII_BUS_ID_SIZE, "%s@%s", mii_np->name, hemac->name); ++ ret = of_mdiobus_register(hemac->mii_bus, mii_np); ++jmp_err_put_node: ++ of_node_put(mii_np); ++ return ret; ++} ++ ++static void MDev_EMAC_mii_uninit(struct net_device* emac_dev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ if (!hemac->mii_bus) ++ return; ++ mdiobus_unregister(hemac->mii_bus); ++ devm_mdiobus_free(hemac->dev, hemac->mii_bus); ++} ++#endif ++ ++static int MDev_EMAC_init(struct platform_device *pdev) ++{ ++ struct emac_handle *hemac; ++ int ret; ++ struct net_device* emac_dev = NULL; ++ ++ emac_dev = alloc_etherdev(sizeof(*hemac)); ++ hemac = netdev_priv(emac_dev); ++ ++ if (!emac_dev) ++ { ++ EMAC_ERR( KERN_ERR "No EMAC dev mem!\n" ); ++ return -ENOMEM; ++ } ++ ++#ifdef CONFIG_SS_SWTOE ++ if (drv_swtoe_create(DRV_SWTOE_PROT_BYPASS, &hemac->cnx_id)) ++ { ++ return -ENOMEM; ++ } ++#endif ++ ++ // led gpio ++ hemac->led_orange = -1; ++ hemac->led_green = -1; ++ hemac->led_count = 0; ++ hemac->led_flick_speed = 30; ++ ++ hemac->gu32intrEnable = 0; ++ memset(hemac->irq_count, 0, sizeof(hemac->irq_count)); ++ ++ hemac->skb_tx_send = 0; ++ hemac->skb_tx_free = 0; ++ hemac->data_done = 0; ++ memset(&hemac->data_time_last, 0, sizeof(hemac->data_time_last)); ++ spin_lock_init(&hemac->emac_data_done_lock); ++ ++ hemac->txPkt = 0; ++ hemac->txInt = 0; ++ ++ hemac->initstate= 0; ++ hemac->contiROVR = 0; ++ ++ hemac->oldTime = 0; ++ hemac->PreLinkStatus = 0; ++ ++ hemac->irq_emac = 0; ++ hemac->irq_lan = 0; ++ ++ hemac->name = NULL; ++ hemac->bInit = 0; ++ hemac->bEthCfg = 0; ++ ++ hemac->u8Minor = _u8Minor; ++ _u8Minor++; ++#if KERNEL_PHY ++ hemac->dev = &pdev->dev; ++#endif ++ ++ emac_dev->dev.of_node = pdev->dev.of_node; //pass of_node to MDev_EMAC_setup() ++ ++ SET_NETDEV_DEV(emac_dev, hemac->dev); ++ // emac_dev->ethtool_ops = &sstar_emac_ethtool_ops; ++ netdev_set_default_ethtool_ops(emac_dev, &sstar_emac_ethtool_ops); ++ ++ MDev_EMAC_dts(emac_dev); ++ hemac->hal = MHal_EMAC_Alloc(hemac->emacRIU, hemac->emacX32, hemac->phyRIU); ++ MHal_EMAC_Pad(hemac->hal, hemac->pad_reg, hemac->pad_msk, hemac->pad_val); ++ MHal_EMAC_PadLed(hemac->hal, hemac->pad_led_reg, hemac->pad_led_msk, hemac->pad_led_val); ++ MHal_EMAC_PhyMode(hemac->hal, hemac->phy_mode); ++ ++ if (0 == _phyReset) ++ { ++ #ifdef CONFIG_MS_PADMUX ++ if (mdrv_padmux_active()) ++ { ++ int gpio_no; ++ if (PAD_UNKNOWN != (gpio_no = mdrv_padmux_getpad(MDRV_PUSE_EMAC0_PHY_RESET))) ++ { ++ MDrv_GPIO_Set_High(gpio_no); ++ } ++ if (PAD_UNKNOWN != (gpio_no = mdrv_padmux_getpad(MDRV_PUSE_EMAC1_PHY_RESET))) ++ { ++ MDrv_GPIO_Set_High(gpio_no); ++ } ++ } ++ #endif ++ _phyReset = 1; ++ } ++ ++#if TX_THROUGHPUT_TEST ++ printk("==========TX_THROUGHPUT_TEST==============="); ++ pseudo_packet = alloc_skb(EMAC_PACKET_SIZE_MAX, GFP_ATOMIC); ++ memcpy(pseudo_packet->data, (void *)packet_content, sizeof(packet_content)); ++ pseudo_packet->len = sizeof(packet_content); ++#endif ++ ++#if RX_THROUGHPUT_TEST ++ printk("==========RX_THROUGHPUT_TEST==============="); ++ init_timer(&RX_timer); ++ ++ RX_timer.data = EMAC_RX_TMR; ++ RX_timer.function = RX_timer_callback; ++ RX_timer.expires = jiffies + 20*EMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++#endif ++ ++ MHal_EMAC_Power_On_Clk(hemac->hal, &pdev->dev); ++ ++#if MSTAR_EMAC_NAPI ++ netif_napi_add(emac_dev, &hemac->napi, MDev_EMAC_napi_poll, EMAC_NAPI_WEIGHT); ++#endif ++ ++ emac_dev->netdev_ops = &mstar_lan_netdev_ops; ++ if (MDev_EMAC_probe (emac_dev)) ++ goto end; ++ ++#if KERNEL_PHY ++ MDev_EMAC_mii_init(emac_dev); ++#endif ++ ++ if ((ret = register_netdev (emac_dev))) ++ goto end; ++ ++#ifdef CONFIG_SS_SWTOE ++ INIT_WORK(&hemac->rx_work, rx_work_func); ++#endif ++ ++ // printk( KERN_ERR "[EMAC]Init EMAC success! (add delay in reset)\n" ); ++ platform_set_drvdata(pdev, (void*)emac_dev); ++ hemac->bInit = 1; ++ return 0; ++ ++end: ++#ifndef CONFIG_SS_SWTOE ++ skb_queue_destroy(&(hemac->skb_queue_tx)); ++#endif ++ free_netdev(emac_dev); ++ emac_dev = NULL; ++ hemac->initstate = ETHERNET_TEST_INIT_FAIL; ++ EMAC_ERR( KERN_ERR "Init EMAC error!\n" ); ++ return -1; ++} ++ ++static void MDev_EMAC_dts(struct net_device* netdev) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(netdev); ++ unsigned int led_data; ++ struct resource res; ++ u32 val[3]; ++ ++ hemac->irq_emac = irq_of_parse_and_map(netdev->dev.of_node, 0); ++ hemac->irq_lan = irq_of_parse_and_map(netdev->dev.of_node, 1); ++ ++ if (of_property_read_u32(netdev->dev.of_node, "txd_num", &hemac->txd_num)) ++ { ++ hemac->txd_num = TXD_NUM; // default value ++ } ++ hemac->txd_num = (hemac->txd_num + 0xFF) & 0x100; // 256 alignment ++ if (of_property_read_u32(netdev->dev.of_node, "txq_num_sw", &hemac->txq_num_sw)) ++ { ++ hemac->txq_num_sw = TXQ_NUM_SW; // default value ++ } ++ ++ if(!of_property_read_u32(netdev->dev.of_node, "led-orange", &led_data)) ++ { ++ hemac->led_orange = (unsigned char)led_data; ++ // printk(KERN_ERR "[EMAC]Set emac_led_orange=%d\n",led_data); ++ } ++ ++ if(!of_property_read_u32(netdev->dev.of_node, "led-green", &led_data)) ++ { ++ hemac->led_green = (unsigned char)led_data; ++ // printk(KERN_ERR "[EMAC]Set emac_led_green=%d\n",led_data); ++ } ++ ++ if (!of_address_to_resource(netdev->dev.of_node, 0, &res)) ++ { ++ hemac->emacRIU = IO_ADDRESS(res.start); ++ // printk("[%s][%d] (emacRIU, start) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacRIU, res.start); ++ } ++ else ++ { ++ hemac->emacRIU = 0x1F2A2000; ++ hemac->emacRIU = IO_ADDRESS(hemac->emacRIU); ++ // printk("[%s][%d] (emacRIU) = (0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacRIU); ++ } ++ if (!of_address_to_resource(netdev->dev.of_node, 1, &res)) ++ { ++ hemac->emacX32 = IO_ADDRESS(res.start); ++ // printk("[%s][%d] (emacX32, start) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacX32, res.start); ++ } ++ else ++ { ++ hemac->emacX32 = 0x1F343C00; ++ hemac->emacX32 = IO_ADDRESS(hemac->emacX32); ++ // printk("[%s][%d] (emacX32) = (0x%08x)\n", __FUNCTION__, __LINE__, hemac->emacX32); ++ } ++ if (!of_address_to_resource(netdev->dev.of_node, 2, &res)) ++ { ++ hemac->phyRIU = (res.start) ? IO_ADDRESS(res.start) : 0; ++ // printk("[%s][%d] (phyRIU, start) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, hemac->phyRIU, res.start); ++ } ++ else ++ { ++ hemac->phyRIU = 0x1F006200; ++ hemac->phyRIU = IO_ADDRESS(hemac->phyRIU); ++ // printk("[%s][%d] (phyRIU) = (0x%08x)\n", __FUNCTION__, __LINE__, hemac->phyRIU); ++ } ++ ++ val[0] = val[1] = val[2] = 0; ++ if (of_property_read_u32_array(netdev->dev.of_node, "pad", val, 3)) ++ { ++ // printk("[%s][%d] parse pad mux fail\n", __FUNCTION__, __LINE__); ++ val[0] = 0x1F203C3C; ++ val[1] = 0x0004; ++ val[2] = 0x0004; ++ } ++ hemac->pad_reg = IO_ADDRESS(val[0]); ++ hemac->pad_msk = val[1]; ++ hemac->pad_val = val[2]; ++ ++ val[0] = val[1] = val[2] = 0; ++ if (of_property_read_u32_array(netdev->dev.of_node, "pad_led", val, 3)) ++ { ++ val[0] = 0x1F001CA0; ++ val[1] = 0x0030; ++ val[2] = 0x0010; ++ } ++ hemac->pad_led_reg = (val[0]) ? IO_ADDRESS(val[0]) : 0; ++ hemac->pad_led_msk = val[1]; ++ hemac->pad_led_val = val[2]; ++ ++ { ++ // struct device_node* np = NULL; ++ int phy_mode; ++ ++ hemac->phy_mode = PHY_INTERFACE_MODE_RMII; ++ ++ if (0 > (phy_mode = of_get_phy_mode(netdev->dev.of_node))) ++ { ++ struct device_node* np = NULL; ++ np = of_parse_phandle(netdev->dev.of_node, "phy-handle", 0); ++ if ((np) && (0 <= (phy_mode = of_get_phy_mode(np)))) ++ { ++ hemac->phy_mode = phy_mode; ++ } ++ if (np) ++ of_node_put(np); ++ } ++ else ++ { ++ hemac->phy_mode = phy_mode; ++ } ++ } ++ hemac->name = netdev->dev.of_node->name; ++} ++ ++#ifndef CONFIG_SS_SWTOE ++#if REDUCE_CPU_FOR_RBNA ++static void _MDev_EMAC_IntRX_CB(unsigned long data) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexIntRX, flags); ++ // MHal_EMAC_RX_Param(hemac->hal, 0x01, 0x01); ++ MHal_EMAC_RX_ParamRestore(hemac->hal); ++ spin_unlock_irqrestore(&hemac->mutexIntRX, flags); ++} ++#endif // #if REDUCE_CPU_FOR_RBNA ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++#if EMAC_FLOW_CONTROL_TX ++static void _MDev_EMAC_FlowTX_CB(unsigned long data) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hemac->mutexFlowTX, flags); ++ netif_wake_queue(hemac->netdev); ++ spin_unlock_irqrestore(&hemac->mutexFlowTX, flags); ++} ++ ++static int _MDrv_EMAC_is_PausePkt(struct sk_buff* skb, unsigned char* p_recv) ++{ ++ unsigned int mac_ctl_opcode = 0; ++ ++ if ((MAC_CONTROL_TYPE&0xFF) != ((skb->protocol>>8)&0xFF)) ++ return 0; ++ if (((MAC_CONTROL_TYPE>>8)&0xFF) != (skb->protocol&0xFF)) ++ return 0; ++ mac_ctl_opcode = (((*(p_recv+14))<<8)&0xFF00) + ((*(p_recv+15))&0xFF); ++ return (MAC_CONTROL_OPCODE == mac_ctl_opcode) ? 1 : 0; ++} ++ ++static int _MDrv_EMAC_Pause_TX(struct net_device* dev, struct sk_buff* skb, unsigned char* p_recv) ++{ ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(dev); ++ int pause_time = 0; ++ int pause_time_to_jiffies = 0; ++ unsigned long flags; ++ unsigned long expires; ++ ++#if EMAC_FLOW_CONTROL_TX_TEST ++{ ++ static unsigned int cnt = 0; ++ cnt++; ++ if ((cnt & 0xF) == 0) ++ { ++ // printk("[%s][%d] pseudo pause packet\n", __FUNCTION__, __LINE__); ++ pause_time = EMAC_FLOW_CONTROL_TX_TEST_TIME; ++ goto jump_pause_tx_test; ++ } ++} ++#endif // #if EMAC_FLOW_CONTROL_TX_TEST ++ ++ if (0 == _MDrv_EMAC_is_PausePkt(skb, p_recv)) ++ return 0; ++ ++ pause_time = (((*(p_recv+16))<<8)&0xFF00) + ((*(p_recv+17))&0xFF); ++ ++#if EMAC_FLOW_CONTROL_TX_TEST ++jump_pause_tx_test: ++#endif // #if EMAC_FLOW_CONTROL_TX_TEST ++ ++ if (SPEED_100 == dev->phydev->speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_100M)+((0==(pause_time%PAUSE_TIME_DIVISOR_100M))?0:1); ++ expires = jiffies + pause_time_to_jiffies; ++ } ++ else if (SPEED_10 == dev->phydev->speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_10M)+((0==(pause_time%PAUSE_TIME_DIVISOR_10M))?0:1); ++ expires = jiffies + pause_time_to_jiffies; ++ } ++ else ++ { ++ printk("[%s][%d] Get emac speed error : %d\n", __FUNCTION__, __LINE__, (int)dev->phydev->speed); ++ return 0; ++ } ++ spin_lock_irqsave(&hemac->mutexFlowTX, flags); ++ ++ if (0 == timer_pending(&hemac->timerFlowTX)) ++ { ++ netif_stop_queue (dev); ++ hemac->timerFlowTX.expires = expires; ++ add_timer(&hemac->timerFlowTX); ++ } ++ else ++ { ++ mod_timer(&hemac->timerFlowTX, expires); ++ } ++ spin_unlock_irqrestore(&hemac->mutexFlowTX, flags); ++ return 1; ++} ++#endif // #if EMAC_FLOW_CONTROL_TX ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC exit module ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_exit(struct platform_device *pdev) ++{ ++ struct net_device* emac_dev =(struct net_device*) platform_get_drvdata(pdev); ++ ++ if (emac_dev) ++ { ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ ++#if EMAC_FLOW_CONTROL_TX ++ // hemac->isPauseTX = 0; ++ del_timer(&hemac->timerFlowTX); ++#endif // #if EMAC_FLOW_CONTROL_TX ++ ++#ifndef CONFIG_SS_SWTOE ++#if REDUCE_CPU_FOR_RBNA ++ del_timer(&hemac->timerIntRX); ++#endif // #if REDUCE_CPU_FOR_RBNA ++#endif // #ifndef CONFIG_SS_SWTOE ++ ++#if KERNEL_PHY ++ MDev_EMAC_mii_uninit(emac_dev); ++#endif ++#ifndef CONFIG_SS_SWTOE ++ skb_queue_destroy(&(hemac->skb_queue_tx)); ++ free_rx_skb(hemac); ++ MDev_EMAC_RX_Desc_Free(hemac); ++#endif ++ MDev_EMAC_MemFree(hemac); ++ ++ MHal_EMAC_Free(hemac->hal); ++ unregister_netdev(emac_dev); ++ free_netdev(emac_dev); ++ } ++} ++ ++static int mstar_emac_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ // struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct net_device *netdev=(struct net_device*) platform_get_drvdata(dev); ++ struct emac_handle *hemac; ++ u32 uRegVal; ++ ++ if(!netdev) ++ { ++ return -1; ++ } ++ ++ hemac = (struct emac_handle*) netdev_priv(netdev); ++ hemac->ep_flag |= EP_FLAG_SUSPENDING; ++ //netif_stop_queue (netdev); ++ ++ ++ disable_irq(netdev->irq); ++ ++#if MSTAR_EMAC_NAPI ++ napi_disable(&hemac->napi); ++#endif ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_EMAC_Read_CTL(hemac->hal); ++ uRegVal &= ~(EMAC_TE | EMAC_RE); ++ MHal_EMAC_Write_CTL(hemac->hal, uRegVal); ++ ++ // Disable PHY interrupt // ++ MHal_EMAC_disable_phyirq(hemac->hal); ++ ++ // MHal_EMAC_Write_IDR(0xFFFFFFFF); ++ MHal_EMAC_IntEnable(hemac->hal, 0xFFFFFFFF, 0); ++ ++ MDev_EMAC_SwReset(netdev); ++ MHal_EMAC_Power_Off_Clk(hemac->hal, &dev->dev); ++#ifndef CONFIG_SS_SWTOE ++ skb_queue_reset(&(hemac->skb_queue_tx)); ++ disable_irq(netdev->irq); ++#endif ++ return 0; ++} ++ ++static int mstar_emac_drv_resume(struct platform_device *dev) ++{ ++ // struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct net_device *netdev=(struct net_device*) platform_get_drvdata(dev); ++ struct emac_handle *hemac; ++ unsigned long flags; ++ ++ if(!netdev) ++ { ++ return -1; ++ } ++ hemac = (struct emac_handle*) netdev_priv(netdev);; ++ hemac->ep_flag &= ~EP_FLAG_SUSPENDING; ++ ++ MHal_EMAC_Power_On_Clk(hemac->hal, &dev->dev); ++ ++ MHal_EMAC_Write_JULIAN_0100(hemac->hal, 0); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ ++ MDev_EMAC_HW_init(netdev); ++ ++ spin_lock_irqsave(&hemac->mutexPhy, flags); ++ MDev_EMAC_update_mac_address (netdev); // Program ethernet address into MAC // ++ MHal_EMAC_enable_mdi(hemac->hal); ++ spin_unlock_irqrestore(&hemac->mutexPhy, flags); ++ enable_irq(netdev->irq); ++ if(hemac->ep_flag & EP_FLAG_OPEND) ++ { ++ if(0>MDev_EMAC_open(netdev)) ++ { ++ // printk(KERN_WARNING "Driver Emac: open failed after resume\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int mstar_emac_drv_probe(struct platform_device *pdev) ++{ ++ int retval=0; ++ struct net_device* netdev; ++ struct emac_handle *hemac; ++ ++ if (!(pdev->name) || strcmp(pdev->name,"Sstar-emac") ++ || pdev->id!=0) ++ { ++ retval = -ENXIO; ++ } ++ ++ if ((retval = MDev_EMAC_init(pdev))) ++ return retval; ++ ++ netdev=(struct net_device*) platform_get_drvdata(pdev); ++ hemac = (struct emac_handle*) netdev_priv(netdev);; ++ ++ if(hemac->led_orange!=-1) ++ { ++ MDrv_GPIO_Pad_Set(hemac->led_orange); ++ } ++ if(hemac->led_green!=-1) ++ { ++ MDrv_GPIO_Pad_Set(hemac->led_green); ++ } ++ return retval; ++} ++ ++static int mstar_emac_drv_remove(struct platform_device *pdev) ++{ ++ struct net_device* emac_dev =(struct net_device*) platform_get_drvdata(pdev); ++ struct emac_handle *hemac = (struct emac_handle *) netdev_priv(emac_dev); ++ ++ if( !(pdev->name) || strcmp(pdev->name,"Sstar-emac") ++ || pdev->id!=0) ++ { ++ return -1; ++ } ++ MDev_EMAC_exit(pdev); ++ MHal_EMAC_Power_Off_Clk(hemac->hal, &pdev->dev); ++#if 0 ++ netif_napi_del(ð->tx_napi); ++ netif_napi_del(ð->rx_napi); ++ ++ netif_napi_add(emac_dev, &hemac->napi, MDev_EMAC_napi_poll, EMAC_NAPI_WEIGHT); ++ ++ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct emac_handle *hemac; ++ ++ printk(KERN_INFO "mstar_emac_drv_resume\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ hemac = (struct emac_handle*) netdev_priv(netdev);; ++ hemac->ep_flag &= ~EP_FLAG_SUSPENDING; ++#endif ++ platform_set_drvdata(pdev, NULL); ++ return 0; ++} ++ ++ ++ ++static struct platform_driver Mstar_emac_driver = { ++ .probe = mstar_emac_drv_probe, ++ .remove = mstar_emac_drv_remove, ++ .suspend = mstar_emac_drv_suspend, ++ .resume = mstar_emac_drv_resume, ++ ++ .driver = { ++ .name = "Sstar-emac", ++#if defined(CONFIG_OF) ++ .of_match_table = mstaremac_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_emac_drv_init_module(void) ++{ ++ int retval=0; ++ ++ retval = platform_driver_register(&Mstar_emac_driver); ++ if (retval) ++ { ++ // printk(KERN_INFO"Mstar_emac_driver register failed...\n"); ++ return retval; ++ } ++ ++ return retval; ++} ++ ++static void __exit mstar_emac_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_emac_driver); ++ // emac_dev=NULL; ++} ++ ++module_init(mstar_emac_drv_init_module); ++module_exit(mstar_emac_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("EMAC Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/emac_toe/mdrv_emac.h b/drivers/sstar/emac_toe/mdrv_emac.h +new file mode 100755 +index 000000000000..624bf5b0adf1 +--- /dev/null ++++ b/drivers/sstar/emac_toe/mdrv_emac.h +@@ -0,0 +1,312 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_emac.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __DRV_EMAC_H_ ++#define __DRV_EMAC_H_ ++ ++#define EMAC_DBG(fmt, args...) //{printk("Sstar_emac: "); printk(fmt, ##args);} ++#define EMAC_ERR(fmt, args...) {printk("Sstar_emac: "); printk(fmt, ##args);} ++#define EMAC_INFO {printk("Line:%u\n", __LINE__);} ++#define EMAC_TODO(fmt, args...) {printk("[EMAC]%d TODO:", __LINE__); printk(fmt, ##args);} ++ ++#define MINOR_EMAC_NUM 1 ++#define MAJOR_EMAC_NUM 241 ++ ++#define EXT_PHY_PATCH 1 ++ ++///////////////////////////////// ++// to be refined ++///////////////////////////////// ++ ++#define EMAC_SG 1 ++#define EMAC_SG_BDMA 0 ++#define EMAC_SG_BUF_CACHE 1 ++ ++#define EMAC_GSO 1 ++ ++// #define DYNAMIC_INT_TX_TH 64 ++#define DYNAMIC_INT_TX 1 ++ ++#define DYNAMIC_INT_RX 1 ++#ifdef CONFIG_SS_SWTOE ++#define REDUCE_CPU_FOR_RBNA 0 ++#else ++#define REDUCE_CPU_FOR_RBNA 1 ++#endif ++ ++ ++#ifdef CONFIG_SS_SWTOE ++ ++ #define MSTAR_EMAC_NAPI 0 ++ ++ #define EMAC_FLOW_CONTROL_RX 0 ++ #define EMAC_FLOW_CONTROL_RX_TEST 0 ++ ++ #define EMAC_FLOW_CONTROL_TX 0 ++ #define EMAC_FLOW_CONTROL_TX_TEST 0 ++ #define EMAC_FLOW_CONTROL_TX_TEST_TIME 0x200 ++ ++#else ++ ++ #define MSTAR_EMAC_NAPI 1 ++ #define EMAC_FLOW_CONTROL_RX 1 ++ #define EMAC_FLOW_CONTROL_RX_TEST 0 ++ ++ #define EMAC_FLOW_CONTROL_TX 1 ++ #define EMAC_FLOW_CONTROL_TX_TEST 0 ++ #define EMAC_FLOW_CONTROL_TX_TEST_TIME 0x200 ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define EMAC_MTU (1524) ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++// #define DRV_EMAC_MAX_DEV 0x1 ++ ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++/* ++phys_addr_t RAM_VA_BASE; //= 0x00000000; // After init, RAM_ADDR_BASE = EMAC_ABSO_MEM_BASE ++phys_addr_t RAM_PA_BASE; ++phys_addr_t RAM_VA_PA_OFFSET; ++phys_addr_t RBQP_BASE; //= RX_BUFFER_SIZE;//0x00004000; // IMPORTANT: lowest 13 bits as zero. ++*/ ++ ++#define ETHERNET_TEST_NO_LINK 0x00000000UL ++#define ETHERNET_TEST_AUTO_NEGOTIATION 0x00000001UL ++#define ETHERNET_TEST_LINK_SUCCESS 0x00000002UL ++#define ETHERNET_TEST_RESET_STATE 0x00000003UL ++#define ETHERNET_TEST_SPEED_100M 0x00000004UL ++#define ETHERNET_TEST_DUPLEX_FULL 0x00000008UL ++#define ETHERNET_TEST_INIT_FAIL 0x00000010UL ++ ++u8 MY_DEV[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; ++u8 MY_MAC[6] = { 0x00UL, 0x30UL, 0x1BUL, 0xBAUL, 0x02UL, 0xDBUL }; ++u8 PC_MAC[6] = { 0x00UL, 0x1AUL, 0x4BUL, 0x5CUL, 0x39UL, 0xDFUL }; ++u8 ETH_PAUSE_FRAME_DA_MAC[6] = { 0x01UL, 0x80UL, 0xC2UL, 0x00UL, 0x00UL, 0x01UL }; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct rbf_t ++{ ++ u32 addr; ++ u32 size; ++} __attribute__ ((packed)); ++ ++#define EP_FLAG_OPEND 0X00000001UL ++#define EP_FLAG_SUSPENDING 0X00000002UL ++ ++typedef struct ++{ ++ // u8 used; ++ struct sk_buff* skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_phys; /* phys addr from pci_map_single */ ++ int skb_len; ++} skb_info; ++ ++typedef struct ++{ ++ skb_info* skb_info_arr; ++ int read; ++ int write; ++ int rw; ++ int size[2]; ++} skb_queue; ++ ++#ifndef CONFIG_SS_SWTOE ++typedef struct ++{ ++ // int off_va_pa; ++ // skb_queue skb_queue_rx; ++ struct rbf_t* desc; ++ // dma_addr_t descPhys; ++ struct sk_buff** skb_arr; ++ int num_desc; ++ int size_desc_queue; ++ int idx; ++} rx_desc_queue_t; ++#endif ++ ++struct emac_handle ++{ ++ struct net_device_stats stats; ++ ++ spinlock_t mutexNetIf; ++ spinlock_t mutexTXQ; // spin_lock_bh¡]¡^ÉOspin_unlock_bh¡]¡^ ++ spinlock_t mutexPhy; ++ ++ /* Transmit */ ++ skb_queue skb_queue_tx; ++ ++ unsigned int irqcnt; ++ unsigned int tx_irqcnt; ++ ++ /* Receive */ ++ // spinlock_t mutexRXD; ++#ifdef CONFIG_SS_SWTOE ++ int cnx_id; ++ struct work_struct rx_work; ++#else ++ rx_desc_queue_t rx_desc_queue; ++#endif ++ ++#if EXT_PHY_PATCH ++ char* pu8RXBuf; ++#endif ++ ++ /* Suspend and resume */ ++ unsigned long ep_flag; ++ ++ struct net_device *netdev; ++ ++ struct device *mstar_class_emac_device; ++#if MSTAR_EMAC_NAPI ++ struct napi_struct napi; ++#else ++ spinlock_t mutexRXInt; ++#endif ++ MSYS_DMEM_INFO mem_info; ++ ++ u32 txd_num; ++ u32 txq_num_sw; ++ ++ // led gpio ++ int led_orange; ++ int led_green; ++ int led_count; ++ int led_flick_speed; ++ ++ // mac address ++ u8 sa[4][6]; ++ ++ // BasicConfigEMAC ThisBCE; ++ // UtilityVarsEMAC ThisUVE; ++ ++ // struct timer_list timer_link; ++ ++ // ++ unsigned int irq_emac; ++ unsigned int irq_lan; ++ ++ // ++ u32 emacRIU; ++ u32 emacX32; ++ u32 phyRIU; ++ ++ // ++ u32 pad_reg; ++ u32 pad_msk; ++ u32 pad_val; ++ ++ u32 phy_mode; ++ ++ // led ++ u32 pad_led_reg; ++ u32 pad_led_msk; ++ u32 pad_led_val; ++ ++ // hal handle ++ void* hal; ++ ++ //////////////// ++ u32 gu32intrEnable; ++ u32 irq_count[32]; ++ ++ u32 skb_tx_send; ++ u32 skb_tx_free; ++ u64 data_done; ++ struct timespec data_time_last; ++ spinlock_t emac_data_done_lock; ++ ++ u32 txPkt; ++ u32 txInt; ++ ++ u32 initstate; ++ u32 contiROVR; ++ unsigned long oldTime; ++ unsigned long PreLinkStatus; ++ ++ // ++ const char* name; ++ u8 bInit; ++ u8 bEthCfg; ++ ++ u8 u8Minor; ++ ++#if KERNEL_PHY ++ /// phy separation ++ struct mii_bus* mii_bus; ++ struct device* dev; // don't know its useness ++#endif ++ ++#if 0 ++ // not sure about its use ++ u32 gu32PhyResetCount1; ++ u32 gu32PhyResetCount2; ++ u32 gu32PhyResetCount3; ++ u32 gu32PhyResetCount4; ++ u32 gu32PhyResetCount; ++#endif ++ ++ ++#if EMAC_FLOW_CONTROL_TX ++ // TX pause packet (TX flow control) ++ spinlock_t mutexFlowTX; ++ struct timer_list timerFlowTX; ++ // int isPauseTX; ++#endif ++ ++#if EMAC_FLOW_CONTROL_RX ++ // RX pause packet (TX flow control) ++ u8* pu8PausePkt; ++ u8 u8PausePktSize; ++ u8 isPausePkt; ++#endif ++ ++#if REDUCE_CPU_FOR_RBNA ++ spinlock_t mutexIntRX; ++ struct timer_list timerIntRX; ++#endif ++ ++#if DYNAMIC_INT_RX ++ struct timespec rx_stats_time; ++ u32 rx_stats_packet; ++ u8 rx_stats_enable; ++#endif ++ ++#if EMAC_SG ++ // char* pTxBuf; ++ // int TxBufIdx; ++ int maxSG; ++#endif // #if EMAC_SG ++ ++}; ++ ++#endif ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h End ++// ----------------------------------------------------------------------------- ++ ++ +diff --git a/drivers/sstar/emac_toe/policy.txt b/drivers/sstar/emac_toe/policy.txt +new file mode 100755 +index 000000000000..f06bedd4b51f +--- /dev/null ++++ b/drivers/sstar/emac_toe/policy.txt +@@ -0,0 +1,45 @@ ++//////////////////////////////////////////// ++// What kind of test before release ++//////////////////////////////////////////// ++ ++A. Auto detection for different speed and duplex ++ 1. 10Mb Full ++ 2. 10Mb Half ++ 3. 100Mb Full ++ 4. 100Mb Half ++ ++B. Data Transfer Rate with different speed and duplex ++ 1. 10Mb Half ++ 1.1 64-byte icmp packet: greater than 7.6Mb ++ 1.2 128-byte icmp packet: greater than 7.6Mb ++ 1.3 256-byte icmp packet: greater than 7.6Mb ++ 1.4 512-byte icmp packet: greater than 7.6Mb ++ 1.5 1024-byte icmp packet: greater than 7.6Mb ++ 1.6 1280-byte icmp packet: greater than 7.6Mb ++ 1.7 1514-byte icmp packet: greater than 7.6Mb ++ 2. 10Mb Full ++ 2.1 64-byte icmp packet: greater than 7.6Mb ++ 2.2 128-byte icmp packet: greater than 7.6Mb ++ 2.3 256-byte icmp packet: greater than 7.6Mb ++ 2.4 512-byte icmp packet: greater than 7.6Mb ++ 2.5 1024-byte icmp packet: greater than 7.6Mb ++ 2.6 1280-byte icmp packet: greater than 7.6Mb ++ 2.7 1514-byte icmp packet: greater than 7.6Mb ++ 3. 100Mb Half ++ 3.1 64-byte icmp packet: greater than 7.6Mb ++ 3.2 128-byte icmp packet: greater than 10Mb ++ 3.3 256-byte icmp packet: greater than 15Mb ++ 3.4 512-byte icmp packet: greater than 30Mb ++ 3.5 1024-byte icmp packet: greater than 50Mb ++ 3.6 1280-byte icmp packet: greater than 55Mb ++ 3.7 1514-byte icmp packet: greater than 60Mb ++ 4. 100Mb Full ++ 4.1 64-byte icmp packet: greater than 7.6Mb ++ 4.2 128-byte icmp packet: greater than 10Mb ++ 4.3 256-byte icmp packet: greater than 15Mb ++ 4.4 512-byte icmp packet: greater than 30Mb ++ 4.5 1024-byte icmp packet: greater than 50Mb ++ 4.6 1280-byte icmp packet: greater than 55Mb ++ 4.7 1514-byte icmp packet: greater than 60Mb ++ ++ +\ No newline at end of file +diff --git a/drivers/sstar/emmc/Kconfig b/drivers/sstar/emmc/Kconfig +new file mode 100755 +index 000000000000..e0e0ab8e9110 +--- /dev/null ++++ b/drivers/sstar/emmc/Kconfig +@@ -0,0 +1,9 @@ ++config MS_EMMC ++ tristate "EMMC driver" ++ depends on MMC ++ help ++ To enable MSTAR EMMC driver. ++ ++config MS_EMMC_UNIFY_DRIVER ++ bool "UNIFY EMMC DRIVER" ++ depends on MS_EMMC +diff --git a/drivers/sstar/emmc/Makefile b/drivers/sstar/emmc/Makefile +new file mode 100755 +index 000000000000..5591294ac8c0 +--- /dev/null ++++ b/drivers/sstar/emmc/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MS_EMMC_UNIFY_DRIVER) += unify_driver/ +diff --git a/drivers/sstar/emmc/unify_driver/Makefile b/drivers/sstar/emmc/unify_driver/Makefile +new file mode 100755 +index 000000000000..dadd50c48016 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/Makefile +@@ -0,0 +1,27 @@ ++# ++# Makefile for MStar eMMC host drivers. ++# ++obj-$(CONFIG_MS_EMMC) += kdrv_emmc.o ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/emmc/unify_driver/inc/api/ ++EXTRA_CFLAGS += -Idrivers/sstar/emmc/unify_driver/inc/common/ ++EXTRA_CFLAGS += -Idrivers/sstar/emmc/unify_driver/inc/config/ ++EXTRA_CFLAGS += -Idrivers/sstar/emmc/unify_driver/inc/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ifndef CONFIG_ARM_LPAE ++#EXTRA_CFLAGS += -Werror ++endif ++ ++# specific options ++ ++# files ++kdrv_emmc-y += src/api/eMMC_prg.o ++kdrv_emmc-y += src/common/eMMC_hal_speed.o ++kdrv_emmc-y += src/common/eMMC_hal_v5.o ++kdrv_emmc-y += mstar_mci_v5.o ++ ++kdrv_emmc-y += src/common/eMMC_ip_verify.o ++kdrv_emmc-y += src/common/eMMC_utl.o ++kdrv_emmc-y += src/config/eMMC_platform.o ++ +diff --git a/drivers/sstar/emmc/unify_driver/inc/api/drv_eMMC.h b/drivers/sstar/emmc/unify_driver/inc/api/drv_eMMC.h +new file mode 100755 +index 000000000000..dc77e3a9f61e +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/api/drv_eMMC.h +@@ -0,0 +1,125 @@ ++/* ++* drv_eMMC.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __DRV_eMMC_H__ ++#define __DRV_eMMC_H__ ++ ++ ++/*=============================================================*/ ++// Include files ++/*=============================================================*/ ++#include "../config/eMMC_config.h" ++ ++/*=============================================================*/ ++// Extern definition ++/*=============================================================*/ ++typedef struct _eMMC_INFO ++{ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ ++ U16 u16_ECCCodeByteCnt; ++ U16 u16_PageSectorCnt; ++ U8 u8_WordMode; ++ ++} eMMC_INFO_t; ++ ++typedef struct _eMMC_CIS { ++ ++ U8 au8_eMMC_nni[512]; ++ U8 au8_eMMC_pni[512]; ++ ++} eMMC_CIS_t; ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Variable definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++extern U32 eMMC_Init(void); ++extern U32 eMMC_Init_Device(void); ++extern U32 eMMC_Init_Device_Ex(void); ++extern U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt); ++//-------------------------------------------- ++// CAUTION: u32_DataByteCnt has to be 512B x n ++//-------------------------------------------- ++extern U32 eMMC_WriteData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_ReadData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++// skip driver-reserved area ++extern U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_GetCapacity(U32 *pu32_TotalSectorCnt); // 1 sector = 512B ++extern U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++//-------------------------------------------- ++extern U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID); ++ ++extern U32 eMMC_EraseAll(void); ++ ++extern U32 eMMC_GetExtCSD(U8* pu8_Ext_CSD); ++extern U32 eMMC_SetExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++ ++/*=============================================================*/ ++// internal function definition ++/*=============================================================*/ ++extern U32 eMMC_ReadBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo); ++extern U32 eMMC_CheckIfReady(void); ++extern void eMMC_ResetReadyFlag(void); ++extern void eMMC_DumpDriverStatus(void); ++extern void eMMC_DumpSpeedStatus(void); ++extern U32 eMMC_FCIE_BuildDDRTimingTable(void); ++extern U32 eMMC_FCIE_BuildHS200TimingTable(void); ++extern void eMMC_FCIE_SetSkew4Value(U32 u32Value); ++extern void eMMC_FCIE_SetDelayLatch(U32 u32Value); ++extern U32 eMMC_SetEnhanceUserPartition(U32 u32_StartAddr,U32 u32_Size,U8 u8_EnAttr, U8 u8_RelW); ++extern U32 eMMC_SetGPPartition(U8 u8_PartNo,U32 u32_PartSize,U8 u8_EnAttr,U8 u8_ExtAttr, U8 u8_RelW); ++extern U32 eMMC_SetPartitionComplete(void); ++extern U32 eMMC_ReadGPPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_WriteGPPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern void eMMC_PrintGPPartition(void); ++ ++//-------------------------------------------- ++ #if defined(eMMC_DRV_G2P_UBOOT) && eMMC_DRV_G2P_UBOOT ++extern U32 eMMC_SearchDevNodeStartSector(void); ++ #endif ++//-------------------------------------------- ++ ++#endif //__DRV_eMMC_H__ ++ +diff --git a/drivers/sstar/emmc/unify_driver/inc/common/eMMC.h b/drivers/sstar/emmc/unify_driver/inc/common/eMMC.h +new file mode 100755 +index 000000000000..1811814f8781 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/common/eMMC.h +@@ -0,0 +1,495 @@ ++/* ++* eMMC.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef eMMC_DRIVER_H ++#define eMMC_DRIVER_H ++ ++//===================================================================================== ++#include "../config/eMMC_config.h" // [CAUTION]: edit eMMC_config.h for your platform ++//===================================================================================== ++#include "eMMC_err_codes.h" ++ ++#define eMMC_DRIVER_VERSION 3 // used to sync with other SW stages (e.g. MBoot) ++ ++//=========================================================== ++// debug macro ++//=========================================================== ++extern U32 gu32_eMMCDrvExtFlag; ++ ++#define eMMCDRV_EXTFLAG_DISABLE_LOG BIT0 ++#define eMMC_DISABLE_LOG(yes) \ ++ do{ \ ++ if(yes) gu32_eMMCDrvExtFlag |= eMMCDRV_EXTFLAG_DISABLE_LOG; \ ++ else gu32_eMMCDrvExtFlag &= ~eMMCDRV_EXTFLAG_DISABLE_LOG;\ ++ }while(0); ++#define eMMC_IF_DISABLE_LOG() \ ++ (gu32_eMMCDrvExtFlag & eMMCDRV_EXTFLAG_DISABLE_LOG) ++ ++#define eMMCDRV_EXTFLAG_BKG_SCAN BIT1 // for Irwin ++#define eMMC_SET_BKG_SCAN_HS200() gu32_eMMCDrvExtFlag |= eMMCDRV_EXTFLAG_BKG_SCAN; ++#define eMMC_CLR_BKG_SCAN_HS200() gu32_eMMCDrvExtFlag &= ~eMMCDRV_EXTFLAG_BKG_SCAN; ++#define eMMC_CHK_BKG_SCAN_HS200() (gu32_eMMCDrvExtFlag & eMMCDRV_EXTFLAG_BKG_SCAN) ++ ++ ++//=========================================================== ++// macro for Spec. ++//=========================================================== ++#define ADDRESSING_MODE_BYTE 1 // 1 byte ++#define ADDRESSING_MODE_SECTOR 2 // 512 bytes ++#define ADDRESSING_MODE_4KB 3 // 4KB bytes ++ ++#define eMMC_DEVTYPE_HS400_1_8V BIT6 // ECSD[196] ++#define eMMC_DEVTYPE_HS200_1_8V BIT4 ++#define eMMC_DEVTYPE_DDR BIT2 ++#define eMMC_DEVTYPE_ALL (eMMC_DEVTYPE_HS400_1_8V|eMMC_DEVTYPE_HS200_1_8V|eMMC_DEVTYPE_DDR) ++ ++#define eMMC_SPEED_OLD 0 // ECSD[185] ++#define eMMC_SPEED_HIGH 1 ++#define eMMC_SPEED_HS200 2 ++#define eMMC_SPEED_HS400 3 ++ ++#define eMMC_DRIVING_TYPE0 0 // x1 ++#define eMMC_DRIVING_TYPE1 1 // x1.5 ++#define eMMC_DRIVING_TYPE2 2 // x0.75 ++#define eMMC_DRIVING_TYPE3 3 // x0.5 ++#define eMMC_DRIVING_TYPE4 4 // x1.2 ++ ++#define eMMC_FLAG_TRIM BIT0 ++#define eMMC_FLAG_HPI_CMD12 BIT1 ++#define eMMC_FLAG_HPI_CMD13 BIT2 ++ ++#define eMMC_PwrOffNotif_OFF 0 ++#define eMMC_PwrOffNotif_ON 1 ++#define eMMC_PwrOffNotif_SHORT 2 ++#define eMMC_PwrOffNotif_LONG 3 ++ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTE 0x200 ++#define eMMC_SECTOR_512BYTE_BITS 9 ++#define eMMC_SECTOR_512BYTE_MASK (eMMC_SECTOR_512BYTE-1) ++ ++#define eMMC_SECTOR_BUF_16KB (eMMC_SECTOR_512BYTE * 0x20) ++ ++#define eMMC_SECTOR_BYTECNT eMMC_SECTOR_512BYTE ++#define eMMC_SECTOR_BYTECNT_BITS eMMC_SECTOR_512BYTE_BITS ++//------------------------------------------------------- ++ ++#define eMMC_ExtCSD_SetBit 1 ++#define eMMC_ExtCSD_ClrBit 2 ++#define eMMC_ExtCSD_WByte 3 ++ ++#define eMMC_CMD_BYTE_CNT 5 ++#define eMMC_R1_BYTE_CNT 5 ++#define eMMC_R1b_BYTE_CNT 5 ++#define eMMC_R2_BYTE_CNT 16 ++#define eMMC_R3_BYTE_CNT 5 ++#define eMMC_R4_BYTE_CNT 5 ++#define eMMC_R5_BYTE_CNT 5 ++#define eMMC_MAX_RSP_BYTE_CNT eMMC_R2_BYTE_CNT ++ ++//=========================================================== ++// Partition Info parameters ++//=========================================================== ++ ++// internal data Sector Address ++#define eMMC_ID_BYTE_CNT 15 ++#define eMMC_ID_FROM_CID_BYTE_CNT 10 ++#define eMMC_ID_DEFAULT_BYTE_CNT 11 // last byte means n GB ++ ++typedef eMMC_PACK0 struct _eMMC_NNI { ++ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 au8_padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ U8 u8_PairPageMapLoc; ++ U8 u8_PairPageMapType; ++ ++} eMMC_PACK1 eMMC_NNI_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PARTITION_RECORD { ++ ++ U16 u16_StartBlk; // the start block index, reserved for UNFD internal use. ++ U16 u16_BlkCnt; // project team defined ++ U16 u16_PartType; // project team defined, e.g. eMMC_PART_XXX_0 ++ U16 u16_BackupBlkCnt; // reserved good blocks count for backup, UNFD internal use. ++ // e.g. u16BackupBlkCnt = u16BlkCnt * 0.03 + 2 ++} eMMC_PACK1 eMMC_PARTITION_RECORD_t, *P_eMMC_PARTITION_RECORD_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PNI { ++ ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U16 u16_PartCnt; ++ U16 u16_UnitByteCnt; ++ eMMC_PARTITION_RECORD_t records[]; ++ ++} eMMC_PACK1 eMMC_PNI_t; ++ ++ ++// Logical Disk Info ++typedef struct _eMMC_DISK_INFO { ++ ++ U32 u32_StartSector; ++ U32 u32_SectorCnt; ++ ++} eMMC_DISK_INFO_t, *P_eMMC_DISK_INFO_t; ++ ++//=========================================================== ++// DDR Timing Table ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_PARAM { ++ ++ U8 u8_DQS, u8_Cell; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_PARAM_t; ++ ++#if 0 ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_WINDOW { ++ ++ U8 u8_Cnt; ++ // DQS uses index, not reg value (see code) ++ eMMC_FCIE_DDRT_PARAM_t aParam[2]; ++ U8 au8_DQSTryCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MODE_SHIFT)+1]; ++ U8 au8_DQSValidCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MODE_SHIFT)+1]; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_WINDOW_t; ++#endif ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_SET { ++ ++ U8 u8_Clk; ++ eMMC_FCIE_DDRT_PARAM_t Param; // register values ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_SET_t; ++ ++ ++#define eMMC_FCIE_DDRT_SET_CNT 12 ++ ++#define eMMC_TIMING_SET_MAX 0 ++#define eMMC_TIMING_SET_MIN 1 ++ ++// ---------------------------------------------- ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_TABLE { ++ ++ U8 u8_SetCnt, u8_CurSetIdx; ++ ++ #if !(defined(ENABLE_eMMC_ATOP) && ENABLE_eMMC_ATOP) ++ // DDR48 (digital macro) ++ eMMC_FCIE_DDRT_SET_t Set[eMMC_FCIE_DDRT_SET_CNT]; ++ #else ++ // ATOP (for DDR52, HS200, HS400) ++ eMMC_FCIE_ATOP_SET_t Set[1];//eMMC_FCIE_VALID_CLK_CNT]; ++ #endif ++ ++ U32 u32_ChkSum; // put in the last ++ U32 u32_VerNo; // for auto update ++ ++} eMMC_PACK1 eMMC_FCIE_TIMING_TABLE_t; ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_EXT_TABLE { //temp solution for monaco U02 HS400 ++ eMMC_FCIE_ATOP_SET_EXT_t Set; ++ U32 u32_ChkSum; // put in the last ++ U32 u32_VerNo; // for auto update ++} eMMC_PACK1 eMMC_FCIE_TIMING_EXT_TABLE_t; ++ ++#define REG_OP_W 1 ++#define REG_OP_CLRBIT 2 ++#define REG_OP_SETBIT 3 ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_REG_SET { //total 10 bytes ++ U32 u32_RegAddress; //(BANK_ADDRESS + REGISTER OFFSET ) << 2 ++ U16 u16_RegValue; ++ U16 u16_RegMask; ++ U16 u16_OpCode; ++} eMMC_PACK1 eMMC_FCIE_REG_SET_t; ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_GEN_TIMING_TABLE { ++ U32 u32_ChkSum; ++ U32 u32_VerNo; // for auto update ++ U32 u32_Clk; ++ U8 u8_SpeedMode; ++ U8 u8_CurSetIdx; ++ U8 u8_RegisterCnt; ++ U8 u8_SetCnt; ++ U8 au8_CID[eMMC_MAX_RSP_BYTE_CNT]; ++ U32 u32_Dummy[6]; //for extension ++ eMMC_FCIE_REG_SET_t RegSet[45]; //at most 45 register set ++} eMMC_PACK1 eMMC_FCIE_GEN_TIMING_TABLE_t; ++ ++#if defined(CONFIG_EMMC_FORCE_DDR52) ++#define eMMC_TIMING_TABLE_VERSION 2 ++#else ++#define eMMC_TIMING_TABLE_VERSION 4 // for CL.731742 & later ++#endif ++#define eMMC_TIMING_TABLE_CHKSUM_OFFSET 8 ++ ++//=========================================================== ++// burst length for write speed ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_FCIE_WLen_TABLE { ++ ++ U16 u16_BestBrustLen, u16_WorstBrustLen; ++ ++ U16 u16_BestMBPerSec, u16_BestMBPerSecPoint; ++ U16 u16_WorstMBPerSec, u16_WorstMBPerSecPoint; ++ ++ U32 u32_ChkSum; // put in the last ++ ++} eMMC_PACK1 eMMC_FCIE_WLen_TABLE_t; ++ ++//=========================================================== ++// Gernel Purpose Partition ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_GP_Part{ ++ U32 u32_PartSize; ++ U8 u8_EnAttr; ++ U8 u8_ExtAttr; ++ U8 u8_RelW; ++} eMMC_PACK1 eMMC_GP_Part_t; ++ ++//=========================================================== ++// driver flag (u32_DrvFlag) ++//=========================================================== ++#define DRV_FLAG_INIT_DONE BIT0 // include eMMC identify done ++ ++#define DRV_FLAG_GET_PART_INFO BIT1 ++#define DRV_FLAG_RSP_WAIT_D0H BIT2 // currently only R1b ++ ++#define DRV_FLAG_DDR_MODE BIT3 ++#define DRV_FLAG_TUNING_TTABLE BIT4 // to avoid retry & heavy log ++#define DRV_FLAG_SPEED_MASK (BIT7|BIT6|BIT5) ++#define DRV_FLAG_SPEED_HIGH BIT5 ++#define DRV_FLAG_SPEED_HS200 BIT6 ++#define DRV_FLAG_SPEED_HS400 BIT7 ++#define eMMC_IF_NORMAL_SDR() (0==(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)&&\ ++ DRV_FLAG_SPEED_HIGH==(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_MASK)) ++#define eMMC_SPEED_MODE() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_MASK) ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_TUNING_TTABLE) ++ ++#define DRV_FLAG_PwrOffNotif_MASK (BIT8|BIT9) ++#define DRV_FLAG_PwrOffNotif_OFF 0 ++#define DRV_FLAG_PwrOffNotif_ON BIT8 ++#define DRV_FLAG_PwrOffNotif_SHORT BIT9 ++#define DRV_FLAG_PwrOffNotif_LONG (BIT8|BIT9) ++ ++#define DRV_FLAG_RSPFROMRAM_SAVE BIT10 ++#define DRV_FLAG_ERROR_RETRY BIT11 ++ ++typedef struct _eMMC_DRIVER ++{ ++ U32 u32_ChkSum; // [8th ~ last-512] bytes ++ U8 au8_Sig[4]; // 'e','M','M','C' ++ ++ // ---------------------------------------- ++ // Config from DTS ++ // ---------------------------------------- ++ U16 u16_of_buswidth; ++ ++ // ---------------------------------------- ++ // FCIE ++ // ---------------------------------------- ++ U16 u16_RCA; ++ U32 u32_DrvFlag, u32_LastErrCode; ++ U8 au8_Rsp[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CSD[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CID[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 u8_PadType; ++ U16 u16_Reg10_Mode; ++ U32 u32_ClkKHz; ++ U16 u16_ClkRegVal; ++ eMMC_FCIE_TIMING_TABLE_t TimingTable_t; ++ eMMC_FCIE_TIMING_EXT_TABLE_t TimingTable_Ext_t; ++ eMMC_FCIE_GEN_TIMING_TABLE_t TimingTable_G_t; ++ ++ // ---------------------------------------- ++ // eMMC ++ // ---------------------------------------- ++ // CSD ++ U8 u8_SPEC_VERS; ++ U8 u8_R_BL_LEN, u8_W_BL_LEN; // supported max blk len ++ U16 u16_C_SIZE; ++ U8 u8_TAAC, u8_NSAC, u8_Tran_Speed; ++ U8 u8_C_SIZE_MULT; ++ U8 u8_ERASE_GRP_SIZE, u8_ERASE_GRP_MULT; ++ U8 u8_R2W_FACTOR; ++ ++ U8 u8_IfSectorMode; ++ U32 u32_eMMCFlag; ++ U32 u32_EraseUnitSize; ++ ++ // ExtCSD ++ U32 u32_SEC_COUNT; ++ U32 u32_BOOT_SEC_COUNT; ++ ++ #define BUS_WIDTH_1 1 ++ #define BUS_WIDTH_4 4 ++ #define BUS_WIDTH_8 8 ++ ++ U8 u8_BUS_WIDTH; ++ U8 u8_ErasedMemContent; ++ U16 u16_ReliableWBlkCnt; ++ U8 u8_ECSD185_HsTiming, u8_ECSD192_Ver, u8_ECSD196_DevType, u8_ECSD197_DriverStrength; ++ U8 u8_ECSD248_CMD6TO, u8_ECSD247_PwrOffLongTO, u8_ECSD34_PwrOffCtrl; ++ U8 u8_ECSD160_PartSupField, u8_ECSD224_HCEraseGRPSize, u8_ECSD221_HCWpGRPSize; ++ U8 u8_ECSD159_MaxEnhSize_2, u8_ECSD158_MaxEnhSize_1, u8_ECSD157_MaxEnhSize_0; ++ U8 u8_u8_ECSD155_PartSetComplete, u8_ECSD166_WrRelParam; ++ U8 u8_ECSD184_Stroe_Support; ++ ++ // ---------------------------------------- ++ // CIS ++ // ---------------------------------------- ++ // nni ++ U8 u8_IDByteCnt, au8_ID[eMMC_ID_BYTE_CNT]; ++ U8 au8_Vendor[16], au8_PartNumber[16]; ++ ++ // pni ++ U32 au32_Pad[2]; // don't move ++ ++ U32 u32_PartDevNodeStartSector; ++ U16 u16_PartDevNodeSectorCnt; ++ U32 u32_FATSectorCnt; ++ ++ // ---------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ // rsp from ram ++ U8 au8_AllRsp[eMMC_SECTOR_512BYTE]; // last 4 bytes are CRC ++ #endif ++ ++ // ---------------------- ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ eMMC_FCIE_WLen_TABLE_t BurstWriteLen_t; ++ #endif ++ ++ // ---------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ U32 u32_CNT_CMD17, u32_CNT_CMD24, u32_CNT_CMD18, u32_CNT_CMD25; ++ U64 u64_CNT_TotalRBlk, u64_CNT_TotalWBlk; ++ ++ U32 u32_CNT_MinRBlk, u32_CNT_MinWBlk, u32_CNT_MaxRBlk, u32_CNT_MaxWBlk; ++ U32 u32_RBlk_tmp, u32_WBlk_tmp; ++ U32 au32_CNT_MinRBlk[0x200], au32_CNT_MinWBlk[0x200]; // for blk count < 0x200, how many times ++ ++ U32 u32_Addr_RLast, u32_Addr_WLast; ++ U32 u32_Addr_RHitCnt, u32_Addr_WHitCnt; ++ ++ U32 u32_temp_count; ++ #endif ++ ++ eMMC_GP_Part_t GP_Part[4]; ++ ++ U32 u32_EnUserStartAddr; ++ U32 u32_EnUserSize; ++ U8 u8_EnUserEnAttr; ++ U8 u8_EnUserRelW; ++ ++ //FCIE5 ++ ++ U16 u16_MacroToggleCnt; ++ U16 u16_EmmcPll_IOBusWidth; ++ U16 u16_EmmcPll_DqsPageByteCnt; ++ U8 u8_MacroType; ++ U8 u8_DefaultBusMode; ++ U8 u8_HS400_mode; ++ ++ // misc ++ U8 u8_disable_retry; ++ ++ U8 u8_make_sts_err; ++ ++ #define FCIE_NOT_MAKE_ERR 0 ++ #define FCIE_MAKE_RD_CRC_ERR 1 ++ #define FCIE_MAKE_WR_CRC_ERR 2 ++ #define FCIE_MAKE_WR_TOUT_ERR 3 ++ #define FCIE_MAKE_CMD_NO_RSP 4 ++ #define FCIE_MAKE_CMD_RSP_ERR 5 ++ #define FCIE_MAKE_RD_TOUT_ERR 6 ++ #define FCIE_MAKE_CARD_BUSY 7 ++ ++ U8 u8_check_last_blk_crc; ++ ++} eMMC_DRIVER, *P_eMMC_DRIVER; ++ ++extern eMMC_DRIVER g_eMMCDrv; ++ ++// ADMA Descriptor ++struct _AdmaDescriptor{ ++ U32 u32_End : 1; ++ U32 u32_MiuSel : 2; ++ U32 : 13; ++ U32 u32_JobCnt : 16; ++ U32 u32_Address; ++ U32 u32_DmaLen; ++ U32 u32_Dummy; ++}; ++ ++//=========================================================== ++// exposed APIs ++//=========================================================== ++#include "../api/drv_eMMC.h" ++ ++//=========================================================== ++// internal used functions ++//=========================================================== ++#include "eMMC_utl.h" ++#include "eMMC_hal.h" ++ ++extern U32 eMMC_IPVerify_Main(void); ++extern U32 eMMC_IPVerify_Main_Ex(U32 u32_DataPattern); ++#define eMMC_TEST_READONLY 1 ++#define eMMC_TEST_WRITEONLY 2 ++extern U32 eMMC_IPVerify_WriteOnly(U16 u16_TestPattern); ++extern U32 eMMC_IPVerify_ReadOnly(void); ++extern U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void); ++extern void eMMCTest_DownCount(U32 u32_Sec); ++extern U32 eMMC_IPVerify_Performance(void); ++extern U32 eMMCTest_BlkWRC_ProbeTiming(U32 u32_eMMC_Addr); ++extern U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt); ++extern U32 eMMCTest_Lifetime(U8 u8_TestMode); ++extern U32 eMMCTest_PwrCut_InitData(U8* u8_DataBuf, U32 u32_BlkStartAddr); ++extern U32 eMMCTest_PwrCut_Test(U8* u8_DataBuf, U32 u32_BlkStartAddr); ++extern U32 eMMCTest_PwrCut_Test2(U8* u8_DataBuf, U32 u32_BlkStartAddr); ++//power cut ++extern void eMMC_CheckPowerCut(void); ++extern void eMMC_Prepare_Power_Saving_Mode_Queue(void); ++ ++#define eMMC_LIFETIME_TEST_FIXED 1 ++#define eMMC_LIFETIME_TEST_FILLED 2 ++#define eMMC_LIFETIME_TEST_RANDOM 3 ++ ++extern U32 eMMC_BootMode(void); ++#endif // eMMC_DRIVER_H ++ +diff --git a/drivers/sstar/emmc/unify_driver/inc/common/eMMC_err_codes.h b/drivers/sstar/emmc/unify_driver/inc/common/eMMC_err_codes.h +new file mode 100755 +index 000000000000..c439bb12bc30 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/common/eMMC_err_codes.h +@@ -0,0 +1,186 @@ ++/* ++* eMMC_err_codes.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __eMMC_ERR_CODES_H__ ++#define __eMMC_ERR_CODES_H__ ++//=========================================================== ++// device status (R1, R1b) ++//=========================================================== ++#define eMMC_R1_ADDRESS_OUT_OF_RANGE BIT31 ++#define eMMC_R1_ADDRESS_MISALIGN BIT30 ++#define eMMC_R1_BLOCK_LEN_ERROR BIT29 ++#define eMMC_R1_ERASE_SEQ_ERROR BIT28 ++#define eMMC_R1_ERASE_PARAM BIT27 ++#define eMMC_R1_WP_VIOLATION BIT26 ++#define eMMC_R1_DEVICE_IS_LOCKED BIT25 ++#define eMMC_R1_LOCK_UNLOCK_FAILED BIT24 ++#define eMMC_R1_COM_CRC_ERROR BIT23 ++#define eMMC_R1_ILLEGAL_COMMAND BIT22 ++#define eMMC_R1_DEVICE_ECC_FAILED BIT21 ++#define eMMC_R1_CC_ERROR BIT20 ++#define eMMC_R1_ERROR BIT19 ++#define eMMC_R1_CID_CSD_OVERWRITE BIT16 ++#define eMMC_R1_WP_ERASE_SKIP BIT15 ++#define eMMC_R1_ERASE_RESET BIT13 ++#define eMMC_R1_CURRENT_STATE (BIT12|BIT11|BIT10|BIT9) ++#define eMMC_R1_READY_FOR_DATA BIT8 ++#define eMMC_R1_SWITCH_ERROR BIT7 ++#define eMMC_R1_EXCEPTION_EVENT BIT6 ++#define eMMC_R1_APP_CMD BIT5 ++ ++#define eMMC_ERR_R1_31_24 (eMMC_R1_ADDRESS_OUT_OF_RANGE| \ ++ eMMC_R1_ADDRESS_MISALIGN| \ ++ eMMC_R1_BLOCK_LEN_ERROR| \ ++ eMMC_R1_ERASE_SEQ_ERROR| \ ++ eMMC_R1_ERASE_PARAM| \ ++ eMMC_R1_WP_VIOLATION| \ ++ eMMC_R1_LOCK_UNLOCK_FAILED) ++#define eMMC_ERR_R1_23_16 (eMMC_R1_COM_CRC_ERROR| \ ++ eMMC_R1_ILLEGAL_COMMAND| \ ++ eMMC_R1_DEVICE_ECC_FAILED| \ ++ eMMC_R1_CC_ERROR| \ ++ eMMC_R1_ERROR| \ ++ eMMC_R1_CID_CSD_OVERWRITE) ++#define eMMC_ERR_R1_15_8 (eMMC_R1_WP_ERASE_SKIP| \ ++ eMMC_R1_ERASE_RESET) ++#define eMMC_ERR_R1_7_0 (eMMC_R1_SWITCH_ERROR) ++ ++#define eMMC_ERR_R1_31_0 (eMMC_ERR_R1_31_24|eMMC_ERR_R1_23_16|eMMC_ERR_R1_15_8|eMMC_ERR_R1_7_0) ++#define eMMC_ERR_R1_NEED_RETRY (eMMC_R1_COM_CRC_ERROR|eMMC_R1_DEVICE_ECC_FAILED|eMMC_R1_CC_ERROR|eMMC_R1_ERROR|eMMC_R1_SWITCH_ERROR) ++//=========================================================== ++// driver error codes ++//=========================================================== ++#define eMMC_ST_SUCCESS 0 ++ ++#define eMMC_ST_ERR_MEM_CORRUPT (0x0001 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_ALIGN (0x0002 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_PACKED (0x0003 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DATA_MISMATCH (0x0004 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAIT_REG0 (0x0005 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY (0x0006 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_MIULASTDONE (0x0007 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITD0HIGH (0x0008 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_CARDDMAEND (0x0009 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT (0x000A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_STS_ERR (0x000B | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_BIST_FAIL (0x0010 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DEBUG_MODE (0x0011 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_CLK (0x0012 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARAMETER (0x0013 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_INIT (0x0014 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INVALID_PARAM (0x0015 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARTITION_CHKSUM (0x0016 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PART_INFO (0x0017 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PARTITION (0x0018 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_OK_DDR_PARAM (0x0019 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SAVE_DDRT_FAIL (0x001A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_CHKSUM (0x001B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_NONA (0x001C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI (0x001D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI (0x001E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI_NONA (0x001F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI_NONA (0x0020 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SDR_DETECT_DDR (0x0021 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_CIS (0x0022 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_eMMC_PLATFROM (0x0023 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_RIU (0x0024 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INT_TO (0x0025 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_UNKNOWN_CLK (0x0026 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_BUILD_DDRT (0x0027 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_RSP_IN_RAM (0x0028 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_SLOWER_CLK (0x0029 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PAD_ABNORMAL_OFF (0x0030 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SAVE_BLEN_FAIL (0x0031 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_BLEN_CHKSUM (0x0032 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CHKSUM (0x0033 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ERR_DET (0x0034 | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_CMD1 (0x0A00 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD1_DEV_NOT_RDY (0x0A01 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD2 (0x0A02 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD3_CMD7 (0x0A03 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_31_24 (0x0A04 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_23_16 (0x0A05 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_15_8 (0x0A06 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_7_0 (0x0A07 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_CIFD (0x0A08 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_MIU (0x0A09 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_CIFD (0x0A0A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_MIU (0x0A0B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD18 (0x0A0C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6 (0x0A0D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD13 (0x0A0E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD12 (0x0A0F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD (0x0A10 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H (0x0A11 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_CHK_R1 (0x0A12 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU (0x0A13 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_WAIT_D0H (0x0A14 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_CHK_R1 (0x0A15 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25 (0x0A16 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_WAIT_D0H (0x0A17 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_CHK_R1 (0x0A18 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD9 (0x0A19 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SEC_UPFW_TO (0x0A20 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD16 (0x0A21 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_HS200_1_8V (0x0A22 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_ONE_BIT (0x0A23 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_NO_RSP (0x0A24 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_DATA_CRC (0x0A25 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_NO_DRVING (0x0A26 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_HS200_FAIL (0x0A27 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_DATA_CMP (0x0A28 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_NO_HS200_1_8V (0x0A29 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SET_DRV_STRENGTH (0x0A2A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SKEW4 (0x0A2B | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_CMD8_ECHO (0x0B00 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_NO_RSP (0x0B01 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD55_NO_RSP (0x0B02 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD55_RSP_CRC (0x0B03 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD55_APP_CMD_BIT (0x0B04 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD41_DEV_BUSY (0x0B05 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD41_NO_RSP (0x0B06 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD9_CSD_FMT (0x0B07 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD6_NO_RSP (0x0B08 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD6_WRONG_PARA (0x0B09 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD13_NO_RSP (0x0B0A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD13_DAT_CRC (0x0B0B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_NO_RSP (0x0B0C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_DAT_CRC (0x0B0D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_WRONG_PARA (0x0B0E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_HS_NOT_SRPO (0x0B0F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_SWC_STS_ERR (0x0B10 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_SWC_STS_CODE (0x0B11 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_NO_RSP (0x0B12 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_SEQ_ERR (0x0B13 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_PARAM_ERR (0x0B14 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_RESET (0x0B15 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_NO_RSP (0x0B16 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_SEQ_ERR (0x0B17 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_PARAM_ERR (0x0B18 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_RESET (0x0B19 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_NO_RSP (0x0B1A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_SEQ_ERR (0x0B1B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_PARAM_ERR (0x0B1C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_RESET (0x0B1D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_TO (0x0B1E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD3536_ERR (0x0B1F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_ERR (0x0B20 | eMMC_ST_PLAT) ++ ++#endif /* __eMMC_ERR_CODES_H__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/common/eMMC_hal.h b/drivers/sstar/emmc/unify_driver/inc/common/eMMC_hal.h +new file mode 100755 +index 000000000000..031a7c125788 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/common/eMMC_hal.h +@@ -0,0 +1,172 @@ ++/* ++* eMMC_hal.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __eMMC_HAL_H__ ++#define __eMMC_HAL_H__ ++ ++#include "eMMC.h" ++ ++#define U32BEND2LEND(X) ( ((X&0x000000FF)<<24) + ((X&0x0000FF00)<<8) + ((X&0x00FF0000)>>8) + ((X&0xFF000000)>>24) ) ++#define U16BEND2LEND(X) ( ((X&0x00FF)<<8) + ((X&0xFF00)>>8) ) ++ ++#define _START_TXMIT 0x40 // transmission bit ++ ++#define eMMC_GO_IDLE_STATE (_START_TXMIT+0) ++#define eMMC_SEND_OP_COND (_START_TXMIT+1) ++#define eMMC_ALL_SEND_CID (_START_TXMIT+2) ++#define eMMC_SET_RLT_ADDR (_START_TXMIT+3) ++#define eMMC_SEL_DESEL_CARD (_START_TXMIT+7) ++#define eMMC_SEND_EXT_CSD (_START_TXMIT+8) ++#define eMMC_SEND_CSD (_START_TXMIT+9) ++#define eMMC_SWITCH (_START_TXMIT+6) ++#define eMMC_ERASE_GROUP_S (_START_TXMIT+35) ++#define eMMC_ERASE_GROUP_E (_START_TXMIT+36) ++#define eMMC_ERASE (_START_TXMIT+38) ++#define eMMC_SEND_STATUS (_START_TXMIT+13) ++#define eMMC_R_SINGLE_BLOCK (_START_TXMIT+17) ++#define eMMC_R_MULTIP_BLOCK (_START_TXMIT+18) ++#define eMMC_STOP_TRANSMIT (_START_TXMIT+12) ++#define eMMC_W_SINGLE_BLOCK (_START_TXMIT+24) ++#define eMMC_W_MULTIP_BLOCK (_START_TXMIT+25) ++#define eMMC_SEND_TUNING_BLK (_START_TXMIT+21) ++ ++#define STUFF_BITS 0x00000000 ++ ++extern U32 eMMC_FCIE_WaitEvents(uintptr_t ulongRegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_PollingEvents(uintptr_t ulongRegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir); ++extern void eMMC_FCIE_DumpDebugBus(void); ++extern void eMMC_FCIE_DumpRegisters(void); ++extern void eMMC_FCIE_CheckResetDone(void); ++extern U32 eMMC_FCIE_Reset(void); ++extern U32 eMMC_FCIE_Init(void); ++extern void eMMC_FCIE_ErrHandler_Stop(void); ++extern U32 eMMC_FCIE_ErrHandler_Retry(void); ++extern void eMMC_FCIE_ErrHandler_RestoreClk(void); ++extern void eMMC_FCIE_ErrHandler_ReInit(void); ++extern U32 eMMC_FCIE_ErrHandler_ReInit_Ex(void); ++extern U32 eMMC_FCIE_SendCmd(U16 u16_Mode, U16 u16_Ctrl, U32 u32_Arg, U8 u8_CmdIdx, U8 u8_RspByteCnt); ++extern void eMMC_FCIE_ClearEvents(void); ++extern void eMMC_FCIE_ClearEvents_Reg0(void); ++extern U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us); ++extern U32 eMMC_FCIE_WaitD0High(U32 u32_us); ++extern void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_GetCMDFIFO(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_GetCIFD(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern U8 eMMC_FCIE_CmdRspBufGet(U8 u8addr); ++extern U8 eMMC_FCIE_DataFifoGet(U8 u8addr); ++ ++// eMMC_hal_speed.c ++ ++extern U32 eMMC_FCIE_EnableDDRMode_Ex(void); ++extern void eMMC_FCIE_ApplyDDRTSet(U8 u8_DDRTIdx); ++extern void eMMC_DumpDDRTTable(void); ++ ++extern U32 eMMC_FCIE_ChooseSpeedMode(void); ++extern void eMMC_FCIE_ApplyTimingSet(U8 u8_Idx); ++extern void eMMC_FCIE_SetATopTimingReg(U8 u8_SetIdx); ++extern U32 eMMC_FCIE_EnableFastMode_Ex(U8 u8_PadType); ++ ++extern void eMMC_FCIE_SetDDR48TimingReg(U8 u8_DQS, U8 u8_DelaySel); ++extern U32 eMMC_FCIE_EnableFastMode(U8 u8_PadType); ++extern U32 eMMC_FCIE_EnableSDRMode(void); ++extern U32 eMMC_FCIE_DetectDDRTiming(void); ++extern void eMMC_DumpTimingTable(void); ++extern U32 eMMC_LoadTimingTable(U8 u8_PadType); ++extern U32 eMMC_TuningDDR52_Skew(void); ++extern U32 eMMC_TuningHS200_Skew(void); ++extern U32 eMMC_SlectBestSkew4(U32 u32_Candidate); ++extern U32 eMMC_Skew_ReTune(void); ++extern U32 eMMC_ATOP_EnableHS200(void); ++extern U32 eMMC_ATOP_EnableDDR52(void); ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++extern void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_SaveRsp(void); ++extern U32 eMMC_SaveDriverContext(void); ++extern U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf); ++extern U32 eMMC_LoadDriverContext(U8 *pu8_Buf); ++#endif ++ ++#if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++extern void eMMC_DumpBurstLenTable(void); ++extern U32 eMMC_LoadBurstLenTable(void); ++extern U32 eMMC_SaveBurstLenTable(void); ++#endif ++ ++//---------------------------------------- ++extern U32 eMMC_Identify(void); ++extern U32 eMMC_CMD0(U32 u32_Arg); ++extern U32 eMMC_CMD1(void); ++extern U32 eMMC_CMD2(void); ++extern U32 eMMC_CMD3(U16 u16_RCA); ++extern U32 eMMC_CMD7(U16 u16_RCA); ++extern U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx); ++extern U32 eMMC_CMD9(U16 u16_RCA); ++extern U32 eMMC_CSD_Config(void); ++extern U32 eMMC_ExtCSD_Config(void); ++extern U32 eMMC_CMD8(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf); ++extern U32 eMMC_SetPwrOffNotification(U8 u8_SetECSD34); ++extern U32 eMMC_SetBusSpeed(U8 u8_BusSpeed); ++extern U32 eMMC_Sanitize(U8 u8_ECSD165); ++extern U32 eMMC_SetDrivingStrength(U8 u8Driving); ++extern U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR); ++extern U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++extern U32 eMMC_CMD6(U32 u32_Arg); ++extern U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++extern U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx); ++extern U32 eMMC_CMD38(void); ++extern U32 eMMC_Dump_eMMCStatus(void); ++extern U32 eMMC_CMD13(U16 u16_RCA); ++extern U32 eMMC_CMD16(U32 u32_BlkLength); ++extern U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD12_NoCheck(U16 u16_RCA); ++extern U32 eMMC_CMD12(U16 u16_RCA); ++extern U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD18_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD23(U16 u16_BlkCnt); ++extern U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD25_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD21(void); ++extern U32 eMMC_GetR1(void); ++extern U32 eMMC_CheckR1Error(void); ++extern U32 eMMC_UpFW_Samsung(U8 *pu8_FWBin); ++extern U32 eMMC_CMD25_NoSched(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern void eMMC_TuningSkew4ForHS200(void); ++ ++//---------------------------------------- ++extern U32 eMMC_FCIE_PollingFifoClkReady(void); ++extern U32 eMMC_FCIE_PollingMIULastDone(void); ++ ++extern void HalFcie_SetFlag4Kernel2RuneMMC(void); ++extern bool HalFcie_CheckIfeMMCRun4Kernel(void); ++ ++extern void eMMC_DumpATopTable(void); ++extern void eMMC_FCIE_SymmetrySkew4(void); ++ ++extern U8 sgu8_IfNeedRestorePadType; // = 0xff ++extern U8 u8_sdr_retry_count; // = 0 ++ ++#endif // __eMMC_HAL_H__ +diff --git a/drivers/sstar/emmc/unify_driver/inc/common/eMMC_utl.h b/drivers/sstar/emmc/unify_driver/inc/common/eMMC_utl.h +new file mode 100755 +index 000000000000..8d9650f549dc +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/common/eMMC_utl.h +@@ -0,0 +1,42 @@ ++/* ++* eMMC_utl.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __eMMC_UTL_H__ ++#define __eMMC_UTL_H__ ++ ++#include "eMMC.h" ++ ++ ++typedef eMMC_PACK0 struct _eMMC_TEST_ALIGN_PACK { ++ ++ U8 u8_0; ++ U16 u16_0; ++ U32 u32_0, u32_1; ++ ++} eMMC_PACK1 eMMC_TEST_ALIGN_PACK_t; ++ ++extern U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt); ++extern void eMMC_dump_mem(unsigned char *buf, U32 cnt); ++extern void eMMC_dump_mem_32(U32 *buf, U32 cnt); ++extern U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt); ++extern U32 eMMC_ChkSum(U8 *pu8_Data, U32 u32_ByteCnt); ++extern U32 eMMC_PrintDeviceInfo(void); ++extern U32 eMMC_CompareCISTag(U8 *tag); ++extern void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo); ++extern void eMMC_dump_pni(eMMC_PNI_t *pPartInfo); ++extern void eMMC_dump_WR_Count(void); ++#endif // __eMMC_UTL_H__ +diff --git a/drivers/sstar/emmc/unify_driver/inc/config/eMMC_config.h b/drivers/sstar/emmc/unify_driver/inc/config/eMMC_config.h +new file mode 100755 +index 000000000000..fd1560ede0dd +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/config/eMMC_config.h +@@ -0,0 +1,95 @@ ++/* ++* eMMC_config.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __eMMC_CONFIG_H__ ++#define __eMMC_CONFIG_H__ ++ ++#define UNIFIED_eMMC_DRIVER 1 ++ ++//===================================================== ++// select a HW platform: ++// - 1: enable, 0: disable. ++// - only one platform can be 1, others have to be 0. ++// - search and check all [FIXME] if need modify or not ++//===================================================== ++ ++#ifndef U64 ++#define U64 unsigned long long ++#endif ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S64 ++#define S64 signed long long ++#endif ++#ifndef S32 ++#define S32 signed int ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#include "eMMC_linux.h" ++ ++//===================================================== ++// misc. do NOT edit the following content. ++//===================================================== ++#define eMMC_DMA_RACING_PATCH 1 ++#define eMMC_DMA_PATCH_WAIT_TIME DELAY_10ms_in_us ++#define eMMC_DMA_RACING_PATTERN0 (((U32)'M'<<24)|((U32)0<<16)|((U32)'S'<<8)|(U32)1) ++#define eMMC_DMA_RACING_PATTERN1 (((U32)'T'<<24)|((U32)6<<16)|((U32)'A'<<8)|(U32)8) ++ ++//=========================================================== ++// Time Dalay, do NOT edit the following content ++//=========================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RESET (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FIFOCLK_RDY (HW_TIMER_DELAY_10ms*10) ++#define TIME_WAIT_CMDRSP_END (HW_TIMER_DELAY_10ms*10) ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*5) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*10) // safe for 512 blocks ++#else ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_ERASE_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RESET HW_TIMER_DELAY_500ms ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT HW_TIMER_DELAY_1us ++#define TIME_WAIT_FIFOCLK_RDY HW_TIMER_DELAY_10ms ++#define TIME_WAIT_CMDRSP_END HW_TIMER_DELAY_10ms ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*1) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*2) // safe for 512 blocks ++#endif ++ ++#ifdef CONFIG_OF ++#define MSTAR_EMMC_CONFIG_OF 1 ++#else ++#define MSTAR_EMMC_CONFIG_OF 0 ++#endif ++ ++extern void mdelay_MacroToFun(u32 time); ++ ++#endif /* __eMMC_CONFIG_H__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/config/eMMC_reg.h b/drivers/sstar/emmc/unify_driver/inc/config/eMMC_reg.h +new file mode 100755 +index 000000000000..46f4babf9639 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/config/eMMC_reg.h +@@ -0,0 +1,358 @@ ++/* ++* eMMC_reg.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __eMMC_FCIE_REG_H__ ++#define __eMMC_FCIE_REG_H__ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++#ifndef BIT0 ++#define BIT0 (1<<0) ++#endif ++#ifndef BIT1 ++#define BIT1 (1<<1) ++#endif ++#ifndef BIT2 ++#define BIT2 (1<<2) ++#endif ++#ifndef BIT3 ++#define BIT3 (1<<3) ++#endif ++#ifndef BIT4 ++#define BIT4 (1<<4) ++#endif ++#ifndef BIT5 ++#define BIT5 (1<<5) ++#endif ++#ifndef BIT6 ++#define BIT6 (1<<6) ++#endif ++#ifndef BIT7 ++#define BIT7 (1<<7) ++#endif ++#ifndef BIT8 ++#define BIT8 (1<<8) ++#endif ++#ifndef BIT9 ++#define BIT9 (1<<9) ++#endif ++#ifndef BIT10 ++#define BIT10 (1<<10) ++#endif ++#ifndef BIT11 ++#define BIT11 (1<<11) ++#endif ++#ifndef BIT12 ++#define BIT12 (1<<12) ++#endif ++#ifndef BIT13 ++#define BIT13 (1<<13) ++#endif ++#ifndef BIT14 ++#define BIT14 (1<<14) ++#endif ++#ifndef BIT15 ++#define BIT15 (1<<15) ++#endif ++#ifndef BIT16 ++#define BIT16 (1<<16) ++#endif ++#ifndef BIT17 ++#define BIT17 (1<<17) ++#endif ++#ifndef BIT18 ++#define BIT18 (1<<18) ++#endif ++#ifndef BIT19 ++#define BIT19 (1<<19) ++#endif ++#ifndef BIT20 ++#define BIT20 (1<<20) ++#endif ++#ifndef BIT21 ++#define BIT21 (1<<21) ++#endif ++#ifndef BIT22 ++#define BIT22 (1<<22) ++#endif ++#ifndef BIT23 ++#define BIT23 (1<<23) ++#endif ++#ifndef BIT24 ++#define BIT24 (1<<24) ++#endif ++#ifndef BIT25 ++#define BIT25 (1<<25) ++#endif ++#ifndef BIT26 ++#define BIT26 (1<<26) ++#endif ++#ifndef BIT27 ++#define BIT27 (1<<27) ++#endif ++#ifndef BIT28 ++#define BIT28 (1<<28) ++#endif ++#ifndef BIT29 ++#define BIT29 (1<<29) ++#endif ++#ifndef BIT30 ++#define BIT30 (1<<30) ++#endif ++#ifndef BIT31 ++#define BIT31 (1<<31) ++#endif ++ ++//------------------------------------------------------------------ ++#define FCIE_MIE_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x00) ++#define FCIE_MIE_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x01) ++#define FCIE_MMA_PRI_REG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x02) ++#define FCIE_MIU_DMA_26_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x03) ++#define FCIE_MIU_DMA_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x04) ++#define FCIE_CARD_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x06) ++#define FCIE_CARD_POWER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x08) ++#define FCIE_FORCE_INT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x09) ++#define FCIE_PATH_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0A) ++#define FCIE_JOB_BL_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0B) ++#define FCIE_TR_BK_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0C) ++#define FCIE_RSP_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0D) ++#define FCIE_CMD_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0E) ++#define FCIE_CIFD_WORD_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0F) ++#define FCIE_SD_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_SD_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++#define FCIE_SD_STATUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x12) ++#define FCIE_REG16h GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x16) ++#define FCIE_SDIO_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1B) ++#define FCIE_SDIO_ADDR0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1C) ++#define FCIE_SDIO_ADDR1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1D) ++#define FCIE_SD_MACRO_REDNT2 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2B) ++#define FCIE_SM_STS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2C) ++#define FCIE_REG_2Dh GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2D) ++#define FCIE_MIU_OFFSET GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2E) ++#define FCIE_BOOT_CONFIG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2F) ++#define FCIE_TEST_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x30) ++#define FCIE_DEBUG_BUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x31) ++#define FCIE_MACRO_REDNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x32) ++#define FCIE_TOGGLE_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x33) ++#define FCIE_PWR_SAVE_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x35) ++#define FCIE_MISC GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x36) ++#define FCIE_HS200_PATCH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x3F) ++#define NC_WIDTH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x41) ++ ++#define FCIE_CIFC_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFC_BASE_ADDR, u16_pos) ++#define FCIE_CIFC_BYTE_CNT 0x40 // 32 x 16 bits ++ ++#define FCIE_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFD_BASE_ADDR, u16_pos) ++#define FCIE_CIFD_BYTE_CNT 0x200 // 256 x 16 bits ++ ++//------------------------------------------------------------------ ++/* FCIE_MIE_EVENT 0x00 */ ++/* FCIE_MIE_INT_EN 0x01 */ ++#define BIT_MMA_DATA_END BIT0 ++#define BIT_SD_CMD_END BIT1 ++#define BIT_SD_DATA_END BIT2 ++#define BIT_CARD_DMA_END BIT11 ++#define BIT_MIU_LAST_DONE BIT14 ++#define BIT_CARD_BOOT_DONE BIT15 ++#define BIT_ALL_CARD_INT_EVENTS (BIT_MMA_DATA_END|BIT_SD_CMD_END|BIT_SD_DATA_END\ ++ |BIT_CARD_DMA_END|BIT_MIU_LAST_DONE|BIT_CARD_BOOT_DONE) ++/* FCIE_MMA_PRI_REG 0x02 */ ++#define BIT_DMA_DIR_W BIT2 ++#define BIT_MIU_REQUEST_RST BIT4 ++#define BIT_FIFO_CLKRDY BIT5 ++#define BIT_MIU_BURST_MASK (BIT8|BIT9|BIT10) ++#define BIT_MIU_BURST_CTRL BIT10 ++#define BIT_MIU_BURST_8 BIT_MIU_BURST_CTRL ++#define BIT_MIU_BURST_16 (BIT8|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_BURST_32 (BIT9|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_CLK_EN_SW BIT12 ++#define BIT_MIU_CLK_EN_HW BIT13 ++#define BIT_MIU_CLK_CTRL_SEL_SW BIT14 ++#define BIT_MIU_CLK_FREE_RUN BIT15 ++/* FCIE_MIU_DMA_26_16 0x03 */ ++#define BIT_MIU1_SELECT BIT15 ++/* FCIE_CARD_POWER 0x08 */ ++#define BIT_SD_PWR_ON_n BIT0 ++#define BIT_SD_PWR_OUT_n BIT2 ++/* FCIE_PATH_CTRL 0x0A */ ++#define BIT_MMA_EN BIT0 ++#define BIT_SD_EN BIT1 ++/* FCIE_JOB_BL_CNT 0x0B */ ++#define BIT_SD_JOB_BLK_CNT_MASK (BIT12-1) ++#define BIT_SD_JOB_CNT_SRC_MIU BIT14 ++#define BIT_SD_JOB_CNT_SRC_SEL BIT15 ++/* FCIE_RSP_SIZE 0x0D */ ++#define BIT_SD_RSP_SIZE_MASK (BIT7-1) ++/* FCIE_SD_MODE 0x10 */ ++#define BIT_SD_CLK_EN BIT0 ++#define BIT_SD_DATA_WIDTH_MASK (BIT1|BIT2) ++#define BIT_SD_DATA_WIDTH_1 0 ++#define BIT_SD_DATA_WIDTH_4 BIT1 ++#define BIT_SD_DATA_WIDTH_8 BIT2 ++#define BIT_SD_IF_LOW BIT3 ++#define BIT_SD_CLK_AUTO_STOP BIT4 ++#define BIT_SD_DATA_CIFD BIT5 ++#define BIT_SD_DATA_SYNC BIT6 // set for eMMC High Speed Mode ++#define BIT_SD_SELECT_SDIO BIT9 ++#define BIT_SD_DMA_R_CLK_STOP BIT11 ++ ++//#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_CLK_EN) ++#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_DATA_SYNC|BIT_SD_CLK_EN) ++ ++/* FCIE_SD_CTRL 0x11 */ ++#define BIT_SD_RSPR2_EN BIT0 ++#define BIT_SD_RSP_EN BIT1 ++#define BIT_SD_CMD_EN BIT2 ++#define BIT_SD_DAT_EN BIT3 ++#define BIT_SD_DAT_DIR_W BIT4 ++/* FCIE_SD_STATUS 0x12 */ ++#define BIT_SD_R_CRC_ERR BIT0 ++#define BIT_SD_W_FAIL BIT1 // no any positive/negative CRC status latched ++#define BIT_SD_W_CRC_ERR BIT2 // negative CRC status latched ++#define BIT_SD_RSP_TIMEOUT BIT3 // response time out in 64 clocks ++#define BIT_SD_RSP_CRC_ERR BIT4 // response crc error ++#define BIT_SD_CARD_WP BIT5 ++#define BIT_SD_CARD_BUSY BIT6 ++#define BIT_SD_D0 BIT8 ++#define BIT_SD_DBUS_MASK (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++#define BIT_SD_DBUS_SHIFT 8 ++ ++//#define BIT_SD_FCIE_ERR_FLAGS ((BIT5-1)|BIT_SD_CARD_BUSY) ++#define BIT_SD_FCIE_ERR_FLAGS (BIT5-1) ++#define BIT_SD_CARD_D0_ST BIT8 ++#define BIT_SD_CARD_D1_ST BIT9 ++#define BIT_SD_CARD_D2_ST BIT10 ++#define BIT_SD_CARD_D3_ST BIT11 ++#define BIT_SD_CARD_D4_ST BIT12 ++#define BIT_SD_CARD_D5_ST BIT13 ++#define BIT_SD_CARD_D6_ST BIT14 ++#define BIT_SD_CARD_D7_ST BIT15 ++/* FCIE_REG16h */ ++#define BIT_EMMC_ACTIVE BIT0 ++#define BIT_KERN_NAND (BIT3|BIT1) ++#define BIT_KERN_EMMC (BIT3|BIT2) ++#define BIT_KERN_CHK_NAND_EMMC BIT3 ++#define BIT_KERN_CHK_NAND_EMMC_MSK (BIT3|BIT2|BIT1) ++/* FCIE_SDIO_CTRL 0x1B */ ++#define BIT_SDIO_BLK_SIZE_MASK (BIT13-1) ++#define BIT_SDIO_BLK_MODE BIT15 ++/* FCIE_SM_STS 0x2B */ ++#define BIT_DDR_TIMING_LATCH BIT8 ++/* FCIE_SM_STS 0x2C */ ++#define BIT_DQS_DELAY_CELL_MASK (BIT8|BIT9|BIT10|BIT11) ++#define BIT_DQS_DELAY_CELL_SHIFT 8 ++#define BIT_DQS_MODE_MASK (BIT12|BIT13) ++#define BIT_DQS_MODE_SHIFT 12 ++#define BIT_DQS_MODE_2T (0 << BIT_DQS_MODE_SHIFT) ++#define BIT_DQS_MODE_1_5T (1 << BIT_DQS_MODE_SHIFT) ++#define BIT_DQS_MODE_2_5T (2 << BIT_DQS_MODE_SHIFT) ++#define BIT_DQS_MODE_1T (3 << BIT_DQS_MODE_SHIFT) ++ ++#define BIT_SKEW1_INV BIT8 ++#define BIT_SKEW2_INV BIT9 ++#define BIT_SKEW3_INV BIT10 ++#define BIT_SKEW4_INV BIT11 ++ ++#define BITS_SKEW_SET_MSK 0x0F00 ++#define BITS_SKEW_SET0 0x0700 ++#define BITS_SKEW_SET1 0x0000 ++ ++/* FCIE_REG_2Dh 0x2D */ ++#define BIT_ddr_timing_patch BIT0 ++#define BIT_eco_d0_busy_check BIT3 ++ ++#define BIT_csreg_miu_wp_last2_sel BIT14 ++/* FCIE_BOOT_CONFIG 0x2F */ ++#define BIT_BOOT_STG2_EN BIT0 ++#define BIT_BOOT_END_EN BIT1 ++#define BIT_BOOT_MODE_EN BIT2 ++#define BIT_MACRO_EN BIT8 ++#define BIT_SD_DDR_EN BIT9 ++#define BIT_SD_BYPASS_MODE_EN BIT10 ++#define BIT_SD_SDR_IN_BYPASS BIT11 ++#define BIT_SD_FROM_TMUX BIT12 ++#define BIT_SD_CLKOE_DELAY_EN BIT13 ++/* FCIE_TEST_MODE 0x30 */ ++#define BIT_FCIE_BIST_FAIL (BIT0|BIT1|BIT2|BIT3|BIT4) ++#define BIT_FCIE_DEBUG_MODE_MASK (BIT8|BIT9|BIT10) ++#define BIT_FCIE_DEBUG_MODE_SHIFT 8 ++#define BIT_FCIE_SOFT_RST_n BIT12 ++#define BIT_FCIE_PPFIFO_CLK BIT14 ++/* FCIE_MACRO_REDNT 0x32 */ ++#define BIT_CRC_STATUS_4_HS200 BIT0 ++#define BIT_LATE_DATA0_W_IP_CLK BIT1 ++#define BIT_DQS_DELAY_CELL_SEL_MASK (BIT0|BIT1|BIT2|BIT3) ++#define BIT_MACRO_TEST_MODE_MASK (BIT4|BIT5) ++#define BIT_MACRO_DIR BIT6 ++#define BIT_TOGGLE_CNT_RST BIT7 ++/* FCIE_TOGGLE_CNT */ ++#define BITS_8_R_TOGGLE_CNT 0x0111 // 256 data clock + 17 bits CRC ++#define BITS_4_R_TOGGLE_CNT 0x0211 // 512 data clcok + 17 bits CRC ++#define BITS_8_W_TOGGLE_CNT 0x011A // 256 data clcok + 26 bits CRC + CRC status ++#define BITS_4_W_TOGGLE_CNT 0x021A // 512 data clcok + 26 bits CRC + CRC status ++ ++#define TOGGLE_CNT_128_CLK_R 0x0091 // 128 data clcok + 17 bits CRC ++#define TOGGLE_CNT_256_CLK_R 0x0111 // 256 data clcok + 17 bits CRC ++#define TOGGLE_CNT_512_CLK_R 0x0211 // 512 data clcok + 17 bits CRC ++#define TOGGLE_CNT_256_CLK_W 0x011A // 256 data clcok + 26 bits CRC + CRC status ++#define TOGGLE_CNT_512_CLK_W 0x021A // 512 data clcok + 26 bits CRC + CRC status ++ ++/* FCIE_PWR_SAVE_MODE 0x35 */ ++#define BIT_POWER_SAVE_MODE_EN BIT0 /* Power Save HW enable, high active */ ++#define BIT_SD_POWER_SAVE_RIU BIT1 /* SW set register to emulate power lost event, high active */ ++#define BIT_POWER_SAVE_MODE_INT_EN BIT2 /* interrupt enable, high active */ ++#define BIT_SD_POWER_SAVE_RST BIT3 /* software reset Power Save HW, default is '1', set '0' to reset HW */ ++#define BIT_RIU_SAVE_EVENT BIT5 /* RO, RIU emulation power save event */ ++#define BIT_RST_SAVE_EVENT BIT6 /* RO, Hardware reset power save event */ ++#define BIT_BAT_SAVE_EVENT BIT7 /* RO, Battery lost power save event */ ++ ++/*FCIE_HS200_PATCH 0x3F*/ ++#define BIT_HS200_RDDAT_PATCH BIT8 ++#define BIT_HS200_NORSP_PATCH BIT9 ++#define BIT_HS200_WCRC_PATCH BIT10 ++#define BIT_sbit_lose_patch BIT11 ++#define BIT_HS200_PATCH_MASK (BIT_HS200_RDDAT_PATCH|BIT_HS200_NORSP_PATCH|BIT_HS200_WCRC_PATCH|BIT_sbit_lose_patch) ++ ++/* NC_WIDTH 0x41 */ ++#define BIT_NC_DEB_SEL_SHIFT 12 ++#define BIT_NC_DEB_SEL_MASK (BIT12|BIT13|BIT14) ++#define BIT_NC_BCH_DEB_SEL BIT15 ++ ++//------------------------------------------------------------------ ++/* ++ * Power Save FIFO Cmd* ++ */ ++#define PWR_BAT_CLASS (0x1 << 13) /* Battery lost class */ ++#define PWR_RST_CLASS (0x1 << 12) /* Reset Class */ ++ ++/* Command Type */ ++#define PWR_CMD_WREG (0x0 << 9) /* Write data */ ++#define PWR_CMD_RDCP (0x1 << 9) /* Read and cmp data. If mismatch, HW retry */ ++#define PWR_CMD_WAIT (0x2 << 9) /* Wait idle, max. 128T */ ++#define PWR_CMD_WINT (0x3 << 9) /* Wait interrupt */ ++#define PWR_CMD_STOP (0x7 << 9) /* Stop */ ++ ++/* RIU Bank */ ++#define PWR_CMD_BK0 (0x0 << 7) ++#define PWR_CMD_BK1 (0x1 << 7) ++#define PWR_CMD_BK2 (0x2 << 7) ++#define PWR_CMD_BK3 (0x3 << 7) ++ ++#define PWR_RIU_ADDR (0x0 << 0) ++ ++#endif /* __eMMC_FCIE_REG_H__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/config/eMMC_reg_v5.h b/drivers/sstar/emmc/unify_driver/inc/config/eMMC_reg_v5.h +new file mode 100755 +index 000000000000..9116f64da382 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/config/eMMC_reg_v5.h +@@ -0,0 +1,425 @@ ++/* ++* eMMC_reg_v5.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __EMMC_REG_V5_H__ ++#define __EMMC_REG_V5_H__ ++ ++#define IP_FCIE_VERSION_5 ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++#ifndef BIT0 ++#define BIT0 (1<<0) ++#endif ++#ifndef BIT1 ++#define BIT1 (1<<1) ++#endif ++#ifndef BIT2 ++#define BIT2 (1<<2) ++#endif ++#ifndef BIT3 ++#define BIT3 (1<<3) ++#endif ++#ifndef BIT4 ++#define BIT4 (1<<4) ++#endif ++#ifndef BIT5 ++#define BIT5 (1<<5) ++#endif ++#ifndef BIT6 ++#define BIT6 (1<<6) ++#endif ++#ifndef BIT7 ++#define BIT7 (1<<7) ++#endif ++#ifndef BIT8 ++#define BIT8 (1<<8) ++#endif ++#ifndef BIT9 ++#define BIT9 (1<<9) ++#endif ++#ifndef BIT10 ++#define BIT10 (1<<10) ++#endif ++#ifndef BIT11 ++#define BIT11 (1<<11) ++#endif ++#ifndef BIT12 ++#define BIT12 (1<<12) ++#endif ++#ifndef BIT13 ++#define BIT13 (1<<13) ++#endif ++#ifndef BIT14 ++#define BIT14 (1<<14) ++#endif ++#ifndef BIT15 ++#define BIT15 (1<<15) ++#endif ++#ifndef BIT16 ++#define BIT16 (1<<16) ++#endif ++#ifndef BIT17 ++#define BIT17 (1<<17) ++#endif ++#ifndef BIT18 ++#define BIT18 (1<<18) ++#endif ++#ifndef BIT19 ++#define BIT19 (1<<19) ++#endif ++#ifndef BIT20 ++#define BIT20 (1<<20) ++#endif ++#ifndef BIT21 ++#define BIT21 (1<<21) ++#endif ++#ifndef BIT22 ++#define BIT22 (1<<22) ++#endif ++#ifndef BIT23 ++#define BIT23 (1<<23) ++#endif ++#ifndef BIT24 ++#define BIT24 (1<<24) ++#endif ++#ifndef BIT25 ++#define BIT25 (1<<25) ++#endif ++#ifndef BIT26 ++#define BIT26 (1<<26) ++#endif ++#ifndef BIT27 ++#define BIT27 (1<<27) ++#endif ++#ifndef BIT28 ++#define BIT28 (1<<28) ++#endif ++#ifndef BIT29 ++#define BIT29 (1<<29) ++#endif ++#ifndef BIT30 ++#define BIT30 (1<<30) ++#endif ++#ifndef BIT31 ++#define BIT31 (1<<31) ++#endif ++ ++//------------------------------------------------------------------ ++#define FCIE_MIE_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x00) ++#define FCIE_MIE_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x01) ++#define FCIE_MMA_PRI_REG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x02) ++#define FCIE_MIU_DMA_ADDR_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x03) ++#define FCIE_MIU_DMA_ADDR_31_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x04) ++#define FCIE_MIU_DMA_LEN_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x05) ++#define FCIE_MIU_DMA_LEN_31_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x06) ++#define FCIE_MIE_FUNC_CTL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x07) ++#define FCIE_JOB_BL_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x08) ++#define FCIE_BLK_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x09) ++#define FCIE_CMD_RSP_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0A) ++#define FCIE_SD_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0B) ++#define FCIE_SD_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0C) ++#define FCIE_SD_STATUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0D) ++#define FCIE_BOOT_CONFIG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0E) ++#define FCIE_DDR_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0F) ++//#define FCIE_DDR_TOGGLE_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_RESERVED_FOR_SW GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_SDIO_MOD GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++//#define FCIE_SBIT_TIMER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++#define FCIE_RSP_SHIFT_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x12) ++#define FCIE_RX_SHIFT_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x13) ++#define FCIE_ZDEC_CTL0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x14) ++#define FCIE_TEST_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x15) ++#define FCIE_MMA_BANK_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x16) ++#define FCIE_WR_SBIT_TIMER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x17) ++//#define FCIE_SDIO_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x17) ++#define FCIE_RD_SBIT_TIMER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x18) ++//#define FCIE_DEBUG_BUS0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1E) ++//#define FCIE_DEBUG_BUS1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1F) ++#define NC_CIFD_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x30) ++#define NC_CIFD_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x31) ++#define FCIE_PWR_RD_MASK GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x34) ++#define FCIE_PWR_SAVE_CTL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x35) ++#define FCIE_BIST GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x36) ++#define FCIE_BOOT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x37) ++#define FCIE_EMMC_DEBUG_BUS0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x38) ++#define FCIE_EMMC_DEBUG_BUS1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x39) ++#define FCIE_RST GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x3F) ++//#define NC_WIDTH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x41) ++#define FCIE_NC_FUN_CTL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x63) ++ ++#define FCIE_CMDFIFO_ADDR(u16_pos) GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, u16_pos) ++#define FCIE_CMDFIFO_BYTE_CNT 0x12// 9 x 16 bits ++ ++#define FCIE_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFD_BASE_ADDR, u16_pos) ++ ++#define NC_WBUF_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_NC_WBUF_CIFD_BASE, u16_pos) // 32 x 16 bits SW Read only ++#define NC_RBUF_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_NC_RBUF_CIFD_BASE, u16_pos) // 32 x 16 bits SW write/read ++ ++#define NC_CIFD_ADDR(u16_pos) NC_RBUF_CIFD_ADDR(u16_pos) ++ ++#define NC_CIFD_WBUF_BYTE_CNT 0x40 // 32 x 16 bits ++#define NC_CIFD_RBUF_BYTE_CNT 0x40 // 32 x 16 bits ++ ++#define FCIE_CIFD_BYTE_CNT 0x40 // 256 x 16 bits ++ ++//------------------------------------------------------------------ ++/* FCIE_MIE_EVENT 0x00 */ ++/* FCIE_MIE_INT_EN 0x01 */ ++#define BIT_DMA_END BIT0 ++#define BIT_SD_CMD_END BIT1 ++#define BIT_ERR_STS BIT2 ++//#define BIT_SD_DATA_END BIT2 ++#define BIT_SDIO_INT BIT3 ++#define BIT_BUSY_END_INT BIT4 ++#define BIT_R2N_RDY_INT BIT5 ++#define BIT_CARD_CHANGE BIT6 ++#define BIT_CARD2_CHANGE BIT7 ++//#define BIT_PWR_SAVE_INT BIT14 ++//#define BIT_BOOT_DONE_INT BIT15 ++//#define BIT_ALL_CARD_INT_EVENTS (BIT_DMA_END|BIT_SD_CMD_END|BIT_BUSY_END_INT) ++#define BIT_ALL_CARD_INT_EVENTS (BIT_DMA_END|BIT_SD_CMD_END|BIT_ERR_STS|BIT_BUSY_END_INT|BIT_R2N_RDY_INT) ++ ++/* FCIE_MMA_PRI_REG 0x02 */ ++#define BIT_MIU_R_PRI BIT0 ++#define BIT_MIU_W_PRI BIT1 ++#define BIT_MIU_SELECT_MASK (BIT3|BIT2) ++#define BIT_MIU1_SELECT BIT2 ++#define BIT_MIU2_SELECT BIT3 ++#define BIT_MIU3_SELECT (BIT3|BIT2) ++//#define BIT_DATA_SCRAMBLE BIT3 ++#define BIT_MIU_BUS_TYPE_MASK (BIT4|BIT5) ++#define BIT_MIU_BURST1 (~BIT_MIU_BUS_TYPE_MASK) ++#define BIT_MIU_BURST2 (BIT4) ++#define BIT_MIU_BURST4 (BIT5) ++#define BIT_MIU_BURST8 (BIT4|BIT5) ++ ++/* FCIE_MIE_FUNC_CTL 0x07 */ ++#define BIT_EMMC_EN BIT0 ++#define BIT_SD_EN BIT1 ++#define BIT_SDIO_MOD BIT2 ++#define BIT_EMMC_ACTIVE BIT12 ++#define BIT_KERN_NAND (BIT_KERN_CHK_NAND_EMMC|BIT13) ++#define BIT_KERN_EMMC (BIT_KERN_CHK_NAND_EMMC|BIT14) ++#define BIT_KERN_CHK_NAND_EMMC BIT15 ++#define BIT_KERN_CHK_NAND_EMMC_MSK (BIT13|BIT14|BIT15) ++ ++/* FCIE_BLK_CNT 0x08 */ ++#define BIT_SD_JOB_BLK_CNT_MASK (BIT13-1) ++ ++/* FCIE_CMD_RSP_SIZE 0x0A */ ++#define BIT_RSP_SIZE_MASK (BIT6-1) ++#define BIT_CMD_SIZE_MASK (BIT13|BIT12|BIT11|BIT10|BIT9|BIT8) ++#define BIT_CMD_SIZE_SHIFT 8 ++ ++/* FCIE_SD_MODE 0x0B */ ++#define BIT_CLK_EN BIT0 ++#define BIT_SD_CLK_EN BIT_CLK_EN ++#define BIT_SD_DATA_WIDTH_MASK (BIT2|BIT1) ++#define BIT_SD_DATA_WIDTH_1 0 ++#define BIT_SD_DATA_WIDTH_4 BIT1 ++#define BIT_SD_DATA_WIDTH_8 BIT2 ++#define BIT_DATA_DEST BIT4 // 0: DMA mode, 1: R2N mode ++#define BIT_SD_DATA_CIFD BIT_DATA_DEST ++#define BIT_DATA_SYNC BIT5 ++#define BIT_SD_DMA_R_CLK_STOP BIT7 ++#define BIT_DIS_WR_BUSY_CHK BIT8 ++ ++#define BIT_SD_DEFAULT_MODE_REG (BIT_CLK_EN) ++ ++/* FCIE_SD_CTRL 0x0C */ ++#define BIT_SD_RSPR2_EN BIT0 ++#define BIT_SD_RSP_EN BIT1 ++#define BIT_SD_CMD_EN BIT2 ++#define BIT_SD_DTRX_EN BIT3 ++#define BIT_SD_DAT_EN BIT_SD_DTRX_EN ++#define BIT_SD_DAT_DIR_W BIT4 ++#define BIT_ADMA_EN BIT5 ++#define BIT_JOB_START BIT6 ++#define BIT_CHK_CMD BIT7 ++#define BIT_BUSY_DET_ON BIT8 ++#define BIT_ERR_DET_ON BIT9 ++ ++/* FCIE_SD_STATUS 0x0D */ ++#define BIT_DAT_RD_CERR BIT0 ++#define BIT_SD_R_CRC_ERR BIT_DAT_RD_CERR ++#define BIT_DAT_WR_CERR BIT1 ++#define BIT_SD_W_FAIL BIT_DAT_WR_CERR ++#define BIT_DAT_WR_TOUT BIT2 ++#define BIT_SD_W_CRC_ERR BIT_DAT_WR_TOUT ++#define BIT_CMD_NO_RSP BIT3 ++#define BIT_SD_RSP_TIMEOUT BIT_CMD_NO_RSP ++#define BIT_CMD_RSP_CERR BIT4 ++#define BIT_SD_RSP_CRC_ERR BIT_CMD_RSP_CERR ++#define BIT_DAT_RD_TOUT BIT5 ++//#define BIT_SD_CARD_WP BIT5 ++#define BIT_SD_CARD_BUSY BIT6 ++ ++#define BITS_ERROR (BIT_SD_R_CRC_ERR|BIT_DAT_WR_CERR|BIT_DAT_WR_TOUT|BIT_CMD_NO_RSP|BIT_CMD_RSP_CERR|BIT_DAT_RD_TOUT) ++ ++#define BIT_SD_D0 BIT8 // not correct D0 in 32 bits macron ++//#define BIT_SD_DBUS_MASK (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++//#define BIT_SD_DBUS_SHIFT 8 ++#define BIT_SD_FCIE_ERR_FLAGS (BIT6-1) ++#define BIT_SD_CARD_D0_ST BIT8 ++#define BIT_SD_CARD_D1_ST BIT9 ++#define BIT_SD_CARD_D2_ST BIT10 ++#define BIT_SD_CARD_D3_ST BIT11 ++#define BIT_SD_CARD_D4_ST BIT12 ++#define BIT_SD_CARD_D5_ST BIT13 ++#define BIT_SD_CARD_D6_ST BIT14 ++#define BIT_SD_CARD_D7_ST BIT15 ++ ++/* FCIE_BOOT_CONFIG 0x0E */ ++#define BIT_EMMC_RSTZ BIT0 ++#define BIT_EMMC_RSTZ_EN BIT1 ++#define BIT_BOOT_MODE_EN BIT2 ++//#define BIT_BOOT_END BIT3 ++ ++/* FCIE_DDR_MODE 0x0F */ ++//#define BIT_DQS_DELAY_CELL_MASK (BIT0|BIT1|BIT2|BIT3) ++//#define BIT_DQS_DELAY_CELL_SHIFT 0 ++#define BIT_MACRO_MODE_MASK (BIT7|BIT8|BIT12|BIT13|BIT14|BIT15) ++#define BIT_8BIT_MACRO_EN BIT7 ++#define BIT_DDR_EN BIT8 ++//#define BIT_SDR200_EN BIT9 ++#define BIT_CLK2_SEL BIT10 ++//#define BIT_SDRIN_BYPASS_EN BIT11 ++#define BIT_32BIT_MACRO_EN BIT12 ++#define BIT_PAD_IN_SEL_SD BIT13 ++#define BIT_FALL_LATCH BIT14 ++#define BIT_PAD_IN_MASK BIT15 ++ ++/* FCIE_TOGGLE_CNT 0x10 */ ++#define BITS_8_MACRO32_DDR52_TOGGLE_CNT 0x110 ++#define BITS_4_MACRO32_DDR52_TOGGLE_CNT 0x210 ++ ++#define BITS_8_MACRO32_HS200_TOGGLE_CNT 0x210 ++#define BITS_4_MACRO32_HS200_TOGGLE_CNT 0x410 ++ ++/* FCIE_SDIO_MOD 0x11 */ ++#define BIT_REG_SDIO_MOD_MASK (BIT1|BIT0) ++#define BIT_SDIO_DET_ON BIT2 ++#define BIT_SDIO_DET_INT_SRC BIT3 ++ ++/* FCIE_RSP_SHIFT_CNT 0x12 */ ++#define BIT_RSP_SHIFT_TUNE_MASK (BIT4 - 1) ++#define BIT_RSP_SHIFT_SEL BIT4 /*SW or HW by default 0*/ ++ ++/* FCIE_RX_SHIFT_CNT 0x13 */ ++#define BIT_RSTOP_SHIFT_TUNE_MASK (BIT4 - 1) ++#define BIT_RSTOP_SHIFT_SEL BIT4 ++#define BIT_WRSTS_SHIFT_TUNE_MASK (BIT8|BIT9|BIT10|BIT11) ++#define BIT_WRSTS_SHIFT_SEL BIT12 ++ ++/* FCIE_ZDEC_CTL0 0x14 */ ++#define BIT_ZDEC_EN BIT0 ++#define BIT_SD2ZDEC_PTR_CLR BIT1 ++ ++/* FCIE_TEST_MODE 0x15 */ ++#define BIT_SDDR1 BIT0 ++#define BIT_DEBUG_MODE_MASK (BIT3|BIT2|BIT1) ++#define BIT_DEBUG_MODE_SHIFT 1 ++#define BIT_BIST_MODE BIT4 ++//#define BIT_DS_TESTEN BIT1 ++//#define BIT_TEST_MODE BIT2 ++//#define BIT_DEBUG_MODE_MASK BIT3|BIT4|BIT5 ++//#define BIT_DEBUG_MODE_SHIFT 3 ++//#define BIT_TEST_MIU BIT6 ++//#define BIT_TEST_MIE BIT7 ++//#define BIT_TEST_MIU_STS BIT8 ++//#define BIT_TEST_MIE_STS BIT9 ++//#define BIT_BIST_MODE BIT10 ++ ++/* FCIE_WR_SBIT_TIMER 0x17 */ ++#define BIT_WR_SBIT_TIMER_MASK (BIT15-1) ++#define BIT_WR_SBIT_TIMER_EN BIT15 ++ ++/* FCIE_RD_SBIT_TIMER 0x18 */ ++#define BIT_RD_SBIT_TIMER_MASK (BIT15-1) ++#define BIT_RD_SBIT_TIMER_EN BIT15 ++ ++ ++/* NC_CIFD_EVENT 0x30 */ ++#define BIT_WBUF_FULL BIT0 ++#define BIT_WBUF_EMPTY_TRI BIT1 ++#define BIT_RBUF_FULL_TRI BIT2 ++#define BIT_RBUF_EMPTY BIT3 ++ ++/* NC_CIFD_INT_EN 0x31 */ ++#define BIT_WBUF_FULL_INT_EN BIT0 ++#define BIT_RBUF_EMPTY_INT_EN BIT1 ++#define BIT_F_WBUF_FULL_INT BIT2 ++#define BIT_F_RBUF_EMPTY_INT BIT3 ++ ++/* FCIE_PWR_SAVE_CTL 0x35 */ ++#define BIT_POWER_SAVE_MODE BIT0 ++#define BIT_SD_POWER_SAVE_RIU BIT1 ++#define BIT_POWER_SAVE_MODE_INT_EN BIT2 ++#define BIT_SD_POWER_SAVE_RST BIT3 ++#define BIT_POWER_SAVE_INT_FORCE BIT4 ++#define BIT_RIU_SAVE_EVENT BIT5 ++#define BIT_RST_SAVE_EVENT BIT6 ++#define BIT_BAT_SAVE_EVENT BIT7 ++#define BIT_BAT_SD_POWER_SAVE_MASK BIT8 ++#define BIT_RST_SD_POWER_SAVE_MASK BIT9 ++#define BIT_POWER_SAVE_MODE_INT BIT15 ++ ++/* FCIE_BOOT 0x37 */ ++#define BIT_NAND_BOOT_EN BIT0 ++#define BIT_BOOTSRAM_ACCESS_SEL BIT1 ++ ++/* FCIE_BOOT 0x39 */ ++#define BIT_DEBUG_MODE_MSK (BIT11|BIT10|BIT9|BIT8) ++#define BIT_DEBUG_MODE_SET (BIT10|BIT8) ++ ++/* FCIE_RESET 0x3F */ ++ ++#define BIT_FCIE_SOFT_RST_n BIT0 ++#define BIT_RST_MIU_STS BIT1 ++#define BIT_RST_MIE_STS BIT2 ++#define BIT_RST_MCU_STS BIT3 ++#define BIT_RST_ECC_STS BIT4 ++//#define BIT_RST_STS_MASK (BIT_RST_MIU_STS | BIT_RST_MIE_STS | BIT_RST_MCU_STS | BIT_RST_ECC_STS) ++#define BIT_RST_STS_MASK (BIT_RST_MIU_STS | BIT_RST_MIE_STS | BIT_RST_MCU_STS) ++#define BIT_NC_DEB_SEL_SHIFT 12 ++#define BIT_NC_DEB_SEL_MASK (BIT15|BIT14|BIT13|BIT12) ++ ++//------------------------------------------------------------------ ++/* ++ * Power Save FIFO Cmd* ++ */ ++#define PWR_BAT_CLASS (0x1 << 13) /* Battery lost class */ ++#define PWR_RST_CLASS (0x1 << 12) /* Reset Class */ ++ ++/* Command Type */ ++#define PWR_CMD_WREG (0x0 << 9) /* Write data */ ++#define PWR_CMD_RDCP (0x1 << 9) /* Read and cmp data. If mismatch, HW retry */ ++#define PWR_CMD_WAIT (0x2 << 9) /* Wait idle, max. 128T */ ++#define PWR_CMD_WINT (0x3 << 9) /* Wait interrupt */ ++#define PWR_CMD_STOP (0x7 << 9) /* Stop */ ++ ++/* RIU Bank */ ++#define PWR_CMD_BK0 (0x0 << 7) ++#define PWR_CMD_BK1 (0x1 << 7) ++#define PWR_CMD_BK2 (0x2 << 7) ++#define PWR_CMD_BK3 (0x3 << 7) ++ ++#define PWR_RIU_ADDR (0x0 << 0) ++ ++#endif /* __EMMC_REG_V5_H__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/infinity2m/eMMC_linux.h b/drivers/sstar/emmc/unify_driver/inc/infinity2m/eMMC_linux.h +new file mode 100755 +index 000000000000..d323bf02b6fd +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/infinity2m/eMMC_linux.h +@@ -0,0 +1,622 @@ ++/* ++* eMMC_linux.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef __eMMC__LINUX__ ++#define __eMMC__LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++//===================================================== ++// Overall ++//===================================================== ++#define SDIO_SETTING_ONLY (1) ++#define INIT_PADMUX (0) ++#define PADMUX_CTRL (0) ++#define DRIVING_CTRL (1) ++#define MAX_CLK_CTRL (1) ++#define SET_BY_DTS (0) ++ ++extern u32 gRegBankFeie0, gRegBankFeie1, gRegBankFeie2; ++extern u32 gRegCkgSd, gBitCkgSdGating, gBitCkgSdInverse, gBitCkgSdMask, gBitCkgSdSrcSel; ++extern u32 gBitCkgSdGpCtrl; ++extern u32 gBitSdModeMask, gBitSdModeSel; ++extern u32 gRegDrivingCfg, gBitDrivingClk, gBitDrivingCmd, gBitDrivingData; ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS (2) ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++// ++#define ENABLE_EMMC_ASYNC_IO 0 ++#define ENABLE_FCIE_HW_BUSY_CHECK 0 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++#define ENABLE_FCIE_ADMA 1 ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET (0) ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET (BL_BLK_CNT) ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE (0x20) // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN (0) // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG (1) ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_48M ++ ++// for backward compatible ++#if 1 ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++#else ++#define FCIE_SLOW_CLK FCIE_SLOWEST_CLK ++#define FCIE_DEFAULT_CLK FCIE_SLOWEST_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_SLOWEST_CLK ++#endif ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++ ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC_INFINITY5_LINUX__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/infinity3/eMMC_linux.h b/drivers/sstar/emmc/unify_driver/inc/infinity3/eMMC_linux.h +new file mode 100755 +index 000000000000..90c20b5fc9fc +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/infinity3/eMMC_linux.h +@@ -0,0 +1,597 @@ ++/* ++* eMMC_linux.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef __eMMC__LINUX__ ++#define __eMMC__LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++//===================================================== ++// Overall ++//===================================================== ++#define SDIO_SETTING_ONLY (0) ++#define INIT_PADMUX (0) ++#define PADMUX_CTRL (0) ++#define DRIVING_CTRL (0) ++#define MAX_CLK_CTRL (0) ++#define SET_BY_DTS (0) ++ ++extern u32 gRegBankFeie0, gRegBankFeie1, gRegBankFeie2; ++extern u32 gRegCkgSd, gBitCkgSdGating, gBitCkgSdInverse, gBitCkgSdMask, gBitCkgSdSrcSel; ++extern u32 gBitCkgSdGpCtrl; ++extern u32 gBitSdModeMask, gBitSdModeSel; ++extern u32 gRegDrivingCfg, gBitDrivingClk, gBitDrivingCmd, gBitDrivingData; ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS (2) ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET (0) ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET (BL_BLK_CNT) ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE (0x20) // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN (0) // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG (1) ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_48M ++ ++// for backward compatible ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++ ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC__LINUX__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/infinity5/eMMC_linux.h b/drivers/sstar/emmc/unify_driver/inc/infinity5/eMMC_linux.h +new file mode 100755 +index 000000000000..9d95d64b8ac6 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/infinity5/eMMC_linux.h +@@ -0,0 +1,607 @@ ++/* ++* eMMC_linux.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef __eMMC__LINUX__ ++#define __eMMC__LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++//===================================================== ++// Overall ++//===================================================== ++#define SDIO_SETTING_ONLY (0) ++#define INIT_PADMUX (0) ++#define PADMUX_CTRL (0) ++#define DRIVING_CTRL (0) ++#define MAX_CLK_CTRL (0) ++#define SET_BY_DTS (0) ++ ++extern u32 gRegBankFeie0, gRegBankFeie1, gRegBankFeie2; ++extern u32 gRegCkgSd, gBitCkgSdGating, gBitCkgSdInverse, gBitCkgSdMask, gBitCkgSdSrcSel; ++extern u32 gBitCkgSdGpCtrl; ++extern u32 gBitSdModeMask, gBitSdModeSel; ++extern u32 gRegDrivingCfg, gBitDrivingClk, gBitDrivingCmd, gBitDrivingData; ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS (2) ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++// ++#define ENABLE_EMMC_ASYNC_IO 0 ++#define ENABLE_FCIE_HW_BUSY_CHECK 0 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++#define ENABLE_FCIE_ADMA 1 ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 0 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET (0) ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET (BL_BLK_CNT) ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE (0x20) // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN (0) // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG (1) ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_43_2M ++ ++// for backward compatible ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++//#define FCIE_SLOW_CLK FCIE_SLOWEST_CLK ++//#define FCIE_DEFAULT_CLK FCIE_SLOWEST_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++ ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC__LINUX__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/infinity6/eMMC_linux.h b/drivers/sstar/emmc/unify_driver/inc/infinity6/eMMC_linux.h +new file mode 100755 +index 000000000000..efea938e3d7f +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/infinity6/eMMC_linux.h +@@ -0,0 +1,604 @@ ++/* ++* eMMC_linux.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef __eMMC__LINUX__ ++#define __eMMC__LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++//===================================================== ++// Overall ++//===================================================== ++#define SDIO_SETTING_ONLY (1) ++#define INIT_PADMUX (0) ++#define PADMUX_CTRL (1) ++#define DRIVING_CTRL (0) ++#define MAX_CLK_CTRL (0) ++#define SET_BY_DTS (0) ++ ++extern u32 gRegBankFeie0, gRegBankFeie1, gRegBankFeie2; ++extern u32 gRegCkgSd, gBitCkgSdGating, gBitCkgSdInverse, gBitCkgSdMask, gBitCkgSdSrcSel; ++extern u32 gBitCkgSdGpCtrl; ++extern u32 gBitSdModeMask, gBitSdModeSel; ++extern u32 gRegDrivingCfg, gBitDrivingClk, gBitDrivingCmd, gBitDrivingData; ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS (2) ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++// ++#define ENABLE_EMMC_ASYNC_IO 0 ++#define ENABLE_FCIE_HW_BUSY_CHECK 0 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++#define ENABLE_FCIE_ADMA 1 ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 0 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET (0) ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET (BL_BLK_CNT) ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE (0x20) // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN (0) // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG (1) ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_48M ++ ++// for backward compatible ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++//#define FCIE_SLOW_CLK FCIE_SLOWEST_CLK ++//#define FCIE_DEFAULT_CLK FCIE_SLOWEST_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++ ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC__LINUX__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/infinity6b0/eMMC_linux.h b/drivers/sstar/emmc/unify_driver/inc/infinity6b0/eMMC_linux.h +new file mode 100755 +index 000000000000..11690388113c +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/infinity6b0/eMMC_linux.h +@@ -0,0 +1,687 @@ ++/* ++* eMMC_linux.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: harry-cl.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __eMMC__LINUX__ ++#define __eMMC__LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++//===================================================== ++// Overall ++//===================================================== ++#define SDIO_SETTING_ONLY (1) ++#define INIT_PADMUX (0) ++#define PADMUX_CTRL (1) ++#define DRIVING_CTRL (1) ++#define MAX_CLK_CTRL (1) ++#define SET_BY_DTS (1) ++ ++extern u32 gRegBankFeie0, gRegBankFeie1, gRegBankFeie2; ++extern u32 gRegCkgSd, gBitCkgSdGating, gBitCkgSdInverse, gBitCkgSdMask, gBitCkgSdSrcSel; ++extern u32 gBitCkgSdGpCtrl; ++extern u32 gBitSdModeMask, gBitSdModeSel; ++extern u32 gRegDrivingCfg, gBitDrivingClk, gBitDrivingCmd, gBitDrivingData; ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS (2) ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++// ++#define ENABLE_EMMC_ASYNC_IO 0 ++#define ENABLE_FCIE_HW_BUSY_CHECK 0 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++#define ENABLE_FCIE_ADMA 1 ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET (0) ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET (BL_BLK_CNT) ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE (0x20) // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN (0) // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG (1) ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_48M ++ ++// for backward compatible ++#if 1 ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++#else ++#define FCIE_SLOW_CLK FCIE_SLOWEST_CLK ++#define FCIE_DEFAULT_CLK FCIE_SLOWEST_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_SLOWEST_CLK ++#endif ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++ ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC__LINUX__ */ +diff --git a/drivers/sstar/emmc/unify_driver/inc/infinity6e/eMMC_linux.h b/drivers/sstar/emmc/unify_driver/inc/infinity6e/eMMC_linux.h +new file mode 100755 +index 000000000000..5019cb019238 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/inc/infinity6e/eMMC_linux.h +@@ -0,0 +1,607 @@ ++/* ++* eMMC_linux.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __eMMC_INFINITY_LINUX__ ++#define __eMMC_INFINITY_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++//===================================================== ++// Overall ++//===================================================== ++#define SDIO_SETTING_ONLY (0) ++#define INIT_PADMUX (1) ++#define PADMUX_CTRL (0) ++#define DRIVING_CTRL (0) ++#define MAX_CLK_CTRL (0) ++#define SET_BY_DTS (0) ++ ++extern u32 gRegBankFeie0, gRegBankFeie1, gRegBankFeie2; ++extern u32 gRegCkgSd, gBitCkgSdGating, gBitCkgSdInverse, gBitCkgSdMask, gBitCkgSdSrcSel; ++extern u32 gBitCkgSdGpCtrl; ++extern u32 gBitSdModeMask, gBitSdModeSel; ++extern u32 gRegDrivingCfg, gBitDrivingClk, gBitDrivingCmd, gBitDrivingData; ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS (2) ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+(y<[1:2]/[PAD_SPI:PAD_GPIO] ++ ++//--------------------------------clock gen------------------------------------ ++#define BIT_FCIE_CLK_48M 0x0 ++#define BIT_FCIE_CLK_43_2M 0x1 ++#define BIT_FCIE_CLK_40M 0x2 ++#define BIT_FCIE_CLK_36M 0x3 ++#define BIT_FCIE_CLK_32M 0x4 ++#define BIT_FCIE_CLK_20M 0x5 ++#define BIT_CLK_XTAL_12M 0x6 ++#define BIT_FCIE_CLK_12M 0x6 ++#define BIT_FCIE_CLK_300K 0x7 ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 // FIXME ++ ++#define PLL_SKEW4_CNT 9 ++#define MIN_OK_SKEW_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++typedef struct _eMMC_FCIE_ATOP_SET { ++ ++ U32 u32_ScanResult; ++ U8 u8_Clk; ++ U8 u8_Reg2Ch, u8_Skew4; ++ U8 u8_Cell; ++ U8 u8_Skew2, u8_CellCnt; ++} eMMC_FCIE_ATOP_SET_t; ++ ++ ++typedef struct _eMMC_FCIE_ATOP_SET_EXT { ++ U32 au32_RXDLLResult[5]; ++ U8 u8_Skew4Idx; ++ U8 au8_Reg2Ch[5], au8_Skew4[5]; ++ U8 au8_Cell[5], au8_CellCnt[5]; ++} eMMC_FCIE_ATOP_SET_EXT_t; ++ ++ ++#define eMMC_RST_L() {REG_FCIE_SETBIT(reg_emmc_rstz_en, BIT_EMMC_RST);\ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_EMMC_RSTZ_EN);\ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_EMMC_RSTZ);} ++#define eMMC_RST_H() {REG_FCIE_SETBIT(reg_emmc_rstz_en, BIT_EMMC_RST);\ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_EMMC_RSTZ_EN);\ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_EMMC_RSTZ);} ++ ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++#if 0 ++//--------------------------------sar5---------------------------- ++#define reg_sel_hvdetect GET_REG_ADDR(RIU_PM_BASE+0x1C00, 0x28) ++#define BIT_SEL_HVDETECT BIT4 ++#define reg_vplug_in_pwrgd GET_REG_ADDR(RIU_PM_BASE+0x1C00, 0x62) ++#endif ++ ++//===================================================== ++// API declarations ++//===================================================== ++ ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ 12000000//12MHz [FIXME] ++// define what latch method (mode) fcie has ++// implement switch pad function with below cases ++ ++#define FCIE_MODE_GPIO_PAD_DEFO_SPEED 0 ++#define FCIE_eMMC_BYPASS FCIE_MODE_GPIO_PAD_DEFO_SPEED ++ ++#define FCIE_MODE_8BITS_MACRO_HIGH_SPEED 2 ++#define FCIE_eMMC_SDR FCIE_MODE_8BITS_MACRO_HIGH_SPEED ++ ++#define FCIE_MODE_8BITS_MACRO_DDR52 3 ++#define FCIE_MODE_32BITS_MACRO_DDR52 4 ++#define FCIE_eMMC_DDR FCIE_MODE_8BITS_MACRO_DDR52 ++#define FCIE_eMMC_DDR_8BIT_MACRO FCIE_MODE_8BITS_MACRO_DDR52 ++ ++#define FCIE_MODE_32BITS_MACRO_HS200 5 ++#define FCIE_eMMC_HS200 FCIE_MODE_32BITS_MACRO_HS200 ++ ++#define FCIE_MODE_32BITS_MACRO_HS400_DS 6 // data strobe ++#define FCIE_MODE_32BITS_MACRO_HS400_SKEW4 7 ++#define FCIE_eMMC_5_1_AFIFO 8 ++#define FCIE_eMMC_HS400 FCIE_MODE_32BITS_MACRO_HS400_DS ++#define FCIE_eMMC_HS400_DS FCIE_eMMC_HS400 ++#define FCIE_eMMC_HS400_SKEW4 FCIE_MODE_32BITS_MACRO_HS400_SKEW4 ++ ++ ++// define what latch method (mode) use for latch eMMC data ++// switch FCIE mode when driver (kernel) change eMMC speed ++ ++#define EMMC_DEFO_SPEED_MODE FCIE_MODE_GPIO_PAD_DEFO_SPEED ++#define EMMC_HIGH_SPEED_MODE FCIE_MODE_GPIO_PAD_DEFO_SPEED ++#define EMMC_DDR52_MODE FCIE_MODE_32BITS_MACRO_DDR52 // FCIE_MODE_8BITS_MACRO_DDR52 ++#define EMMC_HS200_MODE FCIE_MODE_32BITS_MACRO_HS200 ++#define EMMC_HS400_MODE FCIE_MODE_32BITS_MACRO_HS400_DS // FCIE_MODE_32BITS_MACRO_HS400_SKEW4 ++#define ENABLE_AFIFO 1 ++ ++ ++// define what speed we want this chip/project run ++//------------------------------ ++// DDR48, DDR52, HS200, HS400 ++#define IF_DETECT_eMMC_DDR_TIMING 0 // DDR48 (digital macro) ++#define ENABLE_eMMC_ATOP 0 ++#define ENABLE_eMMC_DDR52 0 ++#define ENABLE_eMMC_HS200 0 ++#define ENABLE_eMMC_HS400 0 ++#define eMMC_IF_TUNING_TTABLE() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_TUNING_TTABLE) ++// mboot use this config ++ ++#define WRITE_TO_eMMC 0 ++#define READ_FROM_eMMC 1 ++ ++#include "mstar_chip.h" ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++//extern U32 eMMC_config_clock(U16 u16_SeqAccessTime); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++dma_addr_t eMMC_DMA_MAP_address(uintptr_t ulongBuffer, U32 u32_ByteCnt, int mode); ++void eMMC_DMA_UNMAP_address(dma_addr_t dma_DMAAddr, U32 u32_ByteCnt, int mode); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(uintptr_t u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++//extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++extern int mstar_mci_Housekeep(void *pData); ++extern U32 eMMC_PlatformDeinit(void); ++extern void eMMC_SetMaxClk(U32 clk); ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++ ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++#define eMMC_PART_ENV (0x0D|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_DEV_NODE (0x0F|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_MIU (0x20|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_EBOOT (0x21|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RTK (0x22|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_PARAMS (0x23|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_NVRAM (0x88|eMMC_LOGI_PART) //default start from 31 count ++ ++//extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "sstar_mci" ++#define eMMC_DRV_LINUX 1 ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++// ++#define ENABLE_EMMC_ASYNC_IO 0 ++#define ENABLE_FCIE_HW_BUSY_CHECK 0 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++#define ENABLE_FCIE_ADMA 1 ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET (0) ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET (BL_BLK_CNT) ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE (0x20) // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN (0) // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG (1) ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_48M ++ ++// for backward compatible ++#if 1 ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++#else ++#define FCIE_SLOW_CLK FCIE_SLOWEST_CLK ++#define FCIE_DEFAULT_CLK FCIE_SLOWEST_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_SLOWEST_CLK ++#endif ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++ ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC_INFINITY5_LINUX__ */ +diff --git a/drivers/sstar/emmc/unify_driver/mmc.lds b/drivers/sstar/emmc/unify_driver/mmc.lds +new file mode 100755 +index 000000000000..2e8e3639e12a +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/mmc.lds +@@ -0,0 +1,17 @@ ++SECTIONS ++{ ++ .FCIE.module.text : { *(.text) } ++ .FCIE.module.rodata : { ++ *(.rodata) *(.rodata.*) ++ *(__vermagic) *(__tracepoints_ptrs) *(__markers_strings) *(__tracepoints_strings) ++ *(.rodata1) *(.rio_switch_ops) ++ *(SORT(___ksymtab+*)) *(SORT(___ksymtab_gpl+*)) *(SORT(___ksymtab_unused+*)) *(SORT(___ksymtab_unused_gpl+*)) *(SORT(___ksymtab_gpl_future+*)) ++ *(SORT(___kcrctab+*)) *(SORT(___kcrctab_gpl+*)) *(SORT(___kcrctab_unused+*)) *(SORT(___kcrctab_unused_gpl+*)) *(SORT(___kcrctab_gpl_future+*)) ++ *(__ksymtab_strings) ++ *(.ref.rodata) ++ *(.devinit.rodata) *(.devexit.rodata) ++ *(.cpuinit.rodata) *(.cpuexit.rodata) ++ *(__param) ++ *(__modver) ++ } ++} +diff --git a/drivers/sstar/emmc/unify_driver/mstar_mci.c b/drivers/sstar/emmc/unify_driver/mstar_mci.c +new file mode 100755 +index 000000000000..f655f3d52494 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/mstar_mci.c +@@ -0,0 +1,1734 @@ ++/* ++* mstar_mci.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include "mstar_mci.h" ++ ++/****************************************************************************** ++ * Defines ++ ******************************************************************************/ ++#define MCI_RETRY_CNT_CMD_TO 100 ++#define MCI_RETRY_CNT_CRC_ERR 200 // avoid stack overflow ++#define MCI_RETRY_CNT_OK_CLK_UP 10 ++ ++/****************************************************************************** ++ * Function Prototypes ++ ******************************************************************************/ ++static void mstar_mci_send_command(struct mstar_mci_host *pSstarHost_st, struct mmc_command *pCmd_st); ++static void mstar_mci_completed_command(struct mstar_mci_host *pSstarHost_st); ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pSstarHost_st); ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *pSstarHost_st, struct mmc_data *data, struct mstar_mci_host_next *next); ++static void mstar_mci_pre_req(struct mmc_host *pMMCHost_st, struct mmc_request *mrq, bool is_first_req); ++static void mstar_mci_post_req(struct mmc_host * pMMCHost_st,struct mmc_request * mrq,int err); ++#endif ++#endif ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st); ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st); ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st); ++ ++u32 mstar_mci_WaitD0High(u32 u32_us); ++static U32 u32_ok_cnt=0; ++ ++/***************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++/* MSTAR Multimedia Card Interface Operations */ ++static const struct mmc_host_ops sg_mstar_mci_ops = ++{ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ .pre_req = mstar_mci_pre_req, ++ .post_req = mstar_mci_post_req, ++ #endif ++ #endif ++ .request = mstar_mci_request, ++ .set_ios = mstar_mci_set_ios, ++ .get_ro = mstar_mci_get_ro, ++}; ++ ++static struct task_struct *sgp_eMMCThread_st = NULL; ++static ulong wr_seg_size = 0; ++static ulong wr_split_threshold = 0; ++ ++u8 u8_enable_sar5 = 0; ++ ++// =============================== ++// for /sys files ++U32 gu32_pwrsvr_gpio_enable = 0; ++U32 gu32_pwrsvr_gpio_addr = 0; ++U32 gu32_pwrsvr_gpio_bit = 0; ++U32 gu32_pwrsvr_gpio_trigger = 0; ++U32 gu32_emmc_sanitize = 0; ++ ++/***************************************************************************** ++ * for profiling ++ ******************************************************************************/ ++#if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++static struct proc_dir_entry * writefile; ++const char procfs_name[] = "StorageBytes"; ++ ++int procfile_read(char* buffer, char ** buffer_location, off_t offset, ++ int buffer_length, int *eof, void *data) ++{ ++ int ret; ++ if(offset > 0) ++ ret = 0; ++ else ++ ret = sprintf(buffer,"TotalWriteBytes %llu GB %llu MB\nTotalReadBytes %llu GB %llu MB\n", ++ g_eMMCDrv.u64_CNT_TotalWBlk/1024/1024/2, (g_eMMCDrv.u64_CNT_TotalWBlk/1024/2) % 1024, ++ g_eMMCDrv.u64_CNT_TotalRBlk/1024/1024/2, (g_eMMCDrv.u64_CNT_TotalRBlk/1024/2) % 1024); ++ return ret; ++} ++#endif ++ ++/****************************************************************************** ++ * Functions ++ ******************************************************************************/ ++static int mstar_mci_get_dma_dir(struct mmc_data *data) ++{ ++ #if defined(CONFIG_ENABLE_EMMC_ACP) && CONFIG_ENABLE_EMMC_ACP ++ return DMA_ACP; ++ #else ++ if (data->flags & MMC_DATA_WRITE) ++ return DMA_TO_DEVICE; ++ else ++ return DMA_FROM_DEVICE; ++ #endif ++} ++ ++static void mstar_mci_pre_dma_read(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ struct scatterlist *pSG_st = 0; ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ //int sg_count = 0; ++ u32 u32_dmalen = 0; ++ //u32 u32_sg_count; ++ dma_addr_t dmaaddr = 0; ++ ++ pCmd_st = pSstarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pSstarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ pSG_st = &pData_st->sg[0]; ++ dmaaddr = (u32)sg_dma_address(pSG_st); ++ u32_dmalen = sg_dma_len(pSG_st); ++ u32_dmalen = ((u32_dmalen&0x1FF)?1:0) + u32_dmalen/512; ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ eMMC_FCIE_FifoClkRdy(0); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += u32_dmalen; ++ g_eMMCDrv.u32_RBlk_tmp = u32_dmalen; ++ #endif ++ ++} ++ ++static U32 mstar_mci_post_dma_read(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ int err = eMMC_ST_SUCCESS; ++ ++ pCmd_st = pSstarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ pSG_st = &(pData_st->sg[0]); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ return err; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ for(i=1; isg_len; i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ pSG_st = &(pData_st->sg[i]); ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT,(dmalen/512)); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, ++ eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ goto dma_read_end; ++ } ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ ++ // ----------------------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen / 512); ++ g_eMMCDrv.u32_RBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ dma_read_end: ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_RBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinRBlk[g_eMMCDrv.u32_RBlk_tmp]++; ++ else if(g_eMMCDrv.u32_RBlk_tmp > g_eMMCDrv.u32_CNT_MaxRBlk) ++ g_eMMCDrv.u32_CNT_MaxRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ else if(g_eMMCDrv.u32_RBlk_tmp < g_eMMCDrv.u32_CNT_MinRBlk) ++ g_eMMCDrv.u32_CNT_MinRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_RLast += g_eMMCDrv.u32_RBlk_tmp; ++ g_eMMCDrv.u32_RBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ if( !err ) // success ++ { ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pSstarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pSstarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ } ++ } ++ ++ return err; ++} ++ ++ ++static U32 mstar_mci_dma_write(struct mstar_mci_host *pSstarHost_st) ++{ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ //int sg_count; ++ u32 dmalen = 0, split_len = 0, split_unit_len = 0, split_up_len = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_W : TOGGLE_CNT_256_CLK_W); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ pCmd_st = pSstarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ split_unit_len = wr_seg_size << (10 - eMMC_SECTOR_BYTECNT_BITS); ++ split_up_len = wr_split_threshold << (10 - eMMC_SECTOR_BYTECNT_BITS); ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pSstarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ for(i=0; isg_len; i++) ++ { ++ pSG_st = &(pData_st->sg[i]); ++ dmaaddr = sg_dma_address(pSG_st); ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ dmalen = sg_dma_len(pSG_st)>>eMMC_SECTOR_BYTECNT_BITS; ++ ++ do{ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ split_len = ++ dmalen > g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen ? ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen : dmalen; ++ split_len = ++ split_len == g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen ? ++ split_len>>1 : split_len; ++ #else ++ split_len = dmalen; ++ #endif ++ ++ if(split_unit_len && (!split_up_len || dmalen <= split_up_len)) ++ split_len = dmalen > split_unit_len ? ++ split_unit_len : dmalen; ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, split_len); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, (dmaaddr & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, (dmaaddr >> 16)); ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ if(0==i) ++ eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ ++ eMMC_CheckPowerCut(); ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END, ++ eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ ++ dmalen -= split_len; ++ dmaaddr += split_len << eMMC_SECTOR_BYTECNT_BITS; ++ ++ // ----------------------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalWBlk += (split_len / 512); ++ g_eMMCDrv.u32_WBlk_tmp += (split_len / 512); ++ #endif ++ ++ }while(dmalen > 0); ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ } ++ ++dma_write_end: ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_WBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinWBlk[g_eMMCDrv.u32_WBlk_tmp]++; ++ else if(g_eMMCDrv.u32_WBlk_tmp > g_eMMCDrv.u32_CNT_MaxWBlk) ++ g_eMMCDrv.u32_CNT_MaxWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ else if(g_eMMCDrv.u32_WBlk_tmp < g_eMMCDrv.u32_CNT_MinWBlk) ++ g_eMMCDrv.u32_CNT_MinWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_WLast += g_eMMCDrv.u32_WBlk_tmp; ++ g_eMMCDrv.u32_WBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if( !err ) ++ { ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pSstarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pSstarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ } ++ } ++ ++ return err; ++} ++ ++static void mstar_mci_completed_command(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ u16 u16_st, u16_i; ++ u8 *pTemp; ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ static u32 u32_retry_cnt=0, u32_run_cnt=0; ++ ++ u32_run_cnt++; ++ // ---------------------------------- ++ // retrun response from FCIE to mmc driver ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3 - (u16_i % 4)) + (4 * (u16_i / 4))] = ++ (u8)(REG_FCIE(FCIE1_BASE+(((u16_i+1)/2)*4)) >> (8*((u16_i+1)%2))); ++ } ++ #if 0 ++ eMMC_debug(0,0,"------------------\n"); ++ eMMC_debug(0,1,"resp[0]: %08Xh\n", pCmd_st->resp[0]); ++ eMMC_debug(0,1,"CIFC: %04Xh %04Xh %04Xh \n", REG_FCIE(FCIE_CIFC_BASE_ADDR), ++ REG_FCIE(FCIE_CIFC_BASE_ADDR+4), REG_FCIE(FCIE_CIFC_BASE_ADDR+8)); ++ //eMMC_dump_mem(pTemp, 0x10); ++ eMMC_debug(0,0,"------------------\n"); ++ #endif ++ ++ // ---------------------------------- ++ u16_st = REG_FCIE(FCIE_SD_STATUS); ++ if((u16_st & BIT_SD_FCIE_ERR_FLAGS) /*|| mstar_SD_CardChange()*/ ++ || (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY))// || ((mmc_resp_type(pCmd_st)==MMC_RSP_R1) && (pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY))) ++ { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ ++ if((u16_st & BIT_SD_RSP_CRC_ERR) && !(mmc_resp_type(pCmd_st) & MMC_RSP_CRC)) ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ else ++ { ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: ST:%Xh, CMD:%u, retry: %u, flag: %Xh, R1 err: %Xh\n", ++ u16_st, pCmd_st->opcode, u32_retry_cnt, g_eMMCDrv.u32_DrvFlag, ++ pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY); ++ ++ u32_ok_cnt = 0; ++ if(u32_retry_cnt++ >= MCI_RETRY_CNT_CRC_ERR) ++ eMMC_FCIE_ErrHandler_Stop(); // fatal error ++ ++ if(25==pCmd_st->opcode || 12==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_hw_timer_sleep(1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ ++ if(0 != pCmd_st->data) ++ { ++ eMMC_FCIE_ErrHandler_Retry(); // slow dwon clock ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++ } ++ else // for CMD12 ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: no data, just reset eMMC. \n"); ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ return; ++ } ++ ++ if(0==u32_retry_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: retry ok \n"); ++ return; ++ } ++ ++ //----------------------------------------- ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: ST:%Xh, CMD:%u, retry:%u \n", ++ u16_st, pCmd_st->opcode, pCmd_st->retries); ++ #endif ++ ++ // should be trivial ++ if(u16_st & (BIT_SD_RSP_TIMEOUT | BIT_SD_W_FAIL)) ++ pCmd_st->error = -ETIMEDOUT; ++ else if(u16_st & (BIT_SD_RSP_CRC_ERR | BIT_SD_R_CRC_ERR | BIT_SD_W_CRC_ERR)) ++ pCmd_st->error = -EILSEQ; ++ else ++ pCmd_st->error = -EIO; ++ } ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ ++ u32_retry_cnt = 0; ++ } ++ ++ if((pCmd_st->opcode == 17) || (pCmd_st->opcode == 18) //read ++ ||(pCmd_st->opcode == 24) || (pCmd_st->opcode == 25) //write ++ ||(pCmd_st->opcode == 12)) //stop transmission ++ { ++ if(pCmd_st->resp[0] & eMMC_ERR_R1_31_0) ++ { ++ pCmd_st->error |= -EIO; ++ if(pCmd_st->opcode == 12) ++ eMMC_debug(0,0, "eMMC Warn: CMD12 R1 error: %Xh \n", ++ pCmd_st->resp[0]); ++ else ++ eMMC_debug(0,0, "eMMC Warn: CMD%u R1 error: %Xh, arg %08x, blocks %08x\n", ++ pCmd_st->opcode, pCmd_st->resp[0], pCmd_st->arg, pCmd_st->data->blocks); ++ } ++ } ++ ++ #if 0 ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt) ++ { ++ eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++} ++ ++#define WAIT_D0H_POLLING_TIME HW_TIMER_DELAY_100us ++u32 mstar_mci_WaitD0High(u32 u32_us) ++{ ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ ++ REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_BUSY_DET_ON); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // enable busy int ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_SD_BUSY_END); ++ #endif ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_BUSY_END,u32_us) != eMMC_ST_SUCCESS) ++ { ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ return eMMC_ST_SUCCESS; ++ #else ++ u32 u32_cnt, u32_wait; ++ ++ for(u32_cnt=0; u32_cnt HW_TIMER_DELAY_1ms) ++ { ++ //msleep(1); ++ //schedule_hrtimeout is more precise and can reduce idle time of emmc ++ { ++ ktime_t expires = ktime_add_ns(ktime_get(), 1000 * 1000); ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ schedule_hrtimeout(&expires, HRTIMER_MODE_ABS); ++ } ++ u32_cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ #endif ++} ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static void mstar_mci_send_data(struct work_struct *work) ++{ ++ struct mstar_mci_host *pSstarHost_st = container_of(work, struct mstar_mci_host, async_work); ++ struct mmc_command *pCmd_st; ++ struct mmc_data *pData_st; ++ static u8 u8_retry_data=0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if( !pSstarHost_st ) ++ return; ++ ++ pCmd_st = pSstarHost_st->cmd; ++ ++ if( !pCmd_st ) ++ return; ++ ++ pData_st = pCmd_st->data; ++ ++ if( !pData_st ) ++ return; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pSstarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ err = mstar_mci_post_dma_read(pSstarHost_st); ++ } ++ ++ if( err ) ++ { ++ u32_ok_cnt = 0; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w, cmd.%u arg.%Xh, ST: %Xh or TO\n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r, cmd.%u arg.%Xh, ST: %Xh or TO \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++ } ++ else ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ ++ u8_retry_data =0; ++ } ++} ++#endif ++ ++static void mstar_mci_send_command ++( ++ struct mstar_mci_host *pSstarHost_st, struct mmc_command *pCmd_st ++) ++{ ++ struct mmc_data *pData_st; ++ u32 u32_mie_int=0, u32_sd_ctl=0, u32_sd_mode; ++ u8 u8_retry_cmd=0, u8_retry_D0H=0; ++ ++ #if !(defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO) ++ u8 u8_retry_data=0; ++ u32 err = 0; ++ #endif ++ ++ LABEL_SEND_CMD: ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ u32_sd_mode = g_eMMCDrv.u16_Reg10_Mode; ++ pSstarHost_st->cmd = pCmd_st; ++ pData_st = pCmd_st->data; ++ ++ eMMC_FCIE_ClearEvents(); ++ if(12!=pCmd_st->opcode) ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(HW_TIMER_DELAY_500ms)) ++ { ++ u32_ok_cnt = 0; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ u8_retry_D0H++; ++ if(u8_retry_D0H < 10) ++ { ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ if(u8_retry_D0H) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: wait D0 H [ok]\n"); ++ u8_retry_D0H = 0; ++ } ++ ++ if(pData_st) ++ { ++ pData_st->bytes_xfered = 0; ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE|(u16)pData_st->blksz); ++ ++ if (pData_st->flags & MMC_DATA_READ) ++ { ++ u32_sd_ctl |= BIT_SD_DAT_EN; ++ ++ // enable stoping read clock when using scatter list DMA ++ //if(pData_st->sg_len > 1) ++ if(pCmd_st->opcode == 18) ++ u32_sd_mode |= BIT_SD_DMA_R_CLK_STOP; ++ else ++ u32_sd_mode &= ~BIT_SD_DMA_R_CLK_STOP; ++ ++ mstar_mci_pre_dma_read(pSstarHost_st); ++ } ++ } ++ ++ u32_sd_ctl |= BIT_SD_CMD_EN; ++ u32_mie_int |= BIT_SD_CMD_END; ++ REG_FCIE_W(FCIE_CIFC_ADDR(0), (((pCmd_st->arg >> 24)<<8) | (0x40|pCmd_st->opcode))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), ((pCmd_st->arg & 0xFF00) | ((pCmd_st->arg>>16)&0xFF))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), (pCmd_st->arg & 0xFF)); ++ ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_NONE) ++ { ++ u32_sd_ctl &= ~BIT_SD_RSP_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 0); ++ } ++ else ++ { ++ u32_sd_ctl |= BIT_SD_RSP_EN; ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_R2) ++ { ++ u32_sd_ctl |= BIT_SD_RSPR2_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 16); /* (136-8)/8 */ ++ } ++ else ++ { ++ REG_FCIE_W(FCIE_RSP_SIZE, 5); /*(48-8)/8 */ ++ } ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC: INT_EN: %Xh\n", u32_mie_int); ++ REG_FCIE_W(FCIE_MIE_INT_EN, u32_mie_int); ++ #endif ++ ++ #if 0 ++ //eMMC_debug(0,0,"\n"); ++ eMMC_debug(0,0,"cmd:%u, arg:%Xh, buf:%Xh, ST:%Xh, mode:%Xh, ctrl:%Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, (u32)pData_st, ++ REG_FCIE(FCIE_SD_STATUS), u32_sd_mode, u32_sd_ctl); ++ //eMMC_debug(0,0,"cmd:%u arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ //while(1); ++ #endif ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ switch(pCmd_st->opcode) ++ { ++ case 17: ++ case 18: ++ if(18 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD18++; ++ else if(17 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD17++; ++ ++ if(g_eMMCDrv.u32_Addr_RLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_RHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_RLast = pCmd_st->arg; ++ ++ case 24: ++ case 25: ++ if(25 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD25++; ++ else if(24 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD24++; ++ ++ if(g_eMMCDrv.u32_Addr_WLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_WHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_WLast = pCmd_st->arg; ++ } ++ ++ #endif ++ ++ // ----------------------------------- ++ if((pCmd_st->opcode==12)||(pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ { ++ eMMC_CheckPowerCut(); ++ } ++ ++ REG_FCIE_W(FCIE_SD_MODE, u32_sd_mode); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl); ++ // [FIXME]: retry and timing, and omre... ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, ++ HW_TIMER_DELAY_1s) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)))// || 0==u8_retry_cmd) ++ { ++ // ------------------------------------ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if(NULL==pData_st) // no data, no retry ++ { ++ mstar_mci_completed_command(pSstarHost_st); ++ return; ++ } ++ #endif ++ ++ // ------------------------------------ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: cmd.%u arg.%Xh St: %Xh, retry %u \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS), u8_retry_cmd); ++ if(u8_retry_cmd < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_cmd++; ++ if(12==pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ #endif ++ return; ++ } ++ ++ if(25==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ if(u8_retry_cmd) ++ eMMC_debug(0,0,"eMMC: CMD retry ok\n"); ++ ++ if(pData_st) ++ { ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ schedule_work(&pSstarHost_st->async_work); ++ #else ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pSstarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ err = mstar_mci_post_dma_read(pSstarHost_st); ++ } ++ ++ if( err ) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ } ++ #endif ++ } ++ else ++ { ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd without data ++ ++ if( pCmd_st->opcode == 23 ) ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); // CMD18 or CMD25 ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ } ++ } ++ ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *host, struct mmc_data *data, struct mstar_mci_host_next *next) ++{ ++ int dma_len; ++ ++ /* Check if next job is already prepared */ ++ if (next || (!next && data->host_cookie != host->next_data.cookie)) ++ { ++ dma_len = dma_map_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ else ++ { ++ dma_len = host->next_data.dma_len; ++ host->next_data.dma_len = 0; ++ } ++ ++ if (dma_len == 0) ++ return -EINVAL; ++ ++ if (next) ++ { ++ next->dma_len = dma_len; ++ data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; ++ } ++ ++ return 0; ++} ++ ++ ++static void mstar_mci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, bool is_first_req) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if( mrq->data->host_cookie ) ++ { ++ mrq->data->host_cookie = 0; ++ return; ++ } ++ ++ if (mstar_mci_pre_dma_transfer(host, mrq->data, &host->next_data)) ++ mrq->data->host_cookie = 0; ++ ++} ++ ++static void mstar_mci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ struct mmc_data *data = mrq->data; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if (data->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ ++ data->host_cookie = 0; ++} ++#endif ++#endif ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st) ++{ ++ struct mstar_mci_host *pSstarHost_st; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ if (!pMRQ_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMRQ_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ ++ pSstarHost_st->request = pMRQ_st; ++ ++ // --------------------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ eMMC_Init_Device(); ++ } ++ ++ #ifdef CONFIG_MP_EMMC_TRIM ++ switch(pSstarHost_st->request->cmd->opcode) ++ { ++ case 35: ++ eMMC_CMD35_CMD36(pSstarHost_st->request->cmd->arg, 35); ++ break; ++ case 36: ++ eMMC_CMD35_CMD36(pSstarHost_st->request->cmd->arg, 36); ++ break; ++ case 38: ++ eMMC_CMD38(); ++ break; ++ default: ++ break; ++ } ++ #endif ++ ++ if(NULL == pSstarHost_st->request->cmd->data && 6 != pSstarHost_st->request->cmd->opcode) ++ { ++ pSstarHost_st->cmd = pSstarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ return; ++ } ++ if(6 == pSstarHost_st->request->cmd->opcode && ++ (((pSstarHost_st->request->cmd->arg & 0xff0000) == 0xB70000)|| ++ ((pSstarHost_st->request->cmd->arg & 0xff0000) == 0xB90000))) ++ { ++ pSstarHost_st->cmd = pSstarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ return; ++ } ++ #endif ++ // --------------------------------------------- ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pSstarHost_st->request->sbc) ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++} ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pSstarHost_st) ++{ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ u16 au16_cifc[32], u16_i; ++ u8 *pTemp; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != eMMC_ReturnRsp((u8*)au16_cifc, (u8)pCmd_st->opcode)) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ //eMMC_debug(0,0,"eMMC Info: no rsp\n"); ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3-(u16_i%4)) + 4*(u16_i/4)] = ++ (u8)(au16_cifc[(u16_i+1)/2] >> 8*((u16_i+1)%2)); ++ } ++ #if 0 ++ eMMC_debug(0,1,"------------------\n"); ++ eMMC_dump_mem((u8*)&(pCmd_st->resp[0]), 0x10); ++ eMMC_debug(0,1,"------------------\n"); ++ #endif ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++} ++#endif ++ ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st) ++{ ++ /* Define Local Variables */ ++ struct mstar_mci_host *pSstarHost_st; ++ static u8 u8_IfLock=0; ++ ++ if(0 == (REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ //eMMC_debug(0,1,"lock\n"); ++ } ++ ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ goto LABEL_END; ++ } ++ if (!pIOS_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pIOS_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "eMMC: clock: %u, bus_width %Xh \n", ++ // pIOS_st->clock, pIOS_st->bus_width); ++ ++ // ---------------------------------- ++ if (pIOS_st->clock == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "eMMC Warn: disable clk \n"); ++ eMMC_clock_gating(); ++ } ++ // ---------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ else ++ { eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ } ++ pSstarHost_st->sd_mod = (BIT_SD_DEFAULT_MODE_REG & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ #else ++ // ---------------------------------- ++ else ++ { ++ pSstarHost_st->sd_mod = BIT_SD_DEFAULT_MODE_REG; ++ ++ if(pIOS_st->clock > CLK_400KHz) ++ { ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ else ++ { eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ } ++ ++ if (pIOS_st->bus_width == MMC_BUS_WIDTH_8) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ } ++ else if (pIOS_st->bus_width == MMC_BUS_WIDTH_4) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_4; ++ } ++ else ++ { g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK); ++ } ++ #endif ++ ++ LABEL_END: ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ //eMMC_debug(0,1,"unlock\n"); ++ } ++} ++ ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st) ++{ ++ s32 read_only; ++ ++ read_only = 0; ++ if(!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ read_only = -EINVAL; ++ } ++ ++ return read_only; ++} ++ ++//======================================================================= ++static void mstar_mci_enable(struct mstar_mci_host *pSstarHost_st) ++{ ++ u32 u32_err; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ eMMC_PlatformInit(); ++ ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ ++ u32_err = eMMC_FCIE_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Init fail: %Xh \n", u32_err); ++} ++ ++static void mstar_mci_disable(struct mstar_mci_host *pSstarHost_st) ++{ ++ u32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Reset fail: %Xh\n", u32_err); ++ eMMC_clock_gating(); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_trigger_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_trigger); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_trigger_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_trigger = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_trigger)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_trigger > 1) ++ return -EINVAL; ++ gu32_pwrsvr_gpio_trigger = u32_pwrsvr_gpio_trigger; ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_trigger, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_trigger_show, ++ fcie_pwrsvr_gpio_trigger_store); ++ ++static ssize_t fcie_pwrsvr_gpio_bit_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_bit); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_bit_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_bit = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_bit)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_bit) ++ { ++ if(u32_pwrsvr_gpio_bit > 0xF) ++ return -EINVAL; ++ gu32_pwrsvr_gpio_bit = u32_pwrsvr_gpio_bit; ++ } ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_bit, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_bit_show, ++ fcie_pwrsvr_gpio_bit_store); ++ ++static ssize_t fcie_pwrsvr_gpio_addr_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "0x%X\n", gu32_pwrsvr_gpio_addr); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_addr_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_addr = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_addr)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_addr) ++ gu32_pwrsvr_gpio_addr = u32_pwrsvr_gpio_addr; ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_addr, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_addr_show, ++ fcie_pwrsvr_gpio_addr_store); ++ ++static ssize_t fcie_pwrsvr_gpio_enable_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_enable); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_enable_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_enable = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(u8_enable_sar5) ++ return count; ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_enable)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_enable) ++ gu32_pwrsvr_gpio_enable = u32_pwrsvr_gpio_enable; ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_enable, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_enable_show, ++ fcie_pwrsvr_gpio_enable_store); ++ ++ ++static ssize_t emmc_sanitize_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_emmc_sanitize); ++} ++ ++static ssize_t emmc_sanitize_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_temp = 0; ++ ++ if(kstrtoul(buf, 0, &u32_temp)) ++ return -EINVAL; ++ ++ gu32_emmc_sanitize = u32_temp; ++ //printk("%Xh\n", gu32_emmc_sanitize); ++ ++ if(gu32_emmc_sanitize) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: santizing ...\n"); ++ eMMC_Sanitize(0xAA); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: done\n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(emmc_sanitize, ++ S_IRUSR | S_IWUSR, ++ emmc_sanitize_show, ++ emmc_sanitize_store); ++ ++static struct attribute *mstar_mci_attr[] = ++{ ++ &dev_attr_fcie_pwrsvr_gpio_enable.attr, ++ &dev_attr_fcie_pwrsvr_gpio_addr.attr, ++ &dev_attr_fcie_pwrsvr_gpio_bit.attr, ++ &dev_attr_fcie_pwrsvr_gpio_trigger.attr, ++ &dev_attr_emmc_sanitize.attr, ++ NULL, ++}; ++ ++static struct attribute_group mstar_mci_attr_grp = ++{ ++ .attrs = mstar_mci_attr, ++}; ++ ++static s32 mstar_mci_probe(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pSstarHost_st; ++ s32 s32_ret; ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ eMMC_debug(0,0,"eMMC: has SD 0722\n"); ++ #else ++ eMMC_debug(0,0,"eMMC: no SD 0722\n"); ++ #endif ++ ++ // -------------------------------- ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pDev_st is NULL \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st = 0; ++ pSstarHost_st = 0; ++ s32_ret = 0; ++ g_eMMCDrv.u8_PadType = FCIE_DEFAULT_PAD; ++ g_eMMCDrv.u16_ClkRegVal = FCIE_SLOWEST_CLK; ++ // -------------------------------- ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ mstar_mci_enable(pSstarHost_st); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ pMMCHost_st = mmc_alloc_host(sizeof(struct mstar_mci_host), &pDev_st->dev); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: mmc_alloc_host fail \n"); ++ s32_ret = -ENOMEM; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st->ops = &sg_mstar_mci_ops; ++ // [FIXME]-> ++ pMMCHost_st->f_min = CLK_400KHz; ++ pMMCHost_st->f_max = CLK_200MHz; ++ pMMCHost_st->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | \ ++ MMC_VDD_31_32 | MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; ++ ++ pMMCHost_st->max_blk_count = BIT_SD_JOB_BLK_CNT_MASK; ++ pMMCHost_st->max_blk_size = 512; /* sector */ ++ pMMCHost_st->max_req_size = pMMCHost_st->max_blk_count * pMMCHost_st->max_blk_size; ++ ++ pMMCHost_st->max_seg_size = pMMCHost_st->max_req_size; ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,20) ++ pMMCHost_st->max_phys_segs = 511; ++ pMMCHost_st->max_hw_segs = 511; ++ #else ++ pMMCHost_st->max_segs = 511; // (2^12-1)*512/4096 ++ #endif ++ //--------------------------------------- ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ pSstarHost_st->mmc = pMMCHost_st; ++ //--------------------------------------- ++ ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_NONREMOVABLE; ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ pMMCHost_st->caps |= MMC_CAP_CMD23; ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_TRIM ++ pMMCHost_st->caps |= MMC_CAP_ERASE; ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_CACHE ++ pMMCHost_st->caps2 |= MMC_CAP2_CACHE_CTRL; ++ #endif ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(3,1,10) ++ pMMCHost_st->caps2 |= MMC_CAP2_NO_SLEEP_CMD; ++ #endif ++ pSstarHost_st->baseaddr = (void __iomem *)FCIE0_BASE; ++ // <-[FIXME] ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ pSstarHost_st->next_data.cookie = 1; ++ INIT_WORK(&pSstarHost_st->async_work, mstar_mci_send_data); ++ #endif ++ #endif ++ ++ mmc_add_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, pMMCHost_st); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ s32_ret = request_irq(E_IRQ_NFIE, eMMC_FCIE_IRQ, IRQF_SHARED, DRIVER_NAME, pSstarHost_st); ++ if (s32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: request_irq fail \n"); ++ mmc_free_host(pMMCHost_st); ++ goto LABEL_END; ++ } ++ #endif ++ ++ // For getting and showing device attributes from/to user space. ++ s32_ret = sysfs_create_group(&pDev_st->dev.kobj, &mstar_mci_attr_grp); ++ ++ sgp_eMMCThread_st = kthread_create(mstar_mci_Housekeep, NULL, "eMMC_bg_thread"); ++ if(IS_ERR(sgp_eMMCThread_st)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: create thread fail \n"); ++ return PTR_ERR(sgp_eMMCThread_st); ++ } ++ wake_up_process(sgp_eMMCThread_st); ++ ++ #if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++ g_eMMCDrv.u64_CNT_TotalRBlk = 0; ++ g_eMMCDrv.u64_CNT_TotalWBlk = 0; ++ writefile = create_proc_entry (procfs_name, 0644, NULL); ++ if(writefile == NULL) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Err: Can not initialize /proc/%s\n", procfs_name); ++ else ++ { ++ writefile->read_proc = procfile_read; ++ writefile->mode = S_IFREG | S_IRUGO; ++ writefile->uid = 0; ++ writefile->gid = 0; ++ writefile->size = 0x10; ++ } ++ #endif ++ ++ LABEL_END: ++ return s32_ret; ++} ++ ++static s32 __exit mstar_mci_remove(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pSstarHost_st; ++ s32 s32_ret; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ s32_ret = 0; ++ ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pDev_st is NULL\n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pMMCHost_st is NULL\n"); ++ s32_ret= -1; ++ goto LABEL_END; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove +\n"); ++ ++ mmc_remove_host(pMMCHost_st); ++ ++ mstar_mci_disable(pSstarHost_st); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ free_irq(pSstarHost_st->irq, pSstarHost_st); ++ #endif ++ ++ mmc_free_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, NULL); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove -\n"); ++ ++ LABEL_END: ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if(sgp_eMMCThread_st) ++ kthread_stop(sgp_eMMCThread_st); ++ ++ return s32_ret; ++} ++ ++#ifdef CONFIG_PM ++static s32 mstar_mci_suspend(struct platform_device *pDev_st, pm_message_t state) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ // wait for D0 high before losing eMMC Vcc ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_PlatformDeinit(); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if (pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend + \n"); ++ ret = mmc_suspend_host(pMMCHost_st); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend -, %Xh\n", ret); ++ return ret; ++} ++ ++static s32 mstar_mci_resume(struct platform_device *pDev_st) ++{ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ static u8 u8_IfLock=0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume +\n"); ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ if(0 == (REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"lock\n"); ++ } ++ ++ mstar_mci_enable(mmc_priv(pMMCHost_st)); ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"unlock\n"); ++ } ++ ++ if (pMMCHost_st) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume +\n"); ++ ret = mmc_resume_host(pMMCHost_st); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume -\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume -, %Xh\n", ret); ++ return ret; ++} ++#endif /* End ifdef CONFIG_PM */ ++ ++/****************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++static struct platform_driver sg_mstar_mci_driver = ++{ ++ .probe = mstar_mci_probe, ++ .remove = __exit_p(mstar_mci_remove), ++ ++ #ifdef CONFIG_PM ++ .suspend = mstar_mci_suspend, ++ .resume = mstar_mci_resume, ++ #endif ++ ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++struct platform_device sg_mstar_emmc_device_st = ++{ ++ .name = DRIVER_NAME, ++ .id = 0, ++ .resource = NULL, ++ .num_resources = 0, ++}; ++ ++/****************************************************************************** ++ * Init & Exit Modules ++ ******************************************************************************/ ++static s32 __init mstar_mci_init(void) ++{ ++ int err = 0; ++ u16 u16_regval = 0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"\n"); ++ ++ u16_regval = REG_FCIE(FCIE_REG16h); ++ ++ if( (u16_regval & BIT_KERN_CHK_NAND_EMMC) == BIT_KERN_CHK_NAND_EMMC ) ++ { ++ if( (u16_regval & BIT_KERN_EMMC) != BIT_KERN_EMMC ) ++ return 0; ++ } ++ ++ if((err = platform_device_register(&sg_mstar_emmc_device_st)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ if((err = platform_driver_register(&sg_mstar_mci_driver)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ return err; ++} ++ ++static void __exit mstar_mci_exit(void) ++{ ++ platform_driver_unregister(&sg_mstar_mci_driver); ++} ++ ++static int __init write_seg_size_setup(char *str) ++{ ++ wr_seg_size = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++ ++static int __init write_seg_theshold_setup(char *str) ++{ ++ wr_split_threshold = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++ ++/* SAR5=ON in set_config will enable this feature */ ++static int __init sar5_setup_for_pwr_cut(char * str) ++{ ++ if(str != NULL) ++ { ++ printk(KERN_CRIT"SAR5=%s", str); ++ if(strcmp((const char *) str, "ON") == 0) ++ u8_enable_sar5 = 1; ++ } ++ ++ return 0; ++} ++early_param("SAR5", sar5_setup_for_pwr_cut); ++ ++__setup("mmc_wrsize=", write_seg_size_setup); ++__setup("mmc_wrupsize=", write_seg_theshold_setup); ++ ++subsys_initcall(mstar_mci_init); ++//module_init(mstar_mci_init); ++module_exit(mstar_mci_exit); ++ ++MODULE_LICENSE("non-GPL"); ++MODULE_DESCRIPTION("Sstar Multimedia Card Interface driver"); ++MODULE_AUTHOR("SSTAR"); +diff --git a/drivers/sstar/emmc/unify_driver/mstar_mci.h b/drivers/sstar/emmc/unify_driver/mstar_mci.h +new file mode 100755 +index 000000000000..63f470a48350 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/mstar_mci.h +@@ -0,0 +1,71 @@ ++/* ++* mstar_mci.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef MSTAR_MCI_H ++#define MSTAR_MCI_H ++ ++#include "eMMC.h" ++ ++/****************************************************************************** ++* Function define for this driver ++******************************************************************************/ ++ ++/****************************************************************************** ++* Register Address Base ++******************************************************************************/ ++#define CLK_400KHz 400*1000 ++#define CLK_200MHz 200*1000*1000 ++ ++#define eMMC_GENERIC_WAIT_TIME (HW_TIMER_DELAY_1s*10) ++#define eMMC_READ_WAIT_TIME (HW_TIMER_DELAY_500ms) ++ ++/****************************************************************************** ++* Low level type for this driver ++******************************************************************************/ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++struct mstar_mci_host_next ++{ ++ unsigned int dma_len; ++ s32 cookie; ++}; ++#endif ++#endif ++ ++struct mstar_mci_host ++{ ++ struct mmc_host *mmc; ++ struct mmc_command *cmd; ++ struct mmc_request *request; ++ ++ void __iomem *baseaddr; ++ s32 irq; ++ ++ u16 sd_clk; ++ u16 sd_mod; ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ struct mstar_mci_host_next next_data; ++ struct work_struct async_work; ++ #endif ++ #endif ++ char name[16]; ++}; /* struct mstar_mci_host*/ ++ ++#define MSTAR_MCI_NAME "MSTAR_MCI" ++ ++#endif +diff --git a/drivers/sstar/emmc/unify_driver/mstar_mci_v5.c b/drivers/sstar/emmc/unify_driver/mstar_mci_v5.c +new file mode 100755 +index 000000000000..905813f04a10 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/mstar_mci_v5.c +@@ -0,0 +1,3547 @@ ++/* ++* mstar_mci_v5.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include "eMMC_linux.h" ++#include "mstar_mci.h" ++#include "linux/mmc/mmc.h" ++#include "./inc/api/drv_eMMC.h" ++ ++/****************************************************************************** ++ * Defines ++ ******************************************************************************/ ++#define MCI_RETRY_CNT_CMD_TO 100 ++#define MCI_RETRY_CNT_CRC_ERR 200 // avoid stack overflow ++#define MCI_RETRY_CNT_OK_CLK_UP 10 ++#define EXT_CSD_PART_CONF 179 /* R/W */ ++ ++#define EXT_CSD_BOOT_ACK(x) (x << 6) ++#define EXT_CSD_BOOT_PART_NUM(x) (x << 3) ++#define EXT_CSD_PARTITION_ACCESS(x) (x << 0) ++/****************************************************************************** ++ * * Define Global Variables ++ ******************************************************************************/ ++#if (SET_BY_DTS) ++u32 gIpSel = 0, gPadSel = 0; ++#endif ++u32 gRegBankFeie0 = 0, gRegBankFeie1 = 0, gRegBankFeie2 = 0; ++u32 gRegCkgSd = 0, gBitCkgSdGating = 0, gBitCkgSdInverse = 0, gBitCkgSdMask = 0, gBitCkgSdSrcSel = 0; ++u32 gBitCkgSdGpCtrl = 0; ++u32 gBitSdModeMask = 0, gBitSdModeSel = 0; ++u32 gRegDrivingCfg = 0, gBitDrivingClk = 0, gBitDrivingCmd = 0, gBitDrivingData = 0; ++ ++/****************************************************************************** ++ * Function Prototypes ++ ******************************************************************************/ ++static void mstar_mci_send_command(struct mstar_mci_host *pSstarHost_st, struct mmc_command *pCmd_st); ++static void mstar_mci_completed_command(struct mstar_mci_host *pSstarHost_st); ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pSstarHost_st); ++#endif ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *pSstarHost_st, struct mmc_data *data, struct mstar_mci_host_next *next); ++#endif ++ ++u32 mstar_mci_WaitD0High(u32 u32_us); ++ ++ ++/***************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++static U32 u32_ok_cnt = 0; ++static struct task_struct *sgp_eMMCThread_st = NULL; ++#if 0 ++static ulong wr_seg_size = 0; ++static ulong wr_split_threshold = 0; ++#endif ++u8 u8_enable_sar5 = 0; ++U32 MIU0_BUS_ADDR=0; ++#if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++static int fcie_irq = 0; ++#endif ++// =============================== ++// for /sys files ++#if 0 ++U32 gu32_pwrsvr_gpio_enable = 0; ++U32 gu32_pwrsvr_gpio_addr = 0; ++U32 gu32_pwrsvr_gpio_bit = 0; ++U32 gu32_pwrsvr_gpio_trigger = 0; ++U32 gu32_emmc_sanitize = 0; ++#endif ++U32 gu32_eMMC_read_log_enable =0; ++U32 gu32_eMMC_write_log_enable =0; ++U32 gu32_eMMC_monitor_enable=0; ++U32 gu32_eMMC_read_cnt =0; ++U32 gu32_eMMC_write_cnt =0; ++U32 gu32_eMMC_boot_part_config =0; ++static unsigned long long gu64_jiffies_org; ++static unsigned long long gu64_jiffies_write=0,gu64_jiffies_read=0; ++ ++U16 u16_OldPLLClkParam=0xFFFF; ++U16 u16_OldPLLDLLClkParam=0xFFFF; ++ ++#define FCIE_ADMA_DESC_COUNT 512 ++//struct _AdmaDescriptor eMMC_ALIGN0 gAdmaDesc_st[FCIE_ADMA_DESC_COUNT] eMMC_ALIGN1; ++struct _AdmaDescriptor *gAdmaDesc_st = NULL; ++ ++ ++#if defined(MSTAR_EMMC_CONFIG_OF) ++struct clk_data{ ++ int num_parents; ++ struct clk **clk_fcie; ++ //struct clk *clk_ecc; ++}; ++struct clk_data* clkdata; ++#endif ++ ++ ++/***************************************************************************** ++ * for profiling ++ ******************************************************************************/ ++#if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++static struct proc_dir_entry * writefile; ++const char procfs_name[] = "StorageBytes"; ++ ++int procfile_read(char* buffer, char ** buffer_location, off_t offset, ++ int buffer_length, int *eof, void *data) ++{ ++ int ret; ++ ++ if(offset > 0) ++ ret = 0; ++ else ++ { ++ ret = sprintf(buffer, ++ "TotalWriteBytes %llu GB %llu MB\nTotalReadBytes %llu GB %llu MB\n", ++ g_eMMCDrv.u64_CNT_TotalWBlk/1024/1024/2, ++ (g_eMMCDrv.u64_CNT_TotalWBlk/1024/2) % 1024, ++ g_eMMCDrv.u64_CNT_TotalRBlk/1024/1024/2, ++ (g_eMMCDrv.u64_CNT_TotalRBlk/1024/2) % 1024); ++ } ++ ++ return ret; ++} ++#endif ++ ++/****************************************************************************** ++ * Functions ++ ******************************************************************************/ ++static int mstar_mci_get_dma_dir(struct mmc_data *data) ++{ ++ #if defined(CONFIG_ENABLE_EMMC_ACP) && CONFIG_ENABLE_EMMC_ACP ++ ++ return DMA_ACP; ++ ++ #else ++ ++ if (data->flags & MMC_DATA_WRITE) ++ return DMA_TO_DEVICE; ++ else ++ return DMA_FROM_DEVICE; ++ ++ #endif ++} ++ ++#if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++static int mstar_mci_config_ecsd(struct mmc_data *pData_st) ++{ ++ struct scatterlist *pSG_st = 0; ++ dma_addr_t dmaaddr = 0; ++ int err = 0; ++ u8 *pBuf; ++ #if 0 ++ int i; ++ #endif ++ ++ if( !pData_st ) ++ { ++ return -EINVAL; ++ } ++ ++ if(0 ==(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ pSG_st = &pData_st->sg[0]; ++ dmaaddr = sg_dma_address(pSG_st); ++ ++ pBuf = (u8*)phys_to_virt(dmaaddr); ++ #if 0 ++ for(i=0; i<512; i++) ++ { ++ if( (i&0xF) == 0x0 ) eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%03X: ", i); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%02X ", pBuf[i]); ++ if( (i&0xF) == 0xF ) eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "\n"); ++ } ++ #endif ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((pBuf[215]<<24)| ++ (pBuf[214]<<16)| ++ (pBuf[213]<< 8)| ++ (pBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = pBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ if(!g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = pBuf[183]; ++ ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ } ++ ++ //-------------------------------- ++ if(pBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(pBuf[503]&BIT0) // HPI ++ { ++ if(pBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ } ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(pBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = pBuf[222]; ++ #else ++ if((pBuf[503]&BIT0) && 1==pBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(pBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = pBuf[222]; ++ else ++ { ++ //eMMC_debug(0,1,"eMMC Warn: not support dynamic Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = pBuf[181]; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ECSD184_Stroe_Support = pBuf[184]; ++ g_eMMCDrv.u8_ECSD185_HsTiming = pBuf[185]; ++ g_eMMCDrv.u8_ECSD192_Ver = pBuf[192]; ++ g_eMMCDrv.u8_ECSD196_DevType = pBuf[196]; ++ g_eMMCDrv.u8_ECSD197_DriverStrength = pBuf[197]; ++ g_eMMCDrv.u8_ECSD248_CMD6TO = pBuf[248]; ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO = pBuf[247]; ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl = pBuf[34]; ++ ++ //for GP Partition ++ g_eMMCDrv.u8_ECSD160_PartSupField = pBuf[160]; ++ g_eMMCDrv.u8_ECSD224_HCEraseGRPSize= pBuf[224]; ++ g_eMMCDrv.u8_ECSD221_HCWpGRPSize= pBuf[221]; ++ ++ g_eMMCDrv.GP_Part[0].u32_PartSize = ((pBuf[145] << 16) | ++ (pBuf[144] << 8) | ++ (pBuf[143])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[1].u32_PartSize = ((pBuf[148] << 16) | ++ (pBuf[147] << 8) | ++ (pBuf[146])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[2].u32_PartSize = ((pBuf[151] << 16) | ++ (pBuf[150] << 8) | ++ (pBuf[149])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[3].u32_PartSize = ((pBuf[154] << 16) | ++ (pBuf[153] << 8) | ++ (pBuf[152])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ //for Max Enhance Size ++ g_eMMCDrv.u8_ECSD157_MaxEnhSize_0= pBuf[157]; ++ g_eMMCDrv.u8_ECSD158_MaxEnhSize_1= pBuf[158]; ++ g_eMMCDrv.u8_ECSD159_MaxEnhSize_2= pBuf[159]; ++ ++ g_eMMCDrv.u8_u8_ECSD155_PartSetComplete = pBuf[155]; ++ g_eMMCDrv.u8_ECSD166_WrRelParam = pBuf[166]; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_INIT_DONE; ++ ++ } ++ ++ return err; ++} ++#endif ++ ++#if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ ++static void mstar_mci_pre_adma_read(struct mstar_mci_host *pSstarHost_st) ++{ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = pData_st->sg; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 u32_dma_addr = 0; ++ int i; ++ ++ if( pData_st->sg_len > FCIE_ADMA_DESC_COUNT ) ++ { ++ eMMC_die("mstar_mci_pre_adma_read: sglist has more than FCIE_ADMA_DESC_COUNT items. Must change 512 to larger value.\n"); ++ } ++ ++ if(gAdmaDesc_st == NULL) ++ gAdmaDesc_st = kmalloc(sizeof(struct _AdmaDescriptor)*FCIE_ADMA_DESC_COUNT, GFP_KERNEL | GFP_DMA); ++ memset(gAdmaDesc_st, 0, sizeof(struct _AdmaDescriptor)*FCIE_ADMA_DESC_COUNT); ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"gAdmaDesc_st=0x%x\n", (U32)gAdmaDesc_st); ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pSstarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ // Flush L3, For sg_buffer DMA_FROM_DEVICE. ++ Chip_Flush_MIU_Pipe(); ++ ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ for(i=0; isg_len; i++) ++ { ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_read_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 2; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 1; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 0; ++ } ++ ++ gAdmaDesc_st[i].u32_Address = (u32)dmaaddr; ++ gAdmaDesc_st[i].u32_DmaLen = dmalen; ++ if(dmalen >= 0x200) ++ { ++ gAdmaDesc_st[i].u32_JobCnt = (dmalen >> 9); ++ //eMMC_debug(0,0," %Xh JobCnt\n", (dmalen >> 9)); ++ } ++ else ++ { // should be only one sg element ++ gAdmaDesc_st[i].u32_JobCnt = 1; ++ REG_FCIE_W(FCIE_BLK_SIZE, dmalen); ++ //eMMC_debug(0,0," %Xh bytes\n", dmalen); ++ } ++ ++ pSG_st = sg_next(pSG_st); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen / 512); ++ g_eMMCDrv.u32_RBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ gAdmaDesc_st[pData_st->sg_len-1].u32_End = 1; ++ ++ // Flush L1,L2,L3, For gAdmaDesc_st. ++ Chip_Flush_Cache_Range((uintptr_t)gAdmaDesc_st, sizeof(struct _AdmaDescriptor)*pData_st->sg_len); ++ ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(virt_to_phys(gAdmaDesc_st), 0); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_dma_addr >> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, 0x0010); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,0x0000); ++ ++} ++ ++static U32 mstar_mci_post_adma_read(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS) || ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_R_CRC_ERR|BIT_DAT_RD_TOUT))) ++ { ++ if(REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ return eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ } ++ #if defined(eMMC_EMULATE_WR_FAIL) &&eMMC_EMULATE_WR_FAIL ++ if(!(prandom_u32() % 1000)) ++ { ++ return eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ } ++ #endif ++ pData_st->bytes_xfered = pData_st->blocks * pData_st->blksz; ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_RBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinRBlk[g_eMMCDrv.u32_RBlk_tmp]++; ++ if(g_eMMCDrv.u32_RBlk_tmp > g_eMMCDrv.u32_CNT_MaxRBlk) ++ g_eMMCDrv.u32_CNT_MaxRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ if(g_eMMCDrv.u32_RBlk_tmp < g_eMMCDrv.u32_CNT_MinRBlk) ++ g_eMMCDrv.u32_CNT_MinRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_RLast += g_eMMCDrv.u32_RBlk_tmp; ++ g_eMMCDrv.u32_RBlk_tmp = 0; ++ #endif ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(gu32_eMMC_read_log_enable) ++ { ++ eMMC_debug(0,0,"\n"); ++ if(pCmd_st->opcode==17) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh\n",pCmd_st->opcode, pCmd_st->arg); ++ } ++ else if(pCmd_st->opcode==18) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh, blk cnt:%xh\n",pCmd_st->opcode, pCmd_st->arg ,pData_st->blocks); ++ } ++ } ++ ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pSstarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pSstarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#else ++ ++static void mstar_mci_pre_dma_read(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = &pData_st->sg[0]; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pSstarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ // Flush L3, For sg_buffer DMA_FROM_DEVICE. ++ Chip_Flush_MIU_Pipe(); ++ ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU2_SELECT); ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU1_SELECT); ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, dmaaddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, dmaaddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, dmalen & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, dmalen >> 16); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen/512); ++ g_eMMCDrv.u32_RBlk_tmp = (dmalen/512); ++ #endif ++ ++} ++ ++static U32 mstar_mci_post_dma_read(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = &(pData_st->sg[0]); ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ int i; ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)& (BIT_SD_R_CRC_ERR|BIT_DAT_RD_TOUT))) ++ { ++ if(REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ return eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ if(gu32_eMMC_monitor_enable) ++ gu32_eMMC_read_cnt++; ++ ++ for(i=1; isg_len; i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ pSG_st = sg_next(pSG_st); ++ ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_read_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU2_SELECT); ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU1_SELECT); ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, dmaaddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, dmaaddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, dmalen & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, dmalen >> 16); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++// REG_FCIE_R(FCIE_SD_MODE, sdmode); ++// REG_FCIE_W(FCIE_SD_MODE, sdmode | BIT_SD_DMA_R_CLK_STOP); ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_ERR_DET_ON); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS)|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_R_CRC_ERR|BIT_DAT_RD_TOUT))) ++ { ++ if(REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS)); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ u32_err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ goto dma_read_end; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ // ----------------------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen / 512); ++ g_eMMCDrv.u32_RBlk_tmp += (dmalen / 512); ++ #endif ++ ++ } ++ ++ dma_read_end: ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_RBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinRBlk[g_eMMCDrv.u32_RBlk_tmp]++; ++ if(g_eMMCDrv.u32_RBlk_tmp > g_eMMCDrv.u32_CNT_MaxRBlk) ++ g_eMMCDrv.u32_CNT_MaxRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ if(g_eMMCDrv.u32_RBlk_tmp < g_eMMCDrv.u32_CNT_MinRBlk) ++ g_eMMCDrv.u32_CNT_MinRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_RLast += g_eMMCDrv.u32_RBlk_tmp; ++ g_eMMCDrv.u32_RBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(gu32_eMMC_read_log_enable) ++ { ++ eMMC_debug(0,0,"\n"); ++ if(pCmd_st->opcode==17) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh\n",pCmd_st->opcode, pCmd_st->arg); ++ } ++ else if(pCmd_st->opcode==18) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh, blk cnt:%xh\n",pCmd_st->opcode, pCmd_st->arg ,pData_st->blocks); ++ } ++ } ++ ++ if( !u32_err ) // success ++ { ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pSstarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pSstarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ } ++ } ++ ++ return u32_err; ++} ++ ++#endif ++ ++static U32 mstar_mci_dma_write(struct mstar_mci_host *pSstarHost_st) ++{ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = 0; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ U32 u32_dma_addr = 0; ++ #endif ++ int i; ++ ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ if( pData_st->sg_len > FCIE_ADMA_DESC_COUNT ) ++ { ++ eMMC_die("mstar_mci_pre_adma_read: sglist has more than FCIE_ADMA_DESC_COUNT items. Must change 512 to larger value.\n"); ++ } ++ ++ if(gAdmaDesc_st == NULL) ++ gAdmaDesc_st = kmalloc(sizeof(struct _AdmaDescriptor)*FCIE_ADMA_DESC_COUNT, GFP_KERNEL | GFP_DMA); ++ memset(gAdmaDesc_st, 0, sizeof(struct _AdmaDescriptor)*FCIE_ADMA_DESC_COUNT); ++ #endif ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pSstarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ // Flush L3, For sg_buffer DMA_TO_DEVICE. ++ Chip_Flush_MIU_Pipe(); ++ ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ pSG_st = pData_st->sg; ++ for(i=0; isg_len; i++) ++ { ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_write_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 2; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 1; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 0; ++ } ++ ++ gAdmaDesc_st[i].u32_Address = dmaaddr; ++ gAdmaDesc_st[i].u32_DmaLen = dmalen; ++ gAdmaDesc_st[i].u32_JobCnt = (dmalen >> 9); ++ ++ pSG_st = sg_next(pSG_st); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalWBlk += (dmalen / 512); ++ g_eMMCDrv.u32_WBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ gAdmaDesc_st[pData_st->sg_len-1].u32_End = 1; ++ ++ // Flush L1,L2,L3, For gAdmaDesc_st. ++ Chip_Flush_Cache_Range((uintptr_t)gAdmaDesc_st, sizeof(struct _AdmaDescriptor)*pData_st->sg_len); ++ ++ //eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(virt_to_phys(gAdmaDesc_st), 0); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_dma_addr >> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, 0x0010); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,0x0000); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DTRX_EN|BIT_SD_DAT_DIR_W|BIT_ADMA_EN|BIT_ERR_DET_ON); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DTRX_EN|BIT_SD_DAT_DIR_W|BIT_ADMA_EN|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS)|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_W_FAIL)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ ++ #if defined(eMMC_EMULATE_WR_FAIL) &&eMMC_EMULATE_WR_FAIL ++ if(!(prandom_u32() % 500)) ++ { ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ #endif ++ pData_st->bytes_xfered = pData_st->blocks * pData_st->blksz; ++ ++ #else ++ ++ pSG_st = &(pData_st->sg[0]); ++ for(i=0; isg_len; i++) ++ { ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_write_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU2_SELECT); ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU1_SELECT); ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ REG_FCIE_W(FCIE_BLK_SIZE, 512); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, dmalen>>eMMC_SECTOR_BYTECNT_BITS); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, dmaaddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, dmaaddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, dmalen & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, dmalen >> 16); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_ERR_DET_ON); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS)|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_W_FAIL)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS)); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ ++ // ----------------------------------- ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ pSG_st = sg_next(pSG_st); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalWBlk += (dmalen / 512); ++ g_eMMCDrv.u32_WBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ #endif ++ ++ dma_write_end: ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_WBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinWBlk[g_eMMCDrv.u32_WBlk_tmp]++; ++ if(g_eMMCDrv.u32_WBlk_tmp > g_eMMCDrv.u32_CNT_MaxWBlk) ++ g_eMMCDrv.u32_CNT_MaxWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ if(g_eMMCDrv.u32_WBlk_tmp < g_eMMCDrv.u32_CNT_MinWBlk) ++ g_eMMCDrv.u32_CNT_MinWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_WLast += g_eMMCDrv.u32_WBlk_tmp; ++ g_eMMCDrv.u32_WBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pSstarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(gu32_eMMC_write_log_enable) ++ { ++ eMMC_debug(0,0,"\n"); ++ if(pCmd_st->opcode==24) ++ { ++ eMMC_debug(0,0,"cmd:%u, arg:%xh\n",pCmd_st->opcode,pCmd_st->arg); ++ } ++ else if(pCmd_st->opcode==25) ++ { ++ eMMC_debug(0,0,"cmd:%u, arg:%xh, blk cnt:%xh\n",pCmd_st->opcode,pCmd_st->arg,pData_st->blocks); ++ } ++ } ++ ++ if( !err ) ++ { ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pSstarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pSstarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ } ++ } ++ ++ return err; ++} ++ ++static void mstar_mci_completed_command(struct mstar_mci_host *pSstarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ static u32 u32_retry_cnt = 0; ++ static u32 u32_run_cnt = 0; ++ u16 u16_st; ++ u16 u16_i; ++ u8 *pTemp; ++ ++ u32_run_cnt++; ++ ++ // ---------------------------------- ++ // retrun response from FCIE to mmc driver ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3 - (u16_i % 4)) + (4 * (u16_i / 4))] = ++ (u8)(REG_FCIE(FCIE_CMDFIFO_BASE_ADDR+(((u16_i+1)/2)*4)) >> (8*((u16_i+1)%2))); ++ } ++ #if 0 ++ eMMC_debug(0,0,"------------------\n"); ++ eMMC_debug(0,1,"resp[0]: %08Xh\n", pCmd_st->resp[0]); ++ eMMC_debug(0,1,"CIFC: %04Xh %04Xh %04Xh \n", REG_FCIE(FCIE_CMDFIFO_BASE_ADDR), ++ REG_FCIE(FCIE_CMDFIFO_BASE_ADDR+4), REG_FCIE(FCIE_CMDFIFO_BASE_ADDR+8)); ++ //eMMC_dump_mem(pTemp, 0x10); ++ eMMC_debug(0,0,"------------------\n"); ++ #endif ++ ++ // ---------------------------------- ++ u16_st = REG_FCIE(FCIE_SD_STATUS); ++ if((u16_st & BIT_SD_FCIE_ERR_FLAGS) || (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ ++ if((u16_st & BIT_SD_RSP_CRC_ERR) && !(mmc_resp_type(pCmd_st) & MMC_RSP_CRC)) ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ if((pCmd_st->opcode == 1) &&((pCmd_st->resp[0]>>31) & BIT0)) ++ g_eMMCDrv.u8_IfSectorMode= (pCmd_st->resp[0] >>30) & BIT0; ++ } ++ else ++ { ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: ST:%Xh, CMD:%u, retry: %u, flag: %Xh, R1 err: %Xh\n", ++ u16_st, pCmd_st->opcode, u32_retry_cnt, g_eMMCDrv.u32_DrvFlag, ++ pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY); ++ ++ u32_ok_cnt = 0; ++ ++ if(u32_retry_cnt++ >= MCI_RETRY_CNT_CRC_ERR) ++ eMMC_FCIE_ErrHandler_Stop(); // fatal error ++ ++ if(25==pCmd_st->opcode || 12==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_hw_timer_sleep(1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ ++ if(0 != pCmd_st->data) ++ { ++ eMMC_FCIE_ErrHandler_Retry(); // slow dwon clock ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++ } ++ else // for CMD12 ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: no data, just reset eMMC. \n"); ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ return; ++ } ++ ++ if(0==u32_retry_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: retry ok \n"); ++ return; ++ } ++ ++ //----------------------------------------- ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: ST:%Xh, CMD:%u, arg:%xh, retry:%u \n", ++ u16_st, pCmd_st->opcode, pCmd_st->arg , pCmd_st->retries); ++ #endif ++ ++ // should be trivial ++ if(u16_st & (BIT_SD_RSP_TIMEOUT)) ++ pCmd_st->error = -ETIMEDOUT; ++ else if(u16_st & (BIT_SD_RSP_CRC_ERR | BIT_SD_R_CRC_ERR | BIT_SD_W_CRC_ERR)) ++ pCmd_st->error = -EILSEQ; ++ else ++ pCmd_st->error = -EIO; ++ } ++ } ++ else ++ { ++ #if 0 ++ u16 u16_Tmp; ++ ++ // To prevent res bit shift ++ u16_Tmp = REG_FCIE(FCIE_CMDFIFO_BASE_ADDR); ++ ++ if( (mmc_resp_type(pCmd_st) == MMC_RSP_R2) || ++ (mmc_resp_type(pCmd_st) == MMC_RSP_R3) ) ++ { ++ if( (u16_Tmp & 0x3F) != 0x3F ) ++ { ++ pCmd_st->error = -EILSEQ; ++ eMMC_debug(0, 1, "CMD%d response buffer error\n", pCmd_st->opcode); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ else ++ { ++ if( (u16_Tmp & 0xFF) != pCmd_st->opcode ) ++ { ++ pCmd_st->error = -EILSEQ; ++ eMMC_debug(0, 1, "CMD%d response buffer error\n", pCmd_st->opcode); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ #endif ++ ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ ++ ++ if((pCmd_st->opcode == 17) || (pCmd_st->opcode == 18) || ++ (pCmd_st->opcode == 24) || (pCmd_st->opcode == 25) || ++ (pCmd_st->opcode == 12)) //stop transmission ++ { ++ if(pCmd_st->resp[0] & eMMC_ERR_R1_31_0) ++ { ++ pCmd_st->error |= -EIO; ++ ++ if(pCmd_st->opcode == 12) ++ eMMC_debug(0,0, "eMMC Warn: CMD12 R1 error: %Xh \n", pCmd_st->resp[0]); ++ else ++ eMMC_debug(0,0, "eMMC Warn: CMD%u R1 error: %Xh, arg %08x, blocks %08x\n", ++ pCmd_st->opcode, pCmd_st->resp[0], pCmd_st->arg, pCmd_st->data->blocks); ++ } ++ } ++ ++ #if 0 ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt) ++ { ++ eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++} ++ ++#define WAIT_D0H_POLLING_TIME HW_TIMER_DELAY_100us ++u32 mstar_mci_WaitD0High(u32 u32_us) ++{ ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ ++ REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_BUSY_DET_ON); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // enable busy int ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_BUSY_END_INT); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_BUSY_END_INT, u32_us) != eMMC_ST_SUCCESS) ++ { ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++ ++ #else ++ ++ u32 u32_cnt, u32_wait; ++ ++ for(u32_cnt=0; u32_cnt HW_TIMER_DELAY_1ms) ++ { ++ //msleep(1); ++ //schedule_hrtimeout is more precise and can reduce idle time of emmc ++ ++ { ++ ktime_t expires = ktime_add_ns(ktime_get(), 1000 * 1000); ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ schedule_hrtimeout(&expires, HRTIMER_MODE_ABS); ++ } ++ ++ u32_cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ ++ #endif ++} ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static void mstar_mci_send_data(struct work_struct *work) ++{ ++ struct mstar_mci_host *pSstarHost_st = container_of(work, struct mstar_mci_host, async_work); ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ static u8 u8_retry_data = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pSstarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ err = mstar_mci_post_adma_read(pSstarHost_st); ++ #else ++ err = mstar_mci_post_dma_read(pSstarHost_st); ++ #endif ++ } ++ ++ if( err ) ++ { ++ u32_ok_cnt = 0; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w, cmd.%u arg.%Xh, ST: %Xh or TO\n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r, cmd.%u arg.%Xh, ST: %Xh or TO \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pSstarHost_st->request->sbc) ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++ } ++ else ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ eMMC_dump_mem((U8*)gAdmaDesc_st, (U32)(sizeof(struct _AdmaDescriptor)*(pData_st->sg_len+1))); ++ #endif ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: cmd.%u arg.%Xh: data retry ok \n",pCmd_st->opcode, pCmd_st->arg); ++ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if( pCmd_st->opcode == 8 ) ++ { ++ mstar_mci_config_ecsd(pData_st); ++ } ++ #endif ++ ++ u8_retry_data =0; ++ if(gu32_eMMC_monitor_enable) ++ { ++ if((pCmd_st->opcode==17)||(pCmd_st->opcode==18)) ++ gu64_jiffies_read += (jiffies_64 - gu64_jiffies_org); ++ else if((pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ gu64_jiffies_write += (jiffies_64 - gu64_jiffies_org); ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ } ++} ++#endif ++ ++static void mstar_mci_send_command(struct mstar_mci_host *pSstarHost_st, struct mmc_command *pCmd_st) ++{ ++ u32 u32_mie_int = 0; ++ u32 u32_sd_ctl = 0; ++ u32 u32_sd_mode = 0; ++ static u8 u8_retry_cmd = 0; ++ u8 u8_retry_D0H = 0; ++ struct mmc_data *pData_st; ++ ++ #if !(defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO) ++ static u8 u8_retry_data=0; ++ #endif ++ u32 err = 0; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC: cmd.%u arg.%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ ++ LABEL_SEND_CMD: ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ u32_sd_mode = g_eMMCDrv.u16_Reg10_Mode; ++ pSstarHost_st->cmd = pCmd_st; ++ pData_st = pCmd_st->data; ++ ++ eMMC_FCIE_ClearEvents(); ++ ++ #if 0 ++ if(12!=pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ u32_ok_cnt = 0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ ++ u8_retry_D0H++; ++ if(u8_retry_D0H < 10) ++ { ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ } ++ ++ if(u8_retry_D0H) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: wait D0 H [ok]\n"); ++ u8_retry_D0H = 0; ++ } ++ #endif ++ ++ if(pData_st) ++ { ++ pData_st->bytes_xfered = 0; ++ ++ if (pData_st->flags & MMC_DATA_READ) ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ u32_sd_ctl |= (BIT_SD_DAT_EN | BIT_ADMA_EN | BIT_ERR_DET_ON); ++ mstar_mci_pre_adma_read(pSstarHost_st); ++ #else ++ u32_sd_ctl |= (BIT_SD_DAT_EN | BIT_ERR_DET_ON); ++ ++ // enable stoping read clock when using scatter list DMA ++ if(pCmd_st->opcode == 18) ++ u32_sd_mode |= BIT_SD_DMA_R_CLK_STOP; ++ else ++ u32_sd_mode &= ~BIT_SD_DMA_R_CLK_STOP; ++ ++ mstar_mci_pre_dma_read(pSstarHost_st); ++ #endif ++ } ++ } ++ ++ u32_sd_ctl |= BIT_SD_CMD_EN; ++ u32_mie_int |= BIT_SD_CMD_END; ++ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, 0x00), ++ (((pCmd_st->arg >> 24)<<8) | (0x40|pCmd_st->opcode))); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, 0x01), ++ ((pCmd_st->arg & 0xFF00) | ((pCmd_st->arg>>16)&0xFF))); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, 0x02), ++ (pCmd_st->arg & 0xFF)); ++ ++ REG_FCIE_CLRBIT(FCIE_CMD_RSP_SIZE, BIT_RSP_SIZE_MASK); ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_NONE) ++ { ++ u32_sd_ctl &= ~BIT_SD_RSP_EN; ++ } ++ else ++ { ++ u32_sd_ctl |= BIT_SD_RSP_EN; ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_R2) ++ { ++ u32_sd_ctl |= BIT_SD_RSPR2_EN; ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, 16); ++ } ++ else ++ { ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, 5); ++ } ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, u32_mie_int); ++ #endif ++ ++ #if 0 ++ //eMMC_debug(0,0,"\n"); ++ eMMC_debug(0, 1,"cmd:%u, arg:%Xh, buf:%Xh, block:%u, ST:%Xh, mode:%Xh, ctrl:%Xh \n", ++ pCmd_st->opcode, ++ pCmd_st->arg, ++ (u32)pData_st, ++ pData_st ? pData_st->blocks : 0, ++ REG_FCIE(FCIE_SD_STATUS), ++ u32_sd_mode, ++ u32_sd_ctl); ++ //eMMC_debug(0,0,"cmd:%u arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ //while(1); ++ #endif ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ switch(pCmd_st->opcode) ++ { ++ case 17: ++ case 18: ++ if(18 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD18++; ++ else if(17 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD17++; ++ ++ if(g_eMMCDrv.u32_Addr_RLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_RHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_RLast = pCmd_st->arg; ++ ++ case 24: ++ case 25: ++ if(25 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD25++; ++ else if(24 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD24++; ++ ++ if(g_eMMCDrv.u32_Addr_WLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_WHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_WLast = pCmd_st->arg; ++ } ++ ++ #endif ++ ++ #if defined(ENABLE_EMMC_POWER_SAVING_MODE) && ENABLE_EMMC_POWER_SAVING_MODE ++ // ----------------------------------- ++ if((pCmd_st->opcode==12)||(pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ { ++ eMMC_CheckPowerCut(); ++ } ++ #endif ++ if(gu32_eMMC_monitor_enable) ++ { ++ if((pCmd_st->opcode==17)||(pCmd_st->opcode==18)|| ++ (pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ gu64_jiffies_org = jiffies_64; ++ } ++ REG_FCIE_W(FCIE_SD_MODE, u32_sd_mode); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl|BIT_JOB_START); ++ ++ // [FIXME]: retry and timing, and omre... ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, HW_TIMER_DELAY_1s) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ // ------------------------------------ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if(NULL==pData_st ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && NULL==pSstarHost_st->request->sbc ++ #endif ++ ) // no data, no retry ++ { ++ mstar_mci_completed_command(pSstarHost_st); ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ return; ++ } ++ #endif ++ ++ // ------------------------------------ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: cmd.%u arg.%Xh St: %Xh, retry %u \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS), u8_retry_cmd); ++ ++ if(u8_retry_cmd < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_cmd++; ++ ++ if(12==pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ #endif ++ ++ return; ++ } ++ ++ #if 0 ++ if(25==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ #endif ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ u32_ok_cnt = 0; ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pSstarHost_st->request->sbc) ++ { ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->sbc); ++ return; ++ } ++ #endif ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ if(u8_retry_cmd) ++ { ++ u8_retry_cmd =0; ++ eMMC_debug(0,0,"eMMC: cmd.%u arg.%Xh CMD retry ok\n",pCmd_st->opcode, pCmd_st->arg); ++ } ++ ++ if(pData_st) ++ { ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ ++ schedule_work(&pSstarHost_st->async_work); ++ ++ #else ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pSstarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ err = mstar_mci_post_adma_read(pSstarHost_st); ++ #else ++ err = mstar_mci_post_dma_read(pSstarHost_st); ++ #endif ++ } ++ ++ if( err ) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pSstarHost_st->request->sbc) ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++ ++ } ++ else ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ eMMC_dump_mem((U8*)gAdmaDesc_st, (U32)(sizeof(struct _AdmaDescriptor)*(pData_st->sg_len+1))); ++ #endif ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if( pCmd_st->opcode == 8 ) ++ { ++ mstar_mci_config_ecsd(pData_st); ++ } ++ #endif ++ ++ if(gu32_eMMC_monitor_enable) ++ { ++ if((pCmd_st->opcode==17)||(pCmd_st->opcode==18)) ++ gu64_jiffies_read += (jiffies_64 - gu64_jiffies_org); ++ else if((pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ gu64_jiffies_write += (jiffies_64 - gu64_jiffies_org); ++ } ++ u8_retry_data =0; ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ } ++ ++ #endif ++ } ++ else ++ { ++ if( (mmc_resp_type(pCmd_st) & MMC_RSP_R1B) == MMC_RSP_R1B ) ++ { ++ err = mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ ++ while(err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ ++ u8_retry_D0H++; ++ ++ if(u8_retry_D0H < 10) ++ { ++ err = mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ eMMC_Dump_eMMCStatus(); ++ ++ mstar_mci_completed_command(pSstarHost_st); ++ ++ pCmd_st->error = -ETIMEDOUT; ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ ++ return; ++ } ++ } ++ } ++ ++ mstar_mci_completed_command(pSstarHost_st); // copy back rsp for cmd without data ++ ++ if( pCmd_st->opcode == 23 ) ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); // CMD18 or CMD25 ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ } ++ } ++} ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *host, struct mmc_data *data, struct mstar_mci_host_next *next) ++{ ++ int dma_len; ++ ++ /* Check if next job is already prepared */ ++ if (next || (!next && data->host_cookie != host->next_data.cookie)) ++ { ++ dma_len = dma_map_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ else ++ { ++ dma_len = host->next_data.dma_len; ++ host->next_data.dma_len = 0; ++ } ++ ++ if (dma_len == 0) ++ return -EINVAL; ++ ++ if (next) ++ { ++ next->dma_len = dma_len; ++ data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; ++ } ++ ++ return 0; ++} ++ ++ ++static void mstar_mci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, bool is_first_req) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if( mrq->data->host_cookie ) ++ { ++ mrq->data->host_cookie = 0; ++ return; ++ } ++ ++ if (mstar_mci_pre_dma_transfer(host, mrq->data, &host->next_data)) ++ mrq->data->host_cookie = 0; ++} ++ ++static void mstar_mci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ struct mmc_data *data = mrq->data; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if (data->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ ++ data->host_cookie = 0; ++} ++#endif ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st) ++{ ++ struct mstar_mci_host *pSstarHost_st; ++ ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ return; ++ } ++ ++ if (!pMRQ_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMRQ_st is NULL \n"); ++ return; ++ } ++ ++ pSstarHost_st->request = pMRQ_st; ++ ++ // SD command filter ++ if( (pSstarHost_st->request->cmd->opcode == 52) || ++ (pSstarHost_st->request->cmd->opcode == 55) || ++ ((pSstarHost_st->request->cmd->opcode == 8) && pSstarHost_st->request->cmd->arg) || ++ ((pSstarHost_st->request->cmd->opcode == 5) && (pSstarHost_st->request->cmd->arg == 0)) ) ++ { ++ pSstarHost_st->request->cmd->error = -ETIMEDOUT; ++ ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++ ++ return; ++ } ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ // --------------------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ eMMC_Init_Device(); ++ } ++ ++ #if 0 //def CONFIG_MP_EMMC_TRIM ++ switch(pSstarHost_st->request->cmd->opcode) ++ { ++ case 35: ++ eMMC_CMD35_CMD36(pSstarHost_st->request->cmd->arg, 35); ++ break; ++ case 36: ++ eMMC_CMD35_CMD36(pSstarHost_st->request->cmd->arg, 36); ++ break; ++ case 38: ++ eMMC_CMD38(); ++ break; ++ default: ++ break; ++ } ++ #endif ++ ++ if(NULL == pSstarHost_st->request->cmd->data && 6 != pSstarHost_st->request->cmd->opcode) ++ { ++ pSstarHost_st->cmd = pSstarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ return; ++ } ++ ++ #if 0 ++ if(6 == pSstarHost_st->request->cmd->opcode && ++ (((pSstarHost_st->request->cmd->arg & 0xff0000) == 0xB70000)|| ++ ((pSstarHost_st->request->cmd->arg & 0xff0000) == 0xB90000))) ++ { ++ pSstarHost_st->cmd = pSstarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pSstarHost_st); ++ return; ++ } ++ #endif ++ ++ #endif ++ ++ // --------------------------------------------- ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pSstarHost_st->request->sbc) ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pSstarHost_st, pSstarHost_st->request->cmd); ++} ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pSstarHost_st) ++{ ++ struct mmc_command *pCmd_st = pSstarHost_st->cmd; ++ u16 au16_cifc[32] = {0}; ++ u16 u16_i; ++ u8 *pTemp; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != eMMC_ReturnRsp((u8*)au16_cifc, (u8)pCmd_st->opcode)) ++ { ++ if( mmc_resp_type(pCmd_st) != MMC_RSP_NONE ) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ eMMC_debug(0,0,"eMMC Info: no rsp\n"); ++ } ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3-(u16_i%4)) + 4*(u16_i/4)] = ++ (u8)(au16_cifc[(u16_i+1)/2] >> 8*((u16_i+1)%2)); ++ } ++ #if 0 ++ eMMC_debug(0,1,"------------------\n"); ++ eMMC_dump_mem((u8*)&(pCmd_st->resp[0]), 0x10); ++ eMMC_debug(0,1,"------------------\n"); ++ #endif ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ mmc_request_done(pSstarHost_st->mmc, pSstarHost_st->request); ++} ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++static u8 u8_cur_timing = 0; ++ ++#if (defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400) ||\ ++ (defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200) ++static u32 mstar_mci_read_blocks(struct mmc_host *host, u8 *buf, ulong blkaddr, ulong blkcnt) ++{ ++ struct mmc_request mrq = {NULL}; ++ struct mmc_command cmd = {0}; ++ struct mmc_data data = {0}; ++ struct scatterlist sg; ++ ++ mrq.cmd = &cmd; ++ mrq.data = &data; ++ ++ cmd.opcode = MMC_READ_SINGLE_BLOCK; ++ cmd.arg = blkaddr; ++ ++ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; ++ ++ data.blksz = 512; ++ data.blocks = blkcnt; ++ data.flags = MMC_DATA_READ; ++ data.sg = &sg; ++ data.sg_len = 1; ++ ++ sg_init_one(&sg, buf, 512*blkcnt); ++ ++ data.timeout_ns = TIME_WAIT_1_BLK_END * 1000; ++ data.timeout_clks = 0; ++ ++ mmc_wait_for_req(host, &mrq); ++ ++ if (cmd.error) ++ return cmd.error; ++ ++ if (data.error) ++ return data.error; ++ ++ return 0; ++} ++#endif ++ ++#endif ++ ++#define UNUSED(x) ((x)=(x)) ++ ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st) ++{ ++ /* Define Local Variables */ ++ struct mstar_mci_host *pSstarHost_st; ++ static u8 u8_IfLock=0; ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ u8 u8_pad_type = 0; ++ char *s8_timing_str = 0; ++ #endif ++ ++ UNUSED(s8_timing_str); ++ UNUSED(u8_pad_type); ++ UNUSED(u8_cur_timing); ++ if(0 == (REG_FCIE(FCIE_MIE_FUNC_CTL) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ //eMMC_debug(0,1,"lock\n"); ++ } ++ ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ if (!pIOS_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pIOS_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "eMMC: clock: %u, bus_width %Xh \n", ++ // pIOS_st->clock, pIOS_st->bus_width); ++ ++ // ---------------------------------- ++ if (pIOS_st->clock == 0) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "eMMC Warn: disable clk \n"); ++ //eMMC_clock_gating(); ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ // ---------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ else ++ { ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ } ++ #else ++ // ---------------------------------- ++ else ++ { ++ if( pIOS_st->bus_width == MMC_BUS_WIDTH_8 ) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode = ++ (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ } ++ else if( pIOS_st->bus_width == MMC_BUS_WIDTH_4 ) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode = ++ (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_4; ++ } ++ else if( pIOS_st->bus_width == MMC_BUS_WIDTH_1 ) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = ++ (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK); ++ } ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ ++ if( u8_cur_timing != pIOS_st->timing ) ++ { ++ if( pIOS_st->timing == MMC_TIMING_LEGACY ) ++ { ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ ++ if( pIOS_st->clock > CLK_400KHz ) ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ else ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ u8_cur_timing = pIOS_st->timing; ++ } ++ else if( pIOS_st->timing == MMC_TIMING_MMC_HS ) ++ { ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ u8_cur_timing = pIOS_st->timing; ++ } ++ else if( (pIOS_st->timing == MMC_TIMING_UHS_DDR50) || ++ (pIOS_st->timing == MMC_TIMING_MMC_DDR52) ) ++ { ++ if(u8_IfLock==0) ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_FCIE_EnableSDRMode(); ++ if(g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_DDR) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_DDR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode DDR fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ { ++ eMMC_debug(0,0,"\neMMC: DDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ u8_cur_timing = pIOS_st->timing; ++ } ++ } ++ if(u8_IfLock==0) ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ } ++ else ++ { ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ if( pIOS_st->timing == MMC_TIMING_MMC_HS200 ) ++ { ++ u8_cur_timing = pIOS_st->timing; ++ goto LABEL_END; ++ } ++ #endif ++ ++ switch( pIOS_st->timing ) ++ { ++ case MMC_TIMING_MMC_HS200: ++ u8_pad_type = FCIE_eMMC_HS200; ++ s8_timing_str = "HS200"; ++ break; ++ case MMC_TIMING_MMC_HS400: ++ u8_pad_type = FCIE_eMMC_HS400; ++ s8_timing_str = "HS400"; ++ break; ++ } ++ ++ eMMC_pads_switch(u8_pad_type); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ eMMC_debug(0,0,"eMMC: %s %uMHz \n", s8_timing_str, g_eMMCDrv.u32_ClkKHz/1000); ++ ++ #if defined(ENABLE_eMMC_HS400)&&ENABLE_eMMC_HS400 ++ if(g_eMMCDrv.TimingTable_G_t.u8_SetCnt && u8_pad_type == FCIE_eMMC_HS400) ++ eMMC_FCIE_ApplyTimingSet(g_eMMCDrv.TimingTable_G_t.u8_CurSetIdx); ++ else ++ #endif ++ if(g_eMMCDrv.TimingTable_t.u8_SetCnt) ++ eMMC_FCIE_ApplyTimingSet(eMMC_TIMING_SET_MAX); ++ ++ u8_cur_timing = pIOS_st->timing; ++ } ++ } ++ ++ #else ++ if(pIOS_st->clock > CLK_400KHz) ++ { ++ switch( pIOS_st->timing ) ++ { ++ case MMC_TIMING_LEGACY: ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ break; ++ case MMC_TIMING_UHS_DDR50: ++ if(u8_IfLock==0) ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_FCIE_EnableSDRMode(); ++ if(g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_DDR) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_DDR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode DDR fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ eMMC_debug(0,0,"\neMMC: DDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ if(u8_IfLock==0) ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ break; ++ case MMC_TIMING_MMC_HS200: ++ eMMC_pads_switch(FCIE_eMMC_HS200); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ break; ++ case MMC_TIMING_MMC_HS400: ++ eMMC_pads_switch(FCIE_eMMC_HS400); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ break; ++ //case MMC_TIMING_MMC_HS: ++ default: ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ break; ++ } ++ } ++ else ++ { ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ #endif ++ } ++ #endif ++ ++ LABEL_END: ++ ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ //eMMC_debug(0,1,"unlock\n"); ++ } ++} ++ ++static int mstar_mci_execute_tuning(struct mmc_host *host, u32 opcode) ++{ ++ u32 u32_err = 0; ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ ++ #if 1 ++ ++ U32 u32_ChkSum; ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ mstar_mci_read_blocks(host, gau8_eMMC_SectorBuf, eMMC_HS400TABLE_BLK_0, 1); ++ #elif defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ mstar_mci_read_blocks(host, gau8_eMMC_SectorBuf, eMMC_HS200TABLE_BLK_0, 1); ++ #endif ++ ++ memcpy((U8 *)&g_eMMCDrv.TimingTable_t, gau8_eMMC_SectorBuf, ++ sizeof(g_eMMCDrv.TimingTable_t)); ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&g_eMMCDrv.TimingTable_t, ++ sizeof(g_eMMCDrv.TimingTable_t) - ++ eMMC_TIMING_TABLE_CHKSUM_OFFSET); ++ if(u32_ChkSum != g_eMMCDrv.TimingTable_t.u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: ChkSum error, no Table \n"); ++ printk("u32_ChkSum=%08X\n", u32_ChkSum); ++ printk("g_eMMCDrv.TimingTable_t.u32_ChkSum=%08X\n", ++ g_eMMCDrv.TimingTable_t.u32_ChkSum); ++ eMMC_dump_mem((U8 *)&g_eMMCDrv.TimingTable_t, ++ sizeof(g_eMMCDrv.TimingTable_t)); ++ u32_err = eMMC_ST_ERR_DDRT_CHKSUM; ++ return u32_err; ++ } ++ ++ if (0 == u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: no Table \n"); ++ u32_err = eMMC_ST_ERR_DDRT_NONA; ++ return u32_err; ++ } ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ ++ mstar_mci_read_blocks(host, gau8_eMMC_SectorBuf, ++ eMMC_HS400EXTTABLE_BLK_0, 1); ++ ++ memcpy((U8 *)&g_eMMCDrv.TimingTable_G_t, gau8_eMMC_SectorBuf, ++ sizeof(g_eMMCDrv.TimingTable_G_t)); ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&g_eMMCDrv.TimingTable_G_t.u32_VerNo, ++ (sizeof(g_eMMCDrv.TimingTable_G_t) - sizeof(U32))); ++ ++ if (u32_ChkSum != g_eMMCDrv.TimingTable_G_t.u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: ChkSum error, no Gen_TTable \n"); ++ g_eMMCDrv.TimingTable_G_t.u8_SetCnt = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_ChkSum = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_VerNo = 0; ++ u32_err = eMMC_ST_ERR_DDRT_CHKSUM; ++ return u32_err; ++ } ++ ++ if (0 == u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: no Gen_TTable \n"); ++ g_eMMCDrv.TimingTable_G_t.u8_SetCnt = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_ChkSum = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_VerNo = 0; ++ u32_err = eMMC_ST_ERR_DDRT_CHKSUM; ++ return u32_err; ++ } ++ #endif ++ ++ #else ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ if( (g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS400_1_8V) && (host->caps2 & MMC_CAP2_HS400_1_8V) ) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ u32_err = eMMC_LoadTimingTable(FCIE_eMMC_HS400); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: no Timing Table, %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ #endif ++ ++ #if defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ if( (g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS200_1_8V) && (host->caps2 & MMC_CAP2_HS200_1_8V_SDR) ) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ u32_err = eMMC_LoadTimingTable(FCIE_eMMC_HS200); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: no Timing Table, %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ #endif ++ ++ #endif ++ ++ #else ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ ++ if((g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS400_1_8V) && (host->caps2 & MMC_CAP2_HS400_1_8V_DDR) ) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_HS400)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode HS400 fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ eMMC_debug(0,0,"\neMMC: HS400 %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ ++ #endif //defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ ++ #if defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ if((g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS200_1_8V) && (host->caps2 & MMC_CAP2_HS200_1_8V_SDR)) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_HS200)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode HS200 fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ eMMC_debug(0,0,"\neMMC: HS200 %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ #endif ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ #endif ++ ++ return u32_err; ++} ++ ++//======================================================================= ++static void mstar_mci_enable(void) ++{ ++ u32 u32_err; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ //reset retry status to default ++ sgu8_IfNeedRestorePadType=0xFF; ++ u8_sdr_retry_count = 0; ++ ++ eMMC_PlatformInit(); ++ ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ g_eMMCDrv.u16_RCA=1; ++ ++ u32_err = eMMC_FCIE_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, "eMMC Err: eMMC_FCIE_Init fail: %Xh \n", u32_err); ++ ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++} ++ ++static void mstar_mci_disable(void) ++{ ++ u32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, "eMMC Err: eMMC_FCIE_Reset fail: %Xh\n", u32_err); ++ ++ eMMC_clock_gating(); ++} ++ ++#if 0 ++static ssize_t fcie_pwrsvr_gpio_trigger_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_trigger); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_trigger_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_trigger = 0; ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_trigger)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_trigger > 1) ++ return -EINVAL; ++ ++ gu32_pwrsvr_gpio_trigger = u32_pwrsvr_gpio_trigger; ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_trigger, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_trigger_show, ++ fcie_pwrsvr_gpio_trigger_store); ++ ++static ssize_t fcie_pwrsvr_gpio_bit_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_bit); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_bit_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_bit = 0; ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_bit)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_bit) ++ { ++ if(u32_pwrsvr_gpio_bit > 0xF) ++ return -EINVAL; ++ gu32_pwrsvr_gpio_bit = u32_pwrsvr_gpio_bit; ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_bit, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_bit_show, ++ fcie_pwrsvr_gpio_bit_store); ++ ++static ssize_t fcie_pwrsvr_gpio_addr_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "0x%X\n", gu32_pwrsvr_gpio_addr); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_addr_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_addr = 0; ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_addr)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_addr) ++ gu32_pwrsvr_gpio_addr = u32_pwrsvr_gpio_addr; ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_addr, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_addr_show, ++ fcie_pwrsvr_gpio_addr_store); ++ ++static ssize_t fcie_pwrsvr_gpio_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_enable); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_enable_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_enable = 0; ++ ++ #if 0 ++ if(u8_enable_sar5) ++ return count; ++ #endif ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_enable)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_enable) ++ gu32_pwrsvr_gpio_enable = u32_pwrsvr_gpio_enable; ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_enable, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_enable_show, ++ fcie_pwrsvr_gpio_enable_store); ++ ++ ++static ssize_t emmc_sanitize_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_emmc_sanitize); ++} ++ ++static ssize_t emmc_sanitize_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_temp = 0; ++ ++ if(kstrtoul(buf, 0, &u32_temp)) ++ return -EINVAL; ++ ++ gu32_emmc_sanitize = u32_temp; ++ //printk("%Xh\n", gu32_emmc_sanitize); ++ ++ if(gu32_emmc_sanitize) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: santizing ...\n"); ++ eMMC_Sanitize(0xAA); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: done\n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(emmc_sanitize, ++ S_IRUSR | S_IWUSR, ++ emmc_sanitize_show, ++ emmc_sanitize_store); ++#endif ++ ++static ssize_t eMMC_monitor_count_enable_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ U32 u32_read_bytes,u32_write_bytes; ++ U32 u32_speed_read=0,u32_speed_write=0; ++ ++ u32_read_bytes = ((gu32_eMMC_read_cnt<>3)&7; ++ } ++ ++ return sprintf(buf, "%d\n", gu32_eMMC_boot_part_config); ++} ++ ++static ssize_t eMMC_set_partconf_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_temp = 0; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ if(kstrtoul(buf, 0, &u32_temp)) ++ return -EINVAL; ++ ++ u32_err = eMMC_Init(); ++ if(u32_err) ++ { ++ printk("error: init fail !\n"); ++ return -EINVAL; ++ } ++ ++ if( !(u32_temp == 1 || u32_temp == 2) ) ++ { ++ printk("Illage boot part number! please set 0 / 1. \n"); ++ return -EINVAL; ++ } ++ ++ u32_err = eMMC_SetExtCSD(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_PART_CONF, EXT_CSD_BOOT_ACK(1) | \ ++ EXT_CSD_BOOT_PART_NUM(u32_temp) | EXT_CSD_PARTITION_ACCESS(0)); ++ if(u32_err) ++ { ++ printk("error: set boot part config fail ! \n"); ++ return u32_err; ++ } ++ gu32_eMMC_boot_part_config = u32_temp; ++ ++ return count; ++} ++ ++DEVICE_ATTR(eMMC_set_partconf, ++ S_IRUSR | S_IWUSR, ++ emmc_set_partconf_show, ++ eMMC_set_partconf_store); ++ ++#endif ++ ++static struct attribute *mstar_mci_attr[] = ++{ ++ #if 0 ++ &dev_attr_fcie_pwrsvr_gpio_enable.attr, ++ &dev_attr_fcie_pwrsvr_gpio_addr.attr, ++ &dev_attr_fcie_pwrsvr_gpio_bit.attr, ++ &dev_attr_fcie_pwrsvr_gpio_trigger.attr, ++ &dev_attr_emmc_sanitize.attr, ++ #endif ++ &dev_attr_eMMC_read_log_enable.attr, ++ &dev_attr_eMMC_write_log_enable.attr, ++ &dev_attr_eMMC_monitor_count_enable.attr, ++ &dev_attr_eMMC_set_partconf.attr, ++ NULL, ++}; ++ ++static struct attribute_group mstar_mci_attr_grp = ++{ ++ .attrs = mstar_mci_attr, ++}; ++ ++ ++static const struct mmc_host_ops sg_mstar_mci_ops = ++{ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ .pre_req = mstar_mci_pre_req, ++ .post_req = mstar_mci_post_req, ++ #endif ++ .request = mstar_mci_request, ++ .set_ios = mstar_mci_set_ios, ++ .execute_tuning = mstar_mci_execute_tuning, ++}; ++ ++#if defined(MSTAR_EMMC_CONFIG_OF) ++struct platform_device sg_mstar_emmc_device_st; ++#else ++struct platform_device sg_mstar_emmc_device_st = ++{ ++ .name = DRIVER_NAME, ++ .id = 0, ++ .resource = NULL, ++ .num_resources = 0, ++ .dev.dma_mask = &sg_mstar_emmc_device_st.dev.coherent_dma_mask, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(64), ++}; ++#endif ++ ++static s32 mstar_mci_probe(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st = 0; ++ struct mstar_mci_host *pSstarHost_st = 0; ++ s32 s32_ret = 0; ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ U16 u16_i; ++#endif ++ U32 u32_buswidth = 0; ++#if MAX_CLK_CTRL ++ U32 u32_max_clk = 0; ++#endif ++#if DRIVING_CTRL ++ U32 u32_clk_driving = 0,u32_cmd_driving = 0,u32_data_driving = 0; ++#endif ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ eMMC_debug(0,0,"eMMC: has SD 1006\n"); ++ #else ++ eMMC_debug(0,0,"eMMC: no SD 1006\n"); ++ #endif ++ ++ #if 0//defined(CONFIG_MMC_MSTAR_MMC_EMMC_CHK_VERSION) ++ if(eMMC_DRIVER_VERSION != REG_FCIE(FCIE_RESERVED_FOR_SW)) ++ { ++ eMMC_debug(0,0,"\n eMMC: please update MBoot.\n"); ++ eMMC_debug(0,0,"\n MBoot ver:%u, Kernel ver: %u\n", ++ REG_FCIE(FCIE_RESERVED_FOR_SW), eMMC_DRIVER_VERSION); ++ while(1); ++ } ++ #endif ++ // -------------------------------- ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pDev_st is NULL \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ #if defined(MSTAR_EMMC_CONFIG_OF) ++ memcpy(&sg_mstar_emmc_device_st, pDev_st, sizeof(struct platform_device)); ++ #endif ++ #if defined(MSTAR_EMMC_CONFIG_OF) ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ clkdata = kzalloc(sizeof(struct clk_data), GFP_KERNEL); ++ if(!clkdata) ++ { ++ printk(KERN_CRIT"Unable to allocate nand clock data\n"); ++ return -ENOMEM; ++ } ++ ++ clkdata->num_parents = of_clk_get_parent_count(pDev_st->dev.of_node); ++ if(clkdata->num_parents > 0) ++ { ++ clkdata->clk_fcie = kzalloc(sizeof(struct clk*) * clkdata->num_parents, GFP_KERNEL); ++ } ++ else ++ { ++ printk(KERN_ERR "Unable to get nand clk count from dts\n"); ++ return -ENODEV; ++ } ++ ++ for(u16_i = 0 ; u16_i < clkdata->num_parents; u16_i ++) ++ { ++ clkdata->clk_fcie[u16_i] = of_clk_get(pDev_st->dev.of_node, u16_i); ++ if(IS_ERR(clkdata->clk_fcie[u16_i])) ++ { ++ printk(KERN_CRIT"Unable to get nand clk from dts\n"); ++ return -ENODEV; ++ } ++ } ++#endif ++ ++#if (SET_BY_DTS) ++ if(of_property_read_u32(pDev_st->dev.of_node, "ip-select" , &gIpSel)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [ip-select] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [ip-select]: %u\n", gIpSel); ++ } ++ ++ if(of_property_read_u32(pDev_st->dev.of_node, "pad-select" , &gPadSel)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [pad-select] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [pad-select]: %u\n", gPadSel); ++ } ++ ++ if (gIpSel == 0) ++ { ++ // ++ gRegBankFeie0 = REG_BANK_FCIE0_IP_0; ++ gRegBankFeie1 = REG_BANK_FCIE1_IP_0; ++ gRegBankFeie2 = REG_BANK_FCIE2_IP_0; ++ ++ // ++ gRegCkgSd = reg_ckg_fcie_VALUE_IP_0; ++ gBitCkgSdGating = BIT_FCIE_CLK_GATING_VALUE_IP_0; ++ gBitCkgSdInverse = BIT_FCIE_CLK_INVERSE_VALUE_IP_0; ++ gBitCkgSdMask = BIT_CLKGEN_FCIE_MASK_VALUE_IP_0; ++ gBitCkgSdSrcSel = BIT_FCIE_CLK_SRC_SEL_VALUE_IP_0; ++ ++ // ++ gBitCkgSdGpCtrl = BIT_CKG_SD_VALUE_IP_0; ++ ++ // ++ if (BIT_SD_MODE_MASK_VALUE_IP_0 != 0) ++ { ++ gBitSdModeMask = BIT_SD_MODE_MASK_VALUE_IP_0; ++ } ++ else ++ { ++ pr_err(">> [emmc] ip-select: %u is not available\n", gIpSel); ++ return -ENODEV; ++ } ++ ++ if ((gPadSel == 0) && (BIT_SD_MODE_SEL_VALUE_IP_0_PAD_0 != 0)) ++ { ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE_IP_0_PAD_0; ++ } ++ else if ((gPadSel == 1) && (BIT_SD_MODE_SEL_VALUE_IP_0_PAD_1 != 0)) ++ { ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE_IP_0_PAD_1; ++ } ++ else if ((gPadSel == 2) && (BIT_SD_MODE_SEL_VALUE_IP_0_PAD_2 != 0)) ++ { ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE_IP_0_PAD_2; ++ } ++ else ++ { ++ pr_err(">> [emmc] ip-select: %u pad-select: %u is not available\n", gIpSel, gPadSel); ++ return -ENODEV; ++ } ++ } ++ else if (gIpSel == 1) ++ { ++ // ++ gRegBankFeie0 = REG_BANK_FCIE0_IP_1; ++ gRegBankFeie1 = REG_BANK_FCIE1_IP_1; ++ gRegBankFeie2 = REG_BANK_FCIE2_IP_1; ++ ++ // ++ gRegCkgSd = reg_ckg_fcie_VALUE_IP_1; ++ gBitCkgSdGating = BIT_FCIE_CLK_GATING_VALUE_IP_1; ++ gBitCkgSdInverse = BIT_FCIE_CLK_INVERSE_VALUE_IP_1; ++ gBitCkgSdMask = BIT_CLKGEN_FCIE_MASK_VALUE_IP_1; ++ gBitCkgSdSrcSel = BIT_FCIE_CLK_SRC_SEL_VALUE_IP_1; ++ ++ // ++ gBitCkgSdGpCtrl = BIT_CKG_SD_VALUE_IP_1; ++ ++ // ++ if (BIT_SD_MODE_MASK_VALUE_IP_1 != 0) ++ { ++ gBitSdModeMask = BIT_SD_MODE_MASK_VALUE_IP_1; ++ } ++ else ++ { ++ pr_err(">> [emmc] ip-select: %u is not available\n", gIpSel); ++ return -ENODEV; ++ } ++ ++ if ((gPadSel == 0) && (BIT_SD_MODE_SEL_VALUE_IP_1_PAD_0 != 0)) ++ { ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE_IP_1_PAD_0; ++ } ++ else if ((gPadSel == 1) && (BIT_SD_MODE_SEL_VALUE_IP_1_PAD_1 != 0)) ++ { ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE_IP_1_PAD_1; ++ } ++ else if ((gPadSel == 2) && (BIT_SD_MODE_SEL_VALUE_IP_1_PAD_2 != 0)) ++ { ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE_IP_1_PAD_2; ++ } ++ else ++ { ++ pr_err(">> [emmc] ip-select: %u pad-select: %u is not available\n", gIpSel, gPadSel); ++ return -ENODEV; ++ } ++ } ++ else ++ { ++ pr_err(">> [emmc] get dts [ip-select]: %u is not available\n", gIpSel); ++ } ++ ++ ++#if DRIVING_CTRL ++ // ++ if (gPadSel == 0) ++ { ++ if (reg_driving_config_VALUE_PAD_0 == 0xFFFF) ++ { ++ pr_err(">> [emmc] pad-select: %u drving is not available\n", gPadSel); ++ return -ENODEV; ++ } ++ ++ gRegDrivingCfg = reg_driving_config_VALUE_PAD_0; ++ gBitDrivingClk = BIT_DRIVING_CLK_VALUE_PAD_0; ++ gBitDrivingCmd = BIT_DRIVING_CMD_VALUE_PAD_0; ++ gBitDrivingData = BIT_DRIVING_DATA_VALUE_PAD_0; ++ ++ } ++ else if (gPadSel == 1) ++ { ++ if (reg_driving_config_VALUE_PAD_1 == 0xFFFF) ++ { ++ pr_err(">> [emmc] pad-select: %u drving is not available\n", gPadSel); ++ return -ENODEV; ++ } ++ ++ gRegDrivingCfg = reg_driving_config_VALUE_PAD_1; ++ gBitDrivingClk = BIT_DRIVING_CLK_VALUE_PAD_1; ++ gBitDrivingCmd = BIT_DRIVING_CMD_VALUE_PAD_1; ++ gBitDrivingData = BIT_DRIVING_DATA_VALUE_PAD_1; ++ } ++ else if (gPadSel == 2) ++ { ++ if (reg_driving_config_VALUE_PAD_2 == 0xFFFF) ++ { ++ pr_err(">> [emmc] pad-select: %u drving is not available\n", gPadSel); ++ return -ENODEV; ++ } ++ ++ gRegDrivingCfg = reg_driving_config_VALUE_PAD_2; ++ gBitDrivingClk = BIT_DRIVING_CLK_VALUE_PAD_2; ++ gBitDrivingCmd = BIT_DRIVING_CMD_VALUE_PAD_2; ++ gBitDrivingData = BIT_DRIVING_DATA_VALUE_PAD_2; ++ } ++#endif ++ ++ // PE ++ if (gPadSel == 0) ++ { ++#ifdef SET_PE_ENABLE_PAD_0 ++ SET_PE_ENABLE_PAD_0 ++#endif ++ } ++ else if (gPadSel == 1) ++ { ++#ifdef SET_PE_ENABLE_PAD_1 ++ SET_PE_ENABLE_PAD_1 ++#endif ++ } ++ else if (gPadSel == 2) ++ { ++#ifdef SET_PE_ENABLE_PAD_2 ++ SET_PE_ENABLE_PAD_2 ++#endif ++ } ++ ++#else ++ ++ // ++ gRegBankFeie0 = REG_BANK_FCIE0; ++ gRegBankFeie1 = REG_BANK_FCIE1; ++ gRegBankFeie2 = REG_BANK_FCIE2; ++ ++ // ++ gRegCkgSd = reg_ckg_fcie_VALUE; ++ gBitCkgSdGating = BIT_FCIE_CLK_GATING_VALUE; ++ gBitCkgSdInverse = BIT_FCIE_CLK_INVERSE_VALUE; ++ gBitCkgSdMask = BIT_CLKGEN_FCIE_MASK_VALUE; ++ gBitCkgSdSrcSel = BIT_FCIE_CLK_SRC_SEL_VALUE; ++ ++ // ++ gBitCkgSdGpCtrl = BIT_CKG_SD_VALUE; ++ ++ // ++ gBitSdModeMask = BIT_SD_MODE_MASK_VALUE; ++ gBitSdModeSel = BIT_SD_MODE_SEL_VALUE; ++ ++#if DRIVING_CTRL ++ // ++ gRegDrivingCfg = reg_driving_config_VALUE; ++ gBitDrivingClk = BIT_DRIVING_CLK_VALUE; ++ gBitDrivingCmd = BIT_DRIVING_CMD_VALUE; ++ gBitDrivingData = BIT_DRIVING_DATA_VALUE; ++#endif ++ ++ // PE ++#ifdef SET_PE_ENABLE ++ SET_PE_ENABLE ++#endif ++ ++#endif ++ ++ if(of_property_read_u32(pDev_st->dev.of_node, "bus-width" , &u32_buswidth)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [bus-width] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [bus-width]: %u\n", u32_buswidth); ++ } ++ ++#if MAX_CLK_CTRL ++ ++ if(of_property_read_u32(pDev_st->dev.of_node, "max-clks" , &u32_max_clk)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [max-clks] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [max-clks]: %u\n", u32_max_clk); ++ } ++ ++ eMMC_SetMaxClk(u32_max_clk); ++ ++#endif ++ ++#if DRIVING_CTRL ++ ++ if(of_property_read_u32(pDev_st->dev.of_node, "clk-driving" , &u32_clk_driving)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [clk-driving] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [clk-driving]: %u\n", u32_clk_driving); ++ } ++ ++ if(of_property_read_u32(pDev_st->dev.of_node, "cmd-driving" , &u32_cmd_driving)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [cmd-driving] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [cmd-driving]: %u\n", u32_cmd_driving); ++ } ++ ++ if(of_property_read_u32(pDev_st->dev.of_node, "data-driving" , &u32_data_driving)) ++ { ++ pr_err(">> [emmc] Err: Could not get dts [data-driving] option!\n"); ++ return -ENODEV; ++ } else { ++ pr_err(">> [emmc] get dts [data-driving]: %u\n", u32_data_driving); ++ } ++ ++ if (u32_clk_driving) ++ { ++ REG_FCIE_SETBIT(reg_driving_config, BIT_DRIVING_CLK); ++ } ++ else ++ { ++ REG_FCIE_CLRBIT(reg_driving_config, BIT_DRIVING_CLK); ++ } ++ ++ if (u32_cmd_driving) ++ { ++ REG_FCIE_SETBIT(reg_driving_config, BIT_DRIVING_CMD); ++ } ++ else ++ { ++ REG_FCIE_CLRBIT(reg_driving_config, BIT_DRIVING_CMD); ++ } ++ ++ if (u32_data_driving) ++ { ++ REG_FCIE_SETBIT(reg_driving_config, BIT_DRIVING_DATA); ++ } ++ else ++ { ++ REG_FCIE_CLRBIT(reg_driving_config, BIT_DRIVING_DATA); ++ } ++ ++#endif ++ ++ #endif ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ g_eMMCDrv.u16_ClkRegVal = FCIE_SLOWEST_CLK; ++ ++ // -------------------------------- ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ mstar_mci_enable(); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++#if defined(MSTAR_EMMC_CONFIG_OF) ++ g_eMMCDrv.u16_of_buswidth = u32_buswidth; ++#else ++ // FIXME: force 8 bit bus width if not DTS configuration. ++ g_eMMCDrv.u16_of_buswidth = 8; ++ pr_err(">> [emmc] force 8 bit bus width, no DTS cfg bus:%u\n", g_eMMCDrv.u16_of_buswidth); ++#endif ++ ++ pMMCHost_st = mmc_alloc_host(sizeof(struct mstar_mci_host), &pDev_st->dev); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: mmc_alloc_host fail \n"); ++ s32_ret = -ENOMEM; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st->ops = &sg_mstar_mci_ops; ++ ++ // [FIXME]-> ++ pMMCHost_st->f_min = CLK_400KHz; ++ pMMCHost_st->f_max = CLK_200MHz; ++ pMMCHost_st->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | \ ++ MMC_VDD_31_32 | MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; ++ ++ pMMCHost_st->max_blk_count = BIT_SD_JOB_BLK_CNT_MASK; ++ pMMCHost_st->max_blk_size = 512; ++ pMMCHost_st->max_req_size = pMMCHost_st->max_blk_count * pMMCHost_st->max_blk_size; //could be optimized ++ ++ pMMCHost_st->max_seg_size = pMMCHost_st->max_req_size; ++ pMMCHost_st->max_segs = 32; ++ ++ //--------------------------------------- ++ pSstarHost_st = mmc_priv(pMMCHost_st); ++ pSstarHost_st->mmc = pMMCHost_st; ++ ++ //--------------------------------------- ++#if defined(reg_emmc_4bit_mod) ++ switch(g_eMMCDrv.u16_of_buswidth) { ++ case 4: ++ pMMCHost_st->caps = MMC_CAP_4_BIT_DATA; ++ if(Chip_Get_Revision() == 2) REG_FCIE_SETBIT(reg_emmc_4bit_mod, BIT_4BIT_MODE_MASK); ++ break; ++ case 8: ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA; ++ if(Chip_Get_Revision() == 2) REG_FCIE_CLRBIT(reg_emmc_4bit_mod, BIT_4BIT_MODE_MASK); ++ break; ++ default: ++ pr_err(">> [emmc] Err: wrong buswidth config: %u!\n", g_eMMCDrv.u16_of_buswidth); ++ // FIXME: fall back to 8bits ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA; ++ if(Chip_Get_Revision() == 2) REG_FCIE_CLRBIT(reg_emmc_4bit_mod, BIT_4BIT_MODE_MASK); ++ break; ++ }; ++#elif defined(BIT_EMMC_MODE_8X) ++ REG_FCIE_CLRBIT(reg_emmc_config, BIT_EMMC_MODE_MASK); ++ switch(g_eMMCDrv.u16_of_buswidth) { ++ case 1: ++ pMMCHost_st->caps = MMC_CAP_1_BIT_DATA; ++ REG_FCIE_SETBIT(reg_emmc_config, BIT_EMMC_MODE_1); ++ break; ++ case 4: ++ pMMCHost_st->caps = MMC_CAP_4_BIT_DATA; ++ REG_FCIE_SETBIT(reg_emmc_config, BIT_EMMC_MODE_1); ++ break; ++ case 8: ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA; ++ REG_FCIE_SETBIT(reg_emmc_config, BIT_EMMC_MODE_8X); ++ break; ++ default: ++ pr_err(">> [emmc] Err: wrong buswidth config: %u!\n", g_eMMCDrv.u16_of_buswidth); ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA; ++ REG_FCIE_SETBIT(reg_emmc_config, BIT_EMMC_MODE_8X); ++ break; ++ }; ++#else //reg_emmc_4bit_mod is not defined. it does not support mmc ++ pMMCHost_st->caps = MMC_CAP_4_BIT_DATA; ++#endif ++ ++ pMMCHost_st->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_NONREMOVABLE; ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ pMMCHost_st->caps |= MMC_CAP_CMD23; ++ #endif ++ ++ #if (defined(ENABLE_eMMC_ATOP)&&ENABLE_eMMC_ATOP) ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ pMMCHost_st->caps2 |= MMC_CAP2_HS400_1_8V; ++ #else ++ pMMCHost_st->caps2 |= MMC_CAP2_HS400_1_8V_DDR; ++ #endif ++ #endif ++ ++ #if defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ pMMCHost_st->caps2 |= MMC_CAP2_HS200_1_8V_SDR; ++ #endif ++ ++ pMMCHost_st->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50; ++ ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_TRIM ++ pMMCHost_st->caps |= MMC_CAP_ERASE; ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_CACHE ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) ++ pMMCHost_st->caps2 |= MMC_CAP2_CACHE_CTRL; ++ #endif ++ #endif ++ ++// #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,1) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) ++// pMMCHost_st->caps2 |= MMC_CAP2_NO_SLEEP_CMD; ++// #endif ++ strcpy(pSstarHost_st->name,MSTAR_MCI_NAME); ++ ++ // <-[FIXME] ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ pSstarHost_st->next_data.cookie = 1; ++ INIT_WORK(&pSstarHost_st->async_work, mstar_mci_send_data); ++ #endif ++ ++ mmc_add_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, pMMCHost_st); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ fcie_irq = platform_get_irq(pDev_st, 0); ++ if (fcie_irq < 0) ++ return -ENXIO; ++ ++ s32_ret = request_irq(fcie_irq, eMMC_FCIE_IRQ, IRQF_SHARED, DRIVER_NAME, pSstarHost_st); ++ if (s32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: request_irq fail \n"); ++ mmc_free_host(pMMCHost_st); ++ goto LABEL_END; ++ } ++ #endif ++ ++ #if 1 ++ // For getting and showing device attributes from/to user space. ++ s32_ret = sysfs_create_group(&pDev_st->dev.kobj, &mstar_mci_attr_grp); ++ #endif ++ ++ sgp_eMMCThread_st = kthread_create(mstar_mci_Housekeep, NULL, "eMMC_bg_thread"); ++ if(IS_ERR(sgp_eMMCThread_st)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: create thread fail \n"); ++ return PTR_ERR(sgp_eMMCThread_st); ++ } ++ wake_up_process(sgp_eMMCThread_st); ++ ++ #if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++ g_eMMCDrv.u64_CNT_TotalRBlk = 0; ++ g_eMMCDrv.u64_CNT_TotalWBlk = 0; ++ writefile = create_proc_entry (procfs_name, 0644, NULL); ++ if(writefile == NULL) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Err: Can not initialize /proc/%s\n", procfs_name); ++ else ++ { ++ writefile->read_proc = procfile_read; ++ writefile->mode = S_IFREG | S_IRUGO; ++ writefile->uid = 0; ++ writefile->gid = 0; ++ writefile->size = 0x10; ++ } ++ #endif ++ ++ LABEL_END: ++ ++ return s32_ret; ++} ++ ++static s32 __exit mstar_mci_remove(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st = platform_get_drvdata(pDev_st); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ struct mstar_mci_host *pSstarHost_st = mmc_priv(pMMCHost_st); ++ #endif ++ s32 s32_ret = 0; ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ U16 u16_i; ++#endif ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pDev_st is NULL\n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pMMCHost_st is NULL\n"); ++ s32_ret= -1; ++ goto LABEL_END; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove +\n"); ++ ++ mmc_remove_host(pMMCHost_st); ++ ++ mstar_mci_disable(); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ free_irq(fcie_irq, pSstarHost_st); ++ #endif ++ ++ mmc_free_host(pMMCHost_st); ++ ++ platform_set_drvdata(pDev_st, NULL); ++ ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ if(clkdata) ++ { ++ if(clkdata->clk_fcie) ++ { ++ for(u16_i = 0 ; u16_i < clkdata->num_parents; u16_i ++) ++ { ++ clk_put(clkdata->clk_fcie[u16_i]); ++ } ++ kfree(clkdata->clk_fcie); ++ } ++ kfree(clkdata); ++ } ++#endif ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove -\n"); ++ ++ LABEL_END: ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if(sgp_eMMCThread_st) ++ kthread_stop(sgp_eMMCThread_st); ++ ++ return s32_ret; ++} ++ ++#ifdef CONFIG_PM ++static s32 mstar_mci_suspend(struct platform_device *pDev_st, pm_message_t state) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st = platform_get_drvdata(pDev_st); ++ s32 ret = 0; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ // wait for D0 high before losing eMMC Vcc ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_CMD0(0); mdelay(10); //msleep(10); ++ eMMC_PlatformDeinit(); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if (pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend + \n"); ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) ++ ret = mmc_suspend_host(pMMCHost_st); ++ #endif ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend -, %Xh\n", ret); ++ ++ u16_OldPLLClkParam = 0xFFFF; ++ u16_OldPLLDLLClkParam = 0xFFFF; ++ ++ return ret; ++} ++ ++static s32 mstar_mci_resume(struct platform_device *pDev_st) ++{ ++ struct mmc_host *pMMCHost_st = platform_get_drvdata(pDev_st); ++ s32 ret = 0; ++ static u8 u8_IfLock = 0; ++ ++ if(0 == (REG_FCIE(FCIE_MIE_FUNC_CTL) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"lock\n"); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume +\n"); ++#if defined(MSTAR_EMMC_CONFIG_OF) ++ //enable clock here with clock framework ++ { ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ int i; ++ for(i = 0 ;i < clkdata->num_parents; i ++) ++ clk_prepare_enable(clkdata->clk_fcie[i]); ++#endif ++ } ++#endif ++ ++ mstar_mci_enable(); ++ ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"unlock\n"); ++ } ++ ++ if (pMMCHost_st) ++ { ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) ++ ret = mmc_resume_host(pMMCHost_st); ++ #endif ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume -\n"); ++ ++ return ret; ++} ++#endif /* End ifdef CONFIG_PM */ ++ ++/****************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++ #if defined(MSTAR_EMMC_CONFIG_OF) ++static struct of_device_id ms_mstar_mci_dt_ids[] = { ++ { ++ .compatible = DRIVER_NAME ++ }, ++ {}, ++}; ++#endif ++ ++static struct platform_driver sg_mstar_mci_driver = ++{ ++ .probe = mstar_mci_probe, ++ .remove = __exit_p(mstar_mci_remove), ++ ++ #ifdef CONFIG_PM ++ .suspend = mstar_mci_suspend, ++ .resume = mstar_mci_resume, ++ #endif ++ ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++#if defined(MSTAR_EMMC_CONFIG_OF) ++ .of_match_table = ms_mstar_mci_dt_ids, ++#endif ++ }, ++}; ++ ++extern int Chip_Boot_Get_Dev_Type(void); ++extern unsigned long long Chip_MIU_to_Phys(unsigned long long phys); ++ ++/****************************************************************************** ++ * Init & Exit Modules ++ ******************************************************************************/ ++static s32 __init mstar_mci_init(void) ++{ ++ int err = 0; ++ ++ #if 0 ++ if(MS_BOOT_DEV_EMMC!=(MS_BOOT_DEV_TYPE)Chip_Boot_Get_Dev_Type()) ++ { ++ pr_info("[eMMC] skipping device initialization\n"); ++ return -1; ++ } ++ #endif ++ ++ memset(&g_eMMCDrv, 0, sizeof(eMMC_DRIVER)); ++ MIU0_BUS_ADDR=Chip_MIU_to_Phys(0);//get the MIU0 base; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"\n"); ++ ++#if !defined(MSTAR_EMMC_CONFIG_OF) ++ if((err = platform_device_register(&sg_mstar_emmc_device_st)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++#endif ++ ++ if((err = platform_driver_register(&sg_mstar_mci_driver)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ return err; ++} ++ ++static void __exit mstar_mci_exit(void) ++{ ++ platform_driver_unregister(&sg_mstar_mci_driver); ++} ++bool mstar_mci_is_mstar_host(struct mmc_card* card) ++{ ++ struct mstar_mci_host *mci_host; ++ ++ if( NULL==(card) ++ || NULL==(card->host) ++ || NULL==(mci_host=((struct mstar_mci_host *)card->host->private) ) ++ || 0!=strncmp(mci_host->name,MSTAR_MCI_NAME,strlen(MSTAR_MCI_NAME)) ++ ) ++ { ++ return false; ++ } ++ else ++ { ++ return true; ++ } ++ ++} ++ ++EXPORT_SYMBOL(mstar_mci_is_mstar_host); ++ ++#if 0 ++static int __init write_seg_size_setup(char *str) ++{ ++ wr_seg_size = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++ ++static int __init write_seg_theshold_setup(char *str) ++{ ++ wr_split_threshold = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++#endif ++ ++/* SAR5=ON in set_config will enable this feature */ ++#if 0 ++static int __init sar5_setup_for_pwr_cut(char * str) ++{ ++ if(str != NULL) ++ { ++ printk(KERN_CRIT"SAR5=%s", str); ++ if(strcmp((const char *) str, "ON") == 0) ++ u8_enable_sar5 = 1; ++ } ++ ++ return 0; ++} ++early_param("SAR5", sar5_setup_for_pwr_cut); ++#endif ++ ++#if 0 ++__setup("mmc_wrsize=", write_seg_size_setup); ++__setup("mmc_wrupsize=", write_seg_theshold_setup); ++#endif ++ ++#ifndef CONFIG_MS_EMMC_MODULE ++#if !defined(MSTAR_EMMC_CONFIG_OF) ++subsys_initcall(mstar_mci_init); ++#endif ++#endif ++module_init(mstar_mci_init); ++module_exit(mstar_mci_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Sstar Multimedia Card Interface driver"); ++MODULE_AUTHOR("SSTAR"); +diff --git a/drivers/sstar/emmc/unify_driver/src/api/eMMC_prg.c b/drivers/sstar/emmc/unify_driver/src/api/eMMC_prg.c +new file mode 100755 +index 000000000000..6dab4898b12e +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/src/api/eMMC_prg.c +@@ -0,0 +1,2514 @@ ++/* ++* eMMC_prg.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include "../../inc/common/eMMC.h" ++ ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++/* frequency bases */ ++/* divided by 10 to be nice to platforms without floating point */ ++int fbase[] = { ++ 10000, ++ 100000, ++ 1000000, ++ 10000000, ++}; ++ ++/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice ++ * to platforms without floating point. ++ */ ++int multipliers[] = { ++ 0, /* reserved */ ++ 10, ++ 12, ++ 13, ++ 15, ++ 20, ++ 25, ++ 30, ++ 35, ++ 40, ++ 45, ++ 50, ++ 55, ++ 60, ++ 70, ++ 80, ++}; ++ ++//======================================================== ++ ++#ifndef IP_FCIE_VERSION_5 ++ ++U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt) ++{ ++ U32 u32_err, u32_i; ++ U16 u16_reg, u16_retry=0; ++ ++ // -------------------------------- ++ eMMC_PlatformInit(); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ //*(U16*)0x25020DD4 &= ~BIT6; // FPGA only ++ ++ LABEL_BOOT_MODE_START: ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ // -------------------------------- ++ eMMC_RST_L(); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1ms); ++ eMMC_RST_H(); ++ ++ u32_i = 0; ++ while(u32_i < u32_ItemCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"i:%u SecCnt:%Xh \n", u32_i, pu32_SectorCnt[u32_i]); ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, pu32_SectorCnt[u32_i]); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, pu32_Addr[u32_i] & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, pu32_Addr[u32_i] >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (pu32_Addr[u32_i]>>3) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(pu32_Addr[u32_i]>>3) >> 16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ if(0 == u32_i) // stg.1 ++ { ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_MODE_EN); ++ } ++ else // stg.2 ++ { ++ // can NOT set BIT_SD_DAT_EN ++ //REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_STG2_EN); ++ } ++ ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE, HW_TIMER_DELAY_1s); ++ ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((0==u16_retry) && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ u16_retry++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #if 0 ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ #endif ++ goto LABEL_BOOT_MODE_START; ++ } ++ #if 0 ++ else if(u16_retry && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry fail, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ } ++ #endif ++ u32_i++; ++ } ++ ++ // -------------------------------- ++ // boot end ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_END_EN); ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_CARD_BOOT_DONE, HW_TIMER_DELAY_1s); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_LOAD_IMAGE_END: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: %Xh\n", u32_err); ++ return u32_err; ++} ++ ++#endif ++ ++ ++//======================================================== ++U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID) ++{ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ *pu8IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(pu8ID, g_eMMCDrv.au8_ID, eMMC_ID_BYTE_CNT); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++// data length is 512 bytes ++U32 eMMC_FATAutoSize(void) ++{ ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ volatile U32 u32_PartSectorCnt=0; ++ ++ // calculate FAT sector cnt ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ ++ else if(u32_PartSectorCnt) ++ u32_PartSectorCnt += ++ (pPartInfo->records[u16_i].u16_BlkCnt + pPartInfo->records[u16_i].u16_BackupBlkCnt) ++ * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ g_eMMCDrv.u32_FATSectorCnt = g_eMMCDrv.u32_SEC_COUNT - u32_PartSectorCnt; ++ ++ u32_PartSectorCnt = 0; ++ // shift the StartBlk for partitions following FAT ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ { ++ pPartInfo->records[u16_i].u16_BlkCnt = ++ g_eMMCDrv.u32_FATSectorCnt / pPartInfo->u16_BlkPageCnt; ++ ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk + ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ else if(u32_PartSectorCnt) ++ { ++ pPartInfo->records[u16_i].u16_StartBlk = u32_PartSectorCnt; ++ ++ u32_PartSectorCnt += ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U32 eMMC_ReadPartitionInfo_Ex(void) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // read Partition Info from Blk0 and Blk1 (check) ++ for(u16_i=0; u16_iu32_ChkSum || pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info %u ChkSum failed: %Xh %Xh\n", ++ u16_i, pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: found Part Info %u\n", u16_i); ++ break; ++ } ++ } ++ ++ // print msg ++ if(eMMC_CIS_PNI_BLK_CNT== u16_i) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: no valid Partition Info\n"); ++ return eMMC_ST_ERR_NO_PART_INFO; ++ } ++ else{ ++ // calculate FAT capacity ++ eMMC_FATAutoSize(); ++ //eMMC_debug(0,1,"Total Sec: %Xh, FAT Sec: %Xh \n", g_eMMCDrv.u32_SEC_COUNT, g_eMMCDrv.u32_FATSectorCnt); ++ } ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_GET_PART_INFO; ++ return u32_err; ++} ++ ++ ++// data length is 512 bytes ++U32 eMMC_ReadPartitionInfo(U8 *pu8_Data) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_GET_PART_INFO)) ++ { ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadPartitionInfo_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ } ++ ++ memcpy(pu8_Data, gau8_eMMC_PartInfoBuf, 0x200); ++ ++ return eMMC_ST_SUCCESS; ++} ++U32 eMMC_CheckCIS(eMMC_CIS_t *ptCISData) ++{ ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ U32 u32_ChkSum; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ if (eMMC_CompareCISTag(peMMCInfo->au8_Tag)) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI Tag mismatch\n"); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&peMMCInfo->u16_SpareByteCnt, (U16)((U32)(&peMMCInfo->u16_SeqAccessTime)-(U32)(&peMMCInfo->u16_SpareByteCnt))); ++ if (u32_ChkSum != peMMCInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, peMMCInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)peMMCInfo, 0x200); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&pPartInfo->u16_SpareByteCnt, 0x200-0x04); ++ if (u32_ChkSum != pPartInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pni chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, pPartInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)pPartInfo, 0x200); ++ return eMMC_ST_ERR_CIS_PNI; ++ } ++ ++ eMMC_dump_nni(peMMCInfo); ++ eMMC_dump_pni(pPartInfo); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++// read CIS and set config to UNFD ++U32 eMMC_ReadCIS(eMMC_CIS_t *ptCISData) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ // read NNI in Blk0 and Blk1 ++ for(u16_i=0; u16_iu32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SpareByteCnt: %04Xh \n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PageByteCnt: %04Xh \n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkPageCnt: %04Xh \n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartitionCnt: %04Xh \n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"RecByteCnt: %04Xh \n", pPartInfo->u16_UnitByteCnt); ++ ++ u32_PniBlkByteCnt = pPartInfo->u16_PageByteCnt * pPartInfo->u16_BlkPageCnt; ++ u32_PniBlkCnt = 0; ++ ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Partition: %02u \n", u16_i); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"StartBlk: %04Xh \n", pPartInfo->records[u16_i].u16_StartBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->records[u16_i].u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartType: %04Xh \n", pPartInfo->records[u16_i].u16_PartType); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BackupBlkCnt:%04Xh \n", pPartInfo->records[u16_i].u16_BackupBlkCnt); ++ ++ if(u16_i < pPartInfo->u16_PartCnt-1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u KB\n", ++ (u32_PniBlkByteCnt * pPartInfo->records[u16_i].u16_BlkCnt)>>10); ++ ++ u32_PniBlkCnt += pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u MB\n", ++ (g_eMMCDrv.u32_SEC_COUNT - (u32_PniBlkCnt*u32_PniBlkByteCnt>>9))>>11); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#if 0 ++U32 eMMC_WritePartitionInfo(U8 *pu8_Data, U32 u32_ByteCnt) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)pu8_Data; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u16_SecCnt = (u32_ByteCnt>>eMMC_SECTOR_512BYTE_BITS) + (u32_ByteCnt&eMMC_SECTOR_512BYTE_MASK); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC input Part Info keeps %u sectors\n", u16_SecCnt); ++ ++ // search eMMC Partiton Info from pni (pu8_Data) ++ for(u16_i=0; u16_iu16_SpareByteCnt, pPartInfo->u16_BlkCnt); ++ if(1 == pPartInfo->u16_SpareByteCnt) ++ break; ++ pPartInfo = (eMMC_PNI_t*)((U32)pPartInfo+0x200); ++ } ++ if(u16_i == u16_SecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: no valid Part Info for eMMC\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info ChkSum failed for eMMC, %Xh %Xh\n", ++ pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ return eMMC_ST_ERR_PARTITION_CHKSUM; ++ } ++ ++ // write Partition Info in Blk0 and Blk1 (as MBR) ++ for(u16_i=0; u16_iu16_PartCnt; *pu16_PartIdx+=1) ++ { ++ if(u16_PartType == pPartInfo->records[*pu16_PartIdx].u16_PartType) ++ { ++ if(u16_PartCopy == u32_LogicIdx) ++ break; ++ u16_PartCopy++; ++ } ++ } ++ if(*pu16_PartIdx == pPartInfo->u16_PartCnt) ++ { ++ if(0 == u16_PartCopy) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown Partition ID: %Xh\n", u16_PartType); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: no %u Partition ID: %Xh \n", ++ u32_LogicIdx+1, u16_PartType); ++ ++ return eMMC_ST_ERR_NO_PARTITION; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_GetPartitionCapacity (U16 u16_PartType, U32 *pu32_Cap) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(eMMC_PART_FAT == u16_PartType) ++ *pu32_Cap = g_eMMCDrv.u32_FATSectorCnt; ++ else ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ *pu32_Cap = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ReadPartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_R); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_R fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ return u32_err; ++} ++ ++ ++U32 eMMC_WritePartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_WriteData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_W fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_GetDevInfo(eMMC_INFO_t *peMMCInfo_t) ++{ ++ const char *str = "MSTARSEMIUNFDCIS"; ++ ++ memcpy(peMMCInfo_t->au8_Tag, str, 16); ++ peMMCInfo_t->u8_IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(peMMCInfo_t->au8_ID, g_eMMCDrv.au8_ID, g_eMMCDrv.u8_IDByteCnt); ++ peMMCInfo_t->u16_SpareByteCnt = 1; ++ peMMCInfo_t->u16_PageByteCnt = eMMC_SECTOR_512BYTE; ++ peMMCInfo_t->u16_BlkPageCnt = g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u16_BlkCnt = g_eMMCDrv.u32_SEC_COUNT / g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u32_ChkSum = eMMC_ChkSum((U8*)&peMMCInfo_t->u16_SpareByteCnt, 0x32 - 0x24); ++ ++ memcpy(peMMCInfo_t->au8_Vendor, g_eMMCDrv.au8_Vendor, 16); ++ memcpy(peMMCInfo_t->au8_PartNumber, g_eMMCDrv.au8_PartNumber, 16); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ErasePartition(U16 u16_PartType) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_PartLogiIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ break; ++ } ++ u32_PartLogiIdx++; ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ break; ++ } ++ } ++ ++ if(0 == u32_PartLogiIdx) ++ return u32_err; ++ ++ u32_err = eMMC_BootPartitionHandler_E(u16_PartType); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler fail: %Xh\n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++// erase partitions following eMMC_PART_NVRAMBAK ++U32 eMMC_EraseAllPartitions(void) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx=0, u16_PartIdx_tmp; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_NVRAMBAK, ++ u32_PartLogiIdx, &u16_PartIdx_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u16_PartIdx = u16_PartIdx_tmp; ++ u32_PartLogiIdx++; ++ } ++ ++ for(; u16_PartIdx < pPartInfo->u16_PartCnt; u16_PartIdx++) ++ { ++ // skip some partitions can not be erased ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++ if(eMMC_PART_DEV_NODE == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_E2PBAK == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_NVRAMBAK == pPartInfo->records[u16_PartIdx].u16_PartType) ++ continue; ++ #endif ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ return u32_err; ++ } ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_EraseAll(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_EraseBlock(0, g_eMMCDrv.u32_SEC_COUNT-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: fail: %Xh \n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); //BIT6:ACK ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseBlock(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_EraseBlock fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseBlock( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 fail 0, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ // clear Access Boot Partition ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i ,u16_j; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ // write Boot Code ++ u16_SecCnt = (u32_DataByteCnt>>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Boot Data keeps %Xh sectors, ChkSum: %Xh \n", ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, u16_SecCnt<<9)); ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, BOOT_PART_TOTAL_CNT<<9)); ++ ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Boot Data keeps %Xh sectors, ChkSum: %Xh \n", ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, u16_SecCnt<<9)); ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, BOOT_PART_TOTAL_CNT<<9)); ++ ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u16_SecCnt<> 9 ; ++ else ++ g_eMMCDrv.u32_EnUserStartAddr = u32_StartAddr; ++ g_eMMCDrv.u8_EnUserEnAttr= u8_EnAttr; ++ g_eMMCDrv.u8_EnUserRelW= u8_RelW; ++ return eMMC_ST_SUCCESS; ++ } ++ return eMMC_ST_ERR_INVALID_PARAM; ++} ++ ++U32 eMMC_SetPartitionComplete(void) ++{ ++ U64 u64_MaxEnhSize, u64_tmp; ++ U32 u32_err, u32_HC_WP_Size, u32_tmp; ++ U8 u8_i, u8_j, u8_tmp, u16_tmp; ++ ++ if((g_eMMCDrv.u8_ECSD160_PartSupField & BIT0) == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC doesn't support GP and enhance partitions.\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if((g_eMMCDrv.u8_u8_ECSD155_PartSetComplete & BIT0) == BIT0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Partition setting is already configured.\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ u32_HC_WP_Size = g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000; ++ ++ //set to HC Erase Define ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 175, BIT0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[175]: %Xh fail\n", ++ u32_err, BIT0); ++ return u32_err; ++ } ++ ++ //set Enhance Attribute for each partition ++ if(g_eMMCDrv.u8_ECSD160_PartSupField & BIT1) ++ { ++ u64_MaxEnhSize = (U64)((((U32)(g_eMMCDrv.u8_ECSD159_MaxEnhSize_2) << 16)| ++ ((U32)(g_eMMCDrv.u8_ECSD158_MaxEnhSize_1) << 8) | ++ (U32)(g_eMMCDrv.u8_ECSD157_MaxEnhSize_0)) * u32_HC_WP_Size); ++ ++ ++ u8_tmp = 0; ++ u64_tmp = 0; ++ if(g_eMMCDrv.u8_EnUserEnAttr == 1) ++ { ++ u64_tmp = (U64)g_eMMCDrv.u32_EnUserSize; ++ u8_tmp |= BIT0; ++ } ++ ++ for(u8_i = 0; u8_i < 4; u8_i ++) ++ { ++ if(g_eMMCDrv.GP_Part[u8_i].u8_EnAttr == 1) ++ { ++ u64_tmp += (U64)g_eMMCDrv.GP_Part[u8_i].u32_PartSize; ++ u8_tmp |= (1 << (u8_i + 1)); ++ } ++ } ++ ++ if(u64_MaxEnhSize < u64_tmp) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Sum of all enhance partition size shell be less than 0x%llX, but get 0x%llX\n", u64_MaxEnhSize, u64_tmp); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [156], Partition Attribute, to 0x%X\n", u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 156, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[156]: %Xh fail\n", ++ u32_err, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ ++ //set enhance user partition, if defined ++ if(g_eMMCDrv.u32_EnUserSize) ++ { ++ //size enhance user partition size ++ u32_tmp = g_eMMCDrv.u32_EnUserSize / u32_HC_WP_Size; ++ ++ for(u8_i = 3; u8_i > 0; u8_i --) ++ { ++ u8_tmp = (u32_tmp >> (8 * (u8_i - 1))) & 0xFF; ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Enhance User Size, to 0x%X\n", 140 + (u8_i - 1), u8_tmp); ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 140 + (u8_i - 1), u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 140 + (u8_i - 1), u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ //set enhance user partition start address ++ u32_tmp = g_eMMCDrv.u32_EnUserStartAddr; ++ ++ for(u8_i = 4; u8_i > 0 ;u8_i --) ++ { ++ u8_tmp = (u32_tmp >> (8 * (u8_i - 1))) & 0xFF; ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Enhance Start Address, to 0x%X\n", 136 + u8_i - 1, u8_tmp); ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 136 + u8_i - 1, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 136 + u8_i - 1, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ } ++ } ++ ++ //set GP partition size ++ for(u8_i = 0; u8_i < 4; u8_i ++) ++ { ++ u32_tmp = g_eMMCDrv.GP_Part[u8_i].u32_PartSize / u32_HC_WP_Size; ++ u16_tmp = 143 + u8_i * 3; ++ for(u8_j = 3; u8_j > 0; u8_j --) ++ { ++ u8_tmp = (u32_tmp >> (8 * (u8_j - 1))) & 0xFF; ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], GP Part %d, to 0x%X\n", u16_tmp + (u8_j - 1), u8_i, u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, u16_tmp + (u8_j - 1), u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, u16_tmp + (u8_j - 1), u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ } ++ //set GP partition extend attribute ++ ++ if(g_eMMCDrv.u8_ECSD160_PartSupField & BIT2) ++ { ++ u8_tmp = 0; ++ if(g_eMMCDrv.GP_Part[0].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[0].u8_ExtAttr < 3) ++ { ++ u8_tmp |= (g_eMMCDrv.GP_Part[0].u8_ExtAttr & 0xF); ++ } ++ if(g_eMMCDrv.GP_Part[1].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[1].u8_ExtAttr < 3) ++ { ++ u8_tmp |= ((g_eMMCDrv.GP_Part[1].u8_ExtAttr << 4) & 0xF0); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Extend Attr, to 0x%X\n", 52, u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 52, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 52, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ ++ u8_tmp = 0; ++ if(g_eMMCDrv.GP_Part[2].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[2].u8_ExtAttr < 3) ++ { ++ u8_tmp |= (g_eMMCDrv.GP_Part[2].u8_ExtAttr & 0xF); ++ } ++ if(g_eMMCDrv.GP_Part[3].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[3].u8_ExtAttr < 3) ++ { ++ u8_tmp |= ((g_eMMCDrv.GP_Part[3].u8_ExtAttr << 4) & 0xF0); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Extend Attr, to 0x%X\n", 53, u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 53, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 53, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Warning: eMMC doesn't support GP ext Attribute\n") ++ ; ++ } ++ //set reliable write ++ ++ if((g_eMMCDrv.u8_ECSD166_WrRelParam & (BIT0|BIT2)) == BIT0) //if BIT2 is set -> device support reliable write by default ++ { ++ u8_tmp = 0; ++ if(g_eMMCDrv.u8_EnUserRelW== 1) ++ { ++ u8_tmp |= BIT0; ++ } ++ ++ for(u8_i = 0; u8_i < 4; u8_i ++) ++ { ++ if(g_eMMCDrv.GP_Part[u8_i].u8_RelW == 1) ++ { ++ u8_tmp |= (1 << (u8_i + 1)); ++ } ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Reliable Write Setting, to 0x%X\n", 167, u8_tmp); ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 167, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 167, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Complete Setting, to 0x%X\n", 155, BIT0); ++ ++ //finally set partition setting completed bit ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 155, BIT0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 155, BIT0); ++ return u32_err; ++ } ++ #endif ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ============================================================== ++void eMMC_DumpSpeedStatus(void) ++{ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," DDR Mode\n"); ++ eMMC_DumpTimingTable(); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," \n"); ++ } ++ else { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," SDR Mode\n"); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," FCIE Clk: %u.%u MHz, %Xh\n", ++ g_eMMCDrv.u32_ClkKHz/1000, (g_eMMCDrv.u32_ClkKHz/100)%10, g_eMMCDrv.u16_ClkRegVal); ++ ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case BIT_SD_DATA_WIDTH_1: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," 1-bit "); ++ break; ++ case BIT_SD_DATA_WIDTH_4: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," 4-bits "); ++ break; ++ case BIT_SD_DATA_WIDTH_8: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," 8-bits "); ++ break; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"width\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," Bus Speed:"); ++ switch(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_SPEED_MASK) ++ { ++ case DRV_FLAG_SPEED_HIGH: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," HIGH\n"); ++ break; ++ case DRV_FLAG_SPEED_HS200: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," HS200\n"); ++ eMMC_DumpTimingTable(); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," \n"); ++ break; ++ case DRV_FLAG_SPEED_HS400: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," HS400\n"); ++ eMMC_DumpTimingTable(); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," \n"); ++ break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," LOW\n"); ++ } ++} ++ ++ ++void eMMC_DumpDriverStatus(void) ++{ ++ eMMC_debug(0,1,"\n eMMCDrvExtFlag: %Xh \n\n", gu32_eMMCDrvExtFlag); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC Status: 2014/03/25 \n"); ++ ++ // ------------------------------------------------------ ++ // helpful debug info ++ // ------------------------------------------------------ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," RIU Mode\n"); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," MIU Mode\n"); ++ #endif ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," Interrupt Mode\n"); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," Polling Mode\n"); ++ #endif ++ ++ #if defined(FICE_BYTE_MODE_ENABLE)&&FICE_BYTE_MODE_ENABLE ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," FCIE Byte Mode\n"); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," FCIE Block Mode\n"); ++ #endif ++ ++ eMMC_DumpSpeedStatus(); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," PwrOff Notification: "); ++ switch(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_PwrOffNotif_MASK) ++ { ++ case DRV_FLAG_PwrOffNotif_OFF: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"OFF\n"); break; ++ case DRV_FLAG_PwrOffNotif_ON: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"ON\n"); break; ++ case DRV_FLAG_PwrOffNotif_SHORT: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"SHORT\n"); break; ++ case DRV_FLAG_PwrOffNotif_LONG: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"LONG\n"); break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," eMMC Err: unknown: %Xh\n", ++ g_eMMCDrv.u32_DrvFlag&DRV_FLAG_PwrOffNotif_MASK); ++ } ++ ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ eMMC_DumpBurstLenTable(); ++ #endif ++ ++} ++ ++ ++U32 eMMC_Init(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh\n", u32_err); ++ ++ return u32_err; ++} ++ ++#if 1 //def CONFIG_GENERIC_MMC ++ ++extern int fbase[]; ++extern int multipliers[]; ++ ++ ++U32 eMMC_GetExtCSD(U8* pu8_Ext_CSD) ++{ ++ return eMMC_CMD8(pu8_Ext_CSD); ++} ++ ++U32 eMMC_SetExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ return eMMC_ModifyExtCSD(u8_AccessMode, u8_ByteIdx,u8_Value); ++} ++ ++#if 0 ++static ulong eMMC_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst) ++{ ++ U32 u32_Err; ++ if( blkcnt == 0) ++ return 0; ++ u32_Err = eMMC_ReadData(dst, blkcnt << 9, start); ++ if (u32_Err == eMMC_ST_SUCCESS) ++ return blkcnt; ++ else ++ return 0; ++} ++ ++static ulong eMMC_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void *src) ++{ ++ U32 u32_Err, u32_blkcnt, u32_start = start; ++ U8* pu8_src = (U8*) src; ++ ++ u32_blkcnt = blkcnt; ++ ++ u32_Err = eMMC_WriteData(pu8_src, u32_blkcnt << 9, u32_start); ++ ++ if (u32_Err == eMMC_ST_SUCCESS) ++ return blkcnt; ++ else ++ return 0; ++} ++ ++static ulong eMMC_berase(int dev_num, ulong start, lbaint_t blkcnt) ++{ ++ ++ U32 u32_Err; ++ u32_Err = eMMC_EraseBlock (start, start + blkcnt - 1); ++ if (u32_Err == eMMC_ST_SUCCESS) ++ return blkcnt; ++ else ++ return 0; ++} ++ ++int eMMC_mmc_Init(struct mmc* mmc) ++{ ++ ++ eMMC_Init(); ++ ++ sprintf(mmc->name, "Sstar-eMMC"); ++ mmc->has_init = 1; ++ mmc->capacity = (u64)g_eMMCDrv.u32_SEC_COUNT << 9; ++ ++ ++ eMMC_GetExtCSD((U8*)mmc->ext_csd); ++ ++ mmc->high_capacity = g_eMMCDrv.u8_IfSectorMode; ++ mmc->bus_width = g_eMMCDrv.u8_BUS_WIDTH; ++ ++ switch (g_eMMCDrv.u8_SPEC_VERS) { ++ case 0: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ case 1: ++ mmc->version = MMC_VERSION_1_4; ++ break; ++ case 2: ++ mmc->version = MMC_VERSION_2_2; ++ break; ++ case 3: ++ mmc->version = MMC_VERSION_3; ++ break; ++ case 4: ++ mmc->version = MMC_VERSION_4; ++ break; ++ default: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ } ++ ++ /* divide frequency by 10, since the mults are 10x bigger */ ++ ++ mmc->tran_speed = fbase[( g_eMMCDrv.u8_Tran_Speed & 0x7)] * multipliers[((g_eMMCDrv.u8_Tran_Speed >> 3) & 0xf)]; ++ ++ // reliable write is supported ++ if ((mmc->ext_csd[EXT_CSD_WR_REL_SET] & 0x01) == 1) // reliable write is configured ++ mmc->reliable_write = 2; ++ else if((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[EXT_CSD_WR_REL_PARAM] & BIT0) == BIT0)) ++ { ++ mmc->reliable_write = 1; // reliable write is supported but not configured ++ //eMMC_debug(0,0,"[%s]\treliable write is supported\n", __func__); ++ } ++ else if((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[EXT_CSD_WR_REL_PARAM] & BIT2) == BIT2)) ++ { ++ mmc->reliable_write = 3; // reliable write is supported but not configurable ++ //eMMC_debug(0,0,"[%s]\treliable write is supported\n", __func__); ++ } ++ else ++ { ++ mmc->reliable_write = 0; // reliable write is unsupported ++ //eMMC_debug(0,0,"[%s]\treliable write is unsupported\n", __func__); ++ } ++ ++ if ((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[160] & 0x3) == 3)) ++ { ++ mmc->slc_size = ((u64)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_0] ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_1]) << 8) ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_2]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ mmc->max_slc_size = ((u64)(mmc->ext_csd[157] ++ | ((u32)(mmc->ext_csd[158]) << 8) ++ | ((u32)(mmc->ext_csd[159]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ //eMMC_debug(0,0,"[%s]\t slc_size = %lld, max_slc_size = %lld\n",__func__, mmc->slc_size, mmc->max_slc_size); ++ } ++ else // slc mode is unsupported ++ { ++ mmc->slc_size = mmc->max_slc_size = 0; ++ //eMMC_debug(0,0,"[%s]\t slc mode is unsupported\n",__func__); ++ } ++ ++ ++ { ++ U16 u16_i; ++ for(u16_i = 0; u16_i < 4; u16_i ++) ++ { ++ if(u16_i < 3) ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8 | g_eMMCDrv.au8_CID[u16_i * 4 + 4]; ++ else ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8; ++ } ++ } ++ ++ mmc->read_bl_len = 512; ++ mmc->write_bl_len = 512; ++ mmc->block_dev.lun = 0; ++ mmc->block_dev.type = 0; ++ mmc->block_dev.blksz = 512; ++ mmc->block_dev.lba = g_eMMCDrv.u32_SEC_COUNT; ++ mmc->block_dev.part_type = PART_TYPE_EMMC; ++ sprintf(mmc->block_dev.vendor, "Man %06x Snr %08x", mmc->cid[0] >> 8, ++ (mmc->cid[2] << 8) | (mmc->cid[3] >> 24)); ++ sprintf(mmc->block_dev.product, "%c%c%c%c%c", mmc->cid[0] & 0xff, ++ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, ++ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); ++ sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28, ++ (mmc->cid[2] >> 24) & 0xf); ++ ++// init_part(&mmc->block_dev); ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ struct mmc* mmc = NULL; ++ ++ mmc = malloc(sizeof(struct mmc)); // uboot origianl design, don't free it. ++ if (!mmc) ++ return -ENOMEM; ++ memset(mmc, 0, sizeof(struct mmc)); ++ ++ eMMC_mmc_Init(mmc); ++ ++ mmc_register(mmc); ++ ++ mmc->block_dev.block_read = eMMC_bread; ++ mmc->block_dev.block_write = eMMC_bwrite; ++ mmc->block_dev.block_erase = eMMC_berase; ++ ++ return 0; // uboot origianl design, don't free mmc. ++} ++ ++#endif ++#endif ++ ++#define eMMC_NOT_READY_MARK ~(('e'<<24)|('M'<<16)|('M'<<8)|'C') ++static U32 sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++ ++static U32 eMMC_Init_Ex(void) ++{ ++ U32 u32_err; ++ ++ // --------------------------------- ++ u32_err = eMMC_CheckAlignPack(eMMC_CACHE_LINE); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ ++ // --------------------------------- ++ // init platform & FCIE ++ eMMC_PlatformInit(); ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ // --------------------------------- ++ u32_err = eMMC_Init_Device(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ sgu32_IfReadyGuard = ~eMMC_NOT_READY_MARK; ++ ++ LABEL_INIT_END: ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ ++ // --------------------------------- ++ // setup ID ++ // use first 10 bytes of CID ++ memcpy(g_eMMCDrv.au8_ID, &g_eMMCDrv.au8_CID[1], eMMC_ID_FROM_CID_BYTE_CNT); ++ g_eMMCDrv.u8_IDByteCnt = eMMC_ID_DEFAULT_BYTE_CNT; ++ // add a 11-th byte for number of GB ++ g_eMMCDrv.au8_ID[eMMC_ID_FROM_CID_BYTE_CNT] = ++ (g_eMMCDrv.u32_SEC_COUNT >> (1+10+10)) + 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "%u.%u GB [%Xh]\n", ++ g_eMMCDrv.u32_SEC_COUNT>>11>>10, ++ (g_eMMCDrv.u32_SEC_COUNT>>11)*100/1024%100, ++ g_eMMCDrv.u32_SEC_COUNT); ++ //eMMC_dump_mem(g_eMMCDrv.au8_ID, 0x10); ++ #if 0 ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Err: eMMC Init, no pni, :%Xh\n", u32_err); ++ return eMMC_ST_ERR_NO_CIS; ++ } ++ //eMMC_DumpDriverStatus(); ++ #endif ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Init_Device_Ex(void) ++{ ++ U32 u32_err; ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSPFROMRAM_SAVE; ++ #endif ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_INIT_DONE; ++ ++ // init eMMC device ++ u32_err = eMMC_Identify(); ++ if(u32_err) ++ return u32_err; ++ ++ //eMMC_debug(0, 1, "eMMC 12MHz\n"); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ ++ // determine device parameters, from CSD ++ u32_err = eMMC_CSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // setup eMMC device ++ // CMD7 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ u32_err = eMMC_CMD16(eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ ++ // determine device parameters, from Ext_CSD ++ u32_err = eMMC_ExtCSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u16_of_buswidth = 4; ++ //eMMC_debug(0,0,"set bus witdth 8 bits\n"); ++ u32_err = eMMC_SetBusWidth(g_eMMCDrv.u16_of_buswidth, 0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_debug(0,0,"set to high speed\n"); ++ u32_err = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #ifdef IP_FCIE_VERSION_5 ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ #endif ++ ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_INIT_DONE; ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Init_Device(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_Init_Device_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ // ---------------------------------------- ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ //while(1); ++ ++ // ---------------------------------------- ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ u32_err = eMMC_LoadBurstLenTable(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_SaveBurstLenTable(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: save Burst Len: %Xh\n", u32_err); ++ goto LABEL_INIT_END; ++ } ++ else ++ eMMC_DumpBurstLenTable(); ++ } ++ #endif ++ ++ //eMMC_dump_mem(g_eMMCDrv.au8_AllRsp, 0x100); ++ LABEL_INIT_END: ++ ++ return u32_err; ++ ++} ++ ++ ++U32 eMMC_CheckIfReady(void) ++{ ++ if(eMMC_NOT_READY_MARK != sgu32_IfReadyGuard) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_Init_Ex(); ++} ++ ++void eMMC_ResetReadyFlag(void) ++{ ++ sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++ ++U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseCMDSeq(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 0: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseCMDSeq( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 1, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ return u32_err; ++} ++ ++// ok: return 0 ++U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ eMMC_LockFCIE(NULL); ++ #if defined(MSOS_TYPE_ECOS) ++ u32_BlkAddr += eMMC_TOTAL_RESERVED_BLK_CNT; ++ #endif ++ u32_err = eMMC_WriteData_Ex(pu8_DataBuf, u32_DataByteCnt, u32_BlkAddr); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++} ++ ++U32 eMMC_WriteData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ volatile U16 u16_BlkCnt; ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ } ++ ++ if(NULL == pu8_DataBuf) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w data buf is NULL: %ph \n", pu8_DataBuf); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD25(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD24(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: W fail: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ return u32_err; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++// ok: return 0 ++U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ eMMC_LockFCIE(NULL); ++ #if defined(MSOS_TYPE_ECOS) ++ u32_BlkAddr += eMMC_TOTAL_RESERVED_BLK_CNT; ++ #endif ++ u32_err = eMMC_ReadData_Ex(pu8_DataBuf, u32_DataByteCnt, u32_BlkAddr); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++} ++ ++U32 eMMC_ReadData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ volatile U16 u16_BlkCnt; ++ U8 u8_IfNotCacheLineAligned=0; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ // first 512 bytes, special handle if not cache line aligned ++ if((uintptr_t)pu8_DataBuf & (eMMC_CACHE_LINE-1)) ++ { ++ #if 0 ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING,1, ++ "eMMC Warn: R, buffer not Cache Line aligned: %Xh \n", ++ (U32)pu8_DataBuf); ++ #endif ++ ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.0: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ return u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ u32_BlkAddr += 1; ++ pu8_DataBuf += eMMC_SECTOR_512BYTE; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ ++ // last 512B must be not cache line aligned, ++ // reserved for last eMMC_CMD17_CIFD ++ if(u32_DataByteCnt){ ++ u8_IfNotCacheLineAligned = 1; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ } ++ } ++ ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD18(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD17(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.1: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ // last 512 bytes, special handle if not cache line aligned ++ if(u8_IfNotCacheLineAligned) ++ { ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.2: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_GetCapacity(U32 *pu32_TotalSectorCnt) // 1 sector = 512B ++{ ++ U32 u32_err; ++ ++ eMMC_LockFCIE(NULL); ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ eMMC_UnlockFCIE(NULL); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ } ++ ++ *pu32_TotalSectorCnt = g_eMMCDrv.u32_SEC_COUNT; ++ #if defined(MSOS_TYPE_ECOS) ++ *pu32_TotalSectorCnt -= eMMC_TOTAL_RESERVED_BLK_CNT; ++ #endif ++ eMMC_UnlockFCIE(NULL); ++ return eMMC_ST_SUCCESS; ++} ++ ++#if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++U32 eMMC_SearchDevNodeStartSector(void) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ eMMC_LockFCIE(NULL); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: init fail: %Xh\n", u32_err); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_DEV_NODE, 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: GetPartitionIndex fail: %Xh\n", u32_err); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++ } ++ ++ g_eMMCDrv.u32_PartDevNodeStartSector = pPartInfo->records[u16_PartIdx].u16_StartBlk; ++ g_eMMCDrv.u32_PartDevNodeStartSector *= pPartInfo->u16_BlkPageCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt *= pPartInfo->u16_BlkPageCnt; ++ eMMC_UnlockFCIE(NULL); ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++int get_NVRAM_start_sector(unsigned int *u32_startsector) ++{ ++ ++ ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ U16 u16_PartIdx; ++ eMMC_LockFCIE(NULL); ++ ++ if(eMMC_ST_SUCCESS==eMMC_GetPartitionIndex(eMMC_PART_NVRAM, 0, &u16_PartIdx)) ++ { ++ *u32_startsector = pPartInfo->records[u16_PartIdx].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ printk(KERN_INFO"eMMC_PART_NVRAM start sector: %X\r\n",*u32_startsector); ++ eMMC_UnlockFCIE(NULL); ++ ++ return 0; ++ } ++ ++ eMMC_UnlockFCIE(NULL); ++ ++ return -1; ++} ++ ++//only support p1~p7 for each EMMC device in Linux ++int get_NVRAM_max_part_count(void) ++{ ++ //eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ //return (pPartInfo->u16_PartCnt-1); ++ return 0x0C; ++} ++ ++ ++int get_DEVNODE_start_sector(unsigned int *u32_startsector) ++{ ++ u32 u32_err; ++ if(0 == g_eMMCDrv.u32_PartDevNodeStartSector){ ++ u32_err = eMMC_SearchDevNodeStartSector(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ printk(KERN_ERR"** Err, %s **\n", __func__); ++ return (-1); ++ } ++ } ++ ++ *u32_startsector=g_eMMCDrv.u32_PartDevNodeStartSector; ++ ++ return 0; ++} ++ ++ ++EXPORT_SYMBOL(get_DEVNODE_start_sector); ++EXPORT_SYMBOL(get_NVRAM_max_part_count); ++ ++#endif ++#endif ++ +diff --git a/drivers/sstar/emmc/unify_driver/src/common/eMMC_hal.c b/drivers/sstar/emmc/unify_driver/src/common/eMMC_hal.c +new file mode 100755 +index 000000000000..b25c43ff4317 +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/src/common/eMMC_hal.c +@@ -0,0 +1,3742 @@ ++/* ++* eMMC_hal.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include "eMMC.h" ++ ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//======================================================== ++// HAL pre-processors ++//======================================================== ++#if IF_FCIE_SHARE_IP ++ // re-config FCIE3 for NFIE mode ++ #define eMMC_RECONFIG() //eMMC_ReConfig(); ++#else ++ // NULL to save CPU a JMP/RET time ++ #define eMMC_RECONFIG() ++#endif ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) \ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSPFROMRAM_SAVE)\ ++ eMMC_KeepRsp(pu8_OneRspBuf, u8_CmdIdx) ++#else ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) // NULL to save CPU a JMP/RET time ++#endif ++ ++ ++#define eMMC_FCIE_CLK_DIS() REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN) ++ ++#define eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT 20 ++#define eMMC_CMD_API_ERR_RETRY_CNT 20 ++#define eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT 20 ++ ++#define eMMC_CMD1_RETRY_CNT 0x8000 ++#define eMMC_CMD3_RETRY_CNT 0x5 ++ ++static U32 (*sgpFn_eMMC_FCIE_WaitEvents_Ex)(U32, U16, U32) = NULL; ++//======================================================== ++// HAL APIs ++//======================================================== ++U32 eMMC_FCIE_WaitEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ return (*sgpFn_eMMC_FCIE_WaitEvents_Ex)(u32_RegAddr, u16_Events, u32_MicroSec); ++} ++ ++U32 eMMC_FCIE_PollingEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ volatile U32 u32_i, u32_DelayX; ++ volatile U16 u16_val; ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); // mask interrupts ++ if(u32_MicroSec > HW_TIMER_DELAY_100us) ++ { ++ u32_DelayX = HW_TIMER_DELAY_100us/HW_TIMER_DELAY_1us; ++ u32_MicroSec /= u32_DelayX; ++ } ++ else ++ u32_DelayX = 1; ++ ++ for(u32_i=0; u32_i>REG_OFFSET_SHIFT_BITS, ++ u16_val, u16_Events); ++ ++ return eMMC_ST_ERR_TIMEOUT_WAIT_REG0; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U16 sgau16_eMMCDebugBus[100]; ++void eMMC_FCIE_DumpDebugBus(void) ++{ ++ volatile U16 u16_reg, u16_i; ++ U16 u16_idx = 0; ++ ++ memset(sgau16_eMMCDebugBus, 0xFF, sizeof(sgau16_eMMCDebugBus)); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ ++ for(u16_i=0; u16_i<8; u16_i++) ++ { ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_FCIE_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, u16_i< 0; u16_i--) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "%u ", u16_i); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ ++ // check FCIE reg.30h ++ REG_FCIE_R(FCIE_TEST_MODE, u16_reg); ++ if(0)//u16_reg & BIT_FCIE_BIST_FAIL) /* Andersen: "don't care." */ ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h BIST fail: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_BIST_FAIL; ++ } ++ if(u16_reg & BIT_FCIE_DEBUG_MODE_MASK) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h Debug Mode: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_DEBUG_MODE; ++ } ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ } ++ #endif // eMMC_TEST_IN_DESIGN ++ ++ // ------------------------------------------ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); ++ REG_FCIE_W(FCIE_MMA_PRI_REG, BIT_MIU_CLK_FREE_RUN); ++ REG_FCIE_W(FCIE_PATH_CTRL, BIT_SD_EN); ++ // all cmd are 5 bytes (excluding CRC) ++ REG_FCIE_W(FCIE_CMD_SIZE, eMMC_CMD_BYTE_CNT); ++ REG_FCIE_W(FCIE_SD_CTRL, 0); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ #if FICE_BYTE_MODE_ENABLE ++ // default sector size: 0x200 ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE | eMMC_SECTOR_512BYTE); ++ #else ++ REG_FCIE_W(FCIE_SDIO_CTRL, 0); ++ #endif ++ ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, 0); ++ eMMC_FCIE_ClearEvents(); ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; // ok ++} ++ ++ ++void eMMC_FCIE_ClearEvents(void) ++{ ++ volatile U16 u16_reg; ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU_REQUEST_RST); ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++ REG_FCIE_W1C(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); // W1C ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_REQUEST_RST); ++} ++ ++ ++void eMMC_FCIE_ClearEvents_Reg0(void) ++{ ++ volatile U16 u16_reg; ++ ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++} ++ ++ ++U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ volatile U16 u16_read0=0, u16_read1=0; ++ ++ for(u32_cnt=0; u32_cnt < u32_us; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read0); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read1); ++ ++ if((u16_read0&BIT_SD_CARD_D0_ST) && (u16_read1&BIT_SD_CARD_D0_ST)) ++ break; ++ ++ // interrupt mode, then sleep ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ if(eMMC_WaitCompleteIntr == sgpFn_eMMC_FCIE_WaitEvents_Ex) ++ if(u32_cnt > 500 && u32_us-u32_cnt > 1000) ++ { ++ eMMC_hw_timer_sleep(1); ++ u32_cnt += 1000-2; ++ } ++ #endif ++ } ++ ++ return u32_cnt; ++} ++ ++U32 eMMC_FCIE_WaitD0High(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ u32_cnt = eMMC_FCIE_WaitD0High_Ex(u32_us); ++ ++ if(u32_us == u32_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H timeout %u us\n", u32_cnt); ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++#define FIFO_CLK_RDY_CHECK_CNT 3 ++U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir) ++{ ++ volatile U32 u32_cnt=0; ++ volatile U16 au16_read[FIFO_CLK_RDY_CHECK_CNT], u16_i; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_MMA_PRI_REG, au16_read[0]); ++ if(u8_Dir == (au16_read[0]&BIT_DMA_DIR_W)) ++ break; ++ } ++ if(TIME_WAIT_FIFOCLK_RDY == u32_cnt) ++ return eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ for(u16_i=0; u16_i>24)<<8) | (0x40|u8_CmdIdx)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), u32_Arg&0xFF); ++ ++ REG_FCIE_R(FCIE_CIFC_ADDR(0),au16_tmp[0]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(1),au16_tmp[1]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(2),au16_tmp[2]); ++ ++ if(au16_tmp[0] == (((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx))&& ++ au16_tmp[1] == ((u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF))&& ++ au16_tmp[2] == (u32_Arg&0xFF)) ++ break; ++ } ++ ++ if(12 != u8_CmdIdx) ++ { ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ #endif ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSP_WAIT_D0H){ ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ // wait event ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, TIME_WAIT_CMDRSP_END); ++ ++ LABEL_SEND_CMD_ERROR: ++ return u32_err; ++ ++} ++ ++void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i>1)); ++ ++ if(u8addr&0x1) ++ { ++ return ((u16Tmp>>8)&0xFF); ++ } ++ else ++ { ++ return (u16Tmp&0xFF); ++ } ++} ++ ++U8 eMMC_FCIE_DataFifoGet(U8 u8addr) ++{ ++ U16 u16Tmp; ++ ++ u16Tmp = REG_FCIE(FCIE_CIFD_ADDR(u8addr>>1)); ++ ++ if(u8addr&0x1) ++ return ((u16Tmp>>8)&0xFF); ++ else ++ return (u16Tmp&0xFF); ++} ++ ++//=================================================== ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ eMMC_die("\n"); // should be system fatal error, not eMMC driver ++ } ++ ++ memcpy(g_eMMCDrv.au8_AllRsp + u16_idx, pu8_OneRspBuf, u8_ByteCnt); ++ ++} ++ ++ ++U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ if(0 == g_eMMCDrv.au8_AllRsp[u16_idx]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: no rsp, %u %u \n", u8_CmdIdx, u16_idx); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ memcpy(pu8_OneRspBuf, g_eMMCDrv.au8_AllRsp + u16_idx, u8_ByteCnt); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ------------------------------- ++U32 eMMC_SaveRsp(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_SaveDriverContext(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_LoadDriverContext(U8 *pu8_Buf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++//======================================================== ++// Send CMD HAL APIs ++//======================================================== ++U32 eMMC_Identify(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_i, u16_retry=0; ++ ++ g_eMMCDrv.u16_RCA=1; ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ ++ LABEL_IDENTIFY_CMD0: ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(u16_retry > 10) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ if(u16_retry) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Warn: retry: %u\n", u16_retry); ++ ++ // CMD0 ++ u32_err = eMMC_CMD0(0); // reset to idle state ++ if(eMMC_ST_SUCCESS != u32_err) ++ {u16_retry++; goto LABEL_IDENTIFY_CMD0;} ++ ++ // CMD1 ++ for(u16_i=0; u16_i>6; ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 1); ++ } ++ } ++ #else ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD1 ok, do things here ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ else ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ } ++ } ++ #endif ++ ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// send CID ++U32 eMMC_CMD2(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 2, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD2, %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD2; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD2 Reg.12: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD2 ok, do things here (get CID) ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CID); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CID, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CID, 2); ++ } ++ } ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// CMD3: assign RCA. CMD7: select device ++U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ if(7 == u8_CmdIdx) ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ else{ ++ u8_retry_fcie = 0xF0; // CMD3: not retry ++ } ++ ++ u32_arg = u16_RCA<<16; ++ ++ if(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA) ++ u16_ctrl = BIT_SD_CMD_EN; ++ else ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ return u32_err; ++ } ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ // de-select has no rsp ++ if(!(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA)){ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ return u32_err; ++ } ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ return u32_err; ++ } ++ ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ }} ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_CSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------ ++ g_eMMCDrv.u8_SPEC_VERS = (g_eMMCDrv.au8_CSD[1]&0x3C)>>2; ++ g_eMMCDrv.u8_R_BL_LEN = g_eMMCDrv.au8_CSD[6] & 0xF; ++ g_eMMCDrv.u8_W_BL_LEN = ((g_eMMCDrv.au8_CSD[13]&0x3)<<2)+ ++ ((g_eMMCDrv.au8_CSD[14]&0xC0)>>6); ++ ++ // ------------------------------ ++ g_eMMCDrv.u16_C_SIZE = (g_eMMCDrv.au8_CSD[7] & 3)<<10; ++ g_eMMCDrv.u16_C_SIZE += g_eMMCDrv.au8_CSD[8] << 2; ++ g_eMMCDrv.u16_C_SIZE +=(g_eMMCDrv.au8_CSD[9] & 0xC0) >> 6; ++ if(0xFFF == g_eMMCDrv.u16_C_SIZE) ++ { ++ g_eMMCDrv.u32_SEC_COUNT = 0; ++ } ++ else ++ { ++ g_eMMCDrv.u8_C_SIZE_MULT = ((g_eMMCDrv.au8_CSD[10]&3)<<1)+ ++ ((g_eMMCDrv.au8_CSD[11]&0x80)>>7); ++ ++ g_eMMCDrv.u32_SEC_COUNT = ++ (g_eMMCDrv.u16_C_SIZE+1)* ++ (1<<(g_eMMCDrv.u8_C_SIZE_MULT+2))* ++ ((1<>9) - 8; // -8: //Toshiba CMD18 access the last block report out of range error ++ } ++ // ------------------------------ ++ g_eMMCDrv.u8_ERASE_GRP_SIZE = (g_eMMCDrv.au8_CSD[10]&0x7C)>>2; ++ g_eMMCDrv.u8_ERASE_GRP_MULT = ((g_eMMCDrv.au8_CSD[10]&0x03)<<3)+ ++ ((g_eMMCDrv.au8_CSD[11]&0xE0)>>5); ++ g_eMMCDrv.u32_EraseUnitSize = (g_eMMCDrv.u8_ERASE_GRP_SIZE+1)* ++ (g_eMMCDrv.u8_ERASE_GRP_MULT+1); ++ // ------------------------------ ++ // others ++ g_eMMCDrv.u8_TAAC = g_eMMCDrv.au8_CSD[2]; ++ g_eMMCDrv.u8_NSAC = g_eMMCDrv.au8_CSD[3]; ++ g_eMMCDrv.u8_Tran_Speed = g_eMMCDrv.au8_CSD[4]; ++ g_eMMCDrv.u8_R2W_FACTOR = (g_eMMCDrv.au8_CSD[13]&0x1C)>>2; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// send CSD (in R2) ++U32 eMMC_CMD9(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_RCA<<16; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 9, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD9 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD9; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD9 Reg.12: %04Xh, Retry fail: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD2 ok, do things here ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CSD); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CSD, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CSD, 9); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_ExtCSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD8(gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_dump_mem(gau8_eMMC_SectorBuf, 0x200); ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((gau8_eMMC_SectorBuf[215]<<24)| ++ (gau8_eMMC_SectorBuf[214]<<16)| ++ (gau8_eMMC_SectorBuf[213]<< 8)| ++ (gau8_eMMC_SectorBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = gau8_eMMC_SectorBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ if(!g_eMMCDrv.u8_BUS_WIDTH) { ++ g_eMMCDrv.u8_BUS_WIDTH = gau8_eMMC_SectorBuf[183]; ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ } ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[503]&BIT0) // HPI ++ { ++ if(gau8_eMMC_SectorBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ }else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ #else ++ if((gau8_eMMC_SectorBuf[503]&BIT0) && 1==gau8_eMMC_SectorBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(gau8_eMMC_SectorBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ else ++ { ++ //eMMC_debug(0,1,"eMMC Warn: not support dynamic Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = gau8_eMMC_SectorBuf[181]; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ECSD185_HsTiming = gau8_eMMC_SectorBuf[185]; ++ g_eMMCDrv.u8_ECSD192_Ver = gau8_eMMC_SectorBuf[192]; ++ g_eMMCDrv.u8_ECSD196_DevType = gau8_eMMC_SectorBuf[196]; ++ g_eMMCDrv.u8_ECSD197_DriverStrength = gau8_eMMC_SectorBuf[197]; ++ g_eMMCDrv.u8_ECSD248_CMD6TO = gau8_eMMC_SectorBuf[248]; ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO = gau8_eMMC_SectorBuf[247]; ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl = gau8_eMMC_SectorBuf[34]; ++ ++ //for GP Partition ++ g_eMMCDrv.u8_ECSD160_PartSupField = gau8_eMMC_SectorBuf[160]; ++ g_eMMCDrv.u8_ECSD224_HCEraseGRPSize= gau8_eMMC_SectorBuf[224]; ++ g_eMMCDrv.u8_ECSD221_HCWpGRPSize= gau8_eMMC_SectorBuf[221]; ++ ++ g_eMMCDrv.GP_Part[0].u32_PartSize = ((gau8_eMMC_SectorBuf[145] << 16) | ++ (gau8_eMMC_SectorBuf[144] << 8) | ++ (gau8_eMMC_SectorBuf[143])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[1].u32_PartSize = ((gau8_eMMC_SectorBuf[148] << 16) | ++ (gau8_eMMC_SectorBuf[147] << 8) | ++ (gau8_eMMC_SectorBuf[146])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[2].u32_PartSize = ((gau8_eMMC_SectorBuf[151] << 16) | ++ (gau8_eMMC_SectorBuf[150] << 8) | ++ (gau8_eMMC_SectorBuf[149])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[3].u32_PartSize = ((gau8_eMMC_SectorBuf[154] << 16) | ++ (gau8_eMMC_SectorBuf[153] << 8) | ++ (gau8_eMMC_SectorBuf[152])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ //for Max Enhance Size ++ g_eMMCDrv.u8_ECSD157_MaxEnhSize_0= gau8_eMMC_SectorBuf[157]; ++ g_eMMCDrv.u8_ECSD158_MaxEnhSize_1= gau8_eMMC_SectorBuf[158]; ++ g_eMMCDrv.u8_ECSD159_MaxEnhSize_2= gau8_eMMC_SectorBuf[159]; ++ ++ g_eMMCDrv.u8_u8_ECSD155_PartSetComplete = gau8_eMMC_SectorBuf[155]; ++ g_eMMCDrv.u8_ECSD166_WrRelParam = gau8_eMMC_SectorBuf[166]; ++ ++ //-------------------------------- ++ // set HW RST ++ if(0 == gau8_eMMC_SectorBuf[162]) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 162, BIT0); // RST_FUNC ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[162]: %Xh fail\n", ++ u32_err, BIT0); ++ return u32_err; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_CMD8(U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD8_CIFD(pu8_DataBuf); ++ #else ++ return eMMC_CMD8_MIU(pu8_DataBuf); ++ #endif ++} ++ ++// CMD8: send EXT_CSD ++U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr, u32_DataMapAddr; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_DataMapAddr = eMMC_DMA_MAP_address((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(u32_DataMapAddr, eMMC_SECTOR_512BYTE); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_DataDMAAddr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, ++ TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200)) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ volatile U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0;; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ //eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 8); ++ ++ // ------------------------------- ++ // CMD8 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetPwrOffNotification(U8 u8_SetECSD34) ++{ ++ U32 u32_err; ++ static U8 u8_OldECSD34=0; ++ ++ if(eMMC_PwrOffNotif_SHORT==u8_OldECSD34 || eMMC_PwrOffNotif_LONG==u8_OldECSD34) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: PwrOffNotif already set: %u, now: %u\n", ++ u8_OldECSD34, u8_SetECSD34); ++ return eMMC_ST_SUCCESS; ++ } ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 34, u8_SetECSD34); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_PwrOffNotif_MASK; ++ switch(u8_SetECSD34) ++ { ++ case eMMC_PwrOffNotif_OFF: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_OFF; break; ++ case eMMC_PwrOffNotif_ON: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_ON; break; ++ case eMMC_PwrOffNotif_SHORT: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_SHORT; break; ++ case eMMC_PwrOffNotif_LONG: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_LONG; break; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Sanitize(U8 u8_ECSD165) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 165, u8_ECSD165); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH<<2); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#define BITS_MSK_DRIVER_STRENGTH 0xF0 ++#define BITS_MSK_TIMING 0x0F ++ ++U32 eMMC_SetBusSpeed(U8 u8_BusSpeed) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_TIMING; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8_BusSpeed; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_SPEED_MASK; ++ switch(u8_BusSpeed) ++ { ++ case eMMC_SPEED_HIGH: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_SYNC; ++ break; ++ case eMMC_SPEED_HS200: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS200; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ break; ++ case eMMC_SPEED_HS400: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS400; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ break; ++ default: ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_SetDrivingStrength(U8 u8Driving) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_DRIVER_STRENGTH; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8Driving<<4; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); // HS_TIMING, HS200 ++ if(eMMC_ST_SUCCESS != u32_err) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail: %Xh\n", u32_err); ++ return eMMC_ST_ERR_SET_DRV_STRENGTH; ++ } ++ return eMMC_ST_SUCCESS; ++} ++ ++// Use CMD6 to set ExtCSD[183] BUS_WIDTH ++U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR) ++{ ++ U8 u8_value; ++ U32 u32_err; ++ ++ // ------------------------------- ++ switch(u8_BusWidth) ++ { ++ case 1: u8_value=0; break; ++ case 4: u8_value=1; break; ++ case 8: u8_value=2; break; ++ default: return eMMC_ST_ERR_PARAMETER; ++ } ++ ++ if(u8_IfDDR) ++ { ++ u8_value |= BIT2; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_MODE; ++ } ++ else ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_MODE; ++ ++ ++ // ------------------------------- ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 183, u8_value); // BUS_WIDTH ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------- ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ switch(u8_BusWidth) ++ { ++ case 1: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_1; ++ break; ++ case 4: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_4; ++ break; ++ case 8: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_8; ++ break; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"set %u bus width\n", u8_BusWidth); ++ return u32_err; ++} ++ ++U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ U32 u32_arg, u32_err; ++ ++ u32_arg = ((u8_AccessMode&3)<<24) | (u8_ByteIdx<<16) | ++ (u8_Value<<8); ++ ++ u32_err = eMMC_CMD6(u32_arg); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Warn: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++// SWITCH cmd ++U32 eMMC_CMD6(U32 u32_Arg) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_Arg; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 6, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD6; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 6); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err; ++ U8 u8_retry_cmd=0; ++ ++ LABEL_SEND_CMD: ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_start, 35); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_end, 36); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD38(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEN_END: ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u fail, %Xh \n", ++ u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh \n", u8_CmdIdx, u16_reg); ++ return eMMC_ST_ERR_CMD3536_ERR; ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh\n", u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD38(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ u32_arg = 0x1; ++ else ++ u32_arg = 0x0; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 38, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD38 fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD38_ERR; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 Reg.12: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD38 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 check R1 error: %Xh\n", u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 38); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++// CMD13: send Status ++U32 eMMC_CMD13(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0;// ,u8_retry_r1=0; ++ ++ u32_arg = (u16_RCA<<16); // | ++ // ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD13)?1:0); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 13, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ #if 0 ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ #else ++ eMMC_debug(0, 1, ++ "eMMC: CMD13 check R1 error: %Xh, should not retry\n", u32_err); ++ #endif ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 13); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD16(U32 u32_BlkLength) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_BlkLength; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 16, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD16; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD16 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 16); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++//------------------------------------------------ ++ ++U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD17_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD17_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++#if 0 ++static U32 u32_TestCnt=0; ++#define IF_TEST_RETRY(x) (0==++u32_TestCnt%x) ++#else ++#define IF_TEST_RETRY(x) (0)//==++u32_TestCnt%x) ++#endif ++ ++U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr, u32_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_DataMapAddr = eMMC_DMA_MAP_address((U32)pu8_DataBuf,eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(u32_DataMapAddr, eMMC_SECTOR_512BYTE); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_DataDMAAddr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(7) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200)) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ //if(0 == eMMC_IF_TUNING_TTABLE()) ++ // eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ sgu8_IfNeedRestorePadType = g_eMMCDrv.u8_PadType; ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(28) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // CMD17 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ if(IF_TEST_RETRY(10) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(IF_TEST_RETRY(3) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check Reg.12: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD12; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check Reg.12: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 12); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12_NoCheck(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++ ++U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(20) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>11))); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(24) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(1, 1, "eMMC Err: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200)) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++// enable Reliable Write ++U32 eMMC_CMD23(U16 u16_BlkCnt) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_BlkCnt&0xFFFF; // don't set BIT24 ++ #if defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE ++ u32_arg |= BIT31; // don't set BIT24 ++ #endif ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 23, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 23); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ #endif ++ ++ #if eMMC_BURST_LEN_AUTOCFG || ENABLE_eMMC_RIU_MODE ++ U16 u16_RetryCnt=0; ++ LABEL_CMD25: ++ #endif ++ // ------------------------------RIU mode ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ for(u16_cnt=0; u16_cnt g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen ? ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen : u16_BlkCnt-u16_blk_pos; ++ u16_blk_cnt = u16_blk_cnt == g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen ? ++ u16_blk_cnt/2 : u16_blk_cnt; ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMCBlkAddr+u16_blk_pos, ++ pu8_DataBuf+(u16_blk_pos< u32_t1-u32_t0) ++ { ++ u32_tMin = u32_t1-u32_t0; ++ u16_BestBlkCnt = u16_BurstBlkCnt; ++ } ++ if(u32_tMax < u32_t1-u32_t0) ++ { ++ u32_tMax = u32_t1-u32_t0; ++ u16_WorstBlkCnt = u16_BurstBlkCnt; ++ } ++ ++ if(MAX_DETECT_BLK_CNT != u16_BurstBlkCnt) ++ goto LABEL_DETECT; ++ ++ // -------------------------- ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen = u16_BestBlkCnt; ++ g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen = u16_WorstBlkCnt; ++ ++ u32_tmp = (U32)(MAX_DETECT_BLK_CNT<> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(IF_TEST_RETRY(32) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(1, 1, "eMMC WARN: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>9))); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(43) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ #if 1 //!(defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE) ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ #endif ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD24_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD24_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr, u32_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) { ++ ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_W : TOGGLE_CNT_256_CLK_W); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_DataMapAddr = eMMC_DMA_MAP_address((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE,0); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(u32_DataMapAddr, eMMC_SECTOR_512BYTE); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_DataDMAAddr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(25) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(34) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_MIU_WAIT_D0H; ++ goto LABEL_END; ++ } ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(11) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: CMD24 %sReg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 %sReg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i, *pu16_dat=(U16*)pu8_DataBuf; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ ++ // fill CIFD with data ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ for(u16_i=0; u16_i<(FCIE_CIFD_BYTE_CNT>>1); u16_i++) ++ REG_FCIE_W(FCIE_CIFD_ADDR(u16_i), pu16_dat[u16_i]); ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ sgu8_IfNeedRestorePadType = g_eMMCDrv.u8_PadType; ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(19) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 TO Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(u8_retry_fcie) ++ eMMC_debug(0,1,"eMMC Info: retry ok\n"); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_GetR1(void) ++{ ++ return (g_eMMCDrv.au8_Rsp[1]<<24) | (g_eMMCDrv.au8_Rsp[2]<<16) ++ | (g_eMMCDrv.au8_Rsp[3]<<8) | g_eMMCDrv.au8_Rsp[4]; ++} ++ ++U32 eMMC_CheckR1Error(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ ++ if(g_eMMCDrv.au8_Rsp[1] & (eMMC_ERR_R1_31_24>>24)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_31_24 \n "); ++ u32_err = eMMC_ST_ERR_R1_31_24; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[2] & (eMMC_ERR_R1_23_16>>16)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_23_16 \n "); ++ u32_err = eMMC_ST_ERR_R1_23_16; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[3] & (eMMC_ERR_R1_15_8>>8)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_15_8 \n "); ++ u32_err = eMMC_ST_ERR_R1_15_8; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[4] & (eMMC_ERR_R1_7_0>>0)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_7_0 \n "); ++ u32_err = eMMC_ST_ERR_R1_7_0; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++LABEL_CHECK_R1_END: ++ ++ /*u8_cs = (eMMC_FCIE_CmdRspBufGet(3) & (eMMC_R1_CURRENT_STATE>>8))>>1; ++ eMMC_debug(0,0,"card state: %d ", u8_cs); ++ switch(u8_cs) { ++ case 0: eMMC_debug(0,0,"(idle)\n"); break; ++ case 1: eMMC_debug(0,0,"(ready)\n"); break; ++ case 2: eMMC_debug(0,0,"(ident)\n"); break; ++ case 3: eMMC_debug(0,0,"(stby)\n"); break; ++ case 4: eMMC_debug(0,0,"(tran)\n"); break; ++ case 5: eMMC_debug(0,0,"(data)\n"); break; ++ case 6: eMMC_debug(0,0,"(rcv)\n"); break; ++ case 7: eMMC_debug(0,0,"(prg)\n"); break; ++ case 8: eMMC_debug(0,0,"(dis)\n"); break; ++ default: eMMC_debug(0,0,"(?)\n"); break; ++ }*/ ++ ++ if(eMMC_ST_SUCCESS != u32_err)// && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R1_BYTE_CNT); ++ } ++ return u32_err; ++} ++ ++ ++// ==================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define UPFW_SEC_WIAT_CNT 0x1000000 ++#define UPFW_SEC_BYTE_CNT (128*1024) ++static U32 eMMC_UpFW_Samsung_Wait(void) ++{ ++ U32 u32_err, u32_cnt, u32_st; ++ ++ for(u32_cnt=0; u32_cnt>eMMC_SECTOR_512BYTE_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: write fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 3, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ // --------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"close ... \n"); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, 0, 28, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD28 fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 4, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ LABEL_END_OF_UPFW: ++ return u32_err; ++ ++} ++#endif // eMMC_UPDATE_FIRMWARE ++ ++void HalFcie_SetFlag4Kernel2RuneMMC(void) ++{ ++ REG_FCIE_CLRBIT(FCIE_REG16h, BIT_KERN_CHK_NAND_EMMC_MSK); ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_KERN_EMMC); ++} ++ ++bool HalFcie_CheckIfeMMCRun4Kernel(void) ++{ ++ u16 u16_regval = 0; ++ ++ u16_regval = REG_FCIE(FCIE_REG16h); ++ ++ if( (u16_regval & BIT_KERN_CHK_NAND_EMMC) == BIT_KERN_CHK_NAND_EMMC ) ++ { ++ return ( (u16_regval & BIT_KERN_EMMC) != BIT_KERN_EMMC ) ? 0 : 1; ++ } ++ return 0; ++} ++ ++#endif // UNIFIED_eMMC_DRIVER ++ +diff --git a/drivers/sstar/emmc/unify_driver/src/common/eMMC_hal_speed.c b/drivers/sstar/emmc/unify_driver/src/common/eMMC_hal_speed.c +new file mode 100755 +index 000000000000..2f6485a06b2c +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/src/common/eMMC_hal_speed.c +@@ -0,0 +1,642 @@ ++/* ++* eMMC_hal_speed.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include "eMMC.h" ++ ++// ========================================================== ++U32 eMMC_FCIE_EnableSDRMode(void) ++{ ++ U32 u32_ErrSpeed = eMMC_ST_SUCCESS, u32_ErrWidth = eMMC_ST_SUCCESS, u32_Err = eMMC_ST_SUCCESS; ++ ++ // ---------------------------------------- ++ // may call from any other interface status ++ #if 0 ++ if(DRV_FLAG_SPEED_HS200 == eMMC_SPEED_MODE()) ++ { ++ u32_ErrSpeed = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ } ++ else if(DRV_FLAG_SPEED_HS400 == eMMC_SPEED_MODE()) ++ { ++ u32_ErrSpeed = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ u32_ErrWidth = eMMC_SetBusWidth(g_eMMCDrv.u16_of_buswidth, 0); ++ } ++ else ++ #else ++ if(DRV_FLAG_SPEED_HS200 == eMMC_SPEED_MODE()|| ++ DRV_FLAG_SPEED_HS400 == eMMC_SPEED_MODE()) ++ { ++ u32_Err = eMMC_FCIE_ErrHandler_ReInit_Ex(); ++ if(eMMC_ST_SUCCESS != u32_Err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_Err); ++ return u32_Err; ++ } ++ } ++ #endif ++ { ++ u32_ErrSpeed = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ u32_ErrWidth = eMMC_SetBusWidth(g_eMMCDrv.u16_of_buswidth, 0); ++ } ++ ++ if(eMMC_ST_SUCCESS!=u32_ErrSpeed || eMMC_ST_SUCCESS!=u32_ErrWidth) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh %Xh\n", u32_ErrSpeed, u32_ErrWidth); ++ return u32_ErrSpeed ? u32_ErrSpeed : u32_ErrWidth; ++ } ++ ++ // ---------------------------------------- ++ // set to normal SDR 48MHz ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// =========================== ++#if !(defined(ENABLE_eMMC_ATOP) && ENABLE_eMMC_ATOP) ++void eMMC_DumpDDR48TTable(void) ++{ ++ U16 u16_i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC DDR Timing Table: Cnt:%u CurIdx:%u \n", ++ g_eMMCDrv.TimingTable_t.u8_SetCnt, g_eMMCDrv.TimingTable_t.u8_CurSetIdx); ++ ++ for(u16_i=0; u16_i HW_TIMER_DELAY_100us) ++ { ++ u32_DelayX = HW_TIMER_DELAY_100us/HW_TIMER_DELAY_1us; ++ u32_MicroSec /= u32_DelayX; ++ } ++ else ++ u32_DelayX = 1; ++ ++ for(u32_i=0; u32_i>REG_OFFSET_SHIFT_BITS, ++ u16_val, u16_Events); ++ ++ return eMMC_ST_ERR_TIMEOUT_WAIT_REG0; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++char *gDebugModeName[] = ++{ ++ NULL, ++ NULL, //"NAND", ++ NULL, //"CIFD", ++ "MMA", ++ NULL, //"BOOT", ++ "CARD", ++ NULL, //"BIST", ++ NULL, ++ "REG_QIFX_CNT", ++ "REG_QIFY_CNT", ++ "REG_DMA_REQ_CNT", ++ "REG_DMA_RSP_CNT", ++ NULL, //"BOOT_RDATA_CNT", ++ NULL, //"BIST_RDATA_CNT", ++ NULL, //"MACRO_DBUS1", ++ NULL, //"MACRO_DBUS2", ++}; ++ ++void eMMC_FCIE_DumpDebugBus(void) ++{ ++ U16 u16_i; ++ U16 u16_j; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ ++ for(u16_j=0; u16_j<0x10; u16_j++) ++ { ++ if( gDebugModeName[u16_j] == NULL ) ++ continue; ++ ++ REG_FCIE_CLRBIT(FCIE_EMMC_DEBUG_BUS1, BIT_DEBUG_MODE_MSK); ++ REG_FCIE_SETBIT(FCIE_EMMC_DEBUG_BUS1, u16_j<<8); ++ ++ if( u16_j == 5 ) ++ { ++ for(u16_i=1; u16_i<=4; u16_i++) ++ { ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, u16_i<=1000) ++ eMMC_debug(1, 0, "eMMC Err: FCIE reset fail!\n"); ++ } ++ ++ REG_FCIE_SETBIT(FCIE_RST, BIT_FCIE_SOFT_RST_n); ++ u16Cnt = 0; ++ while(1) ++ { ++ if((REG_FCIE(FCIE_RST)&BIT_RST_STS_MASK)==0) // reset success ++ break; ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(u16Cnt++>=1000) ++ eMMC_debug(1, 0, "eMMC Err: FCIE reset fail2!\n"); ++ } ++ ++ eMMC_clock_setting(u16_clk); ++ return 0; ++ ++ #if 0 ++ U16 u16Reg, u16Cnt; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_clk = g_eMMCDrv.u16_ClkRegVal; ++ ++ eMMC_clock_setting(gau8_FCIEClkSel[0]); // speed up FCIE reset done ++ REG_FCIE_CLRBIT(FCIE_MIE_FUNC_CTL, BIT_FUNC_MASK); ++ REG_FCIE_SETBIT(FCIE_MIE_FUNC_CTL, BIT_MIE_FUNC_ENABLE); ++ eMMC_FCIE_CLK_DIS(); // do not output clock ++ ++ // FCIE reset - set ++ REG_FCIE_CLRBIT(FCIE_RST, BIT_FCIE_SOFT_RST_n); /* active low */ ++ REG_FCIE_CLRBIT(reg_emmcpll_0x6f, BIT1|BIT0); //macro reset ++ ++ // FCIE reset - wait ++ ++ u16Cnt=0; ++ do ++ { ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ if(0x1000 == u16Cnt++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: FCIE Reset fail: %Xh \n", eMMC_ST_ERR_FCIE_NO_CLK); ++ return eMMC_ST_ERR_FCIE_NO_CLK; ++ } ++ ++ REG_FCIE_R(FCIE_RST, u16Reg); ++ ++ }while (BIT_RST_STS_MASK != (u16Reg & BIT_RST_STS_MASK)); ++ ++ //[FIXME] is there any method to check that reseting FCIE is done? ++ ++ // FCIE reset - clear ++ REG_FCIE_SETBIT(FCIE_RST, BIT_FCIE_SOFT_RST_n); ++ REG_FCIE_SETBIT(reg_emmcpll_0x6f, BIT1|BIT0); ++ // FCIE reset - check ++ ++ u16Cnt=0; ++ do ++ { ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ if(0x1000 == u16Cnt++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: FCIE Reset fail2: %Xh \n", eMMC_ST_ERR_FCIE_NO_CLK); ++ return eMMC_ST_ERR_FCIE_NO_CLK; ++ } ++ ++ REG_FCIE_R(FCIE_RST, u16Reg); ++ ++ }while (0 != (u16Reg & BIT_RST_STS_MASK)); ++ ++ eMMC_clock_setting(u16_clk); ++ return u32_err; ++ #endif ++} ++ ++ ++U32 eMMC_FCIE_Init(void) ++{ ++ U32 u32_err; ++ ++ // ------------------------------------------ ++ // setup function pointer to wait for events ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ if(NULL==sgpFn_eMMC_FCIE_WaitEvents_Ex) ++ sgpFn_eMMC_FCIE_WaitEvents_Ex = eMMC_WaitCompleteIntr; ++ #else ++ if(NULL==sgpFn_eMMC_FCIE_WaitEvents_Ex) ++ sgpFn_eMMC_FCIE_WaitEvents_Ex = eMMC_FCIE_PollingEvents; ++ #endif ++ ++ // ------------------------------------------ ++ eMMC_PlatformResetPre(); ++ ++ // ------------------------------------------ ++ #if eMMC_TEST_IN_DESIGN ++ { ++ volatile U16 u16_i, u16_reg; ++ // check timer clock ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Timer test, for 6 sec: "); ++ for(u16_i = 6; u16_i > 0; u16_i--) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "%u ", u16_i); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ ++ // check FCIE reg.30h ++ REG_FCIE_R(FCIE_TEST_MODE, u16_reg); ++ if(0)//u16_reg & BIT_FCIE_BIST_FAIL) /* Andersen: "don't care." */ ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h BIST fail: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_BIST_FAIL; ++ } ++ if(u16_reg & BIT_FCIE_DEBUG_MODE_MASK) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h Debug Mode: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_DEBUG_MODE; ++ } ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ } ++ #endif // eMMC_TEST_IN_DESIGN ++ ++ // ------------------------------------------ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); ++ REG_FCIE_W(FCIE_MIE_FUNC_CTL, BIT_MIE_FUNC_ENABLE|BIT_EMMC_ACTIVE); ++ // all cmd are 5 bytes (excluding CRC) ++ REG_FCIE_CLRBIT(FCIE_CMD_RSP_SIZE, BIT_CMD_SIZE_MASK); ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, (eMMC_CMD_BYTE_CNT)<< BIT_CMD_SIZE_SHIFT); ++ REG_FCIE_W(FCIE_SD_CTRL, 0); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ // default sector size: 0x200 ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_RSP_SHIFT_CNT, 0); ++ REG_FCIE_W(FCIE_RX_SHIFT_CNT, 0); ++ //REG_FCIE_CLRBIT(FCIE_RX_SHIFT_CNT, BIT_RSTOP_SHIFT_SEL|BIT_RSTOP_SHIFT_TUNE_MASK); ++ ++ ++ eMMC_FCIE_ClearEvents(); ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++void eMMC_FCIE_ClearEvents(void) ++{ ++ volatile U16 u16_reg; ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++ REG_FCIE_W1C(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); // W1C ++} ++ ++ ++void eMMC_FCIE_ClearEvents_Reg0(void) ++{ ++ volatile U16 u16_reg; ++ ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++} ++ ++ ++U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ volatile U16 u16_read0=0, u16_read1=0; ++ ++ for(u32_cnt=0; u32_cnt < u32_us; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read0); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read1); ++ ++ if((u16_read0&BIT_SD_CARD_BUSY) ==0 && (u16_read1&BIT_SD_CARD_BUSY) ==0) ++ break; ++ ++ if(u32_cnt > 500 && u32_us-u32_cnt > 1000) ++ { ++ eMMC_hw_timer_sleep(1); ++ u32_cnt += 1000-2; ++ } ++ } ++ ++ return u32_cnt; ++} ++ ++U32 eMMC_FCIE_WaitD0High(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_CLK_EN); ++ u32_cnt = eMMC_FCIE_WaitD0High_Ex(u32_us); ++ ++ if(u32_us == u32_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H timeout %u us\n", u32_cnt); ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_FCIE_SendCmd ++( ++ U16 u16_Mode, U16 u16_Ctrl, U32 u32_Arg, U8 u8_CmdIdx, U8 u8_RspByteCnt ++) ++{ ++ U32 u32_err, u32_Timeout = TIME_WAIT_DAT0_HIGH; ++ //U16 au16_tmp[3]; ++ ++ if(38 == u8_CmdIdx) ++ u32_Timeout = TIME_WAIT_ERASE_DAT0_HIGH; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh, rspb:%Xh, mode:%Xh, ctrl:%Xh \n", ++ u8_CmdIdx, u32_Arg, u8_RspByteCnt, u16_Mode, u16_Ctrl); ++ #endif ++ ++ REG_FCIE_CLRBIT(FCIE_CMD_RSP_SIZE, BIT_RSP_SIZE_MASK); ++ ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, u8_RspByteCnt & BIT_RSP_SIZE_MASK); ++ ++ REG_FCIE_W(FCIE_SD_MODE, u16_Mode); ++ // set cmd ++ // CMDFIFO(0) = 39:32 | 47:40 ++ // CMDFIFO(1) = 23:16 | 31:24 ++ // CMDFIFO(2) = (CIFC(2) & 0xFF00) | 15:8, ignore (CRC7 | end_bit). ++ ++ //check command FIFO for filled command value ++ //REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_CHK_CMD); ++ //while(1) ++ //{ ++// eMMC_debug(0, 1, "FIFO 0 = 0x%4X\n", ((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx)); ++// eMMC_debug(0, 1, "FIFO 1 = 0x%4X\n", (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++// eMMC_debug(0, 1, "FIFO 2 = 0x%4X\n", u32_Arg&0xFF); ++ REG_FCIE_W(FCIE_CMDFIFO_ADDR(0),((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx)); ++ REG_FCIE_W(FCIE_CMDFIFO_ADDR(1), (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++ REG_FCIE_W(FCIE_CMDFIFO_ADDR(2), u32_Arg&0xFF); ++ ++ //REG_FCIE_R(FCIE_CMDFIFO_ADDR(0),au16_tmp[0]); ++ //REG_FCIE_R(FCIE_CMDFIFO_ADDR(1),au16_tmp[1]); ++ //REG_FCIE_R(FCIE_CMDFIFO_ADDR(2),au16_tmp[2]); ++ ++ //if(au16_tmp[0] == (((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx))&& ++ // au16_tmp[1] == ((u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF))&& ++ // au16_tmp[2] == (u32_Arg&0xFF)) ++ // break; ++ //} ++ ++ //clear command check for reading response value ++ //REG_FCIE_CLRBIT(FCIE_SD_CTRL, BIT_CHK_CMD); ++ ++ if(12 != u8_CmdIdx) ++ { ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl); ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl |BIT_JOB_START); ++ ++ #if 1//defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // wait event ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, HW_TIMER_DELAY_1s); ++ #endif ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSP_WAIT_D0H){ ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ LABEL_SEND_CMD_ERROR: ++ return u32_err; ++ ++} ++ ++void eMMC_FCIE_GetCMDFIFO(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i= u32_MicroSec) ++ { ++ REG_FCIE_R(NC_CIFD_EVENT, u16_Reg); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "CIFD Event Timout %X\n", u16_Reg); ++ } ++ return u32_Count; ++} ++ ++U32 eMMC_WaitSetCIFD(U8 * pu8_DataBuf, U32 u32_ByteCnt) ++{ ++ U16 u16_i, *pu16_Data = (U16*)pu8_DataBuf; ++ ++ if(u32_ByteCnt > FCIE_CIFD_BYTE_CNT) ++ { ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ for(u16_i=0; u16_i<(u32_ByteCnt>>1); u16_i++) ++ REG_FCIE_W(NC_RBUF_CIFD_ADDR(u16_i), pu16_Data[u16_i]); ++ ++ REG_FCIE_SETBIT(NC_CIFD_EVENT, BIT_RBUF_FULL_TRI); ++ ++ if (eMMC_WaitCIFD_Event(BIT_RBUF_EMPTY, HW_TIMER_DELAY_500ms)== (HW_TIMER_DELAY_500ms )) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Error: CIFD timeout 0, ErrCode:%Xh\r\n", eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT); ++ return eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT; // timeout ++ } ++ ++ REG_FCIE_SETBIT(NC_CIFD_EVENT, BIT_RBUF_EMPTY); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++void eMMC_FCIE_GetCIFD(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i FCIE_CIFD_BYTE_CNT) ++ { ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if (eMMC_WaitCIFD_Event(BIT_WBUF_FULL, HW_TIMER_DELAY_500ms)== (HW_TIMER_DELAY_500ms )) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Error: CIFD timeout 0, ErrCode:%Xh\r\n", eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT); ++ return eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT; // timeout ++ } ++ ++ for(u16_i=0; u16_i<(u32_ByteCnt>>1); u16_i++) ++ REG_FCIE_R(NC_WBUF_CIFD_ADDR(u16_i), pu16_Data[u16_i]); ++ ++ REG_FCIE_W(NC_CIFD_EVENT,BIT_WBUF_FULL); ++ ++ REG_FCIE_W(NC_CIFD_EVENT, BIT_WBUF_EMPTY_TRI); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U8 eMMC_FCIE_CmdRspBufGet(U8 u8addr) ++{ ++ U16 u16Tmp; ++ ++ u16Tmp = REG_FCIE(FCIE_CMDFIFO_ADDR(u8addr>>1)); ++ ++ if(u8addr&0x1) ++ { ++ return ((u16Tmp>>8)&0xFF); ++ } ++ else ++ { ++ return (u16Tmp&0xFF); ++ } ++} ++ ++U8 eMMC_FCIE_DataFifoGet(U8 u8addr) ++{ ++ U16 u16Tmp; ++ ++ u16Tmp = REG_FCIE(FCIE_CIFD_ADDR(u8addr>>1)); ++ ++ if(u8addr&0x1) ++ return ((u16Tmp>>8)&0xFF); ++ else ++ return (u16Tmp&0xFF); ++} ++ ++//=================================================== ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ eMMC_die("\n"); // should be system fatal error, not eMMC driver ++ } ++ ++ memcpy(g_eMMCDrv.au8_AllRsp + u16_idx, pu8_OneRspBuf, u8_ByteCnt); ++ ++} ++ ++ ++U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ if(0 == g_eMMCDrv.au8_AllRsp[u16_idx]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: no rsp, %u %u \n", u8_CmdIdx, u16_idx); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ memcpy(pu8_OneRspBuf, g_eMMCDrv.au8_AllRsp + u16_idx, u8_ByteCnt); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ------------------------------- ++U32 eMMC_SaveRsp(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_SaveDriverContext(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_LoadDriverContext(U8 *pu8_Buf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++//======================================================== ++// Send CMD HAL APIs ++//======================================================== ++U32 eMMC_Identify(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_i, u16_retry=0; ++ ++ g_eMMCDrv.u16_RCA=1; ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ ++ LABEL_IDENTIFY_CMD0: ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(u16_retry > 10) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ if(u16_retry) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Warn: retry: %u\n", u16_retry); ++ ++ // CMD0 ++ u32_err = eMMC_CMD0(0); // reset to idle state ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u16_retry++; ++ goto LABEL_IDENTIFY_CMD0; ++ } ++ ++ // CMD1 ++ for(u16_i=0; u16_i2G]/[x00_FF_80_00 : x40_FF_80_00] ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 1, eMMC_R3_BYTE_CNT); ++ ++ #if 1 ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: CMD1 send CMD fail: %08Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: CMD1 no Rsp, SD_STS: %04Xh \n", u16_reg); ++ ++ return u32_err; ++ } ++ else ++ { // CMD1 ok, do things here ++ //clear status may be BIT_SD_RSP_CRC_ERR ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ ++ eMMC_FCIE_GetCMDFIFO(0, 3, (U16*)g_eMMCDrv.au8_Rsp); //RDY(2G):x80_FF_80_80/xC0_FF_80_80 ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) { ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ } ++ else ++ { ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 1); ++ } ++ } ++ #else ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD1 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD1 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD1 ok, do things here ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ else ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ } ++ } ++ #endif ++ ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// send CID ++U32 eMMC_CMD2(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 2, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD2, %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD2; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD2 SD_STS: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD2 ok, do things here (get CID) ++ eMMC_FCIE_GetCMDFIFO(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CID); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CID, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CID, 2); ++ } ++ } ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// CMD3: assign RCA. CMD7: select device ++U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ if(7 == u8_CmdIdx) { ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ } ++ else{ ++ u8_retry_fcie = 0xF0; // CMD3: not retry ++ } ++ ++ u32_arg = u16_RCA<<16; ++ ++ if(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA) ++ u16_ctrl = BIT_SD_CMD_EN; ++ else ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ return u32_err; ++ } ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ // de-select has no rsp ++ if(!(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA)){ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u SD_STS: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ return u32_err; ++ } ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u SD_STS: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u SD_STS: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ return u32_err; ++ } ++ ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ }} ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_CSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------ ++ g_eMMCDrv.u8_SPEC_VERS = (g_eMMCDrv.au8_CSD[1]&0x3C)>>2; ++ g_eMMCDrv.u8_R_BL_LEN = g_eMMCDrv.au8_CSD[6] & 0xF; ++ g_eMMCDrv.u8_W_BL_LEN = ((g_eMMCDrv.au8_CSD[13]&0x3)<<2)+ ++ ((g_eMMCDrv.au8_CSD[14]&0xC0)>>6); ++ ++ // ------------------------------ ++ g_eMMCDrv.u16_C_SIZE = (g_eMMCDrv.au8_CSD[7] & 3)<<10; ++ g_eMMCDrv.u16_C_SIZE += g_eMMCDrv.au8_CSD[8] << 2; ++ g_eMMCDrv.u16_C_SIZE +=(g_eMMCDrv.au8_CSD[9] & 0xC0) >> 6; ++ if(0xFFF == g_eMMCDrv.u16_C_SIZE) ++ { ++ g_eMMCDrv.u32_SEC_COUNT = 0; ++ } ++ else ++ { ++ g_eMMCDrv.u8_C_SIZE_MULT = ((g_eMMCDrv.au8_CSD[10]&3)<<1)+ ++ ((g_eMMCDrv.au8_CSD[11]&0x80)>>7); ++ ++ g_eMMCDrv.u32_SEC_COUNT = ++ (g_eMMCDrv.u16_C_SIZE+1)* ++ (1<<(g_eMMCDrv.u8_C_SIZE_MULT+2))* ++ ((1<>9) - 8; // -8: //Toshiba CMD18 access the last block report out of range error ++ } ++ // ------------------------------ ++ g_eMMCDrv.u8_ERASE_GRP_SIZE = (g_eMMCDrv.au8_CSD[10]&0x7C)>>2; ++ g_eMMCDrv.u8_ERASE_GRP_MULT = ((g_eMMCDrv.au8_CSD[10]&0x03)<<3)+ ++ ((g_eMMCDrv.au8_CSD[11]&0xE0)>>5); ++ g_eMMCDrv.u32_EraseUnitSize = (g_eMMCDrv.u8_ERASE_GRP_SIZE+1)* ++ (g_eMMCDrv.u8_ERASE_GRP_MULT+1); ++ // ------------------------------ ++ // others ++ g_eMMCDrv.u8_TAAC = g_eMMCDrv.au8_CSD[2]; ++ g_eMMCDrv.u8_NSAC = g_eMMCDrv.au8_CSD[3]; ++ g_eMMCDrv.u8_Tran_Speed = g_eMMCDrv.au8_CSD[4]; ++ g_eMMCDrv.u8_R2W_FACTOR = (g_eMMCDrv.au8_CSD[13]&0x1C)>>2; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// send CSD (in R2) ++U32 eMMC_CMD9(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_RCA<<16; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 9, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD9 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD9; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD9 SD_STS: %04Xh, Retry fail: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD2 ok, do things here ++ eMMC_FCIE_GetCMDFIFO(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CSD); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CSD, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CSD, 9); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_ExtCSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD8(gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) { ++ eMMC_debug(0,1,"eMMC Err: CMD8 fail\n"); ++ eMMC_dump_mem(gau8_eMMC_SectorBuf, 0x200); ++ return u32_err; ++ } ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((gau8_eMMC_SectorBuf[215]<<24)| ++ (gau8_eMMC_SectorBuf[214]<<16)| ++ (gau8_eMMC_SectorBuf[213]<< 8)| ++ (gau8_eMMC_SectorBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = gau8_eMMC_SectorBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ if(!g_eMMCDrv.u8_BUS_WIDTH) { ++ g_eMMCDrv.u8_BUS_WIDTH = gau8_eMMC_SectorBuf[183]; ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support\n"); ++ while(1); ++ } ++ } ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[503]&BIT0) // HPI ++ { ++ if(gau8_eMMC_SectorBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ }else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ #else ++ if((gau8_eMMC_SectorBuf[503]&BIT0) && 1==gau8_eMMC_SectorBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(gau8_eMMC_SectorBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ else ++ { ++ //eMMC_debug(0,1,"eMMC Warn: not support dynamic Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = gau8_eMMC_SectorBuf[181]; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ECSD184_Stroe_Support = gau8_eMMC_SectorBuf[184]; ++ g_eMMCDrv.u8_ECSD185_HsTiming = gau8_eMMC_SectorBuf[185]; ++ g_eMMCDrv.u8_ECSD192_Ver = gau8_eMMC_SectorBuf[192]; ++ g_eMMCDrv.u8_ECSD196_DevType = gau8_eMMC_SectorBuf[196]; ++ g_eMMCDrv.u8_ECSD197_DriverStrength = gau8_eMMC_SectorBuf[197]; ++ g_eMMCDrv.u8_ECSD248_CMD6TO = gau8_eMMC_SectorBuf[248]; ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO = gau8_eMMC_SectorBuf[247]; ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl = gau8_eMMC_SectorBuf[34]; ++ ++ //for GP Partition ++ g_eMMCDrv.u8_ECSD160_PartSupField = gau8_eMMC_SectorBuf[160]; ++ g_eMMCDrv.u8_ECSD224_HCEraseGRPSize= gau8_eMMC_SectorBuf[224]; ++ g_eMMCDrv.u8_ECSD221_HCWpGRPSize= gau8_eMMC_SectorBuf[221]; ++ ++ g_eMMCDrv.GP_Part[0].u32_PartSize = ((gau8_eMMC_SectorBuf[145] << 16) | ++ (gau8_eMMC_SectorBuf[144] << 8) | ++ (gau8_eMMC_SectorBuf[143])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[1].u32_PartSize = ((gau8_eMMC_SectorBuf[148] << 16) | ++ (gau8_eMMC_SectorBuf[147] << 8) | ++ (gau8_eMMC_SectorBuf[146])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[2].u32_PartSize = ((gau8_eMMC_SectorBuf[151] << 16) | ++ (gau8_eMMC_SectorBuf[150] << 8) | ++ (gau8_eMMC_SectorBuf[149])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[3].u32_PartSize = ((gau8_eMMC_SectorBuf[154] << 16) | ++ (gau8_eMMC_SectorBuf[153] << 8) | ++ (gau8_eMMC_SectorBuf[152])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ //for Max Enhance Size ++ g_eMMCDrv.u8_ECSD157_MaxEnhSize_0= gau8_eMMC_SectorBuf[157]; ++ g_eMMCDrv.u8_ECSD158_MaxEnhSize_1= gau8_eMMC_SectorBuf[158]; ++ g_eMMCDrv.u8_ECSD159_MaxEnhSize_2= gau8_eMMC_SectorBuf[159]; ++ ++ g_eMMCDrv.u8_u8_ECSD155_PartSetComplete = gau8_eMMC_SectorBuf[155]; ++ g_eMMCDrv.u8_ECSD166_WrRelParam = gau8_eMMC_SectorBuf[166]; ++ ++ //-------------------------------- ++ // set HW RST ++ if(0 == gau8_eMMC_SectorBuf[162]) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 162, BIT0); // RST_FUNC ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[162]: %Xh fail\n", ++ u32_err, BIT0); ++ return u32_err; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_CMD8(U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD8_CIFD(pu8_DataBuf); ++ #else ++ return eMMC_CMD8_MIU(pu8_DataBuf); ++ #endif ++} ++ ++// CMD8: send EXT_CSD ++U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr; ++ dma_addr_t dma_DataMapAddr; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN |BIT_ERR_DET_ON; ++ ++ LABEL_SEND_CMD: ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ dma_DataMapAddr = eMMC_DMA_MAP_address((uintptr_t)pu8_DataBuf, eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(dma_DataMapAddr, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_DataDMAAddr >> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ volatile U16 u16_mode, u16_ctrl, u16_reg, u16_j, u16_Tmp; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0;; ++ ++// REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ //read for data ++ for (u16_j=0; u16_j< (eMMC_SECTOR_512BYTE >> 6); u16_j++) ++ { // read data ++ u16_Tmp =( (eMMC_SECTOR_512BYTE - (u16_j << 6)) >= 0x40) ? ++ 0x40 : (eMMC_SECTOR_512BYTE - (u16_j << 6) ); ++ u32_err = eMMC_WaitGetCIFD((U8*)((uintptr_t)pu8_DataBuf + (u16_j << 6)), u16_Tmp); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ //eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 8); ++ ++ // ------------------------------- ++ // CMD8 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_SetPwrOffNotification(U8 u8_SetECSD34) ++{ ++ U32 u32_err; ++ static U8 u8_OldECSD34=0; ++ ++ if(eMMC_PwrOffNotif_SHORT==u8_OldECSD34 || eMMC_PwrOffNotif_LONG==u8_OldECSD34) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: PwrOffNotif already set: %u, now: %u\n", ++ u8_OldECSD34, u8_SetECSD34); ++ return eMMC_ST_SUCCESS; ++ } ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 34, u8_SetECSD34); // PWR_OFF_NOTIFICATION ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_PwrOffNotif_MASK; ++ switch(u8_SetECSD34) ++ { ++ case eMMC_PwrOffNotif_OFF: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_OFF; break; ++ case eMMC_PwrOffNotif_ON: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_ON; break; ++ case eMMC_PwrOffNotif_SHORT: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_SHORT; break; ++ case eMMC_PwrOffNotif_LONG: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_LONG; break; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Sanitize(U8 u8_ECSD165) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 165, u8_ECSD165); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH<<2); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#define BITS_MSK_DRIVER_STRENGTH 0xF0 ++#define BITS_MSK_TIMING 0x0F ++ ++U32 eMMC_SetBusSpeed(U8 u8_BusSpeed) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_TIMING; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8_BusSpeed; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_SPEED_MASK; ++ switch(u8_BusSpeed) ++ { ++ case eMMC_SPEED_HIGH: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ break; ++ case eMMC_SPEED_HS200: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS200; ++ break; ++ case eMMC_SPEED_HS400: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS400; ++ break; ++ default: ++ break; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_SetDrivingStrength(U8 u8Driving) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_DRIVER_STRENGTH; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8Driving<<4; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); // HS_TIMING, HS200 ++ if(eMMC_ST_SUCCESS != u32_err) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail: %Xh\n", u32_err); ++ return eMMC_ST_ERR_SET_DRV_STRENGTH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++// Use CMD6 to set ExtCSD[183] BUS_WIDTH ++U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR) ++{ ++ U8 u8_value; ++ U32 u32_err; ++ ++ // ------------------------------- ++ switch(u8_BusWidth) ++ { ++ case 1: u8_value=0; break; ++ case 4: u8_value=1; break; ++ case 8: u8_value=2; break; ++ default: return eMMC_ST_ERR_PARAMETER; ++ } ++ ++ if(u8_IfDDR) ++ { ++ u8_value |= BIT2; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_MODE; ++ } ++ else { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_MODE; ++ } ++ if(u8_IfDDR == 2 && g_eMMCDrv.u8_ECSD184_Stroe_Support ) ++ { ++ eMMC_debug(0,1,"Enhance Strobe\n"); ++ u8_value |= BIT7; // Enhanced Storbe ++ } ++ ++ // ------------------------------- ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 183, u8_value); // BUS_WIDTH ++ if(eMMC_ST_SUCCESS != u32_err) { ++ return u32_err; ++ } ++ ++ // ------------------------------- ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ switch(u8_BusWidth) ++ { ++ case 1: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_1; ++ break; ++ case 4: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_4; ++ break; ++ case 8: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_8; ++ break; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"set %u bus width\n", u8_BusWidth); ++ return u32_err; ++} ++ ++U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ U32 u32_arg, u32_err; ++ U8 u8_retry_prg = 0; ++ ++ u32_arg = ((u8_AccessMode&3)<<24) | (u8_ByteIdx<<16) | ++ (u8_Value<<8); ++ ++ u32_err = eMMC_CMD6(u32_arg); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ do { ++ if (u8_retry_prg > 5) ++ break; ++ ++ u32_err = eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ if ((eMMC_ST_ERR_R1_7_0 != u32_err) && (eMMC_ST_SUCCESS != u32_err)) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Warn: %Xh \n", u32_err); ++ return u32_err; ++ } ++ else if (eMMC_ST_SUCCESS == u32_err) ++ break; ++ ++ u8_retry_prg++; ++ } while (eMMC_ST_ERR_R1_7_0 == u32_err); ++ ++ return u32_err; ++} ++ ++// SWITCH cmd ++U32 eMMC_CMD6(U32 u32_Arg) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_Arg; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 6, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD6; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 6); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err; ++ U8 u8_retry_cmd=0; ++ ++ LABEL_SEND_CMD: ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_start, 35); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_end, 36); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD38(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEN_END: ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u fail, %Xh \n", ++ u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u SD_STS: %04Xh \n", u8_CmdIdx, u16_reg); ++ return eMMC_ST_ERR_CMD3536_ERR; ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh\n", u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD38(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ u32_arg = 0x1; ++ else ++ u32_arg = 0x0; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 38, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD38 fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD38_ERR; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 SD_STS: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD38 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 check R1 error: %Xh\n", u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 38); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++U32 eMMC_Dump_eMMCStatus(void) ++{ ++ eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC St: %Xh %Xh %Xh %Xh \n", ++ g_eMMCDrv.au8_Rsp[1], g_eMMCDrv.au8_Rsp[2], g_eMMCDrv.au8_Rsp[3], g_eMMCDrv.au8_Rsp[4]); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// CMD13: send Status ++U32 eMMC_CMD13(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0;// ,u8_retry_r1=0; ++ ++ u32_arg = (u16_RCA<<16); // | ++ // ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD13)?1:0); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 13, eMMC_R1_BYTE_CNT); ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ #if 0 ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ #else ++ eMMC_debug(0, 1, ++ "eMMC: CMD13 check R1 error: %Xh, should not retry\n", u32_err); ++ #endif ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 13); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ ++ return u32_err; ++} ++ ++U32 eMMC_CMD16(U32 u32_BlkLength) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_BlkLength; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 16, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD16; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD16 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 16); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++//------------------------------------------------ ++ ++U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD17_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD17_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++#if 0 ++static U32 u32_TestCnt=0; ++#define IF_TEST_RETRY(x) (0==++u32_TestCnt%x) ++#else ++#define IF_TEST_RETRY(x) (0)//==++u32_TestCnt%x) ++#endif ++ ++U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr; ++ dma_addr_t dma_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN |BIT_ERR_DET_ON; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ dma_DataMapAddr = eMMC_DMA_MAP_address((uintptr_t)pu8_DataBuf,eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(dma_DataMapAddr, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_DataDMAAddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_1_BLK_END); ++ ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(7) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ LABEL_END: ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++// REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ //if(0 == eMMC_IF_TUNING_TTABLE()) ++ // eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ for (u16_i=0; u16_i< (eMMC_SECTOR_512BYTE >> 6); u16_i++) ++ { // read data ++ u32_err = eMMC_WaitGetCIFD((U8*)((uintptr_t)pu8_DataBuf + (u16_i << 6)), 0x40); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ //read for data ++ for (u16_i=0; u16_i< (eMMC_SECTOR_512BYTE >> 6); u16_i++) ++ { // read data ++ u32_err = eMMC_WaitGetCIFD((U8*)((uintptr_t)pu8_DataBuf + (u16_i << 6)), 0x40); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(28) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // CMD17 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD12(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ if(IF_TEST_RETRY(10) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(IF_TEST_RETRY(3) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check SD_STS: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD12; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check SD_STS: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 12); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12_NoCheck(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, (eMMC_SECTOR_512BYTE*u16_BlkCnt) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,(eMMC_SECTOR_512BYTE*u16_BlkCnt) >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(20) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>11))); ++ ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(24) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(1, 1, "eMMC Err: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++// enable Reliable Write ++U32 eMMC_CMD23(U16 u16_BlkCnt) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_BlkCnt&0xFFFF; // don't set BIT24 ++ #if defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE ++ u32_arg |= BIT31; // don't set BIT24 ++ #endif ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 23, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 23); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ #if defined(ENABLE_eMMC_RIU_MODE) && ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ #endif ++ ++ #if (defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG) || ENABLE_eMMC_RIU_MODE ++ U16 u16_RetryCnt=0; ++ LABEL_CMD25: ++ #endif ++ // ------------------------------RIU mode ++ #if defined(ENABLE_eMMC_RIU_MODE) && ENABLE_eMMC_RIU_MODE ++ for(u16_cnt=0; u16_cnt g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen ? ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen : u16_BlkCnt-u16_blk_pos; ++ u16_blk_cnt = u16_blk_cnt == g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen ? ++ u16_blk_cnt/2 : u16_blk_cnt; ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMCBlkAddr+u16_blk_pos, ++ pu8_DataBuf+(u16_blk_pos< u32_t1-u32_t0) ++ { ++ u32_tMin = u32_t1-u32_t0; ++ u16_BestBlkCnt = u16_BurstBlkCnt; ++ } ++ if(u32_tMax < u32_t1-u32_t0) ++ { ++ u32_tMax = u32_t1-u32_t0; ++ u16_WorstBlkCnt = u16_BurstBlkCnt; ++ } ++ ++ if(MAX_DETECT_BLK_CNT != u16_BurstBlkCnt) ++ goto LABEL_DETECT; ++ ++ // -------------------------- ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen = u16_BestBlkCnt; ++ g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen = u16_WorstBlkCnt; ++ ++ u32_tmp = (U32)(MAX_DETECT_BLK_CNT<> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, (eMMC_SECTOR_512BYTE*u16_BlkCnt) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, (eMMC_SECTOR_512BYTE*u16_BlkCnt) >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(1, 1, "eMMC WARN: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_ERR_DET_ON); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>9))); ++ ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(43) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ #if 1 //!(defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE) ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ #endif ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD24_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD24_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr; ++ dma_addr_t dma_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ dma_DataMapAddr = eMMC_DMA_MAP_address((uintptr_t)pu8_DataBuf, eMMC_SECTOR_512BYTE,0); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(dma_DataMapAddr, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_DataDMAAddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, (eMMC_SECTOR_512BYTE) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,( eMMC_SECTOR_512BYTE) >> 16); ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(25) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(34) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_MIU_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_ERR_DET_ON); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(11) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: CMD24 %s SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 %s SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(19) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START); ++ ++ for (u16_i=0; u16_i< (eMMC_SECTOR_512BYTE >> 6); u16_i++) ++ { ++ u32_err = eMMC_WaitSetCIFD( (U8*)( (uintptr_t) pu8_DataBuf + (u16_i << 6)), 0x40); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 TO SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(u8_retry_fcie) ++ eMMC_debug(0,1,"eMMC Info: retry ok\n"); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_GetR1(void) ++{ ++ return (g_eMMCDrv.au8_Rsp[1]<<24) | (g_eMMCDrv.au8_Rsp[2]<<16) ++ | (g_eMMCDrv.au8_Rsp[3]<<8) | g_eMMCDrv.au8_Rsp[4]; ++} ++ ++U32 eMMC_CheckR1Error(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ eMMC_FCIE_GetCMDFIFO(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ ++ if(g_eMMCDrv.au8_Rsp[1] & (eMMC_ERR_R1_31_24>>24)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_31_24 \n "); ++ u32_err = eMMC_ST_ERR_R1_31_24; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[2] & (eMMC_ERR_R1_23_16>>16)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_23_16 \n "); ++ u32_err = eMMC_ST_ERR_R1_23_16; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[3] & (eMMC_ERR_R1_15_8>>8)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_15_8 \n "); ++ u32_err = eMMC_ST_ERR_R1_15_8; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[4] & (eMMC_ERR_R1_7_0>>0)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_7_0 \n "); ++ u32_err = eMMC_ST_ERR_R1_7_0; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++LABEL_CHECK_R1_END: ++ ++ /*u8_cs = (eMMC_FCIE_CmdRspBufGet(3) & (eMMC_R1_CURRENT_STATE>>8))>>1; ++ eMMC_debug(0,0,"card state: %d ", u8_cs); ++ switch(u8_cs) { ++ case 0: eMMC_debug(0,0,"(idle)\n"); break; ++ case 1: eMMC_debug(0,0,"(ready)\n"); break; ++ case 2: eMMC_debug(0,0,"(ident)\n"); break; ++ case 3: eMMC_debug(0,0,"(stby)\n"); break; ++ case 4: eMMC_debug(0,0,"(tran)\n"); break; ++ case 5: eMMC_debug(0,0,"(data)\n"); break; ++ case 6: eMMC_debug(0,0,"(rcv)\n"); break; ++ case 7: eMMC_debug(0,0,"(prg)\n"); break; ++ case 8: eMMC_debug(0,0,"(dis)\n"); break; ++ default: eMMC_debug(0,0,"(?)\n"); break; ++ }*/ ++ ++ if(eMMC_ST_SUCCESS != u32_err)// && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R1_BYTE_CNT); ++ } ++ return u32_err; ++} ++ ++ ++// ==================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define UPFW_SEC_WIAT_CNT 0x1000000 ++#define UPFW_SEC_BYTE_CNT (128*1024) ++static U32 eMMC_UpFW_Samsung_Wait(void) ++{ ++ U32 u32_err, u32_cnt, u32_st; ++ ++ for(u32_cnt=0; u32_cnt>eMMC_SECTOR_512BYTE_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: write fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 3, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ // --------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"close ... \n"); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, 0, 28, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD28 fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 4, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ LABEL_END_OF_UPFW: ++ return u32_err; ++ ++} ++#endif // eMMC_UPDATE_FIRMWARE ++ ++#endif // UNIFIED_eMMC_DRIVER ++ +diff --git a/drivers/sstar/emmc/unify_driver/src/common/eMMC_ip_verify.c b/drivers/sstar/emmc/unify_driver/src/common/eMMC_ip_verify.c +new file mode 100755 +index 000000000000..b2d358a5bd2f +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/src/common/eMMC_ip_verify.c +@@ -0,0 +1,2236 @@ ++/* ++* eMMC_ip_verify.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include "eMMC.h" ++#if defined (UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++#define DDR_TEST_BLK_CNT 8 ++#define DDR_TEST_BUFFER_SIZE (eMMC_SECTOR_512BYTE*DDR_TEST_BLK_CNT) ++ ++eMMC_ALIGN0 static U8 gau8_WBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++eMMC_ALIGN0 static U8 gau8_RBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++ ++U32 eMMCTest_BlkWRC_ProbeTiming(U32 u32_eMMC_Addr) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf_DDR, *pu32_R=(U32*)gau8_RBuf_DDR; ++ U32 u32_BlkCnt=eMMC_TEST_BLK_CNT, u32_BufByteCnt; ++ ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ u32_BufByteCnt = u32_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_R[u32_i] = 0; ++ ++ for(u32_j=0; u32_j<9; u32_j++) ++ { ++ // init data pattern ++ switch(u32_j) ++ { ++ case 0: // increase ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = u32_i+1; ++ break; ++ #else ++ continue; ++ #endif ++ case 1: // decrease ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = 0-(u32_i+1); // more FF, more chance to lose start bit ++ break; ++ #else ++ continue; ++ #endif ++ case 2: // 0xF00F ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xF00FF00F; ++ break; ++ case 3: // 0xFF00 ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFF00FF00; ++ break; ++ #else ++ continue; ++ #endif ++ case 4: // 0x5AA5 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5AA55AA5; ++ break; ++ case 5: // 0x55AA ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x55AA55AA; ++ break; ++ #else ++ continue; ++ #endif ++ case 6: // 0x5A5A ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5A5A5A5A; ++ break; ++ #else ++ continue; ++ #endif ++ case 7: // 0x0000 ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x00000000; ++ break; ++ #else ++ continue; ++ #endif ++ case 8: // 0xFFFF ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFFFFFFFF; ++ break; ++ #else ++ continue; ++ #endif ++ } ++ ++ #if 1 ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ break; ++ } ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.single, %Xh \n", u32_err); ++ break; ++ } ++ #endif ++ u32_err = eMMC_CMD25_MIU(u32_eMMC_Addr, gau8_WBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD18_MIU(u32_eMMC_Addr, gau8_RBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, u32_BufByteCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.multi %Xh \n", u32_err); ++ break; ++ } ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //eMMC_debug(0,0,"%s() fail %Xh\n", __FUNCTION__, u32_err); ++ //eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_debug(1,1,"data pattern %u: %02X%02X%02X%02Xh \n\n", ++ u32_j, gau8_WBuf_DDR[3], gau8_WBuf_DDR[2], gau8_WBuf_DDR[1], gau8_WBuf_DDR[0]); ++ } ++ //eMMC_debug(0,0,"%s() return %Xh\n", __FUNCTION__, u32_err); ++ return u32_err; ++} ++ ++ ++//============================================================= ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ ++ ++// can use for RF team test ++#ifndef IP_FCIE_VERSION_5 ++U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, u32_k; ++ U32 u32_BlkCnt, u32_eMMC_Addr; ++ ++ u32_eMMC_Addr = eMMC_TEST_BLK_0; ++ ++ u32_BlkCnt = eMMC_TEST_BLK_CNT; ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ ++ if(8 != u32_BlkCnt) ++ { ++ eMMC_debug(0,1,"Blk count needs to be 8 \n"); ++ while(1); ++ } ++ ++ for(u32_j=0; u32_j>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u32_err = eMMC_CMD24_CIFD(u32_eMMC_Addr, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_CIFD(u32_eMMC_Addr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, FCIE_CIFD_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++extern U32 gu32_DMAAddr; ++U32 eMMCTest_SingleBlkWRC_MIU(U32 u32_eMMC_Addr, U32 u32_DataPattern) ++{ ++ volatile U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ return eMMCTest_SingleBlkWRC_MIU_Ex(u32_eMMC_Addr, (U8*)pu32_W, (U8*)pu32_R); ++} ++ ++ ++U32 eMMCTest_SingleBlkWRC_MIU_Ex(U32 u32_eMMC_Addr, U8 *pu8_W, U8 *pu8_R) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, pu8_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, pu8_R); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(pu8_W, pu8_R, eMMC_SECTOR_BYTECNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++#define eMMC_RETRY_CNT 10 ++ ++U32 eMMCTest_SgW_MIU(U32 u32_eMMC_Addr) ++{ ++ U16 u16_mode, u16_ctrl=0, u16_reg; ++ U32 u32_dmaaddr,u32_dma_addr,u32_dmalen,u32_arg; ++ U32 u32_err,u32_err_12=eMMC_ST_SUCCESS,u32_i; ++ U8 u8_retry_cnt=0; ++ ++ LABEL_RETRY: ++ eMMC_FCIE_ClearEvents(); ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = (BIT_SD_CMD_EN | BIT_SD_RSP_EN); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ // ------------------------------- ++ ++ u32_arg = u32_eMMC_Addr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: R1 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: R1 fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_W : TOGGLE_CNT_256_CLK_W); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ ++ for(u32_i=0; u32_i< MAX_SCATTERLIST_COUNT; u32_i++) ++ { ++ u32_dmaaddr = pSG_st[u32_i].u32_dma_address; ++ u32_dmalen = pSG_st[u32_i].u32_length; ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(u32_dmaaddr, u32_dmalen); ++ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Wait D0 H TO: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ if(u32_i ==0) ++ { ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: FifoClkRdy fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: FifoClkRdy fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ //u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END|BIT_MIU_LAST_DONE, eMMC_GENERIC_WAIT_TIME); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END, eMMC_GENERIC_WAIT_TIME); ++ if(u32_err!= eMMC_ST_SUCCESS) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: event TO: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: event TO \n"); ++ //eMMC_die("\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ break; ++ } ++ //eMMC_hw_timer_delay(1000000); ++ } ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((u16_reg & BIT_SD_FCIE_ERR_FLAGS)||(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Reg.12h: %Xh fail: %Xh \n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, ++ "eMMC Err: Reg.12h: %04Xh, Err: %Xh\n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err_12 && u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD12 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++U32 eMMCTest_SgR_MIU(U32 u32_eMMC_Addr) ++{ ++ U16 u16_mode, u16_ctrl=0, u16_reg; ++ U32 u32_dmaaddr,u32_dma_addr,u32_dmalen,u32_arg; ++ U32 u32_err,u32_err_12=eMMC_ST_SUCCESS,u32_i; ++ U8 u8_retry_cnt=0; ++ ++ LABEL_RETRY: ++ eMMC_FCIE_ClearEvents(); ++ ++ u16_ctrl = BIT_SD_DAT_EN; ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ u16_mode |= BIT_SD_DMA_R_CLK_STOP; ++ ++ REG_FCIE_W(FCIE_SD_MODE, u16_mode); ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ ++ u32_dmaaddr = pSG_st[0].u32_dma_address; ++ u32_dmalen = pSG_st[0].u32_length; ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(u32_dmaaddr, u32_dmalen); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: FifoClkRdy fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: FifoClkRdy fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl |= (BIT_SD_CMD_EN | BIT_SD_RSP_EN); ++ ++ // ------------------------------- ++ u32_arg = u32_eMMC_Addr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "eMMC Err: CMD fail %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ else ++ { ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE, eMMC_GENERIC_WAIT_TIME); ++ if(u32_err!= eMMC_ST_SUCCESS) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: event TO.0: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: event TO.0 \n"); ++ //eMMC_die("\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ return u32_err; ++ } ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((eMMC_ST_SUCCESS != u32_err) || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Reg.12h: %Xh fail: %Xh \n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, ++ "eMMC Err: Reg.12h: %Xh fail: %Xh\n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ for(u32_i=1; u32_i< MAX_SCATTERLIST_COUNT; u32_i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ u32_dmaaddr = pSG_st[u32_i].u32_dma_address; ++ u32_dmalen = pSG_st[u32_i].u32_length; ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(u32_dmaaddr, u32_dmalen); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen>>9); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, TIME_WAIT_n_BLK_END*(1+(u32_dmalen>>24))); ++ if(u32_err!= eMMC_ST_SUCCESS) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: event TO.1: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: event TO.1 \n"); ++ //eMMC_die("\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ break; ++ } ++ } ++ } ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((u16_reg & BIT_SD_FCIE_ERR_FLAGS)||(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Reg.12h: %Xh fail: %Xh \n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: Reg.12h: %Xh fail: %Xh\n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: R1 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: R1 fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err_12 && u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD12 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++U32 eMMCTest_SgWRC_MIU(U32 u32_eMMC_Addr, U16 u16_BlkCnt, U32 u32_DataPattern) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ U32 u32_temp, u32_sg_blocks; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ //check scatterlist count ++ if(u16_BlkCnt % MAX_SCATTERLIST_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: Scatterlist Count Error\n"); ++ return eMMC_ST_ERR_NOT_ALIGN; ++ } ++ ++ u32_sg_blocks = u16_BlkCnt/MAX_SCATTERLIST_COUNT; ++ u32_temp =0; ++ //setting scatterlist dma address and dma length for write multiple block ++ for(u32_i=0; u32_i< MAX_SCATTERLIST_COUNT/4; u32_i++) ++ { ++ for(u32_j=0; u32_j< 4; u32_j++) // 4 groups ++ { ++ pSG_st[u32_i*4+u32_j].u32_dma_address = (U32)(gau8_WBuf+ u32_temp); ++ if(u32_j < 3) // first 3 have 1 block ++ { ++ pSG_st[u32_i*4+u32_j].u32_length = eMMC_SECTOR_512BYTE; ++ u32_temp += eMMC_SECTOR_512BYTE; ++ } ++ else ++ { ++ pSG_st[u32_i*4+u32_j].u32_length = (4*u32_sg_blocks-3)<>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u16_BlkCnt_tmp = TEST_BUFFER_SIZE >> eMMC_SECTOR_512BYTE_BITS; ++ u16_BlkCnt_tmp = u16_BlkCnt_tmp > u16_BlkCnt ? u16_BlkCnt : u16_BlkCnt_tmp; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS; ++ #if IF_eMMC_BOOT_MODE_STG2 ++ au32_Addr[1] = (U32)gau8_BootImage1; ++ au32_SectorCnt[1] = sizeof(gau8_BootImage1)>>eMMC_SECTOR_512BYTE_BITS; ++ au32_Addr[2] = (U32)gau8_BootImage2; ++ au32_SectorCnt[2] = sizeof(gau8_BootImage2)>>eMMC_SECTOR_512BYTE_BITS; ++ #endif ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 1); ++ #else ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 3); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, eMMC_LoadImages: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ //eMMC_debug(0,1,"ChkSum -: %Xh \n", eMMC_ChkSum((U8*)au32_Addr, sizeof(gau8_BootImageOri))); ++ eMMC_debug(0,1,"ChkSum -: %Xh, Addr: %Xh \n", eMMC_ChkSum((U8*)au32_Addr[0], 0xC1< u32_t1) ++ while(0==(u32_t0-eMMC_hw_timer_tick())/eMMC_HW_TIMER_HZ) ++ ; ++ else ++ while(0==(eMMC_hw_timer_tick()-u32_t0)/eMMC_HW_TIMER_HZ) ++ ; ++ #endif ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,".\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"%u %u %u %u %u %u \n", ++ // au32_tmp[0], au32_tmp[1], au32_tmp[2], au32_tmp[3], au32_tmp[4], au32_tmp[5]); ++} ++ ++U32 eMMC_IPVerify_Performance(void) ++{ ++ volatile U32 u32_err, u32_i, u32_SectorAddr=0, u32_SectorCnt=0, u32_t0, u32_t1, u32_t; ++ U8 u8_LoopCnt=0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"SectorBuf:%Xh, RBuf:%Xh, WBuf:%Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMCTest_DownCount(eMMC_SPEED_TEST_COUNTDOWN); ++ for(u32_i=0; u32_i>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_W, 1<>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_W; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ //eMMC_debug(0,0,"%08Xh \n", u32_SectorAddr+u32_i); ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ u32_err = eMMC_CMD24(u32_SectorAddr, gau8_WBuf); ++ #else ++ u32_err = eMMC_CMD24_MIU(u32_SectorAddr, gau8_WBuf); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/1000); // ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u KB/s \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_W<>10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Single Read, total: %u KB, %u blocks, burst size: %Xh\n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R)<>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_R, 1<>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_R; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ u32_err = eMMC_CMD17_MIU(u32_SectorAddr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/1000); // ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u KB/s \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R<>10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ // ================================== ++ u32_SectorCnt = 0; ++ LABEL_MULTI: ++ eMMC_debug(0,0,"------------------------------\n"); ++ switch(u32_SectorCnt) ++ { ++ case 0: ++ u32_SectorCnt = 0x400*4 >> eMMC_SECTOR_512BYTE_BITS; //4KB ++ break; ++ case 0x400*4 >> eMMC_SECTOR_512BYTE_BITS: ++ u32_SectorCnt = 0x400*16 >> eMMC_SECTOR_512BYTE_BITS; //16KB ++ break; ++ case 0x400*16 >> eMMC_SECTOR_512BYTE_BITS: ++ u32_SectorCnt = 0x400*64 >> eMMC_SECTOR_512BYTE_BITS; //64KB ++ break; ++ case 0x400*64 >> eMMC_SECTOR_512BYTE_BITS: ++ u32_SectorCnt = 0x400*1024 >> eMMC_SECTOR_512BYTE_BITS; //1MB ++ break; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Write, total: %u MB, burst size: %u KB\n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20, u32_SectorCnt>>1); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/100); // 10ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u.%u MB/s \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20, ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>10)*10/1024%10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Read, total: %uMB, burst size: %u KB \n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20, u32_SectorCnt>>1); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/10); // 100ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u.%u MB/s \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20, ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>10)*10/1024%10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ if(u32_SectorCnt != 0x400*1024 >> eMMC_SECTOR_512BYTE_BITS) ++ goto LABEL_MULTI; ++ ++ // =============================================== ++ if(0==u8_LoopCnt) ++ { ++ u8_LoopCnt++; ++ ++ eMMC_debug(0,0,"\n\n"); ++ // test for next mode ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: ChooseSpeedMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ goto LABEL_TEST_START; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_Main(void) ++{ ++ U32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC_IPVerify_Main\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"%Xh %Xh %Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ #if 0 ++ eMMC_BootMode(); ++ //while(1); ++ return 0; ++ #endif ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_Init ok] \n"); ++ ++ // =============================================== ++ #if 0 ++ eMMC_debug(0,1,"BootImage ByteCnt: %Xh, ChkSum:%Xh\n", ++ sizeof(gau8_BootImageOri), eMMC_ChkSum(gau8_BootImageOri, sizeof(gau8_BootImageOri))); ++ ++ u32_err = eMMC_WriteBootPart(gau8_BootImageOri, sizeof(gau8_BootImageOri), 0, 1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_WriteBootPart fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "[eMMC_WriteBootPart ok] \n"); ++ ++ while(1); ++ #endif ++ ++ // =============================================== ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal pattern test ok\n\n"); ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "specific pattern test ok\n\n"); ++ ++ #if 1 ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00000000); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal pattern test ok\n\n"); ++ ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "specific pattern test ok\n\n"); ++ #endif ++ ++ #if 1 ++ eMMC_IPVerify_Main_API_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_API_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "APIs test ok\n\n"); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_IPVerify_Main_API_Ex(U32 u32_DataPattern) ++{ ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf, u32_err; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ ++ u32_err = eMMC_WriteData((U8*)pu32_W, TEST_BUFFER_SIZE, eMMC_TEST_BLK_0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_WriteData fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_WriteData ok] \n"); ++ ++ u32_err = eMMC_ReadData((U8*)pu32_R, TEST_BUFFER_SIZE, eMMC_TEST_BLK_0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_ReadData fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_ReadData ok] \n"); ++ ++ u32_err = eMMC_ComapreData((U8*)pu32_W, (U8*)pu32_R, TEST_BUFFER_SIZE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, eMMC_ComapreData fail: %u, %Xh \n", u32_i, u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_Main_Sg_Ex(U32 u32_DataPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt = eMMC_TEST_BLK_CNT; ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ ++ #if 1 ++ u32_err = eMMCTest_SgWRC_MIU(u32_StartSector, u32_SectorCnt, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SgWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SgWRC_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_Main_Ex(U32 u32_DataPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ //eMMC_debug(0,1,"Total Sec: %Xh, StartSec: %Xh, SecCnt: %Xh \n", ++ // g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ ++ #if 1 ++ if(eMMC_IF_NORMAL_SDR()){ ++ u32_err = eMMCTest_SingleBlkWRC_RIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_RIU fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_RIU ok] \n");} ++ #endif ++ ++ #if 1 ++ u32_err = eMMCTest_SingleBlkWRC_MIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMCTest_MultiBlkWRC_MIU(u32_StartSector, u32_SectorCnt, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_MultiBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_MultiBlkWRC_MIU ok] \n"); ++ #endif ++ ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_ReadOnly(void) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ #if 1 ++ if(eMMC_IF_NORMAL_SDR()){ ++ u32_err = eMMC_CMD17_CIFD(u32_StartSector, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD17_CIFD fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD17_CIFD ok] \n");} ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD17_MIU(u32_StartSector, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD17_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD17_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD18_MIU(u32_StartSector, gau8_RBuf, u32_SectorCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD18_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD18_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "fail: %Xh \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_WriteOnly(U16 u16_TestPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, u32_ByteCnt; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ u32_ByteCnt = (u32_SectorCnt<<9) > TEST_BUFFER_SIZE ? ++ TEST_BUFFER_SIZE : (u32_SectorCnt<<9); ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = (u16_TestPattern<<16)+u16_TestPattern; ++ } ++ ++ #if 1 ++ if(eMMC_IF_NORMAL_SDR()){ ++ u32_err = eMMC_CMD24_CIFD(u32_StartSector, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD24_CIFD fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD24_CIFD ok] \n");} ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD24_MIU(u32_StartSector, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD24_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD24_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD25_MIU(u32_StartSector, gau8_WBuf, u32_SectorCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD25_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD25_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "fail: %Xh \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++ ++U32 eMMCTest_Lifetime(U8 u8_TestMode) ++{ ++ U32 u32_i, u32_err=eMMC_ST_SUCCESS, u32_BlkAddr; ++ U32 u32_BlkCnt0=0, u32_BlkCnt1=0, *pu32_BlkCnt, u32_LoopCnt=0; ++ ++ // set to slow & safe clock ++ eMMC_clock_setting(gau8_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT-1]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"===========================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"CAUTION: will damage images in eMMC \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"===========================================\n"); ++ ++ //------------------------------------------------- ++ if(eMMC_LIFETIME_TEST_FIXED == u8_TestMode) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"fixed addr: 6th block\n"); ++ ++ while(1) ++ { ++ eMMC_reset_WatchDog(); ++ ++ if(u32_BlkCnt0 < (U32)(0-1)) ++ pu32_BlkCnt = &u32_BlkCnt0; ++ else if((U32)(0-1) == u32_BlkCnt1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC: %Xh %Xh blocks tested, stop \n", ++ u32_BlkCnt1, u32_BlkCnt0); ++ while(1); ++ } ++ else ++ pu32_BlkCnt = &u32_BlkCnt1; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD18_MIU, %Xh \n", u32_err); ++ break; ++ }u32_err = eMMC_CMD18_MIU( // to drop data from possible cache inside eMMC ++ 100, gau8_RBuf, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD18_MIU, %Xh \n", u32_err); ++ break; ++ } ++ ++ u32_err = eMMC_CMD17_MIU(6, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD17_MIU, %Xh \n", u32_err); ++ break; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, eMMC_SECTOR_BYTECNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, ComapreData, %Xh \n", u32_err); ++ break; ++ } ++ ++ *pu32_BlkCnt+=1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: %08X %08X blocks tested ... ", ++ u32_BlkCnt1, u32_BlkCnt0); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: %Xh %Xh blocks tested, stop \n", ++ u32_BlkCnt1, u32_BlkCnt0); ++ eMMC_FCIE_ErrHandler_Stop(); ++ ++ } ++ //------------------------------------------------- ++ else if(eMMC_LIFETIME_TEST_FILLED == u8_TestMode) ++ { ++ while(1) ++ { ++ eMMC_reset_WatchDog(); ++ ++ if((U32)(0-1) == u32_LoopCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC: %u loops tested, stop \n", ++ u32_LoopCnt); ++ while(1); ++ } ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: w fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_i += TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS; ++ if(g_eMMCDrv.u32_SEC_COUNT-u32_i < ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS)) ++ break; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: w (%08Xh x %08Xh + %08Xh) blocks ... ", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT, u32_i); ++ } ++ // r & c ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: r fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, TEST_BUFFER_SIZE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: c fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_i += TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS; ++ if(g_eMMCDrv.u32_SEC_COUNT-u32_i < ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS)) ++ break; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: r c (%08Xh x %08Xh + %08Xh) blocks ... ", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT, u32_i); ++ } ++ ++ u32_LoopCnt += 1; ++ } ++ } ++ //------------------------------------------------- ++ else if(eMMC_LIFETIME_TEST_RANDOM == u8_TestMode) ++ { ++ eMMC_hw_timer_start(); // use to get tick as a random seed ++ ++ while(1) ++ { ++ eMMC_reset_WatchDog(); ++ ++ if((U32)(0-1) == u32_LoopCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC: %u loops tested, stop \n", ++ u32_LoopCnt); ++ while(1); ++ } ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS)) ++ u32_BlkAddr = g_eMMCDrv.u32_SEC_COUNT ++ - (TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS) - 1; ++ // w ++ u32_err = eMMC_CMD25_MIU(u32_BlkAddr, gau8_WBuf, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: w fail: %Xh, BlkAddr: %Xh \n", u32_err, u32_BlkAddr); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ // r & c ++ u32_err = eMMC_CMD18_MIU(u32_BlkAddr, gau8_RBuf, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: r fail: %Xh, BlkAddr: %Xh \n", u32_err, u32_BlkAddr); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, TEST_BUFFER_SIZE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: c fail: %Xh, BlkAddr: %Xh \n", u32_err, u32_BlkAddr); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_LoopCnt += 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: now @ %08Xh block, total %08Xh x %Xh blocks tested ... ", ++ u32_BlkAddr, u32_LoopCnt, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ } ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void) ++{ ++ U32 u32_err; ++ U8 u8_SDRClkIdx, u8_DDRClkIdx; ++ ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: ChooseSpeedMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ eMMC_DumpTimingTable(); ++ ++ u8_SDRClkIdx = 0; ++ u8_DDRClkIdx = 0; ++ ++ while(1) ++ { ++ #if 1 ++ //eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"SDR\n"); ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ //if(0==u8_SDRClkIdx) u8_SDRClkIdx++; // skip 48MHz ++ eMMC_clock_setting(gau8_FCIEClkSel[u8_SDRClkIdx]); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Clk: %u %sHz\n", ++ g_eMMCDrv.u32_ClkKHz>1000 ? g_eMMCDrv.u32_ClkKHz/1000 : g_eMMCDrv.u32_ClkKHz, ++ g_eMMCDrv.u32_ClkKHz>1000 ? "M" : "K"); ++ u8_SDRClkIdx++; ++ //u8_SDRClkIdx = u8_SDRClkIdx%(eMMC_FCIE_VALID_CLK_CNT-1);// skip 300KHz ++ u8_SDRClkIdx = u8_SDRClkIdx%eMMC_FCIE_VALID_CLK_CNT; ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ #endif ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ // [CAUTION]: switch to fast mode, Brian said a fixed clock for emmcpll, do not switch emmcpll clock. [2013 Nov.. Napoli back] ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: ChooseSpeedMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++#define eMMC_PWRCUT_DATA0 0x55 ++#define eMMC_PWRCUT_DATA1 0xAA ++#define eMMC_PWRCUT_DATA_CNT 2 ++ ++#define eMMC_PWRCUT_TEST_UNIT_BYTECNT 0x1000000 ++#define eMMC_PWRCUT_TEST_SPACE_BYTECNT (16*eMMC_PWRCUT_TEST_UNIT_BYTECNT) // 256MB ++#define eMMC_PWRCUT_TEST_UNIT_CNT (eMMC_PWRCUT_TEST_SPACE_BYTECNT/eMMC_PWRCUT_TEST_UNIT_BYTECNT) ++ ++typedef eMMC_PACK0 struct _eMMC_PWRCUT_CTRLBLK { ++ ++ U32 u32_CheckSum; ++ U8 u8_TargetUnit; ++ U8 au8_TaegetData[eMMC_PWRCUT_TEST_UNIT_CNT]; ++ ++} eMMC_PACK1 eMMC_PWRCUT_CTRLBLK_t; ++ ++void eMMC_DumpsPwrCutCtrlBlk(eMMC_PWRCUT_CTRLBLK_t *pCtrlBlk_t) ++{ ++ U32 u32_i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, ++ "eMMC: CheckSum: %Xh\n", pCtrlBlk_t->u32_CheckSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, ++ "eMMC: TargetUnit: %Xh\n", pCtrlBlk_t->u8_TargetUnit); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, " Target Data: "); ++ for(u32_i=0; u32_iau8_TaegetData[u32_i]); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++} ++ ++U32 eMMC_CheckPwrCutCtrlBlk(U8* u8_DataBuf, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ eMMC_PWRCUT_CTRLBLK_t *pCtrlBlk_t; ++ ++ u32_err = eMMC_ReadData(u8_DataBuf, eMMC_SECTOR_512BYTE, u32_BlkAddr); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: read CtrlBlk, Err:%x\n", u32_err); ++ return u32_err; ++ } ++ ++ pCtrlBlk_t = (eMMC_PWRCUT_CTRLBLK_t*)u8_DataBuf; ++ ++ if(pCtrlBlk_t->u32_CheckSum != ++ eMMC_ChkSum(u8_DataBuf+4, sizeof(eMMC_PWRCUT_CTRLBLK_t)-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: read CtrlBlk, CheckSum fail\n"); ++ return eMMC_ST_ERR_CHKSUM; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMCTest_PwrCut_InitData(U8* u8_DataBuf, U32 u32_BlkStartAddr) ++{ ++ U32 u32_i, u32_j; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ eMMC_PWRCUT_CTRLBLK_t CtrlBlk_t; ++ ++ struct mmc *mmc = find_mmc_device(0); ++ mmc_slc_mode(mmc, 0, 1); // enable reliable ++ ++ // --------------------------------------- ++ CtrlBlk_t.u8_TargetUnit = 0xFF; ++ ++ for(u32_i=0; u32_i>9)); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: Reliable write Fail @ %u unit, Err:%x\n", u32_i, u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"%03u%% \r", (u32_i+1)*100/eMMC_PWRCUT_TEST_UNIT_CNT); ++ } ++ ++ // --------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"\ncheck ...\n"); ++ ++ if(eMMC_ST_SUCCESS != eMMC_CheckPwrCutCtrlBlk(u8_DataBuf, u32_BlkStartAddr-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: read CtrlBlk fail\n"); ++ return eMMC_ST_ERR_CHKSUM; ++ } ++ ++ for(u32_i=0; u32_i>9)); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: Reliable write Fail @ %u unit, Err:%x\n", u32_i, u32_err); ++ return u32_err; ++ } ++ ++ for (u32_j=0; u32_j < eMMC_PWRCUT_TEST_UNIT_BYTECNT; u32_j++) ++ { ++ if (u8_DataBuf[u32_j] != eMMC_PWRCUT_DATA0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: Data Mismatch: Blk:%Xh ByteIdx:%Xh ByteVal:%Xh \n", ++ u32_BlkStartAddr+u32_i*(eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9)+(u32_j>>9), ++ u32_j & 0x1FF, u8_DataBuf[u32_j]); ++ return eMMC_ST_ERR_DATA_MISMATCH; ++ } ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"%03u%% \r", (u32_i+1)*100/eMMC_PWRCUT_TEST_UNIT_CNT); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n init success\n"); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMCTest_PwrCut_Test(U8* u8_DataBuf, U32 u32_BlkStartAddr) ++{ ++ U32 u32_i, u32_j; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U32 u32_T0, u32_BlkAddr; ++ eMMC_PWRCUT_CTRLBLK_t CtrlBlk_t; ++ ++ eMMC_hw_timer_start(); ++ ++ // --------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"\n eMMC PwrCut Test, checking ...\n"); ++ ++ // get Ctrl Blk ++ if(eMMC_ST_SUCCESS != eMMC_CheckPwrCutCtrlBlk(u8_DataBuf, u32_BlkStartAddr)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: read CtrlBlk fail\n"); ++ //return eMMC_ST_ERR_CHKSUM; ++ while(1); ++ } ++ memcpy(&CtrlBlk_t, u8_DataBuf, sizeof(eMMC_PWRCUT_CTRLBLK_t)); ++ ++ // check data ++ u32_BlkStartAddr++; ++ ++ for(u32_i=0; u32_i>9)); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, ++ "\neMMC Err: Reliable write Fail @ %u unit, Err:%x\n", u32_i, u32_err); ++ return u32_err; ++ } ++ ++ if(u32_i == CtrlBlk_t.u8_TargetUnit){ ++ for (u32_j=0; u32_j < eMMC_PWRCUT_TEST_UNIT_BYTECNT; u32_j++) ++ { ++ if (u8_DataBuf[u32_j]!=eMMC_PWRCUT_DATA0 && ++ u8_DataBuf[u32_j]!=eMMC_PWRCUT_DATA1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, ++ "\neMMC Err: Target Data Mismatch: Unit:%Xh " ++ "Blk: %Xh + %Xh x %Xh + %Xh = %Xh, ByteIdx:%Xh ByteVal:%Xh \n", ++ u32_i, ++ u32_BlkStartAddr, u32_i, (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9), (u32_j>>9), ++ u32_BlkStartAddr+u32_i*(eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9)+(u32_j>>9), ++ u32_j & 0x1FF, u8_DataBuf[u32_j]); ++ eMMC_DumpsPwrCutCtrlBlk(&CtrlBlk_t); ++ eMMC_dump_mem(&u8_DataBuf[u32_j]-0x10, 0x30); ++ return eMMC_ST_ERR_DATA_MISMATCH; ++ } ++ } ++ // recover TargetUnit ++ u32_BlkAddr = u32_BlkStartAddr + ++ CtrlBlk_t.u8_TargetUnit * ++ (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>eMMC_SECTOR_512BYTE_BITS); ++ memset(u8_DataBuf, CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit], eMMC_PWRCUT_TEST_UNIT_BYTECNT); ++ u32_err = eMMC_WriteData(u8_DataBuf, eMMC_PWRCUT_TEST_UNIT_BYTECNT, u32_BlkAddr); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: write TargetUnit fail, Err:%x\n",u32_err); ++ return u32_err; ++ }} ++ else{ ++ for (u32_j=0; u32_j < eMMC_PWRCUT_TEST_UNIT_BYTECNT; u32_j++) ++ { ++ if (u8_DataBuf[u32_j]!=CtrlBlk_t.au8_TaegetData[u32_i]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, ++ "\neMMC Err: Data Mismatch: Unit:%Xh " ++ "Blk: %Xh + %Xh x %Xh + %Xh = %Xh, ByteIdx:%Xh ByteVal:%Xh \n", ++ u32_i, ++ u32_BlkStartAddr, u32_i, (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9), (u32_j>>9), ++ u32_BlkStartAddr+u32_i*(eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9)+(u32_j>>9), ++ u32_j & 0x1FF, u8_DataBuf[u32_j]); ++ eMMC_DumpsPwrCutCtrlBlk(&CtrlBlk_t); ++ eMMC_dump_mem(&u8_DataBuf[u32_j]-0x10, 0x30); ++ //return eMMC_ST_ERR_DATA_MISMATCH; ++ while(1); ++ } ++ }} ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"%03u%% \r", (u32_i+1)*100/eMMC_PWRCUT_TEST_UNIT_CNT); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0," ok\n"); ++ ++ // --------------------------------------- ++ while(1) ++ { ++ u32_T0 = eMMC_hw_timer_tick(); ++ CtrlBlk_t.u8_TargetUnit = u32_T0 % eMMC_PWRCUT_TEST_UNIT_CNT; ++ CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit] ^= 0xFF; ++ CtrlBlk_t.u32_CheckSum = eMMC_ChkSum((U8*)&CtrlBlk_t.u8_TargetUnit, ++ sizeof(eMMC_PWRCUT_CTRLBLK_t)-4); ++ u32_err = eMMC_WriteData((U8*)&CtrlBlk_t, eMMC_SECTOR_512BYTE, u32_BlkStartAddr-1); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: write CtrlBlk, Err:%x\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_BlkAddr = u32_BlkStartAddr + ++ CtrlBlk_t.u8_TargetUnit * ++ (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>eMMC_SECTOR_512BYTE_BITS); ++ memset(u8_DataBuf, CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit], eMMC_PWRCUT_TEST_UNIT_BYTECNT); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0 ,"writing... %02Xh %08Xh %02Xh\n", ++ CtrlBlk_t.u8_TargetUnit, u32_BlkAddr, CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit]); ++ ++ u32_err = eMMC_WriteData(u8_DataBuf, eMMC_PWRCUT_TEST_UNIT_BYTECNT, u32_BlkAddr); ++ //u32_err = eMMC_CMD25(u32_BlkAddr, u8_DataBuf, eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: write Fail, Err:%x\n",u32_err); ++ return u32_err; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMCTest_PwrCut_Test2(U8* u8_DataBuf, U32 u32_BlkStartAddr) ++{ ++ U32 u32_blk_cnt ,u32_i,u32_test_loop; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U8 data; ++ ++ struct mmc *mmc = find_mmc_device(0); ++ ++ if (!mmc) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: no mmc device at slot\n"); ++ return 1; ++ } ++ ++ if(!mmc->has_init) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Need mmc init first!\n"); ++ return 1; ++ } ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: Reliable write ext_csd[167] 0x%02x, ext_csd[166] 0x%02x\n", mmc->ext_csd[167], mmc->ext_csd[166]); ++ ++ if (mmc->reliable_write == 1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: Reliable write is supported but unconfigured\n"); ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, EXT_CSD_WR_REL_SET, 0x1f); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // complete the partition configuration ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, EXT_CSD_PARTITION_SETTING_COMPLETED, 0x01); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ mmc->reliable_write = 2; ++ ++ while (1) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: Please reset the board!!!!!! Reliable write would be active after reset!!!!!!\n"); ++ } ++ else if (mmc->reliable_write == 2) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1,"eMMC Info: Reliable write is supported and has been configured\n"); ++ } ++ else if (mmc->reliable_write == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Info: Reliable write is unsupported\n"); ++ while(1); ++ } ++ ++ u32_blk_cnt = (48 *1024 * 1024)>>eMMC_SECTOR_512BYTE_BITS; ++ ++ memset(u8_DataBuf, 0, (48 *1024 * 1024)); ++ //step1 ++ u32_err = eMMC_ReadData(u8_DataBuf, u32_blk_cnt<>9,u32_i & 0x1FF, u8_DataBuf[u32_i], data); ++ return eMMC_ST_ERR_DATA_MISMATCH; ++ } ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Reliable read compare success\n"); ++ ++ data = (U8)eMMC_hw_timer_tick();//rRand((unsigned int)data, (unsigned int)(u8_DataBuf - data)); ++ memset(u8_DataBuf, data, (48 *1024 * 1024)); ++ u32_test_loop=0; ++ ++ u32_err = eMMC_WriteData(u8_DataBuf, (48 *1024 * 1024), u32_BlkStartAddr); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Reliable write Fail,Err:%x\n",u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Reliable write Success\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"power cut test loop star\n"); ++ ++ u32_BlkStartAddr += ((48 *1024 * 1024) >> eMMC_SECTOR_512BYTE_BITS); ++ u32_blk_cnt = (4 *1024 * 1024)>>eMMC_SECTOR_512BYTE_BITS; ++ while(1) ++ { ++ //step3 ++ for (u32_i=0; u32_i < u32_blk_cnt; u32_i++) ++ { ++ u32_err = eMMC_WriteData(u8_DataBuf+(u32_i<= 32 && buf[i] < 128) ? buf[i] : '.'); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "\n"); ++} ++ ++void eMMC_dump_mem(unsigned char *buf, U32 cnt) ++{ ++ U32 i; ++ ++ for (i= 0; i < cnt; i+= 16) ++ dump_mem_line(buf + i, 16); ++} ++ ++static __inline void dump_mem_line_32(U32 *buf, int cnt) ++{ ++ U32 i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " 0x%08lX: ", (uintptr_t)buf); ++ for (i= 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%08Xh ", buf[i]); ++} ++ ++void eMMC_dump_mem_32(U32 *buf, U32 cnt) ++{ ++ U32 i; ++ ++ for (i= 0; i < cnt; i+= 8) ++ { ++ dump_mem_line_32(buf + i, 8); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " | 0x%08X \n", i+7); ++ } ++} ++ ++ ++ ++U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt) ++{ ++ U32 u32_i, u32_offset; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS)<>11); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "eMMC BUS_WIDTH: %Xh\n", g_eMMCDrv.u8_BUS_WIDTH); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TRIM: %Xh\n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_TRIM)?1:0); ++ ++ if(g_eMMCDrv.u32_eMMCFlag & (eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13)) ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: CMD%u \n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_HPI_CMD12)?12:13); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: 0 \n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"Reliable Write BlkCnt: %Xh\n", g_eMMCDrv.u16_ReliableWBlkCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"Power Off Notification: ECSD[34]:%Xh, Short: %u ms, Long: %u ms\n", ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl, ++ g_eMMCDrv.u8_ECSD248_CMD6TO*10, ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO*10); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ // ------------------------------ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(0, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CSD:\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CSD[0], eMMC_MAX_RSP_BYTE_CNT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "SPEC_VERS: %Xh, R_BL_LEN: %Xh, W_BL_LEN: %Xh \n", ++ g_eMMCDrv.u8_SPEC_VERS, g_eMMCDrv.u8_R_BL_LEN, g_eMMCDrv.u8_W_BL_LEN); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "Access Mode: %s\n", g_eMMCDrv.u8_IfSectorMode?"Sector":"Byte"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "C_SIZE: %Xh\n", g_eMMCDrv.u16_C_SIZE); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "ERASE_GRP_SIZE: %Xh, ERASE_GRP_MULT: %Xh\n", ++ g_eMMCDrv.u8_ERASE_GRP_SIZE, g_eMMCDrv.u8_ERASE_GRP_MULT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "EraseUnitSize: %u\n", g_eMMCDrv.u32_EraseUnitSize); ++ switch(g_eMMCDrv.u8_Tran_Speed) ++ { ++ case 0x2A: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 20MHz\n"); break; ++ case 0x32: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 26MHz\n"); break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal TRAN_SPEED: %Xh\n", g_eMMCDrv.u8_Tran_Speed); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TAAC: %Xh, NSAC: %Xh, R2W_FACTOR: %Xh\n", ++ g_eMMCDrv.u8_TAAC, g_eMMCDrv.u8_NSAC, g_eMMCDrv.u8_R2W_FACTOR); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "RCA: %Xh\n", g_eMMCDrv.u16_RCA); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CID:\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CID[1], eMMC_MAX_RSP_BYTE_CNT-1); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ return u32_err; ++} ++ ++ ++void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ int i; ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC NNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "peMMCInfo: 0x%08lX\n", (uintptr_t)peMMCInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_Tag : ["); ++ for (i = 0; i < 16; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%c", peMMCInfo->au8_Tag[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_IDByteCnt : 0x%04x\n", peMMCInfo->u8_IDByteCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_ID : 0x[ "); ++ for (i = 0; i < peMMCInfo->u8_IDByteCnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%02X ", peMMCInfo->au8_ID[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", peMMCInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", peMMCInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", peMMCInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", peMMCInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", peMMCInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_Config : 0x%08X\n", peMMCInfo->u32_Config); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_ECCType : 0x%04x\n", peMMCInfo->u16_ECCType); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SeqAccessTime: 0x%04x\n", peMMCInfo->u16_SeqAccessTime); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_Vendor: %s\n", peMMCInfo->au8_Vendor); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PartNumber: %s\n", peMMCInfo->au8_PartNumber); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapLoc: 0x%04x\n", peMMCInfo->u8_PairPageMapLoc); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapType: 0x%04x\n", peMMCInfo->u8_PairPageMapType); ++#endif ++} ++ ++void eMMC_dump_pni(eMMC_PNI_t *pPartInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC PNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "pPartInfo: 0x%08lX\n", (uintptr_t)pPartInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", pPartInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PartCnt : 0x%04x\n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_UnitByteCnt : 0x%04x\n", pPartInfo->u16_UnitByteCnt); ++ ++ //dump_part_records(pPartInfo->records, pPartInfo->u16_PartCnt); ++#endif ++} ++ ++void eMMC_dump_WR_Count(void) ++{ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "CNT_CMD17: %u, CNT_CMD24: %u \n", g_eMMCDrv.u32_CNT_CMD17, g_eMMCDrv.u32_CNT_CMD24); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "CNT_CMD18: %u, CNT_CMD25: %u \n", g_eMMCDrv.u32_CNT_CMD18, g_eMMCDrv.u32_CNT_CMD25); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "TotalRBlk: %llu, TotalWBlk: %llu \n", g_eMMCDrv.u64_CNT_TotalRBlk, g_eMMCDrv.u64_CNT_TotalWBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "MinRBlk: %u, MinWBlk: %u \n", g_eMMCDrv.u32_CNT_MinRBlk, g_eMMCDrv.u32_CNT_MinWBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "MaxRBlk: %u, MaxWBlk: %u \n", g_eMMCDrv.u32_CNT_MaxRBlk, g_eMMCDrv.u32_CNT_MaxWBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "RHitCnt: %u, WHitCnt: %u \n", g_eMMCDrv.u32_Addr_RHitCnt, g_eMMCDrv.u32_Addr_WHitCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "au32_CNT_MinRBlk: \n"); ++ eMMC_dump_mem_32(g_eMMCDrv.au32_CNT_MinRBlk, 0x200); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "au32_CNT_MinWBlk: \n"); ++ eMMC_dump_mem_32(g_eMMCDrv.au32_CNT_MinWBlk, 0x200); ++ ++ #endif ++} ++ ++#endif +diff --git a/drivers/sstar/emmc/unify_driver/src/config/eMMC_platform.c b/drivers/sstar/emmc/unify_driver/src/config/eMMC_platform.c +new file mode 100755 +index 000000000000..5d36c60abdca +--- /dev/null ++++ b/drivers/sstar/emmc/unify_driver/src/config/eMMC_platform.c +@@ -0,0 +1,767 @@ ++/* ++* eMMC_platform.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include "eMMC.h" ++ ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++// ++static U32 _gu32MaxClk = 0; ++ ++void eMMC_Prepare_Power_Saving_Mode_Queue(void) ++{ ++ #if (defined(eMMC_DRV_CHICAGO_LINUX) && eMMC_DRV_CHICAGO_LINUX) ++ REG_FCIE_SETBIT(REG_BATTERY, reg_nobat_int_en); ++ ++ /* (1) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x40), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x41), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (2) Clear All Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x42), 0xffff); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x43), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (3) Clear SDE MODE Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x44), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x45), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (4) Clear SDE CTL Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x46), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x47), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (5) Reset Start */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x48), 0x4800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x49), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (6) Reset End */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4A), 0x5800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (7) Set "SD_MOD" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4C), 0x0051); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (8) Enable "csreg_sd_en" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4E), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (9) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x50), 0x0040); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x51), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x00); ++ ++ /* (10) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x52), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x53), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x01); ++ ++ /* (11) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x54), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x55), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x02); ++ ++ /* (12) Command Size */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x56), 0x0005); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x57), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0E); ++ ++ /* (13) Response Size */ ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x58), 0x0000); ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x59), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0D); ++ ++ /* (14) Enable Interrupt, SD_CMD_END */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5A), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x01); ++ ++ /* (15) Command Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5C), 0x0004); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (16) Wait Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5E), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WINT); ++ ++ /* (17) Clear Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x60), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x61), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (18) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x62), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x63), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (19) STOP */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x64), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x65), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_STOP); ++ ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, BIT_POWER_SAVE_MODE_EN | BIT_SD_POWER_SAVE_RST); ++ #endif ++} ++ ++ ++//============================================================= ++#if eMMC_DRV_LINUX ++//============================================================= ++U8 gau8_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT]={ ++ BIT_FCIE_CLK_48M, ++ BIT_FCIE_CLK_40M, ++ BIT_FCIE_CLK_36M, ++ BIT_FCIE_CLK_32M, ++ BIT_FCIE_CLK_20M, ++}; ++U32 gu32_eMMCDrvExtFlag = 0; ++ ++#if defined(MSTAR_EMMC_CONFIG_OF) ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++struct clk_data{ ++ int num_parents; ++ struct clk **clk_fcie; ++// struct clk *clk_ecc; ++}; ++extern struct clk_data *clkdata; ++#endif ++#endif ++ ++void mdelay_MacroToFun(u32 time) ++{ ++ mdelay(time); ++} ++ ++U32 eMMC_hw_timer_delay(U32 u32usTick) ++{ ++ volatile U32 u32_i=u32usTick; ++ ++ while(u32_i>1000) ++ { ++ udelay(1000); ++ u32_i-=1000; ++ } ++ ++ udelay(u32usTick); ++ return u32usTick + 1; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ return 0; ++} ++ ++void eMMC_DumpPadClk(void) ++{ ++ //--------------------------------------------------------------------- ++ eMMC_debug(0, 0, "[pad setting]:\r\n"); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_BYPASS: eMMC_debug(0, 0, "Bypass\r\n"); break; ++ case FCIE_eMMC_SDR: eMMC_debug(0, 0, "SDR\r\n"); break; ++ default: ++ eMMC_debug(0, 0, "eMMC Err: Pad unknown, %d\r\n", g_eMMCDrv.u8_PadType); eMMC_die("\r\n"); ++ break; ++ } ++} ++ ++U8 gu8_NANDeMMC_need_preset_flag = 1; ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ g_eMMCDrv.u8_PadType = u32_FCIE_IF_Type; ++ ++#if INIT_PADMUX ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT_ALL_PAD_IN); ++ REG_FCIE_CLRBIT(reg_sd_config, BIT_SD_MODE_MASK); ++#endif ++ ++#if !(SDIO_SETTING_ONLY) ++ #if defined(BIT_EMMC_MODE_8X) ++ REG_FCIE_CLRBIT(reg_sdio_config, BIT_SDIO_MODE_MASK); ++ //Move pad switch to mstar_mci_probe() in mstar_mci_v5.c ++ #else ++ REG_FCIE_CLRBIT(reg_nand_config, BIT_NAND_MODE_MASK); ++ REG_FCIE_SETBIT(reg_emmc_config, BIT_EMMC_MODE_1); ++ #endif ++#endif ++ ++#if PADMUX_CTRL ++ REG_FCIE_CLRBIT(reg_sd_config, BIT_SD_MODE_MASK); ++ REG_FCIE_SETBIT(reg_sd_config, BIT_SD_MODE_SEL); ++#endif ++ ++ // fcie ++ REG_FCIE_CLRBIT(FCIE_DDR_MODE, BIT_MACRO_MODE_MASK); ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 1, "SDR\r\n"); ++ ++ REG_FCIE_SETBIT(FCIE_DDR_MODE, BIT_PAD_IN_SEL_SD|BIT_FALL_LATCH|BIT10); ++ ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++#if 0 //defined(MSTAR_EMMC_CONFIG_OF) ++ U32 u32_clkrate = 0; ++ switch(u16_ClkParam) ++ { ++ case BIT_FCIE_CLK_300K: ++ u32_clkrate = 300*1000; ++ break; ++ case BIT_CLK_XTAL_12M: ++ u32_clkrate = 12*1000*1000; ++ break; ++ case BIT_FCIE_CLK_20M: ++ u32_clkrate = 20*1000*1000; ++ break; ++ case BIT_FCIE_CLK_32M: ++ u32_clkrate = 32*1000*1000; ++ break; ++ case BIT_FCIE_CLK_36M: ++ u32_clkrate = 36*1000*1000; ++ break; ++ case BIT_FCIE_CLK_40M: ++ u32_clkrate = 40*1000*1000; ++ break; ++ case BIT_FCIE_CLK_43_2M: ++ u32_clkrate = 43*1000*1000; ++ break; ++ case BIT_FCIE_CLK_48M: ++ u32_clkrate = 48*1000*1000; ++ break; ++ default: ++ eMMC_die(); ++ break; ++ } ++ //printk("set clock %d\n", u32_clkrate); ++ g_eMMCDrv.u32_ClkKHz = u32_clkrate/1000; ++ g_eMMCDrv.u16_ClkRegVal = u16_ClkParam; ++ clk_set_rate(clkdata->clk_fcie[0], u32_clkrate); ++#else ++ eMMC_PlatformResetPre(); ++ ++#if MAX_CLK_CTRL ++ //printk("u16_ClkParam = %d\r\n",u16_ClkParam); ++ //printk("_gu32MaxClk = %d\r\n",_gu32MaxClk); ++ if (u16_ClkParam < _gu32MaxClk) ++ { ++ u16_ClkParam = _gu32MaxClk; ++ } ++#endif ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_CLK_XTAL_12M: g_eMMCDrv.u32_ClkKHz = 12000; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ //eMMC_debug(0, 1, "clock %dk\n", g_eMMCDrv.u32_ClkKHz); ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie, BIT0|BIT1); ++ REG_FCIE_CLRBIT(reg_ckg_fcie, BIT_CLKGEN_FCIE_MASK|BIT_FCIE_CLK_SRC_SEL); ++ REG_FCIE_SETBIT(reg_ckg_fcie, u16_ClkParam<<2); ++ REG_FCIE_SETBIT(reg_ckg_fcie, BIT_FCIE_CLK_SRC_SEL); //reg_ckg_sdio(BK:x1038_x43) [B5] -> 0:clk_boot 1:clk_sd ++ ++ REG_FCIE_SETBIT(reg_sc_gp_ctrl, BIT_CKG_SD); //reg_ckg_sd(BK:x1133_x25) [B3]SDIO30 [B7]SD30 -> 0:clk_boot 1:clk_sd ++ ++ g_eMMCDrv.u16_ClkRegVal = u16_ClkParam; ++ ++#endif ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_clock_gating(void) ++{ ++ eMMC_PlatformResetPre(); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_CLK_EN); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++extern struct platform_device sg_mstar_emmc_device_st; ++ ++dma_addr_t eMMC_DMA_MAP_address(uintptr_t ulongBuffer, U32 u32_ByteCnt, int mode) ++{ ++ dma_addr_t dma_addr; ++ ++ if(mode == 0) //write ++ { ++ dma_addr = dma_map_single(&sg_mstar_emmc_device_st.dev, (void*)ulongBuffer, u32_ByteCnt, DMA_TO_DEVICE); ++ } ++ else ++ { ++ dma_addr = dma_map_single(&sg_mstar_emmc_device_st.dev, (void*)ulongBuffer, u32_ByteCnt, DMA_FROM_DEVICE); ++ } ++ ++ if( dma_mapping_error(&sg_mstar_emmc_device_st.dev, dma_addr) ) ++ { ++ dma_unmap_single(&sg_mstar_emmc_device_st.dev, dma_addr, u32_ByteCnt, (mode) ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ eMMC_die("eMMC_DMA_MAP_address: Kernel can't mapping dma correctly\n"); ++ } ++ ++ return dma_addr; ++} ++ ++void eMMC_DMA_UNMAP_address(dma_addr_t dma_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++ if(mode == 0) //write ++ { ++ dma_unmap_single(&sg_mstar_emmc_device_st.dev, dma_DMAAddr, u32_ByteCnt, DMA_TO_DEVICE); ++ } ++ else ++ { ++ dma_unmap_single(&sg_mstar_emmc_device_st.dev, dma_DMAAddr, u32_ByteCnt, DMA_FROM_DEVICE); ++ } ++} ++ ++#if 0 ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++#if 1 ++ //mode 0 for write, 1 for read ++ if( mode == WRITE_TO_eMMC ) //Write ++ { ++ //Write (DRAM->NAND)-> flush ++ Chip_Clean_Cache_Range(u32_DMAAddr, u32_ByteCnt); ++ } ++ else //Read ++ { ++ //Read (NAND->DRAM) -> inv ++ Chip_Flush_Cache_Range(u32_DMAAddr, u32_ByteCnt); ++ } ++ /* ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ { ++ REG_SET_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ } ++ else ++ REG_CLR_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ */ ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++#else ++ flush_cache(u32_DMAAddr, u32_ByteCnt); ++ return (u32_DMAAddr); ++#endif ++} ++#else ++extern U32 MIU0_BUS_ADDR; ++U32 eMMC_translate_DMA_address_Ex(dma_addr_t dma_DMAAddr, U32 u32_ByteCnt) ++{ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ dma_DMAAddr -= MSTAR_MIU0_BUS_BASE; ++ ++ return ((U32)dma_DMAAddr); ++} ++ ++#endif ++/* ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ flush_cache(u32_addr, s32_size); ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++*/ ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 0 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ // one time enable one bit ++ ++ REG_FCIE_R(FCIE_PWR_SAVE_CTL, u16_Events); ++ ++ if(u16_Events & BIT_POWER_SAVE_MODE_INT) ++ { ++ REG_FCIE_CLRBIT(FCIE_PWR_SAVE_CTL, BIT_POWER_SAVE_MODE_INT_EN); ++ fcie_int = 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, "SAR5 eMMC WARN.\n"); ++ while(1); ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++ if((REG_FCIE(FCIE_MIE_FUNC_CTL) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & (BIT_DMA_END|BIT_ERR_STS)) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ else if(u16_Events & BIT_BUSY_END_INT) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_BUSY_END_INT); ++ REG_FCIE_CLRBIT(FCIE_SD_CTRL, BIT_BUSY_DET_ON); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ ++ return IRQ_HANDLED; ++ } ++ #endif ++ ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(uintptr_t u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i ++//extern struct semaphore PfModeSem; ++extern struct mutex FCIE3_mutex; ++//#define CRIT_SECT_BEGIN(x) mutex_lock(x) ++//#define CRIT_SECT_END(x) mutex_unlock(x) ++ ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ mutex_lock(&FCIE3_mutex); ++ #if defined (MSTAR_EMMC_CONFIG_OF) ++ { ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ int i; ++ for(i = 0 ;i < clkdata->num_parents; i ++) ++ clk_prepare_enable(clkdata->clk_fcie[i]); ++#endif ++ } ++ #endif ++ ++ #if IF_FCIE_SHARE_IP // && defined(CONFIG_MS_SDMMC) ++// if(false == ms_sdmmc_wait_d0_for_emmc()) ++// { ++// eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++// eMMC_FCIE_ErrHandler_Stop(); ++// } ++ ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, 2<num_parents; i ++) ++ clk_disable_unprepare(clkdata->clk_fcie[i]); ++#endif ++ } ++ #endif ++ ++ mutex_unlock(&FCIE3_mutex); ++} ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ #if defined(ENABLE_EMMC_POWER_SAVING_MODE) && ENABLE_EMMC_POWER_SAVING_MODE ++ eMMC_Prepare_Power_Saving_Mode_Queue(); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++struct page *eMMC_SectorPage = 0; ++struct page *eMMC_PartInfoPage = 0; ++U8 *gau8_eMMC_SectorBuf = 0; // 512 bytes ++U8 *gau8_eMMC_PartInfoBuf =0; // 512 bytes ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(EMMC_DEFO_SPEED_MODE); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ if(gau8_eMMC_SectorBuf == NULL) ++ { ++ eMMC_SectorPage = alloc_pages(__GFP_COMP, 2); ++ if(eMMC_SectorPage ==NULL) ++ { ++ eMMC_debug(0, 1, "Err allocate page 1 fails\n"); ++ eMMC_die(); ++ } ++ gau8_eMMC_SectorBuf =(U8*) kmap(eMMC_SectorPage); ++ } ++ ++ if(gau8_eMMC_PartInfoBuf == NULL) ++ { ++ eMMC_PartInfoPage = alloc_pages(__GFP_COMP, 0); ++ if(eMMC_PartInfoPage ==NULL) ++ { ++ eMMC_debug(0, 1, "Err allocate page 2 fails\n"); ++ eMMC_die(); ++ } ++ gau8_eMMC_PartInfoBuf = (U8*)kmap(eMMC_PartInfoPage); ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_BootPartitionHandler_E(U16 u16_PartType) ++{ ++ return eMMC_ST_SUCCESS; ++} ++ ++// -------------------------------------------- ++static U32 sgu32_MemGuard0 = 0xA55A; ++eMMC_ALIGN0 eMMC_DRIVER g_eMMCDrv eMMC_ALIGN1; ++static U32 sgu32_MemGuard1 = 0x1289; ++ ++U32 eMMC_CheckIfMemCorrupt(void) ++{ ++ if(0xA55A != sgu32_MemGuard0 || 0x1289 != sgu32_MemGuard1) ++ return eMMC_ST_ERR_MEM_CORRUPT; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++int mstar_mci_Housekeep(void *pData) ++{ ++ #if !(defined(eMMC_HOUSEKEEP_THREAD) && eMMC_HOUSEKEEP_THREAD) ++ return 0; ++ #endif ++ ++ ++ ++ while(1) ++ { ++ if(kthread_should_stop()) ++ break; ++ } ++ ++ return 0; ++} ++ ++U32 eMMC_PlatformDeinit(void) ++{ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ++void eMMC_SetMaxClk(U32 clk) ++{ ++ _gu32MaxClk = clk; ++} ++ ++#else ++ ++ ++ #error "Error! no platform functions." ++#endif ++#endif +diff --git a/drivers/sstar/flash_isp/Kconfig b/drivers/sstar/flash_isp/Kconfig +new file mode 100755 +index 000000000000..a486f64ac43b +--- /dev/null ++++ b/drivers/sstar/flash_isp/Kconfig +@@ -0,0 +1,43 @@ ++config MS_FLASH_ISP ++ ++ select MTD ++ #select MTD_CHAR ++ #select MTD_BLKDEVS ++ #select NFTL ++ #select NFTL_RW ++ #select MTD_OOPS ++ ++ #select MTD_COMPLEX_MAPPINGS ++ #select MTD_BLOCK2MTD ++ #select MTD_CMDLINE_PARTS ++ #select SCSI_LOWLEVEL ++ #select AUTOFS_FS ++ ++ #select FAT_FS ++ #select MSDOS_FS ++ #select VFAT_FS ++ ++ #select MTD_DEBUG ++ #select MTD_DEBUG_VERBOSE ++ #select MTD_CONCAT ++ #select MTD_PARTITIONS ++ #select MTD_NAND ++ #select JFFS2_FS ++ #select JFFS2_FS_DEBUG ++ #select JFFS2_FS_WRITEBUFFER ++ ++bool "Serial Flash driver" ++default n ++---help--- ++ Enable compilation option for Serial Flash. ++ FSP support Quadread/Daulread/write with BDMA. ++ ++if MS_FLASH_ISP ++config MS_FLASH_ISP_MXP_PARTS ++ bool ++ default y ++ ++ ++endif ++ ++ +diff --git a/drivers/sstar/flash_isp/Makefile b/drivers/sstar/flash_isp/Makefile +new file mode 100644 +index 000000000000..444ee9f66750 +--- /dev/null ++++ b/drivers/sstar/flash_isp/Makefile +@@ -0,0 +1,20 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/flash_isp ++EXTRA_CFLAGS += -Idrivers/sstar/flash_isp/include ++EXTRA_CFLAGS += -Idrivers/sstar/flash_isp/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/bdma/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_FLASH_ISP) += drvSERFLASH.o mtd_serflash.o drvDeviceInfo.o ++obj-$(CONFIG_MS_FLASH_ISP) += $(CONFIG_SSTAR_CHIP_NAME)/halSERFLASH.o ++obj-$(CONFIG_MS_FLASH_ISP_MXP_PARTS) += part_mxp.o mxp_flash.o ++ ++ ++ +diff --git a/drivers/sstar/flash_isp/drvDeviceInfo.c b/drivers/sstar/flash_isp/drvDeviceInfo.c +new file mode 100755 +index 000000000000..be791cd91a7d +--- /dev/null ++++ b/drivers/sstar/flash_isp/drvDeviceInfo.c +@@ -0,0 +1,1658 @@ ++/* ++* drvDeviceInfo.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "MsTypes.h" ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++ ++ ++ ++// ++// Special Block Table (List) ++// ++ ++ST_SPECIAL_BLOCKS _stSpecialBlocks_EN25F10 = ++{ ++ .u16Start = 0, // Start block# of special block size ++ .u16End = 3, // End block# of special block size ++ .au32SizeList = // List of special size;Total size must be equal to block size ++ { ++ SIZE_32KB, ++ SIZE_32KB, ++ SIZE_32KB, ++ SIZE_32KB, ++ } ++}; ++ ++ST_SPECIAL_BLOCKS _stSpecialBlocks_EN25B32B = ++{ ++ .u16Start = 0, // Start block# of special block size ++ .u16End = 4, // End block# of special block size ++ .au32SizeList = // List of special size;Total size must be equal to block size ++ { ++ SIZE_4KB, ++ SIZE_4KB, ++ SIZE_8KB, ++ SIZE_16KB, ++ SIZE_32KB, ++ } ++}; ++ ++ST_SPECIAL_BLOCKS _stSpecialBlocks_EN25B64B = ++{ ++ .u16Start = 0, // Start block# of special block size ++ .u16End = 4, // End block# of special block size ++ .au32SizeList = // List of special size;Total size must be equal to block size ++ { ++ SIZE_4KB, ++ SIZE_4KB, ++ SIZE_8KB, ++ SIZE_16KB, ++ SIZE_32KB, ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++// Write Protect Table (List) ++//------------------------------------------------------------------------------------------------- ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X32[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x003F0000, 0x003FFFFF }, ++ { BITS(5:2, 2), 0x003E0000, 0x003FFFFF }, ++ { BITS(5:2, 3), 0x003C0000, 0x003FFFFF }, ++ { BITS(5:2, 4), 0x00380000, 0x003FFFFF }, ++ { BITS(5:2, 5), 0x00300000, 0x003FFFFF }, ++ { BITS(5:2, 6), 0x00200000, 0x003FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0000FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x007E0000, 0x007FFFFF }, ++ { BITS(5:2, 2), 0x007C0000, 0x007FFFFF }, ++ { BITS(5:2, 3), 0x00780000, 0x007FFFFF }, ++ { BITS(5:2, 4), 0x00700000, 0x007FFFFF }, ++ { BITS(5:2, 5), 0x00600000, 0x007FFFFF }, ++ { BITS(5:2, 6), 0x00400000, 0x007FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032K_CMP0[]= ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x003F0000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x003E0000, 0x003FFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x003C0000, 0x003FFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00380000, 0x003FFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00300000, 0x003FFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00200000, 0x003FFFFF }, // 32-63 ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // 0 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x001FFFFF }, // 00-31 ++ { BITS(6:2, 0x1F), 0x00000000, 0x003FFFFF }, // 0-63 ++ { BITS(6:2, 0x11), 0x003FF000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x003FE000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x003FC000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x003F8000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032K_CMP1[]= ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x01), 0x00000000, 0x003EFFFF }, // 00-62 ++ { BITS(6:2, 0x02), 0x00000000, 0x003DFFFF }, // 00-61 ++ { BITS(6:2, 0x03), 0x00000000, 0x003BFFFF }, // 00-59 ++ { BITS(6:2, 0x04), 0x00000000, 0x0037FFFF }, // 00-55 ++ { BITS(6:2, 0x05), 0x00000000, 0x002FFFFF }, // 00-47 ++ { BITS(6:2, 0x06), 0x00000000, 0x001FFFFF }, // 00-31 ++ { BITS(6:2, 0x09), 0x00010000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x0A), 0x00020000, 0x003FFFFF }, // 02-63 ++ { BITS(6:2, 0x0B), 0x00040000, 0x003FFFFF }, // 04-63 ++ { BITS(6:2, 0x0C), 0x00080000, 0x003FFFFF }, // 08-63 ++ { BITS(6:2, 0x0D), 0x00100000, 0x003FFFFF }, // 16-63 ++ { BITS(6:2, 0x0E), 0x00200000, 0x003FFFFF }, // 32-63 ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x11), 0x00000000, 0x003FEFFF }, // 00-63 ++ { BITS(6:2, 0x12), 0x00000000, 0x003FDFFF }, // 00-63 ++ { BITS(6:2, 0x13), 0x00000000, 0x003FBFFF }, // 00-62 ++ { BITS(6:2, 0x14), 0x00000000, 0x003F7FFF }, // 00-62 ++ { BITS(6:2, 0x19), 0x00001000, 0x003FFFFF }, // 00-63 ++ { BITS(6:2, 0x1A), 0x00002000, 0x003FFFFF }, // 00-63 ++ { BITS(6:2, 0x1B), 0x00004000, 0x00003FFF }, // 00-63 ++ { BITS(6:2, 0x1C), 0x00008000, 0x003FFFFF }, // 00-63 ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q32_CMP0[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x003F0000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x003E0000, 0x003FFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x003C0000, 0x003FFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00380000, 0x003FFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00300000, 0x003FFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00200000, 0x003FFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // 00 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x001FFFFF }, // 00-31 ++ ++ { BITS(6:2, 0x11), 0x003FF000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x003EE000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x003FC000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x003F8000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x15), 0x003F8000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x16), 0x003F8000, 0x003FFFFF }, // 63 ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1D), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, // 00 ++ ++ { BITS(6:2, 0x07), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x0F), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x17), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x1F), 0x00000000, 0x003FFFFF }, // ALL ++ ++ { BITS(6:2, 0x18), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x10), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x08), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q32_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x01), 0x00000000, 0x003EFFFF }, // 00-62 ++ { BITS(6:2, 0x02), 0x00000000, 0x003DFFFF }, // 00-61 ++ { BITS(6:2, 0x03), 0x00000000, 0x003BFFFF }, // 00-59 ++ { BITS(6:2, 0x04), 0x00000000, 0x0037FFFF }, // 00-55 ++ { BITS(6:2, 0x05), 0x00000000, 0x002FFFFF }, // 00-47 ++ { BITS(6:2, 0x06), 0x00000000, 0x001FFFFF }, // 00-31 ++ ++ { BITS(6:2, 0x09), 0x00010000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x0A), 0x00020000, 0x003FFFFF }, // 02-63 ++ { BITS(6:2, 0x0B), 0x00040000, 0x003FFFFF }, // 04-63 ++ { BITS(6:2, 0x0C), 0x00080000, 0x003FFFFF }, // 08-63 ++ { BITS(6:2, 0x0D), 0x00100000, 0x003FFFFF }, // 16-63 ++ { BITS(6:2, 0x0E), 0x00200000, 0x003FFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x003FEFFF }, // 00-62 ++ { BITS(6:2, 0x12), 0x00000000, 0x003FDFFF }, // 00-62 ++ { BITS(6:2, 0x13), 0x00000000, 0x003FBFFF }, // 00-62 ++ { BITS(6:2, 0x14), 0x00000000, 0x003F7FFF }, // 00-62 ++ { BITS(6:2, 0x15), 0x00000000, 0x003F7FFF }, // 00-62 ++ { BITS(6:2, 0x16), 0x00000000, 0x003F7FFF }, // 00-62 ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1A), 0x00002000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1B), 0x00004000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1C), 0x00008000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1D), 0x00008000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1E), 0x00008000, 0x003FFFFF }, // 01-63 ++ ++ { BITS(6:2, 0x07), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x0F), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x17), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ ++ { BITS(6:2, 0x18), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x10), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x08), 0x00000000, 0x003FFFFF }, // ALL ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_NM25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x007E0000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x007C0000, 0x007FFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x00780000, 0x007FFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00700000, 0x007FFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00600000, 0x007FFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00400000, 0x007FFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0001FFFF }, // 00 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0003FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0007FFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x000FFFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x001FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x003FFFFF }, // 00-31 ++ { BITS(6:2, 0x07), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0x11), 0x007FF000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x007FE000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x007FC000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x007F8000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x16), 0x007F8000, 0x007FFFFF }, // 63 ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, // 00 ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_BY25Q64AS_CMP0[] = ++{ ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x007E0000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x007C0000, 0x007FFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x00780000, 0x007FFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00700000, 0x007FFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00600000, 0x007FFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00400000, 0x007FFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0001FFFF }, // 00 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0003FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0007FFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x000FFFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x001FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x003FFFFF }, // 00-31 ++ { BITS(6:2, 0x07), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0x11), 0x007FF000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x007FE000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x007FC000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x007F8000, 0x007FFFFF }, // 63 ++ { BITS(6:2, 0x16), 0x007F8000, 0x007FFFFF }, // 63 ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, // 00 ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_BY25Q64AS_CMP1[] = ++{ ++ { BITS(6:2, 0x00), 0x00000000, 0x007FFFFF }, // 00 ++ { BITS(6:2, 0x01), 0x00000000, 0x007DFFFF }, // ALL ++ { BITS(6:2, 0x02), 0x00000000, 0x007BFFFF }, // ALL ++ { BITS(6:2, 0x03), 0x00000000, 0x0077FFFF }, // ALL ++ { BITS(6:2, 0x04), 0x00000000, 0x006FFFFF }, // ALL ++ { BITS(6:2, 0x05), 0x00000000, 0x005FFFFF }, // ALL ++ { BITS(6:2, 0x06), 0x00000000, 0x003FFFFF }, // ALL ++ ++ { BITS(6:2, 0x09), 0x00020000, 0x007FFFFF }, // NONE ++ { BITS(6:2, 0x0A), 0x00040000, 0x007FFFFF }, // NONE ++ { BITS(6:2, 0x0B), 0x00080000, 0x007FFFFF }, // NONE ++ { BITS(6:2, 0x0C), 0x00100000, 0x007FFFFF }, // NONE ++ { BITS(6:2, 0x0D), 0x00200000, 0x007FFFFF }, // NONE ++ { BITS(6:2, 0x0E), 0x00400000, 0x007FFFFF }, // NONE ++ { BITS(6:2, 0x07), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x007FEFFF }, // ALL ++ { BITS(6:2, 0x12), 0x00000000, 0x007FDFFF }, // ALL ++ { BITS(6:2, 0x13), 0x00000000, 0x007FBFFF }, // ALL ++ { BITS(6:2, 0x14), 0x00000000, 0x007F7FFF }, // ALL ++ { BITS(6:2, 0x16), 0x00000000, 0x007F7FFF }, // ALL ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x007FFFFF }, // ALL ++ { BITS(6:2, 0x1A), 0x00002000, 0x007FFFFF }, // ALL ++ { BITS(6:2, 0x1B), 0x00004000, 0x007FFFFF }, // ALL ++ { BITS(6:2, 0x1C), 0x00008000, 0x007FFFFF }, // ALL ++ { BITS(6:2, 0x1E), 0x00008000, 0x007FFFFF }, // ALL ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_BY25Q128AS_CMP0[] = ++{ ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x00FC0000, 0x00FFFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x00F80000, 0x00FFFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x00F00000, 0x00FFFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00E00000, 0x00FFFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00C00000, 0x00FFFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00800000, 0x00FFFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0003FFFF }, // 00 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0007FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x000FFFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x001FFFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x003FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x007FFFFF }, // 00-31 ++ { BITS(6:2, 0x07), 0x00000000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00FFF000, 0x00FFFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x00FFE000, 0x00FFFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x00FFC000, 0x00FFFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x00FF8000, 0x00FFFFFF }, // 63 ++ { BITS(6:2, 0x16), 0x00FF8000, 0x00FFFFFF }, // 63 ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, // 00 ++ ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_BY25Q128AS_CMP1[] = ++{ ++ { BITS(6:2, 0x00), 0x00000000, 0x00FFFFFF }, // 00 ++ { BITS(6:2, 0x01), 0x00000000, 0x00FBFFFF }, // ALL ++ { BITS(6:2, 0x02), 0x00000000, 0x00F7FFFF }, // ALL ++ { BITS(6:2, 0x03), 0x00000000, 0x00EFFFFF }, // ALL ++ { BITS(6:2, 0x04), 0x00000000, 0x00DFFFFF }, // ALL ++ { BITS(6:2, 0x05), 0x00000000, 0x00BFFFFF }, // ALL ++ { BITS(6:2, 0x06), 0x00000000, 0x007FFFFF }, // ALL ++ ++ { BITS(6:2, 0x09), 0x00040000, 0x00FFFFFF }, // NONE ++ { BITS(6:2, 0x0A), 0x00080000, 0x00FFFFFF }, // NONE ++ { BITS(6:2, 0x0B), 0x00100000, 0x00FFFFFF }, // NONE ++ { BITS(6:2, 0x0C), 0x00200000, 0x00FFFFFF }, // NONE ++ { BITS(6:2, 0x0D), 0x00400000, 0x00FFFFFF }, // NONE ++ { BITS(6:2, 0x0E), 0x00800000, 0x00FFFFFF }, // NONE ++ { BITS(6:2, 0x07), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x00FFEFFF }, // ALL ++ { BITS(6:2, 0x12), 0x00000000, 0x00FFDFFF }, // ALL ++ { BITS(6:2, 0x13), 0x00000000, 0x00FFBFFF }, // ALL ++ { BITS(6:2, 0x14), 0x00000000, 0x00FF7FFF }, // ALL ++ { BITS(6:2, 0x16), 0x00000000, 0x00FF7FFF }, // ALL ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x00FFFFFF }, // ALL ++ { BITS(6:2, 0x1A), 0x00002000, 0x00FFFFFF }, // ALL ++ { BITS(6:2, 0x1B), 0x00004000, 0x00FFFFFF }, // ALL ++ { BITS(6:2, 0x1C), 0x00008000, 0x00FFFFFF }, // ALL ++ { BITS(6:2, 0x1E), 0x00008000, 0x00FFFFFF }, // ALL ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q16_CMP0[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x001F0000, 0x001FFFFF }, // Upper 1/32 ++ { BITS(6:2, 0x02), 0x001E0000, 0x001FFFFF }, // Upper 1/16 ++ { BITS(6:2, 0x03), 0x001C0000, 0x001FFFFF }, // Upper 1/8 ++ { BITS(6:2, 0x04), 0x00180000, 0x001FFFFF }, // Upper 1/4 ++ { BITS(6:2, 0x05), 0x00100000, 0x001FFFFF }, // Upper 1/2 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // Lower 1/32 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // Lower 1/16 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // Lower 1/8 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // Lower 1/4 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // Lower 1/2 ++ { BITS(6:2, 0x0E), 0x00000000, 0x001FFFFF }, // ALL ++ ++ { BITS(6:2, 0x11), 0x001FF000, 0x001FFFFF }, // 4KB Top Block ++ { BITS(6:2, 0x12), 0x001EE000, 0x001FFFFF }, // 8KB Top Block ++ { BITS(6:2, 0x13), 0x001FC000, 0x001FFFFF }, // 16KB Top Block ++ { BITS(6:2, 0x14), 0x001F8000, 0x001FFFFF }, // 32KB Top Block ++ ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 4KB Bottom Block ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 8KB Bottom Block ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 16KB Bottom Block ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 32KB Bottom Block ++ ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q128_CMP0[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0x01), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(6:2, 0x02), 0x00F80000, 0x00FFFFFF }, ++ { BITS(6:2, 0x03), 0x00F00000, 0x00FFFFFF }, ++ { BITS(6:2, 0x04), 0x00E00000, 0x00FFFFFF }, ++ { BITS(6:2, 0x05), 0x00C00000, 0x00FFFFFF }, ++ { BITS(6:2, 0x06), 0x00800000, 0x0000FFFF }, ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 0x0A), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 0x0B), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 0x0C), 0x00000000, 0x001FFFFF }, ++ { BITS(6:2, 0x0D), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0x0E), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0x0F), 0x00000000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00FFF000, 0x00FFFFFF }, ++ { BITS(6:2, 0x12), 0x00FEE000, 0x00FFFFFF }, ++ { BITS(6:2, 0x13), 0x00FFC000, 0x00FFFFFF }, ++ { BITS(6:2, 0x14), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0x16), 0x00FF8000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, ++}; ++ ++#if 0//researved for GD25Q16 flash ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q16_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x001FFFFF }, // 2M ALL ++ { BITS(6:2, 0x01), 0x00000000, 0x001EFFFF }, // 1984KB Lower 31/32 ++ { BITS(6:2, 0x02), 0x00000000, 0x001DFFFF }, // 1920KB Lower 15/16 ++ { BITS(6:2, 0x03), 0x00000000, 0x001BFFFF }, // 1792KB Lower 7/8 ++ { BITS(6:2, 0x04), 0x00000000, 0x0017FFFF }, // 1536KB Lower 3/4 ++ { BITS(6:2, 0x05), 0x00000000, 0x001FFFFF }, // 1M Lower 1/2 ++ ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // 1984KB Upper 31/32 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // 1920KB Upper 15/16 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // 1792KB Upper 7/8 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // 1536KB Upper 3/4 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // 1M Upper 1/2 ++ ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x001FEFFF }, // 2044KB L - 511/512 ++ { BITS(6:2, 0x12), 0x00000000, 0x001FDFFF }, // 2040KB L - 255/256 ++ { BITS(6:2, 0x13), 0x00000000, 0x001FBFFF }, // 2032KB L - 127/128 ++ { BITS(6:2, 0x14), 0x00000000, 0x001F7FFF }, // 2016KB L - 63/64 ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x001FFFFF }, // 2044KB U - 511/512 ++ { BITS(6:2, 0x1A), 0x00002000, 0x001FFFFF }, // 2040KB U - 255/256 ++ { BITS(6:2, 0x1B), 0x00004000, 0x001FFFFF }, // 2032KB U - 127/128 ++ { BITS(6:2, 0x1C), 0x00008000, 0x001FFFFF }, // 2016KB U - 63/64 ++ ++ ++}; ++#endif ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q64CV_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0x01), 0x00000000, 0x007DFFFF }, ++ { BITS(6:2, 0x02), 0x00000000, 0x007BFFFF }, ++ { BITS(6:2, 0x03), 0x00000000, 0x0077FFFF }, ++ { BITS(6:2, 0x04), 0x00000000, 0x006FFFFF }, ++ { BITS(6:2, 0x05), 0x00000000, 0x005FFFFF }, ++ { BITS(6:2, 0x06), 0x00000000, 0x003FFFFF }, ++ ++ { BITS(6:2, 0x09), 0x00020000, 0x007FFFFF }, ++ { BITS(6:2, 0x0A), 0x00040000, 0x007FFFFF }, ++ { BITS(6:2, 0x0B), 0x00080000, 0x007FFFFF }, ++ { BITS(6:2, 0x0C), 0x00100000, 0x007FFFFF }, ++ { BITS(6:2, 0x0D), 0x00200000, 0x007FFFFF }, ++ { BITS(6:2, 0x0E), 0x00400000, 0x007FFFFF }, ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x007FEFFF }, ++ { BITS(6:2, 0x12), 0x00000000, 0x007FDFFF }, ++ { BITS(6:2, 0x13), 0x00000000, 0x007FBFFF }, ++ { BITS(6:2, 0x14), 0x00000000, 0x007F7FFF }, ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x007FFFFF }, ++ { BITS(6:2, 0x1A), 0x00002000, 0x007FFFFF }, ++ { BITS(6:2, 0x1B), 0x00004000, 0x007FFFFF }, ++ { BITS(6:2, 0x1C), 0x00008000, 0x007FFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q32BV_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0x01), 0x00000000, 0x003EFFFF }, ++ { BITS(6:2, 0x02), 0x00000000, 0x003DFFFF }, ++ { BITS(6:2, 0x03), 0x00000000, 0x003BFFFF }, ++ { BITS(6:2, 0x04), 0x00000000, 0x0037FFFF }, ++ { BITS(6:2, 0x05), 0x00000000, 0x002FFFFF }, ++ { BITS(6:2, 0x06), 0x00000000, 0x001FFFFF }, ++ ++ { BITS(6:2, 0x09), 0x00010000, 0x003FFFFF }, ++ { BITS(6:2, 0x0A), 0x00020000, 0x003FFFFF }, ++ { BITS(6:2, 0x0B), 0x00040000, 0x003FFFFF }, ++ { BITS(6:2, 0x0C), 0x00080000, 0x003FFFFF }, ++ { BITS(6:2, 0x0D), 0x00100000, 0x003FFFFF }, ++ { BITS(6:2, 0x0E), 0x00200000, 0x003FFFFF }, ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x003FEFFF }, ++ { BITS(6:2, 0x12), 0x00000000, 0x003FDFFF }, ++ { BITS(6:2, 0x13), 0x00000000, 0x003FBFFF }, ++ { BITS(6:2, 0x14), 0x00000000, 0x003F7FFF }, ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x003FFFFF }, ++ { BITS(6:2, 0x1A), 0x00002000, 0x003FFFFF }, ++ { BITS(6:2, 0x1B), 0x00004000, 0x003FFFFF }, ++ { BITS(6:2, 0x1C), 0x00008000, 0x003FFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x007E0000, 0x007FFFFF }, ++ { BITS(5:2, 2), 0x007C0000, 0x007FFFFF }, ++ { BITS(5:2, 3), 0x00780000, 0x007FFFFF }, ++ { BITS(5:2, 4), 0x00700000, 0x007FFFFF }, ++ { BITS(5:2, 5), 0x00600000, 0x007FFFFF }, ++ { BITS(5:2, 6), 0x00400000, 0x007FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_XM25QH128A[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0X00), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X01), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(6:2, 0X02), 0x00F80000, 0x00FFFFFF }, ++ { BITS(6:2, 0X03), 0x00F00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X04), 0x00E00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X05), 0x00C00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X06), 0x00800000, 0x00FFFFFF }, ++ { BITS(6:2, 0X07), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X08), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X09), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 0X0A), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 0X0B), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 0X0C), 0x00000000, 0x001FFFFF }, ++ { BITS(6:2, 0X0D), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0X0E), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0X0F), 0x00000000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0X10), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X11), 0x00000000, 0x00FBFFFF }, ++ { BITS(6:2, 0X12), 0x00000000, 0x00F7FFFF }, ++ { BITS(6:2, 0X13), 0x00000000, 0x00EFFFFF }, ++ { BITS(6:2, 0X14), 0x00000000, 0x00DFFFFF }, ++ { BITS(6:2, 0X15), 0x00000000, 0x00BFFFFF }, ++ { BITS(6:2, 0X16), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0X17), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X18), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X19), 0x00040000, 0x00FFFFFF }, ++ { BITS(6:2, 0X1A), 0x00080000, 0x00FFFFFF }, ++ { BITS(6:2, 0X1B), 0x00100000, 0x00FFFFFF }, ++ { BITS(6:2, 0X1C), 0x00200000, 0x00FFFFFF }, ++ { BITS(6:2, 0X1D), 0x00400000, 0x00FFFFFF }, ++ { BITS(6:2, 0X1E), 0x00800000, 0x00FFFFFF }, ++ { BITS(6:2, 0X1F), 0x00000000, 0x00FFFFFF }, ++ ++}; ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_XM25QH64A[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0X00), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X01), 0x007F0000, 0x007FFFFF }, ++ { BITS(6:2, 0X02), 0x007E0000, 0x007FFFFF }, ++ { BITS(6:2, 0X03), 0x007C0000, 0x007FFFFF }, ++ { BITS(6:2, 0X04), 0x00780000, 0x007FFFFF }, ++ { BITS(6:2, 0X05), 0x00700000, 0x007FFFFF }, ++ { BITS(6:2, 0X06), 0x00600000, 0x007FFFFF }, ++ { BITS(6:2, 0X07), 0x00400000, 0x007FFFFF }, ++ { BITS(6:2, 0X08), 0x00200000, 0x007FFFFF }, ++ { BITS(6:2, 0X09), 0x00100000, 0x007FFFFF }, ++ { BITS(6:2, 0X0A), 0x00080000, 0x007FFFFF }, ++ { BITS(6:2, 0X0B), 0x00040000, 0x007FFFFF }, ++ { BITS(6:2, 0X0C), 0x00020000, 0x007FFFFF }, ++ { BITS(6:2, 0X0D), 0x00010000, 0x007FFFFF }, ++ { BITS(6:2, 0X0E), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0X0F), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X10), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X11), 0x00000000, 0x0000FFFF }, ++ { BITS(6:2, 0X12), 0x00000000, 0x0001FFFF }, ++ { BITS(6:2, 0X13), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 0X14), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 0X15), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 0X16), 0x00000000, 0x001FFFFF }, ++ { BITS(6:2, 0X17), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0X18), 0x00000000, 0x005FFFFF }, ++ { BITS(6:2, 0X19), 0x00000000, 0x006FFFFF }, ++ { BITS(6:2, 0X1A), 0x00000000, 0x0077FFFF }, ++ { BITS(6:2, 0X1B), 0x00000000, 0x007BFFFF }, ++ { BITS(6:2, 0X1C), 0x00000000, 0x007DFFFF }, ++ { BITS(6:2, 0X1D), 0x00000000, 0x007EFFFF }, ++ { BITS(6:2, 0X1E), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0X1F), 0x00000000, 0x007FFFFF }, ++ ++}; ++ ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00000000, 0x001EFFFF },//1, 31 ++ { BITS(5:2, 2), 0x00000000, 0x001DFFFF },//2, 30~31 ++ { BITS(5:2, 3), 0x00000000, 0x001BFFFF },//3, 28~31 ++ { BITS(5:2, 4), 0x00000000, 0x0017FFFF },//4, 24~31 ++ { BITS(5:2, 5), 0x00000000, 0x000FFFFF },//5, 16~31 ++ { BITS(5:2, 6), 0x00000000, 0x001FFFFF },//6, all ++ { BITS(5:2, 7), 0x00000000, 0x001FFFFF },//7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF },//8, 31 ++ { BITS(5:2, 9), 0x001FFFFF, 0x00010000 },//9, 30~31 ++ { BITS(5:2, 10), 0x001FFFFF, 0x00020000 },//10, 28~31 ++ { BITS(5:2, 11), 0x001FFFFF, 0x00040000 },//11, 24~31 ++ { BITS(5:2, 12), 0x001FFFFF, 0x00080000 },//12, 16~31 ++ { BITS(5:2, 13), 0x001FFFFF, 0x00100000 },//13, all ++ { BITS(5:2, 14), 0x001FFFFF, 0x00000000 },//14, all ++ { BITS(5:2, 15), 0x001FFFFF, 0x00000000 },//15, all ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, none ++}; ++ ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_XTX_XT25F64B[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0X00), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X01), 0x00000000, 0x007DFFFF }, ++ { BITS(6:2, 0X02), 0x00000000, 0x007BFFFF }, ++ { BITS(6:2, 0X03), 0x00000000, 0x0077FFFF }, ++ { BITS(6:2, 0X04), 0x00000000, 0x006FFFFF }, ++ { BITS(6:2, 0X05), 0x00000000, 0x005FFFFF }, ++ { BITS(6:2, 0X06), 0x00000000, 0x004FFFFF }, ++ ++ { BITS(6:2, 0X07), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X08), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X09), 0x00020000, 0x007FFFFF }, ++ { BITS(6:2, 0X0A), 0x00040000, 0x007FFFFF }, ++ { BITS(6:2, 0X0B), 0x00080000, 0x007FFFFF }, ++ { BITS(6:2, 0X0C), 0x00100000, 0x007FFFFF }, ++ { BITS(6:2, 0X0D), 0x00200000, 0x007FFFFF }, ++ { BITS(6:2, 0X0E), 0x00400000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X0F), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X10), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X11), 0x00000000, 0x007FEFFF }, ++ { BITS(6:2, 0X12), 0x00000000, 0x007FDFFF }, ++ { BITS(6:2, 0X13), 0x00000000, 0x007FBFFF }, ++ { BITS(6:2, 0X14), 0x00000000, 0x007F7FFF }, ++ { BITS(6:2, 0X15), 0x00000000, 0x007F7FFF }, ++ { BITS(6:2, 0X16), 0x00000000, 0x007F7FFF }, ++ ++ { BITS(6:2, 0X17), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X18), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X19), 0x00001000, 0x007FFFFF }, ++ { BITS(6:2, 0X1A), 0x00002000, 0x007FFFFF }, ++ { BITS(6:2, 0X1B), 0x00004000, 0x007FFFFF }, ++ { BITS(6:2, 0X1C), 0x00008000, 0x007FFFFF }, ++ { BITS(6:2, 0X1D), 0x00008000, 0x007FFFFF }, ++ { BITS(6:2, 0X1E), 0x00008000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X1F), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_XTX_XT25F128B[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0X00), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0X01), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(6:2, 0X02), 0x00F80000, 0x00FFFFFF }, ++ { BITS(6:2, 0X03), 0x00F00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X04), 0x00E00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X05), 0x00C00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X06), 0x00800000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0X07), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X08), 0x00FFFFFF, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0X09), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 0X0A), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 0X0B), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 0X0C), 0x00000000, 0x001FFFFF }, ++ { BITS(6:2, 0X0D), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0X0E), 0x00000000, 0x007FFFFF }, ++ ++ { BITS(6:2, 0X0F), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X10), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0X11), 0x00FFF000, 0x00FFFFFF }, ++ { BITS(6:2, 0X12), 0x00FFE000, 0x00FFFFFF }, ++ { BITS(6:2, 0X13), 0x00FFC000, 0x00FFFFFF }, ++ { BITS(6:2, 0X14), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0X15), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0X16), 0x00FF8000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0X17), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X18), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0X19), 0x00000000, 0x00000FFF }, ++ { BITS(6:2, 0X1A), 0x00000000, 0x00001FFF }, ++ { BITS(6:2, 0X1B), 0x00000000, 0x00003FFF }, ++ { BITS(6:2, 0X1C), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0X1D), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0X1E), 0x00000000, 0x00007FFF }, ++ ++ { BITS(6:2, 0X1F), 0x00000000, 0x00FFFFFF }, ++}; ++ ++ ++#define FROM_BLK(x, blk_size) ((x) * (blk_size)) ++#define TO_BLK(x, blk_size) (((x) + 1) * (blk_size) - 1) ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_IS25LP064D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(127, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 2), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 3), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 4), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 5), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 6), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 7), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 8), FROM_BLK(32, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 9), FROM_BLK(16, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 10), FROM_BLK(8, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 12), FROM_BLK(2, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 13), FROM_BLK(1, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q128A[] = ++ // BPX, Lower Bound Upper Bound ++{ ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 1), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 2), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 3), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 4), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 5), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 6), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X40[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 1), FROM_BLK(7, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 2), FROM_BLK(6, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 3), FROM_BLK(4, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, ++ { BITS(5:2,10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, ++ { BITS(5:2,11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, ++ { BITS(5:2,15), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L8005[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 7), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 7, 00~15 ++ { BITS(4:2, 6), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 6, 00~15 ++ { BITS(4:2, 5), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 5, 00~15 ++ { BITS(4:2, 4), FROM_BLK( 8, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 4, 08~15 ++ { BITS(4:2, 3), FROM_BLK( 12, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 3, 12~15 ++ { BITS(4:2, 2), FROM_BLK( 14, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 2, 14~15 ++ { BITS(4:2, 1), FROM_BLK( 15, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 1, 15~15 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L3205D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 0~62 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 0~61 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 0~59 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 0~55 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 0~47 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L3206E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 0~62 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 0~61 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 0~59 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 0~55 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 0~47 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_SST25VF032B[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(2:0, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(2:0, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(2:0, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(2:0, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(2:0, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(2:0, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(2:0, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 00~63 ++ { BITS(2:0, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6405D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(125, SIZE_64KB) }, // 0~125 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(123, SIZE_64KB) }, // 0~123 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(119, SIZE_64KB) }, // 0~119 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(111, SIZE_64KB) }, // 0~111 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(95, SIZE_64KB) }, // 0~95 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 64~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 96~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 126~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 0~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L1606E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(31, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 31~31 ++ { BITS(5:2, 2), FROM_BLK(30, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 30~31 ++ { BITS(5:2, 3), FROM_BLK(28, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 28~31 ++ { BITS(5:2, 4), FROM_BLK(24, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 24~31 ++ { BITS(5:2, 5), FROM_BLK(16, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 16~31 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 0~15 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(23, SIZE_64KB) }, // 0~23 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(27, SIZE_64KB) }, // 0~27 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(29, SIZE_64KB) }, // 0~29 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(30, SIZE_64KB) }, // 0~30 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6406E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(125, SIZE_64KB) }, // 0~125 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(123, SIZE_64KB) }, // 0~123 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(119, SIZE_64KB) }, // 0~119 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(111, SIZE_64KB) }, // 0~111 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(95, SIZE_64KB) }, // 0~95 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 64~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 96~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 126~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 0~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++// New MXIC Flash with the same RDID as MX25L6405D ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 064~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 096~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 126~127 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6455E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 14, 0~127 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 13, 0~127 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 12, 0~127 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 11, 0~127 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 10, 0~127 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 9, 0~127 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 8, 0~127 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, 0~127 ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 6, 64~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 5, 96~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 4, 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 3, 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 2, 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 1, 126~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 15, 0~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L4006E[] = ++{ ++ //BPX, Lower Bound Upper Bound ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(4:2, 1), FROM_BLK(7, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 1, 7 ++ { BITS(4:2, 2), FROM_BLK(6, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 2, 6-7 ++ { BITS(4:2, 3), FROM_BLK(4, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 3, 4-7 ++ { BITS(4:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(4:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q32A[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 00~62 ++ { BITS(5:2, 2), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 00~61 ++ { BITS(5:2, 3), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 00~59 ++ { BITS(5:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 00~55 ++ { BITS(5:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 00~47 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 00~31 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 00~63 ++ { BITS(5:2, 9), FROM_BLK(1, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 01~63 ++ { BITS(5:2, 10), FROM_BLK(2, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 02~63 ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 04~63 ++ { BITS(5:2, 12), FROM_BLK(8, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 08~63 ++ { BITS(5:2, 13), FROM_BLK(16, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 16~63 ++ { BITS(5:2, 14), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 00~63 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(0, SIZE_64KB), TO_BLK(126, SIZE_64KB) }, // 00~126 ++ { BITS(5:2, 2), FROM_BLK(0, SIZE_64KB), TO_BLK(125, SIZE_64KB) }, // 00~125 ++ { BITS(5:2, 3), FROM_BLK(0, SIZE_64KB), TO_BLK(123, SIZE_64KB) }, // 00~123 ++ { BITS(5:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(119, SIZE_64KB) }, // 00~119 ++ { BITS(5:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(111, SIZE_64KB) }, // 00~111 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(95, SIZE_64KB) }, // 00~95 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 9), FROM_BLK(1, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 10), FROM_BLK(2, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 12), FROM_BLK(8, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 13), FROM_BLK(16, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 14), FROM_BLK(32, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_M25PX16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(31, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 2), FROM_BLK(30, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 3), FROM_BLK(28, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 4), FROM_BLK(24, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 5), FROM_BLK(16, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(0, SIZE_64KB), TO_BLK(254, SIZE_64KB) }, // 00~254 ++ { BITS(5:2, 2), FROM_BLK(0, SIZE_64KB), TO_BLK(253, SIZE_64KB) }, // 00~253 ++ { BITS(5:2, 3), FROM_BLK(0, SIZE_64KB), TO_BLK(251, SIZE_64KB) }, // 00~251 ++ { BITS(5:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(247, SIZE_64KB) }, // 00~247 ++ { BITS(5:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(239, SIZE_64KB) }, // 00~239 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(223, SIZE_64KB) }, // 00~223 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 00~255 ++ { BITS(5:2, 9), FROM_BLK(1, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 01~255 ++ { BITS(5:2, 10), FROM_BLK(2, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 02~255 ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 04~255 ++ { BITS(5:2, 12), FROM_BLK(8, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 08~255 ++ { BITS(5:2, 13), FROM_BLK(16, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 16~255 ++ { BITS(5:2, 14), FROM_BLK(32, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 32~255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 00~255 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++/* ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F32[] = ++{ ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++*/ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12805D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 8), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 128~255 ++ { BITS(5:2, 7), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 192~255 ++ { BITS(5:2, 6), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 224~255 ++ { BITS(5:2, 5), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 240~255 ++ { BITS(5:2, 4), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 248~255 ++ { BITS(5:2, 3), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 252~255 ++ { BITS(5:2, 2), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 254~255 ++ { BITS(5:2, 1), FROM_BLK(255, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 0~255 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F40[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(4:2, 1), FROM_BLK(7, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 1, 7 ++ { BITS(4:2, 2), FROM_BLK(6, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 2, 6-7 ++ { BITS(4:2, 3), FROM_BLK(4, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 3, 4-7 ++ { BITS(4:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(4:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++}; ++ ++// New MXIC Flash with the same RDID as MX25L12805D ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 14, 0~255 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 13, 0~255 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 12, 0~255 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 11, 0~255 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 10, 0~255 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 9, 0~255 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 8, 0~255 ++ { BITS(5:2, 7), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 7, 128~255 ++ { BITS(5:2, 6), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 6, 192~255 ++ { BITS(5:2, 5), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 5, 224~255 ++ { BITS(5:2, 4), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 4, 240~255 ++ { BITS(5:2, 3), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 3, 248~255 ++ { BITS(5:2, 2), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 2, 252~255 ++ { BITS(5:2, 1), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 1, 254~255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 15, 0~255 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++// NOTE: AT26DF321 could protect each sector independently and BITS(5:2, 1)~BITS(5:2, 14) is no change for protection. ++// This table is just used to figure out the lower bound and upper bound (no such param in function argument). ++ST_WRITE_PROTECT _pstWriteProtectTable_AT26DF321[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 0~62 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 0~61 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 0~59 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 0~55 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 0~47 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_AT25DF321[] = ++{ ++ { BITS(5:2, 0), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL128P[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 7), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 7, 128~255 ++ { BITS(5:2, 6), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 6, 192~255 ++ { BITS(5:2, 5), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 5, 224~255 ++ { BITS(5:2, 4), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 4, 240~255 ++ { BITS(5:2, 3), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 3, 248~255 ++ { BITS(5:2, 2), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 2, 252~255 ++ { BITS(5:2, 1), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 1, 254~255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 15, 0~255 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL008A[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 7), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 7, 00~15 ++ { BITS(5:2, 6), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 6, 00~15 ++ { BITS(5:2, 5), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 5, 00~15 ++ { BITS(5:2, 4), FROM_BLK( 8, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 4, 08~15 ++ { BITS(5:2, 3), FROM_BLK( 12, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 3, 12~15 ++ { BITS(5:2, 2), FROM_BLK( 14, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 2, 14~15 ++ { BITS(5:2, 1), FROM_BLK( 15, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 1, 15~15 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25P16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 1), 0x001F0000, 0x001FFFFF },//1, 31 ++ { BITS(4:2, 2), 0x001E0000, 0x001FFFFF },//2, 30~31 ++ { BITS(4:2, 3), 0x001C0000, 0x001FFFFF },//3, 28~31 ++ { BITS(4:2, 4), 0x00180000, 0x001FFFFF },//4, 24~31 ++ { BITS(4:2, 5), 0x00100000, 0x001FFFFF },//5, 16~31 ++ { BITS(4:2, 6), 0x00000000, 0x001FFFFF },//6, all ++ { BITS(4:2, 7), 0x00000000, 0x001FFFFF },//7, all ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 1), 0x001F0000, 0x001FFFFF },//1, 31 ++ { BITS(4:2, 2), 0x001E0000, 0x001FFFFF },//2, 30~31 ++ { BITS(4:2, 3), 0x001C0000, 0x001FFFFF },//3, 28~31 ++ { BITS(4:2, 4), 0x00180000, 0x001FFFFF },//4, 24~31 ++ { BITS(4:2, 5), 0x00100000, 0x001FFFFF },//5, 16~31 ++ { BITS(4:2, 6), 0x00000000, 0x001FFFFF },//6, all ++ { BITS(4:2, 7), 0x00000000, 0x001FFFFF },//7, all ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F32[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00000000, 0x003EFFFF },//0~62 ++ { BITS(5:2, 2), 0x00000000, 0x003DFFFF },//0~61 ++ { BITS(5:2, 3), 0x00000000, 0x003BFFFF },//0~59 ++ { BITS(5:2, 4), 0x00000000, 0x0037FFFF },//0~55 ++ { BITS(5:2, 5), 0x00000000, 0x002FFFFF },//0~47 ++ { BITS(5:2, 6), 0x00000000, 0x001FFFFF },//0~31 ++ { BITS(5:2, 7), 0x00000000, 0x003FFFFF },//all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF },//none ++ { BITS(5:2, 9), 0x003FFFFF, 0x00010000 },//63~1 ++ { BITS(5:2, 10), 0x003FFFFF, 0x00020000 },//63~2 ++ { BITS(5:2, 11), 0x003FFFFF, 0x00040000 },//63~4 ++ { BITS(5:2, 12), 0x003FFFFF, 0x00080000 },//63~8 ++ { BITS(5:2, 13), 0x003FFFFF, 0x00100000 },//63~16 ++ { BITS(5:2, 14), 0x003FFFFF, 0x00200000 },//63~32 ++ { BITS(5:2, 15), 0x00000000, 0x003FFFFF },//all ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//none ++ ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q80[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 1), 0x000F0000, 0x000FFFFF }, ++ { BITS(6:2, 2), 0x000E0000, 0x000FFFFF }, ++ { BITS(6:2, 3), 0x000C0000, 0x000FFFFF }, ++ { BITS(6:2, 4), 0x00080000, 0x000FFFFF }, ++ { BITS(6:2, 9), 0x00000000, 0x0000FFFF }, ++ { BITS(6:2, 10), 0x00000000, 0x0001FFFF }, ++ { BITS(6:2, 11), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 12), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 15), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 17), 0x000FF000, 0x000FFFFF }, ++ { BITS(6:2, 18), 0x000FE000, 0x000FFFFF }, ++ { BITS(6:2, 19), 0x000FC000, 0x000FFFFF }, ++ { BITS(6:2, 20), 0x000F8000, 0x000FFFFF }, ++ { BITS(6:2, 25), 0x00000000, 0x00000FFF }, ++ { BITS(6:2, 26), 0x00000000, 0x00001FFF }, ++ { BITS(6:2, 27), 0x00000000, 0x00003FFF }, ++ { BITS(6:2, 28), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X80[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x000F0000, 0x000FFFFF }, ++ { BITS(5:2, 2), 0x000E0000, 0x000FFFFF }, ++ { BITS(5:2, 3), 0x000C0000, 0x000FFFFF }, ++ { BITS(5:2, 4), 0x00080000, 0x000FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0000FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F80[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 1), 0x000F0000, 0x000FFFFF },//1, 15 ++ { BITS(4:2, 2), 0x000E0000, 0x000FFFFF },//2, 14~15 ++ { BITS(4:2, 3), 0x000C0000, 0x000FFFFF },//3, 12~15 ++ { BITS(4:2, 4), 0x00080000, 0x000FFFFF },//4, 8~15 ++ { BITS(4:2, 5), 0x00000000, 0x000FFFFF },//5, all ++ { BITS(4:2, 6), 0x00000000, 0x000FFFFF },//6, all ++ { BITS(4:2, 7), 0x00000000, 0x000FFFFF },//7, all ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, NONE ++ ++}; ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_ZB25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x007F0000, 0x007FFFFF }, ++ { BITS(5:2, 2), 0x007E0000, 0x007FFFFF }, ++ { BITS(5:2, 3), 0x007C0000, 0x007FFFFF }, ++ { BITS(5:2, 4), 0x00780000, 0x007FFFFF }, ++ { BITS(5:2, 5), 0x00700000, 0x007FFFFF }, ++ { BITS(5:2, 6), 0x00600000, 0x007FFFFF }, ++ { BITS(5:2, 7), 0x00400000, 0x007FFFFF }, ++ { BITS(5:2, 8), 0x00200000, 0x007FFFFF }, ++ { BITS(5:2, 9), 0x00100000, 0x007FFFFF }, ++ { BITS(5:2, 10), 0x00080000, 0x007FFFFF }, ++ { BITS(5:2, 11), 0x00040000, 0x007FFFFF }, ++ { BITS(5:2, 12), 0x00020000, 0x007FFFFF }, ++ { BITS(5:2, 13), 0x00010000, 0x007FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++#if 0 ++static ST_WRITE_PROTECT _pstWriteProtectTable_ZB25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(5:2, 2), 0x00F80000, 0x00FFFFFF }, ++ { BITS(5:2, 3), 0x00F00000, 0x00FFFFFF }, ++ { BITS(5:2, 4), 0x00E00000, 0x00FFFFFF }, ++ { BITS(5:2, 5), 0x00C00000, 0x00FFFFFF }, ++ { BITS(5:2, 6), 0x00800000, 0x00FFFFFF }, ++ { BITS(5:2, 7), 0x00000000, 0x00FFFFFF }, ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x00FFFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++#endif ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_ZB25VQ128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(5:2, 2), 0x00F80000, 0x00FFFFFF }, ++ { BITS(5:2, 3), 0x00F00000, 0x00FFFFFF }, ++ { BITS(5:2, 4), 0x00E00000, 0x00FFFFFF }, ++ { BITS(5:2, 5), 0x00C00000, 0x00FFFFFF }, ++ { BITS(5:2, 6), 0x00800000, 0x00FFFFFF }, ++// 0~127 ++ { BITS(5:2, 9), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x007FFFFF }, ++// 255 ++ { BITS(5:2, 17), 0x00FFF000, 0x00FFFFFF }, ++ { BITS(5:2, 18), 0x00FFE000, 0x00FFFFFF }, ++ { BITS(5:2, 19), 0x00FFC000, 0x00FFFFFF }, ++ { BITS(5:2, 20), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(5:2, 21), 0x00FF8000, 0x00FFFFFF }, ++// 0 ++ { BITS(5:2, 25), 0x00000000, 0x00000FFF }, ++ { BITS(5:2, 26), 0x00000000, 0x00001FFF }, ++ { BITS(5:2, 27), 0x00000000, 0x00003FFF }, ++ { BITS(5:2, 28), 0x00000000, 0x00007FFF }, ++ { BITS(5:2, 29), 0x00000000, 0x00007FFF }, ++// NONE ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_PM25LQ032C[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 0~15 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 0~7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 0~3 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 0~1 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 0~0 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_M25P16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(4:2, 1), FROM_BLK(31, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 1, 7 ++ { BITS(4:2, 2), FROM_BLK(30, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 2, 6-7 ++ { BITS(4:2, 3), FROM_BLK(28, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 3, 4-7 ++ { BITS(4:2, 4), FROM_BLK(24, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 4, all ++ { BITS(4:2, 5), FROM_BLK(16, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_N25Q32[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_N25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(127, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 2), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 3), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 4), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 5), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 6), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 7), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_N25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 1), FROM_BLK(255, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 2), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 3), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 4), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 5), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 6), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 7), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 8), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 9), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 10), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 11), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 12), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 13), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 14), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 15), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 1, 126~127 ++ { BITS(4:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 2, 124~127 ++ { BITS(4:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 3, 120~127 ++ { BITS(4:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 4, 112~127 ++ { BITS(4:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 5, 096~127 ++ { BITS(4:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 6, 064~127 ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, 000~127 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL064[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 6), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 1, 126~127 ++ { BITS(4:2, 5), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 2, 124~127 ++ { BITS(4:2, 4), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 3, 120~127 ++ { BITS(4:2, 3), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 4, 112~127 ++ { BITS(4:2, 2), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 5, 096~127 ++ { BITS(4:2, 1), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 6, 064~127 ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, 000~127 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_XM25QH128C[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0X00), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X01), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(6:2, 0X02), 0x00F80000, 0x00FFFFFF }, ++ { BITS(6:2, 0X03), 0x00F00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X04), 0x00E00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X05), 0x00C00000, 0x00FFFFFF }, ++ { BITS(6:2, 0X06), 0x00800000, 0x00FFFFFF }, ++ { BITS(6:2, 0X07), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X08), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X09), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 0X0A), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 0X0B), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 0X0C), 0x00000000, 0x001FFFFF }, ++ { BITS(6:2, 0X0D), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0X0E), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0X0F), 0x00000000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0X10), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X11), 0x00FFF000, 0x00FFFFFF }, ++ { BITS(6:2, 0X12), 0x00FFE000, 0x00FFFFFF }, ++ { BITS(6:2, 0X13), 0x00FFC000, 0x00FFFFFF }, ++ { BITS(6:2, 0X14), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0X15), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0X16), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0X17), 0x00000000, 0x00FFFFFF }, ++ { BITS(6:2, 0X18), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0X19), 0x00000000, 0x00000FFF }, ++ { BITS(6:2, 0X1A), 0x00000000, 0x00001FFF }, ++ { BITS(6:2, 0X1B), 0x00000000, 0x00003FFF }, ++ { BITS(6:2, 0X1C), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0X1D), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0X1E), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0X1F), 0x00000000, 0x00FFFFFF }, ++}; ++ ++// ++// Flash Info Table (List) ++// ++hal_SERFLASH_t _hal_SERFLASH_table[] = // Need to Add more sample for robust ++{ ++ /**********************************************************************/ ++ /* 01. u16FlashType */ ++ /* 02. u8MID */ ++ /* 03. u8DID0 */ ++ /* 04. u8DID1 */ ++ /* 05. pWriteProtectTable */ ++ /* 06. pSpecialBlocks */ ++ /* 07. u32FlashSize */ ++ /* 08. u32NumBLK */ ++ /* 09. u32BlockSize */ ++ /* 10. u16PageSize */ ++ /* 11. u16MaxChipWrDoneTimeout */ ++ /* 12. u8WrsrBlkProtect */ ++ /* 13. u16DevSel */ ++ /* 14. u16SpiEndianSel */ ++ /* 15. Support 2XREAD(SPI CMD is 0xBB) */ ++ /**********************************************************************/ ++ { FLASH_IC_UNKNOWN, 0xFF, 0xFF, 0xFF, NULL, NULL, 0x1000000, 64, SIZE_64KB, 256, 50, BITS(2:0, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, FALSE}, ++ { FLASH_IC_SST25VF032B, MID_SST, 0x25, 0x4A, _pstWriteProtectTable_SST25VF032B, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(2:0, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L1655D, MID_MXIC, 0x26, 0x15, NULL, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_MX25L3255D, MID_MXIC, 0x9E, 0x16, NULL, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_MX25L6455E, MID_MXIC, 0x26, 0x17, _pstWriteProtectTable_MX25L6455E, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MX25L12855E, MID_MXIC, 0x26, 0x18, _pstWriteProtectTable_MX25L12845E, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MX25L3205D, MID_MXIC, 0x20, 0x16, _pstWriteProtectTable_MX25L3205D, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L4006E, MID_MXIC, 0x20, 0x13, _pstWriteProtectTable_MX25L4006E, NULL, 0x80000, 8, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L6405D, MID_MXIC, 0x20, 0x17, _pstWriteProtectTable_MX25L6405D, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L1606E, MID_MXIC, 0x20, 0x15, _pstWriteProtectTable_MX25L1606E, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_MX25L12805D, MID_MXIC, 0x20, 0x18, _pstWriteProtectTable_MX25L12805D, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_MX25L3206E, MID_MXIC, 0x20, 0x15, _pstWriteProtectTable_MX25L3206E, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE }, ++ { FLASH_IC_MX25L8005, MID_MXIC, 0x20, 0x14, _pstWriteProtectTable_MX25L8005, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L8006E, MID_MXIC, 0x20, 0x14, NULL, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE,TRUE }, ++ { FLASH_IC_MX25L6406E, MID_MXIC, 0x20, 0x17, _pstWriteProtectTable_MX25L6406E, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE , TRUE}, ++ { FLASH_IC_MX25L25645G, MID_MXIC, 0x20, 0x19, NULL, NULL, 0x2000000, 512, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_MX25L5123G, MID_MXIC, 0x20, 0x1A, NULL, NULL, 0x4000000, 1024, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE}, ++ { FLASH_IC_W25Q16, MID_WB, 0x40, 0x15, NULL, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_W25Q80, MID_WB, 0x40, 0x14, _pstWriteProtectTable_W25Q80, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25X32, MID_WB, 0x30, 0x16, _pstWriteProtectTable_W25X32, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_W25X40, MID_WB, 0x30, 0x13, _pstWriteProtectTable_W25X40, NULL, 0x80000, 8, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, FALSE, TRUE}, ++ { FLASH_IC_W25Q32, MID_WB, 0x40, 0x16, _pstWriteProtectTable_W25X32, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25X64, MID_WB, 0x30, 0x17, _pstWriteProtectTable_W25X64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_W25X80, MID_WB, 0x30, 0x14, _pstWriteProtectTable_W25X80, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE }, ++ { FLASH_IC_W25Q64, MID_WB, 0x40, 0x17, _pstWriteProtectTable_W25X64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25Q128, MID_WB, 0x40, 0x18, _pstWriteProtectTable_W25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25Q256JV, MID_WB, 0x40, 0x19, /*_pstWriteProtectTable_W25Q256*/NULL, NULL, 0x2000000, 512, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_AT25DF321A, MID_ATMEL, 0x47, 0x01, _pstWriteProtectTable_AT25DF321, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE }, ++ { FLASH_IC_AT26DF321, MID_ATMEL, 0x47, 0x00, _pstWriteProtectTable_AT26DF321, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_STM25P32, MID_ST, 0x20, 0x16, NULL, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25B32B, MID_EON, 0x20, 0x16, NULL, &_stSpecialBlocks_EN25B32B, 0x400000, 68, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25B64B, MID_EON, 0x20, 0x17, NULL, &_stSpecialBlocks_EN25B64B, 0x800000, 132, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25Q32A, MID_EON, 0x30, 0x16, _pstWriteProtectTable_EN25Q32A, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_EN25Q64, MID_EON, 0x30, 0x17, _pstWriteProtectTable_EN25Q64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25Q128, MID_EON, 0x30, 0x18, _pstWriteProtectTable_EN25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_EN25F10, MID_EON, 0x31, 0x11, NULL, &_stSpecialBlocks_EN25F10, 0x20000, 4, SIZE_32KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F16, MID_EON, 0x31, 0x15, _pstWriteProtectTable_EN25F16, NULL, 0x200000, 32, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F32, MID_EON, 0x31, 0x16, _pstWriteProtectTable_EN25F32, NULL, 0x400000, 64, SIZE_64KB, 256, 384, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F40, MID_EON, 0x31, 0x13, _pstWriteProtectTable_EN25F40, NULL, 0x80000, 8, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F80, MID_EON, 0x31, 0x14, _pstWriteProtectTable_EN25F80, NULL, 0x100000, 16, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25P16, MID_EON, 0x20, 0x15, _pstWriteProtectTable_EN25P16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25QH16, MID_EON, 0x70, 0x15, _pstWriteProtectTable_EN25Q16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_EN25Q128A, MID_EON, 0x70, 0x18, _pstWriteProtectTable_EN25Q128A, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_S25FL032P, MID_SPAN, 0x02, 0x15, _pstWriteProtectTable_S25FL032, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(4:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_S25FL064P, MID_SPAN, 0x02, 0x16, _pstWriteProtectTable_S25FL064, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(4:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_S25FL032K, MID_SPAN, 0x40, 0x16, _pstWriteProtectTable_S25FL032K_CMP0, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_S25FL128P, MID_SPAN, 0x20, 0x18, _pstWriteProtectTable_S25FL128P, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_S25FL008A, MID_SPAN, 0x20, 0x13, _pstWriteProtectTable_S25FL008A, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_XTALI, E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_PM25LQ032C, MID_PMC, 0x46, 0x15, _pstWriteProtectTable_PM25LQ032C, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_GD25Q32, MID_GD, 0x40, 0x16, _pstWriteProtectTable_GD25Q32_CMP0, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25Q16, MID_GD, 0x40, 0x15, _pstWriteProtectTable_GD25Q16_CMP0, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25S80, MID_GD, 0x40, 0x14, NULL, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_GD25Q64, MID_GD, 0x40, 0x17, NULL, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25Q128, MID_GD, 0x40, 0x18, _pstWriteProtectTable_GD25Q128_CMP0, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25Q256C, MID_GD, 0x40, 0x19, NULL, NULL, 0x2000000, 512, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MICRON_M25P16, MID_MICRON, 0x20, 0x15, _pstWriteProtectTable_M25P16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MICRON_N25Q32, MID_MICRON, 0xBA, 0x16, _pstWriteProtectTable_N25Q32, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_D_MODE}, TRUE , TRUE}, ++ { FLASH_IC_MICRON_N25Q64, MID_MICRON, 0xBA, 0x17, _pstWriteProtectTable_N25Q64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_D_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MICRON_N25Q128, MID_MICRON, 0xBA, 0x18, _pstWriteProtectTable_N25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_D_MODE}, TRUE, TRUE }, ++ { FLASH_IC_NUMONYX_M25PX16, MID_NUMONYX,0x73, 0x15, _pstWriteProtectTable_M25PX16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE}, ++ { FLASH_IC_A25LM032, MID_AM, 0x30, 0x16, NULL, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++// { FLASH_IC_ST25Q128, MID_ZB, 0x40, 0x18, _pstWriteProtectTable_ZB25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_ZB25Q64 , MID_EON, 0x70, 0x17, _pstWriteProtectTable_ZB25Q64 , NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_ZB25VQ128, MID_ZB, 0x40, 0x18, _pstWriteProtectTable_ZB25VQ128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_QUAD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_25Q128AS, MID_25Q, 0X40, 0X18, NULL, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_SINGLE_MODE}, TRUE, TRUE}, ++{ FLASH_IC_BYT_BY25Q64AS, MID_25Q, 0X40, 0X17, _pstWriteProtectTable_BY25Q64AS_CMP0, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(6:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE, TRUE}, ++ //notsupport { FLASH_IC_BYT_BY25Q128AS, MID_25Q, 0X40, 0X18, _pstWriteProtectTable_BY25Q128AS_CMP0, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH64A, MID_WUHAN, 0X70, 0X17, _pstWriteProtectTable_XM25QH64A, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH128A, MID_WUHAN, 0X70, 0X18, _pstWriteProtectTable_XM25QH128A, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH128B, MID_WUHAN, 0x60, 0x18, NULL, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_NEXTFLASH, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH64B, MID_WUHAN, 0x60, 0x17, NULL, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_NEXTFLASH, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH64C, MID_WUHAN, 0x40, 0x17, NULL, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_NEXTFLASH, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH256C, MID_WUHAN, 0x40, 0x19, NULL, NULL, 0x2000000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_NEXTFLASH, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_XTX_XT25F64B, MID_XTX, 0X40, 0X17, _pstWriteProtectTable_XTX_XT25F64B, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_XTX_XT25F128B, MID_XTX, 0X40, 0X18, _pstWriteProtectTable_XTX_XT25F128B, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_WUHAN_XM25QH128C, MID_WUHAN, 0x40, 0x18, _pstWriteProtectTable_XM25QH128C, NULL, 0x1000000, 256, SIZE_64KB, 256, 133, BITS(6:2, 0x1F), ISP_DEV_NEXTFLASH, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_QUAD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_NM25Q64, MID_NM, 0X22, 0X17, NULL, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_QUAD_MODE }, TRUE, TRUE}, ++ { FLASH_IC_NM25Q128, MID_NM, 0X21, 0X18, NULL, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(6:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_QUAD_MODE }, TRUE, TRUE}, ++ { FLASH_IC_IS25LP064D, MID_IS, 0x60, 0x17, _pstWriteProtectTable_IS25LP064D, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE}, TRUE, TRUE}, ++ { FLASH_IC_PUYA_PY25Q128HA, MID_PY, 0x20, 0x18, NULL, NULL, 0x1000000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE}, TRUE, TRUE} ++}; ++ +diff --git a/drivers/sstar/flash_isp/drvDeviceInfo.h b/drivers/sstar/flash_isp/drvDeviceInfo.h +new file mode 100755 +index 000000000000..de002b0896f9 +--- /dev/null ++++ b/drivers/sstar/flash_isp/drvDeviceInfo.h +@@ -0,0 +1,264 @@ ++/* ++* drvDeviceInfo.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_DEVICE_INFO_H_ ++#define _DRV_DEVICE_INFO_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++#define FLASH_IC_UNKNOWN 0x0000UL ++// SST ++#define FLASH_IC_SST25VF080B 0x0100UL // 1M SST ++#define FLASH_IC_SST25VF016B 0x0101UL // 2M ++#define FLASH_IC_SST25VF032B 0x0102UL // 2M ++ ++#define FLASH_IC_PM25LV080 0x0200UL // 1M PMC ++#define FLASH_IC_PM25LV016 0x0201UL // 2M ++#define FLASH_IC_PM25LQ032C 0x0202UL // 4M ++ ++#define FLASH_IC_ST25P80_A 0x0300UL // 1M ST ++#define FLASH_IC_ST25P16_A 0x0301UL // 2M ++#define FLASH_IC_STM25P32 0x0302UL // 4M ++#define FLASH_IC_ST25Q128 0x0303UL // unknow , history problem , maybe brand typo . ++ ++//ATMEL ++#define FLASH_IC_AT26DF081A 0x0400UL // 1M ATMEL ++#define FLASH_IC_AT26DF161 0x0401UL // 2M ++#define FLASH_IC_AT26DF321 0x0402UL // 4M ++#define FLASH_IC_AT25DF321A 0x0403UL // 4M ++ ++// MXIC ++#define FLASH_IC_MX25L8005 0x0500UL // 1M MXIC ++#define FLASH_IC_MX25L1655D 0x0501UL // 2M for secure option ++#define FLASH_IC_MX25L1606E 0x0502UL // 2M ++#define FLASH_IC_MX25L1605A 0x0503UL // 2M ++#define FLASH_IC_MX25L3206E 0x0504UL // 4M ++#define FLASH_IC_MX25L3205D 0x0505UL // 4M ++#define FLASH_IC_MX25L6405D 0x0506UL // 8M ++#define FLASH_IC_MX25L6406E 0x0507UL // 8M ++#define FLASH_IC_MX25L12805D 0x0508UL // 16M ++#define FLASH_IC_MX25L12845E 0x0509UL // 16M ++#define FLASH_IC_MX25L6445E 0x050AUL // 8M ++#define FLASH_IC_MX25L6455E 0x050BUL // 8M ++#define FLASH_IC_MX25L12855E 0x050CUL // 16M ++#define FLASH_IC_MX25L4006E 0x050DUL // 512K MXIC ++#define FLASH_IC_MX25L8006E 0x050EUL // 1M MXIC ++#define FLASH_IC_MX25L3255D 0x0512UL // 4M for secure option ++#define FLASH_IC_MX25L25645G 0x0513UL // 32M ++#define FLASH_IC_MX25L5123G 0x5014UL //64M / MX25L51245G ++ ++// NX ++#define FLASH_IC_NX25P80 0x0600UL // 1M NX ++#define FLASH_IC_NX25P16 0x0601UL // 2M ++ ++// WINB ++#define FLASH_IC_W25X80 0x0700UL // 1M WINB ++#define FLASH_IC_W25Q80 0x0701UL // 1M ++#define FLASH_IC_W25Q16 0x0702UL // 2M ++#define FLASH_IC_W25X16 0x0703UL // 2M ++#define FLASH_IC_W25X32 0x0704UL // 4M ++#define FLASH_IC_W25Q32 0x0705UL // 4M ++#define FLASH_IC_W25X64 0x0706UL // 8M ++#define FLASH_IC_W25Q64 0x0707UL // 8M ++#define FLASH_IC_W25Q64CV 0x0708UL // 8M ++#define FLASH_IC_W25Q128 0x0709UL // 16M ++#define FLASH_IC_W25Q32BV 0x070AUL // 4M ++#define FLASH_IC_W25X40 0x070BUL // 512K WINB ++#define FLASH_IC_W25Q256JV 0x070CUL // 32M ++ ++//SPANSION ++#define FLASH_IC_S25FL008A 0x0800UL // 1M SPANSION ++#define FLASH_IC_S25FL016A 0x0801UL // 2M ++#define FLASH_IC_S25FL128P 0x0802UL // 16M ++#define FLASH_IC_S25FL032P 0x0803UL // 4M ++#define FLASH_IC_S25FL064P 0x0804UL // 8M ++#define FLASH_IC_S25FL032K 0x0805UL // 4M ++#define FLASH_IC_S25FL032 0x0804UL // 4M ++ ++// EON ++#define FLASH_IC_EN25F10 0x0900UL // 128K for secure boot ++#define FLASH_IC_EN25F16 0x0901UL // 2M ++#define FLASH_IC_EN25F32 0x0902UL // 4M ++#define FLASH_IC_EN25F80 0x0903UL // 1M ++#define FLASH_IC_EN25B20T 0x0904UL // 2M EON ++#define FLASH_IC_EN25B20B 0x0905UL // 2M ++#define FLASH_IC_EN25B10T 0x0906UL // 1M ++#define FLASH_IC_EN25B10B 0x0907UL // 1M ++#define FLASH_IC_EN25B32B 0x0908UL // 4M (Bottom Boot) ++#define FLASH_IC_EN25Q32 0x0909UL // 4M ++#define FLASH_IC_EN25Q32A 0x090AUL // 4M ++#define FLASH_IC_EN25Q64 0x090BUL // 4M ++#define FLASH_IC_EN25B64B 0x090CUL // 4M ++#define FLASH_IC_EN25Q128 0x090DUL // 16M ++#define FLASH_IC_EN25P16 0x090EUL // 2M ++#define FLASH_IC_EN25F40 0x090AUL // 512k ++#define FLASH_IC_EN25QH16 0x090BUL // 2M ++#define FLASH_IC_EN25Q128A 0x090CUL // 16M ++ ++// ESMT ++#define FLASH_IC_ESMT_F25L016A 0x0A00UL // 2M ++// GD ++#define FLASH_IC_GD25Q32 0x0B00UL // 4M ++#define FLASH_IC_GD25Q16 0x0B01UL // 2MByte ++#define FLASH_IC_GD25S80 0x0B02UL ++#define FLASH_IC_GD25Q64 0x0B03UL // 8M ++#define FLASH_IC_GD25Q128 0x0B05UL //16M ++#define FLASH_IC_GD25Q256C 0x0B06UL //32M ++ ++// AM ++#define FLASH_IC_A25LM032 0x0D00UL ++ ++// MICRON ++#define FLASH_IC_MICRON_M25P16 0x0E00UL // 2M ++#define FLASH_IC_MICRON_N25Q32 0x0E01UL // 4M ++#define FLASH_IC_MICRON_N25Q64 0x0E02UL // 8M ++#define FLASH_IC_MICRON_N25Q128 0x0E03UL // 16M ++#define FLASH_IC_NUMONYX_M25PX16 0x0E04UL // 2M ++ ++//ISSI ++#define FLASH_IC_IS25LP064D 0x0D01UL ++ ++//ZB ++#define FLASH_IC_ZB25Q64 0x1002UL // 8M ++#define FLASH_IC_ZB25VQ128 0x1003UL // 16M ++ ++//Wuhan Xinxin ++#define FLASH_IC_WUHAN_XM25QH16A 0x1200UL // 2M ++#define FLASH_IC_WUHAN_XM25QH32A 0x1201UL // 4M ++#define FLASH_IC_WUHAN_XM25QH64A 0x1202UL // 8M ++#define FLASH_IC_WUHAN_XM25QH128A 0x1203UL // 16M ++#define FLASH_IC_WUHAN_XM25QH128B 0x1204UL // 16M ++#define FLASH_IC_WUHAN_XM25QH64B 0x1205UL // 8M ++#define FLASH_IC_WUHAN_XM25QH128C 0x1206UL // 16M ++#define FLASH_IC_WUHAN_XM25QH64C 0x1207UL // 8M ++#define FLASH_IC_WUHAN_XM25QH256C 0x1208UL // 32M ++ ++// NM ++#define FLASH_IC_NM25Q64 0x1406UL ++#define FLASH_IC_NM25Q128 0x1403UL ++ ++//XTX ++#define FLASH_IC_XTX_XT25F16B 0x1300UL // 2M ++#define FLASH_IC_XTX_XT25F32B 0x1301UL // 4M ++#define FLASH_IC_XTX_XT25F64B 0x1302UL // 8M ++#define FLASH_IC_XTX_XT25F128B 0x1303UL // 16M ++ ++ ++#define FLASH_IC_25Q128AS 0x1100UL // 25q128as ++ ++//BYT ++#define FLASH_IC_BYT_BY25Q64AS 0x1400UL // 64M ++#define FLASH_IC_BYT_BY25Q128AS 0x1401UL // 128M ++ ++//PY ++#define FLASH_IC_PUYA_PY25Q128HA 0x1500UL // 128M ++ ++// Flash Manufacture ID ++#define MID_MXIC 0xC2UL ++#define MID_WB 0xEFUL ++#define MID_EON 0x1CUL ++#define MID_ST 0x20UL ++#define MID_SST 0xBFUL ++#define MID_PMC 0x9DUL ++#define MID_ATMEL 0x1FUL ++#define MID_SPAN 0x01UL ++#define MID_GD 0xC8UL ++#define MID_MICRON 0x20UL ++#define MID_NUMONYX 0x20UL ++#define MID_AM 0x37UL ++#define MID_25Q 0x68UL ++#define MID_ZB 0x5EUL ++#define MID_WUHAN 0x20UL ++#define MID_XTX 0x0BUL ++#define MID_NM 0x52UL ++#define MID_IS 0x9DUL ++#define MID_PY 0x85UL ++ ++// Flash Storage Size ++#define SIZE_1KB 0x400UL ++#define SIZE_2KB 0x800UL ++#define SIZE_4KB 0x1000UL ++#define SIZE_8KB 0x2000UL ++#define SIZE_16KB 0x4000UL ++#define SIZE_32KB 0x8000UL ++#define SIZE_64KB 0x10000UL ++#define SIZE_128KB 0x20000UL ++#define SIZE_256KB 0x40000UL ++#define SIZE_512KB 0x80000UL ++#define SIZE_1MB 0x100000UL ++#define SIZE_2MB 0x200000UL ++#define SIZE_4MB 0x400000UL ++#define SIZE_8MB 0x800000UL ++#define SIZE_16MB 0x1000000UL ++ ++// ISP_DEV_SEL ++#define ISP_DEV_PMC BITS(2:0, 0) ++#define ISP_DEV_NEXTFLASH BITS(2:0, 1) ++#define ISP_DEV_ST BITS(2:0, 2) ++#define ISP_DEV_SST BITS(2:0, 3) ++#define ISP_DEV_ATMEL BITS(2:0, 4) ++ ++// ISP_SPI_ENDIAN_SEL ++#define ISP_SPI_ENDIAN_BIG BITS(0:0, 1) ++#define ISP_SPI_ENDIAN_LITTLE BITS(0:0, 0) ++ ++typedef struct ++{ ++ MS_U8 u8BlockProtectBits; // Block Protection Bits ++ MS_U32 u32LowerBound; ++ MS_U32 u32UpperBound; ++} ST_WRITE_PROTECT; ++ ++typedef struct ++{ ++ MS_U16 u16Start; // Start block # of special block size ++ MS_U16 u16End; // End block # of special block size ++ MS_U32 au32SizeList[8]; // List of special block sizes. Total size must be equal to FLASH_BLOCK_SIZE ++} ST_SPECIAL_BLOCKS; ++ ++ ++typedef struct ++{ ++ MS_U16 u16FlashType; // flash type ++ MS_U8 u8MID; // Manufacture ID ++ MS_U8 u8DID0; // Device ID (memory type) ++ MS_U8 u8DID1; // Device ID (memory capacity) ++ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ ST_SPECIAL_BLOCKS *pSpecialBlocks; ++ ++ MS_U32 u32FlashSize; // Flash Size ++ MS_U32 u32NumSec; // NUMBER_OF_SERFLASH_SECTORS // number of sectors ++ MS_U32 u32SecSize; // SERFLASH_SECTOR_SIZE // sector size ++ MS_U16 u16PageSize; // SERFLASH_PAGE_SIZE // page size ++ MS_U16 u16MaxChipWrDoneTimeout; // SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT // max timeout for chip write done ++ MS_U8 u8WrsrBlkProtect; // SERFLASH_WRSR_BLK_PROTECT // BP bits @ Serial Flash Status Register ++ MS_U16 u16DevSel; // ISP_DEV_SEL // reg_device_select ++ MS_U16 u16SpiEndianSel; // ISP_SPI_ENDIAN_SEL // reg_endian_sel_spi ++ MS_U16 u16SPIMaxClk[2]; ++ MS_BOOL b2XREAD; ++ MS_BOOL b4XREAD; ++} hal_SERFLASH_t; ++ ++#endif //_DRV_DEVICE_INFO_H_ ++ +diff --git a/drivers/sstar/flash_isp/drvSERFLASH.c b/drivers/sstar/flash_isp/drvSERFLASH.c +new file mode 100755 +index 000000000000..7a64285b943e +--- /dev/null ++++ b/drivers/sstar/flash_isp/drvSERFLASH.c +@@ -0,0 +1,1066 @@ ++/* ++* drvSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "drvSERFLASH.h" ++ ++// Common Definition ++//#include "MsDevice.h" ++//#include "MsTypes.h" ++ ++// Internal Definition ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++//#include "drvBDMA.h" ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++#define VER_CHECK_HEADER 'M','S','V','C','0','0' ++#define SERFLASH_LIB_ID 'F','1' // F1: libFLASH.a ++#define SERFLASH_INTERFACE_VER '0','1' ++#define SERFLASH_BUILD_VER '0','0','0','1' ++#define CHANGE_LIST_NUM '0','0','0','9','1','9','9','6' ++#define PRODUCT_NAME 'A','E' // AE: T2 ++#define CUSTOMER_NAME '0' // 0: Sstar ++#define DEVELOP_STAGE 'B','L','E','G' ++#define OS_VERSION '0','0' ++#define CHECK_SUM 'T' ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local & Global Variables ++//////////////////////////////////////////////////////////////////////////////// ++//static MSIF_Version _drv_spif_version = { ++// .DDI = { SPIF_DRV_VERSION }, ++//}; ++ ++static SERFLASH_Info _SERFLASHInfo; ++static SERFLASH_DrvStatus _SERFLASHDrvStatus; ++ ++/// Ask 51 to select flash ++ms_Mcu_ChipSelect_CB McuChipSelectCB = NULL; ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++#define DRV_FLASH_MS(x) (5955 * x) ++#define FLASH_WAIT_TIME (DRV_FLASH_MS(100)*0x200UL) ++#define FLASH_IS_TIMEOUT(x) ((x) ? FALSE : TRUE) ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_FLASH_ISP_READFUNC_MAP ++extern MS_BOOL HAL_DMA_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++extern MS_BOOL HAL_MAP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++MS_BOOL MDrv_MAP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ //MS_U8 *pu8BufAddr = (MS_U8*)MS_PA2KSEG0((MS_U32)pu8Data); // Physical Address to Virtual Address, cache. ++ ++ MS_ASSERT( u32FlashSize > 0 ); ++ MS_ASSERT( u32FlashAddr + u32FlashSize <= _SERFLASHInfo.u32TotalSize ); ++ //ASSERT( u32Addr%4 == 0 ); ++ //ASSERT( u32Size%4 == 0 ); ++ MS_ASSERT( user_buffer != NULL ); ++ //#ifdef MCU_MIPS ++ //MS_ASSERT( user_buffer & (0x80000000) ); ++ //#endif ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (int)u32FlashSize, user_buffer)); ++ return HAL_MAP_Read(u32FlashAddr, u32FlashSize, user_buffer); ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Get the information of Serial Flash ++/// @return the pointer to the driver information ++//------------------------------------------------------------------------------------------------- ++const SERFLASH_Info *MDrv_SERFLASH_GetInfo(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("MDrv_SERFLASH_GetInfo()\n" ++ "\tu32AccessWidth = %d\n" ++ "\tu32TotalSize = %d\n" ++ "\tu32SecNum = %d\n" ++ "\tu32SecSize = %d\n", ++ (int)(_SERFLASHInfo.u32AccessWidth), ++ (int)(_SERFLASHInfo.u32TotalSize), ++ (int)(_SERFLASHInfo.u32SecNum), ++ (int)(_SERFLASHInfo.u32SecSize) ++ ) ++ ); ++ ++ return &_SERFLASHInfo; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Show the SERFLASH driver version ++/// @param ppVersion \b OUT: output SERFLASH driver version ++/// @return TRUE : succeed ++/// @return FALSE : failed ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetLibVer(const MSIF_Version **ppVersion) ++{ ++// if (!ppVersion) ++// return FALSE; ++// ++// *ppVersion = &_drv_spif_version; ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Get Serial Flash driver status ++/// @param pDrvStatus \b OUT: poniter to store the returning driver status ++/// @return TRUE : succeed ++/// @return FALSE : failed to get the driver status ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetStatus(SERFLASH_DrvStatus* pDrvStatus) ++{ ++ memcpy(pDrvStatus, &_SERFLASHDrvStatus, sizeof(_SERFLASHDrvStatus)); ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set detailed level of Parallel Flash driver debug message ++/// @param u8DbgLevel \b IN debug level for Serial Flash driver ++/// @return TRUE : succeed ++/// @return FALSE : failed to set the debug level ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_SetDbgLevel(MS_U8 u8DbgLevel) ++{ ++ _u8SERFLASHDbgLevel = u8DbgLevel; ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : HK ask 8051 to select flash chip by call back function ++/// @param ms_Mcu_ChipSelect_CB \b IN call back function ++/// @return TRUE : succeed ++/// @return NULL : ++//------------------------------------------------------------------------------ ++void MDrv_SERFLASH_SetMcuCSCallBack(ms_Mcu_ChipSelect_CB ChipSel_cb) ++{ ++ McuChipSelectCB = ChipSel_cb; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash type by reading the MID and DID ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash type ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectType(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_DetectType(); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash Size ++/// @param u32FlashSize \b OUT: u32 ptr to store flash size ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash size ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_DetectSize(u32FlashSize); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enable Flash 2XREAD mode, if support ++/// @param b2XMode \b IN: ENABLE/DISABLE ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Set2XRead(MS_BOOL b2XMode) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_Set2XREAD(b2XMode); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set ckg_spi which flash supports (please ref. the spec. before using this function) ++/// @param SPI_DrvCKG \b IN: enumerate the ckg_spi ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not. It is safty to run at 43M (Default). ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetCKG(SPI_DrvCKG eCKGspi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_SetCKG(eCKGspi); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set clock div such that spi clock = mcu clock /clock_div. ++/// @param SPI_DrvClkDiv \b IN: enumerate the clock_div ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivspi) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ HAL_SERFLASH_ClkDiv(eClkDivspi); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set XIU/RIU mode (Default : XIU) ++/// @param bXiuRiu \b IN: 1 for XIU, 0 for RIU ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note XIU mode is faster than RIU mode. It is stable to run by XIU (Default) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_SetMode(bXiuRiu); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set active flash among multi-spi flashes ++/// @param u8FlashIndex \b IN: The Flash index, 0 for external #1 spi flash, 1 for external #2 spi flash ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note For Secure booting = 0, please check hw_strapping or e-fuse (the board needs to jump) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_ASSERT((u8FlashIndex < 4)); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_ChipSelect(u8FlashIndex); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Initialize Serial Flash ++/// @return None ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_Init(void) ++{ ++ _u8SERFLASHDbgLevel = E_SERFLASH_DBGLV_ERR; // init debug level first //SERFLASH_DBGLV_DEBUG ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++#if 0 ++ // ++ // 1. HAL init ++ // ++ MS_U32 u32PMBank, u32PMBankSize; ++ MS_U32 u32NonPMBank, u32NonPMBankSize; ++ MS_U32 u32FlashBank0, u32FlashBank0Size; ++ ++ if (!MDrv_MMIO_GetBASE( &u32PMBank, &u32PMBankSize, MS_MODULE_ISP)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("IOMap failure to get DRV_MMIO_NONPM_BANK\n")); ++ } ++ ++ if (!MDrv_MMIO_GetBASE( &u32NonPMBank, &u32NonPMBankSize, MS_MODULE_MHEG5)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("IOMap failure to get DRV_MMIO_NONPM_BANK\n")); ++ } ++ ++ if (!MDrv_MMIO_GetBASE( &u32FlashBank0, &u32FlashBank0Size, MS_MODULE_FLASH)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("IOMap failure to get DRV_MMIO_NONPM_BANK\n")); ++ } ++ ++#endif ++ ++ HAL_SERFLASH_Config(); ++ ++ HAL_SERFLASH_Init(); ++ ++ HAL_SERFLASH_DetectType(); ++ ++ // ++ // 2. init SERFLASH_Info ++ // ++ _SERFLASHInfo.u32AccessWidth = 1; ++ _SERFLASHInfo.u32SecNum = NUMBER_OF_SERFLASH_SECTORS; ++ _SERFLASHInfo.u32SecSize = SERFLASH_SECTOR_SIZE; ++ //_SERFLASHInfo.u32TotalSize = (NUMBER_OF_SERFLASH_SECTORS * SERFLASH_SECTOR_SIZE); ++ HAL_SERFLASH_DetectSize(&_SERFLASHInfo.u32TotalSize); ++ // ++ // 3. init other data structure of Serial Flash driver ++ // ++ _SERFLASHDrvStatus.bIsBusy = FALSE; ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase all sectors in Serial Flash ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_EraseChip(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return HAL_SERFLASH_EraseChip(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start block index of a flash address ++/// @param u32FlashAddr \b IN: flash address ++/// @param pu32BlockIndex \b IN: poniter to store the returning block index ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_ASSERT(u32FlashAddr < _SERFLASHInfo.u32TotalSize); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %p)\n", __FUNCTION__, (int)u32FlashAddr, pu32BlockIndex)); ++ ++ return HAL_SERFLASH_AddressToBlock(u32FlashAddr, pu32BlockIndex); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start address of a block index ++/// @param u32BlockIndex \b IN: block index ++/// @param pu32FlashAddr \b IN: pointer to store the returning flash address ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ MS_ASSERT(u32BlockIndex < _SERFLASHInfo.u32SecNum); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %p)\n", __FUNCTION__, (int)u32BlockIndex, pu32FlashAddr)); ++ ++ return HAL_SERFLASH_BlockToAddress(u32BlockIndex, pu32FlashAddr); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors given starting address and size in Serial Flash ++/// @param u32StartAddr \b IN: start address at block boundry ++/// @param u32EraseSize \b IN: size to erase ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, MS_BOOL bWait) ++{ ++ MS_U32 u32StartBlock; ++ MS_U32 u32EndBlock; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, ++ (unsigned int)u32StartAddr, (unsigned int)u32EraseSize, (int)bWait)); ++ ++ if ( FALSE == MDrv_SERFLASH_AddressToBlock(u32StartAddr, &u32StartBlock) ++ || FALSE == MDrv_SERFLASH_AddressToBlock(u32StartAddr + u32EraseSize - 1, &u32EndBlock) ++ ) ++ { ++ return FALSE; ++ } ++ ++ return MDrv_SERFLASH_BlockErase(u32StartBlock, u32EndBlock, bWait); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors in Serial Flash ++/// @param u32StartBlock \b IN: start block ++/// @param u32EndBlock \b IN: end block ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock 0 ); ++ MS_ASSERT( u32FlashAddr + u32FlashSize <= _SERFLASHInfo.u32TotalSize ); ++ //ASSERT( u32Addr%4 == 0 ); ++ //ASSERT( u32Size%4 == 0 ); ++ MS_ASSERT( user_buffer != NULL ); ++ //#ifdef MCU_MIPS ++ //MS_ASSERT( user_buffer & (0x80000000) ); ++ //#endif ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (int)u32FlashSize, user_buffer)); ++ ++#ifdef CONFIG_FLASH_ISP_READFUNC_MAP ++ return HAL_MAP_Read(u32FlashAddr, u32FlashSize, user_buffer); ++#else ++ return HAL_SERFLASH_Read(u32FlashAddr, u32FlashSize, user_buffer); ++#endif ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnable \b IN: TRUE/FALSE: enable/disable protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, (int)bEnable)); ++ return HAL_SERFLASH_WriteProtect(bEnable); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Enable_All_Range(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_WriteProtect_Area(TRUE, 0 << 2); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Disables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_All_Range(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_WriteProtect_Disable_Range_Set(0, _SERFLASHInfo.u32TotalSize); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set flash disable lower bound and size ++/// @param u32DisableLowerBound \b IN: the lower bound to disable write protect ++/// @param u32DisableSize \b IN: size to disable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_Range_Set(MS_U32 u32DisableLowerBound, MS_U32 u32DisableSize) ++{ ++ MS_U32 u32EnableLowerBound; ++ MS_U32 u32EnableUpperBound; ++ MS_U8 u8BlockProtectBit; ++ ++ MS_U32 u32DisableUpperBound; ++ MS_U32 u32FlashIndexMax; ++ ++ EN_WP_AREA_EXISTED_RTN enWpAreaExistedRtn; ++ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ _SERFLASHDrvStatus.bIsBusy = TRUE; ++ ++ u32DisableUpperBound = u32DisableLowerBound + u32DisableSize - 1; ++ u32FlashIndexMax = _SERFLASHInfo.u32TotalSize - 1; ++ ++ ++ if ( u32DisableLowerBound > u32FlashIndexMax ++ || u32DisableUpperBound > u32FlashIndexMax ++ || u32DisableLowerBound > u32DisableUpperBound ++ ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk(" = FALSE, u32DisableLowerBound(0x%08X), u32DisableUpperBound(0x%08X), u32FlashIndexMax(0x%08X)\n", (int)u32DisableLowerBound, (int)u32DisableUpperBound, (int)u32FlashIndexMax)); ++ ++ return FALSE; ++ } ++ ++ ++ // Step 1. decide u32DisableUpperBound // TODO: review, prefer to unprotect the end of the flash ++ if ( u32DisableUpperBound != u32FlashIndexMax ++ && u32DisableLowerBound != 0 ++ ) ++ { ++ u32DisableUpperBound = u32FlashIndexMax; ++ } ++ ++ ++ // Step 2. decide u32EnableLowerBound & u32EnableUpperBound ++ if ( u32DisableUpperBound > (u32FlashIndexMax - _SERFLASHInfo.u32SecSize) ++ && u32DisableLowerBound == 0 ++ ) ++ { ++ // i.e. no protect ++ u32EnableLowerBound = 0xFFFFFFFFUL; ++ u32EnableUpperBound = 0xFFFFFFFFUL; ++ } ++ else if (u32DisableLowerBound == 0) ++ { ++ u32EnableUpperBound = u32FlashIndexMax; ++ u32EnableLowerBound = u32DisableUpperBound + 1; ++ } ++ else // i.e. (u32DisableUpperBound == u32FlashIndexMax) because of Step 1 ++ { ++ u32EnableUpperBound = u32DisableLowerBound - 1; ++ u32EnableLowerBound = 0; ++ } ++ ++ ++ // Step 3. get u8BlockProtectBit ++ enWpAreaExistedRtn = HAL_SERFLASH_WP_Area_Existed(u32EnableUpperBound, u32EnableLowerBound, &u8BlockProtectBit); ++ ++ switch (enWpAreaExistedRtn) ++ { ++ case WP_AREA_NOT_AVAILABLE: ++ case WP_TABLE_NOT_SUPPORT: ++ u8BlockProtectBit = 0; ++ break; ++ ++ default: ++ /* DO NOTHING */ ++ break; ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return HAL_SERFLASH_WriteProtect_Area(FALSE, u8BlockProtectBit); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnableAllArea \b IN: enable or disable protection ++/// @param u8BlockProtectBits \b IN: block protection bits which stand for the area to enable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, (int)bEnableAllArea, u8BlockProtectBits)); ++ return HAL_SERFLASH_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read ID from Serial Flash ++/// @param pu8FlashID \b OUT: Virtual data ptr to store the read ID ++/// @param u32IDSize \b IN: size in Bytes ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadID(MS_U8 *pu8FlashID, MS_U32 u32IDSize) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%p, %d)\n", __FUNCTION__, pu8FlashID, (int)u32IDSize)); ++ return HAL_SERFLASH_ReadID(pu8FlashID, u32IDSize); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read data from Serial Flash to DRAM in DMA mode ++/// @param u32FlashStart \b IN: src start address in flash (0 ~ flash size-1) ++/// @param u32DRASstart \b IN: dst start address in DRAM (16B-aligned) (0 ~ DRAM size-1) ++/// @param u32Size \b IN: size in Bytes (8B-aligned) (>=8) ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++//MS_BOOL MDrv_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++//{ ++// MS_ASSERT( u32FlashStart+u32Size <= _SERFLASHInfo.u32TotalSize); ++// MS_ASSERT( u32DRASstart%8 ==0 ); ++// MS_ASSERT( u32Size%8 ==0 ); ++// MS_ASSERT( u32Size>=8 ); ++// ++// DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++// return HAL_SERFLASH_DMA(u32FlashStart, u32DRASstart, u32Size); ++//} ++ ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister(MS_U8 *pu8StatusReg) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_ReadStatusReg(pu8StatusReg); ++} ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register2 in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register (high-byte) ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_ReadStatusReg2(pu8StatusReg); ++} ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Write Status Register in Serial Flash ++/// @param u16StatusReg \b IN: Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteStatusRegister(MS_U16 u16StatusReg) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_WriteStatusReg(u16StatusReg); ++} ++ ++////------- ------------------------------------------------------------------------------------------ ++///// Description : Handle for BDMA copy data from ONLY Flash src to other dst ++///// @param u32FlashAddr \b IN: Physical Source address in spi flash ++///// @param u32DramAddr \b IN: Physical Dst address ++///// @param u32Len \b IN: data length ++///// @param eDstDev \b IN: The Dst Device of Flash BDMA ++///// @param u8OpCfg \b IN: u8OpCfg: default is SPIDMA_OPCFG_DEF ++///// - Bit0: inverse mode --> SPIDMA_OPCFG_INV_COPY ++///// - Bit2: Copy & CRC check in wait mode --> SPIDMA_OPCFG_CRC_COPY ++///// - Bit3: Copy without waiting --> SPIDMA_OPCFG_NOWAIT_COPY ++///// @return \b MS_BOOL ++///// [NONOS_SUPPORT] ++///// [fw : drvBDMA ] ++////------------------------------------------------------------------------------------------------- ++//MS_BOOL MDrv_SERFLASH_CopyHnd(MS_PHYADDR u32FlashAddr, ++// MS_PHYADDR u32DstAddr, ++// MS_U32 u32Len, ++// SPIDMA_Dev eDstDev, ++// MS_U8 u8OpCfg) ++//{ ++// #define BDMA_DEV_FLASH 5 ++// MS_U16 CpyType = ((BDMA_DEV_FLASH & 0x0F) | _LShift((eDstDev &0x0F), 8)); ++// MS_U32 u32Delay = FLASH_WAIT_TIME; ++// ++// while (!HAL_SERFLASH_CheckWriteDone()) ++// { ++// if (FLASH_IS_TIMEOUT(u32Delay)) ++// { ++// printk("%s() : DMA flash is busy!\n",__FUNCTION__); ++// return FALSE; ++// } ++// u32Delay--; ++// } ++// ++// return MDrv_BDMA_CopyHnd(u32FlashAddr, u32DstAddr, u32Len, (BDMA_CpyType) CpyType, u8OpCfg); ++//} ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Switch SPI as GPIO Input ++/// @param bSwitch \b IN: 1 for GPIO, 0 for NORMAL ++/// @note Not allowed in interrupt context ++/// @note For project's power consumption ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ HAL_SERFLASH_SetGPIO(bSwitch); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// FSP ++//------------------------------------------------------------------------------------------------- ++/* ++MS_BOOL MDrv_FSP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ MS_U32 Index; ++ ++#define FSP_READ_SIZE 4 ++ ++ for(Index = 0; Index < u32FlashSize; ) ++ { ++ HAL_SERFLASH_ReadWordFlashByFSP(u32FlashAddr+Index, user_buffer+Index); ++ Index += FSP_READ_SIZE; ++ } ++ ++ return 1; ++} ++ ++MS_BOOL MDrv_FSP_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ MS_U32 Index; ++ MS_U32 u32ProgData; ++ ++#define FSP_WRITE_SIZE 4 ++ ++ for(Index = 0; Index < u32FlashSize; ) ++ { ++ u32ProgData = (*(user_buffer + Index))|(*(user_buffer + Index + 1)<<8)|(*(user_buffer + Index + 2)<<16)|(*(user_buffer + Index + 3)<<24); ++ HAL_SERFLASH_ProgramFlashByFSP(u32FlashAddr+Index, u32ProgData); ++ Index += FSP_WRITE_SIZE; ++ } ++ ++ return 1; ++} ++ ++ ++MS_BOOL MDrv_FSP_ReadStatusRegister(MS_U8 *pu8StatusReg) ++{ ++ *pu8StatusReg = HAL_SERFLASH_ReadStatusByFSP(); ++ ++ return 1; ++} ++ ++MS_BOOL MDrv_FSP_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, E_FSP_ERASE eERASE) ++{ ++ MS_U32 Index; ++ ++ switch ( eERASE ) ++ { ++ case E_FSP_ERASE_4K: ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseSectorByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_4K; ++ } ++ } ++ break; ++ case E_FSP_ERASE_32K: ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseBlock32KByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_32K; ++ } ++ } ++ break; ++ case E_FSP_ERASE_64K: ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseBlock64KByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_64K; ++ } ++ } ++ break; ++ default : ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseBlock64KByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_64K; ++ } ++ } ++ break; ++ } ++ return 1; ++} ++*/ ++ ++MS_BOOL MDrv_SERFLASH_QPI_ENABLE(MS_BOOL bEnable) ++{ ++ return HAL_QPI_Enable( bEnable); ++} ++ ++MS_BOOL MDrv_SERFLASH_QPI_REST(MS_BOOL bEnable) ++{ ++ return HAL_QPI_RESET( bEnable); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// WRAPPER FOR CHAKRA ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_FLASH_QPI_ENALBE(MS_BOOL bEnable) ++{ ++ return MDrv_SERFLASH_QPI_ENABLE( bEnable); ++} ++ ++MS_BOOL MDrv_FLASH_QPI_REST(MS_BOOL bEnable) ++{ ++ return MDrv_SERFLASH_QPI_REST( bEnable); ++} ++ ++MS_BOOL MDrv_FLASH_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s( 0x%x, 0x%x, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (unsigned int)u32FlashSize, user_buffer)); ++ return MDrv_SERFLASH_Write(u32FlashAddr, u32FlashSize, user_buffer); ++ ++} ++ ++MS_BOOL MDrv_FLASH_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s( 0x%x, 0x%x, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (unsigned int)u32FlashSize, user_buffer)); ++ return MDrv_SERFLASH_Read(u32FlashAddr, u32FlashSize, user_buffer); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect(MS_BOOL bEnable) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, (int)bEnable)); ++ return MDrv_SERFLASH_WriteProtect(bEnable); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Enable_All_Range(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_WriteProtect_Enable_All_Range(); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_All_Range(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_WriteProtect_Disable_All_Range(); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_Range_Set(MS_U32 DisableLowerBound, MS_U32 DisableSize) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%x, 0x%x)\n", __FUNCTION__, (unsigned int)DisableLowerBound, (unsigned int)DisableSize)); ++ return MDrv_SERFLASH_WriteProtect_Disable_Range_Set(DisableLowerBound, DisableSize); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 BlockProtectBits) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02x)\n", __FUNCTION__, (int)bEnableAllArea, BlockProtectBits)); ++ return MDrv_SERFLASH_WriteProtect_Area(bEnableAllArea, BlockProtectBits); ++} ++ ++MS_BOOL MDrv_FLASH_ReadStatusRegister(MS_U8 *pu8StatusReg) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%p)\n", __FUNCTION__, pu8StatusReg)); ++ return MDrv_SERFLASH_ReadStatusRegister(pu8StatusReg); ++} ++ ++MS_BOOL MDrv_FLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%p)\n", __FUNCTION__, pu8StatusReg)); ++ return MDrv_SERFLASH_ReadStatusRegister2(pu8StatusReg); ++} ++ ++MS_BOOL MDrv_FLASH_WriteStatusRegister(MS_U16 u16StatusReg) ++{ ++ return MDrv_SERFLASH_WriteStatusRegister(u16StatusReg); ++} ++MS_BOOL MDrv_FLASH_DetectType(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_DetectType(); ++} ++ ++MS_BOOL MDrv_FLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_DetectSize(u32FlashSize); ++} ++MS_BOOL MDrv_FLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, pu16BlockIndex)); ++ return MDrv_SERFLASH_AddressToBlock(u32FlashAddr, pu32BlockIndex); ++} ++ ++MS_BOOL MDrv_FLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%04x, %p)\n", __FUNCTION__, u16BlockIndex, pu32FlashAddr)); ++ return MDrv_SERFLASH_BlockToAddress(u32BlockIndex, pu32FlashAddr); ++} ++ ++MS_BOOL MDrv_FLASH_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, MS_BOOL bWait) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartAddr, (unsigned int)u32Size, (int)bWait)); ++ return MDrv_SERFLASH_AddressErase(u32StartAddr, u32EraseSize, bWait); ++} ++ ++MS_BOOL MDrv_FLASH_BlockErase(MS_U16 u16StartBlock, MS_U16 u16EndBlock, MS_BOOL bWait) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%04x, 0x%04x, %d)\n", __FUNCTION__, u16StartBlock, u16EndBlock, (int)bWait)); ++ return MDrv_SERFLASH_BlockErase(u16StartBlock, u16EndBlock, bWait); ++} ++ ++MS_BOOL MDrv_FLASH_CheckWriteDone(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_CheckWriteDone(); ++} ++ ++ ++//MS_BOOL MsOS_In_Interrupt (void) ++inline MS_BOOL MS_SERFLASH_IN_INTERRUPT (void) ++{ ++ return FALSE; ++} ++ ++//MS_S32 MsOS_CreateMutex ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag) ++inline MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag) ++{ ++ return 1; ++} ++ ++//MS_BOOL MsOS_DeleteMutex (MS_S32 s32MutexId) ++inline MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId) ++{ ++ return TRUE; ++} ++ ++//MS_BOOL MsOS_ObtainMutex (MS_S32 s32MutexId, MS_U32 u32WaitMs) ++inline MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs) ++{ ++ return TRUE; ++} ++ ++//MS_BOOL MsOS_ReleaseMutex (MS_S32 s32MutexId) ++inline MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId) ++{ ++ return TRUE; ++} ++ +diff --git a/drivers/sstar/flash_isp/drvSERFLASH.h b/drivers/sstar/flash_isp/drvSERFLASH.h +new file mode 100755 +index 000000000000..933d66ca05a0 +--- /dev/null ++++ b/drivers/sstar/flash_isp/drvSERFLASH.h +@@ -0,0 +1,505 @@ ++/* ++* drvSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_SERFLASH_H_ ++#define _DRV_SERFLASH_H_ ++ ++//#include ++//#include "drvBDMA.h" ++#include "MsTypes.h" ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MSIF_SPIF_LIB_CODE {'S','P','I','F'} //Lib code ++#define MSIF_SPIF_LIBVER {'0','1'} //LIB version ++#define MSIF_SPIF_BUILDNUM {'0','1'} //Build Number ++#define MSIF_SPIF_CHANGELIST {'0','0','1','1','4','5','3','4'} //P4 ChangeList Number ++ ++//------------------------------------------------------------------------------------------------- ++// Version String Definition ++//------------------------------------------------------------------------------------------------- ++// Move from MsVersion.h ++#define MSIF_TAG {'M','S','I','F'} // MSIF ++#define MSIF_CLASS {'0','0'} // DRV/API (DDI) ++#define MSIF_CUS 0x0000UL // Sstar Common library ++#define MSIF_MOD 0x0000UL // Sstar Common library ++#define MSIF_CHIP 0x000FUL ++#define MSIF_CPU '1' ++#define MSIF_OS '0' ++ ++#define SPIF_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_TAG, /* 'MSIF' */ \ ++ MSIF_CLASS, /* '00' */ \ ++ MSIF_CUS, /* 0x0000 */ \ ++ MSIF_MOD, /* 0x0000 */ \ ++ MSIF_CHIP, \ ++ MSIF_CPU, \ ++ MSIF_SPIF_LIB_CODE, /* IP__ */ \ ++ MSIF_SPIF_LIBVER, /* 0.0 ~ Z.Z */ \ ++ MSIF_SPIF_BUILDNUM, /* 00 ~ 99 */ \ ++ MSIF_SPIF_CHANGELIST, /* CL# */ \ ++ MSIF_OS ++ ++/// Operation cfg ++#define SPIDMA_CFG_ADDR_DIR_BIT (0) ++#define SPIDMA_CFG_REFLECT_BIT (1) ++#define SPIDMA_CFG_CRCCOPY_BIT (2) ++#define SPIDMA_CFG_NOWAITCOPY_BIT (3) ++ ++#define SPIDMA_OPCFG_DEF (0) ++#define SPIDMA_OPCFG_INV_COPY _LShift(1, SPIDMA_CFG_ADDR_DIR_BIT) ++#define SPIDMA_OPCFG_CRC_REFLECT _LShift(1, SPIDMA_CFG_REFLECT_BIT) //bit reflection of each input byte ++#define SPIDMA_OPCFG_CRC_COPY _LShift(1, SPIDMA_CFG_CRCCOPY_BIT) //copy then crc check ++#define SPIDMA_OPCFG_NOWAIT_COPY _LShift(1, SPIDMA_CFG_NOWAITCOPY_BIT) //copy then quit ++ ++#define MS_ASSERT(condition) // ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++/// Serial Flash information structure ++typedef struct ++{ ++ MS_U32 u32AccessWidth; //data access width in bytes ++ MS_U32 u32TotalSize; //total size in bytes ++ MS_U32 u32SecNum; //number of sectors ++ MS_U32 u32SecSize; //sector size in bytes ++} SERFLASH_Info; ++ ++typedef struct ++{ ++ MS_BOOL bIsBusy; ++} SERFLASH_DrvStatus; ++ ++typedef enum ++{ ++ E_SERFLASH_DBGLV_NONE, //disable all the debug message ++ E_SERFLASH_DBGLV_INFO, //information ++ E_SERFLASH_DBGLV_NOTICE, //normal but significant condition ++ E_SERFLASH_DBGLV_WARNING, //warning conditions ++ E_SERFLASH_DBGLV_ERR, //error conditions ++ E_SERFLASH_DBGLV_CRIT, //critical conditions ++ E_SERFLASH_DBGLV_ALERT, //action must be taken immediately ++ E_SERFLASH_DBGLV_EMERG, //system is unusable ++ E_SERFLASH_DBGLV_DEBUG //debug-level messages ++} SERFLASH_DbgLv; ++ ++typedef enum _SPIDMA_Dev ++{ ++ E_SPIDMA_DEV_MIU0, ++ E_SPIDMA_DEV_MIU1, ++ E_SPIDMA_DEV_DMDMCU = 6, ++ E_SPIDMA_DEV_VDMCU, ++ E_SPIDMA_DEV_DSP, ++ E_SPIDMA_DEV_TSP, ++ E_SPIDMA_DEV_1KSRAM_HK51, ++ E_SPIDMA_DEV_NOT_SUPPORT ++}SPIDMA_Dev; ++ ++typedef enum _SPI_DrvCKG ++{ ++ E_SPI_XTALI = 0, ++ E_SPI_27M, ++ E_SPI_36M, ++ E_SPI_43M, ++ E_SPI_54M, ++ E_SPI_72M, ++ E_SPI_86M, ++ E_SPI_108M, ++ E_SPI_24M = 15, // T3 only ++ E_SPI_HALCKG_NOT_SUPPORT ++}SPI_DrvCKG; ++ ++typedef enum _SPI_DrvClkDiv ++{ ++ E_SPI_DIV2 ++ ,E_SPI_DIV4 ++ ,E_SPI_DIV8 ++ ,E_SPI_DIV16 ++ ,E_SPI_DIV32 ++ ,E_SPI_DIV64 ++ ,E_SPI_DIV128 ++ ,E_SPI_ClkDiv_NOT_SUPPORT ++}SPI_DrvClkDiv; ++ ++typedef enum _E_FSP_ERASE ++{ ++ E_FSP_ERASE_4K = 0x1000, ++ E_FSP_ERASE_32K = 0x8000, ++ E_FSP_ERASE_64K = 0x10000, ++}E_FSP_ERASE; ++ ++///SPI CS callback ++typedef void (*ms_Mcu_ChipSelect_CB)(void); ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get the information of Serial Flash ++/// @return the pointer to the driver information ++//------------------------------------------------------------------------------------------------- ++const SERFLASH_Info *MDrv_SERFLASH_GetInfo(void); ++ ++//------------------------------------------------------------------------------ ++/// Description : Show the SERFLASH driver version ++/// @param ppVersion \b OUT: output NORF driver version ++/// @return TRUE : succeed ++/// @return FALSE : failed ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetLibVer(const MSIF_Version **ppVersion); ++ ++//------------------------------------------------------------------------------ ++/// Description : Get Serial Flash driver status ++/// @param pDrvStatus \b OUT: poniter to store the returning driver status ++/// @return TRUE : succeed ++/// @return FALSE : failed to get the driver status ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetStatus(SERFLASH_DrvStatus* pDrvStatus); ++ ++//------------------------------------------------------------------------------ ++/// Description : Set detailed level of Parallel Flash driver debug message ++/// @param u8DbgLevel \b IN debug level for Serial Flash driver ++/// @return TRUE : succeed ++/// @return FALSE : failed to set the debug level ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_SetDbgLevel(MS_U8 u8DbgLevel); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash type by reading the MID and DID ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash type ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectType(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash Size ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash size ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enable Flash 2XREAD mode, if support ++/// @param b2XMode \b IN: ENABLE/DISABLE ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Set2XRead(MS_BOOL b2XMode); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set ckg_spi which flash supports (please ref. the spec. before using this function) ++/// @param SPI_DrvCKG \b IN: enumerate the ckg_spi ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not. It is safty to run at 43M (Default). ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetCKG(SPI_DrvCKG eCKGspi); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set XIU/RIU mode (Default : XIU) ++/// @param bXiuRiu \b IN: 1 for XIU, 0 for RIU ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note XIU mode is faster than RIU mode. It is stable to run by XIU (Default) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set active flash among multi-spi flashes ++/// @param u8FlashIndex \b IN: The Flash index, 0 for external #1 spi flash, 1 for external #2 spi flash ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note For Secure booting = 0, please check hw_strapping or e-fuse (the board needs to jump) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++ ++//------------------------------------------------------------------------------------------------- ++/// Initialize Serial Flash ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_Init(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read ID from Serial Flash ++/// @param pu8FlashID \b OUT: Virtual data ptr to store the read ID ++/// @param u32IDSize \b IN: size in Bytes ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadID(MS_U8 *pu8FlashID, MS_U32 u32IDSize); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read data from Serial Flash ++/// @param u32FlashAddr \b IN: Flash Address ++/// @param u32FlashSize \b IN: Flash Size Data in Bytes ++/// @param user_buffer \b OUT: Virtual Buffer Address ptr to store flash read data ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase all sectors in Serial Flash ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_EraseChip(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start block index of a flash address ++/// @param u32FlashAddr \b IN: flash address ++/// @param pu32BlockIndex \b IN: poniter to store the returning block index ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start address of a block index ++/// @param u32BlockIndex \b IN: block index ++/// @param pu32FlashAddr \b IN: pointer to store the returning flash address ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors given starting address and size in Serial Flash ++/// @param u32StartAddr \b IN: start address at block boundry ++/// @param u32EraseSize \b IN: size to erase ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, MS_BOOL bWait); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors in Serial Flash ++/// @param u32StartBlock \b IN: start block ++/// @param u32EndBlock \b IN: end block ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain 4K sectors in Serial Flash ++/// @param u32StartBlock \b IN: start address ++/// @param u32EndBlock \b IN: end address ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SectorErase(MS_U32 u32StartAddr, MS_U32 u32EndAddr); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Check write done in Serial Flash ++/// @return TRUE : done ++/// @return FALSE : not done ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_CheckWriteDone(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Write data to Serial Flash ++/// @param u32FlashAddr \b IN: start address (4-B aligned) ++/// @param u32FlashSize \b IN: size in Bytes (4-B aligned) ++/// @param user_buffer \b IN: Virtual Buffer Address ptr to flash write data ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read data from Serial Flash to DRAM in DMA mode ++/// @param u32FlashStart \b IN: src start address in flash (0 ~ flash size-1) ++/// @param u32DRASstart \b IN: dst start address in DRAM (16B-aligned) (0 ~ DRAM size-1) ++/// @param u32Size \b IN: size in Bytes (8B-aligned) (>=8) ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnable \b IN: TRUE/FALSE: enable/disable protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect(MS_BOOL bEnable); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Enable_All_Range(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Disables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_All_Range(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set flash disable lower bound and size ++/// @param u32DisableLowerBound \b IN: the lower bound to disable write protect ++/// @param u32DisableSize \b IN: size to disable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_Range_Set(MS_U32 u32DisableLowerBound, MS_U32 u32DisableSize); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnableAllArea \b IN: enable or disable protection ++/// @param u8BlockProtectBits \b IN: block protection bits which stand for the area to enable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister(MS_U8 *pu8StatusReg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register2 in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register (high-byte) ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Write Status Register in Serial Flash ++/// @param u16StatusReg \b IN: Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteStatusRegister(MS_U16 u16StatusReg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Handle for BDMA copy data from ONLY Flash src to other dst ++/// @param u32FlashAddr \b IN: Physical Source address in spi flash ++/// @param u32DramAddr \b IN: Physical Dst address ++/// @param u32Len \b IN: data length ++/// @param eDstDev \b IN: The Dst Device of Flash BDMA ++/// @param u8OpCfg \b IN: u8OpCfg: default is SPIDMA_OPCFG_DEF ++/// - Bit0: inverse mode --> SPIDMA_OPCFG_INV_COPY ++/// - Bit2: Copy & CRC check in wait mode --> SPIDMA_OPCFG_CRC_COPY ++/// - Bit3: Copy without waiting --> SPIDMA_OPCFG_NOWAIT_COPY ++/// @return \b MS_BOOL ++/// [NONOS_SUPPORT] ++/// [fw : drvBDMA ] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_CopyHnd(MS_PHYADDR u32FlashAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, SPIDMA_Dev eDstDev, MS_U8 u8OpCfg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Switch SPI as GPIO Input ++/// @param bSwitch \b IN: 1 for GPIO, 0 for NORMAL ++/// @note Not allowed in interrupt context ++/// @note For project's power consumption ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++ ++//------------------------------------------------------------------------------------------------- ++// WRAPPER FOR CHAKRA ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_FLASH_Write(MS_U32 u32FlashAddr,MS_U32 u32FlashSize,MS_U8 * user_buffer); ++MS_BOOL MDrv_FLASH_Read(MS_U32 u32FlashAddr,MS_U32 u32FlashSize,MS_U8 * user_buffer); ++MS_BOOL MDrv_FLASH_WriteProtect(MS_BOOL bEnable); ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Enable_All_Range(void); ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_All_Range(void); ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_Range_Set(MS_U32 DisableLowerBound, MS_U32 DisableSize); ++MS_BOOL MDrv_FLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 BlockProtectBits); ++MS_BOOL MDrv_FLASH_ReadStatusRegister(MS_U8 *pu8StatusReg); ++MS_BOOL MDrv_FLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg); ++MS_BOOL MDrv_FLASH_WriteStatusRegister(MS_U16 u16StatusReg); ++ ++MS_BOOL MDrv_FLASH_DetectType(void); ++MS_BOOL MDrv_FLASH_DetectSize(MS_U32 *u32FlashSize); ++MS_BOOL MDrv_FLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++MS_BOOL MDrv_FLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++MS_BOOL MDrv_FLASH_AddressErase(MS_U32 u32StartAddr,MS_U32 u32EraseSize,MS_BOOL bWait); ++MS_BOOL MDrv_FLASH_BlockErase(MS_U16 u16StartBlock,MS_U16 u16EndBlock,MS_BOOL bWait); ++MS_BOOL MDrv_FLASH_CheckWriteDone(void); ++ ++//Flash Self-Programming (FSP) ++ ++//MS_BOOL MDrv_FSP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++//MS_BOOL MDrv_FSP_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++MS_BOOL MDrv_FSP_ReadStatusRegister(MS_U8 *pu8StatusReg); ++MS_BOOL MDrv_FSP_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, E_FSP_ERASE eERASE); ++ ++ ++extern ms_Mcu_ChipSelect_CB McuChipSelectCB; ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _DRV_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/include/MsTypes.h b/drivers/sstar/flash_isp/include/MsTypes.h +new file mode 100755 +index 000000000000..5d874c95bdc8 +--- /dev/null ++++ b/drivers/sstar/flash_isp/include/MsTypes.h +@@ -0,0 +1,203 @@ ++/* ++* MsTypes.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MS_TYPES_H_ ++#define _MS_TYPES_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// data type unsigned char, data length 1 byte ++typedef unsigned char MS_U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short MS_U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned long MS_U32; // 4 bytes ++/// data type unsigned int, data length 8 byte ++typedef unsigned long long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed long MS_S32; // 4 bytes ++/// data type signed int, data length 8 byte ++typedef signed long long MS_S64; // 8 bytes ++/// data type float, data length 4 byte ++typedef float MS_FLOAT; // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++/// data type hardware physical address ++typedef unsigned long MS_PHYADDR; // 32bit physical address ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// definition for MS_BOOL ++typedef unsigned char MS_BOOL; ++/// definition for VOID ++//typedef void VOID; ++/// definition for FILEID ++typedef MS_S32 FILEID; ++ ++//[TODO] use MS_U8, ... instead ++// data type for 8051 code ++//typedef MS_U16 WORD; ++//typedef MS_U8 BYTE; ++ ++ ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++ ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++///Define MS FB Format, to share with GE,GOP ++/// FIXME THE NAME NEED TO BE REFINED, AND MUST REMOVE UNNESSARY FMT ++typedef enum ++{ ++ /// color format I1 ++ E_MS_FMT_I1 = 0x0, ++ /// color format I2 ++ E_MS_FMT_I2 = 0x1, ++ /// color format I4 ++ E_MS_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ E_MS_FMT_I8 = 0x4, ++ /// color format blinking display ++ E_MS_FMT_FaBaFgBg2266 = 0x6, ++ /// color format for blinking display format ++ E_MS_FMT_1ABFgBg12355 = 0x7, ++ /// color format RGB565 ++ E_MS_FMT_RGB565 = 0x8, ++ /// color format ARGB1555 ++ /// @note [URANUS] ARGB1555 is only RGB555 ++ E_MS_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ E_MS_FMT_ARGB4444 = 0xa, ++ /// color format ARGB1555 DST ++ E_MS_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ E_MS_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ E_MS_FMT_ARGB8888 = 0xf, ++ /// color format RGBA5551 ++ E_MS_FMT_RGBA5551 = 0x10, ++ /// color format RGBA4444 ++ E_MS_FMT_RGBA4444 = 0x11, ++ /// color format ABGR8888 ++ E_MS_FMT_ABGR8888 = 0x1f, ++ ++ E_MS_FMT_GENERIC = 0xFFFF, ++ ++} MS_ColorFormat; ++ ++ ++typedef union _MSIF_Version ++{ ++ struct _DDI ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 model; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 change[8]; ++ MS_U8 os; ++ } MS_DDI; ++ struct _MW ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 mod; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 changelist[8]; ++ MS_U8 os; ++ } MW; ++ struct _APP ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U8 id[4]; ++ MS_U8 quality; ++ MS_U8 version[4]; ++ MS_U8 time[6]; ++ MS_U8 changelist[8]; ++ MS_U8 reserve[3]; ++ } APP; ++} MSIF_Version; ++ ++typedef struct _MS_SW_VERSION_INFO ++{ ++ char UtopiaBspVersion[8]; //Utopia BSP Version ++ char MajorVersion[4]; //Major Version Number ++ char MinorVersion[4]; //Minor Version Number ++ char ChangeList_API[16]; //Sync Perforce Change List Number in API Folder ++ char ChangeList_DRV[16]; //Sync Perforce Change List Number in DRV Folder ++ char ChangeList_HAL[16]; //Sync Perforce Change List Number in HAL Folder ++ ++} MS_SW_VERSION_INFO; ++ ++/// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/sstar/flash_isp/infinity2/halSERFLASH.c b/drivers/sstar/flash_isp/infinity2/halSERFLASH.c +new file mode 100755 +index 000000000000..f33f8abc5e96 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity2/halSERFLASH.c +@@ -0,0 +1,5101 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++#include "registers.h" ++ ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ //#define CONFIG_FSP_READ_BDMA 1 ++ #define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ // #define CONFIG_FSP_WRITE_RIUOP 1 ++ #define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++// #define CONFIG_FSP_WRITE_BDMA 1 ++#endif ++ ++#if defined(CONFIG_FSP_READ_BDMA) && CONFIG_FSP_READ_BDMA == 1 ++#include "hal_bdma.h" ++#endif ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++ ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++#define BDMA_ALIGN (32) ++#define BDMA_SIZE_WARNING (128*1024+BDMA_ALIGN) //print message for unresonable size ++ ++//E_QUAD_MODE;//E_FAST_MODE; ++//const static SPI_READ_MODE gReadMode = E_QUAD_MODE; ++static MS_U32 u32BdmaSize = 64 * 1024 + BDMA_ALIGN;//default size ++static MSYS_DMEM_INFO mem_info; ++ ++SPI_READ_MODE gReadMode = E_FAST_MODE; ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(U32 u32DataSize); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++//chip section timeout ++ QSPI_WRITE(0x66, 0x000F); ++ QSPI_WRITE(0x67, 0x8000); ++ ++#ifdef CONFIG_FSP_WRITE_BDMA ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(u32BdmaSize); ++#endif ++#endif ++} ++ ++ ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++ ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ //MS_U8 u8Status0, u8Status1; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_WB)||(_hal_SERFLASH.u8MID == MID_GD)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++ ++#ifdef CONFIG_NOR_DUAL_AD_READ ++ gReadMode = E_DUAL_AD_MODE; ++#elif defined CONFIG_NOR_QUAD_AD_READ ++ gReadMode = E_QUAD_MODE; ++#else ++ gReadMode = E_FAST_MODE; ++#endif ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++ ++#endif ++ ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA)|| defined(CONFIG_FSP_WRITE_RIUOP_BRUST) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadRedirect(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ return TRUE; ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++#elif defined(CONFIG_FSP_READ_RIUOP) ++ Ret = HAL_FSP_Read(u32Addr, u32Size, pu8Data); ++#elif defined(CONFIG_FSP_READ_BDMA) ++ Ret = HAL_SERFLASH_ReadBdma(u32Addr, u32Size, pu8Data); ++#else ++#error "FPS READ" ++#endif ++ if(gReadMode > E_FAST_MODE && gReadMode != E_RIUISP_MODE) ++ { ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ } ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ case 10: ++ FSP_WRITE_MASK(REG_FSP_WDB10,REG_FSP_WDB10_DATA(u8Data),REG_FSP_WDB10_MASK); ++ break; ++ case 11: ++ FSP_WRITE_MASK(REG_FSP_WDB11,REG_FSP_WDB11_DATA(u8Data),REG_FSP_WDB11_MASK); ++ break; ++ case 12: ++ FSP_WRITE_MASK(REG_FSP_WDB12,REG_FSP_WDB12_DATA(u8Data),REG_FSP_WDB12_MASK); ++ break; ++ case 13: ++ FSP_WRITE_MASK(REG_FSP_WDB13,REG_FSP_WDB13_DATA(u8Data),REG_FSP_WDB13_MASK); ++ break; ++ case 14: ++ FSP_WRITE_MASK(REG_FSP_WDB14,REG_FSP_WDB14_DATA(u8Data),REG_FSP_WDB14_MASK); ++ break; ++ case 15: ++ FSP_WRITE_MASK(REG_FSP_WDB15,REG_FSP_WDB15_DATA(u8Data),REG_FSP_WDB15_MASK); ++ break; ++ case 16: ++ FSP_WRITE_MASK(REG_FSP_WDB16,REG_FSP_WDB16_DATA(u8Data),REG_FSP_WDB16_MASK); ++ break; ++ ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++} ++ ++void HAL_FSP_Exit(void) ++{ ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d\n", __FUNCTION__, bEnable)); ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ if(bEnable) ++ { ++ if((u8data & SF_SR_QUAD) == 0) { ++ u8data |= SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } else { ++ if((u8data & SF_SR_QUAD) != 0) { ++ u8data &= ~SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ bRet = HAL_FSP_ReadStatusReg(&u8Status); ++ if(bRet == FALSE) ++ return bRet; ++ ++ u8Status |= SF_SR_SRWD;//checked on WB/GD/MX ++//quad mode should be handled in read/write ++#if 0 //device dependent ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++#endif ++ //clear BP bits ++ if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ u8Status &= ~BITS(6:2,0x1F); ++ } ++ else {//check on WB/MX ++ u8Status &= ~BITS(5:2,0xF); ++ } ++ ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(U32 u32DataSize) ++{ ++ u32DataSize += BDMA_ALIGN; ++ if(pu8BDMA_virt != 0 && u32BdmaSize < u32DataSize) ++ { ++ int err; ++ err = msys_release_dmem(&mem_info); ++ if(u32DataSize >= BDMA_SIZE_WARNING) ++ { ++ pr_err("\n\n --->from %ld to %d\n\n", u32BdmaSize, u32DataSize); ++ } ++ if(0 != err) ++ { ++ printk("[Ser flash] Unable to free BDMA mem bus=0x%08X (err:%d)\n", (unsigned int)pu8BDMA_bus, err); ++ } ++ pu8BDMA_virt = 0; ++ } ++ if(pu8BDMA_virt != 0) ++ return; ++ mem_info.length = u32DataSize; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ u32BdmaSize = mem_info.length; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x len:0x%lX\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus, u32BdmaSize); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++MS_BOOL _HAL_PP_RIUOP_BURST(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ MS_U32 u32offs = u32Src_off; ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status = 0; ++ MS_U32 u32I, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U32 u32Size; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ //printk("PP 0x%x len:%d\r\n",(unsigned int)u32Dst_off, (unsigned int)u32Len); ++#if 1 ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++#endif ++ ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ //printk("\r\nwrite enable\r\n"); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write enable command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ /* We can't get what time the CS is pull high with hardware contorl. ++ Use software control output a level waveform */ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST | 0x2)); // SW control pull high CS ++ udelay(5); ++ ++ //write command ++ HAL_FSP_WriteBufs(0,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST)); // SW control pull down CS ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ u32quotient = (u32Len / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Len % REG_FSP_MAX_WRITEDATA_SIZE); ++ //printk("quotient:%lu, rem:%lu\r\n",u32quotient, u32remainder); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ { ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ } ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(MS_U8*)(u32offs+u32J)); ++ } ++ u32offs += u32Size; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ } ++ ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); // Disable SW control ++ ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ ++ ++ /*if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ CompareMemory(u32Src_off, u32Dst_off+BASE_FLASH_OFFSET, u32Len);*/ ++ ++ return bRet; ++} ++#endif ++ ++#ifdef CONFIG_FSP_WRITE_BDMA ++void _HAL_BDMA_INIT(void) ++{ ++ MSYS_DMEM_INFO mem_info; ++ ++ mem_info.length = 0x100; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ // Set source as MIU0 ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x3<<2)), 0X0000); //MIU0 as channel0 ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++#endif ++#if defined(CONFIG_FSP_WRITE_RIUOP_BRUST) || defined(CONFIG_FSP_WRITE_BDMA) ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++#endif ++ ++#endif +diff --git a/drivers/sstar/flash_isp/infinity2/halSERFLASH.h b/drivers/sstar/flash_isp/infinity2/halSERFLASH.h +new file mode 100755 +index 000000000000..cf114671584c +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity2/halSERFLASH.h +@@ -0,0 +1,171 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity2/regSERFLASH.h b/drivers/sstar/flash_isp/infinity2/regSERFLASH.h +new file mode 100755 +index 000000000000..bdbd89b5274e +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity2/regSERFLASH.h +@@ -0,0 +1,513 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_PMSLEEP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000E00) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++#define REG_FSP_WDB10 0x70 ++#define REG_FSP_WDB10_MASK BMASK(7:0) ++#define REG_FSP_WDB10_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB11 0x70 ++#define REG_FSP_WDB11_MASK BMASK(15:8) ++#define REG_FSP_WDB11_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB12 0x71 ++#define REG_FSP_WDB12_MASK BMASK(7:0) ++#define REG_FSP_WDB12_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB13 0x71 ++#define REG_FSP_WDB13_MASK BMASK(15:8) ++#define REG_FSP_WDB13_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB14 0x72 ++#define REG_FSP_WDB14_MASK BMASK(7:0) ++#define REG_FSP_WDB14_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB15 0x72 ++#define REG_FSP_WDB15_MASK BMASK(15:8) ++#define REG_FSP_WDB15_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB16 0x73 ++#define REG_FSP_WDB16_MASK BMASK(7:0) ++#define REG_FSP_WDB16_DATA(d) BITS(7:0, d) ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xF ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity2m/halSERFLASH.c b/drivers/sstar/flash_isp/infinity2m/halSERFLASH.c +new file mode 100755 +index 000000000000..e33437798e2d +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity2m/halSERFLASH.c +@@ -0,0 +1,5047 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++#include "registers.h" ++ ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ #define CONFIG_FSP_READ_BDMA 1 ++ //#define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++#endif ++ ++#if defined(CONFIG_FSP_READ_BDMA) && CONFIG_FSP_READ_BDMA == 1 ++#include "hal_bdma.h" ++#endif ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++#define PM_READ(addr) READ_WORD(BASE_REG_PMSLEEP_ADDR+ ((addr)<<2)) ++ ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++ ++#define BDMA_ALIGN (32) ++#define BDMA_SIZE_WARNING (128*1024+BDMA_ALIGN) //print message for unresonable size ++ ++//E_QUAD_MODE;//E_FAST_MODE; ++static SPI_READ_MODE gReadMode = E_QUAD_MODE; ++static MS_U32 u32BdmaSize = 64 * 1024 + BDMA_ALIGN;//default size ++static MSYS_DMEM_INFO mem_info; ++ ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(U32 u32DataSize); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ _HAL_BDMA_INIT(u32BdmaSize); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++MS_U32 PAL_SPI_GetClk(void) ++{ ++ MS_U16 reg; ++ MS_U32 u32Clk = 0; ++ reg = (PM_READ(0x20) >> 10) & 0xF; ++ printk("reg = %X\r\n", reg); ++ switch(reg) ++ { ++ case 1: ++ u32Clk = 27; ++ break; ++ case 4: ++ u32Clk = 54; ++ break; ++ case 5: ++ u32Clk = 72; ++ break; ++ case 6: ++ u32Clk = 86; ++ break; ++ case 7: ++ u32Clk = 108; ++ break; ++ default: ++ u32Clk = 0; ++ break; ++ } ++ return u32Clk; ++} ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ //printk("[FSP] Flash ID (0x%02X, 0x%02X, 0x%02X) \n",u8FlashId[0],u8FlashId[1],u8FlashId[2]); ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ if(gReadMode == E_QUAD_MODE && _hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(PAL_SPI_GetClk() > 54) ++ { ++ printk("MX supports QUAD mode only when CLK <= 54MHz\n"); ++ BUG(); ++ } ++ } ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ gReadMode = E_FAST_MODE; ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++// don't overwrite default setting ++// gReadMode = E_FAST_MODE; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++ ++#endif ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadRedirect(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadBdma(MS_U32 u32Offset, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_U32 u32AlignedOffset = (u32Offset) & (~0xF); ++ MS_U32 u32AlignedSize; ++ MS_U32 u32Delta; ++ ++ u32Delta = u32Offset - u32AlignedOffset; ++ u32AlignedSize = ((u32Size + u32Delta) + 0xF) & (~0xF); ++ { ++ HalBdmaParam_t tBdmaParam; ++ const u8 u8DmaCh = HAL_BDMA_CH0; ++ _HAL_BDMA_INIT(u32AlignedSize); ++ tBdmaParam.ePathSel = HAL_BDMA_SPI_TO_MIU0;//(pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MEM_TO_MIU0) : (HAL_BDMA_MEM_TO_MIU1); ++ tBdmaParam.bIntMode = 0; //0: polling mode ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = u32AlignedSize;//(u32Size + 0xF) & (~0xF); ++ tBdmaParam.pSrcAddr = (void*)u32AlignedOffset;//u32Offset; ++ tBdmaParam.pDstAddr = (void*)pu8BDMA_bus; ++ tBdmaParam.pfTxCbFunc = NULL;//msys_bdma_done; ++ tBdmaParam.u32Pattern = 0; ++ HalBdma_Initialize(u8DmaCh); ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("%s(0x%08X, %d, %p)b\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &tBdmaParam)) { ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("err\n")); ++ return FALSE; ++ } ++ Chip_Inv_Cache_Range(pu8BDMA_virt, u32AlignedSize);//u32Size); ++ //memcpy(pu8Data, (void*)pu8BDMA_virt, u32Size); ++ memcpy(pu8Data, (void*)pu8BDMA_virt + u32Delta, u32Size); ++ Ret = TRUE; ++ } ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ if(_hal_SERFLASH.u8MID == MID_25Q) ++ { ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ } ++ else ++ { ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ } ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++#elif defined(CONFIG_FSP_READ_RIUOP) ++ Ret = HAL_FSP_Read(u32Addr, u32Size, pu8Data); ++#elif defined(CONFIG_FSP_READ_BDMA) ++ Ret = HAL_SERFLASH_ReadBdma(u32Addr, u32Size, pu8Data); ++#else ++#error "FPS READ" ++#endif ++ if(gReadMode > E_FAST_MODE && gReadMode != E_RIUISP_MODE) ++ { ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ } ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++} ++ ++void HAL_FSP_Exit(void) ++{ ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d , _hal_SERFLASH.u8MID = 0x%X \n", __FUNCTION__, bEnable , _hal_SERFLASH.u8MID )); ++ ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ if(bEnable) ++ { ++ if((u8data & SF_SR_QUAD) == 0) { ++ u8data |= SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } else { ++ if((u8data & SF_SR_QUAD) != 0) { ++ u8data &= ~SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD||_hal_SERFLASH.u8MID == MID_ZB) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_ZB) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ //printk("%s pre = 0x%x\n", __func__ , u8data); ++ ++ if(bEnable) ++ { ++ if((u8data & SF_SR2_QUAD) == 0) { ++ u8data |= SF_SR2_QUAD; ++ bRet = HAL_FSP_WriteStatusReg2(u8data); ++ } ++ }else{ ++ if((u8data & SF_SR2_QUAD) != 0) { ++ u8data &= ~SF_SR2_QUAD; ++ bRet = HAL_FSP_WriteStatusReg2(u8data); ++ } ++ } ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ //printk("%s after = 0x%x\n", __func__ , u8data); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ bRet = HAL_FSP_ReadStatusReg(&u8Status); ++ if(bRet == FALSE) ++ return bRet; ++ ++ u8Status |= SF_SR_SRWD;//checked on WB/GD/MX ++//quad mode should be handled in read/write ++#if 0 //device dependent ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++#endif ++ //clear BP bits ++ if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ u8Status &= ~BITS(6:2,0x1F); ++ } ++ else {//check on WB/MX ++ u8Status &= ~BITS(5:2,0xF); ++ } ++ ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg2(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR2); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(U32 u32DataSize) ++{ ++ u32DataSize += BDMA_ALIGN; ++ if(pu8BDMA_virt != 0 && u32BdmaSize < u32DataSize) ++ { ++ int err; ++ err = msys_release_dmem(&mem_info); ++ if(u32DataSize >= BDMA_SIZE_WARNING) ++ { ++ pr_err("\n\n --->from %ld to %d\n\n", u32BdmaSize, u32DataSize); ++ } ++ if(0 != err) ++ { ++ printk("[Ser flash] Unable to free BDMA mem bus=0x%08X (err:%d)\n", (unsigned int)pu8BDMA_bus, err); ++ } ++ pu8BDMA_virt = 0; ++ } ++ if(pu8BDMA_virt != 0) ++ return; ++ mem_info.length = u32DataSize; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ u32BdmaSize = mem_info.length; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x len:0x%lX\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus, u32BdmaSize); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ _HAL_BDMA_INIT(u32Len); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ // Set source as MIU0 ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x3<<2)), 0X0000); //MIU0 as channel0 ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++ ++ ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++ ++#endif +diff --git a/drivers/sstar/flash_isp/infinity2m/halSERFLASH.h b/drivers/sstar/flash_isp/infinity2m/halSERFLASH.h +new file mode 100755 +index 000000000000..faa6b93413c0 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity2m/halSERFLASH.h +@@ -0,0 +1,172 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg2(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity2m/regSERFLASH.h b/drivers/sstar/flash_isp/infinity2m/regSERFLASH.h +new file mode 100755 +index 000000000000..9c90e0cc4147 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity2m/regSERFLASH.h +@@ -0,0 +1,495 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_PMSLEEP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000E00) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++#define SF_SR2_SRWD_MASK BMASK(7:7) ++ #define SF_SR2_QUAD BITS(1:1, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xA ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity3/halSERFLASH.c b/drivers/sstar/flash_isp/infinity3/halSERFLASH.c +new file mode 100755 +index 000000000000..014d1c3d6262 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity3/halSERFLASH.c +@@ -0,0 +1,4830 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++ ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ //#define CONFIG_FSP_READ_BDMA 1 ++ #define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++ ++#endif ++ ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++ ++ ++SPI_READ_MODE gReadMode = E_FAST_MODE; ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(void); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++ ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ //MS_U8 u8Status0, u8Status1; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++ gReadMode = E_FAST_MODE; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++ ++#endif ++ ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++ #elif defined(CONFIG_FSP_READ_RIUOP) ++ Ret = HAL_FSP_Read(u32Addr, u32Size, pu8Data); ++ #else ++ #error "FPS READ" ++ #endif ++ ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++} ++ ++void HAL_FSP_Exit(void) ++{ ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d\n", __FUNCTION__, bEnable)); ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(bEnable) ++ u8data = SF_SR_QUAD; ++ else ++ u8data = 0; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ u8Status = SF_SR_SRWD; ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(void) ++{ ++ MSYS_DMEM_INFO mem_info; ++ ++ mem_info.length = 0x100; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++ ++ ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++ ++#endif +diff --git a/drivers/sstar/flash_isp/infinity3/halSERFLASH.h b/drivers/sstar/flash_isp/infinity3/halSERFLASH.h +new file mode 100755 +index 000000000000..cf114671584c +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity3/halSERFLASH.h +@@ -0,0 +1,171 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity3/regSERFLASH.h b/drivers/sstar/flash_isp/infinity3/regSERFLASH.h +new file mode 100755 +index 000000000000..898f267a5ae9 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity3/regSERFLASH.h +@@ -0,0 +1,491 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xA ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity5/halSERFLASH.c b/drivers/sstar/flash_isp/infinity5/halSERFLASH.c +new file mode 100755 +index 000000000000..ee7ca11977df +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity5/halSERFLASH.c +@@ -0,0 +1,4814 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++ ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ //#define CONFIG_FSP_READ_BDMA 1 ++ #define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++ ++#endif ++ ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (_stamp = jiffies) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 6000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++ ++ ++SPI_READ_MODE gReadMode = E_FAST_MODE; ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(void); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime(unsigned long tPreTime, MS_U32 u32Fac) ++{ ++ if (time_after_eq(jiffies, (tPreTime + u32Fac))) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ unsigned long ts; ++ ++ SER_FLASH_TIME(ts); ++ do { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ unsigned long ts; ++ ++ SER_FLASH_TIME(ts); ++ do { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ unsigned long ts; ++ ++ SER_FLASH_TIME(ts); ++ do { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ unsigned long ts; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ SER_FLASH_TIME(ts); ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++ ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ //MS_U8 u8Status0, u8Status1; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++ gReadMode = E_FAST_MODE; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++ ++#endif ++ ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++ #elif defined(CONFIG_FSP_READ_RIUOP) ++ Ret = HAL_FSP_Read(u32Addr, u32Size, pu8Data); ++ #else ++ #error "FPS READ" ++ #endif ++ ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ unsigned long ts; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(ts); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(ts, msecs_to_jiffies(u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ unsigned long ts; ++ ++ SER_FLASH_TIME(ts); ++ do ++ { ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++} ++ ++void HAL_FSP_Exit(void) ++{ ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d\n", __FUNCTION__, bEnable)); ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(bEnable) ++ u8data = SF_SR_QUAD; ++ else ++ u8data = 0; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ u8Status = SF_SR_SRWD; ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(void) ++{ ++ MSYS_DMEM_INFO mem_info; ++ ++ mem_info.length = 0x100; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ unsigned long ts; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(ts); ++ do ++ { ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timespec time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long ts; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ // Set source as MIU0 ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x3<<2)), 0X0000); //MIU0 as channel0 ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ SER_FLASH_TIME(ts); ++ do { ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(ts, MAX_READY_WAIT_JIFFIES)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++ ++ ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++ ++#endif +diff --git a/drivers/sstar/flash_isp/infinity5/halSERFLASH.h b/drivers/sstar/flash_isp/infinity5/halSERFLASH.h +new file mode 100644 +index 000000000000..cf114671584c +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity5/halSERFLASH.h +@@ -0,0 +1,171 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity5/regSERFLASH.h b/drivers/sstar/flash_isp/infinity5/regSERFLASH.h +new file mode 100755 +index 000000000000..898f267a5ae9 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity5/regSERFLASH.h +@@ -0,0 +1,491 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xA ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity6/halSERFLASH.c b/drivers/sstar/flash_isp/infinity6/halSERFLASH.c +new file mode 100755 +index 000000000000..a32135ba516a +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6/halSERFLASH.c +@@ -0,0 +1,5244 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++#include "registers.h" ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ #define CONFIG_FSP_READ_BDMA 1 ++ //#define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++#endif ++ ++#if defined(CONFIG_FSP_READ_BDMA) && CONFIG_FSP_READ_BDMA == 1 ++#include "hal_bdma.h" ++#endif ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++#define PM_READ(addr) READ_WORD(BASE_REG_PMSLEEP_ADDR+ ((addr)<<2)) ++ ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++#define BDMA_ALIGN (32) ++#define BDMA_SIZE_WARNING (128*1024+BDMA_ALIGN) //print message for unresonable size ++ ++//E_QUAD_MODE;//E_FAST_MODE; ++static SPI_READ_MODE gReadMode = E_QUAD_MODE; ++static MS_U32 u32BdmaSize = 64 * 1024 + BDMA_ALIGN;//default size ++static MSYS_DMEM_INFO mem_info; ++ ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(U32 u32DataSize); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ //chip section timeout ++ QSPI_WRITE(0x66, 0x000F); ++ QSPI_WRITE(0x67, 0x8000); ++ ++ _HAL_BDMA_INIT(u32BdmaSize); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++MS_U32 PAL_SPI_GetClk(void) ++{ ++ MS_U16 reg; ++ MS_U32 u32Clk = 0; ++ reg = (PM_READ(0x20) >> 10) & 0xF; ++ printk("reg = %X\r\n", reg); ++ switch(reg) ++ { ++ case 1: ++ u32Clk = 27; ++ break; ++ case 4: ++ u32Clk = 54; ++ break; ++ case 5: ++ u32Clk = 72; ++ break; ++ case 6: ++ u32Clk = 86; ++ break; ++ case 7: ++ u32Clk = 108; ++ break; ++ default: ++ u32Clk = 0; ++ break; ++ } ++ return u32Clk; ++} ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ //printk("[FSP] Flash ID (0x%02X, 0x%02X, 0x%02X) \n",u8FlashId[0],u8FlashId[1],u8FlashId[2]); ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ if(gReadMode == E_QUAD_MODE && _hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(PAL_SPI_GetClk() > 54) ++ { ++ printk("MX supports QUAD mode only when CLK <= 54MHz\n"); ++ BUG(); ++ } ++ } ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ gReadMode = E_FAST_MODE; ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++// don't overwrite default setting ++// gReadMode = E_FAST_MODE; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++#endif ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) || defined(CONFIG_FSP_WRITE_RIUOP_BRUST) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadRedirect(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_READ_BDMA ++MS_BOOL HAL_SERFLASH_ReadBdma(MS_U32 u32Offset, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_U32 u32AlignedOffset = (u32Offset) & (~0xF); ++ MS_U32 u32AlignedSize; ++ MS_U32 u32Delta; ++ ++ u32Delta = u32Offset - u32AlignedOffset; ++ u32AlignedSize = ((u32Size + u32Delta) + 0xF) & (~0xF); ++ { ++ HalBdmaParam_t tBdmaParam; ++ const u8 u8DmaCh = HAL_BDMA_CH0; ++ _HAL_BDMA_INIT(u32AlignedSize); ++ tBdmaParam.ePathSel = HAL_BDMA_SPI_TO_MIU0;//(pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MEM_TO_MIU0) : (HAL_BDMA_MEM_TO_MIU1); ++ tBdmaParam.bIntMode = 0; //0: polling mode ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = u32AlignedSize;//(u32Size + 0xF) & (~0xF); ++ tBdmaParam.pSrcAddr = (void*)u32AlignedOffset;//u32Offset; ++ tBdmaParam.pDstAddr = (void*)pu8BDMA_bus; ++ tBdmaParam.pfTxCbFunc = NULL;//msys_bdma_done; ++ tBdmaParam.u32Pattern = 0; ++ HalBdma_Initialize(u8DmaCh); ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("%s(0x%08X, %d, %p)b\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &tBdmaParam)) { ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("err\n")); ++ return FALSE; ++ } ++ Chip_Inv_Cache_Range(pu8BDMA_virt, u32AlignedSize);//u32Size); ++ //memcpy(pu8Data, (void*)pu8BDMA_virt, u32Size); ++ memcpy(pu8Data, (void*)pu8BDMA_virt + u32Delta, u32Size); ++ Ret = TRUE; ++ } ++ return TRUE; ++} ++#endif ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++#elif defined(CONFIG_FSP_READ_RIUOP) ++ Ret = HAL_FSP_Read(u32Addr, u32Size, pu8Data); ++#elif defined(CONFIG_FSP_READ_BDMA) ++ Ret = HAL_SERFLASH_ReadBdma(u32Addr, u32Size, pu8Data); ++#else ++#error "FPS READ" ++#endif ++ if(gReadMode > E_FAST_MODE && gReadMode != E_RIUISP_MODE) ++ { ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ } ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ case 10: ++ FSP_WRITE_MASK(REG_FSP_WDB10,REG_FSP_WDB10_DATA(u8Data),REG_FSP_WDB10_MASK); ++ break; ++ case 11: ++ FSP_WRITE_MASK(REG_FSP_WDB11,REG_FSP_WDB11_DATA(u8Data),REG_FSP_WDB11_MASK); ++ break; ++ case 12: ++ FSP_WRITE_MASK(REG_FSP_WDB12,REG_FSP_WDB12_DATA(u8Data),REG_FSP_WDB12_MASK); ++ break; ++ case 13: ++ FSP_WRITE_MASK(REG_FSP_WDB13,REG_FSP_WDB13_DATA(u8Data),REG_FSP_WDB13_MASK); ++ break; ++ case 14: ++ FSP_WRITE_MASK(REG_FSP_WDB14,REG_FSP_WDB14_DATA(u8Data),REG_FSP_WDB14_MASK); ++ break; ++ case 15: ++ FSP_WRITE_MASK(REG_FSP_WDB15,REG_FSP_WDB15_DATA(u8Data),REG_FSP_WDB15_MASK); ++ break; ++ case 16: ++ FSP_WRITE_MASK(REG_FSP_WDB16,REG_FSP_WDB16_DATA(u8Data),REG_FSP_WDB16_MASK); ++ break; ++ ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++} ++ ++void HAL_FSP_Exit(void) ++{ ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data, u8data2; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d , _hal_SERFLASH.u8MID = 0x%X \n", __FUNCTION__, bEnable , _hal_SERFLASH.u8MID )); ++ ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ if(bEnable) ++ { ++ if((u8data & SF_SR_QUAD) == 0) { ++ u8data |= SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } else { ++ if((u8data & SF_SR_QUAD) != 0) { ++ u8data &= ~SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_ZB) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ //printk("%s pre = 0x%x\n", __func__ , u8data); ++ ++ if(bEnable) ++ { ++ if((u8data & SF_SR2_QUAD) == 0) { ++ u8data |= SF_SR2_QUAD; ++ bRet = HAL_FSP_WriteStatusReg2(u8data); ++ } ++ }else{ ++ if((u8data & SF_SR2_QUAD) != 0) { ++ u8data &= ~SF_SR2_QUAD; ++ bRet = HAL_FSP_WriteStatusReg2(u8data); ++ } ++ } ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ //printk("%s after = 0x%x\n", __func__ , u8data); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_XTX ) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ //printk("%s pre CMD_RDSR = 0x%x \n", __func__ , u8data); ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data2); ++ //printk("%s pre CMD_RDSR2 = 0x%x \n", __func__ , u8data2); ++ ++ if(bEnable) ++ { ++ u8data2 |= 0x02; ++ bRet = HAL_FSP_WriteStatusReg( u8data | u8data2<<8); ++ } ++ else ++ { ++ u8data2 &= (~0x02); ++ bRet = HAL_FSP_WriteStatusReg( u8data | u8data2<<8); ++ } ++ ++ //bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ //printk("%s after CMD_RDSR = 0x%x\n", __func__ , u8data); ++ ++ //bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data2); ++ //printk("%s after CMD_RDSR2 = 0x%x\n", __func__ , u8data2); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status,u8Status2; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ bRet = HAL_FSP_ReadStatusReg(&u8Status); ++ if(bRet == FALSE) ++ return bRet; ++ ++ u8Status |= SF_SR_SRWD;//checked on WB/GD/MX ++//quad mode should be handled in read/write ++#if 0 //device dependent ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++#endif ++ ++ //clear BP bits ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u8MID == MID_XTX) || (_hal_SERFLASH.u8MID == MID_WUHAN)) ++ { ++ u8Status &= ~BITS(6:2,0x1F); ++ } ++ else {//check on WB/MX ++ u8Status &= ~BITS(5:2,0xF); ++ } ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++#if 0 ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++#else ++ if(_hal_SERFLASH.u8MID != MID_XTX) ++ { ++ bRet &= HAL_FSP_WriteStatus(SPI_CMD_WRSR, 1, &u8Status); ++ } ++ else ++ { ++ //bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8Status); // escape this by u8Status value has modified with upper clear BP bits operations ++ //printk("%s pre CMD_RDSR = 0x%x \n", __func__ , u8Status); ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8Status2); ++ //printk("%s pre CMD_RDSR2 = 0x%x \n", __func__ , u8Status2); ++ ++ bRet &= HAL_FSP_WriteStatusReg(u8Status | u8Status2<<8); ++ } ++#endif ++ ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg2(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR2); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(U32 u32DataSize) ++{ ++ u32DataSize += BDMA_ALIGN; ++ if(pu8BDMA_virt != 0 && u32BdmaSize < u32DataSize) ++ { ++ int err; ++ err = msys_release_dmem(&mem_info); ++ if(u32DataSize >= BDMA_SIZE_WARNING) ++ { ++ pr_err("\n\n --->from %ld to %d\n\n", u32BdmaSize, u32DataSize); ++ } ++ if(0 != err) ++ { ++ printk("[Ser flash] Unable to free BDMA mem bus=0x%08X (err:%d)\n", (unsigned int)pu8BDMA_bus, err); ++ } ++ pu8BDMA_virt = 0; ++ } ++ if(pu8BDMA_virt != 0) ++ return; ++ mem_info.length = u32DataSize; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ u32BdmaSize = mem_info.length; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x len:0x%lX\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus, u32BdmaSize); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++MS_BOOL _HAL_PP_RIUOP_BURST(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ MS_U32 u32offs = u32Src_off; ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status = 0; ++ MS_U32 u32I, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U32 u32Size; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ //printk("PP 0x%x len:%d\r\n",(unsigned int)u32Dst_off, (unsigned int)u32Len); ++#if 1 ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++#endif ++ ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ //printk("\r\nwrite enable\r\n"); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write enable command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ /* We can't get what time the CS is pull high with hardware contorl. ++ Use software control output a level waveform */ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST | 0x2)); // SW control pull high CS ++ udelay(5); ++ ++ //write command ++ HAL_FSP_WriteBufs(0,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST)); // SW control pull down CS ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ u32quotient = (u32Len / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Len % REG_FSP_MAX_WRITEDATA_SIZE); ++ //printk("quotient:%lu, rem:%lu\r\n",u32quotient, u32remainder); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ { ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ } ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(MS_U8*)(u32offs+u32J)); ++ } ++ u32offs += u32Size; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ } ++ ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); // Disable SW control ++ ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ ++ ++ /*if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ CompareMemory(u32Src_off, u32Dst_off+BASE_FLASH_OFFSET, u32Len);*/ ++ ++ return bRet; ++} ++#endif ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ _HAL_BDMA_INIT(u32Len); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x3<<2)), 0x8000); //set channel0 to MIU ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)&0x0FFF); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++#endif ++#if defined(CONFIG_FSP_WRITE_RIUOP_BRUST) || defined(CONFIG_FSP_WRITE_BDMA) ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++#endif +diff --git a/drivers/sstar/flash_isp/infinity6/halSERFLASH.h b/drivers/sstar/flash_isp/infinity6/halSERFLASH.h +new file mode 100755 +index 000000000000..faa6b93413c0 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6/halSERFLASH.h +@@ -0,0 +1,172 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg2(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity6/regSERFLASH.h b/drivers/sstar/flash_isp/infinity6/regSERFLASH.h +new file mode 100755 +index 000000000000..a905f24fa190 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6/regSERFLASH.h +@@ -0,0 +1,516 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_PMSLEEP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000E00) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++#define SF_SR2_SRWD_MASK BMASK(7:7) ++ #define SF_SR2_QUAD BITS(1:1, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++#define REG_FSP_WDB10 0x70 ++#define REG_FSP_WDB10_MASK BMASK(7:0) ++#define REG_FSP_WDB10_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB11 0x70 ++#define REG_FSP_WDB11_MASK BMASK(15:8) ++#define REG_FSP_WDB11_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB12 0x71 ++#define REG_FSP_WDB12_MASK BMASK(7:0) ++#define REG_FSP_WDB12_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB13 0x71 ++#define REG_FSP_WDB13_MASK BMASK(15:8) ++#define REG_FSP_WDB13_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB14 0x72 ++#define REG_FSP_WDB14_MASK BMASK(7:0) ++#define REG_FSP_WDB14_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB15 0x72 ++#define REG_FSP_WDB15_MASK BMASK(15:8) ++#define REG_FSP_WDB15_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB16 0x73 ++#define REG_FSP_WDB16_MASK BMASK(7:0) ++#define REG_FSP_WDB16_DATA(d) BITS(7:0, d) ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xF ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity6b0/halSERFLASH.c b/drivers/sstar/flash_isp/infinity6b0/halSERFLASH.c +new file mode 100755 +index 000000000000..1d189c8eb618 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6b0/halSERFLASH.c +@@ -0,0 +1,5313 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++#include "registers.h" ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ #define CONFIG_FSP_READ_BDMA 1 ++ //#define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++#endif ++ ++#if defined(CONFIG_FSP_READ_BDMA) && CONFIG_FSP_READ_BDMA == 1 ++#include "hal_bdma.h" ++#endif ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++#define PM_READ(addr) READ_WORD(BASE_REG_PMSLEEP_ADDR+ ((addr)<<2)) ++ ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++#define BDMA_ALIGN (32) ++#define BDMA_SIZE_WARNING (128*1024+BDMA_ALIGN) //print message for unresonable size ++ ++//E_QUAD_MODE;//E_FAST_MODE; ++static SPI_READ_MODE gReadMode = E_QUAD_MODE; ++static MS_U32 u32BdmaSize = 64 * 1024 + BDMA_ALIGN;//default size ++static MSYS_DMEM_INFO mem_info; ++ ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(U32 u32DataSize); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ //chip section timeout ++ QSPI_WRITE(0x66, 0x000F); ++ QSPI_WRITE(0x67, 0x8000); ++ ++ _HAL_BDMA_INIT(u32BdmaSize); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++MS_U32 PAL_SPI_GetClk(void) ++{ ++ MS_U16 reg; ++ MS_U32 u32Clk = 0; ++ reg = (PM_READ(0x20) >> 10) & 0xF; ++ printk("reg = %X\r\n", reg); ++ switch(reg) ++ { ++ case 1: ++ u32Clk = 27; ++ break; ++ case 4: ++ u32Clk = 54; ++ break; ++ case 5: ++ u32Clk = 72; ++ break; ++ case 6: ++ u32Clk = 86; ++ break; ++ case 7: ++ u32Clk = 108; ++ break; ++ default: ++ u32Clk = 0; ++ break; ++ } ++ return u32Clk; ++} ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ //printk("[FSP] Flash ID (0x%02X, 0x%02X, 0x%02X) \n",u8FlashId[0],u8FlashId[1],u8FlashId[2]); ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)||(_hal_SERFLASH.u8MID == MID_WB)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ if(gReadMode == E_QUAD_MODE && _hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(PAL_SPI_GetClk() > 54) ++ { ++ printk("MX supports QUAD mode only when CLK <= 54MHz\n"); ++ BUG(); ++ } ++ } ++ if(_hal_SERFLASH.u8MID == MID_25Q) ++ { ++ gReadMode = E_FAST_MODE; //support FAST_mode ++ } ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ gReadMode = E_FAST_MODE; ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++// don't overwrite default setting ++// gReadMode = E_FAST_MODE; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++#endif ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) || defined(CONFIG_FSP_WRITE_RIUOP_BRUST) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadRedirect(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_READ_BDMA ++MS_BOOL HAL_SERFLASH_ReadBdma(MS_U32 u32Offset, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_U32 u32AlignedOffset = (u32Offset) & (~0xF); ++ MS_U32 u32AlignedSize; ++ MS_U32 u32Delta; ++ ++ u32Delta = u32Offset - u32AlignedOffset; ++ u32AlignedSize = ((u32Size + u32Delta) + 0xF) & (~0xF); ++ { ++ HalBdmaParam_t tBdmaParam; ++ const u8 u8DmaCh = HAL_BDMA_CH0; ++ _HAL_BDMA_INIT(u32AlignedSize); ++ tBdmaParam.ePathSel = HAL_BDMA_SPI_TO_MIU0;//(pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MEM_TO_MIU0) : (HAL_BDMA_MEM_TO_MIU1); ++ tBdmaParam.bIntMode = 0; //0: polling mode ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = u32AlignedSize;//(u32Size + 0xF) & (~0xF); ++ tBdmaParam.pSrcAddr = (void*)u32AlignedOffset;//u32Offset; ++ tBdmaParam.pDstAddr = (void*)pu8BDMA_bus; ++ tBdmaParam.pfTxCbFunc = NULL;//msys_bdma_done; ++ tBdmaParam.u32Pattern = 0; ++ HalBdma_Initialize(u8DmaCh); ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("%s(0x%08X, %d, %p)b\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &tBdmaParam)) { ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("err\n")); ++ return FALSE; ++ } ++ Chip_Inv_Cache_Range(pu8BDMA_virt, u32AlignedSize);//u32Size); ++ //memcpy(pu8Data, (void*)pu8BDMA_virt, u32Size); ++ memcpy(pu8Data, (void*)pu8BDMA_virt + u32Delta, u32Size); ++ Ret = TRUE; ++ } ++ return TRUE; ++} ++#endif ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++#elif defined(CONFIG_FSP_READ_RIUOP) || defined(CONFIG_FSP_READ_BDMA) ++ { ++ MS_U8 u8EAR_min = u32Addr >> 24; ++ MS_U8 u8EAR_max = (u32Addr + u32Size) >> 24; ++ MS_U32 u32ReadSize = 0; ++ //printk("u8EAR_min %d u8EAR_max %d\n",u8EAR_min,u8EAR_max); ++ while(u8EAR_min <= u8EAR_max) ++ { ++ u32ReadSize = ((u8EAR_min+1) << 24) - u32Addr; ++ u32ReadSize = (u32ReadSize > u32Size) ? u32Size : u32ReadSize; ++ if(u8EAR_min != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR_min); ++ } ++ if(u32ReadSize) ++ { ++ #ifdef CONFIG_FSP_READ_RIUOP ++ Ret = HAL_FSP_Read(u32Addr, u32ReadSize, pu8Data); ++ #else ++ Ret = HAL_SERFLASH_ReadBdma(u32Addr, u32ReadSize, pu8Data); ++ #endif ++ } ++ u32Addr += u32ReadSize; ++ u32Size -= u32ReadSize; ++ pu8Data += u32ReadSize; ++ u8EAR_min++; ++ } ++ } ++ ++#else ++#error "FPS READ" ++#endif ++ if(gReadMode > E_FAST_MODE && gReadMode != E_RIUISP_MODE) ++ { ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ } ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ case 10: ++ FSP_WRITE_MASK(REG_FSP_WDB10,REG_FSP_WDB10_DATA(u8Data),REG_FSP_WDB10_MASK); ++ break; ++ case 11: ++ FSP_WRITE_MASK(REG_FSP_WDB11,REG_FSP_WDB11_DATA(u8Data),REG_FSP_WDB11_MASK); ++ break; ++ case 12: ++ FSP_WRITE_MASK(REG_FSP_WDB12,REG_FSP_WDB12_DATA(u8Data),REG_FSP_WDB12_MASK); ++ break; ++ case 13: ++ FSP_WRITE_MASK(REG_FSP_WDB13,REG_FSP_WDB13_DATA(u8Data),REG_FSP_WDB13_MASK); ++ break; ++ case 14: ++ FSP_WRITE_MASK(REG_FSP_WDB14,REG_FSP_WDB14_DATA(u8Data),REG_FSP_WDB14_MASK); ++ break; ++ case 15: ++ FSP_WRITE_MASK(REG_FSP_WDB15,REG_FSP_WDB15_DATA(u8Data),REG_FSP_WDB15_MASK); ++ break; ++ case 16: ++ FSP_WRITE_MASK(REG_FSP_WDB16,REG_FSP_WDB16_DATA(u8Data),REG_FSP_WDB16_MASK); ++ break; ++ ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++#if 0 ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++#endif ++} ++ ++void HAL_FSP_Exit(void) ++{ ++#if 0 ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data, u8data2; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d , _hal_SERFLASH.u8MID = 0x%X \n", __FUNCTION__, bEnable , _hal_SERFLASH.u8MID )); ++ ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ if(bEnable) ++ { ++ if((u8data & SF_SR_QUAD) == 0) { ++ u8data |= SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } else { ++ if((u8data & SF_SR_QUAD) != 0) { ++ u8data &= ~SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_ZB) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ //printk("%s pre = 0x%x\n", __func__ , u8data); ++ ++ if(bEnable) ++ { ++ if((u8data & SF_SR2_QUAD) == 0) { ++ u8data |= SF_SR2_QUAD; ++ bRet = HAL_FSP_WriteStatusReg2(u8data); ++ } ++ }else{ ++ if((u8data & SF_SR2_QUAD) != 0) { ++ u8data &= ~SF_SR2_QUAD; ++ bRet = HAL_FSP_WriteStatusReg2(u8data); ++ } ++ } ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ //printk("%s after = 0x%x\n", __func__ , u8data); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_XTX ) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ //printk("%s pre CMD_RDSR = 0x%x \n", __func__ , u8data); ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data2); ++ //printk("%s pre CMD_RDSR2 = 0x%x \n", __func__ , u8data2); ++ ++ if(bEnable) ++ { ++ u8data2 |= 0x02; ++ bRet = HAL_FSP_WriteStatusReg( u8data | u8data2<<8); ++ } ++ else ++ { ++ u8data2 &= (~0x02); ++ bRet = HAL_FSP_WriteStatusReg( u8data | u8data2<<8); ++ } ++ ++ //bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ //printk("%s after CMD_RDSR = 0x%x\n", __func__ , u8data); ++ ++ //bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data2); ++ //printk("%s after CMD_RDSR2 = 0x%x\n", __func__ , u8data2); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_NM) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8data); ++ ++ if(bEnable) ++ { ++ if((u8data & BIT2) == 0) { ++ u8data |= BIT2; ++ bRet = HAL_FSP_WriteStatus(SPI_CMD_WRSR2, 1, &u8data); ++ } ++ } ++ else ++ { ++ if((u8data & BIT2) != 0) { ++ u8data &= ~BIT2; ++ bRet = HAL_FSP_WriteStatus(SPI_CMD_WRSR2, 1, &u8data); ++ } ++ } ++ } ++ else if(_hal_SERFLASH.u8MID == MID_EON) ++ { ++ MS_U8 u8status[1]={0xff}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(SPI_CMD_WRSR2, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, u8status); ++ //printk("[FSP] WB u8data:0x%x status2:0x%x\n",u8data, u8status[0]); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] WB status2:0x%x\n",u8status[0])); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status,u8Status2; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ bRet = HAL_FSP_ReadStatusReg(&u8Status); ++ if(bRet == FALSE) ++ return bRet; ++ ++ u8Status |= SF_SR_SRWD;//checked on WB/GD/MX ++//quad mode should be handled in read/write ++#if 0 //device dependent ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++#endif ++ ++ //clear BP bits ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u8MID == MID_XTX) || (_hal_SERFLASH.u8MID == MID_WUHAN)) ++ { ++ u8Status &= ~BITS(6:2,0x1F); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_NM) ++ { ++ u8Status &= ~BITS(7:2,0x3F); ++ } ++ else {//check on WB/MX ++ u8Status &= ~BITS(5:2,0xF); ++ } ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++#if 0 ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++#else ++ if(_hal_SERFLASH.u8MID != MID_XTX) ++ { ++ bRet &= HAL_FSP_WriteStatus(SPI_CMD_WRSR, 1, &u8Status); ++ } ++ else ++ { ++ //bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8Status); // escape this by u8Status value has modified with upper clear BP bits operations ++ //printk("%s pre CMD_RDSR = 0x%x \n", __func__ , u8Status); ++ ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR2, 1, &u8Status2); ++ //printk("%s pre CMD_RDSR2 = 0x%x \n", __func__ , u8Status2); ++ ++ bRet &= HAL_FSP_WriteStatusReg(u8Status | u8Status2<<8); ++ } ++#endif ++ ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg2(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR2); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(U32 u32DataSize) ++{ ++ u32DataSize += BDMA_ALIGN; ++ if(pu8BDMA_virt != 0 && u32BdmaSize < u32DataSize) ++ { ++ int err; ++ err = msys_release_dmem(&mem_info); ++ if(u32DataSize >= BDMA_SIZE_WARNING) ++ { ++ pr_err("\n\n --->from %ld to %d\n\n", u32BdmaSize, u32DataSize); ++ } ++ if(0 != err) ++ { ++ printk("[Ser flash] Unable to free BDMA mem bus=0x%08X (err:%d)\n", (unsigned int)pu8BDMA_bus, err); ++ } ++ pu8BDMA_virt = 0; ++ } ++ if(pu8BDMA_virt != 0) ++ return; ++ mem_info.length = u32DataSize; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ u32BdmaSize = mem_info.length; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x len:0x%lX\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus, u32BdmaSize); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++MS_BOOL _HAL_PP_RIUOP_BURST(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ MS_U32 u32offs = u32Src_off; ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status = 0; ++ MS_U32 u32I, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U32 u32Size; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ //printk("PP 0x%x len:%d\r\n",(unsigned int)u32Dst_off, (unsigned int)u32Len); ++#if 1 ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++#endif ++ ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ //printk("\r\nwrite enable\r\n"); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write enable command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ /* We can't get what time the CS is pull high with hardware contorl. ++ Use software control output a level waveform */ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST | 0x2)); // SW control pull high CS ++ udelay(5); ++ ++ //write command ++ HAL_FSP_WriteBufs(0,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST)); // SW control pull down CS ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ u32quotient = (u32Len / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Len % REG_FSP_MAX_WRITEDATA_SIZE); ++ //printk("quotient:%lu, rem:%lu\r\n",u32quotient, u32remainder); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ { ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ } ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(MS_U8*)(u32offs+u32J)); ++ } ++ u32offs += u32Size; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ } ++ ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); // Disable SW control ++ ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ ++ ++ /*if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ CompareMemory(u32Src_off, u32Dst_off+BASE_FLASH_OFFSET, u32Len);*/ ++ ++ return bRet; ++} ++#endif ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ _HAL_BDMA_INIT(u32Len); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x3<<2)), 0x8000); //set channel0 to MIU ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)&0x0FFF); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++#endif ++#if defined(CONFIG_FSP_WRITE_RIUOP_BRUST) || defined(CONFIG_FSP_WRITE_BDMA) ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++#endif +diff --git a/drivers/sstar/flash_isp/infinity6b0/halSERFLASH.h b/drivers/sstar/flash_isp/infinity6b0/halSERFLASH.h +new file mode 100755 +index 000000000000..faa6b93413c0 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6b0/halSERFLASH.h +@@ -0,0 +1,172 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg2(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity6b0/regSERFLASH.h b/drivers/sstar/flash_isp/infinity6b0/regSERFLASH.h +new file mode 100755 +index 000000000000..a905f24fa190 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6b0/regSERFLASH.h +@@ -0,0 +1,516 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_PMSLEEP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000E00) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++#define SF_SR2_SRWD_MASK BMASK(7:7) ++ #define SF_SR2_QUAD BITS(1:1, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++#define REG_FSP_WDB10 0x70 ++#define REG_FSP_WDB10_MASK BMASK(7:0) ++#define REG_FSP_WDB10_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB11 0x70 ++#define REG_FSP_WDB11_MASK BMASK(15:8) ++#define REG_FSP_WDB11_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB12 0x71 ++#define REG_FSP_WDB12_MASK BMASK(7:0) ++#define REG_FSP_WDB12_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB13 0x71 ++#define REG_FSP_WDB13_MASK BMASK(15:8) ++#define REG_FSP_WDB13_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB14 0x72 ++#define REG_FSP_WDB14_MASK BMASK(7:0) ++#define REG_FSP_WDB14_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB15 0x72 ++#define REG_FSP_WDB15_MASK BMASK(15:8) ++#define REG_FSP_WDB15_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB16 0x73 ++#define REG_FSP_WDB16_MASK BMASK(7:0) ++#define REG_FSP_WDB16_DATA(d) BITS(7:0, d) ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xF ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity6e/halSERFLASH.c b/drivers/sstar/flash_isp/infinity6e/halSERFLASH.c +new file mode 100755 +index 000000000000..4e9ff74bbcd4 +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6e/halSERFLASH.c +@@ -0,0 +1,5178 @@ ++/* ++* halSERFLASH.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++#include "registers.h" ++ ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ #define CONFIG_FSP_READ_BDMA 1 ++ //#define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++#endif ++ ++#if defined(CONFIG_FSP_READ_BDMA) && CONFIG_FSP_READ_BDMA == 1 ++#include "hal_bdma.h" ++#endif ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define CHIP_READ(addr) READ_WORD(BASE_REG_CHIPTOP_ADDR + (addr<<2)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++#define PM_READ(addr) READ_WORD(BASE_REG_PMSLEEP_ADDR+ ((addr)<<2)) ++ ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++#define BDMA_ALIGN (32) ++#define BDMA_SIZE_WARNING (128*1024+BDMA_ALIGN) //print message for unresonable size ++ ++//E_QUAD_MODE;//E_FAST_MODE; ++const static SPI_READ_MODE gReadMode = E_FAST_MODE; ++static MS_U32 u32BdmaSize = 64 * 1024 + BDMA_ALIGN;//default size ++static MSYS_DMEM_INFO mem_info; ++ ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(U32 u32DataSize); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_NORMOL_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_DUALREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_FAST_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_FAST_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++ MS_U8 u8BoundID; ++ ++ _hal_isp.u32IspBaseAddr = BASE_REG_ISP_ADDR; ++ ++ //chekc boundID to select pm-spi or non-pm spi ++ u8BoundID = 0x10;//CHIP_READ(0x48) & CHIP_BOUND_TYPES; ++ switch(u8BoundID) ++ { ++ case CHIP_BOUND_QFN88: ++ _hal_isp.u32FspBaseAddr = BASE_REG_FSP_PM_ADDR; ++ _hal_isp.u32QspiBaseAddr = BASE_REG_QSPI_PM_ADDR; ++ break; ++ default: ++ _hal_isp.u32FspBaseAddr = BASE_REG_FSP_ADDR; ++ _hal_isp.u32QspiBaseAddr = BASE_REG_QSPI_ADDR; ++ break; ++ } ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ // QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ //chip section timeout ++ QSPI_WRITE(0x66, 0x000F); ++ QSPI_WRITE(0x67, 0x8000); ++ ++ _HAL_BDMA_INIT(u32BdmaSize); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++MS_U32 PAL_SPI_GetClk(void) ++{ ++ MS_U16 reg; ++ MS_U32 u32Clk = 0; ++ reg = (PM_READ(0x20) >> 10) & 0xF; ++ printk("reg = %X\r\n", reg); ++ switch(reg) ++ { ++ case 1: ++ u32Clk = 27; ++ break; ++ case 4: ++ u32Clk = 54; ++ break; ++ case 5: ++ u32Clk = 72; ++ break; ++ case 6: ++ u32Clk = 86; ++ break; ++ case 7: ++ u32Clk = 108; ++ break; ++ default: ++ u32Clk = 0; ++ break; ++ } ++ return u32Clk; ++} ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ } ++ ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)||(_hal_SERFLASH.u8MID == MID_WB)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ if(gReadMode == E_QUAD_MODE && _hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(PAL_SPI_GetClk() > 54) ++ { ++ printk("MX supports QUAD mode only when CLK <= 54MHz\n"); ++ BUG(); ++ } ++ } ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++// //check norflaash support to 4Xmode or 2xmode ++// if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++// gReadMode = E_DUAL_D_MODE; ++// else ++// gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++// don't overwrite default setting ++// gReadMode = E_FAST_MODE; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++#endif ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) || defined(CONFIG_FSP_WRITE_RIUOP_BRUST) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadRedirect(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_READ_BDMA ++MS_BOOL HAL_SERFLASH_ReadBdma(MS_U32 u32Offset, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_U32 u32AlignedOffset = (u32Offset) & (~0xF); ++ MS_U32 u32AlignedSize; ++ MS_U32 u32Delta; ++ ++ u32Delta = u32Offset - u32AlignedOffset; ++ u32AlignedSize = ((u32Size + u32Delta) + 0xF) & (~0xF); ++ { ++ HalBdmaParam_t tBdmaParam; ++ const u8 u8DmaCh = HAL_BDMA_CH0; ++ _HAL_BDMA_INIT(u32AlignedSize); ++ tBdmaParam.ePathSel = HAL_BDMA_SPI_TO_MIU0;//(pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MEM_TO_MIU0) : (HAL_BDMA_MEM_TO_MIU1); ++ tBdmaParam.bIntMode = 0; //0: polling mode ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = u32AlignedSize;//(u32Size + 0xF) & (~0xF); ++ tBdmaParam.pSrcAddr = (void*)u32AlignedOffset;//u32Offset; ++ tBdmaParam.pDstAddr = (void*)pu8BDMA_bus; ++ tBdmaParam.pfTxCbFunc = NULL;//msys_bdma_done; ++ tBdmaParam.u32Pattern = 0; ++ HalBdma_Initialize(u8DmaCh); ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("%s(0x%08X, %d, %p)b\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &tBdmaParam)) { ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("err\n")); ++ return FALSE; ++ } ++ Chip_Inv_Cache_Range(pu8BDMA_virt, u32AlignedSize);//u32Size); ++ //memcpy(pu8Data, (void*)pu8BDMA_virt, u32Size); ++ memcpy(pu8Data, (void*)pu8BDMA_virt + u32Delta, u32Size); ++ Ret = TRUE; ++ } ++ return TRUE; ++} ++#endif ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++#elif defined(CONFIG_FSP_READ_RIUOP) || defined(CONFIG_FSP_READ_BDMA) ++ { ++ MS_U8 u8EAR_min = u32Addr >> 24; ++ MS_U8 u8EAR_max = (u32Addr + u32Size) >> 24; ++ MS_U32 u32ReadSize = 0; ++ //printk("u8EAR_min %d u8EAR_max %d\n",u8EAR_min,u8EAR_max); ++ while(u8EAR_min <= u8EAR_max) ++ { ++ u32ReadSize = ((u8EAR_min+1) << 24) - u32Addr; ++ u32ReadSize = (u32ReadSize > u32Size) ? u32Size : u32ReadSize; ++ if(u8EAR_min != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR_min); ++ } ++ if(u32ReadSize) ++ { ++ #ifdef CONFIG_FSP_READ_RIUOP ++ Ret = HAL_FSP_Read(u32Addr, u32ReadSize, pu8Data); ++ #else ++ Ret = HAL_SERFLASH_ReadBdma(u32Addr, u32ReadSize, pu8Data); ++ #endif ++ } ++ u32Addr += u32ReadSize; ++ u32Size -= u32ReadSize; ++ pu8Data += u32ReadSize; ++ u8EAR_min++; ++ } ++ } ++#else ++#error "FPS READ" ++#endif ++ if(gReadMode > E_FAST_MODE && gReadMode != E_RIUISP_MODE) ++ { ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ } ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRASstart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRASstart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ case 10: ++ FSP_WRITE_MASK(REG_FSP_WDB10,REG_FSP_WDB10_DATA(u8Data),REG_FSP_WDB10_MASK); ++ break; ++ case 11: ++ FSP_WRITE_MASK(REG_FSP_WDB11,REG_FSP_WDB11_DATA(u8Data),REG_FSP_WDB11_MASK); ++ break; ++ case 12: ++ FSP_WRITE_MASK(REG_FSP_WDB12,REG_FSP_WDB12_DATA(u8Data),REG_FSP_WDB12_MASK); ++ break; ++ case 13: ++ FSP_WRITE_MASK(REG_FSP_WDB13,REG_FSP_WDB13_DATA(u8Data),REG_FSP_WDB13_MASK); ++ break; ++ case 14: ++ FSP_WRITE_MASK(REG_FSP_WDB14,REG_FSP_WDB14_DATA(u8Data),REG_FSP_WDB14_MASK); ++ break; ++ case 15: ++ FSP_WRITE_MASK(REG_FSP_WDB15,REG_FSP_WDB15_DATA(u8Data),REG_FSP_WDB15_MASK); ++ break; ++ case 16: ++ FSP_WRITE_MASK(REG_FSP_WDB16,REG_FSP_WDB16_DATA(u8Data),REG_FSP_WDB16_MASK); ++ break; ++ ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++#if 0 ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++#endif ++} ++ ++void HAL_FSP_Exit(void) ++{ ++#if 0 ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d\n", __FUNCTION__, bEnable)); ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ bRet = HAL_FSP_ReadStatus(SPI_CMD_RDSR, 1, &u8data); ++ if(bEnable) ++ { ++ if((u8data & SF_SR_QUAD) == 0) { ++ u8data |= SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } else { ++ if((u8data & SF_SR_QUAD) != 0) { ++ u8data &= ~SF_SR_QUAD; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ } ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ bRet = HAL_FSP_ReadStatusReg(&u8Status); ++ if(bRet == FALSE) ++ return bRet; ++ ++ u8Status |= SF_SR_SRWD;//checked on WB/GD/MX ++//quad mode should be handled in read/write ++#if 0 //device dependent ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUAD; ++#endif ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u8MID == MID_XTX) || (_hal_SERFLASH.u8MID == MID_WUHAN)) ++ { ++ u8Status &= ~BITS(6:2,0x1F); ++ } ++ else {//check on WB/MX ++ u8Status &= ~BITS(5:2,0xF); ++ } ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((2+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(U32 u32DataSize) ++{ ++ u32DataSize += BDMA_ALIGN; ++ if(pu8BDMA_virt != 0 && u32BdmaSize < u32DataSize) ++ { ++ int err; ++ err = msys_release_dmem(&mem_info); ++ if(u32DataSize >= BDMA_SIZE_WARNING) ++ { ++ pr_err("\n\n --->from %ld to %d\n\n", u32BdmaSize, u32DataSize); ++ } ++ if(0 != err) ++ { ++ printk("[Ser flash] Unable to free BDMA mem bus=0x%08X (err:%d)\n", (unsigned int)pu8BDMA_bus, err); ++ } ++ pu8BDMA_virt = 0; ++ } ++ if(pu8BDMA_virt != 0) ++ return; ++ mem_info.length = u32DataSize; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ u32BdmaSize = mem_info.length; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x len:0x%lX\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus, u32BdmaSize); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++#ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++MS_BOOL _HAL_PP_RIUOP_BURST(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ MS_U32 u32offs = u32Src_off; ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status = 0; ++ MS_U32 u32I, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U32 u32Size; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ //printk("PP 0x%x len:%d\r\n",(unsigned int)u32Dst_off, (unsigned int)u32Len); ++#if 1 ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++#endif ++ ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ //printk("\r\nwrite enable\r\n"); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write enable command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ /* We can't get what time the CS is pull high with hardware contorl. ++ Use software control output a level waveform */ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST | 0x2)); // SW control pull high CS ++ udelay(5); ++ ++ //write command ++ HAL_FSP_WriteBufs(0,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, (REG_SPI_ENABLE_BURST)); // SW control pull down CS ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ u32quotient = (u32Len / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Len % REG_FSP_MAX_WRITEDATA_SIZE); ++ //printk("quotient:%lu, rem:%lu\r\n",u32quotient, u32remainder); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ { ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ } ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(MS_U8*)(u32offs+u32J)); ++ } ++ u32offs += u32Size; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("Write command Fail!!!!\r\n"); ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); ++ return bRet; ++ } ++ ++ } ++ ++ //printk("CS up\r\n"); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_DISABLE_BURST); // Disable SW control ++ ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ ++ ++ /*if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ CompareMemory(u32Src_off, u32Dst_off+BASE_FLASH_OFFSET, u32Len);*/ ++ ++ return bRet; ++} ++#endif ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ _HAL_BDMA_INIT(u32Len); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x3<<2)), 0x8000); //set channel0 to MIU ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)&0x0FFF); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++#endif ++#if defined(CONFIG_FSP_WRITE_RIUOP_BRUST) || defined(CONFIG_FSP_WRITE_BDMA) ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ #ifdef CONFIG_FSP_WRITE_RIUOP_BRUST ++ bRet = _HAL_PP_RIUOP_BURST((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #else ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ #endif ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++#endif +diff --git a/drivers/sstar/flash_isp/infinity6e/halSERFLASH.h b/drivers/sstar/flash_isp/infinity6e/halSERFLASH.h +new file mode 100644 +index 000000000000..e42fbfe8d62b +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6e/halSERFLASH.h +@@ -0,0 +1,178 @@ ++/* ++* halSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//check Bounding Type bank 0x101E , offset 0x48 bit[5:4] ++#define CHIP_BOUND_TYPES (BIT5|BIT4) ++#define CHIP_BOUND_QFN88 0x00//00: QFN88 ++#define CHIP_BOUND_QFN128 (BIT4)//01: QFN128 ++#define CHIP_BOUND_BGA1 (BIT5)//10: BGA1 ++#define CHIP_BOUND_BGA2A2B (BIT5|BIT4)//11: BGA2A & BGA2B ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRASstart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/infinity6e/regSERFLASH.h b/drivers/sstar/flash_isp/infinity6e/regSERFLASH.h +new file mode 100644 +index 000000000000..683fe08b6efa +--- /dev/null ++++ b/drivers/sstar/flash_isp/infinity6e/regSERFLASH.h +@@ -0,0 +1,516 @@ ++/* ++* regSERFLASH.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_PMSLEEP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000E00) ++#define BASE_REG_FSP_PM_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_PM_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100D00) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100E00) ++ ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) ++ #define SFSH_CHIP_NORMOL_ENABLE BITS(3:0, 0x0) // SPI CMD [0x03] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 0x1) // SPI CMD [0x0B] ++ #define SFSH_CHIP_DUALREAD_ENABLE BITS(3:0, 0x2) // SPI CMD [0x3B] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 0x3) // SPI CMD [0xBB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 0xA) // SPI CMD [0xEB] ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUAD BITS(6:6, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x35) ++#define SPI_CMD_RDSR3 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_WRSR2 (0x31) ++#define SPI_CMD_WRSR3 (0x11) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++#define REG_FSP_WDB10 0x70 ++#define REG_FSP_WDB10_MASK BMASK(7:0) ++#define REG_FSP_WDB10_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB11 0x70 ++#define REG_FSP_WDB11_MASK BMASK(15:8) ++#define REG_FSP_WDB11_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB12 0x71 ++#define REG_FSP_WDB12_MASK BMASK(7:0) ++#define REG_FSP_WDB12_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB13 0x71 ++#define REG_FSP_WDB13_MASK BMASK(15:8) ++#define REG_FSP_WDB13_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB14 0x72 ++#define REG_FSP_WDB14_MASK BMASK(7:0) ++#define REG_FSP_WDB14_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB15 0x72 ++#define REG_FSP_WDB15_MASK BMASK(15:8) ++#define REG_FSP_WDB15_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB16 0x73 ++#define REG_FSP_WDB16_MASK BMASK(7:0) ++#define REG_FSP_WDB16_DATA(d) BITS(7:0, d) ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xF ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/sstar/flash_isp/mtd_serflash.c b/drivers/sstar/flash_isp/mtd_serflash.c +new file mode 100755 +index 000000000000..dbfa755ad483 +--- /dev/null ++++ b/drivers/sstar/flash_isp/mtd_serflash.c +@@ -0,0 +1,883 @@ ++/* ++* mtd_serflash.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//********************************************************************* ++// ++// MODULE NAME: ++// mtd_serflash.c ++// ++// DESCRIPTION: ++// This file is an agent between mtd layer and spi flash driver ++// ++// PUBLIC PROCEDURES: ++// Name Title ++// ----------------------- -------------------------------------- ++// int xxx_proc declare in its corresponding header file ++// ++// LOCAL PROCEDURES: ++// Name Title ++// ----------------------- -------------------------------------- ++// get_prnt_cnvs the local procedure in the file ++// ++// Written by Tao.Zhou@MSTAR Inc. ++//--------------------------------------------------------------------- ++// ++//******************************************************************** ++//-------------------------------------------------------------------- ++// GENERAL INCLUDE ++//-------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++#include ++#endif ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#ifdef CONFIG_MS_FLASH_ISP_MXP_PARTS ++#include "part_mxp.h" ++#endif ++#include ++#include ++#include ++#include ++#include //for reading strapping ++ ++#define CONFIG_DISABLE_WRITE_PROTECT ++#define CONFIG_MTD_PARTITIONS ++ ++/* Flash opcodes. */ ++#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ ++#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ ++//#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ ++#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ ++#define OPCODE_RDID 0x9f /* Read JEDEC ID */ ++ ++/* Define max times to check status register before we give up. */ ++#define MAX_READY_WAIT_COUNT 100000 ++#define CMD_SIZE 4 ++ ++//#ifdef CONFIG_MTD_PARTITIONS ++#define mtd_has_partitions() (1) ++//#else ++//#define mtd_has_partitions() (0) ++//#endif ++ ++//#define DEBUG(x...) printk(x...) ++ ++extern int parse_mtd_partitions(struct mtd_info *master, const char *const *types, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ ++/****************************************************************************/ ++ ++struct serflash ++{ ++ struct mutex lock; ++ struct mtd_info mtd; ++ unsigned partitioned:1; ++ u8 erase_opcode; ++}; ++ ++static inline struct serflash *mtd_to_serflash(struct mtd_info *mtd) ++{ ++ return container_of(mtd, struct serflash, mtd); ++} ++ ++/* Erase flash fully or part of it */ ++static int serflash_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ ++ struct serflash *flash = mtd_to_serflash(mtd); ++ uint64_t addr_temp, len_temp; ++ ++ //printk(KERN_WARNING"%s: addr 0x%08x, len %ld\n", __func__, (u32)instr->addr, (long int)instr->len); ++ ++ /* sanity checks */ ++ if (!instr->len) ++ return 0; ++ ++ /* range and alignment check */ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ /* mod = do_div(x,y); ++ result = x; */ ++ addr_temp = instr->addr; ++ len_temp = instr->len; ++ if ((do_div(addr_temp , mtd->erasesize) != 0) ||(do_div(len_temp, mtd->erasesize) != 0)) ++ { ++ return -EINVAL; ++ } ++#else ++ if ((instr->addr % mtd->erasesize) != 0 || (instr->len % mtd->erasesize) != 0) ++ return -EINVAL; ++#endif ++ ++ mutex_lock(&flash->lock); ++ ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ /*write protect false before erase*/ ++ if (!MDrv_SERFLASH_WriteProtect(0)) ++ { ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++#endif ++ /* erase the whole chip */ ++ if (instr->len == mtd->size && !MDrv_SERFLASH_EraseChip()) ++ { ++ instr->state = MTD_ERASE_FAILED; ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ else if (!MDrv_SERFLASH_AddressErase(instr->addr, instr->len, 1)) ++ { ++ instr->state = MTD_ERASE_FAILED; ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ ++ instr->state = MTD_ERASE_DONE; ++ ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++/* ++ * Read an address range from the flash chip. The address range ++ * may be any size provided it is within the physical boundaries. ++ */ ++static int serflash_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct serflash *flash = mtd_to_serflash(mtd); ++ ++ //printk(KERN_WARNING "%s %s 0x%08x, len %zd\n", __func__, "from", (u32)from, len); ++ ++ /* sanity checks */ ++ if (!len) ++ return 0; ++ ++ if (from + len > flash->mtd.size) ++ return -EINVAL; ++ ++ mutex_lock(&flash->lock); ++ ++#if 0 ++ /* Wait till previous write/erase is done. */ ++ if (wait_till_ready(flash)) ++ { ++ /* REVISIT status return?? */ ++ mutex_unlock(&flash->lock); ++ return 1; ++ } ++#endif ++ ++ if (MDrv_SERFLASH_Read(from, len, (unsigned char *)buf)) ++ { ++ *retlen = len; ++ } ++ else ++ { ++ *retlen = 0; ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ ++ mutex_unlock(&flash->lock); ++ ++ return 0; ++} ++ ++/* ++ * Write an address range to the flash chip. Data must be written in ++ * FLASH_PAGESIZE chunks. The address range may be any size provided ++ * it is within the physical boundaries. ++ */ ++static int serflash_write(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct serflash *flash = mtd_to_serflash(mtd); ++ ++ //printk(KERN_WARNING "%s %s 0x%08x, len %zd\n",__func__, "to", (u32)to, len); ++ ++ if (retlen) ++ *retlen = 0; ++ ++ /* sanity checks */ ++ if (!len) ++ return(0); ++ ++ if (to + len > flash->mtd.size) ++ return -EINVAL; ++ ++ mutex_lock(&flash->lock); ++ ++#if 0 ++ /* Wait until finished previous write command. */ ++ if (wait_till_ready(flash)) ++ { ++ mutex_unlock(&flash->lock); ++ return 1; ++ } ++#endif ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ ++ if (!MDrv_SERFLASH_WriteProtect(0)) ++ { ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++#endif ++//modified by daniel.lee 2010/0514 ++ /* ++ if (!MDrv_SERFLASH_BlockErase(erase_start, erase_end, TRUE)) ++ { ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ */ ++ if (MDrv_SERFLASH_Write(to, len, (unsigned char *)buf)) ++ { ++ if (retlen) ++ *retlen = len; ++ } ++ else ++ { ++ if (retlen) ++ *retlen = 0; ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ ++ return 0; ++} ++ ++ ++ ++#define MSTAR_SERFLASH_SIZE (8 * 1024 * 1024) ++ ++ ++#define SERFLASH_PART_PARTITION_0_OFFSET 0 ++#define SERFLASH_PART_PARTITION_0_SIZE (32+512+32) * 1024 ++ ++#define SERFLASH_PART_PARTITION_1_OFFSET (SERFLASH_PART_PARTITION_0_OFFSET + SERFLASH_PART_PARTITION_0_SIZE) ++#define SERFLASH_PART_PARTITION_1_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_PARTITION_2_OFFSET (SERFLASH_PART_PARTITION_1_OFFSET + SERFLASH_PART_PARTITION_1_SIZE) ++#define SERFLASH_PART_PARTITION_2_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_PARTITION_3_OFFSET (SERFLASH_PART_PARTITION_2_OFFSET + SERFLASH_PART_PARTITION_2_SIZE) ++#define SERFLASH_PART_PARTITION_3_SIZE MSTAR_SERFLASH_SIZE - SERFLASH_PART_PARTITION_3_OFFSET ++ ++#if 0 ++#define SERFLASH_PART_PARTITION_TBL_OFFSET 0 ++#define SERFLASH_PART_PARTITION_TBL_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_LINUX_BOOT_PARAM_OFFSET (SERFLASH_PART_PARTITION_TBL_OFFSET + SERFLASH_PART_PARTITION_TBL_SIZE) ++#define SERFLASH_PART_LINUX_BOOT_PARAM_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_KERNEL_OFFSET (SERFLASH_PART_LINUX_BOOT_PARAM_OFFSET + SERFLASH_PART_LINUX_BOOT_PARAM_SIZE) ++#define SERFLASH_PART_KERNEL_SIZE 1536 * 1024 ++ ++#define SERFLASH_PART_ROOTFS_OFFSET (SERFLASH_PART_KERNEL_OFFSET + SERFLASH_PART_KERNEL_SIZE) ++#define SERFLASH_PART_ROOTFS_SIZE 2560 * 1024 ++ ++#define SERFLASH_PART_CONF_OFFSET (SERFLASH_PART_ROOTFS_OFFSET + SERFLASH_PART_ROOTFS_SIZE) ++#define SERFLASH_PART_CONF_SIZE 64 * 1024 ++ ++ ++#define SERFLASH_PART_CHAKRA_BOOT_PARAM_OFFSET (NAND_PART_KERNEL_OFFSET + NAND_PART_KERNEL_SIZE) ++#define SERFLASH_PART_CHAKRA_BOOT_PARAM_SIZE SZ_512KB ++ ++#define SERFLASH_PART_CHAKRA_BIN_OFFSET (NAND_PART_CHAKRA_BOOT_PARAM_OFFSET + NAND_PART_CHAKRA_BOOT_PARAM_SIZE) ++#define SERFLASH_PART_CHAKRA_BIN_PARAM_SIZE SZ_8MB ++ ++#define SERFLASH_PART_SUBSYSTEM_OFFSET (NAND_PART_CONF_OFFSET + NAND_PART_CONF_SIZE) ++#define SERFLASH_PART_SUBSYSTEM_SIZE SZ_2MB ++ ++#define SERFLASH_PART_FONT_OFFSET (NAND_PART_SUBSYSTEM_OFFSET + NAND_PART_SUBSYSTEM_SIZE) ++#define SERFLASH_PART_FONT_SIZE SZ_4MB ++ ++#define SERFLASH_PART_OPT_OFFSET (NAND_PART_FONT_OFFSET + NAND_PART_FONT_SIZE) ++#define SERFLASH_PART_OPT_SIZE SZ_8MB ++ ++#define SERFLASH_PART_APPLICATION_OFFSET (NAND_PART_OPT_OFFSET + NAND_PART_OPT_SIZE) ++#define SERFLASH_PART_APPLICATION_SIZE (MSTAR_NAND_SIZE - NAND_PART_APPLICATION_OFFSET) ++#endif ++// ++//#if ( (NAND_PART_APPLICATION_OFFSET) >= MSTAR_SERFLASH_SIZE) ++// #error "Error: NAND partition is not correct!!!" ++//#endif ++ ++static const struct mtd_partition serflash_partition_info[] = ++{ ++ ++ { ++ .name = "DATA",//"boot", ++ .offset = 0x00300000,//SERFLASH_PART_PARTITION_0_OFFSET, ++ .size = 0x00080000,//SERFLASH_PART_PARTITION_0_SIZE ++ .mask_flags = 0 ++ }, ++ { ++ .name = "SYSTEM",//"boot", ++ .offset = 0x00380000,//SERFLASH_PART_PARTITION_0_OFFSET, ++ .size = 0x00400000,//SERFLASH_PART_PARTITION_0_SIZE ++ .mask_flags = 0 ++ }, ++ { ++ .name = "EXT",//"boot", ++ .offset = 0x00780000,//SERFLASH_PART_PARTITION_0_OFFSET, ++ .size = 0x00880000,//SERFLASH_PART_PARTITION_0_SIZE ++ .mask_flags = 0 ++ }, ++ ++}; ++ ++#define SERFLASH_NUM_PARTITIONS ARRAY_SIZE(serflash_partition_info) ++ ++ ++extern int mxp_init_nor_flash(void); ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++extern MS_BOOL gQuadSupport; ++ ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++ void **pvSerflashclk = NULL; ++ u32 SerflashParentCnt = 1; ++ ++ ++u8 serflash_ClkDisable(void) ++{ ++ u32 u32clknum = 0; ++ ++ for(u32clknum = 0; u32clknum < SerflashParentCnt; u32clknum++) ++ { ++ if (pvSerflashclk[u32clknum]) ++ { ++ CamClkSetOnOff(pvSerflashclk[u32clknum],0); ++ } ++ } ++ return 1; ++} ++u8 serflash_ClkEnable(void) ++{ ++ u32 u32clknum = 0; ++ ++ for(u32clknum = 0; u32clknum < SerflashParentCnt; u32clknum++) ++ { ++ if (pvSerflashclk[u32clknum]) ++ { ++ CamClkSetOnOff(pvSerflashclk[u32clknum],1); ++ } ++ } ++ ++ return 1; ++} ++u8 serflash_ClkRegister( struct device *dev) ++{ ++ u32 u32clknum; ++ u32 SerFlashClk; ++ u8 str[16]; ++ ++ if(of_find_property(dev->of_node,"camclk",&SerflashParentCnt)) ++ { ++ SerflashParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(SerflashParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, SerflashParentCnt); ++ return 0; ++ } ++ pvSerflashclk = kzalloc((sizeof(void *) * SerflashParentCnt), GFP_KERNEL); ++ if(!pvSerflashclk){ ++ return 0; ++ } ++ for(u32clknum = 0; u32clknum < SerflashParentCnt; u32clknum++) ++ { ++ SerFlashClk = 0; ++ of_property_read_u32_index(dev->of_node,"camclk", u32clknum,&(SerFlashClk)); ++ if (!SerFlashClk) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamOsSnprintf(str, 16, "serflash_%d ",u32clknum); ++ CamClkRegister(str,SerFlashClk,&(pvSerflashclk[u32clknum])); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++ return 1; ++} ++u8 serflash_ClkUnregister(void) ++{ ++ ++ u32 u32clknum; ++ ++ for(u32clknum=0;u32clknumdev); ++ serflash_ClkEnable(); ++#else ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_probe] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_prepare_enable(spi_clks[i]); ++ } ++ clk_put(spi_clks[i]); ++ } ++ kfree(spi_clks); ++ } ++#endif ++ if(!of_property_read_u32(pdev->dev.of_node, "quadread", (u32 *)&u32Val)) ++ { ++ gQuadSupport = u32Val; ++ }else{ ++ gQuadSupport = 0; ++ //printk( "[serflash_probe] not search quadread on DTS\n" ); ++ } ++ ++ //if(gQuadSupport) ++ //printk( "[serflash_probe] DTS support Quad Read\n" ); ++ ++ // jedec_probe() will read id, so initialize hardware first ++ MDrv_SERFLASH_Init(); ++ ++ /* Platform data helps sort out which chip type we have, as ++ * well as how this board partitions it. If we don't have ++ * a chip ID, try the JEDEC id commands; they'll work for most ++ * newer chips, even if we don't recognize the particular chip. ++ */ ++ ++ //bDetect is the global variable from halserflash.c ++ if(bDetect == FALSE) ++ { ++ printk(KERN_WARNING"[FSP] found no flash_info!!"); ++ return -ENODEV; ++ } ++ ++ ++ flash = kzalloc(sizeof *flash, GFP_KERNEL); ++ if (!flash) ++ return -ENOMEM; ++ ++ mutex_init(&flash->lock); ++ ++ flash->mtd.priv = flash; ++ flash->mtd.name ="NOR_FLASH"; ++ flash->mtd.type = MTD_NORFLASH; ++ flash->mtd.writesize = 1; ++ flash->mtd.writebufsize = flash->mtd.writesize; ++ flash->mtd.flags = MTD_CAP_NORFLASH; ++ MDrv_SERFLASH_DetectSize(&u32Val); ++ flash->mtd.size = u32Val; ++ flash->mtd._erase = serflash_erase; ++ flash->mtd._read = serflash_read; ++ flash->mtd._write = serflash_write; ++ flash->erase_opcode = OPCODE_SE; ++ flash->mtd.erasesize = (_hal_SERFLASH.u32SecSize); ++ ++ ++#ifdef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(0); ++#endif ++ ++ //dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name, ++ //flash->mtd.size / 1024); ++ ++ printk(KERN_WARNING ++ "mtd .name = %s, .size = 0x%.8x (%uMiB)\n" ++ " .erasesize = 0x%.8x .numeraseregions = %d\n", ++ flash->mtd.name, ++ (unsigned int)flash->mtd.size, (unsigned int)flash->mtd.size / (1024*1024), ++ (unsigned int)flash->mtd.erasesize, ++ flash->mtd.numeraseregions); ++ ++ if (flash->mtd.numeraseregions) ++ for (i = 0; i < flash->mtd.numeraseregions; i++) ++ printk(KERN_WARNING ++ "mtd.eraseregions[%d] = { .offset = 0x%.8x, " ++ ".erasesize = 0x%.8x (%uKiB), " ++ ".numblocks = %d }\n", ++ i, (u32)flash->mtd.eraseregions[i].offset, ++ (unsigned int)flash->mtd.eraseregions[i].erasesize, ++ flash->mtd.eraseregions[i].erasesize / 1024, ++ (unsigned int)flash->mtd.eraseregions[i].numblocks); ++ ++ ++ /* partitions should match sector boundaries; and it may be good to ++ * use readonly partitions for writeprotected sectors (BP2..BP0). ++ */ ++ if (mtd_has_partitions()) ++ { ++ struct mtd_partition *parts = NULL; ++ int nr_parts = 0; ++#ifdef CONFIG_MTD_CMDLINE_PARTS ++ static const char *part_probes[] = { "cmdlinepart", NULL, }; ++#endif ++ ++#ifdef CONFIG_MS_FLASH_ISP_MXP_PARTS ++ printk(KERN_WARNING"MXP_PARTS!!\n"); ++ if(mxp_init_nor_flash()>=0) ++ { ++ int j=0; ++ nr_parts=mxp_get_total_record_count(); ++ parts=kmalloc(sizeof(struct mtd_partition)*nr_parts,GFP_KERNEL); ++ if(NULL==parts)BUG(); ++ ++ for(i=0; ipartitioned = 1; ++ if(j>0) ++ { ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ u32Ret = mtd_device_register(&flash->mtd, parts, j); ++#else ++ u32Ret = add_mtd_partitions(&flash->mtd, parts, j); ++#endif ++ if(!u32Ret)//success ++ { ++ kfree(parts); ++ return u32Ret; ++ } ++ } ++ kfree(parts); ++ parts = NULL; ++ } ++ printk(KERN_WARNING"MXP NOT FOUND!!\n"); ++#endif //end CONFIG_MS_FLASH_ISP_MXP_PARTS ++ ++ ++#ifdef CONFIG_MTD_CMDLINE_PARTS ++ nr_parts = parse_mtd_partitions(&flash->mtd,part_probes, &parts, 0); ++#endif ++ ++ if (nr_parts > 0) ++ { ++ for (i = 0; i < nr_parts; i++) ++ { ++ printk(KERN_WARNING "partitions[%d] = " ++ "{.name = %s, .offset = 0x%.8x, " ++ ".size = 0x%.8x (%uKiB) }\n", ++ i, parts[i].name, ++ (unsigned int)(parts[i].offset), ++ (unsigned int)(parts[i].size), ++ (unsigned int)(parts[i].size / 1024)); ++ } ++ flash->partitioned = 1; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ u32Ret = mtd_device_register(&flash->mtd, parts, nr_parts); ++#else ++ u32Ret = add_mtd_partitions(&flash->mtd, parts, nr_parts); ++#endif ++ } ++ else ++ { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ u32Ret = mtd_device_register(&flash->mtd, serflash_partition_info, SERFLASH_NUM_PARTITIONS); ++#else ++ u32Ret = add_mtd_partitions(&flash->mtd, serflash_partition_info, SERFLASH_NUM_PARTITIONS); ++#endif ++ } ++ if(!u32Ret) //success ++ { ++ return u32Ret; ++ } ++ ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ return mtd_device_register(&flash->mtd, NULL, NULL); ++#else ++ return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; ++#endif ++} ++ ++ ++static int serflash_cleanup(struct platform_device *pdev) ++{ ++#if 0 ++ struct serflash *flash = mtd->priv; ++ int status; ++ ++ /* Clean up MTD stuff. */ ++ if (mtd_has_partitions() && flash->partitioned) ++ status = del_mtd_partitions(&flash->mtd); ++ else ++ status = del_mtd_device(&flash->mtd); ++ if (status == 0) ++ kfree(flash); ++#endif ++#ifdef CONFIG_CAM_CLK ++ serflash_ClkDisable(); ++ serflash_ClkUnregister(); ++#else ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **spi_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_cleanup] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_disable_unprepare(spi_clks[i]); ++ } ++ clk_put(spi_clks[i]); ++ } ++ kfree(spi_clks); ++ } ++#endif ++#endif ++ return 0; ++} ++ ++#if defined (CONFIG_OF) ++static struct of_device_id flashisp_of_device_ids[] = { ++ {.compatible = "mtd-flashisp"}, ++ {}, ++}; ++#endif ++ ++#ifdef CONFIG_PM ++static int serflash_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++#ifdef CONFIG_CAM_CLK ++ serflash_ClkDisable(); ++#else ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **spi_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_suspend] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_disable_unprepare(spi_clks[i]); ++ } ++ clk_put(spi_clks[i]); ++ } ++ kfree(spi_clks); ++ } ++#endif ++#endif ++ return 0; ++} ++ ++static int serflash_resume(struct platform_device *pdev) ++{ ++#ifdef CONFIG_CAM_CLK ++ serflash_ClkEnable(); ++#else ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **spi_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_cleanup] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_prepare_enable(spi_clks[i]); ++ } ++ clk_put(spi_clks[i]); ++ } ++ kfree(spi_clks); ++ } ++#endif ++#endif ++ return 0; ++} ++#endif ++ ++static struct platform_driver ms_flash_driver = { ++ .probe = serflash_probe, ++ .remove = serflash_cleanup, ++#ifdef CONFIG_PM ++ .suspend = serflash_suspend, ++ .resume = serflash_resume, ++#endif ++ .driver = { ++ .name = "mtd-flashisp", ++#if defined(CONFIG_OF) ++ .of_match_table = flashisp_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++ ++module_platform_driver(ms_flash_driver); ++ ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Tao.Zhou"); ++MODULE_DESCRIPTION("MTD Mstar driver for spi flash chips"); ++ +diff --git a/drivers/sstar/flash_isp/mxp_flash.c b/drivers/sstar/flash_isp/mxp_flash.c +new file mode 100755 +index 000000000000..fd98506bd3e2 +--- /dev/null ++++ b/drivers/sstar/flash_isp/mxp_flash.c +@@ -0,0 +1,149 @@ ++/* ++* mxp_flash.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++#include ++#endif ++#include ++#include "part_mxp.h" ++#include "MsTypes.h" ++ ++ ++#ifdef CONFIG_MS_FLASH_ISP ++static mxp_manager* nor_flash_mxp=NULL; ++ ++//#define NOR_FLASH_MXP_TABLE_BASE 0x0020000 ++#define NOR_FLASH_MXP_TABLE_SIZE 0x1000 ++ ++extern MS_BOOL MDrv_SERFLASH_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++ ++static int nor_flash_mxp_read_bytes(int offset,void* buf,int len) ++{ ++ ++ if (!MDrv_SERFLASH_Read(offset,len,buf)) ++ { ++ printk("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++static int nor_flash_mxp_write_bytes(int offset,void* buf,int len) ++{ ++#if 0 ++ int ret; ++ ret = spi_flash_erase(norflash, NOR_FLASH_MXP_TABLE_BASE, NOR_FLASH_MXP_TABLE_SIZE); ++ if (ret) { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ return -1; ++ } ++ ++ ret = spi_flash_write(norflash, NOR_FLASH_MXP_TABLE_BASE+offset, len, buf); ++ if (ret) { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ return -1; ++ } ++#endif ++ return 0; ++} ++ ++static int nor_flash_mxp_update_byte(int offset, char byte) ++{ ++ int ret=-1; ++#if 0 ++ char b; ++ if(spi_flash_read(norflash, (NOR_FLASH_MXP_TABLE_BASE+offset), (size_t)1, &b)) ++ { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ goto DONE; ++ ++ } ++ ++ printf("[nor_flash_mxp_update_byte] 0x%08X: 0x%02X -> 0x%02X\n",(NOR_FLASH_MXP_TABLE_BASE+offset),b,byte); ++ if( (((char)(byte^b)) & (char)(~b)) >0 ) ++ { ++ printf(" using general page flash write\n"); ++ return nor_flash_mxp_write_bytes(offset,&byte,1); ++ } ++ ++ printf(" using single byte flash write\n"); ++ if(spi_flash_write(norflash, NOR_FLASH_MXP_TABLE_BASE+offset, 1, &byte)) { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ goto DONE; ++ } ++ ++ ret=0; ++ ++ ++DONE: ++#endif ++ ++ return ret; ++ ++} ++ ++int mxp_init_nor_flash(void) ++{ ++ int ret=-1; ++ //printk(KERN_WARNING"[mxp_init_nor_flash]\n"); ++ if(nor_flash_mxp==NULL) ++ { ++ nor_flash_mxp=kmalloc(sizeof(mxp_manager),GFP_KERNEL); ++ if(nor_flash_mxp==NULL) ++ { ++ printk(KERN_ERR "ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ goto DONE; ++ } ++ ++ //printk(KERN_WARNING"nor_flash_mxp allocated success!!\n"); ++ ++ } ++ else ++ { ++ return 1; ++ } ++ ++// if(norflash==NULL) ++// { ++// norflash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); ++// if (!norflash) { ++// printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++// goto DONE; ++// } ++// } ++ ++ nor_flash_mxp->read_table_bytes=nor_flash_mxp_read_bytes; ++ nor_flash_mxp->write_table_bytes=nor_flash_mxp_write_bytes; ++ nor_flash_mxp->update_table_byte=nor_flash_mxp_update_byte; ++ ++ if(0!=mxp_init(NOR_FLASH_MXP_TABLE_SIZE,nor_flash_mxp)) ++ { ++ printk(KERN_ERR "ERROR!! [%s] can't find mxp table\n",__FUNCTION__); ++ goto DONE; ++ } ++ ++ ret=0; ++DONE: ++ return ret; ++ ++} ++#endif ++ ++ +diff --git a/drivers/sstar/flash_isp/part_mxp.c b/drivers/sstar/flash_isp/part_mxp.c +new file mode 100755 +index 000000000000..882cacd9c7cc +--- /dev/null ++++ b/drivers/sstar/flash_isp/part_mxp.c +@@ -0,0 +1,321 @@ ++/* ++* part_mxp.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++#include ++#endif ++#include ++#include "part_mxp.h" ++ ++#define MXP_ALLOC(x) kmalloc(x,GFP_KERNEL) ++#define MXP_FREE(x) kfree(x) ++#define MXP_MSG(format,...) printk(format, ##__VA_ARGS__) ++ ++static int mxp_table_size=0; ++static int mxp_record_count=0; ++static mxp_manager* mxp; ++static mxp_record* mxp_parts=NULL; ++static const int mxp_offset[] = {0xA000/*40K*/, 0xC000/*48K*/, 0xF000/*60K*/, 0x20000/*128K*/, 0x40000/*256K*/, 0x80000/*512K*/}; ++ ++int mxp_base; ++ ++static int chk_magic_seq(int seq) ++{ ++ ++ if( mxp_parts[seq].magic_prefix[0]=='M' && ++ mxp_parts[seq].magic_prefix[1]=='X' && ++ mxp_parts[seq].magic_prefix[2]=='P' && ++ mxp_parts[seq].magic_prefix[3]=='T' && ++ mxp_parts[seq].magic_suffix[0]=='T' && ++ mxp_parts[seq].magic_suffix[1]=='P' && ++ mxp_parts[seq].magic_suffix[2]=='X' && ++ mxp_parts[seq].magic_suffix[3]=='M' ) ++ { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++static void fill_init_record(mxp_record* rec) ++{ ++ rec->magic_prefix[0]='M'; ++ rec->magic_prefix[1]='X'; ++ rec->magic_prefix[2]='P'; ++ rec->magic_prefix[3]='T'; ++ rec->magic_suffix[0]='T'; ++ rec->magic_suffix[1]='P'; ++ rec->magic_suffix[2]='X'; ++ rec->magic_suffix[3]='M'; ++ rec->type=MXP_PART_TYPE_TAG; ++ rec->status=MXP_PART_STATUS_EMPTY; ++ rec->format=MXP_PART_FORMAT_NONE; ++ rec->version=1; ++ memset(rec->backup,0x00,sizeof(rec->backup)); ++ memset(rec->name,0x00,sizeof(rec->name)); ++ ++} ++ ++int mxp_init(int size,mxp_manager* manager) ++{ ++ int i=0,j=0; ++ mxp_table_size=size; ++ mxp=manager; ++ ++ if(mxp_parts!=NULL) ++ { ++ MXP_FREE(mxp_parts); ++ } ++ ++ mxp_parts=MXP_ALLOC(mxp_table_size); ++ if(!mxp_parts) ++ { ++ MXP_MSG("ERROR!! Failed to allocate memory with mxp_table_size:%d\n",mxp_table_size); ++ return -1; ++ } ++ ++ for(i=0; iread_table_bytes(mxp_base,mxp_parts,mxp_table_size); ++ ++ if(0==mxp_check_table_magic()) ++ { ++ MXP_MSG("MXP found at mxp_offset[%d]=0x%08X, size=0x%X\n", i, mxp_offset[i], mxp_table_size); ++ for(j=0; jwrite_table_bytes(mxp_base,mxp_parts,mxp_table_size); ++ ++} ++ ++ ++int mxp_get_total_record_count(void) ++{ ++ return mxp_record_count; ++} ++ ++int mxp_save_table(void) ++{ ++ return mxp->write_table_bytes(mxp_base,mxp_parts,mxp_table_size); ++} ++ ++// ++int mxp_save_table_from_mem(u32 mem_address) ++{ ++// mxp_record* recs=(mxp_record*)((void *)mem_address); ++ int count=(mxp_table_size/sizeof(mxp_record)); ++ if((0!=chk_magic_seq(0)) || (0!=chk_magic_seq(count-1))) ++ { ++ MXP_MSG("ERROR!! The head & tail record does not have correct magic word. mem_address=0x%08X!!\n",mem_address); ++ return -1; ++ } ++ return mxp->write_table_bytes(mxp_base,(void*)mem_address,mxp_table_size); ++} ++// ++// ++ ++ ++int mxp_set_record(mxp_record* part) ++{ ++// mxp_record found; ++ ++ int count=mxp_table_size/sizeof(mxp_record); ++ int index=mxp_get_record_index((char *)(part->name)); ++ if(-1==index) //not found ++ { ++ if(mxp_record_count < (count-1)) ++ { ++ index=mxp_record_count; ++ } ++ else ++ { ++ MXP_MSG("ERROR!! No vancacy to add new mxp:%s\n",part->name); ++ return -2; ++ } ++ } ++ ++ ++ MXP_MSG("set mxp:%s to index %d\n",part->name,index); ++ memcpy(&mxp_parts[index],part,sizeof(mxp_record)); ++ ++ ++ mxp_save_table(); ++ ++ return 0; ++ ++} ++ ++//0:success -1:error ++int mxp_get_record_by_index(int index,mxp_record* part) ++{ ++ ++ if(index>=mxp_record_count) ++ { ++ MXP_MSG("ERROR!! index:%d is out of bound:%d\n",index,mxp_record_count); ++ return -1; ++ } ++ memcpy(part,&mxp_parts[index],sizeof(mxp_record)); ++ return 0; ++ ++} ++ ++ ++int mxp_delete_record_by_index(int index) ++{ ++ ++ if(index>=mxp_record_count) ++ { ++ MXP_MSG("ERROR!! index:%d is out of bound:%d\n",index,mxp_record_count); ++ return -1; ++ } ++ memcpy(&mxp_parts[index],&mxp_parts[index+1],(mxp_table_size-sizeof(mxp_record)*(index+1))); ++ ++ mxp_record_count-=1; ++ return 0; ++ ++} ++ ++int mxp_set_record_status(int index,int status) ++{ ++ if(index>=mxp_record_count) ++ { ++ MXP_MSG("ERROR!! index:%d is out of bound:%d\n",index,mxp_record_count); ++ return -1; ++ } ++ mxp_parts[index].status=status; ++ mxp->update_table_byte(mxp_base+((sizeof(mxp_record)*(index))+(sizeof(mxp_record)-5)),status); ++ return 0; ++} ++ ++//0~n:success -1:not found ++int mxp_get_record_index(char* name) ++{ ++ int i=0; ++ for(i=0;i<(mxp_record_count);i++) ++ { ++// mxp->read_bytes(sizeof(mxp_record)*(i+1),&mxp_parts[i+1],sizeof(mxp_record)); ++ ++ if(0==strcmp((const char*)(mxp_parts[i].name),((const char*)name))) ++ { ++// memcpy(part,&mxp_parts[i+1],sizeof(mxp_record)); ++ return i; ++ } ++ } ++ ++ return -1; ++ ++} ++ ++//0 -1:not found ++int mxp_get_record_by_name(char* name,mxp_record* part) ++{ ++ int i=0; ++ for(i=0;i<(mxp_record_count);i++) ++ { ++ ++ if(0==strcmp((const char*)(mxp_parts[i].name),((const char*)name))) ++ { ++ memcpy(part,&mxp_parts[i],sizeof(mxp_record)); ++ return 0; ++ } ++ } ++ ++ return -1; ++ ++} ++ ++int mxp_load_table(void){ ++ ++ int count=mxp_table_size/sizeof(mxp_record); ++ int i=0; ++ ++ if(mxp_parts!=NULL) ++ { ++ MXP_FREE(mxp_parts); ++ mxp_parts=NULL; ++ } ++ ++ mxp_record_count=0; ++ mxp_parts=MXP_ALLOC(mxp_table_size); ++ if(!mxp_parts) ++ { ++ MXP_MSG("ERROR!! Failed to allocate memory with mxp_table_size:%d\n",mxp_table_size); ++ return -1; ++ } ++ memset(mxp_parts,0xFF,mxp_table_size); ++ ++ for(i=0;iread_table_bytes(mxp_base+sizeof(mxp_record)*i,&mxp_parts[i],sizeof(mxp_record)); ++ ++ if(mxp_parts[i].type==MXP_PART_TYPE_TAG) ++ { ++ break; ++ } ++ } ++ ++ mxp_record_count=i; ++ ++ // read last part ++ mxp->read_table_bytes(mxp_base+sizeof(mxp_record)*(count-1),&mxp_parts[count-1],sizeof(mxp_record)); ++ ++ return 0; ++ ++} +diff --git a/drivers/sstar/flash_isp/part_mxp.h b/drivers/sstar/flash_isp/part_mxp.h +new file mode 100755 +index 000000000000..db78007c5433 +--- /dev/null ++++ b/drivers/sstar/flash_isp/part_mxp.h +@@ -0,0 +1,106 @@ ++/* ++* part_mxp.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _PART_MXP_H_ ++#define _PART_MXP_H_ ++ ++ ++#define MXP_PART_MAGIC_PREFIX "MXPT" ++#define MXP_PART_MAGIC_SUFFIX "TPXM" ++ ++#define MXP_STORAGE_TYPE_FLASH 0x01 ++ ++#define MXP_PART_TYPE_TAG 0x00 ++#define MXP_PART_TYPE_NORMAL 0x01 ++#define MXP_PART_TYPE_MTD 0x02 ++ ++#define MXP_PART_FORMAT_NONE 0x00 ++ ++ ++#define MXP_PART_STATUS_UPGRADING 0xF7 ++#define MXP_PART_STATUS_READY 0xF6 ++#define MXP_PART_STATUS_ACTIVE 0xF5 ++#define MXP_PART_STATUS_INACTIVE 0xF4 ++#define MXP_PART_STATUS_EMPTY 0x00 ++ ++typedef struct { ++ ++ u8 magic_prefix[4];//MXPT ++ u8 version; ++ u8 type; ++ u8 format; ++ u8 padding; ++ u64 start; ++ u64 size; ++ u32 block; ++ u32 block_count; ++ u8 name[16]; //should be 0 terminated ++ u8 backup[16]; //should be 0 terminated ++ u8 hash[32]; ++ u8 reserved[23]; ++ u32 crc32; ++ u8 status; ++ u8 magic_suffix[4];//TPXM ++ ++} mxp_record; ++ ++typedef struct { ++ u8 type; ++ u64 size; ++}mxp_storage_info; ++ ++typedef struct{ ++ int (*read_table_bytes)(int offset_from_flash,void* buf,int len); ++ int (*write_table_bytes)(int offset_from_flash,void* buf,int len); ++ int (*update_table_byte)(int offset_from_flash,char b); ++ int (*get_storage_info)(mxp_storage_info* info); ++}mxp_manager; ++ ++ ++//0:success -1:error ++int mxp_set_record_status(int index,int status); ++ ++//0:success -1:error ++int mxp_init(int size,mxp_manager* manager); ++ ++//0:success -1:error ++int mxp_check_record_magic(int index); ++ ++//0:success -1:error ++int mxp_check_table_magic(void); ++ ++//0:success -1:error ++int mxp_init_table(void); ++ ++//0:success -1:error ++int mxp_get_total_record_count(void); ++ ++//0:success -1:error ++int mxp_set_record(mxp_record* rec); ++ ++//0:success -1:error ++int mxp_get_record_by_index(int index,mxp_record* rec); ++int mxp_delete_record_by_index(int index); ++//0~n:success -1:not found ++int mxp_get_record_index(char* name); ++ ++ ++int mxp_save_table(void); ++int mxp_load_table(void); ++ ++ ++#endif +diff --git a/drivers/sstar/gmac/Kconfig b/drivers/sstar/gmac/Kconfig +new file mode 100755 +index 000000000000..460993d541e4 +--- /dev/null ++++ b/drivers/sstar/gmac/Kconfig +@@ -0,0 +1,182 @@ ++config MS_GMAC ++select NET ++select NET_ETHERNET ++select MII ++select PACKET ++select USE_POLICY_FWD ++select INET ++select NETDEVICES ++ ++tristate "GMAC" ++default n ++ ++---help--- ++Enable compilation option for driver GMAC ++ ++if MS_GMAC ++menu "MStar GMAC Driver" ++ ++ ++choice ++ prompt "Default Select PadMux" ++ default GMAC_TO_RMII ++ depends on MSTAR_KANO || ARCH_INFINITY2 ++ ++#config KANO_GMAC1_EPHY ++#bool "GMAC1 + Internal EPHY" ++#help ++# GMAC1 + Internal EPHY ++ ++config KANO_GMAC0_GPHY ++bool "GMAC0 + RGMII GPHY" ++help ++ GMAC0 + RGMII GPHY ++ ++config GMAC_TO_RMII ++bool "GMAC0 + RMII EPHY" ++help ++ GMAC0 + RMII EPHY ++ ++config KANO_GMAC1_GPHY ++bool "GMAC1 + RGMII GPHY" ++help ++ GMAC1 + RGMII GPHY ++ ++config GMAC1_TO_RMII ++bool "GMAC1 + RMII EPHY" ++help ++ GMAC1 + RMII EPHY ++endchoice ++ ++choice ++ prompt "Force MAC mode" ++ default GMAC_DETECT_FROM_PHY ++ ++config GMAC_DETECT_FROM_PHY ++bool "Auto-polling speed&duplex from phy" ++ ++config GMAC_FORCE_MAC_SPEED_100 ++bool "Force MAC speed to 100M" ++depends on GMAC1_TO_RMII || GMAC_TO_RMII ++endchoice ++ ++config GMAC_EXT_PHY_ADDR ++ hex "Phy Address" ++ default 0x1 ++ ++config GMAC_RX_Memory_Copy ++bool "Memory_Copy" ++ ++choice ++ prompt "Select RX Method" ++ default GMAC_Memory_Copy ++ ++config GMAC_RX_Memory_Copy ++bool "Memory_Copy" ++help ++ Use memcpy and additional RX buffer for RX callback function ++ ++config GMAC_RX_DMA ++bool "DMA" ++help ++ GMAC Direct access Kernel Memory in RX callback function. ++ K6, K6lite, k7 can only use one MIU for kernel Memory. ++ ++endchoice ++ ++config GMAC_RX_NAPI ++bool "Enable RX_NAPI" ++default y ++help ++ Enable NAPI Method. Disable interrupt during heavy tracffic. ++ ++ ++config GMAC_RX_NAPI_WEIGHT ++int "RX_NAPI_WEIGHT" ++depends on GMAC_RX_NAPI ++default 64 ++help ++ NAPI Weight ++ ++ ++config GMAC_RX_GRO ++bool "Enable RX_GRO" ++default y ++help ++ Enable Generic receive offload. Merge packet with same destination and source ++ ++ ++config GMAC_RX_DELAY_INTERRUPT ++bool "Enable RX Delay Interrupt" ++default y ++help ++ Enable RX Delay Interrupt. Reduce interrupt number. ++ ++ ++config GMAC_DELAY_INTERRUPT_NUMBER ++int "Packet Threshold" ++depends on GMAC_RX_DELAY_INTERRUPT ++default 64 ++help ++ MAX 255 ++ ++config GMAC_DELAY_INTERRUPT_TIMEOUT ++int "Timeout" ++depends on GMAC_RX_DELAY_INTERRUPT ++default 6 ++help ++ MAX 255 ++ ++choice ++ prompt "Select TX Queue" ++ default GMAC_TX_DESC_MODE if MSTAR_K6Lite ++ default GMAC_NEW_TX_QUEUE_V3 if MSTAR_K6 ++ default GMAC_TX_4_QUEUE ++ ++config GMAC_TX_4_QUEUE ++bool "Default TX Queue" ++help ++ Use default TX Queue 4. ++ ++config GMAC_NEW_TX_QUEUE_V3 ++bool "Enable Additional New TX Queue" ++depends on MSTAR_K6Lite || MSTAR_K6 || ARCH_INFINITY2 ++help ++ Enable New TX Queue. Larger TX Queue. Kayla support ++ ++config GMAC_TX_DESC_MODE ++bool "Enable TX dexcriptor Mode" ++depends on MSTAR_K6Lite || ARCH_INFINITY2 ++help ++ Enable TX dexcriptor Mode. Use DRAM for TX QUEUE. ++endchoice ++ ++config GMAC_NEW_TX_QUEUE_THRESHOLD_V3 ++int "New TX Queue Threshold" ++depends on GMAC_NEW_TX_QUEUE_V3 ++default 60 ++help ++ MAX 63 ++ ++config GMAC_SUPPLY_RNG ++bool "Supply to random number generator device" ++default n ++help ++ Supply to random number generator device ++ ++ ++config MSTAR_GMAC_HW_TX_CHECKSUM ++bool "Supply to hardware TX checksum" ++default n ++help ++ Supply to hardware TX checksum ++ ++config MSTAR_GMAC_JUMBO_PACKET ++bool "Supply to jumbo packet" ++default n ++help ++ Supply to jumbo packet ++ ++endmenu #"MStar GMAC Driver" ++ ++endif +diff --git a/drivers/sstar/gmac/Kconfig.old b/drivers/sstar/gmac/Kconfig.old +new file mode 100755 +index 000000000000..aea5551086d1 +--- /dev/null ++++ b/drivers/sstar/gmac/Kconfig.old +@@ -0,0 +1,266 @@ ++config MS_GMAC ++select NET ++select NET_ETHERNET ++select MII ++select PACKET ++select USE_POLICY_FWD ++select INET ++select NETDEVICES ++ ++tristate "GMAC" ++default n ++ ++---help--- ++Enable compilation option for driver GMAC ++ ++if MS_GMAC ++menu "MStar GMAC Driver" ++ ++ ++choice ++ prompt "Default Select PadMux" ++ default GMAC_TO_RMII ++ depends on MSTAR_KANO || ARCH_INFINITY2 ++ ++#config KANO_GMAC1_EPHY ++#bool "GMAC1 + Internal EPHY" ++#help ++# GMAC1 + Internal EPHY ++ ++config KANO_GMAC0_GPHY ++bool "GMAC0 + external GPHY" ++help ++ GMAC0 + external GPHY ++ ++config GMAC_TO_RMII ++bool "GMAC0 + external EPHY" ++help ++ GMAC0 + external EPHY ++ ++config KANO_GMAC1_GPHY ++bool "GMAC1 + external GPHY" ++help ++ GMAC1 + external GPHY ++ ++config GMAC1_TO_RMII ++bool "GMAC1 + external EPHY" ++help ++ GMAC1 + external EPHY ++endchoice ++ ++ ++choice ++ prompt "Select RX Method" ++ default GMAC_Memory_Copy ++ ++config GMAC_RX_Memory_Copy ++bool "Memory_Copy" ++help ++ Use memcpy and additional RX buffer for RX callback function ++ ++config GMAC_RX_DMA ++bool "DMA" ++help ++ GMAC Direct access Kernel Memory in RX callback function. ++ K6, K6lite, k7 can only use one MIU for kernel Memory. ++ ++endchoice ++ ++config GMAC_RX_NAPI ++bool "Enable RX_NAPI" ++default y ++help ++ Enable NAPI Method. Disable interrupt during heavy tracffic. ++ ++ ++config GMAC_RX_NAPI_WEIGHT ++int "RX_NAPI_WEIGHT" ++depends on GMAC_RX_NAPI ++default 64 ++help ++ NAPI Weight ++ ++ ++config GMAC_RX_GRO ++bool "Enable RX_GRO" ++default y ++help ++ Enable Generic receive offload. Merge packet with same destination and source ++ ++ ++config GMAC_RX_DELAY_INTERRUPT ++bool "Enable RX Delay Interrupt" ++default y ++help ++ Enable RX Delay Interrupt. Reduce interrupt number. ++ ++ ++config GMAC_DELAY_INTERRUPT_NUMBER ++int "Packet Threshold" ++depends on GMAC_RX_DELAY_INTERRUPT ++default 64 ++help ++ MAX 255 ++ ++config GMAC_DELAY_INTERRUPT_TIMEOUT ++int "Timeout" ++default 6 ++help ++ MAX 255 ++ ++ ++choice ++ prompt "Select TX Queue" ++ default GMAC_TX_DESC_MODE if MSTAR_K6Lite ++ default GMAC_NEW_TX_QUEUE_V3 if MSTAR_K6 ++ default GMAC_TX_4_QUEUE ++ ++config GMAC_TX_4_QUEUE ++bool "Default TX Queue" ++help ++ Use default TX Queue 4. ++ ++config GMAC_NEW_TX_QUEUE_V3 ++bool "Enable Additional New TX Queue" ++depends on MSTAR_K6Lite || MSTAR_K6 || ARCH_INFINITY2 ++help ++ Enable New TX Queue. Larger TX Queue. Kayla support ++ ++config GMAC_TX_DESC_MODE ++bool "Enable TX dexcriptor Mode" ++depends on MSTAR_K6Lite || ARCH_INFINITY2 ++help ++ Enable TX dexcriptor Mode. Use DRAM for TX QUEUE. ++ ++endchoice ++ ++if GMAC_NEW_TX_QUEUE_V3 ++config GMAC_NEW_TX_QUEUE_THRESHOLD_V3 ++int "New TX Queue Threshold" ++default 60 ++help ++ MAX 63 ++ ++endif ++ ++#config MSTAR_GMAC_V2 ++#bool "GMAC V2" ++#default n ++#help ++# GMAC V2 architecture. Zero memcpy in RX, pre-allocate ring buffer ++ ++if MSTAR_GMAC_V2 ++config GMAC_RX_CMA ++bool "Support RX skb allocated from CMA buffer" ++default n ++help ++ Support RX skb allocated from CMA buffer ++ ++config GMAC_TX_ENHANCEMENT ++bool "Select TX enhancement" ++default n ++help ++ Select TX enhancement ++ ++if GMAC_TX_ENHANCEMENT ++ ++choice ++ prompt "TX enhancement select" ++ default GMAC_NEW_TX_QUEUE ++ ++config GMAC_NEW_TX_QUEUE ++bool "Use new TX queue hardware design" ++help ++ Use new TX queue hardware design, it's now supported on K6. ++ ++if GMAC_NEW_TX_QUEUE ++config GMAC_NEW_TX_QUEUE_THRESHOLD ++int "New TX queue threshold" ++default 60 ++help ++ New TX queue threshold ++endif ++ ++config GMAC_TX_ZERO_COPY_SW_QUEUE ++bool "Support TX zero copy with software queue" ++help ++ Support TX zero copy with software queue ++ ++endchoice ++ ++endif ++ ++config GMAC_ISR_BOTTOM_HALF ++bool "Support ISR bottom-half" ++default n ++help ++ Support ISR bottom-half ++ ++if GMAC_ISR_BOTTOM_HALF ++ ++choice ++ prompt "GMAC ISR BH select" ++ default GMAC_ISR_BH_NAPI ++ ++config GMAC_ISR_BH_TASKLET ++bool "Use tasklet for bottom-half" ++help ++ Use tasklet for bottom-half ++ ++config GMAC_ISR_BH_NAPI ++bool "Use NAPI for bottom-half" ++help ++ Use NAPI for bottom-half ++ ++if GMAC_ISR_BH_NAPI ++config GMAC_NAPI_WEIGHT ++int "NAPI weight" ++default 64 ++help ++ NAPI weight ++ ++config GMAC_NAPI_GRO ++bool "Use NAPI GRO mechanism" ++default n ++help ++ Use NAPI GRO mechanism ++endif ++ ++endchoice ++ ++endif ++endif ++ ++config GMAC_SUPPLY_RNG ++bool "Supply to random number generator device" ++default n ++help ++ Supply to random number generator device ++ ++#config GMAC_ETHERNET_ALBANY ++#bool "Supply to internel PHY" ++#default n ++#help ++# Supply to internel PHY ++ ++config MSTAR_GMAC_HW_TX_CHECKSUM ++bool "Supply to hardware TX checksum" ++default n ++help ++ Supply to hardware TX checksum ++ ++config MSTAR_GMAC_JUMBO_PACKET ++bool "Supply to jumbo packet" ++default n ++help ++ Supply to jumbo packet ++ ++#config MSTAR_GMAC_RMII_DOWNGRADE_MODE ++#bool "Supply GMAC to use external EPHY by RMII" ++#default n ++#help ++# Supply to GMAC use external RMII EPHY ++ ++endmenu #"MStar GMAC Driver" ++ ++endif +diff --git a/drivers/sstar/gmac/Makefile b/drivers/sstar/gmac/Makefile +new file mode 100755 +index 000000000000..36d04260dff2 +--- /dev/null ++++ b/drivers/sstar/gmac/Makefile +@@ -0,0 +1,24 @@ ++# ++# Makefile for MStar GMAC device drivers. ++# ++ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/gmac ++EXTRA_CFLAGS += -Idrivers/sstar/gmac/hal/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++# specific options ++# EXTRA_CFLAGS += -DRED_LION ++# files ++obj-$(CONFIG_MS_GMAC) := mdrv-gmac.o ++ ++ ++mdrv-gmac-objs := mdrv_gmac_v3.o drv_mdio_sw.o ++ ++mdrv-gmac-objs += hal/$(CONFIG_MSTAR_CHIP_NAME)/mhal_gmac_v3.o ++ ++ ++ccflags-y += -Werror +\ No newline at end of file +diff --git a/drivers/sstar/gmac/drv_mdio_sw.c b/drivers/sstar/gmac/drv_mdio_sw.c +new file mode 100755 +index 000000000000..5b90f0486279 +--- /dev/null ++++ b/drivers/sstar/gmac/drv_mdio_sw.c +@@ -0,0 +1,427 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include"mdrv_types.h" ++#include"gpio.h" ++ ++/* bb:bit-bang, Use software to control serial communication at general-purpose I/O pins*/ ++//#define MDC PAD_SNR0_GPIO0 /* MDC GPIO PAD */ ++//#define MDIO PAD_SNR0_GPIO1 /* MDIO GPIO PAD */ ++#define MDIO_DELAY 250 ++#define MDIO_READ_DELAY 350 ++ ++/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit ++ * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. ++ * */ ++#define MII_ADDR_C45 (1<<30) ++ ++#define MDIO_C45 (1<<15) ++#define MDIO_C45_ADDR (MDIO_C45 | 0) ++#define MDIO_C45_READ (MDIO_C45 | 3) ++#define MDIO_C45_WRITE (MDIO_C45 | 1) ++ ++#define MDIO_READ 2 ++#define MDIO_WRITE 1 ++ ++//#define MDIO_SETUP_TIME 10 ++//#define MDIO_HOLD_TIME 10 ++ ++//#define READ_REG 0x37 ++//#define WRITE_REG 0x38 ++ ++extern void MDrv_GPIO_Pad_Oen(U16 u16IndexGPIO); ++extern void MDrv_GPIO_Pad_Odn(U16 u16IndexGPIO); ++extern void MDrv_GPIO_Pull_High(U16 u16IndexGPIO); ++extern void MDrv_GPIO_Pull_Low(U16 u16IndexGPIO); ++extern U8 MDrv_GPIO_Pad_Read(U16 u16IndexGPIO); ++ ++#define MDIO_C45_TEST 0 ++ ++ ++ ++typedef struct gpio_ctrl_blk{ ++ int pin; ++ int value; ++}gpio_cblk_t; ++ ++typedef struct phy_reg_blk{ ++ unsigned int phy_address; ++ unsigned int reg_address; ++ unsigned int reg_value; ++}phy_reg_cblk_t; ++ ++gpio_cblk_t gpio_mdc_dev; ++gpio_cblk_t gpio_mdio_dev; ++ ++#define MDIO_DEV_ID 't' ++#define READ_REG _IOWR (MDIO_DEV_ID,0x37,phy_reg_cblk_t) ++#define WRITE_REG _IOWR (MDIO_DEV_ID,0x38,phy_reg_cblk_t) ++ ++static void MDC_OUT(void); ++static void MDIO_OUT(void); ++static void MDIO_IN(void); ++static void MDC_H(void); ++static void MDC_L(void); ++static int GET_MDIO(void); ++static void SET_MDIO(int val); ++ ++ ++/* Set MDC as an output pin, set before the MDC output clock */ ++static void MDC_OUT(void) ++{ ++ //gpio_cblk_t gpio_dev; ++ //gpio_dev.pin = MDC; ++ MDrv_GPIO_Pad_Oen(gpio_mdc_dev.pin); ++} ++ ++/* Set MDIO's gpio pin as an output pin */ ++static void MDIO_OUT(void) ++{ ++ //gpio_cblk_t gpio_dev; ++ //gpio_dev.pin = MDIO; ++ MDrv_GPIO_Pad_Oen(gpio_mdio_dev.pin); ++} ++ ++/* Set the gpio pin of MDIO as an input pin */ ++static void MDIO_IN(void) ++{ ++ //gpio_cblk_t gpio_dev; ++ //gpio_dev.pin = MDIO; ++ MDrv_GPIO_Pad_Odn(gpio_mdio_dev.pin); ++} ++ ++/* MDC output high level, called after MDC is set to output */ ++static void MDC_H(void) ++{ ++ //gpio_cblk_t gpio_dev; ++ ++ //gpio_dev.pin = MDC; ++ //gpio_dev.value = 1; ++ MDrv_GPIO_Pull_High(gpio_mdc_dev.pin); ++} ++ ++/* MDC output low level, called after MDC is set to output */ ++static void MDC_L(void) ++{ ++ //gpio_cblk_t gpio_dev; ++ ++ //gpio_dev.pin = MDC; ++ //gpio_dev.value = 0; ++ MDrv_GPIO_Pull_Low(gpio_mdc_dev.pin); ++} ++ ++/* Get MDIO data and get only one bit */ ++static int GET_MDIO(void) ++{ ++ //gpio_cblk_t gpio_dev; ++ ++ //gpio_dev.pin = MDIO; ++ gpio_mdio_dev.value = MDrv_GPIO_Pad_Read(gpio_mdio_dev.pin); ++ ++ return gpio_mdio_dev.value; ++} ++ ++/* Set MDIO data, one bit*/ ++static void SET_MDIO(int val) ++{ ++ //gpio_cblk_t gpio_dev; ++ ++ //gpio_dev.pin = MDIO; ++ //gpio_dev.value = val; ++ if(val == 0) ++ MDrv_GPIO_Pull_Low(gpio_mdio_dev.pin); ++ else ++ MDrv_GPIO_Pull_High(gpio_mdio_dev.pin); ++} ++ ++ ++/* MDIO sends a bit of data, MDIO must have been configured as output */ ++static void mdio_bb_send_bit(int val) ++{ ++ MDC_OUT(); ++ SET_MDIO(val); ++ ndelay(MDIO_DELAY); ++ MDC_L(); ++ ndelay(MDIO_DELAY); ++ MDC_H(); ++} ++ ++/* MDIO gets a bit of data, MDIO must have been configured as input. */ ++static int mdio_bb_get_bit(void) ++{ ++ int value; ++ ++ MDC_OUT(); ++ ndelay(MDIO_DELAY); ++ MDC_L(); ++ ndelay(MDIO_READ_DELAY); ++// ndelay(MDIO_DELAY); ++ MDC_H(); ++ ++ value = GET_MDIO(); ++ ++ return value; ++} ++ ++ /* ++ * MDIO sends a data and MDIO must be configured as an output mode. ++ * */ ++static void mdio_bb_send_num(unsigned int value ,int bits) ++{ ++ int i; ++ MDIO_OUT(); ++ ++ for(i = bits - 1; i >= 0; i--) ++ mdio_bb_send_bit((value >> i) & 1); ++} ++ ++ /* ++ * MDIO gets one data, MDIO must be configured as input mode. ++ * */ ++static int mdio_bb_get_num(int bits) ++{ ++ int i; ++ int ret = 0; ++ for(i = bits - 1; i >= 0; i--) ++ { ++ ret <<= 1; ++ ret |= mdio_bb_get_bit(); ++ } ++ ++ return ret; ++} ++ ++ ++ ++/* Utility to send the preamble, address, and ++* register (common to read and write). ++*/ ++static void mdio_bb_cmd(int op,int phy,int reg) ++{ ++ int i = 0 ; ++ MDIO_OUT(); //Set the MDIO pin as an output pin ++ ++ /*Send 32bit 1, this frame prefix field is not required, MDIO operation of some physical layer chips does not have this domain*/ ++ for(i = 0; i < 32; i++) ++ mdio_bb_send_bit(1); ++ ++ ++ /* Send start bit (01), and read opcode (10), write opcode (01) ++ * Clause 45 operation, the starting bit is (00), (11) is read, (10) is written ++ */ ++#if MDIO_C45_TEST ++ mdio_bb_send_bit(0); ++ if(op & MDIO_C45) ++ mdio_bb_send_bit(0); ++ else ++ mdio_bb_send_bit(1); ++#else ++ mdio_bb_send_bit(0); ++ mdio_bb_send_bit(1); ++ ++#endif ++ ++ mdio_bb_send_bit((op >> 1) & 1); ++ mdio_bb_send_bit((op >> 0) & 1); ++ ++ mdio_bb_send_num(phy,5); ++ mdio_bb_send_num(reg,5); ++ ++} ++ ++#if MDIO_C45_TEST ++static int mdio_bb_cmd_addr(int phy,int addr) ++{ ++ unsigned int dev_addr = (addr >> 16) & 0x1F; ++ unsigned int reg = addr & 0xFFFF; ++ ++ mdio_bb_cmd(MDIO_C45_ADDR,phy,dev_addr); ++ ++ /* send the turnaround (10) */ ++ mdio_bb_send_bit(1); ++ mdio_bb_send_bit(0); ++ ++ mdio_bb_send_num(reg,16); ++ ++ MDIO_IN(); ++ mdio_bb_get_bit(); ++ ++ return dev_addr; ++} ++#endif ++ ++void mdio_set_turnaround(void) ++{ ++ int i = 0; ++ ++ MDIO_IN(); ++ MDC_OUT(); ++ for(i=0;i<2;i++) ++ { ++ ndelay(MDIO_DELAY); ++ MDC_L(); ++ ndelay(MDIO_DELAY); ++ MDC_H(); ++ } ++} ++ ++unsigned int mdio_bb_read(int phy,int reg) ++{ ++ unsigned int ret,i; ++ ++#if MDIO_C45_TEST ++ /* Whether the register is satisfied with the C45 flag */ ++ if(reg & MII_ADDR_C45) ++ { ++ reg = mdio_bb_cmd_addr(phy,reg); ++ mdio_bb_cmd(MDIO_C45_READ,phy,reg); ++ } ++ else ++ mdio_bb_cmd(MDIO_READ,phy,reg); ++#else ++ mdio_bb_cmd(MDIO_READ,phy,reg); ++#endif ++ MDIO_IN(); ++ //mdio_set_turnaround(); ++ /* check the turnaround bit: the PHY should be driving it to zero */ ++ if(mdio_bb_get_bit() != 0) ++ { ++ /* PHY didn't driver TA low -- flush any bits it may be trying to send*/ ++ for(i = 0; i < 32; i++) ++ mdio_bb_get_bit(); ++ return 0xFFFF; ++ } ++ ++ ret = mdio_bb_get_num(16); ++ mdio_bb_get_bit(); ++ ++ return ret; ++} ++ ++unsigned int mdio_bb_write(unsigned int phy,unsigned int reg,unsigned int val) ++{ ++#if MDIO_C45_TEST ++ if(reg & MII_ADDR_C45) ++ { ++ reg = mdio_bb_cmd_addr(phy,reg); ++ mdio_bb_cmd(MDIO_C45_WRITE,phy,reg); ++ } ++ else ++ mdio_bb_cmd(MDIO_WRITE,phy,reg); ++#else ++ mdio_bb_cmd(MDIO_WRITE,phy,reg); ++#endif ++ ++#if 1 ++ /* send the turnaround (10) */ ++ mdio_bb_send_bit(1); ++ mdio_bb_send_bit(0); ++#else ++ mdio_set_turnaround(); ++#endif ++ mdio_bb_send_num(val,16); ++ ++ MDIO_IN(); ++ //mdio_bb_get_bit(); ++ ++ return 0; ++} ++ ++void mdio_bb_init(int pin_mdio, int pin_mdc) ++{ ++ gpio_mdio_dev.pin = pin_mdio; ++ gpio_mdc_dev.pin = pin_mdc; ++} ++/* ++static int mdio_drv_open(struct inode *inode, struct file *file ) ++{ ++ return 0; ++} ++ ++static int mdio_drv_release(struct inode *inode, struct file *file ) ++{ ++ return 0; ++} ++ ++static long mdio_drv_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ phy_reg_cblk_t phy_reg; ++ int ret = 0; ++ ++ void __user *argp = (void __user *)arg; ++ if( argp==NULL ) ++ { ++ return -EFAULT; ++ } ++ ++ if (copy_from_user(&phy_reg, argp, sizeof(phy_reg_cblk_t))) { ++ return -EFAULT; ++ } ++ ++ switch (cmd) { ++ case READ_REG: ++ phy_reg.reg_value = mdio_bb_read(phy_reg.phy_address,phy_reg.reg_address); ++ if(copy_to_user(argp,&phy_reg,sizeof(phy_reg_cblk_t))) ++ { ++ return -EFAULT; ++ } ++ break; ++ case WRITE_REG: ++ ret = mdio_bb_write(phy_reg.phy_address,phy_reg.reg_address,phy_reg.reg_value); ++ default: ++ return -EINVAL; ++ ++ } ++ ++ return 0; ++} ++ ++static struct file_operations mdio_drv_fileops = { ++ .owner = THIS_MODULE, ++ .open = mdio_drv_open, ++ .unlocked_ioctl = mdio_drv_unlocked_ioctl, ++ .release = mdio_drv_release ++}; ++ ++static struct miscdevice mdio_dev = { ++ MISC_DYNAMIC_MINOR, ++ "mdio_dev", ++ &mdio_drv_fileops, ++}; ++ ++int mdio_drv_init(void) ++{ ++ int ret = 0; ++ ++ ret = misc_register(&mdio_dev); ++ if(ret != 0) ++ { ++ ret = -EFAULT; ++ return ret; ++ } ++ printk("mdio_drv_init ok\n"); ++ return 0; ++} ++ ++void mdio_drv_exit(void) ++{ ++ misc_deregister(&mdio_dev); ++ printk("mdio_drv_exit ok\n"); ++} ++ ++module_init(mdio_drv_init); ++module_exit(mdio_drv_exit); ++MODULE_LICENSE("GPL");*/ +\ No newline at end of file +diff --git a/drivers/sstar/gmac/hal/infinity2/mhal_gmac.c.old b/drivers/sstar/gmac/hal/infinity2/mhal_gmac.c.old +new file mode 100755 +index 000000000000..e2c556d8b237 +--- /dev/null ++++ b/drivers/sstar/gmac/hal/infinity2/mhal_gmac.c.old +@@ -0,0 +1,1508 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_gmac.c ++/// @brief GMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_gmac.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct _MHalBasicConfigGMAC ++{ ++ u8 connected; // 0:No, 1:Yes ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _MHalBasicConfigGMAC MHalBasicConfigGMAC; ++ ++struct _MHalUtilityVarsGMAC ++{ ++ u32 cntChkCableConnect; ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ u8 flagISR_INT_DONE; ++}; ++typedef struct _MHalUtilityVarsGMAC MHalUtilityVarsGMAC; ++ ++MHalBasicConfigGMAC MHalGMACThisBCE; ++MHalUtilityVarsGMAC MHalGMACThisUVE; ++ ++#define MHal_MAX_INT_COUNTER 100 ++//------------------------------------------------------------------------------------------------- ++// GMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_GMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ phys_addr_t address = GMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++void MHal_GMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ phys_addr_t address = GMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u8* ) address ) = val; ++} ++ ++u32 MHal_GMAC_ReadReg32( u32 xoffset ) ++{ ++ phys_addr_t address = GMAC_REG_ADDR_BASE + xoffset*2; ++ ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++} ++ ++void MHal_GMAC_WritReg32( u32 xoffset, u32 xval ) ++{ ++ phys_addr_t address = GMAC_REG_ADDR_BASE + xoffset*2; ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++} ++ ++u32 MHal_GMAC_ReadRam32( phys_addr_t uRamAddr, u32 xoffset) ++{ ++ return (*( u32 * ) ( ( char * ) uRamAddr + xoffset ) ); ++} ++ ++void MHal_GMAC_WritRam32( phys_addr_t uRamAddr, u32 xoffset, u32 xval ) ++{ ++ *( ( u32 * ) ( ( char * ) uRamAddr + xoffset ) ) = xval; ++} ++ ++void MHal_GMAC_Write_SA1_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA2_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA3_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA4_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W GMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GMAC_update_HSH(u32 mc0, u32 mc1) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSL, mc0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CTL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CTL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CTL( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CTL, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CFG( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CFG( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RBQP( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RBQP( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TAR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TAR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TCR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TCR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TCR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_TSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TSR ); ++} ++ ++void MHal_GMAC_Write_RSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_RSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RSR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_ISR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_ISR, xval ); ++} ++ ++u32 MHal_GMAC_Read_ISR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ISR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IER( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IER ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IER( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IER, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IDR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IDR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IDR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IDR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IMR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IMR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MAN( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_MAN( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_MAN, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_BUFF( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFF, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_BUFF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RDPTR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFFRDPTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFRDPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFWRPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_FRA( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_FRA ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_OK( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_OK ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SEQE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SEQE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ALE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ALE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_LCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_LCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ECOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ECOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TUE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TUE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CSE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CSE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ROVR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ROVR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ELR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ELR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RJB( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RJB ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_USF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_USF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SQEE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SQEE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0100( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0100 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0100( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0100, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0104, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0108( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0108 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0108( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0108, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 414 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0414( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0414 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 414 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0414( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0414, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 418 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0418( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0418, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 418 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0418( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0418 ); ++} ++ ++void MHal_GMAC_Set_Tx_JULIAN_T(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_GMAC_WritReg32(i, value); ++ } ++ ++} ++ ++u32 MHal_GMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x134) & 0x00f00000) >> 20; ++} ++ ++void MHal_GMAC_Set_Rx_FIFO_Enlarge(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++u32 MHal_GMAC_Get_Rx_FIFO_Enlarge(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x134) & 0x03000000) >> 24; ++} ++ ++void MHal_GMAC_Set_Miu_Priority(u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x100); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x100, value); ++} ++ ++u32 MHal_GMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x100) & 0x00080000) >> 19; ++} ++ ++void MHal_GMAC_Set_Tx_Hang_Fix_ECO(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_MIU_Out_Of_Range_Fix(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_Rx_Tx_Burst16_Mode(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_Rx_Byte_Align_Offset(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x11c); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_GMAC_WritReg32(0x11c, value); ++ ++ value = MHal_GMAC_ReadReg32(0x120); ++ value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_GMAC_WritReg32(0x120, value); ++ ++ value = MHal_GMAC_ReadReg32(0x124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_GMAC_WritReg32(0x124, value); ++ ++ value = MHal_GMAC_ReadReg32(0x100); ++ value |= 0x00000040; ++ MHal_GMAC_WritReg32(0x100, value); ++} ++ ++void MHal_GMAC_Set_Miu_Highway(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_HW_init(void) ++{ ++ MHal_GMAC_Set_Miu_Priority(1); ++// MHal_GMAC_Set_Tx_JULIAN_T(4); ++// MHal_GMAC_Set_Rx_Tx_Burst16_Mode(1); ++// MHal_GMAC_Set_Rx_FIFO_Enlarge(2); ++// MHal_GMAC_Set_Tx_Hang_Fix_ECO(1); ++// MHal_GMAC_Set_MIU_Out_Of_Range_Fix(1); ++// #ifdef GMAC_RX_BYTE_ALIGN_OFFSET ++// MHal_GMAC_Set_Rx_Byte_Align_Offset(2); ++// #endif ++// MHal_GMAC_WritReg32(GMAC_REG_JULIAN_0138, MHal_GMAC_ReadReg32(GMAC_REG_JULIAN_0138) | 0x00000001); ++// MHal_GMAC_Set_Miu_Highway(1); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval |= GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval &= ~GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_write_phy( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ phys_addr_t uRegBase = GMAC_INTERNEL_PHY_REG_BASE; ++ ++ phy_addr =0; ++ ++ *(volatile unsigned int *)(uRegBase + address*4) = value; ++ udelay( 1 ); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_W) | (( phy_addr & 0x1F ) << GMAC_PHY_ADDR_OFFSET ) ++ | ( address << GMAC_PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ ++ MHal_GMAC_Write_MAN( uRegVal ); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ MHal_GMAC_Write_CTL(uCTL); ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_read_phy( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ phys_addr_t uRegBase = GMAC_INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(GMAC_INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(GMAC_INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_R) ++ | ((phy_addr & 0x1f) << GMAC_PHY_ADDR_OFFSET) | (address << GMAC_PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ MHal_GMAC_Write_MAN(uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ *value = ( MHal_GMAC_Read_MAN() & 0x0000ffff ); ++ MHal_GMAC_Write_CTL(uCTL); ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++#ifndef KANO_GMAC0 ++ ++void MHal_GMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfe; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) // 1000 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfd; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++#else ++void MHal_GMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal &= 0xbf; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 1000 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x80; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 100 Full Duplex */ ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else ++ { ++ /* 100 Half Duplex */ ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal &= 0x7f; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 10 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ else ++ { ++ /* 10 Half Duplex */ ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++#endif ++ ++void MHal_GMAC_link_led_on() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x01; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++void MHal_GMAC_link_led_off() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x03; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++u8 MHal_GMAC_CalcMACHash( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_GMAC_get_SA1H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1H ); ++} ++ ++u32 MHal_GMAC_get_SA1L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1L ); ++} ++ ++u32 MHal_GMAC_get_SA2H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2H ); ++} ++ ++u32 MHal_GMAC_get_SA2L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2L ); ++} ++ ++void MHal_GMAC_Write_SA1H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, xval ); ++} ++ ++void MHal_GMAC_Write_SA1L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, xval ); ++} ++ ++void MHal_GMAC_Write_SA2H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, xval ); ++} ++ ++void MHal_GMAC_Write_SA2L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, xval ); ++} ++ ++void* MDev_GMAC_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Check INT Done ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CheckINTDone( void ) ++{ ++ u32 retIntStatus; ++ retIntStatus = MHal_GMAC_Read_ISR(); ++ MHalGMACThisUVE.cntChkINTCounter = ( MHalGMACThisUVE.cntChkINTCounter % ++ MHal_MAX_INT_COUNTER ); ++ MHalGMACThisUVE.cntChkINTCounter ++; ++ if ( ( retIntStatus & GMAC_INT_DONE ) || ++ ( MHalGMACThisUVE.cntChkINTCounter == ( MHal_MAX_INT_COUNTER - 1 ) ) ) ++ { ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x01; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++extern unsigned char gmac_phyaddr; ++//------------------------------------------------------------------------------------------------- ++// MAC cable connection detection ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CableConnection( void ) ++{ ++ u32 retValue = 0; ++ u32 word_ETH_MAN = 0x00000000; ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ ++ MHal_GMAC_Write_CTL( 0x00000010 | word_ETH_CTL ); ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &word_ETH_MAN); ++ ++ if ( word_ETH_MAN & BMSR_LSTATUS ) ++ { ++ retValue = 1; ++ } ++ else ++ { ++ retValue = 0; ++ } ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Negotiation PHY ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_NegotiationPHY( void ) ++{ ++ // Set PHY -------------------------------------------------------------- ++ u32 retValue = 0; ++ u32 bmsr; ++ ++ // IMPORTANT: Get real duplex by negotiation with peer. ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_Write_CTL( 0x0000001C | word_ETH_CTL ); ++ ++ MHalGMACThisBCE.duplex = 1; // Set default as Half-duplex if negotiation fails. ++ retValue = 1; ++ ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHalGMACThisUVE.cntChkCableConnect = 0; ++ ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &bmsr); ++ if ( (bmsr & BMSR_100FULL) || (bmsr & BMSR_10FULL) ) ++ { ++ MHalGMACThisBCE.duplex = 2; ++ retValue = 2; ++ } ++ else ++ { ++ MHalGMACThisBCE.duplex = 1; ++ retValue = 1; ++ } ++ ++ // NOTE: REG_ETH_CFG must be set according to new ThisGMACBCE.duplex. ++ ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ // Set PHY -------------------------------------------------------------- ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_timer_callback( unsigned long value ) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_IER(); ++ uRegVal |= ( GMAC_INT_RCOM ); ++ MHal_GMAC_Write_IER( uRegVal ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++#ifndef KANO_GMAC0 ++ ++void MHal_GMAC_Power_On_Clk( void ) ++{ ++ u8 uRegVal; ++ int clk_handle; ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal &= ~(0x80); ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal &= ~(0x04); ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ ++ //printk("internal ephy flow\n"); ++ /* Set reg_xmii_type as int PHY mode */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set gmac ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable gmac tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x08); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x08); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* Init ePHY */ ++ //gain shift ++ MHal_GMAC_WritReg8(0x0032, 0xb4, 0x02); ++ ++ //det max ++ MHal_GMAC_WritReg8(0x0032, 0x4f, 0x02); ++ ++ //det min ++ MHal_GMAC_WritReg8(0x0032, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_GMAC_WritReg8(0x0032, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_GMAC_WritReg8(0x0031, 0x72, 0xa0); ++ ++ MHal_GMAC_WritReg8(0x0032, 0xfc, 0x00); ++ MHal_GMAC_WritReg8(0x0032, 0xfd, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xa1, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0xcc, 0x40); ++ MHal_GMAC_WritReg8(0x0032, 0xbb, 0x04); ++ MHal_GMAC_WritReg8(0x0033, 0x3a, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xf1, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0x8a, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0x3b, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0xc4, 0x44); ++ MHal_GMAC_WritReg8(0x0033, 0x80, 0x30); ++ ++ //100 gat ++ MHal_GMAC_WritReg8(0x0033, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_GMAC_WritReg8(0x0033, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_GMAC_WritReg8(0x0033, 0x39, 0x41); ++ ++ //Low power mode ++ MHal_GMAC_WritReg8(0x0033, 0xf2, 0xf5); ++ MHal_GMAC_WritReg8(0x0033, 0xf3, 0x0d); ++ ++ // Prevent packet drop by inverted waveform ++ MHal_GMAC_WritReg8(0x0031, 0x79, 0xd0); ++ MHal_GMAC_WritReg8(0x0031, 0x77, 0x5a); ++ ++ //10T waveform ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xac, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xad, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xae, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xaf, 0x19); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0xab, 0x28); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ ++ //Disable eee ++ MHal_GMAC_WritReg8(0x0031, 0x2d, 0x7c); ++ ++ //speed up timing recovery ++ MHal_GMAC_WritReg8(0x0032, 0xf5, 0x02); ++ ++ //signal_det_k ++ MHal_GMAC_WritReg8(0x0032, 0x0f, 0xc9); ++ ++ //snr_h ++ MHal_GMAC_WritReg8(0x0032, 0x89, 0x50); ++ MHal_GMAC_WritReg8(0x0032, 0x8b, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0x8e, 0x0e); ++ MHal_GMAC_WritReg8(0x0032, 0x90, 0x04); ++#else ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set GMAC ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable GMAC tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x00); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x00); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* IO setting, enable TX delay */ ++ MHal_GMAC_WritReg8(0x0033, 0xb2, 0x88); ++ MHal_GMAC_WritReg8(0x0033, 0xb3, 0x80); ++ MHal_GMAC_WritReg8(0x0033, 0xb4, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xb0, 0xac); ++ MHal_GMAC_WritReg8(0x0033, 0xb1, 0x00); ++ ++ /* Enable GT1 */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0e, 0x39); ++ uRegVal &= ~(0x01); ++ MHal_GMAC_WritReg8(0x0e, 0x39, uRegVal); ++ ++ /* Digital synthesizer */ ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x1b); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //Enable GPHY RX delay ++ //MHal_GMAC_enable_mdi(); ++ //MHal_GMAC_Write_MAN( 0x507e0007 ); ++ //MHal_GMAC_Write_MAN( 0x507a00a4 ); ++ //MHal_GMAC_Write_MAN( 0x5072ad91 ); ++ //MHal_GMAC_Write_MAN( 0x507e0000 ); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++#endif ++ ++} ++ ++#else ++ ++void MHal_GMAC_Power_On_Clk( void ) ++{ ++ u8 uRegVal; ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ /* Set GMAC ahb clock to 172MHZ */ ++ MHal_GMAC_WritReg8(0x100a, 0x03, 0x04); ++ ++ /* Enable GMAC tx clock */ ++ /* Enable GMAC rx clock */ ++ /* IO setting, enable TX delay */ ++ MHal_GMAC_WritReg8(0x121f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x121f, 0x23, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x24, 0x80); ++ MHal_GMAC_WritReg8(0x121f, 0x25, 0x28); ++ MHal_GMAC_WritReg8(0x121f, 0x26, 0x02); ++ MHal_GMAC_WritReg8(0x121f, 0x27, 0x0e); ++ MHal_GMAC_WritReg8(0x121f, 0x20, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x21, 0x02); ++ ++ /* Enable GT0 */ ++ MHal_GMAC_WritReg8(0x101e, 0x0c, 0x01); ++ ++ /* Digital synthesizer */ ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x1b); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //Enable GPHY RX delay ++ MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++} ++ ++#endif ++ ++ ++void MHal_GMAC_Power_Off_Clk( void ) ++{ ++ u32 uRegVal; ++ ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal |= 0x80; ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal |= 0x04; ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++} +diff --git a/drivers/sstar/gmac/hal/infinity2/mhal_gmac.h.old b/drivers/sstar/gmac/hal/infinity2/mhal_gmac.h.old +new file mode 100755 +index 000000000000..39a192572f1a +--- /dev/null ++++ b/drivers/sstar/gmac/hal/infinity2/mhal_gmac.h.old +@@ -0,0 +1,417 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file GMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief GMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_GMAC__ ++#define __DRV_GMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++//#define GMAC_RX_SOFTWARE_DESCRIPTOR ++#define GMAC_SOFTWARE_DESCRIPTOR ++#define GMAC_RX_CHECKSUM ++#define GMAC_INT_JULIAN_D ++#define GMAC_CHIP_FLUSH_READ ++#define GMAC_TX_QUEUE_4 ++//#define GMAC_NAPI ++#define GMAC_TX_COUNT (13) //offset of TX counter in TSR ++#define GMAC_LINK_LED_CONTROL ++ ++// Workaround for MST231E-D01A ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++#define KANO_GMAC0 ++#endif ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++#define TX_SW_QUEUE_SIZE (1024) //effected size = TX_RING_SIZE - 1 ++#define TX_DESC_CLEARED 0 ++#define TX_DESC_WROTE 1 ++#define TX_DESC_READ 2 ++#define TX_FIFO_SIZE 4 //HW FIFO size ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++#ifndef KANO_GMAC0 ++#define E_IRQEXPH_SECEMAC E_IRQHYPH_SECGMAC //aliasing for interrupt enum (GMAC1 & Internal) ++#else ++#define E_IRQEXPH_SECEMAC E_IRQ_GMAC //aliasing for interrupt enum (GMAC0) ++#endif ++#ifdef TX_QUEUE_4 ++#define GMAC_INT_MASK (0xdff) ++#else ++#define GMAC_INT_MASK (0xdff) ++#endif ++ ++#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++//#define GMAC_RX_BYTE_ALIGN_OFFSET ++#endif ++// Compiler Switches ++#define GMAC_REG_BIT_MAP ++#define GMAC_URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define GMAC_SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define GMAC_CHECKSUM_ENABLE 0x0FE ++#define GMAC_RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_GMAC_MOA 1 // System Type ++#define GMAC_SPEED_100 100 ++ ++#if defined(CONFIG_ARM) ++#define mstar_pm_base 0xFD000000 ++#endif ++ ++#define GMAC_ALLFF 0xFFFFFFFF ++#define GMAC_ABSO_MEM_BASE 0xA0000000//GMAC_ABSO_MEM_BASE 0xA0000000 ++#define GMAC_INTERNEL_PHY_REG_BASE mstar_pm_base + (0x3100UL<<1) ++ ++#define GMAC_RIU_REG_BASE mstar_pm_base ++ ++#define GMAC_ABSO_PHY_BASE 0x80000000//GMAC_ABSO_MEM_BASE ++#define GMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define GMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define GMAC_BUFFER_MEM_SIZE 0x0004000 ++#define GMAC_MAX_TX_QUEUE 1000 ++// Base address here: ++#define GMAC_MIU0_BUS_BASE MSTAR_MIU0_BUS_BASE ++#ifndef KANO_GMAC0 ++#define GMAC_REG_ADDR_BASE mstar_pm_base + (0x122000UL<<1) // The register address base. Depends on system define. ++#else ++#define GMAC_REG_ADDR_BASE mstar_pm_base + (0x121b00UL<<1) // The register address base. Depends on system define. ++#endif ++ ++#ifdef CONFIG_MSTAR_GMAC_V2 ++#define GMAC_RBQP_LENG 0x400//0x0100 0x40// // ==?descriptors ++#define GMAC_SOFTWARE_DESC_LEN 0x800 ++#else ++#define GMAC_RBQP_LENG 0x20//0x0100 0x40// // ==?descriptors ++#define GMAC_SOFTWARE_DESC_LEN 0x4000 ++#endif ++#define GMAC_MAX_RX_DESCR GMAC_RBQP_LENG//32 /* max number of receive buffers */ ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++#define GMAC_RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define GMAC_RX_BUFFER_SIZE (GMAC_RBQP_LENG*GMAC_SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define GMAC_RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define GMAC_RX_BUFFER_SIZE (0x2000< ++#include ++#include ++#include ++#include ++#include ++//#include ++#include "mhal_gmac_v3.h" ++//#include "chip_int.h" ++#include"gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct _MHalBasicConfigGMAC ++{ ++ u8 connected; // 0:No, 1:Yes ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _MHalBasicConfigGMAC MHalBasicConfigGMAC; ++ ++struct _MHalUtilityVarsGMAC ++{ ++ u32 cntChkCableConnect; ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ u8 flagISR_INT_DONE; ++}; ++typedef struct _MHalUtilityVarsGMAC MHalUtilityVarsGMAC; ++ ++MHalBasicConfigGMAC MHalGMACThisBCE; ++MHalUtilityVarsGMAC MHalGMACThisUVE; ++ ++struct _MHal_GMAC_Ops{ ++ void (*power_on)(void); ++ void (*update_speed_duplex)(u32 uspeed, u32 uduplex); ++ void (*write_phy)(unsigned char phy_addr, unsigned char address, u32 value); ++ void (*read_phy)(unsigned char phy_addr, unsigned char address, u32* value); ++ phys_addr_t GMAC_Reg_Addr_Base; ++ phys_addr_t GMAC_X32_Reg_Addr_Base; ++ u32 GMAC_IRQ; ++ u32 GMAC_BANK; ++ u8 GPHY_ADDR; ++}; ++typedef struct _MHal_GMAC_Ops MHal_GMAC_Ops; ++ ++MHal_GMAC_Ops MHal_GMAC_This_Ops; ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_GMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ phys_addr_t address = RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++void MHal_GMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ phys_addr_t address = RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u8* ) address ) = val; ++} ++ ++u16 MHal_GMAC_ReadReg16( u32 bank, u32 reg ) ++{ ++ u16 val; ++ u32 address = RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u16* ) address ); ++ return val; ++} ++ ++void MHal_GMAC_WritReg16( u32 bank, u32 reg, u16 val ) ++{ ++ u32 address = RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u16* ) address ) = val; ++} ++ ++u32 MHal_GMAC_ReadReg32_XIU16( u32 xoffset ) ++{ ++ phys_addr_t address = MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base + xoffset*2; ++ ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++} ++ ++void MHal_GMAC_WritReg32_XIU16( u32 xoffset, u32 xval ) ++{ ++ phys_addr_t address = MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base + xoffset*2; ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++} ++ ++u32 MHal_GMAC_ReadReg32_XIU32( u32 xoffset ) ++{ ++ u32 val; ++ phys_addr_t address = MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base + xoffset*2; ++ ++ val = *( ( volatile u32* ) address ); ++ return val; ++} ++ ++void MHal_GMAC_WritReg32_XIU32( u32 xoffset, u32 xval ) ++{ ++ phys_addr_t address = MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base + xoffset*2; ++ ++ *( ( volatile u32 * ) address ) = ( u32 ) xval; ++} ++ ++u32 MHal_GMAC_ReadReg32( u32 xoffset ) ++{ ++ #ifdef XIU32_MODE ++ if(xoffset < 0x100UL) ++ return MHal_GMAC_ReadReg32_XIU32(xoffset); ++ else ++ return MHal_GMAC_ReadReg32_XIU16(xoffset); ++ #else ++ return MHal_GMAC_ReadReg32_XIU16(xoffset); ++ #endif ++} ++ ++void MHal_GMAC_WritReg32( u32 xoffset, u32 xval ) ++{ ++ #ifdef XIU32_MODE ++ if(xoffset < 0x100UL) ++ MHal_GMAC_WritReg32_XIU32(xoffset,xval); ++ else ++ MHal_GMAC_WritReg32_XIU16(xoffset,xval); ++ #else ++ MHal_GMAC_WritReg32_XIU16(xoffset,xval); ++ #endif ++} ++ ++u32 MHal_GMAC_ReadRam32( phys_addr_t uRamAddr, u32 xoffset) ++{ ++ return (*( u32 * ) ( ( char * ) uRamAddr + xoffset ) ); ++} ++ ++void MHal_GMAC_WritRam32( phys_addr_t uRamAddr, u32 xoffset, u32 xval ) ++{ ++ *( ( u32 * ) ( ( char * ) uRamAddr + xoffset ) ) = xval; ++} ++ ++void MHal_GMAC_Write_SA1_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA2_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA3_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA4_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W GMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GMAC_update_HSH(u32 mc0, u32 mc1) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSL, mc0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CTL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CTL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CTL( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CTL, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CFG( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CFG( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RBQP( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RBQP( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TAR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TAR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TCR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TCR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TCR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_TSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TSR ); ++} ++ ++void MHal_GMAC_Write_RSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_RSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RSR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_ISR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_ISR, xval ); ++} ++ ++u32 MHal_GMAC_Read_ISR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ISR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IER( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IER ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IER( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IER, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IDR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IDR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IDR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IDR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IMR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IMR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MAN( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_MAN( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_MAN, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_BUFF( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFF, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_BUFF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RDPTR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFFRDPTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFRDPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFWRPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_FRA( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_FRA ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_OK( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_OK ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SEQE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SEQE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ALE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ALE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_LCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_LCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ECOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ECOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TUE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TUE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CSE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CSE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ROVR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ROVR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ELR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ELR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RJB( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RJB ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_USF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_USF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SQEE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SQEE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register2 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register2( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG2 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register2 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register2( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG2, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register3 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register3( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG3 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register3 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register3( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG3, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Delay_interrupt_status ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Delay_interrupt_status( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_RX_DELAY_MODE_STATUS ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Low-Priority TX Descriptor Base Address ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_LOW_PRI_TX_DESC_BASE( void ) ++{ ++ return MHal_GMAC_ReadReg32_XIU16( REG_RW32_LOW_PRI_TX_DESC_BASE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Low-Priority TX Descriptor Base Address ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_LOW_PRI_TX_DESC_BASE( u32 xval ) ++{ ++ MHal_GMAC_WritReg32_XIU16( REG_RW32_LOW_PRI_TX_DESC_BASE, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Low-Priority TX Descriptor Pointer Address ++//------------------------------------------------------------------------------------------------- ++u16 MHal_GMAC_Read_LOW_PRI_TX_DESC_PTR( void ) ++{ ++ return MHal_GMAC_ReadReg16( REG_GMAC0_BANK, REG_RO16_LOW_PRI_TX_DESC_PTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Low-Priority TX Descriptor Queued Packets Number ++//------------------------------------------------------------------------------------------------- ++u16 MHal_GMAC_Read_LOW_PRI_TX_DESC_QUEUED( void ) ++{ ++ return MHal_GMAC_ReadReg16( REG_GMAC0_BANK, REG_RO16_LOW_PRI_TX_DESC_QUEUED ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Low-Priority TX Descriptor THRESHOLD ++//------------------------------------------------------------------------------------------------- ++u16 MHal_GMAC_Read_LOW_PRI_TX_DESC_THRESHOLD( void ) ++{ ++ return MHal_GMAC_ReadReg16( REG_GMAC0_BANK, REG_RW16_LOW_PRI_TX_DESC_THRESHOLD ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Low-Priority TX Descriptor THRESHOLD ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_LOW_PRI_TX_DESC_THRESHOLD( u16 xval ) ++{ ++ MHal_GMAC_WritReg16( REG_GMAC0_BANK, REG_RW16_LOW_PRI_TX_DESC_THRESHOLD , xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read High-Priority TX Descriptor Base Address ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_HIGH_PRI_TX_DESC_BASE( void ) ++{ ++ return MHal_GMAC_ReadReg32_XIU16( REG_RW32_HIGH_PRI_TX_DESC_BASE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write High-Priority TX Descriptor Base Address ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_HIGH_PRI_TX_DESC_BASE( u32 xval ) ++{ ++ MHal_GMAC_WritReg32_XIU16( REG_RW32_HIGH_PRI_TX_DESC_BASE, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read High-Priority TX Descriptor Pointer Address ++//------------------------------------------------------------------------------------------------- ++u16 MHal_GMAC_Read_HIGH_PRI_TX_DESC_PTR( void ) ++{ ++ return MHal_GMAC_ReadReg16( REG_GMAC0_BANK, REG_RO16_HIGH_PRI_TX_DESC_PTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read High-Priority TX Descriptor Queued Packets Number ++//------------------------------------------------------------------------------------------------- ++u16 MHal_GMAC_Read_HIGH_PRI_TX_DESC_QUEUED( void ) ++{ ++ return MHal_GMAC_ReadReg16( REG_GMAC0_BANK, REG_RO16_HIGH_PRI_TX_DESC_QUEUED ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read High-Priority TX Descriptor THRESHOLD ++//------------------------------------------------------------------------------------------------- ++u16 MHal_GMAC_Read_HIGH_PRI_TX_DESC_THRESHOLD( void ) ++{ ++ return MHal_GMAC_ReadReg16( REG_GMAC0_BANK, REG_RW16_HIGH_PRI_TX_DESC_THRESHOLD ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write High-Priority TX Descriptor THRESHOLD ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_HIGH_PRI_TX_DESC_THRESHOLD( u16 xval ) ++{ ++ MHal_GMAC_WritReg16( REG_GMAC0_BANK, REG_RW16_HIGH_PRI_TX_DESC_THRESHOLD , xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Low-Priority TX Descriptor TRANSMIT0 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_LOW_PRI_TX_DESC_TRANSMIT0( u8 xval ) ++{ ++ MHal_GMAC_WritReg8( REG_GMAC0_BANK, REG_WO08_LOW_PRI_TX_DESC_TRANSMIT0 , xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Low-Priority TX Descriptor TRANSMIT1 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_LOW_PRI_TX_DESC_TRANSMIT1( u8 xval ) ++{ ++ MHal_GMAC_WritReg8( REG_GMAC0_BANK, REG_WO08_LOW_PRI_TX_DESC_TRANSMIT1 , xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write High-Priority TX Descriptor TRANSMIT0 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_HIGH_PRI_TX_DESC_TRANSMIT0( u8 xval ) ++{ ++ MHal_GMAC_WritReg8( REG_GMAC0_BANK, REG_WO08_HIGH_PRI_TX_DESC_TRANSMIT0 , xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write High-Priority TX Descriptor TRANSMIT1 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_HIGH_PRI_TX_DESC_TRANSMIT1( u8 xval ) ++{ ++ MHal_GMAC_WritReg8( REG_GMAC0_BANK, REG_WO08_HIGH_PRI_TX_DESC_TRANSMIT1 , xval); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register4 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register4( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG4 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register4 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register4( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG4, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register5 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register5( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register5 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register5( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG5, xval ); ++} ++#ifdef TX_DESC_MODE ++ ++u32 MHal_GMAC_LOW_PRI_TX_DESC_MODE_OVRN_Get(void) ++{ ++ u16 val; ++ ++ val = MHal_GMAC_Read_LOW_PRI_TX_DESC_QUEUED(); ++ if ((val & GMAC_RO_TX_DESC_OVERRUN) != 0) ++ return 1; //is overrun ++ else ++ return 0; //is normal ++} ++ ++#endif ++ ++#ifdef NEW_TX_QUEUE ++void MHal_GMAC_New_TX_QUEUE_Enable(void) ++{ ++ u32 val; ++ ++ val = MHal_GMAC_ReadReg32_XIU16(GMAC_REG_NEW_TX_QUEUE); ++ val |= GMAC_NEW_TXQ_EN; ++ MHal_GMAC_WritReg32_XIU16(GMAC_REG_NEW_TX_QUEUE, val); ++} ++ ++u32 MHal_GMAC_New_TX_QUEUE_COUNT_Get(void) ++{ ++ u32 val; ++ ++ val = MHal_GMAC_ReadReg32_XIU16(GMAC_REG_NEW_TX_QUEUE); ++ val &= GMAC_NEW_TXQ_CNT; ++ return val; ++} ++ ++u32 MHal_GMAC_New_TX_QUEUE_OVRN_Get(void) ++{ ++ u32 val; ++ ++ val = MHal_GMAC_ReadReg32_XIU16(GMAC_REG_NEW_TX_QUEUE); ++ if ((val & GMAC_NEW_TXQ_OV) != 0) ++ return 1; //is overrun ++ else ++ return 0; //is normal ++} ++ ++void MHal_GMAC_New_TX_QUEUE_Threshold_Set(u32 thr) ++{ ++ u32 val; ++ ++ val = MHal_GMAC_ReadReg32_XIU16(GMAC_REG_NEW_TX_QUEUE); ++ val &= ~(GMAC_NEW_TXQ_THR); ++ val |= ((thr << GMAC_NEW_TXQ_THR_OFFSET) & GMAC_NEW_TXQ_THR); ++ MHal_GMAC_WritReg32_XIU16(GMAC_REG_NEW_TX_QUEUE, val); ++} ++#endif /* NEW_TX_QUEUE */ ++ ++void MHal_GMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_GMAC_WritReg32(i, value); ++ } ++ ++} ++ ++void MHal_GMAC_Set_Miu_Priority(u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(REG_RW32_CFG2); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(REG_RW32_CFG2, value); ++} ++ ++u32 MHal_GMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_GMAC_ReadReg32(REG_RW32_CFG2) & 0x00080000) >> 19; ++} ++ ++void MHal_GMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x11c); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_GMAC_WritReg32(0x11c, value); ++ ++ value = MHal_GMAC_ReadReg32(0x120); ++ value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_GMAC_WritReg32(0x120, value); ++ ++ value = MHal_GMAC_ReadReg32(0x124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_GMAC_WritReg32(0x124, value); ++ ++ value = MHal_GMAC_ReadReg32(REG_RW32_CFG2); ++ value |= 0x00000040; ++ MHal_GMAC_WritReg32(REG_RW32_CFG2, value); ++} ++ ++void MHal_GMAC_Set_Miu_Highway(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_HW_init(void) ++{ ++ MHal_GMAC_Set_Miu_Priority(1); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval |= GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval &= ~GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_write_phy_InternalEPHY( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ phys_addr_t uRegBase = INTERNEL_PHY_REG_BASE; ++ if(phy_addr >= 32) return; // invalid phy address ++ ++ phy_addr =0; ++ ++ *(volatile unsigned int *)(uRegBase + address*4) = value; ++ udelay( 1 ); ++} ++ ++void MHal_GMAC_write_phy_GPHY( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ if(phy_addr >= 32) return; // invalid phy address ++ ++ uRegVal = ( GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_W) | (( phy_addr & 0x1F ) << GMAC_PHY_ADDR_OFFSET ) ++ | ( address << GMAC_PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ ++ MHal_GMAC_Write_MAN( uRegVal ); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ MHal_GMAC_Write_CTL(uCTL); ++} ++ ++unsigned int mdio_bb_read(int phy,int reg); ++unsigned int mdio_bb_write(unsigned int phy,unsigned int reg,unsigned int val); ++void mdio_bb_init(int pin_mdio, int pin_mdc); ++ ++void MHal_GMAC_write_phy_swgpio( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++ ++ mdio_bb_write(phy_addr, address, value); ++} ++ ++void MHal_GMAC_write_phy( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ MHal_GMAC_This_Ops.write_phy(phy_addr,address,value); ++ //printk("write phy_addr:%d offs:%d val:0x%04x\n", phy_addr, address, value); ++} ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_read_phy_InternalEPHY( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ phys_addr_t uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ if(phy_addr >= 32) return; // invalid phy address ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++ ++ return; ++} ++ ++void MHal_GMAC_read_phy_GPHY( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ u32 uRegVal = 0, uCTL = 0; ++ if(phy_addr >= 32) return; // invalid phy address ++ ++ uRegVal = (GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_R) ++ | ((phy_addr & 0x1f) << GMAC_PHY_ADDR_OFFSET) | (address << GMAC_PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ MHal_GMAC_Write_MAN(uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ *value = ( MHal_GMAC_Read_MAN() & 0x0000ffff ); ++ MHal_GMAC_Write_CTL(uCTL); ++ ++ return; ++} ++ ++void MHal_GMAC_read_phy_swgpio( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++ ++ *value = mdio_bb_read(phy_addr, address); ++ ++ return; ++} ++void MHal_GMAC_read_phy( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ MHal_GMAC_This_Ops.read_phy(phy_addr,address,value); ++ //printk("read phy_addr:%d offs:%d val:0x%04x\n", phy_addr, address, *value); ++} ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_update_speed_duplex_GMAC1_EPHY( u32 uspeed, u32 uduplex) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfe; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 1000 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfd; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++void MHal_GMAC_update_speed_duplex_GMAC1_GPHY( u32 uspeed, u32 uduplex) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0xA5); ++ uRegVal &= 0xbf; ++ MHal_GMAC_WritReg8(0x1224, 0xA5, uRegVal); ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x140f, 0x60); ++ uRegVal &= 0xfc; ++ MHal_GMAC_WritReg8(0x140f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 1000 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /*For io0 ++ BK_1224_12[15:14] = 2'11 when 100M ++ 2'01 when 10M ++ BK_121F_30[1:0] = 2'01 when 10 or 100M ++ */ ++ ++ /* Enable reg_rgmii_slow, Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0xa5); ++ uRegVal |= 0xC0; ++ MHal_GMAC_WritReg8(0x1224, 0xa5, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x140f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x140f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 100 Full Duplex */ ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else ++ { ++ /* 100 Half Duplex */ ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /*For io0 ++ BK_1224_12[15:14] = 2'11 when 100M ++ 2'01 when 10M ++ BK_121F_30[1:0] = 2'01 when 10 or 100M ++ */ ++ ++ /* Enable reg_rgmii_slow, Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0xa5); ++ uRegVal &= 0x3F; ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x1224, 0xa5, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x140f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x140f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 10 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ else ++ { ++ /* 10 Half Duplex */ ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++ ++} ++ ++void MHal_GMAC_update_speed_duplex_GMAC0_GPHY( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x25); ++ uRegVal &= 0xbf; ++ MHal_GMAC_WritReg8(0x1224, 0x25, uRegVal); ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 1000 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /*For io0 ++ BK_1224_12[15:14] = 2'11 when 100M ++ 2'01 when 10M ++ BK_121F_30[1:0] = 2'01 when 10 or 100M ++ */ ++ ++ /* Enable reg_rgmii_slow, Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x25); ++ uRegVal |= 0xC0; ++ MHal_GMAC_WritReg8(0x1224, 0x25, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 100 Full Duplex */ ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else ++ { ++ /* 100 Half Duplex */ ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /*For io0 ++ BK_1224_12[15:14] = 2'11 when 100M ++ 2'01 when 10M ++ BK_121F_30[1:0] = 2'01 when 10 or 100M ++ */ ++ ++ /* Enable reg_rgmii_slow, Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x25); ++ uRegVal &= 0x3F; ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x1224, 0x25, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 10 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ else ++ { ++ /* 10 Half Duplex */ ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++void MHal_GMAC_update_speed_duplex_RMII_EPHY( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ if ( uspeed == SPEED_100 ) ++ { ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 100 Full Duplex */ ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else ++ { ++ /* 100 Half Duplex */ ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 10 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ else ++ { ++ /* 10 Half Duplex */ ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++void MHal_GMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ MHal_GMAC_This_Ops.update_speed_duplex(uspeed, uduplex); ++} ++ ++void MHal_GMAC_link_led_on() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x01; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++void MHal_GMAC_link_led_off() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x03; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++u8 MHal_GMAC_CalcMACHash( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_GMAC_get_SA1H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1H ); ++} ++ ++u32 MHal_GMAC_get_SA1L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1L ); ++} ++ ++u32 MHal_GMAC_get_SA2H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2H ); ++} ++ ++u32 MHal_GMAC_get_SA2L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2L ); ++} ++ ++void MHal_GMAC_Write_SA1H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, xval ); ++} ++ ++void MHal_GMAC_Write_SA1L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, xval ); ++} ++ ++void MHal_GMAC_Write_SA2H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, xval ); ++} ++ ++void MHal_GMAC_Write_SA2L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, xval ); ++} ++ ++void* MDev_GMAC_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Check INT Done ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CheckINTDone( void ) ++{ ++ u32 retIntStatus; ++ retIntStatus = MHal_GMAC_Read_ISR(); ++ MHalGMACThisUVE.cntChkINTCounter = ( MHalGMACThisUVE.cntChkINTCounter % ++ GMAC_MAX_INT_COUNTER ); ++ MHalGMACThisUVE.cntChkINTCounter ++; ++ if ( ( retIntStatus & GMAC_INT_DONE ) || ++ ( MHalGMACThisUVE.cntChkINTCounter == ( GMAC_MAX_INT_COUNTER - 1 ) ) ) ++ { ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x01; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// MAC cable connection detection ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CableConnection( u8 gmac_phyaddr ) ++{ ++ u32 retValue = 0; ++ u32 word_ETH_MAN = 0x00000000; ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ ++ MHal_GMAC_Write_CTL( 0x00000010 | word_ETH_CTL ); ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &word_ETH_MAN); ++ ++ if ( word_ETH_MAN & BMSR_LSTATUS ) ++ { ++ retValue = 1; ++ } ++ else ++ { ++ retValue = 0; ++ } ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Negotiation PHY ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_NegotiationPHY( u8 gmac_phyaddr ) ++{ ++ // Set PHY -------------------------------------------------------------- ++ u32 retValue = 0; ++ u32 bmsr; ++ ++ // IMPORTANT: Get real duplex by negotiation with peer. ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_Write_CTL( 0x0000001C | word_ETH_CTL ); ++ ++ MHalGMACThisBCE.duplex = 1; // Set default as Half-duplex if negotiation fails. ++ retValue = 1; ++ ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHalGMACThisUVE.cntChkCableConnect = 0; ++ ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &bmsr); ++ if ( (bmsr & BMSR_100FULL) || (bmsr & BMSR_10FULL) ) ++ { ++ MHalGMACThisBCE.duplex = 2; ++ retValue = 2; ++ } ++ else ++ { ++ MHalGMACThisBCE.duplex = 1; ++ retValue = 1; ++ } ++ ++ // NOTE: REG_ETH_CFG must be set according to new ThisGMACBCE.duplex. ++ ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ // Set PHY -------------------------------------------------------------- ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_timer_callback( u32 value ) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_IER(); ++ uRegVal |= ( GMAC_INT_RCOM ); ++ MHal_GMAC_Write_IER( uRegVal ); ++} ++//------------------------------------------------------------------------------------------------- ++// GMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Power_On_Clk_GMAC1_EPHY( void ) ++{ ++ u8 uRegVal; ++ //int clk_handle; ++ ++ ++ //printk("internal ephy flow\n"); ++ /* Set reg_xmii_type as int PHY mode */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set gmac ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable gmac tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x08); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x08); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* Init ePHY */ ++ //gain shift ++ MHal_GMAC_WritReg8(0x0032, 0xb4, 0x02); ++ ++ //det max ++ MHal_GMAC_WritReg8(0x0032, 0x4f, 0x02); ++ ++ //det min ++ MHal_GMAC_WritReg8(0x0032, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_GMAC_WritReg8(0x0032, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_GMAC_WritReg8(0x0031, 0x72, 0xa0); ++ ++ MHal_GMAC_WritReg8(0x0032, 0xfc, 0x00); ++ MHal_GMAC_WritReg8(0x0032, 0xfd, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xa1, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0xcc, 0x40); ++ MHal_GMAC_WritReg8(0x0032, 0xbb, 0x04); ++ MHal_GMAC_WritReg8(0x0033, 0x3a, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xf1, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0x8a, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0x3b, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0xc4, 0x44); ++ MHal_GMAC_WritReg8(0x0033, 0x80, 0x30); ++ ++ //100 gat ++ MHal_GMAC_WritReg8(0x0033, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_GMAC_WritReg8(0x0033, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_GMAC_WritReg8(0x0033, 0x39, 0x41); ++ ++ //Low power mode ++ MHal_GMAC_WritReg8(0x0033, 0xf2, 0xf5); ++ MHal_GMAC_WritReg8(0x0033, 0xf3, 0x0d); ++ ++ // Prevent packet drop by inverted waveform ++ MHal_GMAC_WritReg8(0x0031, 0x79, 0xd0); ++ MHal_GMAC_WritReg8(0x0031, 0x77, 0x5a); ++ ++ //10T waveform ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xac, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xad, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xae, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xaf, 0x19); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0xab, 0x28); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ ++ //Disable eee ++ MHal_GMAC_WritReg8(0x0031, 0x2d, 0x7c); ++ ++ //speed up timing recovery ++ MHal_GMAC_WritReg8(0x0032, 0xf5, 0x02); ++ ++ //signal_det_k ++ MHal_GMAC_WritReg8(0x0032, 0x0f, 0xc9); ++ ++ //snr_h ++ MHal_GMAC_WritReg8(0x0032, 0x89, 0x50); ++ MHal_GMAC_WritReg8(0x0032, 0x8b, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0x8e, 0x0e); ++ MHal_GMAC_WritReg8(0x0032, 0x90, 0x04); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk_GMAC1_GPHY( void ) ++{ ++ //u8 uRegVal; ++ //int clk_handle; ++ ++ //GMACPLL setting ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x14); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //reg_gt1_mode ++ //MHal_GMAC_WritReg8(0x1026, 0x0a, 0x00); //mdio_en=0, gt0 ++ MHal_GMAC_WritReg8(0x1026, 0x0b, 0x02); //gt1 ++ MHal_GMAC_WritReg8(0x1026, 0x00, 0x00); //allpadin ++ ++ //GMAC mux setting ++ MHal_GMAC_WritReg8(0x1224, 0xA2, 0x88); ++ MHal_GMAC_WritReg8(0x1224, 0xA4, 0x91); ++ MHal_GMAC_WritReg8(0x1224, 0xA5, 0x21); ++ MHal_GMAC_WritReg8(0x1224, 0xA6, 0x02); ++ MHal_GMAC_WritReg8(0x1224, 0xA7, 0x6c); ++ MHal_GMAC_WritReg8(0x1224, 0xA0, 0x00); ++ MHal_GMAC_WritReg8(0x1224, 0xA1, 0xa2); ++ MHal_GMAC_WritReg8(0x1224, 0xee, 0x08); ++ MHal_GMAC_WritReg8(0x1224, 0xef, 0x01); ++ MHal_GMAC_WritReg8(0x1224, 0x84, 0x0c); ++ MHal_GMAC_WritReg8(0x1224, 0x85, 0x00); ++ ++ //MHal_GMAC_WritReg8(0x1224, 0x04, 0x00); //disable gmac and noe ++ ++ //clkgen ++ MHal_GMAC_WritReg8(0x100a, 0xa1, 0x0c); ++ MHal_GMAC_WritReg8(0x140f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x140f, 0x23, 0x00); ++ MHal_GMAC_WritReg8(0x140f, 0x24, 0x80); ++ MHal_GMAC_WritReg8(0x140f, 0x25, 0x28); ++ MHal_GMAC_WritReg8(0x140f, 0x60, 0x00); ++ ++ //Enable GPHY RX delay ++ //MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ //MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ //MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ //MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk_GMAC0_GPHY( void ) ++{ ++ //GMACPLL setting ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x14); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //reg_gt0_mode ++ MHal_GMAC_WritReg8(0x1026, 0x0a, 0xc0); ++ MHal_GMAC_WritReg8(0x1026, 0x0b, 0x00); ++ MHal_GMAC_WritReg8(0x1026, 0x00, 0x00); ++ ++ //GMAC mux setting ++ MHal_GMAC_WritReg8(0x1224, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x91); ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x21); ++ MHal_GMAC_WritReg8(0x1224, 0x26, 0x02); ++ MHal_GMAC_WritReg8(0x1224, 0x27, 0x6c); ++ MHal_GMAC_WritReg8(0x1224, 0x20, 0x00); ++ MHal_GMAC_WritReg8(0x1224, 0x21, 0xa2); ++ MHal_GMAC_WritReg8(0x1224, 0x6e, 0x08); ++ MHal_GMAC_WritReg8(0x1224, 0x6f, 0x01); ++ MHal_GMAC_WritReg8(0x1224, 0x04, 0x0c); ++ MHal_GMAC_WritReg8(0x1224, 0x05, 0x00); ++ ++ //clkgen ++ MHal_GMAC_WritReg8(0x100a, 0x03, 0x0c); ++ MHal_GMAC_WritReg8(0x121f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x121f, 0x23, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x24, 0x80); ++ MHal_GMAC_WritReg8(0x121f, 0x25, 0x28); ++ MHal_GMAC_WritReg8(0x121f, 0x60, 0x00); ++ ++ //Enable GPHY RX delay ++ //MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ //MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ //MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ //MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk_GMAC0_EXT_EPHY( void ) ++{ ++ //GMACPLL setting ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x14); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //reg_gt0_mode ++ MHal_GMAC_WritReg8(0x1026, 0x0a, 0xc0); //mdio, gt0 ++ MHal_GMAC_WritReg8(0x1026, 0x0b, 0x00); //gt1 ++ MHal_GMAC_WritReg8(0x1026, 0x00, 0x00); //allpadin ++ ++ //GMAC mux setting ++ MHal_GMAC_WritReg8(0x1224, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x11); ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x21); ++ MHal_GMAC_WritReg8(0x1224, 0x26, 0x02); ++ MHal_GMAC_WritReg8(0x1224, 0x27, 0x6c); ++ MHal_GMAC_WritReg8(0x1224, 0x20, 0x00); ++ MHal_GMAC_WritReg8(0x1224, 0x21, 0xa2); ++ MHal_GMAC_WritReg8(0x1224, 0x6e, 0x08); ++ MHal_GMAC_WritReg8(0x1224, 0x6f, 0x01); ++ MHal_GMAC_WritReg8(0x1224, 0x04, 0x0c); ++ MHal_GMAC_WritReg8(0x1224, 0x05, 0x00); ++ ++ //clkgen ++ MHal_GMAC_WritReg8(0x100a, 0x03, 0x0c); //reg_ckg_gmac_ahb ++ MHal_GMAC_WritReg8(0x121f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x121f, 0x23, 0x04); ++ MHal_GMAC_WritReg8(0x121f, 0x24, 0x04); ++ MHal_GMAC_WritReg8(0x121f, 0x25, 0xe8); ++ MHal_GMAC_WritReg8(0x121f, 0x26, 0xc2); ++ MHal_GMAC_WritReg8(0x121f, 0x60, 0x03); ++ MHal_GMAC_WritReg8(0x121c, 0x00, 0x07); ++ MHal_GMAC_WritReg8(0x121c, 0x01, 0xf0); ++ ++ //Enable GPHY RX delay ++ //MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ //MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ //MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ //MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++ return; ++} ++void MHal_GMAC_Power_On_Clk_GMAC1_EXT_EPHY( void ) ++{ ++ //GMACPLL setting ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x14); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //reg_gt1_mode ++ //MHal_GMAC_WritReg8(0x1026, 0x0a, 0x00); //mdio_en=0, gt0 ++ MHal_GMAC_WritReg8(0x1026, 0x0b, 0x04); //gt1 ++ MHal_GMAC_WritReg8(0x1026, 0x00, 0x00); //allpadin ++ ++ //GMAC mux setting ++ MHal_GMAC_WritReg8(0x1224, 0xa2, 0x88); ++ MHal_GMAC_WritReg8(0x1224, 0xa4, 0x11); ++ MHal_GMAC_WritReg8(0x1224, 0xa5, 0x21); ++ MHal_GMAC_WritReg8(0x1224, 0xa6, 0x02); ++ MHal_GMAC_WritReg8(0x1224, 0xa7, 0x6c); ++ MHal_GMAC_WritReg8(0x1224, 0xa0, 0x00); ++ MHal_GMAC_WritReg8(0x1224, 0xa1, 0xa2); ++ MHal_GMAC_WritReg8(0x1224, 0xee, 0x08); ++ MHal_GMAC_WritReg8(0x1224, 0xef, 0x01); ++ MHal_GMAC_WritReg8(0x1224, 0x84, 0x0c); ++ MHal_GMAC_WritReg8(0x1224, 0x85, 0x00); ++ ++ //MHal_GMAC_WritReg8(0x1224, 0x04, 0x00); //disable gmac, noe and mdio ++ ++ //clkgen ++ MHal_GMAC_WritReg8(0x100a, 0xa1, 0x0c); //reg_ckg_gmac_ahb ++ MHal_GMAC_WritReg8(0x140f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x140f, 0x23, 0x04); ++ MHal_GMAC_WritReg8(0x140f, 0x24, 0x04); ++ MHal_GMAC_WritReg8(0x140f, 0x25, 0xe8); ++ MHal_GMAC_WritReg8(0x140f, 0x26, 0xc2); ++ MHal_GMAC_WritReg8(0x140f, 0x60, 0x03); ++ MHal_GMAC_WritReg8(0x140b, 0x00, 0x07); ++ MHal_GMAC_WritReg8(0x140b, 0x01, 0xf0); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk( void ) ++{ ++ MHal_GMAC_This_Ops.power_on(); ++} ++ ++void MHal_GMAC_Power_Off_Clk( void ) ++{ ++ //u32 uRegVal; ++ ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal |= 0x80; ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal |= 0x04; ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware type check ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Hardware_check( u32 padmux_type ) ++{ ++ if(padmux_type == GMAC1_EPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC1_EPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_GMAC1_EPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_InternalEPHY; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_InternalEPHY; ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC1_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base = GMAC1_XIU32_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = INT_IRQ_30_SECGMAC_INT+32; ++ MHal_GMAC_This_Ops.GPHY_ADDR = 0; ++ return GMAC_EPHY; ++ } ++ else if(padmux_type == GMAC1_GPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC1_GPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_GMAC1_GPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_swgpio; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_swgpio; ++ mdio_bb_init(PAD_SNR0_GPIO1, PAD_SNR0_GPIO0); ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC1_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base = GMAC1_XIU32_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = INT_IRQ_30_SECGMAC_INT+32; ++ MHal_GMAC_This_Ops.GPHY_ADDR = CONFIG_GMAC_EXT_PHY_ADDR; ++ return GMAC_GPHY; ++ } ++ else if(padmux_type == GMAC0_GPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC0_GPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_GMAC0_GPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_GPHY; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_GPHY; ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC0_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base = GMAC0_XIU32_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = INT_IRQ_09_GMAC_INT+32; ++ MHal_GMAC_This_Ops.GPHY_ADDR = CONFIG_GMAC_EXT_PHY_ADDR; ++ return GMAC_GPHY; ++ } ++ else if(padmux_type == GMAC0_RMII_EXT_EPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC0_EXT_EPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_RMII_EPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_GPHY; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_GPHY; ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC0_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base = GMAC0_XIU32_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = INT_IRQ_09_GMAC_INT+32; ++ MHal_GMAC_This_Ops.GPHY_ADDR = CONFIG_GMAC_EXT_PHY_ADDR; ++ return GMAC_EPHY; ++ } ++ else if(padmux_type == GMAC1_RMII_EXT_EPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC1_EXT_EPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_RMII_EPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_swgpio; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_swgpio; ++ mdio_bb_init(PAD_SNR0_GPIO1, PAD_SNR0_GPIO0); ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC1_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_X32_Reg_Addr_Base = GMAC1_XIU32_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = INT_IRQ_30_SECGMAC_INT+32; ++ MHal_GMAC_This_Ops.GPHY_ADDR = CONFIG_GMAC_EXT_PHY_ADDR; ++ return GMAC_EPHY; ++ } ++ else ++ { ++ panic("not support padset"); ++ } ++} ++ ++phys_addr_t MHal_GMAC_REG_ADDR_BASE(void) ++{ ++ return MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base; ++} ++ ++u32 MHal_GMAC_IRQ(void) ++{ ++ return MHal_GMAC_This_Ops.GMAC_IRQ; ++} ++ ++u8 MHal_GMAC_PHY_ADDR(void) ++{ ++ return MHal_GMAC_This_Ops.GPHY_ADDR; ++} +diff --git a/drivers/sstar/gmac/hal/infinity2/mhal_gmac_v3.h b/drivers/sstar/gmac/hal/infinity2/mhal_gmac_v3.h +new file mode 100755 +index 000000000000..3eebfd95a389 +--- /dev/null ++++ b/drivers/sstar/gmac/hal/infinity2/mhal_gmac_v3.h +@@ -0,0 +1,573 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file GMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief GMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_GMAC__ ++#define __DRV_GMAC__ ++ ++//porting ++#define MSTAR_MIU0_BUS_BASE 0x20000000UL ++#define MSTAR_MIU1_BUS_BASE 0x60000000UL ++#define E_IRQ_GMAC 0 ++#define E_IRQHYPH_SECGMAC 0 ++#define TO_DO //printk("%s, %d\n",__FUNCTION__, __LINE__) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define XIU32_MODE ++#define GMAC_LINK_LED_CONTROL ++#define GMAC_CHIP_FLUSH_READ ++#define GMAC_ROVR_SW_RESET ++//#define GMAC_MEMORY_PROTECT ++#define RX_DESC_MODE ++ ++#ifdef CONFIG_GMAC_RX_DMA ++#define RX_ZERO_COPY ++#endif ++#define GMAC_RX_CHECKSUM ++ ++#ifdef CONFIG_GMAC_RX_NAPI ++#define RX_NAPI ++#endif ++ ++#ifdef CONFIG_GMAC_RX_GRO ++#define RX_GRO ++#endif ++ ++#ifdef CONFIG_GMAC_RX_DELAY_INTERRUPT ++#define RX_DELAY_INTERRUPT ++#endif ++ ++#ifdef CONFIG_GMAC_TX_DMA ++#define TX_ZERO_COPY ++#endif ++ ++#ifdef CONFIG_GMAC_TX_DESC_MODE ++#define TX_DESC_MODE ++#else ++ ++#ifdef CONFIG_GMAC_NEW_TX_QUEUE_V3 ++#define NEW_TX_QUEUE ++#else ++#define GMAC_TX_QUEUE_4 ++#endif ++#endif ++ ++#ifdef CONFIG_GMAC_TX_SOFTWARE_QUEUE ++#define TX_SOFTWARE_QUEUE ++#endif ++//#define TX_COM_ENABLE ++//#define TX_SOFTWARE_QUEUE ++//#define TX_NAPI ++// Compiler Switches ++#define GMAC_URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// PadMux ++//-------------------------------------------------------------------------------------------------- ++#define GMAC1_EPHY 1 ++#define GMAC1_GPHY 2 ++#define GMAC0_GPHY 3 ++#define GMAC0_RMII_EXT_EPHY 4 ++#define GMAC1_RMII_EXT_EPHY 5 ++ ++ ++#define GMAC_EPHY 0 ++#define GMAC_GPHY 1 ++ ++#ifdef CONFIG_KANO_GMAC1_EPHY ++#define DEFAULT_PADMUX GMAC1_EPHY ++#endif ++#ifdef CONFIG_KANO_GMAC1_GPHY ++#define DEFAULT_PADMUX GMAC1_GPHY ++#endif ++#ifdef CONFIG_KANO_GMAC0_GPHY ++#define DEFAULT_PADMUX GMAC0_GPHY ++#endif ++#ifdef CONFIG_GMAC_TO_RMII ++#define DEFAULT_PADMUX GMAC0_RMII_EXT_EPHY ++#endif ++#ifdef CONFIG_GMAC1_TO_RMII ++#define DEFAULT_PADMUX GMAC1_RMII_EXT_EPHY ++#endif ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define GMAC_SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define GMAC_RX_CHECKSUM_ENABLE 0x000E ++#define GMAC_SPEED_100 100 ++#define GMAC_MAX_INT_COUNTER 100 ++#define GMAC_TX_CHECKSUM_ENABLE (0x00000470) ++#define GMAC_TX_V6_CHECKSUM_ENABLE (0x000C0000) ++#define GMAC_TX_JUMBO_FRAME_ENABLE (0x0000ffff) ++#define GMAC_MAX_TX_QUEUE 30 ++// Interrupt: ++#define MAC_GMAC0_IRQ E_IRQ_GMAC //aliasing for interrupt enum (GMAC0) ++#define MAC_GMAC1_IRQ E_IRQHYPH_SECGMAC //aliasing for interrupt enum (GMAC1 & Internal) ++#define GMAC_INT_MASK (0xdff) ++#define GMAC_INT_ALL (0xffff) ++#ifdef TX_COM_ENABLE ++#define GMAC_INT_ENABLE GMAC_INT_DONE|GMAC_INT_RBNA|GMAC_INT_TUND|GMAC_INT_RTRY|GMAC_INT_ROVR|GMAC_INT_TCOM|(0x0000E000UL) ++#else ++#define GMAC_INT_ENABLE GMAC_INT_DONE|GMAC_INT_RBNA|GMAC_INT_TUND|GMAC_INT_RTRY|GMAC_INT_ROVR|(0x0000E000UL) ++#endif ++// Base address here: ++#if defined(CONFIG_ARM) ++#define mstar_pm_base 0xFD000000 ++#elif defined(CONFIG_MIPS) ++#define mstar_pm_base 0xBF000000 ++#endif ++#define RIU_REG_BASE mstar_pm_base ++#define REG_ALBANY0_BANK 0x0031UL ++#define REG_GMAC0_BANK 0x121BUL ++#define REG_GMAC1_BANK 0x140AUL ++#define REG_XIU32_GMAC0_BANK 0x1A1EUL ++#define REG_XIU32_GMAC1_BANK 0x1A25UL ++#define INTERNEL_PHY_REG_BASE RIU_REG_BASE + ((REG_ALBANY0_BANK*0x100UL)<<1) ++#define GMAC0_REG_ADDR_BASE RIU_REG_BASE + ((REG_GMAC0_BANK*0x100UL)<<1) ++#define GMAC1_REG_ADDR_BASE RIU_REG_BASE + ((REG_GMAC1_BANK*0x100UL)<<1) ++#define GMAC0_XIU32_REG_ADDR_BASE RIU_REG_BASE + ((REG_XIU32_GMAC0_BANK*0x100UL)<<1) ++#define GMAC1_XIU32_REG_ADDR_BASE RIU_REG_BASE + ((REG_XIU32_GMAC1_BANK*0x100UL)<<1) ++//#define GMAC_REG_ADDR_BASE_XIU32 GMAC0_XIU32_REG_ADDR_BASE ++#define GMAC_MIU0_BUS_BASE MSTAR_MIU0_BUS_BASE ++// Config Registers Value ++#define WRITE_PROTECT_ENABLE GMAC_MIU_WRITE_PROTECT|GMAC_MIU_WP_INT_EN ++#define SOFTWARE_RESET GMAC_SW_RESET_MIU|GMAC_SW_RS_EMAC_TO_MIU|GMAC_SW_RESET_APB|GMAC_SW_RESET_AHB ++#define EXTERNAL_PHY GMAC_RMII|GMAC_RMII_12 ++#ifdef GMAC_MEMORY_PROTECT ++#define CONFIG2_VAL GMAC_POWER_UP|SOFTWARE_RESET|WRITE_PROTECT_ENABLE ++#else ++#define CONFIG2_VAL GMAC_POWER_UP|SOFTWARE_RESET ++#endif ++// Delay Interrupt mode: ++//#define DELAY_NUMBER 0x40 ++//#define DELAY_TIME 0x04 ++#define DELAY_NUMBER CONFIG_GMAC_DELAY_INTERRUPT_NUMBER ++#define DELAY_TIME CONFIG_GMAC_DELAY_INTERRUPT_TIMEOUT ++#define DELAY_INTERRUPT_CONFIG GMAC_INT_DELAY_MODE_EN|(DELAY_NUMBER< ( HZ / 1000 ) ++#define GmacInputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define GMAC_RIU_MAP 0xBF200000 ++#define GMAC_RIU ((unsigned short volatile *) RIU_MAP) ++#define GMAC_REG_MIPS_BASE (0x1D00) ++#define GMAC_MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define GMAC_REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/gmac/hal/kano/mhal_gmac.c b/drivers/sstar/gmac/hal/kano/mhal_gmac.c +new file mode 100755 +index 000000000000..e2c556d8b237 +--- /dev/null ++++ b/drivers/sstar/gmac/hal/kano/mhal_gmac.c +@@ -0,0 +1,1508 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_gmac.c ++/// @brief GMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_gmac.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct _MHalBasicConfigGMAC ++{ ++ u8 connected; // 0:No, 1:Yes ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _MHalBasicConfigGMAC MHalBasicConfigGMAC; ++ ++struct _MHalUtilityVarsGMAC ++{ ++ u32 cntChkCableConnect; ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ u8 flagISR_INT_DONE; ++}; ++typedef struct _MHalUtilityVarsGMAC MHalUtilityVarsGMAC; ++ ++MHalBasicConfigGMAC MHalGMACThisBCE; ++MHalUtilityVarsGMAC MHalGMACThisUVE; ++ ++#define MHal_MAX_INT_COUNTER 100 ++//------------------------------------------------------------------------------------------------- ++// GMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_GMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ phys_addr_t address = GMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++void MHal_GMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ phys_addr_t address = GMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u8* ) address ) = val; ++} ++ ++u32 MHal_GMAC_ReadReg32( u32 xoffset ) ++{ ++ phys_addr_t address = GMAC_REG_ADDR_BASE + xoffset*2; ++ ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++} ++ ++void MHal_GMAC_WritReg32( u32 xoffset, u32 xval ) ++{ ++ phys_addr_t address = GMAC_REG_ADDR_BASE + xoffset*2; ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++} ++ ++u32 MHal_GMAC_ReadRam32( phys_addr_t uRamAddr, u32 xoffset) ++{ ++ return (*( u32 * ) ( ( char * ) uRamAddr + xoffset ) ); ++} ++ ++void MHal_GMAC_WritRam32( phys_addr_t uRamAddr, u32 xoffset, u32 xval ) ++{ ++ *( ( u32 * ) ( ( char * ) uRamAddr + xoffset ) ) = xval; ++} ++ ++void MHal_GMAC_Write_SA1_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA2_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA3_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA4_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W GMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GMAC_update_HSH(u32 mc0, u32 mc1) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSL, mc0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CTL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CTL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CTL( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CTL, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CFG( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CFG( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RBQP( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RBQP( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TAR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TAR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TCR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TCR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TCR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_TSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TSR ); ++} ++ ++void MHal_GMAC_Write_RSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_RSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RSR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_ISR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_ISR, xval ); ++} ++ ++u32 MHal_GMAC_Read_ISR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ISR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IER( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IER ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IER( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IER, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IDR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IDR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IDR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IDR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IMR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IMR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MAN( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_MAN( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_MAN, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_BUFF( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFF, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_BUFF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RDPTR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFFRDPTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFRDPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFWRPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_FRA( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_FRA ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_OK( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_OK ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SEQE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SEQE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ALE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ALE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_LCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_LCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ECOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ECOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TUE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TUE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CSE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CSE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ROVR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ROVR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ELR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ELR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RJB( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RJB ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_USF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_USF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SQEE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SQEE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0100( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0100 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0100( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0100, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0104, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0108( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0108 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0108( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0108, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 414 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0414( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0414 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 414 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0414( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0414, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 418 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_JULIAN_0418( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_JULIAN_0418, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 418 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_JULIAN_0418( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_JULIAN_0418 ); ++} ++ ++void MHal_GMAC_Set_Tx_JULIAN_T(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_GMAC_WritReg32(i, value); ++ } ++ ++} ++ ++u32 MHal_GMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x134) & 0x00f00000) >> 20; ++} ++ ++void MHal_GMAC_Set_Rx_FIFO_Enlarge(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++u32 MHal_GMAC_Get_Rx_FIFO_Enlarge(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x134) & 0x03000000) >> 24; ++} ++ ++void MHal_GMAC_Set_Miu_Priority(u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x100); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x100, value); ++} ++ ++u32 MHal_GMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x100) & 0x00080000) >> 19; ++} ++ ++void MHal_GMAC_Set_Tx_Hang_Fix_ECO(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_MIU_Out_Of_Range_Fix(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_Rx_Tx_Burst16_Mode(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Set_Rx_Byte_Align_Offset(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x11c); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_GMAC_WritReg32(0x11c, value); ++ ++ value = MHal_GMAC_ReadReg32(0x120); ++ value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_GMAC_WritReg32(0x120, value); ++ ++ value = MHal_GMAC_ReadReg32(0x124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_GMAC_WritReg32(0x124, value); ++ ++ value = MHal_GMAC_ReadReg32(0x100); ++ value |= 0x00000040; ++ MHal_GMAC_WritReg32(0x100, value); ++} ++ ++void MHal_GMAC_Set_Miu_Highway(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_HW_init(void) ++{ ++ MHal_GMAC_Set_Miu_Priority(1); ++// MHal_GMAC_Set_Tx_JULIAN_T(4); ++// MHal_GMAC_Set_Rx_Tx_Burst16_Mode(1); ++// MHal_GMAC_Set_Rx_FIFO_Enlarge(2); ++// MHal_GMAC_Set_Tx_Hang_Fix_ECO(1); ++// MHal_GMAC_Set_MIU_Out_Of_Range_Fix(1); ++// #ifdef GMAC_RX_BYTE_ALIGN_OFFSET ++// MHal_GMAC_Set_Rx_Byte_Align_Offset(2); ++// #endif ++// MHal_GMAC_WritReg32(GMAC_REG_JULIAN_0138, MHal_GMAC_ReadReg32(GMAC_REG_JULIAN_0138) | 0x00000001); ++// MHal_GMAC_Set_Miu_Highway(1); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval |= GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval &= ~GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_write_phy( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ phys_addr_t uRegBase = GMAC_INTERNEL_PHY_REG_BASE; ++ ++ phy_addr =0; ++ ++ *(volatile unsigned int *)(uRegBase + address*4) = value; ++ udelay( 1 ); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_W) | (( phy_addr & 0x1F ) << GMAC_PHY_ADDR_OFFSET ) ++ | ( address << GMAC_PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ ++ MHal_GMAC_Write_MAN( uRegVal ); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ MHal_GMAC_Write_CTL(uCTL); ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_read_phy( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ phys_addr_t uRegBase = GMAC_INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(GMAC_INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(GMAC_INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_R) ++ | ((phy_addr & 0x1f) << GMAC_PHY_ADDR_OFFSET) | (address << GMAC_PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ MHal_GMAC_Write_MAN(uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ *value = ( MHal_GMAC_Read_MAN() & 0x0000ffff ); ++ MHal_GMAC_Write_CTL(uCTL); ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++#ifndef KANO_GMAC0 ++ ++void MHal_GMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfe; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) // 1000 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfd; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++#else ++void MHal_GMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal &= 0xbf; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 1000 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x80; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 100 Full Duplex */ ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else ++ { ++ /* 100 Half Duplex */ ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal &= 0x7f; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++#endif ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 10 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ else ++ { ++ /* 10 Half Duplex */ ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++#endif ++ ++void MHal_GMAC_link_led_on() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x01; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++void MHal_GMAC_link_led_off() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x03; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++u8 MHal_GMAC_CalcMACHash( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_GMAC_get_SA1H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1H ); ++} ++ ++u32 MHal_GMAC_get_SA1L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1L ); ++} ++ ++u32 MHal_GMAC_get_SA2H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2H ); ++} ++ ++u32 MHal_GMAC_get_SA2L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2L ); ++} ++ ++void MHal_GMAC_Write_SA1H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, xval ); ++} ++ ++void MHal_GMAC_Write_SA1L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, xval ); ++} ++ ++void MHal_GMAC_Write_SA2H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, xval ); ++} ++ ++void MHal_GMAC_Write_SA2L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, xval ); ++} ++ ++void* MDev_GMAC_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Check INT Done ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CheckINTDone( void ) ++{ ++ u32 retIntStatus; ++ retIntStatus = MHal_GMAC_Read_ISR(); ++ MHalGMACThisUVE.cntChkINTCounter = ( MHalGMACThisUVE.cntChkINTCounter % ++ MHal_MAX_INT_COUNTER ); ++ MHalGMACThisUVE.cntChkINTCounter ++; ++ if ( ( retIntStatus & GMAC_INT_DONE ) || ++ ( MHalGMACThisUVE.cntChkINTCounter == ( MHal_MAX_INT_COUNTER - 1 ) ) ) ++ { ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x01; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++extern unsigned char gmac_phyaddr; ++//------------------------------------------------------------------------------------------------- ++// MAC cable connection detection ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CableConnection( void ) ++{ ++ u32 retValue = 0; ++ u32 word_ETH_MAN = 0x00000000; ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ ++ MHal_GMAC_Write_CTL( 0x00000010 | word_ETH_CTL ); ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &word_ETH_MAN); ++ ++ if ( word_ETH_MAN & BMSR_LSTATUS ) ++ { ++ retValue = 1; ++ } ++ else ++ { ++ retValue = 0; ++ } ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Negotiation PHY ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_NegotiationPHY( void ) ++{ ++ // Set PHY -------------------------------------------------------------- ++ u32 retValue = 0; ++ u32 bmsr; ++ ++ // IMPORTANT: Get real duplex by negotiation with peer. ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_Write_CTL( 0x0000001C | word_ETH_CTL ); ++ ++ MHalGMACThisBCE.duplex = 1; // Set default as Half-duplex if negotiation fails. ++ retValue = 1; ++ ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHalGMACThisUVE.cntChkCableConnect = 0; ++ ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &bmsr); ++ if ( (bmsr & BMSR_100FULL) || (bmsr & BMSR_10FULL) ) ++ { ++ MHalGMACThisBCE.duplex = 2; ++ retValue = 2; ++ } ++ else ++ { ++ MHalGMACThisBCE.duplex = 1; ++ retValue = 1; ++ } ++ ++ // NOTE: REG_ETH_CFG must be set according to new ThisGMACBCE.duplex. ++ ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ // Set PHY -------------------------------------------------------------- ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_timer_callback( unsigned long value ) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_IER(); ++ uRegVal |= ( GMAC_INT_RCOM ); ++ MHal_GMAC_Write_IER( uRegVal ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++#ifndef KANO_GMAC0 ++ ++void MHal_GMAC_Power_On_Clk( void ) ++{ ++ u8 uRegVal; ++ int clk_handle; ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal &= ~(0x80); ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal &= ~(0x04); ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ ++ //printk("internal ephy flow\n"); ++ /* Set reg_xmii_type as int PHY mode */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set gmac ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable gmac tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x08); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x08); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* Init ePHY */ ++ //gain shift ++ MHal_GMAC_WritReg8(0x0032, 0xb4, 0x02); ++ ++ //det max ++ MHal_GMAC_WritReg8(0x0032, 0x4f, 0x02); ++ ++ //det min ++ MHal_GMAC_WritReg8(0x0032, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_GMAC_WritReg8(0x0032, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_GMAC_WritReg8(0x0031, 0x72, 0xa0); ++ ++ MHal_GMAC_WritReg8(0x0032, 0xfc, 0x00); ++ MHal_GMAC_WritReg8(0x0032, 0xfd, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xa1, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0xcc, 0x40); ++ MHal_GMAC_WritReg8(0x0032, 0xbb, 0x04); ++ MHal_GMAC_WritReg8(0x0033, 0x3a, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xf1, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0x8a, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0x3b, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0xc4, 0x44); ++ MHal_GMAC_WritReg8(0x0033, 0x80, 0x30); ++ ++ //100 gat ++ MHal_GMAC_WritReg8(0x0033, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_GMAC_WritReg8(0x0033, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_GMAC_WritReg8(0x0033, 0x39, 0x41); ++ ++ //Low power mode ++ MHal_GMAC_WritReg8(0x0033, 0xf2, 0xf5); ++ MHal_GMAC_WritReg8(0x0033, 0xf3, 0x0d); ++ ++ // Prevent packet drop by inverted waveform ++ MHal_GMAC_WritReg8(0x0031, 0x79, 0xd0); ++ MHal_GMAC_WritReg8(0x0031, 0x77, 0x5a); ++ ++ //10T waveform ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xac, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xad, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xae, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xaf, 0x19); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0xab, 0x28); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ ++ //Disable eee ++ MHal_GMAC_WritReg8(0x0031, 0x2d, 0x7c); ++ ++ //speed up timing recovery ++ MHal_GMAC_WritReg8(0x0032, 0xf5, 0x02); ++ ++ //signal_det_k ++ MHal_GMAC_WritReg8(0x0032, 0x0f, 0xc9); ++ ++ //snr_h ++ MHal_GMAC_WritReg8(0x0032, 0x89, 0x50); ++ MHal_GMAC_WritReg8(0x0032, 0x8b, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0x8e, 0x0e); ++ MHal_GMAC_WritReg8(0x0032, 0x90, 0x04); ++#else ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set GMAC ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable GMAC tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x00); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x00); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* IO setting, enable TX delay */ ++ MHal_GMAC_WritReg8(0x0033, 0xb2, 0x88); ++ MHal_GMAC_WritReg8(0x0033, 0xb3, 0x80); ++ MHal_GMAC_WritReg8(0x0033, 0xb4, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xb0, 0xac); ++ MHal_GMAC_WritReg8(0x0033, 0xb1, 0x00); ++ ++ /* Enable GT1 */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0e, 0x39); ++ uRegVal &= ~(0x01); ++ MHal_GMAC_WritReg8(0x0e, 0x39, uRegVal); ++ ++ /* Digital synthesizer */ ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x1b); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //Enable GPHY RX delay ++ //MHal_GMAC_enable_mdi(); ++ //MHal_GMAC_Write_MAN( 0x507e0007 ); ++ //MHal_GMAC_Write_MAN( 0x507a00a4 ); ++ //MHal_GMAC_Write_MAN( 0x5072ad91 ); ++ //MHal_GMAC_Write_MAN( 0x507e0000 ); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++#endif ++ ++} ++ ++#else ++ ++void MHal_GMAC_Power_On_Clk( void ) ++{ ++ u8 uRegVal; ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ /* Set GMAC ahb clock to 172MHZ */ ++ MHal_GMAC_WritReg8(0x100a, 0x03, 0x04); ++ ++ /* Enable GMAC tx clock */ ++ /* Enable GMAC rx clock */ ++ /* IO setting, enable TX delay */ ++ MHal_GMAC_WritReg8(0x121f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x121f, 0x23, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x24, 0x80); ++ MHal_GMAC_WritReg8(0x121f, 0x25, 0x28); ++ MHal_GMAC_WritReg8(0x121f, 0x26, 0x02); ++ MHal_GMAC_WritReg8(0x121f, 0x27, 0x0e); ++ MHal_GMAC_WritReg8(0x121f, 0x20, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x21, 0x02); ++ ++ /* Enable GT0 */ ++ MHal_GMAC_WritReg8(0x101e, 0x0c, 0x01); ++ ++ /* Digital synthesizer */ ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x1b); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //Enable GPHY RX delay ++ MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++} ++ ++#endif ++ ++ ++void MHal_GMAC_Power_Off_Clk( void ) ++{ ++ u32 uRegVal; ++ ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal |= 0x80; ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal |= 0x04; ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++} +diff --git a/drivers/sstar/gmac/hal/kano/mhal_gmac.h b/drivers/sstar/gmac/hal/kano/mhal_gmac.h +new file mode 100755 +index 000000000000..39a192572f1a +--- /dev/null ++++ b/drivers/sstar/gmac/hal/kano/mhal_gmac.h +@@ -0,0 +1,417 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file GMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief GMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_GMAC__ ++#define __DRV_GMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++//#define GMAC_RX_SOFTWARE_DESCRIPTOR ++#define GMAC_SOFTWARE_DESCRIPTOR ++#define GMAC_RX_CHECKSUM ++#define GMAC_INT_JULIAN_D ++#define GMAC_CHIP_FLUSH_READ ++#define GMAC_TX_QUEUE_4 ++//#define GMAC_NAPI ++#define GMAC_TX_COUNT (13) //offset of TX counter in TSR ++#define GMAC_LINK_LED_CONTROL ++ ++// Workaround for MST231E-D01A ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++#define KANO_GMAC0 ++#endif ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++#define TX_SW_QUEUE_SIZE (1024) //effected size = TX_RING_SIZE - 1 ++#define TX_DESC_CLEARED 0 ++#define TX_DESC_WROTE 1 ++#define TX_DESC_READ 2 ++#define TX_FIFO_SIZE 4 //HW FIFO size ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++#ifndef KANO_GMAC0 ++#define E_IRQEXPH_SECEMAC E_IRQHYPH_SECGMAC //aliasing for interrupt enum (GMAC1 & Internal) ++#else ++#define E_IRQEXPH_SECEMAC E_IRQ_GMAC //aliasing for interrupt enum (GMAC0) ++#endif ++#ifdef TX_QUEUE_4 ++#define GMAC_INT_MASK (0xdff) ++#else ++#define GMAC_INT_MASK (0xdff) ++#endif ++ ++#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++//#define GMAC_RX_BYTE_ALIGN_OFFSET ++#endif ++// Compiler Switches ++#define GMAC_REG_BIT_MAP ++#define GMAC_URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define GMAC_SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define GMAC_CHECKSUM_ENABLE 0x0FE ++#define GMAC_RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_GMAC_MOA 1 // System Type ++#define GMAC_SPEED_100 100 ++ ++#if defined(CONFIG_ARM) ++#define mstar_pm_base 0xFD000000 ++#endif ++ ++#define GMAC_ALLFF 0xFFFFFFFF ++#define GMAC_ABSO_MEM_BASE 0xA0000000//GMAC_ABSO_MEM_BASE 0xA0000000 ++#define GMAC_INTERNEL_PHY_REG_BASE mstar_pm_base + (0x3100UL<<1) ++ ++#define GMAC_RIU_REG_BASE mstar_pm_base ++ ++#define GMAC_ABSO_PHY_BASE 0x80000000//GMAC_ABSO_MEM_BASE ++#define GMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define GMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define GMAC_BUFFER_MEM_SIZE 0x0004000 ++#define GMAC_MAX_TX_QUEUE 1000 ++// Base address here: ++#define GMAC_MIU0_BUS_BASE MSTAR_MIU0_BUS_BASE ++#ifndef KANO_GMAC0 ++#define GMAC_REG_ADDR_BASE mstar_pm_base + (0x122000UL<<1) // The register address base. Depends on system define. ++#else ++#define GMAC_REG_ADDR_BASE mstar_pm_base + (0x121b00UL<<1) // The register address base. Depends on system define. ++#endif ++ ++#ifdef CONFIG_MSTAR_GMAC_V2 ++#define GMAC_RBQP_LENG 0x400//0x0100 0x40// // ==?descriptors ++#define GMAC_SOFTWARE_DESC_LEN 0x800 ++#else ++#define GMAC_RBQP_LENG 0x20//0x0100 0x40// // ==?descriptors ++#define GMAC_SOFTWARE_DESC_LEN 0x4000 ++#endif ++#define GMAC_MAX_RX_DESCR GMAC_RBQP_LENG//32 /* max number of receive buffers */ ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++#define GMAC_RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define GMAC_RX_BUFFER_SIZE (GMAC_RBQP_LENG*GMAC_SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define GMAC_RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define GMAC_RX_BUFFER_SIZE (0x2000< ++#include ++#include ++#include ++#include ++#include ++#include "mhal_gmac_v3.h" ++#include "chip_int.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct _MHalBasicConfigGMAC ++{ ++ u8 connected; // 0:No, 1:Yes ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _MHalBasicConfigGMAC MHalBasicConfigGMAC; ++ ++struct _MHalUtilityVarsGMAC ++{ ++ u32 cntChkCableConnect; ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ u8 flagISR_INT_DONE; ++}; ++typedef struct _MHalUtilityVarsGMAC MHalUtilityVarsGMAC; ++ ++MHalBasicConfigGMAC MHalGMACThisBCE; ++MHalUtilityVarsGMAC MHalGMACThisUVE; ++ ++struct _MHal_GMAC_Ops{ ++ void (*power_on)(void); ++ void (*update_speed_duplex)(u32 uspeed, u32 uduplex); ++ void (*write_phy)(unsigned char phy_addr, unsigned char address, u32 value); ++ void (*read_phy)(unsigned char phy_addr, unsigned char address, u32* value); ++ phys_addr_t GMAC_Reg_Addr_Base; ++ u32 GMAC_IRQ; ++ u32 GMAC_BANK; ++ u8 GPHY_ADDR; ++}; ++typedef struct _MHal_GMAC_Ops MHal_GMAC_Ops; ++ ++MHal_GMAC_Ops MHal_GMAC_This_Ops; ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_GMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ phys_addr_t address = RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++void MHal_GMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ phys_addr_t address = RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u8* ) address ) = val; ++} ++ ++u32 MHal_GMAC_ReadReg32( u32 xoffset ) ++{ ++ phys_addr_t address = MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base + xoffset*2; ++ ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++} ++ ++void MHal_GMAC_WritReg32( u32 xoffset, u32 xval ) ++{ ++ phys_addr_t address = MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base + xoffset*2; ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++} ++ ++u32 MHal_GMAC_ReadRam32( phys_addr_t uRamAddr, u32 xoffset) ++{ ++ return (*( u32 * ) ( ( char * ) uRamAddr + xoffset ) ); ++} ++ ++void MHal_GMAC_WritRam32( phys_addr_t uRamAddr, u32 xoffset, u32 xval ) ++{ ++ *( ( u32 * ) ( ( char * ) uRamAddr + xoffset ) ) = xval; ++} ++ ++void MHal_GMAC_Write_SA1_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA2_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA3_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_GMAC_Write_SA4_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4L, w0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W GMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GMAC_update_HSH(u32 mc0, u32 mc1) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSL, mc0 ); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CTL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CTL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CTL( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CTL, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CFG( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_CFG( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RBQP( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RBQP( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TAR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TAR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TCR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TCR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TCR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_TSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_TSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TSR ); ++} ++ ++void MHal_GMAC_Write_RSR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_RSR, xval ); ++} ++ ++u32 MHal_GMAC_Read_RSR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RSR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_ISR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_ISR, xval ); ++} ++ ++u32 MHal_GMAC_Read_ISR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ISR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IER( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IER ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IER( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IER, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IDR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IDR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_IDR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_IDR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_IMR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_IMR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MAN( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_MAN( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_MAN, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_BUFF( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFF, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_BUFF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RDPTR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_BUFFRDPTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFRDPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_BUFFWRPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_FRA( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_FRA ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_MCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_MCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_OK( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_OK ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SEQE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SEQE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ALE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ALE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_LCOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_LCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ECOL( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ECOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_TUE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_TUE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_CSE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_CSE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ROVR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ROVR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_ELR( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_ELR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_RJB( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_RJB ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_USF( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_USF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_SQEE( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SQEE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register2 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register2( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG2 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register2 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register2( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG2, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register3 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register3( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG3 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register3 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register3( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG3, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Delay_interrupt_status ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Delay_interrupt_status( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_RX_DELAY_MODE_STATUS ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register4 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register4( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG4 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register4 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register4( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG4, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register5 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Read_Network_config_register5( void ) ++{ ++ return MHal_GMAC_ReadReg32( REG_RW32_CFG5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register5 ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Write_Network_config_register5( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( REG_RW32_CFG5, xval ); ++} ++ ++void MHal_GMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_GMAC_WritReg32(i, value); ++ } ++ ++} ++ ++void MHal_GMAC_Set_Miu_Priority(u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x100); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x100, value); ++} ++ ++u32 MHal_GMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_GMAC_ReadReg32(0x100) & 0x00080000) >> 19; ++} ++ ++void MHal_GMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_GMAC_ReadReg32(0x11c); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_GMAC_WritReg32(0x11c, value); ++ ++ value = MHal_GMAC_ReadReg32(0x120); ++ value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_GMAC_WritReg32(0x120, value); ++ ++ value = MHal_GMAC_ReadReg32(0x124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_GMAC_WritReg32(0x124, value); ++ ++ value = MHal_GMAC_ReadReg32(0x100); ++ value |= 0x00000040; ++ MHal_GMAC_WritReg32(0x100, value); ++} ++ ++void MHal_GMAC_Set_Miu_Highway(u32 xval) ++{ ++ u32 value; ++ value = MHal_GMAC_ReadReg32(0x134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_GMAC_WritReg32(0x134, value); ++} ++ ++void MHal_GMAC_HW_init(void) ++{ ++ MHal_GMAC_Set_Miu_Priority(1); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval |= GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_GMAC_Read_CTL(); ++ xval &= ~GMAC_MPE; ++ MHal_GMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_write_phy_EPHY( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++ phys_addr_t uRegBase = INTERNEL_PHY_REG_BASE; ++ ++ phy_addr =0; ++ ++ *(volatile unsigned int *)(uRegBase + address*4) = value; ++ udelay( 1 ); ++} ++ ++void MHal_GMAC_write_phy_GPHY( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_W) | (( phy_addr & 0x1F ) << GMAC_PHY_ADDR_OFFSET ) ++ | ( address << GMAC_PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ ++ MHal_GMAC_Write_MAN( uRegVal ); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ MHal_GMAC_Write_CTL(uCTL); ++} ++ ++void MHal_GMAC_write_phy( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++ MHal_GMAC_This_Ops.write_phy(phy_addr,address,value); ++} ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_read_phy_EPHY( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++ phys_addr_t uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++ ++ return; ++} ++ ++void MHal_GMAC_read_phy_GPHY( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ if(phy_addr >= 32) return; // invalid phy address ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (GMAC_HIGH | GMAC_CODE_802_3 | GMAC_RW_R) ++ | ((phy_addr & 0x1f) << GMAC_PHY_ADDR_OFFSET) | (address << GMAC_PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_enable_mdi(); ++ MHal_GMAC_Write_MAN(uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & GMAC_IDLE ) ) ++ { ++ uRegVal = MHal_GMAC_ReadReg32( GMAC_REG_ETH_SR ); ++ barrier(); ++ } ++ *value = ( MHal_GMAC_Read_MAN() & 0x0000ffff ); ++ MHal_GMAC_Write_CTL(uCTL); ++ ++ return; ++} ++ ++void MHal_GMAC_read_phy( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++ MHal_GMAC_This_Ops.read_phy(phy_addr,address,value); ++} ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_update_speed_duplex_GMAC1_EPHY( u32 uspeed, u32 uduplex) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfe; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 1000 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfd; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++void MHal_GMAC_update_speed_duplex_GMAC1_GPHY( u32 uspeed, u32 uduplex) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfe; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 1000 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x0033, 0xb4); ++ uRegVal &= 0xfd; ++ MHal_GMAC_WritReg8(0x0033, 0xb4, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | GMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++void MHal_GMAC_update_speed_duplex_GMAC0_GPHY( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ u8 uRegVal; ++ ++ xval = MHal_GMAC_ReadReg32( GMAC_REG_ETH_CFG ) & ~( GMAC_SPD | GMAC_FD ); ++ ++ if(uspeed == SPEED_1000) ++ { ++ /* Disable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal &= 0xbf; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 1000 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ } ++ else if ( uspeed == SPEED_100 ) ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Set reg_rgmii10_100 as 100M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x80; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 100 Full Duplex */ ++ xval = xval | GMAC_SPD | GMAC_FD; ++ } ++ else ++ { ++ /* 100 Half Duplex */ ++ xval = xval | GMAC_SPD; ++ } ++ } ++ else ++ { ++ /* Enable reg_rgmii_slow */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal |= 0x40; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Enable reg_rgmii10_100 as 10M*/ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x25); ++ uRegVal &= 0x7f; ++ MHal_GMAC_WritReg8(0x121f, 0x25, uRegVal); ++ ++ /* Set reg_xmii_type as 10M/100M */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x01; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ if ( uduplex == DUPLEX_FULL ) ++ { ++ /* 10 Full Duplex */ ++ xval = xval | GMAC_FD; ++ } ++ else ++ { ++ /* 10 Half Duplex */ ++ } ++ } ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_CFG, xval ); ++} ++ ++void MHal_GMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ MHal_GMAC_This_Ops.update_speed_duplex(uspeed, uduplex); ++} ++ ++void MHal_GMAC_link_led_on() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x01; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++void MHal_GMAC_link_led_off() ++{ ++ u8 uRegVal; ++ ++ ++ uRegVal = MHal_GMAC_ReadReg8(0x000F, 0x1E); ++ uRegVal &= ~0x03; ++ MHal_GMAC_WritReg8(0x000F, 0x1E, uRegVal); ++} ++ ++u8 MHal_GMAC_CalcMACHash( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_enable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_disable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_GMAC_get_SA1H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1H ); ++} ++ ++u32 MHal_GMAC_get_SA1L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA1L ); ++} ++ ++u32 MHal_GMAC_get_SA2H_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2H ); ++} ++ ++u32 MHal_GMAC_get_SA2L_addr( void ) ++{ ++ return MHal_GMAC_ReadReg32( GMAC_REG_ETH_SA2L ); ++} ++ ++void MHal_GMAC_Write_SA1H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1H, xval ); ++} ++ ++void MHal_GMAC_Write_SA1L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA1L, xval ); ++} ++ ++void MHal_GMAC_Write_SA2H( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2H, xval ); ++} ++ ++void MHal_GMAC_Write_SA2L( u32 xval ) ++{ ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_SA2L, xval ); ++} ++ ++void* MDev_GMAC_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Check INT Done ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CheckINTDone( void ) ++{ ++ u32 retIntStatus; ++ retIntStatus = MHal_GMAC_Read_ISR(); ++ MHalGMACThisUVE.cntChkINTCounter = ( MHalGMACThisUVE.cntChkINTCounter % ++ GMAC_MAX_INT_COUNTER ); ++ MHalGMACThisUVE.cntChkINTCounter ++; ++ if ( ( retIntStatus & GMAC_INT_DONE ) || ++ ( MHalGMACThisUVE.cntChkINTCounter == ( GMAC_MAX_INT_COUNTER - 1 ) ) ) ++ { ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x01; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// MAC cable connection detection ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_CableConnection( u8 gmac_phyaddr ) ++{ ++ u32 retValue = 0; ++ u32 word_ETH_MAN = 0x00000000; ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ ++ MHal_GMAC_Write_CTL( 0x00000010 | word_ETH_CTL ); ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &word_ETH_MAN); ++ ++ if ( word_ETH_MAN & BMSR_LSTATUS ) ++ { ++ retValue = 1; ++ } ++ else ++ { ++ retValue = 0; ++ } ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Negotiation PHY ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_NegotiationPHY( u8 gmac_phyaddr ) ++{ ++ // Set PHY -------------------------------------------------------------- ++ u32 retValue = 0; ++ u32 bmsr; ++ ++ // IMPORTANT: Get real duplex by negotiation with peer. ++ u32 word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ MHal_GMAC_Write_CTL( 0x0000001C | word_ETH_CTL ); ++ ++ MHalGMACThisBCE.duplex = 1; // Set default as Half-duplex if negotiation fails. ++ retValue = 1; ++ ++ MHalGMACThisUVE.flagISR_INT_DONE = 0x00; ++ MHalGMACThisUVE.cntChkINTCounter = 0; ++ MHalGMACThisUVE.cntChkCableConnect = 0; ++ ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_BMSR, &bmsr); ++ if ( (bmsr & BMSR_100FULL) || (bmsr & BMSR_10FULL) ) ++ { ++ MHalGMACThisBCE.duplex = 2; ++ retValue = 2; ++ } ++ else ++ { ++ MHalGMACThisBCE.duplex = 1; ++ retValue = 1; ++ } ++ ++ // NOTE: REG_ETH_CFG must be set according to new ThisGMACBCE.duplex. ++ ++ MHal_GMAC_Write_CTL( word_ETH_CTL ); ++ // Set PHY -------------------------------------------------------------- ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_timer_callback( u32 value ) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_IER(); ++ uRegVal |= ( GMAC_INT_RCOM ); ++ MHal_GMAC_Write_IER( uRegVal ); ++} ++//------------------------------------------------------------------------------------------------- ++// GMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_GMAC_Power_On_Clk_GMAC1_EPHY( void ) ++{ ++ u8 uRegVal; ++ int clk_handle; ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal &= ~(0x80); ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal &= ~(0x04); ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++ ++ //printk("internal ephy flow\n"); ++ /* Set reg_xmii_type as int PHY mode */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x02; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set gmac ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable gmac tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x08); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x08); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* Init ePHY */ ++ //gain shift ++ MHal_GMAC_WritReg8(0x0032, 0xb4, 0x02); ++ ++ //det max ++ MHal_GMAC_WritReg8(0x0032, 0x4f, 0x02); ++ ++ //det min ++ MHal_GMAC_WritReg8(0x0032, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_GMAC_WritReg8(0x0032, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_GMAC_WritReg8(0x0031, 0x72, 0xa0); ++ ++ MHal_GMAC_WritReg8(0x0032, 0xfc, 0x00); ++ MHal_GMAC_WritReg8(0x0032, 0xfd, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xa1, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0xcc, 0x40); ++ MHal_GMAC_WritReg8(0x0032, 0xbb, 0x04); ++ MHal_GMAC_WritReg8(0x0033, 0x3a, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xf1, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0x8a, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0x3b, 0x01); ++ MHal_GMAC_WritReg8(0x0032, 0xc4, 0x44); ++ MHal_GMAC_WritReg8(0x0033, 0x80, 0x30); ++ ++ //100 gat ++ MHal_GMAC_WritReg8(0x0033, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_GMAC_WritReg8(0x0033, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_GMAC_WritReg8(0x0033, 0x39, 0x41); ++ ++ //Low power mode ++ MHal_GMAC_WritReg8(0x0033, 0xf2, 0xf5); ++ MHal_GMAC_WritReg8(0x0033, 0xf3, 0x0d); ++ ++ // Prevent packet drop by inverted waveform ++ MHal_GMAC_WritReg8(0x0031, 0x79, 0xd0); ++ MHal_GMAC_WritReg8(0x0031, 0x77, 0x5a); ++ ++ //10T waveform ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0x2b, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x06); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xac, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xad, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xae, 0x19); ++ MHal_GMAC_WritReg8(0x0031, 0xaf, 0x19); ++ MHal_GMAC_WritReg8(0x0033, 0xe8, 0x00); ++ MHal_GMAC_WritReg8(0x0031, 0xab, 0x28); ++ MHal_GMAC_WritReg8(0x0031, 0xaa, 0x19); ++ ++ //Disable eee ++ MHal_GMAC_WritReg8(0x0031, 0x2d, 0x7c); ++ ++ //speed up timing recovery ++ MHal_GMAC_WritReg8(0x0032, 0xf5, 0x02); ++ ++ //signal_det_k ++ MHal_GMAC_WritReg8(0x0032, 0x0f, 0xc9); ++ ++ //snr_h ++ MHal_GMAC_WritReg8(0x0032, 0x89, 0x50); ++ MHal_GMAC_WritReg8(0x0032, 0x8b, 0x80); ++ MHal_GMAC_WritReg8(0x0032, 0x8e, 0x0e); ++ MHal_GMAC_WritReg8(0x0032, 0x90, 0x04); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk_GMAC1_GPHY( void ) ++{ ++ u8 uRegVal; ++ int clk_handle; ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal &= ~(0x80); ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal &= ~(0x04); ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1224, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x1224, 0x60, uRegVal); ++ ++ /* Set GMAC ahb clock to 172MHZ */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_ahb"); ++ set_clk_source(clk_handle, "clk_secgmac_ahb"); ++#else ++ MHal_GMAC_WritReg8(0x1033, 0x64, 0x04); ++#endif ++ ++ /* Enable GMAC tx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_tx"); ++ set_clk_source(clk_handle, "clk_secgmac_tx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x23, 0x00); ++#endif ++ ++ /* Enable gmac rx clock */ ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_rgmii"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x24, 0x00); ++#endif ++#ifdef CONFIG_MSTAR_CLKM ++ clk_handle = get_handle("g_clk_secgamc_rx_ref"); ++ set_clk_source(clk_handle, "clk_secgmac_rx_ref"); ++#else ++ MHal_GMAC_WritReg8(0x1224, 0x25, 0x00); ++#endif ++ ++ /* IO setting, enable TX delay */ ++ MHal_GMAC_WritReg8(0x0033, 0xb2, 0x88); ++ MHal_GMAC_WritReg8(0x0033, 0xb3, 0x80); ++ MHal_GMAC_WritReg8(0x0033, 0xb4, 0x00); ++ MHal_GMAC_WritReg8(0x0033, 0xb0, 0xac); ++ MHal_GMAC_WritReg8(0x0033, 0xb1, 0x00); ++ ++ /* Enable GT1 */ ++ uRegVal = MHal_GMAC_ReadReg8(0x0e, 0x39); ++ uRegVal &= ~(0x01); ++ MHal_GMAC_WritReg8(0x0e, 0x39, uRegVal); ++ ++ /* Digital synthesizer */ ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x1b); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //Enable GPHY RX delay ++ //MHal_GMAC_enable_mdi(); ++ //MHal_GMAC_Write_MAN( 0x507e0007 ); ++ //MHal_GMAC_Write_MAN( 0x507a00a4 ); ++ //MHal_GMAC_Write_MAN( 0x5072ad91 ); ++ //MHal_GMAC_Write_MAN( 0x507e0000 ); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk_GMAC0_GPHY( void ) ++{ ++ u8 uRegVal; ++ ++ /* Set reg_xmii_type as 1G */ ++ uRegVal = MHal_GMAC_ReadReg8(0x121f, 0x60); ++ uRegVal &= 0xfc; ++ uRegVal |= 0x00; ++ MHal_GMAC_WritReg8(0x121f, 0x60, uRegVal); ++ ++ /* Set GMAC ahb clock to 172MHZ */ ++ MHal_GMAC_WritReg8(0x100a, 0x03, 0x04); ++ ++ /* Enable GMAC tx clock */ ++ /* Enable GMAC rx clock */ ++ /* IO setting, enable TX delay */ ++ MHal_GMAC_WritReg8(0x121f, 0x22, 0x88); ++ MHal_GMAC_WritReg8(0x121f, 0x23, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x24, 0x80); ++ MHal_GMAC_WritReg8(0x121f, 0x25, 0x28); ++ MHal_GMAC_WritReg8(0x121f, 0x26, 0x02); ++ MHal_GMAC_WritReg8(0x121f, 0x27, 0x0e); ++ MHal_GMAC_WritReg8(0x121f, 0x20, 0x00); ++ MHal_GMAC_WritReg8(0x121f, 0x21, 0x02); ++ ++ /* Enable GT0 */ ++ MHal_GMAC_WritReg8(0x101e, 0x0c, 0x01); ++ ++ /* Digital synthesizer */ ++ MHal_GMAC_WritReg8(0x100b, 0xc6, 0x00); ++ MHal_GMAC_WritReg8(0x110c, 0xd2, 0x1b); ++ MHal_GMAC_WritReg8(0x110c, 0xc6, 0x00); ++ ++ //Enable GPHY RX delay ++ MHal_GMAC_write_phy(0x0,0x1f,0x0007); ++ MHal_GMAC_write_phy(0x0,0x1e,0x00a4); ++ MHal_GMAC_write_phy(0x0,0x1c,0xad91); ++ MHal_GMAC_write_phy(0x0,0x1f,0x0000); ++ ++ return; ++} ++ ++void MHal_GMAC_Power_On_Clk( void ) ++{ ++ MHal_GMAC_This_Ops.power_on(); ++} ++ ++void MHal_GMAC_Power_Off_Clk( void ) ++{ ++ u32 uRegVal; ++ ++#ifdef CONFIG_MSTAR_SRAMPD ++ /* Close GMAC0 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x20); ++ uRegVal |= 0x80; ++ MHal_GMAC_WriteReg8(0x1712, 0x20, uRegVal); ++ ++ /* Close GMAC1 SRAM Power */ ++ uRegVal = MHal_GMAC_ReadReg8(0x1712, 0x21); ++ uRegVal |= 0x04; ++ MHal_GMAC_WriteReg8(0x1712, 0x21, uRegVal); ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware type check ++//------------------------------------------------------------------------------------------------- ++u32 MHal_GMAC_Hardware_check( u32 padmux_type ) ++{ ++ if(padmux_type == GMAC1_EPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC1_EPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_GMAC1_EPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_EPHY; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_EPHY; ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC1_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = MAC_GMAC1_IRQ; ++ MHal_GMAC_This_Ops.GPHY_ADDR = GMAC1_EPHY_PHY_ADDR; ++ return GMAC_EPHY; ++ } ++ else if(padmux_type == GMAC1_GPHY) ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC1_GPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_GMAC1_GPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_GPHY; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_GPHY; ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC1_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = MAC_GMAC1_IRQ; ++ MHal_GMAC_This_Ops.GPHY_ADDR = GMAC1_GPHY_PHY_ADDR; ++ return GMAC_GPHY; ++ } ++ else ++ { ++ MHal_GMAC_This_Ops.power_on = MHal_GMAC_Power_On_Clk_GMAC0_GPHY; ++ MHal_GMAC_This_Ops.update_speed_duplex = MHal_GMAC_update_speed_duplex_GMAC0_GPHY; ++ MHal_GMAC_This_Ops.read_phy = MHal_GMAC_read_phy_GPHY; ++ MHal_GMAC_This_Ops.write_phy = MHal_GMAC_write_phy_GPHY; ++ MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base = GMAC0_REG_ADDR_BASE; ++ MHal_GMAC_This_Ops.GMAC_IRQ = MAC_GMAC0_IRQ; ++ MHal_GMAC_This_Ops.GPHY_ADDR = GMAC0_GPHY_PHY_ADDR; ++ return GMAC_GPHY; ++ } ++} ++ ++phys_addr_t MHal_GMAC_REG_ADDR_BASE(void) ++{ ++ return MHal_GMAC_This_Ops.GMAC_Reg_Addr_Base; ++} ++ ++u32 MHal_GMAC_IRQ(void) ++{ ++ return MHal_GMAC_This_Ops.GMAC_IRQ; ++} ++ ++u8 MHal_GMAC_PHY_ADDR(void) ++{ ++ return MHal_GMAC_This_Ops.GPHY_ADDR; ++} +diff --git a/drivers/sstar/gmac/hal/kano/mhal_gmac_v3.h b/drivers/sstar/gmac/hal/kano/mhal_gmac_v3.h +new file mode 100755 +index 000000000000..99948f0fda14 +--- /dev/null ++++ b/drivers/sstar/gmac/hal/kano/mhal_gmac_v3.h +@@ -0,0 +1,457 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file GMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief GMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_GMAC__ ++#define __DRV_GMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define GMAC_LINK_LED_CONTROL ++#define GMAC_CHIP_FLUSH_READ ++#define GMAC_ROVR_SW_RESET ++//#define GMAC_MEMORY_PROTECT ++#define RX_DESC_MODE ++#ifdef CONFIG_GMAC_RX_DMA ++#define RX_ZERO_COPY ++#endif ++#define GMAC_RX_CHECKSUM ++#ifdef CONFIG_GMAC_RX_NAPI ++#define RX_NAPI ++#endif ++#ifdef CONFIG_GMAC_RX_GRO ++#define RX_GRO ++#endif ++#define GMAC_TX_QUEUE_4 ++#ifdef CONFIG_GMAC_RX_DELAY_INTERRUPT ++#define RX_DELAY_INTERRUPT ++#endif ++//#define TX_COM_ENABLE ++//#define TX_SOFTWARE_QUEUE ++//#define TX_NAPI ++// Compiler Switches ++#define GMAC_URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// PadMux ++//-------------------------------------------------------------------------------------------------- ++#define GMAC1_EPHY 1 ++#define GMAC1_GPHY 2 ++#define GMAC0_GPHY 3 ++#define GMAC0_GPHY_PHY_ADDR CONFIG_KANO_GMAC0_GPHY_PHY_ADDR ++#define GMAC1_EPHY_PHY_ADDR CONFIG_KANO_GMAC1_EPHY_PHY_ADDR ++#define GMAC1_GPHY_PHY_ADDR CONFIG_KANO_GMAC1_GPHY_PHY_ADDR ++#define GMAC_EPHY 0 ++#define GMAC_GPHY 1 ++#ifdef CONFIG_KANO_GMAC1_EPHY ++#define DEFAULT_PADMUX GMAC1_EPHY ++#endif ++#ifdef CONFIG_KANO_GMAC1_GPHY ++#define DEFAULT_PADMUX GMAC1_GPHY ++#endif ++#ifdef CONFIG_KANO_GMAC0_GPHY ++#define DEFAULT_PADMUX GMAC0_GPHY ++#endif ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define GMAC_SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define GMAC_RX_CHECKSUM_ENABLE 0x000E ++#define GMAC_SPEED_100 100 ++#define GMAC_MAX_INT_COUNTER 100 ++#define GMAC_TX_CHECKSUM_ENABLE (0x00000470) ++#define GMAC_TX_V6_CHECKSUM_ENABLE (0x000C0000) ++#define GMAC_TX_JUMBO_FRAME_ENABLE (0x0000ffff) ++#define GMAC_MAX_TX_QUEUE 30 ++// Interrupt: ++#define MAC_GMAC0_IRQ E_IRQ_GMAC //aliasing for interrupt enum (GMAC0) ++#define MAC_GMAC1_IRQ E_IRQHYPH_SECGMAC //aliasing for interrupt enum (GMAC1 & Internal) ++#define GMAC_INT_MASK (0xdff) ++#define GMAC_INT_ALL (0xffff) ++#ifdef TX_COM_ENABLE ++#define GMAC_INT_ENABLE GMAC_INT_DONE|GMAC_INT_RBNA|GMAC_INT_TUND|GMAC_INT_RTRY|GMAC_INT_ROVR|GMAC_INT_TCOM|(0x0000E000UL) ++#else ++#define GMAC_INT_ENABLE GMAC_INT_DONE|GMAC_INT_RBNA|GMAC_INT_TUND|GMAC_INT_RTRY|GMAC_INT_ROVR|(0x0000E000UL) ++#endif ++// Base address here: ++#if defined(CONFIG_ARM) ++#define mstar_pm_base 0xFD000000 ++#elif defined(CONFIG_MIPS) ++#define mstar_pm_base 0xBF000000 ++#endif ++#define RIU_REG_BASE mstar_pm_base ++#define REG_ALBANY0_BANK 0x0031UL ++#define REG_GMAC0_BANK 0x121BUL ++#define REG_GMAC1_BANK 0x1220UL ++#define INTERNEL_PHY_REG_BASE RIU_REG_BASE + ((REG_ALBANY0_BANK*0x100UL)<<1) ++#define GMAC0_REG_ADDR_BASE RIU_REG_BASE + ((REG_GMAC0_BANK*0x100UL)<<1) ++#define GMAC1_REG_ADDR_BASE RIU_REG_BASE + ((REG_GMAC1_BANK*0x100UL)<<1) ++#define GMAC_MIU0_BUS_BASE MSTAR_MIU0_BUS_BASE ++// Config Registers Value ++#define WRITE_PROTECT_ENABLE GMAC_MIU_WRITE_PROTECT|GMAC_MIU_WP_INT_EN ++#define SOFTWARE_RESET GMAC_SW_RESET_MIU|GMAC_SW_RS_EMAC_TO_MIU|GMAC_SW_RESET_APB|GMAC_SW_RESET_AHB ++#define EXTERNAL_PHY GMAC_RMII|GMAC_RMII_12 ++#ifdef GMAC_MEMORY_PROTECT ++#define CONFIG2_VAL GMAC_POWER_UP|SOFTWARE_RESET|WRITE_PROTECT_ENABLE ++#else ++#define CONFIG2_VAL GMAC_POWER_UP|SOFTWARE_RESET ++#endif ++// Delay Interrupt mode: ++//#define DELAY_NUMBER 0x40 ++//#define DELAY_TIME 0x04 ++#define DELAY_NUMBER CONFIG_GMAC_DELAY_INTERRUPT_NUMBER ++#define DELAY_TIME CONFIG_GMAC_DELAY_INTERRUPT_TIMEOUT ++#define DELAY_INTERRUPT_CONFIG GMAC_INT_DELAY_MODE_EN|(DELAY_NUMBER< ( HZ / 1000 ) ++#define GmacInputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define GMAC_RIU_MAP 0xBF200000 ++#define GMAC_RIU ((unsigned short volatile *) RIU_MAP) ++#define GMAC_REG_MIPS_BASE (0x1D00) ++#define GMAC_MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define GMAC_REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/sstar/gmac/mdrv_gmac.c.old b/drivers/sstar/gmac/mdrv_gmac.c.old +new file mode 100755 +index 000000000000..bd7a43ada83c +--- /dev/null ++++ b/drivers/sstar/gmac/mdrv_gmac.c.old +@@ -0,0 +1,2727 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file devGMAC.c ++/// @brief GMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#elif defined(CONFIG_ARM64) ++#include ++#include ++#endif ++#include "mdrv_types.h" ++#include "mst_platform.h" ++#include "mdrv_system.h" ++#include "chip_int.h" ++#include "mhal_gmac.h" ++#include "mdrv_gmac.h" ++#include "chip_setup.h" ++ ++#ifdef CONFIG_GMAC_SUPPLY_RNG ++#include ++#include ++#include "mhal_rng_reg.h" ++#endif ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++#define GMAC_RX_TMR (0) ++#define GMAC_LINK_TMR (1) ++ ++#define GMAC_CHECK_LINK_TIME (HZ) ++#define GMAC_IER_FOR_INT_JULIAN_D (0x0000E435UL) ++#define GMAC_CHECK_CNT (500000) ++ ++#define GMAC_TX_PTK_BASE (GMAC_TX_SKB_BASE + GMAC_RAM_VA_PA_OFFSET) ++ ++#define GMAC_ALBANY_OUI_MSB (0) ++#define GMAC_RTL_8210 (0x1CUL) ++ ++#define GMAC_RX_THROUGHPUT_TEST 0 ++#define GMAC_TX_THROUGHPUT_TEST 0 ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++u32 gmac_initstate= 0; ++u8 gmac_txidx =0; ++spinlock_t gmac_lock; ++u32 ROVRcount = 0; ++unsigned char gmac_phyaddr = 0; ++ ++// 0x78c9: link is down. ++static u32 gmac_phy_status_register = 0x78c9UL; ++ ++struct sk_buff *gmac_pseudo_packet; ++ ++#if GMAC_TX_THROUGHPUT_TEST ++static unsigned int gmac_tx_test = 0; ++static unsigned int gmac_tx_thread = 10; ++static struct task_struct *tx_tsk[20]; ++unsigned char gmac_packet_content[] = { ++0xa4, 0xba, 0xdb, 0x95, 0x25, 0x29, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x08, 0x00, 0x45, 0x00, ++0x05, 0xda, 0x69, 0x0a, 0x40, 0x00, 0x40, 0x11, 0xbe, 0x94, 0xac, 0x10, 0x5a, 0xe3, 0xac, 0x10, ++0x5a, 0x70, 0x92, 0x7f, 0x13, 0x89, 0x05, 0xc6, 0x0c, 0x5b, 0x00, 0x00, 0x03, 0x73, 0x00, 0x00, ++0x00, 0x65, 0x00, 0x06, 0xe1, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++0x13, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x18, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39 ++}; ++#endif ++ ++unsigned char ipv6udp_csumok[] = ++{ ++0x00, 0x00, 0x86, 0x05, 0x80, 0xda, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x86, 0xdd, 0x60, 0x00, ++0x00, 0x00, 0x00, 0x14, 0x11, 0x02, 0x3f, 0xfe, 0x05, 0x07, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, ++0x86, 0xff, 0xfe, 0x05, 0x80, 0xda, 0x3f, 0xfe, 0x05, 0x01, 0x04, 0x10, 0x00, 0x00, 0x02, 0xc0, ++0xdf, 0xff, 0xfe, 0x47, 0x03, 0x3e, 0xa0, 0x75, 0x82, 0x9f, 0x00, 0x14, 0xed, 0xe2, 0x05, 0x02, ++0x00, 0x00, 0xf9, 0xc8, 0xe7, 0x36, 0x85, 0x91, 0x09, 0x00 ++}; ++ ++unsigned char ipv6udp_csumerr[] = ++{ ++0x00, 0x00, 0x86, 0x05, 0x80, 0xda, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x86, 0xdd, 0x60, 0x00, ++0x00, 0x00, 0x00, 0x14, 0x11, 0x02, 0x3f, 0xfe, 0x05, 0x07, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, ++0x86, 0xff, 0xfe, 0x05, 0x80, 0xda, 0x3f, 0xfe, 0x05, 0x01, 0x04, 0x10, 0x00, 0x00, 0x02, 0xc0, ++0xdf, 0xff, 0xfe, 0x47, 0x03, 0x3e, 0xa0, 0x75, 0x82, 0x9f, 0x00, 0x14, 0x12, 0x34, 0x05, 0x02, ++0x00, 0x00, 0xf9, 0xc8, 0xe7, 0x36, 0x85, 0x91, 0x09, 0x00 ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct timer_list GMAC_timer, GMAC_Link_timer; ++#if GMAC_RX_THROUGHPUT_TEST ++static struct timer_list GMAC_RX_timer; ++#endif ++static struct net_device *gmac_dev; ++//------------------------------------------------------------------------------------------------- ++// GMAC Function ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev); ++static void MDev_GMAC_timer_callback( unsigned long value ); ++static int MDev_GMAC_SwReset(struct net_device *dev); ++//static void MDev_GMAC_Send_PausePkt(struct net_device* dev); ++unsigned long gmac_oldTime; ++static unsigned long getCurMs(void) ++{ ++ struct timeval tv; ++ unsigned long curMs; ++ ++ do_gettimeofday(&tv); ++ curMs = tv.tv_usec/1000; ++ curMs += tv.tv_sec * 1000; ++ return curMs; ++} ++ ++#if GMAC_RX_THROUGHPUT_TEST ++int gmac_receive_bytes = 0; ++static void RX_timer_callback( unsigned long value){ ++ int get_bytes = receive_bytes; ++ int cur_speed; ++ receive_bytes = 0; ++ ++ cur_speed = get_bytes*8/20/1024; ++ printk(" %dkbps",cur_speed); ++ RX_timer.expires = jiffies + 20*GMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++} ++#endif ++ ++#if GMAC_TX_THROUGHPUT_TEST ++static struct timer_list GMAC_TX_timer; ++int gmac_tx_bytes = 0; ++u64 tx_bytes = 0; ++u64 tx_count = 0; ++static void TX_timer_callback( unsigned long value){ ++ u64 get_bytes = tx_bytes; ++ u64 get_count = tx_count; ++ u64 cur_speed; ++ tx_bytes = 0; ++ tx_count = 0; ++ ++ cur_speed = get_bytes*8/10; ++ printk("\n TX %llu bps count= %llu\n",cur_speed, get_count); ++ GMAC_TX_timer.expires = jiffies + 10*GMAC_CHECK_LINK_TIME; ++ add_timer(&GMAC_TX_timer); ++} ++ ++static void tx_sender(void* arg){ ++ int cpu; ++ while (1) { ++ if (gmac_tx_test) { ++ while(1){ ++ MDev_GMAC_tx(gmac_pseudo_packet, gmac_dev); ++ if (!gmac_tx_test) { ++ break; ++ } ++ } ++ } else { ++ cpu=get_cpu(); put_cpu(); ++ printk("%s %d:cpu:%d\n",__func__,__LINE__,cpu); ++ msleep(5000); ++ } ++ } ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// PHY MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Access the PHY to determine the current Link speed and Mode, and update the ++// MAC accordingly. ++// If no link or auto-negotiation is busy, then no changes are made. ++// Returns: 0 : OK ++// -1 : No link ++// -2 : AutoNegotiation still in progress ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_update_linkspeed (struct net_device *dev) ++{ ++ u32 bmsr, bmcr, physr; ++ u32 speed, duplex, LocPtrA; ++ ++ if (gmac_phyaddr >= 32) return 0; ++ /* Link status is latched, so read twice to get current value */ ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ ++ /* No link */ ++ if (!(bmsr & BMSR_LSTATUS)){ ++ return -1; ++ } ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMCR, &bmcr); ++ ++ /* AutoNegotiation is enabled */ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ GMAC_DBG("==> AutoNegotiation still in progress\n"); ++ return -2; ++ } ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_PHYSR, &physr); ++ ++ if(((physr & PHYSR_SPEED_MASK) & PHYSR_1000) && ++ ((physr & PHYSR_DUPLEX_MASK) & PHYSR_FULL_DUPLEX)) ++ { ++ speed = SPEED_1000; ++ duplex = DUPLEX_FULL; ++ } ++ else if(((physr & PHYSR_SPEED_MASK) & PHYSR_1000) && ++ !((physr & PHYSR_DUPLEX_MASK) & PHYSR_HALF_DUPLEX)) ++ { ++ speed = SPEED_1000; ++ duplex = DUPLEX_HALF; ++ } ++ else if(((physr & PHYSR_SPEED_MASK) & PHYSR_100) && ++ ((physr & PHYSR_DUPLEX_MASK) & PHYSR_FULL_DUPLEX)) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if(((physr & PHYSR_SPEED_MASK) & PHYSR_100) && ++ !((physr & PHYSR_DUPLEX_MASK) & PHYSR_HALF_DUPLEX)) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if(!((physr & PHYSR_SPEED_MASK) & PHYSR_10) && ++ ((physr & PHYSR_DUPLEX_MASK) & PHYSR_FULL_DUPLEX)) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++#else ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ speed = SPEED_100; ++ } ++ else ++ { ++ speed = SPEED_10; ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ duplex = DUPLEX_HALF; ++ } ++#endif ++ } ++ else ++ { ++ speed = (bmcr & 0x0040) ? SPEED_1000 : ((bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); ++ duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ // Update the MAC // ++ MHal_GMAC_update_speed_duplex(speed,duplex); ++ return 0; ++} ++ ++static int MDev_GMAC_get_info(struct net_device *dev) ++{ ++ u32 bmsr, bmcr, LocPtrA; ++ u32 uRegStatus =0; ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_NO_LINK; //no link // ++ } ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_AUTO_NEGOTIATION; //AutoNegotiation // ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_LINK_SUCCESS; //link success // ++ } ++ ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ else ++ { ++ if(bmcr & BMCR_SPEED100) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if(bmcr & BMCR_FULLDPLX) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ ++ return uRegStatus; ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Program the hardware MAC address from dev->dev_addr. ++//------------------------------------------------------------------------------------------------- ++void MDev_GMAC_update_mac_address (struct net_device *dev) ++{ ++ u32 value; ++ value = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) |(dev->dev_addr[0]); ++ MHal_GMAC_Write_SA1L(value); ++ value = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]); ++ MHal_GMAC_Write_SA1H(value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// ADDRESS MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Set the ethernet MAC address in dev->dev_addr ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_get_mac_address (struct net_device *dev) ++{ ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_GMAC_get_SA1H_addr(); ++ LoAddr = MHal_GMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_GMAC_get_SA2H_addr(); ++ LoAddr = MHal_GMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++} ++ ++#ifdef GMAC_URANUS_ETHER_ADDR_CONFIGURABLE ++//------------------------------------------------------------------------------------------------- ++// Store the new hardware address in dev->dev_addr, and update the MAC. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_set_mac_address (struct net_device *dev, void *addr) ++{ ++ struct sockaddr *address = addr; ++ if (!is_valid_ether_addr (address->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy (dev->dev_addr, address->sa_data, dev->addr_len); ++ MDev_GMAC_update_mac_address (dev); ++ return 0; ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Add multicast addresses to the internal multicast-hash table. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_sethashtable (struct net_device *dev) ++{ ++ struct dev_mc_list *curr; ++ u32 mc_filter[2], i, bitnr; ++ ++ mc_filter[0] = mc_filter[1] = 0; ++ ++ curr = dev->mc_list; ++ for (i = 0; i < dev->mc_count; i++, curr = curr->next) ++ { ++ if (!curr) ++ break; // unexpected end of list // ++ ++ bitnr = ether_crc (ETH_ALEN, curr->dmi_addr) >> 26; ++ mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); ++ } ++ ++ MHal_GMAC_update_HSH(mc_filter[0],mc_filter[1]); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//Enable/Disable promiscuous and multicast modes. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_set_rx_mode (struct net_device *dev) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_CFG(); ++ ++ if (dev->flags & IFF_PROMISC) ++ { // Enable promiscuous mode // ++ uRegVal |= GMAC_CAF; ++ } ++ else if (dev->flags & (~IFF_PROMISC)) ++ { // Disable promiscuous mode // ++ uRegVal &= ~GMAC_CAF; ++ } ++ MHal_GMAC_Write_CFG(uRegVal); ++ ++ if (dev->flags & IFF_ALLMULTI) ++ { // Enable all multicast mode // ++ MHal_GMAC_update_HSH(-1,-1); ++ uRegVal |= GMAC_MTI; ++ } ++ else if (dev->flags & IFF_MULTICAST) ++ { // Enable specific multicasts// ++ //MDev_GMAC_sethashtable (dev); ++ MHal_GMAC_update_HSH(-1,-1); ++ uRegVal |= GMAC_MTI; ++ } ++ else if (dev->flags & ~(IFF_ALLMULTI | IFF_MULTICAST)) ++ { // Disable all multicast mode// ++ MHal_GMAC_update_HSH(0,0); ++ uRegVal &= ~GMAC_MTI; ++ } ++ ++ MHal_GMAC_Write_CFG(uRegVal); ++} ++//------------------------------------------------------------------------------------------------- ++// IOCTL ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable MDIO ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_mdio_read (struct net_device *dev, int phy_id, int location) ++{ ++ u32 value; ++ MHal_GMAC_read_phy (phy_id, location, &value); ++ return value; ++} ++ ++static void MDev_GMAC_mdio_write (struct net_device *dev, int phy_id, int location, int value) ++{ ++ MHal_GMAC_write_phy (phy_id, location, value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//ethtool support. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ethtool_ioctl (struct net_device *dev, void *useraddr) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 ethcmd; ++ int res = 0; ++ ++ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ spin_lock_irq (LocPtr->lock); ++ ++ switch (ethcmd) ++ { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ res = mii_ethtool_gset (&LocPtr->mii, &ecmd); ++ if (LocPtr->phy_media == PORT_FIBRE) ++ { //override media type since mii.c doesn't know // ++ ecmd.supported = SUPPORTED_FIBRE; ++ ecmd.port = PORT_FIBRE; ++ } ++ if (copy_to_user (useraddr, &ecmd, sizeof (ecmd))) ++ res = -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd ecmd; ++ if (copy_from_user (&ecmd, useraddr, sizeof (ecmd))) ++ res = -EFAULT; ++ else ++ res = mii_ethtool_sset (&LocPtr->mii, &ecmd); ++ break; ++ } ++ case ETHTOOL_NWAY_RST: ++ { ++ res = mii_nway_restart (&LocPtr->mii); ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ edata.data = mii_link_ok (&LocPtr->mii); ++ if (copy_to_user (useraddr, &edata, sizeof (edata))) ++ res = -EFAULT; ++ break; ++ } ++ default: ++ res = -EOPNOTSUPP; ++ } ++ spin_unlock_irq (LocPtr->lock); ++ return res; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// User-space ioctl interface. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct mii_ioctl_data *data = if_mii(rq); ++ ++ if (!netif_running(dev)) ++ { ++ rq->ifr_metric = GMAC_ETHERNET_TEST_INIT_FAIL; ++ } ++ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ data->phy_id = (gmac_phyaddr & 0x1F); ++ return 0; ++ ++ case SIOCDEVPRIVATE: ++ rq->ifr_metric = (MDev_GMAC_get_info(gmac_dev)|gmac_initstate); ++ return 0; ++ ++ case SIOCDEVON: ++ MHal_GMAC_Power_On_Clk(); ++ return 0; ++ ++ case SIOCDEVOFF: ++ MHal_GMAC_Power_Off_Clk(); ++ return 0; ++ ++ case SIOCGMIIREG: ++ // check PHY's register 1. ++ if((data->reg_num & 0x1fUL) == 0x1) ++ { ++ // PHY's register 1 value is set by timer callback function. ++ spin_lock_irq(LocPtr->lock); ++ data->val_out = gmac_phy_status_register; ++ spin_unlock_irq(LocPtr->lock); ++ } ++ else ++ { ++ MHal_GMAC_read_phy((gmac_phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), (u32 *)&(data->val_out)); ++ } ++ return 0; ++ ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ MHal_GMAC_write_phy((gmac_phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), data->val_in); ++ return 0; ++ ++ case SIOCETHTOOL: ++ return MDev_GMAC_ethtool_ioctl (dev, (void *) rq->ifr_data); ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// MAC ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and start the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_start (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct gmac_recv_desc_bufs *dlist, *dlist_phys; ++#ifndef GMAC_SOFTWARE_DESCRIPTOR ++ int i; ++#endif ++ u32 uRegVal; ++ ++ dlist = LocPtr->dlist; ++ dlist_phys = LocPtr->dlist_phys; ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ dlist->descriptors[GMAC_MAX_RX_DESCR - 1].addr |= GMAC_DESC_WRAP; ++#else ++ for(i = 0; i < GMAC_MAX_RX_DESCR; i++) ++ { ++ dlist->descriptors[i].addr = 0; ++ dlist->descriptors[i].size = 0; ++ } ++ // Set the Wrap bit on the last descriptor // ++ dlist->descriptors[GMAC_MAX_RX_DESCR - 1].addr = GMAC_DESC_WRAP; ++#endif //#ifndef SOFTWARE_DESCRIPTOR ++ // set offset of read and write pointers in the receive circular buffer // ++ uRegVal = MHal_GMAC_Read_BUFF(); ++ uRegVal = (GMAC_RX_BUFFER_BASE|GMAC_RX_BUFFER_SEL) - GMAC_MIU0_BUS_BASE; ++ MHal_GMAC_Write_BUFF(uRegVal); ++ MHal_GMAC_Write_RDPTR(0); ++ MHal_GMAC_Write_WRPTR(0); ++ ++ // Program address of descriptor list in Rx Buffer Queue register // ++ uRegVal = ((GMAC_REG) & dlist_phys->descriptors)- GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE; ++ MHal_GMAC_Write_RBQP(uRegVal); ++ ++ //Reset buffer index// ++ LocPtr->rxBuffIndex = 0; ++ ++ // Enable Receive and Transmit // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= (GMAC_RE | GMAC_TE); ++ MHal_GMAC_Write_CTL(uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Open the ethernet interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_open (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 uRegVal; ++ int ret; ++#if GMAC_TX_THROUGHPUT_TEST ++ int i; ++#endif ++ ++#ifdef GMAC_NAPI ++ napi_enable(&LocPtr->napi_str); ++#endif ++ ++ spin_lock_irq (LocPtr->lock); ++ ret = MDev_GMAC_update_linkspeed(dev); ++ spin_unlock_irq (LocPtr->lock); ++ ++ if (!is_valid_ether_addr (dev->dev_addr)) ++ return -EADDRNOTAVAIL; ++ ++ //ato GMAC_SYS->PMC_PCER = 1 << GMAC_ID_GMAC; //Re-enable Peripheral clock // ++ MHal_GMAC_Power_On_Clk(); ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= GMAC_CSR; ++ MHal_GMAC_Write_CTL(uRegVal); ++ // Enable PHY interrupt // ++ MHal_GMAC_enable_phyirq (); ++ ++ // Enable MAC interrupts // ++#ifndef GMAC_INT_JULIAN_D ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IER(uRegVal); ++#else ++ MHal_GMAC_Write_IER(GMAC_IER_FOR_INT_JULIAN_D); ++#endif ++ ++ LocPtr->ep_flag |= GMAC_EP_FLAG_OPEND; ++ ++ MDev_GMAC_start (dev); ++ netif_start_queue (dev); ++ ++ init_timer( &GMAC_Link_timer ); ++ GMAC_Link_timer.data = GMAC_LINK_TMR; ++ GMAC_Link_timer.function = MDev_GMAC_timer_callback; ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ add_timer(&GMAC_Link_timer); ++ ++ /* check if network linked */ ++ if (-1 == ret) ++ { ++ netif_carrier_off(dev); ++ GmacThisBCE.connected = 0; ++ } ++ else if(0 == ret) ++ { ++ netif_carrier_on(dev); ++ GmacThisBCE.connected = 1; ++ } ++#if GMAC_TX_THROUGHPUT_TEST ++ for (i = 0; i < gmac_tx_thread; i++) ++ { ++ tx_tsk[i] = kthread_create(tx_sender, NULL, "tx_sender"); ++ kthread_bind(tx_tsk[i], (i%CONFIG_NR_CPUS)); ++ if (IS_ERR(tx_tsk[i])) { ++ printk("Can't create kthread of TX sender %d failed\n"); ++ } else { ++ wake_up_process(tx_tsk[i]); ++ } ++ } ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Close the interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_close (struct net_device *dev) ++{ ++ u32 uRegVal; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++#ifdef GMAC_NAPI ++ napi_disable(&LocPtr->napi_str); ++#endif ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ // Disable PHY interrupt // ++ MHal_GMAC_disable_phyirq (); ++#ifndef GMAC_INT_JULIAN_D ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IDR(uRegVal); ++#else ++ MHal_GMAC_Write_IDR(GMAC_IER_FOR_INT_JULIAN_D); ++#endif ++ netif_stop_queue (dev); ++ netif_carrier_off(dev); ++ del_timer(&GMAC_Link_timer); ++ //MHal_GMAC_Power_Off_Clk(); ++ GmacThisBCE.connected = 0; ++ LocPtr->ep_flag &= (~GMAC_EP_FLAG_OPEND); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update the current statistics from the internal statistics registers. ++//------------------------------------------------------------------------------------------------- ++static struct net_device_stats * MDev_GMAC_stats (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ int ale, lenerr, seqe, lcol, ecol; ++ if (netif_running (dev)) ++ { ++ LocPtr->stats.rx_packets += MHal_GMAC_Read_OK(); /* Good frames received */ ++ ale = MHal_GMAC_Read_ALE(); ++ LocPtr->stats.rx_frame_errors += ale; /* Alignment errors */ ++ lenerr = MHal_GMAC_Read_ELR(); ++ LocPtr->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ ++ seqe = MHal_GMAC_Read_SEQE(); ++ LocPtr->stats.rx_crc_errors += seqe; /* CRC error */ ++ LocPtr->stats.rx_fifo_errors += MHal_GMAC_Read_ROVR(); ++ LocPtr->stats.rx_errors += ale + lenerr + seqe + MHal_GMAC_Read_SE() + MHal_GMAC_Read_RJB(); ++ LocPtr->stats.tx_packets += MHal_GMAC_Read_FRA(); /* Frames successfully transmitted */ ++ LocPtr->stats.tx_fifo_errors += MHal_GMAC_Read_TUE(); /* Transmit FIFO underruns */ ++ LocPtr->stats.tx_carrier_errors += MHal_GMAC_Read_CSE(); /* Carrier Sense errors */ ++ LocPtr->stats.tx_heartbeat_errors += MHal_GMAC_Read_SQEE(); /* Heartbeat error */ ++ lcol = MHal_GMAC_Read_LCOL(); ++ ecol = MHal_GMAC_Read_ECOL(); ++ LocPtr->stats.tx_window_errors += lcol; /* Late collisions */ ++ LocPtr->stats.tx_aborted_errors += ecol; /* 16 collisions */ ++ LocPtr->stats.collisions += MHal_GMAC_Read_SCOL() + MHal_GMAC_Read_MCOL() + lcol + ecol; ++ } ++ return &LocPtr->stats; ++} ++ ++static int MDev_GMAC_TxReset(void) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x000001FFUL; ++ ++ MHal_GMAC_Write_CTL((val & ~GMAC_TE)); ++ MHal_GMAC_Write_TCR(0); ++ MHal_GMAC_Write_CTL((MHal_GMAC_Read_CTL() | GMAC_TE)); ++ return 0; ++} ++ ++static int MDev_GMAC_CheckTSR(void) ++{ ++ u32 check; ++ u32 tsrval = 0; ++ ++ #ifdef GMAC_TX_QUEUE_4 ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ for (check = 0; check < GMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_GMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & GMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & GMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & GMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & GMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & GMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & GMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & GMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & GMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ return NETDEV_TX_OK; ++ } ++ #else ++ for (check = 0; check < GMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_GMAC_Read_TSR(); ++ ++ // check GMAC_FIFO1IDLE is ok for gmac one queue ++ if ((tsrval & GMAC_IDLETSR) && (tsrval & GMAC_FIFO1IDLE)) ++ return NETDEV_TX_OK; ++ } ++ #endif ++ ++ GMAC_DBG("Err CheckTSR:0x%x\n", tsrval); ++ MDev_GMAC_TxReset(); ++ ++ return NETDEV_TX_BUSY; ++} ++ ++#if 0 ++static u8 pause_pkt[] = ++{ ++ //DA - multicast ++ 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01, ++ //SA ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ //Len-Type ++ 0x88, 0x08, ++ //Ctrl code ++ 0x00, 0x01, ++ //Ctrl para 8192 ++ 0x20, 0x00 ++}; ++#endif ++ ++static dma_addr_t get_tx_addr(void) ++{ ++ dma_addr_t addr; ++ ++ addr = GMAC_TX_PTK_BASE + 16384*gmac_txidx; ++ gmac_txidx ++; ++ gmac_txidx = gmac_txidx % GMAC_TX_RING_SIZE; ++ return addr; ++} ++ ++void MDrv_GMAC_DumpMem(phys_addr_t addr, u32 len) ++{ ++ u8 *ptr = (u8 *)addr; ++ u32 i; ++ ++ printk("\n ===== Dump %lx =====\n", (long unsigned int)ptr); ++ for (i=0; istats.tx_bytes += len; ++ ++#ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_GMAC_Write_TAR(skb_addr - GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_GMAC_Write_TCR(len); ++ ++ return NETDEV_TX_OK; ++} ++ ++static void MDev_GMAC_Send_PausePkt(struct net_device* dev) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x000001FFUL; ++ ++ //Disable Rx ++ MHal_GMAC_Write_CTL((val & ~GMAC_RE)); ++ memcpy(&pause_pkt[6], dev->dev_addr, 6); ++ MDev_GMAC_BGsend(dev, (u32)pause_pkt, sizeof(pause_pkt)); ++ //Enable Rx ++ MHal_GMAC_Write_CTL((MHal_GMAC_Read_CTL() | GMAC_RE)); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (NETDEV_TX_OK != MDev_GMAC_CheckTSR()) ++ { ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; //check ++ } ++ ++#ifndef GMAC_TX_SKB_PTR ++ #ifndef GMAC_TX_QUEUE_4 ++ skb_addr = get_tx_addr(); ++ ++ #ifdef GMAC_K3_SW_PATCH ++ if(_OFFSET_CONDITION(skb->len)) ++ skb_addr+=0x40UL; ++ #endif ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ #else ++ skb_addr = get_tx_addr(); ++ ++ #ifdef GMAC_K3_SW_PATCH ++ if(_OFFSET_CONDITION(skb->len)) ++ skb_addr+=0x40UL; ++ #endif ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ #endif ++#else ++ LocPtr->txpkt = dma_map_single(NULL, skb->data, skb->len,DMA_TO_DEVICE); ++#endif ++ ++ if (!skb_addr) ++ { ++ dev_err(NULL, ++ "dma map 2 failed (%p, %i). Dropping packet\n", ++ skb->data, skb->len); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return -ENOMEM; ++ } ++ ++ // Store packet information (to free when Tx completed) // ++ LocPtr->stats.tx_bytes += skb->len; ++ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ //Moniter TX packet ++ //MDrv_GMAC_DumpMem(skb_addr, skb->len); ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_GMAC_Write_TAR(skb_addr - GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_GMAC_Write_TCR(skb->len); ++ ++ //netif_stop_queue (dev); ++ dev->trans_start = jiffies; ++#if GMAC_TX_THROUGHPUT_TEST ++ if (gmac_tx_test) { ++ tx_bytes += skb->len; ++ tx_count ++; ++ } ++ else { ++ dev_kfree_skb_irq(skb); ++ } ++#else ++ dev_kfree_skb_irq(skb); ++#endif ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_OK; ++} ++ ++#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Enable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_rx (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct recv_desc_bufs *dlist; ++ unsigned char *p_recv; ++ u32 pktlen = 0; ++ u32 retval = 0; ++#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ u32 uRegVal = 0; ++ u32 RBQP_offset; ++#else ++ //u32 wrap_bit; ++ struct sk_buff *skb; ++#endif ++ ++#ifndef GMAC_INT_JULIAN_D ++ u32 uRegVal = 0; ++ int count = 0; ++#endif ++ ++ dlist = LocPtr->dlist ; ++ // If any Ownership bit is 1, frame received. ++ //while ( (dlist->descriptors[LocPtr->rxBuffIndex].addr )& GMAC_DESC_DONE) ++ do ++ { ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Read_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)) & 0x0FFFFFFFUL, sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)__pa((&(dlist->descriptors[LocPtr->rxBuffIndex].addr))), sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #else ++ #ERROR ++ #endif ++#endif ++ if(!((dlist->descriptors[LocPtr->rxBuffIndex].addr) & GMAC_DESC_DONE)) ++ { ++ break; ++ } ++ ++ p_recv = (char *) ((dlist->descriptors[LocPtr->rxBuffIndex].addr) & ~(GMAC_DESC_DONE | GMAC_DESC_WRAP)); ++ pktlen = ((dlist->descriptors[LocPtr->rxBuffIndex].high_tag & 0x7) << 11) | (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & 0x7ffUL); /* Length of frame including FCS */ ++ ++ #if GMAC_RX_THROUGHPUT_TEST ++ receive_bytes += pktlen; ++ ++ #endif ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)p_recv < 0xC0000000UL) ++ { ++ Chip_Read_Memory_Range((unsigned int)(p_recv) & 0x0FFFFFFFUL, pktlen); ++ } ++ else ++ { ++ Chip_Read_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range((unsigned int)(p_recv), pktlen); ++ #else ++ #ERROR ++ #endif ++#endif ++ // the frame is not splitted in two parts // ++ if(rx_skb[LocPtr->rxBuffIndex] == rx_skb_dummy) ++ { ++ rx_skb[LocPtr->rxBuffIndex] = alloc_skb(SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ if(NULL == rx_skb[LocPtr->rxBuffIndex]) ++ { ++ rx_skb[LocPtr->rxBuffIndex] = rx_skb_dummy; ++ LocPtr->stats.rx_dropped += 1; ++ GMAC_DBG("Dummy, skb no enough memory!\n"); ++ goto NOBUF; ++ } ++ ++ rx_abso_addr[LocPtr->rxBuffIndex] = (u32)rx_skb[LocPtr->rxBuffIndex]->data; ++ //copy content of dummy to new skb ++ *rx_skb[LocPtr->rxBuffIndex] = *rx_skb_dummy; ++ rx_skb[LocPtr->rxBuffIndex]->data = (unsigned char *)rx_abso_addr[LocPtr->rxBuffIndex]; ++ memcpy(rx_skb[LocPtr->rxBuffIndex]->data, (void *)rx_abso_addr_dummy, pktlen); ++ } ++ #ifdef GMAC_RX_BYTE_ALIGN_OFFSET ++ else ++ { ++ skb_reserve(rx_skb[LocPtr->rxBuffIndex], 2); ++ } ++ #endif ++ skb_put(rx_skb[LocPtr->rxBuffIndex], pktlen); ++ // update consumer pointer// ++ rx_skb[LocPtr->rxBuffIndex]->dev = dev; ++ rx_skb[LocPtr->rxBuffIndex]->protocol = eth_type_trans (rx_skb[LocPtr->rxBuffIndex], dev); ++ rx_skb[LocPtr->rxBuffIndex]->len = pktlen; ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++ ++ #ifdef GMAC_RX_CHECKSUM ++ if(((dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP ) || (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_UDP )) \ ++ && (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_IP_CSUM) \ ++ && (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ rx_skb[LocPtr->rxBuffIndex]->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ rx_skb[LocPtr->rxBuffIndex]->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ ++ #if GMAC_RX_THROUGHPUT_TEST ++ kfree_skb(rx_skb[LocPtr->rxBuffIndex]); ++ #else ++ retval = netif_rx (rx_skb[LocPtr->rxBuffIndex]); ++ #endif ++ rx_skb[LocPtr->rxBuffIndex] = alloc_skb(SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ if (NULL == rx_skb[LocPtr->rxBuffIndex]) ++ { ++ rx_skb[LocPtr->rxBuffIndex] = rx_skb_dummy; ++ GMAC_DBG("Skb no enough memory!\n"); ++ } ++ ++NOBUF: ++ rx_abso_addr[LocPtr->rxBuffIndex] = (u32)rx_skb[LocPtr->rxBuffIndex]->data; ++ ++ RBQP_offset = LocPtr->rxBuffIndex * 8; ++ if(LocPtr->rxBuffIndex<(MAX_RX_DESCR-1)) ++ { ++ MHal_GMAC_WritRam32(RAM_VA_PA_OFFSET,RBQP_BASE + RBQP_offset, rx_abso_addr[LocPtr->rxBuffIndex]); ++ } ++ else ++ { ++ MHal_GMAC_WritRam32(RAM_VA_PA_OFFSET,RBQP_BASE + RBQP_offset, (rx_abso_addr[LocPtr->rxBuffIndex]+GMAC_DESC_WRAP)); ++ } ++ ++ if (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ dlist->descriptors[LocPtr->rxBuffIndex].addr &= ~GMAC_DESC_DONE; /* reset ownership bit */ ++ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)) & 0x0FFFFFFFUL, sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])),(unsigned long)__pa((&(dlist->descriptors[LocPtr->rxBuffIndex]))), sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++#else ++ #ERROR ++ #endif ++#endif ++ ++ //wrap after last buffer // ++ LocPtr->rxBuffIndex++; ++ if (LocPtr->rxBuffIndex == MAX_RX_DESCR) ++ { ++ LocPtr->rxBuffIndex = 0; ++ } ++ ++ uRegVal = (u32)rx_skb[LocPtr->rxBuffIndex]; ++ MHal_GMAC_Write_RDPTR(uRegVal); ++ #ifdef CONFIG_GMAC_SUPPLY_RNG ++ { ++ static unsigned long u32LastInputRNGJiff=0; ++ unsigned long u32Jiff=jiffies; ++ ++ if ( time_after(u32Jiff, u32LastInputRNGJiff+InputRNGJiffThreshold) ) ++ { ++ unsigned int u32Temp; ++ unsigned short u16Temp; ++ ++ u32LastInputRNGJiff = u32Jiff; ++ u16Temp = MIPS_REG(REG_RNG_OUT); ++ memcpy((unsigned char *)&u32Temp+0, &u16Temp, 2); ++ u16Temp = MIPS_REG(REG_RNG_OUT); ++ memcpy((unsigned char *)&u32Temp+2, &u16Temp, 2); ++ add_input_randomness(EV_MSC, MSC_SCAN, u32Temp); ++ } ++ } ++ #endif ++ #ifdef GMAC_INT_JULIAN_D ++ if(ThisUVE.flagRBNA == 0) ++ { ++ GmacxReceiveNum--; ++ if(GmacxReceiveNum==0) ++ return 0; ++ } ++ #else ++ if( retval != 0) ++ { ++ uRegVal = MHal_GMAC_Read_IDR(); ++ uRegVal |= (GMAC_INT_RCOM |GMAC_INT_RBNA); ++ MHal_GMAC_Write_IDR(uRegVal); ++ GMAC_timer.expires = jiffies+10; ++ add_timer(&GMAC_timer); ++ return 1; ++ } ++ ++ if( ++count > 5 ) return 0; ++ #endif//#ifdef GMAC_INT_JULIAN_D ++ }while(1); ++#ifdef GMAC_INT_JULIAN_D ++ GmacxReceiveNum=0; ++ GmacThisUVE.flagRBNA=0; ++#endif ++ ++ return 0; ++} ++ ++#else //#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Disable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_rx (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct gmac_recv_desc_bufs *dlist; ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 retval=0; ++ u32 received=0; ++ struct sk_buff *skb; ++ ++ ++#ifndef GMAC_INT_JULIAN_D ++ u32 uRegVal=0; ++ int count = 0; ++#endif ++ ++ dlist = LocPtr->dlist ; ++ // If any Ownership bit is 1, frame received. ++ //while ( (dlist->descriptors[LocPtr->rxBuffIndex].addr )& GMAC_DESC_DONE) ++ do ++ { ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Read_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex])) & 0x0FFFFFFFUL, sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET ,sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #else ++ #ERROR ++ #endif ++#endif ++ if(!((dlist->descriptors[LocPtr->rxBuffIndex].addr) & GMAC_DESC_DONE)) ++ { ++ break; ++ } ++ ++p_recv = (char *) ((((dlist->descriptors[LocPtr->rxBuffIndex].addr) & 0xFFFFFFFFUL) + GMAC_RAM_VA_PA_OFFSET + GMAC_MIU0_BUS_BASE) & ~(GMAC_DESC_DONE | GMAC_DESC_WRAP)); ++ pktlen = ((dlist->descriptors[LocPtr->rxBuffIndex].high_tag & 0x7) << 11) | (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & 0x7ffUL); /* Length of frame including FCS */ ++ ++ #if GMAC_RX_THROUGHPUT_TEST ++ receive_bytes += pktlen; ++ #endif ++ ++ skb = alloc_skb (pktlen + 6, GFP_ATOMIC); ++ ++ if (skb != NULL) ++ { ++ skb_reserve (skb, 2); ++ #ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)p_recv < 0xC0000000UL) ++ { ++ Chip_Read_Memory_Range((unsigned int)(p_recv) & 0x0FFFFFFFUL, pktlen); ++ } ++ else ++ { ++ Chip_Read_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range_VA_PA((size_t)p_recv,(size_t)p_recv - GMAC_RAM_VA_PA_OFFSET ,pktlen); ++ #else ++ #ERROR ++ #endif ++ #endif ++ memcpy(skb_put(skb, pktlen), p_recv, pktlen); ++ skb->dev = dev; ++ skb->protocol = eth_type_trans (skb, dev); ++ skb->len = pktlen; ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++ #if GMAC_RX_THROUGHPUT_TEST ++ kfree_skb(skb); ++ #else ++ ++ #ifdef GMAC_RX_CHECKSUM ++ if(((dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP ) || (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_UDP )) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_IP_CSUM) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ skb->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ #ifdef GMAC_NAPI ++ retval = netif_receive_skb(skb); ++ #else ++ retval = netif_rx(skb); ++ #endif ++ ++ received++; ++ #endif ++ } ++ else ++ { ++ LocPtr->stats.rx_dropped += 1; ++ } ++ ++ if (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ dlist->descriptors[LocPtr->rxBuffIndex].addr &= ~GMAC_DESC_DONE; /* reset ownership bit */ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)) & 0x0FFFFFFFUL, sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET ,sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ //wrap after last buffer // ++ LocPtr->rxBuffIndex++; ++ if (LocPtr->rxBuffIndex == GMAC_MAX_RX_DESCR) ++ { ++ LocPtr->rxBuffIndex = 0; ++ } ++ ++ #ifdef CONFIG_GMAC_SUPPLY_RNG ++ { ++ static unsigned long u32LastInputRNGJiff=0; ++ unsigned long u32Jiff=jiffies; ++ ++ if ( time_after(u32Jiff, u32LastInputRNGJiff+InputRNGJiffThreshold) ) ++ { ++ unsigned int u32Temp; ++ unsigned short u16Temp; ++ ++ u32LastInputRNGJiff = u32Jiff; ++ u16Temp = MIPS_REG(REG_RNG_OUT); ++ memcpy((unsigned char *)&u32Temp+0, &u16Temp, 2); ++ u16Temp = MIPS_REG(REG_RNG_OUT); ++ memcpy((unsigned char *)&u32Temp+2, &u16Temp, 2); ++ add_input_randomness(EV_MSC, MSC_SCAN, u32Temp); ++ } ++ } ++ #endif ++ #ifdef GMAC_INT_JULIAN_D ++ if(GmacThisUVE.flagRBNA == 0) ++ { ++ GmacxReceiveNum--; ++ if(GmacxReceiveNum==0) ++ return 0; ++ } ++ #else ++ if( retval != 0) ++ { ++ uRegVal = MHal_GMAC_Read_IDR(); ++ uRegVal |= (GMAC_INT_RCOM |GMAC_INT_RBNA); ++ MHal_GMAC_Write_IDR(uRegVal); ++ GMAC_timer.expires = jiffies+10; ++ add_timer(&GMAC_timer); ++ return 1; ++ } ++ #endif//#ifdef GMAC_INT_JULIAN_D ++ ++ }while(1); ++#ifdef GMAC_INT_JULIAN_D ++ GmacxReceiveNum=0; ++ GmacThisUVE.flagRBNA=0; ++#endif ++ ++ return received; ++} ++ ++#endif //#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ ++#ifdef GMAC_INT_JULIAN_D ++ ++irqreturn_t MDev_GMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 intstatus=0; ++ u32 xReceiveFlag=0; ++ unsigned long flags; ++ u32 uRegVal; ++ ++#ifndef GMAC_RX_SOFTWARE_DESCRIPTOR ++ u32 wp = 0; ++#endif ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ GmacxoffsetValue = MHal_GMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ ++#ifndef GMAC_RX_SOFTWARE_DESCRIPTOR ++ wp = MHal_GMAC_Read_JULIAN_0100() & 0x00100000UL; ++ if(wp) ++ { ++ GMAC_DBG("GMAC HW write invalid address"); ++ } ++#endif ++ ++ if(GmacxoffsetValue&0x8000UL) ++ { ++ xReceiveFlag = 1; ++ } ++ ++ GmacThisUVE.flagRBNA = 0; ++ ++ gmac_oldTime = getCurMs(); ++ while((xReceiveFlag == 1) || (intstatus = (MHal_GMAC_Read_ISR() & ~MHal_GMAC_Read_IMR() & GMAC_INT_MASK )) ) ++ { ++ if (((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ { ++ netif_wake_queue(dev); ++ } ++ ++ if (intstatus & GMAC_INT_RBNA) ++ { ++ LocPtr->stats.rx_dropped ++; ++ GmacThisUVE.flagRBNA = 1; ++ xReceiveFlag = 1; ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_BNA); ++ } ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (GMAC_INT_TUND | GMAC_INT_RTRY)) ++ { ++ LocPtr->stats.tx_errors += 1; ++ ++ if(intstatus & GMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_GMAC_Write_TSR(GMAC_UND); ++ ++ //Reset TX engine ++ MDev_GMAC_TxReset(); ++ GMAC_DBG ("Transmit TUND error, TX reset\n"); ++ } ++ } ++ ++ if(intstatus&GMAC_INT_DONE) ++ { ++ GmacThisUVE.flagISR_INT_DONE = 0x01UL; ++ } ++ ++ //RX Overrun // ++ if(intstatus & GMAC_INT_ROVR) ++ { ++ LocPtr->stats.rx_dropped++; ++ ROVRcount++; ++ ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_RSROVR); ++ ++ #ifdef GMAC_K3_SW_PATCH ++ if (1) ++ #else ++ if (ROVRcount >= 6) ++ #endif ++ { ++ MDev_GMAC_SwReset(dev); ++ } ++ } ++ else ++ { ++ ROVRcount = 0; ++ } ++ ++ // Receive complete // ++ if(xReceiveFlag == 1) ++ { ++ xReceiveFlag = 0; ++ #ifdef GMAC_NAPI ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IDR(uRegVal); ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++ ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ napi_schedule(&LocPtr->napi_str); ++ #else ++ MDev_GMAC_rx(dev); ++ #endif ++ } ++ } ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return IRQ_HANDLED; ++} ++ ++#else //#ifdef GMAC_INT_JULIAN_D ++ ++//------------------------------------------------------------------------------------------------- ++//MAC interrupt handler with interrupt delay disable ++//(Interrupt delay Disable) ++//------------------------------------------------------------------------------------------------- ++irqreturn_t MDev_GMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ unsigned long intstatus; ++ spin_lock_irqsave(LocPtr->lock, flags); ++ ++ while(intstatus = (MHal_GMAC_Read_ISR() & ~MHal_GMAC_Read_IMR() & MASK)) ++ { ++ //RX buffer not available// ++ if (intstatus & GMAC_INT_RBNA) ++ { ++ LocPtr->stats.rx_dropped ++; ++ } ++ // Receive complete // ++ if (intstatus & GMAC_INT_RCOM) ++ { ++ if(MDev_GMAC_rx (dev)) goto quit_int; ++ } ++ // Transmit complete // ++ if (intstatus & GMAC_INT_TCOM) ++ { ++ struct gmac_tx_ring* tx_fifo_data = NULL; ++ u32 remove_cnt = 1; ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (GMAC_INT_TUND | GMAC_INT_RTRY)) ++ { ++ LocPtr->stats.tx_errors += 1; ++ if(intstatus &GMAC_INT_TUND) ++ { ++ GMAC_DBG ("%s: Transmit TUND error\n", dev->name); ++ } ++ if(intstatus &GMAC_INT_RTRY) ++ { ++ GMAC_DBG ("%s: Transmit RTRY error\n", dev->name); ++ } ++ } ++ ++ if (intstatus & GMAC_INT_TBRE) ++ remove_cnt = 2; ++ #if GMAC_TX_THROUGHPUT_TEST ++ MDev_GMAC_tx(gmac_pseudo_packet, gmac_dev); ++ #else ++ #ifdef GMAC_TX_QUEUE_4 ++ remove_cnt = (intstatus >> GMAC_TX_COUNT); ++ #endif ++ while (remove_cnt > 0) ++ { ++ tx_fifo_data = gmac_tx_ring_get(LocPtr, 1); ++ if (tx_fifo_data == NULL) ++ { ++ break; ++ } ++ else ++ { ++ #ifdef GMAC_TX_QUEUE_4 ++ dma_unmap_single(NULL, tx_fifo_data->skb_physaddr, tx_fifo_data->skb->len, DMA_FROM_DEVICE); ++ #endif ++ if (tx_fifo_data->skb) ++ { ++ dev_kfree_skb_irq(tx_fifo_data->skb); ++ tx_fifo_data->skb = NULL; ++ } ++ else ++ { ++ GMAC_DBG ("skb is null!\n"); ++ } ++ } ++ remove_cnt--; ++ } ++ #endif ++ if (netif_queue_stopped(dev)) ++ netif_wake_queue(dev); ++ } ++ ++ if(intstatus&GMAC_INT_DONE) ++ { ++ ThisUVE.flagISR_INT_DONE = 0x01UL; ++ } ++ //Overrun // ++ if(intstatus & GMAC_INT_ROVR) ++ { ++ MDev_GMAC_rx(dev); ++ LocPtr->stats.rx_dropped++; ++ } ++ } ++quit_int: ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return IRQ_HANDLED; ++} ++#endif //#ifdef GMAC_INT_JULIAN_D ++ ++static int MDev_GMAC_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct GMAC_private *LocPtr = container_of(napi, struct GMAC_private, napi_str); ++ struct net_device *dev = LocPtr->dev; ++ unsigned long flags; ++ int work_done = 0; ++ u32 uRegVal; ++ ++ work_done += MDev_GMAC_rx(dev); ++ //printk("work_done = %d, budget = %d\n",work_done, budget); ++ if (work_done < budget) ++ { ++ /* ++ * Order is important since data can get interrupted ++ * again when we think we are done. ++ */ ++ __napi_complete(napi); ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ ++ // Enable MAC interrupts // ++ #ifndef GMAC_INT_JULIAN_D ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IER(uRegVal); ++ #else ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal |= 0x00000080UL; ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++ MHal_GMAC_Write_IER(GMAC_IER_FOR_INT_JULIAN_D); ++ #endif ++ ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ } ++ ++ return work_done; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++void MDev_GMAC_HW_init(void) ++{ ++ u32 word_ETH_CTL = 0x00000000UL; ++ u32 word_ETH_CFG = 0x00000800UL; ++ u32 uJulian104Value = 0; ++ u32 uNegPhyVal = 0; ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ u32 idxRBQP = 0; ++ u32 RBQP_offset = 0; ++#endif ++ // (20071026_CHARLES) Disable TX, RX and MDIO: (If RX still enabled, the RX buffer will be overwrited) ++ MHal_GMAC_Write_CTL(word_ETH_CTL); ++ // Init RX -------------------------------------------------------------- ++ memset((u8*)GMAC_RAM_VA_PA_OFFSET + GMAC_RX_BUFFER_BASE, 0x00UL, GMAC_RX_BUFFER_SIZE); ++ ++ MHal_GMAC_Write_BUFF((GMAC_RX_BUFFER_BASE | GMAC_RX_BUFFER_SEL) - GMAC_MIU0_BUS_BASE); ++ MHal_GMAC_Write_RDPTR(0x00000000UL); ++ MHal_GMAC_Write_WRPTR(0x00000000UL); ++ ++ // Initialize "Receive Buffer Queue Pointer" ++ MHal_GMAC_Write_RBQP(GMAC_RBQP_BASE -GMAC_MIU0_BUS_BASE); ++ ++ // Initialize Receive Buffer Descriptors ++ memset((u8*)GMAC_RAM_VA_PA_OFFSET + GMAC_RBQP_BASE, 0x00UL, GMAC_RBQP_SIZE); // Clear for max(8*1024)bytes (max:1024 descriptors) ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, (GMAC_RBQP_BASE + GMAC_RBQP_SIZE - 0x10UL), 0x00000002UL); // (n-1) : Wrap = 1 ++#ifdef GMAC_INT_JULIAN_D ++ //Reg_rx_frame_cyc[15:8] -0xFF range 1~255 ++ //Reg_rx_frame_num[7:0] -0x05 receive frames per INT. ++ //0x80 Enable interrupt delay mode. ++ //register 0x104 receive counter need to modify smaller for ping ++ //Modify bigger(need small than 8) for throughput ++ uJulian104Value = GMAC_JULIAN_104_VAL;//0xFF050080; ++ MHal_GMAC_Write_JULIAN_0104(uJulian104Value); ++#else ++ // Enable Interrupts ---------------------------------------------------- ++ uJulian104Value = 0x00000000UL; ++ MHal_GMAC_Write_JULIAN_0104(uJulian104Value); ++#endif ++ // Set MAC address ------------------------------------------------------ ++ MHal_GMAC_Write_SA1_MAC_Address(GmacThisBCE.sa1[0], GmacThisBCE.sa1[1], GmacThisBCE.sa1[2], GmacThisBCE.sa1[3], GmacThisBCE.sa1[4], GmacThisBCE.sa1[5]); ++ MHal_GMAC_Write_SA2_MAC_Address(GmacThisBCE.sa2[0], GmacThisBCE.sa2[1], GmacThisBCE.sa2[2], GmacThisBCE.sa2[3], GmacThisBCE.sa2[4], GmacThisBCE.sa2[5]); ++ MHal_GMAC_Write_SA3_MAC_Address(GmacThisBCE.sa3[0], GmacThisBCE.sa3[1], GmacThisBCE.sa3[2], GmacThisBCE.sa3[3], GmacThisBCE.sa3[4], GmacThisBCE.sa3[5]); ++ MHal_GMAC_Write_SA4_MAC_Address(GmacThisBCE.sa4[0], GmacThisBCE.sa4[1], GmacThisBCE.sa4[2], GmacThisBCE.sa4[3], GmacThisBCE.sa4[4], GmacThisBCE.sa4[5]); ++ ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ #ifdef GMAC_RX_CHECKSUM ++ uJulian104Value=uJulian104Value | (GMAC_RX_CHECKSUM_ENABLE | GMAC_SOFTWARE_DESCRIPTOR_ENABLE); ++ #else ++ uJulian104Value=uJulian104Value | GMAC_SOFTWARE_DESCRIPTOR_ENABLE; ++ #endif ++ ++ MHal_GMAC_Write_JULIAN_0104(uJulian104Value); ++ ++ for(idxRBQP = 0; idxRBQP < GMAC_RBQP_LENG; idxRBQP++) ++ { ++ #ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ rx_skb[idxRBQP] = alloc_skb(GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ ++ rx_abso_addr[idxRBQP] = (u32)rx_skb[idxRBQP]->data; ++ RBQP_offset = idxRBQP * 16; ++ if(idxRBQP < (RBQP_LENG - 1)) ++ { ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, rx_abso_addr[idxRBQP]); ++ } ++ else ++ { ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, (rx_abso_addr[idxRBQP] + GMAC_DESC_WRAP)); ++ } ++ #else ++ RBQP_offset = idxRBQP * 16; ++ ++ if(idxRBQP < (GMAC_RBQP_LENG - 1)) ++ { ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, (GMAC_RX_BUFFER_BASE - GMAC_MIU0_BUS_BASE + GMAC_SOFTWARE_DESC_LEN * idxRBQP)); ++ } ++ else ++ { ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, (GMAC_RX_BUFFER_BASE - GMAC_MIU0_BUS_BASE + GMAC_SOFTWARE_DESC_LEN * idxRBQP + GMAC_DESC_WRAP)); ++ } ++ #endif ++ } ++#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ rx_skb_dummy = alloc_skb(GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ if(rx_skb_dummy == NULL) ++ { ++ GMAC_DBG(KERN_INFO "allocate skb dummy failed\n"); ++ } ++ else ++ { ++ rx_abso_addr_dummy = (u32)(rx_skb_dummy->data); ++ } ++#endif ++ ++#endif //#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ ++ if (!GmacThisUVE.initedGMAC) ++ { ++ MHal_GMAC_write_phy(gmac_phyaddr, MII_BMCR, 0x9000UL); ++ MHal_GMAC_write_phy(gmac_phyaddr, MII_BMCR, 0x1000UL); ++ // IMPORTANT: Run NegotiationPHY() before writing REG_ETH_CFG. ++ uNegPhyVal = MHal_GMAC_NegotiationPHY(); ++ if(uNegPhyVal == 0x01UL) ++ { ++ GmacThisUVE.flagMacTxPermit = 0x01UL; ++ GmacThisBCE.duplex = 1; ++ ++ } ++ else if(uNegPhyVal == 0x02UL) ++ { ++ GmacThisUVE.flagMacTxPermit = 0x01UL; ++ GmacThisBCE.duplex = 2; ++ } ++ ++ // ETH_CFG Register ----------------------------------------------------- ++ word_ETH_CFG = 0x00000800UL; // Init: CLK = 0x2 ++ // (20070808) IMPORTANT: REG_ETH_CFG:bit1(FD), 1:TX will halt running RX frame, 0:TX will not halt running RX frame. ++ // If always set FD=0, no CRC error will occur. But throughput maybe need re-evaluate. ++ // IMPORTANT: (20070809) NO_MANUAL_SET_DUPLEX : The real duplex is returned by "negotiation" ++ if(GmacThisBCE.speed == GMAC_SPEED_100) word_ETH_CFG |= 0x00000001UL; ++ if(GmacThisBCE.duplex == 2) word_ETH_CFG |= 0x00000002UL; ++ if(GmacThisBCE.cam == 1) word_ETH_CFG |= 0x00000200UL; ++ if(GmacThisBCE.rcv_bcast == 0) word_ETH_CFG |= 0x00000020UL; ++ if(GmacThisBCE.rlf == 1) word_ETH_CFG |= 0x00000100UL; ++ ++ MHal_GMAC_Write_CFG(word_ETH_CFG); ++ // ETH_CTL Register ----------------------------------------------------- ++ word_ETH_CTL = 0x0000000CUL; // Enable transmit and receive : TE + RE = 0x0C (Disable MDIO) ++ if(GmacThisBCE.wes == 1) word_ETH_CTL |= 0x00000080UL; ++ MHal_GMAC_Write_CTL(word_ETH_CTL); ++#if 0 //FIXME latter ++ MHal_GMAC_Write_JULIAN_0100(GMAC_JULIAN_100_VAL); ++#else ++ MHal_GMAC_Write_JULIAN_0100(0x0000F001UL); ++#endif ++ ++ #ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ MHal_GMAC_Write_JULIAN_0100(0x0000F001UL); ++ #endif ++ ++ GmacThisUVE.flagPowerOn = 1; ++ GmacThisUVE.initedGMAC = 1; ++ } ++ ++ MHal_GMAC_HW_init(); ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC init Variable ++//------------------------------------------------------------------------------------------------- ++extern phys_addr_t memblock_start_of_DRAM(void); ++extern phys_addr_t memblock_size_of_first_region(void); ++ ++static phys_addr_t MDev_GMAC_VarInit(void) ++{ ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ phys_addr_t *alloRAM_VA_BASE; ++ ++ get_boot_mem_info(GMAC_MEM, &alloRAM_PA_BASE, &alloRAM_SIZE); ++#if defined (CONFIG_ARM64) ++ // get gmac addr only from mboot ++ //alloRAM_PA_BASE = memblock_start_of_DRAM() + memblock_size_of_first_region(); ++#endif ++ ++ alloRAM_VA_BASE = (phys_addr_t *)ioremap(alloRAM_PA_BASE, alloRAM_SIZE); //map buncing buffer from PA to VA ++ ++ GMAC_DBG("alloRAM_VA_BASE = 0x%zx alloRAM_PA_BASE= 0x%zx alloRAM_SIZE= 0x%zx\n", (size_t)alloRAM_VA_BASE, (size_t)alloRAM_PA_BASE, alloRAM_SIZE); ++ BUG_ON(!alloRAM_VA_BASE); ++#ifndef GMAC_RX_SOFTWARE_DESCRIPTOR ++ //Add Write Protect ++ MHal_GMAC_Write_Protect(alloRAM_PA_BASE & 0x0fffffffUL, alloRAM_SIZE); ++#endif ++ memset((phys_addr_t *)alloRAM_VA_BASE,0x00UL,alloRAM_SIZE); ++ GMAC_RAM_VA_BASE = ((phys_addr_t)alloRAM_VA_BASE + sizeof(struct GMAC_private) + 0x3FFFUL) & ~0x3FFFUL; // IMPORTANT: Let lowest 14 bits as zero. ++ GMAC_RAM_PA_BASE = ((phys_addr_t)alloRAM_PA_BASE + sizeof(struct GMAC_private) + 0x3FFFUL) & ~0x3FFFUL; // IMPORTANT: Let lowest 14 bits as zero. ++ GMAC_RX_BUFFER_BASE = GMAC_RAM_PA_BASE + GMAC_RBQP_SIZE; ++ GMAC_RBQP_BASE = GMAC_RAM_PA_BASE; ++ GMAC_TX_BUFFER_BASE = GMAC_RAM_PA_BASE + (GMAC_RX_BUFFER_SIZE + GMAC_RBQP_SIZE); ++ GMAC_RAM_VA_PA_OFFSET = GMAC_RAM_VA_BASE - GMAC_RAM_PA_BASE; // IMPORTANT_TRICK_20070512 ++ GMAC_TX_SKB_BASE = GMAC_TX_BUFFER_BASE + GMAC_MAX_RX_DESCR * sizeof(struct gmac_rbf_t); ++ ++ memset(&GmacThisBCE,0x00UL,sizeof(BasicConfigGMAC)); ++ memset(&GmacThisUVE,0x00UL,sizeof(UtilityVarsGMAC)); ++ ++ GmacThisBCE.wes = 0; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ GmacThisBCE.duplex = 2; // 1:Half-duplex, 2:Full-duplex ++ GmacThisBCE.cam = 0; // 0:No CAM, 1:Yes ++ GmacThisBCE.rcv_bcast = 0; // 0:No, 1:Yes ++ GmacThisBCE.rlf = 0; // 0:No, 1:Yes receive long frame(1522) ++ GmacThisBCE.rcv_bcast = 1; ++ GmacThisBCE.speed = GMAC_SPEED_100; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_GMAC_get_SA1H_addr(); ++ LoAddr = MHal_GMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (GmacThisBCE.sa1, &addr, 6); ++ } ++ else ++ { ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_GMAC_get_SA2H_addr(); ++ LoAddr = MHal_GMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (GmacThisBCE.sa1, &addr, 6); ++ } ++ else ++ { ++ GmacThisBCE.sa1[0] = GMAC_MY_MAC[0]; ++ GmacThisBCE.sa1[1] = GMAC_MY_MAC[1]; ++ GmacThisBCE.sa1[2] = GMAC_MY_MAC[2]; ++ GmacThisBCE.sa1[3] = GMAC_MY_MAC[3]; ++ GmacThisBCE.sa1[4] = GMAC_MY_MAC[4]; ++ GmacThisBCE.sa1[5] = GMAC_MY_MAC[5]; ++ } ++ } ++ GmacThisBCE.connected = 0; ++ return (phys_addr_t)alloRAM_VA_BASE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Initialize the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++static const struct net_device_ops mstar_lan_netdev_ops = { ++ .ndo_open = MDev_GMAC_open, ++ .ndo_stop = MDev_GMAC_close, ++ .ndo_start_xmit = MDev_GMAC_tx, ++ .ndo_set_mac_address = MDev_GMAC_set_mac_address, ++ .ndo_set_rx_mode = MDev_GMAC_set_rx_mode, ++ .ndo_do_ioctl = MDev_GMAC_ioctl, ++ .ndo_get_stats = MDev_GMAC_stats, ++}; ++#endif ++static int MDev_GMAC_setup (struct net_device *dev, unsigned long phy_type) ++{ ++ struct GMAC_private *LocPtr; ++ ++ static int already_initialized = 0; ++ dma_addr_t dmaaddr; ++ u32 val; ++ phys_addr_t RetAddr; ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ u32 retval; ++#endif ++#ifdef CONFIG_MSTAR_GMAC_JUMBO_PACKET ++ u32 retval; ++#endif ++ if (already_initialized) ++ return FALSE; ++ ++ LocPtr = (struct GMAC_private *) netdev_priv(dev); ++ ++ LocPtr->dev = dev; ++ RetAddr = MDev_GMAC_VarInit(); ++ ++ if(!RetAddr) ++ { ++ GMAC_DBG("Var init fail!!\n"); ++ return FALSE; ++ } ++ ++ if (LocPtr == NULL) ++ { ++ free_irq (dev->irq, dev); ++ GMAC_DBG("LocPtr fail\n"); ++ return -ENOMEM; ++ } ++ ++ dev->base_addr = (long) GMAC_REG_ADDR_BASE; ++ MDev_GMAC_HW_init(); ++ dev->irq = E_IRQEXPH_SECEMAC; ++ ++ // Allocate memory for DMA Receive descriptors // ++ LocPtr->dlist_phys = LocPtr->dlist = (struct gmac_recv_desc_bufs *) (GMAC_RBQP_BASE + GMAC_RAM_VA_PA_OFFSET); ++ ++ if (LocPtr->dlist == NULL) ++ { ++ dma_free_noncoherent((void *)LocPtr, GMAC_ABSO_MEM_SIZE,&dmaaddr,0);//kfree (dev->priv); ++ free_irq (dev->irq, dev); ++ return -ENOMEM; ++ } ++ ++ LocPtr->lock = &gmac_lock; ++ spin_lock_init (LocPtr->lock); ++ ether_setup (dev); ++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,28) ++ dev->open = MDev_GMAC_open; ++ dev->stop = MDev_GMAC_close; ++ dev->hard_start_xmit = MDev_GMAC_tx; ++ dev->get_stats = MDev_GMAC_stats; ++ dev->set_multicast_list = MDev_GMAC_set_rx_mode; ++ dev->do_ioctl = MDev_GMAC_ioctl; ++ dev->set_mac_address = MDev_GMAC_set_mac_address; ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ dev->netdev_ops = &mstar_lan_netdev_ops; ++#endif ++ dev->tx_queue_len = GMAC_MAX_TX_QUEUE; ++ ++ MDev_GMAC_get_mac_address (dev); // Get ethernet address and store it in dev->dev_addr // ++ MDev_GMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ spin_lock_irq (LocPtr->lock); ++ MHal_GMAC_enable_mdi (); ++ MHal_GMAC_read_phy (gmac_phyaddr, GMAC_MII_USCR_REG, &val); ++ if ((val & (1 << 10)) == 0) // DSCR bit 10 is 0 -- fiber mode // ++ LocPtr->phy_media = PORT_FIBRE; ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++ //Support for ethtool // ++ LocPtr->mii.dev = dev; ++ LocPtr->mii.mdio_read = MDev_GMAC_mdio_read; ++ LocPtr->mii.mdio_write = MDev_GMAC_mdio_write; ++ already_initialized = 1; ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_JULIAN_0104() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0104(retval); ++ dev->features |= NETIF_F_IP_CSUM; ++ ++ retval = MHal_GMAC_Read_JULIAN_0414() | GMAC_TX_V6_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0414(retval); ++ dev->features |= NETIF_F_IPV6_CSUM; ++#endif ++ ++#ifdef CONFIG_MSTAR_GMAC_JUMBO_PACKET ++ retval = MHal_GMAC_Read_JULIAN_0418() | GMAC_TX_CHECKSUM_ENABLE; ++ retval &= 0xffff0000UL; ++ retval |= GMAC_TX_JUMBO_FRAME_ENABLE; ++ MHal_GMAC_Write_JULIAN_0418(retval); ++#endif ++ //Install the interrupt handler // ++ //Notes: Modify linux/kernel/irq/manage.c /* interrupt.h */ ++ if (request_irq(dev->irq, MDev_GMAC_interrupt, SA_INTERRUPT, dev->name, dev)) ++ return -EBUSY; ++ ++#if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) && defined(CONFIG_MP_PLATFORM_INT_1_to_1_SPI) ++ irq_set_affinity_hint(dev->irq, cpu_online_mask); ++ irq_set_affinity(dev->irq, cpu_online_mask); ++#endif ++ ++ //Determine current link speed // ++ spin_lock_irq (LocPtr->lock); ++ (void) MDev_GMAC_update_linkspeed (dev); ++ spin_unlock_irq (LocPtr->lock); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Restar the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_SwReset(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private *) netdev_priv(dev); ++ u32 oldCFG, oldCTL; ++ u32 retval; ++ ++ MDev_GMAC_get_mac_address (dev); ++ oldCFG = MHal_GMAC_Read_CFG(); ++ oldCTL = MHal_GMAC_Read_CTL() & ~(GMAC_TE | GMAC_RE); ++ ++ //free tx skb ++ if (LocPtr->retx_count) ++ { ++ if (LocPtr->skb) ++ { ++ dev_kfree_skb_irq(LocPtr->skb ); ++ LocPtr->skb = NULL; ++ } ++ if (netif_queue_stopped (dev)) ++ netif_wake_queue (dev); ++ } ++ ++ netif_stop_queue (dev); ++ ++ retval = MHal_GMAC_Read_JULIAN_0100(); ++ MHal_GMAC_Write_JULIAN_0100(retval & 0x00000FFFUL); ++ MHal_GMAC_Write_JULIAN_0100(retval); ++ ++ MDev_GMAC_HW_init(); ++ MHal_GMAC_Write_CFG(oldCFG); ++ MHal_GMAC_Write_CTL(oldCTL); ++ MHal_GMAC_enable_mdi (); ++ MDev_GMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ MDev_GMAC_update_linkspeed (dev); ++ MHal_GMAC_Write_IER(GMAC_IER_FOR_INT_JULIAN_D); ++ MDev_GMAC_start (dev); ++ MDev_GMAC_set_rx_mode(dev); ++ netif_start_queue (dev); ++ LocPtr->retx_count = 0; ++ ROVRcount = 0; ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_JULIAN_0104() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0104(retval); ++ dev->features |= NETIF_F_IP_CSUM; ++#endif ++ GMAC_DBG("=> Take %lu ms to reset GMAC!\n", (getCurMs() - gmac_oldTime)); ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstargmac_of_device_ids[] = { ++ {.compatible = "mstar-gmac"}, ++ {}, ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Detect MAC and PHY and perform initialization ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_probe (struct net_device *dev) ++{ ++ int detected = -1; ++ ++ /* Read the PHY ID registers - try all addresses */ ++ detected = MDev_GMAC_setup(dev, GMAC_MII_URANUS_ID); ++ return detected; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_timer_callback(unsigned long value) ++{ ++ int ret = 0; ++ struct GMAC_private *LocPtr = (struct GMAC_private *) netdev_priv(gmac_dev); ++ static u32 bmsr, time_count = 0; ++#ifndef GMAC_INT_JULIAN_D ++ if (GMAC_RX_TMR == value) ++ { ++ MHal_GMAC_timer_callback(value); ++ return; ++ } ++#endif ++ ++ spin_lock_irq (LocPtr->lock); ++ ret = MDev_GMAC_update_linkspeed(gmac_dev); ++ spin_unlock_irq (LocPtr->lock); ++ if (0 == ret) ++ { ++ if (!GmacThisBCE.connected) ++ { ++ GmacThisBCE.connected = 1; ++ netif_carrier_on(gmac_dev); ++ } ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ time_count = 0; ++ spin_lock_irq (LocPtr->lock); ++ gmac_phy_status_register = bmsr; ++ spin_unlock_irq (LocPtr->lock); ++ // Normally, time out sets 1 Sec. ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ } ++ else //no link ++ { ++ if(GmacThisBCE.connected) { ++ GmacThisBCE.connected = 0; ++ } ++ // If disconnected is over 3 Sec, the real value of PHY's status register will report to application. ++ if(time_count > 30) { ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ spin_lock_irq (LocPtr->lock); ++ gmac_phy_status_register = bmsr; ++ spin_unlock_irq (LocPtr->lock); ++ // Report to kernel. ++ netif_carrier_off(gmac_dev); ++ GmacThisBCE.connected = 0; ++ // Normally, time out is set 1 Sec. ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ } ++ else if(time_count <= 30){ ++ time_count++; ++ // Time out is set 100ms. Quickly checks next phy status. ++ GMAC_Link_timer.expires = jiffies + (GMAC_CHECK_LINK_TIME / 10); ++ } ++ } ++ ++ add_timer(&GMAC_Link_timer); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC MACADDR Setup ++//------------------------------------------------------------------------------------------------- ++ ++#define MACADDR_FORMAT "XX:XX:XX:XX:XX:XX" ++ ++static int __init macaddr_auto_config_setup(char *addrs) ++{ ++ if (strlen(addrs) == strlen(MACADDR_FORMAT) ++ && ':' == addrs[2] ++ && ':' == addrs[5] ++ && ':' == addrs[8] ++ && ':' == addrs[11] ++ && ':' == addrs[14] ++ ) ++ { ++ addrs[2] = '\0'; ++ addrs[5] = '\0'; ++ addrs[8] = '\0'; ++ addrs[11] = '\0'; ++ addrs[14] = '\0'; ++ ++ GMAC_MY_MAC[0] = (u8)simple_strtoul(&(addrs[0]), NULL, 16); ++ GMAC_MY_MAC[1] = (u8)simple_strtoul(&(addrs[3]), NULL, 16); ++ GMAC_MY_MAC[2] = (u8)simple_strtoul(&(addrs[6]), NULL, 16); ++ GMAC_MY_MAC[3] = (u8)simple_strtoul(&(addrs[9]), NULL, 16); ++ GMAC_MY_MAC[4] = (u8)simple_strtoul(&(addrs[12]), NULL, 16); ++ GMAC_MY_MAC[5] = (u8)simple_strtoul(&(addrs[15]), NULL, 16); ++ ++ /* set back to ':' or the environment variable would be destoried */ // REVIEW: this coding style is dangerous ++ addrs[2] = ':'; ++ addrs[5] = ':'; ++ addrs[8] = ':'; ++ addrs[11] = ':'; ++ addrs[14] = ':'; ++ } ++ ++ return 1; ++} ++ ++__setup("macaddr=", macaddr_auto_config_setup); ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC init module ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ScanPhyAddr(void) ++{ ++ unsigned char addr = 1; // because address 0 = broadcast, RTL8211E will reply to broadcast addr ++ u32 value = 0; ++ ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ MHal_GMAC_Write_JULIAN_0100(0x0000F001UL); ++#else ++ MHal_GMAC_Write_JULIAN_0100(0x0000F007UL); ++#endif ++ ++ MHal_GMAC_enable_mdi(); ++ do ++ { ++ value = 0; ++ MHal_GMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ GMAC_DBG("[ PHY Addr ] ==> :%u BMSR = %08x\n", addr, value); ++ break; ++ } ++ }while(++addr && addr < 32); ++ ++ gmac_phyaddr = addr; ++ ++ if (gmac_phyaddr >= 32) ++ { ++ addr = 0; ++ MHal_GMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ GMAC_DBG("[ PHY Addr ] ==> :%u BMSR = %08x\n", addr, value); ++ gmac_phyaddr = 0; ++ } ++ else ++ { ++ GMAC_DBG("Wrong PHY Addr, maybe MoCA?\n"); ++ gmac_phyaddr = 32; ++ } ++ } ++ ++ MHal_GMAC_disable_mdi(); ++ return 0; ++} ++ ++static void Rtl_Patch(void) ++{ ++ u32 val; ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, 25, &val); ++ MHal_GMAC_write_phy(gmac_phyaddr, 25, 0x400UL); ++ MHal_GMAC_read_phy(gmac_phyaddr, 25, &val); ++} ++ ++static void MDev_GMAC_Patch_PHY(void) ++{ ++ u32 val; ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, 2, &val); ++ if (GMAC_RTL_8210 == val) ++ Rtl_Patch(); ++} ++ ++static int MDev_GMAC_init(void) ++{ ++ struct GMAC_private *LocPtr; ++ ++ if(gmac_dev) ++ return -1; ++ ++ gmac_dev = alloc_etherdev(sizeof(*LocPtr)); ++ LocPtr = netdev_priv(gmac_dev); ++ if (!gmac_dev) ++ { ++ GMAC_DBG( KERN_ERR "No GMAC dev mem!\n" ); ++ return -ENOMEM; ++ } ++ ++#if GMAC_TX_THROUGHPUT_TEST ++ printk("==========TX_THROUGHPUT_TEST==============="); ++ gmac_pseudo_packet = alloc_skb(GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ memcpy(gmac_pseudo_packet->data, (void *)gmac_packet_content, sizeof(gmac_packet_content)); ++ gmac_pseudo_packet->len = sizeof(gmac_packet_content); ++ init_timer(&GMAC_TX_timer); ++ GMAC_TX_timer.data = GMAC_RX_TMR; ++ GMAC_TX_timer.function = TX_timer_callback; ++ GMAC_TX_timer.expires = jiffies + 10*GMAC_CHECK_LINK_TIME; ++ add_timer(&GMAC_TX_timer); ++#endif ++ ++#if GMAC_RX_THROUGHPUT_TEST ++ printk("==========RX_THROUGHPUT_TEST==============="); ++ init_timer(&RX_timer); ++ ++ RX_timer.data = GMAC_RX_TMR; ++ RX_timer.function = RX_timer_callback; ++ RX_timer.expires = jiffies + 20*GMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++#endif ++#ifdef GMAC_NAPI ++ netif_napi_add(gmac_dev, &LocPtr->napi_str, MDev_GMAC_napi_poll, 10000); ++#endif ++ ++ MHal_GMAC_Power_On_Clk(); ++ ++ init_timer(&GMAC_timer); ++ init_timer(&GMAC_Link_timer); ++ ++ GMAC_timer.data = GMAC_RX_TMR; ++ GMAC_timer.function = MDev_GMAC_timer_callback; ++ GMAC_timer.expires = jiffies; ++ ++ ++ MHal_GMAC_Write_JULIAN_0100(GMAC_JULIAN_100_VAL); ++ ++ if (0 > MDev_GMAC_ScanPhyAddr()) ++ goto end; ++ ++ MDev_GMAC_Patch_PHY(); ++ if (!MDev_GMAC_probe (gmac_dev)) ++ return register_netdev (gmac_dev); ++ ++end: ++ free_netdev(gmac_dev); ++ gmac_dev = 0; ++ gmac_initstate = GMAC_ETHERNET_TEST_INIT_FAIL; ++ GMAC_DBG( KERN_ERR "Init GMAC error!\n" ); ++ return -1; ++} ++//------------------------------------------------------------------------------------------------- ++// GMAC exit module ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_exit(void) ++{ ++ if (gmac_dev) ++ { ++ #ifndef GMAC_INT_JULIAN_D ++ del_timer(&GMAC_timer); ++ #endif ++ unregister_netdev(gmac_dev); ++ free_netdev(gmac_dev); ++ } ++} ++ ++static int mstar_gmac_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct GMAC_private *LocPtr; ++ u32 uRegVal; ++ printk(KERN_INFO "mstar_gmac_drv_suspend\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev); ++ ++ LocPtr->ep_flag |= GMAC_EP_FLAG_SUSPENDING; ++ netif_stop_queue (netdev); ++ ++ disable_irq(netdev->irq); ++ del_timer(&GMAC_Link_timer); ++ ++ MHal_GMAC_Power_On_Clk(); ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ ++ // Disable PHY interrupt // ++ MHal_GMAC_disable_phyirq (); ++#ifndef GMAC_INT_JULIAN_D ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IDR(uRegVal); ++#else ++ MHal_GMAC_Write_IDR(GMAC_IER_FOR_INT_JULIAN_D); ++#endif ++ MHal_GMAC_Power_Off_Clk(); ++ MDev_GMAC_close(netdev); ++ return 0; ++} ++static int mstar_gmac_drv_resume(struct platform_device *dev) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct GMAC_private *LocPtr; ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ u32 retval; ++ printk(KERN_INFO "mstar_gmac_drv_resume\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev);; ++ LocPtr->ep_flag &= ~GMAC_EP_FLAG_SUSPENDING; ++ ++ MHal_GMAC_Power_On_Clk(); ++ ++ MHal_GMAC_Write_JULIAN_0100(GMAC_JULIAN_100_VAL); ++ ++ if (0 > MDev_GMAC_ScanPhyAddr()) ++ return -1; ++ ++ MDev_GMAC_Patch_PHY(); ++ ++ get_boot_mem_info(EMAC_MEM, &alloRAM_PA_BASE, &alloRAM_SIZE); ++#if defined(CONFIG_ARM64) ++ alloRAM_PA_BASE = memblock_start_of_DRAM() + memblock_size_of_first_region(); ++#endif ++#ifndef GMAC_RX_SOFTWARE_DESCRIPTOR ++ //Add Write Protect ++ //MHal_GMAC_Write_Protect(alloRAM_PA_BASE, alloRAM_SIZE); ++#endif ++ ++ GmacThisUVE.initedGMAC = 0; ++ MDev_GMAC_HW_init(); ++ ++ MDev_GMAC_update_mac_address (netdev); // Program ethernet address into MAC // ++ spin_lock_irq (LocPtr->lock); ++ MHal_GMAC_enable_mdi (); ++ MHal_GMAC_read_phy (gmac_phyaddr, GMAC_MII_USCR_REG, &retval); ++ if ((retval & (1 << 10)) == 0) // DSCR bit 10 is 0 -- fiber mode // ++ LocPtr->phy_media = PORT_FIBRE; ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_JULIAN_0104() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0104(retval); ++#endif ++ ++ enable_irq(netdev->irq); ++ if(0>MDev_GMAC_open(netdev)) ++ { ++ printk(KERN_WARNING "Driver GMAC: open failed after resume\n"); ++ } ++ return 0; ++} ++ ++static int mstar_gmac_drv_probe(struct platform_device *pdev) ++{ ++ int retval=0; ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-gmac") ++ || pdev->id!=0) ++ { ++ retval = -ENXIO; ++ } ++ retval = MDev_GMAC_init(); ++ if(!retval) ++ { ++ pdev->dev.platform_data=gmac_dev; ++ } ++ return retval; ++} ++ ++static int mstar_gmac_drv_remove(struct platform_device *pdev) ++{ ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-gmac") ++ || pdev->id!=0) ++ { ++ return -1; ++ } ++ MDev_GMAC_exit(); ++ pdev->dev.platform_data=NULL; ++ return 0; ++} ++ ++ ++ ++static struct platform_driver Mstar_gmac_driver = { ++ .probe = mstar_gmac_drv_probe, ++ .remove = mstar_gmac_drv_remove, ++ .suspend = mstar_gmac_drv_suspend, ++ .resume = mstar_gmac_drv_resume, ++ ++ .driver = { ++ .name = "Mstar-gmac", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstargmac_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_gmac_drv_init_module(void) ++{ ++ int retval=0; ++ ++ gmac_dev=NULL; ++ retval = platform_driver_register(&Mstar_gmac_driver); ++ return retval; ++} ++ ++static void __exit mstar_gmac_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_gmac_driver); ++ gmac_dev=NULL; ++} ++ ++#if GMAC_TX_THROUGHPUT_TEST ++module_param(gmac_tx_test, uint, 0644); ++MODULE_PARM_DESC(gmac_tx_test, "TX test for GMAC"); ++module_param(gmac_tx_thread, uint, 0644); ++MODULE_PARM_DESC(gmac_tx_thread, "TX thread sender for GMAC"); ++#endif ++ ++module_init(mstar_gmac_drv_init_module); ++module_exit(mstar_gmac_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GMAC Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/gmac/mdrv_gmac.h.old b/drivers/sstar/gmac/mdrv_gmac.h.old +new file mode 100755 +index 000000000000..a79cbd84d1bc +--- /dev/null ++++ b/drivers/sstar/gmac/mdrv_gmac.h.old +@@ -0,0 +1,312 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file GMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief GMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h define start ++// ----------------------------------------------------------------------------- ++ ++#ifndef __DRV_GMAC_H_ ++#define __DRV_GMAC_H_ ++ ++#define GMAC_DBG(fmt, args...) {printk("Mstar_gmac: "); printk(fmt, ##args);} ++#define GMAC_INFO {printk("Line:%u\n", __LINE__);} ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define GMAC_USE_TASK 1 // 1:Yes, 0:No ++#define GMAC_MTU (1524) ++ ++#ifdef GMAC_TX_QUEUE_4 ++#define GMAC_TX_RING_SIZE (8) //effected size = TX_RING_SIZE - 1 ++#else ++#define GMAC_TX_RING_SIZE (2) //effected size = TX_RING_SIZE - 1 ++#endif ++#define GMAC_RX_ZERO_COPY 1 ++#ifdef GMAC_RX_ZERO_COPY ++#define GMAC_RX_RING_SIZE (GMAC_RBQP_LENG*2) ++#endif ++#define GMAC_NAPI_WEIGHT 32 ++ ++#ifdef GMAC_NAPI ++//#define NR_NAPI 1 ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#if (!GMAC_USE_TASK) // MEM_BASE_ADJUSTMENT ...................................... ++#define GMAC_RAM_VA_BASE 0xA0000000UL ++#define GMAC_RAM_PA_BASE 0x00000000UL ++#define GMAC_RAM_VA_PA_OFFSET 0x00000000UL ++#define GMAC_RX_BUFFER_BASE 0x00000000UL // ==0xA0000000 ~~ 0xA0004000 (Max: 16 KB) ++#define GMAC_RBQP_BASE GMAC_RX_BUFFER_SIZE//0x00004000 // ==0xA0004000 ~~ 0xA0005FFF for MAX 1024 descriptors ++#define GMAC_TX_BUFFER_BASE (GMAC_RX_BUFFER_SIZE+GMAC_RBQP_SIZE)//0x00006000 // ==0xA0006000 ~~ ???????? ++#define GMAC_TX_SKB_BASE GMAC_TX_BUFFER_BASE+0x100UL//0x00006100 ++#define GMAC_RX_FRAME_ADDR GMAC_TX_SKB_BASE+0x600UL//0x00007000 // Software COPY&STORE one RX frame. Size is not defined. ++#else // The memory allocation for TASK. ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++phys_addr_t GMAC_RAM_VA_BASE; //= 0x00000000; // After init, RAM_ADDR_BASE = GMAC_ABSO_MEM_BASE ++phys_addr_t GMAC_RAM_PA_BASE; ++phys_addr_t GMAC_RAM_VA_PA_OFFSET; ++phys_addr_t GMAC_RX_BUFFER_BASE; //= 0x00000000; // IMPORTANT: lowest 14 bits as zero. ++phys_addr_t GMAC_RBQP_BASE; //= RX_BUFFER_SIZE;//0x00004000; // IMPORTANT: lowest 13 bits as zero. ++phys_addr_t GMAC_TX_BUFFER_BASE; //= (RX_BUFFER_SIZE+RBQP_SIZE);//0x00006000; ++phys_addr_t GMAC_TX_SKB_BASE; //= (RX_BUFFER_SIZE+RBQP_SIZE+0x600);//0x00006100; ++#endif //^MEM_BASE_ADJUSTMENT ............................................... ++ ++#define GMAC_ETHERNET_TEST_NO_LINK 0x00000000UL ++#define GMAC_ETHERNET_TEST_AUTO_NEGOTIATION 0x00000001UL ++#define GMAC_ETHERNET_TEST_LINK_SUCCESS 0x00000002UL ++#define GMAC_ETHERNET_TEST_RESET_STATE 0x00000003UL ++#define GMAC_ETHERNET_TEST_SPEED_100M 0x00000004UL ++#define GMAC_ETHERNET_TEST_DUPLEX_FULL 0x00000008UL ++#define GMAC_ETHERNET_TEST_INIT_FAIL 0x00000010UL ++ ++ ++u8 GMAC_MY_DEV[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; ++u8 GMAC_MY_MAC[6] = { 0x00, 0x30, 0x1B, 0xBA, 0x02, 0xDB }; ++u8 GMAC_PC_MAC[6] = { 0x00, 0x1A, 0x4B, 0x5C, 0x39, 0xDF }; ++ ++#ifdef GMAC_INT_JULIAN_D ++ u32 GmacxoffsetValue, GmacxReceiveNum; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct gmac_rbf_t ++{ ++ unsigned int addr; ++ unsigned int low_tag; ++ unsigned int high_tag; ++ unsigned int dummy; ++}; ++ ++struct gmac_recv_desc_bufs ++{ ++ struct gmac_rbf_t descriptors[GMAC_MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */ ++ char recv_buf[GMAC_RX_BUFFER_SIZE]; /* must be on MAX_RBUFF_SZ boundary */ ++}; ++ ++struct gmac_tx_ring ++{ ++ u8 used; ++ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ ++}; ++ ++#ifdef GMAC_RX_ZERO_COPY ++struct gmac_rx_ring ++{ ++ u8 used; ++ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_paddr; /* phys addr */ ++}; ++#endif ++ ++#define GMAC_EP_FLAG_OPEND 0X00000001UL ++#define GMAC_EP_FLAG_SUSPENDING 0X00000002UL ++ ++ ++struct GMAC_private ++{ ++ struct net_device_stats stats; ++ struct mii_if_info mii; /* ethtool support */ ++ ++ /* PHY */ ++ unsigned long phy_type; /* type of PHY (PHY_ID) */ ++ spinlock_t *lock; /* lock for MDI interface */ ++ spinlock_t *txlock; /* lock for MDI interface */ ++ short phy_media; /* media interface type */ ++ ++ /* Transmit */ ++ struct gmac_tx_ring tx_fifo[GMAC_TX_RING_SIZE]; ++#ifdef GMAC_RX_ZERO_COPY ++ //u64 *tx_ring; ++ dma_addr_t tx_ring_handle; ++ unsigned int tx_next; ++ unsigned int tx_next_clean; ++ unsigned int tx_current_fill; ++ /* The tx_list lock also protects the ring related variables */ ++ struct sk_buff_head tx_list; ++ ++ struct gmac_rx_ring rx_ring[GMAC_RX_RING_SIZE]; ++ /* RX variables only touched in napi_poll. No locking necessary. */ ++ //u64 *rx_ring; ++ dma_addr_t rx_ring_handle; ++ unsigned int rx_next; ++ unsigned int rx_next_fill; ++ int rx_current_fill; ++ struct sk_buff_head rx_list; ++#endif ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ struct gmac_tx_ring tx_swq[TX_SW_QUEUE_SIZE]; ++ unsigned int tx_rdidx; /* TX_SW_QUEUE read to hw index */ ++ unsigned int tx_wridx; /* TX_SW_QUEUE write index */ ++ unsigned int tx_clidx; /* TX_SW_QUEUE clear index */ ++#else ++ unsigned char tx_rdidx; /* FIFO read index */ ++ unsigned char tx_wridx; /* FIFO write index */ ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ ++ int skb_length; /* saved skb length for pci_unmap_single */ ++ unsigned char retx_count; /* resend count of tx */ ++ unsigned int txpkt; /* previous tx packet pointer */ ++ /* Receive */ ++ int rxBuffIndex; /* index into receive descriptor list */ ++ struct gmac_recv_desc_bufs *dlist; /* descriptor list address */ ++ struct gmac_recv_desc_bufs *dlist_phys; /* descriptor list physical address */ ++ ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++#ifdef CONFIG_GMAC_ISR_BH_TASKLET ++ struct work_struct rst_task; ++ struct work_struct rx_task; ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ struct work_struct tx_task; ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++#endif /* CONFIG_GMAC_ISR_BH_TASKLET */ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++ struct napi_struct napi; ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ spinlock_t *lock_rx; ++ spinlock_t *lock_rst; ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++ /* suspend/resume */ ++ unsigned long ep_flag; ++ ++ struct net_device *dev; ++ struct napi_struct napi_str; ++ unsigned int xReceiveFlag; ++}; ++ ++#define GMAC_ROUND_SUP_4(x) (((x)+3)&~3) ++ ++struct gmac_eth_drv_sgX ++{ ++ u32 buf; ++ u32 len; ++}; ++ ++struct _BasicConfigGMAC ++{ ++ u8 connected; // 0:No, 1:Yes <== (20070515) Wait for Julian's reply ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _BasicConfigGMAC BasicConfigGMAC; ++ ++struct _UtilityVarsGMAC ++{ ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ // Statistics Counters : (accumulated) ++ u32 cntREG_ETH_FRA; ++ u32 cntREG_ETH_SCOL; ++ u32 cntREG_ETH_MCOL; ++ u32 cntREG_ETH_OK; ++ u32 cntREG_ETH_SEQE; ++ u32 cntREG_ETH_ALE; ++ u32 cntREG_ETH_DTE; ++ u32 cntREG_ETH_LCOL; ++ u32 cntREG_ETH_ECOL; ++ u32 cntREG_ETH_TUE; ++ u32 cntREG_ETH_CSE; ++ u32 cntREG_ETH_RE; ++ u32 cntREG_ETH_ROVR; ++ u32 cntREG_ETH_SE; ++ u32 cntREG_ETH_ELR; ++ u32 cntREG_ETH_RJB; ++ u32 cntREG_ETH_USF; ++ u32 cntREG_ETH_SQEE; ++ // Interrupt Counter : ++ u32 cntHRESP; // Reset = 0x0000 ++ u32 cntROVR; // Reset = 0x0000 ++ u32 cntLINK; // Reset = 0x0000 ++ u32 cntTIDLE; // Reset = 0x0000 ++ u32 cntTCOM; // Reset = 0x0000 ++ u32 cntTBRE; // Reset = 0x0000 ++ u32 cntRTRY; // Reset = 0x0000 ++ u32 cntTUND; // Reset = 0x0000 ++ u32 cntTOVR; // Reset = 0x0000 ++ u32 cntRBNA; // Reset = 0x0000 ++ u32 cntRCOM; // Reset = 0x0000 ++ u32 cntDONE; // Reset = 0x0000 ++ // Flags: ++ u8 flagMacTxPermit; // 0:No,1:Permitted. Initialize as "permitted" ++ u8 flagISR_INT_RCOM; ++ u8 flagISR_INT_RBNA; ++ u8 flagISR_INT_DONE; ++ u8 flagPowerOn; // 0:Poweroff, 1:Poweron ++ u8 initedGMAC; // 0:Not initialized, 1:Initialized. ++ u8 flagRBNA; ++ // Misc Counter: ++ u32 cntRxFrames; // Reset = 0x00000000 (Counter of RX frames,no matter it's me or not) ++ u32 cntReadONE_RX; // Counter for ReadONE_RX_Frame ++ u32 cntCase20070806; ++ u32 cntChkToTransmit; ++ // Misc Variables: ++ u32 mainThreadTasks; // (20071029_CHARLES) b0=Poweroff,b1=Poweron ++}; ++typedef struct _UtilityVarsGMAC UtilityVarsGMAC; ++ ++BasicConfigGMAC GmacThisBCE; ++UtilityVarsGMAC GmacThisUVE; ++ ++typedef volatile unsigned int GMAC_REG; ++ ++struct sk_buff *Gmac_Tx_SkbAddr; ++ ++ ++#ifdef GMAC_TESTING ++ extern void GMAC_TEST_All(void); ++#endif ++ ++struct sk_buff * gmac_rx_skb[GMAC_MAX_RX_DESCR]; ++u32 gmac_rx_abso_addr[GMAC_MAX_RX_DESCR]; ++struct sk_buff * gmac_rx_skb_dummy; ++u32 gmac_rx_abso_addr_dummy; ++#endif ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h End ++// ----------------------------------------------------------------------------- ++ ++ +diff --git a/drivers/sstar/gmac/mdrv_gmac_v2.c.old b/drivers/sstar/gmac/mdrv_gmac_v2.c.old +new file mode 100755 +index 000000000000..aa4352a1ef25 +--- /dev/null ++++ b/drivers/sstar/gmac/mdrv_gmac_v2.c.old +@@ -0,0 +1,3650 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file devGMAC.c ++/// @brief GMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#elif defined(CONFIG_ARM64) ++#include ++#include ++#endif ++#include "mdrv_types.h" ++#include "mst_platform.h" ++#include "mdrv_system.h" ++#include "chip_int.h" ++#include "mhal_gmac.h" ++#include "mdrv_gmac.h" ++#include "chip_setup.h" ++ ++#ifdef CONFIG_GMAC_SUPPLY_RNG ++#include ++#include ++#include "mhal_rng_reg.h" ++#endif ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++#define GMAC_RX_TMR (0) ++#define GMAC_LINK_TMR (1) ++ ++#define GMAC_CHECK_LINK_TIME (HZ) ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++#define GMAC_IER_FOR_INT_JULIAN_D GMAC_INT_TUND|GMAC_INT_RTRY|GMAC_INT_TCOM|GMAC_INT_ROVR|GMAC_INT_RBNA ++#else /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++#define GMAC_IER_FOR_INT_JULIAN_D (0x0000E435UL) ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++#define GMAC_CHECK_CNT (500000) ++ ++#define GMAC_TX_PTK_BASE (GMAC_TX_SKB_BASE + GMAC_RAM_VA_PA_OFFSET) ++ ++#define GMAC_ALBANY_OUI_MSB (0) ++#define GMAC_RTL_8210 (0x1CUL) ++ ++#define GMAC_RX_THROUGHPUT_TEST 0 ++#define GMAC_RX_THROUGHPUT_TEST_ON_RECEIVE 0 ++#define GMAC_TX_THROUGHPUT_TEST 0 ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++#define GMAC_TX_SW_QUEUE_IN_GENERAL_TX 0 ++#define GMAC_TX_SW_QUEUE_IN_IRQ 1 ++#define GMAC_TX_SW_QUEUE_IN_TIMER 2 ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++u32 gmac_initstate= 0; ++u8 gmac_txidx =0; ++spinlock_t gmac_lock; ++spinlock_t gmac_txlock; ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++spinlock_t gmac_lock_rx; ++spinlock_t gmac_lock_rst; ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++u32 ROVRcount = 0; ++unsigned char gmac_phyaddr = 0; ++static unsigned int gmac_debug = 0; ++static unsigned int gmac_tx_debug = 0; ++static unsigned int gmac_debug_napi = 0; ++static unsigned int gmac_dump_skb = 0; ++unsigned long received_num = 0; ++ ++#ifdef GMAC_RX_ZERO_COPY ++static struct sk_buff *rx_skb[GMAC_MAX_RX_DESCR]; ++static struct sk_buff * rx_skb_dummy; ++#ifdef CONFIG_ARM64 ++static u64 rx_abso_addr[GMAC_MAX_RX_DESCR]; ++static u64 rx_abso_addr_dummy; ++#else ++static u32 rx_abso_addr[GMAC_MAX_RX_DESCR]; ++static u32 rx_abso_addr_dummy; ++#endif /* CONFIG_ARM64 */ ++ ++#ifdef CONFIG_GMAC_RX_CMA ++extern struct device *pci_cma_device; ++extern struct sk_buff *__alloc_skb_from_cma(struct device *cma_dev, unsigned int size, gfp_t gfp_mask, int flags, int node); ++#endif /* CONFIG_GMAC_RX_CMA */ ++#endif ++ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++static void MDev_GMAC_enable_INT_RX(void); ++static void MDev_GMAC_disable_INT_RX(void); ++static int MDev_GMAC_napi_poll(struct napi_struct *napi, int budget); ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ ++#ifdef GMAC_NAPI ++#ifdef NR_NAPI ++int rx_napi_weight[NR_CPUS] = {4, 8, 8, 32}; ++module_param_array(rx_napi_weight, int, NULL, 0444); ++MODULE_PARM_DESC(rx_napi_weight, "Per CPU NAPI WEIGHT parameter in GMAC."); ++struct gmac_napi_wrapper { ++ struct napi_struct napi_str; ++ int available; ++ int cpu; ++} __cacheline_aligned_in_smp; ++static struct gmac_napi_wrapper gmac_napi[NR_CPUS] __cacheline_aligned_in_smp; ++ ++//------------------------------------------------------------------------------------------------- ++// Record each core status ++//------------------------------------------------------------------------------------------------- ++struct gmac_core_state { ++ int baseline_cores; ++ int active_cores; ++ //volatile int active_cores; ++ spinlock_t lock; ++} ____cacheline_aligned_in_smp; ++ ++static struct gmac_core_state cpu_state __cacheline_aligned_in_smp; ++#endif ++#endif ++ ++// 0x78c9: link is down. ++static u32 gmac_phy_status_register = 0x78c9UL; ++ ++struct sk_buff *gmac_pseudo_packet; ++ ++#if GMAC_TX_THROUGHPUT_TEST ++static unsigned int gmac_tx_test = 0; ++static unsigned int gmac_tx_thread = 10; ++static struct task_struct *tx_tsk[20]; ++unsigned char gmac_packet_content[] = { ++0xa4, 0xba, 0xdb, 0x95, 0x25, 0x29, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x08, 0x00, 0x45, 0x00, ++0x05, 0xda, 0x69, 0x0a, 0x40, 0x00, 0x40, 0x11, 0xbe, 0x94, 0xac, 0x10, 0x5a, 0xe3, 0xac, 0x10, ++0x5a, 0x70, 0x92, 0x7f, 0x13, 0x89, 0x05, 0xc6, 0x0c, 0x5b, 0x00, 0x00, 0x03, 0x73, 0x00, 0x00, ++0x00, 0x65, 0x00, 0x06, 0xe1, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++0x13, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x18, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39 ++}; ++#endif ++ ++unsigned char ipv6udp_csumok[] = ++{ ++0x00, 0x00, 0x86, 0x05, 0x80, 0xda, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x86, 0xdd, 0x60, 0x00, ++0x00, 0x00, 0x00, 0x14, 0x11, 0x02, 0x3f, 0xfe, 0x05, 0x07, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, ++0x86, 0xff, 0xfe, 0x05, 0x80, 0xda, 0x3f, 0xfe, 0x05, 0x01, 0x04, 0x10, 0x00, 0x00, 0x02, 0xc0, ++0xdf, 0xff, 0xfe, 0x47, 0x03, 0x3e, 0xa0, 0x75, 0x82, 0x9f, 0x00, 0x14, 0xed, 0xe2, 0x05, 0x02, ++0x00, 0x00, 0xf9, 0xc8, 0xe7, 0x36, 0x85, 0x91, 0x09, 0x00 ++}; ++ ++unsigned char ipv6udp_csumerr[] = ++{ ++0x00, 0x00, 0x86, 0x05, 0x80, 0xda, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x86, 0xdd, 0x60, 0x00, ++0x00, 0x00, 0x00, 0x14, 0x11, 0x02, 0x3f, 0xfe, 0x05, 0x07, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, ++0x86, 0xff, 0xfe, 0x05, 0x80, 0xda, 0x3f, 0xfe, 0x05, 0x01, 0x04, 0x10, 0x00, 0x00, 0x02, 0xc0, ++0xdf, 0xff, 0xfe, 0x47, 0x03, 0x3e, 0xa0, 0x75, 0x82, 0x9f, 0x00, 0x14, 0x12, 0x34, 0x05, 0x02, ++0x00, 0x00, 0xf9, 0xc8, 0xe7, 0x36, 0x85, 0x91, 0x09, 0x00 ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct timer_list GMAC_timer, GMAC_Link_timer; ++#if GMAC_RX_THROUGHPUT_TEST ++#define RX_THROUGHPUT_TEST_INTERVAL 10 ++static struct timer_list GMAC_RX_timer; ++#endif ++static struct net_device *gmac_dev; ++//------------------------------------------------------------------------------------------------- ++// GMAC Function ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev); ++static void MDev_GMAC_timer_callback( unsigned long value ); ++static int MDev_GMAC_SwReset(struct net_device *dev); ++static void MDev_GMAC_irq_onoff(int enable, const char *call_from); ++//static void MDev_GMAC_Send_PausePkt(struct net_device* dev); ++#ifdef GMAC_RX_ZERO_COPY ++static int GMAC_rx_fill_ring(struct net_device *netdev); ++static int GMAC_dequeue_rx_buffer(struct GMAC_private *p, struct sk_buff **pskb); ++static int free_rx_skb(void); ++static int free_rx_skb(void) ++{ ++ int i = 0; ++ ++ for (i = 0; i < GMAC_MAX_RX_DESCR; i ++) ++ { ++ if (rx_skb[i]) ++ kfree_skb(rx_skb[i]); ++ ++ } ++ ++} ++#endif ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++static void _MDev_GMAC_tx_reset_TX_SW_QUEUE(struct net_device* netdev); ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++static void dump_skb(struct sk_buff *skb) ++{ ++ int i; ++ unsigned char *data = skb->data; ++ ++ printk("=== pdata=0x%p, len=%d ===\n", data, skb->len); ++ for (i = 0; i < skb->len; i++) { ++ if ((u32)i%0x10UL ==0) ++ printk("%lx: ", (long unsigned int)&data[i]); ++ if (data[i] < 0x10UL) ++ printk("0%x ", data[i]); ++ else ++ printk("%x ", data[i]); ++ if ((u32)i%0x10UL == 0x0fUL) ++ printk("\n"); ++ } ++ printk("\n"); ++} ++ ++unsigned long gmac_oldTime; ++static unsigned long getCurMs(void) ++{ ++ struct timeval tv; ++ unsigned long curMs; ++ ++ do_gettimeofday(&tv); ++ curMs = tv.tv_usec/1000; ++ curMs += tv.tv_sec * 1000; ++ return curMs; ++} ++ ++#if GMAC_RX_THROUGHPUT_TEST ++unsigned long gmac_receive_bytes = 0; ++static void RX_timer_callback( unsigned long value){ ++ int get_bytes = receive_bytes; ++ int cur_speed; ++ receive_bytes = 0; ++ ++ cur_speed = get_bytes*8/RX_THROUGHPUT_TEST_INTERVAL; ++ printk(" %dkbps",cur_speed); ++ GMAC_RX_timer.expires = jiffies + (RX_THROUGHPUT_TEST_INTERVAL*GMAC_CHECK_LINK_TIME); ++ add_timer(&RX_timer); ++} ++#endif ++ ++#if GMAC_TX_THROUGHPUT_TEST ++static struct timer_list GMAC_TX_timer; ++int gmac_tx_bytes = 0; ++u64 tx_bytes = 0; ++u64 tx_count = 0; ++static void TX_timer_callback( unsigned long value){ ++ u64 get_bytes = tx_bytes; ++ u64 get_count = tx_count; ++ u64 cur_speed; ++ tx_bytes = 0; ++ tx_count = 0; ++ ++ cur_speed = get_bytes*8/10; ++ printk("\n TX %llu bps count= %llu\n",cur_speed, get_count); ++ GMAC_TX_timer.expires = jiffies + 10*GMAC_CHECK_LINK_TIME; ++ add_timer(&GMAC_TX_timer); ++} ++ ++static void tx_sender(void* arg){ ++ int cpu; ++ while (1) { ++ if (gmac_tx_test) { ++ while(1){ ++ MDev_GMAC_tx(gmac_pseudo_packet, gmac_dev); ++ if (!gmac_tx_test) { ++ break; ++ } ++ } ++ } else { ++ cpu=get_cpu(); put_cpu(); ++ printk("%s %d:cpu:%d\n",__func__,__LINE__,cpu); ++ msleep(5000); ++ } ++ } ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// PHY MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Access the PHY to determine the current Link speed and Mode, and update the ++// MAC accordingly. ++// If no link or auto-negotiation is busy, then no changes are made. ++// Returns: 0 : OK ++// -1 : No link ++// -2 : AutoNegotiation still in progress ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_update_linkspeed (struct net_device *dev) ++{ ++ u32 bmsr, bmcr, physr; ++ u32 speed, duplex, LocPtrA; ++ ++ if (gmac_phyaddr >= 32) return 0; ++ /* Link status is latched, so read twice to get current value */ ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ ++ /* No link */ ++ if (!(bmsr & BMSR_LSTATUS)){ ++ return -1; ++ } ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMCR, &bmcr); ++ ++ /* AutoNegotiation is enabled */ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ GMAC_DBG("==> AutoNegotiation still in progress\n"); ++ return -2; ++ } ++ ++#ifndef CONFIG_GMAC_ETHERNET_ALBANY ++ ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_PHYSR, &physr); ++ ++ if(((physr & PHYSR_SPEED_MASK) & PHYSR_1000) && ++ ((physr & PHYSR_DUPLEX_MASK) & PHYSR_FULL_DUPLEX)) ++ { ++ speed = SPEED_1000; ++ duplex = DUPLEX_FULL; ++ } ++ else if(((physr & PHYSR_SPEED_MASK) & PHYSR_1000) && ++ !((physr & PHYSR_DUPLEX_MASK) & PHYSR_HALF_DUPLEX)) ++ { ++ speed = SPEED_1000; ++ duplex = DUPLEX_HALF; ++ } ++ else if(((physr & PHYSR_SPEED_MASK) & PHYSR_100) && ++ ((physr & PHYSR_DUPLEX_MASK) & PHYSR_FULL_DUPLEX)) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if(((physr & PHYSR_SPEED_MASK) & PHYSR_100) && ++ !((physr & PHYSR_DUPLEX_MASK) & PHYSR_HALF_DUPLEX)) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if(!((physr & PHYSR_SPEED_MASK) & PHYSR_10) && ++ ((physr & PHYSR_DUPLEX_MASK) & PHYSR_FULL_DUPLEX)) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++#else ++ MHal_GMAC_read_phy(gmac_phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ speed = SPEED_100; ++ } ++ else ++ { ++ speed = SPEED_10; ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ duplex = DUPLEX_HALF; ++ } ++#endif ++ } ++ else ++ { ++ speed = (bmcr & 0x0040) ? SPEED_1000 : ((bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); ++ duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ // Update the MAC // ++ MHal_GMAC_update_speed_duplex(speed,duplex); ++ return 0; ++} ++ ++static int MDev_GMAC_get_info(struct net_device *dev) ++{ ++ u32 bmsr, bmcr, LocPtrA; ++ u32 uRegStatus =0; ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_NO_LINK; //no link // ++ } ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_AUTO_NEGOTIATION; //AutoNegotiation // ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_LINK_SUCCESS; //link success // ++ } ++ ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ else ++ { ++ if(bmcr & BMCR_SPEED100) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if(bmcr & BMCR_FULLDPLX) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ ++ return uRegStatus; ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Program the hardware MAC address from dev->dev_addr. ++//------------------------------------------------------------------------------------------------- ++void MDev_GMAC_update_mac_address (struct net_device *dev) ++{ ++ u32 value; ++ value = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) |(dev->dev_addr[0]); ++ MHal_GMAC_Write_SA1L(value); ++ value = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]); ++ MHal_GMAC_Write_SA1H(value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// ADDRESS MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Set the ethernet MAC address in dev->dev_addr ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_get_mac_address (struct net_device *dev) ++{ ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_GMAC_get_SA1H_addr(); ++ LoAddr = MHal_GMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_GMAC_get_SA2H_addr(); ++ LoAddr = MHal_GMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++} ++ ++#ifdef GMAC_URANUS_ETHER_ADDR_CONFIGURABLE ++//------------------------------------------------------------------------------------------------- ++// Store the new hardware address in dev->dev_addr, and update the MAC. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_set_mac_address (struct net_device *dev, void *addr) ++{ ++ struct sockaddr *address = addr; ++ if (!is_valid_ether_addr (address->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy (dev->dev_addr, address->sa_data, dev->addr_len); ++ MDev_GMAC_update_mac_address (dev); ++ return 0; ++} ++#endif ++ ++#if 0 ++//------------------------------------------------------------------------------------------------- ++// Add multicast addresses to the internal multicast-hash table. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_sethashtable (struct net_device *dev) ++{ ++ struct dev_mc_list *curr; ++ u32 mc_filter[2], i, bitnr; ++ ++ mc_filter[0] = mc_filter[1] = 0; ++ ++ curr = dev->mc_list; ++ for (i = 0; i < dev->mc_count; i++, curr = curr->next) ++ { ++ if (!curr) ++ break; // unexpected end of list // ++ ++ bitnr = ether_crc (ETH_ALEN, curr->dmi_addr) >> 26; ++ mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); ++ } ++ ++ MHal_GMAC_update_HSH(mc_filter[0],mc_filter[1]); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++//Enable/Disable promiscuous and multicast modes. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_set_rx_mode (struct net_device *dev) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_CFG(); ++ ++ if (dev->flags & IFF_PROMISC) ++ { // Enable promiscuous mode // ++ uRegVal |= GMAC_CAF; ++ } ++ else if (dev->flags & (~IFF_PROMISC)) ++ { // Disable promiscuous mode // ++ uRegVal &= ~GMAC_CAF; ++ } ++ MHal_GMAC_Write_CFG(uRegVal); ++ ++ if (dev->flags & IFF_ALLMULTI) ++ { // Enable all multicast mode // ++ MHal_GMAC_update_HSH(-1,-1); ++ uRegVal |= GMAC_MTI; ++ } ++ else if (dev->flags & IFF_MULTICAST) ++ { // Enable specific multicasts// ++ //MDev_GMAC_sethashtable (dev); ++ MHal_GMAC_update_HSH(-1,-1); ++ uRegVal |= GMAC_MTI; ++ } ++ else if (dev->flags & ~(IFF_ALLMULTI | IFF_MULTICAST)) ++ { // Disable all multicast mode// ++ MHal_GMAC_update_HSH(0,0); ++ uRegVal &= ~GMAC_MTI; ++ } ++ ++ MHal_GMAC_Write_CFG(uRegVal); ++} ++//------------------------------------------------------------------------------------------------- ++// IOCTL ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable MDIO ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_mdio_read (struct net_device *dev, int phy_id, int location) ++{ ++ u32 value; ++ MHal_GMAC_read_phy (phy_id, location, &value); ++ return value; ++} ++ ++static void MDev_GMAC_mdio_write (struct net_device *dev, int phy_id, int location, int value) ++{ ++ MHal_GMAC_write_phy (phy_id, location, value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//ethtool support. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ethtool_ioctl (struct net_device *dev, void *useraddr) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 ethcmd; ++ int res = 0; ++ ++ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ spin_lock_irq (LocPtr->lock); ++ ++ switch (ethcmd) ++ { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ res = mii_ethtool_gset (&LocPtr->mii, &ecmd); ++ if (LocPtr->phy_media == PORT_FIBRE) ++ { //override media type since mii.c doesn't know // ++ ecmd.supported = SUPPORTED_FIBRE; ++ ecmd.port = PORT_FIBRE; ++ } ++ if (copy_to_user (useraddr, &ecmd, sizeof (ecmd))) ++ res = -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd ecmd; ++ if (copy_from_user (&ecmd, useraddr, sizeof (ecmd))) ++ res = -EFAULT; ++ else ++ res = mii_ethtool_sset (&LocPtr->mii, &ecmd); ++ break; ++ } ++ case ETHTOOL_NWAY_RST: ++ { ++ res = mii_nway_restart (&LocPtr->mii); ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ edata.data = mii_link_ok (&LocPtr->mii); ++ if (copy_to_user (useraddr, &edata, sizeof (edata))) ++ res = -EFAULT; ++ break; ++ } ++ default: ++ res = -EOPNOTSUPP; ++ } ++ spin_unlock_irq (LocPtr->lock); ++ return res; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// User-space ioctl interface. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct mii_ioctl_data *data = if_mii(rq); ++ ++ if (!netif_running(dev)) ++ { ++ rq->ifr_metric = GMAC_ETHERNET_TEST_INIT_FAIL; ++ } ++ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ data->phy_id = (gmac_phyaddr & 0x1F); ++ return 0; ++ ++ case SIOCDEVPRIVATE: ++ rq->ifr_metric = (MDev_GMAC_get_info(gmac_dev)|gmac_initstate); ++ return 0; ++ ++ case SIOCDEVON: ++ MHal_GMAC_Power_On_Clk(); ++ return 0; ++ ++ case SIOCDEVOFF: ++ MHal_GMAC_Power_Off_Clk(); ++ return 0; ++ ++ case SIOCGMIIREG: ++ // check PHY's register 1. ++ if((data->reg_num & 0x1fUL) == 0x1) ++ { ++ // PHY's register 1 value is set by timer callback function. ++ spin_lock_irq(LocPtr->lock); ++ data->val_out = gmac_phy_status_register; ++ spin_unlock_irq(LocPtr->lock); ++ } ++ else ++ { ++ MHal_GMAC_read_phy((gmac_phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), (u32 *)&(data->val_out)); ++ } ++ return 0; ++ ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ MHal_GMAC_write_phy((gmac_phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), data->val_in); ++ return 0; ++ ++ case SIOCETHTOOL: ++ return MDev_GMAC_ethtool_ioctl (dev, (void *) rq->ifr_data); ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// MAC ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and start the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_start (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct gmac_recv_desc_bufs *dlist, *dlist_phys; ++#ifndef GMAC_SOFTWARE_DESCRIPTOR ++ int i; ++#endif ++#ifdef GMAC_RX_ZERO_COPY ++ u32 RBQP_rx_skb_addr = 0; ++#endif ++ u32 uRegVal; ++ ++ dlist = LocPtr->dlist; ++ dlist_phys = LocPtr->dlist_phys; ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ dlist->descriptors[GMAC_MAX_RX_DESCR - 1].addr |= GMAC_DESC_WRAP; ++#else ++ for(i = 0; i < GMAC_MAX_RX_DESCR; i++) ++ { ++ dlist->descriptors[i].addr = 0; ++ dlist->descriptors[i].size = 0; ++ } ++ // Set the Wrap bit on the last descriptor // ++ dlist->descriptors[GMAC_MAX_RX_DESCR - 1].addr = GMAC_DESC_WRAP; ++#endif //#ifndef SOFTWARE_DESCRIPTOR ++ ++ // Program address of descriptor list in Rx Buffer Queue register // ++ uRegVal = ((GMAC_REG) & dlist_phys->descriptors)- GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE; ++ MHal_GMAC_Write_RBQP(uRegVal); ++ ++ //Reset buffer index// ++ LocPtr->rxBuffIndex = 0; ++ ++ // Enable Receive and Transmit // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= (GMAC_RE | GMAC_TE); ++ MHal_GMAC_Write_CTL(uRegVal); ++} ++ ++#ifdef NR_NAPI ++//------------------------------------------------------------------------------------------------- ++// Trigger the first NAPI to receive packet ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Schedule a NAPI to receive packet ++//------------------------------------------------------------------------------------------------- ++static void gmac_enable_napi(void) ++{ ++ int cpu = smp_processor_id(); ++ ++ napi_schedule(&gmac_napi[cpu].napi_str); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Trigger one avaliable CPU to receive packet ++//------------------------------------------------------------------------------------------------- ++static void gmac_enable_one_cpu(char *call_from) ++{ ++ int cpu, ret = 0; ++ unsigned long flags; ++ spin_lock_irqsave(&cpu_state.lock, flags); ++ /* if the CPU is available, trigger the NAPI polling for the CPU. */ ++ for_each_online_cpu(cpu) { ++ if (gmac_napi[cpu].available > 0) { ++ gmac_napi[cpu].available--; ++ cpu_state.active_cores++; ++ if (cpu == smp_processor_id()) { ++ BUG_ON(cpu_state.active_cores > cpu_state.baseline_cores); ++ gmac_enable_napi(); ++ } ++ else { ++ ret = smp_call_function_single(cpu, gmac_enable_napi, NULL, 0); ++ if (unlikely(gmac_debug_napi)) ++ printk("%s %d: cpu:%d active_cores:%d napi[%d].available:%d from:%s ret:%d\n",__func__,__LINE__,cpu,cpu_state.active_cores,cpu,gmac_napi[cpu].available, call_from, ret); ++ } ++ if (ret) ++ panic("Can't enable NAPI on CPU:%d.", cpu); ++ spin_unlock_irqrestore(&cpu_state.lock, flags); ++ goto out; ++ } ++ } ++ spin_unlock_irqrestore(&cpu_state.lock, flags); ++out: ++ return; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Trigger one CPU to receive packet ++//------------------------------------------------------------------------------------------------- ++static void gmac_no_more_work(struct napi_struct *napi) ++{ ++ int cur_active; ++ unsigned long flags; ++ struct gmac_napi_wrapper *gn = container_of(napi, struct gmac_napi_wrapper, napi_str); ++ ++ spin_lock_irqsave(&cpu_state.lock, flags); ++ ++ cpu_state.active_cores--; ++ cur_active = cpu_state.active_cores; ++ gn->available++; ++ BUG_ON(gn->available != 1); ++ ++ ++ if (!cur_active) { ++ /* ++ * No more CPUs doing receive packet, enable interrupt so we ++ * can start to processing again. ++ */ ++ if (unlikely(gmac_debug_napi)) ++ printk("%s %d: active core:%d cpu:%d ENABLE IRQ\n",__func__,__LINE__,cur_active, gn->cpu); ++ // Enable MAC interrupts // ++ MDev_GMAC_irq_onoff(1, __func__); ++ } ++ spin_unlock_irqrestore(&cpu_state.lock, flags); ++ ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable IRQ ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_irq_onoff(int enable, const char *call_from) ++{ ++ u32 uRegVal; ++ ++ if (enable) { ++ // Enable MAC interrupts // ++#ifndef GMAC_INT_JULIAN_D ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IER(uRegVal); ++#else ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal |= 0x00000080UL; ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++ MHal_GMAC_Write_IER(GMAC_IER_FOR_INT_JULIAN_D); ++#endif ++ } else { ++#ifndef GMAC_INT_JULIAN_D ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IDR(uRegVal); ++#else ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++ MHal_GMAC_Write_IDR(GMAC_IER_FOR_INT_JULIAN_D); ++#endif ++ } ++#if 0 ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IDR(uRegVal); ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++#endif ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Open the ethernet interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_open (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 uRegVal; ++ int ret; ++#if defined(GMAC_TX_THROUGHPUT_TEST) || defined(NR_NAPI) ++ int i; ++#endif ++ ++#ifdef GMAC_NAPI ++#ifdef NR_NAPI ++ for_each_possible_cpu(i) { ++ if (!gmac_napi[i].available) { ++ napi_enable(&gmac_napi[i].napi_str); ++ gmac_napi[i].available = 1; ++ if (unlikely(gmac_debug)) ++ printk("%s %d:enable napi%d available:%dn",__func__,__LINE__,i,gmac_napi[i].available); ++ } ++ } ++#else ++ if (!netif_running(dev)) ++ napi_enable(&LocPtr->napi_str); ++#endif ++#endif ++ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++ napi_enable(&LocPtr->napi); ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ ++ spin_lock_irq (LocPtr->lock); ++ ret = MDev_GMAC_update_linkspeed(dev); ++ spin_unlock_irq (LocPtr->lock); ++ ++ if (!is_valid_ether_addr (dev->dev_addr)) ++ return -EADDRNOTAVAIL; ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ _MDev_GMAC_tx_reset_TX_SW_QUEUE(dev); ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++ //ato GMAC_SYS->PMC_PCER = 1 << GMAC_ID_GMAC; //Re-enable Peripheral clock // ++ MHal_GMAC_Power_On_Clk(); ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= GMAC_CSR; ++ MHal_GMAC_Write_CTL(uRegVal); ++ // Enable PHY interrupt // ++ MHal_GMAC_enable_phyirq (); ++ ++ // Enable MAC interrupts // ++ MDev_GMAC_irq_onoff(1, __func__); ++ ++ LocPtr->ep_flag |= GMAC_EP_FLAG_OPEND; ++ ++ MDev_GMAC_start (dev); ++ netif_start_queue (dev); ++ ++ init_timer( &GMAC_Link_timer ); ++ GMAC_Link_timer.data = GMAC_LINK_TMR; ++ GMAC_Link_timer.function = MDev_GMAC_timer_callback; ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ add_timer(&GMAC_Link_timer); ++ ++ /* check if network linked */ ++ if (-1 == ret) ++ { ++ netif_carrier_off(dev); ++ GmacThisBCE.connected = 0; ++ } ++ else if(0 == ret) ++ { ++ netif_carrier_on(dev); ++ GmacThisBCE.connected = 1; ++ } ++#if GMAC_TX_THROUGHPUT_TEST ++ for (i = 0; i < gmac_tx_thread; i++) ++ { ++ tx_tsk[i] = kthread_create(tx_sender, NULL, "tx_sender"); ++ kthread_bind(tx_tsk[i], (i%CONFIG_NR_CPUS)); ++ if (IS_ERR(tx_tsk[i])) { ++ printk("Can't create kthread of TX sender %d failed\n"); ++ } else { ++ wake_up_process(tx_tsk[i]); ++ } ++ } ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Close the interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_close (struct net_device *dev) ++{ ++ u32 uRegVal; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++#ifdef GMAC_NAPI ++#ifdef NR_NAPI ++ int i; ++ for_each_possible_cpu(i) { ++ //netif_napi_del(&gmac_napi[i].napi_str); ++ napi_disable(&gmac_napi[i].napi_str); ++ gmac_napi[i].available = 0; ++ } ++ cpu_state.active_cores = 0; ++#else ++ if (netif_running(dev)) ++ napi_disable(&LocPtr->napi_str); ++#endif ++#endif ++ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++ napi_disable(&LocPtr->napi); ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ // Disable PHY interrupt // ++ MHal_GMAC_disable_phyirq (); ++ //Disable MAC interrupts // ++ MDev_GMAC_irq_onoff(0, __func__); ++ netif_stop_queue (dev); ++ netif_carrier_off(dev); ++ del_timer(&GMAC_Link_timer); ++ //MHal_GMAC_Power_Off_Clk(); ++ GmacThisBCE.connected = 0; ++ LocPtr->ep_flag &= (~GMAC_EP_FLAG_OPEND); ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ _MDev_GMAC_tx_reset_TX_SW_QUEUE(dev); ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update the current statistics from the internal statistics registers. ++//------------------------------------------------------------------------------------------------- ++static struct net_device_stats * MDev_GMAC_stats (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ int ale, lenerr, seqe, lcol, ecol; ++ if (netif_running (dev)) ++ { ++ unsigned long flags; ++ spin_lock_irqsave(LocPtr->lock, flags); ++ LocPtr->stats.rx_packets = received_num; ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ //LocPtr->stats.rx_packets += MHal_GMAC_Read_OK(); /* Good frames received */ ++ ale = MHal_GMAC_Read_ALE(); ++ LocPtr->stats.rx_frame_errors += ale; /* Alignment errors */ ++ lenerr = MHal_GMAC_Read_ELR(); ++ LocPtr->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ ++ seqe = MHal_GMAC_Read_SEQE(); ++ LocPtr->stats.rx_crc_errors += seqe; /* CRC error */ ++ LocPtr->stats.rx_fifo_errors += MHal_GMAC_Read_ROVR(); ++ LocPtr->stats.rx_errors += ale + lenerr + seqe + MHal_GMAC_Read_SE() + MHal_GMAC_Read_RJB(); ++ LocPtr->stats.tx_packets += MHal_GMAC_Read_FRA(); /* Frames successfully transmitted */ ++ LocPtr->stats.tx_fifo_errors += MHal_GMAC_Read_TUE(); /* Transmit FIFO underruns */ ++ LocPtr->stats.tx_carrier_errors += MHal_GMAC_Read_CSE(); /* Carrier Sense errors */ ++ LocPtr->stats.tx_heartbeat_errors += MHal_GMAC_Read_SQEE(); /* Heartbeat error */ ++ lcol = MHal_GMAC_Read_LCOL(); ++ ecol = MHal_GMAC_Read_ECOL(); ++ LocPtr->stats.tx_window_errors += lcol; /* Late collisions */ ++ LocPtr->stats.tx_aborted_errors += ecol; /* 16 collisions */ ++ LocPtr->stats.collisions += MHal_GMAC_Read_SCOL() + MHal_GMAC_Read_MCOL() + lcol + ecol; ++ } ++ return &LocPtr->stats; ++} ++ ++static int MDev_GMAC_TxRxReset(void) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x00000000UL; ++ ++ val |= (GMAC_TE|GMAC_RE|GMAC_MPE); ++ MHal_GMAC_Write_CTL(val); ++ return 0; ++} ++ ++static int MDev_GMAC_TxReset(void) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x000001FFUL; ++ ++ MHal_GMAC_Write_CTL((val & ~GMAC_TE)); ++ MHal_GMAC_Write_TCR(0); ++ MHal_GMAC_Write_CTL((MHal_GMAC_Read_CTL() | GMAC_TE)); ++ return 0; ++} ++ ++static int MDev_GMAC_CheckTSR(void) ++{ ++ u32 check; ++ u32 tsrval = 0; ++ ++ #ifdef GMAC_TX_QUEUE_4 ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ for (check = 0; check < GMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_GMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & GMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & GMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & GMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & GMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & GMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & GMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & GMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & GMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ return NETDEV_TX_OK; ++ } ++ #else ++ for (check = 0; check < GMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_GMAC_Read_TSR(); ++ ++ // check GMAC_FIFO1IDLE is ok for gmac one queue ++ if ((tsrval & GMAC_IDLETSR) && (tsrval & GMAC_FIFO1IDLE)) ++ return NETDEV_TX_OK; ++ } ++ #endif ++ ++ GMAC_DBG("Err CheckTSR:0x%x\n", tsrval); ++ MDev_GMAC_TxReset(); ++ ++ return NETDEV_TX_BUSY; ++} ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++int MDev_GMAC_GetTXFIFOIdle(void) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_GMAC_Read_TSR(); ++ avlfifo[0] = ((tsrval & GMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & GMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & GMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & GMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & GMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & GMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & GMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & GMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ return avlfifoval - 4; ++ } ++ ++ return 0; ++} ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++#if 0 ++static u8 pause_pkt[] = ++{ ++ //DA - multicast ++ 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01, ++ //SA ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ //Len-Type ++ 0x88, 0x08, ++ //Ctrl code ++ 0x00, 0x01, ++ //Ctrl para 8192 ++ 0x20, 0x00 ++}; ++#endif ++ ++#ifdef CONFIG_GMAC_NEW_TX_QUEUE ++static dma_addr_t get_tx_addr(void) ++{ ++ dma_addr_t addr; ++ static int gmac_tx_idx = 0; ++ ++ addr = GMAC_TX_PTK_BASE + (GMAC_SOFTWARE_DESC_LEN * gmac_tx_idx); ++ gmac_tx_idx++; ++ gmac_tx_idx = gmac_tx_idx % CONFIG_GMAC_NEW_TX_QUEUE_THRESHOLD; ++ ++ return addr; ++} ++#else ++static dma_addr_t get_tx_addr(void) ++{ ++ dma_addr_t addr; ++ ++ addr = GMAC_TX_PTK_BASE + GMAC_SOFTWARE_DESC_LEN * gmac_txidx; ++ gmac_txidx ++; ++ gmac_txidx = gmac_txidx % GMAC_TX_RING_SIZE; ++ return addr; ++} ++#endif /* CONFIG_GMAC_NEW_TX_QUEUE */ ++ ++void MDrv_GMAC_DumpMem(phys_addr_t addr, u32 len) ++{ ++ u8 *ptr = (u8 *)addr; ++ u32 i; ++ ++ printk("\n ===== Dump %lx, len=%d =====\n", (long unsigned int)ptr, len); ++ for (i=0; istats.tx_bytes += len; ++ ++#ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_GMAC_Write_TAR(skb_addr - GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_GMAC_Write_TCR(len); ++ ++ return NETDEV_TX_OK; ++} ++ ++static void MDev_GMAC_Send_PausePkt(struct net_device* dev) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x000001FFUL; ++ ++ //Disable Rx ++ MHal_GMAC_Write_CTL((val & ~GMAC_RE)); ++ memcpy(&pause_pkt[6], dev->dev_addr, 6); ++ MDev_GMAC_BGsend(dev, (u32)pause_pkt, sizeof(pause_pkt)); ++ //Enable Rx ++ MHal_GMAC_Write_CTL((MHal_GMAC_Read_CTL() | GMAC_RE)); ++} ++#endif ++ ++static void MDev_GMAC_Check_TXRX(int enable) ++{ ++ u32 uRegVal = 0; ++ u32 rRegVal = 0; ++ rRegVal |= (GMAC_TE|GMAC_RE|GMAC_MPE); ++ ++ if (enable) { ++ //Check if Receiver and Transmitter are enabled or not// ++again: ++ uRegVal = MHal_GMAC_Read_CTL(); ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ printk("%s %d: uRegVal:%lx rRegVal:%x\n",__func__,__LINE__,uRegVal,rRegVal); ++ if (uRegVal != rRegVal) ++ { ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ printk("%s %d: TE:%lx RE:%lx\n",__func__,__LINE__,uRegVal&GMAC_TE,uRegVal&GMAC_RE); ++ //MDev_GMAC_TxReset(); ++ MDev_GMAC_TxRxReset(); ++ goto again; ++ } ++ } else { ++ //Check if Receiver and Transmitter are enabled or not// ++ ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++// read skb from TX_SW_QUEUE to HW, ++// !!!! NO SPIN LOCK INSIDE !!!! ++static void _MDev_GMAC_tx_read_TX_SW_QUEUE(int txIdleCount,struct net_device *dev,int intr) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++ while(txIdleCount > 0){ ++ struct gmac_tx_ring *txq = &(LocPtr->tx_swq[LocPtr->tx_rdidx]); ++ if(txq->used == TX_DESC_WROTE) ++ { ++ //Chip_Flush_Cache_Range((size_t)txq->skb->data,txq->skb->len); ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ ++ MHal_GMAC_Write_TAR(txq->skb_physaddr - MIU0_BUS_BASE ); ++ MHal_GMAC_Write_TCR(txq->skb->len); ++ txq->used=TX_DESC_READ; ++ LocPtr->tx_rdidx ++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_rdidx) ++ { ++ LocPtr->tx_rdidx =0; ++ } ++ }else{ ++ break; ++ } ++ txIdleCount--; ++ } ++} ++ ++// clear skb from TX_SW_QUEUE ++// !!!! NO SPIN LOCK INSIDE !!!! ++static void _MDev_GMAC_tx_clear_TX_SW_QUEUE(int txIdleCount,struct net_device *dev,int intr) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ int clearcnt = 0; ++ int fifoCount = 0; ++ if(0 == txIdleCount) return; ++ ++ fifoCount = LocPtr->tx_rdidx - LocPtr->tx_clidx; ++ if(fifoCount < 0) fifoCount = LocPtr->tx_rdidx + (TX_SW_QUEUE_SIZE - LocPtr->tx_clidx); ++ ++ /* ++ * "fifoCount" is the count of the packets that has been sent to the GMAC HW. ++ * "(TX_FIFO_SIZE-txIdleCount)" is the packet count that has not yet been sent ++ * out completely by GMAC HW. ++ */ ++ clearcnt = fifoCount - (TX_FIFO_SIZE - txIdleCount); ++ if((clearcnt > TX_FIFO_SIZE) || (clearcnt < 0)){ ++ //printk(KERN_ERR "fifoCount in _MDev_GMAC_tx_clear_TX_SW_QUEUE() ERROR!! \ ++ fifoCount=%d intr=%d, %d, %d, %d, %d\n", fifoCount, intr, \ ++ LocPtr->tx_rdidx, LocPtr->tx_clidx, txIdleCount, TX_FIFO_SIZE); ++ } ++ ++ while(clearcnt > 0) ++ { ++ struct gmac_tx_ring *txq=&(LocPtr->tx_swq[LocPtr->tx_clidx]); ++ if(TX_DESC_READ==txq->used) ++ { ++ dma_unmap_single(&dev->dev, txq->skb_physaddr, txq->skb->len, DMA_TO_DEVICE); ++ LocPtr->stats.tx_bytes += txq->skb->len; ++ ++ dev_kfree_skb_any(txq->skb); ++ ++ txq->used = TX_DESC_CLEARED; ++ txq->skb=NULL; ++ LocPtr->tx_clidx++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_clidx) ++ { ++ LocPtr->tx_clidx =0; ++ } ++ } else { ++ break; ++ } ++ clearcnt--; ++ } ++} ++ ++static void _MDev_GMAC_tx_reset_TX_SW_QUEUE(struct net_device* netdev) ++{ ++ struct GMAC_private *LocPtr; ++ u32 i=0; ++ ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev); ++ for (i=0;itx_swq[i].skb != NULL) ++ { ++ dma_unmap_single(&netdev->dev, LocPtr->tx_swq[i].skb_physaddr ++ , LocPtr->tx_swq[i].skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb_any(LocPtr->tx_swq[i].skb); ++ } ++ LocPtr->tx_swq[i].skb = NULL; ++ LocPtr->tx_swq[i].used = TX_DESC_CLEARED; ++ LocPtr->tx_swq[i].skb_physaddr = 0; ++ } ++ LocPtr->tx_clidx = 0; ++ LocPtr->tx_wridx = 0; ++ LocPtr->tx_rdidx = 0; ++} ++ ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ spin_lock_irqsave(LocPtr->txlock, flags); ++ ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ { ++ int txIdleCount=0; ++ //FIFO full, loop until HW empty then try again ++ //This is an abnormal condition as the upper network ++ //tx_queue should already been stopped by "netif_stop_queue(dev)" in code below ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used > TX_DESC_CLEARED) ++ { ++ //printk(KERN_ERR"ABNORMAL !! %d, %d, %d, %d\n", ++ // LocPtr->tx_wridx,LocPtr->tx_rdidx, ++ // LocPtr->tx_clidx, LocPtr->tx_swq[LocPtr->tx_wridx].used ); ++ netif_stop_queue(dev); ++ //goto fifo_full; ++ goto out_unlock; ++ //BUG(); ++ } ++ ++#ifdef CONFIG_MSTAR_KANO ++ /* workaround: data bytes at the end are wrong, after dma to GMAC */ ++ if ((skb->len > 1375) && (skb->len < 1392)) { ++ skb->len = 1408; ++ } else if ((skb->len > 863) && (skb->len < 880)) { ++ skb->len = 896; ++ } else if ((skb->len > 351) && (skb->len < 368)) { ++ skb->len = 384; ++ } ++#endif /* CONFIG_MSTAR_KANO */ ++ ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ ++ //map skbuffer for DMA ++ skb_addr = dma_map_single(&dev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(&dev->dev, skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ ++ goto out_unlock; ++ } ++ ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb = skb; ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb_physaddr= skb_addr; ++ LocPtr->tx_swq[LocPtr->tx_wridx].used = TX_DESC_WROTE; ++ LocPtr->tx_wridx ++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_wridx) ++ { ++ LocPtr->tx_wridx=0; ++ } ++ ++ //if FIFO is full, netif_stop_queue ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used > TX_DESC_CLEARED) ++ { ++ netif_stop_queue(dev); ++ } ++ ++fifo_full: ++ // clear & read to HW FIFO ++ txIdleCount=MDev_GMAC_GetTXFIFOIdle(); ++ ++ _MDev_GMAC_tx_clear_TX_SW_QUEUE(txIdleCount,dev,GMAC_TX_SW_QUEUE_IN_GENERAL_TX); ++ _MDev_GMAC_tx_read_TX_SW_QUEUE(txIdleCount,dev,GMAC_TX_SW_QUEUE_IN_GENERAL_TX); ++ } ++ ++out_unlock: ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ ++ return NETDEV_TX_OK; ++} ++ ++#else /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++#ifdef CONFIG_GMAC_NEW_TX_QUEUE ++ ++static int MDev_GMAC_tx(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*)netdev_priv(dev); ++ unsigned long flags; ++ //static int tx_busy_cnt = 0; ++ dma_addr_t skb_addr; ++ ++ spin_lock_irqsave(LocPtr->txlock, flags); ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (MHal_GMAC_New_TX_QUEUE_OVRN_Get() == 1) ++ { ++ //tx_busy_cnt++; ++ //if (tx_busy_cnt > 100) { ++ // GMAC_DBG("TX queues are full, waited to xmit for %d times\n", tx_busy_cnt); ++ // tx_busy_cnt = 0; ++ //} ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ ++ return NETDEV_TX_BUSY; ++ } ++ ++ skb_addr = get_tx_addr(); ++ ++ if (!skb_addr) ++ { ++ GMAC_DBG("Can not get memory from GMAC area\n"); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ ++ return -ENOMEM; ++ } ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ ++ LocPtr->stats.tx_bytes += skb->len; ++ ++#if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++#else ++#ERROR "No Any ARCH Definition" ++#endif ++ ++ MHal_GMAC_Write_TAR(skb_addr - GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ MHal_GMAC_Write_TCR(skb->len); ++ ++ dev->trans_start = jiffies; ++ dev_kfree_skb_irq(skb); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ ++ return NETDEV_TX_OK; ++} ++ ++#else /* CONFIG_GMAC_NEW_TX_QUEUE */ ++static int busy_count; ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ spin_lock_irqsave(LocPtr->txlock, flags); ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (NETDEV_TX_OK != MDev_GMAC_CheckTSR()) ++ { ++#if 0 ++ busy_count ++; ++ if (busy_count >= 3) { ++ spin_lock_irqsave(LocPtr->lock, flags); ++ MDev_GMAC_SwReset(dev); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ } else { ++ busy_count = 0; ++ } ++#endif ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ return NETDEV_TX_BUSY; //check ++ } ++ ++#ifndef GMAC_TX_SKB_PTR ++ #ifndef GMAC_TX_QUEUE_4 ++ skb_addr = get_tx_addr(); ++ ++ #ifdef GMAC_K3_SW_PATCH ++ if(_OFFSET_CONDITION(skb->len)) ++ skb_addr+=0x40UL; ++ #endif ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ #else ++ skb_addr = get_tx_addr(); ++ ++ #ifdef GMAC_K3_SW_PATCH ++ if(_OFFSET_CONDITION(skb->len)) ++ skb_addr+=0x40UL; ++ #endif ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ #endif ++#else ++ LocPtr->txpkt = dma_map_single(NULL, skb->data, skb->len,DMA_TO_DEVICE); ++#endif ++ ++ if (!skb_addr) ++ { ++ dev_err(NULL, ++ "dma map 2 failed (%p, %i). Dropping packet\n", ++ skb->data, skb->len); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ return -ENOMEM; ++ } ++ ++ // Store packet information (to free when Tx completed) // ++ LocPtr->stats.tx_bytes += skb->len; ++ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ //Moniter TX packet ++ //MDrv_GMAC_DumpMem(skb_addr, skb->len); ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_GMAC_Write_TAR(skb_addr - GMAC_RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_GMAC_Write_TCR(skb->len); ++ ++ //netif_stop_queue (dev); ++ dev->trans_start = jiffies; ++#if GMAC_TX_THROUGHPUT_TEST ++ if (gmac_tx_test) { ++ tx_bytes += skb->len; ++ tx_count ++; ++ } ++ else { ++ dev_kfree_skb_irq(skb); ++ } ++#else ++ dev_kfree_skb_irq(skb); ++#endif ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ return NETDEV_TX_OK; ++} ++ ++#endif /* CONFIG_GMAC_NEW_TX_QUEUE */ ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Disable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_rx (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct gmac_recv_desc_bufs *dlist; ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 retval=0; ++ u32 received=0; ++ struct sk_buff *skb; ++ u32 RBQP_offset; ++ u32 RBQP_rx_skb_addr = 0; ++ ++ dlist = LocPtr->dlist ; ++ ++ do ++ { ++ if (LocPtr->rx_current_fill < 5) ++ { ++ GMAC_rx_fill_ring(gmac_dev); ++ } ++ ++#if defined(CONFIG_MIPS) ++ Chip_Read_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex])) & 0x0FFFFFFFUL, ++ sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ //Chip_Inv_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ // (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET, ++ // sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ Chip_Flush_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET, ++ sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++#else ++#ERROR "No Any ARCH Definition" ++#endif /* CONFIG_MIPS CONFIG_ARM CONFIG_ARM64 */ ++ ++ if (!((dlist->descriptors[LocPtr->rxBuffIndex].addr) & GMAC_DESC_DONE)) ++ { ++ if (unlikely(gmac_debug)) ++ GMAC_DBG("CPU:%d rxBuffIndex:%d GMAC_DESC_DONE break\n",smp_processor_id(),LocPtr->rxBuffIndex); ++ break; ++ } ++ ++ p_recv = (char *)((((dlist->descriptors[LocPtr->rxBuffIndex].addr) & 0xFFFFFFFFUL) + \ ++ GMAC_RAM_VA_PA_OFFSET + GMAC_MIU0_BUS_BASE) & \ ++ ~(GMAC_DESC_DONE | GMAC_DESC_WRAP)); ++ /* Length of frame including FCS */ ++ pktlen = ((dlist->descriptors[LocPtr->rxBuffIndex].high_tag & 0x7) << 11) | \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & 0x7ffUL); ++ ++ if (pktlen < 64) ++ { ++ /* the pktlen */ ++ GMAC_DBG("Receive invalid packet with length=%d\n", pktlen); ++ goto no_receive; ++ } ++ ++ /* skip 4 CRC bytes at the end of data */ ++ pktlen -= 4; ++ ++ if (pktlen > GMAC_SOFTWARE_DESC_LEN) ++ { ++ GMAC_DBG("Receive invalid packet with length=%d\n", pktlen); ++ GMAC_DBG("pktlen:%d > GMAC_SOFTWARE_DESC_LEN:%d\n",pktlen,GMAC_SOFTWARE_DESC_LEN); ++ goto no_receive; ++ } ++ ++ skb_put(rx_skb[LocPtr->rxBuffIndex], pktlen); ++ rx_skb[LocPtr->rxBuffIndex]->dev = dev; ++ rx_skb[LocPtr->rxBuffIndex]->protocol = eth_type_trans(rx_skb[LocPtr->rxBuffIndex], dev); ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++ ++ if(((dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP ) || \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_UDP )) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_IP_CSUM) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP_UDP_CSUM)) ++ { ++ rx_skb[LocPtr->rxBuffIndex]->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ rx_skb[LocPtr->rxBuffIndex]->ip_summed = CHECKSUM_NONE; ++ } ++ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++#ifdef CONFIG_GMAC_NAPI_GRO ++ retval = napi_gro_receive(&LocPtr->napi, rx_skb[LocPtr->rxBuffIndex]); ++#else ++ retval = netif_receive_skb(rx_skb[LocPtr->rxBuffIndex]); ++#endif /* CONFIG_GMAC_NAPI_GRO */ ++#else ++ retval = netif_rx_ni(rx_skb[LocPtr->rxBuffIndex]); ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ ++ received++; ++ received_num += received; ++ ++no_receive: ++ ++ GMAC_dequeue_rx_buffer(LocPtr, &skb); ++ if (!skb) ++ { ++ GMAC_DBG("%s[%d]: rx_next:%d rx_next_fill:%d rx_current_fill:%d\n", ++ __func__, __LINE__, LocPtr->rx_next, LocPtr->rx_next_fill, LocPtr->rx_current_fill); ++ panic("Can't dequeue skb from buffer."); ++ } ++ rx_skb[LocPtr->rxBuffIndex] = skb; ++ rx_abso_addr[LocPtr->rxBuffIndex] = rx_skb[LocPtr->rxBuffIndex]->data; ++ ++ RBQP_offset = LocPtr->rxBuffIndex * 16; ++ if(LocPtr->rxBuffIndex < (GMAC_MAX_RX_DESCR-1)) ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[LocPtr->rxBuffIndex]) - GMAC_MIU0_BUS_BASE; ++ RBQP_rx_skb_addr |= GMAC_DESC_DONE; ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ else ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[LocPtr->rxBuffIndex]) - \ ++ GMAC_MIU0_BUS_BASE + GMAC_DESC_WRAP; ++ RBQP_rx_skb_addr |= GMAC_DESC_DONE; ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ ++ if (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ ++ /* reset ownership bit */ ++ dlist->descriptors[LocPtr->rxBuffIndex].addr &= ~GMAC_DESC_DONE; ++ ++#if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)) & 0x0FFFFFFFUL, ++ sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET, ++ sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++#else ++#ERROR "No Any ARCH Definition" ++#endif ++ ++ LocPtr->rxBuffIndex++; ++ if (LocPtr->rxBuffIndex == GMAC_MAX_RX_DESCR) ++ { ++ LocPtr->rxBuffIndex = 0; ++ } ++ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++ if(received >= CONFIG_GMAC_NAPI_WEIGHT) ++ { ++ break; ++ } ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ ++ } while (1); ++ ++ GmacxReceiveNum=0; ++ GmacThisUVE.flagRBNA=0; ++ ++ GMAC_rx_fill_ring(gmac_dev); ++ ++ return received; ++} ++ ++#else /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++static int MDev_GMAC_rx (struct net_device *dev, int budget) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct gmac_recv_desc_bufs *dlist; ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 retval=0; ++ u32 received=0; ++ struct sk_buff *skb; ++#ifdef GMAC_RX_ZERO_COPY ++ u32 uRegVal = 0; ++ u32 RBQP_offset; ++ u32 RBQP_rx_skb_addr = 0; ++#endif ++#ifndef GMAC_INT_JULIAN_D ++ u32 uRegVal=0; ++ int count = 0; ++#endif ++ unsigned long flags; ++ ++#ifdef NR_NAPI ++ if (received == 0) { ++ u32 packets_in_hw; ++ int in_use = cpu_state.active_cores; ++ //In the first time, we check received packet of HW, then decide how many core we must trigger for this moment. ++ packets_in_hw = MHal_GMAC_Read_OK();/* Good frames received */ ++ if (packets_in_hw > (budget * in_use)) { ++ if (unlikely(gmac_debug_napi)) ++ GMAC_DBG("cpu:%d packets in hw:%u. (budget * in_use)=%d. We call one more core\n",smp_processor_id(),packets_in_hw,(budget * in_use)); ++ gmac_enable_one_cpu(__func__); ++ } ++ ++ } ++#endif ++ ++ dlist = LocPtr->dlist ; ++ // If any Ownership bit is 1, frame received. ++ //while ( (dlist->descriptors[LocPtr->rxBuffIndex].addr )& GMAC_DESC_DONE) ++ do ++ { ++ spin_lock_irqsave(LocPtr->lock, flags); ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Read_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex])) & 0x0FFFFFFFUL, sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET ,sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #else ++ #ERROR ++ #endif ++#endif ++ if(!((dlist->descriptors[LocPtr->rxBuffIndex].addr) & GMAC_DESC_DONE)) ++ { ++ if (unlikely(gmac_debug)) ++ GMAC_DBG("CPU:%d rxBuffIndex:%d GMAC_DESC_DONE break\n",smp_processor_id(),LocPtr->rxBuffIndex); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ break; ++ } ++ ++ p_recv = (char *) ((((dlist->descriptors[LocPtr->rxBuffIndex].addr) & 0xFFFFFFFFUL) + GMAC_RAM_VA_PA_OFFSET + GMAC_MIU0_BUS_BASE) & ~(GMAC_DESC_DONE | GMAC_DESC_WRAP)); ++ pktlen = ((dlist->descriptors[LocPtr->rxBuffIndex].high_tag & 0x7) << 11) | (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & 0x7ffUL); /* Length of frame including FCS */ ++ ++ #if GMAC_RX_THROUGHPUT_TEST ++ gmac_receive_bytes += pktlen; ++ #if GMAC_RX_THROUGHPUT_TEST_ON_RECEIVE ++ kfree_skb(skb); ++ goto no_receive; ++ #endif ++ #endif ++ ++#ifdef GMAC_RX_ZERO_COPY ++ if (pktlen > GMAC_SOFTWARE_DESC_LEN) ++ { ++ if (unlikely(gmac_debug)) ++ GMAC_DBG("pktlen:%d > GMAC_SOFTWARE_DESC_LEN:%d\n",pktlen,GMAC_SOFTWARE_DESC_LEN); ++#endif ++ skb = alloc_skb (pktlen + 6, GFP_ATOMIC); ++ ++ if (skb != NULL) ++ { ++ skb_reserve (skb, 2); ++ #ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)p_recv < 0xC0000000UL) ++ { ++ Chip_Read_Memory_Range((unsigned int)(p_recv) & 0x0FFFFFFFUL, pktlen); ++ } ++ else ++ { ++ Chip_Read_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range_VA_PA((size_t)p_recv,(size_t)p_recv - GMAC_RAM_VA_PA_OFFSET ,pktlen); ++ #else ++ #ERROR ++ #endif ++ #endif ++ memcpy(skb_put(skb, pktlen), p_recv, pktlen); ++ skb->dev = dev; ++ skb->protocol = eth_type_trans (skb, dev); ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++ ++ #ifdef GMAC_RX_CHECKSUM ++ if(((dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP ) || (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_UDP )) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_IP_CSUM) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ skb->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ } ++ else ++ { ++ LocPtr->stats.rx_dropped += 1; ++ } ++#ifdef GMAC_RX_ZERO_COPY ++ } ++ else ++ { ++ skb_put(rx_skb[LocPtr->rxBuffIndex], pktlen); ++ // update consumer pointer// ++ rx_skb[LocPtr->rxBuffIndex]->dev = dev; ++ rx_skb[LocPtr->rxBuffIndex]->protocol = eth_type_trans (rx_skb[LocPtr->rxBuffIndex], dev); ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++ #ifdef GMAC_RX_CHECKSUM ++ if(((dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP ) || (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_UDP )) \ ++ && (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_IP_CSUM) \ ++ && (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ rx_skb[LocPtr->rxBuffIndex]->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ rx_skb[LocPtr->rxBuffIndex]->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ } ++#endif /*GMAC_RX_ZERO_COPY*/ ++ ++ #ifdef GMAC_NAPI ++ #ifdef GMAC_RX_ZERO_COPY ++ retval = netif_receive_skb(rx_skb[LocPtr->rxBuffIndex]); ++ if (gmac_dump_skb) ++ dump_skb(rx_skb[LocPtr->rxBuffIndex]); ++ #else ++ retval = netif_receive_skb(skb); ++ if (gmac_dump_skb) ++ dump_skb(skb); ++ #endif ++ #else ++ #ifdef GMAC_RX_ZERO_COPY ++ retval = netif_rx (rx_skb[LocPtr->rxBuffIndex]); ++ #else ++ retval = netif_rx(skb); ++ #endif ++ #endif ++ ++ received++; ++ received_num += received; ++no_receive: ++ ++#ifdef GMAC_RX_ZERO_COPY ++ GMAC_dequeue_rx_buffer(LocPtr, &skb); ++ if (!skb) { ++ GMAC_DBG("%d: rx_next:%d rx_next_fill:%d rx_current_fill:%d\n",__LINE__,LocPtr->rx_next, LocPtr->rx_next_fill, LocPtr->rx_current_fill); ++ panic("Can't dequeue skb from buffer."); ++ } ++ rx_skb[LocPtr->rxBuffIndex] = skb; ++ rx_abso_addr[LocPtr->rxBuffIndex] = rx_skb[LocPtr->rxBuffIndex]->data; ++ ++ RBQP_offset = LocPtr->rxBuffIndex * 16; ++ if(LocPtr->rxBuffIndex<(GMAC_MAX_RX_DESCR-1)) ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[LocPtr->rxBuffIndex]) - GMAC_MIU0_BUS_BASE; ++ RBQP_rx_skb_addr |= GMAC_DESC_DONE; ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ else ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[LocPtr->rxBuffIndex]) - GMAC_MIU0_BUS_BASE + GMAC_DESC_WRAP; ++ RBQP_rx_skb_addr |= GMAC_DESC_DONE; ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++#endif ++ ++ if (dlist->descriptors[LocPtr->rxBuffIndex].low_tag & GMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ dlist->descriptors[LocPtr->rxBuffIndex].addr &= ~GMAC_DESC_DONE; /* reset ownership bit */ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((unsigned int)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)) & 0x0FFFFFFFUL, sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])), ++ (unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex])) - GMAC_RAM_VA_PA_OFFSET ,sizeof(dlist->descriptors[LocPtr->rxBuffIndex])); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ //wrap after last buffer // ++ LocPtr->rxBuffIndex++; ++ if (LocPtr->rxBuffIndex == GMAC_MAX_RX_DESCR) ++ { ++ LocPtr->rxBuffIndex = 0; ++ } ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ ++ #ifdef CONFIG_GMAC_SUPPLY_RNG ++ { ++ static unsigned long u32LastInputRNGJiff=0; ++ unsigned long u32Jiff=jiffies; ++ ++ if ( time_after(u32Jiff, u32LastInputRNGJiff+InputRNGJiffThreshold) ) ++ { ++ unsigned int u32Temp; ++ unsigned short u16Temp; ++ ++ u32LastInputRNGJiff = u32Jiff; ++ u16Temp = MIPS_REG(REG_RNG_OUT); ++ memcpy((unsigned char *)&u32Temp+0, &u16Temp, 2); ++ u16Temp = MIPS_REG(REG_RNG_OUT); ++ memcpy((unsigned char *)&u32Temp+2, &u16Temp, 2); ++ add_input_randomness(EV_MSC, MSC_SCAN, u32Temp); ++ } ++ } ++ #endif ++#ifdef GMAC_NAPI ++ }while(received < budget); ++#else ++ }while(1); ++#endif ++#ifdef GMAC_INT_JULIAN_D ++ GmacxReceiveNum=0; ++ GmacThisUVE.flagRBNA=0; ++#endif ++#ifdef GMAC_RX_ZERO_COPY ++ spin_lock_irqsave(LocPtr->lock, flags); ++ GMAC_rx_fill_ring(gmac_dev); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++#endif ++ ++ return received; ++} ++ ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++#ifdef CONFIG_GMAC_ISR_BH_TASKLET ++void MDev_GMAC_bottom_rx_task(unsigned long data) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(gmac_dev); ++ unsigned long flags; ++ u32 uRegVal; ++ ++ spin_lock_irqsave(LocPtr->lock_rx, flags); ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++ MDev_GMAC_rx(gmac_dev); ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal |= 0x00000080UL; ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++ spin_unlock_irqrestore(LocPtr->lock_rx, flags); ++} ++ ++void MDev_GMAC_bottom_rst_task(unsigned long data) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(gmac_dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(LocPtr->lock_rx, flags); ++ spin_lock_irqsave(LocPtr->txlock, flags); ++ LocPtr->stats.rx_over_errors++; ++ MHal_GMAC_Write_RSR(GMAC_RSROVR); ++ MDev_GMAC_SwReset(gmac_dev); ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++ spin_unlock_irqrestore(LocPtr->lock_rx, flags); ++} ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++void MDev_GMAC_bottom_tx_task(unsigned long data) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(gmac_dev); ++ int txIdleCount = 0; ++ unsigned long flags; ++ u32 uRegVal; ++ ++ spin_lock_irqsave(LocPtr->txlock, flags); ++ uRegVal = GMAC_INT_TCOM; ++ MHal_GMAC_Write_IDR(uRegVal); ++ txIdleCount=MDev_GMAC_GetTXFIFOIdle(); ++ ++ while(txIdleCount>0 && (LocPtr->tx_rdidx != LocPtr->tx_wridx)) ++ { ++ _MDev_GMAC_tx_clear_TX_SW_QUEUE(txIdleCount,gmac_dev,GMAC_TX_SW_QUEUE_IN_IRQ); ++ _MDev_GMAC_tx_read_TX_SW_QUEUE(txIdleCount,gmac_dev,GMAC_TX_SW_QUEUE_IN_IRQ); ++ txIdleCount=MDev_GMAC_GetTXFIFOIdle(); ++ } ++ uRegVal = GMAC_INT_TCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IER(uRegVal); ++ txIdleCount=MDev_GMAC_GetTXFIFOIdle(); ++ ++ if (txIdleCount > 0) { ++ if (netif_queue_stopped(gmac_dev)) ++ netif_wake_queue(gmac_dev); ++ } ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++} ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++#endif /* CONFIG_GMAC_ISR_BH_TASKLET */ ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++#ifdef GMAC_INT_JULIAN_D ++ ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++irqreturn_t MDev_GMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 intstatus=0; ++ u32 xReceiveFlag=0; ++ unsigned long flags; ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ int txIdleCount = 0; ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ /* MAC Interrupt Status register indicates what interrupts are pending. */ ++ /* It is automatically cleared once read. */ ++ GmacxoffsetValue = MHal_GMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ ++ if(GmacxoffsetValue&0x8000UL) ++ { ++ xReceiveFlag = 1; ++ } ++ intstatus = MHal_GMAC_Read_ISR() & ~MHal_GMAC_Read_IMR() & GMAC_INT_MASK; ++ { ++ if (intstatus & GMAC_INT_RBNA) ++ { ++ LocPtr->stats.rx_dropped ++; ++ xReceiveFlag = 1; ++ /* write 1 clear */ ++ MHal_GMAC_Write_RSR(GMAC_BNA); ++ } ++ ++ /* RX Overrun */ ++ if(intstatus & GMAC_INT_ROVR) ++ { ++/* Reset should do rapidly, if ROVR. So, do not push it to BH. */ ++#if 0//def CONFIG_GMAC_ISR_BH_TASKLET ++ tasklet_schedule(&LocPtr->rst_task); ++#else ++ LocPtr->stats.rx_dropped++; ++ ++ /* write 1 clear RX overrun */ ++ MHal_GMAC_Write_RSR(GMAC_RSROVR); ++ MDev_GMAC_SwReset(dev); ++#endif /* CONFIG_GMAC_ISR_BH_TASKLET */ ++ } ++ ++ /* Receive complete */ ++ if(xReceiveFlag == 1) ++ { ++ xReceiveFlag = 0; ++#ifdef CONFIG_GMAC_ISR_BH_TASKLET ++ tasklet_hi_schedule(&LocPtr->rx_task); ++#elif CONFIG_GMAC_ISR_BH_NAPI ++ if (napi_schedule_prep(&LocPtr->napi)) ++ { ++ MDev_GMAC_disable_INT_RX(); ++ __napi_schedule(&LocPtr->napi); ++ } ++#else ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ MDev_GMAC_rx(dev); ++ spin_lock_irqsave(LocPtr->lock, flags); ++#endif /* CONFIG_GMAC_ISR_BH_TASKLET */ ++ } ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ // Transmit complete // ++ if (intstatus & GMAC_INT_TCOM) ++ { ++#ifdef CONFIG_GMAC_ISR_BH_TASKLET ++ tasklet_schedule(&LocPtr->tx_task); ++#else ++ spin_lock_irqsave(LocPtr->txlock, flags); ++ if( ((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ { ++ netif_wake_queue(dev); ++ } ++ ++ txIdleCount = MDev_GMAC_GetTXFIFOIdle(); ++ while(txIdleCount > 0 && (LocPtr->tx_rdidx != LocPtr->tx_wridx)) ++ { ++ _MDev_GMAC_tx_clear_TX_SW_QUEUE(txIdleCount,dev,GMAC_TX_SW_QUEUE_IN_IRQ); ++ _MDev_GMAC_tx_read_TX_SW_QUEUE(txIdleCount,dev,GMAC_TX_SW_QUEUE_IN_IRQ); ++ txIdleCount = MDev_GMAC_GetTXFIFOIdle(); ++ } ++ spin_unlock_irqrestore(LocPtr->txlock, flags); ++#endif /* CONFIG_GMAC_ISR_BH_TASKLET */ ++ } ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ } ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++#else /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++irqreturn_t MDev_GMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 intstatus=0; ++ u32 xReceiveFlag=0; ++ unsigned long flags; ++ u32 uRegVal; ++ ++#ifndef GMAC_RX_ZERO_COPY ++ u32 wp = 0; ++#endif ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ GmacxoffsetValue = MHal_GMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ ++#ifndef GMAC_RX_ZERO_COPY ++ wp = MHal_GMAC_Read_JULIAN_0100() & 0x00100000UL; ++ if(wp) ++ { ++ GMAC_DBG("GMAC HW write invalid address"); ++ } ++#endif ++ ++ if(GmacxoffsetValue&0x8000UL) ++ { ++ xReceiveFlag = 1; ++ } ++ ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ GMAC_DBG("xReceiveFlag:%d\n",xReceiveFlag); ++ ++ GmacThisUVE.flagRBNA = 0; ++ ++ ++ gmac_oldTime = getCurMs(); ++ while((xReceiveFlag == 1) || (intstatus = (MHal_GMAC_Read_ISR() & ~MHal_GMAC_Read_IMR() & GMAC_INT_MASK )) ) ++ { ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ GMAC_DBG("intstatus:%x\n",intstatus); ++ if (((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ { ++ netif_wake_queue(dev); ++ } ++ ++ if (intstatus & GMAC_INT_RBNA) ++ { ++ LocPtr->stats.rx_dropped ++; ++ GmacThisUVE.flagRBNA = 1; ++ xReceiveFlag = 1; ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_BNA); ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ GMAC_DBG("GMAC_INT_RBNA xReceiveFlag:%d\n",xReceiveFlag); ++ } ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (GMAC_INT_TUND | GMAC_INT_RTRY)) ++ { ++ LocPtr->stats.tx_errors += 1; ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ GMAC_DBG("intstatus & GMAC_INT_TUND | GMAC_INT_RTRY\n"); ++ ++ if(intstatus & GMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_GMAC_Write_TSR(GMAC_UND); ++ ++ //Reset TX engine ++ MDev_GMAC_TxReset(); ++ GMAC_DBG ("Transmit TUND error, TX reset\n"); ++ } ++ } ++ ++ if(intstatus&GMAC_INT_DONE) ++ { ++ GmacThisUVE.flagISR_INT_DONE = 0x01UL; ++ } ++ ++ //RX Overrun // ++ if(intstatus & GMAC_INT_ROVR) ++ { ++ LocPtr->stats.rx_dropped++; ++ ROVRcount++; ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ GMAC_DBG("intstatus & GMAC_INT_ROVR ROVRcount:%d\n",ROVRcount); ++ ++ //write 1 clear RX overrun ++ MHal_GMAC_Write_RSR(GMAC_RSROVR); ++ ++ if (ROVRcount >= 1) ++ { //If ROVRcount happens 6 times, we had better do SwReset ++ MDev_GMAC_SwReset(dev); ++ if (unlikely(gmac_debug || gmac_debug_napi)) ++ GMAC_DBG("intstatus & GMAC_INT_ROVR ROVRcount:%d SWReset\n",ROVRcount); ++ } ++ } ++ else ++ { ++ ROVRcount = 0; ++ } ++ ++ // Receive complete // ++ if(xReceiveFlag == 1) ++ { ++ xReceiveFlag = 0; ++ #ifdef GMAC_NAPI ++#if 0 ++ MDev_GMAC_irq_onoff(0, __func__); ++#else ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_IER_FOR_INT_JULIAN_D; ++ MHal_GMAC_Write_IDR(uRegVal); ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++#endif ++ ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ #ifdef NR_NAPI ++ gmac_enable_one_cpu(__func__); ++ //gmac_enable_napi(); ++ #else ++ napi_schedule(&LocPtr->napi_str); ++ #endif ++ #else ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ MDev_GMAC_rx(dev, GMAC_NAPI_WEIGHT); ++ spin_lock_irqsave(LocPtr->lock, flags); ++ #endif ++ } ++ } ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return IRQ_HANDLED; ++} ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++#endif //#ifdef GMAC_INT_JULIAN_D ++ ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++static void MDev_GMAC_enable_INT_RX(void) { ++ u32 uRegVal; ++ ++ /* enable delay interrupt */ ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal |= 0x00000080UL; ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++} ++ ++static void MDev_GMAC_disable_INT_RX(void) { ++ u32 uRegVal; ++ ++ /* disable delay interrupt */ ++ uRegVal = MHal_GMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_JULIAN_0104(uRegVal); ++} ++ ++static int MDev_GMAC_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct GMAC_private *LocPtr = container_of(napi, struct GMAC_private, napi); ++ struct net_device *dev = LocPtr->dev; ++ unsigned long flags = 0; ++ int work_done = 0; ++ ++ work_done = MDev_GMAC_rx(dev); ++ ++ /* If budget not fully consumed, exit the polling mode */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ // enable MAC interrupt ++ spin_lock_irqsave(LocPtr->lock, flags); ++ MDev_GMAC_enable_INT_RX(); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ } ++ ++ return work_done; ++} ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++#else /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++static int MDev_GMAC_napi_poll(struct napi_struct *napi, int budget) ++{ ++#ifdef NR_NAPI ++ struct net_device *dev = napi->dev; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++#else ++ struct GMAC_private *LocPtr = container_of(napi, struct GMAC_private, napi_str); ++ struct net_device *dev = LocPtr->dev; ++#endif ++ unsigned long flags; ++ int work_done = 0; ++ u32 uRegVal; ++ ++ work_done = MDev_GMAC_rx(dev, budget); ++ ++ //printk("work_done = %d, budget = %d\n",work_done, budget); ++ if (work_done < budget) ++ { ++ /* ++ * Order is important since data can get interrupted ++ * again when we think we are done. ++ */ ++ __napi_complete(napi); ++ ++#ifdef NR_NAPI ++ gmac_no_more_work(napi); ++#else ++ // Enable MAC interrupts // ++ MDev_GMAC_irq_onoff(1, __func__); ++#endif ++ } ++ ++ return work_done; ++} ++ ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++void MDev_GMAC_HW_init(void) ++{ ++ u32 word_ETH_CTL = 0x00000000UL; ++ u32 word_ETH_CFG = 0x00000800UL; ++ u32 uJulian104Value = 0; ++ u32 uNegPhyVal = 0; ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ u32 idxRBQP = 0; ++ u32 RBQP_offset = 0; ++#endif ++#ifdef GMAC_RX_ZERO_COPY ++ struct sk_buff *skb = NULL; ++ u32 RBQP_rx_skb_addr = 0; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(gmac_dev); ++#endif ++ // (20071026_CHARLES) Disable TX, RX and MDIO: (If RX still enabled, the RX buffer will be overwrited) ++ MHal_GMAC_Write_CTL(word_ETH_CTL); ++ ++ // Initialize "Receive Buffer Queue Pointer" ++ MHal_GMAC_Write_RBQP(GMAC_RBQP_BASE -GMAC_MIU0_BUS_BASE); ++ ++ // Initialize Receive Buffer Descriptors ++ memset((u8*)GMAC_RAM_VA_PA_OFFSET + GMAC_RBQP_BASE, 0x00UL, GMAC_RBQP_SIZE); // Clear for max(8*1024)bytes (max:1024 descriptors) ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, (GMAC_RBQP_BASE + GMAC_RBQP_SIZE - 0x10UL), 0x00000002UL); // (n-1) : Wrap = 1 ++#ifdef GMAC_INT_JULIAN_D ++ //Reg_rx_frame_cyc[15:8] -0xFF range 1~255 ++ //Reg_rx_frame_num[7:0] -0x05 receive frames per INT. ++ //0x80 Enable interrupt delay mode. ++ //register 0x104 receive counter need to modify smaller for ping ++ //Modify bigger(need small than 8) for throughput ++ uJulian104Value = GMAC_JULIAN_104_VAL;//0xFF050080; ++ MHal_GMAC_Write_JULIAN_0104(uJulian104Value); ++#else ++ // Enable Interrupts ---------------------------------------------------- ++ uJulian104Value = 0x00000000UL; ++ MHal_GMAC_Write_JULIAN_0104(uJulian104Value); ++#endif ++ // Set MAC address ------------------------------------------------------ ++ MHal_GMAC_Write_SA1_MAC_Address(GmacThisBCE.sa1[0], GmacThisBCE.sa1[1], GmacThisBCE.sa1[2], GmacThisBCE.sa1[3], GmacThisBCE.sa1[4], GmacThisBCE.sa1[5]); ++ MHal_GMAC_Write_SA2_MAC_Address(GmacThisBCE.sa2[0], GmacThisBCE.sa2[1], GmacThisBCE.sa2[2], GmacThisBCE.sa2[3], GmacThisBCE.sa2[4], GmacThisBCE.sa2[5]); ++ MHal_GMAC_Write_SA3_MAC_Address(GmacThisBCE.sa3[0], GmacThisBCE.sa3[1], GmacThisBCE.sa3[2], GmacThisBCE.sa3[3], GmacThisBCE.sa3[4], GmacThisBCE.sa3[5]); ++ MHal_GMAC_Write_SA4_MAC_Address(GmacThisBCE.sa4[0], GmacThisBCE.sa4[1], GmacThisBCE.sa4[2], GmacThisBCE.sa4[3], GmacThisBCE.sa4[4], GmacThisBCE.sa4[5]); ++ ++#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ #ifdef GMAC_RX_CHECKSUM ++ uJulian104Value=uJulian104Value | (GMAC_RX_CHECKSUM_ENABLE | GMAC_SOFTWARE_DESCRIPTOR_ENABLE); ++ #else ++ uJulian104Value=uJulian104Value | GMAC_SOFTWARE_DESCRIPTOR_ENABLE; ++ #endif ++ ++ MHal_GMAC_Write_JULIAN_0104(uJulian104Value); ++ ++ for(idxRBQP = 0; idxRBQP < GMAC_RBQP_LENG; idxRBQP++) ++ { ++ #ifdef GMAC_RX_ZERO_COPY ++ #if 1 ++ GMAC_dequeue_rx_buffer(LocPtr, &skb); ++ if (!skb) { ++#ifdef CONFIG_GMAC_RX_CMA ++ skb = __alloc_skb_from_cma(pci_cma_device, GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC, 0, -1); ++#else ++ skb = alloc_skb(GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC); ++#endif /* CONFIG_GMAC_RX_CMA */ ++ } ++ rx_skb[idxRBQP] = skb; ++ #else ++ rx_skb[idxRBQP] = alloc_skb(GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ #endif ++ // skb_reserve(rx_skb[idxRBQP], 2); ++ rx_abso_addr[idxRBQP] = rx_skb[idxRBQP]->data; ++ RBQP_offset = idxRBQP * 16; ++ if(idxRBQP < (GMAC_RBQP_LENG - 1)) ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[idxRBQP]) - GMAC_MIU0_BUS_BASE; ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ else ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[idxRBQP]) - GMAC_MIU0_BUS_BASE + GMAC_DESC_WRAP; ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ #else ++ RBQP_offset = idxRBQP * 16; ++ ++ if(idxRBQP < (GMAC_RBQP_LENG - 1)) ++ { ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, (GMAC_RX_BUFFER_BASE - GMAC_MIU0_BUS_BASE + GMAC_SOFTWARE_DESC_LEN * idxRBQP)); ++ } ++ else ++ { ++ MHal_GMAC_WritRam32(GMAC_RAM_VA_PA_OFFSET, GMAC_RBQP_BASE + RBQP_offset, (GMAC_RX_BUFFER_BASE - GMAC_MIU0_BUS_BASE + GMAC_SOFTWARE_DESC_LEN * idxRBQP + GMAC_DESC_WRAP)); ++ } ++ #endif /*GMAC_RX_ZERO_COPY*/ ++ } ++#endif //#ifdef GMAC_SOFTWARE_DESCRIPTOR ++ ++ if (!GmacThisUVE.initedGMAC) ++ { ++ MHal_GMAC_write_phy(gmac_phyaddr, MII_BMCR, 0x9000UL); ++ MHal_GMAC_write_phy(gmac_phyaddr, MII_BMCR, 0x1000UL); ++ // IMPORTANT: Run NegotiationPHY() before writing REG_ETH_CFG. ++ uNegPhyVal = MHal_GMAC_NegotiationPHY(); ++ if(uNegPhyVal == 0x01UL) ++ { ++ GmacThisUVE.flagMacTxPermit = 0x01UL; ++ GmacThisBCE.duplex = 1; ++ ++ } ++ else if(uNegPhyVal == 0x02UL) ++ { ++ GmacThisUVE.flagMacTxPermit = 0x01UL; ++ GmacThisBCE.duplex = 2; ++ } ++ ++ // ETH_CFG Register ----------------------------------------------------- ++ word_ETH_CFG = 0x00000800UL; // Init: CLK = 0x2 ++ // (20070808) IMPORTANT: REG_ETH_CFG:bit1(FD), 1:TX will halt running RX frame, 0:TX will not halt running RX frame. ++ // If always set FD=0, no CRC error will occur. But throughput maybe need re-evaluate. ++ // IMPORTANT: (20070809) NO_MANUAL_SET_DUPLEX : The real duplex is returned by "negotiation" ++ if(GmacThisBCE.speed == GMAC_SPEED_100) word_ETH_CFG |= 0x00000001UL; ++ if(GmacThisBCE.duplex == 2) word_ETH_CFG |= 0x00000002UL; ++ if(GmacThisBCE.cam == 1) word_ETH_CFG |= 0x00000200UL; ++ if(GmacThisBCE.rcv_bcast == 0) word_ETH_CFG |= 0x00000020UL; ++ if(GmacThisBCE.rlf == 1) word_ETH_CFG |= 0x00000100UL; ++ ++ MHal_GMAC_Write_CFG(word_ETH_CFG); ++ // ETH_CTL Register ----------------------------------------------------- ++ //word_ETH_CTL = 0x0000000CUL; // Enable transmit and receive : TE + RE = 0x0C (Disable MDIO) ++ if(GmacThisBCE.wes == 1) word_ETH_CTL |= 0x00000080UL; ++ MHal_GMAC_Write_CTL(word_ETH_CTL); ++#if 0 //FIXME latter ++ MHal_GMAC_Write_JULIAN_0100(GMAC_JULIAN_100_VAL); ++#else ++ MHal_GMAC_Write_JULIAN_0100(0x0000F001UL); ++#endif ++ ++ #ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ MHal_GMAC_Write_JULIAN_0100(0x0000F001UL); ++ #endif ++ ++ GmacThisUVE.flagPowerOn = 1; ++ GmacThisUVE.initedGMAC = 1; ++ } ++ ++#ifdef CONFIG_GMAC_NEW_TX_QUEUE ++ MHal_GMAC_New_TX_QUEUE_Enable(); ++ MHal_GMAC_New_TX_QUEUE_Threshold_Set(CONFIG_GMAC_NEW_TX_QUEUE_THRESHOLD); ++#endif /* CONFIG_GMAC_NEW_TX_QUEUE */ ++ ++ MHal_GMAC_HW_init(); ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC init Variable ++//------------------------------------------------------------------------------------------------- ++extern phys_addr_t memblock_start_of_DRAM(void); ++extern phys_addr_t memblock_size_of_first_region(void); ++ ++static phys_addr_t MDev_GMAC_VarInit(void) ++{ ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ phys_addr_t *alloRAM_VA_BASE; ++ ++ get_boot_mem_info(GMAC_MEM, &alloRAM_PA_BASE, &alloRAM_SIZE); ++#if defined (CONFIG_ARM64) ++ // get gmac addr only from mboot ++ //alloRAM_PA_BASE = memblock_start_of_DRAM() + memblock_size_of_first_region(); ++#endif ++ ++ alloRAM_VA_BASE = (phys_addr_t *)ioremap(alloRAM_PA_BASE, alloRAM_SIZE); //map buncing buffer from PA to VA ++ ++ GMAC_DBG("alloRAM_VA_BASE = 0x%zx alloRAM_PA_BASE= 0x%zx alloRAM_SIZE= 0x%zx\n", (size_t)alloRAM_VA_BASE, (size_t)alloRAM_PA_BASE, alloRAM_SIZE); ++ BUG_ON(!alloRAM_VA_BASE); ++#ifndef GMAC_RX_ZERO_COPY ++ //Add Write Protect ++ MHal_GMAC_Write_Protect(alloRAM_PA_BASE & 0x0fffffffUL, alloRAM_SIZE); ++#endif ++ memset((phys_addr_t *)alloRAM_VA_BASE,0x00UL,alloRAM_SIZE); ++ GMAC_RAM_VA_BASE = ((phys_addr_t)alloRAM_VA_BASE + sizeof(struct GMAC_private) + 0x3FFFUL) & ~0x3FFFUL; // IMPORTANT: Let lowest 14 bits as zero. ++ GMAC_RAM_PA_BASE = ((phys_addr_t)alloRAM_PA_BASE + sizeof(struct GMAC_private) + 0x3FFFUL) & ~0x3FFFUL; // IMPORTANT: Let lowest 14 bits as zero. ++ GMAC_RX_BUFFER_BASE = GMAC_RAM_PA_BASE + GMAC_RBQP_SIZE; ++ GMAC_RBQP_BASE = GMAC_RAM_PA_BASE; ++#ifdef GMAC_RX_ZERO_COPY ++ GMAC_TX_BUFFER_BASE = GMAC_RAM_PA_BASE + GMAC_RBQP_SIZE; ++#else ++ GMAC_TX_BUFFER_BASE = GMAC_RAM_PA_BASE + (GMAC_RX_BUFFER_SIZE + GMAC_RBQP_SIZE); ++#endif ++ GMAC_RAM_VA_PA_OFFSET = GMAC_RAM_VA_BASE - GMAC_RAM_PA_BASE; // IMPORTANT_TRICK_20070512 ++ GMAC_TX_SKB_BASE = GMAC_TX_BUFFER_BASE + GMAC_MAX_RX_DESCR * sizeof(struct gmac_rbf_t); ++ ++ memset(&GmacThisBCE,0x00UL,sizeof(BasicConfigGMAC)); ++ memset(&GmacThisUVE,0x00UL,sizeof(UtilityVarsGMAC)); ++ ++ GmacThisBCE.wes = 0; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ GmacThisBCE.duplex = 2; // 1:Half-duplex, 2:Full-duplex ++ GmacThisBCE.cam = 0; // 0:No CAM, 1:Yes ++ GmacThisBCE.rcv_bcast = 0; // 0:No, 1:Yes ++ GmacThisBCE.rlf = 0; // 0:No, 1:Yes receive long frame(1522) ++ GmacThisBCE.rcv_bcast = 1; ++ GmacThisBCE.speed = GMAC_SPEED_100; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_GMAC_get_SA1H_addr(); ++ LoAddr = MHal_GMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (GmacThisBCE.sa1, &addr, 6); ++ } ++ else ++ { ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_GMAC_get_SA2H_addr(); ++ LoAddr = MHal_GMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (GmacThisBCE.sa1, &addr, 6); ++ } ++ else ++ { ++ GmacThisBCE.sa1[0] = GMAC_MY_MAC[0]; ++ GmacThisBCE.sa1[1] = GMAC_MY_MAC[1]; ++ GmacThisBCE.sa1[2] = GMAC_MY_MAC[2]; ++ GmacThisBCE.sa1[3] = GMAC_MY_MAC[3]; ++ GmacThisBCE.sa1[4] = GMAC_MY_MAC[4]; ++ GmacThisBCE.sa1[5] = GMAC_MY_MAC[5]; ++ } ++ } ++ GmacThisBCE.connected = 0; ++ return (phys_addr_t)alloRAM_VA_BASE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Initialize the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++static const struct net_device_ops mstar_lan_netdev_ops = { ++ .ndo_open = MDev_GMAC_open, ++ .ndo_stop = MDev_GMAC_close, ++ .ndo_start_xmit = MDev_GMAC_tx, ++ .ndo_set_mac_address = MDev_GMAC_set_mac_address, ++ .ndo_set_rx_mode = MDev_GMAC_set_rx_mode, ++ .ndo_do_ioctl = MDev_GMAC_ioctl, ++ .ndo_get_stats = MDev_GMAC_stats, ++}; ++#endif ++#ifdef GMAC_TASKLET_SUPPORT ++static void MDrv_GMAC_TaskletBH(unsigned long data) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private *) data; ++ struct net_device *dev = LocPtr->dev; ++ ++ MDev_GMAC_rx(dev, GMAC_NAPI_WEIGHT); ++ ++} ++#endif ++ ++static int MDev_GMAC_setup (struct net_device *dev, unsigned long phy_type) ++{ ++ struct GMAC_private *LocPtr; ++ ++ static int already_initialized = 0; ++ dma_addr_t dmaaddr; ++ u32 val; ++ phys_addr_t RetAddr; ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ u32 retval; ++#endif ++#ifdef CONFIG_MSTAR_GMAC_JUMBO_PACKET ++ u32 retval; ++#endif ++ if (already_initialized) ++ return FALSE; ++ ++ LocPtr = (struct GMAC_private *) netdev_priv(dev); ++ ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++#ifdef CONFIG_GMAC_ISR_BH_TASKLET ++ tasklet_init(&LocPtr->rx_task, MDev_GMAC_bottom_rx_task, (unsigned long)LocPtr); ++ tasklet_init(&LocPtr->rst_task, MDev_GMAC_bottom_rst_task, (unsigned long)LocPtr); ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ tasklet_init(&LocPtr->tx_task, MDev_GMAC_bottom_tx_task, (unsigned long)LocPtr); ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++#endif /* CONFIG_GMAC_ISR_BH_TASKLET */ ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ++ LocPtr->dev = dev; ++ RetAddr = MDev_GMAC_VarInit(); ++ ++ if(!RetAddr) ++ { ++ GMAC_DBG("Var init fail!!\n"); ++ return FALSE; ++ } ++ ++ if (LocPtr == NULL) ++ { ++ free_irq (dev->irq, dev); ++ GMAC_DBG("LocPtr fail\n"); ++ return -ENOMEM; ++ } ++ ++ dev->base_addr = (long) GMAC_REG_ADDR_BASE; ++ MDev_GMAC_HW_init(); ++ dev->irq = E_IRQEXPH_SECEMAC; ++ ++ // Allocate memory for DMA Receive descriptors // ++ LocPtr->dlist_phys = LocPtr->dlist = (struct gmac_recv_desc_bufs *) (GMAC_RBQP_BASE + GMAC_RAM_VA_PA_OFFSET); ++ ++ if (LocPtr->dlist == NULL) ++ { ++ dma_free_noncoherent((void *)LocPtr, GMAC_ABSO_MEM_SIZE,&dmaaddr,0);//kfree (dev->priv); ++ free_irq (dev->irq, dev); ++ return -ENOMEM; ++ } ++ ++ LocPtr->lock = &gmac_lock; ++ LocPtr->txlock = &gmac_txlock; ++ spin_lock_init (LocPtr->lock); ++ spin_lock_init (LocPtr->txlock); ++#ifdef CONFIG_GMAC_ISR_BOTTOM_HALF ++ LocPtr->lock_rx = &gmac_lock_rx; ++ spin_lock_init(LocPtr->lock_rx); ++ LocPtr->lock_rst = &gmac_lock_rst; ++ spin_lock_init(LocPtr->lock_rst); ++#endif /* CONFIG_GMAC_ISR_BOTTOM_HALF */ ++ ether_setup (dev); ++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,28) ++ dev->open = MDev_GMAC_open; ++ dev->stop = MDev_GMAC_close; ++ dev->hard_start_xmit = MDev_GMAC_tx; ++ dev->get_stats = MDev_GMAC_stats; ++ dev->set_multicast_list = MDev_GMAC_set_rx_mode; ++ dev->do_ioctl = MDev_GMAC_ioctl; ++ dev->set_mac_address = MDev_GMAC_set_mac_address; ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ dev->netdev_ops = &mstar_lan_netdev_ops; ++#endif ++ dev->tx_queue_len = GMAC_MAX_TX_QUEUE; ++ ++ MDev_GMAC_get_mac_address (dev); // Get ethernet address and store it in dev->dev_addr // ++ MDev_GMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ spin_lock_irq (LocPtr->lock); ++ MHal_GMAC_enable_mdi (); ++ MHal_GMAC_read_phy (gmac_phyaddr, GMAC_MII_USCR_REG, &val); ++ if ((val & (1 << 10)) == 0) // DSCR bit 10 is 0 -- fiber mode // ++ LocPtr->phy_media = PORT_FIBRE; ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++ //Support for ethtool // ++ LocPtr->mii.dev = dev; ++ LocPtr->mii.mdio_read = MDev_GMAC_mdio_read; ++ LocPtr->mii.mdio_write = MDev_GMAC_mdio_write; ++ already_initialized = 1; ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_JULIAN_0104() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0104(retval); ++ dev->features |= NETIF_F_IP_CSUM; ++ ++ retval = MHal_GMAC_Read_JULIAN_0414() | GMAC_TX_V6_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0414(retval); ++ dev->features |= NETIF_F_IPV6_CSUM; ++#endif ++ ++#ifdef CONFIG_MSTAR_GMAC_JUMBO_PACKET ++ retval = MHal_GMAC_Read_JULIAN_0418() | GMAC_TX_CHECKSUM_ENABLE; ++ retval &= 0xffff0000UL; ++ retval |= GMAC_TX_JUMBO_FRAME_ENABLE; ++ MHal_GMAC_Write_JULIAN_0418(retval); ++#endif ++ ++#ifdef CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE ++ /* clear interrupt status, to avoid interrupt was set in uboot*/ ++ MHal_GMAC_Read_ISR(); ++ MHal_GMAC_Write_IDR(0xFFFF); ++ MHal_GMAC_Read_JULIAN_0108(); ++#endif /* CONFIG_GMAC_TX_ZERO_COPY_SW_QUEUE */ ++ ++ //Install the interrupt handler // ++ //Notes: Modify linux/kernel/irq/manage.c /* interrupt.h */ ++ if (request_irq(dev->irq, MDev_GMAC_interrupt, SA_INTERRUPT | IRQF_ONESHOT, dev->name, dev)) ++ return -EBUSY; ++#if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) && defined(CONFIG_MP_PLATFORM_INT_1_to_1_SPI) ++ irq_set_affinity_hint(dev->irq, cpu_online_mask); ++ irq_set_affinity(dev->irq, cpu_online_mask); ++#endif ++ ++#ifdef GMAC_TASKLET_SUPPORT ++ tasklet_init(&LocPtr->rx_tasklet, MDrv_GMAC_TaskletBH, (unsigned long)LocPtr); ++#endif ++ ++ //Determine current link speed // ++ spin_lock_irq (LocPtr->lock); ++ (void) MDev_GMAC_update_linkspeed (dev); ++ spin_unlock_irq (LocPtr->lock); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Restar the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_SwReset(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private *) netdev_priv(dev); ++ u32 oldCFG, oldCTL; ++ u32 retval; ++ ++ MDev_GMAC_get_mac_address (dev); ++ oldCFG = MHal_GMAC_Read_CFG(); ++ oldCTL = MHal_GMAC_Read_CTL() & ~(GMAC_TE | GMAC_RE); ++ ++ //free tx skb ++ if (LocPtr->retx_count) ++ { ++ if (LocPtr->skb) ++ { ++ dev_kfree_skb_irq(LocPtr->skb ); ++ LocPtr->skb = NULL; ++ } ++ if (netif_queue_stopped (dev)) ++ netif_wake_queue (dev); ++ } ++#ifdef GMAC_RX_ZERO_COPY ++ free_rx_skb(); ++#endif ++ ++ netif_stop_queue (dev); ++ ++ retval = MHal_GMAC_Read_JULIAN_0100(); ++ MHal_GMAC_Write_JULIAN_0100(retval & 0x00000FFFUL); ++ MHal_GMAC_Write_JULIAN_0100(retval); ++ ++ MDev_GMAC_HW_init(); ++ MHal_GMAC_Write_CFG(oldCFG); ++ MHal_GMAC_Write_CTL(oldCTL); ++ MHal_GMAC_enable_mdi (); ++ MDev_GMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ MDev_GMAC_update_linkspeed (dev); ++ MHal_GMAC_Write_IER(GMAC_IER_FOR_INT_JULIAN_D); ++ MDev_GMAC_start (dev); ++ MDev_GMAC_set_rx_mode(dev); ++ netif_start_queue (dev); ++ LocPtr->retx_count = 0; ++ ROVRcount = 0; ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_JULIAN_0104() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0104(retval); ++ dev->features |= NETIF_F_IP_CSUM; ++#endif ++ //GMAC_DBG("=> Take %lu ms to reset GMAC!\n", (getCurMs() - gmac_oldTime)); ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstargmac_of_device_ids[] = { ++ {.compatible = "mstar-gmac"}, ++ {}, ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Detect MAC and PHY and perform initialization ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_probe (struct net_device *dev) ++{ ++ int detected = -1; ++ ++ /* Read the PHY ID registers - try all addresses */ ++ detected = MDev_GMAC_setup(dev, GMAC_MII_URANUS_ID); ++ return detected; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_timer_callback(unsigned long value) ++{ ++ int ret = 0; ++ struct GMAC_private *LocPtr = (struct GMAC_private *) netdev_priv(gmac_dev); ++ static u32 bmsr, time_count = 0; ++#ifndef GMAC_INT_JULIAN_D ++ if (GMAC_RX_TMR == value) ++ { ++ MHal_GMAC_timer_callback(value); ++ return; ++ } ++#endif ++ spin_lock_irq (LocPtr->lock); ++ ret = MDev_GMAC_update_linkspeed(gmac_dev); ++ spin_unlock_irq (LocPtr->lock); ++ if (0 == ret) ++ { ++ if (!GmacThisBCE.connected) ++ { ++ GmacThisBCE.connected = 1; ++ netif_carrier_on(gmac_dev); ++ } ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ time_count = 0; ++ spin_lock_irq (LocPtr->lock); ++ gmac_phy_status_register = bmsr; ++ spin_unlock_irq (LocPtr->lock); ++ // Normally, time out sets 1 Sec. ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ } ++ else //no link ++ { ++ if(GmacThisBCE.connected) { ++ GmacThisBCE.connected = 0; ++ } ++ // If disconnected is over 3 Sec, the real value of PHY's status register will report to application. ++ if(time_count > 30) { ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (gmac_phyaddr, MII_BMSR, &bmsr); ++ spin_lock_irq (LocPtr->lock); ++ gmac_phy_status_register = bmsr; ++ spin_unlock_irq (LocPtr->lock); ++ // Report to kernel. ++ netif_carrier_off(gmac_dev); ++ GmacThisBCE.connected = 0; ++ // Normally, time out is set 1 Sec. ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ } ++ else if(time_count <= 30){ ++ time_count++; ++ // Time out is set 100ms. Quickly checks next phy status. ++ GMAC_Link_timer.expires = jiffies + (GMAC_CHECK_LINK_TIME / 10); ++ } ++ } ++ GMAC_Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ ++ if (GmacThisBCE.connected) ++ { ++ MDev_GMAC_Check_TXRX(1); ++ } ++ add_timer(&GMAC_Link_timer); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC MACADDR Setup ++//------------------------------------------------------------------------------------------------- ++ ++#define MACADDR_FORMAT "XX:XX:XX:XX:XX:XX" ++ ++static int __init macaddr_auto_config_setup(char *addrs) ++{ ++ if (strlen(addrs) == strlen(MACADDR_FORMAT) ++ && ':' == addrs[2] ++ && ':' == addrs[5] ++ && ':' == addrs[8] ++ && ':' == addrs[11] ++ && ':' == addrs[14] ++ ) ++ { ++ addrs[2] = '\0'; ++ addrs[5] = '\0'; ++ addrs[8] = '\0'; ++ addrs[11] = '\0'; ++ addrs[14] = '\0'; ++ ++ GMAC_MY_MAC[0] = (u8)simple_strtoul(&(addrs[0]), NULL, 16); ++ GMAC_MY_MAC[1] = (u8)simple_strtoul(&(addrs[3]), NULL, 16); ++ GMAC_MY_MAC[2] = (u8)simple_strtoul(&(addrs[6]), NULL, 16); ++ GMAC_MY_MAC[3] = (u8)simple_strtoul(&(addrs[9]), NULL, 16); ++ GMAC_MY_MAC[4] = (u8)simple_strtoul(&(addrs[12]), NULL, 16); ++ GMAC_MY_MAC[5] = (u8)simple_strtoul(&(addrs[15]), NULL, 16); ++ ++ /* set back to ':' or the environment variable would be destoried */ // REVIEW: this coding style is dangerous ++ addrs[2] = ':'; ++ addrs[5] = ':'; ++ addrs[8] = ':'; ++ addrs[11] = ':'; ++ addrs[14] = ':'; ++ } ++ ++ return 1; ++} ++ ++__setup("macaddr=", macaddr_auto_config_setup); ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC init module ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ScanPhyAddr(void) ++{ ++ unsigned char addr = 1; // because address 0 = broadcast, RTL8211E will reply to broadcast addr ++ u32 value = 0; ++ ++#ifdef CONFIG_GMAC_ETHERNET_ALBANY ++ MHal_GMAC_Write_JULIAN_0100(0x0000F001UL); ++#else ++ MHal_GMAC_Write_JULIAN_0100(0x0000F007UL); ++#endif ++ ++ MHal_GMAC_enable_mdi(); ++ do ++ { ++ value = 0; ++ MHal_GMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ GMAC_DBG("[ PHY Addr ] ==> :%u BMSR = %08x\n", addr, value); ++ break; ++ } ++ }while(++addr && addr < 32); ++ ++ gmac_phyaddr = addr; ++ ++ if (gmac_phyaddr >= 32) ++ { ++ addr = 0; ++ MHal_GMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ GMAC_DBG("[ PHY Addr ] ==> :%u BMSR = %08x\n", addr, value); ++ gmac_phyaddr = 0; ++ } ++ else ++ { ++ GMAC_DBG("Wrong PHY Addr, maybe MoCA?\n"); ++ gmac_phyaddr = 32; ++ } ++ } ++ ++ MHal_GMAC_disable_mdi(); ++ return 0; ++} ++ ++static void Rtl_Patch(void) ++{ ++ u32 val; ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, 25, &val); ++ MHal_GMAC_write_phy(gmac_phyaddr, 25, 0x400UL); ++ MHal_GMAC_read_phy(gmac_phyaddr, 25, &val); ++} ++ ++static void MDev_GMAC_Patch_PHY(void) ++{ ++ u32 val; ++ ++ MHal_GMAC_read_phy(gmac_phyaddr, 2, &val); ++ if (GMAC_RTL_8210 == val) ++ Rtl_Patch(); ++} ++ ++#ifdef GMAC_RX_ZERO_COPY ++static int GMAC_dequeue_rx_buffer(struct GMAC_private *p, struct sk_buff **pskb) ++{ ++ p->rx_next = (p->rx_next + 1) % GMAC_RX_RING_SIZE; ++ p->rx_current_fill--; ++ *pskb = __skb_dequeue(&p->rx_list); ++ ++ if (gmac_debug) ++ GMAC_DBG("rx_next:%d rx_next_fill:%d rx_current_fill:%d\n",p->rx_next, p->rx_next_fill, p->rx_current_fill); ++ return p->rx_current_fill; ++} ++ ++static int GMAC_rx_fill_ring(struct net_device *netdev) ++{ ++ struct GMAC_private *p = netdev_priv(netdev); ++ ++ while (p->rx_current_fill < GMAC_RX_RING_SIZE) ++ { ++ struct sk_buff *skb; ++#ifdef CONFIG_GMAC_RX_CMA ++ if (!(skb = __alloc_skb_from_cma(pci_cma_device, GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC, 0, -1))) { ++#else ++ if (!(skb = alloc_skb (GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC))) { ++#endif /* CONFIG_GMAC_RX_CMA */ ++ GMAC_DBG("%s %d: alloc skb failed! RX current fill:%d\n",__func__,__LINE__, p->rx_current_fill); ++ break; ++ } ++ ++// skb_reserve(skb, NET_IP_ALIGN); ++ __skb_queue_tail(&p->rx_list, skb); ++ p->rx_current_fill++; ++ p->rx_next_fill = (p->rx_next_fill + 1) % GMAC_RX_RING_SIZE; ++ } ++ ++ if (unlikely(gmac_debug)) ++ GMAC_DBG("%s Current fill:%d. rx next fill:%d\n",__func__, p->rx_current_fill, p->rx_next_fill); ++ return p->rx_current_fill; ++} ++#endif /*GMAC_RX_ZERO_COPY*/ ++ ++static int MDev_GMAC_init(void) ++{ ++ struct GMAC_private *LocPtr; ++#ifdef NR_NAPI ++ int i; ++#endif ++ ++ if(gmac_dev) ++ return -1; ++ ++ gmac_dev = alloc_etherdev(sizeof(*LocPtr)); ++ LocPtr = netdev_priv(gmac_dev); ++ if (!gmac_dev) ++ { ++ GMAC_DBG( KERN_ERR "No GMAC dev mem!\n" ); ++ return -ENOMEM; ++ } ++#ifdef GMAC_RX_ZERO_COPY ++ skb_queue_head_init(&LocPtr->tx_list); ++ skb_queue_head_init(&LocPtr->rx_list); ++ LocPtr->rx_next = 0; ++ LocPtr->rx_next_fill = 0; ++ LocPtr->rx_current_fill = 0; ++ ++ GMAC_rx_fill_ring(gmac_dev); ++#endif ++ ++#if GMAC_TX_THROUGHPUT_TEST ++ printk("==========TX_THROUGHPUT_TEST==============="); ++ gmac_pseudo_packet = alloc_skb(GMAC_SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ memcpy(gmac_pseudo_packet->data, (void *)gmac_packet_content, sizeof(gmac_packet_content)); ++ gmac_pseudo_packet->len = sizeof(gmac_packet_content); ++ init_timer(&GMAC_TX_timer); ++ GMAC_TX_timer.data = GMAC_RX_TMR; ++ GMAC_TX_timer.function = TX_timer_callback; ++ GMAC_TX_timer.expires = jiffies + 10*GMAC_CHECK_LINK_TIME; ++ add_timer(&GMAC_TX_timer); ++#endif ++ ++#if GMAC_RX_THROUGHPUT_TEST ++ printk("==========RX_THROUGHPUT_TEST==============="); ++ init_timer(&GMAC_RX_timer); ++ ++ GMAC_RX_timer.data = GMAC_RX_TMR; ++ GMAC_RX_timer.function = RX_timer_callback; ++ GMAC_RX_timer.expires = jiffies + (RX_THROUGHPUT_TEST_INTERVAL*GMAC_CHECK_LINK_TIME); ++ add_timer(&GMAC_RX_timer); ++#endif ++#ifdef GMAC_NAPI ++#ifdef NR_NAPI ++ spin_lock_init(&cpu_state.lock); ++ for_each_possible_cpu(i) { ++ netif_napi_add(gmac_dev, &gmac_napi[i].napi_str, MDev_GMAC_napi_poll, rx_napi_weight[i]); ++ gmac_napi[i].available = 1; ++ gmac_napi[i].cpu = i; ++ napi_enable(&gmac_napi[i].napi_str); ++ } ++ cpu_state.baseline_cores = num_online_cpus(); ++ cpu_state.active_cores = 0; ++#else ++ netif_napi_add(gmac_dev, &LocPtr->napi_str, MDev_GMAC_napi_poll, GMAC_NAPI_WEIGHT); ++ napi_enable(&LocPtr->napi_str); ++#endif ++#endif ++ ++#ifdef CONFIG_GMAC_ISR_BH_NAPI ++ netif_napi_add(gmac_dev, &LocPtr->napi, MDev_GMAC_napi_poll, CONFIG_GMAC_NAPI_WEIGHT); ++#endif /* CONFIG_GMAC_ISR_BH_NAPI */ ++ ++ MHal_GMAC_Power_On_Clk(); ++ ++ init_timer(&GMAC_timer); ++ init_timer(&GMAC_Link_timer); ++ ++ GMAC_timer.data = GMAC_RX_TMR; ++ GMAC_timer.function = MDev_GMAC_timer_callback; ++ GMAC_timer.expires = jiffies; ++ ++ ++ MHal_GMAC_Write_JULIAN_0100(GMAC_JULIAN_100_VAL); ++ ++ if (0 > MDev_GMAC_ScanPhyAddr()) ++ goto end; ++ ++ MDev_GMAC_Patch_PHY(); ++ if (!MDev_GMAC_probe (gmac_dev)) ++ return register_netdev (gmac_dev); ++ ++end: ++ free_netdev(gmac_dev); ++ gmac_dev = 0; ++ gmac_initstate = GMAC_ETHERNET_TEST_INIT_FAIL; ++ GMAC_DBG( KERN_ERR "Init GMAC error!\n" ); ++ return -1; ++} ++//------------------------------------------------------------------------------------------------- ++// GMAC exit module ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_exit(void) ++{ ++ if (gmac_dev) ++ { ++ #ifndef GMAC_INT_JULIAN_D ++ del_timer(&GMAC_timer); ++ #endif ++ unregister_netdev(gmac_dev); ++ free_netdev(gmac_dev); ++ } ++} ++ ++static int mstar_gmac_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct GMAC_private *LocPtr; ++ u32 uRegVal; ++ printk(KERN_INFO "mstar_gmac_drv_suspend\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev); ++ ++ LocPtr->ep_flag |= GMAC_EP_FLAG_SUSPENDING; ++ netif_stop_queue (netdev); ++ ++ disable_irq(netdev->irq); ++ del_timer(&GMAC_Link_timer); ++ ++ MHal_GMAC_Power_On_Clk(); ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ ++ // Disable PHY interrupt // ++ MHal_GMAC_disable_phyirq (); ++ ++ //Disable MAC interrupts // ++ MDev_GMAC_irq_onoff(0, __func__); ++ MHal_GMAC_Power_Off_Clk(); ++ MDev_GMAC_close(netdev); ++ return 0; ++} ++static int mstar_gmac_drv_resume(struct platform_device *dev) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct GMAC_private *LocPtr; ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ u32 retval; ++ printk(KERN_INFO "mstar_gmac_drv_resume\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev);; ++ LocPtr->ep_flag &= ~GMAC_EP_FLAG_SUSPENDING; ++ ++ MHal_GMAC_Power_On_Clk(); ++ ++ MHal_GMAC_Write_JULIAN_0100(GMAC_JULIAN_100_VAL); ++ ++ if (0 > MDev_GMAC_ScanPhyAddr()) ++ return -1; ++ ++ MDev_GMAC_Patch_PHY(); ++ ++ get_boot_mem_info(EMAC_MEM, &alloRAM_PA_BASE, &alloRAM_SIZE); ++#if defined(CONFIG_ARM64) ++ alloRAM_PA_BASE = memblock_start_of_DRAM() + memblock_size_of_first_region(); ++#endif ++#ifndef GMAC_RX_ZERO_COPY ++ //Add Write Protect ++ //MHal_GMAC_Write_Protect(alloRAM_PA_BASE, alloRAM_SIZE); ++#endif ++ ++ GmacThisUVE.initedGMAC = 0; ++ MDev_GMAC_HW_init(); ++ ++ MDev_GMAC_update_mac_address (netdev); // Program ethernet address into MAC // ++ spin_lock_irq (LocPtr->lock); ++ MHal_GMAC_enable_mdi (); ++ MHal_GMAC_read_phy (gmac_phyaddr, GMAC_MII_USCR_REG, &retval); ++ if ((retval & (1 << 10)) == 0) // DSCR bit 10 is 0 -- fiber mode // ++ LocPtr->phy_media = PORT_FIBRE; ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++#ifdef CONFIG_MSTAR_GMAC_HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_JULIAN_0104() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_JULIAN_0104(retval); ++#endif ++ ++ enable_irq(netdev->irq); ++ if(0>MDev_GMAC_open(netdev)) ++ { ++ printk(KERN_WARNING "Driver GMAC: open failed after resume\n"); ++ } ++ return 0; ++} ++ ++static int mstar_gmac_drv_probe(struct platform_device *pdev) ++{ ++ int retval=0; ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-gmac") ++ || pdev->id!=0) ++ { ++ retval = -ENXIO; ++ } ++#ifdef CONFIG_GMAC_NAPI_GRO ++ GMAC_DBG("Start GMAC V2 GRO\n"); ++#else ++ GMAC_DBG("Start GMAC V2\n"); ++#endif ++ ++ retval = MDev_GMAC_init(); ++ if(!retval) ++ { ++ pdev->dev.platform_data=gmac_dev; ++ } ++ return retval; ++} ++ ++static int mstar_gmac_drv_remove(struct platform_device *pdev) ++{ ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-gmac") ++ || pdev->id!=0) ++ { ++ return -1; ++ } ++ MDev_GMAC_exit(); ++ pdev->dev.platform_data=NULL; ++ return 0; ++} ++ ++ ++ ++static struct platform_driver Mstar_gmac_driver = { ++ .probe = mstar_gmac_drv_probe, ++ .remove = mstar_gmac_drv_remove, ++ .suspend = mstar_gmac_drv_suspend, ++ .resume = mstar_gmac_drv_resume, ++ ++ .driver = { ++ .name = "Mstar-gmac", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstargmac_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_gmac_drv_init_module(void) ++{ ++ int retval=0; ++ ++ gmac_dev=NULL; ++ retval = platform_driver_register(&Mstar_gmac_driver); ++ return retval; ++} ++ ++static void __exit mstar_gmac_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_gmac_driver); ++ gmac_dev=NULL; ++} ++ ++module_param(gmac_tx_debug, uint, 0644); ++MODULE_PARM_DESC(gmac_tx_debug, "Debug info for GMAC TX"); ++module_param(gmac_debug, uint, 0644); ++MODULE_PARM_DESC(gmac_debug, "Debug info for GMAC"); ++module_param(gmac_debug_napi, uint, 0644); ++MODULE_PARM_DESC(gmac_debug_napi, "Debug info for GMAC"); ++module_param(gmac_dump_skb, uint, 0644); ++MODULE_PARM_DESC(gmac_dump_skb, "Dump SKB for GMAC"); ++#if GMAC_TX_THROUGHPUT_TEST ++module_param(gmac_tx_test, uint, 0644); ++MODULE_PARM_DESC(gmac_tx_test, "TX test for GMAC"); ++module_param(gmac_tx_thread, uint, 0644); ++MODULE_PARM_DESC(gmac_tx_thread, "TX thread sender for GMAC"); ++#endif ++#if GMAC_RX_THROUGHPUT_TEST ++#endif ++ ++module_init(mstar_gmac_drv_init_module); ++module_exit(mstar_gmac_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GMAC Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/gmac/mdrv_gmac_v3.c b/drivers/sstar/gmac/mdrv_gmac_v3.c +new file mode 100755 +index 000000000000..9bd1f0af0534 +--- /dev/null ++++ b/drivers/sstar/gmac/mdrv_gmac_v3.c +@@ -0,0 +1,3671 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file devGMAC.c ++/// @brief GMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_OF ++#include ++#endif ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++//#include ++#include ++#elif defined(CONFIG_ARM64) ++#include ++#include ++#endif ++#include "mdrv_types.h" ++//#include "mst_platform.h" ++//#include "mdrv_system.h" ++//#include "chip_int.h" ++#include "mhal_gmac_v3.h" ++#include "mdrv_gmac_v3.h" ++//#include "chip_setup.h" ++ ++#ifdef CONFIG_GMAC_SUPPLY_RNG ++#include ++#include ++#include "mhal_rng_reg.h" ++#endif ++ ++#include "ms_msys.h" ++#include "ms_platform.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct net_device *gmac_dev; ++struct device *gdebug_class_gmac_dev; ++static int gb_tx_packet_dump_en=0; ++static int gb_rx_packet_dump_en=0; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Function ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev); ++static void MDev_GMAC_timer_callback( unsigned long value ); ++static int MDev_GMAC_SwReset(struct net_device *dev); ++//static void MDev_GMAC_Send_PausePkt(struct net_device* dev); ++ ++#ifdef RX_ZERO_COPY ++static void MDev_GMAC_RX_DESC_Init_zero_copy(struct net_device *dev); ++static void MDev_GMAC_RX_DESC_close_zero_copy(struct net_device *dev); ++#else ++static void MDev_GMAC_RX_DESC_Init_memcpy(struct net_device *dev); ++static void MDev_GMAC_RX_DESC_Reset_memcpy(struct net_device *dev); ++#endif ++ ++static void MDEV_GMAC_ENABLE_RX_REG(void); ++static void MDEV_GMAC_DISABLE_RX_REG(void); ++#ifdef RX_NAPI ++static int MDev_GMAC_RX_napi_poll(struct napi_struct *napi, int budget); ++#endif ++ ++#ifndef NEW_TX_QUEUE ++static int MDev_GMAC_CheckTSR(void); ++#endif ++ ++#ifdef TX_NAPI ++static void MDEV_GMAC_ENABLE_TX_REG(void); ++static void MDEV_GMAC_DISABLE_TX_REG(void); ++static int MDev_GMAC_TX_napi_poll(struct napi_struct *napi, int budget); ++#endif ++ ++#ifdef TX_DESC_MODE ++static void MDev_GMAC_TX_Desc_Reset(struct net_device *dev); ++static void MDev_GMAC_TX_Desc_Mode_Set(struct net_device *dev); ++#endif ++ ++#ifdef TX_SOFTWARE_QUEUE ++static void _MDev_GMAC_tx_reset_TX_SW_QUEUE(struct net_device* netdev); ++#endif ++//------------------------------------------------------------------------------------------------- ++// PHY MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Access the PHY to determine the current Link speed and Mode, and update the ++// MAC accordingly. ++// If no link or auto-negotiation is busy, then no changes are made. ++// Returns: 0 : OK ++// -1 : No link ++// -2 : AutoNegotiation still in progress ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_update_linkspeed (struct net_device *dev) ++{ ++#ifdef CONFIG_GMAC_DETECT_FROM_PHY ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 bmsr, bmcr, lpa; ++ u32 stat1000; ++ u32 speed, duplex; ++ ++ if (LocPtr->phyaddr >= 32) return 0; ++ /* Link status is latched, so read twice to get current value */ ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ ++ /* No link */ ++ if (!(bmsr & BMSR_LSTATUS)){ ++ #ifdef GMAC_LINK_LED_CONTROL ++ MHal_GMAC_link_led_off(); ++ #endif ++ return -1; ++ } ++#ifdef GMAC_LINK_LED_CONTROL ++ MHal_GMAC_link_led_on(); ++#endif ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMCR, &bmcr); ++ ++ /* AutoNegotiation is enabled */ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ GMAC_DBG("==> AutoNegotiation still in progress\n"); ++ return -2; ++ } ++ ++ ++ if(LocPtr->hardware_type == GMAC_GPHY) ++ { ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_STAT1000, &stat1000); ++ ++ if(stat1000 & LPA_1000FULL) ++ { ++ speed = SPEED_1000; ++ duplex = DUPLEX_FULL; ++ } ++ else if(stat1000 & LPA_1000HALF) ++ { ++ speed = SPEED_1000; ++ duplex = DUPLEX_HALF; ++ } ++ else ++ { ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_LPA, &lpa); ++ if(lpa & LPA_100FULL) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if (lpa & LPA_100HALF) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if (lpa & LPA_10FULL) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++ } ++ } ++ else ++ { ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_LPA, &lpa); ++ if(lpa & LPA_100FULL) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if (lpa & LPA_100HALF) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if (lpa & LPA_10FULL) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++ } ++ } ++ else ++ { ++ speed = (bmcr & BMCR_SPEED1000) ? SPEED_1000 : ((bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); ++ duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ // Update the MAC // ++ MHal_GMAC_update_speed_duplex(speed,duplex); ++#else //defined(CONFIG_GMAC_FORCE_MAC_SPEED_100) ++ MHal_GMAC_update_speed_duplex(SPEED_100, DUPLEX_FULL); ++#endif ++ return 0; ++} ++ ++static int MDev_GMAC_get_info(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 bmsr, bmcr, LocPtrA; ++ u32 uRegStatus =0; ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_NO_LINK; //no link // ++ } ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_AUTO_NEGOTIATION; //AutoNegotiation // ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= GMAC_ETHERNET_TEST_LINK_SUCCESS; //link success // ++ } ++ ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ else ++ { ++ if(bmcr & BMCR_SPEED100) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if(bmcr & BMCR_FULLDPLX) ++ { ++ uRegStatus |= GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~GMAC_ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ ++ return uRegStatus; ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Program the hardware MAC address from dev->dev_addr. ++//------------------------------------------------------------------------------------------------- ++void MDev_GMAC_update_mac_address (struct net_device *dev) ++{ ++ u32 value; ++ value = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) |(dev->dev_addr[0]); ++ MHal_GMAC_Write_SA1L(value); ++ value = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]); ++ MHal_GMAC_Write_SA1H(value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// ADDRESS MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Set the ethernet MAC address in dev->dev_addr ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_get_mac_address (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_GMAC_get_SA1H_addr(); ++ LoAddr = MHal_GMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ GMAC_DBG("SA1_Valid!!!\n"); ++ memcpy (LocPtr->ThisBCE.sa1, &addr, 6); ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_GMAC_get_SA2H_addr(); ++ LoAddr = MHal_GMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ GMAC_DBG("SA2_Valid!!!\n"); ++ memcpy (LocPtr->ThisBCE.sa1, &addr, 6); ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ else ++ { ++ GMAC_DBG("ALL Not Valid!!!, set default MAC addrees\n"); ++ LocPtr->ThisBCE.sa1[0] = GMAC_MY_MAC[0]; ++ LocPtr->ThisBCE.sa1[1] = GMAC_MY_MAC[1]; ++ LocPtr->ThisBCE.sa1[2] = GMAC_MY_MAC[2]; ++ LocPtr->ThisBCE.sa1[3] = GMAC_MY_MAC[3]; ++ LocPtr->ThisBCE.sa1[4] = GMAC_MY_MAC[4]; ++ LocPtr->ThisBCE.sa1[5] = GMAC_MY_MAC[5]; ++ memcpy (dev->dev_addr, LocPtr->ThisBCE.sa1, 6); ++ } ++} ++ ++#ifdef GMAC_URANUS_ETHER_ADDR_CONFIGURABLE ++//------------------------------------------------------------------------------------------------- ++// Store the new hardware address in dev->dev_addr, and update the MAC. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_set_mac_address (struct net_device *dev, void *addr) ++{ ++ struct sockaddr *address = addr; ++ if (!is_valid_ether_addr (address->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy (dev->dev_addr, address->sa_data, dev->addr_len); ++ MDev_GMAC_update_mac_address (dev); ++ return 0; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Mstar Multicast hash rule ++//------------------------------------------------------------------------------------------------- ++//Hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] ++//Hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] ++//Hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] ++//Hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] ++//Hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] ++//Hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] ++//------------------------------------------------------------------------------------------------- ++/* ++static void MDev_GMAC_sethashtable(unsigned char *addr) ++{ ++ u32 mc_filter[2]; ++ u32 uHashIdxBit; ++ u32 uHashValue; ++ u32 i; ++ u32 tmpcrc; ++ u32 uSubIdx; ++ u64 macaddr; ++ u64 mac[6]; ++ ++ uHashValue = 0; ++ macaddr = 0; ++ ++ // Restore mac // ++ for(i = 0; i < 6; i++) ++ { ++ mac[i] =(u64)addr[i]; ++ } ++ ++ // Truncate mac to u64 container // ++ macaddr |= mac[0] | (mac[1] << 8) | (mac[2] << 16); ++ macaddr |= (mac[3] << 24) | (mac[4] << 32) | (mac[5] << 40); ++ ++ // Caculate the hash value // ++ for(uHashIdxBit = 0; uHashIdxBit < 6; uHashIdxBit++) ++ { ++ tmpcrc = (macaddr & (0x1UL << uHashIdxBit)) >> uHashIdxBit; ++ for(i = 1; i < 8; i++) ++ { ++ uSubIdx = uHashIdxBit + (i * 6); ++ tmpcrc = tmpcrc ^ ((macaddr >> uSubIdx) & 0x1); ++ } ++ uHashValue |= (tmpcrc << uHashIdxBit); ++ } ++ ++ mc_filter[0] = MHal_GMAC_ReadReg32( GMAC_REG_ETH_HSL); ++ mc_filter[1] = MHal_GMAC_ReadReg32( GMAC_REG_ETH_HSH); ++ ++ // Set the corrsponding bit according to the hash value // ++ if(uHashValue < 32) ++ { ++ mc_filter[0] |= (0x1UL << uHashValue); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSL, mc_filter[0] ); ++ } ++ else ++ { ++ mc_filter[1] |= (0x1UL << (uHashValue - 32)); ++ MHal_GMAC_WritReg32( GMAC_REG_ETH_HSH, mc_filter[1] ); ++ } ++}*/ ++//------------------------------------------------------------------------------------------------- ++//Enable/Disable promiscuous and multicast modes. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_set_rx_mode (struct net_device *dev) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_GMAC_Read_CFG(); ++ ++ if (dev->flags & IFF_PROMISC) ++ { // Enable promiscuous mode // ++ uRegVal |= GMAC_CAF; ++ } ++ else if (dev->flags & (~IFF_PROMISC)) ++ { // Disable promiscuous mode // ++ uRegVal &= ~GMAC_CAF; ++ } ++ MHal_GMAC_Write_CFG(uRegVal); ++ ++ if (dev->flags & IFF_ALLMULTI) ++ { // Enable all multicast mode // ++ MHal_GMAC_update_HSH(-1,-1); ++ uRegVal |= GMAC_MTI; ++ } ++ else if (dev->flags & IFF_MULTICAST) ++ { // Enable specific multicasts// ++ //MDev_GMAC_sethashtable (dev); ++ MHal_GMAC_update_HSH(-1,-1); ++ uRegVal |= GMAC_MTI; ++ } ++ else if (dev->flags & ~(IFF_ALLMULTI | IFF_MULTICAST)) ++ { // Disable all multicast mode// ++ MHal_GMAC_update_HSH(0,0); ++ uRegVal &= ~GMAC_MTI; ++ } ++ ++ MHal_GMAC_Write_CFG(uRegVal); ++} ++//------------------------------------------------------------------------------------------------- ++// IOCTL ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable MDIO ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_mdio_read (struct net_device *dev, int phy_id, int location) ++{ ++ u32 value; ++ MHal_GMAC_read_phy (phy_id, location, &value); ++ return value; ++} ++ ++static void MDev_GMAC_mdio_write (struct net_device *dev, int phy_id, int location, int value) ++{ ++ MHal_GMAC_write_phy (phy_id, location, value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//ethtool support. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ethtool_ioctl (struct net_device *dev, void *useraddr) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 ethcmd; ++ int res = 0; ++ ++ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ spin_lock_irq (&LocPtr->irq_lock); ++ ++ switch (ethcmd) ++ { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ res = mii_ethtool_gset (&LocPtr->mii, &ecmd); ++ if (copy_to_user (useraddr, &ecmd, sizeof (ecmd))) ++ res = -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd ecmd; ++ if (copy_from_user (&ecmd, useraddr, sizeof (ecmd))) ++ res = -EFAULT; ++ else ++ res = mii_ethtool_sset (&LocPtr->mii, &ecmd); ++ break; ++ } ++ case ETHTOOL_NWAY_RST: ++ { ++ res = mii_nway_restart (&LocPtr->mii); ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ edata.data = mii_link_ok (&LocPtr->mii); ++ if (copy_to_user (useraddr, &edata, sizeof (edata))) ++ res = -EFAULT; ++ break; ++ } ++ default: ++ res = -EOPNOTSUPP; ++ } ++ spin_unlock_irq (&LocPtr->irq_lock); ++ return res; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// User-space ioctl interface. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct mii_ioctl_data *data = if_mii(rq); ++ ++ if (!netif_running(dev)) ++ { ++ rq->ifr_metric = GMAC_ETHERNET_TEST_INIT_FAIL; ++ } ++ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ data->phy_id = (LocPtr->phyaddr & 0x1F); ++ return 0; ++ ++ case SIOCDEVPRIVATE: ++ rq->ifr_metric = (MDev_GMAC_get_info(gmac_dev)|LocPtr->initstate); ++ return 0; ++ ++// case SIOCDEVON: ++// MHal_GMAC_Power_On_Clk(); ++// return 0; ++// ++// case SIOCDEVOFF: ++// MHal_GMAC_Power_Off_Clk(); ++// return 0; ++ ++ case SIOCGMIIREG: ++ // check PHY's register 1. ++ if((data->reg_num & 0x1fUL) == 0x1) ++ { ++ // PHY's register 1 value is set by timer callback function. ++ spin_lock_irq(&LocPtr->irq_lock); ++ data->val_out = LocPtr->phy_status_register; ++ spin_unlock_irq(&LocPtr->irq_lock); ++ } ++ else ++ { ++ MHal_GMAC_read_phy((LocPtr->phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), (u32 *)&(data->val_out)); ++ } ++ return 0; ++ ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ MHal_GMAC_write_phy((LocPtr->phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), data->val_in); ++ return 0; ++ ++ case SIOCETHTOOL: ++ return MDev_GMAC_ethtool_ioctl (dev, (void *) rq->ifr_data); ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// MAC ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and start the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_start (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr; ++ u32 uRegVal; ++ ++#ifdef RX_ZERO_COPY ++ MDev_GMAC_RX_DESC_Init_zero_copy(dev); ++#else ++ MDev_GMAC_RX_DESC_Reset_memcpy(dev); ++#endif ++ ++#ifdef TX_DESC_MODE ++ MDev_GMAC_TX_Desc_Reset(dev); ++ MDev_GMAC_TX_Desc_Mode_Set(dev); ++#else ++#ifdef TX_SOFTWARE_QUEUE ++ _MDev_GMAC_tx_reset_TX_SW_QUEUE(dev); ++#else ++ LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ LocPtr->tx_index = 0; ++#endif ++#endif ++ ++ ++ ++ // Enable Receive and Transmit // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= (GMAC_RE | GMAC_TE); ++ MHal_GMAC_Write_CTL(uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Open the ethernet interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_open (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 uRegVal; ++ int ret; ++ ++#ifdef RX_NAPI ++ if(LocPtr->napi_rx.state == NAPI_STATE_SCHED) ++ { ++ napi_disable(&LocPtr->napi_rx); ++ //GMAC_DBG("napi_disable RX!!!\n"); ++ } ++ ++ napi_enable(&LocPtr->napi_rx); ++ //GMAC_DBG("napi_enable RX!!!\n"); ++ LocPtr->full_budge_count = 0; ++ LocPtr->max_polling = 0; ++ LocPtr->polling_count = 0; ++ LocPtr->ROVR_count = 0; ++#endif ++ ++#ifdef TX_NAPI ++ if(LocPtr->napi_tx.state == NAPI_STATE_SCHED) ++ { ++ napi_disable(&LocPtr->napi_tx); ++ GMAC_DBG("napi_disable TX!!!\n"); ++ } ++ ++ napi_enable(&LocPtr->napi_tx); ++ GMAC_DBG("napi_enable TX!!!\n"); ++#endif ++ ++ spin_lock_irq (&LocPtr->irq_lock); ++ ret = MDev_GMAC_update_linkspeed(dev); ++ spin_unlock_irq (&LocPtr->irq_lock); ++ ++ if (!is_valid_ether_addr (dev->dev_addr)) ++ return -EADDRNOTAVAIL; ++ ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= GMAC_CSR; ++ MHal_GMAC_Write_CTL(uRegVal); ++ // Enable PHY interrupt // ++ MHal_GMAC_enable_phyirq (); ++ ++ // Enable MAC interrupts // ++ MHal_GMAC_Write_IDR(0xFFFF); ++#ifndef RX_DELAY_INTERRUPT ++ uRegVal = GMAC_INT_RCOM | GMAC_INT_ENABLE; ++ MHal_GMAC_Write_IER(uRegVal); ++#else ++ MHal_GMAC_Write_IER(GMAC_INT_ENABLE); ++#endif ++ ++ LocPtr->ep_flag |= GMAC_EP_FLAG_OPEND; ++ ++ MDev_GMAC_start (dev); ++ netif_start_queue (dev); ++ ++ add_timer(&LocPtr->Link_timer); ++ ++ /* check if network linked */ ++ if (-1 == ret) ++ { ++ MDEV_GMAC_DISABLE_RX_REG(); ++ netif_carrier_off(dev); ++ LocPtr->ThisBCE.connected = 0; ++ } ++ else if(0 == ret) ++ { ++ netif_carrier_on(dev); ++ LocPtr->ThisBCE.connected = 1; ++ } ++ ++ return 0; ++} ++//------------------------------------------------------------------------------------------------- ++// Close the interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_close (struct net_device *dev) ++{ ++ u32 uRegVal; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++#ifdef RX_NAPI ++ napi_disable(&LocPtr->napi_rx); ++#endif ++ ++#ifdef TX_NAPI ++ napi_disable(&LocPtr->napi_tx); ++#endif ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ // Disable PHY interrupt // ++ MHal_GMAC_disable_phyirq (); ++#ifndef RX_DELAY_INTERRUPT ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_INT_ENABLE; ++ MHal_GMAC_Write_IDR(uRegVal); ++#else ++ MHal_GMAC_Write_IDR(GMAC_INT_ENABLE); ++#endif ++#ifdef RX_ZERO_COPY ++ MDev_GMAC_RX_DESC_close_zero_copy(dev); ++#endif ++ netif_stop_queue (dev); ++ netif_carrier_off(dev); ++ del_timer(&LocPtr->Link_timer); ++ LocPtr->ThisBCE.connected = 0; ++ LocPtr->ep_flag &= (~GMAC_EP_FLAG_OPEND); ++ ++#ifdef TX_DESC_MODE ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_THRESHOLD(0x0); ++#endif ++ ++#ifdef TX_SOFTWARE_QUEUE ++ _MDev_GMAC_tx_reset_TX_SW_QUEUE(dev); ++#endif ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update the current statistics from the internal statistics registers. ++//------------------------------------------------------------------------------------------------- ++static struct net_device_stats * MDev_GMAC_stats (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ int ale, lenerr, seqe, lcol, ecol; ++ if (netif_running (dev)) ++ { ++ LocPtr->stats.rx_packets += MHal_GMAC_Read_OK(); /* Good frames received */ ++ ale = MHal_GMAC_Read_ALE(); ++ LocPtr->stats.rx_frame_errors += ale; /* Alignment errors */ ++ lenerr = MHal_GMAC_Read_ELR(); ++ LocPtr->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ ++ seqe = MHal_GMAC_Read_SEQE(); ++ LocPtr->stats.rx_crc_errors += seqe; /* CRC error */ ++ LocPtr->stats.rx_fifo_errors += MHal_GMAC_Read_ROVR(); ++ LocPtr->stats.rx_errors += ale + lenerr + seqe + MHal_GMAC_Read_SE() + MHal_GMAC_Read_RJB(); ++ LocPtr->stats.tx_packets += MHal_GMAC_Read_FRA(); /* Frames successfully transmitted */ ++ LocPtr->stats.tx_fifo_errors += MHal_GMAC_Read_TUE(); /* Transmit FIFO underruns */ ++ LocPtr->stats.tx_carrier_errors += MHal_GMAC_Read_CSE(); /* Carrier Sense errors */ ++ LocPtr->stats.tx_heartbeat_errors += MHal_GMAC_Read_SQEE(); /* Heartbeat error */ ++ lcol = MHal_GMAC_Read_LCOL(); ++ ecol = MHal_GMAC_Read_ECOL(); ++ LocPtr->stats.tx_window_errors += lcol; /* Late collisions */ ++ LocPtr->stats.tx_aborted_errors += ecol; /* 16 collisions */ ++ LocPtr->stats.collisions += MHal_GMAC_Read_SCOL() + MHal_GMAC_Read_MCOL() + lcol + ecol; ++ } ++ return &LocPtr->stats; ++} ++ ++static int MDev_GMAC_TxReset(void) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x000001FFUL; ++ ++ MHal_GMAC_Write_CTL((val & ~GMAC_TE)); ++ MHal_GMAC_Write_TCR(0); ++ MHal_GMAC_Write_CTL((MHal_GMAC_Read_CTL() | GMAC_TE)); ++ return 0; ++} ++ ++#if 0 ++static u8 pause_pkt[] = ++{ ++ //DA - multicast ++ 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01, ++ //SA ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ //Len-Type ++ 0x88, 0x08, ++ //Ctrl code ++ 0x00, 0x01, ++ //Ctrl para 8192 ++ 0x20, 0x00 ++}; ++#endif ++ ++void MDrv_GMAC_DumpMem(phys_addr_t addr, u32 len) ++{ ++ u8 *ptr = (u8 *)addr; ++ u32 i; ++ ++ printk("\n ===== Dump %lx =====\n", (long unsigned int)ptr); ++ for (i=0; istats.tx_bytes += len; ++ ++#ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_GMAC_Write_TAR(skb_addr - LocPtr->RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_GMAC_Write_TCR(len); ++ ++ return NETDEV_TX_OK; ++} ++ ++static void MDev_GMAC_Send_PausePkt(struct net_device* dev) ++{ ++ u32 val = MHal_GMAC_Read_CTL() & 0x000001FFUL; ++ ++ //Disable Rx ++ MHal_GMAC_Write_CTL((val & ~GMAC_RE)); ++ memcpy(&pause_pkt[6], dev->dev_addr, 6); ++ MDev_GMAC_BGsend(dev, (u32)pause_pkt, sizeof(pause_pkt)); ++ //Enable Rx ++ MHal_GMAC_Write_CTL((MHal_GMAC_Read_CTL() | GMAC_RE)); ++} ++#endif ++ ++#ifdef TX_ZERO_COPY ++#ifdef TX_DESC_MODE ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_TX_Desc_Reset(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++ LocPtr->tx_desc_write_index = 0; ++ LocPtr->tx_desc_read_index = 0; ++ LocPtr->tx_desc_queued_number = 0; ++ LocPtr->tx_desc_count= 0; ++ LocPtr->tx_desc_full_count= 0; ++} ++ ++static void MDev_GMAC_TX_Desc_Mode_Set(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_BASE(LocPtr->X_LP_DESC_BASE - GMAC_MIU0_BUS_BASE); ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_THRESHOLD(TX_LOW_PRI_DESC_NUMBER|GMAC_RW_TX_DESC_EN_W); ++ return; ++} ++ ++static u32 MDev_GMAC_TX_Free_sk_buff(struct net_device *dev, u32 work_done) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 free_sk_buffer_number, free_count, flags; ++ ++ spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ ++ free_count = 0; ++ free_sk_buffer_number = LocPtr->tx_desc_queued_number - (MHal_GMAC_Read_LOW_PRI_TX_DESC_QUEUED() & 0x03FFFUL); ++ ++ if(free_sk_buffer_number > 8) ++ { ++ free_sk_buffer_number = free_sk_buffer_number - 8; ++ } ++ else ++ { ++ free_sk_buffer_number = 0; ++ } ++ ++ while(free_sk_buffer_number > free_count) ++ { ++ //GMAC_DBG("tx_desc_sk_buff_list = 0x%zx, tx_desc_list = 0x%zx, tx_desc_read_index = 0x%zx\n", (size_t)LocPtr->tx_desc_sk_buff_list[LocPtr->tx_desc_read_index], (size_t)LocPtr->tx_desc_list[LocPtr->tx_desc_read_index].addr, LocPtr->tx_desc_read_index); ++ ++ dma_unmap_single(&dev->dev, LocPtr->tx_desc_list[LocPtr->tx_desc_read_index].addr + GMAC_MIU0_BUS_BASE, LocPtr->tx_desc_list[LocPtr->tx_desc_read_index].low_tag & 0x03FFFUL, DMA_TO_DEVICE); ++ dev_kfree_skb_any(LocPtr->tx_desc_sk_buff_list[LocPtr->tx_desc_read_index]); ++ ++ LocPtr->stats.tx_bytes += (LocPtr->tx_desc_list[LocPtr->tx_desc_read_index].low_tag & 0x03FFFUL); ++ LocPtr->tx_desc_sk_buff_list[LocPtr->tx_desc_read_index]=NULL; ++ LocPtr->tx_desc_read_index++; ++ if(TX_LOW_PRI_DESC_NUMBER == LocPtr->tx_desc_read_index) ++ { ++ LocPtr->tx_desc_read_index = 0; ++ } ++// EMAC_DBG("Free Next No.%d, MHal_EMAC_Read_LOW_PRI_TX_DESC_PTR() = 0x%zx\n", LocPtr->tx_desc_read_index, MHal_EMAC_Read_LOW_PRI_TX_DESC_PTR() & 0x03FFFUL); ++ ++ LocPtr->tx_desc_queued_number--; ++ ++ free_count++; ++#ifdef TX_NAPI ++ if(free_count + work_done > GMAC_TX_NAPI_WEIGHT) ++ break; ++#endif ++ } ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ //MHal_GMAC_Write_IDR(GMAC_INT_TCOM); ++ ++ return free_count; ++} ++ ++ ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 flags; ++ u32 dummy; ++ dma_addr_t skb_addr; ++ ++#ifndef TX_COM_ENABLE ++ MDev_GMAC_TX_Free_sk_buff(dev, 0); ++#endif ++ ++ spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ ++ if(LocPtr->tx_desc_queued_number > TX_DESC_REFILL_NUMBER) ++ { ++ //MHal_GMAC_Write_IER(GMAC_INT_TCOM); ++ } ++ ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ // Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ ++ skb_addr = dma_map_single(&dev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(&dev->dev, skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ goto out_unlock; ++ } ++ ++ #ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((unsigned int)skb&0x0FFFFFFFUL, skb->len); ++ #endif ++ #endif ++ ++ LocPtr->tx_desc_sk_buff_list[LocPtr->tx_desc_write_index]= skb; ++ LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].addr = skb_addr - GMAC_MIU0_BUS_BASE; ++ if(LocPtr->tx_desc_write_index == TX_LOW_PRI_DESC_NUMBER - 1) ++ { ++ LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].low_tag = (skb->len & 0x3FFFUL) | GMAC_TX_DESC_WRAP; ++ #ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((u32)(&(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])) & 0x0FFFFFFF, sizeof(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])); ++ #endif ++ #endif ++ LocPtr->tx_desc_write_index = 0; ++ } ++ else ++ { ++ LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].low_tag = skb->len & 0x3FFFUL; ++ #ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((u32)(&(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])) & 0x0FFFFFFF, sizeof(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])); ++ #endif ++ #endif ++ LocPtr->tx_desc_write_index++; ++ } ++ ++ //GMAC_DBG("tx_desc_sk_buff_list = 0x%zx, tx_desc_list = 0x%zx, tx_desc_write_index = 0x%zx\n", LocPtr->tx_desc_sk_buff_list[LocPtr->tx_desc_write_index], (size_t)LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].addr, (size_t)LocPtr->tx_desc_write_index); ++ ++ //Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ //dummy = MHal_GMAC_ReadRam32((u32)&LocPtr->tx_desc_list[LocPtr->tx_desc_write_index], 0); ++ //udelay(100); ++ ++ //Chip_Flush_Cache_Range_VA_PA((u32)(&(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])),(u32)(&(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])) - LocPtr->RAM_VA_PA_OFFSET ,sizeof(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])); ++ ++ if(LocPtr->tx_desc_count % 2 == 0) ++ { ++ //EMAC_DBG("0x%zx\n", LocPtr->tx_desc_trigger_flag); ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_TRANSMIT0(0x1); ++ } ++ else ++ { ++ //EMAC_DBG("0x%zx\n", LocPtr->tx_desc_trigger_flag); ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_TRANSMIT1(0x1); ++ } ++ ++ if(LocPtr->tx_desc_write_index == TX_LOW_PRI_DESC_NUMBER - 1) ++ { ++ LocPtr->tx_desc_write_index = 0; ++ } ++ else ++ { ++ LocPtr->tx_desc_write_index++; ++ } ++ ++ LocPtr->tx_desc_count++; ++ LocPtr->tx_desc_queued_number++; ++ ++ if( LocPtr->tx_desc_queued_number == TX_LOW_PRI_DESC_NUMBER) ++ { ++ LocPtr->tx_desc_full_count++; ++ GMAC_DBG("TX descriptor full : %d\n", LocPtr->tx_desc_full_count); ++ netif_stop_queue(dev); ++ } ++ ++ out_unlock: ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_OK; ++ ++} ++#else ++#ifdef TX_SOFTWARE_QUEUE ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++// read skb from TX_SW_QUEUE to HW, ++// !!!! NO SPIN LOCK INSIDE !!!! ++static int MDev_GMAC_GetTXFIFOIdle(void) ++{ ++ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_GMAC_Read_TSR(); ++ avlfifo[0] = ((tsrval & GMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & GMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & GMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & GMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & GMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & GMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & GMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & GMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ return avlfifoval-4; ++ } ++ return 0; ++} ++ ++static void _MDev_GMAC_tx_read_TX_SW_QUEUE(int txIdleCount,struct net_device *dev,int intr) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++// int txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ ++ while(txIdleCount>0){ ++ ++ struct tx_ring *txq=&(LocPtr->tx_swq[LocPtr->tx_rdidx]); ++ if(txq->used == TX_DESC_WROTE) ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ //Chip_Flush_Memory_Range((size_t)txq->skb->data,txq->skb->len); ++ MHal_GMAC_Write_TAR(txq->skb_physaddr - GMAC_MIU0_BUS_BASE); ++ MHal_GMAC_Write_TCR(txq->skb->len); ++ txq->used=TX_DESC_READ; ++ LocPtr->tx_rdidx ++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_rdidx) ++ { ++ LocPtr->tx_rdwrp++; ++ LocPtr->tx_rdidx =0; ++ } ++ }else{ ++ break; ++ } ++ txIdleCount--; ++ } ++ ++} ++ ++// clear skb from TX_SW_QUEUE ++// !!!! NO SPIN LOCK INSIDE !!!! ++static void _MDev_GMAC_tx_clear_TX_SW_QUEUE(int txIdleCount,struct net_device *dev,int intr) ++{ ++ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ int clearcnt=0; ++ int fifoCount=0;//LocPtr->tx_rdidx-LocPtr->tx_clidx; ++ if(0==txIdleCount)return; ++ ++ fifoCount=LocPtr->tx_rdidx-LocPtr->tx_clidx; ++ if(fifoCount<0)fifoCount=LocPtr->tx_rdidx+(TX_SW_QUEUE_SIZE-LocPtr->tx_clidx); ++ ++ /* ++ * "fifoCount" is the count of the packets that has been sent to the EMAC HW. ++ * "(TX_FIFO_SIZE-txIdleCount)" is the packet count that has not yet been sent out completely by EMAC HW ++ */ ++ clearcnt = fifoCount-(TX_FIFO_SIZE-txIdleCount); ++ if((clearcnt > TX_FIFO_SIZE) || (clearcnt < 0)){ ++ printk(KERN_ERR"fifoCount in _MDev_EMAC_tx_clear_TX_SW_QUEUE() ERROR!! fifoCount=%d intr=%d, %d, %d, %d, %d\n",fifoCount,intr,LocPtr->tx_rdidx,LocPtr->tx_clidx,txIdleCount,TX_FIFO_SIZE); ++ } ++ ++ while(clearcnt>0) ++ { ++ struct tx_ring *txq=&(LocPtr->tx_swq[LocPtr->tx_clidx]); ++ if(TX_DESC_READ==txq->used) ++ { ++ ++ dma_unmap_single(&dev->dev, txq->skb_physaddr, txq->skb->len, DMA_TO_DEVICE); ++ ++ LocPtr->stats.tx_bytes += txq->skb->len; ++ ++ dev_kfree_skb_any(txq->skb); ++ ++ txq->used = TX_DESC_CLEARED; ++ txq->skb=NULL; ++ LocPtr->tx_clidx++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_clidx) ++ { ++ LocPtr->tx_clwrp++; ++ LocPtr->tx_clidx =0; ++ } ++ }else{ ++ break; ++ } ++ clearcnt--; ++ } ++} ++ ++static void _MDev_GMAC_tx_reset_TX_SW_QUEUE(struct net_device* netdev) ++{ ++ struct GMAC_private *LocPtr; ++ u32 i=0; ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev); ++ for (i=0;itx_swq[i].skb != NULL) ++ { ++ dma_unmap_single(&netdev->dev, LocPtr->tx_swq[i].skb_physaddr, LocPtr->tx_swq[i].skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb_any(LocPtr->tx_swq[i].skb); ++ ++ } ++ LocPtr->tx_swq[i].skb = NULL; ++ LocPtr->tx_swq[i].used = TX_DESC_CLEARED; ++ LocPtr->tx_swq[i].skb_physaddr = 0; ++ } ++ LocPtr->tx_clidx = 0; ++ LocPtr->tx_wridx = 0; ++ LocPtr->tx_rdidx = 0; ++ LocPtr->tx_clwrp = 0; ++ LocPtr->tx_wrwrp = 0; ++ LocPtr->tx_rdwrp = 0; ++ LocPtr->tx_swq_full_cnt=0; ++} ++ ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ { ++ int txIdleCount=0;//MDev_EMAC_GetTXFIFOIdle(); ++ //FIFO full, loop until HW empty then try again ++ //This is an abnormal condition as the upper network tx_queue should already been stopped by "netif_stop_queue(dev)" in code below ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used > TX_DESC_CLEARED) ++ { ++ printk(KERN_ERR"ABNORMAL !! %d, %d, %d, %d\n",LocPtr->tx_wridx,LocPtr->tx_rdidx,LocPtr->tx_clidx, LocPtr->tx_swq[LocPtr->tx_wridx].used ); ++ BUG(); ++ /* ++ txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ while(0==txIdleCount) ++ { ++ txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ } ++ _MDev_EMAC_tx_clear_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_GENERAL_TX); ++ */ ++ } ++ ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ ++ //map skbuffer for DMA ++ skb_addr = dma_map_single(&dev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(&dev->dev, skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ ++ goto out_unlock; ++ } ++ ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb = skb; ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb_physaddr= skb_addr; ++ LocPtr->tx_swq[LocPtr->tx_wridx].used = TX_DESC_WROTE; ++ LocPtr->tx_wridx ++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_wridx) ++ { ++ LocPtr->tx_wridx=0; ++ LocPtr->tx_wrwrp++; ++ } ++ ++ ++ //if FIFO is full, netif_stop_queue ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used > TX_DESC_CLEARED) ++ { ++ LocPtr->tx_swq_full_cnt++; ++ netif_stop_queue(dev); ++ } ++ ++ // clear & read to HW FIFO ++ txIdleCount = MDev_GMAC_GetTXFIFOIdle(); ++ ++ _MDev_GMAC_tx_clear_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_GENERAL_TX); ++ _MDev_GMAC_tx_read_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_GENERAL_TX); ++ } ++ ++out_unlock: ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_OK; ++} ++#endif ++#endif ++#else ++#ifdef NEW_TX_QUEUE ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ //spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (MHal_GMAC_New_TX_QUEUE_OVRN_Get() == 1) ++ { ++ //GMAC_DBG("New_TX_QUEUE_OVRN\n"); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ skb_addr = LocPtr->TX_BUFFER_BASE + LocPtr->RAM_VA_PA_OFFSET + TX_BUFF_ENTRY_SIZE * LocPtr->tx_index; ++ LocPtr->tx_index ++; ++ LocPtr->tx_index = LocPtr->tx_index % TX_BUFF_ENTRY_NUMBER; ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ ++ ++ if (!skb_addr) ++ { ++ GMAC_DBG("Can not get memory from GMAC area\n"); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return -ENOMEM; ++ } ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ ++ ++ LocPtr->stats.tx_bytes += skb->len; ++ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((u32)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ TO_DO;Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ MHal_GMAC_Write_TAR(skb_addr - LocPtr->RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ MHal_GMAC_Write_TCR(skb->len); ++ ++ //netif_stop_queue (dev); ++ dev->trans_start = jiffies; ++ dev_kfree_skb_irq(skb); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_OK; ++} ++#elif defined(TX_DESC_MODE) ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_TX_Desc_Reset(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++ LocPtr->tx_desc_write_index = 0; ++ LocPtr->tx_desc_read_index = 0; ++ LocPtr->tx_desc_queued_number = 0; ++ LocPtr->tx_desc_count = 0; ++ LocPtr->tx_desc_full_count = 0; ++ LocPtr->tx_index = 0; ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_THRESHOLD(0x0); ++} ++ ++static void MDev_GMAC_TX_Desc_Mode_Set(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_BASE(LocPtr->TX_LP_DESC_BASE - GMAC_MIU0_BUS_BASE); ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_THRESHOLD(TX_LOW_PRI_DESC_NUMBER|GMAC_RW_TX_DESC_EN_W); ++ return; ++} ++ ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (MHal_GMAC_LOW_PRI_TX_DESC_MODE_OVRN_Get() == 1) ++ { ++ //EMAC_DBG("New_TX_QUEUE_OVRN\n"); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ ++ skb_addr = LocPtr->TX_BUFFER_BASE + LocPtr->RAM_VA_PA_OFFSET + TX_BUFF_ENTRY_SIZE * LocPtr->tx_index; ++ LocPtr->tx_index ++; ++ LocPtr->tx_index = LocPtr->tx_index % TX_BUFF_ENTRY_NUMBER; ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ ++ if (!skb_addr) ++ { ++ GMAC_DBG("Can not get memory from GMAC area\n"); ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return -ENOMEM; ++ } ++ ++ // Store packet information (to free when Tx completed) // ++ LocPtr->stats.tx_bytes += skb->len; ++ ++ ++#ifdef CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ TO_DO;Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ //Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].addr = skb_addr - LocPtr->RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE; ++ ++ if(LocPtr->tx_desc_write_index == TX_LOW_PRI_DESC_NUMBER - 1) ++ { ++ LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].low_tag = (skb->len & 0x3FFFUL) | GMAC_TX_DESC_WRAP; ++#ifdef GMAC_CHIP_FLUSH_READ ++ Chip_Flush_Memory_Range((u32)(&(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])) & 0x0FFFFFFF, sizeof(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])); ++#endif ++ ++ LocPtr->tx_desc_write_index = 0; ++ } ++ else ++ { ++ LocPtr->tx_desc_list[LocPtr->tx_desc_write_index].low_tag = skb->len & 0x3FFFUL; ++#ifdef GMAC_CHIP_FLUSH_READ ++ Chip_Flush_Memory_Range((u32)(&(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])) & 0x0FFFFFFF, sizeof(LocPtr->tx_desc_list[LocPtr->tx_desc_write_index])); ++#endif ++ LocPtr->tx_desc_write_index++; ++ } ++ ++ if(LocPtr->tx_desc_count % 2 == 0) ++ { ++ //GMAC_DBG("0x%zx\n", LocPtr->tx_desc_trigger_flag); ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_TRANSMIT0(0x1); ++ } ++ else ++ { ++ //GMAC_DBG("0x%zx\n", LocPtr->tx_desc_trigger_flag); ++ MHal_GMAC_Write_LOW_PRI_TX_DESC_TRANSMIT1(0x1); ++ } ++ ++ LocPtr->tx_desc_count++; ++ ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ ++ //netif_stop_queue (dev); ++ dev->trans_start = jiffies; ++ dev_kfree_skb_irq(skb); ++ ++ return NETDEV_TX_OK; ++} ++#else ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_CheckTSR(void) ++{ ++ u32 tsrval = 0; ++ ++ #ifdef GMAC_TX_QUEUE_4 ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ //for (check = 0; check < GMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_GMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & GMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & GMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & GMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & GMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & GMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & GMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & GMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & GMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ return NETDEV_TX_OK; ++ } ++ #else ++ //for (check = 0; check < GMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_GMAC_Read_TSR(); ++ ++ // check GMAC_FIFO1IDLE is ok for gmac one queue ++ if ((tsrval & GMAC_IDLETSR) && (tsrval & GMAC_FIFO1IDLE)) ++ return NETDEV_TX_OK; ++ } ++ #endif ++ ++ //GMAC_DBG("Err CheckTSR:0x%x\n", tsrval); ++ //MDev_GMAC_TxReset(); ++ ++ return NETDEV_TX_BUSY; ++} ++ ++static int MDev_GMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ //spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ ++ if (skb->len > GMAC_MTU) ++ { ++ GMAC_DBG("Wrong Tx len:%u\n", skb->len); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (NETDEV_TX_OK != MDev_GMAC_CheckTSR()) ++ { ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return NETDEV_TX_BUSY; //check ++ } ++ ++ spin_lock_irqsave(&LocPtr->tx_lock, flags); ++ ++ skb_addr = LocPtr->TX_BUFFER_BASE + LocPtr->RAM_VA_PA_OFFSET + TX_BUFF_ENTRY_SIZE * LocPtr->tx_index; ++ LocPtr->tx_index ++; ++ LocPtr->tx_index = LocPtr->tx_index % TX_BUFF_ENTRY_NUMBER; ++ ++ spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ ++ if (!skb_addr) ++ { ++ GMAC_DBG("Can not get memory from EMAC area\n"); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ return -ENOMEM; ++ } ++ ++ // Store packet information (to free when Tx completed) // ++ LocPtr->stats.tx_bytes += skb->len; ++ ++ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((unsigned int)skb_addr < 0xC0000000UL) ++ { ++ Chip_Flush_Memory_Range((unsigned int)skb_addr&0x0FFFFFFFUL, skb->len); ++ } ++ else ++ { ++ Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Cache_Range((size_t)skb->data, skb->len); ++ #else ++ #ERROR ++ #endif ++#endif ++ //Moniter TX packet ++ if(gb_tx_packet_dump_en) ++ MDrv_GMAC_DumpMem(skb_addr, skb->len); ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_GMAC_Write_TAR(skb_addr - LocPtr->RAM_VA_PA_OFFSET - GMAC_MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_GMAC_Write_TCR(skb->len); ++ ++ //netif_stop_queue (dev); ++ dev->trans_start = jiffies; ++ dev_kfree_skb_irq(skb); ++ //spin_unlock_irqrestore(&LocPtr->tx_lock, flags); ++ ++ return NETDEV_TX_OK; ++} ++#endif ++#endif ++ ++#ifdef RX_ZERO_COPY ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Enable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_RX_DESC_Init_zero_copy(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ struct sk_buff *skb = NULL; ++ u32 skb_addr; ++ u32 rx_desc_index; ++ int retry_cnt = 0; ++ ++ MDev_GMAC_RX_DESC_close_zero_copy(dev); ++ ++ memset((void *)LocPtr->RX_DESC_BASE + LocPtr->RAM_VA_PA_OFFSET, 0x00UL, RX_DESC_TABLE_SIZE); ++ ++ for(rx_desc_index = 0; rx_desc_index < RX_DESC_NUMBER; rx_desc_index++) ++ { ++ skb = alloc_skb(RX_BUFF_ENTRY_SIZE, GFP_ATOMIC); ++ ++ while (!skb) { ++ if (retry_cnt > 10) { ++ GMAC_DBG("MDev_GMAC_RX_DESC_Init_zero_copy: alloc skb fail for %d times!\n", retry_cnt); ++ BUG_ON(1); ++ } ++ skb = alloc_skb(RX_BUFF_ENTRY_SIZE, GFP_ATOMIC); ++ retry_cnt++; ++ } ++ retry_cnt = 0; ++ ++ if((skb_addr = (u32)__virt_to_phys((unsigned long)skb->data)) > MSTAR_MIU1_BUS_BASE) ++ { ++ skb_addr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else ++ { ++ skb_addr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ LocPtr->rx_desc_sk_buff_list[rx_desc_index] = skb; ++ if(rx_desc_index < (RX_DESC_NUMBER - 1)) ++ { ++ LocPtr->rx_desc_list[rx_desc_index].addr = (u32)skb_addr; ++ } ++ else ++ { ++ LocPtr->rx_desc_list[rx_desc_index].addr = (u32)skb_addr + GMAC_DESC_WRAP; ++ } ++ ++ skb = NULL; ++ } ++ ++ LocPtr->rx_desc_read_index = 0; ++ ++ MHal_GMAC_Write_RBQP(LocPtr->RX_DESC_BASE - GMAC_MIU0_BUS_BASE); ++ //MHal_GMAC_Write_BUFF(GMAC_CLEAR_BUFF); ++ ++ return; ++} ++ ++static void MDev_GMAC_RX_DESC_close_zero_copy(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 rx_desc_index; ++ ++ for(rx_desc_index = 0; rx_desc_index < RX_DESC_NUMBER; rx_desc_index++) ++ { ++ if(LocPtr->rx_desc_sk_buff_list[rx_desc_index]) ++ dev_kfree_skb_any(LocPtr->rx_desc_sk_buff_list[rx_desc_index]); ++ LocPtr->rx_desc_sk_buff_list[rx_desc_index] = NULL; ++ } ++ return; ++} ++ ++static int MDev_GMAC_rx (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 pktlen=0; ++ u32 received_number=0; ++ struct sk_buff *skb = NULL; ++ int retry_cnt = 0; ++ ++ do ++ { ++ if(!((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr) & GMAC_DESC_DONE)) ++ { ++ if (LocPtr->rx_desc_list[(LocPtr->rx_desc_read_index + RX_DESC_NUMBER - 1) % RX_DESC_NUMBER].addr & GMAC_DESC_DONE) ++ LocPtr->rx_desc_list[(LocPtr->rx_desc_read_index + RX_DESC_NUMBER - 1) % RX_DESC_NUMBER].addr &= ~GMAC_DESC_DONE; ++ break; ++ } ++ ++ pktlen = ((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].high_tag & 0x7UL) << 11) | (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag& 0x7ffUL); /* Length of frame including FCS */ ++ ++ if (pktlen > GMAC_MTU || pktlen < 64) ++ { ++ //GMAC_DBG("Packet RX too large!!(pktlen = %d)\n", pktlen); ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr &= ~GMAC_DESC_DONE; ++ Chip_Flush_MIU_Pipe(); ++ LocPtr->rx_desc_read_index++; ++ if (LocPtr->rx_desc_read_index == RX_DESC_NUMBER) ++ { ++ LocPtr->rx_desc_read_index = 0; ++ } ++ ++ LocPtr->stats.rx_length_errors++; ++ LocPtr->stats.rx_errors++; ++ LocPtr->stats.rx_dropped++; ++ continue; ++ } ++ ++ pktlen = pktlen - 4; ++ ++ skb_put(LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index], pktlen); ++ ++ LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]->protocol = eth_type_trans (LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index], dev); ++ dev->last_rx = jiffies; ++ ++ if(((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_TCP ) || (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_UDP )) && \ ++ (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_IP_CSUM) && \ ++ (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ ++ #ifdef RX_NAPI ++ #ifdef RX_GRO ++ napi_gro_receive(&LocPtr->napi_rx,LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]); ++ #else ++ netif_receive_skb(LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]); ++ #endif ++ #else ++ netif_rx(LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]); ++ #endif ++ ++ received_number++; ++ LocPtr->stats.rx_bytes += pktlen; ++ ++ if (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag& GMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ ++ skb = alloc_skb(RX_BUFF_ENTRY_SIZE, GFP_ATOMIC); ++ ++ while (!skb) { ++ if (retry_cnt > 10) { ++ GMAC_DBG("MDev_GMAC_rx: alloc skb fail for %d times!\n", retry_cnt); ++ BUG_ON(1); ++ } ++ skb = alloc_skb(RX_BUFF_ENTRY_SIZE, GFP_ATOMIC); ++ retry_cnt++; ++ } ++ ++ LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index] = skb; ++ skb = NULL; ++ ++ if(LocPtr->rx_desc_read_index < (RX_DESC_NUMBER - 1)) ++ { ++ if((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr = (u32)__virt_to_phys((unsigned long)LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]->data)) > MSTAR_MIU1_BUS_BASE) ++ { ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else ++ { ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr -= MSTAR_MIU0_BUS_BASE; ++ } ++ } ++ else ++ { ++ if((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr = (u32)__virt_to_phys((unsigned long)LocPtr->rx_desc_sk_buff_list[LocPtr->rx_desc_read_index]->data)) > MSTAR_MIU1_BUS_BASE) ++ { ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr -= MSTAR_MIU1_BUS_BASE; ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr += GMAC_DESC_WRAP; ++ } ++ else ++ { ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr -= MSTAR_MIU0_BUS_BASE; ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr += GMAC_DESC_WRAP; ++ } ++ } ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ LocPtr->rx_desc_read_index++; ++ if (LocPtr->rx_desc_read_index == RX_DESC_NUMBER) ++ { ++ LocPtr->rx_desc_read_index = 0; ++ } ++ ++ #ifdef RX_NAPI ++ if(received_number >= LocPtr->napi_rx.weight) { ++ break; ++ } ++ #endif ++ ++ }while(1); ++ ++ return received_number; ++} ++#else //#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Disable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_RX_DESC_Init_memcpy(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 rx_desc_index; ++ ++ memset((u8*)LocPtr->RAM_VA_PA_OFFSET + LocPtr->RX_BUFFER_BASE, 0x00UL, RX_BUFF_SIZE); ++ ++ for(rx_desc_index = 0; rx_desc_index < RX_DESC_NUMBER; rx_desc_index++) ++ { ++ if(rx_desc_index < (RX_DESC_NUMBER - 1)) ++ { ++ LocPtr->rx_desc_list[rx_desc_index].addr = LocPtr->RX_BUFFER_BASE - GMAC_MIU0_BUS_BASE + RX_BUFF_ENTRY_SIZE * rx_desc_index; ++ } ++ else ++ { ++ LocPtr->rx_desc_list[rx_desc_index].addr = (LocPtr->RX_BUFFER_BASE - GMAC_MIU0_BUS_BASE + RX_BUFF_ENTRY_SIZE * rx_desc_index) | GMAC_DESC_WRAP; ++ } ++ } ++ ++ return; ++} ++ ++static void MDev_GMAC_RX_DESC_Reset_memcpy(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 rx_desc_index; ++ ++ for(rx_desc_index = 0; rx_desc_index < RX_DESC_NUMBER; rx_desc_index++) ++ { ++ LocPtr->rx_desc_list[rx_desc_index].addr &= ~GMAC_DESC_DONE; ++ } ++ ++ // Program address of descriptor list in Rx Buffer Queue register // ++ MHal_GMAC_Write_RBQP(LocPtr->RX_DESC_BASE - GMAC_MIU0_BUS_BASE); ++ ++ //Reset buffer index// ++ LocPtr->rx_desc_read_index = 0; ++ ++ return; ++} ++ ++static int MDev_GMAC_rx (struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 retval=0; ++ u32 received_number=0; ++ struct sk_buff *skb; ++ ++ // If any Ownership bit is 1, frame received. ++ //while ( (dlist->descriptors[LocPtr->rxBuffIndex].addr )& GMAC_DESC_DONE) ++ do ++ { ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Read_Memory_Range((u32)(&(LocPtr->rx_desc_list[LocPtr->rx_desc_read_index])) & 0x0FFFFFFFUL, sizeof(struct rx_descriptor)); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range((u32)(&LocPtr->rx_desc_list[LocPtr->rx_desc_read_index]), sizeof(struct rx_descriptor)); ++ #else ++ #ERROR ++ #endif ++#endif ++ if (!(LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr & GMAC_DESC_DONE)) { ++ if (LocPtr->rx_desc_list[(LocPtr->rx_desc_read_index + RX_DESC_NUMBER - 1) % RX_DESC_NUMBER].addr & GMAC_DESC_DONE) ++ LocPtr->rx_desc_list[(LocPtr->rx_desc_read_index + RX_DESC_NUMBER - 1) % RX_DESC_NUMBER].addr &= ~GMAC_DESC_DONE; ++ break; ++ } ++ ++ p_recv = (char *) ((((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr) & 0xFFFFFFFFUL) + LocPtr->RAM_VA_PA_OFFSET + GMAC_MIU0_BUS_BASE) & ~(GMAC_DESC_DONE | GMAC_DESC_WRAP)); ++ pktlen = ((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].high_tag & 0x7) << 11) | (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & 0x7ffUL); /* Length of frame including FCS */ ++ ++ skb = alloc_skb (pktlen + 6, GFP_ATOMIC); ++ ++ if (skb != NULL) ++ { ++ skb_reserve (skb, 2); ++ #ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ if((u32)p_recv < 0xC0000000UL) ++ { ++ Chip_Read_Memory_Range((u32)(p_recv) & 0x0FFFFFFFUL, pktlen); ++ } ++ else ++ { ++ Chip_Read_Memory_Range(0, 0xFFFFFFFFUL); ++ } ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Inv_Cache_Range((size_t)p_recv, pktlen); ++ #else ++ #ERROR ++ #endif ++ #endif ++ if(gb_rx_packet_dump_en) ++ MDrv_GMAC_DumpMem((phys_addr_t)p_recv, pktlen); ++ ++ memcpy(skb_put(skb, pktlen), p_recv, pktlen); ++ skb->protocol = eth_type_trans (skb, dev); ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++ ++ ++ #ifdef GMAC_RX_CHECKSUM ++ if(((LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_TCP ) || (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_UDP )) && \ ++ (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_IP_CSUM) && \ ++ (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ skb->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ #ifdef RX_NAPI ++ #ifdef RX_GRO ++ retval = napi_gro_receive(&LocPtr->napi_rx, skb); ++ #else ++ retval = netif_receive_skb(skb); ++ #endif ++ #else ++ retval = netif_rx(skb); ++ #endif ++ ++ received_number++; ++ } ++ else ++ { ++ GMAC_DBG("alloc_skb fail!!!\n"); ++ //LocPtr->stats.rx_dropped += 1; ++ } ++ ++ if (LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].low_tag & GMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr &= ~GMAC_DESC_DONE; /* reset ownership bit */ ++#ifdef GMAC_CHIP_FLUSH_READ ++ #if defined(CONFIG_MIPS) ++ Chip_Flush_Memory_Range((u32)(&(LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr)) & 0x0FFFFFFFUL, sizeof(LocPtr->rx_desc_list[LocPtr->rx_desc_read_index].addr)); ++ #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ Chip_Flush_Cache_Range((u32)(&LocPtr->rx_desc_list[LocPtr->rx_desc_read_index]), sizeof(struct rx_descriptor)); ++ #else ++ #ERROR ++ #endif ++#endif ++ ++ //wrap after last buffer // ++ LocPtr->rx_desc_read_index++; ++ if (LocPtr->rx_desc_read_index == RX_DESC_NUMBER) ++ { ++ LocPtr->rx_desc_read_index = 0; ++ } ++ ++ #ifdef RX_NAPI ++ if(received_number >= LocPtr->napi_rx.weight) { ++ break; ++ } ++ #else ++ if(received_number >= GMAC_RX_NAPI_WEIGHT) { ++ break; ++ } ++ #endif ++ ++ }while(1); ++ return received_number; ++} ++#endif //#ifdef GMAC_RX_SOFTWARE_DESCRIPTOR ++ ++// Enable MAC interrupts ++static void MDEV_GMAC_ENABLE_RX_REG(void) ++{ ++ u32 uRegVal; ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++#ifndef RX_DELAY_INTERRUPT ++ // disable MAC interrupts ++ uRegVal = GMAC_INT_RCOM | GMAC_INT_ENABLE; ++ MHal_GMAC_Write_IER(uRegVal); ++#else ++ uRegVal = GMAC_INT_ENABLE; ++ MHal_GMAC_Write_IER(uRegVal); ++ // enable delay interrupt ++ uRegVal = MHal_GMAC_Read_Network_config_register3(); ++ uRegVal |= 0x00000080UL; ++ MHal_GMAC_Write_Network_config_register3(uRegVal); ++#endif ++} ++ ++// Disable MAC interrupts ++static void MDEV_GMAC_DISABLE_RX_REG(void) ++{ ++ u32 uRegVal; ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++#ifndef RX_DELAY_INTERRUPT ++ // Enable MAC interrupts ++ uRegVal = GMAC_INT_RCOM | GMAC_INT_ENABLE; ++ MHal_GMAC_Write_IDR(uRegVal); ++#else ++ uRegVal = 0xFFFF; ++ MHal_GMAC_Write_IDR(uRegVal); ++ // disable delay interrupt ++ uRegVal = MHal_GMAC_Read_Network_config_register3(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_GMAC_Write_Network_config_register3(uRegVal); ++#endif ++} ++ ++#ifdef RX_NAPI ++static int MDev_GMAC_RX_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct GMAC_private *LocPtr = container_of(napi, struct GMAC_private, napi_rx); ++ struct net_device *dev = LocPtr->dev; ++ int work_done = 0; ++ ++ work_done = MDev_GMAC_rx(dev); ++ ++ if (work_done < budget) { ++ napi_complete(napi); ++ // enable MAC interrupt ++ MDEV_GMAC_ENABLE_RX_REG(); ++ } ++ ++ return work_done; ++} ++#endif ++ ++#ifdef TX_NAPI ++// Enable MAC interrupts ++static void MDEV_GMAC_ENABLE_TX_REG(void) ++{ ++ MHal_GMAC_Write_IER(GMAC_INT_TCOM); ++} ++ ++// Disable MAC interrupts ++static void MDEV_GMAC_DISABLE_TX_REG(void) ++{ ++ MHal_GMAC_Write_IDR(GMAC_INT_TCOM); ++} ++ ++static int MDev_GMAC_TX_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct GMAC_private *LocPtr = container_of(napi, struct GMAC_private, napi_tx); ++ struct net_device *dev = LocPtr->dev; ++ unsigned long flags = 0; ++ int work_done = 0; ++ int count = 0; ++ ++ //GMAC_DBG("MDev_GMAC_TX_napi_poll, budget = %d\n", budget); ++ ++ while(work_done < budget) ++ { ++ //GMAC_DBG("work_done = %d, count = %d\n", work_done, count); ++ ++ if((count = MDev_GMAC_TX_Free_sk_buff(dev, work_done)) == 0) ++ break; ++ ++ work_done += count; ++ } ++ ++ /* If budget not fully consumed, exit the polling mode */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ // enable MAC interrupt ++ spin_lock_irqsave(&LocPtr->irq_lock, flags); ++ MDEV_GMAC_ENABLE_TX_REG(); ++ spin_unlock_irqrestore(&LocPtr->irq_lock, flags); ++ } ++ else ++ { ++// GMAC_DBG("TX Over Budget!!! \n"); ++ } ++ ++ return work_done; ++} ++#endif ++ ++#ifdef TX_COM_ENABLE ++irqreturn_t MDev_GMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 intstatus=0; ++ u32 delay_int_status=0; ++ unsigned long flags; ++#ifdef TX_SOFTWARE_QUEUE ++ int txIdleCount=0;//MDev_EMAC_GetTXFIFOIdle(); ++#endif ++ ++#ifndef RX_ZERO_COPY ++ u32 wp = 0; ++#endif ++ ++ spin_lock_irqsave(&LocPtr->irq_lock, flags); ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ delay_int_status = MHal_GMAC_Read_Delay_interrupt_status(); ++ intstatus = MHal_GMAC_Read_ISR() & (~(MHal_GMAC_Read_IMR())) & GMAC_INT_MASK; ++ ++#ifndef RX_ZERO_COPY ++ wp = MHal_GMAC_Read_Network_config_register2() & 0x00100000UL; ++ if(wp) ++ { ++ GMAC_DBG("GMAC HW write invalid address"); ++ } ++#endif ++ ++ //while((delay_int_status & 0x8000UL) || (intstatus = (MHal_GMAC_Read_ISR() & ~MHal_GMAC_Read_IMR() & GMAC_INT_MASK )) ) ++ { ++ if (intstatus & GMAC_INT_RBNA) ++ { ++ GMAC_DBG("RBNA!!!!\n"); ++ LocPtr->stats.rx_dropped ++; ++ //LocPtr->ThisUVE.flagRBNA = 1; ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_BNA); ++ } ++ ++ // Transmit complete // ++ if (intstatus & GMAC_INT_TCOM) ++ { ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (GMAC_INT_TUND | GMAC_INT_RTRY)) ++ { ++ LocPtr->stats.tx_errors += 1; ++ if(intstatus & GMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_GMAC_Write_TSR(GMAC_UND); ++ ++ //Reset TX engine ++ MDev_GMAC_TxReset(); ++ GMAC_DBG ("Transmit TUND error, TX reset\n"); ++ } ++ } ++ ++ #ifdef TX_DESC_MODE ++ #ifdef TX_NAPI ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ if (napi_schedule_prep(&LocPtr->napi_tx)) { ++ MDEV_GMAC_DISABLE_TX_REG(); ++ __napi_schedule(&LocPtr->napi_tx); ++ } ++ #else ++ MDev_GMAC_TX_Free_sk_buff(dev, 0); ++ #endif ++ if (((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev) && (LocPtr->tx_desc_queued_number < TX_DESC_REFILL_NUMBER)); ++ netif_wake_queue(dev); ++ #elif defined(TX_SOFTWARE_QUEUE) ++ if (((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ netif_wake_queue(dev); ++ LocPtr->tx_irqcnt++; ++ txIdleCount=MDev_GMAC_GetTXFIFOIdle(); ++ while(txIdleCount>0 && (LocPtr->tx_rdidx != LocPtr->tx_wridx)) ++ { ++ ++ _MDev_GMAC_tx_clear_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_IRQ); ++ _MDev_GMAC_tx_read_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_IRQ); ++ txIdleCount=MDev_GMAC_GetTXFIFOIdle(); ++ } ++ #else ++ if (((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ netif_wake_queue(dev); ++ #endif ++ } ++ ++ if(intstatus&GMAC_INT_DONE) ++ { ++ LocPtr->ThisUVE.flagISR_INT_DONE = 0x01UL; ++ } ++ ++ //RX Overrun // ++ if(intstatus & GMAC_INT_ROVR) ++ { ++ GMAC_DBG("ROVR!!!!\n"); ++ LocPtr->stats.rx_dropped++; ++ LocPtr->ROVR_count++; ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_RSROVR); ++ ++#ifdef GMAC_ROVR_SW_RESET ++ if (LocPtr->ROVR_count >= 6) ++ { ++ MDev_GMAC_SwReset(dev); ++ } ++#endif ++ } ++ else ++ { ++ LocPtr->ROVR_count = 0; ++ } ++ ++ // Receive complete // ++ if(delay_int_status & 0x8000UL) ++ { ++ #ifdef RX_NAPI ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ if (napi_schedule_prep(&LocPtr->napi_rx)) { ++ MDEV_GMAC_DISABLE_RX_REG(); ++ __napi_schedule(&LocPtr->napi_rx); ++ } ++ #else ++ MDev_GMAC_rx(dev); ++ #endif ++ } ++ //delay_int_status = MHal_GMAC_Read_Delay_interrupt_status(); ++ } ++ spin_unlock_irqrestore(&LocPtr->irq_lock, flags); ++ return IRQ_HANDLED; ++} ++#else ++irqreturn_t MDev_GMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 intstatus = 0; ++ u32 delay_int_status = 0; ++ unsigned long flags; ++#ifdef TX_SOFTWARE_QUEUE ++ int txIdleCount=0;//MDev_EMAC_GetTXFIFOIdle(); ++#endif ++ ++#ifndef RX_ZERO_COPY ++ u32 wp = 0; ++#endif ++ ++ spin_lock_irqsave(&LocPtr->irq_lock, flags); ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ delay_int_status = MHal_GMAC_Read_Delay_interrupt_status(); ++ intstatus = MHal_GMAC_Read_ISR() & (~(MHal_GMAC_Read_IMR())) & GMAC_INT_MASK; ++ ++#ifndef RX_ZERO_COPY ++ wp = MHal_GMAC_Read_Network_config_register2() & 0x00100000UL; ++ if(wp) ++ { ++ GMAC_DBG("GMAC HW write invalid address"); ++ } ++#endif ++ ++ //while((delay_int_status & 0x8000UL) || (intstatus = (MHal_GMAC_Read_ISR() & ~MHal_GMAC_Read_IMR() & GMAC_INT_MASK )) ) ++ { ++ if (((LocPtr->ep_flag&GMAC_EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ { ++ netif_wake_queue(dev); ++ } ++ ++ if (intstatus & GMAC_INT_RBNA) ++ { ++ GMAC_DBG("RBNA!!!!\n"); ++ LocPtr->stats.rx_dropped ++; ++ //LocPtr->ThisUVE.flagRBNA = 1; ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_BNA); ++#ifdef RX_NAPI ++ if (napi_schedule_prep(&LocPtr->napi_rx)) { ++ MDEV_GMAC_DISABLE_RX_REG(); ++ __napi_schedule(&LocPtr->napi_rx); ++ } ++#else ++ MDEV_GMAC_DISABLE_RX_REG(); ++ MDev_GMAC_rx(dev); ++ MHal_GMAC_Write_RSR(GMAC_BNA); ++ MDEV_GMAC_ENABLE_RX_REG(); ++#endif ++ } ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (GMAC_INT_TUND | GMAC_INT_RTRY)) ++ { ++ LocPtr->stats.tx_errors += 1; ++ ++ if(intstatus & GMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_GMAC_Write_TSR(GMAC_UND); ++ ++ //Reset TX engine ++ MDev_GMAC_TxReset(); ++ GMAC_DBG ("Transmit TUND error, TX reset\n"); ++ } ++ else ++ { ++ GMAC_DBG("GMAC_INT_RTRY!!!!\n"); ++ } ++ } ++ ++ if(intstatus&GMAC_INT_DONE) ++ { ++ LocPtr->ThisUVE.flagISR_INT_DONE = 0x01UL; ++ } ++ ++ //RX Overrun // ++ if(intstatus & GMAC_INT_ROVR) ++ { ++ GMAC_DBG("ROVR!!!!\n"); ++ LocPtr->stats.rx_dropped++; ++ LocPtr->ROVR_count++; ++ //write 1 clear ++ MHal_GMAC_Write_RSR(GMAC_RSROVR); ++#ifdef GMAC_ROVR_SW_RESET ++ if (LocPtr->ROVR_count >= 6) ++ { ++ MDev_GMAC_SwReset(dev); ++ } ++#endif ++ } ++ else ++ { ++ LocPtr->ROVR_count = 0; ++ } ++ ++ // Receive complete // ++ if(delay_int_status & 0x8000UL) ++ { ++ //MDev_GMAC_TX_Free_sk_buff(dev, 0); ++ #ifdef RX_NAPI ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ if (napi_schedule_prep(&LocPtr->napi_rx)) { ++ MDEV_GMAC_DISABLE_RX_REG(); ++ __napi_schedule(&LocPtr->napi_rx); ++ } ++ #else ++ MDEV_GMAC_DISABLE_RX_REG(); ++ MDev_GMAC_rx(dev); ++ MDEV_GMAC_ENABLE_RX_REG(); ++ #endif ++ } ++ //delay_int_status = MHal_GMAC_Read_Delay_interrupt_status(); ++ } ++ spin_unlock_irqrestore(&LocPtr->irq_lock, flags); ++ return IRQ_HANDLED; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++// GMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_ScanPhyAddr(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ unsigned char addr = 1; // because address 0 = broadcast, RTL8211E will reply to broadcast addr ++ u32 value = 0; ++ ++ ++ //MHal_GMAC_enable_mdi(); ++ do ++ { ++ value = 0; ++ MHal_GMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ GMAC_DBG("[ PHY Addr ] ==> :%u BMSR = %04x\n", addr, value); ++ if(LocPtr->padmux_type != GMAC1_EPHY) //Extenal phy ++ { ++ u32 value1 = 0,value2 = 0; ++ MHal_GMAC_read_phy(addr, MII_PHYSID1, &value1); ++ MHal_GMAC_read_phy(addr, MII_PHYSID2, &value2); ++ GMAC_DBG("[ PHY ID ]: 0x%04x 0x%04x\n", (unsigned short)value1, (unsigned short)value2); ++ } ++ break; ++ } ++ }while(++addr && addr < 32); ++ ++ LocPtr->phyaddr = addr; ++ ++ if (LocPtr->phyaddr >= 32) ++ { ++ addr = 0; ++ MHal_GMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ GMAC_DBG("[ PHY Addr ] ==> :%u BMSR = %08x\n", addr, value); ++ LocPtr->phyaddr = 0; ++ } ++ else ++ { ++ GMAC_DBG("Wrong PHY Addr, maybe MoCA?\n"); ++ LocPtr->phyaddr = 32; ++ } ++ } ++ ++ //MHal_GMAC_disable_mdi(); ++ return 0; ++} ++/* ++static void Rtl_Patch(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 val; ++ ++ MHal_GMAC_read_phy(LocPtr->phyaddr, 25, &val); ++ MHal_GMAC_write_phy(LocPtr->phyaddr, 25, 0x400UL); ++ MHal_GMAC_read_phy(LocPtr->phyaddr, 25, &val); ++} ++ ++static void MDev_GMAC_Patch_PHY(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 val; ++ ++ MHal_GMAC_read_phy(LocPtr->phyaddr, 2, &val); ++ if (GMAC_RTL_8210 == val) ++ Rtl_Patch(dev); ++}*/ ++ ++static u32 MDev_GMAC_HW_Reg_init(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr = (struct GMAC_private*) netdev_priv(dev); ++ u32 word_ETH_CFG; ++ u32 word_ETH_CTL; ++ u32 config3_Value = 0; ++ u32 config2_Value = 0; ++ u32 uNegPhyVal = 0; ++#ifdef HW_TX_CHECKSUM ++ u32 config4_Value = 0; ++#endif ++#ifdef CONFIG_MSTAR_GMAC_JUMBO_PACKET ++ u32 config5_Value = 0; ++#endif ++ ++ if (!LocPtr->ThisUVE.initedGMAC) ++ { ++ MHal_GMAC_Power_On_Clk(); ++ if((LocPtr->padmux_type==GMAC0_RMII_EXT_EPHY) || (LocPtr->padmux_type==GMAC1_RMII_EXT_EPHY)) ++ config2_Value = CONFIG2_VAL|GMAC_RMII_12|GMAC_RMII; ++ else ++ config2_Value = CONFIG2_VAL; ++ ++ ++ MHal_GMAC_Write_Network_config_register2(config2_Value); ++ ++ LocPtr->phyaddr = MHal_GMAC_PHY_ADDR(); ++ ++ if(LocPtr->phyaddr==0) ++ { ++ if (MDev_GMAC_ScanPhyAddr(dev) < 0) ++ return -1; ++ } ++ ++ //MDev_GMAC_Patch_PHY(dev); ++ } ++ ++#ifdef RX_DELAY_INTERRUPT ++ config3_Value = DELAY_INTERRUPT_CONFIG;//0xFF050080; ++#endif ++ ++#ifdef GMAC_RX_CHECKSUM ++ config3_Value = config3_Value | GMAC_RX_CHECKSUM_ENABLE; ++#endif ++ ++#ifdef RX_DESC_MODE ++ config3_Value = config3_Value | GMAC_SOFTWARE_DESCRIPTOR_ENABLE; ++#endif ++ ++#ifdef HW_TX_CHECKSUM ++ dev->features |= NETIF_F_IP_CSUM; ++ config3_Value = config3_Value | GMAC_TX_CHECKSUM_ENABLE; ++#endif ++ ++ MHal_GMAC_Write_Network_config_register3(config3_Value); ++ ++#ifdef HW_TX_CHECKSUM ++ dev->features |= NETIF_F_IPV6_CSUM; ++ config4_Value = MHal_GMAC_Read_Network_config_register4() | GMAC_TX_V6_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_Network_config_register4(config4_Value); ++#endif ++ ++#ifdef CONFIG_MSTAR_GMAC_JUMBO_PACKET ++ config5_Value = MHal_GMAC_Read_Network_config_register5() | GMAC_TX_CHECKSUM_ENABLE; ++ config5_Value &= 0xffff0000UL; ++ config5_Value |= GMAC_TX_JUMBO_FRAME_ENABLE; ++ MHal_GMAC_Write_Network_config_register5(config5_Value); ++#endif ++ ++#ifdef NEW_TX_QUEUE ++ MHal_GMAC_New_TX_QUEUE_Enable(); ++ MHal_GMAC_New_TX_QUEUE_Threshold_Set(TX_BUFF_ENTRY_NUMBER); ++#endif /* NEW_TX_QUEUE */ ++ ++ if(!(LocPtr->ep_flag & GMAC_EP_FLAG_SUSPENDING)) ++ MDev_GMAC_get_mac_address (dev); // Get ethernet address and store it in dev->dev_addr // ++ ++ MDev_GMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ ++ if (!LocPtr->ThisUVE.initedGMAC) ++ { ++ MHal_GMAC_write_phy(LocPtr->phyaddr, MII_BMCR, 0x1000UL); ++ // IMPORTANT: Run NegotiationPHY() before writing REG_ETH_CFG. ++ uNegPhyVal = MHal_GMAC_NegotiationPHY( LocPtr->phyaddr ); ++ if(uNegPhyVal == 0x01UL) ++ { ++ LocPtr->ThisUVE.flagMacTxPermit = 0x01UL; ++ LocPtr->ThisBCE.duplex = 1; ++ ++ } ++ else if(uNegPhyVal == 0x02UL) ++ { ++ LocPtr->ThisUVE.flagMacTxPermit = 0x01UL; ++ LocPtr->ThisBCE.duplex = 2; ++ } ++ ++ // ETH_CFG Register ----------------------------------------------------- ++ word_ETH_CFG = 0x00000C00UL; // Init: CLK = 0x3 ++ // (20070808) IMPORTANT: REG_ETH_CFG:bit1(FD), 1:TX will halt running RX frame, 0:TX will not halt running RX frame. ++ // If always set FD=0, no CRC error will occur. But throughput maybe need re-evaluate. ++ // IMPORTANT: (20070809) NO_MANUAL_SET_DUPLEX : The real duplex is returned by "negotiation" ++ if(LocPtr->ThisBCE.speed == GMAC_SPEED_100) word_ETH_CFG |= 0x00000001UL; ++ if(LocPtr->ThisBCE.duplex == 2) word_ETH_CFG |= 0x00000002UL; ++ if(LocPtr->ThisBCE.cam == 1) word_ETH_CFG |= 0x00000200UL; ++ if(LocPtr->ThisBCE.rcv_bcast == 0) word_ETH_CFG |= 0x00000020UL; ++ if(LocPtr->ThisBCE.rlf == 1) word_ETH_CFG |= 0x00000100UL; ++ ++ MHal_GMAC_Write_CFG(word_ETH_CFG); ++ // ETH_CTL Register ----------------------------------------------------- ++ ++ if(LocPtr->ThisBCE.wes == 1) ++ { ++ word_ETH_CTL = MHal_GMAC_Read_CTL(); ++ word_ETH_CTL |= 0x00000080UL; ++ MHal_GMAC_Write_CTL(word_ETH_CTL); ++ } ++ ++ LocPtr->ThisUVE.flagPowerOn = 1; ++ LocPtr->ThisUVE.initedGMAC = 1; ++ } ++ ++ MHal_GMAC_HW_init(); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC init Variable ++//------------------------------------------------------------------------------------------------- ++extern phys_addr_t memblock_start_of_DRAM(void); ++extern phys_addr_t memblock_size_of_first_region(void); ++ ++static phys_addr_t MDev_GMAC_MemInit(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ phys_addr_t *alloRAM_VA_BASE; ++ MSYS_DMEM_INFO mem_info; ++ int ret=0; ++ ++/* get_boot_mem_info(GMAC_MEM, &alloRAM_PA_BASE, &alloRAM_SIZE); ++ ++#if defined (CONFIG_ARM64) ++ // get gmac addr only from mboot ++ //alloRAM_PA_BASE = memblock_start_of_DRAM() + memblock_size_of_first_region(); ++#endif ++ alloRAM_VA_BASE = (phys_addr_t *)ioremap(alloRAM_PA_BASE, alloRAM_SIZE); //map buncing buffer from PA to VA ++*/ ++ //alloRAM_SIZE = (sizeof(struct GMAC_private)+ 0x3FFFUL) & ~0x3FFFUL; ++ alloRAM_SIZE = 0; ++ alloRAM_SIZE += RX_DESC_TABLE_SIZE; ++#ifndef RX_ZERO_COPY ++ alloRAM_SIZE += RX_BUFF_SIZE; ++#endif ++#ifdef TX_DESC_MODE ++ alloRAM_SIZE += TX_LOW_PRI_DESC_TABLE_SIZE; ++#else ++ alloRAM_SIZE += TX_BUFF_ENTRY_NUMBER*TX_BUFF_ENTRY_SIZE; ++#endif ++ ++ ++ mem_info.length = alloRAM_SIZE; ++ strcpy(mem_info.name, "GMAC_BUFF"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ panic("unable to locate DMEM for EMAC alloRAM!! error=%d\n",ret); ++ } ++ alloRAM_PA_BASE = mem_info.phys; ++ alloRAM_VA_BASE = (phys_addr_t *)((size_t)mem_info.kvirt); ++ ++ //GMAC_DBG("alloRAM_VA_BASE = 0x%zx\n", (size_t)alloRAM_VA_BASE); ++ //GMAC_DBG("alloRAM_PA_BASE= 0x%zx\n", (size_t)alloRAM_PA_BASE); ++ //GMAC_DBG("alloRAM_SIZE= 0x%zx\n", (size_t)alloRAM_SIZE); ++ BUG_ON(!alloRAM_VA_BASE); ++ ++ memset((phys_addr_t *)alloRAM_VA_BASE,0x00UL,alloRAM_SIZE); ++ ++ //LocPtr->RAM_VA_BASE = ((phys_addr_t)alloRAM_VA_BASE + sizeof(struct GMAC_private) + 0x3FFFUL) & ~0x3FFFUL; // IMPORTANT: Let lowest 14 bits as zero. ++ //LocPtr->RAM_PA_BASE = ((phys_addr_t)alloRAM_PA_BASE + sizeof(struct GMAC_private) + 0x3FFFUL) & ~0x3FFFUL; // IMPORTANT: Let lowest 14 bits as zero. ++ LocPtr->RAM_VA_BASE = (phys_addr_t)alloRAM_VA_BASE; ++ LocPtr->RAM_PA_BASE = (phys_addr_t)alloRAM_PA_BASE; ++ LocPtr->RAM_VA_PA_OFFSET = LocPtr->RAM_VA_BASE - LocPtr->RAM_PA_BASE; // IMPORTANT_TRICK_20070512 ++ LocPtr->RX_DESC_BASE = LocPtr->RAM_PA_BASE; ++#ifndef RX_ZERO_COPY ++ LocPtr->RX_BUFFER_BASE = LocPtr->RAM_PA_BASE + RX_DESC_TABLE_SIZE; ++ #ifdef TX_DESC_MODE ++ LocPtr->TX_LP_DESC_BASE = ((LocPtr->RAM_PA_BASE + RX_DESC_TABLE_SIZE + RX_BUFF_SIZE) + 0x0FFFUL) & ~0x0FFFUL; ++ LocPtr->TX_BUFFER_BASE = LocPtr->TX_LP_DESC_BASE + TX_LOW_PRI_DESC_TABLE_SIZE; ++ #else ++ LocPtr->TX_BUFFER_BASE = LocPtr->RAM_PA_BASE + (RX_DESC_TABLE_SIZE + RX_BUFF_SIZE); ++ #endif ++#else ++ #ifdef TX_DESC_MODE ++ LocPtr->TX_LP_DESC_BASE = ((LocPtr->RAM_PA_BASE + RX_DESC_TABLE_SIZE) + 0x0FFFUL) & ~0x0FFFUL; ++ LocPtr->TX_BUFFER_BASE = LocPtr->TX_LP_DESC_BASE + TX_LOW_PRI_DESC_TABLE_SIZE; ++ #else ++ LocPtr->TX_BUFFER_BASE = LocPtr->RAM_PA_BASE + RX_DESC_TABLE_SIZE; ++ #endif ++#endif ++ ++ //GMAC_DBG("RAM_VA_BASE = 0x%zx\n", (size_t)LocPtr->RAM_VA_BASE); ++ //GMAC_DBG("RAM_PA_BASE = 0x%zx\n", (size_t)LocPtr->RAM_PA_BASE); ++ //GMAC_DBG("RAM_VA_PA_OFFSET = 0x%zx\n", (size_t)LocPtr->RAM_VA_PA_OFFSET); ++ GMAC_DBG("RX_DESC_BASE = 0x%zx, size = 0x%zx\n", (size_t)LocPtr->RX_DESC_BASE, (size_t)RX_DESC_TABLE_SIZE); ++#ifndef RX_ZERO_COPY ++ GMAC_DBG("RX_BUFFER_BASE = 0x%zx, size = 0x%zx\n", (size_t)LocPtr->RX_BUFFER_BASE, (size_t)RX_BUFF_SIZE); ++#endif ++#ifdef TX_DESC_MODE ++ GMAC_DBG("TX_LP_DESC_BASE = 0x%zx, size = 0x%zx\n", (size_t)LocPtr->TX_LP_DESC_BASE, (size_t)TX_LOW_PRI_DESC_TABLE_SIZE); ++#endif ++ GMAC_DBG("TX_BUFFER_BASE = 0x%zx, size = 0x%zx\n", (size_t)LocPtr->TX_BUFFER_BASE, (size_t)(TX_BUFF_ENTRY_NUMBER*TX_BUFF_ENTRY_SIZE)); ++ ++#ifdef RX_DESC_MODE ++ LocPtr->rx_desc_list = (struct rx_descriptor *)(LocPtr->RX_DESC_BASE + LocPtr->RAM_VA_PA_OFFSET); ++#endif ++ ++#ifdef TX_DESC_MODE ++ LocPtr->tx_desc_list = (struct tx_descriptor *)(LocPtr->TX_LP_DESC_BASE + LocPtr->RAM_VA_PA_OFFSET); ++#endif ++ ++#ifndef RX_ZERO_COPY ++ MDev_GMAC_RX_DESC_Init_memcpy(dev); ++#endif ++ ++ memset(&LocPtr->ThisBCE,0x00UL,sizeof(BasicConfigGMAC)); ++ memset(&LocPtr->ThisUVE,0x00UL,sizeof(UtilityVarsGMAC)); ++ ++ LocPtr->ThisBCE.wes = 0; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ LocPtr->ThisBCE.duplex = 2; // 1:Half-duplex, 2:Full-duplex ++ LocPtr->ThisBCE.cam = 0; // 0:No CAM, 1:Yes ++ LocPtr->ThisBCE.rlf = 0; // 0:No, 1:Yes receive long frame(1522) ++ LocPtr->ThisBCE.rcv_bcast = 1; ++ LocPtr->ThisBCE.speed = GMAC_SPEED_100; ++ LocPtr->ThisBCE.connected = 0; ++ return (phys_addr_t)alloRAM_VA_BASE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Initialize the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++static const struct net_device_ops mstar_lan_netdev_ops = { ++ .ndo_open = MDev_GMAC_open, ++ .ndo_stop = MDev_GMAC_close, ++ .ndo_start_xmit = MDev_GMAC_tx, ++ .ndo_set_mac_address = MDev_GMAC_set_mac_address, ++ .ndo_set_rx_mode = MDev_GMAC_set_rx_mode, ++ .ndo_do_ioctl = MDev_GMAC_ioctl, ++ .ndo_get_stats = MDev_GMAC_stats, ++}; ++ ++static int MDev_GMAC_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++#ifdef CONFIG_GMAC_EPHY_LPA_FORCE_SPEED ++ u32 bmsr, bmcr, lpa, adv, neg; ++ u32 lpa1000, ctrl1000; ++#endif ++ ++ mii_ethtool_gset (&LocPtr->mii, cmd); ++ ++#ifdef CONFIG_GMAC_EPHY_LPA_FORCE_SPEED ++ if (cmd->autoneg == AUTONEG_ENABLE) { ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_BMSR, &bmsr); ++ if (bmsr & BMSR_ANEGCOMPLETE) { ++ /* For Link Parterner adopts force mode and EPHY used, ++ * EPHY LPA reveals all zero value. ++ * EPHY would be forced to Full-Duplex mode. ++ */ ++ if (cmd->lp_advertising == 0) { ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_BMCR, &bmcr); ++ ++ if(LocPtr->hardware_type == GMAC_GPHY) ++ { ++ if (bmcr & BMCR_SPEED1000) ++ lpa1000 = LPA_1000FULL; ++ ++ if (bmcr & BMCR_SPEED100) ++ lpa = LPA_100FULL; ++ else ++ lpa = LPA_10FULL; ++ ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_ADVERTISE, &adv); ++ neg = adv & lpa; ++ ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_CTRL1000, &ctrl1000); ++ ++ if((lpa1000 & LPA_1000FULL) && (ctrl1000 & ADVERTISE_1000FULL)) ++ { ++ ethtool_cmd_speed_set(cmd, SPEED_1000); ++ } ++ else ++ { ++ if (neg & LPA_100FULL) ++ { ++ ethtool_cmd_speed_set(cmd, SPEED_100); ++ } ++ else ++ { ++ ethtool_cmd_speed_set(cmd, SPEED_10); ++ } ++ } ++ } ++ else ++ { ++ if (bmcr & BMCR_SPEED100) ++ lpa = LPA_100FULL; ++ else ++ lpa = LPA_10FULL; ++ ++ MHal_GMAC_read_phy(LocPtr->phyaddr, MII_ADVERTISE, &adv); ++ neg = adv & lpa; ++ ++ if (neg & LPA_100FULL) ++ { ++ ethtool_cmd_speed_set(cmd, SPEED_100); ++ } ++ else ++ { ++ ethtool_cmd_speed_set(cmd, SPEED_10); ++ } ++ } ++ cmd->duplex = 0x01; ++ LocPtr->mii.full_duplex = cmd->duplex; ++ } ++ } ++ } ++#endif /* CONFIG_GMAC_EPHY_LPA_FORCE_SPEED */ ++ ++ return 0; ++} ++ ++static int MDev_GMAC_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ ++ mii_ethtool_sset (&LocPtr->mii, cmd); ++ ++ return 0; ++} ++ ++static int MDev_GMAC_nway_reset(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ ++ mii_nway_restart (&LocPtr->mii); ++ ++ return 0; ++} ++ ++static u32 MDev_GMAC_get_link(struct net_device *dev) ++{ ++ u32 u32data; ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ ++ u32data = mii_link_ok (&LocPtr->mii); ++ ++ return u32data; ++} ++ ++static void MDev_GMAC_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) ++{ ++ strlcpy(info->driver, GMAC_DRVNAME, sizeof(info->driver)); ++ strlcpy(info->version, GMAC_DRV_VERSION, sizeof(info->version)); ++ ++ return; ++} ++ ++#define GMAC_STATS_STRING_LEN 23 ++ ++static char mstar_gmac_string[GMAC_STATS_STRING_LEN][ETH_GSTRING_LEN]= ++{ ++ {"rx_packets"}, ++ {"rx_bytes"}, ++ {"rx_errors"}, ++ {"rx_dropped"}, ++ {"rx_length_errors"}, ++ {"rx_over_errors"}, ++ {"rx_crc_errors"}, ++ {"rx_frame_errors"}, ++ {"rx_fifo_errors"}, ++ {"rx_missed_errors"}, ++ {"rx_compressed"}, ++ {"tx_packets"}, ++ {"tx_bytes"}, ++ {"tx_errors"}, ++ {"tx_dropped"}, ++ {"tx_aborted_errors"}, ++ {"tx_carrier_errors"}, ++ {"tx_fifo_errors"}, ++ {"tx_heartbeat_errors"}, ++ {"tx_window_errors"}, ++ {"tx_compressed"}, ++ {"multicast"}, ++ {"collisions"} ++}; ++ ++static u64 *mstar_gmac_stats[GMAC_STATS_STRING_LEN]; //Read only, don't write ++ ++static void MDev_GMAC_ethtool_stats_init(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ ++ mstar_gmac_stats[0] = (u64 *)&LocPtr->stats.rx_packets; ++ mstar_gmac_stats[1] = (u64 *)&LocPtr->stats.rx_bytes; ++ mstar_gmac_stats[2] = (u64 *)&LocPtr->stats.rx_errors; ++ mstar_gmac_stats[3] = (u64 *)&LocPtr->stats.rx_dropped; ++ mstar_gmac_stats[4] = (u64 *)&LocPtr->stats.rx_length_errors; ++ mstar_gmac_stats[5] = (u64 *)&LocPtr->stats.rx_over_errors; ++ mstar_gmac_stats[6] = (u64 *)&LocPtr->stats.rx_crc_errors; ++ mstar_gmac_stats[7] = (u64 *)&LocPtr->stats.rx_frame_errors; ++ mstar_gmac_stats[8] = (u64 *)&LocPtr->stats.rx_fifo_errors; ++ mstar_gmac_stats[9] = (u64 *)&LocPtr->stats.rx_missed_errors; ++ mstar_gmac_stats[10] = (u64 *)&LocPtr->stats.rx_compressed; ++ mstar_gmac_stats[11] = (u64 *)&LocPtr->stats.tx_packets; ++ mstar_gmac_stats[12] = (u64 *)&LocPtr->stats.tx_bytes; ++ mstar_gmac_stats[13] = (u64 *)&LocPtr->stats.tx_errors; ++ mstar_gmac_stats[14] = (u64 *)&LocPtr->stats.tx_dropped; ++ mstar_gmac_stats[15] = (u64 *)&LocPtr->stats.tx_aborted_errors; ++ mstar_gmac_stats[16] = (u64 *)&LocPtr->stats.tx_carrier_errors; ++ mstar_gmac_stats[17] = (u64 *)&LocPtr->stats.tx_fifo_errors; ++ mstar_gmac_stats[18] = (u64 *)&LocPtr->stats.tx_heartbeat_errors; ++ mstar_gmac_stats[19] = (u64 *)&LocPtr->stats.tx_window_errors; ++ mstar_gmac_stats[20] = (u64 *)&LocPtr->stats.tx_compressed; ++ mstar_gmac_stats[21] = (u64 *)&LocPtr->stats.multicast; ++ mstar_gmac_stats[22] = (u64 *)&LocPtr->stats.collisions; ++ ++} ++ ++static void MDev_GMAC_get_strings(struct net_device *dev, u32 stringset, u8 *data) ++{ ++ char *p = (char *)data; ++ unsigned int i; ++ ++ for (i = 0; i < GMAC_STATS_STRING_LEN; i++) ++ { ++ sprintf(p, mstar_gmac_string[i]); ++ p += ETH_GSTRING_LEN; ++ } ++ ++} ++ ++static void MDev_GMAC_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *e_state, u64 *data) ++{ ++ unsigned int i; ++ //GMAC_DBG("MDev_GMAC_get_ethtool_stats\n"); ++ ++ MDev_GMAC_stats(dev); ++ ++ for(i = 0; i < GMAC_STATS_STRING_LEN; i++) ++ { ++ data[i] = *(u32 *)mstar_gmac_stats[i]; ++ } ++} ++ ++static int MDev_GMAC_sset_count(struct net_device *dev, int type) ++{ ++ //GMAC_DBG("MDev_GMAC_sset_count\n"); ++ switch(type) ++ { ++ case ETH_SS_TEST: ++ return GMAC_TEST_STRING_LEN; ++ case ETH_SS_STATS: ++ return GMAC_STATS_STRING_LEN; ++ case ETH_SS_PRIV_FLAGS: ++ return GMAC_PRIV_FLAGS_STRING_LEN; ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++#define GMAC_REGS_LEN 0xC0 ++ ++static int MDev_GMAC_get_regs_len(struct net_device *dev) ++{ ++ return GMAC_REGS_LEN * sizeof(u32); ++} ++ ++static u32 MDev_GMAC_get_regs_transform(u32 reg_data) ++{ ++ return ((reg_data & 0x000000FF) << 8) | ((reg_data & 0x0000FF00) >> 8) | ((reg_data & 0x00FF0000) << 8) | ((reg_data & 0xFF000000) >> 8); ++} ++ ++static void MDev_GMAC_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *data) ++{ ++ u32 *data_32 = data; ++ u32 register_index; ++ u32 address_counter; ++ ++ register_index = 0; ++ address_counter = 0; ++ ++ while(register_index < 0x40) ++ { ++ data_32[register_index] = MDev_GMAC_get_regs_transform(MHal_GMAC_ReadReg32(0x4UL * address_counter)); ++ register_index++; ++ address_counter++; ++ } ++ ++ address_counter = 0; ++ ++ while(register_index < 0x80) ++ { ++ data_32[register_index] = MDev_GMAC_get_regs_transform(MHal_GMAC_ReadReg32(0x4UL * address_counter + 0x100UL)); ++ register_index++; ++ address_counter++; ++ } ++ ++ address_counter = 0; ++ ++ while(register_index < 0xC0) ++ { ++ data_32[register_index] = MDev_GMAC_get_regs_transform(MHal_GMAC_ReadReg32(0x4UL * address_counter + 0x400UL)); ++ register_index++; ++ address_counter++; ++ } ++ ++} ++ ++static int MDev_GMAC_get_coalesce(struct net_device *dev, struct ethtool_coalesce *e_coalesce) ++{ ++#ifdef RX_NAPI ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++#endif ++ u32 register_config; ++ ++ register_config = MHal_GMAC_Read_Network_config_register3(); ++ ++ e_coalesce->rx_coalesce_usecs = (register_config & (~GMAC_INT_DELAY_TIME_MASK)) >> GMAC_INT_DELAY_TIME_SHIFT; ++ e_coalesce->rx_max_coalesced_frames = (register_config & (~GMAC_INT_DELAY_NUMBER_MASK)) >> GMAC_INT_DELAY_NUMBER_SHIFT; ++#ifdef RX_NAPI ++ e_coalesce->rx_max_coalesced_frames_irq = LocPtr->napi_rx.weight; ++#endif ++ e_coalesce->use_adaptive_rx_coalesce = true; ++ ++ return 0; ++} ++ ++static int MDev_GMAC_set_coalesce(struct net_device *dev, struct ethtool_coalesce *e_coalesce) ++{ ++#ifdef RX_NAPI ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++#endif ++ u32 register_config; ++ ++ if(e_coalesce->rx_coalesce_usecs > 0xFF) ++ return -EINVAL; ++ if(e_coalesce->rx_max_coalesced_frames > 0xFF) ++ return -EINVAL; ++ if(e_coalesce->rx_max_coalesced_frames_irq > 0x40) ++ return -EINVAL; ++ ++ register_config = MHal_GMAC_Read_Network_config_register3(); ++ register_config = register_config & GMAC_INT_DELAY_TIME_MASK & GMAC_INT_DELAY_NUMBER_MASK; ++ register_config = register_config | e_coalesce->rx_coalesce_usecs << GMAC_INT_DELAY_TIME_SHIFT; ++ register_config = register_config | e_coalesce->rx_max_coalesced_frames << GMAC_INT_DELAY_NUMBER_SHIFT; ++ MHal_GMAC_Write_Network_config_register3(register_config); ++ ++#ifdef RX_NAPI ++ LocPtr->napi_rx.weight = e_coalesce->rx_max_coalesced_frames_irq; ++#endif ++ ++ return 0; ++} ++ ++static void MDev_GMAC_get_ringparam(struct net_device *dev, struct ethtool_ringparam *e_ringparam) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ ++ e_ringparam->rx_max_pending = RX_DESC_NUMBER; ++ e_ringparam->tx_max_pending = TX_BUFF_ENTRY_NUMBER; ++ e_ringparam->rx_pending = LocPtr->rx_ring_entry_number; ++ e_ringparam->tx_pending = LocPtr->tx_ring_entry_number; ++ ++ return; ++} ++ ++//static int MDev_GMAC_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e_ringparam) ++//{ ++// struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++// ++// if(e_ringparam->rx_pending > RX_DESC_NUMBER) ++// return -EINVAL; ++// if(e_ringparam->tx_pending > TX_BUFF_ENTRY_NUMBER) ++// return -EINVAL; ++// ++// LocPtr->rx_ring_entry_number = e_ringparam->rx_pending; ++// LocPtr->tx_ring_entry_number = e_ringparam->tx_pending; ++// ++// return 0; ++//} ++ ++static u32 MDev_GMAC_get_msglevel(struct net_device *dev) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ return LocPtr->msglvl; ++} ++ ++static void MDev_GMAC_set_msglevel(struct net_device *dev, u32 data) ++{ ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ LocPtr->msglvl = data; ++ return; ++} ++ ++static const struct ethtool_ops mstar_ethtool_ops = { ++ .get_settings = MDev_GMAC_get_settings, ++ .set_settings = MDev_GMAC_set_settings, ++ .nway_reset = MDev_GMAC_nway_reset, ++ .get_link = MDev_GMAC_get_link, ++ .get_drvinfo = MDev_GMAC_get_drvinfo, ++ .get_sset_count = MDev_GMAC_sset_count, ++ .get_ethtool_stats = MDev_GMAC_get_ethtool_stats, ++ .get_strings = MDev_GMAC_get_strings, ++ .get_regs = MDev_GMAC_get_regs, ++ .get_regs_len = MDev_GMAC_get_regs_len, ++ .get_coalesce = MDev_GMAC_get_coalesce, ++ .set_coalesce = MDev_GMAC_set_coalesce, ++ .get_ringparam = MDev_GMAC_get_ringparam, ++ //.set_ringparam = MDev_GMAC_set_ringparam, ++ .get_msglevel = MDev_GMAC_get_msglevel, ++ .set_msglevel = MDev_GMAC_set_msglevel, ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Restar the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++static int MDev_GMAC_SwReset(struct net_device *dev) ++{ ++#if 0 ++ struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ u32 oldCFG, oldCTL; ++ u32 retval; ++ ++ MDev_GMAC_get_mac_address (dev); ++ oldCFG = MHal_GMAC_Read_CFG(); ++ oldCTL = MHal_GMAC_Read_CTL() & ~(GMAC_TE | GMAC_RE); ++ ++ netif_stop_queue (dev); ++ ++ retval = MHal_GMAC_Read_Network_config_register2(); ++ MHal_GMAC_Write_Network_config_register2(retval & 0x00000FFFUL); ++ MHal_GMAC_Write_Network_config_register2(retval); ++ ++ MDev_GMAC_HW_Reg_init(dev); ++ MHal_GMAC_Write_CFG(oldCFG); ++ MHal_GMAC_Write_CTL(oldCTL); ++ MHal_GMAC_enable_mdi (); ++ MDev_GMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ MDev_GMAC_update_linkspeed (dev); ++ MHal_GMAC_Write_IER(GMAC_INT_ENABLE); ++ MDev_GMAC_start (dev); ++ MDev_GMAC_set_rx_mode(dev); ++ netif_start_queue (dev); ++ LocPtr->ROVR_count = 0; ++#ifdef HW_TX_CHECKSUM ++ retval = MHal_GMAC_Read_Network_config_register3() | GMAC_TX_CHECKSUM_ENABLE; ++ MHal_GMAC_Write_Network_config_register3(retval); ++ dev->features |= NETIF_F_IP_CSUM; ++#endif ++ ++#else ++ /* only trigger hw restart */ ++ //struct GMAC_private *LocPtr =(struct GMAC_private *) netdev_priv(dev); ++ u32 uRegVal; ++ ++ /* Disable Receiver and Transmitter */ ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ ++ /* Enable Receive and Transmit */ ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal |= (GMAC_RE | GMAC_TE); ++ MHal_GMAC_Write_CTL(uRegVal); ++#endif ++ ++ return 0; ++} ++ ++#if defined (CONFIG_OF) ++static struct of_device_id mstargmac_of_device_ids[] = { ++ {.compatible = "mstar-gmac"}, ++ {}, ++}; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Detect MAC and PHY and perform initialization ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_timer_callback(unsigned long value) ++{ ++ int ret = 0; ++ struct GMAC_private *LocPtr = (struct GMAC_private *) netdev_priv(gmac_dev); ++ static u32 /*bmsr,*/ time_count = 0; ++ // Normally, time out is set 1 Sec. ++ LocPtr->Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ ++#ifndef RX_DELAY_INTERRUPT ++ if (GMAC_RX_TMR == value) ++ { ++ MHal_GMAC_timer_callback(value); ++ return; ++ } ++#endif ++ ++ spin_lock_irq (&LocPtr->irq_lock); ++ ret = MDev_GMAC_update_linkspeed(gmac_dev); ++ spin_unlock_irq (&LocPtr->irq_lock); ++ if (0 == ret) ++ { ++ if (!LocPtr->ThisBCE.connected) ++ { ++ #ifndef RX_ZERO_COPY ++ MDev_GMAC_RX_DESC_Reset_memcpy(gmac_dev); ++ #endif ++ MDEV_GMAC_ENABLE_RX_REG(); ++ LocPtr->ThisBCE.connected = 1; ++ netif_carrier_on(gmac_dev); ++ } ++ /* ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ time_count = 0; ++ spin_lock_irq (&LocPtr->irq_lock); ++ LocPtr->phy_status_register = bmsr; ++ spin_unlock_irq (&LocPtr->irq_lock); ++ */ ++ } ++ else //no link ++ { ++ if(LocPtr->ThisBCE.connected) { ++ LocPtr->ThisBCE.connected = 0; ++ netif_carrier_off(gmac_dev); ++ } ++ // If disconnected is over 3 Sec, the real value of PHY's status register will report to application. ++ if(time_count > 30) { ++ /* ++ // Link status is latched, so read twice to get current value // ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ MHal_GMAC_read_phy (LocPtr->phyaddr, MII_BMSR, &bmsr); ++ spin_lock_irq (&LocPtr->irq_lock); ++ LocPtr->phy_status_register = bmsr; ++ spin_unlock_irq (&LocPtr->irq_lock); ++ */ ++ // Report to kernel. ++ netif_carrier_off(gmac_dev); ++ LocPtr->ThisBCE.connected = 0; ++ MDEV_GMAC_DISABLE_RX_REG(); ++ } ++ else if(time_count <= 30){ ++ time_count++; ++ // Time out is set 100ms. Quickly checks next phy status. ++ LocPtr->Link_timer.expires = jiffies + (GMAC_CHECK_LINK_TIME / 10); ++ } ++ } ++ ++ add_timer(&LocPtr->Link_timer); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// GMAC MACADDR Setup ++//------------------------------------------------------------------------------------------------- ++ ++#define MACADDR_FORMAT "XX:XX:XX:XX:XX:XX" ++#ifdef CONFIG_MS_GMAC //be used to built-in ++static int __init macaddr_auto_config_setup(char *addrs) ++{ ++ if (strlen(addrs) == strlen(MACADDR_FORMAT) ++ && ':' == addrs[2] ++ && ':' == addrs[5] ++ && ':' == addrs[8] ++ && ':' == addrs[11] ++ && ':' == addrs[14] ++ ) ++ { ++ addrs[2] = '\0'; ++ addrs[5] = '\0'; ++ addrs[8] = '\0'; ++ addrs[11] = '\0'; ++ addrs[14] = '\0'; ++ ++ GMAC_MY_MAC[0] = (u8)simple_strtoul(&(addrs[0]), NULL, 16); ++ GMAC_MY_MAC[1] = (u8)simple_strtoul(&(addrs[3]), NULL, 16); ++ GMAC_MY_MAC[2] = (u8)simple_strtoul(&(addrs[6]), NULL, 16); ++ GMAC_MY_MAC[3] = (u8)simple_strtoul(&(addrs[9]), NULL, 16); ++ GMAC_MY_MAC[4] = (u8)simple_strtoul(&(addrs[12]), NULL, 16); ++ GMAC_MY_MAC[5] = (u8)simple_strtoul(&(addrs[15]), NULL, 16); ++ ++ /* set back to ':' or the environment variable would be destoried */ // REVIEW: this coding style is dangerous ++ addrs[2] = ':'; ++ addrs[5] = ':'; ++ addrs[8] = ':'; ++ addrs[11] = ':'; ++ addrs[14] = ':'; ++ } ++ ++ return 1; ++} ++ ++__setup("macaddr=", macaddr_auto_config_setup); ++#endif ++//------------------------------------------------------------------------------------------------- ++// GMAC init module ++//------------------------------------------------------------------------------------------------- ++int GMAC_PAD_MODE; ++int gIrq_from_dts=0; ++ ++static int MDev_GMAC_init(void) ++{ ++ struct GMAC_private *LocPtr; ++#ifdef RX_ZERO_COPY ++ GMAC_DBG("RX_ZERO_COPY!!!\n"); ++#endif ++#ifdef RX_NAPI ++ GMAC_DBG("RX_NAPI!!!RX_NAPI_WEIGHT = %d\n", GMAC_RX_NAPI_WEIGHT); ++#endif ++#ifdef RX_GRO ++ GMAC_DBG("RX_GRO!!!\n"); ++#endif ++#ifdef RX_DELAY_INTERRUPT ++ GMAC_DBG("DELAY_NUMBER = %d, DELAY_TIME = %d\n", DELAY_NUMBER, DELAY_TIME); ++#endif ++ ++ ++ if(gmac_dev) ++ return -1; ++ ++ gmac_dev = alloc_etherdev(sizeof(*LocPtr)); ++ LocPtr = netdev_priv(gmac_dev); ++ ++ if (gmac_dev == NULL) ++ { ++ GMAC_DBG( KERN_ERR "No GMAC dev mem!\n" ); ++ return -ENOMEM; ++ } ++ ++ if (LocPtr == NULL) ++ { ++ GMAC_DBG("LocPtr fail\n"); ++ return -ENOMEM; ++ } ++ ++#ifdef RX_NAPI ++ netif_napi_add(gmac_dev, &LocPtr->napi_rx, MDev_GMAC_RX_napi_poll, GMAC_RX_NAPI_WEIGHT); ++#endif ++ ++#ifdef TX_NAPI ++ netif_napi_add(gmac_dev, &LocPtr->napi_tx, MDev_GMAC_TX_napi_poll, GMAC_TX_NAPI_WEIGHT); ++#endif ++ ++ if(GMAC_PAD_MODE != 0) ++ { ++ GMAC_DBG("GMAC_PAD_MODE = %d\n", GMAC_PAD_MODE); ++ LocPtr->padmux_type = GMAC_PAD_MODE; ++ } ++ else ++ { ++ GMAC_DBG("GMAC_PAD_MODE not set DEFAULT_PADMUX = %u\n", DEFAULT_PADMUX); ++ LocPtr->padmux_type = DEFAULT_PADMUX; ++ } ++ ++ LocPtr->hardware_type = MHal_GMAC_Hardware_check(LocPtr->padmux_type); ++ LocPtr->dev = gmac_dev; ++ LocPtr->phy_status_register = 0x78c9UL; // 0x78c9: link is down. ++ LocPtr->initstate = 0; ++ LocPtr->phyaddr = 0; ++ spin_lock_init (&LocPtr->irq_lock); ++ spin_lock_init (&LocPtr->tx_lock); ++ ether_setup (gmac_dev); ++ gmac_dev->base_addr = (long) MHal_GMAC_REG_ADDR_BASE(); ++#if 0 //fdef CONFIG_OF ++ gmac_dev->irq = gIrq_from_dts; ++#else ++ gmac_dev->irq = MHal_GMAC_IRQ(); ++#endif ++ gmac_dev->tx_queue_len = GMAC_MAX_TX_QUEUE; ++ gmac_dev->netdev_ops = &mstar_lan_netdev_ops; ++ ++ if( MDev_GMAC_MemInit(gmac_dev) == 0) ++ { ++ GMAC_DBG("Memery init fail!!\n"); ++ goto end; ++ } ++ ++ LocPtr->rx_ring_entry_number = RX_DESC_NUMBER; ++ LocPtr->tx_ring_entry_number = TX_BUFF_ENTRY_NUMBER; ++ ++ if ( MDev_GMAC_HW_Reg_init(gmac_dev) < 0) ++ { ++ GMAC_DBG("Hardware Register init fail!!\n"); ++ goto end; ++ } ++ ++ //Support for ethtool // ++ LocPtr->mii.dev = gmac_dev; ++ LocPtr->mii.mdio_read = MDev_GMAC_mdio_read; ++ LocPtr->mii.mdio_write = MDev_GMAC_mdio_write; ++ LocPtr->mii.phy_id = LocPtr->phyaddr; ++ if(LocPtr->hardware_type == GMAC_GPHY) ++ { ++ LocPtr->mii.supports_gmii = true; ++ } ++ gmac_dev->ethtool_ops = &mstar_ethtool_ops; ++ MDev_GMAC_ethtool_stats_init(gmac_dev); ++ ++ //Install the interrupt handler // ++ //Notes: Modify linux/kernel/irq/manage.c /* interrupt.h */ ++ if (request_irq(gmac_dev->irq, MDev_GMAC_interrupt, 0, gmac_dev->name, gmac_dev)) ++ goto end; ++ ++#if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) && defined(CONFIG_MP_PLATFORM_INT_1_to_1_SPI) ++ irq_set_affinity_hint(gmac_dev->irq, cpu_online_mask); ++ irq_set_affinity(gmac_dev->irq, cpu_online_mask); ++#endif ++ ++ //Determine current link speed // ++ spin_lock_irq (&LocPtr->irq_lock); ++ (void) MDev_GMAC_update_linkspeed (gmac_dev); ++ spin_unlock_irq (&LocPtr->irq_lock); ++ ++ init_timer(&LocPtr->Link_timer); ++ LocPtr->Link_timer.data = GMAC_LINK_TMR; ++ LocPtr->Link_timer.function = MDev_GMAC_timer_callback; ++ LocPtr->Link_timer.expires = jiffies + GMAC_CHECK_LINK_TIME; ++ ++ return register_netdev (gmac_dev); ++ ++end: ++ free_netdev(gmac_dev); ++ gmac_dev = 0; ++ LocPtr->initstate = GMAC_ETHERNET_TEST_INIT_FAIL; ++ GMAC_DBG( KERN_ERR "Init GMAC error!\n" ); ++ return -ENOSYS; ++} ++//------------------------------------------------------------------------------------------------- ++// GMAC exit module ++//------------------------------------------------------------------------------------------------- ++static void MDev_GMAC_exit(void) ++{ ++ if (gmac_dev) ++ { ++ unregister_netdev(gmac_dev); ++ free_netdev(gmac_dev); ++ } ++} ++ ++static int mstar_gmac_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct GMAC_private *LocPtr= (struct GMAC_private*) netdev_priv(netdev); ++ u32 uRegVal; ++ printk(KERN_INFO "mstar_gmac_drv_suspend\n"); ++ ++ if(!netdev) ++ { ++ return -ENODEV; ++ } ++ ++ LocPtr = (struct GMAC_private*) netdev_priv(netdev); ++ LocPtr->ep_flag |= GMAC_EP_FLAG_SUSPENDING; ++ netif_stop_queue (netdev); ++ ++ disable_irq(netdev->irq); ++ del_timer(&LocPtr->Link_timer); ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_GMAC_Read_CTL(); ++ uRegVal &= ~(GMAC_TE | GMAC_RE); ++ MHal_GMAC_Write_CTL(uRegVal); ++ ++ // Disable PHY interrupt // ++ MHal_GMAC_disable_phyirq (); ++#ifndef RX_DELAY_INTERRUPT ++ //Disable MAC interrupts // ++ uRegVal = GMAC_INT_RCOM | GMAC_INT_ENABLE; ++ MHal_GMAC_Write_IDR(uRegVal); ++#else ++ MHal_GMAC_Write_IDR(GMAC_INT_ENABLE); ++#endif ++ MHal_GMAC_Power_Off_Clk(); ++ ++ if(LocPtr->ep_flag & GMAC_EP_FLAG_OPEND) ++ { ++ MDev_GMAC_close(netdev); ++ LocPtr->ep_flag |= GMAC_EP_FLAG_SUSPENDING_OPEND; ++ } ++ ++ return 0; ++} ++static int mstar_gmac_drv_resume(struct platform_device *dev) ++{ ++ struct net_device *netdev = (struct net_device*)dev->dev.platform_data; ++ struct GMAC_private *LocPtr = (struct GMAC_private *) netdev_priv(netdev); ++ ++ printk(KERN_INFO "mstar_gmac_drv_resume\n"); ++ ++ if(!netdev) ++ { ++ return -ENODEV; ++ } ++ ++ MDev_GMAC_HW_Reg_init(netdev); ++ LocPtr->ep_flag &= ~GMAC_EP_FLAG_SUSPENDING; ++ enable_irq(netdev->irq); ++ ++ if(LocPtr->ep_flag & GMAC_EP_FLAG_SUSPENDING_OPEND) ++ { ++ if(0>MDev_GMAC_open(netdev)) ++ { ++ printk(KERN_WARNING "Driver GMAC: open failed after resume\n"); ++ return -ENOSYS; ++ } ++ LocPtr->ep_flag &= ~GMAC_EP_FLAG_SUSPENDING_OPEND; ++ } ++ ++ return 0; ++} ++ ++static ssize_t tx_packet_dump_en_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ int val = simple_strtoul(buf, NULL, 10); ++ if(val) ++ gb_tx_packet_dump_en=1; ++ else ++ gb_tx_packet_dump_en=0; ++ ++ return count; ++} ++static ssize_t tx_packet_dump_en_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "tx_en=%d tx_en=%d\n", gb_tx_packet_dump_en, gb_rx_packet_dump_en); ++} ++DEVICE_ATTR(tx_packet_dump_en, 0644, tx_packet_dump_en_show, tx_packet_dump_en_store); ++ ++static ssize_t rx_packet_dump_en_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ int val = simple_strtoul(buf, NULL, 10); ++ if(val) ++ gb_rx_packet_dump_en=1; ++ else ++ gb_rx_packet_dump_en=0; ++ ++ return count; ++} ++static ssize_t rx_packet_dump_en_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "tx_en=%d tx_en=%d\n", gb_tx_packet_dump_en, gb_rx_packet_dump_en); ++} ++DEVICE_ATTR(rx_packet_dump_en, 0644, rx_packet_dump_en_show, rx_packet_dump_en_store); ++ ++static ssize_t gmac_mdio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int physaddr, reg=0, value=0; ++ ++ physaddr = MHal_GMAC_PHY_ADDR(); ++ str += scnprintf(str, end - str, "%s physaddr:%d\n", gmac_dev->name , physaddr); ++ for(reg=0; reg<32; reg++) ++ { ++ if(reg%8==0) str += scnprintf(str, end - str, "%02d: ", reg); ++ MHal_GMAC_read_phy(physaddr, reg, &value); ++ str += scnprintf(str, end - str, "0x%04x ", value); ++ if(reg%8==7) str += scnprintf(str, end - str, "\n"); ++ } ++ ++ return (str - buf); ++} ++ ++static ssize_t gmac_mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ unsigned int physaddr, reg=0, value=0; ++ unsigned char token[16]; ++ ++ sscanf(buf, "%s", token); ++ if (0 == strcasecmp(token, "r")) ++ { ++ sscanf(buf, "%s %d %d", token, &physaddr, ®); ++ MHal_GMAC_read_phy(physaddr, reg, &value); ++ printk("mdio %s phyaddr:%d reg:%d val:0x%04x\n", token, physaddr, reg, value); ++ } ++ else if (0 == strcasecmp(token, "w")) ++ { ++ sscanf(buf, "%s %d %d 0x%x", token, &physaddr, ®, &value); ++ MHal_GMAC_write_phy(physaddr, reg, value); ++ printk("mdio %s phyaddr:%d reg:%d val:0x%04x\n", token, physaddr, reg, value); ++ } ++ else if (0 == strcasecmp(token, "s")) ++ { ++ MDev_GMAC_ScanPhyAddr(gmac_dev); ++ } ++ else ++ { ++ printk("\nUsage: echo r [phyaddr] [reg] > mdio (r 3 0)\n"); ++ printk("Usage: echo w [phyaddr] [reg] [value_hex] > mdio (w 3 0 0x9140)\n"); ++ } ++ ++ return n; ++} ++DEVICE_ATTR(gmac_mdio, 0644, gmac_mdio_show, gmac_mdio_store); ++ ++static int mstar_gmac_drv_probe(struct platform_device *pdev) ++{ ++ int retval=0; ++ ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-gmac") ++ || pdev->id!=0) ++ { ++ retval = -ENXIO; ++ } ++#ifdef CONFIG_OF ++ gIrq_from_dts = irq_of_parse_and_map(pdev->dev.of_node, 0); ++#endif ++ gdebug_class_gmac_dev = device_create(msys_get_sysfs_class(), NULL, MKDEV(241, 3), NULL, "gmac"); ++ device_create_file(gdebug_class_gmac_dev, &dev_attr_tx_packet_dump_en); ++ device_create_file(gdebug_class_gmac_dev, &dev_attr_rx_packet_dump_en); ++ device_create_file(gdebug_class_gmac_dev, &dev_attr_gmac_mdio); ++ ++ retval = MDev_GMAC_init(); ++ if(!retval) ++ { ++ pdev->dev.platform_data=gmac_dev; ++ } ++ return retval; ++} ++ ++static int mstar_gmac_drv_remove(struct platform_device *pdev) ++{ ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-gmac") ++ || pdev->id!=0) ++ { ++ return -1; ++ } ++ MDev_GMAC_exit(); ++ pdev->dev.platform_data=NULL; ++ return 0; ++} ++ ++static struct platform_driver Mstar_gmac_driver = { ++ .probe = mstar_gmac_drv_probe, ++ .remove = mstar_gmac_drv_remove, ++ .suspend = mstar_gmac_drv_suspend, ++ .resume = mstar_gmac_drv_resume, ++ .driver = { ++ .name = "Mstar-gmac", ++#if defined(CONFIG_OF) ++ .of_match_table = mstargmac_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_gmac_drv_init_module(void) ++{ ++ gmac_dev=NULL; ++ return platform_driver_register(&Mstar_gmac_driver); ++} ++ ++static void __exit mstar_gmac_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_gmac_driver); ++ gmac_dev=NULL; ++ return; ++} ++ ++ ++module_init(mstar_gmac_drv_init_module); ++module_exit(mstar_gmac_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GMAC Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/gmac/mdrv_gmac_v3.h b/drivers/sstar/gmac/mdrv_gmac_v3.h +new file mode 100755 +index 000000000000..dff19c8bb4ab +--- /dev/null ++++ b/drivers/sstar/gmac/mdrv_gmac_v3.h +@@ -0,0 +1,258 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file GMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief GMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h define start ++// ----------------------------------------------------------------------------- ++ ++#ifndef __DRV_GMAC_H_ ++#define __DRV_GMAC_H_ ++ ++#define GMAC_DBG(fmt, args...) {printk("Mstar_gmac: "); printk(fmt, ##args);} ++#define GMAC_INFO {printk("Line:%u\n", __LINE__);} ++#define GMAC_DRVNAME "mstar gmac" ++#define GMAC_DRV_VERSION "3.0.0" ++#define GMAC_TEST_STRING_LEN 0 ++#define GMAC_PRIV_FLAGS_STRING_LEN 0 ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define GMAC_MTU (1518) ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define GMAC_EP_FLAG_OPEND 0X00000001UL ++#define GMAC_EP_FLAG_SUSPENDING 0X00000002UL ++#define GMAC_EP_FLAG_SUSPENDING_OPEND 0X00000004UL ++ ++#define GMAC_ETHERNET_TEST_NO_LINK 0x00000000UL ++#define GMAC_ETHERNET_TEST_AUTO_NEGOTIATION 0x00000001UL ++#define GMAC_ETHERNET_TEST_LINK_SUCCESS 0x00000002UL ++#define GMAC_ETHERNET_TEST_RESET_STATE 0x00000003UL ++#define GMAC_ETHERNET_TEST_SPEED_100M 0x00000004UL ++#define GMAC_ETHERNET_TEST_DUPLEX_FULL 0x00000008UL ++#define GMAC_ETHERNET_TEST_INIT_FAIL 0x00000010UL ++ ++#define GMAC_RX_TMR (0) ++#define GMAC_LINK_TMR (1) ++ ++#define GMAC_CHECK_LINK_TIME (HZ) ++#define GMAC_CHECK_CNT (500000) ++#define GMAC_RTL_8210 (0x1CUL) ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++u8 GMAC_MY_MAC[6] = { 0x00, 0x55, 0x66, 0x00, 0x00, 0x01 }; ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#ifdef TX_DESC_MODE ++struct tx_descriptor ++{ ++ u32 addr; ++ u32 low_tag; ++ u32 reserve0; ++ u32 reserve1; ++}; ++#endif ++ ++#ifdef TX_SOFTWARE_QUEUE ++struct tx_ring ++{ ++ u8 used; ++ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ ++}; ++#endif ++ ++#ifdef RX_DESC_MODE ++struct rx_descriptor ++{ ++ u32 addr; ++ u32 low_tag; ++ u32 high_tag; ++ u32 reserve; ++}; ++#endif ++ ++struct _BasicConfigGMAC ++{ ++ u8 connected; // 0:No, 1:Yes <== (20070515) Wait for Julian's reply ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _BasicConfigGMAC BasicConfigGMAC; ++ ++struct _UtilityVarsGMAC ++{ ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ // Statistics Counters : (accumulated) ++ u32 cntREG_ETH_FRA; ++ u32 cntREG_ETH_SCOL; ++ u32 cntREG_ETH_MCOL; ++ u32 cntREG_ETH_OK; ++ u32 cntREG_ETH_SEQE; ++ u32 cntREG_ETH_ALE; ++ u32 cntREG_ETH_DTE; ++ u32 cntREG_ETH_LCOL; ++ u32 cntREG_ETH_ECOL; ++ u32 cntREG_ETH_TUE; ++ u32 cntREG_ETH_CSE; ++ u32 cntREG_ETH_RE; ++ u32 cntREG_ETH_ROVR; ++ u32 cntREG_ETH_SE; ++ u32 cntREG_ETH_ELR; ++ u32 cntREG_ETH_RJB; ++ u32 cntREG_ETH_USF; ++ u32 cntREG_ETH_SQEE; ++ // Interrupt Counter : ++ u32 cntHRESP; // Reset = 0x0000 ++ u32 cntROVR; // Reset = 0x0000 ++ u32 cntLINK; // Reset = 0x0000 ++ u32 cntTIDLE; // Reset = 0x0000 ++ u32 cntTCOM; // Reset = 0x0000 ++ u32 cntTBRE; // Reset = 0x0000 ++ u32 cntRTRY; // Reset = 0x0000 ++ u32 cntTUND; // Reset = 0x0000 ++ u32 cntTOVR; // Reset = 0x0000 ++ u32 cntRBNA; // Reset = 0x0000 ++ u32 cntRCOM; // Reset = 0x0000 ++ u32 cntDONE; // Reset = 0x0000 ++ // Flags: ++ u8 flagMacTxPermit; // 0:No,1:Permitted. Initialize as "permitted" ++ u8 flagISR_INT_RCOM; ++ u8 flagISR_INT_RBNA; ++ u8 flagISR_INT_DONE; ++ u8 flagPowerOn; // 0:Poweroff, 1:Poweron ++ u8 initedGMAC; // 0:Not initialized, 1:Initialized. ++ u8 flagRBNA; ++ // Misc Counter: ++ u32 cntRxFrames; // Reset = 0x00000000 (Counter of RX frames,no matter it's me or not) ++ u32 cntReadONE_RX; // Counter for ReadONE_RX_Frame ++ u32 cntCase20070806; ++ u32 cntChkToTransmit; ++ // Misc Variables: ++ u32 mainThreadTasks; // (20071029_CHARLES) b0=Poweroff,b1=Poweron ++}; ++typedef struct _UtilityVarsGMAC UtilityVarsGMAC; ++ ++struct GMAC_private ++{ ++ struct net_device *dev; ++ struct net_device_stats stats; ++ struct mii_if_info mii; /* ethtool support */ ++ struct timer_list Link_timer; ++ u32 padmux_type; ++ u32 hardware_type; ++ u32 initstate; ++ u32 msglvl; ++ BasicConfigGMAC ThisBCE; ++ UtilityVarsGMAC ThisUVE; ++ /* Memory */ ++ phys_addr_t RAM_VA_BASE; ++ phys_addr_t RAM_PA_BASE; ++ phys_addr_t RAM_VA_PA_OFFSET; ++ phys_addr_t RX_DESC_BASE; ++#ifndef RX_ZERO_COPY ++ phys_addr_t RX_BUFFER_BASE; ++#endif ++#ifdef TX_DESC_MODE ++ phys_addr_t TX_LP_DESC_BASE; ++ phys_addr_t TX_HP_DESC_BASE; ++#endif ++ phys_addr_t TX_BUFFER_BASE; ++ /* PHY */ ++ u8 phyaddr; ++ u32 phy_status_register; ++ u32 phy_type; /* type of PHY (PHY_ID) */ ++ spinlock_t irq_lock; /* lock for MDI interface */ ++ spinlock_t tx_lock; /* lock for MDI interface */ ++ short phy_media; /* media interface type */ ++ /* Transmit */ ++ u32 tx_index; ++ u32 tx_ring_entry_number; ++#ifdef TX_DESC_MODE ++ struct tx_descriptor *tx_desc_list; ++ struct sk_buff *tx_desc_sk_buff_list[TX_LOW_PRI_DESC_NUMBER]; ++ u32 tx_desc_write_index; ++ u32 tx_desc_read_index; ++ u32 tx_desc_queued_number; ++ u32 tx_desc_count; ++ u32 tx_desc_full_count; ++#endif ++#ifdef TX_SOFTWARE_QUEUE ++ struct tx_ring tx_swq[TX_SW_QUEUE_SIZE]; ++ unsigned int tx_rdidx; /* TX_SW_QUEUE read to hw index */ ++ unsigned int tx_wridx; /* TX_SW_QUEUE write index */ ++ unsigned int tx_clidx; /* TX_SW_QUEUE clear index */ ++ ++ unsigned int tx_rdwrp; /* TX_SW_QUEUE read to hw index wrap*/ ++ unsigned int tx_wrwrp; /* TX_SW_QUEUE write index wrap*/ ++ unsigned int tx_clwrp; /* TX_SW_QUEUE clear index wrap */ ++ unsigned int tx_swq_full_cnt; /* TX_SW_QUEUE full stopped count*/ ++ ++ unsigned int irqcnt; ++ unsigned int tx_irqcnt; ++#endif ++#ifdef TX_NAPI ++ struct napi_struct napi_tx; ++#endif ++ /* Receive */ ++ u32 ROVR_count; ++ u32 full_budge_count; ++ u32 polling_count; ++ u32 max_polling; ++ u32 rx_ring_entry_number; ++#ifdef RX_DESC_MODE ++ struct rx_descriptor *rx_desc_list; ++ u32 rx_desc_read_index; ++#ifdef RX_ZERO_COPY ++ struct sk_buff *rx_desc_sk_buff_list[RX_DESC_NUMBER]; ++#endif ++#endif ++#ifdef RX_NAPI ++ struct napi_struct napi_rx; ++#endif ++ /* suspend/resume */ ++ u32 ep_flag; ++}; ++ ++#endif ++// ----------------------------------------------------------------------------- ++// Linux GMAC.h End ++// ----------------------------------------------------------------------------- +diff --git a/drivers/sstar/gpio/Kconfig b/drivers/sstar/gpio/Kconfig +new file mode 100755 +index 000000000000..811f24c4fa42 +--- /dev/null ++++ b/drivers/sstar/gpio/Kconfig +@@ -0,0 +1,8 @@ ++config MS_GPIO ++ tristate "GPIO driver" ++ default y ++ help ++ ++config MS_SW_I2C ++ tristate "SW I2C via GPIO support" ++ depends on MS_GPIO +diff --git a/drivers/sstar/gpio/Makefile b/drivers/sstar/gpio/Makefile +new file mode 100755 +index 000000000000..34ce1e24423c +--- /dev/null ++++ b/drivers/sstar/gpio/Makefile +@@ -0,0 +1,17 @@ ++# ++# Makefile for MStar GPIO device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/gpio ++EXTRA_CFLAGS += -Idrivers/sstar/gpio/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mdrv_gpio.o mdrv_gpio_io.o ++obj-$(CONFIG_MS_GPIO) += $(CONFIG_SSTAR_CHIP_NAME)/ ++obj-$(CONFIG_MS_SW_I2C) += ms_gpioi2c.o mdrv_sw_iic.o +diff --git a/drivers/sstar/gpio/cedric/Makefile b/drivers/sstar/gpio/cedric/Makefile +new file mode 100755 +index 000000000000..75208f8abe12 +--- /dev/null ++++ b/drivers/sstar/gpio/cedric/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for MStar GPIO HAL drivers. ++# ++ ++ ++ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++include $(TOP_DIR)/modules.mk ++endif ++ ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/gpio ++EXTRA_CFLAGS += -Idrivers/sstar/gpio/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# files ++#obj-$(CONFIG_MSTAR_GPIO) += mhal_gpio.o +diff --git a/drivers/sstar/gpio/cedric/mhal_gpio.c b/drivers/sstar/gpio/cedric/mhal_gpio.c +new file mode 100755 +index 000000000000..5aeee3235ad4 +--- /dev/null ++++ b/drivers/sstar/gpio/cedric/mhal_gpio.c +@@ -0,0 +1,1756 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if 1 ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++/* ++#define BIT0 BIT(0) ++#define BIT1 BIT(1) ++#define BIT2 BIT(2) ++#define BIT3 BIT(3) ++#define BIT4 BIT(4) ++#define BIT5 BIT(5) ++#define BIT6 BIT(6) ++#define BIT7 BIT(7) ++*/ ++ // Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++#define GPIO0_PAD PAD_PM_GPIO0 ++#define GPIO0_OEN 0x0f08, BIT0 ++#define GPIO0_IN 0x0f10, BIT0 ++#define GPIO0_OUT 0x0f0c, BIT0 ++ ++#define GPIO1_PAD PAD_PM_GPIO1 ++#define GPIO1_OEN 0x0f08, BIT1 ++#define GPIO1_IN 0x0f10, BIT1 ++#define GPIO1_OUT 0x0f0c, BIT1 ++ ++#define GPIO2_PAD PAD_PM_IIC_SDA ++#define GPIO2_OEN 0x0f08, BIT2 ++#define GPIO2_IN 0x0f10, BIT2 ++#define GPIO2_OUT 0x0f0c, BIT2 ++ ++#define GPIO3_PAD PAD_PM_IIC_SCL ++#define GPIO3_OEN 0x0f08, BIT3 ++#define GPIO3_IN 0x0f10, BIT3 ++#define GPIO3_OUT 0x0f0c, BIT3 ++ ++#define GPIO4_PAD PAD_PM_MIIC_SDA ++#define GPIO4_OEN 0x0f08, BIT4 ++#define GPIO4_IN 0x0f10, BIT4 ++#define GPIO4_OUT 0x0f0c, BIT4 ++ ++#define GPIO5_PAD PAD_PM_MIIC_SCL ++#define GPIO5_OEN 0x0f08, BIT5 ++#define GPIO5_IN 0x0f10, BIT5 ++#define GPIO5_OUT 0x0f0c, BIT5 ++ ++#define GPIO6_PAD PAD_PM_SPI_CK ++#define GPIO6_OEN 0x0f08, BIT6 ++#define GPIO6_IN 0x0f10, BIT6 ++#define GPIO6_OUT 0x0f0c, BIT6 ++ ++#define GPIO7_PAD PAD_PM_SPI_CZ0 ++#define GPIO7_OEN 0x0f08, BIT7 ++#define GPIO7_IN 0x0f10, BIT7 ++#define GPIO7_OUT 0x0f0c, BIT7 ++ ++#define GPIO8_PAD PAD_PM_SPI_GPIO ++#define GPIO8_OEN 0x0f09, BIT0 ++#define GPIO8_IN 0x0f11, BIT0 ++#define GPIO8_OUT 0x0f0d, BIT0 ++ ++#define GPIO9_PAD PAD_PM_SPI_DI ++#define GPIO9_OEN 0x0f09, BIT1 ++#define GPIO9_IN 0x0f11, BIT1 ++#define GPIO9_OUT 0x0f0d, BIT1 ++ ++#define GPIO10_PAD PAD_PM_SPI_DO ++#define GPIO10_OEN 0x0f09, BIT2 ++#define GPIO10_IN 0x0f11, BIT2 ++#define GPIO10_OUT 0x0f0d, BIT2 ++ ++#define GPIO11_PAD PAD_ONOFF ++#define GPIO11_OEN 0x0f09, BIT3 ++#define GPIO11_IN 0x0f11, BIT3 ++#define GPIO11_OUT 0x0f0d, BIT3 ++ ++#define GPIO12_PAD PAD_CHRGDET ++#define GPIO12_OEN 0x0f09, BIT4 ++#define GPIO12_IN 0x0f11, BIT4 ++#define GPIO12_OUT 0x0f0d, BIT4 ++ ++#define GPIO13_PAD PAD_32K_OUT ++#define GPIO13_OEN 0x0f09, BIT5 ++#define GPIO13_IN 0x0f11, BIT5 ++#define GPIO13_OUT 0x0f0d, BIT5 ++ ++#define GPIO14_PAD PAD_IRIN ++#define GPIO14_OEN 0x0f09, BIT6 ++#define GPIO14_IN 0x0f11, BIT6 ++#define GPIO14_OUT 0x0f0d, BIT6 ++ ++#define GPIO15_PAD PAD_CEC ++#define GPIO15_OEN 0x0f09, BIT7 ++#define GPIO15_IN 0x0f11, BIT7 ++#define GPIO15_OUT 0x0f0d, BIT7 ++ ++#define GPIO16_PAD PAD_PM_SD0_CDZ ++#define GPIO16_OEN 0x0f0a, BIT0 ++#define GPIO16_IN 0x0f12, BIT0 ++#define GPIO16_OUT 0x0f0e, BIT0 ++ ++#define GPIO17_PAD PAD_PM_SD1_CDZ ++#define GPIO17_OEN 0x0f0a, BIT1 ++#define GPIO17_IN 0x0f12, BIT1 ++#define GPIO17_OUT 0x0f0e, BIT1 ++ ++#define GPIO18_PAD PAD_PM_SD2_CDZ ++#define GPIO18_OEN 0x0f0a, BIT2 ++#define GPIO18_IN 0x0f12, BIT2 ++#define GPIO18_OUT 0x0f0e, BIT2 ++ ++#define GPIO19_PAD PAD_PM_SD_GPIO ++#define GPIO19_OEN 0x0f0a, BIT3 ++#define GPIO19_IN 0x0f12, BIT3 ++#define GPIO19_OUT 0x0f0e, BIT3 ++ ++#define GPIO20_PAD PAD_HOTPLUG ++#define GPIO20_OEN 0x0f0a, BIT4 ++#define GPIO20_IN 0x0f12, BIT4 ++#define GPIO20_OUT 0x0f0e, BIT4 ++ ++#define GPIO21_PAD PAD_BATOK ++#define GPIO21_OEN 0x0f0a, BIT5 ++#define GPIO21_IN 0x0f12, BIT5 ++#define GPIO21_OUT 0x0f0e, BIT5 ++ ++#define GPIO22_PAD PAD_PMIC_CHIPEN ++#define GPIO22_OEN 0x0f0a, BIT6 ++#define GPIO22_IN 0x0f12, BIT6 ++#define GPIO22_OUT 0x0f0e, BIT6 ++ ++#define GPIO23_PAD PAD_PMIC_STDBYN ++#define GPIO23_OEN 0x0f0a, BIT7 ++#define GPIO23_IN 0x0f12, BIT7 ++#define GPIO23_OUT 0x0f0e, BIT7 ++ ++#define GPIO24_PAD PAD_PMIC_INT ++#define GPIO24_OEN 0x0f0b, BIT0 ++#define GPIO24_IN 0x0f13, BIT0 ++#define GPIO24_OUT 0x0f0f, BIT0 ++ ++#define GPIO25_PAD PAD_SD0_D1 ++#define GPIO25_OEN 0x102b7A, BIT1 ++#define GPIO25_IN 0x102b7A, BIT2 ++#define GPIO25_OUT 0x102b7A, BIT0 ++ ++#define GPIO26_PAD PAD_SD0_D0 ++#define GPIO26_OEN 0x102b79, BIT1 ++#define GPIO26_IN 0x102b79, BIT2 ++#define GPIO26_OUT 0x102b79, BIT0 ++ ++#define GPIO27_PAD PAD_SD0_CLK ++#define GPIO27_OEN 0x102b7C, BIT1 ++#define GPIO27_IN 0x102b7C, BIT2 ++#define GPIO27_OUT 0x102b7C, BIT0 ++ ++#define GPIO28_PAD PAD_SD0_CMD ++#define GPIO28_OEN 0x102b7B, BIT1 ++#define GPIO28_IN 0x102b7B, BIT2 ++#define GPIO28_OUT 0x102b7B, BIT0 ++ ++#define GPIO29_PAD PAD_SD0_D3 ++#define GPIO29_OEN 0x102b7E, BIT1 ++#define GPIO29_IN 0x102b7E, BIT2 ++#define GPIO29_OUT 0x102b7E, BIT0 ++ ++#define GPIO30_PAD PAD_SD0_D2 ++#define GPIO30_OEN 0x102b7D, BIT1 ++#define GPIO30_IN 0x102b7D, BIT2 ++#define GPIO30_OUT 0x102b7D, BIT0 ++ ++#define GPIO31_PAD PAD_SD1_D1 ++#define GPIO31_OEN 0x102b80, BIT1 ++#define GPIO31_IN 0x102b80, BIT2 ++#define GPIO31_OUT 0x102b80, BIT0 ++ ++#define GPIO32_PAD PAD_SD1_D0 ++#define GPIO32_OEN 0x102b7F, BIT1 ++#define GPIO32_IN 0x102b7F, BIT2 ++#define GPIO32_OUT 0x102b7F, BIT0 ++ ++#define GPIO33_PAD PAD_SD1_CLK ++#define GPIO33_OEN 0x102b82, BIT1 ++#define GPIO33_IN 0x102b82, BIT2 ++#define GPIO33_OUT 0x102b82, BIT0 ++ ++#define GPIO34_PAD PAD_SD1_CMD ++#define GPIO34_OEN 0x102b81, BIT1 ++#define GPIO34_IN 0x102b81, BIT2 ++#define GPIO34_OUT 0x102b81, BIT0 ++ ++#define GPIO35_PAD PAD_SD1_D3 ++#define GPIO35_OEN 0x102b84, BIT1 ++#define GPIO35_IN 0x102b84, BIT2 ++#define GPIO35_OUT 0x102b84, BIT0 ++ ++#define GPIO36_PAD PAD_SD1_D2 ++#define GPIO36_OEN 0x102b83, BIT1 ++#define GPIO36_IN 0x102b83, BIT2 ++#define GPIO36_OUT 0x102b83, BIT0 ++ ++#define GPIO37_PAD PAD_A_GPS_EVENT ++#define GPIO37_OEN 0x102b31, BIT1 ++#define GPIO37_IN 0x102b31, BIT2 ++#define GPIO37_OUT 0x102b31, BIT0 ++ ++#define GPIO38_PAD PAD_AFE1_SGN ++#define GPIO38_OEN 0x102b32, BIT1 ++#define GPIO38_IN 0x102b32, BIT2 ++#define GPIO38_OUT 0x102b32, BIT0 ++ ++#define GPIO39_PAD PAD_AFE1_MAG ++#define GPIO39_OEN 0x102b33, BIT1 ++#define GPIO39_IN 0x102b33, BIT2 ++#define GPIO39_OUT 0x102b33, BIT0 ++ ++#define GPIO40_PAD PAD_RFSPI_CZ1 ++#define GPIO40_OEN 0x102b39, BIT1 ++#define GPIO40_IN 0x102b39, BIT2 ++#define GPIO40_OUT 0x102b39, BIT0 ++ ++#define GPIO41_PAD PAD_AFE0_SGN ++#define GPIO41_OEN 0x102b34, BIT1 ++#define GPIO41_IN 0x102b34, BIT2 ++#define GPIO41_OUT 0x102b34, BIT0 ++ ++#define GPIO42_PAD PAD_AFE0_MAG ++#define GPIO42_OEN 0x102b35, BIT1 ++#define GPIO42_IN 0x102b35, BIT2 ++#define GPIO42_OUT 0x102b35, BIT0 ++ ++#define GPIO43_PAD PAD_RFSPI_CLK ++#define GPIO43_OEN 0x102b38, BIT1 ++#define GPIO43_IN 0x102b38, BIT2 ++#define GPIO43_OUT 0x102b38, BIT0 ++ ++#define GPIO44_PAD PAD_RFSPI_DATA ++#define GPIO44_OEN 0x102b37, BIT1 ++#define GPIO44_IN 0x102b37, BIT2 ++#define GPIO44_OUT 0x102b37, BIT0 ++ ++#define GPIO45_PAD PAD_RFSPI_CZ0 ++#define GPIO45_OEN 0x102b36, BIT1 ++#define GPIO45_IN 0x102b36, BIT2 ++#define GPIO45_OUT 0x102b36, BIT0 ++ ++#define GPIO46_PAD PAD_BTI_RX_TX ++#define GPIO46_OEN 0x102b06, BIT1 ++#define GPIO46_IN 0x102b06, BIT2 ++#define GPIO46_OUT 0x102b06, BIT0 ++ ++#define GPIO47_PAD PAD_BTI_DATA1 ++#define GPIO47_OEN 0x102b05, BIT1 ++#define GPIO47_IN 0x102b05, BIT2 ++#define GPIO47_OUT 0x102b05, BIT0 ++ ++#define GPIO48_PAD PAD_BTI_DATA0 ++#define GPIO48_OEN 0x102b04, BIT1 ++#define GPIO48_IN 0x102b04, BIT2 ++#define GPIO48_OUT 0x102b04, BIT0 ++ ++#define GPIO49_PAD PAD_BT_CLK_24M ++#define GPIO49_OEN 0x102b03, BIT1 ++#define GPIO49_IN 0x102b03, BIT2 ++#define GPIO49_OUT 0x102b03, BIT0 ++ ++#define GPIO50_PAD PAD_BT_SPI_SCLK ++#define GPIO50_OEN 0x102b02, BIT1 ++#define GPIO50_IN 0x102b02, BIT2 ++#define GPIO50_OUT 0x102b02, BIT0 ++ ++#define GPIO51_PAD PAD_BT_SPI_SDATA ++#define GPIO51_OEN 0x102b01, BIT1 ++#define GPIO51_IN 0x102b01, BIT2 ++#define GPIO51_OUT 0x102b01, BIT0 ++ ++#define GPIO52_PAD PAD_BT_SPI_SENB ++#define GPIO52_OEN 0x102b00, BIT1 ++#define GPIO52_IN 0x102b00, BIT2 ++#define GPIO52_OUT 0x102b00, BIT0 ++ ++#define GPIO53_PAD PAD_BT_CHIP_EN ++#define GPIO53_OEN 0x102b07, BIT1 ++#define GPIO53_IN 0x102b07, BIT2 ++#define GPIO53_OUT 0x102b07, BIT0 ++ ++#define GPIO54_PAD PAD_SR_D0 ++#define GPIO54_OEN 0x102b97, BIT1 ++#define GPIO54_IN 0x102b97, BIT2 ++#define GPIO54_OUT 0x102b97, BIT0 ++ ++#define GPIO55_PAD PAD_SR_D1 ++#define GPIO55_OEN 0x102b96, BIT1 ++#define GPIO55_IN 0x102b96, BIT2 ++#define GPIO55_OUT 0x102b96, BIT0 ++ ++#define GPIO56_PAD PAD_SR_D2 ++#define GPIO56_OEN 0x102b99, BIT1 ++#define GPIO56_IN 0x102b99, BIT2 ++#define GPIO56_OUT 0x102b99, BIT0 ++ ++#define GPIO57_PAD PAD_SR_D3 ++#define GPIO57_OEN 0x102b98, BIT1 ++#define GPIO57_IN 0x102b98, BIT2 ++#define GPIO57_OUT 0x102b98, BIT0 ++ ++#define GPIO58_PAD PAD_SR_D4 ++#define GPIO58_OEN 0x102b9B, BIT1 ++#define GPIO58_IN 0x102b9B, BIT2 ++#define GPIO58_OUT 0x102b9B, BIT0 ++ ++#define GPIO59_PAD PAD_SR_D5 ++#define GPIO59_OEN 0x102b9A, BIT1 ++#define GPIO59_IN 0x102b9A, BIT2 ++#define GPIO59_OUT 0x102b9A, BIT0 ++ ++#define GPIO60_PAD PAD_SR_D6 ++#define GPIO60_OEN 0x102b9D, BIT1 ++#define GPIO60_IN 0x102b9D, BIT2 ++#define GPIO60_OUT 0x102b9D, BIT0 ++ ++#define GPIO61_PAD PAD_SR_D7 ++#define GPIO61_OEN 0x102b9C, BIT1 ++#define GPIO61_IN 0x102b9C, BIT2 ++#define GPIO61_OUT 0x102b9C, BIT0 ++ ++#define GPIO62_PAD PAD_SR_PCLK ++#define GPIO62_OEN 0x102bA3, BIT1 ++#define GPIO62_IN 0x102bA3, BIT2 ++#define GPIO62_OUT 0x102bA3, BIT0 ++ ++#define GPIO63_PAD PAD_SR_HSYNC ++#define GPIO63_OEN 0x102b9F, BIT1 ++#define GPIO63_IN 0x102b9F, BIT2 ++#define GPIO63_OUT 0x102b9F, BIT0 ++ ++#define GPIO64_PAD PAD_SR_STROBE ++#define GPIO64_OEN 0x102b9E, BIT1 ++#define GPIO64_IN 0x102b9E, BIT2 ++#define GPIO64_OUT 0x102b9E, BIT0 ++ ++#define GPIO65_PAD PAD_SR_VSYNC ++#define GPIO65_OEN 0x102bA0, BIT1 ++#define GPIO65_IN 0x102bA0, BIT2 ++#define GPIO65_OUT 0x102bA0, BIT0 ++ ++#define GPIO66_PAD PAD_SR_RST ++#define GPIO66_OEN 0x102bA1, BIT1 ++#define GPIO66_IN 0x102bA1, BIT2 ++#define GPIO66_OUT 0x102bA1, BIT0 ++ ++#define GPIO67_PAD PAD_SR_PWRDN ++#define GPIO67_OEN 0x102bA2, BIT1 ++#define GPIO67_IN 0x102bA2, BIT2 ++#define GPIO67_OUT 0x102bA2, BIT0 ++ ++#define GPIO68_PAD PAD_GPIO33 ++#define GPIO68_OEN 0x102b2A, BIT1 ++#define GPIO68_IN 0x102b2A, BIT2 ++#define GPIO68_OUT 0x102b2A, BIT0 ++ ++#define GPIO69_PAD PAD_GPIO32 ++#define GPIO69_OEN 0x102b29, BIT1 ++#define GPIO69_IN 0x102b29, BIT2 ++#define GPIO69_OUT 0x102b29, BIT0 ++ ++#define GPIO70_PAD PAD_GPIO31 ++#define GPIO70_OEN 0x102b28, BIT1 ++#define GPIO70_IN 0x102b28, BIT2 ++#define GPIO70_OUT 0x102b28, BIT0 ++ ++#define GPIO71_PAD PAD_GPIO30 ++#define GPIO71_OEN 0x102b27, BIT1 ++#define GPIO71_IN 0x102b27, BIT2 ++#define GPIO71_OUT 0x102b27, BIT0 ++ ++#define GPIO72_PAD PAD_GPIO29 ++#define GPIO72_OEN 0x102b26, BIT1 ++#define GPIO72_IN 0x102b26, BIT2 ++#define GPIO72_OUT 0x102b26, BIT0 ++ ++#define GPIO73_PAD PAD_GPIO28 ++#define GPIO73_OEN 0x102b25, BIT1 ++#define GPIO73_IN 0x102b25, BIT2 ++#define GPIO73_OUT 0x102b25, BIT0 ++ ++#define GPIO74_PAD PAD_GPIO27 ++#define GPIO74_OEN 0x102b24, BIT1 ++#define GPIO74_IN 0x102b24, BIT2 ++#define GPIO74_OUT 0x102b24, BIT0 ++ ++#define GPIO75_PAD PAD_GPIO26 ++#define GPIO75_OEN 0x102b23, BIT1 ++#define GPIO75_IN 0x102b23, BIT2 ++#define GPIO75_OUT 0x102b23, BIT0 ++ ++#define GPIO76_PAD PAD_GPIO25 ++#define GPIO76_OEN 0x102b22, BIT1 ++#define GPIO76_IN 0x102b22, BIT2 ++#define GPIO76_OUT 0x102b22, BIT0 ++ ++#define GPIO77_PAD PAD_GPIO24 ++#define GPIO77_OEN 0x102b21, BIT1 ++#define GPIO77_IN 0x102b21, BIT2 ++#define GPIO77_OUT 0x102b21, BIT0 ++ ++#define GPIO78_PAD PAD_UART_RX1 ++#define GPIO78_OEN 0x102bB0, BIT1 ++#define GPIO78_IN 0x102bB0, BIT2 ++#define GPIO78_OUT 0x102bB0, BIT0 ++ ++#define GPIO79_PAD PAD_UART_TX1 ++#define GPIO79_OEN 0x102bB1, BIT1 ++#define GPIO79_IN 0x102bB1, BIT2 ++#define GPIO79_OUT 0x102bB1, BIT0 ++ ++#define GPIO80_PAD PAD_UART_RX2 ++#define GPIO80_OEN 0x102bB3, BIT1 ++#define GPIO80_IN 0x102bB3, BIT2 ++#define GPIO80_OUT 0x102bB3, BIT0 ++ ++#define GPIO81_PAD PAD_UART_TX2 ++#define GPIO81_OEN 0x102bB2, BIT1 ++#define GPIO81_IN 0x102bB2, BIT2 ++#define GPIO81_OUT 0x102bB2, BIT0 ++ ++#define GPIO82_PAD PAD_UART_RX3 ++#define GPIO82_OEN 0x102bB5, BIT1 ++#define GPIO82_IN 0x102bB5, BIT2 ++#define GPIO82_OUT 0x102bB5, BIT0 ++ ++#define GPIO83_PAD PAD_UART_TX3 ++#define GPIO83_OEN 0x102bB4, BIT1 ++#define GPIO83_IN 0x102bB4, BIT2 ++#define GPIO83_OUT 0x102bB4, BIT0 ++ ++#define GPIO84_PAD PAD_UART_RX4 ++#define GPIO84_OEN 0x102bB7, BIT1 ++#define GPIO84_IN 0x102bB7, BIT2 ++#define GPIO84_OUT 0x102bB7, BIT0 ++ ++#define GPIO85_PAD PAD_UART_TX4 ++#define GPIO85_OEN 0x102bB6, BIT1 ++#define GPIO85_IN 0x102bB6, BIT2 ++#define GPIO85_OUT 0x102bB6, BIT0 ++ ++#define GPIO86_PAD PAD_UART_CTS2 ++#define GPIO86_OEN 0x102bBD, BIT1 ++#define GPIO86_IN 0x102bBD, BIT2 ++#define GPIO86_OUT 0x102bBD, BIT0 ++ ++#define GPIO87_PAD PAD_UART_RTS2 ++#define GPIO87_OEN 0x102bBC, BIT1 ++#define GPIO87_IN 0x102bBC, BIT2 ++#define GPIO87_OUT 0x102bBC, BIT0 ++ ++#define GPIO88_PAD PAD_GPIO34 ++#define GPIO88_OEN 0x102b2B, BIT1 ++#define GPIO88_IN 0x102b2B, BIT2 ++#define GPIO88_OUT 0x102b2B, BIT0 ++ ++#define GPIO89_PAD PAD_GPIO35 ++#define GPIO89_OEN 0x102b2C, BIT1 ++#define GPIO89_IN 0x102b2C, BIT2 ++#define GPIO89_OUT 0x102b2C, BIT0 ++ ++#define GPIO90_PAD PAD_GPIO36 ++#define GPIO90_OEN 0x102b2D, BIT1 ++#define GPIO90_IN 0x102b2D, BIT2 ++#define GPIO90_OUT 0x102b2D, BIT0 ++ ++#define GPIO91_PAD PAD_GPIO37 ++#define GPIO91_OEN 0x102b2E, BIT1 ++#define GPIO91_IN 0x102b2E, BIT2 ++#define GPIO91_OUT 0x102b2E, BIT0 ++ ++#define GPIO92_PAD PAD_GPIO38 ++#define GPIO92_OEN 0x102b2F, BIT1 ++#define GPIO92_IN 0x102b2F, BIT2 ++#define GPIO92_OUT 0x102b2F, BIT0 ++ ++#define GPIO93_PAD PAD_MPIF_CS1Z ++#define GPIO93_OEN 0x102b5D, BIT1 ++#define GPIO93_IN 0x102b5D, BIT2 ++#define GPIO93_OUT 0x102b5D, BIT0 ++ ++#define GPIO94_PAD PAD_MPIF_CS0Z ++#define GPIO94_OEN 0x102b5E, BIT1 ++#define GPIO94_IN 0x102b5E, BIT2 ++#define GPIO94_OUT 0x102b5E, BIT0 ++ ++#define GPIO95_PAD PAD_MPIF_D0 ++#define GPIO95_OEN 0x102b58, BIT1 ++#define GPIO95_IN 0x102b58, BIT2 ++#define GPIO95_OUT 0x102b58, BIT0 ++ ++#define GPIO96_PAD PAD_MPIF_D1 ++#define GPIO96_OEN 0x102b59, BIT1 ++#define GPIO96_IN 0x102b59, BIT2 ++#define GPIO96_OUT 0x102b59, BIT0 ++ ++#define GPIO97_PAD PAD_MPIF_D2 ++#define GPIO97_OEN 0x102b5A, BIT1 ++#define GPIO97_IN 0x102b5A, BIT2 ++#define GPIO97_OUT 0x102b5A, BIT0 ++ ++#define GPIO98_PAD PAD_MPIF_D3 ++#define GPIO98_OEN 0x102b5B, BIT1 ++#define GPIO98_IN 0x102b5B, BIT2 ++#define GPIO98_OUT 0x102b5B, BIT0 ++ ++#define GPIO99_PAD PAD_MPIF_CK ++#define GPIO99_OEN 0x102b5F, BIT1 ++#define GPIO99_IN 0x102b5F, BIT2 ++#define GPIO99_OUT 0x102b5F, BIT0 ++ ++#define GPIO100_PAD PAD_MPIF_BUSY ++#define GPIO100_OEN 0x102b5C, BIT1 ++#define GPIO100_IN 0x102b5C, BIT2 ++#define GPIO100_OUT 0x102b5C, BIT0 ++ ++#define GPIO101_PAD PAD_MIIC0_SDA ++#define GPIO101_OEN 0x102b3B, BIT1 ++#define GPIO101_IN 0x102b3B, BIT2 ++#define GPIO101_OUT 0x102b3B, BIT0 ++ ++#define GPIO102_PAD PAD_MIIC0_SCL ++#define GPIO102_OEN 0x102b3C, BIT1 ++#define GPIO102_IN 0x102b3C, BIT2 ++#define GPIO102_OUT 0x102b3C, BIT0 ++ ++#define GPIO103_PAD PAD_GPIO23 ++#define GPIO103_OEN 0x102b20, BIT1 ++#define GPIO103_IN 0x102b20, BIT2 ++#define GPIO103_OUT 0x102b20, BIT0 ++ ++#define GPIO104_PAD PAD_GPIO22 ++#define GPIO104_OEN 0x102b1F, BIT1 ++#define GPIO104_IN 0x102b1F, BIT2 ++#define GPIO104_OUT 0x102b1F, BIT0 ++ ++#define GPIO105_PAD PAD_GPIO21 ++#define GPIO105_OEN 0x102b1E, BIT1 ++#define GPIO105_IN 0x102b1E, BIT2 ++#define GPIO105_OUT 0x102b1E, BIT0 ++ ++#define GPIO106_PAD PAD_GPIO20 ++#define GPIO106_OEN 0x102b1D, BIT1 ++#define GPIO106_IN 0x102b1D, BIT2 ++#define GPIO106_OUT 0x102b1D, BIT0 ++ ++#define GPIO107_PAD PAD_GPIO19 ++#define GPIO107_OEN 0x102b1C, BIT1 ++#define GPIO107_IN 0x102b1C, BIT2 ++#define GPIO107_OUT 0x102b1C, BIT0 ++ ++#define GPIO108_PAD PAD_GPIO18 ++#define GPIO108_OEN 0x102b1B, BIT1 ++#define GPIO108_IN 0x102b1B, BIT2 ++#define GPIO108_OUT 0x102b1B, BIT0 ++ ++#define GPIO109_PAD PAD_GPIO17 ++#define GPIO109_OEN 0x102b1A, BIT1 ++#define GPIO109_IN 0x102b1A, BIT2 ++#define GPIO109_OUT 0x102b1A, BIT0 ++ ++#define GPIO110_PAD PAD_GPIO16 ++#define GPIO110_OEN 0x102b19, BIT1 ++#define GPIO110_IN 0x102b19, BIT2 ++#define GPIO110_OUT 0x102b19, BIT0 ++ ++#define GPIO111_PAD PAD_GPIO15 ++#define GPIO111_OEN 0x102b18, BIT1 ++#define GPIO111_IN 0x102b18, BIT2 ++#define GPIO111_OUT 0x102b18, BIT0 ++ ++#define GPIO112_PAD PAD_GPIO14 ++#define GPIO112_OEN 0x102b17, BIT1 ++#define GPIO112_IN 0x102b17, BIT2 ++#define GPIO112_OUT 0x102b17, BIT0 ++ ++#define GPIO113_PAD PAD_GPIO13 ++#define GPIO113_OEN 0x102b16, BIT1 ++#define GPIO113_IN 0x102b16, BIT2 ++#define GPIO113_OUT 0x102b16, BIT0 ++ ++#define GPIO114_PAD PAD_GPIO12 ++#define GPIO114_OEN 0x102b15, BIT1 ++#define GPIO114_IN 0x102b15, BIT2 ++#define GPIO114_OUT 0x102b15, BIT0 ++ ++#define GPIO115_PAD PAD_GPIO11 ++#define GPIO115_OEN 0x102b14, BIT1 ++#define GPIO115_IN 0x102b14, BIT2 ++#define GPIO115_OUT 0x102b14, BIT0 ++ ++#define GPIO116_PAD PAD_GPIO10 ++#define GPIO116_OEN 0x102b13, BIT1 ++#define GPIO116_IN 0x102b13, BIT2 ++#define GPIO116_OUT 0x102b13, BIT0 ++ ++#define GPIO117_PAD PAD_GPIO9 ++#define GPIO117_OEN 0x102b12, BIT1 ++#define GPIO117_IN 0x102b12, BIT2 ++#define GPIO117_OUT 0x102b12, BIT0 ++ ++#define GPIO118_PAD PAD_GPIO8 ++#define GPIO118_OEN 0x102b11, BIT1 ++#define GPIO118_IN 0x102b11, BIT2 ++#define GPIO118_OUT 0x102b11, BIT0 ++ ++#define GPIO119_PAD PAD_GPIO7 ++#define GPIO119_OEN 0x102b10, BIT1 ++#define GPIO119_IN 0x102b10, BIT2 ++#define GPIO119_OUT 0x102b10, BIT0 ++ ++#define GPIO120_PAD PAD_GPIO6 ++#define GPIO120_OEN 0x102b0F, BIT1 ++#define GPIO120_IN 0x102b0F, BIT2 ++#define GPIO120_OUT 0x102b0F, BIT0 ++ ++#define GPIO121_PAD PAD_GPIO5 ++#define GPIO121_OEN 0x102b0E, BIT1 ++#define GPIO121_IN 0x102b0E, BIT2 ++#define GPIO121_OUT 0x102b0E, BIT0 ++ ++#define GPIO122_PAD PAD_GPIO4 ++#define GPIO122_OEN 0x102b0D, BIT1 ++#define GPIO122_IN 0x102b0D, BIT2 ++#define GPIO122_OUT 0x102b0D, BIT0 ++ ++#define GPIO123_PAD PAD_GPIO3 ++#define GPIO123_OEN 0x102b0C, BIT1 ++#define GPIO123_IN 0x102b0C, BIT2 ++#define GPIO123_OUT 0x102b0C, BIT0 ++ ++#define GPIO124_PAD PAD_GPIO2 ++#define GPIO124_OEN 0x102b0B, BIT1 ++#define GPIO124_IN 0x102b0B, BIT2 ++#define GPIO124_OUT 0x102b0B, BIT0 ++ ++#define GPIO125_PAD PAD_GPIO1 ++#define GPIO125_OEN 0x102b0A, BIT1 ++#define GPIO125_IN 0x102b0A, BIT2 ++#define GPIO125_OUT 0x102b0A, BIT0 ++ ++#define GPIO126_PAD PAD_GPIO0 ++#define GPIO126_OEN 0x102b09, BIT1 ++#define GPIO126_IN 0x102b09, BIT2 ++#define GPIO126_OUT 0x102b09, BIT0 ++ ++#define GPIO127_PAD PAD_TESTPIN ++#define GPIO127_OEN 0x0, BIT0 ++#define GPIO127_IN 0x0, BIT0 ++#define GPIO127_OUT 0x0, BIT0 ++ ++#define GPIO128_PAD PAD_SPDIF_OUT ++#define GPIO128_OEN 0x102b94, BIT1 ++#define GPIO128_IN 0x102b94, BIT2 ++#define GPIO128_OUT 0x102b94, BIT0 ++ ++#define GPIO129_PAD PAD_IIS_TRX_BCK ++#define GPIO129_OEN 0x102b51, BIT1 ++#define GPIO129_IN 0x102b51, BIT2 ++#define GPIO129_OUT 0x102b51, BIT0 ++ ++#define GPIO130_PAD PAD_IIS_TRX_WS ++#define GPIO130_OEN 0x102b50, BIT1 ++#define GPIO130_IN 0x102b50, BIT2 ++#define GPIO130_OUT 0x102b50, BIT0 ++ ++#define GPIO131_PAD PAD_IIS_TRX_OUT ++#define GPIO131_OEN 0x102b53, BIT1 ++#define GPIO131_IN 0x102b53, BIT2 ++#define GPIO131_OUT 0x102b53, BIT0 ++ ++#define GPIO132_PAD PAD_IIS_TRX_IN ++#define GPIO132_OEN 0x102b52, BIT1 ++#define GPIO132_IN 0x102b52, BIT2 ++#define GPIO132_OUT 0x102b52, BIT0 ++ ++#define GPIO133_PAD PAD_UART_RX5 ++#define GPIO133_OEN 0x102bB9, BIT1 ++#define GPIO133_IN 0x102bB9, BIT2 ++#define GPIO133_OUT 0x102bB9, BIT0 ++ ++#define GPIO134_PAD PAD_UART_TX5 ++#define GPIO134_OEN 0x102bB8, BIT1 ++#define GPIO134_IN 0x102bB8, BIT2 ++#define GPIO134_OUT 0x102bB8, BIT0 ++ ++#define GPIO135_PAD PAD_UART_CTS1 ++#define GPIO135_OEN 0x102bBB, BIT1 ++#define GPIO135_IN 0x102bBB, BIT2 ++#define GPIO135_OUT 0x102bBB, BIT0 ++ ++#define GPIO136_PAD PAD_UART_RTS1 ++#define GPIO136_OEN 0x102bBA, BIT1 ++#define GPIO136_IN 0x102bBA, BIT2 ++#define GPIO136_OUT 0x102bBA, BIT0 ++ ++#define GPIO137_PAD PAD_TCON_GPIO8 ++#define GPIO137_OEN 0x102bAE, BIT1 ++#define GPIO137_IN 0x102bAE, BIT2 ++#define GPIO137_OUT 0x102bAE, BIT0 ++ ++#define GPIO138_PAD PAD_TCON_GPIO7 ++#define GPIO138_OEN 0x102bAD, BIT1 ++#define GPIO138_IN 0x102bAD, BIT2 ++#define GPIO138_OUT 0x102bAD, BIT0 ++ ++#define GPIO139_PAD PAD_TCON_GPIO6 ++#define GPIO139_OEN 0x102bAC, BIT1 ++#define GPIO139_IN 0x102bAC, BIT2 ++#define GPIO139_OUT 0x102bAC, BIT0 ++ ++#define GPIO140_PAD PAD_TCON_GPIO5 ++#define GPIO140_OEN 0x102bAB, BIT1 ++#define GPIO140_IN 0x102bAB, BIT2 ++#define GPIO140_OUT 0x102bAB, BIT0 ++ ++#define GPIO141_PAD PAD_TCON_GPIO4 ++#define GPIO141_OEN 0x102bAA, BIT1 ++#define GPIO141_IN 0x102bAA, BIT2 ++#define GPIO141_OUT 0x102bAA, BIT0 ++ ++#define GPIO142_PAD PAD_TCON_GPIO3 ++#define GPIO142_OEN 0x102bA9, BIT1 ++#define GPIO142_IN 0x102bA9, BIT2 ++#define GPIO142_OUT 0x102bA9, BIT0 ++ ++#define GPIO143_PAD PAD_TCON_GPIO2 ++#define GPIO143_OEN 0x102bA8, BIT1 ++#define GPIO143_IN 0x102bA8, BIT2 ++#define GPIO143_OUT 0x102bA8, BIT0 ++ ++#define GPIO144_PAD PAD_TCON_GPIO1 ++#define GPIO144_OEN 0x102bA7, BIT1 ++#define GPIO144_IN 0x102bA7, BIT2 ++#define GPIO144_OUT 0x102bA7, BIT0 ++ ++#define GPIO145_PAD PAD_TCON_GPIO0 ++#define GPIO145_OEN 0x102bA6, BIT1 ++#define GPIO145_IN 0x102bA6, BIT2 ++#define GPIO145_OUT 0x102bA6, BIT0 ++ ++#define GPIO146_PAD PAD_TTL_GPIO11 ++#define GPIO146_OEN 0x102b49, BIT1 ++#define GPIO146_IN 0x102b49, BIT2 ++#define GPIO146_OUT 0x102b49, BIT0 ++ ++#define GPIO147_PAD PAD_TTL_GPIO10 ++#define GPIO147_OEN 0x102b48, BIT1 ++#define GPIO147_IN 0x102b48, BIT2 ++#define GPIO147_OUT 0x102b48, BIT0 ++ ++#define GPIO148_PAD PAD_TTL_GPIO9 ++#define GPIO148_OEN 0x102b47, BIT1 ++#define GPIO148_IN 0x102b47, BIT2 ++#define GPIO148_OUT 0x102b47, BIT0 ++ ++#define GPIO149_PAD PAD_TTL_GPIO8 ++#define GPIO149_OEN 0x102b46, BIT1 ++#define GPIO149_IN 0x102b46, BIT2 ++#define GPIO149_OUT 0x102b46, BIT0 ++ ++#define GPIO150_PAD PAD_TTL_GPIO7 ++#define GPIO150_OEN 0x102b45, BIT1 ++#define GPIO150_IN 0x102b45, BIT2 ++#define GPIO150_OUT 0x102b45, BIT0 ++ ++#define GPIO151_PAD PAD_TTL_GPIO6 ++#define GPIO151_OEN 0x102b44, BIT1 ++#define GPIO151_IN 0x102b44, BIT2 ++#define GPIO151_OUT 0x102b44, BIT0 ++ ++#define GPIO152_PAD PAD_TTL_GPIO5 ++#define GPIO152_OEN 0x102b43, BIT1 ++#define GPIO152_IN 0x102b43, BIT2 ++#define GPIO152_OUT 0x102b43, BIT0 ++ ++#define GPIO153_PAD PAD_TTL_GPIO4 ++#define GPIO153_OEN 0x102b42, BIT1 ++#define GPIO153_IN 0x102b42, BIT2 ++#define GPIO153_OUT 0x102b42, BIT0 ++ ++#define GPIO154_PAD PAD_TTL_GPIO3 ++#define GPIO154_OEN 0x102b41, BIT1 ++#define GPIO154_IN 0x102b41, BIT2 ++#define GPIO154_OUT 0x102b41, BIT0 ++ ++#define GPIO155_PAD PAD_TTL_GPIO2 ++#define GPIO155_OEN 0x102b40, BIT1 ++#define GPIO155_IN 0x102b40, BIT2 ++#define GPIO155_OUT 0x102b40, BIT0 ++ ++#define GPIO156_PAD PAD_TTL_GPIO1 ++#define GPIO156_OEN 0x102b3F, BIT1 ++#define GPIO156_IN 0x102b3F, BIT2 ++#define GPIO156_OUT 0x102b3F, BIT0 ++ ++#define GPIO157_PAD PAD_TTL_GPIO0 ++#define GPIO157_OEN 0x102b3E, BIT1 ++#define GPIO157_IN 0x102b3E, BIT2 ++#define GPIO157_OUT 0x102b3E, BIT0 ++ ++#define GPIO158_PAD PAD_NAND_WPZ ++#define GPIO158_OEN 0x102b6A, BIT1 ++#define GPIO158_IN 0x102b6A, BIT2 ++#define GPIO158_OUT 0x102b6A, BIT0 ++ ++#define GPIO159_PAD PAD_NAND_WEZ ++#define GPIO159_OEN 0x102b72, BIT1 ++#define GPIO159_IN 0x102b72, BIT2 ++#define GPIO159_OUT 0x102b72, BIT0 ++ ++#define GPIO160_PAD PAD_NAND_ALE ++#define GPIO160_OEN 0x102b70, BIT1 ++#define GPIO160_IN 0x102b70, BIT2 ++#define GPIO160_OUT 0x102b70, BIT0 ++ ++#define GPIO161_PAD PAD_NAND_CLE ++#define GPIO161_OEN 0x102b71, BIT1 ++#define GPIO161_IN 0x102b71, BIT2 ++#define GPIO161_OUT 0x102b71, BIT0 ++ ++#define GPIO162_PAD PAD_NAND_CE3Z ++#define GPIO162_OEN 0x102b6F, BIT1 ++#define GPIO162_IN 0x102b6F, BIT2 ++#define GPIO162_OUT 0x102b6F, BIT0 ++ ++#define GPIO163_PAD PAD_NAND_CE2Z ++#define GPIO163_OEN 0x102b6E, BIT1 ++#define GPIO163_IN 0x102b6E, BIT2 ++#define GPIO163_OUT 0x102b6E, BIT0 ++ ++#define GPIO164_PAD PAD_NAND_CE1Z ++#define GPIO164_OEN 0x102b6D, BIT1 ++#define GPIO164_IN 0x102b6D, BIT2 ++#define GPIO164_OUT 0x102b6D, BIT0 ++ ++#define GPIO165_PAD PAD_NAND_CE0Z ++#define GPIO165_OEN 0x102b6C, BIT1 ++#define GPIO165_IN 0x102b6C, BIT2 ++#define GPIO165_OUT 0x102b6C, BIT0 ++ ++#define GPIO166_PAD PAD_NAND_REZ ++#define GPIO166_OEN 0x102b73, BIT1 ++#define GPIO166_IN 0x102b73, BIT2 ++#define GPIO166_OUT 0x102b73, BIT0 ++ ++#define GPIO167_PAD PAD_NAND_RBZ ++#define GPIO167_OEN 0x102b6B, BIT1 ++#define GPIO167_IN 0x102b6B, BIT2 ++#define GPIO167_OUT 0x102b6B, BIT0 ++ ++#define GPIO168_PAD PAD_NAND_DA0 ++#define GPIO168_OEN 0x102b62, BIT1 ++#define GPIO168_IN 0x102b62, BIT2 ++#define GPIO168_OUT 0x102b62, BIT0 ++ ++#define GPIO169_PAD PAD_NAND_DA1 ++#define GPIO169_OEN 0x102b63, BIT1 ++#define GPIO169_IN 0x102b63, BIT2 ++#define GPIO169_OUT 0x102b63, BIT0 ++ ++#define GPIO170_PAD PAD_NAND_DA2 ++#define GPIO170_OEN 0x102b64, BIT1 ++#define GPIO170_IN 0x102b64, BIT2 ++#define GPIO170_OUT 0x102b64, BIT0 ++ ++#define GPIO171_PAD PAD_NAND_DA3 ++#define GPIO171_OEN 0x102b65, BIT1 ++#define GPIO171_IN 0x102b65, BIT2 ++#define GPIO171_OUT 0x102b65, BIT0 ++ ++#define GPIO172_PAD PAD_NAND_DQS ++#define GPIO172_OEN 0x102b74, BIT1 ++#define GPIO172_IN 0x102b74, BIT2 ++#define GPIO172_OUT 0x102b74, BIT0 ++ ++#define GPIO173_PAD PAD_NAND_DA4 ++#define GPIO173_OEN 0x102b66, BIT1 ++#define GPIO173_IN 0x102b66, BIT2 ++#define GPIO173_OUT 0x102b66, BIT0 ++ ++#define GPIO174_PAD PAD_NAND_DA5 ++#define GPIO174_OEN 0x102b67, BIT1 ++#define GPIO174_IN 0x102b67, BIT2 ++#define GPIO174_OUT 0x102b67, BIT0 ++ ++#define GPIO175_PAD PAD_NAND_DA6 ++#define GPIO175_OEN 0x102b68, BIT1 ++#define GPIO175_IN 0x102b68, BIT2 ++#define GPIO175_OUT 0x102b68, BIT0 ++ ++#define GPIO176_PAD PAD_NAND_DA7 ++#define GPIO176_OEN 0x102b69, BIT1 ++#define GPIO176_IN 0x102b69, BIT2 ++#define GPIO176_OUT 0x102b69, BIT0 ++ ++#define GPIO177_PAD PAD_SD2_D1 ++#define GPIO177_OEN 0x102b86, BIT1 ++#define GPIO177_IN 0x102b86, BIT2 ++#define GPIO177_OUT 0x102b86, BIT0 ++ ++#define GPIO178_PAD PAD_SD2_D0 ++#define GPIO178_OEN 0x102b85, BIT1 ++#define GPIO178_IN 0x102b85, BIT2 ++#define GPIO178_OUT 0x102b85, BIT0 ++ ++#define GPIO179_PAD PAD_SD2_CLK ++#define GPIO179_OEN 0x102b88, BIT1 ++#define GPIO179_IN 0x102b88, BIT2 ++#define GPIO179_OUT 0x102b88, BIT0 ++ ++#define GPIO180_PAD PAD_SD2_CMD ++#define GPIO180_OEN 0x102b87, BIT1 ++#define GPIO180_IN 0x102b87, BIT2 ++#define GPIO180_OUT 0x102b87, BIT0 ++ ++#define GPIO181_PAD PAD_SD2_D3 ++#define GPIO181_OEN 0x102b8A, BIT1 ++#define GPIO181_IN 0x102b8A, BIT2 ++#define GPIO181_OUT 0x102b8A, BIT0 ++ ++#define GPIO182_PAD PAD_SD2_D2 ++#define GPIO182_OEN 0x102b89, BIT1 ++#define GPIO182_IN 0x102b89, BIT2 ++#define GPIO182_OUT 0x102b89, BIT0 ++ ++ ++ ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), ++ __GPIO(110), __GPIO(111), __GPIO(112), __GPIO(113), __GPIO(114), ++ __GPIO(115), __GPIO(116), __GPIO(117), __GPIO(118), __GPIO(119), ++ __GPIO(120), __GPIO(121), __GPIO(122), __GPIO(123), __GPIO(124), ++ __GPIO(125), __GPIO(126), __GPIO(127), __GPIO(128), __GPIO(129), ++ __GPIO(130), __GPIO(131), __GPIO(132), __GPIO(133), __GPIO(134), ++ __GPIO(135), __GPIO(136), __GPIO(137), __GPIO(138), __GPIO(139), ++ __GPIO(140), __GPIO(141), __GPIO(142), __GPIO(143), __GPIO(144), ++ __GPIO(145), __GPIO(146), __GPIO(147), __GPIO(148), __GPIO(149), ++ __GPIO(150), __GPIO(151), __GPIO(152), __GPIO(153), __GPIO(154), ++ __GPIO(155), __GPIO(156), __GPIO(157), __GPIO(158), __GPIO(159), ++ __GPIO(160), __GPIO(161), __GPIO(162), __GPIO(163), __GPIO(164), ++ __GPIO(165), __GPIO(166), __GPIO(167), __GPIO(168), __GPIO(169), ++ __GPIO(170), __GPIO(171), __GPIO(172), __GPIO(173), __GPIO(174), ++ __GPIO(175), __GPIO(176), __GPIO(177), __GPIO(178), __GPIO(179), ++ __GPIO(180), __GPIO(181), __GPIO(182), ++ ++}; ++#endif ++ ++#define MS_INT_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x80C80) ++#define MS_BACH1_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x89580) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++ MHal_GPIO_REG(REG_ALL_PAD_IN) &= ~BIT0; ++} ++ ++void MHal_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_GPIO_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_GPIO_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++void MHal_GPIO_PAD_32K_OUT(U8 u8Enable) ++{ ++ if (u8Enable) ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,ENABLE,BIT3); ++ else ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT3); ++} ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++ case PAD_PM_GPIO0: ++ case PAD_PM_GPIO1: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT0); ++ break; ++ ++ case PAD_PM_IIC_SDA: ++ case PAD_PM_IIC_SCL: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT2); ++ break; ++ ++ case PAD_PM_MIIC_SDA: ++ case PAD_PM_MIIC_SCL: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT4); ++ break; ++ ++ case PAD_PM_SPI_CK: ++ case PAD_PM_SPI_CZ0: ++ case PAD_PM_SPI_GPIO: ++ case PAD_PM_SPI_DI: ++ case PAD_PM_SPI_DO: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT5|BIT6|BIT7); ++ break; ++ ++ case PAD_ONOFF: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT1); ++ break; ++ ++ case PAD_CHRGDET: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT2); ++ break; ++ ++ case PAD_32K_OUT: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT3); ++ break; ++ ++ case PAD_IRIN: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT3); ++ break; ++ ++ case PAD_CEC: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT1); ++ break; ++ ++ case PAD_PM_SD0_CDZ: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT4); ++ break; ++ ++ case PAD_PM_SD1_CDZ: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT5); ++ break; ++ ++ case PAD_PM_SD2_CDZ: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT6); ++ break; ++ ++ case PAD_SD0_D1: ++ case PAD_SD0_D0: ++ case PAD_SD0_CLK: ++ case PAD_SD0_CMD: ++ case PAD_SD0_D3: ++ case PAD_SD0_D2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_04,DISABLE,BIT0); ++ break; ++ ++ case PAD_SD1_D1: ++ case PAD_SD1_D0: ++ case PAD_SD1_CLK: ++ case PAD_SD1_CMD: ++ case PAD_SD1_D3: ++ case PAD_SD1_D2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_04,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_A_GPS_EVENT: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT6); ++ break; ++ ++ case PAD_AFE1_SGN: ++ case PAD_AFE1_MAG: ++ case PAD_RFSPI_CZ1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT6); ++ break; ++ ++ case PAD_AFE0_SGN: ++ case PAD_AFE0_MAG: ++ case PAD_RFSPI_CZ0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT7); ++ break; ++ ++ case PAD_RFSPI_CLK: ++ case PAD_RFSPI_DATA: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT6|BIT7); ++ break; ++ ++ case PAD_BTI_RX_TX: ++ case PAD_BTI_DATA1: ++ case PAD_BTI_DATA0: ++ case PAD_BT_CLK_24M: ++ case PAD_BT_SPI_SCLK: ++ case PAD_BT_SPI_SDATA: ++ case PAD_BT_SPI_SENB: ++ case PAD_BT_CHIP_EN: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT1); ++ break; ++ ++ case PAD_SR_D0: ++ case PAD_SR_D1: ++ case PAD_SR_D2: ++ case PAD_SR_D3: ++ case PAD_SR_D4: ++ case PAD_SR_D5: ++ case PAD_SR_D6: ++ case PAD_SR_D7: ++ case PAD_SR_PCLK: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT0); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT4); ++ break; ++ ++ case PAD_SR_HSYNC: ++ case PAD_SR_STROBE: ++ case PAD_SR_VSYNC: ++ case PAD_SR_RST: ++ case PAD_SR_PWRDN: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT0); ++ break; ++ ++ case PAD_GPIO33: ++ case PAD_GPIO32: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO31: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT7); ++ break; ++ ++ case PAD_GPIO30: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT6); ++ break; ++ ++ case PAD_GPIO29: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT5); ++ break; ++ ++ case PAD_GPIO28: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT4); ++ OUTREGMSK16(GET_REG_ADDR(MS_BACH1_BASE, 0x16),0x01,0x01); ++ break; ++ ++ case PAD_GPIO27: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_GPIO26: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_GPIO25: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_GPIO24: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ break; ++ ++ case PAD_UART_RX1: ++ case PAD_UART_TX1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT2); ++ break; ++ ++ case PAD_UART_RX2: ++ case PAD_UART_TX2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT3); ++ break; ++ ++ case PAD_UART_RX3: ++ case PAD_UART_TX3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT4); ++ break; ++ ++ case PAD_UART_RX4: ++ case PAD_UART_TX4: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT5); ++ break; ++ ++ case PAD_UART_CTS2: ++ case PAD_UART_RTS2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_CS1Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_03,DISABLE,BIT0); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_CS0Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT4|BIT6); ++ break; ++ ++ case PAD_MPIF_D0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_D1: ++ case PAD_MPIF_D2: ++ case PAD_MPIF_D3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_CK: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_BUSY: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT7); ++ break; ++ ++ case PAD_MIIC0_SDA: ++ case PAD_MIIC0_SCL: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT2); ++ break; ++ ++ case PAD_GPIO23: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_GPIO13: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT3); ++ break; ++ ++ case PAD_GPIO10: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT0); ++ break; ++ ++ case PAD_GPIO9: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT2); ++ break; ++ ++ case PAD_GPIO8: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT0); ++ break; ++ ++ case PAD_GPIO6: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO5: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT5); ++ break; ++ ++ case PAD_GPIO4: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT4); ++ break; ++ ++ case PAD_GPIO3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT3); ++ break; ++ ++ case PAD_GPIO2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT2); ++ break; ++ ++ case PAD_GPIO1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT1); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT0); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT0); ++ break; ++ ++ case PAD_SPDIF_OUT: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT6); ++ break; ++ ++ case PAD_IIS_TRX_BCK: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_IIS_TRX_WS: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_IIS_TRX_OUT: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_IIS_TRX_IN: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_UART_RX5: ++ case PAD_UART_TX5: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT6); ++ break; ++ ++ case PAD_UART_CTS1: ++ case PAD_UART_RTS1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT5); ++ break; ++ ++ case PAD_TCON_GPIO7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT7); ++ break; ++ ++ case PAD_TCON_GPIO5: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT0); ++ break; ++ ++ case PAD_TCON_GPIO3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT2); ++ break; ++ ++ case PAD_TCON_GPIO2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT2); ++ break; ++ ++ case PAD_TCON_GPIO1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT1); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT2); ++ break; ++ ++ case PAD_TCON_GPIO0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT3); ++ break; ++ ++ case PAD_TTL_GPIO11: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO10: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO9: ++ case PAD_TTL_GPIO8: ++ case PAD_TTL_GPIO7: ++ case PAD_TTL_GPIO6: ++ case PAD_TTL_GPIO5: ++ case PAD_TTL_GPIO4: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO1: ++ case PAD_TTL_GPIO0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_NAND_WPZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_ALE: ++ case PAD_NAND_CLE: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_CE3Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT1); ++ break; ++ ++ case PAD_NAND_CE2Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT0); ++ break; ++ ++ case PAD_NAND_CE1Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT7); ++ break; ++ ++ case PAD_NAND_CE0Z: ++ case PAD_NAND_REZ: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_RBZ: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_DQS: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ break; ++ ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_SD2_D1: ++ case PAD_SD2_D0: ++ case PAD_SD2_CLK: ++ case PAD_SD2_CMD: ++ case PAD_SD2_D3: ++ case PAD_SD2_D2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_04,DISABLE,BIT4); ++ break; ++ ++ case PAD_PM_SD_GPIO: ++ case PAD_HOTPLUG: ++ case PAD_BATOK: ++ case PAD_PMIC_CHIPEN: ++ case PAD_PMIC_STDBYN: ++ case PAD_PMIC_INT: ++ case PAD_GPIO34: ++ case PAD_GPIO35: ++ case PAD_GPIO36: ++ case PAD_GPIO37: ++ case PAD_GPIO38: ++ case PAD_GPIO22: ++ case PAD_GPIO21: ++ case PAD_GPIO20: ++ case PAD_GPIO19: ++ case PAD_GPIO18: ++ case PAD_GPIO17: ++ case PAD_GPIO16: ++ case PAD_GPIO15: ++ case PAD_GPIO14: ++ case PAD_GPIO12: ++ case PAD_GPIO11: ++ case PAD_TESTPIN: ++ case PAD_TCON_GPIO8: ++ case PAD_TCON_GPIO6: ++ case PAD_TCON_GPIO4: ++ default: ++ break; ++ } ++} ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break; ++ default: ++ break; ++ } ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u8IndexGPIO) ++ { ++ case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/sstar/gpio/cedric/mhal_gpio.h b/drivers/sstar/gpio/cedric/mhal_gpio.h +new file mode 100755 +index 000000000000..ec0b46c22707 +--- /dev/null ++++ b/drivers/sstar/gpio/cedric/mhal_gpio.h +@@ -0,0 +1,62 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define IO_PHYS 0x1F000000 ++#define MS_BASE_REG_RIU_PA IO_PHYS ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk); ++extern U8 MHal_GPIO_ReadRegBit(U32 u32Reg, U8 u8BitMsk); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/cedric/mhal_gpio_reg.h b/drivers/sstar/gpio/cedric/mhal_gpio_reg.h +new file mode 100755 +index 000000000000..3c5839a4d9b2 +--- /dev/null ++++ b/drivers/sstar/gpio/cedric/mhal_gpio_reg.h +@@ -0,0 +1,79 @@ ++/* ++* mhal_gpio_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++#define GPIO_UNIT_NUM 198 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define REG_MIPS_BASE 0xFD000000//Use 8 bit addressing ++ ++#define REG_ALL_PAD_IN (0x101ea0) //set all pads (except SPI) as input ++#define REG_LVDS_BASE (0x103200) ++#define REG_LVDS_BANK REG_LVDS_BASE ++ ++ ++////8 bit define ++#define REG_PMGPIO_00 0x0f00 ++#define REG_PMGPIO_01 0x0f01 ++#define REG_GPIO1_00 0x101A00////0 ++#define REG_GPIO1_01 0x101A01 ++#define REG_GPIO1_02 0x101A02////1 ++#define REG_GPIO1_03 0x101A03 ++#define REG_GPIO1_04 0x101A04////2 ++#define REG_GPIO1_05 0x101A05 ++#define REG_GPIO1_06 0x101A06////3 ++#define REG_GPIO1_07 0x101A07 ++#define REG_GPIO1_20 0x101A20 ////10 ++#define REG_GPIO1_21 0x101A21 ++#define REG_GPIO1_22 0x101A22 ////11 ++#define REG_GPIO1_23 0x101A23 ++#define REG_GPIO1_24 0x101A24 ////12 ++#define REG_GPIO1_25 0x101A25 ++#define REG_GPIO1_26 0x101A26 ////13 ++#define REG_GPIO1_27 0x101A27 ++#define REG_GPIO1_2A 0x101A2A ////15 ++#define REG_GPIO1_2B 0x101A2B ++#define REG_GPIO1_2C 0x101A2C ////16 ++#define REG_GPIO1_2D 0x101A2D ++ ++ ++ ++ ++#define GPIO_OEN 0 //set o to nake output ++#define GPIO_ODN 1 ++ ++#define IN_HIGH 1 //input high ++#define IN_LOW 0 //input low ++ ++#define OUT_HIGH 1 //output high ++#define OUT_LOW 0 //output low ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_MIPS_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity/Makefile b/drivers/sstar/gpio/infinity/Makefile +new file mode 100755 +index 000000000000..95f53531eafe +--- /dev/null ++++ b/drivers/sstar/gpio/infinity/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for MStar GPIO HAL drivers. ++# ++ ++ ++ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++include $(TOP_DIR)/modules.mk ++endif ++ ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/gpio ++EXTRA_CFLAGS += -Idrivers/sstar/gpio/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# files ++#obj-$(CONFIG_MSTAR_GPIO) += mhal_gpio.o +diff --git a/drivers/sstar/gpio/infinity/mhal_gpio.c b/drivers/sstar/gpio/infinity/mhal_gpio.c +new file mode 100755 +index 000000000000..b97a1dc1b2bc +--- /dev/null ++++ b/drivers/sstar/gpio/infinity/mhal_gpio.c +@@ -0,0 +1,1100 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if 1 ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++//infinity gpio reg start ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103c00, BIT5 ++#define GPIO0_IN 0x103c00, BIT0 ++#define GPIO0_OUT 0x103c00, BIT4 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103c02, BIT5 ++#define GPIO1_IN 0x103c02, BIT0 ++#define GPIO1_OUT 0x103c02, BIT4 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103c04, BIT5 ++#define GPIO2_IN 0x103c04, BIT0 ++#define GPIO2_OUT 0x103c04, BIT4 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103c06, BIT5 ++#define GPIO3_IN 0x103c06, BIT0 ++#define GPIO3_OUT 0x103c06, BIT4 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103c08, BIT5 ++#define GPIO4_IN 0x103c08, BIT0 ++#define GPIO4_OUT 0x103c08, BIT4 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103c0a, BIT5 ++#define GPIO5_IN 0x103c0a, BIT0 ++#define GPIO5_OUT 0x103c0a, BIT4 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103c0c, BIT5 ++#define GPIO6_IN 0x103c0c, BIT0 ++#define GPIO6_OUT 0x103c0c, BIT4 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103c0e, BIT5 ++#define GPIO7_IN 0x103c0e, BIT0 ++#define GPIO7_OUT 0x103c0e, BIT4 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103c10, BIT5 ++#define GPIO8_IN 0x103c10, BIT0 ++#define GPIO8_OUT 0x103c10, BIT4 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103c12, BIT5 ++#define GPIO9_IN 0x103c12, BIT0 ++#define GPIO9_OUT 0x103c12, BIT4 ++ ++#define GPIO10_PAD PAD_GPIO10 ++#define GPIO10_OEN 0x103c14, BIT5 ++#define GPIO10_IN 0x103c14, BIT0 ++#define GPIO10_OUT 0x103c14, BIT4 ++ ++#define GPIO11_PAD PAD_GPIO11 ++#define GPIO11_OEN 0x103c16, BIT5 ++#define GPIO11_IN 0x103c16, BIT0 ++#define GPIO11_OUT 0x103c16, BIT4 ++ ++#define GPIO12_PAD PAD_GPIO12 ++#define GPIO12_OEN 0x103c18, BIT5 ++#define GPIO12_IN 0x103c18, BIT0 ++#define GPIO12_OUT 0x103c18, BIT4 ++ ++#define GPIO13_PAD PAD_GPIO13 ++#define GPIO13_OEN 0x103c1a, BIT5 ++#define GPIO13_IN 0x103c1a, BIT0 ++#define GPIO13_OUT 0x103c1a, BIT4 ++ ++#define GPIO14_PAD PAD_GPIO14 ++#define GPIO14_OEN 0x103c1c, BIT5 ++#define GPIO14_IN 0x103c1c, BIT0 ++#define GPIO14_OUT 0x103c1c, BIT4 ++ ++#define GPIO15_PAD PAD_GPIO15 ++#define GPIO15_OEN 0x103c1e, BIT5 ++#define GPIO15_IN 0x103c1e, BIT0 ++#define GPIO15_OUT 0x103c1e, BIT4 ++ ++#define GPIO16_PAD PAD_PWM0 ++#define GPIO16_OEN 0x103c20, BIT5 ++#define GPIO16_IN 0x103c20, BIT0 ++#define GPIO16_OUT 0x103c20, BIT4 ++ ++#define GPIO17_PAD PAD_PWM1 ++#define GPIO17_OEN 0x103c22, BIT5 ++#define GPIO17_IN 0x103c22, BIT0 ++#define GPIO17_OUT 0x103c22, BIT4 ++ ++#define GPIO18_PAD PAD_FUART_RX ++#define GPIO18_OEN 0x103c28, BIT5 ++#define GPIO18_IN 0x103c28, BIT0 ++#define GPIO18_OUT 0x103c28, BIT4 ++ ++#define GPIO19_PAD PAD_FUART_TX ++#define GPIO19_OEN 0x103c2a, BIT5 ++#define GPIO19_IN 0x103c2a, BIT0 ++#define GPIO19_OUT 0x103c2a, BIT4 ++ ++#define GPIO20_PAD PAD_FUART_CTS ++#define GPIO20_OEN 0x103c2c, BIT5 ++#define GPIO20_IN 0x103c2c, BIT0 ++#define GPIO20_OUT 0x103c2c, BIT4 ++ ++#define GPIO21_PAD PAD_FUART_RTS ++#define GPIO21_OEN 0x103c2e, BIT5 ++#define GPIO21_IN 0x103c2e, BIT0 ++#define GPIO21_OUT 0x103c2e, BIT4 ++ ++#define GPIO22_PAD PAD_UART0_RX ++#define GPIO22_OEN 0x103c30, BIT5 ++#define GPIO22_IN 0x103c30, BIT0 ++#define GPIO22_OUT 0x103c30, BIT4 ++ ++#define GPIO23_PAD PAD_UART0_TX ++#define GPIO23_OEN 0x103c32, BIT5 ++#define GPIO23_IN 0x103c32, BIT0 ++#define GPIO23_OUT 0x103c32, BIT4 ++ ++#define GPIO24_PAD PAD_UART1_RX ++#define GPIO24_OEN 0x103c34, BIT5 ++#define GPIO24_IN 0x103c34, BIT0 ++#define GPIO24_OUT 0x103c34, BIT4 ++ ++#define GPIO25_PAD PAD_UART1_TX ++#define GPIO25_OEN 0x103c36, BIT5 ++#define GPIO25_IN 0x103c36, BIT0 ++#define GPIO25_OUT 0x103c36, BIT4 ++ ++#define GPIO26_PAD PAD_SR_IO00 ++#define GPIO26_OEN 0x103c40, BIT5 ++#define GPIO26_IN 0x103c40, BIT0 ++#define GPIO26_OUT 0x103c40, BIT4 ++ ++#define GPIO27_PAD PAD_SR_IO01 ++#define GPIO27_OEN 0x103c42, BIT5 ++#define GPIO27_IN 0x103c42, BIT0 ++#define GPIO27_OUT 0x103c42, BIT4 ++ ++#define GPIO28_PAD PAD_SR_IO02 ++#define GPIO28_OEN 0x103c44, BIT5 ++#define GPIO28_IN 0x103c44, BIT0 ++#define GPIO28_OUT 0x103c44, BIT4 ++ ++#define GPIO29_PAD PAD_SR_IO03 ++#define GPIO29_OEN 0x103c46, BIT5 ++#define GPIO29_IN 0x103c46, BIT0 ++#define GPIO29_OUT 0x103c46, BIT4 ++ ++#define GPIO30_PAD PAD_SR_IO04 ++#define GPIO30_OEN 0x103c48, BIT5 ++#define GPIO30_IN 0x103c48, BIT0 ++#define GPIO30_OUT 0x103c48, BIT4 ++ ++#define GPIO31_PAD PAD_SR_IO05 ++#define GPIO31_OEN 0x103c4a, BIT5 ++#define GPIO31_IN 0x103c4a, BIT0 ++#define GPIO31_OUT 0x103c4a, BIT4 ++ ++#define GPIO32_PAD PAD_SR_IO06 ++#define GPIO32_OEN 0x103c4c, BIT5 ++#define GPIO32_IN 0x103c4c, BIT0 ++#define GPIO32_OUT 0x103c4c, BIT4 ++ ++#define GPIO33_PAD PAD_SR_IO07 ++#define GPIO33_OEN 0x103c4e, BIT5 ++#define GPIO33_IN 0x103c4e, BIT0 ++#define GPIO33_OUT 0x103c4e, BIT4 ++ ++#define GPIO34_PAD PAD_SR_IO08 ++#define GPIO34_OEN 0x103c50, BIT5 ++#define GPIO34_IN 0x103c50, BIT0 ++#define GPIO34_OUT 0x103c50, BIT4 ++ ++#define GPIO35_PAD PAD_SR_IO09 ++#define GPIO35_OEN 0x103c52, BIT5 ++#define GPIO35_IN 0x103c52, BIT0 ++#define GPIO35_OUT 0x103c52, BIT4 ++ ++#define GPIO36_PAD PAD_SR_IO10 ++#define GPIO36_OEN 0x103c54, BIT5 ++#define GPIO36_IN 0x103c54, BIT0 ++#define GPIO36_OUT 0x103c54, BIT4 ++ ++#define GPIO37_PAD PAD_SR_IO11 ++#define GPIO37_OEN 0x103c56, BIT5 ++#define GPIO37_IN 0x103c56, BIT0 ++#define GPIO37_OUT 0x103c56, BIT4 ++ ++#define GPIO38_PAD PAD_SR_IO12 ++#define GPIO38_OEN 0x103c58, BIT5 ++#define GPIO38_IN 0x103c58, BIT0 ++#define GPIO38_OUT 0x103c58, BIT4 ++ ++#define GPIO39_PAD PAD_SR_IO13 ++#define GPIO39_OEN 0x103c5a, BIT5 ++#define GPIO39_IN 0x103c5a, BIT0 ++#define GPIO39_OUT 0x103c5a, BIT4 ++ ++#define GPIO40_PAD PAD_SR_IO14 ++#define GPIO40_OEN 0x103c5c, BIT5 ++#define GPIO40_IN 0x103c5c, BIT0 ++#define GPIO40_OUT 0x103c5c, BIT4 ++ ++#define GPIO41_PAD PAD_SR_IO15 ++#define GPIO41_OEN 0x103c5e, BIT5 ++#define GPIO41_IN 0x103c5e, BIT0 ++#define GPIO41_OUT 0x103c5e, BIT4 ++ ++#define GPIO42_PAD PAD_SR_IO16 ++#define GPIO42_OEN 0x103c60, BIT5 ++#define GPIO42_IN 0x103c60, BIT0 ++#define GPIO42_OUT 0x103c60, BIT4 ++ ++#define GPIO43_PAD PAD_SR_IO17 ++#define GPIO43_OEN 0x103c62, BIT5 ++#define GPIO43_IN 0x103c62, BIT0 ++#define GPIO43_OUT 0x103c62, BIT4 ++ ++#define GPIO44_PAD PAD_NAND_CEZ ++#define GPIO44_OEN 0x103c80, BIT5 ++#define GPIO44_IN 0x103c80, BIT0 ++#define GPIO44_OUT 0x103c80, BIT4 ++ ++#define GPIO45_PAD PAD_NAND_ALE ++#define GPIO45_OEN 0x103c82, BIT5 ++#define GPIO45_IN 0x103c82, BIT0 ++#define GPIO45_OUT 0x103c82, BIT4 ++ ++#define GPIO46_PAD PAD_NAND_CLE ++#define GPIO46_OEN 0x103c84, BIT5 ++#define GPIO46_IN 0x103c84, BIT0 ++#define GPIO46_OUT 0x103c84, BIT4 ++ ++#define GPIO47_PAD PAD_NAND_WEZ ++#define GPIO47_OEN 0x103c86, BIT5 ++#define GPIO47_IN 0x103c86, BIT0 ++#define GPIO47_OUT 0x103c86, BIT4 ++ ++#define GPIO48_PAD PAD_NAND_WPZ ++#define GPIO48_OEN 0x103c88, BIT5 ++#define GPIO48_IN 0x103c88, BIT0 ++#define GPIO48_OUT 0x103c88, BIT4 ++ ++#define GPIO49_PAD PAD_NAND_REZ ++#define GPIO49_OEN 0x103c8a, BIT5 ++#define GPIO49_IN 0x103c8a, BIT0 ++#define GPIO49_OUT 0x103c8a, BIT4 ++ ++#define GPIO50_PAD PAD_NAND_RBZ ++#define GPIO50_OEN 0x103c8c, BIT5 ++#define GPIO50_IN 0x103c8c, BIT0 ++#define GPIO50_OUT 0x103c8c, BIT4 ++ ++#define GPIO51_PAD PAD_NAND_DA0 ++#define GPIO51_OEN 0x103c8e, BIT5 ++#define GPIO51_IN 0x103c8e, BIT0 ++#define GPIO51_OUT 0x103c8e, BIT4 ++ ++#define GPIO52_PAD PAD_NAND_DA1 ++#define GPIO52_OEN 0x103c90, BIT5 ++#define GPIO52_IN 0x103c90, BIT0 ++#define GPIO52_OUT 0x103c90, BIT4 ++ ++#define GPIO53_PAD PAD_NAND_DA2 ++#define GPIO53_OEN 0x103c92, BIT5 ++#define GPIO53_IN 0x103c92, BIT0 ++#define GPIO53_OUT 0x103c92, BIT4 ++ ++#define GPIO54_PAD PAD_NAND_DA3 ++#define GPIO54_OEN 0x103c94, BIT5 ++#define GPIO54_IN 0x103c94, BIT0 ++#define GPIO54_OUT 0x103c94, BIT4 ++ ++#define GPIO55_PAD PAD_NAND_DA4 ++#define GPIO55_OEN 0x103c96, BIT5 ++#define GPIO55_IN 0x103c96, BIT0 ++#define GPIO55_OUT 0x103c96, BIT4 ++ ++#define GPIO56_PAD PAD_NAND_DA5 ++#define GPIO56_OEN 0x103c98, BIT5 ++#define GPIO56_IN 0x103c98, BIT0 ++#define GPIO56_OUT 0x103c98, BIT4 ++ ++#define GPIO57_PAD PAD_NAND_DA6 ++#define GPIO57_OEN 0x103c9a, BIT5 ++#define GPIO57_IN 0x103c9a, BIT0 ++#define GPIO57_OUT 0x103c9a, BIT4 ++ ++#define GPIO58_PAD PAD_NAND_DA7 ++#define GPIO58_OEN 0x103c9c, BIT5 ++#define GPIO58_IN 0x103c9c, BIT0 ++#define GPIO58_OUT 0x103c9c, BIT4 ++ ++#define GPIO59_PAD PAD_SD_CLK ++#define GPIO59_OEN 0x103ca0, BIT5 ++#define GPIO59_IN 0x103ca0, BIT0 ++#define GPIO59_OUT 0x103ca0, BIT4 ++ ++#define GPIO60_PAD PAD_SD_CMD ++#define GPIO60_OEN 0x103ca2, BIT5 ++#define GPIO60_IN 0x103ca2, BIT0 ++#define GPIO60_OUT 0x103ca2, BIT4 ++ ++#define GPIO61_PAD PAD_SD_D0 ++#define GPIO61_OEN 0x103ca4, BIT5 ++#define GPIO61_IN 0x103ca4, BIT0 ++#define GPIO61_OUT 0x103ca4, BIT4 ++ ++#define GPIO62_PAD PAD_SD_D1 ++#define GPIO62_OEN 0x103ca6, BIT5 ++#define GPIO62_IN 0x103ca6, BIT0 ++#define GPIO62_OUT 0x103ca6, BIT4 ++ ++#define GPIO63_PAD PAD_SD_D2 ++#define GPIO63_OEN 0x103ca8, BIT5 ++#define GPIO63_IN 0x103ca8, BIT0 ++#define GPIO63_OUT 0x103ca8, BIT4 ++ ++#define GPIO64_PAD PAD_SD_D3 ++#define GPIO64_OEN 0x103caa, BIT5 ++#define GPIO64_IN 0x103caa, BIT0 ++#define GPIO64_OUT 0x103caa, BIT4 ++ ++#define GPIO65_PAD PAD_I2C0_SCL ++#define GPIO65_OEN 0x103cc0, BIT5 ++#define GPIO65_IN 0x103cc0, BIT0 ++#define GPIO65_OUT 0x103cc0, BIT4 ++ ++#define GPIO66_PAD PAD_I2C0_SDA ++#define GPIO66_OEN 0x103cc2, BIT5 ++#define GPIO66_IN 0x103cc2, BIT0 ++#define GPIO66_OUT 0x103cc2, BIT4 ++ ++#define GPIO67_PAD PAD_I2C1_SCL ++#define GPIO67_OEN 0x103cc4, BIT5 ++#define GPIO67_IN 0x103cc4, BIT0 ++#define GPIO67_OUT 0x103cc4, BIT4 ++ ++#define GPIO68_PAD PAD_I2C1_SDA ++#define GPIO68_OEN 0x103cc6, BIT5 ++#define GPIO68_IN 0x103cc6, BIT0 ++#define GPIO68_OUT 0x103cc6, BIT4 ++ ++#define GPIO69_PAD PAD_SPI0_CZ ++#define GPIO69_OEN 0x103ce0, BIT5 ++#define GPIO69_IN 0x103ce0, BIT0 ++#define GPIO69_OUT 0x103ce0, BIT4 ++ ++#define GPIO70_PAD PAD_SPI0_CK ++#define GPIO70_OEN 0x103ce2, BIT5 ++#define GPIO70_IN 0x103ce2, BIT0 ++#define GPIO70_OUT 0x103ce2, BIT4 ++ ++#define GPIO71_PAD PAD_SPI0_DI ++#define GPIO71_OEN 0x103ce4, BIT5 ++#define GPIO71_IN 0x103ce4, BIT0 ++#define GPIO71_OUT 0x103ce4, BIT4 ++ ++#define GPIO72_PAD PAD_SPI0_DO ++#define GPIO72_OEN 0x103ce6, BIT5 ++#define GPIO72_IN 0x103ce6, BIT0 ++#define GPIO72_OUT 0x103ce6, BIT4 ++ ++#define GPIO73_PAD PAD_SPI1_CZ ++#define GPIO73_OEN 0x103ce8, BIT5 ++#define GPIO73_IN 0x103ce8, BIT0 ++#define GPIO73_OUT 0x103ce8, BIT4 ++ ++#define GPIO74_PAD PAD_SPI1_CK ++#define GPIO74_OEN 0x103cea, BIT5 ++#define GPIO74_IN 0x103cea, BIT0 ++#define GPIO74_OUT 0x103cea, BIT4 ++ ++#define GPIO75_PAD PAD_SPI1_DI ++#define GPIO75_OEN 0x103cec, BIT5 ++#define GPIO75_IN 0x103cec, BIT0 ++#define GPIO75_OUT 0x103cec, BIT4 ++ ++#define GPIO76_PAD PAD_SPI1_DO ++#define GPIO76_OEN 0x103cee, BIT5 ++#define GPIO76_IN 0x103cee, BIT0 ++#define GPIO76_OUT 0x103cee, BIT4 ++//infinity pm gpio ++#define GPIO77_PAD PAD_PM_SD_CDZ ++#define GPIO77_OEN 0x0f8e, BIT0 ++#define GPIO77_IN 0x0f8e, BIT2 ++#define GPIO77_OUT 0x0f8e, BIT1 ++ ++#define GPIO78_PAD PAD_PM_IRIN ++#define GPIO78_OEN 0x0f28, BIT0 ++#define GPIO78_IN 0x0f28, BIT2 ++#define GPIO78_OUT 0x0f28, BIT1 ++ ++#define GPIO79_PAD PAD_PM_GPIO0 ++#define GPIO79_OEN 0x0f00, BIT0 ++#define GPIO79_IN 0x0f00, BIT2 ++#define GPIO79_OUT 0x0f00, BIT1 ++ ++#define GPIO80_PAD PAD_PM_GPIO1 ++#define GPIO80_OEN 0x0f02, BIT0 ++#define GPIO80_IN 0x0f02, BIT2 ++#define GPIO80_OUT 0x0f02, BIT1 ++ ++#define GPIO81_PAD PAD_PM_GPIO2 ++#define GPIO81_OEN 0x0f04, BIT0 ++#define GPIO81_IN 0x0f04, BIT2 ++#define GPIO81_OUT 0x0f04, BIT1 ++ ++#define GPIO82_PAD PAD_PM_GPIO3 ++#define GPIO82_OEN 0x0f06, BIT0 ++#define GPIO82_IN 0x0f06, BIT2 ++#define GPIO82_OUT 0x0f06, BIT1 ++ ++#define GPIO83_PAD PAD_PM_GPIO4 ++#define GPIO83_OEN 0x0f08, BIT0 ++#define GPIO83_IN 0x0f08, BIT2 ++#define GPIO83_OUT 0x0f08, BIT1 ++ ++#define GPIO84_PAD PAD_PM_GPIO5 ++#define GPIO84_OEN 0x0f0a, BIT0 ++#define GPIO84_IN 0x0f0a, BIT2 ++#define GPIO84_OUT 0x0f0a, BIT1 ++ ++#define GPIO85_PAD PAD_PM_GPIO6 ++#define GPIO85_OEN 0x0f0c, BIT0 ++#define GPIO85_IN 0x0f0c, BIT2 ++#define GPIO85_OUT 0x0f0c, BIT1 ++ ++#define GPIO86_PAD PAD_PM_GPIO7 ++#define GPIO86_OEN 0x0f0e, BIT0 ++#define GPIO86_IN 0x0f0e, BIT2 ++#define GPIO86_OUT 0x0f0e, BIT1 ++ ++#define GPIO87_PAD PAD_PM_GPIO8 ++#define GPIO87_OEN 0x0f10, BIT0 ++#define GPIO87_IN 0x0f10, BIT2 ++#define GPIO87_OUT 0x0f10, BIT1 ++ ++#define GPIO88_PAD PAD_PM_GPIO9 ++#define GPIO88_OEN 0x0f12, BIT0 ++#define GPIO88_IN 0x0f12, BIT2 ++#define GPIO88_OUT 0x0f12, BIT1 ++ ++#define GPIO89_PAD PAD_PM_GPIO10 ++#define GPIO89_OEN 0x0f14, BIT0 ++#define GPIO89_IN 0x0f14, BIT2 ++#define GPIO89_OUT 0x0f14, BIT1 ++ ++#define GPIO90_PAD PAD_PM_SPI_CZ ++#define GPIO90_OEN 0x0f30, BIT0 ++#define GPIO90_IN 0x0f30, BIT2 ++#define GPIO90_OUT 0x0f30, BIT1 ++ ++#define GPIO91_PAD PAD_PM_SPI_CK ++#define GPIO91_OEN 0x0f32, BIT0 ++#define GPIO91_IN 0x0f32, BIT2 ++#define GPIO91_OUT 0x0f32, BIT1 ++ ++#define GPIO92_PAD PAD_PM_SPI_DI ++#define GPIO92_OEN 0x0f34, BIT0 ++#define GPIO92_IN 0x0f34, BIT2 ++#define GPIO92_OUT 0x0f34, BIT1 ++ ++#define GPIO93_PAD PAD_PM_SPI_DO ++#define GPIO93_OEN 0x0f36, BIT0 ++#define GPIO93_IN 0x0f36, BIT2 ++#define GPIO93_OUT 0x0f36, BIT1 ++ ++#define GPIO94_PAD PAD_PM_SPI_WPZ ++#define GPIO94_OEN 0x0f88, BIT0 ++#define GPIO94_IN 0x0f88, BIT2 ++#define GPIO94_OUT 0x0f88, BIT1 ++ ++#define GPIO95_PAD PAD_PM_SPI_HLD ++#define GPIO95_OEN 0x0f8a, BIT0 ++#define GPIO95_IN 0x0f8a, BIT2 ++#define GPIO95_OUT 0x0f8a, BIT1 ++ ++#define GPIO96_PAD PAD_PM_LED0 ++#define GPIO96_OEN 0x0f94, BIT0 ++#define GPIO96_IN 0x0f94, BIT2 ++#define GPIO96_OUT 0x0f94, BIT1 ++ ++#define GPIO97_PAD PAD_PM_LED1 ++#define GPIO97_OEN 0x0f96, BIT0 ++#define GPIO97_IN 0x0f96, BIT2 ++#define GPIO97_OUT 0x0f96, BIT1 ++//SAR GPIO ++#define GPIO98_PAD PAD_SAR_GPIO0 ++#define GPIO98_OEN 0x1423, BIT0 ++#define GPIO98_IN 0x1425, BIT0 ++#define GPIO98_OUT 0x1424, BIT0 ++ ++#define GPIO99_PAD PAD_SAR_GPIO1 ++#define GPIO99_OEN 0x1423, BIT1 ++#define GPIO99_IN 0x1425, BIT1 ++#define GPIO99_OUT 0x1424, BIT1 ++ ++#define GPIO100_PAD PAD_SAR_GPIO2 ++#define GPIO100_OEN 0x1423, BIT2 ++#define GPIO100_IN 0x1425, BIT2 ++#define GPIO100_OUT 0x1424, BIT2 ++ ++#define GPIO101_PAD PAD_SAR_GPIO3 ++#define GPIO101_OEN 0x1423, BIT3 ++#define GPIO101_IN 0x1425, BIT3 ++#define GPIO101_OUT 0x1424, BIT3 ++//ETH GPIO ++#define GPIO102_PAD PAD_ETH_RN ++#define GPIO102_OEN 0x33ee, BIT4 ++#define GPIO102_IN 0x33f0, BIT4 ++#define GPIO102_OUT 0x33f0, BIT0 ++ ++#define GPIO103_PAD PAD_ETH_RP ++#define GPIO103_OEN 0x33ee, BIT5 ++#define GPIO103_IN 0x33f0, BIT5 ++#define GPIO103_OUT 0x33f0, BIT1 ++ ++#define GPIO104_PAD PAD_ETH_TN ++#define GPIO104_OEN 0x33ee, BIT6 ++#define GPIO104_IN 0x33f0, BIT6 ++#define GPIO104_OUT 0x33f0, BIT2 ++ ++#define GPIO105_PAD PAD_ETH_TP ++#define GPIO105_OEN 0x33ee, BIT7 ++#define GPIO105_IN 0x33f0, BIT7 ++#define GPIO105_OUT 0x33f0, BIT3 ++//USB GPIO ++#define GPIO106_PAD PAD_USB_DM ++#define GPIO106_OEN 0x14210a, BIT4 ++#define GPIO106_IN 0x142131, BIT5 ++#define GPIO106_OUT 0x14210a, BIT2 ++ ++#define GPIO107_PAD PAD_USB_DP ++#define GPIO107_OEN 0x14210a, BIT5 ++#define GPIO107_IN 0x142131, BIT4 ++#define GPIO107_OUT 0x14210a, BIT3 ++//infinity gpio reg end ++ ++U32 gChipBaseAddr=0xFD203C00; ++U32 gPmSleepBaseAddr=0xFD001E00; ++U32 gSarBaseAddr=0xFD002800; ++U32 gRIUBaseAddr=0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), ++}; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++// printk("MHal_GPIO_Init gBaseAddr=%x\n",gPadBaseAddr); ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_CHIPTOP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_CHIPTOP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_CHIPTOP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_CHIPTOP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_CHIPTOP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_CHIPTOP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_CHIPTOP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_PM_SLEEP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_PM_SLEEP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_PM_SLEEP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_SAR_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_SAR_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_SAR_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO0: ++ case PAD_GPIO1: ++ case PAD_GPIO2: ++ case PAD_GPIO3: ++ //MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE,DISABLE,BIT0|BIT1); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2S_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO4: ++ case PAD_GPIO5: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO6: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO7: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO8: ++ case PAD_GPIO9: ++ case PAD_GPIO10: ++ case PAD_GPIO11: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO14: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE,BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO15: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE,BIT6); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_PWM0: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ ++ case PAD_PWM1: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ break; ++ case PAD_FUART_RX: ++ case PAD_FUART_TX: ++ case PAD_FUART_CTS: ++ case PAD_FUART_RTS: ++ //MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_UART0_RX: ++ case PAD_UART0_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_UART1_RX: ++ case PAD_UART1_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO00: ++ case PAD_SR_IO01: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO02: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO03: ++ case PAD_SR_IO04: ++ case PAD_SR_IO05: ++ case PAD_SR_IO06: ++ case PAD_SR_IO07: ++ case PAD_SR_IO08: ++ case PAD_SR_IO09: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO10: ++ case PAD_SR_IO11: ++ case PAD_SR_IO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SR_IO13: ++ case PAD_SR_IO14: ++ case PAD_SR_IO15: ++ case PAD_SR_IO16: ++ case PAD_SR_IO17: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ break; ++ case PAD_NAND_ALE: ++ break; ++ case PAD_NAND_CLE: ++ case PAD_NAND_CEZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_WPZ: ++ case PAD_NAND_REZ: ++ case PAD_NAND_RBZ: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_SD_MODE,DISABLE,BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_SD_CLK: ++ case PAD_SD_CMD: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SD_D0: ++ case PAD_SD_D1: ++ case PAD_SD_D2: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SD_D3: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SDIO_MODE,DISABLE,BIT0); ++ break; ++ case PAD_I2C0_SCL: ++ case PAD_I2C0_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_I2C1_SCL: ++ case PAD_I2C1_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ break; ++ ++ case PAD_SPI0_CZ: ++ case PAD_SPI0_CK: ++ case PAD_SPI0_DI: ++ case PAD_SPI0_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SPI1_CZ: ++ case PAD_SPI1_CK: ++ case PAD_SPI1_DI: ++ case PAD_SPI1_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_PM_IRIN: ++ MHal_PM_SLEEP_WriteRegBit(REG_IRIN_MODE,ENABLE,BIT4); ++ break; ++ case PAD_SAR_GPIO0: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT0); ++ break; ++ case PAD_SAR_GPIO1: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT1); ++ break; ++ case PAD_SAR_GPIO2: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT2); ++ break; ++ case PAD_SAR_GPIO3: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT3); ++ break; ++ default: ++ break; ++ ++ } ++} ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++/* case PAD_GPIO7: ++ MHal_CHIPTOP_WriteRegBit(1,DISABLE,BIT7); ++ MHal_CHIPTOP_WriteRegBit(2,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break;*/ ++ default: ++ break; ++ } ++} ++ ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ //160 is PMSLEEP virtual irq start ++ if(u8IndexGPIO==PAD_PM_IRIN) ++ return INT_PMSLEEP_IRIN + 160; ++ else if(u8IndexGPIO>=PAD_PM_GPIO0 && u8IndexGPIO<=PAD_PM_GPIO10) ++ return (u8IndexGPIO - PAD_PM_GPIO0 + (INT_PMSLEEP_GPIO_0+160)); ++ else ++ return -1; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u8IndexGPIO) ++ { ++/* case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++*/ ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/sstar/gpio/infinity/mhal_gpio.h b/drivers/sstar/gpio/infinity/mhal_gpio.h +new file mode 100755 +index 000000000000..e2a2d66b4a24 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity/mhal_gpio.h +@@ -0,0 +1,61 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk); ++extern U8 MHal_GPIO_ReadRegBit(U32 u32Reg, U8 u8BitMsk); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity/mhal_gpio_reg.h b/drivers/sstar/gpio/infinity/mhal_gpio_reg.h +new file mode 100755 +index 000000000000..e2772d39c623 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity/mhal_gpio_reg.h +@@ -0,0 +1,65 @@ ++/* ++* mhal_gpio_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++////8 bit define ++//CHIPTOP ++#define REG_FUART_MODE 0x06 ++#define REG_UART0_MODE 0x06 ++#define REG_UART1_MODE 0x07 ++#define REG_SR_MODE 0x0C ++#define REG_SR_I2C_MODE 0x0C ++#define REG_PWM0_MODE 0x0E ++#define REG_PWM1_MODE 0x0E ++#define REG_PWM2_MODE 0x0E ++#define REG_PWM3_MODE 0x0E ++#define REG_NAND_MODE 0x10 ++#define REG_SD_MODE 0x10 ++#define REG_SDIO_MODE 0x11 ++#define REG_I2C0_MODE 0x12 ++#define REG_I2C1_MODE 0x12 ++#define REG_SPI0_MODE 0x18 ++#define REG_SPI1_MODE 0x18 ++#define REG_EJ_MODE 0x1E ++#define REG_ETH_MODE 0x1E ++#define REG_CCIR_MODE 0x1E ++#define REG_TTL_MODE 0x1E ++#define REG_I2S_MODE 0x1F ++#define REG_DMIC_MODE 0x1F ++#define REG_TEST_IN_MODE 0x24 ++#define REG_TEST_OUT_MODE 0x24 ++#define REG_ALL_PAD_IN 0xA1 ++ ++//PMSLEEP ++#define REG_PMLOCK_L_MODE 0x24 ++#define REG_PMLOCK_H_MODE 0x25 ++#define REG_IRIN_MODE 0x38 ++ ++//SAR ++#define REG_SAR_MODE 0x22 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity2/GPIO_TABLE.h b/drivers/sstar/gpio/infinity2/GPIO_TABLE.h +new file mode 100755 +index 000000000000..03157acdba37 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2/GPIO_TABLE.h +@@ -0,0 +1,1538 @@ ++#define GPIO0_PAD PAD_PM_IRIN ++#define GPIO0_OEN 0x000f28, BIT0 ++#define GPIO0_OUT 0x000f28, BIT1 ++#define GPIO0_IN 0x000f28, BIT2 ++ ++#define GPIO1_PAD PAD_PM_SPI_CZ ++#define GPIO1_OEN 0x000f30, BIT0 ++#define GPIO1_OUT 0x000f30, BIT1 ++#define GPIO1_IN 0x000f30, BIT2 ++ ++#define GPIO2_PAD PAD_PM_SPI_CK ++#define GPIO2_OEN 0x000f32, BIT0 ++#define GPIO2_OUT 0x000f32, BIT1 ++#define GPIO2_IN 0x000f32, BIT2 ++ ++#define GPIO3_PAD PAD_PM_SPI_DI ++#define GPIO3_OEN 0x000f34, BIT0 ++#define GPIO3_OUT 0x000f34, BIT1 ++#define GPIO3_IN 0x000f34, BIT2 ++ ++#define GPIO4_PAD PAD_PM_SPI_DO ++#define GPIO4_OEN 0x000f36, BIT0 ++#define GPIO4_OUT 0x000f36, BIT1 ++#define GPIO4_IN 0x000f36, BIT2 ++ ++#define GPIO5_PAD PAD_PM_SPI_WPZ ++#define GPIO5_OEN 0x000f88, BIT0 ++#define GPIO5_OUT 0x000f88, BIT1 ++#define GPIO5_IN 0x000f88, BIT2 ++ ++#define GPIO6_PAD PAD_PM_SPI_HOLDZ ++#define GPIO6_OEN 0x000f8a, BIT0 ++#define GPIO6_OUT 0x000f8a, BIT1 ++#define GPIO6_IN 0x000f8a, BIT2 ++ ++#define GPIO7_PAD PAD_PM_SPI_RSTZ ++#define GPIO7_OEN 0x000f8c, BIT0 ++#define GPIO7_OUT 0x000f8c, BIT1 ++#define GPIO7_IN 0x000f8c, BIT2 ++ ++#define GPIO8_PAD PAD_PM_GPIO0 ++#define GPIO8_OEN 0x000f00, BIT0 ++#define GPIO8_OUT 0x000f00, BIT1 ++#define GPIO8_IN 0x000f00, BIT2 ++ ++#define GPIO9_PAD PAD_PM_GPIO1 ++#define GPIO9_OEN 0x000f02, BIT0 ++#define GPIO9_OUT 0x000f02, BIT1 ++#define GPIO9_IN 0x000f02, BIT2 ++ ++#define GPIO10_PAD PAD_PM_GPIO2 ++#define GPIO10_OEN 0x000f04, BIT0 ++#define GPIO10_OUT 0x000f04, BIT1 ++#define GPIO10_IN 0x000f04, BIT2 ++ ++#define GPIO11_PAD PAD_PM_GPIO3 ++#define GPIO11_OEN 0x000f06, BIT0 ++#define GPIO11_OUT 0x000f06, BIT1 ++#define GPIO11_IN 0x000f06, BIT2 ++ ++#define GPIO12_PAD PAD_PM_GPIO4 ++#define GPIO12_OEN 0x000f08, BIT0 ++#define GPIO12_OUT 0x000f08, BIT1 ++#define GPIO12_IN 0x000f08, BIT2 ++ ++#define GPIO13_PAD PAD_PM_GPIO5 ++#define GPIO13_OEN 0x000f0a, BIT0 ++#define GPIO13_OUT 0x000f0a, BIT1 ++#define GPIO13_IN 0x000f0a, BIT2 ++ ++#define GPIO14_PAD PAD_PM_GPIO6 ++#define GPIO14_OEN 0x000f0c, BIT0 ++#define GPIO14_OUT 0x000f0c, BIT1 ++#define GPIO14_IN 0x000f0c, BIT2 ++ ++#define GPIO15_PAD PAD_PM_GPIO7 ++#define GPIO15_OEN 0x000f0e, BIT0 ++#define GPIO15_OUT 0x000f0e, BIT1 ++#define GPIO15_IN 0x000f0e, BIT2 ++ ++#define GPIO16_PAD PAD_PM_GPIO8 ++#define GPIO16_OEN 0x000f10, BIT0 ++#define GPIO16_OUT 0x000f10, BIT1 ++#define GPIO16_IN 0x000f10, BIT2 ++ ++#define GPIO17_PAD PAD_PM_GPIO9 ++#define GPIO17_OEN 0x000f12, BIT0 ++#define GPIO17_OUT 0x000f12, BIT1 ++#define GPIO17_IN 0x000f12, BIT2 ++ ++#define GPIO18_PAD PAD_PM_GPIO10 ++#define GPIO18_OEN 0x000f14, BIT0 ++#define GPIO18_OUT 0x000f14, BIT1 ++#define GPIO18_IN 0x000f14, BIT2 ++ ++#define GPIO19_PAD PAD_PM_GPIO11 ++#define GPIO19_OEN 0x000f16, BIT0 ++#define GPIO19_OUT 0x000f16, BIT1 ++#define GPIO19_IN 0x000f16, BIT2 ++ ++#define GPIO20_PAD PAD_PM_GPIO12 ++#define GPIO20_OEN 0x000f18, BIT0 ++#define GPIO20_OUT 0x000f18, BIT1 ++#define GPIO20_IN 0x000f18, BIT2 ++ ++#define GPIO21_PAD PAD_PM_GPIO13 ++#define GPIO21_OEN 0x000f1a, BIT0 ++#define GPIO21_OUT 0x000f1a, BIT1 ++#define GPIO21_IN 0x000f1a, BIT2 ++ ++#define GPIO22_PAD PAD_PM_GPIO14 ++#define GPIO22_OEN 0x000f1c, BIT0 ++#define GPIO22_OUT 0x000f1c, BIT1 ++#define GPIO22_IN 0x000f1c, BIT2 ++ ++#define GPIO23_PAD PAD_PM_GPIO15 ++#define GPIO23_OEN 0x000f1e, BIT0 ++#define GPIO23_OUT 0x000f1e, BIT1 ++#define GPIO23_IN 0x000f1e, BIT2 ++ ++#define GPIO24_PAD PAD_PM_CEC ++#define GPIO24_OEN 0x000f2c, BIT0 ++#define GPIO24_OUT 0x000f2c, BIT1 ++#define GPIO24_IN 0x000f2c, BIT2 ++ ++#define GPIO25_PAD PAD_HDMITX_HPD ++#define GPIO25_OEN 0x001166, BIT3 ++#define GPIO25_OUT 0x001166, BIT2 ++#define GPIO25_IN 0x001166, BIT0 ++ ++#define GPIO26_PAD PAD_HDMIRX_HPD ++#define GPIO26_OEN 0x000e4e, BIT0 ++#define GPIO26_OUT 0x000e4e, BIT4 ++#define GPIO26_IN 0x000e4f, BIT0 ++ ++#define GPIO27_PAD PAD_PM_SD30_CDZ ++#define GPIO27_OEN 0x000f9c, BIT0 ++#define GPIO27_OUT 0x000f9c, BIT1 ++#define GPIO27_IN 0x000f9c, BIT2 ++ ++#define GPIO28_PAD PAD_PM_SD20_CDZ ++#define GPIO28_OEN 0x000f9a, BIT0 ++#define GPIO28_OUT 0x000f9a, BIT1 ++#define GPIO28_IN 0x000f9a, BIT2 ++ ++#define GPIO29_PAD PAD_VID0 ++#define GPIO29_OEN 0x000f90, BIT0 ++#define GPIO29_OUT 0x000f90, BIT1 ++#define GPIO29_IN 0x000f90, BIT2 ++ ++#define GPIO30_PAD PAD_VID1 ++#define GPIO30_OEN 0x000f92, BIT0 ++#define GPIO30_OUT 0x000f92, BIT1 ++#define GPIO30_IN 0x000f92, BIT2 ++ ++#define GPIO31_PAD PAD_PM_LED0 ++#define GPIO31_OEN 0x000f94, BIT0 ++#define GPIO31_OUT 0x000f94, BIT1 ++#define GPIO31_IN 0x000f94, BIT2 ++ ++#define GPIO32_PAD PAD_PM_LED1 ++#define GPIO32_OEN 0x000f96, BIT0 ++#define GPIO32_OUT 0x000f96, BIT1 ++#define GPIO32_IN 0x000f96, BIT2 ++ ++#define GPIO33_PAD PAD_SAR_GPIO0 ++#define GPIO33_OEN 0x001423, BIT0 ++#define GPIO33_OUT 0x001424, BIT0 ++#define GPIO33_IN 0x001425, BIT0 ++ ++#define GPIO34_PAD PAD_SAR_GPIO1 ++#define GPIO34_OEN 0x001423, BIT1 ++#define GPIO34_OUT 0x001424, BIT1 ++#define GPIO34_IN 0x001425, BIT1 ++ ++#define GPIO35_PAD PAD_SAR_GPIO2 ++#define GPIO35_OEN 0x001423, BIT2 ++#define GPIO35_OUT 0x001424, BIT2 ++#define GPIO35_IN 0x001425, BIT2 ++ ++#define GPIO36_PAD PAD_SAR_GPIO3 ++#define GPIO36_OEN 0x001423, BIT3 ++#define GPIO36_OUT 0x001424, BIT3 ++#define GPIO36_IN 0x001425, BIT3 ++ ++#define GPIO37_PAD PAD_SAR_GPIO4 ++#define GPIO37_OEN 0x001423, BIT4 ++#define GPIO37_OUT 0x001424, BIT4 ++#define GPIO37_IN 0x001425, BIT4 ++ ++#define GPIO38_PAD PAD_VPLUG_IN ++#define GPIO38_OEN 0x001423, BIT5 ++#define GPIO38_OUT 0x001424, BIT5 ++#define GPIO38_IN 0x001425, BIT5 ++ ++#define GPIO39_PAD PAD_PM_GPIO16 ++#define GPIO39_OEN 0x000f20, BIT0 ++#define GPIO39_OUT 0x000f20, BIT1 ++#define GPIO39_IN 0x000f20, BIT2 ++ ++#define GPIO40_PAD PAD_PM_GPIO17 ++#define GPIO40_OEN 0x000f22, BIT0 ++#define GPIO40_OUT 0x000f22, BIT1 ++#define GPIO40_IN 0x000f22, BIT2 ++ ++#define GPIO41_PAD PAD_PM_GPIO18 ++#define GPIO41_OEN 0x000f24, BIT0 ++#define GPIO41_OUT 0x000f24, BIT1 ++#define GPIO41_IN 0x000f24, BIT2 ++ ++#define GPIO42_PAD PAD_PM_GPIO19 ++#define GPIO42_OEN 0x000f26, BIT0 ++#define GPIO42_OUT 0x000f26, BIT1 ++#define GPIO42_IN 0x000f26, BIT2 ++ ++#define GPIO43_PAD PAD_PM_SPI_CZ1 ++#define GPIO43_OEN 0x000f98, BIT0 ++#define GPIO43_OUT 0x000f98, BIT1 ++#define GPIO43_IN 0x000f98, BIT2 ++ ++#define GPIO44_PAD PAD_PM_SPI_CZ2 ++#define GPIO44_OEN 0x000f9a, BIT0 ++#define GPIO44_OUT 0x000f9a, BIT1 ++#define GPIO44_IN 0x000f9a, BIT2 ++ ++#define GPIO45_PAD PAD_SPDIF_OUT ++#define GPIO45_OEN 0x1026d7, BIT4 ++#define GPIO45_OUT 0x1026c7, BIT4 ++#define GPIO45_IN 0x102505, BIT5 ++ ++#define GPIO46_PAD PAD_HSYNC_OUT ++#define GPIO46_OEN 0x1026f1, BIT4 ++#define GPIO46_OUT 0x1026c7, BIT5 ++#define GPIO46_IN 0x102525, BIT4 ++ ++#define GPIO47_PAD PAD_VSYNC_OUT ++#define GPIO47_OEN 0x1026f1, BIT5 ++#define GPIO47_OUT 0x1026c7, BIT6 ++#define GPIO47_IN 0x102525, BIT5 ++ ++#define GPIO48_PAD PAD_BT_I2S_RX_BCK ++#define GPIO48_OEN 0x1026cd, BIT0 ++#define GPIO48_OUT 0x1026a0, BIT7 ++#define GPIO48_IN 0x102500, BIT0 ++ ++#define GPIO49_PAD PAD_BT_I2S_RX_WCK ++#define GPIO49_OEN 0x1026cd, BIT1 ++#define GPIO49_OUT 0x1026a1, BIT0 ++#define GPIO49_IN 0x102500, BIT1 ++ ++#define GPIO50_PAD PAD_BT_I2S_RX_SDI ++#define GPIO50_OEN 0x1026cd, BIT2 ++#define GPIO50_OUT 0x1026a1, BIT1 ++#define GPIO50_IN 0x102500, BIT2 ++ ++#define GPIO51_PAD PAD_BT_I2S_TX_SDO ++#define GPIO51_OEN 0x1026cd, BIT3 ++#define GPIO51_OUT 0x1026a1, BIT2 ++#define GPIO51_IN 0x102500, BIT3 ++ ++#define GPIO52_PAD PAD_GPIO0 ++#define GPIO52_OEN 0x1026ce, BIT0 ++#define GPIO52_OUT 0x1026a2, BIT0 ++#define GPIO52_IN 0x10251e, BIT0 ++ ++#define GPIO53_PAD PAD_GPIO1 ++#define GPIO53_OEN 0x1026ce, BIT1 ++#define GPIO53_OUT 0x1026a2, BIT1 ++#define GPIO53_IN 0x10251e, BIT1 ++ ++#define GPIO54_PAD PAD_GPIO2 ++#define GPIO54_OEN 0x1026ce, BIT2 ++#define GPIO54_OUT 0x1026a2, BIT2 ++#define GPIO54_IN 0x10251e, BIT2 ++ ++#define GPIO55_PAD PAD_GPIO3 ++#define GPIO55_OEN 0x1026ce, BIT3 ++#define GPIO55_OUT 0x1026a2, BIT3 ++#define GPIO55_IN 0x10251e, BIT3 ++ ++#define GPIO56_PAD PAD_GPIO4 ++#define GPIO56_OEN 0x1026ce, BIT4 ++#define GPIO56_OUT 0x1026a2, BIT4 ++#define GPIO56_IN 0x10251e, BIT4 ++ ++#define GPIO57_PAD PAD_GPIO5 ++#define GPIO57_OEN 0x1026ce, BIT5 ++#define GPIO57_OUT 0x1026a2, BIT5 ++#define GPIO57_IN 0x10251e, BIT5 ++ ++#define GPIO58_PAD PAD_GPIO6 ++#define GPIO58_OEN 0x1026ce, BIT6 ++#define GPIO58_OUT 0x1026a2, BIT6 ++#define GPIO58_IN 0x10251e, BIT6 ++ ++#define GPIO59_PAD PAD_GPIO7 ++#define GPIO59_OEN 0x1026ce, BIT7 ++#define GPIO59_OUT 0x1026a2, BIT7 ++#define GPIO59_IN 0x10251e, BIT7 ++ ++#define GPIO60_PAD PAD_GPIO8 ++#define GPIO60_OEN 0x1026cf, BIT0 ++#define GPIO60_OUT 0x1026a3, BIT0 ++#define GPIO60_IN 0x10251f, BIT0 ++ ++#define GPIO61_PAD PAD_GPIO9 ++#define GPIO61_OEN 0x1026cf, BIT1 ++#define GPIO61_OUT 0x1026a3, BIT1 ++#define GPIO61_IN 0x10251f, BIT1 ++ ++#define GPIO62_PAD PAD_GPIO10 ++#define GPIO62_OEN 0x1026cf, BIT2 ++#define GPIO62_OUT 0x1026a3, BIT2 ++#define GPIO62_IN 0x10251f, BIT2 ++ ++#define GPIO63_PAD PAD_GPIO11 ++#define GPIO63_OEN 0x1026cf, BIT3 ++#define GPIO63_OUT 0x1026a3, BIT3 ++#define GPIO63_IN 0x10251f, BIT3 ++ ++#define GPIO64_PAD PAD_GPIO12 ++#define GPIO64_OEN 0x1026cf, BIT4 ++#define GPIO64_OUT 0x1026a3, BIT4 ++#define GPIO64_IN 0x10251f, BIT4 ++ ++#define GPIO65_PAD PAD_GPIO13 ++#define GPIO65_OEN 0x1026cf, BIT5 ++#define GPIO65_OUT 0x1026a3, BIT5 ++#define GPIO65_IN 0x10251f, BIT5 ++ ++#define GPIO66_PAD PAD_GPIO14 ++#define GPIO66_OEN 0x1026cf, BIT6 ++#define GPIO66_OUT 0x1026a3, BIT6 ++#define GPIO66_IN 0x10251f, BIT6 ++ ++#define GPIO67_PAD PAD_GPIO15 ++#define GPIO67_OEN 0x1026cf, BIT7 ++#define GPIO67_OUT 0x1026a3, BIT7 ++#define GPIO67_IN 0x10251f, BIT7 ++ ++#define GPIO68_PAD PAD_CODEC_I2S_TX_BCK ++#define GPIO68_OEN 0x1026d0, BIT0 ++#define GPIO68_OUT 0x1026a4, BIT0 ++#define GPIO68_IN 0x102500, BIT4 ++ ++#define GPIO69_PAD PAD_CODEC_I2S_TX_WCK ++#define GPIO69_OEN 0x1026d0, BIT1 ++#define GPIO69_OUT 0x1026a4, BIT1 ++#define GPIO69_IN 0x102500, BIT5 ++ ++#define GPIO70_PAD PAD_CODEC_I2S_TX_SDO ++#define GPIO70_OEN 0x1026d6, BIT2 ++#define GPIO70_OUT 0x1026ac, BIT2 ++#define GPIO70_IN 0x10250a, BIT6 ++ ++#define GPIO71_PAD PAD_CODEC_I2S_RX_MCK ++#define GPIO71_OEN 0x1026d0, BIT3 ++#define GPIO71_OUT 0x1026a4, BIT3 ++#define GPIO71_IN 0x102500, BIT7 ++ ++#define GPIO72_PAD PAD_CODEC_I2S_RX_BCK ++#define GPIO72_OEN 0x1026d0, BIT4 ++#define GPIO72_OUT 0x1026a4, BIT4 ++#define GPIO72_IN 0x102501, BIT0 ++ ++#define GPIO73_PAD PAD_CODEC_I2S_RX_WCK ++#define GPIO73_OEN 0x1026d0, BIT5 ++#define GPIO73_OUT 0x1026a4, BIT5 ++#define GPIO73_IN 0x102501, BIT1 ++ ++#define GPIO74_PAD PAD_CODEC_I2S_RX_SDI0 ++#define GPIO74_OEN 0x1026d0, BIT6 ++#define GPIO74_OUT 0x1026a4, BIT6 ++#define GPIO74_IN 0x102501, BIT2 ++ ++#define GPIO75_PAD PAD_CODEC_I2S_RX_SDI1 ++#define GPIO75_OEN 0x1026d0, BIT7 ++#define GPIO75_OUT 0x1026a4, BIT7 ++#define GPIO75_IN 0x102501, BIT3 ++ ++#define GPIO76_PAD PAD_CODEC_I2S_RX_SDI2 ++#define GPIO76_OEN 0x1026d1, BIT0 ++#define GPIO76_OUT 0x1026a5, BIT0 ++#define GPIO76_IN 0x102501, BIT4 ++ ++#define GPIO77_PAD PAD_CODEC_I2S_RX_SDI3 ++#define GPIO77_OEN 0x1026d1, BIT1 ++#define GPIO77_OUT 0x1026a5, BIT1 ++#define GPIO77_IN 0x102501, BIT5 ++ ++#define GPIO78_PAD PAD_DMIC_BCK ++#define GPIO78_OEN 0x1026ad, BIT0 ++#define GPIO78_OUT 0x1026a6, BIT0 ++#define GPIO78_IN 0x102502, BIT4 ++ ++#define GPIO79_PAD PAD_DMIC_CH0 ++#define GPIO79_OEN 0x1026ad, BIT1 ++#define GPIO79_OUT 0x1026a6, BIT1 ++#define GPIO79_IN 0x102502, BIT5 ++ ++#define GPIO80_PAD PAD_DMIC_CH1 ++#define GPIO80_OEN 0x1026ad, BIT2 ++#define GPIO80_OUT 0x1026a6, BIT2 ++#define GPIO80_IN 0x102502, BIT6 ++ ++#define GPIO81_PAD PAD_DMIC_CH2 ++#define GPIO81_OEN 0x1026ad, BIT3 ++#define GPIO81_OUT 0x1026a6, BIT3 ++#define GPIO81_IN 0x102502, BIT7 ++ ++#define GPIO82_PAD PAD_DMIC_CH3 ++#define GPIO82_OEN 0x1026ad, BIT4 ++#define GPIO82_OUT 0x1026a6, BIT4 ++#define GPIO82_IN 0x102503, BIT0 ++ ++#define GPIO83_PAD PAD_FUART_TX ++#define GPIO83_OEN 0x1026d2, BIT0 ++#define GPIO83_OUT 0x1026a7, BIT0 ++#define GPIO83_IN 0x102502, BIT0 ++ ++#define GPIO84_PAD PAD_FUART_RX ++#define GPIO84_OEN 0x1026d2, BIT1 ++#define GPIO84_OUT 0x1026a7, BIT1 ++#define GPIO84_IN 0x102502, BIT1 ++ ++#define GPIO85_PAD PAD_FUART_RTS ++#define GPIO85_OEN 0x1026d2, BIT2 ++#define GPIO85_OUT 0x1026a7, BIT2 ++#define GPIO85_IN 0x102502, BIT2 ++ ++#define GPIO86_PAD PAD_FUART_CTS ++#define GPIO86_OEN 0x1026d2, BIT3 ++#define GPIO86_OUT 0x1026a7, BIT3 ++#define GPIO86_IN 0x102502, BIT3 ++ ++#define GPIO87_PAD PAD_I2C0_SDA ++#define GPIO87_OEN 0x1026d2, BIT7 ++#define GPIO87_OUT 0x1026a8, BIT0 ++#define GPIO87_IN 0x102504, BIT0 ++ ++#define GPIO88_PAD PAD_I2C0_SCL ++#define GPIO88_OEN 0x1026d3, BIT0 ++#define GPIO88_OUT 0x1026a8, BIT1 ++#define GPIO88_IN 0x102504, BIT1 ++ ++#define GPIO89_PAD PAD_I2C2_SDA ++#define GPIO89_OEN 0x1026d3, BIT1 ++#define GPIO89_OUT 0x1026a8, BIT2 ++#define GPIO89_IN 0x102504, BIT2 ++ ++#define GPIO90_PAD PAD_I2C2_SCL ++#define GPIO90_OEN 0x1026d3, BIT2 ++#define GPIO90_OUT 0x1026a8, BIT3 ++#define GPIO90_IN 0x102504, BIT3 ++ ++#define GPIO91_PAD PAD_I2C3_SCL ++#define GPIO91_OEN 0x1026d3, BIT3 ++#define GPIO91_OUT 0x1026a8, BIT4 ++#define GPIO91_IN 0x102504, BIT4 ++ ++#define GPIO92_PAD PAD_I2C3_SDA ++#define GPIO92_OEN 0x1026d3, BIT4 ++#define GPIO92_OUT 0x1026a8, BIT5 ++#define GPIO92_IN 0x102504, BIT5 ++ ++#define GPIO93_PAD PAD_JTAG_TCK ++#define GPIO93_OEN 0x1026d4, BIT0 ++#define GPIO93_OUT 0x1026a8, BIT6 ++#define GPIO93_IN 0x102505, BIT0 ++ ++#define GPIO94_PAD PAD_JTAG_TDO ++#define GPIO94_OEN 0x1026d4, BIT1 ++#define GPIO94_OUT 0x1026a8, BIT7 ++#define GPIO94_IN 0x102505, BIT1 ++ ++#define GPIO95_PAD PAD_JTAG_TDI ++#define GPIO95_OEN 0x1026d4, BIT2 ++#define GPIO95_OUT 0x1026a9, BIT0 ++#define GPIO95_IN 0x102505, BIT2 ++ ++#define GPIO96_PAD PAD_JTAG_TMS ++#define GPIO96_OEN 0x1026d4, BIT3 ++#define GPIO96_OUT 0x1026a9, BIT1 ++#define GPIO96_IN 0x102505, BIT3 ++ ++#define GPIO97_PAD PAD_MIPI_TX_IO0OUTP_CH0 ++#define GPIO97_OEN 0x1026d4, BIT4 ++#define GPIO97_OUT 0x1026aa, BIT0 ++#define GPIO97_IN 0x102506, BIT0 ++ ++#define GPIO98_PAD PAD_MIPI_TX_IO1OUTN_CH0 ++#define GPIO98_OEN 0x1026d4, BIT5 ++#define GPIO98_OUT 0x1026aa, BIT1 ++#define GPIO98_IN 0x102506, BIT1 ++ ++#define GPIO99_PAD PAD_MIPI_TX_IO2OUTP_CH1 ++#define GPIO99_OEN 0x1026d4, BIT6 ++#define GPIO99_OUT 0x1026aa, BIT2 ++#define GPIO99_IN 0x102506, BIT2 ++ ++#define GPIO100_PAD PAD_MIPI_TX_IO3OUTN_CH1 ++#define GPIO100_OEN 0x1026d4, BIT7 ++#define GPIO100_OUT 0x1026aa, BIT3 ++#define GPIO100_IN 0x102506, BIT3 ++ ++#define GPIO101_PAD PAD_MIPI_TX_IO4OUTP_CH2 ++#define GPIO101_OEN 0x1026d5, BIT0 ++#define GPIO101_OUT 0x1026aa, BIT4 ++#define GPIO101_IN 0x102506, BIT4 ++ ++#define GPIO102_PAD PAD_MIPI_TX_IO5OUTN_CH2 ++#define GPIO102_OEN 0x1026d5, BIT1 ++#define GPIO102_OUT 0x1026aa, BIT5 ++#define GPIO102_IN 0x102506, BIT5 ++ ++#define GPIO103_PAD PAD_MIPI_TX_IO6OUTP_CH3 ++#define GPIO103_OEN 0x1026d5, BIT2 ++#define GPIO103_OUT 0x1026aa, BIT6 ++#define GPIO103_IN 0x102506, BIT6 ++ ++#define GPIO104_PAD PAD_MIPI_TX_IO7OUTN_CH3 ++#define GPIO104_OEN 0x1026d5, BIT3 ++#define GPIO104_OUT 0x1026aa, BIT7 ++#define GPIO104_IN 0x102506, BIT7 ++ ++#define GPIO105_PAD PAD_MIPI_TX_IO8OUTP_CH4 ++#define GPIO105_OEN 0x1026d5, BIT4 ++#define GPIO105_OUT 0x1026ab, BIT0 ++#define GPIO105_IN 0x102507, BIT0 ++ ++#define GPIO106_PAD PAD_MIPI_TX_IO9OUTN_CH4 ++#define GPIO106_OEN 0x1026d5, BIT5 ++#define GPIO106_OUT 0x1026ab, BIT1 ++#define GPIO106_IN 0x102507, BIT1 ++ ++#define GPIO107_PAD PAD_MISC_I2S_TX_BCK ++#define GPIO107_OEN 0x1026d6, BIT0 ++#define GPIO107_OUT 0x1026ac, BIT0 ++#define GPIO107_IN 0x10250a, BIT4 ++ ++#define GPIO108_PAD PAD_MISC_I2S_TX_WCK ++#define GPIO108_OEN 0x1026d6, BIT1 ++#define GPIO108_OUT 0x1026ac, BIT1 ++#define GPIO108_IN 0x10250a, BIT5 ++ ++#define GPIO109_PAD PAD_MISC_I2S_TX_SDO ++#define GPIO109_OEN 0x1026d0, BIT2 ++#define GPIO109_OUT 0x1026a4, BIT2 ++#define GPIO109_IN 0x102500, BIT6 ++ ++#define GPIO110_PAD PAD_MISC_I2S_RX_MCK ++#define GPIO110_OEN 0x1026d6, BIT3 ++#define GPIO110_OUT 0x1026ac, BIT3 ++#define GPIO110_IN 0x10250a, BIT7 ++ ++#define GPIO111_PAD PAD_MISC_I2S_RX_BCK ++#define GPIO111_OEN 0x1026d6, BIT4 ++#define GPIO111_OUT 0x1026ac, BIT4 ++#define GPIO111_IN 0x10250b, BIT0 ++ ++#define GPIO112_PAD PAD_MISC_I2S_RX_WCK ++#define GPIO112_OEN 0x1026d6, BIT5 ++#define GPIO112_OUT 0x1026ac, BIT5 ++#define GPIO112_IN 0x10250b, BIT1 ++ ++#define GPIO113_PAD PAD_MISC_I2S_RX_SDI0 ++#define GPIO113_OEN 0x1026d6, BIT6 ++#define GPIO113_OUT 0x1026ac, BIT6 ++#define GPIO113_IN 0x10250b, BIT2 ++ ++#define GPIO114_PAD PAD_NAND_CEZ0 ++#define GPIO114_OEN 0x1026d8, BIT0 ++#define GPIO114_OUT 0x1026ae, BIT0 ++#define GPIO114_IN 0x102508, BIT0 ++ ++#define GPIO115_PAD PAD_NAND_CEZ1 ++#define GPIO115_OEN 0x1026d8, BIT1 ++#define GPIO115_OUT 0x1026ae, BIT1 ++#define GPIO115_IN 0x102508, BIT1 ++ ++#define GPIO116_PAD PAD_NAND_ALE ++#define GPIO116_OEN 0x1026d8, BIT2 ++#define GPIO116_OUT 0x1026ae, BIT2 ++#define GPIO116_IN 0x102508, BIT2 ++ ++#define GPIO117_PAD PAD_NAND_CLE ++#define GPIO117_OEN 0x10252c, BIT1 ++#define GPIO117_OUT 0x10252c, BIT0 ++#define GPIO117_IN 0x10252c, BIT2 ++ ++#define GPIO118_PAD PAD_NAND_WEZ ++#define GPIO118_OEN 0x1026d8, BIT3 ++#define GPIO118_OUT 0x1026ae, BIT3 ++#define GPIO118_IN 0x102508, BIT3 ++ ++#define GPIO119_PAD PAD_NAND_WPZ ++#define GPIO119_OEN 0x1026d8, BIT4 ++#define GPIO119_OUT 0x1026ae, BIT4 ++#define GPIO119_IN 0x102508, BIT4 ++ ++#define GPIO120_PAD PAD_NAND_REZ ++#define GPIO120_OEN 0x1026d8, BIT5 ++#define GPIO120_OUT 0x1026ae, BIT5 ++#define GPIO120_IN 0x102508, BIT5 ++ ++#define GPIO121_PAD PAD_NAND_RBZ ++#define GPIO121_OEN 0x1026d8, BIT6 ++#define GPIO121_OUT 0x1026ae, BIT6 ++#define GPIO121_IN 0x102508, BIT6 ++ ++#define GPIO122_PAD PAD_NAND_DA0 ++#define GPIO122_OEN 0x1026d8, BIT7 ++#define GPIO122_OUT 0x1026ae, BIT7 ++#define GPIO122_IN 0x102508, BIT7 ++ ++#define GPIO123_PAD PAD_NAND_DA1 ++#define GPIO123_OEN 0x1026d9, BIT0 ++#define GPIO123_OUT 0x1026af, BIT0 ++#define GPIO123_IN 0x102509, BIT0 ++ ++#define GPIO124_PAD PAD_NAND_DA2 ++#define GPIO124_OEN 0x1026d9, BIT1 ++#define GPIO124_OUT 0x1026af, BIT1 ++#define GPIO124_IN 0x102509, BIT1 ++ ++#define GPIO125_PAD PAD_NAND_DA3 ++#define GPIO125_OEN 0x1026d9, BIT2 ++#define GPIO125_OUT 0x1026af, BIT2 ++#define GPIO125_IN 0x102509, BIT2 ++ ++#define GPIO126_PAD PAD_NAND_DA4 ++#define GPIO126_OEN 0x1026d9, BIT3 ++#define GPIO126_OUT 0x1026af, BIT3 ++#define GPIO126_IN 0x102509, BIT3 ++ ++#define GPIO127_PAD PAD_NAND_DA5 ++#define GPIO127_OEN 0x1026d9, BIT4 ++#define GPIO127_OUT 0x1026af, BIT4 ++#define GPIO127_IN 0x102509, BIT4 ++ ++#define GPIO128_PAD PAD_NAND_DA6 ++#define GPIO128_OEN 0x1026d9, BIT5 ++#define GPIO128_OUT 0x1026af, BIT5 ++#define GPIO128_IN 0x102509, BIT5 ++ ++#define GPIO129_PAD PAD_NAND_DA7 ++#define GPIO129_OEN 0x1026d9, BIT6 ++#define GPIO129_OUT 0x1026af, BIT6 ++#define GPIO129_IN 0x102509, BIT6 ++ ++#define GPIO130_PAD PAD_NAND_DQS ++#define GPIO130_OEN 0x1026d9, BIT7 ++#define GPIO130_OUT 0x1026af, BIT7 ++#define GPIO130_IN 0x102509, BIT7 ++ ++#define GPIO131_PAD PAD_RGMII_0_MDIO ++#define GPIO131_OEN 0x1026da, BIT0 ++#define GPIO131_OUT 0x1026b0, BIT0 ++#define GPIO131_IN 0x10250c, BIT0 ++ ++#define GPIO132_PAD PAD_RGMII_0_TX_CTL ++#define GPIO132_OEN 0x1026da, BIT1 ++#define GPIO132_OUT 0x1026b0, BIT1 ++#define GPIO132_IN 0x10250c, BIT1 ++ ++#define GPIO133_PAD PAD_RGMII_0_MDC ++#define GPIO133_OEN 0x1026da, BIT2 ++#define GPIO133_OUT 0x1026b0, BIT2 ++#define GPIO133_IN 0x10250c, BIT2 ++ ++#define GPIO134_PAD PAD_RGMII_0_TXD3 ++#define GPIO134_OEN 0x1026da, BIT3 ++#define GPIO134_OUT 0x1026b0, BIT3 ++#define GPIO134_IN 0x10250c, BIT3 ++ ++#define GPIO135_PAD PAD_RGMII_0_RX_CLK ++#define GPIO135_OEN 0x1026da, BIT4 ++#define GPIO135_OUT 0x1026b0, BIT4 ++#define GPIO135_IN 0x10250c, BIT4 ++ ++#define GPIO136_PAD PAD_RGMII_0_TXD2 ++#define GPIO136_OEN 0x1026da, BIT5 ++#define GPIO136_OUT 0x1026b0, BIT5 ++#define GPIO136_IN 0x10250c, BIT5 ++ ++#define GPIO137_PAD PAD_RGMII_0_RXD3 ++#define GPIO137_OEN 0x1026da, BIT6 ++#define GPIO137_OUT 0x1026b0, BIT6 ++#define GPIO137_IN 0x10250c, BIT6 ++ ++#define GPIO138_PAD PAD_RGMII_0_TXD1 ++#define GPIO138_OEN 0x1026da, BIT7 ++#define GPIO138_OUT 0x1026b0, BIT7 ++#define GPIO138_IN 0x10250c, BIT7 ++ ++#define GPIO139_PAD PAD_RGMII_0_RXD2 ++#define GPIO139_OEN 0x1026db, BIT0 ++#define GPIO139_OUT 0x1026b1, BIT0 ++#define GPIO139_IN 0x10250d, BIT0 ++ ++#define GPIO140_PAD PAD_RGMII_0_TXD0 ++#define GPIO140_OEN 0x1026db, BIT1 ++#define GPIO140_OUT 0x1026b1, BIT1 ++#define GPIO140_IN 0x10250d, BIT1 ++ ++#define GPIO141_PAD PAD_RGMII_0_RXD1 ++#define GPIO141_OEN 0x1026db, BIT2 ++#define GPIO141_OUT 0x1026b1, BIT2 ++#define GPIO141_IN 0x10250d, BIT2 ++ ++#define GPIO142_PAD PAD_RGMII_0_TX_CLK ++#define GPIO142_OEN 0x1026db, BIT3 ++#define GPIO142_OUT 0x1026b1, BIT3 ++#define GPIO142_IN 0x10250d, BIT3 ++ ++#define GPIO143_PAD PAD_RGMII_0_RXD0 ++#define GPIO143_OEN 0x1026db, BIT4 ++#define GPIO143_OUT 0x1026b1, BIT4 ++#define GPIO143_IN 0x10250d, BIT4 ++ ++#define GPIO144_PAD PAD_RGMII_0_RX_CTL ++#define GPIO144_OEN 0x1026db, BIT5 ++#define GPIO144_OUT 0x1026b1, BIT5 ++#define GPIO144_IN 0x10250d, BIT5 ++ ++#define GPIO145_PAD PAD_RGMII_1_TX_CTL ++#define GPIO145_OEN 0x1026dc, BIT0 ++#define GPIO145_OUT 0x1026b2, BIT0 ++#define GPIO145_IN 0x10250e, BIT0 ++ ++#define GPIO146_PAD PAD_RGMII_1_RX_CLK ++#define GPIO146_OEN 0x1026dc, BIT1 ++#define GPIO146_OUT 0x1026b2, BIT1 ++#define GPIO146_IN 0x10250e, BIT1 ++ ++#define GPIO147_PAD PAD_RGMII_1_TXD3 ++#define GPIO147_OEN 0x1026dc, BIT2 ++#define GPIO147_OUT 0x1026b2, BIT2 ++#define GPIO147_IN 0x10250e, BIT2 ++ ++#define GPIO148_PAD PAD_RGMII_1_RXD3 ++#define GPIO148_OEN 0x1026dc, BIT3 ++#define GPIO148_OUT 0x1026b2, BIT3 ++#define GPIO148_IN 0x10250e, BIT3 ++ ++#define GPIO149_PAD PAD_RGMII_1_TXD2 ++#define GPIO149_OEN 0x1026dc, BIT4 ++#define GPIO149_OUT 0x1026b2, BIT4 ++#define GPIO149_IN 0x10250e, BIT4 ++ ++#define GPIO150_PAD PAD_RGMII_1_RXD2 ++#define GPIO150_OEN 0x1026dc, BIT5 ++#define GPIO150_OUT 0x1026b2, BIT5 ++#define GPIO150_IN 0x10250e, BIT5 ++ ++#define GPIO151_PAD PAD_RGMII_1_TXD1 ++#define GPIO151_OEN 0x1026dc, BIT6 ++#define GPIO151_OUT 0x1026b2, BIT6 ++#define GPIO151_IN 0x10250e, BIT6 ++ ++#define GPIO152_PAD PAD_RGMII_1_RXD1 ++#define GPIO152_OEN 0x1026dc, BIT7 ++#define GPIO152_OUT 0x1026b2, BIT7 ++#define GPIO152_IN 0x10250e, BIT7 ++ ++#define GPIO153_PAD PAD_RGMII_1_TXD0 ++#define GPIO153_OEN 0x1026dd, BIT0 ++#define GPIO153_OUT 0x1026b3, BIT0 ++#define GPIO153_IN 0x10250f, BIT0 ++ ++#define GPIO154_PAD PAD_RGMII_1_RXD0 ++#define GPIO154_OEN 0x1026dd, BIT1 ++#define GPIO154_OUT 0x1026b3, BIT1 ++#define GPIO154_IN 0x10250f, BIT1 ++ ++#define GPIO155_PAD PAD_RGMII_1_TX_CLK ++#define GPIO155_OEN 0x1026dd, BIT2 ++#define GPIO155_OUT 0x1026b3, BIT2 ++#define GPIO155_IN 0x10250f, BIT2 ++ ++#define GPIO156_PAD PAD_RGMII_1_RX_CTL ++#define GPIO156_OEN 0x1026dd, BIT3 ++#define GPIO156_OUT 0x1026b3, BIT3 ++#define GPIO156_IN 0x10250f, BIT3 ++ ++#define GPIO157_PAD PAD_PWM0 ++#define GPIO157_OEN 0x1026d6, BIT7 ++#define GPIO157_OUT 0x1026b4, BIT0 ++#define GPIO157_IN 0x10250a, BIT0 ++ ++#define GPIO158_PAD PAD_PWM1 ++#define GPIO158_OEN 0x1026d7, BIT0 ++#define GPIO158_OUT 0x1026b4, BIT1 ++#define GPIO158_IN 0x10250a, BIT1 ++ ++#define GPIO159_PAD PAD_SD_CLK ++#define GPIO159_OEN 0x1026de, BIT0 ++#define GPIO159_OUT 0x1026b4, BIT2 ++#define GPIO159_IN 0x102510, BIT0 ++ ++#define GPIO160_PAD PAD_SD_CMD ++#define GPIO160_OEN 0x1026de, BIT1 ++#define GPIO160_OUT 0x1026b4, BIT3 ++#define GPIO160_IN 0x102510, BIT1 ++ ++#define GPIO161_PAD PAD_SD_D0 ++#define GPIO161_OEN 0x1026de, BIT2 ++#define GPIO161_OUT 0x1026b4, BIT4 ++#define GPIO161_IN 0x102510, BIT2 ++ ++#define GPIO162_PAD PAD_SD_D1 ++#define GPIO162_OEN 0x1026de, BIT3 ++#define GPIO162_OUT 0x1026b4, BIT5 ++#define GPIO162_IN 0x102510, BIT3 ++ ++#define GPIO163_PAD PAD_SD_D2 ++#define GPIO163_OEN 0x1026de, BIT4 ++#define GPIO163_OUT 0x1026b4, BIT6 ++#define GPIO163_IN 0x102510, BIT4 ++ ++#define GPIO164_PAD PAD_SD_D3 ++#define GPIO164_OEN 0x1026de, BIT5 ++#define GPIO164_OUT 0x1026b4, BIT7 ++#define GPIO164_IN 0x102510, BIT5 ++ ++#define GPIO165_PAD PAD_SD30_IO0 ++#define GPIO165_OEN 0x1026df, BIT0 ++#define GPIO165_OUT 0x1026b5, BIT0 ++#define GPIO165_IN 0x102511, BIT0 ++ ++#define GPIO166_PAD PAD_SD30_IO1 ++#define GPIO166_OEN 0x1026df, BIT1 ++#define GPIO166_OUT 0x1026b5, BIT1 ++#define GPIO166_IN 0x102511, BIT1 ++ ++#define GPIO167_PAD PAD_SD30_IO2 ++#define GPIO167_OEN 0x1026df, BIT2 ++#define GPIO167_OUT 0x1026b5, BIT2 ++#define GPIO167_IN 0x102511, BIT2 ++ ++#define GPIO168_PAD PAD_SD30_IO3 ++#define GPIO168_OEN 0x1026df, BIT3 ++#define GPIO168_OUT 0x1026b5, BIT3 ++#define GPIO168_IN 0x102511, BIT3 ++ ++#define GPIO169_PAD PAD_SD30_IO4 ++#define GPIO169_OEN 0x1026df, BIT4 ++#define GPIO169_OUT 0x1026b5, BIT4 ++#define GPIO169_IN 0x102511, BIT4 ++ ++#define GPIO170_PAD PAD_SD30_IO5 ++#define GPIO170_OEN 0x1026df, BIT5 ++#define GPIO170_OUT 0x1026b5, BIT5 ++#define GPIO170_IN 0x102511, BIT5 ++ ++#define GPIO171_PAD PAD_SNR0_D0 ++#define GPIO171_OEN 0x1026e0, BIT0 ++#define GPIO171_OUT 0x1026b6, BIT0 ++#define GPIO171_IN 0x102512, BIT0 ++ ++#define GPIO172_PAD PAD_SNR0_D1 ++#define GPIO172_OEN 0x1026e0, BIT1 ++#define GPIO172_OUT 0x1026b6, BIT1 ++#define GPIO172_IN 0x102512, BIT1 ++ ++#define GPIO173_PAD PAD_SNR0_D2 ++#define GPIO173_OEN 0x1026e0, BIT2 ++#define GPIO173_OUT 0x1026b6, BIT2 ++#define GPIO173_IN 0x102512, BIT2 ++ ++#define GPIO174_PAD PAD_SNR0_D3 ++#define GPIO174_OEN 0x1026e0, BIT3 ++#define GPIO174_OUT 0x1026b6, BIT3 ++#define GPIO174_IN 0x102512, BIT3 ++ ++#define GPIO175_PAD PAD_SNR0_D4 ++#define GPIO175_OEN 0x1026e0, BIT4 ++#define GPIO175_OUT 0x1026b6, BIT4 ++#define GPIO175_IN 0x102512, BIT4 ++ ++#define GPIO176_PAD PAD_SNR0_D5 ++#define GPIO176_OEN 0x1026e0, BIT5 ++#define GPIO176_OUT 0x1026b6, BIT5 ++#define GPIO176_IN 0x102512, BIT5 ++ ++#define GPIO177_PAD PAD_SNR0_D6 ++#define GPIO177_OEN 0x1026e0, BIT6 ++#define GPIO177_OUT 0x1026b6, BIT6 ++#define GPIO177_IN 0x102512, BIT6 ++ ++#define GPIO178_PAD PAD_SNR0_D7 ++#define GPIO178_OEN 0x1026e0, BIT7 ++#define GPIO178_OUT 0x1026b6, BIT7 ++#define GPIO178_IN 0x102512, BIT7 ++ ++#define GPIO179_PAD PAD_SNR0_D8 ++#define GPIO179_OEN 0x1026e1, BIT0 ++#define GPIO179_OUT 0x1026b7, BIT0 ++#define GPIO179_IN 0x102513, BIT0 ++ ++#define GPIO180_PAD PAD_SNR0_D9 ++#define GPIO180_OEN 0x1026e1, BIT1 ++#define GPIO180_OUT 0x1026b7, BIT1 ++#define GPIO180_IN 0x102513, BIT1 ++ ++#define GPIO181_PAD PAD_SNR0_GPIO0 ++#define GPIO181_OEN 0x1026e1, BIT2 ++#define GPIO181_OUT 0x1026b7, BIT2 ++#define GPIO181_IN 0x102513, BIT2 ++ ++#define GPIO182_PAD PAD_SNR0_GPIO1 ++#define GPIO182_OEN 0x1026e1, BIT3 ++#define GPIO182_OUT 0x1026b7, BIT3 ++#define GPIO182_IN 0x102513, BIT3 ++ ++#define GPIO183_PAD PAD_SNR0_GPIO2 ++#define GPIO183_OEN 0x1026e1, BIT4 ++#define GPIO183_OUT 0x1026b7, BIT4 ++#define GPIO183_IN 0x102513, BIT4 ++ ++#define GPIO184_PAD PAD_SNR0_GPIO3 ++#define GPIO184_OEN 0x1026e1, BIT5 ++#define GPIO184_OUT 0x1026b7, BIT5 ++#define GPIO184_IN 0x102513, BIT5 ++ ++#define GPIO185_PAD PAD_SNR0_GPIO4 ++#define GPIO185_OEN 0x1026e1, BIT6 ++#define GPIO185_OUT 0x1026b7, BIT6 ++#define GPIO185_IN 0x102513, BIT6 ++ ++#define GPIO186_PAD PAD_SNR0_GPIO5 ++#define GPIO186_OEN 0x1026e1, BIT7 ++#define GPIO186_OUT 0x1026b7, BIT7 ++#define GPIO186_IN 0x102513, BIT7 ++ ++#define GPIO187_PAD PAD_SNR0_GPIO6 ++#define GPIO187_OEN 0x1026e2, BIT0 ++#define GPIO187_OUT 0x1026b8, BIT0 ++#define GPIO187_IN 0x102514, BIT0 ++ ++#define GPIO188_PAD PAD_SNR0_GPIO7 ++#define GPIO188_OEN 0x1026e2, BIT1 ++#define GPIO188_OUT 0x1026b8, BIT1 ++#define GPIO188_IN 0x102514, BIT1 ++ ++#define GPIO189_PAD PAD_SNR1_D0 ++#define GPIO189_OEN 0x1026e4, BIT0 ++#define GPIO189_OUT 0x1026ba, BIT0 ++#define GPIO189_IN 0x102516, BIT0 ++ ++#define GPIO190_PAD PAD_SNR1_D1 ++#define GPIO190_OEN 0x1026e4, BIT1 ++#define GPIO190_OUT 0x1026ba, BIT1 ++#define GPIO190_IN 0x102516, BIT1 ++ ++#define GPIO191_PAD PAD_SNR1_D2 ++#define GPIO191_OEN 0x1026e4, BIT2 ++#define GPIO191_OUT 0x1026ba, BIT2 ++#define GPIO191_IN 0x102516, BIT2 ++ ++#define GPIO192_PAD PAD_SNR1_D3 ++#define GPIO192_OEN 0x1026e4, BIT3 ++#define GPIO192_OUT 0x1026ba, BIT3 ++#define GPIO192_IN 0x102516, BIT3 ++ ++#define GPIO193_PAD PAD_SNR1_D4 ++#define GPIO193_OEN 0x1026e4, BIT4 ++#define GPIO193_OUT 0x1026ba, BIT4 ++#define GPIO193_IN 0x102516, BIT4 ++ ++#define GPIO194_PAD PAD_SNR1_D5 ++#define GPIO194_OEN 0x1026e4, BIT5 ++#define GPIO194_OUT 0x1026ba, BIT5 ++#define GPIO194_IN 0x102516, BIT5 ++ ++#define GPIO195_PAD PAD_SNR1_D6 ++#define GPIO195_OEN 0x1026e4, BIT6 ++#define GPIO195_OUT 0x1026ba, BIT6 ++#define GPIO195_IN 0x102516, BIT6 ++ ++#define GPIO196_PAD PAD_SNR1_D7 ++#define GPIO196_OEN 0x1026e4, BIT7 ++#define GPIO196_OUT 0x1026ba, BIT7 ++#define GPIO196_IN 0x102516, BIT7 ++ ++#define GPIO197_PAD PAD_SNR1_D8 ++#define GPIO197_OEN 0x1026e5, BIT0 ++#define GPIO197_OUT 0x1026bb, BIT0 ++#define GPIO197_IN 0x102517, BIT0 ++ ++#define GPIO198_PAD PAD_SNR1_D9 ++#define GPIO198_OEN 0x1026e5, BIT1 ++#define GPIO198_OUT 0x1026bb, BIT1 ++#define GPIO198_IN 0x102517, BIT1 ++ ++#define GPIO199_PAD PAD_SNR1_GPIO0 ++#define GPIO199_OEN 0x1026e5, BIT2 ++#define GPIO199_OUT 0x1026bb, BIT2 ++#define GPIO199_IN 0x102517, BIT2 ++ ++#define GPIO200_PAD PAD_SNR1_GPIO1 ++#define GPIO200_OEN 0x1026e5, BIT3 ++#define GPIO200_OUT 0x1026bb, BIT3 ++#define GPIO200_IN 0x102517, BIT3 ++ ++#define GPIO201_PAD PAD_SNR1_GPIO2 ++#define GPIO201_OEN 0x1026e5, BIT4 ++#define GPIO201_OUT 0x1026bb, BIT4 ++#define GPIO201_IN 0x102517, BIT4 ++ ++#define GPIO202_PAD PAD_SNR1_GPIO3 ++#define GPIO202_OEN 0x1026e5, BIT5 ++#define GPIO202_OUT 0x1026bb, BIT5 ++#define GPIO202_IN 0x102517, BIT5 ++ ++#define GPIO203_PAD PAD_SNR1_GPIO4 ++#define GPIO203_OEN 0x1026e5, BIT6 ++#define GPIO203_OUT 0x1026bb, BIT6 ++#define GPIO203_IN 0x102517, BIT6 ++ ++#define GPIO204_PAD PAD_SNR1_GPIO5 ++#define GPIO204_OEN 0x1026e5, BIT7 ++#define GPIO204_OUT 0x1026bb, BIT7 ++#define GPIO204_IN 0x102517, BIT7 ++ ++#define GPIO205_PAD PAD_SNR1_GPIO6 ++#define GPIO205_OEN 0x1026e6, BIT0 ++#define GPIO205_OUT 0x1026bc, BIT0 ++#define GPIO205_IN 0x102518, BIT0 ++ ++#define GPIO206_PAD PAD_SNR1_GPIO7 ++#define GPIO206_OEN 0x1026e6, BIT1 ++#define GPIO206_OUT 0x1026bc, BIT1 ++#define GPIO206_IN 0x102518, BIT1 ++ ++#define GPIO207_PAD PAD_SNR2_D0 ++#define GPIO207_OEN 0x1026e8, BIT0 ++#define GPIO207_OUT 0x1026be, BIT0 ++#define GPIO207_IN 0x10251a, BIT0 ++ ++#define GPIO208_PAD PAD_SNR2_D1 ++#define GPIO208_OEN 0x1026e8, BIT1 ++#define GPIO208_OUT 0x1026be, BIT1 ++#define GPIO208_IN 0x10251a, BIT1 ++ ++#define GPIO209_PAD PAD_SNR2_D2 ++#define GPIO209_OEN 0x1026e8, BIT2 ++#define GPIO209_OUT 0x1026be, BIT2 ++#define GPIO209_IN 0x10251a, BIT2 ++ ++#define GPIO210_PAD PAD_SNR2_D3 ++#define GPIO210_OEN 0x1026e8, BIT3 ++#define GPIO210_OUT 0x1026be, BIT3 ++#define GPIO210_IN 0x10251a, BIT3 ++ ++#define GPIO211_PAD PAD_SNR2_D4 ++#define GPIO211_OEN 0x1026e8, BIT4 ++#define GPIO211_OUT 0x1026be, BIT4 ++#define GPIO211_IN 0x10251a, BIT4 ++ ++#define GPIO212_PAD PAD_SNR2_D5 ++#define GPIO212_OEN 0x1026e8, BIT5 ++#define GPIO212_OUT 0x1026be, BIT5 ++#define GPIO212_IN 0x10251a, BIT5 ++ ++#define GPIO213_PAD PAD_SNR2_D6 ++#define GPIO213_OEN 0x1026e8, BIT6 ++#define GPIO213_OUT 0x1026be, BIT6 ++#define GPIO213_IN 0x10251a, BIT6 ++ ++#define GPIO214_PAD PAD_SNR2_D7 ++#define GPIO214_OEN 0x1026e8, BIT7 ++#define GPIO214_OUT 0x1026be, BIT7 ++#define GPIO214_IN 0x10251a, BIT7 ++ ++#define GPIO215_PAD PAD_SNR2_D8 ++#define GPIO215_OEN 0x1026e9, BIT0 ++#define GPIO215_OUT 0x1026bf, BIT0 ++#define GPIO215_IN 0x10251b, BIT0 ++ ++#define GPIO216_PAD PAD_SNR2_D9 ++#define GPIO216_OEN 0x1026e9, BIT1 ++#define GPIO216_OUT 0x1026bf, BIT1 ++#define GPIO216_IN 0x10251b, BIT1 ++ ++#define GPIO217_PAD PAD_SNR2_GPIO0 ++#define GPIO217_OEN 0x1026e9, BIT2 ++#define GPIO217_OUT 0x1026bf, BIT2 ++#define GPIO217_IN 0x10251b, BIT2 ++ ++#define GPIO218_PAD PAD_SNR2_GPIO1 ++#define GPIO218_OEN 0x1026e9, BIT3 ++#define GPIO218_OUT 0x1026bf, BIT3 ++#define GPIO218_IN 0x10251b, BIT3 ++ ++#define GPIO219_PAD PAD_SNR2_GPIO2 ++#define GPIO219_OEN 0x1026e9, BIT4 ++#define GPIO219_OUT 0x1026bf, BIT4 ++#define GPIO219_IN 0x10251b, BIT4 ++ ++#define GPIO220_PAD PAD_SNR2_GPIO3 ++#define GPIO220_OEN 0x1026e9, BIT5 ++#define GPIO220_OUT 0x1026bf, BIT5 ++#define GPIO220_IN 0x10251b, BIT5 ++ ++#define GPIO221_PAD PAD_SNR2_GPIO4 ++#define GPIO221_OEN 0x1026e9, BIT6 ++#define GPIO221_OUT 0x1026bf, BIT6 ++#define GPIO221_IN 0x10251b, BIT6 ++ ++#define GPIO222_PAD PAD_SNR2_GPIO5 ++#define GPIO222_OEN 0x1026e9, BIT7 ++#define GPIO222_OUT 0x1026bf, BIT7 ++#define GPIO222_IN 0x10251b, BIT7 ++ ++#define GPIO223_PAD PAD_SNR2_GPIO6 ++#define GPIO223_OEN 0x1026ea, BIT0 ++#define GPIO223_OUT 0x1026c0, BIT0 ++#define GPIO223_IN 0x10251c, BIT0 ++ ++#define GPIO224_PAD PAD_SNR2_GPIO7 ++#define GPIO224_OEN 0x1026ea, BIT1 ++#define GPIO224_OUT 0x1026c0, BIT1 ++#define GPIO224_IN 0x10251c, BIT1 ++ ++#define GPIO225_PAD PAD_SNR3_D0 ++#define GPIO225_OEN 0x1026ec, BIT0 ++#define GPIO225_OUT 0x1026c2, BIT0 ++#define GPIO225_IN 0x102520, BIT0 ++ ++#define GPIO226_PAD PAD_SNR3_D1 ++#define GPIO226_OEN 0x1026ec, BIT1 ++#define GPIO226_OUT 0x1026c2, BIT1 ++#define GPIO226_IN 0x102520, BIT1 ++ ++#define GPIO227_PAD PAD_SNR3_D2 ++#define GPIO227_OEN 0x1026ec, BIT2 ++#define GPIO227_OUT 0x1026c2, BIT2 ++#define GPIO227_IN 0x102520, BIT2 ++ ++#define GPIO228_PAD PAD_SNR3_D3 ++#define GPIO228_OEN 0x1026ec, BIT3 ++#define GPIO228_OUT 0x1026c2, BIT3 ++#define GPIO228_IN 0x102520, BIT3 ++ ++#define GPIO229_PAD PAD_SNR3_D4 ++#define GPIO229_OEN 0x1026ec, BIT4 ++#define GPIO229_OUT 0x1026c2, BIT4 ++#define GPIO229_IN 0x102520, BIT4 ++ ++#define GPIO230_PAD PAD_SNR3_D5 ++#define GPIO230_OEN 0x1026ec, BIT5 ++#define GPIO230_OUT 0x1026c2, BIT5 ++#define GPIO230_IN 0x102520, BIT5 ++ ++#define GPIO231_PAD PAD_SNR3_D6 ++#define GPIO231_OEN 0x1026ec, BIT6 ++#define GPIO231_OUT 0x1026c2, BIT6 ++#define GPIO231_IN 0x102520, BIT6 ++ ++#define GPIO232_PAD PAD_SNR3_D7 ++#define GPIO232_OEN 0x1026ec, BIT7 ++#define GPIO232_OUT 0x1026c2, BIT7 ++#define GPIO232_IN 0x102520, BIT7 ++ ++#define GPIO233_PAD PAD_SNR3_D8 ++#define GPIO233_OEN 0x1026ed, BIT0 ++#define GPIO233_OUT 0x1026c3, BIT0 ++#define GPIO233_IN 0x102521, BIT0 ++ ++#define GPIO234_PAD PAD_SNR3_D9 ++#define GPIO234_OEN 0x1026ed, BIT1 ++#define GPIO234_OUT 0x1026c3, BIT1 ++#define GPIO234_IN 0x102521, BIT1 ++ ++#define GPIO235_PAD PAD_SNR3_GPIO0 ++#define GPIO235_OEN 0x1026ed, BIT2 ++#define GPIO235_OUT 0x1026c3, BIT2 ++#define GPIO235_IN 0x102521, BIT2 ++ ++#define GPIO236_PAD PAD_SNR3_GPIO1 ++#define GPIO236_OEN 0x1026ed, BIT3 ++#define GPIO236_OUT 0x1026c3, BIT3 ++#define GPIO236_IN 0x102521, BIT3 ++ ++#define GPIO237_PAD PAD_SNR3_GPIO2 ++#define GPIO237_OEN 0x1026ed, BIT4 ++#define GPIO237_OUT 0x1026c3, BIT4 ++#define GPIO237_IN 0x102521, BIT4 ++ ++#define GPIO238_PAD PAD_SNR3_GPIO3 ++#define GPIO238_OEN 0x1026ed, BIT5 ++#define GPIO238_OUT 0x1026c3, BIT5 ++#define GPIO238_IN 0x102521, BIT5 ++ ++#define GPIO239_PAD PAD_SNR3_GPIO4 ++#define GPIO239_OEN 0x1026ed, BIT6 ++#define GPIO239_OUT 0x1026c3, BIT6 ++#define GPIO239_IN 0x102521, BIT6 ++ ++#define GPIO240_PAD PAD_SNR3_GPIO5 ++#define GPIO240_OEN 0x1026ed, BIT7 ++#define GPIO240_OUT 0x1026c3, BIT7 ++#define GPIO240_IN 0x102521, BIT7 ++ ++#define GPIO241_PAD PAD_SNR3_GPIO6 ++#define GPIO241_OEN 0x1026ee, BIT0 ++#define GPIO241_OUT 0x1026c4, BIT0 ++#define GPIO241_IN 0x102522, BIT0 ++ ++#define GPIO242_PAD PAD_SNR3_GPIO7 ++#define GPIO242_OEN 0x1026ee, BIT1 ++#define GPIO242_OUT 0x1026c4, BIT1 ++#define GPIO242_IN 0x102522, BIT1 ++ ++#define GPIO243_PAD PAD_SPI0_CK ++#define GPIO243_OEN 0x1026f0, BIT0 ++#define GPIO243_OUT 0x1026c6, BIT0 ++#define GPIO243_IN 0x102524, BIT0 ++ ++#define GPIO244_PAD PAD_SPI0_CZ0 ++#define GPIO244_OEN 0x1026f0, BIT1 ++#define GPIO244_OUT 0x1026c6, BIT1 ++#define GPIO244_IN 0x102524, BIT1 ++ ++#define GPIO245_PAD PAD_SPI0_DO ++#define GPIO245_OEN 0x1026f0, BIT2 ++#define GPIO245_OUT 0x1026c6, BIT2 ++#define GPIO245_IN 0x102524, BIT2 ++ ++#define GPIO246_PAD PAD_SPI0_DI ++#define GPIO246_OEN 0x1026f0, BIT3 ++#define GPIO246_OUT 0x1026c6, BIT3 ++#define GPIO246_IN 0x102524, BIT3 ++ ++#define GPIO247_PAD PAD_SPI1_CK ++#define GPIO247_OEN 0x1026f0, BIT4 ++#define GPIO247_OUT 0x1026c6, BIT4 ++#define GPIO247_IN 0x102524, BIT4 ++ ++#define GPIO248_PAD PAD_SPI1_CZ0 ++#define GPIO248_OEN 0x1026f0, BIT5 ++#define GPIO248_OUT 0x1026c6, BIT5 ++#define GPIO248_IN 0x102524, BIT5 ++ ++#define GPIO249_PAD PAD_SPI1_DO ++#define GPIO249_OEN 0x1026f0, BIT6 ++#define GPIO249_OUT 0x1026c6, BIT6 ++#define GPIO249_IN 0x102524, BIT6 ++ ++#define GPIO250_PAD PAD_SPI1_DI ++#define GPIO250_OEN 0x1026f0, BIT7 ++#define GPIO250_OUT 0x1026c6, BIT7 ++#define GPIO250_IN 0x102524, BIT7 ++ ++#define GPIO251_PAD PAD_SPI2_CZ0 ++#define GPIO251_OEN 0x1026f1, BIT0 ++#define GPIO251_OUT 0x1026c7, BIT0 ++#define GPIO251_IN 0x102525, BIT0 ++ ++#define GPIO252_PAD PAD_SPI2_CK ++#define GPIO252_OEN 0x1026f1, BIT1 ++#define GPIO252_OUT 0x1026c7, BIT1 ++#define GPIO252_IN 0x102525, BIT1 ++ ++#define GPIO253_PAD PAD_SPI2_DI ++#define GPIO253_OEN 0x1026f1, BIT2 ++#define GPIO253_OUT 0x1026c7, BIT2 ++#define GPIO253_IN 0x102525, BIT2 ++ ++#define GPIO254_PAD PAD_SPI2_DO ++#define GPIO254_OEN 0x1026f1, BIT3 ++#define GPIO254_OUT 0x1026c7, BIT3 ++#define GPIO254_IN 0x102525, BIT3 ++ ++#define GPIO255_PAD PAD_TTL_HSYNC ++#define GPIO255_OEN 0x1026f2, BIT0 ++#define GPIO255_OUT 0x1026c8, BIT0 ++#define GPIO255_IN 0x102526, BIT0 ++ ++#define GPIO256_PAD PAD_TTL_VSYNC ++#define GPIO256_OEN 0x1026f2, BIT1 ++#define GPIO256_OUT 0x1026c8, BIT1 ++#define GPIO256_IN 0x102526, BIT1 ++ ++#define GPIO257_PAD PAD_TTL_CLK ++#define GPIO257_OEN 0x1026f2, BIT2 ++#define GPIO257_OUT 0x1026c8, BIT2 ++#define GPIO257_IN 0x102526, BIT2 ++ ++#define GPIO258_PAD PAD_TTL_DE ++#define GPIO258_OEN 0x1026f2, BIT3 ++#define GPIO258_OUT 0x1026c8, BIT3 ++#define GPIO258_IN 0x102526, BIT3 ++ ++#define GPIO259_PAD PAD_TTL_D0 ++#define GPIO259_OEN 0x1026f2, BIT4 ++#define GPIO259_OUT 0x1026c8, BIT4 ++#define GPIO259_IN 0x102526, BIT4 ++ ++#define GPIO260_PAD PAD_TTL_D1 ++#define GPIO260_OEN 0x1026f2, BIT5 ++#define GPIO260_OUT 0x1026c8, BIT5 ++#define GPIO260_IN 0x102526, BIT5 ++ ++#define GPIO261_PAD PAD_TTL_D2 ++#define GPIO261_OEN 0x1026f2, BIT6 ++#define GPIO261_OUT 0x1026c8, BIT6 ++#define GPIO261_IN 0x102526, BIT6 ++ ++#define GPIO262_PAD PAD_TTL_D3 ++#define GPIO262_OEN 0x1026f2, BIT7 ++#define GPIO262_OUT 0x1026c8, BIT7 ++#define GPIO262_IN 0x102526, BIT7 ++ ++#define GPIO263_PAD PAD_TTL_D4 ++#define GPIO263_OEN 0x1026f3, BIT0 ++#define GPIO263_OUT 0x1026c9, BIT0 ++#define GPIO263_IN 0x102527, BIT0 ++ ++#define GPIO264_PAD PAD_TTL_D5 ++#define GPIO264_OEN 0x1026f3, BIT1 ++#define GPIO264_OUT 0x1026c9, BIT1 ++#define GPIO264_IN 0x102527, BIT1 ++ ++#define GPIO265_PAD PAD_TTL_D6 ++#define GPIO265_OEN 0x1026f3, BIT2 ++#define GPIO265_OUT 0x1026c9, BIT2 ++#define GPIO265_IN 0x102527, BIT2 ++ ++#define GPIO266_PAD PAD_TTL_D7 ++#define GPIO266_OEN 0x1026f3, BIT3 ++#define GPIO266_OUT 0x1026c9, BIT3 ++#define GPIO266_IN 0x102527, BIT3 ++ ++#define GPIO267_PAD PAD_TTL_D8 ++#define GPIO267_OEN 0x1026f3, BIT4 ++#define GPIO267_OUT 0x1026c9, BIT4 ++#define GPIO267_IN 0x102527, BIT4 ++ ++#define GPIO268_PAD PAD_TTL_D9 ++#define GPIO268_OEN 0x1026f3, BIT5 ++#define GPIO268_OUT 0x1026c9, BIT5 ++#define GPIO268_IN 0x102527, BIT5 ++ ++#define GPIO269_PAD PAD_TTL_D10 ++#define GPIO269_OEN 0x1026f3, BIT6 ++#define GPIO269_OUT 0x1026c9, BIT6 ++#define GPIO269_IN 0x102527, BIT6 ++ ++#define GPIO270_PAD PAD_TTL_D11 ++#define GPIO270_OEN 0x1026f3, BIT7 ++#define GPIO270_OUT 0x1026c9, BIT7 ++#define GPIO270_IN 0x102527, BIT7 ++ ++#define GPIO271_PAD PAD_TTL_D12 ++#define GPIO271_OEN 0x1026f4, BIT0 ++#define GPIO271_OUT 0x1026ca, BIT0 ++#define GPIO271_IN 0x102528, BIT0 ++ ++#define GPIO272_PAD PAD_TTL_D13 ++#define GPIO272_OEN 0x1026f4, BIT1 ++#define GPIO272_OUT 0x1026ca, BIT1 ++#define GPIO272_IN 0x102528, BIT1 ++ ++#define GPIO273_PAD PAD_TTL_D14 ++#define GPIO273_OEN 0x1026f4, BIT2 ++#define GPIO273_OUT 0x1026ca, BIT2 ++#define GPIO273_IN 0x102528, BIT2 ++ ++#define GPIO274_PAD PAD_TTL_D15 ++#define GPIO274_OEN 0x1026f4, BIT3 ++#define GPIO274_OUT 0x1026ca, BIT3 ++#define GPIO274_IN 0x102528, BIT3 ++ ++#define GPIO275_PAD PAD_TTL_D16 ++#define GPIO275_OEN 0x1026f4, BIT4 ++#define GPIO275_OUT 0x1026ca, BIT4 ++#define GPIO275_IN 0x102528, BIT4 ++ ++#define GPIO276_PAD PAD_TTL_D17 ++#define GPIO276_OEN 0x1026f4, BIT5 ++#define GPIO276_OUT 0x1026ca, BIT5 ++#define GPIO276_IN 0x102528, BIT5 ++ ++#define GPIO277_PAD PAD_TTL_D18 ++#define GPIO277_OEN 0x1026f4, BIT6 ++#define GPIO277_OUT 0x1026ca, BIT6 ++#define GPIO277_IN 0x102528, BIT6 ++ ++#define GPIO278_PAD PAD_TTL_D19 ++#define GPIO278_OEN 0x1026f4, BIT7 ++#define GPIO278_OUT 0x1026ca, BIT7 ++#define GPIO278_IN 0x102528, BIT7 ++ ++#define GPIO279_PAD PAD_TTL_D20 ++#define GPIO279_OEN 0x1026f5, BIT0 ++#define GPIO279_OUT 0x1026cb, BIT0 ++#define GPIO279_IN 0x102529, BIT0 ++ ++#define GPIO280_PAD PAD_TTL_D21 ++#define GPIO280_OEN 0x1026f5, BIT1 ++#define GPIO280_OUT 0x1026cb, BIT1 ++#define GPIO280_IN 0x102529, BIT1 ++ ++#define GPIO281_PAD PAD_TTL_D22 ++#define GPIO281_OEN 0x1026f5, BIT2 ++#define GPIO281_OUT 0x1026cb, BIT2 ++#define GPIO281_IN 0x102529, BIT2 ++ ++#define GPIO282_PAD PAD_TTL_D23 ++#define GPIO282_OEN 0x1026f5, BIT3 ++#define GPIO282_OUT 0x1026cb, BIT3 ++#define GPIO282_IN 0x102529, BIT3 ++ ++#define GPIO283_PAD PAD_TTL_GPIO0 ++#define GPIO283_OEN 0x1026f5, BIT4 ++#define GPIO283_OUT 0x1026cb, BIT4 ++#define GPIO283_IN 0x102529, BIT4 ++ ++#define GPIO284_PAD PAD_TTL_GPIO1 ++#define GPIO284_OEN 0x1026f5, BIT5 ++#define GPIO284_OUT 0x1026cb, BIT5 ++#define GPIO284_IN 0x102529, BIT5 ++ ++#define GPIO285_PAD PAD_TTL_GPIO2 ++#define GPIO285_OEN 0x1026f5, BIT6 ++#define GPIO285_OUT 0x1026cb, BIT6 ++#define GPIO285_IN 0x102529, BIT6 ++ ++#define GPIO286_PAD PAD_UART0_RX ++#define GPIO286_OEN 0x1026f6, BIT0 ++#define GPIO286_OUT 0x1026cc, BIT0 ++#define GPIO286_IN 0x10252a, BIT0 ++ ++#define GPIO287_PAD PAD_UART0_TX ++#define GPIO287_OEN 0x1026f6, BIT1 ++#define GPIO287_OUT 0x1026cc, BIT1 ++#define GPIO287_IN 0x10252a, BIT1 ++ ++#define GPIO288_PAD PAD_UART1_RX ++#define GPIO288_OEN 0x1026f6, BIT2 ++#define GPIO288_OUT 0x1026cc, BIT2 ++#define GPIO288_IN 0x10252a, BIT2 ++ ++#define GPIO289_PAD PAD_UART1_TX ++#define GPIO289_OEN 0x1026f6, BIT3 ++#define GPIO289_OUT 0x1026cc, BIT3 ++#define GPIO289_IN 0x10252a, BIT3 ++ ++#define GPIO290_PAD PAD_UART2_RX ++#define GPIO290_OEN 0x1026f6, BIT4 ++#define GPIO290_OUT 0x1026cc, BIT4 ++#define GPIO290_IN 0x10252a, BIT4 ++ ++#define GPIO291_PAD PAD_UART2_TX ++#define GPIO291_OEN 0x1026f6, BIT5 ++#define GPIO291_OUT 0x1026cc, BIT5 ++#define GPIO291_IN 0x10252a, BIT5 ++ ++#define GPIO292_PAD PAD_HDMITX_SCL ++#define GPIO292_OEN 0x1026d2, BIT6 ++#define GPIO292_OUT 0x1026a7, BIT6 ++#define GPIO292_IN 0x102503, BIT6 ++ ++#define GPIO293_PAD PAD_HDMITX_SDA ++#define GPIO293_OEN 0x1026d2, BIT5 ++#define GPIO293_OUT 0x1026a7, BIT5 ++#define GPIO293_IN 0x102503, BIT5 ++ ++#define GPIO294_PAD PAD_HDMITX_ARC ++#define GPIO294_OEN 0x1026d2, BIT4 ++#define GPIO294_OUT 0x1026a7, BIT4 ++#define GPIO294_IN 0x102503, BIT4 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), CONCAT(CONCAT(GPIO, _x_), _OUT), CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), __GPIO(5), __GPIO(6), __GPIO(7), ++ __GPIO(8), __GPIO(9), __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), __GPIO(15), ++ __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), ++ __GPIO(24), __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), __GPIO(30), __GPIO(31), ++ __GPIO(32), __GPIO(33), __GPIO(34), __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), __GPIO(45), __GPIO(46), __GPIO(47), ++ __GPIO(48), __GPIO(49), __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), __GPIO(55), ++ __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), ++ __GPIO(64), __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), __GPIO(70), __GPIO(71), ++ __GPIO(72), __GPIO(73), __GPIO(74), __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), __GPIO(85), __GPIO(86), __GPIO(87), ++ __GPIO(88), __GPIO(89), __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), __GPIO(95), ++ __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), ++ __GPIO(104), __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), __GPIO(110), __GPIO(111), ++ __GPIO(112), __GPIO(113), __GPIO(114), __GPIO(115), __GPIO(116), __GPIO(117), __GPIO(118), __GPIO(119), ++ __GPIO(120), __GPIO(121), __GPIO(122), __GPIO(123), __GPIO(124), __GPIO(125), __GPIO(126), __GPIO(127), ++ __GPIO(128), __GPIO(129), __GPIO(130), __GPIO(131), __GPIO(132), __GPIO(133), __GPIO(134), __GPIO(135), ++ __GPIO(136), __GPIO(137), __GPIO(138), __GPIO(139), __GPIO(140), __GPIO(141), __GPIO(142), __GPIO(143), ++ __GPIO(144), __GPIO(145), __GPIO(146), __GPIO(147), __GPIO(148), __GPIO(149), __GPIO(150), __GPIO(151), ++ __GPIO(152), __GPIO(153), __GPIO(154), __GPIO(155), __GPIO(156), __GPIO(157), __GPIO(158), __GPIO(159), ++ __GPIO(160), __GPIO(161), __GPIO(162), __GPIO(163), __GPIO(164), __GPIO(165), __GPIO(166), __GPIO(167), ++ __GPIO(168), __GPIO(169), __GPIO(170), __GPIO(171), __GPIO(172), __GPIO(173), __GPIO(174), __GPIO(175), ++ __GPIO(176), __GPIO(177), __GPIO(178), __GPIO(179), __GPIO(180), __GPIO(181), __GPIO(182), __GPIO(183), ++ __GPIO(184), __GPIO(185), __GPIO(186), __GPIO(187), __GPIO(188), __GPIO(189), __GPIO(190), __GPIO(191), ++ __GPIO(192), __GPIO(193), __GPIO(194), __GPIO(195), __GPIO(196), __GPIO(197), __GPIO(198), __GPIO(199), ++ __GPIO(200), __GPIO(201), __GPIO(202), __GPIO(203), __GPIO(204), __GPIO(205), __GPIO(206), __GPIO(207), ++ __GPIO(208), __GPIO(209), __GPIO(210), __GPIO(211), __GPIO(212), __GPIO(213), __GPIO(214), __GPIO(215), ++ __GPIO(216), __GPIO(217), __GPIO(218), __GPIO(219), __GPIO(220), __GPIO(221), __GPIO(222), __GPIO(223), ++ __GPIO(224), __GPIO(225), __GPIO(226), __GPIO(227), __GPIO(228), __GPIO(229), __GPIO(230), __GPIO(231), ++ __GPIO(232), __GPIO(233), __GPIO(234), __GPIO(235), __GPIO(236), __GPIO(237), __GPIO(238), __GPIO(239), ++ __GPIO(240), __GPIO(241), __GPIO(242), __GPIO(243), __GPIO(244), __GPIO(245), __GPIO(246), __GPIO(247), ++ __GPIO(248), __GPIO(249), __GPIO(250), __GPIO(251), __GPIO(252), __GPIO(253), __GPIO(254), __GPIO(255), ++ __GPIO(256), __GPIO(257), __GPIO(258), __GPIO(259), __GPIO(260), __GPIO(261), __GPIO(262), __GPIO(263), ++ __GPIO(264), __GPIO(265), __GPIO(266), __GPIO(267), __GPIO(268), __GPIO(269), __GPIO(270), __GPIO(271), ++ __GPIO(272), __GPIO(273), __GPIO(274), __GPIO(275), __GPIO(276), __GPIO(277), __GPIO(278), __GPIO(279), ++ __GPIO(280), __GPIO(281), __GPIO(282), __GPIO(283), __GPIO(284), __GPIO(285), __GPIO(286), __GPIO(287), ++ __GPIO(288), __GPIO(289), __GPIO(290), __GPIO(291), __GPIO(292), __GPIO(293), __GPIO(294), ++}; +\ No newline at end of file +diff --git a/drivers/sstar/gpio/infinity2/Makefile b/drivers/sstar/gpio/infinity2/Makefile +new file mode 100755 +index 000000000000..01cd644f4e48 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2/Makefile +@@ -0,0 +1,14 @@ ++# ++# Makefile for MStar GPIO device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mhal_gpio.o ++obj-$(CONFIG_MS_GPIO) += mhal_pinmux.o +diff --git a/drivers/sstar/gpio/infinity2/mhal_gpio.c b/drivers/sstar/gpio/infinity2/mhal_gpio.c +new file mode 100755 +index 000000000000..208e7054f314 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2/mhal_gpio.c +@@ -0,0 +1,461 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++ ++#include ++#include ++#include ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++#include ++ ++#ifndef MS_ASSERT ++ ++#define MS_ASSERT(expr) do { \ ++ if(!(expr)) \ ++ printk("MVD assert fail %s %d!\n", __FILE__, __LINE__); \ ++} while(0) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++ ++#include "GPIO_TABLE.h" ++ ++U32 gPadTop1BaseAddr=0xFD205200; ++U32 gChipBaseAddr=0xFD203C00; ++U32 gPmSleepBaseAddr=0xFD001C00; ++U32 gSarBaseAddr=0xFD002800; ++U32 gRIUBaseAddr=0xFD000000; ++ ++#define MHal_PADTOP1_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++// printk("MHal_GPIO_Init gBaseAddr=%x\n",gPadBaseAddr); ++ MHal_PADTOP1_REG(REG_ALL_PAD_IN) &= ~BIT0; ++} ++ ++void MHal_CHIPTOP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_CHIPTOP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_CHIPTOP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_CHIPTOP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_CHIPTOP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_CHIPTOP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_CHIPTOP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_PM_SLEEP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_PM_SLEEP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_PM_SLEEP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_SAR_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_SAR_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_SAR_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++void MHal_FuartPAD_DisableFunction(void) ++{ ++ printk("TBD MHal_FuartPAD_DisableFunction\n"); ++} ++ ++void MHal_SPI0PAD_DisableFunction(void) ++{ ++ printk("TBD MHal_FuartPAD_DisableFunction\n"); ++} ++ ++int MHal_GPIO_PadVal_Set(U16 u16IndexGPIO, U32 u32PadMode) ++{ ++ printk("TBD MHal_GPIO_PadVal_Set\n"); ++ return 0; ++} ++int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ printk("TBD MHal_GPIO_PadGroupMode_Set\n"); ++ return 0; ++} ++ ++void MHal_GPIO_Pad_Set(U16 u16IndexGPIO) ++{ ++// printk("[gpio]MHal_GPIO_Pad_Set %d\n", u16IndexGPIO); ++ switch(u16IndexGPIO) ++ { ++ case PAD_SAR_GPIO0: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE, DISABLE, BIT0); ++ break; ++ case PAD_SAR_GPIO1: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE, DISABLE, BIT1); ++ break; ++ case PAD_SAR_GPIO2: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE, DISABLE, BIT2); ++ break; ++ case PAD_SAR_GPIO3: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE, DISABLE, BIT3); ++ break; ++ case PAD_SAR_GPIO4: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE, DISABLE, BIT4); ++ break; ++ default: ++ break; ++ } ++} ++ ++void MHal_GPIO_Pad_Oen(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_oen) &= (~gpio_table[u16IndexGPIO].m_oen); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MHal_GPIO_Pad_Odn(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_oen) |= gpio_table[u16IndexGPIO].m_oen; ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++U16 MHal_GPIO_Pad_Level(U16 u16IndexGPIO) ++{ ++ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ return ((MHal_RIU_REG(gpio_table[u16IndexGPIO].r_in)&gpio_table[u16IndexGPIO].m_in)? 1 : 0); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ return -1; ++ } ++} ++ ++U16 MHal_GPIO_Pad_InOut(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ return ((MHal_RIU_REG(gpio_table[u16IndexGPIO].r_oen)&gpio_table[u16IndexGPIO].m_oen)? 1 : 0); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ return -1; ++ } ++} ++ ++void MHal_GPIO_Pull_High(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_out) |= gpio_table[u16IndexGPIO].m_out; ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MHal_GPIO_Pull_Low(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_out) &= (~gpio_table[u16IndexGPIO].m_out); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MHal_GPIO_Set_High(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_oen) &= (~gpio_table[u16IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_out) |= gpio_table[u16IndexGPIO].m_out; ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MHal_GPIO_Set_Low(U16 u16IndexGPIO) ++{ ++ if (u16IndexGPIO >= 0 && u16IndexGPIO < GPIO_NR) ++ { ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_oen) &= (~gpio_table[u16IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u16IndexGPIO].r_out) &= (~gpio_table[u16IndexGPIO].m_out); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MHal_Enable_GPIO_INT(U16 u16IndexGPIO) ++{ ++/* switch(u8IndexGPIO) ++ { ++ case PAD_GPIO7: ++ MHal_CHIPTOP_WriteRegBit(1,DISABLE,BIT7); ++ MHal_CHIPTOP_WriteRegBit(2,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break; ++ default: ++ break; ++ }*/ ++} ++static int PMSLEEP_GPIO_To_Irq(U16 u16IndexGPIO) ++{ ++ //256 is PMSLEEP virtual irq start ++ ++ if(u16IndexGPIO >= PAD_PM_GPIO0 && u16IndexGPIO <= PAD_PM_GPIO15) ++ return (u16IndexGPIO - (PAD_PM_GPIO0)); ++ ++ else if(u16IndexGPIO >= PAD_PM_GPIO16 && u16IndexGPIO <= PAD_PM_GPIO19) ++ { ++ return (u16IndexGPIO - PAD_PM_GPIO15); ++ } ++ else if(u16IndexGPIO == PAD_PM_IRIN) ++ return INT_PMSLEEP_GPIO_20_IR; ++ ++ else if(u16IndexGPIO == PAD_PM_CEC) ++ return INT_PMSLEEP_GPIO_22_CEC; ++ ++ else if(u16IndexGPIO == PAD_PM_SD30_CDZ) ++ return INT_PMSLEEP_GPIO_78_PAD_PM_SD30_CDZ; ++ ++ else if(u16IndexGPIO == PAD_PM_SD20_CDZ) ++ return INT_PMSLEEP_GPIO_79_PAD_PM_SD20_CDZ; ++ ++ else if(u16IndexGPIO >= PAD_VID0 && u16IndexGPIO <= PAD_PM_LED1) ++ { ++ return (INT_PMSLEEP_GPIO_72_PAD_VID0 + (u16IndexGPIO - PAD_VID0)); ++ } ++ else ++ return -1; ++} ++int MHal_GPIO_To_Irq(U16 u16IndexGPIO) ++{ ++ struct device_node *pm_intr_node; ++ struct irq_domain *pm_intr_domain; ++ struct irq_fwspec fwspec; ++ int hwirq, virq = -1; ++ ++ hwirq = PMSLEEP_GPIO_To_Irq(u16IndexGPIO); ++ ++ if( hwirq >= 0) ++ { ++ //get virtual irq number for request_irq ++ pm_intr_node = of_find_compatible_node(NULL, NULL, "sstar,pm-intc"); ++ pm_intr_domain = irq_find_host(pm_intr_node); ++ ++ if(!pm_intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(pm_intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else ++ { ++ printk("convert fail\r\n"); ++ } ++ return virq; ++} ++ ++void MHal_GPIO_Set_POLARITY(U16 u16IndexGPIO,U8 reverse) ++{ ++//printk("TBD MHal_GPIO_Set_POLARITY\n"); ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u16IndexGPIO) ++ { ++/* case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++*/ ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/sstar/gpio/infinity2/mhal_gpio.h b/drivers/sstar/gpio/infinity2/mhal_gpio.h +new file mode 100755 +index 000000000000..bda2b95754bd +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2/mhal_gpio.h +@@ -0,0 +1,60 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U16 u16IndexGPIO); ++extern int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode); ++extern int MHal_GPIO_PadVal_Set(U16 u16IndexGPIO, U32 u32PadMode); ++extern void MHal_GPIO_Pad_Oen(U16 u16IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U16 u16IndexGPIO); ++extern U16 MHal_GPIO_Pad_Level(U16 u16IndexGPIO); ++extern U16 MHal_GPIO_Pad_InOut(U16 u16IndexGPIO); ++extern void MHal_GPIO_Pull_High(U16 u16IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U16 u16IndexGPIO); ++extern void MHal_GPIO_Set_High(U16 u16IndexGPIO); ++extern void MHal_GPIO_Set_Low(U16 u16IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U16 u16IndexGPIO); ++extern int MHal_GPIO_To_Irq(U16 u16IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U16 u16IndexGPIO, U8 reverse); ++//extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity2/mhal_gpio_reg.h b/drivers/sstar/gpio/infinity2/mhal_gpio_reg.h +new file mode 100755 +index 000000000000..5c211f8a4855 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2/mhal_gpio_reg.h +@@ -0,0 +1,33 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define REG_ALL_PAD_IN 0x00 ++ ++//SAR ++#define REG_SAR_MODE 0x22 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity2/mhal_pinmux.c b/drivers/sstar/gpio/infinity2/mhal_pinmux.c +new file mode 100755 +index 000000000000..506f7ea056b2 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2/mhal_pinmux.c +@@ -0,0 +1,1073 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information!¡Ó) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "padmux.h" ++#include "gpio.h" ++ ++#define PADTOP1_BASE_ADDR 0x1026 ++#define PMSLEEP_BASE_ADDR 0x000E ++#define PM_SAR_BASE_ADDR 0x0014 ++#define ALBANY2_BASE_ADDR 0x0033 ++#define UTMI0_BASE_ADDR 0x1421 ++#define UTMI1_BASE_ADDR 0x1429 ++ ++ ++//16bit offset ++//PADTOP1 ++#define REG_ALL_PAD_IN 0x00 ++#define REG_FORTHUART_MODE 0x01 ++#define REG_SECONDUART_MODE 0x01 ++#define REG_THIRDUART_MODE 0x01 ++#define REG_BT_I2S_RX_0_MODE 0x02 ++#define REG_BT_I2S_TRX_0_MODE 0x02 ++#define REG_BT_I2S_TX_0_MODE 0x02 ++#define REG_CCIR0_16B_MODE 0x02 ++#define REG_CCIR0_8B_MODE 0x02 ++#define REG_CCIR0_CLK_MODE 0x02 ++#define REG_CCIR0_CTRL_MODE 0x02 ++#define REG_CCIR1_8B_MODE 0x02 ++#define REG_CCIR1_CLK_MODE 0x02 ++#define REG_CCIR1_CTRL_MODE 0x02 ++#define REG_CCIR2_16B_MODE 0x02 ++#define REG_CCIR2_8B_MODE 0x02 ++#define REG_CCIR2_CLK_MODE 0x03 ++#define REG_CCIR2_CTRL_MODE 0x03 ++#define REG_CCIR3_8B_MODE 0x03 ++#define REG_CCIR3_CLK_MODE 0x03 ++#define REG_CCIR3_CTRL_MODE 0x03 ++#define REG_CODEC_I2S_RX_0_MODE 0x03 ++#define REG_CODEC_I2S_RX_1_MODE 0x03 ++#define REG_CODEC_I2S_RX_2_MODE 0x03 ++#define REG_CODEC_I2S_RX_3_MODE 0x03 ++#define REG_CODEC_I2S_RX_MCK_MODE 0x03 ++#define REG_CODEC_I2S_TX_0_MODE 0x03 ++#define REG_CODEC_I2S_TX_MUTE_MODE 0x03 ++#define REG_DMIC_0_MODE 0x04 ++#define REG_DMIC_1_MODE 0x04 ++#define REG_DMIC_2_MODE 0x04 ++#define REG_DMIC_3_MODE 0x04 ++#define REG_EJ_CEVA_MODE 0x04 ++#define REG_EJ_MODE 0x04 ++#define REG_EMMC_CONFIG 0x04 ++#define REG_EMMC_RSTN_EN 0x04 ++#define REG_FAST_UART_RTX_MODE 0x05 ++#define REG_FUART_EMMC_MODE 0x05 ++#define REG_FUART_MODE 0x05 ++#define REG_GT0_MDIO 0x05 ++#define REG_GT0_MODE 0x05 ++#define REG_GT1_MODE 0x05 ++#define REG_HDMIRX_ARC_MODE 0x05 ++#define REG_HDMITX_ARC_MODE 0x05 ++#define REG_HDMITX_DDC_MODE 0x05 ++#define REG_HSYNC_EN 0x05 ++#define REG_I2CM0_MODE 0x06 ++#define REG_I2CM1_MODE 0x06 ++#define REG_I2CM2_MODE 0x06 ++#define REG_I2CM3_MODE 0x06 ++#define REG_I2CM4_MODE 0x06 ++#define REG_I2S_IN_MODE 0x06 ++#define REG_I2S_OUT_MODE 0x06 ++#define REG_I2S_OUT_MODE2 0x07 ++#define REG_I2S_OUT_MUTE_MODE 0x07 ++#define REG_I2S_TRX_MODE 0x07 ++#define REG_MIPI_LVDS_TX_2CH_MODE 0x07 ++#define REG_MIPI_LVDS_TX_4CH_MODE 0x07 ++#define REG_MISC_I2S_RX_0_MODE 0x07 ++#define REG_MISC_I2S_RX_MCK_MODE 0x07 ++#define REG_MISC_I2S_TX_0_MODE 0x07 ++#define REG_MISC_I2S_TX_1_MODE 0x07 ++#define REG_MISC_I2S_TX_2_MODE 0x07 ++#define REG_MSPI1_MODE1 0x08 ++#define REG_MSPI1_MODE2 0x08 ++#define REG_MSPI1_MODE3 0x08 ++#define REG_MSPI2_MODE1 0x08 ++#define REG_MSPI3_MODE1 0x08 ++#define REG_NAND_CS1_EN 0x08 ++#define REG_NAND_MODE 0x08 ++#define REG_PWM0_MODE 0x09 ++#define REG_PWM1_MODE 0x09 ++#define REG_PWM2_MODE 0x09 ++#define REG_PWM3_MODE 0x09 ++#define REG_PWM4_MODE 0x09 ++#define REG_PWM5_MODE 0x09 ++#define REG_PWM6_MODE 0x09 ++#define REG_PWM7_MODE 0x09 ++#define REG_RGB_16B_MODE 0x0a ++#define REG_RGB_24B_MODE 0x0a ++#define REG_SATA1_LED_MODE 0x0a ++#define REG_SATA_LED_MODE 0x0a ++#define REG_SD_CONFIG 0x0a ++#define REG_SDIO30_MODE 0x0a ++#define REG_SDIO_MODE 0x0a ++#define REG_SEC_MSPI2_MODE 0x0a ++#define REG_SNR0_IN_MODE 0x0a ++#define REG_SNR1_IN_MODE 0x0a ++#define REG_SNR2_IN_MODE 0x0a ++#define REG_SNR3_IN_MODE 0x0a ++#define REG_SPDIF_IN_MODE 0x0b ++#define REG_SPDIF_OUT_MODE 0x0b ++#define REG_TEST_IN_MODE 0x0b ++#define REG_TEST_OUT_MODE 0x0b ++#define REG_TTL_OUT 0x0b ++#define REG_USB30VCTL_MODE 0x0b ++#define REG_USB30VCTL_MODE1 0x0b ++#define REG_VSYNC_EN 0x0b ++ ++ ++//PMSLEEP ++#define REG_GPIO_PM_LOCK 0x12 ++#define REG_IR_IS_GPIO 0x1c ++#define REG_SD_CDZ_MODE 0x28 ++#define REG_LED_MODE 0x28 ++#define REG_VID_MODE 0x28 ++#define REG_GPU_VID_MODE 0x28 ++#define REG_MIIC_MODE 0x28 ++#define REG_SD_CDZ_MODE 0x28 ++#define REG_PM_PWM0_MODE 0x28 ++#define REG_PM_PWM1_MODE 0x28 ++#define REG_SPI_IS_GPIO 0x35 ++#define REG_MSPI_MODE 0x28 ++#define REG_HDMI_HPD_BYPASS 0x27 ++ ++//SAR ++#define REG_SAR_MODE 0x11 ++ ++//EMAC ALBANY2_BASE_ADDR ++//#define REG_ETH_GPIO_EN 0x71 ++ ++ ++ ++typedef struct stPadmux ++{ ++ U16 padID; ++ U16 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PADMUX; ++ ++ST_PADMUX padmux_table[]= ++{ ++ /* GPIO0-3 - only config as GPIO mode */ ++// {PAD_GPIO0, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO1, PADTOP1_BASE_ADDR, ? , ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO2, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO3, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++ ++ {PAD_GPIO4, PADTOP1_BASE_ADDR, REG_I2CM2_MODE, BIT7|BIT6|BIT5, BIT6|BIT5, PINMUX_FOR_I2CM2_MODE}, /* i2cm2 mode 3 */ ++ {PAD_GPIO5, PADTOP1_BASE_ADDR, REG_I2CM2_MODE, BIT7|BIT6|BIT5, BIT6|BIT5, PINMUX_FOR_I2CM2_MODE}, /* i2cm2 mode 3 */ ++ {PAD_GPIO6, PADTOP1_BASE_ADDR, REG_SATA_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SATA_LED_MODE}, /* sata_led mode 1 */ ++ {PAD_GPIO7, PADTOP1_BASE_ADDR, REG_SATA1_LED_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SATA1_LED_MODE}, /* sata_led mode 1 */ ++ {PAD_GPIO8, PADTOP1_BASE_ADDR, REG_SPDIF_OUT_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SPDIF_OUT_MODE}, /* SPDIF mode 2 */ ++ {PAD_GPIO8, PADTOP1_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_PWM2_MODE}, /* pwm2 mode 1 */ ++ {PAD_GPIO9, PADTOP1_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_PWM3_MODE}, /*pwm3 mode 1 */ ++ {PAD_GPIO10, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT1, PINMUX_FOR_MSPI1_MODE1}, /* mspi1 mode 2*/ ++ {PAD_GPIO10, PADTOP1_BASE_ADDR, REG_PWM4_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM4_MODE}, /* pwm4 mode 1 */ ++ {PAD_GPIO11, PADTOP1_BASE_ADDR, REG_PWM5_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM5_MODE}, /* pwm5 mode 1 */ ++ {PAD_GPIO12, PADTOP1_BASE_ADDR, REG_PWM6_MODE, BIT6|BIT5, BIT5, PINMUX_FOR_PWM6_MODE}, /* pwm6 mode 1 */ ++ {PAD_GPIO13, PADTOP1_BASE_ADDR, REG_PWM7_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_PWM7_MODE}, /* pwm7 mode 1 */ ++ {PAD_GPIO14, PADTOP1_BASE_ADDR, REG_USB30VCTL_MODE, BIT2|BIT1, BIT2|BIT1, PINMUX_FOR_USB30VCTL_MODE}, /* usb30vctl mode 2 */ ++ {PAD_GPIO14, PADTOP1_BASE_ADDR, REG_USB30VCTL_MODE1, BIT4|BIT3, BIT4|BIT3, PINMUX_FOR_USB30VCTL_MODE1}, /* usb30vctl mode 3 */ ++ {PAD_GPIO15, PADTOP1_BASE_ADDR, REG_USB30VCTL_MODE, BIT2|BIT1, BIT2, PINMUX_FOR_USB30VCTL_MODE}, /* usb30vctl mode 2 */ ++ ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT7|BIT6, BIT6, PINMUX_FOR_PMSPI_MODE}, ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_PM_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_VID_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_VID_MODE}, ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_GPU_VID_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_GPU_VID_MODE}, ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_MIIC_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_MIIC_MODE}, ++ {PAD_PM_GPIO1, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT7|BIT6, BIT7, PINMUX_FOR_PMSPI_MODE}, ++ {PAD_PM_GPIO1, PMSLEEP_BASE_ADDR, REG_PM_PWM1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM1_MODE}, ++// {PAD_GPIO2, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++ {PAD_PM_GPIO3, PMSLEEP_BASE_ADDR, REG_VID_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_VID_MODE}, ++ {PAD_PM_GPIO3, PMSLEEP_BASE_ADDR, REG_GPU_VID_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_GPU_VID_MODE}, ++ {PAD_PM_GPIO3, PMSLEEP_BASE_ADDR, REG_MIIC_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_MIIC_MODE}, ++ /* PAD_PM_GPIO4 special case */ ++// {PAD_GPIO5, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO6, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO7, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++ {PAD_PM_GPIO8, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++// {PAD_GPIO9, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO10, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++// {PAD_GPIO11, PADTOP1_BASE_ADDR, ?, ?, ?, PINMUX_FOR_GPIO_MODE}, /* */ ++ {PAD_PM_GPIO12, PMSLEEP_BASE_ADDR, REG_MSPI_MODE, BIT15, BIT15, PINMUX_FOR_PM_MSPI_MODE}, ++ {PAD_PM_GPIO13, PMSLEEP_BASE_ADDR, REG_MSPI_MODE, BIT15, BIT15, PINMUX_FOR_PM_MSPI_MODE}, ++ {PAD_PM_GPIO14, PMSLEEP_BASE_ADDR, REG_MSPI_MODE, BIT15, BIT15, PINMUX_FOR_PM_MSPI_MODE}, ++ {PAD_PM_GPIO15, PMSLEEP_BASE_ADDR, REG_MSPI_MODE, BIT15, BIT15, PINMUX_FOR_PM_MSPI_MODE}, ++ {PAD_HDMITX_HPD, PMSLEEP_BASE_ADDR, REG_HDMI_HPD_BYPASS, BIT15, BIT15, PINMUX_FOR_HDMI_HPD_BYPASS_MODE}, ++ {PAD_PM_SD30_CDZ, PMSLEEP_BASE_ADDR, REG_SD_CDZ_MODE, BIT14, BIT14, PINMUX_FOR_SD_CDZ_MODE}, ++ {PAD_VID0, PMSLEEP_BASE_ADDR, REG_VID_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_VID_MODE}, ++ {PAD_VID0, PMSLEEP_BASE_ADDR, REG_GPU_VID_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_GPU_VID_MODE}, ++ {PAD_VID0, PMSLEEP_BASE_ADDR, REG_MIIC_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_MIIC_MODE}, ++ {PAD_VID1, PMSLEEP_BASE_ADDR, REG_VID_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_VID_MODE}, ++ {PAD_VID1, PMSLEEP_BASE_ADDR, REG_GPU_VID_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_GPU_VID_MODE}, ++ {PAD_VID1, PMSLEEP_BASE_ADDR, REG_MIIC_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_MIIC_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BASE_ADDR, REG_PM_PWM0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PM_PWM0_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BASE_ADDR, REG_PM_PWM1_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PM_PWM1_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ {PAD_SAR_GPIO0, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT0, BIT0, PINMUX_FOR_SAR_MODE}, ++ {PAD_SAR_GPIO1, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT1, BIT1, PINMUX_FOR_SAR_MODE}, ++ {PAD_SAR_GPIO2, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT2, BIT2, PINMUX_FOR_SAR_MODE}, ++ {PAD_SAR_GPIO3, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT3, BIT3, PINMUX_FOR_SAR_MODE}, ++ {PAD_SAR_GPIO4, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT4, BIT4, PINMUX_FOR_SAR_MODE}, ++ {PAD_PM_SPI_CZ1, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT2, BIT2, PINMUX_FOR_PMSPI_MODE}, ++ {PAD_HSYNC_OUT, PADTOP1_BASE_ADDR, REG_THIRDUART_MODE, BIT8|BIT7|BIT6, BIT8, PINMUX_FOR_THIRD_UART_MODE}, ++ {PAD_HSYNC_OUT, PADTOP1_BASE_ADDR, REG_HSYNC_EN, BIT6, BIT6, PINMUX_FOR_HSYNC_EN}, ++ {PAD_VSYNC_OUT, PADTOP1_BASE_ADDR, REG_THIRDUART_MODE, BIT8|BIT7|BIT6, BIT8, PINMUX_FOR_THIRD_UART_MODE}, ++ {PAD_VSYNC_OUT, PADTOP1_BASE_ADDR, REG_VSYNC_EN, BIT5, BIT5, PINMUX_FOR_VSYNC_EN}, ++ {PAD_BT_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_MSPI3_MODE1, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_MSPI3_MODE1}, ++ {PAD_BT_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_BT_I2S_TRX_0_MODE, BIT1, BIT1, PINMUX_FOR_BT_I2S_TRX_0_MODE}, ++ {PAD_BT_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_BT_I2S_RX_0_MODE, BIT0, BIT0, PINMUX_FOR_BT_I2S_RX_0_MODE}, ++ {PAD_BT_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_BT_I2S_TX_0_MODE, BIT2, BIT2, PINMUX_FOR_BT_I2S_TX_0_MODE}, ++ {PAD_BT_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_MSPI3_MODE1, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_MSPI3_MODE1}, ++ {PAD_BT_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_BT_I2S_TRX_0_MODE, BIT1, BIT1, PINMUX_FOR_BT_I2S_TRX_0_MODE}, ++ {PAD_BT_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_BT_I2S_RX_0_MODE, BIT0, BIT0, PINMUX_FOR_BT_I2S_RX_0_MODE}, ++ {PAD_BT_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_BT_I2S_TX_0_MODE, BIT2, BIT2, PINMUX_FOR_BT_I2S_TX_0_MODE}, ++ {PAD_CODEC_I2S_TX_BCK, PADTOP1_BASE_ADDR, REG_CODEC_I2S_TX_0_MODE, BIT14, BIT14, PINMUX_FOR_CODEC_I2S_TX_0_MODE}, ++ {PAD_CODEC_I2S_TX_WCK, PADTOP1_BASE_ADDR, REG_CODEC_I2S_TX_0_MODE, BIT14, BIT14, PINMUX_FOR_CODEC_I2S_TX_0_MODE}, ++ {PAD_CODEC_I2S_TX_SDO, PADTOP1_BASE_ADDR, REG_CODEC_I2S_TX_0_MODE, BIT14, BIT14, PINMUX_FOR_CODEC_I2S_TX_0_MODE}, ++ {PAD_CODEC_I2S_RX_MCK, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_MCK_MODE, BIT13, BIT13, PINMUX_FOR_CODEC_I2S_RX_MCK_MODE}, ++ {PAD_CODEC_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_0_MODE, BIT9, BIT9, PINMUX_FOR_CODEC_I2S_RX_0_MODE}, ++ {PAD_CODEC_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_0_MODE, BIT9, BIT9, PINMUX_FOR_CODEC_I2S_RX_0_MODE}, ++ {PAD_CODEC_I2S_RX_SDI0, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_0_MODE, BIT9, BIT9, PINMUX_FOR_CODEC_I2S_RX_0_MODE}, ++ {PAD_CODEC_I2S_RX_SDI1, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_1_MODE, BIT10, BIT10, PINMUX_FOR_CODEC_I2S_RX_1_MODE}, ++ {PAD_CODEC_I2S_RX_SDI2, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_2_MODE, BIT11, BIT11, PINMUX_FOR_CODEC_I2S_RX_2_MODE}, ++ {PAD_CODEC_I2S_RX_SDI3, PADTOP1_BASE_ADDR, REG_CODEC_I2S_RX_3_MODE, BIT12, BIT12, PINMUX_FOR_CODEC_I2S_RX_3_MODE}, ++ {PAD_DMIC_BCK, PADTOP1_BASE_ADDR, REG_DMIC_0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_BT_DMIC_0_MODE}, ++ {PAD_DMIC_CH0, PADTOP1_BASE_ADDR, REG_DMIC_0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_BT_DMIC_0_MODE}, ++ {PAD_DMIC_CH1, PADTOP1_BASE_ADDR, REG_DMIC_1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_BT_DMIC_1_MODE}, ++ {PAD_DMIC_CH2, PADTOP1_BASE_ADDR, REG_DMIC_2_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_BT_DMIC_2_MODE}, ++ {PAD_DMIC_CH3, PADTOP1_BASE_ADDR, REG_DMIC_3_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_BT_DMIC_3_MODE}, ++ {PAD_FUART_TX, PADTOP1_BASE_ADDR, REG_FAST_UART_RTX_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FAST_UART_RT_MODE}, ++ {PAD_FUART_RX, PADTOP1_BASE_ADDR, REG_FAST_UART_RTX_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FAST_UART_RT_MODE}, ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_FORTHUART_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_FORTH_UART_MODE}, ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_FUART_MODE}, ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_FORTHUART_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_FORTH_UART_MODE}, ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_FUART_MODE}, ++ {PAD_I2C0_SCL, PADTOP1_BASE_ADDR, REG_I2CM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2CM0_EN}, ++ {PAD_I2C0_SCL, PADTOP1_BASE_ADDR, REG_I2CM4_MODE, BIT4|BIT3, BIT4, PINMUX_FOR_I2CM4_MODE}, ++ {PAD_I2C0_SDA, PADTOP1_BASE_ADDR, REG_I2CM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2CM0_EN}, ++ {PAD_I2C0_SDA, PADTOP1_BASE_ADDR, REG_I2CM4_MODE, BIT4|BIT3, BIT4, PINMUX_FOR_I2CM4_MODE}, ++ {PAD_I2C0_SDA, PADTOP1_BASE_ADDR, REG_USB30VCTL_MODE1, BIT4|BIT3, BIT4|BIT3, PINMUX_FOR_USB30VCTL_MODE1}, ++ {PAD_I2C2_SDA, PADTOP1_BASE_ADDR, REG_I2CM2_MODE, BIT7|BIT6|BIT5, BIT5, PINMUX_FOR_I2CM2_MODE}, ++ {PAD_I2C2_SDA, PADTOP1_BASE_ADDR, REG_SECONDUART_MODE, BIT5|BIT4|BIT3, BIT4, PINMUX_FOR_SECOND_UART_MODE}, ++ {PAD_I2C2_SCL, PADTOP1_BASE_ADDR, REG_I2CM2_MODE, BIT7|BIT6|BIT5, BIT5, PINMUX_FOR_I2CM2_MODE}, ++ {PAD_I2C2_SCL, PADTOP1_BASE_ADDR, REG_SECONDUART_MODE, BIT5|BIT4|BIT3, BIT4, PINMUX_FOR_SECOND_UART_MODE}, ++ {PAD_I2C3_SDA, PADTOP1_BASE_ADDR, REG_I2CM3_MODE, BIT10|BIT9|BIT8, BIT8, PINMUX_FOR_I2CM3_MODE}, ++ {PAD_I2C3_SCL, PADTOP1_BASE_ADDR, REG_I2CM3_MODE, BIT10|BIT9|BIT8, BIT8, PINMUX_FOR_I2CM3_MODE}, ++ {PAD_JTAG_TDO, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT2, BIT2, PINMUX_FOR_EJ_MODE}, ++ {PAD_JTAG_TDO, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_JTAG_TDI, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT2, BIT2, PINMUX_FOR_EJ_MODE}, ++ {PAD_JTAG_TDI, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_JTAG_TMS, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT2, BIT2, PINMUX_FOR_EJ_MODE}, ++ {PAD_JTAG_TMS, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_MIPI_TX_IO0, PADTOP1_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PWM0_MODE}, ++ {PAD_MIPI_TX_IO0, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_2CH_MODE, BIT4, BIT4, PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE}, ++ {PAD_MIPI_TX_IO0, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO1, PADTOP1_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_PWM1_MODE}, ++ {PAD_MIPI_TX_IO1, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_2CH_MODE, BIT4, BIT4, PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE}, ++ {PAD_MIPI_TX_IO1, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO2, PADTOP1_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_PWM2_MODE}, ++ {PAD_MIPI_TX_IO2, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_2CH_MODE, BIT4, BIT4, PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE}, ++ {PAD_MIPI_TX_IO2, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO3, PADTOP1_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_PWM3_MODE}, ++ {PAD_MIPI_TX_IO3, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_2CH_MODE, BIT4, BIT4, PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE}, ++ {PAD_MIPI_TX_IO3, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO4, PADTOP1_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_PWM4_MODE}, ++ {PAD_MIPI_TX_IO4, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_2CH_MODE, BIT4, BIT4, PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE}, ++ {PAD_MIPI_TX_IO4, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO5, PADTOP1_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10, BIT11, PINMUX_FOR_PWM5_MODE}, ++ {PAD_MIPI_TX_IO5, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_2CH_MODE, BIT4, BIT4, PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE}, ++ {PAD_MIPI_TX_IO5, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO6, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT7, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_MIPI_TX_IO6, PADTOP1_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_PWM6_MODE}, ++ {PAD_MIPI_TX_IO6, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO7, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT7, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_MIPI_TX_IO7, PADTOP1_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT15, PINMUX_FOR_PWM7_MODE}, ++ {PAD_MIPI_TX_IO7, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO8, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT7, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_MIPI_TX_IO8, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MIPI_TX_IO9, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT7, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_MIPI_TX_IO9, PADTOP1_BASE_ADDR, REG_MIPI_LVDS_TX_4CH_MODE, BIT5, BIT5, PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE}, ++ {PAD_MISC_I2S_TX_BCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_2_MODE, BIT10, BIT10, PINMUX_FOR_MISC_I2S_TX_2_MODE}, ++ {PAD_MISC_I2S_TX_WCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_2_MODE, BIT10, BIT10, PINMUX_FOR_MISC_I2S_TX_2_MODE}, ++ {PAD_MISC_I2S_TX_SDO, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_0_MODE, BIT8, BIT8, PINMUX_FOR_MISC_I2S_TX_0_MODE}, ++ {PAD_MISC_I2S_TX_SDO, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_1_MODE, BIT9, BIT9, PINMUX_FOR_MISC_I2S_TX_1_MODE}, ++ {PAD_MISC_I2S_TX_SDO, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_2_MODE, BIT10, BIT10, PINMUX_FOR_MISC_I2S_TX_2_MODE}, ++ {PAD_MISC_I2S_RX_MCK, PADTOP1_BASE_ADDR, REG_SPDIF_IN_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPDIF_IN_MODE}, ++ {PAD_MISC_I2S_RX_MCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_RX_MCK_MODE, BIT7, BIT7, PINMUX_FOR_MISC_I2S_RX_MCK_MODE}, ++ {PAD_MISC_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_RX_0_MODE, BIT6, BIT6, PINMUX_FOR_MISC_I2S_RX_0_MODE}, ++ {PAD_MISC_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_0_MODE, BIT8, BIT8, PINMUX_FOR_MISC_I2S_TX_0_MODE}, ++ {PAD_MISC_I2S_RX_BCK, PADTOP1_BASE_ADDR, REG_DMIC_0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_BT_DMIC_0_MODE}, ++ {PAD_MISC_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_RX_0_MODE, BIT6, BIT6, PINMUX_FOR_MISC_I2S_RX_0_MODE}, ++ {PAD_MISC_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_MISC_I2S_TX_0_MODE, BIT8, BIT8, PINMUX_FOR_MISC_I2S_TX_0_MODE}, ++ {PAD_MISC_I2S_RX_WCK, PADTOP1_BASE_ADDR, REG_DMIC_0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_BT_DMIC_0_MODE}, ++ {PAD_MISC_I2S_RX_SDI0, PADTOP1_BASE_ADDR, REG_MISC_I2S_RX_0_MODE, BIT6, BIT6, PINMUX_FOR_MISC_I2S_RX_0_MODE}, ++ {PAD_MISC_I2S_RX_SDI0, PADTOP1_BASE_ADDR, REG_DMIC_1_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_BT_DMIC_1_MODE}, ++ {PAD_NAND_CEZ0, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_CEZ1, PADTOP1_BASE_ADDR, REG_NAND_CS1_EN, BIT11, BIT11, PINMUX_FOR_NAND_CS1_EN}, ++ {PAD_NAND_ALE, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_SD_CONFIG, BIT6, BIT6, PINMUX_FOR_SD_CONFIG}, ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_SD_CONFIG, BIT6, BIT6, PINMUX_FOR_SD_CONFIG}, ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_EMMC_RSTN_EN, BIT6|BIT5, BIT5, PINMUX_FOR_EMMC_RSTN_EN}, ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_REZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_RBZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA0, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA0, PADTOP1_BASE_ADDR, REG_SD_CONFIG, BIT6, BIT6, PINMUX_FOR_SD_CONFIG}, ++ {PAD_NAND_DA0, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA1, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA1, PADTOP1_BASE_ADDR, REG_SD_CONFIG, BIT6, BIT6, PINMUX_FOR_SD_CONFIG}, ++ {PAD_NAND_DA1, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA2, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA2, PADTOP1_BASE_ADDR, REG_SD_CONFIG, BIT6, BIT6, PINMUX_FOR_SD_CONFIG}, ++ {PAD_NAND_DA2, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA3, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA3, PADTOP1_BASE_ADDR, REG_SD_CONFIG, BIT6, BIT6, PINMUX_FOR_SD_CONFIG}, ++ {PAD_NAND_DA3, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_FAST_UART_RTX_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FAST_UART_RT_MODE}, ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_FAST_UART_RTX_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FAST_UART_RT_MODE}, ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_I2CM2_MODE, BIT7|BIT6|BIT5, BIT7, PINMUX_FOR_I2CM2_MODE}, ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_FUART_MODE}, ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_I2CM2_MODE, BIT7|BIT6|BIT5, BIT7, PINMUX_FOR_I2CM2_MODE}, ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_FUART_MODE}, ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT3, PINMUX_FOR_EMMC_CONFIG}, ++ ++ {PAD_RGMII_0_MDIO, PADTOP1_BASE_ADDR, REG_GT0_MDIO, BIT6, BIT6, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TX_CTL, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TX_CTL, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_MDC, PADTOP1_BASE_ADDR, REG_GT0_MDIO, BIT6, BIT6, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TXD3, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RX_CLK, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RX_CLK, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TXD2, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RXD3, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TXD1, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TXD1, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RXD2, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TXD0, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TXD0, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RXD1, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RXD1, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_TX_CLK, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RXD0, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RXD0, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RX_CTL, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_0_RX_CTL, PADTOP1_BASE_ADDR, REG_GT0_MODE, BIT8|BIT7, BIT8, PINMUX_FOR_GT0_MODE}, ++ {PAD_RGMII_1_TX_CTL, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TX_CTL, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RX_CLK, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RX_CLK, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TXD3, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RXD3, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TXD2, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RXD2, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TXD1, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TXD1, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RXD1, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RXD1, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TXD0, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TXD0, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RXD0, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RXD0, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_TX_CLK, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RX_CTL, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT9, PINMUX_FOR_GT1_MODE}, ++ {PAD_RGMII_1_RX_CTL, PADTOP1_BASE_ADDR, REG_GT1_MODE, BIT10|BIT9, BIT10, PINMUX_FOR_GT1_MODE}, ++ ++ {PAD_PWM0, PADTOP1_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, ++ {PAD_PWM1, PADTOP1_BASE_ADDR, REG_PWM1_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM1_MODE}, ++ {PAD_SD_CLK, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_CMD, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D0, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D1, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D2, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D3, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8|BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SD30_IO0, PADTOP1_BASE_ADDR, REG_SDIO30_MODE, BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD30_IO0, PADTOP1_BASE_ADDR, REG_DMIC_0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_DMIC_MODE}, ++ {PAD_SD30_IO1, PADTOP1_BASE_ADDR, REG_SDIO30_MODE, BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD30_IO1, PADTOP1_BASE_ADDR, REG_DMIC_0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_DMIC_MODE}, ++ {PAD_SD30_IO2, PADTOP1_BASE_ADDR, REG_SDIO30_MODE, BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD30_IO2, PADTOP1_BASE_ADDR, REG_DMIC_1_MODE, BIT3|BIT2, BIT3|BIT2, PINMUX_FOR_DMIC_MODE}, ++ {PAD_SD30_IO3, PADTOP1_BASE_ADDR, REG_SDIO30_MODE, BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD30_IO3, PADTOP1_BASE_ADDR, REG_DMIC_2_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_DMIC_MODE}, ++ {PAD_SD30_IO4, PADTOP1_BASE_ADDR, REG_SDIO30_MODE, BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD30_IO4, PADTOP1_BASE_ADDR, REG_DMIC_2_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_DMIC_MODE}, ++ {PAD_SD30_IO5, PADTOP1_BASE_ADDR, REG_SDIO30_MODE, BIT7, BIT7, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR0_D0, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D0, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D0, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D0, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ {PAD_SNR0_D1, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D1, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D1, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D1, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ {PAD_SNR0_D2, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D2, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D2, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D2, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ {PAD_SNR0_D3, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D3, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D3, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D4, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D4, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D4, PADTOP1_BASE_ADDR, REG_CCIR0_CLK_MODE, BIT7|BIT6|BIT5, BIT5, PINMUX_FOR_CCIR0_CLK_MODE}, ++ {PAD_SNR0_D5, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D5, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D6, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D6, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D6, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D6, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ ++ {PAD_SNR0_D7, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_D7, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_D7, PADTOP1_BASE_ADDR, REG_SNR0_IN_MODE, BIT11, BIT11, PINMUX_FOR_SNR0_MODE}, ++ {PAD_SNR0_D7, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D7, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ {PAD_SNR0_D8, PADTOP1_BASE_ADDR, REG_SNR0_IN_MODE, BIT11, BIT11, PINMUX_FOR_SNR0_MODE}, ++ {PAD_SNR0_D8, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D8, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ {PAD_SNR0_D9, PADTOP1_BASE_ADDR, REG_SNR0_IN_MODE, BIT11, BIT11, PINMUX_FOR_SNR0_MODE}, ++ {PAD_SNR0_D9, PADTOP1_BASE_ADDR, REG_CCIR0_8B_MODE, BIT4, BIT4, PINMUX_FOR_CCIR0_8B_MODE}, ++ {PAD_SNR0_D9, PADTOP1_BASE_ADDR, REG_CCIR0_16B_MODE, BIT3, BIT3, PINMUX_FOR_CCIR0_16B_MODE}, ++ {PAD_SNR0_GPIO0, PADTOP1_BASE_ADDR, REG_SNR0_IN_MODE, BIT11, BIT11, PINMUX_FOR_SNR0_MODE}, ++ {PAD_SNR0_GPIO1, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_GPIO1, PADTOP1_BASE_ADDR, REG_SNR0_IN_MODE, BIT11, BIT11, PINMUX_FOR_SNR0_MODE}, ++ {PAD_SNR0_GPIO2, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_GPIO2, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_MODE}, ++ {PAD_SNR0_GPIO2, PADTOP1_BASE_ADDR, REG_SNR0_IN_MODE, BIT11, BIT11, PINMUX_FOR_SNR0_MODE}, ++ {PAD_SNR0_GPIO2, PADTOP1_BASE_ADDR, REG_CCIR0_CLK_MODE, BIT7|BIT6|BIT5, BIT6, PINMUX_FOR_CCIR0_CLK_MODE}, ++ {PAD_SNR0_GPIO3, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_GPIO3, PADTOP1_BASE_ADDR, REG_CCIR0_CTRL_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_CCIR0_CTRL_MODE}, ++ {PAD_SNR0_GPIO4, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_GPIO4, PADTOP1_BASE_ADDR, REG_EMMC_RSTN_EN, BIT14|BIT13, BIT14, PINMUX_FOR_EMMC_RSTN_EN}, ++ {PAD_SNR0_GPIO4, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_SNR0_GPIO4, PADTOP1_BASE_ADDR, REG_CCIR0_CTRL_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_CCIR0_CTRL_MODE}, ++ {PAD_SNR0_GPIO5, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_GPIO5, PADTOP1_BASE_ADDR, REG_EMMC_CONFIG, BIT4|BIT3, BIT4, PINMUX_FOR_EMMC_CONFIG}, ++ {PAD_SNR0_GPIO5, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_NAND_MODE}, ++ {PAD_SNR0_GPIO6, PADTOP1_BASE_ADDR, REG_I2CM1_MODE, BIT4|BIT3|BIT2, BIT2, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR0_GPIO6, PADTOP1_BASE_ADDR, REG_I2CM1_MODE, BIT4|BIT3|BIT2, BIT3|BIT2, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR0_GPIO6, PADTOP1_BASE_ADDR, REG_I2CM1_MODE, BIT4|BIT3|BIT2, BIT4, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR0_GPIO7, PADTOP1_BASE_ADDR, REG_I2CM1_MODE, BIT4|BIT3|BIT2, BIT2, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR0_GPIO7, PADTOP1_BASE_ADDR, REG_I2CM1_MODE, BIT4|BIT3|BIT2, BIT3|BIT2, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR0_GPIO7, PADTOP1_BASE_ADDR, REG_I2CM1_MODE, BIT4|BIT3|BIT2, BIT4, PINMUX_FOR_I2C1_MODE}, ++ ++ {PAD_SPI0_CZ0, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_SPI0_CZ0, PADTOP1_BASE_ADDR, REG_I2CM4_MODE, BIT12|BIT11, BIT11, PINMUX_FOR_I2CM4_MODE}, ++ {PAD_SPI0_CZ0, PADTOP1_BASE_ADDR, REG_THIRDUART_MODE, BIT8|BIT7|BIT6, BIT7, PINMUX_FOR_THIRD_UART_MODE}, ++ {PAD_SPI0_CZ0, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT0, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_THIRDUART_MODE, BIT8|BIT7|BIT6, BIT7, PINMUX_FOR_THIRD_UART_MODE}, ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT0, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT1, BIT0, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_I2CM4_MODE, BIT12|BIT11, BIT11, PINMUX_FOR_I2CM4_MODE}, ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_FORTHUART_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_FORTH_UART_MODE}, ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT0, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT1, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_EJ_CEVA_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_EJ_CEVA_MODE}, ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_FORTHUART_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_FORTH_UART_MODE}, ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT0, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_MSPI1_MODE1, BIT1|BIT0, BIT1, PINMUX_FOR_MSPI1_MODE1}, ++ {PAD_SPI1_CK, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT6, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_SPI1_CZ0, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT6, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_SPI1_DO, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT6, PINMUX_FOR_MSPI2_MODE1}, ++ {PAD_SPI1_DI, PADTOP1_BASE_ADDR, REG_MSPI2_MODE1, BIT7|BIT6, BIT6, PINMUX_FOR_MSPI2_MODE1}, ++ ++ {PAD_SNR1_GPIO0, PADTOP1_BASE_ADDR, REG_SNR1_IN_MODE, BIT12, BIT12, PINMUX_FOR_SNR1_IN_MODE}, ++ {PAD_SNR1_GPIO1, PADTOP1_BASE_ADDR, REG_SNR1_IN_MODE, BIT12, BIT12, PINMUX_FOR_SNR1_IN_MODE}, ++ ++ ++ {PAD_PM_SPI_CK, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT0, BIT0, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_DI, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT0, BIT0, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_DO, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT0, BIT0, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_CZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT1, BIT1, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_HOLDZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT7|BIT6, BIT7|BIT6, PINMUX_FOR_SPI1_MODE}, ++ {PAD_PM_SPI_WPZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT4, BIT4, PINMUX_FOR_PMSPI_MODE}, ++ ++}; ++ ++/*TBD*/ ++#if 0 ++ {PAD_FUART_RX, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RX, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_RX, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_RX, PADTOP1_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_UART0_MODE}, /* UART0 mode2 */ ++ {PAD_FUART_RX, PADTOP1_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode3 */ ++ ++ {PAD_FUART_TX, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_TX, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_TX, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_TX, PADTOP1_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_UART0_MODE}, /* UART0 mode2 */ ++ {PAD_FUART_TX, PADTOP1_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT3|BIT2, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode3 */ ++ ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_UART1_MODE}, /* UART1 mode2 */ ++ {PAD_FUART_CTS, PADTOP1_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode2 */ ++ ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_UART1_MODE}, /* UART1 mode2 */ ++ {PAD_FUART_RTS, PADTOP1_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode2 */ ++ ++ {PAD_I2C0_SCL, PADTOP1_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode1 */ ++ {PAD_I2C0_SCL, PADTOP1_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ ++ {PAD_I2C0_SDA, PADTOP1_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode1 */ ++ {PAD_I2C0_SDA, PADTOP1_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ ++ {PAD_I2C1_SCL, PADTOP1_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode1 */ ++ {PAD_I2C1_SCL, PADTOP1_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ ++ {PAD_I2C1_SDA, PADTOP1_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode1 */ ++ {PAD_I2C1_SDA, PADTOP1_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ ++ {PAD_SR_IO00, PADTOP1_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode3 */ ++ {PAD_SR_IO00, PADTOP1_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode3 */ ++ {PAD_SR_IO00, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO00, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO00, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO01, PADTOP1_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode3 */ ++ {PAD_SR_IO01, PADTOP1_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode3 */ ++ {PAD_SR_IO01, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO01, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO01, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO02, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO03, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO04, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO05, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO06, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO07, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO08, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO09, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO10, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO11, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO12, PADTOP1_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO13, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO13, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO13, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO13, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO13, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO13, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO14, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO14, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO14, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO14, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO14, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO14, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO15, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO15, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO15, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO15, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO15, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO15, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO16, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO16, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO16, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO16, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO16, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO17, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO17, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO17, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO17, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO17, PADTOP1_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_NAND_ALE, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_ALE, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_CLE, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_CEZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_CEZ, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_CEZ, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_CEZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_WEZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_WPZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_REZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_REZ, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_REZ, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_REZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_RBZ, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_RBZ, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_RBZ, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_RBZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA0, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA0, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT1, BIT1, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA0, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA1, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA1, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA2, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA2, PADTOP1_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode3 */ ++ {PAD_NAND_DA2, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA3, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA3, PADTOP1_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7|BIT6, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode3 */ ++ {PAD_NAND_DA3, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_PWM4_MODE}, /* PWM4 mode1 */ ++ {PAD_NAND_DA4, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10, BIT10, PINMUX_FOR_PWM5_MODE}, /* PWM5 mode1 */ ++ {PAD_NAND_DA5, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_PWM6_MODE}, /* PWM6 mode1 */ ++ {PAD_NAND_DA6, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT14, PINMUX_FOR_PWM7_MODE}, /* PWM7 mode1 */ ++ {PAD_NAND_DA7, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART0_RX, PADTOP1_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode1 */ ++ {PAD_UART0_RX, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART0_TX, PADTOP1_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode1 */ ++ {PAD_UART0_TX, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART1_RX, PADTOP1_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_UART1_MODE},/* UART1 mode1 */ ++ {PAD_UART1_RX, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART1_TX, PADTOP1_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_UART1_MODE},/* UART1 mode1 */ ++ {PAD_UART1_TX, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_CZ, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_CZ, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_CZ, PADTOP1_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_PWM4_MODE}, /* PWM4 mode2 */ ++ {PAD_SPI0_CZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10, BIT11, PINMUX_FOR_PWM5_MODE}, /* PWM5 mode2 */ ++ {PAD_SPI0_CK, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_PWM6_MODE}, /* PWM6 mode2 */ ++ {PAD_SPI0_DI, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT15, PINMUX_FOR_PWM7_MODE}, /* PWM7 mode2 */ ++ {PAD_SPI0_DO, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_CZ, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_CZ, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_CK, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_CK, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_DI, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_DI, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_DO, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_DO, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_PWM0, PADTOP1_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode2 */ ++ {PAD_PWM0, PADTOP1_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode2 */ ++ {PAD_PWM0, PADTOP1_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode1 */ ++ {PAD_PWM0, PADTOP1_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_PWM1, PADTOP1_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode2 */ ++ {PAD_PWM1, PADTOP1_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode2 */ ++ {PAD_PWM1, PADTOP1_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode1 */ ++ ++ {PAD_SD_CLK, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_CLK, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_CMD, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_CMD, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D0, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D0, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D0, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D1, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D1, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D1, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D2, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D2, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D2, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D3, PADTOP1_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D3, PADTOP1_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D3, PADTOP1_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_PM_SD_CDZ, PMSLEEP_BASE_ADDR, REG_SD_CDZ_MODE, BIT14, BIT14, PINMUX_FOR_SD_MODE}, ++ ++ /* PAD_PM_IRIN special case*/ ++ ++ {PAD_PM_SPI_CZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_CK, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_DI, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_DO, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_WPZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_HLD, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT7|BIT6, BIT6, PINMUX_FOR_SPI1_MODE}, ++ ++ {PAD_PM_LED0, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ ++ {PAD_PM_LED1, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ ++ {PAD_SAR_GPIO0, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT0, BIT0, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO1, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT1, BIT1, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO2, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT2, BIT2, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO3, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT3, BIT3, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_ETH_RN, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT0, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_RP, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT1, BIT1, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_TN, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_TP, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT3, BIT3, PINMUX_FOR_ETH_MODE}, ++}; ++#endif ++ ++S32 halCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) ++ return FALSE; ++ ++ return TRUE; ++} ++ ++S32 halPadGetVal(U32 padID, U32* mode) ++{ ++ U8 i = 0; ++ U8 fgModeIsFind = 0; ++ ++ if (FALSE == halCheckPin(padID)) ++ { ++ return FALSE; ++ } ++ ++ *mode = PINMUX_FOR_GPIO_MODE; ++ ++ switch(padID) ++ { ++ /* PAD_PM_GPIO4 special case */ ++ case PAD_PM_GPIO4: ++ if( INREG16((PMSLEEP_BASE_ADDR*0x200) + (REG_GPIO_PM_LOCK*0x4)) == 0xBABE ) ++ { ++ return TRUE; ++ } ++ else ++ { ++ *mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ } ++ ++ case PAD_PM_SPI_HOLDZ: ++ if(INREGMSK16( PMSLEEP_BASE_ADDR*0x200 + REG_SPI_IS_GPIO*4, BIT6|BIT7) == 0x0) ++ { ++ return TRUE; ++ } ++ else ++ { ++ *mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ } ++ ++ case PAD_PM_SPI_WPZ: ++ if(INREGMSK16( PMSLEEP_BASE_ADDR*0x200 + REG_SPI_IS_GPIO*4, BIT4) == 0x0) ++ { ++ return TRUE; ++ } ++ else ++ { ++ *mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ } ++ ++ case PAD_GPIO0: ++ case PAD_GPIO1: ++ case PAD_GPIO2: ++ case PAD_GPIO3: ++ case PAD_PM_GPIO2: ++ case PAD_PM_GPIO5: ++ case PAD_PM_GPIO6: ++ case PAD_PM_GPIO7: ++ case PAD_PM_GPIO9: ++ case PAD_PM_GPIO10: ++ case PAD_PM_GPIO11: ++ return TRUE; ++ ++ default: ++ for(i=0; i ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++#include "padmux.h" ++ ++#include "gpio_table.h" ++#include "mhal_pinmux.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++U32 gChipBaseAddr = 0xFD203C00; ++U32 gPmSleepBaseAddr = 0xFD001C00; ++U32 gSarBaseAddr = 0xFD002800; ++U32 gRIUBaseAddr = 0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++#define REG_ALL_PAD_IN 0xA1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static int _pmsleep_to_irq_table[] = { ++ INT_PMSLEEP_SD_CDZ, // [58] PAD_PM_SD_CDZ ++ INT_PMSLEEP_IRIN, // [59] PAD_PM_IRIN ++ -1, // [60] PADA_IDAC_OUT_B ++ -1, // [61] PADA_IDAC_OUT_G ++ -1, // [62] PADA_IDAC_OUT_R ++ INT_PMSLEEP_SPI_CZ, // [63] PAD_PM_SPI_CZ ++ INT_PMSLEEP_SPI_CK, // [64] PAD_PM_SPI_CK ++ INT_PMSLEEP_SPI_DI, // [65] PAD_PM_SPI_DI ++ INT_PMSLEEP_SPI_DO, // [66] PAD_PM_SPI_DO ++ INT_PMSLEEP_SPI_WPZ, // [67] PAD_PM_SPI_WPZ ++ INT_PMSLEEP_SPI_HLD, // [68] PAD_PM_SPI_HLD ++ INT_PMSLEEP_LED0, // [69] PAD_PM_LED0 ++ INT_PMSLEEP_LED1, // [70] PAD_PM_LED1 ++}; ++ ++static int _gpi_to_irq_table[] = { ++ INT_GPI_FIQ_GPIO0, ++ INT_GPI_FIQ_GPIO1, ++ INT_GPI_FIQ_GPIO2, ++ INT_GPI_FIQ_GPIO3, ++ INT_GPI_FIQ_GPIO4, ++ INT_GPI_FIQ_GPIO5, ++ INT_GPI_FIQ_GPIO6, ++ INT_GPI_FIQ_GPIO7, ++ INT_GPI_FIQ_GPIO8, ++ INT_GPI_FIQ_GPIO9, ++ INT_GPI_FIQ_GPIO10, ++ INT_GPI_FIQ_GPIO11, ++ INT_GPI_FIQ_GPIO12, ++ INT_GPI_FIQ_GPIO13, ++ INT_GPI_FIQ_GPIO14, ++ INT_GPI_FIQ_FUART_RX, ++ INT_GPI_FIQ_FUART_TX, ++ INT_GPI_FIQ_FUART_CTS, ++ INT_GPI_FIQ_FUART_RTS, ++ INT_GPI_FIQ_TTL0, ++ INT_GPI_FIQ_TTL1, ++ INT_GPI_FIQ_TTL2, ++ INT_GPI_FIQ_TTL3, ++ INT_GPI_FIQ_TTL4, ++ INT_GPI_FIQ_TTL5, ++ INT_GPI_FIQ_TTL6, ++ INT_GPI_FIQ_TTL7, ++ INT_GPI_FIQ_TTL8, ++ INT_GPI_FIQ_TTL9, ++ INT_GPI_FIQ_TTL10, ++ INT_GPI_FIQ_TTL11, ++ INT_GPI_FIQ_TTL12, ++ INT_GPI_FIQ_TTL13, ++ INT_GPI_FIQ_TTL14, ++ INT_GPI_FIQ_TTL15, ++ INT_GPI_FIQ_TTL16, ++ INT_GPI_FIQ_TTL17, ++ INT_GPI_FIQ_TTL18, ++ INT_GPI_FIQ_TTL19, ++ INT_GPI_FIQ_TTL20, ++ INT_GPI_FIQ_TTL21, ++ INT_GPI_FIQ_TTL22, ++ INT_GPI_FIQ_TTL23, ++ INT_GPI_FIQ_TTL24, ++ INT_GPI_FIQ_TTL25, ++ INT_GPI_FIQ_TTL26, ++ INT_GPI_FIQ_TTL27, ++ INT_GPI_FIQ_UART0_RX, ++ INT_GPI_FIQ_UART0_TX, ++ INT_GPI_FIQ_UART1_RX, ++ INT_GPI_FIQ_UART1_TX, ++ INT_GPI_FIQ_SD_CLK, ++ INT_GPI_FIQ_SD_CMD, ++ INT_GPI_FIQ_SD_D0, ++ INT_GPI_FIQ_SD_D1, ++ INT_GPI_FIQ_SD_D2, ++ INT_GPI_FIQ_SD_D3, ++ INT_GPI_FIQ_SD_GPIO, ++ -1, // [58] PAD_PM_SD_CDZ ++ -1, // [59] PAD_PM_IRIN ++ -1, // [60] PADA_IDAC_OUT_B ++ -1, // [61] PADA_IDAC_OUT_G ++ -1, // [62] PADA_IDAC_OUT_R ++ -1, // [63] PAD_PM_SPI_CZ ++ -1, // [64] PAD_PM_SPI_CK ++ -1, // [65] PAD_PM_SPI_DI ++ -1, // [66] PAD_PM_SPI_DO ++ -1, // [67] PAD_PM_SPI_WPZ ++ -1, // [68] PAD_PM_SPI_HLD ++ -1, // [69] PAD_PM_LED0 ++ -1, // [70] PAD_PM_LED1 ++ -1, // [71] PAD_SAR_GPIO0 ++ -1, // [72] PAD_SAR_GPIO1 ++ -1, // [73] PAD_SAR_GPIO2 ++ -1, // [74] PAD_SAR_GPIO3 ++ -1, // [75] PAD_ETH_RN ++ -1, // [76] PAD_ETH_RP ++ -1, // [77] PAD_ETH_TN ++ -1, // [78] PAD_ETH_TP ++ -1, // [79] PAD_DM_P1 ++ -1, // [80] PAD_DP_P1 ++ -1, // [81] PAD_DM_P2 ++ -1, // [82] PAD_DP_P2 ++ -1, // [83] PAD_DM_P3 ++ -1, // [84] PAD_DP_P3 ++ INT_GPI_FIQ_HSYNC_OUT, ++ INT_GPI_FIQ_VSYNC_OUT, ++ INT_GPI_FIQ_HDMITX_SCL, ++ INT_GPI_FIQ_HDMITX_SDA, ++ INT_GPI_FIQ_HDMITX_HPD, ++ INT_GPI_FIQ_SATA_GPIO ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GPIO_Init(void) ++{ ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ HalPadSetVal(u8IndexGPIO, PINMUX_FOR_GPIO_MODE); ++} ++ ++int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ return HalPadSetMode(u32PadMode); ++} ++ ++int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode) ++{ ++ return HalPadSetVal((U32)u8IndexGPIO, u32PadMode); ++} ++ ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ // TBD ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse) ++{ ++ // TBD ++} ++ ++static int PMSLEEP_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if ((u8IndexGPIO < PAD_PM_SD_CDZ) || (u8IndexGPIO > PAD_PM_LED1)) ++ return -1; ++ else ++ return _pmsleep_to_irq_table[u8IndexGPIO-PAD_PM_SD_CDZ]; ++} ++ ++static int GPI_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if (u8IndexGPIO >= GPIO_NR) ++ return -1; ++ else ++ return _gpi_to_irq_table[u8IndexGPIO]; ++} ++ ++//MHal_GPIO_To_Irq return any virq ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ struct device_node *intr_node; ++ struct irq_domain *intr_domain; ++ struct irq_fwspec fwspec; ++ int hwirq, virq = -1; ++ ++ ++ hwirq = PMSLEEP_GPIO_To_Irq(u8IndexGPIO); ++ if( hwirq >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,pm-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ ++ hwirq = GPI_GPIO_To_Irq(u8IndexGPIO); ++ if( hwirq >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,gpi-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ ++ return virq; ++} +diff --git a/drivers/sstar/gpio/infinity2m/mhal_gpio.h b/drivers/sstar/gpio/infinity2m/mhal_gpio.h +new file mode 100644 +index 000000000000..0ee3455c9839 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2m/mhal_gpio.h +@@ -0,0 +1,46 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_GPIO_H_ ++#define _MHAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode); ++extern int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _MHAL_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity2m/mhal_pinmux.c b/drivers/sstar/gpio/infinity2m/mhal_pinmux.c +new file mode 100644 +index 000000000000..a06df9fdf729 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2m/mhal_pinmux.c +@@ -0,0 +1,354 @@ ++/* ++* mhal_pinmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "mhal_gpio.h" ++#include "padmux.h" ++#include "gpio.h" ++ ++#include "padmux_tables.h" ++#include "pmsleep_reg.h" ++ ++//============================================================================== ++// ++// MACRO DEFINE ++// ++//============================================================================== ++ ++#define BASE_RIU_PA 0xFD000000 ++#define SAR_BANK 0x001400 ++#define ALBANY1_BANK 0x003200 ++#define ALBANY2_BANK 0x003300 ++#define UTMI0_BANK 0x142100 ++#define UTMI1_BANK 0x142500 ++#define UTMI2_BANK 0x142900 ++#define DAC_ATOP_BANK 0x112700 ++ ++#define _GPIO_W_WORD(addr,val) {(*(volatile u16*)(addr)) = (u16)(val);} ++#define _GPIO_W_WORD_MASK(addr,val,mask) {(*(volatile u16*)(addr)) = ((*(volatile u16*)(addr)) & ~(mask)) | ((u16)(val) & (mask));} ++#define _GPIO_R_BYTE(addr) (*(volatile u8*)(addr)) ++#define _GPIO_R_WORD_MASK(addr,mask) ((*(volatile u16*)(addr)) & (mask)) ++ ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define _RIUA_8BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + (((offset) & ~1)<<1) + ((offset) & 1) ++#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) ++ ++/* DAC_ATOP */ ++#define REG_GPIO_EN_PAD_OUT 0x10 ++ #define REG_GPIO_EN_PAD_OUT_B_MASK BIT0 ++ #define REG_GPIO_EN_PAD_OUT_G_MASK BIT1 ++ #define REG_GPIO_EN_PAD_OUT_R_MASK BIT2 ++ ++/* SAR : SAR_BANK, R/W 8-bits */ ++#define REG_SAR_AISEL_8BIT 0x11*2 ++ #define REG_SAR_CH0_AISEL BIT0 ++ #define REG_SAR_CH1_AISEL BIT1 ++ #define REG_SAR_CH2_AISEL BIT2 ++ #define REG_SAR_CH3_AISEL BIT3 ++ ++/* EMAC : ALBANY1_BANK */ ++#define REG_ATOP_RX_INOFF 0x69 ++ #define REG_ATOP_RX_INOFF_MASK BIT15|BIT14 ++ ++/* EMAC : ALBANY2_BANK */ ++#define REG_ETH_GPIO_EN 0x71 ++ #define REG_ETH_GPIO_EN_MASK BIT3|BIT2|BIT1|BIT0 ++ ++/* UTMI0/1/2 : UTMI_BANK */ ++#define REG_UTMI_FL_XVR_PDN 0x0 ++ #define REG_UTMI_FL_XVR_PDN_MASK BIT12 ++#define REG_UTMI_REG_PDN 0x0 ++ #define REG_UTMI_REG_PDN_MASK BIT15 // 1: power doen 0: enable ++#define REG_UTMI_CLK_EXTRA0_EN 0x4 ++ #define REG_UTMI_CLK_EXTRA0_EN_MASK BIT7 // 1: power down 0: enable ++#define REG_UTMI_GPIO_EN 0x1f ++ #define REG_UTMI_GPIO_EN_MASK BIT14 ++ ++//-------------------- configuration ----------------- ++#define ENABLE_CHECK_ALL_PAD_CONFLICT 0 ++ ++//============================================================================== ++// ++// FUNCTIONS ++// ++//============================================================================== ++ ++//------------------------------------------------------------------------------ ++// Function : _HalCheckPin ++// Description : ++//------------------------------------------------------------------------------ ++static S32 _HalCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++static void _HalSARGPIOWriteRegBit(u32 u32RegOffset, bool bEnable, U8 u8BitMsk) ++{ ++ if (bEnable) ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) |= u8BitMsk; ++ else ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) &= (~u8BitMsk); ++} ++ ++static void _HalPadDisablePadMux(U32 u32PadModeID) ++{ ++ if (_GPIO_R_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask)) { ++ _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, 0, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask); ++ } ++} ++ ++ ++ ++static S32 HalPadSetMode_General(U32 u32PadID, U32 u32Mode) ++{ ++ U32 u32RegAddr = 0; ++ U16 u16RegVal = 0; ++ U8 u8ModeIsFind = 0; ++ U16 i = 0; ++ ++ for (i = 0; i < g_u32Padmux_cnt; i++) ++ { ++ if (u32PadID == m_stPadMuxTbl[i].padID) ++ { ++ u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[i].base, m_stPadMuxTbl[i].offset); ++ ++ if (u32Mode == m_stPadMuxTbl[i].mode) ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stPadMuxTbl[i].mask); ++ u16RegVal |= m_stPadMuxTbl[i].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ ++ u8ModeIsFind = 1; ++#if (ENABLE_CHECK_ALL_PAD_CONFLICT == 0) ++ break; ++#endif ++ } ++ else ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask); ++ ++ if (u16RegVal == m_stPadMuxTbl[i].val) ++ { ++ printk(KERN_INFO"[Padmux]reset Pad_%d(reg 0x%x; mask0x%x) to %s(org: %s)\n", ++ u32PadID, m_stPadMuxTbl[i].base+m_stPadMuxTbl[i].offset, m_stPadMuxTbl[i].mask, ++ m_stPadModeInfoTbl[u32Mode].u8PadName, ++ m_stPadModeInfoTbl[m_stPadMuxTbl[i].mode].u8PadName ++ ); ++ if (m_stPadMuxTbl[i].val != 0) ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stPadMuxTbl[i].mask); ++ } ++ else ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask, m_stPadMuxTbl[i].mask); ++ } ++ } ++ } ++ } ++ } ++ ++ return (u8ModeIsFind) ? 0 : -1; ++} ++ ++static S32 HalPadSetMode_MISC(U32 u32PadID, U32 u32Mode) ++{ ++ U32 utmi_bank; ++ U16 u16BitMask; ++ U8 u8BitMask; ++ ++ switch(u32PadID) ++ { ++ /* DAC_ATOP */ ++ case PADA_IDAC_OUT_B: /* reg_gpio_en_pad_out_b; reg[112720]#0=1b */ ++ case PADA_IDAC_OUT_G: /* reg_gpio_en_pad_out_b; reg[112720]#1=1b */ ++ case PADA_IDAC_OUT_R: /* reg_gpio_en_pad_out_b; reg[112720]#2=1b */ ++ if (u32PadID == PADA_IDAC_OUT_B) ++ u16BitMask = REG_GPIO_EN_PAD_OUT_B_MASK; ++ else if (u32PadID == PADA_IDAC_OUT_G) ++ u16BitMask = REG_GPIO_EN_PAD_OUT_G_MASK; ++ else if (u32PadID == PADA_IDAC_OUT_R) ++ u16BitMask = REG_GPIO_EN_PAD_OUT_R_MASK; ++ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(DAC_ATOP_BANK,REG_GPIO_EN_PAD_OUT), u16BitMask, u16BitMask); ++ } ++ else if (u32Mode == PINMUX_FOR_DAC_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(DAC_ATOP_BANK,REG_GPIO_EN_PAD_OUT), 0, u16BitMask); ++ } ++ else { ++ return -1; ++ } ++ break; ++ ++ /* SAR */ ++ case PAD_SAR_GPIO0: /* reg_sar_aisel; reg[1422]#5 ~ #0=0b */ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_MODE), 0, REG_PM_SPICSZ2_MODE_MASK); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH0_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_MODE), 0, REG_PM_SPICSZ2_MODE_MASK); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH0_AISEL, REG_SAR_CH0_AISEL); ++ } ++ else { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO1: ++ case PAD_SAR_GPIO2: ++ case PAD_SAR_GPIO3: ++ if (u32PadID == PAD_SAR_GPIO1) ++ u8BitMask = REG_SAR_CH1_AISEL; ++ else if (u32PadID == PAD_SAR_GPIO2) ++ u8BitMask = REG_SAR_CH2_AISEL; ++ else if (u32PadID == PAD_SAR_GPIO3) ++ u8BitMask = REG_SAR_CH3_AISEL; ++ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, u8BitMask); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, u8BitMask, u8BitMask); ++ } ++ else { ++ return -1; ++ } ++ break; ++ ++ /* lan-top */ ++ case PAD_ETH_RN: ++ case PAD_ETH_RP: ++ case PAD_ETH_TN: ++ case PAD_ETH_TP: ++ if (u32PadID == PAD_ETH_RN) ++ u16BitMask = BIT0; ++ else if (u32PadID == PAD_ETH_RP) ++ u16BitMask = BIT1; ++ else if (u32PadID == PAD_ETH_TN) ++ u16BitMask = BIT2; ++ else if (u32PadID == PAD_ETH_TP) ++ u16BitMask = BIT3; ++ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), u16BitMask, u16BitMask); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, u16BitMask); ++ } ++ else { ++ return -1; ++ } ++ break; ++ ++ /* UTMI */ ++ case PAD_DM_P1: ++ case PAD_DP_P1: ++ case PAD_DM_P2: ++ case PAD_DP_P2: ++ case PAD_DM_P3: ++ case PAD_DP_P3: ++ if ((u32PadID == PAD_DM_P1) || (u32PadID == PAD_DP_P1)) ++ utmi_bank = UTMI0_BANK; ++ else if ((u32PadID == PAD_DM_P2) || (u32PadID == PAD_DP_P2)) ++ utmi_bank = UTMI1_BANK; ++ if ((u32PadID == PAD_DM_P3) || (u32PadID == PAD_DP_P3)) ++ utmi_bank = UTMI2_BANK; ++ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE); ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_GPIO_EN), REG_UTMI_GPIO_EN_MASK, REG_UTMI_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_CLK_EXTRA0_EN), REG_UTMI_CLK_EXTRA0_EN_MASK, REG_UTMI_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_REG_PDN), REG_UTMI_REG_PDN_MASK, REG_UTMI_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_FL_XVR_PDN), REG_UTMI_FL_XVR_PDN_MASK, REG_UTMI_FL_XVR_PDN_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_USB_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_GPIO_EN), ~REG_UTMI_GPIO_EN_MASK, REG_UTMI_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_CLK_EXTRA0_EN), ~REG_UTMI_CLK_EXTRA0_EN_MASK, REG_UTMI_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_REG_PDN), ~REG_UTMI_REG_PDN_MASK, REG_UTMI_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(utmi_bank,REG_UTMI_FL_XVR_PDN), REG_UTMI_FL_XVR_PDN_MASK, REG_UTMI_FL_XVR_PDN_MASK); ++ } ++ else { ++ return -1; ++ } ++ break; ++ ++ default: ++ return -1; ++ } ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalPadSetVal ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetVal(U32 u32PadID, U32 u32Mode) ++{ ++ if (FALSE == _HalCheckPin(u32PadID)) { ++ return FALSE; ++ } ++ ++ if ((u32PadID >= PADA_IDAC_OUT_B && u32PadID <= PADA_IDAC_OUT_R) || ++ (u32PadID >= PAD_SAR_GPIO0 && u32PadID <= PAD_DP_P3)) { ++ return HalPadSetMode_MISC(u32PadID, u32Mode); ++ } ++ else { ++ return HalPadSetMode_General(u32PadID, u32Mode); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalPadSet ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetMode(U32 u32Mode) ++{ ++ U32 u32PadID; ++ U16 k = 0; ++ ++ for (k = 0; k < g_u32Padmux_cnt; k++) ++ { ++ if (u32Mode == m_stPadMuxTbl[k].mode) ++ { ++ u32PadID = m_stPadMuxTbl[k].padID; ++ if (HalPadSetMode_General( u32PadID, u32Mode) < 0) ++ return -1; ++ } ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/gpio/infinity2m/mhal_pinmux.h b/drivers/sstar/gpio/infinity2m/mhal_pinmux.h +new file mode 100644 +index 000000000000..32594933c756 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2m/mhal_pinmux.h +@@ -0,0 +1,9 @@ ++#ifndef __MHAL_PINMUX_H__ ++#define __MHAL_PINMUX_H__ ++ ++#include "mdrv_types.h" ++ ++extern S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++extern S32 HalPadSetMode(U32 u32Mode); ++ ++#endif // __MHAL_PINMUX_H__ +diff --git a/drivers/sstar/gpio/infinity2m/padmux_tables.c b/drivers/sstar/gpio/infinity2m/padmux_tables.c +new file mode 100644 +index 000000000000..f2d1df1bfb56 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2m/padmux_tables.c +@@ -0,0 +1,957 @@ ++#include "gpio.h" ++#include "padmux.h" ++#include "padmux_tables.h" ++#include "chiptop_reg.h" ++#include "pmsleep_reg.h" ++ ++//============================================================================== ++// ++// padmux_table ++// ++//============================================================================== ++const ST_PadMuxInfo m_stPadMuxTbl[] = ++{ ++ {PAD_GPIO0, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT1, PINMUX_FOR_SPI0_MODE_6}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PWM0_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT11, PINMUX_FOR_ETH1_MODE_8}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE_1}, ++ ++ {PAD_GPIO1, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT1, PINMUX_FOR_SPI0_MODE_6}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT3, PINMUX_FOR_PWM1_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT11, PINMUX_FOR_ETH1_MODE_8}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE_1}, ++ ++ {PAD_GPIO2, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT1, PINMUX_FOR_SPI0_MODE_6}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PWM2_MODE_1}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE_1}, ++ ++ {PAD_GPIO3, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT1, PINMUX_FOR_SPI0_MODE_6}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PWM3_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE_1}, ++ ++ {PAD_GPIO4, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_PM_SPICZ2_MODE, REG_PM_SPICZ2_MODE_MASK, BIT4, PINMUX_FOR_PM_SPICZ2_MODE_1}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE_2}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM0_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_GPIO5, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE_2}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5, PINMUX_FOR_PWM1_MODE_4}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_GPIO6, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE_2}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_GPIO7, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE_2}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10, PINMUX_FOR_PWM3_MODE_2}, ++ ++ {PAD_GPIO8, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_SPI0_MODE_5}, ++ {PAD_GPIO8, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_GPIO8, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT13, PINMUX_FOR_UART2_MODE_2}, ++ {PAD_GPIO8, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE_2}, ++ ++ {PAD_GPIO9, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_SPI0_MODE_5}, ++ {PAD_GPIO9, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_GPIO9, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT13, PINMUX_FOR_UART2_MODE_2}, ++ {PAD_GPIO9, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE_2}, ++ ++ {PAD_GPIO10, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_SPI0_MODE_5}, ++ {PAD_GPIO10, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, ++ ++ {PAD_GPIO11, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_SPI0_MODE_5}, ++ {PAD_GPIO11, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO11, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PWM2_MODE_2}, ++ ++ {PAD_GPIO12, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM3_MODE_3}, ++ ++ {PAD_GPIO13, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, ++ ++ {PAD_GPIO14, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2, PINMUX_FOR_PWM0_MODE_4}, ++ ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT12, PINMUX_FOR_UART2_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11|BIT9, PINMUX_FOR_PWM3_MODE_5}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT12, PINMUX_FOR_UART2_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8|BIT6, PINMUX_FOR_PWM2_MODE_5}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_PM_SPICZ2_MODE, REG_PM_SPICZ2_MODE_MASK, BIT5, PINMUX_FOR_PM_SPICZ2_MODE_2}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_TTL0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM0_MODE_5}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_TTL1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_ETH1_MODE_7}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_TTL2, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_ETH1_MODE_7}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ ++ {PAD_TTL6, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT13, PINMUX_FOR_TX_MIPI_MODE_2}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL6, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL7, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT13, PINMUX_FOR_TX_MIPI_MODE_2}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL7, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL8, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT13, PINMUX_FOR_TX_MIPI_MODE_2}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL8, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL9, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT13, PINMUX_FOR_TX_MIPI_MODE_2}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL9, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL10, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT13, PINMUX_FOR_TX_MIPI_MODE_2}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL10, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL11, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT13, PINMUX_FOR_TX_MIPI_MODE_2}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL11, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL12, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4, PINMUX_FOR_PWM1_MODE_2}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL12, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL13, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL13, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL14, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL14, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL15, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TX_MIPI_MODE, REG_TX_MIPI_MODE_MASK, BIT12, PINMUX_FOR_TX_MIPI_MODE_1}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL15, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL16, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL16, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL17, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ {PAD_TTL17, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL18, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL18, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL19, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9, PINMUX_FOR_TTL_MODE_10}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL19, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL20, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11, PINMUX_FOR_PWM3_MODE_4}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL20, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL21, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8, PINMUX_FOR_PWM2_MODE_4}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9, PINMUX_FOR_TTL_MODE_6}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT9|BIT8,PINMUX_FOR_TTL_MODE_11}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL21, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ ++ {PAD_TTL22, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT6, PINMUX_FOR_I2C1_MODE_4}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM1_MODE_3}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT9, PINMUX_FOR_ETH1_MODE_6}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL22, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ ++ {PAD_TTL23, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT6, PINMUX_FOR_I2C1_MODE_4}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PWM0_MODE_2}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10, PINMUX_FOR_ETH1_MODE_4}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT9, PINMUX_FOR_ETH1_MODE_6}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ ++ {PAD_TTL24, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_ETH0_MODE, REG_ETH0_MODE_MASK, BIT0, PINMUX_FOR_ETH0_MODE}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT8, PINMUX_FOR_ETH1_MODE_1}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9, PINMUX_FOR_ETH1_MODE_2}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_ETH1_MODE_3}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL24, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ ++ {PAD_TTL25, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT0, PINMUX_FOR_BT1120_MODE_1}, ++ {PAD_TTL25, CHIPTOP_BANK, REG_BT1120_MODE, REG_BT1120_MODE_MASK, BIT1, PINMUX_FOR_BT1120_MODE_2}, ++ ++ {PAD_TTL26, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL26, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ ++ {PAD_TTL27, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT10|BIT8, PINMUX_FOR_ETH1_MODE_5}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT8, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9, PINMUX_FOR_TTL_MODE_2}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT9|BIT8, PINMUX_FOR_TTL_MODE_3}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10, PINMUX_FOR_TTL_MODE_4}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT8, PINMUX_FOR_TTL_MODE_5}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT10|BIT9|BIT8,PINMUX_FOR_TTL_MODE_7}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11, PINMUX_FOR_TTL_MODE_8}, ++ {PAD_TTL27, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT8, PINMUX_FOR_TTL_MODE_9}, ++ ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT11|BIT8, PINMUX_FOR_ETH1_MODE_9}, ++ ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_ETH1_MODE, REG_ETH1_MODE_MASK, BIT11|BIT8, PINMUX_FOR_ETH1_MODE_9}, ++ ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10, PINMUX_FOR_DMIC_MODE_4}, ++ ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10, PINMUX_FOR_DMIC_MODE_4}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10, PINMUX_FOR_TTL_MODE_12}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT11|BIT10|BIT8,PINMUX_FOR_TTL_MODE_13}, ++ ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_I2C1_MODE_5}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE_1}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_I2C1_MODE_5}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE_1}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1|BIT0, PINMUX_FOR_FUART_MODE_7}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE_1}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1|BIT0, PINMUX_FOR_FUART_MODE_7}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE_1}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8|BIT7, PINMUX_FOR_PWM2_MODE_6}, ++ ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT14, PINMUX_FOR_UART2_MODE_4}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE_1}, ++ ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT14, PINMUX_FOR_UART2_MODE_4}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE_1}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_MODE_3}, ++ ++ ++ {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SD_CDZ, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT8, PINMUX_FOR_PM_PWM3_MODE}, ++ {PAD_PM_SD_CDZ, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_SD_CDZ, PMSLEEP_BANK, REG_PM_SD_CDZ_MODE, REG_PM_SD_CDZ_MODE_MASK, BIT14, PINMUX_FOR_PM_SD_CDZ_MODE}, ++ ++ {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_IRIN, PMSLEEP_BANK, REG_PM_SPICSZ2_GPIO, REG_PM_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ2_MODE}, ++ {PAD_PM_IRIN, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PM_PWM2_MODE}, ++ {PAD_PM_IRIN, PMSLEEP_BANK, REG_PM_IR_IS_GPIO, REG_PM_IR_IS_GPIO_MASK, 0, PINMUX_FOR_PM_IRIN_MODE}, ++ ++ ++ ++ ++ {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_CZ, PMSLEEP_BANK, REG_PM_SPICSZ1_GPIO, REG_PM_SPICSZ1_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ1_MODE}, ++ ++ {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_CK, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_DI, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_DO, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_WPZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_WPZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_WPZ, PMSLEEP_BANK, REG_PM_SPIWPN_GPIO, REG_PM_SPIWPN_GPIO_MASK, 0, PINMUX_FOR_PM_SPIWPN_MODE}, ++ ++ {PAD_PM_SPI_HLD, PMSLEEP_BANK, REG_PM_SPIHOLDN_MODE, REG_PM_SPIHOLDN_MODE_MASK, 0, PINMUX_FOR_PM_SPIHOLDN_MODE}, ++ ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_PWM0_MODE, REG_PM_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PM_PWM0_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE_1}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT5, PINMUX_FOR_PM_LED_MODE_2}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT5|BIT4, PINMUX_FOR_PM_LED_MODE_3}, ++ ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM1_MODE, REG_PM_PWM1_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM1_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE_1}, ++/* ++ {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SAR_GPIO0, PMSLEEP_BANK, REG_PM_SPICSZ2_MODE, REG_PM_SPICSZ2_MODE_MASK, BIT12, PINMUX_FOR_PM_SPICSZ2_MODE}, ++ ++ {PAD_SAR_GPIO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SAR_GPIO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ ++ ++ {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++*/ ++ ++ {PAD_HSYNC_OUT, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_HSYNC_OUT, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_HSYNC_OUT, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_HSYNC_OUT, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_HSYNC_OUT, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT13|BIT12, PINMUX_FOR_UART2_MODE_3}, ++ {PAD_HSYNC_OUT, CHIPTOP_BANK, REG_IDAC_MODE, REG_IDAC_MODE_MASK, BIT0, PINMUX_FOR_IDAC_MODE}, ++ ++ {PAD_VSYNC_OUT, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_VSYNC_OUT, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_VSYNC_OUT, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_VSYNC_OUT, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_VSYNC_OUT, CHIPTOP_BANK, REG_UART2_MODE, REG_UART2_MODE_MASK, BIT13|BIT12, PINMUX_FOR_UART2_MODE_3}, ++ {PAD_VSYNC_OUT, CHIPTOP_BANK, REG_IDAC_MODE, REG_IDAC_MODE_MASK, BIT0, PINMUX_FOR_IDAC_MODE}, ++ ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_HDMITX_SCL, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_HDMITX_SDA, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ ++ {PAD_HDMITX_HPD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_HDMITX_HPD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_HDMITX_HPD, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM2_MODE_3}, ++ {PAD_HDMITX_HPD, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ ++ {PAD_SATA_GPIO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SATA_GPIO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SATA_GPIO, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5|BIT3, PINMUX_FOR_PWM1_MODE_5}, ++ {PAD_SATA_GPIO, CHIPTOP_BANK, REG_SATA_LED_MODE, REG_SATA_LED_MODE_MASK, BIT0, PINMUX_FOR_SATA_LED_MODE}, ++ ++}; ++ ++U32 g_u32Padmux_cnt = sizeof(m_stPadMuxTbl)/sizeof(ST_PadMuxInfo); ++ ++ ++//============================================================================== ++// ++// padmode_info ++// ++//============================================================================== ++#define BASE_RIU_PA 0xFD000000 ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) ++ ++const ST_PadModeInfo m_stPadModeInfoTbl[] = ++{ ++ {"GPIO", 0, 0}, ++ // Non PM ++ {"EJ_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"EJ_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"EJ_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"TX_MIPI_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TX_MIPI_MODE), REG_TX_MIPI_MODE_MASK}, ++ {"TX_MIPI_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TX_MIPI_MODE), REG_TX_MIPI_MODE_MASK}, ++ {"TEST_IN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_OUT_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"I2C0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"PM_SPICZ2_MODE_1",_RIUA_16BIT(CHIPTOP_BANK,REG_PM_SPICZ2_MODE), REG_PM_SPICZ2_MODE_MASK}, ++ {"PM_SPICZ2_MODE_2",_RIUA_16BIT(CHIPTOP_BANK,REG_PM_SPICZ2_MODE), REG_PM_SPICZ2_MODE_MASK}, ++ {"SPI0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"FUART_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_7", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"UART0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART2_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART2_MODE), REG_UART2_MODE_MASK}, ++ {"UART2_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART2_MODE), REG_UART2_MODE_MASK}, ++ {"UART2_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART2_MODE), REG_UART2_MODE_MASK}, ++ {"UART2_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART2_MODE), REG_UART2_MODE_MASK}, ++ {"SDIO_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SDIO_MODE), REG_SDIO_MODE_MASK}, ++ {"SDIO_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SDIO_MODE), REG_SDIO_MODE_MASK}, ++ {"PWM0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM2_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM3_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"ETH0_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH0_MODE), REG_ETH0_MODE_MASK}, ++ {"ETH1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_7", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_8", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"ETH1_MODE_9", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH1_MODE), REG_ETH1_MODE_MASK}, ++ {"DMIC_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"I2S_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_7", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_8", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_9", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_10", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_11", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_12", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_13", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"IDAC_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_IDAC_MODE), REG_IDAC_MODE_MASK}, ++ {"SATA_LED_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SATA_LED_MODE), REG_SATA_LED_MODE_MASK}, ++ {"BT1120_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_BT1120_MODE), REG_BT1120_MODE_MASK}, ++ {"BT1120_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_BT1120_MODE), REG_BT1120_MODE_MASK}, ++ // PM Sleep ++ {"PM_SPI_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_GPIO), REG_PM_SPI_GPIO_MASK}, ++ {"PM_SPIWPN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIWPN_GPIO), REG_PM_SPIWPN_GPIO_MASK}, ++ {"PM_SPIHOLDN_MODE",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIHOLDN_MODE), REG_PM_SPIHOLDN_MODE_MASK}, ++ {"PM_SPICSZ1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ1_GPIO), REG_PM_SPICSZ1_GPIO_MASK}, ++ {"PM_SPICSZ2_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_GPIO), REG_PM_SPICSZ2_GPIO_MASK}, ++ {"PM_PWM0_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, ++ {"PM_PWM2_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, ++ {"PM_PWM3_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, ++ {"PM_UART1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), REG_PM_UART1_MODE_MASK}, ++ {"PM_VID_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_3", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_SD_CDZ_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SD_CDZ_MODE), REG_PM_SD_CDZ_MODE_MASK}, ++ {"PM_LED_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, ++ {"PM_LED_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, ++ {"PM_LED_MODE_3", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, ++ {"PM_IRIN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), REG_PM_IR_IS_GPIO_MASK}, ++}; +diff --git a/drivers/sstar/gpio/infinity2m/padmux_tables.h b/drivers/sstar/gpio/infinity2m/padmux_tables.h +new file mode 100644 +index 000000000000..5d26921b3399 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2m/padmux_tables.h +@@ -0,0 +1,32 @@ ++#ifndef __PADMUX_TABLES_H__ ++#define __PADMUX_TABLES_H__ ++ ++#include "mhal_gpio.h" ++ ++//============================================================================== ++// ++// STRUCTURE ++// ++//============================================================================== ++typedef struct stPadMux ++{ ++ U16 padID; ++ U32 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PadMuxInfo; ++ ++typedef struct stPadMode ++{ ++ U8 u8PadName[16]; ++ U32 u32ModeRIU; ++ U32 u32ModeMask; ++} ST_PadModeInfo; ++ ++extern const ST_PadModeInfo m_stPadModeInfoTbl[]; ++extern const ST_PadMuxInfo m_stPadMuxTbl[]; ++extern U32 g_u32Padmux_cnt; ++ ++#endif // __PADMUX_TABLES_H_ +diff --git a/drivers/sstar/gpio/infinity2m/pmsleep_reg.h b/drivers/sstar/gpio/infinity2m/pmsleep_reg.h +new file mode 100644 +index 000000000000..bbb477bfb546 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity2m/pmsleep_reg.h +@@ -0,0 +1,65 @@ ++#ifndef __PMSLEEP_REG_H__ ++#define __PMSLEEP_REG_H__ ++ ++#define PMSLEEP_BANK 0x000E00 ++ ++/* PM PAD : PMSLEEP_BANK */ ++#define REG_GPIO_PM_LOCK 0x12 ++ #define REG_GPIO_PM_LOCK_MASK 0xFFFF ++#define REG_PM_GPIO_PM4_INV 0x1c ++ #define REG_PM_GPIO_PM4_INV_MASK BIT1 ++#define REG_PM_LINK_WKINT2GPIO4 0x1c ++ #define REG_PM_LINK_WKINT2GPIO4_MASK BIT3 ++ ++#define REG_PM_IR_IS_GPIO 0x1c ++ #define REG_PM_IR_IS_GPIO_MASK BIT4 ++#define REG_PM_IRIN_MODE REG_PM_IR_IS_GPIO ++ ++#define REG_PM_PWM0_MODE 0x28 ++ #define REG_PM_PWM0_MODE_MASK BIT1|BIT0 ++#define REG_PM_PWM1_MODE 0x28 ++ #define REG_PM_PWM1_MODE_MASK BIT3|BIT2 ++#define REG_PM_PWM2_MODE 0x28 ++ #define REG_PM_PWM2_MODE_MASK BIT7|BIT6 ++#define REG_PM_PWM3_MODE 0x28 ++ #define REG_PM_PWM3_MODE_MASK BIT9|BIT8 ++#define REG_PM_PWM4_MODE 0x27 ++ #define REG_PM_PWM4_MODE_MASK BIT0 ++#define REG_PM_PWM5_MODE 0x27 ++ #define REG_PM_PWM5_MODE_MASK BIT1 ++#define REG_PM_PWM8_MODE 0x27 ++ #define REG_PM_PWM8_MODE_MASK BIT2 ++#define REG_PM_PWM9_MODE 0x27 ++ #define REG_PM_PWM9_MODE_MASK BIT3 ++#define REG_PM_PWM10_MODE 0x27 ++ #define REG_PM_PWM10_MODE_MASK BIT4 ++#define REG_PM_UART1_MODE 0x27 ++ #define REG_PM_UART1_MODE_MASK BIT8 ++#define REG_PM_LED_MODE 0x28 ++ #define REG_PM_LED_MODE_MASK BIT5|BIT4 ++ ++#define REG_PM_VID_MODE 0x28 ++ #define REG_PM_VID_MODE_MASK BIT13|BIT12 ++#define REG_PM_SD_CDZ_MODE 0x28 ++ #define REG_PM_SD_CDZ_MODE_MASK BIT14 ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++ #define REG_PM_SPI_IS_GPIO_MASK BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0 ++ #define REG_PM_SPI_GPIO_MASK BIT0 ++ #define REG_PM_SPICSZ1_GPIO_MASK BIT2 ++ #define REG_PM_SPICSZ2_GPIO_MASK BIT3 ++ #define REG_PM_SPIWPN_GPIO_MASK BIT4 ++ #define REG_PM_SPIHOLDN_MODE_MASK BIT6 | BIT7 ++#define REG_PM_SPICSZ1_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPICSZ2_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPI_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIWPN_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIHOLDN_MODE REG_PM_SPI_IS_GPIO ++ ++#define REG_PM_UART_IS_GPIO 0x35 ++ #define REG_PM_UART_IS_GPIO_MASK BIT11|BIT10|BIT9|BIT8 ++ ++#define REG_PM_SPICSZ2_MODE 0x36 ++ #define REG_PM_SPICSZ2_MODE_MASK BIT12 ++ ++#endif // __PMSLEEP_REG_H__ +diff --git a/drivers/sstar/gpio/infinity3/mhal_gpio.c b/drivers/sstar/gpio/infinity3/mhal_gpio.c +new file mode 100755 +index 000000000000..c73f9b2c390f +--- /dev/null ++++ b/drivers/sstar/gpio/infinity3/mhal_gpio.c +@@ -0,0 +1,1246 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if 1 ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103c00, BIT5 ++#define GPIO0_IN 0x103c00, BIT0 ++#define GPIO0_OUT 0x103c00, BIT4 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103c02, BIT5 ++#define GPIO1_IN 0x103c02, BIT0 ++#define GPIO1_OUT 0x103c02, BIT4 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103c04, BIT5 ++#define GPIO2_IN 0x103c04, BIT0 ++#define GPIO2_OUT 0x103c04, BIT4 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103c06, BIT5 ++#define GPIO3_IN 0x103c06, BIT0 ++#define GPIO3_OUT 0x103c06, BIT4 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103c08, BIT5 ++#define GPIO4_IN 0x103c08, BIT0 ++#define GPIO4_OUT 0x103c08, BIT4 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103c0a, BIT5 ++#define GPIO5_IN 0x103c0a, BIT0 ++#define GPIO5_OUT 0x103c0a, BIT4 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103c0c, BIT5 ++#define GPIO6_IN 0x103c0c, BIT0 ++#define GPIO6_OUT 0x103c0c, BIT4 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103c0e, BIT5 ++#define GPIO7_IN 0x103c0e, BIT0 ++#define GPIO7_OUT 0x103c0e, BIT4 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103c10, BIT5 ++#define GPIO8_IN 0x103c10, BIT0 ++#define GPIO8_OUT 0x103c10, BIT4 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103c12, BIT5 ++#define GPIO9_IN 0x103c12, BIT0 ++#define GPIO9_OUT 0x103c12, BIT4 ++ ++#define GPIO10_PAD PAD_GPIO10 ++#define GPIO10_OEN 0x103c14, BIT5 ++#define GPIO10_IN 0x103c14, BIT0 ++#define GPIO10_OUT 0x103c14, BIT4 ++ ++#define GPIO11_PAD PAD_GPIO11 ++#define GPIO11_OEN 0x103c16, BIT5 ++#define GPIO11_IN 0x103c16, BIT0 ++#define GPIO11_OUT 0x103c16, BIT4 ++ ++#define GPIO12_PAD PAD_GPIO12 ++#define GPIO12_OEN 0x103c18, BIT5 ++#define GPIO12_IN 0x103c18, BIT0 ++#define GPIO12_OUT 0x103c18, BIT4 ++ ++#define GPIO13_PAD PAD_GPIO13 ++#define GPIO13_OEN 0x103c1a, BIT5 ++#define GPIO13_IN 0x103c1a, BIT0 ++#define GPIO13_OUT 0x103c1a, BIT4 ++ ++#define GPIO14_PAD PAD_GPIO14 ++#define GPIO14_OEN 0x103c1c, BIT5 ++#define GPIO14_IN 0x103c1c, BIT0 ++#define GPIO14_OUT 0x103c1c, BIT4 ++ ++#define GPIO15_PAD PAD_GPIO15 ++#define GPIO15_OEN 0x103c1e, BIT5 ++#define GPIO15_IN 0x103c1e, BIT0 ++#define GPIO15_OUT 0x103c1e, BIT4 ++ ++#define GPIO16_PAD PAD_FUART_RX ++#define GPIO16_OEN 0x103c28, BIT5 ++#define GPIO16_IN 0x103c28, BIT0 ++#define GPIO16_OUT 0x103c28, BIT4 ++ ++#define GPIO17_PAD PAD_FUART_TX ++#define GPIO17_OEN 0x103c2a, BIT5 ++#define GPIO17_IN 0x103c2a, BIT0 ++#define GPIO17_OUT 0x103c2a, BIT4 ++ ++#define GPIO18_PAD PAD_FUART_CTS ++#define GPIO18_OEN 0x103c2c, BIT5 ++#define GPIO18_IN 0x103c2c, BIT0 ++#define GPIO18_OUT 0x103c2c, BIT4 ++ ++#define GPIO19_PAD PAD_FUART_RTS ++#define GPIO19_OEN 0x103c2e, BIT5 ++#define GPIO19_IN 0x103c2e, BIT0 ++#define GPIO19_OUT 0x103c2e, BIT4 ++ ++#define GPIO20_PAD PAD_I2C0_SCL ++#define GPIO20_OEN 0x103cc0, BIT5 ++#define GPIO20_IN 0x103cc0, BIT0 ++#define GPIO20_OUT 0x103cc0, BIT4 ++ ++#define GPIO21_PAD PAD_I2C0_SDA ++#define GPIO21_OEN 0x103cc2, BIT5 ++#define GPIO21_IN 0x103cc2, BIT0 ++#define GPIO21_OUT 0x103cc2, BIT4 ++ ++#define GPIO22_PAD PAD_I2C1_SCL ++#define GPIO22_OEN 0x103cc4, BIT5 ++#define GPIO22_IN 0x103cc4, BIT0 ++#define GPIO22_OUT 0x103cc4, BIT4 ++ ++#define GPIO23_PAD PAD_I2C1_SDA ++#define GPIO23_OEN 0x103cc6, BIT5 ++#define GPIO23_IN 0x103cc6, BIT0 ++#define GPIO23_OUT 0x103cc6, BIT4 ++ ++#define GPIO24_PAD PAD_SR_IO00 ++#define GPIO24_OEN 0x103c40, BIT5 ++#define GPIO24_IN 0x103c40, BIT0 ++#define GPIO24_OUT 0x103c40, BIT4 ++ ++#define GPIO25_PAD PAD_SR_IO01 ++#define GPIO25_OEN 0x103c42, BIT5 ++#define GPIO25_IN 0x103c42, BIT0 ++#define GPIO25_OUT 0x103c42, BIT4 ++ ++#define GPIO26_PAD PAD_SR_IO02 ++#define GPIO26_OEN 0x103c44, BIT5 ++#define GPIO26_IN 0x103c44, BIT0 ++#define GPIO26_OUT 0x103c44, BIT4 ++ ++#define GPIO27_PAD PAD_SR_IO03 ++#define GPIO27_OEN 0x103c46, BIT5 ++#define GPIO27_IN 0x103c46, BIT0 ++#define GPIO27_OUT 0x103c46, BIT4 ++ ++#define GPIO28_PAD PAD_SR_IO04 ++#define GPIO28_OEN 0x103c48, BIT5 ++#define GPIO28_IN 0x103c48, BIT0 ++#define GPIO28_OUT 0x103c48, BIT4 ++ ++#define GPIO29_PAD PAD_SR_IO05 ++#define GPIO29_OEN 0x103c4a, BIT5 ++#define GPIO29_IN 0x103c4a, BIT0 ++#define GPIO29_OUT 0x103c4a, BIT4 ++ ++#define GPIO30_PAD PAD_SR_IO06 ++#define GPIO30_OEN 0x103c4c, BIT5 ++#define GPIO30_IN 0x103c4c, BIT0 ++#define GPIO30_OUT 0x103c4c, BIT4 ++ ++#define GPIO31_PAD PAD_SR_IO07 ++#define GPIO31_OEN 0x103c4e, BIT5 ++#define GPIO31_IN 0x103c4e, BIT0 ++#define GPIO31_OUT 0x103c4e, BIT4 ++ ++#define GPIO32_PAD PAD_SR_IO08 ++#define GPIO32_OEN 0x103c50, BIT5 ++#define GPIO32_IN 0x103c50, BIT0 ++#define GPIO32_OUT 0x103c50, BIT4 ++ ++#define GPIO33_PAD PAD_SR_IO09 ++#define GPIO33_OEN 0x103c52, BIT5 ++#define GPIO33_IN 0x103c52, BIT0 ++#define GPIO33_OUT 0x103c52, BIT4 ++ ++#define GPIO34_PAD PAD_SR_IO10 ++#define GPIO34_OEN 0x103c54, BIT5 ++#define GPIO34_IN 0x103c54, BIT0 ++#define GPIO34_OUT 0x103c54, BIT4 ++ ++#define GPIO35_PAD PAD_SR_IO11 ++#define GPIO35_OEN 0x103c56, BIT5 ++#define GPIO35_IN 0x103c56, BIT0 ++#define GPIO35_OUT 0x103c56, BIT4 ++ ++#define GPIO36_PAD PAD_SR_IO12 ++#define GPIO36_OEN 0x103c58, BIT5 ++#define GPIO36_IN 0x103c58, BIT0 ++#define GPIO36_OUT 0x103c58, BIT4 ++ ++#define GPIO37_PAD PAD_SR_IO13 ++#define GPIO37_OEN 0x103c5a, BIT5 ++#define GPIO37_IN 0x103c5a, BIT0 ++#define GPIO37_OUT 0x103c5a, BIT4 ++ ++#define GPIO38_PAD PAD_SR_IO14 ++#define GPIO38_OEN 0x103c5c, BIT5 ++#define GPIO38_IN 0x103c5c, BIT0 ++#define GPIO38_OUT 0x103c5c, BIT4 ++ ++#define GPIO39_PAD PAD_SR_IO15 ++#define GPIO39_OEN 0x103c5e, BIT5 ++#define GPIO39_IN 0x103c5e, BIT0 ++#define GPIO39_OUT 0x103c5e, BIT4 ++ ++#define GPIO40_PAD PAD_SR_IO16 ++#define GPIO40_OEN 0x103c60, BIT5 ++#define GPIO40_IN 0x103c60, BIT0 ++#define GPIO40_OUT 0x103c60, BIT4 ++ ++#define GPIO41_PAD PAD_SR_IO17 ++#define GPIO41_OEN 0x103c62, BIT5 ++#define GPIO41_IN 0x103c62, BIT0 ++#define GPIO41_OUT 0x103c62, BIT4 ++ ++#define GPIO42_PAD PAD_NAND_ALE ++#define GPIO42_OEN 0x103c82, BIT5 ++#define GPIO42_IN 0x103c82, BIT0 ++#define GPIO42_OUT 0x103c82, BIT4 ++ ++#define GPIO43_PAD PAD_NAND_CLE ++#define GPIO43_OEN 0x103c84, BIT5 ++#define GPIO43_IN 0x103c84, BIT0 ++#define GPIO43_OUT 0x103c84, BIT4 ++ ++#define GPIO44_PAD PAD_NAND_CEZ ++#define GPIO44_OEN 0x103c80, BIT5 ++#define GPIO44_IN 0x103c80, BIT0 ++#define GPIO44_OUT 0x103c80, BIT4 ++ ++#define GPIO45_PAD PAD_NAND_WEZ ++#define GPIO45_OEN 0x103c86, BIT5 ++#define GPIO45_IN 0x103c86, BIT0 ++#define GPIO45_OUT 0x103c86, BIT4 ++ ++#define GPIO46_PAD PAD_NAND_WPZ ++#define GPIO46_OEN 0x103c88, BIT5 ++#define GPIO46_IN 0x103c88, BIT0 ++#define GPIO46_OUT 0x103c88, BIT4 ++ ++#define GPIO47_PAD PAD_NAND_REZ ++#define GPIO47_OEN 0x103c8a, BIT5 ++#define GPIO47_IN 0x103c8a, BIT0 ++#define GPIO47_OUT 0x103c8a, BIT4 ++ ++#define GPIO48_PAD PAD_NAND_RBZ ++#define GPIO48_OEN 0x103c8c, BIT5 ++#define GPIO48_IN 0x103c8c, BIT0 ++#define GPIO48_OUT 0x103c8c, BIT4 ++ ++#define GPIO49_PAD PAD_NAND_DA0 ++#define GPIO49_OEN 0x103c8e, BIT5 ++#define GPIO49_IN 0x103c8e, BIT0 ++#define GPIO49_OUT 0x103c8e, BIT4 ++ ++#define GPIO50_PAD PAD_NAND_DA1 ++#define GPIO50_OEN 0x103c90, BIT5 ++#define GPIO50_IN 0x103c90, BIT0 ++#define GPIO50_OUT 0x103c90, BIT4 ++ ++#define GPIO51_PAD PAD_NAND_DA2 ++#define GPIO51_OEN 0x103c92, BIT5 ++#define GPIO51_IN 0x103c92, BIT0 ++#define GPIO51_OUT 0x103c92, BIT4 ++ ++#define GPIO52_PAD PAD_NAND_DA3 ++#define GPIO52_OEN 0x103c94, BIT5 ++#define GPIO52_IN 0x103c94, BIT0 ++#define GPIO52_OUT 0x103c94, BIT4 ++ ++#define GPIO53_PAD PAD_NAND_DA4 ++#define GPIO53_OEN 0x103c96, BIT5 ++#define GPIO53_IN 0x103c96, BIT0 ++#define GPIO53_OUT 0x103c96, BIT4 ++ ++#define GPIO54_PAD PAD_NAND_DA5 ++#define GPIO54_OEN 0x103c98, BIT5 ++#define GPIO54_IN 0x103c98, BIT0 ++#define GPIO54_OUT 0x103c98, BIT4 ++ ++#define GPIO55_PAD PAD_NAND_DA6 ++#define GPIO55_OEN 0x103c9a, BIT5 ++#define GPIO55_IN 0x103c9a, BIT0 ++#define GPIO55_OUT 0x103c9a, BIT4 ++ ++#define GPIO56_PAD PAD_NAND_DA7 ++#define GPIO56_OEN 0x103c9c, BIT5 ++#define GPIO56_IN 0x103c9c, BIT0 ++#define GPIO56_OUT 0x103c9c, BIT4 ++ ++#define GPIO57_PAD PAD_UART0_RX ++#define GPIO57_OEN 0x103c30, BIT5 ++#define GPIO57_IN 0x103c30, BIT0 ++#define GPIO57_OUT 0x103c30, BIT4 ++ ++#define GPIO58_PAD PAD_UART0_TX ++#define GPIO58_OEN 0x103c32, BIT5 ++#define GPIO58_IN 0x103c32, BIT0 ++#define GPIO58_OUT 0x103c32, BIT4 ++ ++#define GPIO59_PAD PAD_UART1_RX ++#define GPIO59_OEN 0x103c34, BIT5 ++#define GPIO59_IN 0x103c34, BIT0 ++#define GPIO59_OUT 0x103c34, BIT4 ++ ++#define GPIO60_PAD PAD_UART1_TX ++#define GPIO60_OEN 0x103c36, BIT5 ++#define GPIO60_IN 0x103c36, BIT0 ++#define GPIO60_OUT 0x103c36, BIT4 ++ ++#define GPIO61_PAD PAD_SPI0_CZ ++#define GPIO61_OEN 0x103ce0, BIT5 ++#define GPIO61_IN 0x103ce0, BIT0 ++#define GPIO61_OUT 0x103ce0, BIT4 ++ ++#define GPIO62_PAD PAD_SPI0_CK ++#define GPIO62_OEN 0x103ce2, BIT5 ++#define GPIO62_IN 0x103ce2, BIT0 ++#define GPIO62_OUT 0x103ce2, BIT4 ++ ++#define GPIO63_PAD PAD_SPI0_DI ++#define GPIO63_OEN 0x103ce4, BIT5 ++#define GPIO63_IN 0x103ce4, BIT0 ++#define GPIO63_OUT 0x103ce4, BIT4 ++ ++#define GPIO64_PAD PAD_SPI0_DO ++#define GPIO64_OEN 0x103ce6, BIT5 ++#define GPIO64_IN 0x103ce6, BIT0 ++#define GPIO64_OUT 0x103ce6, BIT4 ++ ++#define GPIO65_PAD PAD_SPI1_CZ ++#define GPIO65_OEN 0x103ce8, BIT5 ++#define GPIO65_IN 0x103ce8, BIT0 ++#define GPIO65_OUT 0x103ce8, BIT4 ++ ++#define GPIO66_PAD PAD_SPI1_CK ++#define GPIO66_OEN 0x103cea, BIT5 ++#define GPIO66_IN 0x103cea, BIT0 ++#define GPIO66_OUT 0x103cea, BIT4 ++ ++#define GPIO67_PAD PAD_SPI1_DI ++#define GPIO67_OEN 0x103cec, BIT5 ++#define GPIO67_IN 0x103cec, BIT0 ++#define GPIO67_OUT 0x103cec, BIT4 ++ ++#define GPIO68_PAD PAD_SPI1_DO ++#define GPIO68_OEN 0x103cee, BIT5 ++#define GPIO68_IN 0x103cee, BIT0 ++#define GPIO68_OUT 0x103cee, BIT4 ++ ++#define GPIO69_PAD PAD_PWM0 ++#define GPIO69_OEN 0x103c20, BIT5 ++#define GPIO69_IN 0x103c20, BIT0 ++#define GPIO69_OUT 0x103c20, BIT4 ++ ++#define GPIO70_PAD PAD_PWM1 ++#define GPIO70_OEN 0x103c22, BIT5 ++#define GPIO70_IN 0x103c22, BIT0 ++#define GPIO70_OUT 0x103c22, BIT4 ++ ++#define GPIO71_PAD PAD_SD_CLK ++#define GPIO71_OEN 0x103ca0, BIT5 ++#define GPIO71_IN 0x103ca0, BIT0 ++#define GPIO71_OUT 0x103ca0, BIT4 ++ ++#define GPIO72_PAD PAD_SD_CMD ++#define GPIO72_OEN 0x103ca2, BIT5 ++#define GPIO72_IN 0x103ca2, BIT0 ++#define GPIO72_OUT 0x103ca2, BIT4 ++ ++#define GPIO73_PAD PAD_SD_D0 ++#define GPIO73_OEN 0x103ca4, BIT5 ++#define GPIO73_IN 0x103ca4, BIT0 ++#define GPIO73_OUT 0x103ca4, BIT4 ++ ++#define GPIO74_PAD PAD_SD_D1 ++#define GPIO74_OEN 0x103ca6, BIT5 ++#define GPIO74_IN 0x103ca6, BIT0 ++#define GPIO74_OUT 0x103ca6, BIT4 ++ ++#define GPIO75_PAD PAD_SD_D2 ++#define GPIO75_OEN 0x103ca8, BIT5 ++#define GPIO75_IN 0x103ca8, BIT0 ++#define GPIO75_OUT 0x103ca8, BIT4 ++ ++#define GPIO76_PAD PAD_SD_D3 ++#define GPIO76_OEN 0x103caa, BIT5 ++#define GPIO76_IN 0x103caa, BIT0 ++#define GPIO76_OUT 0x103caa, BIT4 ++//pm gpio ++#define GPIO77_PAD PAD_PM_SD_CDZ ++#define GPIO77_OEN 0x0f8e, BIT0 ++#define GPIO77_IN 0x0f8e, BIT2 ++#define GPIO77_OUT 0x0f8e, BIT1 ++ ++#define GPIO78_PAD PAD_PM_IRIN ++#define GPIO78_OEN 0x0f28, BIT0 ++#define GPIO78_IN 0x0f28, BIT2 ++#define GPIO78_OUT 0x0f28, BIT1 ++ ++#define GPIO79_PAD PAD_PM_GPIO0 ++#define GPIO79_OEN 0x0f00, BIT0 ++#define GPIO79_IN 0x0f00, BIT2 ++#define GPIO79_OUT 0x0f00, BIT1 ++ ++#define GPIO80_PAD PAD_PM_GPIO1 ++#define GPIO80_OEN 0x0f02, BIT0 ++#define GPIO80_IN 0x0f02, BIT2 ++#define GPIO80_OUT 0x0f02, BIT1 ++ ++#define GPIO81_PAD PAD_PM_GPIO2 ++#define GPIO81_OEN 0x0f04, BIT0 ++#define GPIO81_IN 0x0f04, BIT2 ++#define GPIO81_OUT 0x0f04, BIT1 ++ ++#define GPIO82_PAD PAD_PM_GPIO3 ++#define GPIO82_OEN 0x0f06, BIT0 ++#define GPIO82_IN 0x0f06, BIT2 ++#define GPIO82_OUT 0x0f06, BIT1 ++ ++#define GPIO83_PAD PAD_PM_GPIO4 ++#define GPIO83_OEN 0x0f08, BIT0 ++#define GPIO83_IN 0x0f08, BIT2 ++#define GPIO83_OUT 0x0f08, BIT1 ++ ++#define GPIO84_PAD PAD_PM_GPIO5 ++#define GPIO84_OEN 0x0f0a, BIT0 ++#define GPIO84_IN 0x0f0a, BIT2 ++#define GPIO84_OUT 0x0f0a, BIT1 ++ ++#define GPIO85_PAD PAD_PM_GPIO6 ++#define GPIO85_OEN 0x0f0c, BIT0 ++#define GPIO85_IN 0x0f0c, BIT2 ++#define GPIO85_OUT 0x0f0c, BIT1 ++ ++#define GPIO86_PAD PAD_PM_GPIO7 ++#define GPIO86_OEN 0x0f0e, BIT0 ++#define GPIO86_IN 0x0f0e, BIT2 ++#define GPIO86_OUT 0x0f0e, BIT1 ++ ++#define GPIO87_PAD PAD_PM_GPIO8 ++#define GPIO87_OEN 0x0f10, BIT0 ++#define GPIO87_IN 0x0f10, BIT2 ++#define GPIO87_OUT 0x0f10, BIT1 ++ ++#define GPIO88_PAD PAD_PM_GPIO9 ++#define GPIO88_OEN 0x0f12, BIT0 ++#define GPIO88_IN 0x0f12, BIT2 ++#define GPIO88_OUT 0x0f12, BIT1 ++ ++#define GPIO89_PAD PAD_PM_GPIO10 ++#define GPIO89_OEN 0x0f14, BIT0 ++#define GPIO89_IN 0x0f14, BIT2 ++#define GPIO89_OUT 0x0f14, BIT1 ++ ++#define GPIO90_PAD PAD_PM_SPI_CZ ++#define GPIO90_OEN 0x0f30, BIT0 ++#define GPIO90_IN 0x0f30, BIT2 ++#define GPIO90_OUT 0x0f30, BIT1 ++ ++#define GPIO91_PAD PAD_PM_SPI_CK ++#define GPIO91_OEN 0x0f32, BIT0 ++#define GPIO91_IN 0x0f32, BIT2 ++#define GPIO91_OUT 0x0f32, BIT1 ++ ++#define GPIO92_PAD PAD_PM_SPI_DI ++#define GPIO92_OEN 0x0f34, BIT0 ++#define GPIO92_IN 0x0f34, BIT2 ++#define GPIO92_OUT 0x0f34, BIT1 ++ ++#define GPIO93_PAD PAD_PM_SPI_DO ++#define GPIO93_OEN 0x0f36, BIT0 ++#define GPIO93_IN 0x0f36, BIT2 ++#define GPIO93_OUT 0x0f36, BIT1 ++ ++#define GPIO94_PAD PAD_PM_SPI_WPZ ++#define GPIO94_OEN 0x0f88, BIT0 ++#define GPIO94_IN 0x0f88, BIT2 ++#define GPIO94_OUT 0x0f88, BIT1 ++ ++#define GPIO95_PAD PAD_PM_SPI_HLD ++#define GPIO95_OEN 0x0f8a, BIT0 ++#define GPIO95_IN 0x0f8a, BIT2 ++#define GPIO95_OUT 0x0f8a, BIT1 ++ ++#define GPIO96_PAD PAD_PM_LED0 ++#define GPIO96_OEN 0x0f94, BIT0 ++#define GPIO96_IN 0x0f94, BIT2 ++#define GPIO96_OUT 0x0f94, BIT1 ++ ++#define GPIO97_PAD PAD_PM_LED1 ++#define GPIO97_OEN 0x0f96, BIT0 ++#define GPIO97_IN 0x0f96, BIT2 ++#define GPIO97_OUT 0x0f96, BIT1 ++//SAR GPIO ++#define GPIO98_PAD PAD_SAR_GPIO0 ++#define GPIO98_OEN 0x1423, BIT0 ++#define GPIO98_IN 0x1425, BIT0 ++#define GPIO98_OUT 0x1424, BIT0 ++ ++#define GPIO99_PAD PAD_SAR_GPIO1 ++#define GPIO99_OEN 0x1423, BIT1 ++#define GPIO99_IN 0x1425, BIT1 ++#define GPIO99_OUT 0x1424, BIT1 ++ ++#define GPIO100_PAD PAD_SAR_GPIO2 ++#define GPIO100_OEN 0x1423, BIT2 ++#define GPIO100_IN 0x1425, BIT2 ++#define GPIO100_OUT 0x1424, BIT2 ++ ++#define GPIO101_PAD PAD_SAR_GPIO3 ++#define GPIO101_OEN 0x1423, BIT3 ++#define GPIO101_IN 0x1425, BIT3 ++#define GPIO101_OUT 0x1424, BIT3 ++//ETH GPIO ++#define GPIO102_PAD PAD_ETH_RN ++#define GPIO102_OEN 0x33e2, BIT4 ++#define GPIO102_IN 0x33e4, BIT4 ++#define GPIO102_OUT 0x33e4, BIT0 ++ ++#define GPIO103_PAD PAD_ETH_RP ++#define GPIO103_OEN 0x33e2, BIT5 ++#define GPIO103_IN 0x33e4, BIT5 ++#define GPIO103_OUT 0x33e4, BIT1 ++ ++#define GPIO104_PAD PAD_ETH_TN ++#define GPIO104_OEN 0x33e2, BIT6 ++#define GPIO104_IN 0x33e4, BIT6 ++#define GPIO104_OUT 0x33e4, BIT2 ++ ++#define GPIO105_PAD PAD_ETH_TP ++#define GPIO105_OEN 0x33e2, BIT7 ++#define GPIO105_IN 0x33e4, BIT7 ++#define GPIO105_OUT 0x33e4, BIT3 ++ ++ ++//USB GPIO ++#define GPIO106_PAD PAD_USB_DM ++#define GPIO106_OEN 0x14210a, BIT4 ++#define GPIO106_IN 0x142131, BIT5 ++#define GPIO106_OUT 0x14210a, BIT2 ++ ++#define GPIO107_PAD PAD_USB_DP ++#define GPIO107_OEN 0x14210a, BIT5 ++#define GPIO107_IN 0x142131, BIT4 ++#define GPIO107_OUT 0x14210a, BIT3 ++ ++#define GPIO108_PAD PAD_DM_P1 ++#define GPIO108_OEN 0x14290a, BIT4 ++#define GPIO108_IN 0x142931, BIT5 ++#define GPIO108_OUT 0x14290a, BIT2 ++ ++#define GPIO109_PAD PAD_DP_P1 ++#define GPIO109_OEN 0x14290a, BIT5 ++#define GPIO109_IN 0x142931, BIT4 ++#define GPIO109_OUT 0x142924, BIT3 ++ ++U32 gChipBaseAddr=0xFD203C00; ++U32 gPmSleepBaseAddr=0xFD001C00; ++U32 gSarBaseAddr=0xFD002800; ++U32 gRIUBaseAddr=0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), ++ ++}; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++// printk("MHal_GPIO_Init gBaseAddr=%x\n",gPadBaseAddr); ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_CHIPTOP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_CHIPTOP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_CHIPTOP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_CHIPTOP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_CHIPTOP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_CHIPTOP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_CHIPTOP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_PM_SLEEP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_PM_SLEEP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_PM_SLEEP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_SAR_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_SAR_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_SAR_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++void MHal_FuartPAD_DisableFunction(void) ++{ ++ //reg_fuart_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_FUART_MODE, BIT0|BIT1) == BIT0 ){ ++ printk("[gpio] Disable FUART\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE, DISABLE, BIT0|BIT1); ++ } ++ //reg_spi0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_SPI0_MODE, BIT0|BIT1) == (BIT0|BIT1) ){ ++ printk("[gpio] Disable SPI0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE, DISABLE, BIT0|BIT1); ++ } ++ //reg_EJ_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_EJ_MODE, BIT0|BIT1) == BIT0 ){ ++ printk("[gpio] Disable EJ_MODE\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE, BIT1|BIT0); ++ } ++} ++ ++void MHal_SPI0PAD_DisableFunction(void) ++{ ++ //REG_TEST_IN_MODE ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ ++ //spi0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_SPI0_MODE, BIT1|BIT0) == BIT0 ){ ++ printk("[gpio] Disable SPI0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE, DISABLE, BIT0|BIT1); ++ } ++ ++ //reg_EJ_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_EJ_MODE,BIT1|BIT0) == BIT1 ){ ++ printk("[gpio] Disable EJ_MODE\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ } ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ //printk("[gpio]MHal_GPIO_Pad_Set %d\n", u8IndexGPIO); ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO0: ++ case PAD_GPIO1: ++ case PAD_GPIO2: ++ case PAD_GPIO3: ++ //MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE,DISABLE,BIT0|BIT1); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2S_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO4: ++ case PAD_GPIO5: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO6: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO7: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO8: ++ case PAD_GPIO9: ++ case PAD_GPIO10: ++ case PAD_GPIO11: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO14: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE,BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO15: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE,BIT6); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_PWM0: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ ++ case PAD_PWM1: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ break; ++ ++ case PAD_FUART_RX: ++ //PWM0 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM0_MODE, BIT1|BIT0) == (BIT1|BIT0) ){ ++ printk("[gpio] Disable PWM0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE, BIT1|BIT0); ++ } ++ //reg_uart0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART0_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE, DISABLE, BIT0|BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_FUART_TX: ++ //PWM1 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM1_MODE, BIT3|BIT2) == (BIT3|BIT2) ){ ++ printk("[gpio] Disable PWM1\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE, BIT3|BIT2); ++ } ++ ++ //reg_uart0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART0_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE, DISABLE, BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_FUART_CTS: ++ //PWM2 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM2_MODE, BIT5|BIT4) == (BIT4) ){ ++ printk("[gpio] Disable PWM2\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE, BIT4); ++ } ++ ++ //reg_uart1_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART1_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART1\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE, DISABLE, BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_FUART_RTS: ++ //PWM3 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM3_MODE, BIT7|BIT6) == (BIT7|BIT6) ){ ++ printk("[gpio] Disable PWM3\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE, BIT7|BIT6); ++ } ++ ++ //reg_uart1_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART1_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART1\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE, DISABLE, BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_UART0_RX: ++ case PAD_UART0_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_UART1_RX: ++ case PAD_UART1_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO00: ++ case PAD_SR_IO01: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO02: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO03: ++ case PAD_SR_IO04: ++ case PAD_SR_IO05: ++ case PAD_SR_IO06: ++ case PAD_SR_IO07: ++ case PAD_SR_IO08: ++ case PAD_SR_IO09: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO10: ++ case PAD_SR_IO11: ++ case PAD_SR_IO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SR_IO13: ++ case PAD_SR_IO14: ++ case PAD_SR_IO15: ++ case PAD_SR_IO16: ++ case PAD_SR_IO17: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ break; ++ case PAD_NAND_ALE: ++ break; ++ case PAD_NAND_CLE: ++ case PAD_NAND_CEZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_WPZ: ++ case PAD_NAND_REZ: ++ case PAD_NAND_RBZ: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_SD_MODE,DISABLE,BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_SD_CLK: ++ case PAD_SD_CMD: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SD_D0: ++ case PAD_SD_D1: ++ case PAD_SD_D2: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SD_D3: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SDIO_MODE,DISABLE,BIT0); ++ break; ++ case PAD_I2C0_SCL: ++ case PAD_I2C0_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_I2C1_SCL: ++ case PAD_I2C1_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ break; ++ ++ case PAD_SPI0_CZ: ++ //PWM4 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT1|BIT0) == BIT1 ){ ++ printk("[gpio] Disable PWM4\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT1); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI0_CK: ++ //PWM5 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT3|BIT2) == BIT3 ){ ++ printk("[gpio] Disable PWM5\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT3); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI0_DI: ++ //PWM6 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT5|BIT4) == BIT5 ){ ++ printk("[gpio] Disable PWM6\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT5); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI0_DO: ++ //PWM7 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT7|BIT6) == BIT7 ){ ++ printk("[gpio] Disable PWM7\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT7); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI1_CZ: ++ case PAD_SPI1_CK: ++ case PAD_SPI1_DI: ++ case PAD_SPI1_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_PM_IRIN: ++ MHal_PM_SLEEP_WriteRegBit(REG_IRIN_MODE,ENABLE,BIT4); ++ break; ++ case PAD_PM_GPIO4: ++ MHal_PM_SLEEP_WriteRegBit(REG_PMLOCK_L_MODE,ENABLE,0xBE); ++ MHal_PM_SLEEP_WriteRegBit(REG_PMLOCK_H_MODE,ENABLE,0xBA); ++ break; ++ case PAD_PM_LED0: ++ case PAD_PM_LED1: ++ if( MHal_PM_SLEEP_ReadRegMsk(0x50,BIT4|BIT5) == BIT4 ){ ++ printk("[gpio] Disable eth ACK/LINK led\n"); ++ MHal_PM_SLEEP_WriteRegBit(0x50,DISABLE,BIT4); ++ } ++ break; ++ case PAD_SAR_GPIO0: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT0); ++ break; ++ case PAD_SAR_GPIO1: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT1); ++ break; ++ case PAD_SAR_GPIO2: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT2); ++ break; ++ case PAD_SAR_GPIO3: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT3); ++ break; ++ default: ++ break; ++ ++ } ++} ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++/* case PAD_GPIO7: ++ MHal_CHIPTOP_WriteRegBit(1,DISABLE,BIT7); ++ MHal_CHIPTOP_WriteRegBit(2,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break;*/ ++ default: ++ break; ++ } ++} ++ ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ //160 is PMSLEEP virtual irq start ++ if(u8IndexGPIO==PAD_PM_IRIN) ++ return INT_PMSLEEP_IRIN + 160; ++ else if(u8IndexGPIO>=PAD_PM_GPIO0 && u8IndexGPIO<=PAD_PM_GPIO10) ++ return (u8IndexGPIO - PAD_PM_GPIO0 + (INT_PMSLEEP_GPIO_0+160)); ++ ++ else if(u8IndexGPIO>=PAD_SAR_GPIO0 && u8IndexGPIO<=PAD_SAR_GPIO3) ++ return (u8IndexGPIO - PAD_SAR_GPIO0 + (INT_FIQ_SAR_GPIO_0)+GIC_SGI_NR+GIC_PPI_NR); ++ else ++ return -1; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u8IndexGPIO) ++ { ++/* case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++*/ ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/sstar/gpio/infinity3/mhal_gpio.h b/drivers/sstar/gpio/infinity3/mhal_gpio.h +new file mode 100755 +index 000000000000..4a8754ac13c9 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity3/mhal_gpio.h +@@ -0,0 +1,59 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity3/mhal_gpio_reg.h b/drivers/sstar/gpio/infinity3/mhal_gpio_reg.h +new file mode 100755 +index 000000000000..23afbe8287e0 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity3/mhal_gpio_reg.h +@@ -0,0 +1,66 @@ ++/* ++* mhal_gpio_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++////8 bit define ++//CHIPTOP ++#define REG_FUART_MODE 0x06 ++#define REG_UART0_MODE 0x06 ++#define REG_UART1_MODE 0x07 ++#define REG_SR_MODE 0x0C ++#define REG_SR_I2C_MODE 0x0C ++#define REG_PWM0_MODE 0x0E ++#define REG_PWM1_MODE 0x0E ++#define REG_PWM2_MODE 0x0E ++#define REG_PWM3_MODE 0x0E ++#define REG_PWM4_MODE 0x0F ++#define REG_NAND_MODE 0x10 ++#define REG_SD_MODE 0x10 ++#define REG_SDIO_MODE 0x11 ++#define REG_I2C0_MODE 0x12 ++#define REG_I2C1_MODE 0x12 ++#define REG_SPI0_MODE 0x18 ++#define REG_SPI1_MODE 0x18 ++#define REG_EJ_MODE 0x1E ++#define REG_ETH_MODE 0x1E ++#define REG_CCIR_MODE 0x1E ++#define REG_TTL_MODE 0x1E ++#define REG_I2S_MODE 0x1F ++#define REG_DMIC_MODE 0x1F ++#define REG_TEST_IN_MODE 0x24 ++#define REG_TEST_OUT_MODE 0x24 ++#define REG_ALL_PAD_IN 0xA1 ++ ++//PMSLEEP ++#define REG_PMLOCK_L_MODE 0x24 ++#define REG_PMLOCK_H_MODE 0x25 ++#define REG_IRIN_MODE 0x38 ++ ++//SAR ++#define REG_SAR_MODE 0x22 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity3/mhal_pinmux.c b/drivers/sstar/gpio/infinity3/mhal_pinmux.c +new file mode 100755 +index 000000000000..6d7c47ee1f6d +--- /dev/null ++++ b/drivers/sstar/gpio/infinity3/mhal_pinmux.c +@@ -0,0 +1,733 @@ ++/* ++* mhal_pinmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++//#include "mhal_gpio_reg.h" ++//#include "mhal_gpio.h" ++#include "ms_platform.h" ++#include "mdrv_types.h" ++ ++#include "padmux.h" ++#include "gpio.h" ++#define CHIPTOP_BASE_ADDR 0x101E ++#define PMSLEEP_BASE_ADDR 0x000E ++#define PM_SAR_BASE_ADDR 0x0014 ++#define ALBANY2_BASE_ADDR 0x0033 ++#define UTMI0_BASE_ADDR 0x1421 ++#define UTMI1_BASE_ADDR 0x1429 ++ ++ ++ ++ ++//16bit offset ++//CHIPTOP ++#define REG_FUART_MODE 0x03 ++#define REG_UART0_MODE 0x03 ++#define REG_UART1_MODE 0x03 ++#define REG_SR_MODE 0x06 ++#define REG_SR_I2C_MODE 0x06 ++#define REG_PWM0_MODE 0x07 ++#define REG_PWM1_MODE 0x07 ++#define REG_PWM2_MODE 0x07 ++#define REG_PWM3_MODE 0x07 ++#define REG_PWM4_MODE 0x07 ++#define REG_PWM5_MODE 0x07 ++#define REG_PWM6_MODE 0x07 ++#define REG_PWM7_MODE 0x07 ++#define REG_NAND_MODE 0x08 ++#define REG_SD_MODE 0x08 ++#define REG_SDIO_MODE 0x08 ++#define REG_I2C0_MODE 0x09 ++#define REG_I2C1_MODE 0x09 ++#define REG_SPI0_MODE 0x0c ++#define REG_SPI1_MODE 0x0c ++#define REG_EJ_MODE 0x0F ++#define REG_ETH_MODE 0x0F ++#define REG_CCIR_MODE 0x0F ++#define REG_TTL_MODE 0x0F ++#define REG_I2S_MODE 0x0F ++#define REG_DMIC_MODE 0x0F ++#define REG_TEST_IN_MODE 0x12 ++#define REG_TEST_OUT_MODE 0x12 ++#define REG_EMMC_MODE 0x13 ++#define REG_ALL_PAD_IN 0x50 ++ ++ ++//PMSLEEP ++#define REG_GPIO_PM_LOCK 0x12 ++#define REG_IR_IS_GPIO 0x1c ++#define REG_SD_CDZ_MODE 0x28 ++#define REG_PM_PWM0_MODE 0x28 ++#define REG_PM_PWM1_MODE 0x28 ++#define REG_PM_PWM2_MODE 0x28 ++#define REG_PM_PWM3_MODE 0x28 ++#define REG_LED_MODE 0x28 ++#define REG_SPI_IS_GPIO 0x35 ++ ++//SAR ++#define REG_SAR_MODE 0x11 ++ ++//EMAC ALBANY2_BASE_ADDR ++#define REG_ETH_GPIO_EN 0x71 ++ ++ ++ ++typedef struct stPadmux ++{ ++ U16 padID; ++ U16 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PADMUX; ++ ++ST_PADMUX padmux_table[]= ++{ ++ {PAD_GPIO0, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO0, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO0, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO1, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO1, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO1, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO2, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO2, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO2, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO3, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO3, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO3, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO4, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode3 */ ++ {PAD_GPIO4, CHIPTOP_BASE_ADDR, REG_DMIC_MODE, BIT8, BIT8, PINMUX_FOR_DMIC_MODE}, /* DMIC mode */ ++ ++ {PAD_GPIO5, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode3 */ ++ {PAD_GPIO5, CHIPTOP_BASE_ADDR, REG_DMIC_MODE, BIT8, BIT8, PINMUX_FOR_DMIC_MODE}, /* DMIC mode */ ++ ++ {PAD_GPIO6, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9|BIT8, PINMUX_FOR_UART1_MODE}, /* UART1 mode3 */ ++ {PAD_GPIO6, CHIPTOP_BASE_ADDR, REG_DMIC_MODE, BIT8, BIT8, PINMUX_FOR_DMIC_MODE}, /* DMIC mode */ ++ ++ {PAD_GPIO7, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9|BIT8, PINMUX_FOR_UART1_MODE}, /* UART1 mode3 */ ++ {PAD_GPIO7, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO8, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO8, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO9, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO9, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO10, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO10, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO11, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO11, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO12, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO12, CHIPTOP_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode2 */ ++ {PAD_GPIO12, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO13, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO13, CHIPTOP_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode2 */ ++ {PAD_GPIO13, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO14, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO14, CHIPTOP_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode1 */ ++ {PAD_GPIO14, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO15, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO15, CHIPTOP_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode1 */ ++ {PAD_GPIO15, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_UART0_MODE}, /* UART0 mode2 */ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode3 */ ++ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_UART0_MODE}, /* UART0 mode2 */ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT3|BIT2, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode3 */ ++ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_UART1_MODE}, /* UART1 mode2 */ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode2 */ ++ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_UART1_MODE}, /* UART1 mode2 */ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode2 */ ++ ++ {PAD_I2C0_SCL, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode1 */ ++ {PAD_I2C0_SCL, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ ++ {PAD_I2C0_SDA, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode1 */ ++ {PAD_I2C0_SDA, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ ++ {PAD_I2C1_SCL, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode1 */ ++ {PAD_I2C1_SCL, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ ++ {PAD_I2C1_SDA, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode1 */ ++ {PAD_I2C1_SDA, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode3 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode3 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode3 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode3 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_NAND_ALE, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_ALE, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA0, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA0, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT1, BIT1, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA0, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA1, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA1, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA2, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA2, CHIPTOP_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode3 */ ++ {PAD_NAND_DA2, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA3, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA3, CHIPTOP_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7|BIT6, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode3 */ ++ {PAD_NAND_DA3, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_PWM4_MODE}, /* PWM4 mode1 */ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10, BIT10, PINMUX_FOR_PWM5_MODE}, /* PWM5 mode1 */ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_PWM6_MODE}, /* PWM6 mode1 */ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT14, PINMUX_FOR_PWM7_MODE}, /* PWM7 mode1 */ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART0_RX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode1 */ ++ {PAD_UART0_RX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART0_TX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode1 */ ++ {PAD_UART0_TX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART1_RX, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_UART1_MODE},/* UART1 mode1 */ ++ {PAD_UART1_RX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART1_TX, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_UART1_MODE},/* UART1 mode1 */ ++ {PAD_UART1_TX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_PWM4_MODE}, /* PWM4 mode2 */ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10, BIT11, PINMUX_FOR_PWM5_MODE}, /* PWM5 mode2 */ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_PWM6_MODE}, /* PWM6 mode2 */ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT15, PINMUX_FOR_PWM7_MODE}, /* PWM7 mode2 */ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_CZ, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_CZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_CK, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_CK, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_DI, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_DI, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_DO, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_DO, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode2 */ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode2 */ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode1 */ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_PWM1, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode2 */ ++ {PAD_PWM1, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode2 */ ++ {PAD_PWM1, CHIPTOP_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode1 */ ++ ++ {PAD_SD_CLK, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_CLK, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_CMD, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_CMD, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D0, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D0, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D0, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D1, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D1, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D1, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D2, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D2, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D2, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D3, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D3, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D3, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_PM_SD_CDZ, PMSLEEP_BASE_ADDR, REG_SD_CDZ_MODE, BIT14, BIT14, PINMUX_FOR_SD_MODE}, ++ ++ /* PAD_PM_IRIN special case*/ ++ ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_PM_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, ++ ++ {PAD_PM_GPIO1, PMSLEEP_BASE_ADDR, REG_PM_PWM1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM1_MODE}, ++ ++ {PAD_PM_GPIO2, PMSLEEP_BASE_ADDR, REG_PM_PWM2_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_PM_GPIO3, PMSLEEP_BASE_ADDR, REG_PM_PWM3_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_PWM3_MODE}, ++ ++ /* PAD_PM_GPIO4 special case */ ++ ++ {PAD_PM_GPIO5, PMSLEEP_BASE_ADDR, REG_PM_PWM1_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_PWM1_MODE}, ++ ++ {PAD_PM_GPIO6, PMSLEEP_BASE_ADDR, REG_PM_PWM0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PWM0_MODE}, ++ ++ /* PM_GPIO7 - only config as GPIO mode */ ++ ++ {PAD_PM_GPIO8, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3|BIT2, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_GPIO9, PMSLEEP_BASE_ADDR, REG_PM_PWM2_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_PM_GPIO10, PMSLEEP_BASE_ADDR, REG_PM_PWM3_MODE,BIT9|BIT8, BIT9, PINMUX_FOR_PWM3_MODE}, ++ ++ {PAD_PM_SPI_CZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_CK, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_DI, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_DO, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_WPZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_HLD, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT7|BIT6, BIT6, PINMUX_FOR_SPI1_MODE}, ++ ++ {PAD_PM_LED0, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ ++ {PAD_PM_LED1, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ ++ {PAD_SAR_GPIO0, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT0, BIT0, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO1, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT1, BIT1, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO2, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT2, BIT2, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO3, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT3, BIT3, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_ETH_RN, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT0, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_RP, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT1, BIT1, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_TN, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_TP, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT3, BIT3, PINMUX_FOR_ETH_MODE}, ++}; ++ ++ ++S32 halCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) ++ return FALSE; ++ ++ return TRUE; ++} ++ ++S32 halPadGetVal(U32 padID, U32* mode) ++{ ++ U8 i = 0; ++ U8 fgModeIsFind = 0; ++ ++ if (FALSE == halCheckPin(padID)) ++ { ++ return FALSE; ++ } ++ ++ *mode = PINMUX_FOR_GPIO_MODE; ++ ++ switch(padID) ++ { ++ case PAD_PM_GPIO4: ++ if( INREG16((PMSLEEP_BASE_ADDR*0x200) + (REG_GPIO_PM_LOCK*0x4)) == 0xBABE ) ++ { ++ return TRUE; ++ } ++ else ++ { ++ *mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ } ++ ++ case PAD_PM_GPIO7: ++ return TRUE; ++ ++ case PAD_PM_SPI_CZ: ++ *mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ ++ case PAD_PM_IRIN: ++ if( INREG16((PMSLEEP_BASE_ADDR*0x200) + (REG_IR_IS_GPIO*0x4))&BIT4 ) ++ { ++ *mode = PINMUX_FOR_GPIO_MODE; ++ } ++ else ++ { ++ *mode = PINMUX_FOR_IRIN_MODE; ++ } ++ return TRUE; ++ ++ default: ++ for(i=0; i ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++#include "padmux.h" ++#include ++ ++#define NEW_PADMUX_EN (1) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// PADTOP ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103c00, BIT5 ++#define GPIO0_IN 0x103c00, BIT0 ++#define GPIO0_OUT 0x103c00, BIT4 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103c02, BIT5 ++#define GPIO1_IN 0x103c02, BIT0 ++#define GPIO1_OUT 0x103c02, BIT4 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103c04, BIT5 ++#define GPIO2_IN 0x103c04, BIT0 ++#define GPIO2_OUT 0x103c04, BIT4 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103c06, BIT5 ++#define GPIO3_IN 0x103c06, BIT0 ++#define GPIO3_OUT 0x103c06, BIT4 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103c08, BIT5 ++#define GPIO4_IN 0x103c08, BIT0 ++#define GPIO4_OUT 0x103c08, BIT4 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103c0a, BIT5 ++#define GPIO5_IN 0x103c0a, BIT0 ++#define GPIO5_OUT 0x103c0a, BIT4 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103c0c, BIT5 ++#define GPIO6_IN 0x103c0c, BIT0 ++#define GPIO6_OUT 0x103c0c, BIT4 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103c0e, BIT5 ++#define GPIO7_IN 0x103c0e, BIT0 ++#define GPIO7_OUT 0x103c0e, BIT4 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103c10, BIT5 ++#define GPIO8_IN 0x103c10, BIT0 ++#define GPIO8_OUT 0x103c10, BIT4 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103c12, BIT5 ++#define GPIO9_IN 0x103c12, BIT0 ++#define GPIO9_OUT 0x103c12, BIT4 ++ ++#define GPIO10_PAD PAD_GPIO10 ++#define GPIO10_OEN 0x103c14, BIT5 ++#define GPIO10_IN 0x103c14, BIT0 ++#define GPIO10_OUT 0x103c14, BIT4 ++ ++#define GPIO11_PAD PAD_GPIO11 ++#define GPIO11_OEN 0x103c16, BIT5 ++#define GPIO11_IN 0x103c16, BIT0 ++#define GPIO11_OUT 0x103c16, BIT4 ++ ++#define GPIO12_PAD PAD_GPIO12 ++#define GPIO12_OEN 0x103c18, BIT5 ++#define GPIO12_IN 0x103c18, BIT0 ++#define GPIO12_OUT 0x103c18, BIT4 ++ ++#define GPIO13_PAD PAD_GPIO13 ++#define GPIO13_OEN 0x103c1a, BIT5 ++#define GPIO13_IN 0x103c1a, BIT0 ++#define GPIO13_OUT 0x103c1a, BIT4 ++ ++#define GPIO14_PAD PAD_GPIO14 ++#define GPIO14_OEN 0x103c1c, BIT5 ++#define GPIO14_IN 0x103c1c, BIT0 ++#define GPIO14_OUT 0x103c1c, BIT4 ++ ++#define GPIO15_PAD PAD_GPIO15 ++#define GPIO15_OEN 0x103c1e, BIT5 ++#define GPIO15_IN 0x103c1e, BIT0 ++#define GPIO15_OUT 0x103c1e, BIT4 ++ ++#define GPIO16_PAD PAD_FUART_RX ++#define GPIO16_OEN 0x103c28, BIT5 ++#define GPIO16_IN 0x103c28, BIT0 ++#define GPIO16_OUT 0x103c28, BIT4 ++ ++#define GPIO17_PAD PAD_FUART_TX ++#define GPIO17_OEN 0x103c2a, BIT5 ++#define GPIO17_IN 0x103c2a, BIT0 ++#define GPIO17_OUT 0x103c2a, BIT4 ++ ++#define GPIO18_PAD PAD_FUART_CTS ++#define GPIO18_OEN 0x103c2c, BIT5 ++#define GPIO18_IN 0x103c2c, BIT0 ++#define GPIO18_OUT 0x103c2c, BIT4 ++ ++#define GPIO19_PAD PAD_FUART_RTS ++#define GPIO19_OEN 0x103c2e, BIT5 ++#define GPIO19_IN 0x103c2e, BIT0 ++#define GPIO19_OUT 0x103c2e, BIT4 ++ ++#define GPIO20_PAD PAD_I2C0_SCL ++#define GPIO20_OEN 0x103c38, BIT5 ++#define GPIO20_IN 0x103c38, BIT0 ++#define GPIO20_OUT 0x103c38, BIT4 ++ ++#define GPIO21_PAD PAD_I2C0_SDA ++#define GPIO21_OEN 0x103c3a, BIT5 ++#define GPIO21_IN 0x103c3a, BIT0 ++#define GPIO21_OUT 0x103c3a, BIT4 ++ ++#define GPIO22_PAD PAD_I2C1_SCL ++#define GPIO22_OEN 0x103c3c, BIT5 ++#define GPIO22_IN 0x103c3c, BIT0 ++#define GPIO22_OUT 0x103c3c, BIT4 ++ ++#define GPIO23_PAD PAD_I2C1_SDA ++#define GPIO23_OEN 0x103c3e, BIT5 ++#define GPIO23_IN 0x103c3e, BIT0 ++#define GPIO23_OUT 0x103c3e, BIT4 ++ ++#define GPIO24_PAD PAD_SNR0_D0 ++#define GPIO24_OEN 0x103c40, BIT5 ++#define GPIO24_IN 0x103c40, BIT0 ++#define GPIO24_OUT 0x103c40, BIT4 ++ ++#define GPIO25_PAD PAD_SNR0_D1 ++#define GPIO25_OEN 0x103c42, BIT5 ++#define GPIO25_IN 0x103c42, BIT0 ++#define GPIO25_OUT 0x103c42, BIT4 ++ ++#define GPIO26_PAD PAD_SNR0_D2 ++#define GPIO26_OEN 0x103c44, BIT5 ++#define GPIO26_IN 0x103c44, BIT0 ++#define GPIO26_OUT 0x103c44, BIT4 ++ ++#define GPIO27_PAD PAD_SNR0_D3 ++#define GPIO27_OEN 0x103c46, BIT5 ++#define GPIO27_IN 0x103c46, BIT0 ++#define GPIO27_OUT 0x103c46, BIT4 ++ ++#define GPIO28_PAD PAD_SNR0_D4 ++#define GPIO28_OEN 0x103c48, BIT5 ++#define GPIO28_IN 0x103c48, BIT0 ++#define GPIO28_OUT 0x103c48, BIT4 ++ ++#define GPIO29_PAD PAD_SNR0_D5 ++#define GPIO29_OEN 0x103c4a, BIT5 ++#define GPIO29_IN 0x103c4a, BIT0 ++#define GPIO29_OUT 0x103c4a, BIT4 ++ ++#define GPIO30_PAD PAD_SNR0_D6 ++#define GPIO30_OEN 0x103c4c, BIT5 ++#define GPIO30_IN 0x103c4c, BIT0 ++#define GPIO30_OUT 0x103c4c, BIT4 ++ ++#define GPIO31_PAD PAD_SNR0_D7 ++#define GPIO31_OEN 0x103c4e, BIT5 ++#define GPIO31_IN 0x103c4e, BIT0 ++#define GPIO31_OUT 0x103c4e, BIT4 ++ ++#define GPIO32_PAD PAD_SNR0_D8 ++#define GPIO32_OEN 0x103c50, BIT5 ++#define GPIO32_IN 0x103c50, BIT0 ++#define GPIO32_OUT 0x103c50, BIT4 ++ ++#define GPIO33_PAD PAD_SNR0_D9 ++#define GPIO33_OEN 0x103c52, BIT5 ++#define GPIO33_IN 0x103c52, BIT0 ++#define GPIO33_OUT 0x103c52, BIT4 ++ ++#define GPIO34_PAD PAD_SNR0_D10 ++#define GPIO34_OEN 0x103c54, BIT5 ++#define GPIO34_IN 0x103c54, BIT0 ++#define GPIO34_OUT 0x103c54, BIT4 ++ ++#define GPIO35_PAD PAD_SNR0_D11 ++#define GPIO35_OEN 0x103c56, BIT5 ++#define GPIO35_IN 0x103c56, BIT0 ++#define GPIO35_OUT 0x103c56, BIT4 ++ ++#define GPIO36_PAD PAD_SNR0_GPIO0 ++#define GPIO36_OEN 0x103c58, BIT5 ++#define GPIO36_IN 0x103c58, BIT0 ++#define GPIO36_OUT 0x103c58, BIT4 ++ ++#define GPIO37_PAD PAD_SNR0_GPIO1 ++#define GPIO37_OEN 0x103c5a, BIT5 ++#define GPIO37_IN 0x103c5a, BIT0 ++#define GPIO37_OUT 0x103c5a, BIT4 ++ ++#define GPIO38_PAD PAD_SNR0_GPIO2 ++#define GPIO38_OEN 0x103c5c, BIT5 ++#define GPIO38_IN 0x103c5c, BIT0 ++#define GPIO38_OUT 0x103c5c, BIT4 ++ ++#define GPIO39_PAD PAD_SNR0_GPIO3 ++#define GPIO39_OEN 0x103c5e, BIT5 ++#define GPIO39_IN 0x103c5e, BIT0 ++#define GPIO39_OUT 0x103c5e, BIT4 ++ ++#define GPIO40_PAD PAD_SNR0_GPIO4 ++#define GPIO40_OEN 0x103c60, BIT5 ++#define GPIO40_IN 0x103c60, BIT0 ++#define GPIO40_OUT 0x103c60, BIT4 ++ ++#define GPIO41_PAD PAD_SNR0_GPIO5 ++#define GPIO41_OEN 0x103c62, BIT5 ++#define GPIO41_IN 0x103c62, BIT0 ++#define GPIO41_OUT 0x103c62, BIT4 ++ ++#define GPIO42_PAD PAD_SNR0_GPIO6 ++#define GPIO42_OEN 0x103c64, BIT5 ++#define GPIO42_IN 0x103c64, BIT0 ++#define GPIO42_OUT 0x103c64, BIT4 ++ ++#define GPIO43_PAD PAD_SNR1_DA0P ++#define GPIO43_OEN 0x103c74, BIT5 ++#define GPIO43_IN 0x103c66, BIT0 ++#define GPIO43_OUT 0x103c66, BIT4 ++ ++#define GPIO44_PAD PAD_SNR1_DA0N ++#define GPIO44_OEN 0x103c76, BIT5 ++#define GPIO44_IN 0x103c68, BIT0 ++#define GPIO44_OUT 0x103c68, BIT4 ++ ++#define GPIO45_PAD PAD_SNR1_CKP ++#define GPIO45_OEN 0x103c78, BIT5 ++#define GPIO45_IN 0x103c6a, BIT0 ++#define GPIO45_OUT 0x103c6a, BIT4 ++ ++#define GPIO46_PAD PAD_SNR1_CKN ++#define GPIO46_OEN 0x103c7a, BIT5 ++#define GPIO46_IN 0x103c6c, BIT0 ++#define GPIO46_OUT 0x103c6c, BIT4 ++ ++#define GPIO47_PAD PAD_SNR1_DA1P ++#define GPIO47_OEN 0x103c7c, BIT5 ++#define GPIO47_IN 0x103c6e, BIT0 ++#define GPIO47_OUT 0x103c6e, BIT4 ++ ++#define GPIO48_PAD PAD_SNR1_DA1N ++#define GPIO48_OEN 0x103c7e, BIT5 ++#define GPIO48_IN 0x103c70, BIT0 ++#define GPIO48_OUT 0x103c70, BIT4 ++ ++#define GPIO49_PAD PAD_SNR1_GPIO0 ++#define GPIO49_OEN 0x103c66, BIT5 ++#define GPIO49_IN 0x103c72, BIT0 ++#define GPIO49_OUT 0x103c72, BIT4 ++ ++#define GPIO50_PAD PAD_SNR1_GPIO1 ++#define GPIO50_OEN 0x103c68, BIT5 ++#define GPIO50_IN 0x103c74, BIT0 ++#define GPIO50_OUT 0x103c74, BIT4 ++ ++#define GPIO51_PAD PAD_SNR1_GPIO2 ++#define GPIO51_OEN 0x103c6a, BIT5 ++#define GPIO51_IN 0x103c76, BIT0 ++#define GPIO51_OUT 0x103c76, BIT4 ++ ++#define GPIO52_PAD PAD_SNR1_GPIO3 ++#define GPIO52_OEN 0x103c6c, BIT5 ++#define GPIO52_IN 0x103c78, BIT0 ++#define GPIO52_OUT 0x103c78, BIT4 ++ ++#define GPIO53_PAD PAD_SNR1_GPIO4 ++#define GPIO53_OEN 0x103c6e, BIT5 ++#define GPIO53_IN 0x103c7a, BIT0 ++#define GPIO53_OUT 0x103c7a, BIT4 ++ ++#define GPIO54_PAD PAD_SNR1_GPIO5 ++#define GPIO54_OEN 0x103c70, BIT5 ++#define GPIO54_IN 0x103c7c, BIT0 ++#define GPIO54_OUT 0x103c7c, BIT4 ++ ++#define GPIO55_PAD PAD_SNR1_GPIO6 ++#define GPIO55_OEN 0x103c72, BIT5 ++#define GPIO55_IN 0x103c7e, BIT0 ++#define GPIO55_OUT 0x103c7e, BIT4 ++ ++#define GPIO56_PAD PAD_NAND_ALE ++#define GPIO56_OEN 0x103c82, BIT5 ++#define GPIO56_IN 0x103c82, BIT0 ++#define GPIO56_OUT 0x103c82, BIT4 ++ ++#define GPIO57_PAD PAD_NAND_CLE ++#define GPIO57_OEN 0x103c84, BIT5 ++#define GPIO57_IN 0x103c84, BIT0 ++#define GPIO57_OUT 0x103c84, BIT4 ++ ++#define GPIO58_PAD PAD_NAND_CEZ ++#define GPIO58_OEN 0x103c80, BIT5 ++#define GPIO58_IN 0x103c80, BIT0 ++#define GPIO58_OUT 0x103c80, BIT4 ++ ++#define GPIO59_PAD PAD_NAND_WEZ ++#define GPIO59_OEN 0x103c86, BIT5 ++#define GPIO59_IN 0x103c86, BIT0 ++#define GPIO59_OUT 0x103c86, BIT4 ++ ++#define GPIO60_PAD PAD_NAND_WPZ ++#define GPIO60_OEN 0x103c88, BIT5 ++#define GPIO60_IN 0x103c88, BIT0 ++#define GPIO60_OUT 0x103c88, BIT4 ++ ++#define GPIO61_PAD PAD_NAND_REZ ++#define GPIO61_OEN 0x103c8a, BIT5 ++#define GPIO61_IN 0x103c8a, BIT0 ++#define GPIO61_OUT 0x103c8a, BIT4 ++ ++#define GPIO62_PAD PAD_NAND_RBZ ++#define GPIO62_OEN 0x103c8c, BIT5 ++#define GPIO62_IN 0x103c8c, BIT0 ++#define GPIO62_OUT 0x103c8c, BIT4 ++ ++#define GPIO63_PAD PAD_NAND_DA0 ++#define GPIO63_OEN 0x103c8e, BIT5 ++#define GPIO63_IN 0x103c8e, BIT0 ++#define GPIO63_OUT 0x103c8e, BIT4 ++ ++#define GPIO64_PAD PAD_NAND_DA1 ++#define GPIO64_OEN 0x103c90, BIT5 ++#define GPIO64_IN 0x103c90, BIT0 ++#define GPIO64_OUT 0x103c90, BIT4 ++ ++#define GPIO65_PAD PAD_NAND_DA2 ++#define GPIO65_OEN 0x103c92, BIT5 ++#define GPIO65_IN 0x103c92, BIT0 ++#define GPIO65_OUT 0x103c92, BIT4 ++ ++#define GPIO66_PAD PAD_NAND_DA3 ++#define GPIO66_OEN 0x103c94, BIT5 ++#define GPIO66_IN 0x103c94, BIT0 ++#define GPIO66_OUT 0x103c94, BIT4 ++ ++#define GPIO67_PAD PAD_NAND_DA4 ++#define GPIO67_OEN 0x103c96, BIT5 ++#define GPIO67_IN 0x103c96, BIT0 ++#define GPIO67_OUT 0x103c96, BIT4 ++ ++#define GPIO68_PAD PAD_NAND_DA5 ++#define GPIO68_OEN 0x103c98, BIT5 ++#define GPIO68_IN 0x103c98, BIT0 ++#define GPIO68_OUT 0x103c98, BIT4 ++ ++#define GPIO69_PAD PAD_NAND_DA6 ++#define GPIO69_OEN 0x103c9a, BIT5 ++#define GPIO69_IN 0x103c9a, BIT0 ++#define GPIO69_OUT 0x103c9a, BIT4 ++ ++#define GPIO70_PAD PAD_NAND_DA7 ++#define GPIO70_OEN 0x103c9c, BIT5 ++#define GPIO70_IN 0x103c9c, BIT0 ++#define GPIO70_OUT 0x103c9c, BIT4 ++ ++#define GPIO71_PAD PAD_LCD_D0 ++#define GPIO71_OEN 0x103ca0, BIT5 ++#define GPIO71_IN 0x103ca0, BIT0 ++#define GPIO71_OUT 0x103ca0, BIT4 ++ ++#define GPIO72_PAD PAD_LCD_D1 ++#define GPIO72_OEN 0x103ca2, BIT5 ++#define GPIO72_IN 0x103ca2, BIT0 ++#define GPIO72_OUT 0x103ca2, BIT4 ++ ++#define GPIO73_PAD PAD_LCD_D2 ++#define GPIO73_OEN 0x103ca4, BIT5 ++#define GPIO73_IN 0x103ca4, BIT0 ++#define GPIO73_OUT 0x103ca4, BIT4 ++ ++#define GPIO74_PAD PAD_LCD_D3 ++#define GPIO74_OEN 0x103ca6, BIT5 ++#define GPIO74_IN 0x103ca6, BIT0 ++#define GPIO74_OUT 0x103ca6, BIT4 ++ ++#define GPIO75_PAD PAD_LCD_D4 ++#define GPIO75_OEN 0x103ca8, BIT5 ++#define GPIO75_IN 0x103ca8, BIT0 ++#define GPIO75_OUT 0x103ca8, BIT4 ++ ++#define GPIO76_PAD PAD_LCD_D5 ++#define GPIO76_OEN 0x103caa, BIT5 ++#define GPIO76_IN 0x103caa, BIT0 ++#define GPIO76_OUT 0x103caa, BIT4 ++ ++#define GPIO77_PAD PAD_LCD_D6 ++#define GPIO77_OEN 0x103cac, BIT5 ++#define GPIO77_IN 0x103cac, BIT0 ++#define GPIO77_OUT 0x103cac, BIT4 ++ ++#define GPIO78_PAD PAD_LCD_D7 ++#define GPIO78_OEN 0x103cae, BIT5 ++#define GPIO78_IN 0x103cae, BIT0 ++#define GPIO78_OUT 0x103cae, BIT4 ++ ++#define GPIO79_PAD PAD_LCD_D8 ++#define GPIO79_OEN 0x103cb0, BIT5 ++#define GPIO79_IN 0x103cb0, BIT0 ++#define GPIO79_OUT 0x103cb0, BIT4 ++ ++#define GPIO80_PAD PAD_LCD_D9 ++#define GPIO80_OEN 0x103cb2, BIT5 ++#define GPIO80_IN 0x103cb2, BIT0 ++#define GPIO80_OUT 0x103cb2, BIT4 ++ ++#define GPIO81_PAD PAD_LCD_D10 ++#define GPIO81_OEN 0x103cb4, BIT5 ++#define GPIO81_IN 0x103cb4, BIT0 ++#define GPIO81_OUT 0x103cb4, BIT4 ++ ++#define GPIO82_PAD PAD_LCD_D11 ++#define GPIO82_OEN 0x103cb6, BIT5 ++#define GPIO82_IN 0x103cb6, BIT0 ++#define GPIO82_OUT 0x103cb6, BIT4 ++ ++#define GPIO83_PAD PAD_LCD_D12 ++#define GPIO83_OEN 0x103cb8, BIT5 ++#define GPIO83_IN 0x103cb8, BIT0 ++#define GPIO83_OUT 0x103cb8, BIT4 ++ ++#define GPIO84_PAD PAD_LCD_D13 ++#define GPIO84_OEN 0x103cba, BIT5 ++#define GPIO84_IN 0x103cba, BIT0 ++#define GPIO84_OUT 0x103cba, BIT4 ++ ++#define GPIO85_PAD PAD_LCD_D14 ++#define GPIO85_OEN 0x103cbc, BIT5 ++#define GPIO85_IN 0x103cbc, BIT0 ++#define GPIO85_OUT 0x103cbc, BIT4 ++ ++#define GPIO86_PAD PAD_LCD_D15 ++#define GPIO86_OEN 0x103cbe, BIT5 ++#define GPIO86_IN 0x103cbe, BIT0 ++#define GPIO86_OUT 0x103cbe, BIT4 ++ ++#define GPIO87_PAD PAD_LCD_D16 ++#define GPIO87_OEN 0x103cc0, BIT5 ++#define GPIO87_IN 0x103cc0, BIT0 ++#define GPIO87_OUT 0x103cc0, BIT4 ++ ++#define GPIO88_PAD PAD_LCD_D17 ++#define GPIO88_OEN 0x103cc2, BIT5 ++#define GPIO88_IN 0x103cc2, BIT0 ++#define GPIO88_OUT 0x103cc2, BIT4 ++ ++#define GPIO89_PAD PAD_LCD_D18 ++#define GPIO89_OEN 0x103cc4, BIT5 ++#define GPIO89_IN 0x103cc4, BIT0 ++#define GPIO89_OUT 0x103cc4, BIT4 ++ ++#define GPIO90_PAD PAD_LCD_D19 ++#define GPIO90_OEN 0x103cc6, BIT5 ++#define GPIO90_IN 0x103cc6, BIT0 ++#define GPIO90_OUT 0x103cc6, BIT4 ++ ++#define GPIO91_PAD PAD_LCD_D20 ++#define GPIO91_OEN 0x103cc8, BIT5 ++#define GPIO91_IN 0x103cc8, BIT0 ++#define GPIO91_OUT 0x103cc8, BIT4 ++ ++#define GPIO92_PAD PAD_LCD_D21 ++#define GPIO92_OEN 0x103cca, BIT5 ++#define GPIO92_IN 0x103cca, BIT0 ++#define GPIO92_OUT 0x103cca, BIT4 ++ ++#define GPIO93_PAD PAD_LCD_D22 ++#define GPIO93_OEN 0x103ccc, BIT5 ++#define GPIO93_IN 0x103ccc, BIT0 ++#define GPIO93_OUT 0x103ccc, BIT4 ++ ++#define GPIO94_PAD PAD_LCD_D23 ++#define GPIO94_OEN 0x103cce, BIT5 ++#define GPIO94_IN 0x103cce, BIT0 ++#define GPIO94_OUT 0x103cce, BIT4 ++ ++#define GPIO95_PAD PAD_LCD_VSYNC ++#define GPIO95_OEN 0x103cd0, BIT5 ++#define GPIO95_IN 0x103cd0, BIT0 ++#define GPIO95_OUT 0x103cd0, BIT4 ++ ++#define GPIO96_PAD PAD_LCD_HSYNC ++#define GPIO96_OEN 0x103cd2, BIT5 ++#define GPIO96_IN 0x103cd2, BIT0 ++#define GPIO96_OUT 0x103cd2, BIT4 ++ ++#define GPIO97_PAD PAD_LCD_PCLK ++#define GPIO97_OEN 0x103cd4, BIT5 ++#define GPIO97_IN 0x103cd4, BIT0 ++#define GPIO97_OUT 0x103cd4, BIT4 ++ ++#define GPIO98_PAD PAD_LCD_DE ++#define GPIO98_OEN 0x103cd6, BIT5 ++#define GPIO98_IN 0x103cd6, BIT0 ++#define GPIO98_OUT 0x103cd6, BIT4 ++ ++#define GPIO99_PAD PAD_UART0_RX ++#define GPIO99_OEN 0x103c30, BIT5 ++#define GPIO99_IN 0x103c30, BIT0 ++#define GPIO99_OUT 0x103c30, BIT4 ++ ++#define GPIO100_PAD PAD_UART0_TX ++#define GPIO100_OEN 0x103c32, BIT5 ++#define GPIO100_IN 0x103c32, BIT0 ++#define GPIO100_OUT 0x103c32, BIT4 ++ ++#define GPIO101_PAD PAD_UART1_RX ++#define GPIO101_OEN 0x103c34, BIT5 ++#define GPIO101_IN 0x103c34, BIT0 ++#define GPIO101_OUT 0x103c34, BIT4 ++ ++#define GPIO102_PAD PAD_UART1_TX ++#define GPIO102_OEN 0x103c36, BIT5 ++#define GPIO102_IN 0x103c36, BIT0 ++#define GPIO102_OUT 0x103c36, BIT4 ++ ++#define GPIO103_PAD PAD_SPI0_CZ ++#define GPIO103_OEN 0x103ce0, BIT5 ++#define GPIO103_IN 0x103ce0, BIT0 ++#define GPIO103_OUT 0x103ce0, BIT4 ++ ++#define GPIO104_PAD PAD_SPI0_CK ++#define GPIO104_OEN 0x103ce2, BIT5 ++#define GPIO104_IN 0x103ce2, BIT0 ++#define GPIO104_OUT 0x103ce2, BIT4 ++ ++#define GPIO105_PAD PAD_SPI0_DI ++#define GPIO105_OEN 0x103ce4, BIT5 ++#define GPIO105_IN 0x103ce4, BIT0 ++#define GPIO105_OUT 0x103ce4, BIT4 ++ ++#define GPIO106_PAD PAD_SPI0_DO ++#define GPIO106_OEN 0x103ce6, BIT5 ++#define GPIO106_IN 0x103ce6, BIT0 ++#define GPIO106_OUT 0x103ce6, BIT4 ++ ++#define GPIO107_PAD PAD_SPI1_CZ ++#define GPIO107_OEN 0x103ce8, BIT5 ++#define GPIO107_IN 0x103ce8, BIT0 ++#define GPIO107_OUT 0x103ce8, BIT4 ++ ++#define GPIO108_PAD PAD_SPI1_CK ++#define GPIO108_OEN 0x103cea, BIT5 ++#define GPIO108_IN 0x103cea, BIT0 ++#define GPIO108_OUT 0x103cea, BIT4 ++ ++#define GPIO109_PAD PAD_SPI1_DI ++#define GPIO109_OEN 0x103cec, BIT5 ++#define GPIO109_IN 0x103cec, BIT0 ++#define GPIO109_OUT 0x103cec, BIT4 ++ ++#define GPIO110_PAD PAD_SPI1_DO ++#define GPIO110_OEN 0x103cee, BIT5 ++#define GPIO110_IN 0x103cee, BIT0 ++#define GPIO110_OUT 0x103cee, BIT4 ++ ++#define GPIO111_PAD PAD_PWM0 ++#define GPIO111_OEN 0x103c20, BIT5 ++#define GPIO111_IN 0x103c20, BIT0 ++#define GPIO111_OUT 0x103c20, BIT4 ++ ++#define GPIO112_PAD PAD_PWM1 ++#define GPIO112_OEN 0x103c22, BIT5 ++#define GPIO112_IN 0x103c22, BIT0 ++#define GPIO112_OUT 0x103c22, BIT4 ++ ++#define GPIO113_PAD PAD_SD_CLK ++#define GPIO113_OEN 0x103cf0, BIT5 ++#define GPIO113_IN 0x103cf0, BIT0 ++#define GPIO113_OUT 0x103cf0, BIT4 ++ ++#define GPIO114_PAD PAD_SD_CMD ++#define GPIO114_OEN 0x103cf2, BIT5 ++#define GPIO114_IN 0x103cf2, BIT0 ++#define GPIO114_OUT 0x103cf2, BIT4 ++ ++#define GPIO115_PAD PAD_SD_D0 ++#define GPIO115_OEN 0x103cf4, BIT5 ++#define GPIO115_IN 0x103cf4, BIT0 ++#define GPIO115_OUT 0x103cf4, BIT4 ++ ++#define GPIO116_PAD PAD_SD_D1 ++#define GPIO116_OEN 0x103cf6, BIT5 ++#define GPIO116_IN 0x103cf6, BIT0 ++#define GPIO116_OUT 0x103cf6, BIT4 ++ ++#define GPIO117_PAD PAD_SD_D2 ++#define GPIO117_OEN 0x103cf8, BIT5 ++#define GPIO117_IN 0x103cf8, BIT0 ++#define GPIO117_OUT 0x103cf8, BIT4 ++ ++#define GPIO118_PAD PAD_SD_D3 ++#define GPIO118_OEN 0x103cfa, BIT5 ++#define GPIO118_IN 0x103cfa, BIT0 ++#define GPIO118_OUT 0x103cfa, BIT4 ++ ++// PM ++#define GPIO119_PAD PAD_PM_SD_CDZ ++#define GPIO119_OEN 0x0f8e, BIT0 ++#define GPIO119_IN 0x0f8e, BIT2 ++#define GPIO119_OUT 0x0f8e, BIT1 ++ ++#define GPIO120_PAD PAD_PM_IRIN ++#define GPIO120_OEN 0x0f28, BIT0 ++#define GPIO120_IN 0x0f28, BIT2 ++#define GPIO120_OUT 0x0f28, BIT1 ++ ++#define GPIO121_PAD PAD_PM_GPIO0 ++#define GPIO121_OEN 0x0f00, BIT0 ++#define GPIO121_IN 0x0f00, BIT2 ++#define GPIO121_OUT 0x0f00, BIT1 ++ ++#define GPIO122_PAD PAD_PM_GPIO1 ++#define GPIO122_OEN 0x0f02, BIT0 ++#define GPIO122_IN 0x0f02, BIT2 ++#define GPIO122_OUT 0x0f02, BIT1 ++ ++#define GPIO123_PAD PAD_PM_GPIO2 ++#define GPIO123_OEN 0x0f04, BIT0 ++#define GPIO123_IN 0x0f04, BIT2 ++#define GPIO123_OUT 0x0f04, BIT1 ++ ++#define GPIO124_PAD PAD_PM_GPIO3 ++#define GPIO124_OEN 0x0f06, BIT0 ++#define GPIO124_IN 0x0f06, BIT2 ++#define GPIO124_OUT 0x0f06, BIT1 ++ ++#define GPIO125_PAD PAD_PM_GPIO4 ++#define GPIO125_OEN 0x0f08, BIT0 ++#define GPIO125_IN 0x0f08, BIT2 ++#define GPIO125_OUT 0x0f08, BIT1 ++ ++#define GPIO126_PAD PAD_PM_GPIO5 ++#define GPIO126_OEN 0x0f0a, BIT0 ++#define GPIO126_IN 0x0f0a, BIT2 ++#define GPIO126_OUT 0x0f0a, BIT1 ++ ++#define GPIO127_PAD PAD_PM_GPIO6 ++#define GPIO127_OEN 0x0f0c, BIT0 ++#define GPIO127_IN 0x0f0c, BIT2 ++#define GPIO127_OUT 0x0f0c, BIT1 ++ ++#define GPIO128_PAD PAD_PM_GPIO7 ++#define GPIO128_OEN 0x0f0e, BIT0 ++#define GPIO128_IN 0x0f0e, BIT2 ++#define GPIO128_OUT 0x0f0e, BIT1 ++ ++#define GPIO129_PAD PAD_PM_GPIO8 ++#define GPIO129_OEN 0x0f10, BIT0 ++#define GPIO129_IN 0x0f10, BIT2 ++#define GPIO129_OUT 0x0f10, BIT1 ++ ++#define GPIO130_PAD PAD_PM_GPIO9 ++#define GPIO130_OEN 0x0f12, BIT0 ++#define GPIO130_IN 0x0f12, BIT2 ++#define GPIO130_OUT 0x0f12, BIT1 ++ ++#define GPIO131_PAD PAD_PM_GPIO10 ++#define GPIO131_OEN 0x0f14, BIT0 ++#define GPIO131_IN 0x0f14, BIT2 ++#define GPIO131_OUT 0x0f14, BIT1 ++ ++#define GPIO132_PAD PAD_PM_GPIO11 ++#define GPIO132_OEN 0x0f16, BIT0 ++#define GPIO132_IN 0x0f16, BIT2 ++#define GPIO132_OUT 0x0f16, BIT1 ++ ++#define GPIO133_PAD PAD_PM_GPIO12 ++#define GPIO133_OEN 0x0f18, BIT0 ++#define GPIO133_IN 0x0f18, BIT2 ++#define GPIO133_OUT 0x0f18, BIT1 ++ ++#define GPIO134_PAD PAD_PM_GPIO13 ++#define GPIO134_OEN 0x0f1a, BIT0 ++#define GPIO134_IN 0x0f1a, BIT2 ++#define GPIO134_OUT 0x0f1a, BIT1 ++ ++#define GPIO135_PAD PAD_PM_GPIO14 ++#define GPIO135_OEN 0x0f1c, BIT0 ++#define GPIO135_IN 0x0f1c, BIT2 ++#define GPIO135_OUT 0x0f1c, BIT1 ++ ++#define GPIO136_PAD PAD_PM_GPIO15 ++#define GPIO136_OEN 0x0f1e, BIT0 ++#define GPIO136_IN 0x0f1e, BIT2 ++#define GPIO136_OUT 0x0f1e, BIT1 ++ ++#define GPIO137_PAD PAD_PM_SPI_CZ ++#define GPIO137_OEN 0x0f30, BIT0 ++#define GPIO137_IN 0x0f30, BIT2 ++#define GPIO137_OUT 0x0f30, BIT1 ++ ++#define GPIO138_PAD PAD_PM_SPI_CK ++#define GPIO138_OEN 0x0f32, BIT0 ++#define GPIO138_IN 0x0f32, BIT2 ++#define GPIO138_OUT 0x0f32, BIT1 ++ ++#define GPIO139_PAD PAD_PM_SPI_DI ++#define GPIO139_OEN 0x0f34, BIT0 ++#define GPIO139_IN 0x0f34, BIT2 ++#define GPIO139_OUT 0x0f34, BIT1 ++ ++#define GPIO140_PAD PAD_PM_SPI_DO ++#define GPIO140_OEN 0x0f36, BIT0 ++#define GPIO140_IN 0x0f36, BIT2 ++#define GPIO140_OUT 0x0f36, BIT1 ++ ++#define GPIO141_PAD PAD_PM_SPI_WPZ ++#define GPIO141_OEN 0x0f88, BIT0 ++#define GPIO141_IN 0x0f88, BIT2 ++#define GPIO141_OUT 0x0f88, BIT1 ++ ++#define GPIO142_PAD PAD_PM_SPI_HLD ++#define GPIO142_OEN 0x0f8a, BIT0 ++#define GPIO142_IN 0x0f8a, BIT2 ++#define GPIO142_OUT 0x0f8a, BIT1 ++ ++#define GPIO143_PAD PAD_PM_LED0 ++#define GPIO143_OEN 0x0f94, BIT0 ++#define GPIO143_IN 0x0f94, BIT2 ++#define GPIO143_OUT 0x0f94, BIT1 ++ ++#define GPIO144_PAD PAD_PM_LED1 ++#define GPIO144_OEN 0x0f96, BIT0 ++#define GPIO144_IN 0x0f96, BIT2 ++#define GPIO144_OUT 0x0f96, BIT1 ++ ++// SAR ++#define GPIO145_PAD PAD_SAR_GPIO0 ++#define GPIO145_OEN 0x1423, BIT0 ++#define GPIO145_IN 0x1425, BIT0 ++#define GPIO145_OUT 0x1424, BIT0 ++ ++#define GPIO146_PAD PAD_SAR_GPIO1 ++#define GPIO146_OEN 0x1423, BIT1 ++#define GPIO146_IN 0x1425, BIT1 ++#define GPIO146_OUT 0x1424, BIT1 ++ ++#define GPIO147_PAD PAD_SAR_GPIO2 ++#define GPIO147_OEN 0x1423, BIT2 ++#define GPIO147_IN 0x1425, BIT2 ++#define GPIO147_OUT 0x1424, BIT2 ++ ++#define GPIO148_PAD PAD_SAR_GPIO3 ++#define GPIO148_OEN 0x1423, BIT3 ++#define GPIO148_IN 0x1425, BIT3 ++#define GPIO148_OUT 0x1424, BIT3 ++ ++// ALBANY ++#define GPIO149_PAD PAD_ETH_RN ++#define GPIO149_OEN 0x33e2, BIT4 ++#define GPIO149_IN 0x33e4, BIT4 ++#define GPIO149_OUT 0x33e4, BIT0 ++ ++#define GPIO150_PAD PAD_ETH_RP ++#define GPIO150_OEN 0x33e2, BIT5 ++#define GPIO150_IN 0x33e4, BIT5 ++#define GPIO150_OUT 0x33e4, BIT1 ++ ++#define GPIO151_PAD PAD_ETH_TN ++#define GPIO151_OEN 0x33e2, BIT6 ++#define GPIO151_IN 0x33e4, BIT6 ++#define GPIO151_OUT 0x33e4, BIT2 ++ ++#define GPIO152_PAD PAD_ETH_TP ++#define GPIO152_OEN 0x33e2, BIT7 ++#define GPIO152_IN 0x33e4, BIT7 ++#define GPIO152_OUT 0x33e4, BIT3 ++ ++// UTMI ++#define GPIO153_PAD PAD_USB_DM ++#define GPIO153_OEN 0x14210a, BIT4 ++#define GPIO153_IN 0x142131, BIT5 ++#define GPIO153_OUT 0x14210a, BIT2 ++ ++#define GPIO154_PAD PAD_USB_DP ++#define GPIO154_OEN 0x14210a, BIT5 ++#define GPIO154_IN 0x142131, BIT4 ++#define GPIO154_OUT 0x14210a, BIT3 ++ ++#define GPIO155_PAD PAD_DM_P1 ++#define GPIO155_OEN 0x14290a, BIT4 ++#define GPIO155_IN 0x142931, BIT5 ++#define GPIO155_OUT 0x14290a, BIT2 ++ ++#define GPIO156_PAD PAD_DP_P1 ++#define GPIO156_OEN 0x14290a, BIT5 ++#define GPIO156_IN 0x142931, BIT4 ++#define GPIO156_OUT 0x142924, BIT3 ++ ++U32 gChipBaseAddr = 0xFD203C00; ++U32 gPmSleepBaseAddr = 0xFD001C00; ++U32 gSarBaseAddr = 0xFD002800; ++U32 gRIUBaseAddr = 0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), ++ __GPIO(110), __GPIO(111), __GPIO(112), __GPIO(113), __GPIO(114), ++ __GPIO(115), __GPIO(116), __GPIO(117), __GPIO(118), __GPIO(119), ++ __GPIO(120), __GPIO(121), __GPIO(122), __GPIO(123), __GPIO(124), ++ __GPIO(125), __GPIO(126), __GPIO(127), __GPIO(128), __GPIO(129), ++ __GPIO(130), __GPIO(131), __GPIO(132), __GPIO(133), __GPIO(134), ++ __GPIO(135), __GPIO(136), __GPIO(137), __GPIO(138), __GPIO(139), ++ __GPIO(140), __GPIO(141), __GPIO(142), __GPIO(143), __GPIO(144), ++ __GPIO(145), __GPIO(146), __GPIO(147), __GPIO(148), __GPIO(149), ++ __GPIO(150), __GPIO(151), __GPIO(152), __GPIO(153), __GPIO(154), ++ __GPIO(155), __GPIO(156) ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GPIO_Init(void) ++{ ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++#if (NEW_PADMUX_EN == 0) ++void MHal_CHIPTOP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if (u8Enable) ++ MHal_CHIPTOP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_CHIPTOP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_CHIPTOP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_CHIPTOP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_CHIPTOP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_CHIPTOP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_PM_SLEEP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if (u8Enable) ++ MHal_PM_SLEEP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_PM_SLEEP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_SAR_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if (u8Enable) ++ MHal_SAR_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_SAR_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++void MHal_FuartPAD_DisableFunction(U8 u8IndexGPIO) ++{ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_FUART_MODE, BIT0|BIT1|BIT2) == BIT0 ) { ++ printk("[gpio] Disable FUART\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE, DISABLE, BIT0|BIT1|BIT2); ++ } ++ else if (PAD_FUART_RTS != u8IndexGPIO) { ++ if (MHal_CHIPTOP_ReadRegMsk(REG_FUART_MODE, BIT0|BIT1|BIT2) == (BIT0|BIT1)) { ++ printk("[gpio] Disable FUART\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE, DISABLE, BIT0|BIT1|BIT2); ++ } ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_SPI0_MODE, BIT0|BIT1) == (BIT0|BIT1)) { ++ printk("[gpio] Disable SPI0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE, DISABLE, BIT0|BIT1); ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_EJ_MODE, BIT0|BIT1) == BIT0) { ++ printk("[gpio] Disable EJ_MODE\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE, BIT0|BIT1); ++ } ++ ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++} ++ ++void MHal_SPI0PAD_DisableFunction(void) ++{ ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_SPI0_MODE, BIT1|BIT0) == BIT0) { ++ printk("[gpio] Disable SPI0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE, DISABLE, BIT0|BIT1); ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_EJ_MODE,BIT1|BIT0) == BIT1) { ++ printk("[gpio] Disable EJ_MODE\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ } ++} ++#endif ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++#if (NEW_PADMUX_EN) ++ HalPadSetVal(u8IndexGPIO, PINMUX_FOR_GPIO_MODE); ++#else ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO0: ++ case PAD_GPIO1: ++ case PAD_GPIO2: ++ case PAD_GPIO3: ++ //MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE,DISABLE,BIT0|BIT1); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2S_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO4: ++ case PAD_GPIO5: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO6: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO7: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO8: ++ case PAD_GPIO9: ++ case PAD_GPIO10: ++ case PAD_GPIO11: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO14: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE,BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO15: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE,BIT6); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_PWM0: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_PWM1: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ break; ++ case PAD_FUART_RX: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM0_MODE, BIT2|BIT1|BIT0) == (BIT1|BIT0)) { ++ printk("[gpio] Disable PWM0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE, BIT2|BIT1|BIT0); ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_UART0_MODE, BIT6|BIT5|BIT4) == BIT5) { ++ printk("[gpio] Disable UART0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE, DISABLE, BIT6|BIT5|BIT4); ++ } ++ MHal_FuartPAD_DisableFunction(u8IndexGPIO); ++ break; ++ case PAD_FUART_TX: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM1_MODE, BIT5|BIT4|BIT3) == BIT4) { ++ printk("[gpio] Disable PWM1\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE, BIT5|BIT4|BIT3); ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_UART0_MODE, BIT6|BIT5|BIT4) == BIT5) { ++ printk("[gpio] Disable UART0\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE, DISABLE, BIT6|BIT5|BIT4); ++ } ++ ++ MHal_FuartPAD_DisableFunction(u8IndexGPIO); ++ break; ++ case PAD_FUART_CTS: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM2_MODE, BIT2|BIT1|BIT0) == BIT1) { ++ printk("[gpio] Disable PWM2\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE, BIT2|BIT1|BIT0); ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_UART1_MODE, BIT1|BIT0) == BIT1) { ++ printk("[gpio] Disable UART1\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE, DISABLE, BIT1|BIT0); ++ } ++ ++ MHal_FuartPAD_DisableFunction(u8IndexGPIO); ++ break; ++ case PAD_FUART_RTS: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM3_MODE, BIT6|BIT5|BIT4) == BIT5) { ++ printk("[gpio] Disable PWM3\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE, BIT6|BIT5|BIT4); ++ } ++ ++ if (MHal_CHIPTOP_ReadRegMsk(REG_UART1_MODE, BIT0|BIT1) == BIT1) { ++ printk("[gpio] Disable UART1\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE, DISABLE, BIT0|BIT1); ++ } ++ ++ MHal_FuartPAD_DisableFunction(u8IndexGPIO); ++ break; ++ case PAD_UART0_RX: ++ case PAD_UART0_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_UART1_RX: ++ case PAD_UART1_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SNR0_D0: ++ case PAD_SNR0_D1: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SNR0_D2: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SNR0_D3: ++ case PAD_SNR0_D4: ++ case PAD_SNR0_D5: ++ case PAD_SNR0_D6: ++ case PAD_SNR0_D7: ++ case PAD_SNR0_D8: ++ case PAD_SNR0_D9: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SNR0_D10: ++ case PAD_SNR0_D11: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SNR0_GPIO0: ++ case PAD_SNR0_GPIO1: ++ case PAD_SNR0_GPIO2: ++ case PAD_SNR0_GPIO3: ++ case PAD_SNR0_GPIO4: ++ case PAD_SNR0_GPIO5: ++ case PAD_SNR0_GPIO6: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ break; ++ case PAD_NAND_ALE: ++ break; ++ case PAD_NAND_CLE: ++ case PAD_NAND_CEZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_WPZ: ++ case PAD_NAND_REZ: ++ case PAD_NAND_RBZ: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_SD_MODE,DISABLE,BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_SD_CLK: ++ case PAD_SD_CMD: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SD_D0: ++ case PAD_SD_D1: ++ case PAD_SD_D2: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SD_D3: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SDIO_MODE,DISABLE,BIT0); ++ break; ++ case PAD_I2C0_SCL: ++ case PAD_I2C0_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_I2C1_SCL: ++ case PAD_I2C1_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SPI0_CZ: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT1|BIT0) == BIT1) { ++ printk("[gpio] Disable PWM4\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT1|BIT0); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ case PAD_SPI0_CK: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM5_MODE, BIT4|BIT3) == BIT4) { ++ printk("[gpio] Disable PWM5\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM5_MODE,DISABLE, BIT4|BIT3); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ case PAD_SPI0_DI: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM6_MODE, BIT1|BIT0) == BIT1) { ++ printk("[gpio] Disable PWM6\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM6_MODE,DISABLE, BIT1|BIT0); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ case PAD_SPI0_DO: ++ if (MHal_CHIPTOP_ReadRegMsk(REG_PWM7_MODE, BIT5|BIT4) == BIT5) { ++ printk("[gpio] Disable PWM7\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM7_MODE,DISABLE, BIT5|BIT4); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ case PAD_SPI1_CZ: ++ case PAD_SPI1_CK: ++ case PAD_SPI1_DI: ++ case PAD_SPI1_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_PM_IRIN: ++ MHal_PM_SLEEP_WriteRegBit(REG_IRIN_MODE,ENABLE,BIT4); ++ break; ++ case PAD_PM_GPIO4: ++ MHal_PM_SLEEP_WriteRegBit(REG_PMLOCK_L_MODE,ENABLE,0xBE); ++ MHal_PM_SLEEP_WriteRegBit(REG_PMLOCK_H_MODE,ENABLE,0xBA); ++ break; ++ case PAD_PM_LED0: ++ case PAD_PM_LED1: ++ if (MHal_PM_SLEEP_ReadRegMsk(REG_LED_MODE,BIT4|BIT5) == BIT4) { ++ printk("[gpio] Disable eth ACK/LINK led\n"); ++ MHal_PM_SLEEP_WriteRegBit(REG_LED_MODE,DISABLE,BIT4); ++ } ++ break; ++ case PAD_SAR_GPIO0: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT0); ++ break; ++ case PAD_SAR_GPIO1: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT1); ++ break; ++ case PAD_SAR_GPIO2: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT2); ++ break; ++ case PAD_SAR_GPIO3: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT3); ++ break; ++ default: ++ break; ++ } ++#endif ++} ++ ++int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ (void)u32PadMode; ++ return -1; // not support ++} ++ ++int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode) ++{ ++ (void)u8IndexGPIO; ++ (void)u32PadMode; ++ return -1; // not support ++} ++ ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ // TBD ++} ++ ++static int PMSLEEP_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if (u8IndexGPIO == PAD_PM_IRIN) ++ return INT_PMSLEEP_IRIN; ++ else if (u8IndexGPIO >= PAD_PM_GPIO0 && u8IndexGPIO <= PAD_PM_GPIO15) ++ return (u8IndexGPIO-PAD_PM_GPIO0) + INT_PMSLEEP_GPIO_0; ++ else ++ return -1; ++} ++ ++//MHal_GPIO_To_Irq return any virq ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ struct device_node *pm_intr_node; ++ struct irq_domain *pm_intr_domain; ++ struct irq_fwspec fwspec; ++ int hwirq, virq = -1; ++ ++ ++ hwirq = PMSLEEP_GPIO_To_Irq(u8IndexGPIO); ++ if( hwirq >= 0) ++ { ++ //get virtual irq number for request_irq ++ pm_intr_node = of_find_compatible_node(NULL, NULL, "sstar,pm-intc"); ++ pm_intr_domain = irq_find_host(pm_intr_node); ++ if(!pm_intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(pm_intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else if (u8IndexGPIO >= PAD_SAR_GPIO0 && u8IndexGPIO <= PAD_SAR_GPIO3) ++ { ++ struct device_node* np; ++ np = of_find_compatible_node(NULL, NULL, "sstar,sar-gpio"); ++ if (!np) { ++ return -1; ++ } ++ virq = irq_of_parse_and_map(np, u8IndexGPIO - PAD_SAR_GPIO0); ++ } ++ ++ return virq; ++ ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse) ++{ ++ // TBD ++} +diff --git a/drivers/sstar/gpio/infinity5/mhal_gpio.h b/drivers/sstar/gpio/infinity5/mhal_gpio.h +new file mode 100755 +index 000000000000..0ee3455c9839 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity5/mhal_gpio.h +@@ -0,0 +1,46 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_GPIO_H_ ++#define _MHAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode); ++extern int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _MHAL_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity5/mhal_gpio_reg.h b/drivers/sstar/gpio/infinity5/mhal_gpio_reg.h +new file mode 100755 +index 000000000000..36fe2aacaab4 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity5/mhal_gpio_reg.h +@@ -0,0 +1,85 @@ ++/* ++* mhal_gpio_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++////8 bit define ++// CHIPTOP ++#define REG_FUART_MODE 0x06 ++#define REG_UART0_MODE 0x06 ++#define REG_UART1_MODE 0x07 ++#define REG_PWM0_MODE 0x08 ++#define REG_PWM1_MODE 0x08 ++#define REG_PWM2_MODE 0x09 ++#define REG_PWM3_MODE 0x09 ++#define REG_PWM4_MODE 0x0A ++#define REG_PWM5_MODE 0x0A ++#define REG_PWM6_MODE 0x0B ++#define REG_PWM7_MODE 0x0B ++#define REG_SR_MODE 0x0C ++#define REG_SR_I2C_MODE 0x0C ++#define REG_NAND_MODE 0x10 ++#define REG_SD_MODE 0x10 ++#define REG_SDIO_MODE 0x11 ++#define REG_I2C0_MODE 0x12 ++#define REG_I2C1_MODE 0x12 ++#define REG_SPI0_MODE 0x18 ++#define REG_SPI1_MODE 0x18 ++#define REG_EJ_MODE 0x1E ++#define REG_ETH_MODE 0x1E ++#define REG_CCIR_MODE 0x1E ++#define REG_TTL_MODE 0x1E ++#define REG_DMIC_MODE 0x1F ++#define REG_I2S_MODE 0x1F ++#define REG_I2S_RX_MODE 0x20 ++#define REG_I2S_TX_MODE 0x20 ++#define REG_I2S_MCLK_MODE 0x21 ++#define REG_TEST_IN_MODE 0x24 ++#define REG_TEST_OUT_MODE 0x24 ++#define REG_EMMC_MODE 0x26 ++#define REG_SR0_BT656_MODE 0x2A ++#define REG_SR0_MIPI_MODE0 0x2A ++#define REG_SR0_MIPI_MODE1 0x2B ++#define REG_SR0_PAR_MODE 0x2B ++#define REG_I2C2_MODE 0x2D ++#define REG_I2C3_MODE 0x2D ++#define REG_SR1_BT656_MODE 0x30 ++#define REG_SR1_MIPI_MODE0 0x30 ++#define REG_SR1_MIPI_MODE1 0x31 ++#define REG_SR1_PAR_MODE 0x31 ++#define REG_ALL_PAD_IN 0xA1 ++ ++// PMSLEEP ++#define REG_PMLOCK_L_MODE 0x24 ++#define REG_PMLOCK_H_MODE 0x25 ++#define REG_IRIN_MODE 0x38 ++#define REG_LED_MODE 0x50 ++ ++// SAR ++#define REG_SAR_MODE 0x22 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/sstar/gpio/infinity5/mhal_pinmux.c b/drivers/sstar/gpio/infinity5/mhal_pinmux.c +new file mode 100755 +index 000000000000..aaf734191e68 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity5/mhal_pinmux.c +@@ -0,0 +1,1233 @@ ++/* ++* mhal_pinmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "mhal_gpio.h" ++#include "padmux.h" ++#include "gpio.h" ++ ++//============================================================================== ++// ++// MACRO DEFINE ++// ++//============================================================================== ++ ++#define BASE_RIU_PA 0xFD000000 ++#define PMSLEEP_BANK 0x000E00 ++#define SAR_BANK 0x001400 ++#define ALBANY1_BANK 0x003200 ++#define ALBANY2_BANK 0x003300 ++#define CHIPTOP_BANK 0x101E00 ++#define UTMI0_BANK 0x142100 ++#define UTMI1_BANK 0x142900 ++ ++#define _GPIO_W_WORD(addr,val) {(*(volatile u16*)(addr)) = (u16)(val);} ++#define _GPIO_W_WORD_MASK(addr,val,mask) {(*(volatile u16*)(addr)) = ((*(volatile u16*)(addr)) & ~(mask)) | ((u16)(val) & (mask));} ++#define _GPIO_R_BYTE(addr) (*(volatile u8*)(addr)) ++#define _GPIO_R_WORD_MASK(addr,mask) ((*(volatile u16*)(addr)) & (mask)) ++ ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define _RIUA_8BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + (((offset) & ~1)<<1) + ((offset) & 1) ++#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) ++ ++/* Non PM Pad : CHIPTOP_BANK */ ++#define REG_FUART_MODE 0x03 ++ #define REG_FUART_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_UART0_MODE 0x03 ++ #define REG_UART0_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_UART1_MODE 0x03 ++ #define REG_UART1_MODE_MASK BIT9|BIT8 ++#define REG_PWM0_MODE 0x04 ++ #define REG_PWM0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_PWM1_MODE 0x04 ++ #define REG_PWM1_MODE_MASK BIT5|BIT4|BIT3 ++#define REG_PWM2_MODE 0x04 ++ #define REG_PWM2_MODE_MASK BIT10|BIT9|BIT8 ++#define REG_PWM3_MODE 0x04 ++ #define REG_PWM3_MODE_MASK BIT14|BIT13|BIT12 ++#define REG_PWM4_MODE 0x05 ++ #define REG_PWM4_MODE_MASK BIT1|BIT0 ++#define REG_PWM5_MODE 0x05 ++ #define REG_PWM5_MODE_MASK BIT4|BIT3 ++#define REG_PWM6_MODE 0x05 ++ #define REG_PWM6_MODE_MASK BIT9|BIT8 ++#define REG_PWM7_MODE 0x05 ++ #define REG_PWM7_MODE_MASK BIT13|BIT12 ++#define REG_SR_MODE 0x06 ++ #define REG_SR_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_NAND_MODE 0x08 ++ #define REG_NAND_MODE_MASK BIT0 ++#define REG_SD_MODE 0x08 ++ #define REG_SD_MODE_MASK BIT3|BIT2 ++#define REG_SDIO_MODE 0x08 ++ #define REG_SDIO_MODE_MASK BIT10|BIT9|BIT8 ++#define REG_I2C0_MODE 0x09 ++ #define REG_I2C0_MODE_MASK BIT1|BIT0 ++#define REG_I2C1_MODE 0x09 ++ #define REG_I2C1_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_SPI0_MODE 0x0c ++ #define REG_SPI0_MODE_MASK BIT1|BIT0 ++#define REG_SPI1_MODE 0x0c ++ #define REG_SPI1_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_EJ_MODE 0x0f ++ #define REG_EJ_MODE_MASK BIT1|BIT0 ++#define REG_ETH_MODE 0x0f ++ #define REG_ETH_MODE_MASK BIT2 ++#define REG_TTL_MODE 0x0f ++ #define REG_TTL_MODE_MASK BIT7|BIT6 ++#define REG_DMIC_MODE 0x0f ++ #define REG_DMIC_MODE_MASK BIT10|BIT9|BIT8 ++#define REG_I2S_MODE 0x0f ++ #define REG_I2S_MODE_MASK BIT13|BIT12 ++#define REG_I2S_RX_MODE 0x10 ++ #define REG_I2S_RX_MODE_MASK BIT0 ++#define REG_I2S_TX_MODE 0x10 ++ #define REG_I2S_TX_MODE_MASK BIT4 ++#define REG_I2S_MCK_MODE 0x10 ++ #define REG_I2S_MCK_MODE_MASK BIT8 ++#define REG_TESTIN_MODE 0x12 ++ #define REG_TESTIN_MODE_MASK BIT1|BIT0 ++#define REG_TESTOUT_MODE 0x12 ++ #define REG_TESTOUT_MODE_MASK BIT5|BIT4 ++#define REG_EMMC_MODE 0x13 ++ #define REG_EMMC_MODE_MASK BIT0 ++#define REG_EMMC_RSTN_EN 0x13 ++ #define REG_EMMC_RSTN_EN_MASK BIT1 ++#define REG_SR0_BT656_MODE 0x15 ++ #define REG_SR0_BT656_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_SR0_MIPI_MODE 0x15 ++ #define REG_SR0_MIPI_MODE_MASK BIT9|BIT8|BIT7 ++#define REG_SR0_PAR_MODE 0x15 ++ #define REG_SR0_PAR_MODE_MASK BIT12|BIT11|BIT10 ++#define REG_I2C2_MODE 0x16 ++ #define REG_I2C2_MODE_MASK BIT9|BIT8 ++#define REG_I2C3_MODE 0x16 ++ #define REG_I2C3_MODE_MASK BIT12|BIT11|BIT10 ++#define REG_SR1_BT656_MODE 0x18 ++ #define REG_SR1_BT656_MODE_MASK BIT4 ++#define REG_SR1_MIPI_MODE 0x18 ++ #define REG_SR1_MIPI_MODE_MASK BIT8|BIT7 ++#define REG_SR1_PAR_MODE 0x18 ++ #define REG_SR1_PAR_MODE_MASK BIT10 ++ ++/* PM Sleep : PMSLEEP_BANK */ ++#define REG_GPIO_PM_LOCK 0x12 ++ #define REG_GPIO_PM_LOCK_MASK 0xFFFF ++#define REG_PM_GPIO_PM4_INV 0x1c ++ #define REG_PM_GPIO_PM4_INV_MASK BIT1 ++#define REG_PM_LINK_WKINT2GPIO4 0x1c ++ #define REG_PM_LINK_WKINT2GPIO4_MASK BIT3 ++#define REG_PM_IR_IS_GPIO 0x1c ++ #define REG_PM_IR_IS_GPIO_MASK BIT4 ++#define REG_PM_PWM0_MODE 0x28 ++ #define REG_PM_PWM0_MODE_MASK BIT1|BIT0 ++#define REG_PM_PWM1_MODE 0x28 ++ #define REG_PM_PWM1_MODE_MASK BIT3|BIT2 ++#define REG_PM_LED_MODE 0x28 ++ #define REG_PM_LED_MODE_MASK BIT5|BIT4 ++#define REG_PM_PWM2_MODE 0x28 ++ #define REG_PM_PWM2_MODE_MASK BIT7|BIT6 ++#define REG_PM_PWM3_MODE 0x28 ++ #define REG_PM_PWM3_MODE_MASK BIT9|BIT8 ++#define REG_PM_VID_MODE 0x28 ++ #define REG_PM_VID_MODE_MASK BIT13|BIT12 ++#define REG_PM_SD_CDZ_MODE 0x28 ++ #define REG_PM_SD_CDZ_MODE_MASK BIT14 ++#define REG_PM_SPI_IS_GPIO 0x35 ++ #define REG_PM_SPI_IS_GPIO_MASK BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0 ++#define REG_PM_UART_IS_GPIO 0x35 ++ #define REG_PM_UART_IS_GPIO_MASK BIT9|BIT8 ++ ++/* SAR : SAR_BANK, R/W 8-bits */ ++#define REG_SAR_AISEL 0x11*2 ++ #define REG_SAR_CH0_AISEL BIT0 ++ #define REG_SAR_CH1_AISEL BIT1 ++ #define REG_SAR_CH2_AISEL BIT2 ++ #define REG_SAR_CH3_AISEL BIT3 ++ ++/* EMAC : ALBANY1_BANK */ ++#define REG_ATOP_RX_INOFF 0x69 ++ #define REG_ATOP_RX_INOFF_MASK BIT15|BIT14 ++ ++/* EMAC : ALBANY2_BANK */ ++#define REG_ETH_GPIO_EN 0x71 ++ #define REG_ETH_GPIO_EN_MASK BIT3|BIT2|BIT1|BIT0 ++ ++/* UTMI0 : UTMI0_BANK */ ++#define REG_UTMI0_FL_XVR_PDN 0x0 ++ #define REG_UTMI0_FL_XVR_PDN_MASK BIT12 ++#define REG_UTMI0_REG_PDN 0x0 ++ #define REG_UTMI0_REG_PDN_MASK BIT15 ++#define REG_UTMI0_CLK_EXTRA0_EN 0x4 ++ #define REG_UTMI0_CLK_EXTRA0_EN_MASK BIT7 ++#define REG_UTMI0_GPIO_EN 0x1f ++ #define REG_UTMI0_GPIO_EN_MASK BIT14 ++ ++/* UTMI1 : UTMI1_BANK */ ++#define REG_UTMI1_FL_XVR_PDN 0x0 ++ #define REG_UTMI1_FL_XVR_PDN_MASK BIT12 ++#define REG_UTMI1_REG_PDN 0x0 ++ #define REG_UTMI1_REG_PDN_MASK BIT15 ++#define REG_UTMI1_CLK_EXTRA0_EN 0x4 ++ #define REG_UTMI1_CLK_EXTRA0_EN_MASK BIT7 ++#define REG_UTMI1_GPIO_EN 0x1f ++ #define REG_UTMI1_GPIO_EN_MASK BIT14 ++ ++//============================================================================== ++// ++// STRUCTURE ++// ++//============================================================================== ++ ++typedef struct stPadMux ++{ ++ U16 padID; ++ U32 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PadMuxInfo; ++ ++typedef struct stPadMode ++{ ++ U8 u8PadName[16]; ++ U32 u32ModeRIU; ++ U32 u32ModeMask; ++} ST_PadModeInfo; ++ ++//============================================================================== ++// ++// VARIABLES ++// ++//============================================================================== ++ ++static const ST_PadMuxInfo m_stNonPMPadMuxTbl[] = ++{ ++ {PAD_GPIO0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE}, ++ ++ {PAD_GPIO1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE}, ++ ++ {PAD_GPIO2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE}, ++ ++ {PAD_GPIO3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT12, PINMUX_FOR_I2S_MODE}, ++ ++ {PAD_GPIO4, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE}, ++ ++ {PAD_GPIO5, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE}, ++ ++ {PAD_GPIO6, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE}, ++ ++ {PAD_GPIO7, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO8, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE}, ++ {PAD_GPIO8, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO9, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE}, ++ {PAD_GPIO9, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO10, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE}, ++ {PAD_GPIO10, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO11, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE}, ++ {PAD_GPIO11, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO12, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PWM0_MODE}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO13, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4, PINMUX_FOR_PWM1_MODE}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO14, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8, PINMUX_FOR_PWM2_MODE}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO15, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT12, PINMUX_FOR_PWM3_MODE}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM0_MODE}, ++ ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM1_MODE}, ++ ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT9, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT13, PINMUX_FOR_PWM3_MODE}, ++ ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT10, PINMUX_FOR_I2C3_MODE}, ++ ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT10, PINMUX_FOR_I2C3_MODE}, ++ ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE}, ++ ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE}, ++ ++ {PAD_SNR0_D0, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D0, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ {PAD_SNR0_D0, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, ++ ++ {PAD_SNR0_D1, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D1, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D1, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ {PAD_SNR0_D1, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, ++ ++ {PAD_SNR0_D2, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D2, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D2, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D2, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D2, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D3, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D3, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D3, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D3, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D3, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D4, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D4, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D4, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D4, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D4, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D5, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D5, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D5, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D5, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D5, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D6, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D6, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D6, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D6, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D6, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D7, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D7, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D7, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D7, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D7, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D8, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D8, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D8, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D8, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D8, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D9, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D9, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D9, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D9, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D9, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D10, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D10, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D10, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_D10, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D10, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_D11, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_D11, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_D11, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_D11, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_GPIO0, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_GPIO0, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_GPIO0, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_GPIO0, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11,PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_GPIO0, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_GPIO1, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_GPIO1, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_GPIO1, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_GPIO1, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11,PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_GPIO1, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_GPIO2, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_GPIO2, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_GPIO2, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_GPIO2, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_GPIO2, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6, PINMUX_FOR_SR0_BT656_MODE}, ++ {PAD_SNR0_GPIO2, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, ++ ++ {PAD_SNR0_GPIO3, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_GPIO3, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_GPIO3, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_GPIO3, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_GPIO3, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6|BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11|BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT6, PINMUX_FOR_SR0_BT656_MODE}, ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR0_GPIO4, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10|BIT8, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_SNR0_GPIO5, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SNR0_GPIO5, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SNR0_GPIO5, CHIPTOP_BANK, REG_SR0_MIPI_MODE, REG_SR0_MIPI_MODE_MASK, BIT9|BIT7, PINMUX_FOR_SR0_MIPI_MODE}, ++ {PAD_SNR0_GPIO5, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT12|BIT11,PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_SNR0_GPIO5, CHIPTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK,BIT5|BIT4, PINMUX_FOR_SR0_BT656_MODE}, ++ ++ {PAD_SNR0_GPIO6, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_SNR1_DA0P, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_DA0P, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_DA0P, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_DA0P, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SNR1_DA0P, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE}, ++ ++ {PAD_SNR1_DA0N, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_DA0N, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_DA0N, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_DA0N, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SNR1_DA0N, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE}, ++ ++ {PAD_SNR1_CKP, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_SNR1_CKP, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_CKP, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_CKP, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_CKP, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SNR1_CKP, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE}, ++ ++ {PAD_SNR1_CKN, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_SNR1_CKN, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_CKN, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_CKN, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_CKN, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SNR1_CKN, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE}, ++ ++ {PAD_SNR1_DA1P, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_SNR1_DA1P, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_DA1P, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_DA1P, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_DA1P, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE}, ++ ++ {PAD_SNR1_DA1N, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_EJ_MODE}, ++ {PAD_SNR1_DA1N, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_DA1N, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_DA1N, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_DA1N, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE}, ++ ++ {PAD_SNR1_GPIO0, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO0, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_GPIO0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT10, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR1_GPIO1, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_GPIO1, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO1, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_GPIO1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT10, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR1_GPIO2, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO2, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_GPIO2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT10, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR1_GPIO3, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_GPIO3, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO3, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_GPIO3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT10, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR1_GPIO4, CHIPTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT8|BIT7, PINMUX_FOR_SR1_MIPI_MODE}, ++ {PAD_SNR1_GPIO4, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO4, CHIPTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK,BIT4, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SNR1_GPIO4, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT10, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR1_GPIO5, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO5, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT6, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR1_GPIO5, CHIPTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT8, PINMUX_FOR_I2C2_MODE}, ++ {PAD_SNR1_GPIO5, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT10, PINMUX_FOR_SDIO_MODE}, ++ ++ {PAD_SNR1_GPIO6, CHIPTOP_BANK, REG_SR1_PAR_MODE, REG_SR1_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR1_PAR_MODE}, ++ {PAD_SNR1_GPIO6, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT6, PINMUX_FOR_I2C1_MODE}, ++ {PAD_SNR1_GPIO6, CHIPTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT8, PINMUX_FOR_I2C2_MODE}, ++ {PAD_SNR1_GPIO6, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT14, PINMUX_FOR_PWM3_MODE}, ++ ++ {PAD_NAND_ALE, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_ALE, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_CLE, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_CLE, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE}, ++ {PAD_NAND_CLE, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_CLE, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ {PAD_NAND_CLE, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10, PINMUX_FOR_DMIC_MODE}, ++ {PAD_NAND_CLE, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_CEZ, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_CEZ, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE}, ++ {PAD_NAND_CEZ, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_CEZ, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ {PAD_NAND_CEZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_WEZ, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_WEZ, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE}, ++ {PAD_NAND_WEZ, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_WEZ, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ {PAD_NAND_WEZ, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10, PINMUX_FOR_DMIC_MODE}, ++ {PAD_NAND_WEZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_WPZ, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_WPZ, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE}, ++ {PAD_NAND_WPZ, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_WPZ, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ {PAD_NAND_WPZ, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10, PINMUX_FOR_DMIC_MODE}, ++ {PAD_NAND_WPZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_REZ, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_REZ, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE}, ++ {PAD_NAND_REZ, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_REZ, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ {PAD_NAND_REZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_RBZ, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_RBZ, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9, PINMUX_FOR_SDIO_MODE}, ++ {PAD_NAND_RBZ, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_RBZ, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ {PAD_NAND_RBZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA0, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA0, CHIPTOP_BANK, REG_EMMC_RSTN_EN, REG_EMMC_RSTN_EN_MASK, BIT1, PINMUX_FOR_EMMC_RSTN_EN}, ++ {PAD_NAND_DA0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA1, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA1, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10|BIT8, PINMUX_FOR_DMIC_MODE}, ++ {PAD_NAND_DA1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA2, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT11, PINMUX_FOR_I2C3_MODE}, ++ {PAD_NAND_DA2, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT9|BIT8, PINMUX_FOR_PWM2_MODE}, ++ {PAD_NAND_DA2, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10|BIT8, PINMUX_FOR_DMIC_MODE}, ++ {PAD_NAND_DA2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA3, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT11, PINMUX_FOR_I2C3_MODE}, ++ {PAD_NAND_DA3, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT13|BIT12,PINMUX_FOR_PWM3_MODE}, ++ {PAD_NAND_DA3, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10|BIT8, PINMUX_FOR_DMIC_MODE}, ++ {PAD_NAND_DA3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA4, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA4, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_DA4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT0, PINMUX_FOR_PWM4_MODE}, ++ {PAD_NAND_DA4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA5, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA5, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_DA5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT3, PINMUX_FOR_PWM5_MODE}, ++ {PAD_NAND_DA5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA6, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA6, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_DA6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT8, PINMUX_FOR_PWM6_MODE}, ++ {PAD_NAND_DA6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_NAND_DA7, CHIPTOP_BANK, REG_NAND_MODE, REG_NAND_MODE_MASK, BIT0, PINMUX_FOR_NAND_MODE}, ++ {PAD_NAND_DA7, CHIPTOP_BANK, REG_EMMC_MODE, REG_EMMC_MODE_MASK, BIT0, PINMUX_FOR_EMMC_MODE}, ++ {PAD_NAND_DA7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT12, PINMUX_FOR_PWM7_MODE}, ++ {PAD_NAND_DA7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D0, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT11, PINMUX_FOR_I2C3_MODE}, ++ {PAD_LCD_D0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_LCD_D0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9|BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_LCD_D0, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM2_MODE}, ++ {PAD_LCD_D0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT11, PINMUX_FOR_I2C3_MODE}, ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9|BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT14|BIT12,PINMUX_FOR_PWM3_MODE}, ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_LCD_D2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9|BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_LCD_D2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D2, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_SPI1_MODE}, ++ {PAD_LCD_D3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9|BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_LCD_D3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13, PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D3, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D4, CHIPTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9|BIT8, PINMUX_FOR_I2C2_MODE}, ++ {PAD_LCD_D4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D5, CHIPTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9|BIT8, PINMUX_FOR_I2C2_MODE}, ++ {PAD_LCD_D5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D6, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT12, PINMUX_FOR_I2C3_MODE}, ++ {PAD_LCD_D6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D7, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT12, PINMUX_FOR_I2C3_MODE}, ++ {PAD_LCD_D7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D8, CHIPTOP_BANK, REG_I2S_MCK_MODE, REG_I2S_MCK_MODE_MASK, BIT8, PINMUX_FOR_I2S_MCK_MODE}, ++ {PAD_LCD_D8, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D9, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12,PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D9, CHIPTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT0, PINMUX_FOR_I2S_RX_MODE}, ++ {PAD_LCD_D9, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D10, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12,PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D10, CHIPTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT0, PINMUX_FOR_I2S_RX_MODE}, ++ {PAD_LCD_D10, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D11, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12,PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D11, CHIPTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT0, PINMUX_FOR_I2S_RX_MODE}, ++ {PAD_LCD_D11, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D12, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT13|BIT12,PINMUX_FOR_I2S_MODE}, ++ {PAD_LCD_D12, CHIPTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT4, PINMUX_FOR_I2S_TX_MODE}, ++ {PAD_LCD_D12, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D13, CHIPTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT4, PINMUX_FOR_I2S_TX_MODE}, ++ {PAD_LCD_D13, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10|BIT9, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D13, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D14, CHIPTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT4, PINMUX_FOR_I2S_TX_MODE}, ++ {PAD_LCD_D14, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10|BIT9, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D15, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT10|BIT9|BIT8, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D16, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D17, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D18, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D18, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D19, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE}, ++ {PAD_LCD_D19, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D20, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE}, ++ {PAD_LCD_D20, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D21, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE}, ++ {PAD_LCD_D21, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D22, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE}, ++ {PAD_LCD_D22, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_D23, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE}, ++ {PAD_LCD_D23, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_VSYNC, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_LCD_VSYNC, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2, PINMUX_FOR_PWM0_MODE}, ++ {PAD_LCD_VSYNC, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_HSYNC, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_LCD_HSYNC, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9|BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_LCD_HSYNC, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5, PINMUX_FOR_PWM1_MODE}, ++ {PAD_LCD_HSYNC, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_PCLK, CHIPTOP_BANK, REG_SR0_PAR_MODE, REG_SR0_PAR_MODE_MASK, BIT10, PINMUX_FOR_SR0_PAR_MODE}, ++ {PAD_LCD_PCLK, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT9|BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_LCD_PCLK, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_LCD_DE, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7|BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9, PINMUX_FOR_I2C2_MODE}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT12|BIT10,PINMUX_FOR_I2C3_MODE}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9, PINMUX_FOR_I2C2_MODE}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_I2C3_MODE, REG_I2C3_MODE_MASK, BIT12|BIT10,PINMUX_FOR_I2C3_MODE}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE}, ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT1, PINMUX_FOR_PWM4_MODE}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT4, PINMUX_FOR_PWM5_MODE}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT9, PINMUX_FOR_PWM6_MODE}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT4, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT13, PINMUX_FOR_PWM7_MODE}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI1_CZ, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SPI1_CZ, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI1_CK, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SPI1_CK, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI1_DI, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SPI1_DI, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_SPI1_DO, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SPI1_DO, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_PWM0, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PWM0_MODE}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10|BIT9|BIT8, PINMUX_FOR_PWM2_MODE}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE}, ++ ++ {PAD_PWM1, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT3, PINMUX_FOR_PWM1_MODE}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT14|BIT13,PINMUX_FOR_PWM3_MODE}, ++ ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT3, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT3, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT3, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT3, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT3, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TESTIN_MODE, REG_TESTIN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TESTIN_MODE}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TESTOUT_MODE, REG_TESTOUT_MODE_MASK, BIT5, PINMUX_FOR_TESTOUT_MODE}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT3, PINMUX_FOR_SD_MODE}, ++}; ++ ++static const ST_PadModeInfo m_stPadModeInfoTbl[] = ++{ ++ {"GPIO", 0, 0}, ++ // Non PM ++ {"FUART", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"UART0", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"PWM0", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM6", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM7", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"SR", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"NAND", _RIUA_16BIT(CHIPTOP_BANK,REG_NAND_MODE), REG_NAND_MODE_MASK}, ++ {"SD", _RIUA_16BIT(CHIPTOP_BANK,REG_SD_MODE), REG_SD_MODE_MASK}, ++ {"SDIO", _RIUA_16BIT(CHIPTOP_BANK,REG_SDIO_MODE), REG_SDIO_MODE_MASK}, ++ {"I2C0", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"SPI0", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"EJ", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"ETH", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH_MODE), REG_ETH_MODE_MASK}, ++ {"TTL", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"DMIC", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"I2S", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_RX", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_RX_MODE), REG_I2S_RX_MODE_MASK}, ++ {"I2S_TX", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_MCK", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MCK_MODE), REG_I2S_MCK_MODE_MASK}, ++ {"TESTIN", _RIUA_16BIT(CHIPTOP_BANK,REG_TESTIN_MODE), REG_TESTIN_MODE_MASK}, ++ {"TESTOUT", _RIUA_16BIT(CHIPTOP_BANK,REG_TESTOUT_MODE), REG_TESTOUT_MODE_MASK}, ++ {"EMMC", _RIUA_16BIT(CHIPTOP_BANK,REG_EMMC_MODE), REG_EMMC_MODE_MASK}, ++ {"EMMC_RSTN",_RIUA_16BIT(CHIPTOP_BANK,REG_EMMC_RSTN_EN), REG_EMMC_RSTN_EN_MASK}, ++ {"SR0_BT656",_RIUA_16BIT(CHIPTOP_BANK,REG_SR0_BT656_MODE), REG_SR0_BT656_MODE_MASK}, ++ {"SR0_MIPI",_RIUA_16BIT(CHIPTOP_BANK,REG_SR0_MIPI_MODE), REG_SR0_MIPI_MODE_MASK}, ++ {"SR0_PAR", _RIUA_16BIT(CHIPTOP_BANK,REG_SR0_PAR_MODE), REG_SR0_PAR_MODE_MASK}, ++ {"I2C2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C2_MODE), REG_I2C2_MODE_MASK}, ++ {"I2C3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C3_MODE), REG_I2C3_MODE_MASK}, ++ {"SR1_BT656",_RIUA_16BIT(CHIPTOP_BANK,REG_SR1_BT656_MODE), REG_SR1_BT656_MODE_MASK}, ++ {"SR1_MIPI",_RIUA_16BIT(CHIPTOP_BANK,REG_SR1_MIPI_MODE), REG_SR1_MIPI_MODE_MASK}, ++ {"SR1_PAR", _RIUA_16BIT(CHIPTOP_BANK,REG_SR1_PAR_MODE), REG_SR1_PAR_MODE_MASK}, ++ // PM Sleep ++ {"PM_IR_GPIO",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), REG_PM_IR_IS_GPIO_MASK}, ++ {"PM_PWM0", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, ++ {"PM_LED", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, ++ {"PM_PWM2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, ++ {"PM_PWM3", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, ++ {"PM_VID", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_SD_CDZ",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SD_CDZ_MODE), REG_PM_SD_CDZ_MODE_MASK}, ++ {"PM_SPI_GPIO",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO),REG_PM_SPI_IS_GPIO_MASK}, ++ {"PM_UART_GPIO",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART_IS_GPIO), REG_PM_UART_IS_GPIO_MASK}, ++}; ++ ++//============================================================================== ++// ++// FUNCTIONS ++// ++//============================================================================== ++ ++//------------------------------------------------------------------------------ ++// Function : _HalCheckPin ++// Description : ++//------------------------------------------------------------------------------ ++static S32 _HalCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++static void _HalSARGPIOWriteRegBit(u32 u32RegOffset, bool bEnable, U8 u8BitMsk) ++{ ++ if (bEnable) ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) |= u8BitMsk; ++ else ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) &= (~u8BitMsk); ++} ++ ++static void _HalPadDisablePadMux(U32 u32PadModeID) ++{ ++ if (_GPIO_R_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask)) { ++ _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, 0, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask); ++ } ++} ++ ++static S32 HalPadSetMode_NonPM(U32 u32PadID, U32 u32Mode) ++{ ++ U32 u32RegAddr = 0; ++ U16 u16RegVal = 0; ++ U8 u8ModeIsFind = 0; ++ U16 i = 0; ++ ++ for (i = 0; i < sizeof(m_stNonPMPadMuxTbl)/sizeof(struct stPadMux); i++) ++ { ++ if (u32PadID == m_stNonPMPadMuxTbl[i].padID) ++ { ++ u32RegAddr = _RIUA_16BIT(m_stNonPMPadMuxTbl[i].base, m_stNonPMPadMuxTbl[i].offset); ++ ++ if (u32Mode == m_stNonPMPadMuxTbl[i].mode) ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stNonPMPadMuxTbl[i].mask); ++ u16RegVal |= m_stNonPMPadMuxTbl[i].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ ++ u8ModeIsFind = 1; ++ break; ++ } ++ else ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stNonPMPadMuxTbl[i].mask); ++ ++ if (u16RegVal == m_stNonPMPadMuxTbl[i].val) { ++ _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stNonPMPadMuxTbl[i].mask); ++ } ++ } ++ } ++ } ++ ++ return (u8ModeIsFind) ? TRUE : FALSE; ++} ++ ++static S32 HalPadSetMode_PM(U32 u32PadID, U32 u32Mode) ++{ ++ switch(u32PadID) ++ { ++ case PAD_PM_SD_CDZ: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_PM_SD_CDZ_MODE); ++ } ++ else { //enable CDZ function, so ISR can work ++ _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[PINMUX_FOR_PM_SD_CDZ_MODE].u32ModeRIU, ++ m_stPadModeInfoTbl[PINMUX_FOR_PM_SD_CDZ_MODE].u32ModeMask, ++ m_stPadModeInfoTbl[PINMUX_FOR_PM_SD_CDZ_MODE].u32ModeMask); ++ } ++ break; ++ case PAD_PM_IRIN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), REG_PM_IR_IS_GPIO_MASK, REG_PM_IR_IS_GPIO_MASK); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), ~REG_PM_IR_IS_GPIO_MASK, REG_PM_IR_IS_GPIO_MASK); ++ } ++ break; ++ case PAD_PM_GPIO0: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM0_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_PM_VID_MODE); ++ } ++ break; ++ case PAD_PM_GPIO1: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM1_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART_IS_GPIO), ~REG_PM_IR_IS_GPIO_MASK, REG_PM_IR_IS_GPIO_MASK); ++ } ++ break; ++ case PAD_PM_GPIO2: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM2_MODE); ++ } ++ break; ++ case PAD_PM_GPIO3: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM3_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_PM_VID_MODE); ++ } ++ break; ++ case PAD_PM_GPIO4: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), ~REG_PM_LINK_WKINT2GPIO4_MASK, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), ~REG_PM_GPIO_PM4_INV_MASK, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD(_RIUA_16BIT(PMSLEEP_BANK,REG_GPIO_PM_LOCK), 0xBABE); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), REG_PM_LINK_WKINT2GPIO4_MASK, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), REG_PM_GPIO_PM4_INV_MASK, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD(_RIUA_16BIT(PMSLEEP_BANK,REG_GPIO_PM_LOCK), 0x0); ++ } ++ break; ++ case PAD_PM_GPIO5: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM1_MODE); ++ } ++ break; ++ case PAD_PM_GPIO6: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM0_MODE); ++ } ++ break; ++ case PAD_PM_GPIO7: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_VID_MODE); ++ } ++ break; ++ case PAD_PM_GPIO8: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ if ((Chip_Get_Storage_Type() == MS_STORAGE_SPINAND_ECC) || (Chip_Get_Storage_Type() == MS_STORAGE_SPINAND_NOECC)) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT3, BIT3|BIT5|BIT8); ++ } ++ else ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT3|BIT5, BIT2|BIT3|BIT5|BIT8); ++ } ++ _HalPadDisablePadMux(PINMUX_FOR_PM_UART_IS_GPIO); ++ } ++ else { ++ //_GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT2, BIT2); ++ //_GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT3, BIT3); ++ //_GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT5, BIT5); ++ //_GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT8, BIT8); ++ } ++ break; ++ case PAD_PM_GPIO9: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM2_MODE); ++ } ++ break; ++ case PAD_PM_GPIO10: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_PWM3_MODE); ++ } ++ break; ++ case PAD_PM_GPIO11: ++ case PAD_PM_GPIO12: ++ break; ++ case PAD_PM_GPIO13: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT3, BIT3); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT5, BIT5); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT3, BIT3); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT5, BIT5); ++ } ++ break; ++ case PAD_PM_GPIO14: ++ case PAD_PM_GPIO15: ++ break; ++ case PAD_PM_SPI_CZ: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT2, BIT2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT3, BIT3); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT5, BIT5); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT2, BIT2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT3, BIT3); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT5, BIT5); ++ } ++ break; ++ case PAD_PM_SPI_CK: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT0, BIT0); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT0, BIT0); ++ } ++ break; ++ case PAD_PM_SPI_DI: ++ case PAD_PM_SPI_DO: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT0, BIT0); ++ } ++ else { ++ //CHECK ++ //_GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT0|BIT1|BIT2, BIT0|BIT1|BIT2); ++ } ++ break; ++ case PAD_PM_SPI_WPZ: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT4, BIT4); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), ~BIT4, BIT4); ++ } ++ break; ++ case PAD_PM_SPI_HLD: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), BIT6, BIT6|BIT7); ++ } ++ else { ++ //CHECK ++ //_GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_IS_GPIO), 0, BIT6|BIT7); ++ } ++ break; ++ case PAD_PM_LED0: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_VID_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_PM_LED_MODE); ++ } ++ break; ++ case PAD_PM_LED1: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_PM_VID_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_PM_LED_MODE); ++ } ++ break; ++ case PAD_SAR_GPIO0: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, 0, REG_SAR_CH0_AISEL); ++ } ++ else { ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, REG_SAR_CH0_AISEL, REG_SAR_CH0_AISEL); ++ } ++ break; ++ case PAD_SAR_GPIO1: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, 0, REG_SAR_CH1_AISEL); ++ } ++ else { ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, REG_SAR_CH1_AISEL, REG_SAR_CH1_AISEL); ++ } ++ break; ++ case PAD_SAR_GPIO2: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, 0, REG_SAR_CH2_AISEL); ++ } ++ else { ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, REG_SAR_CH2_AISEL, REG_SAR_CH2_AISEL); ++ } ++ break; ++ case PAD_SAR_GPIO3: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, 0, REG_SAR_CH3_AISEL); ++ } ++ else { ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL, REG_SAR_CH3_AISEL, REG_SAR_CH3_AISEL); ++ } ++ break; ++ case PAD_ETH_RN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT0, BIT0); ++ } ++ break; ++ case PAD_ETH_RP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT1, BIT1); ++ } ++ break; ++ case PAD_ETH_TN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT2, BIT2); ++ } ++ break; ++ case PAD_ETH_TP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT3, BIT3); ++ } ++ break; ++ case PAD_USB_DM: ++ case PAD_USB_DP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TESTIN_MODE); ++ _HalPadDisablePadMux(PINMUX_FOR_TESTOUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), ~REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), ~REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), ~REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), ~REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ break; ++ case PAD_DM_P1: ++ case PAD_DP_P1: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_GPIO_EN), REG_UTMI1_GPIO_EN_MASK, REG_UTMI1_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_CLK_EXTRA0_EN), ~REG_UTMI1_CLK_EXTRA0_EN_MASK, REG_UTMI1_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_REG_PDN), ~REG_UTMI1_REG_PDN_MASK, REG_UTMI1_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_FL_XVR_PDN), ~REG_UTMI1_FL_XVR_PDN_MASK, REG_UTMI1_FL_XVR_PDN_MASK); ++ } ++ else { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_GPIO_EN), ~REG_UTMI1_GPIO_EN_MASK, REG_UTMI1_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_CLK_EXTRA0_EN), REG_UTMI1_CLK_EXTRA0_EN_MASK, REG_UTMI1_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_REG_PDN), REG_UTMI1_REG_PDN_MASK, REG_UTMI1_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI1_BANK,REG_UTMI1_FL_XVR_PDN), REG_UTMI1_FL_XVR_PDN_MASK, REG_UTMI1_FL_XVR_PDN_MASK); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalPadSetVal ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetVal(U32 u32PadID, U32 u32Mode) ++{ ++ if (FALSE == _HalCheckPin(u32PadID)) { ++ return FALSE; ++ } ++ ++ if (u32PadID >= PAD_GPIO0 && u32PadID <= PAD_SD_D3) { ++ return HalPadSetMode_NonPM(u32PadID, u32Mode); ++ } ++ else { ++ return HalPadSetMode_PM(u32PadID, u32Mode); ++ } ++} +diff --git a/drivers/sstar/gpio/infinity6/Makefile b/drivers/sstar/gpio/infinity6/Makefile +new file mode 100755 +index 000000000000..01cd644f4e48 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6/Makefile +@@ -0,0 +1,14 @@ ++# ++# Makefile for MStar GPIO device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mhal_gpio.o ++obj-$(CONFIG_MS_GPIO) += mhal_pinmux.o +diff --git a/drivers/sstar/gpio/infinity6/mhal_gpio.c b/drivers/sstar/gpio/infinity6/mhal_gpio.c +new file mode 100755 +index 000000000000..68b482943b6d +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6/mhal_gpio.c +@@ -0,0 +1,846 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include "mhal_gpio.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++#include "padmux.h" ++#include "mhal_pinmux.h" ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// PADTOP ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103C00, BIT5 ++#define GPIO0_OUT 0x103C00, BIT4 ++#define GPIO0_IN 0x103C00, BIT0 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103C02, BIT5 ++#define GPIO1_OUT 0x103C02, BIT4 ++#define GPIO1_IN 0x103C02, BIT0 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103C04, BIT5 ++#define GPIO2_OUT 0x103C04, BIT4 ++#define GPIO2_IN 0x103C04, BIT0 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103C06, BIT5 ++#define GPIO3_OUT 0x103C06, BIT4 ++#define GPIO3_IN 0x103C06, BIT0 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103C08, BIT5 ++#define GPIO4_OUT 0x103C08, BIT4 ++#define GPIO4_IN 0x103C08, BIT0 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103C0A, BIT5 ++#define GPIO5_OUT 0x103C0A, BIT4 ++#define GPIO5_IN 0x103C0A, BIT0 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103C0C, BIT5 ++#define GPIO6_OUT 0x103C0C, BIT4 ++#define GPIO6_IN 0x103C0C, BIT0 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103C0E, BIT5 ++#define GPIO7_OUT 0x103C0E, BIT4 ++#define GPIO7_IN 0x103C0E, BIT0 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103C10, BIT5 ++#define GPIO8_OUT 0x103C10, BIT4 ++#define GPIO8_IN 0x103C10, BIT0 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103C12, BIT5 ++#define GPIO9_OUT 0x103C12, BIT4 ++#define GPIO9_IN 0x103C12, BIT0 ++ ++#define GPIO10_PAD PAD_GPIO12 ++#define GPIO10_OEN 0x103C18, BIT5 ++#define GPIO10_OUT 0x103C18, BIT4 ++#define GPIO10_IN 0x103C18, BIT0 ++ ++#define GPIO11_PAD PAD_GPIO13 ++#define GPIO11_OEN 0x103C1A, BIT5 ++#define GPIO11_OUT 0x103C1A, BIT4 ++#define GPIO11_IN 0x103C1A, BIT0 ++ ++#define GPIO12_PAD PAD_GPIO14 ++#define GPIO12_OEN 0x103C1C, BIT5 ++#define GPIO12_OUT 0x103C1C, BIT4 ++#define GPIO12_IN 0x103C1C, BIT0 ++ ++#define GPIO13_PAD PAD_GPIO15 ++#define GPIO13_OEN 0x103C1E, BIT5 ++#define GPIO13_OUT 0x103C1E, BIT4 ++#define GPIO13_IN 0x103C1E, BIT0 ++ ++#define GPIO14_PAD PAD_FUART_RX ++#define GPIO14_OEN 0x103C28, BIT5 ++#define GPIO14_OUT 0x103C28, BIT4 ++#define GPIO14_IN 0x103C28, BIT0 ++ ++#define GPIO15_PAD PAD_FUART_TX ++#define GPIO15_OEN 0x103C2A, BIT5 ++#define GPIO15_OUT 0x103C2A, BIT4 ++#define GPIO15_IN 0x103C2A, BIT0 ++ ++#define GPIO16_PAD PAD_FUART_CTS ++#define GPIO16_OEN 0x103C2C, BIT5 ++#define GPIO16_OUT 0x103C2C, BIT4 ++#define GPIO16_IN 0x103C2C, BIT0 ++ ++#define GPIO17_PAD PAD_FUART_RTS ++#define GPIO17_OEN 0x103C2E, BIT5 ++#define GPIO17_OUT 0x103C2E, BIT4 ++#define GPIO17_IN 0x103C2E, BIT0 ++ ++#define GPIO18_PAD PAD_I2C0_SCL ++#define GPIO18_OEN 0x103CC0, BIT5 ++#define GPIO18_OUT 0x103CC0, BIT4 ++#define GPIO18_IN 0x103CC0, BIT0 ++ ++#define GPIO19_PAD PAD_I2C0_SDA ++#define GPIO19_OEN 0x103CC2, BIT5 ++#define GPIO19_OUT 0x103CC2, BIT4 ++#define GPIO19_IN 0x103CC2, BIT0 ++ ++#define GPIO20_PAD PAD_I2C1_SCL ++#define GPIO20_OEN 0x103CC4, BIT5 ++#define GPIO20_OUT 0x103CC4, BIT4 ++#define GPIO20_IN 0x103CC4, BIT0 ++ ++#define GPIO21_PAD PAD_I2C1_SDA ++#define GPIO21_OEN 0x103CC6, BIT5 ++#define GPIO21_OUT 0x103CC6, BIT4 ++#define GPIO21_IN 0x103CC6, BIT0 ++ ++#define GPIO22_PAD PAD_SR_IO00 ++#define GPIO22_OEN 0x103C40, BIT5 ++#define GPIO22_OUT 0x103C40, BIT4 ++#define GPIO22_IN 0x103C40, BIT0 ++ ++#define GPIO23_PAD PAD_SR_IO01 ++#define GPIO23_OEN 0x103C42, BIT5 ++#define GPIO23_OUT 0x103C42, BIT4 ++#define GPIO23_IN 0x103C42, BIT0 ++ ++#define GPIO24_PAD PAD_SR_IO02 ++#define GPIO24_OEN 0x103C44, BIT5 ++#define GPIO24_OUT 0x103C44, BIT4 ++#define GPIO24_IN 0x103C44, BIT0 ++ ++#define GPIO25_PAD PAD_SR_IO03 ++#define GPIO25_OEN 0x103C46, BIT5 ++#define GPIO25_OUT 0x103C46, BIT4 ++#define GPIO25_IN 0x103C46, BIT0 ++ ++#define GPIO26_PAD PAD_SR_IO04 ++#define GPIO26_OEN 0x103C48, BIT5 ++#define GPIO26_OUT 0x103C48, BIT4 ++#define GPIO26_IN 0x103C48, BIT0 ++ ++#define GPIO27_PAD PAD_SR_IO05 ++#define GPIO27_OEN 0x103C4A, BIT5 ++#define GPIO27_OUT 0x103C4A, BIT4 ++#define GPIO27_IN 0x103C4A, BIT0 ++ ++#define GPIO28_PAD PAD_SR_IO06 ++#define GPIO28_OEN 0x103C4C, BIT5 ++#define GPIO28_OUT 0x103C4C, BIT4 ++#define GPIO28_IN 0x103C4C, BIT0 ++ ++#define GPIO29_PAD PAD_SR_IO07 ++#define GPIO29_OEN 0x103C4E, BIT5 ++#define GPIO29_OUT 0x103C4E, BIT4 ++#define GPIO29_IN 0x103C4E, BIT0 ++ ++#define GPIO30_PAD PAD_SR_IO08 ++#define GPIO30_OEN 0x103C50, BIT5 ++#define GPIO30_OUT 0x103C50, BIT4 ++#define GPIO30_IN 0x103C50, BIT0 ++ ++#define GPIO31_PAD PAD_SR_IO09 ++#define GPIO31_OEN 0x103C52, BIT5 ++#define GPIO31_OUT 0x103C52, BIT4 ++#define GPIO31_IN 0x103C52, BIT0 ++ ++#define GPIO32_PAD PAD_SR_IO10 ++#define GPIO32_OEN 0x103C54, BIT5 ++#define GPIO32_OUT 0x103C54, BIT4 ++#define GPIO32_IN 0x103C54, BIT0 ++ ++#define GPIO33_PAD PAD_SR_IO11 ++#define GPIO33_OEN 0x103C56, BIT5 ++#define GPIO33_OUT 0x103C56, BIT4 ++#define GPIO33_IN 0x103C56, BIT0 ++ ++#define GPIO34_PAD PAD_SR_IO12 ++#define GPIO34_OEN 0x103C58, BIT5 ++#define GPIO34_OUT 0x103C58, BIT4 ++#define GPIO34_IN 0x103C58, BIT0 ++ ++#define GPIO35_PAD PAD_SR_IO13 ++#define GPIO35_OEN 0x103C5A, BIT5 ++#define GPIO35_OUT 0x103C5A, BIT4 ++#define GPIO35_IN 0x103C5A, BIT0 ++ ++#define GPIO36_PAD PAD_SR_IO14 ++#define GPIO36_OEN 0x103C5C, BIT5 ++#define GPIO36_OUT 0x103C5C, BIT4 ++#define GPIO36_IN 0x103C5C, BIT0 ++ ++#define GPIO37_PAD PAD_SR_IO15 ++#define GPIO37_OEN 0x103C5E, BIT5 ++#define GPIO37_OUT 0x103C5E, BIT4 ++#define GPIO37_IN 0x103C5E, BIT0 ++ ++#define GPIO38_PAD PAD_SR_IO16 ++#define GPIO38_OEN 0x103C60, BIT5 ++#define GPIO38_OUT 0x103C60, BIT4 ++#define GPIO38_IN 0x103C60, BIT0 ++ ++#define GPIO39_PAD PAD_SR_IO17 ++#define GPIO39_OEN 0x103C62, BIT5 ++#define GPIO39_OUT 0x103C62, BIT4 ++#define GPIO39_IN 0x103C62, BIT0 ++ ++#define GPIO40_PAD PAD_UART0_RX ++#define GPIO40_OEN 0x103C30, BIT5 ++#define GPIO40_OUT 0x103C30, BIT4 ++#define GPIO40_IN 0x103C30, BIT0 ++ ++#define GPIO41_PAD PAD_UART0_TX ++#define GPIO41_OEN 0x103C32, BIT5 ++#define GPIO41_OUT 0x103C32, BIT4 ++#define GPIO41_IN 0x103C32, BIT0 ++ ++#define GPIO42_PAD PAD_UART1_RX ++#define GPIO42_OEN 0x103C34, BIT5 ++#define GPIO42_OUT 0x103C34, BIT4 ++#define GPIO42_IN 0x103C34, BIT0 ++ ++#define GPIO43_PAD PAD_UART1_TX ++#define GPIO43_OEN 0x103C36, BIT5 ++#define GPIO43_OUT 0x103C36, BIT4 ++#define GPIO43_IN 0x103C36, BIT0 ++ ++#define GPIO44_PAD PAD_SPI0_CZ ++#define GPIO44_OEN 0x103CE0, BIT5 ++#define GPIO44_OUT 0x103CE0, BIT4 ++#define GPIO44_IN 0x103CE0, BIT0 ++ ++#define GPIO45_PAD PAD_SPI0_CK ++#define GPIO45_OEN 0x103CE2, BIT5 ++#define GPIO45_OUT 0x103CE2, BIT4 ++#define GPIO45_IN 0x103CE2, BIT0 ++ ++#define GPIO46_PAD PAD_SPI0_DI ++#define GPIO46_OEN 0x103CE4, BIT5 ++#define GPIO46_OUT 0x103CE4, BIT4 ++#define GPIO46_IN 0x103CE4, BIT0 ++ ++#define GPIO47_PAD PAD_SPI0_DO ++#define GPIO47_OEN 0x103CE6, BIT5 ++#define GPIO47_OUT 0x103CE6, BIT4 ++#define GPIO47_IN 0x103CE6, BIT0 ++ ++#define GPIO48_PAD PAD_SPI1_CZ ++#define GPIO48_OEN 0x103CE8, BIT5 ++#define GPIO48_OUT 0x103CE8, BIT4 ++#define GPIO48_IN 0x103CE8, BIT0 ++ ++#define GPIO49_PAD PAD_SPI1_CK ++#define GPIO49_OEN 0x103CEA, BIT5 ++#define GPIO49_OUT 0x103CEA, BIT4 ++#define GPIO49_IN 0x103CEA, BIT0 ++ ++#define GPIO50_PAD PAD_SPI1_DI ++#define GPIO50_OEN 0x103CEC, BIT5 ++#define GPIO50_OUT 0x103CEC, BIT4 ++#define GPIO50_IN 0x103CEC, BIT0 ++ ++#define GPIO51_PAD PAD_SPI1_DO ++#define GPIO51_OEN 0x103CEE, BIT5 ++#define GPIO51_OUT 0x103CEE, BIT4 ++#define GPIO51_IN 0x103CEE, BIT0 ++ ++#define GPIO52_PAD PAD_PWM0 ++#define GPIO52_OEN 0x103C20, BIT5 ++#define GPIO52_OUT 0x103C20, BIT4 ++#define GPIO52_IN 0x103C20, BIT0 ++ ++#define GPIO53_PAD PAD_PWM1 ++#define GPIO53_OEN 0x103C22, BIT5 ++#define GPIO53_OUT 0x103C22, BIT4 ++#define GPIO53_IN 0x103C22, BIT0 ++ ++#define GPIO54_PAD PAD_SD_CLK ++#define GPIO54_OEN 0x103CA0, BIT5 ++#define GPIO54_OUT 0x103CA0, BIT4 ++#define GPIO54_IN 0x103CA0, BIT0 ++ ++#define GPIO55_PAD PAD_SD_CMD ++#define GPIO55_OEN 0x103CA2, BIT5 ++#define GPIO55_OUT 0x103CA2, BIT4 ++#define GPIO55_IN 0x103CA2, BIT0 ++ ++#define GPIO56_PAD PAD_SD_D0 ++#define GPIO56_OEN 0x103CA4, BIT5 ++#define GPIO56_OUT 0x103CA4, BIT4 ++#define GPIO56_IN 0x103CA4, BIT0 ++ ++#define GPIO57_PAD PAD_SD_D1 ++#define GPIO57_OEN 0x103CA6, BIT5 ++#define GPIO57_OUT 0x103CA6, BIT4 ++#define GPIO57_IN 0x103CA6, BIT0 ++ ++#define GPIO58_PAD PAD_SD_D2 ++#define GPIO58_OEN 0x103CA8, BIT5 ++#define GPIO58_OUT 0x103CA8, BIT4 ++#define GPIO58_IN 0x103CA8, BIT0 ++ ++#define GPIO59_PAD PAD_SD_D3 ++#define GPIO59_OEN 0x103CAA, BIT5 ++#define GPIO59_OUT 0x103CAA, BIT4 ++#define GPIO59_IN 0x103CAA, BIT0 ++ ++// PM ++#define GPIO60_PAD PAD_PM_SD_CDZ ++#define GPIO60_OEN 0xF8E, BIT0 ++#define GPIO60_OUT 0xF8E, BIT1 ++#define GPIO60_IN 0xF8E, BIT2 ++ ++#define GPIO61_PAD PAD_PM_IRIN ++#define GPIO61_OEN 0xF28, BIT0 ++#define GPIO61_OUT 0xF28, BIT1 ++#define GPIO61_IN 0xF28, BIT2 ++ ++#define GPIO62_PAD PAD_PM_GPIO0 ++#define GPIO62_OEN 0xF00, BIT0 ++#define GPIO62_OUT 0xF00, BIT1 ++#define GPIO62_IN 0xF00, BIT2 ++ ++#define GPIO63_PAD PAD_PM_GPIO1 ++#define GPIO63_OEN 0xF02, BIT0 ++#define GPIO63_OUT 0xF02, BIT1 ++#define GPIO63_IN 0xF02, BIT2 ++ ++#define GPIO64_PAD PAD_PM_GPIO2 ++#define GPIO64_OEN 0xF04, BIT0 ++#define GPIO64_OUT 0xF04, BIT1 ++#define GPIO64_IN 0xF04, BIT2 ++ ++#define GPIO65_PAD PAD_PM_GPIO3 ++#define GPIO65_OEN 0xF06, BIT0 ++#define GPIO65_OUT 0xF06, BIT1 ++#define GPIO65_IN 0xF06, BIT2 ++ ++#define GPIO66_PAD PAD_PM_GPIO4 ++#define GPIO66_OEN 0xF08, BIT0 ++#define GPIO66_OUT 0xF08, BIT1 ++#define GPIO66_IN 0xF08, BIT2 ++ ++#define GPIO67_PAD PAD_PM_GPIO7 ++#define GPIO67_OEN 0xF0E, BIT0 ++#define GPIO67_OUT 0xF0E, BIT1 ++#define GPIO67_IN 0xF0E, BIT2 ++ ++#define GPIO68_PAD PAD_PM_GPIO8 ++#define GPIO68_OEN 0xF10, BIT0 ++#define GPIO68_OUT 0xF10, BIT1 ++#define GPIO68_IN 0xF10, BIT2 ++ ++#define GPIO69_PAD PAD_PM_GPIO9 ++#define GPIO69_OEN 0xF12, BIT0 ++#define GPIO69_OUT 0xF12, BIT1 ++#define GPIO69_IN 0xF12, BIT2 ++ ++#define GPIO70_PAD PAD_PM_SPI_CZ ++#define GPIO70_OEN 0xF30, BIT0 ++#define GPIO70_OUT 0xF30, BIT1 ++#define GPIO70_IN 0xF30, BIT2 ++ ++#define GPIO71_PAD PAD_PM_SPI_CK ++#define GPIO71_OEN 0xF32, BIT0 ++#define GPIO71_OUT 0xF32, BIT1 ++#define GPIO71_IN 0xF32, BIT2 ++ ++#define GPIO72_PAD PAD_PM_SPI_DI ++#define GPIO72_OEN 0xF34, BIT0 ++#define GPIO72_OUT 0xF34, BIT1 ++#define GPIO72_IN 0xF34, BIT2 ++ ++#define GPIO73_PAD PAD_PM_SPI_DO ++#define GPIO73_OEN 0xF36, BIT0 ++#define GPIO73_OUT 0xF36, BIT1 ++#define GPIO73_IN 0xF36, BIT2 ++ ++#define GPIO74_PAD PAD_PM_SPI_WPZ ++#define GPIO74_OEN 0xF88, BIT0 ++#define GPIO74_OUT 0xF88, BIT1 ++#define GPIO74_IN 0xF88, BIT2 ++ ++#define GPIO75_PAD PAD_PM_SPI_HLD ++#define GPIO75_OEN 0xF8A, BIT0 ++#define GPIO75_OUT 0xF8A, BIT1 ++#define GPIO75_IN 0xF8A, BIT2 ++ ++#define GPIO76_PAD PAD_PM_LED0 ++#define GPIO76_OEN 0xF94, BIT0 ++#define GPIO76_OUT 0xF94, BIT1 ++#define GPIO76_IN 0xF94, BIT2 ++ ++#define GPIO77_PAD PAD_PM_LED1 ++#define GPIO77_OEN 0xF96, BIT0 ++#define GPIO77_OUT 0xF96, BIT1 ++#define GPIO77_IN 0xF96, BIT2 ++ ++// SAR ++#define GPIO78_PAD PAD_SAR_GPIO0 ++#define GPIO78_OEN 0x1423, BIT0 ++#define GPIO78_OUT 0x1424, BIT0 ++#define GPIO78_IN 0x1425, BIT0 ++ ++#define GPIO79_PAD PAD_SAR_GPIO1 ++#define GPIO79_OEN 0x1423, BIT1 ++#define GPIO79_OUT 0x1424, BIT1 ++#define GPIO79_IN 0x1425, BIT1 ++ ++#define GPIO80_PAD PAD_SAR_GPIO2 ++#define GPIO80_OEN 0x1423, BIT2 ++#define GPIO80_OUT 0x1424, BIT2 ++#define GPIO80_IN 0x1425, BIT2 ++ ++#define GPIO81_PAD PAD_SAR_GPIO3 ++#define GPIO81_OEN 0x1423, BIT3 ++#define GPIO81_OUT 0x1424, BIT3 ++#define GPIO81_IN 0x1425, BIT3 ++ ++// ALBANY ++#define GPIO82_PAD PAD_ETH_RN ++#define GPIO82_OEN 0x33E2, BIT4 ++#define GPIO82_OUT 0x33E4, BIT0 ++#define GPIO82_IN 0x33E4, BIT4 ++ ++#define GPIO83_PAD PAD_ETH_RP ++#define GPIO83_OEN 0x33E2, BIT5 ++#define GPIO83_OUT 0x33E4, BIT1 ++#define GPIO83_IN 0x33E4, BIT5 ++ ++#define GPIO84_PAD PAD_ETH_TN ++#define GPIO84_OEN 0x33E2, BIT6 ++#define GPIO84_OUT 0x33E4, BIT2 ++#define GPIO84_IN 0x33E4, BIT6 ++ ++#define GPIO85_PAD PAD_ETH_TP ++#define GPIO85_OEN 0x33E2, BIT7 ++#define GPIO85_OUT 0x33E4, BIT3 ++#define GPIO85_IN 0x33E4, BIT7 ++ ++// UTMI ++#define GPIO86_PAD PAD_USB_DM ++#define GPIO86_OEN 0x14210a, BIT4 ++#define GPIO86_OUT 0x14210a, BIT2 ++#define GPIO86_IN 0x142131, BIT5 ++ ++#define GPIO87_PAD PAD_USB_DP ++#define GPIO87_OEN 0x14210a, BIT5 ++#define GPIO87_OUT 0x14210a, BIT3 ++#define GPIO87_IN 0x142131, BIT4 ++ ++//SDIO ++#define GPIO88_PAD PAD_SD1_IO0 ++#define GPIO88_OEN 0x103C80, BIT5 ++#define GPIO88_OUT 0x103C80, BIT4 ++#define GPIO88_IN 0x103C80, BIT0 ++ ++#define GPIO89_PAD PAD_SD1_IO1 ++#define GPIO89_OEN 0x103C82, BIT5 ++#define GPIO89_OUT 0x103C82, BIT4 ++#define GPIO89_IN 0x103C82, BIT0 ++ ++#define GPIO90_PAD PAD_SD1_IO2 ++#define GPIO90_OEN 0x103C84, BIT5 ++#define GPIO90_OUT 0x103C84, BIT4 ++#define GPIO90_IN 0x103C84, BIT0 ++ ++#define GPIO91_PAD PAD_SD1_IO3 ++#define GPIO91_OEN 0x103C86, BIT5 ++#define GPIO91_OUT 0x103C86, BIT4 ++#define GPIO91_IN 0x103C86, BIT0 ++ ++#define GPIO92_PAD PAD_SD1_IO4 ++#define GPIO92_OEN 0x103C88, BIT5 ++#define GPIO92_OUT 0x103C88, BIT4 ++#define GPIO92_IN 0x103C88, BIT0 ++ ++#define GPIO93_PAD PAD_SD1_IO5 ++#define GPIO93_OEN 0x103C8A, BIT5 ++#define GPIO93_OUT 0x103C8A, BIT4 ++#define GPIO93_IN 0x103C8A, BIT0 ++ ++#define GPIO94_PAD PAD_SD1_IO6 ++#define GPIO94_OEN 0x103C8C, BIT5 ++#define GPIO94_OUT 0x103C8C, BIT4 ++#define GPIO94_IN 0x103C8C, BIT0 ++ ++#define GPIO95_PAD PAD_SD1_IO7 ++#define GPIO95_OEN 0x103C8E, BIT5 ++#define GPIO95_OUT 0x103C8E, BIT4 ++#define GPIO95_IN 0x103C8E, BIT0 ++ ++#define GPIO96_PAD PAD_SD1_IO8 ++#define GPIO96_OEN 0x103C90, BIT5 ++#define GPIO96_OUT 0x103C90, BIT4 ++#define GPIO96_IN 0x103C90, BIT0 ++ ++U32 gChipBaseAddr = 0xFD203C00; ++U32 gPmSleepBaseAddr = 0xFD001C00; ++U32 gSarBaseAddr = 0xFD002800; ++U32 gRIUBaseAddr = 0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++#define REG_ALL_PAD_IN 0xA1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++static int _pmsleep_to_irq_table[] = { ++ INT_PMSLEEP_SD_CDZ, ++ INT_PMSLEEP_IRIN, ++ INT_PMSLEEP_GPIO_0, ++ INT_PMSLEEP_GPIO_1, ++ INT_PMSLEEP_GPIO_2, ++ INT_PMSLEEP_GPIO_3, ++ INT_PMSLEEP_GPIO_4, ++ INT_PMSLEEP_GPIO_7, ++ INT_PMSLEEP_GPIO_8, ++ INT_PMSLEEP_GPIO_9, ++ INT_PMSLEEP_SPI_CZ, ++ INT_PMSLEEP_SPI_CK, ++ INT_PMSLEEP_SPI_DI, ++ INT_PMSLEEP_SPI_DO, ++ INT_PMSLEEP_SPI_WPZ, ++ INT_PMSLEEP_SPI_HLD, ++ INT_PMSLEEP_LED0, ++ INT_PMSLEEP_LED1, ++}; ++ ++static int _gpi_to_irq_table[] = { ++ INT_GPI_FIQ_PAD_GPIO0, ++ INT_GPI_FIQ_PAD_GPIO1, ++ INT_GPI_FIQ_PAD_GPIO2, ++ INT_GPI_FIQ_PAD_GPIO3, ++ INT_GPI_FIQ_PAD_GPIO4, ++ INT_GPI_FIQ_PAD_GPIO5, ++ INT_GPI_FIQ_PAD_GPIO6, ++ INT_GPI_FIQ_PAD_GPIO7, ++ INT_GPI_FIQ_PAD_GPIO8, ++ INT_GPI_FIQ_PAD_GPIO9, ++ INT_GPI_FIQ_PAD_GPIO12, ++ INT_GPI_FIQ_PAD_GPIO13, ++ INT_GPI_FIQ_PAD_GPIO14, ++ INT_GPI_FIQ_PAD_GPIO15, ++ INT_GPI_FIQ_PAD_FUART_RX, ++ INT_GPI_FIQ_PAD_FUART_TX, ++ INT_GPI_FIQ_PAD_FUART_CTS, ++ INT_GPI_FIQ_PAD_FUART_RTS, ++ INT_GPI_FIQ_PAD_I2C0_SCL, ++ INT_GPI_FIQ_PAD_I2C0_SDA, ++ INT_GPI_FIQ_PAD_I2C1_SCL, ++ INT_GPI_FIQ_PAD_I2C1_SDA, ++ INT_GPI_FIQ_PAD_SR_IO00, ++ INT_GPI_FIQ_PAD_SR_IO01, ++ INT_GPI_FIQ_PAD_SR_IO02, ++ INT_GPI_FIQ_PAD_SR_IO03, ++ INT_GPI_FIQ_PAD_SR_IO04, ++ INT_GPI_FIQ_PAD_SR_IO05, ++ INT_GPI_FIQ_PAD_SR_IO06, ++ INT_GPI_FIQ_PAD_SR_IO07, ++ INT_GPI_FIQ_PAD_SR_IO08, ++ INT_GPI_FIQ_PAD_SR_IO09, ++ INT_GPI_FIQ_PAD_SR_IO10, ++ INT_GPI_FIQ_PAD_SR_IO11, ++ INT_GPI_FIQ_PAD_SR_IO12, ++ INT_GPI_FIQ_PAD_SR_IO13, ++ INT_GPI_FIQ_PAD_SR_IO14, ++ INT_GPI_FIQ_PAD_SR_IO15, ++ INT_GPI_FIQ_PAD_SR_IO16, ++ INT_GPI_FIQ_PAD_SR_IO17, ++ INT_GPI_FIQ_PAD_UART0_RX, ++ INT_GPI_FIQ_PAD_UART0_TX, ++ INT_GPI_FIQ_PAD_UART1_RX, ++ INT_GPI_FIQ_PAD_UART1_TX, ++ INT_GPI_FIQ_PAD_SPI0_CZ, ++ INT_GPI_FIQ_PAD_SPI0_CK, ++ INT_GPI_FIQ_PAD_SPI0_DI, ++ INT_GPI_FIQ_PAD_SPI0_DO, ++ INT_GPI_FIQ_PAD_SPI1_CZ, ++ INT_GPI_FIQ_PAD_SPI1_CK, ++ INT_GPI_FIQ_PAD_SPI1_DI, ++ INT_GPI_FIQ_PAD_SPI1_DO, ++ INT_GPI_FIQ_PAD_PWM0, ++ INT_GPI_FIQ_PAD_PWM1, ++ INT_GPI_FIQ_PAD_SD_CLK, ++ INT_GPI_FIQ_PAD_SD_CMD, ++ INT_GPI_FIQ_PAD_SD_D0, ++ INT_GPI_FIQ_PAD_SD_D1, ++ INT_GPI_FIQ_PAD_SD_D2, ++ INT_GPI_FIQ_PAD_SD_D3, ++ -1, // [60] PAD_PM_SD_CDZ ++ -1, // [61] PAD_PM_IRIN ++ -1, // [62] PAD_PM_GPIO0 ++ -1, // [63] PAD_PM_GPIO1 ++ -1, // [64] PAD_PM_GPIO2 ++ -1, // [65] PAD_PM_GPIO3 ++ -1, // [66] PAD_PM_GPIO4 ++ -1, // [67] PAD_PM_GPIO7 ++ -1, // [68] PAD_PM_GPIO8 ++ -1, // [69] PAD_PM_GPIO9 ++ -1, // [70] PAD_PM_SPI_CZ ++ -1, // [71] PAD_PM_SPI_CK ++ -1, // [72] PAD_PM_SPI_DI ++ -1, // [73] PAD_PM_SPI_DO ++ -1, // [74] PAD_PM_SPI_WPZ ++ -1, // [75] PAD_PM_SPI_HLD ++ -1, // [76] PAD_PM_LED0 ++ -1, // [77] PAD_PM_LED1 ++ -1, // [78] INT_GPI_FIQ_PAD_SAR_GPIO0, ++ -1, // [79] INT_GPI_FIQ_PAD_SAR_GPIO1, ++ -1, // [80] INT_GPI_FIQ_PAD_SAR_GPIO2, ++ -1, // [81] INT_GPI_FIQ_PAD_SAR_GPIO3, ++ -1, // [82] INT_GPI_FIQ_PAD_ETH_RN, ++ -1, // [83] INT_GPI_FIQ_PAD_ETH_RP, ++ -1, // [84] INT_GPI_FIQ_PAD_ETH_TN, ++ -1, // [85] INT_GPI_FIQ_PAD_ETH_TP, ++ -1, // [86] INT_GPI_FIQ_PAD_USB_DM, ++ -1, // [87] INT_GPI_FIQ_PAD_USB_DP, ++ INT_GPI_FIQ_PAD_SD1_IO0, ++ INT_GPI_FIQ_PAD_SD1_IO1, ++ INT_GPI_FIQ_PAD_SD1_IO2, ++ INT_GPI_FIQ_PAD_SD1_IO3, ++ INT_GPI_FIQ_PAD_SD1_IO4, ++ INT_GPI_FIQ_PAD_SD1_IO5, ++ INT_GPI_FIQ_PAD_SD1_IO6, ++ INT_GPI_FIQ_PAD_SD1_IO7, ++ INT_GPI_FIQ_PAD_SD1_IO8, ++}; ++ ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), __GPIO(5), __GPIO(6), __GPIO(7), ++ __GPIO(8), __GPIO(9), __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), __GPIO(15), ++ __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), ++ __GPIO(24), __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), __GPIO(30), __GPIO(31), ++ __GPIO(32), __GPIO(33), __GPIO(34), __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), __GPIO(45), __GPIO(46), __GPIO(47), ++ __GPIO(48), __GPIO(49), __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), __GPIO(55), ++ __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), ++ __GPIO(64), __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), __GPIO(70), __GPIO(71), ++ __GPIO(72), __GPIO(73), __GPIO(74), __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), __GPIO(85), __GPIO(86), __GPIO(87), ++ __GPIO(88), __GPIO(89), __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), __GPIO(95), ++ __GPIO(96), ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GPIO_Init(void) ++{ ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ HalPadSetVal(u8IndexGPIO, PINMUX_FOR_GPIO_MODE); ++} ++ ++int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ return HalPadSetMode(u32PadMode); ++} ++ ++int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode) ++{ ++ return HalPadSetVal((U32)u8IndexGPIO, u32PadMode); ++} ++ ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ // TBD ++} ++ ++static int PMSLEEP_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if ((u8IndexGPIO < PAD_PM_SD_CDZ) || (u8IndexGPIO > PAD_PM_LED1)) ++ return -1; ++ else ++ { ++ return _pmsleep_to_irq_table[u8IndexGPIO-PAD_PM_SD_CDZ]; ++ } ++} ++ ++static int GPI_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if (u8IndexGPIO >= GPIO_NR) ++ return -1; ++ else ++ return _gpi_to_irq_table[u8IndexGPIO]; ++} ++ ++//MHal_GPIO_To_Irq return any virq ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ struct device_node *intr_node; ++ struct irq_domain *intr_domain; ++ struct irq_fwspec fwspec; ++ int hwirq, virq = -1; ++ ++ if ((hwirq = PMSLEEP_GPIO_To_Irq(u8IndexGPIO)) >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,pm-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else if ((hwirq = GPI_GPIO_To_Irq(u8IndexGPIO)) >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,gpi-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else if ((u8IndexGPIO >= PAD_SAR_GPIO0 && u8IndexGPIO <= PAD_SAR_GPIO3)) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,main-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 3; ++ fwspec.param[0] = GIC_SPI; ++ fwspec.param[1] = u8IndexGPIO - PAD_SAR_GPIO0 + INT_FIQ_SAR_GPIO_0; ++ fwspec.param[2] = IRQ_TYPE_NONE; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ ++ return virq; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse) ++{ ++ // TBD ++} +diff --git a/drivers/sstar/gpio/infinity6/mhal_gpio.h b/drivers/sstar/gpio/infinity6/mhal_gpio.h +new file mode 100755 +index 000000000000..b95fc6f2fe7d +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6/mhal_gpio.h +@@ -0,0 +1,45 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_GPIO_H_ ++#define _MHAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode); ++extern int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _MHAL_GPIO_H_ +diff --git a/drivers/sstar/gpio/infinity6/mhal_pinmux.c b/drivers/sstar/gpio/infinity6/mhal_pinmux.c +new file mode 100755 +index 000000000000..2b786a54c144 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6/mhal_pinmux.c +@@ -0,0 +1,1357 @@ ++/* ++* mhal_pinmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "mhal_gpio.h" ++#include "padmux.h" ++#include "gpio.h" ++ ++//============================================================================== ++// ++// MACRO DEFINE ++// ++//============================================================================== ++ ++#define BASE_RIU_PA 0xFD000000 ++#define PMSLEEP_BANK 0x000E00 ++#define SAR_BANK 0x001400 ++#define ALBANY1_BANK 0x003200 ++#define ALBANY2_BANK 0x003300 ++#define CHIPTOP_BANK 0x101E00 ++#define UTMI0_BANK 0x142100 ++ ++#define _GPIO_W_WORD(addr,val) {(*(volatile u16*)(addr)) = (u16)(val);} ++#define _GPIO_W_WORD_MASK(addr,val,mask) {(*(volatile u16*)(addr)) = ((*(volatile u16*)(addr)) & ~(mask)) | ((u16)(val) & (mask));} ++#define _GPIO_R_BYTE(addr) (*(volatile u8*)(addr)) ++#define _GPIO_R_WORD_MASK(addr,mask) ((*(volatile u16*)(addr)) & (mask)) ++ ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define _RIUA_8BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + (((offset) & ~1)<<1) + ((offset) & 1) ++#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) ++ ++/* Non PM Pad : CHIPTOP_BANK */ ++#define REG_PWM5_MODE 0x02 ++ #define REG_PWM5_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_PWM6_MODE 0x02 ++ #define REG_PWM6_MODE_MASK BIT5|BIT4|BIT3 ++#define REG_PWM7_MODE 0x02 ++ #define REG_PWM7_MODE_MASK BIT8|BIT7|BIT6 ++#define REG_PWM8_MODE 0x02 ++ #define REG_PWM8_MODE_MASK BIT11|BIT10|BIT9 ++#define REG_PWM9_MODE 0x02 ++ #define REG_PWM9_MODE_MASK BIT14|BIT13|BIT12 ++#define REG_FUART_MODE 0x03 ++ #define REG_FUART_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_UART0_MODE 0x03 ++ #define REG_UART0_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_UART1_MODE 0x03 ++ #define REG_UART1_MODE_MASK BIT10|BIT9|BIT8 ++#define REG_PWM10_MODE 0x04 ++ #define REG_PWM10_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_SR_MODE 0x06 ++ #define REG_SR_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_SR_I2C_MODE 0x06 ++ #define REG_SR_I2C_MODE_MASK BIT5|BIT4 ++#define REG_SR_HVSYNC_MODE 0x06 ++ #define REG_SR_HVSYNC_MODE_MASK BIT6 ++#define REG_SR_MCLK_MODE 0x06 ++ #define REG_SR_MCLK_MODE_MASK BIT7 ++#define REG_SR_PCK_MODE 0x06 ++ #define REG_SR_PCK_MODE_MASK BIT8 ++#define REG_SR_PDN_MODE 0x06 ++ #define REG_SR_PDN_MODE_MASK BIT10|BIT9 ++#define REG_SR_RST_MODE 0x06 ++ #define REG_SR_RST_MODE_MASK BIT12|BIT11 ++#define REG_PWM0_MODE 0x07 ++ #define REG_PWM0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_PWM1_MODE 0x07 ++ #define REG_PWM1_MODE_MASK BIT5|BIT4|BIT3 ++#define REG_PWM2_MODE 0x07 ++ #define REG_PWM2_MODE_MASK BIT8|BIT7|BIT6 ++#define REG_PWM3_MODE 0x07 ++ #define REG_PWM3_MODE_MASK BIT11|BIT10|BIT9 ++#define REG_PWM4_MODE 0x07 ++ #define REG_PWM4_MODE_MASK BIT14|BIT13|BIT12 ++#define REG_NAND_MODE 0x08 ++ #define REG_NAND_MODE_MASK BIT0 ++#define REG_SD_MODE 0x08 ++ #define REG_SD_MODE_MASK BIT3|BIT2 ++#define REG_SDIO_MODE 0x08 ++ #define REG_SDIO_MODE_MASK BIT8 ++#define REG_I2C0_MODE 0x09 ++ #define REG_I2C0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_I2C1_MODE 0x09 ++ #define REG_I2C1_MODE_MASK BIT5|BIT4 ++#define REG_SPI0_MODE 0x0c ++ #define REG_SPI0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_SPI1_MODE 0x0c ++ #define REG_SPI1_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_EJ_MODE 0x0f ++ #define REG_EJ_MODE_MASK BIT1|BIT0 ++#define REG_ETH_MODE 0x0f ++ #define REG_ETH_MODE_MASK BIT2 ++#define REG_CCIR_MODE 0x0f ++ #define REG_CCIR_MODE_MASK BIT5|BIT4 ++#define REG_TTL_MODE 0x0f ++ #define REG_TTL_MODE_MASK BIT7|BIT6 ++#define REG_DMIC_MODE 0x0f ++ #define REG_DMIC_MODE_MASK BIT9|BIT8 ++#define REG_I2S_MODE 0x0f ++ #define REG_I2S_MODE_MASK BIT11|BIT10 ++#define REG_TEST_IN_MODE 0x12 ++ #define REG_TEST_IN_MODE_MASK BIT1|BIT0 ++#define REG_TEST_OUT_MODE 0x12 ++ #define REG_TEST_OUT_MODE_MASK BIT5|BIT4 ++#define REG_EMMC_MODE 0x13 ++ #define REG_EMMC_MODE_MASK BIT0 ++#define REG_EMMC_RSTN_EN 0x13 ++ #define REG_EMMC_RSTN_EN_MASK BIT1 ++#define REG_MIPI_PAD_IN 0x33 ++ #define REG_MIPI_PAD_IN_MASK BIT1|BIT0 ++#define REG_ALLPAD_IN 0x50 ++ #define REG_ALLPAD_IN_MASK BIT15 ++ ++/* PM Sleep : PMSLEEP_BANK */ ++#define REG_PM_GPIO_PM_LOCK 0x12 ++ #define REG_PM_GPIO_PM_LOCK_MASK 0xFFFF ++#define REG_PM_GPIO_PM4_INV 0x1c ++ #define REG_PM_GPIO_PM4_INV_MASK BIT1 ++#define REG_PM_LINK_WKINT2GPIO4 0x1c ++ #define REG_PM_LINK_WKINT2GPIO4_MASK BIT3 ++#define REG_PM_IR_IS_GPIO 0x1c ++ #define REG_PM_IR_IS_GPIO_MASK BIT4 ++#define REG_PM_PWM0_MODE 0x28 ++ #define REG_PM_PWM0_MODE_MASK BIT1|BIT0 ++#define REG_PM_PWM1_MODE 0x28 ++ #define REG_PM_PWM1_MODE_MASK BIT3|BIT2 ++#define REG_PM_PWM2_MODE 0x28 ++ #define REG_PM_PWM2_MODE_MASK BIT7|BIT6 ++#define REG_PM_PWM3_MODE 0x28 ++ #define REG_PM_PWM3_MODE_MASK BIT9|BIT8 ++#define REG_PM_PWM4_MODE 0x27 ++ #define REG_PM_PWM4_MODE_MASK BIT0 ++#define REG_PM_PWM5_MODE 0x27 ++ #define REG_PM_PWM5_MODE_MASK BIT1 ++#define REG_PM_PWM8_MODE 0x27 ++ #define REG_PM_PWM8_MODE_MASK BIT2 ++#define REG_PM_PWM9_MODE 0x27 ++ #define REG_PM_PWM9_MODE_MASK BIT3 ++#define REG_PM_PWM10_MODE 0x27 ++ #define REG_PM_PWM10_MODE_MASK BIT4 ++#define REG_PM_UART1_MODE 0x27 ++ #define REG_PM_UART1_MODE_MASK BIT8 ++#define REG_PM_LED_MODE 0x28 ++ #define REG_PM_LED_MODE_MASK BIT5|BIT4 ++ ++#define REG_PM_VID_MODE 0x28 ++ #define REG_PM_VID_MODE_MASK BIT13|BIT12 ++#define REG_PM_SD_CDZ_MODE 0x28 ++ #define REG_PM_SD_CDZ_MODE_MASK BIT14 ++#define REG_PM_SPI_IS_GPIO 0x35 ++ #define REG_PM_SPI_IS_GPIO_MASK BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0 ++ #define REG_PM_SPI_GPIO_MASK BIT0 ++ #define REG_PM_SPICSZ1_GPIO_MASK BIT2 ++ #define REG_PM_SPICSZ2_GPIO_MASK BIT3 ++ #define REG_PM_SPIWPN_GPIO_MASK BIT4 ++ #define REG_PM_SPIHOLDN_MODE_MASK BIT6 | BIT7 ++#define REG_PM_SPICSZ1_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPICSZ2_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPI_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIWPN_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIHOLDN_MODE REG_PM_SPI_IS_GPIO ++ ++#define REG_PM_UART_IS_GPIO 0x35 ++ #define REG_PM_UART_IS_GPIO_MASK BIT11|BIT10|BIT9|BIT8 ++ ++/* SAR : SAR_BANK, R/W 8-bits */ ++#define REG_SAR_AISEL_8BIT 0x11*2 ++ #define REG_SAR_CH0_AISEL BIT0 ++ #define REG_SAR_CH1_AISEL BIT1 ++ #define REG_SAR_CH2_AISEL BIT2 ++ #define REG_SAR_CH3_AISEL BIT3 ++ ++/* EMAC : ALBANY1_BANK */ ++#define REG_ATOP_RX_INOFF 0x69 ++ #define REG_ATOP_RX_INOFF_MASK BIT15|BIT14 ++ ++/* EMAC : ALBANY2_BANK */ ++#define REG_ETH_GPIO_EN 0x71 ++ #define REG_ETH_GPIO_EN_MASK BIT3|BIT2|BIT1|BIT0 ++ ++/* UTMI0 : UTMI0_BANK */ ++#define REG_UTMI0_FL_XVR_PDN 0x0 ++ #define REG_UTMI0_FL_XVR_PDN_MASK BIT12 ++#define REG_UTMI0_REG_PDN 0x0 ++ #define REG_UTMI0_REG_PDN_MASK BIT15 // 1: power doen 0: enable ++#define REG_UTMI0_CLK_EXTRA0_EN 0x4 ++ #define REG_UTMI0_CLK_EXTRA0_EN_MASK BIT7 // 1: power down 0: enable ++#define REG_UTMI0_GPIO_EN 0x1f ++ #define REG_UTMI0_GPIO_EN_MASK BIT14 ++ ++//-------------------- configuration ----------------- ++#define ENABLE_CHECK_ALL_PAD_CONFLICT 0 ++ ++//============================================================================== ++// ++// STRUCTURE ++// ++//============================================================================== ++ ++typedef struct stPadMux ++{ ++ U16 padID; ++ U32 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PadMuxInfo; ++ ++typedef struct stPadMode ++{ ++ U8 u8PadName[16]; ++ U32 u32ModeRIU; ++ U32 u32ModeMask; ++} ST_PadModeInfo; ++ ++//============================================================================== ++// ++// VARIABLES ++// ++//============================================================================== ++ ++const ST_PadMuxInfo m_stPadMuxTbl[] = ++{ ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2, PINMUX_FOR_PWM0_MODE_4}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT9, PINMUX_FOR_PWM8_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5, PINMUX_FOR_PWM1_MODE_4}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT12, PINMUX_FOR_PWM9_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8, PINMUX_FOR_PWM2_MODE_4}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11, PINMUX_FOR_PWM3_MODE_4}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT0, PINMUX_FOR_PWM10_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM4_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM5_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM6_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM7_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO8, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT10, PINMUX_FOR_PWM8_MODE_2}, ++ {PAD_GPIO8, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO9, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO12, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO13, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO14, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PWM0_MODE_2}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PWM2_MODE_1}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM9_MODE_3}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO15, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4, PINMUX_FOR_PWM1_MODE_2}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PWM3_MODE_1}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM10_MODE_3}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM0_MODE_3}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM1_MODE_3}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PWM2_MODE_2}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10, PINMUX_FOR_PWM3_MODE_2}, ++ ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_PDN_MODE, REG_SR_PDN_MODE_MASK, BIT9, PINMUX_FOR_SR_PDN_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_RST_MODE, REG_SR_RST_MODE_MASK, BIT11, PINMUX_FOR_SR_RST_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT11, PINMUX_FOR_PWM8_MODE_4}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_HVSYNC_MODE, REG_SR_HVSYNC_MODE_MASK, BIT6, PINMUX_FOR_SR_HVSYNC_MODE}, ++ ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT14, PINMUX_FOR_PWM9_MODE_4}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_PCK_MODE, REG_SR_PCK_MODE_MASK, BIT8, PINMUX_FOR_SR_PCK_MODE}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT2, PINMUX_FOR_PWM10_MODE_4}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_HVSYNC_MODE, REG_SR_HVSYNC_MODE_MASK, BIT6, PINMUX_FOR_SR_HVSYNC_MODE}, ++ ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MCLK_MODE, REG_SR_MCLK_MODE_MASK, BIT7, PINMUX_FOR_SR_MCLK_MODE}, ++ ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, ++ ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, ++ ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT13, PINMUX_FOR_PWM4_MODE_2}, ++ ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT1, PINMUX_FOR_PWM5_MODE_2}, ++ ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT4, PINMUX_FOR_PWM6_MODE_2}, ++ ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT7, PINMUX_FOR_PWM7_MODE_2}, ++ ++ {PAD_SPI1_CZ, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_CZ, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SPI1_CK, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_CK, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SPI1_DI, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_DI, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SPI1_DO, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_DO, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PWM0_MODE_1}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT13, PINMUX_FOR_PWM9_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_SR_PDN_MODE, REG_SR_PDN_MODE_MASK, BIT10, PINMUX_FOR_SR_PDN_MODE_2}, ++ ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT3, PINMUX_FOR_PWM1_MODE_1}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT1, PINMUX_FOR_PWM10_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_SR_RST_MODE, REG_SR_RST_MODE_MASK, BIT12, PINMUX_FOR_SR_RST_MODE_2}, ++ ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SD_CDZ, PMSLEEP_BANK, REG_PM_SD_CDZ_MODE, REG_PM_SD_CDZ_MODE_MASK, BIT14, PINMUX_FOR_PM_SD_CDZ_MODE}, ++ ++ {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_IRIN, PMSLEEP_BANK, REG_PM_IR_IS_GPIO, REG_PM_IR_IS_GPIO_MASK, 0, PINMUX_FOR_PM_IRIN_MODE}, ++ ++ {PAD_PM_GPIO0, PMSLEEP_BANK, REG_PM_PWM0_MODE, REG_PM_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PM_PWM0_MODE_1}, ++ {PAD_PM_GPIO0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_PM_GPIO1, PMSLEEP_BANK, REG_PM_PWM1_MODE, REG_PM_PWM1_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM1_MODE_1}, ++ {PAD_PM_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_PM_GPIO2, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PM_PWM2_MODE_1}, ++ ++ {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT8, PINMUX_FOR_PM_PWM3_MODE_1}, ++ {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, ++ {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ /* ++ {PAD_PM_GPIO4, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, ++ {PAD_PM_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ */ ++ ++ {PAD_PM_GPIO7, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PM_PWM3_MODE_2}, ++ ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_SPICSZ2_GPIO, REG_PM_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ2_MODE}, ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PM_PWM2_MODE_2}, ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_PWM8_MODE, REG_PM_PWM8_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM8_MODE}, ++ ++ {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_CZ, PMSLEEP_BANK, REG_PM_SPICSZ1_GPIO, REG_PM_SPICSZ1_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ1_MODE}, ++ ++ {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_CK, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_DI, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_DO, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_WPZ,CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_WPZ,CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_WPZ,PMSLEEP_BANK, REG_PM_SPIWPN_GPIO, REG_PM_SPIWPN_GPIO_MASK, 0, PINMUX_FOR_PM_SPIWPN_MODE}, ++ ++ {PAD_PM_SPI_HLD,PMSLEEP_BANK, REG_PM_SPIHOLDN_MODE, REG_PM_SPIHOLDN_MODE_MASK, 0, PINMUX_FOR_PM_SPIHOLDN_MODE}, ++ ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_PWM9_MODE, REG_PM_PWM9_MODE_MASK, BIT3, PINMUX_FOR_PM_PWM9_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE}, ++ ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM5_MODE, REG_PM_PWM5_MODE_MASK, BIT1, PINMUX_FOR_PM_PWM5_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM10_MODE, REG_PM_PWM10_MODE_MASK, BIT4, PINMUX_FOR_PM_PWM10_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE}, ++ ++ /* ++ {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_USB_DM, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_USB_DM, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ */ ++ ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM0_MODE_5}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM2_MODE_3}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5|BIT3, PINMUX_FOR_PWM1_MODE_5}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM3_MODE_3}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8|BIT6, PINMUX_FOR_PWM2_MODE_5}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT12, PINMUX_FOR_PWM4_MODE_1}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11|BIT9, PINMUX_FOR_PWM3_MODE_5}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT0, PINMUX_FOR_PWM5_MODE_1}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT14, PINMUX_FOR_PWM4_MODE_4}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT3, PINMUX_FOR_PWM6_MODE_1}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT2, PINMUX_FOR_PWM5_MODE_4}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT6, PINMUX_FOR_PWM7_MODE_1}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT5, PINMUX_FOR_PWM6_MODE_4}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO7, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_SD1_IO7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT8, PINMUX_FOR_PWM7_MODE_4}, ++ {PAD_SD1_IO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO8, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM8_MODE_3}, ++ {PAD_SD1_IO8, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++}; ++ ++static const ST_PadModeInfo m_stPadModeInfoTbl[] = ++{ ++ {"GPIO", 0, 0}, ++ // Non PM ++ {"EJ_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"EJ_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"ALLPAD_IN", _RIUA_16BIT(CHIPTOP_BANK,REG_ALLPAD_IN), REG_ALLPAD_IN_MASK}, ++ {"MIPI_PAD_IN_1", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, ++ {"MIPI_PAD_IN_2", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, ++ {"MIPI_PAD_IN_3", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, ++ {"TEST_IN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_OUT_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"I2C0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"SPI0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"FUART_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"UART0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"SD_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SD_MODE), REG_SD_MODE_MASK}, ++ {"SDIO_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SDIO_MODE), REG_SDIO_MODE_MASK}, ++ {"PWM0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM2_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM3_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM4_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM5_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM6_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM7_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM8_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM9_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM10_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"PWM10_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"PWM10_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"PWM10_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"SR_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MCLK_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MCLK_MODE), REG_SR_MCLK_MODE_MASK}, ++ {"SR_PDN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PDN_MODE), REG_SR_PDN_MODE_MASK}, ++ {"SR_PDN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PDN_MODE), REG_SR_PDN_MODE_MASK}, ++ {"SR_RST_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_RST_MODE), REG_SR_RST_MODE_MASK}, ++ {"SR_RST_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_RST_MODE), REG_SR_RST_MODE_MASK}, ++ {"SR_HVSYNC_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_HVSYNC_MODE), REG_SR_HVSYNC_MODE_MASK}, ++ {"SR_PCK_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PCK_MODE), REG_SR_PCK_MODE_MASK}, ++ {"ETH_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH_MODE), REG_ETH_MODE_MASK}, ++ {"I2S_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"DMIC_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"CCIR_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, ++ {"CCIR_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, ++ {"CCIR_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, ++ // PM Sleep ++ {"PM_SPI_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_GPIO), REG_PM_SPI_GPIO_MASK}, ++ {"PM_SPIWPN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIWPN_GPIO), REG_PM_SPIWPN_GPIO_MASK}, ++ {"PM_SPIHOLDN_MODE",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIHOLDN_MODE), REG_PM_SPIHOLDN_MODE_MASK}, ++ {"PM_SPICSZ1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ1_GPIO), REG_PM_SPICSZ1_GPIO_MASK}, ++ {"PM_SPICSZ2_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_GPIO), REG_PM_SPICSZ2_GPIO_MASK}, ++ {"PM_PWM0_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM0_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM1_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, ++ {"PM_PWM1_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, ++ {"PM_PWM2_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, ++ {"PM_PWM2_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, ++ {"PM_PWM3_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, ++ {"PM_PWM3_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, ++ {"PM_PWM4_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM4_MODE), REG_PM_PWM4_MODE_MASK}, ++ {"PM_PWM5_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM5_MODE), REG_PM_PWM5_MODE_MASK}, ++ {"PM_PWM8_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM8_MODE), REG_PM_PWM8_MODE_MASK}, ++ {"PM_PWM9_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM9_MODE), REG_PM_PWM9_MODE_MASK}, ++ {"PM_PWM10_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM10_MODE), REG_PM_PWM10_MODE_MASK}, ++ {"PM_UART1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), REG_PM_UART1_MODE_MASK}, ++ {"PM_VID_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_3", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_SD_CDZ_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SD_CDZ_MODE), REG_PM_SD_CDZ_MODE_MASK}, ++ {"PM_LED_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, ++ {"PM_TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"PM_TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"PM_IRIN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), REG_PM_IR_IS_GPIO_MASK}, ++ {"PM_SAR_MODE", _RIUA_16BIT(SAR_BANK,0x11), 0x3F}, ++ {"PM_USB_MODE", _RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK}, ++}; ++ ++//============================================================================== ++// ++// FUNCTIONS ++// ++//============================================================================== ++ ++//------------------------------------------------------------------------------ ++// Function : _HalCheckPin ++// Description : ++//------------------------------------------------------------------------------ ++static S32 _HalCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++static void _HalSARGPIOWriteRegBit(u32 u32RegOffset, bool bEnable, U8 u8BitMsk) ++{ ++ if (bEnable) ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) |= u8BitMsk; ++ else ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) &= (~u8BitMsk); ++} ++ ++static void _HalPadDisablePadMux(U32 u32PadModeID) ++{ ++ if (_GPIO_R_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask)) { ++ _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, 0, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask); ++ } ++} ++ ++static S32 HalPadSetMode_General(U32 u32PadID, U32 u32Mode) ++{ ++ U32 u32RegAddr = 0; ++ U16 u16RegVal = 0; ++ U8 u8ModeIsFind = 0; ++ U16 i = 0; ++ ++ for (i = 0; i < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); i++) ++ { ++ if (u32PadID == m_stPadMuxTbl[i].padID) ++ { ++ u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[i].base, m_stPadMuxTbl[i].offset); ++ ++ if (u32Mode == m_stPadMuxTbl[i].mode) ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stPadMuxTbl[i].mask); ++ u16RegVal |= m_stPadMuxTbl[i].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ ++ u8ModeIsFind = 1; ++#if (ENABLE_CHECK_ALL_PAD_CONFLICT == 0) ++ break; ++#endif ++ } ++ else ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask); ++ ++ if (u16RegVal == m_stPadMuxTbl[i].val) ++ { ++ printk(KERN_INFO"[Padmux]reset PAD%d(reg 0x%x:%x; mask0x%x) t0 %s (org: %s)\n", ++ u32PadID, ++ m_stPadMuxTbl[i].base, ++ m_stPadMuxTbl[i].offset, ++ m_stPadMuxTbl[i].mask, ++ m_stPadModeInfoTbl[u32Mode].u8PadName, ++ m_stPadModeInfoTbl[m_stPadMuxTbl[i].mode].u8PadName); ++ if (m_stPadMuxTbl[i].val != 0) ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stPadMuxTbl[i].mask); ++ } ++ else ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask, m_stPadMuxTbl[i].mask); ++ } ++ } ++ } ++ } ++ } ++ ++ return (u8ModeIsFind) ? 0 : -1; ++} ++ ++static S32 HalPadSetMode_MISC(U32 u32PadID, U32 u32Mode) ++{ ++ switch(u32PadID) ++ { ++ /* PM_GPIO4 */ ++ case PAD_PM_GPIO4: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), 0, REG_TTL_MODE_MASK); ++ } ++ else if (u32Mode == REG_PM_UART1_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_TTL_MODE_1) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), BIT6, REG_TTL_MODE_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_TTL_MODE_2) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), BIT7, REG_TTL_MODE_MASK); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ ++ /* SAR */ ++ case PAD_SAR_GPIO0: /* reg_sar_aisel; reg[1422]#5 ~ #0=0b */ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH0_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH0_AISEL, REG_SAR_CH0_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO1: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH1_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH1_AISEL, REG_SAR_CH1_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO2: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH2_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH2_AISEL, REG_SAR_CH2_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO3: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH3_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH3_AISEL, REG_SAR_CH3_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ ++ /* lan-top */ ++ case PAD_ETH_RN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT0, BIT0); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT0); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_ETH_RP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT1, BIT1); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT1); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_ETH_TN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT2, BIT2); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT2); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_ETH_TP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT3, BIT3); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT3); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ ++ /* UTMI */ ++ case PAD_USB_DM: ++ case PAD_USB_DP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE); ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_USB_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), ~REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), ~REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), ~REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalPadSetVal ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetVal(U32 u32PadID, U32 u32Mode) ++{ ++ if (FALSE == _HalCheckPin(u32PadID)) { ++ return FALSE; ++ } ++ ++ if (u32PadID == PAD_PM_GPIO4 || ++ (u32PadID >= PAD_SAR_GPIO0 && u32PadID <= PAD_USB_DP)) ++ { ++ return HalPadSetMode_MISC(u32PadID, u32Mode); ++ } ++ else ++ { ++ return HalPadSetMode_General(u32PadID, u32Mode); ++ } ++} ++//------------------------------------------------------------------------------ ++// Function : HalPadSet ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetMode(U32 u32Mode) ++{ ++ U32 u32PadID; ++ U16 k = 0; ++ ++ for (k = 0; k < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); k++) ++ { ++ if (u32Mode == m_stPadMuxTbl[k].mode) ++ { ++ u32PadID = m_stPadMuxTbl[k].padID; ++ if (HalPadSetMode_General( u32PadID, u32Mode) < 0) ++ { ++ return -1; ++ } ++ } ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/gpio/infinity6/mhal_pinmux.h b/drivers/sstar/gpio/infinity6/mhal_pinmux.h +new file mode 100644 +index 000000000000..32594933c756 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6/mhal_pinmux.h +@@ -0,0 +1,9 @@ ++#ifndef __MHAL_PINMUX_H__ ++#define __MHAL_PINMUX_H__ ++ ++#include "mdrv_types.h" ++ ++extern S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++extern S32 HalPadSetMode(U32 u32Mode); ++ ++#endif // __MHAL_PINMUX_H__ +diff --git a/drivers/sstar/gpio/infinity6b0/Makefile b/drivers/sstar/gpio/infinity6b0/Makefile +new file mode 100755 +index 000000000000..01cd644f4e48 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6b0/Makefile +@@ -0,0 +1,14 @@ ++# ++# Makefile for MStar GPIO device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mhal_gpio.o ++obj-$(CONFIG_MS_GPIO) += mhal_pinmux.o +diff --git a/drivers/sstar/gpio/infinity6b0/mhal_gpio.c b/drivers/sstar/gpio/infinity6b0/mhal_gpio.c +new file mode 100755 +index 000000000000..0687d949d49b +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6b0/mhal_gpio.c +@@ -0,0 +1,951 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include "mhal_gpio.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++#include "padmux.h" ++#include "mhal_pinmux.h" ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// PADTOP ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103C00, BIT5 ++#define GPIO0_OUT 0x103C00, BIT4 ++#define GPIO0_IN 0x103C00, BIT0 ++#define GPIO0_PE 0x000000, BIT0 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103C02, BIT5 ++#define GPIO1_OUT 0x103C02, BIT4 ++#define GPIO1_IN 0x103C02, BIT0 ++#define GPIO1_PE 0x000000, BIT0 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103C04, BIT5 ++#define GPIO2_OUT 0x103C04, BIT4 ++#define GPIO2_IN 0x103C04, BIT0 ++#define GPIO2_PE 0x000000, BIT0 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103C06, BIT5 ++#define GPIO3_OUT 0x103C06, BIT4 ++#define GPIO3_IN 0x103C06, BIT0 ++#define GPIO3_PE 0x000000, BIT0 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103C08, BIT5 ++#define GPIO4_OUT 0x103C08, BIT4 ++#define GPIO4_IN 0x103C08, BIT0 ++#define GPIO4_PE 0x000000, BIT0 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103C0A, BIT5 ++#define GPIO5_OUT 0x103C0A, BIT4 ++#define GPIO5_IN 0x103C0A, BIT0 ++#define GPIO5_PE 0x000000, BIT0 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103C0C, BIT5 ++#define GPIO6_OUT 0x103C0C, BIT4 ++#define GPIO6_IN 0x103C0C, BIT0 ++#define GPIO6_PE 0x000000, BIT0 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103C0E, BIT5 ++#define GPIO7_OUT 0x103C0E, BIT4 ++#define GPIO7_IN 0x103C0E, BIT0 ++#define GPIO7_PE 0x000000, BIT0 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103C10, BIT5 ++#define GPIO8_OUT 0x103C10, BIT4 ++#define GPIO8_IN 0x103C10, BIT0 ++#define GPIO8_PE 0x000000, BIT0 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103C12, BIT5 ++#define GPIO9_OUT 0x103C12, BIT4 ++#define GPIO9_IN 0x103C12, BIT0 ++#define GPIO9_PE 0x000000, BIT0 ++ ++#define GPIO10_PAD PAD_GPIO12 ++#define GPIO10_OEN 0x103C18, BIT5 ++#define GPIO10_OUT 0x103C18, BIT4 ++#define GPIO10_IN 0x103C18, BIT0 ++#define GPIO10_PE 0x000000, BIT0 ++ ++#define GPIO11_PAD PAD_GPIO13 ++#define GPIO11_OEN 0x103C1A, BIT5 ++#define GPIO11_OUT 0x103C1A, BIT4 ++#define GPIO11_IN 0x103C1A, BIT0 ++#define GPIO11_PE 0x000000, BIT0 ++ ++#define GPIO12_PAD PAD_GPIO14 ++#define GPIO12_OEN 0x103C1C, BIT5 ++#define GPIO12_OUT 0x103C1C, BIT4 ++#define GPIO12_IN 0x103C1C, BIT0 ++#define GPIO12_PE 0x000000, BIT0 ++ ++#define GPIO13_PAD PAD_GPIO15 ++#define GPIO13_OEN 0x103C1E, BIT5 ++#define GPIO13_OUT 0x103C1E, BIT4 ++#define GPIO13_IN 0x103C1E, BIT0 ++#define GPIO13_PE 0x000000, BIT0 ++ ++#define GPIO14_PAD PAD_FUART_RX ++#define GPIO14_OEN 0x103C28, BIT5 ++#define GPIO14_OUT 0x103C28, BIT4 ++#define GPIO14_IN 0x103C28, BIT0 ++#define GPIO14_PE 0x000000, BIT0 ++ ++#define GPIO15_PAD PAD_FUART_TX ++#define GPIO15_OEN 0x103C2A, BIT5 ++#define GPIO15_OUT 0x103C2A, BIT4 ++#define GPIO15_IN 0x103C2A, BIT0 ++#define GPIO15_PE 0x000000, BIT0 ++ ++#define GPIO16_PAD PAD_FUART_CTS ++#define GPIO16_OEN 0x103C2C, BIT5 ++#define GPIO16_OUT 0x103C2C, BIT4 ++#define GPIO16_IN 0x103C2C, BIT0 ++#define GPIO16_PE 0x000000, BIT0 ++ ++#define GPIO17_PAD PAD_FUART_RTS ++#define GPIO17_OEN 0x103C2E, BIT5 ++#define GPIO17_OUT 0x103C2E, BIT4 ++#define GPIO17_IN 0x103C2E, BIT0 ++#define GPIO17_PE 0x000000, BIT0 ++ ++#define GPIO18_PAD PAD_I2C0_SCL ++#define GPIO18_OEN 0x103CC0, BIT5 ++#define GPIO18_OUT 0x103CC0, BIT4 ++#define GPIO18_IN 0x103CC0, BIT0 ++#define GPIO18_PE 0x000000, BIT0 ++ ++#define GPIO19_PAD PAD_I2C0_SDA ++#define GPIO19_OEN 0x103CC2, BIT5 ++#define GPIO19_OUT 0x103CC2, BIT4 ++#define GPIO19_IN 0x103CC2, BIT0 ++#define GPIO19_PE 0x000000, BIT0 ++ ++#define GPIO20_PAD PAD_I2C1_SCL ++#define GPIO20_OEN 0x103CC4, BIT5 ++#define GPIO20_OUT 0x103CC4, BIT4 ++#define GPIO20_IN 0x103CC4, BIT0 ++#define GPIO20_PE 0x101E4A, BIT0 ++ ++#define GPIO21_PAD PAD_I2C1_SDA ++#define GPIO21_OEN 0x103CC6, BIT5 ++#define GPIO21_OUT 0x103CC6, BIT4 ++#define GPIO21_IN 0x103CC6, BIT0 ++#define GPIO21_PE 0x101E4A, BIT1 ++ ++#define GPIO22_PAD PAD_SR_IO00 ++#define GPIO22_OEN 0x103C40, BIT5 ++#define GPIO22_OUT 0x103C40, BIT4 ++#define GPIO22_IN 0x103C40, BIT0 ++#define GPIO22_PE 0x101E74, BIT0 ++ ++#define GPIO23_PAD PAD_SR_IO01 ++#define GPIO23_OEN 0x103C42, BIT5 ++#define GPIO23_OUT 0x103C42, BIT4 ++#define GPIO23_IN 0x103C42, BIT0 ++#define GPIO23_PE 0x101E74, BIT1 ++ ++#define GPIO24_PAD PAD_SR_IO02 ++#define GPIO24_OEN 0x103C44, BIT5 ++#define GPIO24_OUT 0x103C44, BIT4 ++#define GPIO24_IN 0x103C44, BIT0 ++#define GPIO24_PE 0x101E74, BIT2 ++ ++#define GPIO25_PAD PAD_SR_IO03 ++#define GPIO25_OEN 0x103C46, BIT5 ++#define GPIO25_OUT 0x103C46, BIT4 ++#define GPIO25_IN 0x103C46, BIT0 ++#define GPIO25_PE 0x101E74, BIT3 ++ ++#define GPIO26_PAD PAD_SR_IO04 ++#define GPIO26_OEN 0x103C48, BIT5 ++#define GPIO26_OUT 0x103C48, BIT4 ++#define GPIO26_IN 0x103C48, BIT0 ++#define GPIO26_PE 0x101E74, BIT4 ++ ++#define GPIO27_PAD PAD_SR_IO05 ++#define GPIO27_OEN 0x103C4A, BIT5 ++#define GPIO27_OUT 0x103C4A, BIT4 ++#define GPIO27_IN 0x103C4A, BIT0 ++#define GPIO27_PE 0x101E74, BIT5 ++ ++#define GPIO28_PAD PAD_SR_IO06 ++#define GPIO28_OEN 0x103C4C, BIT5 ++#define GPIO28_OUT 0x103C4C, BIT4 ++#define GPIO28_IN 0x103C4C, BIT0 ++#define GPIO28_PE 0x101E74, BIT6 ++ ++#define GPIO29_PAD PAD_SR_IO07 ++#define GPIO29_OEN 0x103C4E, BIT5 ++#define GPIO29_OUT 0x103C4E, BIT4 ++#define GPIO29_IN 0x103C4E, BIT0 ++#define GPIO29_PE 0x101E74, BIT7 ++ ++#define GPIO30_PAD PAD_SR_IO08 ++#define GPIO30_OEN 0x103C50, BIT5 ++#define GPIO30_OUT 0x103C50, BIT4 ++#define GPIO30_IN 0x103C50, BIT0 ++#define GPIO30_PE 0x101E75, BIT0 ++ ++#define GPIO31_PAD PAD_SR_IO09 ++#define GPIO31_OEN 0x103C52, BIT5 ++#define GPIO31_OUT 0x103C52, BIT4 ++#define GPIO31_IN 0x103C52, BIT0 ++#define GPIO31_PE 0x101E75, BIT1 ++ ++#define GPIO32_PAD PAD_SR_IO10 ++#define GPIO32_OEN 0x103C54, BIT5 ++#define GPIO32_OUT 0x103C54, BIT4 ++#define GPIO32_IN 0x103C54, BIT0 ++#define GPIO32_PE 0x101E75, BIT2 ++ ++#define GPIO33_PAD PAD_SR_IO11 ++#define GPIO33_OEN 0x103C56, BIT5 ++#define GPIO33_OUT 0x103C56, BIT4 ++#define GPIO33_IN 0x103C56, BIT0 ++#define GPIO33_PE 0x101E75, BIT3 ++ ++#define GPIO34_PAD PAD_SR_IO12 ++#define GPIO34_OEN 0x103C58, BIT5 ++#define GPIO34_OUT 0x103C58, BIT4 ++#define GPIO34_IN 0x103C58, BIT0 ++#define GPIO34_PE 0x101E75, BIT4 ++ ++#define GPIO35_PAD PAD_SR_IO13 ++#define GPIO35_OEN 0x103C5A, BIT5 ++#define GPIO35_OUT 0x103C5A, BIT4 ++#define GPIO35_IN 0x103C5A, BIT0 ++#define GPIO35_PE 0x101E75, BIT5 ++ ++#define GPIO36_PAD PAD_SR_IO14 ++#define GPIO36_OEN 0x103C5C, BIT5 ++#define GPIO36_OUT 0x103C5C, BIT4 ++#define GPIO36_IN 0x103C5C, BIT0 ++#define GPIO36_PE 0x101E75, BIT6 ++ ++#define GPIO37_PAD PAD_SR_IO15 ++#define GPIO37_OEN 0x103C5E, BIT5 ++#define GPIO37_OUT 0x103C5E, BIT4 ++#define GPIO37_IN 0x103C5E, BIT0 ++#define GPIO37_PE 0x101E75, BIT7 ++ ++#define GPIO38_PAD PAD_SR_IO16 ++#define GPIO38_OEN 0x103C60, BIT5 ++#define GPIO38_OUT 0x103C60, BIT4 ++#define GPIO38_IN 0x103C60, BIT0 ++#define GPIO38_PE 0x101E76, BIT0 ++ ++#define GPIO39_PAD PAD_SR_IO17 ++#define GPIO39_OEN 0x103C62, BIT5 ++#define GPIO39_OUT 0x103C62, BIT4 ++#define GPIO39_IN 0x103C62, BIT0 ++#define GPIO39_PE 0x101E76, BIT1 ++ ++#define GPIO40_PAD PAD_UART0_RX ++#define GPIO40_OEN 0x103C30, BIT5 ++#define GPIO40_OUT 0x103C30, BIT4 ++#define GPIO40_IN 0x103C30, BIT0 ++#define GPIO40_PE 0x000000, BIT0 ++ ++#define GPIO41_PAD PAD_UART0_TX ++#define GPIO41_OEN 0x103C32, BIT5 ++#define GPIO41_OUT 0x103C32, BIT4 ++#define GPIO41_IN 0x103C32, BIT0 ++#define GPIO41_PE 0x000000, BIT0 ++ ++#define GPIO42_PAD PAD_UART1_RX ++#define GPIO42_OEN 0x103C34, BIT5 ++#define GPIO42_OUT 0x103C34, BIT4 ++#define GPIO42_IN 0x103C34, BIT0 ++#define GPIO42_PE 0x000000, BIT0 ++ ++#define GPIO43_PAD PAD_UART1_TX ++#define GPIO43_OEN 0x103C36, BIT5 ++#define GPIO43_OUT 0x103C36, BIT4 ++#define GPIO43_IN 0x103C36, BIT0 ++#define GPIO43_PE 0x000000, BIT0 ++ ++#define GPIO44_PAD PAD_SPI0_CZ ++#define GPIO44_OEN 0x103CE0, BIT5 ++#define GPIO44_OUT 0x103CE0, BIT4 ++#define GPIO44_IN 0x103CE0, BIT0 ++#define GPIO44_PE 0x000000, BIT0 ++ ++#define GPIO45_PAD PAD_SPI0_CK ++#define GPIO45_OEN 0x103CE2, BIT5 ++#define GPIO45_OUT 0x103CE2, BIT4 ++#define GPIO45_IN 0x103CE2, BIT0 ++#define GPIO45_PE 0x000000, BIT0 ++ ++#define GPIO46_PAD PAD_SPI0_DI ++#define GPIO46_OEN 0x103CE4, BIT5 ++#define GPIO46_OUT 0x103CE4, BIT4 ++#define GPIO46_IN 0x103CE4, BIT0 ++#define GPIO46_PE 0x000000, BIT0 ++ ++#define GPIO47_PAD PAD_SPI0_DO ++#define GPIO47_OEN 0x103CE6, BIT5 ++#define GPIO47_OUT 0x103CE6, BIT4 ++#define GPIO47_IN 0x103CE6, BIT0 ++#define GPIO47_PE 0x000000, BIT0 ++ ++#define GPIO48_PAD PAD_SPI1_CZ ++#define GPIO48_OEN 0x103CE8, BIT5 ++#define GPIO48_OUT 0x103CE8, BIT4 ++#define GPIO48_IN 0x103CE8, BIT0 ++#define GPIO48_PE 0x000000, BIT0 ++ ++#define GPIO49_PAD PAD_SPI1_CK ++#define GPIO49_OEN 0x103CEA, BIT5 ++#define GPIO49_OUT 0x103CEA, BIT4 ++#define GPIO49_IN 0x103CEA, BIT0 ++#define GPIO49_PE 0x000000, BIT0 ++ ++#define GPIO50_PAD PAD_SPI1_DI ++#define GPIO50_OEN 0x103CEC, BIT5 ++#define GPIO50_OUT 0x103CEC, BIT4 ++#define GPIO50_IN 0x103CEC, BIT0 ++#define GPIO50_PE 0x000000, BIT0 ++ ++#define GPIO51_PAD PAD_SPI1_DO ++#define GPIO51_OEN 0x103CEE, BIT5 ++#define GPIO51_OUT 0x103CEE, BIT4 ++#define GPIO51_IN 0x103CEE, BIT0 ++#define GPIO51_PE 0x000000, BIT0 ++ ++#define GPIO52_PAD PAD_PWM0 ++#define GPIO52_OEN 0x103C20, BIT5 ++#define GPIO52_OUT 0x103C20, BIT4 ++#define GPIO52_IN 0x103C20, BIT0 ++#define GPIO52_PE 0x000000, BIT0 ++ ++#define GPIO53_PAD PAD_PWM1 ++#define GPIO53_OEN 0x103C22, BIT5 ++#define GPIO53_OUT 0x103C22, BIT4 ++#define GPIO53_IN 0x103C22, BIT0 ++#define GPIO53_PE 0x000000, BIT0 ++ ++#define GPIO54_PAD PAD_SD_CLK ++#define GPIO54_OEN 0x103CA0, BIT5 ++#define GPIO54_OUT 0x103CA0, BIT4 ++#define GPIO54_IN 0x103CA0, BIT0 ++#define GPIO54_PE 0x000000, BIT0 ++ ++#define GPIO55_PAD PAD_SD_CMD ++#define GPIO55_OEN 0x103CA2, BIT5 ++#define GPIO55_OUT 0x103CA2, BIT4 ++#define GPIO55_IN 0x103CA2, BIT0 ++#define GPIO55_PE 0x101E65, BIT0 ++ ++#define GPIO56_PAD PAD_SD_D0 ++#define GPIO56_OEN 0x103CA4, BIT5 ++#define GPIO56_OUT 0x103CA4, BIT4 ++#define GPIO56_IN 0x103CA4, BIT0 ++#define GPIO56_PE 0x101E65, BIT1 ++ ++#define GPIO57_PAD PAD_SD_D1 ++#define GPIO57_OEN 0x103CA6, BIT5 ++#define GPIO57_OUT 0x103CA6, BIT4 ++#define GPIO57_IN 0x103CA6, BIT0 ++#define GPIO57_PE 0x101E65, BIT2 ++ ++#define GPIO58_PAD PAD_SD_D2 ++#define GPIO58_OEN 0x103CA8, BIT5 ++#define GPIO58_OUT 0x103CA8, BIT4 ++#define GPIO58_IN 0x103CA8, BIT0 ++#define GPIO58_PE 0x101E65, BIT3 ++ ++#define GPIO59_PAD PAD_SD_D3 ++#define GPIO59_OEN 0x103CAA, BIT5 ++#define GPIO59_OUT 0x103CAA, BIT4 ++#define GPIO59_IN 0x103CAA, BIT0 ++#define GPIO59_PE 0x101E65, BIT4 ++ ++// PM ++#define GPIO60_PAD PAD_PM_SD_CDZ ++#define GPIO60_OEN 0xF8E, BIT0 ++#define GPIO60_OUT 0xF8E, BIT1 ++#define GPIO60_IN 0xF8E, BIT2 ++#define GPIO60_PE 0x000000, BIT0 ++ ++#define GPIO61_PAD PAD_PM_IRIN ++#define GPIO61_OEN 0xF28, BIT0 ++#define GPIO61_OUT 0xF28, BIT1 ++#define GPIO61_IN 0xF28, BIT2 ++#define GPIO61_PE 0x000000, BIT0 ++ ++#define GPIO62_PAD PAD_PM_GPIO0 ++#define GPIO62_OEN 0xF00, BIT0 ++#define GPIO62_OUT 0xF00, BIT1 ++#define GPIO62_IN 0xF00, BIT2 ++#define GPIO62_PE 0x000000, BIT0 ++ ++#define GPIO63_PAD PAD_PM_GPIO1 ++#define GPIO63_OEN 0xF02, BIT0 ++#define GPIO63_OUT 0xF02, BIT1 ++#define GPIO63_IN 0xF02, BIT2 ++#define GPIO63_PE 0x000000, BIT0 ++ ++#define GPIO64_PAD PAD_PM_GPIO2 ++#define GPIO64_OEN 0xF04, BIT0 ++#define GPIO64_OUT 0xF04, BIT1 ++#define GPIO64_IN 0xF04, BIT2 ++#define GPIO64_PE 0x000000, BIT0 ++ ++#define GPIO65_PAD PAD_PM_GPIO3 ++#define GPIO65_OEN 0xF06, BIT0 ++#define GPIO65_OUT 0xF06, BIT1 ++#define GPIO65_IN 0xF06, BIT2 ++#define GPIO65_PE 0x000000, BIT0 ++ ++#define GPIO66_PAD PAD_PM_GPIO4 ++#define GPIO66_OEN 0xF08, BIT0 ++#define GPIO66_OUT 0xF08, BIT1 ++#define GPIO66_IN 0xF08, BIT2 ++#define GPIO66_PE 0x000000, BIT0 ++ ++#define GPIO67_PAD PAD_PM_GPIO7 ++#define GPIO67_OEN 0xF0E, BIT0 ++#define GPIO67_OUT 0xF0E, BIT1 ++#define GPIO67_IN 0xF0E, BIT2 ++#define GPIO67_PE 0x000000, BIT0 ++ ++#define GPIO68_PAD PAD_PM_GPIO8 ++#define GPIO68_OEN 0xF10, BIT0 ++#define GPIO68_OUT 0xF10, BIT1 ++#define GPIO68_IN 0xF10, BIT2 ++#define GPIO68_PE 0x000000, BIT0 ++ ++#define GPIO69_PAD PAD_PM_GPIO9 ++#define GPIO69_OEN 0xF12, BIT0 ++#define GPIO69_OUT 0xF12, BIT1 ++#define GPIO69_IN 0xF12, BIT2 ++#define GPIO69_PE 0x000000, BIT0 ++ ++#define GPIO70_PAD PAD_PM_SPI_CZ ++#define GPIO70_OEN 0xF30, BIT0 ++#define GPIO70_OUT 0xF30, BIT1 ++#define GPIO70_IN 0xF30, BIT2 ++#define GPIO70_PE 0x000000, BIT0 ++ ++#define GPIO71_PAD PAD_PM_SPI_CK ++#define GPIO71_OEN 0xF32, BIT0 ++#define GPIO71_OUT 0xF32, BIT1 ++#define GPIO71_IN 0xF32, BIT2 ++#define GPIO71_PE 0x000000, BIT0 ++ ++#define GPIO72_PAD PAD_PM_SPI_DI ++#define GPIO72_OEN 0xF34, BIT0 ++#define GPIO72_OUT 0xF34, BIT1 ++#define GPIO72_IN 0xF34, BIT2 ++#define GPIO72_PE 0x000000, BIT0 ++ ++#define GPIO73_PAD PAD_PM_SPI_DO ++#define GPIO73_OEN 0xF36, BIT0 ++#define GPIO73_OUT 0xF36, BIT1 ++#define GPIO73_IN 0xF36, BIT2 ++#define GPIO73_PE 0x000000, BIT0 ++ ++#define GPIO74_PAD PAD_PM_SPI_WPZ ++#define GPIO74_OEN 0xF88, BIT0 ++#define GPIO74_OUT 0xF88, BIT1 ++#define GPIO74_IN 0xF88, BIT2 ++#define GPIO74_PE 0x000000, BIT0 ++ ++#define GPIO75_PAD PAD_PM_SPI_HLD ++#define GPIO75_OEN 0xF8A, BIT0 ++#define GPIO75_OUT 0xF8A, BIT1 ++#define GPIO75_IN 0xF8A, BIT2 ++#define GPIO75_PE 0x000000, BIT0 ++ ++#define GPIO76_PAD PAD_PM_LED0 ++#define GPIO76_OEN 0xF94, BIT0 ++#define GPIO76_OUT 0xF94, BIT1 ++#define GPIO76_IN 0xF94, BIT2 ++#define GPIO76_PE 0x000000, BIT0 ++ ++#define GPIO77_PAD PAD_PM_LED1 ++#define GPIO77_OEN 0xF96, BIT0 ++#define GPIO77_OUT 0xF96, BIT1 ++#define GPIO77_IN 0xF96, BIT2 ++#define GPIO77_PE 0x000000, BIT0 ++ ++// SAR ++#define GPIO78_PAD PAD_SAR_GPIO0 ++#define GPIO78_OEN 0x1423, BIT0 ++#define GPIO78_OUT 0x1424, BIT0 ++#define GPIO78_IN 0x1425, BIT0 ++#define GPIO78_PE 0x000000, BIT0 ++ ++#define GPIO79_PAD PAD_SAR_GPIO1 ++#define GPIO79_OEN 0x1423, BIT1 ++#define GPIO79_OUT 0x1424, BIT1 ++#define GPIO79_IN 0x1425, BIT1 ++#define GPIO79_PE 0x000000, BIT0 ++ ++#define GPIO80_PAD PAD_SAR_GPIO2 ++#define GPIO80_OEN 0x1423, BIT2 ++#define GPIO80_OUT 0x1424, BIT2 ++#define GPIO80_IN 0x1425, BIT2 ++#define GPIO80_PE 0x000000, BIT0 ++ ++#define GPIO81_PAD PAD_SAR_GPIO3 ++#define GPIO81_OEN 0x1423, BIT3 ++#define GPIO81_OUT 0x1424, BIT3 ++#define GPIO81_IN 0x1425, BIT3 ++#define GPIO81_PE 0x000000, BIT0 ++ ++// ALBANY ++#define GPIO82_PAD PAD_ETH_RN ++#define GPIO82_OEN 0x33E2, BIT4 ++#define GPIO82_OUT 0x33E4, BIT0 ++#define GPIO82_IN 0x33E4, BIT4 ++#define GPIO82_PE 0x000000, BIT0 ++ ++#define GPIO83_PAD PAD_ETH_RP ++#define GPIO83_OEN 0x33E2, BIT5 ++#define GPIO83_OUT 0x33E4, BIT1 ++#define GPIO83_IN 0x33E4, BIT5 ++#define GPIO83_PE 0x000000, BIT0 ++ ++#define GPIO84_PAD PAD_ETH_TN ++#define GPIO84_OEN 0x33E2, BIT6 ++#define GPIO84_OUT 0x33E4, BIT2 ++#define GPIO84_IN 0x33E4, BIT6 ++#define GPIO84_PE 0x000000, BIT0 ++ ++#define GPIO85_PAD PAD_ETH_TP ++#define GPIO85_OEN 0x33E2, BIT7 ++#define GPIO85_OUT 0x33E4, BIT3 ++#define GPIO85_IN 0x33E4, BIT7 ++#define GPIO85_PE 0x000000, BIT0 ++ ++// UTMI ++#define GPIO86_PAD PAD_USB_DM ++#define GPIO86_OEN 0x14210a, BIT4 ++#define GPIO86_OUT 0x14210a, BIT2 ++#define GPIO86_IN 0x142131, BIT5 ++#define GPIO86_PE 0x000000, BIT0 ++ ++#define GPIO87_PAD PAD_USB_DP ++#define GPIO87_OEN 0x14210a, BIT5 ++#define GPIO87_OUT 0x14210a, BIT3 ++#define GPIO87_IN 0x142131, BIT4 ++#define GPIO87_PE 0x000000, BIT0 ++ ++//SDIO ++#define GPIO88_PAD PAD_SD1_IO0 ++#define GPIO88_OEN 0x103C80, BIT5 ++#define GPIO88_OUT 0x103C80, BIT4 ++#define GPIO88_IN 0x103C80, BIT0 ++#define GPIO88_PE 0x101E62, BIT0 ++ ++#define GPIO89_PAD PAD_SD1_IO1 ++#define GPIO89_OEN 0x103C82, BIT5 ++#define GPIO89_OUT 0x103C82, BIT4 ++#define GPIO89_IN 0x103C82, BIT0 ++#define GPIO89_PE 0x101E62, BIT1 ++ ++#define GPIO90_PAD PAD_SD1_IO2 ++#define GPIO90_OEN 0x103C84, BIT5 ++#define GPIO90_OUT 0x103C84, BIT4 ++#define GPIO90_IN 0x103C84, BIT0 ++#define GPIO90_PE 0x101E62, BIT2 ++ ++#define GPIO91_PAD PAD_SD1_IO3 ++#define GPIO91_OEN 0x103C86, BIT5 ++#define GPIO91_OUT 0x103C86, BIT4 ++#define GPIO91_IN 0x103C86, BIT0 ++#define GPIO91_PE 0x101E62, BIT3 ++ ++#define GPIO92_PAD PAD_SD1_IO4 ++#define GPIO92_OEN 0x103C88, BIT5 ++#define GPIO92_OUT 0x103C88, BIT4 ++#define GPIO92_IN 0x103C88, BIT0 ++#define GPIO92_PE 0x101E62, BIT4 ++ ++#define GPIO93_PAD PAD_SD1_IO5 ++#define GPIO93_OEN 0x103C8A, BIT5 ++#define GPIO93_OUT 0x103C8A, BIT4 ++#define GPIO93_IN 0x103C8A, BIT0 ++#define GPIO93_PE 0x000000, BIT0 ++ ++#define GPIO94_PAD PAD_SD1_IO6 ++#define GPIO94_OEN 0x103C8C, BIT5 ++#define GPIO94_OUT 0x103C8C, BIT4 ++#define GPIO94_IN 0x103C8C, BIT0 ++#define GPIO94_PE 0x000000, BIT0 ++ ++#define GPIO95_PAD PAD_SD1_IO7 ++#define GPIO95_OEN 0x103C8E, BIT5 ++#define GPIO95_OUT 0x103C8E, BIT4 ++#define GPIO95_IN 0x103C8E, BIT0 ++#define GPIO95_PE 0x000000, BIT0 ++ ++#define GPIO96_PAD PAD_SD1_IO8 ++#define GPIO96_OEN 0x103C90, BIT5 ++#define GPIO96_OUT 0x103C90, BIT4 ++#define GPIO96_IN 0x103C90, BIT0 ++#define GPIO96_PE 0x000000, BIT0 ++ ++U32 gChipBaseAddr = 0xFD203C00; ++U32 gPmSleepBaseAddr = 0xFD001C00; ++U32 gSarBaseAddr = 0xFD002800; ++U32 gRIUBaseAddr = 0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++#define REG_ALL_PAD_IN 0xA1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++static int _pmsleep_to_irq_table[] = { ++ INT_PMSLEEP_SD_CDZ, ++ INT_PMSLEEP_IRIN, ++ INT_PMSLEEP_GPIO_0, ++ INT_PMSLEEP_GPIO_1, ++ INT_PMSLEEP_GPIO_2, ++ INT_PMSLEEP_GPIO_3, ++ INT_PMSLEEP_GPIO_4, ++ INT_PMSLEEP_GPIO_7, ++ INT_PMSLEEP_GPIO_8, ++ INT_PMSLEEP_GPIO_9, ++ INT_PMSLEEP_SPI_CZ, ++ INT_PMSLEEP_SPI_CK, ++ INT_PMSLEEP_SPI_DI, ++ INT_PMSLEEP_SPI_DO, ++ INT_PMSLEEP_SPI_WPZ, ++ INT_PMSLEEP_SPI_HLD, ++ INT_PMSLEEP_LED0, ++ INT_PMSLEEP_LED1, ++}; ++ ++static int _gpi_to_irq_table[] = { ++ INT_GPI_FIQ_PAD_GPIO0, ++ INT_GPI_FIQ_PAD_GPIO1, ++ INT_GPI_FIQ_PAD_GPIO2, ++ INT_GPI_FIQ_PAD_GPIO3, ++ INT_GPI_FIQ_PAD_GPIO4, ++ INT_GPI_FIQ_PAD_GPIO5, ++ INT_GPI_FIQ_PAD_GPIO6, ++ INT_GPI_FIQ_PAD_GPIO7, ++ INT_GPI_FIQ_PAD_GPIO8, ++ INT_GPI_FIQ_PAD_GPIO9, ++ INT_GPI_FIQ_PAD_GPIO12, ++ INT_GPI_FIQ_PAD_GPIO13, ++ INT_GPI_FIQ_PAD_GPIO14, ++ INT_GPI_FIQ_PAD_GPIO15, ++ INT_GPI_FIQ_PAD_FUART_RX, ++ INT_GPI_FIQ_PAD_FUART_TX, ++ INT_GPI_FIQ_PAD_FUART_CTS, ++ INT_GPI_FIQ_PAD_FUART_RTS, ++ INT_GPI_FIQ_PAD_I2C0_SCL, ++ INT_GPI_FIQ_PAD_I2C0_SDA, ++ INT_GPI_FIQ_PAD_I2C1_SCL, ++ INT_GPI_FIQ_PAD_I2C1_SDA, ++ INT_GPI_FIQ_PAD_SR_IO00, ++ INT_GPI_FIQ_PAD_SR_IO01, ++ INT_GPI_FIQ_PAD_SR_IO02, ++ INT_GPI_FIQ_PAD_SR_IO03, ++ INT_GPI_FIQ_PAD_SR_IO04, ++ INT_GPI_FIQ_PAD_SR_IO05, ++ INT_GPI_FIQ_PAD_SR_IO06, ++ INT_GPI_FIQ_PAD_SR_IO07, ++ INT_GPI_FIQ_PAD_SR_IO08, ++ INT_GPI_FIQ_PAD_SR_IO09, ++ INT_GPI_FIQ_PAD_SR_IO10, ++ INT_GPI_FIQ_PAD_SR_IO11, ++ INT_GPI_FIQ_PAD_SR_IO12, ++ INT_GPI_FIQ_PAD_SR_IO13, ++ INT_GPI_FIQ_PAD_SR_IO14, ++ INT_GPI_FIQ_PAD_SR_IO15, ++ INT_GPI_FIQ_PAD_SR_IO16, ++ INT_GPI_FIQ_PAD_SR_IO17, ++ INT_GPI_FIQ_PAD_UART0_RX, ++ INT_GPI_FIQ_PAD_UART0_TX, ++ INT_GPI_FIQ_PAD_UART1_RX, ++ INT_GPI_FIQ_PAD_UART1_TX, ++ INT_GPI_FIQ_PAD_SPI0_CZ, ++ INT_GPI_FIQ_PAD_SPI0_CK, ++ INT_GPI_FIQ_PAD_SPI0_DI, ++ INT_GPI_FIQ_PAD_SPI0_DO, ++ INT_GPI_FIQ_PAD_SPI1_CZ, ++ INT_GPI_FIQ_PAD_SPI1_CK, ++ INT_GPI_FIQ_PAD_SPI1_DI, ++ INT_GPI_FIQ_PAD_SPI1_DO, ++ INT_GPI_FIQ_PAD_PWM0, ++ INT_GPI_FIQ_PAD_PWM1, ++ INT_GPI_FIQ_PAD_SD_CLK, ++ INT_GPI_FIQ_PAD_SD_CMD, ++ INT_GPI_FIQ_PAD_SD_D0, ++ INT_GPI_FIQ_PAD_SD_D1, ++ INT_GPI_FIQ_PAD_SD_D2, ++ INT_GPI_FIQ_PAD_SD_D3, ++ -1, // [60] PAD_PM_SD_CDZ ++ -1, // [61] PAD_PM_IRIN ++ -1, // [62] PAD_PM_GPIO0 ++ -1, // [63] PAD_PM_GPIO1 ++ -1, // [64] PAD_PM_GPIO2 ++ -1, // [65] PAD_PM_GPIO3 ++ -1, // [66] PAD_PM_GPIO4 ++ -1, // [67] PAD_PM_GPIO7 ++ -1, // [68] PAD_PM_GPIO8 ++ -1, // [69] PAD_PM_GPIO9 ++ -1, // [70] PAD_PM_SPI_CZ ++ -1, // [71] PAD_PM_SPI_CK ++ -1, // [72] PAD_PM_SPI_DI ++ -1, // [73] PAD_PM_SPI_DO ++ -1, // [74] PAD_PM_SPI_WPZ ++ -1, // [75] PAD_PM_SPI_HLD ++ -1, // [76] PAD_PM_LED0 ++ -1, // [77] PAD_PM_LED1 ++ -1, // [78] INT_GPI_FIQ_PAD_SAR_GPIO0, ++ -1, // [79] INT_GPI_FIQ_PAD_SAR_GPIO1, ++ -1, // [80] INT_GPI_FIQ_PAD_SAR_GPIO2, ++ -1, // [81] INT_GPI_FIQ_PAD_SAR_GPIO3, ++ -1, // [82] INT_GPI_FIQ_PAD_ETH_RN, ++ -1, // [83] INT_GPI_FIQ_PAD_ETH_RP, ++ -1, // [84] INT_GPI_FIQ_PAD_ETH_TN, ++ -1, // [85] INT_GPI_FIQ_PAD_ETH_TP, ++ -1, // [86] INT_GPI_FIQ_PAD_USB_DM, ++ -1, // [87] INT_GPI_FIQ_PAD_USB_DP, ++ INT_GPI_FIQ_PAD_SD1_IO0, ++ INT_GPI_FIQ_PAD_SD1_IO1, ++ INT_GPI_FIQ_PAD_SD1_IO2, ++ INT_GPI_FIQ_PAD_SD1_IO3, ++ INT_GPI_FIQ_PAD_SD1_IO4, ++ INT_GPI_FIQ_PAD_SD1_IO5, ++ INT_GPI_FIQ_PAD_SD1_IO6, ++ INT_GPI_FIQ_PAD_SD1_IO7, ++ INT_GPI_FIQ_PAD_SD1_IO8, ++}; ++ ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++ U32 r_pe; ++ U8 m_pe; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN), \ ++ CONCAT(CONCAT(GPIO, _x_), _PE)} ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), __GPIO(5), __GPIO(6), __GPIO(7), ++ __GPIO(8), __GPIO(9), __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), __GPIO(15), ++ __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), ++ __GPIO(24), __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), __GPIO(30), __GPIO(31), ++ __GPIO(32), __GPIO(33), __GPIO(34), __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), __GPIO(45), __GPIO(46), __GPIO(47), ++ __GPIO(48), __GPIO(49), __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), __GPIO(55), ++ __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), ++ __GPIO(64), __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), __GPIO(70), __GPIO(71), ++ __GPIO(72), __GPIO(73), __GPIO(74), __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), __GPIO(85), __GPIO(86), __GPIO(87), ++ __GPIO(88), __GPIO(89), __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), __GPIO(95), ++ __GPIO(96), ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GPIO_Init(void) ++{ ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ // Enable PE if necessary ++ if (gpio_table[u8IndexGPIO].r_pe) ++ { ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_pe) |= gpio_table[u8IndexGPIO].m_pe; ++ } ++ HalPadSetVal(u8IndexGPIO, PINMUX_FOR_GPIO_MODE); ++} ++ ++int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ return HalPadSetMode(u32PadMode); ++} ++ ++int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode) ++{ ++ return HalPadSetVal((U32)u8IndexGPIO, u32PadMode); ++} ++ ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ // TBD ++} ++ ++static int PMSLEEP_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if ((u8IndexGPIO < PAD_PM_SD_CDZ) || (u8IndexGPIO > PAD_PM_LED1)) ++ return -1; ++ else ++ { ++ return _pmsleep_to_irq_table[u8IndexGPIO-PAD_PM_SD_CDZ]; ++ } ++} ++ ++static int GPI_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if (u8IndexGPIO >= GPIO_NR) ++ return -1; ++ else ++ return _gpi_to_irq_table[u8IndexGPIO]; ++} ++ ++//MHal_GPIO_To_Irq return any virq ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ struct device_node *intr_node; ++ struct irq_domain *intr_domain; ++ struct irq_fwspec fwspec; ++ int hwirq, virq = -1; ++ ++ if ((hwirq = PMSLEEP_GPIO_To_Irq(u8IndexGPIO)) >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,pm-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else if ((hwirq = GPI_GPIO_To_Irq(u8IndexGPIO)) >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,gpi-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else if ((u8IndexGPIO >= PAD_SAR_GPIO0 && u8IndexGPIO <= PAD_SAR_GPIO3)) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,main-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 3; ++ fwspec.param[0] = GIC_SPI; ++ fwspec.param[1] = u8IndexGPIO - PAD_SAR_GPIO0 + INT_FIQ_SAR_GPIO_0; ++ fwspec.param[2] = IRQ_TYPE_NONE; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ ++ return virq; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse) ++{ ++ // TBD ++} +diff --git a/drivers/sstar/gpio/infinity6b0/mhal_gpio.h b/drivers/sstar/gpio/infinity6b0/mhal_gpio.h +new file mode 100755 +index 000000000000..b95fc6f2fe7d +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6b0/mhal_gpio.h +@@ -0,0 +1,45 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_GPIO_H_ ++#define _MHAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode); ++extern int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _MHAL_GPIO_H_ +diff --git a/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c b/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c +new file mode 100755 +index 000000000000..e7be43a66742 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c +@@ -0,0 +1,1358 @@ ++/* ++* mhal_pinmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "mhal_gpio.h" ++#include "padmux.h" ++#include "gpio.h" ++ ++//============================================================================== ++// ++// MACRO DEFINE ++// ++//============================================================================== ++ ++#define BASE_RIU_PA 0xFD000000 ++#define PMSLEEP_BANK 0x000E00 ++#define SAR_BANK 0x001400 ++#define ALBANY1_BANK 0x003200 ++#define ALBANY2_BANK 0x003300 ++#define CHIPTOP_BANK 0x101E00 ++#define UTMI0_BANK 0x142100 ++ ++#define _GPIO_W_WORD(addr,val) {(*(volatile u16*)(addr)) = (u16)(val);} ++#define _GPIO_W_WORD_MASK(addr,val,mask) {(*(volatile u16*)(addr)) = ((*(volatile u16*)(addr)) & ~(mask)) | ((u16)(val) & (mask));} ++#define _GPIO_R_BYTE(addr) (*(volatile u8*)(addr)) ++#define _GPIO_R_WORD_MASK(addr,mask) ((*(volatile u16*)(addr)) & (mask)) ++ ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define _RIUA_8BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + (((offset) & ~1)<<1) + ((offset) & 1) ++#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) ++ ++/* Non PM Pad : CHIPTOP_BANK */ ++#define REG_PWM5_MODE 0x02 ++ #define REG_PWM5_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_PWM6_MODE 0x02 ++ #define REG_PWM6_MODE_MASK BIT5|BIT4|BIT3 ++#define REG_PWM7_MODE 0x02 ++ #define REG_PWM7_MODE_MASK BIT8|BIT7|BIT6 ++#define REG_PWM8_MODE 0x02 ++ #define REG_PWM8_MODE_MASK BIT11|BIT10|BIT9 ++#define REG_PWM9_MODE 0x02 ++ #define REG_PWM9_MODE_MASK BIT14|BIT13|BIT12 ++#define REG_FUART_MODE 0x03 ++ #define REG_FUART_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_UART0_MODE 0x03 ++ #define REG_UART0_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_UART1_MODE 0x03 ++ #define REG_UART1_MODE_MASK BIT10|BIT9|BIT8 ++#define REG_PWM10_MODE 0x04 ++ #define REG_PWM10_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_SR_MODE 0x06 ++ #define REG_SR_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_SR_I2C_MODE 0x06 ++ #define REG_SR_I2C_MODE_MASK BIT5|BIT4 ++#define REG_SR_HVSYNC_MODE 0x06 ++ #define REG_SR_HVSYNC_MODE_MASK BIT6 ++#define REG_SR_MCLK_MODE 0x06 ++ #define REG_SR_MCLK_MODE_MASK BIT7 ++#define REG_SR_PCK_MODE 0x06 ++ #define REG_SR_PCK_MODE_MASK BIT8 ++#define REG_SR_PDN_MODE 0x06 ++ #define REG_SR_PDN_MODE_MASK BIT10|BIT9 ++#define REG_SR_RST_MODE 0x06 ++ #define REG_SR_RST_MODE_MASK BIT12|BIT11 ++#define REG_PWM0_MODE 0x07 ++ #define REG_PWM0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_PWM1_MODE 0x07 ++ #define REG_PWM1_MODE_MASK BIT5|BIT4|BIT3 ++#define REG_PWM2_MODE 0x07 ++ #define REG_PWM2_MODE_MASK BIT8|BIT7|BIT6 ++#define REG_PWM3_MODE 0x07 ++ #define REG_PWM3_MODE_MASK BIT11|BIT10|BIT9 ++#define REG_PWM4_MODE 0x07 ++ #define REG_PWM4_MODE_MASK BIT14|BIT13|BIT12 ++#define REG_NAND_MODE 0x08 ++ #define REG_NAND_MODE_MASK BIT0 ++#define REG_SD_MODE 0x08 ++ #define REG_SD_MODE_MASK BIT3|BIT2 ++#define REG_SDIO_MODE 0x08 ++ #define REG_SDIO_MODE_MASK BIT8 ++#define REG_I2C0_MODE 0x09 ++ #define REG_I2C0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_I2C1_MODE 0x09 ++ #define REG_I2C1_MODE_MASK BIT5|BIT4 ++#define REG_SPI0_MODE 0x0c ++ #define REG_SPI0_MODE_MASK BIT2|BIT1|BIT0 ++#define REG_SPI1_MODE 0x0c ++ #define REG_SPI1_MODE_MASK BIT6|BIT5|BIT4 ++#define REG_EJ_MODE 0x0f ++ #define REG_EJ_MODE_MASK BIT1|BIT0 ++#define REG_ETH_MODE 0x0f ++ #define REG_ETH_MODE_MASK BIT2 ++#define REG_CCIR_MODE 0x0f ++ #define REG_CCIR_MODE_MASK BIT5|BIT4 ++#define REG_TTL_MODE 0x0f ++ #define REG_TTL_MODE_MASK BIT7|BIT6 ++#define REG_DMIC_MODE 0x0f ++ #define REG_DMIC_MODE_MASK BIT9|BIT8 ++#define REG_I2S_MODE 0x0f ++ #define REG_I2S_MODE_MASK BIT11|BIT10 ++#define REG_TEST_IN_MODE 0x12 ++ #define REG_TEST_IN_MODE_MASK BIT1|BIT0 ++#define REG_TEST_OUT_MODE 0x12 ++ #define REG_TEST_OUT_MODE_MASK BIT5|BIT4 ++#define REG_EMMC_MODE 0x13 ++ #define REG_EMMC_MODE_MASK BIT0 ++#define REG_EMMC_RSTN_EN 0x13 ++ #define REG_EMMC_RSTN_EN_MASK BIT1 ++#define REG_MIPI_PAD_IN 0x33 ++ #define REG_MIPI_PAD_IN_MASK BIT1|BIT0 ++#define REG_ALLPAD_IN 0x50 ++ #define REG_ALLPAD_IN_MASK BIT15 ++ ++/* PM Sleep : PMSLEEP_BANK */ ++#define REG_PM_GPIO_PM_LOCK 0x12 ++ #define REG_PM_GPIO_PM_LOCK_MASK 0xFFFF ++#define REG_PM_GPIO_PM4_INV 0x1c ++ #define REG_PM_GPIO_PM4_INV_MASK BIT1 ++#define REG_PM_LINK_WKINT2GPIO4 0x1c ++ #define REG_PM_LINK_WKINT2GPIO4_MASK BIT3 ++#define REG_PM_IR_IS_GPIO 0x1c ++ #define REG_PM_IR_IS_GPIO_MASK BIT4 ++#define REG_PM_PWM0_MODE 0x28 ++ #define REG_PM_PWM0_MODE_MASK BIT1|BIT0 ++#define REG_PM_PWM1_MODE 0x28 ++ #define REG_PM_PWM1_MODE_MASK BIT3|BIT2 ++#define REG_PM_PWM2_MODE 0x28 ++ #define REG_PM_PWM2_MODE_MASK BIT7|BIT6 ++#define REG_PM_PWM3_MODE 0x28 ++ #define REG_PM_PWM3_MODE_MASK BIT9|BIT8 ++#define REG_PM_PWM4_MODE 0x27 ++ #define REG_PM_PWM4_MODE_MASK BIT0 ++#define REG_PM_PWM5_MODE 0x27 ++ #define REG_PM_PWM5_MODE_MASK BIT1 ++#define REG_PM_PWM8_MODE 0x27 ++ #define REG_PM_PWM8_MODE_MASK BIT2 ++#define REG_PM_PWM9_MODE 0x27 ++ #define REG_PM_PWM9_MODE_MASK BIT3 ++#define REG_PM_PWM10_MODE 0x27 ++ #define REG_PM_PWM10_MODE_MASK BIT4 ++#define REG_PM_UART1_MODE 0x27 ++ #define REG_PM_UART1_MODE_MASK BIT8 ++#define REG_PM_LED_MODE 0x28 ++ #define REG_PM_LED_MODE_MASK BIT5|BIT4 ++ ++#define REG_PM_VID_MODE 0x28 ++ #define REG_PM_VID_MODE_MASK BIT13|BIT12 ++#define REG_PM_SD_CDZ_MODE 0x28 ++ #define REG_PM_SD_CDZ_MODE_MASK BIT14 ++#define REG_PM_SPI_IS_GPIO 0x35 ++ #define REG_PM_SPI_IS_GPIO_MASK BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0 ++ #define REG_PM_SPI_GPIO_MASK BIT0 ++ #define REG_PM_SPICSZ1_GPIO_MASK BIT2 ++ #define REG_PM_SPICSZ2_GPIO_MASK BIT3 ++ #define REG_PM_SPIWPN_GPIO_MASK BIT4 ++ #define REG_PM_SPIHOLDN_MODE_MASK BIT6 | BIT7 ++#define REG_PM_SPICSZ1_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPICSZ2_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPI_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIWPN_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIHOLDN_MODE REG_PM_SPI_IS_GPIO ++ ++#define REG_PM_UART_IS_GPIO 0x35 ++ #define REG_PM_UART_IS_GPIO_MASK BIT11|BIT10|BIT9|BIT8 ++ ++/* SAR : SAR_BANK, R/W 8-bits */ ++#define REG_SAR_AISEL_8BIT 0x11*2 ++ #define REG_SAR_CH0_AISEL BIT0 ++ #define REG_SAR_CH1_AISEL BIT1 ++ #define REG_SAR_CH2_AISEL BIT2 ++ #define REG_SAR_CH3_AISEL BIT3 ++ ++/* EMAC : ALBANY1_BANK */ ++#define REG_ATOP_RX_INOFF 0x69 ++ #define REG_ATOP_RX_INOFF_MASK BIT15|BIT14 ++ ++/* EMAC : ALBANY2_BANK */ ++#define REG_ETH_GPIO_EN 0x71 ++ #define REG_ETH_GPIO_EN_MASK BIT3|BIT2|BIT1|BIT0 ++ ++/* UTMI0 : UTMI0_BANK */ ++#define REG_UTMI0_FL_XVR_PDN 0x0 ++ #define REG_UTMI0_FL_XVR_PDN_MASK BIT12 ++#define REG_UTMI0_REG_PDN 0x0 ++ #define REG_UTMI0_REG_PDN_MASK BIT15 // 1: power doen 0: enable ++#define REG_UTMI0_CLK_EXTRA0_EN 0x4 ++ #define REG_UTMI0_CLK_EXTRA0_EN_MASK BIT7 // 1: power down 0: enable ++#define REG_UTMI0_GPIO_EN 0x1f ++ #define REG_UTMI0_GPIO_EN_MASK BIT14 ++ ++//-------------------- configuration ----------------- ++#define ENABLE_CHECK_ALL_PAD_CONFLICT 0 ++ ++//============================================================================== ++// ++// STRUCTURE ++// ++//============================================================================== ++ ++typedef struct stPadMux ++{ ++ U16 padID; ++ U32 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PadMuxInfo; ++ ++typedef struct stPadMode ++{ ++ U8 u8PadName[16]; ++ U32 u32ModeRIU; ++ U32 u32ModeMask; ++} ST_PadModeInfo; ++ ++//============================================================================== ++// ++// VARIABLES ++// ++//============================================================================== ++ ++const ST_PadMuxInfo m_stPadMuxTbl[] = ++{ ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2, PINMUX_FOR_PWM0_MODE_4}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT9, PINMUX_FOR_PWM8_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5, PINMUX_FOR_PWM1_MODE_4}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT12, PINMUX_FOR_PWM9_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8, PINMUX_FOR_PWM2_MODE_4}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11, PINMUX_FOR_PWM3_MODE_4}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT0, PINMUX_FOR_PWM10_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM4_MODE_3}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM5_MODE_3}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM6_MODE_3}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM7_MODE_3}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO8, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT10, PINMUX_FOR_PWM8_MODE_2}, ++ {PAD_GPIO8, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO9, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO12, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO13, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO14, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PWM0_MODE_2}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PWM2_MODE_1}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM9_MODE_3}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_GPIO15, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4, PINMUX_FOR_PWM1_MODE_2}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PWM3_MODE_1}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM10_MODE_3}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM0_MODE_3}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM1_MODE_3}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PWM2_MODE_2}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10, PINMUX_FOR_PWM3_MODE_2}, ++ ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2C1_SCL, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2C1_SDA, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO10, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO11, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_PDN_MODE, REG_SR_PDN_MODE_MASK, BIT9, PINMUX_FOR_SR_PDN_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, ++ {PAD_SR_IO12, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_RST_MODE, REG_SR_RST_MODE_MASK, BIT11, PINMUX_FOR_SR_RST_MODE_1}, ++ {PAD_SR_IO13, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT11, PINMUX_FOR_PWM8_MODE_4}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_HVSYNC_MODE, REG_SR_HVSYNC_MODE_MASK, BIT6, PINMUX_FOR_SR_HVSYNC_MODE}, ++ ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT14, PINMUX_FOR_PWM9_MODE_4}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_PCK_MODE, REG_SR_PCK_MODE_MASK, BIT8, PINMUX_FOR_SR_PCK_MODE}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, ++ {PAD_SR_IO15, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, ++ ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT2, PINMUX_FOR_PWM10_MODE_4}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_HVSYNC_MODE, REG_SR_HVSYNC_MODE_MASK, BIT6, PINMUX_FOR_SR_HVSYNC_MODE}, ++ ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, ++ {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MCLK_MODE, REG_SR_MCLK_MODE_MASK, BIT7, PINMUX_FOR_SR_MCLK_MODE}, ++ ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_UART0_RX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_UART0_TX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_UART1_RX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, ++ ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_UART1_TX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, ++ ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_CZ, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT13, PINMUX_FOR_PWM4_MODE_2}, ++ ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_CK, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT1, PINMUX_FOR_PWM5_MODE_2}, ++ ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_DI, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT4, PINMUX_FOR_PWM6_MODE_2}, ++ ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_SPI0_DO, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT7, PINMUX_FOR_PWM7_MODE_2}, ++ ++ {PAD_SPI1_CZ, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_CZ, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SPI1_CK, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_CK, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SPI1_DI, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_DI, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_SPI1_DO, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_SPI1_DO, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, ++ ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PWM0_MODE_1}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT13, PINMUX_FOR_PWM9_MODE_2}, ++ {PAD_PWM0, CHIPTOP_BANK, REG_SR_PDN_MODE, REG_SR_PDN_MODE_MASK, BIT10, PINMUX_FOR_SR_PDN_MODE_2}, ++ ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT3, PINMUX_FOR_PWM1_MODE_1}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT1, PINMUX_FOR_PWM10_MODE_2}, ++ {PAD_PWM1, CHIPTOP_BANK, REG_SR_RST_MODE, REG_SR_RST_MODE_MASK, BIT12, PINMUX_FOR_SR_RST_MODE_2}, ++ ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD_CLK, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD_CMD, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D0, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D1, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D2, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ {PAD_SD_D3, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, ++ ++ {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SD_CDZ, PMSLEEP_BANK, REG_PM_SD_CDZ_MODE, REG_PM_SD_CDZ_MODE_MASK, BIT14, PINMUX_FOR_PM_SD_CDZ_MODE}, ++ ++ {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_IRIN, PMSLEEP_BANK, REG_PM_IR_IS_GPIO, REG_PM_IR_IS_GPIO_MASK, 0, PINMUX_FOR_PM_IRIN_MODE}, ++ ++ {PAD_PM_GPIO0, PMSLEEP_BANK, REG_PM_PWM0_MODE, REG_PM_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PM_PWM0_MODE_1}, ++ {PAD_PM_GPIO0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_PM_GPIO1, PMSLEEP_BANK, REG_PM_PWM1_MODE, REG_PM_PWM1_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM1_MODE_1}, ++ {PAD_PM_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ {PAD_PM_GPIO2, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PM_PWM2_MODE_1}, ++ ++ {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT8, PINMUX_FOR_PM_PWM3_MODE_1}, ++ {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, ++ {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ ++ /* ++ {PAD_PM_GPIO4, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, ++ {PAD_PM_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ {PAD_PM_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, ++ */ ++ ++ {PAD_PM_GPIO7, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PM_PWM3_MODE_2}, ++ ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_SPICSZ2_GPIO, REG_PM_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ2_MODE}, ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PM_PWM2_MODE_2}, ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_PWM8_MODE, REG_PM_PWM8_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM8_MODE}, ++ ++ {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_CZ, PMSLEEP_BANK, REG_PM_SPICSZ1_GPIO, REG_PM_SPICSZ1_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ1_MODE}, ++ ++ {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_CK, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_DI, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_DO, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ ++ {PAD_PM_SPI_WPZ,CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_PM_SPI_WPZ,CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_PM_SPI_WPZ,PMSLEEP_BANK, REG_PM_SPIWPN_GPIO, REG_PM_SPIWPN_GPIO_MASK, 0, PINMUX_FOR_PM_SPIWPN_MODE}, ++ ++ {PAD_PM_SPI_HLD,PMSLEEP_BANK, REG_PM_SPIHOLDN_MODE, REG_PM_SPIHOLDN_MODE_MASK, 0, PINMUX_FOR_PM_SPIHOLDN_MODE}, ++ ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_PWM4_MODE, REG_PM_PWM4_MODE_MASK, BIT0, PINMUX_FOR_PM_PWM4_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_PWM9_MODE, REG_PM_PWM9_MODE_MASK, BIT3, PINMUX_FOR_PM_PWM9_MODE}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, ++ {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE}, ++ ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM5_MODE, REG_PM_PWM5_MODE_MASK, BIT1, PINMUX_FOR_PM_PWM5_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM10_MODE, REG_PM_PWM10_MODE_MASK, BIT4, PINMUX_FOR_PM_PWM10_MODE}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, ++ {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE}, ++ ++ /* ++ {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_USB_DM, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_USB_DM, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ */ ++ ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM0_MODE_5}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM2_MODE_3}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5|BIT3, PINMUX_FOR_PWM1_MODE_5}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM3_MODE_3}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8|BIT6, PINMUX_FOR_PWM2_MODE_5}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT12, PINMUX_FOR_PWM4_MODE_1}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11|BIT9, PINMUX_FOR_PWM3_MODE_5}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT0, PINMUX_FOR_PWM5_MODE_1}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, ++ {PAD_SD1_IO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT14, PINMUX_FOR_PWM4_MODE_4}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT3, PINMUX_FOR_PWM6_MODE_1}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_SD1_IO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT2, PINMUX_FOR_PWM5_MODE_4}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT6, PINMUX_FOR_PWM7_MODE_1}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_SD1_IO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT5, PINMUX_FOR_PWM6_MODE_4}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_SD1_IO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO7, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_SD1_IO7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT8, PINMUX_FOR_PWM7_MODE_4}, ++ {PAD_SD1_IO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, ++ ++ {PAD_SD1_IO8, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM8_MODE_3}, ++ {PAD_SD1_IO8, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, ++ ++}; ++ ++static const ST_PadModeInfo m_stPadModeInfoTbl[] = ++{ ++ {"GPIO", 0, 0}, ++ // Non PM ++ {"EJ_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"EJ_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"ALLPAD_IN", _RIUA_16BIT(CHIPTOP_BANK,REG_ALLPAD_IN), REG_ALLPAD_IN_MASK}, ++ {"MIPI_PAD_IN_1", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, ++ {"MIPI_PAD_IN_2", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, ++ {"MIPI_PAD_IN_3", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, ++ {"TEST_IN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_OUT_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"I2C0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"SPI0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"FUART_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"UART0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"SD_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SD_MODE), REG_SD_MODE_MASK}, ++ {"SDIO_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SDIO_MODE), REG_SDIO_MODE_MASK}, ++ {"PWM0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM2_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM3_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM4_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM5_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM6_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM7_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM8_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM9_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM10_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"PWM10_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"PWM10_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"PWM10_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, ++ {"SR_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, ++ {"SR_MCLK_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MCLK_MODE), REG_SR_MCLK_MODE_MASK}, ++ {"SR_PDN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PDN_MODE), REG_SR_PDN_MODE_MASK}, ++ {"SR_PDN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PDN_MODE), REG_SR_PDN_MODE_MASK}, ++ {"SR_RST_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_RST_MODE), REG_SR_RST_MODE_MASK}, ++ {"SR_RST_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_RST_MODE), REG_SR_RST_MODE_MASK}, ++ {"SR_HVSYNC_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_HVSYNC_MODE), REG_SR_HVSYNC_MODE_MASK}, ++ {"SR_PCK_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PCK_MODE), REG_SR_PCK_MODE_MASK}, ++ {"ETH_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH_MODE), REG_ETH_MODE_MASK}, ++ {"I2S_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"I2S_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, ++ {"DMIC_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"CCIR_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, ++ {"CCIR_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, ++ {"CCIR_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, ++ // PM Sleep ++ {"PM_SPI_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_GPIO), REG_PM_SPI_GPIO_MASK}, ++ {"PM_SPIWPN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIWPN_GPIO), REG_PM_SPIWPN_GPIO_MASK}, ++ {"PM_SPIHOLDN_MODE",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIHOLDN_MODE), REG_PM_SPIHOLDN_MODE_MASK}, ++ {"PM_SPICSZ1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ1_GPIO), REG_PM_SPICSZ1_GPIO_MASK}, ++ {"PM_SPICSZ2_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_GPIO), REG_PM_SPICSZ2_GPIO_MASK}, ++ {"PM_PWM0_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM0_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM1_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, ++ {"PM_PWM1_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, ++ {"PM_PWM2_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, ++ {"PM_PWM2_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, ++ {"PM_PWM3_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, ++ {"PM_PWM3_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, ++ {"PM_PWM4_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM4_MODE), REG_PM_PWM4_MODE_MASK}, ++ {"PM_PWM5_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM5_MODE), REG_PM_PWM5_MODE_MASK}, ++ {"PM_PWM8_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM8_MODE), REG_PM_PWM8_MODE_MASK}, ++ {"PM_PWM9_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM9_MODE), REG_PM_PWM9_MODE_MASK}, ++ {"PM_PWM10_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM10_MODE), REG_PM_PWM10_MODE_MASK}, ++ {"PM_UART1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), REG_PM_UART1_MODE_MASK}, ++ {"PM_VID_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_3", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_SD_CDZ_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SD_CDZ_MODE), REG_PM_SD_CDZ_MODE_MASK}, ++ {"PM_LED_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, ++ {"PM_TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"PM_TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, ++ {"PM_IRIN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), REG_PM_IR_IS_GPIO_MASK}, ++ {"PM_SAR_MODE", _RIUA_16BIT(SAR_BANK,0x11), 0x3F}, ++ {"PM_USB_MODE", _RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK}, ++}; ++ ++//============================================================================== ++// ++// FUNCTIONS ++// ++//============================================================================== ++ ++//------------------------------------------------------------------------------ ++// Function : _HalCheckPin ++// Description : ++//------------------------------------------------------------------------------ ++static S32 _HalCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++static void _HalSARGPIOWriteRegBit(u32 u32RegOffset, bool bEnable, U8 u8BitMsk) ++{ ++ if (bEnable) ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) |= u8BitMsk; ++ else ++ _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) &= (~u8BitMsk); ++} ++ ++static void _HalPadDisablePadMux(U32 u32PadModeID) ++{ ++ if (_GPIO_R_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask)) { ++ _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, 0, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask); ++ } ++} ++ ++static S32 HalPadSetMode_General(U32 u32PadID, U32 u32Mode) ++{ ++ U32 u32RegAddr = 0; ++ U16 u16RegVal = 0; ++ U8 u8ModeIsFind = 0; ++ U16 i = 0; ++ ++ for (i = 0; i < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); i++) ++ { ++ if (u32PadID == m_stPadMuxTbl[i].padID) ++ { ++ u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[i].base, m_stPadMuxTbl[i].offset); ++ ++ if (u32Mode == m_stPadMuxTbl[i].mode) ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stPadMuxTbl[i].mask); ++ u16RegVal |= m_stPadMuxTbl[i].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ ++ u8ModeIsFind = 1; ++#if (ENABLE_CHECK_ALL_PAD_CONFLICT == 0) ++ break; ++#endif ++ } ++ else ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask); ++ ++ if (u16RegVal == m_stPadMuxTbl[i].val) ++ { ++ printk(KERN_INFO"[Padmux]reset PAD%d(reg 0x%x:%x; mask0x%x) t0 %s (org: %s)\n", ++ u32PadID, ++ m_stPadMuxTbl[i].base, ++ m_stPadMuxTbl[i].offset, ++ m_stPadMuxTbl[i].mask, ++ m_stPadModeInfoTbl[u32Mode].u8PadName, ++ m_stPadModeInfoTbl[m_stPadMuxTbl[i].mode].u8PadName); ++ if (m_stPadMuxTbl[i].val != 0) ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stPadMuxTbl[i].mask); ++ } ++ else ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask, m_stPadMuxTbl[i].mask); ++ } ++ } ++ } ++ } ++ } ++ ++ return (u8ModeIsFind) ? 0 : -1; ++} ++ ++static S32 HalPadSetMode_MISC(U32 u32PadID, U32 u32Mode) ++{ ++ switch(u32PadID) ++ { ++ /* PM_GPIO4 */ ++ case PAD_PM_GPIO4: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), 0, REG_TTL_MODE_MASK); ++ } ++ else if (u32Mode == REG_PM_UART1_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_TTL_MODE_1) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), BIT6, REG_TTL_MODE_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_TTL_MODE_2) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), BIT7, REG_TTL_MODE_MASK); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ ++ /* SAR */ ++ case PAD_SAR_GPIO0: /* reg_sar_aisel; reg[1422]#5 ~ #0=0b */ ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH0_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH0_AISEL, REG_SAR_CH0_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO1: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH1_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH1_AISEL, REG_SAR_CH1_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO2: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH2_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH2_AISEL, REG_SAR_CH2_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_SAR_GPIO3: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH3_AISEL); ++ } ++ else if (u32Mode == PINMUX_FOR_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH3_AISEL, REG_SAR_CH3_AISEL); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ ++ /* lan-top */ ++ case PAD_ETH_RN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT0, BIT0); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT0); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_ETH_RP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT1, BIT1); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT1); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_ETH_TN: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT2, BIT2); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT2); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ case PAD_ETH_TP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT3, BIT3); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT15); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT3); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ ++ /* UTMI */ ++ case PAD_USB_DM: ++ case PAD_USB_DP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE); ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), ~REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), ~REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), ~REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_USB_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), ~REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), ~REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), ~REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalPadSetVal ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetVal(U32 u32PadID, U32 u32Mode) ++{ ++ if (FALSE == _HalCheckPin(u32PadID)) { ++ return FALSE; ++ } ++ ++ if (u32PadID == PAD_PM_GPIO4 || ++ (u32PadID >= PAD_SAR_GPIO0 && u32PadID <= PAD_USB_DP)) ++ { ++ return HalPadSetMode_MISC(u32PadID, u32Mode); ++ } ++ else ++ { ++ return HalPadSetMode_General(u32PadID, u32Mode); ++ } ++} ++//------------------------------------------------------------------------------ ++// Function : HalPadSet ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetMode(U32 u32Mode) ++{ ++ U32 u32PadID; ++ U16 k = 0; ++ ++ for (k = 0; k < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); k++) ++ { ++ if (u32Mode == m_stPadMuxTbl[k].mode) ++ { ++ u32PadID = m_stPadMuxTbl[k].padID; ++ if (HalPadSetMode_General( u32PadID, u32Mode) < 0) ++ { ++ return -1; ++ } ++ } ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/gpio/infinity6b0/mhal_pinmux.h b/drivers/sstar/gpio/infinity6b0/mhal_pinmux.h +new file mode 100644 +index 000000000000..32594933c756 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6b0/mhal_pinmux.h +@@ -0,0 +1,9 @@ ++#ifndef __MHAL_PINMUX_H__ ++#define __MHAL_PINMUX_H__ ++ ++#include "mdrv_types.h" ++ ++extern S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++extern S32 HalPadSetMode(U32 u32Mode); ++ ++#endif // __MHAL_PINMUX_H__ +diff --git a/drivers/sstar/gpio/infinity6e/Makefile b/drivers/sstar/gpio/infinity6e/Makefile +new file mode 100644 +index 000000000000..01cd644f4e48 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6e/Makefile +@@ -0,0 +1,14 @@ ++# ++# Makefile for MStar GPIO device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mhal_gpio.o ++obj-$(CONFIG_MS_GPIO) += mhal_pinmux.o +diff --git a/drivers/sstar/gpio/infinity6e/mhal_gpio.c b/drivers/sstar/gpio/infinity6e/mhal_gpio.c +new file mode 100755 +index 000000000000..0287403e86ef +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6e/mhal_gpio.c +@@ -0,0 +1,1124 @@ ++/* ++* mhal_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++#include "padmux.h" ++#include "mhal_pinmux.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// PADTOP ++#define GPIO0_PAD PAD_PM_UART_RX1 ++#define GPIO0_OEN 0x3F32, BIT2 ++#define GPIO0_OUT 0x3F32, BIT1 ++#define GPIO0_IN 0x3F32, BIT0 ++#define GPIO0_PE 0x3F32, BIT4 ++ ++#define GPIO1_PAD PAD_PM_UART_TX1 ++#define GPIO1_OEN 0x3F40, BIT2 ++#define GPIO1_OUT 0x3F40, BIT1 ++#define GPIO1_IN 0x3F40, BIT0 ++#define GPIO1_PE 0x3F40, BIT4 ++ ++#define GPIO2_PAD PAD_PM_UART_RX ++#define GPIO2_OEN 0x3F42, BIT2 ++#define GPIO2_OUT 0x3F42, BIT1 ++#define GPIO2_IN 0x3F42, BIT0 ++#define GPIO2_PE 0x3F42, BIT4 ++ ++ ++#define GPIO3_PAD PAD_PM_UART_TX ++#define GPIO3_OEN 0x3F44, BIT2 ++#define GPIO3_OUT 0x3F44, BIT1 ++#define GPIO3_IN 0x3F44, BIT0 ++#define GPIO3_PE 0x3F44, BIT4 ++ ++#define GPIO4_PAD PAD_PM_I2CM_SCL ++#define GPIO4_OEN 0x3F22, BIT2 ++#define GPIO4_OUT 0x3F22, BIT1 ++#define GPIO4_IN 0x3F22, BIT0 ++#define GPIO4_PE 0x3F22, BIT4 ++ ++#define GPIO5_PAD PAD_PM_I2CM_SDA ++#define GPIO5_OEN 0x3F24, BIT2 ++#define GPIO5_OUT 0x3F24, BIT1 ++#define GPIO5_IN 0x3F24, BIT0 ++#define GPIO5_PE 0x3F24, BIT4 ++ ++#define GPIO6_PAD PAD_PM_GPIO0 ++#define GPIO6_OEN 0x3F00, BIT2 ++#define GPIO6_OUT 0x3F00, BIT1 ++#define GPIO6_IN 0x3F00, BIT0 ++#define GPIO6_PE 0x3F00, BIT4 ++ ++#define GPIO7_PAD PAD_PM_GPIO1 ++#define GPIO7_OEN 0x3F02, BIT2 ++#define GPIO7_OUT 0x3F02, BIT1 ++#define GPIO7_IN 0x3F02, BIT0 ++#define GPIO7_PE 0x3F02, BIT4 ++ ++#define GPIO8_PAD PAD_PM_GPIO2 ++#define GPIO8_OEN 0x3F04, BIT2 ++#define GPIO8_OUT 0x3F04, BIT1 ++#define GPIO8_IN 0x3F04, BIT0 ++#define GPIO8_PE 0x3F04, BIT4 ++ ++#define GPIO9_PAD PAD_PM_GPIO3 ++#define GPIO9_OEN 0x3F06, BIT2 ++#define GPIO9_OUT 0x3F06, BIT1 ++#define GPIO9_IN 0x3F06, BIT0 ++#define GPIO9_PE 0x3F06, BIT4 ++ ++#define GPIO10_PAD PAD_PM_GPIO4 ++#define GPIO10_OEN 0x3F08, BIT2 ++#define GPIO10_OUT 0x3F08, BIT1 ++#define GPIO10_IN 0x3F08, BIT0 ++#define GPIO10_PE 0x3F08, BIT4 ++ ++#define GPIO11_PAD PAD_PM_GPIO5 ++#define GPIO11_OEN 0x3F0A, BIT2 ++#define GPIO11_OUT 0x3F0A, BIT1 ++#define GPIO11_IN 0x3F0A, BIT0 ++#define GPIO11_PE 0x3F0A, BIT4 ++ ++#define GPIO12_PAD PAD_PM_GPIO6 ++#define GPIO12_OEN 0x3F0C, BIT2 ++#define GPIO12_OUT 0x3F0C, BIT1 ++#define GPIO12_IN 0x3F0C, BIT0 ++#define GPIO12_PE 0x3F0C, BIT4 ++ ++#define GPIO13_PAD PAD_PM_GPIO7 ++#define GPIO13_OEN 0x3F0E, BIT2 ++#define GPIO13_OUT 0x3F0E, BIT1 ++#define GPIO13_IN 0x3F0E, BIT0 ++#define GPIO13_PE 0x3F0E, BIT4 ++ ++#define GPIO14_PAD PAD_PM_GPIO8 ++#define GPIO14_OEN 0x3F10, BIT2 ++#define GPIO14_OUT 0x3F10, BIT1 ++#define GPIO14_IN 0x3F10, BIT0 ++#define GPIO14_PE 0x3F10, BIT4 ++ ++#define GPIO15_PAD PAD_PM_GPIO9 ++#define GPIO15_OEN 0x3F12, BIT2 ++#define GPIO15_OUT 0x3F12, BIT1 ++#define GPIO15_IN 0x3F12, BIT0 ++#define GPIO15_PE 0x3F12, BIT4 ++ ++#define GPIO16_PAD PAD_PM_GPIO10 ++#define GPIO16_OEN 0x3F20, BIT2 ++#define GPIO16_OUT 0x3F20, BIT1 ++#define GPIO16_IN 0x3F20, BIT0 ++#define GPIO16_PE 0x3F20, BIT4 ++ ++#define GPIO17_PAD PAD_PM_SPI_CZ ++#define GPIO17_OEN 0x3F26, BIT2 ++#define GPIO17_OUT 0x3F26, BIT1 ++#define GPIO17_IN 0x3F26, BIT0 ++#define GPIO17_PE 0x3F26, BIT4 ++ ++#define GPIO18_PAD PAD_PM_SPI_CK ++#define GPIO18_OEN 0x3F28, BIT2 ++#define GPIO18_OUT 0x3F28, BIT1 ++#define GPIO18_IN 0x3F28, BIT0 ++#define GPIO18_PE 0x3F28, BIT4 ++ ++#define GPIO19_PAD PAD_PM_SPI_DI ++#define GPIO19_OEN 0x3F2A, BIT2 ++#define GPIO19_OUT 0x3F2A, BIT1 ++#define GPIO19_IN 0x3F2A, BIT0 ++#define GPIO19_PE 0x3F2A, BIT4 ++ ++#define GPIO20_PAD PAD_PM_SPI_DO ++#define GPIO20_OEN 0x3F2C, BIT2 ++#define GPIO20_OUT 0x3F2C, BIT1 ++#define GPIO20_IN 0x3F2C, BIT0 ++#define GPIO20_PE 0x3F2C, BIT4 ++ ++#define GPIO21_PAD PAD_PM_SPI_WPZ ++#define GPIO21_OEN 0x3F2E, BIT2 ++#define GPIO21_OUT 0x3F2E, BIT1 ++#define GPIO21_IN 0x3F2E, BIT0 ++#define GPIO21_PE 0x3F2E, BIT4 ++ ++#define GPIO22_PAD PAD_PM_SPI_HLD ++#define GPIO22_OEN 0x3F30, BIT2 ++#define GPIO22_OUT 0x3F30, BIT1 ++#define GPIO22_IN 0x3F30, BIT0 ++#define GPIO22_PE 0x3F30, BIT4 ++ ++#define GPIO23_PAD PAD_SAR_GPIO0 ++#define GPIO23_OEN 0x1423, BIT0 ++#define GPIO23_OUT 0x1424, BIT0 ++#define GPIO23_IN 0x1425, BIT0 ++#define GPIO23_PE 0x0000, BIT4 ++ ++#define GPIO24_PAD PAD_SAR_GPIO1 ++#define GPIO24_OEN 0x1423, BIT1 ++#define GPIO24_OUT 0x1424, BIT1 ++#define GPIO24_IN 0x1425, BIT1 ++#define GPIO24_PE 0x0000, BIT4 ++ ++#define GPIO25_PAD PAD_SAR_GPIO2 ++#define GPIO25_OEN 0x1423, BIT2 ++#define GPIO25_OUT 0x1424, BIT2 ++#define GPIO25_IN 0x1425, BIT2 ++#define GPIO25_PE 0x0000, BIT4 ++ ++#define GPIO26_PAD PAD_SAR_GPIO3 ++#define GPIO26_OEN 0x1423, BIT3 ++#define GPIO26_OUT 0x1424, BIT3 ++#define GPIO26_IN 0x1425, BIT3 ++#define GPIO26_PE 0x0000, BIT4 ++ ++#define GPIO27_PAD PAD_SAR_GPIO4 ++#define GPIO27_OEN 0x1423, BIT4 ++#define GPIO27_OUT 0x1424, BIT4 ++#define GPIO27_IN 0x1425, BIT4 ++#define GPIO27_PE 0x0000, BIT4 ++ ++#define GPIO28_PAD PAD_SAR_GPIO5 ++#define GPIO28_OEN 0x1423, BIT5 ++#define GPIO28_OUT 0x1424, BIT5 ++#define GPIO28_IN 0x1425, BIT5 ++#define GPIO28_PE 0x0000, BIT4 ++ ++#define GPIO29_PAD PAD_SD0_GPIO0 ++#define GPIO29_OEN 0x103C20, BIT2 ++#define GPIO29_OUT 0x103C20, BIT1 ++#define GPIO29_IN 0x103C20, BIT0 ++#define GPIO29_PE 0x103C20, BIT4 ++ ++#define GPIO30_PAD PAD_SD0_CDZ ++#define GPIO30_OEN 0x103C22, BIT2 ++#define GPIO30_OUT 0x103C22, BIT1 ++#define GPIO30_IN 0x103C22, BIT0 ++#define GPIO30_PE 0x103C22, BIT4 ++ ++#define GPIO31_PAD PAD_SD0_D1 ++#define GPIO31_OEN 0x103C24, BIT2 ++#define GPIO31_OUT 0x103C24, BIT1 ++#define GPIO31_IN 0x103C24, BIT0 ++#define GPIO31_PE 0x103C24, BIT4 ++ ++#define GPIO32_PAD PAD_SD0_D0 ++#define GPIO32_OEN 0x103C26, BIT2 ++#define GPIO32_OUT 0x103C26, BIT1 ++#define GPIO32_IN 0x103C26, BIT0 ++#define GPIO32_PE 0x103C26, BIT4 ++ ++#define GPIO33_PAD PAD_SD0_CLK ++#define GPIO33_OEN 0x103C28, BIT2 ++#define GPIO33_OUT 0x103C28, BIT1 ++#define GPIO33_IN 0x103C28, BIT0 ++#define GPIO33_PE 0x103C28, BIT4 ++ ++#define GPIO34_PAD PAD_SD0_CMD ++#define GPIO34_OEN 0x103C2A, BIT2 ++#define GPIO34_OUT 0x103C2A, BIT1 ++#define GPIO34_IN 0x103C2A, BIT0 ++#define GPIO34_PE 0x103C2A, BIT4 ++ ++#define GPIO35_PAD PAD_SD0_D3 ++#define GPIO35_OEN 0x103C2C, BIT2 ++#define GPIO35_OUT 0x103C2C, BIT1 ++#define GPIO35_IN 0x103C2C, BIT0 ++#define GPIO35_PE 0x103C2C, BIT4 ++ ++#define GPIO36_PAD PAD_SD0_D2 ++#define GPIO36_OEN 0x103C2E, BIT2 ++#define GPIO36_OUT 0x103C2E, BIT1 ++#define GPIO36_IN 0x103C2E, BIT0 ++#define GPIO36_PE 0x103C2E, BIT4 ++ ++#define GPIO37_PAD PAD_I2S0_MCLK ++#define GPIO37_OEN 0x103C30, BIT2 ++#define GPIO37_OUT 0x103C30, BIT1 ++#define GPIO37_IN 0x103C30, BIT0 ++#define GPIO37_PE 0x103C30, BIT4 ++ ++#define GPIO38_PAD PAD_I2S0_BCK ++#define GPIO38_OEN 0x103C32, BIT2 ++#define GPIO38_OUT 0x103C32, BIT1 ++#define GPIO38_IN 0x103C32, BIT0 ++#define GPIO38_PE 0x103C32, BIT4 ++ ++#define GPIO39_PAD PAD_I2S0_WCK ++#define GPIO39_OEN 0x103C34, BIT2 ++#define GPIO39_OUT 0x103C34, BIT1 ++#define GPIO39_IN 0x103C34, BIT0 ++#define GPIO39_PE 0x103C34, BIT4 ++ ++#define GPIO40_PAD PAD_I2S0_DI ++#define GPIO40_OEN 0x103C36, BIT2 ++#define GPIO40_OUT 0x103C36, BIT1 ++#define GPIO40_IN 0x103C36, BIT0 ++#define GPIO40_PE 0x103C36, BIT4 ++ ++#define GPIO41_PAD PAD_I2S0_DO ++#define GPIO41_OEN 0x103C38, BIT2 ++#define GPIO41_OUT 0x103C38, BIT1 ++#define GPIO41_IN 0x103C38, BIT0 ++#define GPIO41_PE 0x103C38, BIT4 ++ ++#define GPIO42_PAD PAD_I2C0_SCL ++#define GPIO42_OEN 0x103C3A, BIT2 ++#define GPIO42_OUT 0x103C3A, BIT1 ++#define GPIO42_IN 0x103C3A, BIT0 ++#define GPIO42_PE 0x103C3A, BIT4 ++ ++#define GPIO43_PAD PAD_I2C0_SDA ++#define GPIO43_OEN 0x103C3C, BIT2 ++#define GPIO43_OUT 0x103C3C, BIT1 ++#define GPIO43_IN 0x103C3C, BIT0 ++#define GPIO43_PE 0x103C3C, BIT4 ++ ++#define GPIO44_PAD PAD_ETH_LED0 ++#define GPIO44_OEN 0x103C40, BIT2 ++#define GPIO44_OUT 0x103C40, BIT1 ++#define GPIO44_IN 0x103C40, BIT0 ++#define GPIO44_PE 0x103C40, BIT4 ++ ++#define GPIO45_PAD PAD_ETH_LED1 ++#define GPIO45_OEN 0x103C42, BIT2 ++#define GPIO45_OUT 0x103C42, BIT1 ++#define GPIO45_IN 0x103C42, BIT0 ++#define GPIO45_PE 0x103C42, BIT4 ++ ++#define GPIO46_PAD PAD_FUART_RX ++#define GPIO46_OEN 0x103C44, BIT2 ++#define GPIO46_OUT 0x103C44, BIT1 ++#define GPIO46_IN 0x103C44, BIT0 ++#define GPIO46_PE 0x103C44, BIT4 ++ ++#define GPIO47_PAD PAD_FUART_TX ++#define GPIO47_OEN 0x103C46, BIT2 ++#define GPIO47_OUT 0x103C46, BIT1 ++#define GPIO47_IN 0x103C46, BIT0 ++#define GPIO47_PE 0x103C46, BIT4 ++ ++#define GPIO48_PAD PAD_FUART_CTS ++#define GPIO48_OEN 0x103C48, BIT2 ++#define GPIO48_OUT 0x103C48, BIT1 ++#define GPIO48_IN 0x103C48, BIT0 ++#define GPIO48_PE 0x103C48, BIT4 ++ ++#define GPIO49_PAD PAD_FUART_RTS ++#define GPIO49_OEN 0x103C4A, BIT2 ++#define GPIO49_OUT 0x103C4A, BIT1 ++#define GPIO49_IN 0x103C4A, BIT0 ++#define GPIO49_PE 0x103C4A, BIT4 ++ ++#define GPIO50_PAD PAD_SD1_CDZ ++#define GPIO50_OEN 0x103C4C, BIT2 ++#define GPIO50_OUT 0x103C4C, BIT1 ++#define GPIO50_IN 0x103C4C, BIT0 ++#define GPIO50_PE 0x103C4C, BIT4 ++ ++#define GPIO51_PAD PAD_SD1_D1 ++#define GPIO51_OEN 0x103C4E, BIT2 ++#define GPIO51_OUT 0x103C4E, BIT1 ++#define GPIO51_IN 0x103C4E, BIT0 ++#define GPIO51_PE 0x103C4E, BIT4 ++ ++#define GPIO52_PAD PAD_SD1_D0 ++#define GPIO52_OEN 0x103C50, BIT2 ++#define GPIO52_OUT 0x103C50, BIT1 ++#define GPIO52_IN 0x103C50, BIT0 ++#define GPIO52_PE 0x103C50, BIT4 ++ ++#define GPIO53_PAD PAD_SD1_CLK ++#define GPIO53_OEN 0x103C52, BIT2 ++#define GPIO53_OUT 0x103C52, BIT1 ++#define GPIO53_IN 0x103C52, BIT0 ++#define GPIO53_PE 0x103C52, BIT4 ++ ++#define GPIO54_PAD PAD_SD1_CMD ++#define GPIO54_OEN 0x103C54, BIT2 ++#define GPIO54_OUT 0x103C54, BIT1 ++#define GPIO54_IN 0x103C54, BIT0 ++#define GPIO54_PE 0x103C54, BIT4 ++ ++#define GPIO55_PAD PAD_SD1_D3 ++#define GPIO55_OEN 0x103C56, BIT2 ++#define GPIO55_OUT 0x103C56, BIT1 ++#define GPIO55_IN 0x103C56, BIT0 ++#define GPIO55_PE 0x103C56, BIT4 ++ ++#define GPIO56_PAD PAD_SD1_D2 ++#define GPIO56_OEN 0x103C58, BIT2 ++#define GPIO56_OUT 0x103C58, BIT1 ++#define GPIO56_IN 0x103C58, BIT0 ++#define GPIO56_PE 0x103C58, BIT4 ++ ++#define GPIO57_PAD PAD_SD1_GPIO0 ++#define GPIO57_OEN 0x103C5A, BIT2 ++#define GPIO57_OUT 0x103C5A, BIT1 ++#define GPIO57_IN 0x103C5A, BIT0 ++#define GPIO57_PE 0x103C5A, BIT4 ++ ++#define GPIO58_PAD PAD_SD1_GPIO1 ++#define GPIO58_OEN 0x103C5C, BIT2 ++#define GPIO58_OUT 0x103C5C, BIT1 ++#define GPIO58_IN 0x103C5C, BIT0 ++#define GPIO58_PE 0x103C5C, BIT4 ++ ++#define GPIO59_PAD PAD_GPIO0 ++#define GPIO59_OEN 0x103C00, BIT2 ++#define GPIO59_OUT 0x103C00, BIT1 ++#define GPIO59_IN 0x103C00, BIT0 ++#define GPIO59_PE 0x103C00, BIT4 ++ ++#define GPIO60_PAD PAD_GPIO1 ++#define GPIO60_OEN 0x103C02, BIT2 ++#define GPIO60_OUT 0x103C02, BIT1 ++#define GPIO60_IN 0x103C02, BIT0 ++#define GPIO60_PE 0x103C02, BIT4 ++ ++#define GPIO61_PAD PAD_GPIO2 ++#define GPIO61_OEN 0x103C04, BIT2 ++#define GPIO61_OUT 0x103C04, BIT1 ++#define GPIO61_IN 0x103C04, BIT0 ++#define GPIO61_PE 0x103C04, BIT4 ++ ++#define GPIO62_PAD PAD_GPIO3 ++#define GPIO62_OEN 0x103C06, BIT2 ++#define GPIO62_OUT 0x103C06, BIT1 ++#define GPIO62_IN 0x103C06, BIT0 ++#define GPIO62_PE 0x103C06, BIT4 ++ ++#define GPIO63_PAD PAD_GPIO4 ++#define GPIO63_OEN 0x103C08, BIT2 ++#define GPIO63_OUT 0x103C08, BIT1 ++#define GPIO63_IN 0x103C08, BIT0 ++#define GPIO63_PE 0x103C08, BIT4 ++ ++#define GPIO64_PAD PAD_GPIO5 ++#define GPIO64_OEN 0x103C0A, BIT2 ++#define GPIO64_OUT 0x103C0A, BIT1 ++#define GPIO64_IN 0x103C0A, BIT0 ++#define GPIO64_PE 0x103C0A, BIT4 ++ ++#define GPIO65_PAD PAD_GPIO6 ++#define GPIO65_OEN 0x103C0C, BIT2 ++#define GPIO65_OUT 0x103C0C, BIT1 ++#define GPIO65_IN 0x103C0C, BIT0 ++#define GPIO65_PE 0x103C0C, BIT4 ++ ++#define GPIO66_PAD PAD_GPIO7 ++#define GPIO66_OEN 0x103C0E, BIT2 ++#define GPIO66_OUT 0x103C0E, BIT1 ++#define GPIO66_IN 0x103C0E, BIT0 ++#define GPIO66_PE 0x103C0E, BIT4 ++ ++#define GPIO67_PAD PAD_SR0_IO00 ++#define GPIO67_OEN 0x103C6C, BIT2 ++#define GPIO67_OUT 0x103C6C, BIT1 ++#define GPIO67_IN 0x103C6C, BIT0 ++#define GPIO67_PE 0x103C6C, BIT4 ++ ++#define GPIO68_PAD PAD_SR0_IO01 ++#define GPIO68_OEN 0x103C6E, BIT2 ++#define GPIO68_OUT 0x103C6E, BIT1 ++#define GPIO68_IN 0x103C6E, BIT0 ++#define GPIO68_PE 0x103C6E, BIT4 ++ ++#define GPIO69_PAD PAD_SR0_IO02 ++#define GPIO69_OEN 0x103C70, BIT2 ++#define GPIO69_OUT 0x103C70, BIT1 ++#define GPIO69_IN 0x103C70, BIT0 ++#define GPIO69_PE 0x103C70, BIT4 ++ ++#define GPIO70_PAD PAD_SR0_IO03 ++#define GPIO70_OEN 0x103C72, BIT2 ++#define GPIO70_OUT 0x103C72, BIT1 ++#define GPIO70_IN 0x103C72, BIT0 ++#define GPIO70_PE 0x103C72, BIT4 ++ ++#define GPIO71_PAD PAD_SR0_IO04 ++#define GPIO71_OEN 0x103C74, BIT2 ++#define GPIO71_OUT 0x103C74, BIT1 ++#define GPIO71_IN 0x103C74, BIT0 ++#define GPIO71_PE 0x103C74, BIT4 ++ ++#define GPIO72_PAD PAD_SR0_IO05 ++#define GPIO72_OEN 0x103C76, BIT2 ++#define GPIO72_OUT 0x103C76, BIT1 ++#define GPIO72_IN 0x103C76, BIT0 ++#define GPIO72_PE 0x103C76, BIT4 ++ ++#define GPIO73_PAD PAD_SR0_IO06 ++#define GPIO73_OEN 0x103C78, BIT2 ++#define GPIO73_OUT 0x103C78, BIT1 ++#define GPIO73_IN 0x103C78, BIT0 ++#define GPIO73_PE 0x103C78, BIT4 ++ ++#define GPIO74_PAD PAD_SR0_IO07 ++#define GPIO74_OEN 0x103C7A, BIT2 ++#define GPIO74_OUT 0x103C7A, BIT1 ++#define GPIO74_IN 0x103C7A, BIT0 ++#define GPIO74_PE 0x103C7A, BIT4 ++ ++#define GPIO75_PAD PAD_SR0_IO08 ++#define GPIO75_OEN 0x103C7C, BIT2 ++#define GPIO75_OUT 0x103C7C, BIT1 ++#define GPIO75_IN 0x103C7C, BIT0 ++#define GPIO75_PE 0x103C7C, BIT4 ++ ++#define GPIO76_PAD PAD_SR0_IO09 ++#define GPIO76_OEN 0x103C7E, BIT2 ++#define GPIO76_OUT 0x103C7E, BIT1 ++#define GPIO76_IN 0x103C7E, BIT0 ++#define GPIO76_PE 0x103C7E, BIT4 ++ ++#define GPIO77_PAD PAD_SR0_IO10 ++#define GPIO77_OEN 0x103C80, BIT2 ++#define GPIO77_OUT 0x103C80, BIT1 ++#define GPIO77_IN 0x103C80, BIT0 ++#define GPIO77_PE 0x103C80, BIT4 ++ ++#define GPIO78_PAD PAD_SR0_IO11 ++#define GPIO78_OEN 0x103C82, BIT2 ++#define GPIO78_OUT 0x103C82, BIT1 ++#define GPIO78_IN 0x103C82, BIT0 ++#define GPIO78_PE 0x103C82, BIT4 ++ ++#define GPIO79_PAD PAD_SR0_IO12 ++#define GPIO79_OEN 0x103C84, BIT2 ++#define GPIO79_OUT 0x103C84, BIT1 ++#define GPIO79_IN 0x103C84, BIT0 ++#define GPIO79_PE 0x103C84, BIT4 ++ ++#define GPIO80_PAD PAD_SR0_IO13 ++#define GPIO80_OEN 0x103C86, BIT2 ++#define GPIO80_OUT 0x103C86, BIT1 ++#define GPIO80_IN 0x103C86, BIT0 ++#define GPIO80_PE 0x103C86, BIT4 ++ ++#define GPIO81_PAD PAD_SR0_IO14 ++#define GPIO81_OEN 0x103C88, BIT2 ++#define GPIO81_OUT 0x103C88, BIT1 ++#define GPIO81_IN 0x103C88, BIT0 ++#define GPIO81_PE 0x103C88, BIT4 ++ ++#define GPIO82_PAD PAD_SR0_IO15 ++#define GPIO82_OEN 0x103C8A, BIT2 ++#define GPIO82_OUT 0x103C8A, BIT1 ++#define GPIO82_IN 0x103C8A, BIT0 ++#define GPIO82_PE 0x103C8A, BIT4 ++ ++#define GPIO83_PAD PAD_SR0_IO16 ++#define GPIO83_OEN 0x103C8C, BIT2 ++#define GPIO83_OUT 0x103C8C, BIT1 ++#define GPIO83_IN 0x103C8C, BIT0 ++#define GPIO83_PE 0x103C8C, BIT4 ++ ++#define GPIO84_PAD PAD_SR0_IO17 ++#define GPIO84_OEN 0x103C8E, BIT2 ++#define GPIO84_OUT 0x103C8E, BIT1 ++#define GPIO84_IN 0x103C8E, BIT0 ++#define GPIO84_PE 0x103C8E, BIT4 ++ ++#define GPIO85_PAD PAD_SR0_IO18 ++#define GPIO85_OEN 0x103C90, BIT2 ++#define GPIO85_OUT 0x103C90, BIT1 ++#define GPIO85_IN 0x103C90, BIT0 ++#define GPIO85_PE 0x103C90, BIT4 ++ ++#define GPIO86_PAD PAD_SR0_IO19 ++#define GPIO86_OEN 0x103C92, BIT2 ++#define GPIO86_OUT 0x103C92, BIT1 ++#define GPIO86_IN 0x103C92, BIT0 ++#define GPIO86_PE 0x103C92, BIT4 ++ ++#define GPIO87_PAD PAD_SR1_IO00 ++#define GPIO87_OEN 0x103C94, BIT2 ++#define GPIO87_OUT 0x103C94, BIT1 ++#define GPIO87_IN 0x103C94, BIT0 ++#define GPIO87_PE 0x103C94, BIT4 ++ ++#define GPIO88_PAD PAD_SR1_IO01 ++#define GPIO88_OEN 0x103C96, BIT2 ++#define GPIO88_OUT 0x103C96, BIT1 ++#define GPIO88_IN 0x103C96, BIT0 ++#define GPIO88_PE 0x103C96, BIT4 ++ ++#define GPIO89_PAD PAD_SR1_IO02 ++#define GPIO89_OEN 0x103C98, BIT2 ++#define GPIO89_OUT 0x103C98, BIT1 ++#define GPIO89_IN 0x103C98, BIT0 ++#define GPIO89_PE 0x103C98, BIT4 ++ ++#define GPIO90_PAD PAD_SR1_IO03 ++#define GPIO90_OEN 0x103C9A, BIT2 ++#define GPIO90_OUT 0x103C9A, BIT1 ++#define GPIO90_IN 0x103C9A, BIT0 ++#define GPIO90_PE 0x103C9A, BIT4 ++ ++#define GPIO91_PAD PAD_SR1_IO04 ++#define GPIO91_OEN 0x103C9C, BIT2 ++#define GPIO91_OUT 0x103C9C, BIT1 ++#define GPIO91_IN 0x103C9C, BIT0 ++#define GPIO91_PE 0x103C9C, BIT4 ++ ++#define GPIO92_PAD PAD_SR1_IO05 ++#define GPIO92_OEN 0x103C9E, BIT2 ++#define GPIO92_OUT 0x103C9E, BIT1 ++#define GPIO92_IN 0x103C9E, BIT0 ++#define GPIO92_PE 0x103C9E, BIT4 ++ ++#define GPIO93_PAD PAD_SR1_IO06 ++#define GPIO93_OEN 0x103CA0, BIT2 ++#define GPIO93_OUT 0x103CA0, BIT1 ++#define GPIO93_IN 0x103CA0, BIT0 ++#define GPIO93_PE 0x103CA0, BIT4 ++ ++#define GPIO94_PAD PAD_SR1_IO07 ++#define GPIO94_OEN 0x103CA2, BIT2 ++#define GPIO94_OUT 0x103CA2, BIT1 ++#define GPIO94_IN 0x103CA2, BIT0 ++#define GPIO94_PE 0x103CA2, BIT4 ++ ++#define GPIO95_PAD PAD_SR1_IO08 ++#define GPIO95_OEN 0x103CA4, BIT2 ++#define GPIO95_OUT 0x103CA4, BIT1 ++#define GPIO95_IN 0x103CA4, BIT0 ++#define GPIO95_PE 0x103CA4, BIT4 ++ ++#define GPIO96_PAD PAD_SR1_IO09 ++#define GPIO96_OEN 0x103CA6, BIT2 ++#define GPIO96_OUT 0x103CA6, BIT1 ++#define GPIO96_IN 0x103CA6, BIT0 ++#define GPIO96_PE 0x103CA6, BIT4 ++ ++#define GPIO97_PAD PAD_SR1_IO10 ++#define GPIO97_OEN 0x103CA8, BIT2 ++#define GPIO97_OUT 0x103CA8, BIT1 ++#define GPIO97_IN 0x103CA8, BIT0 ++#define GPIO97_PE 0x103CA8, BIT4 ++ ++#define GPIO98_PAD PAD_SR1_IO11 ++#define GPIO98_OEN 0x103CAA, BIT2 ++#define GPIO98_OUT 0x103CAA, BIT1 ++#define GPIO98_IN 0x103CAA, BIT0 ++#define GPIO98_PE 0x103CAA, BIT4 ++ ++#define GPIO99_PAD PAD_SR1_IO12 ++#define GPIO99_OEN 0x103CAC, BIT2 ++#define GPIO99_OUT 0x103CAC, BIT1 ++#define GPIO99_IN 0x103CAC, BIT0 ++#define GPIO99_PE 0x103CAC, BIT4 ++ ++#define GPIO100_PAD PAD_SR1_IO13 ++#define GPIO100_OEN 0x103CAE, BIT2 ++#define GPIO100_OUT 0x103CAE, BIT1 ++#define GPIO100_IN 0x103CAE, BIT0 ++#define GPIO100_PE 0x103CAE, BIT4 ++ ++#define GPIO101_PAD PAD_SR1_IO14 ++#define GPIO101_OEN 0x103CB0, BIT2 ++#define GPIO101_OUT 0x103CB0, BIT1 ++#define GPIO101_IN 0x103CB0, BIT0 ++#define GPIO101_PE 0x103CB0, BIT4 ++ ++#define GPIO102_PAD PAD_SR1_IO15 ++#define GPIO102_OEN 0x103CB2, BIT2 ++#define GPIO102_OUT 0x103CB2, BIT1 ++#define GPIO102_IN 0x103CB2, BIT0 ++#define GPIO102_PE 0x103CB2, BIT4 ++ ++#define GPIO103_PAD PAD_SR1_IO16 ++#define GPIO103_OEN 0x103CB4, BIT2 ++#define GPIO103_OUT 0x103CB4, BIT1 ++#define GPIO103_IN 0x103CB4, BIT0 ++#define GPIO103_PE 0x103CB4, BIT4 ++ ++#define GPIO104_PAD PAD_SR1_IO17 ++#define GPIO104_OEN 0x103CB6, BIT2 ++#define GPIO104_OUT 0x103CB6, BIT1 ++#define GPIO104_IN 0x103CB6, BIT0 ++#define GPIO104_PE 0x103CB6, BIT4 ++ ++#define GPIO105_PAD PAD_SR1_IO18 ++#define GPIO105_OEN 0x103CB8, BIT2 ++#define GPIO105_OUT 0x103CB8, BIT1 ++#define GPIO105_IN 0x103CB8, BIT0 ++#define GPIO105_PE 0x103CB8, BIT4 ++ ++#define GPIO106_PAD PAD_SR1_IO19 ++#define GPIO106_OEN 0x103CBA, BIT2 ++#define GPIO106_OUT 0x103CBA, BIT1 ++#define GPIO106_IN 0x103CBA, BIT0 ++#define GPIO106_PE 0x103CBA, BIT4 ++ ++#define GPIO107_PAD PAD_GPIO8 ++#define GPIO107_OEN 0x103C10, BIT2 ++#define GPIO107_OUT 0x103C10, BIT1 ++#define GPIO107_IN 0x103C10, BIT0 ++#define GPIO107_PE 0x103C10, BIT4 ++ ++#define GPIO108_PAD PAD_GPIO9 ++#define GPIO108_OEN 0x103C12, BIT2 ++#define GPIO108_OUT 0x103C12, BIT1 ++#define GPIO108_IN 0x103C12, BIT0 ++#define GPIO108_PE 0x103C12, BIT4 ++ ++#define GPIO109_PAD PAD_GPIO10 ++#define GPIO109_OEN 0x103C14, BIT2 ++#define GPIO109_OUT 0x103C14, BIT1 ++#define GPIO109_IN 0x103C14, BIT0 ++#define GPIO109_PE 0x103C14, BIT4 ++ ++#define GPIO110_PAD PAD_GPIO11 ++#define GPIO110_OEN 0x103C16, BIT2 ++#define GPIO110_OUT 0x103C16, BIT1 ++#define GPIO110_IN 0x103C16, BIT0 ++#define GPIO110_PE 0x103C16, BIT4 ++ ++#define GPIO111_PAD PAD_GPIO12 ++#define GPIO111_OEN 0x103C18, BIT2 ++#define GPIO111_OUT 0x103C18, BIT1 ++#define GPIO111_IN 0x103C18, BIT0 ++#define GPIO111_PE 0x103C18, BIT4 ++ ++#define GPIO112_PAD PAD_GPIO13 ++#define GPIO112_OEN 0x103C1A, BIT2 ++#define GPIO112_OUT 0x103C1A, BIT1 ++#define GPIO112_IN 0x103C1A, BIT0 ++#define GPIO112_PE 0x103C1A, BIT4 ++ ++#define GPIO113_PAD PAD_GPIO14 ++#define GPIO113_OEN 0x103C1C, BIT2 ++#define GPIO113_OUT 0x103C1C, BIT1 ++#define GPIO113_IN 0x103C1C, BIT0 ++#define GPIO113_PE 0x103C1C, BIT4 ++ ++#define GPIO114_PAD PAD_GPIO15 ++#define GPIO114_OEN 0x103C1E, BIT2 ++#define GPIO114_OUT 0x103C1E, BIT1 ++#define GPIO114_IN 0x103C1E, BIT0 ++#define GPIO114_PE 0x103C1E, BIT4 ++ ++#define GPIO115_PAD PAD_SPI_CZ ++#define GPIO115_OEN 0x103C60, BIT2 ++#define GPIO115_OUT 0x103C60, BIT1 ++#define GPIO115_IN 0x103C60, BIT0 ++#define GPIO115_PE 0x103C60, BIT4 ++ ++#define GPIO116_PAD PAD_SPI_CK ++#define GPIO116_OEN 0x103C62, BIT2 ++#define GPIO116_OUT 0x103C62, BIT1 ++#define GPIO116_IN 0x103C62, BIT0 ++#define GPIO116_PE 0x103C62, BIT4 ++ ++#define GPIO117_PAD PAD_SPI_DI ++#define GPIO117_OEN 0x103C64, BIT2 ++#define GPIO117_OUT 0x103C64, BIT1 ++#define GPIO117_IN 0x103C64, BIT0 ++#define GPIO117_PE 0x103C64, BIT4 ++ ++#define GPIO118_PAD PAD_SPI_DO ++#define GPIO118_OEN 0x103C66, BIT2 ++#define GPIO118_OUT 0x103C66, BIT1 ++#define GPIO118_IN 0x103C66, BIT0 ++#define GPIO118_PE 0x103C66, BIT4 ++ ++#define GPIO119_PAD PAD_SPI_WPZ ++#define GPIO119_OEN 0x103C68, BIT2 ++#define GPIO119_OUT 0x103C68, BIT1 ++#define GPIO119_IN 0x103C68, BIT0 ++#define GPIO119_PE 0x103C68, BIT4 ++ ++#define GPIO120_PAD PAD_SPI_HLD ++#define GPIO120_OEN 0x103C6A, BIT2 ++#define GPIO120_OUT 0x103C6A, BIT1 ++#define GPIO120_IN 0x103C6A, BIT0 ++#define GPIO120_PE 0x103C6A, BIT4 ++ ++#define GPIO121_PAD PAD_ETH_RN ++#define GPIO121_OEN 0x1516E2, BIT4 ++#define GPIO121_OUT 0x1516E4, BIT0 ++#define GPIO121_IN 0x1516E4, BIT4 ++#define GPIO121_PE 0x000000, BIT4 ++ ++#define GPIO122_PAD PAD_ETH_RP ++#define GPIO122_OEN 0x1516E2, BIT5 ++#define GPIO122_OUT 0x1516E4, BIT1 ++#define GPIO122_IN 0x1516E4, BIT5 ++#define GPIO122_PE 0x000000, BIT4 ++ ++#define GPIO123_PAD PAD_ETH_TN ++#define GPIO123_OEN 0x1516E2, BIT6 ++#define GPIO123_OUT 0x1516E4, BIT2 ++#define GPIO123_IN 0x1516E4, BIT6 ++#define GPIO123_PE 0x000000, BIT4 ++ ++#define GPIO124_PAD PAD_ETH_TP ++#define GPIO124_OEN 0x1516E2, BIT7 ++#define GPIO124_OUT 0x1516E4, BIT3 ++#define GPIO124_IN 0x1516E4, BIT7 ++#define GPIO124_PE 0x000000, BIT4 ++ ++#define GPIO125_PAD PAD_USB2_DM ++#define GPIO125_OEN 0x14210a, BIT4 ++#define GPIO125_OUT 0x14210a, BIT2 ++#define GPIO125_IN 0x142131, BIT5 ++#define GPIO125_PE 0x000000, BIT4 ++ ++#define GPIO126_PAD PAD_USB2_DP ++#define GPIO126_OEN 0x14210a, BIT5 ++#define GPIO126_OUT 0x14210a, BIT3 ++#define GPIO126_IN 0x142131, BIT4 ++#define GPIO126_PE 0x000000, BIT4 ++ ++ ++U32 gChipBaseAddr = 0xFD203C00; ++U32 gPmSleepBaseAddr = 0xFD001C00; ++U32 gSarBaseAddr = 0xFD002800; ++U32 gRIUBaseAddr = 0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++#define REG_ALL_PAD_IN 0xA1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++static int _pmsleep_to_irq_table[] = { ++ //INT_PMSLEEP_SD_CDZ, ++ //INT_PMSLEEP_IRIN, ++ INT_PMSLEEP_UART_RX1, ++ INT_PMSLEEP_UART_TX1, ++ INT_PMSLEEP_UART_RX, ++ INT_PMSLEEP_UART_TX, ++ INT_PMSLEEP_I2CM_SCL, ++ INT_PMSLEEP_I2CM_SDA, ++ INT_PMSLEEP_GPIO_0, ++ INT_PMSLEEP_GPIO_1, ++ INT_PMSLEEP_GPIO_2, ++ INT_PMSLEEP_GPIO_3, ++ INT_PMSLEEP_GPIO_4, ++ INT_PMSLEEP_GPIO_5, ++ INT_PMSLEEP_GPIO_6, ++ INT_PMSLEEP_GPIO_7, ++ INT_PMSLEEP_GPIO_8, ++ INT_PMSLEEP_GPIO_9, ++ INT_PMSLEEP_GPIO_10, ++ INT_PMSLEEP_SPI_CZ, ++ INT_PMSLEEP_SPI_CK, ++ INT_PMSLEEP_SPI_DI, ++ INT_PMSLEEP_SPI_DO, ++ INT_PMSLEEP_SPI_WPZ, ++ INT_PMSLEEP_SPI_HLD, ++ INT_PMSLEEP_SAR_GPIO0, ++ INT_PMSLEEP_SAR_GPIO1, ++ INT_PMSLEEP_SAR_GPIO2, ++ INT_PMSLEEP_SAR_GPIO3, ++ INT_PMSLEEP_SAR_GPIO4, ++ INT_PMSLEEP_SAR_GPIO5, ++}; ++ ++static int _gpi_to_irq_table[] = { ++ INT_GPI_FIQ_PAD_SD0_GPIO0, ++ INT_GPI_FIQ_PAD_SD0_CDZ, ++ INT_GPI_FIQ_PAD_SD0_D1, ++ INT_GPI_FIQ_PAD_SD0_D0, ++ INT_GPI_FIQ_PAD_SD0_CLK, ++ INT_GPI_FIQ_PAD_SD0_CMD, ++ INT_GPI_FIQ_PAD_SD0_D3, ++ INT_GPI_FIQ_PAD_SD0_D2, ++ INT_GPI_FIQ_PAD_I2S0_MCLK, ++ INT_GPI_FIQ_PAD_I2S0_BCK, ++ INT_GPI_FIQ_PAD_I2S0_WCK, ++ INT_GPI_FIQ_PAD_I2S0_DI, ++ INT_GPI_FIQ_PAD_I2S0_DO, ++ INT_GPI_FIQ_PAD_I2C0_SCL, ++ INT_GPI_FIQ_PAD_I2C0_SDA, ++ INT_GPI_FIQ_PAD_ETH_LED0, ++ INT_GPI_FIQ_PAD_ETH_LED1, ++ INT_GPI_FIQ_PAD_FUART_RX, ++ INT_GPI_FIQ_PAD_FUART_TX, ++ INT_GPI_FIQ_PAD_FUART_CTS, ++ INT_GPI_FIQ_PAD_FUART_RTS, ++ INT_GPI_FIQ_PAD_SD1_CDZ, ++ INT_GPI_FIQ_PAD_SD1_D1, ++ INT_GPI_FIQ_PAD_SD1_D0, ++ INT_GPI_FIQ_PAD_SD1_CLK, ++ INT_GPI_FIQ_PAD_SD1_CMD, ++ INT_GPI_FIQ_PAD_SD1_D3, ++ INT_GPI_FIQ_PAD_SD1_D2, ++ INT_GPI_FIQ_PAD_SD1_GPIO0, ++ INT_GPI_FIQ_PAD_SD1_GPIO1, ++ INT_GPI_FIQ_PAD_GPIO0, ++ INT_GPI_FIQ_PAD_GPIO1, ++ INT_GPI_FIQ_PAD_GPIO2, ++ INT_GPI_FIQ_PAD_GPIO3, ++ INT_GPI_FIQ_PAD_GPIO4, ++ INT_GPI_FIQ_PAD_GPIO5, ++ INT_GPI_FIQ_PAD_GPIO6, ++ INT_GPI_FIQ_PAD_GPIO7, ++ INT_GPI_FIQ_PAD_SR0_IO00, ++ INT_GPI_FIQ_PAD_SR0_IO01, ++ INT_GPI_FIQ_PAD_SR0_IO02, ++ INT_GPI_FIQ_PAD_SR0_IO03, ++ INT_GPI_FIQ_PAD_SR0_IO04, ++ INT_GPI_FIQ_PAD_SR0_IO05, ++ INT_GPI_FIQ_PAD_SR0_IO06, ++ INT_GPI_FIQ_PAD_SR0_IO07, ++ INT_GPI_FIQ_PAD_SR0_IO08, ++ INT_GPI_FIQ_PAD_SR0_IO09, ++ INT_GPI_FIQ_PAD_SR0_IO10, ++ INT_GPI_FIQ_PAD_SR0_IO11, ++ INT_GPI_FIQ_PAD_SR0_IO12, ++ INT_GPI_FIQ_PAD_SR0_IO13, ++ INT_GPI_FIQ_PAD_SR0_IO14, ++ INT_GPI_FIQ_PAD_SR0_IO15, ++ INT_GPI_FIQ_PAD_SR0_IO16, ++ INT_GPI_FIQ_PAD_SR0_IO17, ++ INT_GPI_FIQ_PAD_SR0_IO18, ++ INT_GPI_FIQ_PAD_SR0_IO19, ++ INT_GPI_FIQ_PAD_SR1_IO00, ++ INT_GPI_FIQ_PAD_SR1_IO01, ++ INT_GPI_FIQ_PAD_SR1_IO02, ++ INT_GPI_FIQ_PAD_SR1_IO03, ++ INT_GPI_FIQ_PAD_SR1_IO04, ++ INT_GPI_FIQ_PAD_SR1_IO05, ++ INT_GPI_FIQ_PAD_SR1_IO06, ++ INT_GPI_FIQ_PAD_SR1_IO07, ++ INT_GPI_FIQ_PAD_SR1_IO08, ++ INT_GPI_FIQ_PAD_SR1_IO09, ++ INT_GPI_FIQ_PAD_SR1_IO10, ++ INT_GPI_FIQ_PAD_SR1_IO11, ++ INT_GPI_FIQ_PAD_SR1_IO12, ++ INT_GPI_FIQ_PAD_SR1_IO13, ++ INT_GPI_FIQ_PAD_SR1_IO14, ++ INT_GPI_FIQ_PAD_SR1_IO15, ++ INT_GPI_FIQ_PAD_SR1_IO16, ++ INT_GPI_FIQ_PAD_SR1_IO17, ++ INT_GPI_FIQ_PAD_SR1_IO18, ++ INT_GPI_FIQ_PAD_SR1_IO19, ++ INT_GPI_FIQ_PAD_GPIO8, ++ INT_GPI_FIQ_PAD_GPIO9, ++ INT_GPI_FIQ_PAD_GPIO10, ++ INT_GPI_FIQ_PAD_GPIO11, ++ INT_GPI_FIQ_PAD_GPIO12, ++ INT_GPI_FIQ_PAD_GPIO13, ++ INT_GPI_FIQ_PAD_GPIO14, ++ INT_GPI_FIQ_PAD_GPIO15, ++ INT_GPI_FIQ_PAD_SPI_CZ, ++ INT_GPI_FIQ_PAD_SPI_CK, ++ INT_GPI_FIQ_PAD_SPI_DI, ++ INT_GPI_FIQ_PAD_SPI_DO, ++ INT_GPI_FIQ_PAD_SPI_WPZ, ++ INT_GPI_FIQ_PAD_SPI_HLD, ++ ++}; ++ ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++ U32 r_pe; ++ U8 m_pe; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN), \ ++ CONCAT(CONCAT(GPIO, _x_), _PE)} ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), __GPIO(5), __GPIO(6), __GPIO(7), ++ __GPIO(8), __GPIO(9), __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), __GPIO(15), ++ __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), ++ __GPIO(24), __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), __GPIO(30), __GPIO(31), ++ __GPIO(32), __GPIO(33), __GPIO(34), __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), __GPIO(45), __GPIO(46), __GPIO(47), ++ __GPIO(48), __GPIO(49), __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), __GPIO(55), ++ __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), ++ __GPIO(64), __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), __GPIO(70), __GPIO(71), ++ __GPIO(72), __GPIO(73), __GPIO(74), __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), __GPIO(85), __GPIO(86), __GPIO(87), ++ __GPIO(88), __GPIO(89), __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), __GPIO(95), ++ __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), ++ __GPIO(104), __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), __GPIO(110), __GPIO(111), ++ __GPIO(112), __GPIO(113), __GPIO(114), __GPIO(115), __GPIO(116), __GPIO(117), __GPIO(118), __GPIO(119), ++ __GPIO(120), __GPIO(121), __GPIO(122), __GPIO(123), __GPIO(124), __GPIO(125), __GPIO(126), ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_GPIO_Init(void) ++{ ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ // Enable PE if necessary ++ if (gpio_table[u8IndexGPIO].r_pe) ++ { ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_pe) |= gpio_table[u8IndexGPIO].m_pe; ++ } ++ HalPadSetVal(u8IndexGPIO, PINMUX_FOR_GPIO_MODE); ++} ++ ++int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ return HalPadSetMode(u32PadMode); ++} ++ ++int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode) ++{ ++ return HalPadSetVal((U32)u8IndexGPIO, u32PadMode); ++} ++ ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ // TBD ++} ++ ++static int PMSLEEP_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if ((u8IndexGPIO < PAD_PM_UART_RX1) || (u8IndexGPIO > PAD_SAR_GPIO5)) ++ return -1; ++ else ++ { ++ return _pmsleep_to_irq_table[u8IndexGPIO - PAD_PM_UART_RX1]; ++ } ++} ++ ++static int GPI_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ if ((u8IndexGPIO < PAD_SD0_GPIO0) || (u8IndexGPIO >= PAD_SPI_HLD)) ++ return -1; ++ else ++ return _gpi_to_irq_table[u8IndexGPIO- PAD_SD0_GPIO0]; ++} ++ ++//MHal_GPIO_To_Irq return any virq ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ struct device_node *intr_node; ++ struct irq_domain *intr_domain; ++ struct irq_fwspec fwspec; ++ int hwirq, virq = -1; ++ ++ if ((hwirq = PMSLEEP_GPIO_To_Irq(u8IndexGPIO)) >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,pm-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ else if ((hwirq = GPI_GPIO_To_Irq(u8IndexGPIO)) >= 0) ++ { ++ //get virtual irq number for request_irq ++ intr_node = of_find_compatible_node(NULL, NULL, "sstar,gpi-intc"); ++ intr_domain = irq_find_host(intr_node); ++ if(!intr_domain) ++ return -ENXIO; ++ ++ fwspec.param_count = 1; ++ fwspec.param[0] = hwirq; ++ fwspec.fwnode = of_node_to_fwnode(intr_node); ++ virq = irq_create_fwspec_mapping(&fwspec); ++ } ++ ++ return virq; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse) ++{ ++ // TBD ++} +diff --git a/drivers/sstar/gpio/infinity6e/mhal_gpio.h b/drivers/sstar/gpio/infinity6e/mhal_gpio.h +new file mode 100644 +index 000000000000..b95fc6f2fe7d +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6e/mhal_gpio.h +@@ -0,0 +1,45 @@ ++/* ++* mhal_gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_GPIO_H_ ++#define _MHAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern int MHal_GPIO_PadGroupMode_Set(U32 u32PadMode); ++extern int MHal_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _MHAL_GPIO_H_ +diff --git a/drivers/sstar/gpio/infinity6e/mhal_pinmux.c b/drivers/sstar/gpio/infinity6e/mhal_pinmux.c +new file mode 100755 +index 000000000000..5c10663b540a +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6e/mhal_pinmux.c +@@ -0,0 +1,2333 @@ ++/* ++* mhal_pinmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "mhal_gpio.h" ++#include "padmux.h" ++#include "gpio.h" ++ ++//============================================================================== ++// ++// MACRO DEFINE ++// ++//============================================================================== ++ ++#define BASE_RIU_PA 0xFD000000 ++#define PMSLEEP_BANK 0x000E00 ++#define PM_SAR_BANK 0x001400 ++#define ALBANY1_BANK 0x151500 ++#define ALBANY2_BANK 0x151600 ++#define CHIPTOP_BANK 0x101E00 ++#define PADTOP_BANK 0x103C00 ++#define PM_PADTOP_BANK 0x003F00 ++#define UTMI0_BANK 0x142100 ++ ++#define _GPIO_W_WORD(addr,val) {(*(volatile u16*)(addr)) = (u16)(val);} ++#define _GPIO_W_WORD_MASK(addr,val,mask) {(*(volatile u16*)(addr)) = ((*(volatile u16*)(addr)) & ~(mask)) | ((u16)(val) & (mask));} ++#define _GPIO_R_BYTE(addr) (*(volatile u8*)(addr)) ++#define _GPIO_R_WORD_MASK(addr,mask) ((*(volatile u16*)(addr)) & (mask)) ++ ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++#define _RIUA_8BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + (((offset) & ~1)<<1) + ((offset) & 1) ++#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) ++ ++/* Non PM Pad : CHIPTOP_BANK */ ++#define REG_TEST_IN_MODE 0x12 ++ #define REG_TEST_IN_MODE_MASK BIT1|BIT0 ++#define REG_TEST_OUT_MODE 0x12 ++ #define REG_TEST_OUT_MODE_MASK BIT5|BIT4 ++ ++/* Non PM Pad : PADTOP_BANK */ ++#define REG_DMIC_MODE 0x60 ++ #define REG_DMIC_MODE_MASK BIT0|BIT1|BIT2|BIT3 ++#define REG_BT656_OUT_MODE 0x60 ++ #define REG_BT656_OUT_MODE_MASK BIT4|BIT5 ++#define REG_EJ_MODE 0x60 ++ #define REG_EJ_MODE_MASK BIT7|BIT8 ++#define REG_EMMC0_4B_MODE 0x61 ++ #define REG_EMMC0_4B_MODE_MASK BIT0 ++#define REG_EMMC0_8B_MODE 0x61 ++ #define REG_EMMC0_8B_MODE_MASK BIT1|BIT2 ++#define REG_EMMC0_RST_MODE 0x61 ++ #define REG_EMMC0_RST_MODE_MASK BIT3 ++#define REG_EMMC1_4B_MODE 0x61 ++ #define REG_EMMC1_4B_MODE_MASK BIT4|BIT5 ++#define REG_EMMC1_RST_MODE 0x61 ++ #define REG_EMMC1_RST_MODE_MASK BIT6|BIT7 ++#define REG_I2S_MCK_MODE 0x62 ++ #define REG_I2S_MCK_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_I2S_RX_MODE 0x62 ++ #define REG_I2S_RX_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_I2S_TX_MODE 0x62 ++ #define REG_I2S_TX_MODE_MASK BIT8|BIT9|BIT10 ++#define REG_I2S_RXTX_MODE 0x62 ++ #define REG_I2S_RXTX_MODE_MASK BIT11|BIT12|BIT13 ++#define REG_LED0_MODE 0x63 ++ #define REG_LED0_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_LED1_MODE 0x63 ++ #define REG_LED1_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_MIPI_TX_MODE 0x64 ++ #define REG_MIPI_TX_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_OTP_TEST 0x64 ++ #define REG_OTP_TEST_MASK BIT8 ++#define REG_PWM0_MODE 0x65 ++ #define REG_PWM0_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_PWM1_MODE 0x65 ++ #define REG_PWM1_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_PWM2_MODE 0x65 ++ #define REG_PWM2_MODE_MASK BIT8|BIT9|BIT10 ++#define REG_PWM3_MODE 0x65 ++ #define REG_PWM3_MODE_MASK BIT12|BIT13|BIT14 ++#define REG_PWM4_MODE 0x66 ++ #define REG_PWM4_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_PWM5_MODE 0x66 ++ #define REG_PWM5_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_PWM6_MODE 0x66 ++ #define REG_PWM6_MODE_MASK BIT8|BIT9|BIT10 ++#define REG_PWM7_MODE 0x66 ++ #define REG_PWM7_MODE_MASK BIT12|BIT13|BIT14 ++#define REG_PWM8_MODE 0x67 ++ #define REG_PWM8_MODE_MASK BIT0|BIT1|BIT2|BIT3 ++#define REG_PWM9_MODE 0x67 ++ #define REG_PWM9_MODE_MASK BIT4|BIT5|BIT6|BIT7 ++#define REG_SD0_MODE 0x67 ++ #define REG_SD0_MODE_MASK BIT8 ++#define REG_SD0_CDZ_MODE 0x67 ++ #define REG_SD0_CDZ_MODE_MASK BIT9 ++#define REG_SD1_MODE 0x67 ++ #define REG_SD1_MODE_MASK BIT12|BIT13 ++#define REG_SPI0_MODE 0x68 ++ #define REG_SPI0_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_SPI1_MODE 0x68 ++ #define REG_SPI1_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_SD1_CDZ_MODE 0x68 ++ #define REG_SD1_CDZ_MODE_MASK BIT8|BIT9 ++#define REG_SR00_MIPI_MODE 0x69 ++ #define REG_SR00_MIPI_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_SR00_CTRL_MODE 0x69 ++ #define REG_SR00_CTRL_MODE_MASK BIT4 ++#define REG_SR00_MCLK_MODE 0x69 ++ #define REG_SR00_MCLK_MODE_MASK BIT5 ++#define REG_SR00_RST_MODE 0x69 ++ #define REG_SR00_RST_MODE_MASK BIT6 ++#define REG_SR00_PDN_MODE 0x69 ++ #define REG_SR00_PDN_MODE_MASK BIT8|BIT9 ++#define REG_SR01_MIPI_MODE 0x69 ++ #define REG_SR01_MIPI_MODE_MASK BIT10 ++#define REG_SR01_CTRL_MODE 0x69 ++ #define REG_SR01_CTRL_MODE_MASK BIT11 ++#define REG_SR01_MCLK_MODE 0x69 ++ #define REG_SR01_MCLK_MODE_MASK BIT12 ++#define REG_SR01_RST_MODE 0x69 ++ #define REG_SR01_RST_MODE_MASK BIT13|BIT14 ++#define REG_SR0_BT656_MODE 0x6a ++ #define REG_SR0_BT656_MODE_MASK BIT0|BIT1 ++#define REG_SR0_BT601_MODE 0x6a ++ #define REG_SR0_BT601_MODE_MASK BIT2|BIT3 ++#define REG_SR1_BT656_MODE 0x6b ++ #define REG_SR1_BT656_MODE_MASK BIT0 ++#define REG_SR1_BT601_MODE 0x6b ++ #define REG_SR1_BT601_MODE_MASK BIT1 ++#define REG_SR1_MIPI_MODE 0x6b ++ #define REG_SR1_MIPI_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_SR1_CTRL_MODE 0x6b ++ #define REG_SR1_CTRL_MODE_MASK BIT8 ++#define REG_SR1_MCLK_MODE 0x6b ++ #define REG_SR1_MCLK_MODE_MASK BIT9|BIT10 ++#define REG_SR1_RST_MODE 0x6b ++ #define REG_SR1_RST_MODE_MASK BIT11|BIT12 ++#define REG_TTL16_MODE 0x6c ++ #define REG_TTL16_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_TTL24_MODE 0x6c ++ #define REG_TTL24_MODE_MASK BIT4 ++#define REG_UART0_MODE 0x6d ++ #define REG_UART0_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_UART1_MODE 0x6d ++ #define REG_UART1_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_UART2_MODE 0x6d ++ #define REG_UART2_MODE_MASK BIT8|BIT9|BIT10 ++#define REG_ETH_MODE 0x6e ++ #define REG_ETH_MODE_MASK BIT0 ++#define REG_FUART_MODE 0x6e ++ #define REG_FUART_MODE_MASK BIT4|BIT5|BIT6 ++#define REG_I2C0_MODE 0x6f ++ #define REG_I2C0_MODE_MASK BIT0|BIT1|BIT2 ++#define REG_I2C1_MODE 0x6f ++ #define REG_I2C1_MODE_MASK BIT4|BIT5 ++#define REG_I2C2_MODE 0x6f ++ #define REG_I2C2_MODE_MASK BIT8|BIT9|BIT10 ++#define REG_SPI_GPIO 0x70 ++ #define REG_SPI_GPIO_MASK BIT0 ++#define REG_SPICSZ1_GPIO 0x70 ++ #define REG_SPICSZ1_GPIO_MASK BIT1 ++#define REG_SPICSZ2_GPIO 0x70 ++ #define REG_SPICSZ2_GPIO_MASK BIT2 ++#define REG_SPIHOLDN_GPIO 0x70 ++ #define REG_SPIHOLDN_GPIO_MASK BIT3 ++#define REG_SPIWPN_GPIO 0x70 ++ #define REG_SPIWPN_GPIO_MASK BIT4 ++#define REG_DLA_EJ_MODE 0x71 ++ #define REG_DLA_EJ_MODE_MASK BIT0|BIT1 ++ ++/* PM Sleep : PMSLEEP_BANK */ ++#define REG_PM_GPIO_PM_LOCK 0x12 ++ #define REG_PM_GPIO_PM_LOCK_MASK 0xFFFF ++#define REG_PM_GPIO_PM4_INV 0x1c ++ #define REG_PM_GPIO_PM4_INV_MASK BIT1 ++#define REG_PM_LINK_ISOEN2GPIO4 0x1c ++ #define REG_PM_LINK_ISOEN2GPIO4_MASK BIT2 ++#define REG_PM_LINK_WKINT2GPIO4 0x1c ++ #define REG_PM_LINK_WKINT2GPIO4_MASK BIT3 ++#define REG_PM_IR_IS_GPIO 0x1c ++ #define REG_PM_IR_IS_GPIO_MASK BIT4 ++ ++#define REG_PM_SD_CDZ_MODE 0x28 ++ #define REG_PM_SD_CDZ_MODE_MASK BIT14 ++#define REG_PM_SPI_IS_GPIO 0x35 ++ #define REG_PM_SPI_IS_GPIO_MASK BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0 ++ #define REG_PM_SPI_GPIO_MASK BIT0 ++ #define REG_PM_SPICSZ1_GPIO_MASK BIT2 ++ #define REG_PM_SPICSZ2_GPIO_MASK BIT3 ++ #define REG_PM_SPIWPN_GPIO_MASK BIT4 ++ ++#define REG_PM_SPICSZ1_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPICSZ2_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPI_GPIO REG_PM_SPI_IS_GPIO ++#define REG_PM_SPIWPN_GPIO REG_PM_SPI_IS_GPIO ++ ++//#define REG_PM_SPIHOLDN_MODE REG_PM_SPI_IS_GPIO ++ ++ ++// PM PADTOP ++#define REG_PM_I2CM_MODE 0x50 ++ #define REG_PM_I2CM_MODE_MASK BIT1|BIT0 ++ ++#define REG_PM_PWM0_MODE 0x51 ++ #define REG_PM_PWM0_MODE_MASK BIT1|BIT0 ++ ++#define REG_PM_SPIHOLDN_MODE 0x52 ++ #define REG_PM_SPIHOLDN_MODE_MASK BIT0 ++ ++#define REG_PM_UART1_MODE 0x53 ++ #define REG_PM_UART1_MODE_MASK BIT1|BIT0 ++#define REG_PM_VID_MODE 0x53 ++ #define REG_PM_VID_MODE_MASK BIT3|BIT2 ++ ++#define REG_PM_PIR_DIR_LINK_MODE 0x54 ++ #define REG_PM_PIR_DIR_LINK_MODE_MASK BIT1|BIT0 ++#define REG_PM_PIR_SERIN_MODE 0x54 ++ #define REG_PM_PIR_SERIN_MODE_MASK BIT3|BIT2 ++ ++#define REG_PM_PM_PAD_EXT_MODE_0 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_0_MASK BIT0 ++#define REG_PM_PM_PAD_EXT_MODE_1 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_1_MASK BIT1 ++#define REG_PM_PM_PAD_EXT_MODE_2 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_2_MASK BIT2 ++#define REG_PM_PM_PAD_EXT_MODE_3 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_3_MASK BIT3 ++#define REG_PM_PM_PAD_EXT_MODE_4 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_4_MASK BIT4 ++#define REG_PM_PM_PAD_EXT_MODE_5 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_5_MASK BIT5 ++#define REG_PM_PM_PAD_EXT_MODE_6 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_6_MASK BIT6 ++#define REG_PM_PM_PAD_EXT_MODE_7 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_7_MASK BIT7 ++#define REG_PM_PM_PAD_EXT_MODE_8 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_8_MASK BIT8 ++#define REG_PM_PM_PAD_EXT_MODE_9 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_9_MASK BIT9 ++#define REG_PM_PM_PAD_EXT_MODE_10 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_10_MASK BIT10 ++#define REG_PM_PM_PAD_EXT_MODE_11 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_11_MASK BIT11 ++#define REG_PM_PM_PAD_EXT_MODE_12 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_12_MASK BIT12 ++#define REG_PM_PM_PAD_EXT_MODE_13 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_13_MASK BIT13 ++#define REG_PM_PM_PAD_EXT_MODE_14 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_14_MASK BIT14 ++#define REG_PM_PM_PAD_EXT_MODE_15 0x55 ++ #define REG_PM_PM_PAD_EXT_MODE_15_MASK BIT15 ++#define REG_PM_PM_PAD_EXT_MODE_16 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_16_MASK BIT0 ++#define REG_PM_PM_PAD_EXT_MODE_17 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_17_MASK BIT1 ++#define REG_PM_PM_PAD_EXT_MODE_18 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_18_MASK BIT2 ++#define REG_PM_PM_PAD_EXT_MODE_19 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_19_MASK BIT3 ++#define REG_PM_PM_PAD_EXT_MODE_20 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_20_MASK BIT4 ++#define REG_PM_PM_PAD_EXT_MODE_21 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_21_MASK BIT5 ++#define REG_PM_PM_PAD_EXT_MODE_22 0x56 ++ #define REG_PM_PM_PAD_EXT_MODE_22_MASK BIT6 ++ ++#define REG_PM_PM51_UART_MODE 0x65 ++ #define REG_PM_PM51_UART_MODE_MASK BIT1|BIT0 ++#define REG_PM_UART_IS_GPIO 0x65 ++ #define REG_PM_UART_IS_GPIO_MASK BIT4 ++ ++// GPIO ENABLE ++#define REG_PM_UART_RX1_GPIO_MODE 0x19 ++ #define REG_PM_UART_RX1_GPIO_MODE_MASK BIT3 ++#define REG_PM_UART_TX1_GPIO_MODE 0x20 ++ #define REG_PM_UART_TX1_GPIO_MODE_MASK BIT3 ++#define REG_PM_UART_RX_GPIO_MODE 0x21 ++ #define REG_PM_UART_RX_GPIO_MODE_MASK BIT3 ++#define REG_PM_UART_TX_GPIO_MODE 0x22 ++ #define REG_PM_UART_TX_GPIO_MODE_MASK BIT3 ++#define REG_PM_I2CM_SCL_GPIO_MODE 0x11 ++ #define REG_PM_I2CM_SCL_GPIO_MODE_MASK BIT3 ++#define REG_PM_I2CM_SDA_GPIO_MODE 0x12 ++ #define REG_PM_I2CM_SDA_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO0_GPIO_MODE 0x00 ++ #define REG_PM_GPIO0_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO1_GPIO_MODE 0x01 ++ #define REG_PM_GPIO1_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO2_GPIO_MODE 0x02 ++ #define REG_PM_GPIO2_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO3_GPIO_MODE 0x03 ++ #define REG_PM_GPIO3_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO4_GPIO_MODE 0x04 ++ #define REG_PM_GPIO4_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO5_GPIO_MODE 0x05 ++ #define REG_PM_GPIO5_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO6_GPIO_MODE 0x06 ++ #define REG_PM_GPIO6_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO7_GPIO_MODE 0x07 ++ #define REG_PM_GPIO7_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO8_GPIO_MODE 0x08 ++ #define REG_PM_GPIO8_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO9_GPIO_MODE 0x09 ++ #define REG_PM_GPIO9_GPIO_MODE_MASK BIT3 ++#define REG_PM_GPIO10_GPIO_MODE 0x10 ++ #define REG_PM_GPIO10_GPIO_MODE_MASK BIT3 ++#define REG_PM_SPI_CZ_GPIO_MODE 0x13 ++ #define REG_PM_SPI_CZ_GPIO_MODE_MASK BIT3 ++#define REG_PM_SPI_CK_GPIO_MODE 0x14 ++ #define REG_PM_SPI_CK_GPIO_MODE_MASK BIT3 ++#define REG_PM_SPI_DI_GPIO_MODE 0x15 ++ #define REG_PM_SPI_DI_GPIO_MODE_MASK BIT3 ++#define REG_PM_SPI_DO_GPIO_MODE 0x16 ++ #define REG_PM_SPI_DO_GPIO_MODE_MASK BIT3 ++#define REG_PM_SPI_WPZ_GPIO_MODE 0x17 ++ #define REG_PM_SPI_WPZ_GPIO_MODE_MASK BIT3 ++#define REG_PM_SPI_HLD_GPIO_MODE 0x18 ++ #define REG_PM_SPI_HLD_GPIO_MODE_MASK BIT3 ++#define REG_SAR_GPIO0_GPIO_MODE 0x11 ++ #define REG_SAR_GPIO0_GPIO_MODE_MASK BIT0 ++#define REG_SAR_GPIO1_GPIO_MODE 0x11 ++ #define REG_SAR_GPIO1_GPIO_MODE_MASK BIT1 ++#define REG_SAR_GPIO2_GPIO_MODE 0x11 ++ #define REG_SAR_GPIO2_GPIO_MODE_MASK BIT2 ++#define REG_SAR_GPIO3_GPIO_MODE 0x11 ++ #define REG_SAR_GPIO3_GPIO_MODE_MASK BIT3 ++#define REG_SAR_GPIO4_GPIO_MODE 0x11 ++ #define REG_SAR_GPIO4_GPIO_MODE_MASK BIT4 ++#define REG_SAR_GPIO5_GPIO_MODE 0x11 ++ #define REG_SAR_GPIO5_GPIO_MODE_MASK BIT5 ++ #define REG_SAR_GPIO_MODE_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5) ++#define REG_SD0_GPIO0_GPIO_MODE 0x10 ++ #define REG_SD0_GPIO0_GPIO_MODE_MASK BIT3 ++#define REG_SD0_CDZ_GPIO_MODE 0x11 ++ #define REG_SD0_CDZ_GPIO_MODE_MASK BIT3 ++#define REG_SD0_D1_GPIO_MODE 0x12 ++ #define REG_SD0_D1_GPIO_MODE_MASK BIT3 ++#define REG_SD0_D0_GPIO_MODE 0x13 ++ #define REG_SD0_D0_GPIO_MODE_MASK BIT3 ++#define REG_SD0_CLK_GPIO_MODE 0x14 ++ #define REG_SD0_CLK_GPIO_MODE_MASK BIT3 ++#define REG_SD0_CMD_GPIO_MODE 0x15 ++ #define REG_SD0_CMD_GPIO_MODE_MASK BIT3 ++#define REG_SD0_D3_GPIO_MODE 0x16 ++ #define REG_SD0_D3_GPIO_MODE_MASK BIT3 ++#define REG_SD0_D2_GPIO_MODE 0x17 ++ #define REG_SD0_D2_GPIO_MODE_MASK BIT3 ++#define REG_I2S0_MCLK_GPIO_MODE 0x18 ++ #define REG_I2S0_MCLK_GPIO_MODE_MASK BIT3 ++#define REG_I2S0_BCK_GPIO_MODE 0x19 ++ #define REG_I2S0_BCK_GPIO_MODE_MASK BIT3 ++#define REG_I2S0_WCK_GPIO_MODE 0x1a ++ #define REG_I2S0_WCK_GPIO_MODE_MASK BIT3 ++#define REG_I2S0_DI_GPIO_MODE 0x1b ++ #define REG_I2S0_DI_GPIO_MODE_MASK BIT3 ++#define REG_I2S0_DO_GPIO_MODE 0x1c ++ #define REG_I2S0_DO_GPIO_MODE_MASK BIT3 ++#define REG_I2C0_SCL_GPIO_MODE 0x1d ++ #define REG_I2C0_SCL_GPIO_MODE_MASK BIT3 ++#define REG_I2C0_SDA_GPIO_MODE 0x1e ++ #define REG_I2C0_SDA_GPIO_MODE_MASK BIT3 ++#define REG_ETH_LED0_GPIO_MODE 0x20 ++ #define REG_ETH_LED0_GPIO_MODE_MASK BIT3 ++#define REG_ETH_LED1_GPIO_MODE 0x21 ++ #define REG_ETH_LED1_GPIO_MODE_MASK BIT3 ++#define REG_FUART_RX_GPIO_MODE 0x22 ++ #define REG_FUART_RX_GPIO_MODE_MASK BIT3 ++#define REG_FUART_TX_GPIO_MODE 0x23 ++ #define REG_FUART_TX_GPIO_MODE_MASK BIT3 ++#define REG_FUART_CTS_GPIO_MODE 0x24 ++ #define REG_FUART_CTS_GPIO_MODE_MASK BIT3 ++#define REG_FUART_RTS_GPIO_MODE 0x25 ++ #define REG_FUART_RTS_GPIO_MODE_MASK BIT3 ++#define REG_SD1_CDZ_GPIO_MODE 0x26 ++ #define REG_SD1_CDZ_GPIO_MODE_MASK BIT3 ++#define REG_SD1_D1_GPIO_MODE 0x27 ++ #define REG_SD1_D1_GPIO_MODE_MASK BIT3 ++#define REG_SD1_D0_GPIO_MODE 0x28 ++ #define REG_SD1_D0_GPIO_MODE_MASK BIT3 ++#define REG_SD1_CLK_GPIO_MODE 0x29 ++ #define REG_SD1_CLK_GPIO_MODE_MASK BIT3 ++#define REG_SD1_CMD_GPIO_MODE 0x2a ++ #define REG_SD1_CMD_GPIO_MODE_MASK BIT3 ++#define REG_SD1_D3_GPIO_MODE 0x2b ++ #define REG_SD1_D3_GPIO_MODE_MASK BIT3 ++#define REG_SD1_D2_GPIO_MODE 0x2c ++ #define REG_SD1_D2_GPIO_MODE_MASK BIT3 ++#define REG_SD1_GPIO0_GPIO_MODE 0x2d ++ #define REG_SD1_GPIO0_GPIO_MODE_MASK BIT3 ++#define REG_SD1_GPIO1_GPIO_MODE 0x2e ++ #define REG_SD1_GPIO1_GPIO_MODE_MASK BIT3 ++#define REG_GPIO0_GPIO_MODE 0x00 ++ #define REG_GPIO0_GPIO_MODE_MASK BIT3 ++#define REG_GPIO1_GPIO_MODE 0x01 ++ #define REG_GPIO1_GPIO_MODE_MASK BIT3 ++#define REG_GPIO2_GPIO_MODE 0x02 ++ #define REG_GPIO2_GPIO_MODE_MASK BIT3 ++#define REG_GPIO3_GPIO_MODE 0x03 ++ #define REG_GPIO3_GPIO_MODE_MASK BIT3 ++#define REG_GPIO4_GPIO_MODE 0x04 ++ #define REG_GPIO4_GPIO_MODE_MASK BIT3 ++#define REG_GPIO5_GPIO_MODE 0x05 ++ #define REG_GPIO5_GPIO_MODE_MASK BIT3 ++#define REG_GPIO6_GPIO_MODE 0x06 ++ #define REG_GPIO6_GPIO_MODE_MASK BIT3 ++#define REG_GPIO7_GPIO_MODE 0x07 ++ #define REG_GPIO7_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO00_GPIO_MODE 0x36 ++ #define REG_SR0_IO00_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO01_GPIO_MODE 0x37 ++ #define REG_SR0_IO01_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO02_GPIO_MODE 0x38 ++ #define REG_SR0_IO02_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO03_GPIO_MODE 0x39 ++ #define REG_SR0_IO03_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO04_GPIO_MODE 0x3a ++ #define REG_SR0_IO04_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO05_GPIO_MODE 0x3b ++ #define REG_SR0_IO05_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO06_GPIO_MODE 0x3c ++ #define REG_SR0_IO06_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO07_GPIO_MODE 0x3d ++ #define REG_SR0_IO07_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO08_GPIO_MODE 0x3e ++ #define REG_SR0_IO08_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO09_GPIO_MODE 0x3f ++ #define REG_SR0_IO09_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO10_GPIO_MODE 0x40 ++ #define REG_SR0_IO10_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO11_GPIO_MODE 0x41 ++ #define REG_SR0_IO11_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO12_GPIO_MODE 0x42 ++ #define REG_SR0_IO12_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO13_GPIO_MODE 0x43 ++ #define REG_SR0_IO13_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO14_GPIO_MODE 0x44 ++ #define REG_SR0_IO14_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO15_GPIO_MODE 0x45 ++ #define REG_SR0_IO15_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO16_GPIO_MODE 0x46 ++ #define REG_SR0_IO16_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO17_GPIO_MODE 0x47 ++ #define REG_SR0_IO17_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO18_GPIO_MODE 0x48 ++ #define REG_SR0_IO18_GPIO_MODE_MASK BIT3 ++#define REG_SR0_IO19_GPIO_MODE 0x49 ++ #define REG_SR0_IO19_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO00_GPIO_MODE 0x4a ++ #define REG_SR1_IO00_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO01_GPIO_MODE 0x4b ++ #define REG_SR1_IO01_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO02_GPIO_MODE 0x4c ++ #define REG_SR1_IO02_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO03_GPIO_MODE 0x4d ++ #define REG_SR1_IO03_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO04_GPIO_MODE 0x4e ++ #define REG_SR1_IO04_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO05_GPIO_MODE 0x4f ++ #define REG_SR1_IO05_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO06_GPIO_MODE 0x50 ++ #define REG_SR1_IO06_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO07_GPIO_MODE 0x51 ++ #define REG_SR1_IO07_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO08_GPIO_MODE 0x52 ++ #define REG_SR1_IO08_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO09_GPIO_MODE 0x53 ++ #define REG_SR1_IO09_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO10_GPIO_MODE 0x54 ++ #define REG_SR1_IO10_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO11_GPIO_MODE 0x55 ++ #define REG_SR1_IO11_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO12_GPIO_MODE 0x56 ++ #define REG_SR1_IO12_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO13_GPIO_MODE 0x57 ++ #define REG_SR1_IO13_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO14_GPIO_MODE 0x58 ++ #define REG_SR1_IO14_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO15_GPIO_MODE 0x59 ++ #define REG_SR1_IO15_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO16_GPIO_MODE 0x5a ++ #define REG_SR1_IO16_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO17_GPIO_MODE 0x5b ++ #define REG_SR1_IO17_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO18_GPIO_MODE 0x5c ++ #define REG_SR1_IO18_GPIO_MODE_MASK BIT3 ++#define REG_SR1_IO19_GPIO_MODE 0x5d ++ #define REG_SR1_IO19_GPIO_MODE_MASK BIT3 ++#define REG_GPIO8_GPIO_MODE 0x08 ++ #define REG_GPIO8_GPIO_MODE_MASK BIT3 ++#define REG_GPIO9_GPIO_MODE 0x09 ++ #define REG_GPIO9_GPIO_MODE_MASK BIT3 ++#define REG_GPIO10_GPIO_MODE 0x0a ++ #define REG_GPIO10_GPIO_MODE_MASK BIT3 ++#define REG_GPIO11_GPIO_MODE 0x0b ++ #define REG_GPIO11_GPIO_MODE_MASK BIT3 ++#define REG_GPIO12_GPIO_MODE 0x0c ++ #define REG_GPIO12_GPIO_MODE_MASK BIT3 ++#define REG_GPIO13_GPIO_MODE 0x0d ++ #define REG_GPIO13_GPIO_MODE_MASK BIT3 ++#define REG_GPIO14_GPIO_MODE 0x0e ++ #define REG_GPIO14_GPIO_MODE_MASK BIT3 ++#define REG_GPIO15_GPIO_MODE 0x0f ++ #define REG_GPIO15_GPIO_MODE_MASK BIT3 ++#define REG_SPI_CZ_GPIO_MODE 0x30 ++ #define REG_SPI_CZ_GPIO_MODE_MASK BIT3 ++#define REG_SPI_CK_GPIO_MODE 0x31 ++ #define REG_SPI_CK_GPIO_MODE_MASK BIT3 ++#define REG_SPI_DI_GPIO_MODE 0x32 ++ #define REG_SPI_DI_GPIO_MODE_MASK BIT3 ++#define REG_SPI_DO_GPIO_MODE 0x33 ++ #define REG_SPI_DO_GPIO_MODE_MASK BIT3 ++#define REG_SPI_WPZ_GPIO_MODE 0x34 ++ #define REG_SPI_WPZ_GPIO_MODE_MASK BIT3 ++#define REG_SPI_HLD_GPIO_MODE 0x35 ++ #define REG_SPI_HLD_GPIO_MODE_MASK BIT3 ++ ++ ++/* EMAC : ALBANY1_BANK */ ++#define REG_ATOP_RX_INOFF 0x69 ++ #define REG_ATOP_RX_INOFF_MASK BIT14 ++ ++/* EMAC : ALBANY2_BANK */ ++#define REG_ETH_GPIO_EN 0x71 ++ #define REG_ETH_GPIO_EN_MASK BIT3|BIT2|BIT1|BIT0 ++ ++ ++/* UTMI0 : UTMI0_BANK */ ++#define REG_UTMI0_FL_XVR_PDN 0x0 ++ #define REG_UTMI0_FL_XVR_PDN_MASK BIT12 ++#define REG_UTMI0_REG_PDN 0x0 ++ #define REG_UTMI0_REG_PDN_MASK BIT15 // 1: power doen 0: enable ++#define REG_UTMI0_CLK_EXTRA0_EN 0x4 ++ #define REG_UTMI0_CLK_EXTRA0_EN_MASK BIT7 // 1: power down 0: enable ++#define REG_UTMI0_GPIO_EN 0x1f ++ #define REG_UTMI0_GPIO_EN_MASK BIT14 ++ ++ ++//-------------------- configuration ----------------- ++#define ENABLE_CHECK_ALL_PAD_CONFLICT 1 ++ ++//============================================================================== ++// ++// STRUCTURE ++// ++//============================================================================== ++ ++typedef struct stPadMux ++{ ++ U16 padID; ++ U32 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PadMuxInfo; ++ ++typedef struct stPadMode ++{ ++ U8 u8PadName[32]; ++ U32 u32ModeRIU; ++ U32 u32ModeMask; ++} ST_PadModeInfo; ++ ++//============================================================================== ++// ++// VARIABLES ++// ++//============================================================================== ++ ++const ST_PadMuxInfo m_stPadMuxTbl[] = ++{ ++ ++ {PAD_PM_UART_RX1, PM_PADTOP_BANK, REG_PM_PM51_UART_MODE, REG_PM_PM51_UART_MODE_MASK, BIT0, PINMUX_FOR_PM_PM51_UART_MODE_1}, ++ {PAD_PM_UART_RX1, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_0, REG_PM_PM_PAD_EXT_MODE_0_MASK, BIT0, PINMUX_FOR_PM_PM_PAD_EXT_MODE_0}, ++ {PAD_PM_UART_RX1, PADTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM4_MODE_3}, ++ {PAD_PM_UART_RX1, PM_PADTOP_BANK, REG_PM_UART_RX1_GPIO_MODE, REG_PM_UART_RX1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_UART_RX1, PM_PADTOP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT0, PINMUX_FOR_PM_UART1_MODE_1}, ++ ++ {PAD_PM_UART_TX1, PM_PADTOP_BANK, REG_PM_PM51_UART_MODE, REG_PM_PM51_UART_MODE_MASK, BIT0, PINMUX_FOR_PM_PM51_UART_MODE_1}, ++ {PAD_PM_UART_TX1, PADTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT5|BIT4, PINMUX_FOR_PWM5_MODE_3}, ++ {PAD_PM_UART_TX1, PM_PADTOP_BANK, REG_PM_UART_TX1_GPIO_MODE, REG_PM_UART_TX1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_UART_TX1, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_1, REG_PM_PM_PAD_EXT_MODE_1_MASK, BIT1, PINMUX_FOR_PM_PM_PAD_EXT_MODE_1}, ++ {PAD_PM_UART_TX1, PM_PADTOP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT0, PINMUX_FOR_PM_UART1_MODE_1}, ++ ++ {PAD_PM_UART_RX, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_UART_RX, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT0, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_PM_UART_RX, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_2, REG_PM_PM_PAD_EXT_MODE_2_MASK, BIT2, PINMUX_FOR_PM_PM_PAD_EXT_MODE_2}, ++ {PAD_PM_UART_RX, PM_PADTOP_BANK, REG_PM_UART_RX_GPIO_MODE, REG_PM_UART_RX_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_UART_RX, PM_PADTOP_BANK, REG_PM_UART_IS_GPIO, REG_PM_UART_IS_GPIO_MASK, 0, PINMUX_FOR_PM_PM_UART_IS_MODE}, ++ ++ {PAD_PM_UART_TX, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_UART_TX, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT0, PINMUX_FOR_UART0_MODE_1}, ++ {PAD_PM_UART_TX, PM_PADTOP_BANK, REG_PM_UART_IS_GPIO, REG_PM_UART_IS_GPIO_MASK, 0, PINMUX_FOR_PM_PM_UART_IS_MODE}, ++ {PAD_PM_UART_TX, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_3, REG_PM_PM_PAD_EXT_MODE_3_MASK, BIT3, PINMUX_FOR_PM_PM_PAD_EXT_MODE_3}, ++ {PAD_PM_UART_TX, PM_PADTOP_BANK, REG_PM_UART_TX_GPIO_MODE, REG_PM_UART_TX_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_PM_I2CM_SCL, PM_PADTOP_BANK, REG_PM_I2CM_MODE, REG_PM_I2CM_MODE_MASK, BIT0, PINMUX_FOR_PM_I2CM_MODE_1}, ++ {PAD_PM_I2CM_SCL, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT10, PINMUX_FOR_I2C2_MODE_4}, ++ {PAD_PM_I2CM_SCL, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_21, REG_PM_PM_PAD_EXT_MODE_21_MASK, BIT5, PINMUX_FOR_PM_PM_PAD_EXT_MODE_21}, ++ {PAD_PM_I2CM_SCL, PADTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT9|BIT8, PINMUX_FOR_PWM6_MODE_3}, ++ {PAD_PM_I2CM_SCL, PM_PADTOP_BANK, REG_PM_I2CM_SCL_GPIO_MODE, REG_PM_I2CM_SCL_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_PM_I2CM_SDA, PADTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM7_MODE_3}, ++ {PAD_PM_I2CM_SDA, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_22, REG_PM_PM_PAD_EXT_MODE_22_MASK, BIT6, PINMUX_FOR_PM_PM_PAD_EXT_MODE_22}, ++ {PAD_PM_I2CM_SDA, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT10, PINMUX_FOR_I2C2_MODE_4}, ++ {PAD_PM_I2CM_SDA, PM_PADTOP_BANK, REG_PM_I2CM_SDA_GPIO_MODE, REG_PM_I2CM_SDA_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_I2CM_SDA, PM_PADTOP_BANK, REG_PM_I2CM_MODE, REG_PM_I2CM_MODE_MASK, BIT0, PINMUX_FOR_PM_I2CM_MODE_1}, ++ ++ {PAD_PM_GPIO0, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_4, REG_PM_PM_PAD_EXT_MODE_4_MASK, BIT4, PINMUX_FOR_PM_PM_PAD_EXT_MODE_4}, ++ {PAD_PM_GPIO0, PM_PADTOP_BANK, REG_PM_PM51_UART_MODE, REG_PM_PM51_UART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PM_PM51_UART_MODE_3}, ++ {PAD_PM_GPIO0, PM_PADTOP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT1, PINMUX_FOR_PM_UART1_MODE_2}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_LED1_MODE, REG_LED1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_LED1_MODE_3}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT10|BIT8, PINMUX_FOR_I2C2_MODE_5}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_LED0_MODE, REG_LED0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_LED0_MODE_3}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM0_MODE_3}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5|BIT4, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT3, PINMUX_FOR_PWM8_MODE_8}, ++ {PAD_PM_GPIO0, PM_PADTOP_BANK, REG_PM_GPIO0_GPIO_MODE, REG_PM_GPIO0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO0, PM_PADTOP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT3, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_GPIO0, PM_PADTOP_BANK, REG_PM_PIR_SERIN_MODE, REG_PM_PIR_SERIN_MODE_MASK, BIT2, PINMUX_FOR_PM_PIR_SERIN_MODE_1}, ++ {PAD_PM_GPIO0, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT11, PINMUX_FOR_I2S_RXTX_MODE_5}, ++ ++ {PAD_PM_GPIO1, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_5, REG_PM_PM_PAD_EXT_MODE_5_MASK, BIT5, PINMUX_FOR_PM_PM_PAD_EXT_MODE_5}, ++ {PAD_PM_GPIO1, PM_PADTOP_BANK, REG_PM_PWM0_MODE, REG_PM_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PM_PWM0_MODE_1}, ++ {PAD_PM_GPIO1, PM_PADTOP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT1, PINMUX_FOR_PM_UART1_MODE_2}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_LED1_MODE, REG_LED1_MODE_MASK, BIT6, PINMUX_FOR_LED1_MODE_4}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT10|BIT8, PINMUX_FOR_I2C2_MODE_5}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT7, PINMUX_FOR_PWM9_MODE_8}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_PWM1_MODE_3}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_LED0_MODE, REG_LED0_MODE_MASK, BIT2, PINMUX_FOR_LED0_MODE_4}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5|BIT4, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_PM_GPIO1, PM_PADTOP_BANK, REG_PM_GPIO1_GPIO_MODE, REG_PM_GPIO1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO1, PM_PADTOP_BANK, REG_PM_PM51_UART_MODE, REG_PM_PM51_UART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PM_PM51_UART_MODE_3}, ++ {PAD_PM_GPIO1, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT11, PINMUX_FOR_I2S_RXTX_MODE_5}, ++ ++ {PAD_PM_GPIO2, PADTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT9|BIT8, PINMUX_FOR_PWM2_MODE_3}, ++ {PAD_PM_GPIO2, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_6, REG_PM_PM_PAD_EXT_MODE_6_MASK, BIT6, PINMUX_FOR_PM_PM_PAD_EXT_MODE_6}, ++ {PAD_PM_GPIO2, PM_PADTOP_BANK, REG_PM_GPIO2_GPIO_MODE, REG_PM_GPIO2_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO2, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5|BIT4, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_PM_GPIO2, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT5, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_PM_GPIO2, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT11, PINMUX_FOR_I2S_RXTX_MODE_5}, ++ ++ {PAD_PM_GPIO3, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT11, PINMUX_FOR_I2S_RXTX_MODE_5}, ++ {PAD_PM_GPIO3, PADTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM3_MODE_3}, ++ {PAD_PM_GPIO3, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5|BIT4, PINMUX_FOR_FUART_MODE_3}, ++ {PAD_PM_GPIO3, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT5, PINMUX_FOR_FUART_MODE_6}, ++ {PAD_PM_GPIO3, PM_PADTOP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT3, PINMUX_FOR_PM_VID_MODE_2}, ++ {PAD_PM_GPIO3, PM_PADTOP_BANK, REG_PM_GPIO3_GPIO_MODE, REG_PM_GPIO3_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO3, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_7, REG_PM_PM_PAD_EXT_MODE_7_MASK, BIT7, PINMUX_FOR_PM_PM_PAD_EXT_MODE_7}, ++ ++ {PAD_PM_GPIO4, PM_PADTOP_BANK, REG_PM_PWM0_MODE, REG_PM_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PM_PWM0_MODE_2}, ++ {PAD_PM_GPIO4, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8|BIT7, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_PM_GPIO4, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_8, REG_PM_PM_PAD_EXT_MODE_8_MASK, BIT8, PINMUX_FOR_PM_PM_PAD_EXT_MODE_8}, ++ {PAD_PM_GPIO4, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2|BIT1, PINMUX_FOR_DMIC_MODE_6}, ++ {PAD_PM_GPIO4, PADTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT2, PINMUX_FOR_PWM4_MODE_4}, ++ {PAD_PM_GPIO4, PM_PADTOP_BANK, REG_PM_I2CM_MODE, REG_PM_I2CM_MODE_MASK, BIT1, PINMUX_FOR_PM_I2CM_MODE_2}, ++ {PAD_PM_GPIO4, PM_PADTOP_BANK, REG_PM_GPIO4_GPIO_MODE, REG_PM_GPIO4_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_PM_GPIO5, PADTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT6, PINMUX_FOR_PWM5_MODE_4}, ++ {PAD_PM_GPIO5, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8|BIT7, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_PM_GPIO5, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2|BIT1, PINMUX_FOR_DMIC_MODE_6}, ++ {PAD_PM_GPIO5, PM_PADTOP_BANK, REG_PM_PIR_DIR_LINK_MODE, REG_PM_PIR_DIR_LINK_MODE_MASK, BIT0, PINMUX_FOR_PM_PIR_DIR_LINK_MODE_1}, ++ {PAD_PM_GPIO5, PM_PADTOP_BANK, REG_PM_I2CM_MODE, REG_PM_I2CM_MODE_MASK, BIT1, PINMUX_FOR_PM_I2CM_MODE_2}, ++ {PAD_PM_GPIO5, PM_PADTOP_BANK, REG_PM_PIR_SERIN_MODE, REG_PM_PIR_SERIN_MODE_MASK, BIT3, PINMUX_FOR_PM_PIR_SERIN_MODE_2}, ++ {PAD_PM_GPIO5, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_9, REG_PM_PM_PAD_EXT_MODE_9_MASK, BIT9, PINMUX_FOR_PM_PM_PAD_EXT_MODE_9}, ++ {PAD_PM_GPIO5, PM_PADTOP_BANK, REG_PM_GPIO5_GPIO_MODE, REG_PM_GPIO5_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_PM_GPIO6, PM_PADTOP_BANK, REG_PM_PIR_DIR_LINK_MODE, REG_PM_PIR_DIR_LINK_MODE_MASK, BIT1, PINMUX_FOR_PM_PIR_DIR_LINK_MODE_2}, ++ {PAD_PM_GPIO6, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8|BIT7, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_PM_GPIO6, PADTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT10, PINMUX_FOR_PWM6_MODE_4}, ++ {PAD_PM_GPIO6, PM_PADTOP_BANK, REG_PM_GPIO6_GPIO_MODE, REG_PM_GPIO6_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO6, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_10, REG_PM_PM_PAD_EXT_MODE_10_MASK, BIT10, PINMUX_FOR_PM_PM_PAD_EXT_MODE_10}, ++ ++ {PAD_PM_GPIO7, PM_PADTOP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT2, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_GPIO7, PADTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT14, PINMUX_FOR_PWM7_MODE_4}, ++ {PAD_PM_GPIO7, PM_PADTOP_BANK, REG_PM_GPIO7_GPIO_MODE, REG_PM_GPIO7_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO7, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8|BIT7, PINMUX_FOR_EJ_MODE_3}, ++ {PAD_PM_GPIO7, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_11, REG_PM_PM_PAD_EXT_MODE_11_MASK, BIT11, PINMUX_FOR_PM_PM_PAD_EXT_MODE_11}, ++ ++ {PAD_PM_GPIO8, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_GPIO8, PM_PADTOP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT2, PINMUX_FOR_PM_VID_MODE_1}, ++ {PAD_PM_GPIO8, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_12, REG_PM_PM_PAD_EXT_MODE_12_MASK, BIT12, PINMUX_FOR_PM_PM_PAD_EXT_MODE_12}, ++ {PAD_PM_GPIO8, PM_PADTOP_BANK, REG_PM_GPIO8_GPIO_MODE, REG_PM_GPIO8_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_PM_GPIO9, PM_PADTOP_BANK, REG_PM_PM51_UART_MODE, REG_PM_PM51_UART_MODE_MASK, BIT1, PINMUX_FOR_PM_PM51_UART_MODE_2}, ++ {PAD_PM_GPIO9, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_13, REG_PM_PM_PAD_EXT_MODE_13_MASK, BIT13, PINMUX_FOR_PM_PM_PAD_EXT_MODE_13}, ++ {PAD_PM_GPIO9, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT4, PINMUX_FOR_PWM9_MODE_1}, ++ {PAD_PM_GPIO9, PM_PADTOP_BANK, REG_PM_GPIO9_GPIO_MODE, REG_PM_GPIO9_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_SPICSZ2_GPIO, REG_PM_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ2_MODE}, ++ ++ {PAD_PM_GPIO10, PM_PADTOP_BANK, REG_PM_PM51_UART_MODE, REG_PM_PM51_UART_MODE_MASK, BIT1, PINMUX_FOR_PM_PM51_UART_MODE_2}, ++ {PAD_PM_GPIO10, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT0, PINMUX_FOR_PWM8_MODE_1}, ++ {PAD_PM_GPIO10, PM_PADTOP_BANK, REG_PM_GPIO10_GPIO_MODE, REG_PM_GPIO10_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_GPIO10, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_14, REG_PM_PM_PAD_EXT_MODE_14_MASK, BIT14, PINMUX_FOR_PM_PM_PAD_EXT_MODE_14}, ++ {PAD_PM_GPIO10, PMSLEEP_BANK, REG_PM_SPICSZ2_GPIO, REG_PM_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ2_MODE}, ++ ++ {PAD_PM_SPI_CZ, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_SPI_CZ, PMSLEEP_BANK, REG_PM_SPICSZ1_GPIO, REG_PM_SPICSZ1_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ1_MODE}, ++ {PAD_PM_SPI_CZ, PADTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT2|BIT1, PINMUX_FOR_PWM4_MODE_6}, ++ {PAD_PM_SPI_CZ, PM_PADTOP_BANK, REG_PM_SPI_CZ_GPIO_MODE, REG_PM_SPI_CZ_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_CZ, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2S_RX_MODE_3}, ++ {PAD_PM_SPI_CZ, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE_5}, ++ {PAD_PM_SPI_CZ, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT5|BIT4, PINMUX_FOR_FUART_MODE_7}, ++ {PAD_PM_SPI_CZ, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_15, REG_PM_PM_PAD_EXT_MODE_15_MASK, BIT15, PINMUX_FOR_PM_PM_PAD_EXT_MODE_15}, ++ {PAD_PM_SPI_CZ, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12|BIT11, PINMUX_FOR_I2S_RXTX_MODE_3}, ++ ++ {PAD_PM_SPI_CK, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_19, REG_PM_PM_PAD_EXT_MODE_19_MASK, BIT3, PINMUX_FOR_PM_PM_PAD_EXT_MODE_19}, ++ {PAD_PM_SPI_CK, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_SPI_CK, PADTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT6|BIT5, PINMUX_FOR_PWM5_MODE_6}, ++ {PAD_PM_SPI_CK, PM_PADTOP_BANK, REG_PM_SPI_CK_GPIO_MODE, REG_PM_SPI_CK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_CK, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ {PAD_PM_SPI_CK, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2S_RX_MODE_3}, ++ {PAD_PM_SPI_CK, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE_5}, ++ {PAD_PM_SPI_CK, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT5|BIT4, PINMUX_FOR_FUART_MODE_7}, ++ {PAD_PM_SPI_CK, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12|BIT11, PINMUX_FOR_I2S_RXTX_MODE_3}, ++ ++ {PAD_PM_SPI_DI, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_16, REG_PM_PM_PAD_EXT_MODE_16_MASK, BIT0, PINMUX_FOR_PM_PM_PAD_EXT_MODE_16}, ++ {PAD_PM_SPI_DI, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE_5}, ++ {PAD_PM_SPI_DI, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_SPI_DI, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ {PAD_PM_SPI_DI, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2S_RX_MODE_3}, ++ {PAD_PM_SPI_DI, PADTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM6_MODE_6}, ++ {PAD_PM_SPI_DI, PM_PADTOP_BANK, REG_PM_SPI_DI_GPIO_MODE, REG_PM_SPI_DI_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_DI, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12|BIT11, PINMUX_FOR_I2S_RXTX_MODE_3}, ++ {PAD_PM_SPI_DI, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT5|BIT4, PINMUX_FOR_FUART_MODE_7}, ++ ++ {PAD_PM_SPI_DO, PADTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT14|BIT13, PINMUX_FOR_PWM7_MODE_6}, ++ {PAD_PM_SPI_DO, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_18, REG_PM_PM_PAD_EXT_MODE_18_MASK, BIT2, PINMUX_FOR_PM_PM_PAD_EXT_MODE_18}, ++ {PAD_PM_SPI_DO, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_SPI_DO, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, ++ {PAD_PM_SPI_DO, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SPI1_MODE_5}, ++ {PAD_PM_SPI_DO, PM_PADTOP_BANK, REG_PM_SPI_DO_GPIO_MODE, REG_PM_SPI_DO_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_DO, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT5|BIT4, PINMUX_FOR_FUART_MODE_7}, ++ {PAD_PM_SPI_DO, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT10, PINMUX_FOR_I2S_TX_MODE_4}, ++ {PAD_PM_SPI_DO, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12|BIT11, PINMUX_FOR_I2S_RXTX_MODE_3}, ++ ++ {PAD_PM_SPI_WPZ, PADTOP_BANK, REG_I2S_MCK_MODE, REG_I2S_MCK_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2S_MCK_MODE_3}, ++ {PAD_PM_SPI_WPZ, PMSLEEP_BANK, REG_PM_SPIWPN_GPIO, REG_PM_SPIWPN_GPIO_MASK, 0, PINMUX_FOR_PM_SPIWPN_MODE}, ++ {PAD_PM_SPI_WPZ, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_SPI_WPZ, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT1|BIT0, PINMUX_FOR_DMIC_MODE_3}, ++ {PAD_PM_SPI_WPZ, PM_PADTOP_BANK, REG_PM_SPI_WPZ_GPIO_MODE, REG_PM_SPI_WPZ_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_WPZ, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_17, REG_PM_PM_PAD_EXT_MODE_17_MASK, BIT1, PINMUX_FOR_PM_PM_PAD_EXT_MODE_17}, ++ ++ {PAD_PM_SPI_HLD, PM_PADTOP_BANK, REG_PM_SPI_HLD_GPIO_MODE, REG_PM_SPI_HLD_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_PM_SPI_HLD, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_PM_SPI_HLD, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT1|BIT0, PINMUX_FOR_DMIC_MODE_3}, ++ {PAD_PM_SPI_HLD, PM_PADTOP_BANK, REG_PM_SPIHOLDN_MODE, REG_PM_SPIHOLDN_MODE_MASK, 0, PINMUX_FOR_PM_SPIHOLDN_MODE}, ++ {PAD_PM_SPI_HLD, PM_PADTOP_BANK, REG_PM_PM_PAD_EXT_MODE_20, REG_PM_PM_PAD_EXT_MODE_20_MASK, BIT4, PINMUX_FOR_PM_PM_PAD_EXT_MODE_20}, ++ ++ {PAD_SAR_GPIO0, PM_SAR_BANK, REG_SAR_GPIO0_GPIO_MODE, REG_SAR_GPIO0_GPIO_MODE_MASK, BIT0, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SAR_GPIO1, PM_SAR_BANK, REG_SAR_GPIO1_GPIO_MODE, REG_SAR_GPIO1_GPIO_MODE_MASK, BIT1, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SAR_GPIO2, PM_SAR_BANK, REG_SAR_GPIO2_GPIO_MODE, REG_SAR_GPIO2_GPIO_MODE_MASK, BIT2, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SAR_GPIO3, PM_SAR_BANK, REG_SAR_GPIO3_GPIO_MODE, REG_SAR_GPIO3_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SAR_GPIO4, PM_SAR_BANK, REG_SAR_GPIO4_GPIO_MODE, REG_SAR_GPIO4_GPIO_MODE_MASK, BIT4, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SAR_GPIO5, PM_SAR_BANK, REG_SAR_GPIO5_GPIO_MODE, REG_SAR_GPIO5_GPIO_MODE_MASK, BIT5, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SD0_GPIO0, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_GPIO0, PADTOP_BANK, REG_SPICSZ2_GPIO, REG_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_SPICSZ2_MODE}, ++ {PAD_SD0_GPIO0, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT1, PINMUX_FOR_PWM8_MODE_2}, ++ {PAD_SD0_GPIO0, PADTOP_BANK, REG_SD0_GPIO0_GPIO_MODE, REG_SD0_GPIO0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SD0_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SD0_CDZ, PADTOP_BANK, REG_EMMC0_RST_MODE, REG_EMMC0_RST_MODE_MASK, BIT3, PINMUX_FOR_EMMC0_RST_MODE}, ++ {PAD_SD0_CDZ, PADTOP_BANK, REG_SD0_CDZ_GPIO_MODE, REG_SD0_CDZ_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_CDZ, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_CDZ, PADTOP_BANK, REG_SD0_CDZ_MODE, REG_SD0_CDZ_MODE_MASK, BIT9, PINMUX_FOR_SD0_CDZ_MODE}, ++ {PAD_SD0_CDZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SD0_D1, PADTOP_BANK, REG_EMMC0_4B_MODE, REG_EMMC0_4B_MODE_MASK, BIT0, PINMUX_FOR_EMMC0_4B_MODE}, ++ {PAD_SD0_D1, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_D1, PADTOP_BANK, REG_SD0_MODE, REG_SD0_MODE_MASK, BIT8, PINMUX_FOR_SD0_MODE}, ++ {PAD_SD0_D1, PADTOP_BANK, REG_SD0_D1_GPIO_MODE, REG_SD0_D1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_D1, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SD0_D1, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_SD0_D1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SD0_D1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SD0_D0, PADTOP_BANK, REG_EMMC0_4B_MODE, REG_EMMC0_4B_MODE_MASK, BIT0, PINMUX_FOR_EMMC0_4B_MODE}, ++ {PAD_SD0_D0, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_D0, PADTOP_BANK, REG_SD0_D0_GPIO_MODE, REG_SD0_D0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_D0, PADTOP_BANK, REG_SD0_MODE, REG_SD0_MODE_MASK, BIT8, PINMUX_FOR_SD0_MODE}, ++ {PAD_SD0_D0, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SD0_D0, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_SD0_D0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SD0_D0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SD0_CLK, PADTOP_BANK, REG_EMMC0_4B_MODE, REG_EMMC0_4B_MODE_MASK, BIT0, PINMUX_FOR_EMMC0_4B_MODE}, ++ {PAD_SD0_CLK, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_CLK, PADTOP_BANK, REG_SD0_CLK_GPIO_MODE, REG_SD0_CLK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_CLK, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_SD0_CLK, PADTOP_BANK, REG_SD0_MODE, REG_SD0_MODE_MASK, BIT8, PINMUX_FOR_SD0_MODE}, ++ {PAD_SD0_CLK, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SD0_CLK, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_SD0_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SD0_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SD0_CMD, PADTOP_BANK, REG_EMMC0_4B_MODE, REG_EMMC0_4B_MODE_MASK, BIT0, PINMUX_FOR_EMMC0_4B_MODE}, ++ {PAD_SD0_CMD, PADTOP_BANK, REG_SD0_CMD_GPIO_MODE, REG_SD0_CMD_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_CMD, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_CMD, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_SD0_CMD, PADTOP_BANK, REG_SD0_MODE, REG_SD0_MODE_MASK, BIT8, PINMUX_FOR_SD0_MODE}, ++ {PAD_SD0_CMD, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SD0_CMD, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_SD0_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SD0_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SD0_D3, PADTOP_BANK, REG_EMMC0_4B_MODE, REG_EMMC0_4B_MODE_MASK, BIT0, PINMUX_FOR_EMMC0_4B_MODE}, ++ {PAD_SD0_D3, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_D3, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_SD0_D3, PADTOP_BANK, REG_SD0_MODE, REG_SD0_MODE_MASK, BIT8, PINMUX_FOR_SD0_MODE}, ++ {PAD_SD0_D3, PADTOP_BANK, REG_SD0_D3_GPIO_MODE, REG_SD0_D3_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_D3, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SD0_D3, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_SD0_D3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SD0_D3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SD0_D2, PADTOP_BANK, REG_EMMC0_4B_MODE, REG_EMMC0_4B_MODE_MASK, BIT0, PINMUX_FOR_EMMC0_4B_MODE}, ++ {PAD_SD0_D2, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SD0_D2, PADTOP_BANK, REG_SD0_D2_GPIO_MODE, REG_SD0_D2_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD0_D2, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, ++ {PAD_SD0_D2, PADTOP_BANK, REG_SD0_MODE, REG_SD0_MODE_MASK, BIT8, PINMUX_FOR_SD0_MODE}, ++ {PAD_SD0_D2, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SD0_D2, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_SD0_D2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_SD0_D2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_I2S0_MCLK, PADTOP_BANK, REG_I2S_MCK_MODE, REG_I2S_MCK_MODE_MASK, BIT0, PINMUX_FOR_I2S_MCK_MODE_1}, ++ {PAD_I2S0_MCLK, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2S0_MCLK, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT6|BIT5|BIT4, PINMUX_FOR_PWM9_MODE_7}, ++ {PAD_I2S0_MCLK, PADTOP_BANK, REG_I2S0_MCLK_GPIO_MODE, REG_I2S0_MCLK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_I2S0_MCLK, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT13, PINMUX_FOR_SD1_MODE_2}, ++ {PAD_I2S0_MCLK, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT4, PINMUX_FOR_EMMC1_4B_MODE_1}, ++ {PAD_I2S0_MCLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2S0_MCLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT4, PINMUX_FOR_EMMC1_4B_MODE_1}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT13, PINMUX_FOR_SD1_MODE_2}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT0, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT4, PINMUX_FOR_I2S_RX_MODE_1}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM4_MODE_5}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_I2S0_BCK_GPIO_MODE, REG_I2S0_BCK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2S0_BCK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2S0_BCK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2S0_BCK, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT11, PINMUX_FOR_I2S_RXTX_MODE_1}, ++ ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT4, PINMUX_FOR_EMMC1_4B_MODE_1}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_UART0_MODE_3}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT13, PINMUX_FOR_SD1_MODE_2}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT6|BIT4, PINMUX_FOR_PWM5_MODE_5}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT4, PINMUX_FOR_I2S_RX_MODE_1}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT0, PINMUX_FOR_DMIC_MODE_1}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_I2S0_WCK_GPIO_MODE, REG_I2S0_WCK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2S0_WCK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2S0_WCK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2S0_WCK, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT11, PINMUX_FOR_I2S_RXTX_MODE_1}, ++ ++ {PAD_I2S0_DI, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT11, PINMUX_FOR_I2S_RXTX_MODE_1}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT4, PINMUX_FOR_EMMC1_4B_MODE_1}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT13, PINMUX_FOR_SD1_MODE_2}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT4, PINMUX_FOR_I2S_RX_MODE_1}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT5, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT10|BIT8, PINMUX_FOR_PWM6_MODE_5}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2S0_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2S0_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2S0_DI, PADTOP_BANK, REG_I2S0_DI_GPIO_MODE, REG_I2S0_DI_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_I2S0_DO, PADTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT14|BIT12, PINMUX_FOR_PWM7_MODE_5}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_I2S0_DO_GPIO_MODE, REG_I2S0_DO_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT4, PINMUX_FOR_EMMC1_4B_MODE_1}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT13, PINMUX_FOR_SD1_MODE_2}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT8, PINMUX_FOR_EJ_MODE_2}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT5, PINMUX_FOR_UART1_MODE_2}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT8, PINMUX_FOR_I2S_TX_MODE_1}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT9|BIT8, PINMUX_FOR_I2S_TX_MODE_3}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2S0_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2S0_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2S0_DO, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT11, PINMUX_FOR_I2S_RXTX_MODE_1}, ++ ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT13, PINMUX_FOR_SD1_MODE_2}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT4, PINMUX_FOR_EMMC1_4B_MODE_1}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2, PINMUX_FOR_DMIC_MODE_4}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM0_MODE_5}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT2|BIT1, PINMUX_FOR_PWM8_MODE_6}, ++ {PAD_I2C0_SCL, PADTOP_BANK, REG_I2C0_SCL_GPIO_MODE, REG_I2C0_SCL_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT6|BIT5, PINMUX_FOR_PWM9_MODE_6}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_EMMC1_RST_MODE, REG_EMMC1_RST_MODE_MASK, BIT6, PINMUX_FOR_EMMC1_RST_MODE_1}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_PWM1_MODE_5}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_I2C0_SDA_GPIO_MODE, REG_I2C0_SDA_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2, PINMUX_FOR_DMIC_MODE_4}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ {PAD_I2C0_SDA, PADTOP_BANK, REG_SD1_CDZ_MODE, REG_SD1_CDZ_MODE_MASK, BIT9, PINMUX_FOR_SD1_CDZ_MODE_2}, ++ ++ {PAD_ETH_LED0, PADTOP_BANK, REG_LED1_MODE, REG_LED1_MODE_MASK, BIT4, PINMUX_FOR_LED1_MODE_1}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_LED0_MODE, REG_LED0_MODE_MASK, BIT0, PINMUX_FOR_LED0_MODE_1}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9|BIT8, PINMUX_FOR_I2C2_MODE_3}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT5|BIT4, PINMUX_FOR_PWM9_MODE_3}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10|BIT8, PINMUX_FOR_PWM2_MODE_5}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT1, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_ETH_LED0_GPIO_MODE, REG_ETH_LED0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT8, PINMUX_FOR_I2S_TX_MODE_1}, ++ {PAD_ETH_LED0, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_ETH_LED0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_ETH_LED1, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM8_MODE_3}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT14|BIT12, PINMUX_FOR_PWM3_MODE_5}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_LED1_MODE, REG_LED1_MODE_MASK, BIT5, PINMUX_FOR_LED1_MODE_2}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_LED0_MODE, REG_LED0_MODE_MASK, BIT1, PINMUX_FOR_LED0_MODE_2}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9|BIT8, PINMUX_FOR_I2C2_MODE_3}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART1_MODE_3}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_ETH_LED1_GPIO_MODE, REG_ETH_LED1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT1, PINMUX_FOR_UART0_MODE_2}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT8, PINMUX_FOR_I2S_TX_MODE_1}, ++ {PAD_ETH_LED1, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_ETH_LED1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_FUART_RX, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT0, PINMUX_FOR_DLA_EJ_MODE_1}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2|BIT1, PINMUX_FOR_PWM0_MODE_6}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_FUART_RX_GPIO_MODE, REG_FUART_RX_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT7, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT4, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT4, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_FUART_RX, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_FUART_TX, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT0, PINMUX_FOR_DLA_EJ_MODE_1}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT7, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_PWM1_MODE_6}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_FUART_TX_GPIO_MODE, REG_FUART_TX_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT4, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6|BIT4, PINMUX_FOR_FUART_MODE_5}, ++ {PAD_FUART_TX, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_FUART_CTS, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_UART1_MODE_5}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT0, PINMUX_FOR_DLA_EJ_MODE_1}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT7, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT5, PINMUX_FOR_PWM9_MODE_2}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM2_MODE_6}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_FUART_CTS_GPIO_MODE, REG_FUART_CTS_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT4, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_CTS, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_FUART_RTS, PADTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT14|BIT13, PINMUX_FOR_PWM3_MODE_6}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT6|BIT4, PINMUX_FOR_UART1_MODE_5}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_FUART_RTS_GPIO_MODE, REG_FUART_RTS_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT0, PINMUX_FOR_DLA_EJ_MODE_1}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT7, PINMUX_FOR_EJ_MODE_1}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT4, PINMUX_FOR_FUART_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_FUART_RTS, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_SD1_CDZ, PADTOP_BANK, REG_EMMC1_RST_MODE, REG_EMMC1_RST_MODE_MASK, BIT7, PINMUX_FOR_EMMC1_RST_MODE_2}, ++ {PAD_SD1_CDZ, PADTOP_BANK, REG_SD1_CDZ_MODE, REG_SD1_CDZ_MODE_MASK, BIT8, PINMUX_FOR_SD1_CDZ_MODE_1}, ++ {PAD_SD1_CDZ, PADTOP_BANK, REG_SD1_CDZ_GPIO_MODE, REG_SD1_CDZ_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SD1_D1, PADTOP_BANK, REG_SD1_D1_GPIO_MODE, REG_SD1_D1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD1_D1, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT5, PINMUX_FOR_EMMC1_4B_MODE_2}, ++ {PAD_SD1_D1, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT12, PINMUX_FOR_SD1_MODE_1}, ++ {PAD_SD1_D1, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6, PINMUX_FOR_FUART_MODE_4}, ++ ++ {PAD_SD1_D0, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT5, PINMUX_FOR_EMMC1_4B_MODE_2}, ++ {PAD_SD1_D0, PADTOP_BANK, REG_SD1_D0_GPIO_MODE, REG_SD1_D0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD1_D0, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT12, PINMUX_FOR_SD1_MODE_1}, ++ {PAD_SD1_D0, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6, PINMUX_FOR_FUART_MODE_4}, ++ ++ {PAD_SD1_CLK, PADTOP_BANK, REG_SD1_CLK_GPIO_MODE, REG_SD1_CLK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD1_CLK, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT5, PINMUX_FOR_EMMC1_4B_MODE_2}, ++ {PAD_SD1_CLK, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT12, PINMUX_FOR_SD1_MODE_1}, ++ {PAD_SD1_CLK, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6, PINMUX_FOR_FUART_MODE_4}, ++ ++ {PAD_SD1_CMD, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT5, PINMUX_FOR_EMMC1_4B_MODE_2}, ++ {PAD_SD1_CMD, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT12, PINMUX_FOR_SD1_MODE_1}, ++ {PAD_SD1_CMD, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT6, PINMUX_FOR_FUART_MODE_4}, ++ {PAD_SD1_CMD, PADTOP_BANK, REG_SD1_CMD_GPIO_MODE, REG_SD1_CMD_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SD1_D3, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT12, PINMUX_FOR_SD1_MODE_1}, ++ {PAD_SD1_D3, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT5, PINMUX_FOR_EMMC1_4B_MODE_2}, ++ {PAD_SD1_D3, PADTOP_BANK, REG_SD1_D3_GPIO_MODE, REG_SD1_D3_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SD1_D2, PADTOP_BANK, REG_EMMC1_4B_MODE, REG_EMMC1_4B_MODE_MASK, BIT5, PINMUX_FOR_EMMC1_4B_MODE_2}, ++ {PAD_SD1_D2, PADTOP_BANK, REG_SD1_D2_GPIO_MODE, REG_SD1_D2_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SD1_D2, PADTOP_BANK, REG_SD1_MODE, REG_SD1_MODE_MASK, BIT12, PINMUX_FOR_SD1_MODE_1}, ++ ++ {PAD_SD1_GPIO0, PADTOP_BANK, REG_SD1_GPIO0_GPIO_MODE, REG_SD1_GPIO0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SD1_GPIO1, PADTOP_BANK, REG_SD1_GPIO1_GPIO_MODE, REG_SD1_GPIO1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_GPIO0, PADTOP_BANK, REG_I2S_MCK_MODE, REG_I2S_MCK_MODE_MASK, BIT1, PINMUX_FOR_I2S_MCK_MODE_2}, ++ {PAD_GPIO0, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1, PINMUX_FOR_DLA_EJ_MODE_2}, ++ {PAD_GPIO0, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO0, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9, PINMUX_FOR_I2C2_MODE_2}, ++ {PAD_GPIO0, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT4, PINMUX_FOR_UART1_MODE_1}, ++ {PAD_GPIO0, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO0, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_GPIO0, PADTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PWM0_MODE_2}, ++ {PAD_GPIO0, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO0, PADTOP_BANK, REG_GPIO0_GPIO_MODE, REG_GPIO0_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO0, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO1, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12, PINMUX_FOR_I2S_RXTX_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT4, PINMUX_FOR_UART1_MODE_1}, ++ {PAD_GPIO1, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1, PINMUX_FOR_DLA_EJ_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO1, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT9, PINMUX_FOR_I2C2_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT5, PINMUX_FOR_I2S_RX_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5, PINMUX_FOR_PWM1_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_GPIO1_GPIO_MODE, REG_GPIO1_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO1, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_GPIO1, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT3, PINMUX_FOR_DMIC_MODE_8}, ++ {PAD_GPIO1, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO1, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO2, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12, PINMUX_FOR_I2S_RXTX_MODE_2}, ++ {PAD_GPIO2, PADTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT9, PINMUX_FOR_PWM2_MODE_2}, ++ {PAD_GPIO2, PADTOP_BANK, REG_GPIO2_GPIO_MODE, REG_GPIO2_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO2, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1, PINMUX_FOR_DLA_EJ_MODE_2}, ++ {PAD_GPIO2, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT5, PINMUX_FOR_I2S_RX_MODE_2}, ++ {PAD_GPIO2, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO2, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_GPIO2, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT3, PINMUX_FOR_DMIC_MODE_8}, ++ {PAD_GPIO2, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO2, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO3, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12, PINMUX_FOR_I2S_RXTX_MODE_2}, ++ {PAD_GPIO3, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1, PINMUX_FOR_DLA_EJ_MODE_2}, ++ {PAD_GPIO3, PADTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT13, PINMUX_FOR_PWM3_MODE_2}, ++ {PAD_GPIO3, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT5, PINMUX_FOR_I2S_RX_MODE_2}, ++ {PAD_GPIO3, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO3, PADTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, ++ {PAD_GPIO3, PADTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT5, PINMUX_FOR_FUART_MODE_2}, ++ {PAD_GPIO3, PADTOP_BANK, REG_GPIO3_GPIO_MODE, REG_GPIO3_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO3, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO4, PADTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT1, PINMUX_FOR_PWM4_MODE_2}, ++ {PAD_GPIO4, PADTOP_BANK, REG_GPIO4_GPIO_MODE, REG_GPIO4_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO4, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT12, PINMUX_FOR_I2S_RXTX_MODE_2}, ++ {PAD_GPIO4, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO4, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT6, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO4, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT9, PINMUX_FOR_I2S_TX_MODE_2}, ++ {PAD_GPIO4, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT10|BIT8, PINMUX_FOR_I2S_TX_MODE_5}, ++ {PAD_GPIO4, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO5, PADTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT5, PINMUX_FOR_PWM5_MODE_2}, ++ {PAD_GPIO5, PADTOP_BANK, REG_GPIO5_GPIO_MODE, REG_GPIO5_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO5, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT6, PINMUX_FOR_UART1_MODE_4}, ++ {PAD_GPIO5, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO5, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT9, PINMUX_FOR_I2S_TX_MODE_2}, ++ {PAD_GPIO5, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO6, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_GPIO6, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO6, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT1, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_GPIO6, PADTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT9, PINMUX_FOR_PWM6_MODE_2}, ++ {PAD_GPIO6, PADTOP_BANK, REG_GPIO6_GPIO_MODE, REG_GPIO6_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO6, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT9, PINMUX_FOR_I2S_TX_MODE_2}, ++ {PAD_GPIO6, PADTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_GPIO7, PADTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT13, PINMUX_FOR_PWM7_MODE_2}, ++ {PAD_GPIO7, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, ++ {PAD_GPIO7, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_GPIO7, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT1, PINMUX_FOR_DMIC_MODE_2}, ++ {PAD_GPIO7, PADTOP_BANK, REG_GPIO7_GPIO_MODE, REG_GPIO7_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1, PINMUX_FOR_SR0_BT656_MODE_2}, ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR00_PDN_MODE, REG_SR00_PDN_MODE_MASK, BIT8, PINMUX_FOR_SR00_PDN_MODE_1}, ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR01_MIPI_MODE, REG_SR01_MIPI_MODE_MASK, BIT10, PINMUX_FOR_SR01_MIPI_MODE}, ++ {PAD_SR0_IO00, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR0_IO00_GPIO_MODE, REG_SR0_IO00_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO00, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO00, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO01, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO01, PADTOP_BANK, REG_SR01_MIPI_MODE, REG_SR01_MIPI_MODE_MASK, BIT10, PINMUX_FOR_SR01_MIPI_MODE}, ++ {PAD_SR0_IO01, PADTOP_BANK, REG_SR0_IO01_GPIO_MODE, REG_SR0_IO01_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO01, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR0_IO01, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR0_IO01, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO01, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1, PINMUX_FOR_SR00_MIPI_MODE_2}, ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR0_IO02_GPIO_MODE, REG_SR0_IO02_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR01_MIPI_MODE, REG_SR01_MIPI_MODE_MASK, BIT10, PINMUX_FOR_SR01_MIPI_MODE}, ++ {PAD_SR0_IO02, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ ++ {PAD_SR0_IO02, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO02, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1, PINMUX_FOR_SR00_MIPI_MODE_2}, ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR0_IO03_GPIO_MODE, REG_SR0_IO03_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR01_MIPI_MODE, REG_SR01_MIPI_MODE_MASK, BIT10, PINMUX_FOR_SR01_MIPI_MODE}, ++ {PAD_SR0_IO03, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ ++ {PAD_SR0_IO03, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, ++ ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO03, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR0_IO04_GPIO_MODE, REG_SR0_IO04_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1, PINMUX_FOR_SR00_MIPI_MODE_2}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT2, PINMUX_FOR_SR00_MIPI_MODE_4}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR01_MIPI_MODE, REG_SR01_MIPI_MODE_MASK, BIT10, PINMUX_FOR_SR01_MIPI_MODE}, ++ {PAD_SR0_IO04, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO04, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO04, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO05, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR0_IO05_GPIO_MODE, REG_SR0_IO05_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1, PINMUX_FOR_SR00_MIPI_MODE_2}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT2, PINMUX_FOR_SR00_MIPI_MODE_4}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR01_MIPI_MODE, REG_SR01_MIPI_MODE_MASK, BIT10, PINMUX_FOR_SR01_MIPI_MODE}, ++ {PAD_SR0_IO05, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO05, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO05, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO06, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1, PINMUX_FOR_SR00_MIPI_MODE_2}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR00_MIPI_MODE_3}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT2, PINMUX_FOR_SR00_MIPI_MODE_4}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR0_IO06_GPIO_MODE, REG_SR0_IO06_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO06, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO06, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO06, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR0_IO07_GPIO_MODE, REG_SR0_IO07_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1, PINMUX_FOR_SR00_MIPI_MODE_2}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR00_MIPI_MODE_3}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT2, PINMUX_FOR_SR00_MIPI_MODE_4}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO07, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO07, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO07, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR0_IO08_GPIO_MODE, REG_SR0_IO08_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR00_MIPI_MODE_3}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT2, PINMUX_FOR_SR00_MIPI_MODE_4}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO08, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO08, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO08, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO09, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR00_MIPI_MODE_3}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT2, PINMUX_FOR_SR00_MIPI_MODE_4}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR0_IO09_GPIO_MODE, REG_SR0_IO09_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO09, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO09, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO09, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO10, PADTOP_BANK, REG_SR0_IO10_GPIO_MODE, REG_SR0_IO10_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO10, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO10, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO10, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR00_MIPI_MODE_3}, ++ {PAD_SR0_IO10, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO10, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO10, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO10, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO10, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO11, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO11, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT0, PINMUX_FOR_SR00_MIPI_MODE_1}, ++ {PAD_SR0_IO11, PADTOP_BANK, REG_SR00_MIPI_MODE, REG_SR00_MIPI_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR00_MIPI_MODE_3}, ++ {PAD_SR0_IO11, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO11, PADTOP_BANK, REG_SR0_IO11_GPIO_MODE, REG_SR0_IO11_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO11, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ ++ {PAD_SR0_IO11, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO11, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO11, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ ++ {PAD_SR0_IO12, PADTOP_BANK, REG_SR0_IO12_GPIO_MODE, REG_SR0_IO12_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO12, PADTOP_BANK, REG_SR01_CTRL_MODE, REG_SR01_CTRL_MODE_MASK, BIT11, PINMUX_FOR_SR01_CTRL_MODE}, ++ {PAD_SR0_IO12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR0_IO12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR0_IO12, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ ++ {PAD_SR0_IO13, PADTOP_BANK, REG_SR01_RST_MODE, REG_SR01_RST_MODE_MASK, BIT13, PINMUX_FOR_SR01_RST_MODE_1}, ++ {PAD_SR0_IO13, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT2|BIT1|BIT0, PINMUX_FOR_PWM8_MODE_7}, ++ {PAD_SR0_IO13, PADTOP_BANK, REG_SR0_IO13_GPIO_MODE, REG_SR0_IO13_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO13, PADTOP_BANK, REG_SR01_CTRL_MODE, REG_SR01_CTRL_MODE_MASK, BIT11, PINMUX_FOR_SR01_CTRL_MODE}, ++ {PAD_SR0_IO13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR0_IO13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ {PAD_SR0_IO13, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR01_MCLK_MODE, REG_SR01_MCLK_MODE_MASK, BIT12, PINMUX_FOR_SR01_MCLK_MODE}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR0_BT656_MODE_1}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR0_BT656_MODE, REG_SR0_BT656_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR0_BT656_MODE_3}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR00_PDN_MODE, REG_SR00_PDN_MODE_MASK, BIT9, PINMUX_FOR_SR00_PDN_MODE_2}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR01_CTRL_MODE, REG_SR01_CTRL_MODE_MASK, BIT11, PINMUX_FOR_SR01_CTRL_MODE}, ++ {PAD_SR0_IO14, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR0_IO14, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT2, PINMUX_FOR_SR0_BT601_MODE_1}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR0_BT601_MODE, REG_SR0_BT601_MODE_MASK, BIT3, PINMUX_FOR_SR0_BT601_MODE_2}, ++ {PAD_SR0_IO14, PADTOP_BANK, REG_SR0_IO14_GPIO_MODE, REG_SR0_IO14_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR0_IO15, PADTOP_BANK, REG_SR00_CTRL_MODE, REG_SR00_CTRL_MODE_MASK, BIT4, PINMUX_FOR_SR00_CTRL_MODE}, ++ {PAD_SR0_IO15, PADTOP_BANK, REG_SR01_RST_MODE, REG_SR01_RST_MODE_MASK, BIT14, PINMUX_FOR_SR01_RST_MODE_2}, ++ {PAD_SR0_IO15, PADTOP_BANK, REG_SR0_IO15_GPIO_MODE, REG_SR0_IO15_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO15, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR0_IO15, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ ++ {PAD_SR0_IO16, PADTOP_BANK, REG_SR0_IO16_GPIO_MODE, REG_SR0_IO16_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO16, PADTOP_BANK, REG_SR00_CTRL_MODE, REG_SR00_CTRL_MODE_MASK, BIT4, PINMUX_FOR_SR00_CTRL_MODE}, ++ {PAD_SR0_IO16, PADTOP_BANK, REG_SR00_RST_MODE, REG_SR00_RST_MODE_MASK, BIT6, PINMUX_FOR_SR00_RST_MODE}, ++ {PAD_SR0_IO16, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO16, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SR0_IO16, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_SR0_IO17, PADTOP_BANK, REG_SR0_IO17_GPIO_MODE, REG_SR0_IO17_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO17, PADTOP_BANK, REG_SR00_CTRL_MODE, REG_SR00_CTRL_MODE_MASK, BIT4, PINMUX_FOR_SR00_CTRL_MODE}, ++ {PAD_SR0_IO17, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO17, PADTOP_BANK, REG_SR00_MCLK_MODE, REG_SR00_MCLK_MODE_MASK, BIT5, PINMUX_FOR_SR00_MCLK_MODE}, ++ {PAD_SR0_IO17, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SR0_IO17, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_SR0_IO18, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO18, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ {PAD_SR0_IO18, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR0_IO18, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SR0_IO18, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_SR0_IO18, PADTOP_BANK, REG_SR0_IO18_GPIO_MODE, REG_SR0_IO18_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR0_IO19, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_SR0_IO19, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, ++ {PAD_SR0_IO19, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR0_IO19, PADTOP_BANK, REG_SR0_IO19_GPIO_MODE, REG_SR0_IO19_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR0_IO19, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, ++ ++ {PAD_SR0_IO19, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ ++ {PAD_SR1_IO00, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_SR1_MCLK_MODE, REG_SR1_MCLK_MODE_MASK, BIT10, PINMUX_FOR_SR1_MCLK_MODE_2}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2, PINMUX_FOR_PWM0_MODE_4}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT2, PINMUX_FOR_PWM8_MODE_4}, ++ {PAD_SR1_IO00, PADTOP_BANK, REG_SR1_IO00_GPIO_MODE, REG_SR1_IO00_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO00, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR1_IO00, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ ++ {PAD_SR1_IO01, PADTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT6, PINMUX_FOR_PWM1_MODE_4}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_SR1_IO01_GPIO_MODE, REG_SR1_IO01_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO01, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR1_IO01, PADTOP_BANK, REG_SR1_RST_MODE, REG_SR1_RST_MODE_MASK, BIT12, PINMUX_FOR_SR1_RST_MODE_2}, ++ {PAD_SR1_IO01, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ ++ {PAD_SR1_IO02, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT10, PINMUX_FOR_PWM2_MODE_4}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1, PINMUX_FOR_MIPI_TX_MODE_2}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_SR1_IO02_GPIO_MODE, REG_SR1_IO02_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO02, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5, PINMUX_FOR_SR1_MIPI_MODE_2}, ++ {PAD_SR1_IO02, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR1_IO02, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ ++ {PAD_SR1_IO03, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT14, PINMUX_FOR_PWM3_MODE_4}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_SR1_IO03_GPIO_MODE, REG_SR1_IO03_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1, PINMUX_FOR_MIPI_TX_MODE_2}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO03, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5, PINMUX_FOR_SR1_MIPI_MODE_2}, ++ {PAD_SR1_IO03, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, ++ {PAD_SR1_IO03, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, ++ ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_IO04_GPIO_MODE, REG_SR1_IO04_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1, PINMUX_FOR_MIPI_TX_MODE_2}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT2, PINMUX_FOR_MIPI_TX_MODE_4}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5, PINMUX_FOR_SR1_MIPI_MODE_2}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6, PINMUX_FOR_SR1_MIPI_MODE_4}, ++ {PAD_SR1_IO04, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SR1_MIPI_MODE_5}, ++ ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_IO05_GPIO_MODE, REG_SR1_IO05_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1, PINMUX_FOR_MIPI_TX_MODE_2}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT2, PINMUX_FOR_MIPI_TX_MODE_4}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5, PINMUX_FOR_SR1_MIPI_MODE_2}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6, PINMUX_FOR_SR1_MIPI_MODE_4}, ++ {PAD_SR1_IO05, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SR1_MIPI_MODE_5}, ++ ++ {PAD_SR1_IO06, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1, PINMUX_FOR_MIPI_TX_MODE_2}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_TX_MODE_3}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT2, PINMUX_FOR_MIPI_TX_MODE_4}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_IO06_GPIO_MODE, REG_SR1_IO06_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5, PINMUX_FOR_SR1_MIPI_MODE_2}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SR1_MIPI_MODE_3}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6, PINMUX_FOR_SR1_MIPI_MODE_4}, ++ {PAD_SR1_IO06, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SR1_MIPI_MODE_5}, ++ ++ {PAD_SR1_IO07, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_IO07_GPIO_MODE, REG_SR1_IO07_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1, PINMUX_FOR_MIPI_TX_MODE_2}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_TX_MODE_3}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT2, PINMUX_FOR_MIPI_TX_MODE_4}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5, PINMUX_FOR_SR1_MIPI_MODE_2}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SR1_MIPI_MODE_3}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6, PINMUX_FOR_SR1_MIPI_MODE_4}, ++ {PAD_SR1_IO07, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6|BIT4, PINMUX_FOR_SR1_MIPI_MODE_5}, ++ ++ {PAD_SR1_IO08, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_SR1_IO08_GPIO_MODE, REG_SR1_IO08_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_TX_MODE_3}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT2, PINMUX_FOR_MIPI_TX_MODE_4}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SR1_MIPI_MODE_3}, ++ {PAD_SR1_IO08, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6, PINMUX_FOR_SR1_MIPI_MODE_4}, ++ ++ {PAD_SR1_IO09, PADTOP_BANK, REG_SR1_IO09_GPIO_MODE, REG_SR1_IO09_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_TX_MODE_3}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT2, PINMUX_FOR_MIPI_TX_MODE_4}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SR1_MIPI_MODE_3}, ++ {PAD_SR1_IO09, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT6, PINMUX_FOR_SR1_MIPI_MODE_4}, ++ ++ {PAD_SR1_IO10, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_TX_MODE_3}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SR1_MIPI_MODE_3}, ++ {PAD_SR1_IO10, PADTOP_BANK, REG_SR1_IO10_GPIO_MODE, REG_SR1_IO10_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR1_IO11, PADTOP_BANK, REG_SR1_IO11_GPIO_MODE, REG_SR1_IO11_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT0, PINMUX_FOR_MIPI_TX_MODE_1}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_MIPI_TX_MODE, REG_MIPI_TX_MODE_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_TX_MODE_3}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT4, PINMUX_FOR_SR1_MIPI_MODE_1}, ++ {PAD_SR1_IO11, PADTOP_BANK, REG_SR1_MIPI_MODE, REG_SR1_MIPI_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SR1_MIPI_MODE_3}, ++ ++ {PAD_SR1_IO12, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO12, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT6, PINMUX_FOR_PWM9_MODE_4}, ++ {PAD_SR1_IO12, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO12, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO12, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO12, PADTOP_BANK, REG_SR1_IO12_GPIO_MODE, REG_SR1_IO12_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR1_IO13, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_SR1_IO13, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO13, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO13, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO13, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO13, PADTOP_BANK, REG_SR1_IO13_GPIO_MODE, REG_SR1_IO13_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR1_IO14, PADTOP_BANK, REG_SR1_IO14_GPIO_MODE, REG_SR1_IO14_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT4, PINMUX_FOR_BT656_OUT_MODE_1}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_SR1_BT656_MODE, REG_SR1_BT656_MODE_MASK, BIT0, PINMUX_FOR_SR1_BT656_MODE}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_SR1_BT601_MODE, REG_SR1_BT601_MODE_MASK, BIT1, PINMUX_FOR_SR1_BT601_MODE}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO14, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ ++ {PAD_SR1_IO15, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO15, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO15, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO15, PADTOP_BANK, REG_SR1_IO15_GPIO_MODE, REG_SR1_IO15_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO15, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO15, PADTOP_BANK, REG_SR1_CTRL_MODE, REG_SR1_CTRL_MODE_MASK, BIT8, PINMUX_FOR_SR1_CTRL_MODE}, ++ ++ {PAD_SR1_IO16, PADTOP_BANK, REG_SR1_CTRL_MODE, REG_SR1_CTRL_MODE_MASK, BIT8, PINMUX_FOR_SR1_CTRL_MODE}, ++ {PAD_SR1_IO16, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO16, PADTOP_BANK, REG_SR1_IO16_GPIO_MODE, REG_SR1_IO16_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO16, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO16, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO16, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO16, PADTOP_BANK, REG_SR1_RST_MODE, REG_SR1_RST_MODE_MASK, BIT11, PINMUX_FOR_SR1_RST_MODE_1}, ++ ++ {PAD_SR1_IO17, PADTOP_BANK, REG_SR1_IO17_GPIO_MODE, REG_SR1_IO17_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO17, PADTOP_BANK, REG_SR1_CTRL_MODE, REG_SR1_CTRL_MODE_MASK, BIT8, PINMUX_FOR_SR1_CTRL_MODE}, ++ {PAD_SR1_IO17, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO17, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO17, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO17, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO17, PADTOP_BANK, REG_SR1_MCLK_MODE, REG_SR1_MCLK_MODE_MASK, BIT9, PINMUX_FOR_SR1_MCLK_MODE_1}, ++ ++ {PAD_SR1_IO18, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT8, PINMUX_FOR_I2C2_MODE_1}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ {PAD_SR1_IO18, PADTOP_BANK, REG_SR1_IO18_GPIO_MODE, REG_SR1_IO18_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SR1_IO19, PADTOP_BANK, REG_I2C2_MODE, REG_I2C2_MODE_MASK, BIT8, PINMUX_FOR_I2C2_MODE_1}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1, PINMUX_FOR_TTL16_MODE_2}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_SR1_IO19_GPIO_MODE, REG_SR1_IO19_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, ++ {PAD_SR1_IO19, PADTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, ++ ++ {PAD_GPIO8, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO8, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_GPIO8, PADTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PWM0_MODE_1}, ++ {PAD_GPIO8, PADTOP_BANK, REG_GPIO8_GPIO_MODE, REG_GPIO8_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO8, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_GPIO8, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO8, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT6, PINMUX_FOR_I2S_RX_MODE_4}, ++ {PAD_GPIO8, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_UART1_MODE_6}, ++ {PAD_GPIO8, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO8, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO8, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13, PINMUX_FOR_I2S_RXTX_MODE_4}, ++ ++ {PAD_GPIO9, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO9, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO9, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT6, PINMUX_FOR_I2S_RX_MODE_4}, ++ {PAD_GPIO9, PADTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT6|BIT5, PINMUX_FOR_UART1_MODE_6}, ++ {PAD_GPIO9, PADTOP_BANK, REG_GPIO9_GPIO_MODE, REG_GPIO9_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO9, PADTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4, PINMUX_FOR_PWM1_MODE_1}, ++ {PAD_GPIO9, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO9, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13, PINMUX_FOR_I2S_RXTX_MODE_4}, ++ ++ {PAD_GPIO10, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO10, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO10, PADTOP_BANK, REG_I2S_RX_MODE, REG_I2S_RX_MODE_MASK, BIT6, PINMUX_FOR_I2S_RX_MODE_4}, ++ {PAD_GPIO10, PADTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8, PINMUX_FOR_PWM2_MODE_1}, ++ {PAD_GPIO10, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO10, PADTOP_BANK, REG_GPIO10_GPIO_MODE, REG_GPIO10_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO10, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13, PINMUX_FOR_I2S_RXTX_MODE_4}, ++ ++ {PAD_GPIO11, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO11, PADTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT12, PINMUX_FOR_PWM3_MODE_1}, ++ {PAD_GPIO11, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO11, PADTOP_BANK, REG_GPIO11_GPIO_MODE, REG_GPIO11_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO11, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO11, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13, PINMUX_FOR_I2S_RXTX_MODE_4}, ++ ++ {PAD_GPIO12, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO12, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO12, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_GPIO12, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_DLA_EJ_MODE_3}, ++ {PAD_GPIO12, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_GPIO12, PADTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT0, PINMUX_FOR_PWM4_MODE_1}, ++ {PAD_GPIO12, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_I2C0_MODE_5}, ++ {PAD_GPIO12, PADTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM8_MODE_5}, ++ {PAD_GPIO12, PADTOP_BANK, REG_GPIO12_GPIO_MODE, REG_GPIO12_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO12, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_GPIO12, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO12, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO12, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2|BIT0, PINMUX_FOR_DMIC_MODE_5}, ++ {PAD_GPIO12, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_GPIO12, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO12, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT10|BIT9, PINMUX_FOR_I2S_TX_MODE_6}, ++ {PAD_GPIO12, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT10|BIT9|BIT8, PINMUX_FOR_I2S_TX_MODE_7}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_GPIO12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_GPIO12, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_RXTX_MODE_6}, ++ ++ {PAD_GPIO13, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO13, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_GPIO13, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_DLA_EJ_MODE_3}, ++ {PAD_GPIO13, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_GPIO13, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO13, PADTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT4, PINMUX_FOR_PWM5_MODE_1}, ++ {PAD_GPIO13, PADTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_I2C0_MODE_5}, ++ {PAD_GPIO13, PADTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT6|BIT4, PINMUX_FOR_PWM9_MODE_5}, ++ {PAD_GPIO13, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO13, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_GPIO13, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO13, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO13, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2|BIT0, PINMUX_FOR_DMIC_MODE_5}, ++ {PAD_GPIO13, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_GPIO13, PADTOP_BANK, REG_GPIO13_GPIO_MODE, REG_GPIO13_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO13, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT10|BIT9, PINMUX_FOR_I2S_TX_MODE_6}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_GPIO13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_GPIO13, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_RXTX_MODE_6}, ++ ++ {PAD_GPIO14, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO14, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_GPIO14, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_DLA_EJ_MODE_3}, ++ {PAD_GPIO14, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_GPIO14, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO14, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO14, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_GPIO14, PADTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT8, PINMUX_FOR_PWM6_MODE_1}, ++ {PAD_GPIO14, PADTOP_BANK, REG_GPIO14_GPIO_MODE, REG_GPIO14_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO14, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO14, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO14, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT2, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_GPIO14, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_GPIO14, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_RXTX_MODE_6}, ++ {PAD_GPIO14, PADTOP_BANK, REG_I2S_TX_MODE, REG_I2S_TX_MODE_MASK, BIT10|BIT9, PINMUX_FOR_I2S_TX_MODE_6}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_GPIO14, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ ++ {PAD_GPIO15, PADTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT12, PINMUX_FOR_PWM7_MODE_1}, ++ {PAD_GPIO15, PADTOP_BANK, REG_I2S_MCK_MODE, REG_I2S_MCK_MODE_MASK, BIT2, PINMUX_FOR_I2S_MCK_MODE_4}, ++ {PAD_GPIO15, PADTOP_BANK, REG_DLA_EJ_MODE, REG_DLA_EJ_MODE_MASK, BIT1|BIT0, PINMUX_FOR_DLA_EJ_MODE_3}, ++ {PAD_GPIO15, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT0, PINMUX_FOR_TTL16_MODE_1}, ++ {PAD_GPIO15, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TTL16_MODE_3}, ++ {PAD_GPIO15, PADTOP_BANK, REG_TTL16_MODE, REG_TTL16_MODE_MASK, BIT2, PINMUX_FOR_TTL16_MODE_4}, ++ {PAD_GPIO15, PADTOP_BANK, REG_OTP_TEST, REG_OTP_TEST_MASK, BIT8, PINMUX_FOR_OTP_TEST}, ++ {PAD_GPIO15, PADTOP_BANK, REG_GPIO15_GPIO_MODE, REG_GPIO15_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_GPIO15, PADTOP_BANK, REG_TTL24_MODE, REG_TTL24_MODE_MASK, BIT4, PINMUX_FOR_TTL24_MODE}, ++ {PAD_GPIO15, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, ++ {PAD_GPIO15, PADTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT2, PINMUX_FOR_UART0_MODE_4}, ++ {PAD_GPIO15, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT2, PINMUX_FOR_EMMC0_8B_MODE_2}, ++ {PAD_GPIO15, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5, PINMUX_FOR_BT656_OUT_MODE_2}, ++ {PAD_GPIO15, PADTOP_BANK, REG_BT656_OUT_MODE, REG_BT656_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_BT656_OUT_MODE_3}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, ++ {PAD_GPIO15, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, ++ {PAD_GPIO15, PADTOP_BANK, REG_I2S_RXTX_MODE, REG_I2S_RXTX_MODE_MASK, BIT13|BIT12, PINMUX_FOR_I2S_RXTX_MODE_6}, ++ ++ {PAD_SPI_CZ, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2|BIT1|BIT0, PINMUX_FOR_DMIC_MODE_7}, ++ {PAD_SPI_CZ, PADTOP_BANK, REG_SPICSZ1_GPIO, REG_SPICSZ1_GPIO_MASK, 0, PINMUX_FOR_SPICSZ1_MODE}, ++ {PAD_SPI_CZ, PADTOP_BANK, REG_SPI_CZ_GPIO_MODE, REG_SPI_CZ_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SPI_CZ, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ ++ {PAD_SPI_CK, PADTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT2|BIT1|BIT0, PINMUX_FOR_DMIC_MODE_7}, ++ {PAD_SPI_CK, PADTOP_BANK, REG_SPI_CK_GPIO_MODE, REG_SPI_CK_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SPI_CK, PADTOP_BANK, REG_SPI_GPIO, REG_SPI_GPIO_MASK, 0, PINMUX_FOR_SPI_MODE}, ++ {PAD_SPI_CK, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ ++ {PAD_SPI_DI, PADTOP_BANK, REG_SPI_DI_GPIO_MODE, REG_SPI_DI_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SPI_DI, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SPI_DI, PADTOP_BANK, REG_SPI_GPIO, REG_SPI_GPIO_MASK, 0, PINMUX_FOR_SPI_MODE}, ++ {PAD_SPI_DI, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ ++ {PAD_SPI_DO, PADTOP_BANK, REG_SPI_DO_GPIO_MODE, REG_SPI_DO_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ {PAD_SPI_DO, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SPI_DO, PADTOP_BANK, REG_SPI_GPIO, REG_SPI_GPIO_MASK, 0, PINMUX_FOR_SPI_MODE}, ++ {PAD_SPI_DO, PADTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, ++ ++ {PAD_SPI_WPZ, PADTOP_BANK, REG_SPIWPN_GPIO, REG_SPIWPN_GPIO_MASK, 0, PINMUX_FOR_SPIWPN_MODE}, ++ {PAD_SPI_WPZ, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SPI_WPZ, PADTOP_BANK, REG_SPI_WPZ_GPIO_MODE, REG_SPI_WPZ_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++ {PAD_SPI_HLD, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_SPI_HLD, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ {PAD_SPI_HLD, PADTOP_BANK, REG_SPI_HLD_GPIO_MODE, REG_SPI_HLD_GPIO_MODE_MASK, BIT3, PINMUX_FOR_GPIO_MODE}, ++ ++#if 0 ++ {PAD_ETH_RN, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_ETH_RN, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ ++ {PAD_ETH_RP, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_ETH_RP, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ ++ {PAD_ETH_TN, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_ETH_TN, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ ++ {PAD_ETH_TP, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_ETH_TP, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ ++ {PAD_USB2_DM, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_USB2_DM, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++ ++ {PAD_USB2_DP, PADTOP_BANK, REG_SPIHOLDN_GPIO, REG_SPIHOLDN_GPIO_MASK, 0, PINMUX_FOR_SPIHOLDN_MODE}, ++ {PAD_USB2_DP, PADTOP_BANK, REG_EMMC0_8B_MODE, REG_EMMC0_8B_MODE_MASK, BIT1, PINMUX_FOR_EMMC0_8B_MODE_1}, ++#endif ++}; ++ ++static const ST_PadModeInfo m_stPadModeInfoTbl[] = ++{ ++ {"GPIO", 0, 0}, ++ // Non PM ++ {"EJ_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"EJ_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"EJ_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, ++ {"DLA_EJ_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_DLA_EJ_MODE), REG_DLA_EJ_MODE_MASK}, ++ {"DLA_EJ_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_DLA_EJ_MODE), REG_DLA_EJ_MODE_MASK}, ++ {"DLA_EJ_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_DLA_EJ_MODE), REG_DLA_EJ_MODE_MASK}, ++ {"TEST_IN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_IN_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, ++ {"TEST_OUT_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"TEST_OUT_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, ++ {"SPI_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SPI_GPIO), REG_SPI_GPIO_MASK}, ++ {"SPIWPN_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SPIWPN_GPIO), REG_SPIWPN_GPIO_MASK}, ++ {"SPIHOLDN_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SPIHOLDN_GPIO), REG_SPIHOLDN_GPIO_MASK}, ++ {"SPICSZ1_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SPICSZ1_GPIO), REG_SPICSZ1_GPIO_MASK}, ++ {"SPICSZ2_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SPICSZ2_GPIO), REG_SPICSZ2_GPIO_MASK}, ++ {"I2C0_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C0_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, ++ {"I2C1_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C1_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, ++ {"I2C2_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2C2_MODE), REG_I2C2_MODE_MASK}, ++ {"I2C2_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2C2_MODE), REG_I2C2_MODE_MASK}, ++ {"I2C2_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2C2_MODE), REG_I2C2_MODE_MASK}, ++ {"I2C2_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_I2C2_MODE), REG_I2C2_MODE_MASK}, ++ {"I2C2_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_I2C2_MODE), REG_I2C2_MODE_MASK}, ++ {"SPI0_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI0_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, ++ {"SPI1_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"SPI1_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, ++ {"FUART_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"FUART_MODE_7", _RIUA_16BIT(PADTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, ++ {"UART0_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART0_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, ++ {"UART1_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"UART1_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, ++ {"SD0_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SD0_MODE), REG_SD0_MODE_MASK}, ++ {"SD0_CDZ_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SD0_CDZ_MODE), REG_SD0_CDZ_MODE_MASK}, ++ {"SD1_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SD1_MODE), REG_SD1_MODE_MASK}, ++ {"SD1_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SD1_MODE), REG_SD1_MODE_MASK}, ++ {"SD1_CDZ_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SD1_CDZ_MODE), REG_SD1_CDZ_MODE_MASK}, ++ {"SD1_CDZ_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SD1_CDZ_MODE), REG_SD1_CDZ_MODE_MASK}, ++ {"EMMC0_8B_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_EMMC0_8B_MODE), REG_EMMC0_8B_MODE_MASK}, ++ {"EMMC0_8B_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_EMMC0_8B_MODE), REG_EMMC0_8B_MODE_MASK}, ++ {"EMMC0_4B_MODE", _RIUA_16BIT(PADTOP_BANK,REG_EMMC0_4B_MODE), REG_EMMC0_4B_MODE_MASK}, ++ {"EMMC1_4B_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_EMMC1_4B_MODE), REG_EMMC1_4B_MODE_MASK}, ++ {"EMMC1_4B_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_EMMC1_4B_MODE), REG_EMMC1_4B_MODE_MASK}, ++ {"EMMC0_RST_MODE", _RIUA_16BIT(PADTOP_BANK,REG_EMMC0_RST_MODE), REG_EMMC0_RST_MODE_MASK}, ++ {"EMMC1_RST_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_EMMC1_RST_MODE), REG_EMMC1_RST_MODE_MASK}, ++ {"EMMC1_RST_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_EMMC1_RST_MODE), REG_EMMC1_RST_MODE_MASK}, ++ {"PWM0_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM0_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, ++ {"PWM1_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM1_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, ++ {"PWM2_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM2_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, ++ {"PWM3_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM3_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, ++ {"PWM4_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM4_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, ++ {"PWM5_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM5_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, ++ {"PWM6_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM6_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, ++ {"PWM7_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM7_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, ++ {"PWM8_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_7", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM8_MODE_8", _RIUA_16BIT(PADTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, ++ {"PWM9_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_7", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"PWM9_MODE_8", _RIUA_16BIT(PADTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, ++ {"ETH_MODE", _RIUA_16BIT(PADTOP_BANK,REG_ETH_MODE), REG_ETH_MODE_MASK}, ++ {"LED0_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_LED0_MODE), REG_LED0_MODE_MASK}, ++ {"LED0_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_LED0_MODE), REG_LED0_MODE_MASK}, ++ {"LED0_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_LED0_MODE), REG_LED0_MODE_MASK}, ++ {"LED0_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_LED0_MODE), REG_LED0_MODE_MASK}, ++ {"LED1_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_LED1_MODE), REG_LED1_MODE_MASK}, ++ {"LED1_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_LED1_MODE), REG_LED1_MODE_MASK}, ++ {"LED1_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_LED1_MODE), REG_LED1_MODE_MASK}, ++ {"LED1_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_LED1_MODE), REG_LED1_MODE_MASK}, ++ {"I2S_MCK_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2S_MCK_MODE), REG_I2S_MCK_MODE_MASK}, ++ {"I2S_MCK_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2S_MCK_MODE), REG_I2S_MCK_MODE_MASK}, ++ {"I2S_MCK_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2S_MCK_MODE), REG_I2S_MCK_MODE_MASK}, ++ {"I2S_MCK_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_I2S_MCK_MODE), REG_I2S_MCK_MODE_MASK}, ++ {"I2S_RX_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RX_MODE), REG_I2S_RX_MODE_MASK}, ++ {"I2S_RX_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RX_MODE), REG_I2S_RX_MODE_MASK}, ++ {"I2S_RX_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RX_MODE), REG_I2S_RX_MODE_MASK}, ++ {"I2S_RX_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RX_MODE), REG_I2S_RX_MODE_MASK}, ++ {"I2S_TX_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_TX_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_TX_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_TX_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_TX_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_TX_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_TX_MODE_7", _RIUA_16BIT(PADTOP_BANK,REG_I2S_TX_MODE), REG_I2S_TX_MODE_MASK}, ++ {"I2S_RXTX_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RXTX_MODE), REG_I2S_RXTX_MODE_MASK}, ++ {"I2S_RXTX_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RXTX_MODE), REG_I2S_RXTX_MODE_MASK}, ++ {"I2S_RXTX_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RXTX_MODE), REG_I2S_RXTX_MODE_MASK}, ++ {"I2S_RXTX_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RXTX_MODE), REG_I2S_RXTX_MODE_MASK}, ++ {"I2S_RXTX_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RXTX_MODE), REG_I2S_RXTX_MODE_MASK}, ++ {"I2S_RXTX_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_I2S_RXTX_MODE), REG_I2S_RXTX_MODE_MASK}, ++ {"DMIC_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_6", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_7", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"DMIC_MODE_8", _RIUA_16BIT(PADTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, ++ {"SR00_MIPI_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR00_MIPI_MODE), REG_SR00_MIPI_MODE_MASK}, ++ {"SR00_MIPI_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR00_MIPI_MODE), REG_SR00_MIPI_MODE_MASK}, ++ {"SR00_MIPI_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_SR00_MIPI_MODE), REG_SR00_MIPI_MODE_MASK}, ++ {"SR00_MIPI_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_SR00_MIPI_MODE), REG_SR00_MIPI_MODE_MASK}, ++ {"SR00_CTRL_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR00_CTRL_MODE), REG_SR00_CTRL_MODE_MASK}, ++ {"SR00_MCLK_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR00_MCLK_MODE), REG_SR00_MCLK_MODE_MASK}, ++ {"SR00_RST_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR00_RST_MODE), REG_SR00_RST_MODE_MASK}, ++ {"SR00_PDN_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR00_PDN_MODE), REG_SR00_PDN_MODE_MASK}, ++ {"SR00_PDN_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR00_PDN_MODE), REG_SR00_PDN_MODE_MASK}, ++ {"SR01_MIPI_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR01_MIPI_MODE), REG_SR01_MIPI_MODE_MASK}, ++ {"SR01_CTRL_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR01_CTRL_MODE), REG_SR01_CTRL_MODE_MASK}, ++ {"SR01_MCLK_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR01_MCLK_MODE), REG_SR01_MCLK_MODE_MASK}, ++ {"SR01_RST_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR01_RST_MODE), REG_SR01_RST_MODE_MASK}, ++ {"SR01_RST_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR01_RST_MODE), REG_SR01_RST_MODE_MASK}, ++ {"SR0_BT601_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR0_BT601_MODE), REG_SR0_BT601_MODE_MASK}, ++ {"SR0_BT601_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR0_BT601_MODE), REG_SR0_BT601_MODE_MASK}, ++ {"SR0_BT656_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR0_BT656_MODE), REG_SR0_BT656_MODE_MASK}, ++ {"SR0_BT656_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR0_BT656_MODE), REG_SR0_BT656_MODE_MASK}, ++ {"SR0_BT656_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_SR0_BT656_MODE), REG_SR0_BT656_MODE_MASK}, ++ {"SR1_MIPI_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MIPI_MODE), REG_SR1_MIPI_MODE_MASK}, ++ {"SR1_MIPI_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MIPI_MODE), REG_SR1_MIPI_MODE_MASK}, ++ {"SR1_MIPI_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MIPI_MODE), REG_SR1_MIPI_MODE_MASK}, ++ {"SR1_MIPI_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MIPI_MODE), REG_SR1_MIPI_MODE_MASK}, ++ {"SR1_MIPI_MODE_5", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MIPI_MODE), REG_SR1_MIPI_MODE_MASK}, ++ {"SR1_CTRL_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR1_CTRL_MODE), REG_SR1_CTRL_MODE_MASK}, ++ {"SR1_MCLK_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MCLK_MODE), REG_SR1_MCLK_MODE_MASK}, ++ {"SR1_MCLK_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR1_MCLK_MODE), REG_SR1_MCLK_MODE_MASK}, ++ {"SR1_RST_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_SR1_RST_MODE), REG_SR1_RST_MODE_MASK}, ++ {"SR1_RST_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_SR1_RST_MODE), REG_SR1_RST_MODE_MASK}, ++ {"SR1_BT601_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR1_BT601_MODE), REG_SR1_BT601_MODE_MASK}, ++ {"SR1_BT656_MODE", _RIUA_16BIT(PADTOP_BANK,REG_SR1_BT656_MODE), REG_SR1_BT656_MODE_MASK}, ++ {"MIPI_TX_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_MIPI_TX_MODE), REG_MIPI_TX_MODE_MASK}, ++ {"MIPI_TX_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_MIPI_TX_MODE), REG_MIPI_TX_MODE_MASK}, ++ {"MIPI_TX_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_MIPI_TX_MODE), REG_MIPI_TX_MODE_MASK}, ++ {"MIPI_TX_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_MIPI_TX_MODE), REG_MIPI_TX_MODE_MASK}, ++ {"TTL24_MODE", _RIUA_16BIT(PADTOP_BANK,REG_TTL24_MODE), REG_TTL24_MODE_MASK}, ++ {"TTL16_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_TTL16_MODE), REG_TTL16_MODE_MASK}, ++ {"TTL16_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_TTL16_MODE), REG_TTL16_MODE_MASK}, ++ {"TTL16_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_TTL16_MODE), REG_TTL16_MODE_MASK}, ++ {"TTL16_MODE_4", _RIUA_16BIT(PADTOP_BANK,REG_TTL16_MODE), REG_TTL16_MODE_MASK}, ++ {"BT656_OUT_MODE_1", _RIUA_16BIT(PADTOP_BANK,REG_BT656_OUT_MODE), REG_BT656_OUT_MODE_MASK}, ++ {"BT656_OUT_MODE_2", _RIUA_16BIT(PADTOP_BANK,REG_BT656_OUT_MODE), REG_BT656_OUT_MODE_MASK}, ++ {"BT656_OUT_MODE_3", _RIUA_16BIT(PADTOP_BANK,REG_BT656_OUT_MODE), REG_BT656_OUT_MODE_MASK}, ++ {"OTP_TEST", _RIUA_16BIT(PADTOP_BANK,REG_OTP_TEST), REG_OTP_TEST_MASK}, ++ // PM Sleep and PM PADTOP ++ {"PM_SPI_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_GPIO), REG_PM_SPI_GPIO_MASK}, ++ {"PM_SPIWPN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIWPN_GPIO), REG_PM_SPIWPN_GPIO_MASK}, ++ {"PM_SPIHOLDN_MODE", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_SPIHOLDN_MODE), REG_PM_SPIHOLDN_MODE_MASK}, ++ {"PM_SPICSZ1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ1_GPIO), REG_PM_SPICSZ1_GPIO_MASK}, ++ {"PM_SPICSZ2_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_GPIO), REG_PM_SPICSZ2_GPIO_MASK}, ++ {"PM_VID_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_VID_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, ++ {"PM_PIR_SERIN_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PIR_SERIN_MODE), REG_PM_PIR_SERIN_MODE_MASK}, ++ {"PM_PIR_SERIN_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PIR_SERIN_MODE), REG_PM_PIR_SERIN_MODE_MASK}, ++ {"PM_PIR_DIR_LINK_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PIR_DIR_LINK_MODE), REG_PM_PIR_DIR_LINK_MODE_MASK}, ++ {"PM_PIR_DIR_LINK_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PIR_DIR_LINK_MODE), REG_PM_PIR_DIR_LINK_MODE_MASK}, ++ {"PM_I2CM_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_I2CM_MODE), REG_PM_I2CM_MODE_MASK}, ++ {"PM_I2CM_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_I2CM_MODE), REG_PM_I2CM_MODE_MASK}, ++ {"PM_PWM0_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_PWM0_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, ++ {"PM_UART1_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_UART1_MODE), REG_PM_UART1_MODE_MASK}, ++ {"PM_UART1_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_UART1_MODE), REG_PM_UART1_MODE_MASK}, ++ {"PM_PM51_UART_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM51_UART_MODE), REG_PM_PM51_UART_MODE_MASK}, ++ {"PM_PM51_UART_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM51_UART_MODE), REG_PM_PM51_UART_MODE_MASK}, ++ {"PM_PM51_UART_MODE_3", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM51_UART_MODE), REG_PM_PM51_UART_MODE_MASK}, ++ {"PM_PM_PAD_EXT_MODE_0", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_0), REG_PM_PM_PAD_EXT_MODE_0_MASK}, ++ {"PM_PM_PAD_EXT_MODE_1", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_1), REG_PM_PM_PAD_EXT_MODE_1_MASK}, ++ {"PM_PM_PAD_EXT_MODE_2", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_2), REG_PM_PM_PAD_EXT_MODE_2_MASK}, ++ {"PM_PM_PAD_EXT_MODE_3", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_3), REG_PM_PM_PAD_EXT_MODE_3_MASK}, ++ {"PM_PM_PAD_EXT_MODE_4", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_4), REG_PM_PM_PAD_EXT_MODE_4_MASK}, ++ {"PM_PM_PAD_EXT_MODE_5", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_5), REG_PM_PM_PAD_EXT_MODE_5_MASK}, ++ {"PM_PM_PAD_EXT_MODE_6", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_6), REG_PM_PM_PAD_EXT_MODE_6_MASK}, ++ {"PM_PM_PAD_EXT_MODE_7", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_7), REG_PM_PM_PAD_EXT_MODE_7_MASK}, ++ {"PM_PM_PAD_EXT_MODE_8", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_8), REG_PM_PM_PAD_EXT_MODE_8_MASK}, ++ {"PM_PM_PAD_EXT_MODE_9", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_9), REG_PM_PM_PAD_EXT_MODE_9_MASK}, ++ {"PM_PM_PAD_EXT_MODE_10", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_10), REG_PM_PM_PAD_EXT_MODE_10_MASK}, ++ {"PM_PM_PAD_EXT_MODE_11", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_11), REG_PM_PM_PAD_EXT_MODE_11_MASK}, ++ {"PM_PM_PAD_EXT_MODE_12", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_12), REG_PM_PM_PAD_EXT_MODE_12_MASK}, ++ {"PM_PM_PAD_EXT_MODE_13", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_13), REG_PM_PM_PAD_EXT_MODE_13_MASK}, ++ {"PM_PM_PAD_EXT_MODE_14", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_14), REG_PM_PM_PAD_EXT_MODE_14_MASK}, ++ {"PM_PM_PAD_EXT_MODE_15", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_15), REG_PM_PM_PAD_EXT_MODE_15_MASK}, ++ {"PM_PM_PAD_EXT_MODE_16", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_16), REG_PM_PM_PAD_EXT_MODE_16_MASK}, ++ {"PM_PM_PAD_EXT_MODE_17", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_17), REG_PM_PM_PAD_EXT_MODE_17_MASK}, ++ {"PM_PM_PAD_EXT_MODE_18", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_18), REG_PM_PM_PAD_EXT_MODE_18_MASK}, ++ {"PM_PM_PAD_EXT_MODE_19", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_19), REG_PM_PM_PAD_EXT_MODE_19_MASK}, ++ {"PM_PM_PAD_EXT_MODE_20", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_20), REG_PM_PM_PAD_EXT_MODE_20_MASK}, ++ {"PM_PM_PAD_EXT_MODE_21", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_21), REG_PM_PM_PAD_EXT_MODE_21_MASK}, ++ {"PM_PM_PAD_EXT_MODE_22", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_PM_PAD_EXT_MODE_22), REG_PM_PM_PAD_EXT_MODE_22_MASK}, ++ {"PM_PM_UART_IS_MODE", _RIUA_16BIT(PM_PADTOP_BANK,REG_PM_UART_IS_GPIO), REG_PM_UART_IS_GPIO_MASK}, ++ {"PM_SAR_MODE", _RIUA_16BIT(PM_SAR_BANK,REG_SAR_GPIO0_GPIO_MODE), REG_SAR_GPIO_MODE_MASK}, ++}; ++ ++//============================================================================== ++// ++// FUNCTIONS ++// ++//============================================================================== ++ ++//------------------------------------------------------------------------------ ++// Function : _HalCheckPin ++// Description : ++//------------------------------------------------------------------------------ ++static S32 _HalCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++#if 0 ++static void _HalSARGPIOWriteRegBit(u32 u32RegOffset, bool bEnable, U8 u8BitMsk) ++{ ++ if (bEnable) ++ _GPIO_R_BYTE(_RIUA_8BIT(PM_SAR_BANK, u32RegOffset)) |= u8BitMsk; ++ else ++ _GPIO_R_BYTE(_RIUA_8BIT(PM_SAR_BANK, u32RegOffset)) &= (~u8BitMsk); ++} ++#endif ++ ++static void _HalPadDisablePadMux(U32 u32PadModeID) ++{ ++ if (_GPIO_R_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask)) { ++ _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, 0, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask); ++ } ++} ++ ++static S32 HalPadSetMode_General(U32 u32PadID, U32 u32Mode) ++{ ++ U32 u32RegAddr = 0; ++ U16 u16RegVal = 0; ++ U8 u8ModeIsFind = 0; ++ U16 i = 0; ++ ++ for (i = 0; i < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); i++) ++ { ++ if (u32PadID == m_stPadMuxTbl[i].padID) ++ { ++ u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[i].base, m_stPadMuxTbl[i].offset); ++ ++ if (u32Mode == m_stPadMuxTbl[i].mode) ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stPadMuxTbl[i].mask); ++ u16RegVal |= m_stPadMuxTbl[i].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ ++ u8ModeIsFind = 1; ++#if (ENABLE_CHECK_ALL_PAD_CONFLICT == 0) ++ break; ++#endif ++ } ++ else ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask); ++ if (u16RegVal == m_stPadMuxTbl[i].val) ++ { ++ printk(KERN_INFO"[Padmux]reset PAD%d(reg 0x%x:%x; mask0x%x) t0 %s (org: %s)\n", ++ u32PadID, ++ m_stPadMuxTbl[i].base, ++ m_stPadMuxTbl[i].offset, ++ m_stPadMuxTbl[i].mask, ++ m_stPadModeInfoTbl[u32Mode].u8PadName, ++ m_stPadModeInfoTbl[m_stPadMuxTbl[i].mode].u8PadName); ++ if (m_stPadMuxTbl[i].val != 0) ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stPadMuxTbl[i].mask); ++ } ++ else ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask, m_stPadMuxTbl[i].mask); ++ } ++ } ++ } ++ } ++ else if (u8ModeIsFind) ++ break; ++ } ++ ++ return (u8ModeIsFind) ? 0 : -1; ++} ++ ++static S32 HalPadSetMode_GeneralPMPad(U32 u32PadID, U32 u32Mode) ++{ ++ U32 u32RegAddr = 0; ++ U16 u16RegVal = 0; ++ U8 u8ModeIsFind = 0; ++ U16 i = 0, ExtItemID = 0; ++ U32 SetBank = 0; ++ ++ for (i = 0; i < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); i++) ++ { ++ if (u32PadID == m_stPadMuxTbl[i].padID) ++ { ++ u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[i].base, m_stPadMuxTbl[i].offset); ++ ++ if (u32Mode == m_stPadMuxTbl[i].mode) ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stPadMuxTbl[i].mask); ++ u16RegVal |= m_stPadMuxTbl[i].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ ++ u8ModeIsFind = 1; ++ SetBank = m_stPadMuxTbl[i].base; ++#if (ENABLE_CHECK_ALL_PAD_CONFLICT == 0) ++ break; ++#endif ++ } ++ else if ((m_stPadMuxTbl[i].mode >= PINMUX_FOR_PM_PM_PAD_EXT_MODE_0) && ++ (m_stPadMuxTbl[i].mode <= PINMUX_FOR_PM_PM_PAD_EXT_MODE_22)) { ++ ExtItemID = i; ++ } ++ else ++ { ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask); ++ if (u16RegVal == m_stPadMuxTbl[i].val) ++ { ++ printk(KERN_INFO"[Padmux]reset PAD%d(reg 0x%x:%x; mask0x%x) t0 %s (org: %s)\n", ++ u32PadID, ++ m_stPadMuxTbl[i].base, ++ m_stPadMuxTbl[i].offset, ++ m_stPadMuxTbl[i].mask, ++ m_stPadModeInfoTbl[u32Mode].u8PadName, ++ m_stPadModeInfoTbl[m_stPadMuxTbl[i].mode].u8PadName); ++ if (m_stPadMuxTbl[i].val != 0) ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stPadMuxTbl[i].mask); ++ } ++ else ++ { ++ _GPIO_W_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask, m_stPadMuxTbl[i].mask); ++ } ++ } ++ } ++ } ++ else if (u8ModeIsFind) ++ break; ++ } ++ ++ if (u8ModeIsFind && ((SetBank >> 8) > 0x1000)) { ++ // set external data mode ++ u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[ExtItemID].base, m_stPadMuxTbl[ExtItemID].offset); ++ u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); ++ u16RegVal &= ~(m_stPadMuxTbl[ExtItemID].mask); ++ u16RegVal |= m_stPadMuxTbl[ExtItemID].val; // CHECK Multi-Pad Mode ++ ++ _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); ++ } ++ ++ return (u8ModeIsFind) ? 0 : -1; ++} ++ ++static S32 HalPadSetMode_MISC(U32 u32PadID, U32 u32Mode) ++{ ++ switch(u32PadID) ++ { ++ /* SAR */ ++ case PAD_SAR_GPIO0: /* reg_sar_aisel; reg[1422]#5 ~ #0=0b */ ++ case PAD_SAR_GPIO1: ++ case PAD_SAR_GPIO2: ++ case PAD_SAR_GPIO3: ++ case PAD_SAR_GPIO4: ++ case PAD_SAR_GPIO5: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PM_SAR_BANK,REG_SAR_GPIO0_GPIO_MODE), 0, 1<<(u32PadID-PAD_SAR_GPIO0)); ++ } ++ else if (u32Mode == PINMUX_FOR_PM_SAR_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(PM_SAR_BANK,REG_SAR_GPIO0_GPIO_MODE), 1<<(u32PadID-PAD_SAR_GPIO0), 1<<(u32PadID-PAD_SAR_GPIO0)); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ /* lan-top */ ++ case PAD_ETH_RN: ++ case PAD_ETH_RP: ++ case PAD_ETH_TN: ++ case PAD_ETH_TP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 1<<(u32PadID-PAD_ETH_RN), 1<<(u32PadID-PAD_ETH_RN)); ++ } ++ else if (u32Mode == PINMUX_FOR_ETH_MODE) ++ { ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); ++ _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, 1<<(u32PadID-PAD_ETH_RN)); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ /* UTMI */ ++ case PAD_USB2_DM: ++ case PAD_USB2_DP: ++ if (u32Mode == PINMUX_FOR_GPIO_MODE) ++ { ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE); ++ //_HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), ~REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), ~REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), ~REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else if (u32Mode == PINMUX_FOR_USB_MODE) ++ { ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), ~REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); ++ _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); ++ } ++ else ++ { ++ return -1; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalPadSetVal ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetVal(U32 u32PadID, U32 u32Mode) ++{ ++ if (FALSE == _HalCheckPin(u32PadID)) { ++ return FALSE; ++ } ++ if((u32PadID >= PAD_SAR_GPIO0 && u32PadID <= PAD_SAR_GPIO5) || ++ (u32PadID >= PAD_ETH_RN && u32PadID <= PAD_USB2_DP)) ++ { ++ return HalPadSetMode_MISC(u32PadID, u32Mode); ++ } ++ if (u32PadID >= PAD_PM_UART_RX1 && u32PadID <= PAD_PM_SPI_HLD) { ++ return HalPadSetMode_GeneralPMPad(u32PadID, u32Mode); ++ } ++ else ++ { ++ return HalPadSetMode_General(u32PadID, u32Mode); ++ } ++ ++} ++//------------------------------------------------------------------------------ ++// Function : HalPadSet ++// Description : ++//------------------------------------------------------------------------------ ++S32 HalPadSetMode(U32 u32Mode) ++{ ++ U32 u32PadID; ++ U16 k = 0; ++ ++ for (k = 0; k < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); k++) ++ { ++ if (u32Mode == m_stPadMuxTbl[k].mode) ++ { ++ u32PadID = m_stPadMuxTbl[k].padID; ++ if (HalPadSetMode_General( u32PadID, u32Mode) < 0) ++ { ++ return -1; ++ } ++ } ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/gpio/infinity6e/mhal_pinmux.h b/drivers/sstar/gpio/infinity6e/mhal_pinmux.h +new file mode 100644 +index 000000000000..32594933c756 +--- /dev/null ++++ b/drivers/sstar/gpio/infinity6e/mhal_pinmux.h +@@ -0,0 +1,9 @@ ++#ifndef __MHAL_PINMUX_H__ ++#define __MHAL_PINMUX_H__ ++ ++#include "mdrv_types.h" ++ ++extern S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++extern S32 HalPadSetMode(U32 u32Mode); ++ ++#endif // __MHAL_PINMUX_H__ +diff --git a/drivers/sstar/gpio/mdrv_gpio.c b/drivers/sstar/gpio/mdrv_gpio.c +new file mode 100755 +index 000000000000..ea5b0b6eadb8 +--- /dev/null ++++ b/drivers/sstar/gpio/mdrv_gpio.c +@@ -0,0 +1,208 @@ ++/* ++* mdrv_gpio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++ ++#include "mdrv_gpio.h" ++#include "mhal_gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// GPIO chiptop initialization ++/// @return None ++/// @note Called only once at system initialization ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Init(void) ++{ ++ MHal_GPIO_Init(); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// select one pad to set to GPIO mode ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pad_Set(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// set the specified pad mode( a set of GPIO pad will be effected) ++/// @param u8PadMode \b IN: pad mode ++/// @return 0: success; -1: fail or not supported ++/// @note ++//------------------------------------------------------------------------------------------------- ++int MDrv_GPIO_PadGroupMode_Set(U32 u32PadMode) ++{ ++ return MHal_GPIO_PadGroupMode_Set(u32PadMode); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// set a pad to the specified mode ++/// @param u8PadMode \b IN: pad mode ++/// @return 0: success; -1: fail or not supported ++/// @note ++//------------------------------------------------------------------------------------------------- ++int MDrv_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode) ++{ ++ return MHal_GPIO_PadVal_Set(u8IndexGPIO, u32PadMode); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// enable output for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pad_Oen(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// enable input for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pad_Odn(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// read data from selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO) ++{ ++ return MHal_GPIO_Pad_Level(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// read pad direction for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return MHal_GPIO_Pad_InOut(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// output pull high for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pull_High(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// output pull low for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pull_Low(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// output set high for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Set_High(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// output set low for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Set_Low(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// enable GPIO int for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ MHal_Enable_GPIO_INT(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// enable GPIO int for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++int MDrv_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ return MHal_GPIO_To_Irq(u8IndexGPIO); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// set GPIO int polarity for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse) ++{ ++ MHal_GPIO_Set_POLARITY(u8IndexGPIO, reverse); ++} ++ ++EXPORT_SYMBOL(MDrv_GPIO_Init); ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Set); ++EXPORT_SYMBOL(MDrv_GPIO_PadGroupMode_Set); ++EXPORT_SYMBOL(MDrv_GPIO_PadVal_Set); ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Oen); ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Odn); ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Read); ++EXPORT_SYMBOL(MDrv_GPIO_Pad_InOut); ++EXPORT_SYMBOL(MDrv_GPIO_Pull_High); ++EXPORT_SYMBOL(MDrv_GPIO_Pull_Low); ++EXPORT_SYMBOL(MDrv_GPIO_Set_High); ++EXPORT_SYMBOL(MDrv_GPIO_Set_Low); ++EXPORT_SYMBOL(MDrv_Enable_GPIO_INT); ++EXPORT_SYMBOL(MDrv_GPIO_To_Irq); ++EXPORT_SYMBOL(MDrv_GPIO_Set_POLARITY); ++ +diff --git a/drivers/sstar/gpio/mdrv_gpio_io.c b/drivers/sstar/gpio/mdrv_gpio_io.c +new file mode 100755 +index 000000000000..ec4afe52389f +--- /dev/null ++++ b/drivers/sstar/gpio/mdrv_gpio_io.c +@@ -0,0 +1,356 @@ ++/* ++* mdrv_gpio_io.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "mst_devid.h" ++ ++#include "mdrv_gpio_io.h" ++#include "mhal_gpio.h" ++#include "mdrv_gpio.h" ++#include "ms_platform.h" ++#include "gpio.h" ++ ++ ++//#include "mdrv_probe.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#define GPIO_DBG_ENABLE 0 ++ ++#if GPIO_DBG_ENABLE ++#define GPIO_DBG(_f) (_f) ++#else ++#define GPIO_DBG(_f) ++#endif ++ ++#if 0 ++#define LINE_DBG() printf("GPIO %d\n", __LINE__) ++#else ++#define LINE_DBG() ++#endif ++ ++#define GPIO_PRINT(fmt, args...) //printk("\n[GPIO][%05d] " fmt, __LINE__, ## args) ++ ++typedef struct ++{ ++ S32 s32MajorGPIO; ++ S32 s32MinorGPIO; ++ struct cdev cDevice; ++ struct file_operations GPIOFop; ++ struct fasync_struct *async_queue; /* asynchronous readers */ ++} GPIO_ModHandle_t; ++ ++#ifdef CONFIG_PM_SLEEP ++typedef enum ++{ ++ GPIO_INVAILD = 0, ++ GPIO_OUT, ++ GPIO_IN, ++}GPIO_Dir_e; ++ ++typedef struct ++{ ++ U8 isreq; ++ U8 dir; ++ U8 val; ++}GPIO_State_t; ++#endif ++ ++ ++#define MOD_GPIO_DEVICE_COUNT 1 ++#define MOD_GPIO_NAME "ModGPIO" ++ ++#define MDRV_NAME_GPIO "gpio" ++#define MDRV_MAJOR_GPIO 0x9b ++#define MDRV_MINOR_GPIO 0x00 ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++static struct device *dev; ++ ++#ifdef CONFIG_PM_SLEEP ++static GPIO_State_t gpio_state_table[GPIO_NR]; ++#endif ++ ++//static struct class *gpio_class; ++ ++int camdriver_gpio_request(struct gpio_chip *chip, unsigned offset) ++{ ++ #ifdef CONFIG_PM_SLEEP ++ gpio_state_table[offset].isreq = TRUE; ++ #endif ++ MDrv_GPIO_Pad_Set(offset); ++ GPIO_PRINT("[camdriver-gpio]camdriver_gpio_request offset=%d\n",offset); ++ return 0; ++} ++ ++static void camdriver_gpio_free(struct gpio_chip *chip, unsigned offset) ++{ ++ #ifdef CONFIG_PM_SLEEP ++ gpio_state_table[offset].isreq = FALSE; ++ #endif ++ GPIO_PRINT("[camdriver-gpio]camdriver_gpio_free\n"); ++} ++ ++void camdriver_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ #ifdef CONFIG_PM_SLEEP ++ gpio_state_table[offset].val = value; ++ #endif ++ if(value==0) ++ MDrv_GPIO_Pull_Low(offset); ++ else ++ MDrv_GPIO_Pull_High(offset); ++ GPIO_PRINT("[camdriver-gpio]camdriver_gpio_set\n"); ++} ++ ++int camdriver_gpio_get(struct gpio_chip *chip, unsigned offset) ++{ ++ GPIO_PRINT("[camdriver-gpio]camdriver_gpio_get\n"); ++ return MDrv_GPIO_Pad_Read(offset); ++} ++ ++int camdriver_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ++{ ++ #ifdef CONFIG_PM_SLEEP ++ gpio_state_table[offset].dir = GPIO_IN; ++ #endif ++ GPIO_PRINT("[camdriver-gpio]camdriver_gpio_direction_input\n"); ++ MDrv_GPIO_Pad_Odn(offset); ++ return 0; ++} ++ ++int camdriver_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ++ int value) ++{ ++ #ifdef CONFIG_PM_SLEEP ++ gpio_state_table[offset].val = value; ++ gpio_state_table[offset].dir = GPIO_OUT; ++ #endif ++ MDrv_GPIO_Pad_Oen(offset); ++ if(value==0) ++ MDrv_GPIO_Pull_Low(offset); ++ else ++ MDrv_GPIO_Pull_High(offset); ++ GPIO_PRINT("[camdriver-gpio]camdriver_gpio_direction_output\n"); ++ return 0; ++} ++ ++int camdriver_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++{ ++ int virq; ++ ++ virq = MDrv_GPIO_To_Irq(offset); ++ if (virq < 0) ++ return -ENXIO; ++ ++ GPIO_PRINT("%s virq:%d \n", __FUNCTION__, virq); ++ return virq; ++} ++ ++static struct gpio_chip camdriver_gpio_chip = { ++ .label = "gpio", ++ .request = camdriver_gpio_request, ++ .free = camdriver_gpio_free, ++ .direction_input = camdriver_gpio_direction_input, ++ .get = camdriver_gpio_get, ++ .direction_output = camdriver_gpio_direction_output, ++ .set = camdriver_gpio_set, ++ .to_irq = camdriver_gpio_to_irq, ++ .base = 0, ++}; ++ ++ ++static const struct of_device_id camdriver_gpio_of_match[] = { ++ { .compatible = "sstar,gpio" }, ++ { }, ++}; ++ ++static int camdriver_gpio_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *match; ++ int ret; ++/* ++ struct resource *res; ++ void __iomem *base; ++ int gpionum; ++ struct device_node *node = pdev->dev.of_node; ++*/ ++ dev = &pdev->dev; ++ GPIO_PRINT("\n++[camdriver-gpio]camdriver_gpio_probe start\n"); ++/* ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gPadBaseAddr=(U32)base; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gChipBaseAddr=(U32)base; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gPmGpioBaseAddr=(U32)base; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 3); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gPmSleepBaseAddr=(U32)base; ++ GPIO_PRINT("gPadBaseAddr=%x\n",gPadBaseAddr); ++ GPIO_PRINT("gChipBaseAddr=%x\n",gChipBaseAddr); ++ GPIO_PRINT("gPmGpioBaseAddr=%x\n",gPmGpioBaseAddr); ++*/ ++ match = of_match_device(camdriver_gpio_of_match, &pdev->dev); ++ if (!match) { ++ printk("Err:[gpio] No dev found\n"); ++ return -ENODEV; ++ } ++// of_property_read_u32(node, "gpio-num", &gpionum); ++ ++ camdriver_gpio_chip.ngpio = GPIO_NR; ++ camdriver_gpio_chip.of_node = pdev->dev.of_node; ++ ret = gpiochip_add(&camdriver_gpio_chip); ++ if (ret < 0) { ++ printk("[gpio] add err\n"); ++ return ret; ++ } ++ ++ GPIO_PRINT("--[camdriver-gpio]camdriver_gpio_probe end\n"); ++ ++ MDrv_GPIO_Init(); ++ printk(KERN_WARNING"GPIO: probe end"); ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int camdriver_gpio_suspend(struct device *dev) ++{ ++ return 0; ++} ++ ++static int camdriver_gpio_resume(struct device *dev) ++{ ++ int i; ++ for (i = 0; i < GPIO_NR; i++) ++ { ++ if(gpio_state_table[i].isreq == TRUE) ++ { ++ MDrv_GPIO_Pad_Set(i); ++ if(gpio_state_table[i].dir == GPIO_IN) ++ { ++ MDrv_GPIO_Pad_Odn(i); ++ } ++ else if(gpio_state_table[i].dir == GPIO_OUT) ++ { ++ MDrv_GPIO_Pad_Oen(i); ++ if(gpio_state_table[i].val == 0) ++ { ++ MDrv_GPIO_Pull_Low(i); ++ } ++ else ++ { ++ MDrv_GPIO_Pull_High(i); ++ } ++ } ++ } ++ } ++ return 0; ++} ++#else ++#define camdriver_gpio_suspend NULL ++#define camdriver_gpio_resume NULL ++#endif ++ ++static const struct dev_pm_ops camdriver_gpio_pm_ops = { ++ .suspend = camdriver_gpio_suspend, ++ .resume = camdriver_gpio_resume, ++}; ++ ++static struct platform_driver camdriver_gpio_driver = { ++ .driver = { ++ .name = "gpio", ++ .owner = THIS_MODULE, ++ .of_match_table = camdriver_gpio_of_match, ++ .pm = &camdriver_gpio_pm_ops, ++ }, ++ .probe = camdriver_gpio_probe, ++}; ++ ++ ++ ++void __mod_gpio_init(void) ++{ ++ //GPIO chiptop initialization ++ MDrv_GPIO_Init(); ++} ++ ++ ++static int __init camdriver_gpio_init(void) ++{ ++ return platform_driver_register(&camdriver_gpio_driver); ++} ++postcore_initcall(camdriver_gpio_init); ++ ++EXPORT_SYMBOL(camdriver_gpio_to_irq); ++EXPORT_SYMBOL(camdriver_gpio_direction_output); ++EXPORT_SYMBOL(camdriver_gpio_request); ++EXPORT_SYMBOL(camdriver_gpio_set); ++EXPORT_SYMBOL(camdriver_gpio_get); ++EXPORT_SYMBOL(camdriver_gpio_direction_input); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("GPIO driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/gpio/mdrv_sw_iic.c b/drivers/sstar/gpio/mdrv_sw_iic.c +new file mode 100755 +index 000000000000..4ff53f4d4f0c +--- /dev/null ++++ b/drivers/sstar/gpio/mdrv_sw_iic.c +@@ -0,0 +1,683 @@ ++/* ++* mdrv_sw_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++ ++#include "mdrv_sw_iic.h" ++#include "mdrv_gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++//#define OPEN_SWI2C_DEBUG ++ ++#ifdef OPEN_SWI2C_DEBUG ++#define swi2cDbg printk ++#else ++#define swi2cDbg(...) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++// for SW I2C ++#define _INPUT 1 ++#define _OUTPUT 0 ++#define _HIGH 1 ++#define _LOW 0 ++#define SWIIC_READ 0 ++#define SWIIC_WRITE 1 ++#define I2C_CHECK_PIN_DUMMY 3200/*6000*//*3200*/ ++#define I2C_ACKNOWLEDGE _LOW ++#define I2C_NON_ACKNOWLEDGE _HIGH ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++I2C_BusCfg_t g_I2CBusCfg[SW_IIC_NUM_OF_MAX]; ++int gpioi2c_delay_us = 20; //default ++int access_dummy_time = 1; //default ++ ++#define SWIIC_SCL_PIN(chNum, x) \ ++ ((x == _INPUT) ? MDrv_GPIO_Pad_Odn(g_I2CBusCfg[chNum].u8PadSCL) : MDrv_GPIO_Pad_Oen(g_I2CBusCfg[chNum].u8PadSCL)) ++ ++#define SWIIC_SDA_PIN(chNum, x) \ ++ ((x == _INPUT) ? MDrv_GPIO_Pad_Odn(g_I2CBusCfg[chNum].u8PadSDA) : MDrv_GPIO_Pad_Oen(g_I2CBusCfg[chNum].u8PadSDA)) ++ ++#define SWIIC_SCL_OUT(chNum, x) \ ++ ((x == _HIGH) ? MDrv_GPIO_Pull_High(g_I2CBusCfg[chNum].u8PadSCL) : MDrv_GPIO_Pull_Low(g_I2CBusCfg[chNum].u8PadSCL)) ++ ++#define SWIIC_SDA_OUT(chNum, x) \ ++ ((x == _HIGH) ? MDrv_GPIO_Pull_High(g_I2CBusCfg[chNum].u8PadSDA) : MDrv_GPIO_Pull_Low(g_I2CBusCfg[chNum].u8PadSDA)); ++ ++#define GET_SWIIC_SCL(chNum) MDrv_GPIO_Pad_Read(g_I2CBusCfg[chNum].u8PadSCL) ++ ++#define GET_SWIIC_SDA(chNum) MDrv_GPIO_Pad_Read(g_I2CBusCfg[chNum].u8PadSDA) ++ ++//#define SWII_DELAY(chNum) (_I2CBus[chNum].DefDelay) ++ ++#define _SDA_HIGH(chNum) SWIIC_SDA_PIN(chNum, _INPUT) ++#define _SDA_LOW(chNum) do { SWIIC_SDA_OUT(chNum, _LOW); SWIIC_SDA_PIN(chNum, _OUTPUT); } while(0) ++ ++#define _SCL_HIGH(chNum) SWIIC_SCL_PIN(chNum, _INPUT) ++#define _SCL_LOW(chNum) do { SWIIC_SCL_OUT(chNum, _LOW); SWIIC_SCL_PIN(chNum, _OUTPUT); } while(0) ++ ++ ++#define DISABLE 0 ++#define ENABLE 1 ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MDrv_SW_IIC_Delay(U8 u8ChIIC) ++{ ++/* ++ //U32 volatile u32Loop = DELAY_CYCLES(g_I2CBusCfg[u8ChIIC].u16SpeedKHz) / 2; ++ U32 volatile u32Loop=gpioi2c_delay_param; ++ ++ while(u32Loop--) ++ { ++ __asm__ __volatile__ ("mov r0, r0"); ++ } ++*/ ++ udelay(gpioi2c_delay_us); ++ ++} ++ ++void MDrv_SW_IIC_SCL(U8 u8ChIIC, U8 u8Data) ++{ ++ if ( u8Data == _HIGH ) ++ { ++ SWIIC_SCL_PIN(u8ChIIC, _INPUT); //set to input ++ } ++ else ++ { ++ SWIIC_SCL_OUT(u8ChIIC, _LOW); ++ SWIIC_SCL_PIN(u8ChIIC, _OUTPUT); ++ } ++} ++ ++void MDrv_SW_IIC_SDA(U8 u8ChIIC, U8 u8Data) ++{ ++ if ( u8Data == _HIGH ) ++ { ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); //set to input ++ } ++ else ++ { ++ //printk(KERN_INFO "SWIIC_SDA_OUT(u8ChIIC, _LOW)\r\n"); ++ SWIIC_SDA_OUT(u8ChIIC, _LOW); ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); //set to output ++ } ++} ++ ++void MDrv_SW_IIC_SCL_Chk(U8 u8ChIIC, U16 bSet) ++{ ++ U16 u16Dummy; // loop dummy ++ ++ if (bSet == _HIGH) // if set pin high ++ { ++ SWIIC_SCL_PIN(u8ChIIC, _INPUT); ++ u16Dummy = I2C_CHECK_PIN_DUMMY; // initialize dummy ++ ++ while ((GET_SWIIC_SCL(u8ChIIC) == _LOW) && (u16Dummy--)); ++ } ++ else ++ { ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); // set SCL pin ++ SWIIC_SCL_PIN(u8ChIIC, _OUTPUT); ++ } ++} ++ ++void MDrv_SW_IIC_SDA_Chk(U8 u8ChIIC, U16 bSet) ++{ ++ U16 u16Dummy; // loop dummy ++ ++ if (bSet == _HIGH) // if set pin high ++ { ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ u16Dummy = I2C_CHECK_PIN_DUMMY; // initialize dummy ++ while ((GET_SWIIC_SDA(u8ChIIC) == _LOW) && (u16Dummy--));// check SDA pull high ++ } ++ else ++ { ++ MDrv_SW_IIC_SDA(u8ChIIC, _LOW); // set SDA pin ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SW I2C: start signal. ++// ++// SCL ________ ++// \_________ ++// SDA _____ ++// \____________ ++// ++// Return value: None ++//------------------------------------------------------------------------------------------------- ++U16 MDrv_SW_IIC_Start(U8 u8ChIIC) ++{ ++ ++ U16 bStatus = TRUE; // success status ++ ++ //printk(KERN_INFO "u8ChIIC = %d \r\n", u8ChIIC); ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ // check pin error ++ SWIIC_SCL_PIN(u8ChIIC, _INPUT); ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ if ((GET_SWIIC_SCL(u8ChIIC) == _LOW) || (GET_SWIIC_SDA(u8ChIIC) == _LOW)) ++ { ++ SWIIC_SCL_PIN(u8ChIIC, _OUTPUT); ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ bStatus = FALSE; ++ } ++ else // success ++ { ++ MDrv_SW_IIC_SDA(u8ChIIC, _LOW); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ } ++ ++ return bStatus; //vain ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SW I2C: stop signal. ++// ++// ____________ ++// SCL _______/ ++// _________ ++// SDA __________/ ++//------------------------------------------------------------------------------------------------- ++void MDrv_SW_IIC_Stop(U8 u8ChIIC) ++{ ++ _SCL_LOW(u8ChIIC); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ _SDA_LOW(u8ChIIC); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++// _SCL_HIGH(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); // <20091212 takerest> fix SCL pin error ++ MDrv_SW_IIC_Delay(u8ChIIC); ++// _SDA_HIGH(u8ChIIC); ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _HIGH); // <20091212 takerest> fix SDA pin error ++ MDrv_SW_IIC_Delay(u8ChIIC); ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Send 1 bytes data ++///@param u8data \b IN: 1 byte data to send ++//------------------------------------------------------------------------------------------------- ++static U16 _IIC_SendByte(U8 u8ChIIC, U8 u8data, U8 u8Delay4Ack ) // Be used int IIC_SendByte ++{ ++ U8 u8Mask = 0x80; ++ U16 bAck; // acknowledge bit ++ ++ while ( u8Mask ) ++ { ++ if (u8data & u8Mask) ++ { ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _HIGH); ++ } ++ else ++ { ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _LOW); ++ } ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ #if 0//(EXTRA_DELAY_CYCLE) ++ if(SWII_DELAY(u8ChIIC) == 2) ++ { ++ MDrv_SW_IIC_DelayEx(u8ChIIC, 8); ++ } ++ #endif ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); // clock ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ u8Mask >>= 1; // next ++ } ++ ++ // recieve acknowledge ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ if( u8Delay4Ack > 0 ) ++ { ++ udelay( u8Delay4Ack ); ++ } ++ else ++ { ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ } ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ ++ bAck = GET_SWIIC_SDA(u8ChIIC); // recieve acknowlege ++// SWIIC_SDA(u8ChIIC, bAck); //for I2c waveform sharp ++// SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ MDrv_SW_IIC_SDA(u8ChIIC, (U8)bAck); //for I2c waveform sharp ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ return (bAck); ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Send 1 bytes data, this function will retry 5 times until success. ++///@param u8data \b IN: 1 byte data to send ++///@return BOOLEAN: ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++U16 MDrv_SW_IIC_SendByte(U8 u8ChIIC, U8 u8data, U8 u8Delay4Ack ) ++{ ++ U8 u8I; ++ ++ //printk(KERN_INFO "send byte u8data = 0x%x \r\n", u8data); ++ ++ for(u8I=0;u8IFailed\n"); ++ continue; ++ } ++ ++ if ( MDrv_SW_IIC_SendByte(u8ChIIC, u8SlaveAdr, u8Delay4Ack) == TRUE ) //I2C_ACKNOWLEDGE) // check acknowledge ++ { ++ return TRUE; ++ } ++ MDrv_SW_IIC_Stop(u8ChIIC); ++ } ++ ++ //printk(KERN_INFO "MDrv_SW_IIC_SendByte u8SlaveAdr = 0x%x\r\n", u8SlaveAdr); ++ return FALSE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Get 1 bytes data ++///@param u16Ack \b IN: acknowledge ++///@return U8: \b OUT: get data from the device ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_SW_IIC_GetByte (U8 u8ChIIC, U16 u16Ack) ++{ ++ U8 u8Receive = 0; ++ U8 u8Mask = 0x80; ++ ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ ++ while ( u8Mask ) ++ { ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ if (GET_SWIIC_SDA(u8ChIIC) == _HIGH) ++ { ++ u8Receive |= u8Mask; ++ } ++ u8Mask >>= 1; // next ++ ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ ++ #if 0//(EXTRA_DELAY_CYCLE) ++ if(SWII_DELAY(u8ChIIC) == 2) ++ { ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_DelayEx(u8ChIIC, 8); ++ } ++ #endif ++ } ++ if (u16Ack) ++ { ++ // acknowledge ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, I2C_ACKNOWLEDGE); ++ } ++ else ++ { ++ // non-acknowledge ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, I2C_NON_ACKNOWLEDGE); ++ } ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ return u8Receive; ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Write bytes, be able to write 1 byte or several bytes to several register offsets in same slave address. ++///@param u8SlaveID \b IN: Slave ID (Address) ++///@param u8AddrCnt \b IN: register NO to write, this parameter is the NO of register offsets in pu8addr buffer, ++///it should be 0 when *pu8Addr = NULL. ++///@param *pu8Addr \b IN: pointer to a buffer containing target register offsets to write ++///@param u32BufLen \b IN: Data length (in byte) to write ++///@param *pu8Buf \b IN: pointer to the data buffer for write ++///@return BOOLEAN: ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++S32 MDrv_SW_IIC_Write(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf) ++{ ++ U8 u8Dummy; // loop dummy ++ S32 s32RetCountIIC; ++ ++ //check if sw i2c channel is disabled ++ if(g_I2CBusCfg[u8ChIIC].u8Enable == DISABLE) ++ return -1; ++ ++ u8Dummy = access_dummy_time; ++ s32RetCountIIC = u32BufLen; ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_Lock(); ++ #endif ++ ++ //printk(KERN_INFO "u8AddrCnt = %d u32BufLen = %d\r\n" , u8AddrCnt, u32BufLen); ++ while (u8Dummy--) ++ { ++ if (MDrv_SW_IIC_AccessStart(u8ChIIC, u8SlaveID, SWIIC_WRITE) == FALSE) ++ { ++ s32RetCountIIC = -2; ++ swi2cDbg(":W slave addr fail(%d)\r\n",s32RetCountIIC); ++ //OALMSG(1, (L":W slave addr fail(%d)\r\n",s32RetCountIIC)); ++ ++ goto SW_IIC_Write_End; ++ } ++ ++ while( u8AddrCnt ) ++ { ++ u8AddrCnt--; ++ if ( MDrv_SW_IIC_SendByte(u8ChIIC, *pu8Addr, 0) == FALSE ) ++ { ++ s32RetCountIIC = -3; ++ swi2cDbg(":W reg addr fail(%d)\r\n",s32RetCountIIC); ++ goto SW_IIC_Write_End; ++ } ++ pu8Addr++; ++ } ++ while (u32BufLen) // loop of writting data ++ { ++ u32BufLen-- ; ++ if ( MDrv_SW_IIC_SendByte(u8ChIIC, *pu8Buf, 0) == FALSE ) ++ { ++ s32RetCountIIC = -4; ++ swi2cDbg(":W data fail(%d)\r\n",s32RetCountIIC); ++ goto SW_IIC_Write_End; ++ } ++ pu8Buf++; // next byte pointer ++ } ++ ++ break; ++ } ++ ++SW_IIC_Write_End: ++ MDrv_SW_IIC_Stop(u8ChIIC); ++ ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_UnLock(); ++ #endif ++ return s32RetCountIIC; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Read bytes, be able to read 1 byte or several bytes from several register offsets in same slave address. ++///@param u8SlaveID \b IN: Slave ID (Address) ++///@param u8AddrCnt \b IN: register NO to read, this parameter is the NO of register offsets in pu8addr buffer, ++///it should be 0 when *paddr = NULL. ++///@param *pu8Addr \b IN: pointer to a buffer containing target register offsets to read ++///@param u32BufLen \b IN: Data length (in byte) to read ++///@param *pu8Buf \b IN: pointer to retun data buffer. ++///@return BOOLEAN: ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++S32 MDrv_SW_IIC_Read(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf) ++{ ++ U8 u8Dummy; // loop dummy ++ S32 s32RetCountIIC; ++ ++ //check if sw i2c channel is disabled ++ if(g_I2CBusCfg[u8ChIIC].u8Enable == DISABLE) ++ return -1; ++ ++ u8Dummy = access_dummy_time; ++ s32RetCountIIC = u32BufLen; ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_Lock(); ++ #endif ++ ++ while (u8Dummy--) ++ { ++ if( u8AddrCnt > 0 ) ++ { ++ if (MDrv_SW_IIC_AccessStart(u8ChIIC, u8SlaveID, SWIIC_WRITE) == FALSE) ++ { ++ s32RetCountIIC = -2; ++ swi2cDbg(":W slave addr fail(%d)\r\n",s32RetCountIIC); ++ //printk(KERN_INFO "%s:W slave addr fail(%d)\n",__FUNCTION__,s32RetCountIIC); ++ goto SW_IIC_Read_End; ++ } ++ ++ while( u8AddrCnt ) ++ { ++ u8AddrCnt--; ++ //printk(KERN_INFO "%s:pu8Addr=0x%02x\n",__FUNCTION__,*pu8Addr); ++ if (MDrv_SW_IIC_SendByte(u8ChIIC, *pu8Addr, 0) == FALSE) ++ { ++ s32RetCountIIC = -3; ++ swi2cDbg(":W reg addr fail(%d)\r\n",s32RetCountIIC); ++ //printk(KERN_INFO "%s:W reg addr fail(%d)\n",__FUNCTION__,s32RetCountIIC); ++ goto SW_IIC_Read_End; ++ } ++ pu8Addr++; ++ } ++ } ++ ++ if (MDrv_SW_IIC_AccessStart(u8ChIIC, u8SlaveID, SWIIC_READ) == FALSE) ++ { ++ s32RetCountIIC = -4; ++ swi2cDbg(":W slave addr fail(%d)\r\n",s32RetCountIIC); ++ //printk(KERN_INFO "%s:W slave addr fail(%d)\n",__FUNCTION__,s32RetCountIIC); ++ goto SW_IIC_Read_End; ++ } ++ ++ while (u32BufLen--) // loop to burst read ++ { ++ *pu8Buf = MDrv_SW_IIC_GetByte(u8ChIIC, (U16)u32BufLen); // receive byte ++ //printk(KERN_INFO "%s:pu8Buf=0x%02x\n",__FUNCTION__,*pu8Buf); ++ pu8Buf++; // next byte pointer ++ } ++ ++ break; ++ } ++ ++SW_IIC_Read_End: ++ MDrv_SW_IIC_Stop(u8ChIIC); ++ ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_UnLock(); ++ #endif ++ return s32RetCountIIC; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC Set Speed by Index ++/// @param u8ChIIC \b IN: channel index ++/// @param u8Speed \b IN: u8Speed index ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MDrv_SW_IIC_SetSpeed(U8 u8ChIIC, U8 u8Speed) ++{ ++ ++ //switch(SWII_DELAY(u8ChIIC)) ++ switch(u8Speed) ++ { ++ case 1: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 400; //KHz ++ break; ++ case 2: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 300; //KHz ++ break; ++ case 3: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 200; //KHz ++ break; ++ case 4: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 100; //KHz ++ break; ++ default: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 100; //KHz ++ break; ++ } ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC Bus Enable or Disable ++/// @param u8ChIIC \b IN: channel index ++/// @param bEnable \b IN: enable ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MDrv_SW_IIC_Enable( U8 u8ChIIC, U8 bEnable ) ++{ ++ g_I2CBusCfg[u8ChIIC].u8Enable = bEnable; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC Bus Configuration ++/// @param pBusCfg \b IN: clock selection ++/// @return None ++//------------------------------------------------------------------------------------------------- ++U16 MDrv_SW_IIC_ConfigBus(I2C_BusCfg_t* pBusCfg) ++{ ++ U8 u8ChIIC; ++ ++ ++ swi2cDbg("[%s] Ch index = %d \r\n",__FUNCTION__,pBusCfg->u8ChIdx); ++ swi2cDbg("[%s] Ch PadSCL = %d \r\n",__FUNCTION__,pBusCfg->u8PadSCL); ++ swi2cDbg("[%s] Ch PadSDA = %d \r\n",__FUNCTION__,pBusCfg->u8PadSDA); ++ swi2cDbg("[%s] Ch SpeedKHz = %d \r\n",__FUNCTION__,pBusCfg->u16SpeedKHz); ++ swi2cDbg("[%s] Ch Enable = %d \r\n",__FUNCTION__,pBusCfg->u8Enable); ++ u8ChIIC = pBusCfg->u8ChIdx; ++ g_I2CBusCfg[u8ChIIC].u8ChIdx = pBusCfg->u8ChIdx; ++ g_I2CBusCfg[u8ChIIC].u8PadSCL = pBusCfg->u8PadSCL; ++ g_I2CBusCfg[u8ChIIC].u8PadSDA = pBusCfg->u8PadSDA; ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = pBusCfg->u16SpeedKHz; ++ g_I2CBusCfg[u8ChIIC].u8Enable = pBusCfg->u8Enable; ++ pBusCfg++; ++ ++ return TRUE; ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC master initialization ++/// @return None ++/// @note Hardware IIC. Called only once at system initialization ++//------------------------------------------------------------------------------------------------- ++void MDrv_IIC_Init(void) ++{ ++ U8 u8ChIIC; ++ for(u8ChIIC=0;u8ChIIC ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_IIC_H_ ++#define _DRV_IIC_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++#define SW_IIC_NUM_OF_MAX (5) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++struct I2C_BusCfg ++{ ++ U8 u8ChIdx; ///Channel index ++ U8 u8PadSCL; ///Pad(Gpio) number for SCL ++ U8 u8PadSDA; ///Pad(Gpio) number for SDA ++ U16 u16SpeedKHz; ///Speed in KHz ++ U8 u8Enable; ///Enable ++} ; ++//} __attribute__ ((packed)); ++ ++typedef struct I2C_BusCfg I2C_BusCfg_t; ++extern int gpioi2c_delay_us; ++extern int access_dummy_time; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++// for software IIC ++void MDrv_SW_IIC_SetSpeed(U8 u8ChIIC, U8 u8Speed); ++void MDrv_SW_IIC_Delay(U8 u8ChIIC); ++void MDrv_SW_IIC_SCL(U8 u8ChIIC, U8 u8Data); ++void MDrv_SW_IIC_SDA(U8 u8ChIIC, U8 u8Data); ++void MDrv_SW_IIC_SCL_Chk(U8 u8ChIIC, U16 bSet); ++void MDrv_SW_IIC_SDA_Chk(U8 u8ChIIC, U16 bSet); ++U16 MDrv_SW_IIC_Start(U8 u8ChIIC); ++void MDrv_SW_IIC_Stop(U8 u8ChIIC); ++U16 MDrv_SW_IIC_SendByte(U8 u8ChIIC, U8 u8data, U8 u8Delay4Ack); ++U16 MDrv_SW_IIC_AccessStart(U8 u8ChIIC, U8 u8SlaveAdr, U8 u8Trans); ++U8 MDrv_SW_IIC_GetByte (U8 u8ChIIC, U16 u16Ack); ++S32 MDrv_SW_IIC_Write(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf); ++S32 MDrv_SW_IIC_Read(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf); ++#if (defined(CONFIG_MSTAR_TITANIA)||defined(CONFIG_MSTAR_TITANIA2)) ++#else ++void MDrv_SW_IIC_Enable( U8 u8ChIIC, U8 bEnable ); ++#endif ++U16 MDrv_SW_IIC_ConfigBus(I2C_BusCfg_t* pBusCfg); ++void MDrv_IIC_Init(void); ++ ++#endif // _DRV_IIC_H_ +diff --git a/drivers/sstar/gpio/ms_gpioi2c.c b/drivers/sstar/gpio/ms_gpioi2c.c +new file mode 100755 +index 000000000000..52c35ede990e +--- /dev/null ++++ b/drivers/sstar/gpio/ms_gpioi2c.c +@@ -0,0 +1,249 @@ ++/* ++* ms_gpioi2c.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_sw_iic.h" ++#include "ms_msys.h" ++ ++#define GPIO_I2C_READ 0x01 ++#define GPIO_I2C_WRITE 0x03 ++ ++struct cdev ms_gpioi2c_cdev; ++int ms_gpioi2c_major; ++int ms_gpioi2c_minor_start=0; ++int ms_gpioi2c_dev_count=3; ++ ++static ssize_t access_retry_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ access_dummy_time = simple_strtoul(buf, NULL, 10); ++ printk("\naccess_dummy_time=%d\n", access_dummy_time); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t access_retry_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", access_dummy_time); ++ return (str - buf); ++} ++DEVICE_ATTR(access_retry, 0644, access_retry_show, access_retry_store); ++ ++static ssize_t gpioi2c_delay_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ gpioi2c_delay_us = simple_strtoul(buf, NULL, 10); ++ printk("\ngpioi2c_delay_us=%d\n", gpioi2c_delay_us); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t gpioi2c_delay_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", gpioi2c_delay_us); ++ return (str - buf); ++} ++DEVICE_ATTR(gpioi2c_delay, 0644, gpioi2c_delay_show, gpioi2c_delay_store); ++ ++ ++unsigned char gpio_i2c_read(unsigned char devaddress, unsigned char address) ++{ ++ int rxdata; ++ ++ MDrv_SW_IIC_Start(0); ++ MDrv_SW_IIC_SendByte(0, devaddress, 0); ++ MDrv_SW_IIC_SendByte(0, address, 0); ++ MDrv_SW_IIC_Start(0); ++ MDrv_SW_IIC_SendByte(0, (devaddress | 1), 0); ++ rxdata = MDrv_SW_IIC_GetByte(0, FALSE); ++ MDrv_SW_IIC_Stop(0); ++ return rxdata; ++} ++EXPORT_SYMBOL(gpio_i2c_read); ++ ++void gpio_i2c_write(unsigned char devaddress, unsigned char address, unsigned char data) ++{ ++ MDrv_SW_IIC_Start(0); ++ MDrv_SW_IIC_SendByte(0, devaddress, 0); ++ MDrv_SW_IIC_SendByte(0, address, 0); ++ MDrv_SW_IIC_SendByte(0, data, 0); ++ MDrv_SW_IIC_Stop(0); ++} ++EXPORT_SYMBOL(gpio_i2c_write); ++ ++ ++long gpioi2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ unsigned int val; ++ char device_addr, reg_addr; ++ short reg_val; ++ ++ switch(cmd) ++ { ++ case GPIO_I2C_READ: ++ //printk("GPIO_I2C_READ arg=0x%08X\n", *(unsigned int *)arg); ++ val = *(unsigned int *)arg; ++ device_addr = (val&0xff000000)>>24; ++ reg_addr = (val&0xff0000)>>16; ++ ++ reg_val = gpio_i2c_read(device_addr, reg_addr); ++ *(unsigned int *)arg = (val&0xffff0000)|reg_val; ++ ++ break; ++ ++ case GPIO_I2C_WRITE: ++ //printk("GPIO_I2C_WRITE arg=0x%08X\n", *(unsigned int *)arg); ++ val = *(unsigned int *)arg; ++ device_addr = (val&0xff000000)>>24; ++ reg_addr = (val&0xff0000)>>16; ++ ++ reg_val = val&0xffff; ++ gpio_i2c_write(device_addr, reg_addr, reg_val); ++ ++ break; ++ ++ default: ++ return -1; ++ } ++ return 0; ++} ++ ++ ++int gpioi2c_open(struct inode * inode, struct file * file) ++{ ++ return 0; ++} ++int gpioi2c_close(struct inode * inode, struct file * file) ++{ ++ return 0; ++} ++ ++static struct file_operations gpioi2c_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gpioi2c_ioctl, ++ .open = gpioi2c_open, ++ .release = gpioi2c_close, ++}; ++ ++static int ms_gpioi2c_probe(struct platform_device *pdev) ++{ ++ int err, sda, scl; ++ dev_t dev; ++ I2C_BusCfg_t gpioi2c_cfg; ++ struct device* gpioi2c_dev; ++ ++ MDrv_IIC_Init(); ++ ++ if(0 != of_property_read_u32(pdev->dev.of_node, "sda-gpio", &sda)) ++ return -EINVAL; ++ ++ if(0 != of_property_read_u32(pdev->dev.of_node, "scl-gpio", &scl)) ++ return -EINVAL; ++ ++ gpioi2c_cfg.u8ChIdx = 0; ++ gpioi2c_cfg.u8PadSDA = sda; ++ gpioi2c_cfg.u8PadSCL = scl; ++ gpioi2c_cfg.u16SpeedKHz = 100; //gpioi2c no used ++ gpioi2c_cfg.u8Enable = ENABLE; ++ ++ MDrv_SW_IIC_ConfigBus(&gpioi2c_cfg); ++ ++ if (0 != (err = alloc_chrdev_region(&dev, ms_gpioi2c_minor_start, ms_gpioi2c_dev_count, "mstar_gpioi2c"))) ++ return err; ++ ++ ms_gpioi2c_major = MAJOR(dev); ++ ++ cdev_init(&ms_gpioi2c_cdev, &gpioi2c_fops); ++ ms_gpioi2c_cdev.owner=THIS_MODULE; ++ ++ if(0 != (err = cdev_add(&ms_gpioi2c_cdev, dev, ms_gpioi2c_dev_count))) ++ return err; ++ ++ gpioi2c_dev = device_create(msys_get_sysfs_class(), NULL, dev, NULL, "gpioi2c"); ++ ++ device_create_file(gpioi2c_dev, &dev_attr_gpioi2c_delay); ++ device_create_file(gpioi2c_dev, &dev_attr_access_retry); ++ ++ printk("[gpioi2c] sda-gpio=%d, scl-gpio=%d\n", sda, scl); ++ ++ return err; ++} ++ ++static int ms_gpioi2c_remove(struct platform_device *pdev) ++{ ++ printk("[gpioi2c] removed\n"); ++ ++ cdev_del(&ms_gpioi2c_cdev); ++ unregister_chrdev_region(MKDEV(ms_gpioi2c_major, ms_gpioi2c_minor_start), ms_gpioi2c_dev_count); ++ device_destroy(msys_get_sysfs_class(), MKDEV(ms_gpioi2c_major, ms_gpioi2c_dev_count)); ++ ++ return 0; ++} ++ ++static const struct of_device_id ms_gpioi2c_of_match_table[] = { ++ { .compatible = "sstar,infinity-gpioi2c" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_gpioi2c_of_match_table); ++ ++static struct platform_driver ms_gpioi2c_driver = { ++ .remove = ms_gpioi2c_remove, ++ .probe = ms_gpioi2c_probe, ++ .driver = { ++ .name = "ms_gpioi2c_driver", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_gpioi2c_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_gpioi2c_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("ms_sw_iic driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/gpio/test/Makefile b/drivers/sstar/gpio/test/Makefile +new file mode 100755 +index 000000000000..fc3762623675 +--- /dev/null ++++ b/drivers/sstar/gpio/test/Makefile +@@ -0,0 +1,15 @@ ++obj-m := gpio_irq.o ++gpio_irq-objs := gpio_irq_test.o ++ ++export ARCH=arm ++export CROSS_COMPILE=arm-linux-gnueabihf- ++ ++KERNEL = $(PWD)/../../../../ ++CC = $(CROSS_COMPILE)gcc ++EXTRA_CFLAGS := -I$(KERNEL)/drivers/sstar/include/ -I$(KERNEL)/include/ ++ ++all: ++ make modules -C $(KERNEL) M=`pwd` ++ ++clean: ++ make modules clean -C $(KERNEL) M=`pwd` +diff --git a/drivers/sstar/gpio/test/gpio_irq_test.c b/drivers/sstar/gpio/test/gpio_irq_test.c +new file mode 100755 +index 000000000000..5e0feace77e1 +--- /dev/null ++++ b/drivers/sstar/gpio/test/gpio_irq_test.c +@@ -0,0 +1,93 @@ ++/* ++* gpio_irq_test.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file gpio_irq_test.c ++/// @brief GPIO IRQ Test Code for Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include ++#include ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("SStar GPIO IRQ Test"); ++MODULE_LICENSE("GPL"); ++ ++int pin = 0; ++module_param(pin, int, 0); ++int level = 0; ++module_param(level, int, 0); ++ ++s32 gpio_set_success = 0; ++u32 gpio_irq_num = 0; ++ ++irqreturn_t gpio_test_isr(int irq, void *dev_instance) ++{ ++ CamOsTimespec_t ptRes; ++ CamOsGetMonotonicTime(&ptRes); ++ printk("%s [%d.%09d]\n", __func__, ptRes.nSec, ptRes.nNanoSec); ++ ++ return IRQ_NONE; ++} ++ ++static int __init GpioIrqTestInit(void) ++{ ++ gpio_set_success = 0; ++ ++ if(gpio_request(pin, "gpio_irq_test") < 0) ++ { ++ printk("request gpio[%d] failed...\n", pin); ++ return 0; ++ } ++ ++ if (gpio_direction_input(pin) < 0) { ++ printk("gpio_direction_input[%d] failed...\n", pin); ++ return 0; ++ } ++ ++ gpio_irq_num = gpio_to_irq(pin); ++ if (request_irq(gpio_irq_num, gpio_test_isr, (level==0)? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING, "PAD", NULL)) ++ { ++ printk(KERN_ERR"can't allocate irq\n"); ++ return 0; ++ } ++ ++ gpio_set_success = 1; ++ ++ return 0; ++} ++ ++static void __exit GpioIrqTestExit(void) ++{ ++ if (gpio_set_success) ++ free_irq(gpio_irq_num, NULL); ++ gpio_free(pin); ++} ++ ++module_init(GpioIrqTestInit); ++module_exit(GpioIrqTestExit); +diff --git a/drivers/sstar/gpio_key_sample/gpio_key_driver/Makefile b/drivers/sstar/gpio_key_sample/gpio_key_driver/Makefile +new file mode 100755 +index 000000000000..4b8eba28a4d2 +--- /dev/null ++++ b/drivers/sstar/gpio_key_sample/gpio_key_driver/Makefile +@@ -0,0 +1,29 @@ ++# ++# Makefile for the Linux network IOT device drivers. ++# ++ ++KERNEL_DIR ?=../kernel ++PWD := $(shell pwd) ++MODULE_NAME = gpio_key_driver ++ ++#ifdef CONFIG_MSTAR_CHIP_NAME ++#EXTRA_CFLAGS += -I$(KERNEL_DIR)/drivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++#endif ++ ++#ifdef CONFIG_SSTAR_CHIP_NAME ++#EXTRA_CFLAGS += -I$(KERNEL_DIR)/drivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++#endif ++ ++ ++ ++obj-m += $(MODULE_NAME).o ++obj-$(MODULE_NAME) += gpio_key_driver.c ++ ++modules: ++ make -C $(KERNEL_DIR) M=$(PWD) modules ++ ++clean: ++ make -C $(KERNEL_DIR) M=$(PWD) clean ++ ++.PHONY: modules ++ +diff --git a/drivers/sstar/gpio_key_sample/gpio_key_driver/gpio_key_driver.c b/drivers/sstar/gpio_key_sample/gpio_key_driver/gpio_key_driver.c +new file mode 100755 +index 000000000000..79a3d81a12d3 +--- /dev/null ++++ b/drivers/sstar/gpio_key_sample/gpio_key_driver/gpio_key_driver.c +@@ -0,0 +1,48 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static struct gpio_keys_button sstar_buttons[] = { ++ { ++ .code = 0x7, ++ .gpio = 66, ++ .active_low = 1, ++ .desc = "key wakeup", ++ .type = EV_KEY, ++ .wakeup = 1, ++ //.debounce_interval = 10, ++ }, ++}; ++ ++static struct gpio_keys_platform_data sstar_gpio_keys_data = { ++ .buttons = sstar_buttons, ++ .nbuttons = ARRAY_SIZE(sstar_buttons), ++}; ++ ++ ++static struct platform_device sstar_gpio_keys = { ++ .name = "gpio-keys", ++ .id = -1, ++ .dev.platform_data = &sstar_gpio_keys_data, ++}; ++ ++ ++static struct platform_device *devices[] __initdata = { ++ &sstar_gpio_keys, ++}; ++ ++static int __init sstar_init(void) ++{ ++ ++ return platform_add_devices(devices, ARRAY_SIZE(devices)); ++} ++ ++module_init(sstar_init); ++ ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/sstar/gpio_key_sample/kernel_gpio_key_patch/drivers/input/keyboard/gpio_keys.c b/drivers/sstar/gpio_key_sample/kernel_gpio_key_patch/drivers/input/keyboard/gpio_keys.c +new file mode 100755 +index 000000000000..b4292962d65c +--- /dev/null ++++ b/drivers/sstar/gpio_key_sample/kernel_gpio_key_patch/drivers/input/keyboard/gpio_keys.c +@@ -0,0 +1,955 @@ ++/* ++ * Driver for keys on GPIO lines capable of generating interrupts. ++ * ++ * Copyright 2005 Phil Blundell ++ * Copyright 2010, 2011 David Jander ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define SUPPORT_SW_BOTH_TRIGGER ++ ++#ifdef SUPPORT_SW_BOTH_TRIGGER ++int key_status; ++#endif ++ ++struct gpio_button_data { ++ const struct gpio_keys_button *button; ++ struct input_dev *input; ++ struct gpio_desc *gpiod; ++ ++ struct timer_list release_timer; ++ unsigned int release_delay; /* in msecs, for IRQ-only buttons */ ++ ++ struct delayed_work work; ++ unsigned int software_debounce; /* in msecs, for GPIO-driven buttons */ ++ ++ unsigned int irq; ++ spinlock_t lock; ++ bool disabled; ++ bool key_pressed; ++}; ++ ++struct gpio_keys_drvdata { ++ const struct gpio_keys_platform_data *pdata; ++ struct input_dev *input; ++ struct mutex disable_lock; ++ struct gpio_button_data data[0]; ++}; ++ ++/* ++ * SYSFS interface for enabling/disabling keys and switches: ++ * ++ * There are 4 attributes under /sys/devices/platform/gpio-keys/ ++ * keys [ro] - bitmap of keys (EV_KEY) which can be ++ * disabled ++ * switches [ro] - bitmap of switches (EV_SW) which can be ++ * disabled ++ * disabled_keys [rw] - bitmap of keys currently disabled ++ * disabled_switches [rw] - bitmap of switches currently disabled ++ * ++ * Userland can change these values and hence disable event generation ++ * for each key (or switch). Disabling a key means its interrupt line ++ * is disabled. ++ * ++ * For example, if we have following switches set up as gpio-keys: ++ * SW_DOCK = 5 ++ * SW_CAMERA_LENS_COVER = 9 ++ * SW_KEYPAD_SLIDE = 10 ++ * SW_FRONT_PROXIMITY = 11 ++ * This is read from switches: ++ * 11-9,5 ++ * Next we want to disable proximity (11) and dock (5), we write: ++ * 11,5 ++ * to file disabled_switches. Now proximity and dock IRQs are disabled. ++ * This can be verified by reading the file disabled_switches: ++ * 11,5 ++ * If we now want to enable proximity (11) switch we write: ++ * 5 ++ * to disabled_switches. ++ * ++ * We can disable only those keys which don't allow sharing the irq. ++ */ ++ ++/** ++ * get_n_events_by_type() - returns maximum number of events per @type ++ * @type: type of button (%EV_KEY, %EV_SW) ++ * ++ * Return value of this function can be used to allocate bitmap ++ * large enough to hold all bits for given type. ++ */ ++static int get_n_events_by_type(int type) ++{ ++ BUG_ON(type != EV_SW && type != EV_KEY); ++ ++ return (type == EV_KEY) ? KEY_CNT : SW_CNT; ++} ++ ++/** ++ * get_bm_events_by_type() - returns bitmap of supported events per @type ++ * @input: input device from which bitmap is retrieved ++ * @type: type of button (%EV_KEY, %EV_SW) ++ * ++ * Return value of this function can be used to allocate bitmap ++ * large enough to hold all bits for given type. ++ */ ++static const unsigned long *get_bm_events_by_type(struct input_dev *dev, ++ int type) ++{ ++ BUG_ON(type != EV_SW && type != EV_KEY); ++ ++ return (type == EV_KEY) ? dev->keybit : dev->swbit; ++} ++ ++/** ++ * gpio_keys_disable_button() - disables given GPIO button ++ * @bdata: button data for button to be disabled ++ * ++ * Disables button pointed by @bdata. This is done by masking ++ * IRQ line. After this function is called, button won't generate ++ * input events anymore. Note that one can only disable buttons ++ * that don't share IRQs. ++ * ++ * Make sure that @bdata->disable_lock is locked when entering ++ * this function to avoid races when concurrent threads are ++ * disabling buttons at the same time. ++ */ ++static void gpio_keys_disable_button(struct gpio_button_data *bdata) ++{ ++ if (!bdata->disabled) { ++ /* ++ * Disable IRQ and associated timer/work structure. ++ */ ++ disable_irq(bdata->irq); ++ ++ if (bdata->gpiod) ++ cancel_delayed_work_sync(&bdata->work); ++ else ++ del_timer_sync(&bdata->release_timer); ++ ++ bdata->disabled = true; ++ } ++} ++ ++/** ++ * gpio_keys_enable_button() - enables given GPIO button ++ * @bdata: button data for button to be disabled ++ * ++ * Enables given button pointed by @bdata. ++ * ++ * Make sure that @bdata->disable_lock is locked when entering ++ * this function to avoid races with concurrent threads trying ++ * to enable the same button at the same time. ++ */ ++static void gpio_keys_enable_button(struct gpio_button_data *bdata) ++{ ++ if (bdata->disabled) { ++ enable_irq(bdata->irq); ++ bdata->disabled = false; ++ } ++} ++ ++/** ++ * gpio_keys_attr_show_helper() - fill in stringified bitmap of buttons ++ * @ddata: pointer to drvdata ++ * @buf: buffer where stringified bitmap is written ++ * @type: button type (%EV_KEY, %EV_SW) ++ * @only_disabled: does caller want only those buttons that are ++ * currently disabled or all buttons that can be ++ * disabled ++ * ++ * This function writes buttons that can be disabled to @buf. If ++ * @only_disabled is true, then @buf contains only those buttons ++ * that are currently disabled. Returns 0 on success or negative ++ * errno on failure. ++ */ ++static ssize_t gpio_keys_attr_show_helper(struct gpio_keys_drvdata *ddata, ++ char *buf, unsigned int type, ++ bool only_disabled) ++{ ++ int n_events = get_n_events_by_type(type); ++ unsigned long *bits; ++ ssize_t ret; ++ int i; ++ ++ bits = kcalloc(BITS_TO_LONGS(n_events), sizeof(*bits), GFP_KERNEL); ++ if (!bits) ++ return -ENOMEM; ++ ++ for (i = 0; i < ddata->pdata->nbuttons; i++) { ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ ++ if (bdata->button->type != type) ++ continue; ++ ++ if (only_disabled && !bdata->disabled) ++ continue; ++ ++ __set_bit(bdata->button->code, bits); ++ } ++ ++ ret = scnprintf(buf, PAGE_SIZE - 1, "%*pbl", n_events, bits); ++ buf[ret++] = '\n'; ++ buf[ret] = '\0'; ++ ++ kfree(bits); ++ ++ return ret; ++} ++ ++/** ++ * gpio_keys_attr_store_helper() - enable/disable buttons based on given bitmap ++ * @ddata: pointer to drvdata ++ * @buf: buffer from userspace that contains stringified bitmap ++ * @type: button type (%EV_KEY, %EV_SW) ++ * ++ * This function parses stringified bitmap from @buf and disables/enables ++ * GPIO buttons accordingly. Returns 0 on success and negative error ++ * on failure. ++ */ ++static ssize_t gpio_keys_attr_store_helper(struct gpio_keys_drvdata *ddata, ++ const char *buf, unsigned int type) ++{ ++ int n_events = get_n_events_by_type(type); ++ const unsigned long *bitmap = get_bm_events_by_type(ddata->input, type); ++ unsigned long *bits; ++ ssize_t error; ++ int i; ++ ++ bits = kcalloc(BITS_TO_LONGS(n_events), sizeof(*bits), GFP_KERNEL); ++ if (!bits) ++ return -ENOMEM; ++ ++ error = bitmap_parselist(buf, bits, n_events); ++ if (error) ++ goto out; ++ ++ /* First validate */ ++ if (!bitmap_subset(bits, bitmap, n_events)) { ++ error = -EINVAL; ++ goto out; ++ } ++ ++ for (i = 0; i < ddata->pdata->nbuttons; i++) { ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ ++ if (bdata->button->type != type) ++ continue; ++ ++ if (test_bit(bdata->button->code, bits) && ++ !bdata->button->can_disable) { ++ error = -EINVAL; ++ goto out; ++ } ++ } ++ ++ mutex_lock(&ddata->disable_lock); ++ ++ for (i = 0; i < ddata->pdata->nbuttons; i++) { ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ ++ if (bdata->button->type != type) ++ continue; ++ ++ if (test_bit(bdata->button->code, bits)) ++ gpio_keys_disable_button(bdata); ++ else ++ gpio_keys_enable_button(bdata); ++ } ++ ++ mutex_unlock(&ddata->disable_lock); ++ ++out: ++ kfree(bits); ++ return error; ++} ++ ++#define ATTR_SHOW_FN(name, type, only_disabled) \ ++static ssize_t gpio_keys_show_##name(struct device *dev, \ ++ struct device_attribute *attr, \ ++ char *buf) \ ++{ \ ++ struct platform_device *pdev = to_platform_device(dev); \ ++ struct gpio_keys_drvdata *ddata = platform_get_drvdata(pdev); \ ++ \ ++ return gpio_keys_attr_show_helper(ddata, buf, \ ++ type, only_disabled); \ ++} ++ ++ATTR_SHOW_FN(keys, EV_KEY, false); ++ATTR_SHOW_FN(switches, EV_SW, false); ++ATTR_SHOW_FN(disabled_keys, EV_KEY, true); ++ATTR_SHOW_FN(disabled_switches, EV_SW, true); ++ ++/* ++ * ATTRIBUTES: ++ * ++ * /sys/devices/platform/gpio-keys/keys [ro] ++ * /sys/devices/platform/gpio-keys/switches [ro] ++ */ ++static DEVICE_ATTR(keys, S_IRUGO, gpio_keys_show_keys, NULL); ++static DEVICE_ATTR(switches, S_IRUGO, gpio_keys_show_switches, NULL); ++ ++#define ATTR_STORE_FN(name, type) \ ++static ssize_t gpio_keys_store_##name(struct device *dev, \ ++ struct device_attribute *attr, \ ++ const char *buf, \ ++ size_t count) \ ++{ \ ++ struct platform_device *pdev = to_platform_device(dev); \ ++ struct gpio_keys_drvdata *ddata = platform_get_drvdata(pdev); \ ++ ssize_t error; \ ++ \ ++ error = gpio_keys_attr_store_helper(ddata, buf, type); \ ++ if (error) \ ++ return error; \ ++ \ ++ return count; \ ++} ++ ++ATTR_STORE_FN(disabled_keys, EV_KEY); ++ATTR_STORE_FN(disabled_switches, EV_SW); ++ ++/* ++ * ATTRIBUTES: ++ * ++ * /sys/devices/platform/gpio-keys/disabled_keys [rw] ++ * /sys/devices/platform/gpio-keys/disables_switches [rw] ++ */ ++static DEVICE_ATTR(disabled_keys, S_IWUSR | S_IRUGO, ++ gpio_keys_show_disabled_keys, ++ gpio_keys_store_disabled_keys); ++static DEVICE_ATTR(disabled_switches, S_IWUSR | S_IRUGO, ++ gpio_keys_show_disabled_switches, ++ gpio_keys_store_disabled_switches); ++ ++static struct attribute *gpio_keys_attrs[] = { ++ &dev_attr_keys.attr, ++ &dev_attr_switches.attr, ++ &dev_attr_disabled_keys.attr, ++ &dev_attr_disabled_switches.attr, ++ NULL, ++}; ++ ++static struct attribute_group gpio_keys_attr_group = { ++ .attrs = gpio_keys_attrs, ++}; ++ ++static void gpio_keys_gpio_report_event(struct gpio_button_data *bdata) ++{ ++ const struct gpio_keys_button *button = bdata->button; ++ struct input_dev *input = bdata->input; ++ unsigned int type = button->type ?: EV_KEY; ++ int state; ++ ++ state = gpiod_get_value_cansleep(bdata->gpiod); ++ if (state < 0) { ++ dev_err(input->dev.parent, ++ "failed to get gpio state: %d\n", state); ++ return; ++ } ++#ifdef SUPPORT_SW_BOTH_TRIGGER ++ if(key_status==state) ++ { ++ pr_info("false trigger"); ++ return; ++ } ++ key_status = state; ++ ++ if(key_status) ++ { ++ //irqflags = IRQF_TRIGGER_RISING; ++ irq_set_irq_type(bdata->irq,IRQF_TRIGGER_RISING); ++ ++ ++ } ++ else ++ { ++ //irqflags = IRQF_TRIGGER_FALLING; ++ irq_set_irq_type(bdata->irq,IRQF_TRIGGER_FALLING); ++ ++ } ++ ++ pr_info("gpio_keys_gpio_report_event: code = %d state=%d\r\n", button->code, state); ++#endif ++ if (type == EV_ABS) { ++ if (state) ++ input_event(input, type, button->code, button->value); ++ } else { ++ input_event(input, type, button->code, state); ++ } ++ input_sync(input); ++} ++ ++static void gpio_keys_gpio_work_func(struct work_struct *work) ++{ ++ struct gpio_button_data *bdata = ++ container_of(work, struct gpio_button_data, work.work); ++ ++ gpio_keys_gpio_report_event(bdata); ++ ++ if (bdata->button->wakeup) ++ pm_relax(bdata->input->dev.parent); ++} ++ ++static irqreturn_t gpio_keys_gpio_isr(int irq, void *dev_id) ++{ ++ struct gpio_button_data *bdata = dev_id; ++ ++ BUG_ON(irq != bdata->irq); ++ ++ if (bdata->button->wakeup) ++ pm_stay_awake(bdata->input->dev.parent); ++ ++ mod_delayed_work(system_wq, ++ &bdata->work, ++ msecs_to_jiffies(bdata->software_debounce)); ++ ++ return IRQ_HANDLED; ++} ++ ++static void gpio_keys_irq_timer(unsigned long _data) ++{ ++ struct gpio_button_data *bdata = (struct gpio_button_data *)_data; ++ struct input_dev *input = bdata->input; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&bdata->lock, flags); ++ if (bdata->key_pressed) { ++ input_event(input, EV_KEY, bdata->button->code, 0); ++ input_sync(input); ++ bdata->key_pressed = false; ++ } ++ spin_unlock_irqrestore(&bdata->lock, flags); ++} ++ ++static irqreturn_t gpio_keys_irq_isr(int irq, void *dev_id) ++{ ++ struct gpio_button_data *bdata = dev_id; ++ const struct gpio_keys_button *button = bdata->button; ++ struct input_dev *input = bdata->input; ++ unsigned long flags; ++ ++ BUG_ON(irq != bdata->irq); ++ ++ spin_lock_irqsave(&bdata->lock, flags); ++ ++ if (!bdata->key_pressed) { ++ if (bdata->button->wakeup) ++ pm_wakeup_event(bdata->input->dev.parent, 0); ++ ++ input_event(input, EV_KEY, button->code, 1); ++ input_sync(input); ++ ++ if (!bdata->release_delay) { ++ input_event(input, EV_KEY, button->code, 0); ++ input_sync(input); ++ goto out; ++ } ++ ++ bdata->key_pressed = true; ++ } ++ ++ if (bdata->release_delay) ++ mod_timer(&bdata->release_timer, ++ jiffies + msecs_to_jiffies(bdata->release_delay)); ++out: ++ spin_unlock_irqrestore(&bdata->lock, flags); ++ return IRQ_HANDLED; ++} ++ ++static void gpio_keys_quiesce_key(void *data) ++{ ++ struct gpio_button_data *bdata = data; ++ ++ if (bdata->gpiod) ++ cancel_delayed_work_sync(&bdata->work); ++ else ++ del_timer_sync(&bdata->release_timer); ++} ++ ++static int gpio_keys_setup_key(struct platform_device *pdev, ++ struct input_dev *input, ++ struct gpio_button_data *bdata, ++ const struct gpio_keys_button *button) ++{ ++ const char *desc = button->desc ? button->desc : "gpio_keys"; ++ struct device *dev = &pdev->dev; ++ irq_handler_t isr; ++ unsigned long irqflags; ++ int irq; ++ int error; ++ ++ bdata->input = input; ++ bdata->button = button; ++ spin_lock_init(&bdata->lock); ++ ++ /* ++ * Legacy GPIO number, so request the GPIO here and ++ * convert it to descriptor. ++ */ ++ if (gpio_is_valid(button->gpio)) { ++ unsigned flags = GPIOF_IN; ++ ++ if (button->active_low) ++ flags |= GPIOF_ACTIVE_LOW; ++ ++ error = devm_gpio_request_one(&pdev->dev, button->gpio, flags, ++ desc); ++ if (error < 0) { ++ dev_err(dev, "Failed to request GPIO %d, error %d\n", ++ button->gpio, error); ++ return error; ++ } ++ ++ bdata->gpiod = gpio_to_desc(button->gpio); ++ if (!bdata->gpiod) ++ return -EINVAL; ++ ++ if (button->debounce_interval) { ++ error = gpiod_set_debounce(bdata->gpiod, ++ button->debounce_interval * 1000); ++ /* use timer if gpiolib doesn't provide debounce */ ++ if (error < 0) ++ bdata->software_debounce = ++ button->debounce_interval; ++ } ++ ++ if (button->irq) { ++ bdata->irq = button->irq; ++ } else { ++ irq = gpiod_to_irq(bdata->gpiod); ++ if (irq < 0) { ++ error = irq; ++ dev_err(dev, ++ "Unable to get irq number for GPIO %d, error %d\n", ++ button->gpio, error); ++ return error; ++ } ++ bdata->irq = irq; ++ } ++ ++ INIT_DELAYED_WORK(&bdata->work, gpio_keys_gpio_work_func); ++ ++ isr = gpio_keys_gpio_isr; ++#ifdef SUPPORT_SW_BOTH_TRIGGER ++ key_status = gpiod_get_value_cansleep(bdata->gpiod); ++ if (key_status < 0) { ++ dev_err(input->dev.parent, ++ "failed to get gpio state: %d\n", key_status); ++ return key_status; ++ } ++ ++ if(key_status) ++ irqflags = IRQF_TRIGGER_RISING; ++ else ++ irqflags = IRQF_TRIGGER_FALLING; ++ ++#else ++ irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; ++#endif ++ } else { ++ if (!button->irq) { ++ dev_err(dev, "No IRQ specified\n"); ++ return -EINVAL; ++ } ++ bdata->irq = button->irq; ++ ++ if (button->type && button->type != EV_KEY) { ++ dev_err(dev, "Only EV_KEY allowed for IRQ buttons.\n"); ++ return -EINVAL; ++ } ++ ++ bdata->release_delay = button->debounce_interval; ++ setup_timer(&bdata->release_timer, ++ gpio_keys_irq_timer, (unsigned long)bdata); ++ ++ isr = gpio_keys_irq_isr; ++ irqflags = 0; ++ } ++ ++ input_set_capability(input, button->type ?: EV_KEY, button->code); ++ ++ /* ++ * Install custom action to cancel release timer and ++ * workqueue item. ++ */ ++ error = devm_add_action(&pdev->dev, gpio_keys_quiesce_key, bdata); ++ if (error) { ++ dev_err(&pdev->dev, ++ "failed to register quiesce action, error: %d\n", ++ error); ++ return error; ++ } ++ ++ /* ++ * If platform has specified that the button can be disabled, ++ * we don't want it to share the interrupt line. ++ */ ++ if (!button->can_disable) ++ irqflags |= IRQF_SHARED; ++ ++ error = devm_request_any_context_irq(&pdev->dev, bdata->irq, ++ isr, irqflags, desc, bdata); ++ if (error < 0) { ++ dev_err(dev, "Unable to claim irq %d; error %d\n", ++ bdata->irq, error); ++ return error; ++ } ++ ++ return 0; ++} ++ ++static void gpio_keys_report_state(struct gpio_keys_drvdata *ddata) ++{ ++ struct input_dev *input = ddata->input; ++ int i; ++ ++ for (i = 0; i < ddata->pdata->nbuttons; i++) { ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ if (bdata->gpiod) ++ gpio_keys_gpio_report_event(bdata); ++ } ++ input_sync(input); ++} ++ ++static int gpio_keys_open(struct input_dev *input) ++{ ++ struct gpio_keys_drvdata *ddata = input_get_drvdata(input); ++ const struct gpio_keys_platform_data *pdata = ddata->pdata; ++ int error; ++ ++ if (pdata->enable) { ++ error = pdata->enable(input->dev.parent); ++ if (error) ++ return error; ++ } ++ ++ /* Report current state of buttons that are connected to GPIOs */ ++ gpio_keys_report_state(ddata); ++ ++ return 0; ++} ++ ++static void gpio_keys_close(struct input_dev *input) ++{ ++ struct gpio_keys_drvdata *ddata = input_get_drvdata(input); ++ const struct gpio_keys_platform_data *pdata = ddata->pdata; ++ ++ if (pdata->disable) ++ pdata->disable(input->dev.parent); ++} ++ ++/* ++ * Handlers for alternative sources of platform_data ++ */ ++ ++#ifdef CONFIG_OF ++/* ++ * Translate OpenFirmware node properties into platform_data ++ */ ++static struct gpio_keys_platform_data * ++gpio_keys_get_devtree_pdata(struct device *dev) ++{ ++ struct device_node *node, *pp; ++ struct gpio_keys_platform_data *pdata; ++ struct gpio_keys_button *button; ++ int error; ++ int nbuttons; ++ int i; ++ ++ node = dev->of_node; ++ if (!node) ++ return ERR_PTR(-ENODEV); ++ ++ nbuttons = of_get_available_child_count(node); ++ if (nbuttons == 0) ++ return ERR_PTR(-ENODEV); ++ ++ pdata = devm_kzalloc(dev, ++ sizeof(*pdata) + nbuttons * sizeof(*button), ++ GFP_KERNEL); ++ if (!pdata) ++ return ERR_PTR(-ENOMEM); ++ ++ pdata->buttons = (struct gpio_keys_button *)(pdata + 1); ++ pdata->nbuttons = nbuttons; ++ ++ pdata->rep = !!of_get_property(node, "autorepeat", NULL); ++ ++ of_property_read_string(node, "label", &pdata->name); ++ ++ i = 0; ++ for_each_available_child_of_node(node, pp) { ++ enum of_gpio_flags flags; ++ ++ button = &pdata->buttons[i++]; ++ ++ button->gpio = of_get_gpio_flags(pp, 0, &flags); ++ if (button->gpio < 0) { ++ error = button->gpio; ++ if (error != -ENOENT) { ++ if (error != -EPROBE_DEFER) ++ dev_err(dev, ++ "Failed to get gpio flags, error: %d\n", ++ error); ++ return ERR_PTR(error); ++ } ++ } else { ++ button->active_low = flags & OF_GPIO_ACTIVE_LOW; ++ } ++ ++ button->irq = irq_of_parse_and_map(pp, 0); ++ ++ if (!gpio_is_valid(button->gpio) && !button->irq) { ++ dev_err(dev, "Found button without gpios or irqs\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (of_property_read_u32(pp, "linux,code", &button->code)) { ++ dev_err(dev, "Button without keycode: 0x%x\n", ++ button->gpio); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ button->desc = of_get_property(pp, "label", NULL); ++ ++ if (of_property_read_u32(pp, "linux,input-type", &button->type)) ++ button->type = EV_KEY; ++ ++ button->wakeup = of_property_read_bool(pp, "wakeup-source") || ++ /* legacy name */ ++ of_property_read_bool(pp, "gpio-key,wakeup"); ++ ++ button->can_disable = !!of_get_property(pp, "linux,can-disable", NULL); ++ ++ if (of_property_read_u32(pp, "debounce-interval", ++ &button->debounce_interval)) ++ button->debounce_interval = 5; ++ } ++ ++ if (pdata->nbuttons == 0) ++ return ERR_PTR(-EINVAL); ++ ++ return pdata; ++} ++ ++static const struct of_device_id gpio_keys_of_match[] = { ++ { .compatible = "gpio-keys", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, gpio_keys_of_match); ++ ++#else ++ ++static inline struct gpio_keys_platform_data * ++gpio_keys_get_devtree_pdata(struct device *dev) ++{ ++ return ERR_PTR(-ENODEV); ++} ++ ++#endif ++ ++static int gpio_keys_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct gpio_keys_platform_data *pdata = dev_get_platdata(dev); ++ struct gpio_keys_drvdata *ddata; ++ struct input_dev *input; ++ size_t size; ++ int i, error; ++ int wakeup = 0; ++ ++ if (!pdata) { ++ pdata = gpio_keys_get_devtree_pdata(dev); ++ if (IS_ERR(pdata)) ++ return PTR_ERR(pdata); ++ } ++ ++ size = sizeof(struct gpio_keys_drvdata) + ++ pdata->nbuttons * sizeof(struct gpio_button_data); ++ ddata = devm_kzalloc(dev, size, GFP_KERNEL); ++ if (!ddata) { ++ dev_err(dev, "failed to allocate state\n"); ++ return -ENOMEM; ++ } ++ ++ input = devm_input_allocate_device(dev); ++ if (!input) { ++ dev_err(dev, "failed to allocate input device\n"); ++ return -ENOMEM; ++ } ++ ++ ddata->pdata = pdata; ++ ddata->input = input; ++ mutex_init(&ddata->disable_lock); ++ ++ platform_set_drvdata(pdev, ddata); ++ input_set_drvdata(input, ddata); ++ ++ input->name = pdata->name ? : pdev->name; ++ input->phys = "gpio-keys/input0"; ++ input->dev.parent = &pdev->dev; ++ input->open = gpio_keys_open; ++ input->close = gpio_keys_close; ++ ++ input->id.bustype = BUS_HOST; ++ input->id.vendor = 0x0001; ++ input->id.product = 0x0001; ++ input->id.version = 0x0100; ++ ++ /* Enable auto repeat feature of Linux input subsystem */ ++ if (pdata->rep) ++ __set_bit(EV_REP, input->evbit); ++ ++ for (i = 0; i < pdata->nbuttons; i++) { ++ const struct gpio_keys_button *button = &pdata->buttons[i]; ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ ++ error = gpio_keys_setup_key(pdev, input, bdata, button); ++ if (error) ++ return error; ++ ++ if (button->wakeup) ++ wakeup = 1; ++ } ++ ++ error = sysfs_create_group(&pdev->dev.kobj, &gpio_keys_attr_group); ++ if (error) { ++ dev_err(dev, "Unable to export keys/switches, error: %d\n", ++ error); ++ return error; ++ } ++ ++ error = input_register_device(input); ++ if (error) { ++ dev_err(dev, "Unable to register input device, error: %d\n", ++ error); ++ goto err_remove_group; ++ } ++ ++ device_init_wakeup(&pdev->dev, wakeup); ++ ++ return 0; ++ ++err_remove_group: ++ sysfs_remove_group(&pdev->dev.kobj, &gpio_keys_attr_group); ++ return error; ++} ++ ++static int gpio_keys_remove(struct platform_device *pdev) ++{ ++ sysfs_remove_group(&pdev->dev.kobj, &gpio_keys_attr_group); ++ ++ device_init_wakeup(&pdev->dev, 0); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int gpio_keys_suspend(struct device *dev) ++{ ++ struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev); ++ struct input_dev *input = ddata->input; ++ int i; ++ ++ if (device_may_wakeup(dev)) { ++ for (i = 0; i < ddata->pdata->nbuttons; i++) { ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ if (bdata->button->wakeup) ++ enable_irq_wake(bdata->irq); ++ } ++ } else { ++ mutex_lock(&input->mutex); ++ if (input->users) ++ gpio_keys_close(input); ++ mutex_unlock(&input->mutex); ++ } ++ ++ return 0; ++} ++ ++static int gpio_keys_resume(struct device *dev) ++{ ++ struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev); ++ struct input_dev *input = ddata->input; ++ int error = 0; ++ int i; ++ ++ if (device_may_wakeup(dev)) { ++ for (i = 0; i < ddata->pdata->nbuttons; i++) { ++ struct gpio_button_data *bdata = &ddata->data[i]; ++ if (bdata->button->wakeup) ++ disable_irq_wake(bdata->irq); ++ } ++ } else { ++ mutex_lock(&input->mutex); ++ if (input->users) ++ error = gpio_keys_open(input); ++ mutex_unlock(&input->mutex); ++ } ++ ++ if (error) ++ return error; ++ ++ gpio_keys_report_state(ddata); ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(gpio_keys_pm_ops, gpio_keys_suspend, gpio_keys_resume); ++ ++static struct platform_driver gpio_keys_device_driver = { ++ .probe = gpio_keys_probe, ++ .remove = gpio_keys_remove, ++ .driver = { ++ .name = "gpio-keys", ++ .pm = &gpio_keys_pm_ops, ++ .of_match_table = of_match_ptr(gpio_keys_of_match), ++ } ++}; ++ ++static int __init gpio_keys_init(void) ++{ ++ return platform_driver_register(&gpio_keys_device_driver); ++} ++ ++static void __exit gpio_keys_exit(void) ++{ ++ platform_driver_unregister(&gpio_keys_device_driver); ++} ++ ++late_initcall(gpio_keys_init); ++module_exit(gpio_keys_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Phil Blundell "); ++MODULE_DESCRIPTION("Keyboard driver for GPIOs"); ++MODULE_ALIAS("platform:gpio-keys"); +diff --git a/drivers/sstar/gpio_key_sample/key_test.c b/drivers/sstar/gpio_key_sample/key_test.c +new file mode 100755 +index 000000000000..3cdd46354c93 +--- /dev/null ++++ b/drivers/sstar/gpio_key_sample/key_test.c +@@ -0,0 +1,35 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define INPUT_DEV "/dev/input/event0" ++ ++int main(int argc, char * const argv[]) ++{ ++ int fd = 0; ++ ++ struct input_event event; ++ ++ int ret = 0; ++ ++ fd = open(INPUT_DEV, O_RDONLY); ++ ++ while(1){ ++ ret = read(fd, &event, sizeof(event)); ++ if(ret == -1) { ++ perror("Failed to read.\n"); ++ exit(1); ++ } ++ ++ if(event.type != EV_SYN) { ++ printf("type:%d, code:%d, value:%d\n", event.type, event.code, event.value); ++ } ++ } ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/gpio_key_sample/readme.txt b/drivers/sstar/gpio_key_sample/readme.txt +new file mode 100755 +index 000000000000..cf2e495e2a9c +--- /dev/null ++++ b/drivers/sstar/gpio_key_sample/readme.txt +@@ -0,0 +1,23 @@ ++1. Merge kernel_gpio_key_patch to your kernel. ++ #cd kernel ++ #make ++ ++2. Build gpio key driver: ++ -put gpio_key_driver and kernel in same path. ++ -If you want to change GPIO number, modify gpio_key_driver.c. In current sample, it uses PM_GPIO4. ++ -make driver in gpio_key_driver folder.It generate gpio_key_driver.ko ++ #cd gpio_key_driver ++ #make ++ ++3. copy gpio_ker_driver to your target board and insert driver. ++ /customer#insert gpio_key_driver.ko ++ After driver inserted, event0 will show in /dev/input folder in your taget board. ++ ++4. Press key button on target board, you will see some log as bellow. ++ "gpio_keys_gpio_report_event: code = 7 state=1 " ++ "gpio_keys_gpio_report_event: code = 7 state=0 " ++ ++5. Use key_test.c in user space to monitor key event. ++ ++ ++ +\ No newline at end of file +diff --git a/drivers/sstar/i2c/Kconfig b/drivers/sstar/i2c/Kconfig +new file mode 100755 +index 000000000000..ff1341ae70aa +--- /dev/null ++++ b/drivers/sstar/i2c/Kconfig +@@ -0,0 +1,11 @@ ++config MS_I2C ++ tristate "Sstar I2C driver" ++ help ++ Sstar I2C driver function ++ ++config MS_I2C_INT_ISR ++ bool "Support I2c ISR" ++ depends on MS_I2C ++ default n ++ help ++ Support I2c ISR +\ No newline at end of file +diff --git a/drivers/sstar/i2c/Makefile b/drivers/sstar/i2c/Makefile +new file mode 100755 +index 000000000000..77f05b2b9636 +--- /dev/null ++++ b/drivers/sstar/i2c/Makefile +@@ -0,0 +1,22 @@ ++# ++# Makefile for MStar IIC device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c ++EXTRA_CFLAGS += -Idrivers/sstar/i2c/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++ ++# specific options ++EXTRA_CFLAGS += -DTITANIA ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_I2C) += ms_iic.o $(CONFIG_SSTAR_CHIP_NAME)/mhal_iic.o ++ ++# export header files ++EXPORT_H_FILES += mdrv_iic_io.h +diff --git a/drivers/sstar/i2c/cedric/Makefile b/drivers/sstar/i2c/cedric/Makefile +new file mode 100755 +index 000000000000..1c2a8f4c3cc5 +--- /dev/null ++++ b/drivers/sstar/i2c/cedric/Makefile +@@ -0,0 +1,23 @@ ++# ++# Makefile for MStar IIC HAL drivers. ++# ++ ++ ++#ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++#include $(TOP_DIR)/modules.mk ++#endif ++ ++ ++#CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c ++EXTRA_CFLAGS += -Idrivers/sstar/i2c/cedric3 ++ ++# specific options ++#EXTRA_CFLAGS += -Iinclude/asm-mips/titania ++ ++# files ++#obj-$(CONFIG_MSTAR_IIC) += mhal_iic.o +diff --git a/drivers/sstar/i2c/cedric/mhal_iic.c b/drivers/sstar/i2c/cedric/mhal_iic.c +new file mode 100755 +index 000000000000..444732abb84b +--- /dev/null ++++ b/drivers/sstar/i2c/cedric/mhal_iic.c +@@ -0,0 +1,1699 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (3) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __FUNCTION__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase = 0; ++static U32 _gMChipIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase = u32Base; ++ _gMChipIO_MapBase=u32ChipBase; ++ //HWI2C_HAL_INFO("HWI2C IOMap base:%16lx Reg offset:%4x\n", u32Base, (U16)HWI2C_REG_BASE); ++ printk("\n HWI2C IOMap base:%x \n", u32Base); ++ printk("\n HWI2C u32ChipBase base:%x \n", u32ChipBase); ++ ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ //return ((volatile U16*)(_gMIO_MapBase))[u32RegAddr]; ++ return (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase, u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ //((volatile U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val; ++ //HAL_HWI2C_WriteByte(u32RegAddr,LOWBYTE(u16Val)); ++ //HAL_HWI2C_WriteByte(u32RegAddr+1,HIBYTE(u16Val)); ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u8Mask: %x bEnable: %x\n", _gMIO_MapBase, u32RegAddr, u8Mask, bEnable); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, u32MiuAddr); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port); ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ return TRUE; ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet; ++ HWI2C_HAL_FUNC(); ++ ++ //if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ // return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,TRUE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ {//port 2 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(int ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ ++ } ++ else if(ePort==1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else ++ { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ break; ++ } ++ } ++ } ++ } ++ HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_ERR("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_ERR("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++#endif +diff --git a/drivers/sstar/i2c/cedric/mhal_iic.h b/drivers/sstar/i2c/cedric/mhal_iic.h +new file mode 100755 +index 000000000000..8fbd0e4bd861 +--- /dev/null ++++ b/drivers/sstar/i2c/cedric/mhal_iic.h +@@ -0,0 +1,282 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(int ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/sstar/i2c/cedric/mhal_iic_reg.h b/drivers/sstar/i2c/cedric/mhal_iic_reg.h +new file mode 100755 +index 000000000000..f83c3adb670a +--- /dev/null ++++ b/drivers/sstar/i2c/cedric/mhal_iic_reg.h +@@ -0,0 +1,293 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_GPIO1_REG_BASE+ (0x01*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT2) ++ #define CHIP_MIIC0_PAD_MSK (__BIT2) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT1) ++ #define CHIP_MIIC1_PAD_MSK (__BIT1) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE ++ #define CHIP_DDCR_PAD_0 (0) ++ #define CHIP_DDCR_PAD_1 (__BIT1) ++ #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/sstar/i2c/infinity/Makefile b/drivers/sstar/i2c/infinity/Makefile +new file mode 100755 +index 000000000000..1c2a8f4c3cc5 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity/Makefile +@@ -0,0 +1,23 @@ ++# ++# Makefile for MStar IIC HAL drivers. ++# ++ ++ ++#ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++#include $(TOP_DIR)/modules.mk ++#endif ++ ++ ++#CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/sstar/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c ++EXTRA_CFLAGS += -Idrivers/sstar/i2c/cedric3 ++ ++# specific options ++#EXTRA_CFLAGS += -Iinclude/asm-mips/titania ++ ++# files ++#obj-$(CONFIG_MSTAR_IIC) += mhal_iic.o +diff --git a/drivers/sstar/i2c/infinity/mhal_iic.c b/drivers/sstar/i2c/infinity/mhal_iic.c +new file mode 100755 +index 000000000000..fa13a451e860 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity/mhal_iic.c +@@ -0,0 +1,1737 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __FUNCTION__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase = 0; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase = u32Base; ++ _gMChipIO_MapBase=u32ChipBase; ++ _gMClkIO_MapBase=u32ClkBase; ++ //HWI2C_HAL_INFO("HWI2C IOMap base:%16lx Reg offset:%4x\n", u32Base, (U16)HWI2C_REG_BASE); ++// printk(" HWI2C IOMap base:%x \n", u32Base); ++// printk("HWI2C u32ChipBase base:%x\n ", u32ChipBase); ++// printk(" HWI2C u32ClkBase base:%x \n", u32ClkBase); ++ ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ //return ((volatile U16*)(_gMIO_MapBase))[u32RegAddr]; ++ return (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase, u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ //((volatile U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val; ++ //HAL_HWI2C_WriteByte(u32RegAddr,LOWBYTE(u16Val)); ++ //HAL_HWI2C_WriteByte(u32RegAddr+1,HIBYTE(u16Val)); ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u8Mask: %x bEnable: %x\n", _gMIO_MapBase, u32RegAddr, u8Mask, bEnable); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMClkIO_MapBase, u32RegAddr); ++ //return ((volatile U16*)(_gMIO_MapBase))[u32RegAddr]; ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMClkIO_MapBase, u32RegAddr,(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ //((volatile U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val; ++ //HAL_HWI2C_WriteByte(u32RegAddr,LOWBYTE(u16Val)); ++ //HAL_HWI2C_WriteByte(u32RegAddr+1,HIBYTE(u16Val)); ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, u32MiuAddr); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port); ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ return TRUE; ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet; ++ HWI2C_HAL_FUNC(); ++ ++ //if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ // return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,TRUE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ {//port 2 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(int ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ //HAL_HWI2C_WriteClkByteMask((0x37*2), 0x08, 0x09); ++ } ++ else if(ePort==1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ //HAL_HWI2C_WriteClkByteMask((0x37*2), 0x800, 0x900); ++ } ++ else ++ { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ break; ++ } ++ } ++ } ++ } ++ HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_ERR("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_ERR("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++#endif +diff --git a/drivers/sstar/i2c/infinity/mhal_iic.h b/drivers/sstar/i2c/infinity/mhal_iic.h +new file mode 100755 +index 000000000000..58ba356fd298 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity/mhal_iic.h +@@ -0,0 +1,282 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(int ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/sstar/i2c/infinity/mhal_iic_reg.h b/drivers/sstar/i2c/infinity/mhal_iic_reg.h +new file mode 100755 +index 000000000000..01bc306cd649 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity/mhal_iic_reg.h +@@ -0,0 +1,293 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_GPIO1_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) //0x1EDC ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE ++ #define CHIP_DDCR_PAD_0 (0) ++ #define CHIP_DDCR_PAD_1 (__BIT1) ++ #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/sstar/i2c/infinity2/Makefile b/drivers/sstar/i2c/infinity2/Makefile +new file mode 100755 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity2/mhal_iic.c b/drivers/sstar/i2c/infinity2/mhal_iic.c +new file mode 100755 +index 000000000000..f0219ac1940e +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2/mhal_iic.c +@@ -0,0 +1,1882 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "infinity/gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port); ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port); ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++// U16 u16value; ++ U8 u8Port; ++ ++// if (!u32RegAddr) ++// { ++// HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++// return FALSE; ++// } ++ ++ HWI2C_HAL_FUNC(); ++ HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port); ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) - 1)) = u8Val; ++ } ++ else ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) )) = u8Val; ++ } ++ ++ return TRUE; ++ ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port); ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++static BOOL HAL_HWI2C_DelayClkRelease(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_RESERVE+u16PortOffset, _DELAY_CLK_RELEASE, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port); ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,TRUE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ HAL_HWI2C_DelayClkRelease(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x113300 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x113400 ++ *pu16Offset = (U16)0x100; ++ } ++ else if(u8Port==HAL_HWI2C_PORT2) ++ {//port 2 : bank register address 0x113500 ++ *pu16Offset = (U16)0x200; ++ } ++ else if(u8Port==HAL_HWI2C_PORT3) ++ {//port 3 : bank register address 0x113a00 ++ *pu16Offset = (U16)0x600; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x113400 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x113500 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x113600 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x600) ++ {//port 3 : bank register address 0x113A00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==E_HAL_HWI2C_PORT0_0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_1) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_2) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_3) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_3; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_0) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_2) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_3) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_3; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_4) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_4; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_0) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_1) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_2) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_3) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_3; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_4) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_4; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_5) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_5; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_6) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_6; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT2_7) ++ { ++ u8Value1 = CHIP_MIIC2_PAD_7; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC2, u8Value1, CHIP_MIIC2_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT3_0) ++ { ++ u8Value1 = CHIP_MIIC3_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC3, u8Value1, CHIP_MIIC3_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT3_1) ++ { ++ u8Value1 = CHIP_MIIC3_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC3, u8Value1, CHIP_MIIC3_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT3_2) ++ { ++ u8Value1 = CHIP_MIIC3_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC3, u8Value1, CHIP_MIIC3_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT3_3) ++ { ++ u8Value1 = CHIP_MIIC3_PAD_3; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC3, u8Value1, CHIP_MIIC3_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT3_4) ++ { ++ u8Value1 = CHIP_MIIC3_PAD_4; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC3, u8Value1, CHIP_MIIC3_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT3_5) ++ { ++ u8Value1 = CHIP_MIIC3_PAD_5; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC3, u8Value1, CHIP_MIIC3_PAD_MSK); ++ } ++ else ++ { ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 26; u16ClkLCnt = 28; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 35; u16ClkLCnt = 37; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 50; u16ClkLCnt = 64; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 113; u16ClkLCnt = 115; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 232; u16ClkLCnt = 234; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 255; u16ClkLCnt = 255; break; ++ default: ++ u16ClkHCnt = 35; u16ClkLCnt = 37; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,0,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype, mhal_i2c_feature_fp *fp) ++{ ++ return FALSE; ++} ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++#endif +diff --git a/drivers/sstar/i2c/infinity2/mhal_iic.h b/drivers/sstar/i2c/infinity2/mhal_iic.h +new file mode 100755 +index 000000000000..8a57fdaae5e0 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2/mhal_iic.h +@@ -0,0 +1,296 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @author MStar Semiconductor Inc. ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#define __BIT8 __BIT(8) ++#define __BIT9 __BIT(9) ++#define __BIT10 __BIT(10) ++ ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype, mhal_i2c_feature_fp *fp); ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/sstar/i2c/infinity2/mhal_iic_reg.h b/drivers/sstar/i2c/infinity2/mhal_iic_reg.h +new file mode 100755 +index 000000000000..89f836ad3b2e +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2/mhal_iic_reg.h +@@ -0,0 +1,317 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x102600) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x06*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x06*2)) ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT2) ++ #define CHIP_MIIC1_PAD_2 (__BIT3) ++ #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3) ++ #define CHIP_MIIC1_PAD_4 (__BIT4) ++ #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3|__BIT4) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x06*2)) ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT5) ++ #define CHIP_MIIC2_PAD_2 (__BIT6) ++ #define CHIP_MIIC2_PAD_3 (__BIT5|__BIT6) ++ #define CHIP_MIIC2_PAD_4 (__BIT7) ++ #define CHIP_MIIC2_PAD_5 (__BIT7|__BIT5) ++ #define CHIP_MIIC2_PAD_6 (__BIT7|__BIT6) ++ #define CHIP_MIIC2_PAD_7 (__BIT5|__BIT6|__BIT7) ++ #define CHIP_MIIC2_PAD_MSK (__BIT5|__BIT6|__BIT7) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x06*2)+0x1) //high byte address ++ #define CHIP_MIIC3_PAD_0 (0) ++ #define CHIP_MIIC3_PAD_1 (__BIT0) ++ #define CHIP_MIIC3_PAD_2 (__BIT1) ++ #define CHIP_MIIC3_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC3_PAD_4 (__BIT2) ++ #define CHIP_MIIC3_PAD_5 (__BIT2|__BIT0) ++ #define CHIP_MIIC3_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++//for port 4 ++#define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x06*2)+0x1)//high byte address ++ #define CHIP_MIIC4_PAD_0 (0) ++ #define CHIP_MIIC4_PAD_1 (__BIT3) ++ #define CHIP_MIIC4_PAD_2 (__BIT4) ++ #define CHIP_MIIC4_PAD_3 (__BIT3|__BIT4) ++ #define CHIP_MIIC4_PAD_MSK (__BIT3|__BIT4) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++#define REG_HWI2C_MIIC_RESERVE (HWI2C_REG_BASE+0x10*2) ++ #define _DELAY_CLK_RELEASE (__BIT6) ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/sstar/i2c/infinity2m/Makefile b/drivers/sstar/i2c/infinity2m/Makefile +new file mode 100644 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2m/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity2m/mhal_iic.c b/drivers/sstar/i2c/infinity2m/mhal_iic.c +new file mode 100755 +index 000000000000..8b200df185c1 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2m/mhal_iic.c +@@ -0,0 +1,1826 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) - 1)) = u8Val; ++ } ++ else ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) )) = u8Val; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ ++ /*Enable I2C DMA wait MIU done*/ ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_RESERVED0+u16PortOffset, __BIT7|__BIT4, TRUE); ++ ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ // HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,FALSE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if(u8Port==HAL_HWI2C_PORT2) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if(u8Port==HAL_HWI2C_PORT3) ++ {//port 3 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U32 u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ U8 u8Val = CHIP_MIIC0_PAD_1; ++ U8 u8Mask = CHIP_MIIC0_PAD_MSK; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort >= E_HAL_HWI2C_PORT0_0) && (ePort <= E_HAL_HWI2C_PORT0_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ u8Mask = CHIP_MIIC0_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT1_0) && (ePort <= E_HAL_HWI2C_PORT1_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC1; ++ u8Mask = CHIP_MIIC1_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT2_0) && (ePort <= E_HAL_HWI2C_PORT2_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC2; ++ u8Mask = CHIP_MIIC2_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT3_0) && (ePort <= E_HAL_HWI2C_PORT3_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC3; ++ u8Mask = CHIP_MIIC3_PAD_MSK; ++ } ++ ++ switch(ePort) { ++ case E_HAL_HWI2C_PORT0_0: u8Val = CHIP_MIIC0_PAD_0; break; ++ case E_HAL_HWI2C_PORT0_1: u8Val = CHIP_MIIC0_PAD_1; break; ++ case E_HAL_HWI2C_PORT0_2: u8Val = CHIP_MIIC0_PAD_2; break; ++ case E_HAL_HWI2C_PORT0_3: u8Val = CHIP_MIIC0_PAD_3; break; ++ case E_HAL_HWI2C_PORT0_4: u8Val = CHIP_MIIC0_PAD_4; break; ++ case E_HAL_HWI2C_PORT1_0: u8Val = CHIP_MIIC1_PAD_0; break; ++ case E_HAL_HWI2C_PORT1_1: u8Val = CHIP_MIIC1_PAD_1; break; ++ case E_HAL_HWI2C_PORT1_2: u8Val = CHIP_MIIC1_PAD_2; break; ++ case E_HAL_HWI2C_PORT1_3: u8Val = CHIP_MIIC1_PAD_3; break; ++ case E_HAL_HWI2C_PORT1_4: u8Val = CHIP_MIIC1_PAD_4; break; ++ case E_HAL_HWI2C_PORT1_5: u8Val = CHIP_MIIC1_PAD_5; break; ++ case E_HAL_HWI2C_PORT2_0: u8Val = CHIP_MIIC2_PAD_0; break; ++ case E_HAL_HWI2C_PORT2_1: u8Val = CHIP_MIIC2_PAD_1; break; ++ case E_HAL_HWI2C_PORT2_2: u8Val = CHIP_MIIC2_PAD_2; break; ++ case E_HAL_HWI2C_PORT2_3: u8Val = CHIP_MIIC2_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_0: u8Val = CHIP_MIIC3_PAD_0; break; ++ case E_HAL_HWI2C_PORT3_1: u8Val = CHIP_MIIC3_PAD_1; break; ++ case E_HAL_HWI2C_PORT3_2: u8Val = CHIP_MIIC3_PAD_2; break; ++ case E_HAL_HWI2C_PORT3_3: u8Val = CHIP_MIIC3_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_4: u8Val = CHIP_MIIC3_PAD_4; break; ++ case E_HAL_HWI2C_PORT3_5: u8Val = CHIP_MIIC3_PAD_5; break; ++ default: ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ ++ HAL_HWI2C_WriteChipByteMask(u32RegAddr, u8Val, u8Mask); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ // HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,0,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++ ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp) ++{ ++ return FALSE; ++} ++void HAL_HWI2C_IrqFree(U32 u32irq) ++{ ++ return; ++} ++void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemInit(U8 u8Port) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port) ++{ ++ return; ++} ++ ++#endif +diff --git a/drivers/sstar/i2c/infinity2m/mhal_iic.h b/drivers/sstar/i2c/infinity2m/mhal_iic.h +new file mode 100755 +index 000000000000..5e3e3a93ed9d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2m/mhal_iic.h +@@ -0,0 +1,294 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqFree(U32 u32irq); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemInit(U8 u8Port); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port); ++ ++ ++#endif //_MHAL_HWI2C_H_ +diff --git a/drivers/sstar/i2c/infinity2m/mhal_iic_reg.h b/drivers/sstar/i2c/infinity2m/mhal_iic_reg.h +new file mode 100644 +index 000000000000..e60c79d0c8e0 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity2m/mhal_iic_reg.h +@@ -0,0 +1,304 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223000 //0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_4 (__BIT2) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT5) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_4 (__BIT6) ++ #define CHIP_MIIC1_PAD_5 (__BIT4|__BIT6) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5|__BIT6) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT0) ++ #define CHIP_MIIC2_PAD_2 (__BIT1) ++ #define CHIP_MIIC2_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC2_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC3_PAD_0 (0) ++ #define CHIP_MIIC3_PAD_1 (__BIT2) ++ #define CHIP_MIIC3_PAD_2 (__BIT3) ++ #define CHIP_MIIC3_PAD_3 (__BIT3|__BIT2) ++ #define CHIP_MIIC3_PAD_4 (__BIT4) ++ #define CHIP_MIIC3_PAD_5 (__BIT4|__BIT0) ++ #define CHIP_MIIC3_PAD_MSK (__BIT2|__BIT3|__BIT4) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++#define REG_HWI2C_DMA_RESERVED0 (HWI2C_REG_BASE+0x30*2) ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ +diff --git a/drivers/sstar/i2c/infinity3/Makefile b/drivers/sstar/i2c/infinity3/Makefile +new file mode 100755 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity3/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity3/mhal_iic.c b/drivers/sstar/i2c/infinity3/mhal_iic.c +new file mode 100755 +index 000000000000..7f25e66ed58e +--- /dev/null ++++ b/drivers/sstar/i2c/infinity3/mhal_iic.c +@@ -0,0 +1,1805 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ //((volatile U8*)(_gMIO_MapBase[u8Port]))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,FALSE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==E_HAL_HWI2C_PORT0_0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_1) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_2) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_3) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_3; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_0) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_2) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else ++ { ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,0,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++ ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp) ++{ ++ return FALSE; ++} ++void HAL_HWI2C_IrqFree(U32 u32irq) ++{ ++ return; ++} ++void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemInit(U8 u8Port) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port) ++{ ++ return; ++} ++ ++#endif +diff --git a/drivers/sstar/i2c/infinity3/mhal_iic.h b/drivers/sstar/i2c/infinity3/mhal_iic.h +new file mode 100755 +index 000000000000..3c828678609e +--- /dev/null ++++ b/drivers/sstar/i2c/infinity3/mhal_iic.h +@@ -0,0 +1,295 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqFree(U32 u32irq); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemInit(U8 u8Port); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/sstar/i2c/infinity3/mhal_iic_reg.h b/drivers/sstar/i2c/infinity3/mhal_iic_reg.h +new file mode 100755 +index 000000000000..4cfd398b9cb9 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity3/mhal_iic_reg.h +@@ -0,0 +1,298 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_GPIO1_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) //0x1EDC ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT4) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE ++ #define CHIP_DDCR_PAD_0 (0) ++ #define CHIP_DDCR_PAD_1 (__BIT1) ++ #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/sstar/i2c/infinity5/Makefile b/drivers/sstar/i2c/infinity5/Makefile +new file mode 100644 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity5/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity5/mhal_iic.c b/drivers/sstar/i2c/infinity5/mhal_iic.c +new file mode 100755 +index 000000000000..0bd4cb9ccefb +--- /dev/null ++++ b/drivers/sstar/i2c/infinity5/mhal_iic.c +@@ -0,0 +1,1818 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ struct timespec delay; ++ delay.tv_nsec = u32Us * 1000; ++ delay.tv_sec = 0; ++ hrtimer_nanosleep(&delay, NULL, HRTIMER_MODE_REL, CLOCK_MONOTONIC); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) - 1)) = u8Val; ++ } ++ else ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) )) = u8Val; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ ++ /*Enable I2C DMA wait MIU done*/ ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_RESERVED0+u16PortOffset, __BIT7|__BIT4, TRUE); ++ ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ // HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,FALSE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if(u8Port==HAL_HWI2C_PORT2) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if(u8Port==HAL_HWI2C_PORT3) ++ {//port 3 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U32 u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ U8 u8Val = CHIP_MIIC0_PAD_1; ++ U8 u8Mask = CHIP_MIIC0_PAD_MSK; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort >= E_HAL_HWI2C_PORT0_0) && (ePort <= E_HAL_HWI2C_PORT0_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ u8Mask = CHIP_MIIC0_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT1_0) && (ePort <= E_HAL_HWI2C_PORT1_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC1; ++ u8Mask = CHIP_MIIC1_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT2_0) && (ePort <= E_HAL_HWI2C_PORT2_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC2; ++ u8Mask = CHIP_MIIC2_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT3_0) && (ePort <= E_HAL_HWI2C_PORT3_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC3; ++ u8Mask = CHIP_MIIC3_PAD_MSK; ++ } ++ ++ switch(ePort) { ++ case E_HAL_HWI2C_PORT0_0: u8Val = CHIP_MIIC0_PAD_0; break; ++ case E_HAL_HWI2C_PORT0_1: u8Val = CHIP_MIIC0_PAD_1; break; ++ case E_HAL_HWI2C_PORT0_2: u8Val = CHIP_MIIC0_PAD_2; break; ++ case E_HAL_HWI2C_PORT0_3: u8Val = CHIP_MIIC0_PAD_3; break; ++ case E_HAL_HWI2C_PORT1_0: u8Val = CHIP_MIIC1_PAD_0; break; ++ case E_HAL_HWI2C_PORT1_1: u8Val = CHIP_MIIC1_PAD_1; break; ++ case E_HAL_HWI2C_PORT1_2: u8Val = CHIP_MIIC1_PAD_2; break; ++ case E_HAL_HWI2C_PORT1_3: u8Val = CHIP_MIIC1_PAD_3; break; ++ case E_HAL_HWI2C_PORT1_4: u8Val = CHIP_MIIC1_PAD_4; break; ++ case E_HAL_HWI2C_PORT2_0: u8Val = CHIP_MIIC2_PAD_0; break; ++ case E_HAL_HWI2C_PORT2_1: u8Val = CHIP_MIIC2_PAD_1; break; ++ case E_HAL_HWI2C_PORT2_2: u8Val = CHIP_MIIC2_PAD_2; break; ++ case E_HAL_HWI2C_PORT2_3: u8Val = CHIP_MIIC2_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_0: u8Val = CHIP_MIIC3_PAD_0; break; ++ case E_HAL_HWI2C_PORT3_1: u8Val = CHIP_MIIC3_PAD_1; break; ++ case E_HAL_HWI2C_PORT3_2: u8Val = CHIP_MIIC3_PAD_2; break; ++ case E_HAL_HWI2C_PORT3_3: u8Val = CHIP_MIIC3_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_4: u8Val = CHIP_MIIC3_PAD_4; break; ++ case E_HAL_HWI2C_PORT3_5: u8Val = CHIP_MIIC3_PAD_5; break; ++ default: ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ ++ HAL_HWI2C_WriteChipByteMask(u32RegAddr, u8Val, u8Mask); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ HAL_HWI2C_ExtraDelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ HAL_HWI2C_ExtraDelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ HAL_HWI2C_ExtraDelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ HAL_HWI2C_ExtraDelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ // HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,0,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++ ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp) ++{ ++ return FALSE; ++} ++void HAL_HWI2C_IrqFree(U32 u32irq) ++{ ++ return; ++} ++void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemInit(U8 u8Port) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port) ++{ ++ return; ++} ++ ++#endif +diff --git a/drivers/sstar/i2c/infinity5/mhal_iic.h b/drivers/sstar/i2c/infinity5/mhal_iic.h +new file mode 100755 +index 000000000000..3c828678609e +--- /dev/null ++++ b/drivers/sstar/i2c/infinity5/mhal_iic.h +@@ -0,0 +1,295 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqFree(U32 u32irq); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemInit(U8 u8Port); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/sstar/i2c/infinity5/mhal_iic_reg.h b/drivers/sstar/i2c/infinity5/mhal_iic_reg.h +new file mode 100644 +index 000000000000..339bc4a8f75a +--- /dev/null ++++ b/drivers/sstar/i2c/infinity5/mhal_iic_reg.h +@@ -0,0 +1,303 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223000 //0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT5) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_4 (__BIT6) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5|__BIT6) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT0) ++ #define CHIP_MIIC2_PAD_2 (__BIT1) ++ #define CHIP_MIIC2_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC2_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC3_PAD_0 (0) ++ #define CHIP_MIIC3_PAD_1 (__BIT2) ++ #define CHIP_MIIC3_PAD_2 (__BIT3) ++ #define CHIP_MIIC3_PAD_3 (__BIT3|__BIT2) ++ #define CHIP_MIIC3_PAD_4 (__BIT4) ++ #define CHIP_MIIC3_PAD_5 (__BIT4|__BIT0) ++ #define CHIP_MIIC3_PAD_MSK (__BIT2|__BIT3|__BIT4) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++#define REG_HWI2C_DMA_RESERVED0 (HWI2C_REG_BASE+0x30*2) ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/sstar/i2c/infinity6/Makefile b/drivers/sstar/i2c/infinity6/Makefile +new file mode 100644 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity6/mhal_iic.c b/drivers/sstar/i2c/infinity6/mhal_iic.c +new file mode 100755 +index 000000000000..a2393bd94a69 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6/mhal_iic.c +@@ -0,0 +1,1828 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) - 1)) = u8Val; ++ } ++ else ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) )) = u8Val; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ ++ /*Enable I2C DMA wait MIU done*/ ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_RESERVED0+u16PortOffset, __BIT7|__BIT4, TRUE); ++ ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ // HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,FALSE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if(u8Port==HAL_HWI2C_PORT2) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if(u8Port==HAL_HWI2C_PORT3) ++ {//port 3 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U32 u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ U8 u8Val = CHIP_MIIC0_PAD_1; ++ U8 u8Mask = CHIP_MIIC0_PAD_MSK; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort >= E_HAL_HWI2C_PORT0_0) && (ePort <= E_HAL_HWI2C_PORT0_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ u8Mask = CHIP_MIIC0_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT1_0) && (ePort <= E_HAL_HWI2C_PORT1_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC1; ++ u8Mask = CHIP_MIIC1_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT2_0) && (ePort <= E_HAL_HWI2C_PORT2_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC2; ++ u8Mask = CHIP_MIIC2_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT3_0) && (ePort <= E_HAL_HWI2C_PORT3_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC3; ++ u8Mask = CHIP_MIIC3_PAD_MSK; ++ } ++ ++ switch(ePort) { ++ case E_HAL_HWI2C_PORT0_0: u8Val = CHIP_MIIC0_PAD_0; break; ++ case E_HAL_HWI2C_PORT0_1: u8Val = CHIP_MIIC0_PAD_1; break; ++ case E_HAL_HWI2C_PORT0_2: u8Val = CHIP_MIIC0_PAD_2; break; ++ case E_HAL_HWI2C_PORT0_3: u8Val = CHIP_MIIC0_PAD_3; break; ++ case E_HAL_HWI2C_PORT0_4: u8Val = CHIP_MIIC0_PAD_4; break; ++ case E_HAL_HWI2C_PORT1_0: u8Val = CHIP_MIIC1_PAD_0; break; ++ case E_HAL_HWI2C_PORT1_1: u8Val = CHIP_MIIC1_PAD_1; break; ++ case E_HAL_HWI2C_PORT1_2: u8Val = CHIP_MIIC1_PAD_2; break; ++ case E_HAL_HWI2C_PORT1_3: u8Val = CHIP_MIIC1_PAD_3; break; ++ // case E_HAL_HWI2C_PORT1_4: u8Val = CHIP_MIIC1_PAD_4; break; ++ case E_HAL_HWI2C_PORT2_0: u8Val = CHIP_MIIC2_PAD_0; break; ++ case E_HAL_HWI2C_PORT2_1: u8Val = CHIP_MIIC2_PAD_1; break; ++ case E_HAL_HWI2C_PORT2_2: u8Val = CHIP_MIIC2_PAD_2; break; ++ case E_HAL_HWI2C_PORT2_3: u8Val = CHIP_MIIC2_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_0: u8Val = CHIP_MIIC3_PAD_0; break; ++ case E_HAL_HWI2C_PORT3_1: u8Val = CHIP_MIIC3_PAD_1; break; ++ case E_HAL_HWI2C_PORT3_2: u8Val = CHIP_MIIC3_PAD_2; break; ++ case E_HAL_HWI2C_PORT3_3: u8Val = CHIP_MIIC3_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_4: u8Val = CHIP_MIIC3_PAD_4; break; ++ case E_HAL_HWI2C_PORT3_5: u8Val = CHIP_MIIC3_PAD_5; break; ++ default: ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ ++ HAL_HWI2C_WriteChipByteMask(u32RegAddr, u8Val, u8Mask); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ // HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,0,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //set DMA buffer MIU address ++ HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset, g_stPortCfg[u8Port].u32DmaPhyAddr); ++ ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++ ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp) ++{ ++ return FALSE; ++} ++void HAL_HWI2C_IrqFree(U32 u32irq) ++{ ++ return; ++} ++void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemInit(U8 u8Port) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port) ++{ ++ return; ++} ++ ++#endif +diff --git a/drivers/sstar/i2c/infinity6/mhal_iic.h b/drivers/sstar/i2c/infinity6/mhal_iic.h +new file mode 100755 +index 000000000000..5e3e3a93ed9d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6/mhal_iic.h +@@ -0,0 +1,294 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqFree(U32 u32irq); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemInit(U8 u8Port); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port); ++ ++ ++#endif //_MHAL_HWI2C_H_ +diff --git a/drivers/sstar/i2c/infinity6/mhal_iic_reg.h b/drivers/sstar/i2c/infinity6/mhal_iic_reg.h +new file mode 100644 +index 000000000000..dfc7f5974718 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6/mhal_iic_reg.h +@@ -0,0 +1,302 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223000 //0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_4 (__BIT2) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT5) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT0) ++ #define CHIP_MIIC2_PAD_2 (__BIT1) ++ #define CHIP_MIIC2_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC2_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC3_PAD_0 (0) ++ #define CHIP_MIIC3_PAD_1 (__BIT2) ++ #define CHIP_MIIC3_PAD_2 (__BIT3) ++ #define CHIP_MIIC3_PAD_3 (__BIT3|__BIT2) ++ #define CHIP_MIIC3_PAD_4 (__BIT4) ++ #define CHIP_MIIC3_PAD_5 (__BIT4|__BIT0) ++ #define CHIP_MIIC3_PAD_MSK (__BIT2|__BIT3|__BIT4) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++#define REG_HWI2C_DMA_RESERVED0 (HWI2C_REG_BASE+0x30*2) ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ +diff --git a/drivers/sstar/i2c/infinity6b0/Makefile b/drivers/sstar/i2c/infinity6b0/Makefile +new file mode 100644 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6b0/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity6b0/mhal_iic.c b/drivers/sstar/i2c/infinity6b0/mhal_iic.c +new file mode 100755 +index 000000000000..abeaf95a3bfb +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6b0/mhal_iic.c +@@ -0,0 +1,1829 @@ ++/* ++* mhal_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) - 1)) = u8Val; ++ } ++ else ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) )) = u8Val; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ ++ /*Enable I2C DMA wait MIU done*/ ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_RESERVED0+u16PortOffset, __BIT7|__BIT4, TRUE); ++ ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ Chip_Flush_Cache_Range((u32)pu8SrcData, u32Length); ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ Chip_Flush_Cache_Range((u32)pMiuData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ Chip_Inv_Cache_Range((u32)pMiuData, u32Length); ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ Chip_Inv_Cache_Range((u32)pu8DstData, u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ // HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ udelay(20); ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,FALSE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if(u8Port==HAL_HWI2C_PORT2) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if(u8Port==HAL_HWI2C_PORT3) ++ {//port 3 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U32 u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ U8 u8Val = CHIP_MIIC0_PAD_1; ++ U8 u8Mask = CHIP_MIIC0_PAD_MSK; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort >= E_HAL_HWI2C_PORT0_0) && (ePort <= E_HAL_HWI2C_PORT0_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ u8Mask = CHIP_MIIC0_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT1_0) && (ePort <= E_HAL_HWI2C_PORT1_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC1; ++ u8Mask = CHIP_MIIC1_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT2_0) && (ePort <= E_HAL_HWI2C_PORT2_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC2; ++ u8Mask = CHIP_MIIC2_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT3_0) && (ePort <= E_HAL_HWI2C_PORT3_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC3; ++ u8Mask = CHIP_MIIC3_PAD_MSK; ++ } ++ ++ switch(ePort) { ++ case E_HAL_HWI2C_PORT0_0: u8Val = CHIP_MIIC0_PAD_0; break; ++ case E_HAL_HWI2C_PORT0_1: u8Val = CHIP_MIIC0_PAD_1; break; ++ case E_HAL_HWI2C_PORT0_2: u8Val = CHIP_MIIC0_PAD_2; break; ++ case E_HAL_HWI2C_PORT0_3: u8Val = CHIP_MIIC0_PAD_3; break; ++ case E_HAL_HWI2C_PORT0_4: u8Val = CHIP_MIIC0_PAD_4; break; ++ case E_HAL_HWI2C_PORT1_0: u8Val = CHIP_MIIC1_PAD_0; break; ++ case E_HAL_HWI2C_PORT1_1: u8Val = CHIP_MIIC1_PAD_1; break; ++ case E_HAL_HWI2C_PORT1_2: u8Val = CHIP_MIIC1_PAD_2; break; ++ case E_HAL_HWI2C_PORT1_3: u8Val = CHIP_MIIC1_PAD_3; break; ++ // case E_HAL_HWI2C_PORT1_4: u8Val = CHIP_MIIC1_PAD_4; break; ++ case E_HAL_HWI2C_PORT2_0: u8Val = CHIP_MIIC2_PAD_0; break; ++ case E_HAL_HWI2C_PORT2_1: u8Val = CHIP_MIIC2_PAD_1; break; ++ case E_HAL_HWI2C_PORT2_2: u8Val = CHIP_MIIC2_PAD_2; break; ++ case E_HAL_HWI2C_PORT2_3: u8Val = CHIP_MIIC2_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_0: u8Val = CHIP_MIIC3_PAD_0; break; ++ case E_HAL_HWI2C_PORT3_1: u8Val = CHIP_MIIC3_PAD_1; break; ++ case E_HAL_HWI2C_PORT3_2: u8Val = CHIP_MIIC3_PAD_2; break; ++ case E_HAL_HWI2C_PORT3_3: u8Val = CHIP_MIIC3_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_4: u8Val = CHIP_MIIC3_PAD_4; break; ++ case E_HAL_HWI2C_PORT3_5: u8Val = CHIP_MIIC3_PAD_5; break; ++ default: ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ ++ HAL_HWI2C_WriteChipByteMask(u32RegAddr, u8Val, u8Mask); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ // HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++ ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp) ++{ ++ return FALSE; ++} ++void HAL_HWI2C_IrqFree(U32 u32irq) ++{ ++ return; ++} ++void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemInit(U8 u8Port) ++{ ++ return; ++} ++void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port) ++{ ++ return; ++} ++ ++#endif +diff --git a/drivers/sstar/i2c/infinity6b0/mhal_iic.h b/drivers/sstar/i2c/infinity6b0/mhal_iic.h +new file mode 100755 +index 000000000000..5e3e3a93ed9d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6b0/mhal_iic.h +@@ -0,0 +1,294 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqFree(U32 u32irq); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemInit(U8 u8Port); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port); ++ ++ ++#endif //_MHAL_HWI2C_H_ +diff --git a/drivers/sstar/i2c/infinity6b0/mhal_iic_reg.h b/drivers/sstar/i2c/infinity6b0/mhal_iic_reg.h +new file mode 100644 +index 000000000000..dfc7f5974718 +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6b0/mhal_iic_reg.h +@@ -0,0 +1,302 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223000 //0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_4 (__BIT2) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT5) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT0) ++ #define CHIP_MIIC2_PAD_2 (__BIT1) ++ #define CHIP_MIIC2_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC2_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x16*2+1)) ++ #define CHIP_MIIC3_PAD_0 (0) ++ #define CHIP_MIIC3_PAD_1 (__BIT2) ++ #define CHIP_MIIC3_PAD_2 (__BIT3) ++ #define CHIP_MIIC3_PAD_3 (__BIT3|__BIT2) ++ #define CHIP_MIIC3_PAD_4 (__BIT4) ++ #define CHIP_MIIC3_PAD_5 (__BIT4|__BIT0) ++ #define CHIP_MIIC3_PAD_MSK (__BIT2|__BIT3|__BIT4) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++#define REG_HWI2C_DMA_RESERVED0 (HWI2C_REG_BASE+0x30*2) ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ +diff --git a/drivers/sstar/i2c/infinity6e/Makefile b/drivers/sstar/i2c/infinity6e/Makefile +new file mode 100755 +index 000000000000..94258202838d +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6e/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/i2c +diff --git a/drivers/sstar/i2c/infinity6e/mhal_iic.c b/drivers/sstar/i2c/infinity6e/mhal_iic.c +new file mode 100755 +index 000000000000..5cef2d52ef3f +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6e/mhal_iic.c +@@ -0,0 +1,2266 @@ ++/* ++* mhal_iic.c- Sigmastarz ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++static CamOsTsem_t g_stSemaphore[HAL_HWI2C_PORTS]; ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) - 1)) = u8Val; ++ } ++ else ++ { ++ (*(volatile U8*)(_gMIO_MapBase[u8Port]+(u32RegAddr << 1) )) = u8Val; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U8 HAL_HWI2C_ReadChipPmByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ //HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", 0xFD007E00, u32RegAddr,(0xFD007E00+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(0xFD007E00+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++BOOL HAL_HWI2C_WriteChipPmByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ //HWI2C_HAL_FUNC(); ++ //("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", 0xFD007E00, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(0xFD007E00+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(0xFD007E00+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(0xFD007E00+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipPmByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ //HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipPmByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipPmByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, bEnable); ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Core2DMA_SetINT ++/// @brief \b Function \b Description: Enable Interrupt (set int en core to DMA inside IP) ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Core2DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_RESERVE0+u16PortOffset, _INT_CFG_CORE2DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ ++ /*Enable I2C DMA wait MIU done*/ ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_RESERVED0+u16PortOffset, __BIT7|__BIT4, TRUE); ++ ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++ ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ Chip_Flush_Cache_Range((u32)pu8SrcData, u32Length); ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ Chip_Flush_Cache_Range((u32)pMiuData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ Chip_Inv_Cache_Range((u32)pMiuData, u32Length); ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ Chip_Inv_Cache_Range((u32)pu8DstData, u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ // HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ udelay(20); ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetGroupLen ++/// @brief \b Function \b Description: Set HWI2C DMA group length (nwrite N) ++/// @param \b u32DataLen : group length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetGroupLen(U16 u16PortOffset, U32 u32GroupLen) ++{ ++ U32 u32GroupLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32GroupLenSet = u32GroupLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_GROUP_LEN+u16PortOffset, u32GroupLenSet); ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnWnmode(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_WNMODE_EN+u16PortOffset, _DMA_CTL_WNMODE_EN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetWaitCnt ++/// @brief \b Function \b Description: Set wait cnt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetWaitCnt(U16 u16PortOffset, U32 u32WaitCnt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_WN_WAITCNT+u16PortOffset, u32WaitCnt); ++} ++ ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,FALSE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if(u8Port==HAL_HWI2C_PORT2) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if(u8Port==HAL_HWI2C_PORT3) ++ {//port 3 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U32 u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ U8 u8Val = CHIP_MIIC0_PAD_1; ++ U8 u8Mask = CHIP_MIIC0_PAD_MSK; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort >= E_HAL_HWI2C_PORT0_0) && (ePort <= E_HAL_HWI2C_PORT0_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC0; ++ u8Mask = CHIP_MIIC0_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT1_0) && (ePort <= E_HAL_HWI2C_PORT1_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC1; ++ u8Mask = CHIP_MIIC1_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT2_0) && (ePort <= E_HAL_HWI2C_PORT2_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC2; ++ u8Mask = CHIP_MIIC2_PAD_MSK; ++ } ++ else if((ePort >= E_HAL_HWI2C_PORT3_0) && (ePort <= E_HAL_HWI2C_PORT3_7)) ++ { ++ u32RegAddr = CHIP_REG_HWI2C_MIIC3; ++ u8Mask = CHIP_MIIC3_PAD_MSK; ++ } ++ ++ switch(ePort) { ++ case E_HAL_HWI2C_PORT0_0: u8Val = CHIP_MIIC0_PAD_0; break; ++ case E_HAL_HWI2C_PORT0_1: u8Val = CHIP_MIIC0_PAD_1; break; ++ case E_HAL_HWI2C_PORT0_2: u8Val = CHIP_MIIC0_PAD_2; break; ++ case E_HAL_HWI2C_PORT0_3: u8Val = CHIP_MIIC0_PAD_3; break; ++ case E_HAL_HWI2C_PORT0_4: u8Val = CHIP_MIIC0_PAD_4; break; ++ case E_HAL_HWI2C_PORT0_5: u8Val = CHIP_MIIC0_PAD_5; break; ++ case E_HAL_HWI2C_PORT1_0: u8Val = CHIP_MIIC1_PAD_0; break; ++ case E_HAL_HWI2C_PORT1_1: u8Val = CHIP_MIIC1_PAD_1; break; ++ case E_HAL_HWI2C_PORT1_2: u8Val = CHIP_MIIC1_PAD_2; break; ++ case E_HAL_HWI2C_PORT1_3: u8Val = CHIP_MIIC1_PAD_3; break; ++ // case E_HAL_HWI2C_PORT1_4: u8Val = CHIP_MIIC1_PAD_4; break; ++ case E_HAL_HWI2C_PORT2_0: u8Val = CHIP_MIIC2_PAD_0; break; ++ case E_HAL_HWI2C_PORT2_1: u8Val = CHIP_MIIC2_PAD_1; break; ++ case E_HAL_HWI2C_PORT2_2: u8Val = CHIP_MIIC2_PAD_2; break; ++ case E_HAL_HWI2C_PORT2_3: u8Val = CHIP_MIIC2_PAD_3; break; ++ case E_HAL_HWI2C_PORT2_4: ++ u8Val = CHIP_MIIC2_PAD_4; ++ HAL_HWI2C_WriteChipPmByteMask(CHIP_REG_PM_PAD_EXT_MODE1, CHIP_PAD_PM_I2CM_SCL, CHIP_PAD_PM_I2CM_SCL); ++ HAL_HWI2C_WriteChipPmByteMask(CHIP_REG_PM_PAD_EXT_MODE1, CHIP_PAD_PM_I2CM_SDA, CHIP_PAD_PM_I2CM_SDA); ++ break; ++ case E_HAL_HWI2C_PORT2_5: u8Val = CHIP_MIIC2_PAD_5; break; ++ case E_HAL_HWI2C_PORT3_0: u8Val = CHIP_MIIC3_PAD_0; break; ++ case E_HAL_HWI2C_PORT3_1: u8Val = CHIP_MIIC3_PAD_1; break; ++ case E_HAL_HWI2C_PORT3_2: u8Val = CHIP_MIIC3_PAD_2; break; ++ case E_HAL_HWI2C_PORT3_3: u8Val = CHIP_MIIC3_PAD_3; break; ++ case E_HAL_HWI2C_PORT3_4: u8Val = CHIP_MIIC3_PAD_4; break; ++ case E_HAL_HWI2C_PORT3_5: u8Val = CHIP_MIIC3_PAD_5; break; ++ default: ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ ++ HAL_HWI2C_WriteChipByteMask(u32RegAddr, u8Val, u8Mask); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ bRet &= HAL_HWI2C_DMA_Core2DMA_SetINT(u16PortOffset,bEnable); //DMA enable, always enable ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,FALSE); //force int disable, prevent pulling time out ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ // HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TsemInit ++/// @brief \b Function \b Description: init Tcond ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_DMA_TsemInit(U8 u8Port) ++{ ++ CamOsTsemInit(&g_stSemaphore[u8Port], 0); ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TsemDeinit ++/// @brief \b Function \b Description: deinit Tcond ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port) ++{ ++ CamOsTsemDeinit(&g_stSemaphore[u8Port]); ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ // HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //set DMA buffer MIU address ++ HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset, g_stPortCfg[u8Port].u32DmaPhyAddr); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ // HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_I2c0_Isr ++/// @brief \b Function \b Description: Isr of DMA tx done ++/// @param \b IntNum : Int number, void * dev_id ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static irqreturn_t HAL_HWI2C_DMA_WN_I2c0_Isr(int IntNum, void* dev_id) ++{ ++ U16 u16PortOffset; ++ ++ HAL_HWI2C_SetPortRegOffset(0, &u16PortOffset); ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ CamOsTsemUp(&g_stSemaphore[0]); ++ return 0; ++}; ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_I2c1_Isr ++/// @brief \b Function \b Description: Isr of DMA tx done ++/// @param \b IntNum : Int number, void * dev_id ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static irqreturn_t HAL_HWI2C_DMA_WN_I2c1_Isr(int IntNum, void* dev_id) ++{ ++ U16 u16PortOffset; ++ ++ HAL_HWI2C_SetPortRegOffset(1, &u16PortOffset); ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ CamOsTsemUp(&g_stSemaphore[1]); ++ return 0; ++}; ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_I2c2_Isr ++/// @brief \b Function \b Description: Isr of DMA tx done ++/// @param \b IntNum : Int number, void * dev_id ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static irqreturn_t HAL_HWI2C_DMA_WN_I2c2_Isr(int IntNum, void* dev_id) ++{ ++ U16 u16PortOffset; ++ ++ HAL_HWI2C_SetPortRegOffset(2, &u16PortOffset); ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ CamOsTsemUp(&g_stSemaphore[2]); ++ return 0; ++}; ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_SetMiuData ++/// @brief \b Function \b Description: Set MIIC WN DMA Miu data buf ++/// @param \b u16PortOffset: port offset, pmsg: i2c msg, u32cnt: msg cnt ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_WN_SetMiuData(U16 u16PortOffset, struct i2c_msg* pmsg, U32 u32cnt) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ U32 i; ++ struct i2c_msg* pCurmsg = pmsg; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ ++ ++ for(i = 0; i < u32cnt; i++) ++ { ++ pCurmsg = pmsg + i; ++ memcpy(pMiuData + (i * pCurmsg->len), pCurmsg->buf, pCurmsg->len); ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset, (pmsg->len *u32cnt)); ++ ++ return TRUE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_WaitDone ++/// @brief \b Function \b Description: trigger and wait DMA wn mode tx done ++/// @param \b u16PortOffset: port offset, u8ReadWrite : read or write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_WN_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U8 u8Port; ++ U32 u32Txfrcnt; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //set int en ++ HAL_HWI2C_DMA_SetINT(u16PortOffset, TRUE); ++ //issue write trigger ++ //HWI2C_HAL_ERR("[DMA]HAL_HWI2C_DMA_Trigger\n"); ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //CamOsTcondTimedWait ++ if (CAM_OS_TIMEOUT == CamOsTsemTimedDown(&g_stSemaphore[u8Port], 1000)){ ++ HWI2C_HAL_ERR("[DMA]: WN Wait ISR time out!\n"); ++ return FALSE; ++ } ++ //disable int ++ HAL_HWI2C_DMA_SetINT(u16PortOffset, FALSE); ++ //HWI2C_HAL_ERR("[DMA]: WN Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ u32Txfrcnt = HAL_HWI2C_DMA_GetTxfrCnt(u16PortOffset); ++ HWI2C_HAL_ERR("[DMA]: WN Transfer NACK!\n"); ++ HWI2C_HAL_ERR("[DMA]: WN TxfrCnt %d\n", u32Txfrcnt); ++ return FALSE; ++ } ++ ++ return FALSE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_WriteBytes ++/// @brief \b Function \b Description: DMA WN mode write bytes ++/// @param \b u16PortOffset: port offset, u16SlaveCfg: slave addr, pmsg: i2c_msg, u32cnt: msg cnt ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WN_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, struct i2c_msg* pmsg, U32 u32cnt) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(pmsg == NULL){ ++ HWI2C_HAL_ERR("[DMA_NW]: Null pointer pmsg!\n"); ++ return FALSE; ++ } ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set multi data to dram ++ if(HAL_HWI2C_DMA_WN_SetMiuData(u16PortOffset, pmsg, u32cnt)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_NW]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //set n number ++ HAL_HWI2C_DMA_SetGroupLen(u16PortOffset, pmsg->len); ++ //enable nwrite mode ++ HAL_HWI2C_EnWnmode(u16PortOffset, true); ++ //Set wait count ++ HAL_HWI2C_DMA_SetWaitCnt(u16PortOffset, 0x1FFF); ++ //trigger and wait ISR ++ if(HAL_HWI2C_DMA_WN_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE){ ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WN_WriteSeq ++/// @brief \b Function \b Description: DMA WN mode write seqs ++/// @param \b u16PortOffset: port offset, u16SlaveCfg: slave addr, pmsg: i2c_msg, num: total msg num ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WN_WriteSeq(U16 u16PortOffset, U16 u16SlaveCfg, void* pmsg, U32 num) ++{ ++ U16 u16nwritecnt[HAL_HWI2C_NWRITE_MAXNUM] = {0}; ++ U16 i = 1; ++ U16 u16index = 0; ++ U16 len; ++ struct i2c_msg* pi2cmsg = (struct i2c_msg*)pmsg; ++ ++ memset(u16nwritecnt, 0xFFFF, sizeof(u16nwritecnt)); ++ ++ if(num <= 0) ++ return FALSE; ++ ++ //first ++ len = pi2cmsg->len; ++ u16nwritecnt[u16index] = 1; ++ ++ while(i < num) ++ { ++ pi2cmsg++; ++ if(pi2cmsg->len == len){ ++ u16nwritecnt[u16index]++; ++ } ++ else{ ++ u16index++; ++ u16nwritecnt[u16index] = 1; ++ } ++ len = pi2cmsg->len; ++ i++; ++ } ++ //point to start addr ++ pi2cmsg = (struct i2c_msg*)pmsg; ++ //1.array 2.cnt = u16index + 1 ++ for( i = 0; i <= u16index; i++) ++ { ++ if(u16nwritecnt[i] == 0xFFFF){ ++ break; ++ } ++ ++ if(!HAL_HWI2C_DMA_WN_WriteBytes(u16PortOffset, u16SlaveCfg, pi2cmsg, u16nwritecnt[i])){ ++ return FALSE; ++ } ++ pi2cmsg+=u16nwritecnt[i]; ++ } ++ ++ return TRUE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_CheckAbility ++/// @brief \b Function \b Description: check function ability by etype ++/// @param \b etype: feature type, fp :function pointer of feature ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp) ++{ ++ //tmp disable wn dma write ++ #if 0 ++ switch (etype) ++ { ++ case E_HAL_HWI2C_FEATURE_NWRITE: ++ *fp = (mhal_i2c_feature_fp)HAL_HWI2C_DMA_WN_WriteSeq; //TODO ++ return TRUE; ++ break; ++ default: ++ return FALSE; ++ break; ++ } ++ #endif ++ return FALSE; ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IrqRequest ++/// @brief \b Function \b Description: request IRQ ++/// @param \b u32irq: irq num, u32group: port,pdev: dev ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev) ++{ ++ ++ switch(u32group) ++ { ++ case 0: ++ if (0 == CamOsIrqRequest(u32irq, (CamOsIrqHandler)HAL_HWI2C_DMA_WN_I2c0_Isr, "I2C0", pdev)){ ++ HWI2C_HAL_ERR("[I2C] i2c0 irq interrupt registered #%d\n", u32irq);} ++ else{ ++ HWI2C_HAL_ERR("[I2C] failed to request i2c0 irq #%d\n", u32irq);} ++ break; ++ case 1: ++ if (0 == CamOsIrqRequest(u32irq, (CamOsIrqHandler)HAL_HWI2C_DMA_WN_I2c1_Isr, "I2C1", pdev)){ ++ HWI2C_HAL_ERR("[I2C] i2c1 irq interrupt registered #%d\n", u32irq);} ++ else{ ++ HWI2C_HAL_ERR("[I2C] failed to request i2c1 irq #%d\n", u32irq);} ++ break; ++ case 2: ++ if (0 == CamOsIrqRequest(u32irq, (CamOsIrqHandler)HAL_HWI2C_DMA_WN_I2c2_Isr, "I2C2", pdev)){ ++ HWI2C_HAL_ERR("[I2C] i2c2 irq interrupt registered #%d\n", u32irq);} ++ else{ ++ HWI2C_HAL_ERR("[I2C] failed to request i2c2 irq #%d\n", u32irq);} ++ break; ++ default: ++ break; ++ } ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IrqFree ++/// @brief \b Function \b Description: free IRQ ++/// @param \b u32irq: irq num ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_IrqFree(U32 u32irq) ++{ ++ CamOsIrqFree(u32irq, NULL); ++} ++/* ++BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ //1.DMA rsest ++ //2.DMA MIU reset ++ //3.clear tx done ++ //4.set write mode ++ //5.trigger DMA ++ //6.wait ISR ,using CamOsTcondTimedWait ++ //7.if wait time out, check NACK reg ++ //8.tx done, return ++} ++ ++BOOL HAL_HWI2C_DMA_NwriteMode_WriteBytes(pmsg, num) ++{ ++ // 1.Check pmsg/num and split it to several continous parts ++ // |3bytes|3bytes|3bytes|4btyes|3bytes| ++ // ==> |3bytes|3bytes|3bytes| + |4btyes| + 3bytes| ++ // send 3 times nwrite mode by for loop ++ // 2.Set nwrite para and trigger ++ // (1.)SetTxfrStop ++ // (2.)Set Slave Addr ++ // (3.)Set miu addr ++ // (4.)Set data length and N number ++ // (5.)Enable nwrite mode ++ // (6.)Set wait count ++ // (7.)Trigger tx and DMA wait done by ISR ++} ++*/ ++ ++#endif +diff --git a/drivers/sstar/i2c/infinity6e/mhal_iic.h b/drivers/sstar/i2c/infinity6e/mhal_iic.h +new file mode 100755 +index 000000000000..492d23335c2e +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6e/mhal_iic.h +@@ -0,0 +1,297 @@ ++/* ++* mhal_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++//DMA N write ++#define HAL_HWI2C_NWRITE_MAXNUM 256 ++typedef void* (*mhal_i2c_feature_fp)(U16, U16, void*, U32); ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef enum _HAL_HWI2C_HW_FEATURE ++{ ++ E_HAL_HWI2C_FEATURE_NWRITE = 0, ++ E_HAL_HWI2C_FEATURE_MAX, ++}HAL_HWI2C_HW_FEATURE; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_CheckAbility(HAL_HWI2C_HW_FEATURE etype,mhal_i2c_feature_fp *fp); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqFree(U32 u32irq); ++_extern_HAL_IIC_ void HAL_HWI2C_IrqRequest(U32 u32irq, U32 u32group, void *pdev); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemInit(U8 u8Port); ++_extern_HAL_IIC_ void HAL_HWI2C_DMA_TsemDeinit(U8 u8Port); ++//_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WN_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, i2c_msg* pmsg, U32 u32cnt); ++ ++ ++#endif //_MHAL_HWI2C_H_ +diff --git a/drivers/sstar/i2c/infinity6e/mhal_iic_reg.h b/drivers/sstar/i2c/infinity6e/mhal_iic_reg.h +new file mode 100755 +index 000000000000..fd82d13e60ee +--- /dev/null ++++ b/drivers/sstar/i2c/infinity6e/mhal_iic_reg.h +@@ -0,0 +1,315 @@ ++/* ++* mhal_iic_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223000 //0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x103C00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6f*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_4 (__BIT2) ++ #define CHIP_MIIC0_PAD_5 (__BIT0|__BIT2) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6f*2)) ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT5) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6f*2+1)) ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT0) ++ #define CHIP_MIIC2_PAD_2 (__BIT1) ++ #define CHIP_MIIC2_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC2_PAD_4 (__BIT2) ++ #define CHIP_MIIC2_PAD_5 (__BIT0|__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x50*2)) ++ #define CHIP_MIIC3_PAD_0 (0) ++ #define CHIP_MIIC3_PAD_1 (__BIT0) ++ #define CHIP_MIIC3_PAD_2 (__BIT1) ++ #define CHIP_MIIC3_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC3_PAD_4 (__BIT2) ++ #define CHIP_MIIC3_PAD_5 (__BIT0|__BIT2) ++ #define CHIP_MIIC3_PAD_MSK (__BIT0|__BIT1|__BIT2) ++ ++#define CHIP_REG_PM_PAD_EXT_MODE1 (0x56*2) ++ #define CHIP_PAD_PM_I2CM_SCL (__BIT5) ++ #define CHIP_PAD_PM_I2CM_SDA (__BIT6) ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_RESERVE0 (HWI2C_REG_BASE+0x10*2) ++ #define _INT_CFG_CORE2DMA (__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++#define REG_HWI2C_DMA_RESERVED0 (HWI2C_REG_BASE+0x30*2) ++#define REG_HWI2C_DMA_GROUP_LEN (HWI2C_REG_BASE+0x32*2) ++#define REG_HWI2C_DMA_WNMODE_EN (HWI2C_REG_BASE+0x33*2) ++ #define _DMA_CTL_WNMODE_EN (__BIT0) ++#define REG_HWI2C_DMA_WN_WAITCNT (HWI2C_REG_BASE+0x34*2) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ +diff --git a/drivers/sstar/i2c/ms_iic.c b/drivers/sstar/i2c/ms_iic.c +new file mode 100755 +index 000000000000..86f2b189de95 +--- /dev/null ++++ b/drivers/sstar/i2c/ms_iic.c +@@ -0,0 +1,1782 @@ ++/* ++* ms_iic.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include "mst_devid.h" ++#include ++#include ++ ++#include "ms_iic.h" ++#include "mhal_iic_reg.h" ++#include "mhal_iic.h" ++#include "ms_platform.h" ++#include "cam_sysfs.h" ++#include "drv_camclk_Api.h" ++#define I2C_ACCESS_DUMMY_TIME 5//3 ++///////////////////////////////////////////&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//////////////////////////////////////////////// ++///////////////////////////////////////////&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//////////////////////////////////////////////// ++///////////////////////////////////////////&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//////////////////////////////////////////////// ++// Local defines & local structures ++//////////////////////////////////////////////////////////////////////////////// ++//define hwi2c ports ++#define HWI2C_PORTS HAL_HWI2C_PORTS ++#define HWI2C_PORT0 HAL_HWI2C_PORT0 ++#define HWI2C_PORT1 HAL_HWI2C_PORT1 ++#define HWI2C_PORT2 HAL_HWI2C_PORT2 ++#define HWI2C_PORT3 HAL_HWI2C_PORT3 ++#define HWI2C_STARTDLY 5 //us ++#define HWI2C_STOPDLY 5 //us ++//define mutex ++static DEFINE_MUTEX(i2cMutex); ++I2C_DMA HWI2C_DMA[HWI2C_PORTM]; ++ ++#define HWI2C_MUTEX_CREATE(_P_) //g_s32HWI2CMutex[_P_] = MsOS_CreateMutex(E_MSOS_FIFO, (char*)gu8HWI2CMutexName[_P_] , MSOS_PROCESS_SHARED) ++#define HWI2C_MUTEX_LOCK(_P_) //OS_OBTAIN_MUTEX(g_s32HWI2CMutex[_P_],MSOS_WAIT_FOREVER) ++#define HWI2C_MUTEX_UNLOCK(_P_) //OS_RELEASE_MUTEX(g_s32HWI2CMutex[_P_]) ++#define HWI2C_MUTEX_DELETE(_P_) //OS_DELETE_MUTEX(g_s32HWI2CMutex[_P_]) ++#define MsOS_DelayTaskUs(x) udelay(x) ++#define MS_DEBUG_MSG(x) x ++ ++#ifdef CONFIG_MS_PADMUX ++#include "mdrv_padmux.h" ++#include "mdrv_puse.h" ++#include "gpio.h" ++#endif ++ ++//static MS_S32 g_s32HWI2CMutex[HWI2C_PORTM] = {-1,-1,-1,-1}; ++//static char gu8HWI2CMutexName[HWI2C_PORTM][13] = {"HWI2CMUTEXP0","HWI2CMUTEXP1","HWI2CMUTEXP2","HWI2CMUTEXP3"}; ++ ++//#define EN_I2C_LOG ++#ifdef EN_I2C_LOG ++#define HWI2C_DBG_FUNC() if (_geDbgLv >= E_HWI2C_DBGLV_ALL) \ ++ {MS_DEBUG_MSG(printk("\t==== %s ====\n", __FUNCTION__);)} ++#define HWI2C_DBG_INFO(x, args...) if (_geDbgLv >= E_HWI2C_DBGLV_INFO ) \ ++ {MS_DEBUG_MSG(printk(x, ##args);)} ++#define HWI2C_DBG_ERR(x, args...) if (_geDbgLv >= E_HWI2C_DBGLV_ERR_ONLY) \ ++ {MS_DEBUG_MSG(printk(x, ##args);)} ++#else ++#define HWI2C_DBG_FUNC() //printk("\t########################## %s ################################\n", __FUNCTION__) ++#define HWI2C_DBG_INFO(x, args...) //printk(x, ##args) ++#define HWI2C_DBG_ERR(x, args...) printk(x, ##args) ++#endif ++ ++ ++//#define I2C_ACCESS_DUMMY_TIME 50 ++//////////////////////////////////////////////////////////////////////////////// ++// Local & Global Variables ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++struct mstar_i2c_dev { ++ struct device *dev; ++ struct i2c_adapter adapter; ++ struct clk *div_clk; ++ struct clk *fast_clk; ++ struct reset_control *rst; ++ void __iomem *base; ++ void __iomem *chipbase; ++ void __iomem *clkbase; ++ int cont_id; ++ bool irq_disabled; ++ int is_dvc; ++ struct completion msg_complete; ++ int msg_err; ++ u8 *msg_buf; ++ size_t msg_buf_remaining; ++ int msg_read; ++ u32 bus_clk_rate; ++ bool is_suspended; ++ int i2cgroup; ++ int i2cpadmux; ++ int i2c_speed; ++ int i2c_en_dma; ++}; ++typedef struct _i2c_dev_data{ ++ u32 i2cirq; ++ int i2cgroup; ++}i2c_dev_data; ++ ++ ++//typedef void* (*i2c_nwrite_fp)(void*); ++ ++static BOOL _gbInit = FALSE; ++ ++#ifdef EN_I2C_LOG ++static HWI2C_DbgLv _geDbgLv = E_HWI2C_DBGLV_INFO; //E_HWI2C_DBGLV_ERR_ONLY; ++#endif ++ ++static HWI2C_State _geState = E_HWI2C_IDLE; ++static U32 g_u32StartDelay = HWI2C_STARTDLY, g_u32StopDelay = HWI2C_STOPDLY; ++static HWI2C_ReadMode g_HWI2CReadMode[HWI2C_PORTS]; ++//static HWI2C_PORT g_HWI2CPort[HWI2C_PORTS]; ++static U16 g_u16DelayFactor[HWI2C_PORTS]; ++static BOOL g_bDMAEnable[HWI2C_PORTS]; ++#ifdef CONFIG_CAM_CLK ++void **pvhandler; ++#endif ++//static U8 g_HWI2CPortIdx = HWI2C_PORT0; ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDrv_HWI2C_Send_Byte HAL_HWI2C_Send_Byte ++#define _MDrv_HWI2C_Recv_Byte HAL_HWI2C_Recv_Byte ++ ++#if 0 ++static void _MDrv_HWI2C_DelayUs(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++BOOL MDrv_MMIO_GetBASE(U32 *u32Baseaddr, U32 *u32Basesize, U32 u32Module) ++{ ++ ++ return TRUE ; ++} ++#endif ++ ++ ++BOOL MDrv_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ return HAL_HWI2C_Send_Byte(u16PortOffset, u8Data); ++} ++ ++BOOL MDrv_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ return HAL_HWI2C_Recv_Byte(u16PortOffset, pData); ++} ++ ++ ++BOOL MDrv_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ return HAL_HWI2C_NoAck(u16PortOffset); ++} ++ ++ ++BOOL MDrv_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ return HAL_HWI2C_Reset(u16PortOffset, bReset); ++} ++ ++ ++BOOL _MDrv_HWI2C_GetPortRegOffset(U8 u8Port, U16 *pu16Offset) ++{ ++ HWI2C_DBG_FUNC(); ++ ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ return HAL_HWI2C_SetPortRegOffset(u8Port,pu16Offset); ++} ++ ++BOOL _MDrv_HWI2C_ReadBytes(U8 u8Port, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveID = LOW_BYTE(u16SlaveCfg); ++ U16 u16Offset = 0x00; ++ U16 u16Dummy = I2C_ACCESS_DUMMY_TIME; // loop dummy ++ BOOL bComplete = FALSE; ++ U32 uAddrCntBkp,uSizeBkp; ++ U8 *pRegAddrBkp,*pDataBkp; ++ ++ HWI2C_DBG_FUNC(); ++ ++ _geState = E_HWI2C_READ_DATA; ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //no meaning operation ++ if (!uSize) ++ { ++ // HWI2C_DBG_ERR("Read bytes error!\n"); ++ return FALSE; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ // HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ _geState = E_HWI2C_DMA_READ_DATA; ++ return HAL_HWI2C_DMA_ReadBytes(u16Offset, u16SlaveCfg, uAddrCnt, pRegAddr, uSize, pData); ++ } ++ ++ //start access routines ++ uAddrCntBkp = uAddrCnt; ++ pRegAddrBkp = pRegAddr; ++ uSizeBkp = uSize; ++ pDataBkp = pData; ++ ++ while (u16Dummy--) ++ { ++ if((g_HWI2CReadMode[u8Port]!=E_HWI2C_READ_MODE_DIRECT) && (uAddrCnt>0)&& (pRegAddr)) ++ { ++ HAL_HWI2C_Start(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StartDelay); ++ ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,HWI2C_SET_RW_BIT(FALSE, u8SlaveID))) ++ goto end; ++ ++ while(uAddrCnt--) ++ { ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,*pRegAddr)) ++ goto end; ++ pRegAddr++; ++ } ++ ++ if(g_HWI2CReadMode[u8Port]==E_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ { ++ HAL_HWI2C_Stop(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StopDelay); ++ } ++ else ++ { ++ HAL_HWI2C_Reset(u16Offset,TRUE); ++ HAL_HWI2C_Reset(u16Offset,FALSE); ++ } ++ } ++ ++ //Very important to add delay to support all clock speeds ++ //Strongly recommend that do not remove this delay routine ++ HAL_HWI2C_ExtraDelay(g_u16DelayFactor[u8Port]); ++ HAL_HWI2C_Start(u16Offset); ++ ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StartDelay); ++ ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,HWI2C_SET_RW_BIT(TRUE, u8SlaveID))) ++ goto end; ++ ++ while(uSize) ++ { ++ /////////////////////////////////// ++ // ++ // must set ACK/NAK before read ready ++ // ++ uSize--; ++ if (uSize==0) ++ HAL_HWI2C_NoAck(u16Offset); ++ if (_MDrv_HWI2C_Recv_Byte(u16Offset,pData)==FALSE) ++ goto end; ++ pData++; ++ } ++ bComplete = TRUE; ++ ++ end: ++ HAL_HWI2C_Stop(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StopDelay); ++ if(u16Dummy&&(bComplete==FALSE)) ++ { ++ uAddrCnt = uAddrCntBkp; ++ pRegAddr = pRegAddrBkp; ++ uSize = uSizeBkp; ++ pData = pDataBkp; ++ continue; ++ } ++ break; ++ } ++ _geState = E_HWI2C_IDLE; ++ HAL_HWI2C_Reset(u16Offset,TRUE); ++ HAL_HWI2C_Reset(u16Offset,FALSE); ++ ++ return bComplete; ++} ++ ++BOOL _MDrv_HWI2C_WriteBytes(U8 u8Port, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveID = LOW_BYTE(u16SlaveCfg); ++ U16 u16Offset = 0x00; ++ ++ U16 u16Dummy = I2C_ACCESS_DUMMY_TIME; // loop dummy ++ BOOL bComplete = FALSE; ++ U32 uAddrCntBkp,uSizeBkp; ++ U8 *pRegAddrBkp,*pDataBkp; ++ ++ HWI2C_DBG_FUNC(); ++ ++ _geState = E_HWI2C_WRITE_DATA; ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //no meaning operation ++ if (!uSize) ++ { ++ // HWI2C_DBG_ERR("Write bytes error!\n"); ++ return FALSE; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ // HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ _geState = E_HWI2C_DMA_WRITE_DATA; ++ return HAL_HWI2C_DMA_WriteBytes(u16Offset, u16SlaveCfg, uAddrCnt, pRegAddr, uSize, pData); ++ } ++ ++ //start access routines ++ uAddrCntBkp = uAddrCnt; ++ pRegAddrBkp = pRegAddr; ++ uSizeBkp = uSize; ++ pDataBkp = pData; ++ while(u16Dummy--) ++ { ++ HAL_HWI2C_Start(u16Offset); ++ MsOS_DelayTaskUs(g_u32StartDelay); ++ ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,HWI2C_SET_RW_BIT(FALSE, u8SlaveID))) ++ {HWI2C_DBG_ERR("HWI2C_SET_RW_BIT error!\n"); ++ goto end; ++ } ++ while(uAddrCnt) ++ { ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset, *pRegAddr)) ++ {HWI2C_DBG_ERR("pRegAddr error!\n"); ++ goto end; ++ } ++ uAddrCnt--; ++ pRegAddr++; ++ } ++ ++ while(uSize) ++ { ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset, *pData)) ++ {HWI2C_DBG_ERR("pData error!\n"); ++ goto end; ++ } ++ uSize--; ++ pData++; ++ } ++ bComplete = TRUE; ++ ++ end: ++ HAL_HWI2C_Stop(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StopDelay); ++ if(u16Dummy&&(bComplete==FALSE)) ++ { ++ uAddrCnt = uAddrCntBkp; ++ pRegAddr = pRegAddrBkp; ++ uSize = uSizeBkp; ++ pData = pDataBkp; ++ continue; ++ } ++ break; ++ } ++ _geState = E_HWI2C_IDLE; ++ HAL_HWI2C_Reset(u16Offset,TRUE); ++ HAL_HWI2C_Reset(u16Offset,FALSE); ++ return bComplete; ++} ++ ++#if defined(CONFIG_MS_PADMUX) ++static int _MDrv_HWI2C_IsPadSet(HWI2C_PORT ePort) ++{ ++ // important: need to modify if more MDRV_PUSE_I2C? defined ++ if(ePort >= E_HWI2C_PORT_0 && ePort <= E_HWI2C_PORT0_7) ++ return (PAD_UNKNOWN == mdrv_padmux_getpad(MDRV_PUSE_I2C0_SCL))?FALSE:TRUE; ++ else if(ePort >= E_HWI2C_PORT_1 && ePort <= E_HWI2C_PORT1_7) ++ return (PAD_UNKNOWN == mdrv_padmux_getpad(MDRV_PUSE_I2C1_SCL))?FALSE:TRUE; ++ else if(ePort >= E_HWI2C_PORT_2 && ePort <= E_HWI2C_PORT2_7) ++ return (PAD_UNKNOWN == mdrv_padmux_getpad(MDRV_PUSE_I2C2_SCL))?FALSE:TRUE; ++ else ++ return FALSE; ++} ++#endif ++ ++static BOOL _MDrv_HWI2C_SelectPort(HWI2C_PORT ePort) ++{ ++ U16 u16Offset = 0x00; ++ U8 u8Port = 0x00; ++ BOOL bRet=TRUE; ++ ++ HWI2C_DBG_FUNC(); ++ ++ //(1) Get port index by port number ++ if(!HAL_HWI2C_GetPortIdxByPort((HAL_HWI2C_PORT)ePort,&u8Port)) ++ return FALSE; ++ ++ //(2) Set pad mux for port number ++#if defined(CONFIG_MS_PADMUX) ++ if (0 == mdrv_padmux_active() || ++ FALSE == _MDrv_HWI2C_IsPadSet(ePort) ) ++#endif ++ { ++ bRet &= HAL_HWI2C_SelectPort((HAL_HWI2C_PORT)ePort); ++ } ++ ++ //(3) configure port register offset ==> important ++ bRet &= _MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset); ++ ++ //(4) master init ++ bRet &= HAL_HWI2C_Master_Enable(u16Offset); ++ ++ return bRet; ++} ++ ++static BOOL _MDrv_HWI2C_SetClk(U8 u8Port, HWI2C_CLKSEL eClk) ++{ ++ U16 u16Offset = 0x00; ++ ++ HWI2C_DBG_FUNC(); ++ HWI2C_DBG_INFO("Port%d clk: %u\n", u8Port, eClk); ++ ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //check support clock speed ++ if (eClk >= E_HWI2C_NOSUP) ++ { ++ // HWI2C_DBG_ERR("Clock [%u] is not supported!\n",eClk); ++ return FALSE; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ // HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ g_u16DelayFactor[u8Port] = (U16)(1<<(eClk)); ++ HWI2C_DBG_INFO("Port%d clk: %u offset:%d\n", u8Port, eClk, u16Offset); ++ ++ return HAL_HWI2C_SetClk(u16Offset,(HAL_HWI2C_CLKSEL)eClk); ++} ++ ++static BOOL _MDrv_HWI2C_SetReadMode(U8 u8Port, HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_DBG_FUNC(); ++ HWI2C_DBG_INFO("Port%d Readmode: %u\n", u8Port, eReadMode); ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ if(eReadMode>=E_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ g_HWI2CReadMode[u8Port] = eReadMode; ++ return TRUE; ++} ++ ++static BOOL _MDrv_HWI2C_InitPort(HWI2C_UnitCfg *psCfg) ++{ ++ U8 u8PortIdx = 0, u8Port = 0; ++ U16 u16Offset = 0x00; ++ BOOL bRet = TRUE; ++ HWI2C_PortCfg stPortCfg; ++ ++ HWI2C_DBG_FUNC(); ++ ++ //(1) set default value for port variables ++ for(u8PortIdx=0; u8PortIdx < HWI2C_PORTS; u8PortIdx++) ++ { ++ stPortCfg = psCfg->sCfgPort[u8PortIdx]; ++ if(stPortCfg.bEnable) ++ { ++ if(HAL_HWI2C_GetPortIdxByPort(stPortCfg.ePort,&u8Port) && _MDrv_HWI2C_SelectPort(stPortCfg.ePort)) ++ { ++ //set clock speed ++ bRet &= _MDrv_HWI2C_SetClk(u8Port, stPortCfg.eSpeed); ++ //set read mode ++ bRet &= _MDrv_HWI2C_SetReadMode(u8Port, stPortCfg.eReadMode); ++ //get port index ++ bRet &= _MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset); ++ //master init ++ bRet &= HAL_HWI2C_Master_Enable(u16Offset); ++ //dma init ++ bRet &= HAL_HWI2C_DMA_Init(u16Offset,(HAL_HWI2C_PortCfg*)&stPortCfg); ++ g_bDMAEnable[u8Port] = stPortCfg.bDmaEnable; ++ //dump port information ++ pr_debug("Port:%u Index=%u\n",u8Port,stPortCfg.ePort); ++ pr_debug("Enable=%u\n",stPortCfg.bEnable); ++ pr_debug("DmaReadMode:%u\n",stPortCfg.eReadMode); ++ pr_debug("Speed:%u\n",stPortCfg.eSpeed); ++ pr_debug("DmaEnable:%u\n",stPortCfg.bDmaEnable); ++ pr_debug("DmaAddrMode:%u\n",stPortCfg.eDmaAddrMode); ++ pr_debug("DmaMiuCh:%u\n",stPortCfg.eDmaMiuCh); ++ pr_debug("DmaMiuPri:%u\n",stPortCfg.eDmaMiuPri); ++ pr_debug("DmaPhyAddr:%x\n",stPortCfg.u32DmaPhyAddr); ++ } ++ } ++ } ++ ++ //(2) check initialized port : override above port configuration ++ if(HAL_HWI2C_GetPortIdxByPort(psCfg->ePort,&u8Port) && _MDrv_HWI2C_SelectPort(psCfg->ePort)) ++ { ++ //set clock speed ++ bRet &=_MDrv_HWI2C_SetClk(u8Port,psCfg->eSpeed); ++ //set read mode ++ bRet &=_MDrv_HWI2C_SetReadMode(u8Port,psCfg->eReadMode); ++ //get port index ++ //configure port register offset ==> important ++ bRet &= _MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset); ++ //master init ++ bRet &= HAL_HWI2C_Master_Enable(u16Offset); ++ } ++ ++ //(3) dump allocated port information ++ /*for(u8PortIdx=0; u8PortIdx < HWI2C_PORTS; u8PortIdx++) ++ { ++ HWI2C_DBG_INFO("HWI2C Allocated Port[%d] = 0x%02X\n",u8PortIdx,g_HWI2CPort[u8PortIdx]); ++ }*/ ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_Init ++/// @brief \b Function \b Description: Init HWI2C driver ++/// @param psCfg \b IN: hw I2C config ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_Init(HWI2C_UnitCfg *psCfg) ++{ ++ BOOL bRet = TRUE; ++ U8 u8Port=0; ++ ++ HWI2C_DBG_FUNC(); ++ ++ HAL_HWI2C_SetIOMapBase(psCfg->eGroup,psCfg->eBaseAddr,psCfg->eChipAddr,psCfg->eClkAddr); ++ ++ //(2) Initialize pad mux and basic settings ++ pr_debug("Pinreg:%x bit:%u enable:%u speed:%u\n",psCfg->sI2CPin.u32Reg, psCfg->sI2CPin.u8BitPos, psCfg->sI2CPin.bEnable,psCfg->eSpeed); ++ bRet &= HAL_HWI2C_Init_Chip(); ++ //(3) Initialize all port ++ bRet &= _MDrv_HWI2C_InitPort(psCfg); ++ //(4) Check final result ++ if (!bRet) ++ { ++ HWI2C_DBG_ERR("I2C init fail!\n"); ++ } ++ ++ //(5) Extra procedure to do after initialization ++ HAL_HWI2C_Init_ExtraProc(); ++ ++ g_u32StartDelay = HWI2C_STARTDLY; ++ g_u32StopDelay = HWI2C_STOPDLY; ++ pr_debug("START default delay %d(us)\n",(int)g_u32StartDelay); ++ pr_debug("STOP default delay %d(us)\n",(int)g_u32StopDelay); ++ _gbInit = TRUE; ++ ++ pr_debug("HWI2C_MUTEX_CREATE!\n"); ++ for(u8Port=0;u8Port<(U8)HWI2C_PORTS;u8Port++) ++ { ++ HWI2C_MUTEX_CREATE(u8Port); ++ } ++ pr_debug("HWI2C(%d): initialized\n", psCfg->eGroup); ++ return bRet; ++} ++ ++void MDrv_HW_IIC_Init(void *base,void *chipbase,int i2cgroup,void *clkbase, int i2cpadmux, int i2cspeed, int i2c_enDma) ++{ ++ HWI2C_UnitCfg pHwbuscfg[1]; ++ U8 j; ++ ++ memset(pHwbuscfg, 0, sizeof(HWI2C_UnitCfg)); ++ ++ HWI2C_DMA[i2cgroup].i2c_virt_addr = dma_alloc_coherent(NULL, 4096, &HWI2C_DMA[i2cgroup].i2c_dma_addr, GFP_KERNEL); ++ //We only initialze sCfgPort[0] ++ for(j = 0 ; j < 1 ; j++) ++ { ++ pHwbuscfg[0].sCfgPort[j].bEnable = TRUE; ++ //use default pad mode 1 ++ if(i2cgroup==0) ++ { ++ if(i2cpadmux == 0) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_0; ++ else if(i2cpadmux == 1) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_1; ++ else if(i2cpadmux == 2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_2; ++ else if(i2cpadmux == 3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_3; ++ else if(i2cpadmux == 4) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_4; ++ else if(i2cpadmux == 5) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_5; ++ }else if(i2cgroup==1) { ++ if(i2cpadmux == 0) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_0; ++ else if(i2cpadmux == 1) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_1; ++ else if(i2cpadmux == 2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_2; ++ else if(i2cpadmux == 3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_3; ++ else if(i2cpadmux == 4) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_4; ++ else if(i2cpadmux == 5) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_5; ++ }else if(i2cgroup==2) { ++ if(i2cpadmux == 0) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_0; ++ else if(i2cpadmux == 1) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_1; ++ else if(i2cpadmux == 2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_2; ++ else if(i2cpadmux == 3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_3; ++ else if(i2cpadmux == 4) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_4; ++ else if(i2cpadmux == 5) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_5; ++ } ++ else if(i2cgroup==3) { ++ if(i2cpadmux == 0) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_0; ++ else if(i2cpadmux == 1) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_1; ++ else if(i2cpadmux == 2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_2; ++ else if(i2cpadmux == 3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_3; ++ else if(i2cpadmux == 4) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_4; ++ else if(i2cpadmux == 5) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_5; ++ } ++ pHwbuscfg[0].sCfgPort[j].eSpeed= i2cspeed; //E_HWI2C_NORMAL; //E_HAL_HWI2C_CLKSEL_VSLOW;//pIIC_Param->u8ClockIIC;// ++ pHwbuscfg[0].sCfgPort[j].eReadMode = E_HWI2C_READ_MODE_DIRECT;//pIIC_Param->u8IICReadMode;// ++ if (i2c_enDma == -1) ++ { ++ if(i2cgroup==0) ++ pHwbuscfg[0].sCfgPort[j].bDmaEnable = FALSE; //Use default setting ++ else ++ pHwbuscfg[0].sCfgPort[j].bDmaEnable = TRUE; //Use default setting */ ++ } ++ else ++ { ++ pHwbuscfg[0].sCfgPort[j].bDmaEnable = i2c_enDma; ++ } ++ pHwbuscfg[0].sCfgPort[j].eDmaAddrMode = E_HWI2C_DMA_ADDR_NORMAL; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].eDmaMiuPri = E_HWI2C_DMA_PRI_LOW; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].eDmaMiuCh = E_HWI2C_DMA_MIU_CH0; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].u32DmaPhyAddr = HWI2C_DMA[i2cgroup].i2c_dma_addr; //Use default setting ++ j++; ++ } ++ ++ pHwbuscfg[0].sI2CPin.bEnable = FALSE; ++ pHwbuscfg[0].sI2CPin.u8BitPos = 0; ++ pHwbuscfg[0].sI2CPin.u32Reg = 0; ++ pHwbuscfg[0].eSpeed = i2cspeed; //E_HWI2C_NORMAL; //E_HAL_HWI2C_CLKSEL_VSLOW;//pIIC_Param->u8ClockIIC;// ++ pHwbuscfg[0].ePort = pHwbuscfg[0].sCfgPort[0].ePort; /// port ++ pHwbuscfg[0].eReadMode = E_HWI2C_READ_MODE_DIRECT; //pIIC_Param->u8IICReadMode;// ++ pHwbuscfg[0].eBaseAddr=(U32)base; ++ pHwbuscfg[0].eChipAddr=(U32)chipbase; ++ pHwbuscfg[0].eClkAddr=(U32)clkbase; ++ pHwbuscfg[0].eGroup=i2cgroup; ++ ++ MDrv_HWI2C_Init(&pHwbuscfg[0]); ++} ++EXPORT_SYMBOL(MDrv_HW_IIC_Init); ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HW_IIC_DeInit ++/// @brief \b Function \b Description: de init iic ++//////////////////////////////////////////////////////////////////////////////// ++void MDrv_HW_IIC_DeInit(int i2cgroup) ++{ ++ //printk( "[%s] dma_free_coherent : %d\n", __func__, i2cgroup); ++ dma_free_coherent(NULL, 4096, HWI2C_DMA[i2cgroup].i2c_virt_addr, HWI2C_DMA[i2cgroup].i2c_dma_addr); ++} ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_Start ++/// @brief \b Function \b Description: send start bit ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_Start(U16 u16PortOffset) ++{ ++ HWI2C_DBG_FUNC(); ++ return HAL_HWI2C_Start(u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_Stop ++/// @brief \b Function \b Description: send stop bit ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_Stop(U16 u16PortOffset) ++{ ++ HWI2C_DBG_FUNC(); ++ return HAL_HWI2C_Stop(u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_GetPortIndex ++/// @brief \b Function \b Description: Get port index from port number ++/// @param ePort \b IN: port number ++/// @param ePort \b OUT: pointer to port index ++/// @return \b U8: Port Index ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_GetPortIndex(HWI2C_PORT ePort, U8* pu8Port) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_DBG_FUNC(); ++ ++ //(1) Get port index by port number ++ bRet &= HAL_HWI2C_GetPortIdxByPort((HAL_HWI2C_PORT)ePort, pu8Port); ++ HWI2C_DBG_INFO("ePort:0x%02X, u8Port:0x%02X\n",(U8)ePort,(U8)*pu8Port); ++ ++ return bRet; ++} ++ ++BOOL MDrv_HWI2C_CheckAbility(HWI2C_DMA_HW_FEATURE etype,ms_i2c_feature_fp *fp) ++{ ++ if(etype >= E_HWI2C_FEATURE_MAX){ ++ HWI2C_DBG_ERR("etype invalid %d\n", etype); ++ return FALSE; ++ } ++ return HAL_HWI2C_CheckAbility(etype, fp); ++} ++ ++//################### ++// ++// Multi-Port Support: Port 0 ++// ++//################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_SelectPort ++/// @brief \b Function \b Description: Decide port index and pad mux for port number ++/// @param ePort \b IN: port number ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_SelectPort(HWI2C_PORT ePort) ++{ ++ HWI2C_DBG_FUNC(); ++ if(ePort >= E_HWI2C_PORT_NOSUP) ++ return FALSE; ++ return _MDrv_HWI2C_SelectPort(ePort); ++} ++#if 0 ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_SetClk ++/// @brief \b Function \b Description: Set HW I2C clock ++/// @param eClk \b IN: clock rate ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_SetClk(HWI2C_CLKSEL eClk) ++{ ++ HWI2C_DBG_FUNC(); ++ return _MDrv_HWI2C_SetClk(g_HWI2CPortIdx, eClk); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_SetReadMode ++/// @brief \b Function \b Description: Set HW I2C Read Mode ++/// @param eClk \b IN: ReadMode ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_SetReadMode(HWI2C_ReadMode eReadMode) ++{ ++ return _MDrv_HWI2C_SetReadMode(g_HWI2CPortIdx, eReadMode); ++} ++#endif ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 byte data ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param u8RegAddr \b IN: target register address ++/// @param pData \b Out: read 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_ReadByte(U16 u16SlaveCfg, U8 u8RegAddr, U8 *pData) ++{ ++ HWI2C_DBG_FUNC(); ++ return MDrv_HWI2C_ReadBytes(u16SlaveCfg, 1, &u8RegAddr, 1, pData); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_ReadByte ++/// @brief \b Function \b Description: write 1 byte data ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param u8RegAddr \b IN: target register address ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_WriteByte(U16 u16SlaveCfg, U8 u8RegAddr, U8 u8Data) ++{ ++ HWI2C_DBG_FUNC(); ++ return MDrv_HWI2C_WriteBytes(u16SlaveCfg, 1, &u8RegAddr, 1, &u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_WriteBytes ++/// @brief \b Function \b Description: Init HWI2C driver ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param uAddrCnt \b IN: register address count ++/// @param pRegAddr \b IN: pointer to targert register address ++/// @param uSize \b IN: data length ++/// @param pData \b IN: data array ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_WriteBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ BOOL bRet; ++ U8 u8Port; ++ ++ u8Port = HIGH_BYTE(u16SlaveCfg); ++ //u8Port = g_HWI2CPortIdx; ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //HWI2C_MUTEX_LOCK(u8Port); ++ //mutex_lock(&i2cMutex); ++ bRet = _MDrv_HWI2C_WriteBytes(u8Port,u16SlaveCfg,uAddrCnt,pRegAddr,uSize,pData); ++ //HWI2C_MUTEX_UNLOCK(u8Port); ++ //mutex_unlock(&i2cMutex); ++ return bRet; ++} ++EXPORT_SYMBOL(MDrv_HWI2C_WriteBytes); ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_ReadBytes ++/// @brief \b Function \b Description: Init HWI2C driver ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param uAddrCnt \b IN: register address count ++/// @param pRegAddr \b IN: pointer to targert register address ++/// @param uSize \b IN: data length ++/// @param pData \b Out: read data aray ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_ReadBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ BOOL bRet; ++ U8 u8Port; ++ ++ u8Port = HIGH_BYTE(u16SlaveCfg); ++ //u8Port = g_HWI2CPortIdx; ++ if(u8Port>=HWI2C_PORTS) ++ { ++ // HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //HWI2C_MUTEX_LOCK(u8Port); ++ //mutex_lock(&i2cMutex); ++ bRet = _MDrv_HWI2C_ReadBytes(u8Port,u16SlaveCfg,uAddrCnt,pRegAddr,uSize,pData); ++ //HWI2C_MUTEX_UNLOCK(u8Port); ++ //mutex_unlock(&i2cMutex); ++ return bRet; ++} ++EXPORT_SYMBOL(MDrv_HWI2C_ReadBytes); ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_xfer_read +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function is called by ms_i2c_xfer, ++| used to read data from i2c bus ++| 1. send start ++| 2. send address + R (read bit), and wait ack ++| 3. just set start_byte_read, ++| loop ++| 4. wait interrupt is arised, then clear interrupt and read byte in ++| 5. Auto generate NACK by IP, ++| 6. the master does not acknowledge the final byte it receives. ++| This tells the slave that its transmission is done ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pmsg | x | | pass in the slave id (addr) and R/W flag ++|--------------------+---+---+------------------------------------------------- ++| pbuf | x | | the message buffer, the buffer used to fill ++| | | | data readed ++|--------------------+---+---+------------------------------------------------- ++| length | x | | the byte to be readed from slave +++------------------------------------------------------------------------------ ++*/ ++char errBuf[4096]; ++char *perrBuf; ++ ++static int ++ms_i2c_xfer_read(u8 u8Port, struct i2c_msg *pmsg, u8 *pbuf, int length) ++{ ++ BOOL ret = FALSE; ++ u32 u32i = 0; ++ U16 u16Offset = 0x00; ++ ++ if (NULL == pmsg) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_read: pmsg is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ if (NULL == pbuf) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_read: pbuf is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ // HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ //pr_err("I2C read DMA: port = %#x\n", u8Port); ++ ret = MDrv_HWI2C_ReadBytes((u8Port<< 8)|(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)), 0, pbuf, length, pbuf); ++ if(ret==FALSE) ++ { ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_read: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ return -ETIMEDOUT; ++ } else { ++ return 0; ++ } ++ } ++ /* ***** 1. Send start bit ***** */ ++ if(!MDrv_HWI2C_Start(u16Offset)) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_read: Send Start error \r\n"); ++ return -ETIMEDOUT; ++ ++ } ++ // Delay for 1 SCL cycle 10us -> 4000T ++ udelay(2); ++ //LOOP_DELAY(8000); //20us ++ ++ /* ***** 2. Send slave id + read bit ***** */ ++ if (!MDrv_HWI2C_Send_Byte(u16Offset, ((pmsg->addr & I2C_BYTE_MASK) << 1) | ++ ((pmsg->flags & I2C_M_RD) ? 1 : 0))) ++ { ++ ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_read: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ ++ return -ETIMEDOUT; ++ } ++ udelay(1); ++ ++ /* Read data */ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ /* ***** 6. Read byte data from slave ***** */ ++ if ((length-1) == u32i) ++ { ++ MDrv_HWI2C_NoAck(u16Offset); ++ } ++ ret = MDrv_HWI2C_Recv_Byte(u16Offset, pbuf); ++ pbuf++; ++ } ++ ++ return 0; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_xfer_write +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function is called by ms_i2c_xfer ++| used to write data to i2c bus the procedure is as following ++ ++| 1. send start ++| 2. send address, and wait ack and clear interrupt in wait_ack() ++| loop ++| 3. send byte ++| 4. wait interrupt is arised, then clear interrupt ++| and check if recieve ACK ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pmsg | x | | pass in the slave id (addr) and R/W flag ++|--------------------+---+---+------------------------------------------------- ++| pbuf | x | | the message buffer, the buffer used to fill ++| | | | data readed ++|--------------------+---+---+------------------------------------------------- ++| length | x | | the byte to be writen from slave +++------------------------------------------------------------------------------ ++*/ ++static int ++ms_i2c_xfer_write(u8 u8Port, struct i2c_msg *pmsg, u8 *pbuf, int length) ++{ ++ u32 u32i = 0; ++ U16 u16Offset = 0x00; ++ int ret = FALSE; ++ ++ if (NULL == pmsg) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_write: pmsg is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ if (NULL == pbuf) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_write: pbuf is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ // HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ //pr_err("I2C write DMA: port = %#x\n", u8Port); ++ ret = MDrv_HWI2C_WriteBytes((u8Port<< 8)|(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)), 0, pbuf, length, pbuf); ++ if(ret==FALSE) ++ { ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_write: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ return -ETIMEDOUT; ++ }else{ ++ return 0; ++ } ++ } ++ ++ ++ /* ***** 1. Send start bit ***** */ ++ if(!MDrv_HWI2C_Start(u16Offset)) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_write: Send Start error \r\n"); ++ return -ETIMEDOUT; ++ } ++ // Delay for 1 SCL cycle 10us -> 4000T ++ //LOOP_DELAY(8000); //20us ++ udelay(2); ++ ++ /* ***** 2. Send slave id + read bit ***** */ ++ if (!MDrv_HWI2C_Send_Byte(u16Offset, ((pmsg->addr & I2C_BYTE_MASK) << 1) | ++ ((pmsg->flags & I2C_M_RD) ? 1 : 0))) ++ { ++ ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_write: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ return -ETIMEDOUT; ++ } ++ ++ /* ***** 3. Send register address and data to write ***** */ ++ /* we send register is first buffer */ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ /* ***** 4. Write high byte data to slave ***** */ ++ if(MDrv_HWI2C_Send_Byte(u16Offset, *pbuf)) ++ { ++ pbuf++; ++ } ++ else ++ { ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_write: Slave data NAK, Addr: %#x, Data: %#x \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),*pbuf); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return ret; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_xfer +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function will be called by i2c-core.c i2c-transfer() ++| i2c_master_send(), and i2c_master_recv() ++| We implement the I2C communication protocol here ++| Generic i2c master transfer entrypoint. ++| ++| RETURN : When the operation is success, it return the number of message ++| requrested. Negative number when error occurs. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| padap | x | | the adaptor which the communication will be ++| | | | procceed ++|--------------------+---+---+------------------------------------------------- ++| pmsg | x | | the message buffer, the buffer with message to ++| | | | be sent or used to fill data readed ++|--------------------+---+---+------------------------------------------------- ++| num | x | | number of message to be transfer +++------------------------------------------------------------------------------ ++*/ ++//static int ++int ++ms_i2c_xfer(struct i2c_adapter *padap, struct i2c_msg *pmsg, int num) ++{ ++ int i, err; ++ U16 u16Offset = 0x00; ++ BOOL bSendStop = 1; ++ ms_i2c_feature_fp ms_i2c_nwrite_fp; ++ struct i2c_msg *ptmpmsg = pmsg; ++ BOOL bDoRead = 0; ++ ++ HWI2C_DBG_INFO("ms_i2c_xfer: processing %d messages:\n", num); ++ ++ i = 0; ++ err = 0; ++ ++ if (NULL == padap) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer: adap is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ if (NULL == pmsg) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer: pmsg is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(padap->nr,&u16Offset)) ++ { ++ // HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ mutex_lock(&i2cMutex); ++ MDrv_HWI2C_Reset(u16Offset,TRUE); ++ udelay(1); ++ MDrv_HWI2C_Reset(u16Offset,FALSE); ++ udelay(1); ++ ++ //check read cmd ++ for(i = 0; i < num; i++) ++ { ++ ++ if(ptmpmsg->len && ptmpmsg->buf){ ++ if(ptmpmsg->flags & I2C_M_RD){ ++ bDoRead = 1; ++ break; ++ } ++ } ++ ptmpmsg++; ++ } ++ //query nwrite mode ability and proc nwrite ++ if(MDrv_HWI2C_CheckAbility(E_HWI2C_FEATURE_NWRITE, &ms_i2c_nwrite_fp) && !bDoRead) ++ { ++ if(ms_i2c_nwrite_fp == NULL){ ++ return FALSE; ++ } ++ ++ //HWI2C_DBG_ERR("ms_i2c_nwrite_fp num %d\n", num); ++ ms_i2c_nwrite_fp(u16Offset, ((pmsg->addr & I2C_BYTE_MASK) << 1), pmsg, num); ++ } ++ else{ ++/* in i2c-master_send or recv, the num is always 1, */ ++/* but use i2c_transfer() can set multiple message */ ++ ++ for (i = 0; i < num; i++) ++ { ++#if 0 ++ printk(KERN_INFO " #%d: %sing %d byte%s %s 0x%02x\n", i, ++ pmsg->flags & I2C_M_RD ? "read" : "writ", ++ pmsg->len, pmsg->len > 1 ? "s" : "", ++ pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr); ++#endif ++ /* do Read/Write */ ++ if (pmsg->len && pmsg->buf) /* sanity check */ ++ { ++ bSendStop = (pmsg->flags & I2C_CUST_M_NOSTOP) ? 0 : 1; ++ ++ if (pmsg->flags & I2C_M_RD) ++ err = ms_i2c_xfer_read(padap->nr, pmsg, pmsg->buf, pmsg->len); ++ else ++ err = ms_i2c_xfer_write(padap->nr, pmsg, pmsg->buf, pmsg->len); ++ ++ //MDrv_HWI2C_Stop(u16Offset); ++ ++ if (err) ++ { ++ mutex_unlock(&i2cMutex); ++ return err; ++ } ++ } ++ pmsg++; /* next message */ ++ } ++ } ++ /* ***** 6. Send stop bit ***** */ ++ /* finish the read/write, then issues the stop condition (P). ++ * for repeat start, diposit stop, two start and one stop only ++ */ ++ ++ if(bSendStop) ++ { ++ MDrv_HWI2C_Stop(u16Offset); ++ } ++ ++ mutex_unlock(&i2cMutex); ++ return i; ++} ++EXPORT_SYMBOL(ms_i2c_xfer); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_func +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function is returned list of supported functionality. ++| ++| RETURN : return list of supported functionality ++| ++| Variable : no variable +++------------------------------------------------------------------------------ ++*/ ++static u32 ms_i2c_func(struct i2c_adapter *padapter) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; ++} ++ ++/* implement the i2c transfer function in algorithm structure */ ++static struct i2c_algorithm sg_ms_i2c_algorithm = ++{ ++ .master_xfer = ms_i2c_xfer, ++ .functionality = ms_i2c_func, ++}; ++ ++/* Match table for of_platform binding */ ++static const struct of_device_id mstar_i2c_of_match[] = { ++ { .compatible = "sstar,i2c", 0}, ++ {}, ++}; ++ ++static int mstar_i2c_probe(struct platform_device *pdev) ++{ ++ struct mstar_i2c_dev *i2c_dev; ++ struct resource *res; ++ void __iomem *base; ++ void __iomem *chipbase; ++ void __iomem *clkbase; ++ struct device_node *node = pdev->dev.of_node; ++ int ret = 0; ++ int i2cgroup = 0; ++ int i2cpadmux = 0; ++ int i2c_speed = E_HWI2C_NORMAL; ++ int i2c_en_dma = -1; ++ int num_parents, i; ++//#if 1 ++#ifndef CONFIG_CAM_CLK ++ struct clk **iic_clks; ++#else ++ int *iic_clks; ++ CAMCLK_Set_Attribute stSetCfg; ++#endif ++ i2c_dev_data *data = NULL; ++ ++ data = kzalloc(sizeof(i2c_dev_data), GFP_KERNEL); ++ if(!data){ ++ ret = -ENOMEM; ++ goto out; ++ } ++#ifndef CONFIG_CAM_CLK ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, num_parents); ++ ret = -ENOENT ; ++ goto out; ++ } ++ ++ iic_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(!iic_clks){ ++ ret = -ENOMEM; ++ goto out; ++ } ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(iic_clks[i])) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ ret = -ENOENT; ++ } ++ else ++ { ++ clk_prepare_enable(iic_clks[i]); ++ if(i == 0) ++ clk_set_rate(iic_clks[i], 12000000); ++ clk_put(iic_clks[i]); ++ } ++ } ++ kfree(iic_clks); ++ if(ret){ ++ goto out; ++ } ++#else ++ if(of_find_property(pdev->dev.of_node,"camclk",&num_parents)) ++ { ++ num_parents /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(num_parents < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, num_parents); ++ ret = -ENOENT ; ++ goto out; ++ } ++ iic_clks = kzalloc((sizeof(int) * num_parents), GFP_KERNEL); ++ pvhandler = kzalloc((sizeof(void *) * num_parents), GFP_KERNEL); ++ if(!iic_clks){ ++ ret = -ENOMEM; ++ goto out; ++ } ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = 0; ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", i,&iic_clks[i]); ++ if (!iic_clks[i]) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ ret = -ENOENT; ++ } ++ else ++ { ++ CamClkRegister("iic",iic_clks[i],&pvhandler[i]); ++ CamClkSetOnOff(pvhandler[i],1); ++ if(i == 0) ++ { ++ CAMCLK_SETRATE_ROUNDUP(stSetCfg,12000000); ++ CamClkAttrSet(pvhandler[i],&stSetCfg); ++ } ++ //CamClkUnregister(pvhandler[i]); ++ } ++ } ++ kfree(iic_clks); ++ //kfree(pvhandler); ++ if(ret){ ++ goto out; ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#endif ++ HWI2C_DBG_INFO(" mstar_i2c_probe\n"); ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(!res) ++ { ++ ret = -ENOENT; ++ goto out; ++ } ++ base = (void *)(IO_ADDRESS(res->start)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if(!res) ++ { ++ ret = -ENOENT; ++ goto out; ++ } ++ chipbase = (void *)(IO_ADDRESS(res->start)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ if(!res) ++ { ++ ret = -ENOENT; ++ goto out; ++ } ++ clkbase = (void *)(IO_ADDRESS(res->start)); ++ ++ i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); ++ if (!i2c_dev) ++ { ++ ret = -ENOMEM; ++ goto out; ++ } ++ i2c_dev->base = base; ++ i2c_dev->chipbase = chipbase; ++ i2c_dev->adapter.algo = &sg_ms_i2c_algorithm; ++ i2c_dev->cont_id = pdev->id; ++ i2c_dev->dev = &pdev->dev; ++ i2c_dev->clkbase = clkbase; ++ ++ of_property_read_u32(node, "i2c-group", &i2cgroup); ++ //i2cgroup = of_alias_get_id(pdev->dev.of_node, "iic"); ++ HWI2C_DBG_INFO("i2cgroup=%d\n",i2cgroup); ++ i2c_dev->i2cgroup = i2cgroup; ++ ++ of_property_read_u32(node, "i2c-padmux", &i2cpadmux); ++ HWI2C_DBG_INFO("i2cpadmux=%d\n",i2cpadmux); ++ i2c_dev->i2cpadmux = i2cpadmux; ++ ++ of_property_read_u32(node, "i2c-speed", &i2c_speed); ++ HWI2C_DBG_INFO("i2c_speed=%d\n",i2c_speed); ++ i2c_dev->i2c_speed = i2c_speed; ++ ++ of_property_read_u32(node, "i2c-en-dma", &i2c_en_dma); ++ HWI2C_DBG_INFO("i2c_en_dma=%d\n",i2c_en_dma); ++ i2c_dev->i2c_en_dma = i2c_en_dma; ++ ++ if (pdev->dev.of_node) { ++ const struct of_device_id *match; ++ match = of_match_device(mstar_i2c_of_match, &pdev->dev); ++ //i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, ++ // "sstar,cedric-i2c-dvc"); ++ } else if (pdev->id == 3) { ++ i2c_dev->is_dvc = 1; ++ } ++ ++ #ifdef CONFIG_MS_I2C_INT_ISR ++ #if 0 //tmp cancel request ISR ++ //init isr ++ data->i2cgroup = i2c_dev->i2cgroup; ++ data->i2cirq = CamIrqOfParseAndMap(node, 0); ++ HAL_HWI2C_IrqRequest(data->i2cirq, i2c_dev->i2cgroup, (void*)pdev); ++ //init tcond ++ HAL_HWI2C_DMA_TsemInit((u8)i2c_dev->i2cgroup); ++ //HWI2C_DBG_ERR("1mstar_i2c_probe i2cirq %d\n", data->i2cirq); ++ #endif ++ #endif ++ ++ init_completion(&i2c_dev->msg_complete); ++ ++ platform_set_drvdata(pdev, i2c_dev); ++ ++ MDrv_HW_IIC_Init(i2c_dev->base,i2c_dev->chipbase,i2cgroup,clkbase, i2cpadmux, i2c_speed, i2c_en_dma); ++ ++ //i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); ++ i2c_dev->adapter.owner = THIS_MODULE; ++ i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; ++ //strlcpy(i2c_dev->adapter.name, "Sstar I2C adapter", ++ // sizeof(i2c_dev->adapter.name)); ++ scnprintf(i2c_dev->adapter.name, sizeof(i2c_dev->adapter.name), ++ "Sstar I2C adapter %d", i2cgroup); ++ i2c_dev->adapter.algo = &sg_ms_i2c_algorithm; ++ ++ i2c_dev->adapter.dev.parent = &pdev->dev; ++ i2c_dev->adapter.nr = i2cgroup; ++ i2c_dev->adapter.dev.of_node = pdev->dev.of_node; ++ ++ pdev->dev.platform_data = (void*)data; ++ ++ HWI2C_DBG_INFO(" i2c_dev->adapter.nr=%d\n",i2c_dev->adapter.nr); ++ i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); ++ ++ ret = i2c_add_numbered_adapter(&i2c_dev->adapter); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to add I2C adapter\n"); ++ goto out; ++ } ++ ++ return 0; ++//err return ++out: ++ if(data){ ++ kfree(data); ++ } ++ //clk_unprepare(i2c_dev->div_clk); ++ return ret; ++} ++ ++static int mstar_i2c_remove(struct platform_device *pdev) ++{ ++ struct mstar_i2c_dev *i2c_dev = platform_get_drvdata(pdev); ++ i2c_dev_data *data; ++//#if 1 ++#ifndef CONFIG_CAM_CLK ++#else ++ int num_parents, i; ++ int *iic_clks; ++#endif ++ data = (i2c_dev_data*)pdev->dev.platform_data; ++ ++ MDrv_HW_IIC_DeInit(i2c_dev->adapter.nr); ++ #ifdef CONFIG_MS_I2C_INT_ISR ++ //free isr and uninit I2c DMA ++ HAL_HWI2C_IrqFree(data->i2cirq); ++ HAL_HWI2C_DMA_TsemDeinit(data->i2cgroup); ++ #endif ++#ifndef CONFIG_CAM_CLK ++#else ++ if(of_find_property(pdev->dev.of_node,"camclk",&num_parents)) ++ { ++ num_parents /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(num_parents < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, num_parents); ++ goto out; ++ } ++ iic_clks = kzalloc((sizeof(int) * num_parents), GFP_KERNEL); ++ if(!iic_clks){ ++ goto out; ++ } ++ for(i = 0; i < num_parents; i++) ++ { ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", i,&iic_clks[i]); ++ if (!iic_clks[i]) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkSetOnOff(pvhandler[i],0); ++ CamClkUnregister(pvhandler[i]); ++ } ++ } ++ kfree(iic_clks); ++ kfree(pvhandler); ++ pvhandler = NULL; ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++ out: ++#endif ++ ++ kfree(data); ++ i2c_del_adapter(&i2c_dev->adapter); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mstar_i2c_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct mstar_i2c_dev *i2c_dev = platform_get_drvdata(pdev); ++ ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **iic_clks; ++ struct clk *parent; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ iic_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(iic_clks[i])) ++ { ++ printk( "[iic_clks] Fail to get clk!\n" ); ++ kfree(iic_clks); ++ return -1; ++ } ++ else ++ { ++ //force clock parent to 0, otherwise set rate to 12MHz in resume will not take effect ++ parent = clk_hw_get_parent_by_index(__clk_get_hw(iic_clks[i]), 0)->clk; ++ //pr_err("%s parent 0 clk: %ld\n", pdev->name, clk_get_rate(parent)); ++ clk_set_parent(iic_clks[i], parent); ++ clk_disable_unprepare(iic_clks[i]); ++ clk_put(iic_clks[i]); ++ } ++ } ++ kfree(iic_clks); ++#endif ++ MDrv_HW_IIC_DeInit(i2c_dev->adapter.nr); ++ i2c_lock_adapter(&i2c_dev->adapter); ++ i2c_dev->is_suspended = true; ++ i2c_unlock_adapter(&i2c_dev->adapter); ++ ++ return 0; ++} ++ ++static int mstar_i2c_resume(struct platform_device *pdev) ++{ ++ struct mstar_i2c_dev *i2c_dev = platform_get_drvdata(pdev); ++ ++ //int ret; ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **iic_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ iic_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(iic_clks[i])) ++ { ++ printk( "[iic_clks] Fail to get clk!\n" ); ++ kfree(iic_clks); ++ return -1; ++ } ++ else ++ { ++ clk_prepare_enable(iic_clks[i]); ++ if(i == 0) ++ clk_set_rate(iic_clks[i], 12000000); ++ clk_put(iic_clks[i]); ++ } ++ } ++ kfree(iic_clks); ++#endif ++ ++ i2c_lock_adapter(&i2c_dev->adapter); ++ ++ MDrv_HW_IIC_Init(i2c_dev->base,i2c_dev->chipbase,i2c_dev->adapter.nr,i2c_dev->clkbase, i2c_dev->i2cpadmux, i2c_dev->i2c_speed, i2c_dev->i2c_en_dma); ++ i2c_dev->is_suspended = false; ++ ++ i2c_unlock_adapter(&i2c_dev->adapter); ++ ++ return 0; ++} ++#endif ++MODULE_DEVICE_TABLE(of, mstar_i2c_of_match); ++ ++ ++static struct platform_driver mstar_i2c_driver = { ++ .probe = mstar_i2c_probe, ++ .remove = mstar_i2c_remove, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = mstar_i2c_suspend, ++ .resume = mstar_i2c_resume, ++#endif ++ .driver = { ++ .name = "mstar-i2c", ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_i2c_of_match, ++ }, ++}; ++ ++static int __init mstar_i2c_init_driver(void) ++{ ++ return platform_driver_register(&mstar_i2c_driver); ++} ++ ++static void __exit mstar_i2c_exit_driver(void) ++{ ++ platform_driver_unregister(&mstar_i2c_driver); ++} ++ ++subsys_initcall(mstar_i2c_init_driver); ++module_exit(mstar_i2c_exit_driver); ++ ++MODULE_DESCRIPTION("Sstar I2C Bus Controller driver"); ++MODULE_AUTHOR("SSTAR"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/i2c/ms_iic.h b/drivers/sstar/i2c/ms_iic.h +new file mode 100755 +index 000000000000..7c4e91444c0e +--- /dev/null ++++ b/drivers/sstar/i2c/ms_iic.h +@@ -0,0 +1,258 @@ ++/* ++* ms_iic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_IIC_H_ ++#define _DRV_IIC_H_ ++ ++#include "ms_types.h" ++ ++#define IIC_NUM_OF_MAX (20) ++#define I2C_BYTE_MASK 0xFF ++ ++#define IIC_NUM_OF_HW (1) ++#define MDRV_NAME_IIC "iic" ++#define MDRV_MAJOR_IIC 0x8a ++#define MDRV_MINOR_IIC 0x00 ++#define HWI2C_PORTM 4 //maximum support ports ++ ++#define I2C_CUST_M_NOSTOP BIT1 /* customized use of i2c_msg.flags ++ no stop after sending data: S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] ++ */ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++#define MSIF_HWI2C_LIB_CODE {'H','I','2','C'} //Lib code ++#define MSIF_HWI2C_LIBVER {'0','6'} //LIB version ++#define MSIF_HWI2C_BUILDNUM {'0','6'} //Build Number ++#define MSIF_HWI2C_CHANGELIST {'0','0','5','4','9','6','1','5'} //P4 ChangeList Number ++ ++#define HWI2C_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_TAG, /* 'MSIF' */ \ ++ MSIF_CLASS, /* '00' */ \ ++ MSIF_CUS, /* 0x0000 */ \ ++ MSIF_MOD, /* 0x0000 */ \ ++ MSIF_CHIP, \ ++ MSIF_CPU, \ ++ MSIF_HWI2C_LIB_CODE, /* IP__ */ \ ++ MSIF_HWI2C_LIBVER, /* 0.0 ~ Z.Z */ \ ++ MSIF_HWI2C_BUILDNUM, /* 00 ~ 99 */ \ ++ MSIF_HWI2C_CHANGELIST, /* CL# */ \ ++ MSIF_OS ++ ++// ++typedef void* (*ms_i2c_feature_fp)(u16, u16, void*, u32); ++ ++/// debug level ++typedef enum _HWI2C_DbgLv ++{ ++ E_HWI2C_DBGLV_NONE, /// no debug message ++ E_HWI2C_DBGLV_ERR_ONLY, /// show error only ++ E_HWI2C_DBGLV_INFO, /// show error & informaiton ++ E_HWI2C_DBGLV_ALL /// show error, information & funciton name ++}HWI2C_DbgLv; ++ ++/// I2C select master port ++typedef enum _HWI2C_PORT ++{ ++ E_HWI2C_PORT_0 = 0, /// port 0_0 //disable port 0 ++ E_HWI2C_PORT0_1, /// port 0_1 ++ E_HWI2C_PORT0_2, /// port 0_2 ++ E_HWI2C_PORT0_3, /// port 0_3 ++ E_HWI2C_PORT0_4, /// port 0_4 ++ E_HWI2C_PORT0_5, /// port 0_5 ++ E_HWI2C_PORT0_6, /// port 0_6 ++ E_HWI2C_PORT0_7, /// port 0_7 ++ ++ E_HWI2C_PORT_1 = 8, /// port 1_0 //disable port 1 ++ E_HWI2C_PORT1_1, /// port 1_1 ++ E_HWI2C_PORT1_2, /// port 1_2 ++ E_HWI2C_PORT1_3, /// port 1_3 ++ E_HWI2C_PORT1_4, /// port 1_4 ++ E_HWI2C_PORT1_5, /// port 1_5 ++ E_HWI2C_PORT1_6, /// port 1_6 ++ E_HWI2C_PORT1_7, /// port 1_7 ++ ++ E_HWI2C_PORT_2 = 16,/// port 2_0 //disable port 2 ++ E_HWI2C_PORT2_1, /// port 2_1 ++ E_HWI2C_PORT2_2, /// port 2_2 ++ E_HWI2C_PORT2_3, /// port 2_3 ++ E_HWI2C_PORT2_4, /// port 2_4 ++ E_HWI2C_PORT2_5, /// port 2_5 ++ E_HWI2C_PORT2_6, /// port 2_6 ++ E_HWI2C_PORT2_7, /// port 2_7 ++ ++ E_HWI2C_PORT_3 = 24,/// port 3_0 //disable port 3 ++ E_HWI2C_PORT3_1, /// port 3_1 ++ E_HWI2C_PORT3_2, /// port 3_2 ++ E_HWI2C_PORT3_3, /// port 3_3 ++ E_HWI2C_PORT3_4, /// port 3_4 ++ E_HWI2C_PORT3_5, /// port 3_5 ++ E_HWI2C_PORT3_6, /// port 3_6 ++ E_HWI2C_PORT3_7, /// port 3_7 ++ ++ E_HWI2C_PORT_NOSUP /// non-support port ++}HWI2C_PORT; ++ ++/// I2C clock speed select ++typedef enum _HWI2C_CLKSEL ++{ ++ E_HWI2C_HIGH = 0, /// high speed ++ E_HWI2C_NORMAL, /// normal speed ++ E_HWI2C_SLOW, /// slow speed ++ E_HWI2C_VSLOW, /// very slow ++ E_HWI2C_USLOW, /// ultra slow ++ E_HWI2C_UVSLOW, /// ultra-very slow ++ E_HWI2C_NOSUP /// non-support speed ++}HWI2C_CLKSEL; ++ ++/// I2C state ++typedef enum _HWI2C_State ++{ ++ E_HWI2C_IDLE, /// idle state ++ E_HWI2C_READ_DATA, /// read data state ++ E_HWI2C_WRITE_DATA, /// write data state ++ E_HWI2C_DMA_READ_DATA, /// DMA read data state ++ E_HWI2C_DMA_WRITE_DATA /// DMA write data state ++}HWI2C_State; ++ ++typedef enum { ++ E_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HWI2C_READ_MODE_MAX ++} HWI2C_ReadMode; ++ ++typedef enum _HWI2C_DMA_ADDRMODE ++{ ++ E_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HWI2C_DMA_ADDR_10BIT, ++ E_HWI2C_DMA_ADDR_MAX, ++}HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HWI2C_DMA_READMODE ++{ ++ E_HWI2C_DMA_READ_NOSTOP = 0, ++ E_HWI2C_DMA_READ_STOP, ++ E_HWI2C_DMA_READ_MAX, ++}HWI2C_DMA_READMODE; ++ ++typedef enum _HWI2C_DMA_MIUPRI ++{ ++ E_HWI2C_DMA_PRI_LOW = 0, ++ E_HWI2C_DMA_PRI_HIGH, ++ E_HWI2C_DMA_PRI_MAX, ++}HWI2C_DMA_MIUPRI; ++ ++typedef enum _HWI2C_DMA_MIUCH ++{ ++ E_HWI2C_DMA_MIU_CH0 = 0, ++ E_HWI2C_DMA_MIU_CH1, ++ E_HWI2C_DMA_MIU_MAX, ++}HWI2C_DMA_MIUCH; ++ ++typedef enum _HWI2C_DMA_HW_FEATURE ++{ ++ E_HWI2C_FEATURE_NWRITE = 0, ++ E_HWI2C_FEATURE_MAX, ++}HWI2C_DMA_HW_FEATURE; ++ ++/// I2C master pin config ++typedef struct _HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HWI2C_PinCfg; ++ ++/// I2C port config ++typedef struct _HWI2C_PortCfg ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HWI2C_PORT ePort; /// number ++ HWI2C_CLKSEL eSpeed; /// clock speed ++ HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HWI2C_UnitCfg ++{ ++ HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HWI2C_PinCfg sI2CPin; /// pin info ++ HWI2C_CLKSEL eSpeed; /// speed ++ HWI2C_PORT ePort; /// port ++ HWI2C_ReadMode eReadMode; /// read mode ++ int eGroup; /// port ++ U32 eBaseAddr; ++ U32 eChipAddr; ++ U32 eClkAddr; ++}HWI2C_UnitCfg; ++ ++/// I2C information ++typedef struct _HWI2C_Info ++{ ++ U32 u32IOMap; /// base address ++ HWI2C_UnitCfg sUnitCfg; /// configuration ++}HWI2C_Info; ++ ++/// I2C status ++typedef struct _HWI2C_Status ++{ ++ U8 u8DbgLevel; /// debug level ++ BOOL bIsInit; /// initialized ++ BOOL bIsMaster; /// master ++ HWI2C_State eState; /// state ++}HWI2C_Status; ++ ++typedef struct _I2C_DMA ++{ ++ dma_addr_t i2c_dma_addr; ++ u8 *i2c_virt_addr; ++}I2C_DMA; ++ ++extern I2C_DMA HWI2C_DMA[HWI2C_PORTM]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++void MDrv_HW_IIC_Init(void *base,void *chipbase,int i2cgroup,void *clkbase, int i2cpadmux, int i2cspeed, int i2c_enDma); ++BOOL MDrv_HWI2C_Init(HWI2C_UnitCfg *psCfg); ++BOOL MDrv_HWI2C_WriteBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++BOOL MDrv_HWI2C_ReadBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++//BOOL MDrv_HWI2C_SetClk(HWI2C_CLKSEL eClk); ++ ++ ++BOOL MDrv_HWI2C_Start(U16 u16PortOffset); ++BOOL MDrv_HWI2C_Stop(U16 u16PortOffset); ++BOOL MDrv_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++BOOL MDrv_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++BOOL MDrv_HWI2C_NoAck(U16 u16PortOffset); ++BOOL _MDrv_HWI2C_GetPortRegOffset(U8 u8Port, U16 *pu16Offset); ++BOOL MDrv_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++ ++ ++ ++#endif // _DRV_IIC_H_ ++ +diff --git a/drivers/sstar/include/MsTypes.h b/drivers/sstar/include/MsTypes.h +new file mode 100755 +index 000000000000..b96f7b9ff181 +--- /dev/null ++++ b/drivers/sstar/include/MsTypes.h +@@ -0,0 +1,425 @@ ++/* ++* MsTypes.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MS_TYPES_H_ ++#define _MS_TYPES_H_ ++ ++ ++#ifdef CONFIG_ENABLE_MENUCONFIG ++ #include "autoconf.h" ++#endif ++ ++#include ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++#define SUPPORT_ANDROID_L_PHYVIR_TYPE ++ ++#if defined(UFO_PUBLIC_HEADER_300) ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned long MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed long MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef MS_U32 MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef MS_U32 MS_PHYADDR; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U32 MS_PHY; // 8 bytes ++ /// data type size_t ++ typedef size_t MS_SIZE; // 8 bytes ++ /// definition for MS_BOOL ++ typedef unsigned char MS_BOOL; // 1 byte ++ /// print type MPRI_DEC ++ #define MPRI_DEC "%ld" ++ /// print type MPRI_UDEC ++ #define MPRI_UDEC "%lu" ++ /// print type MPRI_HEX ++ #define MPRI_HEX "%lx" ++#elif defined(UFO_PUBLIC_HEADER_212) ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned long MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed long MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef MS_U32 MS_VIRT; // 4 bytes ++ /// data type hardware physical address ++ typedef MS_U32 MS_PHYADDR; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U32 MS_PHY; // 4 bytes ++ /// data type null pointer ++ /// definition for MS_BOOL ++ typedef unsigned char MS_BOOL; ++ /// data type size_t ++ typedef MS_U32 MS_SIZE; // 4 bytes ++#else ++#if defined (__aarch64__) ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned int MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed int MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef size_t MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef size_t MS_PHYADDR; // 8 bytes ++ /// data type size_t ++ typedef size_t MS_SIZE; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U64 MS_PHY; // 8 bytes ++ /// definition for MS_BOOL ++ typedef unsigned char MS_BOOL; // 1 byte ++ /// print type MPRI_PHY ++ #define MPRI_PHY "%x" ++ /// print type MPRI_VIRT ++ #define MPRI_VIRT "%tx" ++#elif defined(MSOS_TYPE_NUTTX) ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned long MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed long MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef MS_U32 MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef MS_U32 MS_PHYADDR; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U32 MS_PHY; // 8 bytes ++ /// data type size_t ++ typedef MS_U32 MS_SIZE; // 8 bytes ++ /// definition for MS_BOOL ++ typedef unsigned char MS_BOOL; // 1 byte ++ /// print type MPRI_PHY ++ #define MPRI_PHY "%x" ++ /// print type MPRI_PHY ++ #define MPRI_VIRT "%tx" ++#else ++#if (defined(CONFIG_PURE_SN) || defined(CONFIG_MBOOT)) ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned int MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed int MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef MS_U32 MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef MS_U32 MS_PHYADDR; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U32 MS_PHY; // 8 bytes ++ /// data type size_t ++ typedef MS_U32 MS_SIZE; // 8 bytes ++ /// definition for MS_BOOL ++ typedef unsigned char MS_BOOL; // 1 byte ++ /// print type MPRI_PHY ++ #define MPRI_PHY "%x" ++ /// print type MPRI_PHY ++ #define MPRI_VIRT "%tx" ++#else ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned int MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed int MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef size_t MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef MS_U64 MS_PHYADDR; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U64 MS_PHY; // 8 bytes ++ /// data type size_t ++ typedef size_t MS_SIZE; // 8 bytes ++ /// definition for MS_BOOL ++ typedef unsigned char MS_BOOL; // 1 byte ++ /// print type MPRI_PHY ++ #define MPRI_PHY "%x" ++ /// print type MPRI_PHY ++ #define MPRI_VIRT "%tx" ++#endif ++#endif ++#endif ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// definition for VOID ++typedef void VOID; ++/// definition for FILEID ++typedef MS_S32 FILEID; ++ ++//[TODO] use MS_U8, ... instead ++// data type for 8051 code ++//typedef MS_U16 WORD; ++//typedef MS_U8 BYTE; ++ ++#ifndef MSOS_TYPE_LINUX_KERNEL ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++#endif //End undef MSOS_TYPE_LINUX_KERNEL ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++///Define MS FB Format, to share with GE,GOP ++/// FIXME THE NAME NEED TO BE REFINED, AND MUST REMOVE UNNESSARY FMT ++typedef enum ++{ ++ /// color format I1 ++ E_MS_FMT_I1 = 0x0, ++ /// color format I2 ++ E_MS_FMT_I2 = 0x1, ++ /// color format I4 ++ E_MS_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ E_MS_FMT_I8 = 0x4, ++ /// color format blinking display ++ E_MS_FMT_FaBaFgBg2266 = 0x6, ++ /// color format for blinking display format ++ E_MS_FMT_1ABFgBg12355 = 0x7, ++ /// color format RGB565 ++ E_MS_FMT_RGB565 = 0x8, ++ /// color format ARGB1555 ++ /// @note [URANUS] ARGB1555 is only RGB555 ++ E_MS_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ E_MS_FMT_ARGB4444 = 0xa, ++ /// color format ARGB1555 DST ++ E_MS_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ E_MS_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ E_MS_FMT_ARGB8888 = 0xf, ++ /// color format RGBA5551 ++ E_MS_FMT_RGBA5551 = 0x10, ++ /// color format RGBA4444 ++ E_MS_FMT_RGBA4444 = 0x11, ++ /// Start of New color define ++ /// color format BGRA5551 ++ E_MS_FMT_BGRA5551 = 0x12, ++ /// color format ABGR1555 ++ E_MS_FMT_ABGR1555 = 0x13, ++ /// color format ABGR4444 ++ E_MS_FMT_ABGR4444 = 0x14, ++ /// color format BGRA4444 ++ E_MS_FMT_BGRA4444 = 0x15, ++ /// color format BGR565 ++ E_MS_FMT_BGR565 = 0x16, ++ /// color format RGBA8888 ++ E_MS_FMT_RGBA8888 = 0x1d, ++ /// color format BGRA8888 ++ E_MS_FMT_BGRA8888 = 0x1e, ++ /// color format ABGR8888 ++ E_MS_FMT_ABGR8888 = 0x1f, ++ /// color format AYUV8888 ++ E_MS_FMT_AYUV8888 = 0x20, ++ ++ E_MS_FMT_GENERIC = 0xFFFF, ++ ++} MS_ColorFormat; ++ ++typedef union _MSIF_Version ++{ ++ struct _DDI ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 model; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 change[8]; ++ MS_U8 os; ++ } DDI; ++ struct _MW ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 mod; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 changelist[8]; ++ MS_U8 os; ++ } MW; ++ struct _APP ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U8 id[4]; ++ MS_U8 quality; ++ MS_U8 version[4]; ++ MS_U8 time[6]; ++ MS_U8 changelist[8]; ++ MS_U8 reserve[3]; ++ } APP; ++} MSIF_Version; ++ ++typedef struct _MS_SW_VERSION_INFO ++{ ++ char UtopiaBspVersion[8]; //Utopia BSP Version ++ char MajorVersion[4]; //Major Version Number ++ char MinorVersion[4]; //Minor Version Number ++ char ChangeList_API[16]; //Sync Perforce Change List Number in API Folder ++ char ChangeList_DRV[16]; //Sync Perforce Change List Number in DRV Folder ++ char ChangeList_HAL[16]; //Sync Perforce Change List Number in HAL Folder ++ ++} MS_SW_VERSION_INFO; ++ ++typedef struct _MS_SW_VERSION_NUM ++{ ++ char UtopiaBspVersion[32]; ++ MS_U32 UtopiaVerNum; ++} MS_SW_VERSION_NUM; ++ ++/* ++ * function pointers ++ */ ++typedef MS_U32 (*FUtopiaOpen)(void** ppInstance, const void* const pAttribute); ++typedef MS_U32 (*FUtopiaIOctl)(void* pInstance, ++ MS_U32 u32Cmd, void* const pArgs); ++typedef MS_U32 (*FUtopiaClose)(void* pInstance); ++typedef MS_U32 (*FUtopiaSTR)(MS_U32 u32PowerState, void* pModule); ++typedef MS_U32 (*FUtopiaMdbIoctl)(MS_U32 cmd, const void* const pArgs); ++ ++#ifndef MSOS_TYPE_DEF_MSOSATTRIBUTE ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++#define MSOS_TYPE_DEF_MSOSATTRIBUTE ++#endif ++ ++#define DLL_PACKED __attribute__((__packed__)) ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/sstar/include/_ms_private.h b/drivers/sstar/include/_ms_private.h +new file mode 100755 +index 000000000000..e1b319e462fb +--- /dev/null ++++ b/drivers/sstar/include/_ms_private.h +@@ -0,0 +1,57 @@ ++/* ++* _ms_private.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MS_PRIVATE__ ++#define __MS_PRIVATE__ ++ ++ ++struct ms_chip ++{ ++ void (*chip_flush_miu_pipe)(void); ++ void (*chip_flush_miu_pipe_nodsb)(void); ++ void (*chip_flush_memory)(void); ++ void (*chip_read_memory)(void); ++ int (*cache_outer_is_enabled)(void); ++ void (*cache_flush_dcache_page)(struct page *page); ++ void (*cache_flush_all)(void); ++ void (*cache_clean_range_va_pa)(unsigned long, unsigned long,unsigned long); ++ void (*cache_flush_range_va_pa)(unsigned long, unsigned long,unsigned long); ++ void (*cache_clean_range)(unsigned long, unsigned long); ++ void (*cache_flush_range)(unsigned long, unsigned long); ++ void (*cache_invalidate_range)(unsigned long, unsigned long); ++ u64 (*phys_to_miu)(u64); ++ u64 (*miu_to_phys)(u64); ++ ++ int (*chip_get_device_id)(void); ++ char* (*chip_get_platform_name)(void); ++ int (*chip_get_revision)(void); ++ ++ const char* (*chip_get_API_version)(void); ++ ++ int (*chip_get_boot_dev_type)(void); ++ unsigned long long (*chip_get_riu_phys)(void); ++ int (*chip_get_riu_size)(void); ++ int (*chip_get_storage_type)(void); ++ int (*chip_get_package_type)(void); ++ ++ int (*chip_function_set)(int functionId, int param); ++ ++ u64 (*chip_get_us_ticks)(void); ++}; ++ ++ ++#endif +diff --git a/drivers/sstar/include/cam_clkgen.h b/drivers/sstar/include/cam_clkgen.h +new file mode 100755 +index 000000000000..3582bfde67bc +--- /dev/null ++++ b/drivers/sstar/include/cam_clkgen.h +@@ -0,0 +1,91 @@ ++/* ++* cam_clkgen.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_clkgen.h ++/// @brief Cam Clk Wrapper Header File for ++/// 1. RTK OS ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_CLK_GEN_H__ ++#define __CAM_CLK_GEN_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++ ++ ++//============================================================================= ++// Description: ++// return the rate of clk ++// Return: ++// the clk whose rate is being returned ++//============================================================================= ++unsigned long CamClkGetRate(struct clk *clk); ++unsigned long CamClkHWGetNumParents(const struct clk_hw *hw); ++const char *CamOfClkGetParentName(struct device_node *np, int index); ++unsigned int CamOfClkGetParentCount(struct device_node *np); ++struct clk_hw *__CamClkGetHw(struct clk *clk); ++long CamClkRoundRate(struct clk *clk, unsigned long rate); ++int CamClkSetParent(struct clk *clk, struct clk *parent); ++int CamClkSetRate(struct clk *clk, unsigned long rate); ++void CamClkDisable(struct clk *clk); ++void CamClkUnprepare(struct clk *clk); ++int CamClkEnable(struct clk *clk); ++int CamClkPrepare(struct clk *clk); ++int msys_of_property_read_u32_index(const struct device_node *np, ++ const char *propname, ++ u32 index, u32 *out_value); ++static inline void CamClkDisableUnprepare(struct clk *clk) ++{ ++ CamClkDisable(clk); ++ CamClkUnprepare(clk); ++} ++ ++static inline int CamClkPrepareEnable(struct clk *clk) ++{ ++ int ret; ++ ++ ret = CamClkPrepare(clk); ++ ++ if (ret) ++ return ret; ++ ret = CamClkEnable(clk); ++ ++ if (ret) ++ CamClkUnprepare(clk); ++ return ret; ++} ++ ++unsigned long CamClkHwGetNumParents(const struct clk_hw *hw); ++struct clk_hw *CamClkGetParentByIndex(const struct clk_hw *hw, unsigned int index); ++#endif /* __CAM_OS_WRAPPER_H__ */ +diff --git a/drivers/sstar/include/cam_dev_wrapper.h b/drivers/sstar/include/cam_dev_wrapper.h +new file mode 100644 +index 000000000000..d05e01c1123d +--- /dev/null ++++ b/drivers/sstar/include/cam_dev_wrapper.h +@@ -0,0 +1,83 @@ ++/* ++* cam_dev_wrapper.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __CAM_DEV_WRAPPER_H__ ++#define __CAM_DEV_WRAPPER_H__ ++ ++#define CAM_DEV_WRAPPER_VERSION "v1.0.2" ++ ++ ++#ifdef CAM_OS_RTK /*start RTK part*/ ++#include "cam_drv_poll.h" ++ ++struct pollfd { ++ int fd; ++ short events; ++ short revents; ++}; ++ ++#define _IOC(dir,type,nr,size) \ ++ (((dir) << 0) | \ ++ ((type) << 8) | \ ++ ((nr) << 16) | \ ++ ((size) << 24)) ++ ++#define _IOC_TYPECHECK(t) (sizeof(t)) ++ ++/* used to create numbers */ ++#define _IO(type,nr) _IOC(0,(type),(nr),0) ++#define _IOR(type,nr,size) _IOC(1,(type),(nr),(_IOC_TYPECHECK(size))) ++#define _IOW(type,nr,size) _IOC(2,(type),(nr),(_IOC_TYPECHECK(size))) ++#define _IOWR(type,nr,size) _IOC(3,(type),(nr),(_IOC_TYPECHECK(size))) ++ ++#define FILL_VERCHK_TYPE(var, var_ver, var_size, version) \ ++({ \ ++ var_ver = ((version & 0xffffffff)); \ ++ var_size = sizeof(var); \ ++ var; \ ++}) ++ ++int CamDevOpen(char* name); ++int CamDevClose(int fd); ++int CamDevIoctl(int fd, unsigned long request, void *param); ++int CamDevPoll(struct pollfd *fds, int nfds, int timeout); ++void* CamDevMmap(int length,int fd,int offset); ++int CamDevMunmap(int fd,void* start,int length); ++int CamDevRead(int fd, void *buf, unsigned int count); ++int CamDevWrite(int fd, const void *buf, unsigned int count); ++ ++#else // For linux user space ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define CamDevOpen(a) open(a, O_RDWR) ++#define CamDevClose(a) close(a) ++#define CamDevIoctl(a, b, c) ioctl(a, b, c) ++#define CamDevPoll(a, b, c) poll(a, b, c) ++#define CamDevMmap(a, b, c) mmap(0, a, PROT_READ | PROT_WRITE, MAP_SHARED, b, c) ++#define CamDevMunmap(a, b, c) munmap(b, c) ++#define CamDevRead(a, b, c) read(a, b, c) ++#define CamDevWrite(a, b, c) write(a, b, c) ++ ++#endif ++ ++#endif // __CAM_DEV_WRAPPER_H__ +diff --git a/drivers/sstar/include/cam_drv_buffer.h b/drivers/sstar/include/cam_drv_buffer.h +new file mode 100644 +index 000000000000..4ad506226f74 +--- /dev/null ++++ b/drivers/sstar/include/cam_drv_buffer.h +@@ -0,0 +1,219 @@ ++/* ++* cam_drv_buffer.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_drv_buffer.h ++/// @brief Cam Drv Buffer Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_DRV_BUFFER_H__ ++#define __CAM_DRV_BUFFER_H__ ++ ++#define CAM_DRV_BUFFER_VERSION "v0.0.1" ++ ++#include "cam_os_wrapper.h" ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++typedef enum ++{ ++ CAM_DRV_OK = 0, ++ CAM_DRV_NULL_PTR = 1, ++ CAM_DRV_FREE_ERROR = 2, ++ CAM_DRV_QUEUE_EMPTY = 3, ++ CAM_DRV_QUEUE_FULL = 4, ++ CAM_DRV_THREAD_RACE = 5, ++ CAM_DRV_OUT_OF_RANGE = 6, ++ CAM_DRV_FAIL = 7, ++} CamDrvRet_e; ++ ++typedef struct CamDrvQueueNode_s CamDrvQueueNode_t; ++ ++struct CamDrvQueueNode_s ++{ ++ void * pData; ++ CamDrvQueueNode_t* pNext; ++} ; ++ ++typedef struct CamDrvQueue_s ++{ ++ CamDrvQueueNode_t* pHead; ++ CamDrvQueueNode_t* pTail; ++ CamOsAtomic_t count; ++} CamDrvQueue_t; ++ ++typedef struct QueueOps_s ++{ ++ u32 nBufferSize; ++ u32 nThreadSize; ++ CamDrvQueueNode_t *pInsertNode; ++ CamDrvQueue_t* pInvalidHandle; ++ CamDrvQueue_t* pValidHandle; ++ CamDrvQueue_t* pFillHandle; ++ CamDrvQueue_t* pReadyHandle; ++} QueueOps_t; ++ ++//============================================================================= ++// Description: ++// Queue handle initialization ++// Parameters: ++// param[in] max_consumer: Maximum consumer thread count ++// Return: ++// Queue handle pointer ++//============================================================================= ++CamDrvQueue_t* CamDrvQueueInit(u32 nMaxConsumer); ++ ++//============================================================================= ++// Description: ++// Queue handle Release ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvQueueDeinit(CamDrvQueue_t* ptQueue); ++ ++//============================================================================= ++// Description: ++// Enqueue one block buffer ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// param[in] ptPushNode: Push node into queue. If ptPushNode == NULL , will use the memory allocation ++// param[in] ptData: input data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvQueuePush(CamDrvQueue_t* ptQueue, CamDrvQueueNode_t* ptPushNode, void* ptData); ++ ++//============================================================================= ++// Description: ++// Dequeue one block buffer ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// Return: ++// Queue node pointer ++//============================================================================= ++CamDrvQueueNode_t* CamDrvQueuePop(CamDrvQueue_t* ptQueue); ++ ++//============================================================================= ++// Description: ++// Query single buffer info ++// Parameters: ++// param[in] ptQueue: Queue handle. ++// param[out] count: How many node inside ptQueue. ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvQueueQuery(CamDrvQueue_t* ptQueue, s32* ptCount); ++ ++//============================================================================= ++// Description: ++// Buffer handle initialization ++// Parameters: ++// param[in] Buffer_size: The node size of Invalid linked list ++// param[in] max_consumer: Maximum consumer thread count ++// Return: ++// Buffer handle pointer ++//============================================================================= ++QueueOps_t* CamDrvBuffInit(u32 nBufferSize, u32 nMaxConsumer); ++ ++//============================================================================= ++// Description: ++// Buffer handle Release ++// Parameters: ++// param[in] ptBuff: Buffer handle ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffDeinit(QueueOps_t* ptBuff); ++ ++//============================================================================= ++// Description: ++// Add new buffer into valid linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: input data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffAdd(QueueOps_t* ptBuff, void* ptData); ++ ++//============================================================================= ++// Description: ++// Query buffer info for specific linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] size: the number of new buffer ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffQuery(QueueOps_t* ptBuff, s32* ptInvalidSize, s32* ptValidSize, s32* ptFillSize, s32* ptReadySize); ++ ++//============================================================================= ++// Description: ++// Get buffer from ready linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffGet(QueueOps_t* ptBuff, void** pptData); ++ ++//============================================================================= ++// Description: ++// Fill buffer from valid into filling linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffFill(QueueOps_t* ptBuff, void** pptData); ++ ++//============================================================================= ++// Description: ++// Recycle unused buffer from valid into invalid linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// param[in] ptData: output data ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffRecycle(QueueOps_t* ptBuff, void** pptData); ++ ++//============================================================================= ++// Description: ++// Extract buffer from fill into ready linked-list ++// Parameters: ++// param[in] param[in] ptBuff: Buffer handle ++// Return: ++// CAM_DRV_OK is returned if successful; otherwise, returns CamDrvRet_e. ++//============================================================================= ++CamDrvRet_e CamDrvBuffDone(QueueOps_t* ptBuff); ++ ++#endif /* __CAM_DRV_BUFFER_H__ */ +diff --git a/drivers/sstar/include/cam_drv_poll.h b/drivers/sstar/include/cam_drv_poll.h +new file mode 100644 +index 000000000000..c7794ef86dfe +--- /dev/null ++++ b/drivers/sstar/include/cam_drv_poll.h +@@ -0,0 +1,55 @@ ++/* ++* cam_drv_poll.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __CAM_DRV_POLL_H__ ++#define __CAM_DRV_POLL_H__ ++ ++#define CAM_DRV_POLL_VERSION "v1.0.1" ++ ++#include ++ ++#ifdef CAM_OS_RTK ++ ++#ifndef POLLIN ++#define POLLIN 0x1 ++#define POLLPRI 0x2 ++#define POLLOUT 0x4 ++#define POLLERR 0x8 ++#define POLLRDNORM 0x40 ++#endif ++ ++struct file ++{ ++ //u8 nPollval; // the event to be polled ++ s32 nPollTimeout; // used internally by poll ++ void *private_data; // for drivers’ private use ++}; ++ ++typedef void poll_table; ++#elif defined(__KERNEL__) ++#include ++#include ++#endif ++ ++s32 CamDrvPollRegEventGrp(void); ++void CamDrvPollDeRegEventGrp(u32 nEventID); ++void CamDrvPollSetEvent(u32 nEventID, u32 nEventBits); ++s32 CamDrvPollEvent(u32 nEventID, u32 nWaitBits, struct file *filp, poll_table *tPoll); ++ ++ ++#endif /* __CAM_DRV_POLL_H__ */ +diff --git a/drivers/sstar/include/cam_fs_wrapper.h b/drivers/sstar/include/cam_fs_wrapper.h +new file mode 100755 +index 000000000000..ee071393044a +--- /dev/null ++++ b/drivers/sstar/include/cam_fs_wrapper.h +@@ -0,0 +1,187 @@ ++/* ++* cam_fs_wrapper.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_fs_wrapper.h ++/// @brief Cam FS Wrapper Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_FS_WRAPPER_H__ ++#define __CAM_FS_WRAPPER_H__ ++ ++#define CAM_FS_WRAPPER_VERSION "v0.0.6" ++ ++#include "cam_os_wrapper.h" ++ ++#ifndef O_CLOEXEC ++#define O_CLOEXEC 02000000 ++#endif ++#ifndef O_NOATIME ++#define O_NOATIME 01000000 ++#endif ++#ifndef O_NOFOLLOW ++#define O_NOFOLLOW 00400000 ++#endif ++#ifndef O_DIRECTORY ++#define O_DIRECTORY 00200000 ++#endif ++#ifndef O_LARGEFILE ++#define O_LARGEFILE 00100000 ++#endif ++#ifndef O_DIRECT ++#define O_DIRECT 00040000 ++#endif ++#ifndef FASYNC ++#define FASYNC 00020000 ++#endif ++#ifndef O_DSYNC ++#define O_DSYNC 00010000 ++#endif ++#ifndef O_NONBLOCK ++#define O_NONBLOCK 00004000 ++#endif ++#ifndef O_APPEND ++#define O_APPEND 00002000 ++#endif ++#ifndef O_TRUNC ++#define O_TRUNC 00001000 ++#endif ++#ifndef O_NOCTTY ++#define O_NOCTTY 00000400 ++#endif ++#ifndef O_EXCL ++#define O_EXCL 00000200 ++#endif ++#ifndef O_CREAT ++#define O_CREAT 00000100 ++#endif ++#ifndef O_PATH ++#define O_PATH 010000000 ++#endif ++#ifndef O_RDWR ++#define O_RDWR 00000002 ++#endif ++#ifndef O_WRONLY ++#define O_WRONLY 00000001 ++#endif ++#ifndef O_RDONLY ++#define O_RDONLY 00000000 ++#endif ++#ifndef O_ACCMODE ++#define O_ACCMODE 00000003 ++#endif ++#ifndef O_SYNC ++#define __O_SYNC 04000000 ++#define O_SYNC (__O_SYNC|O_DSYNC) ++#endif ++ ++#ifndef SEEK_SET ++#define SEEK_SET 0 ++#endif ++#ifndef SEEK_CUR ++#define SEEK_CUR 1 ++#endif ++#ifndef SEEK_END ++#define SEEK_END 2 ++#endif ++ ++typedef enum ++{ ++ CAM_FS_OK = 0, ++ CAM_FS_FAIL = -1, ++} CamFsRet_e; ++ ++typedef void * CamFsFd; ++ ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] ptFd: Pointer to file descriptor. ++// [in] szPath: Point to a pathname naming the file. ++// [in] nFlag: File status flags. ++// [in] nMode: File access modes. ++// Return: ++// CAM_FS_OK on success. On error, CAM_FS_FAIL is returned. ++//============================================================================= ++CamFsRet_e CamFsOpen(CamFsFd *ptFd, const char *szPath, u32 nFlag, u32 nMode); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] tFd: File descriptor. ++// Return: ++// CAM_FS_OK on success. On error, CAM_FS_FAIL is returned. ++//============================================================================= ++CamFsRet_e CamFsClose(CamFsFd tFd); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] tFd: File descriptor. ++// [in] pBuf: Pointer to the buffer start address. ++// [in] nByte: Read up to nCount bytes from file descriptor nFd. ++// Return: ++// On success, the number of bytes read is returned. On error, -1 is returned. ++//============================================================================= ++s32 CamFsRead(CamFsFd tFd, void *pBuf, u32 nCount); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// [in] tFd: File descriptor. ++// [in] pBuf: Pointer to the buffer start address. ++// [in] nByte: Write up to nCount bytes to the file referred to by the file ++// descriptor nFd. ++// Return: ++// On success, the number of bytes written is returned (zero indicates nothing ++// was written). On error, -1 is returned. ++//============================================================================= ++s32 CamFsWrite(CamFsFd tFd, const void *pBuf, u32 nCount); ++ ++//============================================================================= ++// Description: ++// Reposition read/write file offset ++// Parameters: ++// [in] tFd: File descriptor. ++// [in] nOffset: Number of bytes to offset from nWhence. ++// [in] nWhence: Position used as reference for the offset. ++// --------------------------------------------------- ++// | Constant | Reference position | ++// --------------------------------------------------- ++// | SEEK_SET | Beginning of file | ++// --------------------------------------------------- ++// | SEEK_CUR | Current position of the file pointer | ++// --------------------------------------------------- ++// | SEEK_END | End of file | ++// --------------------------------------------------- ++// Return: ++// On success, returns the resulting offset location as measured in bytes ++// from the beginning of the file. On error, -1 is returned. ++//============================================================================= ++s32 CamFsSeek(CamFsFd tFd, u32 nOffset, u32 nWhence); ++ ++#endif /* __CAM_FS_WRAPPER_H__ */ +diff --git a/drivers/sstar/include/cam_os_condition.h b/drivers/sstar/include/cam_os_condition.h +new file mode 100755 +index 000000000000..605c99f57146 +--- /dev/null ++++ b/drivers/sstar/include/cam_os_condition.h +@@ -0,0 +1,184 @@ ++/* ++* cam_os_condition.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_CONDITION_H__ ++#define __CAM_OS_CONDITION_H__ ++ ++#include "cam_os_wrapper.h" ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#if defined(CAM_OS_RTK) ++#include "sys_MsWrapper_cus_os_sem.h" ++typedef Ms_DynSemaphor_t CamOsCondition_t; ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include "linux/wait.h" ++typedef wait_queue_head_t CamOsCondition_t; ++#else // CAM_OS_LINUX_USER ++#include "pthread.h" ++typedef struct ++{ ++ pthread_mutex_t tMutex; ++ pthread_cond_t tCondition; ++} CamOsCondition_t; ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionInit(ptCondition) \ ++ MsCreateDynSem(ptCondition, 0); ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionInit(ptCondition) \ ++ init_waitqueue_head(ptCondition); ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionInit(ptCondition) \ ++({ \ ++ pthread_condattr_t cattr; \ ++ pthread_condattr_init(&cattr); \ ++ pthread_condattr_setclock(&cattr, CLOCK_MONOTONIC); \ ++ pthread_cond_init(ptCondition.tCondition, &cattr); \ ++ pthread_mutex_init(ptCondition.tMutex, NULL); \ ++}) ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionDeinit(ptCondition) \ ++ MsDestroyDynSem(ptCondition) ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionDeinit(ptCondition) ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionDeinit(ptCondition) \ ++({ \ ++ pthread_cond_destroy(ptCondition.tCondition); \ ++ pthread_mutex_destroy(ptCondition.tMutex); \ ++}) ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionWakeUpAll(ptCondition) \ ++ MsProduceSafeDynSem(ptCondition, 1); ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionWakeUpAll(ptCondition) \ ++ wake_up_all(ptCondition); ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionWakeUpAll(ptCondition) \ ++({ \ ++ pthread_mutex_lock(ptCondition.tMutex); \ ++ pthread_cond_broadcast(ptCondition.tCondition); \ ++ pthread_mutex_unlock(ptCondition.tMutex); \ ++}) ++#endif ++ ++#if defined(CAM_OS_RTK) ++#define CamOsConditionWait(ptCondition, condition) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ while (!(condition)) \ ++ MsConsumeDynSem(ptCondition); \ ++ __eRet; \ ++}) ++#elif defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionWait(ptCondition, condition) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ wait_event((*(ptCondition)), condition); \ ++ __eRet; \ ++}) ++#else // CAM_OS_LINUX_USER ++#define CamOsConditionWait(ptCondition, condition) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ pthread_mutex_lock(ptCondition.tMutex); \ ++ while (!(condition)) \ ++ pthread_cond_wait(ptCondition.tCondition, ptCondition.tMutex); \ ++ pthread_mutex_unlock(ptCondition.tMutex); \ ++ __eRet; \ ++}) ++#endif ++ ++#if defined(CAM_OS_LINUX_KERNEL) ++#define CamOsConditionTimedWait(ptCondition, condition, nMsec) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ if (!wait_event_timeout((*(ptCondition)), condition, \ ++ msecs_to_jiffies(nMsec))) \ ++ { \ ++ __eRet = CAM_OS_TIMEOUT; \ ++ } \ ++ __eRet; \ ++}) ++#elif defined(CAM_OS_RTK) ++#define __CamOsConditionTimedWait(ptCondition, condition, timeout_ms) \ ++({ \ ++ unsigned long __ret = timeout_ms; \ ++ unsigned long long __target_time = CamOsGetTimeInMs() + timeout_ms; \ ++ while (!(condition)) \ ++ { \ ++ if (MS_NO_MESSAGE == MsConsumeDynSemDelay(ptCondition, __ret)) { \ ++ __ret = (condition); \ ++ break; \ ++ } \ ++ __ret = (unsigned long)(__target_time - CamOsGetTimeInMs()); \ ++ } \ ++ __ret; \ ++}) ++ ++#define CamOsConditionTimedWait(ptCondition, condition, nMsec) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ if(!__CamOsConditionTimedWait(ptCondition, condition, nMsec)) \ ++ { \ ++ __eRet = CAM_OS_TIMEOUT; \ ++ } \ ++ __eRet; \ ++}) ++#else // CAM_OS_LINUX_USER ++#define __CamOsConditionTimedWait(ptCondition, condition, timeout_ms) \ ++({ \ ++ int __ret = 1; \ ++ struct timespec max_wait; \ ++ s64 nano_sec = 0; \ ++ clock_gettime(CLOCK_MONOTONIC, &max_wait); \ ++ nano_sec = (timeout_ms * 1000000LL) + max_wait.tv_nsec; \ ++ max_wait.tv_sec += (nano_sec / 1000000000LL); \ ++ max_wait.tv_nsec = nano_sec % 1000000000LL; \ ++ pthread_mutex_lock(ptCondition.tMutex); \ ++ while (!(condition)) { \ ++ if (0 != pthread_cond_timedwait(ptCondition.tCondition, \ ++ ptCondition.tMutex, &max_wait)) { \ ++ __ret = (condition); \ ++ break; \ ++ } \ ++ } \ ++ pthread_mutex_unlock(ptCondition.tMutex); \ ++ __ret; \ ++}) ++ ++#define CamOsConditionTimedWait(ptCondition, condition, nMsec) \ ++({ \ ++ CamOsRet_e __eRet = CAM_OS_OK; \ ++ if(!__CamOsConditionTimedWait(ptCondition, condition, nMsec)) \ ++ { \ ++ __eRet = CAM_OS_TIMEOUT; \ ++ } \ ++ __eRet; \ ++}) ++#endif ++ ++#endif //__CAM_OS_CONDITION_H__ +diff --git a/drivers/sstar/include/cam_os_util.h b/drivers/sstar/include/cam_os_util.h +new file mode 100644 +index 000000000000..42c46c665b7d +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util.h +@@ -0,0 +1,144 @@ ++/* ++* cam_os_util.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_H__ ++#define __CAM_OS_UTIL_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define FORCE_INLINE __attribute__((always_inline)) inline ++ ++#ifndef offsetof ++#ifdef __compiler_offsetof ++#define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) ++#else ++#ifdef size_t ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++#else ++#define offsetof(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) ++#endif ++#endif ++#endif ++ ++#define CAM_OS_CONTAINER_OF(ptr, type, member) ({ \ ++ void *__mptr = (void *)(ptr); \ ++ ((type *)(__mptr - offsetof(type, member))); }) ++ ++#ifndef likely ++#define CAM_OS_LIKELY(x) __builtin_expect(!!(x), 1) ++#else ++#define CAM_OS_LIKELY(x) likely(x) ++#endif ++ ++#ifndef unlikely ++#define CAM_OS_UNLIKELY(x) __builtin_expect(!!(x), 0) ++#else ++#define CAM_OS_UNLIKELY(x) unlikely(x) ++#endif ++ ++static FORCE_INLINE s32 CAM_OS_FLS(s32 x) ++{ ++ int r = 32; ++ ++ if (!x) ++ return 0; ++ if (!(x & 0xffff0000u)) { ++ x <<= 16; ++ r -= 16; ++ } ++ if (!(x & 0xff000000u)) { ++ x <<= 8; ++ r -= 8; ++ } ++ if (!(x & 0xf0000000u)) { ++ x <<= 4; ++ r -= 4; ++ } ++ if (!(x & 0xc0000000u)) { ++ x <<= 2; ++ r -= 2; ++ } ++ if (!(x & 0x80000000u)) { ++ x <<= 1; ++ r -= 1; ++ } ++ return r; ++} ++ ++#if CAM_OS_BITS_PER_LONG == 32 ++static FORCE_INLINE s32 CAM_OS_FLS64(u64 x) ++{ ++ u32 h = x >> 32; ++ if (h) ++ return CAM_OS_FLS(h) + 32; ++ return CAM_OS_FLS(x); ++} ++#elif CAM_OS_BITS_PER_LONG == 64 ++static FORCE_INLINE s32 _CAM_OS_FLS(u64 word) ++{ ++ s32 num = CAM_OS_BITS_PER_LONG - 1; ++ ++//#if CAM_OS_BITS_PER_LONG == 64 ++ if (!(word & (~0ul << 32))) { ++ num -= 32; ++ word <<= 32; ++ } ++//#endif ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-16)))) { ++ num -= 16; ++ word <<= 16; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-8)))) { ++ num -= 8; ++ word <<= 8; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-4)))) { ++ num -= 4; ++ word <<= 4; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-2)))) { ++ num -= 2; ++ word <<= 2; ++ } ++ if (!(word & (~0ul << (CAM_OS_BITS_PER_LONG-1)))) ++ num -= 1; ++ return num; ++} ++ ++static FORCE_INLINE s32 CAM_OS_FLS64(u64 x) ++{ ++ if (x == 0) ++ return 0; ++ return _CAM_OS_FLS(x) + 1; ++} ++#else ++#error CAM_OS_BITS_PER_LONG not 32 or 64 ++#endif ++ ++#define CAM_OS_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#define CAM_OS_MIN(a,b) (((a)<(b))?(a):(b)) ++#define CAM_OS_MAX(a,b) (((a)>(b))?(a):(b)) ++ ++#endif //__CAM_OS_UTIL_H__ +diff --git a/drivers/sstar/include/cam_os_util_bitmap.h b/drivers/sstar/include/cam_os_util_bitmap.h +new file mode 100644 +index 000000000000..9b9b1a181086 +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util_bitmap.h +@@ -0,0 +1,121 @@ ++/* ++* cam_os_util_bitmap.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_BITMAP_H__ ++#define __CAM_OS_UTIL_BITMAP_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define CAM_OS_BIT_MASK(nr) (1UL << ((nr) % CAM_OS_BITS_PER_LONG)) ++#define CAM_OS_BIT_WORD(nr) ((nr) / CAM_OS_BITS_PER_LONG) ++#define CAM_OS_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++#define CAM_OS_BITS_TO_LONGS(nr) CAM_OS_DIV_ROUND_UP(nr, CAM_OS_BITS_PER_LONG) ++ ++#define CAM_OS_DECLARE_BITMAP(name,bits) \ ++ unsigned long name[CAM_OS_BITS_TO_LONGS(bits)] ++ ++#define CAM_OS_BITMAP_CLEAR(name) do { \ ++ memset((name), 0, sizeof(name)); \ ++} while (0) ++ ++unsigned long _CamOsFindFirstZeroBit(unsigned long *pAddr, unsigned long nSize, ++ unsigned long nOffset); ++#define CAM_OS_FIND_FIRST_ZERO_BIT(p,sz) _CamOsFindFirstZeroBit(p,sz,0) ++#define CAM_OS_FIND_NEXT_ZERO_BIT(p,sz,of) _CamOsFindFirstZeroBit(p,sz,of) ++ ++static inline int CAM_OS_FFS(unsigned long x) ++{ ++ return CAM_OS_FLS(x & -x); ++} ++ ++static inline unsigned long _CAM_OS_FFS(unsigned long x) ++{ ++ return CAM_OS_FFS(x) - 1; ++} ++ ++#define CAM_OS_FFZ(x) _CAM_OS_FFS( ~(x) ) ++ ++/* WARNING: bitmap operation is non atomic */ ++static inline void CAM_OS_SET_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ ++ *p |= mask; ++} ++ ++static inline void CAM_OS_CLEAR_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ ++ *p &= ~mask; ++} ++ ++static inline void CAM_OS_CHANGE_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ ++ *p ^= mask; ++} ++ ++static inline s32 CAM_OS_TEST_AND_SET_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ volatile unsigned long old = *p; ++ ++ *p = old | mask; ++ return (old & mask) != 0; ++} ++ ++static inline s32 CAM_OS_TEST_AND_CLEAR_BIT(s32 nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ volatile unsigned long old = *p; ++ ++ *p = old & ~mask; ++ return (old & mask) != 0; ++} ++ ++static inline s32 CAM_OS_TEST_AND_CHANGE_BIT(s32 nr, ++ volatile unsigned long *addr) ++{ ++ unsigned long mask = CAM_OS_BIT_MASK(nr); ++ volatile unsigned long *p = (addr) + CAM_OS_BIT_WORD(nr); ++ volatile unsigned long old = *p; ++ ++ *p = old ^ mask; ++ return (old & mask) != 0; ++} ++ ++static inline s32 CAM_OS_TEST_BIT(s32 nr, const volatile unsigned long *addr) ++{ ++ return 1UL & (addr[CAM_OS_BIT_WORD(nr)] >> (nr & (CAM_OS_BITS_PER_LONG-1))); ++} ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_BITMAP_H__ +diff --git a/drivers/sstar/include/cam_os_util_bug.h b/drivers/sstar/include/cam_os_util_bug.h +new file mode 100644 +index 000000000000..e537778b3684 +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util_bug.h +@@ -0,0 +1,47 @@ ++/* ++* cam_os_util_bug.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_BUG_H__ ++#define __CAM_OS_UTIL_BUG_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define CAM_OS_BUG() do { \ ++ CamOsPrintf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ ++ CamOsPanic("BUG!"); \ ++} while (0) ++ ++#define CAM_OS_BUG_ON(condition) do { if (unlikely(condition)) CAM_OS_BUG(); } while (0) ++ ++#define CAM_OS_MAX_ERRNO 4096 ++#define CAM_OS_IS_ERR_VALUE(x) CAM_OS_UNLIKELY((x) >= (unsigned long)-CAM_OS_MAX_ERRNO) ++ ++#define CAM_OS_ERR_PTR(x) (void *)(x) ++ ++#define CAM_OS_PTR_ERR(x) (long)(x) ++ ++#define CAM_OS_IS_ERR(x) CAM_OS_IS_ERR_VALUE((unsigned long)(x)) ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_BUG_H__ +diff --git a/drivers/sstar/include/cam_os_util_hash.h b/drivers/sstar/include/cam_os_util_hash.h +new file mode 100644 +index 000000000000..1359f6eb839d +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util_hash.h +@@ -0,0 +1,98 @@ ++/* ++* cam_os_util_hash.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_HASH_H__ ++#define __CAM_OS_UTIL_HASH_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++static inline __attribute__((const)) ++s32 _CAM_OS_ILOG2_U32(u32 n) ++{ ++ return CAM_OS_FLS(n) - 1; ++} ++ ++static inline __attribute__((const)) ++s32 _CAM_OS_ILOG2_U64(u64 n) ++{ ++ return CAM_OS_FLS64(n) - 1; ++} ++ ++#define CAM_OS_ILOG2(n) \ ++( \ ++ __builtin_constant_p(n) ? ( \ ++ (n) < 1 ? 0 : \ ++ (n) & (1ULL << 63) ? 63 : (n) & (1ULL << 62) ? 62 : (n) & (1ULL << 61) ? 61 : (n) & (1ULL << 60) ? 60 : \ ++ (n) & (1ULL << 59) ? 59 : (n) & (1ULL << 58) ? 58 : (n) & (1ULL << 57) ? 57 : (n) & (1ULL << 56) ? 56 : \ ++ (n) & (1ULL << 55) ? 55 : (n) & (1ULL << 54) ? 54 : (n) & (1ULL << 53) ? 53 : (n) & (1ULL << 52) ? 52 : \ ++ (n) & (1ULL << 51) ? 51 : (n) & (1ULL << 50) ? 50 : (n) & (1ULL << 49) ? 49 : (n) & (1ULL << 48) ? 48 : \ ++ (n) & (1ULL << 47) ? 47 : (n) & (1ULL << 46) ? 46 : (n) & (1ULL << 45) ? 45 : (n) & (1ULL << 44) ? 44 : \ ++ (n) & (1ULL << 43) ? 43 : (n) & (1ULL << 42) ? 42 : (n) & (1ULL << 41) ? 41 : (n) & (1ULL << 40) ? 40 : \ ++ (n) & (1ULL << 39) ? 39 : (n) & (1ULL << 38) ? 38 : (n) & (1ULL << 37) ? 37 : (n) & (1ULL << 36) ? 36 : \ ++ (n) & (1ULL << 35) ? 35 : (n) & (1ULL << 34) ? 34 : (n) & (1ULL << 33) ? 33 : (n) & (1ULL << 32) ? 32 : \ ++ (n) & (1ULL << 31) ? 31 : (n) & (1ULL << 30) ? 30 : (n) & (1ULL << 29) ? 29 : (n) & (1ULL << 28) ? 28 : \ ++ (n) & (1ULL << 27) ? 27 : (n) & (1ULL << 26) ? 26 : (n) & (1ULL << 25) ? 25 : (n) & (1ULL << 24) ? 24 : \ ++ (n) & (1ULL << 23) ? 23 : (n) & (1ULL << 22) ? 22 : (n) & (1ULL << 21) ? 21 : (n) & (1ULL << 20) ? 20 : \ ++ (n) & (1ULL << 19) ? 19 : (n) & (1ULL << 18) ? 18 : (n) & (1ULL << 17) ? 17 : (n) & (1ULL << 16) ? 16 : \ ++ (n) & (1ULL << 15) ? 15 : (n) & (1ULL << 14) ? 14 : (n) & (1ULL << 13) ? 13 : (n) & (1ULL << 12) ? 12 : \ ++ (n) & (1ULL << 11) ? 11 : (n) & (1ULL << 10) ? 10 : (n) & (1ULL << 9) ? 9 : (n) & (1ULL << 8) ? 8 : \ ++ (n) & (1ULL << 7) ? 7 : (n) & (1ULL << 6) ? 6 : (n) & (1ULL << 5) ? 5 : (n) & (1ULL << 4) ? 4 : \ ++ (n) & (1ULL << 3) ? 3 : (n) & (1ULL << 2) ? 2 : (n) & (1ULL << 1) ? 1 : (n) & (1ULL << 0) ? 0 : \ ++ 0) : \ ++ (sizeof(n) <= 4) ? \ ++ _CAM_OS_ILOG2_U32(n) : \ ++ _CAM_OS_ILOG2_U64(n) \ ++ ) ++ ++#define CAM_OS_HASH_SIZE(name) (CAM_OS_ARRAY_SIZE(name)) ++ ++#define CAM_OS_HASH_BITS(name) CAM_OS_ILOG2(CAM_OS_HASH_SIZE(name)) ++ ++#define CAM_OS_DEFINE_HASHTABLE(name, bits) \ ++ struct CamOsHListHead_t name[1 << (bits)] = \ ++ { [0 ... ((1 << (bits)) - 1)] = CAM_OS_HLIST_HEAD_INIT } ++ ++static inline void _CAM_OS_HASH_INIT(struct CamOsHListHead_t *ht, unsigned int sz) ++{ ++ u32 i; ++ ++ for (i = 0; i < sz; i++) ++ CAM_OS_INIT_HLIST_HEAD(&ht[i]); ++} ++ ++#define CAM_OS_HASH_INIT(hashtable) _CAM_OS_HASH_INIT(hashtable, CAM_OS_HASH_SIZE(hashtable)) ++ ++#define CAM_OS_HASH_ADD(hashtable, node, key) \ ++ CAM_OS_HLIST_ADD_HEAD(node, &hashtable[CAM_OS_HASH_MIN(key, CAM_OS_HASH_BITS(hashtable))]) ++ ++#define CAM_OS_HASH_FOR_EACH_POSSIBLE(name, obj, member, key) \ ++ CAM_OS_HLIST_FOR_EACH_ENTRY(obj, &name[CAM_OS_HASH_MIN(key, CAM_OS_HASH_BITS(name))], member) ++ ++static inline void CAM_OS_HASH_DEL(struct CamOsHListNode_t *node) ++{ ++ CAM_OS_HLIST_DEL_INIT(node); ++} ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_HASH_H__ +diff --git a/drivers/sstar/include/cam_os_util_ioctl.h b/drivers/sstar/include/cam_os_util_ioctl.h +new file mode 100644 +index 000000000000..8eebabdcaeec +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util_ioctl.h +@@ -0,0 +1,83 @@ ++/* ++* cam_os_util_ioctl.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_IOCTL_H__ ++#define __CAM_OS_UTIL_IOCTL_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define CAM_OS_IOC_NRBITS 8 ++#define CAM_OS_IOC_TYPEBITS 8 ++ ++#define CAM_OS_IOC_SIZEBITS 14 ++ ++#define CAM_OS_IOC_DIRBITS 2 ++ ++#define CAM_OS_IOC_NRMASK ((1 << CAM_OS_IOC_NRBITS)-1) ++#define CAM_OS_IOC_TYPEMASK ((1 << CAM_OS_IOC_TYPEBITS)-1) ++#define CAM_OS_IOC_SIZEMASK ((1 << CAM_OS_IOC_SIZEBITS)-1) ++#define CAM_OS_IOC_DIRMASK ((1 << CAM_OS_IOC_DIRBITS)-1) ++ ++#define CAM_OS_IOC_NRSHIFT 0 ++#define CAM_OS_IOC_TYPESHIFT (CAM_OS_IOC_NRSHIFT+CAM_OS_IOC_NRBITS) ++#define CAM_OS_IOC_SIZESHIFT (CAM_OS_IOC_TYPESHIFT+CAM_OS_IOC_TYPEBITS) ++#define CAM_OS_IOC_DIRSHIFT (CAM_OS_IOC_SIZESHIFT+CAM_OS_IOC_SIZEBITS) ++ ++#define CAM_OS_IOC_NONE 0U ++#define CAM_OS_IOC_WRITE 1U ++#define CAM_OS_IOC_READ 2U ++ ++#define CAM_OS_IOC(dir,type,nr,size) \ ++ (((dir) << CAM_OS_IOC_DIRSHIFT) | \ ++ ((type) << CAM_OS_IOC_TYPESHIFT) | \ ++ ((nr) << CAM_OS_IOC_NRSHIFT) | \ ++ ((size) << CAM_OS_IOC_SIZESHIFT)) ++ ++#define CAM_OS_IOC_TYPECHECK(t) (sizeof(t)) ++ ++/* used to create numbers */ ++#define CAM_OS_IO(type,nr) CAM_OS_IOC(CAM_OS_IOC_NONE,(type),(nr),0) ++#define CAM_OS_IOR(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ,(type),(nr),(CAM_OS_IOC_TYPECHECK(size))) ++#define CAM_OS_IOW(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_WRITE,(type),(nr),(CAM_OS_IOC_TYPECHECK(size))) ++#define CAM_OS_IOWR(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ|CAM_OS_IOC_WRITE,(type),(nr),(CAM_OS_IOC_TYPECHECK(size))) ++#define CAM_OS_IOR_BAD(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ,(type),(nr),sizeof(size)) ++#define CAM_OS_IOW_BAD(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_WRITE,(type),(nr),sizeof(size)) ++#define CAM_OS_IOWR_BAD(type,nr,size) CAM_OS_IOC(CAM_OS_IOC_READ|CAM_OS_IOC_WRITE,(type),(nr),sizeof(size)) ++ ++/* used to decode ioctl numbers.. */ ++#define CAM_OS_IOC_DIR(nr) (((nr) >> CAM_OS_IOC_DIRSHIFT) & CAM_OS_IOC_DIRMASK) ++#define CAM_OS_IOC_TYPE(nr) (((nr) >> CAM_OS_IOC_TYPESHIFT) & CAM_OS_IOC_TYPEMASK) ++#define CAM_OS_IOC_NR(nr) (((nr) >> CAM_OS_IOC_NRSHIFT) & CAM_OS_IOC_NRMASK) ++#define CAM_OS_IOC_SIZE(nr) (((nr) >> CAM_OS_IOC_SIZESHIFT) & CAM_OS_IOC_SIZEMASK) ++ ++/* ...and for the drivers/sound files... */ ++ ++#define CAM_OS_IOC_IN (CAM_OS_IOC_WRITE << CAM_OS_IOC_DIRSHIFT) ++#define CAM_OS_IOC_OUT (CAM_OS_IOC_READ << CAM_OS_IOC_DIRSHIFT) ++#define CAM_OS_IOC_INOUT ((CAM_OS_IOC_WRITE|CAM_OS_IOC_READ) << CAM_OS_IOC_DIRSHIFT) ++#define CAM_OS_IOCSIZE_MASK (CAM_OS_IOC_SIZEMASK << CAM_OS_IOC_SIZESHIFT) ++#define CAM_OS_IOCSIZE_SHIFT (CAM_OS_IOC_SIZESHIFT) ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_IOCTL_H__ +diff --git a/drivers/sstar/include/cam_os_util_list.h b/drivers/sstar/include/cam_os_util_list.h +new file mode 100644 +index 000000000000..e8f8eb234b9a +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util_list.h +@@ -0,0 +1,308 @@ ++/* ++* cam_os_util_list.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_LIST_H__ ++#define __CAM_OS_UTIL_LIST_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++// List API ++struct CamOsListHead_t ++{ ++ struct CamOsListHead_t *pNext, *pPrev; ++}; ++ ++ ++#define CAM_OS_POISON_POINTER_DELTA 0 ++#define CAM_OS_LIST_POISON1 (void *)(0x00100100 + CAM_OS_POISON_POINTER_DELTA) ++#define CAM_OS_LIST_POISON2 (void *)(0x00200200 + CAM_OS_POISON_POINTER_DELTA) ++ ++#define CAM_OS_LIST_HEAD_INIT(name) { &(name), &(name) } ++ ++#define CAM_OS_LIST_HEAD(name) \ ++ struct CamOsListHead_t name = CAM_OS_LIST_HEAD_INIT(name) ++ ++#define CAM_OS_LIST_ENTRY(ptr, type, member) \ ++ CAM_OS_CONTAINER_OF(ptr, type, member) ++ ++#define CAM_OS_LIST_FOR_EACH(pos, head) \ ++ for (pos = (head)->pNext; pos != (head); pos = pos->pNext) ++ ++#define CAM_OS_LIST_FOR_EACH_SAFE(pos, n, head) \ ++ for (pos = (head)->pNext, n = pos->pNext; pos != (head); \ ++ pos = n, n = pos->pNext) ++ ++#define CAM_OS_LIST_FIRST_ENTRY(ptr, type, member) \ ++ CAM_OS_LIST_ENTRY((ptr)->pNext, type, member) ++ ++#define CAM_OS_LIST_LAST_ENTRY(ptr, type, member) \ ++ CAM_OS_LIST_ENTRY((ptr)->pPrev, type, member) ++ ++#define CAM_OS_LIST_NEXT_ENTRY(pos, member) \ ++ CAM_OS_LIST_ENTRY((pos)->member.pNext, __typeof__(*(pos)), member) ++ ++#define CAM_OS_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member) \ ++ for (pos = CAM_OS_LIST_FIRST_ENTRY(head, __typeof__(*pos), member), \ ++ n = CAM_OS_LIST_NEXT_ENTRY(pos, member); \ ++ &pos->member != (head); \ ++ pos = n, n = CAM_OS_LIST_NEXT_ENTRY(n, member)) ++ ++#define CAM_OS_LIST_FOR_EACH_ENTRY(pos, head, member) \ ++ for (pos = CAM_OS_LIST_FIRST_ENTRY(head, __typeof__(*pos), member); \ ++ &pos->member != (head); \ ++ pos = CAM_OS_LIST_NEXT_ENTRY(pos, member)) ++ ++ ++ static inline void CAM_OS_INIT_LIST_HEAD(struct CamOsListHead_t *pList) ++ { ++ pList->pNext = pList; ++ pList->pPrev = pList; ++ } ++ ++ static inline void _CAM_OS_LIST_ADD(struct CamOsListHead_t *pNew, ++ struct CamOsListHead_t *pPrev, ++ struct CamOsListHead_t *pNext) ++ { ++ pNext->pPrev = pNew; ++ pNew->pNext = pNext; ++ pNew->pPrev = pPrev; ++ pPrev->pNext = pNew; ++ } ++ ++ static inline void CAM_OS_LIST_ADD(struct CamOsListHead_t *pNew, struct CamOsListHead_t *head) ++ { ++ _CAM_OS_LIST_ADD(pNew, head, head->pNext); ++ } ++ ++ ++ static inline void CAM_OS_LIST_ADD_TAIL(struct CamOsListHead_t *pNew, struct CamOsListHead_t *head) ++ { ++ _CAM_OS_LIST_ADD(pNew, head->pPrev, head); ++ } ++ ++ static inline void _CAM_OS_LIST_DEL(struct CamOsListHead_t * pPrev, struct CamOsListHead_t * pNext) ++ { ++ pNext->pPrev = pPrev; ++ pPrev->pNext = pNext; ++ } ++ ++ static inline void _CAM_OS_LIST_DEL_ENTRY(struct CamOsListHead_t *entry) ++ { ++ _CAM_OS_LIST_DEL(entry->pPrev, entry->pNext); ++ } ++ ++ ++ static inline void CAM_OS_LIST_DEL(struct CamOsListHead_t *pEntry) ++ { ++ _CAM_OS_LIST_DEL(pEntry->pPrev, pEntry->pNext); ++ pEntry->pNext = (struct CamOsListHead_t *)CAM_OS_LIST_POISON1; ++ pEntry->pPrev = (struct CamOsListHead_t *)CAM_OS_LIST_POISON2; ++ } ++ ++ static inline void CAM_OS_LIST_DEL_INIT(struct CamOsListHead_t *entry) ++ { ++ _CAM_OS_LIST_DEL_ENTRY(entry); ++ CAM_OS_INIT_LIST_HEAD(entry); ++ } ++ ++ static inline int CAM_OS_LIST_IS_LAST(const struct CamOsListHead_t *list, ++ const struct CamOsListHead_t *head) ++ { ++ return list->pNext == head; ++ } ++ ++ static inline int CAM_OS_LIST_EMPTY(const struct CamOsListHead_t *head) ++ { ++ return head->pNext == head; ++ } ++ ++ static inline int CAM_OS_LIST_EMPTY_CAREFUL(const struct CamOsListHead_t *head) ++ { ++ struct CamOsListHead_t *pNext = head->pNext; ++ return (pNext == head) && (pNext == head->pPrev); ++ } ++ ++ ++void CamOsListSort(void *priv, struct CamOsListHead_t *head, ++ int (*cmp)(void *priv, struct CamOsListHead_t *a, ++ struct CamOsListHead_t *b)); ++ ++#pragma GCC diagnostic push ++#pragma GCC diagnostic ignored "-Wcast-qual" ++// HList API ++static FORCE_INLINE ++void _CAM_OS_READ_ONCE_SIZE(const volatile void *p, void *res, int size) ++{ ++ switch (size) { ++ case 1: *(u8 *)res = *(volatile u8 *)p; break; ++ case 2: *(u16 *)res = *(volatile u16 *)p; break; ++ case 4: *(u32 *)res = *(volatile u32 *)p; break; ++ case 8: *(u64 *)res = *(volatile u64 *)p; break; ++ default: ++ asm volatile("": : :"memory"); // barrier() ++ __builtin_memcpy((void *)res, (const void *)p, size); ++ asm volatile("": : :"memory"); // barrier() ++ } ++} ++#pragma GCC diagnostic pop ++ ++#define CAM_OS_READ_ONCE(x) \ ++({ \ ++ union { __typeof__(x) __val; char __c[1]; } __u = {0}; \ ++ _CAM_OS_READ_ONCE_SIZE(&(x), __u.__c, sizeof(x)); \ ++ __u.__val; \ ++}) ++ ++#pragma GCC diagnostic push ++#pragma GCC diagnostic ignored "-Wcast-qual" ++static FORCE_INLINE void _CAM_OS_WRITE_ONCE_SIZE(volatile void *p, void *res, int size) ++{ ++ switch (size) { ++ case 1: *(volatile u8 *)p = *(u8 *)res; break; ++ case 2: *(volatile u16 *)p = *(u16 *)res; break; ++ case 4: *(volatile u32 *)p = *(u32 *)res; break; ++ case 8: *(volatile u64 *)p = *(u64 *)res; break; ++ default: ++ asm volatile("": : :"memory"); // barrier() ++ __builtin_memcpy((void *)p, (const void *)res, size); ++ asm volatile("": : :"memory"); // barrier() ++ } ++} ++#pragma GCC diagnostic pop ++ ++#define CAM_OS_WRITE_ONCE(x, val) \ ++({ \ ++ union { struct CamOsHListNode_t * __val; char __c[1]; } __u = \ ++ { .__val = (struct CamOsHListNode_t *) (val) }; \ ++ _CAM_OS_WRITE_ONCE_SIZE(&(x), __u.__c, sizeof(x)); \ ++ __u.__val; \ ++}) ++ ++/* 2^31 + 2^29 - 2^25 + 2^22 - 2^19 - 2^16 + 1 */ ++#define CAM_OS_GOLDEN_RATIO_PRIME_32 0x9e370001UL ++/* 2^63 + 2^61 - 2^57 + 2^54 - 2^51 - 2^18 + 1 */ ++#define CAM_OS_GOLDEN_RATIO_PRIME_64 0x9e37fffffffc0001UL ++ ++#if CAM_OS_BITS_PER_LONG == 32 ++static inline u32 CAM_OS_HASH_32(u32 val, u32 bits) ++{ ++ /* On some cpus multiply is faster, on others gcc will do shifts */ ++ u32 hash = val * CAM_OS_GOLDEN_RATIO_PRIME_32; ++ ++ /* High bits are more random, so use them. */ ++ return hash >> (32 - bits); ++} ++ ++#define CAM_OS_GOLDEN_RATIO_PRIME CAM_OS_GOLDEN_RATIO_PRIME_32 ++#define CAM_OS_HASH_LONG(val, bits) CAM_OS_HASH_32(val, bits) ++#elif CAM_OS_BITS_PER_LONG == 64 ++static FORCE_INLINE uint64_t CAM_OS_HASH_64(u64 val, u32 bits) ++{ ++ u64 hash = val; ++ ++ hash = hash * CAM_OS_GOLDEN_RATIO_PRIME_64; ++ ++ /* High bits are more random, so use them. */ ++ return hash >> (64 - bits); ++} ++ ++#define CAM_OS_HASH_LONG(val, bits) CAM_OS_HASH_64(val, bits) ++#define CAM_OS_GOLDEN_RATIO_PRIME CAM_OS_GOLDEN_RATIO_PRIME_64 ++#else ++#error CAM_OS_BITS_PER_LONG not 32 or 64 ++#endif ++ ++struct CamOsHListHead_t { ++ struct CamOsHListNode_t *pFirst; ++}; ++ ++struct CamOsHListNode_t { ++ struct CamOsHListNode_t *pNext, **ppPrev; ++}; ++ ++#define CAM_OS_HLIST_HEAD_INIT { .pFirst = NULL } ++#define CAM_OS_HLIST_HEAD(name) struct CamOsHListHead_t name = { .pFirst = NULL } ++#define CAM_OS_INIT_HLIST_HEAD(ptr) ((ptr)->pFirst = NULL) ++ ++#define CAM_OS_HASH_MIN(val, bits) \ ++ (sizeof(val) <= 4 ? CAM_OS_HASH_32(val, bits) : CAM_OS_HASH_LONG(val, bits)) ++ ++static inline void CAM_OS_INIT_HLIST_NODE(struct CamOsHListNode_t *h) ++{ ++ h->pNext = NULL; ++ h->ppPrev = NULL; ++} ++ ++static inline int CAM_OS_HLIST_UNHASHED(const struct CamOsHListNode_t *h) ++{ ++ return !h->ppPrev; ++} ++ ++static inline int CAM_OS_HLIST_EMPTY(const struct CamOsHListHead_t *h) ++{ ++ return !CAM_OS_READ_ONCE(h->pFirst); ++} ++ ++static inline void _CAM_OS_HLIST_DEL(struct CamOsHListNode_t *n) ++{ ++ struct CamOsHListNode_t *pNext = n->pNext; ++ struct CamOsHListNode_t **ppPrev = n->ppPrev; ++ ++ CAM_OS_WRITE_ONCE(*ppPrev, pNext); ++ if (pNext) ++ pNext->ppPrev = ppPrev; ++} ++ ++static inline void CAM_OS_HLIST_DEL_INIT(struct CamOsHListNode_t *n) ++{ ++ if (!CAM_OS_HLIST_UNHASHED(n)) { ++ _CAM_OS_HLIST_DEL(n); ++ CAM_OS_INIT_HLIST_NODE(n); ++ } ++} ++ ++static inline void CAM_OS_HLIST_ADD_HEAD(struct CamOsHListNode_t *n, struct CamOsHListHead_t *h) ++{ ++ struct CamOsHListNode_t *pFirst = h->pFirst; ++ n->pNext = pFirst; ++ if (pFirst) ++ pFirst->ppPrev = &n->pNext; ++ h->pFirst = n; ++ n->ppPrev = &h->pFirst; ++} ++ ++#define CAM_OS_HLIST_ENTRY(ptr, type, member) CAM_OS_CONTAINER_OF(ptr,type,member) ++ ++#define CAM_OS_HLIST_ENTRY_SAFE(ptr, type, member) \ ++ ({ __typeof__(ptr) ____ptr = (ptr); \ ++ ____ptr ? CAM_OS_HLIST_ENTRY(____ptr, type, member) : NULL; \ ++ }) ++ ++#define CAM_OS_HLIST_FOR_EACH_ENTRY(pos, head, member) \ ++ for (pos = CAM_OS_HLIST_ENTRY_SAFE((head)->pFirst, __typeof__(*(pos)), member);\ ++ pos; \ ++ pos = CAM_OS_HLIST_ENTRY_SAFE((pos)->member.pNext, __typeof__(*(pos)), member)) ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_LIST_H__ +diff --git a/drivers/sstar/include/cam_os_util_string.h b/drivers/sstar/include/cam_os_util_string.h +new file mode 100755 +index 000000000000..3e1b3883c435 +--- /dev/null ++++ b/drivers/sstar/include/cam_os_util_string.h +@@ -0,0 +1,82 @@ ++/* ++* cam_os_util_string.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++#ifndef __CAM_OS_UTIL_STRING_H__ ++#define __CAM_OS_UTIL_STRING_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#if defined(__KERNEL__) ++#include "linux/kernel.h" ++#include "linux/string.h" ++#include "linux/sort.h" ++#else ++#include "string.h" ++#include "stdlib.h" ++#include "stdio.h" ++#endif ++ ++#if defined(__KERNEL__) ++#define atoi(s) simple_strtol(s, NULL, 10) ++#define qsort(b,n,s,c) sort(b,n,s,c,NULL) ++#endif ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#ifndef KERN_SOH ++#define KERN_SOH "\001" /* ASCII Start Of Header */ ++#endif ++ ++#ifndef KERN_EMERG ++#define KERN_EMERG KERN_SOH "0" /* system is unusable */ ++#endif ++ ++#ifndef KERN_ALERT ++#define KERN_ALERT KERN_SOH "1" /* action must be taken immediately */ ++#endif ++ ++#ifndef KERN_CRIT ++#define KERN_CRIT KERN_SOH "2" /* critical conditions */ ++#endif ++ ++#ifndef KERN_ERR ++#define KERN_ERR KERN_SOH "3" /* error conditions */ ++#endif ++ ++#ifndef KERN_WARNING ++#define KERN_WARNING KERN_SOH "4" /* warning conditions */ ++#endif ++ ++#ifndef KERN_NOTICE ++#define KERN_NOTICE KERN_SOH "5" /* normal but significant condition */ ++#endif ++ ++#ifndef KERN_INFO ++#define KERN_INFO KERN_SOH "6" /* informational */ ++#endif ++ ++#ifndef KERN_DEBUG ++#define KERN_DEBUG KERN_SOH "7" /* debug-level messages */ ++#endif ++ ++#endif //__CAM_OS_UTIL_STRING_H__ +diff --git a/drivers/sstar/include/cam_os_wrapper.h b/drivers/sstar/include/cam_os_wrapper.h +new file mode 100644 +index 000000000000..e1a591a844c2 +--- /dev/null ++++ b/drivers/sstar/include/cam_os_wrapper.h +@@ -0,0 +1,1779 @@ ++/* ++* cam_os_wrapper.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.h ++/// @brief Cam OS Wrapper Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_OS_WRAPPER_H__ ++#define __CAM_OS_WRAPPER_H__ ++ ++#define CAM_OS_WRAPPER_VERSION "v1.0.35" ++ ++#if defined(__aarch64__) ++#define CAM_OS_BITS_PER_LONG 64 ++#else ++#define CAM_OS_BITS_PER_LONG 32 ++#endif ++ ++#ifndef NULL ++#define NULL 0 ++#endif ++ ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++#include "cam_os_util.h" ++#include "cam_os_util_list.h" ++#include "cam_os_util_bug.h" ++#include "cam_os_util_hash.h" ++#include "cam_os_util_bitmap.h" ++#include "cam_os_util_ioctl.h" ++#include "cam_os_util_string.h" ++ ++#define CAM_OS_MAX_TIMEOUT ((u32)(~0U)) ++#define CAM_OS_MAX_INT ((s32)(~0U>>1)) ++ ++typedef enum ++{ ++ CAM_OS_OK = 0, ++ CAM_OS_FAIL = -1, ++ CAM_OS_PARAM_ERR = -2, ++ CAM_OS_ALLOCMEM_FAIL = -3, ++ CAM_OS_TIMEOUT = -4, ++ CAM_OS_RESOURCE_BUSY = -5, ++ CAM_OS_INTERRUPTED = -6, ++} CamOsRet_e; ++ ++typedef enum ++{ ++ CAM_OS_MEM_1MB = 0, ++ CAM_OS_MEM_2MB = 1, ++ CAM_OS_MEM_4MB = 2, ++ CAM_OS_MEM_8MB = 3, ++ CAM_OS_MEM_16MB = 4, ++ CAM_OS_MEM_32MB = 5, ++ CAM_OS_MEM_64MB = 6, ++ CAM_OS_MEM_128MB = 7, ++ CAM_OS_MEM_256MB = 8, ++ CAM_OS_MEM_512MB = 9, ++ CAM_OS_MEM_1024MB = 10, ++ CAM_OS_MEM_UNKNOWN = 99, ++} CamOsMemSize_e; ++ ++typedef enum ++{ ++ CAM_OS_TIME_DIFF_SEC = 0, ++ CAM_OS_TIME_DIFF_MS = 1, ++ CAM_OS_TIME_DIFF_US = 2, ++ CAM_OS_TIME_DIFF_NS = 3, ++} CamOsTimeDiffUnit_e; ++ ++typedef struct ++{ ++ u32 nPriv[11]; ++} CamOsMutex_t; ++ ++typedef struct ++{ ++ u32 nPriv[16]; ++} CamOsTsem_t; ++ ++typedef struct ++{ ++ u32 nPriv[20]; ++} CamOsRwsem_t; ++ ++typedef struct ++{ ++ u32 nPriv[20]; ++} CamOsTcond_t; ++ ++typedef struct ++{ ++ u32 nPriv[6]; ++}CamOsSpinlock_t; ++ ++typedef struct ++{ ++ u32 nSec; ++ u32 nNanoSec; ++} CamOsTimespec_t; ++ ++typedef struct ++{ ++ u32 nPriority; /* From 1(lowest) to 99(highest), use OS default priority if set 0 */ ++ u32 nStackSize; /* If nStackSize is zero, use OS default value */ ++ char *szName; ++} CamOsThreadAttrb_t, *pCamOsThreadAttrb; ++ ++typedef struct ++{ ++ u32 nPriv[8]; ++} CamOsTimer_t; ++ ++typedef struct ++{ ++ u32 nPriv[2]; ++} CamOsMemCache_t; ++ ++typedef struct ++{ ++ volatile s32 nCounter; ++} CamOsAtomic_t; ++ ++typedef struct ++{ ++ u32 nPriv[20]; ++} CamOsIdr_t; ++ ++typedef struct ++{ ++ u32 nBytes; ++ u16 nType; ++ u16 nBusWidth; ++} CamOsDramInfo_t; ++ ++typedef void * CamOsThread; ++ ++typedef void (*CamOsIrqHandler)(u32 nIrq, void *pDevId); ++ ++//============================================================================= ++// Description: ++// Get cam_os_wrapper version with C string format. ++// Parameters: ++// N/A ++// Return: ++// C string type of version information. ++//============================================================================= ++char *CamOsVersion(void); ++ ++//============================================================================= ++// Description: ++// Writes the C string pointed by format to the standard output. ++// Parameters: ++// [in] szFmt: C string that contains the text to be written, it can ++// optionally contain embedded format specifiers. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPrintf(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Writes the C string pointed without format to the standard output. ++// Parameters: ++// [in] szStr: C string that contains the text to be written. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPrintString(const char *szStr); ++ ++//============================================================================= ++// Description: ++// Reads data from stdin and stores them according to the parameter format ++// into the locations pointed by the additional arguments. ++// Parameters: ++// [in] szFmt: C string that contains the text to be parsing, it can ++// optionally contain embedded format specifiers. ++// Return: ++// The number of items of the argument list successfully filled. ++//============================================================================= ++s32 CamOsScanf(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Returns the next character from the standard input. ++// Parameters: ++// N/A ++// Return: ++// the character read is returned. ++//============================================================================= ++s32 CamOsGetChar(void); ++ ++//============================================================================= ++// Description: ++// Reads data from stdin and stores them according to the parameter format ++// into the locations pointed by the additional arguments. ++// Parameters: ++// [in] szBuf: Pointer to a buffer where the resulting C-string is stored. ++// The buffer should have a size of at least nSize characters. ++// [in] nSize: Maximum number of bytes to be used in the buffer. ++// The generated string has a length of at most nSize-1, ++// leaving space for the additional terminating null character. ++// [in] szFmt: C string that contains a format string, it can optionally ++// contain embedded format specifiers. ++// Return: ++// The number of items of the argument list successfully filled. ++//============================================================================= ++s32 CamOsSnprintf(char *szBuf, u32 nSize, const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Display the input offset in hexadecimal ++// Parameters: ++// [in] szBuf: Pointer to a buffer. ++// [in] nSize: Interpret only length bytes of input. ++// Return: ++// N/A ++//============================================================================= ++void CamOsHexdump(char *szBuf, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Suspend execution for millisecond intervals. ++// In Linux, sleeping for larger msecs(10ms+). ++// Parameters: ++// [in] nMsec: Millisecond to suspend. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMsSleep(u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Suspend execution for microsecond intervals. ++// In Linux, sleeping for ~usecs or small msecs(10us~20ms). ++// Parameters: ++// [in] nUsec: Microsecond to suspend. ++// Return: ++// N/A ++//============================================================================= ++void CamOsUsSleep(u32 nUsec); ++ ++//============================================================================= ++// Description: ++// Busy-delay execution for millisecond intervals. ++// Parameters: ++// [in] nMsec: Millisecond to busy-delay. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMsDelay(u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Busy-delay execution for microsecond intervals. ++// Parameters: ++// [in] nUsec: Microsecond to busy-delay. ++// Return: ++// N/A ++//============================================================================= ++void CamOsUsDelay(u32 nUsec); ++ ++//============================================================================= ++// Description: ++// Get the number of seconds and nanoseconds since the Epoch. ++// Parameters: ++// [out] ptRes: A pointer to a CamOsTimespec_t structure where ++// CamOsGetTimeOfDay() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetTimeOfDay(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Set the number of seconds and nanoseconds since the Epoch. ++// Parameters: ++// [in] ptRes: A pointer to a CamOsTimespec_t structure. ++// Return: ++// N/A ++//============================================================================= ++void CamOsSetTimeOfDay(const CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Gets the current time of the clock specified, and puts it into the ++// buffer pointed to by ptRes. ++// Parameters: ++// [out] ptRes: A pointer to a CamOsTimespec_t structure where ++// CamOsGetMonotonicTime() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Subtracts ptEnd from ptStart ++// Parameters: ++// [in] ptStart: A pointer to a CamOsTimespec_t structure store the start time. ++// [in] ptEnd: A pointer to a CamOsTimespec_t structure store the end time. ++// [in] eUnit: result unit in second, millisecond, microsecond or nanosecond. ++// Return: ++// Difference of ptEnd and ptStart, or return 0 if giving invalid parameter. ++//============================================================================= ++s64 CamOsTimeDiff(CamOsTimespec_t *ptStart, CamOsTimespec_t *ptEnd, CamOsTimeDiffUnit_e eUnit); ++ ++//============================================================================= ++// Description: ++// The CamOsThreadCreate() function is used to create a new thread/task, ++// with attributes specified by ptAttrb. If ptAttrb is NULL, the default ++// attributes are used. ++// Parameters: ++// [out] ptThread: A successful call to CamOsThreadCreate() stores the handle ++// of the new thread. ++// [in] ptAttrb: Argument points to a CamOsThreadAttrb_t structure whose ++// contents are used at thread creation time to determine ++// thread priority, stack size and thread name. Thread ++// priority range from 1(lowest) to 99(highest), use OS ++// default priority if set 0. ++// ------------------------------------------------------------------------ ++// |nPriority| 1 ~ 49 | 50 | 51 ~ 70 | 71 ~ 94 | 95 ~ 99 | ++// ------------------------------------------------------------------------ ++// | Linux |SCHED_OTHER|SCHED_OTHER|SCHED_OTHER| SCHED_RR | SCHED_RR | ++// | | NICE 19~1 | NICE 0 |NICE -1~-20|RTPRIO 1~94|RTPRIO 95~99| ++// ------------------------------------------------------------------------ ++// [in] pfnStartRoutine(): The new thread starts execution by invoking it. ++// [in] pArg: It is passed as the sole argument of pfnStartRoutine(). ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadCreate(CamOsThread *ptThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg); ++ ++//============================================================================= ++// Description: ++// Change priority of a thread created by CamOsThreadCreate. ++// Parameters: ++// [in] pThread: Handle of target thread. ++// [in] nPriority: New priority of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadChangePriority(CamOsThread pThread, u32 nPriority); ++ ++//============================================================================= ++// Description: ++// Schedule out a thread created by CamOsThreadCreate. ++// Parameters: ++// [in] bInterruptible: Setup if schedule method with timeout is ++// interruptible. This parameter is only applicable ++// to Linux kernel space. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadSchedule(u8 bInterruptible, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Wake up the thread specified by pThread to run. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadWakeUp(CamOsThread tThread); ++ ++//============================================================================= ++// Description: ++// Waits for the thread specified by tThread to terminate. If that thread ++// has already terminated, then CamOsThreadJoin() returns immediately. This ++// function is not applicable to Linux kernel space. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadJoin(CamOsThread tThread); ++ ++//============================================================================= ++// Description: ++// Stop a thread created by CamOsThreadCreate in Linux kernel space. This ++// function is not applicable to Linux user space. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadStop(CamOsThread tThread); ++ ++//============================================================================= ++// Description: ++// When someone calls CamOsThreadStop, it will be woken and this will ++// return true. You should then return from the thread. This function is ++// not applicable to Linux user space. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadShouldStop(void); ++ ++//============================================================================= ++// Description: ++// Set the name of a thread. The thread name is a meaningful C language ++// string, whose length is restricted to 16 characters, including the ++// terminating null byte ('\0'). ++// Parameters: ++// [in] tThread: Handle of target thread. ++// [in] szName: specifies the new name. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadSetName(CamOsThread tThread, const char *szName); ++ ++//============================================================================= ++// Description: ++// Get the name of a thread. The buffer specified by name should be at ++// least 16 characters in length. ++// Parameters: ++// [in] tThread: Handle of target thread. ++// [out] szName: Buffer used to return the thread name. ++// [in] nLen: Specifies the number of bytes available in szName ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadGetName(CamOsThread tThread, char *szName, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Get thread identification. ++// Parameters: ++// N/A ++// Return: ++// On success, returns the thread ID of the calling process. ++//============================================================================= ++u32 CamOsThreadGetID(void); ++ ++//============================================================================= ++// Description: ++// Initializes the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Destroys the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Lock the mutex, if mutex isn't initialized, this API will init it ++// automatically. ++// Parameters: ++// [in] ptMutex: The mutex to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Try lock the mutex, and return as non-blocking mode. If mutex isn't ++// initialized, this API will init itautomatically. ++// Parameters: ++// [in] ptMutex: The mutex to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexTryLock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Unlock the mutex, if mutex isn't initialized, this API will init it ++// automatically. ++// Parameters: ++// [in] ptMutex: The mutex to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Initializes the semaphore at a given value. ++// Parameters: ++// [in] ptTsem: The semaphore to initialize. ++// [in] nVal: the initial value of the semaphore. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal); ++ ++//============================================================================= ++// Description: ++// Destroy the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Increases the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to increase. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemUp(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemDown(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. This function is interruptible in Linux kernel. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// N/A ++//============================================================================= ++CamOsRet_e CamOsTsemDownInterruptible(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if down successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Always return as non-blocking mode. Decreases the value of the semaphore ++// if it is bigger than zero. If the semaphore value is less than or equal ++// to zero, return directly. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// CAM_OS_OK is returned if down successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTryDown(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Initializes the rw semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemInit(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Destroys the read-write semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemDeinit(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Unlock the read semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to unlock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemUpRead(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Unlock the write semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to unlock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemUpWrite(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Lock the read semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemDownRead(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Lock the write semaphore. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// N/A ++//============================================================================= ++void CamOsRwsemDownWrite(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Try lock the read semaphore, and return as non-blocking mode. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemTryDownRead(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Try lock the write semaphore, and return as non-blocking mode. ++// Parameters: ++// [in] ptRwsem: The rw semaphore to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsRwsemTryDownWrite(CamOsRwsem_t *ptRwsem); ++ ++//============================================================================= ++// Description: ++// Initializes the condition. ++// Parameters: ++// [in] ptTcond: The condition to Initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondInit(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Destroys the condition. ++// Parameters: ++// [in] ptTcond: The condition to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondDeinit(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Signal the condition, if anyone waiting. ++// Parameters: ++// [in] ptTcond: The condition to signal ++// Return: ++// N/A ++//============================================================================= ++void CamOsTcondSignal(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Signal the condition for all waitings totally. ++// Parameters: ++// [in] ptTcond: The condition to signal ++// Return: ++// N/A ++//============================================================================= ++void CamOsTcondSignalAll(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTcondWait(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if wait successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondTimedWait(CamOsTcond_t *ptTcond, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Wait on the condition(it's interruptible). ++// This API is the same with CamOsTcondSignal in RTK and Linux user space. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// Return: ++// If a signal was received while waiting it will return CAM_OS_INTERRUPTED; ++// CAM_OS_OK is returned if wait successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondWaitInterruptible(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Wait on the condition with time limitation(it's interruptible). ++// This API is the same with CamOsTcondSignal in RTK and Linux user space. ++// Parameters: ++// [in] ptTcond: The condition to wait. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If a signal was received it will return CAM_OS_INTERRUPTED; otherwise ++// it returns CAM_OS_TIMEOUT if the completion timed out or CAM_OS_OK if ++// completion occurred. ++//============================================================================= ++CamOsRet_e CamOsTcondTimedWaitInterruptible(CamOsTcond_t *ptTcond, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Check if any task wait for this condition. ++// This API is not supported to Linux user space. ++// Parameters: ++// [in] ptTcond: The condition to check. ++// Return: ++// If any task waits for this condition, CAM_OS_OK is returned. ++// CAM_OS_FAIL is returned if no one waits; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTcondWaitActive(CamOsTcond_t *ptTcond); ++ ++//============================================================================= ++// Description: ++// Initializes the spinlock. ++// Parameters: ++// [in] ptSpinlock: The spinlock to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinInit(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Lock the spinlock, if spinlock isn't initialized, this API will init it ++// automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinLock(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Unlock the spinlock, if spinlock isn't initialized, this API will init ++// it automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinUnlock(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Lock the spinlock and save IRQ status, if spinlock isn't initialized, ++// this API will init it automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinLockIrqSave(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Unlock the spinlock and restore IRQ status, if spinlock isn't initialized, ++// this API will init it automatically. ++// Parameters: ++// [in] ptSpinlock: The spinlock to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsSpinUnlockIrqRestore(CamOsSpinlock_t *ptSpinlock); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of memory, returning a pointer to the ++// beginning of the block. ++// Parameters: ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemAlloc(u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of memory without sleep, returning a ++// pointer to the beginning of the block. ++// Parameters: ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemAllocAtomic(u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of memory for an array of nNum elements, each of them ++// nSize bytes long, and initializes all its bits to zero. ++// Parameters: ++// [in] nNum: Number of elements to allocate. ++// [in] nSize: Size of each element. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemCalloc(u32 nNum, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of memory for an array of nNum elements without sleep, ++// each of them nSize bytes long, and initializes all its bits to zero. ++// Parameters: ++// [in] nNum: Number of elements to allocate. ++// [in] nSize: Size of each element. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemCallocAtomic(u32 nNum, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Changes the size of the memory block pointed to by pPtr. The function ++// may move the memory block to a new location (whose address is returned ++// by the function). ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// [in] nSize: New size for the memory block, in bytes. ++// Return: ++// A pointer to the reallocated memory block, which may be either the same ++// as pPtr or a new location. ++//============================================================================= ++void* CamOsMemRealloc(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Changes the size of the memory block pointed to by pPtr without sleep. ++// The function may move the memory block to a new location (whose address ++// is returned by the function). ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// [in] nSize: New size for the memory block, in bytes. ++// Return: ++// A pointer to the reallocated memory block, which may be either the same ++// as pPtr or a new location. ++//============================================================================= ++void* CamOsMemReallocAtomic(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Flush data in cache ++// Parameters: ++// [in] pPtr: Virtual start address ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemFlush(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Flush data in inner and outer cache ++// Parameters: ++// [in] pVa: Virtual start address ++// [in] pPa: Physical start address ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemFlushExt(void* pVa, void* pPA, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Invalidate data in cache ++// Parameters: ++// [in] pPtr: Virtual start address ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemInvalidate(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsMemAlloc, ++// CamOsMemCalloc or CamOsMemRealloc is deallocated, making it available ++// again for further allocations. If pPtr is a null pointer, the function ++// does nothing. ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemRelease(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Flush MIU write buffer. ++// Parameters: ++// N/A ++// Return: ++// N/A ++//============================================================================= ++void CamOsMiuPipeFlush(void); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of direct memory (non-cached memory), ++// returning three pointer for different address domain to the beginning ++// of the block. ++// Parameters: ++// [in] szName: Name of the memory block, whose length is restricted to ++// 16 characters. ++// [in] nSize: Size of the memory block, in bytes. ++// [out] ppVirtPtr: Virtual address pointer to the memory block. ++// [out] ppPhysPtr: Physical address pointer to the memory block. ++// [out] ppMiuPtr: Memory Interface Unit address pointer to the memory block. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppVirtPtr, ++ void** ppPhysPtr, ++ void** ppMiuPtr); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsDirectMemAlloc, ++// is deallocated, making it available again for further allocations. ++// Parameters: ++// [in] pPtr: Physical or Virtual address pointer to a memory block ++// previously allocated with CamOsDirectMemAlloc. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemRelease(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Flush chche of a block of memory previously allocated by a call to ++// CamOsDirectMemAlloc. ++// Parameters: ++// [in] pPtr: Physical or Virtual address pointer to a memory block ++// previously allocated with CamOsDirectMemAlloc. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemFlush(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Print all allocated direct memory information to the standard output. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemStat(void); ++ ++//============================================================================= ++// Description: ++// Transfer Physical address to MIU address. ++// Parameters: ++// [in] pPtr: Physical address. ++// Return: ++// MIU address. ++//============================================================================= ++void* CamOsDirectMemPhysToMiu(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Transfer MIU address to Physical address. ++// Parameters: ++// [in] pPtr: MIU address. ++// Return: ++// Physical address. ++//============================================================================= ++void* CamOsDirectMemMiuToPhys(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Transfer Physical address to Virtual address. ++// Parameters: ++// [in] pPtr: Physical address. ++// Return: ++// Virtual address. ++//============================================================================= ++void* CamOsDirectMemPhysToVirt(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Transfer Virtual address to Physical address. ++// Parameters: ++// [in] pPtr: Virtual address. ++// Return: ++// Physical address. ++//============================================================================= ++void* CamOsDirectMemVirtToPhys(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Map Physical address to Virtual address. ++// Parameters: ++// [in] pPhyPtr: Physical address. ++// [in] nSize: Size of the memory block, in bytes. ++// [in] bNonCache: Map to cache or non-cache area. ++// Return: ++// Virtual address. ++//============================================================================= ++void* CamOsPhyMemMap(void* pPhyPtr, u32 nSize, u8 bNonCache); ++ ++//============================================================================= ++// Description: ++// Unmap Virtual address that was mapped by CamOsPhyMemMap. ++// Parameters: ++// [in] pVirtPtr: Virtual address. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPhyMemUnMap(void* pVirtPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Map physical address to virtual address. ++// Parameters: ++// [in] pPhyPtr: Physical address. ++// [in] nSize: Size of the memory block, in bytes. ++// [in] bCache: Map to cache or non-cache area. ++// Return: ++// Virtual address. ++//============================================================================= ++void* CamOsMemMap(void* pPhyPtr, u32 nSize, u8 bCache); ++ ++//============================================================================= ++// Description: ++// Unmap virtual address that was mapped by CamOsMemMap. ++// Parameters: ++// [in] pVirtPtr: Virtual address. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemUnmap(void* pVirtPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Create a memory cache(memory pool) and allocate with specified size ++// to ignore internal fragmentation. ++// Parameters: ++// [out] ptMemCache: Get memory cache information if create successfully. ++// [in] szName: A string which is used in /proc/slabinfo to identify ++// this cache(It's significant only in linux kernel). ++// [in] nSize: Object size in this cache. ++// [in] bHwCacheAlign: Align objs on cache lines(Only for Linux) ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMemCacheCreate(CamOsMemCache_t *ptMemCache, char *szName, u32 nSize, u8 bHwCacheAlign); ++ ++//============================================================================= ++// Description: ++// Destroy the memory cache. ++// Parameters: ++// [in] ptMemCache: The cache to destroy. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemCacheDestroy(CamOsMemCache_t *ptMemCache); ++ ++//============================================================================= ++// Description: ++// Allocate a memory block(object) from this memory cache. ++// Parameters: ++// [in] ptMemCache: The cache to be allocated. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void *CamOsMemCacheAlloc(CamOsMemCache_t *ptMemCache); ++ ++//============================================================================= ++// Description: ++// Allocate a memory block(object) from this memory cache without sleep. ++// Parameters: ++// [in] ptMemCache: The cache to be allocated. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void *CamOsMemCacheAllocAtomic(CamOsMemCache_t *ptMemCache); ++ ++//============================================================================= ++// Description: ++// Release a memory block(object) to this memory cache. ++// Parameters: ++// [in] ptMemCache: The cache to be released to. ++// [in] pObjPtr: Pointer to a memory block(object) previously allocated by ++// CamOsMemCacheAlloc. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemCacheFree(CamOsMemCache_t *ptMemCache, void *pObjPtr); ++ ++//============================================================================= ++// Description: ++// Set property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [in] szValue: Value if property. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue); ++ ++//============================================================================= ++// Description: ++// Get property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [out] szValue: Value if property. ++// [in] szDefaultValue: If the property read fails or returns an empty ++// value, the default value is used ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertyGet(const char *szkey, char *szValue, const char *szDefaultValue); ++ ++//============================================================================= ++// Description: ++// Unsigned 64bit divide with Unsigned 64bit divisor with remainder. ++// Parameters: ++// [in] nDividend: Dividend. ++// [in] nDivisor: Divisor. ++// [out] pRemainder: Pointer to the remainder. This parameter can also be ++// a null pointer, in which case it is not used. ++// Return: ++// Quotient of division. ++//============================================================================= ++u64 CamOsMathDivU64(u64 nDividend, u64 nDivisor, u64 *pRemainder); ++ ++//============================================================================= ++// Description: ++// Signed 64bit divide with signed 64bit divisor with remainder. ++// Parameters: ++// [in] nDividend: Dividend. ++// [in] nDivisor: Divisor. ++// [out] pRemainder: Pointer to the remainder. This parameter can also be ++// a null pointer, in which case it is not used. ++// Return: ++// Quotient of division. ++//============================================================================= ++s64 CamOsMathDivS64(s64 nDividend, s64 nDivisor, s64 *pRemainder); ++ ++//============================================================================= ++// Description: ++// Copy a block of data from user space in Linux kernel space, it just ++// memory copy in RTOS. ++// Parameters: ++// [in] pTo: Destination address, in kernel space. ++// [in] pFrom: Source address, in user space. ++// [in] nLen: Number of bytes to copy. ++// Return: ++// Number of bytes that could not be copied. On success, this will be zero. ++//============================================================================= ++u32 CamOsCopyFromUpperLayer(void *pTo, const void *pFrom, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Copy a block of data into user space in Linux kernel space, it just ++// memory copy in RTOS. ++// Parameters: ++// [in] pTo: Destination address, in user space. ++// [in] pFrom: Source address, in kernel space. ++// [in] nLen: Number of bytes to copy. ++// Return: ++// Number of bytes that could not be copied. On success, this will be zero. ++//============================================================================= ++u32 CamOsCopyToUpperLayer(void *pTo, const void * pFrom, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Init timer. ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTimerInit(CamOsTimer_t *ptTimer); ++ ++//============================================================================= ++// Description: ++// Deactivates a timer ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// Return: ++// 0 is returned if timer has expired; otherwise, returns 1. ++//============================================================================= ++u32 CamOsTimerDelete(CamOsTimer_t *ptTimer); ++ ++//============================================================================= ++// Description: ++// Deactivates a timer and wait for the handler to finish. This function ++// only differs from del_timer on SMP ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// Return: ++// 0 is returned if timer has expired; otherwise, returns 1. ++//============================================================================= ++u32 CamOsTimerDeleteSync(CamOsTimer_t *ptTimer); ++ ++//============================================================================= ++// Description: ++// Start timer. ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// [in] nMsec: The value of timer for the timeout. ++// [in] pDataPtr: Pointer of user data for callback function. ++// [in] pfnFunc: Pointer of callback function. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTimerAdd(CamOsTimer_t *ptTimer, u32 nMsec, void *pDataPtr, void (*pfnFunc)(unsigned long nDataAddr)); ++ ++//============================================================================= ++// Description: ++// Restart timer that has been added with new timeout value. ++// Parameters: ++// [in] ptTimer: Pointer of type CamOsTimer_t. ++// [in] nMsec: The value of timer for the timeout. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTimerModify(CamOsTimer_t *ptTimer, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Read atomic variable. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicRead(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Set atomic variable. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Required value. ++// Return: ++// N/A ++//============================================================================= ++void CamOsAtomicSet(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Add to the atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to add. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicAddReturn(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Subtract the atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to subtract. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicSubReturn(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Subtract value from variable and test result. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to subtract. ++// Return: ++// Returns true if the result is zero, or false for all other cases. ++//============================================================================= ++s32 CamOsAtomicSubAndTest(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Increment atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicIncReturn(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// decrement atomic variable and return value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicDecReturn(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Increment and test result. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// Returns true if the result is zero, or false for all other cases. ++//============================================================================= ++s32 CamOsAtomicIncAndTest(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Decrement and test result. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// Return: ++// Returns true if the result is zero, or false for all other cases. ++//============================================================================= ++s32 CamOsAtomicDecAndTest(CamOsAtomic_t *ptAtomic); ++ ++//============================================================================= ++// Description: ++// Add to the atomic variable and test if negative. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to subtract. ++// Return: ++// Returns true if the result is negative, or false when result is greater ++// than or equal to zero. ++//============================================================================= ++s32 CamOsAtomicAddNegative(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Read the 32-bit value (referred to as nOldValue) stored at location pointed by ptAtomic. ++// Compute (nOldValue == cmp) ? val : nOldValue and store result at location pointed by ptAtomic. The function returns nOldValue ++// Parameters: ++// [in] ptr: Pointer of type void ++// [in] nOldValue: old value. ++// [in] nNewValue : new value ++ ++// Return: ++// Returns true if the val is changed into new value ++//============================================================================= ++s32 CamOsAtomicCompareAndSwap(CamOsAtomic_t *ptAtomic, s32 nOldValue, s32 nNewValue); ++ ++//============================================================================= ++// Description: ++// AND operation with the atomic variable and return the new value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to AND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicAndFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// AND operation with the atomic variable and returns the value that had ++// previously been in memory. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to AND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchAnd(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// NAND operation with the atomic variable and return the new value. ++// GCC 4.4 and later implement NAND as "~(ptAtomic & nValue)" instead of ++// "~ptAtomic & nValue". ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to NAND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicNandFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// NAND operation with the atomic variable and returns the value that had ++// previously been in memory. GCC 4.4 and later implement NAND as ++// "~(ptAtomic & nValue)" instead of "~ptAtomic & nValue". ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to NAND. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchNand(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// OR operation with the atomic variable and return the new value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to OR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicOrFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// OR operation with the atomic variable and returns the value that had ++// previously been in memory. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to OR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchOr(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// XOR operation with the atomic variable and return the new value. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to XOR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicXorFetch(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// XOR operation with the atomic variable and returns the value that had ++// previously been in memory. ++// Parameters: ++// [in] ptAtomic: Pointer of type CamOsAtomic_t. ++// [in] nValue: Integer value to XOR. ++// Return: ++// The value of ptAtomic. ++//============================================================================= ++s32 CamOsAtomicFetchXor(CamOsAtomic_t *ptAtomic, s32 nValue); ++ ++//============================================================================= ++// Description: ++// Init IDR data structure. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsIdrInit(CamOsIdr_t *ptIdr); ++ ++//============================================================================= ++// Description: ++// Init IDR data structure with maximum entry number. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] nEntryNum: Maximum number of entries. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsIdrInitEx(CamOsIdr_t *ptIdr, u32 nEntryNum); ++ ++//============================================================================= ++// Description: ++// Destroy the IDR data structure. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIdrDestroy(CamOsIdr_t *ptIdr); ++ ++//============================================================================= ++// Description: ++// Increment atomic variable and return value. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] pPtr: Pointer of the data to store in IDR structure. ++// [in] nStart: Start number of requested ID range. ++// [in] nEnd: End number of requested ID range. ++// Return: ++// The allocated ID number. If allocation fail, negative integer will ++// be returned. ++//============================================================================= ++s32 CamOsIdrAlloc(CamOsIdr_t *ptIdr, void *pPtr, s32 nStart, s32 nEnd); ++ ++//============================================================================= ++// Description: ++// Remove data from the IDR structure by ID. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] nId: Data ID number. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIdrRemove(CamOsIdr_t *ptIdr, s32 nId); ++ ++//============================================================================= ++// Description: ++// Find data from the IDR structure by ID. ++// Parameters: ++// [in] ptIdr: Pointer of type CamOsIdr_t. ++// [in] nId: Data ID number. ++// Return: ++// On success, a pointer to the data stored in IDR structure. If ++// failed to find, a null pointer is returned. ++//============================================================================= ++void *CamOsIdrFind(CamOsIdr_t *ptIdr, s32 nId); ++ ++//============================================================================= ++// Description: ++// Get physical memory size of system. ++// Parameters: ++// N/A ++// Return: ++// Enumeration of memory size. ++//============================================================================= ++CamOsMemSize_e CamOsPhysMemSize(void); ++ ++//============================================================================= ++// Description: ++// Get physical memory size of system. ++// Parameters: ++// [out] ptInfo: A pointer to a CamOsDramInfo_t structure where ++// CamOsDramInfo() can store the information. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDramInfo(CamOsDramInfo_t *ptInfo); ++ ++//============================================================================= ++// Description: ++// Get Chip ID. ++// Parameters: ++// N/A ++// Return: ++// Chip ID. ++//============================================================================= ++u32 CamOsChipId(void); ++ ++//============================================================================= ++// Description: ++// Get Chip Revision. ++// Parameters: ++// N/A ++// Return: ++// Chip revision. ++//============================================================================= ++u32 CamOsChipRevision(void); ++ ++//============================================================================= ++// Description: ++// Free an interrupt allocated with request_irq. ++// Parameters: ++// [in] nIrq: Interrupt line to allocate. ++// [in] pfnHandler: Function to be called when the IRQ occurs. ++// [in] szName: An ascii name for the claiming device. ++// [in] pDevId: A cookie passed back to the handler function. ++// Return: ++// N/A ++//============================================================================= ++CamOsRet_e CamOsIrqRequest(u32 nIrq, CamOsIrqHandler pfnHandler, const char *szName, void *pDevId); ++ ++//============================================================================= ++// Description: ++// Free an interrupt allocated with request_irq. ++// Parameters: ++// [in] nIrq: Interrupt line to free. ++// [in] pDevId: Device identity to free. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIrqFree(u32 nIrq, void *pDevId); ++ ++//============================================================================= ++// Description: ++// Enable handling of an irq. ++// Parameters: ++// [in] nIrq: Interrupt to enable. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIrqEnable(u32 nIrq); ++ ++//============================================================================= ++// Description: ++// Disable an irq and wait for completion. ++// Parameters: ++// [in] nIrq: Interrupt to disable. ++// Return: ++// N/A ++//============================================================================= ++void CamOsIrqDisable(u32 nIrq); ++ ++//============================================================================= ++// Description: ++// Check if current function runs in ISR. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if in ISR; otherwise, returns CAM_OS_FAIL. ++//============================================================================= ++CamOsRet_e CamOsInInterrupt(void); ++ ++//============================================================================= ++// Description: ++// Memory barrier. ++// Parameters: ++// N/A ++// Return: ++// N/A. ++//============================================================================= ++void CamOsMemoryBarrier(void); ++ ++//============================================================================= ++// Description: ++// Symmetric multiprocessing memory barrier. ++// Parameters: ++// N/A ++// Return: ++// N/A. ++//============================================================================= ++void CamOsSmpMemoryBarrier(void); ++ ++//============================================================================= ++// Description: ++// Return string describing error number. ++// Parameters: ++// [in] nErrNo: Error number to be converted. ++// Return: ++// Character pointer to string of description. ++//============================================================================= ++char *CamOsStrError(s32 nErrNo); ++ ++//============================================================================= ++// Description: ++// Put system into panic. ++// Parameters: ++// [in] szMessage: message to output in console. ++// Return: ++// N/A ++//============================================================================= ++void CamOsPanic(const char *szMessage); ++ ++//============================================================================= ++// Description: ++// Convert string to long integer with specific base. ++// Parameters: ++// [in] szStr: String beginning with the representation of ++// an integral number. ++// [in] szEndptr: Reference to an object of type char*, whose value ++// is set by the function to the next character in szStr ++// after the numerical value. ++// This parameter can also be a null pointer, in which ++// case it is not used. ++// [in] nBase: Numerical base (radix) that determines the valid characters ++// and their interpretation. If this is 0, the base used is ++// determined by the format in the sequence (see above). ++// Return: ++// Converted long integer. ++//============================================================================= ++long CamOsStrtol(const char *szStr, char** szEndptr, s32 nBase); ++ ++//============================================================================= ++// Description: ++// Convert string to unsigned long integer with specific base. ++// Parameters: ++// [in] szStr: String beginning with the representation of ++// an integral number. ++// [in] szEndptr: Reference to an object of type char*, whose value ++// is set by the function to the next character in szStr ++// after the numerical value. ++// This parameter can also be a null pointer, in which ++// case it is not used. ++// [in] nBase: Numerical base (radix) that determines the valid characters ++// and their interpretation. If this is 0, the base used is ++// determined by the format in the sequence (see above). ++// Return: ++// Converted long integer. ++//============================================================================= ++unsigned long CamOsStrtoul(const char *szStr, char** szEndptr, s32 nBase); ++ ++//============================================================================= ++// Description: ++// Convert string to unsigned long long integer with specific base. ++// Parameters: ++// [in] szStr: String beginning with the representation of ++// an integral number. ++// [in] szEndptr: Reference to an object of type char*, whose value ++// is set by the function to the next character in szStr ++// after the numerical value. ++// This parameter can also be a null pointer, in which ++// case it is not used. ++// [in] nBase: Numerical base (radix) that determines the valid characters ++// and their interpretation. If this is 0, the base used is ++// determined by the format in the sequence (see above). ++// Return: ++// Converted long integer. ++//============================================================================= ++unsigned long long CamOsStrtoull(const char *szStr, char** szEndptr, s32 nBase); ++ ++#endif /* __CAM_OS_WRAPPER_H__ */ +diff --git a/drivers/sstar/include/cam_sysfs.h b/drivers/sstar/include/cam_sysfs.h +new file mode 100755 +index 000000000000..b80a8db97f6d +--- /dev/null ++++ b/drivers/sstar/include/cam_sysfs.h +@@ -0,0 +1,84 @@ ++/* ++* cam_sysfs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_sysfs.h ++/// @brief Cam sysfs Wrapper Header File for ++/// 1. RTK OS ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_SYSFS_H__ ++#define __CAM_SYSFS_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++void CamModulePlatformDriver(struct platform_driver); ++int CamOfPropertyReadU32Array(const struct device_node *np, ++ const char *propname, u32 *out_values, ++ size_t sz); ++void CamClassDestroy(struct class *cls); ++struct class * __must_check CamClassCreate(struct module *owner, const char *name); ++struct kobject *CamKobjectCreateAndAdd(const char *name, struct kobject *parent); ++void CamDeviceUnregister(struct device *dev); ++void CamDeviceRemoveFile(struct device *dev, const struct device_attribute *attr); ++void CamDeviceDestroy(struct class *class, dev_t devt); ++int CamDeviceCreateFile(struct device *dev, const struct device_attribute *attr); ++struct device *CamDeviceCreate(struct class *class, struct device *parent, dev_t devt, void *drvdata, const char *fmt, ...); ++void CamSysfsRemoveFiles(struct kobject *kobj, const struct attribute **attr); ++void CamSysfsRemoveFile(struct kobject *kobj, const struct attribute *attr); ++int CamSysfsCreateLink(struct kobject *kobj, struct kobject *target, const char *name); ++int CamSysfsCreateFiles(struct kobject *kobj, const struct attribute **ptr); ++int __must_check CamSysfsCreateFile(struct kobject *kobj, const struct attribute * attr); ++int CamPlatformGetIrqByname(struct platform_device *dev, const char *name); ++void CamPlatformDriverUnregister(struct platform_driver *drv); ++int CamPlatformDriverRegister(struct platform_driver *drv); ++struct resource *CamPlatformGetResource(struct platform_device *dev, unsigned int type, unsigned int num); ++int CamOfAddressToResource(struct device_node *dev, int index, struct resource *r); ++int CamOfIrqToResource(struct device_node *dev, int index, struct resource *r); ++int CamOfPropertyReadU32Index(const struct device_node *np, const char *propname, u32 index, u32 *out_value); ++int CamOfPropertyReadVariableU32Array(const struct device_node *np, const char *propname, u32 *out_values, size_t sz_min, size_t sz_max); ++int CamofPropertyReadU32(const struct device_node *np, ++ const char *propname, ++ u32 *out_value); ++int CamIoremapPageRange(unsigned long addr, ++ unsigned long end, phys_addr_t phys_addr, pgprot_t prot); ++void CamDevmKfree(struct device *dev, void *p); ++void * CamDevmKmalloc(struct device *dev, size_t size, gfp_t gfp); ++int CamGpioRequest(unsigned gpio, const char *label); ++unsigned int CamIrqOfParseAndMap(struct device_node *dev, int index); ++struct workqueue_struct* CamCreatesiglethreadWorkqueue(const char *fmt); ++ ++#endif /* __CAM_SYSFS_H__ */ +\ No newline at end of file +diff --git a/drivers/sstar/include/cam_sysfs.h.bak b/drivers/sstar/include/cam_sysfs.h.bak +new file mode 100755 +index 000000000000..46826dda9e66 +--- /dev/null ++++ b/drivers/sstar/include/cam_sysfs.h.bak +@@ -0,0 +1,66 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_sysfs.h ++/// @brief Cam sysfs Wrapper Header File for ++/// 1. RTK OS ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_SYSFS_H__ ++#define __CAM_SYSFS_H__ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++void CamModulePlatformDriver(struct platform_driver); ++ ++void CamClassDestroy(struct class *cls); ++struct class * __must_check CamClassCreate(struct module *owner, const char *name); ++struct kobject *CamKobjectCreateAndAdd(const char *name, struct kobject *parent); ++void CamDeviceUnregister(struct device *dev); ++void CamDeviceRemoveFile(struct device *dev, const struct device_attribute *attr); ++void CamDeviceDestroy(struct class *class, dev_t devt); ++int CamDeviceCreateFile(struct device *dev, const struct device_attribute *attr); ++struct device *CamDeviceCreate(struct class *class, struct device *parent, dev_t devt, void *drvdata, const char *fmt, ...); ++void CamSysfsRemoveFiles(struct kobject *kobj, const struct attribute **attr); ++void CamSysfsRemoveFile(struct kobject *kobj, const struct attribute *attr); ++int CamSysfsCreateLink(struct kobject *kobj, struct kobject *target, const char *name); ++int CamSysfsCreateFiles(struct kobject *kobj, const struct attribute **ptr); ++int __must_check CamSysfsCreateFile(struct kobject *kobj, const struct attribute * attr); ++int CamPlatformGetIrqByname(struct platform_device *dev, const char *name); ++void CamPlatformDriverUnregister(struct platform_driver *drv); ++int CamPlatformDriverRegister(struct platform_driver *drv); ++struct resource *CamPlatformGetResource(struct platform_device *dev, unsigned int type, unsigned int num); ++int CamOfAddressToResource(struct device_node *dev, int index, struct resource *r); ++int CamOfIrqToResource(struct device_node *dev, int index, struct resource *r); ++int CamOfPropertyReadU32Index(const struct device_node *np, const char *propname, u32 index, u32 *out_value); ++int CamOfPropertyReadVariableU32Array(const struct device_node *np, const char *propname, u32 *out_values, size_t sz_min, size_t sz_max); ++ ++#endif /* __CAM_SYSFS_H__ */ +diff --git a/drivers/sstar/include/ceva_linkdrv-generic.h b/drivers/sstar/include/ceva_linkdrv-generic.h +new file mode 100644 +index 000000000000..1f49a785cf0d +--- /dev/null ++++ b/drivers/sstar/include/ceva_linkdrv-generic.h +@@ -0,0 +1,198 @@ ++/* ++* ceva_linkdrv-generic.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * ceva_linkdrv-generic.h ++ * ++ * Created on: Nov 13, 2013 ++ * Author: Ido Reis ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#ifndef CEVA_LINKDRV_GENERIC_H_ ++#define CEVA_LINKDRV_GENERIC_H_ ++ ++#include ++#include ++#include ++ ++ ++/*! ++ * Device name for kernel registration ++ */ ++#define CEVA_PCIDEV_DEVICE_NAME "ceva_linkdrv_xm6_" ++/*! ++ * dma region size ++ */ ++#define CEVADEV_PCI_DMA_MEM_SIZE_ORDER (20) ++#define CEVADEV_PCI_DMA_MEM_SIZE (1<fiq_cnt++ ++#define RTKINFO_FFIQTS() _rtk->ffiq_ts = (unsigned int)(_getsysts() - epiod); ++#define RTKINFO_LOADNSTS() _rtk->ldns_ts = (unsigned int)(_getsysts() - epiod); ++#define RTKINFO_TTFF_ISP() if (!_rtk->ttff_isp) _rtk->ttff_isp = (unsigned int)(_getsysts() - epiod); ++#define RTKINFO_TTFF_SCL() if (!_rtk->ttff_scl) _rtk->ttff_scl = (unsigned int)(_getsysts() - epiod); ++#define RTKINFO_TTFF_MFE() if (!_rtk->ttff_mfe) _rtk->ttff_mfe = (unsigned int)(_getsysts() - epiod); ++#define RTK_TIME_TO_US(x) (x / 6) ++ ++struct rlink_head { ++ struct rlink_head *next, *prev; ++ void* nphys; // next object physical address ++ unsigned int nsize; // next object size ++ unsigned int reserved; ++}; ++ ++typedef struct { ++ struct rlink_head root; ++ char name[8]; ++ char version[64]; ++ unsigned int verid; ++ unsigned int size; ++ unsigned int fiq_cnt; ++ unsigned int ffiq_ts; ++ unsigned int ttff_isp; ++ unsigned int ttff_scl; ++ unsigned int ttff_mfe; ++ unsigned int ldns_ts; ++ u64 start_ts; ++ u64 lifet; ++ u64 spent; ++ u64 spent_hyp; ++ u64 spent_sc; ++ u64 linux_idle_in_rtos_time; ++ unsigned int diff; ++ unsigned int linux_idle; ++ u64 syscall_cnt; ++ ++ // sbox must be 16-byte aligned ++ unsigned char sbox[1024]; ++} rtkinfo_t; ++ ++extern rtkinfo_t *_rtk; ++extern u64 epiod; ++ ++rtkinfo_t* get_rtkinfo(void); ++unsigned long signal_rtos(u32 type, u32 arg1, u32 arg2, u32 arg3); ++void handle_interos_nblk_call_req(void); ++void handle_reroute_smc(void); ++ ++#endif //__DRV_DUALOS_H__ +diff --git a/drivers/sstar/include/drv_isrcb.h b/drivers/sstar/include/drv_isrcb.h +new file mode 100644 +index 000000000000..b06ec5adee7c +--- /dev/null ++++ b/drivers/sstar/include/drv_isrcb.h +@@ -0,0 +1,49 @@ ++/* ++* drv_isrcb.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_ISRCB_ ++#define _DRV_ISRCB_ ++ ++typedef enum ++{ ++ eISRCB_ID_ISP_WDMA0_DONE=0, ++ eISRCB_ID_ISP_WDMA1_DONE, ++ eISRCB_ID_ISP_WDMA2_DONE, ++ eISRCB_ID_ISP_WDMA3_DONE, ++ eISRCB_ID_ISP_WDMA0_HIT_LINE_CNT, ++ eISRCB_ID_ISP_WDMA1_HIT_LINE_CNT, ++ eISRCB_ID_ISP_WDMA2_HIT_LINE_CNT, ++ eISRCB_ID_ISP_WDMA3_HIT_LINE_CNT, ++ eISRCB_ID_ISP_VIF0_FRAME_START, ++ eISRCB_ID_ISP_VIF1_FRAME_START, ++ eISRCB_ID_ISP_VIF2_FRAME_START, ++ eISRCB_ID_ISP_VIF3_FRAME_START, ++ eISRCB_ID_ISP_VIF0_FRAME_END, ++ eISRCB_ID_ISP_VIF1_FRAME_END, ++ eISRCB_ID_ISP_VIF2_FRAME_END, ++ eISRCB_ID_ISP_VIF3_FRAME_END, ++ eISRCB_ID_MAX, ++}ISRCB_ID_e; ++ ++typedef void* ISRCB_Handle; ++typedef void (*ISRCB_fp)(void* pData); ++ ++ISRCB_Handle ISRCB_RegisterCallback(ISRCB_ID_e eID,ISRCB_fp fpCB,void* pData); ++void ISRCB_UnRegisterCallback(ISRCB_Handle hHnd); ++void ISRCB_Proc(ISRCB_ID_e eID); ++ ++#endif +diff --git a/drivers/sstar/include/drvcmdq_io.h b/drivers/sstar/include/drvcmdq_io.h +new file mode 100644 +index 000000000000..068b0ae4b127 +--- /dev/null ++++ b/drivers/sstar/include/drvcmdq_io.h +@@ -0,0 +1,29 @@ ++/* ++* drvcmdq_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __DRVCMDQ_IO_HH__ ++#define __DRVCMDQ_IO_HH__ ++ ++#define IOCTL_CMDQ_TEST1_CONFIG (1) ++#define IOCTL_VIP_MAGIC ('3') ++/** ++* Used to set CMDQ cmd, use ST_IOCTL_VIP_CMDQ_CONFIG. ++*/ ++#define IOCTL_CMDQ_TEST_1 _IO(IOCTL_VIP_MAGIC, IOCTL_CMDQ_TEST1_CONFIG) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity2/Kconfig b/drivers/sstar/include/infinity2/Kconfig +new file mode 100755 +index 000000000000..c393005981c1 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/Kconfig +@@ -0,0 +1,11 @@ ++source "drivers/sstar/ive/Kconfig" ++source "drivers/sstar/warp/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/vcore_dvfs/Kconfig" ++source "drivers/sstar/ceva_link/Kconfig" ++source "drivers/sstar/gmac/Kconfig" ++source "drivers/sstar/noe/Kconfig" ++source "drivers/sstar/miu/Kconfig" ++source "drivers/sstar/bdma/Kconfig" ++source "drivers/sstar/movedma/Kconfig" ++source "drivers/sstar/sata_host/Kconfig" +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/gpi-irqs.h b/drivers/sstar/include/infinity2/gpi-irqs.h +new file mode 100755 +index 000000000000..2dc8c5644a0a +--- /dev/null ++++ b/drivers/sstar/include/infinity2/gpi-irqs.h +@@ -0,0 +1,113 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++#define GPI_FIQ_START 0 ++#define INT_GPI_FIQ_UART1_RX (GPI_FIQ_START + 0) ++#define INT_GPI_FIQ_UART1_TX (GPI_FIQ_START + 1) ++#define INT_GPI_FIQ_UART0_RX (GPI_FIQ_START + 2) ++#define INT_GPI_FIQ_UART0_TX (GPI_FIQ_START + 3) ++#define INT_GPI_FIQ_TTL0 (GPI_FIQ_START + 4) ++#define INT_GPI_FIQ_TTL1 (GPI_FIQ_START + 5) ++#define INT_GPI_FIQ_TTL2 (GPI_FIQ_START + 6) ++#define INT_GPI_FIQ_TTL3 (GPI_FIQ_START + 7) ++#define INT_GPI_FIQ_TTL4 (GPI_FIQ_START + 8) ++#define INT_GPI_FIQ_TTL5 (GPI_FIQ_START + 9) ++#define INT_GPI_FIQ_TTL6 (GPI_FIQ_START + 10) ++#define INT_GPI_FIQ_TTL7 (GPI_FIQ_START + 11) ++#define INT_GPI_FIQ_TTL8 (GPI_FIQ_START + 12) ++#define INT_GPI_FIQ_TTL9 (GPI_FIQ_START + 13) ++#define INT_GPI_FIQ_TTL10 (GPI_FIQ_START + 14) ++#define INT_GPI_FIQ_TTL11 (GPI_FIQ_START + 15) ++#define INT_GPI_FIQ_TTL12 (GPI_FIQ_START + 16) ++#define INT_GPI_FIQ_TTL13 (GPI_FIQ_START + 17) ++#define INT_GPI_FIQ_TTL14 (GPI_FIQ_START + 18) ++#define INT_GPI_FIQ_TTL15 (GPI_FIQ_START + 19) ++#define INT_GPI_FIQ_TTL16 (GPI_FIQ_START + 20) ++#define INT_GPI_FIQ_TTL17 (GPI_FIQ_START + 21) ++#define INT_GPI_FIQ_TTL18 (GPI_FIQ_START + 22) ++#define INT_GPI_FIQ_TTL19 (GPI_FIQ_START + 23) ++#define INT_GPI_FIQ_TTL20 (GPI_FIQ_START + 24) ++#define INT_GPI_FIQ_TTL21 (GPI_FIQ_START + 25) ++#define INT_GPI_FIQ_TTL22 (GPI_FIQ_START + 26) ++#define INT_GPI_FIQ_TTL23 (GPI_FIQ_START + 27) ++#define INT_GPI_FIQ_TTL24 (GPI_FIQ_START + 28) ++#define INT_GPI_FIQ_TTL25 (GPI_FIQ_START + 29) ++#define INT_GPI_FIQ_TTL26 (GPI_FIQ_START + 30) ++#define INT_GPI_FIQ_TTL27 (GPI_FIQ_START + 31) ++#define INT_GPI_FIQ_SD_D0 (GPI_FIQ_START + 32) ++#define INT_GPI_FIQ_SD_D1 (GPI_FIQ_START + 33) ++#define INT_GPI_FIQ_SD_D2 (GPI_FIQ_START + 34) ++#define INT_GPI_FIQ_SD_D3 (GPI_FIQ_START + 35) ++#define INT_GPI_FIQ_SD_CMD (GPI_FIQ_START + 36) ++#define INT_GPI_FIQ_SD_CLK (GPI_FIQ_START + 37) ++#define INT_GPI_FIQ_SD_GPIO (GPI_FIQ_START + 38) ++#define INT_GPI_FIQ_SATA_GPIO (GPI_FIQ_START + 39) ++#define INT_GPI_FIQ_HSYNC_OUT (GPI_FIQ_START + 40) ++#define INT_GPI_FIQ_VSYNC_OUT (GPI_FIQ_START + 41) ++#define INT_GPI_FIQ_HDMITX_SCL (GPI_FIQ_START + 42) ++#define INT_GPI_FIQ_HDMITX_SDA (GPI_FIQ_START + 43) ++#define INT_GPI_FIQ_HDMITX_HPD (GPI_FIQ_START + 44) ++#define INT_GPI_FIQ_GPIO0 (GPI_FIQ_START + 45) ++#define INT_GPI_FIQ_GPIO1 (GPI_FIQ_START + 46) ++#define INT_GPI_FIQ_GPIO2 (GPI_FIQ_START + 47) ++#define INT_GPI_FIQ_GPIO3 (GPI_FIQ_START + 48) ++#define INT_GPI_FIQ_GPIO4 (GPI_FIQ_START + 49) ++#define INT_GPI_FIQ_GPIO5 (GPI_FIQ_START + 50) ++#define INT_GPI_FIQ_GPIO6 (GPI_FIQ_START + 51) ++#define INT_GPI_FIQ_GPIO7 (GPI_FIQ_START + 52) ++#define INT_GPI_FIQ_GPIO8 (GPI_FIQ_START + 53) ++#define INT_GPI_FIQ_GPIO9 (GPI_FIQ_START + 54) ++#define INT_GPI_FIQ_GPIO10 (GPI_FIQ_START + 55) ++#define INT_GPI_FIQ_GPIO11 (GPI_FIQ_START + 56) ++#define INT_GPI_FIQ_GPIO12 (GPI_FIQ_START + 57) ++#define INT_GPI_FIQ_GPIO13 (GPI_FIQ_START + 58) ++#define INT_GPI_FIQ_GPIO14 (GPI_FIQ_START + 59) ++#define INT_GPI_FIQ_FUART_RX (GPI_FIQ_START + 60) ++#define INT_GPI_FIQ_FUART_TX (GPI_FIQ_START + 61) ++#define INT_GPI_FIQ_FUART_CTS (GPI_FIQ_START + 62) ++#define INT_GPI_FIQ_FUART_RTS (GPI_FIQ_START + 63) ++#define INT_GPI_FIQ_DUMMY64 (GPI_FIQ_START + 64) ++#define INT_GPI_FIQ_DUMMY65 (GPI_FIQ_START + 65) ++#define INT_GPI_FIQ_DUMMY66 (GPI_FIQ_START + 66) ++#define INT_GPI_FIQ_DUMMY67 (GPI_FIQ_START + 67) ++#define INT_GPI_FIQ_DUMMY68 (GPI_FIQ_START + 68) ++#define INT_GPI_FIQ_DUMMY69 (GPI_FIQ_START + 69) ++#define INT_GPI_FIQ_DUMMY70 (GPI_FIQ_START + 70) ++#define INT_GPI_FIQ_DUMMY71 (GPI_FIQ_START + 71) ++#define INT_GPI_FIQ_DUMMY72 (GPI_FIQ_START + 72) ++#define INT_GPI_FIQ_DUMMY73 (GPI_FIQ_START + 73) ++#define INT_GPI_FIQ_DUMMY74 (GPI_FIQ_START + 74) ++#define INT_GPI_FIQ_DUMMY75 (GPI_FIQ_START + 75) ++#define GPI_FIQ_END (GPI_FIQ_START + 76) ++#define GPI_FIQ_NUM (GPI_FIQ_END - GPI_FIQ_START) ++ ++#define GPI_IRQ_START 0 ++#define INT_GPI_IRQ_DUMMY00 (GPI_IRQ_START + 0) ++#define INT_GPI_IRQ_DUMMY01 (GPI_IRQ_START + 1) ++#define INT_GPI_IRQ_DUMMY02 (GPI_IRQ_START + 2) ++#define INT_GPI_IRQ_DUMMY03 (GPI_IRQ_START + 3) ++#define INT_GPI_IRQ_DUMMY04 (GPI_IRQ_START + 4) ++#define INT_GPI_IRQ_DUMMY05 (GPI_IRQ_START + 5) ++#define INT_GPI_IRQ_DUMMY06 (GPI_IRQ_START + 6) ++#define INT_GPI_IRQ_DUMMY07 (GPI_IRQ_START + 7) ++#define GPI_IRQ_END (GPI_IRQ_START + 8) ++#define GPI_IRQ_NUM (GPI_IRQ_END - GPI_IRQ_START) +diff --git a/drivers/sstar/include/infinity2/gpio.h b/drivers/sstar/include/infinity2/gpio.h +new file mode 100755 +index 000000000000..d498d3b10cbb +--- /dev/null ++++ b/drivers/sstar/include/infinity2/gpio.h +@@ -0,0 +1,304 @@ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_PM_IRIN 0 //intr ++#define PAD_PM_SPI_CZ 1 //intr ++#define PAD_PM_SPI_CK 2 //intr ++#define PAD_PM_SPI_DI 3 //intr ++#define PAD_PM_SPI_DO 4 //intr ++#define PAD_PM_SPI_WPZ 5 ++#define PAD_PM_SPI_HOLDZ 6 ++#define PAD_PM_SPI_RSTZ 7 ++#define PAD_PM_GPIO0 8 //intr ++#define PAD_PM_GPIO1 9 //intr ++#define PAD_PM_GPIO2 10 //intr ++#define PAD_PM_GPIO3 11 //intr ++#define PAD_PM_GPIO4 12 //intr ++#define PAD_PM_GPIO5 13 //intr ++#define PAD_PM_GPIO6 14 //intr ++#define PAD_PM_GPIO7 15 //intr ++#define PAD_PM_GPIO8 16 //intr ++#define PAD_PM_GPIO9 17 //intr ++#define PAD_PM_GPIO10 18 //intr ++#define PAD_PM_GPIO11 19 //intr ++#define PAD_PM_GPIO12 20 //intr ++#define PAD_PM_GPIO13 21 //intr ++#define PAD_PM_GPIO14 22 //intr ++#define PAD_PM_GPIO15 23 //intr ++#define PAD_PM_CEC 24 //intr ++#define PAD_HDMITX_HPD 25 ++#define PAD_HDMIRX_HPD 26 ++#define PAD_PM_SD30_CDZ 27 //intr ++#define PAD_PM_SD20_CDZ 28 //intr ++#define PAD_VID0 29 //intr ++#define PAD_VID1 30 //intr ++#define PAD_PM_LED0 31 //intr ++#define PAD_PM_LED1 32 //intr ++#define PAD_SAR_GPIO0 33 //?? ++#define PAD_SAR_GPIO1 34 //?? ++#define PAD_SAR_GPIO2 35 //?? ++#define PAD_SAR_GPIO3 36 //?? ++#define PAD_SAR_GPIO4 37 //?? ++#define PAD_VPLUG_IN 38 //?? ++#define PAD_PM_GPIO16 39 //intr ++#define PAD_PM_GPIO17 40 //intr ++#define PAD_PM_GPIO18 41 //intr ++#define PAD_PM_GPIO19 42 //intr ++#define PAD_PM_SPI_CZ1 43 //intr ++#define PAD_PM_SPI_CZ2 44 //intr ++#define PAD_SPDIF_OUT 45 ++#define PAD_HSYNC_OUT 46 ++#define PAD_VSYNC_OUT 47 ++#define PAD_BT_I2S_RX_BCK 48 ++#define PAD_BT_I2S_RX_WCK 49 ++#define PAD_BT_I2S_RX_SDI 50 ++#define PAD_BT_I2S_TX_SDO 51 ++#define PAD_GPIO0 52 ++#define PAD_GPIO1 53 ++#define PAD_GPIO2 54 ++#define PAD_GPIO3 55 ++#define PAD_GPIO4 56 ++#define PAD_GPIO5 57 ++#define PAD_GPIO6 58 ++#define PAD_GPIO7 59 ++#define PAD_GPIO8 60 ++#define PAD_GPIO9 61 ++#define PAD_GPIO10 62 ++#define PAD_GPIO11 63 ++#define PAD_GPIO12 64 ++#define PAD_GPIO13 65 ++#define PAD_GPIO14 66 ++#define PAD_GPIO15 67 ++#define PAD_CODEC_I2S_TX_BCK 68 ++#define PAD_CODEC_I2S_TX_WCK 69 ++#define PAD_CODEC_I2S_TX_SDO 70 ++#define PAD_CODEC_I2S_RX_MCK 71 ++#define PAD_CODEC_I2S_RX_BCK 72 ++#define PAD_CODEC_I2S_RX_WCK 73 ++#define PAD_CODEC_I2S_RX_SDI0 74 ++#define PAD_CODEC_I2S_RX_SDI1 75 ++#define PAD_CODEC_I2S_RX_SDI2 76 ++#define PAD_CODEC_I2S_RX_SDI3 77 ++#define PAD_DMIC_BCK 78 ++#define PAD_DMIC_CH0 79 ++#define PAD_DMIC_CH1 80 ++#define PAD_DMIC_CH2 81 ++#define PAD_DMIC_CH3 82 ++#define PAD_FUART_TX 83 ++#define PAD_FUART_RX 84 ++#define PAD_FUART_RTS 85 ++#define PAD_FUART_CTS 86 ++#define PAD_I2C0_SDA 87 ++#define PAD_I2C0_SCL 88 ++#define PAD_I2C2_SDA 89 ++#define PAD_I2C2_SCL 90 ++#define PAD_I2C3_SCL 91 ++#define PAD_I2C3_SDA 92 ++#define PAD_JTAG_TCK 93 ++#define PAD_JTAG_TDO 94 ++#define PAD_JTAG_TDI 95 ++#define PAD_JTAG_TMS 96 ++#define PAD_MIPI_TX_IO0 97 //OUTP_CH0 ++#define PAD_MIPI_TX_IO1 98 //OUTN_CH0 ++#define PAD_MIPI_TX_IO2 99 //OUTP_CH1 ++#define PAD_MIPI_TX_IO3 100 //OUTN_CH1 ++#define PAD_MIPI_TX_IO4 101 //OUTP_CH2 ++#define PAD_MIPI_TX_IO5 102 //OUTN_CH2 ++#define PAD_MIPI_TX_IO6 103 //OUTP_CH3 ++#define PAD_MIPI_TX_IO7 104 //OUTN_CH3 ++#define PAD_MIPI_TX_IO8 105 //OUTP_CH4 ++#define PAD_MIPI_TX_IO9 106 //OUTN_CH4 ++#define PAD_MISC_I2S_TX_BCK 107 ++#define PAD_MISC_I2S_TX_WCK 108 ++#define PAD_MISC_I2S_TX_SDO 109 ++#define PAD_MISC_I2S_RX_MCK 110 ++#define PAD_MISC_I2S_RX_BCK 111 ++#define PAD_MISC_I2S_RX_WCK 112 ++#define PAD_MISC_I2S_RX_SDI0 113 ++#define PAD_NAND_CEZ0 114 ++#define PAD_NAND_CEZ1 115 ++#define PAD_NAND_ALE 116 ++#define PAD_NAND_CLE 117 ++#define PAD_NAND_WEZ 118 ++#define PAD_NAND_WPZ 119 ++#define PAD_NAND_REZ 120 ++#define PAD_NAND_RBZ 121 ++#define PAD_NAND_DA0 122 ++#define PAD_NAND_DA1 123 ++#define PAD_NAND_DA2 124 ++#define PAD_NAND_DA3 125 ++#define PAD_NAND_DA4 126 ++#define PAD_NAND_DA5 127 ++#define PAD_NAND_DA6 128 ++#define PAD_NAND_DA7 129 ++#define PAD_NAND_DQS 130 ++#define PAD_RGMII_0_MDIO 131 ++#define PAD_RGMII_0_TX_CTL 132 ++#define PAD_RGMII_0_MDC 133 ++#define PAD_RGMII_0_TXD3 134 ++#define PAD_RGMII_0_RX_CLK 135 ++#define PAD_RGMII_0_TXD2 136 ++#define PAD_RGMII_0_RXD3 137 ++#define PAD_RGMII_0_TXD1 138 ++#define PAD_RGMII_0_RXD2 139 ++#define PAD_RGMII_0_TXD0 140 ++#define PAD_RGMII_0_RXD1 141 ++#define PAD_RGMII_0_TX_CLK 142 ++#define PAD_RGMII_0_RXD0 143 ++#define PAD_RGMII_0_RX_CTL 144 ++#define PAD_RGMII_1_TX_CTL 145 ++#define PAD_RGMII_1_RX_CLK 146 ++#define PAD_RGMII_1_TXD3 147 ++#define PAD_RGMII_1_RXD3 148 ++#define PAD_RGMII_1_TXD2 149 ++#define PAD_RGMII_1_RXD2 150 ++#define PAD_RGMII_1_TXD1 151 ++#define PAD_RGMII_1_RXD1 152 ++#define PAD_RGMII_1_TXD0 153 ++#define PAD_RGMII_1_RXD0 154 ++#define PAD_RGMII_1_TX_CLK 155 ++#define PAD_RGMII_1_RX_CTL 156 ++#define PAD_PWM0 157 ++#define PAD_PWM1 158 ++#define PAD_SD_CLK 159 ++#define PAD_SD_CMD 160 ++#define PAD_SD_D0 161 ++#define PAD_SD_D1 162 ++#define PAD_SD_D2 163 ++#define PAD_SD_D3 164 ++#define PAD_SD30_IO0 165 ++#define PAD_SD30_IO1 166 ++#define PAD_SD30_IO2 167 ++#define PAD_SD30_IO3 168 ++#define PAD_SD30_IO4 169 ++#define PAD_SD30_IO5 170 ++#define PAD_SNR0_D0 171 ++#define PAD_SNR0_D1 172 ++#define PAD_SNR0_D2 173 ++#define PAD_SNR0_D3 174 ++#define PAD_SNR0_D4 175 ++#define PAD_SNR0_D5 176 ++#define PAD_SNR0_D6 177 ++#define PAD_SNR0_D7 178 ++#define PAD_SNR0_D8 179 ++#define PAD_SNR0_D9 180 ++#define PAD_SNR0_GPIO0 181 ++#define PAD_SNR0_GPIO1 182 ++#define PAD_SNR0_GPIO2 183 ++#define PAD_SNR0_GPIO3 184 ++#define PAD_SNR0_GPIO4 185 ++#define PAD_SNR0_GPIO5 186 ++#define PAD_SNR0_GPIO6 187 ++#define PAD_SNR0_GPIO7 188 ++#define PAD_SNR1_D0 189 ++#define PAD_SNR1_D1 190 ++#define PAD_SNR1_D2 191 ++#define PAD_SNR1_D3 192 ++#define PAD_SNR1_D4 193 ++#define PAD_SNR1_D5 194 ++#define PAD_SNR1_D6 195 ++#define PAD_SNR1_D7 196 ++#define PAD_SNR1_D8 197 ++#define PAD_SNR1_D9 198 ++#define PAD_SNR1_GPIO0 199 ++#define PAD_SNR1_GPIO1 200 ++#define PAD_SNR1_GPIO2 201 ++#define PAD_SNR1_GPIO3 202 ++#define PAD_SNR1_GPIO4 203 ++#define PAD_SNR1_GPIO5 204 ++#define PAD_SNR1_GPIO6 205 ++#define PAD_SNR1_GPIO7 206 ++#define PAD_SNR2_D0 207 ++#define PAD_SNR2_D1 208 ++#define PAD_SNR2_D2 209 ++#define PAD_SNR2_D3 210 ++#define PAD_SNR2_D4 211 ++#define PAD_SNR2_D5 212 ++#define PAD_SNR2_D6 213 ++#define PAD_SNR2_D7 214 ++#define PAD_SNR2_D8 215 ++#define PAD_SNR2_D9 216 ++#define PAD_SNR2_GPIO0 217 ++#define PAD_SNR2_GPIO1 218 ++#define PAD_SNR2_GPIO2 219 ++#define PAD_SNR2_GPIO3 220 ++#define PAD_SNR2_GPIO4 221 ++#define PAD_SNR2_GPIO5 222 ++#define PAD_SNR2_GPIO6 223 ++#define PAD_SNR2_GPIO7 224 ++#define PAD_SNR3_D0 225 ++#define PAD_SNR3_D1 226 ++#define PAD_SNR3_D2 227 ++#define PAD_SNR3_D3 228 ++#define PAD_SNR3_D4 229 ++#define PAD_SNR3_D5 230 ++#define PAD_SNR3_D6 231 ++#define PAD_SNR3_D7 232 ++#define PAD_SNR3_D8 233 ++#define PAD_SNR3_D9 234 ++#define PAD_SNR3_GPIO0 235 ++#define PAD_SNR3_GPIO1 236 ++#define PAD_SNR3_GPIO2 237 ++#define PAD_SNR3_GPIO3 238 ++#define PAD_SNR3_GPIO4 239 ++#define PAD_SNR3_GPIO5 240 ++#define PAD_SNR3_GPIO6 241 ++#define PAD_SNR3_GPIO7 242 ++#define PAD_SPI0_CK 243 ++#define PAD_SPI0_CZ0 244 ++#define PAD_SPI0_DO 245 ++#define PAD_SPI0_DI 246 ++#define PAD_SPI1_CK 247 ++#define PAD_SPI1_CZ0 248 ++#define PAD_SPI1_DO 249 ++#define PAD_SPI1_DI 250 ++#define PAD_SPI2_CZ0 251 ++#define PAD_SPI2_CK 252 ++#define PAD_SPI2_DI 253 ++#define PAD_SPI2_DO 254 ++#define PAD_TTL_HSYNC 255 ++#define PAD_TTL_VSYNC 256 ++#define PAD_TTL_CLK 257 ++#define PAD_TTL_DE 258 ++#define PAD_TTL_D0 259 ++#define PAD_TTL_D1 260 ++#define PAD_TTL_D2 261 ++#define PAD_TTL_D3 262 ++#define PAD_TTL_D4 263 ++#define PAD_TTL_D5 264 ++#define PAD_TTL_D6 265 ++#define PAD_TTL_D7 266 ++#define PAD_TTL_D8 267 ++#define PAD_TTL_D9 268 ++#define PAD_TTL_D10 269 ++#define PAD_TTL_D11 270 ++#define PAD_TTL_D12 271 ++#define PAD_TTL_D13 272 ++#define PAD_TTL_D14 273 ++#define PAD_TTL_D15 274 ++#define PAD_TTL_D16 275 ++#define PAD_TTL_D17 276 ++#define PAD_TTL_D18 277 ++#define PAD_TTL_D19 278 ++#define PAD_TTL_D20 279 ++#define PAD_TTL_D21 280 ++#define PAD_TTL_D22 281 ++#define PAD_TTL_D23 282 ++#define PAD_TTL_GPIO0 283 ++#define PAD_TTL_GPIO1 284 ++#define PAD_TTL_GPIO2 285 ++#define PAD_UART0_RX 286 ++#define PAD_UART0_TX 287 ++#define PAD_UART1_RX 288 ++#define PAD_UART1_TX 289 ++#define PAD_UART2_RX 290 ++#define PAD_UART2_TX 291 ++#define PAD_HDMITX_SCL 292 ++#define PAD_HDMITX_SDA 293 ++#define PAD_HDMITX_ARC 294 ++ ++#define GPIO_NR 295 ++#define PAD_UNKNOWN 0xFFFF ++ ++#endif // #ifndef ___GPIO_H ++ +diff --git a/drivers/sstar/include/infinity2/irqs.h b/drivers/sstar/include/infinity2/irqs.h +new file mode 100755 +index 000000000000..31002f2ed996 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/irqs.h +@@ -0,0 +1,548 @@ ++/*------------------------------------------------------------------------------ ++ Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++------------------------------------------------------------------------------*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 95 : SPI:MS_IRQ0 ++ ID 96 - 159 : SPI:MS_FIQ0 ++ ID 160 - 191 : SPI:Debug/Profiling(ARM_INTERNAL named in I3) ++ ID 192 - 255 : SPI:MS_IRQ1 ++ ID 256 - 319 : SPI:MS_FIQ1 ++*/ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR) ++ ++//for GIC_ID ++#define GIC_ID_LEGACY_FIQ 0x1C ++#define GIC_ID_LEGACY_IRQ 0x1F ++#define GIC_ID_LOCAL_TIMER_IRQ 0x1D ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++ if need to get the interrupt number for request_irq(), manual calculate the number is ++ GIC_SGI_NR+GIC_PPI_NR+X=32+X ++ NOTE: We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 */ ++ ++/* MS_NON_PM_IRQ SPI_ID:0-63 */ ++#define GIC_SPI_MS_IRQ_START (0) ++#define INT_IRQ_00_INT_UART0 (GIC_SPI_MS_IRQ_START + 0) // gic 32 spi 0 ++#define INT_IRQ_01_MIIC1_INT (GIC_SPI_MS_IRQ_START + 1) // gic 33 spi 1 ++#define INT_IRQ_02_USB30M1_SS_INT (GIC_SPI_MS_IRQ_START + 2) // gic 34 spi 2 ++#define INT_IRQ_03_USB30M1_HS_UHC_INT (GIC_SPI_MS_IRQ_START + 3) // gic 35 spi 3 ++#define INT_IRQ_04_TILDE_REG_TOP_GPIO_IN_2 (GIC_SPI_MS_IRQ_START + 4) // gic 36 spi 4 ++#define INT_IRQ_05_U3D_INT (GIC_SPI_MS_IRQ_START + 5) // gic 37 spi 5 ++#define INT_IRQ_06_USB_INT (GIC_SPI_MS_IRQ_START + 6) // gic 38 spi 6 ++#define INT_IRQ_07_UHC_INT (GIC_SPI_MS_IRQ_START + 7) // gic 39 spi 7 ++#define INT_IRQ_08_REG_CMDQ_DUMMY_15 (GIC_SPI_MS_IRQ_START + 8) // gic 40 spi 8 ++#define INT_IRQ_09_GMAC_INT (GIC_SPI_MS_IRQ_START + 9) // gic 41 spi 9 ++#define INT_IRQ_10_DISP_INT (GIC_SPI_MS_IRQ_START + 10) // gic 42 spi 10 ++#define INT_IRQ_11_RESERVED (GIC_SPI_MS_IRQ_START + 11) // gic 43 spi 11 ++#define INT_IRQ_12_MSPI_INT (GIC_SPI_MS_IRQ_START + 12) // gic 44 spi 12 ++#define INT_IRQ_13_EVD_INT (GIC_SPI_MS_IRQ_START + 13) // gic 45 spi 13 ++#define INT_IRQ_14_SATA_PHY_IRQ (GIC_SPI_MS_IRQ_START + 14) // gic 46 spi 14 ++#define INT_IRQ_15_SATA_INTRQ (GIC_SPI_MS_IRQ_START + 15) // gic 47 spi 15 ++#define INT_IRQ_16_SATA_P1_INTRQ (GIC_SPI_MS_IRQ_START + 16) // gic 48 spi 16 ++#define INT_IRQ_17_VE_INT (GIC_SPI_MS_IRQ_START + 17) // gic 49 spi 17 ++#define INT_IRQ_18_IRQ_AEON2HI (GIC_SPI_MS_IRQ_START + 18) // gic 50 spi 18 ++#define INT_IRQ_19_DC_INT (GIC_SPI_MS_IRQ_START + 19) // gic 51 spi 19 ++#define INT_IRQ_20_GOP_INT (GIC_SPI_MS_IRQ_START + 20) // gic 52 spi 20 ++#define INT_IRQ_21_PCM2MCU_INT (GIC_SPI_MS_IRQ_START + 21) // gic 53 spi 21 ++#define INT_IRQ_22_MIIC0_INT (GIC_SPI_MS_IRQ_START + 22) // gic 54 spi 22 ++#define INT_IRQ_23_RTC0_INT (GIC_SPI_MS_IRQ_START + 23) // gic 55 spi 23 ++#define INT_IRQ_24_KEYPAD_INT (GIC_SPI_MS_IRQ_START + 24) // gic 56 spi 24 ++#define INT_IRQ_25_PM_INT (GIC_SPI_MS_IRQ_START + 25) // gic 57 spi 25 ++#define INT_IRQ_26_MFE_INT (GIC_SPI_MS_IRQ_START + 26) // gic 58 spi 26 ++#define INT_IRQ_27_REG_CMDQ2_DUMMY_15 (GIC_SPI_MS_IRQ_START + 27) // gic 59 spi 27 ++#define INT_IRQ_28_REG_CMDQ3_DUMMY_15 (GIC_SPI_MS_IRQ_START + 28) // gic 60 spi 28 ++#define INT_IRQ_29_RTC1_INT (GIC_SPI_MS_IRQ_START + 29) // gic 61 spi 29 ++#define INT_IRQ_30_SECGMAC_INT (GIC_SPI_MS_IRQ_START + 30) // gic 62 spi 30 ++#define INT_IRQ_31_RESERVED (GIC_SPI_MS_IRQ_START + 31) // gic 63 spi 31 ++#define INT_IRQ_32_REG_CMDQ4_DUMMY_15 (GIC_SPI_MS_IRQ_START + 32) // gic 64 spi 32 ++#define INT_IRQ_33_USB_INT1 (GIC_SPI_MS_IRQ_START + 33) // gic 65 spi 33 ++#define INT_IRQ_34_UHC_INT1 (GIC_SPI_MS_IRQ_START + 34) // gic 66 spi 34 ++#define INT_IRQ_35_MIU_INT (GIC_SPI_MS_IRQ_START + 35) // gic 67 spi 35 ++#define INT_IRQ_36_ERROR_RESP_INT (GIC_SPI_MS_IRQ_START + 36) // gic 68 spi 36 ++#define INT_IRQ_37_OTG_INT_P0 (GIC_SPI_MS_IRQ_START + 37) // gic 69 spi 37 ++#define INT_IRQ_38_U3_PCIE_PHY_IRQ_OUT (GIC_SPI_MS_IRQ_START + 38) // gic 70 spi 38 ++#define INT_IRQ_39_INT_UART1 (GIC_SPI_MS_IRQ_START + 39) // gic 71 spi 39 ++#define INT_IRQ_40_HVD_INT (GIC_SPI_MS_IRQ_START + 40) // gic 72 spi 40 ++#define INT_IRQ_41_REG_TOP_GPIO_IN_4 (GIC_SPI_MS_IRQ_START + 41) // gic 73 spi 41 ++#define INT_IRQ_42_TILDE_REG_TOP_GPIO_IN_4 (GIC_SPI_MS_IRQ_START + 42) // gic 74 spi 42 ++#define INT_IRQ_43_GMAC_TX_INT (GIC_SPI_MS_IRQ_START + 43) // gic 75 spi 43 ++#define INT_IRQ_44_SECGMAC_TX_INT (GIC_SPI_MS_IRQ_START + 44) // gic 76 spi 44 ++#define INT_IRQ_45_JPD_INT (GIC_SPI_MS_IRQ_START + 45) // gic 77 spi 45 ++#define INT_IRQ_46_DISP1_INT (GIC_SPI_MS_IRQ_START + 46) // gic 78 spi 46 ++#define INT_IRQ_47_PWD_STATUS_INT (GIC_SPI_MS_IRQ_START + 47) // gic 79 spi 47 ++#define INT_IRQ_48_INT_BDMA_0 (GIC_SPI_MS_IRQ_START + 48) // gic 80 spi 48 ++#define INT_IRQ_49_INT_BDMA_1 (GIC_SPI_MS_IRQ_START + 49) // gic 81 spi 49 ++#define INT_IRQ_50_UART2MCU_INTR (GIC_SPI_MS_IRQ_START + 50) // gic 82 spi 50 ++#define INT_IRQ_51_URDMA2MCU_INTR (GIC_SPI_MS_IRQ_START + 51) // gic 83 spi 51 ++#define INT_IRQ_52_DVI_HDMI_HDCP_INT (GIC_SPI_MS_IRQ_START + 52) // gic 84 spi 52 ++#define INT_IRQ_53_CEC_IRQ_OUT (GIC_SPI_MS_IRQ_START + 53) // gic 85 spi 53 ++#define INT_IRQ_54_HDMITX_IRQ_LEVEL (GIC_SPI_MS_IRQ_START + 54) // gic 86 spi 54 ++#define INT_IRQ_55_FCIE_INT (GIC_SPI_MS_IRQ_START + 55) // gic 87 spi 55 ++#define INT_IRQ_56_RESERVED (GIC_SPI_MS_IRQ_START + 56) // gic 88 spi 56 ++#define INT_IRQ_57_REG_CMDQ5_DUMMY (GIC_SPI_MS_IRQ_START + 57) // gic 89 spi 57 ++#define INT_IRQ_58_SAR1_INT (GIC_SPI_MS_IRQ_START + 58) // gic 90 spi 58 ++#define INT_IRQ_59_IRQ_DAC_PLUG_DET (GIC_SPI_MS_IRQ_START + 59) // gic 91 spi 59 ++#define INT_IRQ_60_REG_TOP_GPIO_IN_2 (GIC_SPI_MS_IRQ_START + 60) // gic 92 spi 60 ++#define INT_IRQ_61_RESERVED (GIC_SPI_MS_IRQ_START + 61) // gic 93 spi 61 ++#define INT_IRQ_62_FI_QUEUE_INT (GIC_SPI_MS_IRQ_START + 62) // gic 94 spi 62 ++#define INT_IRQ_63_IRQ_FRM_PM (GIC_SPI_MS_IRQ_START + 63) // gic 95 spi 63 ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++ ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ SPI_ID:64-127 */ ++#define GIC_SPI_MS_FIQ_START (GIC_SPI_MS_IRQ_END) ++#define INT_FIQ_00_INT_TIMER0 (GIC_SPI_MS_FIQ_START + 0) // gic 96 spi 64 ++#define INT_FIQ_01_INT_TIMER1 (GIC_SPI_MS_FIQ_START + 1) // gic 97 spi 65 ++#define INT_FIQ_02_INT_WDT (GIC_SPI_MS_FIQ_START + 2) // gic 98 spi 66 ++#define INT_FIQ_03_INT_SEC_TIMER0 (GIC_SPI_MS_FIQ_START + 3) // gic 99 spi 67 ++#define INT_FIQ_04_INT_SEC_TIMER1 (GIC_SPI_MS_FIQ_START + 4) // gic 100 spi 68 ++#define INT_FIQ_05_RESERVED (GIC_SPI_MS_FIQ_START + 5) // gic 101 spi 69 ++#define INT_FIQ_06_RESERVED (GIC_SPI_MS_FIQ_START + 6) // gic 102 spi 70 ++#define INT_FIQ_07_RESERVED (GIC_SPI_MS_FIQ_START + 7) // gic 103 spi 71 ++#define INT_FIQ_08_RESERVED (GIC_SPI_MS_FIQ_START + 8) // gic 104 spi 72 ++#define INT_FIQ_09_RESERVED (GIC_SPI_MS_FIQ_START + 9) // gic 105 spi 73 ++#define INT_FIQ_10_RESERVED (GIC_SPI_MS_FIQ_START + 10) // gic 106 spi 74 ++#define INT_FIQ_11_RESERVED (GIC_SPI_MS_FIQ_START + 11) // gic 107 spi 75 ++#define INT_FIQ_12_RESERVED (GIC_SPI_MS_FIQ_START + 12) // gic 108 spi 76 ++#define INT_FIQ_13_LAN_ESD_INT (GIC_SPI_MS_FIQ_START + 13) // gic 109 spi 77 ++#define INT_FIQ_14_RESERVED (GIC_SPI_MS_FIQ_START + 14) // gic 110 spi 78 ++#define INT_FIQ_15_RESERVED (GIC_SPI_MS_FIQ_START + 15) // gic 111 spi 79 ++#define INT_FIQ_16_RESERVED (GIC_SPI_MS_FIQ_START + 16) // gic 112 spi 80 ++#define INT_FIQ_17_RESERVED (GIC_SPI_MS_FIQ_START + 17) // gic 113 spi 81 ++#define INT_FIQ_18_RESERVED (GIC_SPI_MS_FIQ_START + 18) // gic 114 spi 82 ++#define INT_FIQ_19_XIU_TIMEOUT_INT (GIC_SPI_MS_FIQ_START + 19) // gic 115 spi 83 ++#define INT_FIQ_20_RESERVED (GIC_SPI_MS_FIQ_START + 20) // gic 116 spi 84 ++#define INT_FIQ_21_VE_VBI_F0_INT (GIC_SPI_MS_FIQ_START + 21) // gic 117 spi 85 ++#define INT_FIQ_22_VE_VBI_F1_INT (GIC_SPI_MS_FIQ_START + 22) // gic 118 spi 86 ++#define INT_FIQ_23_RESERVED (GIC_SPI_MS_FIQ_START + 23) // gic 119 spi 87 ++#define INT_FIQ_24_VE_DONE_TT_IRQ (GIC_SPI_MS_FIQ_START + 24) // gic 120 spi 88 ++#define INT_FIQ_25_RESERVED (GIC_SPI_MS_FIQ_START + 25) // gic 121 spi 89 ++#define INT_FIQ_26_RESERVED (GIC_SPI_MS_FIQ_START + 26) // gic 122 spi 90 ++#define INT_FIQ_27_IR_INT (GIC_SPI_MS_FIQ_START + 27) // gic 123 spi 91 ++#define INT_FIQ_28_RESERVED (GIC_SPI_MS_FIQ_START + 28) // gic 124 spi 92 ++#define INT_FIQ_29_RESERVED (GIC_SPI_MS_FIQ_START + 29) // gic 125 spi 93 ++#define INT_FIQ_30_RESERVED (GIC_SPI_MS_FIQ_START + 30) // gic 126 spi 94 ++#define INT_FIQ_31_RESERVED (GIC_SPI_MS_FIQ_START + 31) // gic 127 spi 95 ++#define INT_FIQ_32_IR_INT_RC (GIC_SPI_MS_FIQ_START + 32) // gic 128 spi 96 ++#define INT_FIQ_33_RESERVED (GIC_SPI_MS_FIQ_START + 33) // gic 129 spi 97 ++#define INT_FIQ_34_VE_SW_WR2BUF_INT (GIC_SPI_MS_FIQ_START + 34) // gic 130 spi 98 ++#define INT_FIQ_35_RESERVED (GIC_SPI_MS_FIQ_START + 35) // gic 131 spi 99 ++#define INT_FIQ_36_REG_HST0TO3_INT (GIC_SPI_MS_FIQ_START + 36) // gic 132 spi 100 ++#define INT_FIQ_37_REG_HST0TO2_INT (GIC_SPI_MS_FIQ_START + 37) // gic 133 spi 101 ++#define INT_FIQ_38_REG_HST0TO1_INT (GIC_SPI_MS_FIQ_START + 38) // gic 134 spi 102 ++#define INT_FIQ_39_REG_HST0TO4_IN (GIC_SPI_MS_FIQ_START + 39) // gic 135 spi 103 ++#define INT_FIQ_40_REG_HST1TO3_INT (GIC_SPI_MS_FIQ_START + 40) // gic 136 spi 104 ++#define INT_FIQ_41_REG_HST1TO2_INT (GIC_SPI_MS_FIQ_START + 41) // gic 137 spi 105 ++#define INT_FIQ_42_REG_HST1TO0_INT (GIC_SPI_MS_FIQ_START + 42) // gic 138 spi 106 ++#define INT_FIQ_43_REG_HST1TO4_INT (GIC_SPI_MS_FIQ_START + 43) // gic 139 spi 107 ++#define INT_FIQ_44_REG_HST2TO3_INT (GIC_SPI_MS_FIQ_START + 44) // gic 140 spi 108 ++#define INT_FIQ_45_REG_HST2TO1_INT (GIC_SPI_MS_FIQ_START + 45) // gic 141 spi 109 ++#define INT_FIQ_46_REG_HST2TO0_INT (GIC_SPI_MS_FIQ_START + 46) // gic 142 spi 110 ++#define INT_FIQ_47_REG_HST2TO4_INT (GIC_SPI_MS_FIQ_START + 47) // gic 143 spi 111 ++#define INT_FIQ_48_REG_HST3TO2_INT (GIC_SPI_MS_FIQ_START + 48) // gic 144 spi 112 ++#define INT_FIQ_49_REG_HST3TO1_INT (GIC_SPI_MS_FIQ_START + 49) // gic 145 spi 113 ++#define INT_FIQ_50_REG_HST3TO0_INT (GIC_SPI_MS_FIQ_START + 50) // gic 146 spi 114 ++#define INT_FIQ_51_REG_HST3TO4_INT (GIC_SPI_MS_FIQ_START + 51) // gic 147 spi 115 ++#define INT_FIQ_52_RESERVED (GIC_SPI_MS_FIQ_START + 52) // gic 148 spi 116 ++#define INT_FIQ_53_RESERVED (GIC_SPI_MS_FIQ_START + 53) // gic 149 spi 117 ++#define INT_FIQ_54_HDMITX_IRQ_EDGE (GIC_SPI_MS_FIQ_START + 54) // gic 150 spi 118 ++#define INT_FIQ_55_RESERVED (GIC_SPI_MS_FIQ_START + 55) // gic 151 spi 119 ++#define INT_FIQ_56_RESERVED (GIC_SPI_MS_FIQ_START + 56) // gic 152 spi 120 ++#define INT_FIQ_57_REG_HST4TO3_INT (GIC_SPI_MS_FIQ_START + 57) // gic 153 spi 121 ++#define INT_FIQ_58_REG_HST4TO2_INT (GIC_SPI_MS_FIQ_START + 58) // gic 154 spi 122 ++#define INT_FIQ_59_REG_HST4TO1_INT (GIC_SPI_MS_FIQ_START + 59) // gic 155 spi 123 ++#define INT_FIQ_60_REG_HST4TO0_INT (GIC_SPI_MS_FIQ_START + 60) // gic 156 spi 124 ++#define INT_FIQ_61_RESERVED (GIC_SPI_MS_FIQ_START + 61) // gic 157 spi 125 ++#define INT_FIQ_62_RESERVED (GIC_SPI_MS_FIQ_START + 62) // gic 158 spi 126 ++#define INT_FIQ_63_FIQ_FRM_PM (GIC_SPI_MS_FIQ_START + 63) // gic 159 spi 127 //Timer2!! ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 64) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++/* SPI_ID:128-159 */ ++#define GIC_SPI_MS_EXT_START (GIC_SPI_MS_FIQ_END) ++#define INT_160_1_b0 (GIC_SPI_MS_EXT_START + 0) // gic 160 spi 128 ++#define INT_161_1_b0 (GIC_SPI_MS_EXT_START + 1) // gic 161 spi 129 ++#define INT_162_IRQ_IN_0 (GIC_SPI_MS_EXT_START + 2) // gic 162 spi 130 ++#define INT_163_IRQ_IN_1 (GIC_SPI_MS_EXT_START + 3) // gic 163 spi 131 ++#define INT_164_FIQ_IN_0 (GIC_SPI_MS_EXT_START + 4) // gic 164 spi 132 ++#define INT_165_FIQ_IN_1 (GIC_SPI_MS_EXT_START + 5) // gic 165 spi 133 ++#define INT_166_INT_MERGE_0 (GIC_SPI_MS_EXT_START + 6) // gic 166 spi 134 ++#define INT_167_INT_MERGE_1 (GIC_SPI_MS_EXT_START + 7) // gic 167 spi 135 ++#define INT_168_REG_DUMMY_ECO_1_0 (GIC_SPI_MS_EXT_START + 8) // gic 168 spi 136 ++#define INT_169_REG_DUMMY_ECO_1_1 (GIC_SPI_MS_EXT_START + 9) // gic 169 spi 137 ++#define INT_170_1_b0 (GIC_SPI_MS_EXT_START + 10) // gic 170 spi 138 ++#define INT_171_RXIU_TIMEOUT_INT (GIC_SPI_MS_EXT_START + 11) // gic 171 spi 139 ++#define INT_172_SCUEVABORT_INTR (GIC_SPI_MS_EXT_START + 12) // gic 172 spi 140 ++#define INT_173_L2_INTR (GIC_SPI_MS_EXT_START + 13) // gic 173 spi 141 ++#define INT_174_DEFLAGS0_INTR_0 (GIC_SPI_MS_EXT_START + 14) // gic 174 spi 142 ++#define INT_175_DEFLAGS0_INTR_1 (GIC_SPI_MS_EXT_START + 15) // gic 175 spi 143 ++#define INT_176_DEFLAGS0_INTR_2 (GIC_SPI_MS_EXT_START + 16) // gic 176 spi 144 ++#define INT_177_DEFLAGS0_INTR_3 (GIC_SPI_MS_EXT_START + 17) // gic 177 spi 145 ++#define INT_178_DEFLAGS0_INTR_4 (GIC_SPI_MS_EXT_START + 18) // gic 178 spi 146 ++#define INT_179_DEFLAGS0_INTR_5 (GIC_SPI_MS_EXT_START + 19) // gic 179 spi 147 ++#define INT_180_DEFLAGS0_INTR_6 (GIC_SPI_MS_EXT_START + 20) // gic 180 spi 148 ++#define INT_181_CTI_INTR_XOR_0 (GIC_SPI_MS_EXT_START + 21) // gic 181 spi 149 ++#define INT_182_PMU_IRQ_0 (GIC_SPI_MS_EXT_START + 22) // gic 182 spi 150 ++#define INT_183_DEFLAGS1_INTR_0 (GIC_SPI_MS_EXT_START + 23) // gic 183 spi 151 ++#define INT_184_DEFLAGS1_INTR_1 (GIC_SPI_MS_EXT_START + 24) // gic 184 spi 152 ++#define INT_185_DEFLAGS1_INTR_2 (GIC_SPI_MS_EXT_START + 25) // gic 185 spi 153 ++#define INT_186_DEFLAGS1_INTR_3 (GIC_SPI_MS_EXT_START + 26) // gic 186 spi 154 ++#define INT_187_DEFLAGS1_INTR_4 (GIC_SPI_MS_EXT_START + 27) // gic 187 spi 155 ++#define INT_188_DEFLAGS1_INTR_5 (GIC_SPI_MS_EXT_START + 28) // gic 188 spi 156 ++#define INT_189_DEFLAGS1_INTR_6 (GIC_SPI_MS_EXT_START + 29) // gic 189 spi 157 ++#define INT_190_CTI_INTR_XOR_1 (GIC_SPI_MS_EXT_START + 30) // gic 190 spi 158 ++#define INT_191_PMU_IRQ_1 (GIC_SPI_MS_EXT_START + 31) // gic 191 spi 159 ++#define GIC_SPI_MS_EXT_END (GIC_SPI_MS_EXT_START + 32) // gic 192 spi 160 ++#define GIC_SPI_MS_EXT_NR (GIC_SPI_MS_EXT_END - GIC_SPI_MS_EXT_START) ++ ++/*IRQ1 :0*/ ++#define GIC_SPI_MS_IRQ1_START (GIC_SPI_MS_EXT_END) ++#define INT_IRQ_64_MIIC2_INT (GIC_SPI_MS_IRQ1_START + 0) // gic 192 spi 160 ++#define INT_IRQ_65_MIIC3_INT (GIC_SPI_MS_IRQ1_START + 1) // gic 193 spi 161 ++#define INT_IRQ_66_MIIC4_INT (GIC_SPI_MS_IRQ1_START + 2) // gic 194 spi 162 ++#define INT_IRQ_67_RESERVED (GIC_SPI_MS_IRQ1_START + 3) // gic 195 spi 163 ++#define INT_IRQ_68_HDMITX_PHY_INT (GIC_SPI_MS_IRQ1_START + 4) // gic 196 spi 164 ++#define INT_IRQ_69_GE_INT (GIC_SPI_MS_IRQ1_START + 5) // gic 197 spi 165 ++#define INT_IRQ_70_MIU_SECURITY_INT (GIC_SPI_MS_IRQ1_START + 6) // gic 198 spi 166 ++#define INT_IRQ_71_U3_PHY_IRQ_OUT (GIC_SPI_MS_IRQ1_START + 7) // gic 199 spi 167 ++#define INT_IRQ_72_G3D2MCU_IRQ_DFT (GIC_SPI_MS_IRQ1_START + 8) // gic 200 spi 168 ++#define INT_IRQ_73_CMDQ_INT (GIC_SPI_MS_IRQ1_START + 9) // gic 201 spi 169 ++#define INT_IRQ_74_CMDQ3_INT (GIC_SPI_MS_IRQ1_START + 10) // gic 202 spi 170 ++#define INT_IRQ_75_SCDC_INT_PM (GIC_SPI_MS_IRQ1_START + 11) // gic 203 spi 171 ++#define INT_IRQ_76_MSPI2_INT (GIC_SPI_MS_IRQ1_START + 12) // gic 204 spi 172 ++#define INT_IRQ_77_CEVA2RIU_INT (GIC_SPI_MS_IRQ1_START + 13) // gic 205 spi 173 ++#define INT_IRQ_78_WARP2RIU_INT (GIC_SPI_MS_IRQ1_START + 14) // gic 206 spi 174 ++#define INT_IRQ_79_DCSUB_INT (GIC_SPI_MS_IRQ1_START + 15) // gic 207 spi 175 ++#define INT_IRQ_80_SDIO_INT (GIC_SPI_MS_IRQ1_START + 16) // gic 208 spi 176 ++#define INT_IRQ_81_USB30_SS_INT (GIC_SPI_MS_IRQ1_START + 17) // gic 209 spi 177 ++#define INT_IRQ_82_MIU_CMA_CLR_INT (GIC_SPI_MS_IRQ1_START + 18) // gic 210 spi 178 ++#define INT_IRQ_83_VIF_INT (GIC_SPI_MS_IRQ1_START + 19) // gic 211 spi 179 ++#define INT_IRQ_84_USB30_HS_USB_INT (GIC_SPI_MS_IRQ1_START + 20) // gic 212 spi 180 ++#define INT_IRQ_85_USB30_HS_UHC_INT (GIC_SPI_MS_IRQ1_START + 21) // gic 213 spi 181 ++#define INT_IRQ_86_RXIU_TIMEOUT_NODEF_INT (GIC_SPI_MS_IRQ1_START + 22) // gic 214 spi 182 ++#define INT_IRQ_87_MIPI_TX_INT (GIC_SPI_MS_IRQ1_START + 23) // gic 215 spi 183 ++#define INT_IRQ_88_RESERVED (GIC_SPI_MS_IRQ1_START + 24) // gic 216 spi 184 ++#define INT_IRQ_89_CMDQ5_INT (GIC_SPI_MS_IRQ1_START + 25) // gic 217 spi 185 ++#define INT_IRQ_90_CMDQ4_INT (GIC_SPI_MS_IRQ1_START + 26) // gic 218 spi 186 ++#define INT_IRQ_91_RESERVED (GIC_SPI_MS_IRQ1_START + 27) // gic 219 spi 187 ++#define INT_IRQ_92_MIU_TLB_INT (GIC_SPI_MS_IRQ1_START + 28) // gic 220 spi 188 ++#define INT_IRQ_93_DIPW_INT (GIC_SPI_MS_IRQ1_START + 29) // gic 221 spi 189 ++#define INT_IRQ_94_EMAC_INT (GIC_SPI_MS_IRQ1_START + 30) // gic 222 spi 190 ++#define INT_IRQ_95_RESERVED (GIC_SPI_MS_IRQ1_START + 31) // gic 223 spi 191 ++#define INT_FIQ_64_SEC_GUARD_INT (GIC_SPI_MS_IRQ1_START + 32) // gic 224 spi 192 ++#define INT_FIQ_65_SD_CDZ_IN (GIC_SPI_MS_IRQ1_START + 33) // gic 225 spi 193 ++#define INT_IRQ_96_CORE0_MHE_INT (GIC_SPI_MS_IRQ1_START + 34) // gic 226 spi 194 ++#define INT_IRQ_97_CORE1_MFE_INT (GIC_SPI_MS_IRQ1_START + 35) // gic 227 spi 195 ++#define INT_IRQ_98_CORE1_MHE_INT (GIC_SPI_MS_IRQ1_START + 36) // gic 228 spi 196 ++#define INT_IRQ_99_INT_UART2 (GIC_SPI_MS_IRQ1_START + 37) // gic 229 spi 197 ++#define INT_IRQ_100_MSPI3_INT (GIC_SPI_MS_IRQ1_START + 38) // gic 230 spi 198 ++#define INT_IRQ_101_SD_INT (GIC_SPI_MS_IRQ1_START + 39) // gic 231 spi 199 ++#define INT_IRQ_102_SD_OSP_INT (GIC_SPI_MS_IRQ1_START + 40) // gic 232 spi 200 ++#define INT_IRQ_103_JPE_IRQ (GIC_SPI_MS_IRQ1_START + 41) // gic 233 spi 201 ++#define INT_IRQ_104_MIPI_CSI2_INT_0 (GIC_SPI_MS_IRQ1_START + 42) // gic 234 spi 202 ++#define INT_IRQ_105_MIPI_CSI2_INT_1 (GIC_SPI_MS_IRQ1_START + 43) // gic 235 spi 203 ++#define INT_IRQ_106_MIPI_CSI2_INT_2 (GIC_SPI_MS_IRQ1_START + 44) // gic 236 spi 204 ++#define INT_IRQ_107_MIPI_CSI2_INT_3 (GIC_SPI_MS_IRQ1_START + 45) // gic 237 spi 205 ++#define INT_IRQ_108_DMA2CPU_INT (GIC_SPI_MS_IRQ1_START + 46) // gic 238 spi 206 ++#define INT_IRQ_109_ISP_GOP_INT (GIC_SPI_MS_IRQ1_START + 47) // gic 239 spi 207 ++#define INT_IRQ_110_AU_INT (GIC_SPI_MS_IRQ1_START + 48) // gic 240 spi 208 ++#define INT_IRQ_111_AU_INT_GEN (GIC_SPI_MS_IRQ1_START + 49) // gic 241 spi 209 ++#define INT_IRQ_112_CMDQ_INT2 (GIC_SPI_MS_IRQ1_START + 50) // gic 242 spi 210 ++#define INT_IRQ_113_IMI_TOP_IRQ_0 (GIC_SPI_MS_IRQ1_START + 51) // gic 243 spi 211 ++#define INT_IRQ_114_IMI_TOP_IRQ_1 (GIC_SPI_MS_IRQ1_START + 52) // gic 244 spi 212 ++#define INT_IRQ_115_NOE_IRQ0 (GIC_SPI_MS_IRQ1_START + 53) // gic 245 spi 213 ++#define INT_IRQ_116_NOE_IRQ1 (GIC_SPI_MS_IRQ1_START + 54) // gic 246 spi 214 ++#define INT_IRQ_117_NOE_IRQ2 (GIC_SPI_MS_IRQ1_START + 55) // gic 247 spi 215 ++#define INT_IRQ_118_ISP_INT (GIC_SPI_MS_IRQ1_START + 56) // gic 248 spi 216 ++#define INT_IRQ_119_ISP_DMA_INT (GIC_SPI_MS_IRQ1_START + 57) // gic 249 spi 217 ++#define INT_IRQ_120_IVE_INT (GIC_SPI_MS_IRQ1_START + 58) // gic 250 spi 218 ++#define INT_IRQ_121_sc_top_int_0 (GIC_SPI_MS_IRQ1_START + 59) // gic 251 spi 219 ++#define INT_IRQ_122_sc_top_int_1 (GIC_SPI_MS_IRQ1_START + 60) // gic 252 spi 220 ++#define INT_IRQ_123_sc_top_int_2 (GIC_SPI_MS_IRQ1_START + 61) // gic 253 spi 221 ++#define INT_IRQ_124_NOT_ALLOW (GIC_SPI_MS_IRQ1_START + 62) // gic 254 spi 222 ++#define INT_IRQ_125_NOT_ALLOW (GIC_SPI_MS_IRQ1_START + 63) // gic 255 spi 223 ++//#define INT_IRQ_126_NOT_ALLOW (GIC_SPI_MS_IRQ1_START + 64) // gic 256 spi 224 ++//#define INT_IRQ_127_NOT_ALLOW (GIC_SPI_MS_IRQ1_START + 65) // gic 257 spi 225 ++#define GIC_SPI_MS_IRQ1_END (GIC_SPI_MS_IRQ1_START + 64) // gic 256 spi 224 ++#define GIC_SPI_MS_IRQ1_NR (GIC_SPI_MS_IRQ1_END - GIC_SPI_MS_IRQ1_START) ++ ++ ++ ++ ++#define GIC_SPI_MS_FIQ1_START (GIC_SPI_MS_IRQ1_END) ++//#define INT_FIQ_64_SEC_GUARD_INT (GIC_SPI_MS_FIQ1_START + 0) ++//#define INT_FIQ_65_SD_CDZ_IN (GIC_SPI_MS_FIQ1_START + 1) ++#define INT_FIQ_66_RESERVED (GIC_SPI_MS_FIQ1_START + 2) ++#define INT_FIQ_67_RESERVED (GIC_SPI_MS_FIQ1_START + 3) ++#define INT_FIQ_68_RESERVED (GIC_SPI_MS_FIQ1_START + 4) ++#define INT_FIQ_69_RESERVED (GIC_SPI_MS_FIQ1_START + 5) ++#define INT_FIQ_70_RESERVED (GIC_SPI_MS_FIQ1_START + 6) ++#define INT_FIQ_71_RESERVED (GIC_SPI_MS_FIQ1_START + 7) ++#define INT_FIQ_72_RESERVED (GIC_SPI_MS_FIQ1_START + 8) ++#define INT_FIQ_73_RESERVED (GIC_SPI_MS_FIQ1_START + 9) ++#define INT_FIQ_74_RESERVED (GIC_SPI_MS_FIQ1_START + 10) ++#define INT_FIQ_75_RESERVED (GIC_SPI_MS_FIQ1_START + 11) ++#define INT_FIQ_76_USB_INT_P0 (GIC_SPI_MS_FIQ1_START + 12) ++#define INT_FIQ_77_UHC_INT_P0 (GIC_SPI_MS_FIQ1_START + 13) ++#define INT_FIQ_78_USB30_SS_INT (GIC_SPI_MS_FIQ1_START + 14) ++#define INT_FIQ_79_OTG_INT_P0 (GIC_SPI_MS_FIQ1_START + 15) ++#define INT_FIQ_80_USB_INT_P1 (GIC_SPI_MS_FIQ1_START + 16) ++#define INT_FIQ_81_UHC_INT_P1 (GIC_SPI_MS_FIQ1_START + 17) ++#define INT_FIQ_82_RESERVED (GIC_SPI_MS_FIQ1_START + 18) ++#define INT_FIQ_83_RESERVED (GIC_SPI_MS_FIQ1_START + 19) ++#define INT_FIQ_84_USB31_HS_USB_INT (GIC_SPI_MS_FIQ1_START + 20) ++#define INT_FIQ_85_USB30_HS_UHC_INT (GIC_SPI_MS_FIQ1_START + 21) ++#define INT_FIQ_86_RESERVED (GIC_SPI_MS_FIQ1_START + 22) ++#define INT_FIQ_87_RESERVED (GIC_SPI_MS_FIQ1_START + 23) ++#define INT_FIQ_88_RESERVED (GIC_SPI_MS_FIQ1_START + 24) ++#define INT_FIQ_89_RESERVED (GIC_SPI_MS_FIQ1_START + 25) ++#define INT_FIQ_90_RESERVED (GIC_SPI_MS_FIQ1_START + 26) ++#define INT_FIQ_91_RESERVED (GIC_SPI_MS_FIQ1_START + 27) ++#define INT_FIQ_92_RESERVED (GIC_SPI_MS_FIQ1_START + 28) ++#define INT_FIQ_93_RESERVED (GIC_SPI_MS_FIQ1_START + 29) ++#define INT_FIQ_94_RESERVED (GIC_SPI_MS_FIQ1_START + 30) ++#define INT_FIQ_95_RESERVED (GIC_SPI_MS_FIQ1_START + 31) ++#define INT_FIQ_96_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 32) ++#define INT_FIQ_97_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 33) ++#define INT_FIQ_98_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 34) ++#define INT_FIQ_99_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 35) ++#define INT_FIQ_100_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 36) ++#define INT_FIQ_101_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 37) ++#define INT_FIQ_102_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 38) ++#define INT_FIQ_103_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 39) ++#define INT_FIQ_104_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 40) ++#define INT_FIQ_105_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 41) ++#define INT_FIQ_106_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 42) ++#define INT_FIQ_107_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 43) ++#define INT_FIQ_108_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 44) ++#define INT_FIQ_109_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 45) ++#define INT_FIQ_110_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 46) ++#define INT_FIQ_111_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 47) ++#define INT_FIQ_112_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 48) ++#define INT_FIQ_113_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 49) ++#define INT_FIQ_114_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 50) ++#define INT_FIQ_115_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 51) ++#define INT_FIQ_116_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 52) ++#define INT_FIQ_117_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 53) ++#define INT_FIQ_118_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 54) ++#define INT_FIQ_119_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 55) ++#define INT_FIQ_120_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 56) ++#define INT_FIQ_121_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 57) ++#define INT_FIQ_122_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 58) ++#define INT_FIQ_123_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 59) ++#define INT_FIQ_124_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 60) ++#define INT_FIQ_125_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 61) ++#define INT_FIQ_126_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 62) ++#define INT_FIQ_127_NOT_ALLOW (GIC_SPI_MS_FIQ1_START + 63) ++#define GIC_SPI_MS_FIQ1_END (GIC_SPI_MS_FIQ1_START + 64) ++#define GIC_SPI_MS_FIQ1_NR (GIC_SPI_MS_FIQ1_END - GIC_SPI_MS_FIQ1_START) ++ ++ ++#if 1 ++/* [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=256+X */ ++ ++/* INT_PMSLEEP_DVI_CK_DET *///rm dvi_clk_det, because can not find gpio index ++/* MS_PM_SLEEP_FIQ 0-31 */ ++//#define PMSLEEP_FIQ_START 0 ++//#define INT_PMSLEEP_IR (PMSLEEP_FIQ_START + 0) ++//#define INT_PMSLEEP_DVI_CK_DET (PMSLEEP_FIQ_START + 1) ++//#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 2) ++//#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 3) ++//#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 4) ++//#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 5) ++//#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 6) ++//#define INT_PMSLEEP_GPIO_5 (PMSLEEP_FIQ_START + 7) ++//#define INT_PMSLEEP_GPIO_6 (PMSLEEP_FIQ_START + 8) ++//#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 9) ++//#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 10) ++//#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 11) ++//#define INT_PMSLEEP_GPIO_10 (PMSLEEP_FIQ_START + 12) ++//#define INT_PMSLEEP_GPIO_11 (PMSLEEP_FIQ_START + 13) ++//#define INT_PMSLEEP_GPIO_12 (PMSLEEP_FIQ_START + 14) ++//#define INT_PMSLEEP_GPIO_13 (PMSLEEP_FIQ_START + 15) ++//#define INT_PMSLEEP_GPIO_14 (PMSLEEP_FIQ_START + 16) ++//#define INT_PMSLEEP_GPIO_15 (PMSLEEP_FIQ_START + 17) ++//#define INT_PMSLEEP_18_RESERVED (PMSLEEP_FIQ_START + 18) ++//#define INT_PMSLEEP_19_RESERVED (PMSLEEP_FIQ_START + 19) ++//#define INT_PMSLEEP_20_RESERVED (PMSLEEP_FIQ_START + 20) ++//#define INT_PMSLEEP_21_RESERVED (PMSLEEP_FIQ_START + 21) ++//#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 22) ++//#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 23) ++//#define INT_PMSLEEP_CEC (PMSLEEP_FIQ_START + 24) ++//#define INT_PMSLEEP_25_DUMMY (PMSLEEP_FIQ_START + 25) ++//#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 26) ++//#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 27) ++//#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 28) ++//#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 29) ++//#define INT_PMSLEEP_30_RESERVED (PMSLEEP_FIQ_START + 30) ++//#define INT_PMSLEEP_31_RESERVED (PMSLEEP_FIQ_START + 31) ++//#define INT_PMSLEEP_32_RESERVED (PMSLEEP_FIQ_START + 32) ++//#define INT_PMSLEEP_33_RESERVED (PMSLEEP_FIQ_START + 33) ++//#define INT_PMSLEEP_34_RESERVED (PMSLEEP_FIQ_START + 34) ++//#define INT_PMSLEEP_35_RESERVED (PMSLEEP_FIQ_START + 35) ++//#define INT_PMSLEEP_36_RESERVED (PMSLEEP_FIQ_START + 36) ++//#define INT_PMSLEEP_37_RESERVED (PMSLEEP_FIQ_START + 37) ++//#define INT_PMSLEEP_38_RESERVED (PMSLEEP_FIQ_START + 38) ++//#define INT_PMSLEEP_39_RESERVED (PMSLEEP_FIQ_START + 39) ++//#define INT_PMSLEEP_40_RESERVED (PMSLEEP_FIQ_START + 40) ++//#define INT_PMSLEEP_41_RESERVED (PMSLEEP_FIQ_START + 41) ++//#define INT_PMSLEEP_42_RESERVED (PMSLEEP_FIQ_START + 42) ++//#define INT_PMSLEEP_43_RESERVED (PMSLEEP_FIQ_START + 43) ++//#define INT_PMSLEEP_44_RESERVED (PMSLEEP_FIQ_START + 44) ++//#define INT_PMSLEEP_45_RESERVED (PMSLEEP_FIQ_START + 45) ++//#define INT_PMSLEEP_46_RESERVED (PMSLEEP_FIQ_START + 46) ++//#define INT_PMSLEEP_47_RESERVED (PMSLEEP_FIQ_START + 47) ++//#define INT_PMSLEEP_48_RESERVED (PMSLEEP_FIQ_START + 48) ++//#define INT_PMSLEEP_49_RESERVED (PMSLEEP_FIQ_START + 49) ++//#define INT_PMSLEEP_50_RESERVED (PMSLEEP_FIQ_START + 50) ++//#define INT_PMSLEEP_51_RESERVED (PMSLEEP_FIQ_START + 51) ++//#define INT_PMSLEEP_52_RESERVED (PMSLEEP_FIQ_START + 52) ++//#define INT_PMSLEEP_53_RESERVED (PMSLEEP_FIQ_START + 53) ++//#define INT_PMSLEEP_54_RESERVED (PMSLEEP_FIQ_START + 54) ++//#define INT_PMSLEEP_55_RESERVED (PMSLEEP_FIQ_START + 55) ++//#define INT_PMSLEEP_56_RESERVED (PMSLEEP_FIQ_START + 56) ++//#define INT_PMSLEEP_57_RESERVED (PMSLEEP_FIQ_START + 57) ++//#define INT_PMSLEEP_58_RESERVED (PMSLEEP_FIQ_START + 58) ++//#define INT_PMSLEEP_59_RESERVED (PMSLEEP_FIQ_START + 59) ++//#define INT_PMSLEEP_60_RESERVED (PMSLEEP_FIQ_START + 60) ++//#define INT_PMSLEEP_61_RESERVED (PMSLEEP_FIQ_START + 61) ++//#define INT_PMSLEEP_62_RESERVED (PMSLEEP_FIQ_START + 62) ++//#define INT_PMSLEEP_63_RESERVED (PMSLEEP_FIQ_START + 63) ++//#define INT_PMSLEEP_64_RESERVED (PMSLEEP_FIQ_START + 64) ++//#define INT_PMSLEEP_65_RESERVED (PMSLEEP_FIQ_START + 65) ++//#define INT_PMSLEEP_66_RESERVED (PMSLEEP_FIQ_START + 66) ++//#define INT_PMSLEEP_67_RESERVED (PMSLEEP_FIQ_START + 67) ++//#define INT_PMSLEEP_68_RESERVED (PMSLEEP_FIQ_START + 68) ++//#define INT_PMSLEEP_69_RESERVED (PMSLEEP_FIQ_START + 69) ++//#define INT_PMSLEEP_70_RESERVED (PMSLEEP_FIQ_START + 70) ++//#define INT_PMSLEEP_71_RESERVED (PMSLEEP_FIQ_START + 71) ++//#define INT_PMSLEEP_72_RESERVED (PMSLEEP_FIQ_START + 72) ++//#define INT_PMSLEEP_73_RESERVED (PMSLEEP_FIQ_START + 73) ++//#define INT_PMSLEEP_74_RESERVED (PMSLEEP_FIQ_START + 74) ++//#define INT_PMSLEEP_75_RESERVED (PMSLEEP_FIQ_START + 75) ++//#define INT_PMSLEEP_76_RESERVED (PMSLEEP_FIQ_START + 76) ++//#define INT_PMSLEEP_77_RESERVED (PMSLEEP_FIQ_START + 77) ++//#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 30) ++//#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++/*pm_gpio bank 0xf*/ ++#define PM_GPIO_INT_START (0) ++#define INT_PMSLEEP_GPIO_0 (PM_GPIO_INT_START + 0) //pm_sleep_gpio0 ++#define INT_PMSLEEP_GPIO_1 (PM_GPIO_INT_START + 1) ++#define INT_PMSLEEP_GPIO_2 (PM_GPIO_INT_START + 2) ++#define INT_PMSLEEP_GPIO_3 (PM_GPIO_INT_START + 3) ++#define INT_PMSLEEP_GPIO_4 (PM_GPIO_INT_START + 4) ++#define INT_PMSLEEP_GPIO_5 (PM_GPIO_INT_START + 5) ++#define INT_PMSLEEP_GPIO_6 (PM_GPIO_INT_START + 6) ++#define INT_PMSLEEP_GPIO_7 (PM_GPIO_INT_START + 7) ++#define INT_PMSLEEP_GPIO_8 (PM_GPIO_INT_START + 8) ++#define INT_PMSLEEP_GPIO_9 (PM_GPIO_INT_START + 9) ++#define INT_PMSLEEP_GPIO_10 (PM_GPIO_INT_START + 10) ++#define INT_PMSLEEP_GPIO_11 (PM_GPIO_INT_START + 11) ++#define INT_PMSLEEP_GPIO_12 (PM_GPIO_INT_START + 12) ++#define INT_PMSLEEP_GPIO_13 (PM_GPIO_INT_START + 13) ++#define INT_PMSLEEP_GPIO_14 (PM_GPIO_INT_START + 14) ++#define INT_PMSLEEP_GPIO_15 (PM_GPIO_INT_START + 15) //pm_sleep_gpio15 ++#define INT_PMSLEEP_GPIO_16 (PM_GPIO_INT_START + 16) ++#define INT_PMSLEEP_GPIO_17 (PM_GPIO_INT_START + 17) ++#define INT_PMSLEEP_GPIO_18 (PM_GPIO_INT_START + 18) ++#define INT_PMSLEEP_GPIO_19 (PM_GPIO_INT_START + 19) //pm_sleep_gpio19 ++#define INT_PMSLEEP_GPIO_20_IR (PM_GPIO_INT_START + 20) ++//#define INT_PMSLEEP_GPIO_21_UART_RX (PM_GPIO_INT_START + 21) //?? check ?? ++#define INT_PMSLEEP_GPIO_22_CEC (PM_GPIO_INT_START + 22) ++//#define GPIO_23_un_connect (PM_GPIO_INT_START + 23) ++#define INT_PMSLEEP_GPIO_24_SPI_CZ (PM_GPIO_INT_START + 24) ++#define INT_PMSLEEP_GPIO_25_SPI_CK (PM_GPIO_INT_START + 25) ++#define INT_PMSLEEP_GPIO_26_SPI_DI (PM_GPIO_INT_START + 26) ++#define INT_PMSLEEP_GPIO_27_SPI_DO (PM_GPIO_INT_START + 27) ++//#define GPIO_28 (PM_GPIO_INT_START + 28) ++//#define GPIO_29 (PM_GPIO_INT_START + 29) ++//#define GPIO_30 (PM_GPIO_INT_START + 30) ++//#define GPIO_31 (PM_GPIO_INT_START + 31) ++//#define GPIO_32 (PM_GPIO_INT_START + 32) ++//#define GPIO_33 (PM_GPIO_INT_START + 33) ++//#define GPIO_34 (PM_GPIO_INT_START + 34) ++//#define GPIO_35 (PM_GPIO_INT_START + 35) ++//#define GPIO_36 (PM_GPIO_INT_START + 36) ++//#define GPIO_37 (PM_GPIO_INT_START + 37) ++//#define GPIO_38 (PM_GPIO_INT_START + 38) ++//#define GPIO_39_PAD_GT0_MDC (PM_GPIO_INT_START + 39) ++//#define GPIO_40_PAD_GT0_MDIO (PM_GPIO_INT_START + 40) ++//#define GPIO_41_PAD_GT0_RX_CLK (PM_GPIO_INT_START + 41) ++//#define GPIO_42_PAD_GT0_RX_CTL (PM_GPIO_INT_START + 42) ++//#define GPIO_43_PAD_GT0_RX_D0 (PM_GPIO_INT_START + 43) ++//#define GPIO_44_PAD_GT0_RX_D1 (PM_GPIO_INT_START + 44) ++//#define GPIO_45_PAD_GT0_RX_D2 (PM_GPIO_INT_START + 45) ++//#define GPIO_46_PAD_GT0_RX_D3 (PM_GPIO_INT_START + 46) ++//#define GPIO_47_PAD_GT0_TX_CLK (PM_GPIO_INT_START + 47) ++//#define GPIO_48_PAD_GT0_TX_CTL (PM_GPIO_INT_START + 48) ++//#define GPIO_49_PAD_GT0_TX_D0 (PM_GPIO_INT_START + 49) ++//#define GPIO_50_PAD_GT0_TX_D1 (PM_GPIO_INT_START + 50) ++//#define GPIO_51_PAD_GT0_TX_D2 (PM_GPIO_INT_START + 51) ++//#define GPIO_52_PAD_GT0_TX_D3 (PM_GPIO_INT_START + 52) ++//#define GPIO_53_PAD_GT1_MDC (PM_GPIO_INT_START + 53) ++//#define GPIO_54_PAD_GT1_MDIO (PM_GPIO_INT_START + 54) ++//#define GPIO_55_PAD_GT1_RX_CLK (PM_GPIO_INT_START + 55) ++//#define GPIO_56_PAD_GT1_RX_CTL (PM_GPIO_INT_START + 56) ++//#define GPIO_57_PAD_GT1_RX_D0 (PM_GPIO_INT_START + 57) ++//#define GPIO_58_PAD_GT1_RX_D1 (PM_GPIO_INT_START + 58) ++//#define GPIO_59_PAD_GT1_RX_D2 (PM_GPIO_INT_START + 59) ++//#define GPIO_60_PAD_GT1_RX_D3 (PM_GPIO_INT_START + 60) ++//#define GPIO_61_PAD_GT1_TX_CLK (PM_GPIO_INT_START + 61) ++//#define GPIO_62_PAD_GT1_TX_CTL (PM_GPIO_INT_START + 62) ++//#define GPIO_63_PAD_GT1_TX_D0 (PM_GPIO_INT_START + 63) ++//#define GPIO_64_PAD_GT1_TX_D1 (PM_GPIO_INT_START + 64) ++//#define GPIO_65_PAD_GT1_TX_D2 (PM_GPIO_INT_START + 65) ++//#define GPIO_66_PAD_GT1_TX_D3 (PM_GPIO_INT_START + 66) ++#define INT_PMSLEEP_GPIO_67_PAD_PM_HDMI_CEC (PM_GPIO_INT_START + 67) ++#define INT_PMSLEEP_GPIO_68_PAD_PM_SPI_WPZ (PM_GPIO_INT_START + 68) ++#define INT_PMSLEEP_GPIO_69_PAD_PM_SPI_HOLDZ (PM_GPIO_INT_START + 69) ++#define INT_PMSLEEP_GPIO_70_PAD_PM_SPI_RSTZ (PM_GPIO_INT_START + 70) ++#define INT_PMSLEEP_GPIO_71_PAD_PM_SD_CDZ (PM_GPIO_INT_START + 71) ++#define INT_PMSLEEP_GPIO_72_PAD_VID0 (PM_GPIO_INT_START + 72) //279 ++#define INT_PMSLEEP_GPIO_73_PAD_VID1 (PM_GPIO_INT_START + 73) //280 ++#define INT_PMSLEEP_GPIO_74_PAD_LED0 (PM_GPIO_INT_START + 74) //281 ++#define INT_PMSLEEP_GPIO_75_PAD_LED1 (PM_GPIO_INT_START + 75) //282 ++#define INT_PMSLEEP_GPIO_76_PAD_PM_SPI_CZ1 (PM_GPIO_INT_START + 76) ++#define INT_PMSLEEP_GPIO_77_PAD_PM_SPI_CZ2 (PM_GPIO_INT_START + 77) ++#define INT_PMSLEEP_GPIO_78_PAD_PM_SD30_CDZ (PM_GPIO_INT_START + 78) //277 ++#define INT_PMSLEEP_GPIO_79_PAD_PM_SD20_CDZ (PM_GPIO_INT_START + 79) //278 ++#define PM_GPIO_INT_END (PM_GPIO_INT_START + 80) ++#define PM_GPIO_INT_NR (PM_GPIO_INT_END - PM_GPIO_INT_START) ++ ++ ++#define PMSLEEP_IRQ_START (PM_GPIO_INT_END) ++#define INT_PMSLEEP_IRQ_00_CEC (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_01_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_02_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_03_SYNC_DET (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_04_RTC0 (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_05_DDC (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_06_RTC2 (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_07_RTC1 (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) // PMSLEEP_IRQ_END = 38 ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) ++ ++ ++ ++#endif ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity2/mcm_id.h b/drivers/sstar/include/infinity2/mcm_id.h +new file mode 100755 +index 000000000000..1ddad4a7f0be +--- /dev/null ++++ b/drivers/sstar/include/infinity2/mcm_id.h +@@ -0,0 +1,32 @@ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_MCU51 0 ++#define MCM_ID_URDMA 1 ++#define MCM_ID_BDMA 2 ++#define MCM_ID_VHE 3 ++#define MCM_ID_MFE 4 ++#define MCM_ID_JPE 5 ++#define MCM_ID_BACH 6 ++#define MCM_ID_AESDMA 7 ++#define MCM_ID_UHC 8 ++#define MCM_ID_EMAC 9 ++#define MCM_ID_CMDQ 10 ++#define MCM_ID_ISP_DNR 11 ++#define MCM_ID_ISP_DMA 12 ++#define MCM_ID_GOP 13 ++#define MCM_ID_SC_DNR 14 ++#define MCM_ID_SC_DNR_SAD 15 ++#define MCM_ID_SC_CROP 16 ++#define MCM_ID_SC1_FRM 17 ++#define MCM_ID_SC1_SNP 18 ++#define MCM_ID_SC1_DBG 19 ++#define MCM_ID_SC2_FRM 20 ++#define MCM_ID_SC3_FRM 21 ++#define MCM_ID_FCIE 22 ++#define MCM_ID_SDIO 23 ++#define MCM_ID_SC1_SNPI 24 ++#define MCM_ID_SC2_SNPI 25 ++#define MCM_ID_ALL 99 ++ ++#endif +diff --git a/drivers/sstar/include/infinity2/mdrv_miu.h b/drivers/sstar/include/infinity2/mdrv_miu.h +new file mode 100755 +index 000000000000..6dbd98f91efa +--- /dev/null ++++ b/drivers/sstar/include/infinity2/mdrv_miu.h +@@ -0,0 +1,282 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mdrv_mtlb.h ++/// @brief MTLB Driver Interface ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux Mhal_mtlb.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_MTLB_H__ ++#define __DRV_MTLB_H__ ++ ++ ++#ifdef CONFIG_64BIT ++ typedef unsigned long phy_addr; // 8 bytes ++#else ++ typedef unsigned long long phy_addr; // 8 bytes ++#endif ++typedef enum ++{ ++ // group 0 ++ MIU_CLIENT_NONE, //none can access ++ MIU_CLIENT_CEVAXM6_0_RW, ++ MIU_CLIENT_CEVAXM6_1_RW, ++ MIU_CLIENT_VD_R2I_R, ++ MIU_CLIENT_VD_R2_SUBSYS_R, ++ MIU_CLIENT_VD_R2D_RW, ++ MIU_CLIENT_CEVAXM6_2_RW, ++ MIU_CLIENT_CEVAXM6_3_RW, ++ MIU_CLIENT_AUDIO_R, ++ MIU_CLIENT_AUDIO_AU2_R, ++ MIU_CLIENT_AUDIO_AU3_W, ++ MIU_CLIENT_CMDQ_R, ++ MIU_CLIENT_XD2MIU_RW, ++ MIU_CLIENT_UART_DMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_DUMMY_G0CF, ++ // group 1 ++ MIU_CLIENT_SC1_CROP_LDC, ++ MIU_CLIENT_ISP_GOP1_R, ++ MIU_CLIENT_CMDQ_TOP_1_R, ++ MIU_CLIENT_NOE_RW, ++ MIU_CLIENT_USB30_RW, ++ MIU_CLIENT_ISP_STA_W, ++ MIU_CLIENT_ISP_AF_STA1_W, ++ MIU_CLIENT_ISP_GOP2_R, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_IVE_TOP_RW, ++ MIU_CLIENT_ISP_GOP3_R, ++ MIU_CLIENT_MIIC0_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_MIIC2_RW, ++ MIU_CLIENT_ISP_SC1_DBG_R, ++ MIU_CLIENT_ISP_CMDQ_TOP2_R, ++ // group 2 ++ MIU_CLIENT_SDIO_RW, ++ MIU_CLIENT_USB30_1_RW, ++ MIU_CLIENT_USB30_2_RW, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_JPE_W, ++ MIU_CLIENT_JPE_R, ++ MIU_CLIENT_U3DEV_RW, ++ MIU_CLIENT_JPD_RW, ++ MIU_CLIENT_GMAC_RW, ++ MIU_CLIENT_FCIE5_RW,/*PNAND/EMMC*/ ++ MIU_CLIENT_SECGMAC, ++ MIU_CLIENT_USB30M1_HS_RW, ++ MIU_CLIENT_SATA0_RW, ++ MIU_CLIENT_SATA1_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_USB20_P1_RW, ++ // group 3 ++ MIU_CLIENT_ISP_GOP4_R, ++ MIU_CLIENT_ISOSC_BLKS_RW, ++ MIU_CLIENT_CMDQ_TOP5_R, ++ MIU_CLIENT_ISP_GOP0_R, ++ MIU_CLIENT_SC1_FRAME_W, ++ MIU_CLIENT_SC1_SNAPSHOT_W, ++ MIU_CLIENT_SC2_FRAME_W, ++ MIU_CLIENT_CMDQ_TOP4_R, ++ MIU_CLIENT_MFE0_R, ++ MIU_CLIENT_MFE0_W, ++ MIU_CLIENT_SC3_FRAME_RW, ++ MIU_CLIENT_DUMMY_G3CB, ++ MIU_CLIENT_DUMMY_G3CC, ++ MIU_CLIENT_MFE1_R, ++ MIU_CLIENT_MFE1_W, ++ MIU_CLIENT_ISP_MLOAD_R, ++ // group 4 ++ MIU_CLIENT_VE_W, ++ MIU_CLIENT_EVD_ENG1_RW, ++ MIU_CLIENT_MGWIN0_R, ++ MIU_CLIENT_MGWIN1_R, ++ MIU_CLIENT_HVD_RW, ++ MIU_CLIENT_HVD1_RW, ++ MIU_CLIENT_DDI_0_RW, ++ MIU_CLIENT_EVD_ENG0_RW, ++ MIU_CLIENT_MFDEC0_1_R, ++ MIU_CLIENT_ISPSC_DMAG, ++ MIU_CLIENT_EVD_BBU_R, ++ MIU_CLIENT_HVD_BBU_R, ++ MIU_CLIENT_SC1_IPMAIN_RW, ++ MIU_CLIENT_SC1_OPM_R, ++ MIU_CLIENT_MFDEC_1_1_R, ++ MIU_CLIENT_LDC_R, ++ // group 5 ++ MIU_CLIENT_GOP0_R, ++ MIU_CLIENT_GOP1_R, ++ MIU_CLIENT_AUTO_DOWNLOAD_R, ++ MIU_CLIENT_SC_DIPW_RW, ++ MIU_CLIENT_MVOP_128BIT_R, ++ MIU_CLIENT_MVOP1_R, ++ MIU_CLIENT_FRC_IPM0_W, ++ MIU_CLIENT_SC_IPSUB_RW, ++ MIU_CLIENT_FRC_OPM0_R, ++ MIU_CLIENT_MDWIN0_W, ++ MIU_CLIENT_MFDEC0_R, ++ MIU_CLIENT_MFDEC1_R, ++ MIU_CLIENT_MDWIN1_W, ++ MIU_CLIENT_SC_DYN_SCL_R, ++ MIU_CLIENT_VE_R, ++ MIU_CLIENT_GE_RW, ++ // group 6 ++ MIU_CLIENT_ISP_DMAG0_W, ++ MIU_CLIENT_ISP_DMAG0_R, ++ MIU_CLIENT_ISP_DMAG1_W, ++ MIU_CLIENT_ISP_DMAG1_R, ++ MIU_CLIENT_ISP_DMAG2_RW, ++ MIU_CLIENT_ISP_DMAG3_RW, ++ MIU_CLIENT_ISP_DMAG4_W, ++ MIU_CLIENT_ISP_DMAG4_R, ++ MIU_CLIENT_ISP_DMAG_RW, ++ MIU_CLIENT_DMA_GENERAL_RW, ++ MIU_CLIENT_SC1_DNR_RW, ++ MIU_CLIENT_DUMMY_G6CB, ++ MIU_CLIENT_MHE0_R, ++ MIU_CLIENT_MHE0_W, ++ MIU_CLIENT_MHE1_R, ++ MIU_CLIENT_MHE1_W, ++ // group 7 ++ MIU_CLIENT_MIPS_RW, //ARM CPU ++ MIU_CLIENT_G3D_RW, ++ MIU_CLIENT_DUMMY_G7_C2, ++ MIU_CLIENT_DUMMY_G7_C3, ++ MIU_CLIENT_DUMMY_G7_C4, ++ MIU_CLIENT_DUMMY_G7_C5, ++ MIU_CLIENT_DUMMY_G7_C6, ++ MIU_CLIENT_DUMMY_G7_C7, ++ MIU_CLIENT_DUMMY_G7_C8, ++ MIU_CLIENT_DUMMY_G7_C9, ++ MIU_CLIENT_DUMMY_G7_CA, ++ MIU_CLIENT_DUMMY_G7_CB, ++ MIU_CLIENT_DUMMY_G7_CC, ++ MIU_CLIENT_DUMMY_G7_CD, ++ MIU_CLIENT_DUMMY_G7_CE, ++ MIU_CLIENT_DUMMY_G7_CF, ++ // no use ++ MIU_CLIENT_VIVALDI9_DECODER_R, ++ MIU_CLIENT_SECAU_R2_RW, ++ MIU_CLIENT_TSP_FIQ_RW, ++ MIU_CLIENT_USB3_RW, ++ MIU_CLIENT_CMD_QUEUE_RW, ++ MIU_CLIENT_ZDEC_RW, ++ MIU_CLIENT_ZDEC_ACP_RW, ++ MIU_CLIENT_EVD_RW, ++ MIU_CLIENT_EVD_R2D_RW, ++ MIU_CLIENT_EVD_R2I_R, ++ MIU_CLIENT_3RDHVD_RW, ++ MIU_CLIENT_EVD_R, ++ MIU_CLIENT_MFDEC_R, ++ MIU_CLIENT_MVD_RTO_RW, ++ MIU_CLIENT_SC1_OP_R, ++ MIU_CLIENT_SECMFDEC_R, ++ MIU_CLIENT_SECURE_R2_RW, ++ MIU_CLIENT_AU_R2_RW, ++ MIU_CLIENT_DUMMY, ++ MIU_CLIENT_MVD_RW, ++ MIU_CLIENT_VIVALDI9_MAD_RW, ++ MIU_CLIENT_SECEMAC_RW, ++ MIU_CLIENT_USB_UHC1_RW, ++ MIU_CLIENT_USB_UHC2_RW, ++ MIU_CLIENT_TSP_R, ++ MIU_CLIENT_TSP_PVR1_W, ++ MIU_CLIENT_GPD_RW, ++ MIU_CLIENT_USB_UHC0_RW, ++ MIU_CLIENT_GOP2_R, ++ MIU_CLIENT_GOP3_R, ++ //Add new after here ++}eMIUClientID; ++ ++typedef enum ++{ ++ E_MIU_0 = 0, ++ E_MIU_1, ++ E_MIU_2, ++ E_MIU_3, ++ E_MIU_NUM, ++} MIU_ID; ++ ++typedef enum ++{ ++ E_PROTECT_0 = 0, ++ E_PROTECT_1, ++ E_PROTECT_2, ++ E_PROTECT_3, ++ E_SLIT_0 = 16, ++ E_MIU_PROTECT_NUM, ++} PROTECT_ID; ++//#define CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ ++typedef enum ++{ ++ P_DISABLE = 0, ++ W_EN, ++ R_EN, ++ WR_EN, ++ W_EN_INVERT, ++ R_EN_INVERT, ++ WR_EN_INVERT, ++} PROTECT_CTRL; ++ ++//#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++typedef struct ++{ ++ unsigned char bHit; ++ unsigned char u8Group; ++ unsigned char u8ClientID; ++ unsigned char u8Block; ++ unsigned int u16ProtectType; ++ unsigned int uAddress; ++}MIU_PortectInfo; ++//#endif ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++unsigned char MDrv_MIU_Init(void); ++unsigned short* MDrv_MIU_GetDefaultClientID_KernelProtect(void); ++unsigned char MDrv_MIU_Protect(unsigned char u8Blockx, unsigned short *pu8ProtectId, phy_addr u64Start, phy_addr u64End, PROTECT_CTRL eSetFlag); ++unsigned char MDrv_MIU_Save(void); ++unsigned char MDrv_MIU_Restore(void); ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++unsigned char MDrv_MIU_GetProtectInfo(unsigned char u8MiuDev, MIU_PortectInfo *pInfo); ++#endif ++unsigned char MDrv_MIU_Slits(unsigned char u8Blockx, phy_addr u64SlitsStart, phy_addr u65SlitsEnd, unsigned char bSetFlag); ++unsigned char MDrv_MIU_Get_IDEnables_Value(unsigned char u8MiuDev, unsigned char u8Blockx, unsigned char u8ClientIndex); ++unsigned int MDrv_MIU_ProtectDramSize(void); ++ ++unsigned char MDrv_MIU_SetSsc(unsigned short u16Fmodulation, unsigned short u16FDeviation, unsigned char bEnable); ++unsigned char MDrv_MIU_SetSscValue(unsigned char u8MiuDev, unsigned short u16Fmodulation, unsigned short u16FDeviation, unsigned char bEnable); ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo); ++ ++#endif +diff --git a/drivers/sstar/include/infinity2/mhal_miu.h b/drivers/sstar/include/infinity2/mhal_miu.h +new file mode 100755 +index 000000000000..9e2f770c2c78 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/mhal_miu.h +@@ -0,0 +1,162 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_mtlb.h ++/// @author MStar Semiconductor Inc. ++/// @brief MTLB Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux Mhal_miu.h define start ++// ----------------------------------------------------------------------------- ++#ifndef _HAL_MIU_H_ ++#define _HAL_MIU_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define _FUNC_NOT_USED() do {} while ( 0 ) ++ ++#define MIU_MAX_DEVICE (2) ++//Max MIU Group number ++#define MIU_MAX_GROUP (8) ++#define MIU_MAX_GP_CLIENT (16) ++#define MIU_MAX_TBL_CLIENT (MIU_MAX_GROUP*MIU_MAX_GP_CLIENT) ++#define MIU_PAGE_SHIFT (13) //Unit for MIU protect ++#define MIU_PROTECT_ADDRESS_UNIT (0x20UL) //Unit for MIU hitted address ++#define MIU_MAX_PROTECT_BLOCK (4) ++#define MIU_MAX_PROTECT_ID (16) ++#define MIU_BLOCK0_CLIENT_NUMBER (16) ++#define MIU_BLOCK1_CLIENT_NUMBER (16) ++#define MIU_BLOCK2_CLIENT_NUMBER (16) ++#define MIU_BLOCK3_CLIENT_NUMBER (16) ++#define MIU_BLOCK4_CLIENT_NUMBER (16) ++#define MIU_BLOCK5_CLIENT_NUMBER (16) ++ ++#ifndef BIT0 ++#define BIT0 0x0001UL ++#define BIT1 0x0002UL ++#define BIT2 0x0004UL ++#define BIT3 0x0008UL ++#define BIT4 0x0010UL ++#define BIT5 0x0020UL ++#define BIT6 0x0040UL ++#define BIT7 0x0080UL ++#define BIT8 0x0100UL ++#define BIT9 0x0200UL ++#define BIT10 0x0400UL ++#define BIT11 0x0800UL ++#define BIT12 0x1000UL ++#define BIT13 0x2000UL ++#define BIT14 0x4000UL ++#define BIT15 0x8000UL ++#endif ++ ++#define MIU_OPM_R_MASK 0x0667UL ++#define MIU_OPM_W_MASK 0x0666UL ++#define MIU_MVD_R_MASK 0x06F6UL ++#define MIU_MVD_W_MASK 0x06F7UL ++ ++//$ MIU0 Request Mask functions ++#define _MaskMiuReq_OPM_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1) ++ ++#define _MaskMiuReq_DNRB_W( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2) ++#define _MaskMiuReq_DNRB_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT3) ++#define _MaskMiuReq_DNRB_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2|BIT3) ++ ++#define _MaskMiuReq_SC_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1|BIT2|BIT3) ++ ++#define _MaskMiuReq_MVOP_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1L_MASK, m, BIT3) ++ ++#define _MaskMiuReq_MVD_R( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT5); } while(0) ++#define _MaskMiuReq_MVD_W( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT5); } while(0) ++#define _MaskMiuReq_MVD_RW( m ) do { _MaskMiuReq_MVD_R( m ); _MaskMiuReq_MVD_W( m ); } while (0) ++ ++#define _MaskMiuReq_AUDIO_RW( m ) _FUNC_NOT_USED() ++ ++ ++//$ MIU1 Request Mask functions ++#define _MaskMiu1Req_OPM_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1) ++ ++#define _MaskMiu1Req_DNRB_W( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2) ++#define _MaskMiu1Req_DNRB_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT3) ++#define _MaskMiu1Req_DNRB_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2|BIT3) ++ ++#define _MaskMiu1Req_SC_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1|BIT2|BIT3) ++ ++#define _MaskMiu1Req_MVOP_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1L_MASK, m, BIT3) ++ ++#define _MaskMiu1Req_MVD_R( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT5); } while(0) ++#define _MaskMiu1Req_MVD_W( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT5); } while(0) ++#define _MaskMiu1Req_MVD_RW( m ) do { _MaskMiuReq_MVD_R( m ); _MaskMiuReq_MVD_W( m ); } while (0) ++ ++#define _MaskMiu1Req_AUDIO_RW( m ) _FUNC_NOT_USED() ++ ++#define MIU_GET_CLIENT_POS(x) (x & 0x0FUL) ++#define MIU_GET_CLIENT_GROUP(x) ((x & 0xF0UL) >> 4) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MIU_BLOCK_0 = 0, ++ E_MIU_BLOCK_1, ++ E_MIU_BLOCK_2, ++ E_MIU_BLOCK_3, ++ E_MIU_BLOCK_NUM, ++} MIU_BLOCK_ID; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo_Hal; ++ ++#ifdef CONFIG_MSC006A_S01A_S_UVC ++#define IDNUM_KERNELPROTECT (16) ++#else ++#define IDNUM_KERNELPROTECT (16) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++MS_U16* HAL_MIU_GetDefaultClientID_KernelProtect(void); ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, PROTECT_CTRL eSetFlag); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void); ++ ++//#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++MS_BOOL HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev, MIU_PortectInfo *pInfo); ++//#endif ++MS_BOOL HAL_Protect_Save(void); ++MS_BOOL HAL_Protect_Restore(void); ++MS_BOOL HAL_MIU_Get_IDEnables_Value(MS_U8 u8MiuDev, MS_U8 u8MiuBlockId, MS_U8 u8ProtectIdIndex); ++unsigned int HAL_MIU_ProtectDramSize(void); ++MS_BOOL HAL_MIU_SetSsc(MS_U8 u8MiuDev, MS_U16 u16Fmodulation, MS_U16 u16FDeviation, MS_BOOL bEnable); ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo); ++ ++#endif // _HAL_MIU_H_ ++ +diff --git a/drivers/sstar/include/infinity2/padmux.h b/drivers/sstar/include/infinity2/padmux.h +new file mode 100755 +index 000000000000..3da53cc7a548 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/padmux.h +@@ -0,0 +1,134 @@ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++//#define PINMUX_FOR_GPIO_MODE 0x00 ++ ++typedef enum ++{ ++ PINMUX_FOR_GPIO_MODE = 0, ++ PINMUX_FOR_GT0_MODE, ++ PINMUX_FOR_GT1_MODE, ++ PINMUX_FOR_SEC_MSPI2_MODE, ++ PINMUX_FOR_SPDIF_OUT_MODE, ++ PINMUX_FOR_SPDIF_IN_MODE, ++ PINMUX_FOR_I2S_IN_MODE, ++ PINMUX_FOR_I2S_TRX_MODE, ++ PINMUX_FOR_I2S_OUT_MODE, ++ PINMUX_FOR_I2S_OUT_MODE2, ++ PINMUX_FOR_NAND_MODE, ++ PINMUX_FOR_NAND_CS1_EN, ++ PINMUX_FOR_I2CM0_EN, ++ PINMUX_FOR_I2CM1_MODE, ++ PINMUX_FOR_I2CM2_MODE, ++ PINMUX_FOR_I2CM3_MODE, ++ PINMUX_FOR_I2CM4_MODE, ++ PINMUX_FOR_SECOND_UART_MODE, ++ PINMUX_FOR_THIRD_UART_MODE, ++ PINMUX_FOR_FORTH_UART_MODE, ++ PINMUX_FOR_FAST_UART_RT_MODE, ++ PINMUX_FOR_FUART_MODE, ++ PINMUX_FOR_FUART_EMMC_MODE, ++ PINMUX_FOR_MSPI1_MODE1, ++ PINMUX_FOR_MSPI2_MODE1, ++ PINMUX_FOR_MSPI3_MODE1, ++ PINMUX_FOR_SD_CONFIG, ++ PINMUX_FOR_SDIO_MODE, ++ PINMUX_FOR_SDIO30_MODE, ++ PINMUX_FOR_EMMC_RSTN_EN, ++ PINMUX_FOR_EMMC_CONFIG, ++ PINMUX_FOR_PWM0_MODE, ++ PINMUX_FOR_PWM1_MODE, ++ PINMUX_FOR_PWM2_MODE, ++ PINMUX_FOR_PWM3_MODE, ++ PINMUX_FOR_PWM4_MODE, ++ PINMUX_FOR_PWM5_MODE, ++ PINMUX_FOR_PWM6_MODE, ++ PINMUX_FOR_PWM7_MODE, ++ PINMUX_FOR_USB30VCTL_MODE, ++ PINMUX_FOR_USB30VCTL_MODE1, ++ PINMUX_FOR_HDMITX_DDC_MODE, ++ PINMUX_FOR_HDMITX_ARC_MODE, ++ PINMUX_FOR_HDMIRX_ARC_MODE, ++ PINMUX_FOR_HSYNC_EN, ++ PINMUX_FOR_VSYNC_EN, ++ PINMUX_FOR_SATA_LED_MODE, ++ PINMUX_FOR_SATA1_LED_MODE, ++ PINMUX_FOR_SNR0_MODE, ++ PINMUX_FOR_SNR1_MODE, ++ PINMUX_FOR_SNR2_MODE, ++ PINMUX_FOR_SNR3_MODE, ++ PINMUX_FOR_CCIR0_CTRL_MODE, ++ PINMUX_FOR_CCIR1_CTRL_MODE, ++ PINMUX_FOR_CCIR2_CTRL_MODE, ++ PINMUX_FOR_CCIR3_CTRL_MODE, ++ PINMUX_FOR_CCIR0_CLK_MODE, ++ PINMUX_FOR_CCIR1_CLK_MODE, ++ PINMUX_FOR_CCIR2_CLK_MODE, ++ PINMUX_FOR_CCIR3_CLK_MODE, ++ PINMUX_FOR_CCIR0_8B_MODE, ++ PINMUX_FOR_CCIR1_8B_MODE, ++ PINMUX_FOR_CCIR2_8B_MODE, ++ PINMUX_FOR_CCIR3_8B_MODE, ++ PINMUX_FOR_CCIR0_16B_MODE, ++ PINMUX_FOR_CCIR2_16B_MODE, ++ PINMUX_FOR_MIPI_LVDS_TX_2CH_MODE, ++ PINMUX_FOR_MIPI_LVDS_TX_4CH_MODE, ++ PINMUX_FOR_RGB_16B_MODE, ++ PINMUX_FOR_RGB_24B_MODE, ++ PINMUX_FOR_TTL_OUT, ++ PINMUX_FOR_CODEC_I2S_RX_MCK_MODE, ++ PINMUX_FOR_CODEC_I2S_RX_0_MODE, ++ PINMUX_FOR_CODEC_I2S_RX_1_MODE, ++ PINMUX_FOR_CODEC_I2S_RX_2_MODE, ++ PINMUX_FOR_CODEC_I2S_RX_3_MODE, ++ PINMUX_FOR_CODEC_I2S_TX_0_MODE, ++ PINMUX_FOR_MISC_I2S_TX_MUTE_MODE, ++ PINMUX_FOR_MISC_I2S_RX_0_MODE, ++ PINMUX_FOR_MISC_I2S_TX_0_MODE, ++ PINMUX_FOR_MISC_I2S_TX_1_MODE, ++ PINMUX_FOR_MISC_I2S_TX_2_MODE, ++ PINMUX_FOR_BT_I2S_TRX_0_MODE, ++ PINMUX_FOR_BT_I2S_RX_0_MODE, ++ PINMUX_FOR_BT_I2S_TX_0_MODE, ++ PINMUX_FOR_BT_DMIC_0_MODE, ++ PINMUX_FOR_BT_DMIC_1_MODE, ++ PINMUX_FOR_BT_DMIC_2_MODE, ++ PINMUX_FOR_BT_DMIC_3_MODE, ++ PINMUX_FOR_EJ_MODE, ++ PINMUX_FOR_EJ_CEVA_MODE, ++ PINMUX_FOR_PMSPI_MODE, ++ PINMUX_FOR_VID_MODE, ++ PINMUX_FOR_GPU_VID_MODE, ++ PINMUX_FOR_MIIC_MODE, ++ PINMUX_FOR_HDMI_HPD_BYPASS_MODE, ++ PINMUX_FOR_SD_CDZ_MODE, ++ PINMUX_FOR_PM_PWM0_MODE, ++ PINMUX_FOR_PM_PWM1_MODE, ++ PINMUX_FOR_MISC_I2S_RX_MCK_MODE, ++ PINMUX_FOR_LED_MODE, ++ PINMUX_FOR_UNKNOWN_MODE, ++ PINMUX_FOR_SAR_MODE, ++ PINMUX_FOR_I2C1_MODE, ++ PINMUX_FOR_I2C1_MODE2, ++ PINMUX_FOR_I2C1_MODE3, ++ PINMUX_FOR_I2C1_MODE4, ++ PINMUX_FOR_I2C2_MODE, ++ PINMUX_FOR_I2C2_MODE3, ++ PINMUX_FOR_I2C2_MODE4, ++ PINMUX_FOR_I2C2_MODE5, ++ PINMUX_FOR_I2C2_MODE6, ++ PINMUX_FOR_I2C2_MODE7, ++ PINMUX_FOR_I2C3_MODE4, ++ PINMUX_FOR_EMMC_MODE, ++ PINMUX_FOR_DMIC_MODE, ++ PINMUX_FOR_PM_MSPI_MODE, ++ PINMUX_FOR_SNR1_IN_MODE, ++ PINMUX_FOR_SPI1_MODE, ++}PINMUX_MODE; ++ ++ ++S32 halPadGetVal(U32 padID, U32* mode); ++S32 halPadSetVal(U32 padID, U32 mode); ++S32 halCheckPin(U32 padID); ++ ++#endif +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/1_Infinity2_usb20_p0_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/1_Infinity2_usb20_p0_pd.h +new file mode 100755 +index 000000000000..555c67f9b0a0 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/1_Infinity2_usb20_p0_pd.h +@@ -0,0 +1,28 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// USB2.0 P0 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x05); ++// [2]: PDN_REF ++// [6]: R_DP_PDEN ++// [7]: R_DM_PDEN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0xff); ++// [0]: HS_DM_PDN ++// [2]: HS_TED_PDN ++// [3]: HS_PREAMP_PDN ++// [4]: FL_XCVR_PDN ++// [6]: IREF_PDN ++// [7]: REG_PDN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a90), 0x00); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/2_Infinity2_upll_p0_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/2_Infinity2_upll_p0_pd.h +new file mode 100755 +index 000000000000..0f7d1894988c +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/2_Infinity2_upll_p0_pd.h +@@ -0,0 +1,26 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// UPLL P0 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0x32); ++//[1]: PD_UPLL ++//[4]: PD_CLKO_UPLL_20M ++//[5]: PD_CLKO_UPLL_320M ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100801), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100802), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010080e), 0x04); ++//[0]: EN_CLKO_UPLL_384M ++//[1]: EN_UPLL_PRDT2 ++//[2]: GCR_UPLL_PD_CLKO_AUDIO +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/3_Infinity2_gmacpll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/3_Infinity2_gmacpll_pd.h +new file mode 100755 +index 000000000000..ce519ac83650 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/3_Infinity2_gmacpll_pd.h +@@ -0,0 +1,15 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// GMACPLL power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110c06), 0x80); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/4_Infinity2_cevapll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/4_Infinity2_cevapll_pd.h +new file mode 100755 +index 000000000000..9ee17b8db6fd +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/4_Infinity2_cevapll_pd.h +@@ -0,0 +1,16 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// cevapll power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00162e23), 0x01); ++ +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/5_Infinity2_extaupll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/5_Infinity2_extaupll_pd.h +new file mode 100755 +index 000000000000..353463885ce0 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/5_Infinity2_extaupll_pd.h +@@ -0,0 +1,15 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// EXTAUPLL power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00311176), 0x80); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/6_Infinity2_hdmi2txpll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/6_Infinity2_hdmi2txpll_pd.h +new file mode 100755 +index 000000000000..327e044cfdf3 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P0/6_Infinity2_hdmi2txpll_pd.h +@@ -0,0 +1,15 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// HDMI2TX PLL power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0011292f), 0x01); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/1_Infinity2_usb20_p0_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/1_Infinity2_usb20_p0_pd.h +new file mode 100755 +index 000000000000..a21a92ab8c38 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/1_Infinity2_usb20_p0_pd.h +@@ -0,0 +1,28 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// USB2.0 P1 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x05); ++// [2]: PDN_REF ++// [6]: R_DP_PDEN ++// [7]: R_DM_PDEN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0xff); ++// [0]: HS_DM_PDN ++// [2]: HS_TED_PDN ++// [3]: HS_PREAMP_PDN ++// [4]: FL_XCVR_PDN ++// [6]: IREF_PDN ++// [7]: REG_PDN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a10), 0x00); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/2_Infinity2_upll_p0_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/2_Infinity2_upll_p0_pd.h +new file mode 100755 +index 000000000000..0e6267b43996 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/2_Infinity2_upll_p0_pd.h +@@ -0,0 +1,26 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// UPLL P1 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0x32); ++//[1]: PD_UPLL ++//[4]: PD_CLKO_UPLL_20M ++//[5]: PD_CLKO_UPLL_320M ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100841), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100842), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010084e), 0x04); ++//[0]: EN_CLKO_UPLL_384M ++//[1]: EN_UPLL_PRDT2 ++//[2]: GCR_UPLL_PD_CLKO_AUDIO +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/3_Infinity2_mipspll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/3_Infinity2_mipspll_pd.h +new file mode 100755 +index 000000000000..c19ad73449b8 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/3_Infinity2_mipspll_pd.h +@@ -0,0 +1,16 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// mipspll power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110a23), 0x01); ++ +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/4_Infinity2_isppll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/4_Infinity2_isppll_pd.h +new file mode 100755 +index 000000000000..5cf3cbb49037 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/4_Infinity2_isppll_pd.h +@@ -0,0 +1,16 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// isppll power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001129a3), 0x01); ++ +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/5_Infinity2_hicodecpll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/5_Infinity2_hicodecpll_pd.h +new file mode 100755 +index 000000000000..dde624310b3f +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/5_Infinity2_hicodecpll_pd.h +@@ -0,0 +1,16 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// hicodecpll power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110993), 0x01); ++ +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/6_Infinity2_evdpll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/6_Infinity2_evdpll_pd.h +new file mode 100755 +index 000000000000..91192a540191 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P1/6_Infinity2_evdpll_pd.h +@@ -0,0 +1,16 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// evdpll power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110983), 0x01); ++ +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/1_Infinity2_usb20_p0_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/1_Infinity2_usb20_p0_pd.h +new file mode 100755 +index 000000000000..67cd8a4e0a8a +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/1_Infinity2_usb20_p0_pd.h +@@ -0,0 +1,28 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// USB2.0 P2 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x05); ++// [2]: PDN_REF ++// [6]: R_DP_PDEN ++// [7]: R_DM_PDEN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0xff); ++// [0]: HS_DM_PDN ++// [2]: HS_TED_PDN ++// [3]: HS_PREAMP_PDN ++// [4]: FL_XCVR_PDN ++// [6]: IREF_PDN ++// [7]: REG_PDN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103890), 0x00); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/2_Infinity2_upll_p2_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/2_Infinity2_upll_p2_pd.h +new file mode 100755 +index 000000000000..707cbd1f0fd2 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/2_Infinity2_upll_p2_pd.h +@@ -0,0 +1,26 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// UPLL P2 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0x32); ++//[1]: PD_UPLL ++//[4]: PD_CLKO_UPLL_20M ++//[5]: PD_CLKO_UPLL_320M ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100882), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010088e), 0x04); ++//[0]: EN_CLKO_UPLL_384M ++//[1]: EN_UPLL_PRDT2 ++//[2]: GCR_UPLL_PD_CLKO_AUDIO +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/3_Infinity2_miu128pll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/3_Infinity2_miu128pll_pd.h +new file mode 100755 +index 000000000000..52c8c3da3ab1 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P2/3_Infinity2_miu128pll_pd.h +@@ -0,0 +1,16 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// miu128pll power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110963), 0x01); ++ +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P3/1_Infinity2_usb20_p3_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P3/1_Infinity2_usb20_p3_pd.h +new file mode 100755 +index 000000000000..cdd877651234 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD3P3_USB_P3/1_Infinity2_usb20_p3_pd.h +@@ -0,0 +1,27 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// USB2.0 P3 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x05); ++// [0]: HS_DM_PDN ++// [2]: HS_TED_PDN ++// [3]: HS_PREAMP_PDN ++// [4]: FL_XCVR_PDN ++// [6]: IREF_PDN ++// [7]: REG_PDN ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b10), 0x00); ++//[7]PD_BG_CURRENT ++//[6]HS_TXSER_EN +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/1_Infinity2_mipi_combotx_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/1_Infinity2_mipi_combotx_pd.h +new file mode 100755 +index 000000000000..6efa54e08124 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/1_Infinity2_mipi_combotx_pd.h +@@ -0,0 +1,40 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// MIPI COMBO TX power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150800), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150802), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150808), 0x20); ++//[4]: LPTX0_EN ++//[7:6]: HSTX0_EN[1:0] ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150809), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x15080e), 0x20); ++//[4]: LPTX1_EN ++//[7:6]: HSTX1_EN[1:0] ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x15080f), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150814), 0x20); ++//[4]: LPTX2_EN[0] ++//[7:6]: HSTX2_EN[1:0] ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150815), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150822), 0x20); ++//[4]: LPTX3_EN[0] ++//[7:6]: HSTX3_EN[1:0] ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150823), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150828), 0x20); ++//[4]: LPTX4_EN[0] ++//[7:6]: HSTX4_EN[1:0] ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150829), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150851), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150856), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x150859), 0x7C); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x171006), 0x00); +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/2_Infinity2_mpll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/2_Infinity2_mpll_pd.h +new file mode 100755 +index 000000000000..403f561f3524 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/2_Infinity2_mpll_pd.h +@@ -0,0 +1,27 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// MPLL power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110b03), 0x1f); ++//[0]: PD_MPLL ++//[1]: PD_MPLL_CLK_ADC_VCO_DIV2 ++//[2]: PD_MPLL_CLK_ADC_VCO_DIV2_2 ++//[3]: PD_MPLL_CLK_ADC_VCO_DIV2_3 ++//[4]: PD_DIGCLK ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110b04), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110b08), 0x00); ++//[0]: EN_MPLL_TEST ++//[1]: EN_MPLL_OV_CP_SW ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00110b09), 0x00); ++//[2]: EN_MPLL_XTAL ++//[7]: EN_MPLL_PRDT +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/3_Infinity2_lpll_pd.h b/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/3_Infinity2_lpll_pd.h +new file mode 100755 +index 000000000000..985eded88119 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/AVDD_MIPI_TX/3_Infinity2_lpll_pd.h +@@ -0,0 +1,19 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// LPLL power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103181), 0x80); ++//[1]: LPLL1_EN_SCALAR ++//[2]: LPLL1_EN_FIFO ++//[5]: LPLL1_EN_MINI ++//[7]: LPLL1_PD +diff --git a/drivers/sstar/include/infinity2/powerDown/ETH_TX_100T_RANDOM.h b/drivers/sstar/include/infinity2/powerDown/ETH_TX_100T_RANDOM.h +new file mode 100755 +index 000000000000..c993aacbfa1d +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/ETH_TX_100T_RANDOM.h +@@ -0,0 +1,50 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// Reset ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00000e60), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ea1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033a1), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032cc), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032bb), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338f), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d9), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f7), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fb), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fd), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000333a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338a), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032c4), 0x44); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003380), 0x30); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000323b), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033c5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003330), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003240), 0x30); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003187), 0x14); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312d), 0x0c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x21); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x21); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x21); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003187), 0x14); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032d5), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000325a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000325b), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003253), 0x4f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000315d), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000315d), 0x02); ++// measure RJ45 connector +diff --git a/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_ALL_ONE.h b/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_ALL_ONE.h +new file mode 100755 +index 000000000000..65610b6b8112 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_ALL_ONE.h +@@ -0,0 +1,56 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// Reset ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00000e60), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ea1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033a1), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032cc), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032bb), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338f), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d9), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f7), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fb), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fd), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000333a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338a), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032c4), 0x44); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003380), 0x30); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000323b), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033c5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003330), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003187), 0x14); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312d), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003180), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317e), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317f), 0x1e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317a), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317b), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317c), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317d), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003173), 0x0c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003140), 0xd2); +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_LTP.h b/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_LTP.h +new file mode 100755 +index 000000000000..7537560254f0 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_LTP.h +@@ -0,0 +1,64 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// Reset ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00000e60), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ea1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033a1), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032cc), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032bb), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338f), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d9), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f7), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fb), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fd), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000333a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338a), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032c4), 0x44); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003380), 0x30); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000323b), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033c5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003330), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031aa), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ac), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ad), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ae), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031af), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031aa), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ab), 0x28); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000316f), 0x7f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312d), 0x0c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003330), 0x41); ++// Setting 10T generate LTP output waveform ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031eb), 0x29); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312d), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000333a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003339), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003240), 0x30); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003187), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003140), 0xd2); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003141), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000315c), 0x01); +diff --git a/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_TP_IDL.h b/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_TP_IDL.h +new file mode 100755 +index 000000000000..a95d42b2e7cf +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/ETH_TX_10T_TP_IDL.h +@@ -0,0 +1,66 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// Reset ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00000e60), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ea1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032fd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033a1), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032cc), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032bb), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338f), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033d9), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f7), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fb), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033fd), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000333a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033f1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000338a), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000032c4), 0x44); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003380), 0x30); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000323b), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033c5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003330), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031aa), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ac), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ad), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ae), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031af), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000033e8), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031aa), 0x1c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000031ab), 0x28); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003187), 0x14); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000312d), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003180), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317e), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317a), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317b), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317c), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317d), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000317f), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003173), 0x0c); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00003140), 0xd2); +diff --git a/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p0_pd.h b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p0_pd.h +new file mode 100755 +index 000000000000..75265b6b7fe6 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p0_pd.h +@@ -0,0 +1,31 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// MIPI RX P0 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122600), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122602), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122608), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122609), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122610), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122611), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122618), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122619), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122640), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122641), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122646), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122647), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x12260b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122613), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x12261b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122643), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122649), 0x08); +diff --git a/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p1_pd.h b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p1_pd.h +new file mode 100755 +index 000000000000..1633288c9b50 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p1_pd.h +@@ -0,0 +1,31 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// MIPI RX P1 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122900), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122902), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122908), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122909), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122910), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122911), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122918), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122919), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122940), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122941), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122946), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122947), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x12290b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122913), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x12291b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122943), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122949), 0x08); +diff --git a/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p2_pd.h b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p2_pd.h +new file mode 100755 +index 000000000000..8acac5ade33f +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p2_pd.h +@@ -0,0 +1,31 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// MIPI RX P2 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c00), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c02), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c08), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c10), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c11), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c18), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c19), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c40), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c41), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c46), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c47), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c0b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c13), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c1b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c43), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x122c49), 0x08); +diff --git a/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p3_pd.h b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p3_pd.h +new file mode 100755 +index 000000000000..c2b2ee7e5d1d +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/Infinity2_mipi_rx_pd/Infinity2_mipi_rx_p3_pd.h +@@ -0,0 +1,31 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++// MIPI RX P3 power down ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123600), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123602), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123608), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123609), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123610), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123611), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123618), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123619), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123640), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123641), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123646), 0xa0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123647), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x12360b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123613), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x12361b), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123643), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x123649), 0x08); +diff --git a/drivers/sstar/include/infinity2/powerDown/U3CP_CP0_CP7_pattern_p0.h b/drivers/sstar/include/infinity2/powerDown/U3CP_CP0_CP7_pattern_p0.h +new file mode 100755 +index 000000000000..6ad0d999b6fe +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/U3CP_CP0_CP7_pattern_p0.h +@@ -0,0 +1,208 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102106), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102107), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102307), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002307), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a00), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a04), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a05), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a82), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a83), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a94), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a95), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103882), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103883), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103894), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103895), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001021a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102102), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102103), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102100), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102301), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002301), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002202), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002203), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002208), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002209), 0x11); ++ ++// SSC setting ++// wriu 0x000022c4 0x03 ++// wriu 0x000022c5 0x30 ++// wriu 0x000022c6 0xa0 ++// wriu 0x000022c7 0x04 ++// wriu 0x000022c8 0x04 ++// wriu 0x000022c9 0x00 ++// wriu 0x000022c0 0x75 ++// wriu 0x000022c1 0x93 ++// wriu 0x000022c2 0x18 ++// wriu 0x000022c3 0x00 ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022c0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022c1), 0x8e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022c2), 0x18); ++ ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e0), 0x75); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e1), 0x93); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e2), 0x18); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e6), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e7), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e8), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e9), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002312), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002313), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002218), 0x60); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002219), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000233a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000233b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002220), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002221), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002222), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002223), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e8e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e8f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e90), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e91), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e92), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e93), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e94), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e95), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e96), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e97), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e98), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e99), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9b), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9c), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea1), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea5), 0x00); ++ ++ ++// 3d00002e72, 8brxxxxxxxx //8rxx ++// 3d00002e73, 8brxxxxxxxx //8rxx ++// 3d00002e72, 8wxX ++// 3d00002e73, 8wxx ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e64), 0xe8); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e08), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e04), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000013c), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090700), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090701), 0x0a); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090702), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090703), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090708), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090709), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0009070a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0009070b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090730), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090731), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090732), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090733), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090750), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090751), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090752), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090753), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2534), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2535), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2536), 0x64); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2537), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1800), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1801), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1802), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1803), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1008), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1009), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a100a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a100b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c0), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d0), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241c), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180c), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2620), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2621), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2622), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2623), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); +diff --git a/drivers/sstar/include/infinity2/powerDown/U3CP_CP0_CP7_pattern_p1.h b/drivers/sstar/include/infinity2/powerDown/U3CP_CP0_CP7_pattern_p1.h +new file mode 100755 +index 000000000000..c1a6f2b6fd08 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/U3CP_CP0_CP7_pattern_p1.h +@@ -0,0 +1,206 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102106), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102107), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102307), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002307), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a00), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a04), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a05), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a82), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a83), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a94), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a95), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103882), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103883), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103894), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103895), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001021a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102102), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102103), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102100), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102301), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002301), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002305), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002202), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002203), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002208), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002209), 0x11); ++ ++// SSC setting ++// wriu 0x000022c4 0x03 ++// wriu 0x000022c5 0x30 ++// wriu 0x000022c6 0xa0 ++// wriu 0x000022c7 0x04 ++// wriu 0x000022c8 0x04 ++// wriu 0x000022c9 0x00 ++// wriu 0x000022c0 0x75 ++// wriu 0x000022c1 0x93 ++// wriu 0x000022c2 0x18 ++// wriu 0x000022c3 0x00 ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022c0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022c1), 0x8e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022c2), 0x18); ++ ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e0), 0x75); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e1), 0x93); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e2), 0x18); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e6), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e7), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e8), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000022e9), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002312), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002313), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002218), 0x60); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002219), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000233a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000233b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002220), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002221), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002222), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002223), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e8e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e8f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e90), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e91), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e92), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e93), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e94), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e95), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e96), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e97), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e98), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e99), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9b), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9c), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e9f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea1), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002ea5), 0x00); ++// 3d00002e72, 8brxxxxxxxx //8rxx ++// 3d00002e73, 8brxxxxxxxx //8rxx ++// 3d00002e72, 8wxX ++// 3d00002e73, 8wxx ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e64), 0xe8); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e04), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0000013c), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090700), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090701), 0x0a); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090702), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090703), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090708), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090709), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0009070a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0009070b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090730), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090731), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090732), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090733), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090750), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090751), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090752), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00090753), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2534), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2535), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2536), 0x64); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2537), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1800), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1801), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1802), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1803), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1008), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a1009), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a100a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a100b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c0), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a10c3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d0), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a26d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241c), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a241f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180c), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180e), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a180f), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2620), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2621), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2622), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000a2623), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002e42), 0x01); +diff --git a/drivers/sstar/include/infinity2/powerDown/U3PCIE_CP0_CP7_pattern_m_PHY_p0.h b/drivers/sstar/include/infinity2/powerDown/U3PCIE_CP0_CP7_pattern_m_PHY_p0.h +new file mode 100755 +index 000000000000..9a78f0d03f18 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/U3PCIE_CP0_CP7_pattern_m_PHY_p0.h +@@ -0,0 +1,244 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103380), 0x34); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103381), 0x12); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101e38), 0x00); ++//-------------------------------------- ++//Enable U3PCIE_PHY 1G clock pass ++//-------------------------------------- ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102106), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102107), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102307), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002307), 0x01); ++//-------------------------------------- ++//Enable UPLL ++//-------------------------------------- ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a00), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a04), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a05), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x01); ++//-------------------------------------- ++//Be careful of the order of utmi_ss ++//Initial UTMI_SS0 ++//-------------------------------------- ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a82), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a83), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a94), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a95), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103882), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103883), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103894), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103895), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++//============================== ++// UTMI_SS0 wait for clock ready ++//============================== ++//-------------------------------------- ++//Wait UTMI clock ready for U3PCIE_PHY ++//-------------------------------------- ++////////////////////////// ++// PHY POWER ON // ++////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001021a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102102), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102103), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102100), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102301), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002301), 0x00); ++////////////////////////// ++// 1. SIM ONLY SETING // ++////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102002), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102003), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102202), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102203), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102008), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102009), 0x11); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102208), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102209), 0x11); ++////////////////////////////////// ++// 3. enable PIPE3 interface ++////////////////////////////////// ++/////////////////////////////// ++//wriu 0x001020c4 0x03 ++//wriu 0x001020c5 0x30 ++//wriu 0x001020c6 0xa0 ++//wriu 0x001020c7 0x04 ++//wriu 0x001020c8 0x04 ++//wriu 0x001020c9 0x00 ++////////SSC//////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020c0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020c1), 0x8e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020c2), 0x18); ++//wriu 0x001020c3 0x00 ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020e0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020e1), 0x8e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020e2), 0x18); ++////////SSC//////////// ++//wriu 0x001020e3 0x00 ++//wriu 0x001020e4 0x00 ++//wriu 0x001020e5 0x00 ++//wriu 0x001020e6 0x00 ++//wriu 0x001020e7 0x00 ++//wriu 0x001020e8 0x04 ++//wriu 0x001020e9 0x00 ++/////////////////////////////// ++//wriu 0x001022c4 0x03 ++//wriu 0x001022c5 0x30 ++//wriu 0x001022c6 0xa0 ++//wriu 0x001022c7 0x04 ++//wriu 0x001022c8 0x04 ++//wriu 0x001022c9 0x00 ++//wriu 0x001022c0 0x75 ++//wriu 0x001022c1 0x93 ++//wriu 0x001022c2 0x18 ++//wriu 0x001022c3 0x00 ++//wriu 0x001022e0 0x75 ++//wriu 0x001022e1 0x93 ++//wriu 0x001022e2 0x18 ++//wriu 0x001022e3 0x00 ++//wriu 0x001022e4 0x00 ++//wriu 0x001022e5 0x00 ++//wriu 0x001022e6 0x00 ++//wriu 0x001022e7 0x00 ++//wriu 0x001022e8 0x04 ++//wriu 0x001022e9 0x00 ++/////////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102112), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102113), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102312), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102313), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102018), 0x60); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102019), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102218), 0x60); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102219), 0x05); ++///////////////////////////////////// ++// 4. Release PHY PD overrade enable ++///////////////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010233a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010233b), 0x00); ++///////////////////////// ++// 5. clkgen enable ++///////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102020), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102021), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102022), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102023), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102220), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102221), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102222), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102223), 0x00); ++/////////////////////// ++// 6 .Wait PIPE ready ++/////////////////////// ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00380020), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386817), 0x00); //hang ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213a), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213b), 0x00); ++ ++//Polling if reset is completed! ++//Delay 1ms ++//Delay 1ms ++//Connect SS device !! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Delay 360ms to let link into Compliance State!! ++//SS is now in CP0!! ++//Set following command to have CP1!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP2!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP3!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP4!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP5!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP6!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP7!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); ++//Set following command to have CP8!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386862), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00386863), 0x01); +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/U3PCIE_CP0_CP7_pattern_m_PHY_p1.h b/drivers/sstar/include/infinity2/powerDown/U3PCIE_CP0_CP7_pattern_m_PHY_p1.h +new file mode 100755 +index 000000000000..f3249ad4c717 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/U3PCIE_CP0_CP7_pattern_m_PHY_p1.h +@@ -0,0 +1,210 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103380), 0x34); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103381), 0x12); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101e38), 0x00); ++//-------------------------------------- ++//Enable U3PCIE_PHY 1G clock pass ++//-------------------------------------- ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102106), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102107), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102307), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002306), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002307), 0x01); ++//-------------------------------------- ++//Enable UPLL ++//-------------------------------------- ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a00), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a04), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a05), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0xc0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x01); ++//-------------------------------------- ++//Be careful of the order of utmi_ss ++//Initial UTMI_SS0 ++//-------------------------------------- ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a82), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a83), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a94), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a95), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103882), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103883), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103894), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103895), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b14), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b15), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++//============================== ++// UTMI_SS0 wait for clock ready ++//============================== ++//-------------------------------------- ++//Wait UTMI clock ready for U3PCIE_PHY ++//-------------------------------------- ++////////////////////////// ++// PHY POWER ON // ++////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001021a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102102), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102103), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102100), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102101), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102301), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x000023a1), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002302), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002303), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002300), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00002301), 0x00); ++////////////////////////// ++// 1. SIM ONLY SETING // ++////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102002), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102003), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102202), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102203), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102008), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102009), 0x11); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102208), 0x81); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102209), 0x11); ++////////////////////////////////// ++// 3. enable PIPE3 interface ++////////////////////////////////// ++////////SSC//////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020c0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020c1), 0x8e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020c2), 0x18); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020e0), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020e1), 0x8e); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001020e2), 0x18); ++/////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102112), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102113), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102312), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102313), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102018), 0x60); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102019), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102218), 0x60); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102219), 0x05); ++///////////////////////////////////// ++// 4. Release PHY PD overrade enable ++///////////////////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010233a), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010233b), 0x00); ++///////////////////////// ++// 5. clkgen enable ++///////////////////////// ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102020), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102021), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102022), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102023), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102220), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102221), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102222), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00102223), 0x00); ++/////////////////////// ++// 6 .Wait PIPE ready ++/////////////////////// ++//-------------------------------------- ++//USB3 PIPE3 Task Ends ++//-------------------------------------- ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00390020), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396817), 0x00);//hang ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213a), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010213b), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010233a), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x0010233b), 0x00); ++//Polling if reset is completed! ++//Delay 1ms ++//Delay 1ms ++//Connect SS device !! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Delay 360ms to let link into Compliance State!! ++//SS is now in CP0!! ++//Set following command to have CP1!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP2!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP3!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP4!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP5!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP6!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP7!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); ++//Set following command to have CP8!! ++OUTREG16(GET_REG_ADDR(RIU_BASE_ADDR, 0x0010013C), 0x0040); ++mdelay(100); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396862), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00396863), 0x01); +diff --git a/drivers/sstar/include/infinity2/powerDown/USB20_verification_pattern_TSTPG_FS_v2.h b/drivers/sstar/include/infinity2/powerDown/USB20_verification_pattern_TSTPG_FS_v2.h +new file mode 100755 +index 000000000000..e9f757ab846d +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/USB20_verification_pattern_TSTPG_FS_v2.h +@@ -0,0 +1,226 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++#define RIU_BASE_ADDR 0x1F000000 ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103380), 0x34); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103381), 0x12); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ed2), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ed3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113700), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113702), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113720), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113722), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113740), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113742), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010c00), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010c02), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100801), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100841), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100881), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a00), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a01), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a04), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a05), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x7f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x05); ++printk("TSTPG 1\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x7f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x7f); ++printk("TSTPG 2\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x7f); ++ ++//OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001012fe), 0xe1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001012ff), 0x08); ++ ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa0), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa1), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa2), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa3), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad2), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a82), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a83), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a20), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a21), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a22), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a23), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a52), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a52), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++printk("TSTPG 5\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a0), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a1), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a2), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a3), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d2), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103882), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103883), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++printk("TSTPG 6\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b20), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b21), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b22), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b23), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b52), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b02), 0x84); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b03), 0x90); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x02); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b52), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++//TE WAIT 1ms ++printk("TSTPG 7\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abc), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3c), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3c), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bc), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bd), 0x00); ++printk("TSTPG 8\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3c), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3c), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3d), 0x00); ++//TE WAIT 5ms ++printk("TSTPG 9\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a90), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a91), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a86), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a87), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a86), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a87), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0xeb); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad2), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a94), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a95), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab2), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab3), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a10), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a11), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a06), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a06), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0xeb); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a52), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a14), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a15), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a34), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a35), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a32), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a33), 0x0b); ++printk("TSTPG 10\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103890), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103891), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103886), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103887), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103886), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103887), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0xeb); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d2), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103894), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103895), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b2), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b3), 0x0b); ++printk("TSTPG 11\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b10), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b11), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b06), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b06), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0xeb); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b52), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b14), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b15), 0x07); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b34), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b35), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b32), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b33), 0x0b); ++printk("TSTPG 12\n"); +\ No newline at end of file +diff --git a/drivers/sstar/include/infinity2/powerDown/USB20_verification_pattern_TSTPG_v2.h b/drivers/sstar/include/infinity2/powerDown/USB20_verification_pattern_TSTPG_v2.h +new file mode 100755 +index 000000000000..25d31865d672 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/powerDown/USB20_verification_pattern_TSTPG_v2.h +@@ -0,0 +1,200 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++//****************************************************************************** ++// ++#define RIU_BASE_ADDR 0x1F000000 ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103380), 0x34); ++printk("TSTPG\n"); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103381), 0x12); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ed2), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00101ed3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113700), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113702), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113720), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113722), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113740), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00113742), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010c00), 0xff); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010c02), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100800), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100801), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100840), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100841), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100880), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100881), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a00), 0xb0); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a01), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100804), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100805), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100844), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100845), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100884), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00100885), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a04), 0x10); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010a05), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x7f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x7f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x7f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x05); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x7f); ++//OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001012fe), 0xe1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001012ff), 0x08); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a88), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a89), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa0), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa1), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa2), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103aa3), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x6b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad2), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a20), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a21), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a22), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a23), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x6b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a52), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103888), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103889), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a0), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a1), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a2), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038a3), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x6b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d2), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b08), 0x0f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b09), 0x04); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b20), 0xa1); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b21), 0x80); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b22), 0x88); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b23), 0x20); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x03); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x6b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b52), 0x3f); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b53), 0x00); ++//TE WAIT 1ms ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x69); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0xc3); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x69); ++//TE WAIT 2ms ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ad3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abc), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103abd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a52), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3c), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3c), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a3d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d2), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038d3), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bc), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bc), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038bd), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b52), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b53), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3c), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3d), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3c), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b3d), 0x00); ++//TE WAIT 2ms ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a90), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a91), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a86), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a87), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a86), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a87), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a80), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a81), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a94), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a95), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab2), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103ab3), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a10), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a11), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a06), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a06), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a14), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a15), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a34), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a35), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a32), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103a33), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103890), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103891), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103886), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103887), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103886), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103887), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103880), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103881), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103894), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00103895), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b4), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b5), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b2), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x001038b3), 0x0b); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b10), 0x78); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b11), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b06), 0x43); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b06), 0x40); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b07), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b00), 0x01); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b01), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b14), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b15), 0x06); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b34), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b35), 0x00); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b32), 0xfe); ++OUTREG8(GET_REG8_ADDRE(RIU_BASE_ADDR, 0x00010b33), 0x0b); +diff --git a/drivers/sstar/include/infinity2/regMIU.h b/drivers/sstar/include/infinity2/regMIU.h +new file mode 100755 +index 000000000000..6387b0028259 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/regMIU.h +@@ -0,0 +1,190 @@ ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file regMIU.h ++/// @brief MIU Control Register Definition ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_MIU_H_ ++#define _REG_MIU_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) ++#define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) ++#define MIU_REG_BASE (0x1200UL) ++#define MIU1_REG_BASE (0x0600UL) ++#define MIU2_REG_BASE (0x62000UL) ++#define PM_REG_BASE (0x1E00UL) ++#define MIU_ATOP_BASE (0x10D00UL) ++// #define MIU1_ATOP_BASE (0x61600UL) ++// #define MIU2_ATOP_BASE (0x62100UL) ++#define CHIP_TOP_BASE (0x1E00UL) ++#define MIU_ARB_REG_BASE (0x61500UL) ++#define MIU1_ARB_REG_BASE (0x62200UL) ++#define MIU2_ARB_REG_BASE (0x62300UL) ++ ++#define PM_CHIP_REVISION (PM_REG_BASE+0x03UL) // 0x1E03 ++#define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20UL) // 0x1220 ++#define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21UL) //0x1221 ++#define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25UL) //0x1225 ++#define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26UL) //0x1226 ++#define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27UL) //0x1227 ++#define DDR_CLK_SELECT (MIU_REG_BASE+0x3eUL) //0x123E ++#define DDR_FREQ_STATUS (MIU_REG_BASE+0x3fUL) //0x123F ++ ++#define MIU_RQ0L_MASK (MIU_REG_BASE+0x46UL) ++#define MIU_RQ0H_MASK (MIU_REG_BASE+0x47UL) ++#define MIU_RQ1L_MASK (MIU_REG_BASE+0x66UL) ++#define MIU_RQ1H_MASK (MIU_REG_BASE+0x67UL) ++#define MIU_RQ2L_MASK (MIU_REG_BASE+0x86UL) ++#define MIU_RQ2H_MASK (MIU_REG_BASE+0x87UL) ++#define MIU_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x46UL + 0x20UL*Group) : (MIU_ARB_REG_BASE + 0x06UL + 0x20UL * (Group - 4))) ++#define MIU_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x48UL + 0x20UL*Group) : (MIU_ARB_REG_BASE + 0x08UL + 0x20UL * (Group - 4))) ++ ++#define MIU_PROTECT_EN_INTERNAL (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3UL) ++#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(11:8) ++#define MIU_PROTECT_DDR_32MB (0x50UL) ++#define MIU_PROTECT_DDR_64MB (0x60UL) ++#define MIU_PROTECT_DDR_128MB (0x70UL) ++#define MIU_PROTECT_DDR_256MB (0x80UL) ++#define MIU_PROTECT_DDR_512MB (0x90UL) ++#define MIU_PROTECT_DDR_1024MB (0xA0UL) ++#define MIU_PROTECT_DDR_2048MB (0xB0UL) ++ ++ ++#define MIU_PROTECT0_ID0 (MIU_REG_BASE+0x2EUL) ++#define MIU_BW_REQUEST (MIU_REG_BASE+0x1AUL) ++#define MIU_BW_RESULT (MIU_REG_BASE+0x1CUL) ++#define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20UL) ++#define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22UL) ++#define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24UL) ++#define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26UL) ++#define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT0_START (MIU_REG_BASE+0xC0UL) ++#define MIU_PROTECT1_START (MIU_REG_BASE+0xC4UL) ++#define MIU_PROTECT2_START (MIU_REG_BASE+0xC8UL) ++#define MIU_PROTECT3_START (MIU_REG_BASE+0xCCUL) ++#define REG_MIU_PROTECT_ENGINE (0x69UL << 1) ++#define REG_MIU_PROTECT_LOADDR (0x6DUL << 1) //0xDE ++#define REG_MIU_PROTECT_HIADDR (0x6EUL << 1) //0xDE ++#define REG_MIU_GROUP_PRIORITY (0x7FUL << 1) ++#define REG_MIU_PROTECT_STATUS (0x6FUL << 1) //0xDE ++ ++// MIU selection registers ++#define REG_MIU_SEL0 (MIU_REG_BASE+0xf0UL) //0x12F0 ++#define REG_MIU_SEL1 (MIU_REG_BASE+0xf2UL) //0x12F1 ++#define REG_MIU_SEL2 (MIU_REG_BASE+0xf4UL) //0x12F2 ++#define REG_MIU_SEL3 (MIU_REG_BASE+0xf6UL) //0x12F3 ++#define REG_MIU_SELX(x) (0xF0UL+x*2) ++ ++//MIU1 ++#define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3UL) ++#define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2EUL) ++#define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1AUL) ++#define MIU1_BW_RESULT (MIU1_REG_BASE+0x1CUL) ++#define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20UL) ++#define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22UL) ++#define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24UL) ++#define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26UL) ++#define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0UL) ++#define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4UL) ++#define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8UL) ++#define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCCUL) ++#define MIU1_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x46UL + 0x20UL*Group) : (MIU1_ARB_REG_BASE + 0x06UL + 0x20UL * (Group - 4))) ++#define MIU1_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x48UL + 0x20UL*Group) : (MIU1_ARB_REG_BASE + 0x08UL + 0x20UL * (Group - 4))) ++ ++//MIU2 ++#define MIU2_PROTECT_EN (MIU2_REG_BASE+0xD2) ++#define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE+0xD3) ++#define MIU2_PROTECT0_ID0 (MIU2_REG_BASE+0x2E) ++#define MIU2_BW_REQUEST (MIU2_REG_BASE+0x1A) ++#define MIU2_BW_RESULT (MIU2_REG_BASE+0x1C) ++#define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE+0x20) ++#define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE+0x22) ++#define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE+0x24) ++#define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE+0x26) ++#define MIU2_PROTECT0_MSB (MIU2_REG_BASE+0xD0) ++#define MIU2_PROTECT0_START (MIU2_REG_BASE+0xC0) ++#define MIU2_PROTECT1_START (MIU2_REG_BASE+0xC4) ++#define MIU2_PROTECT2_START (MIU2_REG_BASE+0xC8) ++#define MIU2_PROTECT3_START (MIU2_REG_BASE+0xCC) ++#define MIU2_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU2_REG_BASE + 0x46UL + 0x20UL*Group) : (MIU2_ARB_REG_BASE + 0x06UL + 0x20UL * (Group - 4))) ++#define MIU2_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU2_REG_BASE + 0x48UL + 0x20UL*Group) : (MIU2_ARB_REG_BASE + 0x08UL + 0x20UL * (Group - 4))) ++ ++ ++#define REG_MIU_I64_MODE (BIT7) ++#define REG_MIU_INIT_DONE (BIT15) ++ ++//Protection Status ++#define REG_MIU_PROTECT_LOG_CLR (BIT0) ++#define REG_MIU_PROTECT_IRQ_MASK (BIT1) ++#define REG_MIU_PROTECT_HIT_FALG (BIT4) ++#define REG_MIU_PROTECT_HIT_ID 14:8 ++#define REG_MIU_PROTECT_HIT_NO 7:5 ++ ++// MIU Scramble ++#define REG_MIU_SCRAMBLE_EN (MIU_REG_BASE+0x06UL) ++ ++//MIU Bus Width ++#define REG_MI64_FORCE (CHIP_TOP_BASE+0x40UL) ++ ++//------------------------------------------------------------------------------------------------- ++//MAU ++// ++//------------------------------------------------------------------------------------------------- ++#define RIUBASE_MAU0 0x1840UL ++#define RIUBASE_MAU1 0x1860UL ++ ++ ++//------------------------------------------------------------------------------------------------- ++// MIU ATOP registers ++//------------------------------------------------------------------------------------------------- ++#define MIU_DDFSTEP (0x28UL)//0x110D28 ++#define MIU_SSC_EN (0x29UL)//0x110D29 ++#define MIU_DDFSPAN (0x2AUL)//0x110D2A ++#define MIU_DDFSET (0x30UL) ++#define MIU_PLL_INPUT_DIV_2ND (0x34UL) // no this reg in Einstein ++#define MIU_PLL_LOOP_DIV_2ND (0x34UL) ++//xxx_div_first ++#define MIU_PLLCTRL (0x36UL) ++#define MIU_DDRPLL_DIV_FIRST (0x37UL) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++#endif // _REG_MIU_H_ ++ +diff --git a/drivers/sstar/include/infinity2/reg_clks.h b/drivers/sstar/include/infinity2/reg_clks.h +new file mode 100755 +index 000000000000..fe0a4d4c50f3 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/reg_clks.h +@@ -0,0 +1,24 @@ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++#define REG_CKG0_BASE 0x1F201600 //0x100B ++//#define REG_SC_GP_CTRL_BASE 0x1F226600 ++//#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++//====NORMAL_CKG_REG============================================== ++ ++#define REG_CKG_UART0_BASE (REG_CKG0_BASE+(0x13<<2)) ++#define REG_CKG_UART0_OFFSET (8) ++#define REG_CKG_UART1_BASE (REG_CKG0_BASE+(0x14<<2)) ++#define REG_CKG_UART1_OFFSET (0) ++#define REG_CKG_UART2_BASE (REG_CKG0_BASE+(0x14<<2)) ++#define REG_CKG_UART2_OFFSET (8) ++#define REG_CKG_FUART_BASE (REG_CKG0_BASE+(0x17<<2)) ++#define REG_CKG_FUART_OFFSET (0) ++#define REG_CKG_FUARTSYN_BASE (REG_CKG0_BASE+(0x17<<2)) ++#define REG_CKG_FUARTSYN_OFFSET (4) ++#endif +diff --git a/drivers/sstar/include/infinity2/registers.h b/drivers/sstar/include/infinity2/registers.h +new file mode 100755 +index 000000000000..8894ba1097b4 +--- /dev/null ++++ b/drivers/sstar/include/infinity2/registers.h +@@ -0,0 +1,254 @@ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define MIU0_BASE 0x20000000 ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00800000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define CEVA_PHYS 0xC0000000 ++#define CEVA_VIRT 0xF9000000 ++#define CEVA_OFFSET (CEVA_VIRT-CEVA_PHYS) ++#define CEVA_SIZE 0x500000 ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0xFFFFFFFF ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++#define L2_CACHE_PHYS 0x15000000 ++#define L2_CACHE_VIRT (L2_CACHE_PHYS+L2_CACHE_OFFSET) ++#define L2_CACHE_OFFSET (MS_IO_OFFSET) ++#define L2_CACHE_SIZE 0x1000 ++ ++#ifdef CONFIG_MS_DUAL_OS_SUPPORT ++#define IPC_MEM_PHYS 0x58000000 ++#define IPC_MEM_VIRT 0xFE000000 //(IPC_MEM_PHYS+IPC_MEM_OFFSET) ++#define IPC_MEM_OFFSET (MS_IO_OFFSET) ++#define IPC_MEM_SIZE 0x100000 ++#endif ++ ++#define PREFETCH_CTL_REG 0xF60 ++#define DOUBLE_LINEFILL_ENABLE 0x40000000 //[30] ++#define I_PREFETCH_ENABLE 0x20000000 //[29] ++#define D_PREFETCH_ENABLE 0x10000000 //[28] ++#define LINEFILL_WRAP_DISABLE 0x08000000 //[27] ++#define PREFETCH_OFFSET 0x00000000 //[4:0] ,only support 0-7,15,23,31 ++ ++#define L2_CACHE_p2v(pa) ((pa) + L2_CACHE_OFFSET) ++#define L2_CACHE_ADDRESS(x) L2_CACHE_p2v(x) ++#define L2_CACHE_write(v,a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a) = (v)) ++#define L2_CACHE_read(a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a)) ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0xA5000 ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103340) ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_INTRCTL_PA1 GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101000) //intr_ctrl_cpu2~3 ++#define BASE_REG_INTRCTL_PA0 GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101900) //intr_ctrl_cpu2~3 ++#define BASE_REG_MCU_ARM GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101D00) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_IRQ_PM GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x002b00) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100800) //upll0 ++#define BASE_REG_UPLL1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100840) //upll1 ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103A00) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103300) ++#define BASE_REG_CLKGEN0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100B00) ++#define BASE_REG_CLKGEN1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103300) ++#define BASE_REG_CLKGEN2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100A00) ++#define BASE_REG_PADTOP1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x102600) ++#define BASE_REG_IIC0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_MOVDMA_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x112500) ++#define BASE_REG_BDMA0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100920) ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0600) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3000) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I2_PACKAGE_UNKNOWN =0x00, ++ MS_I2_PACKAGE_BGA_1GB, ++ MS_I2_PACKAGE_FPGA_128MB =0x90, ++} MS_I2_PACKAGE_TYPE; ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity2/vcore_dvfs.h b/drivers/sstar/include/infinity2/vcore_dvfs.h +new file mode 100755 +index 000000000000..03a019a293ee +--- /dev/null ++++ b/drivers/sstar/include/infinity2/vcore_dvfs.h +@@ -0,0 +1,56 @@ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2019 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// vcore_dvfs.h ++// ++// DESCRIPTION ++// ++// ++// HISTORY ++// ++//----------------------------------------------------------------------------- ++#ifndef __VCORE_DVFS_H ++#define __VCORE_DVFS_H ++ ++ ++ ++#define VCORE_DVFS_IOC_MAGIC 'v' ++#define VCORE_DVFS_INIT _IO(VCORE_DVFS_IOC_MAGIC, 0) ++#define VCORE_DVFS_OP _IO(VCORE_DVFS_IOC_MAGIC, 1) ++ ++#define VCORE_DVFS_IOC_MAXNR 1 ++ ++ ++ ++typedef enum ++{ ++ VCORE_DVFS_DEMANDER_CEVA_PLL, ++ VCORE_DVFS_DEMANDER_TOTAL, ++ ++} vcore_dvfs_demander_e; ++ ++ ++ ++struct vcore_dvfs_init_data { ++ unsigned long rate; ++ int active; ++}; ++ ++ ++ ++typedef int (*set_rate_hw)(unsigned long rate); ++typedef int (*clk_enable_hw)(void); ++typedef int (*clk_disable_hw)(void); ++ ++ ++ ++extern int vcore_dvfs_register(vcore_dvfs_demander_e demander, struct vcore_dvfs_init_data *init_data); ++extern int vcore_dvfs_unregister(vcore_dvfs_demander_e demander); ++extern int vcore_dvfs_clk_enable(vcore_dvfs_demander_e demander, clk_enable_hw clk_enable_hw); ++extern int vcore_dvfs_clk_disable(vcore_dvfs_demander_e demander, clk_disable_hw clk_disable_hw); ++extern int vcore_dvfs_clk_set_rate(vcore_dvfs_demander_e demander, unsigned long rate, set_rate_hw set_rate_hw); ++ ++#endif +diff --git a/drivers/sstar/include/infinity2m/Kconfig b/drivers/sstar/include/infinity2m/Kconfig +new file mode 100644 +index 000000000000..da71730ca7e3 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/Kconfig +@@ -0,0 +1,10 @@ ++source "drivers/sstar/emmc/Kconfig" ++source "drivers/sstar/sdmmc/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/crypto/Kconfig" ++source "drivers/sstar/cpufreq/Kconfig" ++source "drivers/sstar/miu/Kconfig" ++source "drivers/sstar/bdma/Kconfig" ++source "drivers/sstar/movedma/Kconfig" ++source "drivers/sstar/sata_host/Kconfig" ++ +diff --git a/drivers/sstar/include/infinity2m/camclk.h b/drivers/sstar/include/infinity2m/camclk.h +new file mode 100644 +index 000000000000..eef5168553c9 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/camclk.h +@@ -0,0 +1,185 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_upll_384m 3 ++#define CAMCLK_upll_320m 4 ++#define CAMCLK_mpll_288m 5 ++#define CAMCLK_utmi_240m 6 ++#define CAMCLK_mpll_216m 7 ++#define CAMCLK_utmi_192m 8 ++#define CAMCLK_mpll_172m 9 ++#define CAMCLK_utmi_160m 10 ++#define CAMCLK_mpll_123m 11 ++#define CAMCLK_mpll_86m 12 ++#define CAMCLK_mpll_288m_div2 13 ++#define CAMCLK_mpll_288m_div4 14 ++#define CAMCLK_mpll_288m_div8 15 ++#define CAMCLK_mpll_288m_div32 16 ++#define CAMCLK_mpll_216m_div2 17 ++#define CAMCLK_mpll_216m_div4 18 ++#define CAMCLK_mpll_216m_div8 19 ++#define CAMCLK_mpll_123m_div2 20 ++#define CAMCLK_mpll_86m_div2 21 ++#define CAMCLK_mpll_86m_div4 22 ++#define CAMCLK_mpll_86m_div16 23 ++#define CAMCLK_utmi_192m_div4 24 ++#define CAMCLK_utmi_160m_div4 25 ++#define CAMCLK_utmi_160m_div5 26 ++#define CAMCLK_utmi_160m_div8 27 ++#define CAMCLK_xtali_12m 28 ++#define CAMCLK_xtali_12m_div8 29 ++#define CAMCLK_xtali_12m_div16 30 ++#define CAMCLK_xtali_12m_div40 31 ++#define CAMCLK_xtali_12m_div64 32 ++#define CAMCLK_xtali_12m_div128 33 ++#define CAMCLK_xtali_24m 34 ++#define CAMCLK_RTC_CLK_32K 35 ++#define CAMCLK_pm_riu_w_clk_in 36 ++#define CAMCLK_lpll_clk_div2 37 ++#define CAMCLK_lpll_clk_div4 38 ++#define CAMCLK_lpll_clk_div8 39 ++#define CAMCLK_riu_w_clk_in 40 ++#define CAMCLK_riu_w_clk_top 41 ++#define CAMCLK_riu_w_clk_sc_gp 42 ++#define CAMCLK_riu_w_clk_vhe_gp 43 ++#define CAMCLK_riu_w_clk_dec_gp 44 ++#define CAMCLK_riu_w_clk_hemcu_gp 45 ++#define CAMCLK_riu_w_clk_mipi_if_gp 46 ++#define CAMCLK_riu_w_clk_mcu_if_gp 47 ++#define CAMCLK_miu_p 48 ++#define CAMCLK_mspi0_p 49 ++#define CAMCLK_mspi1_p 50 ++#define CAMCLK_miu_sc_gp_p 51 ++#define CAMCLK_miu2x_p 52 ++#define CAMCLK_mcu_p 53 ++#define CAMCLK_mcu_pm_p 54 ++#define CAMCLK_sdio_p 55 ++#define CAMCLK_fcie_p 56 ++#define CAMCLK_tck_buf 57 ++#define CAMCLK_pad2isp_sr_pclk 58 ++#define CAMCLK_csi2_mac_p 59 ++#define CAMCLK_mipi_tx_dsi_p 60 ++#define CAMCLK_sc_pixel_p 61 ++#define CAMCLK_ccir_in_clk 62 ++#define CAMCLK_eth_buf 63 ++#define CAMCLK_rmii_buf 64 ++#define CAMCLK_emac_testrx125_in_lan 65 ++#define CAMCLK_armpll_37p125m 66 ++#define CAMCLK_hdmi_in 67 ++#define CAMCLK_dac_in 68 ++#define CAMCLK_miu_ff 69 ++#define CAMCLK_miu_sc_gp 70 ++#define CAMCLK_miu_dec_gp 71 ++#define CAMCLK_miu_dig 72 ++#define CAMCLK_miu_urdma 73 ++#define CAMCLK_miu_miic0 74 ++#define CAMCLK_miu_miic1 75 ++#define CAMCLK_miu_dma0 76 ++#define CAMCLK_riu 77 ++#define CAMCLK_riu_nogating 78 ++#define CAMCLK_riu_sc_gp 79 ++#define CAMCLK_riu_dec_gp 80 ++#define CAMCLK_riu_hemcu_gp 81 ++#define CAMCLK_riu_mipi_gp 82 ++#define CAMCLK_riu_mcu_if 83 ++#define CAMCLK_miu2x 84 ++#define CAMCLK_axi2x 85 ++#define CAMCLK_mpll_144m 86 ++#define CAMCLK_mpll_144m_div2 87 ++#define CAMCLK_mpll_144m_div4 88 ++#define CAMCLK_xtali_12m_div2 89 ++#define CAMCLK_xtali_12m_div4 90 ++#define CAMCLK_xtali_12m_div12 91 ++#define CAMCLK_rtc_32k 92 ++#define CAMCLK_rtc_32k_div4 93 ++#define CAMCLK_live_pm 94 ++#define CAMCLK_mcu_pm 95 ++#define CAMCLK_riu_pm 96 ++#define CAMCLK_miupll_clk 97 ++#define CAMCLK_ddrpll_clk 98 ++#define CAMCLK_lpll_clk 99 ++#define CAMCLK_cpupll_clk 100 ++#define CAMCLK_utmi 101 ++#define CAMCLK_upll 102 ++#define CAMCLK_fuart0_synth_out 103 ++#define CAMCLK_miu 104 ++#define CAMCLK_miu_xd2miu 105 ++#define CAMCLK_bdma 106 ++#define CAMCLK_ddr_syn 107 ++#define CAMCLK_miu_rec 108 ++#define CAMCLK_mcu 109 ++#define CAMCLK_riubrdg 110 ++#define CAMCLK_spi 111 ++#define CAMCLK_uart0 112 ++#define CAMCLK_uart1 113 ++#define CAMCLK_uart2 114 ++#define CAMCLK_fuart0_synth_in 115 ++#define CAMCLK_fuart 116 ++#define CAMCLK_mspi0 117 ++#define CAMCLK_mspi1 118 ++#define CAMCLK_mspi 119 ++#define CAMCLK_miic0 120 ++#define CAMCLK_miic1 121 ++#define CAMCLK_bist 122 ++#define CAMCLK_pwr_ctl 123 ++#define CAMCLK_xtali 124 ++#define CAMCLK_live_c 125 ++#define CAMCLK_live 126 ++#define CAMCLK_sata_phy_108 127 ++#define CAMCLK_sata_phy_432 128 ++#define CAMCLK_disp_432 129 ++#define CAMCLK_bist_dec_gp 130 ++#define CAMCLK_dec_pclk 131 ++#define CAMCLK_dec_aclk 132 ++#define CAMCLK_dec_bclk 133 ++#define CAMCLK_dec_cclk 134 ++#define CAMCLK_xtali_sc_gp 135 ++#define CAMCLK_bist_sc_gp 136 ++#define CAMCLK_emac_ahb 137 ++#define CAMCLK_jpe 138 ++#define CAMCLK_aesdma 139 ++#define CAMCLK_sdio 140 ++#define CAMCLK_dip 141 ++#define CAMCLK_ge 142 ++#define CAMCLK_mop 143 ++#define CAMCLK_disp_216 144 ++#define CAMCLK_sc_pixel 145 ++#define CAMCLK_sata_pm 146 ++#define CAMCLK_sata_axi 147 ++#define CAMCLK_mipi_tx_dsi 148 ++#define CAMCLK_mipi_tx_dsi_apb 149 ++#define CAMCLK_hdmi 150 ++#define CAMCLK_dac 151 ++#define CAMCLK_emac1_tx 152 ++#define CAMCLK_emac1_rx 153 ++#define CAMCLK_emac1_tx_ref 154 ++#define CAMCLK_emac1_rx_ref 155 ++#define CAMCLK_emac_tx 156 ++#define CAMCLK_emac_rx 157 ++#define CAMCLK_emac_tx_ref 158 ++#define CAMCLK_emac_rx_ref 159 ++#define CAMCLK_hemcu_216m 160 ++#define CAMCLK_spi_pm 161 ++#define CAMCLK_pm_sleep 162 ++#define CAMCLK_pwm 163 ++#define CAMCLK_sar 164 ++#define CAMCLK_rtc 165 ++#define CAMCLK_ir 166 ++#endif +diff --git a/drivers/sstar/include/infinity2m/gpi-irqs.h b/drivers/sstar/include/infinity2m/gpi-irqs.h +new file mode 100755 +index 000000000000..2dc8c5644a0a +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/gpi-irqs.h +@@ -0,0 +1,113 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++#define GPI_FIQ_START 0 ++#define INT_GPI_FIQ_UART1_RX (GPI_FIQ_START + 0) ++#define INT_GPI_FIQ_UART1_TX (GPI_FIQ_START + 1) ++#define INT_GPI_FIQ_UART0_RX (GPI_FIQ_START + 2) ++#define INT_GPI_FIQ_UART0_TX (GPI_FIQ_START + 3) ++#define INT_GPI_FIQ_TTL0 (GPI_FIQ_START + 4) ++#define INT_GPI_FIQ_TTL1 (GPI_FIQ_START + 5) ++#define INT_GPI_FIQ_TTL2 (GPI_FIQ_START + 6) ++#define INT_GPI_FIQ_TTL3 (GPI_FIQ_START + 7) ++#define INT_GPI_FIQ_TTL4 (GPI_FIQ_START + 8) ++#define INT_GPI_FIQ_TTL5 (GPI_FIQ_START + 9) ++#define INT_GPI_FIQ_TTL6 (GPI_FIQ_START + 10) ++#define INT_GPI_FIQ_TTL7 (GPI_FIQ_START + 11) ++#define INT_GPI_FIQ_TTL8 (GPI_FIQ_START + 12) ++#define INT_GPI_FIQ_TTL9 (GPI_FIQ_START + 13) ++#define INT_GPI_FIQ_TTL10 (GPI_FIQ_START + 14) ++#define INT_GPI_FIQ_TTL11 (GPI_FIQ_START + 15) ++#define INT_GPI_FIQ_TTL12 (GPI_FIQ_START + 16) ++#define INT_GPI_FIQ_TTL13 (GPI_FIQ_START + 17) ++#define INT_GPI_FIQ_TTL14 (GPI_FIQ_START + 18) ++#define INT_GPI_FIQ_TTL15 (GPI_FIQ_START + 19) ++#define INT_GPI_FIQ_TTL16 (GPI_FIQ_START + 20) ++#define INT_GPI_FIQ_TTL17 (GPI_FIQ_START + 21) ++#define INT_GPI_FIQ_TTL18 (GPI_FIQ_START + 22) ++#define INT_GPI_FIQ_TTL19 (GPI_FIQ_START + 23) ++#define INT_GPI_FIQ_TTL20 (GPI_FIQ_START + 24) ++#define INT_GPI_FIQ_TTL21 (GPI_FIQ_START + 25) ++#define INT_GPI_FIQ_TTL22 (GPI_FIQ_START + 26) ++#define INT_GPI_FIQ_TTL23 (GPI_FIQ_START + 27) ++#define INT_GPI_FIQ_TTL24 (GPI_FIQ_START + 28) ++#define INT_GPI_FIQ_TTL25 (GPI_FIQ_START + 29) ++#define INT_GPI_FIQ_TTL26 (GPI_FIQ_START + 30) ++#define INT_GPI_FIQ_TTL27 (GPI_FIQ_START + 31) ++#define INT_GPI_FIQ_SD_D0 (GPI_FIQ_START + 32) ++#define INT_GPI_FIQ_SD_D1 (GPI_FIQ_START + 33) ++#define INT_GPI_FIQ_SD_D2 (GPI_FIQ_START + 34) ++#define INT_GPI_FIQ_SD_D3 (GPI_FIQ_START + 35) ++#define INT_GPI_FIQ_SD_CMD (GPI_FIQ_START + 36) ++#define INT_GPI_FIQ_SD_CLK (GPI_FIQ_START + 37) ++#define INT_GPI_FIQ_SD_GPIO (GPI_FIQ_START + 38) ++#define INT_GPI_FIQ_SATA_GPIO (GPI_FIQ_START + 39) ++#define INT_GPI_FIQ_HSYNC_OUT (GPI_FIQ_START + 40) ++#define INT_GPI_FIQ_VSYNC_OUT (GPI_FIQ_START + 41) ++#define INT_GPI_FIQ_HDMITX_SCL (GPI_FIQ_START + 42) ++#define INT_GPI_FIQ_HDMITX_SDA (GPI_FIQ_START + 43) ++#define INT_GPI_FIQ_HDMITX_HPD (GPI_FIQ_START + 44) ++#define INT_GPI_FIQ_GPIO0 (GPI_FIQ_START + 45) ++#define INT_GPI_FIQ_GPIO1 (GPI_FIQ_START + 46) ++#define INT_GPI_FIQ_GPIO2 (GPI_FIQ_START + 47) ++#define INT_GPI_FIQ_GPIO3 (GPI_FIQ_START + 48) ++#define INT_GPI_FIQ_GPIO4 (GPI_FIQ_START + 49) ++#define INT_GPI_FIQ_GPIO5 (GPI_FIQ_START + 50) ++#define INT_GPI_FIQ_GPIO6 (GPI_FIQ_START + 51) ++#define INT_GPI_FIQ_GPIO7 (GPI_FIQ_START + 52) ++#define INT_GPI_FIQ_GPIO8 (GPI_FIQ_START + 53) ++#define INT_GPI_FIQ_GPIO9 (GPI_FIQ_START + 54) ++#define INT_GPI_FIQ_GPIO10 (GPI_FIQ_START + 55) ++#define INT_GPI_FIQ_GPIO11 (GPI_FIQ_START + 56) ++#define INT_GPI_FIQ_GPIO12 (GPI_FIQ_START + 57) ++#define INT_GPI_FIQ_GPIO13 (GPI_FIQ_START + 58) ++#define INT_GPI_FIQ_GPIO14 (GPI_FIQ_START + 59) ++#define INT_GPI_FIQ_FUART_RX (GPI_FIQ_START + 60) ++#define INT_GPI_FIQ_FUART_TX (GPI_FIQ_START + 61) ++#define INT_GPI_FIQ_FUART_CTS (GPI_FIQ_START + 62) ++#define INT_GPI_FIQ_FUART_RTS (GPI_FIQ_START + 63) ++#define INT_GPI_FIQ_DUMMY64 (GPI_FIQ_START + 64) ++#define INT_GPI_FIQ_DUMMY65 (GPI_FIQ_START + 65) ++#define INT_GPI_FIQ_DUMMY66 (GPI_FIQ_START + 66) ++#define INT_GPI_FIQ_DUMMY67 (GPI_FIQ_START + 67) ++#define INT_GPI_FIQ_DUMMY68 (GPI_FIQ_START + 68) ++#define INT_GPI_FIQ_DUMMY69 (GPI_FIQ_START + 69) ++#define INT_GPI_FIQ_DUMMY70 (GPI_FIQ_START + 70) ++#define INT_GPI_FIQ_DUMMY71 (GPI_FIQ_START + 71) ++#define INT_GPI_FIQ_DUMMY72 (GPI_FIQ_START + 72) ++#define INT_GPI_FIQ_DUMMY73 (GPI_FIQ_START + 73) ++#define INT_GPI_FIQ_DUMMY74 (GPI_FIQ_START + 74) ++#define INT_GPI_FIQ_DUMMY75 (GPI_FIQ_START + 75) ++#define GPI_FIQ_END (GPI_FIQ_START + 76) ++#define GPI_FIQ_NUM (GPI_FIQ_END - GPI_FIQ_START) ++ ++#define GPI_IRQ_START 0 ++#define INT_GPI_IRQ_DUMMY00 (GPI_IRQ_START + 0) ++#define INT_GPI_IRQ_DUMMY01 (GPI_IRQ_START + 1) ++#define INT_GPI_IRQ_DUMMY02 (GPI_IRQ_START + 2) ++#define INT_GPI_IRQ_DUMMY03 (GPI_IRQ_START + 3) ++#define INT_GPI_IRQ_DUMMY04 (GPI_IRQ_START + 4) ++#define INT_GPI_IRQ_DUMMY05 (GPI_IRQ_START + 5) ++#define INT_GPI_IRQ_DUMMY06 (GPI_IRQ_START + 6) ++#define INT_GPI_IRQ_DUMMY07 (GPI_IRQ_START + 7) ++#define GPI_IRQ_END (GPI_IRQ_START + 8) ++#define GPI_IRQ_NUM (GPI_IRQ_END - GPI_IRQ_START) +diff --git a/drivers/sstar/include/infinity2m/gpio.h b/drivers/sstar/include/infinity2m/gpio.h +new file mode 100644 +index 000000000000..4f65ceaca083 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/gpio.h +@@ -0,0 +1,116 @@ ++/* ++* gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __GPIO_H__ ++#define __GPIO_H__ ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO10 10 ++#define PAD_GPIO11 11 ++#define PAD_GPIO12 12 ++#define PAD_GPIO13 13 ++#define PAD_GPIO14 14 ++#define PAD_FUART_RX 15 ++#define PAD_FUART_TX 16 ++#define PAD_FUART_CTS 17 ++#define PAD_FUART_RTS 18 ++#define PAD_TTL0 19 ++#define PAD_TTL1 20 ++#define PAD_TTL2 21 ++#define PAD_TTL3 22 ++#define PAD_TTL4 23 ++#define PAD_TTL5 24 ++#define PAD_TTL6 25 ++#define PAD_TTL7 26 ++#define PAD_TTL8 27 ++#define PAD_TTL9 28 ++#define PAD_TTL10 29 ++#define PAD_TTL11 30 ++#define PAD_TTL12 31 ++#define PAD_TTL13 32 ++#define PAD_TTL14 33 ++#define PAD_TTL15 34 ++#define PAD_TTL16 35 ++#define PAD_TTL17 36 ++#define PAD_TTL18 37 ++#define PAD_TTL19 38 ++#define PAD_TTL20 39 ++#define PAD_TTL21 40 ++#define PAD_TTL22 41 ++#define PAD_TTL23 42 ++#define PAD_TTL24 43 ++#define PAD_TTL25 44 ++#define PAD_TTL26 45 ++#define PAD_TTL27 46 ++#define PAD_UART0_RX 47 ++#define PAD_UART0_TX 48 ++#define PAD_UART1_RX 49 ++#define PAD_UART1_TX 50 ++#define PAD_SD_CLK 51 ++#define PAD_SD_CMD 52 ++#define PAD_SD_D0 53 ++#define PAD_SD_D1 54 ++#define PAD_SD_D2 55 ++#define PAD_SD_D3 56 ++#define PAD_SD_GPIO 57 ++#define PAD_PM_SD_CDZ 58 ++#define PAD_PM_IRIN 59 ++#define PADA_IDAC_OUT_B 60 ++#define PADA_IDAC_OUT_G 61 ++#define PADA_IDAC_OUT_R 62 ++#define PAD_PM_SPI_CZ 63 ++#define PAD_PM_SPI_CK 64 ++#define PAD_PM_SPI_DI 65 ++#define PAD_PM_SPI_DO 66 ++#define PAD_PM_SPI_WPZ 67 ++#define PAD_PM_SPI_HLD 68 ++#define PAD_PM_LED0 69 ++#define PAD_PM_LED1 70 ++#define PAD_SAR_GPIO0 71 ++#define PAD_SAR_GPIO1 72 ++#define PAD_SAR_GPIO2 73 ++#define PAD_SAR_GPIO3 74 ++#define PAD_ETH_RN 75 ++#define PAD_ETH_RP 76 ++#define PAD_ETH_TN 77 ++#define PAD_ETH_TP 78 ++#define PAD_DM_P1 79 ++#define PAD_DP_P1 80 ++#define PAD_DM_P2 81 ++#define PAD_DP_P2 82 ++#define PAD_DM_P3 83 ++#define PAD_DP_P3 84 ++#define PAD_HSYNC_OUT 85 ++#define PAD_VSYNC_OUT 86 ++#define PAD_HDMITX_SCL 87 ++#define PAD_HDMITX_SDA 88 ++#define PAD_HDMITX_HPD 89 ++#define PAD_SATA_GPIO 90 ++ ++#define GPIO_NR 91 ++#define PAD_UNKNOWN 0xFFFF ++ ++#endif // __GPIO_H__ +diff --git a/drivers/sstar/include/infinity2m/irqs.h b/drivers/sstar/include/infinity2m/irqs.h +new file mode 100644 +index 000000000000..c72fc12b4755 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/irqs.h +@@ -0,0 +1,251 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++#include "gpi-irqs.h" ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_SAR_GPIO_WK (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_POWER_0_NG (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_POWER_1_NG (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DUMMY_09 (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_DUMMY_10 (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_DUMMY_11 (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_PM_ERROR_RESP (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_WAKE_ON_LAN (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_PWM_HOLD (GIC_SPI_MS_IRQ_START + 14) //I2m modified ++#define INT_IRQ_PWM_ROUND (GIC_SPI_MS_IRQ_START + 15) //I2m modified ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_SATA (GIC_SPI_MS_IRQ_START + 18) //I2m modified ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_DISP0 (GIC_SPI_MS_IRQ_START + 20) //I2m modified ++#define INT_IRQ_DEC (GIC_SPI_MS_IRQ_START + 21) //I2m modified ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_GE (GIC_SPI_MS_IRQ_START + 25) //I2m modified ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) ++#define INT_IRQ_DUMMY_12 (GIC_SPI_MS_IRQ_START + 28) //I2m modified ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB_P3 (GIC_SPI_MS_IRQ_START + 30) //I2m modified ++#define INT_IRQ_UHC_P3 (GIC_SPI_MS_IRQ_START + 31) //I2m modified ++#define INT_IRQ_USB_P2 (GIC_SPI_MS_IRQ_START + 32) //I2m modified ++#define INT_IRQ_UHC_P2 (GIC_SPI_MS_IRQ_START + 33) //I2m modified ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_UART_2 (GIC_SPI_MS_IRQ_START + 39) //I2m modified ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_DISP_1 (GIC_SPI_MS_IRQ_START + 50) //I2m modified ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_EMAC_1 (GIC_SPI_MS_IRQ_START + 52) //I2m modified ++#define INT_IRQ_MMU (GIC_SPI_MS_IRQ_START + 53) //I2m new ++#define INT_IRQ_USB_INT_P1 (GIC_SPI_MS_IRQ_START + 54) ++#define INT_IRQ_UHC_INT_P1 (GIC_SPI_MS_IRQ_START + 55) ++#define INT_IRQ_GPI (GIC_SPI_MS_IRQ_START + 56) ++#define INT_IRQ_MIPI_TX_DSI (GIC_SPI_MS_IRQ_START + 57) //I2m modified ++#define INT_IRQ_DISP_2 (GIC_SPI_MS_IRQ_START + 58) //I2m modified ++#define INT_IRQ_DISP_3 (GIC_SPI_MS_IRQ_START + 59) //I2m modified ++#define INT_IRQ_MOVEDMA (GIC_SPI_MS_IRQ_START + 60) //I6 new ++#define INT_IRQ_BDMA_2 (GIC_SPI_MS_IRQ_START + 61) //I6 new ++#define INT_IRQ_BDMA_3 (GIC_SPI_MS_IRQ_START + 62) //I6 new ++#define INT_IRQ_DIP0 (GIC_SPI_MS_IRQ_START + 63) //I6 new ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_DUMMY_0 (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_DUMMY_1 (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_DUMMY_2 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_DUMMY_3 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_DUMMY_4 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_DUMMY_5 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_DUMMY_6 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_DUMMY_7 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_DUMMY_8 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_DUMMY_9 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_DUMMY_10 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_DUMMY_11 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_DUMMY_12 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_DUMMY_13 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_DUMMY_14 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_DUMMY_15 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_DUMMY_16 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_DUMMY_17 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_DUMMY_18 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_DUMMY_19 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_DUMMY_22 (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_DUMMY_23 (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_32 (PMSLEEP_FIQ_START + 32) ++#define INT_PMSLEEP_DUMMY_33 (PMSLEEP_FIQ_START + 33) ++#define INT_PMSLEEP_DUMMY_34 (PMSLEEP_FIQ_START + 34) ++#define INT_PMSLEEP_DUMMY_35 (PMSLEEP_FIQ_START + 35) ++#define INT_PMSLEEP_DUMMY_36 (PMSLEEP_FIQ_START + 36) ++#define INT_PMSLEEP_DUMMY_37 (PMSLEEP_FIQ_START + 37) ++#define INT_PMSLEEP_DUMMY_38 (PMSLEEP_FIQ_START + 38) ++#define INT_PMSLEEP_DUMMY_39 (PMSLEEP_FIQ_START + 39) ++#define INT_PMSLEEP_DUMMY_40 (PMSLEEP_FIQ_START + 40) ++#define INT_PMSLEEP_DUMMY_41 (PMSLEEP_FIQ_START + 41) ++#define INT_PMSLEEP_DUMMY_42 (PMSLEEP_FIQ_START + 42) ++#define INT_PMSLEEP_DUMMY_43 (PMSLEEP_FIQ_START + 43) ++#define INT_PMSLEEP_DUMMY_44 (PMSLEEP_FIQ_START + 44) ++#define INT_PMSLEEP_DUMMY_45 (PMSLEEP_FIQ_START + 45) ++#define INT_PMSLEEP_DUMMY_46 (PMSLEEP_FIQ_START + 46) ++#define INT_PMSLEEP_DUMMY_47 (PMSLEEP_FIQ_START + 47) ++#define INT_PMSLEEP_DUMMY_48 (PMSLEEP_FIQ_START + 48) ++#define INT_PMSLEEP_DUMMY_49 (PMSLEEP_FIQ_START + 49) ++#define INT_PMSLEEP_DUMMY_50 (PMSLEEP_FIQ_START + 50) ++#define INT_PMSLEEP_DUMMY_51 (PMSLEEP_FIQ_START + 51) ++#define INT_PMSLEEP_DUMMY_52 (PMSLEEP_FIQ_START + 52) ++#define INT_PMSLEEP_DUMMY_53 (PMSLEEP_FIQ_START + 53) ++#define INT_PMSLEEP_DUMMY_54 (PMSLEEP_FIQ_START + 54) ++#define INT_PMSLEEP_DUMMY_55 (PMSLEEP_FIQ_START + 55) ++#define INT_PMSLEEP_DUMMY_56 (PMSLEEP_FIQ_START + 56) ++#define INT_PMSLEEP_DUMMY_57 (PMSLEEP_FIQ_START + 57) ++#define INT_PMSLEEP_DUMMY_58 (PMSLEEP_FIQ_START + 58) ++#define INT_PMSLEEP_DUMMY_59 (PMSLEEP_FIQ_START + 59) ++#define INT_PMSLEEP_DUMMY_60 (PMSLEEP_FIQ_START + 60) ++#define INT_PMSLEEP_DUMMY_61 (PMSLEEP_FIQ_START + 61) ++#define INT_PMSLEEP_DUMMY_62 (PMSLEEP_FIQ_START + 62) ++#define INT_PMSLEEP_DUMMY_63 (PMSLEEP_FIQ_START + 63) ++#define INT_PMSLEEP_DUMMY_64 (PMSLEEP_FIQ_START + 64) ++#define INT_PMSLEEP_DUMMY_65 (PMSLEEP_FIQ_START + 65) ++#define INT_PMSLEEP_DUMMY_66 (PMSLEEP_FIQ_START + 66) ++#define INT_PMSLEEP_DUMMY_67 (PMSLEEP_FIQ_START + 67) ++#define INT_PMSLEEP_SPI_WPZ (PMSLEEP_FIQ_START + 68) ++#define INT_PMSLEEP_SPI_HLD (PMSLEEP_FIQ_START + 69) ++#define INT_PMSLEEP_DUMMY_70 (PMSLEEP_FIQ_START + 70) ++#define INT_PMSLEEP_SD_CDZ (PMSLEEP_FIQ_START + 71) ++#define INT_PMSLEEP_DUMMY_72 (PMSLEEP_FIQ_START + 72) ++#define INT_PMSLEEP_DUMMY_73 (PMSLEEP_FIQ_START + 73) ++#define INT_PMSLEEP_LED0 (PMSLEEP_FIQ_START + 74) ++#define INT_PMSLEEP_LED1 (PMSLEEP_FIQ_START + 75) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 76) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_DUMMY_00 (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_SAR_GPIO (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_DUMMY_07 (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity2m/mcm_id.h b/drivers/sstar/include/infinity2m/mcm_id.h +new file mode 100644 +index 000000000000..91d265366640 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/mcm_id.h +@@ -0,0 +1,49 @@ ++/* ++* mcm_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_MCU51 0 ++#define MCM_ID_URDMA 1 ++#define MCM_ID_BDMA 2 ++#define MCM_ID_VHE 3 ++#define MCM_ID_MFE 4 ++#define MCM_ID_JPE 5 ++#define MCM_ID_BACH 6 ++#define MCM_ID_AESDMA 7 ++#define MCM_ID_UHC 8 ++#define MCM_ID_EMAC 9 ++#define MCM_ID_CMDQ 10 ++#define MCM_ID_ISP_DNR 11 ++#define MCM_ID_ISP_DMA 12 ++#define MCM_ID_GOP 13 ++#define MCM_ID_SC_DNR 14 ++#define MCM_ID_SC_DNR_SAD 15 ++#define MCM_ID_SC_CROP 16 ++#define MCM_ID_SC1_FRM 17 ++#define MCM_ID_SC1_SNP 18 ++#define MCM_ID_SC1_DBG 19 ++#define MCM_ID_SC2_FRM 20 ++#define MCM_ID_SC3_FRM 21 ++#define MCM_ID_FCIE 22 ++#define MCM_ID_SDIO 23 ++#define MCM_ID_SC1_SNPI 24 ++#define MCM_ID_SC2_SNPI 25 ++#define MCM_ID_ALL 99 ++ ++#endif +diff --git a/drivers/sstar/include/infinity2m/mdrv_miu.h b/drivers/sstar/include/infinity2m/mdrv_miu.h +new file mode 100755 +index 000000000000..10a83888ae74 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/mdrv_miu.h +@@ -0,0 +1,277 @@ ++/* ++* mdrv_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_MIU_H__ ++#define __MDRV_MIU_H__ ++ ++#ifdef CONFIG_64BIT ++ typedef unsigned long phy_addr; // 4 bytes ++#else ++ typedef unsigned long long phy_addr; // 8 bytes ++#endif ++ ++#define MMU_ADDR_TO_REGION(addr) ((addr >> 26) & 0x1F) ++#define MMU_ADDR_TO_ENTRY(addr) ((addr >> 17) & 0x1FF) ++#define MMU_PAGE_SIZE (0x20000) //128KB ++ ++//------------------------------------------------------------------------------------------------- ++// Enumeration Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ // group 0 ++ MIU_CLIENT_NONE, //none can access ++ MIU_CLIENT_MIIC0_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_DUMMY_G0C3, ++ MIU_CLIENT_JPE_R, ++ MIU_CLIENT_JPE_W, ++ MIU_CLIENT_BACH_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_DUMMY_G08, ++ MIU_CLIENT_DUMMY_G09, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ MIU_CLIENT_DUMMY_G0CE, ++ MIU_CLIENT_DUMMY_G0CF, ++ // group 1 ++ MIU_CLIENT_CMDQ0_R, ++ MIU_CLIENT_SATA_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_EMAC1_RW, ++ MIU_CLIENT_DUMMY_G1C4, ++ MIU_CLIENT_DUMMY_G1C5, ++ MIU_CLIENT_DUMMY_G1C6, ++ MIU_CLIENT_USB20_1_RW, ++ MIU_CLIENT_USB20_2_RW, ++ MIU_CLIENT_USB20_3_RW, ++ MIU_CLIENT_GE_RW, ++ MIU_CLIENT_DUMMY_G1CB, ++ MIU_CLIENT_DUMMY_G1CC, ++ MIU_CLIENT_DUMMY_G1CD, ++ MIU_CLIENT_DUMMY_G1CE, ++ MIU_CLIENT_SDIO30_RW, ++ // group 2 ++ MIU_CLIENT_DIP0_R, ++ MIU_CLIENT_DIP0_W, ++ MIU_CLIENT_GOP0_R, ++ MIU_CLIENT_GOP1_R, ++ MIU_CLIENT_MOP_ROT0_Y_R, ++ MIU_CLIENT_MOP_ROT0_C_R, ++ MIU_CLIENT_MOP_ROT1_Y_R, ++ MIU_CLIENT_MOP_ROT1_C_R, ++ MIU_CLIENT_MOP_S_Y_R, ++ MIU_CLIENT_MOP_S_C_R, ++ MIU_CLIENT_MOP_G_Y_R, ++ MIU_CLIENT_MOP_G_C_R, ++ MIU_CLIENT_DUMMY_G2CC, ++ MIU_CLIENT_DUMMY_G2CD, ++ MIU_CLIENT_WAVE511_RW, ++ MIU_CLIENT_DIAMOND_RW, ++ // group 3 ++ MIU_CLIENT_DUMMY_G3C0, ++ MIU_CLIENT_DUMMY_G3C1, ++ MIU_CLIENT_DUMMY_G3C2, ++ MIU_CLIENT_DUMMY_G3C3, ++ MIU_CLIENT_DUMMY_G3C4, ++ MIU_CLIENT_DUMMY_G3C5, ++ MIU_CLIENT_DUMMY_G3C6, ++ MIU_CLIENT_DUMMY_G3C7, ++ MIU_CLIENT_DUMMY_G3C8, ++ MIU_CLIENT_DUMMY_G3C9, ++ MIU_CLIENT_DUMMY_G3CA, ++ MIU_CLIENT_DUMMY_G3CB, ++ MIU_CLIENT_DUMMY_G3CC, ++ MIU_CLIENT_DUMMY_G3CD, ++ MIU_CLIENT_DUMMY_G3CE, ++ MIU_CLIENT_DUMMY_G3CF, ++ // group 4 ++ MIU_CLIENT_DUMMY_G4C0, ++ MIU_CLIENT_DUMMY_G4C1, ++ MIU_CLIENT_DUMMY_G4C2, ++ MIU_CLIENT_DUMMY_G4C3, ++ MIU_CLIENT_DUMMY_G4C4, ++ MIU_CLIENT_DUMMY_G4C5, ++ MIU_CLIENT_DUMMY_G4C6, ++ MIU_CLIENT_DUMMY_G4C7, ++ MIU_CLIENT_DUMMY_G4C8, ++ MIU_CLIENT_DUMMY_G4C9, ++ MIU_CLIENT_DUMMY_G4CA, ++ MIU_CLIENT_DUMMY_G4CB, ++ MIU_CLIENT_DUMMY_G4CC, ++ MIU_CLIENT_DUMMY_G4CD, ++ MIU_CLIENT_DUMMY_G4CE, ++ MIU_CLIENT_DUMMY_G4CF, ++ // group 5 ++ MIU_CLIENT_DUMMY_G5C0, ++ MIU_CLIENT_DUMMY_G5C1, ++ MIU_CLIENT_DUMMY_G5C2, ++ MIU_CLIENT_DUMMY_G5C3, ++ MIU_CLIENT_DUMMY_G5C4, ++ MIU_CLIENT_DUMMY_G5C5, ++ MIU_CLIENT_DUMMY_G5C6, ++ MIU_CLIENT_DUMMY_G5C7, ++ MIU_CLIENT_DUMMY_G5C8, ++ MIU_CLIENT_DUMMY_G5C9, ++ MIU_CLIENT_DUMMY_G5CA, ++ MIU_CLIENT_DUMMY_G5CB, ++ MIU_CLIENT_DUMMY_G5CC, ++ MIU_CLIENT_DUMMY_G5CD, ++ MIU_CLIENT_DUMMY_G5CE, ++ MIU_CLIENT_DUMMY_G5CF, ++ // group 6 ++ MIU_CLIENT_DUMMY_G6C0, ++ MIU_CLIENT_DUMMY_G6C1, ++ MIU_CLIENT_DUMMY_G6C2, ++ MIU_CLIENT_DUMMY_G6C3, ++ MIU_CLIENT_DUMMY_G6C4, ++ MIU_CLIENT_DUMMY_G6C5, ++ MIU_CLIENT_DUMMY_G6C6, ++ MIU_CLIENT_DUMMY_G6C7, ++ MIU_CLIENT_DUMMY_G6C8, ++ MIU_CLIENT_DUMMY_G6C9, ++ MIU_CLIENT_DUMMY_G6CA, ++ MIU_CLIENT_DUMMY_G6CB, ++ MIU_CLIENT_DUMMY_G6CC, ++ MIU_CLIENT_DUMMY_G6CD, ++ MIU_CLIENT_DUMMY_G6CE, ++ MIU_CLIENT_DUMMY_G6CF, ++ // group 7 ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_DUMMY_G7C1, ++ MIU_CLIENT_DUMMY_G7C2, ++ MIU_CLIENT_DUMMY_G7C3, ++ MIU_CLIENT_DUMMY_G7C4, ++ MIU_CLIENT_DUMMY_G7C5, ++ MIU_CLIENT_DUMMY_G7C6, ++ MIU_CLIENT_DUMMY_G7C7, ++ MIU_CLIENT_DUMMY_G7C8, ++ MIU_CLIENT_DUMMY_G7C9, ++ MIU_CLIENT_DUMMY_G7CA, ++ MIU_CLIENT_DUMMY_G7CB, ++ MIU_CLIENT_DUMMY_G7CC, ++ MIU_CLIENT_DUMMY_G7CD, ++ MIU_CLIENT_DUMMY_G7CE, ++ MIU_CLIENT_DUMMY_G7CF, ++} eMIUClientID; ++ ++typedef enum ++{ ++ E_MIU_0 = 0, ++ E_MIU_1, ++ E_MIU_2, ++ E_MIU_3, ++ E_MIU_NUM, ++} MIU_ID; ++ ++typedef enum ++{ ++ E_PROTECT_0 = 0, ++ E_PROTECT_1, ++ E_PROTECT_2, ++ E_PROTECT_3, ++ E_PROTECT_4, ++ E_SLIT_0 = 16, ++ E_MIU_PROTECT_NUM, ++} PROTECT_ID; ++ ++#ifdef CONFIG_MIU_HW_MMU ++typedef enum ++{ ++ E_MMU_STATUS_NORMAL = 0, ++ E_MMU_STATUS_RW_COLLISION = 0x1, ++ E_MMU_STATUS_R_INVALID = 0x2, ++ E_MMU_STATUS_W_INVALID = 0x4, ++ E_MMU_STATUS_NUM, ++} MMU_STATUS; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Structure Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ unsigned char bHit; ++ unsigned char u8Group; ++ unsigned char u8ClientID; ++ unsigned char u8Block; ++ unsigned int uAddress; ++} MIU_PortectInfo; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++#define CONFIG_MIU_HW_MMU ++#ifdef CONFIG_MIU_HW_MMU ++#define CONFIG_MMU_INTERRUPT_ENABLE ++ ++// MDrv_MMU_Callback parameter: [IRQ Status] [Phyical Address Entry] [Client ID] [Is Write Command] ++typedef void (*MDrv_MMU_Callback)(unsigned int, unsigned short, unsigned short, unsigned char); ++#endif ++ ++unsigned char MDrv_MIU_Init(void); ++unsigned short* MDrv_MIU_GetDefaultClientID_KernelProtect(void); ++unsigned short* MDrv_MIU_GetClientID_KernelProtect(unsigned char u8MiuSel); ++ ++unsigned char MDrv_MIU_Protect( unsigned char u8Blockx, ++ unsigned short *pu8ProtectId, ++ phy_addr u64BusStart, ++ phy_addr u64BusEnd, ++ unsigned char bSetFlag); ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++unsigned char MDrv_MIU_GetProtectInfo(unsigned char u8MiuDev, MIU_PortectInfo *pInfo); ++#endif ++unsigned char MDrv_MIU_Slits(unsigned char u8Blockx, phy_addr u64SlitsStart, phy_addr u65SlitsEnd, unsigned char bSetFlag); ++unsigned char MDrv_MIU_Get_IDEnables_Value(unsigned char u8MiuDev, unsigned char u8Blockx, unsigned char u8ClientIndex); ++unsigned int MDrv_MIU_ProtectDramSize(void); ++int MDrv_MIU_ClientIdToName(unsigned short clientId, char *clientName); ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo); ++ ++#ifdef CONFIG_MIU_HW_MMU ++int MDrv_MMU_SetRegion(unsigned short u16Region, unsigned short u16ReplaceRegion); ++int MDrv_MMU_SetPageSize(unsigned char u8PgSz256En); ++int MDrv_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry); ++unsigned short MDrv_MMU_MapQuery(unsigned short u16PhyAddrEntry); ++int MDrv_MMU_UnMap(unsigned short u16PhyAddrEntry); ++int MDrv_MMU_AddClientId(unsigned short u16ClientId); ++int MDrv_MMU_RemoveClientId(unsigned short u16ClientId); ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++void MDrv_MMU_CallbackFunc(MDrv_MMU_Callback pFuncPtr); ++#endif ++int MDrv_MMU_Enable(unsigned char u8Enable); ++int MDrv_MMU_Reset(void); ++unsigned int MDrv_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsWriteCmd); ++#endif ++ ++#endif // __MDRV_MIU_H__ +diff --git a/drivers/sstar/include/infinity2m/mhal_miu.h b/drivers/sstar/include/infinity2m/mhal_miu.h +new file mode 100755 +index 000000000000..0db8826fe69c +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/mhal_miu.h +@@ -0,0 +1,121 @@ ++/* ++* mhal_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_MIU_H_ ++#define _MHAL_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_MAX_DEVICE (2) ++#define MIU_MAX_GROUP (8) ++#define MIU_MAX_GP_CLIENT (16) ++#define MIU_MAX_TBL_CLIENT (MIU_MAX_GROUP*MIU_MAX_GP_CLIENT) ++ ++#define MIU_PAGE_SHIFT (13) // Unit for MIU protect (8KB) ++#define MIU_PROTECT_ADDRESS_UNIT (0x20UL) // Unit for MIU hitted address ++#define MIU_MAX_PROTECT_BLOCK (5) ++#define MIU_MAX_PROTECT_ID (16) ++ ++#define IDNUM_KERNELPROTECT (16) ++ ++// MMU ++#define MMU_MAX_CLIENT_NUM (8) ++#define MMU_INVALID_ENTRY_VAL (0x1FF) ++ ++#ifndef BIT0 ++#define BIT0 0x0001UL ++#define BIT1 0x0002UL ++#define BIT2 0x0004UL ++#define BIT3 0x0008UL ++#define BIT4 0x0010UL ++#define BIT5 0x0020UL ++#define BIT6 0x0040UL ++#define BIT7 0x0080UL ++#define BIT8 0x0100UL ++#define BIT9 0x0200UL ++#define BIT10 0x0400UL ++#define BIT11 0x0800UL ++#define BIT12 0x1000UL ++#define BIT13 0x2000UL ++#define BIT14 0x4000UL ++#define BIT15 0x8000UL ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MIU_BLOCK_0 = 0, ++ E_MIU_BLOCK_1, ++ E_MIU_BLOCK_2, ++ E_MIU_BLOCK_3, ++ E_MIU_BLOCK_4, ++ E_MIU_BLOCK_NUM, ++} MIU_BLOCK_ID; ++ ++typedef enum ++{ ++ E_HAL_MMU_STATUS_NORMAL = 0, ++ E_HAL_MMU_STATUS_RW_COLLISION = 0x1, ++ E_HAL_MMU_STATUS_R_INVALID = 0x2, ++ E_HAL_MMU_STATUS_W_INVALID = 0x4, ++ E_HAL_MMU_STATUS_NUM, ++} HAL_MMU_STATUS; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo_Hal; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuDev, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex); ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void); ++unsigned int HAL_MIU_ProtectDramSize(void); ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName); ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo); ++ ++// MMU HAL Function ++int __HAL_MMU_GetChipId(void); ++int HAL_MMU_SetRegion(unsigned short u16Region); ++int HAL_MMU_SetRegionReplaceable(unsigned short u16Region, unsigned short u16ReplaceRegion); ++int HAL_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry); ++unsigned short HAL_MMU_MapQuery(unsigned short u16PhyAddrEntry); ++int HAL_MMU_UnMap(unsigned short u16PhyAddrEntry); ++int HAL_MMU_AddClientId(unsigned short u16ClientId); ++int HAL_MMU_RemoveClientId(unsigned short u16ClientId); ++int HAL_MMU_Enable(unsigned char u8Enable); ++int HAL_MMU_Reset(void); ++unsigned int HAL_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsReadCmd); ++ ++#endif // _MHAL_MIU_H_ +diff --git a/drivers/sstar/include/infinity2m/padmux.h b/drivers/sstar/include/infinity2m/padmux.h +new file mode 100644 +index 000000000000..88be9e5a8419 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/padmux.h +@@ -0,0 +1,139 @@ ++#ifndef __PADMUX_H__ ++#define __PADMUX_H__ ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++ ++#define PINMUX_FOR_EJ_MODE_1 0x01 ++#define PINMUX_FOR_EJ_MODE_2 0x02 ++#define PINMUX_FOR_EJ_MODE_3 0x03 ++#define PINMUX_FOR_TX_MIPI_MODE_1 0x04 ++#define PINMUX_FOR_TX_MIPI_MODE_2 0x05 ++#define PINMUX_FOR_TEST_IN_MODE_1 0x06 ++#define PINMUX_FOR_TEST_IN_MODE_2 0x07 ++#define PINMUX_FOR_TEST_IN_MODE_3 0x08 ++#define PINMUX_FOR_TEST_OUT_MODE_1 0x09 ++#define PINMUX_FOR_TEST_OUT_MODE_2 0x0a ++#define PINMUX_FOR_TEST_OUT_MODE_3 0x0b ++#define PINMUX_FOR_I2C0_MODE_1 0x0c ++#define PINMUX_FOR_I2C0_MODE_2 0x0d ++#define PINMUX_FOR_I2C0_MODE_3 0x0e ++#define PINMUX_FOR_I2C0_MODE_4 0x0f ++#define PINMUX_FOR_I2C1_MODE_1 0x10 ++#define PINMUX_FOR_I2C1_MODE_2 0x11 ++#define PINMUX_FOR_I2C1_MODE_3 0x12 ++#define PINMUX_FOR_I2C1_MODE_4 0x13 ++#define PINMUX_FOR_I2C1_MODE_5 0x14 ++#define PINMUX_FOR_PM_SPICZ2_MODE_1 0x15 ++#define PINMUX_FOR_PM_SPICZ2_MODE_2 0x16 ++#define PINMUX_FOR_SPI0_MODE_1 0x17 ++#define PINMUX_FOR_SPI0_MODE_2 0x18 ++#define PINMUX_FOR_SPI0_MODE_3 0x19 ++#define PINMUX_FOR_SPI0_MODE_4 0x1a ++#define PINMUX_FOR_SPI0_MODE_5 0x1b ++#define PINMUX_FOR_SPI0_MODE_6 0x1c ++#define PINMUX_FOR_FUART_MODE_1 0x1d ++#define PINMUX_FOR_FUART_MODE_2 0x1e ++#define PINMUX_FOR_FUART_MODE_3 0x1f ++#define PINMUX_FOR_FUART_MODE_4 0x20 ++#define PINMUX_FOR_FUART_MODE_5 0x21 ++#define PINMUX_FOR_FUART_MODE_6 0x22 ++#define PINMUX_FOR_FUART_MODE_7 0x23 ++#define PINMUX_FOR_UART0_MODE_1 0x24 ++#define PINMUX_FOR_UART0_MODE_2 0x25 ++#define PINMUX_FOR_UART0_MODE_3 0x26 ++#define PINMUX_FOR_UART0_MODE_4 0x27 ++#define PINMUX_FOR_UART1_MODE_1 0x28 ++#define PINMUX_FOR_UART1_MODE_2 0x29 ++#define PINMUX_FOR_UART1_MODE_3 0x2a ++#define PINMUX_FOR_UART1_MODE_4 0x2b ++#define PINMUX_FOR_UART2_MODE_1 0x2c ++#define PINMUX_FOR_UART2_MODE_2 0x2d ++#define PINMUX_FOR_UART2_MODE_3 0x2e ++#define PINMUX_FOR_UART2_MODE_4 0x2f ++#define PINMUX_FOR_SDIO_MODE_1 0x30 ++#define PINMUX_FOR_SDIO_MODE_2 0x31 ++#define PINMUX_FOR_PWM0_MODE_1 0x32 ++#define PINMUX_FOR_PWM0_MODE_2 0x33 ++#define PINMUX_FOR_PWM0_MODE_3 0x34 ++#define PINMUX_FOR_PWM0_MODE_4 0x35 ++#define PINMUX_FOR_PWM0_MODE_5 0x36 ++#define PINMUX_FOR_PWM1_MODE_1 0x37 ++#define PINMUX_FOR_PWM1_MODE_2 0x38 ++#define PINMUX_FOR_PWM1_MODE_3 0x39 ++#define PINMUX_FOR_PWM1_MODE_4 0x3a ++#define PINMUX_FOR_PWM1_MODE_5 0x3b ++#define PINMUX_FOR_PWM2_MODE_1 0x3c ++#define PINMUX_FOR_PWM2_MODE_2 0x3d ++#define PINMUX_FOR_PWM2_MODE_3 0x3e ++#define PINMUX_FOR_PWM2_MODE_4 0x3f ++#define PINMUX_FOR_PWM2_MODE_5 0x40 ++#define PINMUX_FOR_PWM2_MODE_6 0x41 ++#define PINMUX_FOR_PWM3_MODE_1 0x42 ++#define PINMUX_FOR_PWM3_MODE_2 0x43 ++#define PINMUX_FOR_PWM3_MODE_3 0x44 ++#define PINMUX_FOR_PWM3_MODE_4 0x45 ++#define PINMUX_FOR_PWM3_MODE_5 0x46 ++#define PINMUX_FOR_ETH0_MODE 0x47 ++#define PINMUX_FOR_ETH1_MODE_1 0x48 ++#define PINMUX_FOR_ETH1_MODE_2 0x49 ++#define PINMUX_FOR_ETH1_MODE_3 0x4a ++#define PINMUX_FOR_ETH1_MODE_4 0x4b ++#define PINMUX_FOR_ETH1_MODE_5 0x4c ++#define PINMUX_FOR_ETH1_MODE_6 0x4d ++#define PINMUX_FOR_ETH1_MODE_7 0x4e ++#define PINMUX_FOR_ETH1_MODE_8 0x4f ++#define PINMUX_FOR_ETH1_MODE_9 0x50 ++#define PINMUX_FOR_DMIC_MODE_1 0x51 ++#define PINMUX_FOR_DMIC_MODE_2 0x52 ++#define PINMUX_FOR_DMIC_MODE_3 0x53 ++#define PINMUX_FOR_DMIC_MODE_4 0x54 ++#define PINMUX_FOR_I2S_MODE_1 0x55 ++#define PINMUX_FOR_I2S_MODE_2 0x56 ++#define PINMUX_FOR_I2S_MODE_3 0x57 ++#define PINMUX_FOR_TTL_MODE_1 0x58 ++#define PINMUX_FOR_TTL_MODE_2 0x59 ++#define PINMUX_FOR_TTL_MODE_3 0x5a ++#define PINMUX_FOR_TTL_MODE_4 0x5b ++#define PINMUX_FOR_TTL_MODE_5 0x5c ++#define PINMUX_FOR_TTL_MODE_6 0x5d ++#define PINMUX_FOR_TTL_MODE_7 0x5e ++#define PINMUX_FOR_TTL_MODE_8 0x5f ++#define PINMUX_FOR_TTL_MODE_9 0x60 ++#define PINMUX_FOR_TTL_MODE_10 0x61 ++#define PINMUX_FOR_TTL_MODE_11 0x62 ++#define PINMUX_FOR_TTL_MODE_12 0x63 ++#define PINMUX_FOR_TTL_MODE_13 0x64 ++#define PINMUX_FOR_IDAC_MODE 0x65 ++#define PINMUX_FOR_SATA_LED_MODE 0x66 ++#define PINMUX_FOR_BT1120_MODE_1 0x67 ++#define PINMUX_FOR_BT1120_MODE_2 0x68 ++ ++#define PINMUX_FOR_PM_SPI_MODE 0x69 ++#define PINMUX_FOR_PM_SPIWPN_MODE 0x6a ++#define PINMUX_FOR_PM_SPIHOLDN_MODE 0x6b ++#define PINMUX_FOR_PM_SPICSZ1_MODE 0x6c ++#define PINMUX_FOR_PM_SPICSZ2_MODE 0x6d ++#define PINMUX_FOR_PM_PWM0_MODE 0x6e ++#define PINMUX_FOR_PM_PWM1_MODE 0x6f ++#define PINMUX_FOR_PM_PWM2_MODE 0x70 ++#define PINMUX_FOR_PM_PWM3_MODE 0x71 ++#define PINMUX_FOR_PM_UART1_MODE 0x72 ++#define PINMUX_FOR_PM_VID_MODE_1 0x73 ++#define PINMUX_FOR_PM_VID_MODE_2 0x74 ++#define PINMUX_FOR_PM_VID_MODE_3 0x75 ++#define PINMUX_FOR_PM_SD_CDZ_MODE 0x76 ++#define PINMUX_FOR_PM_LED_MODE_1 0x77 ++#define PINMUX_FOR_PM_LED_MODE_2 0x78 ++#define PINMUX_FOR_PM_LED_MODE_3 0x79 ++#define PINMUX_FOR_PM_IRIN_MODE 0x7a ++ ++// add manually for misc pads here ++#define PINMUX_FOR_DAC_MODE 0x7b ++#define PINMUX_FOR_SAR_MODE 0x7c ++#define PINMUX_FOR_ETH_MODE 0x7d ++#define PINMUX_FOR_USB_MODE 0x7e ++ ++ ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++#endif // __PADMUX_H__ +diff --git a/drivers/sstar/include/infinity2m/regMIU.h b/drivers/sstar/include/infinity2m/regMIU.h +new file mode 100755 +index 000000000000..6f7837ba9d8e +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/regMIU.h +@@ -0,0 +1,182 @@ ++/* ++* regMIU.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_MIU_H_ ++#define _REG_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) ++#define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) ++ ++ ++#define MIU_REG_BASE (0x1200UL) ++#define MIU1_REG_BASE (0x0D00UL) ++#define MIU2_REG_BASE (0x62000UL) ++#define PM_REG_BASE (0x1E00UL) ++#define MIU_ATOP_BASE (0x1000UL) ++#define MIU1_ATOP_BASE (0x0B00UL) ++#define MIU2_ATOP_BASE (0x62100UL) ++#define CHIP_TOP_BASE (0x1E00UL) ++#define MIU_ARB_REG_BASE (0x1100UL) ++#define MIU1_ARB_REG_BASE (0x0C00UL) ++#define MIU2_ARB_REG_BASE (0x62300UL) ++#define MIU_MMU_REG_BASE (0x1300UL) ++ ++#define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3UL) ++#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++#define MIU_PROTECT_DDR_32MB (0x50UL) ++#define MIU_PROTECT_DDR_64MB (0x60UL) ++#define MIU_PROTECT_DDR_128MB (0x70UL) ++#define MIU_PROTECT_DDR_256MB (0x80UL) ++#define MIU_PROTECT_DDR_512MB (0x90UL) ++#define MIU_PROTECT_DDR_1024MB (0xA0UL) ++#define MIU_PROTECT_DDR_2048MB (0xB0UL) ++ ++#define MIU_PROTECT0_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT1_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT2_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT3_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT4_EN (MIU_ARB_REG_BASE+0xDEUL) ++#define MIU_PROTECT_ID0 (MIU_REG_BASE+0x2EUL) ++#define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20UL) ++#define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22UL) ++#define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24UL) ++#define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26UL) ++#define MIU_PROTECT4_ID_ENABLE (MIU_ARB_REG_BASE+0xDC) ++#define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT1_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT2_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT3_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT4_MSB (MIU_REG_BASE+0xB2UL) ++#define MIU_PROTECT0_START (MIU_REG_BASE+0xC0UL) ++#define MIU_PROTECT0_END (MIU_REG_BASE+0xC2UL) ++#define MIU_PROTECT1_START (MIU_REG_BASE+0xC4UL) ++#define MIU_PROTECT1_END (MIU_REG_BASE+0xC6UL) ++#define MIU_PROTECT2_START (MIU_REG_BASE+0xC8UL) ++#define MIU_PROTECT2_END (MIU_REG_BASE+0xCAUL) ++#define MIU_PROTECT3_START (MIU_REG_BASE+0xCCUL) ++#define MIU_PROTECT3_END (MIU_REG_BASE+0xCEUL) ++#define MIU_PROTECT4_START (MIU_REG_BASE+0x72UL) ++#define MIU_PROTECT4_END (MIU_REG_BASE+0x92UL) ++#define REG_MIU_PROTECT_LOADDR (0x6DUL << 1) //0xDE ++#define REG_MIU_PROTECT_HIADDR (0x6EUL << 1) //0xDE ++#define REG_MIU_PROTECT_STATUS (0x6FUL << 1) //0xDE ++ ++// MIU selection registers ++#define REG_MIU_SEL0 (MIU_REG_BASE+0xf0UL) //0x12F0 ++#define REG_MIU_SEL1 (MIU_REG_BASE+0xf2UL) //0x12F1 ++#define REG_MIU_SEL2 (MIU_REG_BASE+0xf4UL) //0x12F2 ++#define REG_MIU_SEL3 (MIU_REG_BASE+0xf6UL) //0x12F3 ++#define REG_MIU_SELX(x) (0xF0UL+x*2) ++ ++// MIU1 ++#define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3UL) ++#define MIU1_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++ ++#define MIU1_PROTECT0_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT1_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT2_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT3_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT4_EN (MIU1_ARB_REG_BASE+0xDEUL) ++#define MIU1_PROTECT_ID0 (MIU1_REG_BASE+0x2EUL) ++#define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20UL) ++#define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22UL) ++#define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24UL) ++#define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26UL) ++#define MIU1_PROTECT4_ID_ENABLE (MIU1_ARB_REG_BASE+0xDC) ++#define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT1_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT2_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT3_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT4_MSB (MIU1_REG_BASE+0xB2UL) ++#define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0UL) ++#define MIU1_PROTECT0_END (MIU1_REG_BASE+0xC2UL) ++#define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4UL) ++#define MIU1_PROTECT1_END (MIU1_REG_BASE+0xC6UL) ++#define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8UL) ++#define MIU1_PROTECT2_END (MIU1_REG_BASE+0xCAUL) ++#define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCCUL) ++#define MIU1_PROTECT3_END (MIU1_REG_BASE+0xCEUL) ++#define MIU1_PROTECT4_START (MIU1_REG_BASE+0x72UL) ++#define MIU1_PROTECT4_END (MIU1_REG_BASE+0x92UL) ++ ++#define REG_MIU_I64_MODE (BIT7) ++#define REG_MIU_INIT_DONE (BIT15) ++ ++// Protection Status ++#define REG_MIU_PROTECT_LOG_CLR (BIT0) ++#define REG_MIU_PROTECT_IRQ_MASK (BIT1) ++#define REG_MIU_PROTECT_HIT_FALG (BIT4) ++#define REG_MIU_PROTECT_HIT_ID 14:8 ++#define REG_MIU_PROTECT_HIT_NO 7:5 ++ ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET (MIU_REG_BASE+0xD8UL) ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_BIT (BIT11) ++ ++// PM Top Resiter ++#define REG_CHIP_INFORM_SHADOW (PM_REG_BASE + 0xCEUL) ++ ++// MMU Control Register ++#define REG_MMU_CTRL (MIU_MMU_REG_BASE+0xA0UL) ++#define REG_MMU_RW_ENTRY (MIU_MMU_REG_BASE+0xA2UL) ++#define REG_MMU_W_DATA (MIU_MMU_REG_BASE+0xA4UL) ++#define REG_MMU_R_DATA (MIU_MMU_REG_BASE+0xA6UL) ++#define REG_MMU_CLIENT_ID_0_1 (MIU_MMU_REG_BASE+0xA8UL) ++#define REG_MMU_CLIENT_ID_2_3 (MIU_MMU_REG_BASE+0xAAUL) ++#define REG_MMU_CLIENT_ID_4_5 (MIU_MMU_REG_BASE+0xACUL) ++#define REG_MMU_CLIENT_ID_6_7 (MIU_MMU_REG_BASE+0xAEUL) ++#define REG_MMU_CLIENT_ID_SEL (MIU_MMU_REG_BASE+0xB0UL) ++#define REG_MMU_IRQ_CTRL (MIU_MMU_REG_BASE+0xB2UL) ++#define REG_MMU_COLLISION_ENTRY (MIU_MMU_REG_BASE+0xB4UL) ++#define REG_MMU_ACCESS (MIU_MMU_REG_BASE+0xB6UL) ++// Chip2 new function Register ++#define REG_MMU_REPLACE_MSB (MIU_MMU_REG_BASE+0xA8UL) ++ ++// MMU Control ++#define REG_MMU_CTRL_ENABLE (BIT0) ++#define REG_MMU_CTRL_RESET (BIT4) ++#define REG_MMU_CTRL_RESET_INIT_VAL (BIT5) ++#define REG_MMU_CTRL_INIT_DONE (BIT7) ++#define REG_MMU_CTRL_REGION_MASK 12:8 ++ ++// Read/Write Entry ++#define REG_MMU_RW_ENTRY_MODE (BIT15) ++ ++// IRQ Control ++#define REG_MMU_IRQ_RW_CLR (BIT0) ++#define REG_MMU_IRQ_RW_MASK (BIT1) ++#define REG_MMU_IRQ_RD_CLR (BIT2) ++#define REG_MMU_IRQ_RD_MASK (BIT3) ++#define REG_MMU_IRQ_WR_CLR (BIT4) ++#define REG_MMU_IRQ_WR_MASK (BIT5) ++#define REG_MMU_IRQ_RW_FLAG (BIT6) ++#define REG_MMU_IRQ_RD_FLAG (BIT7) ++#define REG_MMU_IRQ_WR_FLAG (BIT8) ++#define REG_MMU_IRQ_INVALID_RW (BIT9) ++#define REG_MMU_IRQ_INVALID_ID_MASK 15:10 ++ ++// Chip2 new function ++#define REG_MMU_REPLACE_MSB_MASK 4:0 ++ ++#endif // _REG_MIU_H_ +diff --git a/drivers/sstar/include/infinity2m/reg_clks.h b/drivers/sstar/include/infinity2m/reg_clks.h +new file mode 100644 +index 000000000000..9caff9089d0e +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/reg_clks.h +@@ -0,0 +1,427 @@ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I2m/iNfinity2m_Clock_Table_20190226_SW.xls */ ++/* REG FILENAME: I2m/iNfinity2m_reg_CLKGEN.xls, I2m/iNfinity2m_reg_pm_sleep.xls, I2m/iNfinity2m_reg_block.xls, I2m/iNfinity2m_reg_chiptop.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++#define REG_CHIPTOP_BASE 0x1F203C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CHIPTOP_DUMMY_0_BASE (REG_CHIPTOP_BASE+0x20*4) ++#define REG_CHIPTOP_DUMMY_0_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_1_BASE (REG_CHIPTOP_BASE+0x21*4) ++#define REG_CHIPTOP_DUMMY_1_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_2_BASE (REG_CHIPTOP_BASE+0x22*4) ++#define REG_CHIPTOP_DUMMY_2_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_3_BASE (REG_CHIPTOP_BASE+0x23*4) ++#define REG_CHIPTOP_DUMMY_3_OFFSET (0) ++ ++#define REG_CHIPTOP_RESERVED_BASE (REG_CHIPTOP_BASE+0x7B*4) ++#define REG_CHIPTOP_RESERVED_OFFSET (0) ++ ++#define REG_CKG_DAC_BASE (REG_SC_GP_CTRL_BASE+0x36*4) ++#define REG_CKG_DAC_OFFSET (0) ++ ++#define REG_CKG_EMAC1_RX_BASE (REG_SC_GP_CTRL_BASE+0x33*4) ++#define REG_CKG_EMAC1_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC1_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x33*4) ++#define REG_CKG_EMAC1_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC1_TX_BASE (REG_SC_GP_CTRL_BASE+0x34*4) ++#define REG_CKG_EMAC1_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC1_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x34*4) ++#define REG_CKG_EMAC1_TX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_HDMI_BASE (REG_SC_GP_CTRL_BASE+0x35*4) ++#define REG_CKG_HDMI_OFFSET (0) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_MIPI_TX_DSI_APB_BASE (REG_SC_GP_CTRL_BASE+0x37*4) ++#define REG_CKG_MIPI_TX_DSI_APB_OFFSET (0) ++ ++#define REG_CKG_SD_BASE (REG_SC_GP_CTRL_BASE+0x25*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++#define REG_SRAM_SD_EN_BASE (REG_SC_GP_CTRL_BASE+0x12*4) ++#define REG_SRAM_SD_EN_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_TMP_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_TMP_OFFSET (0) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PWM_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SPI_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_DEC_GP_BASE (REG_CKG_BASE+0x57*4) ++#define REG_CKG_BIST_DEC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DEC_ACLK_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_DEC_ACLK_OFFSET (8) ++ ++#define REG_CKG_DEC_BCLK_BASE (REG_CKG_BASE+0x56*4) ++#define REG_CKG_DEC_BCLK_OFFSET (0) ++ ++#define REG_CKG_DEC_CCLK_BASE (REG_CKG_BASE+0x56*4) ++#define REG_CKG_DEC_CCLK_OFFSET (8) ++ ++#define REG_CKG_DEC_PCLK_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_DEC_PCLK_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_DISP_216_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_DISP_216_OFFSET (8) ++ ++#define REG_CKG_DISP_432_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_DISP_432_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GE_BASE (REG_CKG_BASE+0x51*4) ++#define REG_CKG_GE_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIPI_TX_DSI_BASE (REG_CKG_BASE+0x6F*4) ++#define REG_CKG_MIPI_TX_DSI_OFFSET (0) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MOP_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_MOP_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SATA_AXI_BASE (REG_CKG_BASE+0x6E*4) ++#define REG_CKG_SATA_AXI_OFFSET (0) ++ ++#define REG_CKG_SATA_PHY_108_BASE (REG_CKG_BASE+0x46*4) ++#define REG_CKG_SATA_PHY_108_OFFSET (0) ++ ++#define REG_CKG_SATA_PHY_432_BASE (REG_CKG_BASE+0x46*4) ++#define REG_CKG_SATA_PHY_432_OFFSET (8) ++ ++#define REG_CKG_SATA_PM_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_SATA_PM_OFFSET (8) ++ ++#define REG_CKG_SC_PIXEL_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_SC_PIXEL_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_TMP_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_TMP_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_UART2_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART2_OFFSET (12) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity2m/registers.h b/drivers/sstar/include/infinity2m/registers.h +new file mode 100755 +index 000000000000..ca7bb9ba4a9e +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/registers.h +@@ -0,0 +1,278 @@ ++/* ++* registers.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++#define REG_ADDR(addr) (*((volatile U16*)(0xFD200000 + (addr << 1)))) ++ ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0xFFFFFFFF ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++#define MIU0_BASE ARM_MIU0_BUS_BASE ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x10000 ++ ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++#ifdef CONFIG_SS_AMP ++#define IPC_MEM_PHYS 0x27000000 ++#define IPC_MEM_VIRT 0xFE000000 ++#define IPC_MEM_OFFSET (MS_IO_OFFSET) ++#define IPC_MEM_SIZE 0x800000 ++#endif ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0600) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3000) ++#define BASE_REG_LANTOP0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3100) ++#define BASE_REG_LANTOP1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3200) ++#define BASE_REG_LANTOP2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3300) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++#define BASE_REG_BDMA0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100200) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100220) ++#define BASE_REG_BDMA2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100240) ++#define BASE_REG_BDMA3_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100260) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_MOVDMA_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100B00) ++#define BASE_REG_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101000) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_MIUPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103100) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++#define BASE_REG_GPI_INT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103D00) ++#define BASE_REG_MPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103000) ++#define BASE_REG_MIUPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103100) ++#define BASE_REG_ARMPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103200) ++#define BASE_REG_DISP_LPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103300) ++#define BASE_REG_AUSDM_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103400) ++#define BASE_REG_HDMI_TX_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x112600) ++#define BASE_REG_DAC_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x112700) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x141F00) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++#define BASE_REG_UTMI1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142500) ++#define BASE_REG_SATA_MAC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x152500) ++#define BASE_REG_SATA_PHY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x152600) ++#define BASE_REG_SATA_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x152700) ++#define BASE_REG_DPHY_DSI_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x152800) ++#define BASE_REG_UTMI2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142900) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I2M_PACKAGE_UNKNOWN =0x00, ++ MS_I2M_PACKAGE_QFN_DDR2_32MB, ++ MS_I2M_PACKAGE_QFN_DDR2_64MB, ++ MS_I2M_PACKAGE_BGA_128MB, ++ MS_I2M_PACKAGE_BGA_256MB, ++ MS_I2M_PACKAGE_QFN_DDR3_128MB, ++ MS_I2M_PACKAGE_EXTENDED=0x30, ++ MS_I2M_PACKAGE_DDR3_1866_128MB =0x30, ++ MS_I2M_PACKAGE_DDR3_1866_256MB, ++ MS_I2M_PACKAGE_FPGA_128MB =0x90, ++} MS_I2M_PACKAGE_TYPE; ++ ++ ++#endif // ___REGS_H +diff --git a/drivers/sstar/include/infinity2m/tsensor.h b/drivers/sstar/include/infinity2m/tsensor.h +new file mode 100755 +index 000000000000..30e40f7d6d1b +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/tsensor.h +@@ -0,0 +1,23 @@ ++/* ++* tsensor.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __CPU_FREQ_H ++#define __CPU_FREQ_H ++ ++int ms_get_temp(void); ++ ++#endif //__CPU_FREQ_H +diff --git a/drivers/sstar/include/infinity2m/voltage_ctrl_demander.h b/drivers/sstar/include/infinity2m/voltage_ctrl_demander.h +new file mode 100755 +index 000000000000..d04460e64eb8 +--- /dev/null ++++ b/drivers/sstar/include/infinity2m/voltage_ctrl_demander.h +@@ -0,0 +1,36 @@ ++/* ++* voltage_ctrl.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __VOLTAGE_CTRL_DEMANDER_H ++#define __VOLTAGE_CTRL_DEMANDER_H ++ ++#define FOREACH_DEMANDER(DEMANDER) \ ++ DEMANDER(VOLTAGE_DEMANDER_CPUFREQ) \ ++ DEMANDER(VOLTAGE_DEMANDER_TEMPERATURE) \ ++ DEMANDER(VOLTAGE_DEMANDER_VENC) \ ++ DEMANDER(VOLTAGE_DEMANDER_MIU) \ ++ DEMANDER(VOLTAGE_DEMANDER_USER) \ ++ DEMANDER(VOLTAGE_DEMANDER_MAX) \ ++ ++#define GENERATE_ENUM(ENUM) ENUM, ++#define GENERATE_STRING(STRING) #STRING, ++ ++typedef enum { ++ FOREACH_DEMANDER(GENERATE_ENUM) ++} VOLTAGE_DEMANDER_E; ++ ++#endif //__VOLTAGE_CTRL_DEMANDER_H +diff --git a/drivers/sstar/include/infinity3/Kconfig b/drivers/sstar/include/infinity3/Kconfig +new file mode 100644 +index 000000000000..f7269f296f47 +--- /dev/null ++++ b/drivers/sstar/include/infinity3/Kconfig +@@ -0,0 +1,20 @@ ++#source "drivers/sstar/isp/Kconfig" ++#source "drivers/sstar/sound/Kconfig" ++source "drivers/sstar/emmc/Kconfig" ++source "drivers/sstar/sdmmc/Kconfig" ++source "drivers/sstar/usb/Kconfig" ++#source "drivers/sstar/fb/Kconfig" ++#source "drivers/sstar/fb1/Kconfig" ++#source "drivers/sstar/fb2/Kconfig" ++#source "drivers/sstar/scl/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/ircut/Kconfig" ++#source "drivers/sstar/vhe/Kconfig" ++#source "drivers/sstar/mfev5/Kconfig" ++source "drivers/sstar/rtc/Kconfig" ++#source "drivers/sstar/jpe/Kconfig" ++source "drivers/sstar/xpm/Kconfig" ++source "drivers/sstar/crypto/Kconfig" ++source "drivers/sstar/cpufreq/Kconfig" ++source "drivers/sstar/notify/Kconfig" ++ +diff --git a/drivers/sstar/include/infinity3/gpio.h b/drivers/sstar/include/infinity3/gpio.h +new file mode 100755 +index 000000000000..9f0c4e737c0a +--- /dev/null ++++ b/drivers/sstar/include/infinity3/gpio.h +@@ -0,0 +1,134 @@ ++/* ++* gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO10 10 ++#define PAD_GPIO11 11 ++#define PAD_GPIO12 12 ++#define PAD_GPIO13 13 ++#define PAD_GPIO14 14 ++#define PAD_GPIO15 15 ++#define PAD_FUART_RX 16 ++#define PAD_FUART_TX 17 ++#define PAD_FUART_CTS 18 ++#define PAD_FUART_RTS 19 ++#define PAD_I2C0_SCL 20 ++#define PAD_I2C0_SDA 21 ++#define PAD_I2C1_SCL 22 ++#define PAD_I2C1_SDA 23 ++#define PAD_SR_IO00 24 ++#define PAD_SR_IO01 25 ++#define PAD_SR_IO02 26 ++#define PAD_SR_IO03 27 ++#define PAD_SR_IO04 28 ++#define PAD_SR_IO05 29 ++#define PAD_SR_IO06 30 ++#define PAD_SR_IO07 31 ++#define PAD_SR_IO08 32 ++#define PAD_SR_IO09 33 ++#define PAD_SR_IO10 34 ++#define PAD_SR_IO11 35 ++#define PAD_SR_IO12 36 ++#define PAD_SR_IO13 37 ++#define PAD_SR_IO14 38 ++#define PAD_SR_IO15 39 ++#define PAD_SR_IO16 40 ++#define PAD_SR_IO17 41 ++#define PAD_NAND_ALE 42 ++#define PAD_NAND_CLE 43 ++#define PAD_NAND_CEZ 44 ++#define PAD_NAND_WEZ 45 ++#define PAD_NAND_WPZ 46 ++#define PAD_NAND_REZ 47 ++#define PAD_NAND_RBZ 48 ++#define PAD_NAND_DA0 49 ++#define PAD_NAND_DA1 50 ++#define PAD_NAND_DA2 51 ++#define PAD_NAND_DA3 52 ++#define PAD_NAND_DA4 53 ++#define PAD_NAND_DA5 54 ++#define PAD_NAND_DA6 55 ++#define PAD_NAND_DA7 56 ++#define PAD_UART0_RX 57 ++#define PAD_UART0_TX 58 ++#define PAD_UART1_RX 59 ++#define PAD_UART1_TX 60 ++#define PAD_SPI0_CZ 61 ++#define PAD_SPI0_CK 62 ++#define PAD_SPI0_DI 63 ++#define PAD_SPI0_DO 64 ++#define PAD_SPI1_CZ 65 ++#define PAD_SPI1_CK 66 ++#define PAD_SPI1_DI 67 ++#define PAD_SPI1_DO 68 ++#define PAD_PWM0 69 ++#define PAD_PWM1 70 ++#define PAD_SD_CLK 71 ++#define PAD_SD_CMD 72 ++#define PAD_SD_D0 73 ++#define PAD_SD_D1 74 ++#define PAD_SD_D2 75 ++#define PAD_SD_D3 76 ++#define PAD_PM_SD_CDZ 77 ++#define PAD_PM_IRIN 78 ++#define PAD_PM_GPIO0 79 ++#define PAD_PM_GPIO1 80 ++#define PAD_PM_GPIO2 81 ++#define PAD_PM_GPIO3 82 ++#define PAD_PM_GPIO4 83 ++#define PAD_PM_GPIO5 84 ++#define PAD_PM_GPIO6 85 ++#define PAD_PM_GPIO7 86 ++#define PAD_PM_GPIO8 87 ++#define PAD_PM_GPIO9 88 ++#define PAD_PM_GPIO10 89 ++#define PAD_PM_SPI_CZ 90 ++#define PAD_PM_SPI_CK 91 ++#define PAD_PM_SPI_DI 92 ++#define PAD_PM_SPI_DO 93 ++#define PAD_PM_SPI_WPZ 94 ++#define PAD_PM_SPI_HLD 95 ++#define PAD_PM_LED0 96 ++#define PAD_PM_LED1 97 ++#define PAD_SAR_GPIO0 98 ++#define PAD_SAR_GPIO1 99 ++#define PAD_SAR_GPIO2 100 ++#define PAD_SAR_GPIO3 101 ++#define PAD_ETH_RN 102 ++#define PAD_ETH_RP 103 ++#define PAD_ETH_TN 104 ++#define PAD_ETH_TP 105 ++#define PAD_USB_DM 106 ++#define PAD_USB_DP 107 ++#define PAD_DM_P1 108 ++#define PAD_DP_P1 109 ++ ++#define GPIO_NR 110 ++#define PAD_UNKNOWN 0xFF ++#endif +diff --git a/drivers/sstar/include/infinity3/irqs.h b/drivers/sstar/include/infinity3/irqs.h +new file mode 100755 +index 000000000000..4e303b861925 +--- /dev/null ++++ b/drivers/sstar/include/infinity3/irqs.h +@@ -0,0 +1,251 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_DUMMY_03 (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_POWER_0_NG (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_POWER_1_NG (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DUMMY_09 (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_DUMMY_10 (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_DUMMY_11 (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_PM_ERROR_RESP (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_WAKE_ON_LAN (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_DUMMY_14 (GIC_SPI_MS_IRQ_START + 14) ++#define INT_IRQ_DUMMY_15 (GIC_SPI_MS_IRQ_START + 15) ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_FCIE (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_VHE (GIC_SPI_MS_IRQ_START + 21) ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) //? ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) //? ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) //? ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_CMDQ1 (GIC_SPI_MS_IRQ_START + 52) //I3 New ++#define INT_IRQ_CMDQ2 (GIC_SPI_MS_IRQ_START + 53) //I3 New ++#define INT_IRQ_USB_INT_P1 (GIC_SPI_MS_IRQ_START + 54) //I3 New ++#define INT_IRQ_UHC_INT_P1 (GIC_SPI_MS_IRQ_START + 55) //I3 New ++#define INT_IRQ_IVE_INT (GIC_SPI_MS_IRQ_START + 56) //I3 New ++#define INT_IRQ_LDC_IRQ (GIC_SPI_MS_IRQ_START + 57) //I3 New ++#define INT_IRQ_SC1_TOP_INT (GIC_SPI_MS_IRQ_START + 58) //I3 New ++#define INT_IRQ_SC2_TOP_INT (GIC_SPI_MS_IRQ_START + 59) //I3 New ++#define INT_IRQ_DUMMY_60 (GIC_SPI_MS_IRQ_START + 60) ++#define INT_IRQ_DUMMY_61 (GIC_SPI_MS_IRQ_START + 61) ++#define INT_IRQ_DUMMY_62 (GIC_SPI_MS_IRQ_START + 62) ++#define INT_IRQ_DUMMY_63 (GIC_SPI_MS_IRQ_START + 63) ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_IR (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_DVI_CK_DET (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_5 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_6 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_GPIO_10 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_DUMMY_13 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_DUMMY_14 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_DUMMY_15 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_DUMMY_16 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_DUMMY_17 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_DUMMY_18 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_DUMMY_19 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_DUMMY_20 (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_DUMMY_21 (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_DUMMY_24 (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_DUMMY_25 (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_32 (PMSLEEP_FIQ_START + 32) ++#define INT_PMSLEEP_DUMMY_33 (PMSLEEP_FIQ_START + 33) ++#define INT_PMSLEEP_DUMMY_34 (PMSLEEP_FIQ_START + 34) ++#define INT_PMSLEEP_DUMMY_35 (PMSLEEP_FIQ_START + 35) ++#define INT_PMSLEEP_DUMMY_36 (PMSLEEP_FIQ_START + 36) ++#define INT_PMSLEEP_DUMMY_37 (PMSLEEP_FIQ_START + 37) ++#define INT_PMSLEEP_DUMMY_38 (PMSLEEP_FIQ_START + 38) ++#define INT_PMSLEEP_DUMMY_39 (PMSLEEP_FIQ_START + 39) ++#define INT_PMSLEEP_DUMMY_40 (PMSLEEP_FIQ_START + 40) ++#define INT_PMSLEEP_DUMMY_41 (PMSLEEP_FIQ_START + 41) ++#define INT_PMSLEEP_DUMMY_42 (PMSLEEP_FIQ_START + 42) ++#define INT_PMSLEEP_DUMMY_43 (PMSLEEP_FIQ_START + 43) ++#define INT_PMSLEEP_DUMMY_44 (PMSLEEP_FIQ_START + 44) ++#define INT_PMSLEEP_DUMMY_45 (PMSLEEP_FIQ_START + 45) ++#define INT_PMSLEEP_DUMMY_46 (PMSLEEP_FIQ_START + 46) ++#define INT_PMSLEEP_DUMMY_47 (PMSLEEP_FIQ_START + 47) ++#define INT_PMSLEEP_DUMMY_48 (PMSLEEP_FIQ_START + 48) ++#define INT_PMSLEEP_DUMMY_49 (PMSLEEP_FIQ_START + 49) ++#define INT_PMSLEEP_DUMMY_50 (PMSLEEP_FIQ_START + 50) ++#define INT_PMSLEEP_DUMMY_51 (PMSLEEP_FIQ_START + 51) ++#define INT_PMSLEEP_DUMMY_52 (PMSLEEP_FIQ_START + 52) ++#define INT_PMSLEEP_DUMMY_53 (PMSLEEP_FIQ_START + 53) ++#define INT_PMSLEEP_DUMMY_54 (PMSLEEP_FIQ_START + 54) ++#define INT_PMSLEEP_DUMMY_55 (PMSLEEP_FIQ_START + 55) ++#define INT_PMSLEEP_DUMMY_56 (PMSLEEP_FIQ_START + 56) ++#define INT_PMSLEEP_DUMMY_57 (PMSLEEP_FIQ_START + 57) ++#define INT_PMSLEEP_DUMMY_58 (PMSLEEP_FIQ_START + 58) ++#define INT_PMSLEEP_DUMMY_59 (PMSLEEP_FIQ_START + 59) ++#define INT_PMSLEEP_DUMMY_60 (PMSLEEP_FIQ_START + 60) ++#define INT_PMSLEEP_DUMMY_61 (PMSLEEP_FIQ_START + 61) ++#define INT_PMSLEEP_DUMMY_62 (PMSLEEP_FIQ_START + 62) ++#define INT_PMSLEEP_DUMMY_63 (PMSLEEP_FIQ_START + 63) ++#define INT_PMSLEEP_DUMMY_64 (PMSLEEP_FIQ_START + 64) ++#define INT_PMSLEEP_DUMMY_65 (PMSLEEP_FIQ_START + 65) ++#define INT_PMSLEEP_DUMMY_66 (PMSLEEP_FIQ_START + 66) ++#define INT_PMSLEEP_DUMMY_67 (PMSLEEP_FIQ_START + 67) ++#define INT_PMSLEEP_DUMMY_68 (PMSLEEP_FIQ_START + 68) ++#define INT_PMSLEEP_DUMMY_69 (PMSLEEP_FIQ_START + 69) ++#define INT_PMSLEEP_DUMMY_70 (PMSLEEP_FIQ_START + 70) ++#define INT_PMSLEEP_DUMMY_71 (PMSLEEP_FIQ_START + 71) ++#define INT_PMSLEEP_DUMMY_72 (PMSLEEP_FIQ_START + 72) ++#define INT_PMSLEEP_DUMMY_73 (PMSLEEP_FIQ_START + 73) ++#define INT_PMSLEEP_DUMMY_74 (PMSLEEP_FIQ_START + 74) ++#define INT_PMSLEEP_DUMMY_75 (PMSLEEP_FIQ_START + 75) ++#define INT_PMSLEEP_DUMMY_76 (PMSLEEP_FIQ_START + 76) ++#define INT_PMSLEEP_DUMMY_77 (PMSLEEP_FIQ_START + 77) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 78) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_DUMMY_00 (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_SAR_GPIO (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_DUMMY_07 (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity3/mcm_id.h b/drivers/sstar/include/infinity3/mcm_id.h +new file mode 100755 +index 000000000000..91d265366640 +--- /dev/null ++++ b/drivers/sstar/include/infinity3/mcm_id.h +@@ -0,0 +1,49 @@ ++/* ++* mcm_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_MCU51 0 ++#define MCM_ID_URDMA 1 ++#define MCM_ID_BDMA 2 ++#define MCM_ID_VHE 3 ++#define MCM_ID_MFE 4 ++#define MCM_ID_JPE 5 ++#define MCM_ID_BACH 6 ++#define MCM_ID_AESDMA 7 ++#define MCM_ID_UHC 8 ++#define MCM_ID_EMAC 9 ++#define MCM_ID_CMDQ 10 ++#define MCM_ID_ISP_DNR 11 ++#define MCM_ID_ISP_DMA 12 ++#define MCM_ID_GOP 13 ++#define MCM_ID_SC_DNR 14 ++#define MCM_ID_SC_DNR_SAD 15 ++#define MCM_ID_SC_CROP 16 ++#define MCM_ID_SC1_FRM 17 ++#define MCM_ID_SC1_SNP 18 ++#define MCM_ID_SC1_DBG 19 ++#define MCM_ID_SC2_FRM 20 ++#define MCM_ID_SC3_FRM 21 ++#define MCM_ID_FCIE 22 ++#define MCM_ID_SDIO 23 ++#define MCM_ID_SC1_SNPI 24 ++#define MCM_ID_SC2_SNPI 25 ++#define MCM_ID_ALL 99 ++ ++#endif +diff --git a/drivers/sstar/include/infinity3/padmux.h b/drivers/sstar/include/infinity3/padmux.h +new file mode 100755 +index 000000000000..44e4ad2d02a1 +--- /dev/null ++++ b/drivers/sstar/include/infinity3/padmux.h +@@ -0,0 +1,58 @@ ++/* ++* padmux.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++#define PINMUX_FOR_I2C0_MODE 0x01 ++#define PINMUX_FOR_I2C1_MODE 0x02 ++#define PINMUX_FOR_SPI0_MODE 0x03 ++#define PINMUX_FOR_SPI1_MODE 0x04 ++#define PINMUX_FOR_FUART_MODE 0x05 ++#define PINMUX_FOR_UART0_MODE 0x06 ++#define PINMUX_FOR_UART1_MODE 0x07 ++#define PINMUX_FOR_SD_MODE 0x08 ++#define PINMUX_FOR_SDIO_MODE 0x09 ++#define PINMUX_FOR_NAND_MODE 0x0a ++#define PINMUX_FOR_EMMC_MODE 0x0b ++#define PINMUX_FOR_IRIN_MODE 0x0c ++#define PINMUX_FOR_SAR_MODE 0x0d ++#define PINMUX_FOR_SR_MODE 0x0e ++#define PINMUX_FOR_TTL_MODE 0x0f ++#define PINMUX_FOR_PWM0_MODE 0x10 ++#define PINMUX_FOR_PWM1_MODE 0x11 ++#define PINMUX_FOR_PWM2_MODE 0x12 ++#define PINMUX_FOR_PWM3_MODE 0x13 ++#define PINMUX_FOR_PWM4_MODE 0x14 ++#define PINMUX_FOR_PWM5_MODE 0x15 ++#define PINMUX_FOR_PWM6_MODE 0x16 ++#define PINMUX_FOR_PWM7_MODE 0x17 ++#define PINMUX_FOR_I2S_MODE 0x18 ++#define PINMUX_FOR_ETH_MODE 0x19 ++#define PINMUX_FOR_CCIR_MODE 0x1a ++#define PINMUX_FOR_DMIC_MODE 0x1b ++#define PINMUX_FOR_EJ_MODE 0x1c ++#define PINMUX_FOR_PMSPI_MODE 0x1d ++#define PINMUX_FOR_LED_MODE 0x1e ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++S32 halPadGetVal(U32 padID, U32* mode); ++S32 halPadSetVal(U32 padID, U32 mode); ++S32 halCheckPin(U32 padID); ++ ++#endif +diff --git a/drivers/sstar/include/infinity3/reg_clks.h b/drivers/sstar/include/infinity3/reg_clks.h +new file mode 100755 +index 000000000000..0be3e5441999 +--- /dev/null ++++ b/drivers/sstar/include/infinity3/reg_clks.h +@@ -0,0 +1,449 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_OFFSET (10) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCIE_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_FCIE_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FCLK2_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity3/registers.h b/drivers/sstar/include/infinity3/registers.h +new file mode 100755 +index 000000000000..b8f1c40a2790 +--- /dev/null ++++ b/drivers/sstar/include/infinity3/registers.h +@@ -0,0 +1,247 @@ ++/* ++* registers.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++#define REG_ADDR(addr) (*((volatile U16*)(0xFD200000 + (addr << 1)))) ++ ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0xFFFFFFFF ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++#define MIU0_BASE ARM_MIU0_BUS_BASE ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x10000 ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100220) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0600) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3000) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I3_PACKAGE_UNKNOWN =0x00, ++ MS_I3_PACKAGE_QFN_DDR2_32MB, ++ MS_I3_PACKAGE_QFN_DDR2_64MB, ++ MS_I3_PACKAGE_BGA_128MB, ++ MS_I3_PACKAGE_BGA_256MB, ++ MS_I3_PACKAGE_QFN_DDR3_128MB, ++ MS_I3_PACKAGE_EXTENDED=0x30, ++ MS_I3_PACKAGE_DDR3_1866_128MB =0x30, ++ MS_I3_PACKAGE_DDR3_1866_256MB, ++ MS_I3_PACKAGE_FPGA_128MB =0x90, ++} MS_I3_PACKAGE_TYPE; ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity3/tsensor.h b/drivers/sstar/include/infinity3/tsensor.h +new file mode 100755 +index 000000000000..30e40f7d6d1b +--- /dev/null ++++ b/drivers/sstar/include/infinity3/tsensor.h +@@ -0,0 +1,23 @@ ++/* ++* tsensor.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __CPU_FREQ_H ++#define __CPU_FREQ_H ++ ++int ms_get_temp(void); ++ ++#endif //__CPU_FREQ_H +diff --git a/drivers/sstar/include/infinity5/Kconfig b/drivers/sstar/include/infinity5/Kconfig +new file mode 100644 +index 000000000000..b8c53a9bb548 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/Kconfig +@@ -0,0 +1,16 @@ ++source "drivers/sstar/emmc/Kconfig" ++source "drivers/sstar/sdmmc/Kconfig" ++source "drivers/sstar/usb/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/ircut/Kconfig" ++source "drivers/sstar/rtc/Kconfig" ++source "drivers/sstar/xpm/Kconfig" ++source "drivers/sstar/crypto/Kconfig" ++source "drivers/sstar/cpufreq/Kconfig" ++source "drivers/sstar/ive/Kconfig" ++source "drivers/sstar/notify/Kconfig" ++source "drivers/sstar/isrcb/Kconfig" ++source "drivers/sstar/miu/Kconfig" ++source "drivers/sstar/bdma/Kconfig" ++source "drivers/sstar/movedma/Kconfig" ++ +diff --git a/drivers/sstar/include/infinity5/camclk.h b/drivers/sstar/include/infinity5/camclk.h +new file mode 100644 +index 000000000000..1028447a4b63 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/camclk.h +@@ -0,0 +1,210 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_mpll_432m 1 ++#define CAMCLK_upll_384m 2 ++#define CAMCLK_upll_320m 3 ++#define CAMCLK_mpll_288m 4 ++#define CAMCLK_utmi_240m 5 ++#define CAMCLK_mpll_216m 6 ++#define CAMCLK_utmi_192m 7 ++#define CAMCLK_mpll_172m 8 ++#define CAMCLK_utmi_160m 9 ++#define CAMCLK_mpll_123m 10 ++#define CAMCLK_mpll_86m 11 ++#define CAMCLK_mpll_288m_div2 12 ++#define CAMCLK_mpll_288m_div4 13 ++#define CAMCLK_mpll_288m_div8 14 ++#define CAMCLK_mpll_216m_div2 15 ++#define CAMCLK_mpll_216m_div4 16 ++#define CAMCLK_mpll_216m_div8 17 ++#define CAMCLK_mpll_123m_div2 18 ++#define CAMCLK_mpll_86m_div2 19 ++#define CAMCLK_mpll_86m_div4 20 ++#define CAMCLK_mpll_86m_div16 21 ++#define CAMCLK_utmi_192m_div4 22 ++#define CAMCLK_utmi_160m_div4 23 ++#define CAMCLK_utmi_160m_div5 24 ++#define CAMCLK_utmi_160m_div8 25 ++#define CAMCLK_xtali_12m 26 ++#define CAMCLK_xtali_12m_div8 27 ++#define CAMCLK_xtali_12m_div16 28 ++#define CAMCLK_xtali_12m_div40 29 ++#define CAMCLK_xtali_12m_div64 30 ++#define CAMCLK_xtali_12m_div128 31 ++#define CAMCLK_RTC_CLK_32K 32 ++#define CAMCLK_pm_riu_w_clk_in 33 ++#define CAMCLK_riu_w_clk_in 34 ++#define CAMCLK_riu_w_clk_top 35 ++#define CAMCLK_riu_w_clk_sc_gp 36 ++#define CAMCLK_riu_w_clk_vhe_gp 37 ++#define CAMCLK_riu_w_clk_hemcu_gp 38 ++#define CAMCLK_riu_w_clk_mipi_if_gp 39 ++#define CAMCLK_riu_w_clk_mcu_if_gp 40 ++#define CAMCLK_miu_p 41 ++#define CAMCLK_miu_vhe_gp_p 42 ++#define CAMCLK_miu_sc_gp_p 43 ++#define CAMCLK_miu2x_p 44 ++#define CAMCLK_mcu_p 45 ++#define CAMCLK_mcu_pm_p 46 ++#define CAMCLK_isp_p 47 ++#define CAMCLK_fclk1_p 48 ++#define CAMCLK_fclk2_p 49 ++#define CAMCLK_sdio_p 50 ++#define CAMCLK_fcie_p 51 ++#define CAMCLK_tck_buf 52 ++#define CAMCLK_pad2isp_sr_pclk 53 ++#define CAMCLK_ccir_in_clk 54 ++#define CAMCLK_eth_buf 55 ++#define CAMCLK_rmii_buf 56 ++#define CAMCLK_emac_testrx125_in_lan 57 ++#define CAMCLK_miu_ff 58 ++#define CAMCLK_miu_sc_gp 59 ++#define CAMCLK_miu_vhe_gp 60 ++#define CAMCLK_miu_dig 61 ++#define CAMCLK_miu_xd2miu 62 ++#define CAMCLK_miu_urdma 63 ++#define CAMCLK_miu_bdma 64 ++#define CAMCLK_miu_vhe 65 ++#define CAMCLK_miu_jpe1 66 ++#define CAMCLK_miu_jpe0 67 ++#define CAMCLK_miu_bach 68 ++#define CAMCLK_miu_file 69 ++#define CAMCLK_miu_uhc0 70 ++#define CAMCLK_miu_emac 71 ++#define CAMCLK_miu_cmdq 72 ++#define CAMCLK_miu_isp_dnr 73 ++#define CAMCLK_miu_isp_rot 74 ++#define CAMCLK_miu_isp_dma 75 ++#define CAMCLK_miu_isp_sta 76 ++#define CAMCLK_miu_gop 77 ++#define CAMCLK_miu_sc_dnr 78 ++#define CAMCLK_miu_sc_dnr_sad 79 ++#define CAMCLK_miu_sc_crop 80 ++#define CAMCLK_miu_sc1_frm 81 ++#define CAMCLK_miu_sc1_snp 82 ++#define CAMCLK_miu_sc1_snpi 83 ++#define CAMCLK_miu_sc1_dbg 84 ++#define CAMCLK_miu_sc2_frm 85 ++#define CAMCLK_miu_sc2_snpi 86 ++#define CAMCLK_miu_sc3_frm 87 ++#define CAMCLK_miu_fcie 88 ++#define CAMCLK_miu_sdio 89 ++#define CAMCLK_miu_ive 90 ++#define CAMCLK_riu 91 ++#define CAMCLK_riu_nogating 92 ++#define CAMCLK_riu_sc_gp 93 ++#define CAMCLK_riu_vhe_gp 94 ++#define CAMCLK_riu_hemcu_gp 95 ++#define CAMCLK_riu_mipi_gp 96 ++#define CAMCLK_riu_mcu_if 97 ++#define CAMCLK_miu2x 98 ++#define CAMCLK_axi2x 99 ++#define CAMCLK_tck 100 ++#define CAMCLK_imi 101 ++#define CAMCLK_gop0 102 ++#define CAMCLK_gop1 103 ++#define CAMCLK_gop2 104 ++#define CAMCLK_mpll_144m 105 ++#define CAMCLK_mpll_144m_div2 106 ++#define CAMCLK_mpll_144m_div4 107 ++#define CAMCLK_xtali_24m 108 ++#define CAMCLK_xtali_12m_div2 109 ++#define CAMCLK_xtali_12m_div4 110 ++#define CAMCLK_xtali_12m_div12 111 ++#define CAMCLK_rtc_32k 112 ++#define CAMCLK_rtc_32k_div4 113 ++#define CAMCLK_live_pm 114 ++#define CAMCLK_riu_pm 115 ++#define CAMCLK_miupll_clk 116 ++#define CAMCLK_ddrpll_clk 117 ++#define CAMCLK_lpll_clk 118 ++#define CAMCLK_lpll_clk_div2 119 ++#define CAMCLK_lpll_clk_div4 120 ++#define CAMCLK_lpll_clk_div8 121 ++#define CAMCLK_cpupll_clk 122 ++#define CAMCLK_ipupll_clk 123 ++#define CAMCLK_venpll_clk 124 ++#define CAMCLK_utmi 125 ++#define CAMCLK_upll 126 ++#define CAMCLK_fuart0_synth_out 127 ++#define CAMCLK_csi2_mac_p 128 ++#define CAMCLK_miu 129 ++#define CAMCLK_ddr_syn 130 ++#define CAMCLK_miu_rec 131 ++#define CAMCLK_mcu 132 ++#define CAMCLK_riubrdg 133 ++#define CAMCLK_bdma 134 ++#define CAMCLK_spi 135 ++#define CAMCLK_uart0 136 ++#define CAMCLK_uart1 137 ++#define CAMCLK_fuart0_synth_in 138 ++#define CAMCLK_fuart 139 ++#define CAMCLK_mspi0 140 ++#define CAMCLK_mspi1 141 ++#define CAMCLK_miic0 142 ++#define CAMCLK_miic1 143 ++#define CAMCLK_bist 144 ++#define CAMCLK_xtali 145 ++#define CAMCLK_live 146 ++#define CAMCLK_sr_mclk 147 ++#define CAMCLK_sr_mclk1 148 ++#define CAMCLK_bist_pm 149 ++#define CAMCLK_pwr_ctl 150 ++#define CAMCLK_ipu 151 ++#define CAMCLK_bist_ipu_gp 152 ++#define CAMCLK_miic2 153 ++#define CAMCLK_miic3 154 ++#define CAMCLK_csi_mac_lptx_top_i_0 155 ++#define CAMCLK_csi_mac_top_i_0 156 ++#define CAMCLK_csi_ns_top_i_0 157 ++#define CAMCLK_csi_mac_lptx_top_i_1 158 ++#define CAMCLK_csi_mac_top_i_1 159 ++#define CAMCLK_csi_ns_top_i_1 160 ++#define CAMCLK_bist_vhe_gp 161 ++#define CAMCLK_vhe 162 ++#define CAMCLK_xtali_sc_gp 163 ++#define CAMCLK_bist_sc_gp 164 ++#define CAMCLK_emac_ahb 165 ++#define CAMCLK_jpe 166 ++#define CAMCLK_aesdma 167 ++#define CAMCLK_sdio 168 ++#define CAMCLK_fcie 169 ++#define CAMCLK_ecc 170 ++#define CAMCLK_sr 171 ++#define CAMCLK_isp 172 ++#define CAMCLK_idclk 173 ++#define CAMCLK_fclk1 174 ++#define CAMCLK_fclk2 175 ++#define CAMCLK_odclk 176 ++#define CAMCLK_ive 177 ++#define CAMCLK_dip 178 ++#define CAMCLK_emac_tx 179 ++#define CAMCLK_emac_rx 180 ++#define CAMCLK_emac_tx_ref 181 ++#define CAMCLK_emac_rx_ref 182 ++#define CAMCLK_hemcu_216m 183 ++#define CAMCLK_csi_mac 184 ++#define CAMCLK_mac_lptx 185 ++#define CAMCLK_ns 186 ++#define CAMCLK_mcu_pm 187 ++#define CAMCLK_spi_pm 188 ++#define CAMCLK_pm_sleep 189 ++#define CAMCLK_sar 190 ++#define CAMCLK_rtc 191 ++#endif +diff --git a/drivers/sstar/include/infinity5/gpio.h b/drivers/sstar/include/infinity5/gpio.h +new file mode 100644 +index 000000000000..2d5ac61a2b76 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/gpio.h +@@ -0,0 +1,182 @@ ++/* ++* gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO10 10 ++#define PAD_GPIO11 11 ++#define PAD_GPIO12 12 ++#define PAD_GPIO13 13 ++#define PAD_GPIO14 14 ++#define PAD_GPIO15 15 ++#define PAD_FUART_RX 16 ++#define PAD_FUART_TX 17 ++#define PAD_FUART_CTS 18 ++#define PAD_FUART_RTS 19 ++#define PAD_I2C0_SCL 20 ++#define PAD_I2C0_SDA 21 ++#define PAD_I2C1_SCL 22 ++#define PAD_I2C1_SDA 23 ++#define PAD_SNR0_D0 24 ++#define PAD_SNR0_D1 25 ++#define PAD_SNR0_D2 26 ++#define PAD_SNR0_D3 27 ++#define PAD_SNR0_D4 28 ++#define PAD_SNR0_D5 29 ++#define PAD_SNR0_D6 30 ++#define PAD_SNR0_D7 31 ++#define PAD_SNR0_D8 32 ++#define PAD_SNR0_D9 33 ++#define PAD_SNR0_D10 34 ++#define PAD_SNR0_D11 35 ++#define PAD_SNR0_GPIO0 36 ++#define PAD_SNR0_GPIO1 37 ++#define PAD_SNR0_GPIO2 38 ++#define PAD_SNR0_GPIO3 39 ++#define PAD_SNR0_GPIO4 40 ++#define PAD_SNR0_GPIO5 41 ++#define PAD_SNR0_GPIO6 42 ++#define PAD_SNR1_DA0P 43 ++#define PAD_SNR1_DA0N 44 ++#define PAD_SNR1_CKP 45 ++#define PAD_SNR1_CKN 46 ++#define PAD_SNR1_DA1P 47 ++#define PAD_SNR1_DA1N 48 ++#define PAD_SNR1_GPIO0 49 ++#define PAD_SNR1_GPIO1 50 ++#define PAD_SNR1_GPIO2 51 ++#define PAD_SNR1_GPIO3 52 ++#define PAD_SNR1_GPIO4 53 ++#define PAD_SNR1_GPIO5 54 ++#define PAD_SNR1_GPIO6 55 ++#define PAD_NAND_ALE 56 ++#define PAD_NAND_CLE 57 ++#define PAD_NAND_CEZ 58 ++#define PAD_NAND_WEZ 59 ++#define PAD_NAND_WPZ 60 ++#define PAD_NAND_REZ 61 ++#define PAD_NAND_RBZ 62 ++#define PAD_NAND_DA0 63 ++#define PAD_NAND_DA1 64 ++#define PAD_NAND_DA2 65 ++#define PAD_NAND_DA3 66 ++#define PAD_NAND_DA4 67 ++#define PAD_NAND_DA5 68 ++#define PAD_NAND_DA6 69 ++#define PAD_NAND_DA7 70 ++#define PAD_LCD_D0 71 ++#define PAD_LCD_D1 72 ++#define PAD_LCD_D2 73 ++#define PAD_LCD_D3 74 ++#define PAD_LCD_D4 75 ++#define PAD_LCD_D5 76 ++#define PAD_LCD_D6 77 ++#define PAD_LCD_D7 78 ++#define PAD_LCD_D8 79 ++#define PAD_LCD_D9 80 ++#define PAD_LCD_D10 81 ++#define PAD_LCD_D11 82 ++#define PAD_LCD_D12 83 ++#define PAD_LCD_D13 84 ++#define PAD_LCD_D14 85 ++#define PAD_LCD_D15 86 ++#define PAD_LCD_D16 87 ++#define PAD_LCD_D17 88 ++#define PAD_LCD_D18 89 ++#define PAD_LCD_D19 90 ++#define PAD_LCD_D20 91 ++#define PAD_LCD_D21 92 ++#define PAD_LCD_D22 93 ++#define PAD_LCD_D23 94 ++#define PAD_LCD_VSYNC 95 ++#define PAD_LCD_HSYNC 96 ++#define PAD_LCD_PCLK 97 ++#define PAD_LCD_DE 98 ++#define PAD_UART0_RX 99 ++#define PAD_UART0_TX 100 ++#define PAD_UART1_RX 101 ++#define PAD_UART1_TX 102 ++#define PAD_SPI0_CZ 103 ++#define PAD_SPI0_CK 104 ++#define PAD_SPI0_DI 105 ++#define PAD_SPI0_DO 106 ++#define PAD_SPI1_CZ 107 ++#define PAD_SPI1_CK 108 ++#define PAD_SPI1_DI 109 ++#define PAD_SPI1_DO 110 ++#define PAD_PWM0 111 ++#define PAD_PWM1 112 ++#define PAD_SD_CLK 113 ++#define PAD_SD_CMD 114 ++#define PAD_SD_D0 115 ++#define PAD_SD_D1 116 ++#define PAD_SD_D2 117 ++#define PAD_SD_D3 118 ++#define PAD_PM_SD_CDZ 119 ++#define PAD_PM_IRIN 120 ++#define PAD_PM_GPIO0 121 ++#define PAD_PM_GPIO1 122 ++#define PAD_PM_GPIO2 123 ++#define PAD_PM_GPIO3 124 ++#define PAD_PM_GPIO4 125 ++#define PAD_PM_GPIO5 126 ++#define PAD_PM_GPIO6 127 ++#define PAD_PM_GPIO7 128 ++#define PAD_PM_GPIO8 129 ++#define PAD_PM_GPIO9 130 ++#define PAD_PM_GPIO10 131 ++#define PAD_PM_GPIO11 132 ++#define PAD_PM_GPIO12 133 ++#define PAD_PM_GPIO13 134 ++#define PAD_PM_GPIO14 135 ++#define PAD_PM_GPIO15 136 ++#define PAD_PM_SPI_CZ 137 ++#define PAD_PM_SPI_CK 138 ++#define PAD_PM_SPI_DI 139 ++#define PAD_PM_SPI_DO 140 ++#define PAD_PM_SPI_WPZ 141 ++#define PAD_PM_SPI_HLD 142 ++#define PAD_PM_LED0 143 ++#define PAD_PM_LED1 144 ++#define PAD_SAR_GPIO0 145 ++#define PAD_SAR_GPIO1 146 ++#define PAD_SAR_GPIO2 147 ++#define PAD_SAR_GPIO3 148 ++#define PAD_ETH_RN 149 ++#define PAD_ETH_RP 150 ++#define PAD_ETH_TN 151 ++#define PAD_ETH_TP 152 ++#define PAD_USB_DM 153 ++#define PAD_USB_DP 154 ++#define PAD_DM_P1 155 ++#define PAD_DP_P1 156 ++ ++#define GPIO_NR 157 ++#define PAD_UNKNOWN 0xFF ++ ++#endif // ___GPIO_H +diff --git a/drivers/sstar/include/infinity5/irqs.h b/drivers/sstar/include/infinity5/irqs.h +new file mode 100644 +index 000000000000..bc6b410ca807 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/irqs.h +@@ -0,0 +1,205 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_DUMMY_00 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_DUMMY_01 (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_DUMMY_02 (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_DUMMY_03 (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_MHE (GIC_SPI_MS_IRQ_START + 5) //I5 New ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_DIP (GIC_SPI_MS_IRQ_START + 7) //I5 New ++#define INT_IRQ_DUMMY_08 (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_BDMA_2 (GIC_SPI_MS_IRQ_START + 9) //I5 New ++#define INT_IRQ_BDMA_3 (GIC_SPI_MS_IRQ_START + 10) //I5 New ++#define INT_IRQ_MIIC_2 (GIC_SPI_MS_IRQ_START + 11) //I5 New ++#define INT_IRQ_MIIC_3 (GIC_SPI_MS_IRQ_START + 12) //I5 New ++#define INT_IRQ_LDC_FEYE (GIC_SPI_MS_IRQ_START + 13) //I5 New ++#define INT_IRQ_DUMMY_14 (GIC_SPI_MS_IRQ_START + 14) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 15) ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_FCIE (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_DUMMY_21 (GIC_SPI_MS_IRQ_START + 21) ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) //? ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) //? ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) //? ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2_0 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_CMDQ1 (GIC_SPI_MS_IRQ_START + 52) ++#define INT_IRQ_CMDQ2 (GIC_SPI_MS_IRQ_START + 53) ++#define INT_IRQ_USB_INT_P1 (GIC_SPI_MS_IRQ_START + 54) ++#define INT_IRQ_UHC_INT_P1 (GIC_SPI_MS_IRQ_START + 55) ++#define INT_IRQ_IVE_INT (GIC_SPI_MS_IRQ_START + 56) ++#define INT_IRQ_DLA_IRQ (GIC_SPI_MS_IRQ_START + 57) //I5 New ++#define INT_IRQ_SC1_TOP_INT (GIC_SPI_MS_IRQ_START + 58) ++#define INT_IRQ_SC2_TOP_INT (GIC_SPI_MS_IRQ_START + 59) ++#define INT_IRQ_MIPI_CSI2_1 (GIC_SPI_MS_IRQ_START + 60) ++#define INT_IRQ_VIF (GIC_SPI_MS_IRQ_START + 61) //I5 New ++#define INT_IRQ_MOVEDMA (GIC_SPI_MS_IRQ_START + 62) //I5 New ++#define INT_IRQ_CMDQ3 (GIC_SPI_MS_IRQ_START + 63) //I5 New ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_IR (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_DVI_CK_DET (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_5 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_6 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_GPIO_10 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_GPIO_11 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_GPIO_12 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_GPIO_13 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_GPIO_14 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_GPIO_15 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_DUMMY_18 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_DUMMY_19 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_DUMMY_20 (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_DUMMY_21 (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_DUMMY_24 (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_DUMMY_25 (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 32) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_DUMMY_00 (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_DUMMY_06 (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_DUMMY_07 (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity5/mcm_id.h b/drivers/sstar/include/infinity5/mcm_id.h +new file mode 100755 +index 000000000000..9da332459090 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/mcm_id.h +@@ -0,0 +1,82 @@ ++/* ++* mcm_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define REG_MCM_DIG_GP (BASE_REG_MCM_DIG_GP_PA) ++#define REG_MCM_MCU51 (REG_MCM_DIG_GP+(0x0<<2) ) ++#define REG_MCM_URDMA (REG_MCM_DIG_GP+(0x0<<2)+1) ++#define REG_MCM_BDMA (REG_MCM_DIG_GP+(0x1<<2) ) ++ ++#define REG_MCM_SC_GP1 (BASE_REG_MCM_SC_GP_PA) ++#define REG_MCM_DIP_R (REG_MCM_SC_GP1+(0x0<<2) ) ++#define REG_MCM_DIP_W (REG_MCM_SC_GP1+(0x0<<2)+1) ++#define REG_MCM_LDC (REG_MCM_SC_GP1+(0x1<<2) ) ++#define REG_MCM_SC2_FRM (REG_MCM_SC_GP1+(0x1<<2)+1) ++#define REG_MCM_SC3_FRM (REG_MCM_SC_GP1+(0x2<<2) ) ++#define REG_MCM_RSC (REG_MCM_SC_GP1+(0x2<<2)+1) ++#define REG_MCM_SC1_DBG (REG_MCM_SC_GP1+(0x3<<2) ) ++#define REG_MCM_CMDQ0 (REG_MCM_SC_GP1+(0x3<<2)+1) ++#define REG_MCM_MOVDMA0 (REG_MCM_SC_GP1+(0x4<<2) ) ++#define REG_MCM_EMAC (REG_MCM_SC_GP1+(0x4<<2)+1) ++// REG_MCM_GE ++#define REG_MCM_3DNR0_R (REG_MCM_SC_GP1+(0x5<<2)+1) ++#define REG_MCM_3DNR0_W (REG_MCM_SC_GP1+(0x6<<2) ) ++#define REG_MCM_GOP4 (REG_MCM_SC_GP1+(0x6<<2)+1) ++#define REG_MCM_ISP_DMAG0 (REG_MCM_SC_GP1+(0x7<<2) ) ++#define REG_MCM_ISP_DMAG1 (REG_MCM_SC_GP1+(0x7<<2)+1) ++#define REG_MCM_ISP_DMAG2 (REG_MCM_SC_GP1+(0x8<<2) ) ++#define REG_MCM_GOP2 (REG_MCM_SC_GP1+(0x8<<2)+1) ++#define REG_MCM_GOP3 (REG_MCM_SC_GP1+(0x9<<2) ) ++#define REG_MCM_ISP_DMAG (REG_MCM_SC_GP1+(0x9<<2)+1) ++#define REG_MCM_ISP_STA (REG_MCM_SC_GP1+(0xA<<2) ) ++#define REG_MCM_ISP_STA1 (REG_MCM_SC_GP1+(0xA<<2)+1) ++#define REG_MCM_CMDQ1 (REG_MCM_SC_GP1+(0xB<<2) ) ++#define REG_MCM_MOVDMA1 (REG_MCM_SC_GP1+(0xB<<2)+1) ++#define REG_MCM_IVE (REG_MCM_SC_GP1+(0xC<<2) ) ++#define REG_MCM_SC_ROT_R (REG_MCM_SC_GP1+(0xC<<2)+1) ++#define REG_MCM_SC_AIP_W (REG_MCM_SC_GP1+(0xD<<2) ) ++#define REG_MCM_SC0_FRM (REG_MCM_SC_GP1+(0xD<<2)+1) ++#define REG_MCM_SC0_SNP (REG_MCM_SC_GP1+(0xE<<2) ) ++#define REG_MCM_SC1_FRM (REG_MCM_SC_GP1+(0xE<<2)+1) ++#define REG_MCM_GOP0 (REG_MCM_SC_GP1+(0xF<<2) ) ++#define REG_MCM_3DNR1_R (REG_MCM_SC_GP1+(0xF<<2)+1) ++ ++#define REG_MCM_SC_GP2 (BASE_REG_MCM_SC_GP2_PA) ++#define REG_MCM_3DNR1_W (REG_MCM_SC_GP2+(0x0<<2) ) ++#define REG_MCM_CMDQ2 (REG_MCM_SC_GP2+(0x0<<2)+1) ++#define REG_MCM_AESDMA (REG_MCM_SC_GP2+(0x1<<2) ) ++#define REG_MCM_USB20 (REG_MCM_SC_GP2+(0x1<<2)+1) ++#define REG_MCM_USB20_H (REG_MCM_SC_GP2+(0x2<<2) ) ++#define REG_MCM_JPE (REG_MCM_SC_GP2+(0x2<<2)+1) ++// REG_MCM_XX ++// REG_MCM_DIP1_R ++// REG_MCM_DIP1_W ++#define REG_MCM_GOP1 (REG_MCM_SC_GP2+(0x4<<2)+1) ++#define REG_MCM_BACH (REG_MCM_SC_GP2+(0x5<<2) ) ++// REG_MCM_XX ++#define REG_MCM_CMDQ3 (REG_MCM_SC_GP2+(0x6<<2) ) ++#define REG_MCM_SDIO (REG_MCM_SC_GP2+(0x6<<2)+1) ++#define REG_MCM_FCIE (REG_MCM_SC_GP2+(0x7<<2) ) ++ ++#define REG_MCM_VHE_GP (BASE_REG_MCM_VHE_GP_PA) ++#define REG_MCM_VEN (REG_MCM_VHE_GP+(0x0<<2) ) ++ ++#define MCM_ID_ALL (0xFF) ++ ++#endif +diff --git a/drivers/sstar/include/infinity5/mdrv_miu.h b/drivers/sstar/include/infinity5/mdrv_miu.h +new file mode 100755 +index 000000000000..b6075714dbd6 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/mdrv_miu.h +@@ -0,0 +1,236 @@ ++/* ++* mdrv_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_MIU_H__ ++#define __MDRV_MIU_H__ ++ ++#ifdef CONFIG_64BIT ++ typedef unsigned long phy_addr; // 4 bytes ++#else ++ typedef unsigned long long phy_addr; // 8 bytes ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Enumeration Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ // group 0 ++ MIU_CLIENT_NONE = 0, //none can access ++ MIU_CLIENT_DIP0_R, ++ MIU_CLIENT_DIP0_W, ++ MIU_CLIENT_LDC_R, ++ MIU_CLIENT_SC2_FRAME_W, ++ MIU_CLIENT_SC3_FRAME_W, ++ MIU_CLIENT_RSC_R, ++ MIU_CLIENT_SC1_DBG_R, ++ MIU_CLIENT_CMDQ0_R, ++ MIU_CLIENT_MOVDMA0_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_2DGE_RW, ++ MIU_CLIENT_3DNR0_R, ++ MIU_CLIENT_3DNR0_W, ++ MIU_CLIENT_GOP4_R, ++ MIU_CLIENT_DUMMY_G0CF, ++ // group 1 ++ MIU_CLIENT_ISP_DMAG0_RW, ++ MIU_CLIENT_ISP_DMAG1_RW, ++ MIU_CLIENT_ISP_DMAG2_RW, ++ MIU_CLIENT_GOP2_R, ++ MIU_CLIENT_GOP3_R, ++ MIU_CLIENT_ISP_DMAG_RW, ++ MIU_CLIENT_ISP_AF_STA1_W, ++ MIU_CLIENT_ISP_MLOAD_RW, ++ MIU_CLIENT_CMDQ1_R, ++ MIU_CLIENT_MOVDMA1_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_DLA_RW, ++ MIU_CLIENT_IVE_RW, ++ MIU_CLIENT_DUMMY_G1CD, ++ MIU_CLIENT_DUMMY_G1CE, ++ MIU_CLIENT_DUMMY_G1CF, ++ // group 2 ++ MIU_CLIENT_DUMMY_G2C0, ++ MIU_CLIENT_SC_ROT_R, ++ MIU_CLIENT_SC_AIP_W, ++ MIU_CLIENT_SC0_FRAME_W, ++ MIU_CLIENT_SC0_SNAPSHOT_W, ++ MIU_CLIENT_SC1_FRAME_W, ++ MIU_CLIENT_GOP0_R, ++ MIU_CLIENT_3DNR1_R, ++ MIU_CLIENT_3DNR1_W, ++ MIU_CLIENT_CMDQ2_R, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_URDMA_RW, ++ // group 3 ++ MIU_CLIENT_VEN_R, ++ MIU_CLIENT_VEN_W, ++ MIU_CLIENT_JPE_W, ++ MIU_CLIENT_JPE_R, ++ MIU_CLIENT_DIP1_R, ++ MIU_CLIENT_DIP1_W, ++ MIU_CLIENT_GOP1_R, ++ MIU_CLIENT_BACH_RW, ++ MIU_CLIENT_BACH2_RW, ++ MIU_CLIENT_CMDQ3_R, ++ MIU_CLIENT_SDIO_RW, ++ MIU_CLIENT_FCIE_RW, ++ MIU_CLIENT_MIIC2_RW, ++ MIU_CLIENT_MIIC3_RW, ++ MIU_CLIENT_DUMMY_G3CE, ++ MIU_CLIENT_DUMMY_G3CF, ++ // group 4 ++ MIU_CLIENT_DUMMY_G4C0, ++ MIU_CLIENT_DUMMY_G4C1, ++ MIU_CLIENT_DUMMY_G4C2, ++ MIU_CLIENT_DUMMY_G4C3, ++ MIU_CLIENT_DUMMY_G4C4, ++ MIU_CLIENT_DUMMY_G4C5, ++ MIU_CLIENT_DUMMY_G4C6, ++ MIU_CLIENT_DUMMY_G4C7, ++ MIU_CLIENT_DUMMY_G4C8, ++ MIU_CLIENT_DUMMY_G4C9, ++ MIU_CLIENT_DUMMY_G4CA, ++ MIU_CLIENT_DUMMY_G4CB, ++ MIU_CLIENT_DUMMY_G4CC, ++ MIU_CLIENT_DUMMY_G4CD, ++ MIU_CLIENT_DUMMY_G4CE, ++ MIU_CLIENT_DUMMY_G4CF, ++ // group 5 ++ MIU_CLIENT_DUMMY_G5C0, ++ MIU_CLIENT_DUMMY_G5C1, ++ MIU_CLIENT_DUMMY_G5C2, ++ MIU_CLIENT_DUMMY_G5C3, ++ MIU_CLIENT_DUMMY_G5C4, ++ MIU_CLIENT_DUMMY_G5C5, ++ MIU_CLIENT_DUMMY_G5C6, ++ MIU_CLIENT_DUMMY_G5C7, ++ MIU_CLIENT_DUMMY_G5C8, ++ MIU_CLIENT_DUMMY_G5C9, ++ MIU_CLIENT_DUMMY_G5CA, ++ MIU_CLIENT_DUMMY_G5CB, ++ MIU_CLIENT_DUMMY_G5CC, ++ MIU_CLIENT_DUMMY_G5CD, ++ MIU_CLIENT_DUMMY_G5CE, ++ MIU_CLIENT_DUMMY_G5CF, ++ // group 6 ++ MIU_CLIENT_DUMMY_G6C0, ++ MIU_CLIENT_DUMMY_G6C1, ++ MIU_CLIENT_DUMMY_G6C2, ++ MIU_CLIENT_DUMMY_G6C3, ++ MIU_CLIENT_DUMMY_G6C4, ++ MIU_CLIENT_DUMMY_G6C5, ++ MIU_CLIENT_DUMMY_G6C6, ++ MIU_CLIENT_DUMMY_G6C7, ++ MIU_CLIENT_DUMMY_G6C8, ++ MIU_CLIENT_DUMMY_G6C9, ++ MIU_CLIENT_DUMMY_G6CA, ++ MIU_CLIENT_DUMMY_G6CB, ++ MIU_CLIENT_DUMMY_G6CC, ++ MIU_CLIENT_DUMMY_G6CD, ++ MIU_CLIENT_DUMMY_G6CE, ++ MIU_CLIENT_DUMMY_G6CF, ++ // group 7 ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_DUMMY_G7C1, ++ MIU_CLIENT_DUMMY_G7C2, ++ MIU_CLIENT_DUMMY_G7C3, ++ MIU_CLIENT_DUMMY_G7C4, ++ MIU_CLIENT_DUMMY_G7C5, ++ MIU_CLIENT_DUMMY_G7C6, ++ MIU_CLIENT_DUMMY_G7C7, ++ MIU_CLIENT_DUMMY_G7C8, ++ MIU_CLIENT_DUMMY_G7C9, ++ MIU_CLIENT_DUMMY_G7CA, ++ MIU_CLIENT_DUMMY_G7CB, ++ MIU_CLIENT_DUMMY_G7CC, ++ MIU_CLIENT_DUMMY_G7CD, ++ MIU_CLIENT_DUMMY_G7CE, ++ MIU_CLIENT_DUMMY_G7CF, ++} eMIUClientID; ++ ++typedef enum ++{ ++ E_MIU_0 = 0, ++ E_MIU_1, ++ E_MIU_2, ++ E_MIU_3, ++ E_MIU_NUM, ++} MIU_ID; ++ ++typedef enum ++{ ++ E_PROTECT_0 = 0, ++ E_PROTECT_1, ++ E_PROTECT_2, ++ E_PROTECT_3, ++ E_SLIT_0 = 16, ++ E_MIU_PROTECT_NUM, ++} PROTECT_ID; ++ ++//------------------------------------------------------------------------------------------------- ++// Structure Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ unsigned char bHit; ++ unsigned char u8Group; ++ unsigned char u8ClientID; ++ unsigned char u8Block; ++ unsigned int uAddress; ++} MIU_PortectInfo; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++unsigned char MDrv_MIU_Init(void); ++unsigned short* MDrv_MIU_GetDefaultClientID_KernelProtect(void); ++unsigned short* MDrv_MIU_GetClientID_KernelProtect(unsigned char u8MiuSel); ++ ++unsigned char MDrv_MIU_Protect( unsigned char u8Blockx, ++ unsigned short *pu8ProtectId, ++ phy_addr u64BusStart, ++ phy_addr u64BusEnd, ++ unsigned char bSetFlag); ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++unsigned char MDrv_MIU_GetProtectInfo(unsigned char u8MiuDev, MIU_PortectInfo *pInfo); ++#endif ++unsigned char MDrv_MIU_Slits(unsigned char u8Blockx, phy_addr u64SlitsStart, phy_addr u65SlitsEnd, unsigned char bSetFlag); ++unsigned char MDrv_MIU_Get_IDEnables_Value(unsigned char u8MiuDev, unsigned char u8Blockx, unsigned char u8ClientIndex); ++unsigned int MDrv_MIU_ProtectDramSize(void); ++int MDrv_MIU_ClientIdToName(unsigned short clientId, char *clientName); ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo); ++ ++#endif // __MDRV_MIU_H__ +diff --git a/drivers/sstar/include/infinity5/mhal_miu.h b/drivers/sstar/include/infinity5/mhal_miu.h +new file mode 100755 +index 000000000000..939fa4ceb5a7 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/mhal_miu.h +@@ -0,0 +1,95 @@ ++/* ++* mhal_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_MIU_H_ ++#define _MHAL_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_MAX_DEVICE (2) ++#define MIU_MAX_GROUP (8) ++#define MIU_MAX_GP_CLIENT (16) ++#define MIU_MAX_TBL_CLIENT (MIU_MAX_GROUP*MIU_MAX_GP_CLIENT) ++ ++#define MIU_PAGE_SHIFT (13) // Unit for MIU protect (8KB) ++#define MIU_PROTECT_ADDRESS_UNIT (0x20UL) // Unit for MIU hitted address ++#define MIU_MAX_PROTECT_BLOCK (4) ++#define MIU_MAX_PROTECT_ID (16) ++ ++#define IDNUM_KERNELPROTECT (16) ++ ++#ifndef BIT0 ++#define BIT0 0x0001UL ++#define BIT1 0x0002UL ++#define BIT2 0x0004UL ++#define BIT3 0x0008UL ++#define BIT4 0x0010UL ++#define BIT5 0x0020UL ++#define BIT6 0x0040UL ++#define BIT7 0x0080UL ++#define BIT8 0x0100UL ++#define BIT9 0x0200UL ++#define BIT10 0x0400UL ++#define BIT11 0x0800UL ++#define BIT12 0x1000UL ++#define BIT13 0x2000UL ++#define BIT14 0x4000UL ++#define BIT15 0x8000UL ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MIU_BLOCK_0 = 0, ++ E_MIU_BLOCK_1, ++ E_MIU_BLOCK_2, ++ E_MIU_BLOCK_3, ++ E_MIU_BLOCK_NUM, ++} MIU_BLOCK_ID; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo_Hal; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuDev, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex); ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void); ++unsigned int HAL_MIU_ProtectDramSize(void); ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName); ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo); ++ ++#endif // _MHAL_MIU_H_ ++ +diff --git a/drivers/sstar/include/infinity5/padmux.h b/drivers/sstar/include/infinity5/padmux.h +new file mode 100644 +index 000000000000..ef788cd7da1c +--- /dev/null ++++ b/drivers/sstar/include/infinity5/padmux.h +@@ -0,0 +1,83 @@ ++/* ++* padmux.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++#define PINMUX_FOR_FUART_MODE 0x01 ++#define PINMUX_FOR_UART0_MODE 0x02 ++#define PINMUX_FOR_UART1_MODE 0x03 ++#define PINMUX_FOR_PWM0_MODE 0x04 ++#define PINMUX_FOR_PWM1_MODE 0x05 ++#define PINMUX_FOR_PWM2_MODE 0x06 ++#define PINMUX_FOR_PWM3_MODE 0x07 ++#define PINMUX_FOR_PWM4_MODE 0x08 ++#define PINMUX_FOR_PWM5_MODE 0x09 ++#define PINMUX_FOR_PWM6_MODE 0x0a ++#define PINMUX_FOR_PWM7_MODE 0x0b ++#define PINMUX_FOR_SR_MODE 0x0c ++#define PINMUX_FOR_NAND_MODE 0x0d ++#define PINMUX_FOR_SD_MODE 0x0e ++#define PINMUX_FOR_SDIO_MODE 0x0f ++#define PINMUX_FOR_I2C0_MODE 0x10 ++#define PINMUX_FOR_I2C1_MODE 0x11 ++#define PINMUX_FOR_SPI0_MODE 0x12 ++#define PINMUX_FOR_SPI1_MODE 0x13 ++#define PINMUX_FOR_EJ_MODE 0x14 ++#define PINMUX_FOR_ETH_MODE 0x15 ++#define PINMUX_FOR_TTL_MODE 0x16 ++#define PINMUX_FOR_DMIC_MODE 0x17 ++#define PINMUX_FOR_I2S_MODE 0x18 ++#define PINMUX_FOR_I2S_RX_MODE 0x19 ++#define PINMUX_FOR_I2S_TX_MODE 0x1a ++#define PINMUX_FOR_I2S_MCK_MODE 0x1b ++#define PINMUX_FOR_TESTIN_MODE 0x1c ++#define PINMUX_FOR_TESTOUT_MODE 0x1d ++#define PINMUX_FOR_EMMC_MODE 0x1e ++#define PINMUX_FOR_EMMC_RSTN_EN 0x1f ++#define PINMUX_FOR_SR0_BT656_MODE 0x20 ++#define PINMUX_FOR_SR0_MIPI_MODE 0x21 ++#define PINMUX_FOR_SR0_PAR_MODE 0x22 ++#define PINMUX_FOR_I2C2_MODE 0x23 ++#define PINMUX_FOR_I2C3_MODE 0x24 ++#define PINMUX_FOR_SR1_BT656_MODE 0x25 ++#define PINMUX_FOR_SR1_MIPI_MODE 0x26 ++#define PINMUX_FOR_SR1_PAR_MODE 0x27 ++ ++#define PINMUX_FOR_PM_PM_IR_IS_GPIO 0x28 ++#define PINMUX_FOR_PM_PWM0_MODE 0x29 ++#define PINMUX_FOR_PM_PWM1_MODE 0x2a ++#define PINMUX_FOR_PM_LED_MODE 0x2b ++#define PINMUX_FOR_PM_PWM2_MODE 0x2c ++#define PINMUX_FOR_PM_PWM3_MODE 0x2d ++#define PINMUX_FOR_PM_VID_MODE 0x2e ++#define PINMUX_FOR_PM_SD_CDZ_MODE 0x2f ++#define PINMUX_FOR_PM_SPI_IS_GPIO 0x30 ++#define PINMUX_FOR_PM_UART_IS_GPIO 0x31 ++ ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++//============================================================================== ++// ++// FUNCTION PROTOTYPE ++// ++//============================================================================== ++ ++S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++ ++#endif // ___PADMUX_H +diff --git a/drivers/sstar/include/infinity5/regMIU.h b/drivers/sstar/include/infinity5/regMIU.h +new file mode 100755 +index 000000000000..6261d46e8412 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/regMIU.h +@@ -0,0 +1,101 @@ ++/* ++* regMIU.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_MIU_H_ ++#define _REG_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) ++#define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) ++ ++#define MIU_REG_BASE (0x1200UL) ++#define MIU1_REG_BASE (0x0D00UL) ++#define MIU2_REG_BASE (0x62000UL) ++#define PM_REG_BASE (0x1E00UL) ++#define MIU_ATOP_BASE (0x1000UL) ++#define MIU1_ATOP_BASE (0x0B00UL) ++#define MIU2_ATOP_BASE (0x62100UL) ++#define CHIP_TOP_BASE (0x1E00UL) ++#define MIU_ARB_REG_BASE (0x1100UL) ++#define MIU1_ARB_REG_BASE (0x0C00UL) ++#define MIU2_ARB_REG_BASE (0x62300UL) ++ ++#define MIU_PROTECT_EN_INTERNAL (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3UL) ++#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(11:8) ++#define MIU_PROTECT_DDR_32MB (0x50UL) ++#define MIU_PROTECT_DDR_64MB (0x60UL) ++#define MIU_PROTECT_DDR_128MB (0x70UL) ++#define MIU_PROTECT_DDR_256MB (0x80UL) ++#define MIU_PROTECT_DDR_512MB (0x90UL) ++#define MIU_PROTECT_DDR_1024MB (0xA0UL) ++#define MIU_PROTECT_DDR_2048MB (0xB0UL) ++ ++#define MIU_PROTECT0_ID0 (MIU_REG_BASE+0x2EUL) ++#define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20UL) ++#define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22UL) ++#define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24UL) ++#define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26UL) ++#define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT0_START (MIU_REG_BASE+0xC0UL) ++#define MIU_PROTECT1_START (MIU_REG_BASE+0xC4UL) ++#define MIU_PROTECT2_START (MIU_REG_BASE+0xC8UL) ++#define MIU_PROTECT3_START (MIU_REG_BASE+0xCCUL) ++#define REG_MIU_PROTECT_LOADDR (0x6DUL << 1) //0xDE ++#define REG_MIU_PROTECT_HIADDR (0x6EUL << 1) //0xDE ++#define REG_MIU_PROTECT_STATUS (0x6FUL << 1) //0xDE ++ ++// MIU selection registers ++#define REG_MIU_SEL0 (MIU_REG_BASE+0xf0UL) //0x12F0 ++#define REG_MIU_SEL1 (MIU_REG_BASE+0xf2UL) //0x12F1 ++#define REG_MIU_SEL2 (MIU_REG_BASE+0xf4UL) //0x12F2 ++#define REG_MIU_SEL3 (MIU_REG_BASE+0xf6UL) //0x12F3 ++#define REG_MIU_SELX(x) (0xF0UL+x*2) ++ ++// MIU1 ++#define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3UL) ++#define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2EUL) ++#define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20UL) ++#define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22UL) ++#define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24UL) ++#define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26UL) ++#define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0UL) ++#define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4UL) ++#define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8UL) ++#define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCCUL) ++ ++#define REG_MIU_I64_MODE (BIT7) ++#define REG_MIU_INIT_DONE (BIT15) ++ ++// Protection Status ++#define REG_MIU_PROTECT_LOG_CLR (BIT0) ++#define REG_MIU_PROTECT_IRQ_MASK (BIT1) ++#define REG_MIU_PROTECT_HIT_FALG (BIT4) ++#define REG_MIU_PROTECT_HIT_ID 14:8 ++#define REG_MIU_PROTECT_HIT_NO 7:5 ++ ++#endif // _REG_MIU_H_ ++ +diff --git a/drivers/sstar/include/infinity5/reg_clks.h b/drivers/sstar/include/infinity5/reg_clks.h +new file mode 100644 +index 000000000000..0be1b7bb1db9 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/reg_clks.h +@@ -0,0 +1,488 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_OFFSET (10) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BIST_IPU_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_IPU_GP_OFFSET (12) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP0_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP0_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP1_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP1_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_TOP0_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_CSI_MAC_TOP0_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_TOP1_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_CSI_MAC_TOP1_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCIE_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_FCIE_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_ISPSC_LDC_FEYE_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_IPU_BASE (REG_CKG_BASE+0x50*4) ++#define REG_CKG_IPU_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIIC2_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_MIIC2_OFFSET (0) ++ ++#define REG_CKG_MIIC3_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_MIIC3_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_NS_TOP0_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_NS_TOP0_OFFSET (0) ++ ++#define REG_CKG_NS_TOP1_BASE (REG_CKG_BASE+0x55*4) ++#define REG_CKG_NS_TOP1_OFFSET (8) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_SR_MCLK1_BASE (REG_CKG_BASE+0x56*4) ++#define REG_CKG_SR_MCLK1_OFFSET (0) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity5/registers.h b/drivers/sstar/include/infinity5/registers.h +new file mode 100755 +index 000000000000..171f713721d6 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/registers.h +@@ -0,0 +1,248 @@ ++/* ++* registers.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define REG_ADDR(addr) (*((volatile U16*)(0xFD200000 + (addr << 1)))) ++ ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xA0000000 ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0x80000000 ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++ ++#define MIU0_BASE ARM_MIU0_BUS_BASE ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0x1FC00000 ++#define IMI_VIRT (IMI_PHYS+IMI_OFFSET) //from IO_ADDRESS(x) ++#define IMI_OFFSET (MS_IO_OFFSET) ++#define IMI_SIZE 0x20000 ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x000E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x000F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x001200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x001400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x001E00) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x003800) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_MIU1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100D00) ++#define BASE_REG_MIU1_ARB_B_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100F00) ++#define BASE_REG_MIU_ARB_B_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101400) ++#define BASE_REG_MIU_ARB_E_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101600) ++#define BASE_REG_MIU1_ARB_E_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101900) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_MCM_SC_GP2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113600) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x002000) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_MOVDMA_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x131B00) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++#define BASE_REG_VENPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103600) ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x000600) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x003000) ++ ++#define BASE_REG_BDMA0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100200) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100220) ++#define BASE_REG_BDMA2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100240) ++#define BASE_REG_BDMA3_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100260) ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I5_PACKAGE_UNKNOWN =0x00, ++ MS_I5_PACKAGE_BGA_13X13, ++ MS_I5_PACKAGE_QFN, ++ MS_I5_PACKAGE_EXTENDED=0x30, ++ MS_I5_PACKAGE_FPGA_128MB =0x90, ++} MS_I5_PACKAGE_TYPE; ++ ++#endif // ___REGS_H +diff --git a/drivers/sstar/include/infinity5/tsensor.h b/drivers/sstar/include/infinity5/tsensor.h +new file mode 100755 +index 000000000000..30e40f7d6d1b +--- /dev/null ++++ b/drivers/sstar/include/infinity5/tsensor.h +@@ -0,0 +1,23 @@ ++/* ++* tsensor.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __CPU_FREQ_H ++#define __CPU_FREQ_H ++ ++int ms_get_temp(void); ++ ++#endif //__CPU_FREQ_H +diff --git a/drivers/sstar/include/infinity5/voltage_ctrl_demander.h b/drivers/sstar/include/infinity5/voltage_ctrl_demander.h +new file mode 100755 +index 000000000000..d04460e64eb8 +--- /dev/null ++++ b/drivers/sstar/include/infinity5/voltage_ctrl_demander.h +@@ -0,0 +1,36 @@ ++/* ++* voltage_ctrl.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __VOLTAGE_CTRL_DEMANDER_H ++#define __VOLTAGE_CTRL_DEMANDER_H ++ ++#define FOREACH_DEMANDER(DEMANDER) \ ++ DEMANDER(VOLTAGE_DEMANDER_CPUFREQ) \ ++ DEMANDER(VOLTAGE_DEMANDER_TEMPERATURE) \ ++ DEMANDER(VOLTAGE_DEMANDER_VENC) \ ++ DEMANDER(VOLTAGE_DEMANDER_MIU) \ ++ DEMANDER(VOLTAGE_DEMANDER_USER) \ ++ DEMANDER(VOLTAGE_DEMANDER_MAX) \ ++ ++#define GENERATE_ENUM(ENUM) ENUM, ++#define GENERATE_STRING(STRING) #STRING, ++ ++typedef enum { ++ FOREACH_DEMANDER(GENERATE_ENUM) ++} VOLTAGE_DEMANDER_E; ++ ++#endif //__VOLTAGE_CTRL_DEMANDER_H +diff --git a/drivers/sstar/include/infinity6/Kconfig b/drivers/sstar/include/infinity6/Kconfig +new file mode 100644 +index 000000000000..6c7d94244816 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/Kconfig +@@ -0,0 +1,13 @@ ++source "drivers/sstar/emmc/Kconfig" ++source "drivers/sstar/sdmmc/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/ircut/Kconfig" ++source "drivers/sstar/rtc/Kconfig" ++source "drivers/sstar/crypto/Kconfig" ++source "drivers/sstar/cpufreq/Kconfig" ++source "drivers/sstar/notify/Kconfig" ++source "drivers/sstar/isrcb/Kconfig" ++source "drivers/sstar/miu/Kconfig" ++source "drivers/sstar/bdma/Kconfig" ++source "drivers/sstar/movedma/Kconfig" ++ +diff --git a/drivers/sstar/include/infinity6/camclk.h b/drivers/sstar/include/infinity6/camclk.h +new file mode 100644 +index 000000000000..2e47c8f657f8 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/camclk.h +@@ -0,0 +1,201 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_upll_384m 3 ++#define CAMCLK_upll_320m 4 ++#define CAMCLK_mpll_288m 5 ++#define CAMCLK_utmi_240m 6 ++#define CAMCLK_mpll_216m 7 ++#define CAMCLK_utmi_192m 8 ++#define CAMCLK_mpll_172m 9 ++#define CAMCLK_utmi_160m 10 ++#define CAMCLK_mpll_123m 11 ++#define CAMCLK_mpll_86m 12 ++#define CAMCLK_mpll_288m_div2 13 ++#define CAMCLK_mpll_288m_div4 14 ++#define CAMCLK_mpll_288m_div8 15 ++#define CAMCLK_mpll_216m_div2 16 ++#define CAMCLK_mpll_216m_div4 17 ++#define CAMCLK_mpll_216m_div8 18 ++#define CAMCLK_mpll_123m_div2 19 ++#define CAMCLK_mpll_86m_div2 20 ++#define CAMCLK_mpll_86m_div4 21 ++#define CAMCLK_mpll_86m_div16 22 ++#define CAMCLK_utmi_192m_div4 23 ++#define CAMCLK_utmi_160m_div4 24 ++#define CAMCLK_utmi_160m_div5 25 ++#define CAMCLK_utmi_160m_div8 26 ++#define CAMCLK_xtali_12m 27 ++#define CAMCLK_xtali_12m_div8 28 ++#define CAMCLK_xtali_12m_div16 29 ++#define CAMCLK_xtali_12m_div40 30 ++#define CAMCLK_xtali_12m_div64 31 ++#define CAMCLK_xtali_12m_div128 32 ++#define CAMCLK_xtali_24m 33 ++#define CAMCLK_RTC_CLK_32K 34 ++#define CAMCLK_pm_riu_w_clk_in 35 ++#define CAMCLK_lpll_clk_div2 36 ++#define CAMCLK_lpll_clk_div4 37 ++#define CAMCLK_lpll_clk_div8 38 ++#define CAMCLK_armpll_37p125m 39 ++#define CAMCLK_riu_w_clk_in 40 ++#define CAMCLK_riu_w_clk_top 41 ++#define CAMCLK_riu_w_clk_sc_gp 42 ++#define CAMCLK_riu_w_clk_vhe_gp 43 ++#define CAMCLK_riu_w_clk_hemcu_gp 44 ++#define CAMCLK_riu_w_clk_mipi_if_gp 45 ++#define CAMCLK_riu_w_clk_mcu_if_gp 46 ++#define CAMCLK_miu_p 47 ++#define CAMCLK_mspi0_p 48 ++#define CAMCLK_mspi1_p 49 ++#define CAMCLK_miu_vhe_gp_p 50 ++#define CAMCLK_miu_sc_gp_p 51 ++#define CAMCLK_miu2x_p 52 ++#define CAMCLK_mcu_p 53 ++#define CAMCLK_mcu_pm_p 54 ++#define CAMCLK_isp_p 55 ++#define CAMCLK_fclk1_p 56 ++#define CAMCLK_fclk2_p 57 ++#define CAMCLK_sdio_p 58 ++#define CAMCLK_tck_buf 59 ++#define CAMCLK_pad2isp_sr_pclk 60 ++#define CAMCLK_ccir_in_clk 61 ++#define CAMCLK_eth_buf 62 ++#define CAMCLK_rmii_buf 63 ++#define CAMCLK_emac_testrx125_in_lan 64 ++#define CAMCLK_miu_ff 65 ++#define CAMCLK_miu_sc_gp 66 ++#define CAMCLK_miu_vhe_gp 67 ++#define CAMCLK_miu_dig 68 ++#define CAMCLK_miu_xd2miu 69 ++#define CAMCLK_miu_urdma 70 ++#define CAMCLK_miu_bdma 71 ++#define CAMCLK_miu_vhe 72 ++#define CAMCLK_miu_mfeh 73 ++#define CAMCLK_miu_mfe 74 ++#define CAMCLK_miu_jpe1 75 ++#define CAMCLK_miu_jpe0 76 ++#define CAMCLK_miu_bach 77 ++#define CAMCLK_miu_file 78 ++#define CAMCLK_miu_uhc0 79 ++#define CAMCLK_miu_emac 80 ++#define CAMCLK_miu_cmdq 81 ++#define CAMCLK_miu_isp_dnr 82 ++#define CAMCLK_miu_isp_rot 83 ++#define CAMCLK_miu_isp_dma 84 ++#define CAMCLK_miu_isp_sta 85 ++#define CAMCLK_miu_gop 86 ++#define CAMCLK_miu_sc_dnr 87 ++#define CAMCLK_miu_sc_dnr_sad 88 ++#define CAMCLK_miu_sc_crop 89 ++#define CAMCLK_miu_sc1_frm 90 ++#define CAMCLK_miu_sc1_snp 91 ++#define CAMCLK_miu_sc1_snpi 92 ++#define CAMCLK_miu_sc1_dbg 93 ++#define CAMCLK_miu_sc2_frm 94 ++#define CAMCLK_miu_sc2_snpi 95 ++#define CAMCLK_miu_sc3_frm 96 ++#define CAMCLK_miu_fcie 97 ++#define CAMCLK_miu_sdio 98 ++#define CAMCLK_miu_ive 99 ++#define CAMCLK_riu 100 ++#define CAMCLK_riu_nogating 101 ++#define CAMCLK_riu_sc_gp 102 ++#define CAMCLK_riu_vhe_gp 103 ++#define CAMCLK_riu_hemcu_gp 104 ++#define CAMCLK_riu_mipi_gp 105 ++#define CAMCLK_riu_mcu_if 106 ++#define CAMCLK_miu2x 107 ++#define CAMCLK_axi2x 108 ++#define CAMCLK_tck 109 ++#define CAMCLK_imi 110 ++#define CAMCLK_gop0 111 ++#define CAMCLK_gop1 112 ++#define CAMCLK_gop2 113 ++#define CAMCLK_mpll_144m 114 ++#define CAMCLK_mpll_144m_div2 115 ++#define CAMCLK_mpll_144m_div4 116 ++#define CAMCLK_xtali_12m_div2 117 ++#define CAMCLK_xtali_12m_div4 118 ++#define CAMCLK_xtali_12m_div12 119 ++#define CAMCLK_rtc_32k 120 ++#define CAMCLK_rtc_32k_div4 121 ++#define CAMCLK_live_pm 122 ++#define CAMCLK_riu_pm 123 ++#define CAMCLK_miupll_clk 124 ++#define CAMCLK_ddrpll_clk 125 ++#define CAMCLK_lpll_clk 126 ++#define CAMCLK_cpupll_clk 127 ++#define CAMCLK_utmi 128 ++#define CAMCLK_upll 129 ++#define CAMCLK_fuart0_synth_out 130 ++#define CAMCLK_csi2_mac_p 131 ++#define CAMCLK_miu 132 ++#define CAMCLK_ddr_syn 133 ++#define CAMCLK_miu_rec 134 ++#define CAMCLK_mcu 135 ++#define CAMCLK_riubrdg 136 ++#define CAMCLK_bdma 137 ++#define CAMCLK_spi 138 ++#define CAMCLK_uart0 139 ++#define CAMCLK_uart1 140 ++#define CAMCLK_fuart0_synth_in 141 ++#define CAMCLK_fuart 142 ++#define CAMCLK_mspi0 143 ++#define CAMCLK_mspi1 144 ++#define CAMCLK_mspi 145 ++#define CAMCLK_miic0 146 ++#define CAMCLK_miic1 147 ++#define CAMCLK_bist 148 ++#define CAMCLK_pwr_ctl 149 ++#define CAMCLK_xtali 150 ++#define CAMCLK_live 151 ++#define CAMCLK_sr_mclk 152 ++#define CAMCLK_bist_vhe_gp 153 ++#define CAMCLK_vhe 154 ++#define CAMCLK_mfe 155 ++#define CAMCLK_xtali_sc_gp 156 ++#define CAMCLK_bist_sc_gp 157 ++#define CAMCLK_emac_ahb 158 ++#define CAMCLK_jpe 159 ++#define CAMCLK_aesdma 160 ++#define CAMCLK_sdio 161 ++#define CAMCLK_sd 162 ++#define CAMCLK_isp 163 ++#define CAMCLK_fclk1 164 ++#define CAMCLK_fclk2 165 ++#define CAMCLK_odclk 166 ++#define CAMCLK_dip 167 ++#define CAMCLK_nlm 168 ++#define CAMCLK_emac_tx 169 ++#define CAMCLK_emac_rx 170 ++#define CAMCLK_emac_tx_ref 171 ++#define CAMCLK_emac_rx_ref 172 ++#define CAMCLK_hemcu_216m 173 ++#define CAMCLK_csi_mac 174 ++#define CAMCLK_mac_lptx 175 ++#define CAMCLK_ns 176 ++#define CAMCLK_mcu_pm 177 ++#define CAMCLK_spi_pm 178 ++#define CAMCLK_pm_sleep 179 ++#define CAMCLK_sar 180 ++#define CAMCLK_rtc 181 ++#define CAMCLK_ir 182 ++#endif +diff --git a/drivers/sstar/include/infinity6/gpi-irqs.h b/drivers/sstar/include/infinity6/gpi-irqs.h +new file mode 100755 +index 000000000000..82bff20dba31 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/gpi-irqs.h +@@ -0,0 +1,114 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++#define GPI_FIQ_START 0 ++#define INT_GPI_FIQ_PAD_UART1_RX (GPI_FIQ_START + 0) ++#define INT_GPI_FIQ_PAD_UART1_TX (GPI_FIQ_START + 1) ++#define INT_GPI_FIQ_PAD_UART0_RX (GPI_FIQ_START + 2) ++#define INT_GPI_FIQ_PAD_UART0_TX (GPI_FIQ_START + 3) ++#define INT_GPI_FIQ_PAD_SR_IO00 (GPI_FIQ_START + 4) ++#define INT_GPI_FIQ_PAD_SR_IO01 (GPI_FIQ_START + 5) ++#define INT_GPI_FIQ_PAD_SR_IO02 (GPI_FIQ_START + 6) ++#define INT_GPI_FIQ_PAD_SR_IO03 (GPI_FIQ_START + 7) ++#define INT_GPI_FIQ_PAD_SR_IO04 (GPI_FIQ_START + 8) ++#define INT_GPI_FIQ_PAD_SR_IO05 (GPI_FIQ_START + 9) ++#define INT_GPI_FIQ_PAD_SR_IO06 (GPI_FIQ_START + 10) ++#define INT_GPI_FIQ_PAD_SR_IO07 (GPI_FIQ_START + 11) ++#define INT_GPI_FIQ_PAD_SR_IO08 (GPI_FIQ_START + 12) ++#define INT_GPI_FIQ_PAD_SR_IO09 (GPI_FIQ_START + 13) ++#define INT_GPI_FIQ_PAD_SR_IO10 (GPI_FIQ_START + 14) ++#define INT_GPI_FIQ_PAD_SR_IO11 (GPI_FIQ_START + 15) ++#define INT_GPI_FIQ_PAD_SR_IO12 (GPI_FIQ_START + 16) ++#define INT_GPI_FIQ_PAD_SR_IO13 (GPI_FIQ_START + 17) ++#define INT_GPI_FIQ_PAD_SR_IO14 (GPI_FIQ_START + 18) ++#define INT_GPI_FIQ_PAD_SR_IO15 (GPI_FIQ_START + 19) ++#define INT_GPI_FIQ_PAD_SR_IO16 (GPI_FIQ_START + 20) ++#define INT_GPI_FIQ_PAD_SR_IO17 (GPI_FIQ_START + 21) ++#define INT_GPI_FIQ_PAD_SPI1_CZ (GPI_FIQ_START + 22) ++#define INT_GPI_FIQ_PAD_SPI1_CK (GPI_FIQ_START + 23) ++#define INT_GPI_FIQ_PAD_SPI1_DI (GPI_FIQ_START + 24) ++#define INT_GPI_FIQ_PAD_SPI1_DO (GPI_FIQ_START + 25) ++#define INT_GPI_FIQ_PAD_SPI0_CZ (GPI_FIQ_START + 26) ++#define INT_GPI_FIQ_PAD_SPI0_CK (GPI_FIQ_START + 27) ++#define INT_GPI_FIQ_PAD_SPI0_DI (GPI_FIQ_START + 28) ++#define INT_GPI_FIQ_PAD_SPI0_DO (GPI_FIQ_START + 29) ++#define INT_GPI_FIQ_PAD_SD_CLK (GPI_FIQ_START + 30) ++#define INT_GPI_FIQ_PAD_SD_CMD (GPI_FIQ_START + 31) ++#define INT_GPI_FIQ_PAD_SD_D0 (GPI_FIQ_START + 32) ++#define INT_GPI_FIQ_PAD_SD_D1 (GPI_FIQ_START + 33) ++#define INT_GPI_FIQ_PAD_SD_D2 (GPI_FIQ_START + 34) ++#define INT_GPI_FIQ_PAD_SD_D3 (GPI_FIQ_START + 35) ++#define INT_GPI_FIQ_PAD_SD1_IO0 (GPI_FIQ_START + 36) ++#define INT_GPI_FIQ_PAD_SD1_IO1 (GPI_FIQ_START + 37) ++#define INT_GPI_FIQ_PAD_SD1_IO2 (GPI_FIQ_START + 38) ++#define INT_GPI_FIQ_PAD_SD1_IO3 (GPI_FIQ_START + 39) ++#define INT_GPI_FIQ_PAD_SD1_IO4 (GPI_FIQ_START + 40) ++#define INT_GPI_FIQ_PAD_SD1_IO5 (GPI_FIQ_START + 41) ++#define INT_GPI_FIQ_PAD_SD1_IO6 (GPI_FIQ_START + 42) ++#define INT_GPI_FIQ_PAD_SD1_IO7 (GPI_FIQ_START + 43) ++#define INT_GPI_FIQ_PAD_SD1_IO8 (GPI_FIQ_START + 44) ++#define INT_GPI_FIQ_PAD_PWM0 (GPI_FIQ_START + 45) ++#define INT_GPI_FIQ_PAD_PWM1 (GPI_FIQ_START + 46) ++#define INT_GPI_FIQ_PAD_I2C1_SCL (GPI_FIQ_START + 47) ++#define INT_GPI_FIQ_PAD_I2C1_SDA (GPI_FIQ_START + 48) ++#define INT_GPI_FIQ_PAD_I2C0_SCL (GPI_FIQ_START + 49) ++#define INT_GPI_FIQ_PAD_I2C0_SDA (GPI_FIQ_START + 50) ++#define INT_GPI_FIQ_PAD_GPIO0 (GPI_FIQ_START + 51) ++#define INT_GPI_FIQ_PAD_GPIO1 (GPI_FIQ_START + 52) ++#define INT_GPI_FIQ_PAD_GPIO2 (GPI_FIQ_START + 53) ++#define INT_GPI_FIQ_PAD_GPIO3 (GPI_FIQ_START + 54) ++#define INT_GPI_FIQ_PAD_GPIO4 (GPI_FIQ_START + 55) ++#define INT_GPI_FIQ_PAD_GPIO5 (GPI_FIQ_START + 56) ++#define INT_GPI_FIQ_PAD_GPIO6 (GPI_FIQ_START + 57) ++#define INT_GPI_FIQ_PAD_GPIO7 (GPI_FIQ_START + 58) ++#define INT_GPI_FIQ_PAD_GPIO8 (GPI_FIQ_START + 59) ++#define INT_GPI_FIQ_PAD_GPIO9 (GPI_FIQ_START + 60) ++#define INT_GPI_FIQ_DUMMY61 (GPI_FIQ_START + 61) ++#define INT_GPI_FIQ_DUMMY62 (GPI_FIQ_START + 62) ++#define INT_GPI_FIQ_PAD_GPIO12 (GPI_FIQ_START + 63) ++#define INT_GPI_FIQ_PAD_GPIO13 (GPI_FIQ_START + 64) ++#define INT_GPI_FIQ_PAD_GPIO14 (GPI_FIQ_START + 65) ++#define INT_GPI_FIQ_PAD_GPIO15 (GPI_FIQ_START + 66) ++#define INT_GPI_FIQ_PAD_FUART_RX (GPI_FIQ_START + 67) ++#define INT_GPI_FIQ_PAD_FUART_TX (GPI_FIQ_START + 68) ++#define INT_GPI_FIQ_PAD_FUART_CTS (GPI_FIQ_START + 69) ++#define INT_GPI_FIQ_PAD_FUART_RTS (GPI_FIQ_START + 70) ++#define INT_GPI_FIQ_DUMMY71 (GPI_FIQ_START + 71) ++#define INT_GPI_FIQ_DUMMY72 (GPI_FIQ_START + 72) ++#define INT_GPI_FIQ_DUMMY73 (GPI_FIQ_START + 73) ++#define INT_GPI_FIQ_DUMMY74 (GPI_FIQ_START + 74) ++#define INT_GPI_FIQ_DUMMY75 (GPI_FIQ_START + 75) ++#define GPI_FIQ_END (GPI_FIQ_START + 76) ++#define GPI_FIQ_NUM (GPI_FIQ_END - GPI_FIQ_START) ++ ++#define GPI_IRQ_START 0 ++#define INT_GPI_IRQ_DUMMY00 (GPI_IRQ_START + 0) ++#define INT_GPI_IRQ_DUMMY01 (GPI_IRQ_START + 1) ++#define INT_GPI_IRQ_DUMMY02 (GPI_IRQ_START + 2) ++#define INT_GPI_IRQ_DUMMY03 (GPI_IRQ_START + 3) ++#define INT_GPI_IRQ_DUMMY04 (GPI_IRQ_START + 4) ++#define INT_GPI_IRQ_DUMMY05 (GPI_IRQ_START + 5) ++#define INT_GPI_IRQ_DUMMY06 (GPI_IRQ_START + 6) ++#define INT_GPI_IRQ_DUMMY07 (GPI_IRQ_START + 7) ++#define GPI_IRQ_END (GPI_IRQ_START + 8) ++#define GPI_IRQ_NUM (GPI_IRQ_END - GPI_IRQ_START) ++ +diff --git a/drivers/sstar/include/infinity6/gpio.h b/drivers/sstar/include/infinity6/gpio.h +new file mode 100755 +index 000000000000..4f6e4e4ecaf5 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/gpio.h +@@ -0,0 +1,122 @@ ++/* ++* gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO12 10 ++#define PAD_GPIO13 11 ++#define PAD_GPIO14 12 ++#define PAD_GPIO15 13 ++#define PAD_FUART_RX 14 ++#define PAD_FUART_TX 15 ++#define PAD_FUART_CTS 16 ++#define PAD_FUART_RTS 17 ++#define PAD_I2C0_SCL 18 ++#define PAD_I2C0_SDA 19 ++#define PAD_I2C1_SCL 20 ++#define PAD_I2C1_SDA 21 ++#define PAD_SR_IO00 22 ++#define PAD_SR_IO01 23 ++#define PAD_SR_IO02 24 ++#define PAD_SR_IO03 25 ++#define PAD_SR_IO04 26 ++#define PAD_SR_IO05 27 ++#define PAD_SR_IO06 28 ++#define PAD_SR_IO07 29 ++#define PAD_SR_IO08 30 ++#define PAD_SR_IO09 31 ++#define PAD_SR_IO10 32 ++#define PAD_SR_IO11 33 ++#define PAD_SR_IO12 34 ++#define PAD_SR_IO13 35 ++#define PAD_SR_IO14 36 ++#define PAD_SR_IO15 37 ++#define PAD_SR_IO16 38 ++#define PAD_SR_IO17 39 ++#define PAD_UART0_RX 40 ++#define PAD_UART0_TX 41 ++#define PAD_UART1_RX 42 ++#define PAD_UART1_TX 43 ++#define PAD_SPI0_CZ 44 ++#define PAD_SPI0_CK 45 ++#define PAD_SPI0_DI 46 ++#define PAD_SPI0_DO 47 ++#define PAD_SPI1_CZ 48 ++#define PAD_SPI1_CK 49 ++#define PAD_SPI1_DI 50 ++#define PAD_SPI1_DO 51 ++#define PAD_PWM0 52 ++#define PAD_PWM1 53 ++#define PAD_SD_CLK 54 ++#define PAD_SD_CMD 55 ++#define PAD_SD_D0 56 ++#define PAD_SD_D1 57 ++#define PAD_SD_D2 58 ++#define PAD_SD_D3 59 ++#define PAD_PM_SD_CDZ 60 ++#define PAD_PM_IRIN 61 ++#define PAD_PM_GPIO0 62 ++#define PAD_PM_GPIO1 63 ++#define PAD_PM_GPIO2 64 ++#define PAD_PM_GPIO3 65 ++#define PAD_PM_GPIO4 66 ++#define PAD_PM_GPIO7 67 ++#define PAD_PM_GPIO8 68 ++#define PAD_PM_GPIO9 69 ++#define PAD_PM_SPI_CZ 70 ++#define PAD_PM_SPI_CK 71 ++#define PAD_PM_SPI_DI 72 ++#define PAD_PM_SPI_DO 73 ++#define PAD_PM_SPI_WPZ 74 ++#define PAD_PM_SPI_HLD 75 ++#define PAD_PM_LED0 76 ++#define PAD_PM_LED1 77 ++#define PAD_SAR_GPIO0 78 ++#define PAD_SAR_GPIO1 79 ++#define PAD_SAR_GPIO2 80 ++#define PAD_SAR_GPIO3 81 ++#define PAD_ETH_RN 82 ++#define PAD_ETH_RP 83 ++#define PAD_ETH_TN 84 ++#define PAD_ETH_TP 85 ++#define PAD_USB_DM 86 ++#define PAD_USB_DP 87 ++#define PAD_SD1_IO0 88 ++#define PAD_SD1_IO1 89 ++#define PAD_SD1_IO2 90 ++#define PAD_SD1_IO3 91 ++#define PAD_SD1_IO4 92 ++#define PAD_SD1_IO5 93 ++#define PAD_SD1_IO6 94 ++#define PAD_SD1_IO7 95 ++#define PAD_SD1_IO8 96 ++ ++#define GPIO_NR 97 ++#define PAD_UNKNOWN 0xFFFF ++ ++#endif // #ifndef ___GPIO_H +diff --git a/drivers/sstar/include/infinity6/irqs.h b/drivers/sstar/include/infinity6/irqs.h +new file mode 100755 +index 000000000000..ee18b0dd0ac9 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/irqs.h +@@ -0,0 +1,155 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++#include "gpi-irqs.h" ++#include "pmsleep-irqs.h" ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_DUMMY_03 (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_POWER_0_NG (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_POWER_1_NG (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DUMMY_09 (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_DUMMY_10 (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_DUMMY_11 (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_PM_ERROR_RESP (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_WAKE_ON_LAN (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_PWM_ROUND (GIC_SPI_MS_IRQ_START + 14) //I6 new ++#define INT_IRQ_PWM_HOLD (GIC_SPI_MS_IRQ_START + 15) //I6 new ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_FCIE (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_MHE (GIC_SPI_MS_IRQ_START + 21) //I6 modified ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) //? ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) //? ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) //? ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_CMDQ1 (GIC_SPI_MS_IRQ_START + 52) ++#define INT_IRQ_CMDQ2 (GIC_SPI_MS_IRQ_START + 53) ++#define INT_IRQ_USB_INT_P1 (GIC_SPI_MS_IRQ_START + 54) ++#define INT_IRQ_UHC_INT_P1 (GIC_SPI_MS_IRQ_START + 55) ++#define INT_IRQ_IVE_INT (GIC_SPI_MS_IRQ_START + 56) //still used in dtsi ++#define INT_IRQ_GPI_OUT (GIC_SPI_MS_IRQ_START + 56) //I6 modified ++#define INT_IRQ_VIF (GIC_SPI_MS_IRQ_START + 57) //I6 modified ++#define INT_IRQ_SC1_TOP_INT (GIC_SPI_MS_IRQ_START + 58) ++#define INT_IRQ_SC2_TOP_INT (GIC_SPI_MS_IRQ_START + 59) ++#define INT_IRQ_MOVEDMA (GIC_SPI_MS_IRQ_START + 60) //I6 new ++#define INT_IRQ_BDMA_2 (GIC_SPI_MS_IRQ_START + 61) //I6 new ++#define INT_IRQ_BDMA_3 (GIC_SPI_MS_IRQ_START + 62) //I6 new ++#define INT_IRQ_DIP0 (GIC_SPI_MS_IRQ_START + 63) //I6 new ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity6/mcm_id.h b/drivers/sstar/include/infinity6/mcm_id.h +new file mode 100755 +index 000000000000..6769ad536845 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/mcm_id.h +@@ -0,0 +1,98 @@ ++/* ++* mcm_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_START (0) ++#define MCM_ID_MCU51 (MCM_ID_START+0) ++#define MCM_ID_URDMA (MCM_ID_START+1) ++#define MCM_ID_BDMA (MCM_ID_START+2) ++#define MCM_ID_MFE (MCM_ID_START+3) ++#define MCM_ID_JPE (MCM_ID_START+4) ++#define MCM_ID_BACH (MCM_ID_START+5) ++#define MCM_ID_FILE (MCM_ID_START+6) ++#define MCM_ID_UHC0 (MCM_ID_START+7) ++#define MCM_ID_EMAC (MCM_ID_START+8) ++#define MCM_ID_CMDQ (MCM_ID_START+9) ++#define MCM_ID_ISP_DNR (MCM_ID_START+10) ++#define MCM_ID_ISP_DMA (MCM_ID_START+11) ++#define MCM_ID_GOP0 (MCM_ID_START+12) ++#define MCM_ID_SC_DNR (MCM_ID_START+13) ++#define MCM_ID_SC_DNR_SAD (MCM_ID_START+14) ++#define MCM_ID_SC_CROP (MCM_ID_START+15) ++#define MCM_ID_SC1_FRM (MCM_ID_START+16) ++#define MCM_ID_SC1_SNP (MCM_ID_START+17) ++#define MCM_ID_SC1_DBG (MCM_ID_START+18) ++#define MCM_ID_SC2_FRM (MCM_ID_START+19) ++#define MCM_ID_SC3_FRM (MCM_ID_START+20) ++#define MCM_ID_FCIE (MCM_ID_START+21) ++#define MCM_ID_SDIO (MCM_ID_START+22) ++#define MCM_ID_SC1_SNPI (MCM_ID_START+23) ++#define MCM_ID_SC2_SNPI (MCM_ID_START+24) ++#define MCM_ID_CMDQ1 (MCM_ID_START+25) ++#define MCM_ID_CMDQ2 (MCM_ID_START+26) ++#define MCM_ID_GOP1 (MCM_ID_START+27) ++#define MCM_ID_GOP2 (MCM_ID_START+28) ++#define MCM_ID_UHC1 (MCM_ID_START+29) ++#define MCM_ID_IVE (MCM_ID_START+30) ++#define MCM_ID_VHE (MCM_ID_START+31) ++#define MCM_ID_END (MCM_ID_START+32) ++#define MCM_ID_ALL (256) ++ ++ ++#define OFFSET_MCM_DIG_GP_START (BASE_REG_MCM_DIG_GP_PA+0x0) ++#define OFFSET_MCM_ID_MCU51 (OFFSET_MCM_DIG_GP_START+(0x0<<2) ) ++#define OFFSET_MCM_ID_URDMA (OFFSET_MCM_DIG_GP_START+(0x0<<2)+1) ++#define OFFSET_MCM_ID_BDMA (OFFSET_MCM_DIG_GP_START+(0x1<<2) ) ++ ++ ++#define OFFSET_MCM_SC_GP_START (BASE_REG_MCM_SC_GP_PA+0x10) ++#define OFFSET_MCM_ID_MFE (OFFSET_MCM_SC_GP_START+(0x0<<2) ) ++#define OFFSET_MCM_ID_JPE (OFFSET_MCM_SC_GP_START+(0x0<<2)+1) ++#define OFFSET_MCM_ID_BACH (OFFSET_MCM_SC_GP_START+(0x1<<2) ) ++#define OFFSET_MCM_ID_FILE (OFFSET_MCM_SC_GP_START+(0x1<<2)+1) ++#define OFFSET_MCM_ID_UHC0 (OFFSET_MCM_SC_GP_START+(0x2<<2) ) ++#define OFFSET_MCM_ID_EMAC (OFFSET_MCM_SC_GP_START+(0x2<<2)+1) ++#define OFFSET_MCM_ID_CMDQ (OFFSET_MCM_SC_GP_START+(0x3<<2) ) ++#define OFFSET_MCM_ID_ISP_DNR (OFFSET_MCM_SC_GP_START+(0x3<<2)+1) ++#define OFFSET_MCM_ID_ISP_DMA (OFFSET_MCM_SC_GP_START+(0x4<<2) ) ++#define OFFSET_MCM_ID_GOP0 (OFFSET_MCM_SC_GP_START+(0x4<<2)+1) ++#define OFFSET_MCM_ID_SC_DNR (OFFSET_MCM_SC_GP_START+(0x5<<2) ) ++#define OFFSET_MCM_ID_SC_DNR_SAD (OFFSET_MCM_SC_GP_START+(0x5<<2)+1) ++#define OFFSET_MCM_ID_SC_CROP (OFFSET_MCM_SC_GP_START+(0x6<<2) ) ++#define OFFSET_MCM_ID_SC1_FRM (OFFSET_MCM_SC_GP_START+(0x6<<2)+1) ++#define OFFSET_MCM_ID_SC1_SNP (OFFSET_MCM_SC_GP_START+(0x7<<2) ) ++#define OFFSET_MCM_ID_SC1_DBG (OFFSET_MCM_SC_GP_START+(0x7<<2)+1) ++#define OFFSET_MCM_ID_SC2_FRM (OFFSET_MCM_SC_GP_START+(0x8<<2) ) ++#define OFFSET_MCM_ID_SC3_FRM (OFFSET_MCM_SC_GP_START+(0x8<<2)+1) ++#define OFFSET_MCM_ID_FCIE (OFFSET_MCM_SC_GP_START+(0x9<<2) ) ++#define OFFSET_MCM_ID_SDIO (OFFSET_MCM_SC_GP_START+(0x9<<2)+1) ++#define OFFSET_MCM_ID_SC1_SNPI (OFFSET_MCM_SC_GP_START+(0xA<<2) ) ++#define OFFSET_MCM_ID_SC2_SNPI (OFFSET_MCM_SC_GP_START+(0xA<<2)+1) ++#define OFFSET_MCM_ID_CMDQ1 (OFFSET_MCM_SC_GP_START+(0xB<<2) ) ++#define OFFSET_MCM_ID_CMDQ2 (OFFSET_MCM_SC_GP_START+(0xB<<2)+1) ++#define OFFSET_MCM_ID_GOP1 (OFFSET_MCM_SC_GP_START+(0xD<<2) ) ++#define OFFSET_MCM_ID_GOP2 (OFFSET_MCM_SC_GP_START+(0xD<<2)+1) ++#define OFFSET_MCM_ID_UHC1 (OFFSET_MCM_SC_GP_START+(0xE<<2) ) ++#define OFFSET_MCM_ID_IVE (OFFSET_MCM_SC_GP_START+(0xE<<2)+1) ++ ++ ++#define OFFSET_MCM_VHE_GP_START (BASE_REG_MCM_VHE_GP_PA+0x30) ++#define OFFSET_MCM_ID_VHE (OFFSET_MCM_VHE_GP_START+(0x0<<2) ) ++ ++#endif +diff --git a/drivers/sstar/include/infinity6/mdrv_miu.h b/drivers/sstar/include/infinity6/mdrv_miu.h +new file mode 100755 +index 000000000000..26a8f6fc0348 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/mdrv_miu.h +@@ -0,0 +1,239 @@ ++/* ++* mdrv_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_MIU_H__ ++#define __MDRV_MIU_H__ ++ ++#ifdef CONFIG_64BIT ++ typedef unsigned long phy_addr; // 4 bytes ++#else ++ typedef unsigned long long phy_addr; // 8 bytes ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Enumeration Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ // group 0 ++ MIU_CLIENT_NONE, //none can access ++ MIU_CLIENT_VEN_R, ++ MIU_CLIENT_VEN_W, ++ MIU_CLIENT_DUMMY_G0C3, ++ MIU_CLIENT_JPE_R, ++ MIU_CLIENT_JPE_W, ++ MIU_CLIENT_BACH_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ MIU_CLIENT_DUMMY_G0CE, ++ MIU_CLIENT_DUMMY_G0CF, ++ // group 1 ++ MIU_CLIENT_CMDQ0_R, ++ MIU_CLIENT_ISP_DMA_W, ++ MIU_CLIENT_ISP_DMA_R, ++ MIU_CLIENT_ISP_ROT_R, ++ MIU_CLIENT_ISP_MLOAD_STA, ++ MIU_CLIENT_GOP, ++ MIU_CLIENT_DUMMY_G1C6, ++ MIU_CLIENT_DIP0_R, ++ MIU_CLIENT_DIP0_W, ++ MIU_CLIENT_SC0_FRAME_W, ++ MIU_CLIENT_DUMMY_G1CA, ++ MIU_CLIENT_SC0_DBG_R, ++ MIU_CLIENT_SC1_FRAME_W, ++ MIU_CLIENT_SC2_FRAME_W, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SDIO30_RW, ++ // group 2 ++ MIU_CLIENT_CMDQ1_R, ++ MIU_CLIENT_CMDQ2_R, ++ MIU_CLIENT_DUMMY_G2C2, ++ MIU_CLIENT_ISP_DMAG_RW, ++ MIU_CLIENT_GOP1_R, ++ MIU_CLIENT_GOP2_R, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_DUMMY_G2C7, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_3DNR0_W, ++ MIU_CLIENT_3DNR0_R, ++ MIU_CLIENT_DUMMY_G2CB, ++ MIU_CLIENT_DUMMY_G2CC, ++ MIU_CLIENT_DUMMY_G2CD, ++ MIU_CLIENT_DUMMY_G2CE, ++ MIU_CLIENT_DUMMY_G2CF, ++ // group 3 ++ MIU_CLIENT_DUMMY_G3C0, ++ MIU_CLIENT_DUMMY_G3C1, ++ MIU_CLIENT_DUMMY_G3C2, ++ MIU_CLIENT_DUMMY_G3C3, ++ MIU_CLIENT_DUMMY_G3C4, ++ MIU_CLIENT_DUMMY_G3C5, ++ MIU_CLIENT_DUMMY_G3C6, ++ MIU_CLIENT_DUMMY_G3C7, ++ MIU_CLIENT_DUMMY_G3C8, ++ MIU_CLIENT_DUMMY_G3C9, ++ MIU_CLIENT_DUMMY_G3CA, ++ MIU_CLIENT_DUMMY_G3CB, ++ MIU_CLIENT_DUMMY_G3CC, ++ MIU_CLIENT_DUMMY_G3CD, ++ MIU_CLIENT_DUMMY_G3CE, ++ MIU_CLIENT_DUMMY_G3CF, ++ // group 4 ++ MIU_CLIENT_DUMMY_G4C0, ++ MIU_CLIENT_DUMMY_G4C1, ++ MIU_CLIENT_DUMMY_G4C2, ++ MIU_CLIENT_DUMMY_G4C3, ++ MIU_CLIENT_DUMMY_G4C4, ++ MIU_CLIENT_DUMMY_G4C5, ++ MIU_CLIENT_DUMMY_G4C6, ++ MIU_CLIENT_DUMMY_G4C7, ++ MIU_CLIENT_DUMMY_G4C8, ++ MIU_CLIENT_DUMMY_G4C9, ++ MIU_CLIENT_DUMMY_G4CA, ++ MIU_CLIENT_DUMMY_G4CB, ++ MIU_CLIENT_DUMMY_G4CC, ++ MIU_CLIENT_DUMMY_G4CD, ++ MIU_CLIENT_DUMMY_G4CE, ++ MIU_CLIENT_DUMMY_G4CF, ++ // group 5 ++ MIU_CLIENT_DUMMY_G5C0, ++ MIU_CLIENT_DUMMY_G5C1, ++ MIU_CLIENT_DUMMY_G5C2, ++ MIU_CLIENT_DUMMY_G5C3, ++ MIU_CLIENT_DUMMY_G5C4, ++ MIU_CLIENT_DUMMY_G5C5, ++ MIU_CLIENT_DUMMY_G5C6, ++ MIU_CLIENT_DUMMY_G5C7, ++ MIU_CLIENT_DUMMY_G5C8, ++ MIU_CLIENT_DUMMY_G5C9, ++ MIU_CLIENT_DUMMY_G5CA, ++ MIU_CLIENT_DUMMY_G5CB, ++ MIU_CLIENT_DUMMY_G5CC, ++ MIU_CLIENT_DUMMY_G5CD, ++ MIU_CLIENT_DUMMY_G5CE, ++ MIU_CLIENT_DUMMY_G5CF, ++ // group 6 ++ MIU_CLIENT_DUMMY_G6C0, ++ MIU_CLIENT_DUMMY_G6C1, ++ MIU_CLIENT_DUMMY_G6C2, ++ MIU_CLIENT_DUMMY_G6C3, ++ MIU_CLIENT_DUMMY_G6C4, ++ MIU_CLIENT_DUMMY_G6C5, ++ MIU_CLIENT_DUMMY_G6C6, ++ MIU_CLIENT_DUMMY_G6C7, ++ MIU_CLIENT_DUMMY_G6C8, ++ MIU_CLIENT_DUMMY_G6C9, ++ MIU_CLIENT_DUMMY_G6CA, ++ MIU_CLIENT_DUMMY_G6CB, ++ MIU_CLIENT_DUMMY_G6CC, ++ MIU_CLIENT_DUMMY_G6CD, ++ MIU_CLIENT_DUMMY_G6CE, ++ MIU_CLIENT_DUMMY_G6CF, ++ // group 7 ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_DUMMY_G7C1, ++ MIU_CLIENT_DUMMY_G7C2, ++ MIU_CLIENT_DUMMY_G7C3, ++ MIU_CLIENT_DUMMY_G7C4, ++ MIU_CLIENT_DUMMY_G7C5, ++ MIU_CLIENT_DUMMY_G7C6, ++ MIU_CLIENT_DUMMY_G7C7, ++ MIU_CLIENT_DUMMY_G7C8, ++ MIU_CLIENT_DUMMY_G7C9, ++ MIU_CLIENT_DUMMY_G7CA, ++ MIU_CLIENT_DUMMY_G7CB, ++ MIU_CLIENT_DUMMY_G7CC, ++ MIU_CLIENT_DUMMY_G7CD, ++ MIU_CLIENT_DUMMY_G7CE, ++ MIU_CLIENT_DUMMY_G7CF, ++} eMIUClientID; ++ ++typedef enum ++{ ++ E_MIU_0 = 0, ++ E_MIU_1, ++ E_MIU_2, ++ E_MIU_3, ++ E_MIU_NUM, ++} MIU_ID; ++ ++typedef enum ++{ ++ E_PROTECT_0 = 0, ++ E_PROTECT_1, ++ E_PROTECT_2, ++ E_PROTECT_3, ++ E_PROTECT_4, ++ E_SLIT_0 = 16, ++ E_MIU_PROTECT_NUM, ++} PROTECT_ID; ++ ++//------------------------------------------------------------------------------------------------- ++// Structure Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ unsigned char bHit; ++ unsigned char u8Group; ++ unsigned char u8ClientID; ++ unsigned char u8Block; ++ unsigned int uAddress; ++} MIU_PortectInfo; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ ++unsigned char MDrv_MIU_Init(void); ++unsigned short* MDrv_MIU_GetDefaultClientID_KernelProtect(void); ++unsigned short* MDrv_MIU_GetClientID_KernelProtect(unsigned char u8MiuSel); ++ ++unsigned char MDrv_MIU_Protect( unsigned char u8Blockx, ++ unsigned short *pu8ProtectId, ++ phy_addr u64BusStart, ++ phy_addr u64BusEnd, ++ unsigned char bSetFlag); ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++unsigned char MDrv_MIU_GetProtectInfo(unsigned char u8MiuDev, MIU_PortectInfo *pInfo); ++#endif ++unsigned char MDrv_MIU_Slits(unsigned char u8Blockx, phy_addr u64SlitsStart, phy_addr u65SlitsEnd, unsigned char bSetFlag); ++unsigned char MDrv_MIU_Get_IDEnables_Value(unsigned char u8MiuDev, unsigned char u8Blockx, unsigned char u8ClientIndex); ++unsigned int MDrv_MIU_ProtectDramSize(void); ++int MDrv_MIU_ClientIdToName(unsigned short clientId, char *clientName); ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo); ++ ++#endif // __MDRV_MIU_H__ +diff --git a/drivers/sstar/include/infinity6/mhal_miu.h b/drivers/sstar/include/infinity6/mhal_miu.h +new file mode 100755 +index 000000000000..42f29a9abb78 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/mhal_miu.h +@@ -0,0 +1,95 @@ ++/* ++* mhal_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_MIU_H_ ++#define _MHAL_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_MAX_DEVICE (1) ++#define MIU_MAX_GROUP (8) ++#define MIU_MAX_GP_CLIENT (16) ++#define MIU_MAX_TBL_CLIENT (MIU_MAX_GROUP*MIU_MAX_GP_CLIENT) ++ ++#define MIU_PAGE_SHIFT (13) // Unit for MIU protect (8KB) ++#define MIU_PROTECT_ADDRESS_UNIT (0x20UL) // Unit for MIU hitted address ++#define MIU_MAX_PROTECT_BLOCK (5) ++#define MIU_MAX_PROTECT_ID (16) ++ ++#define IDNUM_KERNELPROTECT (16) ++ ++#ifndef BIT0 ++#define BIT0 0x0001UL ++#define BIT1 0x0002UL ++#define BIT2 0x0004UL ++#define BIT3 0x0008UL ++#define BIT4 0x0010UL ++#define BIT5 0x0020UL ++#define BIT6 0x0040UL ++#define BIT7 0x0080UL ++#define BIT8 0x0100UL ++#define BIT9 0x0200UL ++#define BIT10 0x0400UL ++#define BIT11 0x0800UL ++#define BIT12 0x1000UL ++#define BIT13 0x2000UL ++#define BIT14 0x4000UL ++#define BIT15 0x8000UL ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MIU_BLOCK_0 = 0, ++ E_MIU_BLOCK_1, ++ E_MIU_BLOCK_2, ++ E_MIU_BLOCK_3, ++ E_MIU_BLOCK_4, ++ E_MIU_BLOCK_NUM, ++} MIU_BLOCK_ID; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo_Hal; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuDev, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex); ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void); ++unsigned int HAL_MIU_ProtectDramSize(void); ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName); ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo); ++ ++#endif // _MHAL_MIU_H_ +diff --git a/drivers/sstar/include/infinity6/padmux.h b/drivers/sstar/include/infinity6/padmux.h +new file mode 100755 +index 000000000000..87d86c5fd779 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/padmux.h +@@ -0,0 +1,171 @@ ++/* ++* padmux.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++ ++#define PINMUX_FOR_EJ_MODE_1 0x01 ++#define PINMUX_FOR_EJ_MODE_2 0x02 ++#define PINMUX_FOR_ALLPAD_IN 0x03 ++#define PINMUX_FOR_MIPI_PAD_IN_1 0x04 ++#define PINMUX_FOR_MIPI_PAD_IN_2 0x05 ++#define PINMUX_FOR_MIPI_PAD_IN_3 0x06 ++#define PINMUX_FOR_TEST_IN_MODE_1 0x07 ++#define PINMUX_FOR_TEST_IN_MODE_2 0x08 ++#define PINMUX_FOR_TEST_IN_MODE_3 0x09 ++#define PINMUX_FOR_TEST_OUT_MODE_1 0x0a ++#define PINMUX_FOR_TEST_OUT_MODE_2 0x0b ++#define PINMUX_FOR_TEST_OUT_MODE_3 0x0c ++#define PINMUX_FOR_I2C0_MODE_1 0x0d ++#define PINMUX_FOR_I2C0_MODE_2 0x0e ++#define PINMUX_FOR_I2C0_MODE_3 0x0f ++#define PINMUX_FOR_I2C0_MODE_4 0x10 ++#define PINMUX_FOR_I2C1_MODE_1 0x11 ++#define PINMUX_FOR_I2C1_MODE_2 0x12 ++#define PINMUX_FOR_I2C1_MODE_3 0x13 ++#define PINMUX_FOR_SPI0_MODE_1 0x14 ++#define PINMUX_FOR_SPI0_MODE_2 0x15 ++#define PINMUX_FOR_SPI0_MODE_3 0x16 ++#define PINMUX_FOR_SPI0_MODE_4 0x17 ++#define PINMUX_FOR_SPI1_MODE_1 0x18 ++#define PINMUX_FOR_SPI1_MODE_2 0x19 ++#define PINMUX_FOR_SPI1_MODE_3 0x1a ++#define PINMUX_FOR_SPI1_MODE_4 0x1b ++#define PINMUX_FOR_FUART_MODE_1 0x1c ++#define PINMUX_FOR_FUART_MODE_2 0x1d ++#define PINMUX_FOR_FUART_MODE_3 0x1e ++#define PINMUX_FOR_FUART_MODE_4 0x1f ++#define PINMUX_FOR_FUART_MODE_5 0x20 ++#define PINMUX_FOR_FUART_MODE_6 0x21 ++#define PINMUX_FOR_UART0_MODE_1 0x22 ++#define PINMUX_FOR_UART0_MODE_2 0x23 ++#define PINMUX_FOR_UART0_MODE_3 0x24 ++#define PINMUX_FOR_UART0_MODE_4 0x25 ++#define PINMUX_FOR_UART1_MODE_1 0x26 ++#define PINMUX_FOR_UART1_MODE_2 0x27 ++#define PINMUX_FOR_UART1_MODE_3 0x28 ++#define PINMUX_FOR_UART1_MODE_4 0x29 ++#define PINMUX_FOR_SD_MODE 0x2a ++#define PINMUX_FOR_SDIO_MODE 0x2b ++#define PINMUX_FOR_PWM0_MODE_1 0x2c ++#define PINMUX_FOR_PWM0_MODE_2 0x2d ++#define PINMUX_FOR_PWM0_MODE_3 0x2e ++#define PINMUX_FOR_PWM0_MODE_4 0x2f ++#define PINMUX_FOR_PWM0_MODE_5 0x30 ++#define PINMUX_FOR_PWM1_MODE_1 0x31 ++#define PINMUX_FOR_PWM1_MODE_2 0x32 ++#define PINMUX_FOR_PWM1_MODE_3 0x33 ++#define PINMUX_FOR_PWM1_MODE_4 0x34 ++#define PINMUX_FOR_PWM1_MODE_5 0x35 ++#define PINMUX_FOR_PWM2_MODE_1 0x36 ++#define PINMUX_FOR_PWM2_MODE_2 0x37 ++#define PINMUX_FOR_PWM2_MODE_3 0x38 ++#define PINMUX_FOR_PWM2_MODE_4 0x39 ++#define PINMUX_FOR_PWM2_MODE_5 0x3a ++#define PINMUX_FOR_PWM3_MODE_1 0x3b ++#define PINMUX_FOR_PWM3_MODE_2 0x3c ++#define PINMUX_FOR_PWM3_MODE_3 0x3d ++#define PINMUX_FOR_PWM3_MODE_4 0x3e ++#define PINMUX_FOR_PWM3_MODE_5 0x3f ++#define PINMUX_FOR_PWM4_MODE_1 0x40 ++#define PINMUX_FOR_PWM4_MODE_2 0x41 ++#define PINMUX_FOR_PWM4_MODE_3 0x42 ++#define PINMUX_FOR_PWM4_MODE_4 0x43 ++#define PINMUX_FOR_PWM5_MODE_1 0x44 ++#define PINMUX_FOR_PWM5_MODE_2 0x45 ++#define PINMUX_FOR_PWM5_MODE_3 0x46 ++#define PINMUX_FOR_PWM5_MODE_4 0x47 ++#define PINMUX_FOR_PWM6_MODE_1 0x48 ++#define PINMUX_FOR_PWM6_MODE_2 0x49 ++#define PINMUX_FOR_PWM6_MODE_3 0x4a ++#define PINMUX_FOR_PWM6_MODE_4 0x4b ++#define PINMUX_FOR_PWM7_MODE_1 0x4c ++#define PINMUX_FOR_PWM7_MODE_2 0x4d ++#define PINMUX_FOR_PWM7_MODE_3 0x4e ++#define PINMUX_FOR_PWM7_MODE_4 0x4f ++#define PINMUX_FOR_PWM8_MODE_1 0x50 ++#define PINMUX_FOR_PWM8_MODE_2 0x51 ++#define PINMUX_FOR_PWM8_MODE_3 0x52 ++#define PINMUX_FOR_PWM8_MODE_4 0x53 ++#define PINMUX_FOR_PWM9_MODE_1 0x54 ++#define PINMUX_FOR_PWM9_MODE_2 0x55 ++#define PINMUX_FOR_PWM9_MODE_3 0x56 ++#define PINMUX_FOR_PWM9_MODE_4 0x57 ++#define PINMUX_FOR_PWM10_MODE_1 0x58 ++#define PINMUX_FOR_PWM10_MODE_2 0x59 ++#define PINMUX_FOR_PWM10_MODE_3 0x5a ++#define PINMUX_FOR_PWM10_MODE_4 0x5b ++#define PINMUX_FOR_SR_MODE_1 0x5c ++#define PINMUX_FOR_SR_MODE_2 0x5d ++#define PINMUX_FOR_SR_MODE_3 0x5e ++#define PINMUX_FOR_SR_MODE_4 0x5f ++#define PINMUX_FOR_SR_MCLK_MODE 0x60 ++#define PINMUX_FOR_SR_PDN_MODE_1 0x61 ++#define PINMUX_FOR_SR_PDN_MODE_2 0x62 ++#define PINMUX_FOR_SR_RST_MODE_1 0x63 ++#define PINMUX_FOR_SR_RST_MODE_2 0x64 ++#define PINMUX_FOR_SR_HVSYNC_MODE 0x65 ++#define PINMUX_FOR_SR_PCK_MODE 0x66 ++#define PINMUX_FOR_ETH_MODE 0x67 ++#define PINMUX_FOR_I2S_MODE_1 0x68 ++#define PINMUX_FOR_I2S_MODE_2 0x69 ++#define PINMUX_FOR_I2S_MODE_3 0x6a ++#define PINMUX_FOR_DMIC_MODE_1 0x6b ++#define PINMUX_FOR_DMIC_MODE_2 0x6c ++#define PINMUX_FOR_DMIC_MODE_3 0x6d ++#define PINMUX_FOR_TTL_MODE_1 0x6e ++#define PINMUX_FOR_TTL_MODE_2 0x6f ++#define PINMUX_FOR_CCIR_MODE_1 0x70 ++#define PINMUX_FOR_CCIR_MODE_2 0x71 ++#define PINMUX_FOR_CCIR_MODE_3 0x72 ++ ++#define PINMUX_FOR_PM_SPI_MODE 0x73 ++#define PINMUX_FOR_PM_SPIWPN_MODE 0x74 ++#define PINMUX_FOR_PM_SPIHOLDN_MODE 0x75 ++#define PINMUX_FOR_PM_SPICSZ1_MODE 0x76 ++#define PINMUX_FOR_PM_SPICSZ2_MODE 0x77 ++#define PINMUX_FOR_PM_PWM0_MODE_1 0x78 ++#define PINMUX_FOR_PM_PWM0_MODE_2 0x79 ++#define PINMUX_FOR_PM_PWM1_MODE_1 0x7a ++#define PINMUX_FOR_PM_PWM1_MODE_2 0x7b ++#define PINMUX_FOR_PM_PWM2_MODE_1 0x7c ++#define PINMUX_FOR_PM_PWM2_MODE_2 0x7d ++#define PINMUX_FOR_PM_PWM3_MODE_1 0x7e ++#define PINMUX_FOR_PM_PWM3_MODE_2 0x7f ++#define PINMUX_FOR_PM_PWM4_MODE 0x80 ++#define PINMUX_FOR_PM_PWM5_MODE 0x81 ++#define PINMUX_FOR_PM_PWM8_MODE 0x82 ++#define PINMUX_FOR_PM_PWM9_MODE 0x83 ++#define PINMUX_FOR_PM_PWM10_MODE 0x84 ++#define PINMUX_FOR_PM_UART1_MODE 0x85 ++#define PINMUX_FOR_PM_VID_MODE_1 0x86 ++#define PINMUX_FOR_PM_VID_MODE_2 0x87 ++#define PINMUX_FOR_PM_VID_MODE_3 0x88 ++#define PINMUX_FOR_PM_SD_CDZ_MODE 0x89 ++#define PINMUX_FOR_PM_LED_MODE 0x8a ++#define PINMUX_FOR_PM_TTL_MODE_1 0x8b ++#define PINMUX_FOR_PM_TTL_MODE_2 0x8c ++#define PINMUX_FOR_PM_IRIN_MODE 0x8d ++ ++#define PINMUX_FOR_SAR_MODE 0x8e ++#define PINMUX_FOR_USB_MODE 0x8f ++ ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++#endif // ___PADMUX_H +diff --git a/drivers/sstar/include/infinity6/pmsleep-irqs.h b/drivers/sstar/include/infinity6/pmsleep-irqs.h +new file mode 100755 +index 000000000000..8e1106aeb733 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/pmsleep-irqs.h +@@ -0,0 +1,130 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_DUMMY_5 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_DUMMY_6 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_DUMMY_10 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_DUMMY_11 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_DUMMY_12 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_DUMMY_13 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_DUMMY_14 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_DUMMY_15 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_DUMMY_16 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_DUMMY_17 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_DUMMY_18 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_DUMMY_19 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_DUMMY_22 (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_DUMMY_23 (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_32 (PMSLEEP_FIQ_START + 32) ++#define INT_PMSLEEP_DUMMY_33 (PMSLEEP_FIQ_START + 33) ++#define INT_PMSLEEP_DUMMY_34 (PMSLEEP_FIQ_START + 34) ++#define INT_PMSLEEP_DUMMY_35 (PMSLEEP_FIQ_START + 35) ++#define INT_PMSLEEP_DUMMY_36 (PMSLEEP_FIQ_START + 36) ++#define INT_PMSLEEP_DUMMY_37 (PMSLEEP_FIQ_START + 37) ++#define INT_PMSLEEP_DUMMY_38 (PMSLEEP_FIQ_START + 38) ++#define INT_PMSLEEP_DUMMY_39 (PMSLEEP_FIQ_START + 39) ++#define INT_PMSLEEP_DUMMY_40 (PMSLEEP_FIQ_START + 40) ++#define INT_PMSLEEP_DUMMY_41 (PMSLEEP_FIQ_START + 41) ++#define INT_PMSLEEP_DUMMY_42 (PMSLEEP_FIQ_START + 42) ++#define INT_PMSLEEP_DUMMY_43 (PMSLEEP_FIQ_START + 43) ++#define INT_PMSLEEP_DUMMY_44 (PMSLEEP_FIQ_START + 44) ++#define INT_PMSLEEP_DUMMY_45 (PMSLEEP_FIQ_START + 45) ++#define INT_PMSLEEP_DUMMY_46 (PMSLEEP_FIQ_START + 46) ++#define INT_PMSLEEP_DUMMY_47 (PMSLEEP_FIQ_START + 47) ++#define INT_PMSLEEP_DUMMY_48 (PMSLEEP_FIQ_START + 48) ++#define INT_PMSLEEP_DUMMY_49 (PMSLEEP_FIQ_START + 49) ++#define INT_PMSLEEP_DUMMY_50 (PMSLEEP_FIQ_START + 50) ++#define INT_PMSLEEP_DUMMY_51 (PMSLEEP_FIQ_START + 51) ++#define INT_PMSLEEP_DUMMY_52 (PMSLEEP_FIQ_START + 52) ++#define INT_PMSLEEP_DUMMY_53 (PMSLEEP_FIQ_START + 53) ++#define INT_PMSLEEP_DUMMY_54 (PMSLEEP_FIQ_START + 54) ++#define INT_PMSLEEP_DUMMY_55 (PMSLEEP_FIQ_START + 55) ++#define INT_PMSLEEP_DUMMY_56 (PMSLEEP_FIQ_START + 56) ++#define INT_PMSLEEP_DUMMY_57 (PMSLEEP_FIQ_START + 57) ++#define INT_PMSLEEP_DUMMY_58 (PMSLEEP_FIQ_START + 58) ++#define INT_PMSLEEP_DUMMY_59 (PMSLEEP_FIQ_START + 59) ++#define INT_PMSLEEP_DUMMY_60 (PMSLEEP_FIQ_START + 60) ++#define INT_PMSLEEP_DUMMY_61 (PMSLEEP_FIQ_START + 61) ++#define INT_PMSLEEP_DUMMY_62 (PMSLEEP_FIQ_START + 62) ++#define INT_PMSLEEP_DUMMY_63 (PMSLEEP_FIQ_START + 63) ++#define INT_PMSLEEP_DUMMY_64 (PMSLEEP_FIQ_START + 64) ++#define INT_PMSLEEP_DUMMY_65 (PMSLEEP_FIQ_START + 65) ++#define INT_PMSLEEP_DUMMY_66 (PMSLEEP_FIQ_START + 66) ++#define INT_PMSLEEP_DUMMY_67 (PMSLEEP_FIQ_START + 67) ++#define INT_PMSLEEP_SPI_WPZ (PMSLEEP_FIQ_START + 68) ++#define INT_PMSLEEP_SPI_HLD (PMSLEEP_FIQ_START + 69) ++#define INT_PMSLEEP_DUMMY_70 (PMSLEEP_FIQ_START + 70) ++#define INT_PMSLEEP_SD_CDZ (PMSLEEP_FIQ_START + 71) ++#define INT_PMSLEEP_DUMMY_72 (PMSLEEP_FIQ_START + 72) ++#define INT_PMSLEEP_DUMMY_73 (PMSLEEP_FIQ_START + 73) ++#define INT_PMSLEEP_LED0 (PMSLEEP_FIQ_START + 74) ++#define INT_PMSLEEP_LED1 (PMSLEEP_FIQ_START + 75) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 76) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_CEC (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_SAR_GPIO (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_RTCPWC_ALARM (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) +diff --git a/drivers/sstar/include/infinity6/regMIU.h b/drivers/sstar/include/infinity6/regMIU.h +new file mode 100755 +index 000000000000..36e367cb6a9d +--- /dev/null ++++ b/drivers/sstar/include/infinity6/regMIU.h +@@ -0,0 +1,135 @@ ++/* ++* regMIU.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_MIU_H_ ++#define _REG_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) ++#define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) ++ ++#define MIU_REG_BASE (0x1200UL) ++#define MIU1_REG_BASE (0x0D00UL) ++#define MIU2_REG_BASE (0x62000UL) ++#define PM_REG_BASE (0x1E00UL) ++#define MIU_ATOP_BASE (0x1000UL) ++#define MIU1_ATOP_BASE (0x0B00UL) ++#define MIU2_ATOP_BASE (0x62100UL) ++#define CHIP_TOP_BASE (0x1E00UL) ++#define MIU_ARB_REG_BASE (0x1100UL) ++#define MIU1_ARB_REG_BASE (0x0C00UL) ++#define MIU2_ARB_REG_BASE (0x62300UL) ++ ++#define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3UL) ++#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++#define MIU_PROTECT_DDR_32MB (0x50UL) ++#define MIU_PROTECT_DDR_64MB (0x60UL) ++#define MIU_PROTECT_DDR_128MB (0x70UL) ++#define MIU_PROTECT_DDR_256MB (0x80UL) ++#define MIU_PROTECT_DDR_512MB (0x90UL) ++#define MIU_PROTECT_DDR_1024MB (0xA0UL) ++#define MIU_PROTECT_DDR_2048MB (0xB0UL) ++ ++#define MIU_PROTECT0_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT1_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT2_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT3_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT4_EN (MIU_ARB_REG_BASE+0xDEUL) ++#define MIU_PROTECT_ID0 (MIU_REG_BASE+0x2EUL) ++#define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20UL) ++#define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22UL) ++#define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24UL) ++#define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26UL) ++#define MIU_PROTECT4_ID_ENABLE (MIU_ARB_REG_BASE+0xDC) ++#define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT1_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT2_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT3_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT4_MSB (MIU_REG_BASE+0xB2UL) ++#define MIU_PROTECT0_START (MIU_REG_BASE+0xC0UL) ++#define MIU_PROTECT0_END (MIU_REG_BASE+0xC2UL) ++#define MIU_PROTECT1_START (MIU_REG_BASE+0xC4UL) ++#define MIU_PROTECT1_END (MIU_REG_BASE+0xC6UL) ++#define MIU_PROTECT2_START (MIU_REG_BASE+0xC8UL) ++#define MIU_PROTECT2_END (MIU_REG_BASE+0xCAUL) ++#define MIU_PROTECT3_START (MIU_REG_BASE+0xCCUL) ++#define MIU_PROTECT3_END (MIU_REG_BASE+0xCEUL) ++#define MIU_PROTECT4_START (MIU_REG_BASE+0x72UL) ++#define MIU_PROTECT4_END (MIU_REG_BASE+0x92UL) ++#define REG_MIU_PROTECT_LOADDR (0x6DUL << 1) //0xDE ++#define REG_MIU_PROTECT_HIADDR (0x6EUL << 1) //0xDE ++#define REG_MIU_PROTECT_STATUS (0x6FUL << 1) //0xDE ++ ++// MIU selection registers ++#define REG_MIU_SEL0 (MIU_REG_BASE+0xf0UL) //0x12F0 ++#define REG_MIU_SEL1 (MIU_REG_BASE+0xf2UL) //0x12F1 ++#define REG_MIU_SEL2 (MIU_REG_BASE+0xf4UL) //0x12F2 ++#define REG_MIU_SEL3 (MIU_REG_BASE+0xf6UL) //0x12F3 ++#define REG_MIU_SELX(x) (0xF0UL+x*2) ++ ++// MIU1 ++#define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3UL) ++#define MIU1_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++ ++#define MIU1_PROTECT0_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT1_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT2_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT3_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT4_EN (MIU1_ARB_REG_BASE+0xDEUL) ++#define MIU1_PROTECT_ID0 (MIU1_REG_BASE+0x2EUL) ++#define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20UL) ++#define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22UL) ++#define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24UL) ++#define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26UL) ++#define MIU1_PROTECT4_ID_ENABLE (MIU1_ARB_REG_BASE+0xDC) ++#define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT1_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT2_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT3_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT4_MSB (MIU1_REG_BASE+0xB2UL) ++#define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0UL) ++#define MIU1_PROTECT0_END (MIU1_REG_BASE+0xC2UL) ++#define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4UL) ++#define MIU1_PROTECT1_END (MIU1_REG_BASE+0xC6UL) ++#define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8UL) ++#define MIU1_PROTECT2_END (MIU1_REG_BASE+0xCAUL) ++#define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCCUL) ++#define MIU1_PROTECT3_END (MIU1_REG_BASE+0xCEUL) ++#define MIU1_PROTECT4_START (MIU1_REG_BASE+0x72UL) ++#define MIU1_PROTECT4_END (MIU1_REG_BASE+0x92UL) ++ ++#define REG_MIU_I64_MODE (BIT7) ++#define REG_MIU_INIT_DONE (BIT15) ++ ++// Protection Status ++#define REG_MIU_PROTECT_LOG_CLR (BIT0) ++#define REG_MIU_PROTECT_IRQ_MASK (BIT1) ++#define REG_MIU_PROTECT_HIT_FALG (BIT4) ++#define REG_MIU_PROTECT_HIT_ID 14:8 ++#define REG_MIU_PROTECT_HIT_NO 7:5 ++ ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET (MIU_REG_BASE+0xD8UL) ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_BIT (BIT11) ++ ++#endif // _REG_MIU_H_ +diff --git a/drivers/sstar/include/infinity6/reg_clks.h b/drivers/sstar/include/infinity6/reg_clks.h +new file mode 100755 +index 000000000000..aea7f0c63eff +--- /dev/null ++++ b/drivers/sstar/include/infinity6/reg_clks.h +@@ -0,0 +1,463 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I6/iNfinity6_Clock_Table_1022_SW.xls */ ++/* REG FILENAME: I6/iNfinity6_reg_CLKGEN.xls, I6/iNfinity6_reg_pm_sleep.xls, I6/iNfinity6_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_CKG_SNR0_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR0_OFFSET (0) ++ ++#define REG_CKG_SNR1_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR1_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PWM_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_BT656_0_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_BT656_0_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FCLK2_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SD_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity6/registers.h b/drivers/sstar/include/infinity6/registers.h +new file mode 100755 +index 000000000000..78d1029d9202 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/registers.h +@@ -0,0 +1,258 @@ ++/* ++* registers.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define REG_ADDR(addr) (*((volatile U16*)(0xFD200000 + (addr << 1)))) ++ ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0xFFFFFFFF ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++ ++#define MIU0_BASE ARM_MIU0_BUS_BASE ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x18000 ++ // #define IMI_SIZE (0x20000) // 128K ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0600) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3000) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++ ++#define BASE_REG_BDMA0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100200) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100220) ++#define BASE_REG_BDMA2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100240) ++#define BASE_REG_BDMA3_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100260) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_MOVDMA_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100B00) ++#define BASE_REG_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101000) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_MIUPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103100) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++#define BASE_REG_GPI_INT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103D00) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I6_PACKAGE_UNKNOWN =0x00, ++ MS_I6_PACKAGE_QFN_DDR2_32MB, ++ MS_I6_PACKAGE_QFN_DDR2_64MB, ++ MS_I6_PACKAGE_BGA_128MB, ++ MS_I6_PACKAGE_BGA_256MB, ++ MS_I6_PACKAGE_QFN_DDR3_128MB, ++ MS_I6_PACKAGE_EXTENDED=0x30, ++ MS_I6_PACKAGE_DDR3_1866_128MB =0x30, ++ MS_I6_PACKAGE_DDR3_1866_256MB, ++ MS_I6_PACKAGE_FPGA_128MB =0x90, ++} MS_I6_PACKAGE_TYPE; ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity6/tsensor.h b/drivers/sstar/include/infinity6/tsensor.h +new file mode 100755 +index 000000000000..30e40f7d6d1b +--- /dev/null ++++ b/drivers/sstar/include/infinity6/tsensor.h +@@ -0,0 +1,23 @@ ++/* ++* tsensor.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __CPU_FREQ_H ++#define __CPU_FREQ_H ++ ++int ms_get_temp(void); ++ ++#endif //__CPU_FREQ_H +diff --git a/drivers/sstar/include/infinity6/voltage_ctrl_demander.h b/drivers/sstar/include/infinity6/voltage_ctrl_demander.h +new file mode 100755 +index 000000000000..d04460e64eb8 +--- /dev/null ++++ b/drivers/sstar/include/infinity6/voltage_ctrl_demander.h +@@ -0,0 +1,36 @@ ++/* ++* voltage_ctrl.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __VOLTAGE_CTRL_DEMANDER_H ++#define __VOLTAGE_CTRL_DEMANDER_H ++ ++#define FOREACH_DEMANDER(DEMANDER) \ ++ DEMANDER(VOLTAGE_DEMANDER_CPUFREQ) \ ++ DEMANDER(VOLTAGE_DEMANDER_TEMPERATURE) \ ++ DEMANDER(VOLTAGE_DEMANDER_VENC) \ ++ DEMANDER(VOLTAGE_DEMANDER_MIU) \ ++ DEMANDER(VOLTAGE_DEMANDER_USER) \ ++ DEMANDER(VOLTAGE_DEMANDER_MAX) \ ++ ++#define GENERATE_ENUM(ENUM) ENUM, ++#define GENERATE_STRING(STRING) #STRING, ++ ++typedef enum { ++ FOREACH_DEMANDER(GENERATE_ENUM) ++} VOLTAGE_DEMANDER_E; ++ ++#endif //__VOLTAGE_CTRL_DEMANDER_H +diff --git a/drivers/sstar/include/infinity6b0/Kconfig b/drivers/sstar/include/infinity6b0/Kconfig +new file mode 100755 +index 000000000000..4a9a5970388c +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/Kconfig +@@ -0,0 +1,14 @@ ++source "drivers/sstar/emmc/Kconfig" ++source "drivers/sstar/sdmmc/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/ircut/Kconfig" ++source "drivers/sstar/rtc/Kconfig" ++source "drivers/sstar/crypto/Kconfig" ++source "drivers/sstar/cpufreq/Kconfig" ++source "drivers/sstar/ive/Kconfig" ++source "drivers/sstar/notify/Kconfig" ++source "drivers/sstar/isrcb/Kconfig" ++source "drivers/sstar/miu/Kconfig" ++source "drivers/sstar/bdma/Kconfig" ++source "drivers/sstar/movedma/Kconfig" ++ +diff --git a/drivers/sstar/include/infinity6b0/camclk.h b/drivers/sstar/include/infinity6b0/camclk.h +new file mode 100644 +index 000000000000..479f803f8276 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/camclk.h +@@ -0,0 +1,203 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_mpll_345m 3 ++#define CAMCLK_upll_384m 4 ++#define CAMCLK_upll_320m 5 ++#define CAMCLK_mpll_288m 6 ++#define CAMCLK_utmi_240m 7 ++#define CAMCLK_mpll_216m 8 ++#define CAMCLK_utmi_192m 9 ++#define CAMCLK_mpll_172m 10 ++#define CAMCLK_utmi_160m 11 ++#define CAMCLK_mpll_123m 12 ++#define CAMCLK_mpll_86m 13 ++#define CAMCLK_mpll_288m_div2 14 ++#define CAMCLK_mpll_288m_div4 15 ++#define CAMCLK_mpll_288m_div8 16 ++#define CAMCLK_mpll_216m_div2 17 ++#define CAMCLK_mpll_216m_div4 18 ++#define CAMCLK_mpll_216m_div8 19 ++#define CAMCLK_mpll_123m_div2 20 ++#define CAMCLK_mpll_86m_div2 21 ++#define CAMCLK_mpll_86m_div4 22 ++#define CAMCLK_mpll_86m_div16 23 ++#define CAMCLK_utmi_192m_div4 24 ++#define CAMCLK_utmi_160m_div4 25 ++#define CAMCLK_utmi_160m_div5 26 ++#define CAMCLK_utmi_160m_div8 27 ++#define CAMCLK_xtali_12m 28 ++#define CAMCLK_xtali_12m_div8 29 ++#define CAMCLK_xtali_12m_div16 30 ++#define CAMCLK_xtali_12m_div40 31 ++#define CAMCLK_xtali_12m_div64 32 ++#define CAMCLK_xtali_12m_div128 33 ++#define CAMCLK_xtali_24m 34 ++#define CAMCLK_RTC_CLK_32K 35 ++#define CAMCLK_pm_riu_w_clk_in 36 ++#define CAMCLK_lpll_clk_div2 37 ++#define CAMCLK_lpll_clk_div4 38 ++#define CAMCLK_lpll_clk_div8 39 ++#define CAMCLK_armpll_37p125m 40 ++#define CAMCLK_riu_w_clk_in 41 ++#define CAMCLK_riu_w_clk_top 42 ++#define CAMCLK_riu_w_clk_sc_gp 43 ++#define CAMCLK_riu_w_clk_vhe_gp 44 ++#define CAMCLK_riu_w_clk_hemcu_gp 45 ++#define CAMCLK_riu_w_clk_mipi_if_gp 46 ++#define CAMCLK_riu_w_clk_mcu_if_gp 47 ++#define CAMCLK_miu_p 48 ++#define CAMCLK_mspi0_p 49 ++#define CAMCLK_mspi1_p 50 ++#define CAMCLK_miu_vhe_gp_p 51 ++#define CAMCLK_miu_sc_gp_p 52 ++#define CAMCLK_miu2x_p 53 ++#define CAMCLK_mcu_p 54 ++#define CAMCLK_mcu_pm_p 55 ++#define CAMCLK_isp_p 56 ++#define CAMCLK_fclk1_p 57 ++#define CAMCLK_fclk2_p 58 ++#define CAMCLK_sdio_p 59 ++#define CAMCLK_tck_buf 60 ++#define CAMCLK_pad2isp_sr_pclk 61 ++#define CAMCLK_ccir_in_clk 62 ++#define CAMCLK_eth_buf 63 ++#define CAMCLK_rmii_buf 64 ++#define CAMCLK_emac_testrx125_in_lan 65 ++#define CAMCLK_miu_ff 66 ++#define CAMCLK_miu_sc_gp 67 ++#define CAMCLK_miu_vhe_gp 68 ++#define CAMCLK_miu_dig 69 ++#define CAMCLK_miu_xd2miu 70 ++#define CAMCLK_miu_urdma 71 ++#define CAMCLK_miu_bdma 72 ++#define CAMCLK_miu_vhe 73 ++#define CAMCLK_miu_mfeh 74 ++#define CAMCLK_miu_mfe 75 ++#define CAMCLK_miu_jpe1 76 ++#define CAMCLK_miu_jpe0 77 ++#define CAMCLK_miu_bach 78 ++#define CAMCLK_miu_file 79 ++#define CAMCLK_miu_uhc0 80 ++#define CAMCLK_miu_emac 81 ++#define CAMCLK_miu_cmdq 82 ++#define CAMCLK_miu_isp_dnr 83 ++#define CAMCLK_miu_isp_rot 84 ++#define CAMCLK_miu_isp_dma 85 ++#define CAMCLK_miu_isp_sta 86 ++#define CAMCLK_miu_gop 87 ++#define CAMCLK_miu_sc_dnr 88 ++#define CAMCLK_miu_sc_dnr_sad 89 ++#define CAMCLK_miu_sc_crop 90 ++#define CAMCLK_miu_sc1_frm 91 ++#define CAMCLK_miu_sc1_snp 92 ++#define CAMCLK_miu_sc1_snpi 93 ++#define CAMCLK_miu_sc1_dbg 94 ++#define CAMCLK_miu_sc2_frm 95 ++#define CAMCLK_miu_sc2_snpi 96 ++#define CAMCLK_miu_sc3_frm 97 ++#define CAMCLK_miu_fcie 98 ++#define CAMCLK_miu_sdio 99 ++#define CAMCLK_miu_ive 100 ++#define CAMCLK_riu 101 ++#define CAMCLK_riu_nogating 102 ++#define CAMCLK_riu_sc_gp 103 ++#define CAMCLK_riu_vhe_gp 104 ++#define CAMCLK_riu_hemcu_gp 105 ++#define CAMCLK_riu_mipi_gp 106 ++#define CAMCLK_riu_mcu_if 107 ++#define CAMCLK_miu2x 108 ++#define CAMCLK_axi2x 109 ++#define CAMCLK_tck 110 ++#define CAMCLK_imi 111 ++#define CAMCLK_gop0 112 ++#define CAMCLK_gop1 113 ++#define CAMCLK_gop2 114 ++#define CAMCLK_mpll_144m 115 ++#define CAMCLK_mpll_144m_div2 116 ++#define CAMCLK_mpll_144m_div4 117 ++#define CAMCLK_xtali_12m_div2 118 ++#define CAMCLK_xtali_12m_div4 119 ++#define CAMCLK_xtali_12m_div12 120 ++#define CAMCLK_rtc_32k 121 ++#define CAMCLK_rtc_32k_div4 122 ++#define CAMCLK_live_pm 123 ++#define CAMCLK_riu_pm 124 ++#define CAMCLK_miupll_clk 125 ++#define CAMCLK_ddrpll_clk 126 ++#define CAMCLK_lpll_clk 127 ++#define CAMCLK_cpupll_clk 128 ++#define CAMCLK_utmi 129 ++#define CAMCLK_upll 130 ++#define CAMCLK_fuart0_synth_out 131 ++#define CAMCLK_csi2_mac_p 132 ++#define CAMCLK_miu 133 ++#define CAMCLK_ddr_syn 134 ++#define CAMCLK_miu_rec 135 ++#define CAMCLK_mcu 136 ++#define CAMCLK_riubrdg 137 ++#define CAMCLK_bdma 138 ++#define CAMCLK_spi 139 ++#define CAMCLK_uart0 140 ++#define CAMCLK_uart1 141 ++#define CAMCLK_fuart0_synth_in 142 ++#define CAMCLK_fuart 143 ++#define CAMCLK_mspi0 144 ++#define CAMCLK_mspi1 145 ++#define CAMCLK_mspi 146 ++#define CAMCLK_miic0 147 ++#define CAMCLK_miic1 148 ++#define CAMCLK_bist 149 ++#define CAMCLK_pwr_ctl 150 ++#define CAMCLK_xtali 151 ++#define CAMCLK_live 152 ++#define CAMCLK_sr_mclk 153 ++#define CAMCLK_bist_vhe_gp 154 ++#define CAMCLK_vhe 155 ++#define CAMCLK_vhe_vpu 156 ++#define CAMCLK_xtali_sc_gp 157 ++#define CAMCLK_bist_sc_gp 158 ++#define CAMCLK_emac_ahb 159 ++#define CAMCLK_jpe 160 ++#define CAMCLK_aesdma 161 ++#define CAMCLK_sdio 162 ++#define CAMCLK_sd 163 ++#define CAMCLK_isp 164 ++#define CAMCLK_fclk1 165 ++#define CAMCLK_fclk2 166 ++#define CAMCLK_odclk 167 ++#define CAMCLK_dip 168 ++#define CAMCLK_ive 169 ++#define CAMCLK_nlm 170 ++#define CAMCLK_emac_tx 171 ++#define CAMCLK_emac_rx 172 ++#define CAMCLK_emac_tx_ref 173 ++#define CAMCLK_emac_rx_ref 174 ++#define CAMCLK_hemcu_216m 175 ++#define CAMCLK_csi_mac 176 ++#define CAMCLK_mac_lptx 177 ++#define CAMCLK_ns 178 ++#define CAMCLK_mcu_pm 179 ++#define CAMCLK_spi_pm 180 ++#define CAMCLK_pm_sleep 181 ++#define CAMCLK_sar 182 ++#define CAMCLK_rtc 183 ++#define CAMCLK_ir 184 ++#endif +diff --git a/drivers/sstar/include/infinity6b0/gpi-irqs.h b/drivers/sstar/include/infinity6b0/gpi-irqs.h +new file mode 100755 +index 000000000000..82bff20dba31 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/gpi-irqs.h +@@ -0,0 +1,114 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++#define GPI_FIQ_START 0 ++#define INT_GPI_FIQ_PAD_UART1_RX (GPI_FIQ_START + 0) ++#define INT_GPI_FIQ_PAD_UART1_TX (GPI_FIQ_START + 1) ++#define INT_GPI_FIQ_PAD_UART0_RX (GPI_FIQ_START + 2) ++#define INT_GPI_FIQ_PAD_UART0_TX (GPI_FIQ_START + 3) ++#define INT_GPI_FIQ_PAD_SR_IO00 (GPI_FIQ_START + 4) ++#define INT_GPI_FIQ_PAD_SR_IO01 (GPI_FIQ_START + 5) ++#define INT_GPI_FIQ_PAD_SR_IO02 (GPI_FIQ_START + 6) ++#define INT_GPI_FIQ_PAD_SR_IO03 (GPI_FIQ_START + 7) ++#define INT_GPI_FIQ_PAD_SR_IO04 (GPI_FIQ_START + 8) ++#define INT_GPI_FIQ_PAD_SR_IO05 (GPI_FIQ_START + 9) ++#define INT_GPI_FIQ_PAD_SR_IO06 (GPI_FIQ_START + 10) ++#define INT_GPI_FIQ_PAD_SR_IO07 (GPI_FIQ_START + 11) ++#define INT_GPI_FIQ_PAD_SR_IO08 (GPI_FIQ_START + 12) ++#define INT_GPI_FIQ_PAD_SR_IO09 (GPI_FIQ_START + 13) ++#define INT_GPI_FIQ_PAD_SR_IO10 (GPI_FIQ_START + 14) ++#define INT_GPI_FIQ_PAD_SR_IO11 (GPI_FIQ_START + 15) ++#define INT_GPI_FIQ_PAD_SR_IO12 (GPI_FIQ_START + 16) ++#define INT_GPI_FIQ_PAD_SR_IO13 (GPI_FIQ_START + 17) ++#define INT_GPI_FIQ_PAD_SR_IO14 (GPI_FIQ_START + 18) ++#define INT_GPI_FIQ_PAD_SR_IO15 (GPI_FIQ_START + 19) ++#define INT_GPI_FIQ_PAD_SR_IO16 (GPI_FIQ_START + 20) ++#define INT_GPI_FIQ_PAD_SR_IO17 (GPI_FIQ_START + 21) ++#define INT_GPI_FIQ_PAD_SPI1_CZ (GPI_FIQ_START + 22) ++#define INT_GPI_FIQ_PAD_SPI1_CK (GPI_FIQ_START + 23) ++#define INT_GPI_FIQ_PAD_SPI1_DI (GPI_FIQ_START + 24) ++#define INT_GPI_FIQ_PAD_SPI1_DO (GPI_FIQ_START + 25) ++#define INT_GPI_FIQ_PAD_SPI0_CZ (GPI_FIQ_START + 26) ++#define INT_GPI_FIQ_PAD_SPI0_CK (GPI_FIQ_START + 27) ++#define INT_GPI_FIQ_PAD_SPI0_DI (GPI_FIQ_START + 28) ++#define INT_GPI_FIQ_PAD_SPI0_DO (GPI_FIQ_START + 29) ++#define INT_GPI_FIQ_PAD_SD_CLK (GPI_FIQ_START + 30) ++#define INT_GPI_FIQ_PAD_SD_CMD (GPI_FIQ_START + 31) ++#define INT_GPI_FIQ_PAD_SD_D0 (GPI_FIQ_START + 32) ++#define INT_GPI_FIQ_PAD_SD_D1 (GPI_FIQ_START + 33) ++#define INT_GPI_FIQ_PAD_SD_D2 (GPI_FIQ_START + 34) ++#define INT_GPI_FIQ_PAD_SD_D3 (GPI_FIQ_START + 35) ++#define INT_GPI_FIQ_PAD_SD1_IO0 (GPI_FIQ_START + 36) ++#define INT_GPI_FIQ_PAD_SD1_IO1 (GPI_FIQ_START + 37) ++#define INT_GPI_FIQ_PAD_SD1_IO2 (GPI_FIQ_START + 38) ++#define INT_GPI_FIQ_PAD_SD1_IO3 (GPI_FIQ_START + 39) ++#define INT_GPI_FIQ_PAD_SD1_IO4 (GPI_FIQ_START + 40) ++#define INT_GPI_FIQ_PAD_SD1_IO5 (GPI_FIQ_START + 41) ++#define INT_GPI_FIQ_PAD_SD1_IO6 (GPI_FIQ_START + 42) ++#define INT_GPI_FIQ_PAD_SD1_IO7 (GPI_FIQ_START + 43) ++#define INT_GPI_FIQ_PAD_SD1_IO8 (GPI_FIQ_START + 44) ++#define INT_GPI_FIQ_PAD_PWM0 (GPI_FIQ_START + 45) ++#define INT_GPI_FIQ_PAD_PWM1 (GPI_FIQ_START + 46) ++#define INT_GPI_FIQ_PAD_I2C1_SCL (GPI_FIQ_START + 47) ++#define INT_GPI_FIQ_PAD_I2C1_SDA (GPI_FIQ_START + 48) ++#define INT_GPI_FIQ_PAD_I2C0_SCL (GPI_FIQ_START + 49) ++#define INT_GPI_FIQ_PAD_I2C0_SDA (GPI_FIQ_START + 50) ++#define INT_GPI_FIQ_PAD_GPIO0 (GPI_FIQ_START + 51) ++#define INT_GPI_FIQ_PAD_GPIO1 (GPI_FIQ_START + 52) ++#define INT_GPI_FIQ_PAD_GPIO2 (GPI_FIQ_START + 53) ++#define INT_GPI_FIQ_PAD_GPIO3 (GPI_FIQ_START + 54) ++#define INT_GPI_FIQ_PAD_GPIO4 (GPI_FIQ_START + 55) ++#define INT_GPI_FIQ_PAD_GPIO5 (GPI_FIQ_START + 56) ++#define INT_GPI_FIQ_PAD_GPIO6 (GPI_FIQ_START + 57) ++#define INT_GPI_FIQ_PAD_GPIO7 (GPI_FIQ_START + 58) ++#define INT_GPI_FIQ_PAD_GPIO8 (GPI_FIQ_START + 59) ++#define INT_GPI_FIQ_PAD_GPIO9 (GPI_FIQ_START + 60) ++#define INT_GPI_FIQ_DUMMY61 (GPI_FIQ_START + 61) ++#define INT_GPI_FIQ_DUMMY62 (GPI_FIQ_START + 62) ++#define INT_GPI_FIQ_PAD_GPIO12 (GPI_FIQ_START + 63) ++#define INT_GPI_FIQ_PAD_GPIO13 (GPI_FIQ_START + 64) ++#define INT_GPI_FIQ_PAD_GPIO14 (GPI_FIQ_START + 65) ++#define INT_GPI_FIQ_PAD_GPIO15 (GPI_FIQ_START + 66) ++#define INT_GPI_FIQ_PAD_FUART_RX (GPI_FIQ_START + 67) ++#define INT_GPI_FIQ_PAD_FUART_TX (GPI_FIQ_START + 68) ++#define INT_GPI_FIQ_PAD_FUART_CTS (GPI_FIQ_START + 69) ++#define INT_GPI_FIQ_PAD_FUART_RTS (GPI_FIQ_START + 70) ++#define INT_GPI_FIQ_DUMMY71 (GPI_FIQ_START + 71) ++#define INT_GPI_FIQ_DUMMY72 (GPI_FIQ_START + 72) ++#define INT_GPI_FIQ_DUMMY73 (GPI_FIQ_START + 73) ++#define INT_GPI_FIQ_DUMMY74 (GPI_FIQ_START + 74) ++#define INT_GPI_FIQ_DUMMY75 (GPI_FIQ_START + 75) ++#define GPI_FIQ_END (GPI_FIQ_START + 76) ++#define GPI_FIQ_NUM (GPI_FIQ_END - GPI_FIQ_START) ++ ++#define GPI_IRQ_START 0 ++#define INT_GPI_IRQ_DUMMY00 (GPI_IRQ_START + 0) ++#define INT_GPI_IRQ_DUMMY01 (GPI_IRQ_START + 1) ++#define INT_GPI_IRQ_DUMMY02 (GPI_IRQ_START + 2) ++#define INT_GPI_IRQ_DUMMY03 (GPI_IRQ_START + 3) ++#define INT_GPI_IRQ_DUMMY04 (GPI_IRQ_START + 4) ++#define INT_GPI_IRQ_DUMMY05 (GPI_IRQ_START + 5) ++#define INT_GPI_IRQ_DUMMY06 (GPI_IRQ_START + 6) ++#define INT_GPI_IRQ_DUMMY07 (GPI_IRQ_START + 7) ++#define GPI_IRQ_END (GPI_IRQ_START + 8) ++#define GPI_IRQ_NUM (GPI_IRQ_END - GPI_IRQ_START) ++ +diff --git a/drivers/sstar/include/infinity6b0/gpio.h b/drivers/sstar/include/infinity6b0/gpio.h +new file mode 100755 +index 000000000000..4f6e4e4ecaf5 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/gpio.h +@@ -0,0 +1,122 @@ ++/* ++* gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO12 10 ++#define PAD_GPIO13 11 ++#define PAD_GPIO14 12 ++#define PAD_GPIO15 13 ++#define PAD_FUART_RX 14 ++#define PAD_FUART_TX 15 ++#define PAD_FUART_CTS 16 ++#define PAD_FUART_RTS 17 ++#define PAD_I2C0_SCL 18 ++#define PAD_I2C0_SDA 19 ++#define PAD_I2C1_SCL 20 ++#define PAD_I2C1_SDA 21 ++#define PAD_SR_IO00 22 ++#define PAD_SR_IO01 23 ++#define PAD_SR_IO02 24 ++#define PAD_SR_IO03 25 ++#define PAD_SR_IO04 26 ++#define PAD_SR_IO05 27 ++#define PAD_SR_IO06 28 ++#define PAD_SR_IO07 29 ++#define PAD_SR_IO08 30 ++#define PAD_SR_IO09 31 ++#define PAD_SR_IO10 32 ++#define PAD_SR_IO11 33 ++#define PAD_SR_IO12 34 ++#define PAD_SR_IO13 35 ++#define PAD_SR_IO14 36 ++#define PAD_SR_IO15 37 ++#define PAD_SR_IO16 38 ++#define PAD_SR_IO17 39 ++#define PAD_UART0_RX 40 ++#define PAD_UART0_TX 41 ++#define PAD_UART1_RX 42 ++#define PAD_UART1_TX 43 ++#define PAD_SPI0_CZ 44 ++#define PAD_SPI0_CK 45 ++#define PAD_SPI0_DI 46 ++#define PAD_SPI0_DO 47 ++#define PAD_SPI1_CZ 48 ++#define PAD_SPI1_CK 49 ++#define PAD_SPI1_DI 50 ++#define PAD_SPI1_DO 51 ++#define PAD_PWM0 52 ++#define PAD_PWM1 53 ++#define PAD_SD_CLK 54 ++#define PAD_SD_CMD 55 ++#define PAD_SD_D0 56 ++#define PAD_SD_D1 57 ++#define PAD_SD_D2 58 ++#define PAD_SD_D3 59 ++#define PAD_PM_SD_CDZ 60 ++#define PAD_PM_IRIN 61 ++#define PAD_PM_GPIO0 62 ++#define PAD_PM_GPIO1 63 ++#define PAD_PM_GPIO2 64 ++#define PAD_PM_GPIO3 65 ++#define PAD_PM_GPIO4 66 ++#define PAD_PM_GPIO7 67 ++#define PAD_PM_GPIO8 68 ++#define PAD_PM_GPIO9 69 ++#define PAD_PM_SPI_CZ 70 ++#define PAD_PM_SPI_CK 71 ++#define PAD_PM_SPI_DI 72 ++#define PAD_PM_SPI_DO 73 ++#define PAD_PM_SPI_WPZ 74 ++#define PAD_PM_SPI_HLD 75 ++#define PAD_PM_LED0 76 ++#define PAD_PM_LED1 77 ++#define PAD_SAR_GPIO0 78 ++#define PAD_SAR_GPIO1 79 ++#define PAD_SAR_GPIO2 80 ++#define PAD_SAR_GPIO3 81 ++#define PAD_ETH_RN 82 ++#define PAD_ETH_RP 83 ++#define PAD_ETH_TN 84 ++#define PAD_ETH_TP 85 ++#define PAD_USB_DM 86 ++#define PAD_USB_DP 87 ++#define PAD_SD1_IO0 88 ++#define PAD_SD1_IO1 89 ++#define PAD_SD1_IO2 90 ++#define PAD_SD1_IO3 91 ++#define PAD_SD1_IO4 92 ++#define PAD_SD1_IO5 93 ++#define PAD_SD1_IO6 94 ++#define PAD_SD1_IO7 95 ++#define PAD_SD1_IO8 96 ++ ++#define GPIO_NR 97 ++#define PAD_UNKNOWN 0xFFFF ++ ++#endif // #ifndef ___GPIO_H +diff --git a/drivers/sstar/include/infinity6b0/irqs.h b/drivers/sstar/include/infinity6b0/irqs.h +new file mode 100755 +index 000000000000..15aac5177650 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/irqs.h +@@ -0,0 +1,154 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++#include "gpi-irqs.h" ++#include "pmsleep-irqs.h" ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_DUMMY_03 (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_POWER_0_NG (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_POWER_1_NG (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DUMMY_09 (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_DUMMY_10 (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_DUMMY_11 (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_PM_ERROR_RESP (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_WAKE_ON_LAN (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_DUMMY_14 (GIC_SPI_MS_IRQ_START + 14) ++#define INT_IRQ_PWM_INT_ALL (GIC_SPI_MS_IRQ_START + 15) //I6E,I6B0 new ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_FCIE (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_MHE (GIC_SPI_MS_IRQ_START + 21) //I6 modified ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) //? ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) //? ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) //? ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_DUMMY_52 (GIC_SPI_MS_IRQ_START + 52) ++#define INT_IRQ_IVE_INT (GIC_SPI_MS_IRQ_START + 53) ++#define INT_IRQ_USB_INT_P1 (GIC_SPI_MS_IRQ_START + 54) ++#define INT_IRQ_UHC_INT_P1 (GIC_SPI_MS_IRQ_START + 55) ++#define INT_IRQ_GPI_OUT (GIC_SPI_MS_IRQ_START + 56) //I6 modified ++#define INT_IRQ_VIF (GIC_SPI_MS_IRQ_START + 57) //I6 modified ++#define INT_IRQ_SC1_TOP_INT (GIC_SPI_MS_IRQ_START + 58) ++#define INT_IRQ_SC2_TOP_INT (GIC_SPI_MS_IRQ_START + 59) ++#define INT_IRQ_MOVEDMA (GIC_SPI_MS_IRQ_START + 60) //I6 new ++#define INT_IRQ_BDMA_2 (GIC_SPI_MS_IRQ_START + 61) //I6 new ++#define INT_IRQ_BDMA_3 (GIC_SPI_MS_IRQ_START + 62) //I6 new ++#define INT_IRQ_DIP0 (GIC_SPI_MS_IRQ_START + 63) //I6 new ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity6b0/mcm_id.h b/drivers/sstar/include/infinity6b0/mcm_id.h +new file mode 100755 +index 000000000000..6769ad536845 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/mcm_id.h +@@ -0,0 +1,98 @@ ++/* ++* mcm_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_START (0) ++#define MCM_ID_MCU51 (MCM_ID_START+0) ++#define MCM_ID_URDMA (MCM_ID_START+1) ++#define MCM_ID_BDMA (MCM_ID_START+2) ++#define MCM_ID_MFE (MCM_ID_START+3) ++#define MCM_ID_JPE (MCM_ID_START+4) ++#define MCM_ID_BACH (MCM_ID_START+5) ++#define MCM_ID_FILE (MCM_ID_START+6) ++#define MCM_ID_UHC0 (MCM_ID_START+7) ++#define MCM_ID_EMAC (MCM_ID_START+8) ++#define MCM_ID_CMDQ (MCM_ID_START+9) ++#define MCM_ID_ISP_DNR (MCM_ID_START+10) ++#define MCM_ID_ISP_DMA (MCM_ID_START+11) ++#define MCM_ID_GOP0 (MCM_ID_START+12) ++#define MCM_ID_SC_DNR (MCM_ID_START+13) ++#define MCM_ID_SC_DNR_SAD (MCM_ID_START+14) ++#define MCM_ID_SC_CROP (MCM_ID_START+15) ++#define MCM_ID_SC1_FRM (MCM_ID_START+16) ++#define MCM_ID_SC1_SNP (MCM_ID_START+17) ++#define MCM_ID_SC1_DBG (MCM_ID_START+18) ++#define MCM_ID_SC2_FRM (MCM_ID_START+19) ++#define MCM_ID_SC3_FRM (MCM_ID_START+20) ++#define MCM_ID_FCIE (MCM_ID_START+21) ++#define MCM_ID_SDIO (MCM_ID_START+22) ++#define MCM_ID_SC1_SNPI (MCM_ID_START+23) ++#define MCM_ID_SC2_SNPI (MCM_ID_START+24) ++#define MCM_ID_CMDQ1 (MCM_ID_START+25) ++#define MCM_ID_CMDQ2 (MCM_ID_START+26) ++#define MCM_ID_GOP1 (MCM_ID_START+27) ++#define MCM_ID_GOP2 (MCM_ID_START+28) ++#define MCM_ID_UHC1 (MCM_ID_START+29) ++#define MCM_ID_IVE (MCM_ID_START+30) ++#define MCM_ID_VHE (MCM_ID_START+31) ++#define MCM_ID_END (MCM_ID_START+32) ++#define MCM_ID_ALL (256) ++ ++ ++#define OFFSET_MCM_DIG_GP_START (BASE_REG_MCM_DIG_GP_PA+0x0) ++#define OFFSET_MCM_ID_MCU51 (OFFSET_MCM_DIG_GP_START+(0x0<<2) ) ++#define OFFSET_MCM_ID_URDMA (OFFSET_MCM_DIG_GP_START+(0x0<<2)+1) ++#define OFFSET_MCM_ID_BDMA (OFFSET_MCM_DIG_GP_START+(0x1<<2) ) ++ ++ ++#define OFFSET_MCM_SC_GP_START (BASE_REG_MCM_SC_GP_PA+0x10) ++#define OFFSET_MCM_ID_MFE (OFFSET_MCM_SC_GP_START+(0x0<<2) ) ++#define OFFSET_MCM_ID_JPE (OFFSET_MCM_SC_GP_START+(0x0<<2)+1) ++#define OFFSET_MCM_ID_BACH (OFFSET_MCM_SC_GP_START+(0x1<<2) ) ++#define OFFSET_MCM_ID_FILE (OFFSET_MCM_SC_GP_START+(0x1<<2)+1) ++#define OFFSET_MCM_ID_UHC0 (OFFSET_MCM_SC_GP_START+(0x2<<2) ) ++#define OFFSET_MCM_ID_EMAC (OFFSET_MCM_SC_GP_START+(0x2<<2)+1) ++#define OFFSET_MCM_ID_CMDQ (OFFSET_MCM_SC_GP_START+(0x3<<2) ) ++#define OFFSET_MCM_ID_ISP_DNR (OFFSET_MCM_SC_GP_START+(0x3<<2)+1) ++#define OFFSET_MCM_ID_ISP_DMA (OFFSET_MCM_SC_GP_START+(0x4<<2) ) ++#define OFFSET_MCM_ID_GOP0 (OFFSET_MCM_SC_GP_START+(0x4<<2)+1) ++#define OFFSET_MCM_ID_SC_DNR (OFFSET_MCM_SC_GP_START+(0x5<<2) ) ++#define OFFSET_MCM_ID_SC_DNR_SAD (OFFSET_MCM_SC_GP_START+(0x5<<2)+1) ++#define OFFSET_MCM_ID_SC_CROP (OFFSET_MCM_SC_GP_START+(0x6<<2) ) ++#define OFFSET_MCM_ID_SC1_FRM (OFFSET_MCM_SC_GP_START+(0x6<<2)+1) ++#define OFFSET_MCM_ID_SC1_SNP (OFFSET_MCM_SC_GP_START+(0x7<<2) ) ++#define OFFSET_MCM_ID_SC1_DBG (OFFSET_MCM_SC_GP_START+(0x7<<2)+1) ++#define OFFSET_MCM_ID_SC2_FRM (OFFSET_MCM_SC_GP_START+(0x8<<2) ) ++#define OFFSET_MCM_ID_SC3_FRM (OFFSET_MCM_SC_GP_START+(0x8<<2)+1) ++#define OFFSET_MCM_ID_FCIE (OFFSET_MCM_SC_GP_START+(0x9<<2) ) ++#define OFFSET_MCM_ID_SDIO (OFFSET_MCM_SC_GP_START+(0x9<<2)+1) ++#define OFFSET_MCM_ID_SC1_SNPI (OFFSET_MCM_SC_GP_START+(0xA<<2) ) ++#define OFFSET_MCM_ID_SC2_SNPI (OFFSET_MCM_SC_GP_START+(0xA<<2)+1) ++#define OFFSET_MCM_ID_CMDQ1 (OFFSET_MCM_SC_GP_START+(0xB<<2) ) ++#define OFFSET_MCM_ID_CMDQ2 (OFFSET_MCM_SC_GP_START+(0xB<<2)+1) ++#define OFFSET_MCM_ID_GOP1 (OFFSET_MCM_SC_GP_START+(0xD<<2) ) ++#define OFFSET_MCM_ID_GOP2 (OFFSET_MCM_SC_GP_START+(0xD<<2)+1) ++#define OFFSET_MCM_ID_UHC1 (OFFSET_MCM_SC_GP_START+(0xE<<2) ) ++#define OFFSET_MCM_ID_IVE (OFFSET_MCM_SC_GP_START+(0xE<<2)+1) ++ ++ ++#define OFFSET_MCM_VHE_GP_START (BASE_REG_MCM_VHE_GP_PA+0x30) ++#define OFFSET_MCM_ID_VHE (OFFSET_MCM_VHE_GP_START+(0x0<<2) ) ++ ++#endif +diff --git a/drivers/sstar/include/infinity6b0/mdrv_miu.h b/drivers/sstar/include/infinity6b0/mdrv_miu.h +new file mode 100755 +index 000000000000..0c9adfdc87c4 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/mdrv_miu.h +@@ -0,0 +1,239 @@ ++/* ++* mdrv_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_MIU_H__ ++#define __MDRV_MIU_H__ ++ ++#ifdef CONFIG_64BIT ++ typedef unsigned long phy_addr; // 4 bytes ++#else ++ typedef unsigned long long phy_addr; // 8 bytes ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Enumeration Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ // group 0 ++ MIU_CLIENT_NONE, //none can access ++ MIU_CLIENT_VEN_R, ++ MIU_CLIENT_VEN_W, ++ MIU_CLIENT_DUMMY_G0C3, ++ MIU_CLIENT_JPE_R, ++ MIU_CLIENT_JPE_W, ++ MIU_CLIENT_BACH_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ MIU_CLIENT_GOP3_R, ++ MIU_CLIENT_DUMMY_G0CF, ++ // group 1 ++ MIU_CLIENT_CMDQ_R, ++ MIU_CLIENT_ISP_DMA_W, ++ MIU_CLIENT_ISP_DMA_R, ++ MIU_CLIENT_ISP_ROT_R, ++ MIU_CLIENT_ISP_MLOAD_STA, ++ MIU_CLIENT_GOP, ++ MIU_CLIENT_DUMMY_G1C6, ++ MIU_CLIENT_DIP0_R, ++ MIU_CLIENT_DIP0_W, ++ MIU_CLIENT_SC0_FRAME_W, ++ MIU_CLIENT_DUMMY_G1CA, ++ MIU_CLIENT_SC0_DBG_R, ++ MIU_CLIENT_SC1_FRAME_W, ++ MIU_CLIENT_SC2_FRAME_W, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SDIO30_RW, ++ // group 2 ++ MIU_CLIENT_DUMMY_G2C0, ++ MIU_CLIENT_DUMMY_G2C1, ++ MIU_CLIENT_DUMMY_G2C2, ++ MIU_CLIENT_DUMMY_G2C3, ++ MIU_CLIENT_GOP1_R, ++ MIU_CLIENT_GOP2_R, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_IVE_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_3DNR0_W, ++ MIU_CLIENT_3DNR0_R, ++ MIU_CLIENT_DUMMY_G2CB, ++ MIU_CLIENT_DUMMY_G2CC, ++ MIU_CLIENT_DUMMY_G2CD, ++ MIU_CLIENT_DUMMY_G2CE, ++ MIU_CLIENT_DUMMY_G2CF, ++ // group 3 ++ MIU_CLIENT_DUMMY_G3C0, ++ MIU_CLIENT_DUMMY_G3C1, ++ MIU_CLIENT_DUMMY_G3C2, ++ MIU_CLIENT_DUMMY_G3C3, ++ MIU_CLIENT_DUMMY_G3C4, ++ MIU_CLIENT_DUMMY_G3C5, ++ MIU_CLIENT_DUMMY_G3C6, ++ MIU_CLIENT_DUMMY_G3C7, ++ MIU_CLIENT_DUMMY_G3C8, ++ MIU_CLIENT_DUMMY_G3C9, ++ MIU_CLIENT_DUMMY_G3CA, ++ MIU_CLIENT_DUMMY_G3CB, ++ MIU_CLIENT_DUMMY_G3CC, ++ MIU_CLIENT_DUMMY_G3CD, ++ MIU_CLIENT_DUMMY_G3CE, ++ MIU_CLIENT_DUMMY_G3CF, ++ // group 4 ++ MIU_CLIENT_DUMMY_G4C0, ++ MIU_CLIENT_DUMMY_G4C1, ++ MIU_CLIENT_DUMMY_G4C2, ++ MIU_CLIENT_DUMMY_G4C3, ++ MIU_CLIENT_DUMMY_G4C4, ++ MIU_CLIENT_DUMMY_G4C5, ++ MIU_CLIENT_DUMMY_G4C6, ++ MIU_CLIENT_DUMMY_G4C7, ++ MIU_CLIENT_DUMMY_G4C8, ++ MIU_CLIENT_DUMMY_G4C9, ++ MIU_CLIENT_DUMMY_G4CA, ++ MIU_CLIENT_DUMMY_G4CB, ++ MIU_CLIENT_DUMMY_G4CC, ++ MIU_CLIENT_DUMMY_G4CD, ++ MIU_CLIENT_DUMMY_G4CE, ++ MIU_CLIENT_DUMMY_G4CF, ++ // group 5 ++ MIU_CLIENT_DUMMY_G5C0, ++ MIU_CLIENT_DUMMY_G5C1, ++ MIU_CLIENT_DUMMY_G5C2, ++ MIU_CLIENT_DUMMY_G5C3, ++ MIU_CLIENT_DUMMY_G5C4, ++ MIU_CLIENT_DUMMY_G5C5, ++ MIU_CLIENT_DUMMY_G5C6, ++ MIU_CLIENT_DUMMY_G5C7, ++ MIU_CLIENT_DUMMY_G5C8, ++ MIU_CLIENT_DUMMY_G5C9, ++ MIU_CLIENT_DUMMY_G5CA, ++ MIU_CLIENT_DUMMY_G5CB, ++ MIU_CLIENT_DUMMY_G5CC, ++ MIU_CLIENT_DUMMY_G5CD, ++ MIU_CLIENT_DUMMY_G5CE, ++ MIU_CLIENT_DUMMY_G5CF, ++ // group 6 ++ MIU_CLIENT_DUMMY_G6C0, ++ MIU_CLIENT_DUMMY_G6C1, ++ MIU_CLIENT_DUMMY_G6C2, ++ MIU_CLIENT_DUMMY_G6C3, ++ MIU_CLIENT_DUMMY_G6C4, ++ MIU_CLIENT_DUMMY_G6C5, ++ MIU_CLIENT_DUMMY_G6C6, ++ MIU_CLIENT_DUMMY_G6C7, ++ MIU_CLIENT_DUMMY_G6C8, ++ MIU_CLIENT_DUMMY_G6C9, ++ MIU_CLIENT_DUMMY_G6CA, ++ MIU_CLIENT_DUMMY_G6CB, ++ MIU_CLIENT_DUMMY_G6CC, ++ MIU_CLIENT_DUMMY_G6CD, ++ MIU_CLIENT_DUMMY_G6CE, ++ MIU_CLIENT_DUMMY_G6CF, ++ // group 7 ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_DUMMY_G7C1, ++ MIU_CLIENT_DUMMY_G7C2, ++ MIU_CLIENT_DUMMY_G7C3, ++ MIU_CLIENT_DUMMY_G7C4, ++ MIU_CLIENT_DUMMY_G7C5, ++ MIU_CLIENT_DUMMY_G7C6, ++ MIU_CLIENT_DUMMY_G7C7, ++ MIU_CLIENT_DUMMY_G7C8, ++ MIU_CLIENT_DUMMY_G7C9, ++ MIU_CLIENT_DUMMY_G7CA, ++ MIU_CLIENT_DUMMY_G7CB, ++ MIU_CLIENT_DUMMY_G7CC, ++ MIU_CLIENT_DUMMY_G7CD, ++ MIU_CLIENT_DUMMY_G7CE, ++ MIU_CLIENT_DUMMY_G7CF, ++} eMIUClientID; ++ ++typedef enum ++{ ++ E_MIU_0 = 0, ++ E_MIU_1, ++ E_MIU_2, ++ E_MIU_3, ++ E_MIU_NUM, ++} MIU_ID; ++ ++typedef enum ++{ ++ E_PROTECT_0 = 0, ++ E_PROTECT_1, ++ E_PROTECT_2, ++ E_PROTECT_3, ++ E_PROTECT_4, ++ E_SLIT_0 = 16, ++ E_MIU_PROTECT_NUM, ++} PROTECT_ID; ++ ++//------------------------------------------------------------------------------------------------- ++// Structure Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ unsigned char bHit; ++ unsigned char u8Group; ++ unsigned char u8ClientID; ++ unsigned char u8Block; ++ unsigned int uAddress; ++} MIU_PortectInfo; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ ++unsigned char MDrv_MIU_Init(void); ++unsigned short* MDrv_MIU_GetDefaultClientID_KernelProtect(void); ++unsigned short* MDrv_MIU_GetClientID_KernelProtect(unsigned char u8MiuSel); ++ ++unsigned char MDrv_MIU_Protect( unsigned char u8Blockx, ++ unsigned short *pu8ProtectId, ++ phy_addr u64BusStart, ++ phy_addr u64BusEnd, ++ unsigned char bSetFlag); ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++unsigned char MDrv_MIU_GetProtectInfo(unsigned char u8MiuDev, MIU_PortectInfo *pInfo); ++#endif ++unsigned char MDrv_MIU_Slits(unsigned char u8Blockx, phy_addr u64SlitsStart, phy_addr u65SlitsEnd, unsigned char bSetFlag); ++unsigned char MDrv_MIU_Get_IDEnables_Value(unsigned char u8MiuDev, unsigned char u8Blockx, unsigned char u8ClientIndex); ++unsigned int MDrv_MIU_ProtectDramSize(void); ++int MDrv_MIU_ClientIdToName(unsigned short clientId, char *clientName); ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo); ++ ++#endif // __MDRV_MIU_H__ +diff --git a/drivers/sstar/include/infinity6b0/mhal_miu.h b/drivers/sstar/include/infinity6b0/mhal_miu.h +new file mode 100755 +index 000000000000..42f29a9abb78 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/mhal_miu.h +@@ -0,0 +1,95 @@ ++/* ++* mhal_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_MIU_H_ ++#define _MHAL_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_MAX_DEVICE (1) ++#define MIU_MAX_GROUP (8) ++#define MIU_MAX_GP_CLIENT (16) ++#define MIU_MAX_TBL_CLIENT (MIU_MAX_GROUP*MIU_MAX_GP_CLIENT) ++ ++#define MIU_PAGE_SHIFT (13) // Unit for MIU protect (8KB) ++#define MIU_PROTECT_ADDRESS_UNIT (0x20UL) // Unit for MIU hitted address ++#define MIU_MAX_PROTECT_BLOCK (5) ++#define MIU_MAX_PROTECT_ID (16) ++ ++#define IDNUM_KERNELPROTECT (16) ++ ++#ifndef BIT0 ++#define BIT0 0x0001UL ++#define BIT1 0x0002UL ++#define BIT2 0x0004UL ++#define BIT3 0x0008UL ++#define BIT4 0x0010UL ++#define BIT5 0x0020UL ++#define BIT6 0x0040UL ++#define BIT7 0x0080UL ++#define BIT8 0x0100UL ++#define BIT9 0x0200UL ++#define BIT10 0x0400UL ++#define BIT11 0x0800UL ++#define BIT12 0x1000UL ++#define BIT13 0x2000UL ++#define BIT14 0x4000UL ++#define BIT15 0x8000UL ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MIU_BLOCK_0 = 0, ++ E_MIU_BLOCK_1, ++ E_MIU_BLOCK_2, ++ E_MIU_BLOCK_3, ++ E_MIU_BLOCK_4, ++ E_MIU_BLOCK_NUM, ++} MIU_BLOCK_ID; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo_Hal; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuDev, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex); ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void); ++unsigned int HAL_MIU_ProtectDramSize(void); ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName); ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo); ++ ++#endif // _MHAL_MIU_H_ +diff --git a/drivers/sstar/include/infinity6b0/padmux.h b/drivers/sstar/include/infinity6b0/padmux.h +new file mode 100755 +index 000000000000..87d86c5fd779 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/padmux.h +@@ -0,0 +1,171 @@ ++/* ++* padmux.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++ ++#define PINMUX_FOR_EJ_MODE_1 0x01 ++#define PINMUX_FOR_EJ_MODE_2 0x02 ++#define PINMUX_FOR_ALLPAD_IN 0x03 ++#define PINMUX_FOR_MIPI_PAD_IN_1 0x04 ++#define PINMUX_FOR_MIPI_PAD_IN_2 0x05 ++#define PINMUX_FOR_MIPI_PAD_IN_3 0x06 ++#define PINMUX_FOR_TEST_IN_MODE_1 0x07 ++#define PINMUX_FOR_TEST_IN_MODE_2 0x08 ++#define PINMUX_FOR_TEST_IN_MODE_3 0x09 ++#define PINMUX_FOR_TEST_OUT_MODE_1 0x0a ++#define PINMUX_FOR_TEST_OUT_MODE_2 0x0b ++#define PINMUX_FOR_TEST_OUT_MODE_3 0x0c ++#define PINMUX_FOR_I2C0_MODE_1 0x0d ++#define PINMUX_FOR_I2C0_MODE_2 0x0e ++#define PINMUX_FOR_I2C0_MODE_3 0x0f ++#define PINMUX_FOR_I2C0_MODE_4 0x10 ++#define PINMUX_FOR_I2C1_MODE_1 0x11 ++#define PINMUX_FOR_I2C1_MODE_2 0x12 ++#define PINMUX_FOR_I2C1_MODE_3 0x13 ++#define PINMUX_FOR_SPI0_MODE_1 0x14 ++#define PINMUX_FOR_SPI0_MODE_2 0x15 ++#define PINMUX_FOR_SPI0_MODE_3 0x16 ++#define PINMUX_FOR_SPI0_MODE_4 0x17 ++#define PINMUX_FOR_SPI1_MODE_1 0x18 ++#define PINMUX_FOR_SPI1_MODE_2 0x19 ++#define PINMUX_FOR_SPI1_MODE_3 0x1a ++#define PINMUX_FOR_SPI1_MODE_4 0x1b ++#define PINMUX_FOR_FUART_MODE_1 0x1c ++#define PINMUX_FOR_FUART_MODE_2 0x1d ++#define PINMUX_FOR_FUART_MODE_3 0x1e ++#define PINMUX_FOR_FUART_MODE_4 0x1f ++#define PINMUX_FOR_FUART_MODE_5 0x20 ++#define PINMUX_FOR_FUART_MODE_6 0x21 ++#define PINMUX_FOR_UART0_MODE_1 0x22 ++#define PINMUX_FOR_UART0_MODE_2 0x23 ++#define PINMUX_FOR_UART0_MODE_3 0x24 ++#define PINMUX_FOR_UART0_MODE_4 0x25 ++#define PINMUX_FOR_UART1_MODE_1 0x26 ++#define PINMUX_FOR_UART1_MODE_2 0x27 ++#define PINMUX_FOR_UART1_MODE_3 0x28 ++#define PINMUX_FOR_UART1_MODE_4 0x29 ++#define PINMUX_FOR_SD_MODE 0x2a ++#define PINMUX_FOR_SDIO_MODE 0x2b ++#define PINMUX_FOR_PWM0_MODE_1 0x2c ++#define PINMUX_FOR_PWM0_MODE_2 0x2d ++#define PINMUX_FOR_PWM0_MODE_3 0x2e ++#define PINMUX_FOR_PWM0_MODE_4 0x2f ++#define PINMUX_FOR_PWM0_MODE_5 0x30 ++#define PINMUX_FOR_PWM1_MODE_1 0x31 ++#define PINMUX_FOR_PWM1_MODE_2 0x32 ++#define PINMUX_FOR_PWM1_MODE_3 0x33 ++#define PINMUX_FOR_PWM1_MODE_4 0x34 ++#define PINMUX_FOR_PWM1_MODE_5 0x35 ++#define PINMUX_FOR_PWM2_MODE_1 0x36 ++#define PINMUX_FOR_PWM2_MODE_2 0x37 ++#define PINMUX_FOR_PWM2_MODE_3 0x38 ++#define PINMUX_FOR_PWM2_MODE_4 0x39 ++#define PINMUX_FOR_PWM2_MODE_5 0x3a ++#define PINMUX_FOR_PWM3_MODE_1 0x3b ++#define PINMUX_FOR_PWM3_MODE_2 0x3c ++#define PINMUX_FOR_PWM3_MODE_3 0x3d ++#define PINMUX_FOR_PWM3_MODE_4 0x3e ++#define PINMUX_FOR_PWM3_MODE_5 0x3f ++#define PINMUX_FOR_PWM4_MODE_1 0x40 ++#define PINMUX_FOR_PWM4_MODE_2 0x41 ++#define PINMUX_FOR_PWM4_MODE_3 0x42 ++#define PINMUX_FOR_PWM4_MODE_4 0x43 ++#define PINMUX_FOR_PWM5_MODE_1 0x44 ++#define PINMUX_FOR_PWM5_MODE_2 0x45 ++#define PINMUX_FOR_PWM5_MODE_3 0x46 ++#define PINMUX_FOR_PWM5_MODE_4 0x47 ++#define PINMUX_FOR_PWM6_MODE_1 0x48 ++#define PINMUX_FOR_PWM6_MODE_2 0x49 ++#define PINMUX_FOR_PWM6_MODE_3 0x4a ++#define PINMUX_FOR_PWM6_MODE_4 0x4b ++#define PINMUX_FOR_PWM7_MODE_1 0x4c ++#define PINMUX_FOR_PWM7_MODE_2 0x4d ++#define PINMUX_FOR_PWM7_MODE_3 0x4e ++#define PINMUX_FOR_PWM7_MODE_4 0x4f ++#define PINMUX_FOR_PWM8_MODE_1 0x50 ++#define PINMUX_FOR_PWM8_MODE_2 0x51 ++#define PINMUX_FOR_PWM8_MODE_3 0x52 ++#define PINMUX_FOR_PWM8_MODE_4 0x53 ++#define PINMUX_FOR_PWM9_MODE_1 0x54 ++#define PINMUX_FOR_PWM9_MODE_2 0x55 ++#define PINMUX_FOR_PWM9_MODE_3 0x56 ++#define PINMUX_FOR_PWM9_MODE_4 0x57 ++#define PINMUX_FOR_PWM10_MODE_1 0x58 ++#define PINMUX_FOR_PWM10_MODE_2 0x59 ++#define PINMUX_FOR_PWM10_MODE_3 0x5a ++#define PINMUX_FOR_PWM10_MODE_4 0x5b ++#define PINMUX_FOR_SR_MODE_1 0x5c ++#define PINMUX_FOR_SR_MODE_2 0x5d ++#define PINMUX_FOR_SR_MODE_3 0x5e ++#define PINMUX_FOR_SR_MODE_4 0x5f ++#define PINMUX_FOR_SR_MCLK_MODE 0x60 ++#define PINMUX_FOR_SR_PDN_MODE_1 0x61 ++#define PINMUX_FOR_SR_PDN_MODE_2 0x62 ++#define PINMUX_FOR_SR_RST_MODE_1 0x63 ++#define PINMUX_FOR_SR_RST_MODE_2 0x64 ++#define PINMUX_FOR_SR_HVSYNC_MODE 0x65 ++#define PINMUX_FOR_SR_PCK_MODE 0x66 ++#define PINMUX_FOR_ETH_MODE 0x67 ++#define PINMUX_FOR_I2S_MODE_1 0x68 ++#define PINMUX_FOR_I2S_MODE_2 0x69 ++#define PINMUX_FOR_I2S_MODE_3 0x6a ++#define PINMUX_FOR_DMIC_MODE_1 0x6b ++#define PINMUX_FOR_DMIC_MODE_2 0x6c ++#define PINMUX_FOR_DMIC_MODE_3 0x6d ++#define PINMUX_FOR_TTL_MODE_1 0x6e ++#define PINMUX_FOR_TTL_MODE_2 0x6f ++#define PINMUX_FOR_CCIR_MODE_1 0x70 ++#define PINMUX_FOR_CCIR_MODE_2 0x71 ++#define PINMUX_FOR_CCIR_MODE_3 0x72 ++ ++#define PINMUX_FOR_PM_SPI_MODE 0x73 ++#define PINMUX_FOR_PM_SPIWPN_MODE 0x74 ++#define PINMUX_FOR_PM_SPIHOLDN_MODE 0x75 ++#define PINMUX_FOR_PM_SPICSZ1_MODE 0x76 ++#define PINMUX_FOR_PM_SPICSZ2_MODE 0x77 ++#define PINMUX_FOR_PM_PWM0_MODE_1 0x78 ++#define PINMUX_FOR_PM_PWM0_MODE_2 0x79 ++#define PINMUX_FOR_PM_PWM1_MODE_1 0x7a ++#define PINMUX_FOR_PM_PWM1_MODE_2 0x7b ++#define PINMUX_FOR_PM_PWM2_MODE_1 0x7c ++#define PINMUX_FOR_PM_PWM2_MODE_2 0x7d ++#define PINMUX_FOR_PM_PWM3_MODE_1 0x7e ++#define PINMUX_FOR_PM_PWM3_MODE_2 0x7f ++#define PINMUX_FOR_PM_PWM4_MODE 0x80 ++#define PINMUX_FOR_PM_PWM5_MODE 0x81 ++#define PINMUX_FOR_PM_PWM8_MODE 0x82 ++#define PINMUX_FOR_PM_PWM9_MODE 0x83 ++#define PINMUX_FOR_PM_PWM10_MODE 0x84 ++#define PINMUX_FOR_PM_UART1_MODE 0x85 ++#define PINMUX_FOR_PM_VID_MODE_1 0x86 ++#define PINMUX_FOR_PM_VID_MODE_2 0x87 ++#define PINMUX_FOR_PM_VID_MODE_3 0x88 ++#define PINMUX_FOR_PM_SD_CDZ_MODE 0x89 ++#define PINMUX_FOR_PM_LED_MODE 0x8a ++#define PINMUX_FOR_PM_TTL_MODE_1 0x8b ++#define PINMUX_FOR_PM_TTL_MODE_2 0x8c ++#define PINMUX_FOR_PM_IRIN_MODE 0x8d ++ ++#define PINMUX_FOR_SAR_MODE 0x8e ++#define PINMUX_FOR_USB_MODE 0x8f ++ ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++#endif // ___PADMUX_H +diff --git a/drivers/sstar/include/infinity6b0/pmsleep-irqs.h b/drivers/sstar/include/infinity6b0/pmsleep-irqs.h +new file mode 100755 +index 000000000000..8e1106aeb733 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/pmsleep-irqs.h +@@ -0,0 +1,130 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_DUMMY_5 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_DUMMY_6 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_DUMMY_10 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_DUMMY_11 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_DUMMY_12 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_DUMMY_13 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_DUMMY_14 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_DUMMY_15 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_DUMMY_16 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_DUMMY_17 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_DUMMY_18 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_DUMMY_19 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_DUMMY_22 (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_DUMMY_23 (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_32 (PMSLEEP_FIQ_START + 32) ++#define INT_PMSLEEP_DUMMY_33 (PMSLEEP_FIQ_START + 33) ++#define INT_PMSLEEP_DUMMY_34 (PMSLEEP_FIQ_START + 34) ++#define INT_PMSLEEP_DUMMY_35 (PMSLEEP_FIQ_START + 35) ++#define INT_PMSLEEP_DUMMY_36 (PMSLEEP_FIQ_START + 36) ++#define INT_PMSLEEP_DUMMY_37 (PMSLEEP_FIQ_START + 37) ++#define INT_PMSLEEP_DUMMY_38 (PMSLEEP_FIQ_START + 38) ++#define INT_PMSLEEP_DUMMY_39 (PMSLEEP_FIQ_START + 39) ++#define INT_PMSLEEP_DUMMY_40 (PMSLEEP_FIQ_START + 40) ++#define INT_PMSLEEP_DUMMY_41 (PMSLEEP_FIQ_START + 41) ++#define INT_PMSLEEP_DUMMY_42 (PMSLEEP_FIQ_START + 42) ++#define INT_PMSLEEP_DUMMY_43 (PMSLEEP_FIQ_START + 43) ++#define INT_PMSLEEP_DUMMY_44 (PMSLEEP_FIQ_START + 44) ++#define INT_PMSLEEP_DUMMY_45 (PMSLEEP_FIQ_START + 45) ++#define INT_PMSLEEP_DUMMY_46 (PMSLEEP_FIQ_START + 46) ++#define INT_PMSLEEP_DUMMY_47 (PMSLEEP_FIQ_START + 47) ++#define INT_PMSLEEP_DUMMY_48 (PMSLEEP_FIQ_START + 48) ++#define INT_PMSLEEP_DUMMY_49 (PMSLEEP_FIQ_START + 49) ++#define INT_PMSLEEP_DUMMY_50 (PMSLEEP_FIQ_START + 50) ++#define INT_PMSLEEP_DUMMY_51 (PMSLEEP_FIQ_START + 51) ++#define INT_PMSLEEP_DUMMY_52 (PMSLEEP_FIQ_START + 52) ++#define INT_PMSLEEP_DUMMY_53 (PMSLEEP_FIQ_START + 53) ++#define INT_PMSLEEP_DUMMY_54 (PMSLEEP_FIQ_START + 54) ++#define INT_PMSLEEP_DUMMY_55 (PMSLEEP_FIQ_START + 55) ++#define INT_PMSLEEP_DUMMY_56 (PMSLEEP_FIQ_START + 56) ++#define INT_PMSLEEP_DUMMY_57 (PMSLEEP_FIQ_START + 57) ++#define INT_PMSLEEP_DUMMY_58 (PMSLEEP_FIQ_START + 58) ++#define INT_PMSLEEP_DUMMY_59 (PMSLEEP_FIQ_START + 59) ++#define INT_PMSLEEP_DUMMY_60 (PMSLEEP_FIQ_START + 60) ++#define INT_PMSLEEP_DUMMY_61 (PMSLEEP_FIQ_START + 61) ++#define INT_PMSLEEP_DUMMY_62 (PMSLEEP_FIQ_START + 62) ++#define INT_PMSLEEP_DUMMY_63 (PMSLEEP_FIQ_START + 63) ++#define INT_PMSLEEP_DUMMY_64 (PMSLEEP_FIQ_START + 64) ++#define INT_PMSLEEP_DUMMY_65 (PMSLEEP_FIQ_START + 65) ++#define INT_PMSLEEP_DUMMY_66 (PMSLEEP_FIQ_START + 66) ++#define INT_PMSLEEP_DUMMY_67 (PMSLEEP_FIQ_START + 67) ++#define INT_PMSLEEP_SPI_WPZ (PMSLEEP_FIQ_START + 68) ++#define INT_PMSLEEP_SPI_HLD (PMSLEEP_FIQ_START + 69) ++#define INT_PMSLEEP_DUMMY_70 (PMSLEEP_FIQ_START + 70) ++#define INT_PMSLEEP_SD_CDZ (PMSLEEP_FIQ_START + 71) ++#define INT_PMSLEEP_DUMMY_72 (PMSLEEP_FIQ_START + 72) ++#define INT_PMSLEEP_DUMMY_73 (PMSLEEP_FIQ_START + 73) ++#define INT_PMSLEEP_LED0 (PMSLEEP_FIQ_START + 74) ++#define INT_PMSLEEP_LED1 (PMSLEEP_FIQ_START + 75) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 76) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_CEC (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_SAR_GPIO (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_RTCPWC_ALARM (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) +diff --git a/drivers/sstar/include/infinity6b0/regMIU.h b/drivers/sstar/include/infinity6b0/regMIU.h +new file mode 100755 +index 000000000000..36e367cb6a9d +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/regMIU.h +@@ -0,0 +1,135 @@ ++/* ++* regMIU.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_MIU_H_ ++#define _REG_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) ++#define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) ++ ++#define MIU_REG_BASE (0x1200UL) ++#define MIU1_REG_BASE (0x0D00UL) ++#define MIU2_REG_BASE (0x62000UL) ++#define PM_REG_BASE (0x1E00UL) ++#define MIU_ATOP_BASE (0x1000UL) ++#define MIU1_ATOP_BASE (0x0B00UL) ++#define MIU2_ATOP_BASE (0x62100UL) ++#define CHIP_TOP_BASE (0x1E00UL) ++#define MIU_ARB_REG_BASE (0x1100UL) ++#define MIU1_ARB_REG_BASE (0x0C00UL) ++#define MIU2_ARB_REG_BASE (0x62300UL) ++ ++#define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3UL) ++#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++#define MIU_PROTECT_DDR_32MB (0x50UL) ++#define MIU_PROTECT_DDR_64MB (0x60UL) ++#define MIU_PROTECT_DDR_128MB (0x70UL) ++#define MIU_PROTECT_DDR_256MB (0x80UL) ++#define MIU_PROTECT_DDR_512MB (0x90UL) ++#define MIU_PROTECT_DDR_1024MB (0xA0UL) ++#define MIU_PROTECT_DDR_2048MB (0xB0UL) ++ ++#define MIU_PROTECT0_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT1_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT2_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT3_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT4_EN (MIU_ARB_REG_BASE+0xDEUL) ++#define MIU_PROTECT_ID0 (MIU_REG_BASE+0x2EUL) ++#define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20UL) ++#define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22UL) ++#define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24UL) ++#define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26UL) ++#define MIU_PROTECT4_ID_ENABLE (MIU_ARB_REG_BASE+0xDC) ++#define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT1_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT2_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT3_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT4_MSB (MIU_REG_BASE+0xB2UL) ++#define MIU_PROTECT0_START (MIU_REG_BASE+0xC0UL) ++#define MIU_PROTECT0_END (MIU_REG_BASE+0xC2UL) ++#define MIU_PROTECT1_START (MIU_REG_BASE+0xC4UL) ++#define MIU_PROTECT1_END (MIU_REG_BASE+0xC6UL) ++#define MIU_PROTECT2_START (MIU_REG_BASE+0xC8UL) ++#define MIU_PROTECT2_END (MIU_REG_BASE+0xCAUL) ++#define MIU_PROTECT3_START (MIU_REG_BASE+0xCCUL) ++#define MIU_PROTECT3_END (MIU_REG_BASE+0xCEUL) ++#define MIU_PROTECT4_START (MIU_REG_BASE+0x72UL) ++#define MIU_PROTECT4_END (MIU_REG_BASE+0x92UL) ++#define REG_MIU_PROTECT_LOADDR (0x6DUL << 1) //0xDE ++#define REG_MIU_PROTECT_HIADDR (0x6EUL << 1) //0xDE ++#define REG_MIU_PROTECT_STATUS (0x6FUL << 1) //0xDE ++ ++// MIU selection registers ++#define REG_MIU_SEL0 (MIU_REG_BASE+0xf0UL) //0x12F0 ++#define REG_MIU_SEL1 (MIU_REG_BASE+0xf2UL) //0x12F1 ++#define REG_MIU_SEL2 (MIU_REG_BASE+0xf4UL) //0x12F2 ++#define REG_MIU_SEL3 (MIU_REG_BASE+0xf6UL) //0x12F3 ++#define REG_MIU_SELX(x) (0xF0UL+x*2) ++ ++// MIU1 ++#define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3UL) ++#define MIU1_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++ ++#define MIU1_PROTECT0_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT1_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT2_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT3_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT4_EN (MIU1_ARB_REG_BASE+0xDEUL) ++#define MIU1_PROTECT_ID0 (MIU1_REG_BASE+0x2EUL) ++#define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20UL) ++#define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22UL) ++#define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24UL) ++#define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26UL) ++#define MIU1_PROTECT4_ID_ENABLE (MIU1_ARB_REG_BASE+0xDC) ++#define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT1_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT2_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT3_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT4_MSB (MIU1_REG_BASE+0xB2UL) ++#define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0UL) ++#define MIU1_PROTECT0_END (MIU1_REG_BASE+0xC2UL) ++#define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4UL) ++#define MIU1_PROTECT1_END (MIU1_REG_BASE+0xC6UL) ++#define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8UL) ++#define MIU1_PROTECT2_END (MIU1_REG_BASE+0xCAUL) ++#define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCCUL) ++#define MIU1_PROTECT3_END (MIU1_REG_BASE+0xCEUL) ++#define MIU1_PROTECT4_START (MIU1_REG_BASE+0x72UL) ++#define MIU1_PROTECT4_END (MIU1_REG_BASE+0x92UL) ++ ++#define REG_MIU_I64_MODE (BIT7) ++#define REG_MIU_INIT_DONE (BIT15) ++ ++// Protection Status ++#define REG_MIU_PROTECT_LOG_CLR (BIT0) ++#define REG_MIU_PROTECT_IRQ_MASK (BIT1) ++#define REG_MIU_PROTECT_HIT_FALG (BIT4) ++#define REG_MIU_PROTECT_HIT_ID 14:8 ++#define REG_MIU_PROTECT_HIT_NO 7:5 ++ ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET (MIU_REG_BASE+0xD8UL) ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_BIT (BIT11) ++ ++#endif // _REG_MIU_H_ +diff --git a/drivers/sstar/include/infinity6b0/reg_clks.h b/drivers/sstar/include/infinity6b0/reg_clks.h +new file mode 100755 +index 000000000000..01cadb436642 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/reg_clks.h +@@ -0,0 +1,466 @@ ++/* ++* reg_clks.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I6/iNfinity6_Clock_Table_1022_SW.xls */ ++/* REG FILENAME: I6/iNfinity6_reg_CLKGEN.xls, I6/iNfinity6_reg_pm_sleep.xls, I6/iNfinity6_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_CKG_SNR0_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR0_OFFSET (0) ++ ++#define REG_CKG_SNR1_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR1_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PWM_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_BT656_0_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_BT656_0_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FCLK2_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SD_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_VHE_VPU_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_VHE_VPU_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity6b0/registers.h b/drivers/sstar/include/infinity6b0/registers.h +new file mode 100755 +index 000000000000..78d1029d9202 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/registers.h +@@ -0,0 +1,258 @@ ++/* ++* registers.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define REG_ADDR(addr) (*((volatile U16*)(0xFD200000 + (addr << 1)))) ++ ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0xFFFFFFFF ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++ ++#define MIU0_BASE ARM_MIU0_BUS_BASE ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x18000 ++ // #define IMI_SIZE (0x20000) // 128K ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0600) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3000) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++ ++#define BASE_REG_BDMA0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100200) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100220) ++#define BASE_REG_BDMA2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100240) ++#define BASE_REG_BDMA3_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100260) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_MOVDMA_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100B00) ++#define BASE_REG_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101000) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_MIUPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103100) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++#define BASE_REG_GPI_INT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103D00) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I6_PACKAGE_UNKNOWN =0x00, ++ MS_I6_PACKAGE_QFN_DDR2_32MB, ++ MS_I6_PACKAGE_QFN_DDR2_64MB, ++ MS_I6_PACKAGE_BGA_128MB, ++ MS_I6_PACKAGE_BGA_256MB, ++ MS_I6_PACKAGE_QFN_DDR3_128MB, ++ MS_I6_PACKAGE_EXTENDED=0x30, ++ MS_I6_PACKAGE_DDR3_1866_128MB =0x30, ++ MS_I6_PACKAGE_DDR3_1866_256MB, ++ MS_I6_PACKAGE_FPGA_128MB =0x90, ++} MS_I6_PACKAGE_TYPE; ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity6b0/tsensor.h b/drivers/sstar/include/infinity6b0/tsensor.h +new file mode 100755 +index 000000000000..30e40f7d6d1b +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/tsensor.h +@@ -0,0 +1,23 @@ ++/* ++* tsensor.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __CPU_FREQ_H ++#define __CPU_FREQ_H ++ ++int ms_get_temp(void); ++ ++#endif //__CPU_FREQ_H +diff --git a/drivers/sstar/include/infinity6b0/voltage_ctrl_demander.h b/drivers/sstar/include/infinity6b0/voltage_ctrl_demander.h +new file mode 100755 +index 000000000000..d04460e64eb8 +--- /dev/null ++++ b/drivers/sstar/include/infinity6b0/voltage_ctrl_demander.h +@@ -0,0 +1,36 @@ ++/* ++* voltage_ctrl.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __VOLTAGE_CTRL_DEMANDER_H ++#define __VOLTAGE_CTRL_DEMANDER_H ++ ++#define FOREACH_DEMANDER(DEMANDER) \ ++ DEMANDER(VOLTAGE_DEMANDER_CPUFREQ) \ ++ DEMANDER(VOLTAGE_DEMANDER_TEMPERATURE) \ ++ DEMANDER(VOLTAGE_DEMANDER_VENC) \ ++ DEMANDER(VOLTAGE_DEMANDER_MIU) \ ++ DEMANDER(VOLTAGE_DEMANDER_USER) \ ++ DEMANDER(VOLTAGE_DEMANDER_MAX) \ ++ ++#define GENERATE_ENUM(ENUM) ENUM, ++#define GENERATE_STRING(STRING) #STRING, ++ ++typedef enum { ++ FOREACH_DEMANDER(GENERATE_ENUM) ++} VOLTAGE_DEMANDER_E; ++ ++#endif //__VOLTAGE_CTRL_DEMANDER_H +diff --git a/drivers/sstar/include/infinity6e/Kconfig b/drivers/sstar/include/infinity6e/Kconfig +new file mode 100755 +index 000000000000..6ab19f8d46b0 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/Kconfig +@@ -0,0 +1,13 @@ ++source "drivers/sstar/emmc/Kconfig" ++source "drivers/sstar/sdmmc/Kconfig" ++source "drivers/sstar/emac/Kconfig" ++source "drivers/sstar/ircut/Kconfig" ++source "drivers/sstar/rtc/Kconfig" ++source "drivers/sstar/crypto/Kconfig" ++source "drivers/sstar/cpufreq/Kconfig" ++source "drivers/sstar/ive/Kconfig" ++source "drivers/sstar/notify/Kconfig" ++source "drivers/sstar/isrcb/Kconfig" ++source "drivers/sstar/miu/Kconfig" ++source "drivers/sstar/bdma/Kconfig" ++source "drivers/sstar/movedma/Kconfig" +diff --git a/drivers/sstar/include/infinity6e/camclk.h b/drivers/sstar/include/infinity6e/camclk.h +new file mode 100644 +index 000000000000..fdfd17ec4551 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/camclk.h +@@ -0,0 +1,167 @@ ++/* Copyright (c) 2018-2019 Sigmastar Technology Corp. ++ All rights reserved. ++ ++ Unless otherwise stipulated in writing, any and all information contained ++herein regardless in any format shall remain the sole proprietary of ++Sigmastar Technology Corp. and be kept in strict confidence ++(Sigmastar Confidential Information) by the recipient. ++Any unauthorized act including without limitation unauthorized disclosure, ++copying, use, reproduction, sale, distribution, modification, disassembling, ++reverse engineering and compiling of the contents of Sigmastar Confidential ++Information is unlawful and strictly prohibited. Sigmastar hereby reserves the ++rights to any and all damages, losses, costs and expenses resulting therefrom. ++*/ ++ ++#ifndef __CAMCLK_H__ ++#define __CAMCLK_H__ ++ ++#define CAMCLK_VOID 0 ++#define CAMCLK_utmi_480m 1 ++#define CAMCLK_mpll_432m 2 ++#define CAMCLK_upll_384m 3 ++#define CAMCLK_mpll_345m 4 ++#define CAMCLK_upll_320m 5 ++#define CAMCLK_mpll_288m 6 ++#define CAMCLK_utmi_240m 7 ++#define CAMCLK_mpll_216m 8 ++#define CAMCLK_utmi_192m 9 ++#define CAMCLK_mpll_172m 10 ++#define CAMCLK_utmi_160m 11 ++#define CAMCLK_mpll_123m 12 ++#define CAMCLK_mpll_86m 13 ++#define CAMCLK_mpll_288m_div2 14 ++#define CAMCLK_mpll_288m_div4 15 ++#define CAMCLK_mpll_288m_div8 16 ++#define CAMCLK_mpll_216m_div2 17 ++#define CAMCLK_mpll_216m_div4 18 ++#define CAMCLK_mpll_216m_div8 19 ++#define CAMCLK_mpll_123m_div2 20 ++#define CAMCLK_mpll_86m_div2 21 ++#define CAMCLK_mpll_86m_div4 22 ++#define CAMCLK_mpll_86m_div16 23 ++#define CAMCLK_utmi_192m_div4 24 ++#define CAMCLK_utmi_160m_div4 25 ++#define CAMCLK_utmi_160m_div5 26 ++#define CAMCLK_utmi_160m_div8 27 ++#define CAMCLK_xtali_12m 28 ++#define CAMCLK_xtali_12m_div2 29 ++#define CAMCLK_xtali_12m_div4 30 ++#define CAMCLK_xtali_12m_div8 31 ++#define CAMCLK_xtali_12m_div16 32 ++#define CAMCLK_xtali_12m_div40 33 ++#define CAMCLK_xtali_12m_div64 34 ++#define CAMCLK_xtali_12m_div128 35 ++#define CAMCLK_xtali_24m 36 ++#define CAMCLK_RTC_CLK_32K 37 ++#define CAMCLK_pm_riu_w_clk_in 38 ++#define CAMCLK_miupll_clk 39 ++#define CAMCLK_ddrpll_clk 40 ++#define CAMCLK_lpll_clk 41 ++#define CAMCLK_ven_pll 42 ++#define CAMCLK_ven_pll_div6 43 ++#define CAMCLK_lpll_div2 44 ++#define CAMCLK_lpll_div4 45 ++#define CAMCLK_lpll_div8 46 ++#define CAMCLK_armpll_37p125m 47 ++#define CAMCLK_riu_w_clk_in 48 ++#define CAMCLK_riu_w_clk_top 49 ++#define CAMCLK_riu_w_clk_sc_gp 50 ++#define CAMCLK_riu_w_clk_vhe_gp 51 ++#define CAMCLK_riu_w_clk_hemcu_gp 52 ++#define CAMCLK_riu_w_clk_mipi_if_gp 53 ++#define CAMCLK_riu_w_clk_mcu_if_gp 54 ++#define CAMCLK_fuart0_synth_out 55 ++#define CAMCLK_miu_p 56 ++#define CAMCLK_mspi0_p 57 ++#define CAMCLK_mspi1_p 58 ++#define CAMCLK_miu_vhe_gp_p 59 ++#define CAMCLK_miu_sc_gp_p 60 ++#define CAMCLK_mcu_p 61 ++#define CAMCLK_fclk1_p 62 ++#define CAMCLK_sdio_p 63 ++#define CAMCLK_tck_buf 64 ++#define CAMCLK_eth_buf 65 ++#define CAMCLK_rmii_buf 66 ++#define CAMCLK_emac_testrx125_in_lan 67 ++#define CAMCLK_gop0 68 ++#define CAMCLK_rtc_32k 69 ++#define CAMCLK_fro 70 ++#define CAMCLK_fro_div2 71 ++#define CAMCLK_fro_div8 72 ++#define CAMCLK_fro_div16 73 ++#define CAMCLK_cpupll_clk 74 ++#define CAMCLK_utmi 75 ++#define CAMCLK_bach 76 ++#define CAMCLK_miu 77 ++#define CAMCLK_miu_boot 78 ++#define CAMCLK_ddr_syn 79 ++#define CAMCLK_miu_rec 80 ++#define CAMCLK_mcu 81 ++#define CAMCLK_riubrdg 82 ++#define CAMCLK_bdma 83 ++#define CAMCLK_spi_arb 84 ++#define CAMCLK_spi_flash 85 ++#define CAMCLK_pwm 86 ++#define CAMCLK_uart0 87 ++#define CAMCLK_uart1 88 ++#define CAMCLK_fuart0_synth_in 89 ++#define CAMCLK_fuart 90 ++#define CAMCLK_mspi0 91 ++#define CAMCLK_mspi1 92 ++#define CAMCLK_mspi 93 ++#define CAMCLK_miic0 94 ++#define CAMCLK_miic1 95 ++#define CAMCLK_miic2 96 ++#define CAMCLK_bist 97 ++#define CAMCLK_pwr_ctl 98 ++#define CAMCLK_xtali 99 ++#define CAMCLK_live 100 ++#define CAMCLK_sr00_mclk 101 ++#define CAMCLK_sr01_mclk 102 ++#define CAMCLK_sr1_mclk 103 ++#define CAMCLK_bist_pm 104 ++#define CAMCLK_bist_ipu_gp 105 ++#define CAMCLK_ipu 106 ++#define CAMCLK_ipuff 107 ++#define CAMCLK_bist_usb30_gp 108 ++#define CAMCLK_csi_mac_lptx_top_i_m00 109 ++#define CAMCLK_csi_mac_top_i_m00 110 ++#define CAMCLK_ns_top_i_m00 111 ++#define CAMCLK_csi_mac_lptx_top_i_m01 112 ++#define CAMCLK_csi_mac_top_i_m01 113 ++#define CAMCLK_ns_top_i_m01 114 ++#define CAMCLK_csi_mac_lptx_top_i_m1 115 ++#define CAMCLK_csi_mac_top_i_m1 116 ++#define CAMCLK_ns_top_i_m1 117 ++#define CAMCLK_mipi1_tx_csi 118 ++#define CAMCLK_bist_vhe_gp 119 ++#define CAMCLK_vhe 120 ++#define CAMCLK_mfe 121 ++#define CAMCLK_xtali_sc_gp 122 ++#define CAMCLK_bist_sc_gp 123 ++#define CAMCLK_emac_ahb 124 ++#define CAMCLK_jpe 125 ++#define CAMCLK_aesdma 126 ++#define CAMCLK_sdio 127 ++#define CAMCLK_sd 128 ++#define CAMCLK_ecc 129 ++#define CAMCLK_isp 130 ++#define CAMCLK_fclk1 131 ++#define CAMCLK_odclk 132 ++#define CAMCLK_dip 133 ++#define CAMCLK_emac_tx 134 ++#define CAMCLK_emac_rx 135 ++#define CAMCLK_emac_tx_ref 136 ++#define CAMCLK_emac_rx_ref 137 ++#define CAMCLK_ive 138 ++#define CAMCLK_ldcfeye 139 ++#define CAMCLK_live_pm 140 ++#define CAMCLK_mcu_pm_p1 141 ++#define CAMCLK_spi_pm 142 ++#define CAMCLK_miic_pm 143 ++#define CAMCLK_pm_sleep 144 ++#define CAMCLK_rtc 145 ++#define CAMCLK_sar 146 ++#define CAMCLK_pir 147 ++#define CAMCLK_pm_uart 148 ++#endif +diff --git a/drivers/sstar/include/infinity6e/gpi-irqs.h b/drivers/sstar/include/infinity6e/gpi-irqs.h +new file mode 100755 +index 000000000000..7203ac8d233a +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/gpi-irqs.h +@@ -0,0 +1,132 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++#define GPI_FIQ_START 0 ++#define INT_GPI_FIQ_PAD_GPIO0 (GPI_FIQ_START + 0) ++#define INT_GPI_FIQ_PAD_GPIO1 (GPI_FIQ_START + 1) ++#define INT_GPI_FIQ_PAD_GPIO2 (GPI_FIQ_START + 2) ++#define INT_GPI_FIQ_PAD_GPIO3 (GPI_FIQ_START + 3) ++#define INT_GPI_FIQ_PAD_GPIO4 (GPI_FIQ_START + 4) ++#define INT_GPI_FIQ_PAD_GPIO5 (GPI_FIQ_START + 5) ++#define INT_GPI_FIQ_PAD_GPIO6 (GPI_FIQ_START + 6) ++#define INT_GPI_FIQ_PAD_GPIO7 (GPI_FIQ_START + 7) ++#define INT_GPI_FIQ_PAD_GPIO8 (GPI_FIQ_START + 8) ++#define INT_GPI_FIQ_PAD_GPIO9 (GPI_FIQ_START + 9) ++#define INT_GPI_FIQ_PAD_GPIO10 (GPI_FIQ_START + 10) ++#define INT_GPI_FIQ_PAD_GPIO11 (GPI_FIQ_START + 11) ++#define INT_GPI_FIQ_PAD_GPIO12 (GPI_FIQ_START + 12) ++#define INT_GPI_FIQ_PAD_GPIO13 (GPI_FIQ_START + 13) ++#define INT_GPI_FIQ_PAD_GPIO14 (GPI_FIQ_START + 14) ++#define INT_GPI_FIQ_PAD_GPIO15 (GPI_FIQ_START + 15) ++#define INT_GPI_FIQ_PAD_SD0_GPIO0 (GPI_FIQ_START + 16) ++#define INT_GPI_FIQ_PAD_SD0_CDZ (GPI_FIQ_START + 17) ++#define INT_GPI_FIQ_PAD_SD0_D1 (GPI_FIQ_START + 18) ++#define INT_GPI_FIQ_PAD_SD0_D0 (GPI_FIQ_START + 19) ++#define INT_GPI_FIQ_PAD_SD0_CLK (GPI_FIQ_START + 20) ++#define INT_GPI_FIQ_PAD_SD0_CMD (GPI_FIQ_START + 21) ++#define INT_GPI_FIQ_PAD_SD0_D3 (GPI_FIQ_START + 22) ++#define INT_GPI_FIQ_PAD_SD0_D2 (GPI_FIQ_START + 23) ++#define INT_GPI_FIQ_PAD_I2S0_MCLK (GPI_FIQ_START + 24) ++#define INT_GPI_FIQ_PAD_I2S0_BCK (GPI_FIQ_START + 25) ++#define INT_GPI_FIQ_PAD_I2S0_WCK (GPI_FIQ_START + 26) ++#define INT_GPI_FIQ_PAD_I2S0_DI (GPI_FIQ_START + 27) ++#define INT_GPI_FIQ_PAD_I2S0_DO (GPI_FIQ_START + 28) ++#define INT_GPI_FIQ_PAD_I2C0_SCL (GPI_FIQ_START + 29) ++#define INT_GPI_FIQ_PAD_I2C0_SDA (GPI_FIQ_START + 30) ++#define INT_GPI_FIQ_DUMMY_31 (GPI_FIQ_START + 31) ++#define INT_GPI_FIQ_PAD_ETH_LED0 (GPI_FIQ_START + 32) ++#define INT_GPI_FIQ_PAD_ETH_LED1 (GPI_FIQ_START + 33) ++#define INT_GPI_FIQ_PAD_FUART_RX (GPI_FIQ_START + 34) ++#define INT_GPI_FIQ_PAD_FUART_TX (GPI_FIQ_START + 35) ++#define INT_GPI_FIQ_PAD_FUART_CTS (GPI_FIQ_START + 36) ++#define INT_GPI_FIQ_PAD_FUART_RTS (GPI_FIQ_START + 37) ++#define INT_GPI_FIQ_PAD_SD1_CDZ (GPI_FIQ_START + 38) ++#define INT_GPI_FIQ_PAD_SD1_D1 (GPI_FIQ_START + 39) ++#define INT_GPI_FIQ_PAD_SD1_D0 (GPI_FIQ_START + 40) ++#define INT_GPI_FIQ_PAD_SD1_CLK (GPI_FIQ_START + 41) ++#define INT_GPI_FIQ_PAD_SD1_CMD (GPI_FIQ_START + 42) ++#define INT_GPI_FIQ_PAD_SD1_D3 (GPI_FIQ_START + 43) ++#define INT_GPI_FIQ_PAD_SD1_D2 (GPI_FIQ_START + 44) ++#define INT_GPI_FIQ_PAD_SD1_GPIO0 (GPI_FIQ_START + 45) ++#define INT_GPI_FIQ_PAD_SD1_GPIO1 (GPI_FIQ_START + 46) ++#define INT_GPI_FIQ_DUMMY_47 (GPI_FIQ_START + 47) ++#define INT_GPI_FIQ_PAD_SPI_CZ (GPI_FIQ_START + 48) ++#define INT_GPI_FIQ_PAD_SPI_CK (GPI_FIQ_START + 49) ++#define INT_GPI_FIQ_PAD_SPI_DI (GPI_FIQ_START + 50) ++#define INT_GPI_FIQ_PAD_SPI_DO (GPI_FIQ_START + 51) ++#define INT_GPI_FIQ_PAD_SPI_WPZ (GPI_FIQ_START + 52) ++#define INT_GPI_FIQ_PAD_SPI_HLD (GPI_FIQ_START + 53) ++#define INT_GPI_FIQ_PAD_SR0_IO00 (GPI_FIQ_START + 54) ++#define INT_GPI_FIQ_PAD_SR0_IO01 (GPI_FIQ_START + 55) ++#define INT_GPI_FIQ_PAD_SR0_IO02 (GPI_FIQ_START + 56) ++#define INT_GPI_FIQ_PAD_SR0_IO03 (GPI_FIQ_START + 57) ++#define INT_GPI_FIQ_PAD_SR0_IO04 (GPI_FIQ_START + 58) ++#define INT_GPI_FIQ_PAD_SR0_IO05 (GPI_FIQ_START + 59) ++#define INT_GPI_FIQ_PAD_SR0_IO06 (GPI_FIQ_START + 60) ++#define INT_GPI_FIQ_PAD_SR0_IO07 (GPI_FIQ_START + 61) ++#define INT_GPI_FIQ_PAD_SR0_IO08 (GPI_FIQ_START + 62) ++#define INT_GPI_FIQ_PAD_SR0_IO09 (GPI_FIQ_START + 63) ++#define INT_GPI_FIQ_PAD_SR0_IO10 (GPI_FIQ_START + 64) ++#define INT_GPI_FIQ_PAD_SR0_IO11 (GPI_FIQ_START + 65) ++#define INT_GPI_FIQ_PAD_SR0_IO12 (GPI_FIQ_START + 66) ++#define INT_GPI_FIQ_PAD_SR0_IO13 (GPI_FIQ_START + 67) ++#define INT_GPI_FIQ_PAD_SR0_IO14 (GPI_FIQ_START + 68) ++#define INT_GPI_FIQ_PAD_SR0_IO15 (GPI_FIQ_START + 69) ++#define INT_GPI_FIQ_PAD_SR0_IO16 (GPI_FIQ_START + 70) ++#define INT_GPI_FIQ_PAD_SR0_IO17 (GPI_FIQ_START + 71) ++#define INT_GPI_FIQ_PAD_SR0_IO18 (GPI_FIQ_START + 72) ++#define INT_GPI_FIQ_PAD_SR0_IO19 (GPI_FIQ_START + 73) ++#define INT_GPI_FIQ_PAD_SR1_IO00 (GPI_FIQ_START + 74) ++#define INT_GPI_FIQ_PAD_SR1_IO01 (GPI_FIQ_START + 75) ++#define INT_GPI_FIQ_PAD_SR1_IO02 (GPI_FIQ_START + 76) ++#define INT_GPI_FIQ_PAD_SR1_IO03 (GPI_FIQ_START + 77) ++#define INT_GPI_FIQ_PAD_SR1_IO04 (GPI_FIQ_START + 78) ++#define INT_GPI_FIQ_PAD_SR1_IO05 (GPI_FIQ_START + 79) ++#define INT_GPI_FIQ_PAD_SR1_IO06 (GPI_FIQ_START + 80) ++#define INT_GPI_FIQ_PAD_SR1_IO07 (GPI_FIQ_START + 81) ++#define INT_GPI_FIQ_PAD_SR1_IO08 (GPI_FIQ_START + 82) ++#define INT_GPI_FIQ_PAD_SR1_IO09 (GPI_FIQ_START + 83) ++#define INT_GPI_FIQ_PAD_SR1_IO10 (GPI_FIQ_START + 84) ++#define INT_GPI_FIQ_PAD_SR1_IO11 (GPI_FIQ_START + 85) ++#define INT_GPI_FIQ_PAD_SR1_IO12 (GPI_FIQ_START + 86) ++#define INT_GPI_FIQ_PAD_SR1_IO13 (GPI_FIQ_START + 87) ++#define INT_GPI_FIQ_PAD_SR1_IO14 (GPI_FIQ_START + 88) ++#define INT_GPI_FIQ_PAD_SR1_IO15 (GPI_FIQ_START + 89) ++#define INT_GPI_FIQ_PAD_SR1_IO16 (GPI_FIQ_START + 90) ++#define INT_GPI_FIQ_PAD_SR1_IO17 (GPI_FIQ_START + 91) ++#define INT_GPI_FIQ_PAD_SR1_IO18 (GPI_FIQ_START + 92) ++#define INT_GPI_FIQ_PAD_SR1_IO19 (GPI_FIQ_START + 93) ++#define GPI_FIQ_END (GPI_FIQ_START + 94) ++#define GPI_FIQ_NUM (GPI_FIQ_END - GPI_FIQ_START) ++ ++ ++#define GPI_IRQ_START 0 ++#define INT_GPI_IRQ_DUMMY00 (GPI_IRQ_START + 0) ++#define INT_GPI_IRQ_DUMMY01 (GPI_IRQ_START + 1) ++#define INT_GPI_IRQ_DUMMY02 (GPI_IRQ_START + 2) ++#define INT_GPI_IRQ_DUMMY03 (GPI_IRQ_START + 3) ++#define INT_GPI_IRQ_DUMMY04 (GPI_IRQ_START + 4) ++#define INT_GPI_IRQ_DUMMY05 (GPI_IRQ_START + 5) ++#define INT_GPI_IRQ_DUMMY06 (GPI_IRQ_START + 6) ++#define INT_GPI_IRQ_DUMMY07 (GPI_IRQ_START + 7) ++#define GPI_IRQ_END (GPI_IRQ_START + 8) ++#define GPI_IRQ_NUM (GPI_IRQ_END - GPI_IRQ_START) +diff --git a/drivers/sstar/include/infinity6e/gpio.h b/drivers/sstar/include/infinity6e/gpio.h +new file mode 100755 +index 000000000000..8f3b4a46b01d +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/gpio.h +@@ -0,0 +1,152 @@ ++/* ++* gpio.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_PM_UART_RX1 0 ++#define PAD_PM_UART_TX1 1 ++#define PAD_PM_UART_RX 2 ++#define PAD_PM_UART_TX 3 ++#define PAD_PM_I2CM_SCL 4 ++#define PAD_PM_I2CM_SDA 5 ++#define PAD_PM_GPIO0 6 ++#define PAD_PM_GPIO1 7 ++#define PAD_PM_GPIO2 8 ++#define PAD_PM_GPIO3 9 ++#define PAD_PM_GPIO4 10 ++#define PAD_PM_GPIO5 11 ++#define PAD_PM_GPIO6 12 ++#define PAD_PM_GPIO7 13 ++#define PAD_PM_GPIO8 14 ++#define PAD_PM_GPIO9 15 ++#define PAD_PM_GPIO10 16 ++#define PAD_PM_SPI_CZ 17 ++#define PAD_PM_SPI_CK 18 ++#define PAD_PM_SPI_DI 19 ++#define PAD_PM_SPI_DO 20 ++#define PAD_PM_SPI_WPZ 21 ++#define PAD_PM_SPI_HLD 22 ++#define PAD_SAR_GPIO0 23 ++#define PAD_SAR_GPIO1 24 ++#define PAD_SAR_GPIO2 25 ++#define PAD_SAR_GPIO3 26 ++#define PAD_SAR_GPIO4 27 ++#define PAD_SAR_GPIO5 28 ++#define PAD_SD0_GPIO0 29 ++#define PAD_SD0_CDZ 30 ++#define PAD_SD0_D1 31 ++#define PAD_SD0_D0 32 ++#define PAD_SD0_CLK 33 ++#define PAD_SD0_CMD 34 ++#define PAD_SD0_D3 35 ++#define PAD_SD0_D2 36 ++#define PAD_I2S0_MCLK 37 ++#define PAD_I2S0_BCK 38 ++#define PAD_I2S0_WCK 39 ++#define PAD_I2S0_DI 40 ++#define PAD_I2S0_DO 41 ++#define PAD_I2C0_SCL 42 ++#define PAD_I2C0_SDA 43 ++#define PAD_ETH_LED0 44 ++#define PAD_ETH_LED1 45 ++#define PAD_FUART_RX 46 ++#define PAD_FUART_TX 47 ++#define PAD_FUART_CTS 48 ++#define PAD_FUART_RTS 49 ++#define PAD_SD1_CDZ 50 ++#define PAD_SD1_D1 51 ++#define PAD_SD1_D0 52 ++#define PAD_SD1_CLK 53 ++#define PAD_SD1_CMD 54 ++#define PAD_SD1_D3 55 ++#define PAD_SD1_D2 56 ++#define PAD_SD1_GPIO0 57 ++#define PAD_SD1_GPIO1 58 ++#define PAD_GPIO0 59 ++#define PAD_GPIO1 60 ++#define PAD_GPIO2 61 ++#define PAD_GPIO3 62 ++#define PAD_GPIO4 63 ++#define PAD_GPIO5 64 ++#define PAD_GPIO6 65 ++#define PAD_GPIO7 66 ++#define PAD_SR0_IO00 67 ++#define PAD_SR0_IO01 68 ++#define PAD_SR0_IO02 69 ++#define PAD_SR0_IO03 70 ++#define PAD_SR0_IO04 71 ++#define PAD_SR0_IO05 72 ++#define PAD_SR0_IO06 73 ++#define PAD_SR0_IO07 74 ++#define PAD_SR0_IO08 75 ++#define PAD_SR0_IO09 76 ++#define PAD_SR0_IO10 77 ++#define PAD_SR0_IO11 78 ++#define PAD_SR0_IO12 79 ++#define PAD_SR0_IO13 80 ++#define PAD_SR0_IO14 81 ++#define PAD_SR0_IO15 82 ++#define PAD_SR0_IO16 83 ++#define PAD_SR0_IO17 84 ++#define PAD_SR0_IO18 85 ++#define PAD_SR0_IO19 86 ++#define PAD_SR1_IO00 87 ++#define PAD_SR1_IO01 88 ++#define PAD_SR1_IO02 89 ++#define PAD_SR1_IO03 90 ++#define PAD_SR1_IO04 91 ++#define PAD_SR1_IO05 92 ++#define PAD_SR1_IO06 93 ++#define PAD_SR1_IO07 94 ++#define PAD_SR1_IO08 95 ++#define PAD_SR1_IO09 96 ++#define PAD_SR1_IO10 97 ++#define PAD_SR1_IO11 98 ++#define PAD_SR1_IO12 99 ++#define PAD_SR1_IO13 100 ++#define PAD_SR1_IO14 101 ++#define PAD_SR1_IO15 102 ++#define PAD_SR1_IO16 103 ++#define PAD_SR1_IO17 104 ++#define PAD_SR1_IO18 105 ++#define PAD_SR1_IO19 106 ++#define PAD_GPIO8 107 ++#define PAD_GPIO9 108 ++#define PAD_GPIO10 109 ++#define PAD_GPIO11 110 ++#define PAD_GPIO12 111 ++#define PAD_GPIO13 112 ++#define PAD_GPIO14 113 ++#define PAD_GPIO15 114 ++#define PAD_SPI_CZ 115 ++#define PAD_SPI_CK 116 ++#define PAD_SPI_DI 117 ++#define PAD_SPI_DO 118 ++#define PAD_SPI_WPZ 119 ++#define PAD_SPI_HLD 120 ++#define PAD_ETH_RN 121 ++#define PAD_ETH_RP 122 ++#define PAD_ETH_TN 123 ++#define PAD_ETH_TP 124 ++#define PAD_USB2_DM 125 ++#define PAD_USB2_DP 126 ++ ++#define GPIO_NR 127 ++#define PAD_UNKNOWN 0xFFFF ++ ++#endif // #ifndef ___GPIO_H +diff --git a/drivers/sstar/include/infinity6e/iopow.h b/drivers/sstar/include/infinity6e/iopow.h +new file mode 100755 +index 000000000000..c906ad9d6c51 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/iopow.h +@@ -0,0 +1,32 @@ ++/* ++* iopow.h- Sigmastar ++* ++* Copyright (C) 2019 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___IOPOW_H ++#define ___IOPOW_H ++ ++#define PM_SAR_ATOP_LDO18 (0x73<<2) ++#define PM_SAR_ATOP_LDO18_BIT 3 ++#define PM_SAR_ATOP_LDO18_VAL_18V 0 ++#define PM_SAR_ATOP_LDO18_VAL_33V 1 ++ ++ ++#define PM_SAR_ATOP_VDDP1 (0x10<<2) ++#define PM_SAR_ATOP_VDDP1_BIT 2 ++#define PM_SAR_ATOP_VDDP1_VAL_18V 0 ++#define PM_SAR_ATOP_VDDP1_VAL_33V 1 ++ ++#endif // ___IOPOW_H +diff --git a/drivers/sstar/include/infinity6e/irqs.h b/drivers/sstar/include/infinity6e/irqs.h +new file mode 100755 +index 000000000000..630668f85045 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/irqs.h +@@ -0,0 +1,154 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++#include "gpi-irqs.h" ++#include "pmsleep-irqs.h" ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_SAR_GPIO_WK (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_PM_UART (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_SAR1 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_PIR_RX (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DIG_TOP (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_PIR_TX (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_SAR_KP (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_MIIC_2 (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_MASTER_IIC (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_MMU (GIC_SPI_MS_IRQ_START + 14) ++#define INT_IRQ_OTP (GIC_SPI_MS_IRQ_START + 15) ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_SD (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_MHE (GIC_SPI_MS_IRQ_START + 21) ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) ++#define INT_IRQ_USB3_GP2TOP (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_LDC_FEYE (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_PM_DIP (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_IVE (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_BOOT_TOP (GIC_SPI_MS_IRQ_START + 52) ++#define INT_IRQ_DLA_TOP (GIC_SPI_MS_IRQ_START + 53) ++#define INT_IRQ_TX_CSI (GIC_SPI_MS_IRQ_START + 54) ++#define INT_IRQ_USB3_PHY (GIC_SPI_MS_IRQ_START + 55) ++#define INT_IRQ_GPI_OUT (GIC_SPI_MS_IRQ_START + 56) ++#define INT_IRQ_VIF (GIC_SPI_MS_IRQ_START + 57) ++#define INT_IRQ_SC1_TOP_INT (GIC_SPI_MS_IRQ_START + 58) ++#define INT_IRQ_SC2_TOP_INT (GIC_SPI_MS_IRQ_START + 59) ++#define INT_IRQ_MOVEDMA (GIC_SPI_MS_IRQ_START + 60) ++#define INT_IRQ_BDMA_2 (GIC_SPI_MS_IRQ_START + 61) ++#define INT_IRQ_BDMA_3 (GIC_SPI_MS_IRQ_START + 62) ++#define INT_IRQ_DIP0 (GIC_SPI_MS_IRQ_START + 63) ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_PIR_TOP (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_PWM_TOP (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_DUMMY_8 (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_9 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_DUMMY_12 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ_0 (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SD_CDZ_1 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_DUMMY_25 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_DUMMY_26 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_DUMMY_27 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_DUMMY_28 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_DUMMY_29 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_DUMMY_30 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_DUMMY_31 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/sstar/include/infinity6e/mcm_id.h b/drivers/sstar/include/infinity6e/mcm_id.h +new file mode 100755 +index 000000000000..6769ad536845 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/mcm_id.h +@@ -0,0 +1,98 @@ ++/* ++* mcm_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_START (0) ++#define MCM_ID_MCU51 (MCM_ID_START+0) ++#define MCM_ID_URDMA (MCM_ID_START+1) ++#define MCM_ID_BDMA (MCM_ID_START+2) ++#define MCM_ID_MFE (MCM_ID_START+3) ++#define MCM_ID_JPE (MCM_ID_START+4) ++#define MCM_ID_BACH (MCM_ID_START+5) ++#define MCM_ID_FILE (MCM_ID_START+6) ++#define MCM_ID_UHC0 (MCM_ID_START+7) ++#define MCM_ID_EMAC (MCM_ID_START+8) ++#define MCM_ID_CMDQ (MCM_ID_START+9) ++#define MCM_ID_ISP_DNR (MCM_ID_START+10) ++#define MCM_ID_ISP_DMA (MCM_ID_START+11) ++#define MCM_ID_GOP0 (MCM_ID_START+12) ++#define MCM_ID_SC_DNR (MCM_ID_START+13) ++#define MCM_ID_SC_DNR_SAD (MCM_ID_START+14) ++#define MCM_ID_SC_CROP (MCM_ID_START+15) ++#define MCM_ID_SC1_FRM (MCM_ID_START+16) ++#define MCM_ID_SC1_SNP (MCM_ID_START+17) ++#define MCM_ID_SC1_DBG (MCM_ID_START+18) ++#define MCM_ID_SC2_FRM (MCM_ID_START+19) ++#define MCM_ID_SC3_FRM (MCM_ID_START+20) ++#define MCM_ID_FCIE (MCM_ID_START+21) ++#define MCM_ID_SDIO (MCM_ID_START+22) ++#define MCM_ID_SC1_SNPI (MCM_ID_START+23) ++#define MCM_ID_SC2_SNPI (MCM_ID_START+24) ++#define MCM_ID_CMDQ1 (MCM_ID_START+25) ++#define MCM_ID_CMDQ2 (MCM_ID_START+26) ++#define MCM_ID_GOP1 (MCM_ID_START+27) ++#define MCM_ID_GOP2 (MCM_ID_START+28) ++#define MCM_ID_UHC1 (MCM_ID_START+29) ++#define MCM_ID_IVE (MCM_ID_START+30) ++#define MCM_ID_VHE (MCM_ID_START+31) ++#define MCM_ID_END (MCM_ID_START+32) ++#define MCM_ID_ALL (256) ++ ++ ++#define OFFSET_MCM_DIG_GP_START (BASE_REG_MCM_DIG_GP_PA+0x0) ++#define OFFSET_MCM_ID_MCU51 (OFFSET_MCM_DIG_GP_START+(0x0<<2) ) ++#define OFFSET_MCM_ID_URDMA (OFFSET_MCM_DIG_GP_START+(0x0<<2)+1) ++#define OFFSET_MCM_ID_BDMA (OFFSET_MCM_DIG_GP_START+(0x1<<2) ) ++ ++ ++#define OFFSET_MCM_SC_GP_START (BASE_REG_MCM_SC_GP_PA+0x10) ++#define OFFSET_MCM_ID_MFE (OFFSET_MCM_SC_GP_START+(0x0<<2) ) ++#define OFFSET_MCM_ID_JPE (OFFSET_MCM_SC_GP_START+(0x0<<2)+1) ++#define OFFSET_MCM_ID_BACH (OFFSET_MCM_SC_GP_START+(0x1<<2) ) ++#define OFFSET_MCM_ID_FILE (OFFSET_MCM_SC_GP_START+(0x1<<2)+1) ++#define OFFSET_MCM_ID_UHC0 (OFFSET_MCM_SC_GP_START+(0x2<<2) ) ++#define OFFSET_MCM_ID_EMAC (OFFSET_MCM_SC_GP_START+(0x2<<2)+1) ++#define OFFSET_MCM_ID_CMDQ (OFFSET_MCM_SC_GP_START+(0x3<<2) ) ++#define OFFSET_MCM_ID_ISP_DNR (OFFSET_MCM_SC_GP_START+(0x3<<2)+1) ++#define OFFSET_MCM_ID_ISP_DMA (OFFSET_MCM_SC_GP_START+(0x4<<2) ) ++#define OFFSET_MCM_ID_GOP0 (OFFSET_MCM_SC_GP_START+(0x4<<2)+1) ++#define OFFSET_MCM_ID_SC_DNR (OFFSET_MCM_SC_GP_START+(0x5<<2) ) ++#define OFFSET_MCM_ID_SC_DNR_SAD (OFFSET_MCM_SC_GP_START+(0x5<<2)+1) ++#define OFFSET_MCM_ID_SC_CROP (OFFSET_MCM_SC_GP_START+(0x6<<2) ) ++#define OFFSET_MCM_ID_SC1_FRM (OFFSET_MCM_SC_GP_START+(0x6<<2)+1) ++#define OFFSET_MCM_ID_SC1_SNP (OFFSET_MCM_SC_GP_START+(0x7<<2) ) ++#define OFFSET_MCM_ID_SC1_DBG (OFFSET_MCM_SC_GP_START+(0x7<<2)+1) ++#define OFFSET_MCM_ID_SC2_FRM (OFFSET_MCM_SC_GP_START+(0x8<<2) ) ++#define OFFSET_MCM_ID_SC3_FRM (OFFSET_MCM_SC_GP_START+(0x8<<2)+1) ++#define OFFSET_MCM_ID_FCIE (OFFSET_MCM_SC_GP_START+(0x9<<2) ) ++#define OFFSET_MCM_ID_SDIO (OFFSET_MCM_SC_GP_START+(0x9<<2)+1) ++#define OFFSET_MCM_ID_SC1_SNPI (OFFSET_MCM_SC_GP_START+(0xA<<2) ) ++#define OFFSET_MCM_ID_SC2_SNPI (OFFSET_MCM_SC_GP_START+(0xA<<2)+1) ++#define OFFSET_MCM_ID_CMDQ1 (OFFSET_MCM_SC_GP_START+(0xB<<2) ) ++#define OFFSET_MCM_ID_CMDQ2 (OFFSET_MCM_SC_GP_START+(0xB<<2)+1) ++#define OFFSET_MCM_ID_GOP1 (OFFSET_MCM_SC_GP_START+(0xD<<2) ) ++#define OFFSET_MCM_ID_GOP2 (OFFSET_MCM_SC_GP_START+(0xD<<2)+1) ++#define OFFSET_MCM_ID_UHC1 (OFFSET_MCM_SC_GP_START+(0xE<<2) ) ++#define OFFSET_MCM_ID_IVE (OFFSET_MCM_SC_GP_START+(0xE<<2)+1) ++ ++ ++#define OFFSET_MCM_VHE_GP_START (BASE_REG_MCM_VHE_GP_PA+0x30) ++#define OFFSET_MCM_ID_VHE (OFFSET_MCM_VHE_GP_START+(0x0<<2) ) ++ ++#endif +diff --git a/drivers/sstar/include/infinity6e/mdrv_miu.h b/drivers/sstar/include/infinity6e/mdrv_miu.h +new file mode 100755 +index 000000000000..f0ba8ee52ead +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/mdrv_miu.h +@@ -0,0 +1,280 @@ ++/* ++* mdrv_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_MIU_H__ ++#define __MDRV_MIU_H__ ++ ++#ifdef CONFIG_64BIT ++ typedef unsigned long phy_addr; // 4 bytes ++#else ++ typedef unsigned long long phy_addr; // 8 bytes ++#endif ++ ++#define MMU_ADDR_TO_REGION(addr) ((addr >> 27) & 0xF) ++#define MMU_ADDR_TO_ENTRY(addr) ((addr >> 17) & 0x3FF) ++#define MMU_PAGE_SIZE (0x20000) //128KB ++ ++#define MMU_ADDR_TO_REGION_256(addr) ((addr >> 28) & 0x7) ++#define MMU_ADDR_TO_ENTRY_256(addr) ((addr >> 18) & 0x3FF) ++#define MMU_PAGE_SIZE_256 (0x40000) //256KB ++ ++//------------------------------------------------------------------------------------------------- ++// Enumeration Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ // group 0 ++ MIU_CLIENT_NONE, //none can access ++ MIU_CLIENT_VEN_R, ++ MIU_CLIENT_VEN_W, ++ MIU_CLIENT_USB30_RW, ++ MIU_CLIENT_JPE_R, ++ MIU_CLIENT_JPE_W, ++ MIU_CLIENT_BACH_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ MIU_CLIENT_LDCFeye_RW, ++ MIU_CLIENT_DUMMY_G0CF, ++ // group 1 ++ MIU_CLIENT_CMDQ0_R, ++ MIU_CLIENT_ISP_DMA_W, ++ MIU_CLIENT_ISP_DMA_R, ++ MIU_CLIENT_ISP_ROT_R, ++ MIU_CLIENT_ISP_MLOAD_STA, ++ MIU_CLIENT_GOP, ++ MIU_CLIENT_DUMMY_G1C6, ++ MIU_CLIENT_DIP0_R, ++ MIU_CLIENT_DIP0_W, ++ MIU_CLIENT_SC0_FRAME_W, ++ MIU_CLIENT_SC0_FRAME_R, ++ MIU_CLIENT_SC0_DBG_R, ++ MIU_CLIENT_SC1_FRAME_W, ++ MIU_CLIENT_SC2_FRAME_W, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SDIO30_RW, ++ // group 2 ++ MIU_CLIENT_DUMMY_G2C0, ++ MIU_CLIENT_CSI_TX_R, ++ MIU_CLIENT_DUMMY_G2C2, ++ MIU_CLIENT_ISP_DMAG_RW, ++ MIU_CLIENT_GOP1_R, ++ MIU_CLIENT_GOP2_R, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_MIIC2_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_3DNR0_W, ++ MIU_CLIENT_3DNR0_R, ++ MIU_CLIENT_DLA_RW, ++ MIU_CLIENT_DUMMY_G2CC, ++ MIU_CLIENT_DUMMY_G2CD, ++ MIU_CLIENT_MIIC0_RW, ++ MIU_CLIENT_IVE_RW, ++ // group 3 ++ MIU_CLIENT_DIAMOND_RW, ++ MIU_CLIENT_DUMMY_G3C1, ++ MIU_CLIENT_DUMMY_G3C2, ++ MIU_CLIENT_DUMMY_G3C3, ++ MIU_CLIENT_DUMMY_G3C4, ++ MIU_CLIENT_DUMMY_G3C5, ++ MIU_CLIENT_DUMMY_G3C6, ++ MIU_CLIENT_DUMMY_G3C7, ++ MIU_CLIENT_DUMMY_G3C8, ++ MIU_CLIENT_DUMMY_G3C9, ++ MIU_CLIENT_DUMMY_G3CA, ++ MIU_CLIENT_DUMMY_G3CB, ++ MIU_CLIENT_DUMMY_G3CC, ++ MIU_CLIENT_DUMMY_G3CD, ++ MIU_CLIENT_DUMMY_G3CE, ++ MIU_CLIENT_DUMMY_G3CF, ++ // group 4 ++ MIU_CLIENT_DUMMY_G4C0, ++ MIU_CLIENT_DUMMY_G4C1, ++ MIU_CLIENT_DUMMY_G4C2, ++ MIU_CLIENT_DUMMY_G4C3, ++ MIU_CLIENT_DUMMY_G4C4, ++ MIU_CLIENT_DUMMY_G4C5, ++ MIU_CLIENT_DUMMY_G4C6, ++ MIU_CLIENT_DUMMY_G4C7, ++ MIU_CLIENT_DUMMY_G4C8, ++ MIU_CLIENT_DUMMY_G4C9, ++ MIU_CLIENT_DUMMY_G4CA, ++ MIU_CLIENT_DUMMY_G4CB, ++ MIU_CLIENT_DUMMY_G4CC, ++ MIU_CLIENT_DUMMY_G4CD, ++ MIU_CLIENT_DUMMY_G4CE, ++ MIU_CLIENT_DUMMY_G4CF, ++ // group 5 ++ MIU_CLIENT_DUMMY_G5C0, ++ MIU_CLIENT_DUMMY_G5C1, ++ MIU_CLIENT_DUMMY_G5C2, ++ MIU_CLIENT_DUMMY_G5C3, ++ MIU_CLIENT_DUMMY_G5C4, ++ MIU_CLIENT_DUMMY_G5C5, ++ MIU_CLIENT_DUMMY_G5C6, ++ MIU_CLIENT_DUMMY_G5C7, ++ MIU_CLIENT_DUMMY_G5C8, ++ MIU_CLIENT_DUMMY_G5C9, ++ MIU_CLIENT_DUMMY_G5CA, ++ MIU_CLIENT_DUMMY_G5CB, ++ MIU_CLIENT_DUMMY_G5CC, ++ MIU_CLIENT_DUMMY_G5CD, ++ MIU_CLIENT_DUMMY_G5CE, ++ MIU_CLIENT_DUMMY_G5CF, ++ // group 6 ++ MIU_CLIENT_DUMMY_G6C0, ++ MIU_CLIENT_DUMMY_G6C1, ++ MIU_CLIENT_DUMMY_G6C2, ++ MIU_CLIENT_DUMMY_G6C3, ++ MIU_CLIENT_DUMMY_G6C4, ++ MIU_CLIENT_DUMMY_G6C5, ++ MIU_CLIENT_DUMMY_G6C6, ++ MIU_CLIENT_DUMMY_G6C7, ++ MIU_CLIENT_DUMMY_G6C8, ++ MIU_CLIENT_DUMMY_G6C9, ++ MIU_CLIENT_DUMMY_G6CA, ++ MIU_CLIENT_DUMMY_G6CB, ++ MIU_CLIENT_DUMMY_G6CC, ++ MIU_CLIENT_DUMMY_G6CD, ++ MIU_CLIENT_DUMMY_G6CE, ++ MIU_CLIENT_DUMMY_G6CF, ++ // group 7 ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_DLA_HIWAY, ++ MIU_CLIENT_DUMMY_G7C2, ++ MIU_CLIENT_DUMMY_G7C3, ++ MIU_CLIENT_DUMMY_G7C4, ++ MIU_CLIENT_DUMMY_G7C5, ++ MIU_CLIENT_DUMMY_G7C6, ++ MIU_CLIENT_DUMMY_G7C7, ++ MIU_CLIENT_DUMMY_G7C8, ++ MIU_CLIENT_DUMMY_G7C9, ++ MIU_CLIENT_DUMMY_G7CA, ++ MIU_CLIENT_DUMMY_G7CB, ++ MIU_CLIENT_DUMMY_G7CC, ++ MIU_CLIENT_DUMMY_G7CD, ++ MIU_CLIENT_DUMMY_G7CE, ++ MIU_CLIENT_DUMMY_G7CF, ++} eMIUClientID; ++ ++typedef enum ++{ ++ E_MIU_0 = 0, ++ E_MIU_1, ++ E_MIU_2, ++ E_MIU_3, ++ E_MIU_NUM, ++} MIU_ID; ++ ++typedef enum ++{ ++ E_PROTECT_0 = 0, ++ E_PROTECT_1, ++ E_PROTECT_2, ++ E_PROTECT_3, ++ E_PROTECT_4, ++ E_SLIT_0 = 16, ++ E_MIU_PROTECT_NUM, ++} PROTECT_ID; ++ ++#ifdef CONFIG_MIU_HW_MMU ++typedef enum ++{ ++ E_MMU_STATUS_NORMAL = 0, ++ E_MMU_STATUS_RW_COLLISION = 0x1, ++ E_MMU_STATUS_R_INVALID = 0x2, ++ E_MMU_STATUS_W_INVALID = 0x4, ++ E_MMU_STATUS_NUM, ++} MMU_STATUS; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Structure Define ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ unsigned char bHit; ++ unsigned char u8Group; ++ unsigned char u8ClientID; ++ unsigned char u8Block; ++ unsigned int uAddress; ++} MIU_PortectInfo; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++#define CONFIG_MIU_HW_MMU ++#ifdef CONFIG_MIU_HW_MMU ++#define CONFIG_MMU_INTERRUPT_ENABLE ++ ++// MDrv_MMU_Callback parameter: [IRQ Status] [Phyical Address Entry] [Client ID] [Is Write Command] ++typedef void (*MDrv_MMU_Callback)(unsigned int, unsigned short, unsigned short, unsigned char); ++#endif ++ ++unsigned char MDrv_MIU_Init(void); ++unsigned short* MDrv_MIU_GetDefaultClientID_KernelProtect(void); ++unsigned short* MDrv_MIU_GetClientID_KernelProtect(unsigned char u8MiuSel); ++ ++unsigned char MDrv_MIU_Protect( unsigned char u8Blockx, ++ unsigned short *pu8ProtectId, ++ phy_addr u64BusStart, ++ phy_addr u64BusEnd, ++ unsigned char bSetFlag); ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++unsigned char MDrv_MIU_GetProtectInfo(unsigned char u8MiuDev, MIU_PortectInfo *pInfo); ++#endif ++unsigned char MDrv_MIU_Slits(unsigned char u8Blockx, phy_addr u64SlitsStart, phy_addr u65SlitsEnd, unsigned char bSetFlag); ++unsigned char MDrv_MIU_Get_IDEnables_Value(unsigned char u8MiuDev, unsigned char u8Blockx, unsigned char u8ClientIndex); ++unsigned int MDrv_MIU_ProtectDramSize(void); ++int MDrv_MIU_ClientIdToName(unsigned short clientId, char *clientName); ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo); ++ ++#ifdef CONFIG_MIU_HW_MMU ++int MDrv_MMU_SetPageSize(unsigned char u8PgSz256En); ++int MDrv_MMU_SetRegion(unsigned short u16Region, unsigned short u16ReplaceRegion); ++int MDrv_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry); ++unsigned short MDrv_MMU_MapQuery(unsigned short u16PhyAddrEntry); ++int MDrv_MMU_UnMap(unsigned short u16PhyAddrEntry); ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++void MDrv_MMU_CallbackFunc(MDrv_MMU_Callback pFuncPtr); ++#endif ++int MDrv_MMU_Enable(unsigned char u8Enable); ++int MDrv_MMU_Reset(void); ++unsigned int MDrv_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsWriteCmd); ++#endif ++ ++#endif // __MDRV_MIU_H__ +diff --git a/drivers/sstar/include/infinity6e/mhal_miu.h b/drivers/sstar/include/infinity6e/mhal_miu.h +new file mode 100755 +index 000000000000..e71b33abb95d +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/mhal_miu.h +@@ -0,0 +1,115 @@ ++/* ++* mhal_miu.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MHAL_MIU_H_ ++#define _MHAL_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_MAX_DEVICE (1) ++#define MIU_MAX_GROUP (8) ++#define MIU_MAX_GP_CLIENT (16) ++#define MIU_MAX_TBL_CLIENT (MIU_MAX_GROUP*MIU_MAX_GP_CLIENT) ++ ++#define MIU_PAGE_SHIFT (13) // Unit for MIU protect (8KB) ++#define MIU_PROTECT_ADDRESS_UNIT (0x20UL) // Unit for MIU hitted address ++#define MIU_MAX_PROTECT_BLOCK (5) ++#define MIU_MAX_PROTECT_ID (16) ++ ++#define IDNUM_KERNELPROTECT (16) ++#define MMU_INVALID_ENTRY_VAL (0x3FF) ++ ++#ifndef BIT0 ++#define BIT0 0x0001UL ++#define BIT1 0x0002UL ++#define BIT2 0x0004UL ++#define BIT3 0x0008UL ++#define BIT4 0x0010UL ++#define BIT5 0x0020UL ++#define BIT6 0x0040UL ++#define BIT7 0x0080UL ++#define BIT8 0x0100UL ++#define BIT9 0x0200UL ++#define BIT10 0x0400UL ++#define BIT11 0x0800UL ++#define BIT12 0x1000UL ++#define BIT13 0x2000UL ++#define BIT14 0x4000UL ++#define BIT15 0x8000UL ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MIU_BLOCK_0 = 0, ++ E_MIU_BLOCK_1, ++ E_MIU_BLOCK_2, ++ E_MIU_BLOCK_3, ++ E_MIU_BLOCK_4, ++ E_MIU_BLOCK_NUM, ++} MIU_BLOCK_ID; ++ ++typedef enum ++{ ++ E_HAL_MMU_STATUS_NORMAL = 0, ++ E_HAL_MMU_STATUS_RW_COLLISION = 0x1, ++ E_HAL_MMU_STATUS_R_INVALID = 0x2, ++ E_HAL_MMU_STATUS_W_INVALID = 0x4, ++ E_HAL_MMU_STATUS_NUM, ++} HAL_MMU_STATUS; ++ ++typedef struct ++{ ++ unsigned int size; // bytes ++ unsigned int dram_freq; // MHz ++ unsigned int miupll_freq; // MHz ++ unsigned char type; // 2:DDR2, 3:DDR3 ++ unsigned char data_rate; // 4:4x mode, 8:8x mode, ++ unsigned char bus_width; // 16:16bit, 32:32bit, 64:64bit ++ unsigned char ssc; // 0:off, 1:on ++} MIU_DramInfo_Hal; ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuDev, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex); ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void); ++unsigned int HAL_MIU_ProtectDramSize(void); ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName); ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo); ++ ++// MMU HAL Function ++int HAL_MMU_SetPageSize(unsigned char u8PgSz256En); ++int HAL_MMU_SetRegion(unsigned short u16Region, unsigned short u16ReplaceRegion); ++int HAL_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry); ++unsigned short HAL_MMU_MapQuery(unsigned short u16PhyAddrEntry); ++int HAL_MMU_UnMap(unsigned short u16PhyAddrEntry); ++int HAL_MMU_Enable(unsigned char u8Enable); ++int HAL_MMU_Reset(void); ++unsigned int HAL_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsReadCmd); ++ ++#endif // _MHAL_MIU_H_ +diff --git a/drivers/sstar/include/infinity6e/padmux.h b/drivers/sstar/include/infinity6e/padmux.h +new file mode 100755 +index 000000000000..1834279befeb +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/padmux.h +@@ -0,0 +1,294 @@ ++/* ++* padmux.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++ ++#define PINMUX_FOR_EJ_MODE_1 0x01 ++#define PINMUX_FOR_EJ_MODE_2 0x02 ++#define PINMUX_FOR_EJ_MODE_3 0x03 ++#define PINMUX_FOR_DLA_EJ_MODE_1 0x04 ++#define PINMUX_FOR_DLA_EJ_MODE_2 0x05 ++#define PINMUX_FOR_DLA_EJ_MODE_3 0x06 ++#define PINMUX_FOR_TEST_IN_MODE_1 0x07 ++#define PINMUX_FOR_TEST_IN_MODE_2 0x08 ++#define PINMUX_FOR_TEST_IN_MODE_3 0x09 ++#define PINMUX_FOR_TEST_OUT_MODE_1 0x0a ++#define PINMUX_FOR_TEST_OUT_MODE_2 0x0b ++#define PINMUX_FOR_TEST_OUT_MODE_3 0x0c ++#define PINMUX_FOR_SPI_MODE 0x0d ++#define PINMUX_FOR_SPIWPN_MODE 0x0e ++#define PINMUX_FOR_SPIHOLDN_MODE 0x0f ++#define PINMUX_FOR_SPICSZ1_MODE 0x10 ++#define PINMUX_FOR_SPICSZ2_MODE 0x11 ++#define PINMUX_FOR_I2C0_MODE_1 0x12 ++#define PINMUX_FOR_I2C0_MODE_2 0x13 ++#define PINMUX_FOR_I2C0_MODE_3 0x14 ++#define PINMUX_FOR_I2C0_MODE_4 0x15 ++#define PINMUX_FOR_I2C0_MODE_5 0x16 ++#define PINMUX_FOR_I2C1_MODE_1 0x17 ++#define PINMUX_FOR_I2C1_MODE_2 0x18 ++#define PINMUX_FOR_I2C1_MODE_3 0x19 ++#define PINMUX_FOR_I2C2_MODE_1 0x1a ++#define PINMUX_FOR_I2C2_MODE_2 0x1b ++#define PINMUX_FOR_I2C2_MODE_3 0x1c ++#define PINMUX_FOR_I2C2_MODE_4 0x1d ++#define PINMUX_FOR_I2C2_MODE_5 0x1e ++#define PINMUX_FOR_SPI0_MODE_1 0x1f ++#define PINMUX_FOR_SPI0_MODE_2 0x20 ++#define PINMUX_FOR_SPI0_MODE_3 0x21 ++#define PINMUX_FOR_SPI0_MODE_4 0x22 ++#define PINMUX_FOR_SPI1_MODE_1 0x23 ++#define PINMUX_FOR_SPI1_MODE_2 0x24 ++#define PINMUX_FOR_SPI1_MODE_3 0x25 ++#define PINMUX_FOR_SPI1_MODE_4 0x26 ++#define PINMUX_FOR_SPI1_MODE_5 0x27 ++#define PINMUX_FOR_FUART_MODE_1 0x28 ++#define PINMUX_FOR_FUART_MODE_2 0x29 ++#define PINMUX_FOR_FUART_MODE_3 0x2a ++#define PINMUX_FOR_FUART_MODE_4 0x2b ++#define PINMUX_FOR_FUART_MODE_5 0x2c ++#define PINMUX_FOR_FUART_MODE_6 0x2d ++#define PINMUX_FOR_FUART_MODE_7 0x2e ++#define PINMUX_FOR_UART0_MODE_1 0x2f ++#define PINMUX_FOR_UART0_MODE_2 0x30 ++#define PINMUX_FOR_UART0_MODE_3 0x31 ++#define PINMUX_FOR_UART0_MODE_4 0x32 ++#define PINMUX_FOR_UART1_MODE_1 0x33 ++#define PINMUX_FOR_UART1_MODE_2 0x34 ++#define PINMUX_FOR_UART1_MODE_3 0x35 ++#define PINMUX_FOR_UART1_MODE_4 0x36 ++#define PINMUX_FOR_UART1_MODE_5 0x37 ++#define PINMUX_FOR_UART1_MODE_6 0x38 ++#define PINMUX_FOR_SD0_MODE 0x39 ++#define PINMUX_FOR_SD0_CDZ_MODE 0x3a ++#define PINMUX_FOR_SD1_MODE_1 0x3b ++#define PINMUX_FOR_SD1_MODE_2 0x3c ++#define PINMUX_FOR_SD1_CDZ_MODE_1 0x3d ++#define PINMUX_FOR_SD1_CDZ_MODE_2 0x3e ++#define PINMUX_FOR_EMMC0_8B_MODE_1 0x3f ++#define PINMUX_FOR_EMMC0_8B_MODE_2 0x40 ++#define PINMUX_FOR_EMMC0_4B_MODE 0x41 ++#define PINMUX_FOR_EMMC1_4B_MODE_1 0x42 ++#define PINMUX_FOR_EMMC1_4B_MODE_2 0x43 ++#define PINMUX_FOR_EMMC0_RST_MODE 0x44 ++#define PINMUX_FOR_EMMC1_RST_MODE_1 0x45 ++#define PINMUX_FOR_EMMC1_RST_MODE_2 0x46 ++#define PINMUX_FOR_PWM0_MODE_1 0x47 ++#define PINMUX_FOR_PWM0_MODE_2 0x48 ++#define PINMUX_FOR_PWM0_MODE_3 0x49 ++#define PINMUX_FOR_PWM0_MODE_4 0x4a ++#define PINMUX_FOR_PWM0_MODE_5 0x4b ++#define PINMUX_FOR_PWM0_MODE_6 0x4c ++#define PINMUX_FOR_PWM1_MODE_1 0x4d ++#define PINMUX_FOR_PWM1_MODE_2 0x4e ++#define PINMUX_FOR_PWM1_MODE_3 0x4f ++#define PINMUX_FOR_PWM1_MODE_4 0x50 ++#define PINMUX_FOR_PWM1_MODE_5 0x51 ++#define PINMUX_FOR_PWM1_MODE_6 0x52 ++#define PINMUX_FOR_PWM2_MODE_1 0x53 ++#define PINMUX_FOR_PWM2_MODE_2 0x54 ++#define PINMUX_FOR_PWM2_MODE_3 0x55 ++#define PINMUX_FOR_PWM2_MODE_4 0x56 ++#define PINMUX_FOR_PWM2_MODE_5 0x57 ++#define PINMUX_FOR_PWM2_MODE_6 0x58 ++#define PINMUX_FOR_PWM3_MODE_1 0x59 ++#define PINMUX_FOR_PWM3_MODE_2 0x5a ++#define PINMUX_FOR_PWM3_MODE_3 0x5b ++#define PINMUX_FOR_PWM3_MODE_4 0x5c ++#define PINMUX_FOR_PWM3_MODE_5 0x5d ++#define PINMUX_FOR_PWM3_MODE_6 0x5e ++#define PINMUX_FOR_PWM4_MODE_1 0x5f ++#define PINMUX_FOR_PWM4_MODE_2 0x60 ++#define PINMUX_FOR_PWM4_MODE_3 0x61 ++#define PINMUX_FOR_PWM4_MODE_4 0x62 ++#define PINMUX_FOR_PWM4_MODE_5 0x63 ++#define PINMUX_FOR_PWM4_MODE_6 0x64 ++#define PINMUX_FOR_PWM5_MODE_1 0x65 ++#define PINMUX_FOR_PWM5_MODE_2 0x66 ++#define PINMUX_FOR_PWM5_MODE_3 0x67 ++#define PINMUX_FOR_PWM5_MODE_4 0x68 ++#define PINMUX_FOR_PWM5_MODE_5 0x69 ++#define PINMUX_FOR_PWM5_MODE_6 0x6a ++#define PINMUX_FOR_PWM6_MODE_1 0x6b ++#define PINMUX_FOR_PWM6_MODE_2 0x6c ++#define PINMUX_FOR_PWM6_MODE_3 0x6d ++#define PINMUX_FOR_PWM6_MODE_4 0x6e ++#define PINMUX_FOR_PWM6_MODE_5 0x6f ++#define PINMUX_FOR_PWM6_MODE_6 0x70 ++#define PINMUX_FOR_PWM7_MODE_1 0x71 ++#define PINMUX_FOR_PWM7_MODE_2 0x72 ++#define PINMUX_FOR_PWM7_MODE_3 0x73 ++#define PINMUX_FOR_PWM7_MODE_4 0x74 ++#define PINMUX_FOR_PWM7_MODE_5 0x75 ++#define PINMUX_FOR_PWM7_MODE_6 0x76 ++#define PINMUX_FOR_PWM8_MODE_1 0x77 ++#define PINMUX_FOR_PWM8_MODE_2 0x78 ++#define PINMUX_FOR_PWM8_MODE_3 0x79 ++#define PINMUX_FOR_PWM8_MODE_4 0x7a ++#define PINMUX_FOR_PWM8_MODE_5 0x7b ++#define PINMUX_FOR_PWM8_MODE_6 0x7c ++#define PINMUX_FOR_PWM8_MODE_7 0x7d ++#define PINMUX_FOR_PWM8_MODE_8 0x7e ++#define PINMUX_FOR_PWM9_MODE_1 0x7f ++#define PINMUX_FOR_PWM9_MODE_2 0x80 ++#define PINMUX_FOR_PWM9_MODE_3 0x81 ++#define PINMUX_FOR_PWM9_MODE_4 0x82 ++#define PINMUX_FOR_PWM9_MODE_5 0x83 ++#define PINMUX_FOR_PWM9_MODE_6 0x84 ++#define PINMUX_FOR_PWM9_MODE_7 0x85 ++#define PINMUX_FOR_PWM9_MODE_8 0x86 ++#define PINMUX_FOR_ETH_MODE 0x87 ++#define PINMUX_FOR_LED0_MODE_1 0x88 ++#define PINMUX_FOR_LED0_MODE_2 0x89 ++#define PINMUX_FOR_LED0_MODE_3 0x8a ++#define PINMUX_FOR_LED0_MODE_4 0x8b ++#define PINMUX_FOR_LED1_MODE_1 0x8c ++#define PINMUX_FOR_LED1_MODE_2 0x8d ++#define PINMUX_FOR_LED1_MODE_3 0x8e ++#define PINMUX_FOR_LED1_MODE_4 0x8f ++#define PINMUX_FOR_I2S_MCK_MODE_1 0x90 ++#define PINMUX_FOR_I2S_MCK_MODE_2 0x91 ++#define PINMUX_FOR_I2S_MCK_MODE_3 0x92 ++#define PINMUX_FOR_I2S_MCK_MODE_4 0x93 ++#define PINMUX_FOR_I2S_RX_MODE_1 0x94 ++#define PINMUX_FOR_I2S_RX_MODE_2 0x95 ++#define PINMUX_FOR_I2S_RX_MODE_3 0x96 ++#define PINMUX_FOR_I2S_RX_MODE_4 0x97 ++#define PINMUX_FOR_I2S_TX_MODE_1 0x98 ++#define PINMUX_FOR_I2S_TX_MODE_2 0x99 ++#define PINMUX_FOR_I2S_TX_MODE_3 0x9a ++#define PINMUX_FOR_I2S_TX_MODE_4 0x9b ++#define PINMUX_FOR_I2S_TX_MODE_5 0x9c ++#define PINMUX_FOR_I2S_TX_MODE_6 0x9d ++#define PINMUX_FOR_I2S_TX_MODE_7 0x9e ++#define PINMUX_FOR_I2S_RXTX_MODE_1 0x9f ++#define PINMUX_FOR_I2S_RXTX_MODE_2 0xa0 ++#define PINMUX_FOR_I2S_RXTX_MODE_3 0xa1 ++#define PINMUX_FOR_I2S_RXTX_MODE_4 0xa2 ++#define PINMUX_FOR_I2S_RXTX_MODE_5 0xa3 ++#define PINMUX_FOR_I2S_RXTX_MODE_6 0xa4 ++#define PINMUX_FOR_DMIC_MODE_1 0xa5 ++#define PINMUX_FOR_DMIC_MODE_2 0xa6 ++#define PINMUX_FOR_DMIC_MODE_3 0xa7 ++#define PINMUX_FOR_DMIC_MODE_4 0xa8 ++#define PINMUX_FOR_DMIC_MODE_5 0xa9 ++#define PINMUX_FOR_DMIC_MODE_6 0xaa ++#define PINMUX_FOR_DMIC_MODE_7 0xab ++#define PINMUX_FOR_DMIC_MODE_8 0xac ++#define PINMUX_FOR_SR00_MIPI_MODE_1 0xad ++#define PINMUX_FOR_SR00_MIPI_MODE_2 0xae ++#define PINMUX_FOR_SR00_MIPI_MODE_3 0xaf ++#define PINMUX_FOR_SR00_MIPI_MODE_4 0xb0 ++#define PINMUX_FOR_SR00_CTRL_MODE 0xb1 ++#define PINMUX_FOR_SR00_MCLK_MODE 0xb2 ++#define PINMUX_FOR_SR00_RST_MODE 0xb3 ++#define PINMUX_FOR_SR00_PDN_MODE_1 0xb4 ++#define PINMUX_FOR_SR00_PDN_MODE_2 0xb5 ++#define PINMUX_FOR_SR01_MIPI_MODE 0xb6 ++#define PINMUX_FOR_SR01_CTRL_MODE 0xb7 ++#define PINMUX_FOR_SR01_MCLK_MODE 0xb8 ++#define PINMUX_FOR_SR01_RST_MODE_1 0xb9 ++#define PINMUX_FOR_SR01_RST_MODE_2 0xba ++#define PINMUX_FOR_SR0_BT601_MODE_1 0xbb ++#define PINMUX_FOR_SR0_BT601_MODE_2 0xbc ++#define PINMUX_FOR_SR0_BT656_MODE_1 0xbd ++#define PINMUX_FOR_SR0_BT656_MODE_2 0xbe ++#define PINMUX_FOR_SR0_BT656_MODE_3 0xbf ++#define PINMUX_FOR_SR1_MIPI_MODE_1 0xc0 ++#define PINMUX_FOR_SR1_MIPI_MODE_2 0xc1 ++#define PINMUX_FOR_SR1_MIPI_MODE_3 0xc2 ++#define PINMUX_FOR_SR1_MIPI_MODE_4 0xc3 ++#define PINMUX_FOR_SR1_MIPI_MODE_5 0xc4 ++#define PINMUX_FOR_SR1_CTRL_MODE 0xc5 ++#define PINMUX_FOR_SR1_MCLK_MODE_1 0xc6 ++#define PINMUX_FOR_SR1_MCLK_MODE_2 0xc7 ++#define PINMUX_FOR_SR1_RST_MODE_1 0xc8 ++#define PINMUX_FOR_SR1_RST_MODE_2 0xc9 ++#define PINMUX_FOR_SR1_BT601_MODE 0xca ++#define PINMUX_FOR_SR1_BT656_MODE 0xcb ++#define PINMUX_FOR_MIPI_TX_MODE_1 0xcc ++#define PINMUX_FOR_MIPI_TX_MODE_2 0xcd ++#define PINMUX_FOR_MIPI_TX_MODE_3 0xce ++#define PINMUX_FOR_MIPI_TX_MODE_4 0xcf ++#define PINMUX_FOR_TTL24_MODE 0xd0 ++#define PINMUX_FOR_TTL16_MODE_1 0xd1 ++#define PINMUX_FOR_TTL16_MODE_2 0xd2 ++#define PINMUX_FOR_TTL16_MODE_3 0xd3 ++#define PINMUX_FOR_TTL16_MODE_4 0xd4 ++#define PINMUX_FOR_BT656_OUT_MODE_1 0xd5 ++#define PINMUX_FOR_BT656_OUT_MODE_2 0xd6 ++#define PINMUX_FOR_BT656_OUT_MODE_3 0xd7 ++#define PINMUX_FOR_OTP_TEST 0xd8 ++ ++#define PINMUX_FOR_PM_SPI_MODE 0xd9 ++#define PINMUX_FOR_PM_SPIWPN_MODE 0xda ++#define PINMUX_FOR_PM_SPIHOLDN_MODE 0xdb ++#define PINMUX_FOR_PM_SPICSZ1_MODE 0xdc ++#define PINMUX_FOR_PM_SPICSZ2_MODE 0xdd ++#define PINMUX_FOR_PM_VID_MODE_1 0xde ++#define PINMUX_FOR_PM_VID_MODE_2 0xdf ++#define PINMUX_FOR_PM_PIR_SERIN_MODE_1 0xe0 ++#define PINMUX_FOR_PM_PIR_SERIN_MODE_2 0xe1 ++#define PINMUX_FOR_PM_PIR_DIR_LINK_MODE_1 0xe2 ++#define PINMUX_FOR_PM_PIR_DIR_LINK_MODE_2 0xe3 ++#define PINMUX_FOR_PM_I2CM_MODE_1 0xe4 ++#define PINMUX_FOR_PM_I2CM_MODE_2 0xe5 ++#define PINMUX_FOR_PM_PWM0_MODE_1 0xe6 ++#define PINMUX_FOR_PM_PWM0_MODE_2 0xe7 ++#define PINMUX_FOR_PM_UART1_MODE_1 0xe8 ++#define PINMUX_FOR_PM_UART1_MODE_2 0xe9 ++#define PINMUX_FOR_PM_PM51_UART_MODE_1 0xea ++#define PINMUX_FOR_PM_PM51_UART_MODE_2 0xeb ++#define PINMUX_FOR_PM_PM51_UART_MODE_3 0xec ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_0 0xed ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_1 0xee ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_2 0xef ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_3 0xf0 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_4 0xf1 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_5 0xf2 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_6 0xf3 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_7 0xf4 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_8 0xf5 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_9 0xf6 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_10 0xf7 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_11 0xf8 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_12 0xf9 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_13 0xfa ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_14 0xfb ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_15 0xfc ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_16 0xfd ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_17 0xfe ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_18 0xff ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_19 0x100 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_20 0x101 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_21 0x102 ++#define PINMUX_FOR_PM_PM_PAD_EXT_MODE_22 0x103 ++#define PINMUX_FOR_PM_PM_UART_IS_MODE 0x104 ++#define PINMUX_FOR_PM_SAR_MODE 0x105 ++ ++ ++// add manually for misc pads here ++#define PINMUX_FOR_USB_MODE 0x106 ++ ++ ++ ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++#endif // ___PADMUX_H +diff --git a/drivers/sstar/include/infinity6e/pmsleep-irqs.h b/drivers/sstar/include/infinity6e/pmsleep-irqs.h +new file mode 100755 +index 000000000000..07a9a4e34845 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/pmsleep-irqs.h +@@ -0,0 +1,130 @@ ++/* ++* irqs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 2 ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_GPIO_5 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_GPIO_6 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_GPIO_10 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_I2CM_SCL (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_I2CM_SDA (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_SPI_WPZ (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_SPI_HLD (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_UART_RX1 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_UART_TX1 (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_UART_TX (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_SAR_GPIO0 (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_SAR_GPIO1 (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_SAR_GPIO2 (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SAR_GPIO3 (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SAR_GPIO4 (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_SAR_GPIO5 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_28 (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_DUMMY_29 (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_32 (PMSLEEP_FIQ_START + 32) ++#define INT_PMSLEEP_DUMMY_33 (PMSLEEP_FIQ_START + 33) ++#define INT_PMSLEEP_DUMMY_34 (PMSLEEP_FIQ_START + 34) ++#define INT_PMSLEEP_DUMMY_35 (PMSLEEP_FIQ_START + 35) ++#define INT_PMSLEEP_DUMMY_36 (PMSLEEP_FIQ_START + 36) ++#define INT_PMSLEEP_DUMMY_37 (PMSLEEP_FIQ_START + 37) ++#define INT_PMSLEEP_DUMMY_38 (PMSLEEP_FIQ_START + 38) ++#define INT_PMSLEEP_DUMMY_39 (PMSLEEP_FIQ_START + 39) ++#define INT_PMSLEEP_DUMMY_40 (PMSLEEP_FIQ_START + 40) ++#define INT_PMSLEEP_DUMMY_41 (PMSLEEP_FIQ_START + 41) ++#define INT_PMSLEEP_DUMMY_42 (PMSLEEP_FIQ_START + 42) ++#define INT_PMSLEEP_DUMMY_43 (PMSLEEP_FIQ_START + 43) ++#define INT_PMSLEEP_DUMMY_44 (PMSLEEP_FIQ_START + 44) ++#define INT_PMSLEEP_DUMMY_45 (PMSLEEP_FIQ_START + 45) ++#define INT_PMSLEEP_DUMMY_46 (PMSLEEP_FIQ_START + 46) ++#define INT_PMSLEEP_DUMMY_47 (PMSLEEP_FIQ_START + 47) ++#define INT_PMSLEEP_DUMMY_48 (PMSLEEP_FIQ_START + 48) ++#define INT_PMSLEEP_DUMMY_49 (PMSLEEP_FIQ_START + 49) ++#define INT_PMSLEEP_DUMMY_50 (PMSLEEP_FIQ_START + 50) ++#define INT_PMSLEEP_DUMMY_51 (PMSLEEP_FIQ_START + 51) ++#define INT_PMSLEEP_DUMMY_52 (PMSLEEP_FIQ_START + 52) ++#define INT_PMSLEEP_DUMMY_53 (PMSLEEP_FIQ_START + 53) ++#define INT_PMSLEEP_DUMMY_54 (PMSLEEP_FIQ_START + 54) ++#define INT_PMSLEEP_DUMMY_55 (PMSLEEP_FIQ_START + 55) ++#define INT_PMSLEEP_DUMMY_56 (PMSLEEP_FIQ_START + 56) ++#define INT_PMSLEEP_DUMMY_57 (PMSLEEP_FIQ_START + 57) ++#define INT_PMSLEEP_DUMMY_58 (PMSLEEP_FIQ_START + 58) ++#define INT_PMSLEEP_DUMMY_59 (PMSLEEP_FIQ_START + 59) ++#define INT_PMSLEEP_DUMMY_60 (PMSLEEP_FIQ_START + 60) ++#define INT_PMSLEEP_DUMMY_61 (PMSLEEP_FIQ_START + 61) ++#define INT_PMSLEEP_DUMMY_62 (PMSLEEP_FIQ_START + 62) ++#define INT_PMSLEEP_DUMMY_63 (PMSLEEP_FIQ_START + 63) ++#define INT_PMSLEEP_DUMMY_64 (PMSLEEP_FIQ_START + 64) ++#define INT_PMSLEEP_DUMMY_65 (PMSLEEP_FIQ_START + 65) ++#define INT_PMSLEEP_DUMMY_66 (PMSLEEP_FIQ_START + 66) ++#define INT_PMSLEEP_DUMMY_67 (PMSLEEP_FIQ_START + 67) ++#define INT_PMSLEEP_DUMMY_68 (PMSLEEP_FIQ_START + 68) ++#define INT_PMSLEEP_DUMMY_69 (PMSLEEP_FIQ_START + 69) ++#define INT_PMSLEEP_DUMMY_70 (PMSLEEP_FIQ_START + 70) ++#define INT_PMSLEEP_DUMMY_71 (PMSLEEP_FIQ_START + 71) ++#define INT_PMSLEEP_DUMMY_72 (PMSLEEP_FIQ_START + 72) ++#define INT_PMSLEEP_DUMMY_73 (PMSLEEP_FIQ_START + 73) ++#define INT_PMSLEEP_DUMMY_74 (PMSLEEP_FIQ_START + 74) ++#define INT_PMSLEEP_DUMMY_75 (PMSLEEP_FIQ_START + 75) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 76) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_DUMMY_00 (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_DUMMY_06 (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_DUMMY_07 (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) +diff --git a/drivers/sstar/include/infinity6e/regMIU.h b/drivers/sstar/include/infinity6e/regMIU.h +new file mode 100755 +index 000000000000..af91a7fce655 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/regMIU.h +@@ -0,0 +1,178 @@ ++/* ++* regMIU.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_MIU_H_ ++#define _REG_MIU_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) ++#define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) ++ ++#define MIU_REG_BASE (0x1200UL) ++#define MIU1_REG_BASE (0x0D00UL) ++#define MIU2_REG_BASE (0x62000UL) ++#define PM_REG_BASE (0x1E00UL) ++#define MIU_ATOP_BASE (0x1000UL) ++#define MIU1_ATOP_BASE (0x0B00UL) ++#define MIU2_ATOP_BASE (0x62100UL) ++#define CHIP_TOP_BASE (0x1E00UL) ++#define MIU_ARB_REG_BASE (0x1100UL) ++#define MIU1_ARB_REG_BASE (0x0C00UL) ++#define MIU2_ARB_REG_BASE (0x62300UL) ++#define MIU_MMU_REG_BASE (0x1300UL) ++ ++#define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3UL) ++#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++#define MIU_PROTECT_DDR_32MB (0x50UL) ++#define MIU_PROTECT_DDR_64MB (0x60UL) ++#define MIU_PROTECT_DDR_128MB (0x70UL) ++#define MIU_PROTECT_DDR_256MB (0x80UL) ++#define MIU_PROTECT_DDR_512MB (0x90UL) ++#define MIU_PROTECT_DDR_1024MB (0xA0UL) ++#define MIU_PROTECT_DDR_2048MB (0xB0UL) ++ ++#define MIU_PROTECT0_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT1_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT2_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT3_EN (MIU_REG_BASE+0xD2UL) ++#define MIU_PROTECT4_EN (MIU_ARB_REG_BASE+0xDEUL) ++#define MIU_PROTECT_ID0 (MIU_REG_BASE+0x2EUL) ++#define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20UL) ++#define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22UL) ++#define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24UL) ++#define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26UL) ++#define MIU_PROTECT4_ID_ENABLE (MIU_ARB_REG_BASE+0xDC) ++#define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT1_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT2_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT3_MSB (MIU_REG_BASE+0xD0UL) ++#define MIU_PROTECT4_MSB (MIU_REG_BASE+0xB2UL) ++#define MIU_PROTECT0_START (MIU_REG_BASE+0xC0UL) ++#define MIU_PROTECT0_END (MIU_REG_BASE+0xC2UL) ++#define MIU_PROTECT1_START (MIU_REG_BASE+0xC4UL) ++#define MIU_PROTECT1_END (MIU_REG_BASE+0xC6UL) ++#define MIU_PROTECT2_START (MIU_REG_BASE+0xC8UL) ++#define MIU_PROTECT2_END (MIU_REG_BASE+0xCAUL) ++#define MIU_PROTECT3_START (MIU_REG_BASE+0xCCUL) ++#define MIU_PROTECT3_END (MIU_REG_BASE+0xCEUL) ++#define MIU_PROTECT4_START (MIU_REG_BASE+0x72UL) ++#define MIU_PROTECT4_END (MIU_REG_BASE+0x92UL) ++#define REG_MIU_PROTECT_LOADDR (0x6DUL << 1) //0xDE ++#define REG_MIU_PROTECT_HIADDR (0x6EUL << 1) //0xDE ++#define REG_MIU_PROTECT_STATUS (0x6FUL << 1) //0xDE ++ ++// MIU selection registers ++#define REG_MIU_SEL0 (MIU_REG_BASE+0xf0UL) //0x12F0 ++#define REG_MIU_SEL1 (MIU_REG_BASE+0xf2UL) //0x12F1 ++#define REG_MIU_SEL2 (MIU_REG_BASE+0xf4UL) //0x12F2 ++#define REG_MIU_SEL3 (MIU_REG_BASE+0xf6UL) //0x12F3 ++#define REG_MIU_SELX(x) (0xF0UL+x*2) ++ ++// MIU1 ++#define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3UL) ++#define MIU1_PROTECT_DDR_SIZE_MASK BITS_RANGE(15:12) ++ ++#define MIU1_PROTECT0_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT1_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT2_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT3_EN (MIU1_REG_BASE+0xD2UL) ++#define MIU1_PROTECT4_EN (MIU1_ARB_REG_BASE+0xDEUL) ++#define MIU1_PROTECT_ID0 (MIU1_REG_BASE+0x2EUL) ++#define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20UL) ++#define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22UL) ++#define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24UL) ++#define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26UL) ++#define MIU1_PROTECT4_ID_ENABLE (MIU1_ARB_REG_BASE+0xDC) ++#define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT1_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT2_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT3_MSB (MIU1_REG_BASE+0xD0UL) ++#define MIU1_PROTECT4_MSB (MIU1_REG_BASE+0xB2UL) ++#define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0UL) ++#define MIU1_PROTECT0_END (MIU1_REG_BASE+0xC2UL) ++#define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4UL) ++#define MIU1_PROTECT1_END (MIU1_REG_BASE+0xC6UL) ++#define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8UL) ++#define MIU1_PROTECT2_END (MIU1_REG_BASE+0xCAUL) ++#define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCCUL) ++#define MIU1_PROTECT3_END (MIU1_REG_BASE+0xCEUL) ++#define MIU1_PROTECT4_START (MIU1_REG_BASE+0x72UL) ++#define MIU1_PROTECT4_END (MIU1_REG_BASE+0x92UL) ++ ++#define REG_MIU_I64_MODE (BIT7) ++#define REG_MIU_INIT_DONE (BIT15) ++ ++// Protection Status ++#define REG_MIU_PROTECT_LOG_CLR (BIT0) ++#define REG_MIU_PROTECT_IRQ_MASK (BIT1) ++#define REG_MIU_PROTECT_HIT_FALG (BIT4) ++#define REG_MIU_PROTECT_HIT_ID 14:8 ++#define REG_MIU_PROTECT_HIT_NO 7:5 ++ ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET (MIU_REG_BASE+0xD8UL) ++#define REG_MIU_PROTECT_PWR_IRQ_MASK_BIT (BIT11) ++ ++// MMU Control Register ++#define REG_MMU_CTRL (MIU_MMU_REG_BASE+0xA0UL) ++#define REG_MMU_RW_ENTRY (MIU_MMU_REG_BASE+0xA2UL) ++#define REG_MMU_W_DATA (MIU_MMU_REG_BASE+0xA4UL) ++#define REG_MMU_R_DATA (MIU_MMU_REG_BASE+0xA6UL) ++#define REG_MMU_CLIENT_ID_0_1 (MIU_MMU_REG_BASE+0xA8UL) ++#define REG_MMU_CLIENT_ID_2_3 (MIU_MMU_REG_BASE+0xAAUL) ++#define REG_MMU_CLIENT_ID_4_5 (MIU_MMU_REG_BASE+0xACUL) ++#define REG_MMU_CLIENT_ID_6_7 (MIU_MMU_REG_BASE+0xAEUL) ++#define REG_MMU_CLIENT_ID_SEL (MIU_MMU_REG_BASE+0xB0UL) ++#define REG_MMU_IRQ_CTRL (MIU_MMU_REG_BASE+0xB2UL) ++#define REG_MMU_COLLISION_ENTRY (MIU_MMU_REG_BASE+0xB4UL) ++#define REG_MMU_ACCESS (MIU_MMU_REG_BASE+0xB6UL) ++#define REG_MMU_INVALID_ENTRY (MIU_MMU_REG_BASE+0xB8UL) ++#define REG_MMU_INVALID_CLIENT_ID (MIU_MMU_REG_BASE+0xBAUL) ++ ++// MMU Control ++#define REG_MMU_CTRL_ENABLE (BIT0) ++#define REG_MMU_CTRL_PG_SIZE (BIT1) ++#define REG_MMU_CTRL_RESET (BIT4) ++#define REG_MMU_CTRL_RESET_INIT_VAL (BIT5) ++#define REG_MMU_CTRL_INIT_DONE (BIT7) ++#define REG_MMU_CTRL_REGION_MASK 11:8 ++#define REG_MMU_CTRL_RP_REGION_MASK 15:12 ++ ++// Read/Write Entry ++#define REG_MMU_RW_ENTRY_MODE (BIT15) ++ ++// IRQ Control ++#define REG_MMU_IRQ_RW_CLR (BIT0) ++#define REG_MMU_IRQ_RW_MASK (BIT1) ++#define REG_MMU_IRQ_RD_CLR (BIT2) ++#define REG_MMU_IRQ_RD_MASK (BIT3) ++#define REG_MMU_IRQ_WR_CLR (BIT4) ++#define REG_MMU_IRQ_WR_MASK (BIT5) ++#define REG_MMU_IRQ_RW_FLAG (BIT6) ++#define REG_MMU_IRQ_RD_FLAG (BIT7) ++#define REG_MMU_IRQ_WR_FLAG (BIT8) ++#define REG_MMU_IRQ_INVALID_RW (BIT9) ++#define REG_MMU_IRQ_INVALID_ID_MASK 6:0 ++ ++ ++#endif // _REG_MIU_H_ +diff --git a/drivers/sstar/include/infinity6e/reg_clks.h b/drivers/sstar/include/infinity6e/reg_clks.h +new file mode 100755 +index 000000000000..3e048a2f013c +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/reg_clks.h +@@ -0,0 +1,574 @@ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5.1 */ ++/* CLK FILENAME: I6e/iNfinity6e_Clock_Table_0903.xls */ ++/* REG FILENAME: I6e/iNfinity6e_reg_CLKGEN.xls, I6e/iNfinity6e_reg_pm_sleep.xls, I6e/iNfinity6e_reg_block.xls, I6e/iNfinity6e_reg_chiptop.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++#define REG_CHIPTOP_BASE 0x1F203C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CHIPTOP_DUMMY_0_BASE (REG_CHIPTOP_BASE+0x20*4) ++#define REG_CHIPTOP_DUMMY_0_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_1_BASE (REG_CHIPTOP_BASE+0x21*4) ++#define REG_CHIPTOP_DUMMY_1_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_2_BASE (REG_CHIPTOP_BASE+0x22*4) ++#define REG_CHIPTOP_DUMMY_2_OFFSET (0) ++ ++#define REG_CHIPTOP_DUMMY_3_BASE (REG_CHIPTOP_BASE+0x23*4) ++#define REG_CHIPTOP_DUMMY_3_OFFSET (0) ++ ++#define REG_CHIPTOP_RESERVED_BASE (REG_CHIPTOP_BASE+0x7B*4) ++#define REG_CHIPTOP_RESERVED_OFFSET (0) ++ ++#define REG_CKG_BT656_0_FIXME_BASE (REG_SC_GP_CTRL_BASE+0x27*4) ++#define REG_CKG_BT656_0_FIXME_OFFSET (0) ++ ++#define REG_CKG_BT656_1_FIXME_BASE (REG_SC_GP_CTRL_BASE+0x27*4) ++#define REG_CKG_BT656_1_FIXME_OFFSET (8) ++ ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_CKG_ODCLK_FIXME_BASE (REG_SC_GP_CTRL_BASE+0x24*4) ++#define REG_CKG_ODCLK_FIXME_OFFSET (8) ++ ++#define REG_CKG_SD_FIXME2_BASE (REG_SC_GP_CTRL_BASE+0x25*4) ++#define REG_CKG_SD_FIXME2_OFFSET (0) ++ ++#define REG_CKG_SNR0_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR0_OFFSET (0) ++ ++#define REG_CKG_SNR1_BASE (REG_SC_GP_CTRL_BASE+0x28*4) ++#define REG_CKG_SNR1_OFFSET (8) ++ ++#define REG_CKG_SNR2_BASE (REG_SC_GP_CTRL_BASE+0x29*4) ++#define REG_CKG_SNR2_OFFSET (0) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++#define REG_SRAM_SD_EN_BASE (REG_SC_GP_CTRL_BASE+0x10*4) ++#define REG_SRAM_SD_EN_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_LIVE_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x34*4) ++#define REG_CKG_LIVE_PM_OFFSET (0) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (7) ++ ++#define REG_CKG_MCU_PM_P1_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_P1_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PIR_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_PIR_OFFSET (8) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_PM_UART_BASE (REG_PM_SLEEP_CKG_BASE+0x25*4) ++#define REG_CKG_PM_UART_OFFSET (0) ++ ++#define REG_CKG_PWM_FIXME_BASE (REG_PM_SLEEP_CKG_BASE+0x1C*4) ++#define REG_CKG_PWM_FIXME_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_FIXME_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_FIXME_OFFSET (10) ++ ++#define REG_CKG_SPI_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_384M_2BACH_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_384M_2BACH_OFFSET (7) ++ ++#define REG_CKG_432M_2BACH_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_432M_2BACH_OFFSET (6) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_IPU_GP_BASE (REG_CKG_BASE+0x05*4) ++#define REG_CKG_BIST_IPU_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_USB30_GP_BASE (REG_CKG_BASE+0x05*4) ++#define REG_CKG_BIST_USB30_GP_OFFSET (8) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_BT656_0_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_BT656_0_OFFSET (0) ++ ++#define REG_CKG_BT656_1_BASE (REG_CKG_BASE+0x54*4) ++#define REG_CKG_BT656_1_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M00_BASE (REG_CKG_BASE+0x58*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M00_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M01_BASE (REG_CKG_BASE+0x59*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M01_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M1_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_CSI_MAC_LPTX_TOP_I_M1_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_TOP_I_M00_BASE (REG_CKG_BASE+0x58*4) ++#define REG_CKG_CSI_MAC_TOP_I_M00_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_TOP_I_M01_BASE (REG_CKG_BASE+0x5A*4) ++#define REG_CKG_CSI_MAC_TOP_I_M01_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_TOP_I_M1_BASE (REG_CKG_BASE+0x5B*4) ++#define REG_CKG_CSI_MAC_TOP_I_M1_OFFSET (8) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_DIP_BASE (REG_CKG_BASE+0x52*4) ++#define REG_CKG_DIP_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_BACH_384M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_BACH_384M_OFFSET (7) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_IPU_BASE (REG_CKG_BASE+0x50*4) ++#define REG_CKG_IPU_OFFSET (0) ++ ++#define REG_CKG_IPUFF_BASE (REG_CKG_BASE+0x50*4) ++#define REG_CKG_IPUFF_OFFSET (8) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_JPE_GATE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_GATE_OFFSET (7) ++ ++#define REG_CKG_LDCFEYE_BASE (REG_CKG_BASE+0x53*4) ++#define REG_CKG_LDCFEYE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIIC2_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC2_OFFSET (12) ++ ++#define REG_CKG_MIPI1_TX_CSI_BASE (REG_CKG_BASE+0x5C*4) ++#define REG_CKG_MIPI1_TX_CSI_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI_OFFSET (12) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_NS_TOP_I_M00_BASE (REG_CKG_BASE+0x59*4) ++#define REG_CKG_NS_TOP_I_M00_OFFSET (0) ++ ++#define REG_CKG_NS_TOP_I_M01_BASE (REG_CKG_BASE+0x5A*4) ++#define REG_CKG_NS_TOP_I_M01_OFFSET (8) ++ ++#define REG_CKG_NS_TOP_I_M1_BASE (REG_CKG_BASE+0x5C*4) ++#define REG_CKG_NS_TOP_I_M1_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_PWM_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_PWM_OFFSET (8) ++ ++#define REG_CKG_PWR_CTL_BASE (REG_CKG_BASE+0x04*4) ++#define REG_CKG_PWR_CTL_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SD_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_SD_OFFSET (0) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_ARB_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_ARB_OFFSET (0) ++ ++#define REG_CKG_SPI_FLASH_BASE (REG_CKG_BASE+0x38*4) ++#define REG_CKG_SPI_FLASH_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR00_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR00_MCLK_OFFSET (8) ++ ++#define REG_CKG_SR01_MCLK_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_SR01_MCLK_OFFSET (0) ++ ++#define REG_CKG_SR1_MCLK_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_SR1_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_VHE_GATE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_GATE_OFFSET (7) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x35*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity6e/registers.h b/drivers/sstar/include/infinity6e/registers.h +new file mode 100755 +index 000000000000..2177d885add5 +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/registers.h +@@ -0,0 +1,258 @@ ++/* ++* registers.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define REG_ADDR(addr) (*((volatile U16*)(0xFD200000 + (addr << 1)))) ++ ++#define ARM_MIU0_BUS_BASE 0x20000000 ++#define ARM_MIU1_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU0_BASE_ADDR 0x00000000 ++#define ARM_MIU1_BASE_ADDR 0xFFFFFFFF ++ ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFF ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFF ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFF ++ ++#define MIU0_BASE ARM_MIU0_BUS_BASE ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x2E000 // 184K ++ // #define IMI_SIZE (0x20000) // 128K ++ #define IMI_ADDR_PHYS_1 (IMI_PHYS) ++ #define IMI_SIZE_1 (IMI_SIZE>>1) ++ #define IMI_ADDR_PHYS_2 ((IMI_PHYS)+ ((IMI_SIZE)>>1)) ++ #define IMI_SIZE_2 (IMI_SIZE>>1) ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_PADTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103C00) ++#define BASE_REG_PMPOR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0600) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++#define BASE_REG_WDT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3000) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++ ++#define BASE_REG_BDMA0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100200) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100240) ++#define BASE_REG_BDMA2_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100280) ++#define BASE_REG_BDMA3_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1002C0) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_MOVDMA_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100B00) ++#define BASE_REG_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101000) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_OTP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101800) ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_MIUPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103100) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++#define BASE_REG_GPI_INT_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103D00) ++#define BASE_REG_XTAL_ATOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x111B00) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++#define BASE_REG_VENPLL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103600) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I6E_PACKAGE_UNKNOWN =0x00, ++ MS_I6E_PACKAGE_QFN_DDR3, ++ MS_I6E_PACKAGE_BGA_LPDDR2, ++ MS_I6E_PACKAGE_EXTENDED =0x30, ++ MS_I6E_PACKAGE_BGA2_DDR3 =0x30, ++ MS_I6E_PACKAGE_FPGA_128MB =0x90, ++} MS_I6_PACKAGE_TYPE; ++ ++ ++#endif +diff --git a/drivers/sstar/include/infinity6e/tsensor.h b/drivers/sstar/include/infinity6e/tsensor.h +new file mode 100755 +index 000000000000..30e40f7d6d1b +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/tsensor.h +@@ -0,0 +1,23 @@ ++/* ++* tsensor.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: giggs.huang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __CPU_FREQ_H ++#define __CPU_FREQ_H ++ ++int ms_get_temp(void); ++ ++#endif //__CPU_FREQ_H +diff --git a/drivers/sstar/include/infinity6e/voltage_ctrl_demander.h b/drivers/sstar/include/infinity6e/voltage_ctrl_demander.h +new file mode 100755 +index 000000000000..844a4cd4ff4c +--- /dev/null ++++ b/drivers/sstar/include/infinity6e/voltage_ctrl_demander.h +@@ -0,0 +1,37 @@ ++/* ++* voltage_ctrl.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __VOLTAGE_CTRL_DEMANDER_H ++#define __VOLTAGE_CTRL_DEMANDER_H ++ ++#define FOREACH_DEMANDER(DEMANDER) \ ++ DEMANDER(VOLTAGE_DEMANDER_CPUFREQ) \ ++ DEMANDER(VOLTAGE_DEMANDER_TEMPERATURE) \ ++ DEMANDER(VOLTAGE_DEMANDER_VENC) \ ++ DEMANDER(VOLTAGE_DEMANDER_MIU) \ ++ DEMANDER(VOLTAGE_DEMANDER_IPUFREQ) \ ++ DEMANDER(VOLTAGE_DEMANDER_USER) \ ++ DEMANDER(VOLTAGE_DEMANDER_MAX) \ ++ ++#define GENERATE_ENUM(ENUM) ENUM, ++#define GENERATE_STRING(STRING) #STRING, ++ ++typedef enum { ++ FOREACH_DEMANDER(GENERATE_ENUM) ++} VOLTAGE_DEMANDER_E; ++ ++#endif //__VOLTAGE_CTRL_DEMANDER_H +diff --git a/drivers/sstar/include/mdrv_API_version.h b/drivers/sstar/include/mdrv_API_version.h +new file mode 100755 +index 000000000000..805533bc1277 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_API_version.h +@@ -0,0 +1,18 @@ ++/* ++* mdrv_API_version.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#define KL_API_VERSION "1.0.0" +diff --git a/drivers/sstar/include/mdrv_cipher.h b/drivers/sstar/include/mdrv_cipher.h +new file mode 100755 +index 000000000000..43aa111040ab +--- /dev/null ++++ b/drivers/sstar/include/mdrv_cipher.h +@@ -0,0 +1,107 @@ ++/* ++* mdrv_cipher.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _SS_CIPHER_H_ ++#define _SS_CIPHER_H_ ++ ++#define AES_MODE_ECB 0 ++#define AES_MODE_CBC 1 ++#define AES_MODE_CTR 2 ++ ++/* ++ * AES ++ */ ++ ++// algorithm mode ++typedef enum ++{ ++ E_AES_ALGO_ECB = 0, ++ E_AES_ALGO_CBC, ++ E_AES_ALGO_CTR, ++} MDRV_AES_ALGO_MODE; ++ ++typedef enum ++{ ++ E_AES_KEY_SRC_INT_UNI = 1, ++ E_AES_KEY_SRC_INT_CONST, ++} MDRV_AES_KEY_SOURCE; ++ ++// AES handle ++typedef struct ++{ ++ u8 *in; // input ++ u8 *out; // output ++ u32 len; // length of input ++ u8 key[16]; // key ++ u8 iv[16]; // initial vector ++ u32 keylen; // length of key ++ MDRV_AES_ALGO_MODE mode; ++} MDRV_AES_HANDLE; ++ ++/* ++ * RSA ++ */ ++ ++// RSA handle ++typedef struct ++{ ++ u32 exp[64]; // exponent, 256 bit in max for RSA-2048 ++ u32 modulus[64];// public / private modulus, 256 bit in max for RSA-2048 ++ u32 exp_len; // length of exponent ++ u32 mod_len; // lenght of modulus ++ u32 in[64]; // input, 256 bit in max for RSA-2048 ++ u32 out[64]; // output, 256 bit in max for RSA-2048 ++ u8 len; // length of input, must be less than modulus length ++} MDRV_RSA_HANDLE; ++ ++/* ++ * SHA ++ */ ++typedef enum ++{ ++ E_SHA_1 = 0, ++ E_SHA_256 = 1, ++ E_SHA_1_ONCE = 2, ++ E_SHA_256_ONCE = 3, ++ E_SHA_MODE_NUM = 4, ++} MDRV_SHA_MODE; ++ ++typedef struct ++{ ++ u32 u32ShaVal[8]; // SHA256_DIGEST_SIZE, final hash value ++ u32 u32DataPhy; // data physical address ++ u32 u32DataLen; ++ struct { ++ u32 state[8]; // SHA256_DIGEST_SIZE, init hash value ++ u32 count; // bytes processed ++ } ctx; ++ MDRV_SHA_MODE mode; ++} MDRV_SHA_HANDLE; ++ ++// Public ++int cipher_aes_init(void); ++int cipher_aes_uninit(void); ++int cipher_aes_encrypt(MDRV_AES_HANDLE *handle); ++int cipher_aes_decrypt(MDRV_AES_HANDLE *handle); ++int cipher_rsa_crypto(MDRV_RSA_HANDLE *handle); ++int cipher_sha_init(MDRV_SHA_HANDLE *handle); ++int cipher_sha_update(MDRV_SHA_HANDLE *handle); ++int cipher_sha_final(MDRV_SHA_HANDLE *handle); ++u32 cipher_random_num(void); ++ ++#endif //_SS_CIPHER_H_ +\ No newline at end of file +diff --git a/drivers/sstar/include/mdrv_device_id.h b/drivers/sstar/include/mdrv_device_id.h +new file mode 100755 +index 000000000000..470aed154210 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_device_id.h +@@ -0,0 +1,74 @@ ++/* ++* mdrv_device_id.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_DEVICE_ID_H__ ++#define __MDRV_DEVICE_ID_H__ ++ ++typedef enum ++{ ++CHIP_REVISION_U01=0x00, ++CHIP_REVISION_U02, ++CHIP_REVISION_U03, ++CHIP_REVISION_U04, ++CHIP_REVISION_U05, ++CHIP_REVISION_U06, ++CHIP_REVISION_U07, ++CHIP_REVISION_U08, ++CHIP_REVISION_U09, ++CHIP_REVISION_U0A, ++CHIP_REVISION_U0B, ++CHIP_REVISION_U0C, ++CHIP_REVISION_U0D, ++CHIP_REVISION_U0E, ++CHIP_REVISION_U0F, ++CHIP_REVISION_U10, ++CHIP_REVISION_U11, ++CHIP_REVISION_U12, ++CHIP_REVISION_U13, ++CHIP_REVISION_U14, ++CHIP_REVISION_U15, ++CHIP_REVISION_U16, ++CHIP_REVISION_U17, ++CHIP_REVISION_U18, ++CHIP_REVISION_U19, ++CHIP_REVISION_U1A, ++CHIP_REVISION_U1B, ++CHIP_REVISION_U1C, ++CHIP_REVISION_U1D, ++CHIP_REVISION_U1E, ++CHIP_REVISION_U1F, ++CHIP_REVISION_END=0xFF ++ ++}MS_CHIP_REVISION; ++ ++ ++ ++typedef enum ++{ ++DEVICE_ID_CEDRIC = (0x50), ++DEVICE_ID_CHICAGO = (0x70), ++DEVICE_ID_INFINITY = (0xAE), ++DEVICE_ID_INFINITY5 = (0xED), ++DEVICE_ID_END=0xFFFFFFFF ++}MS_DEVICE_ID; ++ ++ ++#define KERNEL_310_VER "3.10" ++#define KERNEL_318_VER "3.18" ++ ++ ++#endif +diff --git a/drivers/sstar/include/mdrv_fb_io.h b/drivers/sstar/include/mdrv_fb_io.h +new file mode 100755 +index 000000000000..4902d77a22ee +--- /dev/null ++++ b/drivers/sstar/include/mdrv_fb_io.h +@@ -0,0 +1,160 @@ ++/* ++* mdrv_fb_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/** ++ * \defgroup fb_group FrameBuffer driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/soc0/soc/soc:gop/gopinfo ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: print fb/gop current status and settings ++ * ++ * @{ ++ */ ++ ++ ++#ifndef _MDRV_FB_IO_H ++#define _MDRV_FB_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++ ++// Use 'F' as magic number. In Documentation/ioctl-number.txt says 'F' for all linux/fb.h ++ ++#define G3D_IOC_MAGIC_INFINITY 'F' ///< The Type definition of IOCTL for fb driver ++ ++// number before 20 was set at fb.h, skip them ++ ++/** ++* Used to get framebuffer physical address, return type is unsigned long long. ++*/ ++#define IOCTL_FB_GETFBPHYADDRESS _IO(G3D_IOC_MAGIC_INFINITY,21) ++ ++/** ++* Used to get framebuffer memory size, return type is unsigned long. ++*/ ++#define IOCTL_FB_GETVIDEOMEMSIZE _IO(G3D_IOC_MAGIC_INFINITY,22) ++ ++/** ++* Used to get framebuffer support information, return type is FB_GOP_SUPINF_CONFIG. ++*/ ++#define IOCTL_FB_GETFBSUPPORTINF _IO(G3D_IOC_MAGIC_INFINITY,23) ++ ++/** ++* Used to get gwin's parameters including starting point and ending point, return type is FB_GOP_GWIN_CONFIG. ++*/ ++#define IOCTL_FB_GETGWININFO _IO(G3D_IOC_MAGIC_INFINITY,24) ++ ++/** ++* Used to set gwin's parameters including starting point and ending point, using type is FB_GOP_GWIN_CONFIG. ++*/ ++#define IOCTL_FB_SETGWININFO _IO(G3D_IOC_MAGIC_INFINITY,25) ++ ++/** ++* Used to get gop's conditon, enable or disable, return type is unsigned char. ++*/ ++#define IOCTL_FB_GETENABLEGOP _IO(G3D_IOC_MAGIC_INFINITY,26) ++ ++/** ++* Used to set gop's conditon, enable or disable, using type is unsigned char. ++*/ ++#define IOCTL_FB_SETENABLEGOP _IO(G3D_IOC_MAGIC_INFINITY,27) ++ ++/** ++* Used to get alpha blending conditon including disable or constant_alpha or pixel_alpha, return type is FB_GOP_ALPHA_CONFIG. ++*/ ++#define IOCTL_FB_GETALPHA _IO(G3D_IOC_MAGIC_INFINITY,28) ++ ++/** ++* Used to set alpha blending conditon including disable or constant_alpha or pixel_alpha, using type is FB_GOP_ALPHA_CONFIG. ++*/ ++#define IOCTL_FB_SETALPHA _IO(G3D_IOC_MAGIC_INFINITY,29) ++ ++/** ++* Used to get colorkey information, return type is FB_GOP_COLORKEY_CONFIG. ++*/ ++#define IOCTL_FB_GETCOLORKEY _IO(G3D_IOC_MAGIC_INFINITY,30) ++ ++/** ++* Used to set colorkey information, using type is FB_GOP_COLORKEY_CONFIG. ++*/ ++#define IOCTL_FB_SETCOLORKEY _IO(G3D_IOC_MAGIC_INFINITY,31) ++ ++/** ++* Used to use system imageblit, using type is fb_image, which is defined in "linux/fb.h". ++*/ ++#define IOCTL_FB_IMAGEBLIT _IO(G3D_IOC_MAGIC_INFINITY,32) ++ ++/** ++* Used to set palette, using type is FB_GOP_PaletteEntry. ++*/ ++#define IOCTL_FB_SETPALETTE _IO(G3D_IOC_MAGIC_INFINITY,33) ++ ++/** ++* Used to get settings, include memory width & height, display width & height, buffer number and stretch ratio. ++*/ ++#define IOCTL_FB_GETGENERALCONFIG _IO(G3D_IOC_MAGIC_INFINITY,34) ++ ++/** ++* Used to set settings, include memory width & height, display width & height, buffer number and stretch ratio. ++*/ ++#define IOCTL_FB_SETGENERALCONFIG _IO(G3D_IOC_MAGIC_INFINITY,35) ++ ++/** ++* Used to set gop's inverse color, enable or disable, using type is unsigned char. ++*/ ++#define IOCTL_FB_SETENABLEINVCOLOR _IO(G3D_IOC_MAGIC_INFINITY,36) ++ ++/** ++* Used to set AE configurations, using type is FB_GOP_INVCOLOR_AE_CONFIG. ++*/ ++#define IOCTL_FB_SETAECONFIG _IO(G3D_IOC_MAGIC_INFINITY,37) ++ ++/** ++* Used to set Y threshlod to do inverse color, using type is unsigned long. ++*/ ++#define IOCTL_FB_SETYTHRES _IO(G3D_IOC_MAGIC_INFINITY,38) ++ ++/** ++* Used to set Scaler configurations, using type is FB_GOP_INVCOLOR_SCALER_CONFIG. ++*/ ++#define IOCTL_FB_SETSCALERCONFIG _IO(G3D_IOC_MAGIC_INFINITY,39) ++ ++/** ++* Used to trigger driver to update AE information from ISP driver and return value to user, using type is FB_GOP_INVCOLOR_AE_CONFIG. ++*/ ++#define IOCTL_FB_AUTOUPDATEAE _IO(G3D_IOC_MAGIC_INFINITY,40) ++ ++/** ++* Used to set sw inverse table, using type is FB_GOP_SW_INV_TABLE. ++*/ ++#define IOCTL_FB_SWINVTABLE _IO(G3D_IOC_MAGIC_INFINITY,41) ++ ++ ++#endif //MDRV_FB_IO_H ++ ++ ++/** @} */ // end of fb_group +diff --git a/drivers/sstar/include/mdrv_fb_st.h b/drivers/sstar/include/mdrv_fb_st.h +new file mode 100755 +index 000000000000..04595c867068 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_fb_st.h +@@ -0,0 +1,220 @@ ++/* ++* mdrv_fb_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup fb_group ++ * @{ ++ */ ++#ifndef _MDRV_FB_ST_H ++#define _MDRV_FB_ST_H ++ ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to show current support color format of gop in FB_GOP_SUPINF_CONFIG ++*/ ++typedef enum ++{ ++ COLORFMT_ARGB8888 = 0, ++ COLORFMT_RGB565 = 1, ++ COLORFMT_YUV422 = 2, ++ COLORFMT_I8PALETTE= 3, ++ COLORFMT_MAX = 4, ++}FB_GOP_COLORFORMAT_TYPE; ++ ++/** ++* Used to setup the mode of alpha blending for gop in FB_GOP_ALPHA_CONFIG ++*/ ++typedef enum ++{ ++ PIXEL_ALPHA = 0, ++ CONST_ALPHA = 1, ++}FB_GOP_ALPHA_TYPE; ++ ++/** ++* Used to setup the buffer number for gop in FB_GOP_RESOLUTION_STRETCH_H_CONFIG ++*/ ++typedef enum ++{ ++ FB_SINGLE_BUFFER = 1, ++ FB_DOUBLE_BUFFER = 2, ++}FB_GOP_BUFFER_NUM; ++ ++/** ++* Used to setup the stretch H ratio for gop in FB_GOP_RESOLUTION_STRETCH_H_CONFIG ++*/ ++typedef enum ++{ ++ FB_STRETCH_H_RATIO_1 = 1, ++ FB_STRETCH_H_RATIO_2 = 2, ++ FB_STRETCH_H_RATIO_4 = 4, ++ FB_STRETCH_H_RATIO_8 = 8, ++}FB_GOP_STRETCH_H_RATIO; ++ ++/** ++* Used to setup the stretch H ratio for gop in FB_GOP_RESOLUTION_STRETCH_H_CONFIG ++*/ ++typedef enum ++{ ++ FB_INV_COLOR_ROTATE_CLOCKWISE_0 = 0, ++ FB_INV_COLOR_ROTATE_CLOCKWISE_90 = 1, ++ FB_INV_COLOR_ROTATE_CLOCKWISE_180 = 2, ++ FB_INV_COLOR_ROTATE_CLOCKWISE_270 = 3, ++}FB_GOP_INV_COLOR_ROTATE; ++ ++//============================================================================= ++// struct ++//============================================================================= ++ ++ ++ ++//============================================================================= ++// struct for IOCTL_FB_GETFBSUPPORTINF ++/** ++* Used to get framebuffer support information ++*/ ++typedef struct ++{ ++ ++ unsigned char bKeyAlpha; ///< whether support colorkey ++ unsigned char bConstAlpha; ///< whether support constant alpha ++ unsigned char bPixelAlpha; ///< whether support pixel alpha ++ unsigned char bColFmt[COLORFMT_MAX]; ///< support which color format ++ unsigned long u32MaxWidth; ///< the max pixels per line ++ unsigned long u32MaxHeight; ///< the max lines ++}FB_GOP_SUPINF_CONFIG; ++ ++// struct for FB_GOP_GWIN_CONFIG ++/** ++* Used to set or get gwin parameters ++*/ ++typedef struct ++{ ++ unsigned short u18HStart; ///< gwin horizontal starting coordinate ++ unsigned short u18HEnd; ///< gwin horizontal ending coordinate ++ unsigned short u18VStart; ///< gwin vertical starting coordinate ++ unsigned short u18VEnd; ///< gwin vertical ending coordinate ++}FB_GOP_GWIN_CONFIG; ++ ++// struct for FB_GOP_ALPHA_CONFIG ++/** ++* Used to set or get gop alpha blending settings ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< alpha blending enable or disable ++ FB_GOP_ALPHA_TYPE enAlphaType; ///< set alpha type: pixel alpha or constant alpha ++ unsigned char u8Alpha; ///< constant alpha value, availble for setting constant alpha ++}FB_GOP_ALPHA_CONFIG; ++ ++// struct for FB_GOP_COLORKEY_CONFIG ++/** ++* Used to set or get gop colorkey settings ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< colorkey enable or disable ++ unsigned char u8R; ///< parameter for red color in colorkey ++ unsigned char u8G; ///< parameter for green color in colorkey ++ unsigned char u8B; ///< parameter for blue color in colorkey ++}FB_GOP_COLORKEY_CONFIG; ++ ++// struct for FB_GOP_PaletteEntry ++/** ++* Used to set palette parameters ++*/ ++typedef union ++{ ++ /// RGBA8888 ++ struct ++ { ++ unsigned char u8B; ///< parameter for blue color in palette ++ unsigned char u8G; ///< parameter for green color in palette ++ unsigned char u8R; ///< parameter for red color in palette ++ unsigned char u8A; ///< parameter for alpha in palette ++ } BGRA; ++} FB_GOP_PaletteEntry; ++ ++// struct for FB_GOP_RESOLUTION_STRETCH_H_CONFIG ++/** ++* Used to set or get gop colorkey settings ++*/ ++typedef struct ++{ ++ unsigned long u32Width; ///< the width for gop resolution ++ unsigned long u32Height; ///< the height for gop resolution ++ unsigned long u32DisplayWidth; ///< the width for display resolution, =u32Width*enStretchH_Ratio ++ unsigned long u32DisplayHeight; ///< the height for display resolution,=u32Height ++ FB_GOP_BUFFER_NUM enBufferNum; ///< buffer number ++ FB_GOP_STRETCH_H_RATIO enStretchH_Ratio; ///< stretch H ratio ++}FB_GOP_RESOLUTION_STRETCH_H_CONFIG; ++ ++// struct for FB_GOP_INVCOLOR_AE_CONFIG ++/** ++* Used to set AE configurations into the engine of gop inverse color ++*/ ++typedef struct ++{ ++ unsigned long u32AEBlkWidth; ///< the width for AE block ++ unsigned long u32AEBlkHeight; ///< the height for AE block ++ unsigned long u32AEDisplayWidth; ///< the width for AE display resolutionfor ++ unsigned long u32AEDisplayHeight; ///< the height for AE display resolutionfor ++}FB_GOP_INVCOLOR_AE_CONFIG; ++ ++// struct for FB_GOP_INVCOLOR_SCALER_CONFIG ++/** ++* Used to set Scaler configurations into the engine of gop inverse color ++*/ ++typedef struct ++{ ++ unsigned char bCropEn; ///< scaler do crop or not ++ unsigned char bScalingEn; ///< scaler do scaling or not ++ unsigned char bRotateEn; ///< scaler do rotate or not ++ ++ unsigned long u32ScalerWidth; ///< the width for Scaler resolution ++ unsigned long u32ScalerHeight; ///< the height for Scaler resolution ++ ++ unsigned long u32CropXstart; ///< the start x coordinate for Scaler crop to calculate the crop width, available for bCropEn=1 ++ unsigned long u32CropXend; ///< the end x coordinate for Scaler crop to calculate the crop width, available for bCropEn=1 ++ unsigned long u32CropYstart; ///< the start y coordinate for Scaler crop to calculate the crop height, available for bCropEn=1 ++ unsigned long u32CropYend; ///< the end y coordinate for Scaler crop to calculate the crop height, available for bCropEn=1 ++ ++ FB_GOP_INV_COLOR_ROTATE enRotateA; ///< the rotate angle for Scaler rotate, available for bRotateEn=1 ++}FB_GOP_INVCOLOR_SCALER_CONFIG; ++ ++// struct for FB_GOP_SW_INV_TABLE ++/** ++* Used to set sw inverse table ++*/ ++typedef struct ++{ ++ unsigned char *invTable; ///< sw inverse table ++ int size; /// ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_GPIO_H_ ++#define _MDRV_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++void MDrv_GPIO_Init(void); ++void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); // set a pad to GPIO mode ++int MDrv_GPIO_PadGroupMode_Set(U32 u32PadMode); // set the specified pad mode(a set of GPIO pads will be effected) ++ // return: 0->success; -1: fail or not supported ++int MDrv_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); // set a pad to the specified mode ++ // return: 0->success; -1: fail or not supported ++void MDrv_GPIO_Pad_Oen(U8 u8IndexGPIO); ++void MDrv_GPIO_Pad_Odn(U8 u8IndexGPIO); ++U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO); ++U8 MDrv_GPIO_Pad_InOut(U8 u8IndexGPIO); ++void MDrv_GPIO_Pull_High(U8 u8IndexGPIO); ++void MDrv_GPIO_Pull_Low(U8 u8IndexGPIO); ++void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++void MDrv_Enable_GPIO_INT(U8 u8IndexGPIO); ++int MDrv_GPIO_To_Irq(U8 u8IndexGPIO); ++void MDrv_GPIO_PAD_32K_OUT(U8 u8Enable); ++void MDrv_GPIO_Set_POLARITY(U8 u8IndexGPIO, U8 reverse); ++ ++#endif // _MDRV_GPIO_H_ ++ +diff --git a/drivers/sstar/include/mdrv_gpio_io.h b/drivers/sstar/include/mdrv_gpio_io.h +new file mode 100755 +index 000000000000..c90d82979b9b +--- /dev/null ++++ b/drivers/sstar/include/mdrv_gpio_io.h +@@ -0,0 +1,75 @@ ++/* ++* mdrv_gpio_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "mdrv_types.h" ++#include ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++struct GPIO_Reg ++{ ++ U32 u32Reg; ++ U8 u8Enable; ++ U8 u8BitMsk; ++} __attribute__ ((packed)); ++ ++typedef struct GPIO_Reg GPIO_Reg_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define IOCTL_GPIO_INIT_NR (0) ++#define IOCTL_GPIO_SET_NR (1) ++#define IOCTL_GPIO_OEN_NR (2) ++#define IOCTL_GPIO_ODN_NR (3) ++#define IOCTL_GPIO_READ_NR (4) ++#define IOCTL_GPIO_PULL_HIGH_NR (5) ++#define IOCTL_GPIO_PULL_LOW_NR (6) ++#define IOCTL_GPIO_INOUT_NR (7) ++#define IOCTL_GPIO_WREGB_NR (8) ++ ++#define GPIO_IOC_MAGIC 'g' ++#define IOCTL_GPIO_INIT _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_INIT_NR) ++#define IOCTL_GPIO_SET _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_SET_NR) ++#define IOCTL_GPIO_OEN _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_OEN_NR) ++#define IOCTL_GPIO_ODN _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_ODN_NR) ++#define IOCTL_GPIO_READ _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_READ_NR) ++#define IOCTL_GPIO_PULL_HIGH _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_PULL_HIGH_NR) ++#define IOCTL_GPIO_PULL_LOW _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_PULL_LOW_NR) ++#define IOCTL_GPIO_INOUT _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_INOUT_NR) ++#define IOCTL_GPIO_WREGB _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_WREGB_NR) ++ ++#define GPIO_IOC_MAXNR 9 ++ ++//for rename use ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++void camdriver_gpio_set(struct gpio_chip *chip, unsigned offset, int value); ++int camdriver_gpio_get(struct gpio_chip *chip, unsigned offset); ++int camdriver_gpio_direction_input(struct gpio_chip *chip, unsigned offset); ++int camdriver_gpio_request(struct gpio_chip *chip, unsigned offset); ++int camdriver_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ++ int value); ++int camdriver_gpio_to_irq(struct gpio_chip *chip, unsigned offset); ++ ++void __mod_gpio_init(void); +diff --git a/drivers/sstar/include/mdrv_hvsp_io.h b/drivers/sstar/include/mdrv_hvsp_io.h +new file mode 100755 +index 000000000000..cfb8c6acc075 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_hvsp_io.h +@@ -0,0 +1,123 @@ ++/* ++* mdrv_hvsp_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/** ++ * \defgroup hvsp_group HVSP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/clk ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W:control clk by explain. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckcrop ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print vsync count,err times W: if 0 close ptgen ,if echo 1 open check crop ,echo 2 open check hvsp and dma count ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ptgen ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W: if 0 close ptgen ,if echo 1 open static ptgen ,echo 2 open dynamic ptgen,echo 3 open scl time gen ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_H ++#define _MDRV_HVSP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++ ++#define IOCTL_HVSP_SET_IN_CONFIG_NR (0) ///< The IOCTL NR definition,IOCTL_HVSP_SET_IN_CONFIG ++#define IOCTL_HVSP_SET_OUT_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OUT_CONFIG ++#define IOCTL_HVSP_SET_SCALING_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_HVSP_SET_SCALING_CONFIG ++#define IOCTL_HVSP_REQ_MEM_CONFIG_NR (3) ///< The IOCTL NR definition,IOCTL_HVSP_REQ_MEM_CONFIG ++#define IOCTL_HVSP_SET_MISC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_HVSP_SET_MISC_CONFIG ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG_NR (5) ///< The IOCTL NR definition,IOCTL_HVSP_SET_POST_CROP_CONFIG ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ++#define IOCTL_HVSP_GET_INFORM_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_HVSP_GET_INFORM_CONFIG ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_HVSP_RELEASE_MEM_CONFIG ++#define IOCTL_HVSP_SET_OSD_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OSD_CONFIG ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_HVSP_SET_FB_MANAGE_CONFIG ++#define IOCLT_HVSP_GET_VERSION_CONFIG_NR (11) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_MAX_NR (12) ///< The Max IOCTL NR for hvsp driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_HVSP_MAGIC ('1')///< The Type definition of IOCTL for hvsp driver ++/** ++* Used to set Input MUX,capture window, use ST_IOCTL_HVSP_INPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_IN_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_IN_CONFIG_NR) ++/** ++* Used to set output configuration, use ST_IOCTL_HVSP_OUTPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OUT_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OUT_CONFIG_NR) ++/** ++* Used to set HVSP configuration and set post crop ,line,frame buffer size, use ST_IOCTL_HVSP_SCALING_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_SCALING_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_SCALING_CONFIG_NR) ++/** ++* Used to allocate DNR buffer and set framebuffer configuration, use ST_IOCTL_HVSP_REQ_MEM_CONFIG. ++*/ ++#define IOCTL_HVSP_REQ_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_REQ_MEM_CONFIG_NR) ++/** ++* Used to set register without interface, use ST_IOCTL_HVSP_MISC_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_MISC_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_MISC_CONFIG_NR) ++/** ++* Used to set post crop if need, use ST_IOCTL_HVSP_POSTCROP_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_POST_CROP_CONFIG_NR) ++/** ++* Used to get mutiinst private id, use ST_IOCTL_HVSP_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR) ++/** ++* Used to get display size and crop information, use ST_IOCTL_HVSP_SCINFORM_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_INFORM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_INFORM_CONFIG_NR) ++/** ++* Used to releace DNR buffer, use void. ++*/ ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_RELEASE_MEM_CONFIG_NR) ++/** ++* Used to Set OSD Configuration, use ST_IOCTL_HVSP_OSD_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OSD_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OSD_CONFIG_NR) ++/** ++* Used to Set FB Configuration,debug, use ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_HVSP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_VERSION_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCLT_HVSP_GET_VERSION_CONFIG_NR) ++ ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/sstar/include/mdrv_hvsp_io_i3.h b/drivers/sstar/include/mdrv_hvsp_io_i3.h +new file mode 100755 +index 000000000000..dbd8312068ac +--- /dev/null ++++ b/drivers/sstar/include/mdrv_hvsp_io_i3.h +@@ -0,0 +1,143 @@ ++/* ++* mdrv_hvsp_io_i3.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/** ++ * \defgroup hvsp_group HVSP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/clk ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W:control clk by explain. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckcrop ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print vsync count,err times W: if 0 close ptgen ,if echo 1 open check crop ,echo 2 open check hvsp and dma count ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ptgen ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W: if 0 close ptgen ,if echo 1 open static ptgen ,echo 2 open dynamic ptgen,echo 3 open scl time gen ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_H ++#define _MDRV_HVSP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++ ++#define IOCTL_HVSP_SET_IN_CONFIG_NR (0) ///< The IOCTL NR definition,IOCTL_HVSP_SET_IN_CONFIG ++#define IOCTL_HVSP_SET_OUT_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OUT_CONFIG ++#define IOCTL_HVSP_SET_SCALING_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_HVSP_SET_SCALING_CONFIG ++#define IOCTL_HVSP_REQ_MEM_CONFIG_NR (3) ///< The IOCTL NR definition,IOCTL_HVSP_REQ_MEM_CONFIG ++#define IOCTL_HVSP_SET_MISC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_HVSP_SET_MISC_CONFIG ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG_NR (5) ///< The IOCTL NR definition,IOCTL_HVSP_SET_POST_CROP_CONFIG ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ++#define IOCTL_HVSP_GET_INFORM_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_HVSP_GET_INFORM_CONFIG ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_HVSP_RELEASE_MEM_CONFIG ++#define IOCTL_HVSP_SET_OSD_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OSD_CONFIG ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_HVSP_SET_FB_MANAGE_CONFIG ++#define IOCTL_HVSP_SET_PRIMASK_CONFIG_NR (11) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG_NR (12) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_SET_VTRACK_CONFIG_NR (13) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_CONFIG ++#define IOCTL_HVSP_SET_VTRACK_ONOFF_CONFIG_NR (14) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ++#define IOCLT_HVSP_GET_VERSION_CONFIG_NR (15) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_MAX_NR (IOCLT_HVSP_GET_VERSION_CONFIG_NR+1) ///< The Max IOCTL NR for hvsp driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_HVSP_MAGIC ('1')///< The Type definition of IOCTL for hvsp driver ++/** ++* Used to set Input MUX,capture window, use ST_IOCTL_HVSP_INPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_IN_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_IN_CONFIG_NR) ++/** ++* Used to set output configuration, use ST_IOCTL_HVSP_OUTPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OUT_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OUT_CONFIG_NR) ++/** ++* Used to set HVSP configuration and set post crop ,line,frame buffer size, use ST_IOCTL_HVSP_SCALING_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_SCALING_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_SCALING_CONFIG_NR) ++/** ++* Used to allocate DNR buffer and set framebuffer configuration, use ST_IOCTL_HVSP_REQ_MEM_CONFIG. ++*/ ++#define IOCTL_HVSP_REQ_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_REQ_MEM_CONFIG_NR) ++/** ++* Used to set register without interface, use ST_IOCTL_HVSP_MISC_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_MISC_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_MISC_CONFIG_NR) ++/** ++* Used to set post crop if need, use ST_IOCTL_HVSP_POSTCROP_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_POST_CROP_CONFIG_NR) ++/** ++* Used to get mutiinst private id, use ST_IOCTL_HVSP_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR) ++/** ++* Used to get display size and crop information, use ST_IOCTL_HVSP_SCINFORM_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_INFORM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_INFORM_CONFIG_NR) ++/** ++* Used to releace DNR buffer, use void. ++*/ ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_RELEASE_MEM_CONFIG_NR) ++/** ++* Used to Set OSD Configuration, use ST_IOCTL_HVSP_OSD_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OSD_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OSD_CONFIG_NR) ++/** ++* Used to Set FB Configuration,debug, use ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_HVSP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_VERSION_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCLT_HVSP_GET_VERSION_CONFIG_NR) ++/** ++* Used to Set MASK Configuration, use ST_IOCTL_HVSP_PRIMASK_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_PRIMASK_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_PRIMASK_CONFIG_NR) ++/** ++* Used to Set MASK Trigger, use ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG. ++*/ ++#define IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG_NR) ++/** ++* Used to set VTRACK, use ST_IOCTL_VIP_VTRACK_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_VTRACK_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_VTRACK_CONFIG_NR) ++/** ++* Used to set VTACK ON, use ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_VTRACK_ONOFF_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_VTRACK_ONOFF_CONFIG_NR) ++ ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/sstar/include/mdrv_hvsp_io_i3_st.h b/drivers/sstar/include/mdrv_hvsp_io_i3_st.h +new file mode 100755 +index 000000000000..31146b2e1275 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_hvsp_io_i3_st.h +@@ -0,0 +1,366 @@ ++/* ++* mdrv_hvsp_io_i3_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup hvsp_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_ST_H ++#define _MDRV_HVSP_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++#define IOCTL_HVSP_VERSION 0x0100 ++#define HVSP_VTRACK_KEY_SETTING_LENGTH 8 ///< HVSP_VTRACK_KEY_SETTING_LENGTH ++#define HVSP_VTRACK_SETTING_LENGTH 23 ///< HVSP_VTRACK_SETTING_LENGTH ++ ++ ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to setup the input source of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_SRC_ISP, ///< input source: ISP ++ E_IOCTL_HVSP_SRC_BT656, ///< input source: BT656 ++ E_IOCTL_HVSP_SRC_DRAM, ///< input source: DRAM ++ E_IOCTL_HVSP_SRC_HVSP, ///< input source: HVSP1 ++ E_IOCTL_HVSP_SRC_PAT_TGEN, ///< input source: PATGEN ++ E_IOCTL_HVSP_SRC_NUM, ///< The max number of input source ++}EN_IOCTL_HVSP_SRC_TYPE; ++ ++/** ++* Used to setup the color format of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_COLOR_RGB, ///< color format:RGB ++ E_IOCTL_HVSP_COLOR_YUV444, ///< color format:YUV444 ++ E_IOCTL_HVSP_COLOR_YUV422, ///< color format:YUV422 ++ E_IOCTL_HVSP_COLOR_YUV420, ///< color format:YUV420 ++ E_IOCTL_HVSP_COLOR_NUM, ///< The max number of color format ++}EN_IOCTL_HVSP_COLOR_TYPE; ++ ++/** ++* Used to setup the IPR/W status of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_MCNR_YCM_R = 0x1, ///< IP only read ++ E_IOCTL_HVSP_MCNR_YCM_W = 0x2, ///< IP only write ++ E_IOCTL_HVSP_MCNR_YCM_RW = 0x3, ///< IP R/W ++ E_IOCTL_HVSP_MCNR_CIIR_R = 0x4, ///< IP only read ++ E_IOCTL_HVSP_MCNR_CIIR_W = 0x8, ///< IP only write ++ E_IOCTL_HVSP_MCNR_CIIR_RW = 0xC, ///< IP R/W ++ E_IOCTL_HVSP_MCNR_NON = 0x10, ///< IP none open ++}EN_IOCTL_HVSP_MCNR_TYPE; ++ ++/** ++* Used to setup the OSD locate of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ E_IOCTL_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_IOCTL_HVSP_OSD_LOC_TYPE; ++ ++/** ++* Used to setup the FB locate of hvsp device ++*/ ++typedef enum ++{ ++ EN_IOCTL_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_IOCTL_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_IOCTL_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++ EN_IOCTL_HVSP_FBMG_SET_PRVCROP_ON = 0x1000, ++ EN_IOCTL_HVSP_FBMG_SET_PRVCROP_OFF = 0x2000, ++ EN_IOCTL_HVSP_FBMG_SET_CIIR_ON = 0x4000, ++ EN_IOCTL_HVSP_FBMG_SET_CIIR_OFF = 0x8000, ++}EN_IOCTL_HVSP_FBMG_SET_TYPE; ++/** ++* Used to setup the vtrack status of vip device ++*/ ++typedef enum ++{ ++ EN_HVSP_IOCTL_VTRACK_ENABLE_ON, ///< Vtrack on ++ EN_HVSP_IOCTL_VTRACK_ENABLE_OFF, ///< Vtrack off ++ EN_HVSP_IOCTL_VTRACK_ENABLE_DEBUG, ///< Vtrack debug ++}EN_HVSP_IOCTL_VTRACK_ENABLE_TYPE; ++//============================================================================= ++// struct ++//============================================================================= ++/** ++* Used to get HVSP drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_VERSION_CONFIG; ++ ++/** ++* Used to setup the crop size of hvsp device ++*/ ++typedef struct ++{ ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop width size ++ unsigned short u16Height; ///< crop height size ++}__attribute__ ((__packed__))ST_IOCTL_HVSP_WINDOW_CONFIG; ++ ++/** ++* Used to setup the HVSP timing gen of hvsp device ++*/ ++typedef struct ++{ ++ unsigned char bInterlace; ///< is interlace or progressive ++ unsigned short u16Htotal; ///< Htt ++ unsigned short u16Vtotal; ///< Vtt ++ unsigned short u16Vfrequency; ///< Vfreq ++}ST_IOCTL_HVSPTIMING_CONFIG; ++ ++//============================================================================= ++// struct for IOCTL_HVSP_SET_IN_CONFIG ++/** ++* Used to setup the input mux ,input capture window of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ EN_IOCTL_HVSP_SRC_TYPE enSrcType; ///< Input source type ++ EN_IOCTL_HVSP_COLOR_TYPE enColor; ///< color type ++ ST_IOCTL_HVSP_WINDOW_CONFIG stCaptureWin; ///< Input Source Size(input src is scl capture win ++ ST_IOCTL_HVSPTIMING_CONFIG stTimingCfg; ///< Input Timing ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_INPUT_CONFIG; ++ ++ ++// struct for IOCTL_HVSP_SET_OUT_CONFIG ++/** ++* Used to setup the output config of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ EN_IOCTL_HVSP_COLOR_TYPE enColor; ///< color type ++ ST_IOCTL_HVSP_WINDOW_CONFIG stDisplayWin; ///< display window size ++ ST_IOCTL_HVSPTIMING_CONFIG stTimingCfg; ///< output timing ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_OUTPUT_CONFIG; ++/** ++* Used to set CLK mux of hvsp device ++*/ ++typedef struct ++{ ++ struct clk* idclk; ///< idclk ++ struct clk* fclk1; ///< fclk (SC1 SC2 ++ struct clk* fclk2; ///< fclk (SC3 ++ struct clk* odclk; ///< odclk (display Lpll ++}ST_IOCTL_HVSP_CLK_CONFIG; ++// sturct for IOCTL_HVSP_SET_SCALING_CONFIG ++/** ++* Used to setup the crop and HVSP123 scaling configuration of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Src_Width; ///< post crop IN width ++ unsigned short u16Src_Height; ///< post crop IN height ++ unsigned short u16Dsp_Width; ///< after HVSP width ++ unsigned short u16Dsp_Height; ///< after HVSP height ++ unsigned char bCropEn; ///< Is post crop En ++ ST_IOCTL_HVSP_WINDOW_CONFIG stCropWin; ///< post crop size ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_SCALING_CONFIG; ++ ++//IOCTL_HVSP_REQ_MEM_CONFIG ++/** ++* Used to allocate the buffer and setup framebuffer configuration of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Vsize; ///< framebuffer height ++ unsigned short u16Pitch; ///< framebuffer width ++ unsigned long u32MemSize; ///< height*width *2(YUV422) *2(2frame) ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_REQ_MEM_CONFIG; ++ ++//IOCTL_HVSP_SET_MISC_CONFIG ++/** ++* Used to setup the register of hvsp device ++*/ ++typedef struct ++{ ++ unsigned char u8Cmd; ///< register value ++ unsigned long u32Size; ///< number ++ unsigned long u32Addr; ///< bank&addr ++}__attribute__ ((__packed__))ST_IOCTL_HVSP_MISC_CONFIG; ++ ++//IOCTL HVSP_SET_POST_CROP_CONFIG ++/** ++* Used to setup the post crop of hvsp device if need ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned char bCropEn; ///< post crop En ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop frame width ++ unsigned short u16Height; ///< crop frame height ++ unsigned char bFmCntEn; ///< Is use CMDQ to set ++ unsigned char u8FmCnt; ///< when frame count ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_POSTCROP_CONFIG; ++ ++//IOCTL HVSP_SET_POST_CROP_CONFIG ++/** ++* Used to get resolution information of hvsp device ++*/ ++typedef struct ++{ ++ unsigned short u16X; ///< x vs input src ++ unsigned short u16Y; ///< y vs input src ++ unsigned short u16Width; ///< display width ++ unsigned short u16Height; ///< display height ++ unsigned short u16crop2inWidth; ///< framebuffer width ++ unsigned short u16crop2inHeight;///< framebuffer height ++ unsigned short u16crop2OutWidth; ///< after crop width ++ unsigned short u16crop2OutHeight;///< after crop height ++}ST_IOCTL_HVSP_SCINFORM_CONFIG; ++ ++//IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ++/** ++* Used to get private ID of hvsp device ++*/ ++typedef struct ++{ ++ signed long s32Id; ///< private ID ++}ST_IOCTL_HVSP_PRIVATE_ID_CONFIG; ++ ++//IOCTL_HVSP_PRIMASK_CONFIG ++/** ++* Used to set MASK of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned char bMask; /// ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup hvsp_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_ST_H ++#define _MDRV_HVSP_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++#define IOCTL_HVSP_VERSION 0x0100 ++ ++ ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to setup the input source of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_SRC_ISP, ///< input source: ISP ++ E_IOCTL_HVSP_SRC_BT656, ///< input source: BT656 ++ E_IOCTL_HVSP_SRC_DRAM, ///< input source: DRAM ++ E_IOCTL_HVSP_SRC_HVSP, ///< input source: HVSP1 ++ E_IOCTL_HVSP_SRC_PAT_TGEN, ///< input source: PATGEN ++ E_IOCTL_HVSP_SRC_NUM, ///< The max number of input source ++}EN_IOCTL_HVSP_SRC_TYPE; ++ ++/** ++* Used to setup the color format of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_COLOR_RGB, ///< color format:RGB ++ E_IOCTL_HVSP_COLOR_YUV444, ///< color format:YUV444 ++ E_IOCTL_HVSP_COLOR_YUV422, ///< color format:YUV422 ++ E_IOCTL_HVSP_COLOR_YUV420, ///< color format:YUV420 ++ E_IOCTL_HVSP_COLOR_NUM, ///< The max number of color format ++}EN_IOCTL_HVSP_COLOR_TYPE; ++ ++/** ++* Used to setup the IPR/W status of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_DNR_R = 1, ///< IP only read ++ E_IOCTL_HVSP_DNR_W = 2, ///< IP only write ++ E_IOCTL_HVSP_DNR_RW = 3, ///< IP R/W ++ E_IOCTL_HVSP_DNR_NUM= 4, ///< IP none open ++}EN_IOCTL_HVSP_DNR_TYPE; ++ ++/** ++* Used to setup the OSD locate of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ E_IOCTL_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_IOCTL_HVSP_OSD_LOC_TYPE; ++ ++/** ++* Used to setup the FB locate of hvsp device ++*/ ++typedef enum ++{ ++ EN_IOCTL_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_IOCTL_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_IOCTL_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++}EN_IOCTL_HVSP_FBMG_SET_TYPE; ++//============================================================================= ++// struct ++//============================================================================= ++/** ++* Used to get HVSP drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_VERSION_CONFIG; ++ ++/** ++* Used to setup the crop size of hvsp device ++*/ ++typedef struct ++{ ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop width size ++ unsigned short u16Height; ///< crop height size ++}ST_IOCTL_HVSP_WINDOW_CONFIG; ++ ++/** ++* Used to setup the HVSP timing gen of hvsp device ++*/ ++typedef struct ++{ ++ unsigned char bInterlace; ///< is interlace or progressive ++ unsigned short u16Htotal; ///< Htt ++ unsigned short u16Vtotal; ///< Vtt ++ unsigned short u16Vfrequency; ///< Vfreq ++}ST_IOCTL_HVSPTIMING_CONFIG; ++ ++//============================================================================= ++// struct for IOCTL_HVSP_SET_IN_CONFIG ++/** ++* Used to setup the input mux ,input capture window of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ EN_IOCTL_HVSP_SRC_TYPE enSrcType; ///< Input source type ++ EN_IOCTL_HVSP_COLOR_TYPE enColor; ///< color type ++ ST_IOCTL_HVSP_WINDOW_CONFIG stCaptureWin; ///< Input Source Size(input src is scl capture win ++ ST_IOCTL_HVSPTIMING_CONFIG stTimingCfg; ///< Input Timing ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_INPUT_CONFIG; ++ ++ ++// struct for IOCTL_HVSP_SET_OUT_CONFIG ++/** ++* Used to setup the output config of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ EN_IOCTL_HVSP_COLOR_TYPE enColor; ///< color type ++ ST_IOCTL_HVSP_WINDOW_CONFIG stDisplayWin; ///< display window size ++ ST_IOCTL_HVSPTIMING_CONFIG stTimingCfg; ///< output timing ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_OUTPUT_CONFIG; ++/** ++* Used to set CLK mux of hvsp device ++*/ ++typedef struct ++{ ++ struct clk* idclk; ///< idclk ++ struct clk* fclk1; ///< fclk (SC1 SC2 ++ struct clk* fclk2; ///< fclk (SC3 ++ struct clk* odclk; ///< odclk (display Lpll ++}ST_IOCTL_HVSP_CLK_CONFIG; ++// sturct for IOCTL_HVSP_SET_SCALING_CONFIG ++/** ++* Used to setup the crop and HVSP123 scaling configuration of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Src_Width; ///< post crop IN width ++ unsigned short u16Src_Height; ///< post crop IN height ++ unsigned short u16Dsp_Width; ///< after HVSP width ++ unsigned short u16Dsp_Height; ///< after HVSP height ++ unsigned char bCropEn; ///< Is post crop En ++ ST_IOCTL_HVSP_WINDOW_CONFIG stCropWin; ///< post crop size ++ ST_IOCTL_HVSP_CLK_CONFIG *stclk; ///< clk framework ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_SCALING_CONFIG; ++ ++//IOCTL_HVSP_REQ_MEM_CONFIG ++/** ++* Used to allocate the buffer and setup framebuffer configuration of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Vsize; ///< framebuffer height ++ unsigned short u16Pitch; ///< framebuffer width ++ unsigned long u32MemSize; ///< height*width *2(YUV422) *2(2frame) ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_REQ_MEM_CONFIG; ++ ++//IOCTL_HVSP_SET_MISC_CONFIG ++/** ++* Used to setup the register of hvsp device ++*/ ++typedef struct ++{ ++ unsigned char u8Cmd; ///< register value ++ unsigned long u32Size; ///< number ++ unsigned long u32Addr; ///< bank&addr ++}ST_IOCTL_HVSP_MISC_CONFIG; ++ ++//IOCTL HVSP_SET_POST_CROP_CONFIG ++/** ++* Used to setup the post crop of hvsp device if need ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned char bCropEn; ///< post crop En ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop frame width ++ unsigned short u16Height; ///< crop frame height ++ unsigned char bFmCntEn; ///< Is use CMDQ to set ++ unsigned char u8FmCnt; ///< when frame count ++ ST_IOCTL_HVSP_CLK_CONFIG *stclk; /// ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_ISP_IO_H ++#define _MDRV_ISP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// Defines ++//============================================================================= ++ ++#define ISP_IOCTL_MAGIC 'I' ++#define IOCTL_ISP_CLOCK_CTL _IO(ISP_IOCTL_MAGIC, 0x1) ++#define IOCTL_ISP_IQ_RGBCCM _IO(ISP_IOCTL_MAGIC, 0x2) ++#define IOCTL_ISP_IQ_YUVCCM _IO(ISP_IOCTL_MAGIC, 0x3) ++#define IOCTL_ISP_GET_ISP_FLAG _IO(ISP_IOCTL_MAGIC, 0x4) ++#define IOCTL_ISP_GET_INFO _IO(ISP_IOCTL_MAGIC, 0x5) ++#define IOCTL_ISP_GET_MEM_INFO _IO(ISP_IOCTL_MAGIC, 0x6) ++#define IOCTL_ISP_GET_AE_IMG_INFO _IO(ISP_IOCTL_MAGIC, 0x7) ++#define IOCTL_ISP_SET_AE_DGAIN _IO(ISP_IOCTL_MAGIC, 0x8) ++#define IOCTL_ISP_SET_FIFO_MASK _IO(ISP_IOCTL_MAGIC, 0x9) ++#define IOCTL_ISP_UPDATE_AE_IMG_INFO _IO(ISP_IOCTL_MAGIC, 0xa) ++#define IOCTL_ISP_TRIGGER_WDMA _IO(ISP_IOCTL_MAGIC, 0xb) ++#define IOCTL_ISP_SKIP_FRAME _IO(ISP_IOCTL_MAGIC, 0xc) ++#define IOCTL_ISP_INIT _IO(ISP_IOCTL_MAGIC, 0xd) ++#endif //_MDRV_GFLIP_IO_H +diff --git a/drivers/sstar/include/mdrv_isp_io_st.h b/drivers/sstar/include/mdrv_isp_io_st.h +new file mode 100755 +index 000000000000..6022c905580e +--- /dev/null ++++ b/drivers/sstar/include/mdrv_isp_io_st.h +@@ -0,0 +1,225 @@ ++/* ++* mdrv_isp_io_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_ISP_IO_ST_H ++#define _MDRV_ISP_IO_ST_H ++ ++#define CLK_ID_ISP 0 ++#define CLK_ID_SR 1 ++#define CLK_ID_SR_MCLK 2 ++#define CLK_ID_CSI_MAC 3 ++typedef struct ++{ ++ unsigned int id; ++ unsigned int rate; ++ unsigned int enable; ++}isp_ioctl_clock_ctl; ++ ++//// for ioctl IOCTL_ISP_IQ_YUVCCM, IOCTL_ISP_IQ_RGBCCM //// ++typedef struct ++{ ++ s16 ccm[9]; ++} __attribute__((packed, aligned(1))) isp_ioctl_ccm_coeff; ++ ++ ++//// for ioctl ioctl IOCTL_ISP_GET_ISP_FLAG //// ++//same IspBufferFlag_e ++#define ISP_FLAG_ENABLE_ROT 0x01 ++#define ISP_FLAG_ENABLE_DNR 0x02 ++typedef struct ++{ ++ u32 flag; ++} __attribute__((packed, aligned(1))) isp_ioctl_isp_flag; ++ ++//// for ioctl ioctl IOCTL_ISP_GET_MEM_INFO //// ++#define ISP_GET_MEM_INFO_BASE 0x00 ++#define ISP_GET_MEM_INFO_AE 0x01 ++#define ISP_GET_MEM_INFO_AWB 0x02 ++#define ISP_GET_MEM_INFO_AF 0x03 ++#define ISP_GET_MEM_INFO_MOT 0x04 ++#define ISP_GET_MEM_INFO_HISTO 0x05 ++#define ISP_GET_MEM_INFO_RGBIR 0x06 ++ ++typedef struct ++{ ++ u32 mem_id; ++ u32 phy_addr; ++ u32 blk_offset; ++ u32 blk_size; ++} __attribute__((packed, aligned(1))) isp_ioctl_mem_info; ++ ++typedef struct ++{ ++ u32 fcount; //frame count ++}__attribute__((packed, aligned(1))) isp_isr_event_data; ++ ++typedef struct ++{ ++ u32 frame_cnt; ++ u32 hw_frame_cnt; ++}__attribute__((packed, aligned(1))) ve_isr_data; //vsync end isr data ++ ++//// for IOCTL_ISP_GET_AE_IMG_INFO //// ++typedef struct ++{ ++ u32 img_w; ++ u32 img_h; ++ u32 blk_w; ++ u32 blk_h; ++ u32 rot; ++}__attribute__((packed, aligned(1))) isp_isr_ae_img_info; ++u32 isp_get_ae_img_info(isp_isr_ae_img_info *info); //kernel api only ++ ++//// for IOCTL_ISP_SET_AE_DGAIN //// ++typedef struct ++{ ++ u32 enable; ++ u32 dgain; //1X = 1024 ++} __attribute__((packed, aligned(1))) isp_ioctl_ae_dgian; ++ ++//// for IOCTL_ISP_SET_FIFO_MASK//// ++typedef struct ++{ ++ u32 enable; ++} __attribute__((packed, aligned(1))) isp_ioctl_fifo_mask; ++ ++//// for IOCTL_ISP_TRIGGER_WDMA//// ++ ++ ++typedef enum ++{ ++ ISP_WDMA_ICP, ++ ISP_WDMA_SIF, ++ ISP_WDMA_ISP, ++ ISP_WDMA_ISPDS, ++ ISP_WDMA_ISPSWAPYC, ++ ISP_WDMA_VDOS, ++ ISP_WDMA_DEFAULT_SIF, ++ ISP_WDMA_DEFAULT_YC ++}WDMA_PATH; ++ ++typedef struct ++{ ++ u32 width; ++ u32 height; ++ u32 x; ++ u32 y; ++ WDMA_PATH wdma_path; ++ u32 buf_addr_phy; ++ u32 buf_addr_kvir; ++} __attribute__((packed, aligned(1))) isp_ioctl_trigger_wdma_attr; ++ ++ ++ ++typedef struct ++{ ++ u32 skip_cnt; ++} __attribute__((packed, aligned(1))) isp_ioctl_trigger_skip_attr; ++ ++ ++typedef enum ++{ ++ ISP_COLOR_ID_R, ++ ISP_COLOR_ID_GR, ++ ISP_COLOR_ID_GB, ++ ISP_COLOR_ID_B, ++}IspColorID_e; ++ ++//frame buffer control bit ++typedef enum ++{ ++ ISP_FB_ROT = 0x01, //enable ROR frame buffer ++ ISP_FB_DNR = 0x02, //enable BDNR frame buffer ++}IspFrameBufferFlag_e; ++ ++typedef struct ++{ ++ u32 nSize; //size of this struct in byte ++ u32 nRawX; ++ u32 nRawY; ++ u32 nRawW; ++ u32 nRawH; ++ u32 nDnrFlag; ++ //u32 nColorID; ++ //u32 nPixelDepth; ++} __attribute__((packed, aligned(1))) isp_ioctl_isp_init; ++ ++typedef enum ++{ ++ WDMA_SRC_BAYER_RAW = 0, ++ WDMA_SRC_ISP_OUTPUT_0 = 1, ++ WDMA_SRC_ISP_OUTPUT_1 = 2, ++ WDMA_SRC_ISP_VIDEO_STABILIZATION=3, ++}WDMA_SRC; ++ ++typedef enum ++{ ++ WDMA_REQ_WAIT = 0, ++ WDMA_REQ_PROC = 1, ++ WDMA_REQ_DONE = 2, ++}WDMA_REQ_STATUS; ++ ++typedef struct ++{ ++ u32 uSourceSel; ++ u32 uBufferPhysAddr; ++ WDMA_SRC uReqStatus; //WDMA_SRC ++}__attribute__((packed, aligned(1))) WDMA_CFG; ++ ++ ++typedef struct ++{ ++ u32 bActive; //Active data state ++ u32 u4FrameCnt; //frame count ++ u32 bIspInputEnable; ++ u32 u4OBCInValid; ++ u32 u4OBC_a; ++ u32 u4OBC_b; ++ u32 uIspStatusSet; // isp status set from user space ++ u32 uIspStatusReport; //isp satus get from kernel space ++ WDMA_CFG wdma_cfg; ++}__attribute__((packed, aligned(1))) FRAME_STATE; ++ ++ ++typedef enum ++{ ++ FRAME_START_EVENT = 0x00000001, ++ FRAME_END_EVENT = 0x00000002, ++ AE_DONE_EVENT = 0x00000004, ++ AWB_DONE_EVENT = 0x00000008, ++ AF_DONE_EVENT = 0x00000010, ++ WDMA_DONE_EVENT = 0x00000020, ++ FIFO_FULL_EVENT = 0x00000040, ++ IDLE_EVENT = 0x00000080, ++ RDMA_DONE_EVENT = 0x00000100, ++ SCL_VEND_EVENT = 0x00000200, ++}INTERRUPT_EVENT_e; ++ ++typedef struct ++{ ++ u32 u32IspInt1; ++ u32 u32IspInt2; ++ u32 u32IspInt3; ++}__attribute__((packed, aligned(1))) ISP_INTERRUPTS_STATE; ++ ++ ++typedef struct ++{ ++ FRAME_STATE frame_state; ++ ISP_INTERRUPTS_STATE isp_ints_state; ++}__attribute__((packed, aligned(1))) ISP_SHARE_DATA; ++#endif +diff --git a/drivers/sstar/include/mdrv_ive_io.h b/drivers/sstar/include/mdrv_ive_io.h +new file mode 100755 +index 000000000000..90425df09941 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_ive_io.h +@@ -0,0 +1,24 @@ ++/* ++* mdrv_ive_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_IVE_IO_H_ ++#define _MDRV_IVE_IO_H_ ++ ++#define IVE_IOC_MAGIC 'I' ++#define IVE_IOC_PROCESS _IOW(IVE_IOC_MAGIC, 1, ive_ioc_config*) ++ ++#endif // _MDRV_IVE_IO_H_ +diff --git a/drivers/sstar/include/mdrv_ive_io_st.h b/drivers/sstar/include/mdrv_ive_io_st.h +new file mode 100755 +index 000000000000..93b0b3609a29 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_ive_io_st.h +@@ -0,0 +1,438 @@ ++/* ++* mdrv_ive_io_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_IVE_IO_ST_H_ ++#define _MDRV_IVE_IO_ST_H_ ++ ++#include ++#include ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ IVE_IOC_ERROR_NONE = 0x0000, ++ IVE_IOC_ERROR_IN_OUT_SIZE_DIFFERENT = 0x1000, ++ IVE_IOC_ERROR_IMG_TOO_SMALL = 0x1001, ++ IVE_IOC_ERROR_PROC_CONFIG = 0x1002, ++ IVE_IOC_ERROR_BUSY = 0x1003, ++ IVE_IOC_ERROR_MEMROY_FAILURE = 0x1004, ++ IVE_IOC_ERROR_CLK = 0x1005 ++} IVE_IOC_ERROR; ++ ++typedef enum ++{ ++ IVE_IOC_OP_TYPE_FILTER = 0x00, ++ IVE_IOC_OP_TYPE_CSC = 0x01, ++ IVE_IOC_OP_TYPE_FILTER_AND_CSC = 0x02, ++ IVE_IOC_OP_TYPE_SOBEL = 0x03, ++ IVE_IOC_OP_TYPE_MAG_AND_ANG = 0x04, ++ IVE_IOC_OP_TYPE_ORD_STA_FILTER = 0x05, ++ IVE_IOC_OP_TYPE_BERNSEN = 0x06, ++ IVE_IOC_OP_TYPE_DILATE = 0x07, ++ IVE_IOC_OP_TYPE_ERODE = 0x08, ++ IVE_IOC_OP_TYPE_THRESH = 0x09, ++ IVE_IOC_OP_TYPE_THRESH_S16 = 0x0A, ++ IVE_IOC_OP_TYPE_THRESH_U16 = 0x0B, ++ IVE_IOC_OP_TYPE_AND = 0x0C, ++ IVE_IOC_OP_TYPE_OR = 0x0D, ++ IVE_IOC_OP_TYPE_XOR = 0x0E, ++ IVE_IOC_OP_TYPE_ADD = 0x0F, ++ IVE_IOC_OP_TYPE_SUB = 0x10, ++ IVE_IOC_OP_TYPE_16BIT_TO_8BIT = 0x11, ++ IVE_IOC_OP_TYPE_MAP = 0x12, ++ IVE_IOC_OP_TYPE_HISTOGRAM = 0x13, ++ IVE_IOC_OP_TYPE_INTEGRAL = 0x14, ++ IVE_IOC_OP_TYPE_SAD = 0x15, ++ IVE_IOC_OP_TYPE_NCC = 0x16, ++ IVE_IOC_OP_TYPE_LBP = 0x18, ++ IVE_IOC_OP_TYPE_BAT = 0x19, ++ IVE_IOC_OP_TYPE_ADP_THRESH = 0x1A, ++ IVE_IOC_OP_TYPE_MATRIX_TRANSFORM = 0x1F, ++ IVE_IOC_OP_TYPE_IMAGE_DOT = 0x20 ++} IVE_IOC_OP_TYPE; ++ ++typedef enum ++{ ++ IVE_IOC_IMAGE_FORMAT_B8C1 = 0x00, ++ IVE_IOC_IMAGE_FORMAT_B8C3_PLAN = 0x02, ++ IVE_IOC_IMAGE_FORMAT_B16C1 = 0x03, ++ IVE_IOC_IMAGE_FORMAT_B8C3_PACK = 0x04, ++ IVE_IOC_IMAGE_FORMAT_420SP = 0x05, ++ IVE_IOC_IMAGE_FORMAT_422SP = 0x06, ++ IVE_IOC_IMAGE_FORMAT_B32C1 = 0x80, // dummy enum for destination buffer ++ IVE_IOC_IMAGE_FORMAT_B64C1 = 0x81 // dummy enum for destination buffer ++} IVE_IOC_IMAGE_FORMAT; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SOBEL_BOTH = 0x00, ++ IVE_IOC_MODE_SOBEL_HORIZONTAL = 0x01, ++ IVE_IOC_MODE_SOBEL_VERTICAL = 0x02, ++} IVE_IOC_MODE_SOBEL; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_MAG_AND_ANG_ONLY_MAG = 0x00, ++ IVE_IOC_MODE_MAG_AND_ANG_BOTH = 0x01 ++} IVE_IOC_MODE_MAG_AND_ANG; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_ORD_STAT_FILTER_MEDIAN = 0x00, ++ IVE_IOC_MODE_ORD_STAT_FILTER_MAX = 0x01, ++ IVE_IOC_MODE_ORD_STAT_FILTER_MIN = 0x02, ++ ++} IVE_IOC_MODE_ORD_STAT_FILTER; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_BERNSEN_NORMAL_3X3 = 0x00, ++ IVE_IOC_MODE_BERNSEN_NORMAL_5X5 = 0x01, ++ IVE_IOC_MODE_BERNSEN_THRESH_3X3 = 0x02, ++ IVE_IOC_MODE_BERNSEN_THRESH_5X5 = 0x03 ++} IVE_IOC_MODE_BERNSEN; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_THRESH_BINARY = 0x00, ++ IVE_IOC_MODE_THRESH_TRUNC = 0x01, ++ IVE_IOC_MODE_THRESH_TO_MINVAL = 0x02, ++ IVE_IOC_MODE_THRESH_MIN_MID_MAX = 0x03, ++ IVE_IOC_MODE_THRESH_ORI_MID_MAX = 0x04, ++ IVE_IOC_MODE_THRESH_MIN_MID_ORI = 0x05, ++ IVE_IOC_MODE_THRESH_MIN_ORI_MAX = 0x06, ++ IVE_IOC_MODE_THRESH_ORI_MID_ORI = 0x07 ++} IVE_IOC_MODE_THRESH; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_THRESH_S16_TO_S8_MIN_MID_MAX = 0x00, ++ IVE_IOC_MODE_THRESH_S16_TO_S8_MIN_ORI_MAX = 0x01, ++ IVE_IOC_MODE_THRESH_S16_TO_U8_MIN_MID_MAX = 0x02, ++ IVE_IOC_MODE_THRESH_S16_TO_U8_MIN_ORI_MAX = 0x03, ++ ++} IVE_IOC_MODE_THRESH_S16; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_THRESH_U16_TO_U8_MIN_MID_MAX = 0x00, ++ IVE_IOC_MODE_THRESH_U16_TO_U8_MIN_ORI_MAX = 0x01, ++ ++} IVE_IOC_MODE_THRESH_U16; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_ADD_ROUNDING = 0x00, ++ IVE_IOC_MODE_ADD_CLIPPING = 0x01, ++} IVE_IOC_MODE_ADD; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SUB_ABS = 0x00, ++ IVE_IOC_MODE_SUB_SHIFT = 0x01, ++} IVE_IOC_MODE_SUB; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_S16_TO_S8 = 0x00, ++ IVE_IOC_MODE_S16_TO_U8_ABS = 0x01, ++ IVE_IOC_MODE_S16_TO_U8_BIAS = 0x02, ++ IVE_IOC_MODE_U16_TO_U8 = 0x03, ++ ++} IVE_IOC_MODE_16_TO_8; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_INTEGRAL_BOTH = 0x00, ++ IVE_IOC_MODE_INTEGRAL_SUM = 0x01, ++ IVE_IOC_MODE_INTEGRAL_SQUARE_SUM = 0x02 ++} IVE_IOC_MODE_INTEGRAL; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SAD_BLOCK_4X4 = 0x00, ++ IVE_IOC_MODE_SAD_BLOCK_8X8 = 0x01, ++ IVE_IOC_MODE_SAD_BLOCK_16X16 = 0x02, ++ ++} IVE_IOC_MODE_SAD_BLOCK; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SAD_OUT_CTRL_16BIT_BOTH = 0x00, ++ IVE_IOC_MODE_SAD_OUT_CTRL_8BIT_BOTH = 0x01, ++ IVE_IOC_MODE_SAD_OUT_CTRL_16BIT_SAD = 0x02, ++ IVE_IOC_MODE_SAD_OUT_CTRL_8BIT_SAD = 0x03, ++ IVE_IOC_MODE_SAD_OUT_CTRL_THRESH = 0x04 ++} IVE_IOC_MODE_SAD_OUT; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_LBP_COMP_NORMAL = 0x00, ++ IVE_IOC_MODE_LBP_COMP_ABS = 0x01, ++ IVE_IOC_MODE_LBP_COMP_ABS_MUL = 0x02, ++ ++} IVE_IOC_MODE_LBP; ++ ++typedef enum ++{ ++ IVE_IOC_CHANNEL_MODE_LBP_C1 = 0x00, ++ IVE_IOC_CHANNEL_MODE_LBP_C2 = 0x01, ++ ++}IVE_IOC_CHANNEL_MODE_LBP; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_MATRIX_TRANSFORM_C1 = 0x00, ++ IVE_IOC_MODE_MATRIX_TRANSFORM_C2 = 0x01, ++ IVE_IOC_MODE_MATRIX_TRANSFORM_C3 = 0x02 ++ ++} IVE_IOC_CHANNEL_MODE_MATRIX_TRANSFORM; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_MATRIX_TRANSFORM_ROUNDING = 0x00, ++ IVE_IOC_MODE_MATRIX_TRANSFORM_CLIPPING = 0x01 ++ ++} IVE_IOC_CONTROL_MODE_MATRIX_TRANSFORM; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_IMAGE_DOT_ROUNDING = 0x00, ++ IVE_IOC_MODE_IMAGE_DOT_CLIPPING = 0x01, ++ ++} IVE_IOC_MODE_IMAGE_DOT; ++ ++typedef struct ++{ ++ IVE_IOC_IMAGE_FORMAT format; ++ ++ __u16 width; ++ __u16 height; ++ void* address[3]; ++ __u16 stride[3]; ++} ive_ioc_image; ++ ++typedef struct ++{ ++ __u8 mask[25]; ++ __u8 shift; ++} ive_ioc_coeff_filter; ++ ++typedef struct ++{ ++ __u8 clamp_low; ++ __u8 clamp_high; ++} ive_ioc_coeff_csc_clamp; ++ ++typedef struct ++{ ++ __u16 coeff[9]; ++ __u16 offset[3]; ++ ive_ioc_coeff_csc_clamp clamp[3]; ++} ive_ioc_coeff_csc; ++ ++typedef struct ++{ ++ ive_ioc_coeff_filter filter; ++ ive_ioc_coeff_csc csc; ++} ive_ioc_coeff_filter_csc; ++ ++ ++typedef struct ++{ ++ IVE_IOC_MODE_SOBEL mode; ++ __u8 mask[25]; ++} ive_ioc_coeff_sobel; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_MAG_AND_ANG mode; ++ __u8 mask[25]; ++ __u16 thresh; ++} ive_ioc_coeff_mag_and_ang; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_ORD_STAT_FILTER mode; ++} ive_ioc_coeff_ord_stat_filter; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_BERNSEN mode; ++ __u16 thresh; ++} ive_ioc_coeff_bernsen; ++ ++typedef struct ++{ ++ __u8 mask[25]; ++} ive_ioc_coeff_dilate; ++ ++typedef struct ++{ ++ __u8 mask[25]; ++} ive_ioc_coeff_erode; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_THRESH mode; ++ __u16 low; ++ __u16 high; ++ __u8 min; ++ __u8 mid; ++ __u8 max; ++} ive_ioc_coeff_thresh; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_THRESH_S16 mode; ++ __u16 low; ++ __u16 high; ++ __u8 min; ++ __u8 mid; ++ __u8 max; ++} ive_ioc_coeff_thresh_s16; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_THRESH_U16 mode; ++ __u16 low; ++ __u16 high; ++ __u8 min; ++ __u8 mid; ++ __u8 max; ++} ive_ioc_coeff_thresh_u16; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_ADD mode; ++ __u16 weight_x; ++ __u16 weight_y; ++} ive_ioc_coeff_add; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_SUB mode; ++} ive_ioc_coeff_sub; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_16_TO_8 mode; ++ __u16 denominator; ++ __u8 numerator; ++ __s8 bias; ++} ive_ioc_coeff_16to8; ++ ++typedef struct ++{ ++ __u8 *map; ++} ive_ioc_coeff_map; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_INTEGRAL mode; ++} ive_ioc_coeff_integral; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_SAD_BLOCK block_mode; ++ IVE_IOC_MODE_SAD_OUT out_mode; ++ __u16 thresh; ++ __u8 min; ++ __u8 max; ++} ive_ioc_coeff_sad; ++ ++typedef struct ++{ ++ __u64 numerator; ++ __u64 sum1; ++ __u64 sum2; ++} ive_ioc_coeff_ncc; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_LBP mode; ++ IVE_IOC_CHANNEL_MODE_LBP chlmode; ++ __u16 thresh; ++} ive_ioc_coeff_lbp; ++ ++typedef struct ++{ ++ __u16 h_times; ++ __u16 v_times; ++} ive_ioc_coeff_bat; ++ ++typedef struct ++{ ++ __u8 u8RateThr; ++ __u8 u8HalfMaskx; ++ __u8 u8HalfMasky; ++ __s8 s8Offset; ++ __u8 u8ValueThr; ++} ive_ioc_coeff_adp_thresh; ++ ++typedef struct ++{ ++ IVE_IOC_CHANNEL_MODE_MATRIX_TRANSFORM chl_mode; ++ IVE_IOC_CONTROL_MODE_MATRIX_TRANSFORM ctrl_mode; ++ __u16 s16MatrixArray[9]; ++}ive_ioc_coeff_matrix_transform; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_IMAGE_DOT mode; ++}ive_ioc_coeff_image_dot; ++ ++typedef struct ++{ ++ IVE_IOC_OP_TYPE op_type; ++ ++ ive_ioc_image input; ++ ive_ioc_image output; ++ ++ union ++ { ++ ive_ioc_coeff_filter coeff_filter; ++ ive_ioc_coeff_csc coeff_csc; ++ ive_ioc_coeff_filter_csc coeff_filter_csc; ++ ive_ioc_coeff_sobel coeff_sobel; ++ ive_ioc_coeff_mag_and_ang coeff_mag_and_ang; ++ ive_ioc_coeff_ord_stat_filter coeff_ord_stat_filter; ++ ive_ioc_coeff_bernsen coeff_bernsen; ++ ive_ioc_coeff_dilate coeff_dilate; ++ ive_ioc_coeff_erode coeff_erode; ++ ive_ioc_coeff_thresh coeff_thresh; ++ ive_ioc_coeff_thresh_s16 coeff_thresh_s16; ++ ive_ioc_coeff_thresh_u16 coeff_thresh_u16; ++ ive_ioc_coeff_add coeff_add; ++ ive_ioc_coeff_sub coeff_sub; ++ ive_ioc_coeff_16to8 coeff_16to8; ++ ive_ioc_coeff_map coeff_map; ++ ive_ioc_coeff_integral coeff_integral; ++ ive_ioc_coeff_sad coeff_sad; ++ ive_ioc_coeff_ncc *coeff_ncc; ++ ive_ioc_coeff_lbp coeff_lbp; ++ ive_ioc_coeff_bat coeff_bat; ++ ive_ioc_coeff_adp_thresh coeff_adp_thresh; ++ ive_ioc_coeff_matrix_transform coeff_matrix_transform; ++ ive_ioc_coeff_image_dot coeff_image_dot; ++ }; ++} ive_ioc_config; ++ ++#endif //_MDRV_IVE_IO_ST_H_ +diff --git a/drivers/sstar/include/mdrv_jpe_io.h b/drivers/sstar/include/mdrv_jpe_io.h +new file mode 100755 +index 000000000000..c818b148e70c +--- /dev/null ++++ b/drivers/sstar/include/mdrv_jpe_io.h +@@ -0,0 +1,44 @@ ++/* ++* mdrv_jpe_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_JPE_IO_H_ ++#define _MDRV_JPE_IO_H_ ++ ++#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ ++#define IOC_JPE_VOID 0x20000000 /* no parameters */ ++#define IOC_JPE_OUT 0x40000000 /* copy out parameters */ ++#define IOC_JPE_IN 0x80000000 /* copy in parameters */ ++#define IOC_JPE_INOUT (IOC_JPE_IN|IOC_JPE_OUT) ++ ++#define _IO_JPE(x,y) (IOC_JPE_VOID|((x)<<8)|(y)) ++#define _IOR_JPE(x,y,t) (IOC_JPE_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++#define _IOW_JPE(x,y,t) (IOC_JPE_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++ ++//JPE IOC COMMANDS ++#define JPE_IOC_MAGIC 'J' ++// Initialize *pJpeInfo ++#define JPE_IOC_INIT _IO_JPE(JPE_IOC_MAGIC, 0) ++// Set up JPE RIU and fire JPE ++#define JPE_IOC_ENCODE_FRAME _IO_JPE(JPE_IOC_MAGIC, 1) ++// Get output buffer status ++#define JPE_IOC_GETBITS _IOR_JPE(JPE_IOC_MAGIC, 2, __u32) ++// ++#define JPE_IOC_GET_CAPS _IOR_JPE(JPE_IOC_MAGIC, 3, __u32) ++// ++#define JPE_IOC_SET_OUTBUF _IOR_JPE(JPE_IOC_MAGIC, 4, __u32) ++ ++#endif // _MDRV_JPE_IO_H_ +\ No newline at end of file +diff --git a/drivers/sstar/include/mdrv_jpe_io_st.h b/drivers/sstar/include/mdrv_jpe_io_st.h +new file mode 100755 +index 000000000000..269532770a96 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_jpe_io_st.h +@@ -0,0 +1,134 @@ ++/* ++* mdrv_jpe_io_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_JPE_IO_ST_H_ ++#define _MDRV_JPE_IO_ST_H_ ++ ++#include ++#include ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ JPE_IBUF_ROW_MODE = 0x0, ++ JPE_IBUF_FRAME_MODE = 0x1 ++} JpeInBufMode_e; ++ ++typedef enum ++{ ++ JPE_RAW_YUYV = 0x0, ++ JPE_RAW_YVYU = 0x1, ++ JPE_RAW_NV12 = 0x3, ++ JPE_RAW_NV21 = 0x4, ++} JpeRawFormat_e; ++ ++typedef enum ++{ ++ JPE_CODEC_JPEG = 0x1, ++ JPE_CODEC_H263I = 0x2, //! obsolete ++ JPE_CODEC_ENCODE_DCT = 0x4, //! obsolete ++} JpeCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_IDLE_STATE = 0, ++ JPE_BUSY_STATE = 1, ++ JPE_FRAME_DONE_STATE = 2, ++ JPE_OUTBUF_FULL_STATE = 3, ++ JPE_INBUF_FULL_STATE = 4 ++} JpeState_e; ++ ++typedef enum ++{ ++ JPE_IOC_RET_SUCCESS = 0, ++ JPE_IOC_RET_BAD_QTABLE = 1, ++ JPE_IOC_RET_BAD_QP = 2, ++ JPE_IOC_RET_BAD_BITSOFFSET = 3, ++ JPE_IOC_RET_BAD_BANKNUM = 4, ++ JPE_IOC_RET_BAD_INBUF = 5, ++ JPE_IOC_RET_BAD_OUTBUF = 6, ++ JPE_IOC_RET_BAD_NULLPTR = 7, ++ JPE_IOC_RET_BAD_BANKCNT = 8, ++ JPE_IOC_RET_BAD_LASTZZ = 9, ++ JPE_IOC_RET_UNKOWN_COMMAND = 10, ++ JPE_IOC_RET_BAD_VIRTUAL_MEM = 11, ++ JPE_IOC_RET_NEED_DRIVER_INIT = 12, ++ JPE_IOC_RET_FMT_NOT_SUPPORT = 13, ++ JPE_IOC_RET_HW_IS_RUNNING = 14, ++ JPE_IOC_RET_FAIL = 15 ++} JPE_IOC_RET_STATUS_e; ++ ++typedef enum ++{ ++ JPE_COLOR_PLAN_LUMA = 0, ++ JPE_COLOR_PLAN_CHROMA = 1, ++ JPE_COLOR_PLAN_MAX = 2 ++} JPE_COLOR_PLAN_e; ++ ++typedef struct ++{ ++ __u32 __u32JpeId; ++ __u32 nRefYLogAddrAlign[2]; ++ __u32 nRefCLogAddrAlign[2]; ++ __u32 nOutBufSLogAddrAlign; ++ __u8 nSclHandShakeSupport; ++ __u8 nCodecSupport; ++ __u8 nBufferModeSupport; ++} JpeCaps_t, *pJpeCaps; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; ++ unsigned long nOutputSize; ++ JpeState_e eState; ++} JpeBitstreamInfo_t, *pJpeBitstreamInfo; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nSize; ++} JpeBufInfo_t; ++ ++typedef struct ++{ ++ JpeInBufMode_e eInBufMode; ++ JpeRawFormat_e eRawFormat; ++ JpeCodecFormat_e eCodecFormat; ++ __u32 nWidth; ++ __u32 nHeight; ++ __u16 YQTable[64]; ++ __u16 CQTable[64]; ++ __u16 nQScale; ++ JpeBufInfo_t InBuf[JPE_COLOR_PLAN_MAX]; ++ JpeBufInfo_t OutBuf; ++ __u32 nJpeOutBitOffset; ++} JpeCfg_t; ++ ++ ++typedef struct JpeEncOutbuf_t ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; // Original buffer Size ++ unsigned long nOutputSize; // Output Size ++ JpeState_e eState; ++} JpeEncOutbuf_t; ++ ++#endif //_MDRV_JPE_IO_ST_H_ +\ No newline at end of file +diff --git a/drivers/sstar/include/mdrv_mfe_io.h b/drivers/sstar/include/mdrv_mfe_io.h +new file mode 100755 +index 000000000000..e84d5f3bcccf +--- /dev/null ++++ b/drivers/sstar/include/mdrv_mfe_io.h +@@ -0,0 +1,135 @@ ++/* ++* mdrv_mfe_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MDRV_MMFE_IO_H_ ++#define _MDRV_MMFE_IO_H_ ++ ++/* definition of structures */ ++ ++#define MEMORY_USER 0 ++#define MEMORY_MMAP 1 ++ ++#define PIXFMT_TILED 0 ++#define PIXFMT_PLANE 1 ++ ++typedef struct mmfe_reqbuf { ++ int i_vq; ++ int i_memory; ++ int i_pic_w, i_pic_h; ++ int i_count; ++} mmfe_reqbuf; ++ ++typedef struct mmfe_buffer { ++ int i_vq; ++ int i_vb; ++ int i_memory; ++ int i_planes; ++ struct { ++ union { ++ unsigned int addr; ++ void* uptr; ++ }; ++ int size; ++ int used; ++ } planes[4]; ++ long long timecode; ++} mmfe_buffer; ++ ++#define MVIDPARAMS_PIXELS 0 ++#define MVIDPARAMS_FRAMERATE 1 ++#define MVIDPARAMS_MOTION 2 ++#define MVIDPARAMS_BITRATE 3 ++#define MVIDPARAMS_GOP 4 ++#define MVIDPARAMS_AVC 5 ++ ++#define RC_METHOD_CBR 0 ++#define RC_METHOD_VBR 1 ++#define RC_METHOD_CONST 2 ++ ++#define MV_BLOCK_4x4 (1<<0) ++#define MV_BLOCK_8x4 (1<<1) ++#define MV_BLOCK_4x8 (1<<2) ++#define MV_BLOCK_8x8 (1<<3) ++#define MV_BLOCK_16x8 (1<<4) ++#define MV_BLOCK_8x16 (1<<5) ++#define MV_BLOCK_16x16 (1<<6) ++#define MV_BLOCK_SKIP (1<<7) ++ ++typedef struct mmfe_params { ++ int i_params; ++ union { ++ unsigned char bytes[60]; ++ struct { ++ int i_pict_w; /* picture width */ ++ int i_pict_h; /* picture height */ ++ int i_pixfmt; /* pixel format */ ++ } pixels; ++ struct { ++ int i_num; /* numerator of frame-rate */ ++ int i_den; /* denominator of frame-rate */ ++ } framerate; ++ struct { ++ int i_dmv_x; /* dMV x-direction (8~16) */ ++ int i_dmv_y; /* dMV y-direction (8/16) */ ++ int i_subpel; /* subpel: 0-integral,1-half,2-quarter */ ++ unsigned int i_mv_block[2]; /* motion block flags */ ++ } motion; ++ struct { ++ int i_pframes; /* p-frames count per i-frame */ ++ int i_bframes; /* b-frames count per i/p-frame */ ++ } gop; ++ struct { ++ int i_method; /* constant bit-rate/variable bit-rate/constant quality */ ++ int i_kbps; /* bps/1024 */ ++ int i_qp; /* qp-value */ ++ } bitrate; ++ struct { ++ int i_profile; /* avc profile value */ ++ int i_level; /* avc level value */ ++ int i_num_ref_frames; /* reference frame count */ ++ int b_cabac; /* entropy: cabac/cavlc */ ++ int b_constrained_intra_pred; /* contrained intra pred */ ++ int b_deblock_filter_control; /* deblock filter control */ ++ int i_disable_deblocking_idc; /* disable deblocking idc */ ++ int i_alpha_c0_offset; /* offset alpha div2 */ ++ int i_beta_offset; /* offset beta div2 */ ++ int b_multiple_slices; /* multi-slices */ ++ } avc; ++ }; ++} mmfe_params; ++ ++typedef struct mmfe_control { ++ int i_control; ++ int i_value; ++} mmfe_control; ++ ++/* definition of ioctl codes */ ++ ++#define IOCTL_MFE_S_PARM _IOWR('m', 0,struct mmfe_params) ++#define IOCTL_MFE_G_PARM _IOWR('m', 1,struct mmfe_params) ++#define IOCTL_MFE_S_CTRL _IOWR('m', 2,struct mmfe_control) ++#define IOCTL_MFE_G_CTRL _IOWR('m', 3,struct mmfe_control) ++#define IOCTL_MFE_STREAMON _IO('m', 4) ++#define IOCTL_MFE_STREAMOFF _IO('m', 5) ++#define IOCTL_MFE_REQBUF _IOWR('m', 6,struct mmfe_reqbuf) ++#define IOCTL_MFE_S_PICT _IOWR('m', 7,struct mmfe_buffer) ++#define IOCTL_MFE_G_BITS _IOWR('m', 8,struct mmfe_buffer) ++#define IOCTL_MFE_FLUSH _IO('m', 9) ++ ++#endif//_MDRV_MMFE_IO_H_ ++ +diff --git a/drivers/sstar/include/mdrv_mma_heap.h b/drivers/sstar/include/mdrv_mma_heap.h +new file mode 100755 +index 000000000000..3b5e3cc17bcd +--- /dev/null ++++ b/drivers/sstar/include/mdrv_mma_heap.h +@@ -0,0 +1,36 @@ ++/* ++* mdrv_mma_heap.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++ ++ ++ ++#define MMA_HEAP_NAME_LENG 32 ++ ++//enable max mma areas be a large value . ++#define MAX_MMA_AREAS 30 ++ ++struct MMA_BootArgs_Config { ++ int miu;//input :from bootargs or dts ++ unsigned long size;//input :from bootargs or dts ++ char name[MMA_HEAP_NAME_LENG];//input :from bootargs or dts ++ unsigned long max_start_offset_to_curr_bus_base; ++ unsigned long max_end_offset_to_curr_bus_base;//input:for vdec use. ++ ++ phys_addr_t reserved_start;//out: reserved_start ++}; +diff --git a/drivers/sstar/include/mdrv_mmfe_io.h b/drivers/sstar/include/mdrv_mmfe_io.h +new file mode 100755 +index 000000000000..e7388950516e +--- /dev/null ++++ b/drivers/sstar/include/mdrv_mmfe_io.h +@@ -0,0 +1,57 @@ ++/* ++* mdrv_mmfe_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_MMFE_IO_H_ ++#define _MDRV_MMFE_IO_H_ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++#include ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Magic Number of MFEv5 driver. ++#define MAGIC_MMFE ('m') ++//! Use to Query version number of user interface. ++#define IOCTL_MMFE_VERSION _IOWR(MAGIC_MMFE, 0,unsigned int) ++//! Use to set parameters out of streaming. ++#define IOCTL_MMFE_S_PARM _IOWR(MAGIC_MMFE, 1,mmfe_parm) ++//! Use to get parameters any time. ++#define IOCTL_MMFE_G_PARM _IOWR(MAGIC_MMFE, 2,mmfe_parm) ++//! Use to transit the state to streaming-on. ++#define IOCTL_MMFE_STREAMON _IO(MAGIC_MMFE, 3) ++//! Use to transit the state to streaming-off. ++#define IOCTL_MMFE_STREAMOFF _IO(MAGIC_MMFE, 4) ++//! Use to set control during streaming. ++#define IOCTL_MMFE_S_CTRL _IOWR(MAGIC_MMFE, 5,mmfe_ctrl) ++//! Use to get control during streaming. ++#define IOCTL_MMFE_G_CTRL _IOWR(MAGIC_MMFE, 6,mmfe_ctrl) ++//! Use to encode a picture during streaming. ++#define IOCTL_MMFE_S_PICT _IOWR(MAGIC_MMFE, 7,mmfe_buff) ++//! Use to acquire the output bits of last coded picture. ++#define IOCTL_MMFE_G_BITS _IOWR(MAGIC_MMFE, 8,mmfe_buff) ++//! Use to encode a picture and acquire the output at the same time. ++#define IOCTL_MMFE_ENCODE _IOWR(MAGIC_MMFE, 9,mmfe_buff[2]) ++//! Use to put user data. ++#define IOCTL_MMFE_S_DATA _IOWR(MAGIC_MMFE,10,mmfe_buff) ++ ++#endif//_MDRV_MMFE_IO_H_ ++//! @} ++ +diff --git a/drivers/sstar/include/mdrv_mmfe_st.h b/drivers/sstar/include/mdrv_mmfe_st.h +new file mode 100755 +index 000000000000..b87958a1bc05 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_mmfe_st.h +@@ -0,0 +1,287 @@ ++/* ++* mdrv_mmfe_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_MMFE_ST_H_ ++#define _MDRV_MMFE_ST_H_ ++ ++#define MMFEIF_MAJ 1 //!< major version: Major number of driver-I/F version. ++#define MMFEIF_MIN 2 //!< minor version: Minor number of driver-I/F version. ++#define MMFEIF_EXT 1 //!< extended code: Extended number of version. It should increase when "mdrv_mmfe_io.h/mdrv_mmfe_st.h" changed. ++ ++//! User Interface version number. ++#define MMFEIF_VERSION_ID ((MMFEIF_MAJ<<22)|(MMFEIF_MIN<<12)|(MMFEIF_EXT)) ++//! Acquire version number. ++#define MMFEIF_GET_VER(v) (((v)>>12)) ++//! Acquire major version number. ++#define MMFEIF_GET_MJR(v) (((v)>>22)&0x3FF) ++//! Acquire minor version number. ++#define MMFEIF_GET_MNR(v) (((v)>>12)&0x3FF) ++//! Acquire extended number. ++#define MMFEIF_GET_EXT(v) (((v)>> 0)&0xFFF) ++ ++//! mmfe_pixfmt indicates pixels formats ++enum mmfe_pixfmt { ++ MMFE_PIXFMT_NV12=0, //!< pixel format NV12. ++ MMFE_PIXFMT_NV21, //!< pixel format NV21. ++ MMFE_PIXFMT_YUYV, //!< pixel format YUYV. ++ MMFE_PIXFMT_YVYU, //!< pixel format YVYU. ++}; ++ ++//! mmfe_subpel indicates interpolation granularity ++enum mmfe_subpel ++{ ++ MMFE_SUBPEL_INT=0, //!< subpel integral. ++ MMFE_SUBPEL_HALF, //!< subpel half. ++ MMFE_SUBPEL_QUATER, //!< subpel quater. ++}; ++ ++#define MMFE_MVBLK_4x4 (1<<0) //!< bit-field of 4x4 block ++#define MMFE_MVBLK_8x4 (1<<1) //!< bit-field of 8x4 block ++#define MMFE_MVBLK_4x8 (1<<2) //!< bit-field of 4x8 block ++#define MMFE_MVBLK_8x8 (1<<3) //!< bit-field of 8x8 block ++#define MMFE_MVBLK_16x8 (1<<4) //!< bit-field of 16x8 block ++#define MMFE_MVBLK_8x16 (1<<5) //!< bit-field of 8x16 block ++#define MMFE_MVBLK_16x16 (1<<6) //!< bit-field of 16x16 block ++#define MMFE_MVBLK_SKIP (1<<7) //!< bit-field of skip ++#define MMFE_AVC_PROFILE_BP 66 //!< H.264 Base Line Profile ++#define MMFE_AVC_PROFILE_MP 77 //!< H.264 Main Profile ++#define MMFE_AVC_LEVEL_3 30 //!< H.264 Level-3.0 ++#define MMFE_AVC_LEVEL_31 31 //!< H.264 Level-3.1 ++#define MMFE_AVC_LEVEL_32 32 //!< H.264 Level-3.2 ++#define MMFE_AVC_LEVEL_4 40 //!< H.264 Level-4.0 ++ ++//! mmfe_parm is used to apply/query configs out of streaming period. ++typedef union mmfe_parm ++{ ++ //! indicating parameter type. ++ enum mmfe_parm_e ++ { ++ MMFE_PARM_IDX = 0, //!< parameters of streamid: query stream-id. ++ MMFE_PARM_RES, //!< parameters of resource: including image's resolution and format ++ MMFE_PARM_FPS, //!< parameters of fps: fraction of framerate. ++ MMFE_PARM_GOP, //!< parameters of gop: ip frame period. ++ MMFE_PARM_BPS, //!< parameters of bps: bit per second. ++ MMFE_PARM_MOT, //!< parameters of motion: interpolation granularity, mv-partition. ++ MMFE_PARM_AVC, //!< parameters of avc: codec settings. ++ MMFE_PARM_VUI, //!< parameters of vui: vui params. ++ MMFE_PARM_LTR, //!< parameters of ltr: long term reference. ++ } type; //!< indicating which kind of mmfe_parm is. ++ ++ //! set res parameter out of streaming. ++ struct mmfe_parm_idx ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_IDX. ++ int i_stream; //!< stream-id. ++ } idx; ++ ++ //! set res parameter out of streaming. ++ struct mmfe_parm_res ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_RES. ++ int i_pict_w; //!< picture width. ++ int i_pict_h; //!< picture height. ++ enum mmfe_pixfmt i_pixfmt; //!< pixel format. ++ int i_outlen; //!< output length: '<0' mmap-mode, '>=0' user-mode. ++ int i_flags; //!< flags. ++#define STREAM_ID_DEFAULT 0xFFFF ++ int i_strid; //!< stream id, use STREAM_ID_DEFAULT as older naming ++ } res; //!< used to set resource parameters. ++ ++ //! set fps parameter out of streaming. ++ struct mmfe_parm_fps ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_FPS. ++ int i_num; //!< numerator of fps. ++ int i_den; //!< denominator of fps. ++ } fps; //!< used to set fraction of frame rate. ++ ++ //! set mot parameter out of streaming. ++ struct mmfe_parm_mot ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_MOT. ++ int i_dmv_x; //!< x-dir dmv. ++ int i_dmv_y; //!< y-dir dmv. ++ enum mmfe_subpel i_subpel; //!< interpolation granularity. ++ unsigned int i_mvblks[2]; //!< mv-partitions. ++ } mot; //!< used to set motion configuration. ++ ++ //! set gop parameter out of streaming. ++ struct mmfe_parm_gop ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_GOP. ++ int i_pframes; //!< p-frames count per i-frame ++ int i_bframes; //!< b-frames count per i/p-frame ++ } gop; //!< used to set gop structure. ++ ++ //! set bps parameter out of streaming. ++ struct mmfe_parm_bps ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_BPS. ++ int i_method; //!< rate-control method. ++ int i_ref_qp; //!< ref. QP. ++ int i_bps; //!< bitrate. ++ } bps; //!< used to set bit rate controller. ++ ++ //! set avc parameter out of streaming. ++ struct mmfe_parm_avc ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_AVC. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_num_ref_frames; //!< ref.frames count. ++ unsigned char i_poc_type; //!< poc_type: support 0,2. ++ unsigned char b_cabac; //!< entropy: cabac/cavlc. ++ unsigned char b_constrained_intra_pred; //!< contrained intra pred. ++ unsigned char b_deblock_filter_control; //!< deblock filter control. ++ unsigned char i_disable_deblocking_idc; //!< disable deblocking idc. ++ signed char i_alpha_c0_offset; //!< offset alpha div2. ++ signed char i_beta_offset; //!< offset beta div2. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ } avc; //!< used to set codec configuration. ++ ++ //! set avc parameter out of streaming. ++ struct mmfe_parm_vui ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_VUI. ++ int b_video_full_range; ++ int b_timing_info_pres; ++ } vui; //!< used to set codec configuration. ++ ++ //! set ltr parameter out of streaming. ++ struct mmfe_parm_ltr ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_LTR. ++ int b_long_term_reference; //!< toggle ltr mode ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set ltr configuration. ++ ++ unsigned char byte[64]; //!< dummy bytes ++ ++} mmfe_parm; ++ ++//! mmfe_ctrl is used to apply/query control configs during streaming period. ++typedef union mmfe_ctrl ++{ ++ //! indicating control type. ++ enum mmfe_ctrl_e ++ { ++ MMFE_CTRL_SEQ = 0, //!< control of sequence: includes resolution, pixel format and frame-rate. ++ MMFE_CTRL_AVC, //!< control of avc codec settings. ++ MMFE_CTRL_ROI, //!< control of roi setting changing. ++ MMFE_CTRL_SPL, //!< control of slice spliting. ++ MMFE_CTRL_LTR, //!< control of long term reference. ++ } type; //!< indicating which kind of mmfe_ctrl is. ++ ++ //! set seq parameter during streaming. ++ struct mmfe_ctrl_seq ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_SEQ. ++ enum mmfe_pixfmt i_pixfmt; //!< pixel-format ++ short i_pixelw; //!< pixels in width ++ short i_pixelh; //!< pixels in height ++ short n_fps; //!< numerator of frame-rate ++ short d_fps; //!< denominator of frame-rate ++ } seq; //!< used to start new sequence. ++ ++ //! set avc parameter during streaming. ++ struct mmfe_ctrl_avc ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_AVC. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_num_ref_frames; //!< ref.frames count. ++ unsigned char i_poc_type; //!< poc_type: support 0,2. ++ unsigned char b_cabac; //!< entropy: cabac/cavlc. ++ unsigned char b_constrained_intra_pred; //!< Constrained intra pred. ++ unsigned char b_deblock_filter_control; //!< deblock filter control. ++ unsigned char i_disable_deblocking_idc; //!< disable deblocking idc. ++ signed char i_alpha_c0_offset; //!< offset alpha div2. ++ signed char i_beta_offset; //!< offset beta div2. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ } avc; //!< used to set avc codec setting. ++ ++ //! set roi parameter during streaming. ++ struct mmfe_ctrl_roi ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_ROI. ++ short i_index; //!< roi index. ++ short i_dqp; //!< roi delta-qp: 0-disable roi, negative value. ++ unsigned short i_mbx; //!< roi rectangle position-X. ++ unsigned short i_mby; //!< roi rectangle position-Y. ++ unsigned short i_mbw; //!< roi rectangle-W. ++ unsigned short i_mbh; //!< roi rectangle-H. ++ } roi; //!< used to set roi region and dqp. ++ ++ //! set spl parameter during streaming. ++ struct mmfe_ctrl_spl ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_SPL. ++ int i_rows; //!< slice split by mb-rows. ++ int i_bits; //!< slice split by bitcnt. ++ } spl; //!< used to set slice splitting. ++ ++ //! set ltr parameter during streaming. ++ struct mmfe_ctrl_ltr ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_LTR. ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set long term reference. ++ ++ unsigned char byte[64]; //!< dummy bytes ++} mmfe_ctrl; ++ ++#define MMFE_FLAGS_IDR (1<< 0) //!< request IDR. ++#define MMFE_FLAGS_DISPOSABLE (1<< 1) //!< request unref-pic. ++#define MMFE_FLAGS_NIGHT_MODE (1<< 2) //!< night mode. ++#define MMFE_FLAGS_LTR_PFRAME (1<< 4) //!< LTR P-frame flag. ++#define MMFE_FLAGS_SOP (1<<30) //!< start of picture. ++#define MMFE_FLAGS_EOP (1<<31) //!< end of picture. ++#define MMFE_MEMORY_USER (0) //!< user mode. (pass pointer) ++#define MMFE_MEMORY_MMAP (1) //!< mmap mode. (pass physic address) ++ ++//! mmfe_buff is used to exchange video/obits buffer between user and driver during streaming period. ++typedef struct mmfe_buff ++{ ++ int i_index; //!< index of buffer: '-1' invalid, '>=0' valid. ++ int i_flags; //!< flags for request/reports. ++ short i_memory; //!< memory mode of user/mmap. ++ short i_width; //!< pixels in width. (if buffer is image) ++ short i_height; //!< pixels in height. (if buffer is image) ++ short i_stride; //!< pixels in stride. (if buffer is image) ' ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_MSYS_IO_H_ ++#define _MDRV_MSYS_IO_H_ ++ ++#define MSYS_IOCTL_MAGIC 'S' ++ ++#define IOCTL_MSYS_FIND_DMEM_BY_NAME _IO(MSYS_IOCTL_MAGIC, 0x0F) ++#define IOCTL_MSYS_REQUEST_DMEM _IO(MSYS_IOCTL_MAGIC, 0x10) ++#define IOCTL_MSYS_RELEASE_DMEM _IO(MSYS_IOCTL_MAGIC, 0x11) ++#define IOCTL_MSYS_FLUSH_CACHE _IO(MSYS_IOCTL_MAGIC, 0x12) ++#define IOCTL_MSYS_PHYS_TO_MIU _IO(MSYS_IOCTL_MAGIC, 0x13) ++#define IOCTL_MSYS_MIU_TO_PHYS _IO(MSYS_IOCTL_MAGIC, 0x14) ++#define IOCTL_MSYS_GET_RIU_MAP _IO(MSYS_IOCTL_MAGIC, 0x15) ++#define IOCTL_MSYS_FIX_DMEM _IO(MSYS_IOCTL_MAGIC, 0x16) ++#define IOCTL_MSYS_UNFIX_DMEM _IO(MSYS_IOCTL_MAGIC, 0x17) ++#define IOCTL_MSYS_MIU_PROTECT _IO(MSYS_IOCTL_MAGIC, 0x18) ++#define IOCTL_MSYS_USER_TO_PHYSICAL _IO(MSYS_IOCTL_MAGIC, 0x19) ++#define IOCTL_MSYS_GET_SYSP_STRING _IO(MSYS_IOCTL_MAGIC, 0x20) ++#define IOCTL_MSYS_GET_DATAP_STRING _IO(MSYS_IOCTL_MAGIC, 0x22) ++#define IOCTL_MSYS_GET_PROPERTY_PATH _IO(MSYS_IOCTL_MAGIC, 0x23) ++#define IOCTL_MSYS_SET_PROPERTY_PATH _IO(MSYS_IOCTL_MAGIC, 0x24) ++#define IOCTL_MSYS_PRINT_PIU_TIMER_TICKS _IO(MSYS_IOCTL_MAGIC, 0x30) ++#define IOCTL_MSYS_GET_US_TICKS _IO(MSYS_IOCTL_MAGIC, 0x31) ++#define IOCTL_MSYS_GET_UDID _IO(MSYS_IOCTL_MAGIC, 0x32) ++#define IOCTL_MSYS_BENCH_MEMORY _IO(MSYS_IOCTL_MAGIC, 0x63) ++#define IOCTL_MSYS_RESET_TO_UBOOT _IO(MSYS_IOCTL_MAGIC, 0x77) ++#define IOCTL_MSYS_READ_PM_TSENSOR _IO(MSYS_IOCTL_MAGIC, 0x78) ++ ++#define IOCTL_MSYS_REQUEST_PROC_DEVICE _IO(MSYS_IOCTL_MAGIC, 0x86) ++#define IOCTL_MSYS_RELEASE_PROC_DEVICE _IO(MSYS_IOCTL_MAGIC, 0x87) ++#define IOCTL_MSYS_REQUEST_PROC_ATTRIBUTE _IO(MSYS_IOCTL_MAGIC, 0x88) ++#define IOCTL_MSYS_RELEASE_PROC_ATTRIBUTE _IO(MSYS_IOCTL_MAGIC, 0x89) ++#define IOCTL_MSYS_FLUSH_MEMORY _IO(MSYS_IOCTL_MAGIC, 0x90) ++//#define IOCTL_MSYS_ADMA _IO(MSYS_IOCTL_MAGIC, 0x91) ++//#define IOCTL_MSYS_BDMA _IO(MSYS_IOCTL_MAGIC, 0x92) ++ ++#define IOCTL_MSYS_REQUEST_FREQUENCY _IO(MSYS_IOCTL_MAGIC, 0x93) ++#define IOCTL_MSYS_GET_CHIPVERSION _IO(MSYS_IOCTL_MAGIC, 0x94) ++ ++#define IOCTL_SYS_MAXNR 0xFF ++ ++#endif +diff --git a/drivers/sstar/include/mdrv_msys_io_st.h b/drivers/sstar/include/mdrv_msys_io_st.h +new file mode 100755 +index 000000000000..a82ea0376381 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_msys_io_st.h +@@ -0,0 +1,210 @@ ++/* ++* mdrv_msys_io_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_MSYS_IO_ST_H_ ++#define _MDRV_MSYS_IO_ST_H_ ++ ++/*******************************************************/ ++#define IOCTL_MSYS_VERSION 0x0100 ++/*******************************************************/ ++ ++#define PAD_CLOCK_OUT (GPIO_NR+1) ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ char name[16]; ++ unsigned int length; //32 bit ++ unsigned long long phys; //64 bit ++ unsigned long long kvirt; //Kernel Virtual Address 64 bit ++ unsigned int option; //reserved ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_DMEM_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_DUMMY_INFO; ++typedef struct ++{ ++ unsigned int IRQNumber; //reserved ++ void* action; ++ unsigned long long timeStart; ++ unsigned long long timeEnd; ++} __attribute__ ((__packed__)) MSYS_IRQ_INFO; ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned long long addr; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_ADDR_TRANSLATION_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned long long addr; ++ unsigned int size; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_MMIO_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned long long phys; //64 bit ++ unsigned int length; //32 bit ++ unsigned char id[16]; ++ unsigned int r_protect; ++ unsigned int w_protect; ++ unsigned int inv_protect; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_MIU_PROTECT_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned char str[32]; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_STRING_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned int temp; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_TEMP_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned long long udid; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_UDID_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ unsigned int chipVersion; ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_CHIPVER_INFO; ++ ++typedef struct ++{ ++ unsigned int VerChk_Version; ++ char name[16]; ++ unsigned int length; //32 bit ++ unsigned long long kphy_src; //Kernel Virtual Address src 64 bit ++ unsigned long long kphy_des; //Kernel Virtual Address des64 bit ++ unsigned int VerChk_Size; ++} __attribute__ ((__packed__)) MSYS_DMA_INFO; ++ ++typedef enum ++{ ++ FREQ_6MHZ = 0, ++ FREQ_12MHZ = 1, ++ FREQ_24MHZ = 2, ++ FREQ_27MHZ = 3, ++ FREQ_36MHZ = 4, ++ FREQ_37_5MHZ = 5, ++ FREQ_54MHZ = 6, ++ FREQ_75MHZ = 7, ++}MSYS_FREQ_TYPE; ++ ++typedef enum ++{ ++ U01 = 0, ++ U02 = 1, ++} CHIP_VERSION; ++ ++typedef struct ++{ ++ unsigned int padnum; ++ unsigned int freq; ++ unsigned char bEnable; ++ unsigned char bInvert; ++} __attribute__ ((__packed__)) MSYS_FREQGEN_INFO; ++ ++typedef struct ++{ ++ char name[128]; ++ unsigned long size; ++ void *handle; //don't set this ++ void *parent; ++ void *data; ++} MSYS_PROC_DEVICE; ++ ++typedef struct ++{ ++ void *handle; ++ char name[128]; ++ unsigned int type; ++ unsigned int offset; ++} MSYS_PROC_ATTRIBUTE; ++ ++typedef enum ++{ ++ MSYS_PROC_ATTR_CHAR, ++ MSYS_PROC_ATTR_UINT, ++ MSYS_PROC_ATTR_INT, //also for enum, bool ++ MSYS_PROC_ATTR_XINT, ++ MSYS_PROC_ATTR_ULONG, ++ MSYS_PROC_ATTR_LONG, ++ MSYS_PROC_ATTR_XLONG, ++ MSYS_PROC_ATTR_ULLONG, ++ MSYS_PROC_ATTR_LLONG, ++ MSYS_PROC_ATTR_XLLONG, ++ MSYS_PROC_ATTR_STRING, ++} MSYS_PROC_ATTR_ENUM; ++ ++typedef struct ++{ ++ unsigned long long phyaddr_src; // MIU address of source ++ unsigned long long phyaddr_dst; // MIU address of destination ++ unsigned int lineofst_src; // line-offset of source, set 0 to disable line offset ++ unsigned int lineofst_dst; // line-offset of destination, set 0 to disable line offset ++ unsigned int width_src; // width of source, set 0 to disable line offset ++ unsigned int width_dst; // width of destination, set 0 to disable line offset ++ unsigned int length; // total size (bytes) ++} MSYS_DMA_BLIT; ++ ++#if defined(CONFIG_MS_BDMA_LINE_OFFSET_ON) ++typedef struct ++{ ++ unsigned long long phyaddr; // MIU address of source ++ unsigned int length; // total size (bytes) ++ //unsigned int lineofst_src; // line-offset of source, set 0 to disable line offset ++ unsigned int lineofst_dst; // line-offset of destination, set 0 to disable line offset ++ //unsigned int width_src; // width of source, set 0 to disable line offset ++ unsigned int width_dst; // width of destination, set 0 to disable line offset ++ unsigned int pattern; // pattern (4-byte) ++} MSYS_DMA_FILL_BILT; ++#endif ++ ++typedef struct ++{ ++ unsigned long long phyaddr; // MIU address of source ++ unsigned int length; // total size (bytes) ++ unsigned int pattern; // pattern (4-byte) ++} MSYS_DMA_FILL; ++ ++typedef struct ++{ ++ unsigned long long phyaddr_src; // MIU address of source ++ unsigned long long phyaddr_dst; // MIU address of destination ++ unsigned int length; // total size (bytes) ++}MSYS_DMA_COPY; ++#endif +diff --git a/drivers/sstar/include/mdrv_mvhe_io.h b/drivers/sstar/include/mdrv_mvhe_io.h +new file mode 100755 +index 000000000000..60510abef3f8 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_mvhe_io.h +@@ -0,0 +1,57 @@ ++/* ++* mdrv_mvhe_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDIV_MVHE_IO_H_ ++#define _MDIV_MVHE_IO_H_ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++#include ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Magic Number of MFEv5 driver. ++#define MAGIC_MVHE ('v') ++//! Use to Query version number of user interface. ++#define IOCTL_MVHE_VERSION _IOWR(MAGIC_MVHE, 0,unsigned int) ++//! Use to set parameters out of streaming. ++#define IOCTL_MVHE_S_PARM _IOWR(MAGIC_MVHE, 1,mvhe_parm) ++//! Use to get parameters any time. ++#define IOCTL_MVHE_G_PARM _IOWR(MAGIC_MVHE, 2,mvhe_parm) ++//! Use to transit the state to streaming-on. ++#define IOCTL_MVHE_STREAMON _IO(MAGIC_MVHE, 3) ++//! Use to transit the state to streaming-off. ++#define IOCTL_MVHE_STREAMOFF _IO(MAGIC_MVHE, 4) ++//! Use to set control during streaming. ++#define IOCTL_MVHE_S_CTRL _IOWR(MAGIC_MVHE, 5,mvhe_ctrl) ++//! Use to get control during streaming. ++#define IOCTL_MVHE_G_CTRL _IOWR(MAGIC_MVHE, 6,mvhe_ctrl) ++//! Use to encode a picture during streaming. ++#define IOCTL_MVHE_S_PICT _IOWR(MAGIC_MVHE, 7,mvhe_buff) ++//! Use to acquire the output bits of last coded picture. ++#define IOCTL_MVHE_G_BITS _IOWR(MAGIC_MVHE, 8,mvhe_buff) ++//! Use to encode a picture and acquire the output at the same time. ++#define IOCTL_MVHE_ENCODE _IOWR(MAGIC_MVHE, 9,mvhe_buff[2]) ++//! Use to put user data. ++#define IOCTL_MVHE_S_DATA _IOWR(MAGIC_MVHE,10,mvhe_buff) ++ ++#endif//_MDIV_MVHE_IO_H_ ++//! @} ++ +diff --git a/drivers/sstar/include/mdrv_mvhe_st.h b/drivers/sstar/include/mdrv_mvhe_st.h +new file mode 100755 +index 000000000000..db648986684d +--- /dev/null ++++ b/drivers/sstar/include/mdrv_mvhe_st.h +@@ -0,0 +1,310 @@ ++/* ++* mdrv_mvhe_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_MVHE_ST_H_ ++#define _MDRV_MVHE_ST_H_ ++ ++#define MVHEIF_MAJ 1 //!< major version: Major number of driver-I/F version. ++#define MVHEIF_MIN 2 //!< minor version: Minor number of driver-I/F version. ++#define MVHEIF_EXT 1 //!< extended code: Extended number of version. It should increase when "mdrv_mvhe_io.h/mdrv_mvhe_st.h" changed. ++ ++//! User Interface version number. ++#define MVHEIF_VERSION_ID ((MVHEIF_MAJ<<22)|(MVHEIF_MIN<<12)|(MVHEIF_EXT)) ++//! Acquire version number. ++#define MVHEIF_GET_VER(v) (((v)>>12)) ++//! Acquire major version number. ++#define MVHEIF_GET_MJR(v) (((v)>>22)&0x3FF) ++//! Acquire minor version number. ++#define MVHEIF_GET_MNR(v) (((v)>>12)&0x3FF) ++//! Acquire extended number. ++#define MVHEIF_GET_EXT(v) (((v)>> 0)&0xFFF) ++ ++//! mvhe_pixfmt indicates pixels formats ++enum mvhe_pixfmt ++{ ++ MVHE_PIXFMT_NV12=0, //!< pixel format NV12. ++ MVHE_PIXFMT_NV21, //!< pixel format NV21. ++ MVHE_PIXFMT_YUYV, //!< pixel format YUYV. ++ MVHE_PIXFMT_YVYU, //!< pixel format YVYU. ++}; ++ ++#define MVHE_HEVC_PROFILE_MAIN 1 //!< hevc main profile ++#define MVHE_HEVC_PROFILE_MAIN10 2 //!< hevc main10 profile ++#define MVHE_HEVC_LEVEL_1 30 //!< hevc level 1.0 ++#define MVHE_HEVC_LEVEL_2 60 //!< hevc level 2.0 ++#define MVHE_HEVC_LEVEL_2_1 63 //!< hevc level 2.1 ++#define MVHE_HEVC_LEVEL_3 90 //!< hevc level 3.0 ++#define MVHE_HEVC_LEVEL_3_1 93 //!< hevc level 3.1 ++#define MVHE_HEVC_LEVEL_4 120 //!< hevc level 4.0 ++#define MVHE_HEVC_LEVEL_4_1 124 //!< hevc level 4.1 ++#define MVHE_HEVC_LEVEL_5 150 //!< hevc level 5.0 ++#define MVHE_HEVC_LEVEL_5_1 153 //!< hevc level 5.1 ++#define MVHE_HEVC_LEVEL_5_2 156 //!< hevc level 5.2 ++#define MVHE_HEVC_LEVEL_6 180 //!< hevc level 6.0 ++#define MVHE_HEVC_LEVEL_6_1 183 //!< hevc level 6.1 ++#define MVHE_HEVC_LEVEL_6_2 186 //!< hevc level 6.2 ++#define MVHE_FLAGS_CMPRY (1<< 0) ++#define MVHE_FLAGS_COMPR (MVHE_FLAGS_CMPRY) ++ ++//! mvhe_parm is used to apply/query configs out of streaming period. ++typedef union mvhe_parm ++{ ++ //! mvhe_parm_e indicates parameter type. ++ enum mvhe_parm_e ++ { ++ MVHE_PARM_IDX=0, //!< parameters of streamid: query stream-id. ++ MVHE_PARM_RES, //!< parameters of resource: including image's resolution and format ++ MVHE_PARM_FPS, //!< parameters of fps: fraction of framerate. ++ MVHE_PARM_GOP, //!< parameters of gop: ip frame period. ++ MVHE_PARM_BPS, //!< parameters of bps: bit per second. ++ MVHE_PARM_HEVC, //!< parameters of hevc: codec settings. ++ MVHE_PARM_VUI, //!< parameters of vui: vui params. ++ MVHE_PARM_LTR, //!< parameters of ltr: long term reference. ++ MVHE_PARM_PEN, //!< parameters of pen: penalty params. ++ } type; //!< indicating which kind of mvhe_parm is. ++ ++ //! get ver parameter out of streaming. ++ struct mvhe_parm_idx ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MMFE_PARM_IDX. ++ unsigned int i_stream; //!< stream-id. ++ } idx; //!< used to get version/id parameters. ++ ++ //! set res parameters out of streaming. ++ struct mvhe_parm_res ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_RES. ++ int i_pict_w; //!< picture width. ++ int i_pict_h; //!< picture height. ++ enum mvhe_pixfmt i_pixfmt; //!< pixel format. ++ int i_outlen; //!< output length: '<0' mmap-out, '=0' default, '>0' aligned to 512K ++ int i_flags; //!< flags. ++#define STREAM_ID_DEFAULT 0xFFFF ++ int i_strid; //!< stream id, use STREAM_ID_DEFAULT as older naming ++ } res; //!< used to set resource parameters. ++ ++ //! set fps parameters out of streaming. ++ struct mvhe_parm_fps ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_FPS. ++ int i_num; //!< numerator of fps. ++ int i_den; //!< denominator of fps. ++ } fps; //!< used to set fraction of frame rate. ++ ++ //! set gop parameters out of streaming. ++ struct mvhe_parm_gop ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_GOP. ++ int i_pframes; //!< p-frames count per i-frame. ++ int i_bframes; //!< b-frames count per i/p-frame. ++ } gop; //!< used to set gop structure. ++ ++ //! set bps parameters out of streaming. ++ struct mvhe_parm_bps ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_BPS. ++ int i_method; //!< rate-control method. ++ int i_ref_qp; //!< ref. QP. ++ int i_bps; //!< bitrate. ++ } bps; //!< used to set bit rate controller. ++ ++ //! set hevc parameters out of streaming. ++ struct mvhe_parm_hevc ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_HEVC. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_log2_max_cb_size; //!< max ctb size. ++ unsigned char i_log2_min_cb_size; //!< min ctb size. ++ unsigned char i_log2_max_tr_size; //!< max trb size. ++ unsigned char i_log2_min_tr_size; //!< min trb size. ++ unsigned char i_tr_depth_intra; //!< tr depth intra. ++ unsigned char i_tr_depth_inter; //!< tr depth inter. ++ unsigned char b_scaling_list_enable; //!< scaling list enable. ++ unsigned char b_ctu_qp_delta_enable; //!< ctu dqp enable. ++ unsigned char b_sao_enable; //!< sao enable. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ unsigned char b_strong_intra_smoothing; //!< strong intra smoothing. ++ unsigned char b_constrained_intra_pred; //!< intra prediction constrained. ++ unsigned char b_deblocking_override_enable; //!< deblocking override enable. ++ unsigned char b_deblocking_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } hevc; //!< used to set codec configuration. ++ ++ //! set vui parameter out of streaming. ++ struct mvhe_parm_vui ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_VUI. ++ int b_video_full_range; ++ int b_timing_info_pres; ++ } vui; //!< used to set codec configuration. ++ ++ //! set ltr parameter out of streaming. ++ struct mvhe_parm_ltr ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_LTR. ++ int b_long_term_reference; //!< toggle ltr mode ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set ltr configuration. ++ ++ unsigned char byte[64]; //!< dummy bytes ++} mvhe_parm; ++ ++//! mvhe_ctrl is used to apply/query control configs during streaming period. ++typedef union mvhe_ctrl ++{ ++ //! mvhe_ctrl_e indicates control type. ++ enum mvhe_ctrl_e ++ { ++ MVHE_CTRL_SEQ=0,//!< control of sequence: includes resolution, pixel format and frame-rate. ++ MVHE_CTRL_HEVC, //!< control of hevc codec settings. ++ MVHE_CTRL_ROI, //!< control of roi setting changing. ++ MVHE_CTRL_SPL, //!< control of slice spliting. ++ MVHE_CTRL_DBK, //!< control of deblocking. ++ MVHE_CTRL_BAC, //!< control of cabac_init. ++ MVHE_CTRL_LTR, //!< control of long term reference. ++ } type; //!< indicating which kind of mvhe_ctrl is. ++ ++ //! set seq control during streaming. ++ struct mvhe_ctrl_seq ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_SEQ. ++ enum mvhe_pixfmt i_pixfmt; //!< pixel-format ++ short i_pixelw; //!< pixels in width. ++ short i_pixelh; //!< pixels in height. ++ short n_fps; //!< numerator of frame-rate. ++ short d_fps; //!< denominator of frame-rate. ++ } seq; //!< used to start new sequence. ++ ++ //! set hevc control during streaming. ++ struct mvhe_ctrl_hevc ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_SEQ. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_log2_max_cb_size; //!< max ctb size. ++ unsigned char i_log2_min_cb_size; //!< min ctb size. ++ unsigned char i_log2_max_tr_size; //!< max trb size. ++ unsigned char i_log2_min_tr_size; //!< min trb size. ++ unsigned char i_tr_depth_intra; //!< tr depth intra. ++ unsigned char i_tr_depth_inter; //!< tr depth inter. ++ unsigned char b_scaling_list_enable; //!< scaling list enable. ++ unsigned char b_ctu_qp_delta_enable; //!< ctu dqp enable. ++ unsigned char b_sao_enable; //!< sao enable. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ unsigned char b_strong_intra_smoothing; //!< strong intra smoothing. ++ unsigned char b_constrained_intra_pred; //!< intra prediction constrained. ++ unsigned char b_deblocking_override_enable; //!< deblocking override enable. ++ unsigned char b_deblocking_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } hevc; //!< used to set hevc codec setting. ++ ++ //! set roi control during streaming. ++ struct mvhe_ctrl_roi ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_ROI. ++ short i_index; //!< roi index. ++ short i_dqp; //!< dqp: -15~0, =0: disable, !=0: enable. ++ unsigned short i_cbx; //!< roi region posotion-X. (in CTB unit) ++ unsigned short i_cby; //!< roi region posotion-Y. (in CTB unit) ++ unsigned short i_cbw; //!< roi region rectangle-W. (in CTB unit) ++ unsigned short i_cbh; //!< roi region rectangle-H. (in CTB unit) ++ } roi; //!< used to set roi region and dqp. ++ ++ //! set spl control during streaming. ++ struct mvhe_ctrl_spl ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_SPL. ++ int i_rows; //!< split slice by cb-rows. ++ int i_bits; //!< split slice by cb-bits. ++ } spl; //!< used to set slice splitting. ++ ++ //! set dbk control during streaming. ++ struct mvhe_ctrl_dbk { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_DBK. ++ unsigned char b_override; //!< override deblocking setting. ++ unsigned char b_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } dbk; //!< used to set deblocking splitting. ++ ++ //! set bac control during streaming. ++ struct mvhe_ctrl_bac ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_BAC. ++ int b_init; //!< cabac_init_flag: 0,1 ++ } bac; //!< used to set cabac_init. ++ ++ //! set ltr parameter during streaming. ++ struct mvhe_ctrl_ltr ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_LTR. ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set long term reference. ++ ++ unsigned char byte[64]; //!< dummy bytes ++} mvhe_ctrl; ++ ++#define MVHE_FLAGS_IDR (1<< 0) //!< request IDR. ++#define MVHE_FLAGS_DISPOSABLE (1<< 1) //!< request unref-pic. ++#define MVHE_FLAGS_NIGHT_MODE (1<< 2) //!< night mode. ++#define MVHE_FLAGS_LTR_PFRAME (1<< 4) //!< LTR P-frame flag. ++#define MVHE_FLAGS_SOP (1<<30) //!< start of picture. ++#define MVHE_FLAGS_EOP (1<<31) //!< end of picture. ++#define MVHE_MEMORY_USER (0) //!< user mode. (pass pointer) ++#define MVHE_MEMORY_MMAP (1) //!< mmap mode. (pass physic address) ++ ++//! mvhe_buff is used to exchange video/obits buffer between user and driver during streaming period. ++typedef struct mvhe_buff ++{ ++ int i_index; //!< index of buffer: '-1' invalid, '>=0' valid. ++ int i_flags; //!< flags for request/reports. ++ short i_memory; //!< memory mode of user/mmap. ++ short i_width; //!< pixels in width. (if buffer is image) ++ short i_height; //!< pixels in height. (if buffer is image) ++ short i_stride; //!< pixels in stride. (if buffer is image) ' ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_PADMUX_H__ ++#define __MDRV_PADMUX_H__ ++ ++int mdrv_padmux_active(void); ++int mdrv_padmux_getpad(int puse); ++int mdrv_padmux_getmode(int puse); ++ ++#endif // #ifndef __MDRV_PADMUX_H__ +diff --git a/drivers/sstar/include/mdrv_pnl_io.h b/drivers/sstar/include/mdrv_pnl_io.h +new file mode 100755 +index 000000000000..7c6932d171f1 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_pnl_io.h +@@ -0,0 +1,59 @@ ++/* ++* mdrv_pnl_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/** ++ * \defgroup pnl_group PNL driver ++ * @{ ++ */ ++#ifndef _MDRV_PNL_IO_H ++#define _MDRV_PNL_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++ ++ ++#define IOCTL_PNL_SET_TIMING_CONFIG_NR (0)///< The IOCTL NR definition,IOCTL_PNL_SET_TIMING_CONFIG ++#define IOCTL_PNL_SET_LPLL_CONFIG_NR (1)///< The IOCTL NR definition,IOCTL_PNL_SET_TIMING_CONFIG ++#define IOCLT_PNL_GET_VERSION_CONFIG_NR (2)///< The IOCTL NR definition, IOCTL_PNL_GET_VERSION_CONFIG ++#define IOCTL_PNL_MAX_NR (IOCLT_PNL_GET_VERSION_CONFIG_NR+1)///< The Max IOCTL NR for pnl driver ++ ++// use 'm' as magic number ++#define IOCTL_PNL_MAGIC ('8')///< The Type definition of IOCTL for pnl driver ++/** ++* Used to set Panel timing LPLL timing, use ST_IOCTL_HVSP_INPUT_CONFIG. ++*/ ++#define IOCTL_PNL_SET_TIMING_CONFIG _IO(IOCTL_PNL_MAGIC, IOCTL_PNL_SET_TIMING_CONFIG_NR) ++/** ++* Used to set LPLL timing, use ST_IOCTL_HVSP_INPUT_CONFIG. ++*/ ++#define IOCTL_PNL_SET_LPLL_CONFIG _IO(IOCTL_PNL_MAGIC, IOCTL_PNL_SET_LPLL_CONFIG_NR) ++ ++ ++/** ++* Used to get version, use ST_IOCTL_PNL_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_PNL_GET_VERSION_CONFIG _IO(IOCTL_PNL_MAGIC, IOCLT_PNL_GET_VERSION_CONFIG_NR) ++ ++#endif // ++/** @} */ // end of pnl_group +diff --git a/drivers/sstar/include/mdrv_pnl_io_st.h b/drivers/sstar/include/mdrv_pnl_io_st.h +new file mode 100755 +index 000000000000..9aa332a4a4b3 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_pnl_io_st.h +@@ -0,0 +1,83 @@ ++/* ++* mdrv_pnl_io_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup pnl_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_PNL_IO_ST_H ++#define _MDRV_PNL_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++ ++ ++ ++//============================================================================= ++// enum ++//============================================================================= ++#define IOCTL_PNL_VERSION 0x0100 ++ ++//============================================================================= ++// struct ++//============================================================================= ++/** ++* Used to setup the panel timing of pnl device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Vsync_St; ///< vsync start point ++ unsigned short u16Vsync_End;///< vsync end point ++ unsigned short u16Vde_St; ///< Vdata enable start point ++ unsigned short u16Vde_End; ///< Vdata enable end point ++ unsigned short u16Vfde_St; ///< V framecolor data enable start point ++ unsigned short u16Vfde_End; ///< V framecolor data enable end point ++ unsigned short u16Vtt; ///< V total ++ unsigned short u16Hsync_St; ///< hsync start point ++ unsigned short u16Hsync_End;///< hsync end point ++ unsigned short u16Hde_St; ///< Hdata enable start point ++ unsigned short u16Hde_End; ///< Hdata enable end point ++ unsigned short u16Hfde_St; ///< H framecolor data enable start point ++ unsigned short u16Hfde_End; ///< H framecolor data enable end point ++ unsigned short u16Htt; ///< H total ++ unsigned short u16VFreqx10; ///< FPS x10 ++ ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCLT_PNL_TIMING_CONFIG; ++ ++ ++/** ++* Used to get PNL drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_PNL_VERSION_CONFIG; ++//============================================================================= ++ ++//============================================================================= ++#endif // ++/** @} */ // end of pnl_group +diff --git a/drivers/sstar/include/mdrv_puse.h b/drivers/sstar/include/mdrv_puse.h +new file mode 100755 +index 000000000000..eaa2a5938d65 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_puse.h +@@ -0,0 +1,216 @@ ++/* ++* mdrv_puse.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_PUSE_H__ ++#define __MDRV_PUSE_H__ ++ ++/* ++ * Naming Rule: MDRV_PUSE__ ++ * ++ * define-value rule: Bit[16~31] for IP Group (e.g 0x00060000 for I2C ++ * Bit[8~15] for each IP in the group(e.g 0x00060000 for i2c0, ox00060100 for i2c1) ++ * Bit[0~7] for each PAD of a IP(e.g. 0x00060000 for i2c0_scl, 0x00060001 for i2c0_sda) ++ * ++ */ ++ ++// Don't need to specify pad usage by which driver ++#define MDRV_PUSE_NA 0x00000000 ++ ++// EMAC0 pad usage ++#define MDRV_PUSE_EMAC0_LED 0x00010000 ++// #define MDRV_PUSE_EMAC0_LED_GPIO_GREEN 0x00010001 ++// #define MDRV_PUSE_EMAC0_LED_GPIO_ORANGE 0x00010002 ++#define MDRV_PUSE_EMAC0_PHY_RESET 0x00010003 ++ ++// EMAC1 pad usage ++#define MDRV_PUSE_EMAC1_LED 0x00010100 ++// #define MDRV_PUSE_EMAC1_LED_GPIO_GREEN 0x00010101 ++// #define MDRV_PUSE_EMAC1_LED_GPIO_ORANGE 0x00010102 ++#define MDRV_PUSE_EMAC1_PHY_RESET 0x00010103 ++ ++// SDIO0 ++#define MDRV_PUSE_SDIO0_PWR 0x00020000 ++#define MDRV_PUSE_SDIO0_CDZ 0x00020001 ++#define MDRV_PUSE_SDIO0_CLK 0x00020002 ++#define MDRV_PUSE_SDIO0_CMD 0x00020003 ++#define MDRV_PUSE_SDIO0_D0 0x00020004 ++#define MDRV_PUSE_SDIO0_D1 0x00020005 ++#define MDRV_PUSE_SDIO0_D2 0x00020006 ++#define MDRV_PUSE_SDIO0_D3 0x00020007 ++ ++// SDIO1 ++#define MDRV_PUSE_SDIO1_PWR 0x00020100 ++#define MDRV_PUSE_SDIO1_CDZ 0x00020101 ++#define MDRV_PUSE_SDIO1_CLK 0x00020102 ++#define MDRV_PUSE_SDIO1_CMD 0x00020103 ++#define MDRV_PUSE_SDIO1_D0 0x00020104 ++#define MDRV_PUSE_SDIO1_D1 0x00020105 ++#define MDRV_PUSE_SDIO1_D2 0x00020106 ++#define MDRV_PUSE_SDIO1_D3 0x00020107 ++ ++// CPUFREQ ++#define MDRV_PUSE_CPUFREQ_VID0 0x00030000 ++#define MDRV_PUSE_CPUFREQ_VID1 0x00030001 ++ ++//IR ++#define MDRV_PUSE_IR 0x00040000 ++ ++// EJ-Tag ++#define MDRV_PUSE_EJ_TCK 0x00050000 ++#define MDRV_PUSE_EJ_TMS 0x00050001 ++#define MDRV_PUSE_EJ_TDO 0x00050002 ++#define MDRV_PUSE_EJ_TDI 0x00050003 ++ ++// I2C ++#define MDRV_PUSE_I2C0_SCL 0x00060000 ++#define MDRV_PUSE_I2C0_SDA 0x00060001 ++#define MDRV_PUSE_I2C1_SCL 0x00060100 ++#define MDRV_PUSE_I2C1_SDA 0x00060101 ++#define MDRV_PUSE_I2C1_DEV_RESET 0x00060102 ++#define MDRV_PUSE_I2C1_DEV_IRQ 0x00060103 ++#define MDRV_PUSE_I2C2_SCL 0x00060200 ++#define MDRV_PUSE_I2C2_SDA 0x00060201 ++#define MDRV_PUSE_I2C3_SCL 0x00060300 ++#define MDRV_PUSE_I2C3_SDA 0x00060301 ++#define MDRV_PUSE_I2C4_SCL 0x00060400 ++#define MDRV_PUSE_I2C4_SDA 0x00060401 ++#define MDRV_PUSE_I2C5_SCL 0x00060500 ++#define MDRV_PUSE_I2C5_SDA 0x00060501 ++#define MDRV_PUSE_I2CSW_SCL 0x00061000 ++#define MDRV_PUSE_I2CSW_SDA 0x00061001 ++ ++//I2 ++// UART0 ++#define MDRV_PUSE_UART0_RX 0x00070000 ++#define MDRV_PUSE_UART0_TX 0x00070001 ++//UART1 ++#define MDRV_PUSE_UART1_RX 0x00070010 ++#define MDRV_PUSE_UART1_TX 0x00070011 ++//UART2 ++#define MDRV_PUSE_UART2_RX 0x00070020 ++#define MDRV_PUSE_UART2_TX 0x00070021 ++//FUART ++#define MDRV_PUSE_FUART_RX 0x00070030 ++#define MDRV_PUSE_FUART_TX 0x00070031 ++#define MDRV_PUSE_FUART_CTS 0x00070032 ++#define MDRV_PUSE_FUART_RTS 0x00070033 ++ ++// PWM0 ++#define MDRV_PUSE_PWM0 0x00080000 ++#define MDRV_PUSE_PWM1 0x00080100 ++#define MDRV_PUSE_PWM2 0x00080200 ++#define MDRV_PUSE_PWM3 0x00080300 ++#define MDRV_PUSE_PWM4 0x00080400 ++#define MDRV_PUSE_PWM5 0x00080500 ++#define MDRV_PUSE_PWM6 0x00080600 ++#define MDRV_PUSE_PWM7 0x00080700 ++#define MDRV_PUSE_PWM8 0x00080800 ++#define MDRV_PUSE_PWM9 0x00080900 ++ ++ ++// DMIC ++#define MDRV_PUSE_DMIC_D1 0x00090000 ++#define MDRV_PUSE_DMIC_D0 0x00090001 ++#define MDRV_PUSE_DMIC_CLK 0x00090002 ++ ++// I2S ++#define MDRV_PUSE_I2S_WCK 0x000A0000 ++#define MDRV_PUSE_I2S_BCK 0x000A0001 ++#define MDRV_PUSE_I2S_SDI 0x000A0002 ++#define MDRV_PUSE_I2S_SDO 0x000A0003 ++ ++ ++// TTL / Tx Mipi ++#define MDRV_PUSE_TTL_DOUT00 0x000B0000 ++#define MDRV_PUSE_TTL_DOUT01 0x000B0001 ++#define MDRV_PUSE_TTL_DOUT02 0x000B0002 ++#define MDRV_PUSE_TTL_DOUT03 0x000B0003 ++#define MDRV_PUSE_TTL_DOUT04 0x000B0004 ++#define MDRV_PUSE_TTL_DOUT05 0x000B0005 ++#define MDRV_PUSE_TTL_DOUT06 0x000B0006 ++#define MDRV_PUSE_TTL_DOUT07 0x000B0007 ++#define MDRV_PUSE_TTL_DOUT08 0x000B0008 ++#define MDRV_PUSE_TTL_DOUT09 0x000B0009 ++#define MDRV_PUSE_TTL_DOUT10 0x000B000A ++#define MDRV_PUSE_TTL_DOUT11 0x000B000B ++#define MDRV_PUSE_TTL_DOUT12 0x000B000C ++#define MDRV_PUSE_TTL_DOUT13 0x000B000D ++#define MDRV_PUSE_TTL_DOUT14 0x000B000E ++#define MDRV_PUSE_TTL_DOUT15 0x000B000F ++#define MDRV_PUSE_TTL_DOUT16 0x000B0010 ++#define MDRV_PUSE_TTL_DOUT17 0x000B0011 ++#define MDRV_PUSE_TTL_DOUT18 0x000B0012 ++#define MDRV_PUSE_TTL_DOUT19 0x000B0013 ++#define MDRV_PUSE_TTL_DOUT20 0x000B0014 ++#define MDRV_PUSE_TTL_DOUT21 0x000B0015 ++#define MDRV_PUSE_TTL_DOUT22 0x000B0016 ++#define MDRV_PUSE_TTL_DOUT23 0x000B0017 ++#define MDRV_PUSE_TTL_DOUT24 0x000B0018 ++#define MDRV_PUSE_TTL_CLK 0x000B0019 ++#define MDRV_PUSE_TTL_HSYNC 0x000B001A ++#define MDRV_PUSE_TTL_VSYNC 0x000B001B ++#define MDRV_PUSE_TTL_DE 0x000B001C ++ ++#define MDRV_PUSE_TX_MIPI_P_CH0 0x000B0080 ++#define MDRV_PUSE_TX_MIPI_N_CH0 0x000B0081 ++#define MDRV_PUSE_TX_MIPI_P_CH1 0x000B0082 ++#define MDRV_PUSE_TX_MIPI_N_CH1 0x000B0083 ++#define MDRV_PUSE_TX_MIPI_P_CH2 0x000B0084 ++#define MDRV_PUSE_TX_MIPI_N_CH2 0x000B0085 ++#define MDRV_PUSE_TX_MIPI_P_CH3 0x000B0086 ++#define MDRV_PUSE_TX_MIPI_N_CH3 0x000B0087 ++#define MDRV_PUSE_TX_MIPI_P_CH4 0x000B0088 ++#define MDRV_PUSE_TX_MIPI_N_CH4 0x000B0089 ++ ++#define MDRV_PUSE_IDAC_HSYNC 0x000B0100 ++#define MDRV_PUSE_IDAC_VSYNC 0x000B0101 ++ ++// SPI0 ++#define MDRV_PUSE_SPI0_CZ 0x000C0000 ++#define MDRV_PUSE_SPI0_CK 0x000C0001 ++#define MDRV_PUSE_SPI0_DI 0x000C0002 ++#define MDRV_PUSE_SPI0_DO 0x000C0003 ++ ++// SAR ++#define MDRV_PUSE_SAR_GPIO0 0x000D0000 ++#define MDRV_PUSE_SAR_GPIO1 0x000D0100 ++ ++//usb host ++#define MDRV_PUSE_UTMI1_DM 0x000E0000 ++#define MDRV_PUSE_UTMI1_DP 0x000E0000 ++#define MDRV_PUSE_UTMI2_DM 0x000E0100 ++#define MDRV_PUSE_UTMI2_DP 0x000E0100 ++#define MDRV_PUSE_UTMI3_DM 0x000E0200 ++#define MDRV_PUSE_UTMI3_DP 0x000E0200 ++#define MDRV_PUSE_UTMI_POWER 0x000E1000 ++ ++// Audio ++#define MDRV_PUSE_AIO_AMP_PWR 0x000F0000 ++#define MDRV_PUSE_AIO_MCK 0x000F0001 ++ ++// EMAC RMII ++#define MDRV_PUSE_ETH_MDC 0x00100000 ++#define MDRV_PUSE_ETH_MDIO 0x00100001 ++#define MDRV_PUSE_ETH_COL 0x00100002 ++#define MDRV_PUSE_ETH_TXD1 0x00100003 ++#define MDRV_PUSE_ETH_TXD0 0x00100004 ++#define MDRV_PUSE_ETH_TX_EN 0x00100005 ++#define MDRV_PUSE_ETH_TX_CLK 0x00100006 ++#define MDRV_PUSE_ETH_RXD1 0x00100007 ++#define MDRV_PUSE_ETH_RXD0 0x00100008 ++ ++#endif // #define __MDRV_PUSE_H__ +diff --git a/drivers/sstar/include/mdrv_rqct_io.h b/drivers/sstar/include/mdrv_rqct_io.h +new file mode 100755 +index 000000000000..7c165861078f +--- /dev/null ++++ b/drivers/sstar/include/mdrv_rqct_io.h +@@ -0,0 +1,40 @@ ++/* ++* mdrv_rqct_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_RQCT_IO_H_ ++#define _MDRV_RQCT_IO_H_ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++#include ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Magic Number of RQCT. ++#define MAGIC_RQCT ('q') ++//! Use to Query version number of user interface. ++#define IOCTL_RQCT_VERSION _IOWR(MAGIC_RQCT, 0,unsigned int) ++//! Use to set rq-control during streaming. ++#define IOCTL_RQCT_S_CONF _IOWR(MAGIC_RQCT, 1,rqct_conf) ++//! Use to get rq-control during streaming. ++#define IOCTL_RQCT_G_CONF _IOWR(MAGIC_RQCT, 2,rqct_conf) ++ ++#endif//_MDRV_RQCT_IO_H_ ++//! @} +diff --git a/drivers/sstar/include/mdrv_rqct_st.h b/drivers/sstar/include/mdrv_rqct_st.h +new file mode 100755 +index 000000000000..0a4280b35aea +--- /dev/null ++++ b/drivers/sstar/include/mdrv_rqct_st.h +@@ -0,0 +1,132 @@ ++/* ++* mdrv_rqct_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_RQCT_ST_H_ ++#define _MDRV_RQCT_ST_H_ ++ ++#define RQCTIF_MAJ 1 //!< major version: Major number of driver-I/F version. ++#define RQCTIF_MIN 1 //!< minor version: Minor number of driver-I/F version. ++#define RQCTIF_EXT 1 //!< extended code: Extended number of version. It should increase when "mdrv_rqct_io.h/mdrv_rqct_st.h" changed. ++ ++//! RQCT Interface version number. ++#define RQCTIF_VERSION_ID ((RQCTIF_MAJ<<22)|(RQCTIF_MIN<<12)|(RQCTIF_EXT)) ++//! Acquire version number. ++#define RQCTIF_GET_VER(v) (((v)>>12)) ++//! Acquire major version number. ++#define RQCTIF_GET_MJR(v) (((v)>>22)&0x3FF) ++//! Acquire minor version number. ++#define RQCTIF_GET_MNR(v) (((v)>>12)&0x3FF) ++//! Acquire extended number. ++#define RQCTIF_GET_EXT(v) (((v)>> 0)&0xFFF) ++ ++//! rqct-method : support 3 types - CQP, CBR, VBR. ++enum rqct_method ++{ ++ RQCT_METHOD_CQP=0, //!< constant QP. ++ RQCT_METHOD_CBR, //!< constant bitrate. ++ RQCT_METHOD_VBR, //!< variable bitrate. ++}; ++ ++//! mvhe_superfrm_mode indicates super frame mechanism ++enum rqct_superfrm_mode ++{ ++ RQCT_SUPERFRM_NONE=0, //!< super frame mode none. ++ RQCT_SUPERFRM_DISCARD, //!< super frame mode discard. ++ RQCT_SUPERFRM_REENCODE, //!< super frame mode reencode. ++}; ++ ++//! rqct_conf is used to apply/query rq-configs during streaming period. ++typedef union rqct_conf ++{ ++ //! rqct-config type. ++ enum rqct_conf_e ++ { ++ RQCT_CONF_SEQ=0, //!< set sequence rate-control. ++ RQCT_CONF_DQP, //!< set delta-qp between I/P. ++ RQCT_CONF_QPR, //!< set range-qp. ++ RQCT_CONF_LOG, //!< turn on/off rqct log message. ++ RQCT_CONF_PEN, //!< penalties for mfe. ++ RQCT_CONF_SPF, //!< super frame settings. ++ RQCT_CONF_LTR, //!< long term reference setting ++ RQCT_CONF_END, //!< endof rqct-conf-enum. ++ } type; //!< indicating config. type. ++ ++ //! set rqct seq. config. ++ struct _seq ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_SEQ. ++ enum rqct_method i_method; //!< indicating rqct-method. ++ int i_period; //!< ip-period. ++ int i_leadqp; //!< leadqp. ++ int i_btrate; //!< btrate. ++ } seq; //!< rqct configs of seq. setting. ++ ++ //! set rqct lt config ++ struct _ltr ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CONF_LTR. ++ int i_period; //!< ltr period ++ } ltr; ++ ++ //! set rqct dqp. config. ++ struct _dqp ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_DQP. ++ int i_dqp; //!< dif-qp between I/P. ++ } dqp; //!< rqct configs of dqp. setting. ++ ++ //! set rqct qpr. config. ++ struct _qpr ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_QPR. ++ int i_iupperq; //!< I frame upperq. ++ int i_ilowerq; //!< I frame lowerq. ++ int i_pupperq; //!< P frame upperq. ++ int i_plowerq; //!< P frame lowerq. ++ } qpr; //!< rqct configs of dqp. setting. ++ ++ //! set rqct log. config. ++ struct _log ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_LOG. ++ int b_logm; //!< switch of log-message. ++ } log; //!< rqct configs of dqp. setting. ++ ++ //! set rqct pen. config. ++ struct _pen ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_PEN. ++ short b_i16pln; //!< enable intra16 planar. ++ short i_peni4x; //!< penalty intra4x4. ++ short i_peni16; //!< penalty intra16. ++ short i_penint; //!< penalty inter. ++ short i_penYpl; //!< penalty planar luma. ++ short i_penCpl; //!< penalty planar cbcr. ++ } pen; //!< rqct configs of dqp. setting. ++ ++ struct _spf ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be MVHE_PARM_SPF. ++ enum rqct_superfrm_mode i_spfrm; ++ int i_IFrmBitsThr; ++ int i_PFrmBitsThr; ++ int i_BFrmBitsThr; ++ } spf; //!< used to set super frame skip mode configuration. ++} rqct_conf; ++ ++#endif//_MDRV_RQCT_ST_H_ ++//! @} +diff --git a/drivers/sstar/include/mdrv_sar_io.h b/drivers/sstar/include/mdrv_sar_io.h +new file mode 100755 +index 000000000000..5e816e2df7e3 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_sar_io.h +@@ -0,0 +1,32 @@ ++/* ++* mdrv_sar_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_SAR_IO__ ++#define __MDRV_SAR_IO__ ++ ++typedef struct ++{ ++ int channel_value; ++ int adc_value; ++} SAR_ADC_CONFIG_READ; ++ ++ ++#define SARADC_IOC_MAGIC 'a' ++#define IOCTL_SAR_INIT _IO(SARADC_IOC_MAGIC, 0) ++#define IOCTL_SAR_SET_CHANNEL_READ_VALUE _IO(SARADC_IOC_MAGIC, 1) ++ ++#endif +diff --git a/drivers/sstar/include/mdrv_sca_io.h b/drivers/sstar/include/mdrv_sca_io.h +new file mode 100755 +index 000000000000..85ce76f10471 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_sca_io.h +@@ -0,0 +1,165 @@ ++/* ++* mdrv_sca_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_SCA_IO_H ++#define _MDRV_SCA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++#include "mdrv_sca_st.h" ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_SCA_LIB_CODE {'S','C','A','\0'} ++#define MSIF_SCA_BUILDNUM {'_','0','1','\0'} ++#define MSIF_SCA_LIBVER (2) ++#define MSIF_SCA_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++#define IOCTL_SCA_CONNECT_NR (0) ++#define IOCTL_SCA_DISCONNECT_NR (1) ++#define IOCTL_SCA_SET_TIMING_WINDOW_NR (2) ++#define IOCTL_SCA_SET_MVOP_NR (3) ++#define IOCTL_SCA_SET_DISPLAY_MUTE_NR (4) ++#define IOCTL_SCA_YPBPR_VGA_MODE_MON_PAR_NR (5) ++#define IOCTL_SCA_GET_MODE_NR (6) ++#define IOCTL_SCA_SET_VE_NR (7) ++#define IOCTL_SCA_SET_WINDOW_ONOFF_NR (8) ++#define IOCTL_SCA_SET_COLOR_KEY_NR (9) ++#define IOCTL_SCA_SET_MVOP_BASEADDR_NR (10) ++#define IOCTL_SCA_GET_MVOP_BASEADDR_NR (11) ++#define IOCTL_SCA_CHANGE_WINDOW_NR (12) ++#define IOCTL_SCA_SET_PICTURE_NR (13) ++#define IOCTL_SCA_GET_PICTURE_NR (14) ++#define IOCTL_SCA_SET_OUTPUT_TIMING_NR (15) ++#define IOCTL_SCA_CALIBRATION_NR (16) ++#define IOCTL_SCA_LOAD_ADC_SETTING_NR (17) ++#define IOCTL_SCA_AVD_CONNECT_NR (18) ++#define IOCTL_SCA_AVD_CHEKC_VIDEO_STD_NR (19) ++#define IOCTL_SCA_SET_CONSTANTAPLHA_VALUE_NR (20) ++#define IOCTL_SCA_GET_LIB_VER_NR (21) ++#define IOCTL_SCA_SET_DISP_INTR_NR (22) ++#define IOCTL_SCA_GET_DISP_INTR_NR (23) ++#define IOCTL_SCA_RW_REGISTER_NR (24) ++#define IOCTL_SCA_GET_ACE_INFO_NR (25) ++#define IOCTL_SCA_GET_DLC_INFO_NR (26) ++#define IOCTL_SCA_GET_DISP_PATH_CONFIG_NR (27) ++#define IOCTL_SCA_SET_MIRRORCONFIG_NR (28) ++#define IOCTL_SCA_SET_PQ_BIN_NR (29) ++#define IOCTL_SCA_SET_DIP_CONFIG_NR (30) ++#define IOCTL_SCA_GET_DISP_INTR_STATUS_NR (31) ++#define IOCTL_SCA_SET_HDMITX_CONFIG_NR (32) ++#define IOCTL_SCA_SET_DIP_WONCE_TRIG_BASE_NR (33) ++#define IOCTL_SCA_SET_FREEZE_CONFIG_NR (34) ++#define IOCTL_SCA_INIT_MST701_NR (35) ++#define IOCTL_SCA_GEOMETRY_CALIBRATION_NR (36) ++#define IOCTL_SCA_LOAD_GEOMETRY_SETTING_NR (37) ++#define IOCTL_SCA_SET_ANALOG_POLLING_CONFIG_NR (38) ++#define IOCTL_SCA_SET_CLONE_SCREEN_CONFIG_NR (39) ++#define IOCTL_SCA_GET_CLONE_SCREEN_CONFIG_NR (40) ++#define IOCTL_SCA_SET_PNL_SCC_CONFIG_NR (41) ++#define IOCTL_SCA_SET_CONSTANTALPHA_STATE_NR (42) ++#define IOCTL_SCA_SET_PNL_TIMING_CONFIG_NR (43) ++#define IOCTL_SCA_GET_MONITOR_STATUS_CONFIG_NR (44) ++#define IOCTL_SCA_SET_USER_DISPLAY_CONFIG_NR (45) ++#define IOCTL_SCA_SET_DISPLAY_MUTE_COLOR_NR (46) ++#define IOCTL_SCA_SET_CLONE_SCREEN_RATIO_NR (47) ++#define IOCTL_SCA_SET_DLC_INIT_CONFIG_NR (48) ++#define IOCTL_SCA_SET_DLC_ONOFF_CONFIG_NR (49) ++#define IOCTL_SCA_SET_UEVENT_CONFIG_NR (50) ++#define IOCTL_SCA_SET_CVBSOUT_DAC_CONFIG_NR (51) ++#define IOCTL_SCA_SET_USER_DIPLAY_CONFIG_EX_NR (52) ++#define IOCTL_SCA_SET_CAMERA_INPUTTIMING_CONFIG_NR (53) ++#ifdef __BOOT_PNL__//paul_test ++#define IOCTL_SCA_SET_PQ_BIN_IBC_NR (54) ++#define IOCTL_SCA_SET_PQ_BIN_ICC_NR (55) ++#define IOCTL_SCA_SET_PQ_BIN_IHC_NR (56) ++#define IOCTL_SCA_MAX_NR (57) ++#else ++#define IOCTL_SCA_MAX_NR (54) ++#endif ++ ++ ++ ++ ++// use 'm' as magic number ++#define IOCTL_SCA_MAGIC ('2') ++ ++#define IOCTL_SCA_CONNECT _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_CONNECT_NR) ++#define IOCTL_SCA_DISCONNECT _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_DISCONNECT_NR) ++#define IOCTL_SCA_SET_TIMING_WINDOW _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_TIMING_WINDOW_NR) ++#define IOCTL_SCA_SET_MVOP _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_MVOP_NR) ++#define IOCTL_SCA_SET_DISPLAY_MUTE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DISPLAY_MUTE_NR) ++#define IOCTL_SCA_YPBPR_VGA_MODE_MON_PAR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_YPBPR_VGA_MODE_MON_PAR_NR) ++#define IOCTL_SCA_GET_MODE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_MODE_NR) ++#define IOCTL_SCA_SET_VE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_VE_NR) ++#define IOCTL_SCA_SET_WINDOW_ONOFF _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_WINDOW_ONOFF_NR) ++#define IOCTL_SCA_SET_COLOR_KEY _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_COLOR_KEY_NR) ++#define IOCTL_SCA_SET_MVOP_BASEADDR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_MVOP_BASEADDR_NR) ++#define IOCTL_SCA_GET_MVOP_BASEADDR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_MVOP_BASEADDR_NR) ++#define IOCTL_SCA_CHANGE_WINDOW _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_CHANGE_WINDOW_NR) ++#define IOCTL_SCA_SET_PICTURE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PICTURE_NR) ++#define IOCTL_SCA_GET_PICTURE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_PICTURE_NR) ++#define IOCTL_SCA_SET_OUTPUT_TIMING _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_OUTPUT_TIMING_NR) ++#define IOCTL_SCA_CALIBRATION _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_CALIBRATION_NR) ++#define IOCTL_SCA_LOAD_ADC_SETTING _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_LOAD_ADC_SETTING_NR) ++#define IOCTL_SCA_AVD_CONNECT _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_AVD_CONNECT_NR) ++#define IOCTL_SCA_AVD_CHECK_VIDEO_STD _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_AVD_CHEKC_VIDEO_STD_NR) ++#define IOCTL_SCA_GET_LIB_VER _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_LIB_VER_NR) ++#define IOCTL_SCA_SET_CONSTANTALPHA_VALUE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CONSTANTAPLHA_VALUE_NR) ++#define IOCTL_SCA_SET_DISP_INTR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DISP_INTR_NR) ++#define IOCTL_SCA_GET_DISP_INTR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DISP_INTR_NR) ++#define IOCTL_SCA_RW_REGISTER _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_RW_REGISTER_NR) ++#define IOCTL_SCA_GET_ACE_INFO _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_ACE_INFO_NR) ++#define IOCTL_SCA_GET_DLC_INFO _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DLC_INFO_NR) ++#define IOCTL_SCA_GET_DISP_PATH_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DISP_PATH_CONFIG_NR) ++#define IOCTL_SCA_SET_MIRROR_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_MIRRORCONFIG_NR) ++#define IOCTL_SCA_SET_PQ_BIN _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_NR) ++#define IOCTL_SCA_SET_DIP_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DIP_CONFIG_NR) ++#define IOCTL_SCA_GET_DISP_INTR_STATUS _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DISP_INTR_STATUS_NR) ++#define IOCTL_SCA_SET_HDMITX_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_HDMITX_CONFIG_NR) ++#define IOCTL_SCA_SET_DIP_WONCE_BASE_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DIP_WONCE_TRIG_BASE_NR) ++#define IOCTL_SCA_SET_FREEZE_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_FREEZE_CONFIG_NR) ++#define IOCTL_SCA_INIT_MST701 _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_INIT_MST701_NR) ++#define IOCTL_SCA_GEOMETRY_CALIBRATION _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GEOMETRY_CALIBRATION_NR) ++#define IOCTL_SCA_LOAD_GEOMETRY_SETTING _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_LOAD_GEOMETRY_SETTING_NR) ++#define IOCTL_SCA_SET_ANALOG_POLLING_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_ANALOG_POLLING_CONFIG_NR) ++#define IOCTL_SCA_SET_CLONE_SCREEN_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CLONE_SCREEN_CONFIG_NR) ++#define IOCTL_SCA_GET_CLONE_SCREEN_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_CLONE_SCREEN_CONFIG_NR) ++#define IOCTL_SCA_SET_PNL_SSC_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PNL_SCC_CONFIG_NR) ++#define IOCTL_SCA_SET_CONSTANTALPHA_STATE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CONSTANTALPHA_STATE_NR) ++#define IOCTL_SCA_SET_PNL_TIMING_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PNL_TIMING_CONFIG_NR) ++#define IOCTL_SCA_GET_MONITOR_STATUS_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_MONITOR_STATUS_CONFIG_NR) ++#define IOCTL_SCA_SET_USER_DISPLAY_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_USER_DISPLAY_CONFIG_NR) ++#define IOCTL_SCA_SET_DISPLAY_MUTE_COLOR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DISPLAY_MUTE_COLOR_NR) ++#define IOCTL_SCA_SET_CLONE_SCREEN_RATIO _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CLONE_SCREEN_RATIO_NR) ++#define IOCTL_SCA_SET_DLC_INIT_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DLC_INIT_CONFIG_NR) ++#define IOCTL_SCA_SET_DLC_ONOFF_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DLC_ONOFF_CONFIG_NR) ++#define IOCTL_SCA_SET_UEVENT_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_UEVENT_CONFIG_NR) ++#define IOCTL_SCA_SET_CVBSOUT_DAC_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CVBSOUT_DAC_CONFIG_NR) ++#define IOCTL_SCA_SET_USER_DISPLAY_CONFIG_EX _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_USER_DIPLAY_CONFIG_EX_NR) ++#define IOCTL_SCA_SET_CAMERA_INPUTTIMING_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CAMERA_INPUTTIMING_CONFIG_NR) ++#ifdef __BOOT_PNL__//paul_test ++#define IOCTL_SCA_SET_PQ_BIN_IBC _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_IBC_NR) ++#define IOCTL_SCA_SET_PQ_BIN_ICC _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_ICC_NR) ++#define IOCTL_SCA_SET_PQ_BIN_IHC _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_IHC_NR) ++#endif ++ ++#endif //_MDRV_GFLIP_IO_H +diff --git a/drivers/sstar/include/mdrv_sca_st.h b/drivers/sstar/include/mdrv_sca_st.h +new file mode 100755 +index 000000000000..40a764c65d74 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_sca_st.h +@@ -0,0 +1,939 @@ ++/* ++* mdrv_sca_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_SCA_ST_H ++#define _MDRV_SCA_ST_H ++ ++#if !defined(MS_U8) && !defined(MS_BOOL) ++#define MS_U8 unsigned char ++#define MS_U16 unsigned short ++#define MS_U32 unsigned long ++#define MS_U64 unsigned long long ++#define MS_BOOL unsigned char ++#define MS_S16 signed short ++#endif ++ ++//============================================================================= ++// structure & Enum ++//============================================================================= ++typedef enum ++{ ++ SCA_DEST_MAIN = 0, ++ SCA_DEST_SUB = 1, ++ SCA_DEST_MAIN_1 = 2, ++ SCA_DEST_MAIN_2 = 3, ++ SCA_DEST_SUB_2 = 4, ++ SCA_DEST_CVBSO = 5, ++ SCA_DEST_HDMITx = 6, ++ SCA_DEST_NUM, ++}SCA_DEST_TYPE; ++ ++ ++typedef enum ++{ ++ SCA_SRC_VGA, ++ SCA_SRC_YPBPR, ++ SCA_SRC_CVBS, ++ SCA_SRC_CVBS2, ++ SCA_SRC_CVBS3, ++ SCA_SRC_SVIDEO, // Add S-video input source // ++ SCA_SRC_DTV, ++ SCA_SRC_SC0_VOP, ++ SCA_SRC_SC1_VOP, ++ SCA_SRC_SC2_VOP, ++ SCA_SRC_BT656, ++ SCA_SRC_BT656_1, ++ SCA_SRC_CAMERA, ++ SCA_SRC_NUM, ++}SCA_SRC_TYPE; ++ ++typedef enum ++{ ++ SCA_MVOP_INPUT_DRAM, ++ SCA_MVOP_INPUT_H264, ++ SCA_MVOP_INPUT_MVD, ++ SCA_MVOP_INPUT_RVD, ++ SCA_MVOP_INPUT_CLIP, ++ SCA_MVOP_INPUT_JPD, ++ SCA_MVOP_INPUT_HVD_3DLR, ++ SCA_MVOP_INPUT_MVD_3DLR, ++ SCA_MVOP_INPUT_UNKNOWN, ++} SCA_MVOP_INPUT_SEL; ++ ++ ++typedef enum ++{ ++ SCA_MODE_PARSING_SUPPORT, ++ SCA_MODE_PARSING_UNSUPPORT, ++ SCA_MODE_PARSING_FAIL, ++}SCA_PARSING_MODE_STATUS; ++ ++typedef enum ++{ ++ SCA_VE_OUTPUT_NTSC, ++ SCA_VE_OUTPUT_PAL, ++}SCA_VE_OUTPUT_STD; ++ ++ ++typedef enum ++{ ++ SCA_MVOP_TILE_8x32, ++ SCA_MVOP_TILE_16x32, ++ SCA_MVOP_TILE_NONE, ++}SCA_MVOP_TILE_TYPE; ++ ++typedef enum ++{ ++ SCA_MODE_MONITOR_NOSYNC = 0, ///< Input timing stable, no input sync detected ++ SCA_MODE_MONITOR_STABLE_SUPPORT_MODE, ///< Input timing stable, has stable input sync and support this timing ++ SCA_MODE_MONITOR_STABLE_UN_SUPPORT_MODE, ///< Input timing stable, has stable input sync but this timing is not supported ++ SCA_MODE_MONITOR_UNSTABLE, ///< Timing change, has to wait InfoFrame if HDMI input ++}SCA_MODE_MOINITOR_STATUS; ++ ++ ++typedef enum ++{ ++ SCA_PICTURE_BRIGHTNESS = 0x01, ++ SCA_PICTURE_CONTRAST = 0x02, ++ SCA_PICTURE_HUE = 0x04, ++ SCA_PICTURE_SATURATION = 0x08, ++ SCA_PICTURE_SHARPNESS = 0x10, ++ SCA_PICTURE_COLOR_TEMPERATURE = 0x20, ++}SCA_PICTURE_TYPE; ++ ++typedef enum ++{ ++ SCA_COLOR_TEMP_COOL, ++ SCA_COLOR_TEMP_NORMAL, ++ SCA_COLOR_TEMP_WARM, ++}SCA_COLOR_TEMPERATURE_TYPE; ++ ++typedef enum ++{ ++ SCA_OUTPUT_480_I_60, ++ SCA_OUTPUT_480_P_60, ++ SCA_OUTPUT_576_I_50, ++ SCA_OUTPUT_576_P_50, ++ SCA_OUTPUT_720_P_50, ++ SCA_OUTPUT_720_P_60, ++ SCA_OUTPUT_1080_P_50, ++ SCA_OUTPUT_1080_P_60, ++ SCA_OUTPUT_480_P_30, ++ SCA_OUTPUT_720_P_30, ++}SCA_OUTPUT_TIMING_TYPE; ++ ++typedef enum ++{ ++ SCA_REG_R_BYTE, ++ SCA_REG_W_BYTE, ++ SCA_REG_XC_R2BYTEMSK, ++ SCA_REG_XC_W2BYTEMSK, ++}SCA_RW_REG_TYPE; ++ ++ ++typedef enum ++{ ++ SCA_DISP_PRI_NONE = 0, ++ SCA_DISP_PRI_NORMAL = 1, ++ SCA_DISP_PRI_CAR_BACK = 2, ++}SCA_DISP_PRIORITY_TYPE; ++ ++typedef enum ++{ ++ SCA_PQ_BIN_ID_STD_MAIN = 0x0, ++ SCA_PQ_BIN_ID_STD_SUB = 0x1, ++ SCA_PQ_BIN_ID_STD_SC1_MAIN = 0x2, ++ SCA_PQ_BIN_ID_STD_SC2_MAIN = 0x3, ++ SCA_PQ_BIN_ID_STD_SC2_SUB = 0x4, ++ SCA_PQ_BIN_ID_EXT_MAIN = 0x5, ++ SCA_PQ_BIN_ID_EXT_SUB = 0x6, ++ SCA_PQ_BIN_ID_EXT_SC1_MAIN = 0x7, ++ SCA_PQ_BIN_ID_EXT_SC2_MAIN = 0x8, ++ SCA_PQ_BIN_ID_EXT_SC2_SUB = 0x9, ++ SCA_PQ_BIN_ID_NUM, ++ SCA_PQ_BIN_ID_NONE = 0xFF, ++}SCA_PQ_BIN_ID_TYPE; ++ ++typedef enum ++{ ++ SCA_DIP_DEST_FMT_YC422, ++ SCA_DIP_DEST_FMT_RGB565, ++ SCA_DIP_DEST_FMT_ARGB8888, ++ SCA_DIP_DEST_FMT_YC420_MVOP, ++ SCA_DIP_DEST_FMT_YC420_MFE, ++}SCA_DIP_DEST_FMT_TYPE; ++ ++typedef enum ++{ ++ SCA_DIP_TRIGGER_LOOP = 0, ++ SCA_DIP_TRIGGER_ONCE, ++}SCA_DIP_TRIGGER_TYPE; ++ ++typedef enum ++{ ++ SCA_HDMITX_OUT_HDMI, ++ SCA_HDMITX_OUT_HDMI_HDCP, ++}SCA_HDMITX_MODE_TYPE; ++ ++typedef enum ++{ ++ SCA_HDMITX_480_I_60, ++ SCA_HDMITX_480_P_60, ++ SCA_HDMITX_576_I_50, ++ SCA_HDMITX_576_P_50, ++ SCA_HDMITX_720_P_50, ++ SCA_HDMITX_720_P_60, ++ SCA_HDMITX_1080_I_50, ++ SCA_HDMITX_1080_I_60, ++ SCA_HDMITX_1080_P_50, ++ SCA_HDMITX_1080_P_60, ++ SCA_HDMITX_1080_P_30, ++ SCA_HDMITX_1080_P_25, ++ SCA_HDMITX_1080_P_24, ++}SCA_HDMITX_OUTPUT_TIMINE_TYPE; ++ ++typedef enum ++{ ++ SCA_HDMITX_OUTPUT_COLOR_RGB, ++ SCA_HDMITX_OUTPUT_COLOR_YUV, ++}SCA_HDMITX_OUTPUT_COLOR_TYPE; ++ ++typedef enum ++{ ++ SCA_CLONE_SCREEN_NONE, ++ SCA_CLONE_SCREEN_GOP, ++}SCA_CLONE_SCREEN_TYPE; ++ ++ ++typedef enum ++{ ++ SCA_DISPLAY_MUTE_BLACK, ++ SCA_DISPLAY_MUTE_WHITE, ++ SCA_DISPLAY_MUTE_BLUE, ++ SCA_DISPLAY_MUTE_RED, ++ SCA_DISPLAY_MUTE_GREEN, ++}SCA_DISPLAY_MUTE_COLOR_TYPE; ++ ++ ++//------------------------------------------------------------------------------ ++typedef struct ++{ ++ SCA_SRC_TYPE enSrcType; ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bAutoDetect; ++ SCA_DISP_PRIORITY_TYPE enPriType; ++ MS_U32 dwUID; ++}SCA_CONNECT_CONFIG, *PSCA_CONNECT_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16HSize; ++ MS_U16 u16VSize; ++ MS_U32 u32YOffset; ++ MS_U32 u32UVOffset; ++ MS_BOOL bSD; ++ MS_BOOL bYUV422; ++ MS_BOOL bProgressive; ++ MS_BOOL bUV7bit; ++ MS_BOOL bDramRdContd; ++ MS_BOOL bField; ++ MS_BOOL b422pack; ++ MS_U16 u16StripSize; ++ SCA_MVOP_INPUT_SEL enInputSel; ++}SCA_MVOP_IN_CONFIG, *PSCA_MVOP_IN_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16HorSize; ++ MS_U16 u16VerSize; ++ MS_U16 u16FrameRate; ++ MS_U8 u8AspectRate; ++ MS_U8 u8Interlace; ++}SCA_MVOP_OUT_CONFIG, *PSCA_MVOP_OUT_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_MVOP_TILE_TYPE enTileType; ++ SCA_MVOP_IN_CONFIG stInConfig; ++ SCA_MVOP_OUT_CONFIG stOutConfig; ++}SCA_MVOP_CONFIG, *PSCA_MVOP_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bUpdate; ++ MS_U16 u16InputVTotal; ++ MS_BOOL bInterlace; ++ MS_U16 u16InputVFreq; ++}SCA_TIMING_CONFIG, *PSCA_TIMING_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 x; ++ MS_U16 y; /// valid, valid -> none) ++ MS_U8 INT_F1_CSOG :1; ++ MS_U8 INT_F2_ATS_READY :1; ///< scaler dosen't have this interrupt now ++ MS_U8 INT_F1_ATS_READY :1; ++ MS_U8 INT_F2_ATP_READY :1; ///< auto phase ready interrupt ++ MS_U8 INT_F1_ATP_READY :1; ++ MS_U8 INT_F2_ATG_READY :1; ///< scaler dosen't have this interrupt now ++ MS_U8 INT_F1_ATG_READY :1; ++}SCA_DISP_INTR_CONFIG; ++ ++typedef struct ++{ ++ #define SCA_NUM 3 ++ SCA_DISP_INTR_CONFIG stIntrConfig[SCA_NUM]; ++ MS_BOOL bIntrConfig_DIPW; ++ MS_U32 u32DIPW_Signal_PID; ++}SCA_DISP_INTR_SETTING; ++ ++typedef struct ++{ ++ #define SCA_NUM 3 ++ SCA_DISP_INTR_CONFIG stDisp_Intr_Status[SCA_NUM]; ++ MS_U8 u8DIPW_Status; ++}SCA_DISP_INTR_STATUS; ++ ++typedef struct ++{ ++ SCA_RW_REG_TYPE enType; ++ MS_U32 u32addr; ++ MS_U16 u16value; ++ MS_U16 u16mask; ++}SCA_RW_REGISTER_CONFIG, *PSCA_RW_REGISTER_CONFIG; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ MS_U16 u16version; ++ MS_U16 u16contrast; ++ MS_U16 u16r_gain; ++ MS_U16 u16g_gain; ++ MS_U16 u16b_gain; ++ MS_U16 u16saturation; ++ MS_U16 u16hue; ++ MS_U16 u16color_correct_xy_r; ++ MS_U16 u16color_correct_xy_g; ++ MS_U16 u16color_correct_xy_b; ++ MS_U16 u16color_correct_offset_r; ++ MS_U16 u16color_correct_offset_g; ++ MS_U16 u16color_correct_offset_b; ++}SCA_ACE_INFO_CONFIG, *PSCA_ACE_INFO_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32CmdBufAddr; ++ MS_U16 u16CmdBufLen; ++ MS_U16 u16DataLen; ++ MS_U16 u16PNL_Width; ++ MS_U16 u16PNL_Height; ++}SCA_DLC_INFO_CONFIG, *PSCA_DLC_INFO_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bChanged; ++ MS_BOOL bDisConnect; ++ SCA_DISP_PRIORITY_TYPE enPriType; ++ SCA_DEST_TYPE enDestType; ++ SCA_SRC_TYPE enSrcType; ++ MS_U32 dwUID; ++}SCA_DISP_PATH_CONFIG, *PSCA_DISP_PATH_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ SCA_DEST_TYPE enDestType; ++}SCA_MIRROR_CONFIG, *PSCA_MIRROR_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_PQ_BIN_ID_TYPE enPQBinIDType; ++ MS_U32 u32PQBin_Addr; ++ MS_U32 u32PQBin_Size; ++}SCA_PQ_BIN_INFO; ++ ++typedef struct ++{ ++ SCA_PQ_BIN_INFO stPQBinInfo[SCA_PQ_BIN_ID_NUM]; ++}SCA_PQ_BIN_CONFIG, *PSCA_PQ_BIN_CONFIG; ++typedef struct { ++ MS_U16 u16value; ++ MS_BOOL bnegative;//0=add ,1=minus ++}SCA_PQ_adj; ++ ++typedef struct { ++ MS_BOOL icc_en; ++ SCA_PQ_adj icc_gain_R; ++ SCA_PQ_adj icc_gain_G; ++ SCA_PQ_adj icc_gain_B; ++ SCA_PQ_adj icc_gain_Y; ++ SCA_PQ_adj icc_gain_M; ++ SCA_PQ_adj icc_gain_C; ++ SCA_PQ_adj icc_gain_F; ++ SCA_PQ_adj icc_gain_NC; ++}SCA_PQ_ICC_CFG,*PSCA_PQ_ICC_CFG; ++ ++typedef struct { ++ MS_BOOL ibc_en; ++ SCA_PQ_adj ibc_gain_R;//RGB...no use positive ++ SCA_PQ_adj ibc_gain_G; ++ SCA_PQ_adj ibc_gain_B; ++ SCA_PQ_adj ibc_gain_Y; ++ SCA_PQ_adj ibc_gain_M; ++ SCA_PQ_adj ibc_gain_C; ++ SCA_PQ_adj ibc_gain_F; ++}SCA_PQ_IBC_CFG,*PSCA_PQ_IBC_CFG; ++ ++typedef struct { ++ MS_BOOL ihc_en; ++ SCA_PQ_adj ihc_gain_R;//RGB...=max3F+P/N ++ SCA_PQ_adj ihc_gain_G; ++ SCA_PQ_adj ihc_gain_B; ++ SCA_PQ_adj ihc_gain_Y; ++ SCA_PQ_adj ihc_gain_M; ++ SCA_PQ_adj ihc_gain_C; ++ SCA_PQ_adj ihc_gain_F; ++}SCA_PQ_IHC_CFG,*PSCA_PQ_IHC_CFG; ++ ++ ++ ++ ++ ++typedef struct ++{ ++ SCA_DIP_DEST_FMT_TYPE enDestFmtType; ++ MS_BOOL bClipEn; ++ SCA_WINDOW_TYPE stClipWin; ++ MS_U8 u8FrameNum; ++ MS_U32 u32BuffAddress; ++ MS_U32 u32BuffSize; ++ MS_U32 u32C_BuffAddress; ++ MS_U32 u32C_BuffSize; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++ MS_BOOL bTriggle; ++ SCA_DIP_TRIGGER_TYPE enTrigMode; ++}SCA_DIP_CONFIG, *PSCA_DIP_CONFIG; ++ ++ ++typedef struct ++{ ++ MS_U32 u32BuffAddress; ++ MS_U32 u32C_BuffAddress; ++ MS_BOOL bTrig; ++}SCA_DIP_WONCE_BASE_CONFIG, *PSCA_DIP_WONCE_BASE_CONFIG; ++ ++typedef struct ++{ ++ SCA_HDMITX_OUTPUT_TIMINE_TYPE enHDMITx_OutputTiming; ++ SCA_HDMITX_MODE_TYPE enHDMITx_Mode; ++ SCA_HDMITX_OUTPUT_COLOR_TYPE enHDMITx_ColorType; ++ MS_BOOL bEn; ++}SCA_HDMITX_CONFIG, *PSCA_HDMITX_CONFIG; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bEn; ++}SCA_FREEZE_CONFIG, *PSCA_FREEZE_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bFroceInit; ++ MS_U32 u32MST701Bin_Addr; ++ MS_U32 u32MST701Bin_Bytes; ++}SCA_MST701_CONFIG, *PSCA_MST701_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_SRC_TYPE enSrcType; ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bSuccess; ++ MS_U8 u8ModeIndex; ++ MS_U16 u16Hstart; ++ MS_U16 u16Vstart; ++ MS_U16 u16Phase; ++ MS_U16 u16Htotal; ++}SCA_GEOMETRY_CALI_CONFIG, *PSCA_GEOMETRY_CALI_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16SableCnt; ++ MS_U16 u16NoSyncCnt; ++ MS_U32 u32PollingPeriod; //ms ++}SCA_ANALOG_POLLING_CONFIG, *PSCA_ANALOG_POLLING_CONFIG; ++ ++typedef struct ++{ ++ SCA_CLONE_SCREEN_TYPE enCloneScreenType; ++}SCA_CLONE_SCREEN_CONFIG, *PSCA_CLONE_SCREEN_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Modulation; ++ MS_U16 u16Deviation; ++ MS_BOOL bEn; ++}SCA_PNL_SSC_CONFIG, *PSCA_PNL_SSC_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Htt; ++ MS_U16 u16H_Active; ++ MS_U16 u16HSync_Width; ++ MS_U16 u16HSync_Fporch; ++ MS_U16 u16HSync_Bporch; ++ MS_U16 u16Vtt; ++ MS_U16 u16V_Active; ++ MS_U16 u16VSync_Width; ++ MS_U16 u16VSync_Fporch; ++ MS_U16 u16VSync_Bporch; ++ MS_U16 u16DCLK_MHz; ++}SCA_PNL_TIMING_CONFIG, *PSCA_PNL_TIMING_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ SCA_SRC_TYPE enSrcType; ++ MS_BOOL bSetModeDone; ++}SCA_MONITOR_STATUS_CONFIG, *PSCA_MONITOR_STATUS_CONFIG; ++ ++typedef struct ++{ ++ SCA_SRC_TYPE enSrcType; ++ MS_BOOL bEn; ++ MS_U16 u16H_Overscan; ++ MS_U16 u16V_Overscan; ++ MS_S16 s16H_Offset; ++ MS_S16 s16V_Offset; ++ MS_BOOL bCVBS_NTSC; ++}SCA_USER_DISPLAY_CONFIG, *PSCA_USER_DISPLAY_CONFIG; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ SCA_SRC_TYPE enSrcType; ++ MS_BOOL bEn; ++ MS_U16 u16H_Overscan; ++ MS_U16 u16V_Overscan; ++ MS_S16 s16H_Offset; ++ MS_S16 s16V_Offset; ++ MS_BOOL bCVBS_NTSC; ++}SCA_USER_DISPLAY_CONFIG_EX, *PSCA_USER_DISPLAY_CONFIG_EX; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ SCA_DISPLAY_MUTE_COLOR_TYPE enColorType; ++}SCA_DISPLAY_MUTE_COLOR_CONFIG, *PSCA_DISPLAY_MUTE_COLOR_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U16 u16H_ratio; ++ MS_U16 u16V_ratio; ++}SCA_CLONE_SCREEN_DISPLAY_RATIO_CONFIG, *PSCA_CLONE_SCREEN_DISPLAY_RATIO_CONFIG; ++ ++typedef struct ++{ ++ ++ ++ MS_U8 ucLumaCurve[16]; ++ MS_U8 ucLumaCurve2_a[16]; ++ MS_U8 ucLumaCurve2_b[16]; ++ MS_U8 ucDlcHistogramLimitCurve[17]; ++ ++ MS_U8 u8_L_L_U; ++ MS_U8 u8_L_L_D; ++ MS_U8 u8_L_H_U; ++ MS_U8 u8_L_H_D; ++ MS_U8 u8_S_L_U; ++ MS_U8 u8_S_L_D; ++ MS_U8 u8_S_H_U; ++ MS_U8 u8_S_H_D; ++ ++ MS_U8 ucDlcPureImageMode; ++ MS_U8 ucDlcLevelLimit; ++ MS_U8 ucDlcAvgDelta; ++ MS_U8 ucDlcAvgDeltaStill; ++ MS_U8 ucDlcFastAlphaBlending; ++ MS_U8 ucDlcYAvgThresholdL; ++ MS_U8 ucDlcYAvgThresholdH; ++ MS_U8 ucDlcBLEPoint; ++ MS_U8 ucDlcWLEPoint; ++ MS_U8 bEnableBLE; ++ MS_U8 bEnableWLE; ++ ++ MS_U8 ucDlcYAvgThresholdM; ++ MS_U8 ucDlcCurveMode; ++ MS_U8 ucDlcCurveModeMixAlpha; ++ ++ MS_U8 ucDlcAlgorithmMode; ++ ++ MS_U8 ucDlcSepPointH; ++ MS_U8 ucDlcSepPointL; ++ MS_U16 uwDlcBleStartPointTH; ++ MS_U16 uwDlcBleEndPointTH; ++ MS_U8 ucDlcCurveDiff_L_TH; ++ MS_U8 ucDlcCurveDiff_H_TH; ++ MS_U16 uwDlcBLESlopPoint_1; ++ MS_U16 uwDlcBLESlopPoint_2; ++ MS_U16 uwDlcBLESlopPoint_3; ++ MS_U16 uwDlcBLESlopPoint_4; ++ MS_U16 uwDlcBLESlopPoint_5; ++ MS_U16 uwDlcDark_BLE_Slop_Min; ++ MS_U8 ucDlcCurveDiffCoringTH; ++ MS_U8 ucDlcAlphaBlendingMin; ++ MS_U8 ucDlcAlphaBlendingMax; ++ MS_U8 ucDlcFlicker_alpha; ++ MS_U8 ucDlcYAVG_L_TH; ++ MS_U8 ucDlcYAVG_H_TH; ++ MS_U8 ucDlcDiffBase_L; ++ MS_U8 ucDlcDiffBase_M; ++ MS_U8 ucDlcDiffBase_H; ++ ++ MS_U8 bCGCCGainCtrl; ++ MS_U8 ucCGCCGain_offset; ++ MS_U8 ucCGCChroma_GainLimitH; ++ MS_U8 ucCGCChroma_GainLimitL; ++ MS_U8 ucCGCYCslope; ++ MS_U8 ucCGCYth; ++}SCA_DLC_INIT_CONFIG, *PSCA_DLC_INIT_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bDLCOnOff; ++ MS_BOOL bUserControl; ++}SCA_DLC_ONOFF_CONFIG, *PSCA_DLC_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U16 u16Size; ++ MS_U8 u8Msg[64]; ++}SCA_UEVENT_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++}SCA_CVBSOUT_DAC_CONFIG, *PSCA_CVBSOUT_DAC_CONFIG; ++ ++ ++typedef struct ++{ ++ MS_U16 u16x; ++ MS_U16 u16y; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++ MS_U16 u16Vtotal; ++ MS_U16 u16VFreq; ++ MS_BOOL bInterlace; ++}SCA_CAMERA_INPUTTIMING_CONFIG, *PSCA_CAMERA_INPUTTIMING_CONFIG; ++#endif //_MDRV_GFLIP_IO_H +diff --git a/drivers/sstar/include/mdrv_scldma_io.h b/drivers/sstar/include/mdrv_scldma_io.h +new file mode 100755 +index 000000000000..9a13c6072837 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_scldma_io.h +@@ -0,0 +1,144 @@ ++/* ++* mdrv_scldma_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/** ++ * \defgroup scldma_group SCLDMA driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/cksnp ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count ,W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma2.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmR ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmW ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_H ++#define _MDRV_SCLDMA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR (0) ///< The IOCTL NR definition, SET_IN_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR (1) ///< The IOCTL NR definition, SET_IN_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR (2) ///< The IOCTL NR definition, SET_OUT_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR (3) ///< The IOCTL NR definition, SET_OUT_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR (4) ///< The IOCTL NR definition, GET_IN_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR (5) ///< The IOCTL NR definition, GET_OUT_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition, GET_PRIVATE_ID_CONFIG ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG_NR (7) ///< The IOCTL NR definition, SET_LOCK_CONFIG ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR (8) ///< The IOCTL NR definition, SET_UNLOCK_CONFIG ++#define IOCLT_SCLDMA_GET_VERSION_CONFIG_NR (9) ///< The IOCTL NR definition, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR (10) ///< The IOCTL NR definition, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR (12) ///< The IOCTL NR definition, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR ++#define IOCTL_SCLDMA_MAX_NR (13) ///< The Max IOCTL NR for scldma driver ++ ++// use 'm' as magic number ++#define IOCTL_SCLDMA_MAGIC ('2') ///< The Type definition of IOCTL for scldma driver ++ ++/** ++* Used to set parameters of in buffer configurate ,buffer address and number,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_R device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set parameters of out buffer configurate,buffer address and number ,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_W device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_R device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_W device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to peek queue information and set read flag , use ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG. ++*/ ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR) ++/** ++* Used to get mutiinst parameters of private id configurate ,use ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of lock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_LOCK_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of unlock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_SCLDMA_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_VERSION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR) ++/** ++* Used to get DMA information, use ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR) ++ ++#endif // ++ ++/** @} */ // end of scldma_group +diff --git a/drivers/sstar/include/mdrv_scldma_io_i3.h b/drivers/sstar/include/mdrv_scldma_io_i3.h +new file mode 100755 +index 000000000000..1b640eb87bbc +--- /dev/null ++++ b/drivers/sstar/include/mdrv_scldma_io_i3.h +@@ -0,0 +1,144 @@ ++/* ++* mdrv_scldma_io_i3.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/** ++ * \defgroup scldma_group SCLDMA driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/cksnp ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count ,W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma2.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmR ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmW ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_H ++#define _MDRV_SCLDMA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR (0) ///< The IOCTL NR definition, SET_IN_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR (1) ///< The IOCTL NR definition, SET_IN_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR (2) ///< The IOCTL NR definition, SET_OUT_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR (3) ///< The IOCTL NR definition, SET_OUT_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR (4) ///< The IOCTL NR definition, GET_IN_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR (5) ///< The IOCTL NR definition, GET_OUT_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition, GET_PRIVATE_ID_CONFIG ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG_NR (7) ///< The IOCTL NR definition, SET_LOCK_CONFIG ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR (8) ///< The IOCTL NR definition, SET_UNLOCK_CONFIG ++#define IOCLT_SCLDMA_GET_VERSION_CONFIG_NR (9) ///< The IOCTL NR definition, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR (10) ///< The IOCTL NR definition, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR (12) ///< The IOCTL NR definition, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR ++#define IOCTL_SCLDMA_MAX_NR (13) ///< The Max IOCTL NR for scldma driver ++ ++// use 'm' as magic number ++#define IOCTL_SCLDMA_MAGIC ('2') ///< The Type definition of IOCTL for scldma driver ++ ++/** ++* Used to set parameters of in buffer configurate ,buffer address and number,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_R device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set parameters of out buffer configurate,buffer address and number ,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_W device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_R device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_W device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to peek queue information and set read flag , use ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG. ++*/ ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR) ++/** ++* Used to get mutiinst parameters of private id configurate ,use ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of lock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_LOCK_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of unlock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_SCLDMA_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_VERSION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR) ++/** ++* Used to get DMA information, use ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR) ++ ++#endif // ++ ++/** @} */ // end of scldma_group +diff --git a/drivers/sstar/include/mdrv_scldma_io_i3_st.h b/drivers/sstar/include/mdrv_scldma_io_i3_st.h +new file mode 100755 +index 000000000000..a112036d0a5e +--- /dev/null ++++ b/drivers/sstar/include/mdrv_scldma_io_i3_st.h +@@ -0,0 +1,257 @@ ++/* ++* mdrv_scldma_io_i3_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup scldma_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_ST_H ++#define _MDRV_SCLDMA_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++//1.0.1:for clean scldma. ++//1.1.1:for add buffer queue handler and swring mode. ++//1.1.3:refine for 1.1.1 scl test OK,stabilize not yet. ++#define IOCTL_SCLDMA_VERSION 0x0113 ///< H:Major L:minor H3:Many Change H2:adjust Struct L1:add struct L0:adjust driver ++#define IOCTL_SCLDMA_BUFFER_QUEUE_OFFSET sizeof(ST_IOCTL_SCLDMA_FRAME_BUFFER_CONFIG)/// ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup scldma_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_ST_H ++#define _MDRV_SCLDMA_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++//1.0.1:for clean scldma. ++//1.1.1:for add buffer queue handler and swring mode. ++//1.1.3:refine for 1.1.1 scl test OK,stabilize not yet. ++#define IOCTL_SCLDMA_VERSION 0x0113 ///< H:Major L:minor H3:Many Change H2:adjust Struct L1:add struct L0:adjust driver ++#define IOCTL_SCLDMA_BUFFER_QUEUE_OFFSET sizeof(ST_IOCTL_SCLDMA_FRAME_BUFFER_CONFIG)/// ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * mdrv_sound_io.h ++ * ++ * Created on: Jul 12, 2016 ++ * Author: trevor.wu ++ */ ++ ++#ifndef MDRV_SOUND_IO_H_ ++#define MDRV_SOUND_IO_H_ ++ ++ ++#define AUDIO_IOCTL_MAGIC 'S' ++ ++#define MDRV_SOUND_STARTTIME_READ _IOR(AUDIO_IOCTL_MAGIC, 0, unsigned long long) ++ ++#define IOCTL_AUDIO_MAXNR 0 ++ ++#endif /* MDRV_SOUND_IO_H_ */ +diff --git a/drivers/sstar/include/mdrv_swtoe.h b/drivers/sstar/include/mdrv_swtoe.h +new file mode 100755 +index 000000000000..61ddbfaa5a8e +--- /dev/null ++++ b/drivers/sstar/include/mdrv_swtoe.h +@@ -0,0 +1,129 @@ ++/* ++* mdrv_swtoe.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_SWTOE_H_ ++#define _MDRV_SWTOE_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ char* buf; ++ int buf_size; ++ char* data; ++ int data_size; ++ int offset; ++} drv_swtoe_rx_data; ++ ++typedef struct ++{ ++ u32 saddr; ++ u32 daddr; ++ u16 sport; ++ u16 dport; ++ u32 blk : 1; ++ u32 reserved : 31; ++} __attribute__ ((packed)) drv_swtoe_glue_cnx_data; ++ ++#define drv_swtoe_lstn_data drv_swtoe_glue_cnx_data ++ ++#if 0 ++typedef struct ++{ ++ drv_swtoe_glue_cnx_data lstn_data; ++ // struct sock* newsk; ++} drv_swtoe_lstn_data; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++/* ++ * serv : service for network transreciv ++ * cnx : connection ++ * prot : protocol ++ * DRV_SWTOE_PROT_BYPASS : bypass ++ * DRV_SWTOE_PROT_TCP : TCP ++ * DRV_SWTOE_PROT_UDP : UDP ++ * 3 : reserved ++ * q : queue ++ * tgt : target ++ * req : request ++int drv_swtoe_cnx_txq_create(int serv_id, int prot); ++ * en : enable ++*/ ++ ++#define DRV_SWTOE_PROT_BYPASS 0x00 ++#define DRV_SWTOE_PROT_TCP 0x01 ++#define DRV_SWTOE_PROT_UDP 0x02 ++ ++#define DRV_SWTOE_CNX_INVALID (0x7FF) ++int drv_swtoe_create(int prot, int* cnx_id); ++int drv_swtoe_clone(int cnx_id, int* new_cnx_id, drv_swtoe_lstn_data* plstn_data); ++ ++int drv_swtoe_bind(int cnx_id, struct sockaddr* addr); ++int drv_swtoe_bind_status(int cnx_id); ++ ++int drv_swtoe_lstn_start(int cnx_id, int backlog); ++int drv_swtoe_lstn_stop(int cnx_id); ++int drv_swtoe_lstn_empty(int cnx_id); ++int drv_swtoe_lstn_remove(int cnx_id, drv_swtoe_lstn_data* plstn_data); ++int drv_swtoe_lstn_clr(int cnx_id); ++ ++int drv_swtoe_acpt(int cnx_id, int cnx_id_new); ++ ++int drv_swtoe_shutdown(int cnx_id); ++int drv_swtoe_close(int cnx_id); ++int drv_swtoe_connect(int cnx_id, struct sockaddr* addr, int blk); ++// int drv_swtoe_connect_timeo(int cnx_id, int timeo); ++int drv_swtoe_disconnect(int cnx_id); ++ ++int drv_swtoe_rx_data_get(int cnx_id, drv_swtoe_rx_data* from, drv_swtoe_rx_data** pp_rx_data); ++int drv_swtoe_rx_data_free(int cnx_id, drv_swtoe_rx_data* p_rx_data, int free); ++int drv_swtoe_rx_data_avail(int cnx_id); ++ ++#define SWTOE_TX_SEND_SKB 0x00 ++#define SWTOE_TX_SEND_PAGE 0x01 ++#define SWTOE_TX_SEND_IOV 0x02 ++int drv_swtoe_tx_send(int cnx_id, void* p, int size, int offset, int data_cat); ++int drv_swtoe_tx_avail(int cnx_id, int n); ++int drv_swtoe_tx_pump(int cnx_id); ++ ++typedef int (*drv_swtoe_cb_func_t)(int cnx, int reason, void* reason_data, void* cb_data); ++ ++#define DRV_SWTOE_GLUE_TCOM 0x10000001 ++#define DRV_SWTOE_GLUE_RCOM 0x20000001 ++#define DRV_SWTOE_GLUE_CNX_OK 0x30000001 ++#define DRV_SWTOE_GLUE_CNX_FAIL 0x30000002 ++#define DRV_SWTOE_GLUE_CLS_RESP 0x30000003 ++#define DRV_SWTOE_GLUE_LSTN_RESP 0x30000004 ++ ++int drv_swtoe_glue_req(int cnx_id, drv_swtoe_cb_func_t cb, void* cb_data); ++int drv_swtoe_glue_en(int cnx_id, int mask, int bEn); ++ ++#endif // _MDRV_SWTOE_H_ ++ +diff --git a/drivers/sstar/include/mdrv_system.h b/drivers/sstar/include/mdrv_system.h +new file mode 100755 +index 000000000000..1d440dad7b34 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_system.h +@@ -0,0 +1,276 @@ ++/* ++* mdrv_system.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "../include/mdrv_system_st.h" ++#include "mst_platform.h" ++ ++#ifndef _DRV_SYSTEM_H_ ++#define _DRV_SYSTEM_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define SYS_BOARD_NAME_MAX 32 ///< Maximum length of board name ++#define SYS_PLATFORM_NAME_MAX 32 ///< Maximum length of playform name ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++/// System output pad switch type ++typedef enum ++{ ++ E_SYS_PAD_MSD5010_SM2_IIC2, ///< 5010 SM2, IIC2 ++ E_SYS_PAD_MSD5011_SM2_IIC2, ///< 5011 SM2, IIC2 ++ E_SYS_PAD_MSD5015_GPIO, ///< 5015 GPIO ++ E_SYS_PAD_MSD5018_SM2, ///< 5018 SM2 ++} SYS_PadType; ++ ++/// System information ++typedef struct ++{ ++ /// Software information ++ struct ++ { ++ U8 Board[SYS_BOARD_NAME_MAX]; ///< Board name ++ U8 Platform[SYS_PLATFORM_NAME_MAX]; ///< Platform name ++ } SWLib; ++} SYS_Info; ++ ++/// Memory mapping type ++typedef enum ++{ ++ E_SYS_MMAP_LINUX_BASE, //0 ++ E_SYS_MMAP_BIN_MEM, //1 ++ E_SYS_MMAP_MAD_BASE, //2 ++ E_SYS_MMAP_SCALER_DNR_BUF, //3 ++ E_SYS_MMAP_RLD_BUF, //4 ++ E_SYS_MMAP_MVD_SW, //5 ++ E_SYS_MMAP_VD_3DCOMB, //6 ++ E_SYS_MMAP_VE, //7 ++ E_SYS_MMAP_TTX_BUF, //8 ++ E_SYS_MMAP_MPOOL, //9 ++ E_SYS_MMAP_EMAC_MEM, //10 ++ E_SYS_MMAP_LINUX_MEM, //11 ++ E_SYS_MMAP_SVD, //12 ++ E_SYS_MMAP_SVD_ALL, //13 ++ E_SYS_MMAP_MVD_FB, //14 ++ E_SYS_MMAP_MVD_BS, //15 ++ E_SYS_MMAP_POSD0_MEM, //16 ++ E_SYS_MMAP_POSD1_MEM, //17 ++ E_SYS_MMAP_TSP, // samuel, 20081107 //18 ++ E_SYS_MMAP_AUDIO_CLIP_MEM, // samuel, 20081107 //19 ++ E_SYS_MMAP_MBOX_SHM, //20 ++ E_SYS_MMAP_CHAKRA_SUBSYSTEM, //21 ++ E_SYS_MMAP_CHAKRA_FW, //22 ++#ifdef CONFIG_MSTAR_KIP ++ E_SYS_MMAP_AEON_SHM, // 23 ++#endif ++ E_SYS_MMAP_NUMBER, //23 ++ ++} SYS_Memory_Mapping; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++BOOL MDrv_System_Init(void); ++//BOOL MDrv_System_SwitchPad(SYS_PadType ePadType); ++void MDrv_System_WDTEnable(BOOL bEnable); ++void MDrv_System_WDTClear(void); ++BOOL MDrv_System_WDTLastStatus(void); ++void MDrv_System_WDTSetTime(U32 u32Ms); ++void MDrv_System_ResetChip(void); ++void MDrv_System_ResetCPU(void); ++ ++ ++PMST_PANEL_INFO_t MDrv_SYS_GetPanelInfo(void); ++ ++void MDrv_SYS_PowerDown(int src); ++void MDrv_SYS_PD_ADC_R(B16 bStatus); ++void MDrv_SYS_PD_ADC_G(B16 bStatus); ++void MDrv_SYS_PD_ADC_B(B16 bStatus); ++void MDrv_SYS_PD_ADC_Y(B16 bStatus); ++void MDrv_SYS_PD_GMC_P(B16 bStatus); ++void MDrv_SYS_PD_GMC_Y(B16 bStatus); ++void MDrv_SYS_PD_GMC_C(B16 bStatus); ++void MDrv_SYS_PD_CVBS_Buffer(B16 bStatus); ++void MDrv_SYS_PD_DAC_CVBS(B16 bStatus); ++void MDrv_SYS_PD_DAC(B16 bStatus); ++void MDrv_SYS_PD_FB_DAC(B16 bStatus); ++void MDrv_SYS_PD_DAC_RGB(B16 bStatus); ++void MDrv_SYS_PD_Audio(B16 bStatus); ++void MDrv_SYS_PD_LVDS(B16 bStatus); ++void MDrv_SYS_PD_VD(B16 bStatus); ++void MDrv_SYS_PD_SVD(B16 bStatus); ++void MDrv_SYS_PD_MVD_M4V(B16 bStatus); ++void MDrv_SYS_PD_TSP(B16 bStatus); ++void MDrv_SYS_PD_VE(B16 bStatus); ++void MDrv_SYS_PD_RVD(B16 bStatus); ++void MDrv_SYS_PD_STRLD(B16 bStatus); ++void MDrv_SYS_PD_AEON(B16 bStatus); ++void MDrv_SYS_PD_GOPG2(B16 bStatus); ++ ++ ++#ifdef CONFIG_MSTAR_SPI_FLASH ++U32 MDrv_SYS_SPI_READ(U32 arg); ++U32 MDrv_SYS_SPI_WRITE(U32 arg); ++U32 MDrv_SYS_SPI_ERASE(U32 arg); ++U32 MDrv_SYS_SPI_ERASE_SECTOR(U32 arg); ++U32 MDrv_SYS_SPI_SIZE_DETECT(U32 arg); ++U32 MDrv_SYS_SPI_READ_STATUS(U32 arg); ++U32 MDrv_SYS_SPI_WRITE_STATUS(U32 arg); ++U32 MDrv_SYS_SPI_INIT(void); ++U32 MDrv_SYS_SPI_WRITE_PROTECT(U32 arg); ++U32 MDrv_SYS_SPI_ERASE_ALL(void); ++U32 MDrv_SYS_SPI_GetFlash_INFO(U32 arg); ++#endif ++ ++ ++unsigned int MDrv_SYS_GetDRAMLength(void); ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++extern int MDrv_SYS_GetMMAP(int type, unsigned int *addr, unsigned int *len); ++#elif defined(CONFIG_ARM64) ++extern int MDrv_SYS_GetMMAP(int type, u64 *addr, u64 *len); ++#endif ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++ ++U32 MDrv_SYS_SetPanelInfo(U32 arg); ++void MDrv_SYS_GetPanelRes(U32 arg); ++void MDrv_SYS_GetPanelHStart(U32 argv); ++void MDrv_SYS_GetGFXGOPPipelineDelay(U32 argv); ++ ++void MDrv_SYS_ReadGeneralRegister(U32 arg); ++void MDrv_SYS_WriteGeneralRegister(U32 arg); ++void MDrv_SYS_LoadAeon(U32 arg); ++void MDrv_SYS_ResetAeon(U32 arg); ++void MDrv_SYS_EnableAeon(void); ++void MDrv_SYS_DumpAeonMessage(void); ++void MDrv_SYS_DisableAeon(void); ++void MDrv_SYS_SwitchUart(U32 arg); ++U32 MDrv_SYS_IsAeonEnable(U32 arg); ++ ++void MDrv_SYS_SetNexusPID(U32 argv); ++void MDrv_SYS_GetNexusPID(U32 argv); ++ ++U32 MDrv_SYS_PCMCIA_WRITE(U32 arg, BOOL bFromUser); ++U32 MDrv_SYS_PCMCIA_READ(U32 arg, BOOL bFromUser); ++U32 MDrv_SYS_PCMCIA_READ_DATA(U32 arg, BOOL bFromUser); ++//U32 MDrv_SYS_PCMCIA_WRITE_DATA(U32 arg, BOOL bFromUser); ++ ++void MDrv_SYS_GetMBoxShareMemory(U32 argv); ++ ++void MDrv_SYS_GetMsBinInfo(U32 argv); ++void MDrv_SYS_GetMIU1Base(U32 argv); ++void MDrv_SYS_GetMIU1BusBase(U32 argv); ++void MDrv_SYS_ForceUpgradeOADByDRAM(U32 arg); ++void MDrv_SYS_ForceUpgradeENVByDRAM(U32 arg); ++void MDrv_SYS_PrintMsg(U32 arg); ++ ++U32 MDrv_SYS_GetRawUART(U32 arg); ++void MDrv_SYS_ReloadAeon( U32 arg ) ; ++U32 MDrv_SYS_Timer(U32 arg) ; ++U32 MDrv_SYS_RegOP(U32 arg); ++extern void MDrv_SYS_MMAP_Dump( void ) ; ++U32 MDrv_SYS_HotelMode(U32 arg) ; ++U32 MDrv_SYS_HotelModePrintf(U32 arg) ; ++ ++void MDrv_SYS_ChangeUart( U32 arg ); ++ ++void MDrv_SYS_SetGFXGOPIndex(U32 argv); ++void MDrv_SYS_GetGFXGOPIndex(U32 argv); ++ ++void MDrv_SYS_SetDisplayControllerSeparated(U32 argv); ++U32 MDrv_SYS_GetDisplayControllerSeparated(void); ++void MDrv_SYS_IsDisplayControllerSeparated(U32 argv); ++ ++void MDrv_SYS_SetNexus(U32 argv); ++void MDrv_SYS_HasNexus(U32 argv); ++ ++ ++U32 MDrv_SYS_SPI_LOAD(U32 arg); //20100120 Terry, SPI Load Code ++ ++#elif defined(CONFIG_ARM64) ++ ++U32 MDrv_SYS_SetPanelInfo(unsigned long arg); ++void MDrv_SYS_GetPanelRes(unsigned long arg); ++void MDrv_SYS_GetPanelHStart(unsigned long argv); ++void MDrv_SYS_GetGFXGOPPipelineDelay(unsigned long argv); ++ ++void MDrv_SYS_ReadGeneralRegister(unsigned long arg); ++void MDrv_SYS_WriteGeneralRegister(unsigned long arg); ++void MDrv_SYS_LoadAeon(unsigned long arg); ++void MDrv_SYS_ResetAeon(unsigned long arg); ++void MDrv_SYS_EnableAeon(void); ++void MDrv_SYS_DumpAeonMessage(void); ++void MDrv_SYS_DisableAeon(void); ++void MDrv_SYS_SwitchUart(unsigned long arg); ++U32 MDrv_SYS_IsAeonEnable(unsigned long arg); ++ ++void MDrv_SYS_SetNexusPID(unsigned long argv); ++void MDrv_SYS_GetNexusPID(unsigned long argv); ++ ++U32 MDrv_SYS_PCMCIA_WRITE(unsigned long arg, BOOL bFromUser); ++U32 MDrv_SYS_PCMCIA_READ(unsigned long arg, BOOL bFromUser); ++U32 MDrv_SYS_PCMCIA_READ_DATA(unsigned long arg, BOOL bFromUser); ++//U32 MDrv_SYS_PCMCIA_WRITE_DATA(unsigned long arg); ++ ++void MDrv_SYS_GetMBoxShareMemory(unsigned long argv); ++ ++void MDrv_SYS_GetMsBinInfo(unsigned long argv); ++void MDrv_SYS_GetMIU1Base(unsigned long argv); ++void MDrv_SYS_GetMIU1BusBase(unsigned long argv); ++void MDrv_SYS_ForceUpgradeOADByDRAM(unsigned long arg); ++void MDrv_SYS_ForceUpgradeENVByDRAM(unsigned long arg); ++void MDrv_SYS_PrintMsg(unsigned long arg); ++ ++U32 MDrv_SYS_GetRawUART(unsigned long arg); ++void MDrv_SYS_ReloadAeon(unsigned long arg ) ; ++U32 MDrv_SYS_Timer(unsigned long arg) ; ++U32 MDrv_SYS_RegOP(unsigned long arg); ++extern void MDrv_SYS_MMAP_Dump( void ) ; ++U32 MDrv_SYS_HotelMode(unsigned long arg) ; ++U32 MDrv_SYS_HotelModePrintf(unsigned long arg) ; ++ ++void MDrv_SYS_ChangeUart(unsigned long arg ); ++ ++void MDrv_SYS_SetGFXGOPIndex(unsigned long argv); ++void MDrv_SYS_GetGFXGOPIndex(unsigned long argv); ++ ++void MDrv_SYS_SetDisplayControllerSeparated(unsigned long argv); ++U32 MDrv_SYS_GetDisplayControllerSeparated(void); ++void MDrv_SYS_IsDisplayControllerSeparated(unsigned long argv); ++ ++void MDrv_SYS_SetNexus(unsigned long argv); ++void MDrv_SYS_HasNexus(unsigned long argv); ++ ++ ++U32 MDrv_SYS_SPI_LOAD(unsigned long arg); //20100120 Terry, SPI Load Code ++ ++#endif ++ ++void MDrv_SYS_ReadMemory(void); ++void MDrv_SYS_FlushMemory(void); ++ ++unsigned int MDrv_SYS_GetPowerStates(void); ++unsigned int MDrv_SYS_GetGPIOIR(void); ++unsigned int MDrv_SYS_GetGPIOIRType(void); ++ ++#endif // _DRV_SYSTEM_H_ +diff --git a/drivers/sstar/include/mdrv_system_st.h b/drivers/sstar/include/mdrv_system_st.h +new file mode 100755 +index 000000000000..c07c3c7a8aae +--- /dev/null ++++ b/drivers/sstar/include/mdrv_system_st.h +@@ -0,0 +1,302 @@ ++/* ++* mdrv_system_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __DRV_SYSTEM_ST_H__ ++#define __DRV_SYSTEM_ST_H__ ++ ++#ifdef CONFIG_COMPAT ++#include ++#endif ++//------------------------------------------------------------------------------ ++// Data structure ++//------------------------------------------------------------------------------ ++typedef struct IO_SYS_PANEL_INFO_s ++{ ++ U32* pPanelInfo; ++ U16 u16Len; ++} IO_SYS_PANEL_INFO_t, *PIO_SYS_PANEL_INFO_t; ++ ++typedef struct IO_SYS_PANEL_Res_s ++{ ++ U16 u16Width; ++ U16 u16Height; ++} IO_SYS_PANEL_GET_RES_t, *PIO_SYS_PANEL_GET_RES_t; ++ ++typedef struct IO_SYS_BOARD_INFO_s ++{ ++ U32* pu32BoardInfo; ++ U16 u16Len; ++} IO_SYS_BOARD_INFO_t, *PIO_SYS_BOARD_INFO_t; ++ ++typedef struct IO_SYS_GENERAL_REG_s ++{ ++ U16 u16Reg; ++ U8 u8Value; ++} IO_SYS_GENERAL_REG_t; ++ ++typedef struct IO_SYS_AEONBIN_INFO_s ++{ ++ U8* pu8AeonStart; ++ U32 u32Len; ++ BOOL bRet; ++} IO_SYS_AEONBIN_INFO_t; ++ ++/* PCMCIA_MAP_IOC_INFO */ ++typedef struct ++{ ++ U16 u16Addr; ++ U8 u8Value; ++ U8 u8Type; // 1: AttribMem, 2: IOMem ++ U16 u16DataLen; ++ U8 * u8pReadBuffer; ++ U8 * u8pWriteBuffer; ++} PCMCIA_Map_Info_t; ++#ifdef CONFIG_COMPAT ++typedef struct ++{ ++ U16 u16Addr; ++ U8 u8Value; ++ U8 u8Type; // 1: AttribMem, 2: IOMem ++ U16 u16DataLen; ++ compat_uptr_t u8pReadBuffer; ++ compat_uptr_t u8pWriteBuffer; ++} COMPAT_PCMCIA_Map_Info_t; ++#endif ++ ++typedef enum ++{ ++ RELOAD_AEON_STOP, ++ RELOAD_AEON_RESTART ++} AEON_CONTROL ; ++ ++typedef enum ++{ ++ // Analog port ++ INPUT_SRC_VGA, ++ INPUT_SRC_YPBPR_1, ++ INPUT_SRC_YPBPR_2, ++ ++ // Digital port ++ INPUT_SRC_ATV, ++ INPUT_SRC_CVBS_1, ++ INPUT_SRC_CVBS_2, ++ INPUT_SRC_CVBS_3, ++ ++ INPUT_SRC_SVIDEO_1, ++ INPUT_SRC_SVIDEO_2, ++ ++ INPUT_SRC_SCART_1, ++ INPUT_SRC_SCART_2, ++ ++ // HDMI port ++ INPUT_SRC_HDMI_A, ++#if 1 ++ INPUT_SRC_HDMI_B, ++#else ++ INPUT_SRC_HDMI_B1, ++ INPUT_SRC_HDMI_B2, ++ INPUT_SRC_HDMI_B3, ++#endif ++ INPUT_SRC_HDMI_C, ++ ++ // MVD port ++ INPUT_SRC_DTV, ++ INPUT_SRC_DTV_MLINK, ++ ++ INPUT_SRC_STORAGE, ///< input source is Storage ++ ++ INPUT_SRC_NUM, ++ INPUT_SRC_NONE = INPUT_SRC_NUM ++} SYS_INPUT_SOURCE_e; ++ ++ ++typedef struct IO_SYS_SPI_s ++{ ++ U32 u32Start; ++ U32 u32Len; ++ U8 *u8data; ++} IO_SYS_SPI_t; ++ ++typedef struct IO_SYS_SPI_ERASE_s ++{ ++ U32 u32StartAddr; ++ U32 u32Size; ++ BOOL bWait; ++} IO_SYS_SPI_ERASE_t; ++ ++typedef struct IO_SYS_SPI_ERASE_SECTOR_s ++{ ++ U32 u32StartAddr; ++ U32 u32EndAddr; ++} IO_SYS_SPI_ERASE_SECTOR_t; ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++#ifdef CONFIG_MP_NEW_UTOPIA_32BIT ++typedef struct ++{ ++ u64 LX_MEM_ADDR; ++ u64 LX_MEM_LENGTH; ++ u64 LX_MEM2_ADDR; ++ u64 LX_MEM2_LENGTH; ++ u64 EMAC_ADDR; ++ u64 EMAC_LENGTH; ++ u64 DRAM_ADDR; ++ u64 DRAM_LENGTH; ++ u64 BB_ADDR; ++ u64 BB_LENGTH; ++ u64 MPOOL_MEM_ADDR; ++ u64 MPOOL_MEM_LENGTH; ++ u64 G3D_MEM0_ADDR; ++ u64 G3D_MEM0_LENGTH; ++ u64 G3D_MEM1_ADDR; ++ u64 G3D_MEM1_LENGTH; ++ u64 G3D_CMDQ_ADDR; ++ u64 G3D_CMDQ_LENGTH; ++} IO_Sys_Info_t; ++ ++typedef struct ++{ ++ u64 LX_MEM_ADDR; ++ u64 LX_MEM_LENGTH; ++ u64 LX_MEM2_ADDR; ++ u64 LX_MEM2_LENGTH; ++ u64 LX_MEM3_ADDR; ++ u64 LX_MEM3_LENGTH; ++ u64 LX_MEM4_ADDR; ++ u64 LX_MEM4_LENGTH; ++ u64 LX_MEM5_ADDR; ++ u64 LX_MEM5_LENGTH; ++ u64 EMAC_ADDR; ++ u64 EMAC_LENGTH; ++ u64 DRAM_ADDR; ++ u64 DRAM_LENGTH; ++ u64 BB_ADDR; ++ u64 BB_LENGTH; ++ u64 MPOOL_MEM_ADDR; ++ u64 MPOOL_MEM_LENGTH; ++ u64 G3D_MEM0_ADDR; ++ u64 G3D_MEM0_LENGTH; ++ u64 G3D_MEM1_ADDR; ++ u64 G3D_MEM1_LENGTH; ++ u64 G3D_CMDQ_ADDR; ++ u64 G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t_EX; ++#else ++typedef struct ++{ ++ unsigned int LX_MEM_ADDR; ++ unsigned int LX_MEM_LENGTH; ++ unsigned int LX_MEM2_ADDR; ++ unsigned int LX_MEM2_LENGTH; ++ unsigned int EMAC_ADDR; ++ unsigned int EMAC_LENGTH; ++ unsigned int DRAM_ADDR; ++ unsigned int DRAM_LENGTH; ++ unsigned int BB_ADDR; ++ unsigned int BB_LENGTH; ++ unsigned int MPOOL_MEM_ADDR; ++ unsigned int MPOOL_MEM_LENGTH; ++ unsigned int G3D_MEM0_ADDR; ++ unsigned int G3D_MEM0_LENGTH; ++ unsigned int G3D_MEM1_ADDR; ++ unsigned int G3D_MEM1_LENGTH; ++ unsigned int G3D_CMDQ_ADDR; ++ unsigned int G3D_CMDQ_LENGTH; ++} IO_Sys_Info_t; ++ ++typedef struct ++{ ++ unsigned int LX_MEM_ADDR; ++ unsigned int LX_MEM_LENGTH; ++ unsigned int LX_MEM2_ADDR; ++ unsigned int LX_MEM2_LENGTH; ++ unsigned int LX_MEM3_ADDR; ++ unsigned int LX_MEM3_LENGTH; ++ unsigned int LX_MEM4_ADDR; ++ unsigned int LX_MEM4_LENGTH; ++ unsigned int LX_MEM5_ADDR; ++ unsigned int LX_MEM5_LENGTH; ++ unsigned int EMAC_ADDR; ++ unsigned int EMAC_LENGTH; ++ unsigned int DRAM_ADDR; ++ unsigned int DRAM_LENGTH; ++ unsigned int BB_ADDR; ++ unsigned int BB_LENGTH; ++ unsigned int MPOOL_MEM_ADDR; ++ unsigned int MPOOL_MEM_LENGTH; ++ unsigned int G3D_MEM0_ADDR; ++ unsigned int G3D_MEM0_LENGTH; ++ unsigned int G3D_MEM1_ADDR; ++ unsigned int G3D_MEM1_LENGTH; ++ unsigned int G3D_CMDQ_ADDR; ++ unsigned int G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t_EX; ++#endif //CONFIG_MP_NEW_UTOPIA_32BIT ++#elif defined(CONFIG_ARM64) ++typedef struct ++{ ++ u64 LX_MEM_ADDR; ++ u64 LX_MEM_LENGTH; ++ u64 LX_MEM2_ADDR; ++ u64 LX_MEM2_LENGTH; ++ u64 EMAC_ADDR; ++ u64 EMAC_LENGTH; ++ u64 DRAM_ADDR; ++ u64 DRAM_LENGTH; ++ u64 BB_ADDR; ++ u64 BB_LENGTH; ++ u64 MPOOL_MEM_ADDR; ++ u64 MPOOL_MEM_LENGTH; ++ u64 G3D_MEM0_ADDR; ++ u64 G3D_MEM0_LENGTH; ++ u64 G3D_MEM1_ADDR; ++ u64 G3D_MEM1_LENGTH; ++ u64 G3D_CMDQ_ADDR; ++ u64 G3D_CMDQ_LENGTH; ++} IO_Sys_Info_t; ++ ++typedef struct ++{ ++ u64 LX_MEM_ADDR; ++ u64 LX_MEM_LENGTH; ++ u64 LX_MEM2_ADDR; ++ u64 LX_MEM2_LENGTH; ++ u64 LX_MEM3_ADDR; ++ u64 LX_MEM3_LENGTH; ++ u64 LX_MEM4_ADDR; ++ u64 LX_MEM4_LENGTH; ++ u64 LX_MEM5_ADDR; ++ u64 LX_MEM5_LENGTH; ++ u64 EMAC_ADDR; ++ u64 EMAC_LENGTH; ++ u64 DRAM_ADDR; ++ u64 DRAM_LENGTH; ++ u64 BB_ADDR; ++ u64 BB_LENGTH; ++ u64 MPOOL_MEM_ADDR; ++ u64 MPOOL_MEM_LENGTH; ++ u64 G3D_MEM0_ADDR; ++ u64 G3D_MEM0_LENGTH; ++ u64 G3D_MEM1_ADDR; ++ u64 G3D_MEM1_LENGTH; ++ u64 G3D_CMDQ_ADDR; ++ u64 G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t_EX; ++ ++#endif ++ ++#endif // __DRV_SYSTEM_ST_H__ ++ +diff --git a/drivers/sstar/include/mdrv_types.h b/drivers/sstar/include/mdrv_types.h +new file mode 100755 +index 000000000000..aceb7081c12f +--- /dev/null ++++ b/drivers/sstar/include/mdrv_types.h +@@ -0,0 +1,115 @@ ++/* ++* mdrv_types.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_TYPE_H__ ++#define __MDRV_TYPE_H__ ++ ++#define U8 unsigned char // 1 byte ++#define U16 unsigned short // 2 byte ++#define U32 unsigned int // 4 byte ++#define U64 unsigned long long // 8 byte ++ ++#define S8 signed char // 1 byte ++#define S16 signed short // 2 byte ++#define S32 signed int // 4 byte ++#define S64 signed long long // 4 byte ++ ++#define B16 unsigned short // 2 byte ++#define BOOL unsigned int // 4 byte ++ ++#define BOOLEAN BOOL ++#define WORD U16 ++#define BYTE U8 ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++ ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if !defined(ENABLE) && !defined(DISABLE) ++/// definition for ENABLE ++#define ENABLE 1 ++/// definition for DISABLE ++#define DISABLE 0 ++#endif ++ ++ ++#if !defined(ON) && !defined(OFF) ++/// definition for ON ++#define ON 1 ++/// definition for OFF ++#define OFF 0 ++#endif ++ ++/// @name BIT# ++/// definition of one bit mask ++/// @{ ++#if !defined(BIT0) && !defined(BIT1) ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++#endif ++/// @} ++#endif // ++ +diff --git a/drivers/sstar/include/mdrv_verchk.h b/drivers/sstar/include/mdrv_verchk.h +new file mode 100755 +index 000000000000..c696a99e87f0 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_verchk.h +@@ -0,0 +1,101 @@ ++/* ++* mdrv_verchk.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_VERCHK_H ++#define _MDRV_VERCHK_H ++ ++ ++//---------------------------------------------------------------------------------- ++// define & Macro ++//---------------------------------------------------------------------------------- ++#define VERCHK_HEADER 0x4D530000 ++#define VERCHK_HADER_MASK 0xFFFF0000 ++#define VERCHK_VERSION_MASK 0x0000FFFF ++#define VERCHK_MAJORVERSION_MASK 0x0000FF00 ++ ++#define FILL_VERCHK_TYPE(var, var_ver, var_size, version) \ ++({ \ ++ var_ver = (VERCHK_HEADER | (version & VERCHK_VERSION_MASK)); \ ++ var_size = sizeof(var); \ ++ var; \ ++}) ++ ++ ++#define CHK_VERCHK_HEADER(pvar) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ ((*p & VERCHK_HADER_MASK) == VERCHK_HEADER) ? 1 : 0; \ ++}) ++ ++ ++#define CHK_VERCHK_VERSION_EQU(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) == v) ? 1 : 0; \ ++}) ++ ++#define CHK_VERCHK_VERSION_LESS(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) < v) ? 1 : 0; \ ++}) ++ ++#define CHK_VERCHK_MAJORVERSION_LESS(pvar, v) \ ++ ({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ ((*p & VERCHK_MAJORVERSION_MASK) < (v& VERCHK_MAJORVERSION_MASK)) ? 1 : 0; \ ++ }) ++ ++#define CHK_VERCHK_VERSION_GREATER(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) > v) ? 1 : 0; \ ++}) ++ ++ ++#define CHK_VERCHK_VERSION_LESS_EQU(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) <= v) ? 1 : 0; \ ++}) ++ ++#define CHK_VERCHK_VERSION_GREATER_EQU(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) >= v) ? 1 : 0; \ ++}) ++ ++ ++#define CHK_VERCHK_SIZE(pvar,s) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ (*p == s ) ? 1 : 0; \ ++}) ++ ++ ++#define VERCHK_ERR(_fmt, _args...) \ ++ do \ ++ { \ ++ printk(KERN_WARNING _fmt, ## _args); \ ++ }while(0); ++ ++#endif +diff --git a/drivers/sstar/include/mdrv_video.h b/drivers/sstar/include/mdrv_video.h +new file mode 100755 +index 000000000000..49ad8808fffe +--- /dev/null ++++ b/drivers/sstar/include/mdrv_video.h +@@ -0,0 +1,55 @@ ++/* ++* mdrv_video.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MDRV_VIDEO_H_ ++#define _MDRV_VIDEO_H_ ++ ++/* ++ * NOTE: ++ * This is old version naming of MFE driver. It wiil be deprecated in the future. ++ * ++ */ ++ ++/* definition of structures */ ++ ++#ifndef _MDRV_MMFE_IO_H_ ++ ++#include ++ ++#endif//_MDRV_MMFE_IO_H_ ++ ++typedef mmfe_reqbuf mvideo_reqbuf; ++typedef mmfe_buffer mvideo_buffer; ++typedef mmfe_params mvideo_params; ++typedef mmfe_control mvideo_control; ++ ++/* definition of ioctl codes */ ++ ++#define MVIDIOC_S_PARM IOCTL_MFE_S_PARM ++#define MVIDIOC_G_PARM IOCTL_MFE_G_PARM ++#define MVIDIOC_S_CTRL IOCTL_MFE_S_CTRL ++#define MVIDIOC_G_CTRL IOCTL_MFE_G_CTRL ++#define MVIDIOC_STREAMON IOCTL_MFE_STREAMON ++#define MVIDIOC_STREAMOFF IOCTL_MFE_STREAMOFF ++#define MVIDIOC_REQBUF IOCTL_MFE_REQBUF ++#define MVIDIOC_S_PICT IOCTL_MFE_S_PICT ++#define MVIDIOC_G_BITS IOCTL_MFE_G_BITS ++#define MVIDIOC_FLUSH IOCTL_MFE_FLUSH ++ ++#endif//_MDRV_VIDEO_H_ ++ +diff --git a/drivers/sstar/include/mdrv_vip_io.h b/drivers/sstar/include/mdrv_vip_io.h +new file mode 100755 +index 000000000000..edd80d160c9c +--- /dev/null ++++ b/drivers/sstar/include/mdrv_vip_io.h +@@ -0,0 +1,185 @@ ++/* ++* mdrv_vip_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/** ++ * \defgroup vip_group VIP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mvip1.0/bypass ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: W:echo 1 open bypass ,echo 0 close. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckPQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 PQ already setting check , echo 2 Auto test PQ ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckCMDQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 CMDQ already setting check , echo 2 Auto test CMDQ ++ * ++ * @{ ++ */ ++#ifndef _MDRV_VIP_IO_H ++#define _MDRV_VIP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_VIP_SET_DNR_CONFIG_NR (0) ///< The IOCTL NR definition,IOCTL_VIP_SET_DNR_CONFIG ++#define IOCTL_VIP_SET_PEAKING_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_VIP_SET_PEAKING_CONFIG ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR (3) ///< The IOCTL NR definition,IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ++#define IOCTL_VIP_SET_DLC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_CONFIG ++#define IOCTL_VIP_SET_LCE_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_VIP_SET_LCE_CONFIG ++#define IOCTL_VIP_SET_UVC_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_VIP_SET_UVC_CONFIG ++#define IOCTL_VIP_SET_IHC_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_CONFIG ++#define IOCTL_VIP_SET_ICE_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_VIP_SET_ICE_CONFIG ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG ++#define IOCTL_VIP_SET_IBC_CONFIG_NR (11) ///< The IOCTL NR definition,IOCTL_VIP_SET_IBC_CONFIG ++#define IOCTL_VIP_SET_FCC_CONFIG_NR (12) ///< The IOCTL NR definition,IOCTL_VIP_SET_FCC_CONFIG ++#define IOCTL_VIP_SET_VIP_CONFIG_NR (13) ///< The IOCTL NR definition,IOCTL_VIP_SET_VIP_CONFIG ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG_NR (14) ///< The IOCTL NR definition,IOCTL_VIP_CMDQ_WRITE_CONFIG ++#define IOCTL_VIP_SET_LDC_CONFIG_NR (15) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_CONFIG ++#define IOCTL_VIP_SET_LDC_MD_CONFIG_NR (16) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_MD_CONFIG ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR (17) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_DMAP_CONFIG ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR (18) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_SRAM_CONFIG ++#define IOCTL_VIP_SET_ACK_CONFIG_NR (19) ///< The IOCTL NR definition,IOCTL_VIP_SET_ACK_CONFIG ++#define IOCTL_VIP_SET_NLM_CONFIG_NR (20) ///< The IOCTL NR definition,IOCTL_VIP_SET_NLM_CONFIG ++#define IOCTL_VIP_SNR_CONFIG_NR (21) ///< The IOCTL NR definition,IOCTL_VIP_SNR_CONFIG ++#define IOCTL_VIP_SET_VTRACK_CONFIG_NR (22) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_CONFIG ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR (23) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ++#define IOCLT_VIP_GET_VERSION_CONFIG_NR (24) ///< The IOCTL NR definition, IOCLT_VIP_GET_VERSION_CONFIG_NR ++#define IOCLT_VIP_SET_ALLVIP_CONFIG_NR (25) ///< The IOCTL NR for vip driver ++#define IOCTL_VIP_MAX_NR (26) ///< The Max IOCTL NR for vip driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_VIP_MAGIC ('3') ///< The Type definition of IOCTL for vip driver ++/** ++* Used to set CMDQ cmd, use ST_IOCTL_VIP_CMDQ_CONFIG. ++*/ ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_CMDQ_WRITE_CONFIG_NR) ++/** ++* Used to set DNR, use ST_IOCTL_VIP_DNR_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DNR_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DNR_CONFIG_NR) ++/** ++* Used to set LDC, use ST_IOCTL_VIP_LDC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_CONFIG_NR) ++/** ++* Used to set LDC mode, use ST_IOCTL_VIP_LDC_MD_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_MD_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_MD_CONFIG_NR) ++/** ++* Used to set LDC DMAP address, use ST_IOCTL_VIP_LDC_DMAP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR) ++/** ++* Used to set LDC SRAM address, use ST_IOCTL_VIP_LDC_SRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR) ++/** ++* Used to set PK, use ST_IOCTL_VIP_PEAKING_CONFIG. ++*/ ++#define IOCTL_VIP_SET_PEAKING_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_PEAKING_CONFIG_NR) ++/** ++* Used to set DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR) ++/** ++* Used to get DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT. ++*/ ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR) ++/** ++* Used to set DLC, use ST_IOCTL_VIP_DLC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_CONFIG_NR) ++/** ++* Used to set LCE, use ST_IOCTL_VIP_LCE_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LCE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LCE_CONFIG_NR) ++/** ++* Used to set UVC, use ST_IOCTL_VIP_UVC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_UVC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_UVC_CONFIG_NR) ++/** ++* Used to set IHC, use ST_IOCTL_VIP_IHC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_CONFIG_NR) ++/** ++* Used to set ICE, use ST_IOCTL_VIP_ICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ICE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ICE_CONFIG_NR) ++/** ++* Used to set IHCICC, use ST_IOCTL_VIP_IHCICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR) ++/** ++* Used to set IBC, use ST_IOCTL_VIP_IBC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IBC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IBC_CONFIG_NR) ++/** ++* Used to set FCC, use ST_IOCTL_VIP_FCC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_FCC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_FCC_CONFIG_NR) ++/** ++* Used to set ACK, use ST_IOCTL_VIP_ACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ACK_CONFIG_NR) ++/** ++* Used to set NLM, use ST_IOCTL_VIP_NLM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_NLM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_NLM_CONFIG_NR) ++/** ++* Used to set SNR, use ST_IOCTL_VIP_SNR_CONFIG. ++*/ ++#define IOCTL_VIP_SET_SNR_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SNR_CONFIG_NR) ++/** ++* Used to set VIPLB, use ST_IOCTL_VIP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VIP_CONFIG_NR) ++/** ++* Used to set VTRACK, use ST_IOCTL_VIP_VTRACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VTRACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VTRACK_CONFIG_NR) ++/** ++* Used to set VTACK ON, use ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_VIP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_VIP_GET_VERSION_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_GET_VERSION_CONFIG_NR) ++/** ++* Used to set all vip config, use ST_IOCTL_VIP_AllSET_CONFIG. ++*/ ++#define IOCLT_VIP_SET_ALLVIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_SET_ALLVIP_CONFIG_NR) ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/sstar/include/mdrv_vip_io_i3.h b/drivers/sstar/include/mdrv_vip_io_i3.h +new file mode 100755 +index 000000000000..4d88783dfbba +--- /dev/null ++++ b/drivers/sstar/include/mdrv_vip_io_i3.h +@@ -0,0 +1,183 @@ ++/* ++* mdrv_vip_io_i3.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/** ++ * \defgroup vip_group VIP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mvip1.0/bypass ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: W:echo 1 open bypass ,echo 0 close. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckPQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 PQ already setting check , echo 2 Auto test PQ ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckCMDQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 CMDQ already setting check , echo 2 Auto test CMDQ ++ * ++ * @{ ++ */ ++#ifndef _MDRV_VIP_IO_H ++#define _MDRV_VIP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_VIP_SET_PEAKING_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_VIP_SET_PEAKING_CONFIG ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR (3) ///< The IOCTL NR definition,IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ++#define IOCTL_VIP_SET_DLC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_CONFIG ++#define IOCTL_VIP_SET_LCE_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_VIP_SET_LCE_CONFIG ++#define IOCTL_VIP_SET_UVC_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_VIP_SET_UVC_CONFIG ++#define IOCTL_VIP_SET_IHC_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_CONFIG ++#define IOCTL_VIP_SET_ICE_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_VIP_SET_ICE_CONFIG ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG ++#define IOCTL_VIP_SET_IBC_CONFIG_NR (11) ///< The IOCTL NR definition,IOCTL_VIP_SET_IBC_CONFIG ++#define IOCTL_VIP_SET_FCC_CONFIG_NR (12) ///< The IOCTL NR definition,IOCTL_VIP_SET_FCC_CONFIG ++#define IOCTL_VIP_SET_VIP_CONFIG_NR (13) ///< The IOCTL NR definition,IOCTL_VIP_SET_VIP_CONFIG ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG_NR (14) ///< The IOCTL NR definition,IOCTL_VIP_CMDQ_WRITE_CONFIG ++#define IOCTL_VIP_SET_LDC_CONFIG_NR (15) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_CONFIG ++#define IOCTL_VIP_SET_LDC_MD_CONFIG_NR (16) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_MD_CONFIG ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR (17) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_DMAP_CONFIG ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR (18) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_SRAM_CONFIG ++#define IOCTL_VIP_SET_ACK_CONFIG_NR (19) ///< The IOCTL NR definition,IOCTL_VIP_SET_ACK_CONFIG ++#define IOCTL_VIP_SET_NLM_CONFIG_NR (20) ///< The IOCTL NR definition,IOCTL_VIP_SET_NLM_CONFIG ++#define IOCTL_VIP_SET_VTRACK_CONFIG_NR (22) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_CONFIG ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR (23) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ++#define IOCTL_VIP_AIP_CONFIG_NR (24) ///< The IOCTL NR definition,IOCTL_VIP_AIP_CONFIG ++#define IOCTL_VIP_AIP_SRAM_CONFIG_NR (25) ///< The IOCTL NR definition,IOCTL_VIP_AIP_SRAM_CONFIG ++#define IOCTL_VIP_SET_MCNR_CONFIG_NR (26) ///< The IOCTL NR definition,IOCTL_VIP_SET_MCNR_CONFIG ++#define IOCLT_VIP_GET_VERSION_CONFIG_NR (27) ///< The IOCTL NR definition, IOCLT_VIP_GET_VERSION_CONFIG_NR ++#define IOCLT_VIP_SET_ALLVIP_CONFIG_NR (IOCLT_VIP_GET_VERSION_CONFIG_NR+1) ///< The IOCTL NR for vip driver ++#define IOCTL_VIP_MAX_NR (IOCLT_VIP_SET_ALLVIP_CONFIG_NR+1) ///< The Max IOCTL NR for vip driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_VIP_MAGIC ('3') ///< The Type definition of IOCTL for vip driver ++/** ++* Used to set CMDQ cmd, use ST_IOCTL_VIP_CMDQ_CONFIG. ++*/ ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_CMDQ_WRITE_CONFIG_NR) ++/** ++* Used to set LDC, use ST_IOCTL_VIP_LDC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_CONFIG_NR) ++/** ++* Used to set LDC mode, use ST_IOCTL_VIP_LDC_MD_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_MD_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_MD_CONFIG_NR) ++/** ++* Used to set LDC DMAP address, use ST_IOCTL_VIP_LDC_DMAP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR) ++/** ++* Used to set LDC SRAM address, use ST_IOCTL_VIP_LDC_SRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR) ++/** ++* Used to set PK, use ST_IOCTL_VIP_PEAKING_CONFIG. ++*/ ++#define IOCTL_VIP_SET_PEAKING_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_PEAKING_CONFIG_NR) ++/** ++* Used to set DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR) ++/** ++* Used to get DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT. ++*/ ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR) ++/** ++* Used to set DLC, use ST_IOCTL_VIP_DLC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_CONFIG_NR) ++/** ++* Used to set LCE, use ST_IOCTL_VIP_LCE_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LCE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LCE_CONFIG_NR) ++/** ++* Used to set UVC, use ST_IOCTL_VIP_UVC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_UVC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_UVC_CONFIG_NR) ++/** ++* Used to set IHC, use ST_IOCTL_VIP_IHC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_CONFIG_NR) ++/** ++* Used to set ICE, use ST_IOCTL_VIP_ICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ICE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ICE_CONFIG_NR) ++/** ++* Used to set IHCICC, use ST_IOCTL_VIP_IHCICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR) ++/** ++* Used to set IBC, use ST_IOCTL_VIP_IBC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IBC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IBC_CONFIG_NR) ++/** ++* Used to set FCC, use ST_IOCTL_VIP_FCC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_FCC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_FCC_CONFIG_NR) ++/** ++* Used to set ACK, use ST_IOCTL_VIP_ACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ACK_CONFIG_NR) ++/** ++* Used to set NLM, use ST_IOCTL_VIP_NLM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_NLM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_NLM_CONFIG_NR) ++/** ++* Used to set VIPLB, use ST_IOCTL_VIP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VIP_CONFIG_NR) ++/** ++* Used to set AIP, use ST_IOCTL_VIP_AIP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_AIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_AIP_CONFIG_NR) ++/** ++* Used to set AIP, use ST_IOCTL_VIP_AIP_SRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_AIP_SRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_AIP_SRAM_CONFIG_NR) ++/** ++* Used to set MCNR , use ST_IOCTL_VIP_MCNR_CONFIG. ++*/ ++#define IOCTL_VIP_SET_MCNR_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_MCNR_CONFIG_NR) ++ ++/** ++* Used to get version, use ST_IOCTL_VIP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_VIP_GET_VERSION_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_GET_VERSION_CONFIG_NR) ++/** ++* Used to set all vip config, use ST_IOCTL_VIP_AllSET_CONFIG. ++*/ ++#define IOCLT_VIP_SET_ALLVIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_SET_ALLVIP_CONFIG_NR) ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/sstar/include/mdrv_vip_io_i3_st.h b/drivers/sstar/include/mdrv_vip_io_i3_st.h +new file mode 100755 +index 000000000000..b9571a0668f8 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_vip_io_i3_st.h +@@ -0,0 +1,1276 @@ ++/* ++* mdrv_vip_io_i3_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup vip_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_VIP_IO_ST_H ++#define _MDRV_VIP_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++#define VIP_LCE_CURVE_SECTION_NUM 16 ///< VIP_LCE_CURVE_SECTION_NUM ++#define VIP_PEAKING_BAND_NUM 8 ///< VIP_PEAKING_BAND_NUM ++#define VIP_PEAKING_ADP_Y_LUT_NUM 8 ///< VIP_PEAKING_ADP_Y_LUT_NUM ++#define VIP_PEAKING_BAND_TERM_NUM 16 ///< VIP_PEAKING_BAND_TERM_NUM ++#define VIP_DLC_HISTOGRAM_SECTION_NUM 7 ///< VIP_DLC_HISTOGRAM_SECTION_NUM ++#define VIP_DLC_HISTOGRAM_REPORT_NUM 8 ///< VIP_DLC_HISTOGRAM_REPORT_NUM ++#define VIP_DLC_LUMA_SECTION_NUM 64 ///< VIP_DLC_LUMA_SECTION_NUM ++#define VIP_IHC_COLOR_NUM 16 ///< VIP_IHC_COLOR_NUM ++#define VIP_IHC_USER_COLOR_NUM 16 ///< VIP_IHC_USER_COLOR_NUM ++#define VIP_ICE_COLOR_NUM 16 ///< VIP_ICE_COLOR_NUM ++#define VIP_IBC_COLOR_NUM 16 ///< VIP_IBC_COLOR_NUM ++#define VIP_FCC_YWIN_LUT_ENTRY_NUM 17 ///< VIP_FCC_YWIN_LUT_ENTRY_NUM ++#define VIP_NLM_DISTWEIGHT_NUM 9 ///< VIP_NLM_DISTWEIGHT_NUM ++#define VIP_NLM_WEIGHT_NUM 32 ///< VIP_NLM_WEIGHT_NUM ++#define VIP_NLM_LUMAGAIN_NUM 64 ///< VIP_NLM_LUMAGAIN_NUM ++#define VIP_NLM_POSTLUMA_NUM 16 ///< VIP_NLM_POSTLUMA_NUM ++#define VIP_CMDQ_MEM_256K 0x0040000 ///< VIP_CMDQ_MEM_164K ++#define VIP_CMDQ_MEM_196K 0x0030000 ///< VIP_CMDQ_MEM_164K ++#define VIP_CMDQ_MEM_164K 0x0028000 ///< VIP_CMDQ_MEM_164K ++#define VIP_CMDQ_MEM_128K 0x0020000 ///< VIP_CMDQ_MEM_128K ++#define VIP_CMDQ_MEM_64K 0x0010000 ///< VIP_CMDQ_MEM_64K ++#define VIP_CMDQ_MEM_32K 0x0008000 ///< VIP_CMDQ_MEM_32K ++#define VIP_CMDQ_MEM_16K 0x0004000 ///< VIP_CMDQ_MEM_16K ++#define VIP_CMDQ_MEM_TEST 0x0001000 ///< VIP_CMDQ_MEM_TEST ++#define VIP_VTRACK_KEY_SETTING_LENGTH 8 ///< VIP_VTRACK_KEY_SETTING_LENGTH ++#define VIP_VTRACK_SETTING_LENGTH 23 ///< VIP_VTRACK_SETTING_LENGTH ++ ++// ++//1.0.1:for clean vip. ++#define IOCTL_VIP_VERSION 0x0101 ///< H:Major L:minor H3:Many Change H2:adjust Struct L1:add struct L0:adjust driver ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to setup vsrc of vip device ++*/ ++typedef enum ++{ ++ E_VIP_SRC_ISP, ///< VIP src ISP ++ E_VIP_SRC_BT656,///< VIP src BT656 ++ E_VIP_SRC_DRAM, ///< VIP src DRAM ++ E_VIP_SRC_NUM, ///< VIP src max number ++}__attribute__ ((__packed__))EN_VIP_SRC_TYPE; ++ ++/** ++* Used to setup LCE AVE of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_LCE_Y_AVE_5X11 = 0x0, ///< mask 0x10 ++ EN_VIP_LCE_Y_AVE_5X7 = 0x10, ///< mask 0x10 ++}__attribute__ ((__packed__))EN_VIP_LCE_Y_AVE_SEL_TYPE; ++ ++ ++/** ++* Used to setup UVC_ADP_Y_INPUT_SEL of vip device ++*/ ++typedef enum ++{ ++ E_VIP_UVC_ADP_Y_INPUT_SEL_UVC_LOCATE = 0x0, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_RGB_Y_OUTPUT = 0x40, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_DLC_Y_INPUT = 0x80, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_RGB_Y_INPUT = 0xC0, ///< mask 0xC0 ++}__attribute__ ((__packed__))EN_VIP_UVC_ADP_Y_INPUT_SEL_TYPE; ++ ++/** ++* Used to setup LDC_BYPASS of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_MENULOAD, ///< no bypass ++ E_VIP_LDC_BYPASS, ///< bypass ++ E_VIP_LDC_BYPASS_TYPE_NUM, ///< no use ++}__attribute__ ((__packed__))EN_VIP_LDC_BYPASS_TYPE; ++/** ++* Used to setup LDCLCBANKMODE of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_LDCLCBANKMODE_64, ///< 64p ++ EN_VIP_LDCLCBANKMODE_128, ///< 128p ++}__attribute__ ((__packed__))EN_VIP_LDCLCBANKMODE_TYPE; ++ ++/** ++* Used to setup VIP_LDC_422_444 of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_422_444_DUPLICATE = 0x1, ///< mask 0x3 ++ E_VIP_LDC_422_444_QUARTER = 0x2, ///< mask 0x3 ++ E_VIP_LDC_422_444_AVERAGE = 0x3, ///< mask 0x3 ++}__attribute__ ((__packed__))EN_VIP_LDC_422_444_TYPE; ++/** ++* Used to setup VIP_LDC_444_422 of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_444_422_DROP = 0x0, ///< mask 0x1C ++ E_VIP_LDC_444_422_AVERAGE = 0x4, ///< mask 0x1C ++}__attribute__ ((__packed__))EN_VIP_LDC_444_422_TYPE; ++/** ++* Used to VIP_NLM_Average of vip device ++*/ ++typedef enum ++{ ++ E_VIP_NLM_Average_3x3_mode = 0x0, ///< mask 0x2 ++ E_VIP_NLM_Average_5x5_mode = 0x2, ///< mask 0x2 ++}__attribute__ ((__packed__))EN_VIP_NLM_Average_TYPE; ++/** ++* Used to NLM_DSW of vip device ++*/ ++typedef enum ++{ ++ E_VIP_NLM_DSW_16x8_mode = 0x0, ///< mask 0x20 ++ E_VIP_NLM_DSW_32x16_mode = 0x20, ///< mask 0x20 ++}__attribute__ ((__packed__))EN_VIP_NLM_DSW_TYPE; ++/** ++* Used to VIP_FCC_Y of vip device ++*/ ++typedef enum ++{ ++ E_VIP_FCC_Y_DIS_CR_DOWN, ///< cr down ++ E_VIP_FCC_Y_DIS_CR_UP, ///< cr up ++ E_VIP_FCC_Y_DIS_CB_DOWN, ///< cb down ++ E_VIP_FCC_Y_DIS_CB_UP, ///< cb up ++ E_VIP_FCC_Y_DIS_NUM, ///< 4type ++}__attribute__ ((__packed__))EN_VIP_FCC_Y_DIS_TYPE; ++/** ++* Used to setup IHC_ICE_ADP_Y of vip device ++*/ ++typedef enum ++{ ++ E_VIP_IHC_ICE_ADP_Y_SECTION_0, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_1, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_2, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_3, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_NUM, ///< section ++}__attribute__ ((__packed__))EN_VIP_IHC_ICE_ADP_Y_SECTION_TYPE; ++/** ++* Used to setup suspend of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_ACK_CONFIG = 0x1, ///< ACK ++ EN_VIP_IBC_CONFIG = 0x2, ///< IBC ++ EN_VIP_IHCICC_CONFIG = 0x4, ///< ICCIHC ++ EN_VIP_ICC_CONFIG = 0x8, ///< ICE ++ EN_VIP_IHC_CONFIG = 0x10, ///< IHC ++ EN_VIP_FCC_CONFIG = 0x20, ///< FCC ++ EN_VIP_UVC_CONFIG = 0x40, ///< UVC ++ EN_VIP_DLC_HISTOGRAM_CONFIG = 0x80, ///< HIST ++ EN_VIP_DLC_CONFIG = 0x100, ///< DLC ++ EN_VIP_LCE_CONFIG = 0x200, ///< LCE ++ EN_VIP_PEAKING_CONFIG = 0x400, ///< PK ++ EN_VIP_NLM_CONFIG = 0x800, ///< NLM ++ EN_VIP_LDC_MD_CONFIG = 0x1000, ///< LDCMD ++ EN_VIP_LDC_DMAP_CONFIG = 0x2000, ///< LDCDMAP ++ EN_VIP_LDC_SRAM_CONFIG = 0x4000, ///< LDC SRAM ++ EN_VIP_LDC_CONFIG = 0x8000, ///< LDC ++ EN_VIP_CONFIG = 0x40000, ///< 19 bit to control 19 IOCTL ++}__attribute__ ((__packed__))EN_VIP_CONFIG_TYPE; ++/** ++* Used to setup the vtrack status of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_VTRACK_ENABLE_ON, ///< Vtrack on ++ EN_VIP_IOCTL_VTRACK_ENABLE_OFF, ///< Vtrack off ++ EN_VIP_IOCTL_VTRACK_ENABLE_DEBUG, ///< Vtrack debug ++}EN_VIP_IOCTL_VTRACK_ENABLE_TYPE; ++/** ++* Used to setup the AIP of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_AIP_YEE = 0, ///< yee ++ EN_VIP_IOCTL_AIP_YEE_AC_LUT, ///< yee ac lut ++ EN_VIP_IOCTL_AIP_WDR_GLOB, ///< wdr glob ++ EN_VIP_IOCTL_AIP_WDR_LOC, ///< wdr loc ++ EN_VIP_IOCTL_AIP_MXNR, ///< mxnr ++ EN_VIP_IOCTL_AIP_UVADJ, ///< uvadj ++ EN_VIP_IOCTL_AIP_XNR, ///< xnr ++ EN_VIP_IOCTL_AIP_YCUVM, ///< ycuvm ++ EN_VIP_IOCTL_AIP_COLORTRAN, ///< ct ++ EN_VIP_IOCTL_AIP_GAMMA, ///< gamma ++ EN_VIP_IOCTL_AIP_422TO444, ///< 422to444 ++ EN_VIP_IOCTL_AIP_YUVTORGB, ///< yuv2rgb ++ EN_VIP_IOCTL_AIP_GM10TO12, ///< 10 to 12 ++ EN_VIP_IOCTL_AIP_CCM, ///< ccm ++ EN_VIP_IOCTL_AIP_HSV, ///< hsv ++ EN_VIP_IOCTL_AIP_GM12TO10, ///< gm12to10 ++ EN_VIP_IOCTL_AIP_RGBTOYUV, ///< rgb2yuv ++ EN_VIP_IOCTL_AIP_444TO422, ///< 4442422 ++ EN_VIP_IOCTL_AIP_NUM, ///< Num ++}EN_VIP_IOCTL_AIP_TYPE; ++ ++/** ++* Used to setup the AIP SRAM of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_AIP_SRAM_GAMMA_Y, ///< gamma y ++ EN_VIP_IOCTL_AIP_SRAM_GAMMA_U, ///< gamma u ++ EN_VIP_IOCTL_AIP_SRAM_GAMMA_V, ///< gamma v ++ EN_VIP_IOCTL_AIP_SRAM_GM10to12_R, ///< gamma R ++ EN_VIP_IOCTL_AIP_SRAM_GM10to12_G, ///< gamma G ++ EN_VIP_IOCTL_AIP_SRAM_GM10to12_B, ///< gamma B ++ EN_VIP_IOCTL_AIP_SRAM_GM12to10_R, ///< gamma R ++ EN_VIP_IOCTL_AIP_SRAM_GM12to10_G, ///< gamma G ++ EN_VIP_IOCTL_AIP_SRAM_GM12to10_B, ///< gamma B ++ EN_VIP_IOCTL_AIP_SRAM_WDR, ///< wdr ++ EN_VIP_IOCTL_AIP_SRAM_NUM, ///< wdr ++}EN_VIP_IOCTL_AIP_SRAM_TYPE; ++ ++//============================================================================= ++// struct ++//============================================================================= ++ ++/** ++* Used to get VIP drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_VIP_VERSION_CONFIG; ++ ++/** ++* Used to setup CMDQ be used of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< enable CMDQ ++ unsigned char u8framecnt; ///< assign framecount ++}ST_IOCTL_VIP_FC_CONFIG; ++/** ++* Used to setup AIP config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32Viraddr; ///< AIP setting ++ EN_VIP_IOCTL_AIP_TYPE enAIPType; ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_AIP_CONFIG; ++/** ++* Used to setup AIP SRAM config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned long u32Viraddr; ///< AIP setting ++ EN_VIP_IOCTL_AIP_SRAM_TYPE enAIPType; ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_AIP_SRAM_CONFIG; ++ ++/** ++* Used to setup MCNR config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned char bEnMCNR; ++ unsigned char bEnCIIR; ++ unsigned long u32Viraddr; ///< MCNR setting ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_MCNR_CONFIG; ++ ++ ++/** ++* Used to setup LDC onoff of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLdc_path_sel; ///< reg_ldc_path_sel ++ unsigned char bEn_ldc; ///< reg_en_ldc(nonuse just bypass) ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_OnOffCONFIG; ++/** ++* Used to setup LDC mode of vip device ++*/ ++typedef struct ++{ ++ EN_VIP_LDC_422_444_TYPE en422to444; ///< reg_422to444_md ++ EN_VIP_LDC_444_422_TYPE en444to422; ///< reg_444to422_md ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_422_444_CONFIG; ++ ++/** ++* Used to setup LDC config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_LDC_OnOffCONFIG stEn; ///< be bypass ++ ST_IOCTL_VIP_LDC_422_444_CONFIG stmd; ///< set mode ++ EN_VIP_LDCLCBANKMODE_TYPE enLDCType; ///< LDC 64p or 128p ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_CONFIG; ++ ++/** ++* Used to setup LDC mode of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned char u8FBidx; ///< reg_ldc_fb_sw_idx ++ unsigned char u8FBrwdiff; ///< reg_ldc_fb_hw_rw_diff ++ unsigned char bEnSWMode; ///< reg_ldc_fb_sw_mode ++ EN_VIP_LDC_BYPASS_TYPE enbypass; ///< reg_ldc_ml_bypass ++ EN_VIP_LDCLCBANKMODE_TYPE enLDCType;///< LDC 64p or 128p ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_MD_CONFIG; ++/** ++* Used to setup LDC DMAP address of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32DMAPaddr; ///< reg_ldc_dmap_st_addr ++ unsigned short u16DMAPWidth; ///< reg_ldc_dmap_pitch ++ unsigned char u8DMAPoffset; ///< reg_ldc_dmap_blk_xstart ++ unsigned char bEnPowerSave; ///< reg_ldc_en_power_saving_mode ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_DMAP_CONFIG; ++ ++/** ++* Used to setup SRAM address of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32loadhoraddr; ///< reg_ldc_load_st_addr0 ++ unsigned short u16SRAMhorstr; ///< reg_ldc_sram_st_addr0 ++ unsigned short u16SRAMhoramount; ///< reg_ldc_load_amount0 ++ unsigned long u32loadveraddr; ///< reg_ldc_load_st_addr1 ++ unsigned short u16SRAMverstr; ///< reg_ldc_sram_st_addr1 ++ unsigned short u16SRAMveramount; ///< reg_ldc_load_amount1 ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_SRAM_CONFIG; ++ ++/** ++* Used to setup NLM setting of vip device ++*/ ++typedef struct ++{ ++ unsigned char bNlm_en; ///< reg_nlm_en ++ EN_VIP_NLM_Average_TYPE enAvgmode; ///< reg_nlm_avg_mode :0:3x3 1:5x5 ++ unsigned char bnlm_bdry_en; ///< reg_nlm_bdry_en ++ unsigned char bnlm_post_luma_adap_en; ///< reg_nlm_post_luma_adap_en ++ unsigned char bnlm_luma_adap_en; ///< reg_nlm_luma_adap_en ++ unsigned char bnlm_dsw_adap_en; ///< reg_nlm_dsw_adap_en ++ unsigned char bnlmdsw_lpf_en; ///< reg_nlm_dsw_lpf_en ++ unsigned char bnlm_region_adap_en; ///< reg_nlm_region_adap_en ++ EN_VIP_NLM_DSW_TYPE u8nlm_region_adap_size_config; ///< reg_nlm_region_adap_size_config 0:16x8 1:32x16 ++ unsigned char bnlm_histIIR_en; ///< reg_nlm_histiir_adap_en ++ unsigned char bnlm_bypass_en; ///< reg_nlm_bypass_en ++ unsigned char u8nlm_fin_gain; ///< reg_nlm_fin_gain ++ unsigned char u8nlm_histIIR; ///< reg_nlm_histiir_adap_ratio ++ unsigned char u8nlm_sad_shift; ///< reg_nlm_sad_shift ++ unsigned char u8nlm_sad_gain; ///< reg_nlm_sad_gain ++ unsigned char u8nlm_dsw_ratio; ///< reg_nlm_dsw_ratio ++ unsigned char u8nlm_dsw_offset; ///< reg_nlm_dsw_offset ++ unsigned char u8nlm_dsw_shift; ///< reg_nlm_dsw_shift ++ unsigned char u8nlm_weight_lut[VIP_NLM_WEIGHT_NUM]; ///< reg_nlm_weight_lut0-31 ,Qmap has adjust register squence ++ unsigned char u8nlm_luma_adap_gain_lut[VIP_NLM_LUMAGAIN_NUM]; ///< reg_nlm_luma_adap_gain_lut0-63,adjust register squence ++ unsigned char u8nlm_post_luma_adap_gain_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_nlm_post_luma_adap_gain_lut0-15,adjust register squence ++ unsigned char u8nlm_dist_weight_7x7_lut[VIP_NLM_DISTWEIGHT_NUM]; ///< reg_nlm_dist_weight_7x7_lut0-8,adjust register squence ++ unsigned char u8nlm_main_snr_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_main_snr_lut ++ unsigned char u8nlm_wb_snr_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_wb_snr_lut ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_MAIN_CONFIG; ++/** ++* Used to setup NLM autodown load of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< enable auto downlaod ++ unsigned long u32Baseadr; ///< auto download phy addr ++ unsigned long u32viradr; ///< disable auto download need virtual ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_SRAM_CONFIG; ++/** ++* Used to setup NLM config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_NLM_MAIN_CONFIG stNLM; ///< NLM setting ++ ST_IOCTL_VIP_NLM_SRAM_CONFIG stSRAM; ///< Autodownload ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_CONFIG; ++ ++ ++/** ++* Used to setup 422to444 of vip device ++*/ ++typedef struct ++{ ++ unsigned char bvip_422to444_en; ///< reg_vip_422to444_en ++ unsigned char u8vip_422to444_md; ///< reg_vip_422to444_md ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_422_444_CONFIG; ++ ++/** ++* Used to setup bypass MACE of vip device ++*/ ++typedef struct ++{ ++ unsigned char bvip_fun_bypass_en; ///< reg_vip_fun_bypass_en :except DNR,SNR,NLM,LDC ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_BYPASS_CONFIG; ++ ++/** ++* Used to setup the LB of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8vps_sram_act; ///< reg_vps_sram_act ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LINEBUFFER_CONFIG; ++/** ++* Used to setup mix vip of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_422_444_CONFIG st422_444; ///< 422 to 444 ++ ST_IOCTL_VIP_BYPASS_CONFIG stBypass; ///< bypass ++ ST_IOCTL_VIP_LINEBUFFER_CONFIG stLB; ///< VIP Mixed ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_CONFIG; ++ ++/** ++* Used to setup PK HLPF of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8main_y_lpf_coef; ///< reg_main_y_lpf_coef ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_HLPF_CONFIG; ++ ++/** ++* Used to setup PK HLPF dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char hlpf_dither_en; ///< reg_hlpf_dither_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_HLPF_DITHER_CONFIG; ++ ++/** ++* Used to setup PK VLPF of vip device ++*/ ++typedef struct ++{ ++ unsigned char main_v_lpf_coef; ///< reg_main_v_lpf_coef_1,2 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_VLPF_COEF_CONFIG; ++ ++/** ++* Used to PK VLPF dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char vlpf_dither_en; ///< reg_vlpf_dither_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_VLPF_DITHER_CONFIG; ++ ++ ++/** ++* Used to setup PK onoff of vip device ++*/ ++typedef struct ++{ ++ unsigned char bpost_peaking_en; ///< reg_main_post_peaking_en ++ unsigned char u8vps_sram_act; ///< reg_vps_sram_act ++ unsigned char u8band6_dia_filter_sel; ///< reg_main_band6_dia_filter_sel ++ unsigned char u8peaking_ac_yee_mode; ///< reg_peaking_ac_yee_mode ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ONOFFCONFIG; ++ ++/** ++* Used to setup PK band of vip device ++*/ ++typedef struct ++{ ++ unsigned char bBand_En[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_peaking_en 1-8 ++ unsigned char u8Band_COEF_STEP[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coef_step 1-8 ++ unsigned char u8Band_COEF[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coef 1-8 ++ unsigned char u8peaking_term[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_main_peaking_term1_select 1-16 ++ unsigned char u8Band_Over[VIP_PEAKING_BAND_NUM]; ///< reg_band1_overshoot_limit 1-8 ++ unsigned char u8Band_Under[VIP_PEAKING_BAND_NUM]; ///< reg_band1_undershoot_limit 1-8 ++ unsigned char u8Band_coring_thrd[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coring_thrd 1-8 ++ unsigned char u8alpha_thrd; ///< reg_main_alpha_thrd ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_BAND_CONFIG; ++ ++/** ++* Used to setup pk adptive of vip device ++*/ ++typedef struct ++{ ++ unsigned char badaptive_en[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_adaptive_en 1-8 ++ unsigned char u8hor_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_hor_lut_0-15 ++ unsigned char u8ver_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_ver_lut_0-15 ++ unsigned char u8low_diff_thrd_and_adaptive_gain_step[VIP_PEAKING_BAND_TERM_NUM]; ///< alternation(reg_band1_adaptive_gain_step, reg_band1_low_diff_thrd) 1-8 ++ unsigned char u8dia_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_dia_lut_0-15 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ADPTIVE_CONFIG; ++ ++/** ++* Used to setup PK preCoring of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8coring_thrd_1; ///< reg_main_coring_thrd_1 ++ unsigned char u8coring_thrd_2; ///< reg_main_coring_thrd_2 ++ unsigned char u8coring_thrd_step; ///< reg_main_coring_thrd_step ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_PCORING_CONFIG; ++ ++/** ++* Used to setup pk ADP_Y of vip device ++*/ ++typedef struct ++{ ++ unsigned char bcoring_adp_y_en; ///< reg_main_coring_adp_y_en ++ unsigned char bcoring_adp_y_alpha_lpf_en; ///< reg_main_coring_adp_y_alpha_lpf_en ++ unsigned char u8coring_y_low_thrd; ///< reg_main_coring_y_low_thrd ++ unsigned char u8coring_adp_y_step; ///< reg_main_coring_adp_y_step ++ unsigned char u8coring_adp_y_alpha_lut[VIP_PEAKING_ADP_Y_LUT_NUM]; ///< reg_main_coring_adp_y_alpha_lut_0-7 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ADP_Y_CONFIG; ++ ++/** ++* Used to setup PK gain of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8osd_sharpness_ctrl ; ///< reg_main_osd_sharpness_ctrl ++ unsigned char bosd_sharpness_sep_hv_en; ///< reg_main_osd_sharpness_sep_hv_en ++ unsigned char u8osd_sharpness_ctrl_h ; ///< reg_main_osd_sharpness_ctrl_h ++ unsigned char u8osd_sharpness_ctrl_v ; ///< reg_main_osd_sharpness_ctrl_v ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_GAIN_CONFIG; ++ ++/** ++* Used to setup PK adpy gain of vip device ++*/ ++typedef struct ++{ ++ unsigned char bpk_adp_y_en; ///< reg_main_coring_adp_y_en ++ unsigned char bpk_adp_y_alpha_lpf_en; ///< reg_main_coring_adp_y_alpha_lpf_en ++ unsigned char u8pk_y_low_thrd; ///< reg_main_coring_y_low_thrd ++ unsigned char u8pk_adp_y_step; ///< reg_main_coring_adp_y_step ++ unsigned char u8pk_adp_y_alpha_lut[VIP_PEAKING_ADP_Y_LUT_NUM]; ///< reg_main_coring_adp_y_alpha_lut_0-7 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_GAIN_ADP_Y_CONFIG; ++ ++/** ++* Used to setup pk yc gain of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16Dlc_in_y_gain; ///< reg_dlc_in_y_gain 16bit ++ unsigned short u16Dlc_in_y_offset; ///< reg_dlc_in_y_offset 16 bit ++ unsigned short u16Dlc_in_c_gain; ///< reg_dlc_in_c_gain 16 bit ++ unsigned short u16Dlc_in_c_offset; ///< reg_dlc_in_c_offset 16 bit ++ unsigned short u16Dlc_out_y_gain; ///< reg_dlc_out_y_gain 16 bit ++ unsigned short u16Dlc_out_y_offset;///< reg_dlc_out_y_offset 16 bit ++ unsigned short u16Dlc_out_c_gain; ///< reg_dlc_out_c_gain 16 bit ++ unsigned short u16Dlc_out_c_offset;///< reg_dlc_out_c_offset 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_YC_GAIN_OFFSET_CONFIG; ++ ++/** ++* Used to setup pk config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_HLPF_CONFIG stHLPF; ///< HLPF ++ ST_IOCTL_VIP_HLPF_DITHER_CONFIG stHLPFDith; ///< HDither ++ ST_IOCTL_VIP_VLPF_COEF_CONFIG stVLPFcoef1; ///< VLPF coef1 ++ ST_IOCTL_VIP_VLPF_COEF_CONFIG stVLPFcoef2; ///< VLPF coef2 ++ ST_IOCTL_VIP_VLPF_DITHER_CONFIG stVLPFDith; ///< VDither ++ ST_IOCTL_VIP_PEAKING_ONOFFCONFIG stOnOff; ///< pkonoff ++ ST_IOCTL_VIP_PEAKING_BAND_CONFIG stBand; ///< pkband ++ ST_IOCTL_VIP_PEAKING_ADPTIVE_CONFIG stAdp; ///< pk adp ++ ST_IOCTL_VIP_PEAKING_PCORING_CONFIG stPcor; ///< pk precore ++ ST_IOCTL_VIP_PEAKING_ADP_Y_CONFIG stAdpY; ///< pk adp y ++ ST_IOCTL_VIP_PEAKING_GAIN_CONFIG stGain; ///< pk gain ++ ST_IOCTL_VIP_PEAKING_GAIN_ADP_Y_CONFIG stGainAdpY; ///< pk Y gain ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_CONFIG; ++ ++ ++/** ++* Used to setup LCE of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_En; ///< LCE en ++ unsigned char u8ControlNum; ///< vip control guard pipe number ++ ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_ONOFF_CONFIG; ++ ++ ++/** ++* Used to setup LCE dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_Dither_En; ///< LCE dither ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_DITHER_CONFIG; ++ ++/** ++* Used to setup LCE config of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_sodc_alpha_en; ///< reg_main_lce_sodc_alpha_en ++ unsigned char bLce_dering_alpha_en; ///< reg_main_lce_dering_alpha_en ++ EN_VIP_LCE_Y_AVE_SEL_TYPE enLce_y_ave_sel; ///< reg_main_lce_y_ave_sel (1'b1: 5x7; 1'b0:5x11) ++ unsigned char bLce_3curve_en; ///< reg_lce_3curve_en ++ unsigned char u8Lce_std_slop1; ///< reg_main_lce_std_slop1 ++ unsigned char u8Lce_std_slop2; ///< reg_main_lce_std_slop2 ++ unsigned char u8Lce_std_th1; ///< reg_main_lce_std_th1 ++ unsigned char u8Lce_std_th2; ///< reg_main_lce_std_th2 ++ unsigned char u8Lce_gain_min; ///< reg_main_lce_gain_min ++ unsigned char u8Lce_gain_max; ///< reg_main_lce_gain_max ++ unsigned char u8Lce_sodc_low_alpha; ///< reg_main_lce_sodc_low_alpha ++ unsigned char u8Lce_sodc_low_th; ///< reg_main_lce_sodc_low_th ++ unsigned char u8Lce_sodc_slop; ///< reg_main_lce_sodc_slop ++ unsigned char u8Lce_diff_gain; ///< reg_main_lce_diff_gain ++ unsigned char u8Lce_gain_complex; ///< reg_main_lce_gain_complex ++ unsigned char u8Lce_dsw_minsadgain; ///< reg_dsptch_lce_dsw_minsadgain ++ unsigned char u8Lce_dsw_gain; ///< reg_dsptch_lce_dsw_gian ++ unsigned char u8LCE_dsw_thrd; ///< reg_dsptch_lce_dsw_thrd ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_SETTING_CONFIG; ++ ++/** ++* Used to setup LCE curve of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8Curve_Thread[4]; ///< reg_main_lce_curve_a-d ++ unsigned short u16Curve1[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut1_08-f8 (lsb|msb) 16bit ++ unsigned short u16Curve2[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut2_08-f8 (lsb|msb) 16bit ++ unsigned short u16Curve3[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut3_08-f8 (lsb|msb) 16bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_CRUVE_CONFIG; ++ ++/** ++* Used to setup LCE of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_LCE_ONOFF_CONFIG stOnOff; ///< bEn ++ ST_IOCTL_VIP_LCE_DITHER_CONFIG stDITHER; ///< dither ++ ST_IOCTL_VIP_LCE_SETTING_CONFIG stSet; ///< config ++ ST_IOCTL_VIP_LCE_CRUVE_CONFIG stCurve; ///< curve ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_CONFIG; ++ ++/** ++* Used to setup DLC prog of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8VARCP[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_curve_fit_var_cp1 -64 ++ unsigned char u8Tbln0; ///< reg_main_curve_table_n0 ++ unsigned char u8Tbln0LSB; ///< reg_main_curve_table_n0_LSB ++ unsigned char u8Tbln0sign; ///< reg_main_curve_table_n0_sign ++ unsigned short u16Tbl64; ///< reg_main_curve_table64 16 bit ++ unsigned char u8Tbl64LSB; ///< reg_main_curve_table64_LSB ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_PROG_CONFIG; ++ ++//IOCTL_VIP_SET_DLC_CURVE_CONFIG ++/** ++* Used to setup DLC curve config of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8InLuma[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_main_curve_table0-63 ++ unsigned char u8InLumaLSB[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_main_curve_table0-63 LSB ++ ST_IOCTL_VIP_DLC_PROG_CONFIG ProgCfg; ///< dlc proc ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_CURVE_CONFIG; ++ ++/** ++* Used to DLC enable of vip device ++*/ ++typedef struct ++{ ++ unsigned char bcurve_fit_var_pw_en; ///< reg_main_curve_fit_var_pw_en ++ ST_IOCTL_VIP_DLC_CURVE_CONFIG stCurve; ///< curve config ++ unsigned char bcurve_fit_en; ///< reg_main_curve_fit_en ++ unsigned char bstatistic_en; ///< reg_main_statistic_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_ENABLE_CONFIG; ++ ++/** ++* Used to setup dic dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char bDLCdither_en; ///< bdlc dither ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_DITHER_CONFIG; ++ ++/** ++* Used to setup DLC range of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8brange_en; ///< brange ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_EN_CONFIG; ++ ++/** ++* Used to setup DLC H of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16statistic_h_start; ///< reg_main_statistic_h_start 16 bit ++ unsigned short u16statistic_h_end; ///< reg_main_statistic_h_end 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_H_CONFIG; ++ ++/** ++* Used to setup DLC V of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16statistic_v_start; ///< reg_main_statistic_v_start 16 bit ++ unsigned short u16statistic_v_end; ///< reg_main_statistic_v_end 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_V_CONFIG; ++ ++/** ++* Used to setup DLC PC of vip device ++*/ ++typedef struct ++{ ++ unsigned char bhis_y_rgb_mode_en; ///< reg_his_y_rgb_mode_en ++ unsigned char bcurve_fit_rgb_en; ///< reg_main_curve_fit_rgb_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_PC_CONFIG; ++/** ++* Used to setup DLC of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_YC_GAIN_OFFSET_CONFIG stGainOffset; ///< Gain ++ ST_IOCTL_VIP_DLC_ENABLE_CONFIG stEn; ///< EN ++ ST_IOCTL_VIP_DLC_DITHER_CONFIG stDither; ///< Dither ++ ST_IOCTL_VIP_DLC_HISTOGRAM_EN_CONFIG sthist; ///< hist ++ ST_IOCTL_VIP_DLC_HISTOGRAM_H_CONFIG stHistH; /// ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ /** ++ * \ingroup vip_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_VIP_IO_ST_H ++#define _MDRV_VIP_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++#define VIP_DNR_Y_RANGE_NUM 4 ///< VIP_DNR_Y_RANGE_NUM ++#define VIP_DNR_C_RANGE_NUM 4 ///< VIP_DNR_C_RANGE_NUM ++#define VIP_LCE_CURVE_SECTION_NUM 16 ///< VIP_LCE_CURVE_SECTION_NUM ++#define VIP_PEAKING_BAND_NUM 8 ///< VIP_PEAKING_BAND_NUM ++#define VIP_PEAKING_ADP_Y_LUT_NUM 8 ///< VIP_PEAKING_ADP_Y_LUT_NUM ++#define VIP_PEAKING_BAND_TERM_NUM 16 ///< VIP_PEAKING_BAND_TERM_NUM ++#define VIP_DLC_HISTOGRAM_SECTION_NUM 7 ///< VIP_DLC_HISTOGRAM_SECTION_NUM ++#define VIP_DLC_HISTOGRAM_REPORT_NUM 8 ///< VIP_DLC_HISTOGRAM_REPORT_NUM ++#define VIP_DLC_LUMA_SECTION_NUM 64 ///< VIP_DLC_LUMA_SECTION_NUM ++#define VIP_IHC_COLOR_NUM 16 ///< VIP_IHC_COLOR_NUM ++#define VIP_IHC_USER_COLOR_NUM 16 ///< VIP_IHC_USER_COLOR_NUM ++#define VIP_ICE_COLOR_NUM 16 ///< VIP_ICE_COLOR_NUM ++#define VIP_IBC_COLOR_NUM 16 ///< VIP_IBC_COLOR_NUM ++#define VIP_FCC_YWIN_LUT_ENTRY_NUM 17 ///< VIP_FCC_YWIN_LUT_ENTRY_NUM ++#define VIP_NLM_DISTWEIGHT_NUM 9 ///< VIP_NLM_DISTWEIGHT_NUM ++#define VIP_NLM_WEIGHT_NUM 32 ///< VIP_NLM_WEIGHT_NUM ++#define VIP_NLM_LUMAGAIN_NUM 64 ///< VIP_NLM_LUMAGAIN_NUM ++#define VIP_NLM_POSTLUMA_NUM 16 ///< VIP_NLM_POSTLUMA_NUM ++#define VIP_SNR_MD_NUM 4 ///< VIP_SNR_MD_NUM ++#define VIP_CMDQ_MEM_128K 0x0020000 ///< VIP_CMDQ_MEM_128K ++#define VIP_CMDQ_MEM_64K 0x0010000 ///< VIP_CMDQ_MEM_64K ++#define VIP_CMDQ_MEM_32K 0x0008000 ///< VIP_CMDQ_MEM_32K ++#define VIP_CMDQ_MEM_16K 0x0004000 ///< VIP_CMDQ_MEM_16K ++#define VIP_CMDQ_MEM_TEST 0x0001000 ///< VIP_CMDQ_MEM_TEST ++#define VIP_VTRACK_KEY_SETTING_LENGTH 8 ///< VIP_VTRACK_KEY_SETTING_LENGTH ++#define VIP_VTRACK_SETTING_LENGTH 23 ///< VIP_VTRACK_SETTING_LENGTH ++ ++// ++//1.0.1:for clean vip. ++#define IOCTL_VIP_VERSION 0x0101 ///< H:Major L:minor H3:Many Change H2:adjust Struct L1:add struct L0:adjust driver ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to setup vsrc of vip device ++*/ ++typedef enum ++{ ++ E_VIP_SRC_ISP, ///< VIP src ISP ++ E_VIP_SRC_BT656,///< VIP src BT656 ++ E_VIP_SRC_DRAM, ///< VIP src DRAM ++ E_VIP_SRC_NUM, ///< VIP src max number ++}__attribute__ ((__packed__))EN_VIP_SRC_TYPE; ++ ++/** ++* Used to setup LCE AVE of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_LCE_Y_AVE_5X11 = 0x0, ///< mask 0x10 ++ EN_VIP_LCE_Y_AVE_5X7 = 0x10, ///< mask 0x10 ++}__attribute__ ((__packed__))EN_VIP_LCE_Y_AVE_SEL_TYPE; ++ ++ ++/** ++* Used to setup UVC_ADP_Y_INPUT_SEL of vip device ++*/ ++typedef enum ++{ ++ E_VIP_UVC_ADP_Y_INPUT_SEL_UVC_LOCATE = 0x0, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_RGB_Y_OUTPUT = 0x40, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_DLC_Y_INPUT = 0x80, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_RGB_Y_INPUT = 0xC0, ///< mask 0xC0 ++}__attribute__ ((__packed__))EN_VIP_UVC_ADP_Y_INPUT_SEL_TYPE; ++ ++/** ++* Used to setup LDC_BYPASS of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_MENULOAD, ///< no bypass ++ E_VIP_LDC_BYPASS, ///< bypass ++ E_VIP_LDC_BYPASS_TYPE_NUM, ///< no use ++}__attribute__ ((__packed__))EN_VIP_LDC_BYPASS_TYPE; ++/** ++* Used to setup LDCLCBANKMODE of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_LDCLCBANKMODE_64, ///< 64p ++ EN_VIP_LDCLCBANKMODE_128, ///< 128p ++}__attribute__ ((__packed__))EN_VIP_LDCLCBANKMODE_TYPE; ++ ++/** ++* Used to setup VIP_LDC_422_444 of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_422_444_DUPLICATE = 0x1, ///< mask 0x3 ++ E_VIP_LDC_422_444_QUARTER = 0x2, ///< mask 0x3 ++ E_VIP_LDC_422_444_AVERAGE = 0x3, ///< mask 0x3 ++}__attribute__ ((__packed__))EN_VIP_LDC_422_444_TYPE; ++/** ++* Used to setup VIP_LDC_444_422 of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_444_422_DROP = 0x0, ///< mask 0x1C ++ E_VIP_LDC_444_422_AVERAGE = 0x4, ///< mask 0x1C ++}__attribute__ ((__packed__))EN_VIP_LDC_444_422_TYPE; ++/** ++* Used to VIP_NLM_Average of vip device ++*/ ++typedef enum ++{ ++ E_VIP_NLM_Average_3x3_mode = 0x0, ///< mask 0x2 ++ E_VIP_NLM_Average_5x5_mode = 0x2, ///< mask 0x2 ++}__attribute__ ((__packed__))EN_VIP_NLM_Average_TYPE; ++/** ++* Used to NLM_DSW of vip device ++*/ ++typedef enum ++{ ++ E_VIP_NLM_DSW_16x8_mode = 0x0, ///< mask 0x20 ++ E_VIP_NLM_DSW_32x16_mode = 0x20, ///< mask 0x20 ++}__attribute__ ((__packed__))EN_VIP_NLM_DSW_TYPE; ++/** ++* Used to VIP_FCC_Y of vip device ++*/ ++typedef enum ++{ ++ E_VIP_FCC_Y_DIS_CR_DOWN, ///< cr down ++ E_VIP_FCC_Y_DIS_CR_UP, ///< cr up ++ E_VIP_FCC_Y_DIS_CB_DOWN, ///< cb down ++ E_VIP_FCC_Y_DIS_CB_UP, ///< cb up ++ E_VIP_FCC_Y_DIS_NUM, ///< 4type ++}__attribute__ ((__packed__))EN_VIP_FCC_Y_DIS_TYPE; ++/** ++* Used to setup IHC_ICE_ADP_Y of vip device ++*/ ++typedef enum ++{ ++ E_VIP_IHC_ICE_ADP_Y_SECTION_0, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_1, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_2, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_3, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_NUM, ///< section ++}__attribute__ ((__packed__))EN_VIP_IHC_ICE_ADP_Y_SECTION_TYPE; ++/** ++* Used to setup suspend of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_ACK_CONFIG = 0x1, ///< ACK ++ EN_VIP_IBC_CONFIG = 0x2, ///< IBC ++ EN_VIP_IHCICC_CONFIG = 0x4, ///< ICCIHC ++ EN_VIP_ICC_CONFIG = 0x8, ///< ICE ++ EN_VIP_IHC_CONFIG = 0x10, ///< IHC ++ EN_VIP_FCC_CONFIG = 0x20, ///< FCC ++ EN_VIP_UVC_CONFIG = 0x40, ///< UVC ++ EN_VIP_DLC_HISTOGRAM_CONFIG = 0x80, ///< HIST ++ EN_VIP_DLC_CONFIG = 0x100, ///< DLC ++ EN_VIP_LCE_CONFIG = 0x200, ///< LCE ++ EN_VIP_PEAKING_CONFIG = 0x400, ///< PK ++ EN_VIP_NLM_CONFIG = 0x800, ///< NLM ++ EN_VIP_LDC_MD_CONFIG = 0x1000, ///< LDCMD ++ EN_VIP_LDC_DMAP_CONFIG = 0x2000, ///< LDCDMAP ++ EN_VIP_LDC_SRAM_CONFIG = 0x4000, ///< LDC SRAM ++ EN_VIP_LDC_CONFIG = 0x8000, ///< LDC ++ EN_VIP_DNR_CONFIG = 0x10000, ///< DNR ++ EN_VIP_SNR_CONFIG = 0x20000, ///< SNR ++ EN_VIP_CONFIG = 0x40000, ///< 19 bit to control 19 IOCTL ++}__attribute__ ((__packed__))EN_VIP_CONFIG_TYPE; ++/** ++* Used to setup the vtrack status of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_VTRACK_ENABLE_ON, ///< Vtrack on ++ EN_VIP_IOCTL_VTRACK_ENABLE_OFF, ///< Vtrack off ++ EN_VIP_IOCTL_VTRACK_ENABLE_DEBUG, ///< Vtrack debug ++}EN_VIP_IOCTL_VTRACK_ENABLE_TYPE; ++ ++//============================================================================= ++// struct ++//============================================================================= ++ ++/** ++* Used to get VIP drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_VIP_VERSION_CONFIG; ++ ++// IOCTL_VIP_SET_DNR_CONFIG ++/** ++* Used to setup CMDQ be used of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< enable CMDQ ++ unsigned char u8framecnt; ///< assign framecount ++}ST_IOCTL_VIP_FC_CONFIG; ++/** ++* Used to setup snr format of vip device ++*/ ++typedef struct ++{ ++ unsigned char bsnr_en; ///< reg_snr_en ++ unsigned char bsnr_md_en; ///< reg_snr_md_en ++ unsigned char u8f2_sharp_level; ///< reg_f2_sharp_level ++ unsigned short u16snr_md_table[VIP_SNR_MD_NUM]; ///< reg_snr_md_table_0~3 16bit *4 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_SNR_MAIN_CONFIG; ++/** ++* Used to setup snr config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_SNR_MAIN_CONFIG stSNR; ///< SNR setting ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_SNR_CONFIG; ++/** ++* Used to setup the DNR format of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< DNR enable reg_dnr_en_f2 ++ unsigned char bCoreEn; ///< DNR core function enable reg_dnr_core_en_f2 ++ unsigned char bEncode; ///< reg_ipm_ce_en ++ unsigned char bDecode; ///< reg_ipm_ce_de_en need together bEncode ++ unsigned char bStickyYEn; ///< reg_f2_sticky_solver_en_y ++ unsigned char bStickyCEn; ///< reg_f2_sticky_solver_en_c ++ unsigned char bStickyDithEn; ///< reg_f2_sticky_solver_dith_en ++ unsigned char bStickyThEn; ///< reg_f2_sticky_solver_th ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DNR_ONOFF_CONFIG; ++ ++/** ++* Used to setup DNR Y filter of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8nr_table_sel_y; ///< reg_nr_table_sel_y ++ unsigned char bf2_dnr_filter_en_y; ///< reg_f2_dnr_filter_en_y ++ unsigned char bf2_max_mot_enable_y; ///< reg_f2_max_mot_enable_y ++ unsigned char u8filter_y_div0; ///< reg_filter_y_div0 ++ unsigned char u8filter_y_div1; ///< reg_filter_y_div1 ++ unsigned char u8filter_y_mode; ///< reg_filter_y_mode ++ unsigned short u16dnr_tabley[VIP_DNR_Y_RANGE_NUM]; ///< reg_dnr_tabley_0~3 16bit * 4 ++ unsigned char u8f2_round_mode_y; ///< reg_f2_round_mode_y ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DNR_Y_CONFIG; ++ ++/** ++* Used to setup DNR Y filter of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8nr_table_sel_c; ///< reg_nr_table_sel_c ++ unsigned char bf2_dnr_filter_en_c; ///< reg_f2_dnr_filter_en_c ++ unsigned char bf2_max_mot_enable_c; ///< reg_f2_max_mot_enable_c ++ unsigned char u8filter_c_div0; ///< reg_filter_c_div0 ++ unsigned char u8filter_c_div1; ///< reg_filter_c_div1 ++ unsigned char u8filter_c_mode; ///< reg_filter_c_mode ++ unsigned short u16dnr_tablec[VIP_DNR_C_RANGE_NUM]; ///< reg_dnr_tablec_0~3 16bit * 4 ++ unsigned char u8f2_round_mode_c; ///< reg_f2_round_mode_c ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DNR_C_CONFIG; ++/** ++* Used to setup the DNR config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_DNR_ONOFF_CONFIG stOnOff; ///< DNR enable ++ ST_IOCTL_VIP_DNR_Y_CONFIG stY; ///< DNR Y function ++ ST_IOCTL_VIP_DNR_C_CONFIG stC; ///< DNR C function ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DNR_CONFIG; ++ ++ ++/** ++* Used to setup LDC onoff of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLdc_path_sel; ///< reg_ldc_path_sel ++ unsigned char bEn_ldc; ///< reg_en_ldc(nonuse just bypass) ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_OnOffCONFIG; ++/** ++* Used to setup LDC mode of vip device ++*/ ++typedef struct ++{ ++ EN_VIP_LDC_422_444_TYPE en422to444; ///< reg_422to444_md ++ EN_VIP_LDC_444_422_TYPE en444to422; ///< reg_444to422_md ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_422_444_CONFIG; ++ ++/** ++* Used to setup LDC config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_LDC_OnOffCONFIG stEn; ///< be bypass ++ ST_IOCTL_VIP_LDC_422_444_CONFIG stmd; ///< set mode ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_CONFIG; ++/** ++* Used to setup LDC mode of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned char u8FBidx; ///< reg_ldc_fb_sw_idx ++ unsigned char u8FBrwdiff; ///< reg_ldc_fb_hw_rw_diff ++ unsigned char bEnSWMode; ///< reg_ldc_fb_sw_mode ++ EN_VIP_LDC_BYPASS_TYPE enbypass; ///< reg_ldc_ml_bypass ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_MD_CONFIG; ++/** ++* Used to setup LDC DMAP address of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32DMAPaddr; ///< reg_ldc_dmap_st_addr ++ unsigned short u16DMAPWidth; ///< reg_ldc_dmap_pitch ++ unsigned char u8DMAPoffset; ///< reg_ldc_dmap_blk_xstart ++ unsigned char bEnPowerSave; ///< reg_ldc_en_power_saving_mode ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_DMAP_CONFIG; ++ ++/** ++* Used to setup SRAM address of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32loadhoraddr; ///< reg_ldc_load_st_addr0 ++ unsigned short u16SRAMhorstr; ///< reg_ldc_sram_st_addr0 ++ unsigned short u16SRAMhoramount; ///< reg_ldc_load_amount0 ++ unsigned long u32loadveraddr; ///< reg_ldc_load_st_addr1 ++ unsigned short u16SRAMverstr; ///< reg_ldc_sram_st_addr1 ++ unsigned short u16SRAMveramount; ///< reg_ldc_load_amount1 ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_SRAM_CONFIG; ++ ++/** ++* Used to setup NLM setting of vip device ++*/ ++typedef struct ++{ ++ unsigned char bNlm_en; ///< reg_nlm_en ++ EN_VIP_NLM_Average_TYPE enAvgmode; ///< reg_nlm_avg_mode :0:3x3 1:5x5 ++ unsigned char bnlm_bdry_en; ///< reg_nlm_bdry_en ++ unsigned char bnlm_post_luma_adap_en; ///< reg_nlm_post_luma_adap_en ++ unsigned char bnlm_luma_adap_en; ///< reg_nlm_luma_adap_en ++ unsigned char bnlm_dsw_adap_en; ///< reg_nlm_dsw_adap_en ++ unsigned char bnlmdsw_lpf_en; ///< reg_nlm_dsw_lpf_en ++ unsigned char bnlm_region_adap_en; ///< reg_nlm_region_adap_en ++ EN_VIP_NLM_DSW_TYPE u8nlm_region_adap_size_config; ///< reg_nlm_region_adap_size_config 0:16x8 1:32x16 ++ unsigned char bnlm_bypass_en; ///< reg_nlm_bypass_en ++ unsigned char u8nlm_fin_gain; ///< reg_nlm_fin_gain ++ unsigned char u8nlm_sad_shift; ///< reg_nlm_sad_shift ++ unsigned char u8nlm_sad_gain; ///< reg_nlm_sad_gain ++ unsigned char u8nlm_dsw_ratio; ///< reg_nlm_dsw_ratio ++ unsigned char u8nlm_dsw_offset; ///< reg_nlm_dsw_offset ++ unsigned char u8nlm_dsw_shift; ///< reg_nlm_dsw_shift ++ unsigned char u8nlm_weight_lut[VIP_NLM_WEIGHT_NUM]; ///< reg_nlm_weight_lut0-31 ,Qmap has adjust register squence ++ unsigned char u8nlm_luma_adap_gain_lut[VIP_NLM_LUMAGAIN_NUM]; ///< reg_nlm_luma_adap_gain_lut0-63,adjust register squence ++ unsigned char u8nlm_post_luma_adap_gain_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_nlm_post_luma_adap_gain_lut0-15,adjust register squence ++ unsigned char u8nlm_dist_weight_7x7_lut[VIP_NLM_DISTWEIGHT_NUM]; ///< reg_nlm_dist_weight_7x7_lut0-8,adjust register squence ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_MAIN_CONFIG; ++/** ++* Used to setup NLM autodown load of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< enable auto downlaod ++ unsigned long u32Baseadr; ///< auto download phy addr ++ unsigned long u32viradr; ///< disable auto download need virtual ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_SRAM_CONFIG; ++/** ++* Used to setup NLM config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_NLM_MAIN_CONFIG stNLM; ///< NLM setting ++ ST_IOCTL_VIP_NLM_SRAM_CONFIG stSRAM; ///< Autodownload ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_CONFIG; ++ ++ ++/** ++* Used to setup 422to444 of vip device ++*/ ++typedef struct ++{ ++ unsigned char bvip_422to444_en; ///< reg_vip_422to444_en ++ unsigned char u8vip_422to444_md; ///< reg_vip_422to444_md ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_422_444_CONFIG; ++ ++/** ++* Used to setup bypass MACE of vip device ++*/ ++typedef struct ++{ ++ unsigned char bvip_fun_bypass_en; ///< reg_vip_fun_bypass_en :except DNR,SNR,NLM,LDC ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_BYPASS_CONFIG; ++ ++/** ++* Used to setup the LB of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8vps_sram_act; ///< reg_vps_sram_act ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LINEBUFFER_CONFIG; ++/** ++* Used to setup mix vip of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_422_444_CONFIG st422_444; ///< 422 to 444 ++ ST_IOCTL_VIP_BYPASS_CONFIG stBypass; ///< bypass ++ ST_IOCTL_VIP_LINEBUFFER_CONFIG stLB; ///< VIP Mixed ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_CONFIG; ++ ++/** ++* Used to setup PK HLPF of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8main_y_lpf_coef; ///< reg_main_y_lpf_coef ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_HLPF_CONFIG; ++ ++/** ++* Used to setup PK HLPF dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char hlpf_dither_en; ///< reg_hlpf_dither_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_HLPF_DITHER_CONFIG; ++ ++/** ++* Used to setup PK VLPF of vip device ++*/ ++typedef struct ++{ ++ unsigned char main_v_lpf_coef; ///< reg_main_v_lpf_coef_1,2 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_VLPF_COEF_CONFIG; ++ ++/** ++* Used to PK VLPF dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char vlpf_dither_en; ///< reg_vlpf_dither_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_VLPF_DITHER_CONFIG; ++ ++ ++/** ++* Used to setup PK onoff of vip device ++*/ ++typedef struct ++{ ++ unsigned char bpost_peaking_en; ///< reg_main_post_peaking_en ++ unsigned char u8vps_sram_act; ///< reg_vps_sram_act ++ unsigned char u8band6_dia_filter_sel; ///< reg_main_band6_dia_filter_sel ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ONOFFCONFIG; ++ ++/** ++* Used to setup PK band of vip device ++*/ ++typedef struct ++{ ++ unsigned char bBand_En[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_peaking_en 1-8 ++ unsigned char u8Band_COEF_STEP[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coef_step 1-8 ++ unsigned char u8Band_COEF[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coef 1-8 ++ unsigned char u8peaking_term[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_main_peaking_term1_select 1-16 ++ unsigned char u8Band_Over[VIP_PEAKING_BAND_NUM]; ///< reg_band1_overshoot_limit 1-8 ++ unsigned char u8Band_Under[VIP_PEAKING_BAND_NUM]; ///< reg_band1_undershoot_limit 1-8 ++ unsigned char u8Band_coring_thrd[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coring_thrd 1-8 ++ unsigned char u8alpha_thrd; ///< reg_main_alpha_thrd ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_BAND_CONFIG; ++ ++/** ++* Used to setup pk adptive of vip device ++*/ ++typedef struct ++{ ++ unsigned char badaptive_en[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_adaptive_en 1-8 ++ unsigned char u8hor_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_hor_lut_0-15 ++ unsigned char u8ver_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_ver_lut_0-15 ++ unsigned char u8low_diff_thrd_and_adaptive_gain_step[VIP_PEAKING_BAND_TERM_NUM]; ///< alternation(reg_band1_adaptive_gain_step, reg_band1_low_diff_thrd) 1-8 ++ unsigned char u8dia_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_dia_lut_0-15 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ADPTIVE_CONFIG; ++ ++/** ++* Used to setup PK preCoring of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8coring_thrd_1; ///< reg_main_coring_thrd_1 ++ unsigned char u8coring_thrd_2; ///< reg_main_coring_thrd_2 ++ unsigned char u8coring_thrd_step; ///< reg_main_coring_thrd_step ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_PCORING_CONFIG; ++ ++/** ++* Used to setup pk ADP_Y of vip device ++*/ ++typedef struct ++{ ++ unsigned char bcoring_adp_y_en; ///< reg_main_coring_adp_y_en ++ unsigned char bcoring_adp_y_alpha_lpf_en; ///< reg_main_coring_adp_y_alpha_lpf_en ++ unsigned char u8coring_y_low_thrd; ///< reg_main_coring_y_low_thrd ++ unsigned char u8coring_adp_y_step; ///< reg_main_coring_adp_y_step ++ unsigned char u8coring_adp_y_alpha_lut[VIP_PEAKING_ADP_Y_LUT_NUM]; ///< reg_main_coring_adp_y_alpha_lut_0-7 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ADP_Y_CONFIG; ++ ++/** ++* Used to setup PK gain of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8osd_sharpness_ctrl ; ///< reg_main_osd_sharpness_ctrl ++ unsigned char bosd_sharpness_sep_hv_en; ///< reg_main_osd_sharpness_sep_hv_en ++ unsigned char u8osd_sharpness_ctrl_h ; ///< reg_main_osd_sharpness_ctrl_h ++ unsigned char u8osd_sharpness_ctrl_v ; ///< reg_main_osd_sharpness_ctrl_v ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_GAIN_CONFIG; ++ ++/** ++* Used to setup PK adpy gain of vip device ++*/ ++typedef struct ++{ ++ unsigned char bpk_adp_y_en; ///< reg_main_coring_adp_y_en ++ unsigned char bpk_adp_y_alpha_lpf_en; ///< reg_main_coring_adp_y_alpha_lpf_en ++ unsigned char u8pk_y_low_thrd; ///< reg_main_coring_y_low_thrd ++ unsigned char u8pk_adp_y_step; ///< reg_main_coring_adp_y_step ++ unsigned char u8pk_adp_y_alpha_lut[VIP_PEAKING_ADP_Y_LUT_NUM]; ///< reg_main_coring_adp_y_alpha_lut_0-7 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_GAIN_ADP_Y_CONFIG; ++ ++/** ++* Used to setup pk yc gain of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16Dlc_in_y_gain; ///< reg_dlc_in_y_gain 16bit ++ unsigned short u16Dlc_in_y_offset; ///< reg_dlc_in_y_offset 16 bit ++ unsigned short u16Dlc_in_c_gain; ///< reg_dlc_in_c_gain 16 bit ++ unsigned short u16Dlc_in_c_offset; ///< reg_dlc_in_c_offset 16 bit ++ unsigned short u16Dlc_out_y_gain; ///< reg_dlc_out_y_gain 16 bit ++ unsigned short u16Dlc_out_y_offset;///< reg_dlc_out_y_offset 16 bit ++ unsigned short u16Dlc_out_c_gain; ///< reg_dlc_out_c_gain 16 bit ++ unsigned short u16Dlc_out_c_offset;///< reg_dlc_out_c_offset 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_YC_GAIN_OFFSET_CONFIG; ++ ++/** ++* Used to setup pk config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_HLPF_CONFIG stHLPF; ///< HLPF ++ ST_IOCTL_VIP_HLPF_DITHER_CONFIG stHLPFDith; ///< HDither ++ ST_IOCTL_VIP_VLPF_COEF_CONFIG stVLPFcoef1; ///< VLPF coef1 ++ ST_IOCTL_VIP_VLPF_COEF_CONFIG stVLPFcoef2; ///< VLPF coef2 ++ ST_IOCTL_VIP_VLPF_DITHER_CONFIG stVLPFDith; ///< VDither ++ ST_IOCTL_VIP_PEAKING_ONOFFCONFIG stOnOff; ///< pkonoff ++ ST_IOCTL_VIP_PEAKING_BAND_CONFIG stBand; ///< pkband ++ ST_IOCTL_VIP_PEAKING_ADPTIVE_CONFIG stAdp; ///< pk adp ++ ST_IOCTL_VIP_PEAKING_PCORING_CONFIG stPcor; ///< pk precore ++ ST_IOCTL_VIP_PEAKING_ADP_Y_CONFIG stAdpY; ///< pk adp y ++ ST_IOCTL_VIP_PEAKING_GAIN_CONFIG stGain; ///< pk gain ++ ST_IOCTL_VIP_PEAKING_GAIN_ADP_Y_CONFIG stGainAdpY; ///< pk Y gain ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_CONFIG; ++ ++ ++/** ++* Used to setup LCE of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_En; ///< LCE en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_ONOFF_CONFIG; ++ ++ ++/** ++* Used to setup LCE dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_Dither_En; ///< LCE dither ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_DITHER_CONFIG; ++ ++/** ++* Used to setup LCE config of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_sodc_alpha_en; ///< reg_main_lce_sodc_alpha_en ++ unsigned char bLce_dering_alpha_en; ///< reg_main_lce_dering_alpha_en ++ EN_VIP_LCE_Y_AVE_SEL_TYPE enLce_y_ave_sel; ///< reg_main_lce_y_ave_sel (1'b1: 5x7; 1'b0:5x11) ++ unsigned char bLce_3curve_en; ///< reg_lce_3curve_en ++ unsigned char u8Lce_std_slop1; ///< reg_main_lce_std_slop1 ++ unsigned char u8Lce_std_slop2; ///< reg_main_lce_std_slop2 ++ unsigned char u8Lce_std_th1; ///< reg_main_lce_std_th1 ++ unsigned char u8Lce_std_th2; ///< reg_main_lce_std_th2 ++ unsigned char u8Lce_gain_min; ///< reg_main_lce_gain_min ++ unsigned char u8Lce_gain_max; ///< reg_main_lce_gain_max ++ unsigned char u8Lce_sodc_low_alpha; ///< reg_main_lce_sodc_low_alpha ++ unsigned char u8Lce_sodc_low_th; ///< reg_main_lce_sodc_low_th ++ unsigned char u8Lce_sodc_slop; ///< reg_main_lce_sodc_slop ++ unsigned char u8Lce_diff_gain; ///< reg_main_lce_diff_gain ++ unsigned char u8Lce_gain_complex; ///< reg_main_lce_gain_complex ++ unsigned char u8Lce_dsw_minsadgain; ///< reg_dsptch_lce_dsw_minsadgain ++ unsigned char u8Lce_dsw_gain; ///< reg_dsptch_lce_dsw_gian ++ unsigned char u8LCE_dsw_thrd; ///< reg_dsptch_lce_dsw_thrd ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_SETTING_CONFIG; ++ ++/** ++* Used to setup LCE curve of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8Curve_Thread[4]; ///< reg_main_lce_curve_a-d ++ unsigned short u16Curve1[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut1_08-f8 (lsb|msb) 16bit ++ unsigned short u16Curve2[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut2_08-f8 (lsb|msb) 16bit ++ unsigned short u16Curve3[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut3_08-f8 (lsb|msb) 16bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_CRUVE_CONFIG; ++ ++/** ++* Used to setup LCE of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_LCE_ONOFF_CONFIG stOnOff; ///< bEn ++ ST_IOCTL_VIP_LCE_DITHER_CONFIG stDITHER; ///< dither ++ ST_IOCTL_VIP_LCE_SETTING_CONFIG stSet; ///< config ++ ST_IOCTL_VIP_LCE_CRUVE_CONFIG stCurve; ///< curve ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_CONFIG; ++ ++/** ++* Used to setup DLC prog of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8VARCP[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_curve_fit_var_cp1 -64 ++ unsigned char u8Tbln0; ///< reg_main_curve_table_n0 ++ unsigned char u8Tbln0LSB; ///< reg_main_curve_table_n0_LSB ++ unsigned char u8Tbln0sign; ///< reg_main_curve_table_n0_sign ++ unsigned short u16Tbl64; ///< reg_main_curve_table64 16 bit ++ unsigned char u8Tbl64LSB; ///< reg_main_curve_table64_LSB ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_PROG_CONFIG; ++ ++//IOCTL_VIP_SET_DLC_CURVE_CONFIG ++/** ++* Used to setup DLC curve config of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8InLuma[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_main_curve_table0-63 ++ unsigned char u8InLumaLSB[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_main_curve_table0-63 LSB ++ ST_IOCTL_VIP_DLC_PROG_CONFIG ProgCfg; ///< dlc proc ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_CURVE_CONFIG; ++ ++/** ++* Used to DLC enable of vip device ++*/ ++typedef struct ++{ ++ unsigned char bcurve_fit_var_pw_en; ///< reg_main_curve_fit_var_pw_en ++ ST_IOCTL_VIP_DLC_CURVE_CONFIG stCurve; ///< curve config ++ unsigned char bcurve_fit_en; ///< reg_main_curve_fit_en ++ unsigned char bstatistic_en; ///< reg_main_statistic_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_ENABLE_CONFIG; ++ ++/** ++* Used to setup dic dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char bDLCdither_en; ///< bdlc dither ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_DITHER_CONFIG; ++ ++/** ++* Used to setup DLC range of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8brange_en; ///< brange ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_EN_CONFIG; ++ ++/** ++* Used to setup DLC H of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16statistic_h_start; ///< reg_main_statistic_h_start 16 bit ++ unsigned short u16statistic_h_end; ///< reg_main_statistic_h_end 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_H_CONFIG; ++ ++/** ++* Used to setup DLC V of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16statistic_v_start; ///< reg_main_statistic_v_start 16 bit ++ unsigned short u16statistic_v_end; ///< reg_main_statistic_v_end 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_V_CONFIG; ++ ++/** ++* Used to setup DLC PC of vip device ++*/ ++typedef struct ++{ ++ unsigned char bhis_y_rgb_mode_en; ///< reg_his_y_rgb_mode_en ++ unsigned char bcurve_fit_rgb_en; ///< reg_main_curve_fit_rgb_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_PC_CONFIG; ++/** ++* Used to setup DLC of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_YC_GAIN_OFFSET_CONFIG stGainOffset; ///< Gain ++ ST_IOCTL_VIP_DLC_ENABLE_CONFIG stEn; ///< EN ++ ST_IOCTL_VIP_DLC_DITHER_CONFIG stDither; ///< Dither ++ ST_IOCTL_VIP_DLC_HISTOGRAM_EN_CONFIG sthist; ///< hist ++ ST_IOCTL_VIP_DLC_HISTOGRAM_H_CONFIG stHistH; /// ++ ++#define WARP_IOC_MAGIC 'I' ++#define WARP_IOC_TRIGGER _IOW(WARP_IOC_MAGIC, 1, MHAL_WARP_CONFIG*) ++ ++#endif //_MDRV_WARP_IO_H_ +\ No newline at end of file +diff --git a/drivers/sstar/include/mdrv_warp_io_st.h b/drivers/sstar/include/mdrv_warp_io_st.h +new file mode 100755 +index 000000000000..643080d4d519 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_warp_io_st.h +@@ -0,0 +1,149 @@ ++#ifndef _MDRV_WARP_IO_ST_H_ ++#define _MDRV_WARP_IO_ST_H_ ++ ++#include ++#include ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++/// @brief MHAL WARP operation modes enumeration ++typedef enum ++{ ++ MHAL_WARP_OP_MODE_PERSPECTIVE = 0, ++ MHAL_WARP_OP_MODE_MAP = 1 ++} MHAL_WARP_OP_MODE_E; ++ ++/// @brief MHAL WARP image formats enumeration ++typedef enum ++{ ++ MHAL_WARP_IMAGE_FORMAT_RGBA = 0, ++ MHAL_WARP_IMAGE_FORMAT_YUV422 = 1, ++ MHAL_WARP_IMAGE_FORMAT_YUV420 = 2 ++} MHAL_WARP_IMAGE_FORMAT_E; ++ ++/// @brief MHAL WARP perspective coefficients enumeration ++typedef enum ++{ ++ MHAL_WARP_PERSECTIVE_COEFFS_C00 = 0, ++ MHAL_WARP_PERSECTIVE_COEFFS_C01 = 1, ++ MHAL_WARP_PERSECTIVE_COEFFS_C02 = 2, ++ MHAL_WARP_PERSECTIVE_COEFFS_C10 = 3, ++ MHAL_WARP_PERSECTIVE_COEFFS_C11 = 4, ++ MHAL_WARP_PERSECTIVE_COEFFS_C12 = 5, ++ MHAL_WARP_PERSECTIVE_COEFFS_C20 = 6, ++ MHAL_WARP_PERSECTIVE_COEFFS_C21 = 7, ++ MHAL_WARP_PERSECTIVE_COEFFS_C22 = 8, ++ MHAL_WARP_PERSECTIVE_COEFFS_NUM_COEFFS = 9 ++} MHAL_WARP_PERSECTIVE_COEFFS_E; ++ ++/// @brief MHAL WARP displacement map resolution enumeration ++typedef enum ++{ ++ MHAL_WARP_MAP_RESLOUTION_8X8 = 0, ++ MHAL_WARP_MAP_RESLOUTION_16X16 = 1 ++} MHAL_WARP_MAP_RESLOUTION_E; ++ ++/// @brief MHAL WARP displacement map format enumeration ++typedef enum ++{ ++ MHAL_WARP_MAP_FORMAT_ABSOLUTE = 0, ++ MHAL_WARP_MAP_FORMAT_RELATIVE = 1 ++} MHAL_WARP_MAP_FORMAT_E; ++ ++/// @brief WARP image plane index enumeration ++typedef enum ++{ ++ MHAL_WARP_IMAGE_PLANE_RGBA = 0, ++ MHAL_WARP_IMAGE_PLANE_Y = 0, ++ MHAL_WARP_IMAGE_PLANE_UV = 1 ++} MHAL_WARP_IMAGE_PLANE_E; ++ ++typedef enum ++{ ++ MHAL_WARP_INSTANCE_STATE_READY = 0, ++ MHAL_WARP_INSTANCE_STATE_PROCESSING = 1, ++ MHAL_WARP_INSTANCE_STATE_DONE = 2, ++ MHAL_WARP_INSTANCE_STATE_AXI_ERROR = 3, ++ MHAL_WARP_INSTANCE_STATE_PROC_ERROR = 4 ++} MHAL_WARP_INSTANCE_STATE_E; ++ ++typedef enum ++{ ++ MHAL_WARP_ISR_STATE_DONE = 0, ++ MHAL_WARP_ISR_STATE_PROCESSING = 1 ++} MHAL_WARP_ISR_STATE_E; ++ ++/// @brief MHAL WARP displacement map entry for absolute coordinates format ++typedef struct ++{ ++ __s32 y; ++ __s32 x; ++} MHAL_WARP_DISPPLAY_ABSOLUTE_ENTRY_T; ++ ++/// @brief MHAL WARP displacement map entry for coordinates' relative offset format ++typedef struct ++{ ++ __s16 y; ++ __s16 x; ++} MHAL_WARP_DISPPLAY_RELATIVE_ENTRY_T; ++ ++/// @brief MHAL WARP displacement table descriptor ++typedef struct ++{ ++ MHAL_WARP_MAP_RESLOUTION_E resolution; // map resolution ++ MHAL_WARP_MAP_FORMAT_E format; // map format (absolute, relative) ++ __s32 size; // size of Disp. ++ __u64 table; ++} MHAL_WARP_DISPLAY_TABLE_T; ++ ++typedef struct ++{ ++ __s16 height; // input tile height ++ __s16 width; // input tile width ++ __s16 y; // input tile top left y coordinate ++ __s16 x; // input tile top left x coordinate ++} MHAL_WARP_BOUND_BOX_ENTRY_T; ++ ++typedef struct ++{ ++ __s32 size; // bytes of bound boxes ++ __u64 table; // list of all bound boxes ++}MHAL_WARP_BOUND_BOX_TABLE_T; ++ ++/// @brief MHAL WARP image descriptor ++typedef struct ++{ ++ MHAL_WARP_IMAGE_FORMAT_E format; // image format ++ __u32 width; // image width (for YUV - Y plane width) ++ __u32 height; // image height (for YUV - Y plane width) ++} MHAL_WARP_IMAGE_DESC_T; ++ ++/// @brief MHAL WARP image data structure ++typedef struct ++{ ++ __u32 num_planes; // number of image planes ++ __u64 data[2]; // pointers to the image planes' data ++} MHAL_WARP_IMAGE_DATA_T; ++ ++/// @brief MHAL WARP hardware configuration structure ++typedef struct ++{ ++ MHAL_WARP_OP_MODE_E op_mode; // Operation mode ++ MHAL_WARP_DISPLAY_TABLE_T disp_table; // Displacement table descriptor ++ MHAL_WARP_BOUND_BOX_TABLE_T bb_table; // Bounding box table descriptor ++ ++ int coeff[MHAL_WARP_PERSECTIVE_COEFFS_NUM_COEFFS]; // Perspective transform coefficients ++ ++ MHAL_WARP_IMAGE_DESC_T input_image; // Input image ++ MHAL_WARP_IMAGE_DATA_T input_data; ++ ++ MHAL_WARP_IMAGE_DESC_T output_image; // Output image ++ MHAL_WARP_IMAGE_DATA_T output_data; ++ ++ __u8 fill_value[2]; // Fill value for out of range pixels ++ ++} MHAL_WARP_CONFIG; ++ ++#endif // _MDRV_WARP_IO_ST_H_ +diff --git a/drivers/sstar/include/mdrv_xpm_io.h b/drivers/sstar/include/mdrv_xpm_io.h +new file mode 100755 +index 000000000000..a60c90e17104 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_xpm_io.h +@@ -0,0 +1,28 @@ ++/* ++* mdrv_xpm_io.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_XPM_IO_H_ ++#define _MDRV_XPM_IO_H_ ++ ++#define XPM_IOCTL_MAGIC 'S' ++ ++#define IOCTL_XPM_REGISTER_SOURCE _IO(XPM_IOCTL_MAGIC, 0x81) ++#define IOCTL_XPM_DEREGISTER_SOURCE _IO(XPM_IOCTL_MAGIC, 0x82) ++#define IOCTL_XPM_MAXNR 0x83 ++ ++ ++#endif +diff --git a/drivers/sstar/include/mdrv_xpm_io_st.h b/drivers/sstar/include/mdrv_xpm_io_st.h +new file mode 100755 +index 000000000000..8d31f0dac4c2 +--- /dev/null ++++ b/drivers/sstar/include/mdrv_xpm_io_st.h +@@ -0,0 +1,39 @@ ++/* ++* mdrv_xpm_io_st.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MDRV_XPM_IO_ST_H_ ++#define _MDRV_XPM_IO_ST_H_ ++ ++ ++typedef enum ++{ ++ XPM_STATE_SUSPENDING =0x01, ++ XPM_STATE_SUSPENDED =0x02, ++ XPM_STATE_SUSPEND_ABORT =0x04, ++ XPM_STATE_WAKEUPED =0x08, ++ XPM_STATE_END =0xFFFFFFFF ++}EN_XPM_STATE; ++ ++ ++typedef enum ++{ ++ XPM_SOURCE_ACTIVE =0x10, ++ XPM_SOURCE_STANDBY =0x20, ++ XPM_SOURCE_STATUS_END=0xFFFFFFFF, ++}EN_XPM_SOURCE_STATUS; ++ ++#endif +diff --git a/drivers/sstar/include/ms_msys.h b/drivers/sstar/include/ms_msys.h +new file mode 100755 +index 000000000000..72848803a463 +--- /dev/null ++++ b/drivers/sstar/include/ms_msys.h +@@ -0,0 +1,56 @@ ++/* ++* ms_msys.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MS_MSYS_H_ ++#define _MS_MSYS_H_ ++ ++#include "mdrv_msys_io_st.h" ++#include "linux/proc_fs.h" ++ ++#define MSYS_REBOOT_BY_WDT_RST 1 ++#define MSYS_REBOOT_BY_SW_RST 2 ++#define MSYS_REBOOT_BY_HW_RST 3 ++ ++extern int msys_release_dmem(MSYS_DMEM_INFO *mem_info); ++extern int msys_request_dmem(MSYS_DMEM_INFO *mem_info); ++extern void ms_records_irq(MSYS_IRQ_INFO *irq_info); ++extern void msys_set_rebootType(u16 arg); ++extern void msys_dump_irq_info(void); ++extern void ms_records_sirq(MSYS_IRQ_INFO *irq_info); ++extern void msys_dump_sirq_info(void); ++extern void ms_dump_irq_count(void); ++extern struct proc_dir_entry* msys_get_proc_zen(void); ++extern struct proc_dir_entry* msys_get_proc_zen_kernel(void); ++extern struct proc_dir_entry* msys_get_proc_zen_mi(void); ++extern struct proc_dir_entry* msys_get_proc_zen_omx(void); ++extern struct class *msys_get_sysfs_class(void); ++ ++extern void ms_record_large_latency_in_top(MSYS_IRQ_INFO *irq_info); ++void msys_print(const char *fmt, ...); ++void msys_prints(const char *string, int length); ++void msys_prints(const char *string, int length); ++extern int msys_read_uuid(unsigned long long* udid); ++extern int msys_dma_blit(MSYS_DMA_BLIT *cfg); ++extern int msys_dma_fill(MSYS_DMA_FILL *cfg); ++extern int msys_dma_copy(MSYS_DMA_COPY *cfg); ++#if defined(CONFIG_MS_BDMA_LINE_OFFSET_ON) ++extern int msys_dma_fill_lineoffset(MSYS_DMA_FILL_BILT *pstDmaCfg); ++extern int msys_dma_copy_lineoffset(MSYS_DMA_BLIT *cfg); ++#endif ++extern int ssys_get_HZ(void); ++ ++#endif +diff --git a/drivers/sstar/include/ms_platform.h b/drivers/sstar/include/ms_platform.h +new file mode 100755 +index 000000000000..13156daccea4 +--- /dev/null ++++ b/drivers/sstar/include/ms_platform.h +@@ -0,0 +1,156 @@ ++/* ++* ms_platform.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MS_PLATFORM_H__ ++#define __MS_PLATFORM_H__ ++ ++#include "mdrv_device_id.h" ++#include "linux/proc_fs.h" ++ ++#define MS_IO_OFFSET 0xDE000000 ++/* macro to get at MMIO space when running virtually */ ++#define IO_ADDRESS(x) ( (u32)(x) + MS_IO_OFFSET ) ++//#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n)) ++ ++// Register macros ++#define GET_REG_ADDR(x, y) ((x) + ((y) << 2)) ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++ ++/* read register by byte */ ++#define ms_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) ++ ++/* read register by word */ ++#define ms_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++ ++/* read register by long */ ++#define ms_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) ++ ++/* write register by byte */ ++#define ms_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) ++ ++/* write register by word */ ++#define ms_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++ ++/* write register by long */ ++#define ms_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Macros: INREGx/OUTREGx/SETREGx/CLRREGx ++// ++// This macros encapsulates basic I/O operations. ++// Memory address space operation is used on all platforms. ++// ++#define INREG8(x) ms_readb(x) ++#define OUTREG8(x, y) ms_writeb((u8)(y), x) ++#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y)) ++#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y)) ++#define INREGMSK8(x, y) (INREG8(x) & (y)) ++#define OUTREGMSK8(x, y, z) OUTREG8(x, ((INREG8(x)&~(z))|((y)&(z)))) ++ ++#define INREG16(x) ms_readw(x) ++#define OUTREG16(x, y) ms_writew((u16)(y), x) ++#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) ++#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) ++#define INREGMSK16(x, y) (INREG16(x) & (y)) ++#define OUTREGMSK16(x, y, z) OUTREG16(x, ((INREG16(x)&~(z))|((y)&(z)))) ++ ++#define INREG32(x) ms_readl(x) ++#define OUTREG32(x, y) ms_writel((u32)(y), x) ++#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y)) ++#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y)) ++#define INREGMSK32(x, y) (INREG32(x) & (y)) ++#define OUTREGMSK32(x, y, z) OUTREG32(x, ((INREG32(x)&~(z))|((y)&(z)))) ++ ++ ++#define PM_READ32(x) ((((unsigned int)INREG16(x+4)<<16)&0xFFFF0000) | (INREG16(x) & 0x0000FFFF)) ++#define PM_WRITE32(x,y) do{OUTREG16(x,(y&0x0000FFFF));OUTREG16((x+4),((y>>16)&0x0000FFFF));}while(0) ++ ++#define XTAL_26000K 26000000 ++#define XTAL_24000K 24000000 ++#define XTAL_16369K 16369000 ++#define XTAL_16367K 16367000 ++ ++#define STR_HELPER(x) #x ++#define STR(x) STR_HELPER(x) ++ ++struct MS_BIN_OPTION ++{ ++ u8 name[8]; ++ u8 args[8]; ++}; ++ ++typedef enum ++{ ++ MS_BOOT_DEV_NONE=0x00, ++ MS_BOOT_DEV_SPI=0x01, ++ MS_BOOT_DEV_EMMC=0x02, ++ MS_BOOT_DEV_8051=0x03, ++} MS_BOOT_DEV_TYPE; ++ ++typedef enum ++{ ++ MS_STORAGE_UNKNOWN =0x00, ++ MS_STORAGE_NOR, ++ MS_STORAGE_NAND, ++ MS_STORAGE_EMMC, ++ MS_STORAGE_SPINAND_ECC, ++ MS_STORAGE_SPINAND_NOECC, ++} MS_STORAGE_TYPE; ++ ++extern void Chip_Flush_MIU_Pipe(void); ++extern void Chip_Flush_Memory(void); ++extern void Chip_Read_Memory(void); ++ ++extern int Chip_Cache_Outer_Is_Enabled(void); ++extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++extern void Chip_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size); ++extern void Chip_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size); ++extern void Chip_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size); ++extern void Chip_Flush_CacheAll(void); ++ ++extern u64 Chip_Phys_to_MIU(u64 phys); ++extern u64 Chip_MIU_to_Phys(u64 miu); ++ ++extern char* Chip_Get_Platform_Name(void); ++extern int Chip_Get_Device_ID(void); ++extern int Chip_Get_Revision(void); ++ ++extern int Chip_Boot_Get_Dev_Type(void); ++extern unsigned long long Chip_Get_RIU_Phys(void); ++extern int Chip_Get_RIU_Size(void); ++extern int Chip_Function_Set(int function_id, int param); ++ ++extern int Chip_Get_Storage_Type(void); ++extern int Chip_Get_Package_Type(void); ++extern u64 Chip_Get_US_Ticks(void); ++ ++typedef enum ++{ ++ CHIP_FUNC_UART_ENABLE_LINE=0x0001, ++ CHIP_FUNC_UART_DISABLE_LINE, ++ CHIP_FUNC_IR_ENABLE, ++ CHIP_FUNC_USB_VBUS_CONTROL, ++ CHIP_FUNC_MCM_DISABLE_ID, ++ CHIP_FUNC_MCM_ENABLE_ID, ++ CHIP_FUNC_END, ++ CHIP_FUNC_DUMMY=0xFFFF ++} EN_CHIP_FUNC_ID; ++ ++#endif +diff --git a/drivers/sstar/include/ms_types.h b/drivers/sstar/include/ms_types.h +new file mode 100755 +index 000000000000..eefdb74fd147 +--- /dev/null ++++ b/drivers/sstar/include/ms_types.h +@@ -0,0 +1,25 @@ ++/* ++* ms_types.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MS_TYPE_H__ ++#define __MS_TYPE_H__ ++ ++#include "mdrv_types.h" ++ ++ ++#endif // __MS_TYPE_H__ ++ +diff --git a/drivers/sstar/include/mst_platform.h b/drivers/sstar/include/mst_platform.h +new file mode 100755 +index 000000000000..eb39fb6c1c2c +--- /dev/null ++++ b/drivers/sstar/include/mst_platform.h +@@ -0,0 +1,138 @@ ++/* ++* mst_platform.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MST_PLATFORM_H__ ++#define __MST_PLATFORM_H__ ++ ++#define _6BITS 0 ++#define _8BITS 1 ++#define _10BITS 2 ++ ++#define _TTL 0 ++#define _TCON 1 ++#define _LVDS 2 ++#define _RSDS 3 ++ ++#define _SINGLE 0 ++#define _DUAL 1 ++#define _QUAD 2 ++#define _QUAD_LR 3 ++ ++// for Lvds output channel, ++// REG_321F[7:6]=>D, [5:4]=>C, [3:2]=>B, [1:0]=>A ++#define CHANNEL_SWAP(D, C, B, A) ((D<<6)&0xC0)|((C<<4)&0x30)|((B<<2)&0x0C)|(A&0x03) ++#define _CH_A 0 ++#define _CH_B 1 ++#define _CH_C 2 ++#define _CH_D 3 ++ ++//For titania control setting; REG_MOD40 [2]=>TI/JATA [5]=>P_N_SWAP [6]=>LSB_MSB_SWAP ++#define MOD40(TI_JA, P_N_SWAP, L_M_SWAP, DCLK_DLY) (((TI_JA<<2)&0x04)|((P_N_SWAP<<5)&0x20)|((L_M_SWAP<<6)&0x40)|((DCLK_DLY<<7)&0x0F00)) ++#define _TI 1 ++#define _JEIDA 0 ++#define _L_M_SWAP_ON 1 ++#define _L_M_SWAP_OFF 0 ++#define _P_N_SWAP_ON 1 ++#define _P_N_SWAP_OFF 0 ++ ++/*For titania control setting; REG_MOD49[3]=>SWAP_ODD_RB, ++ [4]=>SWAP_EVEN_RB, ++ [5]=>SWAP_ODD_ML, ++ [6]=>SWAP_EVEN_ML, ++*/ ++#define MOD49(EVEN_ML, EVEN_RB, ODD_ML, ODD_RB, BIT_NUM) \ ++ (((EVEN_ML<<14)&0x4000)|((EVEN_RB<<13)&0x2000)|\ ++ ((ODD_ML<<12)&0x1000)|((ODD_RB<<11)&0x0800)) ++#define _10BITS_OP 0 ++#define _6BITS_OP 1 ++#define _8BITS_OP 2 ++#define _ODD_RB_OFF 0 ++#define _ODD_RB_ON 1 ++#define _ODD_ML_OFF 0 ++#define _ODD_ML_ON 1 ++#define _EVEN_RB_OFF 0 ++#define _EVEN_RB_ON 1 ++#define _EVEN_ML_OFF 0 ++#define _EVEN_ML_ON 1 ++ ++/*For titania control setting; REG_MOD4A[0]=>ODD_EVEN_SWAP, ++ [1]=>SINGLE_DUAL_CHANNEL ++ [2]=>INVERT_DATA_ENABLE ++ [3]=>INVERT_VSYNC ++ [4]=>INVERT_DCLK ++ [12]=>INVERT_HSYNC ++*/ ++#define MOD4A(INV_HSYNC, INV_DCLK, INV_VSYNC, INV_DE, SD_CH, OE_SWAP) \ ++ (((INV_VSYNC<<12)&0x1000)|((INV_VSYNC<<4)&0x10)|\ ++ ((INV_VSYNC<<3)&0x08)|((INV_DE<<2)&0x04)|\ ++ ((SD_CH<<1)&0x02)|(OE_SWAP&0x01)) ++#define _ODD_EVEN_SWAP_OFF 0 ++#define _ODD_EVEN_SWAP_ON 1 ++#define _INV_DE_OFF 0 ++#define _INV_DE_ON 1 ++#define _INV_VSYNC_OFF 0 ++#define _INV_VSYNC_ON 1 ++#define _INV_DCLK_OFF 0 ++#define _INV_DCLK_ON 1 ++#define _INV_HSYNC_OFF 0 ++#define _INV_HSYNC_ON 1 ++ ++//For titania control setting; REG_MOD4B[0:1]=>0x: 10-bits, 10: 8-bits, 11: 6-bits ++#define MOD4B(TI_BIT_MOD) (TI_BIT_MOD&0x03) ++#define _TI_10_BITS 0 ++#define _TI_8_BITS 2 ++#define _TI_6_BITS 3 ++//------------------------------------------------------------------------------------------------- ++// Board ++//------------------------------------------------------------------------------------------------- ++typedef struct MST_BOARD_INFO_s ++{ ++ ++} MST_BOARD_INFO_t, *PMST_BOARD_INFO_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Panel ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct MST_PANEL_INFO_s ++{ ++ // Basic ++ U16 u16HStart; //ursa scaler ++ U16 u16VStart; //ursa scaler ++ U16 u16Width; //ursa scaler ++ U16 u16Height; //ursa scaler ++ U16 u16HTotal; //ursa scaler ++ U16 u16VTotal; //ursa scaler ++ U16 u16DefaultVFreq; ++ U8 u8LPLL_Type; ++ U8 u8LPLL_Mode; ++ U8 u8HSyncWidth; ++} MST_PANEL_INFO_t, *PMST_PANEL_INFO_t; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Platform ++//------------------------------------------------------------------------------------------------- ++typedef struct MST_PLATFORM_INFO_s ++{ ++ MST_BOARD_INFO_t board; ++ MST_PANEL_INFO_t panel; ++} MST_PLATFORM_INFO_t, *PMST_PLATFORM_INFO_t; ++ ++ ++#endif // __MST_PLATFORM_H__ +diff --git a/drivers/sstar/include/mstar_chip.h b/drivers/sstar/include/mstar_chip.h +new file mode 100755 +index 000000000000..159d82180ad6 +--- /dev/null ++++ b/drivers/sstar/include/mstar_chip.h +@@ -0,0 +1,50 @@ ++/* ++* mstar_chip.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifdef CONFIG_ARM_LPAE ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000UL ++#define MSTAR_MIU1_BUS_BASE 0x200000000ULL ++ ++#define ARM_MIU0_BUS_BASE MSTAR_MIU0_BUS_BASE ++#define ARM_MIU1_BUS_BASE MSTAR_MIU1_BUS_BASE ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFFFFFFFFFFULL ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFFFFFFFFFFULL ++ ++#define ARM_MIU0_BASE_ADDR 0x00000000UL ++#define ARM_MIU1_BASE_ADDR 0x80000000UL ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFFFFFFFFFFULL ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFFFFFFFFFFULL ++ ++#else ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000UL ++#define MSTAR_MIU1_BUS_BASE 0xA0000000UL ++ ++#define ARM_MIU0_BUS_BASE MSTAR_MIU0_BUS_BASE ++#define ARM_MIU1_BUS_BASE MSTAR_MIU1_BUS_BASE ++#define ARM_MIU2_BUS_BASE 0xFFFFFFFFUL ++#define ARM_MIU3_BUS_BASE 0xFFFFFFFFUL ++ ++#define ARM_MIU0_BASE_ADDR 0x00000000UL ++#define ARM_MIU1_BASE_ADDR 0x80000000UL ++#define ARM_MIU2_BASE_ADDR 0xFFFFFFFFUL ++#define ARM_MIU3_BASE_ADDR 0xFFFFFFFFUL ++ ++#endif // CONFIG_ARM_LPAE ++ ++extern unsigned int query_frequency(void); +diff --git a/drivers/sstar/include/prom.h b/drivers/sstar/include/prom.h +new file mode 100755 +index 000000000000..cd61ab502b14 +--- /dev/null ++++ b/drivers/sstar/include/prom.h +@@ -0,0 +1,56 @@ ++/* ++* prom.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MIPS_PROM_H ++#define _MIPS_PROM_H ++ ++typedef enum ++{ ++ LINUX_MEM, ++ EMAC_MEM, ++ MPOOL_MEM, ++ LINUX_MEM2, ++ LINUX_MEM3, ++ G3D_MEM0, ++ G3D_MEM1, ++ G3D_CMDQ, ++ DRAM, ++ BB, ++ GMAC_MEM ++}BOOT_MEM_INFO; ++ ++char *prom_getcmdline(void); ++char *prom_getenv(char *name); ++void prom_init_cmdline(void); ++void prom_meminit(void); ++void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); ++void mips_display_message(const char *str); ++void mips_display_word(unsigned int num); ++void mips_scroll_message(void); ++int get_ethernet_addr(char *ethernet_addr); ++void get_boot_mem_info(BOOT_MEM_INFO type, phys_addr_t *addr, phys_addr_t *len); ++ ++/* Memory descriptor management. */ ++#define PROM_MAX_PMEMBLOCKS 32 ++struct prom_pmemblock { ++ unsigned long base; /* Within KSEG0. */ ++ unsigned int size; /* In bytes. */ ++ unsigned int type; /* free or prom memory */ ++}; ++ ++#endif /* !(_MIPS_PROM_H) */ +diff --git a/drivers/sstar/include/region_substract.h b/drivers/sstar/include/region_substract.h +new file mode 100755 +index 000000000000..455b76da85c6 +--- /dev/null ++++ b/drivers/sstar/include/region_substract.h +@@ -0,0 +1,179 @@ ++/* ++* region_substract.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REGIONSUBSTRACT_H_ ++#define _REGIONSUBSTRACT_H_ ++ ++typedef int BOOL; ++typedef unsigned char BYTE; ++typedef void *PBLOCKHEAP; ++ ++/** ++ * A rectangle defined by coordinates of corners. ++ * ++ * \note The lower-right corner does not belong to the rectangle, ++ * i.e. the bottom horizontal line and the right vertical line are excluded ++ * from the retangle. ++ * ++ * \sa PRECT, GAL_Rect ++ */ ++typedef struct _RECT ++{ ++ /** ++ * The x coordinate of the upper-left corner of the rectangle. ++ */ ++ int left; ++ /** ++ * The y coordinate of the upper-left corner of the rectangle. ++ */ ++ int top; ++ /** ++ * The x coordinate of the lower-right corner of the rectangle. ++ */ ++ int right; ++ /** ++ * The y coordinate of the lower-right corner of the rectangle. ++ */ ++ int bottom; ++} RECT; ++/** ++ * \var typedef RECT* PRECT ++ * \brief Data type of the pointer to a RECT. ++ * ++ * \sa RECT ++ */ ++typedef RECT* PRECT; ++ ++ /** ++ * \defgroup region_fns Region operations ++ * ++ * A Region is simply an area, as the name implies, and is implemented as ++ * a "y-x-banded" array of rectangles. To explain: Each Region is made up ++ * of a certain number of rectangles sorted by y coordinate first, ++ * and then by x coordinate. ++ * ++ * Furthermore, the rectangles are banded such that every rectangle with a ++ * given upper-left y coordinate (y1) will have the same lower-right y ++ * coordinate (y2) and vice versa. If a rectangle has scanlines in a band, it ++ * will span the entire vertical distance of the band. This means that some ++ * areas that could be merged into a taller rectangle will be represented as ++ * several shorter rectangles to account for shorter rectangles to its left ++ * or right but within its "vertical scope". ++ * ++ * An added constraint on the rectangles is that they must cover as much ++ * horizontal area as possible. E.g. no two rectangles in a band are allowed ++ * to touch. ++ * ++ * Whenever possible, bands will be merged together to cover a greater ++ * vertical distance (and thus reduce the number of rectangles). Two bands ++ * can be merged only if the bottom of one touches the top of the other and ++ * they have rectangles in the same places (of the same width, of course). ++ * This maintains the y-x-banding that's so nice to have... ++ * ++ * Example: ++ * ++ * \include region.c ++ * ++ * @{ ++ */ ++ ++/** ++ * Clipping rectangle structure. ++ */ ++typedef struct _CLIPRECT ++{ ++ /** ++ * The clipping rectangle itself. ++ */ ++ RECT rc; ++ /** ++ * The next clipping rectangle. ++ */ ++ struct _CLIPRECT* next; ++ /** ++ * The previous clipping rectangle. ++ */ ++ struct _CLIPRECT* prev; ++} CLIPRECT; ++typedef CLIPRECT* PCLIPRECT; ++ ++/* Clipping Region */ ++#define NULLREGION 0x00 ++#define SIMPLEREGION 0x01 ++#define COMPLEXREGION 0x02 ++ ++/** ++ * Clipping region structure, alos used for general regions. ++ */ ++typedef struct _CLIPRGN ++{ ++ /** ++ * Type of the region, can be one of the following: ++ * - NULLREGION\n ++ * A null region. ++ * - SIMPLEREGION\n ++ * A simple region. ++ * - COMPLEXREGION\n ++ * A complex region. ++ */ ++ BYTE type; ++ /** ++ * Reserved for alignment. ++ */ ++ BYTE reserved[3]; ++ /** ++ * The bounding rect of the region. ++ */ ++ RECT rcBound; ++ /** ++ * Head of the clipping rectangle list. ++ */ ++ PCLIPRECT head; ++ /** ++ * Tail of the clipping rectangle list. ++ */ ++ PCLIPRECT tail; ++ /** ++ * The private block data heap used to allocate clipping rectangles. ++ * \sa BLOCKHEAP ++ */ ++ PBLOCKHEAP heap; ++} CLIPRGN; ++ ++/** ++ * \var typedef CLIPRGN* PCLIPRGN ++ * \brief Data type of the pointer to a CLIPRGN. ++ * ++ * \sa CLIPRGN ++ */ ++typedef CLIPRGN* PCLIPRGN; ++ ++#define region_for_each_rect(rect, rgn) \ ++ for(rect=((rgn)->head)?(&((rgn)->head->rc)):NULL; \ ++ rect; \ ++ rect=(container_of(rect, CLIPRECT, rc)->next)?&(container_of(rect, CLIPRECT, rc)->next->rc):NULL) ++ ++void dbg_dumpRegion (CLIPRGN* region); ++BOOL IsEmptyClipRgn (const CLIPRGN* pRgn); ++void EmptyClipRgn (PCLIPRGN pRgn); ++void InitClipRgn (PCLIPRGN pRgn, PBLOCKHEAP heap); ++BOOL AddClipRect (PCLIPRGN region, const RECT *rect); ++BOOL SubtractRegion (CLIPRGN *rgnD, const CLIPRGN *rgnM, const CLIPRGN *rgnS); ++int region_substract_init(void); ++int region_substract_deinit(void); ++ ++#endif +\ No newline at end of file +diff --git a/drivers/sstar/include/vcore_defs.h b/drivers/sstar/include/vcore_defs.h +new file mode 100644 +index 000000000000..b17de53bf671 +--- /dev/null ++++ b/drivers/sstar/include/vcore_defs.h +@@ -0,0 +1,34 @@ ++/* ++* vcore_defs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __VCORE_DEFS_H ++#define __VCORE_DEFS_H ++ ++#define VOLTAGE_CORE_INIT 0 ++#define VOLTAGE_CORE_850 850 ++#define VOLTAGE_CORE_900 900 ++#define VOLTAGE_CORE_950 950 ++#define VOLTAGE_CORE_1000 1000 ++#define VOLTAGE_CORE_NO_CTRL 0xDEAD ++ ++#define VID_MAX_GPIO_CNT 2 ++ ++#define VID_LOW 0 ++#define VID_HIGH 1 ++#define VID_INPUT 2 ++ ++#endif //__VCORE_DEFS_H +diff --git a/drivers/sstar/include/voltage_ctrl.h b/drivers/sstar/include/voltage_ctrl.h +new file mode 100755 +index 000000000000..afeefd31f161 +--- /dev/null ++++ b/drivers/sstar/include/voltage_ctrl.h +@@ -0,0 +1,36 @@ ++/* ++* voltage_ctrl.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef __VOLTAGE_CTRL_H ++#define __VOLTAGE_CTRL_H ++ ++#include "voltage_ctrl_demander.h" ++ ++#define VOLTAGE_CORE_850 850 ++#define VOLTAGE_CORE_900 900 ++#define VOLTAGE_CORE_950 950 ++#define VOLTAGE_CORE_1000 1000 ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL_WITH_OSC ++int sync_core_voltage_with_OSC_and_TEMP(int useTT); ++#endif ++void set_core_voltage(VOLTAGE_DEMANDER_E demander, int mV); ++int get_core_voltage(void); ++int core_voltage_available(unsigned int **voltages, unsigned int *num); ++int core_voltage_pin(unsigned int **pins, unsigned int *num); ++ ++#endif //__VOLTAGE_CTRL_H +diff --git a/drivers/sstar/iopower/Kconfig b/drivers/sstar/iopower/Kconfig +new file mode 100755 +index 000000000000..8900c5431a9d +--- /dev/null ++++ b/drivers/sstar/iopower/Kconfig +@@ -0,0 +1,4 @@ ++config MS_IOPOWER ++ bool ++ depends on ARCH_INFINITY6E ++ default y +diff --git a/drivers/sstar/iopower/Makefile b/drivers/sstar/iopower/Makefile +new file mode 100755 +index 000000000000..ba00a96498e3 +--- /dev/null ++++ b/drivers/sstar/iopower/Makefile +@@ -0,0 +1,14 @@ ++# ++# Makefile for MStar IO Power device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mdrv_iopower.o ++ +diff --git a/drivers/sstar/iopower/mdrv_iopower.c b/drivers/sstar/iopower/mdrv_iopower.c +new file mode 100755 +index 000000000000..a5c46d940c78 +--- /dev/null ++++ b/drivers/sstar/iopower/mdrv_iopower.c +@@ -0,0 +1,158 @@ ++/* ++* mdrv_iopower.c- Sigmastar ++* ++* Copyright (C) 2019 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_types.h" ++#include ++#include ++#include "iopow.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++#define IOPOW_DBG_ENABLE 0 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if IOPOW_DBG_ENABLE ++ #define IOPOW_DBG_PRINT(x, args...) { printk(x, ##args); } ++#else ++ #define IOPOW_DBG_PRINT(x, args...) { } ++#endif ++ ++struct ss_iopow_info { ++ struct platform_device *pdev; ++ void __iomem *reg_base; ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Implementation ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------ ++// Function : ss_iopow_Set_IO_Voltage ++// Description : This function is used for set io voltage. ++//------------------------------------------------------------------------------ ++static void ss_iopow_Set_IO_Voltage(struct device *dev, u32 offset, u32 shift, u32 val) ++{ ++ struct ss_iopow_info *info = dev_get_drvdata(dev); ++ u16 reg; ++ ++ reg = readw(info->reg_base + offset); ++ reg &= ~(1<reg_base + offset); ++} ++ ++static int _mdrv_iopow_dts(struct device *dev) ++{ ++ ++ int ret = 0; ++ int val; ++ ++ ret = of_property_read_u32(dev->of_node, "pm_sar_atop_vddp1", &val); ++ if (ret < 0 && ret != -EINVAL) ++ { ++ IOPOW_DBG_PRINT("[%s][%d] of_property_read_u32 (pm_sar_atop_vddp1) fail\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ IOPOW_DBG_PRINT("[%s][%d] pm_sar_atop_vddp1= (%d)\n", __FUNCTION__, __LINE__, val); ++ ss_iopow_Set_IO_Voltage(dev, PM_SAR_ATOP_VDDP1, PM_SAR_ATOP_VDDP1_BIT, val); ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "pm_sar_atop_pmspi", &val); ++ if (ret < 0 && ret != -EINVAL) ++ { ++ IOPOW_DBG_PRINT("[%s][%d] of_property_read_u32 fail (pm_sar_atop_pmspi)\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ IOPOW_DBG_PRINT("[%s][%d] pm_sar_atop_pmspi (%d)\n", __FUNCTION__, __LINE__, val); ++ ss_iopow_Set_IO_Voltage(dev, PM_SAR_ATOP_LDO18, PM_SAR_ATOP_LDO18_BIT, val); ++ } ++ ++ return 0; ++} ++ ++static int sstar_iopow_probe(struct platform_device *pdev) ++{ ++ struct ss_iopow_info *info; ++ struct resource *res; ++ ++ info = devm_kzalloc(&pdev->dev, sizeof(struct ss_iopow_info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ IOPOW_DBG_PRINT("IOPOW initial\n"); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ IOPOW_DBG_PRINT("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ ++ info->reg_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(info->reg_base)) ++ return PTR_ERR(info->reg_base); ++ ++ info->pdev = pdev; ++ platform_set_drvdata(pdev, info); ++ ++ _mdrv_iopow_dts(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id sstar_iopow_of_match[] = { ++ { .compatible = "sstar-iopower" }, ++ { }, ++}; ++ ++static struct platform_driver sstar_iopow_driver = { ++ .driver = { ++ .name = "iopower", ++ .owner = THIS_MODULE, ++ .of_match_table = sstar_iopow_of_match, ++ }, ++ .probe = sstar_iopow_probe, ++}; ++ ++static int __init sstar_iopow_init(void) ++{ ++ return platform_driver_register(&sstar_iopow_driver); ++} ++postcore_initcall_sync(sstar_iopow_init); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("io power driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/ir/Kconfig b/drivers/sstar/ir/Kconfig +new file mode 100755 +index 000000000000..488676b5e96a +--- /dev/null ++++ b/drivers/sstar/ir/Kconfig +@@ -0,0 +1,7 @@ ++config MS_IR ++ ++tristate "SStar IR driver" ++ default n ++ help ++ enable support for IR driver ++ +diff --git a/drivers/sstar/ir/Makefile b/drivers/sstar/ir/Makefile +new file mode 100755 +index 000000000000..794b463ccd05 +--- /dev/null ++++ b/drivers/sstar/ir/Makefile +@@ -0,0 +1,11 @@ ++# ++# Makefile for kernel IR drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/ir/include ++ ++obj-$(CONFIG_MS_IR) += ms_ir.o +diff --git a/drivers/sstar/ir/include/IR_CONFIG.h b/drivers/sstar/ir/include/IR_CONFIG.h +new file mode 100755 +index 000000000000..5ead31491ecd +--- /dev/null ++++ b/drivers/sstar/ir/include/IR_CONFIG.h +@@ -0,0 +1,33 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (C) 2018 Sigmastar Technology Corp. ++// All rights reserved. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef IR_CONFIG_H ++#define IR_CONFIG_H ++ ++#define IR_TYPE_OLD 0 ++#define IR_TYPE_NEW 1 ++#define IR_TYPE_MSTAR_DTV 2 ++#define IR_TYPE_MSTAR_RAW 3 ++#define IR_TYPE_RC_V16 4 ++#define IR_TYPE_CUS03_DTV 5 ++#define IR_TYPE_MSTAR_FANTASY 6 ++#define IR_TYPE_MSTAR_SZ1 7 ++#define IR_TYPE_CUS08_RC5 8 ++#define IR_TYPE_CUS21SH 9 ++#define IR_TYPE_RCMM 10 ++ ++#define IR_TYPE_SEL IR_TYPE_MSTAR_DTV ++ ++#if (IR_TYPE_SEL == IR_TYPE_MSTAR_DTV) ++#include "IR_MSTAR_DTV.h" ++#elif (IR_TYPE_SEL == IR_TYPE_RCMM) ++#include "IR_RCMM.h" ++#else ++#include "IR_MSTAR_DTV.h" ++#endif ++ ++#endif +diff --git a/drivers/sstar/ir/include/IR_MSTAR_DTV.h b/drivers/sstar/ir/include/IR_MSTAR_DTV.h +new file mode 100755 +index 000000000000..ab5cde9105f6 +--- /dev/null ++++ b/drivers/sstar/ir/include/IR_MSTAR_DTV.h +@@ -0,0 +1,112 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (C) 2018 Sigmastar Technology Corp. ++// All rights reserved. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef IR_FORMAT_H ++#define IR_FORMAT_H ++ ++#include ++ ++#define IR_VENDOR_ID 0x3697 ++#define IR_INPUT_NAME "mstar ir" ++#define IR_MAP_NAME "rc-mstar-dtv" ++ ++// IR Header code define ++#define IR_HEADER_CODE0 0x80 // Custom 0 ++#define IR_HEADER_CODE1 0x7F // Custom 1 ++ ++// IR Timing define ++#define IR_HEADER_CODE_TIME 9000 // us ++#define IR_OFF_CODE_TIME 4500 // us ++#define IR_OFF_CODE_RP_TIME 2500 // us ++#define IR_LOGI_01H_TIME 560 // us ++#define IR_LOGI_0_TIME 1120 // us ++#define IR_LOGI_1_TIME 2240 // us ++#define IR_TIMEOUT_CYC 140000 // us ++ ++#define IR_EVENT_TIMEOUT 220 ++ ++static struct rc_map_table mstar_tv[] = { ++ { 0x0046, KEY_POWER }, ++ { 0x0050, KEY_0 }, ++ { 0x0049, KEY_1 }, ++ { 0x0055, KEY_2 }, ++ { 0x0059, KEY_3 }, ++ { 0x004D, KEY_4 }, ++ { 0x0051, KEY_5 }, ++ { 0x005D, KEY_6 }, ++ { 0x0048, KEY_7 }, ++ { 0x0054, KEY_8 }, ++ { 0x0058, KEY_9 }, ++ { 0x0047, KEY_RED }, ++ { 0x004B, KEY_GREEN }, ++ { 0x0057, KEY_YELLOW }, ++ { 0x005B, KEY_BLUE }, ++ { 0x0052, KEY_UP }, ++ { 0x0013, KEY_DOWN }, ++ { 0x0006, KEY_LEFT }, ++ { 0x001A, KEY_RIGHT }, ++ { 0x000F, KEY_ENTER }, ++ { 0x001F, KEY_CHANNELUP }, ++ { 0x0019, KEY_CHANNELDOWN }, ++ { 0x0016, KEY_VOLUMEUP }, ++ { 0x0015, KEY_VOLUMEDOWN }, ++ { 0x0003, KEY_PAGEUP }, ++ { 0x0005, KEY_PAGEDOWN }, ++ { 0x0017, KEY_HOME}, ++ { 0x0007, KEY_MENU }, ++ { 0x001B, KEY_BACK }, ++ { 0x005A, KEY_MUTE }, ++ { 0x000D, KEY_RECORD }, // DVR ++ { 0x0042, KEY_HELP }, // GUIDE ++ { 0x0014, KEY_INFO }, ++ { 0x0040, KEY_KP0 }, // WINDOW ++ { 0x0004, KEY_KP1 }, // TV_INPUT ++ { 0x000E, KEY_REWIND }, ++ { 0x0012, KEY_FORWARD }, ++ { 0x0002, KEY_PREVIOUSSONG }, ++ { 0x001E, KEY_NEXTSONG }, ++ { 0x0001, KEY_PLAY }, ++ { 0x001D, KEY_PAUSE }, ++ { 0x0011, KEY_STOP }, ++ { 0x0044, KEY_AUDIO }, // (C)SOUND_MODE ++ { 0x0056, KEY_CAMERA }, // (C)PICTURE_MODE ++ { 0x004C, KEY_ZOOM }, // (C)ASPECT_RATIO ++ { 0x005C, KEY_CHANNEL }, // (C)CHANNEL_RETURN ++ { 0x0045, KEY_SLEEP }, // (C)SLEEP ++ { 0x004A, KEY_EPG }, // (C)EPG ++ { 0x0010, KEY_LIST }, // (C)LIST ++ { 0x0053, KEY_SUBTITLE }, // (C)SUBTITLE ++ { 0x0041, KEY_FN_F1 }, // (C)MTS ++ { 0x004E, KEY_FN_F2 }, // (C)FREEZE ++ { 0x000A, KEY_FN_F3 }, // (C)TTX ++ { 0x0009, KEY_FN_F4 }, // (C)CC ++ { 0x001C, KEY_FN_F5 }, // (C)TV_SETTING ++ { 0x0008, KEY_FN_F6 }, // (C)SCREENSHOT ++ { 0x000B, KEY_F1 }, // MSTAR_BALANCE ++ { 0x0018, KEY_F2 }, // MSTAR_INDEX ++ { 0x0000, KEY_F3 }, // MSTAR_HOLD ++ { 0x000C, KEY_F4 }, // MSTAR_UPDATE ++ { 0x004F, KEY_F5 }, // MSTAR_REVEAL ++ { 0x005E, KEY_F6 }, // MSTAR_SUBCODE ++ { 0x0043, KEY_F7 }, // MSTAR_SIZE ++ { 0x005F, KEY_F8 }, // MSTAR_CLOCK ++ { 0x00FE, KEY_POWER2 }, // FAKE_POWER ++ { 0x00FF, KEY_OK }, // KEY_OK ++ ++ // 2nd IR controller. ++}; ++ ++static struct rc_map_list mdrv_rc_map = { ++ .map = { ++ .scan = mstar_tv, ++ .size = ARRAY_SIZE(mstar_tv), ++ .rc_type = RC_TYPE_UNKNOWN, /* Legacy IR type */ ++ .name = IR_MAP_NAME, ++ } ++}; ++ ++#endif +diff --git a/drivers/sstar/ir/ms_ir.c b/drivers/sstar/ir/ms_ir.c +new file mode 100755 +index 000000000000..c541910822d8 +--- /dev/null ++++ b/drivers/sstar/ir/ms_ir.c +@@ -0,0 +1,715 @@ ++/* ++ * ms_ir.c ++ * ++ * Created on: ++ * Author: Administrator ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "IR_CONFIG.h" ++#include "reg_ir.h" ++#include "ms_ir.h" ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++#endif ++#define IR_DBG 0 ++#if IR_DBG ++ #define ir_dbg(args...) printk(args) ++ #define ir_err(args...) printk(args) ++ #define ir_info(args...) printk(args) ++#else ++ #define ir_dbg(args...) ++ #define ir_err(args...) ++ #define ir_info(args...) //printk(args) ++#endif ++ ++#define IR_MODE_SEL IR_MODE_FULLDECODE ++ ++/************************************************************** ++ *struct ++ *************************************************************/ ++struct sstar_ir_dev ++{ ++ int irq; ++ int protocol; ++ void __iomem *membase; ++ struct rc_dev *dev; ++ struct completion key_done; ++ ++ int workrun; ++ struct work_struct key_dispatch_wk; ++ struct workqueue_struct *key_dispatch_wq; ++#ifdef CONFIG_CAM_CLK ++ void *pvIrClk; ++#endif ++}; ++ ++static struct sstar_ir_dev *gIr_Dev; ++ ++#define READ_WORD(bank) (*(volatile u16*)(gIr_Dev->membase + ((bank)<<2))) ++#define WRITE_WORD(bank, val) (*(volatile u16*)(gIr_Dev->membase + ((bank)<<2))) = (u16)(val) ++ ++//#define USE_POLLING_MODE ++#ifdef USE_POLLING_MODE ++struct work_struct key_polling_wk; ++struct workqueue_struct *key_polling_wq; ++#endif ++/************************************************************** ++ *function ++ *************************************************************/ ++ ++static struct Key_Queue queue; ++static DEFINE_SEMAPHORE(queue_lock); ++static void _key_enqueue(u32 data) ++{ ++ if (down_trylock(&queue_lock)) ++ return; ++ ++ if (queue.front == ((queue.rear + 1) % MaxQueue)) ++ { ++ ir_dbg("queue is full \n"); ++ } ++ else ++ { ++ queue.item[queue.rear] = data; ++ queue.rear = (queue.rear + 1) % MaxQueue; ++ } ++ ++ up(&queue_lock); ++} ++ ++static u32 _key_dequeue(void) ++{ ++ u32 data = 0xFFFF; ++ ++ down(&queue_lock); ++ ++ if (queue.front == queue.rear) ++ { ++ ir_dbg("queue is empty \n"); ++ } ++ else ++ { ++ data = queue.item[queue.front]; ++ queue.front = (queue.front + 1) % MaxQueue; ++ } ++ ++ up(&queue_lock); ++ return data; ++} ++ ++unsigned long _mdrv_get_sys_time(void) ++{ ++ return((unsigned long)((jiffies)*(1000/HZ))); ++} ++ ++static U8 _mdrv_read_fifo(void) ++{ ++ U8 keyVal = 0; ++ U16 regVal = 0; ++ ++ keyVal = READ_WORD(REG_IR_CKDIV_NUM_KEY_DATA)>>8; ++ regVal = READ_WORD(REG_IR_FIFO_RD_PULSE)|0x01; ++ WRITE_WORD(REG_IR_FIFO_RD_PULSE,regVal); ++ ++ return keyVal; ++} ++ ++static void _mdrv_clear_fifo(void) ++{ ++ U16 regVal = 0; ++ ++ regVal = READ_WORD(REG_IR_SEPR_BIT_FIFO_CTRL); ++ regVal |= 0x01 << 15; ++ WRITE_WORD(REG_IR_SEPR_BIT_FIFO_CTRL,regVal); ++} ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE) ++static void _mdrv_set_sw_decode(int bEnable) ++{ ++ U16 regVal = 0; ++ ++ regVal = READ_WORD(REG_IR_SEPR_BIT_FIFO_CTRL); ++ if(bEnable) ++ { ++ regVal |= 0x01<<14; ++ regVal |= 0x01<<6; ++ } ++ else ++ { ++ regVal &= ~(0x01<<14); ++ regVal &= ~(0x01<<6); ++ } ++ WRITE_WORD(REG_IR_SEPR_BIT_FIFO_CTRL,regVal); ++} ++#endif ++ ++static void _mdrv_set_timing(void) ++{ ++ // header code upper/lower bound ++ WRITE_WORD(REG_IR_HDC_UPB,IR_HDC_UPB); ++ WRITE_WORD(REG_IR_HDC_LOB, IR_HDC_LOB); ++ ++ // off code upper/lower bound ++ WRITE_WORD(REG_IR_OFC_UPB, IR_OFC_UPB); ++ WRITE_WORD(REG_IR_OFC_LOB, IR_OFC_LOB); ++ ++ // off code repeat upper/lower bound ++ WRITE_WORD(REG_IR_OFC_RP_UPB, IR_OFC_RP_UPB); ++ WRITE_WORD(REG_IR_OFC_RP_LOB, IR_OFC_RP_LOB); ++ ++ // logical 0/1 high upper/lower bound ++ WRITE_WORD(REG_IR_LG01H_UPB, IR_LG01H_UPB); ++ WRITE_WORD(REG_IR_LG01H_LOB, IR_LG01H_LOB); ++ ++ // logical 0 upper/lower bound ++ WRITE_WORD(REG_IR_LG0_UPB, IR_LG0_UPB); ++ WRITE_WORD(REG_IR_LG0_LOB, IR_LG0_LOB); ++ ++ // logical 1 upper/lower bound ++ WRITE_WORD(REG_IR_LG1_UPB, IR_LG1_UPB); ++ WRITE_WORD(REG_IR_LG1_LOB, IR_LG1_LOB); ++ ++ // timeout cycles ++ WRITE_WORD(REG_IR_TIMEOUT_CYC_L, IR_RP_TIMEOUT&0xFFFF); ++ //set up ccode bytes and code bytes/bits num ++ WRITE_WORD(REG_IR_TIMEOUT_CYC_H, IR_CCB_CB | 0x30UL | ((IR_RP_TIMEOUT >> 16)&0x0F)); ++ ++ WRITE_WORD(REG_IR_CKDIV_NUM_KEY_DATA, IR_CKDIV_NUM); ++} ++ ++void _mdrv_set_int_enable(U8 bEnable) ++{ ++#ifndef USE_POLLING_MODE ++ if (bEnable) ++ { ++ enable_irq(gIr_Dev->irq); ++ } ++ else ++ { ++ disable_irq(gIr_Dev->irq); ++ } ++#endif ++} ++ ++static void _key_dispatch_thread(struct work_struct *work) ++{ ++ int ret = 0; ++ U32 currKey = 0; ++ static u32 preKey = 0xFFFF; ++ struct sstar_ir_dev *ir_dev = container_of(work, struct sstar_ir_dev, key_dispatch_wk); ++ ++ ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ while(ir_dev->workrun) ++ { ++ try_to_freeze(); ++ ++ if (preKey == 0xFFFF) ++ { ++ //ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ ret = wait_for_completion_interruptible(&ir_dev->key_done); ++ } ++ else ++ { ++ //ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ // Depend on different IR to wait timeout. ++ // IR_TYPE_MSTAR_DTV, 150 is better, because ISR need such time to get another ir key. ++ // ++ // NOTE: ++ // Too small, you will find the repeat function in android don't work. (up immediately) ++ // It will become down->up->down->down.....(not continue down) ++ // In input driver(2.6.35), over REP_DELAY(250 msecs) will auto-repeat, and every REP_PERIOD(33 msecs) will send repeat key. ++ // In input driver(3.0.20), over REP_DELAY(500 msecs) will auto-repeat, and every REP_PERIOD(125 msecs) will send repeat key. ++ // In android, over DEFAULT_LONG_PRESS_TIMEOUT(500 mesc) will auto-repeat, and every KEY_REPEAT_DELAY(50 mesc) will send repeat key. ++ ret = wait_for_completion_interruptible_timeout(&ir_dev->key_done, msecs_to_jiffies(IR_EVENT_TIMEOUT)); ++ } ++ ++ if (ret < 0) ++ { ++ //ir_dbg("%s:%d %d enter \n",__func__, __LINE__, ret); ++ continue; ++ } ++ ++ currKey = _key_dequeue(); ++ ir_info("%s:%d currKey=0x%x enter \n",__func__, __LINE__, currKey); ++ if ((preKey != 0xFFFF) && (currKey == 0xFFFF)) ++ { ++ //ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ rc_keyup(ir_dev->dev); ++ } ++ else if((preKey != 0xFFFF) ++ && (currKey != 0xFFFF) ++ && (preKey != currKey)) ++ { ++ //ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ rc_keyup(ir_dev->dev); ++ rc_keydown_notimeout(ir_dev->dev,ir_dev->protocol, currKey, 0); ++ } ++ else if((preKey == 0xFFFF) ++ && (currKey != 0xFFFF)) ++ { ++ //ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ rc_keydown_notimeout(ir_dev->dev,ir_dev->protocol, currKey, 0); ++ } ++ ++ preKey = currKey; ++ } ++} ++ ++#if (IR_MODE_SEL == IR_MODE_FULLDECODE) ++static void _mdrv_get_key_fullmode(struct IR_KeyInfo *keyInfo) ++{ ++ U16 regVal=0; ++ U8 currKey=0; ++ static U8 prevKey=0; ++ static int bRepeat=0; ++ static unsigned long prevTime=0; ++ static unsigned long currTime=0; ++ ++ regVal = READ_WORD(REG_IR_SHOT_CNT_H_FIFO_STATUS); ++ if(regVal&IR_FIFO_EMPTY) ++ { ++ bRepeat = 0; ++ keyInfo->u8Valid = 0; ++ return; ++ } ++ ++ currTime = _mdrv_get_sys_time(); ++ if(currTime - prevTime >= IR_TIMEOUT_CYC/1000) ++ { ++ currKey = _mdrv_read_fifo(); ++ bRepeat = 0; ++ prevKey = currKey; ++ keyInfo->u8Key = currKey; ++ keyInfo->u8Valid = 1; ++ } ++ else ++ { ++ if(bRepeat == 0) ++ { ++ bRepeat = 1; ++ keyInfo->u8Valid = 0; ++ } ++ else ++ { ++ currKey = _mdrv_read_fifo(); ++ regVal = READ_WORD(REG_IR_SHOT_CNT_H_FIFO_STATUS); ++ keyInfo->u8Flag = (regVal&IR_RPT_FLAG)?1:0; ++ keyInfo->u8Key = currKey; ++ keyInfo->u8Valid = ((keyInfo->u8Flag)&&(currKey == prevKey)); ++ } ++ } ++ ++ prevTime = currTime; ++ _mdrv_clear_fifo(); ++} ++#elif(IR_MODE_SEL == IR_MODE_RAWDATA) ++#define IR_RAW_DATA_NUM 4 ++static void _mdrv_get_key_rawmode(struct IR_KeyInfo *keyInfo) ++{ ++ U16 i,regVal=0; ++ static int bRepeat=0; ++ static U8 preKey = 0; ++ static U8 keyCount = 0; ++ static U8 rawKey[IR_RAW_DATA_NUM]; ++ ++ regVal = READ_WORD(REG_IR_SHOT_CNT_H_FIFO_STATUS); ++ if(bRepeat == 1 && (regVal&IR_RPT_FLAG) == IR_RPT_FLAG) ++ { ++ bRepeat = 0; ++ keyInfo->u8Valid = 1; ++ keyInfo->u8Key = preKey; ++ _mdrv_clear_fifo(); ++ return; ++ } ++ bRepeat = 1; ++ ++ for(i = 0; i < IR_RAW_DATA_NUM; i++) ++ { ++ regVal = READ_WORD(REG_IR_SHOT_CNT_H_FIFO_STATUS); ++ if(regVal&IR_FIFO_EMPTY) ++ { ++ bRepeat = 0; ++ keyInfo->u8Valid = 0; ++ return; ++ } ++ ++ rawKey[keyCount++] = _mdrv_read_fifo(); ++ if(keyCount == IR_RAW_DATA_NUM) ++ { ++ keyCount = 0; ++ if( (rawKey[0] == IR_HEADER_CODE0) ++ &&(rawKey[1] == IR_HEADER_CODE1) ++ &&(rawKey[2] == (U8)(~rawKey[3]))) ++ { ++ bRepeat = 0; ++ preKey = rawKey[2]; ++ keyInfo->u8Key = rawKey[2]; ++ keyInfo->u8Valid = 1; ++ } ++ } ++ } ++ ++ _mdrv_clear_fifo(); ++} ++#endif ++static int _mdrv_get_key(void) ++{ ++ struct IR_KeyInfo ir_keyInfo; ++ ++ memset((void*)&ir_keyInfo, 0, sizeof(struct IR_KeyInfo)); ++ ++ #if (IR_MODE_SEL == IR_MODE_FULLDECODE) ++ _mdrv_get_key_fullmode(&ir_keyInfo); ++ #elif (IR_MODE_SEL == IR_MODE_RAWDATA) ++ _mdrv_get_key_rawmode(&ir_keyInfo); ++ #endif ++ ++ if(ir_keyInfo.u8Valid) ++ { ++ _key_enqueue(ir_keyInfo.u8System<<8|ir_keyInfo.u8Key); ++ complete(&gIr_Dev->key_done); ++ } ++ ++ return 0; ++} ++ ++#ifndef USE_POLLING_MODE ++irqreturn_t _mdrv_int_handler(int irq, void *dev_id) ++{ ++ return _mdrv_get_key(); ++} ++ ++#else ++static void _key_polling_thread(struct work_struct *work) ++{ ++ while(1) ++ { ++ _mdrv_get_key(); ++ mdelay(100); ++ } ++} ++#endif ++ ++static int _mdrv_input_init(struct sstar_ir_dev *ir_dev) ++{ ++ int err = 0; ++ struct rc_dev *dev; ++ ++ rc_map_register(&mdrv_rc_map); ++ ++ dev=rc_allocate_device(); ++ if (!dev) ++ { ++ ir_err("%s:%d rc_allocate_device failed() \n",__func__, __LINE__); ++ return -ENOMEM; ++ } ++ ++ dev->driver_name = "ir"; ++ dev->map_name = IR_MAP_NAME; ++ dev->driver_type = RC_DRIVER_IR_RAW; ++ dev->allowed_protocols = RC_BIT_ALL; ++ dev->input_name = IR_INPUT_NAME; ++ dev->input_phys = "/dev/ir"; ++ dev->input_id.bustype = BUS_I2C; ++ dev->input_id.vendor = IR_VENDOR_ID; ++ dev->input_id.product = 0x0001; ++ dev->input_id.version = 1; ++ ++ err = rc_register_device(dev); ++ if (err != 0) ++ { ++ rc_free_device(dev); ++ ir_err("%s:%d rc_register_device failed() \n",__func__, __LINE__); ++ return err; ++ } ++ ++ clear_bit(EV_REP, dev->input_dev->evbit); ++ ++ ir_dev->dev=dev; ++ ir_dev->protocol=RC_TYPE_UNKNOWN; ++ init_completion(&ir_dev->key_done); ++ ++ return 0; ++} ++ ++static int _mdrv_input_exit(struct sstar_ir_dev *ir_dev) ++{ ++ rc_unregister_device(ir_dev->dev); ++ rc_free_device(ir_dev->dev); ++ rc_map_unregister(&mdrv_rc_map); ++ ++ return 0; ++} ++ ++static int _mdrv_workqueue_init(struct sstar_ir_dev *ir_dev) ++{ ++ ir_dev->workrun = 1; ++ ir_dev->key_dispatch_wq = create_workqueue("keydispatch_wq"); ++ INIT_WORK(&ir_dev->key_dispatch_wk,_key_dispatch_thread); ++ queue_work(ir_dev->key_dispatch_wq,&ir_dev->key_dispatch_wk); ++ ++ return 0; ++} ++ ++static int _mdrv_workqueue_exit(struct sstar_ir_dev *ir_dev) ++{ ++ ir_dev->workrun = 0; ++ destroy_workqueue(ir_dev->key_dispatch_wq); ++ ++ return 0; ++} ++ ++static int _mdrv_ir_init(void) ++{ ++ U16 regVal = 0; ++ ++ _mdrv_set_timing(); ++ ++ WRITE_WORD(REG_IR_CCODE, (IR_HEADER_CODE1<<8)|IR_HEADER_CODE0); ++ WRITE_WORD(REG_IR_CTRL, 0x01BF); ++ WRITE_WORD(REG_IR_GLHRM_NUM, 0x0804); ++ WRITE_WORD(REG_IR_SEPR_BIT_FIFO_CTRL,0x0F00); ++ ++ if(IR_MODE_SEL == IR_MODE_RAWDATA) ++ { ++ WRITE_WORD(REG_IR_CTRL, 0x01B3); ++ WRITE_WORD(REG_IR_GLHRM_NUM, READ_WORD(REG_IR_GLHRM_NUM)|(0x02<<12)); ++ WRITE_WORD(REG_IR_FIFO_RD_PULSE,READ_WORD(REG_IR_FIFO_RD_PULSE)|0x20); //wakeup key sel ++ } ++ else if(IR_MODE_SEL == IR_MODE_FULLDECODE) ++ { ++ WRITE_WORD(REG_IR_GLHRM_NUM, READ_WORD(REG_IR_GLHRM_NUM)|(0x03<<12)); ++ WRITE_WORD(REG_IR_FIFO_RD_PULSE,READ_WORD(REG_IR_FIFO_RD_PULSE)|0x20); //wakeup key sel ++ } ++ else ++ { ++ WRITE_WORD(REG_IR_GLHRM_NUM, READ_WORD(REG_IR_GLHRM_NUM)|(0x01<<12)); ++ if(IR_TYPE_SEL == IR_TYPE_RCMM) ++ { ++ regVal = READ_WORD(REG_IR_SEPR_BIT_FIFO_CTRL)|(0x01<<12); ++ WRITE_WORD(REG_IR_SEPR_BIT_FIFO_CTRL, regVal); ++ } ++ else ++ { ++ #ifdef IR_INT_NP_EDGE_TRIG ++ regVal = READ_WORD(REG_IR_SEPR_BIT_FIFO_CTRL)|(0x03<<12); ++ WRITE_WORD(REG_IR_SEPR_BIT_FIFO_CTRL, regVal); ++ #else ++ WRITE_WORD(REG_IR_SEPR_BIT_FIFO_CTRL,0x2F00);//[10:8]: FIFO depth, [11]:Enable FIFO full ++ #endif ++ } ++ } ++ ++ #if(IR_MODE_SEL==IR_MODE_SWDECODE) ++ _mdrv_set_sw_decode(1); ++ WRITE_WORD(REG_IR_CKDIV_NUM_KEY_DATA,0x00CF); ++ #endif ++ ++ #if((IR_MODE_SEL==IR_MODE_RAWDATA)||(IR_MODE_SEL==IR_MODE_FULLDECODE)||(IR_MODE_SEL==IR_MODE_SWDECODE)) ++ _mdrv_clear_fifo(); ++ #endif ++ ++ return 0; ++} ++ ++static int mdrv_ir_probe(struct platform_device *pdev) ++{ ++ int retval; ++ struct resource *res; ++ struct sstar_ir_dev *ir_dev; ++#ifdef CONFIG_CAM_CLK ++ u32 IrClk = 0; ++ CAMCLK_Set_Attribute stSetCfg; ++ CAMCLK_Get_Attribute stGetCfg; ++#else ++ struct clk *ir_clk; ++ struct clk_hw *hw_parent; ++#endif ++ ++ ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ ir_dev = devm_kzalloc(&pdev->dev, sizeof(*ir_dev), GFP_KERNEL); ++ if (!ir_dev) ++ { ++ ir_err("%s:%d devm_kzalloc() failed\n",__func__, __LINE__); ++ return -ENOMEM; ++ } ++ ++ ir_dev->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (!ir_dev->irq) ++ { ++ ir_err("%s:%d irq_of_parse_and_map() failed\n",__func__, __LINE__); ++ return -ENODEV; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ir_dev->membase = (void *)(IO_ADDRESS(res->start)); ++#ifdef CONFIG_CAM_CLK ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", 0,&(IrClk)); ++ if (!IrClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ if(CamClkRegister("Ir",IrClk,&(ir_dev->pvIrClk))==CAMCLK_RET_OK) ++ { ++ CamClkAttrGet(ir_dev->pvIrClk,&stGetCfg); ++ CAMCLK_SETPARENT(stSetCfg,stGetCfg.u32Parent[0]); ++ CamClkAttrSet(ir_dev->pvIrClk,&stSetCfg); ++ CamClkSetOnOff(ir_dev->pvIrClk,1); ++ } ++ } ++#else ++ //2. set clk ++ ir_clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(ir_clk)) ++ { ++ retval = PTR_ERR(ir_clk); ++ ir_err("[%s]: of_clk_get failed\n", __func__); ++ } ++ else ++ { ++ /* select clock mux */ ++ hw_parent = clk_hw_get_parent_by_index(__clk_get_hw(ir_clk), 0); ++ ir_dbg( "[%s]parent_num:%d parent[0]:%s\n", __func__, ++ clk_hw_get_num_parents(__clk_get_hw(ir_clk)), clk_hw_get_name(hw_parent)); ++ clk_set_parent(ir_clk, hw_parent->clk); ++ ++ clk_prepare_enable(ir_clk); ++ ir_dbg("[IR] clk_prepare_enable\n"); ++ } ++#endif ++ gIr_Dev = ir_dev; ++ platform_set_drvdata(pdev, &ir_dev); ++ ++ retval = _mdrv_input_init(ir_dev); ++ if(retval != 0) ++ { ++ ir_err("%s:%d mdrv_input_init() failed\n",__func__, __LINE__); ++ return retval; ++ } ++ ++ _mdrv_ir_init(); ++ _mdrv_workqueue_init(ir_dev); ++ ++#ifndef USE_POLLING_MODE ++ retval = request_irq(ir_dev->irq, _mdrv_int_handler, IRQF_SHARED, "IR", ir_dev); ++ if(retval != 0) ++ { ++ ir_err("%s:%d request_irq() failed\n",__func__, __LINE__); ++ _mdrv_input_exit(ir_dev); ++ _mdrv_workqueue_exit(ir_dev); ++ return retval; ++ } ++#else ++ key_polling_wq = create_workqueue("keypolling_wq"); ++ INIT_WORK(&key_polling_wk,_key_polling_thread); ++ queue_work(key_polling_wq,&key_polling_wk); ++#endif ++ ++ return 0; ++} ++ ++static int mdrv_ir_remove(struct platform_device *pdev) ++{ ++ struct sstar_ir_dev *ir_dev = platform_get_drvdata(pdev); ++#ifndef CONFIG_CAM_CLK ++ struct clk *ir_clk; ++#endif ++ ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ _mdrv_set_int_enable(0); ++ _mdrv_workqueue_exit(ir_dev); ++ _mdrv_input_exit(ir_dev); ++ ++#ifndef USE_POLLING_MODE ++ free_irq(ir_dev->irq,ir_dev); ++#else ++ destroy_workqueue(key_polling_wq); ++#endif ++#ifdef CONFIG_CAM_CLK ++ if(ir_dev->pvIrClk) ++ { ++ CamClkSetOnOff(ir_dev->pvIrClk,0); ++ CamClkUnregister(ir_dev->pvIrClk); ++ } ++#else ++ ir_clk = of_clk_get(pdev->dev.of_node, 0); ++ if (IS_ERR(ir_clk)) ++ { ++ ir_err( "[IR] Fail to get clk!\n" ); ++ } ++ else ++ { ++ clk_disable_unprepare(ir_clk); ++ clk_put(ir_clk); ++ } ++#endif ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int mdrv_ir_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ _mdrv_set_int_enable(0); ++ ++ #if(IR_MODE_SEL==IR_MODE_SWDECODE) ++ _mdrv_set_sw_decode(0); ++ #endif ++ ++ return 0; ++} ++ ++static int mdrv_ir_resume(struct platform_device *pdev) ++{ ++ ir_dbg("%s:%d enter \n",__func__, __LINE__); ++ _mdrv_ir_init(); ++ _mdrv_set_int_enable(1); ++ ++ return 0; ++} ++#endif ++ ++static const struct of_device_id sstar_ir_match_table[] = { ++ {.compatible = "sstar,infinity-ir" }, ++ {} ++}; ++ ++static struct platform_driver sstar_ir_driver = { ++ .probe = mdrv_ir_probe, ++ .remove = mdrv_ir_remove, ++#ifdef CONFIG_PM ++ .suspend = mdrv_ir_suspend, ++ .resume = mdrv_ir_resume, ++#endif ++ .driver = { ++ .name = "Sstar-ir", ++ .owner = THIS_MODULE, ++ .of_match_table = sstar_ir_match_table, ++ } ++}; ++ ++module_platform_driver(sstar_ir_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("IR driver"); ++MODULE_LICENSE("GPL"); ++ ++ +diff --git a/drivers/sstar/ir/ms_ir.h b/drivers/sstar/ir/ms_ir.h +new file mode 100755 +index 000000000000..fc21dd5ca013 +--- /dev/null ++++ b/drivers/sstar/ir/ms_ir.h +@@ -0,0 +1,59 @@ ++/* ++ * ms_ir.h ++ * ++ * Created on: ++ * Author: Administrator ++ */ ++ ++#ifndef _MS_IR_H_ ++#define _MS_IR_H_ ++#include "ms_types.h" ++ ++#define IR_MODE_FULLDECODE 1 ++#define IR_MODE_RAWDATA 2 ++#define IR_MODE_SWDECODE 3 //not support now ++#define IR_MODE_SWDECODE_KON 4 //not support now ++ ++#define XTAL_CLOCK_FREQ 12000000 //12 MHz ++//------------------------------------------------------------------------------------------- ++// IR system parameter define for H/W setting (Please don't modify them) ++//------------------------------------------------------------------------------------------- ++#define IR_CKDIV_NUM ((XTAL_CLOCK_FREQ+500000)/1000000) ++#define IR_CLK (XTAL_CLOCK_FREQ/1000000) ++ ++#define irGetMinCnt(time, tolerance) ((u32)(((double)time*((double)IR_CLK)/(IR_CKDIV_NUM+1))*((double)1-tolerance))) ++#define irGetMaxCnt(time, tolerance) ((u32)(((double)time*((double)IR_CLK)/(IR_CKDIV_NUM+1))*((double)1+tolerance))) ++#define irGetCnt(time) ((u32)((double)time*((double)IR_CLK)/(IR_CKDIV_NUM+1))) ++ ++// 90Mhz ++#define IR_RP_TIMEOUT irGetCnt(IR_TIMEOUT_CYC) ++#define IR_HDC_UPB irGetMaxCnt(IR_HEADER_CODE_TIME, 0.2) ++#define IR_HDC_LOB irGetMinCnt(IR_HEADER_CODE_TIME, 0.2) ++#define IR_OFC_UPB irGetMaxCnt(IR_OFF_CODE_TIME, 0.2) ++#define IR_OFC_LOB irGetMinCnt(IR_OFF_CODE_TIME, 0.2) ++#define IR_OFC_RP_UPB irGetMaxCnt(IR_OFF_CODE_RP_TIME, 0.2) ++#define IR_OFC_RP_LOB irGetMinCnt(IR_OFF_CODE_RP_TIME, 0.2) ++#define IR_LG01H_UPB irGetMaxCnt(IR_LOGI_01H_TIME, 0.35) ++#define IR_LG01H_LOB irGetMinCnt(IR_LOGI_01H_TIME, 0.3) ++#define IR_LG0_UPB irGetMaxCnt(IR_LOGI_0_TIME, 0.2) ++#define IR_LG0_LOB irGetMinCnt(IR_LOGI_0_TIME, 0.2) ++#define IR_LG1_UPB irGetMaxCnt(IR_LOGI_1_TIME, 0.2) ++#define IR_LG1_LOB irGetMinCnt(IR_LOGI_1_TIME, 0.2) ++ ++struct IR_KeyInfo ++{ ++ U8 u8Key; ++ U8 u8System; ++ U8 u8Flag; ++ U8 u8Valid; ++}; ++ ++#define MaxQueue 100 ++struct Key_Queue ++{ ++ u32 item[MaxQueue]; ++ int front; ++ int rear; ++}; ++ ++#endif /*_MS_IR_H_ */ +diff --git a/drivers/sstar/ir/reg_ir.h b/drivers/sstar/ir/reg_ir.h +new file mode 100755 +index 000000000000..2b224432d7a9 +--- /dev/null ++++ b/drivers/sstar/ir/reg_ir.h +@@ -0,0 +1,38 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (C) 2018 Sigmastar Technology Corp. ++// All rights reserved. ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_IR_H_ ++#define _REG_IR_H_ ++ ++#define REG_IR_CTRL 0x40 ++#define REG_IR_HDC_UPB 0x41 ++#define REG_IR_HDC_LOB 0x42 ++#define REG_IR_OFC_UPB 0x43 ++#define REG_IR_OFC_LOB 0x44 ++#define REG_IR_OFC_RP_UPB 0x45 ++#define REG_IR_OFC_RP_LOB 0x46 ++#define REG_IR_LG01H_UPB 0x47 ++#define REG_IR_LG01H_LOB 0x48 ++#define REG_IR_LG0_UPB 0x49 ++#define REG_IR_LG0_LOB 0x4A ++#define REG_IR_LG1_UPB 0x4B ++#define REG_IR_LG1_LOB 0x4C ++#define REG_IR_SEPR_UPB 0x4D ++#define REG_IR_SEPR_LOB 0x4E ++#define REG_IR_TIMEOUT_CYC_L 0x4F ++#define REG_IR_TIMEOUT_CYC_H 0x50 ++ #define IR_CCB_CB 0x9F00//ir_ccode_byte:1+ir_code_bit_num:32 ++#define REG_IR_SEPR_BIT_FIFO_CTRL 0x51 ++#define REG_IR_CCODE 0x52 ++#define REG_IR_GLHRM_NUM 0x53 ++#define REG_IR_CKDIV_NUM_KEY_DATA 0x54 ++#define REG_IR_SHOT_CNT_L 0x55 ++#define REG_IR_SHOT_CNT_H_FIFO_STATUS 0x56 ++ #define IR_RPT_FLAG 0x0100 ++ #define IR_FIFO_EMPTY 0x0200 ++#define REG_IR_FIFO_RD_PULSE 0x58 ++ ++#endif // _REG_IR_H_ +diff --git a/drivers/sstar/ircut/Kconfig b/drivers/sstar/ircut/Kconfig +new file mode 100755 +index 000000000000..8a4113d5ae71 +--- /dev/null ++++ b/drivers/sstar/ircut/Kconfig +@@ -0,0 +1,9 @@ ++config MS_IRCUT ++ tristate "ircut driver" ++ help ++ Say Y here to enable the driver for the ircut. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mdrv_ircut. +diff --git a/drivers/sstar/ircut/Makefile b/drivers/sstar/ircut/Makefile +new file mode 100755 +index 000000000000..90b096cec670 +--- /dev/null ++++ b/drivers/sstar/ircut/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_MS_IRCUT) += ms_ircut.o +diff --git a/drivers/sstar/ircut/ms_ircut.c b/drivers/sstar/ircut/ms_ircut.c +new file mode 100755 +index 000000000000..a2fa31fea0d1 +--- /dev/null ++++ b/drivers/sstar/ircut/ms_ircut.c +@@ -0,0 +1,202 @@ ++/* ++* ms_ircut.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include /* for MODULE_ALIAS_MISCDEV */ ++#include ++#include ++#include ++#include ++#include ++#include /* kmalloc, kfree */ ++#include /* class_create */ ++#include /* kobject_uevent */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "irqs.h" ++#include "gpio.h" ++#include "mdrv_types.h" ++ ++extern U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Odn(U8 u8IndexGPIO); ++ ++ ++//#define IRCUT_DEBUG 1 ++u32 mGpioNum=78; ++u32 mIntNum=182; ++#ifdef IRCUT_DEBUG ++#define IRCUT_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define IRCUT_DBG(fmt, arg...) ++#endif ++#define IRCUT_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++ ++static const struct of_device_id ms_ircut_of_match_table[] = { ++ { .compatible = "sstar,infinity-ircut" }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, ms_ircut_of_match_table); ++static irqreturn_t ircut_handler(int irq, struct uio_info *dev_info) ++{ ++ struct irq_data *data; ++ int level; ++ ++ level= MDrv_GPIO_Pad_Read(mGpioNum); ++ IRCUT_DBG("ms_ircut_level=%d\n",level); ++ IRCUT_DBG("ms_ircut_level irq=%d\n",irq); ++ data = irq_get_irq_data(irq); ++ //data->chip->irq_set_type(data, level?1:0); ++ if(!data) ++ return -ENODEV; ++ data->chip->irq_set_type(data, level?IRQ_TYPE_EDGE_FALLING:IRQ_TYPE_EDGE_RISING); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ms_ircut_probe(struct platform_device *pdev) ++{ ++ //struct resource *res; ++ int ret = 0; ++ struct uio_info *info; ++ const struct of_device_id *match; ++ struct device_node *node = pdev->dev.of_node; ++ struct irq_data *data; ++ int level; ++ ++ IRCUT_DBG("ms_ircut_probe\n"); ++ ++ match = of_match_device(ms_ircut_of_match_table, &pdev->dev); ++ if (!match) { ++ printk("Error:[infinity-ircut] No device match found\n"); ++ return -ENODEV; ++ } ++ ++ if (of_property_read_u32(node, "ircut-gpio-num", &mGpioNum)) { ++ pr_err("%s get failed\n", "ircut-gpio-num"); ++ return -ENODEV; ++ } ++ IRCUT_DBG("11111111 u8GpioNum=%d\n",mGpioNum); ++ ++ MDrv_GPIO_Pad_Set(mGpioNum); ++ MDrv_GPIO_Pad_Odn(mGpioNum); ++ info = kzalloc(sizeof(struct uio_info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ ++ /*res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) ++ { ++ IRCUT_ERR("[%s]: failed to get IORESOURCE_IRQ\n", __func__); ++ return -ENODEV; ++ } ++ info->irq=res->start; ++ ++ IRCUT_DBG("info->irq=%ld\n",info->irq); ++*/ ++ info->mem[0].addr = (unsigned long)kmalloc(1024,GFP_KERNEL); ++ ++ if(info->mem[0].addr == 0) ++ { ++ IRCUT_ERR("Invalid memory resource\n"); ++ kfree(info); ++ return -ENOMEM; ++ } ++ ++ info->mem[0].memtype = UIO_MEM_LOGICAL; ++ info->mem[0].size = 1024; ++ info->version = "0.1"; ++ info->name="ircut"; ++ info->irq=irq_of_parse_and_map(pdev->dev.of_node, 0); ++ info->irq_flags = IRQF_SHARED; ++ info->handler = ircut_handler; ++ mIntNum=(int)info->irq; ++ ret = uio_register_device(&pdev->dev, info); ++ if (ret) ++ { ++ IRCUT_ERR("uio_register failed %d\n",ret); ++ //iounmap(info->mem[0].internal_addr); ++ // printk("uio_register failed %d\n",ret); ++ kfree(info); ++ return -ENODEV; ++ } ++ platform_set_drvdata(pdev, info); ++ ++ level= MDrv_GPIO_Pad_Read(mGpioNum); ++ IRCUT_DBG("ms_ircut_probe,level=%d,info->irq=%ld\n",level,info->irq); ++ ++ data = irq_get_irq_data(mIntNum); ++ data->chip->irq_set_type(data, level?1:0); ++ ++ return 0; ++} ++ ++static int ms_ircut_remove(struct platform_device *pdev) ++{ ++ //uio_unregister_device(&ircut_info); ++ IRCUT_DBG("ms_ircut_remove\n"); ++ return 0; ++} ++#ifdef CONFIG_PM ++static int ms_ircut_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ //uio_unregister_device(&ircut_info); ++ IRCUT_DBG("ms_ircut_suspend\n"); ++ return 0; ++} ++ ++static int ms_ircut_resume(struct platform_device *pdev) ++{ ++ //uio_unregister_device(&ircut_info); ++ IRCUT_DBG("ms_ircut_resume\n"); ++ MDrv_GPIO_Pad_Set(mGpioNum); ++ MDrv_GPIO_Pad_Odn(mGpioNum); ++ return 0; ++} ++#endif ++ ++ ++ ++static struct platform_driver ms_ircut_driver = { ++ .probe = ms_ircut_probe, ++ .remove = ms_ircut_remove, ++#ifdef CONFIG_PM ++ .suspend = ms_ircut_suspend, ++ .resume = ms_ircut_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "infinity-ircut", ++ .of_match_table = ms_ircut_of_match_table, ++ }, ++}; ++module_platform_driver(ms_ircut_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("ms ircut Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:ms-ircut"); +diff --git a/drivers/sstar/irqchip/Kconfig b/drivers/sstar/irqchip/Kconfig +new file mode 100755 +index 000000000000..e69de29bb2d1 +diff --git a/drivers/sstar/irqchip/Makefile b/drivers/sstar/irqchip/Makefile +new file mode 100755 +index 000000000000..448f768021d2 +--- /dev/null ++++ b/drivers/sstar/irqchip/Makefile +@@ -0,0 +1,3 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++obj-y += $(CONFIG_SSTAR_CHIP_NAME)/ +diff --git a/drivers/sstar/irqchip/infinity2/Makefile b/drivers/sstar/irqchip/infinity2/Makefile +new file mode 100755 +index 000000000000..9265e9bdcbc6 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2/Makefile +@@ -0,0 +1,10 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/irqchip ++ ++obj-y += irqchip.o ++#TBD_EDIE# ++#obj-y += irq-gpi.o ++obj-y += irq-pmsleep.o +diff --git a/drivers/sstar/irqchip/infinity2/irq-gpi.c b/drivers/sstar/irqchip/infinity2/irq-gpi.c +new file mode 100755 +index 000000000000..5147b47589fe +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2/irq-gpi.c +@@ -0,0 +1,294 @@ ++/* ++* irq-ss-gpi.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++static void ss_gpi_irq_ack(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ if(!d) ++ { ++ dump_stack(); ++ return; ++ } ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d\n", __FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_0A + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_mask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_unmask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++ ++static int ss_gpi_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 gpi_irq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ gpi_irq = d->hwirq; ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ default: ++ return -EINVAL; ++ ++ } ++ ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ss_gpi_intc_irqchip = { ++ .name = "MS_GPI_INTC", ++ .irq_ack = ss_gpi_irq_ack, ++ .irq_eoi = ss_gpi_irq_ack, ++ .irq_mask = ss_gpi_irq_mask, ++ .irq_unmask = ss_gpi_irq_unmask, ++ .irq_set_type = ss_gpi_irq_set_type, ++}; ++EXPORT_SYMBOL(ss_gpi_intc_irqchip); ++ ++ ++static void ss_handle_cascade_gpi(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i, j; ++ unsigned int virq=0xFFFFFFFF; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ for (j=0; j<=GPI_FIQ_NUM/16; j++) ++ { ++ final_status = INREG16(BASE_REG_GPI_INT_PA + REG_ID_30 + j*4); ++ for(i=0; i<16 && final_status!=0; i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ss_gpi_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ss_gpi_intc_irqchip, NULL, handle_edge_irq, NULL, NULL); ++ pr_err("[%s] hw:%d -> v:%d\n", __FUNCTION__, (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ss_gpi_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ss_gpi_intc_domain_ops = { ++ .translate = ss_gpi_intc_domain_translate, ++ .alloc = ss_gpi_intc_domain_alloc, ++ .free = ss_gpi_intc_domain_free, ++}; ++ ++ ++ ++static int __init ss_init_gpi_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ss_gpi_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ss_gpi_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ss_gpi_intc_domain_ops, NULL); ++ ++ if (!ss_gpi_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ss_handle_cascade_gpi, ss_gpi_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ss_gpi_intc, "sstar,gpi-intc", ss_init_gpi_intc); +diff --git a/drivers/sstar/irqchip/infinity2/irq-pmsleep.c b/drivers/sstar/irqchip/infinity2/irq-pmsleep.c +new file mode 100755 +index 000000000000..7b7e39c82cbe +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2/irq-pmsleep.c +@@ -0,0 +1,318 @@ ++/* ++* irq-pmsleep.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++#include ++#define CONFIG_PATCH_STATUS_FAILS 0 ++extern CHIP_VERSION msys_get_chipVersion(void); ++ ++#define PMGPIO_OEN BIT0 ++#define PMGPIO_OUTPUT BIT1 ++#define PMGPIO_INPUT BIT2 ++#define PMGPIO_FIQ_MASK BIT4 ++#define PMGPIO_FIQ_FROCE BIT5 ++#define PMGPIO_FIQ_CLEAR BIT6 ++#define PMGPIO_FIQ_POLARITY BIT7 ++#define PMGPIO_FIQ_FINAL_STATUS BIT8 ++#define PMGPIO_FIQ_RAW_STATUS BIT9 ++#define PMGPIO_FIQ_FINAL_STATUS_ECO BIT14 ++ ++ ++static void ms_pm_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ else if(pmsleep_fiq >= PMSLEEP_IRQ_START) ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ ++ else if(pmsleep_fiq >= PMSLEEP_IRQ_START) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ ++ else if(pmsleep_fiq >= PMSLEEP_IRQ_START) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ else ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ } ++ ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ if(type&IRQ_TYPE_LEVEL_LOW) ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ else ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_ack = ms_pm_irq_ack, ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_pm_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ unsigned int virq ; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_0E)& 0xFF; ++// int triggered = 0; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ spin_lock(&ss_irq_controller_lock); ++ { ++ for(i=0;ifwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, handle_fasteoi_irq, NULL, NULL); ++ pr_err("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ int irq=0; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ parent_domain = irq_find_host(interrupt_parent); ++ ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_IRQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ irq = irq_of_parse_and_map(np, 0); ++ ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ /* unmask pm domain IRQ ctrl */ ++ CLRREG16( (BASE_REG_IRQ_PM + REG_ID_14) , (1 << 02) );//pm_sleep ++ /* unmask pm domain FIQ ctrl */ ++ CLRREG16( (BASE_REG_IRQ_PM + REG_ID_04) , (1 << 12) );//timer2 ++ ++ /* U02 eco patch, mask FIQ interrupt*/ ++ if(msys_get_chipVersion()) ++ OUTREGMSK16((BASE_REG_MCU_ARM+REG_ID_52), 0xFF, 0xFF); ++ ++ irq_set_chained_handler_and_data(irq, ms_handle_cascade_pm_irq, ms_pm_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity2/irqchip.c b/drivers/sstar/irqchip/infinity2/irqchip.c +new file mode 100755 +index 000000000000..91b598c21e8f +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2/irqchip.c +@@ -0,0 +1,576 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++ ++ ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | |---------| *//* 352 */ ++/* | MS_FIQ (32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | |---------| *//* 320 */ ++/* | MS_IRQ (32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | |---------| *//* 288 */ ++/* | pmuirq (32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | | | *//* 256 */ ++/* | MS_FIQ (64) | | --ms_pmsleep */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | | | *//* 128 */ ++/* | MS_IRQ (64) | gic_spi | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | | | *//* 64 */ ++/* | ARM_INTERNAL(32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ |------- */ ++/* | | *//* 32 */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++ ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 gic_spi_irq, ms_fiq, ms_fiq1; ++ gic_spi_irq = d->hwirq; ++ ++ /* NOTE: only clear if it is FIQ */ ++// if( d->hwirq < GIC_HWIRQ_MS_START ) ++// { ++// return; ++// } ++// else ++ if( gic_spi_irq >= GIC_SPI_MS_FIQ_START && gic_spi_irq < GIC_SPI_MS_FIQ_END ) ++ { ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ ++ if (ms_fiq == 63)//PM_FIQ ++ SETREG16( (BASE_REG_IRQ_PM + REG_ID_0C ), (1 << 12) );//clear timer2 (pm_fiq[12]) ++ } ++ else if( gic_spi_irq >= GIC_SPI_MS_FIQ1_START && gic_spi_irq < GIC_SPI_MS_FIQ1_END ) ++ { ++ ms_fiq1 = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_4C + (ms_fiq1/16)*4 ) , (1 << (ms_fiq1%16)) ); ++ } ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 gic_spi_irq, ms_fiq, ms_fiq1; ++ gic_spi_irq = d->hwirq; ++ /* NOTE: only clear if it is FIQ */ ++// if( d->hwirq < GIC_HWIRQ_MS_START ) ++// { ++// return; ++// } ++// else ++if( gic_spi_irq >= GIC_SPI_MS_FIQ_START && gic_spi_irq < GIC_SPI_MS_FIQ_END ) ++ { ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ ++ if (ms_fiq == 63)//PM_FIQ ++ SETREG16( (BASE_REG_IRQ_PM + REG_ID_0C ), (1 << 12) );//clear timer2 (pm_fiq[12]) ++ } ++ else if( gic_spi_irq >= GIC_SPI_MS_FIQ1_START && gic_spi_irq < GIC_SPI_MS_FIQ1_END ) ++ { ++ ms_fiq1 = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_4C + (ms_fiq1/16)*4 ) , (1 << (ms_fiq1%16)) ); ++ } ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ s16 gic_spi_irq; ++ ++ gic_spi_irq = d->hwirq; ++// pr_err("[@@-ms_irq_mask] gic_spi_irq %d\n", gic_spi_irq); ++// if( d->hwirq < GIC_HWIRQ_MS_START ) ++// { ++// return; ++// } ++// else ++ if((gic_spi_irq >= GIC_SPI_MS_IRQ_START) && (gic_spi_irq < GIC_SPI_MS_IRQ_END)) ++ { ++ /*MS_IRQ0*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ_START; ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ_START) && (gic_spi_irq < GIC_SPI_MS_FIQ_END)) ++ { ++ /*MS_FIQ0*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ /*MS_FIQ 64!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_64_SEC_GUARD_INT) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (0)) ); ++ } ++ /*MS_FIQ 65!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_65_SD_CDZ_IN) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (1)) ); ++ } ++ /*MS_IRQ 1*/ ++ else if ((gic_spi_irq >= GIC_SPI_MS_IRQ1_START) && (gic_spi_irq < INT_FIQ_64_SEC_GUARD_INT)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if ((gic_spi_irq > INT_FIQ_65_SD_CDZ_IN) && (gic_spi_irq < GIC_SPI_MS_IRQ1_END)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START - 2; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ1_START) && (gic_spi_irq < GIC_SPI_MS_FIQ1_END)) ++ { ++ /*MS_FIQ1*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if((gic_spi_irq == INT_169_REG_DUMMY_ECO_1_1) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[1] */ ++ SETREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (1)) ); ++ } ++ else if((gic_spi_irq == INT_168_REG_DUMMY_ECO_1_0) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[0] */ ++ SETREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (0)) ); ++ } ++ else if(((INT_162_IRQ_IN_0 <= gic_spi_irq) && (gic_spi_irq <= INT_165_FIQ_IN_1)) ) ++ { ++ OUTREG32(GIC_PHYS + 0x1000 + + GIC_DIST_ENABLE_CLEAR + (d->hwirq / 32) * 4, (1<<(d->hwirq % 32))); ++ } ++ else if((gic_spi_irq == INT_182_PMU_IRQ_0) ||(gic_spi_irq == INT_191_PMU_IRQ_1)) ++ { ++ /* PMU */ ++ } ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ s16 gic_spi_irq; ++ ++ gic_spi_irq = d->hwirq; ++// if ((gic_spi_irq != INT_IRQ_00_INT_UART0) || (gic_spi_irq != INT_FIQ_00_INT_TIMER0)) ++ // if( d->hwirq < GIC_HWIRQ_MS_START ) ++// { ++// return; ++// } ++// else ++ if((gic_spi_irq >= GIC_SPI_MS_IRQ_START) && (gic_spi_irq < GIC_SPI_MS_IRQ_END)) ++ { ++ /*MS_IRQ0*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ_START) && (gic_spi_irq < GIC_SPI_MS_FIQ_END)) ++ { ++ /*MS_FIQ0*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ /*MS_FIQ 64!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_64_SEC_GUARD_INT) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (0)) ); ++ } ++ /*MS_FIQ 65!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_65_SD_CDZ_IN) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (1)) ); ++ } ++ /*MS_IRQ 1*/ ++ else if ((gic_spi_irq >= GIC_SPI_MS_IRQ1_START) && (gic_spi_irq < INT_FIQ_64_SEC_GUARD_INT)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if ((gic_spi_irq > INT_FIQ_65_SD_CDZ_IN) && (gic_spi_irq < GIC_SPI_MS_IRQ1_END)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START - 2; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ /*MS_FIQ 1*/ ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ1_START) && (gic_spi_irq < GIC_SPI_MS_FIQ1_END)) ++ { ++ /*MS_FIQ1*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if((gic_spi_irq == INT_169_REG_DUMMY_ECO_1_1) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[1] */ ++ CLRREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (1)) ); ++ } ++ else if((gic_spi_irq == INT_168_REG_DUMMY_ECO_1_0) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[0] */ ++ CLRREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (0)) ); ++ } ++ else if(((INT_162_IRQ_IN_0 <= gic_spi_irq) && (gic_spi_irq <= INT_165_FIQ_IN_1)) ) ++ { ++ OUTREG32(GIC_PHYS + 0x1000 + GIC_DIST_ENABLE_SET + (d->hwirq / 32) * 4, (1<<(d->hwirq % 32))); ++ } ++ else if((gic_spi_irq == INT_182_PMU_IRQ_0) ||(gic_spi_irq == INT_191_PMU_IRQ_1)) ++ { ++ /* PMU */ ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++#ifdef CONFIG_SMP ++static int ms_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++{ ++ //use a very simple implementation here... ++ return irq_chip_set_affinity_parent(data,dest,true); ++} ++#endif ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ s16 gic_spi_irq; ++ ++ gic_spi_irq = data->hwirq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("could not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ if( data->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return 0; ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_IRQ_START) && (gic_spi_irq < GIC_SPI_MS_IRQ_END)) ++ { ++ /*MS_IRQ0*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ_START; ++ ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ_START) && (gic_spi_irq < GIC_SPI_MS_FIQ_END)) ++ { ++ /*MS_FIQ0*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ /*MS_FIQ 64!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_64_SEC_GUARD_INT) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (0)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (0)) ); ++ ++ } ++ ++ /*MS_FIQ 65!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_65_SD_CDZ_IN) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (1)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (1)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_IRQ1_START) && (gic_spi_irq < INT_FIQ_64_SEC_GUARD_INT)) ++ { ++ /*MS_IRQ1*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if ((gic_spi_irq > INT_FIQ_65_SD_CDZ_IN) && (gic_spi_irq < GIC_SPI_MS_IRQ1_END)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START - 2; ++ ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) );; ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ1_START) && (gic_spi_irq < GIC_SPI_MS_FIQ1_END)) ++ { ++ /*MS_FIQ1*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ irq_chip_set_type_parent(data, flow_type); ++ return 0; ++ ++} ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++#ifdef CONFIG_SMP ++ .irq_set_affinity=ms_irq_set_affinity, ++#endif ++ ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++ ++static int ms_irqchip_suspend(void) ++{ ++ pr_debug("\nms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ pr_debug("\nms_irqchip_resume\n\n"); ++ printk("%s TBD\r\n", __FUNCTION__); ++ //Patch for disable bypass IRQ/FIQ ++ { ++// u32 bypass = 0; ++// bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++// bypass |= GICC_DIS_BYPASS_MASK; ++// OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++extern CHIP_VERSION msys_get_chipVersion(void); ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x0100 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x0100 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+ ++ GIC_SPI_MS_FIQ1_NR+GIC_SPI_MS_IRQ1_NR+GIC_SPI_MS_EXT_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ /* U02 eco patch, mask FIQ interrupt*/ ++ if(msys_get_chipVersion()) ++ OUTREGMSK16((BASE_REG_MCU_ARM+REG_ID_52), 0xFF, 0xFF); ++ ++ register_syscore_ops(&ms_irq_syscore_ops); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); +diff --git a/drivers/sstar/irqchip/infinity2/irqchip_i2.c b/drivers/sstar/irqchip/infinity2/irqchip_i2.c +new file mode 100755 +index 000000000000..503938d227f8 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2/irqchip_i2.c +@@ -0,0 +1,623 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "infinity2/irqs.h" ++#include "infinity2/registers.h" ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "infinity2/gpio.h" ++#include ++static DEFINE_SPINLOCK(infinity_irq_controller_lock); ++ ++ ++ ++ ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | |---------| *//* 352 */ ++/* | MS_FIQ (32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | |---------| *//* 320 */ ++/* | MS_IRQ (32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | |---------| *//* 288 */ ++/* | pmuirq (32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | | | *//* 256 */ ++/* | MS_FIQ (64) | | --ms_pmsleep */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | | | *//* 128 */ ++/* | MS_IRQ (64) | gic_spi | */ ++/* |_ _ _ _ _ _ _ _ _ _| | */ ++/* | | | *//* 64 */ ++/* | ARM_INTERNAL(32) | | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ |------- */ ++/* | | *//* 32 */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++ ++ ++ ++#if 0 ++static void ms_pm_sleep_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT6); ++ else if(pmsleep_fiq >= PMSLEEP_IRQ_START) ++ { ++ ++ } ++} ++ ++static void ms_pm_sleep_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ ++ else if(pmsleep_fiq >= PMSLEEP_IRQ_START) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ ++} ++ ++static void ms_pm_sleep_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ ++ else if(pmsleep_fiq >= PMSLEEP_IRQ_START) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ ++} ++ ++static int ms_pm_sleep_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PM_GPIO_INT_END) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ else ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ } ++ ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ if(type&IRQ_TYPE_LEVEL_LOW) ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ else ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ return 0; ++} ++#endif ++ ++ ++ ++static void ms_eoi_irq(struct irq_data *d) ++{ ++ s16 gic_spi_irq, ms_fiq, ms_fiq1; ++ ++ gic_spi_irq = d->hwirq - GIC_SGI_NR - GIC_PPI_NR; ++ ++ /* NOTE: only clear if it is FIQ */ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( gic_spi_irq >= GIC_SPI_MS_FIQ_START && gic_spi_irq < GIC_SPI_MS_FIQ_END ) ++ { ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ ++ if (ms_fiq == 63)//PM_FIQ ++ SETREG16( (BASE_REG_IRQ_PM + REG_ID_0C ), (1 << 12) );//clear timer2 (pm_fiq[12]) ++ } ++ else if( gic_spi_irq >= GIC_SPI_MS_FIQ1_START && gic_spi_irq < GIC_SPI_MS_FIQ1_END ) ++ { ++ ms_fiq1 = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_4C + (ms_fiq1/16)*4 ) , (1 << (ms_fiq1%16)) ); ++ } ++} ++ ++static void ms_mask_irq(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ s16 gic_spi_irq; ++ ++ gic_spi_irq = d->hwirq - GIC_SGI_NR - GIC_PPI_NR; ++// pr_err("[@@-ms_irq_mask] gic_spi_irq %d\n", gic_spi_irq); ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if((gic_spi_irq >= GIC_SPI_MS_IRQ_START) && (gic_spi_irq < GIC_SPI_MS_IRQ_END)) ++ { ++ /*MS_IRQ0*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ_START; ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ_START) && (gic_spi_irq < GIC_SPI_MS_FIQ_END)) ++ { ++ /*MS_FIQ0*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ /*MS_FIQ 64!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_64_SEC_GUARD_INT) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (0)) ); ++ } ++ /*MS_FIQ 65!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_65_SD_CDZ_IN) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (1)) ); ++ } ++ /*MS_IRQ 1*/ ++ else if ((gic_spi_irq >= GIC_SPI_MS_IRQ1_START) && (gic_spi_irq < INT_FIQ_64_SEC_GUARD_INT)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if ((gic_spi_irq > INT_FIQ_65_SD_CDZ_IN) && (gic_spi_irq < GIC_SPI_MS_IRQ1_END)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START - 2; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ1_START) && (gic_spi_irq < GIC_SPI_MS_FIQ1_END)) ++ { ++ /*MS_FIQ1*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if((gic_spi_irq == INT_169_REG_DUMMY_ECO_1_1) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[1] */ ++ SETREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (1)) ); ++ } ++ else if((gic_spi_irq == INT_168_REG_DUMMY_ECO_1_0) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[0] */ ++ SETREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (0)) ); ++ } ++ else if(((INT_162_IRQ_IN_0 <= gic_spi_irq) && (gic_spi_irq <= INT_165_FIQ_IN_1)) ) ++ { ++ OUTREG32(GIC_PHYS + 0x1000 + + GIC_DIST_ENABLE_CLEAR + (d->hwirq / 32) * 4, (1<<(d->hwirq % 32))); ++ } ++ else if((gic_spi_irq == INT_182_PMU_IRQ_0) ||(gic_spi_irq == INT_191_PMU_IRQ_1)) ++ { ++ /* PMU */ ++ } ++ else ++ { ++ pr_err("[ms_irq_mask] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++} ++ ++static void ms_unmask_irq(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ s16 gic_spi_irq; ++ ++ gic_spi_irq = d->hwirq - GIC_SGI_NR - GIC_PPI_NR; ++// if ((gic_spi_irq != INT_IRQ_00_INT_UART0) || (gic_spi_irq != INT_FIQ_00_INT_TIMER0)) ++// printk("ms_unmask_irq: %d/n", gic_spi_irq); ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if((gic_spi_irq >= GIC_SPI_MS_IRQ_START) && (gic_spi_irq < GIC_SPI_MS_IRQ_END)) ++ { ++ /*MS_IRQ0*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ_START) && (gic_spi_irq < GIC_SPI_MS_FIQ_END)) ++ { ++ /*MS_FIQ0*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ /*MS_FIQ 64!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_64_SEC_GUARD_INT) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (0)) ); ++ } ++ /*MS_FIQ 65!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_65_SD_CDZ_IN) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + 0 ) , (1 << (1)) ); ++ } ++ /*MS_IRQ 1*/ ++ else if ((gic_spi_irq >= GIC_SPI_MS_IRQ1_START) && (gic_spi_irq < INT_FIQ_64_SEC_GUARD_INT)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if ((gic_spi_irq > INT_FIQ_65_SD_CDZ_IN) && (gic_spi_irq < GIC_SPI_MS_IRQ1_END)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START - 2; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ /*MS_FIQ 1*/ ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ1_START) && (gic_spi_irq < GIC_SPI_MS_FIQ1_END)) ++ { ++ /*MS_FIQ1*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if((gic_spi_irq == INT_169_REG_DUMMY_ECO_1_1) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[1] */ ++ CLRREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (1)) ); ++ } ++ else if((gic_spi_irq == INT_168_REG_DUMMY_ECO_1_0) ) ++ { ++ /* sw interrupt, riu bank 0x101d, offset 0x2d[0] */ ++ CLRREG16( (BASE_REG_MCU_ARM + REG_ID_2D + 0) , (1 << (0)) ); ++ } ++ else if(((INT_162_IRQ_IN_0 <= gic_spi_irq) && (gic_spi_irq <= INT_165_FIQ_IN_1)) ) ++ { ++ OUTREG32(GIC_PHYS + 0x1000 + GIC_DIST_ENABLE_SET + (d->hwirq / 32) * 4, (1<<(d->hwirq % 32))); ++ } ++ else if((gic_spi_irq == INT_182_PMU_IRQ_0) ||(gic_spi_irq == INT_191_PMU_IRQ_1)) ++ { ++ /* PMU */ ++ } ++ else ++ { ++ pr_err("[ms_unmask_irq] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++ ++} ++ ++void ms_mask_irq_all(void) ++{ ++ /* mask FIQ0 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_44) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_45) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_46) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_47) , 0xFFFF ); ++ ++ /* mask IRQ0 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_54) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_55) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_56) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_57) , 0xFFFF ); ++ /* mask FIQ1 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_45) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_46) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_47) , 0xFFFF ); ++ ++ /* mask IRQ1 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_55) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_56) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_57) , 0xFFFF ); ++} ++ ++void ms_unmask_irq_all(void) ++{ ++ /* unmask FIQ 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_44) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_45) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_46) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_47) , 0 ); ++ /* unmask IRQ 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_54) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_55) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_56) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_57) , 0 ); ++ ++ /* unmask IRQ 1 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_44) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_45) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_46) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_47) , 0 ); ++ /* unmask IRQ 1 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_54) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_55) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_56) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_57) , 0 ); ++} ++ ++static int ms_set_type_irq(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ s16 gic_spi_irq; ++ ++ gic_spi_irq = data->hwirq - GIC_SGI_NR - GIC_PPI_NR; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("could not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ if( data->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return 0; ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_IRQ_START) && (gic_spi_irq < GIC_SPI_MS_IRQ_END)) ++ { ++ /*MS_IRQ0*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ_START; ++ ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ_START) && (gic_spi_irq < GIC_SPI_MS_FIQ_END)) ++ { ++ /*MS_FIQ0*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA0 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ /*MS_FIQ 64!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_64_SEC_GUARD_INT) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (0)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (0)) ); ++ ++ } ++ ++ /*MS_FIQ 65!!!!*/ ++ else if (gic_spi_irq == INT_FIQ_65_SD_CDZ_IN) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (1)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + 0 ) , (1 << (1)) ); ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_IRQ1_START) && (gic_spi_irq < INT_FIQ_64_SEC_GUARD_INT)) ++ { ++ /*MS_IRQ1*/ ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START; ++ ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ ++ else if ((gic_spi_irq > INT_FIQ_65_SD_CDZ_IN) && (gic_spi_irq < GIC_SPI_MS_IRQ1_END)) ++ { ++ ms_irq = gic_spi_irq - GIC_SPI_MS_IRQ1_START - 2; ++ ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) );; ++ } ++ ++ else if((gic_spi_irq >= GIC_SPI_MS_FIQ1_START) && (gic_spi_irq < GIC_SPI_MS_FIQ1_END)) ++ { ++ /*MS_FIQ1*/ ++ ms_fiq = gic_spi_irq - GIC_SPI_MS_FIQ1_START; ++ ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA1 + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ ++ else ++ { ++ pr_err("[ms_irq_set_polarity] Unknown hwirq %lu from GIC\n", data->hwirq); ++ } ++ ++ return 0; ++} ++ ++#if 1 ++static void ms_handle_cascade_pm_irq(unsigned int irq, struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ struct irq_chip *chip = irq_get_chip(irq); ++// unsigned int fiq_final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ unsigned int irq_final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_0E)& 0xFF; ++// unsigned int irq_gpio_status = INREG16(BASE_REG_PMGPIO_PA)& 0xFF; ++ ++ chained_irq_enter(chip, desc); ++ ++ spin_lock(&infinity_irq_controller_lock); ++ { ++ for(i=0;i ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++static void ss_gpi_irq_ack(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ if(!d) ++ { ++ dump_stack(); ++ return; ++ } ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d\n", __FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_0A + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_mask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_unmask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++ ++static int ss_gpi_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 gpi_irq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ gpi_irq = d->hwirq; ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ // TODO:I2m U02 ++ if(Chip_Get_Revision() == 0x2) ++ { ++ if( (gpi_irq == INT_GPI_FIQ_SATA_GPIO || gpi_irq == INT_GPI_FIQ_HDMITX_HPD) && ++ type == IRQ_TYPE_EDGE_BOTH ) ++ { ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ // Enable rise/fall int ++ SETREG16(BASE_REG_GPI_INT_PA + REG_ID_22, 0x3); ++ } ++ else ++ { ++ pr_err("[%s] both-edge trigger doesn't supported @ irq(%u)\n", __func__, gpi_irq); ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ pr_err("[%s] both-edge trigger doesn't supported @ irq(%u) on chip(rev.%u)\n", __func__, gpi_irq, Chip_Get_Revision()); ++ return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ss_gpi_intc_irqchip = { ++ .name = "MS_GPI_INTC", ++ .irq_ack = ss_gpi_irq_ack, ++ .irq_eoi = ss_gpi_irq_ack, ++ .irq_mask = ss_gpi_irq_mask, ++ .irq_unmask = ss_gpi_irq_unmask, ++ .irq_set_type = ss_gpi_irq_set_type, ++}; ++EXPORT_SYMBOL(ss_gpi_intc_irqchip); ++ ++ ++static void ss_handle_cascade_gpi(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i, j; ++ unsigned int virq=0xFFFFFFFF; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ for (j=0; j<=GPI_FIQ_NUM/16; j++) ++ { ++ final_status = INREG16(BASE_REG_GPI_INT_PA + REG_ID_30 + j*4); ++ for(i=0; i<16 && final_status!=0; i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ss_gpi_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ss_gpi_intc_irqchip, NULL, handle_edge_irq, NULL, NULL); ++ pr_err("[%s] hw:%d -> v:%d\n", __FUNCTION__, (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ss_gpi_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ss_gpi_intc_domain_ops = { ++ .translate = ss_gpi_intc_domain_translate, ++ .alloc = ss_gpi_intc_domain_alloc, ++ .free = ss_gpi_intc_domain_free, ++}; ++ ++ ++ ++static int __init ss_init_gpi_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ss_gpi_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ss_gpi_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ss_gpi_intc_domain_ops, NULL); ++ ++ if (!ss_gpi_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ss_handle_cascade_gpi, ss_gpi_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ss_gpi_intc, "sstar,gpi-intc", ss_init_gpi_intc); +diff --git a/drivers/sstar/irqchip/infinity2m/irq-pmsleep.c b/drivers/sstar/irqchip/infinity2m/irq-pmsleep.c +new file mode 100755 +index 000000000000..388e17922920 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2m/irq-pmsleep.c +@@ -0,0 +1,411 @@ ++/* ++* irq-pmsleep.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++#define CONFIG_PATCH_STATUS_FAILS 0 ++#define CONFIG_I2M_PM_INTC_ECO 1 ++ ++#define PMGPIO_OEN BIT0 ++#define PMGPIO_OUTPUT BIT1 ++#define PMGPIO_INPUT BIT2 ++#define PMGPIO_FIQ_MASK BIT4 ++#define PMGPIO_FIQ_FROCE BIT5 ++#define PMGPIO_FIQ_CLEAR BIT6 ++#define PMGPIO_FIQ_POLARITY BIT7 ++#define PMGPIO_FIQ_FINAL_STATUS BIT8 ++#define PMGPIO_FIQ_RAW_STATUS BIT9 ++#if CONFIG_I2M_PM_INTC_ECO ++#define PMGPIO_FIQ_FINAL_STATUS_ECO BIT14 ++#endif ++ ++static void ms_pm_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if( pmsleep_fiq >= PMSLEEP_FIQ_START && pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if( pmsleep_fiq >= PMSLEEP_FIQ_START && pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if( pmsleep_fiq >= PMSLEEP_FIQ_START && pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_MASK); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if( pmsleep_fiq >= PMSLEEP_FIQ_START && pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_MASK); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if( pmsleep_fiq >= PMSLEEP_FIQ_START && pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_ack = ms_pm_irq_ack, ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_pm_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ unsigned int virq = 0xDEADBEEF; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status = 0xDEADBEEF; ++ int triggered = 0; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ spin_lock(&ss_irq_controller_lock); ++#if CONFIG_PATCH_STATUS_FAILS ++ for(i=0;i<=75;i++) ++ { ++ final_status =INREG16(BASE_REG_PMGPIO_PA+i*4); ++ if(!(final_status&PMGPIO_FIQ_MASK)) ++ { ++ if( (final_status&PMGPIO_FIQ_POLARITY)? !(final_status&PMGPIO_INPUT):(final_status&PMGPIO_INPUT)) ++ { ++ cascade_irq = i; ++ pr_debug("[%s] Get hwirq:%d, Reg:0x%04x\n", __FUNCTION__, cascade_irq, final_status); ++ break; ++ } ++ } ++ } ++#elif CONFIG_I2M_PM_INTC_ECO ++ // FIXME: traverse through the following active PMSLEEP interrupts ++ for(i=INT_PMSLEEP_DUMMY_0;i<=INT_PMSLEEP_LED1;i++) ++ { ++ if( (i>=INT_PMSLEEP_IRIN && i<=INT_PMSLEEP_SPI_DO) || ++ (i>=INT_PMSLEEP_SPI_WPZ && i<=INT_PMSLEEP_SPI_HLD) ) ++ { ++ final_status = INREG16(BASE_REG_PMGPIO_PA+i*4); ++ triggered = ( final_status & PMGPIO_FIQ_FINAL_STATUS_ECO ); ++ } ++ else if(i == INT_PMSLEEP_SD_CDZ) /* PAD_PM_SD_CDZ: Addr 7f Bit0 */ ++ { ++ final_status = INREG16(BASE_REG_PMGPIO_PA + 0x7f*4); ++ triggered = final_status & BIT0; ++ } ++ else if (i == INT_PMSLEEP_LED0) /* PAD_PM_LED0: Addr 7f Bit1 */ ++ { ++ final_status = INREG16(BASE_REG_PMGPIO_PA + 0x7f*4); ++ triggered = final_status & BIT1; ++ } ++ else if (i == INT_PMSLEEP_LED1) /* PAD_PM_LED1: Addr 7f Bit2 */ ++ { ++ final_status = INREG16(BASE_REG_PMGPIO_PA + 0x7f*4); ++ triggered = final_status & BIT2; ++ } ++ ++ if( triggered ) ++ { ++ cascade_irq = i; ++ pr_debug("[%s] Get hwirq:%d, Reg:0x%04x\n", __FUNCTION__, cascade_irq, final_status); ++ break; ++ } ++ } ++#else ++ final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ for(i=0;i<32;i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, handle_fasteoi_irq, NULL, NULL); ++ pr_err("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ms_handle_cascade_pm_irq, ms_pm_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity2m/irqchip.c b/drivers/sstar/irqchip/infinity2m/irqchip.c +new file mode 100755 +index 000000000000..e05856260678 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity2m/irqchip.c +@@ -0,0 +1,349 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ pr_debug("[%s] hwirq %lu\n", __func__, d->hwirq); ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++#ifdef CONFIG_SMP ++static int ms_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++{ ++ //use a very simple implementation here... ++ return irq_chip_set_affinity_parent(data,dest,true); ++} ++#endif ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ ++ ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ irq_chip_set_type_parent(data, flow_type); ++ return 0; ++ ++} ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++#ifdef CONFIG_SMP ++ .irq_set_affinity=ms_irq_set_affinity, ++#endif ++ ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++ ++static int ms_irqchip_suspend(void) ++{ ++ pr_debug("\nms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ pr_debug("\nms_irqchip_resume\n\n"); ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ register_syscore_ops(&ms_irq_syscore_ops); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); +diff --git a/drivers/sstar/irqchip/infinity3/irqchip.c b/drivers/sstar/irqchip/infinity3/irqchip.c +new file mode 100755 +index 000000000000..96801967b1c5 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity3/irqchip.c +@@ -0,0 +1,625 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT0); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT1); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT6); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ irq_chip_unmask_parent(d); ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ else ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ if(type&IRQ_TYPE_LEVEL_LOW) ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ else ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %lu\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ ++ ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++ ++} ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ unsigned int final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ ++ chained_irq_enter(chip, desc); ++ ++ spin_lock(&ss_irq_controller_lock); ++ { ++ for(i=0;i<32;i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, ++ ms_handle_cascade_pm_irq, NULL, NULL); ++ pr_debug("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ //extend to GIC format, pass to parents ++ parent_fwspec.param_count=3; ++ parent_fwspec.param[0]=GIC_SPI; ++ parent_fwspec.param[1]=INT_IRQ_PM_SLEEP; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++ ++static int ms_irqchip_suspend(void) ++{ ++ pr_debug("\nms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ pr_debug("\nms_irqchip_resume\n\n"); ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ register_syscore_ops(&ms_irq_syscore_ops); ++ ++ return 0; ++} ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++// int virq_base; ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity5/Makefile b/drivers/sstar/irqchip/infinity5/Makefile +new file mode 100755 +index 000000000000..213adac5debf +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity5/Makefile +@@ -0,0 +1,7 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/irqchip ++ ++obj-y += irqchip.o +diff --git a/drivers/sstar/irqchip/infinity5/irqchip.c b/drivers/sstar/irqchip/infinity5/irqchip.c +new file mode 100755 +index 000000000000..c7e17a117d09 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity5/irqchip.c +@@ -0,0 +1,656 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++static void ms_pm_irq_ack(struct irq_data *d) ++{ ++} ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT0); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT1); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT6); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ pr_debug("%s %d \n", __FUNCTION__, __LINE__); ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ else ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ if(type&IRQ_TYPE_LEVEL_LOW) ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ else ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_ack = ms_pm_irq_ack, ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_pm_intc_irqchip); ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ pr_debug("[%s] hwirq %lu\n", __func__, d->hwirq); ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ ++ ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ irq_chip_set_type_parent(data, flow_type); ++ return 0; ++ ++} ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ unsigned int virq ; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ return ; ++ } ++ ++ spin_lock(&ss_irq_controller_lock); ++ final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ for(i=0;i<32;i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, handle_fasteoi_irq, NULL, NULL); ++ pr_err("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++ ++static int ms_irqchip_suspend(void) ++{ ++ pr_debug("\nms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ pr_debug("\nms_irqchip_resume\n\n"); ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ register_syscore_ops(&ms_irq_syscore_ops); ++ ++ return 0; ++} ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ms_handle_cascade_pm_irq, ms_pm_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity6/Makefile b/drivers/sstar/irqchip/infinity6/Makefile +new file mode 100755 +index 000000000000..7d98d02768c2 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6/Makefile +@@ -0,0 +1,9 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/irqchip ++ ++obj-y += irqchip.o ++obj-y += irq-gpi.o ++obj-y += irq-pmsleep.o +diff --git a/drivers/sstar/irqchip/infinity6/irq-gpi.c b/drivers/sstar/irqchip/infinity6/irq-gpi.c +new file mode 100755 +index 000000000000..424bc2ff41a8 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6/irq-gpi.c +@@ -0,0 +1,296 @@ ++/* ++* irq-ss-gpi.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++static void ss_gpi_irq_ack(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ if(!d) ++ { ++ dump_stack(); ++ return; ++ } ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d\n", __FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_0A + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_mask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_unmask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++ ++static int ss_gpi_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 gpi_irq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ gpi_irq = d->hwirq; ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ default: ++ return -EINVAL; ++ ++ } ++ // prevent the very 1st unexpected trigger right after irq_request() ++ // http://mantis.sigmastar.com.tw/view.php?id=1688845 ++ ss_gpi_irq_ack(d); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ss_gpi_intc_irqchip = { ++ .name = "MS_GPI_INTC", ++ .irq_ack = ss_gpi_irq_ack, ++ .irq_eoi = ss_gpi_irq_ack, ++ .irq_mask = ss_gpi_irq_mask, ++ .irq_unmask = ss_gpi_irq_unmask, ++ .irq_set_type = ss_gpi_irq_set_type, ++}; ++EXPORT_SYMBOL(ss_gpi_intc_irqchip); ++ ++ ++static void ss_handle_cascade_gpi(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i, j; ++ unsigned int virq=0xFFFFFFFF; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ for (j=0; j<=GPI_FIQ_NUM/16; j++) ++ { ++ final_status = INREG16(BASE_REG_GPI_INT_PA + REG_ID_30 + j*4); ++ for(i=0; i<16 && final_status!=0; i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ss_gpi_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ss_gpi_intc_irqchip, NULL, handle_edge_irq, NULL, NULL); ++ pr_err("[%s] hw:%d -> v:%d\n", __FUNCTION__, (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ss_gpi_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ss_gpi_intc_domain_ops = { ++ .translate = ss_gpi_intc_domain_translate, ++ .alloc = ss_gpi_intc_domain_alloc, ++ .free = ss_gpi_intc_domain_free, ++}; ++ ++ ++ ++static int __init ss_init_gpi_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ss_gpi_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ss_gpi_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ss_gpi_intc_domain_ops, NULL); ++ ++ if (!ss_gpi_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ss_handle_cascade_gpi, ss_gpi_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ss_gpi_intc, "sstar,gpi-intc", ss_init_gpi_intc); +diff --git a/drivers/sstar/irqchip/infinity6/irq-pmsleep.c b/drivers/sstar/irqchip/infinity6/irq-pmsleep.c +new file mode 100755 +index 000000000000..02b301040a7e +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6/irq-pmsleep.c +@@ -0,0 +1,372 @@ ++/* ++* irq-pmsleep.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++#define CONFIG_PATCH_STATUS_FAILS 1 ++ ++ ++#define PMGPIO_OEN BIT0 ++#define PMGPIO_OUTPUT BIT1 ++#define PMGPIO_INPUT BIT2 ++#define PMGPIO_FIQ_MASK BIT4 ++#define PMGPIO_FIQ_FROCE BIT5 ++#define PMGPIO_FIQ_CLEAR BIT6 ++#define PMGPIO_FIQ_POLARITY BIT7 ++#define PMGPIO_FIQ_FINAL_STATUS BIT8 ++#define PMGPIO_FIQ_RAW_STATUS BIT9 ++ ++static void ms_pm_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_MASK); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_MASK); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_ack = ms_pm_irq_ack, ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_pm_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ unsigned int virq ; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ spin_lock(&ss_irq_controller_lock); ++#ifdef CONFIG_PATCH_STATUS_FAILS ++ for(i=0;i<=75;i++) ++ { ++ final_status =INREG16(BASE_REG_PMGPIO_PA+i*4); ++ if(!(final_status&PMGPIO_FIQ_MASK)) ++ { ++ if( (final_status&PMGPIO_FIQ_POLARITY)? !(final_status&PMGPIO_INPUT):(final_status&PMGPIO_INPUT)) ++ { ++ cascade_irq = i; ++ pr_debug("[%s] Get hwirq:%d, Reg:0x%04x\n", __FUNCTION__, cascade_irq, final_status); ++ break; ++ } ++ } ++ } ++#else ++ final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ for(i=0;i<32;i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, handle_fasteoi_irq, NULL, NULL); ++ pr_err("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ms_handle_cascade_pm_irq, ms_pm_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity6/irqchip.c b/drivers/sstar/irqchip/infinity6/irqchip.c +new file mode 100755 +index 000000000000..9ee0e4d9d90c +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6/irqchip.c +@@ -0,0 +1,341 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ pr_debug("[%s] hwirq %lu\n", __func__, d->hwirq); ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ ++ ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ irq_chip_set_type_parent(data, flow_type); ++ return 0; ++ ++} ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++ ++static int ms_irqchip_suspend(void) ++{ ++ pr_debug("\nms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ pr_debug("\nms_irqchip_resume\n\n"); ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ register_syscore_ops(&ms_irq_syscore_ops); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); +diff --git a/drivers/sstar/irqchip/infinity6b0/Makefile b/drivers/sstar/irqchip/infinity6b0/Makefile +new file mode 100755 +index 000000000000..7d98d02768c2 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6b0/Makefile +@@ -0,0 +1,9 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/irqchip ++ ++obj-y += irqchip.o ++obj-y += irq-gpi.o ++obj-y += irq-pmsleep.o +diff --git a/drivers/sstar/irqchip/infinity6b0/irq-gpi.c b/drivers/sstar/irqchip/infinity6b0/irq-gpi.c +new file mode 100755 +index 000000000000..424bc2ff41a8 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6b0/irq-gpi.c +@@ -0,0 +1,296 @@ ++/* ++* irq-ss-gpi.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++static void ss_gpi_irq_ack(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ if(!d) ++ { ++ dump_stack(); ++ return; ++ } ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d\n", __FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_0A + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_mask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_unmask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++ ++static int ss_gpi_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 gpi_irq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ gpi_irq = d->hwirq; ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ default: ++ return -EINVAL; ++ ++ } ++ // prevent the very 1st unexpected trigger right after irq_request() ++ // http://mantis.sigmastar.com.tw/view.php?id=1688845 ++ ss_gpi_irq_ack(d); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ss_gpi_intc_irqchip = { ++ .name = "MS_GPI_INTC", ++ .irq_ack = ss_gpi_irq_ack, ++ .irq_eoi = ss_gpi_irq_ack, ++ .irq_mask = ss_gpi_irq_mask, ++ .irq_unmask = ss_gpi_irq_unmask, ++ .irq_set_type = ss_gpi_irq_set_type, ++}; ++EXPORT_SYMBOL(ss_gpi_intc_irqchip); ++ ++ ++static void ss_handle_cascade_gpi(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i, j; ++ unsigned int virq=0xFFFFFFFF; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ for (j=0; j<=GPI_FIQ_NUM/16; j++) ++ { ++ final_status = INREG16(BASE_REG_GPI_INT_PA + REG_ID_30 + j*4); ++ for(i=0; i<16 && final_status!=0; i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ss_gpi_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ss_gpi_intc_irqchip, NULL, handle_edge_irq, NULL, NULL); ++ pr_err("[%s] hw:%d -> v:%d\n", __FUNCTION__, (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ss_gpi_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ss_gpi_intc_domain_ops = { ++ .translate = ss_gpi_intc_domain_translate, ++ .alloc = ss_gpi_intc_domain_alloc, ++ .free = ss_gpi_intc_domain_free, ++}; ++ ++ ++ ++static int __init ss_init_gpi_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ss_gpi_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ss_gpi_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ss_gpi_intc_domain_ops, NULL); ++ ++ if (!ss_gpi_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ss_handle_cascade_gpi, ss_gpi_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ss_gpi_intc, "sstar,gpi-intc", ss_init_gpi_intc); +diff --git a/drivers/sstar/irqchip/infinity6b0/irq-pmsleep.c b/drivers/sstar/irqchip/infinity6b0/irq-pmsleep.c +new file mode 100755 +index 000000000000..7aaae27969d5 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6b0/irq-pmsleep.c +@@ -0,0 +1,348 @@ ++/* ++* irq-pmsleep.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++ ++#define PMGPIO_OEN BIT0 ++#define PMGPIO_OUTPUT BIT1 ++#define PMGPIO_INPUT BIT2 ++#define PMGPIO_FIQ_MASK BIT4 ++#define PMGPIO_FIQ_FROCE BIT5 ++#define PMGPIO_FIQ_CLEAR BIT6 ++#define PMGPIO_FIQ_POLARITY BIT7 ++#define PMGPIO_FIQ_FINAL_STATUS BIT8 ++#define PMGPIO_FIQ_RAW_STATUS BIT9 ++ ++static void ms_pm_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_MASK); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_MASK); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ // prevent the very 1st unexpected trigger right after irq_request() ++ // http://mantis.sigmastar.com.tw/view.php?id=1688845 ++ ms_pm_irq_ack(d); ++ ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_ack = ms_pm_irq_ack, ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_pm_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ unsigned int virq ; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ spin_lock(&ss_irq_controller_lock); ++ for(i=0;i<=75;i++) ++ { ++ final_status =INREG16(BASE_REG_PMGPIO_PA+i*4); ++ if(final_status&PMGPIO_FIQ_FINAL_STATUS) ++ { ++ cascade_irq = i; ++ pr_debug("[%s] Get hwirq:%d, Reg:0x%04x\n", __FUNCTION__, cascade_irq, final_status); ++ break; ++ } ++ } ++ spin_unlock(&ss_irq_controller_lock); ++ ++ if(0xFFFFFFFF==cascade_irq) ++ { ++ pr_err("[%s:%d] error final_status:%d 0x%04X\n", __FUNCTION__, __LINE__, cascade_irq, final_status); ++ panic("%s(%d) invalid cascade_irq: %d\n", __FUNCTION__, __LINE__, cascade_irq); ++ chained_irq_exit(chip, desc); ++ goto exit; ++ } ++ ++ virq = irq_find_mapping(domain, cascade_irq); ++ if(!virq) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ pr_debug("%s %d final_status:%d 0x%04X virq:%d\n", __FUNCTION__, __LINE__, cascade_irq, final_status, virq); ++ chained_irq_enter(chip, desc); ++ generic_handle_irq(virq); ++ ++exit: ++ chained_irq_exit(chip, desc); ++} ++ ++static int ms_pm_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, handle_fasteoi_irq, NULL, NULL); ++ pr_err("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ms_handle_cascade_pm_irq, ms_pm_irq_domain); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity6b0/irqchip.c b/drivers/sstar/irqchip/infinity6b0/irqchip.c +new file mode 100755 +index 000000000000..9ee0e4d9d90c +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6b0/irqchip.c +@@ -0,0 +1,341 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ pr_debug("[%s] hwirq %lu\n", __func__, d->hwirq); ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ ++ ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ irq_chip_set_type_parent(data, flow_type); ++ return 0; ++ ++} ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++ ++static int ms_irqchip_suspend(void) ++{ ++ pr_debug("\nms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ pr_debug("\nms_irqchip_resume\n\n"); ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ register_syscore_ops(&ms_irq_syscore_ops); ++ ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); +diff --git a/drivers/sstar/irqchip/infinity6e/Makefile b/drivers/sstar/irqchip/infinity6e/Makefile +new file mode 100644 +index 000000000000..7d98d02768c2 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6e/Makefile +@@ -0,0 +1,9 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/irqchip ++ ++obj-y += irqchip.o ++obj-y += irq-gpi.o ++obj-y += irq-pmsleep.o +diff --git a/drivers/sstar/irqchip/infinity6e/irq-gpi.c b/drivers/sstar/irqchip/infinity6e/irq-gpi.c +new file mode 100755 +index 000000000000..7d6ebde03dc6 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6e/irq-gpi.c +@@ -0,0 +1,342 @@ ++/* ++* irq-ss-gpi.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_PM_SLEEP ++/** ++ * struct ss_gpi_irq_priv - private gpi interrupt data ++ * @polarity: fiq polarity ++ */ ++struct ss_gpi_irq_priv { ++ U16 polarity[(GPI_FIQ_NUM+15)>>4]; ++}; ++ ++static struct ss_gpi_irq_priv gpi_irq_priv; ++#endif ++ ++static void ss_gpi_irq_ack(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ if(!d) ++ { ++ dump_stack(); ++ return; ++ } ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d\n", __FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_10 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_mask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ss_gpi_irq_unmask(struct irq_data *d) ++{ ++ U16 gpi_irq; ++ ++ gpi_irq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, gpi_irq); ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_00 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_57, BIT8); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++} ++ ++ ++static int ss_gpi_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 gpi_irq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ gpi_irq = d->hwirq; ++ ++ if( gpi_irq >= 0 && gpi_irq < GPI_FIQ_END ) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ SETREG16( (BASE_REG_GPI_INT_PA + REG_ID_18 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ CLRREG16( (BASE_REG_GPI_INT_PA + REG_ID_18 + (gpi_irq/16)*4 ) , (1 << (gpi_irq%16)) ); ++ break; ++ default: ++ return -EINVAL; ++ ++ } ++ // prevent the very 1st unexpected trigger right after irq_request() ++ // http://mantis.sigmastar.com.tw/view.php?id=1688845 ++ ss_gpi_irq_ack(d); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct irq_chip ss_gpi_intc_irqchip = { ++ .name = "MS_GPI_INTC", ++ .irq_ack = ss_gpi_irq_ack, ++ .irq_eoi = ss_gpi_irq_ack, ++ .irq_mask = ss_gpi_irq_mask, ++ .irq_unmask = ss_gpi_irq_unmask, ++ .irq_set_type = ss_gpi_irq_set_type, ++}; ++EXPORT_SYMBOL(ss_gpi_intc_irqchip); ++ ++ ++static void ss_handle_cascade_gpi(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i, j; ++ unsigned int virq=0xFFFFFFFF; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ for (j=0; j<=GPI_FIQ_NUM/16; j++) ++ { ++ final_status = INREG16(BASE_REG_GPI_INT_PA + REG_ID_30 + j*4); ++ for(i=0; i<16 && final_status!=0; i++) ++ { ++ if(0 !=(final_status & (1<fwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ss_gpi_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ss_gpi_intc_irqchip, NULL, handle_edge_irq, NULL, NULL); ++ pr_err("[%s] hw:%d -> v:%d\n", __FUNCTION__, (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ss_gpi_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ss_gpi_intc_domain_ops = { ++ .translate = ss_gpi_intc_domain_translate, ++ .alloc = ss_gpi_intc_domain_alloc, ++ .free = ss_gpi_intc_domain_free, ++}; ++ ++#ifdef CONFIG_PM_SLEEP ++static int ss_gpi_intc_suspend(void) ++{ ++ unsigned int i, num; ++ ++ num = (GPI_FIQ_NUM + 15) >> 4; ++ for (i = 0; i < num; i++) { ++ gpi_irq_priv.polarity[i] = INREG16(BASE_REG_GPI_INT_PA + REG_ID_18 + (i << 2)); ++ } ++ ++ pr_debug("ss_gpi_intc_suspend\n\n"); ++ return 0; ++} ++ ++static void ss_gpi_intc_resume(void) ++{ ++ unsigned int i, num; ++ ++ num = (GPI_FIQ_NUM + 15) >> 4; ++ for (i = 0; i < num; i++) { ++ OUTREG16(BASE_REG_GPI_INT_PA + REG_ID_18 + (i << 2), gpi_irq_priv.polarity[i]); ++ } ++ pr_debug("ss_gpi_intc_resume\n\n"); ++} ++ ++struct syscore_ops ss_gpi_intc_syscore_ops = { ++ .suspend = ss_gpi_intc_suspend, ++ .resume = ss_gpi_intc_resume, ++}; ++#endif ++ ++static int __init ss_init_gpi_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ss_gpi_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ss_gpi_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ //PMSLEEP_FIQ_NR, //76 ++ GPI_FIQ_NUM, //94 ++ np, &ss_gpi_intc_domain_ops, NULL); ++ ++ if (!ss_gpi_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ss_handle_cascade_gpi, ss_gpi_irq_domain); ++#ifdef CONFIG_PM_SLEEP ++ register_syscore_ops(&ss_gpi_intc_syscore_ops); ++#endif ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ss_gpi_intc, "sstar,gpi-intc", ss_init_gpi_intc); +diff --git a/drivers/sstar/irqchip/infinity6e/irq-pmsleep.c b/drivers/sstar/irqchip/infinity6e/irq-pmsleep.c +new file mode 100755 +index 000000000000..22ff84bb2c37 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6e/irq-pmsleep.c +@@ -0,0 +1,398 @@ ++/* ++* irq-pmsleep.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++ ++#define PMGPIO_OEN BIT0 ++#define PMGPIO_OUTPUT BIT1 ++#define PMGPIO_INPUT BIT2 ++#define PMGPIO_FIQ_MASK BIT4 ++#define PMGPIO_FIQ_FROCE BIT5 ++#define PMGPIO_FIQ_CLEAR BIT6 ++#define PMGPIO_FIQ_POLARITY BIT7 ++#define PMGPIO_FIQ_FINAL_STATUS BIT8 ++#define PMGPIO_FIQ_RAW_STATUS BIT9 ++ ++#ifdef CONFIG_PM_SLEEP ++#define PM_FIQ_NUM (INT_PMSLEEP_SAR_GPIO5 - PMSLEEP_FIQ_START + 1) ++ ++/** ++ * struct ms_pm_irq_priv - private pm interrupt data ++ * @fiq_flags: Flags of each pm-gpio fiq ++ * @irq_polarity: Polarity of pm-sleep irq ++ */ ++struct ms_pm_irq_priv { ++ U16 fiq_flags[PM_FIQ_NUM]; ++ U8 irq_polarity; ++}; ++ ++static struct ms_pm_irq_priv pm_irq_priv; ++#endif ++ ++static void ms_pm_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + ((pmsleep_fiq-PMSLEEP_FIQ_START) << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_eoi(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + ((pmsleep_fiq-PMSLEEP_FIQ_START) << 2), PMGPIO_FIQ_CLEAR); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ SETREG16(BASE_REG_PMGPIO_PA + ((pmsleep_fiq-PMSLEEP_FIQ_START) << 2), PMGPIO_FIQ_MASK); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++} ++ ++static void ms_pm_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ pr_debug("[%s] hw:%d \n",__FUNCTION__, pmsleep_fiq); ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ CLRREG16(BASE_REG_PMGPIO_PA + ((pmsleep_fiq-PMSLEEP_FIQ_START) << 2), PMGPIO_FIQ_MASK); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++} ++ ++static int ms_pm_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ pr_debug("%s %d type:0x%08x\n", __FUNCTION__, __LINE__, type); ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG16(BASE_REG_PMGPIO_PA + ((pmsleep_fiq-PMSLEEP_FIQ_START) << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG16(BASE_REG_PMGPIO_PA + ((pmsleep_fiq-PMSLEEP_FIQ_START) << 2), PMGPIO_FIQ_POLARITY); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ switch(type) ++ { ++ case IRQ_TYPE_EDGE_FALLING: ++ case IRQ_TYPE_LEVEL_LOW: ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ case IRQ_TYPE_LEVEL_HIGH: ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return -EINVAL; ++ } ++ // prevent the very 1st unexpected trigger right after irq_request() ++ // http://mantis.sigmastar.com.tw/view.php?id=1688845 ++ ms_pm_irq_ack(d); ++ ++ return 0; ++} ++ ++struct irq_chip ms_pm_intc_irqchip = { ++ .name = "MS_PM_INTC", ++ .irq_ack = ms_pm_irq_ack, ++ .irq_eoi = ms_pm_irq_eoi, ++ .irq_mask = ms_pm_irq_mask, ++ .irq_unmask = ms_pm_irq_unmask, ++ .irq_set_type = ms_pm_irq_set_type, ++}; ++EXPORT_SYMBOL(ms_pm_intc_irqchip); ++ ++static DEFINE_SPINLOCK(ss_irq_controller_lock); ++ ++static void ms_handle_cascade_pm_irq(struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ unsigned int virq = 0 ; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct irq_domain *domain = irq_desc_get_handler_data(desc); ++ unsigned int final_status; ++ ++ if(!domain) ++ { ++ printk("[%s] err %d \n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ ++ spin_lock(&ss_irq_controller_lock); ++ for(i=PMSLEEP_FIQ_START;ifwnode)) { ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_pm_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 1) ++ return -EINVAL; ++ ++ hwirq = fwspec->param[0]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_info(domain, virq + i, hwirq + i , &ms_pm_intc_irqchip, NULL, handle_fasteoi_irq, NULL, NULL); ++ pr_err("[MS_PM_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ ++ return 0; ++} ++ ++static void ms_pm_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_pm_intc_domain_ops = { ++ .translate = ms_pm_intc_domain_translate, ++ .alloc = ms_pm_intc_domain_alloc, ++ .free = ms_pm_intc_domain_free, ++}; ++ ++#ifdef CONFIG_PM_SLEEP ++static int ms_pm_intc_suspend(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < PM_FIQ_NUM; i++) { ++ pm_irq_priv.fiq_flags[i] = INREG16(BASE_REG_PMGPIO_PA + (i << 2)); ++ pm_irq_priv.fiq_flags[i] |= PMGPIO_FIQ_MASK; // always set mask here, unmask will be set by irq/pm.c ++ } ++ pm_irq_priv.irq_polarity = INREG8(BASE_REG_PMSLEEP_PA + REG_ID_09); ++ ++ pr_debug("ms_pm_intc_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_pm_intc_resume(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < PM_FIQ_NUM; i++) { ++ OUTREG16(BASE_REG_PMGPIO_PA + (i << 2), pm_irq_priv.fiq_flags[i]); ++ } ++ OUTREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, pm_irq_priv.irq_polarity); ++ pr_debug("ms_pm_intc_resume\n\n"); ++} ++ ++struct syscore_ops ms_pm_intc_syscore_ops = { ++ .suspend = ms_pm_intc_suspend, ++ .resume = ms_pm_intc_resume, ++}; ++#endif ++ ++static int __init ms_init_pm_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *ms_pm_irq_domain; ++ int irq=0; ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ ms_pm_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ++ PMSLEEP_FIQ_NR, ++ np, &ms_pm_intc_domain_ops, NULL); ++ ++ if (!ms_pm_irq_domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++ ++ irq = irq_of_parse_and_map(np, 0); ++ if (!irq) ++ { ++ pr_err("Get irq err from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ irq_set_chained_handler_and_data(irq, ms_handle_cascade_pm_irq, ms_pm_irq_domain); ++ ++#ifdef CONFIG_PM_SLEEP ++ register_syscore_ops(&ms_pm_intc_syscore_ops); ++#endif ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_pm_intc, "sstar,pm-intc", ms_init_pm_intc); +diff --git a/drivers/sstar/irqchip/infinity6e/irqchip.c b/drivers/sstar/irqchip/infinity6e/irqchip.c +new file mode 100755 +index 000000000000..06e8f2192343 +--- /dev/null ++++ b/drivers/sstar/irqchip/infinity6e/irqchip.c +@@ -0,0 +1,389 @@ ++/* ++* irqchip.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "irqs.h" ++#include "registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++#include ++#include ++#include ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++#ifdef CONFIG_PM_SLEEP ++/** ++ * struct ms_main_irq_priv - private main interrupt data ++ * @irq_polarity: irq polarity ++ * @fiq_polarity: fiq polarity ++ */ ++struct ms_main_irq_priv { ++ U16 irq_polarity[(GIC_SPI_MS_IRQ_NR)>>4]; ++ U16 fiq_polarity[(GIC_SPI_MS_FIQ_NR)>>4]; ++}; ++ ++static struct ms_main_irq_priv ms_main_irq_priv; ++#endif ++ ++static void ms_main_irq_ack(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ if(d && d->chip && d->parent_data && d->parent_data->chip->irq_ack) ++ { ++ irq_chip_ack_parent(d); ++ } ++} ++ ++static void ms_main_irq_eoi(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[%s] Unknown hwirq %lu, ms_fiq %d\n", __func__, d->hwirq, ms_fiq); ++ return; ++ } ++ ++ irq_chip_eoi_parent(d); ++} ++ ++static void ms_main_irq_mask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ pr_debug("[%s] hwirq %lu %s=%d\n", __func__, d->hwirq, (ms_fiq>=0)?"ms_fiq":"ms_irq",(ms_fiq>=0)?ms_fiq:ms_irq); ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_mask_parent(d); ++} ++ ++static void ms_main_irq_unmask(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = d->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ INREG16(BASE_REG_MAILBOX_PA);//read a register make ensure the previous write command was compeleted ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, d->hwirq); ++ return; ++ } ++ ++ irq_chip_unmask_parent(d); ++} ++ ++static int ms_main_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("Not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ ++ ms_irq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR; ++ ms_fiq = data->hwirq - GIC_SPI_ARM_INTERNAL_NR - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[%s] Unknown hwirq %lu\n", __func__, data->hwirq); ++ return -EINVAL; ++ } ++ irq_chip_set_type_parent(data, flow_type); ++ return 0; ++ ++} ++ ++#ifdef CONFIG_SMP ++static int ms_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++{ ++ //use a very simple implementation here... ++ return irq_chip_set_affinity_parent(data,dest,true); ++} ++#endif ++ ++struct irq_chip ms_main_intc_irqchip = { ++ .name = "MS_MAIN_INTC", ++ .irq_ack = ms_main_irq_ack, ++ .irq_eoi = ms_main_irq_eoi, ++ .irq_mask = ms_main_irq_mask, ++ .irq_unmask = ms_main_irq_unmask, ++ .irq_set_type = ms_main_irq_set_type, ++#ifdef CONFIG_SMP ++ .irq_set_affinity=ms_irq_set_affinity, ++#endif ++}; ++EXPORT_SYMBOL(ms_main_intc_irqchip); ++ ++static int ms_main_intc_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, ++ unsigned long *hwirq, unsigned int *type) ++{ ++ if (is_of_node(fwspec->fwnode)) { ++ if (fwspec->param_count != 3) ++ return -EINVAL; ++ ++ /* No PPI should point to this domain */ ++ if (fwspec->param[0] != 0) ++ return -EINVAL; ++ ++ *hwirq = fwspec->param[1]; ++ *type = fwspec->param[2]; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int ms_main_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *data) ++{ ++ struct irq_fwspec *fwspec = data; ++ struct irq_fwspec parent_fwspec; ++ irq_hw_number_t hwirq; ++ unsigned int i; ++ ++ if (fwspec->param_count != 3) ++ return -EINVAL; /* Not GIC compliant */ ++ ++ if (fwspec->param[0] != GIC_SPI) ++ return -EINVAL; /* No PPI should point to this domain */ ++ ++ hwirq = fwspec->param[1]; ++ ++ for (i = 0; i < nr_irqs; i++) ++ { ++ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &ms_main_intc_irqchip, NULL); ++ pr_debug("[MS_MAIN_INTC] hw:%d -> v:%d\n", (unsigned int)hwirq+i, virq+i); ++ } ++ ++ parent_fwspec = *fwspec; ++ parent_fwspec.fwnode = domain->parent->fwnode; ++ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, ++ &parent_fwspec); ++} ++ ++static void ms_main_intc_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr_irqs; i++) { ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); ++ irq_domain_reset_irq_data(d); ++ } ++} ++ ++ ++struct irq_domain_ops ms_main_intc_domain_ops = { ++ .translate = ms_main_intc_domain_translate, ++ .alloc = ms_main_intc_domain_alloc, ++ .free = ms_main_intc_domain_free, ++}; ++ ++#ifdef CONFIG_PM_SLEEP ++static int ms_irqchip_suspend(void) ++{ ++ unsigned int i, num; ++ ++ num = (GIC_SPI_MS_IRQ_NR) >> 4; ++ for (i = 0; i < num; i++) { ++ ms_main_irq_priv.irq_polarity[i] = INREG16(BASE_REG_INTRCTL_PA + REG_ID_58 + (i << 2)); ++ } ++ num = (GIC_SPI_MS_FIQ_NR) >> 4; ++ for (i = 0; i < num; i++) { ++ ms_main_irq_priv.fiq_polarity[i] = INREG16(BASE_REG_INTRCTL_PA + REG_ID_48 + (i << 2)); ++ } ++ ++ pr_debug("ms_irqchip_suspend\n\n"); ++ return 0; ++} ++ ++static void ms_irqchip_resume(void) ++{ ++ unsigned int i, num; ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ num = (GIC_SPI_MS_IRQ_NR) >> 4; ++ for (i = 0; i < num; i++) { ++ OUTREG16(BASE_REG_INTRCTL_PA + REG_ID_58 + (i << 2), ms_main_irq_priv.irq_polarity[i]); ++ } ++ num = (GIC_SPI_MS_FIQ_NR) >> 4; ++ for (i = 0; i < num; i++) { ++ OUTREG16(BASE_REG_INTRCTL_PA + REG_ID_48 + (i << 2), ms_main_irq_priv.fiq_polarity[i]); ++ } ++ ++ pr_debug("ms_irqchip_resume\n\n"); ++} ++ ++struct syscore_ops ms_irq_syscore_ops = { ++ .suspend = ms_irqchip_suspend, ++ .resume = ms_irqchip_resume, ++}; ++#endif ++ ++static int __init ms_init_main_intc(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ struct irq_domain *parent_domain, *domain; ++ ++ if (!interrupt_parent) ++ { ++ pr_err("%s: %s no parent\n", __func__, np->name); ++ return -ENODEV; ++ } ++ ++ pr_err("%s: np->name=%s, parent=%s\n", __func__, np->name, interrupt_parent->name); ++ ++ parent_domain = irq_find_host(interrupt_parent); ++ if (!parent_domain) ++ { ++ pr_err("%s: %s unable to obtain parent domain\n", __func__, np->name); ++ return -ENXIO; ++ } ++ ++ //Patch for disable bypass IRQ/FIQ ++ { ++ u32 bypass = 0; ++ bypass = INREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL); ++ bypass |= GICC_DIS_BYPASS_MASK; ++ OUTREG32(GIC_PHYS + 0x2000 + GIC_CPU_CTRL, bypass | GICC_ENABLE); ++ } ++ ++ domain = irq_domain_add_hierarchy(parent_domain, 0, ++ GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR, ++ np, &ms_main_intc_domain_ops, NULL); ++ ++ if (!domain) ++ { ++ pr_err("%s: %s allocat domain fail\n", __func__, np->name); ++ return -ENOMEM; ++ } ++#ifdef CONFIG_PM_SLEEP ++ register_syscore_ops(&ms_irq_syscore_ops); ++#endif ++ return 0; ++} ++ ++IRQCHIP_DECLARE(ms_main_intc, "sstar,main-intc", ms_init_main_intc); +diff --git a/drivers/sstar/isrcb/Kconfig b/drivers/sstar/isrcb/Kconfig +new file mode 100644 +index 000000000000..00e4e96ee33a +--- /dev/null ++++ b/drivers/sstar/isrcb/Kconfig +@@ -0,0 +1,7 @@ ++#config MS_ISRCB ++# boolean "Mstar ISRCB driver" ++# help ++# MStar ISRCB driver function ++ ++config SS_ISP_ISRCB ++ tristate "ISRCB driver support" +diff --git a/drivers/sstar/isrcb/Makefile b/drivers/sstar/isrcb/Makefile +new file mode 100644 +index 000000000000..82067cf10e90 +--- /dev/null ++++ b/drivers/sstar/isrcb/Makefile +@@ -0,0 +1,13 @@ ++# ++# Makefile for interrupt router driver ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/cam_os_wrapper/pub ++EXTRA_CFLAGS += -Idrivers/sstar/isrcb/drv/pub ++ ++# files ++obj-$(CONFIG_SS_ISP_ISRCB) := isrcb.o ++isrcb-y := drv/src/common/drv_isrcb.o\ ++ drv/src/linux/drv_isrcb_module.o +diff --git a/drivers/sstar/isrcb/drv/pub/drv_isrcb.h b/drivers/sstar/isrcb/drv/pub/drv_isrcb.h +new file mode 100644 +index 000000000000..79c6f0bc3033 +--- /dev/null ++++ b/drivers/sstar/isrcb/drv/pub/drv_isrcb.h +@@ -0,0 +1,49 @@ ++/* ++* drv_isrcb.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Andy.Hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_ISRCB_ ++#define _DRV_ISRCB_ ++ ++typedef enum ++{ ++ eISRCB_ID_ISP_WDMA0_DONE=0, ++ eISRCB_ID_ISP_WDMA1_DONE, ++ eISRCB_ID_ISP_WDMA2_DONE, ++ eISRCB_ID_ISP_WDMA3_DONE, ++ eISRCB_ID_ISP_WDMA0_HIT_LINE_CNT, ++ eISRCB_ID_ISP_WDMA1_HIT_LINE_CNT, ++ eISRCB_ID_ISP_WDMA2_HIT_LINE_CNT, ++ eISRCB_ID_ISP_WDMA3_HIT_LINE_CNT, ++ eISRCB_ID_ISP_VIF0_FRAME_START, ++ eISRCB_ID_ISP_VIF1_FRAME_START, ++ eISRCB_ID_ISP_VIF2_FRAME_START, ++ eISRCB_ID_ISP_VIF3_FRAME_START, ++ eISRCB_ID_ISP_VIF0_FRAME_END, ++ eISRCB_ID_ISP_VIF1_FRAME_END, ++ eISRCB_ID_ISP_VIF2_FRAME_END, ++ eISRCB_ID_ISP_VIF3_FRAME_END, ++ eISRCB_ID_MAX, ++}ISRCB_ID_e; ++ ++typedef void* ISRCB_Handle; ++typedef void (*ISRCB_fp)(void* pData); ++ ++ISRCB_Handle ISRCB_RegisterCallback(ISRCB_ID_e eID,ISRCB_fp fpCB,void* pData); ++void ISRCB_UnRegisterCallback(ISRCB_Handle hHnd); ++void ISRCB_Proc(ISRCB_ID_e eID); ++ ++#endif +diff --git a/drivers/sstar/isrcb/drv/src/common/drv_isrcb.c b/drivers/sstar/isrcb/drv/src/common/drv_isrcb.c +new file mode 100644 +index 000000000000..dd6fdd3181ab +--- /dev/null ++++ b/drivers/sstar/isrcb/drv/src/common/drv_isrcb.c +@@ -0,0 +1,78 @@ ++/* ++* drv_isrcb.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Andy.Hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++ ++#define _MAX_CALLBACKS_ 8 ++ ++typedef struct ++{ ++ void* pData; ++ ISRCB_fp fpISRCB; ++}CBInfo_t; ++ ++CBInfo_t g_CBInfo[eISRCB_ID_MAX][_MAX_CALLBACKS_]; ++ ++//int __init ISRCB_EarlyInit(void) ++int ISRCB_EarlyInit(void) ++{ ++ int n; ++ int nID; ++ for(nID=0;nIDfpISRCB = 0; ++ pInfo->pData = 0; ++} ++ ++void ISRCB_Proc(ISRCB_ID_e eID) ++{ ++ int n=0; ++ for(n=0;n<_MAX_CALLBACKS_;++n) ++ { ++ if(g_CBInfo[eID][n].fpISRCB) ++ g_CBInfo[eID][n].fpISRCB(g_CBInfo[eID][n].pData); ++ } ++} +diff --git a/drivers/sstar/isrcb/drv/src/linux/drv_isrcb_module.c b/drivers/sstar/isrcb/drv/src/linux/drv_isrcb_module.c +new file mode 100644 +index 000000000000..824479f3f16f +--- /dev/null ++++ b/drivers/sstar/isrcb/drv/src/linux/drv_isrcb_module.c +@@ -0,0 +1,45 @@ ++/* ++* drv_isrcb_module.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Andy.Hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++ ++EXPORT_SYMBOL(ISRCB_RegisterCallback); ++EXPORT_SYMBOL(ISRCB_UnRegisterCallback); ++EXPORT_SYMBOL(ISRCB_Proc); ++ ++//int __init ISRCB_EarlyInit(void); ++//early_initcall(ISRCB_EarlyInit); ++ ++int ISRCB_EarlyInit(void); ++static int __init isrcb_init_driver(void) ++{ ++ ISRCB_EarlyInit(); ++ return 0; ++} ++ ++static void __exit isrcb_exit_driver(void) ++{ ++} ++ ++subsys_initcall(isrcb_init_driver); ++module_exit(isrcb_exit_driver); ++ ++MODULE_DESCRIPTION("Isp interrupt dispatcher driver"); ++MODULE_AUTHOR("SSTAR"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/ive/Kconfig b/drivers/sstar/ive/Kconfig +new file mode 100755 +index 000000000000..14d36d6e95a3 +--- /dev/null ++++ b/drivers/sstar/ive/Kconfig +@@ -0,0 +1,3 @@ ++config MS_IVE ++ tristate "Mstar IVE driver" ++ help +diff --git a/drivers/sstar/ive/Makefile b/drivers/sstar/ive/Makefile +new file mode 100755 +index 000000000000..5ebabd166293 +--- /dev/null ++++ b/drivers/sstar/ive/Makefile +@@ -0,0 +1,22 @@ ++# ++# Makefile for MStar Infinity3 IVE device drivers. ++ ++IVE_CHIP_DIR := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/ive ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ ++ccflags-$(CONFIG_MS_IVE) += -DMSOS_TYPE_LINUX_KERNEL ++ ++ifeq ($(CONFIG_SSTAR_CHIP_NAME), "infinity2") ++ EXTRA_CFLAGS += -DCONFIG_CHIP_INFINITY2 ++endif ++ ++# files ++obj-$(CONFIG_MS_IVE) += mstar_ive.o ++mstar_ive-y := mdrv_ive.o \ ++ hal_ive.o \ ++ hal_clk.o \ ++ drv_ive.o \ ++ hal_ive_simulate.o +diff --git a/drivers/sstar/ive/drv_ive.c b/drivers/sstar/ive/drv_ive.c +new file mode 100755 +index 000000000000..96d2a1ee7100 +--- /dev/null ++++ b/drivers/sstar/ive/drv_ive.c +@@ -0,0 +1,576 @@ ++/* ++* drv_ive.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mdrv_ive.h" ++#include "drv_ive.h" ++#include "hal_ive.h" ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define MINIMUM_WIDTH 16 ++#define MINIMUM_HEIGHT 5 ++ ++typedef struct { ++ struct list_head list; ++ ive_file_data *file_data; ++} ive_request_data; ++ ++/******************************************************************************************************************* ++ * drv_ive_extract_request ++ * Extract a request from waiting list ++ * The request is removed from list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * ++ * Return: ++ * File data of IVE driver ++ */ ++static ive_file_data* drv_ive_extract_request(ive_drv_handle *handle) ++{ ++ struct platform_device *pdev = handle->pdev; ++ ive_request_data *list_data = NULL; ++ ive_file_data *file_data = NULL; ++ ++ if (list_empty(&handle->request_list)) ++ { ++ return NULL; ++ } ++ ++ list_data = list_first_entry(&handle->request_list, ive_request_data, list); ++ if (list_data != NULL) { ++ list_del(handle->request_list.next); ++ file_data = list_data->file_data; ++ IVE_MSG(IVE_MSG_DBG, "extract: 0x%p, 0x%p\n", list_data, file_data); ++ devm_kfree(&pdev->dev, list_data); ++ } else { ++ IVE_MSG(IVE_MSG_DBG, "extract: 0x%p\n", list_data); ++ } ++ ++ return file_data; ++} ++ ++ ++/******************************************************************************************************************* ++ * drv_ive_get_request ++ * Get a request from waiting list ++ * The request is still kpet in list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * ++ * Return: ++ * File data of IVE driver ++ */ ++static ive_file_data* drv_ive_get_request(ive_drv_handle *handle) ++{ ++ ive_request_data *list_data = NULL; ++ ++ if (list_empty(&handle->request_list)) ++ { ++ return NULL; ++ } ++ ++ list_data = list_first_entry(&handle->request_list, ive_request_data, list); ++ if (list_data != NULL) { ++ IVE_MSG(IVE_MSG_DBG, "get: 0x%p, 0x%p\n", list_data, list_data->file_data); ++ return list_data->file_data; ++ } else { ++ IVE_MSG(IVE_MSG_DBG, "get: 0x%p\n", list_data); ++ } ++ ++ return NULL; ++} ++ ++/******************************************************************************************************************* ++ * drv_ive_add_request ++ * Add a request to waiting list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * file_data: File data of IVE driver ++ * ++ * Return: ++ * none ++ */ ++static void drv_ive_add_request(ive_drv_handle *handle, ive_file_data *file_data) ++{ ++ struct platform_device *pdev = handle->pdev; ++ ive_request_data *list_data; ++ ++ list_data = devm_kcalloc(&pdev->dev, 1, sizeof(ive_request_data), GFP_KERNEL); ++ list_data->file_data = file_data; ++ ++ IVE_MSG(IVE_MSG_DBG, "add: 0x%p, 0x%p\n", list_data, file_data); ++ ++ if (list_data != NULL) { ++ list_add_tail(&list_data->list, &handle->request_list); ++ } ++} ++ ++/******************************************************************************************************************* ++ * drv_ive_check_config ++ * Check the configuration ++ * ++ * Parameters: ++ * config: IO configuration ++ * ++ * Return: ++ * standard return enum ++ */ ++static IVE_IOC_ERROR drv_ive_check_config(ive_ioc_config *config) ++{ ++ switch (config->op_type) ++ { ++ case IVE_IOC_OP_TYPE_SAD: ++ break; ++ ++ case IVE_IOC_OP_TYPE_NCC: ++ case IVE_IOC_OP_TYPE_MAP: ++ case IVE_IOC_OP_TYPE_HISTOGRAM: ++ case IVE_IOC_OP_TYPE_BAT: ++ return IVE_IOC_ERROR_NONE; ++ ++ default: ++ if (config->input.width != config->output.width || config->input.height != config->output.height) { ++ IVE_MSG(IVE_MSG_ERR, "Input and output size are not the same\n"); ++ return IVE_IOC_ERROR_IN_OUT_SIZE_DIFFERENT; ++ } ++ break; ++ } ++ ++ if (config->input.width < MINIMUM_WIDTH || config->input.height < MINIMUM_HEIGHT) { ++ IVE_MSG(IVE_MSG_ERR, "The minimum withd/height is %d\n", MINIMUM_WIDTH); ++ return IVE_IOC_ERROR_IMG_TOO_SMALL; ++ } ++ ++ return IVE_IOC_ERROR_NONE; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_sync_image ++ * Sync image ++ * ++ * Parameters: ++ * handle: device handle ++ * image: image ++ * direct: DMA directon ++ * ++ * Return: ++ * None ++ */ ++static void ive_drv_sync_image(ive_drv_handle *handle, ive_ioc_image *image, enum dma_data_direction direct) ++{ ++#ifdef USE_MIU_DIRECT ++ IVE_MSG(IVE_MSG_DBG, "sync buffer %p, but nothing to do for MIU buffer\n", image->address[0]); ++#else ++ int i, size, byte_per_pixel; ++ ++ switch (image->format) ++ { ++ case IVE_IOC_IMAGE_FORMAT_B8C1: ++ byte_per_pixel = sizeof(u8); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B16C1: ++ byte_per_pixel = sizeof(u16); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B32C1: ++ byte_per_pixel = sizeof(u32); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B64C1: ++ byte_per_pixel = sizeof(u64); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B8C3_PACK: ++ byte_per_pixel = sizeof(u8) * 3; ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B8C3_PLAN: ++ size = image->stride[0] * image->height * sizeof(u8); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[0], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[1], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[2], size, direct); ++ return; ++ ++ case IVE_IOC_IMAGE_FORMAT_420SP: ++ size = image->stride[0] * image->height * sizeof(u8); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[0], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[1], size/2, direct); ++ return; ++ ++ case IVE_IOC_IMAGE_FORMAT_422SP: ++ size = image->stride[0] * image->height * sizeof(u8); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[0], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[1], size, direct); ++ return; ++ ++ default: ++ return; ++ } ++ ++ // sync for single channel, HW use multi channel to represent multi inputs ++ for (i=0; i<3; i++) ++ { ++ if (image->address[i] != NULL) ++ { ++ size = image->stride[i] * image->height * byte_per_pixel; ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[i], size, direct); ++ IVE_MSG(IVE_MSG_DBG, "sync buffer %p, format %x, size %d * %d * %d = %d\n", image->address[i], image->format, image->stride[i], image->height, byte_per_pixel, size); ++ } ++ } ++#endif ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_set_images ++ * Set & sync input/output images ++ * ++ * Parameters: ++ * handle: device handle ++ * config: configuration ++ * ++ * Return: ++ * None ++ */ ++static void ive_drv_set_images(ive_drv_handle *handle, ive_ioc_config *config) ++{ ++ ive_hal_set_images(&handle->hal_handle, &config->input, &config->output); ++ ++ switch (config->op_type) ++ { ++ case IVE_IOC_OP_TYPE_NCC: ++ ive_drv_sync_image(handle, &config->input, DMA_TO_DEVICE); ++ break; ++ ++ default: ++ ive_drv_sync_image(handle, &config->input, DMA_TO_DEVICE); ++ ive_drv_sync_image(handle, &config->output, DMA_FROM_DEVICE); ++ break; ++ } ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_drv_isr_handler ++ * ISR handler ++ * ++ * Parameters: ++ * irq: interrupt number ++ * handle: device handle ++ * ++ * Return: ++ * None ++ */ ++IVE_DRV_STATE ive_drv_isr_handler(int irq, ive_drv_handle *handle) ++{ ++ IVE_MSG(IVE_MSG_DBG, "Interrupt: 0x%X\n", ive_hal_get_irq(&handle->hal_handle)); ++ ++ // IVE_HAL_IRQ_MASK_FRAME_DONE ++ if(ive_hal_get_irq_check(&handle->hal_handle, IVE_HAL_IRQ_MASK_FRAME_DONE)) { ++ handle->dev_state = IVE_DRV_STATE_DONE; ++ ++ // Clear IRQ ++ ive_hal_clear_irq(&handle->hal_handle, IVE_HAL_IRQ_MASK_FRAME_DONE); ++ ++ return IVE_DRV_STATE_DONE; ++ } ++ ++ return IVE_DRV_STATE_PROCESSING; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_init ++ * Init IVEG settings ++ * ++ * Parameters: ++ * handle: device handle ++ * pdev: platform device ++ * base_addr0: base addr of HW register bank 0 ++ * base_addr1: base addr of HW register bank 1 ++ * ++ * Return: ++ * none ++ */ ++int ive_drv_init(ive_drv_handle *handle, struct platform_device *pdev, phys_addr_t base_addr0, phys_addr_t base_addr1) ++{ ++ IVE_MSG(IVE_MSG_DBG, "name: %s, addr 0x%08X, 0x%08X\n", pdev->name, base_addr0, base_addr1); ++ ++ memset(handle, 0, sizeof(ive_drv_handle)); ++ ++ ive_hal_init(&handle->hal_handle, base_addr0, base_addr1); ++ INIT_LIST_HEAD(&handle->request_list); ++ IVE_MSG(IVE_MSG_DBG, "list_empty = %d\n", list_empty(&handle->request_list)); ++ ++ handle->pdev = pdev; ++ handle->dev_state = IVE_DRV_STATE_READY; ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_release ++ * Release IVEG settings ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * none ++ */ ++void ive_drv_release(ive_drv_handle *handle) ++{ ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_start ++ * Start HW engine ++ * ++ * Parameters: ++ * handle: device handle ++ * config: IVE configurations ++ * ++ * Return: ++ * none ++ */ ++static void ive_drv_start(ive_drv_handle *handle, ive_ioc_config *config) ++{ ++ IVE_MSG(IVE_MSG_DBG, "op_type: 0x%X\n", config->op_type); ++ ++ ive_hal_sw_reset(&handle->hal_handle); ++ ++ ive_hal_set_operation(&handle->hal_handle, config->op_type); ++ ++ ive_drv_set_images(handle, config); ++ ++ switch (config->op_type) { ++ case IVE_IOC_OP_TYPE_FILTER: ++ ive_hal_set_coeff_filter(&handle->hal_handle, &config->coeff_filter); ++ break; ++ ++ case IVE_IOC_OP_TYPE_CSC: ++ ive_hal_set_coeff_csc(&handle->hal_handle, &config->coeff_csc); ++ break; ++ ++ case IVE_IOC_OP_TYPE_FILTER_AND_CSC: ++ ive_hal_set_coeff_filter(&handle->hal_handle, &config->coeff_filter_csc.filter); ++ ive_hal_set_coeff_csc(&handle->hal_handle, &config->coeff_filter_csc.csc); ++ break; ++ ++ case IVE_IOC_OP_TYPE_SOBEL: ++ ive_hal_set_coeff_sobel(&handle->hal_handle, &config->coeff_sobel); ++ break; ++ ++ case IVE_IOC_OP_TYPE_MAG_AND_ANG: ++ ive_hal_set_coeff_mag_and_ang(&handle->hal_handle, &config->coeff_mag_and_ang); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ORD_STA_FILTER: ++ ive_hal_set_coeff_ord_stat_filter(&handle->hal_handle, &config->coeff_ord_stat_filter); ++ break; ++ ++ case IVE_IOC_OP_TYPE_BERNSEN: ++ ive_hal_set_coeff_bernsen(&handle->hal_handle, &config->coeff_bernsen); ++ break; ++ ++ case IVE_IOC_OP_TYPE_DILATE: ++ ive_hal_set_coeff_dilate(&handle->hal_handle, &config->coeff_dilate); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ERODE: ++ ive_hal_set_coeff_erode(&handle->hal_handle, &config->coeff_erode); ++ break; ++ ++ case IVE_IOC_OP_TYPE_THRESH: ++ ive_hal_set_coeff_thresh(&handle->hal_handle, &config->coeff_thresh); ++ break; ++ ++ case IVE_IOC_OP_TYPE_THRESH_S16: ++ ive_hal_set_coeff_thresh_s16(&handle->hal_handle, &config->coeff_thresh_s16); ++ break; ++ ++ case IVE_IOC_OP_TYPE_THRESH_U16: ++ ive_hal_set_coeff_thresh_u16(&handle->hal_handle, &config->coeff_thresh_u16); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ADD: ++ ive_hal_set_coeff_add(&handle->hal_handle, &config->coeff_add); ++ break; ++ ++ case IVE_IOC_OP_TYPE_SUB: ++ ive_hal_set_coeff_sub(&handle->hal_handle, &config->coeff_sub); ++ break; ++ ++ case IVE_IOC_OP_TYPE_16BIT_TO_8BIT: ++ ive_hal_set_coeff_16to8(&handle->hal_handle, &config->coeff_16to8); ++ break; ++ ++ case IVE_IOC_OP_TYPE_MAP: ++ ive_hal_set_coeff_map(&handle->hal_handle, (uintptr_t)config->coeff_map.map); ++ break; ++ ++ case IVE_IOC_OP_TYPE_INTEGRAL: ++ ive_hal_set_coeff_integral(&handle->hal_handle, &config->coeff_integral); ++ break; ++ ++ case IVE_IOC_OP_TYPE_SAD: ++ ive_hal_set_coeff_sad(&handle->hal_handle, &config->coeff_sad); ++ break; ++ ++ case IVE_IOC_OP_TYPE_NCC: ++ ive_hal_set_coeff_ncc(&handle->hal_handle, (uintptr_t)config->coeff_ncc); ++ break; ++ ++ case IVE_IOC_OP_TYPE_LBP: ++ ive_hal_set_coeff_lbp(&handle->hal_handle, &config->coeff_lbp); ++ break; ++ ++ case IVE_IOC_OP_TYPE_BAT: ++ ive_hal_set_coeff_bat(&handle->hal_handle, &config->coeff_bat); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ADP_THRESH: ++ ive_hal_set_coeff_adp_thresh(&handle->hal_handle, &config->coeff_adp_thresh); ++ break; ++ ++ case IVE_IOC_OP_TYPE_MATRIX_TRANSFORM: ++ ive_hal_set_coeff_matrix_transform(&handle->hal_handle, &config->coeff_matrix_transform); ++ break; ++ ++ case IVE_IOC_OP_TYPE_IMAGE_DOT: ++ ive_hal_set_coeff_image_dot(&handle->hal_handle, &config->coeff_image_dot); ++ break; ++ ++ default: ++ break; ++ } ++ ++ ive_hal_clear_irq(&handle->hal_handle, IVE_HAL_IRQ_MASK_ALL); ++ ive_hal_set_irq_mask(&handle->hal_handle, IVE_HAL_IRQ_MASK_FRAME_DONE); ++ ++ ive_hal_start(&handle->hal_handle); ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_start_proc ++ * Start IVE process image ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * IVE_IOC_ERROR ++ */ ++IVE_IOC_ERROR ive_drv_process(ive_drv_handle *handle, ive_file_data *file_data) ++{ ++ IVE_IOC_ERROR ret = IVE_IOC_ERROR_NONE; ++#if 0 // multi instance test ++ static int pause_count = 0; ++#endif ++ ++ ret = drv_ive_check_config(&file_data->ioc_config); ++ if (ret != IVE_IOC_ERROR_NONE) { ++ return ret; ++ } ++ ++ file_data->state = IVE_FILE_STATE_IN_QUEUE; ++ drv_ive_add_request(handle, file_data); ++ ++ // do nothing if hw is not ready ++ if ((handle->dev_state != IVE_DRV_STATE_READY) ++#if 0 // multi instance test ++ || (pause_count++ < 10) ++#endif ++ ) ++ { ++ IVE_MSG(IVE_MSG_DBG, "HW is busy\n"); ++ return IVE_IOC_ERROR_NONE; ++ } ++ ++ file_data = drv_ive_get_request(handle); ++ if (file_data == NULL) { ++ IVE_MSG(IVE_MSG_DBG, "no more request in queue\n"); ++ return IVE_IOC_ERROR_MEMROY_FAILURE; ++ } ++ ++ file_data->state = IVE_FILE_STATE_PROCESSING; ++ handle->dev_state = IVE_DRV_STATE_PROCESSING; ++ ++ IVE_MSG(IVE_MSG_DBG, "process: %p ; %p ; %p\n", file_data->ioc_config.input.address[0], file_data->ioc_config.input.address[1], file_data->ioc_config.input.address[2]); ++ ++ ive_drv_start(handle, &file_data->ioc_config); ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_post_process ++ * Post process after IVE HW done ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * IVE_IOC_ERROR ++ */ ++ive_file_data* ive_drv_post_process(ive_drv_handle *handle) ++{ ++ ive_file_data *previous_file_data, *next_file_data; ++ ++ previous_file_data = drv_ive_extract_request(handle); ++ next_file_data = drv_ive_get_request(handle); ++ ++ if (previous_file_data != NULL) { ++ previous_file_data->state = IVE_FILE_STATE_DONE; ++ } ++ ++ if (next_file_data == NULL) { ++ IVE_MSG(IVE_MSG_DBG, "no more request in queue\n"); ++ handle->dev_state = IVE_DRV_STATE_READY; ++ } else { ++ IVE_MSG(IVE_MSG_DBG, "process: 0x%p, 0x%p, 0x%p\n", next_file_data->ioc_config.input.address[0], next_file_data->ioc_config.input.address[1], next_file_data->ioc_config.output.address[2]); ++ next_file_data->state = IVE_FILE_STATE_PROCESSING; ++ ive_drv_start(handle, &next_file_data->ioc_config); ++ } ++ ++ return previous_file_data; ++} +diff --git a/drivers/sstar/ive/drv_ive.h b/drivers/sstar/ive/drv_ive.h +new file mode 100755 +index 000000000000..f7839d7e2430 +--- /dev/null ++++ b/drivers/sstar/ive/drv_ive.h +@@ -0,0 +1,33 @@ ++/* ++* drv_ive.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _IVE_DRV_H_ ++#define _IVE_DRV_H_ ++ ++#include ++#include "mdrv_ive.h" ++#include "hal_ive.h" ++#include "mdrv_ive_io_st.h" ++ ++IVE_DRV_STATE ive_drv_isr_handler(int irq, ive_drv_handle *handle); ++ ++int ive_drv_init(ive_drv_handle *handle, struct platform_device *pdev, phys_addr_t base_addr0, phys_addr_t base_addr1); ++void ive_drv_release(ive_drv_handle *handle); ++IVE_IOC_ERROR ive_drv_process(ive_drv_handle *handle, ive_file_data *file_data); ++ive_file_data* ive_drv_post_process(ive_drv_handle *handle); ++ ++#endif +diff --git a/drivers/sstar/ive/hal_clk.c b/drivers/sstar/ive/hal_clk.c +new file mode 100755 +index 000000000000..4510dc3475ce +--- /dev/null ++++ b/drivers/sstar/ive/hal_clk.c +@@ -0,0 +1,40 @@ ++#include "hal_clk.h" ++#include "hal_debug.h" ++ ++#define RIU_BASE_ADDR (0x1F000000) ++#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR)) ++ ++#define BANK_CLK_GEN (BANK_CAL(0x100A)) ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++ ++/******************************************************************************************************************* ++ * clk_hal_init ++ * init device clock ++ * ++ * Parameters: ++ * RIU_BASE_ADDR: clock base address ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++////CEVA PLL: 600MHz setting ++int ive_clk_hal_init(void) ++{ ++ u16 value; ++ ++ value = REGR(BANK_CLK_GEN, 0x52); ++ value &= ~0xF8; ++ value |= 0x80; //320 MHz ++ ++ REGW(BANK_CLK_GEN, 0x52, value); ++ ++ return 0; ++} +diff --git a/drivers/sstar/ive/hal_clk.h b/drivers/sstar/ive/hal_clk.h +new file mode 100755 +index 000000000000..52b1457aa6a6 +--- /dev/null ++++ b/drivers/sstar/ive/hal_clk.h +@@ -0,0 +1,8 @@ ++#ifndef HAL_CLK_H ++#define HAL_CLK_H ++ ++#include "ms_platform.h" ++#include ++int ive_clk_hal_init(void); ++ ++#endif +diff --git a/drivers/sstar/ive/hal_debug.h b/drivers/sstar/ive/hal_debug.h +new file mode 100755 +index 000000000000..5fcbd47df134 +--- /dev/null ++++ b/drivers/sstar/ive/hal_debug.h +@@ -0,0 +1,38 @@ ++#ifndef __HAL_DEBUG_H__ ++#define __HAL_DEBUG_H__ ++ ++#include ++ ++// Defines debug message levels of HAL_MSG ++#define HAL_MSG_ERR 3 ++#define HAL_MSG_WRN 4 ++#define HAL_MSG_DBG 5 ++ ++#define HAL_MSG_LEVL HAL_MSG_WRN ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#define HAL_MSG_ENABLE // enable/disable message ++#define HAL_MSG_FUNC_ENABLE // enable/disable function name dump ++ ++#if defined(HAL_MSG_ENABLE) ++ ++#define HAL_STRINGIFY(x) #x ++#define HAL_TOSTRING(x) HAL_STRINGIFY(x) ++ ++#if defined(HAL_MSG_FUNC_ENABLE) ++#define HAL_MSG_TITLE "[HAL, %s] " ++#define HAL_MSG_FUNC __func__ ++#else // NOT defined(HAL_MSG_FUNC_ENABLE) ++#define HAL_MSG_TITLE "[HAL] %s" ++#define HAL_MSG_FUNC "" ++#endif // NOT defined(HAL_MSG_FUNC_ENABLE) ++ ++#define HAL_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= HAL_MSG_LEVL) { \ ++ printk(KERN_SOH HAL_TOSTRING(dbglv) HAL_MSG_TITLE _fmt, HAL_MSG_FUNC, ## _args); \ ++ } while(0) ++#else // NOT defined(HAL_MSG_ENABLE) ++#define HAL_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(HAL_MSG_ENABLE) ++ ++#endif // __HAL_DEBUG_H__ +diff --git a/drivers/sstar/ive/hal_ive.c b/drivers/sstar/ive/hal_ive.c +new file mode 100755 +index 000000000000..c22bf1a340b6 +--- /dev/null ++++ b/drivers/sstar/ive/hal_ive.c +@@ -0,0 +1,1111 @@ ++/* ++* hal_ive.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mdrv_ive.h" ++#include "hal_ive.h" ++#include "hal_ive_simulate.h" ++#include "ms_platform.h" ++ ++#define HAL_MIU1_BASE 0x80000000 ++ ++#define ADDR_LOW(addr) (((u32)(addr))&0x0000FFFF) ++#define ADDR_HIGH(addr) ((((u32)(addr))&0xFFFF0000)>>16) ++ ++#if 1 ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{IVE_MSG(IVE_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++#define REMOVE_MIU1_OFFSET(input_addr) ((u64)input_addr -0x80000000) ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// IRQ API // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * ive_hal_init ++ * init IVE HAL layer ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * base_addr0: base address 0 ++ * base_addr1: base address 1 ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_init(ive_hal_handle *handle, phys_addr_t base_addr0, phys_addr_t base_addr1) ++{ ++ memset(handle, 0, sizeof(ive_hal_handle)); ++ handle->base_addr0 = base_addr0; ++ handle->base_addr1 = base_addr1; ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_irq_mask ++ * Set interrupt trigger mask ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwize mask, defined in IveHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_irq_mask(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask) ++{ ++ handle->reg_bank0.irq_mask = ~mask; ++ REGW(handle->base_addr0, 0x10, handle->reg_bank0.reg10); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_clear_irq ++ * Clear triggered interrupt ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwize mask, defined in IveHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_clear_irq(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask) ++{ ++ handle->reg_bank0.woc_irq_clr = mask; ++ REGW(handle->base_addr0, 0x15, handle->reg_bank0.reg15); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_get_irq_check ++ * Check current IRQ status ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwise mask to be checked ++ * ++ * Return: ++ * Checked result, bitwise ++ */ ++IVE_HAL_IRQ_MASK ive_hal_get_irq_check(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask) ++{ ++#if !defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = REGR(handle->base_addr0, 0x13); ++#else // defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = IVE_HAL_IRQ_MASK_FRAME_DONE; ++#endif // defined(IVE_SW_SIMULATE) ++ ++ return handle->reg_bank0.irq_final_status & mask; ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_get_irq ++ * Get current interrupt trigger status ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwize mask, defined in IveHalIrqEvent_e ++ * ++ * Return: ++ * Bitwize status ++ */ ++u16 ive_hal_get_irq(ive_hal_handle *handle) ++{ ++#if !defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = REGR(handle->base_addr0, 0x13); ++#else // defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = IVE_HAL_IRQ_MASK_FRAME_DONE; ++#endif // defined(IVE_SW_SIMULATE) ++ ++ return handle->reg_bank0.irq_final_status; ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_operation ++ * Set operation of IVE HW ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * op_type: operation type ++ * op_mode: operation mode ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_operation(ive_hal_handle *handle, IVE_IOC_OP_TYPE op_type) ++{ ++ handle->reg_bank1.op_type = op_type; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_miu_set ++ * Set miu value ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_miu_set(ive_hal_handle *handle, int miu_state) ++{ ++ handle->reg_bank0.miu_sel = miu_state; ++ ++ REGW(handle->base_addr0, 0x03, handle->reg_bank0.reg03); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_images ++ * Set input & output image ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * input: input image ++ * output: output image ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_images(ive_hal_handle *handle, ive_ioc_image *input, ive_ioc_image *output) ++{ ++ int miu_value; ++ u64 input_addr0, input_addr1, input_addr2, output_addr0, output_addr1, output_addr2; ++ ++ IVE_MSG(IVE_MSG_DBG, "Ori -input : address[0] = 0x%p\n",(unsigned char*)input->address[0]); ++ IVE_MSG(IVE_MSG_DBG, "Ori -input : address[1] = 0x%p\n",(unsigned char*)input->address[1]); ++ IVE_MSG(IVE_MSG_DBG, "Ori -input : address[2] = 0x%p\n",(unsigned char*)input->address[2]); ++ ++#if defined(USE_MIU_DIRECT) ++ input_addr0 = (uintptr_t)(input->address[0]); ++ input_addr1 = (uintptr_t)(input->address[1]); ++ input_addr2 = (uintptr_t)(input->address[2]); ++ output_addr0 = (uintptr_t)(output->address[0]); ++ output_addr1 = (uintptr_t)(output->address[1]); ++ output_addr2 = (uintptr_t)(output->address[2]); ++#else ++ input_addr0 = Chip_Phys_to_MIU((uintptr_t)input->address[0]); ++ input_addr1 = Chip_Phys_to_MIU((uintptr_t)input->address[1]); ++ input_addr2 = Chip_Phys_to_MIU((uintptr_t)input->address[2]); ++ output_addr0 = Chip_Phys_to_MIU((uintptr_t)output->address[0]); ++ output_addr1 = Chip_Phys_to_MIU((uintptr_t)output->address[1]); ++ output_addr2 = Chip_Phys_to_MIU((uintptr_t)output->address[2]); ++#endif ++ ++ //Check address and switch MIU ++ if( (input_addr0 >= HAL_MIU1_BASE) || (input_addr1 >= HAL_MIU1_BASE) || (input_addr2 >= HAL_MIU1_BASE) ) ++ { ++ input_addr0 = REMOVE_MIU1_OFFSET(input_addr0); ++ input_addr1 = REMOVE_MIU1_OFFSET(input_addr1); ++ input_addr2 = REMOVE_MIU1_OFFSET(input_addr2); ++ output_addr0 = REMOVE_MIU1_OFFSET(output_addr0); ++ output_addr1 = REMOVE_MIU1_OFFSET(output_addr1); ++ output_addr2 = REMOVE_MIU1_OFFSET(output_addr2); ++ ++ miu_value = 1; ++ ive_hal_miu_set(handle, miu_value); ++ } ++ else ++ { ++ miu_value = 0; ++ ive_hal_miu_set(handle, miu_value); ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "Final - input_addr0 = %lld\n", input_addr0); ++ IVE_MSG(IVE_MSG_DBG, "Final - input_addr1 = %lld\n", input_addr1); ++ IVE_MSG(IVE_MSG_DBG, "Final - input_addr2 = %lld\n", input_addr2); ++ IVE_MSG(IVE_MSG_DBG, "Final - output_addr0 = %lld\n", output_addr0); ++ IVE_MSG(IVE_MSG_DBG, "Final - output_addr1 = %lld\n", output_addr1); ++ IVE_MSG(IVE_MSG_DBG, "Final - output_addr2 = %lld\n", output_addr2); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x03, REGR(handle->base_addr0, 0x03)); //MIU Register ++ ++ handle->reg_bank1.infmt = input->format; ++ handle->reg_bank1.outfmt = output->format; ++ ++ handle->reg_bank1.frame_width = input->width -1; ++ handle->reg_bank1.frame_height = input->height -1; ++ ++ handle->reg_bank1.src1_addr_low = ADDR_LOW( input_addr0); ++ handle->reg_bank1.src1_addr_high = ADDR_HIGH(input_addr0); ++ handle->reg_bank1.src2_addr_low = ADDR_LOW( input_addr1); ++ handle->reg_bank1.src2_addr_high = ADDR_HIGH(input_addr1); ++ handle->reg_bank1.src3_addr_low = ADDR_LOW( input_addr2); ++ handle->reg_bank1.src3_addr_high = ADDR_HIGH(input_addr2); ++ handle->reg_bank1.src1_stride = input->stride[0] -1; ++ handle->reg_bank1.src2_stride = input->stride[1] -1; ++ handle->reg_bank1.src3_stride = input->stride[2] -1; ++ ++ handle->reg_bank1.dst1_addr_low = ADDR_LOW( output_addr0); ++ handle->reg_bank1.dst1_addr_high = ADDR_HIGH(output_addr0); ++ handle->reg_bank1.dst2_addr_low = ADDR_LOW( output_addr1); ++ handle->reg_bank1.dst2_addr_high = ADDR_HIGH(output_addr1); ++ handle->reg_bank1.dst3_addr_low = ADDR_LOW( output_addr2); ++ handle->reg_bank1.dst3_addr_high = ADDR_HIGH(output_addr2); ++ handle->reg_bank1.dst1_stride = output->stride[0] -1; ++ handle->reg_bank1.dst2_stride = output->stride[1] -1; ++ handle->reg_bank1.dst3_stride = output->stride[2] -1; ++ ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x06, handle->reg_bank1.reg06); ++ REGW(handle->base_addr1, 0x07, handle->reg_bank1.reg07); ++ REGW(handle->base_addr1, 0x08, handle->reg_bank1.reg08); ++ REGW(handle->base_addr1, 0x09, handle->reg_bank1.reg09); ++ REGW(handle->base_addr1, 0x0A, handle->reg_bank1.reg0A); ++ REGW(handle->base_addr1, 0x0B, handle->reg_bank1.reg0B); ++ REGW(handle->base_addr1, 0x0C, handle->reg_bank1.reg0C); ++ REGW(handle->base_addr1, 0x0D, handle->reg_bank1.reg0D); ++ REGW(handle->base_addr1, 0x0E, handle->reg_bank1.reg0E); ++ REGW(handle->base_addr1, 0x0F, handle->reg_bank1.reg0F); ++ REGW(handle->base_addr1, 0x10, handle->reg_bank1.reg10); ++ REGW(handle->base_addr1, 0x11, handle->reg_bank1.reg11); ++ REGW(handle->base_addr1, 0x12, handle->reg_bank1.reg12); ++ REGW(handle->base_addr1, 0x13, handle->reg_bank1.reg13); ++ REGW(handle->base_addr1, 0x14, handle->reg_bank1.reg14); ++ REGW(handle->base_addr1, 0x15, handle->reg_bank1.reg15); ++ REGW(handle->base_addr1, 0x16, handle->reg_bank1.reg16); ++ REGW(handle->base_addr1, 0x17, handle->reg_bank1.reg17); ++ REGW(handle->base_addr1, 0x18, handle->reg_bank1.reg18); ++ REGW(handle->base_addr1, 0x19, handle->reg_bank1.reg19); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_mask ++ * Set mask coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: mask coefficient ++ * ++ * Return: ++ * none ++ */ ++static void ive_hal_set_coeff_mask(ive_hal_handle *handle, u8 *mask, u8 shift) ++{ ++ handle->reg_bank1.mask0 = mask[0]; ++ handle->reg_bank1.mask1 = mask[1]; ++ handle->reg_bank1.mask2 = mask[2]; ++ handle->reg_bank1.mask3 = mask[3]; ++ handle->reg_bank1.mask4 = mask[4]; ++ handle->reg_bank1.mask5 = mask[5]; ++ handle->reg_bank1.mask6 = mask[6]; ++ handle->reg_bank1.mask7 = mask[7]; ++ handle->reg_bank1.mask8 = mask[8]; ++ handle->reg_bank1.mask9 = mask[9]; ++ handle->reg_bank1.mask10 = mask[10]; ++ handle->reg_bank1.mask11 = mask[11]; ++ handle->reg_bank1.mask12 = mask[12]; ++ handle->reg_bank1.mask13 = mask[13]; ++ handle->reg_bank1.mask14 = mask[14]; ++ handle->reg_bank1.mask15 = mask[15]; ++ handle->reg_bank1.mask16 = mask[16]; ++ handle->reg_bank1.mask17 = mask[17]; ++ handle->reg_bank1.mask18 = mask[18]; ++ handle->reg_bank1.mask19 = mask[19]; ++ handle->reg_bank1.mask20 = mask[20]; ++ handle->reg_bank1.mask21 = mask[21]; ++ handle->reg_bank1.mask22 = mask[22]; ++ handle->reg_bank1.mask23 = mask[23]; ++ handle->reg_bank1.mask24 = mask[24]; ++ handle->reg_bank1.shift = shift; ++ ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x1C, handle->reg_bank1.reg1C); ++ REGW(handle->base_addr1, 0x1D, handle->reg_bank1.reg1D); ++ REGW(handle->base_addr1, 0x1E, handle->reg_bank1.reg1E); ++ REGW(handle->base_addr1, 0x1F, handle->reg_bank1.reg1F); ++ REGW(handle->base_addr1, 0x20, handle->reg_bank1.reg20); ++ REGW(handle->base_addr1, 0x21, handle->reg_bank1.reg21); ++ REGW(handle->base_addr1, 0x22, handle->reg_bank1.reg22); ++ REGW(handle->base_addr1, 0x23, handle->reg_bank1.reg23); ++ REGW(handle->base_addr1, 0x24, handle->reg_bank1.reg24); ++ REGW(handle->base_addr1, 0x25, handle->reg_bank1.reg25); ++ REGW(handle->base_addr1, 0x26, handle->reg_bank1.reg26); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_filter ++ * Set filter coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_filter(ive_hal_handle *handle, ive_ioc_coeff_filter *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, coeff->shift); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_csc ++ * Set CSC coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: CSC coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_csc(ive_hal_handle *handle, ive_ioc_coeff_csc *coeff) ++{ ++ handle->reg_bank1.csc_coeff0 = coeff->coeff[0]; ++ handle->reg_bank1.csc_coeff1 = coeff->coeff[1]; ++ handle->reg_bank1.csc_coeff2 = coeff->coeff[2]; ++ handle->reg_bank1.csc_coeff3 = coeff->coeff[3]; ++ handle->reg_bank1.csc_coeff4 = coeff->coeff[4]; ++ handle->reg_bank1.csc_coeff5 = coeff->coeff[5]; ++ handle->reg_bank1.csc_coeff6 = coeff->coeff[6]; ++ handle->reg_bank1.csc_coeff7 = coeff->coeff[7]; ++ handle->reg_bank1.csc_coeff8 = coeff->coeff[8]; ++ ++ handle->reg_bank1.csc_offset0 = coeff->offset[0]; ++ handle->reg_bank1.csc_offset1 = coeff->offset[1]; ++ handle->reg_bank1.csc_offset2 = coeff->offset[2]; ++ ++ handle->reg_bank1.csc_clamp0_low = coeff->clamp[0].clamp_low; ++ handle->reg_bank1.csc_clamp0_high = coeff->clamp[0].clamp_high; ++ handle->reg_bank1.csc_clamp1_low = coeff->clamp[1].clamp_low; ++ handle->reg_bank1.csc_clamp1_high = coeff->clamp[1].clamp_high; ++ handle->reg_bank1.csc_clamp2_low = coeff->clamp[2].clamp_low; ++ handle->reg_bank1.csc_clamp2_high = coeff->clamp[2].clamp_high; ++ ++ REGW(handle->base_addr1, 0x30, handle->reg_bank1.reg30); ++ REGW(handle->base_addr1, 0x31, handle->reg_bank1.reg31); ++ REGW(handle->base_addr1, 0x32, handle->reg_bank1.reg32); ++ REGW(handle->base_addr1, 0x33, handle->reg_bank1.reg33); ++ REGW(handle->base_addr1, 0x34, handle->reg_bank1.reg34); ++ REGW(handle->base_addr1, 0x35, handle->reg_bank1.reg35); ++ REGW(handle->base_addr1, 0x36, handle->reg_bank1.reg36); ++ REGW(handle->base_addr1, 0x37, handle->reg_bank1.reg37); ++ REGW(handle->base_addr1, 0x38, handle->reg_bank1.reg38); ++ REGW(handle->base_addr1, 0x39, handle->reg_bank1.reg39); ++ REGW(handle->base_addr1, 0x3A, handle->reg_bank1.reg3A); ++ REGW(handle->base_addr1, 0x3B, handle->reg_bank1.reg3B); ++ REGW(handle->base_addr1, 0x3C, handle->reg_bank1.reg3C); ++ REGW(handle->base_addr1, 0x3D, handle->reg_bank1.reg3D); ++ REGW(handle->base_addr1, 0x3E, handle->reg_bank1.reg3E); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_sobel ++ * Set sobel coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_sobel(ive_hal_handle *handle, ive_ioc_coeff_sobel *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++ ++ handle->reg_bank1.outfmt = coeff->mode; ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_mag_and_ang ++ * Set mag and ang coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_mag_and_ang(ive_hal_handle *handle, ive_ioc_coeff_mag_and_ang *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++ ++ handle->reg_bank1.outfmt = coeff->mode; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh; ++ ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_ord_stat_filter ++ * Set order statistics filter coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_ord_stat_filter(ive_hal_handle *handle, ive_ioc_coeff_ord_stat_filter *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_bernsen ++ * Set bernsen coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_bernsen(ive_hal_handle *handle, ive_ioc_coeff_bernsen *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_dilate ++ * Set dilate coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_dilate(ive_hal_handle *handle, ive_ioc_coeff_dilate *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_erode ++ * Set erode coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_erode(ive_hal_handle *handle, ive_ioc_coeff_erode *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_thresh ++ * Set thresh coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_thresh(ive_hal_handle *handle, ive_ioc_coeff_thresh *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->mid; ++ handle->reg_bank1.mask2 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->low; ++ handle->reg_bank1.thresh_16bit_2 = coeff->high; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_thresh_s16 ++ * Set thresh s16 coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_thresh_s16(ive_hal_handle *handle, ive_ioc_coeff_thresh_s16 *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->mid; ++ handle->reg_bank1.mask2 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->low; ++ handle->reg_bank1.thresh_16bit_2 = coeff->high; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_thresh_u16 ++ * Set thresh u16 coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_thresh_u16(ive_hal_handle *handle, ive_ioc_coeff_thresh_u16 *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->mid; ++ handle->reg_bank1.mask2 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->low; ++ handle->reg_bank1.thresh_16bit_2 = coeff->high; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_add ++ * Set add coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_add(ive_hal_handle *handle, ive_ioc_coeff_add *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.add_weight_x = coeff->weight_x; ++ handle->reg_bank1.add_weight_y = coeff->weight_y; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x2B, handle->reg_bank1.reg2B); ++ REGW(handle->base_addr1, 0x2C, handle->reg_bank1.reg2C); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_sub ++ * Set sub coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_sub(ive_hal_handle *handle, ive_ioc_coeff_sub *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_16to8 ++ * Set 16 to 8 coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_16to8(ive_hal_handle *handle, ive_ioc_coeff_16to8 *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.fraction = (u16)(((u32)coeff->numerator << 16) / (u32)coeff->denominator); ++ handle->reg_bank1.mask0 = coeff->bias; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x2A, handle->reg_bank1.reg2A); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_map ++ * Set map coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_map(ive_hal_handle *handle, u64 map_addr) ++{ ++#if defined(USE_MIU_DIRECT) ++ u64 miu_addr = map_addr; ++#else ++ u64 miu_addr = Chip_Phys_to_MIU(map_addr); ++#endif ++ ++ //Check address ++ if( miu_addr >= HAL_MIU1_BASE ) ++ { ++ miu_addr = REMOVE_MIU1_OFFSET(miu_addr); ++ } ++ ++ handle->reg_bank1.src1_addr_low = ADDR_LOW( miu_addr); ++ handle->reg_bank1.src1_addr_high = ADDR_HIGH(miu_addr); ++ ++ REGW(handle->base_addr1, 0x08, handle->reg_bank1.reg08); ++ REGW(handle->base_addr1, 0x09, handle->reg_bank1.reg09); ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_integral ++ * Set integral coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_integral(ive_hal_handle *handle, ive_ioc_coeff_integral *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_sad ++ * Set SAD coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_sad(ive_hal_handle *handle, ive_ioc_coeff_sad *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->block_mode; ++ handle->reg_bank1.outfmt = coeff->out_mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_lbp ++ * Set LBP coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_ncc(ive_hal_handle *handle, u64 output_addr) ++{ ++#if defined(USE_MIU_DIRECT) ++ u64 miu_addr = output_addr; ++#else ++ u64 miu_addr = Chip_Phys_to_MIU(output_addr); ++#endif ++ ++ //Check address ++ if( miu_addr >= HAL_MIU1_BASE ) ++ { ++ miu_addr = REMOVE_MIU1_OFFSET(miu_addr); ++ } ++ ++ handle->reg_bank1.dst1_addr_low = ADDR_LOW( miu_addr); ++ handle->reg_bank1.dst1_addr_high = ADDR_HIGH(miu_addr); ++ // handle->reg_bank1.dst1_stride = handle->reg_bank1.src1_stride; ++ ++ REGW(handle->base_addr1, 0x0A, handle->reg_bank1.reg0A); ++ REGW(handle->base_addr1, 0x0B, handle->reg_bank1.reg0B); ++ // REGW(handle->base_addr1, 0x15, handle->reg_bank1.reg15); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_lbp ++ * Set LBP coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_lbp(ive_hal_handle *handle, ive_ioc_coeff_lbp *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.infmt = coeff->chlmode; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh-1; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_bat ++ * Set bat coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_bat(ive_hal_handle *handle, ive_ioc_coeff_bat *coeff) ++{ ++ handle->reg_bank1.thresh_16bit_1 = coeff->h_times; ++ handle->reg_bank1.thresh_16bit_2 = coeff->v_times; ++ ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_adp_thresh ++ * Set adaptive threshold coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_adp_thresh(ive_hal_handle *handle, ive_ioc_coeff_adp_thresh *coeff) ++{ ++ handle->reg_bank1.mask0 = coeff->u8HalfMaskx; ++ handle->reg_bank1.mask1 = coeff->u8HalfMasky; ++ handle->reg_bank1.shift = coeff->s8Offset; ++ handle->reg_bank1.thresh_16bit_1 = coeff->u8ValueThr; ++ handle->reg_bank1.add_weight_x = coeff->u8RateThr; ++ ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x26, handle->reg_bank1.reg26); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x2B, handle->reg_bank1.reg2B); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_matrix_transform ++ * Set matrix transform coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_matrix_transform(ive_hal_handle *handle, ive_ioc_coeff_matrix_transform *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->ctrl_mode; ++ ++ switch( coeff->chl_mode ) ++ { ++ case IVE_IOC_MODE_MATRIX_TRANSFORM_C1: ++ handle->reg_bank1.infmt = 13; ++ handle->reg_bank1.outfmt = 13; ++ handle->reg_bank1.mask0 = coeff->s16MatrixArray[0] & 0xFF; ++ handle->reg_bank1.mask1 = (coeff->s16MatrixArray[0] & 0xFF00) >> 8; ++ handle->reg_bank1.mask2 = 0; ++ handle->reg_bank1.mask3 = 0; ++ handle->reg_bank1.mask4 = 0; ++ handle->reg_bank1.mask5 = 0; ++ handle->reg_bank1.mask6 = 0; ++ handle->reg_bank1.mask7 = 0; ++ handle->reg_bank1.mask8 = 0; ++ handle->reg_bank1.mask9 = 0; ++ handle->reg_bank1.mask10 = 0; ++ handle->reg_bank1.mask11 = 0; ++ handle->reg_bank1.mask12 = 0; ++ handle->reg_bank1.mask13 = 0; ++ handle->reg_bank1.mask14 = 0; ++ handle->reg_bank1.mask15 = 0; ++ handle->reg_bank1.mask16 = 0; ++ handle->reg_bank1.mask17 = 0; ++ break; ++ ++ case IVE_IOC_MODE_MATRIX_TRANSFORM_C2: ++ handle->reg_bank1.infmt = 14; ++ handle->reg_bank1.outfmt = 14; ++ ++ handle->reg_bank1.mask0 = coeff->s16MatrixArray[0] & 0xFF; ++ handle->reg_bank1.mask1 = (coeff->s16MatrixArray[0] & 0xFF00) >> 8; ++ handle->reg_bank1.mask2 = coeff->s16MatrixArray[1] & 0xFF; ++ handle->reg_bank1.mask3 = (coeff->s16MatrixArray[1] & 0xFF00) >> 8; ++ handle->reg_bank1.mask4 = 0; ++ handle->reg_bank1.mask5 = 0; ++ handle->reg_bank1.mask6 = coeff->s16MatrixArray[2] & 0xFF; ++ handle->reg_bank1.mask7 = (coeff->s16MatrixArray[2] & 0xFF00) >> 8; ++ handle->reg_bank1.mask8 = coeff->s16MatrixArray[3] & 0xFF; ++ handle->reg_bank1.mask9 = (coeff->s16MatrixArray[3] & 0xFF00) >> 8; ++ handle->reg_bank1.mask10 = 0; ++ handle->reg_bank1.mask11 = 0; ++ handle->reg_bank1.mask12 = 0; ++ handle->reg_bank1.mask13 = 0; ++ handle->reg_bank1.mask14 = 0; ++ handle->reg_bank1.mask15 = 0; ++ handle->reg_bank1.mask16 = 0; ++ handle->reg_bank1.mask17 = 0; ++ break; ++ ++ case IVE_IOC_MODE_MATRIX_TRANSFORM_C3: ++ handle->reg_bank1.infmt = 15; ++ handle->reg_bank1.outfmt = 15; ++ ++ handle->reg_bank1.mask0 = coeff->s16MatrixArray[0] & 0xFF; ++ handle->reg_bank1.mask1 = (coeff->s16MatrixArray[0] & 0xFF00) >> 8; ++ handle->reg_bank1.mask2 = coeff->s16MatrixArray[1] & 0xFF; ++ handle->reg_bank1.mask3 = (coeff->s16MatrixArray[1] & 0xFF00) >> 8; ++ handle->reg_bank1.mask4 = coeff->s16MatrixArray[2] & 0xFF; ++ handle->reg_bank1.mask5 = (coeff->s16MatrixArray[2] & 0xFF00) >> 8; ++ handle->reg_bank1.mask6 = coeff->s16MatrixArray[3] & 0xFF; ++ handle->reg_bank1.mask7 = (coeff->s16MatrixArray[3] & 0xFF00) >> 8; ++ handle->reg_bank1.mask8 = coeff->s16MatrixArray[4] & 0xFF; ++ handle->reg_bank1.mask9 = (coeff->s16MatrixArray[4] & 0xFF00) >> 8; ++ handle->reg_bank1.mask10 = coeff->s16MatrixArray[5] & 0xFF; ++ handle->reg_bank1.mask11 = (coeff->s16MatrixArray[5] & 0xFF00) >> 8; ++ handle->reg_bank1.mask12 = coeff->s16MatrixArray[6] & 0xFF; ++ handle->reg_bank1.mask13 = (coeff->s16MatrixArray[6] & 0xFF00) >> 8; ++ handle->reg_bank1.mask14 = coeff->s16MatrixArray[7] & 0xFF; ++ handle->reg_bank1.mask15 = (coeff->s16MatrixArray[7] & 0xFF00) >> 8; ++ handle->reg_bank1.mask16 = coeff->s16MatrixArray[8] & 0xFF; ++ handle->reg_bank1.mask17 = (coeff->s16MatrixArray[8] & 0xFF00) >> 8; ++ break; ++ ++ default : ++ IVE_MSG(IVE_MSG_ERR, "Invalid input type of matrix transform!!\n"); ++ break; ++ } ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x1C, handle->reg_bank1.reg1C); ++ REGW(handle->base_addr1, 0x1D, handle->reg_bank1.reg1D); ++ REGW(handle->base_addr1, 0x1E, handle->reg_bank1.reg1E); ++ REGW(handle->base_addr1, 0x1F, handle->reg_bank1.reg1F); ++ REGW(handle->base_addr1, 0x20, handle->reg_bank1.reg20); ++ REGW(handle->base_addr1, 0x21, handle->reg_bank1.reg21); ++ REGW(handle->base_addr1, 0x22, handle->reg_bank1.reg22); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_image_dot ++ * Set image dot coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_image_dot(ive_hal_handle *handle, ive_ioc_coeff_image_dot *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.infmt = 14; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_start ++ * start IVE HW engine to process images ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * ++ * Return: ++ * none ++ */ ++ void ive_hal_start(ive_hal_handle *handle) ++{ ++#if !defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.sw_fire = 1; ++ ++ REGW(handle->base_addr0, 0x00, handle->reg_bank0.reg00); ++ ++ handle->reg_bank0.sw_fire = 0; // write one clear ++#else // !defined(IVE_SW_SIMULATE) ++ ive_hal_run_simulate(handle); ++#endif // defined(IVE_SW_SIMULATE) ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_sw_reset ++ * reset IVE HW engine ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_sw_reset(ive_hal_handle *handle) ++{ ++ handle->reg_bank0.sw_rst = 1; ++ ++ REGW(handle->base_addr0, 0x02, handle->reg_bank0.reg02); ++ ++ handle->reg_bank0.sw_rst = 0; // write one clear ++ ++ REGW(handle->base_addr0, 0x02, handle->reg_bank0.reg02); ++ ++ memset(&handle->reg_bank0, 0, sizeof(handle->reg_bank0)); ++ memset(&handle->reg_bank1, 0, sizeof(handle->reg_bank1)); ++} ++ ++void ive_hal_reg_dump(ive_hal_handle *handle) ++{ ++ IVE_MSG(IVE_MSG_DBG, "clock reg = 0x%04x\n", REGR(0x1F207000, 0x6A)); ++ ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x00, REGR(handle->base_addr0, 0x00)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x01, REGR(handle->base_addr0, 0x01)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x02, REGR(handle->base_addr0, 0x02)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x03, REGR(handle->base_addr0, 0x03)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x10, REGR(handle->base_addr0, 0x10)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x11, REGR(handle->base_addr0, 0x11)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x12, REGR(handle->base_addr0, 0x12)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x13, REGR(handle->base_addr0, 0x13)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x14, REGR(handle->base_addr0, 0x14)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x15, REGR(handle->base_addr0, 0x15)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x16, REGR(handle->base_addr0, 0x16)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x17, REGR(handle->base_addr0, 0x17)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x18, REGR(handle->base_addr0, 0x18)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x20, REGR(handle->base_addr0, 0x20)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x21, REGR(handle->base_addr0, 0x21)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x22, REGR(handle->base_addr0, 0x22)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x23, REGR(handle->base_addr0, 0x23)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x24, REGR(handle->base_addr0, 0x24)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x25, REGR(handle->base_addr0, 0x25)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x30, REGR(handle->base_addr0, 0x30)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x31, REGR(handle->base_addr0, 0x31)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x40, REGR(handle->base_addr0, 0x40)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x41, REGR(handle->base_addr0, 0x41)); ++ ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x00, REGR(handle->base_addr1, 0x00)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x01, REGR(handle->base_addr1, 0x01)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x02, REGR(handle->base_addr1, 0x02)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x03, REGR(handle->base_addr1, 0x03)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x04, REGR(handle->base_addr1, 0x04)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x05, REGR(handle->base_addr1, 0x05)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x06, REGR(handle->base_addr1, 0x06)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x07, REGR(handle->base_addr1, 0x07)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x08, REGR(handle->base_addr1, 0x08)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x09, REGR(handle->base_addr1, 0x09)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0A, REGR(handle->base_addr1, 0x0A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0B, REGR(handle->base_addr1, 0x0B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0C, REGR(handle->base_addr1, 0x0C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0D, REGR(handle->base_addr1, 0x0D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0E, REGR(handle->base_addr1, 0x0E)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0F, REGR(handle->base_addr1, 0x0F)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x10, REGR(handle->base_addr1, 0x10)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x11, REGR(handle->base_addr1, 0x11)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x12, REGR(handle->base_addr1, 0x12)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x13, REGR(handle->base_addr1, 0x13)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x14, REGR(handle->base_addr1, 0x14)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x15, REGR(handle->base_addr1, 0x15)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x16, REGR(handle->base_addr1, 0x16)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x17, REGR(handle->base_addr1, 0x17)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x18, REGR(handle->base_addr1, 0x18)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x19, REGR(handle->base_addr1, 0x19)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1A, REGR(handle->base_addr1, 0x1A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1B, REGR(handle->base_addr1, 0x1B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1C, REGR(handle->base_addr1, 0x1C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1D, REGR(handle->base_addr1, 0x1D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1E, REGR(handle->base_addr1, 0x1E)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1F, REGR(handle->base_addr1, 0x1F)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x20, REGR(handle->base_addr1, 0x20)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x21, REGR(handle->base_addr1, 0x21)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x22, REGR(handle->base_addr1, 0x22)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x23, REGR(handle->base_addr1, 0x23)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x24, REGR(handle->base_addr1, 0x24)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x25, REGR(handle->base_addr1, 0x25)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x26, REGR(handle->base_addr1, 0x26)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x27, REGR(handle->base_addr1, 0x27)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x28, REGR(handle->base_addr1, 0x28)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x29, REGR(handle->base_addr1, 0x29)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2A, REGR(handle->base_addr1, 0x2A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2B, REGR(handle->base_addr1, 0x2B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2C, REGR(handle->base_addr1, 0x2C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2D, REGR(handle->base_addr1, 0x2D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2E, REGR(handle->base_addr1, 0x2E)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2F, REGR(handle->base_addr1, 0x2F)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x30, REGR(handle->base_addr1, 0x30)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x31, REGR(handle->base_addr1, 0x31)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x32, REGR(handle->base_addr1, 0x32)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x33, REGR(handle->base_addr1, 0x33)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x34, REGR(handle->base_addr1, 0x34)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x35, REGR(handle->base_addr1, 0x35)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x36, REGR(handle->base_addr1, 0x36)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x37, REGR(handle->base_addr1, 0x37)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x38, REGR(handle->base_addr1, 0x38)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x39, REGR(handle->base_addr1, 0x39)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3A, REGR(handle->base_addr1, 0x3A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3B, REGR(handle->base_addr1, 0x3B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3C, REGR(handle->base_addr1, 0x3C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3D, REGR(handle->base_addr1, 0x3D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3E, REGR(handle->base_addr1, 0x3E)); ++} +diff --git a/drivers/sstar/ive/hal_ive.h b/drivers/sstar/ive/hal_ive.h +new file mode 100755 +index 000000000000..18b1458f3200 +--- /dev/null ++++ b/drivers/sstar/ive/hal_ive.h +@@ -0,0 +1,84 @@ ++/* ++* hal_ive.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_IVE_H_ ++#define _HAL_IVE_H_ ++ ++#include ++#include "hal_ive_reg.h" ++#include "mdrv_ive_io_st.h" ++ ++typedef enum ++{ ++ IVE_HAL_IRQ_MASK_FRAME_DONE = 0x00000001, // bit 0, frame done ++ IVE_HAL_IRQ_MASK_Y_CNT_HIT_0 = 0x00000002, // bit 1, Y line counter 0 hit ++ IVE_HAL_IRQ_MASK_Y_CNT_HIT_1 = 0x00000004, // bit 2, Y line counter 1 hit ++ IVE_HAL_IRQ_MASK_Y_CNT_HIT_2 = 0x00000008, // bit 3, Y line counter 2 hit ++ IVE_HAL_IRQ_MASK_ALL = 0xF000000F // ALL bits ++} IVE_HAL_IRQ_MASK; ++ ++typedef struct ++{ ++ phys_addr_t base_addr0; ++ ive_hal_reg_bank0 reg_bank0; ++ ++ phys_addr_t base_addr1; ++ ive_hal_reg_bank1 reg_bank1; ++} ive_hal_handle; ++ ++void ive_hal_init(ive_hal_handle *handle, phys_addr_t base_addr0, phys_addr_t base_addr1); ++ ++void ive_hal_set_irq_mask(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask); ++void ive_hal_clear_irq(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask); ++IVE_HAL_IRQ_MASK ive_hal_get_irq_check(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask); ++u16 ive_hal_get_irq(ive_hal_handle *handle); ++ ++void ive_hal_set_operation(ive_hal_handle *handle, IVE_IOC_OP_TYPE op_type); ++void ive_hal_set_images(ive_hal_handle *handle, ive_ioc_image *input, ive_ioc_image *output); ++ ++void ive_hal_set_coeff_filter(ive_hal_handle *handle, ive_ioc_coeff_filter *coeff); ++void ive_hal_set_coeff_csc(ive_hal_handle *handle, ive_ioc_coeff_csc *coeff); ++void ive_hal_set_coeff_sobel(ive_hal_handle *handle, ive_ioc_coeff_sobel *coeff); ++void ive_hal_set_coeff_mag_and_ang(ive_hal_handle *handle, ive_ioc_coeff_mag_and_ang *coeff); ++void ive_hal_set_coeff_ord_stat_filter(ive_hal_handle *handle, ive_ioc_coeff_ord_stat_filter *coeff); ++void ive_hal_set_coeff_bernsen(ive_hal_handle *handle, ive_ioc_coeff_bernsen *coeff); ++void ive_hal_set_coeff_dilate(ive_hal_handle *handle, ive_ioc_coeff_dilate *coeff); ++void ive_hal_set_coeff_erode(ive_hal_handle *handle, ive_ioc_coeff_erode *coeff); ++void ive_hal_set_coeff_thresh(ive_hal_handle *handle, ive_ioc_coeff_thresh *coeff); ++void ive_hal_set_coeff_thresh_s16(ive_hal_handle *handle, ive_ioc_coeff_thresh_s16 *coeff); ++void ive_hal_set_coeff_thresh_u16(ive_hal_handle *handle, ive_ioc_coeff_thresh_u16 *coeff); ++void ive_hal_set_coeff_add(ive_hal_handle *handle, ive_ioc_coeff_add *coeff); ++void ive_hal_set_coeff_sub(ive_hal_handle *handle, ive_ioc_coeff_sub *coeff); ++void ive_hal_set_coeff_16to8(ive_hal_handle *handle, ive_ioc_coeff_16to8 *coeff); ++void ive_hal_set_coeff_map(ive_hal_handle *handle, u64 map_addr); ++void ive_hal_set_coeff_integral(ive_hal_handle *handle, ive_ioc_coeff_integral *coeff); ++void ive_hal_set_coeff_sad(ive_hal_handle *handle, ive_ioc_coeff_sad *coeff); ++void ive_hal_set_coeff_ncc(ive_hal_handle *handle, u64 output_addr); ++void ive_hal_set_coeff_lbp(ive_hal_handle *handle, ive_ioc_coeff_lbp *coeff); ++void ive_hal_set_coeff_bat(ive_hal_handle *handle, ive_ioc_coeff_bat *coeff); ++void ive_hal_set_coeff_adp_thresh(ive_hal_handle *handle, ive_ioc_coeff_adp_thresh *coeff); ++void ive_hal_set_coeff_matrix_transform(ive_hal_handle *handle, ive_ioc_coeff_matrix_transform *coeff); ++void ive_hal_set_coeff_image_dot(ive_hal_handle *handle, ive_ioc_coeff_image_dot *coeff); ++ ++void ive_hal_start(ive_hal_handle *handle); ++void ive_hal_sw_reset(ive_hal_handle *handle); ++ ++void ive_hal_reg_dump(ive_hal_handle *handle); ++ ++void ive_hal_miu_set(ive_hal_handle *handle, int miu_state); ++ ++#endif // _HAL_IVE_H_ +diff --git a/drivers/sstar/ive/hal_ive_reg.h b/drivers/sstar/ive/hal_ive_reg.h +new file mode 100755 +index 000000000000..a5666caa889a +--- /dev/null ++++ b/drivers/sstar/ive/hal_ive_reg.h +@@ -0,0 +1,787 @@ ++/* ++* hal_ive_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_IVE_REG_H_ ++#define _HAL_IVE_REG_H_ ++ ++#include ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 sw_fire:1; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 opr_upd_mode:1; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 sw_rst:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 miu_sel:1; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_mask:8; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_force:8; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_raw_status:8; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_final_status:8; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_sel:8; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 woc_irq_clr:8; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 y_cnt_hit_set0:11; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 y_cnt_hit_set1:11; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 y_cnt_hit_set2:11; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_mask:8; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_force:8; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_raw_status:8; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_final_status:8; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_sel:1; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 woc_cmq_trig_clr:8; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 bist_fail_rd_low:16; ++ }; ++ u16 reg30; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 bist_fail_rd_high:16; ++ }; ++ u16 reg31; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cycle_count_low:16; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cycle_count_high:16; ++ }; ++ u16 reg41; ++ }; ++} ive_hal_reg_bank0; ++ ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 nxt_cmd_addr_low:16; // not used ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 nxt_cmd_addr_high:16; // not used ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 task_id:16; // not used ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 bpp:8; // not used ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 op_type:8; ++ u16 op_mode:8; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 infmt:8; ++ u16 outfmt:8; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 frame_width:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 frame_height:16; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src1_addr_low:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src1_addr_high:16; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst1_addr_low:16; ++ }; ++ u16 reg0A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst1_addr_high:16; ++ }; ++ u16 reg0B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src2_addr_low:16; ++ }; ++ u16 reg0C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src2_addr_high:16; ++ }; ++ u16 reg0D; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst2_addr_low:16; ++ }; ++ u16 reg0E; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst2_addr_high:16; ++ }; ++ u16 reg0F; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src3_addr_low:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src3_addr_high:16; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst3_addr_low:16; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst3_addr_high:16; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src1_stride:16; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst1_stride:16; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src2_stride:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst2_stride:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src3_stride:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst3_stride:16; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask0:8; ++ u16 mask1:8; ++ }; ++ u16 reg1A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask2:8; ++ u16 mask3:8; ++ }; ++ u16 reg1B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask4:8; ++ u16 mask5:8; ++ }; ++ u16 reg1C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask6:8; ++ u16 mask7:8; ++ }; ++ u16 reg1D; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask8:8; ++ u16 mask9:8; ++ }; ++ u16 reg1E; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask10:8; ++ u16 mask11:8; ++ }; ++ u16 reg1F; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask12:8; ++ u16 mask13:8; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask14:8; ++ u16 mask15:8; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask16:8; ++ u16 mask17:8; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask18:8; ++ u16 mask19:8; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask20:8; ++ u16 mask21:8; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask22:8; ++ u16 mask23:8; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask24:8; ++ u16 shift:8; ++ }; ++ u16 reg26; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 thresh_16bit_1:16; ++ }; ++ u16 reg28; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 thresh_16bit_2:16; ++ }; ++ u16 reg29; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 fraction:16; ++ }; ++ u16 reg2A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 add_weight_x:16; ++ }; ++ u16 reg2B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 add_weight_y:16; ++ }; ++ u16 reg2C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff0:12; ++ }; ++ u16 reg30; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff1:12; ++ }; ++ u16 reg31; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff2:12; ++ }; ++ u16 reg32; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff3:12; ++ }; ++ u16 reg33; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff4:12; ++ }; ++ u16 reg34; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff5:12; ++ }; ++ u16 reg35; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff6:12; ++ }; ++ u16 reg36; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff7:12; ++ }; ++ u16 reg37; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff8:12; ++ }; ++ u16 reg38; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_offset0:12; ++ }; ++ u16 reg39; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_offset1:12; ++ }; ++ u16 reg3A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_offset2:12; ++ }; ++ u16 reg3B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_clamp0_low:8; ++ u16 csc_clamp0_high:8; ++ }; ++ u16 reg3C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_clamp1_low:8; ++ u16 csc_clamp1_high:8; ++ }; ++ u16 reg3D; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_clamp2_low:8; ++ u16 csc_clamp2_high:8; ++ }; ++ u16 reg3E; ++ }; ++ ++} ive_hal_reg_bank1; ++ ++#endif // _HAL_IVE_REG_H_ +diff --git a/drivers/sstar/ive/hal_ive_simulate.c b/drivers/sstar/ive/hal_ive_simulate.c +new file mode 100755 +index 000000000000..7804cc09be50 +--- /dev/null ++++ b/drivers/sstar/ive/hal_ive_simulate.c +@@ -0,0 +1,181 @@ ++/* ++* hal_ive_simulate.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mdrv_ive.h" ++#include "hal_ive_simulate.h" ++ ++#include ++#include ++#include ++#include ++// #include ++ ++struct ive_simulation { ++ struct list_head list; ++ struct work_struct work_queue; ++ ive_dev_data *dev_data; ++}; ++ ++#if defined(IVE_SW_SIMULATE) ++ ++// We declare the function here because this API should not extern by default ++void mdrv_ive_drv_isr_post_proc(struct work_struct *wq); ++ ++// Static work queue data ++#define DATA_SIZE (10) ++static struct ive_simulation g_list_data[DATA_SIZE]; ++static LIST_HEAD(g_work_queue_list); ++ ++/******************************************************************************************************************* ++ * __get_work_queue_data ++ * Get a work queue data for simulation ++ * We need the paired API because work buffer can't free before work queue done ++ * Therefor a static linked list to prepared the work queue structure & relative data ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * work queue data ++ */ ++static struct ive_simulation* __get_work_queue_data(void) ++{ ++ int i; ++ ++ struct ive_simulation *list_data = NULL; ++ ++ // init g_work_queue_list ++ if (list_empty(&g_work_queue_list)) { ++ memset(g_list_data, 0, sizeof(g_list_data)); ++ IVE_MSG(IVE_MSG_DBG, "add work queue list\n"); ++ for (i=0; ilist, &g_work_queue_list); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_op_simulate ++ * A dummy simulation function. ++ * There is nothing to do because work queue is a kernel thread and has no way ++ * to get data from user space. ++ * ++ * Parameters: ++ * handle: hal handle ++ * ++ * Return: ++ * none ++ */ ++static void ive_hal_op_simulate(ive_hal_handle *handle) ++{ ++#define BLOCK_SIZE (64*1024) ++ ++ int i, length = handle->reg_bank1.frame_width * handle->reg_bank1.frame_height; ++ void *user_src0, *user_src1, *user_dst; ++ u16 weight_x, weight_y; ++ ++ weight_x = handle->reg_bank1.add_weight_x; ++ weight_y = handle->reg_bank1.add_weight_y; ++ ++ user_src0 = (void*)(handle->reg_bank1.src1_addr_high<<16 | handle->reg_bank1.src1_addr_low); ++ user_src1 = (void*)(handle->reg_bank1.src2_addr_high<<16 | handle->reg_bank1.src2_addr_low); ++ user_dst = (void*)(handle->reg_bank1.dst1_addr_high<<16 | handle->reg_bank1.dst1_addr_low); ++ ++ IVE_MSG(IVE_MSG_DBG, "0x%p, 0x%p, 0x%p (%d x %d)\n", user_src0, user_src1, user_dst, handle->reg_bank1.frame_width, handle->reg_bank1.frame_height); ++ ++ for (i=0; idev_data; ++ ++ ive_hal_op_simulate(&dev_data->drv_handle.hal_handle); ++ ++ ive_drv_isr_handler(0, &dev_data->drv_handle); ++ mdrv_ive_drv_isr_post_proc(&dev_data->work_queue); ++ ++ __return_work_queue_data(simulation); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_run_simulate ++ * A simulation for HW start. ++ * ++ * Parameters: ++ * handle: hal handle ++ * ++ * Return: ++ * none ++ */ ++ void ive_hal_run_simulate(ive_hal_handle *handle) ++{ ++ ive_drv_handle *drv_handle = container_of(handle, ive_drv_handle, hal_handle); ++ ive_dev_data *dev_data = container_of(drv_handle, ive_dev_data, drv_handle); ++ // struct ive_simulation *simulation = kzalloc(sizeof(struct ive_simulation), GFP_KERNEL); ++ struct ive_simulation *simulation = __get_work_queue_data(); ++ ++ IVE_MSG(IVE_MSG_DBG, "run simulation, dev_data = 0x%p\n", dev_data); ++ ++ simulation->dev_data = dev_data; ++ INIT_WORK(&simulation->work_queue, mdrv_ive_drv_isr_simulate); ++ schedule_work(&simulation->work_queue); ++} ++#endif +diff --git a/drivers/sstar/ive/hal_ive_simulate.h b/drivers/sstar/ive/hal_ive_simulate.h +new file mode 100755 +index 000000000000..f71f7d011aa2 +--- /dev/null ++++ b/drivers/sstar/ive/hal_ive_simulate.h +@@ -0,0 +1,26 @@ ++/* ++* hal_ive_simulate.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_IVE_SIMULATE_H_ ++#define _HAL_IVE_SIMULATE_H_ ++ ++#include ++#include "hal_ive.h" ++ ++void ive_hal_run_simulate(ive_hal_handle *handle); ++ ++#endif // _HAL_IVE_SIMULATE_H_ +\ No newline at end of file +diff --git a/drivers/sstar/ive/mdrv_ive.c b/drivers/sstar/ive/mdrv_ive.c +new file mode 100755 +index 000000000000..75014f0fdc18 +--- /dev/null ++++ b/drivers/sstar/ive/mdrv_ive.c +@@ -0,0 +1,846 @@ ++/* ++* mdrv_ive.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mdrv_ive.h" ++ ++// #include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "mdrv_ive_io.h" ++#include "mdrv_ive_io_st.h" ++#include "drv_ive.h" ++#include "drv_camclk_Api.h" ++#if defined(CONFIG_CHIP_INFINITY2) ++#include "hal_clk.h" ++#endif ++ ++#define MDRV_IVE_DEVICE_COUNT (1) // How many device will be installed ++#define MDRV_IVE_NAME "mstar_ive" ++#define MDRV_IVE_MINOR (0) ++#define MDRV_IVE_CLASS_NAME "mstar_ive_class" ++ ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++//------------------------------------------------------------------------------------------------- ++// Driver Data Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Clock Enable ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_init ++ * init device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++static int mdrv_ive_clock_init(ive_dev_data *dev_data) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum; ++ u32 IveClk,ret = 0; ++ u8 str[8]; ++ CAMCLK_Set_Attribute stSetCfg; ++ CAMCLK_Get_Attribute stGetCfg; ++ ++ if(of_find_property(dev_data->pdev->dev.of_node,"camclk",&dev_data->IveParentCnt)) ++ { ++ dev_data->IveParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(dev_data->IveParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, dev_data->IveParentCnt); ++ return 0; ++ } ++ dev_data->pvclk = devm_kcalloc(&dev_data->pdev->dev, 1, (sizeof(void *) * dev_data->IveParentCnt), GFP_KERNEL); ++ if(!dev_data->pvclk){ ++ return 0; ++ } ++ for(u32clknum = 0; u32clknum < dev_data->IveParentCnt; u32clknum++) ++ { ++ IveClk = 0; ++ of_property_read_u32_index(dev_data->pdev->dev.of_node,"camclk", u32clknum,&(IveClk)); ++ if (!IveClk) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamOsSnprintf(str, 8, "Ive_%d ",u32clknum); ++ CamClkRegister(str,IveClk,&(dev_data->pvclk[u32clknum])); ++ CamClkAttrGet(dev_data->pvclk[u32clknum],&stGetCfg); ++ CAMCLK_SETPARENT(stSetCfg,stGetCfg.u32Parent[0]); ++ CamClkAttrSet(dev_data->pvclk[u32clknum],&stSetCfg); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++#else ++ int i, ret = 0; ++ struct clk *clk_parent; ++ ++ IVE_MSG(IVE_MSG_DBG, "init clock\n"); ++ ++ dev_data->clk_num = of_clk_get_parent_count(dev_data->pdev->dev.of_node); ++ if (dev_data->clk_num <= 0) { ++ IVE_MSG(IVE_MSG_ERR, "incorrect clock number (%d)\n", dev_data->clk_num); ++ return -1; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data->clk_num = %d\n", dev_data->clk_num); ++ ++ dev_data->clk = devm_kcalloc(&dev_data->pdev->dev, 1, (sizeof(struct clk *) * dev_data->clk_num), GFP_KERNEL); ++ if (dev_data->clk == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "can't allocate buffer for clock\n"); ++ return -1; ++ } ++ ++ for (i=0; iclk_num; i++) { ++ dev_data->clk[i] = of_clk_get(dev_data->pdev->dev.of_node, i); ++ if (IS_ERR(dev_data->clk[i])) { ++ IVE_MSG(IVE_MSG_ERR, "can't get clock %s\n", of_clk_get_parent_name(dev_data->pdev->dev.of_node, i)); ++ ret = -1; ++ goto ERROR; ++ } ++ ++ if (i == 0) ++ { ++ //clk_parent = clk_get_parent_by_index(dev_data->clk[i], 0); ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(dev_data->clk[i]), 0)->clk; ++ if(IS_ERR(clk_parent)) ++ { ++ IVE_MSG(IVE_MSG_ERR, "can't get parent clock\n"); ++ ret = -1; ++ goto ERROR; ++ } ++ ++ /* Set clock parent */ ++ if (clk_set_parent(dev_data->clk[i], clk_parent)) ++ { ++ IVE_MSG(IVE_MSG_ERR, "can't set parent clock\n"); ++ ret = -1; ++ goto ERROR; ++ } ++ } ++ } ++ ++ return ret; ++ ++ERROR: ++ devm_kfree(&dev_data->pdev->dev, dev_data->clk); ++ dev_data->clk = NULL; ++ dev_data->clk_num = 0; ++#endif ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_release ++ * release device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * none ++ */ ++static void mdrv_ive_clock_release(ive_dev_data *dev_data) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum; ++ ++ for(u32clknum=0;u32clknumIveParentCnt;u32clknum++) ++ { ++ if(dev_data->pvclk[u32clknum]) ++ { ++ printk(KERN_DEBUG "[%s] %p\n", __func__,dev_data->pvclk[u32clknum]); ++ CamClkUnregister(dev_data->pvclk[u32clknum]); ++ dev_data->pvclk[u32clknum] = NULL; ++ } ++ } ++ devm_kfree(&dev_data->pdev->dev, dev_data->pvclk); ++#else ++ int i; ++ ++ IVE_MSG(IVE_MSG_DBG, "release clock\n"); ++ ++ ++ for (i=0; iclk_num; i++) { ++ clk_put(dev_data->clk[i]); ++ } ++ ++ devm_kfree(&dev_data->pdev->dev, dev_data->clk); ++#endif ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_en ++ * enable device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++static int mdrv_ive_clock_en(ive_dev_data *dev_data) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0; ++ ++ for(u32clknum = 0; u32clknum < dev_data->IveParentCnt; u32clknum++) ++ { ++ if (dev_data->pvclk[u32clknum]) ++ { ++ CamClkSetOnOff(dev_data->pvclk[u32clknum],1); ++ } ++ } ++ ++#else ++ int i, ret = 0; ++ ++ IVE_MSG(IVE_MSG_DBG, "enable clock\n"); ++ ++ for (i=0; iclk_num; i++) { ++ ret = clk_prepare_enable(dev_data->clk[i]); ++ if (ret) { ++ IVE_MSG(IVE_MSG_ERR, "can't enable clock\n"); ++ return -1; ++ } ++ } ++#endif ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_dis ++ * disable device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++static void mdrv_ive_clock_dis(ive_dev_data *dev_data) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0; ++ ++ for(u32clknum = 0; u32clknum < dev_data->IveParentCnt; u32clknum++) ++ { ++ if (dev_data->pvclk[u32clknum]) ++ { ++ CamClkSetOnOff(dev_data->pvclk[u32clknum],0); ++ } ++ } ++#else ++ int i = 0; ++ ++ IVE_MSG(IVE_MSG_DBG, "disable clock\n"); ++ ++ for (i=0; iclk_num; i++) { ++ clk_disable_unprepare(dev_data->clk[i]); ++ } ++#endif ++} ++#endif //#if !defined(CONFIG_CHIAO_INFINITY2) //Only used by I5, I6E, except infinity 2 ++ ++//------------------------------------------------------------------------------------------------- ++// File operations ++//------------------------------------------------------------------------------------------------- ++ ++void mdrv_ive_drv_isr_post_proc(struct work_struct *wq) ++{ ++ ive_dev_data *dev_data = container_of(wq, ive_dev_data, work_queue); ++ ive_file_data *file_data; ++ ++ // Enter cirtical section ++ mutex_lock(&dev_data->mutex); ++ ++ file_data = ive_drv_post_process(&dev_data->drv_handle); ++ ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++ mdrv_ive_clock_dis(dev_data); ++#endif ++ ++ // Leave critical section ++ mutex_unlock(&dev_data->mutex); ++ ++ if (file_data == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "isr post process get NULL of file_data!!\n"); ++ return; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "post porcess 0x%p\n", &file_data->wait_queue); ++ ++ // set ready and wake up waiting thread/process ++ wake_up_interruptible(&file_data->wait_queue); ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_isr ++ * ISR handler ++ * ++ * Parameters: ++ * irq: IRQ ++ * dev_data: Device data which is assigned from request_irq() ++ * ++ * Return: ++ * Always IRQ_HANDLED to stop parsing ISR ++ */ ++irqreturn_t mdrv_ive_drv_isr(int irq, void* data) ++{ ++ ive_dev_data *dev_data = (ive_dev_data*)data; ++ IVE_DRV_STATE state; ++ ++ state = ive_drv_isr_handler(irq, &dev_data->drv_handle); ++ switch(state) { ++ case IVE_DRV_STATE_DONE: ++ INIT_WORK(&dev_data->work_queue, mdrv_ive_drv_isr_post_proc); ++ schedule_work(&dev_data->work_queue); ++ return IRQ_HANDLED; ++ ++ default: ++ return IRQ_NONE; ++ } ++ ++ return IRQ_NONE; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_open ++ * File open handler ++ * The device can has a instance at the same time, and the open ++ * operator also enable the clock and request q ISR. ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_ive_drv_open(struct inode *inode, struct file *filp) ++{ ++ ive_dev_data *dev_data = container_of(inode->i_cdev, ive_dev_data, cdev); ++ ive_file_data *file_data; ++ ++ // allocate buffer ++ file_data = devm_kcalloc(&dev_data->pdev->dev, 1, sizeof(ive_file_data), GFP_KERNEL); ++ if (file_data == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "error: can't allocate buffer\n"); ++ return -ENOSPC; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "filp: 0x%p, file_data: 0x%p\n", filp, file_data); ++ ++ // Assgin dev_data and keep file_data in the file structure ++ file_data->state = IVE_FILE_STATE_READY; ++ file_data->dev_data = dev_data; ++ filp->private_data = file_data; ++ ++ // Init wait queue ++ init_waitqueue_head(&file_data->wait_queue); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_release ++ * File close handler ++ * The operator will release clock & ISR ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_ive_drv_release(struct inode *inode, struct file *filp) ++{ ++ ive_file_data *file_data = (ive_file_data*)filp->private_data; ++ ive_dev_data *dev_data = file_data->dev_data; ++ ++ IVE_MSG(IVE_MSG_DBG, "filp: 0x%p\n", filp); ++ ++ // Release memory ++ devm_kfree(&dev_data->pdev->dev, file_data); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_ioctl_process ++ * IOCTL handler for IVE_IOC_PROCESS ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of ive_ioc_config from userspace ++ * ++ * Return: ++ * IVE_IOC_RET ++ */ ++static IVE_IOC_ERROR mdrv_ive_drv_ioctl_process(ive_file_data *file_data, unsigned long arg) ++{ ++ if (file_data->state != IVE_FILE_STATE_READY) { ++ IVE_MSG(IVE_MSG_ERR, "One file can request once at the same time only\n"); ++ return IVE_IOC_ERROR_BUSY; ++ } ++ ++ if (copy_from_user(&file_data->ioc_config, (void*)arg, sizeof(ive_ioc_config)) != 0) { ++ IVE_MSG(IVE_MSG_ERR, "Can't copy config from user space\n"); ++ return IVE_IOC_ERROR_PROC_CONFIG; ++ } ++ ++ file_data->user_io_config = (ive_ioc_config*)arg; ++ ++ return ive_drv_process(&(file_data->dev_data->drv_handle), file_data); ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_ioctl ++ * IOCTL handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * cmd: command ++ * arg: argument from user space ++ * ++ * Return: ++ * standard return value ++ */ ++long mdrv_ive_drv_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ ive_file_data *file_data = (ive_file_data*)filp->private_data; ++ ive_dev_data *dev_data = file_data->dev_data; ++ IVE_IOC_ERROR err = IVE_IOC_ERROR_NONE; ++ ++ IVE_MSG(IVE_MSG_DBG, "filp: 0x%p, command: 0x%X\n", filp, cmd); ++ ++ // Enter cirtical section ++ mutex_lock(&dev_data->mutex); ++ ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++ if (mdrv_ive_clock_en(dev_data)) { ++ err = IVE_IOC_ERROR_CLK; ++ goto RETURN; ++ } ++#endif ++ ++ switch(cmd) { ++ case IVE_IOC_PROCESS: ++ err = mdrv_ive_drv_ioctl_process(file_data, arg); ++ break; ++ ++ default: ++ err = ESRCH; ++ break; ++ } ++ ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++RETURN: ++#endif ++ ++ // Leave critical section ++ mutex_unlock(&dev_data->mutex); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_ioctl ++ * poll handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * wait: wait queue ++ * ++ * Return: ++ * only 0 or POLLIN | POLLRDNORM ++ */ ++static unsigned int mdrv_ive_drv_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ive_file_data *file_data = (ive_file_data*)filp->private_data; ++ ++ IVE_MSG(IVE_MSG_DBG, "polling 0x%p 0x%X\n", &file_data->wait_queue, file_data->state); ++ ++ if (file_data->state == IVE_FILE_STATE_READY) ++ { ++ return POLLIN | POLLRDNORM; ++ } ++ ++ poll_wait(filp, &file_data->wait_queue, wait); ++ ++ switch(file_data->state) ++ { ++ case IVE_FILE_STATE_DONE: ++ file_data->state = IVE_FILE_STATE_READY; ++ return POLLIN | POLLRDNORM; ++ ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Platform functions ++//------------------------------------------------------------------------------------------------- ++ ++// Use a struct to gather all global variable ++static struct ++{ ++ int major; // cdev major number ++ int minor_star; // begining of cdev minor number ++ int reg_count; // registered count ++ struct class *class; // class pointer ++} g_ive_drv = {0, 0, 0, NULL}; ++ ++static const struct file_operations ive_fops = { ++ .owner = THIS_MODULE, ++ .open = mdrv_ive_drv_open, ++ .release = mdrv_ive_drv_release, ++ .unlocked_ioctl = mdrv_ive_drv_ioctl, ++ .poll = mdrv_ive_drv_poll, ++}; ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_probe ++ * Platform device prob handler ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_probe(struct platform_device *pdev) ++{ ++ int err; ++ ive_dev_data *dev_data; ++ struct resource *res0, *res1; ++ struct device *dev; ++ ++ // create drv data buffer ++ dev_data = devm_kcalloc(&pdev->dev, 1, sizeof(ive_dev_data), GFP_KERNEL); ++ if (dev_data == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "can't allocate dev data buffer\n"); ++ return -ENOMEM; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p (size = %d)\n", dev_data, sizeof(ive_dev_data)); ++ // Get base address ++ res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (res0 == NULL || res1 == NULL ) { ++ IVE_MSG(IVE_MSG_ERR, "can't find base address\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ mutex_init(&dev_data->mutex); ++ ++ // Init dev_data ++ dev_data->pdev = pdev; ++ if (ive_drv_init(&dev_data->drv_handle, pdev, res0->start, res1->start) < 0) ++ { ++ IVE_MSG(IVE_MSG_ERR, "can't init driver\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ // Init clock ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++ if (mdrv_ive_clock_init(dev_data)) { ++ IVE_MSG(IVE_MSG_ERR, "can't init clock\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++#else //Only for infinity 2 ++ if (ive_clk_hal_init()) { ++ IVE_MSG(IVE_MSG_ERR, "can't init clock - I2\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++#endif ++ ++ // Retrieve IRQ ++ dev_data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (dev_data->irq < 0) { ++ IVE_MSG(IVE_MSG_ERR, "can't find IRQ\n"); ++ err = -ENODEV; ++ goto ERROR_2; ++ } ++ ++ // Register a ISR ++ err = request_irq(dev_data->irq, mdrv_ive_drv_isr, IRQ_TYPE_LEVEL_HIGH, "ive isr", dev_data); ++ if (err != 0) { ++ IVE_MSG(IVE_MSG_ERR, "isp interrupt failed (irq: %d, errno:%d)\n", dev_data->irq, err); ++ err = -ENODEV; ++ goto ERROR_2; ++ } ++ ++ // Add cdev ++ cdev_init(&dev_data->cdev, &ive_fops); ++ err= cdev_add(&dev_data->cdev, MKDEV(g_ive_drv.major, g_ive_drv.minor_star + g_ive_drv.reg_count), 1); ++ if (err) { ++ IVE_MSG(IVE_MSG_ERR, "Unable add a character device\n"); ++ goto ERROR_3; ++ } ++ ++ // Create a instance in class ++ dev = device_create(g_ive_drv.class, ++ NULL, ++ MKDEV(g_ive_drv.major, g_ive_drv.minor_star + g_ive_drv.reg_count), ++ dev_data, ++ MDRV_IVE_NAME"%d", g_ive_drv.minor_star + g_ive_drv.reg_count); ++ if (IS_ERR(dev)) { ++ IVE_MSG(IVE_MSG_ERR, "can't create device\n"); ++ err = -ENODEV; ++ goto ERROR_4; ++ } ++ ++ // Increase registered count ++ g_ive_drv.reg_count++; ++ ++ dev_set_drvdata(&pdev->dev, dev_data); ++ ++ return 0; ++ ++ERROR_4: ++ cdev_del(&dev_data->cdev); ++ ++ERROR_3: ++ free_irq(dev_data->irq, dev_data); ++ ++ERROR_2: ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++ mdrv_ive_clock_release(dev_data); ++#endif ++ ++ERROR_1: ++ devm_kfree(&dev_data->pdev->dev, dev_data); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_remove ++ * Platform device remove handler ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_remove(struct platform_device *pdev) ++{ ++ ive_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++#if !defined(CONFIG_CHIP_INFINITY2) //Only used by I5, I6E, except infinity 2 ++ mdrv_ive_clock_release(dev_data); ++#endif ++ ++ free_irq(dev_data->irq, dev_data); ++ ++ ive_drv_release(&dev_data->drv_handle); ++ ++ device_destroy(g_ive_drv.class, dev_data->cdev.dev); ++ cdev_del(&dev_data->cdev); ++ ++ devm_kfree(&dev_data->pdev->dev, dev_data); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_suspend ++ * Platform device suspend handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ ive_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_resume ++ * Platform device resume handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_resume(struct platform_device *pdev) ++{ ++ ive_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data strucure for device driver ++//------------------------------------------------------------------------------------------------- ++static const struct of_device_id mdrv_iveg_match[] = { ++ { ++ .compatible = "sstar,infinity-ive", ++ /*.data = NULL,*/ ++ }, ++ {}, ++}; ++ ++ ++static struct platform_driver mdrv_ive_driver = { ++ .probe = mdrv_ive_drv_probe, ++ .remove = mdrv_ive_drv_remove, ++ .suspend = mdrv_ive_drv_suspend, ++ .resume = mdrv_ive_drv_resume, ++ ++ .driver = { ++ .of_match_table = of_match_ptr(mdrv_iveg_match), ++ .name = "mstar_ive", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * _mdrv_ive_module_init ++ * module init function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_ive_module_init(void) ++{ ++ int err; ++ dev_t dev; ++ ++ IVE_MSG(IVE_MSG_DBG, "Moudle Init\n"); ++ ++ // Allocate cdev id ++ err = alloc_chrdev_region(&dev, MDRV_IVE_MINOR, MDRV_IVE_DEVICE_COUNT, MDRV_IVE_NAME); ++ if (err) { ++ IVE_MSG(IVE_MSG_ERR, "Unable allocate cdev id\n"); ++ return err; ++ } ++ ++ g_ive_drv.major = MAJOR(dev); ++ g_ive_drv.minor_star = MINOR(dev); ++ g_ive_drv.reg_count = 0; ++ ++ // Register device class ++ g_ive_drv.class = class_create(THIS_MODULE, MDRV_IVE_CLASS_NAME); ++ if (IS_ERR(g_ive_drv.class)) { ++ IVE_MSG(IVE_MSG_ERR, "Failed at class_create().Please exec [mknod] before operate the device/n"); ++ err = PTR_ERR(g_ive_drv.class); ++ goto ERR_RETURN_1; ++ } ++ ++ // Register platform driver ++ err = platform_driver_register(&mdrv_ive_driver); ++ if (err != 0) { ++ goto ERR_RETURN_2; ++ } ++ ++ return 0; ++ ++ERR_RETURN_2: ++ class_destroy(g_ive_drv.class); ++ ++ERR_RETURN_1: ++ unregister_chrdev_region(MKDEV(g_ive_drv.major, g_ive_drv.minor_star), MDRV_IVE_DEVICE_COUNT); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_module_exit ++ * module exit function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++void mdrv_ive_module_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ IVE_MSG(IVE_MSG_DBG, "Modules Exit\n"); ++ ++ platform_driver_unregister(&mdrv_ive_driver); ++ class_destroy(g_ive_drv.class); ++ unregister_chrdev_region(MKDEV(g_ive_drv.major, g_ive_drv.minor_star), MDRV_IVE_DEVICE_COUNT); ++} ++ ++module_init(mdrv_ive_module_init); ++module_exit(mdrv_ive_module_exit); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("IVE ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/ive/mdrv_ive.h b/drivers/sstar/ive/mdrv_ive.h +new file mode 100755 +index 000000000000..833b0d706f1d +--- /dev/null ++++ b/drivers/sstar/ive/mdrv_ive.h +@@ -0,0 +1,156 @@ ++/* ++* mdrv_ive.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: chris.luo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++ ++#include "drv_ive.h" ++#include "hal_ive.h" ++#include "mdrv_ive_io_st.h" ++ ++#ifndef _MDRV_IVE_H_ ++#define _MDRV_IVE_H_ ++ ++// SW simulation for driver debug without real HW ++// #define IVE_SW_SIMULATE ++ ++// Defines reference kern levels of printfk ++#define IVE_MSG_ERR 3 ++#define IVE_MSG_WRN 4 ++#define IVE_MSG_DBG 5 ++ ++#define IVE_MSG_LEVL IVE_MSG_WRN ++ ++ ++#define IVE_MSG_ENABLE ++ ++#if defined(IVE_MSG_ENABLE) ++#define IVE_MSG_FUNC_ENABLE ++ ++#define IVE_STRINGIFY(x) #x ++#define IVE_TOSTRING(x) IVE_STRINGIFY(x) ++ ++#if defined(IVE_MSG_FUNC_ENABLE) ++#define IVE_MSG_TITLE "[IVE, %s] " ++#define IVE_MSG_FUNC __func__ ++#else // NOT defined(IVE_MSG_FUNC_ENABLE) ++#define IVE_MSG_TITLE "[IVE] %s" ++#define IVE_MSG_FUNC "" ++#endif // NOT defined(IVE_MSG_FUNC_ENABLE) ++ ++#define IVE_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define IVE_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= IVE_MSG_LEVL) { \ ++ printk(KERN_SOH IVE_TOSTRING(dbglv) IVE_MSG_TITLE _fmt, IVE_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++#else // NOT defined(IVE_MSG_ENABLE) ++#define IVE_ASSERT(arg) ++#define IVE_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(IVE_MSG_ENABLE) ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// Driver Data Structure ++// ++// Enum and structure fo IVE dirver ++// We declare enum & structure here because enum and structures are ++// shared in all three layers (mdrv, drv, and hal_simulation) ++// ++// It is not good way for modulization, but most members of structure are not pointer ++// because it can simplify the memory managent ++// and container_of() is a key funtion to access data strucure in operators ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * There are 2 state enumeration ++ * IVE_DRV_STATE: indicate the state of HW ++ * IVE_FILE_STATE: indicate the state of File ++ * ++ * File and HW has different state because it support multi instance ++ * and file request may be queued if HW is busy ++ */ ++#define USE_MIU_DIRECT ++ ++typedef enum ++{ ++ IVE_DRV_STATE_READY = 0, ++ IVE_DRV_STATE_PROCESSING = 1, ++ IVE_DRV_STATE_DONE = 2 ++} IVE_DRV_STATE; ++ ++typedef enum ++{ ++ IVE_FILE_STATE_READY = 0, ++ IVE_FILE_STATE_PROCESSING = 1, ++ IVE_FILE_STATE_DONE = 2, ++ IVE_FILE_STATE_IN_QUEUE = 3 ++} IVE_FILE_STATE; ++ ++typedef union ++{ ++ ive_ioc_coeff_ncc ncc_buffer; ++ __u8 map_buffer[256]; ++} ive_work_buffer; ++ ++// Data structure for driver ++typedef struct ++{ ++ struct platform_device *pdev; // platform device data ++ ive_hal_handle hal_handle; // HAL handle for real HW configuration ++ IVE_DRV_STATE dev_state; // HW state ++ struct list_head request_list; // request list to queue waiting requst ++} ive_drv_handle; ++ ++// Device data ++typedef struct { ++ struct platform_device *pdev; // platform device data ++ struct cdev cdev; // character device ++ struct clk **clk; // clock ++ int clk_num; // clock number ++ unsigned int irq; // IRQ number ++ ive_drv_handle drv_handle; // device handle ++ struct work_struct work_queue; // work queue for post process after ISR ++ struct mutex mutex; // for critical section ++#ifdef CONFIG_CAM_CLK ++ void **pvclk; ++ int IveParentCnt; ++#endif ++} ive_dev_data; ++ ++// File private data ++typedef struct{ ++ ive_dev_data *dev_data; // Device data ++ ive_ioc_config ioc_config; // IO configuation, i.e. one device file can service one request at the same time ++ IVE_FILE_STATE state; // File state ++ wait_queue_head_t wait_queue; // Wait queue for polling operation ++ ive_ioc_config *user_io_config;// IO configuation pointer from user space ++} ive_file_data; ++ ++#endif //_MDRV_IVE_H_ +diff --git a/drivers/sstar/miu/Kconfig b/drivers/sstar/miu/Kconfig +new file mode 100755 +index 000000000000..6d8c9d7daf8e +--- /dev/null ++++ b/drivers/sstar/miu/Kconfig +@@ -0,0 +1,19 @@ ++config MSTAR_MIU ++ ++tristate "MSTAR MIU" ++ ++help ++ MStar miu driver ++default n ++ ++if MSTAR_MIU ++choice ++ prompt "MIU_PROTECT" ++ default SSC007A_S01A ++config SSC007A_S01A ++ bool "ssc007a-s01a" ++endchoice ++ ++ ++endif ++ +diff --git a/drivers/sstar/miu/Makefile b/drivers/sstar/miu/Makefile +new file mode 100755 +index 000000000000..70f2d6507fa3 +--- /dev/null ++++ b/drivers/sstar/miu/Makefile +@@ -0,0 +1,24 @@ ++# ++# Makefile for MStar mtlb device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ifdef CONFIG_MSTAR_PROJECT_NAME ++ CONFIG_MSTAR_PROJECT_NAME := $(subst ",,$(CONFIG_MSTAR_PROJECT_NAME)) ++endif ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include/ ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/miu ++EXTRA_CFLAGS += -Iinclude/linux ++# specific options ++EXTRA_CFLAGS += ++ ++ ++# files ++obj-$(CONFIG_MSTAR_MIU) := mdrv-miu.o ++ ++mdrv-miu-objs := $(CONFIG_SSTAR_CHIP_NAME)/mdrv_miu.o ++mdrv-miu-objs += $(CONFIG_SSTAR_CHIP_NAME)/mhal_miu.o ++ +diff --git a/drivers/sstar/miu/MsTypes.h b/drivers/sstar/miu/MsTypes.h +new file mode 100755 +index 000000000000..13cd7b7a06ff +--- /dev/null ++++ b/drivers/sstar/miu/MsTypes.h +@@ -0,0 +1,271 @@ ++/* ++* MsTypes.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _MS_TYPES_H_ ++#define _MS_TYPES_H_ ++ ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_64BIT ++//============================================================================= ++// Type and Structure Declaration ++//============================================================================= ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned int MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed int MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef size_t MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef size_t MS_PHYADDR; // 8 bytes ++ /// data type size_t ++ typedef size_t MS_SIZE; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U64 MS_PHY; // 8 bytes ++ ++ /// print type MPRI_PHY ++ #define MPRI_PHY "%x" ++ /// print type MPRI_VIRT ++ #define MPRI_VIRT "%tx" ++ ++#else ++//============================================================================= ++// Type and Structure Declaration ++//============================================================================= ++ /// data type unsigned char, data length 1 byte ++ typedef unsigned char MS_U8; // 1 byte ++ /// data type unsigned short, data length 2 byte ++ typedef unsigned short MS_U16; // 2 bytes ++ /// data type unsigned int, data length 4 byte ++ typedef unsigned int MS_U32; // 4 bytes ++ /// data type unsigned int, data length 8 byte ++ typedef unsigned long long MS_U64; // 8 bytes ++ /// data type signed char, data length 1 byte ++ typedef signed char MS_S8; // 1 byte ++ /// data type signed short, data length 2 byte ++ typedef signed short MS_S16; // 2 bytes ++ /// data type signed int, data length 4 byte ++ typedef signed int MS_S32; // 4 bytes ++ /// data type signed int, data length 8 byte ++ typedef signed long long MS_S64; // 8 bytes ++ /// data type float, data length 4 byte ++ typedef float MS_FLOAT; // 4 bytes ++ /// data type pointer content ++ typedef size_t MS_VIRT; // 8 bytes ++ /// data type hardware physical address ++ typedef size_t MS_PHYADDR; // 8 bytes ++ /// data type 64bit physical address ++ typedef MS_U64 MS_PHY; // 8 bytes ++ /// data type size_t ++ typedef size_t MS_SIZE; // 8 bytes ++ ++ ++ /// print type MPRI_PHY ++ #define MPRI_PHY "%x" ++ /// print type MPRI_PHY ++ #define MPRI_VIRT "%tx" ++#endif ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#ifdef CONFIG_MP_PURE_SN_32BIT ++typedef unsigned int MS_PHY64; // 32bit physical address ++#else ++typedef unsigned long long MS_PHY64; // 64bit physical address ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// definition for MS_BOOL ++typedef unsigned char MS_BOOL; ++/// definition for VOID ++typedef void VOID; ++/// definition for FILEID ++typedef MS_S32 FILEID; ++ ++//[TODO] use MS_U8, ... instead ++// data type for 8051 code ++//typedef MS_U16 WORD; ++//typedef MS_U8 BYTE; ++ ++ ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++ ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++///Define MS FB Format, to share with GE,GOP ++/// FIXME THE NAME NEED TO BE REFINED, AND MUST REMOVE UNNESSARY FMT ++typedef enum ++{ ++ /// color format I1 ++ E_MS_FMT_I1 = 0x0, ++ /// color format I2 ++ E_MS_FMT_I2 = 0x1, ++ /// color format I4 ++ E_MS_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ E_MS_FMT_I8 = 0x4, ++ /// color format blinking display ++ E_MS_FMT_FaBaFgBg2266 = 0x6, ++ /// color format for blinking display format ++ E_MS_FMT_1ABFgBg12355 = 0x7, ++ /// color format RGB565 ++ E_MS_FMT_RGB565 = 0x8, ++ /// color format ARGB1555 ++ /// @note [URANUS] ARGB1555 is only RGB555 ++ E_MS_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ E_MS_FMT_ARGB4444 = 0xa, ++ /// color format ARGB1555 DST ++ E_MS_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ E_MS_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ E_MS_FMT_ARGB8888 = 0xf, ++ ++ E_MS_FMT_GENERIC = 0xFFFF, ++ ++} MS_ColorFormat; ++ ++ ++typedef union _MSIF_Version ++{ ++ struct _DDI ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 model; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 change[8]; ++ MS_U8 os; ++ } DDI; ++ struct _MW ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 mod; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 changelist[8]; ++ MS_U8 os; ++ } MW; ++ struct _APP ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U8 id[4]; ++ MS_U8 quality; ++ MS_U8 version[4]; ++ MS_U8 time[6]; ++ MS_U8 changelist[8]; ++ MS_U8 reserve[3]; ++ } APP; ++} MSIF_Version; ++ ++typedef MS_U8 BOOLEAN; ///< BOOLEAN ++ ++#define COUNTOF( array ) (sizeof(array) / sizeof((array)[0])) ++ ++#define _OFF 0 ++#define _ON 1 ++#define _HIGH 1 ++#define _LOW 0 ++#define _OUTPUT 0 ++#define _INPUT 1 ++ ++#define bit MS_U8 ++ ++#if !defined(BIT0) && !defined(BIT1) ++#define BIT0 0x0001 ++#define BIT1 0x0002 ++#define BIT2 0x0004 ++#define BIT3 0x0008 ++#define BIT4 0x0010 ++#define BIT5 0x0020 ++#define BIT6 0x0040 ++#define BIT7 0x0080 ++#define BIT8 0x0100 ++#define BIT9 0x0200 ++#define BIT10 0x0400 ++#define BIT11 0x0800 ++#define BIT12 0x1000 ++#define BIT13 0x2000 ++#define BIT14 0x4000 ++#define BIT15 0x8000 ++#endif ++ ++typedef unsigned char BYTE; ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/sstar/miu/infinity2/mdrv_miu.c b/drivers/sstar/miu/infinity2/mdrv_miu.c +new file mode 100755 +index 000000000000..2f870b659adc +--- /dev/null ++++ b/drivers/sstar/miu/infinity2/mdrv_miu.c +@@ -0,0 +1,453 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mdrvl_miu.c ++/// @brief MIU Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include "MsTypes.h" ++#include "mdrv_miu.h" ++#include "mhal_miu.h" ++#include "regMIU.h" ++#include ++ ++#include ++#include ++#include ++ ++#include "irqs.h" ++ ++#ifndef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ struct timer_list monitor_timer; ++ int gOpenTimeList = 0; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_MSTAR_MONET) || defined(CONFIG_MSTAR_MESSI) || defined(CONFIG_MSTAR_MASERATI) || defined(CONFIG_MSTAR_MANHATTAN) || defined(CONFIG_MSTAR_KANO) ++ MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY phy64Start, MS_PHY phy64End, MS_BOOL bSetFlag) __attribute__((weak)); ++#else ++ MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, MS_U32 u32BusEnd, PROTECT_CTRL bSetFlag) __attribute__((weak)); ++#endif ++ ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetDefaultClientID_KernelProtect(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SlitInit(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SetSlitRange(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY u64BusStart, MS_PHY u64BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++MS_BOOL HAL_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++unsigned int u32MiuDramSize = 0x40000000UL; ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++static DEFINE_SPINLOCK(miu_lock); ++MS_U8 u8_MiuWhiteListNum = 0; ++//------------------------------------------------------------------------------------------------- ++// Local functions ++//------------------------------------------------------------------------------------------------- ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Init ++/// @brief \b Function \b Description: parse occupied resource to software structure ++/// @param None \b IN : ++/// @param None \b OUT : ++/// @param MS_BOOL \b RET ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++ ++MS_BOOL MDrv_MIU_Init(void) ++{ ++ MS_BOOL ret; ++ ++ /* Parse the used client ID in hardware into software data structure */ ++ if(HAL_MIU_ParseOccupiedResource) ++ { ++ ret = HAL_MIU_ParseOccupiedResource(); ++ } ++ else ++ { ++ ret = FALSE; ++ } ++ ++ /* Initialize MIU slit setting */ ++ if(HAL_MIU_SlitInit) ++ { ++ ret = HAL_MIU_SlitInit(); ++ } ++ ++ u8_MiuWhiteListNum = IDNUM_KERNELPROTECT; ++ return ret; ++} ++#if (1 == CONFIG_MSTAR_MMAHEAP) ++EXPORT_SYMBOL(MDrv_MIU_Init); ++EXPORT_SYMBOL(u8_MiuWhiteListNum); ++#endif ++///////////////////////////////////////////////////////////////////////// ++// @brief \n get IDenables in mi layer. ++MS_BOOL MDrv_MIU_Get_IDEnables_Value(MS_U8 u8MiuDev, MS_U8 u8Blockx, MS_U8 u8ClientIndex) ++{ ++ return HAL_MIU_Get_IDEnables_Value(u8MiuDev, u8Blockx, u8ClientIndex); ++} ++EXPORT_SYMBOL(MDrv_MIU_Get_IDEnables_Value); ++ ++MS_BOOL MDrv_MIU_GetProtectInfo(MS_U8 u8MiuDev, MIU_PortectInfo *pInfo) ++{ ++ return HAL_MIU_GetProtectInfo(u8MiuDev, pInfo); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* MDrv_MIU_GetDefaultClientID_KernelProtect(void) ++{ ++ if(HAL_MIU_GetDefaultClientID_KernelProtect) ++ { ++ return HAL_MIU_GetDefaultClientID_KernelProtect(); ++ } ++ else ++ { ++ return NULL; ++ } ++} ++#if (1 == CONFIG_MSTAR_MMAHEAP) ++EXPORT_SYMBOL(MDrv_MIU_GetDefaultClientID_KernelProtect); ++#endif ++#include ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static irqreturn_t MDrv_MIU_Protect_interrupt(s32 irq, void *dev_id) ++{ ++ MS_U8 u8MiuDev = 0; ++ MIU_PortectInfo *pInfo = kmalloc(sizeof(MIU_PortectInfo), GFP_KERNEL); ++ MDrv_MIU_GetProtectInfo(u8MiuDev, pInfo); ++ BUG(); ++ return IRQ_HANDLED; ++} ++#else ++//create timer process ++static void MDev_timer_callback(unsigned long value) ++{ ++ MS_U8 u8MiuDev = 0; ++ MIU_PortectInfo pInfo; ++ ++ pInfo.bHit = FALSE; ++ ++ MDrv_MIU_GetProtectInfo(u8MiuDev, &pInfo); ++ if(pInfo.bHit) ++ /* panic("MIU Protect hit!\n"); */ ++ printk(KERN_ERR "MIU Protect hit!\n"); ++ ++ mod_timer(&monitor_timer, jiffies+1*HZ); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 3) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Protect( ++ MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_PHY u64BusStart, ++ MS_PHY u64BusEnd, ++ PROTECT_CTRL bSetFlag ++ ) ++{ ++ MS_BOOL Result = FALSE; ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ int rc = 0; ++#endif ++ /*Case of former MIU protect*/ ++ if((u8Blockx >= E_PROTECT_0) && (u8Blockx < E_SLIT_0)) ++ { ++ if(HAL_MIU_Protect) ++ { ++ Result = HAL_MIU_Protect(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag); ++ } ++ } ++ /*Case of MIU slits*/ ++ else if (u8Blockx == E_SLIT_0) ++ { ++ if(HAL_MIU_SetSlitRange) ++ { ++ Result = HAL_MIU_SetSlitRange(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag); ++ } ++ } ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ rc = request_irq(( GIC_PPI_NR + GIC_SGI_NR + INT_IRQ_35_MIU_INT), MDrv_MIU_Protect_interrupt, IRQF_TRIGGER_HIGH, "MIU_Protect", NULL); ++#else ++ if(gOpenTimeList == 0 ) ++ { ++ init_timer( &monitor_timer ); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++ gOpenTimeList++; ++ } ++#endif ++ ++ ++ return Result; ++} ++ ++#if (1 == CONFIG_MSTAR_MMAHEAP) ++EXPORT_SYMBOL(MDrv_MIU_Protect); ++#endif ++ ++MS_BOOL MDrv_MIU_Save(void) ++{ ++ MS_BOOL Result = FALSE; ++ #if 0 ++ ///TODO:now k6l do not have HAL_MIU_Save,even main trunk k6l do not have. ++ //BUT now we need open CONFIG_MSTAR_MIU,though not use MDrv_MIU_Save , ++ //here we keep MDrv_MIU_Save ,but git a BUG_ON for build success. ++ //Future owner should add HAL_MIU_Save for k6l if k6l need both STR and CONFIG_MSTAR_MIU enable. ++ ++ Result = HAL_MIU_Save(); ++ #else ++ BUG_ON(1);//give this BUG_ON to show owner that we need HAL_MIU_Save for k6l. ++ #endif ++ return Result; ++} ++ ++MS_BOOL MDrv_MIU_Restore(void) ++{ ++ MS_BOOL Result = FALSE; ++ #if 0 ++ ///TODO:now k6l do not have HAL_MIU_Restore,even main trunk k6l do not have. ++ //BUT now we need open CONFIG_MSTAR_MIU,though not use MDrv_MIU_Restore , ++ //here we keep MDrv_MIU_Restore ,but git a BUG_ON for build success. ++ //Future owner should add HAL_MIU_Save for k6l if k6l need both STR and CONFIG_MSTAR_MIU enable ++ ++ Result = HAL_MIU_Restore(); ++ #else ++ BUG_ON(1);//give this BUG_ON to show owner that we need HAL_MIU_Restore for k6l. ++ #endif ++ return Result; ++} ++ ++unsigned int MDrv_MIU_ProtectDramSize(void) ++{ ++ return HAL_MIU_ProtectDramSize(); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: _MDrv_MIU_SetSsc() ++/// @brief \b Function \b Description: _MDrv_MIU_SetSsc, @Step & Span ++/// @param u16Fmodulation \b IN : 20KHz ~ 40KHz (Input Value = 20 ~ 40) ++/// @param u16FDeviation \b IN : under 0.1% ~ 3% (Input Value = 1 ~ 30) ++/// @param bEnable \b IN : ++/// @param None \b OUT : ++/// @param None \b RET : ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++unsigned char MDrv_MIU_SetSsc(unsigned short u16Fmodulation, unsigned short u16FDeviation, unsigned char bEnable) ++{ ++ return (unsigned char)HAL_MIU_SetSsc((MS_U8)0, (MS_U16)u16Fmodulation, (MS_U16)u16FDeviation, (MS_BOOL)bEnable); ++} ++EXPORT_SYMBOL(MDrv_MIU_SetSsc); ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: _MDrv_MIU_SetSscValue() ++/// @brief \b Function \b Description: _MDrv_MIU_SetSscValue, @Step & Span ++/// @param u8Miu \b IN : 0: MIU0 1:MIU1 ++/// @param u16Fmodulation \b IN : 20KHz ~ 40KHz (Input Value = 20 ~ 40) ++/// @param u16FDeviation \b IN : under 0.1% ~ 3% (Input Value = 1 ~ 30) ++/// @param bEnable \b IN : ++/// @param None \b OUT : ++/// @param None \b RET : ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++unsigned char MDrv_MIU_SetSscValue(unsigned char u8MiuDev, unsigned short u16Fmodulation, unsigned short u16FDeviation, unsigned char bEnable) ++{ ++ return (unsigned char)HAL_MIU_SetSsc((MS_U8)u8MiuDev, (MS_U16)u16Fmodulation, (MS_U16)u16FDeviation, (MS_BOOL)bEnable); ++} ++EXPORT_SYMBOL(MDrv_MIU_SetSscValue); ++ ++//#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetProtectInfo() ++/// @brief \b Function \b Description: This function for querying client ID info ++/// @param u8MiuDev \b IN : select MIU0 or MIU1 ++/// @param eClientID \b IN : Client ID ++/// @param pInfo \b OUT : Client Info ++/// @param None \b RET: 0: Fail 1: Ok ++//////////////////////////////////////////////////////////////////////////////// ++ ++//#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Slits() ++/// @brief \b Function \b Description: Enable/Disable MIU Slit ++/// @param u8Blockx \b IN : MIU Block to protect (E_MIU_SLIT_0) ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) ++{ ++ unsigned long flags; ++ MS_BOOL Result = FALSE; ++ ++ spin_lock_irqsave(&miu_lock, flags); ++ ++ if(HAL_MIU_Slits) ++ { ++ Result = HAL_MIU_Slits(u8Blockx, u64SlitsStart, u64SlitsEnd, bSetFlag); ++ } ++ ++ spin_unlock_irqrestore(&miu_lock, flags); ++ ++ return Result; ++} ++ ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo) ++{ ++ return HAL_MIU_Info((MIU_DramInfo_Hal *)pDramInfo); ++} ++EXPORT_SYMBOL(MDrv_MIU_Info); ++ ++static int mstar_miu_drv_probe(struct platform_device *pdev) ++{ ++ u32MiuDramSize = MDrv_MIU_ProtectDramSize(); ++ return 0; ++} ++ ++static const struct of_device_id ms_uart_of_match_table[] = { ++ { .compatible = "mstar,miu" }, ++ {} ++}; ++ ++static int mstar_miu_drv_remove(struct platform_device *pdev) ++{ ++ del_timer(&monitor_timer); ++ return 0; ++} ++ ++static int mstar_miu_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++#ifndef CONFIG_MSTAR_CMAPOOL ++#if 0 ++ ///TODO:now k6l do not have HAL_MIU_Save,even main trunk k6l do not have. ++ //BUT now we need open CONFIG_MSTAR_MIU, ++ //here we keep mstar_miu_drv_suspend ,but git a BUG_ON for build success. ++ //Future owner should add HAL_MIU_Save for k6l if k6l need both STR and CONFIG_MSTAR_MIU enable ++ ++ HAL_MIU_Save(); ++#else ++ BUG_ON(1); ++#endif ++ ++ ++#endif ++ return 0; ++} ++ ++static int mstar_miu_drv_resume(struct platform_device *dev) ++{ ++#ifndef CONFIG_MSTAR_CMAPOOL ++ ++#if 0 ++ ///TODO:now k6l do not have HAL_MIU_Restore,even main trunk k6l do not have. ++ //BUT now we need open CONFIG_MSTAR_MIU, ++ //here we keep mstar_miu_drv_resume ,but git a BUG_ON for build success. ++ //Future owner should add HAL_MIU_Restore for k6l if k6l need both STR and CONFIG_MSTAR_MIU enable ++ ++ HAL_MIU_Restore(); ++#else ++ BUG_ON(1); ++#endif ++ ++#endif ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstarmiu_of_device_ids[] = { ++ {.compatible = "mstar-miu"}, ++ {}, ++}; ++#endif ++ ++static struct platform_driver Mstar_miu_driver = { ++ .probe = mstar_miu_drv_probe, ++ .remove = mstar_miu_drv_remove, ++ .suspend = mstar_miu_drv_suspend, ++ .resume = mstar_miu_drv_resume, ++ .driver = { ++ .name = "Mstar-miu", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstarmiu_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++EXPORT_SYMBOL(u32MiuDramSize); ++static int __init mstar_miu_drv_init_module(void) ++{ ++// retval = platform_driver_register(&Mstar_miu_driver); ++ int ret = 0; ++ ret = platform_driver_register(&Mstar_miu_driver); ++ if (ret) ++ { ++ printk("Register Mstar MIU Platform Driver Failed!"); ++ } ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_miu_driver); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/miu/infinity2/mhal_miu.c b/drivers/sstar/miu/infinity2/mhal_miu.c +new file mode 100755 +index 000000000000..ae74dd8263db +--- /dev/null ++++ b/drivers/sstar/miu/infinity2/mhal_miu.c +@@ -0,0 +1,1726 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_mtlb.c ++/// @brief MTLB Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include "MsTypes.h" ++#include "mdrv_types.h" ++#include "mdrv_miu.h" ++#include "regMIU.h" ++#include "mhal_miu.h" ++#if defined(CONFIG_COMPAT) ++#include ++#endif ++#include "mdrv_system.h" ++#include "registers.h" ++#include "ms_platform.h" ++//------------------------------------------------------------------------------------------------- ++// Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_CEVAXM6_0_RW, \ ++/* 2 */ MIU_CLIENT_CEVAXM6_1_RW, \ ++/* 3 */ MIU_CLIENT_VD_R2I_R, \ ++/* 4 */ MIU_CLIENT_VD_R2_SUBSYS_R, \ ++/* 5 */ MIU_CLIENT_VD_R2D_RW, \ ++/* 6 */ MIU_CLIENT_CEVAXM6_2_RW, \ ++/* 7 */ MIU_CLIENT_CEVAXM6_3_RW, \ ++/* 8 */ MIU_CLIENT_AUDIO_R, \ ++/* 9 */ MIU_CLIENT_AUDIO_AU2_R, \ ++/* A */ MIU_CLIENT_AUDIO_AU3_W, \ ++/* B */ MIU_CLIENT_CMDQ_R, \ ++/* C */ MIU_CLIENT_XD2MIU_RW, \ ++/* D */ MIU_CLIENT_UART_DMA_RW, \ ++/* E */ MIU_CLIENT_BDMA_RW, \ ++/* F */ MIU_CLIENT_DUMMY_G0CF ++ ++#define MIU_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_SC1_CROP_LDC, \ ++/* 1 */ MIU_CLIENT_ISP_GOP1_R, \ ++/* 2 */ MIU_CLIENT_CMDQ_TOP_1_R, \ ++/* 3 */ MIU_CLIENT_NOE_RW, \ ++/* 4 */ MIU_CLIENT_USB30_RW, \ ++/* 5 */ MIU_CLIENT_ISP_STA_W, \ ++/* 6 */ MIU_CLIENT_ISP_AF_STA1_W, \ ++/* 7 */ MIU_CLIENT_ISP_GOP2_R, \ ++/* 8 */ MIU_CLIENT_EMAC_RW, \ ++/* 9 */ MIU_CLIENT_IVE_TOP_RW, \ ++/* A */ MIU_CLIENT_ISP_GOP3_R, \ ++/* B */ MIU_CLIENT_MIIC0_RW, \ ++/* C */ MIU_CLIENT_MIIC1_RW, \ ++/* D */ MIU_CLIENT_MIIC2_RW, \ ++/* E */ MIU_CLIENT_ISP_SC1_DBG_R, \ ++/* F */ MIU_CLIENT_ISP_CMDQ_TOP2_R ++ ++#define MIU_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_SDIO_RW, \ ++/* 1 */ MIU_CLIENT_USB30_1_RW, \ ++/* 2 */ MIU_CLIENT_USB30_2_RW, \ ++/* 3 */ MIU_CLIENT_SD30_RW, \ ++/* 4 */ MIU_CLIENT_JPE_W, \ ++/* 5 */ MIU_CLIENT_JPE_R, \ ++/* 6 */ MIU_CLIENT_U3DEV_RW, \ ++/* 7 */ MIU_CLIENT_JPD_RW, \ ++/* 8 */ MIU_CLIENT_GMAC_RW, \ ++/* 9 */ MIU_CLIENT_FCIE5_RW, \ ++/* A */ MIU_CLIENT_SECGMAC, \ ++/* B */ MIU_CLIENT_USB30M1_HS_RW, \ ++/* C */ MIU_CLIENT_SATA0_RW, \ ++/* D */ MIU_CLIENT_SATA1_RW, \ ++/* E */ MIU_CLIENT_USB20_RW, \ ++/* F */ MIU_CLIENT_USB20_P1_RW ++ ++#define MIU_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_ISP_GOP4_R, \ ++/* 1 */ MIU_CLIENT_ISOSC_BLKS_RW, \ ++/* 2 */ MIU_CLIENT_CMDQ_TOP5_R, \ ++/* 3 */ MIU_CLIENT_ISP_GOP0_R, \ ++/* 4 */ MIU_CLIENT_SC1_FRAME_W, \ ++/* 5 */ MIU_CLIENT_SC1_SNAPSHOT_W, \ ++/* 6 */ MIU_CLIENT_SC2_FRAME_W, \ ++/* 7 */ MIU_CLIENT_CMDQ_TOP4_R, \ ++/* 8 */ MIU_CLIENT_MFE0_R, \ ++/* 9 */ MIU_CLIENT_MFE0_W, \ ++/* A */ MIU_CLIENT_SC3_FRAME_RW, \ ++/* B */ MIU_CLIENT_DUMMY_G3CB, \ ++/* C */ MIU_CLIENT_DUMMY_G3CC, \ ++/* D */ MIU_CLIENT_MFE1_R, \ ++/* E */ MIU_CLIENT_MFE1_W, \ ++/* F */ MIU_CLIENT_ISP_MLOAD_R ++ ++#define MIU_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_VE_W, \ ++/* 1 */ MIU_CLIENT_EVD_ENG1_RW, \ ++/* 2 */ MIU_CLIENT_MGWIN0_R, \ ++/* 3 */ MIU_CLIENT_MGWIN1_R, \ ++/* 4 */ MIU_CLIENT_HVD_RW, \ ++/* 5 */ MIU_CLIENT_HVD1_RW, \ ++/* 6 */ MIU_CLIENT_DDI_0_RW, \ ++/* 7 */ MIU_CLIENT_EVD_ENG0_RW, \ ++/* 8 */ MIU_CLIENT_MFDEC0_1_R, \ ++/* 9 */ MIU_CLIENT_ISPSC_DMAG, \ ++/* A */ MIU_CLIENT_EVD_BBU_R, \ ++/* B */ MIU_CLIENT_HVD_BBU_R, \ ++/* C */ MIU_CLIENT_SC1_IPMAIN_RW, \ ++/* D */ MIU_CLIENT_SC1_OPM_R, \ ++/* E */ MIU_CLIENT_MFDEC_1_1_R, \ ++/* F */ MIU_CLIENT_LDC_R ++ ++#define MIU_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_GOP0_R, \ ++/* 1 */ MIU_CLIENT_GOP1_R, \ ++/* 2 */ MIU_CLIENT_AUTO_DOWNLOAD_R, \ ++/* 3 */ MIU_CLIENT_SC_DIPW_RW, \ ++/* 4 */ MIU_CLIENT_MVOP_128BIT_R, \ ++/* 5 */ MIU_CLIENT_MVOP1_R, \ ++/* 6 */ MIU_CLIENT_FRC_IPM0_W, \ ++/* 7 */ MIU_CLIENT_SC_IPSUB_RW, \ ++/* 8 */ MIU_CLIENT_FRC_OPM0_R, \ ++/* 9 */ MIU_CLIENT_MDWIN0_W, \ ++/* A */ MIU_CLIENT_MFDEC0_R, \ ++/* B */ MIU_CLIENT_MFDEC1_R, \ ++/* C */ MIU_CLIENT_MDWIN1_W, \ ++/* D */ MIU_CLIENT_SC_DYN_SCL_R, \ ++/* E */ MIU_CLIENT_VE_R, \ ++/* F */ MIU_CLIENT_GE_RW ++ ++#define MIU_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_ISP_DMAG0_W, \ ++/* 1 */ MIU_CLIENT_ISP_DMAG0_R, \ ++/* 2 */ MIU_CLIENT_ISP_DMAG1_W, \ ++/* 3 */ MIU_CLIENT_ISP_DMAG1_R, \ ++/* 4 */ MIU_CLIENT_ISP_DMAG2_RW, \ ++/* 5 */ MIU_CLIENT_ISP_DMAG3_RW, \ ++/* 6 */ MIU_CLIENT_ISP_DMAG4_W, \ ++/* 7 */ MIU_CLIENT_ISP_DMAG4_R, \ ++/* 8 */ MIU_CLIENT_ISP_DMAG_RW, \ ++/* 9 */ MIU_CLIENT_DMA_GENERAL_RW, \ ++/* A */ MIU_CLIENT_SC1_DNR_RW, \ ++/* B */ MIU_CLIENT_DUMMY_G6CB, \ ++/* C */ MIU_CLIENT_MHE0_R, \ ++/* D */ MIU_CLIENT_MHE0_W, \ ++/* E */ MIU_CLIENT_MHE1_R, \ ++/* F */ MIU_CLIENT_MHE1_W ++ ++#define MIU_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_G3D_RW, \ ++/* 2 */ MIU_CLIENT_DUMMY_G7_C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G7_C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G7_C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G7_C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G7_C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G7_C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G7_C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G7_C9, \ ++/* A */ MIU_CLIENT_DUMMY_G7_CA, \ ++/* B */ MIU_CLIENT_DUMMY_G7_CB, \ ++/* C */ MIU_CLIENT_DUMMY_G7_CC, \ ++/* D */ MIU_CLIENT_DUMMY_G7_CD, \ ++/* E */ MIU_CLIENT_DUMMY_G7_CE, \ ++/* F */ MIU_CLIENT_DUMMY_G7_CF ++ ++///////////////////////////////////////////////////////////////////////////////////////////// ++ ++#define MIU1_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_VIVALDI9_DECODER_R, \ ++/* 2 */ MIU_CLIENT_SECAU_R2_RW, \ ++/* 3 */ MIU_CLIENT_VD_R2D_RW, \ ++/* 4 */ MIU_CLIENT_SECURE_R2_RW, \ ++/* 5 */ MIU_CLIENT_VD_R2I_R, \ ++/* 6 */ MIU_CLIENT_AU_R2_RW, \ ++/* 7 */ MIU_CLIENT_DUMMY, \ ++/* 8 */ MIU_CLIENT_DUMMY, \ ++/* 9 */ MIU_CLIENT_TSP_FIQ_RW, \ ++/* A */ MIU_CLIENT_MVD_RW, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_BDMA_RW, \ ++/* D */ MIU_CLIENT_UART_DMA_RW, \ ++/* E */ MIU_CLIENT_XD2MIU_RW, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++#define MIU1_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_VIVALDI9_MAD_RW, \ ++/* 1 */ MIU_CLIENT_DUMMY, \ ++/* 2 */ MIU_CLIENT_DUMMY, \ ++/* 3 */ MIU_CLIENT_DUMMY, \ ++/* 4 */ MIU_CLIENT_DUMMY, \ ++/* 5 */ MIU_CLIENT_DUMMY, \ ++/* 6 */ MIU_CLIENT_DUMMY, \ ++/* 7 */ MIU_CLIENT_DUMMY, \ ++/* 8 */ MIU_CLIENT_SECEMAC_RW, \ ++/* 9 */ MIU_CLIENT_USB_UHC1_RW, \ ++/* A */ MIU_CLIENT_USB_UHC2_RW, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_DUMMY, \ ++/* D */ MIU_CLIENT_TSP_R, \ ++/* E */ MIU_CLIENT_TSP_PVR1_W, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++#define MIU1_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_SDIO_RW, \ ++/* 1 */ MIU_CLIENT_USB30_1_RW, \ ++/* 2 */ MIU_CLIENT_USB30_2_RW, \ ++/* 3 */ MIU_CLIENT_DUMMY, \ ++/* 4 */ MIU_CLIENT_DUMMY, \ ++/* 5 */ MIU_CLIENT_DUMMY, \ ++/* 6 */ MIU_CLIENT_MVD_RW, \ ++/* 7 */ MIU_CLIENT_JPD_RW, \ ++/* 8 */ MIU_CLIENT_GMAC_RW, \ ++/* 9 */ MIU_CLIENT_FCIE5_RW, \ ++/* A */ MIU_CLIENT_DUMMY, \ ++/* B */ MIU_CLIENT_GPD_RW, \ ++/* C */ MIU_CLIENT_DUMMY, \ ++/* D */ MIU_CLIENT_USB3_RW, \ ++/* E */ MIU_CLIENT_DUMMY, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++#define MIU1_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_DUMMY, \ ++/* 1 */ MIU_CLIENT_DUMMY, \ ++/* 2 */ MIU_CLIENT_CMD_QUEUE_RW, \ ++/* 3 */ MIU_CLIENT_USB_UHC0_RW, \ ++/* 4 */ MIU_CLIENT_DUMMY, \ ++/* 5 */ MIU_CLIENT_ZDEC_RW, \ ++/* 6 */ MIU_CLIENT_DUMMY, \ ++/* 7 */ MIU_CLIENT_ZDEC_ACP_RW, \ ++/* 8 */ MIU_CLIENT_MFE0_W, \ ++/* 9 */ MIU_CLIENT_DUMMY, \ ++/* A */ MIU_CLIENT_HVD_RW, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_DUMMY, \ ++/* D */ MIU_CLIENT_DUMMY, \ ++/* E */ MIU_CLIENT_DUMMY, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++#define MIU1_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_DUMMY, \ ++/* 1 */ MIU_CLIENT_EVD_RW, \ ++/* 2 */ MIU_CLIENT_EVD_R2D_RW, \ ++/* 3 */ MIU_CLIENT_EVD_R2I_R, \ ++/* 4 */ MIU_CLIENT_HVD_BBU_R, \ ++/* 5 */ MIU_CLIENT_3RDHVD_RW, \ ++/* 6 */ MIU_CLIENT_EVD_BBU_R, \ ++/* 7 */ MIU_CLIENT_EVD_R, \ ++/* 8 */ MIU_CLIENT_MFDEC_R, \ ++/* 9 */ MIU_CLIENT_MVD_RTO_RW, \ ++/* A */ MIU_CLIENT_DUMMY, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_SC1_IPMAIN_RW, \ ++/* D */ MIU_CLIENT_SC1_OP_R, \ ++/* E */ MIU_CLIENT_SECMFDEC_R, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++#define MIU1_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_GOP0_R, \ ++/* 1 */ MIU_CLIENT_GOP1_R, \ ++/* 2 */ MIU_CLIENT_GOP2_R, \ ++/* 3 */ MIU_CLIENT_GOP3_R, \ ++/* 4 */ MIU_CLIENT_MVOP_128BIT_R, \ ++/* 5 */ MIU_CLIENT_MVOP1_R, \ ++/* 6 */ MIU_CLIENT_FRC_IPM0_W, \ ++/* 7 */ MIU_CLIENT_SC_IPSUB_RW, \ ++/* 8 */ MIU_CLIENT_FRC_OPM0_R, \ ++/* 9 */ MIU_CLIENT_SC_DIPW_RW, \ ++/* A */ MIU_CLIENT_DUMMY, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_DUMMY, \ ++/* D */ MIU_CLIENT_DUMMY, \ ++/* E */ MIU_CLIENT_VE_W, \ ++/* F */ MIU_CLIENT_GE_RW ++ ++#define MIU1_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_DUMMY, \ ++/* 1 */ MIU_CLIENT_DUMMY, \ ++/* 2 */ MIU_CLIENT_DUMMY, \ ++/* 3 */ MIU_CLIENT_DUMMY, \ ++/* 4 */ MIU_CLIENT_DUMMY, \ ++/* 5 */ MIU_CLIENT_DUMMY, \ ++/* 6 */ MIU_CLIENT_DUMMY, \ ++/* 7 */ MIU_CLIENT_DUMMY, \ ++/* 8 */ MIU_CLIENT_DUMMY, \ ++/* 9 */ MIU_CLIENT_DUMMY, \ ++/* A */ MIU_CLIENT_DUMMY, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_DUMMY, \ ++/* D */ MIU_CLIENT_DUMMY, \ ++/* E */ MIU_CLIENT_DUMMY, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++#define MIU1_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_G3D_RW, \ ++/* 2 */ MIU_CLIENT_DUMMY, \ ++/* 3 */ MIU_CLIENT_DUMMY, \ ++/* 4 */ MIU_CLIENT_DUMMY, \ ++/* 5 */ MIU_CLIENT_DUMMY, \ ++/* 6 */ MIU_CLIENT_DUMMY, \ ++/* 7 */ MIU_CLIENT_DUMMY, \ ++/* 8 */ MIU_CLIENT_DUMMY, \ ++/* 9 */ MIU_CLIENT_DUMMY, \ ++/* A */ MIU_CLIENT_DUMMY, \ ++/* B */ MIU_CLIENT_DUMMY, \ ++/* C */ MIU_CLIENT_DUMMY, \ ++/* D */ MIU_CLIENT_DUMMY, \ ++/* E */ MIU_CLIENT_DUMMY, \ ++/* F */ MIU_CLIENT_DUMMY ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] = ++{ ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ }, ++ { ++ MIU1_CLIENT_GP0, ++ MIU1_CLIENT_GP1, ++ MIU1_CLIENT_GP2, ++ MIU1_CLIENT_GP3, ++ MIU1_CLIENT_GP4, ++ MIU1_CLIENT_GP5, ++ MIU1_CLIENT_GP6, ++ MIU1_CLIENT_GP7 ++ } ++}; ++ ++#ifdef CONFIG_MSC006A_S01A_S_UVC ++MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_USB20_P1_RW, //MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_USB30M1_HS_RW, MIU_CLIENT_USB30_1_RW, ++ MIU_CLIENT_USB30_2_RW, MIU_CLIENT_USB30_RW, ++ MIU_CLIENT_U3DEV_RW, MIU_CLIENT_MIIC0_RW, ++ MIU_CLIENT_MIIC1_RW, MIU_CLIENT_MIIC2_RW, ++ MIU_CLIENT_SDIO_RW, MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SATA1_RW, MIU_CLIENT_SATA0_RW, ++ MIU_CLIENT_FCIE5_RW//emmc ++}; ++#else //CONFIG_MSC005A_6A_S01A ++MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_USB20_P1_RW, MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_NOE_RW, MIU_CLIENT_SATA0_RW, ++ MIU_CLIENT_SATA1_RW, MIU_CLIENT_USB30M1_HS_RW, ++ MIU_CLIENT_USB30_1_RW, MIU_CLIENT_USB30_2_RW, ++ MIU_CLIENT_USB30_RW, MIU_CLIENT_EVD_ENG0_RW, ++ MIU_CLIENT_MIIC0_RW, MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_MIIC2_RW, MIU_CLIENT_GMAC_RW ++}; ++#endif ++ ++ ++EXPORT_SYMBOL(clientId_KernelProtect); ++ ++int clientId_KernelProtectToName(MS_U16 clientId,char *clientName) ++{ ++ int ret = 0; ++ if(!clientName) ++ { ++ ret = -1; ++ printk("do nothing, input wrong clientName\n"); ++ return ret; ++ } ++ switch(clientId) ++ { ++ // group 0 ++ case MIU_CLIENT_CEVAXM6_0_RW: ++ strcpy(clientName, "CEVAXM6_0_RW"); ++ break; ++ case MIU_CLIENT_CEVAXM6_1_RW: ++ strcpy(clientName, "CEVAXM6_1_RW"); ++ break; ++ case MIU_CLIENT_VD_R2I_R: ++ strcpy(clientName, "VD_R2I_R"); ++ break; ++ case MIU_CLIENT_VD_R2_SUBSYS_R: ++ strcpy(clientName, "VD_R2_SUBSYS_R"); ++ break; ++ case MIU_CLIENT_VD_R2D_RW: ++ strcpy(clientName, "VD_R2D_RW"); ++ break; ++ case MIU_CLIENT_CEVAXM6_2_RW: ++ strcpy(clientName, "CEVAXM6_2_RW"); ++ break; ++ case MIU_CLIENT_CEVAXM6_3_RW: ++ strcpy(clientName, "CEVAXM6_3_RW"); ++ break; ++ case MIU_CLIENT_AUDIO_R: ++ strcpy(clientName, "AUDIO_R"); ++ break; ++ case MIU_CLIENT_AUDIO_AU2_R: ++ strcpy(clientName, "AUDIO_AU2_R"); ++ break; ++ case MIU_CLIENT_AUDIO_AU3_W: ++ strcpy(clientName, "AUDIO_AU3_W"); ++ break; ++ case MIU_CLIENT_CMDQ_R: ++ strcpy(clientName, "CMDQ_R"); ++ break; ++ case MIU_CLIENT_XD2MIU_RW: ++ strcpy(clientName, "XD2MIU_RW"); ++ break; ++ case MIU_CLIENT_UART_DMA_RW: ++ strcpy(clientName, "UART_DMA_RW"); ++ break; ++ case MIU_CLIENT_BDMA_RW: ++ strcpy(clientName, "BDMA_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CF: ++ strcpy(clientName, "DUMMY_G0CF"); ++ break; ++ // group 1 ++ case MIU_CLIENT_SC1_CROP_LDC: ++ strcpy(clientName, "SC1_CROP_LDC"); ++ break; ++ case MIU_CLIENT_ISP_GOP1_R: ++ strcpy(clientName, "ISP_GOP1_R"); ++ break; ++ case MIU_CLIENT_CMDQ_TOP_1_R: ++ strcpy(clientName, "CMDQ_TOP_1_R"); ++ break; ++ case MIU_CLIENT_NOE_RW: ++ strcpy(clientName, "NOE_RW"); ++ break; ++ case MIU_CLIENT_USB30_RW: ++ strcpy(clientName, "USB30_RW"); ++ break; ++ case MIU_CLIENT_ISP_STA_W: ++ strcpy(clientName, "ISP_STA_W"); ++ break; ++ case MIU_CLIENT_ISP_AF_STA1_W: ++ strcpy(clientName, "ISP_AF_STA1_W"); ++ break; ++ case MIU_CLIENT_ISP_GOP2_R: ++ strcpy(clientName, "ISP_GOP2_R"); ++ break; ++ case MIU_CLIENT_EMAC_RW: ++ strcpy(clientName, "EMAC_RW"); ++ break; ++ case MIU_CLIENT_IVE_TOP_RW: ++ strcpy(clientName, "IVE_TOP_RW"); ++ break; ++ case MIU_CLIENT_ISP_GOP3_R: ++ strcpy(clientName, "ISP_GOP3_R"); ++ break; ++ case MIU_CLIENT_MIIC0_RW: ++ strcpy(clientName, "MIIC0_RW"); ++ break; ++ case MIU_CLIENT_MIIC1_RW: ++ strcpy(clientName, "MIIC1_RW"); ++ break; ++ case MIU_CLIENT_MIIC2_RW: ++ strcpy(clientName, "MIIC2_RW"); ++ break; ++ case MIU_CLIENT_ISP_SC1_DBG_R: ++ strcpy(clientName, "ISP_SC1_DBG_R"); ++ break; ++ case MIU_CLIENT_ISP_CMDQ_TOP2_R: ++ strcpy(clientName, "ISP_CMDQ_TOP2_R"); ++ break; ++ // group 2 ++ case MIU_CLIENT_SDIO_RW: ++ strcpy(clientName, "SDIO_RW"); ++ break; ++ case MIU_CLIENT_USB30_1_RW: ++ strcpy(clientName, "USB30_1_RW"); ++ break; ++ case MIU_CLIENT_USB30_2_RW: ++ strcpy(clientName, "USB30_2_RW"); ++ break; ++ case MIU_CLIENT_SD30_RW: ++ strcpy(clientName, "SD30_RW"); ++ break; ++ case MIU_CLIENT_JPE_W: ++ strcpy(clientName, "JPE_W"); ++ break; ++ case MIU_CLIENT_JPE_R: ++ strcpy(clientName, "JPE_R"); ++ break; ++ case MIU_CLIENT_U3DEV_RW: ++ strcpy(clientName, "U3DEV_RW"); ++ break; ++ case MIU_CLIENT_JPD_RW: ++ strcpy(clientName, "JPD_RW"); ++ break; ++ case MIU_CLIENT_GMAC_RW: ++ strcpy(clientName, "GMAC_RW"); ++ break; ++ case MIU_CLIENT_FCIE5_RW: ++ strcpy(clientName, "FCIE5_RW"); ++ break; ++ case MIU_CLIENT_SECGMAC: ++ strcpy(clientName, "SECGMAC"); ++ break; ++ case MIU_CLIENT_USB30M1_HS_RW: ++ strcpy(clientName, "USB30M1_HS_RW"); ++ break; ++ case MIU_CLIENT_SATA0_RW: ++ strcpy(clientName, "SATA0_RW"); ++ break; ++ case MIU_CLIENT_SATA1_RW: ++ strcpy(clientName, "SATA1_RW"); ++ break; ++ case MIU_CLIENT_USB20_RW: ++ strcpy(clientName, "USB20_RW"); ++ break; ++ case MIU_CLIENT_USB20_P1_RW: ++ strcpy(clientName, "USB20_P1_RW"); ++ break; ++ // group 3 ++ case MIU_CLIENT_ISP_GOP4_R: ++ strcpy(clientName, "ISP_GOP4_R"); ++ break; ++ case MIU_CLIENT_ISOSC_BLKS_RW: ++ strcpy(clientName, "ISOSC_BLKS_RW"); ++ break; ++ case MIU_CLIENT_CMDQ_TOP5_R: ++ strcpy(clientName, "CMDQ_TOP5_R"); ++ break; ++ case MIU_CLIENT_ISP_GOP0_R: ++ strcpy(clientName, "ISP_GOP0_R"); ++ break; ++ case MIU_CLIENT_SC1_FRAME_W: ++ strcpy(clientName, "SC1_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC1_SNAPSHOT_W: ++ strcpy(clientName, "SC1_SNAPSHOT_W"); ++ break; ++ case MIU_CLIENT_SC2_FRAME_W: ++ strcpy(clientName, "SC2_FRAME_W"); ++ break; ++ case MIU_CLIENT_CMDQ_TOP4_R: ++ strcpy(clientName, "CMDQ_TOP4_R"); ++ break; ++ case MIU_CLIENT_MFE0_R: ++ strcpy(clientName, "MFE0_R"); ++ break; ++ case MIU_CLIENT_MFE0_W: ++ strcpy(clientName, "MFE0_W"); ++ break; ++ case MIU_CLIENT_SC3_FRAME_RW: ++ strcpy(clientName, "SC3_FRAME_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G3CB: ++ strcpy(clientName, "DUMMY_G3CB"); ++ break; ++ case MIU_CLIENT_DUMMY_G3CC: ++ strcpy(clientName, "DUMMY_G3CC"); ++ break; ++ case MIU_CLIENT_MFE1_R: ++ strcpy(clientName, "MFE1_R"); ++ break; ++ case MIU_CLIENT_MFE1_W: ++ strcpy(clientName, "MFE1_W"); ++ break; ++ case MIU_CLIENT_ISP_MLOAD_R: ++ strcpy(clientName, "ISP_MLOAD_R"); ++ break; ++ // group 4 ++ case MIU_CLIENT_VE_W: ++ strcpy(clientName, "VE_W"); ++ ++ case MIU_CLIENT_EVD_ENG1_RW: ++ strcpy(clientName, "EVD_ENG1_RW"); ++ break; ++ case MIU_CLIENT_MGWIN0_R: ++ strcpy(clientName, "MGWIN0_R"); ++ break; ++ case MIU_CLIENT_MGWIN1_R: ++ strcpy(clientName, "MGWIN1_R"); ++ break; ++ case MIU_CLIENT_HVD_RW: ++ strcpy(clientName, "HVD_RW"); ++ break; ++ case MIU_CLIENT_HVD1_RW: ++ strcpy(clientName, "HVD1_RW"); ++ break; ++ case MIU_CLIENT_DDI_0_RW: ++ strcpy(clientName, "DDI_0_RW"); ++ break; ++ case MIU_CLIENT_EVD_ENG0_RW: ++ strcpy(clientName, "EVD_ENG0_RW"); ++ break; ++ case MIU_CLIENT_MFDEC0_1_R: ++ strcpy(clientName, "MFDEC0_1_R"); ++ break; ++ case MIU_CLIENT_ISPSC_DMAG: ++ strcpy(clientName, "ISPSC_DMAG"); ++ break; ++ case MIU_CLIENT_EVD_BBU_R: ++ strcpy(clientName, "EVD_BBU_R"); ++ break; ++ case MIU_CLIENT_HVD_BBU_R: ++ strcpy(clientName, "HVD_BBU_R"); ++ break; ++ case MIU_CLIENT_SC1_IPMAIN_RW: ++ strcpy(clientName, "SC1_IPMAIN_RW"); ++ break; ++ case MIU_CLIENT_SC1_OPM_R: ++ strcpy(clientName, "SC1_OPM_R"); ++ break; ++ case MIU_CLIENT_MFDEC_1_1_R: ++ strcpy(clientName, "MFDEC_1_1_R"); ++ break; ++ case MIU_CLIENT_LDC_R: ++ strcpy(clientName, "LDC_R"); ++ break; ++ // group 5 ++ case MIU_CLIENT_GOP0_R: ++ strcpy(clientName, "GOP0_R"); ++ break; ++ case MIU_CLIENT_GOP1_R: ++ strcpy(clientName, "GOP1_R"); ++ break; ++ case MIU_CLIENT_AUTO_DOWNLOAD_R: ++ strcpy(clientName, "AUTO_DOWNLOAD_R"); ++ break; ++ case MIU_CLIENT_SC_DIPW_RW: ++ strcpy(clientName, "SC_DIPW_RW"); ++ break; ++ case MIU_CLIENT_MVOP_128BIT_R: ++ strcpy(clientName, "MVOP_128BIT_R"); ++ break; ++ case MIU_CLIENT_MVOP1_R: ++ strcpy(clientName, "MVOP1_R"); ++ break; ++ case MIU_CLIENT_FRC_IPM0_W: ++ strcpy(clientName, "FRC_IPM0_W"); ++ break; ++ case MIU_CLIENT_SC_IPSUB_RW: ++ strcpy(clientName, "SC_IPSUB_RW"); ++ break; ++ case MIU_CLIENT_FRC_OPM0_R: ++ strcpy(clientName, "FRC_OPM0_R"); ++ break; ++ case MIU_CLIENT_MDWIN0_W: ++ strcpy(clientName, "MDWIN0_W"); ++ break; ++ case MIU_CLIENT_MFDEC0_R: ++ strcpy(clientName, "MFDEC0_R"); ++ break; ++ case MIU_CLIENT_MFDEC1_R: ++ strcpy(clientName, "MFDEC1_R"); ++ break; ++ case MIU_CLIENT_MDWIN1_W: ++ strcpy(clientName, "MDWIN1_W"); ++ break; ++ case MIU_CLIENT_SC_DYN_SCL_R: ++ strcpy(clientName, "SC_DYN_SCL_R"); ++ break; ++ case MIU_CLIENT_VE_R: ++ strcpy(clientName, "VE_R"); ++ break; ++ case MIU_CLIENT_GE_RW: ++ strcpy(clientName, "GE_RW"); ++ break; ++ // group 6 ++ case MIU_CLIENT_ISP_DMAG0_W: ++ strcpy(clientName, "ISP_DMAG0_W"); ++ break; ++ case MIU_CLIENT_ISP_DMAG0_R: ++ strcpy(clientName, "ISP_DMAG0_R"); ++ break; ++ case MIU_CLIENT_ISP_DMAG1_W: ++ strcpy(clientName, "ISP_DMAG1_W"); ++ break; ++ case MIU_CLIENT_ISP_DMAG1_R: ++ strcpy(clientName, "ISP_DMAG1_R"); ++ break; ++ case MIU_CLIENT_ISP_DMAG2_RW: ++ strcpy(clientName, "ISP_DMAG2_RW"); ++ break; ++ case MIU_CLIENT_ISP_DMAG3_RW: ++ strcpy(clientName, "ISP_DMAG3_RW"); ++ break; ++ case MIU_CLIENT_ISP_DMAG4_W: ++ strcpy(clientName, "ISP_DMAG4_W"); ++ break; ++ case MIU_CLIENT_ISP_DMAG4_R: ++ strcpy(clientName, "ISP_DMAG4_R"); ++ break; ++ case MIU_CLIENT_ISP_DMAG_RW: ++ strcpy(clientName, "ISP_DMAG_RW"); ++ break; ++ case MIU_CLIENT_DMA_GENERAL_RW: ++ strcpy(clientName, "DMA_GENERAL_RW"); ++ break; ++ case MIU_CLIENT_SC1_DNR_RW: ++ strcpy(clientName, "SC1_DNR_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G6CB: ++ strcpy(clientName, "DUMMY_G6CB"); ++ break; ++ case MIU_CLIENT_MHE0_R: ++ strcpy(clientName, "MHE0_R"); ++ break; ++ case MIU_CLIENT_MHE0_W: ++ strcpy(clientName, "MHE0_W"); ++ break; ++ case MIU_CLIENT_MHE1_R: ++ strcpy(clientName, "MHE1_R"); ++ break; ++ case MIU_CLIENT_MHE1_W: ++ strcpy(clientName, "MHE1_W"); ++ break; ++ // group 7 ++ case MIU_CLIENT_MIPS_RW: //ARM CPU ++ strcpy(clientName, "MIPS_RW"); ++ break; ++ case MIU_CLIENT_G3D_RW: ++ strcpy(clientName, "G3D_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C2: ++ strcpy(clientName, "DUMMY_G7_C2"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C3: ++ strcpy(clientName, "DUMMY_G7_C3"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C4: ++ strcpy(clientName, "DUMMY_G7_C4"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C5: ++ strcpy(clientName, "DUMMY_G7_C5"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C6: ++ strcpy(clientName, "DUMMY_G7_C6"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C7: ++ strcpy(clientName, "DUMMY_G7_C7"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C8: ++ strcpy(clientName, "DUMMY_G7_C8"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_C9: ++ strcpy(clientName, "DUMMY_G7_C9"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_CA: ++ strcpy(clientName, "DUMMY_G7_CA"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_CB: ++ strcpy(clientName, "DUMMY_G7_CB"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_CC: ++ strcpy(clientName, "DUMMY_G7_CC"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_CD: ++ strcpy(clientName, "DUMMY_G7_CD"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_CE: ++ strcpy(clientName, "DUMMY_G7_CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G7_CF: ++ strcpy(clientName, "DUMMY_G7_CF"); ++ break; ++ default: ++ printk("do nothing,may input wrong clientId\n"); ++ ret = -1; ++ break; ++ } ++ return ret; ++} ++EXPORT_SYMBOL(clientId_KernelProtectToName); ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_CHIP_MIU_0 = 0, ++ E_CHIP_MIU_1, ++ E_CHIP_MIU_2, ++ E_CHIP_MIU_3, ++ E_CHIP_MIU_NUM, ++} CHIP_MIU_ID; ++ ++//------------------------------------------------------------------------------------------------- ++// Macros ++//------------------------------------------------------------------------------------------------- ++#define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < ARM_MIU1_BASE_ADDR) \ ++ {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ ++ else if ((PhysAddr >= ARM_MIU1_BASE_ADDR) && (PhysAddr < ARM_MIU2_BASE_ADDR)) \ ++ {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - ARM_MIU2_BASE_ADDR;} ++ ++#define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ ++ {PhysAddr = Offset;} \ ++ else if (MiuSel == E_CHIP_MIU_1) \ ++ {PhysAddr = Offset + ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {PhysAddr = Offset + ARM_MIU2_BASE_ADDR;} ++ ++#define MIU_HAL_ERR(fmt, args...) printk(KERN_ERR "miu hal error %s:%d" fmt,__FUNCTION__,__LINE__,## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++//static MS_U32 _gMIU_MapBase = 0xBF200000; //default set to MIPS platfrom ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++static MS_U32 _gMIU_MapBase = 0xFD200000UL; //default set to arm 32bit platfrom ++#elif defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++static ptrdiff_t _gMIU_MapBase; ++#endif ++ ++#if 0 ++MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}, {{0},{0},{0},{0}}, {{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++MS_U8 IDs[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}, {0}, {0}}; //IDs for protection ++#else ++MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}, {{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++MS_U16 IDs[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}, {0}}; //IDs for protection ++#endif ++MS_BOOL HAL_MIU_Get_IDEnables_Value(MS_U8 u8MiuDev, MS_U8 u8MiuBlockId, MS_U8 u8ProtectIdIndex) ++{ ++ return IDEnables[u8MiuDev][u8MiuBlockId][u8ProtectIdIndex]; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// MTLB HAL internal function ++//------------------------------------------------------------------------------------------------- ++MS_U32 HAL_MIU_BA2PA(MS_U32 u32BusAddr) ++{ ++ MS_U32 u32PhyAddr = 0x0UL; ++ ++ // pa = ba - offset ++ if( (u32BusAddr >= ARM_MIU0_BUS_BASE) && (u32BusAddr < ARM_MIU1_BUS_BASE) ) // MIU0 ++ u32PhyAddr = u32BusAddr - ARM_MIU0_BUS_BASE + ARM_MIU0_BASE_ADDR; ++ else if( (u32BusAddr >= ARM_MIU1_BUS_BASE) && (u32BusAddr < ARM_MIU2_BUS_BASE)) // MIU1 ++ u32PhyAddr = u32BusAddr - ARM_MIU1_BUS_BASE + ARM_MIU1_BASE_ADDR; ++ else ++ u32PhyAddr = u32BusAddr - ARM_MIU2_BUS_BASE + ARM_MIU2_BASE_ADDR; // MIU2 ++ ++ return u32PhyAddr; ++} ++ ++MS_S16 HAL_MIU_GetClientInfo(MS_U8 u8MiuDev, eMIUClientID eClientID) ++{ ++ MS_U8 idx; ++ ++ if (MIU_MAX_DEVICE <= u8MiuDev) ++ { ++ MIU_HAL_ERR("Wrong MIU device:%u\n", u8MiuDev); ++ return (-1); ++ } ++ ++ for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++) ++ if (eClientID == clientTbl[u8MiuDev][idx]) ++ return idx; ++ return (-1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b MS_U8 ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegAddr) ++{ ++#if defined(CONFIG_ARM64) ++ _gMIU_MapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b MS_U16 ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegAddr) ++{ ++#if defined(CONFIG_ARM64) ++ _gMIU_MapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr]; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b MS_U32 ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_U32 HAL_MIU_Read4Byte(MS_U32 u32RegAddr) ++{ ++ return (HAL_MIU_Read2Byte(u32RegAddr) | HAL_MIU_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE: Ok FALSE: Fail ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val) ++{ ++ if (!u32RegAddr) ++ { ++ MIU_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ _gMIU_MapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE: Ok FALSE: Fail ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ MIU_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ _gMIU_MapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr] = u16Val; ++ return TRUE; ++} ++ ++void HAL_MIU_SetProtectID(MS_U32 u32Reg, MS_U8 u8MiuDev, MS_U16 u8ClientID) ++{ ++ MS_S16 sVal = HAL_MIU_GetClientInfo(u8MiuDev, (eMIUClientID)u8ClientID); ++ MS_S16 sIDVal; ++ ++ if (0 > sVal) ++ sVal = 0; ++ ++ sIDVal = HAL_MIU_ReadByte(u32Reg); ++ sIDVal &= 0x80; ++ sIDVal |= sVal; ++ HAL_MIU_WriteByte(u32Reg, sIDVal); ++} ++ ++MS_BOOL HAL_MIU_WriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(u32RegAddr); ++ if (!u32RegAddr) ++ { ++ MIU_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ u8Val = HAL_MIU_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_MIU_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U16 u16ID; ++ MS_U8 u8isfound0, u8isfound1; ++ MS_U16 u16idenable; ++ ++ //reset IDenables for protect u8Blockx ++ for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u16ID = pu8ProtectId[u32index0]; ++ ++ //Unused ID ++ if(u16ID == 0) ++ continue; ++ ++ u8isfound0 = FALSE; ++ ++ for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if(IDs[u8MiuSel][u32index1] == u16ID) ++ { ++ //ID reused former setting ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound0 = TRUE; ++ break; ++ } ++ } ++ ++ //Need to create new ID in IDs ++ if(u8isfound0 != TRUE) ++ { ++ u8isfound1 = FALSE; ++ ++ for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if(IDs[u8MiuSel][u32index1] == 0) ++ { ++ IDs[u8MiuSel][u32index1] = u16ID; ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound1 = TRUE; ++ break; ++ } ++ } ++ ++ //ID overflow ++ if(u8isfound1 == FALSE) ++ return FALSE; ++ } ++ } ++ ++ u16idenable = 0; ++ ++ for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ if(IDEnables[u8MiuSel][u8Blockx][u32index0] == 1) ++ u16idenable |= (1<bHit = TRUE; ++ pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(ret); ++ pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(ret) >> 4); ++ pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(ret) & 0x0F); ++ pInfo->uAddress = (MS_U32)((hiaddr << 16) | loaddr) ; ++ pInfo->uAddress = pInfo->uAddress * MIU_PROTECT_ADDRESS_UNIT; ++ pInfo->u16ProtectType = HAL_MIU_Read2Byte(u32Reg + REG_MIU_PROTECT_ENGINE); ++ u32endAddr = (pInfo->uAddress + MIU_PROTECT_ADDRESS_UNIT - 1); ++ clientId_KernelProtectToName((MS_U8)(GET_HIT_CLIENT(ret)), clientName); ++ ++ if(pInfo->u8Block == 7) ++ { ++ printk(KERN_ERR "MIU%u OutofArea[W] Client:%s ID:%u-%u Hitted_Address(MIU):0x%x<->0x%x\n", ++ u8MiuDev, clientName, pInfo->u8Group, pInfo->u8ClientID, pInfo->uAddress, u32endAddr); ++ } ++ else if(pInfo->u8Block == 6) ++ { ++ printk(KERN_ERR "MIU%u OutofArea[R] Client:%s ID:%u-%u Hitted_Address(MIU):0x%x<->0x%x\n", ++ u8MiuDev, clientName, pInfo->u8Group, pInfo->u8ClientID, pInfo->uAddress, u32endAddr); ++ } ++ else ++ { ++ printk(KERN_ERR "MIU%u Block:%u Client:%s ID:%u-%u Hitted_Address(MIU):0x%x<->0x%x Type(0x69): 0x%x:\n", ++ u8MiuDev, pInfo->u8Block,clientName, pInfo->u8Group, pInfo->u8ClientID, pInfo->uAddress, u32endAddr, pInfo->u16ProtectType); ++ } ++ ++ //clear log ++ HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR); ++ HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR); ++ ++ } ++ ++ return TRUE; ++} ++//#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* HAL_MIU_GetDefaultClientID_KernelProtect() ++{ ++ if(IDNUM_KERNELPROTECT > 0) ++ return (MS_U16 *)&clientId_KernelProtect[0]; ++ ++ return NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting bus address ++/// @param u32End \b IN : End bus address ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Protect( ++ MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ PROTECT_CTRL eSetFlag ++ ) ++{ ++ MS_U32 u32RegAddr; ++ MS_U32 u32Reg; ++ MS_U32 u32RegAddrStar; ++ MS_U32 u32RegAddrMSB; ++ MS_U32 u32RegAddrIDenable; ++ MS_U32 u32MiuProtectEn; ++ MS_U32 u32StartOffset; ++ MS_U32 u32EndOffset; ++ MS_U16 u16Data; ++ MS_U16 u16Data1; ++ MS_U16 u16Data2; ++ MS_U8 u8Data; ++ MS_U8 u8MiuSel; ++ MS_U32 u32Start, u32End; ++ ++ u32Start = HAL_MIU_BA2PA(u32BusStart); ++ u32End = HAL_MIU_BA2PA(u32BusEnd); ++ ++ // Get MIU selection and offset ++ _phy_to_miu_offset(u8MiuSel, u32EndOffset, u32End); ++ _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32Start); ++ ++ u32Start = u32StartOffset; ++ u32End = u32EndOffset; ++ ++ // Incorrect Block ID ++ if(u8Blockx >= E_MIU_BLOCK_NUM) ++ { ++ MIU_HAL_ERR("Err: Out of the number of protect device\n"); ++ return FALSE; ++ } ++ else if(((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0)) ++ { ++ MIU_HAL_ERR("Err: Protected address should be aligned to 8KB\n"); ++ return FALSE; ++ } ++ else if(u32Start >= u32End) ++ { ++ MIU_HAL_ERR("Err: Start address is equal to or more than end address\n"); ++ return FALSE; ++ } ++ ++ //write_enable ++ u8Data = 1 << u8Blockx; ++ ++ if(u8MiuSel == E_CHIP_MIU_0) ++ { ++ u32RegAddrMSB = MIU_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ ++ u32RegAddr = MIU_PROTECT0_ID0; ++ u32MiuProtectEn=MIU_PROTECT_EN_INTERNAL; ++ u32Reg = MIU_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegAddrStar = MIU_PROTECT0_START; ++ u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegAddrStar = MIU_PROTECT1_START; ++ u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegAddrStar = MIU_PROTECT2_START; ++ u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegAddrStar = MIU_PROTECT3_START; ++ u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if(u8MiuSel == E_CHIP_MIU_1) ++ { ++ u32RegAddrMSB = MIU1_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ ++ u32RegAddr = MIU1_PROTECT0_ID0; ++ u32MiuProtectEn=MIU1_PROTECT_EN; ++ u32Reg = MIU1_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegAddrStar = MIU1_PROTECT0_START; ++ u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegAddrStar = MIU1_PROTECT1_START; ++ u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegAddrStar = MIU1_PROTECT2_START; ++ u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegAddrStar = MIU1_PROTECT3_START; ++ u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if(u8MiuSel == E_CHIP_MIU_2) ++ { ++ u32RegAddrMSB = MIU2_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ ++ u32RegAddr = MIU2_PROTECT0_ID0; ++ u32MiuProtectEn=MIU2_PROTECT_EN; ++ u32Reg = MIU2_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegAddrStar = MIU2_PROTECT0_START; ++ u32RegAddrIDenable = MIU2_PROTECT0_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegAddrStar = MIU2_PROTECT1_START; ++ u32RegAddrIDenable = MIU2_PROTECT1_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegAddrStar = MIU2_PROTECT2_START; ++ u32RegAddrIDenable = MIU2_PROTECT2_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegAddrStar = MIU2_PROTECT3_START; ++ u32RegAddrIDenable = MIU2_PROTECT3_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ // Disable MIU protect ++ HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data, DISABLE); //write disable ++ HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data << 4, DISABLE); //read disable ++ HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data << 8, DISABLE); //invert disable ++ ++ if ( eSetFlag ) ++ { ++ // Set Protect IDs ++ if(HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable) == FALSE) ++ { ++ return FALSE; ++ } ++ ++ // Set BIT29,30 of start/end address ++ u16Data2 = u16Data2 | (MS_U16)((u32Start >> 29) << (u8Blockx*4)); // u16Data2 for start_ext addr ++ u16Data1 = u16Data2 | (MS_U16)(((u32End - 1) >> 29) << (u8Blockx*4+2)); ++ HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1); ++ ++ // Start Address ++ u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); //8k/unit ++ HAL_MIU_Write2Byte(u32RegAddrStar , u16Data); ++ ++ // End Address ++ u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); //8k/unit; ++ HAL_MIU_Write2Byte(u32RegAddrStar + 2, u16Data); ++ ++ // Enable MIU protect ++ if(eSetFlag == W_EN) ++ { ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE); //write ++ } ++ else if(eSetFlag == R_EN) ++ { ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data << 4, ENABLE); //read ++ } ++ else if(eSetFlag == WR_EN) ++ { ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE); //write ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data << 4, ENABLE); //read ++ } ++ else if(eSetFlag == W_EN_INVERT) ++ { ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE); //write ++ HAL_MIU_WriteRegBit(u32MiuProtectEn+1, u8Data, ENABLE); //invert ++ } ++ else if(eSetFlag == R_EN_INVERT) ++ { ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data << 4, ENABLE); //read ++ HAL_MIU_WriteRegBit(u32MiuProtectEn+1, u8Data, ENABLE); //invert ++ } ++ else if(eSetFlag == WR_EN_INVERT) ++ { ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE); //write ++ HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data << 4, ENABLE); //read ++ HAL_MIU_WriteRegBit(u32MiuProtectEn+1, u8Data, ENABLE); //invert ++ } ++ else ++ printk(KERN_ERR"[miu protect] invalid operation !!\n"); ++ } ++ else ++ { ++ // Reset Protect IDs ++ HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable); ++ } ++ ++ // clear log ++ HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR); ++ HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource ++/// @brief \b Function \b Description: Parse occupied resource to software structure ++/// @return \b 0: Fail 1: OK ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) ++{ ++ MS_U8 u8MiuSel; ++ MS_U8 u8Blockx; ++ MS_U8 u8ClientID; ++ MS_U16 u16idenable; ++ MS_U32 u32index; ++ MS_U32 u32RegAddr; ++ MS_U32 u32RegAddrIDenable; ++ ++ for(u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ { ++ if(u8MiuSel == E_MIU_0) ++ { ++ u32RegAddr = MIU_PROTECT0_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE; ++ break; ++ default: ++ return false; ++ } ++ } ++ else if(u8MiuSel == E_MIU_1) ++ { ++ u32RegAddr = MIU1_PROTECT0_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE; ++ break; ++ default: ++ return false; ++ } ++ } ++ else if(u8MiuSel == E_MIU_2) ++ { ++ u32RegAddr = MIU2_PROTECT0_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegAddrIDenable = MIU2_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegAddrIDenable = MIU2_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegAddrIDenable = MIU2_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegAddrIDenable = MIU2_PROTECT3_ID_ENABLE; ++ break; ++ default: ++ return false; ++ } ++ } ++ else ++ { ++ printk(KERN_ERR "%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ u16idenable = HAL_MIU_Read2Byte(u32RegAddrIDenable); ++ for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16idenable >> u32index) & 0x1UL)? 1: 0; ++ } ++ }//for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ ++ for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ u8ClientID = HAL_MIU_ReadByte(u32RegAddr + u32index) & 0x7F; ++ IDs[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID]; ++ } ++ }//for(u8MiuSel = E_MIU_0; u8MiuSel < E_MIU_NUM; u8MiuSel++) ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_Protect_Save(void) ++{ ++ return TRUE; ++} ++ ++MS_BOOL HAL_Protect_Restore(void) ++{ ++ return TRUE; ++} ++ ++unsigned int HAL_MIU_ProtectDramSize(void) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(MIU_PROTECT_DDR_SIZE); ++ u8Val = (u8Val >> 4) & 0xF; ++ ++ if (0 == u8Val) ++ { ++ printk("[%s][%d] MIU protect DRAM size is undefined. Using 0x40000000 as default\n", __FUNCTION__, __LINE__); ++ return 0x40000000; ++ } ++ return (0x1 << (20 + u8Val)); ++} ++ ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ printk("Not support HAL_MIU_Info in this platform\n"); ++ ++ return -1; ++} ++ ++//// porting from k6 utopia ++#define HAL_MIU_SSC_DBG(x) // x ++// #define MIU_HAL_ERR(x, args...) {printf(x, ##args);} ++#ifndef printf ++#define printf printk ++#endif ++ ++#define MPPL (432) ++#define DDR_FACTOR (524288) ++#define DDFSPAN_FACTOR (131072) ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_SetSsc() ++/// @brief \b Function \b Description: MDrv_MIU_SetSsc, @Step & Span ++/// @param u16Fmodulation \b IN : 20KHz ~ 40KHz (Input Value = 20 ~ 40) ++/// @param u16FDeviation \b IN : under 0.1% ~ 2% (Input Value = 1 ~ 20) ++/// @param bEnable \b IN : ++/// @param None \b OUT : ++/// @param None \b RET : ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_SetSsc(MS_U8 u8MiuDev, MS_U16 u16Fmodulation, MS_U16 u16FDeviation, MS_BOOL bEnable) ++{ ++ MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE; ++ MS_U16 u16DDFSpan; ++ MS_U16 u16Input_DIV_First,u16Input_DIV_Second,u16Loop_DIV_First,u16Loop_DIV_Second; ++ MS_U8 u8Temp,i; ++ ++ //Pre check the input ++ if (u8MiuDev == 1) ++ { ++#if 0 ++ if((HAL_MIU_Read2Byte(MIU1_REG_BASE)&BIT15)) ++ { ++ uRegBase = MIU_ATOP_BASE+0x80; ++ } ++ else ++ { ++ printf("there is no MIU1\n"); ++ return 0; ++ } ++#else ++ printf("there is no MIU1\n"); ++ return FALSE; ++#endif ++ } ++ else ++ { ++ uRegBase = MIU_ATOP_BASE; ++ } ++ HAL_MIU_SSC_DBG(printf("MMIO base:%lx uRegBase:%lx\n", _gMIU_MapBase, uRegBase)); ++ ++ if ((u16Fmodulation<20)||(u16Fmodulation>40)) ++ { ++ MIU_HAL_ERR("SSC u16Fmodulation Error...(20KHz - 40KHz)\n"); ++ return 0; ++ } ++ ++ if ((u16FDeviation<1)||(u16FDeviation>20)) ++ { ++ MIU_HAL_ERR("SSC u16FDeviation Error...(0.1%% - 2%% ==> 1 ~20)\n"); ++ return 0; ++ } ++ ++ HAL_MIU_SSC_DBG(printf("---> u16Fmodulation = %d u16FDeviation = %d \n",(int)u16Fmodulation,(int)u16FDeviation)); ++ //<1>.Caculate DDFM = (Loop_DIV_First * Loop_DIV_Second)/(Input_DIV_First * Input_DIV_Second); ++ //Prepare Input_DIV_First ++ u8Temp = ((MS_U16)(HAL_MIU_Read2Byte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0x30)>>4); //Bit 13,12 (0x110D36) ++ u16Input_DIV_First = 0x01; ++ for (i=0;i>6); //Bit 15,14 (0x110D36) ++ u16Loop_DIV_First = 0x01; ++ for (i=0;i.From DDFSET register to get DDRPLL ++ uDDFSET = HAL_MIU_Read4Byte(uRegBase+MIU_DDFSET) & 0x00ffffff; ++ //DDRPLL = MPPL * DDR_FACTOR * Loop_First * Loop_Second / DDFSET * Input_First * Input_Second ++ HAL_MIU_SSC_DBG(printf("---> Loop_First:%u Loop_Second:%u\n", u16Loop_DIV_First, u16Loop_DIV_Second)); ++ HAL_MIU_SSC_DBG(printf("---> Input_first:%u Input_second:%u\n", u16Input_DIV_First, u16Input_DIV_Second)); ++ uDDR_MHz = (MPPL * DDR_FACTOR * u16Loop_DIV_First * u16Loop_DIV_Second)/ (uDDFSET*u16Input_DIV_First*u16Input_DIV_Second); ++ HAL_MIU_SSC_DBG(printf("---> uDDFSET = 0x%lx\n",uDDFSET)); ++ HAL_MIU_SSC_DBG(printf("---> DDR_MHZ = 0x%lx (%d MHz)\n",uDDR_MHz,(int)uDDR_MHz)); ++ ++ //<3>.Caculate DDFSPAN = (MPLL * DDFSPAN_FACTOR * MHz) / (DDFSET * Fmodulation * KHz) ++ u16DDFSpan = (MS_U32)((DDFSPAN_FACTOR * MPPL/u16Fmodulation)* 1000/uDDFSET); ++ HAL_MIU_SSC_DBG(printf("---> DDFSPAN = 0x%x (%d)\n",u16DDFSpan,(int)u16DDFSpan)); ++ if (u16DDFSpan > 0x3FFF) ++ { ++ u16DDFSpan = 0x3FFF; ++ HAL_MIU_SSC_DBG(printf("??? DDFSPAN overflow > 0x3FFF, Fource set to 0x03FF\n")); ++ } ++ ++ //Write to Register ++ HAL_MIU_Write2Byte(uRegBase+MIU_DDFSPAN,u16DDFSpan); ++ //<4>.Caculate DDFSTEP = (FDeviation*DDFSET/10)/(DDFSPAN*100) ++ uDDFStep = (MS_U32)((u16FDeviation * (uDDFSET/10))/(u16DDFSpan*100)); ++ HAL_MIU_SSC_DBG(printf("---> DDFSTEP = 0x%lx (%lu)\n",uDDFStep,uDDFStep)); ++ //Write to Register ++ uDDFStep &= (0x03FF); ++ HAL_MIU_Write2Byte(uRegBase+MIU_DDFSTEP,(HAL_MIU_Read2Byte(uRegBase+MIU_DDFSTEP) & (~0x03FF))|uDDFStep); ++ ++ //<5>.Set ENABLE ++ if(bEnable == ENABLE) ++ { ++ HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)|0xC0)); ++ } ++ else ++ { ++ HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)&(~0xC0))|0x80); ++ } ++ return 1; ++} +diff --git a/drivers/sstar/miu/infinity2m/mdrv_miu.c b/drivers/sstar/miu/infinity2m/mdrv_miu.c +new file mode 100755 +index 000000000000..8cfd1decd4cf +--- /dev/null ++++ b/drivers/sstar/miu/infinity2m/mdrv_miu.c +@@ -0,0 +1,598 @@ ++/* ++* mdrv_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "MsTypes.h" ++#include "mdrv_miu.h" ++#include "mhal_miu.h" ++#include "regMIU.h" ++#include "ms_platform.h" ++#include ++#include "irqs.h" ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_MSTAR_MONET) || defined(CONFIG_MSTAR_MESSI) || defined(CONFIG_MSTAR_MASERATI) || defined(CONFIG_MSTAR_MANHATTAN) || defined(CONFIG_MSTAR_KANO) ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY phy64Start, MS_PHY phy64End, MS_BOOL bSetFlag) __attribute__((weak)); ++#else ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, MS_U32 u32BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++#endif ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) __attribute__((weak)); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) __attribute__((weak)); ++ ++MS_BOOL HAL_MIU_SlitInit(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SetSlitRange(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY u64BusStart, MS_PHY u64BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++MS_BOOL HAL_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++ ++#ifndef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static struct timer_list monitor_timer; ++#endif ++static int bMiuProtect_is_initialized = 0; ++ ++static DEFINE_SPINLOCK(miu_lock); ++MS_U8 u8_MiuWhiteListNum = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Local functions ++//------------------------------------------------------------------------------------------------- ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Init ++/// @brief \b Function \b Description: parse occupied resource to software structure ++/// @param None \b IN : ++/// @param None \b OUT : ++/// @param MS_BOOL \b RET ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Init(void) ++{ ++ MS_BOOL ret = FALSE; ++ ++ /* Parse the used client ID in hardware into software data structure */ ++ if (HAL_MIU_ParseOccupiedResource) { ++ ret = HAL_MIU_ParseOccupiedResource(); ++ } ++ else { ++ ret = FALSE; ++ } ++ ++ /* Initialize MIU slit setting */ ++ if (HAL_MIU_SlitInit) { ++ ret = HAL_MIU_SlitInit(); ++ } ++ ++ u8_MiuWhiteListNum = IDNUM_KERNELPROTECT; ++ ++ return ret; ++} ++ ++MS_BOOL MDrv_MIU_GetProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ return HAL_MIU_GetHitProtectInfo(u8MiuSel, pInfo); ++} ++ ++MS_BOOL MDrv_MIU_Get_IDEnables_Value(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 u8ClientIndex) ++{ ++ return HAL_MIU_GetProtectIdEnVal(u8MiuSel, u8Blockx, u8ClientIndex); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* MDrv_MIU_GetDefaultClientID_KernelProtect(void) ++{ ++ if (HAL_MIU_GetDefaultKernelProtectClientID) { ++ return HAL_MIU_GetDefaultKernelProtectClientID(); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++MS_U16* MDrv_MIU_GetClientID_KernelProtect(MS_U8 u8MiuSel) ++{ ++ if (HAL_MIU_GetKernelProtectClientID) { ++ return HAL_MIU_GetKernelProtectClientID(u8MiuSel); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static irqreturn_t MDrv_MIU_Protect_interrupt(s32 irq, void *dev_id) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo pInfo; ++ ++ memset(&pInfo, 0 , sizeof(pInfo)); ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &pInfo); ++ if (pInfo.bHit) ++ BUG(); ++ return IRQ_HANDLED; ++} ++#else ++//create timer process ++static void MDev_timer_callback(unsigned long value) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo stProtInfo; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) { ++ stProtInfo.bHit = FALSE; ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &stProtInfo); ++ if (stProtInfo.bHit) { ++ panic("MIU %d Protect hit!\n", u8MiuSel); ++ } ++ } ++ mod_timer(&monitor_timer, jiffies+1*HZ); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 3) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_PHY u64BusStart, ++ MS_PHY u64BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_BOOL Result = FALSE; ++ ++ /* Case of former MIU protect */ ++ if ((u8Blockx >= E_PROTECT_0) && (u8Blockx < E_SLIT_0)) ++ { ++ if (HAL_MIU_Protect) { ++ if (TRUE != (Result = HAL_MIU_Protect(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ /* Case of MIU slits */ ++ else if (u8Blockx == E_SLIT_0) ++ { ++ if (HAL_MIU_SetSlitRange) { ++ if (TRUE != (Result = HAL_MIU_SetSlitRange(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ ++ ++ if(!bMiuProtect_is_initialized) ++ { ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ struct device_node *dev_node = NULL; ++ int rc = 0; ++ int iIrqNum = 0; ++ dev_node = of_find_compatible_node(NULL, NULL, "sstar,miu"); ++ if (!dev_node) ++ { ++ printk("[MIU Protecrt] find node Fail\r\n"); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ if(0 != (rc = request_irq(iIrqNum, MDrv_MIU_Protect_interrupt, IRQF_TRIGGER_HIGH, "MIU_Protect", NULL))) ++ { ++ printk("[MIU Protecrt] request_irq [%d] Fail, Err:%d\r\n", iIrqNum, rc); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++#else ++ init_timer(&monitor_timer); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++#endif ++ bMiuProtect_is_initialized++; ++ } ++ ++ ++MDrv_MIU_Protect_Exit: ++ return Result; ++} ++ ++unsigned int MDrv_MIU_ProtectDramSize(void) ++{ ++ return HAL_MIU_ProtectDramSize(); ++} ++ ++int MDrv_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++ ++MS_BOOL MDrv_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) ++{ ++ unsigned long flags; ++ MS_BOOL Result = FALSE; ++ ++ spin_lock_irqsave(&miu_lock, flags); ++ ++ if (HAL_MIU_Slits) { ++ Result = HAL_MIU_Slits(u8Blockx, u64SlitsStart, u64SlitsEnd, bSetFlag); ++ } ++ ++ spin_unlock_irqrestore(&miu_lock, flags); ++ ++ return Result; ++} ++ ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo) ++{ ++ return HAL_MIU_Info((MIU_DramInfo_Hal *)pDramInfo); ++} ++ ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(MDrv_MIU_Init); ++EXPORT_SYMBOL(u8_MiuWhiteListNum); ++EXPORT_SYMBOL(MDrv_MIU_GetDefaultClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_GetClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_Protect); ++#endif ++EXPORT_SYMBOL(MDrv_MIU_Get_IDEnables_Value); ++EXPORT_SYMBOL(MDrv_MIU_Info); ++ ++#ifdef CONFIG_MIU_HW_MMU ++static DEFINE_SPINLOCK(mmu_lock); ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++static int mmu_isr_init=0; ++MDrv_MMU_Callback MDrv_MMU_Notify=NULL; ++#endif ++ ++int MDrv_MMU_SetRegion(unsigned short u16Region, unsigned short u16ReplaceRegion) ++{ ++ unsigned long flags; ++ int ret; ++ ++ if(u16Region ==u16ReplaceRegion) ++ { ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_SetRegion(u16Region); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ } ++ else ++ { ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x1) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_SetRegionReplaceable(u16Region,u16ReplaceRegion); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ } ++ ++ return ret; ++} ++ ++int MDrv_MMU_SetPageSize(unsigned char u8PgSz256En) ++{ ++ if(0 != u8PgSz256En) ++ { ++ printk("[%s] not support u8PgSz256En = %d \n", __FUNCTION__, u8PgSz256En); ++ return -1 ; ++ } ++ ++ return 0; ++} ++ ++int MDrv_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry) ++{ ++ unsigned long flags; ++ int ret; ++ ++ if (u16VirtAddrEntry == MMU_INVALID_ENTRY_VAL) ++ { ++ printk("[%s] Virtual address entry is invalid(0x%X)\n", __FUNCTION__, u16VirtAddrEntry); ++ return -1; ++ } ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_Map(u16PhyAddrEntry, u16VirtAddrEntry); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++unsigned short MDrv_MMU_MapQuery(unsigned short u16PhyAddrEntry) ++{ ++ unsigned long flags; ++ unsigned short entry; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ entry = HAL_MMU_MapQuery(u16PhyAddrEntry); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return entry; ++} ++ ++int MDrv_MMU_UnMap(unsigned short u16PhyAddrEntry) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_UnMap(u16PhyAddrEntry); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++int MDrv_MMU_AddClientId(unsigned short u16ClientId) ++{ ++ unsigned long flags; ++ int ret; ++ ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x2) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_AddClientId(u16ClientId); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++int MDrv_MMU_RemoveClientId(unsigned short u16ClientId) ++{ ++ unsigned long flags; ++ int ret; ++ ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x2) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_RemoveClientId(u16ClientId); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++static irqreturn_t MDrv_MMU_interrupt(s32 irq, void *dev_id) ++{ ++ unsigned long flags; ++ unsigned int status; ++ unsigned short u16PhyAddrEntry, u16ClientId; ++ unsigned char u8IsWriteCmd; ++ char name[32]={0}; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ status = HAL_MMU_Status(&u16PhyAddrEntry, &u16ClientId, &u8IsWriteCmd); ++ ++ if (MDrv_MMU_Notify != NULL) ++ { ++ MDrv_MMU_Notify(status, u16PhyAddrEntry, u16ClientId, u8IsWriteCmd); ++ } ++ else ++ { ++ HAL_MIU_ClientIdToName(u16ClientId , name ); ++ printk("[%s] Status=0x%x, PhyAddrEntry=0x%x, ClientId=0x%x, name =%s , IsWrite=%d\n", __FUNCTION__, ++ status, ++ u16PhyAddrEntry, ++ u16ClientId, ++ name, ++ u8IsWriteCmd); ++ } ++ ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++void MDrv_MMU_CallbackFunc(MDrv_MMU_Callback pFuncPtr) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ MDrv_MMU_Notify = pFuncPtr; ++ spin_unlock_irqrestore(&mmu_lock, flags); ++} ++EXPORT_SYMBOL(MDrv_MMU_CallbackFunc); ++#endif ++ ++int MDrv_MMU_Enable(unsigned char u8Enable) ++{ ++ unsigned long flags; ++ int ret; ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++ if (!mmu_isr_init) ++ { ++ struct device_node *dev_node = NULL; ++ int rc = 0; ++ int iIrqNum = 0; ++ dev_node = of_find_compatible_node(NULL, NULL, "sstar,mmu"); ++ if (!dev_node) ++ { ++ printk("[MMU] find node Fail\r\n"); ++ } ++ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ if(0 != (rc = request_irq(iIrqNum, MDrv_MMU_interrupt, IRQF_TRIGGER_HIGH, "MMU", NULL))) ++ { ++ printk("[MMU] request_irq [%d] Fail, Err:%d\r\n", iIrqNum, rc); ++ } ++ mmu_isr_init = 1; ++ } ++#endif ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_Enable(u8Enable); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++int MDrv_MMU_Reset(void) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_Reset(); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++#ifndef CONFIG_MMU_INTERRUPT_ENABLE ++unsigned int MDrv_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsWriteCmd) ++{ ++ unsigned long flags; ++ unsigned int status; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ status = HAL_MMU_Status(u16PhyAddrEntry, u16ClientId, u8IsWriteCmd); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return status; ++} ++#endif ++ ++EXPORT_SYMBOL(MDrv_MMU_SetRegion); ++EXPORT_SYMBOL(MDrv_MMU_SetPageSize); ++EXPORT_SYMBOL(MDrv_MMU_Map); ++EXPORT_SYMBOL(MDrv_MMU_MapQuery); ++EXPORT_SYMBOL(MDrv_MMU_UnMap); ++EXPORT_SYMBOL(MDrv_MMU_AddClientId); ++EXPORT_SYMBOL(MDrv_MMU_RemoveClientId); ++EXPORT_SYMBOL(MDrv_MMU_Enable); ++EXPORT_SYMBOL(MDrv_MMU_Reset); ++#ifndef CONFIG_MMU_INTERRUPT_ENABLE ++EXPORT_SYMBOL(MDrv_MMU_Status); ++#endif ++#endif ++ ++static int mstar_miu_drv_probe(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstarmiu_of_device_ids[] = { ++ {.compatible = "sstar-miu"}, ++ {}, ++}; ++#endif ++ ++static struct platform_driver Sstar_miu_driver = { ++ .probe = mstar_miu_drv_probe, ++ .remove = mstar_miu_drv_remove, ++ .suspend = mstar_miu_drv_suspend, ++ .resume = mstar_miu_drv_resume, ++ .driver = { ++ .name = "Sstar-miu", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstarmiu_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_miu_drv_init_module(void) ++{ ++ int ret = 0; ++ ++ ret = platform_driver_register(&Sstar_miu_driver); ++ ++ if (ret) { ++ printk("Register MIU Driver Fail"); ++ } ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Sstar_miu_driver); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/miu/infinity2m/mhal_miu.c b/drivers/sstar/miu/infinity2m/mhal_miu.c +new file mode 100755 +index 000000000000..4b964cbdd59d +--- /dev/null ++++ b/drivers/sstar/miu/infinity2m/mhal_miu.c +@@ -0,0 +1,1477 @@ ++/* ++* mhal_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_COMPAT) ++#include ++#endif ++#include "MsTypes.h" ++#include "mdrv_types.h" ++#include "mdrv_miu.h" ++#include "mdrv_system.h" ++#include "regMIU.h" ++#include "mhal_miu.h" ++#include "registers.h" ++#include "ms_platform.h" ++//------------------------------------------------------------------------------------------------- ++// Macro Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_MIIC0_RW, \ ++/* 2 */ MIU_CLIENT_MIIC1_RW, \ ++/* 3 */ MIU_CLIENT_DUMMY_G0C3, \ ++/* 4 */ MIU_CLIENT_JPE_R, \ ++/* 5 */ MIU_CLIENT_JPE_W, \ ++/* 6 */ MIU_CLIENT_BACH_RW, \ ++/* 7 */ MIU_CLIENT_AESDMA_RW, \ ++/* 8 */ MIU_CLIENT_DUMMY_G08, \ ++/* 9 */ MIU_CLIENT_DUMMY_G09, \ ++/* A */ MIU_CLIENT_MCU51_RW, \ ++/* B */ MIU_CLIENT_URDMA_RW, \ ++/* C */ MIU_CLIENT_BDMA_RW, \ ++/* D */ MIU_CLIENT_MOVDMA0_RW, \ ++/* E */ MIU_CLIENT_DUMMY_G0CE, \ ++/* F */ MIU_CLIENT_DUMMY_G0CF ++ ++#define MIU_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_CMDQ0_R, \ ++/* 1 */ MIU_CLIENT_SATA_RW, \ ++/* 2 */ MIU_CLIENT_EMAC_RW, \ ++/* 3 */ MIU_CLIENT_EMAC1_RW, \ ++/* 4 */ MIU_CLIENT_DUMMY_G1C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G1C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G1C6, \ ++/* 7 */ MIU_CLIENT_USB20_1_RW, \ ++/* 8 */ MIU_CLIENT_USB20_2_RW, \ ++/* 9 */ MIU_CLIENT_USB20_3_RW, \ ++/* A */ MIU_CLIENT_GE_RW, \ ++/* B */ MIU_CLIENT_DUMMY_G1CB, \ ++/* C */ MIU_CLIENT_DUMMY_G1CC, \ ++/* D */ MIU_CLIENT_DUMMY_G1CD, \ ++/* E */ MIU_CLIENT_DUMMY_G1CE, \ ++/* F */ MIU_CLIENT_SDIO30_RW ++ ++#define MIU_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_DIP0_R, \ ++/* 1 */ MIU_CLIENT_DIP0_W, \ ++/* 2 */ MIU_CLIENT_GOP0_R, \ ++/* 3 */ MIU_CLIENT_GOP1_R, \ ++/* 4 */ MIU_CLIENT_MOP_ROT0_Y_R, \ ++/* 5 */ MIU_CLIENT_MOP_ROT0_C_R, \ ++/* 6 */ MIU_CLIENT_MOP_ROT1_Y_R, \ ++/* 7 */ MIU_CLIENT_MOP_ROT1_C_R, \ ++/* 8 */ MIU_CLIENT_MOP_S_Y_R, \ ++/* 9 */ MIU_CLIENT_MOP_S_C_R, \ ++/* A */ MIU_CLIENT_MOP_G_Y_R, \ ++/* B */ MIU_CLIENT_MOP_G_C_R, \ ++/* C */ MIU_CLIENT_DUMMY_G2CC, \ ++/* D */ MIU_CLIENT_DUMMY_G2CD, \ ++/* E */ MIU_CLIENT_WAVE511_RW, \ ++/* F */ MIU_CLIENT_DIAMOND_RW ++ ++#define MIU_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_DUMMY_G3C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G3C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G3C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G3C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G3C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G3C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G3C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G3C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G3C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G3C9, \ ++/* A */ MIU_CLIENT_DUMMY_G3CA, \ ++/* B */ MIU_CLIENT_DUMMY_G3CB, \ ++/* C */ MIU_CLIENT_DUMMY_G3CC, \ ++/* D */ MIU_CLIENT_DUMMY_G3CD, \ ++/* E */ MIU_CLIENT_DUMMY_G3CE, \ ++/* F */ MIU_CLIENT_DUMMY_G3CF ++ ++#define MIU_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_DUMMY_G4C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G4C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G4C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G4C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G4C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G4C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G4C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G4C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G4C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G4C9, \ ++/* A */ MIU_CLIENT_DUMMY_G4CA, \ ++/* B */ MIU_CLIENT_DUMMY_G4CB, \ ++/* C */ MIU_CLIENT_DUMMY_G4CC, \ ++/* D */ MIU_CLIENT_DUMMY_G4CD, \ ++/* E */ MIU_CLIENT_DUMMY_G4CE, \ ++/* F */ MIU_CLIENT_DUMMY_G4CF ++ ++#define MIU_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_DUMMY_G5C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G5C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G5C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G5C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G5C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G5C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G5C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G5C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G5C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G5C9, \ ++/* A */ MIU_CLIENT_DUMMY_G5CA, \ ++/* B */ MIU_CLIENT_DUMMY_G5CB, \ ++/* C */ MIU_CLIENT_DUMMY_G5CC, \ ++/* D */ MIU_CLIENT_DUMMY_G5CD, \ ++/* E */ MIU_CLIENT_DUMMY_G5CE, \ ++/* F */ MIU_CLIENT_DUMMY_G5CF ++ ++#define MIU_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_DUMMY_G6C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G6C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G6C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G6C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G6C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G6C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G6C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G6C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G6C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G6C9, \ ++/* A */ MIU_CLIENT_DUMMY_G6CA, \ ++/* B */ MIU_CLIENT_DUMMY_G6CB, \ ++/* C */ MIU_CLIENT_DUMMY_G6CC, \ ++/* D */ MIU_CLIENT_DUMMY_G6CD, \ ++/* E */ MIU_CLIENT_DUMMY_G6CE, \ ++/* F */ MIU_CLIENT_DUMMY_G6CF ++ ++#define MIU_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_DUMMY_G7C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G7C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G7C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G7C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G7C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G7C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G7C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G7C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G7C9, \ ++/* A */ MIU_CLIENT_DUMMY_G7CA, \ ++/* B */ MIU_CLIENT_DUMMY_G7CB, \ ++/* C */ MIU_CLIENT_DUMMY_G7CC, \ ++/* D */ MIU_CLIENT_DUMMY_G7CD, \ ++/* E */ MIU_CLIENT_DUMMY_G7CE, \ ++/* F */ MIU_CLIENT_DUMMY_G7CF ++ ++#define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < ARM_MIU1_BASE_ADDR) \ ++ {MiuSel = E_MIU_0; Offset = PhysAddr - ARM_MIU0_BASE_ADDR;} \ ++ else if ((PhysAddr >= ARM_MIU1_BASE_ADDR) && (PhysAddr < ARM_MIU2_BASE_ADDR)) \ ++ {MiuSel = E_MIU_1; Offset = PhysAddr - ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {MiuSel = E_MIU_2; Offset = PhysAddr - ARM_MIU2_BASE_ADDR;} ++ ++#define MIU_HAL_ERR(fmt, args...) printk(KERN_ERR "miu hal error %s:%d" fmt,__FUNCTION__,__LINE__,## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++ ++const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] = ++{ ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ }, ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ } ++}; ++ ++static MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_USB20_1_RW, ++ MIU_CLIENT_USB20_2_RW, ++ MIU_CLIENT_USB20_3_RW, ++ MIU_CLIENT_WAVE511_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_EMAC1_RW, ++ MIU_CLIENT_SATA_RW, ++ MIU_CLIENT_SDIO30_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ MIU_CLIENT_GE_RW, ++ 0, ++}; ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++static MS_U32 m_u32MiuMapBase = 0xFD200000UL; //default set to arm 32bit platform ++#elif defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++static ptrdiff_t m_u32MiuMapBase; ++#endif ++ ++static MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}, {{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++static MS_U16 IDList[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}, {0}}; //IDList for protection ++ ++//------------------------------------------------------------------------------------------------- ++// MTLB HAL internal function ++//------------------------------------------------------------------------------------------------- ++ ++static MS_U32 HAL_MIU_BA2PA(MS_U32 u32BusAddr) ++{ ++ MS_PHYADDR u32PhyAddr = 0x0UL; ++ ++ // pa = ba - offset ++ if ((u32BusAddr >= ARM_MIU0_BUS_BASE) && (u32BusAddr < ARM_MIU1_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU0_BUS_BASE + ARM_MIU0_BASE_ADDR; ++ else if ((u32BusAddr >= ARM_MIU1_BUS_BASE) && (u32BusAddr < ARM_MIU2_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU1_BUS_BASE + ARM_MIU1_BASE_ADDR; ++ else ++ u32PhyAddr = u32BusAddr - ARM_MIU2_BUS_BASE + ARM_MIU2_BASE_ADDR; ++ ++ return u32PhyAddr; ++} ++ ++static MS_S16 HAL_MIU_GetClientIndex(MS_U8 u8MiuSel, eMIUClientID eClientID) ++{ ++ MS_U8 idx = 0; ++ ++ if (MIU_MAX_DEVICE <= u8MiuSel) { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return (-1); ++ } ++ ++ for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++) { ++ if (eClientID == clientTbl[u8MiuSel][idx]) ++ return idx; ++ } ++ return (-1); ++} ++ ++static MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)]; ++} ++ ++static MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId]; ++} ++ ++static MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegProtectId, MS_U8 u8Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)] = u8Val; ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegProtectId, MS_U16 u16Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId] = u16Val; ++ ++ return TRUE; ++} ++ ++static void HAL_MIU_WriteByteMask(MS_U32 u32RegOffset, MS_U8 u8Mask, MS_BOOL bEnable) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(u32RegOffset); ++ ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_MIU_WriteByte(u32RegOffset, u8Val); ++} ++ ++static void HAL_MIU_Write2BytesMask(MS_U32 u32RegOffset, MS_U16 u16Mask, MS_BOOL bEnable) ++{ ++ MS_U16 u16Val = HAL_MIU_Read2Byte(u32RegOffset); ++ ++ u16Val = (bEnable) ? (u16Val | u16Mask) : (u16Val & ~u16Mask); ++ HAL_MIU_Write2Byte(u32RegOffset, u16Val); ++} ++ ++static void HAL_MIU_SetProtectIDReg(MS_U32 u32RegBase, MS_U8 u8MiuSel, MS_U16 u16ClientID) ++{ ++ MS_S16 sVal = HAL_MIU_GetClientIndex(u8MiuSel, (eMIUClientID)u16ClientID); ++ MS_S16 sIDVal = 0; ++ ++ if (0 > sVal) { ++ sVal = 0; ++ } ++ ++ sIDVal = HAL_MIU_ReadByte(u32RegBase); ++ sIDVal &= 0x80; ++ sIDVal |= sVal; ++ HAL_MIU_WriteByte(u32RegBase, sIDVal); ++} ++ ++static MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U16 u16ID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U8 u8isfound0, u8isfound1; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u16ID = pu8ProtectId[u32index0]; ++ ++ // Unused ID ++ if (u16ID == 0) ++ continue; ++ ++ u8isfound0 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == u16ID) ++ { ++ // ID reused former setting ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound0 = TRUE; ++ break; ++ } ++ } ++ ++ // Need to create new ID in IDList ++ if (u8isfound0 != TRUE) ++ { ++ u8isfound1 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == 0) ++ { ++ IDList[u8MiuSel][u32index1] = u16ID; ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound1 = TRUE; ++ break; ++ } ++ } ++ ++ // ID overflow ++ if (u8isfound1 == FALSE) { ++ return FALSE; ++ } ++ } ++ } ++ ++ u16IdEnable = 0; ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ if (IDEnables[u8MiuSel][u8Blockx][u32index0] == 1) { ++ u16IdEnable |= (1 << u32index0); ++ } ++ } ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U8 u8isIDNoUse = 0; ++ MS_U16 u16IdEnable = 0; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ u16IdEnable = 0x0UL; ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u8isIDNoUse = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++) ++ { ++ if (IDEnables[u8MiuSel][u32index1][u32index0] == 1) ++ { ++ // Protect ID is still be used ++ u8isIDNoUse = FALSE; ++ break; ++ } ++ u8isIDNoUse = TRUE; ++ } ++ ++ if (u8isIDNoUse == TRUE) { ++ IDList[u8MiuSel][u32index0] = 0; ++ } ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++#define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO) ++#define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID) ++ ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ MS_U16 u16Ret = 0; ++ MS_U16 u16LoAddr = 0; ++ MS_U16 u16HiAddr = 0; ++ MS_U32 u32RegBase = (u8MiuSel) ? MIU1_REG_BASE : MIU_REG_BASE; ++ MS_U32 u32EndAddr = 0; ++ char clientName[40]; ++ if (!pInfo) { ++ return FALSE; ++ } ++ ++ u16Ret = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_STATUS); ++ u16LoAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_LOADDR); ++ u16HiAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_HIADDR); ++ ++ HAL_MIU_ClientIdToName((MS_U8)(GET_HIT_CLIENT(u16Ret)), clientName); ++ ++ if (REG_MIU_PROTECT_HIT_FALG & u16Ret) ++ { ++ pInfo->bHit = TRUE; ++ pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(u16Ret); ++ pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(u16Ret) >> 4); ++ pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(u16Ret) & 0x0F); ++ pInfo->uAddress = (MS_U32)((u16HiAddr << 16) | u16LoAddr); ++ pInfo->uAddress = pInfo->uAddress * MIU_PROTECT_ADDRESS_UNIT; ++ ++ u32EndAddr = (pInfo->uAddress + MIU_PROTECT_ADDRESS_UNIT - 1); ++ ++ if (pInfo->u8Block == 6 || pInfo->u8Block == 7) ++ { ++ printk(KERN_EMERG "MIU%u %s Out of Range Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x (Valid Range: 0x00000000 ~ 0x%08X)\n", ++ u8MiuSel, (pInfo->u8Block == 6)? "Read" : "Write", clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr, HAL_MIU_ProtectDramSize()); ++ } ++ else ++ { ++ printk(KERN_EMERG "MIU%u Block:%u Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x\n", ++ u8MiuSel, pInfo->u8Block, clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ if ((MIU_CLIENT_WAVE511_RW == GET_HIT_CLIENT(u16Ret)) && (pInfo->u8Block == 6)) ++ { ++ pInfo->bHit = FALSE; ++ } ++ ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuSel, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex) ++{ ++ return IDEnables[u8MiuSel][u8BlockId][u8ProtectIdIndex]; ++} ++ ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&clientId_KernelProtect[0]; ++ } ++ return NULL; ++} ++ ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&IDList[u8MiuSel][0]; ++ } ++ return NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4) ++/// @param *pu8ProtectId \b IN : Allow specified client IDList to write ++/// @param u32Start \b IN : Starting bus address ++/// @param u32End \b IN : End bus address ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegBase = 0; ++ MS_U32 u32RegStartAddr = 0; ++ MS_U32 u32RegStartEnd = 0; ++ MS_U32 u32RegAddrMSB = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ MS_U32 u32RegRWProtectEn = 0; ++ MS_U32 u32StartOffset = 0; ++ MS_U32 u32EndOffset = 0; ++ MS_U8 u8MiuSel = 0; ++ MS_U16 u16Data = 0; ++ MS_U16 u16Data1 = 0; ++ MS_U16 u16Data2 = 0; ++ MS_U8 u8Data = 0; ++ MS_U32 u32Start = 0, u32End = 0; ++ ++ u32Start = HAL_MIU_BA2PA(u32BusStart); ++ u32End = HAL_MIU_BA2PA(u32BusEnd); ++ ++ // Get MIU selection and offset ++ _phy_to_miu_offset(u8MiuSel, u32EndOffset, u32End); ++ _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32Start); ++ ++ u32Start = u32StartOffset; ++ u32End = u32EndOffset; ++ ++ // Parameter check ++ if (u8Blockx >= E_MIU_BLOCK_NUM) ++ { ++ MIU_HAL_ERR("Err: Blk Num out of range\n"); ++ return FALSE; ++ } ++ else if (((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ++ ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0)) ++ { ++ MIU_HAL_ERR("Err: Protected addr not 8KB aligned\n"); ++ return FALSE; ++ } ++ else if (u32Start >= u32End) ++ { ++ MIU_HAL_ERR("Err: Invalid end addr\n"); ++ return FALSE; ++ } ++ ++ ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ u32RegBase = MIU_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT0_EN; ++ u32RegStartAddr = MIU_PROTECT0_START; ++ u32RegStartEnd = MIU_PROTECT0_END; ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU_PROTECT1_EN; ++ u32RegStartAddr = MIU_PROTECT1_START; ++ u32RegStartEnd = MIU_PROTECT1_END; ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU_PROTECT2_EN; ++ u32RegStartAddr = MIU_PROTECT2_START; ++ u32RegStartEnd = MIU_PROTECT2_END; ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU_PROTECT3_EN; ++ u32RegStartAddr = MIU_PROTECT3_START; ++ u32RegStartEnd = MIU_PROTECT3_END; ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT4_EN; ++ u32RegStartAddr = MIU_PROTECT4_START; ++ u32RegStartEnd = MIU_PROTECT4_END; ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ u32RegBase = MIU1_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT0_EN; ++ u32RegStartAddr = MIU1_PROTECT0_START; ++ u32RegStartEnd = MIU1_PROTECT0_END; ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU1_PROTECT1_EN; ++ u32RegStartAddr = MIU1_PROTECT1_START; ++ u32RegStartEnd = MIU1_PROTECT1_END; ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU1_PROTECT2_EN; ++ u32RegStartAddr = MIU1_PROTECT2_START; ++ u32RegStartEnd = MIU1_PROTECT2_END; ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU1_PROTECT3_EN; ++ u32RegStartAddr = MIU1_PROTECT3_START; ++ u32RegStartEnd = MIU1_PROTECT3_END; ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT4_EN; ++ u32RegStartAddr = MIU1_PROTECT4_START; ++ u32RegStartEnd = MIU1_PROTECT4_END; ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ // Disable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, DISABLE); ++ ++ if (bSetFlag) ++ { ++ // Set Protect IDList ++ if (HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn) == FALSE) ++ { ++ return FALSE; ++ } ++ ++ // Set BIT29,30 of start/end address ++ u16Data2 = u16Data2 | (MS_U16)((u32Start >> 29) << ((u8Blockx%4)*4)); // u16Data2 for start_ext addr ++ u16Data1 = u16Data2 | (MS_U16)(((u32End - 1) >> 29) << ((u8Blockx%4)*4+2)); ++ HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1); ++ ++ // Start Address ++ u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); // 8k unit ++ HAL_MIU_Write2Byte(u32RegStartAddr, u16Data); ++ ++ // End Address ++ u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); // 8k unit; ++ HAL_MIU_Write2Byte(u32RegStartEnd, u16Data); ++ ++ // Enable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, ENABLE); ++ } ++ else ++ { ++ // Reset Protect IDList ++ HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // Mask PWR IRQ ++ HAL_MIU_Write2BytesMask(REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET, REG_MIU_PROTECT_PWR_IRQ_MASK_BIT, TRUE); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource ++/// @brief \b Function \b Description: Parse occupied resource to software structure ++/// @return \b 0: Fail 1: OK ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) ++{ ++ MS_U8 u8MiuSel = 0; ++ MS_U8 u8Blockx = 0; ++ MS_U8 u8ClientID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U32 u32index = 0; ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ ++ for (u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ for (u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ { ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel); ++ return FALSE; ++ } ++ ++ u16IdEnable = HAL_MIU_Read2Byte(u32RegProtectIdEn); ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16IdEnable >> u32index) & 0x1UL) ? 1: 0; ++ } ++ } ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ u8ClientID = HAL_MIU_ReadByte(u32RegProtectId + u32index) & 0x7F; ++ IDList[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID]; ++ } ++ } ++ ++ return TRUE; ++} ++ ++unsigned int HAL_MIU_ProtectDramSize(void) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(MIU_PROTECT_DDR_SIZE); ++ ++ u8Val = (u8Val >> 4) & 0xF; ++ ++ if (0 == u8Val) { ++ MIU_HAL_ERR("MIU protect size undefined. Using 0x40000000\n"); ++ return 0x40000000; ++ } ++ return (0x1 << (20 + u8Val)); ++} ++ ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ int iRet = 0; ++ ++ if (!clientName) { ++ iRet = -1; ++ MIU_HAL_ERR("Wrong clientName\n"); ++ return iRet; ++ } ++ ++ switch(clientId) ++ { ++ // group 0 ++ case MIU_CLIENT_NONE: ++ strcpy(clientName, "NONE"); ++ break; ++ case MIU_CLIENT_MIIC0_RW: ++ strcpy(clientName, "MIIC0_RW"); ++ break; ++ case MIU_CLIENT_MIIC1_RW: ++ strcpy(clientName, "MIIC1_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G0C3: ++ strcpy(clientName, "DUMMY_G0C3"); ++ break; ++ case MIU_CLIENT_JPE_W: ++ strcpy(clientName, "JPE_W"); ++ break; ++ case MIU_CLIENT_JPE_R: ++ strcpy(clientName, "JPE_R"); ++ break; ++ case MIU_CLIENT_BACH_RW: ++ strcpy(clientName, "BACH_RW"); ++ break; ++ case MIU_CLIENT_AESDMA_RW: ++ strcpy(clientName, "AESDMA_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G08: ++ strcpy(clientName, "DUMMY_G0C8"); ++ break; ++ case MIU_CLIENT_DUMMY_G09: ++ strcpy(clientName, "DUMMY_G0C9"); ++ break; ++ case MIU_CLIENT_MCU51_RW: ++ strcpy(clientName, "MCU51_RW"); ++ break; ++ case MIU_CLIENT_URDMA_RW: ++ strcpy(clientName, "URDMA_RW"); ++ break; ++ case MIU_CLIENT_BDMA_RW: ++ strcpy(clientName, "BDMA_RW"); ++ break; ++ case MIU_CLIENT_MOVDMA0_RW: ++ strcpy(clientName, "MOVDMA0_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CE: ++ strcpy(clientName, "DUMMY_G0CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CF: ++ strcpy(clientName, "DUMMY_G0CF"); ++ break; ++ // group 1 ++ case MIU_CLIENT_CMDQ0_R: ++ strcpy(clientName, "CMDQ0_R"); ++ break; ++ case MIU_CLIENT_SATA_RW: ++ strcpy(clientName, "SATA_RW"); ++ break; ++ case MIU_CLIENT_EMAC_RW: ++ strcpy(clientName, "EMAC_RW"); ++ break; ++ case MIU_CLIENT_EMAC1_RW: ++ strcpy(clientName, "EMAC1_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G1C4: ++ strcpy(clientName, "DUMMY_G1C4"); ++ break; ++ case MIU_CLIENT_DUMMY_G1C5: ++ strcpy(clientName, "DUMMY_G1C5"); ++ break; ++ case MIU_CLIENT_DUMMY_G1C6: ++ strcpy(clientName, "DUMMY_G1C6"); ++ break; ++ case MIU_CLIENT_USB20_1_RW: ++ strcpy(clientName, "USB20_1_RW"); ++ break; ++ case MIU_CLIENT_USB20_2_RW: ++ strcpy(clientName, "USB20_2_RW"); ++ break; ++ case MIU_CLIENT_USB20_3_RW: ++ strcpy(clientName, "USB20_3_RW"); ++ break; ++ case MIU_CLIENT_GE_RW: ++ strcpy(clientName, "GE_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CB: ++ strcpy(clientName, "DUMMY_G1CB"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CC: ++ strcpy(clientName, "DUMMY_G1CC"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CD: ++ strcpy(clientName, "DUMMY_G1CD"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CE: ++ strcpy(clientName, "DUMMY_G1CE"); ++ break; ++ case MIU_CLIENT_SDIO30_RW: ++ strcpy(clientName, "SDIO30_RW"); ++ break; ++ // group 2 ++ case MIU_CLIENT_DIP0_R: ++ strcpy(clientName, "DIP0_R"); ++ break; ++ case MIU_CLIENT_DIP0_W: ++ strcpy(clientName, "DIP0_W"); ++ break; ++ case MIU_CLIENT_GOP0_R: ++ strcpy(clientName, "GOP0_R"); ++ break; ++ case MIU_CLIENT_GOP1_R: ++ strcpy(clientName, "GOP1_R"); ++ break; ++ case MIU_CLIENT_MOP_ROT0_Y_R: ++ strcpy(clientName, "MOP_ROT0_Y_R"); ++ break; ++ case MIU_CLIENT_MOP_ROT0_C_R: ++ strcpy(clientName, "MOP_ROT0_C_R"); ++ break; ++ case MIU_CLIENT_MOP_ROT1_Y_R: ++ strcpy(clientName, "MOP_ROT1_Y_R"); ++ break; ++ case MIU_CLIENT_MOP_ROT1_C_R: ++ strcpy(clientName, "MOP_ROT1_C_R"); ++ break; ++ case MIU_CLIENT_MOP_S_Y_R: ++ strcpy(clientName, "MOP_S_Y_R"); ++ break; ++ case MIU_CLIENT_MOP_S_C_R: ++ strcpy(clientName, "MOP_S_C_R"); ++ break; ++ case MIU_CLIENT_MOP_G_Y_R: ++ strcpy(clientName, "MOP_G_Y_R"); ++ break; ++ case MIU_CLIENT_MOP_G_C_R: ++ strcpy(clientName, "MOP_G_C_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CC: ++ strcpy(clientName, "DUMMY_G2CC"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CD: ++ strcpy(clientName, "DUMMY_G2CD"); ++ break; ++ case MIU_CLIENT_WAVE511_RW: ++ strcpy(clientName, "WAVE511_RW"); ++ break; ++ case MIU_CLIENT_DIAMOND_RW: ++ strcpy(clientName, "DIAMOND_RW"); ++ break; ++ // DIAMOND ++ case MIU_CLIENT_MIPS_RW: ++ strcpy(clientName, "CPU_RW"); ++ break; ++ default: ++ MIU_HAL_ERR("Wrong clientId %d\n", clientId); ++ iRet = -1; ++ break; ++ } ++ return iRet; ++} ++EXPORT_SYMBOL(HAL_MIU_ClientIdToName); ++ ++int clientId_KernelProtectToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++EXPORT_SYMBOL(clientId_KernelProtectToName); ++ ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ unsigned int ddfset = 0; ++ ++ if (pDramInfo) ++ { ++ ddfset = (INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF); ++ ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ pDramInfo->miupll_freq = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++int HAL_MMU_SetRegion(unsigned short u16Region) ++{ ++ MS_U16 u16CtrlRegVal; ++ ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x2) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ ++ if (u16Region >> 5) ++ { ++ MIU_HAL_ERR("Region over range(0x%x)\n", u16Region); ++ return -1; ++ } ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_CTRL) & ~(BITS_RANGE(REG_MMU_CTRL_REGION_MASK)); ++ u16CtrlRegVal |= (u16Region << 8); ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, u16CtrlRegVal); ++ ++ return 0; ++} ++ ++ ++int HAL_MMU_SetRegionReplaceable(unsigned short u16Region, unsigned short u16ReplaceRegion) ++{ ++ MS_U16 u16CtrlRegVal; ++ ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x1) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ ++ if ((u16Region >> 5) || (u16ReplaceRegion >> 5)) ++ { ++ MIU_HAL_ERR("Region(0x%X) or ReplaceRegion(0x%X) over range \n", u16Region,u16ReplaceRegion); ++ return -1; ++ } ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_CTRL) & ~(BITS_RANGE(REG_MMU_CTRL_REGION_MASK)); ++ u16CtrlRegVal |= (u16Region << 8); ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, u16CtrlRegVal); ++ ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_REPLACE_MSB) & ~(BITS_RANGE(REG_MMU_REPLACE_MSB_MASK)); ++ u16CtrlRegVal |= u16ReplaceRegion; ++ ++ HAL_MIU_Write2Byte(REG_MMU_REPLACE_MSB, u16CtrlRegVal); ++ ++ return 0; ++} ++ ++ ++ ++ ++int HAL_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry) ++{ ++ MS_U16 u16RegVal; ++ ++ if ((u16PhyAddrEntry >> 9) || (u16VirtAddrEntry >> 9)) ++ { ++ MIU_HAL_ERR("Entry over range(Phy:0x%x, Virt:0x%x)\n", u16PhyAddrEntry, u16VirtAddrEntry); ++ return -1; ++ } ++ ++ // reg_mmu_wdata ++ HAL_MIU_Write2Byte(REG_MMU_W_DATA, u16VirtAddrEntry); ++ ++ // reg_mmu_entry ++ u16RegVal = REG_MMU_RW_ENTRY_MODE | u16PhyAddrEntry; ++ HAL_MIU_Write2Byte(REG_MMU_RW_ENTRY, u16RegVal); ++ ++ // reg_mmu_access ++ HAL_MIU_Write2Byte(REG_MMU_ACCESS, BIT0); ++ ++ return 0; ++} ++ ++unsigned short HAL_MMU_MapQuery(unsigned short u16PhyAddrEntry) ++{ ++ MS_U16 u16RegVal; ++ ++ if (u16PhyAddrEntry >> 9) ++ { ++ MIU_HAL_ERR("Entry over range(Phy:0x%x)\n", u16PhyAddrEntry); ++ return -1; ++ } ++ ++ // reg_mmu_entry ++ HAL_MIU_Write2Byte(REG_MMU_RW_ENTRY, u16PhyAddrEntry); ++ ++ // reg_mmu_access ++ HAL_MIU_Write2Byte(REG_MMU_ACCESS, BIT0); ++ ++ // delay 100ns for SRAM read latency(designer comfirmed) ++ ndelay(100); ++ ++ // reg_mmu_rdata ++ u16RegVal = HAL_MIU_Read2Byte(REG_MMU_R_DATA); ++ ++ return u16RegVal; ++} ++ ++int HAL_MMU_UnMap(unsigned short u16PhyAddrEntry) ++{ ++ MS_U16 u16RegVal; ++ ++ if (u16PhyAddrEntry >> 9) ++ { ++ MIU_HAL_ERR("Entry over range(Phy:0x%x)\n", u16PhyAddrEntry); ++ return -1; ++ } ++ ++ // reg_mmu_wdata ++ HAL_MIU_Write2Byte(REG_MMU_W_DATA, MMU_INVALID_ENTRY_VAL); ++ ++ // reg_mmu_entry ++ u16RegVal = REG_MMU_RW_ENTRY_MODE | u16PhyAddrEntry; ++ HAL_MIU_Write2Byte(REG_MMU_RW_ENTRY, u16RegVal); ++ ++ // reg_mmu_access ++ HAL_MIU_Write2Byte(REG_MMU_ACCESS, BIT0); ++ ++ return 0; ++} ++ ++static MS_U16 u16ClientIdMap[MMU_MAX_CLIENT_NUM]={0}; ++static MS_U16 u16ClientSel=0; ++int HAL_MMU_AddClientId(unsigned short u16ClientId) ++{ ++ MS_U16 u16ClientIdx, u16RegVal; ++ MS_U32 u32RegOffset; ++ ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x2) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ ++ for (u16ClientIdx = 0; u16ClientIdx < MMU_MAX_CLIENT_NUM; u16ClientIdx++) ++ { ++ if (u16ClientIdMap[u16ClientIdx] == u16ClientId) ++ return 0; ++ ++ if (u16ClientIdMap[u16ClientIdx] == 0) ++ break; ++ } ++ ++ if (u16ClientIdx != MMU_MAX_CLIENT_NUM) ++ { ++ switch (u16ClientIdx) ++ { ++ case 0: ++ case 1: ++ u32RegOffset = REG_MMU_CLIENT_ID_0_1; ++ break; ++ case 2: ++ case 3: ++ u32RegOffset = REG_MMU_CLIENT_ID_2_3; ++ break; ++ case 4: ++ case 5: ++ u32RegOffset = REG_MMU_CLIENT_ID_4_5; ++ break; ++ case 6: ++ case 7: ++ u32RegOffset = REG_MMU_CLIENT_ID_6_7; ++ break; ++ default: ++ break; ++ } ++ ++ u16RegVal = HAL_MIU_Read2Byte(u32RegOffset); ++ if (!(u16ClientIdx & 0x1)) // ID=0,2,4,6 ++ { ++ u16RegVal &= ~0x3F; ++ u16RegVal |= (u16ClientId & 0x3F); ++ } ++ else // ID=1,3,5,7 ++ { ++ u16RegVal &= ~0x3F00; ++ u16RegVal |= ((u16ClientId << 8) & 0x3F00); ++ } ++ ++ // Add client ID ++ u16ClientIdMap[u16ClientIdx] = u16ClientId; ++ HAL_MIU_Write2Byte(u32RegOffset, u16RegVal); ++ ++ // Enable this client ID ++ u16ClientSel |= (1 << u16ClientIdx); ++ HAL_MIU_Write2Byte(REG_MMU_CLIENT_ID_SEL, u16ClientSel); ++ ++ return 0; ++ } ++ else ++ MIU_HAL_ERR("Client ID is full(max:%d)\n", MMU_MAX_CLIENT_NUM); ++ ++ return -1; ++} ++ ++int HAL_MMU_RemoveClientId(unsigned short u16ClientId) ++{ ++ MS_U16 u16ClientIdx, u16RegVal; ++ MS_U32 u32RegOffset; ++ ++#ifndef CONFIG_FPGA ++ if(Chip_Get_Revision() == 0x2) ++ { ++ printk("[%s] not support , chipId = %d \n", __FUNCTION__, Chip_Get_Revision() ); ++ return -1; ++ } ++#endif ++ ++ for (u16ClientIdx = 0; u16ClientIdx < MMU_MAX_CLIENT_NUM; u16ClientIdx++) ++ { ++ if (u16ClientIdMap[u16ClientIdx] == u16ClientId) ++ break; ++ } ++ ++ if (u16ClientIdx != MMU_MAX_CLIENT_NUM) ++ { ++ switch (u16ClientIdx) ++ { ++ case 0: ++ case 1: ++ u32RegOffset = REG_MMU_CLIENT_ID_0_1; ++ break; ++ case 2: ++ case 3: ++ u32RegOffset = REG_MMU_CLIENT_ID_2_3; ++ break; ++ case 4: ++ case 5: ++ u32RegOffset = REG_MMU_CLIENT_ID_4_5; ++ break; ++ case 6: ++ case 7: ++ u32RegOffset = REG_MMU_CLIENT_ID_6_7; ++ break; ++ default: ++ break; ++ } ++ ++ u16RegVal = HAL_MIU_Read2Byte(u32RegOffset); ++ if (!(u16ClientIdx & 0x1)) // ID=0,2,4,6 ++ { ++ u16RegVal &= ~0x3F; ++ } ++ else // ID=1,3,5,7 ++ { ++ u16RegVal &= ~0x3F00; ++ } ++ ++ // Remove client ID ++ u16ClientIdMap[u16ClientIdx] = 0; ++ HAL_MIU_Write2Byte(u32RegOffset, u16RegVal); ++ ++ // Disable this client ID ++ u16ClientSel &= ~(1 << u16ClientIdx); ++ HAL_MIU_Write2Byte(REG_MMU_CLIENT_ID_SEL, u16ClientSel); ++ ++ return 0; ++ } ++ ++ return 0; ++} ++ ++int HAL_MMU_Enable(unsigned char u8Enable) ++{ ++ MS_U16 u16CtrlRegVal; ++ MS_U16 u16IrqRegVal; ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_CTRL); ++ u16IrqRegVal = HAL_MIU_Read2Byte(REG_MMU_IRQ_CTRL); ++ ++ if (u8Enable) ++ { ++ u16CtrlRegVal |= REG_MMU_CTRL_ENABLE; ++ // Enable IRQ ++ //u16IrqRegVal |= (REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ u16IrqRegVal &= ~(REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ } ++ else ++ { ++ u16CtrlRegVal &= ~REG_MMU_CTRL_ENABLE; ++ // Disable IRQ ++ //u16IrqRegVal &= ~(REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ u16IrqRegVal |= (REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ } ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, u16CtrlRegVal); ++ HAL_MIU_Write2Byte(REG_MMU_IRQ_CTRL, u16IrqRegVal); ++ ++ return 0; ++} ++ ++int HAL_MMU_Reset(void) ++{ ++ MS_U16 u16RetryNum=100; ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, 0x0); ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, REG_MMU_CTRL_RESET | REG_MMU_CTRL_RESET_INIT_VAL); ++ ++ do { ++ if (HAL_MIU_Read2Byte(REG_MMU_CTRL) & REG_MMU_CTRL_INIT_DONE) ++ { ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, 0x0); ++ return 0; ++ } ++ ++ u16RetryNum--; ++ } while (u16RetryNum > 0); ++ ++ MIU_HAL_ERR("Reset timeout!\n"); ++ ++ return -1; ++} ++ ++unsigned int HAL_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsWriteCmd) ++{ ++ MS_U16 u16IrqRegVal; ++ unsigned int u32Status=0; ++ ++ u16IrqRegVal = HAL_MIU_Read2Byte(REG_MMU_IRQ_CTRL); ++ ++ if (u16IrqRegVal & REG_MMU_IRQ_RW_FLAG) ++ { ++ *u16PhyAddrEntry = HAL_MIU_Read2Byte(REG_MMU_COLLISION_ENTRY); ++ u16IrqRegVal |= REG_MMU_IRQ_RW_CLR; ++ u32Status |= E_HAL_MMU_STATUS_RW_COLLISION; ++ } ++ ++ if ((u16IrqRegVal & REG_MMU_IRQ_RD_FLAG) || (u16IrqRegVal & REG_MMU_IRQ_WR_FLAG)) ++ { ++ *u16ClientId = BITS_RANGE_VAL(u16IrqRegVal, REG_MMU_IRQ_INVALID_ID_MASK); ++ *u8IsWriteCmd = (u16IrqRegVal & REG_MMU_IRQ_INVALID_RW)?1:0; ++ ++ if (u16IrqRegVal & REG_MMU_IRQ_RD_FLAG) ++ { ++ u16IrqRegVal |= REG_MMU_IRQ_RD_CLR; ++ u32Status |= E_HAL_MMU_STATUS_R_INVALID; ++ } ++ ++ if (u16IrqRegVal & REG_MMU_IRQ_WR_FLAG) ++ { ++ u16IrqRegVal |= REG_MMU_IRQ_WR_CLR; ++ u32Status |= E_HAL_MMU_STATUS_W_INVALID; ++ } ++ } ++ ++ // Clear IRQ ++ if (u32Status != E_HAL_MMU_STATUS_NORMAL) ++ { ++ HAL_MIU_Write2Byte(REG_MMU_IRQ_CTRL, u16IrqRegVal); ++ HAL_MIU_Write2Byte(REG_MMU_IRQ_CTRL, 0x0); ++ } ++ ++ if (!u32Status) ++ MIU_HAL_ERR("Unknown MIU MMU error: 0x%x\n", u16IrqRegVal); ++ ++ return u32Status; ++} +diff --git a/drivers/sstar/miu/infinity5/mdrv_miu.c b/drivers/sstar/miu/infinity5/mdrv_miu.c +new file mode 100755 +index 000000000000..0fcc44e43ddf +--- /dev/null ++++ b/drivers/sstar/miu/infinity5/mdrv_miu.c +@@ -0,0 +1,324 @@ ++/* ++* mdrv_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "MsTypes.h" ++#include "mdrv_miu.h" ++#include "mhal_miu.h" ++#include "regMIU.h" ++#include ++#include "irqs.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_MSTAR_MONET) || defined(CONFIG_MSTAR_MESSI) || defined(CONFIG_MSTAR_MASERATI) || defined(CONFIG_MSTAR_MANHATTAN) || defined(CONFIG_MSTAR_KANO) ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY phy64Start, MS_PHY phy64End, MS_BOOL bSetFlag) __attribute__((weak)); ++#else ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, MS_U32 u32BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++#endif ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) __attribute__((weak)); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) __attribute__((weak)); ++ ++MS_BOOL HAL_MIU_SlitInit(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SetSlitRange(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY u64BusStart, MS_PHY u64BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++MS_BOOL HAL_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++ ++#ifndef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static struct timer_list monitor_timer; ++static int gOpenTimeList = 0; ++#endif ++ ++static DEFINE_SPINLOCK(miu_lock); ++MS_U8 u8_MiuWhiteListNum = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Local functions ++//------------------------------------------------------------------------------------------------- ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Init ++/// @brief \b Function \b Description: parse occupied resource to software structure ++/// @param None \b IN : ++/// @param None \b OUT : ++/// @param MS_BOOL \b RET ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Init(void) ++{ ++ MS_BOOL ret = FALSE; ++ ++ /* Parse the used client ID in hardware into software data structure */ ++ if (HAL_MIU_ParseOccupiedResource) { ++ ret = HAL_MIU_ParseOccupiedResource(); ++ } ++ else { ++ ret = FALSE; ++ } ++ ++ /* Initialize MIU slit setting */ ++ if (HAL_MIU_SlitInit) { ++ ret = HAL_MIU_SlitInit(); ++ } ++ ++ u8_MiuWhiteListNum = IDNUM_KERNELPROTECT; ++ ++ return ret; ++} ++ ++MS_BOOL MDrv_MIU_GetProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ return HAL_MIU_GetHitProtectInfo(u8MiuSel, pInfo); ++} ++ ++MS_BOOL MDrv_MIU_Get_IDEnables_Value(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 u8ClientIndex) ++{ ++ return HAL_MIU_GetProtectIdEnVal(u8MiuSel, u8Blockx, u8ClientIndex); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* MDrv_MIU_GetDefaultClientID_KernelProtect(void) ++{ ++ if (HAL_MIU_GetDefaultKernelProtectClientID) { ++ return HAL_MIU_GetDefaultKernelProtectClientID(); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++MS_U16* MDrv_MIU_GetClientID_KernelProtect(MS_U8 u8MiuSel) ++{ ++ if (HAL_MIU_GetKernelProtectClientID) { ++ return HAL_MIU_GetKernelProtectClientID(u8MiuSel); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static irqreturn_t MDrv_MIU_Protect_interrupt(s32 irq, void *dev_id) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo *pInfo = kmalloc(sizeof(MIU_PortectInfo), GFP_KERNEL); ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, pInfo); ++ BUG(); ++ return IRQ_HANDLED; ++} ++#else ++//create timer process ++static void MDev_timer_callback(unsigned long value) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo stProtInfo; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) { ++ stProtInfo.bHit = FALSE; ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &stProtInfo); ++ if (stProtInfo.bHit) { ++ panic("MIU %d Protect hit!\n", u8MiuSel); ++ } ++ } ++ mod_timer(&monitor_timer, jiffies+1*HZ); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 3) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_PHY u64BusStart, ++ MS_PHY u64BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_BOOL Result = FALSE; ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ int rc = 0; ++#endif ++ ++ /* Case of former MIU protect */ ++ if ((u8Blockx >= E_PROTECT_0) && (u8Blockx < E_SLIT_0)) ++ { ++ if (HAL_MIU_Protect) { ++ Result = HAL_MIU_Protect(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag); ++ } ++ } ++ /* Case of MIU slits */ ++ else if (u8Blockx == E_SLIT_0) ++ { ++ if (HAL_MIU_SetSlitRange) { ++ Result = HAL_MIU_SetSlitRange(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag); ++ } ++ } ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ rc = request_irq(INT_IRQ_MIU, MDrv_MIU_Protect_interrupt, IRQF_TRIGGER_HIGH, "MIU_Protect", NULL); ++#else ++ if (gOpenTimeList == 0) ++ { ++ init_timer(&monitor_timer); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++ gOpenTimeList++; ++ } ++#endif ++ ++ return Result; ++} ++ ++unsigned int MDrv_MIU_ProtectDramSize(void) ++{ ++ return HAL_MIU_ProtectDramSize(); ++} ++ ++int MDrv_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++ ++MS_BOOL MDrv_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) ++{ ++ unsigned long flags; ++ MS_BOOL Result = FALSE; ++ ++ spin_lock_irqsave(&miu_lock, flags); ++ ++ if (HAL_MIU_Slits) { ++ Result = HAL_MIU_Slits(u8Blockx, u64SlitsStart, u64SlitsEnd, bSetFlag); ++ } ++ ++ spin_unlock_irqrestore(&miu_lock, flags); ++ ++ return Result; ++} ++ ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo) ++{ ++ return HAL_MIU_Info((MIU_DramInfo_Hal *)pDramInfo); ++} ++ ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(MDrv_MIU_Init); ++EXPORT_SYMBOL(u8_MiuWhiteListNum); ++EXPORT_SYMBOL(MDrv_MIU_GetDefaultClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_GetClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_Protect); ++#endif ++EXPORT_SYMBOL(MDrv_MIU_Get_IDEnables_Value); ++EXPORT_SYMBOL(MDrv_MIU_Info); ++ ++static int mstar_miu_drv_probe(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_remove(struct platform_device *pdev) ++{ ++ del_timer(&monitor_timer); ++ return 0; ++} ++ ++static int mstar_miu_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstarmiu_of_device_ids[] = { ++ {.compatible = "sstar-miu"}, ++ {}, ++}; ++#endif ++ ++static struct platform_driver Sstar_miu_driver = { ++ .probe = mstar_miu_drv_probe, ++ .remove = mstar_miu_drv_remove, ++ .suspend = mstar_miu_drv_suspend, ++ .resume = mstar_miu_drv_resume, ++ .driver = { ++ .name = "Sstar-miu", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstarmiu_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_miu_drv_init_module(void) ++{ ++ int ret = 0; ++ ++ ret = platform_driver_register(&Sstar_miu_driver); ++ ++ if (ret) { ++ printk("Register MIU Driver Fail"); ++ } ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Sstar_miu_driver); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/miu/infinity5/mhal_miu.c b/drivers/sstar/miu/infinity5/mhal_miu.c +new file mode 100755 +index 000000000000..278f25ffa399 +--- /dev/null ++++ b/drivers/sstar/miu/infinity5/mhal_miu.c +@@ -0,0 +1,1069 @@ ++/* ++* mhal_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#if defined(CONFIG_COMPAT) ++#include ++#endif ++#include "MsTypes.h" ++#include "mdrv_types.h" ++#include "mdrv_miu.h" ++#include "mdrv_system.h" ++#include "regMIU.h" ++#include "mhal_miu.h" ++#include "registers.h" ++#include "ms_platform.h" ++//------------------------------------------------------------------------------------------------- ++// Macro Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_DIP0_R, \ ++/* 2 */ MIU_CLIENT_DIP0_W, \ ++/* 3 */ MIU_CLIENT_LDC_R, \ ++/* 4 */ MIU_CLIENT_SC2_FRAME_W, \ ++/* 5 */ MIU_CLIENT_SC3_FRAME_W, \ ++/* 6 */ MIU_CLIENT_RSC_R, \ ++/* 7 */ MIU_CLIENT_SC1_DBG_R, \ ++/* 8 */ MIU_CLIENT_CMDQ0_R, \ ++/* 9 */ MIU_CLIENT_MOVDMA0_RW, \ ++/* A */ MIU_CLIENT_EMAC_RW, \ ++/* B */ MIU_CLIENT_2DGE_RW, \ ++/* C */ MIU_CLIENT_3DNR0_R, \ ++/* D */ MIU_CLIENT_3DNR0_W, \ ++/* E */ MIU_CLIENT_GOP4_R, \ ++/* F */ MIU_CLIENT_DUMMY_G0CF ++ ++#define MIU_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_ISP_DMAG0_RW, \ ++/* 1 */ MIU_CLIENT_ISP_DMAG1_RW, \ ++/* 2 */ MIU_CLIENT_ISP_DMAG2_RW, \ ++/* 3 */ MIU_CLIENT_GOP2_R, \ ++/* 4 */ MIU_CLIENT_GOP3_R, \ ++/* 5 */ MIU_CLIENT_ISP_DMAG_RW, \ ++/* 6 */ MIU_CLIENT_ISP_AF_STA1_W, \ ++/* 7 */ MIU_CLIENT_ISP_MLOAD_RW, \ ++/* 8 */ MIU_CLIENT_CMDQ1_R, \ ++/* 9 */ MIU_CLIENT_MOVDMA1_RW, \ ++/* A */ MIU_CLIENT_MCU51_RW, \ ++/* B */ MIU_CLIENT_DLA_RW, \ ++/* C */ MIU_CLIENT_IVE_RW, \ ++/* D */ MIU_CLIENT_DUMMY_G1CD, \ ++/* E */ MIU_CLIENT_DUMMY_G1CE, \ ++/* F */ MIU_CLIENT_DUMMY_G1CF ++ ++#define MIU_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_DUMMY_G2C0, \ ++/* 1 */ MIU_CLIENT_SC_ROT_R, \ ++/* 2 */ MIU_CLIENT_SC_AIP_W, \ ++/* 3 */ MIU_CLIENT_SC0_FRAME_W, \ ++/* 4 */ MIU_CLIENT_SC0_SNAPSHOT_W, \ ++/* 5 */ MIU_CLIENT_SC1_FRAME_W, \ ++/* 6 */ MIU_CLIENT_GOP0_R, \ ++/* 7 */ MIU_CLIENT_3DNR1_R, \ ++/* 8 */ MIU_CLIENT_3DNR1_W, \ ++/* 9 */ MIU_CLIENT_CMDQ2_R, \ ++/* A */ MIU_CLIENT_BDMA_RW, \ ++/* B */ MIU_CLIENT_AESDMA_RW, \ ++/* C */ MIU_CLIENT_USB20_RW, \ ++/* D */ MIU_CLIENT_USB20_H_RW, \ ++/* E */ MIU_CLIENT_MIIC1_RW, \ ++/* F */ MIU_CLIENT_URDMA_RW ++ ++#define MIU_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_VEN_R, \ ++/* 1 */ MIU_CLIENT_VEN_W, \ ++/* 2 */ MIU_CLIENT_JPE_W, \ ++/* 3 */ MIU_CLIENT_JPE_R, \ ++/* 4 */ MIU_CLIENT_DIP1_R, \ ++/* 5 */ MIU_CLIENT_DIP1_W, \ ++/* 6 */ MIU_CLIENT_GOP1_R, \ ++/* 7 */ MIU_CLIENT_BACH_RW, \ ++/* 8 */ MIU_CLIENT_BACH2_RW, \ ++/* 9 */ MIU_CLIENT_CMDQ3_R, \ ++/* A */ MIU_CLIENT_SDIO_RW, \ ++/* B */ MIU_CLIENT_FCIE_RW, \ ++/* C */ MIU_CLIENT_MIIC2_RW, \ ++/* D */ MIU_CLIENT_MIIC3_RW, \ ++/* E */ MIU_CLIENT_DUMMY_G3CE, \ ++/* F */ MIU_CLIENT_DUMMY_G3CF ++ ++#define MIU_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_DUMMY_G4C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G4C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G4C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G4C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G4C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G4C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G4C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G4C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G4C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G4C9, \ ++/* A */ MIU_CLIENT_DUMMY_G4CA, \ ++/* B */ MIU_CLIENT_DUMMY_G4CB, \ ++/* C */ MIU_CLIENT_DUMMY_G4CC, \ ++/* D */ MIU_CLIENT_DUMMY_G4CD, \ ++/* E */ MIU_CLIENT_DUMMY_G4CE, \ ++/* F */ MIU_CLIENT_DUMMY_G4CF ++ ++#define MIU_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_DUMMY_G5C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G5C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G5C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G5C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G5C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G5C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G5C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G5C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G5C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G5C9, \ ++/* A */ MIU_CLIENT_DUMMY_G5CA, \ ++/* B */ MIU_CLIENT_DUMMY_G5CB, \ ++/* C */ MIU_CLIENT_DUMMY_G5CC, \ ++/* D */ MIU_CLIENT_DUMMY_G5CD, \ ++/* E */ MIU_CLIENT_DUMMY_G5CE, \ ++/* F */ MIU_CLIENT_DUMMY_G5CF ++ ++#define MIU_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_DUMMY_G6C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G6C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G6C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G6C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G6C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G6C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G6C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G6C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G6C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G6C9, \ ++/* A */ MIU_CLIENT_DUMMY_G6CA, \ ++/* B */ MIU_CLIENT_DUMMY_G6CB, \ ++/* C */ MIU_CLIENT_DUMMY_G6CC, \ ++/* D */ MIU_CLIENT_DUMMY_G6CD, \ ++/* E */ MIU_CLIENT_DUMMY_G6CE, \ ++/* F */ MIU_CLIENT_DUMMY_G6CF ++ ++#define MIU_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_DUMMY_G7C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G7C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G7C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G7C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G7C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G7C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G7C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G7C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G7C9, \ ++/* A */ MIU_CLIENT_DUMMY_G7CA, \ ++/* B */ MIU_CLIENT_DUMMY_G7CB, \ ++/* C */ MIU_CLIENT_DUMMY_G7CC, \ ++/* D */ MIU_CLIENT_DUMMY_G7CD, \ ++/* E */ MIU_CLIENT_DUMMY_G7CE, \ ++/* F */ MIU_CLIENT_DUMMY_G7CF ++ ++#define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < ARM_MIU1_BASE_ADDR) \ ++ {MiuSel = E_MIU_0; Offset = PhysAddr - ARM_MIU0_BASE_ADDR;} \ ++ else if ((PhysAddr >= ARM_MIU1_BASE_ADDR) && (PhysAddr < ARM_MIU2_BASE_ADDR)) \ ++ {MiuSel = E_MIU_1; Offset = PhysAddr - ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {MiuSel = E_MIU_2; Offset = PhysAddr - ARM_MIU2_BASE_ADDR;} ++ ++#define MIU_HAL_ERR(fmt, args...) printk(KERN_ERR "miu hal error %s:%d" fmt,__FUNCTION__,__LINE__,## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++ ++const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] = ++{ ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ }, ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ } ++}; ++ ++static MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_MIIC2_RW, ++ MIU_CLIENT_MIIC3_RW, ++ MIU_CLIENT_IVE_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_SDIO_RW, ++ MIU_CLIENT_FCIE_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ 0, ++}; ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++static MS_U32 m_u32MiuMapBase = 0xFD200000UL; //default set to arm 32bit platform ++#elif defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++static ptrdiff_t m_u32MiuMapBase; ++#endif ++ ++static MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}, {{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++static MS_U16 IDList[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}, {0}}; //IDList for protection ++ ++//------------------------------------------------------------------------------------------------- ++// MTLB HAL internal function ++//------------------------------------------------------------------------------------------------- ++ ++static MS_U32 HAL_MIU_BA2PA(MS_U32 u32BusAddr) ++{ ++ MS_PHYADDR u32PhyAddr = 0x0UL; ++ ++ // pa = ba - offset ++ if ((u32BusAddr >= ARM_MIU0_BUS_BASE) && (u32BusAddr < ARM_MIU1_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU0_BUS_BASE + ARM_MIU0_BASE_ADDR; ++ else if ((u32BusAddr >= ARM_MIU1_BUS_BASE) && (u32BusAddr < ARM_MIU2_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU1_BUS_BASE + ARM_MIU1_BASE_ADDR; ++ else ++ u32PhyAddr = u32BusAddr - ARM_MIU2_BUS_BASE + ARM_MIU2_BASE_ADDR; ++ ++ return u32PhyAddr; ++} ++ ++static MS_S16 HAL_MIU_GetClientIndex(MS_U8 u8MiuSel, eMIUClientID eClientID) ++{ ++ MS_U8 idx = 0; ++ ++ if (MIU_MAX_DEVICE <= u8MiuSel) { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return (-1); ++ } ++ ++ for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++) { ++ if (eClientID == clientTbl[u8MiuSel][idx]) ++ return idx; ++ } ++ return (-1); ++} ++ ++static MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)]; ++} ++ ++static MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId]; ++} ++ ++static MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegProtectId, MS_U8 u8Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)] = u8Val; ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegProtectId, MS_U16 u16Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId] = u16Val; ++ ++ return TRUE; ++} ++ ++static void HAL_MIU_WriteByteMask(MS_U32 u32RegOffset, MS_U8 u8Mask, MS_BOOL bEnable) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(u32RegOffset); ++ ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_MIU_WriteByte(u32RegOffset, u8Val); ++} ++ ++static void HAL_MIU_Write2BytesMask(MS_U32 u32RegOffset, MS_U16 u16Mask, MS_BOOL bEnable) ++{ ++ MS_U16 u16Val = HAL_MIU_Read2Byte(u32RegOffset); ++ ++ u16Val = (bEnable) ? (u16Val | u16Mask) : (u16Val & ~u16Mask); ++ HAL_MIU_Write2Byte(u32RegOffset, u16Val); ++} ++ ++static void HAL_MIU_SetProtectIDReg(MS_U32 u32RegBase, MS_U8 u8MiuSel, MS_U16 u16ClientID) ++{ ++ MS_S16 sVal = HAL_MIU_GetClientIndex(u8MiuSel, (eMIUClientID)u16ClientID); ++ MS_S16 sIDVal = 0; ++ ++ if (0 > sVal) { ++ sVal = 0; ++ } ++ ++ sIDVal = HAL_MIU_ReadByte(u32RegBase); ++ sIDVal &= 0x80; ++ sIDVal |= sVal; ++ HAL_MIU_WriteByte(u32RegBase, sIDVal); ++} ++ ++static MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U16 u16ID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U8 u8isfound0, u8isfound1; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u16ID = pu8ProtectId[u32index0]; ++ ++ // Unused ID ++ if (u16ID == 0) ++ continue; ++ ++ u8isfound0 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == u16ID) ++ { ++ // ID reused former setting ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound0 = TRUE; ++ break; ++ } ++ } ++ ++ // Need to create new ID in IDList ++ if (u8isfound0 != TRUE) ++ { ++ u8isfound1 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == 0) ++ { ++ IDList[u8MiuSel][u32index1] = u16ID; ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound1 = TRUE; ++ break; ++ } ++ } ++ ++ // ID overflow ++ if (u8isfound1 == FALSE) { ++ return FALSE; ++ } ++ } ++ } ++ ++ u16IdEnable = 0; ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ if (IDEnables[u8MiuSel][u8Blockx][u32index0] == 1) { ++ u16IdEnable |= (1 << u32index0); ++ } ++ } ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U8 u8isIDNoUse = 0; ++ MS_U16 u16IdEnable = 0; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ u16IdEnable = 0x0UL; ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u8isIDNoUse = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++) ++ { ++ if (IDEnables[u8MiuSel][u32index1][u32index0] == 1) ++ { ++ // Protect ID is still be used ++ u8isIDNoUse = FALSE; ++ break; ++ } ++ u8isIDNoUse = TRUE; ++ } ++ ++ if (u8isIDNoUse == TRUE) { ++ IDList[u8MiuSel][u32index0] = 0; ++ } ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++#define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO) ++#define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID) ++ ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ MS_U16 u16Ret = 0; ++ MS_U16 u16LoAddr = 0; ++ MS_U16 u16HiAddr = 0; ++ MS_U32 u32RegBase = (u8MiuSel) ? MIU1_REG_BASE : MIU_REG_BASE; ++ MS_U32 u32EndAddr = 0; ++ char clientName[40]; ++ static MS_U16 u16HitCnt[MIU_MAX_DEVICE] = {0, }; ++ ++ if (!pInfo) { ++ return FALSE; ++ } ++ ++ u16Ret = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_STATUS); ++ u16LoAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_LOADDR); ++ u16HiAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_HIADDR); ++ ++ if (REG_MIU_PROTECT_HIT_FALG & u16Ret) ++ { ++ pInfo->bHit = TRUE; ++ pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(u16Ret); ++ pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(u16Ret) >> 4); ++ pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(u16Ret) & 0x0F); ++ pInfo->uAddress = (MS_U32)((u16HiAddr << 16) | u16LoAddr); ++ pInfo->uAddress = pInfo->uAddress * MIU_PROTECT_ADDRESS_UNIT; ++ ++ u32EndAddr = (pInfo->uAddress + MIU_PROTECT_ADDRESS_UNIT - 1); ++ ++ HAL_MIU_ClientIdToName((MS_U8)(GET_HIT_CLIENT(u16Ret)), clientName); ++ printk(KERN_EMERG "MIU%u Block:%u Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x\n", ++ u8MiuSel, pInfo->u8Block, clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr); ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // FIXME: Workaround for the unknown SC3_FRAME_W request even DMA disabled ++ if ((u16HitCnt[u8MiuSel] == 0) && (MIU_CLIENT_SC3_FRAME_W == GET_HIT_CLIENT(u16Ret))) ++ { ++ pInfo->bHit = FALSE; ++ } ++ // FIXME: Workaround for the unknown VEN_R request addr over DRAM size ++ if (MIU_CLIENT_VEN_R == GET_HIT_CLIENT(u16Ret)) ++ { ++ pInfo->bHit = FALSE; ++ } ++ u16HitCnt[u8MiuSel]++; ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuSel, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex) ++{ ++ return IDEnables[u8MiuSel][u8BlockId][u8ProtectIdIndex]; ++} ++ ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&clientId_KernelProtect[0]; ++ } ++ return NULL; ++} ++ ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&IDList[u8MiuSel][0]; ++ } ++ return NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4) ++/// @param *pu8ProtectId \b IN : Allow specified client IDList to write ++/// @param u32Start \b IN : Starting bus address ++/// @param u32End \b IN : End bus address ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegBase = 0; ++ MS_U32 u32RegStartAddr = 0; ++ MS_U32 u32RegAddrMSB = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ MS_U32 u32RegRWProtectEn = 0; ++ MS_U32 u32StartOffset = 0; ++ MS_U32 u32EndOffset = 0; ++ MS_U8 u8MiuSel = 0; ++ MS_U16 u16Data = 0; ++ MS_U16 u16Data1 = 0; ++ MS_U16 u16Data2 = 0; ++ MS_U8 u8Data = 0; ++ MS_U32 u32Start = 0, u32End = 0; ++ ++ u32Start = HAL_MIU_BA2PA(u32BusStart); ++ u32End = HAL_MIU_BA2PA(u32BusEnd); ++ ++ // Get MIU selection and offset ++ _phy_to_miu_offset(u8MiuSel, u32EndOffset, u32End); ++ _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32Start); ++ ++ u32Start = u32StartOffset; ++ u32End = u32EndOffset; ++ ++ // Parameter check ++ if (u8Blockx >= E_MIU_BLOCK_NUM) ++ { ++ MIU_HAL_ERR("Err: Blk Num out of range\n"); ++ return FALSE; ++ } ++ else if (((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ++ ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0)) ++ { ++ MIU_HAL_ERR("Err: Protected addr not 8KB aligned\n"); ++ return FALSE; ++ } ++ else if (u32Start >= u32End) ++ { ++ MIU_HAL_ERR("Err: Invalid end addr\n"); ++ return FALSE; ++ } ++ ++ // Write_enable ++ u8Data = 1 << u8Blockx; ++ ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegAddrMSB = MIU_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ ++ u32RegProtectId = MIU_PROTECT0_ID0; ++ u32RegRWProtectEn = MIU_PROTECT_EN_INTERNAL; ++ u32RegBase = MIU_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegStartAddr = MIU_PROTECT0_START; ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegStartAddr = MIU_PROTECT1_START; ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegStartAddr = MIU_PROTECT2_START; ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegStartAddr = MIU_PROTECT3_START; ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegAddrMSB = MIU1_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ ++ u32RegProtectId = MIU1_PROTECT0_ID0; ++ u32RegRWProtectEn = MIU1_PROTECT_EN; ++ u32RegBase = MIU1_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegStartAddr = MIU1_PROTECT0_START; ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegStartAddr = MIU1_PROTECT1_START; ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegStartAddr = MIU1_PROTECT2_START; ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegStartAddr = MIU1_PROTECT3_START; ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ // Disable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, DISABLE); ++ ++ if (bSetFlag) ++ { ++ // Set Protect IDList ++ if (HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn) == FALSE) ++ { ++ return FALSE; ++ } ++ ++ // Set BIT29,30 of start/end address ++ u16Data2 = u16Data2 | (MS_U16)((u32Start >> 29) << (u8Blockx*4)); // u16Data2 for start_ext addr ++ u16Data1 = u16Data2 | (MS_U16)(((u32End - 1) >> 29) << (u8Blockx*4+2)); ++ HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1); ++ ++ // Start Address ++ u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); // 8k unit ++ HAL_MIU_Write2Byte(u32RegStartAddr, u16Data); ++ ++ // End Address ++ u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); // 8k unit; ++ HAL_MIU_Write2Byte(u32RegStartAddr + 2, u16Data); ++ ++ // Enable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, ENABLE); ++ } ++ else ++ { ++ // Reset Protect IDList ++ HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource ++/// @brief \b Function \b Description: Parse occupied resource to software structure ++/// @return \b 0: Fail 1: OK ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) ++{ ++ MS_U8 u8MiuSel = 0; ++ MS_U8 u8Blockx = 0; ++ MS_U8 u8ClientID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U32 u32index = 0; ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ ++ for (u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ for (u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ { ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT0_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT0_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel); ++ return FALSE; ++ } ++ ++ u16IdEnable = HAL_MIU_Read2Byte(u32RegProtectIdEn); ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16IdEnable >> u32index) & 0x1UL) ? 1: 0; ++ } ++ } ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ u8ClientID = HAL_MIU_ReadByte(u32RegProtectId + u32index) & 0x7F; ++ IDList[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID]; ++ } ++ } ++ ++ return TRUE; ++} ++ ++unsigned int HAL_MIU_ProtectDramSize(void) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(MIU_PROTECT_DDR_SIZE); ++ ++ u8Val = (u8Val >> 4) & 0xF; ++ ++ if (0 == u8Val) { ++ MIU_HAL_ERR("MIU protect size undefined. Using 0x40000000\n"); ++ return 0x40000000; ++ } ++ return (0x1 << (20 + u8Val)); ++} ++ ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ int iRet = 0; ++ ++ if (!clientName) { ++ iRet = -1; ++ MIU_HAL_ERR("Wrong clientName\n"); ++ return iRet; ++ } ++ ++ switch(clientId) ++ { ++ // group 0 ++ case MIU_CLIENT_DIP0_R: ++ strcpy(clientName, "DIP0_R"); ++ break; ++ case MIU_CLIENT_DIP0_W: ++ strcpy(clientName, "DIP0_W"); ++ break; ++ case MIU_CLIENT_LDC_R: ++ strcpy(clientName, "LDC_R"); ++ break; ++ case MIU_CLIENT_SC2_FRAME_W: ++ strcpy(clientName, "SC2_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC3_FRAME_W: ++ strcpy(clientName, "SC3_FRAME_W"); ++ break; ++ case MIU_CLIENT_RSC_R: ++ strcpy(clientName, "RSC_R"); ++ break; ++ case MIU_CLIENT_SC1_DBG_R: ++ strcpy(clientName, "SC_DBG_R"); ++ break; ++ case MIU_CLIENT_CMDQ0_R: ++ strcpy(clientName, "CMDQ0_R"); ++ break; ++ case MIU_CLIENT_MOVDMA0_RW: ++ strcpy(clientName, "MDMA0_RW"); ++ break; ++ case MIU_CLIENT_EMAC_RW: ++ strcpy(clientName, "EMAC_RW"); ++ break; ++ case MIU_CLIENT_2DGE_RW: ++ strcpy(clientName, "2DGE_RW"); ++ break; ++ case MIU_CLIENT_3DNR0_R: ++ strcpy(clientName, "3DNR0_R"); ++ break; ++ case MIU_CLIENT_3DNR0_W: ++ strcpy(clientName, "3DNR0_W"); ++ break; ++ case MIU_CLIENT_GOP4_R: ++ strcpy(clientName, "GOP4_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CF: ++ strcpy(clientName, "DUMMY_G0CF"); ++ break; ++ // group 1 ++ case MIU_CLIENT_ISP_DMAG0_RW: ++ strcpy(clientName, "ISP_DMAG0_RW"); ++ break; ++ case MIU_CLIENT_ISP_DMAG1_RW: ++ strcpy(clientName, "ISP_DMAG1_RW"); ++ break; ++ case MIU_CLIENT_ISP_DMAG2_RW: ++ strcpy(clientName, "ISP_DMAG2_RW"); ++ break; ++ case MIU_CLIENT_GOP2_R: ++ strcpy(clientName, "GOP2_R"); ++ break; ++ case MIU_CLIENT_GOP3_R: ++ strcpy(clientName, "GOP3_R"); ++ break; ++ case MIU_CLIENT_ISP_DMAG_RW: ++ strcpy(clientName, "ISP_DMAG_RW"); ++ break; ++ case MIU_CLIENT_ISP_AF_STA1_W: ++ strcpy(clientName, "ISP_AF_STA1_W"); ++ break; ++ case MIU_CLIENT_ISP_MLOAD_RW: ++ strcpy(clientName, "ISP_MLOAD_RW"); ++ break; ++ case MIU_CLIENT_CMDQ1_R: ++ strcpy(clientName, "CMDQ1_R"); ++ break; ++ case MIU_CLIENT_MOVDMA1_RW: ++ strcpy(clientName, "MDMA1_RW"); ++ break; ++ case MIU_CLIENT_MCU51_RW: ++ strcpy(clientName, "MCU51_RW"); ++ break; ++ case MIU_CLIENT_DLA_RW: ++ strcpy(clientName, "DLA_RW"); ++ break; ++ case MIU_CLIENT_IVE_RW: ++ strcpy(clientName, "IVE_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CD: ++ strcpy(clientName, "DUMMY_G1CD"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CE: ++ strcpy(clientName, "DUMMY_G1CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CF: ++ strcpy(clientName, "DUMMY_G1CF"); ++ break; ++ // group 2 ++ case MIU_CLIENT_DUMMY_G2C0: ++ strcpy(clientName, "DUMMY_G2C0"); ++ break; ++ case MIU_CLIENT_SC_ROT_R: ++ strcpy(clientName, "SC_ROT_R"); ++ break; ++ case MIU_CLIENT_SC_AIP_W: ++ strcpy(clientName, "SC_AIP_W"); ++ break; ++ case MIU_CLIENT_SC0_FRAME_W: ++ strcpy(clientName, "SC0_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC0_SNAPSHOT_W: ++ strcpy(clientName, "SC0_SNP_W"); ++ break; ++ case MIU_CLIENT_SC1_FRAME_W: ++ strcpy(clientName, "SC1_FRAME_W"); ++ break; ++ case MIU_CLIENT_GOP0_R: ++ strcpy(clientName, "GOP0_R"); ++ break; ++ case MIU_CLIENT_3DNR1_R: ++ strcpy(clientName, "3DNR1_R"); ++ break; ++ case MIU_CLIENT_3DNR1_W: ++ strcpy(clientName, "3DNR1_W"); ++ break; ++ case MIU_CLIENT_CMDQ2_R: ++ strcpy(clientName, "CMDQ2_R"); ++ break; ++ case MIU_CLIENT_BDMA_RW: ++ strcpy(clientName, "BDMA_RW"); ++ break; ++ case MIU_CLIENT_AESDMA_RW: ++ strcpy(clientName, "AESDMA_RW"); ++ break; ++ case MIU_CLIENT_USB20_RW: ++ strcpy(clientName, "USB20_RW"); ++ break; ++ case MIU_CLIENT_USB20_H_RW: ++ strcpy(clientName, "USB20_H_RW"); ++ break; ++ case MIU_CLIENT_MIIC1_RW: ++ strcpy(clientName, "MIIC1_RW"); ++ break; ++ case MIU_CLIENT_URDMA_RW: ++ strcpy(clientName, "URDMA_RW"); ++ break; ++ // group 3 ++ case MIU_CLIENT_VEN_R: ++ strcpy(clientName, "VEN_R"); ++ break; ++ case MIU_CLIENT_VEN_W: ++ strcpy(clientName, "VEN_W"); ++ break; ++ case MIU_CLIENT_JPE_W: ++ strcpy(clientName, "JPE_W"); ++ break; ++ case MIU_CLIENT_JPE_R: ++ strcpy(clientName, "JPE_R"); ++ break; ++ case MIU_CLIENT_DIP1_R: ++ strcpy(clientName, "DIP1_R"); ++ break; ++ case MIU_CLIENT_DIP1_W: ++ strcpy(clientName, "DIP1_W"); ++ break; ++ case MIU_CLIENT_GOP1_R: ++ strcpy(clientName, "GOP1_R"); ++ break; ++ case MIU_CLIENT_BACH_RW: ++ strcpy(clientName, "BACH_RW"); ++ break; ++ case MIU_CLIENT_BACH2_RW: ++ strcpy(clientName, "BACH2_RW"); ++ break; ++ case MIU_CLIENT_CMDQ3_R: ++ strcpy(clientName, "CMDQ3_R"); ++ break; ++ case MIU_CLIENT_SDIO_RW: ++ strcpy(clientName, "SDIO_RW"); ++ break; ++ case MIU_CLIENT_FCIE_RW: ++ strcpy(clientName, "FCIE_RW"); ++ break; ++ case MIU_CLIENT_MIIC2_RW: ++ strcpy(clientName, "MIIC2_RW"); ++ break; ++ case MIU_CLIENT_MIIC3_RW: ++ strcpy(clientName, "MIIC3_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G3CE: ++ strcpy(clientName, "DUMMY_G3CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G3CF: ++ strcpy(clientName, "DUMMY_G3CF"); ++ break; ++ // DIAMOND ++ case MIU_CLIENT_MIPS_RW: ++ strcpy(clientName, "CPU_RW"); ++ break; ++ default: ++ MIU_HAL_ERR("Wrong clientId %d\n", clientId); ++ iRet = -1; ++ break; ++ } ++ return iRet; ++} ++ ++int clientId_KernelProtectToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++EXPORT_SYMBOL(clientId_KernelProtectToName); ++ ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ printk("Not support HAL_MIU_Info in this platform\n"); ++ ++ return -1; ++} +diff --git a/drivers/sstar/miu/infinity6/mdrv_miu.c b/drivers/sstar/miu/infinity6/mdrv_miu.c +new file mode 100755 +index 000000000000..823233d56b38 +--- /dev/null ++++ b/drivers/sstar/miu/infinity6/mdrv_miu.c +@@ -0,0 +1,375 @@ ++/* ++* mdrv_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "MsTypes.h" ++#include "mdrv_miu.h" ++#include "mhal_miu.h" ++#include "regMIU.h" ++#include ++#include "irqs.h" ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_MSTAR_MONET) || defined(CONFIG_MSTAR_MESSI) || defined(CONFIG_MSTAR_MASERATI) || defined(CONFIG_MSTAR_MANHATTAN) || defined(CONFIG_MSTAR_KANO) ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY phy64Start, MS_PHY phy64End, MS_BOOL bSetFlag) __attribute__((weak)); ++#else ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, MS_U32 u32BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++#endif ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) __attribute__((weak)); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) __attribute__((weak)); ++ ++MS_BOOL HAL_MIU_SlitInit(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SetSlitRange(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY u64BusStart, MS_PHY u64BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++MS_BOOL HAL_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++ ++#ifndef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static struct timer_list monitor_timer; ++#endif ++static int bMiuProtect_is_initialized = 0; ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static int MiuSelId[MIU_MAX_DEVICE] = {0}; ++#endif ++ ++static DEFINE_SPINLOCK(miu_lock); ++MS_U8 u8_MiuWhiteListNum = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Local functions ++//------------------------------------------------------------------------------------------------- ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Init ++/// @brief \b Function \b Description: parse occupied resource to software structure ++/// @param None \b IN : ++/// @param None \b OUT : ++/// @param MS_BOOL \b RET ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Init(void) ++{ ++ MS_BOOL ret = FALSE; ++ ++ /* Parse the used client ID in hardware into software data structure */ ++ if (HAL_MIU_ParseOccupiedResource) { ++ ret = HAL_MIU_ParseOccupiedResource(); ++ } ++ else { ++ ret = FALSE; ++ } ++ ++ /* Initialize MIU slit setting */ ++ if (HAL_MIU_SlitInit) { ++ ret = HAL_MIU_SlitInit(); ++ } ++ ++ u8_MiuWhiteListNum = IDNUM_KERNELPROTECT; ++ ++ return ret; ++} ++ ++MS_BOOL MDrv_MIU_GetProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ return HAL_MIU_GetHitProtectInfo(u8MiuSel, pInfo); ++} ++ ++MS_BOOL MDrv_MIU_Get_IDEnables_Value(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 u8ClientIndex) ++{ ++ return HAL_MIU_GetProtectIdEnVal(u8MiuSel, u8Blockx, u8ClientIndex); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* MDrv_MIU_GetDefaultClientID_KernelProtect(void) ++{ ++ if (HAL_MIU_GetDefaultKernelProtectClientID) { ++ return HAL_MIU_GetDefaultKernelProtectClientID(); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++MS_U16* MDrv_MIU_GetClientID_KernelProtect(MS_U8 u8MiuSel) ++{ ++ if (HAL_MIU_GetKernelProtectClientID) { ++ return HAL_MIU_GetKernelProtectClientID(u8MiuSel); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static irqreturn_t MDrv_MIU_Protect_interrupt(s32 irq, void *dev_id) ++{ ++ MS_U8 u8MiuSel = *(MS_U8 *)dev_id; ++ MIU_PortectInfo pInfo; ++ ++ memset(&pInfo, 0, sizeof(pInfo)); ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &pInfo); ++ ++ if(pInfo.bHit) ++ BUG(); ++ else ++ printk (KERN_EMERG "in miu hit interrupt, but bHit not match\n"); ++ ++ return IRQ_HANDLED; ++} ++#else ++//create timer process ++static void MDev_timer_callback(unsigned long value) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo stProtInfo; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) { ++ stProtInfo.bHit = FALSE; ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &stProtInfo); ++ if (stProtInfo.bHit) { ++ panic("MIU %d Protect hit!\n", u8MiuSel); ++ } ++ } ++ mod_timer(&monitor_timer, jiffies+1*HZ); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 3) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_PHY u64BusStart, ++ MS_PHY u64BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_BOOL Result = FALSE; ++ ++ /* Case of former MIU protect */ ++ if ((u8Blockx >= E_PROTECT_0) && (u8Blockx < E_SLIT_0)) ++ { ++ if (HAL_MIU_Protect) { ++ if (TRUE != (Result = HAL_MIU_Protect(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ /* Case of MIU slits */ ++ else if (u8Blockx == E_SLIT_0) ++ { ++ if (HAL_MIU_SetSlitRange) { ++ if (TRUE != (Result = HAL_MIU_SetSlitRange(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ ++ ++ if(!bMiuProtect_is_initialized) ++ { ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ struct device_node *dev_node = NULL; ++ MS_U8 u8MiuSel = 0; ++ int rc = 0; ++ int iIrqNum = 0; ++ char compat_str[32] = {0}; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ if (u8MiuSel == 0) ++ { ++ snprintf(compat_str, sizeof(compat_str)-1, "sstar,miu"); ++ } ++ else ++ { ++ snprintf(compat_str, sizeof(compat_str)-1, "sstar,miu%d", u8MiuSel); ++ } ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compat_str); ++ if (!dev_node) ++ { ++ printk("[MIU Protecrt] find node Fail\r\n"); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ MiuSelId[u8MiuSel] = u8MiuSel; ++ ++ if(0 != (rc = request_irq(iIrqNum, MDrv_MIU_Protect_interrupt, IRQF_TRIGGER_HIGH, "MIU_Protect", (void *)&MiuSelId[u8MiuSel]))) ++ { ++ printk("[MIU Protecrt] request_irq [%d] Fail, Err:%d\r\n", iIrqNum, rc); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++#else ++ init_timer(&monitor_timer); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++#endif ++ bMiuProtect_is_initialized++; ++ } ++ ++ ++MDrv_MIU_Protect_Exit: ++ return Result; ++} ++ ++unsigned int MDrv_MIU_ProtectDramSize(void) ++{ ++ return HAL_MIU_ProtectDramSize(); ++} ++ ++int MDrv_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++ ++MS_BOOL MDrv_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) ++{ ++ unsigned long flags; ++ MS_BOOL Result = FALSE; ++ ++ spin_lock_irqsave(&miu_lock, flags); ++ ++ if (HAL_MIU_Slits) { ++ Result = HAL_MIU_Slits(u8Blockx, u64SlitsStart, u64SlitsEnd, bSetFlag); ++ } ++ ++ spin_unlock_irqrestore(&miu_lock, flags); ++ ++ return Result; ++} ++ ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo) ++{ ++ return HAL_MIU_Info((MIU_DramInfo_Hal *)pDramInfo); ++} ++ ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(MDrv_MIU_Init); ++EXPORT_SYMBOL(u8_MiuWhiteListNum); ++EXPORT_SYMBOL(MDrv_MIU_GetDefaultClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_GetClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_Protect); ++#endif ++EXPORT_SYMBOL(MDrv_MIU_Get_IDEnables_Value); ++EXPORT_SYMBOL(MDrv_MIU_Info); ++ ++static int mstar_miu_drv_probe(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstarmiu_of_device_ids[] = { ++ {.compatible = "sstar-miu"}, ++ {}, ++}; ++#endif ++ ++static struct platform_driver Sstar_miu_driver = { ++ .probe = mstar_miu_drv_probe, ++ .remove = mstar_miu_drv_remove, ++ .suspend = mstar_miu_drv_suspend, ++ .resume = mstar_miu_drv_resume, ++ .driver = { ++ .name = "Sstar-miu", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstarmiu_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_miu_drv_init_module(void) ++{ ++ int ret = 0; ++ ++ ret = platform_driver_register(&Sstar_miu_driver); ++ ++ if (ret) { ++ printk("Register MIU Driver Fail"); ++ } ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Sstar_miu_driver); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/miu/infinity6/mhal_miu.c b/drivers/sstar/miu/infinity6/mhal_miu.c +new file mode 100755 +index 000000000000..f35a2819fe0a +--- /dev/null ++++ b/drivers/sstar/miu/infinity6/mhal_miu.c +@@ -0,0 +1,1115 @@ ++/* ++* mhal_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#if defined(CONFIG_COMPAT) ++#include ++#endif ++#include "MsTypes.h" ++#include "mdrv_types.h" ++#include "mdrv_miu.h" ++#include "mdrv_system.h" ++#include "regMIU.h" ++#include "mhal_miu.h" ++#include "registers.h" ++#include "ms_platform.h" ++#ifdef CONFIG_CAM_CLK ++#include "camclk.h" ++#include "drv_camclk_Api.h" ++#endif ++//------------------------------------------------------------------------------------------------- ++// Macro Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_VEN_R, \ ++/* 2 */ MIU_CLIENT_VEN_W, \ ++/* 3 */ MIU_CLIENT_DUMMY_G0C3, \ ++/* 4 */ MIU_CLIENT_JPE_R, \ ++/* 5 */ MIU_CLIENT_JPE_W, \ ++/* 6 */ MIU_CLIENT_BACH_RW, \ ++/* 7 */ MIU_CLIENT_AESDMA_RW, \ ++/* 8 */ MIU_CLIENT_USB20_RW, \ ++/* 9 */ MIU_CLIENT_EMAC_RW, \ ++/* A */ MIU_CLIENT_MCU51_RW, \ ++/* B */ MIU_CLIENT_URDMA_RW, \ ++/* C */ MIU_CLIENT_BDMA_RW, \ ++/* D */ MIU_CLIENT_MOVDMA0_RW, \ ++/* E */ MIU_CLIENT_DUMMY_G0CE, \ ++/* F */ MIU_CLIENT_DUMMY_G0CF ++ ++#define MIU_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_CMDQ0_R, \ ++/* 1 */ MIU_CLIENT_ISP_DMA_W, \ ++/* 2 */ MIU_CLIENT_ISP_DMA_R, \ ++/* 3 */ MIU_CLIENT_ISP_ROT_R, \ ++/* 4 */ MIU_CLIENT_ISP_MLOAD_STA, \ ++/* 5 */ MIU_CLIENT_GOP, \ ++/* 6 */ MIU_CLIENT_DUMMY_G1C6, \ ++/* 7 */ MIU_CLIENT_DIP0_R, \ ++/* 8 */ MIU_CLIENT_DIP0_W, \ ++/* 9 */ MIU_CLIENT_SC0_FRAME_W, \ ++/* A */ MIU_CLIENT_DUMMY_G1CA, \ ++/* B */ MIU_CLIENT_SC0_DBG_R, \ ++/* C */ MIU_CLIENT_SC1_FRAME_W, \ ++/* D */ MIU_CLIENT_SC2_FRAME_W, \ ++/* E */ MIU_CLIENT_SD30_RW, \ ++/* F */ MIU_CLIENT_SDIO30_RW ++ ++#define MIU_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_CMDQ1_R, \ ++/* 1 */ MIU_CLIENT_CMDQ2_R, \ ++/* 2 */ MIU_CLIENT_DUMMY_G2C2, \ ++/* 3 */ MIU_CLIENT_ISP_DMAG_RW, \ ++/* 4 */ MIU_CLIENT_GOP1_R, \ ++/* 5 */ MIU_CLIENT_GOP2_R, \ ++/* 6 */ MIU_CLIENT_USB20_H_RW, \ ++/* 7 */ MIU_CLIENT_DUMMY_G2C7, \ ++/* 8 */ MIU_CLIENT_MIIC1_RW, \ ++/* 9 */ MIU_CLIENT_3DNR0_W, \ ++/* A */ MIU_CLIENT_3DNR0_R, \ ++/* B */ MIU_CLIENT_DUMMY_G2CB, \ ++/* C */ MIU_CLIENT_DUMMY_G2CC, \ ++/* D */ MIU_CLIENT_DUMMY_G2CD, \ ++/* E */ MIU_CLIENT_DUMMY_G2CE, \ ++/* F */ MIU_CLIENT_DUMMY_G2CF ++ ++#define MIU_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_DUMMY_G3C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G3C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G3C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G3C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G3C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G3C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G3C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G3C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G3C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G3C9, \ ++/* A */ MIU_CLIENT_DUMMY_G3CA, \ ++/* B */ MIU_CLIENT_DUMMY_G3CB, \ ++/* C */ MIU_CLIENT_DUMMY_G3CC, \ ++/* D */ MIU_CLIENT_DUMMY_G3CD, \ ++/* E */ MIU_CLIENT_DUMMY_G3CE, \ ++/* F */ MIU_CLIENT_DUMMY_G3CF ++ ++#define MIU_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_DUMMY_G4C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G4C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G4C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G4C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G4C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G4C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G4C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G4C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G4C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G4C9, \ ++/* A */ MIU_CLIENT_DUMMY_G4CA, \ ++/* B */ MIU_CLIENT_DUMMY_G4CB, \ ++/* C */ MIU_CLIENT_DUMMY_G4CC, \ ++/* D */ MIU_CLIENT_DUMMY_G4CD, \ ++/* E */ MIU_CLIENT_DUMMY_G4CE, \ ++/* F */ MIU_CLIENT_DUMMY_G4CF ++ ++#define MIU_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_DUMMY_G5C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G5C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G5C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G5C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G5C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G5C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G5C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G5C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G5C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G5C9, \ ++/* A */ MIU_CLIENT_DUMMY_G5CA, \ ++/* B */ MIU_CLIENT_DUMMY_G5CB, \ ++/* C */ MIU_CLIENT_DUMMY_G5CC, \ ++/* D */ MIU_CLIENT_DUMMY_G5CD, \ ++/* E */ MIU_CLIENT_DUMMY_G5CE, \ ++/* F */ MIU_CLIENT_DUMMY_G5CF ++ ++#define MIU_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_DUMMY_G6C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G6C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G6C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G6C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G6C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G6C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G6C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G6C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G6C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G6C9, \ ++/* A */ MIU_CLIENT_DUMMY_G6CA, \ ++/* B */ MIU_CLIENT_DUMMY_G6CB, \ ++/* C */ MIU_CLIENT_DUMMY_G6CC, \ ++/* D */ MIU_CLIENT_DUMMY_G6CD, \ ++/* E */ MIU_CLIENT_DUMMY_G6CE, \ ++/* F */ MIU_CLIENT_DUMMY_G6CF ++ ++#define MIU_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_DUMMY_G7C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G7C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G7C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G7C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G7C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G7C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G7C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G7C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G7C9, \ ++/* A */ MIU_CLIENT_DUMMY_G7CA, \ ++/* B */ MIU_CLIENT_DUMMY_G7CB, \ ++/* C */ MIU_CLIENT_DUMMY_G7CC, \ ++/* D */ MIU_CLIENT_DUMMY_G7CD, \ ++/* E */ MIU_CLIENT_DUMMY_G7CE, \ ++/* F */ MIU_CLIENT_DUMMY_G7CF ++ ++#define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < ARM_MIU1_BASE_ADDR) \ ++ {MiuSel = E_MIU_0; Offset = PhysAddr - ARM_MIU0_BASE_ADDR;} \ ++ else if ((PhysAddr >= ARM_MIU1_BASE_ADDR) && (PhysAddr < ARM_MIU2_BASE_ADDR)) \ ++ {MiuSel = E_MIU_1; Offset = PhysAddr - ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {MiuSel = E_MIU_2; Offset = PhysAddr - ARM_MIU2_BASE_ADDR;} ++ ++#define MIU_HAL_ERR(fmt, args...) printk(KERN_ERR "miu hal error %s:%d" fmt,__FUNCTION__,__LINE__,## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++ ++const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] = ++{ ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ } ++}; ++ ++static MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SDIO30_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ 0, ++}; ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++static MS_U32 m_u32MiuMapBase = 0xFD200000UL; //default set to arm 32bit platform ++#elif defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++static ptrdiff_t m_u32MiuMapBase; ++#endif ++ ++static MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++static MS_U16 IDList[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}}; //IDList for protection ++ ++//------------------------------------------------------------------------------------------------- ++// MTLB HAL internal function ++//------------------------------------------------------------------------------------------------- ++ ++static MS_U32 HAL_MIU_BA2PA(MS_U32 u32BusAddr) ++{ ++ MS_PHYADDR u32PhyAddr = 0x0UL; ++ ++ // pa = ba - offset ++ if ((u32BusAddr >= ARM_MIU0_BUS_BASE) && (u32BusAddr < ARM_MIU1_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU0_BUS_BASE + ARM_MIU0_BASE_ADDR; ++ else if ((u32BusAddr >= ARM_MIU1_BUS_BASE) && (u32BusAddr < ARM_MIU2_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU1_BUS_BASE + ARM_MIU1_BASE_ADDR; ++ else ++ u32PhyAddr = u32BusAddr - ARM_MIU2_BUS_BASE + ARM_MIU2_BASE_ADDR; ++ ++ return u32PhyAddr; ++} ++ ++static MS_S16 HAL_MIU_GetClientIndex(MS_U8 u8MiuSel, eMIUClientID eClientID) ++{ ++ MS_U8 idx = 0; ++ ++ if (MIU_MAX_DEVICE <= u8MiuSel) { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return (-1); ++ } ++ ++ for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++) { ++ if (eClientID == clientTbl[u8MiuSel][idx]) ++ return idx; ++ } ++ return (-1); ++} ++ ++static MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)]; ++} ++ ++static MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId]; ++} ++ ++static MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegProtectId, MS_U8 u8Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)] = u8Val; ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegProtectId, MS_U16 u16Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId] = u16Val; ++ ++ return TRUE; ++} ++ ++static void HAL_MIU_WriteByteMask(MS_U32 u32RegOffset, MS_U8 u8Mask, MS_BOOL bEnable) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(u32RegOffset); ++ ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_MIU_WriteByte(u32RegOffset, u8Val); ++} ++ ++static void HAL_MIU_Write2BytesMask(MS_U32 u32RegOffset, MS_U16 u16Mask, MS_BOOL bEnable) ++{ ++ MS_U16 u16Val = HAL_MIU_Read2Byte(u32RegOffset); ++ ++ u16Val = (bEnable) ? (u16Val | u16Mask) : (u16Val & ~u16Mask); ++ HAL_MIU_Write2Byte(u32RegOffset, u16Val); ++} ++ ++static void HAL_MIU_SetProtectIDReg(MS_U32 u32RegBase, MS_U8 u8MiuSel, MS_U16 u16ClientID) ++{ ++ MS_S16 sVal = HAL_MIU_GetClientIndex(u8MiuSel, (eMIUClientID)u16ClientID); ++ MS_S16 sIDVal = 0; ++ ++ if (0 > sVal) { ++ sVal = 0; ++ } ++ ++ sIDVal = HAL_MIU_ReadByte(u32RegBase); ++ sIDVal &= 0x80; ++ sIDVal |= sVal; ++ HAL_MIU_WriteByte(u32RegBase, sIDVal); ++} ++ ++static MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U16 u16ID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U8 u8isfound0, u8isfound1; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u16ID = pu8ProtectId[u32index0]; ++ ++ // Unused ID ++ if (u16ID == 0) ++ continue; ++ ++ u8isfound0 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == u16ID) ++ { ++ // ID reused former setting ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound0 = TRUE; ++ break; ++ } ++ } ++ ++ // Need to create new ID in IDList ++ if (u8isfound0 != TRUE) ++ { ++ u8isfound1 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == 0) ++ { ++ IDList[u8MiuSel][u32index1] = u16ID; ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound1 = TRUE; ++ break; ++ } ++ } ++ ++ // ID overflow ++ if (u8isfound1 == FALSE) { ++ return FALSE; ++ } ++ } ++ } ++ ++ u16IdEnable = 0; ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ if (IDEnables[u8MiuSel][u8Blockx][u32index0] == 1) { ++ u16IdEnable |= (1 << u32index0); ++ } ++ } ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U8 u8isIDNoUse = 0; ++ MS_U16 u16IdEnable = 0; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ u16IdEnable = 0x0UL; ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u8isIDNoUse = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++) ++ { ++ if (IDEnables[u8MiuSel][u32index1][u32index0] == 1) ++ { ++ // Protect ID is still be used ++ u8isIDNoUse = FALSE; ++ break; ++ } ++ u8isIDNoUse = TRUE; ++ } ++ ++ if (u8isIDNoUse == TRUE) { ++ IDList[u8MiuSel][u32index0] = 0; ++ } ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++#define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO) ++#define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID) ++ ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ MS_U16 u16Ret = 0; ++ MS_U16 u16LoAddr = 0; ++ MS_U16 u16HiAddr = 0; ++ MS_U32 u32RegBase = (u8MiuSel) ? MIU1_REG_BASE : MIU_REG_BASE; ++ MS_U32 u32EndAddr = 0; ++ char clientName[40]; ++ if (!pInfo) { ++ return FALSE; ++ } ++ ++ u16Ret = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_STATUS); ++ u16LoAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_LOADDR); ++ u16HiAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_HIADDR); ++ ++ if (REG_MIU_PROTECT_HIT_FALG & u16Ret) ++ { ++ pInfo->bHit = TRUE; ++ pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(u16Ret); ++ pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(u16Ret) >> 4); ++ pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(u16Ret) & 0x0F); ++ pInfo->uAddress = (MS_U32)((u16HiAddr << 16) | u16LoAddr); ++ pInfo->uAddress = pInfo->uAddress * MIU_PROTECT_ADDRESS_UNIT; ++ ++ u32EndAddr = (pInfo->uAddress + MIU_PROTECT_ADDRESS_UNIT - 1); ++ ++ HAL_MIU_ClientIdToName((MS_U8)(GET_HIT_CLIENT(u16Ret)), clientName); ++ ++ if (pInfo->u8Block == 6 || pInfo->u8Block == 7) ++ { ++ printk(KERN_EMERG "MIU%u %s Out of Range Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x (Valid Range: 0x00000000 ~ 0x%08X)\n", ++ u8MiuSel, (pInfo->u8Block == 6)? "Read" : "Write", clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr, HAL_MIU_ProtectDramSize()); ++ } ++ else ++ { ++ printk(KERN_EMERG "MIU%u Block:%u Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x\n", ++ u8MiuSel, pInfo->u8Block, clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // FIXME: Workaround for the unknown VEN_R request addr over DRAM size ++ if (MIU_CLIENT_VEN_R == GET_HIT_CLIENT(u16Ret)) ++ { ++ pInfo->bHit = FALSE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuSel, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex) ++{ ++ return IDEnables[u8MiuSel][u8BlockId][u8ProtectIdIndex]; ++} ++ ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&clientId_KernelProtect[0]; ++ } ++ return NULL; ++} ++ ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&IDList[u8MiuSel][0]; ++ } ++ return NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4) ++/// @param *pu8ProtectId \b IN : Allow specified client IDList to write ++/// @param u32Start \b IN : Starting bus address ++/// @param u32End \b IN : End bus address ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegBase = 0; ++ MS_U32 u32RegStartAddr = 0; ++ MS_U32 u32RegStartEnd = 0; ++ MS_U32 u32RegAddrMSB = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ MS_U32 u32RegRWProtectEn = 0; ++ MS_U32 u32StartOffset = 0; ++ MS_U32 u32EndOffset = 0; ++ MS_U8 u8MiuSel = 0; ++ MS_U16 u16Data = 0; ++ MS_U16 u16Data1 = 0; ++ MS_U16 u16Data2 = 0; ++ MS_U8 u8Data = 0; ++ MS_U32 u32Start = 0, u32End = 0; ++ ++ u32Start = HAL_MIU_BA2PA(u32BusStart); ++ u32End = HAL_MIU_BA2PA(u32BusEnd); ++ ++ // Get MIU selection and offset ++ _phy_to_miu_offset(u8MiuSel, u32EndOffset, u32End); ++ _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32Start); ++ ++ u32Start = u32StartOffset; ++ u32End = u32EndOffset; ++ ++ // Parameter check ++ if (u8Blockx >= E_MIU_BLOCK_NUM) ++ { ++ MIU_HAL_ERR("Err: Blk Num out of range\n"); ++ return FALSE; ++ } ++ else if (((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ++ ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0)) ++ { ++ MIU_HAL_ERR("Err: Protected addr not 8KB aligned\n"); ++ return FALSE; ++ } ++ else if (u32Start >= u32End) ++ { ++ MIU_HAL_ERR("Err: Invalid end addr\n"); ++ return FALSE; ++ } ++ ++ ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ u32RegBase = MIU_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT0_EN; ++ u32RegStartAddr = MIU_PROTECT0_START; ++ u32RegStartEnd = MIU_PROTECT0_END; ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU_PROTECT1_EN; ++ u32RegStartAddr = MIU_PROTECT1_START; ++ u32RegStartEnd = MIU_PROTECT1_END; ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU_PROTECT2_EN; ++ u32RegStartAddr = MIU_PROTECT2_START; ++ u32RegStartEnd = MIU_PROTECT2_END; ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU_PROTECT3_EN; ++ u32RegStartAddr = MIU_PROTECT3_START; ++ u32RegStartEnd = MIU_PROTECT3_END; ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT4_EN; ++ u32RegStartAddr = MIU_PROTECT4_START; ++ u32RegStartEnd = MIU_PROTECT4_END; ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ u32RegBase = MIU1_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT0_EN; ++ u32RegStartAddr = MIU1_PROTECT0_START; ++ u32RegStartEnd = MIU1_PROTECT0_END; ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU1_PROTECT1_EN; ++ u32RegStartAddr = MIU1_PROTECT1_START; ++ u32RegStartEnd = MIU1_PROTECT1_END; ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU1_PROTECT2_EN; ++ u32RegStartAddr = MIU1_PROTECT2_START; ++ u32RegStartEnd = MIU1_PROTECT2_END; ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU1_PROTECT3_EN; ++ u32RegStartAddr = MIU1_PROTECT3_START; ++ u32RegStartEnd = MIU1_PROTECT3_END; ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT4_EN; ++ u32RegStartAddr = MIU1_PROTECT4_START; ++ u32RegStartEnd = MIU1_PROTECT4_END; ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ // Disable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, DISABLE); ++ ++ if (bSetFlag) ++ { ++ // Set Protect IDList ++ if (HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn) == FALSE) ++ { ++ return FALSE; ++ } ++ ++ // Set BIT29,30 of start/end address ++ u16Data2 = u16Data2 | (MS_U16)((u32Start >> 29) << ((u8Blockx%4)*4)); // u16Data2 for start_ext addr ++ u16Data1 = u16Data2 | (MS_U16)(((u32End - 1) >> 29) << ((u8Blockx%4)*4+2)); ++ HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1); ++ ++ // Start Address ++ u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); // 8k unit ++ HAL_MIU_Write2Byte(u32RegStartAddr, u16Data); ++ ++ // End Address ++ u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); // 8k unit; ++ HAL_MIU_Write2Byte(u32RegStartEnd, u16Data); ++ ++ // Enable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, ENABLE); ++ } ++ else ++ { ++ // Reset Protect IDList ++ HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // Mask PWR IRQ ++ HAL_MIU_Write2BytesMask(REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET, REG_MIU_PROTECT_PWR_IRQ_MASK_BIT, TRUE); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource ++/// @brief \b Function \b Description: Parse occupied resource to software structure ++/// @return \b 0: Fail 1: OK ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) ++{ ++ MS_U8 u8MiuSel = 0; ++ MS_U8 u8Blockx = 0; ++ MS_U8 u8ClientID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U32 u32index = 0; ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ ++ for (u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ for (u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ { ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel); ++ return FALSE; ++ } ++ ++ u16IdEnable = HAL_MIU_Read2Byte(u32RegProtectIdEn); ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16IdEnable >> u32index) & 0x1UL) ? 1: 0; ++ } ++ } ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ u8ClientID = HAL_MIU_ReadByte(u32RegProtectId + u32index) & 0x7F; ++ IDList[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID]; ++ } ++ } ++ ++ return TRUE; ++} ++ ++unsigned int HAL_MIU_ProtectDramSize(void) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(MIU_PROTECT_DDR_SIZE); ++ ++ u8Val = (u8Val >> 4) & 0xF; ++ ++ if (0 == u8Val) { ++ MIU_HAL_ERR("MIU protect size undefined. Using 0x40000000\n"); ++ return 0x40000000; ++ } ++ return (0x1 << (20 + u8Val)); ++} ++ ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ int iRet = 0; ++ ++ if (!clientName) { ++ iRet = -1; ++ MIU_HAL_ERR("Wrong clientName\n"); ++ return iRet; ++ } ++ ++ switch(clientId) ++ { ++ // group 0 ++ case MIU_CLIENT_NONE: ++ strcpy(clientName, "NONE"); ++ break; ++ case MIU_CLIENT_VEN_R: ++ strcpy(clientName, "VEN_R"); ++ break; ++ case MIU_CLIENT_VEN_W: ++ strcpy(clientName, "VEN_W"); ++ break; ++ case MIU_CLIENT_DUMMY_G0C3: ++ strcpy(clientName, "DUMMY_G0C3"); ++ break; ++ case MIU_CLIENT_JPE_W: ++ strcpy(clientName, "JPE_W"); ++ break; ++ case MIU_CLIENT_JPE_R: ++ strcpy(clientName, "JPE_R"); ++ break; ++ case MIU_CLIENT_BACH_RW: ++ strcpy(clientName, "BACH_RW"); ++ break; ++ case MIU_CLIENT_AESDMA_RW: ++ strcpy(clientName, "AESDMA_RW"); ++ break; ++ case MIU_CLIENT_USB20_RW: ++ strcpy(clientName, "USB20_RW"); ++ break; ++ case MIU_CLIENT_EMAC_RW: ++ strcpy(clientName, "EMAC_RW"); ++ break; ++ case MIU_CLIENT_MCU51_RW: ++ strcpy(clientName, "MCU51_RW"); ++ break; ++ case MIU_CLIENT_URDMA_RW: ++ strcpy(clientName, "URDMA_RW"); ++ break; ++ case MIU_CLIENT_BDMA_RW: ++ strcpy(clientName, "BDMA_RW"); ++ break; ++ case MIU_CLIENT_MOVDMA0_RW: ++ strcpy(clientName, "MOVDMA0_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CE: ++ strcpy(clientName, "DUMMY_G0CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CF: ++ strcpy(clientName, "DUMMY_G0CF"); ++ break; ++ // group 1 ++ case MIU_CLIENT_CMDQ0_R: ++ strcpy(clientName, "CMDQ0_R"); ++ break; ++ case MIU_CLIENT_ISP_DMA_W: ++ strcpy(clientName, "ISP_DMA_W"); ++ break; ++ case MIU_CLIENT_ISP_DMA_R: ++ strcpy(clientName, "ISP_DMA_R"); ++ break; ++ case MIU_CLIENT_ISP_ROT_R: ++ strcpy(clientName, "ISP_ROT_R"); ++ break; ++ case MIU_CLIENT_ISP_MLOAD_STA: ++ strcpy(clientName, "ISP_MLOAD_STA"); ++ break; ++ case MIU_CLIENT_GOP: ++ strcpy(clientName, "GOP"); ++ break; ++ case MIU_CLIENT_DUMMY_G1C6: ++ strcpy(clientName, "DUMMY_G1C6"); ++ break; ++ case MIU_CLIENT_DIP0_R: ++ strcpy(clientName, "DIP0_R"); ++ break; ++ case MIU_CLIENT_DIP0_W: ++ strcpy(clientName, "DIP0_W"); ++ break; ++ case MIU_CLIENT_SC0_FRAME_W: ++ strcpy(clientName, "SC0_FRAME_W"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CA: ++ strcpy(clientName, "DUMMY_G1CA"); ++ break; ++ case MIU_CLIENT_SC0_DBG_R: ++ strcpy(clientName, "SC0_DBG_R"); ++ break; ++ case MIU_CLIENT_SC1_FRAME_W: ++ strcpy(clientName, "SC1_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC2_FRAME_W: ++ strcpy(clientName, "SC2_FRAME_W"); ++ break; ++ case MIU_CLIENT_SD30_RW: ++ strcpy(clientName, "SD30_RW"); ++ break; ++ case MIU_CLIENT_SDIO30_RW: ++ strcpy(clientName, "SDIO30_RW"); ++ break; ++ // group 2 ++ case MIU_CLIENT_CMDQ1_R: ++ strcpy(clientName, "CMDQ1_R"); ++ break; ++ case MIU_CLIENT_CMDQ2_R: ++ strcpy(clientName, "CMDQ2_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G2C2: ++ strcpy(clientName, "DUMMY_G2C2"); ++ break; ++ case MIU_CLIENT_ISP_DMAG_RW: ++ strcpy(clientName, "ISP_DMAG_RW"); ++ break; ++ case MIU_CLIENT_GOP1_R: ++ strcpy(clientName, "GOP1_R"); ++ break; ++ case MIU_CLIENT_GOP2_R: ++ strcpy(clientName, "GOP2_R"); ++ break; ++ case MIU_CLIENT_USB20_H_RW: ++ strcpy(clientName, "USB20_H_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G2C7: ++ strcpy(clientName, "DUMMY_G2C7"); ++ break; ++ case MIU_CLIENT_MIIC1_RW: ++ strcpy(clientName, "MIIC1_RW"); ++ break; ++ case MIU_CLIENT_3DNR0_W: ++ strcpy(clientName, "3DNR0_W"); ++ break; ++ case MIU_CLIENT_3DNR0_R: ++ strcpy(clientName, "3DNR0_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CB: ++ strcpy(clientName, "DUMMY_G2CB"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CC: ++ strcpy(clientName, "DUMMY_G2CC"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CD: ++ strcpy(clientName, "DUMMY_G2CD"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CE: ++ strcpy(clientName, "DUMMY_G2CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CF: ++ strcpy(clientName, "DUMMY_G2CF"); ++ break; ++ // DIAMOND ++ case MIU_CLIENT_MIPS_RW: ++ strcpy(clientName, "CPU_RW"); ++ break; ++ default: ++ MIU_HAL_ERR("Wrong clientId %d\n", clientId); ++ iRet = -1; ++ break; ++ } ++ return iRet; ++} ++ ++int clientId_KernelProtectToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++EXPORT_SYMBOL(clientId_KernelProtectToName); ++ ++#ifdef CONFIG_CAM_CLK ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ ++ if (pDramInfo) ++ { ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = CamClkRateGet(CAMCLK_ddrpll_clk) / 1000000; ++ pDramInfo->miupll_freq = CamClkRateGet(CAMCLK_miupll_clk) / 1000000; ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++#else //CONFIG_CAM_CLK ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ unsigned int ddfset = 0; ++ ++ if (pDramInfo) ++ { ++ ddfset = (INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF); ++ ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ pDramInfo->miupll_freq = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++#endif +diff --git a/drivers/sstar/miu/infinity6b0/mdrv_miu.c b/drivers/sstar/miu/infinity6b0/mdrv_miu.c +new file mode 100755 +index 000000000000..823233d56b38 +--- /dev/null ++++ b/drivers/sstar/miu/infinity6b0/mdrv_miu.c +@@ -0,0 +1,375 @@ ++/* ++* mdrv_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "MsTypes.h" ++#include "mdrv_miu.h" ++#include "mhal_miu.h" ++#include "regMIU.h" ++#include ++#include "irqs.h" ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_MSTAR_MONET) || defined(CONFIG_MSTAR_MESSI) || defined(CONFIG_MSTAR_MASERATI) || defined(CONFIG_MSTAR_MANHATTAN) || defined(CONFIG_MSTAR_KANO) ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY phy64Start, MS_PHY phy64End, MS_BOOL bSetFlag) __attribute__((weak)); ++#else ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, MS_U32 u32BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++#endif ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) __attribute__((weak)); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) __attribute__((weak)); ++ ++MS_BOOL HAL_MIU_SlitInit(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SetSlitRange(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY u64BusStart, MS_PHY u64BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++MS_BOOL HAL_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++ ++#ifndef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static struct timer_list monitor_timer; ++#endif ++static int bMiuProtect_is_initialized = 0; ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static int MiuSelId[MIU_MAX_DEVICE] = {0}; ++#endif ++ ++static DEFINE_SPINLOCK(miu_lock); ++MS_U8 u8_MiuWhiteListNum = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Local functions ++//------------------------------------------------------------------------------------------------- ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Init ++/// @brief \b Function \b Description: parse occupied resource to software structure ++/// @param None \b IN : ++/// @param None \b OUT : ++/// @param MS_BOOL \b RET ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Init(void) ++{ ++ MS_BOOL ret = FALSE; ++ ++ /* Parse the used client ID in hardware into software data structure */ ++ if (HAL_MIU_ParseOccupiedResource) { ++ ret = HAL_MIU_ParseOccupiedResource(); ++ } ++ else { ++ ret = FALSE; ++ } ++ ++ /* Initialize MIU slit setting */ ++ if (HAL_MIU_SlitInit) { ++ ret = HAL_MIU_SlitInit(); ++ } ++ ++ u8_MiuWhiteListNum = IDNUM_KERNELPROTECT; ++ ++ return ret; ++} ++ ++MS_BOOL MDrv_MIU_GetProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ return HAL_MIU_GetHitProtectInfo(u8MiuSel, pInfo); ++} ++ ++MS_BOOL MDrv_MIU_Get_IDEnables_Value(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 u8ClientIndex) ++{ ++ return HAL_MIU_GetProtectIdEnVal(u8MiuSel, u8Blockx, u8ClientIndex); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* MDrv_MIU_GetDefaultClientID_KernelProtect(void) ++{ ++ if (HAL_MIU_GetDefaultKernelProtectClientID) { ++ return HAL_MIU_GetDefaultKernelProtectClientID(); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++MS_U16* MDrv_MIU_GetClientID_KernelProtect(MS_U8 u8MiuSel) ++{ ++ if (HAL_MIU_GetKernelProtectClientID) { ++ return HAL_MIU_GetKernelProtectClientID(u8MiuSel); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static irqreturn_t MDrv_MIU_Protect_interrupt(s32 irq, void *dev_id) ++{ ++ MS_U8 u8MiuSel = *(MS_U8 *)dev_id; ++ MIU_PortectInfo pInfo; ++ ++ memset(&pInfo, 0, sizeof(pInfo)); ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &pInfo); ++ ++ if(pInfo.bHit) ++ BUG(); ++ else ++ printk (KERN_EMERG "in miu hit interrupt, but bHit not match\n"); ++ ++ return IRQ_HANDLED; ++} ++#else ++//create timer process ++static void MDev_timer_callback(unsigned long value) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo stProtInfo; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) { ++ stProtInfo.bHit = FALSE; ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &stProtInfo); ++ if (stProtInfo.bHit) { ++ panic("MIU %d Protect hit!\n", u8MiuSel); ++ } ++ } ++ mod_timer(&monitor_timer, jiffies+1*HZ); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 3) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_PHY u64BusStart, ++ MS_PHY u64BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_BOOL Result = FALSE; ++ ++ /* Case of former MIU protect */ ++ if ((u8Blockx >= E_PROTECT_0) && (u8Blockx < E_SLIT_0)) ++ { ++ if (HAL_MIU_Protect) { ++ if (TRUE != (Result = HAL_MIU_Protect(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ /* Case of MIU slits */ ++ else if (u8Blockx == E_SLIT_0) ++ { ++ if (HAL_MIU_SetSlitRange) { ++ if (TRUE != (Result = HAL_MIU_SetSlitRange(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ ++ ++ if(!bMiuProtect_is_initialized) ++ { ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ struct device_node *dev_node = NULL; ++ MS_U8 u8MiuSel = 0; ++ int rc = 0; ++ int iIrqNum = 0; ++ char compat_str[32] = {0}; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ if (u8MiuSel == 0) ++ { ++ snprintf(compat_str, sizeof(compat_str)-1, "sstar,miu"); ++ } ++ else ++ { ++ snprintf(compat_str, sizeof(compat_str)-1, "sstar,miu%d", u8MiuSel); ++ } ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compat_str); ++ if (!dev_node) ++ { ++ printk("[MIU Protecrt] find node Fail\r\n"); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ MiuSelId[u8MiuSel] = u8MiuSel; ++ ++ if(0 != (rc = request_irq(iIrqNum, MDrv_MIU_Protect_interrupt, IRQF_TRIGGER_HIGH, "MIU_Protect", (void *)&MiuSelId[u8MiuSel]))) ++ { ++ printk("[MIU Protecrt] request_irq [%d] Fail, Err:%d\r\n", iIrqNum, rc); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++#else ++ init_timer(&monitor_timer); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++#endif ++ bMiuProtect_is_initialized++; ++ } ++ ++ ++MDrv_MIU_Protect_Exit: ++ return Result; ++} ++ ++unsigned int MDrv_MIU_ProtectDramSize(void) ++{ ++ return HAL_MIU_ProtectDramSize(); ++} ++ ++int MDrv_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++ ++MS_BOOL MDrv_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) ++{ ++ unsigned long flags; ++ MS_BOOL Result = FALSE; ++ ++ spin_lock_irqsave(&miu_lock, flags); ++ ++ if (HAL_MIU_Slits) { ++ Result = HAL_MIU_Slits(u8Blockx, u64SlitsStart, u64SlitsEnd, bSetFlag); ++ } ++ ++ spin_unlock_irqrestore(&miu_lock, flags); ++ ++ return Result; ++} ++ ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo) ++{ ++ return HAL_MIU_Info((MIU_DramInfo_Hal *)pDramInfo); ++} ++ ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(MDrv_MIU_Init); ++EXPORT_SYMBOL(u8_MiuWhiteListNum); ++EXPORT_SYMBOL(MDrv_MIU_GetDefaultClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_GetClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_Protect); ++#endif ++EXPORT_SYMBOL(MDrv_MIU_Get_IDEnables_Value); ++EXPORT_SYMBOL(MDrv_MIU_Info); ++ ++static int mstar_miu_drv_probe(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#if defined (CONFIG_ARM64) ++static struct of_device_id mstarmiu_of_device_ids[] = { ++ {.compatible = "sstar-miu"}, ++ {}, ++}; ++#endif ++ ++static struct platform_driver Sstar_miu_driver = { ++ .probe = mstar_miu_drv_probe, ++ .remove = mstar_miu_drv_remove, ++ .suspend = mstar_miu_drv_suspend, ++ .resume = mstar_miu_drv_resume, ++ .driver = { ++ .name = "Sstar-miu", ++#if defined(CONFIG_ARM64) ++ .of_match_table = mstarmiu_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_miu_drv_init_module(void) ++{ ++ int ret = 0; ++ ++ ret = platform_driver_register(&Sstar_miu_driver); ++ ++ if (ret) { ++ printk("Register MIU Driver Fail"); ++ } ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Sstar_miu_driver); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/miu/infinity6b0/mhal_miu.c b/drivers/sstar/miu/infinity6b0/mhal_miu.c +new file mode 100755 +index 000000000000..6de740a579f0 +--- /dev/null ++++ b/drivers/sstar/miu/infinity6b0/mhal_miu.c +@@ -0,0 +1,1115 @@ ++/* ++* mhal_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#if defined(CONFIG_COMPAT) ++#include ++#endif ++#include "MsTypes.h" ++#include "mdrv_types.h" ++#include "mdrv_miu.h" ++#include "mdrv_system.h" ++#include "regMIU.h" ++#include "mhal_miu.h" ++#include "registers.h" ++#include "ms_platform.h" ++#ifdef CONFIG_CAM_CLK ++#include "camclk.h" ++#include "drv_camclk_Api.h" ++#endif ++//------------------------------------------------------------------------------------------------- ++// Macro Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_VEN_R, \ ++/* 2 */ MIU_CLIENT_VEN_W, \ ++/* 3 */ MIU_CLIENT_DUMMY_G0C3, \ ++/* 4 */ MIU_CLIENT_JPE_R, \ ++/* 5 */ MIU_CLIENT_JPE_W, \ ++/* 6 */ MIU_CLIENT_BACH_RW, \ ++/* 7 */ MIU_CLIENT_AESDMA_RW, \ ++/* 8 */ MIU_CLIENT_USB20_RW, \ ++/* 9 */ MIU_CLIENT_EMAC_RW, \ ++/* A */ MIU_CLIENT_MCU51_RW, \ ++/* B */ MIU_CLIENT_URDMA_RW, \ ++/* C */ MIU_CLIENT_BDMA_RW, \ ++/* D */ MIU_CLIENT_MOVDMA0_RW, \ ++/* E */ MIU_CLIENT_GOP3_R, \ ++/* F */ MIU_CLIENT_DUMMY_G0CF ++ ++#define MIU_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_CMDQ_R, \ ++/* 1 */ MIU_CLIENT_ISP_DMA_W, \ ++/* 2 */ MIU_CLIENT_ISP_DMA_R, \ ++/* 3 */ MIU_CLIENT_ISP_ROT_R, \ ++/* 4 */ MIU_CLIENT_ISP_MLOAD_STA, \ ++/* 5 */ MIU_CLIENT_GOP, \ ++/* 6 */ MIU_CLIENT_DUMMY_G1C6, \ ++/* 7 */ MIU_CLIENT_DIP0_R, \ ++/* 8 */ MIU_CLIENT_DIP0_W, \ ++/* 9 */ MIU_CLIENT_SC0_FRAME_W, \ ++/* A */ MIU_CLIENT_DUMMY_G1CA, \ ++/* B */ MIU_CLIENT_SC0_DBG_R, \ ++/* C */ MIU_CLIENT_SC1_FRAME_W, \ ++/* D */ MIU_CLIENT_SC2_FRAME_W, \ ++/* E */ MIU_CLIENT_SD30_RW, \ ++/* F */ MIU_CLIENT_SDIO30_RW ++ ++#define MIU_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_DUMMY_G2C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G2C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G2C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G2C3, \ ++/* 4 */ MIU_CLIENT_GOP1_R, \ ++/* 5 */ MIU_CLIENT_GOP2_R, \ ++/* 6 */ MIU_CLIENT_USB20_H_RW, \ ++/* 7 */ MIU_CLIENT_IVE_RW, \ ++/* 8 */ MIU_CLIENT_MIIC1_RW, \ ++/* 9 */ MIU_CLIENT_3DNR0_W, \ ++/* A */ MIU_CLIENT_3DNR0_R, \ ++/* B */ MIU_CLIENT_DUMMY_G2CB, \ ++/* C */ MIU_CLIENT_DUMMY_G2CC, \ ++/* D */ MIU_CLIENT_DUMMY_G2CD, \ ++/* E */ MIU_CLIENT_DUMMY_G2CE, \ ++/* F */ MIU_CLIENT_DUMMY_G2CF ++ ++#define MIU_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_DUMMY_G3C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G3C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G3C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G3C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G3C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G3C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G3C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G3C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G3C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G3C9, \ ++/* A */ MIU_CLIENT_DUMMY_G3CA, \ ++/* B */ MIU_CLIENT_DUMMY_G3CB, \ ++/* C */ MIU_CLIENT_DUMMY_G3CC, \ ++/* D */ MIU_CLIENT_DUMMY_G3CD, \ ++/* E */ MIU_CLIENT_DUMMY_G3CE, \ ++/* F */ MIU_CLIENT_DUMMY_G3CF ++ ++#define MIU_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_DUMMY_G4C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G4C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G4C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G4C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G4C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G4C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G4C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G4C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G4C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G4C9, \ ++/* A */ MIU_CLIENT_DUMMY_G4CA, \ ++/* B */ MIU_CLIENT_DUMMY_G4CB, \ ++/* C */ MIU_CLIENT_DUMMY_G4CC, \ ++/* D */ MIU_CLIENT_DUMMY_G4CD, \ ++/* E */ MIU_CLIENT_DUMMY_G4CE, \ ++/* F */ MIU_CLIENT_DUMMY_G4CF ++ ++#define MIU_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_DUMMY_G5C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G5C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G5C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G5C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G5C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G5C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G5C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G5C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G5C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G5C9, \ ++/* A */ MIU_CLIENT_DUMMY_G5CA, \ ++/* B */ MIU_CLIENT_DUMMY_G5CB, \ ++/* C */ MIU_CLIENT_DUMMY_G5CC, \ ++/* D */ MIU_CLIENT_DUMMY_G5CD, \ ++/* E */ MIU_CLIENT_DUMMY_G5CE, \ ++/* F */ MIU_CLIENT_DUMMY_G5CF ++ ++#define MIU_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_DUMMY_G6C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G6C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G6C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G6C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G6C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G6C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G6C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G6C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G6C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G6C9, \ ++/* A */ MIU_CLIENT_DUMMY_G6CA, \ ++/* B */ MIU_CLIENT_DUMMY_G6CB, \ ++/* C */ MIU_CLIENT_DUMMY_G6CC, \ ++/* D */ MIU_CLIENT_DUMMY_G6CD, \ ++/* E */ MIU_CLIENT_DUMMY_G6CE, \ ++/* F */ MIU_CLIENT_DUMMY_G6CF ++ ++#define MIU_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_DUMMY_G7C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G7C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G7C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G7C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G7C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G7C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G7C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G7C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G7C9, \ ++/* A */ MIU_CLIENT_DUMMY_G7CA, \ ++/* B */ MIU_CLIENT_DUMMY_G7CB, \ ++/* C */ MIU_CLIENT_DUMMY_G7CC, \ ++/* D */ MIU_CLIENT_DUMMY_G7CD, \ ++/* E */ MIU_CLIENT_DUMMY_G7CE, \ ++/* F */ MIU_CLIENT_DUMMY_G7CF ++ ++#define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < ARM_MIU1_BASE_ADDR) \ ++ {MiuSel = E_MIU_0; Offset = PhysAddr - ARM_MIU0_BASE_ADDR;} \ ++ else if ((PhysAddr >= ARM_MIU1_BASE_ADDR) && (PhysAddr < ARM_MIU2_BASE_ADDR)) \ ++ {MiuSel = E_MIU_1; Offset = PhysAddr - ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {MiuSel = E_MIU_2; Offset = PhysAddr - ARM_MIU2_BASE_ADDR;} ++ ++#define MIU_HAL_ERR(fmt, args...) printk(KERN_ERR "miu hal error %s:%d" fmt,__FUNCTION__,__LINE__,## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++ ++const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] = ++{ ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ } ++}; ++ ++static MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_MCU51_RW, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SDIO30_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ 0, ++}; ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++static MS_U32 m_u32MiuMapBase = 0xFD200000UL; //default set to arm 32bit platform ++#elif defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++static ptrdiff_t m_u32MiuMapBase; ++#endif ++ ++static MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++static MS_U16 IDList[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}}; //IDList for protection ++ ++//------------------------------------------------------------------------------------------------- ++// MTLB HAL internal function ++//------------------------------------------------------------------------------------------------- ++ ++static MS_U32 HAL_MIU_BA2PA(MS_U32 u32BusAddr) ++{ ++ MS_PHYADDR u32PhyAddr = 0x0UL; ++ ++ // pa = ba - offset ++ if ((u32BusAddr >= ARM_MIU0_BUS_BASE) && (u32BusAddr < ARM_MIU1_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU0_BUS_BASE + ARM_MIU0_BASE_ADDR; ++ else if ((u32BusAddr >= ARM_MIU1_BUS_BASE) && (u32BusAddr < ARM_MIU2_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU1_BUS_BASE + ARM_MIU1_BASE_ADDR; ++ else ++ u32PhyAddr = u32BusAddr - ARM_MIU2_BUS_BASE + ARM_MIU2_BASE_ADDR; ++ ++ return u32PhyAddr; ++} ++ ++static MS_S16 HAL_MIU_GetClientIndex(MS_U8 u8MiuSel, eMIUClientID eClientID) ++{ ++ MS_U8 idx = 0; ++ ++ if (MIU_MAX_DEVICE <= u8MiuSel) { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return (-1); ++ } ++ ++ for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++) { ++ if (eClientID == clientTbl[u8MiuSel][idx]) ++ return idx; ++ } ++ return (-1); ++} ++ ++static MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)]; ++} ++ ++static MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId]; ++} ++ ++static MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegProtectId, MS_U8 u8Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)] = u8Val; ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegProtectId, MS_U16 u16Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg err\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId] = u16Val; ++ ++ return TRUE; ++} ++ ++static void HAL_MIU_WriteByteMask(MS_U32 u32RegOffset, MS_U8 u8Mask, MS_BOOL bEnable) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(u32RegOffset); ++ ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_MIU_WriteByte(u32RegOffset, u8Val); ++} ++ ++static void HAL_MIU_Write2BytesMask(MS_U32 u32RegOffset, MS_U16 u16Mask, MS_BOOL bEnable) ++{ ++ MS_U16 u16Val = HAL_MIU_Read2Byte(u32RegOffset); ++ ++ u16Val = (bEnable) ? (u16Val | u16Mask) : (u16Val & ~u16Mask); ++ HAL_MIU_Write2Byte(u32RegOffset, u16Val); ++} ++ ++static void HAL_MIU_SetProtectIDReg(MS_U32 u32RegBase, MS_U8 u8MiuSel, MS_U16 u16ClientID) ++{ ++ MS_S16 sVal = HAL_MIU_GetClientIndex(u8MiuSel, (eMIUClientID)u16ClientID); ++ MS_S16 sIDVal = 0; ++ ++ if (0 > sVal) { ++ sVal = 0; ++ } ++ ++ sIDVal = HAL_MIU_ReadByte(u32RegBase); ++ sIDVal &= 0x80; ++ sIDVal |= sVal; ++ HAL_MIU_WriteByte(u32RegBase, sIDVal); ++} ++ ++static MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U16 u16ID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U8 u8isfound0, u8isfound1; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u16ID = pu8ProtectId[u32index0]; ++ ++ // Unused ID ++ if (u16ID == 0) ++ continue; ++ ++ u8isfound0 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == u16ID) ++ { ++ // ID reused former setting ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound0 = TRUE; ++ break; ++ } ++ } ++ ++ // Need to create new ID in IDList ++ if (u8isfound0 != TRUE) ++ { ++ u8isfound1 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == 0) ++ { ++ IDList[u8MiuSel][u32index1] = u16ID; ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound1 = TRUE; ++ break; ++ } ++ } ++ ++ // ID overflow ++ if (u8isfound1 == FALSE) { ++ return FALSE; ++ } ++ } ++ } ++ ++ u16IdEnable = 0; ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ if (IDEnables[u8MiuSel][u8Blockx][u32index0] == 1) { ++ u16IdEnable |= (1 << u32index0); ++ } ++ } ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U8 u8isIDNoUse = 0; ++ MS_U16 u16IdEnable = 0; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ u16IdEnable = 0x0UL; ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u8isIDNoUse = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++) ++ { ++ if (IDEnables[u8MiuSel][u32index1][u32index0] == 1) ++ { ++ // Protect ID is still be used ++ u8isIDNoUse = FALSE; ++ break; ++ } ++ u8isIDNoUse = TRUE; ++ } ++ ++ if (u8isIDNoUse == TRUE) { ++ IDList[u8MiuSel][u32index0] = 0; ++ } ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++#define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO) ++#define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID) ++ ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ MS_U16 u16Ret = 0; ++ MS_U16 u16LoAddr = 0; ++ MS_U16 u16HiAddr = 0; ++ MS_U32 u32RegBase = (u8MiuSel) ? MIU1_REG_BASE : MIU_REG_BASE; ++ MS_U32 u32EndAddr = 0; ++ char clientName[40]; ++ if (!pInfo) { ++ return FALSE; ++ } ++ ++ u16Ret = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_STATUS); ++ u16LoAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_LOADDR); ++ u16HiAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_HIADDR); ++ ++ if (REG_MIU_PROTECT_HIT_FALG & u16Ret) ++ { ++ pInfo->bHit = TRUE; ++ pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(u16Ret); ++ pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(u16Ret) >> 4); ++ pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(u16Ret) & 0x0F); ++ pInfo->uAddress = (MS_U32)((u16HiAddr << 16) | u16LoAddr); ++ pInfo->uAddress = pInfo->uAddress * MIU_PROTECT_ADDRESS_UNIT; ++ ++ u32EndAddr = (pInfo->uAddress + MIU_PROTECT_ADDRESS_UNIT - 1); ++ ++ HAL_MIU_ClientIdToName((MS_U8)(GET_HIT_CLIENT(u16Ret)), clientName); ++ ++ if (pInfo->u8Block == 6 || pInfo->u8Block == 7) ++ { ++ printk(KERN_EMERG "MIU%u %s Out of Range Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x (Valid Range: 0x00000000 ~ 0x%08X)\n", ++ u8MiuSel, (pInfo->u8Block == 6)? "Read" : "Write", clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr, HAL_MIU_ProtectDramSize()); ++ } ++ else ++ { ++ printk(KERN_EMERG "MIU%u Block:%u Client:%s ID:%u-%u Hitted_Addr:0x%x<->0x%x\n", ++ u8MiuSel, pInfo->u8Block, clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // FIXME: Workaround for the unknown VEN_R request addr over DRAM size ++ if (MIU_CLIENT_VEN_R == GET_HIT_CLIENT(u16Ret)) ++ { ++ pInfo->bHit = FALSE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuSel, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex) ++{ ++ return IDEnables[u8MiuSel][u8BlockId][u8ProtectIdIndex]; ++} ++ ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&clientId_KernelProtect[0]; ++ } ++ return NULL; ++} ++ ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&IDList[u8MiuSel][0]; ++ } ++ return NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4) ++/// @param *pu8ProtectId \b IN : Allow specified client IDList to write ++/// @param u32Start \b IN : Starting bus address ++/// @param u32End \b IN : End bus address ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegBase = 0; ++ MS_U32 u32RegStartAddr = 0; ++ MS_U32 u32RegStartEnd = 0; ++ MS_U32 u32RegAddrMSB = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ MS_U32 u32RegRWProtectEn = 0; ++ MS_U32 u32StartOffset = 0; ++ MS_U32 u32EndOffset = 0; ++ MS_U8 u8MiuSel = 0; ++ MS_U16 u16Data = 0; ++ MS_U16 u16Data1 = 0; ++ MS_U16 u16Data2 = 0; ++ MS_U8 u8Data = 0; ++ MS_U32 u32Start = 0, u32End = 0; ++ ++ u32Start = HAL_MIU_BA2PA(u32BusStart); ++ u32End = HAL_MIU_BA2PA(u32BusEnd); ++ ++ // Get MIU selection and offset ++ _phy_to_miu_offset(u8MiuSel, u32EndOffset, u32End); ++ _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32Start); ++ ++ u32Start = u32StartOffset; ++ u32End = u32EndOffset; ++ ++ // Parameter check ++ if (u8Blockx >= E_MIU_BLOCK_NUM) ++ { ++ MIU_HAL_ERR("Err: Blk Num out of range\n"); ++ return FALSE; ++ } ++ else if (((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ++ ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0)) ++ { ++ MIU_HAL_ERR("Err: Protected addr not 8KB aligned\n"); ++ return FALSE; ++ } ++ else if (u32Start >= u32End) ++ { ++ MIU_HAL_ERR("Err: Invalid end addr\n"); ++ return FALSE; ++ } ++ ++ ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ u32RegBase = MIU_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT0_EN; ++ u32RegStartAddr = MIU_PROTECT0_START; ++ u32RegStartEnd = MIU_PROTECT0_END; ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU_PROTECT1_EN; ++ u32RegStartAddr = MIU_PROTECT1_START; ++ u32RegStartEnd = MIU_PROTECT1_END; ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU_PROTECT2_EN; ++ u32RegStartAddr = MIU_PROTECT2_START; ++ u32RegStartEnd = MIU_PROTECT2_END; ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU_PROTECT3_EN; ++ u32RegStartAddr = MIU_PROTECT3_START; ++ u32RegStartEnd = MIU_PROTECT3_END; ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT4_EN; ++ u32RegStartAddr = MIU_PROTECT4_START; ++ u32RegStartEnd = MIU_PROTECT4_END; ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ u32RegBase = MIU1_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT0_EN; ++ u32RegStartAddr = MIU1_PROTECT0_START; ++ u32RegStartEnd = MIU1_PROTECT0_END; ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU1_PROTECT1_EN; ++ u32RegStartAddr = MIU1_PROTECT1_START; ++ u32RegStartEnd = MIU1_PROTECT1_END; ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU1_PROTECT2_EN; ++ u32RegStartAddr = MIU1_PROTECT2_START; ++ u32RegStartEnd = MIU1_PROTECT2_END; ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU1_PROTECT3_EN; ++ u32RegStartAddr = MIU1_PROTECT3_START; ++ u32RegStartEnd = MIU1_PROTECT3_END; ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT4_EN; ++ u32RegStartAddr = MIU1_PROTECT4_START; ++ u32RegStartEnd = MIU1_PROTECT4_END; ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ // Disable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, DISABLE); ++ ++ if (bSetFlag) ++ { ++ // Set Protect IDList ++ if (HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn) == FALSE) ++ { ++ return FALSE; ++ } ++ ++ // Set BIT29,30 of start/end address ++ u16Data2 = u16Data2 | (MS_U16)((u32Start >> 29) << ((u8Blockx%4)*4)); // u16Data2 for start_ext addr ++ u16Data1 = u16Data2 | (MS_U16)(((u32End - 1) >> 29) << ((u8Blockx%4)*4+2)); ++ HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1); ++ ++ // Start Address ++ u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); // 8k unit ++ HAL_MIU_Write2Byte(u32RegStartAddr, u16Data); ++ ++ // End Address ++ u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); // 8k unit; ++ HAL_MIU_Write2Byte(u32RegStartEnd, u16Data); ++ ++ // Enable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, ENABLE); ++ } ++ else ++ { ++ // Reset Protect IDList ++ HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // Mask PWR IRQ ++ HAL_MIU_Write2BytesMask(REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET, REG_MIU_PROTECT_PWR_IRQ_MASK_BIT, TRUE); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource ++/// @brief \b Function \b Description: Parse occupied resource to software structure ++/// @return \b 0: Fail 1: OK ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) ++{ ++ MS_U8 u8MiuSel = 0; ++ MS_U8 u8Blockx = 0; ++ MS_U8 u8ClientID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U32 u32index = 0; ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ ++ for (u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ for (u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ { ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel); ++ return FALSE; ++ } ++ ++ u16IdEnable = HAL_MIU_Read2Byte(u32RegProtectIdEn); ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16IdEnable >> u32index) & 0x1UL) ? 1: 0; ++ } ++ } ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ u8ClientID = HAL_MIU_ReadByte(u32RegProtectId + u32index) & 0x7F; ++ IDList[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID]; ++ } ++ } ++ ++ return TRUE; ++} ++ ++unsigned int HAL_MIU_ProtectDramSize(void) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(MIU_PROTECT_DDR_SIZE); ++ ++ u8Val = (u8Val >> 4) & 0xF; ++ ++ if (0 == u8Val) { ++ MIU_HAL_ERR("MIU protect size undefined. Using 0x40000000\n"); ++ return 0x40000000; ++ } ++ return (0x1 << (20 + u8Val)); ++} ++ ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ int iRet = 0; ++ ++ if (!clientName) { ++ iRet = -1; ++ MIU_HAL_ERR("Wrong clientName\n"); ++ return iRet; ++ } ++ ++ switch(clientId) ++ { ++ // group 0 ++ case MIU_CLIENT_NONE: ++ strcpy(clientName, "NONE"); ++ break; ++ case MIU_CLIENT_VEN_R: ++ strcpy(clientName, "VEN_R"); ++ break; ++ case MIU_CLIENT_VEN_W: ++ strcpy(clientName, "VEN_W"); ++ break; ++ case MIU_CLIENT_DUMMY_G0C3: ++ strcpy(clientName, "DUMMY_G0C3"); ++ break; ++ case MIU_CLIENT_JPE_W: ++ strcpy(clientName, "JPE_W"); ++ break; ++ case MIU_CLIENT_JPE_R: ++ strcpy(clientName, "JPE_R"); ++ break; ++ case MIU_CLIENT_BACH_RW: ++ strcpy(clientName, "BACH_RW"); ++ break; ++ case MIU_CLIENT_AESDMA_RW: ++ strcpy(clientName, "AESDMA_RW"); ++ break; ++ case MIU_CLIENT_USB20_RW: ++ strcpy(clientName, "USB20_RW"); ++ break; ++ case MIU_CLIENT_EMAC_RW: ++ strcpy(clientName, "EMAC_RW"); ++ break; ++ case MIU_CLIENT_MCU51_RW: ++ strcpy(clientName, "MCU51_RW"); ++ break; ++ case MIU_CLIENT_URDMA_RW: ++ strcpy(clientName, "URDMA_RW"); ++ break; ++ case MIU_CLIENT_BDMA_RW: ++ strcpy(clientName, "BDMA_RW"); ++ break; ++ case MIU_CLIENT_MOVDMA0_RW: ++ strcpy(clientName, "MOVDMA0_RW"); ++ break; ++ case MIU_CLIENT_GOP3_R: ++ strcpy(clientName, "GOP3_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CF: ++ strcpy(clientName, "DUMMY_G0CF"); ++ break; ++ // group 1 ++ case MIU_CLIENT_CMDQ_R: ++ strcpy(clientName, "CMDQ_R"); ++ break; ++ case MIU_CLIENT_ISP_DMA_W: ++ strcpy(clientName, "ISP_DMA_W"); ++ break; ++ case MIU_CLIENT_ISP_DMA_R: ++ strcpy(clientName, "ISP_DMA_R"); ++ break; ++ case MIU_CLIENT_ISP_ROT_R: ++ strcpy(clientName, "ISP_ROT_R"); ++ break; ++ case MIU_CLIENT_ISP_MLOAD_STA: ++ strcpy(clientName, "ISP_MLOAD_STA"); ++ break; ++ case MIU_CLIENT_GOP: ++ strcpy(clientName, "GOP"); ++ break; ++ case MIU_CLIENT_DUMMY_G1C6: ++ strcpy(clientName, "DUMMY_G1C6"); ++ break; ++ case MIU_CLIENT_DIP0_R: ++ strcpy(clientName, "DIP0_R"); ++ break; ++ case MIU_CLIENT_DIP0_W: ++ strcpy(clientName, "DIP0_W"); ++ break; ++ case MIU_CLIENT_SC0_FRAME_W: ++ strcpy(clientName, "SC0_FRAME_W"); ++ break; ++ case MIU_CLIENT_DUMMY_G1CA: ++ strcpy(clientName, "DUMMY_G1CA"); ++ break; ++ case MIU_CLIENT_SC0_DBG_R: ++ strcpy(clientName, "SC0_DBG_R"); ++ break; ++ case MIU_CLIENT_SC1_FRAME_W: ++ strcpy(clientName, "SC1_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC2_FRAME_W: ++ strcpy(clientName, "SC2_FRAME_W"); ++ break; ++ case MIU_CLIENT_SD30_RW: ++ strcpy(clientName, "SD30_RW"); ++ break; ++ case MIU_CLIENT_SDIO30_RW: ++ strcpy(clientName, "SDIO30_RW"); ++ break; ++ // group 2 ++ case MIU_CLIENT_DUMMY_G2C0: ++ strcpy(clientName, "DUMMY_G2C0"); ++ break; ++ case MIU_CLIENT_DUMMY_G2C1: ++ strcpy(clientName, "DUMMY_G2C1"); ++ break; ++ case MIU_CLIENT_DUMMY_G2C2: ++ strcpy(clientName, "DUMMY_G2C2"); ++ break; ++ case MIU_CLIENT_DUMMY_G2C3: ++ strcpy(clientName, "DUMMY_G2C3"); ++ break; ++ case MIU_CLIENT_GOP1_R: ++ strcpy(clientName, "GOP1_R"); ++ break; ++ case MIU_CLIENT_GOP2_R: ++ strcpy(clientName, "GOP2_R"); ++ break; ++ case MIU_CLIENT_USB20_H_RW: ++ strcpy(clientName, "USB20_H_RW"); ++ break; ++ case MIU_CLIENT_IVE_RW: ++ strcpy(clientName, "IVE_RW"); ++ break; ++ case MIU_CLIENT_MIIC1_RW: ++ strcpy(clientName, "MIIC1_RW"); ++ break; ++ case MIU_CLIENT_3DNR0_W: ++ strcpy(clientName, "3DNR0_W"); ++ break; ++ case MIU_CLIENT_3DNR0_R: ++ strcpy(clientName, "3DNR0_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CB: ++ strcpy(clientName, "DUMMY_G2CB"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CC: ++ strcpy(clientName, "DUMMY_G2CC"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CD: ++ strcpy(clientName, "DUMMY_G2CD"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CE: ++ strcpy(clientName, "DUMMY_G2CE"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CF: ++ strcpy(clientName, "DUMMY_G2CF"); ++ break; ++ // DIAMOND ++ case MIU_CLIENT_MIPS_RW: ++ strcpy(clientName, "CPU_RW"); ++ break; ++ default: ++ MIU_HAL_ERR("Wrong clientId %d\n", clientId); ++ iRet = -1; ++ break; ++ } ++ return iRet; ++} ++ ++int clientId_KernelProtectToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++EXPORT_SYMBOL(clientId_KernelProtectToName); ++ ++#ifdef CONFIG_CAM_CLK ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ ++ if (pDramInfo) ++ { ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = CamClkRateGet(CAMCLK_ddrpll_clk) / 1000000; ++ pDramInfo->miupll_freq = CamClkRateGet(CAMCLK_miupll_clk) / 1000000; ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++#else //CONFIG_CAM_CLK ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ unsigned int ddfset = 0; ++ ++ if (pDramInfo) ++ { ++ ddfset = (INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF); ++ ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ pDramInfo->miupll_freq = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++#endif +diff --git a/drivers/sstar/miu/infinity6e/mdrv_miu.c b/drivers/sstar/miu/infinity6e/mdrv_miu.c +new file mode 100755 +index 000000000000..9d5d07fbe062 +--- /dev/null ++++ b/drivers/sstar/miu/infinity6e/mdrv_miu.c +@@ -0,0 +1,591 @@ ++/* ++* mdrv_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "MsTypes.h" ++#include "mdrv_miu.h" ++#include "mhal_miu.h" ++#include "regMIU.h" ++#include ++#include "irqs.h" ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_MSTAR_MONET) || defined(CONFIG_MSTAR_MESSI) || defined(CONFIG_MSTAR_MASERATI) || defined(CONFIG_MSTAR_MANHATTAN) || defined(CONFIG_MSTAR_KANO) ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY phy64Start, MS_PHY phy64End, MS_BOOL bSetFlag) __attribute__((weak)); ++#else ++MS_BOOL HAL_MIU_Protect(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32BusStart, MS_U32 u32BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++#endif ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) __attribute__((weak)); ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) __attribute__((weak)); ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) __attribute__((weak)); ++ ++MS_BOOL HAL_MIU_SlitInit(void) __attribute__((weak)); ++MS_BOOL HAL_MIU_SetSlitRange(MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_PHY u64BusStart, MS_PHY u64BusEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++MS_BOOL HAL_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) __attribute__((weak)); ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++ ++#ifndef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static struct timer_list monitor_timer; ++#endif ++static int bMiuProtect_is_initialized = 0; ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static int MiuSelId[MIU_MAX_DEVICE] = {0}; ++#endif ++ ++static DEFINE_SPINLOCK(miu_lock); ++MS_U8 u8_MiuWhiteListNum = 0; ++ ++#ifdef CONFIG_PM_SLEEP ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static unsigned int miu_irq = 0; ++#endif ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++static unsigned int mmu_irq = 0; ++#endif ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local functions ++//------------------------------------------------------------------------------------------------- ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Init ++/// @brief \b Function \b Description: parse occupied resource to software structure ++/// @param None \b IN : ++/// @param None \b OUT : ++/// @param MS_BOOL \b RET ++/// @param None \b GLOBAL : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Init(void) ++{ ++ MS_BOOL ret = FALSE; ++ ++ /* Parse the used client ID in hardware into software data structure */ ++ if (HAL_MIU_ParseOccupiedResource) { ++ ret = HAL_MIU_ParseOccupiedResource(); ++ } ++ else { ++ ret = FALSE; ++ } ++ ++ /* Initialize MIU slit setting */ ++ if (HAL_MIU_SlitInit) { ++ ret = HAL_MIU_SlitInit(); ++ } ++ ++ u8_MiuWhiteListNum = IDNUM_KERNELPROTECT; ++ ++ return ret; ++} ++ ++MS_BOOL MDrv_MIU_GetProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ return HAL_MIU_GetHitProtectInfo(u8MiuSel, pInfo); ++} ++ ++MS_BOOL MDrv_MIU_Get_IDEnables_Value(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 u8ClientIndex) ++{ ++ return HAL_MIU_GetProtectIdEnVal(u8MiuSel, u8Blockx, u8ClientIndex); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_GetDefaultClientID_KernelProtect() ++/// @brief \b Function \b Description: Get default client id array pointer for protect kernel ++/// @param \b : The pointer of Array of client IDs ++//////////////////////////////////////////////////////////////////////////////// ++MS_U16* MDrv_MIU_GetDefaultClientID_KernelProtect(void) ++{ ++ if (HAL_MIU_GetDefaultKernelProtectClientID) { ++ return HAL_MIU_GetDefaultKernelProtectClientID(); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++MS_U16* MDrv_MIU_GetClientID_KernelProtect(MS_U8 u8MiuSel) ++{ ++ if (HAL_MIU_GetKernelProtectClientID) { ++ return HAL_MIU_GetKernelProtectClientID(u8MiuSel); ++ } ++ else { ++ return NULL; ++ } ++} ++ ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++static irqreturn_t MDrv_MIU_Protect_interrupt(s32 irq, void *dev_id) ++{ ++ MS_U8 u8MiuSel = *(MS_U8 *)dev_id; ++ MIU_PortectInfo pInfo; ++ ++ memset(&pInfo, 0, sizeof(pInfo)); ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &pInfo); ++ BUG(); ++ return IRQ_HANDLED; ++} ++#else ++//create timer process ++static void MDev_timer_callback(unsigned long value) ++{ ++ MS_U8 u8MiuSel = 0; ++ MIU_PortectInfo stProtInfo; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) { ++ stProtInfo.bHit = FALSE; ++ ++ MDrv_MIU_GetProtectInfo(u8MiuSel, &stProtInfo); ++ if (stProtInfo.bHit) { ++ panic("MIU %d Protect hit!\n", u8MiuSel); ++ } ++ } ++ mod_timer(&monitor_timer, jiffies+1*HZ); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 3) ++/// @param *pu8ProtectId \b IN : Allow specified client IDs to write ++/// @param u32Start \b IN : Starting address(bus address) ++/// @param u32End \b IN : End address(bus address) ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL MDrv_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_PHY u64BusStart, ++ MS_PHY u64BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_BOOL Result = FALSE; ++ ++ /* Case of former MIU protect */ ++ if ((u8Blockx >= E_PROTECT_0) && (u8Blockx < E_SLIT_0)) ++ { ++ if (HAL_MIU_Protect) { ++ if (TRUE != (Result = HAL_MIU_Protect(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ /* Case of MIU slits */ ++ else if (u8Blockx == E_SLIT_0) ++ { ++ if (HAL_MIU_SetSlitRange) { ++ if (TRUE != (Result = HAL_MIU_SetSlitRange(u8Blockx, pu8ProtectId, u64BusStart, u64BusEnd, bSetFlag))) ++ { ++ goto MDrv_MIU_Protect_Exit; ++ } ++ } ++ } ++ ++ if(!bMiuProtect_is_initialized) ++ { ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ struct device_node *dev_node = NULL; ++ MS_U8 u8MiuSel = 0; ++ int rc = 0; ++ int iIrqNum = 0; ++ char compat_str[32] = {0}; ++ ++ for (u8MiuSel = 0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ if (u8MiuSel == 0) ++ { ++ snprintf(compat_str, sizeof(compat_str)-1, "sstar,miu"); ++ } ++ else ++ { ++ snprintf(compat_str, sizeof(compat_str)-1, "sstar,miu%d", u8MiuSel); ++ } ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compat_str); ++ if (!dev_node) ++ { ++ printk("[MIU Protecrt] of_find_compatible_node Fail\r\n"); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ MiuSelId[u8MiuSel] = u8MiuSel; ++ ++ if(0 != (rc = request_irq(iIrqNum, MDrv_MIU_Protect_interrupt, IRQF_TRIGGER_HIGH, "MIU_Protect", (void *)&MiuSelId[u8MiuSel]))) ++ { ++ printk("[MIU Protecrt] request_irq [%d] Fail, ErrCode: %d\r\n", iIrqNum, rc); ++ Result = FALSE; ++ goto MDrv_MIU_Protect_Exit; ++ } ++#ifdef CONFIG_PM_SLEEP ++ miu_irq = iIrqNum; ++#endif ++ } ++#else ++ init_timer(&monitor_timer); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++#endif ++ bMiuProtect_is_initialized++; ++ } ++ ++ ++MDrv_MIU_Protect_Exit: ++ return Result; ++} ++ ++unsigned int MDrv_MIU_ProtectDramSize(void) ++{ ++ return HAL_MIU_ProtectDramSize(); ++} ++ ++int MDrv_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++ ++MS_BOOL MDrv_MIU_Slits(MS_U8 u8Blockx, MS_PHY u64SlitsStart, MS_PHY u64SlitsEnd, MS_BOOL bSetFlag) ++{ ++ unsigned long flags; ++ MS_BOOL Result = FALSE; ++ ++ spin_lock_irqsave(&miu_lock, flags); ++ ++ if (HAL_MIU_Slits) { ++ Result = HAL_MIU_Slits(u8Blockx, u64SlitsStart, u64SlitsEnd, bSetFlag); ++ } ++ ++ spin_unlock_irqrestore(&miu_lock, flags); ++ ++ return Result; ++} ++ ++int MDrv_MIU_Info(MIU_DramInfo *pDramInfo) ++{ ++ return HAL_MIU_Info((MIU_DramInfo_Hal *)pDramInfo); ++} ++ ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(MDrv_MIU_Init); ++EXPORT_SYMBOL(u8_MiuWhiteListNum); ++EXPORT_SYMBOL(MDrv_MIU_GetDefaultClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_GetClientID_KernelProtect); ++EXPORT_SYMBOL(MDrv_MIU_Protect); ++#endif ++EXPORT_SYMBOL(MDrv_MIU_Get_IDEnables_Value); ++EXPORT_SYMBOL(MDrv_MIU_Info); ++#ifdef CONFIG_MIU_HW_MMU ++static DEFINE_SPINLOCK(mmu_lock); ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++static int mmu_isr_init=0; ++MDrv_MMU_Callback MDrv_MMU_Notify=NULL; ++#endif ++ ++int MDrv_MMU_SetPageSize(unsigned char u8PgSz256En) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_SetPageSize(u8PgSz256En); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++int MDrv_MMU_SetRegion(unsigned short u16Region, unsigned short u16ReplaceRegion) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_SetRegion(u16Region,u16ReplaceRegion); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++int MDrv_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_Map(u16PhyAddrEntry, u16VirtAddrEntry); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++unsigned short MDrv_MMU_MapQuery(unsigned short u16PhyAddrEntry) ++{ ++ unsigned long flags; ++ unsigned short entry; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ entry = HAL_MMU_MapQuery(u16PhyAddrEntry); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return entry; ++} ++ ++int MDrv_MMU_UnMap(unsigned short u16PhyAddrEntry) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_UnMap(u16PhyAddrEntry); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++static irqreturn_t MDrv_MMU_interrupt(s32 irq, void *dev_id) ++{ ++ unsigned long flags; ++ unsigned int status; ++ unsigned short u16PhyAddrEntry, u16ClientId; ++ unsigned char u8IsWriteCmd; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ status = HAL_MMU_Status(&u16PhyAddrEntry, &u16ClientId, &u8IsWriteCmd); ++ ++ if (MDrv_MMU_Notify != NULL) ++ { ++ MDrv_MMU_Notify(status, u16PhyAddrEntry, u16ClientId, u8IsWriteCmd); ++ } ++ else ++ { ++ printk("[%s] Status=0x%x, PhyAddrEntry=0x%x, ClientId=0x%x, IsWrite=%d\n", __FUNCTION__, ++ status, ++ u16PhyAddrEntry, ++ u16ClientId, ++ u8IsWriteCmd); ++ } ++ ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++void MDrv_MMU_CallbackFunc(MDrv_MMU_Callback pFuncPtr) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ MDrv_MMU_Notify = pFuncPtr; ++ spin_unlock_irqrestore(&mmu_lock, flags); ++} ++EXPORT_SYMBOL(MDrv_MMU_CallbackFunc); ++#endif ++int MDrv_MMU_Enable(unsigned char u8Enable) ++{ ++ unsigned long flags; ++ int ret; ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++ if (!mmu_isr_init) ++ { ++ struct device_node *dev_node = NULL; ++ int rc = 0; ++ int iIrqNum = 0; ++ dev_node = of_find_compatible_node(NULL, NULL, "sstar,mmu"); ++ if (!dev_node) ++ { ++ printk("[MMU] of_find_compatible_node Fail\r\n"); ++ } ++ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ if(0 != (rc = request_irq(iIrqNum, MDrv_MMU_interrupt, IRQF_TRIGGER_HIGH, "MMU", NULL))) ++ { ++ printk("[MMU] request_irq [%d] Fail, ErrCode: %d\r\n", iIrqNum, rc); ++ } ++#ifdef CONFIG_PM_SLEEP ++ else { ++ mmu_irq = iIrqNum; ++ } ++#endif ++ mmu_isr_init = 1; ++ } ++#endif ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_Enable(u8Enable); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++int MDrv_MMU_Reset(void) ++{ ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ ret = HAL_MMU_Reset(); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return ret; ++} ++ ++#ifndef CONFIG_MMU_INTERRUPT_ENABLE ++unsigned int MDrv_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsWriteCmd) ++{ ++ unsigned long flags; ++ unsigned int status; ++ ++ spin_lock_irqsave(&mmu_lock, flags); ++ status = HAL_MMU_Status(u16PhyAddrEntry, u16ClientId, u8IsWriteCmd); ++ spin_unlock_irqrestore(&mmu_lock, flags); ++ ++ return status; ++} ++#endif ++EXPORT_SYMBOL(MDrv_MMU_SetPageSize); ++EXPORT_SYMBOL(MDrv_MMU_SetRegion); ++EXPORT_SYMBOL(MDrv_MMU_Map); ++EXPORT_SYMBOL(MDrv_MMU_MapQuery); ++EXPORT_SYMBOL(MDrv_MMU_UnMap); ++EXPORT_SYMBOL(MDrv_MMU_Enable); ++EXPORT_SYMBOL(MDrv_MMU_Reset); ++#ifndef CONFIG_MMU_INTERRUPT_ENABLE ++EXPORT_SYMBOL(MDrv_MMU_Status); ++#endif ++#endif ++ ++static int mstar_miu_drv_probe(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int mstar_miu_drv_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mstar_miu_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ if (bMiuProtect_is_initialized) ++ { ++#ifdef CONFIG_MP_CMA_PATCH_DEBUG_STATIC_MIU_PROTECT ++ if (miu_irq) ++ { ++ disable_irq(miu_irq); ++ free_irq(miu_irq, (void *)&MiuSelId[0]); ++ miu_irq = 0; ++ } ++#else ++ del_timer(&monitor_timer); ++#endif ++ bMiuProtect_is_initialized = 0; ++ } ++ ++#ifdef CONFIG_MMU_INTERRUPT_ENABLE ++ if (mmu_isr_init) ++ { ++ if (mmu_irq) ++ { ++ disable_irq(mmu_irq); ++ free_irq(mmu_irq, NULL); ++ mmu_irq = 0; ++ } ++ mmu_isr_init = 0; ++ } ++#endif ++ ++ return 0; ++} ++ ++static int mstar_miu_drv_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++#endif ++ ++static struct of_device_id mstarmiu_of_device_ids[] = { ++ {.compatible = "sstar,miu"}, ++ {}, ++}; ++ ++static struct platform_driver Sstar_miu_driver = { ++ .probe = mstar_miu_drv_probe, ++ .remove = mstar_miu_drv_remove, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = mstar_miu_drv_suspend, ++ .resume = mstar_miu_drv_resume, ++#endif ++ .driver = { ++ .name = "sstar-miu", ++ .of_match_table = mstarmiu_of_device_ids, ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init mstar_miu_drv_init_module(void) ++{ ++ int ret = 0; ++ ++ ret = platform_driver_register(&Sstar_miu_driver); ++ ++ if (ret) { ++ printk("Register Sstar MIU Platform Driver Failed!"); ++ } ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Sstar_miu_driver); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/miu/infinity6e/mhal_miu.c b/drivers/sstar/miu/infinity6e/mhal_miu.c +new file mode 100755 +index 000000000000..8350e3d0885e +--- /dev/null ++++ b/drivers/sstar/miu/infinity6e/mhal_miu.c +@@ -0,0 +1,1321 @@ ++/* ++* mhal_miu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_COMPAT) ++#include ++#endif ++#include "MsTypes.h" ++#include "mdrv_types.h" ++#include "mdrv_miu.h" ++#include "mdrv_system.h" ++#include "regMIU.h" ++#include "mhal_miu.h" ++#include "registers.h" ++#include "ms_platform.h" ++#ifdef CONFIG_CAM_CLK ++#include "camclk.h" ++#include "drv_camclk_Api.h" ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Macro Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MIU_CLIENT_GP0 \ ++/* 0 */ MIU_CLIENT_NONE, \ ++/* 1 */ MIU_CLIENT_VEN_R, \ ++/* 2 */ MIU_CLIENT_VEN_W, \ ++/* 3 */ MIU_CLIENT_USB30_RW, \ ++/* 4 */ MIU_CLIENT_JPE_R, \ ++/* 5 */ MIU_CLIENT_JPE_W, \ ++/* 6 */ MIU_CLIENT_BACH_RW, \ ++/* 7 */ MIU_CLIENT_AESDMA_RW, \ ++/* 8 */ MIU_CLIENT_USB20_RW, \ ++/* 9 */ MIU_CLIENT_EMAC_RW, \ ++/* A */ MIU_CLIENT_MCU51_RW, \ ++/* B */ MIU_CLIENT_URDMA_RW, \ ++/* C */ MIU_CLIENT_BDMA_RW, \ ++/* D */ MIU_CLIENT_MOVDMA0_RW, \ ++/* E */ MIU_CLIENT_LDCFeye_RW, \ ++/* F */ MIU_CLIENT_DUMMY_G0CF ++ ++#define MIU_CLIENT_GP1 \ ++/* 0 */ MIU_CLIENT_CMDQ0_R, \ ++/* 1 */ MIU_CLIENT_ISP_DMA_W, \ ++/* 2 */ MIU_CLIENT_ISP_DMA_R, \ ++/* 3 */ MIU_CLIENT_ISP_ROT_R, \ ++/* 4 */ MIU_CLIENT_ISP_MLOAD_STA, \ ++/* 5 */ MIU_CLIENT_GOP, \ ++/* 6 */ MIU_CLIENT_DUMMY_G1C6, \ ++/* 7 */ MIU_CLIENT_DIP0_R, \ ++/* 8 */ MIU_CLIENT_DIP0_W, \ ++/* 9 */ MIU_CLIENT_SC0_FRAME_W, \ ++/* A */ MIU_CLIENT_SC0_FRAME_R, \ ++/* B */ MIU_CLIENT_SC0_DBG_R, \ ++/* C */ MIU_CLIENT_SC1_FRAME_W, \ ++/* D */ MIU_CLIENT_SC2_FRAME_W, \ ++/* E */ MIU_CLIENT_SD30_RW, \ ++/* F */ MIU_CLIENT_SDIO30_RW ++ ++#define MIU_CLIENT_GP2 \ ++/* 0 */ MIU_CLIENT_DUMMY_G2C0, \ ++/* 1 */ MIU_CLIENT_CSI_TX_R, \ ++/* 2 */ MIU_CLIENT_DUMMY_G2C2, \ ++/* 3 */ MIU_CLIENT_ISP_DMAG_RW, \ ++/* 4 */ MIU_CLIENT_GOP1_R, \ ++/* 5 */ MIU_CLIENT_GOP2_R, \ ++/* 6 */ MIU_CLIENT_USB20_H_RW, \ ++/* 7 */ MIU_CLIENT_MIIC2_RW, \ ++/* 8 */ MIU_CLIENT_MIIC1_RW, \ ++/* 9 */ MIU_CLIENT_3DNR0_W, \ ++/* A */ MIU_CLIENT_3DNR0_R, \ ++/* B */ MIU_CLIENT_DLA_RW, \ ++/* C */ MIU_CLIENT_DUMMY_G2CC, \ ++/* D */ MIU_CLIENT_DUMMY_G2CD, \ ++/* E */ MIU_CLIENT_MIIC0_RW, \ ++/* F */ MIU_CLIENT_IVE_RW ++ ++#define MIU_CLIENT_GP3 \ ++/* 0 */ MIU_CLIENT_DIAMOND_RW, \ ++/* 1 */ MIU_CLIENT_DUMMY_G3C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G3C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G3C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G3C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G3C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G3C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G3C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G3C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G3C9, \ ++/* A */ MIU_CLIENT_DUMMY_G3CA, \ ++/* B */ MIU_CLIENT_DUMMY_G3CB, \ ++/* C */ MIU_CLIENT_DUMMY_G3CC, \ ++/* D */ MIU_CLIENT_DUMMY_G3CD, \ ++/* E */ MIU_CLIENT_DUMMY_G3CE, \ ++/* F */ MIU_CLIENT_DUMMY_G3CF ++ ++#define MIU_CLIENT_GP4 \ ++/* 0 */ MIU_CLIENT_DUMMY_G4C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G4C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G4C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G4C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G4C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G4C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G4C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G4C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G4C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G4C9, \ ++/* A */ MIU_CLIENT_DUMMY_G4CA, \ ++/* B */ MIU_CLIENT_DUMMY_G4CB, \ ++/* C */ MIU_CLIENT_DUMMY_G4CC, \ ++/* D */ MIU_CLIENT_DUMMY_G4CD, \ ++/* E */ MIU_CLIENT_DUMMY_G4CE, \ ++/* F */ MIU_CLIENT_DUMMY_G4CF ++ ++#define MIU_CLIENT_GP5 \ ++/* 0 */ MIU_CLIENT_DUMMY_G5C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G5C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G5C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G5C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G5C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G5C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G5C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G5C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G5C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G5C9, \ ++/* A */ MIU_CLIENT_DUMMY_G5CA, \ ++/* B */ MIU_CLIENT_DUMMY_G5CB, \ ++/* C */ MIU_CLIENT_DUMMY_G5CC, \ ++/* D */ MIU_CLIENT_DUMMY_G5CD, \ ++/* E */ MIU_CLIENT_DUMMY_G5CE, \ ++/* F */ MIU_CLIENT_DUMMY_G5CF ++ ++#define MIU_CLIENT_GP6 \ ++/* 0 */ MIU_CLIENT_DUMMY_G6C0, \ ++/* 1 */ MIU_CLIENT_DUMMY_G6C1, \ ++/* 2 */ MIU_CLIENT_DUMMY_G6C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G6C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G6C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G6C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G6C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G6C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G6C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G6C9, \ ++/* A */ MIU_CLIENT_DUMMY_G6CA, \ ++/* B */ MIU_CLIENT_DUMMY_G6CB, \ ++/* C */ MIU_CLIENT_DUMMY_G6CC, \ ++/* D */ MIU_CLIENT_DUMMY_G6CD, \ ++/* E */ MIU_CLIENT_DUMMY_G6CE, \ ++/* F */ MIU_CLIENT_DUMMY_G6CF ++ ++#define MIU_CLIENT_GP7 \ ++/* 0 */ MIU_CLIENT_MIPS_RW, \ ++/* 1 */ MIU_CLIENT_DLA_HIWAY, \ ++/* 2 */ MIU_CLIENT_DUMMY_G7C2, \ ++/* 3 */ MIU_CLIENT_DUMMY_G7C3, \ ++/* 4 */ MIU_CLIENT_DUMMY_G7C4, \ ++/* 5 */ MIU_CLIENT_DUMMY_G7C5, \ ++/* 6 */ MIU_CLIENT_DUMMY_G7C6, \ ++/* 7 */ MIU_CLIENT_DUMMY_G7C7, \ ++/* 8 */ MIU_CLIENT_DUMMY_G7C8, \ ++/* 9 */ MIU_CLIENT_DUMMY_G7C9, \ ++/* A */ MIU_CLIENT_DUMMY_G7CA, \ ++/* B */ MIU_CLIENT_DUMMY_G7CB, \ ++/* C */ MIU_CLIENT_DUMMY_G7CC, \ ++/* D */ MIU_CLIENT_DUMMY_G7CD, \ ++/* E */ MIU_CLIENT_DUMMY_G7CE, \ ++/* F */ MIU_CLIENT_DUMMY_G7CF ++ ++#define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < ARM_MIU1_BASE_ADDR) \ ++ {MiuSel = E_MIU_0; Offset = PhysAddr - ARM_MIU0_BASE_ADDR;} \ ++ else if ((PhysAddr >= ARM_MIU1_BASE_ADDR) && (PhysAddr < ARM_MIU2_BASE_ADDR)) \ ++ {MiuSel = E_MIU_1; Offset = PhysAddr - ARM_MIU1_BASE_ADDR;} \ ++ else \ ++ {MiuSel = E_MIU_2; Offset = PhysAddr - ARM_MIU2_BASE_ADDR;} ++ ++#define MIU_HAL_ERR(fmt, args...) printk(KERN_ERR "miu hal error %s:%d" fmt,__FUNCTION__,__LINE__,## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++ ++const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] = ++{ ++ { ++ MIU_CLIENT_GP0, ++ MIU_CLIENT_GP1, ++ MIU_CLIENT_GP2, ++ MIU_CLIENT_GP3, ++ MIU_CLIENT_GP4, ++ MIU_CLIENT_GP5, ++ MIU_CLIENT_GP6, ++ MIU_CLIENT_GP7 ++ } ++}; ++ ++static MS_U16 clientId_KernelProtect[IDNUM_KERNELPROTECT] = ++{ ++ MIU_CLIENT_MIPS_RW, ++ MIU_CLIENT_USB20_H_RW, ++ MIU_CLIENT_USB20_RW, ++ MIU_CLIENT_USB30_RW, ++ MIU_CLIENT_MIIC2_RW, ++ MIU_CLIENT_MIIC1_RW, ++ MIU_CLIENT_MIIC0_RW, ++ MIU_CLIENT_EMAC_RW, ++ MIU_CLIENT_SD30_RW, ++ MIU_CLIENT_SDIO30_RW, ++ MIU_CLIENT_AESDMA_RW, ++ MIU_CLIENT_URDMA_RW, ++ MIU_CLIENT_BDMA_RW, ++ MIU_CLIENT_MOVDMA0_RW, ++ 0, ++}; ++ ++#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) ++static MS_U32 m_u32MiuMapBase = 0xFD200000UL; //default set to arm 32bit platform ++#elif defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++static ptrdiff_t m_u32MiuMapBase; ++#endif ++ ++static MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}}; //ID enable for protect block 0~3 ++static MS_U16 IDList[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}}; //IDList for protection ++ ++//------------------------------------------------------------------------------------------------- ++// MTLB HAL internal function ++//------------------------------------------------------------------------------------------------- ++ ++static MS_U32 HAL_MIU_BA2PA(MS_U32 u32BusAddr) ++{ ++ MS_PHYADDR u32PhyAddr = 0x0UL; ++ ++ // pa = ba - offset ++ if ((u32BusAddr >= ARM_MIU0_BUS_BASE) && (u32BusAddr < ARM_MIU1_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU0_BUS_BASE + ARM_MIU0_BASE_ADDR; ++ else if ((u32BusAddr >= ARM_MIU1_BUS_BASE) && (u32BusAddr < ARM_MIU2_BUS_BASE)) ++ u32PhyAddr = u32BusAddr - ARM_MIU1_BUS_BASE + ARM_MIU1_BASE_ADDR; ++ else ++ u32PhyAddr = u32BusAddr - ARM_MIU2_BUS_BASE + ARM_MIU2_BASE_ADDR; ++ ++ return u32PhyAddr; ++} ++ ++static MS_S16 HAL_MIU_GetClientIndex(MS_U8 u8MiuSel, eMIUClientID eClientID) ++{ ++ MS_U8 idx = 0; ++ ++ if (MIU_MAX_DEVICE <= u8MiuSel) { ++ MIU_HAL_ERR("Wrong MIU device:%u\n", u8MiuSel); ++ return (-1); ++ } ++ ++ for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++) { ++ if (eClientID == clientTbl[u8MiuSel][idx]) ++ return idx; ++ } ++ return (-1); ++} ++ ++static MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)]; ++} ++ ++static MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegProtectId) ++{ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ return ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId]; ++} ++ ++static MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegProtectId, MS_U8 u8Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U8*)(m_u32MiuMapBase))[(u32RegProtectId << 1) - (u32RegProtectId & 1)] = u8Val; ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegProtectId, MS_U16 u16Val) ++{ ++ if (!u32RegProtectId) { ++ MIU_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++#if defined(CONFIG_ARM64) ++ m_u32MiuMapBase = (mstar_pm_base + 0x00200000UL); ++#endif ++ ((volatile MS_U16*)(m_u32MiuMapBase))[u32RegProtectId] = u16Val; ++ ++ return TRUE; ++} ++ ++static void HAL_MIU_WriteByteMask(MS_U32 u32RegOffset, MS_U8 u8Mask, MS_BOOL bEnable) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(u32RegOffset); ++ ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_MIU_WriteByte(u32RegOffset, u8Val); ++} ++ ++static void HAL_MIU_Write2BytesMask(MS_U32 u32RegOffset, MS_U16 u16Mask, MS_BOOL bEnable) ++{ ++ MS_U16 u16Val = HAL_MIU_Read2Byte(u32RegOffset); ++ ++ u16Val = (bEnable) ? (u16Val | u16Mask) : (u16Val & ~u16Mask); ++ HAL_MIU_Write2Byte(u32RegOffset, u16Val); ++} ++ ++static void HAL_MIU_SetProtectIDReg(MS_U32 u32RegBase, MS_U8 u8MiuSel, MS_U16 u16ClientID) ++{ ++ MS_S16 sVal = HAL_MIU_GetClientIndex(u8MiuSel, (eMIUClientID)u16ClientID); ++ MS_S16 sIDVal = 0; ++ ++ if (0 > sVal) { ++ sVal = 0; ++ } ++ ++ sIDVal = HAL_MIU_ReadByte(u32RegBase); ++ sIDVal &= 0x80; ++ sIDVal |= sVal; ++ HAL_MIU_WriteByte(u32RegBase, sIDVal); ++} ++ ++static MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U16 u16ID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U8 u8isfound0, u8isfound1; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u16ID = pu8ProtectId[u32index0]; ++ ++ // Unused ID ++ if (u16ID == 0) ++ continue; ++ ++ u8isfound0 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == u16ID) ++ { ++ // ID reused former setting ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound0 = TRUE; ++ break; ++ } ++ } ++ ++ // Need to create new ID in IDList ++ if (u8isfound0 != TRUE) ++ { ++ u8isfound1 = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++) ++ { ++ if (IDList[u8MiuSel][u32index1] == 0) ++ { ++ IDList[u8MiuSel][u32index1] = u16ID; ++ IDEnables[u8MiuSel][u8Blockx][u32index1] = 1; ++ u8isfound1 = TRUE; ++ break; ++ } ++ } ++ ++ // ID overflow ++ if (u8isfound1 == FALSE) { ++ return FALSE; ++ } ++ } ++ } ++ ++ u16IdEnable = 0; ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ if (IDEnables[u8MiuSel][u8Blockx][u32index0] == 1) { ++ u16IdEnable |= (1 << u32index0); ++ } ++ } ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++static MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U16 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegProtectIdEn) ++{ ++ MS_U32 u32index0, u32index1; ++ MS_U8 u8isIDNoUse = 0; ++ MS_U16 u16IdEnable = 0; ++ ++ // Reset IDEnables for protect u8Blockx ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index0] = 0; ++ } ++ ++ u16IdEnable = 0x0UL; ++ ++ HAL_MIU_Write2Byte(u32RegProtectIdEn, u16IdEnable); ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ u8isIDNoUse = FALSE; ++ ++ for (u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++) ++ { ++ if (IDEnables[u8MiuSel][u32index1][u32index0] == 1) ++ { ++ // Protect ID is still be used ++ u8isIDNoUse = FALSE; ++ break; ++ } ++ u8isIDNoUse = TRUE; ++ } ++ ++ if (u8isIDNoUse == TRUE) { ++ IDList[u8MiuSel][u32index0] = 0; ++ } ++ } ++ ++ for (u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++) ++ { ++ HAL_MIU_SetProtectIDReg(u32RegAddrID + u32index0, u8MiuSel, IDList[u8MiuSel][u32index0]); ++ } ++ ++ return TRUE; ++} ++ ++#define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO) ++#define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID) ++ ++MS_BOOL HAL_MIU_GetHitProtectInfo(MS_U8 u8MiuSel, MIU_PortectInfo *pInfo) ++{ ++ MS_U16 u16Ret = 0; ++ MS_U16 u16LoAddr = 0; ++ MS_U16 u16HiAddr = 0; ++ MS_U32 u32RegBase = (u8MiuSel) ? MIU1_REG_BASE : MIU_REG_BASE; ++ MS_U32 u32EndAddr = 0; ++ char clientName[40]; ++ if (!pInfo) { ++ return FALSE; ++ } ++ ++ u16Ret = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_STATUS); ++ u16LoAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_LOADDR); ++ u16HiAddr = HAL_MIU_Read2Byte(u32RegBase + REG_MIU_PROTECT_HIADDR); ++ ++ if (REG_MIU_PROTECT_HIT_FALG & u16Ret) ++ { ++ pInfo->bHit = TRUE; ++ pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(u16Ret); ++ pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(u16Ret) >> 4); ++ pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(u16Ret) & 0x0F); ++ pInfo->uAddress = (MS_U32)((u16HiAddr << 16) | u16LoAddr); ++ pInfo->uAddress = pInfo->uAddress * MIU_PROTECT_ADDRESS_UNIT; ++ ++ u32EndAddr = (pInfo->uAddress + MIU_PROTECT_ADDRESS_UNIT - 1); ++ ++ HAL_MIU_ClientIdToName((MS_U8)(GET_HIT_CLIENT(u16Ret)), clientName); ++ printk(KERN_EMERG "MIU%u Block:%u Client:%s ID:%u-%u Hitted_Address(MIU):0x%x<->0x%x\n", ++ u8MiuSel, pInfo->u8Block, clientName, ++ pInfo->u8Group, pInfo->u8ClientID, ++ pInfo->uAddress, u32EndAddr); ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_MIU_GetProtectIdEnVal(MS_U8 u8MiuSel, MS_U8 u8BlockId, MS_U8 u8ProtectIdIndex) ++{ ++ return IDEnables[u8MiuSel][u8BlockId][u8ProtectIdIndex]; ++} ++ ++MS_U16* HAL_MIU_GetDefaultKernelProtectClientID(void) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&clientId_KernelProtect[0]; ++ } ++ return NULL; ++} ++ ++MS_U16* HAL_MIU_GetKernelProtectClientID(MS_U8 u8MiuSel) ++{ ++ if (IDNUM_KERNELPROTECT > 0) { ++ return (MS_U16 *)&IDList[u8MiuSel][0]; ++ } ++ return NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_Protect() ++/// @brief \b Function \b Description: Enable/Disable MIU Protection mode ++/// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4) ++/// @param *pu8ProtectId \b IN : Allow specified client IDList to write ++/// @param u32Start \b IN : Starting bus address ++/// @param u32End \b IN : End bus address ++/// @param bSetFlag \b IN : Disable or Enable MIU protection ++/// - -Disable(0) ++/// - -Enable(1) ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_Protect( MS_U8 u8Blockx, ++ MS_U16 *pu8ProtectId, ++ MS_U32 u32BusStart, ++ MS_U32 u32BusEnd, ++ MS_BOOL bSetFlag) ++{ ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegBase = 0; ++ MS_U32 u32RegStartAddr = 0; ++ MS_U32 u32RegStartEnd = 0; ++ MS_U32 u32RegAddrMSB = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ MS_U32 u32RegRWProtectEn = 0; ++ MS_U32 u32StartOffset = 0; ++ MS_U32 u32EndOffset = 0; ++ MS_U8 u8MiuSel = 0; ++ MS_U16 u16Data = 0; ++ MS_U16 u16Data1 = 0; ++ MS_U16 u16Data2 = 0; ++ MS_U8 u8Data = 0; ++ MS_U32 u32Start = 0, u32End = 0; ++ ++ u32Start = HAL_MIU_BA2PA(u32BusStart); ++ u32End = HAL_MIU_BA2PA(u32BusEnd); ++ ++ // Get MIU selection and offset ++ _phy_to_miu_offset(u8MiuSel, u32EndOffset, u32End); ++ _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32Start); ++ ++ u32Start = u32StartOffset; ++ u32End = u32EndOffset; ++ ++ // Parameter check ++ if (u8Blockx >= E_MIU_BLOCK_NUM) ++ { ++ MIU_HAL_ERR("Err: Out of the number of protect device\n"); ++ return FALSE; ++ } ++ else if (((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ++ ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0)) ++ { ++ MIU_HAL_ERR("Err: Protected address should be aligned to 8KB\n"); ++ return FALSE; ++ } ++ else if (u32Start >= u32End) ++ { ++ MIU_HAL_ERR("Err: Start address is equal to or more than end address\n"); ++ return FALSE; ++ } ++ ++ ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ u32RegBase = MIU_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT0_EN; ++ u32RegStartAddr = MIU_PROTECT0_START; ++ u32RegStartEnd = MIU_PROTECT0_END; ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU_PROTECT1_EN; ++ u32RegStartAddr = MIU_PROTECT1_START; ++ u32RegStartEnd = MIU_PROTECT1_END; ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU_PROTECT2_EN; ++ u32RegStartAddr = MIU_PROTECT2_START; ++ u32RegStartEnd = MIU_PROTECT2_END; ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU_PROTECT3_EN; ++ u32RegStartAddr = MIU_PROTECT3_START; ++ u32RegStartEnd = MIU_PROTECT3_END; ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU_PROTECT4_EN; ++ u32RegStartAddr = MIU_PROTECT4_START; ++ u32RegStartEnd = MIU_PROTECT4_END; ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ u32RegBase = MIU1_REG_BASE; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT0_EN; ++ u32RegStartAddr = MIU1_PROTECT0_START; ++ u32RegStartEnd = MIU1_PROTECT0_END; ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT0_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ case E_MIU_BLOCK_1: ++ u8Data = 1 << 1; ++ u32RegRWProtectEn = MIU1_PROTECT1_EN; ++ u32RegStartAddr = MIU1_PROTECT1_START; ++ u32RegStartEnd = MIU1_PROTECT1_END; ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT1_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFF0FUL); ++ break; ++ case E_MIU_BLOCK_2: ++ u8Data = 1 << 2; ++ u32RegRWProtectEn = MIU1_PROTECT2_EN; ++ u32RegStartAddr = MIU1_PROTECT2_START; ++ u32RegStartEnd = MIU1_PROTECT2_END; ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT2_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xF0FFUL); ++ break; ++ case E_MIU_BLOCK_3: ++ u8Data = 1 << 3; ++ u32RegRWProtectEn = MIU1_PROTECT3_EN; ++ u32RegStartAddr = MIU1_PROTECT3_START; ++ u32RegStartEnd = MIU1_PROTECT3_END; ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT3_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0x0FFFUL); ++ break; ++ case E_MIU_BLOCK_4: ++ u8Data = 1 << 0; ++ u32RegRWProtectEn = MIU1_PROTECT4_EN; ++ u32RegStartAddr = MIU1_PROTECT4_START; ++ u32RegStartEnd = MIU1_PROTECT4_END; ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ u32RegAddrMSB = MIU1_PROTECT4_MSB; ++ u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB); ++ u16Data2 = (u16Data1 & 0xFFF0UL); ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel ); ++ return FALSE; ++ } ++ ++ // Disable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, DISABLE); ++ ++ if (bSetFlag) ++ { ++ // Set Protect IDList ++ if (HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn) == FALSE) ++ { ++ return FALSE; ++ } ++ ++ // Set BIT29,30 of start/end address ++ u16Data2 = u16Data2 | (MS_U16)((u32Start >> 29) << ((u8Blockx%4)*4)); // u16Data2 for start_ext addr ++ u16Data1 = u16Data2 | (MS_U16)(((u32End - 1) >> 29) << ((u8Blockx%4)*4+2)); ++ HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1); ++ ++ // Start Address ++ u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); // 8k unit ++ HAL_MIU_Write2Byte(u32RegStartAddr, u16Data); ++ ++ // End Address ++ u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); // 8k unit; ++ HAL_MIU_Write2Byte(u32RegStartEnd, u16Data); ++ ++ // Enable MIU write protect ++ HAL_MIU_WriteByteMask(u32RegRWProtectEn, u8Data, ENABLE); ++ } ++ else ++ { ++ // Reset Protect IDList ++ HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegProtectId, u32RegProtectIdEn); ++ } ++ ++ // Clear log ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, TRUE); ++ HAL_MIU_Write2BytesMask(u32RegBase + REG_MIU_PROTECT_STATUS, REG_MIU_PROTECT_LOG_CLR, FALSE); ++ ++ // Mask PWR IRQ ++ HAL_MIU_Write2BytesMask(REG_MIU_PROTECT_PWR_IRQ_MASK_OFFSET, REG_MIU_PROTECT_PWR_IRQ_MASK_BIT, TRUE); ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource ++/// @brief \b Function \b Description: Parse occupied resource to software structure ++/// @return \b 0: Fail 1: OK ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_MIU_ParseOccupiedResource(void) ++{ ++ MS_U8 u8MiuSel = 0; ++ MS_U8 u8Blockx = 0; ++ MS_U8 u8ClientID = 0; ++ MS_U16 u16IdEnable = 0; ++ MS_U32 u32index = 0; ++ MS_U32 u32RegProtectId = 0; ++ MS_U32 u32RegProtectIdEn = 0; ++ ++ for (u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++) ++ { ++ for (u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++) ++ { ++ if (u8MiuSel == E_MIU_0) ++ { ++ u32RegProtectId = MIU_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else if (u8MiuSel == E_MIU_1) ++ { ++ u32RegProtectId = MIU1_PROTECT_ID0; ++ ++ switch (u8Blockx) ++ { ++ case E_MIU_BLOCK_0: ++ u32RegProtectIdEn = MIU1_PROTECT0_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_1: ++ u32RegProtectIdEn = MIU1_PROTECT1_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_2: ++ u32RegProtectIdEn = MIU1_PROTECT2_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_3: ++ u32RegProtectIdEn = MIU1_PROTECT3_ID_ENABLE; ++ break; ++ case E_MIU_BLOCK_4: ++ u32RegProtectIdEn = MIU1_PROTECT4_ID_ENABLE; ++ break; ++ default: ++ return FALSE; ++ } ++ } ++ else ++ { ++ MIU_HAL_ERR("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel); ++ return FALSE; ++ } ++ ++ u16IdEnable = HAL_MIU_Read2Byte(u32RegProtectIdEn); ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16IdEnable >> u32index) & 0x1UL) ? 1: 0; ++ } ++ } ++ ++ for (u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++) ++ { ++ u8ClientID = HAL_MIU_ReadByte(u32RegProtectId + u32index) & 0x7F; ++ IDList[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID]; ++ } ++ } ++ ++ return TRUE; ++} ++ ++unsigned int HAL_MIU_ProtectDramSize(void) ++{ ++ MS_U8 u8Val = HAL_MIU_ReadByte(MIU_PROTECT_DDR_SIZE); ++ ++ u8Val = (u8Val >> 4) & 0xF; ++ ++ if (0 == u8Val) { ++ MIU_HAL_ERR("MIU protect DRAM size is undefined. Using 0x40000000 as default\n"); ++ return 0x40000000; ++ } ++ return (0x1 << (20 + u8Val)); ++} ++ ++int HAL_MIU_ClientIdToName(MS_U16 clientId, char *clientName) ++{ ++ int iRet = 0; ++ ++ if (!clientName) { ++ iRet = -1; ++ MIU_HAL_ERR("do nothing, input wrong clientName\n"); ++ return iRet; ++ } ++ ++ switch(clientId) ++ { ++ // group 0 ++ case MIU_CLIENT_NONE: ++ strcpy(clientName, "NONE"); ++ break; ++ case MIU_CLIENT_VEN_R: ++ strcpy(clientName, "VEN_R"); ++ break; ++ case MIU_CLIENT_VEN_W: ++ strcpy(clientName, "VEN_W"); ++ break; ++ case MIU_CLIENT_USB30_RW: ++ strcpy(clientName, "USB30_RW"); ++ break; ++ case MIU_CLIENT_JPE_W: ++ strcpy(clientName, "JPE_W"); ++ break; ++ case MIU_CLIENT_JPE_R: ++ strcpy(clientName, "JPE_R"); ++ break; ++ case MIU_CLIENT_BACH_RW: ++ strcpy(clientName, "BACH_RW"); ++ break; ++ case MIU_CLIENT_AESDMA_RW: ++ strcpy(clientName, "AESDMA_RW"); ++ break; ++ case MIU_CLIENT_USB20_RW: ++ strcpy(clientName, "USB20_RW"); ++ break; ++ case MIU_CLIENT_EMAC_RW: ++ strcpy(clientName, "EMAC_RW"); ++ break; ++ case MIU_CLIENT_MCU51_RW: ++ strcpy(clientName, "MCU51_RW"); ++ break; ++ case MIU_CLIENT_URDMA_RW: ++ strcpy(clientName, "URDMA_RW"); ++ break; ++ case MIU_CLIENT_BDMA_RW: ++ strcpy(clientName, "BDMA_RW"); ++ break; ++ case MIU_CLIENT_MOVDMA0_RW: ++ strcpy(clientName, "MOVDMA0_RW"); ++ break; ++ case MIU_CLIENT_LDCFeye_RW: ++ strcpy(clientName, "LDCFeye_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G0CF: ++ strcpy(clientName, "DUMMY_G0CF"); ++ break; ++ // group 1 ++ case MIU_CLIENT_CMDQ0_R: ++ strcpy(clientName, "CMDQ0_R"); ++ break; ++ case MIU_CLIENT_ISP_DMA_W: ++ strcpy(clientName, "ISP_DMA_W"); ++ break; ++ case MIU_CLIENT_ISP_DMA_R: ++ strcpy(clientName, "ISP_DMA_R"); ++ break; ++ case MIU_CLIENT_ISP_ROT_R: ++ strcpy(clientName, "ISP_ROT_R"); ++ break; ++ case MIU_CLIENT_ISP_MLOAD_STA: ++ strcpy(clientName, "ISP_MLOAD_STA"); ++ break; ++ case MIU_CLIENT_GOP: ++ strcpy(clientName, "GOP"); ++ break; ++ case MIU_CLIENT_DUMMY_G1C6: ++ strcpy(clientName, "DUMMY_G1C6"); ++ break; ++ case MIU_CLIENT_DIP0_R: ++ strcpy(clientName, "DIP0_R"); ++ break; ++ case MIU_CLIENT_DIP0_W: ++ strcpy(clientName, "DIP0_W"); ++ break; ++ case MIU_CLIENT_SC0_FRAME_W: ++ strcpy(clientName, "SC0_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC0_FRAME_R: ++ strcpy(clientName, "SC0_FRAME_R"); ++ break; ++ case MIU_CLIENT_SC0_DBG_R: ++ strcpy(clientName, "SC0_DBG_R"); ++ break; ++ case MIU_CLIENT_SC1_FRAME_W: ++ strcpy(clientName, "SC1_FRAME_W"); ++ break; ++ case MIU_CLIENT_SC2_FRAME_W: ++ strcpy(clientName, "SC2_FRAME_W"); ++ break; ++ case MIU_CLIENT_SD30_RW: ++ strcpy(clientName, "SD30_RW"); ++ break; ++ case MIU_CLIENT_SDIO30_RW: ++ strcpy(clientName, "SDIO30_RW"); ++ break; ++ // group 2 ++ case MIU_CLIENT_DUMMY_G2C0: ++ strcpy(clientName, "DUMMY_G2C0"); ++ break; ++ case MIU_CLIENT_CSI_TX_R: ++ strcpy(clientName, "CSI_TX_R"); ++ break; ++ case MIU_CLIENT_DUMMY_G2C2: ++ strcpy(clientName, "DUMMY_G2C2"); ++ break; ++ case MIU_CLIENT_ISP_DMAG_RW: ++ strcpy(clientName, "ISP_DMAG_RW"); ++ break; ++ case MIU_CLIENT_GOP1_R: ++ strcpy(clientName, "GOP1_R"); ++ break; ++ case MIU_CLIENT_GOP2_R: ++ strcpy(clientName, "GOP2_R"); ++ break; ++ case MIU_CLIENT_USB20_H_RW: ++ strcpy(clientName, "USB20_H_RW"); ++ break; ++ case MIU_CLIENT_MIIC2_RW: ++ strcpy(clientName, "MIIC2_RW"); ++ break; ++ case MIU_CLIENT_MIIC1_RW: ++ strcpy(clientName, "MIIC1_RW"); ++ break; ++ case MIU_CLIENT_3DNR0_W: ++ strcpy(clientName, "3DNR0_W"); ++ break; ++ case MIU_CLIENT_3DNR0_R: ++ strcpy(clientName, "3DNR0_R"); ++ break; ++ case MIU_CLIENT_DLA_RW: ++ strcpy(clientName, "DLA_RW"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CC: ++ strcpy(clientName, "DUMMY_G2CC"); ++ break; ++ case MIU_CLIENT_DUMMY_G2CD: ++ strcpy(clientName, "DUMMY_G2CD"); ++ break; ++ case MIU_CLIENT_MIIC0_RW: ++ strcpy(clientName, "MIIC0_RW"); ++ break; ++ case MIU_CLIENT_IVE_RW: ++ strcpy(clientName, "IVE_RW"); ++ break; ++ case MIU_CLIENT_DIAMOND_RW: ++ strcpy(clientName, "DIAMOND_RW"); ++ // DIAMOND ++ case MIU_CLIENT_MIPS_RW: ++ strcpy(clientName, "CPU_RW"); ++ break; ++ // DLA Highway ++ case MIU_CLIENT_DLA_HIWAY: ++ strcpy(clientName, "DLA_HIWAY_RW"); ++ break; ++ default: ++ MIU_HAL_ERR("Input wrong clientId [%d]\n", clientId); ++ iRet = -1; ++ break; ++ } ++ return iRet; ++} ++ ++int clientId_KernelProtectToName(MS_U16 clientId, char *clientName) ++{ ++ return HAL_MIU_ClientIdToName(clientId, clientName); ++} ++EXPORT_SYMBOL(clientId_KernelProtectToName); ++ ++#ifdef CONFIG_CAM_CLK ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ ++ if (pDramInfo) ++ { ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = CamClkRateGet(CAMCLK_ddrpll_clk) / 1000000; ++ pDramInfo->miupll_freq = CamClkRateGet(CAMCLK_miupll_clk) / 1000000; ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++#else ++int HAL_MIU_Info(MIU_DramInfo_Hal *pDramInfo) ++{ ++ int ret = -1; ++ unsigned int ddfset = 0; ++ ++ if (pDramInfo) ++ { ++ ddfset = (INREGMSK16(BASE_REG_ATOP_PA + REG_ID_19, 0x00FF) << 16) + INREGMSK16(BASE_REG_ATOP_PA + REG_ID_18, 0xFFFF); ++ ++ pDramInfo->size = HAL_MIU_ProtectDramSize(); ++ pDramInfo->dram_freq = ((432 * 4 * 4) << 19) / ddfset; ++ pDramInfo->miupll_freq = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ pDramInfo->type = INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0003);; ++ pDramInfo->data_rate = (1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8)); ++ pDramInfo->bus_width = (16 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x000C) >> 2)); ++ pDramInfo->ssc = ((INREGMSK16(BASE_REG_ATOP_PA + REG_ID_14, 0xC000)==0x8000)? 0 : 1); ++ ++ ret = 0; ++ } ++ ++ return ret; ++} ++#endif ++ ++static MS_U8 m_u8PageSize256Enable = 0; ++ ++int HAL_MMU_SetPageSize(unsigned char u8PgSz256En) ++{ ++ MS_U16 u16CtrlRegVal; ++ ++ m_u8PageSize256Enable = u8PgSz256En; ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_CTRL); ++ if (m_u8PageSize256Enable) ++ { ++ u16CtrlRegVal |= REG_MMU_CTRL_PG_SIZE; ++ } ++ else ++ { ++ u16CtrlRegVal &= ~REG_MMU_CTRL_PG_SIZE; ++ } ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, u16CtrlRegVal); ++ ++ return 0; ++} ++ ++int HAL_MMU_SetRegion(unsigned short u16Region, unsigned short u16ReplaceRegion) ++{ ++ MS_U16 u16CtrlRegVal; ++ MS_U8 u8RegShiftVal = (m_u8PageSize256Enable ? 3 : 4); ++ ++ if (u16Region >> u8RegShiftVal) ++ { ++ MIU_HAL_ERR("Region value over range(0x%x)\n", u16Region); ++ return -1; ++ } ++ ++ if (u16ReplaceRegion >> u8RegShiftVal) ++ { ++ MIU_HAL_ERR("Replace Region value over range(0x%x)\n", u16ReplaceRegion); ++ return -1; ++ } ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_CTRL) & ~(BITS_RANGE(REG_MMU_CTRL_REGION_MASK)) & ~(BITS_RANGE(REG_MMU_CTRL_RP_REGION_MASK)); ++ u16CtrlRegVal |= (u16Region << 8); ++ u16CtrlRegVal |= (u16ReplaceRegion << 12); ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, u16CtrlRegVal); ++ ++ return 0; ++} ++ ++int HAL_MMU_Map(unsigned short u16PhyAddrEntry, unsigned short u16VirtAddrEntry) ++{ ++ MS_U16 u16RegVal; ++ ++ if ((u16PhyAddrEntry >> 10) || (u16VirtAddrEntry >> 10)) ++ { ++ MIU_HAL_ERR("Entry value over range(Phy:0x%x, Virt:0x%x)\n", u16PhyAddrEntry, u16VirtAddrEntry); ++ return -1; ++ } ++ ++ // reg_mmu_wdata ++ HAL_MIU_Write2Byte(REG_MMU_W_DATA, u16VirtAddrEntry); ++ ++ // reg_mmu_entry ++ u16RegVal = REG_MMU_RW_ENTRY_MODE | u16PhyAddrEntry; ++ HAL_MIU_Write2Byte(REG_MMU_RW_ENTRY, u16RegVal); ++ ++ // reg_mmu_access ++ HAL_MIU_Write2Byte(REG_MMU_ACCESS, BIT0); ++ ++ return 0; ++} ++ ++unsigned short HAL_MMU_MapQuery(unsigned short u16PhyAddrEntry) ++{ ++ MS_U16 u16RegVal; ++ ++ if (u16PhyAddrEntry >> 10) ++ { ++ MIU_HAL_ERR("Entry value over range(Phy:0x%x)\n", u16PhyAddrEntry); ++ return -1; ++ } ++ ++ // reg_mmu_entry ++ HAL_MIU_Write2Byte(REG_MMU_RW_ENTRY, u16PhyAddrEntry); ++ ++ // reg_mmu_access ++ HAL_MIU_Write2Byte(REG_MMU_ACCESS, BIT0); ++ ++ ndelay(100); ++ ++ // reg_mmu_rdata ++ u16RegVal = HAL_MIU_Read2Byte(REG_MMU_R_DATA); ++ ++ return u16RegVal; ++} ++ ++int HAL_MMU_UnMap(unsigned short u16PhyAddrEntry) ++{ ++ MS_U16 u16RegVal; ++ ++ if (u16PhyAddrEntry >> 10) ++ { ++ MIU_HAL_ERR("Entry value over range(Phy:0x%x)\n", u16PhyAddrEntry); ++ return -1; ++ } ++ ++ // reg_mmu_wdata ++ HAL_MIU_Write2Byte(REG_MMU_W_DATA, MMU_INVALID_ENTRY_VAL); ++ ++ // reg_mmu_entry ++ u16RegVal = REG_MMU_RW_ENTRY_MODE | u16PhyAddrEntry; ++ HAL_MIU_Write2Byte(REG_MMU_RW_ENTRY, u16RegVal); ++ ++ // reg_mmu_access ++ HAL_MIU_Write2Byte(REG_MMU_ACCESS, BIT0); ++ ++ return 0; ++} ++ ++int HAL_MMU_Enable(unsigned char u8Enable) ++{ ++ MS_U16 u16CtrlRegVal; ++ MS_U16 u16IrqRegVal; ++ ++ u16CtrlRegVal = HAL_MIU_Read2Byte(REG_MMU_CTRL); ++ u16IrqRegVal = HAL_MIU_Read2Byte(REG_MMU_IRQ_CTRL); ++ ++ if (u8Enable) ++ { ++ u16CtrlRegVal |= REG_MMU_CTRL_ENABLE; ++ // Enable IRQ ++ //u16IrqRegVal |= (REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ u16IrqRegVal &= ~(REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ } ++ else ++ { ++ u16CtrlRegVal &= ~REG_MMU_CTRL_ENABLE; ++ // Disable IRQ ++ //u16IrqRegVal &= ~(REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ u16IrqRegVal |= (REG_MMU_IRQ_RW_MASK | REG_MMU_IRQ_RD_MASK | REG_MMU_IRQ_WR_MASK); ++ } ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, u16CtrlRegVal); ++ HAL_MIU_Write2Byte(REG_MMU_IRQ_CTRL, u16IrqRegVal); ++ ++ return 0; ++} ++ ++int HAL_MMU_Reset(void) ++{ ++ MS_U16 u16RetryNum=100; ++ ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, 0x0); ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, REG_MMU_CTRL_RESET | REG_MMU_CTRL_RESET_INIT_VAL); ++ ++ do { ++ if (HAL_MIU_Read2Byte(REG_MMU_CTRL) & REG_MMU_CTRL_INIT_DONE) ++ { ++ HAL_MIU_Write2Byte(REG_MMU_CTRL, 0x0); ++ return 0; ++ } ++ ++ u16RetryNum--; ++ } while (u16RetryNum > 0); ++ ++ MIU_HAL_ERR("Reset timeout!\n"); ++ ++ return -1; ++} ++unsigned int HAL_MMU_Status(unsigned short *u16PhyAddrEntry, unsigned short *u16ClientId, unsigned char *u8IsWriteCmd) ++{ ++ MS_U16 u16IrqRegVal; ++ unsigned int u32Status=0; ++ ++ u16IrqRegVal = HAL_MIU_Read2Byte(REG_MMU_IRQ_CTRL); ++ ++ if (u16IrqRegVal & REG_MMU_IRQ_RW_FLAG) ++ { ++ *u16PhyAddrEntry = HAL_MIU_Read2Byte(REG_MMU_COLLISION_ENTRY); ++ u16IrqRegVal |= REG_MMU_IRQ_RW_CLR; ++ u32Status |= E_HAL_MMU_STATUS_RW_COLLISION; ++ } ++ ++ if ((u16IrqRegVal & REG_MMU_IRQ_RD_FLAG) || (u16IrqRegVal & REG_MMU_IRQ_WR_FLAG)) ++ { ++ *u16PhyAddrEntry = HAL_MIU_Read2Byte(REG_MMU_INVALID_ENTRY); ++ *u16ClientId = BITS_RANGE_VAL(HAL_MIU_Read2Byte(REG_MMU_INVALID_CLIENT_ID),REG_MMU_IRQ_INVALID_ID_MASK); ++ *u8IsWriteCmd = (u16IrqRegVal & REG_MMU_IRQ_INVALID_RW)?1:0; ++ ++ if (u16IrqRegVal & REG_MMU_IRQ_RD_FLAG) ++ { ++ u16IrqRegVal |= REG_MMU_IRQ_RD_CLR; ++ u32Status |= E_HAL_MMU_STATUS_R_INVALID; ++ } ++ ++ if (u16IrqRegVal & REG_MMU_IRQ_WR_FLAG) ++ { ++ u16IrqRegVal |= REG_MMU_IRQ_WR_CLR; ++ u32Status |= E_HAL_MMU_STATUS_W_INVALID; ++ } ++ } ++ ++ // Clear IRQ ++ if (u32Status != E_HAL_MMU_STATUS_NORMAL) ++ { ++ HAL_MIU_Write2Byte(REG_MMU_IRQ_CTRL, u16IrqRegVal); ++ HAL_MIU_Write2Byte(REG_MMU_IRQ_CTRL, 0x0); ++ } ++ ++ return u32Status; ++} +diff --git a/drivers/sstar/mma_heap/Kconfig b/drivers/sstar/mma_heap/Kconfig +new file mode 100755 +index 000000000000..23bcab3226ee +--- /dev/null ++++ b/drivers/sstar/mma_heap/Kconfig +@@ -0,0 +1,8 @@ ++config MSTAR_MMAHEAP ++bool "MMA HEAP" ++select MSTAR_MIU ++default n ++ ++help ++ MStar MMA HEAP driver function ++ +diff --git a/drivers/sstar/mma_heap/Makefile b/drivers/sstar/mma_heap/Makefile +new file mode 100755 +index 000000000000..70a3d7e2d5e7 +--- /dev/null ++++ b/drivers/sstar/mma_heap/Makefile +@@ -0,0 +1,17 @@ ++# ++# Makefile for MStar MMA HEAP drivers. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include/sys/common ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/mma_heap ++EXTRA_CFLAGS += -Idrivers/sstar/miu ++EXTRA_CFLAGS += -Idrivers/sstar/cpu/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++# specific options ++EXTRA_CFLAGS += -Idrivers/staging/android/ion ++ ++# files ++obj-$(CONFIG_MSTAR_MMAHEAP) += mdrv-mma_heap.o ++mdrv-mma_heap-objs += mdrv_mma_heap.o region_substract.o +diff --git a/drivers/sstar/mma_heap/mdrv_mma_heap.c b/drivers/sstar/mma_heap/mdrv_mma_heap.c +new file mode 100755 +index 000000000000..27861282acf3 +--- /dev/null ++++ b/drivers/sstar/mma_heap/mdrv_mma_heap.c +@@ -0,0 +1,371 @@ ++/* ++* mdrv_mma_heap.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: malloc.peng ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "mdrv_mma_heap.h" ++ ++#include ++#include ++//#include ++#include ++//#include ++#include // ++#include ++#include ++#include ++#include ++#include // ++#include // ++#include // ++#include // ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include // ++#include ++ ++#include // ++#include ++ ++#define MMU_MAX_SIZE 0x4000000 ++#define MMU_HEAP_NAME "MMU_MMA" ++ ++int mstar_driver_boot_mma_buffer_num = 0; ++struct MMA_BootArgs_Config mma_config[MAX_MMA_AREAS]; ++bool b_mma_memblock_remove = false; ++ ++EXPORT_SYMBOL(mma_config); ++EXPORT_SYMBOL(mstar_driver_boot_mma_buffer_num); ++ ++/* ++example: ++mma_heap=mma_heap_name0,miu=0,sz=0x300000 ++mma_heap=mma_heap_name_1,miu=0,sz=0x200000 ++mma_heap=mma_heap_name_2,miu=0,sz=0x400000 ++mma_heap=mma_heap_name_3,miu=1,sz=0x100000 ++*/ ++static bool parse_mmaheap_config(char *cmdline, struct MMA_BootArgs_Config * heapconfig) ++{ ++ char *option; ++ int leng = 0; ++ //bool has_start = false; ++ //int i; ++ ++ if(cmdline == NULL) ++ goto INVALID_HEAP_CONFIG; ++ ++ option = strstr(cmdline, ","); ++ leng = (int)(option - cmdline); ++ if(leng > (MMA_HEAP_NAME_LENG-1)) ++ leng = MMA_HEAP_NAME_LENG -1; ++ ++ strncpy(heapconfig->name, cmdline, leng); ++ heapconfig->name[leng] = '\0'; ++ ++ option = strstr(cmdline, "sz="); ++ if(option == NULL) ++ goto INVALID_HEAP_CONFIG; ++ option = strstr(cmdline, "miu="); ++ if(option == NULL) ++ goto INVALID_HEAP_CONFIG; ++ sscanf(option, "miu=%d,sz=%lx", &heapconfig->miu, &heapconfig->size); ++ option = strstr(cmdline, "max_start_off"); ++ if (option) ++ sscanf(option, "max_start_off=%lx", &heapconfig->max_start_offset_to_curr_bus_base); ++ else ++ heapconfig->max_start_offset_to_curr_bus_base = -1UL; ++ option = strstr(cmdline, "max_end_off"); ++ if (option) ++ sscanf(option, "max_end_off=%lx", &heapconfig->max_end_offset_to_curr_bus_base); ++ else ++ heapconfig->max_end_offset_to_curr_bus_base = -1UL; ++ ++#if 0//debug code ++ printk(" debug %s %d success name:",__FUNCTION__,__LINE__); ++ for(i=0;iname[i]); ++ } ++ printk(" miu=%d,sz=%lx \n", heapconfig->miu, heapconfig->size); ++ printk("Max start %lx max end %lx\n", heapconfig->max_start_offset_to_curr_bus_base, heapconfig->max_end_offset_to_curr_bus_base); ++#endif ++ ++ return true; ++ ++INVALID_HEAP_CONFIG: ++ heapconfig->size = 0; ++ #if 0//debug code ++ printk("samson debug %s %d fail \n",__FUNCTION__,__LINE__); ++ #endif ++ return false; ++} ++ ++int __init get_mma_memblock_remove(char *cmdline) ++{ ++ int value = 0; ++ if(cmdline) ++ sscanf(cmdline, "%d", &value); ++ if(value != 0) ++ b_mma_memblock_remove = true; ++ return 0; ++} ++ ++early_param("mma_memblock_remove", get_mma_memblock_remove); ++ ++int __init setup_mma_info(char *cmdline) ++{ ++ if(!parse_mmaheap_config(cmdline, &mma_config[mstar_driver_boot_mma_buffer_num])) ++ printk(KERN_ERR "error: mma_heap args invalid\n"); ++ else ++ mstar_driver_boot_mma_buffer_num++; ++ ++ return 0; ++} ++ ++early_param("mma_heap", setup_mma_info); ++ ++void deal_with_reserve_mma_heap(void) ++{ ++ int i=0,j=0,k=0; ++ phys_addr_t base = 0; ++ int ret; ++ phys_addr_t start; ++ phys_addr_t end; ++ phys_addr_t size; ++ ++ if(mstar_driver_boot_mma_buffer_num == 0) ++ { ++ //need do nothing ++ printk(KERN_WARNING "no any mma heap\n"); ++ return; ++ } ++ ++ //check whether have same mma heap name. ++ for(i=0;i 0) ++ break; ++ count ++; ++ } ++ } ++ else ++ { ++ base = memblock_find_in_range(start, end, size, PAGE_SIZE); ++ } ++ ++ if(base == 0)//fail ++ { ++ printk(KERN_ERR "memblock_find_in_range fail "); ++ #ifdef CONFIG_PHYS_ADDR_T_64BIT ++ printk("start=0x%llx, end=0x%llx, size=0x%llx\n",(unsigned long long)start, (unsigned long long)end, (unsigned long long)size); ++ #else ++ printk("start=0x%lx, end=0x%lx, size=0x%lx\n",(unsigned long)start, (unsigned long)end, (unsigned long)size); ++ #endif ++ ++ ++ ++ //In early stage of starting kernel,do not use BUG(). ++ //replace BUG() with much normal printk to let user notice what happened for debug easier. ++ //BUG(); ++ printk("#####################################\n"); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_find_in_range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("#####################################\n"); ++ ++ return; ++ } ++ ++ //In early stage of starting kernel,do not use BUG_ON(). ++ //replace BUG_ON() with much normal printk to let user notice what happened for debug easier. ++ //BUG_ON(base < start || base > end); ++ if(base < start || base > end) ++ { ++ printk("#####################################\n"); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d base range fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("#####################################\n"); ++ return; ++ } ++ ++ //printk("memblock_find_in_range success \n"); ++ ++ ret = memblock_reserve(base,size); ++ //printk("%s:%d ",__FUNCTION__,__LINE__); ++ if(ret != 0)//fail ++ { ++ printk(KERN_ERR "%s memblock_reserve fail , ret=%d\n",__FUNCTION__,ret); ++ #ifdef CONFIG_PHYS_ADDR_T_64BIT ++ printk("baset=0x%llx size=0x%llx\n",(unsigned long long)base,(unsigned long long)size); ++ #else ++ printk("base=0x%lx size=0x%lx\n",(unsigned long)base,(unsigned long)size); ++ #endif ++ ++ //In early stage of starting kernel,do not use BUG(). ++ //replace BUG() with much normal printk to let user notice what happened for debug easier. ++ //BUG(); ++ printk("#####################################\n"); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("%s:%d memblock_reserve fail,error !!!! \n",__FUNCTION__,__LINE__); ++ printk("#####################################\n"); ++ return; ++ } ++ else ++ { ++ if(b_mma_memblock_remove) ++ memblock_remove(base,size); ++ mma_config[i].reserved_start = base; ++ printk("%s memblock_reserve success mma_config[%d].reserved_start=",__FUNCTION__,i); ++ #ifdef CONFIG_PHYS_ADDR_T_64BIT ++ printk("0x%llx",(unsigned long long)mma_config[i].reserved_start); ++ #else ++ printk("0x%lx",(unsigned long)mma_config[i].reserved_start); ++ #endif ++ printk("\n"); ++ ++#if 0//debug code ++ printk(" debug %s %d name:",__FUNCTION__,__LINE__); ++ for(j=0;j ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "region_substract.h" ++ ++#undef DBG_INFO ++#undef DBG_ERR ++#define DBG_INFO(...) ++#define DBG_ERR(...) ++ ++/* 1 if two RECTs overlap. ++ * 0 if two RECTs do not overlap. ++ */ ++#define EXTENTCHECK(r1, r2) \ ++ ((r1)->right > (r2)->left && \ ++ (r1)->left < (r2)->right && \ ++ (r1)->bottom > (r2)->top && \ ++ (r1)->top < (r2)->bottom) ++ ++ ++/* ++ * Allocate a new clipping rect and add it to the region. ++ */ ++#define NEWCLIPRECT(region, rect) \ ++ {\ ++ rect = ClipRectAlloc(region->heap);\ ++ rect->next = NULL;\ ++ rect->prev = region->tail;\ ++ if (region->tail)\ ++ region->tail->next = rect;\ ++ region->tail = rect;\ ++ if (region->head == NULL)\ ++ region->head = rect;\ ++ } ++ ++/** ++ * \def CopyRegion ++ * \brief Is an alias of \a ClipRgnCopy ++ * \sa ClipRgnCopy ++ */ ++#define CopyRegion ClipRgnCopy ++ ++/* MAX/MIN/ABS macors */ ++/** ++ * \def MAX(x, y) ++ * \brief A macro returns the maximum of \a x and \a y. ++ */ ++#ifndef MAX ++#define MAX(x, y) (((x) > (y))?(x):(y)) ++#endif ++/** ++ * \def MIN(x, y) ++ * \brief A macro returns the minimum of \a x and \a y. ++ */ ++#ifndef MIN ++#define MIN(x, y) (((x) < (y))?(x):(y)) ++#endif ++/** ++ * \def ABS(x) ++ * \brief A macro returns the absolute value of \a x. ++ */ ++#ifndef ABS ++#define ABS(x) (((x)<0) ? -(x) : (x)) ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++ ++typedef void (*voidProcp1)(CLIPRGN *region, const CLIPRECT *r1, const CLIPRECT *r1End, ++ const CLIPRECT *r2, const CLIPRECT *r2End, int top, int bottom); ++typedef void (*voidProcp2)(CLIPRGN *region, const CLIPRECT *r, const CLIPRECT *rEnd, ++ int top, int bottom); ++ ++static struct kmem_cache *cliprect_cache=NULL; ++ ++ ++void* ClipRectAlloc (PBLOCKHEAP heap) ++{ ++ return kmem_cache_alloc(cliprect_cache,GFP_KERNEL); ++} ++void FreeClipRect (PBLOCKHEAP heap, void* data) ++{ ++ kmem_cache_free(cliprect_cache,data); ++} ++ ++/** ++ * \fn void SetRectEmpty (RECT* prc) ++ * \brief Empties a rectangle. ++ * ++ * ++ * \param prc The pointer to the rectangle. ++ * ++ * \sa SetRect ++ */ ++static inline void SetRectEmpty (RECT* prc) ++{ ++ (prc)->left = (prc)->top = (prc)->right = (prc)->bottom = 0; ++} ++ ++BOOL IsEmptyClipRgn (const CLIPRGN* pRgn) ++{ ++ if (pRgn->head == NULL) ++ return TRUE; ++ ++ return FALSE; ++} ++EXPORT_SYMBOL(IsEmptyClipRgn); ++BOOL IsRectEmpty (const RECT* prc) ++{ ++ if( prc->left == prc->right ) return TRUE; ++ if( prc->top == prc->bottom ) return TRUE; ++ return FALSE; ++} ++ ++void EmptyClipRgn (PCLIPRGN pRgn) ++{ ++ PCLIPRECT pCRect, pTemp; ++ ++ pCRect = pRgn->head; ++ while (pCRect) { ++ pTemp = pCRect->next; ++ FreeClipRect (pRgn->heap, pCRect); ++ pCRect = pTemp; ++ } ++ ++ pRgn->type = NULLREGION; ++ SetRectEmpty (&pRgn->rcBound); ++ pRgn->head = NULL; ++ pRgn->tail = NULL; ++} ++EXPORT_SYMBOL(EmptyClipRgn); ++ ++/* Init a region */ ++void InitClipRgn (PCLIPRGN pRgn, PBLOCKHEAP heap) ++{ ++ pRgn->type = NULLREGION; ++ SetRectEmpty (&pRgn->rcBound); ++ pRgn->head = NULL; ++ pRgn->tail = NULL; ++ ++ pRgn->heap = heap; // read-only field. ++} ++EXPORT_SYMBOL(InitClipRgn); ++/* Reset a region */ ++BOOL SetClipRgn (PCLIPRGN pRgn, const RECT* pRect) ++{ ++ PCLIPRECT pClipRect; ++ ++ if (IsRectEmpty (pRect)) ++ return FALSE; ++ ++ // empty rgn first ++ EmptyClipRgn (pRgn); ++ ++ // get a new clip rect from free list ++ pClipRect = ClipRectAlloc (pRgn->heap); ++ if (pClipRect == NULL) ++ return FALSE; ++ ++ // set clip rect ++ pClipRect->rc = *pRect; ++ pClipRect->next = NULL; ++ pClipRect->prev = NULL; ++ ++ pRgn->type = SIMPLEREGION; ++ pRgn->head = pRgn->tail = pClipRect; ++ pRgn->rcBound = *pRect; ++ ++ return TRUE; ++} ++ ++/* Re-calculate the rcBound of a region */ ++static void REGION_SetExtents (CLIPRGN *region) ++{ ++ PCLIPRECT cliprect; ++ RECT *pExtents; ++ ++ if (region->head == NULL) { ++ region->rcBound.left = 0; region->rcBound.top = 0; ++ region->rcBound.right = 0; region->rcBound.bottom = 0; ++ return; ++ } ++ ++ pExtents = ®ion->rcBound; ++ ++ /* ++ * Since head is the first rectangle in the region, it must have the ++ * smallest top and since tail is the last rectangle in the region, ++ * it must have the largest bottom, because of banding. Initialize left and ++ * right from head and tail, resp., as good things to initialize them ++ * to... ++ */ ++ pExtents->left = region->head->rc.left; ++ pExtents->top = region->head->rc.top; ++ pExtents->right = region->tail->rc.right; ++ pExtents->bottom = region->tail->rc.bottom; ++ ++ cliprect = region->head; ++ while (cliprect) { ++ if (cliprect->rc.left < pExtents->left) ++ pExtents->left = cliprect->rc.left; ++ if (cliprect->rc.right > pExtents->right) ++ pExtents->right = cliprect->rc.right; ++ ++ cliprect = cliprect->next; ++ } ++} ++ ++BOOL ClipRgnCopy (PCLIPRGN pDstRgn, const CLIPRGN* pSrcRgn) ++{ ++ PCLIPRECT pcr; ++ PCLIPRECT pnewcr, prev; ++ ++ // return false if the destination region is not an empty one. ++ if (pDstRgn == pSrcRgn) ++ return FALSE; ++ ++ EmptyClipRgn (pDstRgn); ++ if (!(pcr = pSrcRgn->head)) ++ return TRUE; ++ ++ pnewcr = ClipRectAlloc (pDstRgn->heap); ++ ++ pDstRgn->head = pnewcr; ++ pnewcr->rc = pcr->rc; ++ ++ prev = NULL; ++ while (pcr->next) { ++ ++ pnewcr->next = ClipRectAlloc (pDstRgn->heap); ++ pnewcr->prev = prev; ++ ++ prev = pnewcr; ++ pcr = pcr->next; ++ pnewcr = pnewcr->next; ++ ++ pnewcr->rc = pcr->rc; ++ } ++ ++ pnewcr->prev = prev; ++ pnewcr->next = NULL; ++ pDstRgn->tail = pnewcr; ++ ++ pDstRgn->type = pSrcRgn->type; ++ pDstRgn->rcBound = pSrcRgn->rcBound; ++ ++ return TRUE; ++} ++ ++/*********************************************************************** ++ * REGION_Coalesce ++ * ++ * Attempt to merge the rects in the current band with those in the ++ * previous one. Used only by REGION_RegionOp. ++ * ++ * Results: ++ * The new index for the previous band. ++ * ++ * Side Effects: ++ * If coalescing takes place: ++ * - rectangles in the previous band will have their bottom fields ++ * altered. ++ * - some clipping rect will be deleted. ++ * ++ */ ++static CLIPRECT* REGION_Coalesce ( ++ CLIPRGN *region, /* Region to coalesce */ ++ CLIPRECT *prevStart, /* start of previous band */ ++ CLIPRECT *curStart /* start of current band */ ++) { ++ CLIPRECT *newStart; /* Start of new band */ ++ CLIPRECT *pPrevRect; /* Current rect in previous band */ ++ CLIPRECT *pCurRect; /* Current rect in current band */ ++ CLIPRECT *temp; /* Temporary clipping rect */ ++ int curNumRects; /* Number of rectangles in current band */ ++ int prevNumRects; /* Number of rectangles in previous band */ ++ int bandtop; /* top coordinate for current band */ ++ ++ if (prevStart == NULL) prevStart = region->head; ++ if (curStart == NULL) curStart = region->head; ++ ++ if (prevStart == curStart) ++ return prevStart; ++ ++ newStart = pCurRect = curStart; ++ ++ pPrevRect = prevStart; ++ temp = prevStart; ++ prevNumRects = 0; ++ while (temp != curStart) { ++ prevNumRects ++; ++ temp = temp->next; ++ } ++ ++ /* ++ * Figure out how many rectangles are in the current band. Have to do ++ * this because multiple bands could have been added in REGION_RegionOp ++ * at the end when one region has been exhausted. ++ */ ++ pCurRect = curStart; ++ bandtop = pCurRect->rc.top; ++ curNumRects = 0; ++ while (pCurRect && (pCurRect->rc.top == bandtop)) { ++ curNumRects ++; ++ pCurRect = pCurRect->next; ++ } ++ ++ if (pCurRect) { ++ /* ++ * If more than one band was added, we have to find the start ++ * of the last band added so the next coalescing job can start ++ * at the right place... (given when multiple bands are added, ++ * this may be pointless -- see above). ++ */ ++ temp = region->tail; ++ while (temp->prev->rc.top == temp->rc.top) { ++ temp = temp->prev; ++ } ++ newStart = temp; ++ } ++ ++ if ((curNumRects == prevNumRects) && (curNumRects != 0)) { ++ pCurRect = curStart; ++ /* ++ * The bands may only be coalesced if the bottom of the previous ++ * matches the top scanline of the current. ++ */ ++ if (pPrevRect->rc.bottom == pCurRect->rc.top) { ++ /* ++ * Make sure the bands have rects in the same places. This ++ * assumes that rects have been added in such a way that they ++ * cover the most area possible. I.e. two rects in a band must ++ * have some horizontal space between them. ++ */ ++ do { ++ if ((pPrevRect->rc.left != pCurRect->rc.left) || ++ (pPrevRect->rc.right != pCurRect->rc.right)) ++ { ++ /* ++ * The bands don't line up so they can't be coalesced. ++ */ ++ return newStart; ++ } ++ pPrevRect = pPrevRect->next; ++ pCurRect = pCurRect->next; ++ } while (--prevNumRects); ++ ++ /* ++ * If only one band was added to the region, we have to backup ++ * newStart to the start of the previous band. ++ */ ++ if (pCurRect == NULL) { ++ newStart = prevStart; ++ } ++ ++ /* ++ * The bands may be merged, so set the bottom of each rect ++ * in the previous band to that of the corresponding rect in ++ * the current band. ++ */ ++ pCurRect = curStart; ++ pPrevRect = prevStart; ++ do { ++ pPrevRect->rc.bottom = pCurRect->rc.bottom; ++ pPrevRect = pPrevRect->next; ++ ++ if (pCurRect->next) ++ pCurRect->next->prev = pCurRect->prev; ++ else ++ region->tail = pCurRect->prev; ++ if (pCurRect->prev) ++ pCurRect->prev->next = pCurRect->next; ++ else ++ region->head = pCurRect->next; ++ ++ temp = pCurRect->next; ++ FreeClipRect (region->heap, pCurRect); ++ pCurRect = temp; ++ } while (--curNumRects); ++ ++ } ++ } ++ return (newStart); ++} ++ ++/*********************************************************************** ++ * REGION_RegionOp ++ * ++ * Apply an operation to two regions. Called by Union, ++ * Xor, Subtract, Intersect... ++ * ++ * Results: ++ * None. ++ * ++ * Side Effects: ++ * The new region is overwritten. ++ * ++ * Notes: ++ * The idea behind this function is to view the two regions as sets. ++ * Together they cover a rectangle of area that this function divides ++ * into horizontal bands where points are covered only by one region ++ * or by both. For the first case, the nonOverlapFunc is called with ++ * each the band and the band's upper and lower rcBound. For the ++ * second, the overlapFunc is called to process the entire band. It ++ * is responsible for clipping the rectangles in the band, though ++ * this function provides the boundaries. ++ * At the end of each band, the new region is coalesced, if possible, ++ * to reduce the number of rectangles in the region. ++ * ++ */ ++static void ++REGION_RegionOp( ++ CLIPRGN *newReg, /* Place to store result */ ++ const CLIPRGN *reg1, /* First region in operation */ ++ const CLIPRGN *reg2, /* 2nd region in operation */ ++ voidProcp1 overlapFunc, /* Function to call for over-lapping bands */ ++ voidProcp2 nonOverlap1Func, /* Function to call for non-overlapping bands in region 1 */ ++ voidProcp2 nonOverlap2Func /* Function to call for non-overlapping bands in region 2 */ ++) { ++ CLIPRGN my_dst; ++ CLIPRGN* pdst; ++ const CLIPRECT *r1; /* Pointer into first region */ ++ const CLIPRECT *r2; /* Pointer into 2d region */ ++ const CLIPRECT *r1BandEnd; /* End of current band in r1 */ ++ const CLIPRECT *r2BandEnd; /* End of current band in r2 */ ++ int ybot; /* Bottom of intersection */ ++ int ytop; /* Top of intersection */ ++ CLIPRECT* prevBand; /* start of previous band in newReg */ ++ CLIPRECT* curBand; /* start of current band in newReg */ ++ int top; /* Top of non-overlapping band */ ++ int bot; /* Bottom of non-overlapping band */ ++ ++ /* ++ * Initialization: ++ * set r1, r2, r1End and r2End appropriately, preserve the important ++ * parts of the destination region until the end in case it's one of ++ * the two source regions, then mark the "new" region empty, allocating ++ * another array of rectangles for it to use. ++ */ ++ r1 = reg1->head; ++ r2 = reg2->head; ++ ++ ++ if (newReg == reg1 || newReg == reg2) { ++ InitClipRgn (&my_dst, newReg->heap); ++ pdst = &my_dst; ++ } ++ else { ++ EmptyClipRgn (newReg); ++ pdst = newReg; ++ } ++ ++ ++ /* ++ * Initialize ybot and ytop. ++ * In the upcoming loop, ybot and ytop serve different functions depending ++ * on whether the band being handled is an overlapping or non-overlapping ++ * band. ++ * In the case of a non-overlapping band (only one of the regions ++ * has points in the band), ybot is the bottom of the most recent ++ * intersection and thus clips the top of the rectangles in that band. ++ * ytop is the top of the next intersection between the two regions and ++ * serves to clip the bottom of the rectangles in the current band. ++ * For an overlapping band (where the two regions intersect), ytop clips ++ * the top of the rectangles of both regions and ybot clips the bottoms. ++ */ ++ if (reg1->rcBound.top < reg2->rcBound.top) ++ ybot = reg1->rcBound.top; ++ else ++ ybot = reg2->rcBound.top; ++ ++ /* ++ * prevBand serves to mark the start of the previous band so rectangles ++ * can be coalesced into larger rectangles. qv. miCoalesce, above. ++ * In the beginning, there is no previous band, so prevBand == curBand ++ * (curBand is set later on, of course, but the first band will always ++ * start at index 0). prevBand and curBand must be indices because of ++ * the possible expansion, and resultant moving, of the new region's ++ * array of rectangles. ++ */ ++ prevBand = pdst->head; ++ ++ do { ++ curBand = pdst->tail; ++ ++ /* ++ * This algorithm proceeds one source-band (as opposed to a ++ * destination band, which is determined by where the two regions ++ * intersect) at a time. r1BandEnd and r2BandEnd serve to mark the ++ * rectangle after the last one in the current band for their ++ * respective regions. ++ */ ++ r1BandEnd = r1; ++ while (r1BandEnd && (r1BandEnd->rc.top == r1->rc.top)) ++ r1BandEnd = r1BandEnd->next; ++ ++ r2BandEnd = r2; ++ while (r2BandEnd && (r2BandEnd->rc.top == r2->rc.top)) ++ r2BandEnd = r2BandEnd->next; ++ ++ /* ++ * First handle the band that doesn't intersect, if any. ++ * ++ * Note that attention is restricted to one band in the ++ * non-intersecting region at once, so if a region has n ++ * bands between the current position and the next place it overlaps ++ * the other, this entire loop will be passed through n times. ++ */ ++ if (r1->rc.top < r2->rc.top) { ++ top = MAX (r1->rc.top, ybot); ++ bot = MIN (r1->rc.bottom, r2->rc.top); ++ ++ if ((top != bot) && (nonOverlap1Func != NULL)) ++ (* nonOverlap1Func) (pdst, r1, r1BandEnd, top, bot); ++ ++ ytop = r2->rc.top; ++ } ++ else if (r2->rc.top < r1->rc.top) { ++ top = MAX (r2->rc.top, ybot); ++ bot = MIN (r2->rc.bottom, r1->rc.top); ++ ++ if ((top != bot) && (nonOverlap2Func != NULL)) ++ (* nonOverlap2Func) (pdst, r2, r2BandEnd, top, bot); ++ ++ ytop = r1->rc.top; ++ } ++ else { ++ ytop = r1->rc.top; ++ } ++ ++ /* ++ * If any rectangles got added to the region, try and coalesce them ++ * with rectangles from the previous band. Note we could just do ++ * this test in miCoalesce, but some machines incur a not ++ * inconsiderable cost for function calls, so... ++ */ ++ if (pdst->tail != curBand) { ++ if(curBand)curBand=curBand->next; ++ prevBand = REGION_Coalesce (pdst, prevBand, curBand); ++ } ++ ++ /* ++ * Now see if we've hit an intersecting band. The two bands only ++ * intersect if ybot > ytop ++ */ ++ ybot = MIN (r1->rc.bottom, r2->rc.bottom); ++ curBand = pdst->tail; ++ if (ybot > ytop) ++ (* overlapFunc) (pdst, r1, r1BandEnd, r2, r2BandEnd, ytop, ybot); ++ ++ if (pdst->tail != curBand) { ++ if(curBand)curBand=curBand->next; ++ prevBand = REGION_Coalesce (pdst, prevBand, curBand); ++ } ++ ++ /* ++ * If we've finished with a band (bottom == ybot) we skip forward ++ * in the region to the next band. ++ */ ++ if (r1->rc.bottom == ybot) ++ r1 = r1BandEnd; ++ if (r2->rc.bottom == ybot) ++ r2 = r2BandEnd; ++ } while (r1 && r2); ++ ++ /* ++ * Deal with whichever region still has rectangles left. ++ */ ++ curBand = pdst->tail; ++ if (r1) { ++ if (nonOverlap1Func != NULL) { ++ do { ++ r1BandEnd = r1; ++ while ((r1BandEnd) && (r1BandEnd->rc.top == r1->rc.top)) { ++ r1BandEnd = r1BandEnd->next; ++ } ++ (* nonOverlap1Func) (pdst, r1, r1BandEnd, ++ MAX (r1->rc.top, ybot), r1->rc.bottom); ++ r1 = r1BandEnd; ++ } while (r1); ++ } ++ } ++ else if ((r2) && (nonOverlap2Func != NULL)) ++ { ++ do { ++ r2BandEnd = r2; ++ while ((r2BandEnd) && (r2BandEnd->rc.top == r2->rc.top)) { ++ r2BandEnd = r2BandEnd->next; ++ } ++ (* nonOverlap2Func) (pdst, r2, r2BandEnd, ++ MAX (r2->rc.top, ybot), r2->rc.bottom); ++ r2 = r2BandEnd; ++ } while (r2); ++ } ++ ++ if (pdst->tail != curBand) { ++ if(curBand)curBand=curBand->next; ++ (void) REGION_Coalesce (pdst, prevBand, curBand); ++ } ++ ++ /* ++ * A bit of cleanup. To keep regions from growing without bound, ++ * we shrink the array of rectangles to match the new number of ++ * rectangles in the region. This never goes to 0, however... ++ * ++ * Only do this stuff if the number of rectangles allocated is more than ++ * twice the number of rectangles in the region (a simple optimization...). ++ */ ++ ++ if (pdst != newReg) { ++ EmptyClipRgn (newReg); ++ *newReg = my_dst; ++ } ++} ++ ++/*********************************************************************** ++ * REGION_SubtractNonO1 ++ * ++ * Deal with non-overlapping band for subtraction. Any parts from ++ * region 2 we discard. Anything from region 1 we add to the region. ++ * ++ * Results: ++ * None. ++ * ++ * Side Effects: ++ * region may be affected. ++ * ++ */ ++static void ++REGION_SubtractNonO1 (CLIPRGN *region, const CLIPRECT *r, const CLIPRECT *rEnd, ++ int top, int bottom) ++{ ++ CLIPRECT *newcliprect; ++ ++ while (r && r != rEnd) { ++ NEWCLIPRECT(region, newcliprect); ++ newcliprect->rc.left = r->rc.left; ++ newcliprect->rc.top = top; ++ newcliprect->rc.right = r->rc.right; ++ newcliprect->rc.bottom = bottom; ++ r = r->next; ++ } ++} ++ ++ ++/*********************************************************************** ++ * REGION_SubtractO ++ * ++ * Overlapping band subtraction. x1 is the left-most point not yet ++ * checked. ++ * ++ * Results: ++ * None. ++ * ++ * Side Effects: ++ * region may have rectangles added to it. ++ * ++ */ ++static void ++REGION_SubtractO (CLIPRGN *region, const CLIPRECT *r1, const CLIPRECT *r1End, ++ const CLIPRECT *r2, const CLIPRECT *r2End, int top, int bottom) ++{ ++ CLIPRECT *newcliprect; ++ int left; ++ ++ left = r1->rc.left; ++ while (r1 && r2 && (r1 != r1End) && (r2 != r2End)) { ++ if (r2->rc.right <= left) { ++ /* ++ * Subtrahend missed the boat: go to next subtrahend. ++ */ ++ r2 = r2->next; ++ } ++ else if (r2->rc.left <= left) ++ { ++ /* ++ * Subtrahend preceeds minuend: nuke left edge of minuend. ++ */ ++ left = r2->rc.right; ++ if (left >= r1->rc.right) ++ { ++ /* ++ * Minuend completely covered: advance to next minuend and ++ * reset left fence to edge of new minuend. ++ */ ++ r1 = r1->next; ++ if (r1 != r1End) ++ left = r1->rc.left; ++ } ++ else ++ { ++ /* ++ * Subtrahend now used up since it doesn't extend beyond ++ * minuend ++ */ ++ r2 = r2->next; ++ } ++ } ++ else if (r2->rc.left < r1->rc.right) ++ { ++ /* ++ * Left part of subtrahend covers part of minuend: add uncovered ++ * part of minuend to region and skip to next subtrahend. ++ */ ++ NEWCLIPRECT(region, newcliprect); ++ newcliprect->rc.left = left; ++ newcliprect->rc.top = top; ++ newcliprect->rc.right = r2->rc.left; ++ newcliprect->rc.bottom = bottom; ++ left = r2->rc.right; ++ if (left >= r1->rc.right) ++ { ++ /* ++ * Minuend used up: advance to new... ++ */ ++ r1 = r1->next; ++ if (r1 != r1End) ++ left = r1->rc.left; ++ } ++ else ++ { ++ /* ++ * Subtrahend used up ++ */ ++ r2 = r2->next; ++ } ++ } ++ else ++ { ++ /* ++ * Minuend used up: add any remaining piece before advancing. ++ */ ++ if (r1->rc.right > left) ++ { ++ NEWCLIPRECT(region, newcliprect); ++ newcliprect->rc.left = left; ++ newcliprect->rc.top = top; ++ newcliprect->rc.right = r1->rc.right; ++ newcliprect->rc.bottom = bottom; ++ } ++ r1 = r1->next; ++ if (r1 != r1End) ++ left = r1->rc.left; ++ } ++ } ++ ++ /* ++ * Add remaining minuend rectangles to region. ++ */ ++ while (r1 && r1 != r1End) ++ { ++ NEWCLIPRECT(region, newcliprect); ++ newcliprect->rc.left = left; ++ newcliprect->rc.top = top; ++ newcliprect->rc.right = r1->rc.right; ++ newcliprect->rc.bottom = bottom; ++ r1 = r1->next; ++ if (r1 != r1End) ++ left = r1->rc.left; ++ } ++} ++ ++/*********************************************************************** ++ * SubtractRegion ++ * ++ * Subtract rgnS from rgnM and leave the result in rgnD. ++ * S stands for subtrahend, M for minuend and D for difference. ++ * ++ * Results: ++ * TRUE. ++ * ++ * Side Effects: ++ * regD is overwritten. ++ * ++ */ ++BOOL SubtractRegion (CLIPRGN *rgnD, const CLIPRGN *rgnM, const CLIPRGN *rgnS) ++{ ++ /* check for trivial reject */ ++ if ( (!(rgnM->head)) || (!(rgnS->head)) || ++ (!EXTENTCHECK (&rgnM->rcBound, &rgnS->rcBound)) ) { ++ CopyRegion (rgnD, rgnM); ++ return TRUE; ++ } ++ ++ REGION_RegionOp (rgnD, rgnM, rgnS, REGION_SubtractO, ++ REGION_SubtractNonO1, NULL); ++ ++ /* ++ * Can't alter newReg's rcBound before we call miRegionOp because ++ * it might be one of the source regions and miRegionOp depends ++ * on the rcBound of those regions being the unaltered. Besides, this ++ * way there's no checking against rectangles that will be nuked ++ * due to coalescing, so we have to examine fewer rectangles. ++ */ ++ REGION_SetExtents (rgnD); ++ rgnD->type = (rgnD->head) ? COMPLEXREGION : NULLREGION; ++ ++ return TRUE; ++} ++EXPORT_SYMBOL(SubtractRegion); ++ ++/*********************************************************************** ++ * REGION_UnionNonO ++ * ++ * Handle a non-overlapping band for the union operation. Just ++ * Adds the rectangles into the region. Doesn't have to check for ++ * subsumption or anything. ++ * ++ * Results: ++ * None. ++ * ++ * Side Effects: ++ * region->numRects is incremented and the final rectangles overwritten ++ * with the rectangles we're passed. ++ * ++ */ ++static void ++REGION_UnionNonO (CLIPRGN *region, const CLIPRECT *r, const CLIPRECT *rEnd, int top, int bottom) ++{ ++ CLIPRECT *newcliprect; ++ ++ while (r && r != rEnd) { ++ NEWCLIPRECT (region, newcliprect); ++ newcliprect->rc.left = r->rc.left; ++ newcliprect->rc.top = top; ++ newcliprect->rc.right = r->rc.right; ++ newcliprect->rc.bottom = bottom; ++ ++ r = r->next; ++ } ++} ++ ++/*********************************************************************** ++ * REGION_UnionO ++ * ++ * Handle an overlapping band for the union operation. Picks the ++ * left-most rectangle each time and merges it into the region. ++ * ++ * Results: ++ * None. ++ * ++ * Side Effects: ++ * Rectangles are overwritten in region->rects and region->numRects will ++ * be changed. ++ * ++ */ ++static void ++REGION_UnionO(CLIPRGN *region, const CLIPRECT *r1, const CLIPRECT *r1End, ++ const CLIPRECT *r2, const CLIPRECT *r2End, int top, int bottom) ++{ ++ CLIPRECT *newcliprect; ++ ++#define MERGERECT(r) \ ++ if ((region->head) && \ ++ (region->tail->rc.top == top) && \ ++ (region->tail->rc.bottom == bottom) && \ ++ (region->tail->rc.right >= r->rc.left)) \ ++ { \ ++ if (region->tail->rc.right < r->rc.right) \ ++ { \ ++ region->tail->rc.right = r->rc.right; \ ++ } \ ++ } \ ++ else \ ++ { \ ++ NEWCLIPRECT(region, newcliprect); \ ++ newcliprect->rc.top = top; \ ++ newcliprect->rc.bottom = bottom; \ ++ newcliprect->rc.left = r->rc.left; \ ++ newcliprect->rc.right = r->rc.right; \ ++ } \ ++ r = r->next; ++ ++ while (r1 && r2 && (r1 != r1End) && (r2 != r2End)) ++ { ++ if (r1->rc.left < r2->rc.left) ++ { ++ MERGERECT(r1); ++ } ++ else ++ { ++ MERGERECT(r2); ++ } ++ } ++ ++ if (r1 && r1 != r1End) ++ { ++ do { ++ MERGERECT(r1); ++ } while (r1 && r1 != r1End); ++ } ++ else while (r2 && r2 != r2End) ++ { ++ MERGERECT(r2); ++ } ++} ++ ++ ++/*********************************************************************** ++ * UnionRegion ++ */ ++BOOL UnionRegion (CLIPRGN *dst, const CLIPRGN *src1, const CLIPRGN *src2) ++{ ++ /* checks all the simple cases */ ++ ++ /* ++ * Region 1 and 2 are the same or region 1 is empty ++ */ ++ if ( (src1 == src2) || (!(src1->head)) ) { ++ if (dst != src2) ++ CopyRegion (dst, src2); ++ return TRUE; ++ } ++ ++ /* ++ * if nothing to union (region 2 empty) ++ */ ++ if (!(src2->head)) { ++ if (dst != src1) ++ CopyRegion (dst, src1); ++ return TRUE; ++ } ++ ++ /* ++ * Region 1 completely subsumes region 2 ++ */ ++ if ((src1->head == src1->tail) && ++ (src1->rcBound.left <= src2->rcBound.left) && ++ (src1->rcBound.top <= src2->rcBound.top) && ++ (src1->rcBound.right >= src2->rcBound.right) && ++ (src1->rcBound.bottom >= src2->rcBound.bottom)) ++ { ++ if (dst != src1) ++ CopyRegion (dst, src1); ++ return TRUE; ++ } ++ ++ /* ++ * Region 2 completely subsumes region 1 ++ */ ++ if ((src2->head == src2->tail) && ++ (src2->rcBound.left <= src1->rcBound.left) && ++ (src2->rcBound.top <= src1->rcBound.top) && ++ (src2->rcBound.right >= src1->rcBound.right) && ++ (src2->rcBound.bottom >= src1->rcBound.bottom)) ++ { ++ if (dst != src2) ++ CopyRegion(dst, src2); ++ return TRUE; ++ } ++ ++ REGION_RegionOp (dst, src1, src2, REGION_UnionO, ++ REGION_UnionNonO, REGION_UnionNonO); ++ ++ REGION_SetExtents (dst); ++ dst->type = (dst->head) ? COMPLEXREGION : NULLREGION ; ++#if 0 ++ dst->rcBound.left = MIN (src1->rcBound.left, src2->rcBound.left); ++ dst->rcBound.top = MIN (src1->rcBound.top, src2->rcBound.top); ++ dst->rcBound.right = MAX (src1->rcBound.right, src2->rcBound.right); ++ dst->rcBound.bottom = MAX (src1->rcBound.bottom, src2->rcBound.bottom); ++ dbg_dumpRegion (dst); ++#endif ++ ++ return TRUE; ++} ++ ++/* Adds a rectangle to a region */ ++BOOL AddClipRect (PCLIPRGN region, const RECT *rect) ++{ ++ CLIPRGN my_region; ++ CLIPRECT my_cliprect; ++ ++ if (IsRectEmpty (rect)) ++ return FALSE; ++ ++ my_cliprect.rc = *rect; ++ my_cliprect.next = NULL; ++ my_cliprect.prev = NULL; ++ ++ my_region.type = SIMPLEREGION; ++ my_region.rcBound = *rect; ++ my_region.head = &my_cliprect; ++ my_region.tail = &my_cliprect; ++ my_region.heap = NULL; ++ ++ UnionRegion (region, region, &my_region); ++ ++ return TRUE; ++} ++EXPORT_SYMBOL(AddClipRect); ++ ++void dbg_dumpRegion (CLIPRGN* region) ++{ ++ CLIPRECT *cliprect; ++ ++ if (!(cliprect = region->head)) { ++ DBG_INFO ("region: %p is a null region.\n", region); ++ } ++ else { ++ DBG_INFO ("start of region: %p.\n", region); ++ DBG_INFO ("head of region: %p.\n", region->head); ++ DBG_INFO ("tail of region: %p.\n", region->tail); ++ DBG_INFO ("Bound of region: (%d, %d, %d, %d)\n", ++ region->rcBound.left, ++ region->rcBound.top, ++ region->rcBound.right, ++ region->rcBound.bottom); ++ while (cliprect) { ++ DBG_INFO ("cliprect %p: (%d, %d, %d, %d)\n", cliprect, ++ cliprect->rc.left, cliprect->rc.top, ++ cliprect->rc.right, ++ cliprect->rc.bottom); ++ ++ cliprect = cliprect->next; ++ } ++ DBG_INFO ("end of region: %p.\n", region); ++ } ++ ++} ++EXPORT_SYMBOL(dbg_dumpRegion); ++int region_substract_init(void) ++{ ++ cliprect_cache=kmem_cache_create("cliprect-cache", ++ sizeof(CLIPRECT),0,0,NULL); ++ if(!cliprect_cache){ ++ DBG_ERR("cliprect mem cache init fail\n"); ++ return -1; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(region_substract_init); ++int region_substract_deinit(void) ++{ ++ kmem_cache_destroy(cliprect_cache); ++ cliprect_cache=NULL; ++ return 0; ++} ++EXPORT_SYMBOL(region_substract_deinit); ++ +diff --git a/drivers/sstar/movedma/Kconfig b/drivers/sstar/movedma/Kconfig +new file mode 100755 +index 000000000000..71533ad1cd85 +--- /dev/null ++++ b/drivers/sstar/movedma/Kconfig +@@ -0,0 +1,5 @@ ++config MS_MOVE_DMA ++ bool "Mstar Move DMA driver" ++ default n ++ help ++ +diff --git a/drivers/sstar/movedma/Makefile b/drivers/sstar/movedma/Makefile +new file mode 100755 +index 000000000000..df0e9e44b380 +--- /dev/null ++++ b/drivers/sstar/movedma/Makefile +@@ -0,0 +1,11 @@ ++# ++# Makefile for the kernel BDMA drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-y = hal_movedma.o ++ +diff --git a/drivers/sstar/movedma/hal_movedma.c b/drivers/sstar/movedma/hal_movedma.c +new file mode 100755 +index 000000000000..2e58b6f4c3f8 +--- /dev/null ++++ b/drivers/sstar/movedma/hal_movedma.c +@@ -0,0 +1,291 @@ ++/* ++* hal_movedma.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++// Include files ++/*=============================================================*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "kernel_movedma.h" ++#include "hal_movedma.h" ++#include "cam_os_wrapper.h" ++ ++/*=============================================================*/ ++// Variable definition ++/*=============================================================*/ ++ ++volatile KeMoveDma_t* const g_ptKeMoveDma = (KeMoveDma_t *)IO_ADDRESS(BASE_REG_MOVDMA_PA); ++ ++static HalMoveDmaCBFunc *m_pfMdmaTxDoneCBFunc = NULL; ++static u32 m_u32MdmaTxDoneCBArgu = 0; ++static bool m_bMdmaInited = FALSE; ++static CamOsTsem_t m_stMdmaSemID; ++ ++/*=============================================================*/ ++// Function definition ++/*=============================================================*/ ++ ++static u32 _HalMoveDmaVA2Miu(void* virAddr) ++{ ++#if 1 ++ return (u32)virAddr; ++#else ++ unsigned int phyAddr = 0; ++ u32 MiuAddr = 0; ++ ++ phyAddr = (unsigned int)MsVA2PA(virAddr); ++ ++ MiuAddr = HalUtilPHY2MIUAddr(phyAddr); ++ ++ if (MiuAddr == 0xFFFFFFFF) { ++ CamOsPrintf("[DMA] WrongAddr[%x][%x][%x]\r\n", (int)virAddr, phyAddr, MiuAddr); ++ } ++ return MiuAddr; ++#endif ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalMoveDma_ISR ++// Description : ++//------------------------------------------------------------------------------ ++static irqreturn_t HalMoveDma_ISR(int irq, void* priv) ++{ ++ u16 intsrc = 0; ++ ++ intsrc = g_ptKeMoveDma->reg_dma_irq_final_status; ++ g_ptKeMoveDma->reg_dma_irq_clr = intsrc; ++ ++ if (intsrc & MOVEDMA_INT_MOVE0_DONE) { ++ ++ ++ CamOsTsemUp(&m_stMdmaSemID); ++ ++ //CamOsPrintf("[MDMA] Done\r\n"); ++ ++ if (m_pfMdmaTxDoneCBFunc) { ++ (*m_pfMdmaTxDoneCBFunc)(m_u32MdmaTxDoneCBArgu); ++ } ++ } ++ else ++ { ++ CamOsPrintf("[MDMA] Can't find irq status!!!!\r\n"); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalDmaGen_Initialize ++// Description : ++//------------------------------------------------------------------------------ ++HalMoveDmaErr_e HalMoveDma_Initialize(void) ++{ ++ if (!m_bMdmaInited) { ++ ++ struct device_node *dev_node = NULL; ++ irq_handler_t pfIrqHandler = NULL; ++ char compatible[16]; ++ int iIrqNum = 0; ++ ++ CamOsSnprintf(compatible, sizeof(compatible), "sstar,movdma"); ++ ++ dev_node = of_find_compatible_node(NULL, NULL, compatible); ++ ++ if (!dev_node) { ++ CamOsPrintf("[MDMA] of_find_compatible_node Fail\r\n"); ++ return HAL_MOVEDMA_ERR_PARAM; ++ } ++ ++ /* Register interrupt handler */ ++ iIrqNum = irq_of_parse_and_map(dev_node, 0); ++ ++ pfIrqHandler = HalMoveDma_ISR; ++ ++ if (0 != request_irq(iIrqNum, HalMoveDma_ISR, 0, "HalMoveDma_ISR", NULL)) { ++ CamOsPrintf("[MDMA] request_irq [%d] Fail\r\n", iIrqNum); ++ return HAL_MOVEDMA_ERR_PARAM; ++ } ++ else { ++ //CamOsPrintf("[MDMA] request_irq [%d] OK\r\n", iIrqNum); ++ } ++ ++ g_ptKeMoveDma->reg_dma_irq_mask = 0; ++ ++ /* Initial semaphore */ ++ CamOsTsemInit(&m_stMdmaSemID, 1); ++ ++ m_pfMdmaTxDoneCBFunc = NULL; ++ ++ m_bMdmaInited = 1; ++ } ++ ++ return HAL_MOVEDMA_NO_ERR; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : HalMoveDma_MoveData ++// Description : ++//------------------------------------------------------------------------------ ++HalMoveDmaErr_e HalMoveDma_MoveData(HalMoveDmaParam_t *ptMoveDmaParam) ++{ ++ CamOsRet_e eOSRet = CAM_OS_OK; ++ ++ eOSRet = CamOsTsemTimedDown(&m_stMdmaSemID, 3000); ++ ++ if (eOSRet == CAM_OS_TIMEOUT) ++ { ++ ++ CamOsPrintf("MoveDMA TsemTimedDown TimeOut\r\n"); ++ return HAL_MOVEDMA_POLLING_TIMEOUT; ++ } ++ ++ m_pfMdmaTxDoneCBFunc = ptMoveDmaParam->CallBackFunc; ++ m_u32MdmaTxDoneCBArgu = ptMoveDmaParam->CallBackArg; ++ ++ /* Reset DMA first */ ++ //g_ptKeMoveDma->reg_dma_mov_sw_rst = 1; ++ g_ptKeMoveDma->reg_dma_irq_mask = 0; ++ ++ /* Set LineOffset Attribute */ ++ if (ptMoveDmaParam->u32Mode == HAL_MOVEDMA_LINE_OFFSET) ++ { ++ if(ptMoveDmaParam->pstLineOfst) ++ { ++ g_ptKeMoveDma->reg_move0_offset_src_width_l = (U16)(ptMoveDmaParam->pstLineOfst->u32SrcWidth & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_offset_src_width_h = (U16)(ptMoveDmaParam->pstLineOfst->u32SrcWidth >> 16); ++ g_ptKeMoveDma->reg_move0_offset_src_offset_l = (U16)(ptMoveDmaParam->pstLineOfst->u32SrcOffset & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_offset_src_offset_h = (U16)(ptMoveDmaParam->pstLineOfst->u32SrcOffset >> 16); ++ g_ptKeMoveDma->reg_move0_offset_dest_width_l = (U16)(ptMoveDmaParam->pstLineOfst->u32DstWidth & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_offset_dest_width_h = (U16)(ptMoveDmaParam->pstLineOfst->u32DstWidth >> 16); ++ g_ptKeMoveDma->reg_move0_offset_dest_offset_l = (U16)(ptMoveDmaParam->pstLineOfst->u32DstOffset & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_offset_dest_offset_h = (U16)(ptMoveDmaParam->pstLineOfst->u32DstOffset >> 16); ++ g_ptKeMoveDma->reg_move0_offset_en = 1; ++ } ++ else ++ { ++ CamOsPrintf("pstLineOfst is null\r\n"); ++ g_ptKeMoveDma->reg_move0_offset_en = 1; ++ return HAL_MOVEDMA_ERR_PARAM; ++ } ++ } ++ else ++ { ++ g_ptKeMoveDma->reg_move0_offset_en = 0; ++ } ++ ++ g_ptKeMoveDma->reg_move0_src_start_addr_l = (U16)(_HalMoveDmaVA2Miu((void*)ptMoveDmaParam->u32SrcAddr) & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_src_start_addr_h = (U16)(_HalMoveDmaVA2Miu((void*)ptMoveDmaParam->u32SrcAddr) >> 16); ++ g_ptKeMoveDma->reg_move0_dest_start_addr_l = (U16)(_HalMoveDmaVA2Miu((void*)ptMoveDmaParam->u32DstAddr) & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_dest_start_addr_h = (U16)(_HalMoveDmaVA2Miu((void*)ptMoveDmaParam->u32DstAddr) >> 16); ++ ++ if (ptMoveDmaParam->u32Mode == HAL_MOVEDMA_MSPI) ++ { ++ if(ptMoveDmaParam->pstMspist) ++ { ++ if(ptMoveDmaParam->pstMspist->u32Direction < HAL_MOVEDMA_RW_MAX) ++ { ++ g_ptKeMoveDma->reg_dma_spi_rw = ptMoveDmaParam->pstMspist->u32Direction; ++ } ++ else ++ { ++ CamOsPrintf("rw para is err\r\n"); ++ return HAL_MOVEDMA_ERR_PARAM; ++ } ++ ++ if(g_ptKeMoveDma->reg_spi_device_select < HAL_MOVEDMA_MSPI_MAX) ++ { ++ g_ptKeMoveDma->reg_spi_device_select = ptMoveDmaParam->pstMspist->u32DeviceSelect; //0 select mspi0 , 1 select mspi1 ++ } ++ else ++ { ++ CamOsPrintf("mspi channel is unsupported\r\n"); ++ return HAL_MOVEDMA_ERR_PARAM; ++ } ++ g_ptKeMoveDma->reg_dma_spi_device_mode = 1; // 1 to enable dma device mode ++ ++ if(ptMoveDmaParam->pstMspist->u32Direction == HAL_MOVEDMA_RD) ++ { ++ g_ptKeMoveDma->reg_move0_src_start_addr_l = 0; ++ g_ptKeMoveDma->reg_move0_src_start_addr_h = 0; ++ } ++ else ++ { ++ g_ptKeMoveDma->reg_move0_dest_start_addr_l = 0; ++ g_ptKeMoveDma->reg_move0_dest_start_addr_h = 0; ++ } ++ } ++ else ++ { ++ CamOsPrintf("pstMspist is null\r\n"); ++ g_ptKeMoveDma->reg_dma_spi_device_mode = 0; // 1 to enable dma device mode ++ return HAL_MOVEDMA_ERR_PARAM; ++ } ++ } ++ else ++ { ++ g_ptKeMoveDma->reg_dma_spi_device_mode = 0; // 1 to enable dma device mode ++ } ++ ++ g_ptKeMoveDma->reg_move0_total_byte_cnt_l = (U16)(ptMoveDmaParam->u32Count & 0xFFFF); ++ g_ptKeMoveDma->reg_move0_total_byte_cnt_h = (U16)(ptMoveDmaParam->u32Count >> 16); ++ ++ g_ptKeMoveDma->reg_dma_move0_miu_sel_en = 1; ++ g_ptKeMoveDma->reg_dma_move0_src_miu_sel = (ptMoveDmaParam->u32SrcMiuSel) ? (REG_DMA_MOVE0_SEL_MIU1) : (REG_DMA_MOVE0_SEL_MIU0); ++ g_ptKeMoveDma->reg_dma_move0_dst_miu_sel = (ptMoveDmaParam->u32DstMiuSel) ? (REG_DMA_MOVE0_SEL_MIU1) : (REG_DMA_MOVE0_SEL_MIU0); ++ ++#if 0 ++ CamOsPrintf("==========================================\r\n"); ++ CamOsPrintf("g_ptKeMoveDma %p\r\n", g_ptKeMoveDma); ++ CamOsPrintf("reg_move0_offset_en %x\r\n", g_ptKeMoveDma->reg_move0_offset_en); ++ CamOsPrintf("reg_move0_src_start_addr_l %x\r\n", g_ptKeMoveDma->reg_move0_src_start_addr_l); ++ CamOsPrintf("reg_move0_src_start_addr_h %x\r\n", g_ptKeMoveDma->reg_move0_src_start_addr_h); ++ CamOsPrintf("reg_move0_dest_start_addr_l %x\r\n", g_ptKeMoveDma->reg_move0_dest_start_addr_l); ++ CamOsPrintf("reg_move0_dest_start_addr_h %x\r\n", g_ptKeMoveDma->reg_move0_dest_start_addr_h); ++ CamOsPrintf("reg_move0_total_byte_cnt_l %x\r\n", g_ptKeMoveDma->reg_move0_total_byte_cnt_l); ++ CamOsPrintf("reg_move0_total_byte_cnt_h %x\r\n", g_ptKeMoveDma->reg_move0_total_byte_cnt_h); ++ CamOsPrintf("reg_move0_offset_src_width_l %x\r\n", g_ptKeMoveDma->reg_move0_offset_src_width_l); ++ CamOsPrintf("reg_move0_offset_src_width_h %x\r\n", g_ptKeMoveDma->reg_move0_offset_src_width_h); ++ CamOsPrintf("reg_move0_offset_src_offset_l %x\r\n", g_ptKeMoveDma->reg_move0_offset_src_offset_l); ++ CamOsPrintf("reg_move0_offset_src_offset_h %x\r\n", g_ptKeMoveDma->reg_move0_offset_src_offset_h); ++ CamOsPrintf("reg_move0_offset_dest_width_l %x\r\n", g_ptKeMoveDma->reg_move0_offset_dest_width_l); ++ CamOsPrintf("reg_move0_offset_dest_width_h %x\r\n", g_ptKeMoveDma->reg_move0_offset_dest_width_h); ++ CamOsPrintf("reg_move0_offset_dest_offset_l %x\r\n", g_ptKeMoveDma->reg_move0_offset_dest_offset_l); ++ CamOsPrintf("reg_move0_offset_dest_offset_h %x\r\n", g_ptKeMoveDma->reg_move0_offset_dest_offset_h); ++ CamOsPrintf("reg_dma_move0_left_byte_l %x\r\n", g_ptKeMoveDma->reg_dma_move0_left_byte_l); ++ CamOsPrintf("reg_dma_move0_left_byte_h %x\r\n", g_ptKeMoveDma->reg_dma_move0_left_byte_h); ++ CamOsPrintf("reg_dma_irq_mask %x\r\n", g_ptKeMoveDma->reg_dma_irq_mask); ++ CamOsPrintf("reg_dma_irq_final_status %x\r\n", g_ptKeMoveDma->reg_dma_irq_final_status); ++ CamOsPrintf("reg_dma_move0_miu_sel_en %x\r\n", g_ptKeMoveDma->reg_dma_move0_miu_sel_en); ++ CamOsPrintf("reg_dma_move0_src_miu_sel %x\r\n", g_ptKeMoveDma->reg_dma_move0_src_miu_sel); ++ CamOsPrintf("reg_dma_move0_dst_miu_sel %x\r\n", g_ptKeMoveDma->reg_dma_move0_dst_miu_sel); ++ //0x50 ++ CamOsPrintf("reg_dma_rw [%p]=%x\r\n", &g_ptKeMoveDma->reg_50, g_ptKeMoveDma->reg_dma_rw); ++ CamOsPrintf("reg_dma_device_mode %x\r\n", g_ptKeMoveDma->reg_dma_device_mode); ++ CamOsPrintf("reg_device_select %x\r\n", g_ptKeMoveDma->reg_device_select); ++#endif ++ ++ g_ptKeMoveDma->reg_dma_move_en = 1; ++ ++ return HAL_MOVEDMA_NO_ERR; ++} ++ ++EXPORT_SYMBOL(HalMoveDma_MoveData); //for unittest ++ +diff --git a/drivers/sstar/movedma/hal_movedma.h b/drivers/sstar/movedma/hal_movedma.h +new file mode 100755 +index 000000000000..7d4e807e9776 +--- /dev/null ++++ b/drivers/sstar/movedma/hal_movedma.h +@@ -0,0 +1,108 @@ ++/* ++* hal_movedma.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __HAL_MOVE_DMA_H__ ++#define __HAL_MOVE_DMA_H__ ++ ++/*=============================================================*/ ++// Include files ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Enumeration definition ++/*=============================================================*/ ++ ++#define REG_DMA_MOVE0_SEL_MIU0 (0) ++#define REG_DMA_MOVE0_SEL_MIU1 (1) ++ ++typedef enum ++{ ++ HAL_MOVEDMA_0 = 0, ++ HAL_MOVEDMA_MAX ++} HalMoveDmaId_e; ++ ++typedef enum ++{ ++ HAL_MOVEDMA_MSPI0 = 0, ++ HAL_MOVEDMA_MSPI1, ++ HAL_MOVEDMA_MSPI_MAX ++} HalMoveDmaMspiCh_e; ++ ++typedef enum ++{ ++ HAL_MOVEDMA_WR = 0, ++ HAL_MOVEDMA_RD, ++ HAL_MOVEDMA_RW_MAX ++} HalMoveDmaRw_e; ++ ++ ++typedef enum ++{ ++ HAL_MOVEDMA_NO_ERR = 0, ++ HAL_MOVEDMA_ERR_PARAM = -1, ++ HAL_MOVEDMA_POLLING_TIMEOUT = -2 ++} HalMoveDmaErr_e; ++ ++typedef enum ++{ ++ HAL_MOVEDMA_LINEAR = 0, ++ HAL_MOVEDMA_LINE_OFFSET = 1, ++ HAL_MOVEDMA_MSPI = 2, ++} HalMoveDmaMode_e; ++ ++/*=============================================================*/ ++// Structure definition ++/*=============================================================*/ ++ ++typedef void HalMoveDmaCBFunc(u32 argu); ++ ++typedef struct { ++ u32 u32SrcWidth; ///< Width of source ++ u32 u32SrcOffset; ///< Line-to-line offset of source ++ u32 u32DstWidth; ///< Width of destination ++ u32 u32DstOffset; ///< Line-to-line offset of destination ++} HalMoveDmaLineOfst_t; ++ ++typedef struct { ++ u32 u32Direction; // 0 for dma write to device, 1 for dma read from device ++ u32 u32DeviceSelect; // 0 select mspi0, 1 select mspi1 ++} HalMoveDmaMspi_t; ++ ++ ++typedef struct { ++ u32 u32Mode; // be used to HalMoveDmaMode_e ++ u32 u32SrcAddr; ++ u32 u32SrcMiuSel; ++ u32 u32DstAddr; ++ u32 u32DstMiuSel; ++ u32 u32Count; ++ HalMoveDmaCBFunc *CallBackFunc; ++ u32 CallBackArg; ++ u32 bEnLineOfst; ++ HalMoveDmaLineOfst_t *pstLineOfst; ++ HalMoveDmaMspi_t *pstMspist; ++} HalMoveDmaParam_t; ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++HalMoveDmaErr_e HalMoveDma_Initialize(void); ++HalMoveDmaErr_e HalMoveDma_MoveData(HalMoveDmaParam_t *ptMoveDmaParam); ++ ++#endif // __HAL_MOVE_DMA_H__ ++ +diff --git a/drivers/sstar/movedma/kernel_movedma.h b/drivers/sstar/movedma/kernel_movedma.h +new file mode 100755 +index 000000000000..cc05488ddd9e +--- /dev/null ++++ b/drivers/sstar/movedma/kernel_movedma.h +@@ -0,0 +1,247 @@ ++/* ++* kernel_movedma.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++/*************************************************************************** ++ * kernel_movedma.h ++ *-------------------------------------------------------------------------- ++ * Scope: General DMA related definitions ++ * ++ ****************************************************************************/ ++ ++#ifndef __KERNEL_MOVEDMA_H__ ++#define __KERNEL_MOVEDMA_H__ ++ ++/****************************************************************************/ ++/* General DMA registers */ ++/****************************************************************************/ ++ ++typedef struct KeMoveDma_s ++{ ++ // 0x00 ++ u32 reg_dma_move_en :1; ++ u32 :31; ++ // 0x01 ++ u32 reg_move0_offset_en :1; ++ u32 :31; ++ // 0x02 ++ u32 reg_dma_move0_en_status :1; // [RO] ++ u32 :31; ++ // 0x03 ++ u32 reg_move0_src_start_addr_l :16; ++ u32 :16; ++ // 0x04 ++ u32 reg_move0_src_start_addr_h :16; ++ u32 :16; ++ // 0x05 ++ u32 reg_move0_dest_start_addr_l :16; ++ u32 :16; ++ // 0x06 ++ u32 reg_move0_dest_start_addr_h :16; ++ u32 :16; ++ // 0x07 ++ u32 reg_move0_total_byte_cnt_l :16; ++ u32 :16; ++ // 0x08 ++ u32 reg_move0_total_byte_cnt_h :12; ++ u32 :20; ++ // 0x09 ++ u32 reg_move0_offset_src_width_l :16; ++ u32 :16; ++ // 0x0A ++ u32 reg_move0_offset_src_width_h :12; ++ u32 :20; ++ // 0x0B ++ u32 reg_move0_offset_src_offset_l :16; ++ u32 :16; ++ // 0x0C ++ u32 reg_move0_offset_src_offset_h :12; ++ u32 :20; ++ // 0x0D ++ u32 reg_move0_offset_dest_width_l :16; ++ u32 :16; ++ // 0x0E ++ u32 reg_move0_offset_dest_width_h :12; ++ u32 :20; ++ // 0x0F ++ u32 reg_move0_offset_dest_offset_l :16; ++ u32 :16; ++ // 0x10 ++ u32 reg_move0_offset_dest_offset_h :12; ++ u32 :20; ++ // 0x11 ++ u32 reg_dma_move0_left_byte_l :16; // [RO] ++ u32 :16; ++ // 0x12 ++ u32 reg_dma_move0_left_byte_h :13; // [RO] ++ u32 :19; ++ // 0x13 ++ u32 :32; ++ // 0x14 ++ u32 :32; ++ // 0x15 ++ u32 :32; ++ // 0x16 ++ u32 :32; ++ // 0x17 ++ u32 :32; ++ // 0x18 ++ u32 :32; ++ // 0x19 ++ u32 :32; ++ // 0x1A ++ u32 :32; ++ // 0x1B ++ u32 :32; ++ // 0x1C ++ u32 :32; ++ // 0x1D ++ u32 :32; ++ // 0x1E ++ u32 :32; ++ // 0x1F ++ u32 :32; ++ // 0x20 ++ u32 :32; ++ // 0x21 ++ u32 :32; ++ // 0x22 ++ u32 :32; ++ // 0x23 ++ u32 reg_dummy :16; ++ u32 :16; ++ // 0x24 ++ u32 reg_dma_mov_sw_rst :1; // [WO] ++ u32 :31; ++ // 0x25 ++ u32 reg_dma02mi_priority_mask :1; ++ u32 :31; ++ // 0x26 ++ u32 reg_dma_irq_mask :1; ++ u32 :31; ++ // 0x27 ++ u32 reg_dma_irq_force :1; ++ u32 :31; ++ // 0x28 ++ u32 reg_dma_irq_clr :1; ++ u32 :31; ++ // 0x29 ++ u32 reg_dma_irq_select :1; ++ u32 :31; ++ // 0x2A ++ u32 reg_dma_irq_final_status :1; // [RO] ++ u32 :31; ++ // 0x2B ++ u32 reg_dma_irq_raw_status :1; // [RO] ++ u32 :31; ++ #define MOVEDMA_INT_MOVE0_DONE (0x01) ++ // 0x2C ++ u32 reg_dma_probe_sel :8; ++ u32 :24; ++ // 0x2D ++ u32 reg_dma_probe_l :16; // [RO] ++ u32 :16; ++ // 0x2E ++ u32 reg_dma_probe_h :8; // [RO] ++ u32 :24; ++ // 0x2F ++ u32 reg_dma_bist_fail_rd :1; // [RO] ++ u32 :31; ++ // 0x30 ++ u32 reg_dma_move0_miu_sel_en :1; ++ u32 reg_dma_move0_src_miu_sel :1; ++ u32 reg_dma_move0_dst_miu_sel :1; ++ u32 :29; ++ // 0x31 ++ u32 :32; ++ // 0x32 ++ u32 :32; ++ // 0x33 ++ u32 :32; ++ // 0x34 ++ u32 :32; ++ // 0x35 ++ u32 :32; ++ // 0x36 ++ u32 :32; ++ // 0x37 ++ u32 :32; ++ // 0x38 ++ u32 :32; ++ // 0x39 ++ u32 :32; ++ // 0x3A ++ u32 :32; ++ // 0x3B ++ u32 :32; ++ // 0x3C ++ u32 :32; ++ // 0x3D ++ u32 :32; ++ // 0x3E ++ u32 :32; ++ // 0x3F ++ u32 :32; ++ // 0x40 ++ u32 reg_dma_cmdq_irq_mask :1; ++ u32 :31; ++ // 0x41 ++ u32 reg_dma_cmdq_irq_force :1; ++ u32 :31; ++ // 0x42 ++ u32 reg_dma_cmdq_irq_clr :1; ++ u32 :31; ++ // 0x43 ++ u32 reg_dma_cmdq_irq_select :1; ++ u32 :31; ++ // 0x44 ++ u32 reg_dma_cmdq_irq_final_status :1; // [RO] ++ u32 :31; ++ // 0x45 ++ u32 reg_dma_cmdq_irq_raw_status :1; // [RO] ++ u32 :31; ++ // 0x46 ++ u32 :32; ++ // 0x47 ++ u32 :32; ++ // 0x48 ++ u32 :32; ++ // 0x49 ++ u32 :32; ++ // 0x4A ++ u32 :32; ++ // 0x4B ++ u32 :32; ++ // 0x4C ++ u32 :32; ++ // 0x4D ++ u32 :32; ++ // 0x4E ++ u32 :32; ++ // 0x4F ++ u32 :32; ++ // 0x50 ++ u32 reg_dma_spi_rw :1; ++ u32 :31; ++ // 0x51 ++ u32 reg_dma_spi_device_mode :1; ++ u32 :31; ++ // 0x52 ++ u32 reg_spi_device_select :1; ++ u32 :31; ++} KeMoveDma_t; ++ ++#endif // __KERNEL_MOVEDMA_H__ ++ +diff --git a/drivers/sstar/mspi/Kconfig b/drivers/sstar/mspi/Kconfig +new file mode 100755 +index 000000000000..61955d88515f +--- /dev/null ++++ b/drivers/sstar/mspi/Kconfig +@@ -0,0 +1,12 @@ ++config SS_MSPI ++ tristate "SStar MSPI driver" ++ default n ++ help ++ Enable support for SPI master driver ++ ++config SPI_INT_CALL ++ bool "Support SPI INT READ/WRITE" ++ default n ++ depends on SS_MSPI ++ help ++ Support SPI INT READ/WRITE +diff --git a/drivers/sstar/mspi/Makefile b/drivers/sstar/mspi/Makefile +new file mode 100755 +index 000000000000..8a26a63dd07a +--- /dev/null ++++ b/drivers/sstar/mspi/Makefile +@@ -0,0 +1,14 @@ ++# ++# Makefile for kernel SPI drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/movedma ++EXTRA_CFLAGS += -Idrivers/sstar/mspi/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_SS_MSPI) += sstar_mspi.o ++sstar_mspi-objs := drv_mspi.o $(CONFIG_SSTAR_CHIP_NAME)/hal_mspi.o ++ +diff --git a/drivers/sstar/mspi/drv_mspi.c b/drivers/sstar/mspi/drv_mspi.c +new file mode 100755 +index 000000000000..dd6f31860610 +--- /dev/null ++++ b/drivers/sstar/mspi/drv_mspi.c +@@ -0,0 +1,1078 @@ ++/* ++* drv_mspi.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_gpio.h" ++ ++#include ++#include ++#include ++#include ++ ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk("[MSPI] : " args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++#define mspi_errmsg(fmt, ...) printk(KERN_ERR "[MSPI] error : " fmt, ##__VA_ARGS__) ++#define mspi_warnmsg(fmt, ...) printk(KERN_ERR "[MSPI] warning : " fmt, ##__VA_ARGS__) ++ ++#define SSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH ) ++ ++u8 HAL_MSPI_SET_FRAMECFG(struct mspi_hal *mspi, int bits_per_word) __attribute__((weak)); ++ ++struct mspi_clk ++{ ++ u8 clk_src; ++ u8 clk_div; ++ u32 clk_rate; ++}; ++ ++struct mspi_clk_tbl ++{ ++ u32 *clk_src_tbl; ++ u32 clk_src_tbl_sz; ++ u32 *clk_div_tbl; ++ u32 clk_div_tbl_sz; ++ u32 clk_cfg_tbl_sz; ++ struct mspi_clk *clk_cfg_tbl; ++}; ++ ++struct sstar_mspi ++{ ++ int irq_num; ++ int len; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ ++ u16 mode; ++ s16 bus_num; ++ u32 use_dma; ++ u32 xfer_dma; ++ u32 bits_per_word; ++ u32 max_speed_hz; ++ ++ u32 word_size; ++ ++ #ifdef CONFIG_CAM_CLK ++ void **camclk; ++ #endif ++ ++ struct mspi_hal hal; ++ struct platform_device *pdev; ++ struct mspi_clk_tbl mspi_clk_tbl; ++}; ++ ++static const u32 sstar_spi_clk_div_tbl[] = MSPI_CLK_DIV_VAL; ++ ++#ifndef CONFIG_SPI_INT_CALL ++static irqreturn_t sstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *sstar_master = dev_id; ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(sstar_master); ++ int uDoneFlag = 0; ++ ++ uDoneFlag = HAL_MSPI_CheckDone(&sstar_spimst->hal); ++ ++ if(uDoneFlag == 1) ++ { ++ HAL_MSPI_ClearDone(&sstar_spimst->hal); ++ mspi_dbgmsg("<<<<<<<<<<<<< SPI_%d Done >>>>>>>>>>>>>\n", sstar_spimst->bus_num); ++ complete(&sstar_spimst->hal.done); ++ } ++ return IRQ_HANDLED; ++} ++#endif ++ ++static void sstar_spi_clk_tbl_init(struct mspi_clk_tbl *clk_tbl) ++{ ++ u8 i = 0; ++ u8 j = 0; ++ u32 clk =0; ++ struct mspi_clk temp; ++ ++ memset(&temp,0,sizeof(struct mspi_clk)); ++ memset(clk_tbl->clk_cfg_tbl,0,sizeof(struct mspi_clk)*clk_tbl->clk_cfg_tbl_sz); ++ ++ for(i = 0; i < clk_tbl->clk_src_tbl_sz; i++) ++ { ++ for(j = 0; j < clk_tbl->clk_div_tbl_sz; j++) ++ { ++ clk = clk_tbl->clk_src_tbl[i]; ++ clk_tbl->clk_cfg_tbl[j+clk_tbl->clk_div_tbl_sz*i].clk_src = i; ++ clk_tbl->clk_cfg_tbl[j+clk_tbl->clk_div_tbl_sz*i].clk_div = j ; ++ clk_tbl->clk_cfg_tbl[j+clk_tbl->clk_div_tbl_sz*i].clk_rate = clk/clk_tbl->clk_div_tbl[j]; ++ } ++ } ++ ++ for(i = 0; i < clk_tbl->clk_cfg_tbl_sz; i++) ++ { ++ for(j = i ; j < clk_tbl->clk_cfg_tbl_sz; j++) ++ { ++ if(clk_tbl->clk_cfg_tbl[i].clk_rate > clk_tbl->clk_cfg_tbl[j].clk_rate) ++ { ++ memcpy(&temp,&clk_tbl->clk_cfg_tbl[i],sizeof(struct mspi_clk)); ++ ++ memcpy(&clk_tbl->clk_cfg_tbl[i],&clk_tbl->clk_cfg_tbl[j],sizeof(struct mspi_clk)); ++ ++ memcpy(&clk_tbl->clk_cfg_tbl[j],&temp,sizeof(struct mspi_clk)); ++ } ++ } ++ } ++ ++ for (i = 0; i < clk_tbl->clk_cfg_tbl_sz; i++) ++ { ++ mspi_dbgmsg("clk_cfg_tbl[%d].clk_cfg = %d\n", i, clk_tbl->clk_cfg_tbl[i].clk_src); ++ mspi_dbgmsg("clk_cfg_tbl[%d].clk_div = %d\n", i, clk_tbl->clk_cfg_tbl[i].clk_div); ++ mspi_dbgmsg("clk_cfg_tbl[%d].clk_rate = %d\n", i, clk_tbl->clk_cfg_tbl[i].clk_rate); ++ } ++ ++} ++ ++static u32 sstar_spi_set_clock(struct sstar_mspi *mspi, u32 clock) ++{ ++ u8 i = 0; ++#ifdef CONFIG_CAM_CLK ++ u8 cam_on; ++ CAMCLK_Set_Attribute stSetCfg; ++#else ++ struct clk *mspi_clock; ++#endif ++ struct mspi_clk_tbl *clk_tbl = &mspi->mspi_clk_tbl; ++ ++ for(i = 0; i < clk_tbl->clk_cfg_tbl_sz; i++) ++ { ++ if(clock <= clk_tbl->clk_cfg_tbl[i].clk_rate) ++ { ++ break; ++ } ++ } ++ if (clk_tbl->clk_cfg_tbl_sz == i) ++ { ++ i--; ++ } ++ //match Closer clk ++ if ((i) && ((clock - clk_tbl->clk_cfg_tbl[i-1].clk_rate)<(clk_tbl->clk_cfg_tbl[i].clk_rate - clock))) ++ { ++ i -= 1; ++ } ++ ++#ifdef CONFIG_CAM_CLK ++ if(CamClkGetOnOff(mspi->camclk[0], &cam_on)) ++ { ++ mspi_errmsg("cam clk 0 on get fail\n"); ++ return 0; ++ } ++ if(!cam_on) ++ { ++ if(CamClkSetOnOff(mspi->camclk[0], 1)) ++ { ++ mspi_errmsg("cam clk 0 on set fail\n"); ++ return 0; ++ } ++ } ++ CAMCLK_SETRATE_ROUNDUP(stSetCfg,clk_tbl->clk_src_tbl[clk_tbl->clk_cfg_tbl[i].clk_src]); ++ if(CamClkAttrSet(mspi->camclk[0],&stSetCfg)) ++ { ++ mspi_errmsg("cam clk 0 rate set fail\n"); ++ return 0; ++ } ++#else ++ mspi_clock = of_clk_get(mspi->pdev->dev.of_node, 0); ++ if (IS_ERR(mspi_clock)) ++ { ++ mspi_errmsg("get clock fail 0\n"); ++ return 0; ++ } ++ if(!__clk_is_enabled(mspi_clock)) ++ { ++ clk_prepare_enable(mspi_clock); ++ } ++ clk_set_rate(mspi_clock, clk_tbl->clk_src_tbl[clk_tbl->clk_cfg_tbl[i].clk_src]); ++ clk_put(mspi_clock); ++#endif ++ ++ HAL_MSPI_SetDivClk(&mspi->hal, clk_tbl->clk_cfg_tbl[i].clk_div); ++ ++ mspi_dbgmsg("calc config : %04d\n", clk_tbl->clk_cfg_tbl[i].clk_src); ++ mspi_dbgmsg("calc div : %04d\n", clk_tbl->clk_cfg_tbl[i].clk_div); ++ mspi_dbgmsg("calc rate : %d\n", clk_tbl->clk_cfg_tbl[i].clk_rate); ++ ++ return clk_tbl->clk_cfg_tbl[i].clk_rate; ++} ++ ++static int sstar_spi_select_dma_clk(u8 u8Channel, struct sstar_mspi *mspi) ++{ ++#ifdef CONFIG_CAM_CLK ++ u8 cam_on; ++ CAMCLK_Get_Attribute stGetCfg; ++ CAMCLK_Set_Attribute stSetCfg; ++#else ++ u32 num_parents; ++ struct clk *movdma_clock; ++ struct clk_hw *movdma_hw; ++ struct clk_hw *parent_hw; ++#endif ++ ++#ifdef CONFIG_CAM_CLK ++ if(CamClkGetOnOff(mspi->camclk[1], &cam_on)) ++ { ++ mspi_errmsg("cam clk 1 on get fail\n"); ++ return -EIO; ++ } ++ if(!cam_on) ++ { ++ if(CamClkSetOnOff(mspi->camclk[1], 1)) ++ { ++ mspi_errmsg("cam clk 1 on set fail\n"); ++ return -EIO; ++ } ++ } ++ if(CamClkAttrGet(mspi->camclk[1], &stGetCfg)) ++ { ++ mspi_errmsg("cam clk 1 att get fail\n"); ++ return -ENOENT; ++ } ++ CAMCLK_SETPARENT(stSetCfg, stGetCfg.u32Parent[u8Channel]); ++#else ++ num_parents = of_clk_get_parent_count(mspi->pdev->dev.of_node); ++ if(num_parents < 2) ++ { ++ mspi_errmsg("can't find mspi clocks property %d\n", num_parents); ++ return -EIO; ++ } ++ movdma_clock = of_clk_get(mspi->pdev->dev.of_node, 1); ++ if (IS_ERR(movdma_clock)) ++ { ++ mspi_errmsg("get clock fail 1\n"); ++ return -EIO; ++ } ++ if(!__clk_is_enabled(movdma_clock)) ++ { ++ clk_prepare_enable(movdma_clock); ++ } ++ movdma_hw = __clk_get_hw(movdma_clock); ++ parent_hw = clk_hw_get_parent_by_index(movdma_hw, u8Channel); ++ clk_set_parent(movdma_clock, parent_hw->clk); ++ clk_put(movdma_clock); ++#endif ++ ++ return 0; ++} ++ ++static int sstar_spi_setup(struct spi_device *spi) ++{ ++ int err = 0; ++ u32 new_clock = 0; ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(spi->master); ++ ++ mspi_dbgmsg("setup channel:%d\n", sstar_spimst->bus_num); ++ if(sstar_spimst->mode != spi->mode) ++ { ++ sstar_spimst->mode = spi->mode; ++ ++ err = HAL_MSPI_SetMode(&sstar_spimst->hal, sstar_spimst->mode & (SPI_CPHA | SPI_CPOL)); ++ if(err) ++ { ++ return -EIO; ++ } ++ ++ err = HAL_MSPI_SetLSB(&sstar_spimst->hal,(sstar_spimst->mode & SPI_LSB_FIRST)>>3); ++ if(err) ++ { ++ return -EIO; ++ } ++ ++ HAL_MSPI_ChipSelect(&sstar_spimst->hal,((spi->mode & SPI_CS_HIGH) == SPI_CS_HIGH),0); ++ ++ mspi_dbgmsg("setup mode:%d\n", sstar_spimst->mode); ++ } ++ ++ if(sstar_spimst->max_speed_hz != spi->max_speed_hz) ++ { ++ new_clock = sstar_spi_set_clock(sstar_spimst, spi->max_speed_hz); ++ if(new_clock > 0) ++ { ++ spi->max_speed_hz = new_clock; ++ sstar_spimst->max_speed_hz = spi->max_speed_hz; ++ } ++ else ++ { ++ return -EIO; ++ } ++ ++ mspi_dbgmsg("setup speed : %d\n", sstar_spimst->max_speed_hz); ++ } ++ ++ if(sstar_spimst->bits_per_word != spi->bits_per_word) ++ { ++ sstar_spimst->xfer_dma = (spi->bits_per_word % 8 ==0) ? sstar_spimst->use_dma : false; ++ sstar_spimst->bits_per_word = spi->bits_per_word; ++ sstar_spimst->hal.bits_per_word = spi->bits_per_word; ++ if (spi->bits_per_word > MSPI_MAX_SUPPORT_BITS) ++ { ++ return -EINVAL; ++ } ++ else if (spi->bits_per_word > 8) ++ { ++ sstar_spimst->word_size = 2; ++ } ++ else ++ { ++ sstar_spimst->word_size = 1; ++ } ++ HAL_MSPI_SET_FRAMECFG(&sstar_spimst->hal, spi->bits_per_word); ++ ++ mspi_dbgmsg("setup bits : %d\n", sstar_spimst->bits_per_word); ++ } ++ return 0; ++} ++ ++static int sstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ int err = 0; ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(spi->master); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ sstar_spimst->tx_buf = tfr->tx_buf; ++ sstar_spimst->rx_buf = tfr->rx_buf; ++ sstar_spimst->len = tfr->len; ++ ++ HAL_MSPI_ChipSelect(&sstar_spimst->hal,!((spi->mode & SPI_CS_HIGH) == SPI_CS_HIGH),0); ++ ++ if(sstar_spimst->use_dma) ++ { ++ err = sstar_spi_select_dma_clk(spi->master->bus_num, sstar_spimst); ++ if(err) ++ { ++ return -EIO; ++ } ++ } ++ ++ /* ++ Document\spi\spi-summary: ++ which I/O buffers are used ... each spi_transfer wraps a ++ buffer for each transfer direction, supporting full duplex ++ (two pointers, maybe the same one in both cases) and half ++ duplex (one pointer is NULL) transfers; ++ */ ++ ++ if(sstar_spimst->tx_buf != NULL && sstar_spimst->rx_buf != NULL) ++ { ++ HAL_MSPI_FullDuplex(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->rx_buf, (u8 *)sstar_spimst->tx_buf, (u16)sstar_spimst->len); ++ } ++ else if(sstar_spimst->tx_buf != NULL) ++ { ++ if(sstar_spimst->xfer_dma) ++ { ++ err = HAL_MSPI_DMA_Write(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->tx_buf, (u32)sstar_spimst->len); ++ if(err) ++ { ++ return -EIO; ++ } ++ } ++ else ++ { ++ err = HAL_MSPI_Write(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->tx_buf,(u32)sstar_spimst->len); ++ if(err) ++ { ++ return -EIO; ++ } ++ } ++ } ++ else if(sstar_spimst->rx_buf != NULL) ++ { ++ if(sstar_spimst->xfer_dma) ++ { ++ err = HAL_MSPI_DMA_Read(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->rx_buf, (u32)sstar_spimst->len); ++ if(err) ++ { ++ return -EIO; ++ } ++ } ++ else ++ { ++ err = HAL_MSPI_Read(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->rx_buf, (u32)sstar_spimst->len); ++ if(err) ++ { ++ return -EIO; ++ } ++ } ++ } ++ ++ return err; ++} ++ ++static int sstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(spi->master); ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change) ++ { ++ /* Clear TA flag */ ++ HAL_MSPI_ChipSelect(&sstar_spimst->hal,((spi->mode & SPI_CS_HIGH) == SPI_CS_HIGH),0); ++ } ++ return 0; ++} ++ ++static int sstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ int err = 0; ++ bool cs_change; ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(master); ++ ++ //mspi_dbgmsg("[sstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) ++ { ++ if (tfr->len % sstar_spimst->word_size != 0) { ++ mspi_dbgmsg("invalid transfer len\n"); ++ goto out; ++ } ++ ++ err = sstar_spi_start_transfer(spi, tfr); ++ if (err) ++ { ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = sstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err) ++ { ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ mesg->actual_length += sstar_spimst->len; ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++#if IS_ENABLED(CONFIG_SPI_SPIDEV) ++static struct spi_board_info sstar_info = ++{ ++ .modalias = "spidev", ++}; ++#endif ++ ++static int sstar_spi_probe(struct platform_device *pdev) ++{ ++ int i; ++ int err; ++ u32 use_dma; ++ u32 pad_ctrl; ++ u32 irq_num; ++ u32 mspi_group; ++ char irq_name[20]; ++ u8 num_parents; ++#ifdef CONFIG_CAM_CLK ++ char cam_name[20]; ++ u32 mspi_clkid; ++ u32 movedma_clkid; ++ CAMCLK_Get_Attribute stGetCfg; ++#else ++ struct clk *mspi_clock; ++ struct clk_hw *parent_hw; ++#endif ++ void __iomem *mspi_base; ++ struct sstar_mspi *sstar_spimst; ++ struct spi_master *sstar_master; ++ struct resource *mspi_resource; ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ err = of_property_read_u32(pdev->dev.of_node, "mspi-group", &mspi_group); ++ if(err) ++ { ++ mspi_errmsg("read mspi-group property : %d\n", err); ++ return err; ++ } ++ mspi_dbgmsg("mspi-grounp = %d\n", mspi_group); ++ ++ irq_num = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if(irq_num == 0) ++ { ++ mspi_errmsg("can't find interrupts property\n"); ++ return -ENOENT; ++ } ++ mspi_dbgmsg("irq_num = %d\n", irq_num); ++ if(!snprintf(irq_name, sizeof(irq_name), "mspi%d interrupt", mspi_group)) ++ { ++ mspi_errmsg("find irq reformat failed\n"); ++ return -ENOENT; ++ } ++ mspi_dbgmsg("irq name : %s\n", irq_name); ++ ++ err = of_property_read_u32(pdev->dev.of_node, "use-dma", &use_dma); ++ if(err) ++ { ++ use_dma = 0; ++ } ++ ++ if(use_dma && HAL_MSPI_CheckDmaMode(mspi_group)) ++ { ++ mspi_warnmsg("mspi %d no support dma mode, change to normal mode default\n", mspi_group); ++ use_dma = 0; ++ } ++ ++ if(use_dma) ++ { ++ printk("[MSPI] mspi %d use dma mode\n", mspi_group); ++ } ++ else ++ { ++ printk("[MSPI] mspi %d use normal mode\n", mspi_group); ++ } ++ ++ err = of_property_read_u32(pdev->dev.of_node, "pad-ctrl", &pad_ctrl); ++ if(err) ++ { ++ mspi_dbgmsg("read pad-ctrl failed \n"); ++ } ++ ++ mspi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(!mspi_resource) ++ { ++ return -ENOENT; ++ } ++ mspi_base = (void *)(IO_ADDRESS(mspi_resource->start)); ++ mspi_dbgmsg("mspi_base = %px\n",mspi_base); ++ ++ sstar_master = spi_alloc_master(&pdev->dev, sizeof(struct sstar_mspi)); ++ if (!sstar_master) ++ { ++ mspi_errmsg( "alloc spi master failed\n"); ++ dev_err(&pdev->dev, "alloc spi master failed\n"); ++ return -ENOMEM; ++ } ++ sstar_master->mode_bits = SSTAR_SPI_MODE_BITS; ++ sstar_master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, MSPI_MAX_SUPPORT_BITS);; ++ sstar_master->num_chipselect = 3; ++ sstar_master->transfer_one_message = sstar_spi_transfer_one; ++ sstar_master->dev.of_node = pdev->dev.of_node; ++ sstar_master->setup = sstar_spi_setup; ++ //sstar_master->max_speed_hz = 72000000; ++ //sstar_master->min_speed_hz = 46875; ++ sstar_master->bus_num = mspi_group; ++ platform_set_drvdata(pdev, sstar_master); ++ ++ sstar_spimst = spi_master_get_devdata(sstar_master); ++ sstar_spimst->hal.mspi_base = (u32)mspi_base; ++ sstar_spimst->use_dma = use_dma; ++ sstar_spimst->bus_num = mspi_group; ++ sstar_spimst->pdev = pdev; ++ sstar_spimst->hal.pad_ctrl= pad_ctrl; ++ init_completion(&sstar_spimst->hal.done); ++ ++#ifndef CONFIG_SPI_INT_CALL ++ err = request_irq(irq_num, sstar_spi_interrupt, 0, irq_name, (void*)sstar_master); ++ if (err == 0) ++ { ++ mspi_dbgmsg("%s registered\n", irq_name); ++ } ++ else ++ { ++ mspi_errmsg("%s register failed", irq_name); ++ goto err_irq; ++ } ++ sstar_spimst->irq_num = irq_num; ++#endif ++ ++#ifdef CONFIG_CAM_CLK ++ sstar_spimst->camclk = kmalloc((sizeof(void *) * 2), GFP_KERNEL); ++ if(!sstar_spimst->camclk) ++ { ++ err = -ENOMEM; ++ mspi_errmsg("malloc camclk fail\n"); ++ goto err_cam; ++ } ++ err = of_property_read_u32_index(pdev->dev.of_node,"camclk", 0, &mspi_clkid); ++ if(err) ++ { ++ err = -EINVAL; ++ mspi_errmsg("read camclk 0 property fail\n"); ++ goto err_cam; ++ } ++ mspi_dbgmsg("mspi %d camclk property : %d\n", mspi_group, mspi_clkid); ++ ++ err = of_property_read_u32_index(pdev->dev.of_node,"camclk", 1, &movedma_clkid); ++ if(err) ++ { ++ err = -EINVAL; ++ mspi_errmsg("read camclk 1 property fail\n"); ++ goto err_cam; ++ } ++ mspi_dbgmsg("movedma camclk property : %d\n", movedma_clkid); ++ ++ if(!snprintf(cam_name, sizeof(cam_name), "mspi%d camclk", mspi_group)) ++ { ++ mspi_errmsg("mspi %d camclk name reformat failed\n", mspi_group); ++ err = -ENOENT; ++ goto err_cam; ++ } ++ mspi_dbgmsg("camlck name : %s\n", cam_name); ++ ++ if(CamClkRegister(cam_name, mspi_clkid, &sstar_spimst->camclk[0])) ++ { ++ err = -ENOENT; ++ mspi_errmsg("register mspi %d camclk fail\n", mspi_group); ++ goto err_cam; ++ } ++ ++ if(CamClkRegister("movedma camclk", movedma_clkid, &sstar_spimst->camclk[1])) ++ { ++ err = -ENOENT; ++ mspi_errmsg("register movedma camclk fail\n"); ++ goto err_cam; ++ } ++ ++ if(CamClkAttrGet(sstar_spimst->camclk[0], &stGetCfg)) ++ { ++ err = -ENOENT; ++ mspi_errmsg("get camclk att fail\n"); ++ goto err_cam; ++ } ++ num_parents = stGetCfg.u32NodeCount; ++ mspi_dbgmsg("parents n = %d\n", num_parents); ++ sstar_spimst->mspi_clk_tbl.clk_src_tbl_sz = num_parents; ++ sstar_spimst->mspi_clk_tbl.clk_src_tbl = kmalloc(sizeof(u32) * sstar_spimst->mspi_clk_tbl.clk_src_tbl_sz, GFP_KERNEL); ++ if(!sstar_spimst->mspi_clk_tbl.clk_src_tbl) ++ { ++ err = -ENOMEM; ++ mspi_errmsg("malloc clk_src_tbl fail\n"); ++ goto err_src; ++ } ++ for (i = 0; i < num_parents; i++) ++ { ++ sstar_spimst->mspi_clk_tbl.clk_src_tbl[i] = CamClkRateGet(stGetCfg.u32Parent[i]); ++ mspi_dbgmsg("clk src %d = %d\n", i, sstar_spimst->mspi_clk_tbl.clk_src_tbl[i]); ++ } ++#else ++ // clock table source table cfg ++ mspi_clock = of_clk_get(pdev->dev.of_node, 0); ++ if (IS_ERR(mspi_clock)) ++ { ++ mspi_errmsg("get mspi %d clock fail\n", mspi_group); ++ err = -ENXIO; ++ goto err_irq; ++ } ++ num_parents = clk_hw_get_num_parents(__clk_get_hw(mspi_clock)); ++ mspi_dbgmsg("parents n = %d\n", num_parents); ++ sstar_spimst->mspi_clk_tbl.clk_src_tbl_sz = num_parents; ++ sstar_spimst->mspi_clk_tbl.clk_src_tbl = kmalloc(sizeof(u32) * sstar_spimst->mspi_clk_tbl.clk_src_tbl_sz, GFP_KERNEL); ++ if(!sstar_spimst->mspi_clk_tbl.clk_src_tbl) ++ { ++ err = -ENOMEM; ++ mspi_errmsg("malloc clk_src_tbl fail\n"); ++ goto err_src; ++ } ++ for (i = 0; i < num_parents; i++) ++ { ++ parent_hw = clk_hw_get_parent_by_index(__clk_get_hw(mspi_clock), i); ++ sstar_spimst->mspi_clk_tbl.clk_src_tbl[i] = clk_get_rate(parent_hw->clk); ++ mspi_dbgmsg("clk src %d = %d\n", i, sstar_spimst->mspi_clk_tbl.clk_src_tbl[i]); ++ } ++ clk_put(mspi_clock); ++#endif ++ ++ // clock table divide table cfg ++ sstar_spimst->mspi_clk_tbl.clk_div_tbl_sz = ARRAY_SIZE(sstar_spi_clk_div_tbl); ++ sstar_spimst->mspi_clk_tbl.clk_div_tbl = kmalloc(sizeof(u32) * sstar_spimst->mspi_clk_tbl.clk_div_tbl_sz, GFP_KERNEL); ++ if (!sstar_spimst->mspi_clk_tbl.clk_div_tbl) ++ { ++ err = -ENOMEM; ++ mspi_errmsg("malloc clk_div_tbl fail\n"); ++ goto err_div; ++ } ++ memcpy(sstar_spimst->mspi_clk_tbl.clk_div_tbl, sstar_spi_clk_div_tbl, sizeof(sstar_spi_clk_div_tbl)); ++ for (i = 0; i < ARRAY_SIZE(sstar_spi_clk_div_tbl); i++) ++ { ++ mspi_dbgmsg("clk div %d = %d\n", i, sstar_spimst->mspi_clk_tbl.clk_div_tbl[i]); ++ } ++ ++ // clock table config table malloc ++ sstar_spimst->mspi_clk_tbl.clk_cfg_tbl_sz = sstar_spimst->mspi_clk_tbl.clk_div_tbl_sz * sstar_spimst->mspi_clk_tbl.clk_src_tbl_sz; ++ sstar_spimst->mspi_clk_tbl.clk_cfg_tbl = kmalloc(sizeof(struct mspi_clk) * sstar_spimst->mspi_clk_tbl.clk_cfg_tbl_sz, GFP_KERNEL); ++ if(!sstar_spimst->mspi_clk_tbl.clk_cfg_tbl) ++ { ++ err = -ENOMEM; ++ mspi_errmsg("malloc clk_cfg_tbl fail\n"); ++ goto err_cfg; ++ } ++ ++ /* initialise the clock calc table for calc closest clock */ ++ sstar_spi_clk_tbl_init(&sstar_spimst->mspi_clk_tbl); ++ ++ sstar_master->max_speed_hz = sstar_spimst->mspi_clk_tbl.clk_cfg_tbl[sstar_spimst->mspi_clk_tbl.clk_cfg_tbl_sz-1].clk_rate; ++ sstar_master->min_speed_hz = sstar_spimst->mspi_clk_tbl.clk_cfg_tbl[0].clk_rate; ++ mspi_dbgmsg("max_speed_hz = %d\n", sstar_master->max_speed_hz); ++ mspi_dbgmsg("min_speed_hz = %d\n", sstar_master->min_speed_hz); ++ ++ /* initialise the hardware */ ++ err = HAL_MSPI_Config(&sstar_spimst->hal); ++ if(err) ++ { ++ err = -EIO; ++ mspi_errmsg("config mspi%d master: %d\n", mspi_group, err); ++ dev_err(&pdev->dev, "config mspi%d master: %d\n", mspi_group, err); ++ goto err_out; ++ } ++ ++ //err = devm_spi_register_master(sstar_master); ++ err = spi_register_master(sstar_master); ++ if (err) ++ { ++ mspi_errmsg("could not register mspi%d master: %d\n", mspi_group, err); ++ dev_err(&pdev->dev, "could not register mspi%d master: %d\n", mspi_group, err); ++ goto err_out; ++ } ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<< Probe End >>>>>>>>>>>>>\n"); ++ ++#if IS_ENABLED(CONFIG_SPI_SPIDEV) ++ spi_new_device(sstar_master, &sstar_info); // use for "user mode spi device driver support" ++#endif ++ ++ return 0; ++ ++err_out: ++ spi_unregister_master(sstar_master); ++err_cfg: ++ kfree(sstar_spimst->mspi_clk_tbl.clk_cfg_tbl); ++err_div: ++ kfree(sstar_spimst->mspi_clk_tbl.clk_div_tbl); ++err_src: ++ kfree(sstar_spimst->mspi_clk_tbl.clk_src_tbl); ++#ifdef CONFIG_CAM_CLK ++err_cam: ++ kfree(sstar_spimst->camclk); ++#endif ++err_irq: ++ free_irq(irq_num, (void*)sstar_master); ++ return err; ++} ++ ++static int sstar_spi_remove(struct platform_device *pdev) ++{ ++#ifdef CONFIG_CAM_CLK ++ u8 cam_on; ++#else ++ struct clk *mspi_clock; ++ struct clk *movdma_clock; ++ struct clk_hw *mspi_hw; ++ struct clk_hw *movdma_hw; ++ struct clk_hw *parent_hw; ++#endif ++ ++ struct spi_master *sstar_master = platform_get_drvdata(pdev); ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(sstar_master); ++ ++ if(sstar_master) ++ { ++ ++#ifdef CONFIG_CAM_CLK ++ if(CamClkGetOnOff(sstar_spimst->camclk[0], &cam_on)) ++ { ++ mspi_errmsg("cam clk 0 get on fail\n"); ++ return -ENOENT; ++ } ++ if(cam_on) ++ { ++ if(CamClkSetOnOff(sstar_spimst->camclk[0], 0)) ++ { ++ mspi_errmsg("cam clk 0 set on fail\n"); ++ return -ENOENT; ++ } ++ } ++ if(CamClkUnregister(sstar_spimst->camclk[0])) ++ { ++ mspi_errmsg("cam clk 0 unregister fail\n"); ++ return -ENOENT; ++ } ++ ++ if(CamClkGetOnOff(sstar_spimst->camclk[1], &cam_on)) ++ { ++ mspi_errmsg("cam clk 1 get on fail\n"); ++ return -ENOENT; ++ } ++ if(cam_on) ++ { ++ if(CamClkSetOnOff(sstar_spimst->camclk[1], 0)) ++ { ++ mspi_errmsg("cam clk 1 set on fail\n"); ++ return -ENOENT; ++ } ++ } ++ if(CamClkUnregister(sstar_spimst->camclk[1])) ++ { ++ mspi_errmsg("cam clk 1 unregister fail\n"); ++ return -ENOENT; ++ } ++ kfree(sstar_spimst->camclk); ++ sstar_spimst->camclk = NULL; ++#else ++ mspi_clock = of_clk_get(sstar_spimst->pdev->dev.of_node, 0); ++ if (IS_ERR(mspi_clock)) ++ { ++ mspi_errmsg("get clock fail 0\n"); ++ return -ENOENT; ++ } ++ if(__clk_is_enabled(mspi_clock)) ++ { ++ mspi_hw = __clk_get_hw(mspi_clock); ++ parent_hw = clk_hw_get_parent_by_index(mspi_hw, 0); ++ clk_set_parent(mspi_clock, parent_hw->clk); ++ clk_disable_unprepare(mspi_clock); ++ } ++ clk_put(mspi_clock); ++ ++ movdma_clock = of_clk_get(sstar_spimst->pdev->dev.of_node, 1); ++ if (IS_ERR(movdma_clock)) ++ { ++ mspi_errmsg("get clock fail 1\n"); ++ return -ENOENT; ++ } ++ if(__clk_is_enabled(movdma_clock)) ++ { ++ movdma_hw = __clk_get_hw(movdma_clock); ++ parent_hw = clk_hw_get_parent_by_index(movdma_hw, 0); ++ clk_set_parent(movdma_clock, parent_hw->clk); ++ clk_disable_unprepare(movdma_clock); ++ } ++ clk_put(movdma_clock); ++#endif ++ ++ free_irq(sstar_spimst->irq_num, (void *)sstar_master); ++ ++ if(sstar_spimst->mspi_clk_tbl.clk_cfg_tbl) ++ { ++ kfree(sstar_spimst->mspi_clk_tbl.clk_cfg_tbl); ++ } ++ if(sstar_spimst->mspi_clk_tbl.clk_div_tbl) ++ { ++ kfree(sstar_spimst->mspi_clk_tbl.clk_div_tbl); ++ } ++ if(sstar_spimst->mspi_clk_tbl.clk_src_tbl) ++ { ++ kfree(sstar_spimst->mspi_clk_tbl.clk_src_tbl); ++ } ++ ++ spi_unregister_master(sstar_master); ++ ++ } ++ else ++ { ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_SPI_INT_CALL ++int sstar_spi_transfer(struct spi_device *spi, struct spi_transfer *tfr, int chip_select) ++{ ++ int ret = 0; ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(spi->master); ++ ++ sstar_spimst->tx_buf = tfr->tx_buf; ++ sstar_spimst->rx_buf = tfr->rx_buf; ++ sstar_spimst->len = tfr->len; ++ ++ if(chip_select) ++ { ++ MDrv_GPIO_Set_High(chip_select); ++ MDrv_GPIO_Set_Low(chip_select); ++ } ++ else ++ { ++ HAL_MSPI_ChipSelect(&sstar_spimst->hal,1,0); ++ } ++ ++ if(sstar_spimst->tx_buf != NULL && sstar_spimst->rx_buf != NULL) ++ { ++ ret = HAL_MSPI_FullDuplex(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->rx_buf, (u8 *)sstar_spimst->tx_buf, (u16)sstar_spimst->len); ++ } ++ else if(sstar_spimst->tx_buf != NULL) ++ { ++ ret = HAL_MSPI_Write(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->tx_buf,(u16)sstar_spimst->len); ++ } ++ else if(sstar_spimst->rx_buf != NULL) ++ { ++ ret = HAL_MSPI_Read(spi->master->bus_num, &sstar_spimst->hal, (u8 *)sstar_spimst->rx_buf, (u16)sstar_spimst->len); ++ } ++ ++ if(chip_select) ++ { ++ MDrv_GPIO_Set_High(chip_select); ++ } ++ else ++ { ++ HAL_MSPI_ChipSelect(&sstar_spimst->hal,0,0); ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(sstar_spi_transfer); ++#endif ++ ++ ++#ifdef CONFIG_PM_SLEEP ++static int sstar_spi_suspend(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct spi_master *sstar_master = platform_get_drvdata(pdev); ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(sstar_master); ++ ++ struct clk *mspi_clock; ++ struct clk *movdma_clock; ++ struct clk_hw *mspi_hw; ++ struct clk_hw *movdma_hw; ++ struct clk_hw *parent_hw; ++ ++ mspi_clock = of_clk_get(sstar_spimst->pdev->dev.of_node, 0); ++ if (IS_ERR(mspi_clock)) ++ { ++ mspi_errmsg("get clock fail 0\n"); ++ return -ENOENT; ++ } ++ if(__clk_is_enabled(mspi_clock)) ++ { ++ mspi_hw = __clk_get_hw(mspi_clock); ++ parent_hw = clk_hw_get_parent_by_index(mspi_hw, 0); ++ clk_set_parent(mspi_clock, parent_hw->clk); ++ clk_disable_unprepare(mspi_clock); ++ } ++ clk_put(mspi_clock); ++ ++ movdma_clock = of_clk_get(sstar_spimst->pdev->dev.of_node, 1); ++ if (IS_ERR(movdma_clock)) ++ { ++ mspi_errmsg("get clock fail 1\n"); ++ return -ENOENT; ++ } ++ if(__clk_is_enabled(movdma_clock)) ++ { ++ movdma_hw = __clk_get_hw(movdma_clock); ++ parent_hw = clk_hw_get_parent_by_index(movdma_hw, 0); ++ clk_set_parent(movdma_clock, parent_hw->clk); ++ clk_disable_unprepare(movdma_clock); ++ } ++ clk_put(movdma_clock); ++ ++ return 0; ++} ++ ++static int sstar_spi_resume(struct device *dev) ++{ ++ int err = 0; ++ u32 new_clock = 0; ++ struct platform_device *pdev = to_platform_device(dev); ++ struct spi_master *sstar_master = platform_get_drvdata(pdev); ++ struct sstar_mspi *sstar_spimst = spi_master_get_devdata(sstar_master); ++ ++ err = HAL_MSPI_Config(&sstar_spimst->hal); ++ if(err) ++ { ++ return -EIO; ++ } ++ ++ err = HAL_MSPI_SetMode(&sstar_spimst->hal, sstar_spimst->mode & (SPI_CPHA | SPI_CPOL)); ++ if(err) ++ { ++ return -EIO; ++ } ++ ++ err = HAL_MSPI_SetLSB(&sstar_spimst->hal, (sstar_spimst->mode & SPI_LSB_FIRST)>>3); ++ if(err) ++ { ++ return -EIO; ++ } ++ ++ new_clock = sstar_spi_set_clock(sstar_spimst, sstar_spimst->max_speed_hz); ++ if(new_clock == 0) ++ { ++ return -EIO;; ++ } ++ mspi_dbgmsg("resume mode:0x%x speed:%d channel:%d\n",sstar_spimst->mode,sstar_spimst->max_speed_hz,sstar_master->bus_num); ++ return err; ++} ++ ++#else ++#define sstar_spi_suspend NULL ++#define sstar_spi_resume NULL ++#endif ++ ++static const struct of_device_id sstar_spi_match[] = { ++ { .compatible = "sstar,mspi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sstar_spi_match); ++ ++static const struct dev_pm_ops sstar_spi_pm_ops = { ++ .suspend = sstar_spi_suspend, ++ .resume = sstar_spi_resume, ++}; ++ ++static struct platform_driver sstar_spi_driver = { ++ .driver = { ++ .name = "spi", ++ .owner = THIS_MODULE, ++ .pm = &sstar_spi_pm_ops, ++ .of_match_table = sstar_spi_match, ++ }, ++ .probe = sstar_spi_probe, ++ .remove = sstar_spi_remove, ++}; ++module_platform_driver(sstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for SigmaStar"); ++MODULE_AUTHOR("Gavin Xu "); ++MODULE_LICENSE("GPL v2"); ++ +diff --git a/drivers/sstar/mspi/infinity5/hal_mspi.c b/drivers/sstar/mspi/infinity5/hal_mspi.c +new file mode 100755 +index 000000000000..0ffeb0b0ebe8 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity5/hal_mspi.c +@@ -0,0 +1,921 @@ ++/* ++* hal_mspi.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include "gpio.h" ++#include ++#include ++#include ++ ++#include "hal_mspi.h" ++#include "hal_mspireg.h" ++ ++#if defined(CONFIG_MS_PADMUX) ++#include "mdrv_padmux.h" ++#endif ++ ++#define SSTAR_MSPI_HAL_MUX 0 ++ ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk("[MSPI] : " args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++#define mspi_errmsg(fmt, ...) printk(KERN_ERR "[MSPI] error : " fmt, ##__VA_ARGS__) ++#define mspi_warnmsg(fmt, ...) printk(KERN_WARNING "[MSPI] warning : " fmt, ##__VA_ARGS__) ++ ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define WRITE_WORD(_reg, _val) (*((volatile u16*)(_reg))) = (u16)(_val) ++ ++#define MSPI_READ(_reg_) READ_WORD(mspi->mspi_base + ((_reg_)<<2)) ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(mspi->mspi_base + ((_reg_)<<2), (_val_)) ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(mspi->mspi_base + ((_reg_)<<2), (_val_), (mask)) ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++ ++#define MSPI_MIU0_BUS_BASE ARM_MIU0_BUS_BASE ++#define MSPI_MIU1_BUS_BASE ARM_MIU1_BUS_BASE ++ ++#define MSPI_DMA_MODE_MAX 1 ++ ++typedef enum ++{ ++ E_MSPI_OK = 0, ++ E_MSPI_INIT_FLOW_ERROR, ++ E_MSPI_DCCONFIG_ERROR, ++ E_MSPI_CLKCONFIG_ERROR, ++ E_MSPI_FRAMECONFIG_ERROR, ++ E_MSPI_OPERATION_ERROR, ++ E_MSPI_PARAM_OVERFLOW, ++ E_MSPI_MMIO_ERROR, ++ E_MSPI_TIMEOUT, ++ E_MSPI_HW_NOT_SUPPORT, ++ E_MSPI_NOMEM, ++ E_MSPI_NULL, ++ E_MSPI_ERR, ++} MSPI_ErrorNo; ++ ++typedef enum ++{ ++ E_MSPI_OFF = 0, ++ E_MSPI_ON, ++} MSPI_CsState; ++ ++typedef enum ++{ ++ E_MSPI_CS0 = 0, ++ E_MSPI_CS1, ++ E_MSPI_CS2, ++} MSPI_CsChannel; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++static bool gbInitFlag = false; ++ ++#if SSTAR_MSPI_HAL_MUX ++static CamOsMutex_t hal_mspi_lock; ++#define HAL_MSPI_Lock() CamOsMutexLock(&hal_mspi_lock); ++#define HAL_MSPI_Unlock() CamOsMutexUnlock(&hal_mspi_lock); ++#else ++#define HAL_MSPI_Lock() ++#define HAL_MSPI_Unlock() ++#endif ++ ++static void HAL_MSPI_Enable(struct mspi_hal *mspi, bool bEnable) ++{ ++ HAL_MSPI_Lock(); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ HAL_MSPI_Unlock(); ++} ++ ++void HAL_MSPI_select_pad( int pad_ctrl, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_SPI0: ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(MSPI0_MODE<<2), pad_mode << 0, 0x3 << 0); //reg_spi0_mode[1:0] ++ break; ++ case MUX_SPI1: ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(MSPI1_MODE<<2), pad_mode << 4, 0x7 << 4); //reg_spi1_mode[6:4] ++ break; ++ ++ default: ++ break; ++ } ++ ++ if(pad_ctrl==PAD_SPI0_CZ) ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(0x0F<<2), 0, 0x02 << 0); //Disable jtag mode // IO PAD conflict turn off jtag ++} ++ ++int HAL_MSPI_get_padmux(int pad_ctrl, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(pad_ctrl) ++ { ++ /* mspi0, 3 modes */ ++ case PAD_SPI0_CZ: ++ *padmux = MUX_SPI0; ++ *pad_mode = 1; ++ break; ++ case PAD_GPIO8: ++ *padmux = MUX_SPI0; ++ *pad_mode = 2; ++ break; ++ case PAD_FUART_RX: ++ *padmux = MUX_SPI0; ++ *pad_mode = 3; ++ break; ++ ++ /* mspi1, 6 modes */ ++ case PAD_SPI1_CZ: ++ *padmux = MUX_SPI1; ++ *pad_mode = 1; ++ break; ++ case PAD_GPIO12: ++ *padmux = MUX_SPI1; ++ *pad_mode = 2; ++ break; ++ case PAD_SD_D0: ++ *padmux = MUX_SPI1; ++ *pad_mode = 3; ++ break; ++ case PAD_GPIO0: ++ *padmux = MUX_SPI1; ++ *pad_mode = 4; ++ break; ++ case PAD_SNR1_DA0P: ++ *padmux = MUX_SPI1; ++ *pad_mode = 5; ++ break; ++ case PAD_LCD_D0: ++ *padmux = MUX_SPI1; ++ *pad_mode = 6; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} ++ ++static void HAL_MSPI_PadSet(struct mspi_hal *mspi) ++{ ++ u8 padmux; ++ u8 pad_mode; ++ ++ HAL_MSPI_get_padmux(mspi->pad_ctrl,&padmux,&pad_mode); ++ HAL_MSPI_select_pad(mspi->pad_ctrl,padmux,pad_mode); ++} ++ ++static void HAL_MSPI_Init(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++#if defined(CONFIG_MS_PADMUX) ++ if (0 == mdrv_padmux_active()) ++#endif ++ { ++ HAL_MSPI_PadSet(mspi); ++ } ++ ++ HAL_MSPI_Unlock(); ++ HAL_MSPI_Enable(mspi,true); ++ gbInitFlag = true; ++} ++ ++static void HAL_MSPI_Reset_DCConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++void HAL_MSPI_SetDcTiming(struct mspi_hal *mspi, eDC_config eDCField, u8 u8DCtiming) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ HAL_MSPI_Unlock(); ++} ++ ++ ++static u8 HAL_DC_TrStartSetting(struct mspi_hal *mspi, u8 TrStart) ++{ ++ u8 u8TrStartMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++ ++ ++static u8 HAL_DC_TrEndSetting(struct mspi_hal *mspi,u8 TrEnd) ++{ ++ u8 u8TrEndMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TREND ,TrEnd); ++ return errnum; ++} ++ ++static u8 HAL_DC_TBSetting(struct mspi_hal *mspi, u8 TB) ++{ ++ u8 u8TBMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TB ,TB); ++ return errnum; ++} ++ ++static u8 HAL_DC_TRWSetting(struct mspi_hal *mspi, u8 TRW) ++{ ++ u8 u8TRWMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRW ,TRW); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_DCConfig(struct mspi_hal *mspi, MSPI_DCConfig *ptDCConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_ERR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(mspi); ++ return E_MSPI_OK; ++ } ++ errnum = HAL_DC_TrStartSetting(mspi,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TrEndSetting(mspi,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TBSetting(mspi,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TRWSetting(mspi,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++static void HAL_MSPI_SetCLKTiming(struct mspi_hal *mspi, eCLK_config eCLKField, u8 u8CLKVal) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eCLKField) ++ { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_Reset_CLKConfig(struct mspi_hal *mspi) ++{ ++ u16 Tempbuf; ++ HAL_MSPI_Lock(); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) ++ { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) ++ { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(mspi); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static void HAL_MSPI_Reset_FrameConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xFFF); ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_SetPerFrameSize(struct mspi_hal *mspi, u8 bDirect, u8 u8BufOffset, u8 u8PerFrameSize) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 u8BitOffset = 0; ++ u16 u16regIndex = 0; ++ ++ HAL_MSPI_Lock(); ++ if(bDirect == MSPI_READ_INDEX) ++ { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } ++ else ++ { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_FRAMEConfig(struct mspi_hal *mspi, MSPI_FrameConfig *ptFrameConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ u8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) ++ { ++ HAL_MSPI_Reset_FrameConfig(mspi); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi, u8 Enable, u8 eSelect) ++{ ++ u16 regdata = 0; ++ u8 bitmask = 0; ++ HAL_MSPI_Lock(); ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) ++ { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } ++ else ++ { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable) ++{ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ HAL_MSPI_Unlock(); ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Config(struct mspi_hal *mspi) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++#if SSTAR_MSPI_HAL_MUX ++ CamOsMutexInit(&hal_mspi_lock); ++#endif ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ HAL_MSPI_Init(mspi); ++ ++ errnum = HAL_MSPI_DCConfig(mspi, &stDCConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_SetMode(mspi, mspimode); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_FRAMEConfig(mspi, &stFrameConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ //MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ HAL_MSPI_ChipSelect(mspi,E_MSPI_OFF,E_MSPI_CS0); ++ errnum = HAL_MSPI_SetLSB(mspi, 0); ++ if(errnum) ++ { ++ return errnum; ++ } ++ return errnum; ++} ++ ++static void HAL_MSPI_RWBUFSize(struct mspi_hal *mspi,u8 Direct, u8 Size) ++{ ++ u16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++ ++u8 HAL_MSPI_Trigger(struct mspi_hal *mspi) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&mspi->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ timeout = wait_for_completion_timeout(&mspi->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) ++ { ++ mspi_errmsg("mspi timeout\n"); ++ return E_MSPI_TIMEOUT; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static u8 HAL_MSPI_FullDuplexBuf(struct mspi_hal *mspi, u8 *rx_buff, u8 *tx_buff, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ ++ HAL_MSPI_Lock(); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = (tx_buff[u8Index] << 8) | tx_buff[u8Index-1]; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),tx_buff[u8Index]); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ rx_buff[u8Index] = u16TempBuf >> 8; ++ rx_buff[u8Index-1] = u16TempBuf & 0xFF; ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ rx_buff[u8Index] = u16TempBuf & 0xFF; ++ } ++ } ++ ++err_out: ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_ReadBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u16 i =0, j = 0; ++ u8 errnum = E_MSPI_OK; ++ ++ HAL_MSPI_Lock(); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) ++ { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) ++ { ++ j = MAX_READ_BUF_SIZE; ++ } ++ else ++ { ++ j = u16TempBuf; ++ } ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, j); ++ ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < j; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } ++ else if(u8Index == (j -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ } ++ pData+= j; ++ } ++ ++err_out: ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_WriteBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ ++ HAL_MSPI_Lock(); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ // set write data size ++err_out: ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(rx_buff == NULL || tx_buff == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16Index*MAX_READ_BUF_SIZE,tx_buff+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16TempFrameCnt*MAX_READ_BUF_SIZE,tx_buff+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ return E_MSPI_HW_NOT_SUPPORT; ++} ++ ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ return E_MSPI_HW_NOT_SUPPORT; ++} ++ ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi) ++{ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++ ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi) ++{ ++ MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE); ++} ++ ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div) ++{ ++ u16 TempData = 0; ++ ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= div << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel) ++{ ++ return E_MSPI_HW_NOT_SUPPORT; ++} ++ +diff --git a/drivers/sstar/mspi/infinity5/hal_mspi.h b/drivers/sstar/mspi/infinity5/hal_mspi.h +new file mode 100755 +index 000000000000..cadcec667119 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity5/hal_mspi.h +@@ -0,0 +1,60 @@ ++/* ++* hal_mspi.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_H__ ++#define __MHAL_MSPI_H__ ++ ++#define MSPI_MAX_SUPPORT_BITS 16 ++ ++struct mspi_hal ++{ ++ u32 mspi_base; ++ u32 pad_ctrl; ++ u32 bits_per_word; ++ struct completion done; ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel); ++u8 HAL_MSPI_Config(struct mspi_hal *mspi); ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi); ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi); ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable); ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div); ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode); ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi,u8 Enable ,u8 eSelect); ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size); ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity5/hal_mspireg.h b/drivers/sstar/mspi/infinity5/hal_mspireg.h +new file mode 100755 +index 000000000000..b2b54f523ff5 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity5/hal_mspireg.h +@@ -0,0 +1,95 @@ ++/* ++* hal_mspireg.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_REG_H__ ++#define __MHAL_MSPI_REG_H__ ++ ++#define MUX_SPI0 0 ++#define MUX_SPI1 1 ++ ++#define EJTAG_MODE 0x0F ++#define MSPI0_MODE 0x0C //bit0~bit1 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_OFFSET 0x78 ++ ++//chip select bit map ++#define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++//spi dma ++#define MSPI_DMA_DATA_LENGTH_L 0x30 ++#define MSPI_DMA_DATA_LENGTH_H 0x31 ++#define MSPI_DMA_ENABLE 0x32 ++#define MSPI_DMA_RW_MODE 0x33 ++ #define MSPI_DMA_WRITE 0x00 ++ #define MSPI_DMA_READ 0x01 ++ ++#define MSPI_CLK_DIV_VAL {2, 4, 8, 16, 32, 64, 128, 256} ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity6/hal_mspi.c b/drivers/sstar/mspi/infinity6/hal_mspi.c +new file mode 100755 +index 000000000000..bb6d4ad51e39 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6/hal_mspi.c +@@ -0,0 +1,1018 @@ ++/* ++* hal_mspi.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include "gpio.h" ++#include ++#include ++#include ++#include ++ ++#include "hal_mspi.h" ++#include "hal_mspireg.h" ++ ++#if defined(CONFIG_MS_PADMUX) ++#include "mdrv_padmux.h" ++#endif ++ ++#define SSTAR_MSPI_HAL_MUX 0 ++ ++#define mspi_dbg 1 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk("[MSPI] : " args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++#define mspi_errmsg(fmt, ...) printk(KERN_ERR "[MSPI] error : " fmt, ##__VA_ARGS__) ++#define mspi_warnmsg(fmt, ...) printk(KERN_ERR "[MSPI] warning : " fmt, ##__VA_ARGS__) ++ ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define WRITE_WORD(_reg, _val) (*((volatile u16*)(_reg))) = (u16)(_val) ++ ++#define MSPI_READ(_reg_) READ_WORD(mspi->mspi_base + ((_reg_)<<2)) ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(mspi->mspi_base + ((_reg_)<<2), (_val_)) ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(mspi->mspi_base + ((_reg_)<<2), (_val_), (mask)) ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++ ++#define MSPI_MIU0_BUS_BASE ARM_MIU0_BUS_BASE ++#define MSPI_MIU1_BUS_BASE ARM_MIU1_BUS_BASE ++ ++#define MSPI_DMA_MODE_MAX 1 ++ ++typedef enum ++{ ++ E_MSPI_OK = 0, ++ E_MSPI_INIT_FLOW_ERROR, ++ E_MSPI_DCCONFIG_ERROR, ++ E_MSPI_CLKCONFIG_ERROR, ++ E_MSPI_FRAMECONFIG_ERROR, ++ E_MSPI_OPERATION_ERROR, ++ E_MSPI_PARAM_OVERFLOW, ++ E_MSPI_MMIO_ERROR, ++ E_MSPI_TIMEOUT, ++ E_MSPI_HW_NOT_SUPPORT, ++ E_MSPI_NOMEM, ++ E_MSPI_NULL, ++ E_MSPI_ERR, ++} MSPI_ErrorNo; ++ ++typedef enum ++{ ++ E_MSPI_OFF = 0, ++ E_MSPI_ON, ++} MSPI_CsState; ++ ++typedef enum ++{ ++ E_MSPI_CS0 = 0, ++ E_MSPI_CS1, ++ E_MSPI_CS2, ++} MSPI_CsChannel; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++static bool gbInitFlag = false; ++ ++#if SSTAR_MSPI_HAL_MUX ++static CamOsMutex_t hal_mspi_lock; ++#define HAL_MSPI_Lock() CamOsMutexLock(&hal_mspi_lock); ++#define HAL_MSPI_Unlock() CamOsMutexUnlock(&hal_mspi_lock); ++#else ++#define HAL_MSPI_Lock() ++#define HAL_MSPI_Unlock() ++#endif ++ ++static void HAL_MSPI_Enable(struct mspi_hal *mspi, bool bEnable) ++{ ++ HAL_MSPI_Lock(); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ HAL_MSPI_Unlock(); ++} ++ ++void HAL_MSPI_select_pad( int pad_ctrl, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_SPI0: ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(MSPI0_MODE<<2), pad_mode << 0, 0x7 << 0); //reg_spi0_mode[2:0] ++ break; ++ case MUX_SPI1: ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(MSPI1_MODE<<2), pad_mode << 4, 0x7 << 4); //reg_spi1_mode[6:4] ++ break; ++ ++ default: ++ break; ++ } ++ ++ if(pad_ctrl==PAD_SPI0_CZ) ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(0x0F<<2), 0, 0x02 << 0); //Disable jtag mode // IO PAD conflict turn off jtag ++} ++ ++int HAL_MSPI_get_padmux(int pad_ctrl, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(pad_ctrl) ++ { ++ case PAD_SPI0_CZ: ++ *padmux=MUX_SPI0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_SPI1_CZ: ++ *padmux=MUX_SPI1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ *padmux=MUX_SPI1; ++ *pad_mode=0x4; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} ++ ++static void HAL_MSPI_PadSet(struct mspi_hal *mspi) ++{ ++ u8 padmux; ++ u8 pad_mode; ++ ++ HAL_MSPI_get_padmux(mspi->pad_ctrl,&padmux,&pad_mode); ++ HAL_MSPI_select_pad(mspi->pad_ctrl,padmux,pad_mode); ++} ++ ++static void HAL_MSPI_Init(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++#if defined(CONFIG_MS_PADMUX) ++ if (0 == mdrv_padmux_active()) ++#endif ++ { ++ HAL_MSPI_PadSet(mspi); ++ } ++ ++ HAL_MSPI_Unlock(); ++ HAL_MSPI_Enable(mspi,true); ++ gbInitFlag = true; ++} ++ ++static void HAL_MSPI_Reset_DCConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++void HAL_MSPI_SetDcTiming (struct mspi_hal *mspi, eDC_config eDCField, u8 u8DCtiming) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ HAL_MSPI_Unlock(); ++} ++ ++ ++static u8 HAL_DC_TrStartSetting(struct mspi_hal *mspi, u8 TrStart) ++{ ++ u8 u8TrStartMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++ ++ ++static u8 HAL_DC_TrEndSetting(struct mspi_hal *mspi,u8 TrEnd) ++{ ++ u8 u8TrEndMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TREND ,TrEnd); ++ return errnum; ++} ++ ++static u8 HAL_DC_TBSetting(struct mspi_hal *mspi, u8 TB) ++{ ++ u8 u8TBMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TB ,TB); ++ return errnum; ++} ++ ++static u8 HAL_DC_TRWSetting(struct mspi_hal *mspi, u8 TRW) ++{ ++ u8 u8TRWMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRW ,TRW); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_DCConfig(struct mspi_hal *mspi, MSPI_DCConfig *ptDCConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_ERR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(mspi); ++ return E_MSPI_OK; ++ } ++ errnum = HAL_DC_TrStartSetting(mspi,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TrEndSetting(mspi,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TBSetting(mspi,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TRWSetting(mspi,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++static void HAL_MSPI_SetCLKTiming(struct mspi_hal *mspi, eCLK_config eCLKField, u8 u8CLKVal) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eCLKField) ++ { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_Reset_CLKConfig(struct mspi_hal *mspi) ++{ ++ u16 Tempbuf; ++ HAL_MSPI_Lock(); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) ++ { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) ++ { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(mspi); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static void HAL_MSPI_Reset_FrameConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xFFF); ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_SetPerFrameSize(struct mspi_hal *mspi, u8 bDirect, u8 u8BufOffset, u8 u8PerFrameSize) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 u8BitOffset = 0; ++ u16 u16regIndex = 0; ++ ++ HAL_MSPI_Lock(); ++ if(bDirect == MSPI_READ_INDEX) ++ { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } ++ else ++ { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_FRAMEConfig(struct mspi_hal *mspi, MSPI_FrameConfig *ptFrameConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ u8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) ++ { ++ HAL_MSPI_Reset_FrameConfig(mspi); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi, u8 Enable, u8 eSelect) ++{ ++ u16 regdata = 0; ++ u8 bitmask = 0; ++ HAL_MSPI_Lock(); ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) ++ { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } ++ else ++ { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable) ++{ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ HAL_MSPI_Unlock(); ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Config(struct mspi_hal *mspi) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++#if SSTAR_MSPI_HAL_MUX ++ CamOsMutexInit(&hal_mspi_lock); ++#endif ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ HAL_MSPI_Init(mspi); ++ ++ errnum = HAL_MSPI_DCConfig(mspi, &stDCConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_SetMode(mspi, mspimode); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_FRAMEConfig(mspi, &stFrameConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ //MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ HAL_MSPI_ChipSelect(mspi,E_MSPI_OFF,E_MSPI_CS0); ++ errnum = HAL_MSPI_SetLSB(mspi, 0); ++ if(errnum) ++ { ++ return errnum; ++ } ++ return errnum; ++} ++ ++static void HAL_MSPI_RWBUFSize(struct mspi_hal *mspi,u8 Direct, u8 Size) ++{ ++ u16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++ ++u8 HAL_MSPI_Trigger(struct mspi_hal *mspi) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&mspi->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ timeout = wait_for_completion_timeout(&mspi->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) ++ { ++ mspi_errmsg("mspi timeout\n"); ++ return E_MSPI_TIMEOUT; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static u8 HAL_MSPI_FullDuplexBuf(struct mspi_hal *mspi, u8 *rx_buff, u8 *tx_buff, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ ++ HAL_MSPI_Lock(); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = (tx_buff[u8Index] << 8) | tx_buff[u8Index-1]; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),tx_buff[u8Index]); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ rx_buff[u8Index] = u16TempBuf >> 8; ++ rx_buff[u8Index-1] = u16TempBuf & 0xFF; ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ rx_buff[u8Index] = u16TempBuf & 0xFF; ++ } ++ } ++ ++err_out: ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_ReadBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u16 i =0, j = 0; ++ u8 errnum = E_MSPI_OK; ++ ++ HAL_MSPI_Lock(); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) ++ { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) ++ { ++ j = MAX_READ_BUF_SIZE; ++ } ++ else ++ { ++ j = u16TempBuf; ++ } ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, j); ++ ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < j; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } ++ else if(u8Index == (j -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ } ++ pData+= j; ++ } ++ ++err_out: ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_WriteBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ ++ HAL_MSPI_Lock(); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ // set write data size ++err_out: ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(rx_buff == NULL || tx_buff == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16Index*MAX_READ_BUF_SIZE,tx_buff+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16TempFrameCnt*MAX_READ_BUF_SIZE,tx_buff+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 errnum; ++ u32 data_addr; ++ HalMoveDmaMspi_t tMoveDmaMspi; ++ HalMoveDmaParam_t tMoveDmaParam; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ data_addr = virt_to_phys(pData); ++ if(data_addr > MSPI_MIU1_BUS_BASE) ++ data_addr -= MSPI_MIU1_BUS_BASE; ++ else ++ data_addr -= MSPI_MIU0_BUS_BASE; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_MSPI; ++ tMoveDmaParam.u32SrcAddr = data_addr; ++ tMoveDmaParam.u32SrcMiuSel = (data_addr < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32DstAddr = 0; ++ tMoveDmaParam.u32DstMiuSel = 0; ++ tMoveDmaParam.u32Count = u16Size; ++ tMoveDmaParam.CallBackFunc = NULL; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ tMoveDmaMspi.u32Direction = HAL_MOVEDMA_WR; ++ tMoveDmaMspi.u32DeviceSelect = u8Channel; ++ tMoveDmaParam.pstMspist = &tMoveDmaMspi; ++ ++ Chip_Flush_Cache_Range((u32)pData, u16Size); ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) ++ { ++ mspi_errmsg("move dma set fail wr\n"); ++ return E_MSPI_ERR; ++ } ++ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_WRITE); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u16Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, u16Size>>16 ); ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, 0); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++err_out: ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x00); ++ HAL_MSPI_Unlock(); ++ return errnum; ++ ++} ++ ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 errnum; ++ u32 data_addr; ++ HalMoveDmaMspi_t tMoveDmaMspi; ++ HalMoveDmaParam_t tMoveDmaParam; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ data_addr = virt_to_phys(pData); ++ if(data_addr > MSPI_MIU1_BUS_BASE) ++ data_addr -= MSPI_MIU1_BUS_BASE; ++ else ++ data_addr -= MSPI_MIU0_BUS_BASE; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_MSPI; ++ tMoveDmaParam.u32SrcAddr = 0; ++ tMoveDmaParam.u32SrcMiuSel = 0; ++ tMoveDmaParam.u32DstAddr = data_addr; ++ tMoveDmaParam.u32DstMiuSel = (data_addr < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32Count = u16Size; ++ tMoveDmaParam.CallBackFunc = NULL; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ tMoveDmaMspi.u32Direction = HAL_MOVEDMA_RD; ++ tMoveDmaMspi.u32DeviceSelect = u8Channel; ++ tMoveDmaParam.pstMspist = &tMoveDmaMspi; ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) ++ { ++ mspi_errmsg("move dma set fail rd\n"); ++ return E_MSPI_ERR; ++ } ++ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_READ); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u16Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, (u16Size>>16)& 0x00FF); // 24bit ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, 0); //spi length = 0 ++ Chip_Inv_Cache_Range((u32)pData, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ Chip_Inv_Cache_Range((u32)pData, u16Size); ++ ++err_out: ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x00); ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi) ++{ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++ ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi) ++{ ++ MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE); ++} ++ ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div) ++{ ++ u16 TempData = 0; ++ ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= div << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel) ++{ ++ if(u8Channel > MSPI_DMA_MODE_MAX) ++ { ++ return E_MSPI_HW_NOT_SUPPORT; ++ } ++ else ++ { ++ return E_MSPI_OK; ++ } ++} ++ +diff --git a/drivers/sstar/mspi/infinity6/hal_mspi.h b/drivers/sstar/mspi/infinity6/hal_mspi.h +new file mode 100755 +index 000000000000..cadcec667119 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6/hal_mspi.h +@@ -0,0 +1,60 @@ ++/* ++* hal_mspi.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_H__ ++#define __MHAL_MSPI_H__ ++ ++#define MSPI_MAX_SUPPORT_BITS 16 ++ ++struct mspi_hal ++{ ++ u32 mspi_base; ++ u32 pad_ctrl; ++ u32 bits_per_word; ++ struct completion done; ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel); ++u8 HAL_MSPI_Config(struct mspi_hal *mspi); ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi); ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi); ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable); ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div); ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode); ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi,u8 Enable ,u8 eSelect); ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u16 u16Size); ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size); ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity6/hal_mspireg.h b/drivers/sstar/mspi/infinity6/hal_mspireg.h +new file mode 100755 +index 000000000000..b2b54f523ff5 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6/hal_mspireg.h +@@ -0,0 +1,95 @@ ++/* ++* hal_mspireg.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_REG_H__ ++#define __MHAL_MSPI_REG_H__ ++ ++#define MUX_SPI0 0 ++#define MUX_SPI1 1 ++ ++#define EJTAG_MODE 0x0F ++#define MSPI0_MODE 0x0C //bit0~bit1 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_OFFSET 0x78 ++ ++//chip select bit map ++#define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++//spi dma ++#define MSPI_DMA_DATA_LENGTH_L 0x30 ++#define MSPI_DMA_DATA_LENGTH_H 0x31 ++#define MSPI_DMA_ENABLE 0x32 ++#define MSPI_DMA_RW_MODE 0x33 ++ #define MSPI_DMA_WRITE 0x00 ++ #define MSPI_DMA_READ 0x01 ++ ++#define MSPI_CLK_DIV_VAL {2, 4, 8, 16, 32, 64, 128, 256} ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity6b0/hal_mspi.c b/drivers/sstar/mspi/infinity6b0/hal_mspi.c +new file mode 100755 +index 000000000000..5d2e33fa0b44 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6b0/hal_mspi.c +@@ -0,0 +1,1063 @@ ++/* ++* hal_mspi.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include "gpio.h" ++#include ++#include ++#include ++#include ++ ++#include "hal_mspi.h" ++#include "hal_mspireg.h" ++ ++#if defined(CONFIG_MS_PADMUX) ++#include "mdrv_padmux.h" ++#endif ++ ++#define SSTAR_MSPI_HAL_MUX 0 ++ ++#define mspi_dbg 1 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk("[MSPI] : " args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++#define mspi_errmsg(fmt, ...) printk(KERN_ERR "[MSPI] error : " fmt, ##__VA_ARGS__) ++#define mspi_warnmsg(fmt, ...) printk(KERN_ERR "[MSPI] warning : " fmt, ##__VA_ARGS__) ++ ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define WRITE_WORD(_reg, _val) (*((volatile u16*)(_reg))) = (u16)(_val) ++ ++#define MSPI_READ(_reg_) READ_WORD(mspi->mspi_base + ((_reg_)<<2)) ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(mspi->mspi_base + ((_reg_)<<2), (_val_)) ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(mspi->mspi_base + ((_reg_)<<2), (_val_), (mask)) ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++ ++#define MSPI_MIU0_BUS_BASE ARM_MIU0_BUS_BASE ++#define MSPI_MIU1_BUS_BASE ARM_MIU1_BUS_BASE ++ ++#define MSPI_DMA_MODE_MAX 1 ++ ++typedef enum ++{ ++ E_MSPI_OK = 0, ++ E_MSPI_INIT_FLOW_ERROR, ++ E_MSPI_DCCONFIG_ERROR, ++ E_MSPI_CLKCONFIG_ERROR, ++ E_MSPI_FRAMECONFIG_ERROR, ++ E_MSPI_OPERATION_ERROR, ++ E_MSPI_PARAM_OVERFLOW, ++ E_MSPI_MMIO_ERROR, ++ E_MSPI_TIMEOUT, ++ E_MSPI_HW_NOT_SUPPORT, ++ E_MSPI_NOMEM, ++ E_MSPI_NULL, ++ E_MSPI_ERR, ++} MSPI_ErrorNo; ++ ++typedef enum ++{ ++ E_MSPI_OFF = 0, ++ E_MSPI_ON, ++} MSPI_CsState; ++ ++typedef enum ++{ ++ E_MSPI_CS0 = 0, ++ E_MSPI_CS1, ++ E_MSPI_CS2, ++} MSPI_CsChannel; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++static bool gbInitFlag = false; ++ ++#if SSTAR_MSPI_HAL_MUX ++static CamOsMutex_t hal_mspi_lock; ++#define HAL_MSPI_Lock() CamOsMutexLock(&hal_mspi_lock); ++#define HAL_MSPI_Unlock() CamOsMutexUnlock(&hal_mspi_lock); ++#else ++#define HAL_MSPI_Lock() ++#define HAL_MSPI_Unlock() ++#endif ++ ++static void HAL_MSPI_Enable(struct mspi_hal *mspi, bool bEnable) ++{ ++ HAL_MSPI_Lock(); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ HAL_MSPI_Unlock(); ++} ++ ++void HAL_MSPI_select_pad( int pad_ctrl, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_SPI0: ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(MSPI0_MODE<<2), pad_mode << 0, 0x7 << 0); //reg_spi0_mode[2:0] ++ break; ++ case MUX_SPI1: ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(MSPI1_MODE<<2), pad_mode << 4, 0x7 << 4); //reg_spi1_mode[6:4] ++ break; ++ ++ default: ++ break; ++ } ++ ++ if(pad_ctrl==PAD_SPI0_CZ) ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA+(0x0F<<2), 0, 0x02 << 0); //Disable jtag mode // IO PAD conflict turn off jtag ++} ++ ++int HAL_MSPI_get_padmux(int pad_ctrl, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(pad_ctrl) ++ { ++ case PAD_SPI0_CZ: ++ *padmux=MUX_SPI0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_SPI1_CZ: ++ *padmux=MUX_SPI1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ *padmux=MUX_SPI1; ++ *pad_mode=0x4; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} ++ ++static void HAL_MSPI_PadSet(struct mspi_hal *mspi) ++{ ++ u8 padmux; ++ u8 pad_mode; ++ ++ if(HAL_MSPI_get_padmux(mspi->pad_ctrl,&padmux,&pad_mode)==0) ++ { ++ HAL_MSPI_select_pad(mspi->pad_ctrl,padmux,pad_mode); ++ } ++ else ++ { ++ mspi_warnmsg("pad_ctrl err\n"); ++ } ++} ++ ++static void HAL_MSPI_Init(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++#if defined(CONFIG_MS_PADMUX) ++ if (0 == mdrv_padmux_active()) ++#endif ++ { ++ HAL_MSPI_PadSet(mspi); ++ } ++ ++ HAL_MSPI_Unlock(); ++ HAL_MSPI_Enable(mspi,true); ++ gbInitFlag = true; ++} ++ ++static void HAL_MSPI_Reset_DCConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++void HAL_MSPI_SetDcTiming (struct mspi_hal *mspi, eDC_config eDCField, u8 u8DCtiming) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ HAL_MSPI_Unlock(); ++} ++ ++ ++static u8 HAL_DC_TrStartSetting(struct mspi_hal *mspi, u8 TrStart) ++{ ++ u8 u8TrStartMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++ ++ ++static u8 HAL_DC_TrEndSetting(struct mspi_hal *mspi,u8 TrEnd) ++{ ++ u8 u8TrEndMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TREND ,TrEnd); ++ return errnum; ++} ++ ++static u8 HAL_DC_TBSetting(struct mspi_hal *mspi, u8 TB) ++{ ++ u8 u8TBMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TB ,TB); ++ return errnum; ++} ++ ++static u8 HAL_DC_TRWSetting(struct mspi_hal *mspi, u8 TRW) ++{ ++ u8 u8TRWMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRW ,TRW); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_DCConfig(struct mspi_hal *mspi, MSPI_DCConfig *ptDCConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_ERR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(mspi); ++ return E_MSPI_OK; ++ } ++ errnum = HAL_DC_TrStartSetting(mspi,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TrEndSetting(mspi,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TBSetting(mspi,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TRWSetting(mspi,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++static void HAL_MSPI_SetCLKTiming(struct mspi_hal *mspi, eCLK_config eCLKField, u8 u8CLKVal) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eCLKField) ++ { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_Reset_CLKConfig(struct mspi_hal *mspi) ++{ ++ u16 Tempbuf; ++ HAL_MSPI_Lock(); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) ++ { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) ++ { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(mspi); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static void HAL_MSPI_Reset_FrameConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xFFF); ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_SetPerFrameSize(struct mspi_hal *mspi, u8 bDirect, u8 u8BufOffset, u8 u8PerFrameSize) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 u8BitOffset = 0; ++ u16 u16regIndex = 0; ++ ++ HAL_MSPI_Lock(); ++ if(bDirect == MSPI_READ_INDEX) ++ { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } ++ else ++ { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_FRAMEConfig(struct mspi_hal *mspi, MSPI_FrameConfig *ptFrameConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ u8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) ++ { ++ HAL_MSPI_Reset_FrameConfig(mspi); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi, u8 Enable, u8 eSelect) ++{ ++ u16 regdata = 0; ++ u8 bitmask = 0; ++ HAL_MSPI_Lock(); ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) ++ { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } ++ else ++ { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable) ++{ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ HAL_MSPI_Unlock(); ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Config(struct mspi_hal *mspi) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++#if SSTAR_MSPI_HAL_MUX ++ CamOsMutexInit(&hal_mspi_lock); ++#endif ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ HAL_MSPI_Init(mspi); ++ ++ errnum = HAL_MSPI_DCConfig(mspi, &stDCConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_SetMode(mspi, mspimode); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_FRAMEConfig(mspi, &stFrameConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ //MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ HAL_MSPI_ChipSelect(mspi,E_MSPI_OFF,E_MSPI_CS0); ++ errnum = HAL_MSPI_SetLSB(mspi, 0); ++ if(errnum) ++ { ++ return errnum; ++ } ++ return errnum; ++} ++ ++static void HAL_MSPI_RWBUFSize(struct mspi_hal *mspi,u8 Direct, u8 Size) ++{ ++ u16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++ ++#ifndef CONFIG_SPI_INT_CALL ++u8 HAL_MSPI_Trigger(struct mspi_hal *mspi) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&mspi->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ timeout = wait_for_completion_timeout(&mspi->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) ++ { ++ mspi_errmsg("mspi timeout\n"); ++ return E_MSPI_TIMEOUT; ++ } ++ ++ return E_MSPI_OK; ++} ++#else ++u8 HAL_MSPI_Trigger(struct mspi_hal *mspi) ++{ ++ unsigned int timeout = 30000000; ++ u16 done = 0; ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ while(timeout != 0 && !done) ++ { ++ done = MSPI_READ(MSPI_DONE_OFFSET); ++ //udelay(1); ++ timeout--; ++ } ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE); ++ ++ if(!timeout) ++ { ++ printk("mspi timeout\n"); ++ return E_MSPI_TIMEOUT; ++ } ++ ++ return E_MSPI_OK; ++} ++#endif ++static u8 HAL_MSPI_FullDuplexBuf(struct mspi_hal *mspi, u8 *rx_buff, u8 *tx_buff, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Lock(); ++#endif ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = (tx_buff[u8Index] << 8) | tx_buff[u8Index-1]; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),tx_buff[u8Index]); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ rx_buff[u8Index] = u16TempBuf >> 8; ++ rx_buff[u8Index-1] = u16TempBuf & 0xFF; ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ rx_buff[u8Index] = u16TempBuf & 0xFF; ++ } ++ } ++ ++err_out: ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Unlock(); ++#endif ++ return errnum; ++} ++ ++static u8 HAL_MSPI_ReadBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u16 i =0, j = 0; ++ u8 errnum = E_MSPI_OK; ++ ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Lock(); ++#endif ++ ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) ++ { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) ++ { ++ j = MAX_READ_BUF_SIZE; ++ } ++ else ++ { ++ j = u16TempBuf; ++ } ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, j); ++ ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < j; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } ++ else if(u8Index == (j -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ } ++ pData+= j; ++ } ++ ++err_out: ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Unlock(); ++#endif ++ return errnum; ++} ++ ++static u8 HAL_MSPI_WriteBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Lock(); ++#endif ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ // set write data size ++err_out: ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Unlock(); ++#endif ++ return errnum; ++} ++ ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(rx_buff == NULL || tx_buff == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16Index*MAX_READ_BUF_SIZE,tx_buff+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16TempFrameCnt*MAX_READ_BUF_SIZE,tx_buff+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ u32 u32Index = 0; ++ u32 u32TempFrameCnt=0; ++ u32 u32TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u32TempFrameCnt = u32Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u32TempLastFrameCnt = u32Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u32Index = 0; u32Index < u32TempFrameCnt; u32Index++) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u32Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u32TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u32TempFrameCnt*MAX_WRITE_BUF_SIZE,u32TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ u32 u32Index = 0; ++ u32 u32TempFrameCnt=0; ++ u32 u32TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u32TempFrameCnt = u32Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u32TempLastFrameCnt = u32Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u32Index = 0; u32Index < u32TempFrameCnt; u32Index++) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u32Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(u32TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u32TempFrameCnt*MAX_WRITE_BUF_SIZE,u32TempLastFrameCnt); ++ } ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ u8 errnum; ++ u32 data_addr; ++ HalMoveDmaMspi_t tMoveDmaMspi; ++ HalMoveDmaParam_t tMoveDmaParam; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ data_addr = virt_to_phys(pData); ++ if(data_addr > MSPI_MIU1_BUS_BASE) ++ data_addr -= MSPI_MIU1_BUS_BASE; ++ else ++ data_addr -= MSPI_MIU0_BUS_BASE; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_MSPI; ++ tMoveDmaParam.u32SrcAddr = data_addr; ++ tMoveDmaParam.u32SrcMiuSel = (data_addr < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32DstAddr = 0; ++ tMoveDmaParam.u32DstMiuSel = 0; ++ tMoveDmaParam.u32Count = (u32)u32Size; ++ tMoveDmaParam.CallBackFunc = NULL; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ tMoveDmaMspi.u32Direction = HAL_MOVEDMA_WR; ++ tMoveDmaMspi.u32DeviceSelect = u8Channel; ++ tMoveDmaParam.pstMspist = &tMoveDmaMspi; ++ ++ Chip_Flush_Cache_Range((u32)pData, u32Size); ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) ++ { ++ mspi_errmsg("move dma set fail wr\n"); ++ return E_MSPI_ERR; ++ } ++ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_WRITE); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u32Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, u32Size>>16 ); ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, 0); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++err_out: ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x00); ++ HAL_MSPI_Unlock(); ++ return errnum; ++ ++} ++ ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ u8 errnum; ++ u32 data_addr; ++ HalMoveDmaMspi_t tMoveDmaMspi; ++ HalMoveDmaParam_t tMoveDmaParam; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ data_addr = virt_to_phys(pData); ++ if(data_addr > MSPI_MIU1_BUS_BASE) ++ data_addr -= MSPI_MIU1_BUS_BASE; ++ else ++ data_addr -= MSPI_MIU0_BUS_BASE; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_MSPI; ++ tMoveDmaParam.u32SrcAddr = 0; ++ tMoveDmaParam.u32SrcMiuSel = 0; ++ tMoveDmaParam.u32DstAddr = data_addr; ++ tMoveDmaParam.u32DstMiuSel = (data_addr < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32Count = (u32)u32Size; ++ tMoveDmaParam.CallBackFunc = NULL; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ tMoveDmaMspi.u32Direction = HAL_MOVEDMA_RD; ++ tMoveDmaMspi.u32DeviceSelect = u8Channel; ++ tMoveDmaParam.pstMspist = &tMoveDmaMspi; ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) ++ { ++ mspi_errmsg("move dma set fail rd\n"); ++ return E_MSPI_ERR; ++ } ++ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_READ); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u32Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, (u32Size>>16)& 0x00FF); // 24bit ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, 0); //spi length = 0 ++ Chip_Inv_Cache_Range((u32)pData, u32Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ Chip_Inv_Cache_Range((u32)pData, u32Size); ++ ++err_out: ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x00); ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi) ++{ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++ ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi) ++{ ++ MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE); ++} ++ ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div) ++{ ++ u16 TempData = 0; ++ ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= div << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel) ++{ ++ if(u8Channel > MSPI_DMA_MODE_MAX) ++ { ++ return E_MSPI_HW_NOT_SUPPORT; ++ } ++ else ++ { ++ return E_MSPI_OK; ++ } ++} ++ +diff --git a/drivers/sstar/mspi/infinity6b0/hal_mspi.h b/drivers/sstar/mspi/infinity6b0/hal_mspi.h +new file mode 100755 +index 000000000000..3cc415a6fe04 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6b0/hal_mspi.h +@@ -0,0 +1,60 @@ ++/* ++* hal_mspi.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_H__ ++#define __MHAL_MSPI_H__ ++ ++#define MSPI_MAX_SUPPORT_BITS 16 ++ ++struct mspi_hal ++{ ++ u32 mspi_base; ++ u32 pad_ctrl; ++ u32 bits_per_word; ++ struct completion done; ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel); ++u8 HAL_MSPI_Config(struct mspi_hal *mspi); ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi); ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi); ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable); ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div); ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode); ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi,u8 Enable ,u8 eSelect); ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size); ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity6b0/hal_mspireg.h b/drivers/sstar/mspi/infinity6b0/hal_mspireg.h +new file mode 100755 +index 000000000000..b2b54f523ff5 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6b0/hal_mspireg.h +@@ -0,0 +1,95 @@ ++/* ++* hal_mspireg.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_REG_H__ ++#define __MHAL_MSPI_REG_H__ ++ ++#define MUX_SPI0 0 ++#define MUX_SPI1 1 ++ ++#define EJTAG_MODE 0x0F ++#define MSPI0_MODE 0x0C //bit0~bit1 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_OFFSET 0x78 ++ ++//chip select bit map ++#define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++//spi dma ++#define MSPI_DMA_DATA_LENGTH_L 0x30 ++#define MSPI_DMA_DATA_LENGTH_H 0x31 ++#define MSPI_DMA_ENABLE 0x32 ++#define MSPI_DMA_RW_MODE 0x33 ++ #define MSPI_DMA_WRITE 0x00 ++ #define MSPI_DMA_READ 0x01 ++ ++#define MSPI_CLK_DIV_VAL {2, 4, 8, 16, 32, 64, 128, 256} ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity6e/hal_mspi.c b/drivers/sstar/mspi/infinity6e/hal_mspi.c +new file mode 100755 +index 000000000000..8e21e24429b7 +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6e/hal_mspi.c +@@ -0,0 +1,1104 @@ ++/* ++* hal_mspi.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hal_mspi.h" ++#include "hal_mspireg.h" ++ ++#define SSTAR_MSPI_HAL_MUX 0 ++ ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk("[MSPI] : " args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++#define mspi_errmsg(fmt, ...) printk(KERN_ERR "[MSPI] error : " fmt, ##__VA_ARGS__) ++#define mspi_warnmsg(fmt, ...) printk(KERN_ERR "[MSPI] warning : " fmt, ##__VA_ARGS__) ++ ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define WRITE_WORD(_reg, _val) (*((volatile u16*)(_reg))) = (u16)(_val) ++ ++#define MSPI_READ(_reg_) READ_WORD(mspi->mspi_base + ((_reg_)<<2)) ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(mspi->mspi_base + ((_reg_)<<2), (_val_)) ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(mspi->mspi_base + ((_reg_)<<2), (_val_), (mask)) ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++ ++#define MSPI_MIU0_BUS_BASE ARM_MIU0_BUS_BASE ++#define MSPI_MIU1_BUS_BASE ARM_MIU1_BUS_BASE ++ ++#define MSPI_DMA_MODE_MAX 1 ++ ++typedef enum ++{ ++ E_MSPI_OK = 0, ++ E_MSPI_INIT_FLOW_ERROR, ++ E_MSPI_DCCONFIG_ERROR, ++ E_MSPI_CLKCONFIG_ERROR, ++ E_MSPI_FRAMECONFIG_ERROR, ++ E_MSPI_OPERATION_ERROR, ++ E_MSPI_PARAM_OVERFLOW, ++ E_MSPI_MMIO_ERROR, ++ E_MSPI_TIMEOUT, ++ E_MSPI_HW_NOT_SUPPORT, ++ E_MSPI_NOMEM, ++ E_MSPI_NULL, ++ E_MSPI_ERR, ++} MSPI_ErrorNo; ++ ++typedef enum ++{ ++ E_MSPI_OFF = 0, ++ E_MSPI_ON, ++} MSPI_CsState; ++ ++typedef enum ++{ ++ E_MSPI_CS0 = 0, ++ E_MSPI_CS1, ++ E_MSPI_CS2, ++} MSPI_CsChannel; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++static bool gbInitFlag = false; ++ ++#if SSTAR_MSPI_HAL_MUX ++static CamOsMutex_t hal_mspi_lock; ++#define HAL_MSPI_Lock() CamOsMutexLock(&hal_mspi_lock); ++#define HAL_MSPI_Unlock() CamOsMutexUnlock(&hal_mspi_lock); ++#else ++#define HAL_MSPI_Lock() ++#define HAL_MSPI_Unlock() ++#endif ++ ++static void HAL_MSPI_Enable(struct mspi_hal *mspi, bool bEnable) ++{ ++ HAL_MSPI_Lock(); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_Init(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ HAL_MSPI_Unlock(); ++ HAL_MSPI_Enable(mspi,true); ++ gbInitFlag = true; ++} ++ ++static void HAL_MSPI_Reset_DCConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++void HAL_MSPI_SetDcTiming (struct mspi_hal *mspi, eDC_config eDCField, u8 u8DCtiming) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ HAL_MSPI_Unlock(); ++} ++ ++ ++static u8 HAL_DC_TrStartSetting(struct mspi_hal *mspi, u8 TrStart) ++{ ++ u8 u8TrStartMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++ ++ ++static u8 HAL_DC_TrEndSetting(struct mspi_hal *mspi,u8 TrEnd) ++{ ++ u8 u8TrEndMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TREND ,TrEnd); ++ return errnum; ++} ++ ++static u8 HAL_DC_TBSetting(struct mspi_hal *mspi, u8 TB) ++{ ++ u8 u8TBMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TB ,TB); ++ return errnum; ++} ++ ++static u8 HAL_DC_TRWSetting(struct mspi_hal *mspi, u8 TRW) ++{ ++ u8 u8TRWMax; ++ u8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(mspi,E_MSPI_TRW ,TRW); ++ return errnum; ++} ++ ++static u8 HAL_MSPI_DCConfig(struct mspi_hal *mspi, MSPI_DCConfig *ptDCConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_ERR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(mspi); ++ return E_MSPI_OK; ++ } ++ errnum = HAL_DC_TrStartSetting(mspi,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TrEndSetting(mspi,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TBSetting(mspi,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = HAL_DC_TRWSetting(mspi,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++static void HAL_MSPI_SetCLKTiming(struct mspi_hal *mspi, eCLK_config eCLKField, u8 u8CLKVal) ++{ ++ u16 u16TempBuf = 0; ++ HAL_MSPI_Lock(); ++ switch(eCLKField) ++ { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_Reset_CLKConfig(struct mspi_hal *mspi) ++{ ++ u16 Tempbuf; ++ HAL_MSPI_Lock(); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) ++ { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) ++ { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(mspi, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(mspi); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static void HAL_MSPI_Reset_FrameConfig(struct mspi_hal *mspi) ++{ ++ HAL_MSPI_Lock(); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xFFF); ++ HAL_MSPI_Unlock(); ++} ++ ++static void HAL_MSPI_SetPerFrameSize(struct mspi_hal *mspi, u8 bDirect, u8 u8BufOffset, u8 u8PerFrameSize) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 u8BitOffset = 0; ++ u16 u16regIndex = 0; ++ ++ HAL_MSPI_Lock(); ++ if(bDirect == MSPI_READ_INDEX) ++ { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } ++ else ++ { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ HAL_MSPI_Unlock(); ++} ++ ++static u8 HAL_MSPI_FRAMEConfig(struct mspi_hal *mspi, MSPI_FrameConfig *ptFrameConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ u8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) ++ { ++ HAL_MSPI_Reset_FrameConfig(mspi); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(mspi, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi, u8 Enable, u8 eSelect) ++{ ++ u16 regdata = 0; ++ u8 bitmask = 0; ++ HAL_MSPI_Lock(); ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) ++ { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } ++ else ++ { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++ HAL_MSPI_Unlock(); ++} ++ ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable) ++{ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ HAL_MSPI_Unlock(); ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Config(struct mspi_hal *mspi) ++{ ++ u8 errnum = E_MSPI_OK; ++ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++#if SSTAR_MSPI_HAL_MUX ++ CamOsMutexInit(&hal_mspi_lock); ++#endif ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ HAL_MSPI_Init(mspi); ++ ++ errnum = HAL_MSPI_DCConfig(mspi, &stDCConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_SetMode(mspi, mspimode); ++ if(errnum) ++ { ++ return errnum; ++ } ++ ++ errnum = HAL_MSPI_FRAMEConfig(mspi, &stFrameConfig); ++ if(errnum) ++ { ++ return errnum; ++ } ++ //MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ HAL_MSPI_ChipSelect(mspi,E_MSPI_OFF,E_MSPI_CS0); ++ errnum = HAL_MSPI_SetLSB(mspi, 0); ++ if(errnum) ++ { ++ return errnum; ++ } ++ return errnum; ++} ++ ++static void HAL_MSPI_RWBUFSize(struct mspi_hal *mspi,u8 Direct, u8 Size) ++{ ++ u16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++ ++#ifndef CONFIG_SPI_INT_CALL ++u8 HAL_MSPI_Trigger(struct mspi_hal *mspi) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&mspi->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ timeout = wait_for_completion_timeout(&mspi->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) ++ { ++ mspi_errmsg("mspi timeout\n"); ++ return E_MSPI_TIMEOUT; ++ } ++ ++ return E_MSPI_OK; ++} ++#else ++u8 HAL_MSPI_Trigger(struct mspi_hal *mspi) ++{ ++ unsigned int timeout = 30000000; ++ u16 done = 0; ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ while(timeout != 0 && !done) ++ { ++ done = MSPI_READ(MSPI_DONE_OFFSET); ++ //udelay(1); ++ timeout--; ++ } ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE); ++ ++ if(!timeout) ++ { ++ printk("mspi timeout\n"); ++ return E_MSPI_TIMEOUT; ++ } ++ ++ return E_MSPI_OK; ++} ++#endif ++static u8 HAL_MSPI_FullDuplexBuf(struct mspi_hal *mspi, u8 *rx_buff, u8 *tx_buff, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ u8 shift; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & BIT0); ++ ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Lock(); ++#endif ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ if(mspi->bits_per_word <= 8) ++ { ++ shift = (isMsbBitMode) ? (8 - mspi->bits_per_word) : 0; ++ u16TempBuf = (tx_buff[u8Index] << (shift + 8)) | (tx_buff[u8Index-1] << shift); ++ } ++ else ++ { ++ shift = 16 - mspi->bits_per_word; ++ if(isMsbBitMode) ++ { ++ u16TempBuf = (tx_buff[u8Index] << shift) | (tx_buff[u8Index-1] << 8); ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ shift = (isMsbBitMode) ? (8 - mspi->bits_per_word) : 0; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),tx_buff[u8Index] << shift); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ if (isMsbBitMode) ++ { ++ if (mspi->bits_per_word <= 8) ++ { ++ shift = mspi->bits_per_word; ++ rx_buff[u8Index] = (u16TempBuf >> 8) & ((0x1 << shift) - 0x1); ++ rx_buff[u8Index-1] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ else //bits_per_word=9~15 ++ { ++ shift = mspi->bits_per_word - 8; ++ rx_buff[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ rx_buff[u8Index-1] = u16TempBuf >> 8; ++ } ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_FULL_DEPLUX_OFFSET + (u8Index >> 1))); ++ shift = mspi->bits_per_word; ++ rx_buff[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ } ++ ++err_out: ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Unlock(); ++#endif ++ return errnum; ++} ++ ++static u8 HAL_MSPI_ReadBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u16 i =0, j = 0; ++ u8 errnum = E_MSPI_OK; ++ u8 shift; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & BIT0); ++ ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Lock(); ++#endif ++ ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) ++ { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) ++ { ++ j = MAX_READ_BUF_SIZE; ++ } ++ else ++ { ++ j = u16TempBuf; ++ } ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, j); ++ ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ for(u8Index = 0; u8Index < j; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ if (isMsbBitMode) ++ { ++ //MSB MODE ++ if (mspi->bits_per_word <= 8) ++ { ++ //printk("u16TempBuf 0x%x\n",u16TempBuf); ++ shift = mspi->bits_per_word; ++ pData[u8Index] = (u16TempBuf >> 8) & ((0x1 << shift) - 0x1); ++ pData[u8Index-1] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ else //bits_per_word=9~15 ++ { ++ shift = mspi->bits_per_word - 8; ++ pData[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ pData[u8Index-1] = u16TempBuf >> 8; ++ } ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ else if(u8Index == (j -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ shift = mspi->bits_per_word; ++ pData[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ } ++ pData+= j; ++ } ++ ++err_out: ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Unlock(); ++#endif ++ return errnum; ++} ++ ++static u8 HAL_MSPI_WriteBuf(struct mspi_hal *mspi, u8 *pData, u16 u16Size) ++{ ++ u8 u8Index = 0; ++ u16 u16TempBuf = 0; ++ u8 errnum = E_MSPI_OK; ++ u8 shift = 0; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & BIT0); ++ ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Lock(); ++#endif ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ if(mspi->bits_per_word <= 8) ++ { ++ shift = (isMsbBitMode) ? (8 - mspi->bits_per_word) : 0; ++ u16TempBuf = (pData[u8Index] << (shift + 8)) | (pData[u8Index-1] << shift); ++ } ++ else ++ { ++ shift = 16 - mspi->bits_per_word; ++ if(isMsbBitMode) ++ { ++ u16TempBuf = (pData[u8Index] << shift) | (pData[u8Index-1] << 8); ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ shift = 8 - mspi->bits_per_word; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index] << shift); ++ } ++ } ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, u16Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ // set write data size ++err_out: ++#ifndef CONFIG_SPI_INT_CALL ++ HAL_MSPI_Unlock(); ++#endif ++ return errnum; ++} ++ ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size) ++{ ++ u16 u16Index = 0; ++ u16 u16TempFrameCnt=0; ++ u16 u16TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(rx_buff == NULL || tx_buff == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u16TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u16TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u16Index = 0; u16Index < u16TempFrameCnt; u16Index++) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16Index*MAX_READ_BUF_SIZE,tx_buff+u16Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u16TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_FullDuplexBuf(mspi,rx_buff+u16TempFrameCnt*MAX_READ_BUF_SIZE,tx_buff+u16TempFrameCnt*MAX_WRITE_BUF_SIZE,u16TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ u32 u32Index = 0; ++ u32 u32TempFrameCnt=0; ++ u32 u32TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u32TempFrameCnt = u32Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u32TempLastFrameCnt = u32Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ ++ for (u32Index = 0; u32Index < u32TempFrameCnt; u32Index++) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u32Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(u32TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_WriteBuf(mspi,pData+u32TempFrameCnt*MAX_WRITE_BUF_SIZE,u32TempLastFrameCnt); ++ } ++ ++ if (ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ u32 u32Index = 0; ++ u32 u32TempFrameCnt=0; ++ u32 u32TempLastFrameCnt=0; ++ u8 ret = E_MSPI_OK; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ u32TempFrameCnt = u32Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ u32TempLastFrameCnt = u32Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u32Index = 0; u32Index < u32TempFrameCnt; u32Index++) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u32Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(u32TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_ReadBuf(mspi,pData+u32TempFrameCnt*MAX_WRITE_BUF_SIZE,u32TempLastFrameCnt); ++ } ++ if (ret) ++ { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ u8 errnum; ++ u32 data_addr; ++ HalMoveDmaMspi_t tMoveDmaMspi; ++ HalMoveDmaParam_t tMoveDmaParam; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ data_addr = virt_to_phys(pData); ++ if(data_addr > MSPI_MIU1_BUS_BASE) ++ data_addr -= MSPI_MIU1_BUS_BASE; ++ else ++ data_addr -= MSPI_MIU0_BUS_BASE; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_MSPI; ++ tMoveDmaParam.u32SrcAddr = data_addr; ++ tMoveDmaParam.u32SrcMiuSel = (data_addr < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32DstAddr = 0; ++ tMoveDmaParam.u32DstMiuSel = 0; ++ tMoveDmaParam.u32Count = (u32)u32Size; ++ tMoveDmaParam.CallBackFunc = NULL; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ tMoveDmaMspi.u32Direction = HAL_MOVEDMA_WR; ++ tMoveDmaMspi.u32DeviceSelect = u8Channel; ++ tMoveDmaParam.pstMspist = &tMoveDmaMspi; ++ ++ Chip_Flush_Cache_Range((u32)pData, u32Size); ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) ++ { ++ mspi_errmsg("move dma set fail wr\n"); ++ return E_MSPI_ERR; ++ } ++ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_WRITE); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u32Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, u32Size>>16 ); ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_WRITE_INDEX, 0); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++err_out: ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x00); ++ HAL_MSPI_Unlock(); ++ return errnum; ++ ++} ++ ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size) ++{ ++ u8 errnum; ++ u32 data_addr; ++ HalMoveDmaMspi_t tMoveDmaMspi; ++ HalMoveDmaParam_t tMoveDmaParam; ++ ++ if(pData == NULL) ++ { ++ return E_MSPI_NULL; ++ } ++ ++ data_addr = virt_to_phys(pData); ++ if(data_addr > MSPI_MIU1_BUS_BASE) ++ data_addr -= MSPI_MIU1_BUS_BASE; ++ else ++ data_addr -= MSPI_MIU0_BUS_BASE; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_MSPI; ++ tMoveDmaParam.u32SrcAddr = 0; ++ tMoveDmaParam.u32SrcMiuSel = 0; ++ tMoveDmaParam.u32DstAddr = data_addr; ++ tMoveDmaParam.u32DstMiuSel = (data_addr < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32Count = (u32)u32Size; ++ tMoveDmaParam.CallBackFunc = NULL; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ tMoveDmaMspi.u32Direction = HAL_MOVEDMA_RD; ++ tMoveDmaMspi.u32DeviceSelect = u8Channel; ++ tMoveDmaParam.pstMspist = &tMoveDmaMspi; ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) ++ { ++ mspi_errmsg("move dma set fail rd\n"); ++ return E_MSPI_ERR; ++ } ++ ++ HAL_MSPI_Lock(); ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_READ); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u32Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, (u32Size>>16)& 0x00FF); // 24bit ++ ++ HAL_MSPI_RWBUFSize(mspi,MSPI_READ_INDEX, 0); //spi length = 0 ++ Chip_Inv_Cache_Range((u32)pData, u32Size); ++ errnum = HAL_MSPI_Trigger(mspi); ++ if(errnum) ++ { ++ goto err_out; ++ } ++ ++ Chip_Inv_Cache_Range((u32)pData, u32Size); ++ ++err_out: ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x00); ++ HAL_MSPI_Unlock(); ++ return errnum; ++} ++ ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi) ++{ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++ ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi) ++{ ++ MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE); ++} ++ ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div) ++{ ++ u16 TempData = 0; ++ ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= div << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return E_MSPI_OK; ++} ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel) ++{ ++ if(u8Channel > MSPI_DMA_MODE_MAX) ++ { ++ return E_MSPI_HW_NOT_SUPPORT; ++ } ++ else ++ { ++ return E_MSPI_OK; ++ } ++} ++ ++u8 HAL_MSPI_SET_FRAMECFG(struct mspi_hal *mspi, int bits_per_word) ++{ ++ MSPI_FrameConfig stFrameConfig; ++ int i; ++ ++ if (bits_per_word > MSPI_MAX_SUPPORT_BITS) ++ { ++ return -EINVAL; ++ } ++ else if (bits_per_word > 8) ++ { ++ for (i = 0; i < MAX_WRITE_BUF_SIZE; i+=2) ++ { ++ stFrameConfig.u8WBitConfig[i] = bits_per_word - 8 -1; ++ stFrameConfig.u8WBitConfig[i+1] = 8 -1; ++ } ++ for (i = 0; i < MAX_READ_BUF_SIZE; i+=2) ++ { ++ stFrameConfig.u8RBitConfig[i] = bits_per_word - 8 -1; ++ stFrameConfig.u8RBitConfig[i+1] = 8 -1; ++ } ++ } ++ else ++ { ++ for (i = 0; i < MAX_WRITE_BUF_SIZE; i++) ++ { ++ stFrameConfig.u8WBitConfig[i] = bits_per_word -1; ++ } ++ for (i = 0; i < MAX_READ_BUF_SIZE; i++) ++ { ++ stFrameConfig.u8RBitConfig[i] = bits_per_word -1; ++ } ++ } ++ HAL_MSPI_FRAMEConfig(mspi,&stFrameConfig); ++ ++ return 0; ++} ++ ++ +diff --git a/drivers/sstar/mspi/infinity6e/hal_mspi.h b/drivers/sstar/mspi/infinity6e/hal_mspi.h +new file mode 100755 +index 000000000000..bd6739f08bca +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6e/hal_mspi.h +@@ -0,0 +1,61 @@ ++/* ++* hal_mspi.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_H__ ++#define __MHAL_MSPI_H__ ++ ++#define MSPI_MAX_SUPPORT_BITS 16 ++ ++struct mspi_hal ++{ ++ u32 mspi_base; ++ u32 pad_ctrl; ++ u32 bits_per_word; ++ struct completion done; ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++u8 HAL_MSPI_CheckDmaMode(u8 u8Channel); ++u8 HAL_MSPI_Config(struct mspi_hal *mspi); ++u16 HAL_MSPI_CheckDone(struct mspi_hal *mspi); ++void HAL_MSPI_ClearDone(struct mspi_hal *mspi); ++u8 HAL_MSPI_SetLSB(struct mspi_hal *mspi, u8 enable); ++u8 HAL_MSPI_SetDivClk(struct mspi_hal *mspi, u8 div); ++u8 HAL_MSPI_SetMode(struct mspi_hal *mspi, MSPI_Mode_Config_e eMode); ++void HAL_MSPI_ChipSelect(struct mspi_hal *mspi,u8 Enable ,u8 eSelect); ++u8 HAL_MSPI_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_Write(u8 u8Channel ,struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_DMA_Write(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_DMA_Read(u8 u8Channel, struct mspi_hal *mspi, u8 *pData, u32 u32Size); ++u8 HAL_MSPI_FullDuplex(u8 u8Channel ,struct mspi_hal * mspi, u8 * rx_buff, u8 * tx_buff, u16 u16Size); ++u8 HAL_MSPI_SET_FRAMECFG(struct mspi_hal *mspi, int bits_per_word); ++ ++#endif ++ +diff --git a/drivers/sstar/mspi/infinity6e/hal_mspireg.h b/drivers/sstar/mspi/infinity6e/hal_mspireg.h +new file mode 100755 +index 000000000000..77fc7ae0927e +--- /dev/null ++++ b/drivers/sstar/mspi/infinity6e/hal_mspireg.h +@@ -0,0 +1,88 @@ ++/* ++* hal_mspireg.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++ ++#ifndef __MHAL_MSPI_REG_H__ ++#define __MHAL_MSPI_REG_H__ ++ ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_OFFSET 0x78 ++ ++//chip select bit map ++#define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++//spi dma ++#define MSPI_DMA_DATA_LENGTH_L 0x30 ++#define MSPI_DMA_DATA_LENGTH_H 0x31 ++#define MSPI_DMA_ENABLE 0x32 ++#define MSPI_DMA_RW_MODE 0x33 ++ #define MSPI_DMA_WRITE 0x00 ++ #define MSPI_DMA_READ 0x01 ++ ++#define MSPI_CLK_DIV_VAL {2, 4, 8, 16, 32, 64, 128, 256} ++ ++#endif ++ +diff --git a/drivers/sstar/msys/Kconfig b/drivers/sstar/msys/Kconfig +new file mode 100755 +index 000000000000..562b1f3f9152 +--- /dev/null ++++ b/drivers/sstar/msys/Kconfig +@@ -0,0 +1,33 @@ ++config MS_MSYS ++ bool "msys api" ++ default y ++ ++config MS_ZEN ++ bool ++ depends on MS_MSYS ++ default y ++ ++config MS_MSYS_LOG ++ bool "Log Redirection" ++ depends on MS_MSYS ++ default n ++ ++config MSYS_PERF_TEST ++ bool "sysfs:perf test" ++ depends on MS_MSYS ++ default n ++ ++config MSYS_BENCH_MEMORY_FUNC ++ bool "ioctl:bench memory function" ++ depends on MS_MSYS ++ default n ++ ++config MSYS_MIU_PROTECT ++ bool "sysfs:MIU protest" ++ depends on MS_MSYS ++ default n ++ ++config MSYS_DMEM_SYSFS_ALL ++ bool "add more dmem sysfs node" ++ depends on MS_MSYS ++ default n +diff --git a/drivers/sstar/msys/Makefile b/drivers/sstar/msys/Makefile +new file mode 100755 +index 000000000000..70fc3332a3d5 +--- /dev/null ++++ b/drivers/sstar/msys/Makefile +@@ -0,0 +1,22 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/crypto/infinity ++EXTRA_CFLAGS += -Idrivers/sstar/bdma/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/movedma/ ++ ++obj-$(CONFIG_MS_MSYS) = ms_msys.o ++obj-$(CONFIG_MS_MSYS) += ms_msys_dma_wrapper.o ++obj-$(CONFIG_MSYS_PERF_TEST) += ms_msys_perf_test.o ++obj-$(CONFIG_MS_MSYS) += $(CONFIG_SSTAR_CHIP_NAME)/platform_msys.o ++obj-$(CONFIG_MS_MSYS_LOG) += ms_msys_log.o ++obj-$(CONFIG_MSYS_BENCH_MEMORY_FUNC) += ms_msys_memory_bench.o ++obj-$(CONFIG_MSYS_MIU_PROTECT) += ms_msys_miu_protect.o ++obj-$(CONFIG_MP_IRQ_TRACE) += ms_msys_irq_stat.o ++ ++ ++ifneq ($(CONFIG_THUMB2_KERNEL),y) ++ obj-$(CONFIG_MS_MSYS) += memcpy.o ++endif +diff --git a/drivers/sstar/msys/arm.include b/drivers/sstar/msys/arm.include +new file mode 100755 +index 000000000000..90f865e05e80 +--- /dev/null ++++ b/drivers/sstar/msys/arm.include +@@ -0,0 +1,133 @@ ++//* ++//* $Id: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/include/arm.include#1 $ ++//* $Header: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/include/arm.include#1 $ ++//* $Date: 2015/05/27 $ ++//* $DateTime: 2015/05/27 17:11:47 $ ++//* $Change: 1236156 $ ++//* $File: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/include/arm.include $ ++//* $Revision: #1 $ ++//* ++ ++ ++//======================= ++//ARM modes ++//======================= ++.equ MODE_USR_32, 0x10 //USR mode ++.equ MODE_FIQ_32, 0x11 //FIQ mode ++.equ MODE_IRQ_32, 0x12 //IRQ mode ++.equ MODE_SVC_32, 0x13 //SVC mode ++.equ MODE_ABT_32, 0x17 //ABORT mode ++.equ MODE_UND_32, 0x1B //UNDEF mode ++.equ MODE_SYS_32, 0x1F ++ ++.equ Mode_mask, 0x1F // mask to handle the processor modes ++ ++ ++.equ Mode_IRQ_MIRQ, 0x92 // Mode IRQ and Mask IRQ ++.equ Mode_SVC_MIRQ, 0x93 // Mode SVC and Mask IRQ ++.equ Mode_SVC_UIRQ, 0x13 // Mode SVC and UnMask IRQ ++.equ Mode_SVC_MIRQ_MFIQ,0xD3 // Mode SVC, Mask IRQ, Mask FIQ ++.equ Mode_SVC, 0x13 // SVC mode ++ ++.equ MODE_BITS, 0x1F ++ ++.equ TBIT, 0x20 ++.equ FBIT, 0x40 ++.equ IBIT, 0x80 ++ ++ ++.equ T_Bit, 0x20 // Thumb enable bit ++.equ I_Bit, 0x80 // IRQ disable bit ++.equ F_Bit, 0x40 // FIQ disable bit ++//======================= ++//ARM interrupts ++//======================= ++.equ INTERRUPT_BITS, 0xC0 ++ ++.equ ENABLE_IRQ, 0x0 ++.equ ENABLE_FIQ, 0x0 ++.equ DISABLE_FIQ, 0x40 ++.equ DISABLE_IRQ, 0x80 ++ ++//======================= ++//ARM fLAGs ++//======================= ++.equ FLAG_BITS, 0xF0000000 ++ ++.equ NFLAG, 0x80000000 ++.equ ZFLAG, 0x40000000 ++.equ CFLAG, 0x20000000 ++.equ VFLAG, 0x10000000 ++ ++ ++.equ SVC_SWI, 0x00 // SWI to enter in SVC mode ++ ++.equ ERROR_UNDEF, 0x01 ++.equ ERROR_SWI, 0x02 ++.equ ERROR_PREFETCH, 0x03 ++.equ ERROR_ABT, 0x04 ++.equ ERROR_IRQ, 0x05 ++.equ ERROR_FIQ, 0x06 ++.equ ERROR_BOOT_FAIL, 0x07 ++ ++ ++ ++ ++#ifdef __ELF__ ++# define _C_LABEL(x) x ++#else ++# ifdef __STDC__ ++# define _C_LABEL(x) _ ## x ++# else ++# define _C_LABEL(x) _/**/x ++# endif ++#endif ++#define _ASM_LABEL(x) x ++ ++#ifdef __STDC__ ++# define __CONCAT(x,y) x ## y ++# define __STRING(x) #x ++#else ++# define __CONCAT(x,y) x/**/y ++# define __STRING(x) "x" ++#endif ++ ++#ifndef _ALIGN_TEXT ++# define _ALIGN_TEXT .align 0 ++#endif ++ ++/* ++ * gas/arm uses @ as a single comment character and thus cannot be used here ++ * Instead it recognised the # instead of an @ symbols in .type directives ++ * We define a couple of macros so that assembly code will not be dependant ++ * on one or the other. ++ */ ++#define _ASM_TYPE_FUNCTION #function ++#define _ASM_TYPE_OBJECT #object ++#define _ENTRY(x) \ ++ .text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x: .fnstart ++ ++#define _ASM_SIZE(x) .size x, .-x; ++ ++#define _END(x) \ ++ .fnend; \ ++ _ASM_SIZE(x) ++ ++#ifdef GPROF ++# ifdef __ELF__ ++# define _PROF_PROLOGUE \ ++ mov ip, lr; bl __mcount ++# else ++# define _PROF_PROLOGUE \ ++ mov ip,lr; bl mcount ++# endif ++#else ++# define _PROF_PROLOGUE ++#endif ++ ++#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE ++#define ENTRY_NP(y) _ENTRY(_C_LABEL(y)) ++#define END(y) _END(_C_LABEL(y)) ++#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE ++#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y)) ++#define ASEND(y) _END(_ASM_LABEL(y)) +\ No newline at end of file +diff --git a/drivers/sstar/msys/infinity2/platform_msys.c b/drivers/sstar/msys/infinity2/platform_msys.c +new file mode 100755 +index 000000000000..24b41edeb504 +--- /dev/null ++++ b/drivers/sstar/msys/infinity2/platform_msys.c +@@ -0,0 +1,72 @@ ++/* ++* platform_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "ms_platform.h" ++#include "gpio.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info) ++{ ++ if(freq_info->padnum != PAD_CLOCK_OUT) ++ { ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bEnable) ++ { ++ if(freq_info->freq != FREQ_24MHZ) ++ { ++ MSYS_ERROR("Not implement FREQ: %d for this platform\n", freq_info->freq); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bInvert != false) ++ MSYS_WARN("Not support invert clock in this platform"); ++ ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=0 ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1);//enable clock ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ else //disable clk ++ { ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=1 ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1); //disable clk ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/msys/infinity2m/platform_msys.c b/drivers/sstar/msys/infinity2m/platform_msys.c +new file mode 100644 +index 000000000000..24b41edeb504 +--- /dev/null ++++ b/drivers/sstar/msys/infinity2m/platform_msys.c +@@ -0,0 +1,72 @@ ++/* ++* platform_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "ms_platform.h" ++#include "gpio.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info) ++{ ++ if(freq_info->padnum != PAD_CLOCK_OUT) ++ { ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bEnable) ++ { ++ if(freq_info->freq != FREQ_24MHZ) ++ { ++ MSYS_ERROR("Not implement FREQ: %d for this platform\n", freq_info->freq); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bInvert != false) ++ MSYS_WARN("Not support invert clock in this platform"); ++ ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=0 ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1);//enable clock ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ else //disable clk ++ { ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=1 ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1); //disable clk ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/msys/infinity5/platform_msys.c b/drivers/sstar/msys/infinity5/platform_msys.c +new file mode 100644 +index 000000000000..0c9c43e7a548 +--- /dev/null ++++ b/drivers/sstar/msys/infinity5/platform_msys.c +@@ -0,0 +1,34 @@ ++/* ++* platform_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include "ms_platform.h" ++#include "gpio.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info) ++{ ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ MSYS_ERROR("%s not support for this platform\n", __FUNCTION__); ++ return -EPERM; ++} +diff --git a/drivers/sstar/msys/infinity6/platform_msys.c b/drivers/sstar/msys/infinity6/platform_msys.c +new file mode 100644 +index 000000000000..4ecad97330e6 +--- /dev/null ++++ b/drivers/sstar/msys/infinity6/platform_msys.c +@@ -0,0 +1,72 @@ ++/* ++* platform_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "ms_platform.h" ++#include "gpio.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info) ++{ ++ if(freq_info->padnum != PAD_CLOCK_OUT) ++ { ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bEnable) ++ { ++ if(freq_info->freq != FREQ_24MHZ) ++ { ++ MSYS_ERROR("Not implement FREQ: %d for this platform\n", freq_info->freq); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bInvert != false) ++ MSYS_WARN("Not support invert clock in this platform"); ++ ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=0 ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1);//enable clock ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ else //disable clk ++ { ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=1 ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1); //disable clk ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/msys/infinity6b0/platform_msys.c b/drivers/sstar/msys/infinity6b0/platform_msys.c +new file mode 100755 +index 000000000000..4ecad97330e6 +--- /dev/null ++++ b/drivers/sstar/msys/infinity6b0/platform_msys.c +@@ -0,0 +1,72 @@ ++/* ++* platform_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "ms_platform.h" ++#include "gpio.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info) ++{ ++ if(freq_info->padnum != PAD_CLOCK_OUT) ++ { ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bEnable) ++ { ++ if(freq_info->freq != FREQ_24MHZ) ++ { ++ MSYS_ERROR("Not implement FREQ: %d for this platform\n", freq_info->freq); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bInvert != false) ++ MSYS_WARN("Not support invert clock in this platform"); ++ ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=0 ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1);//enable clock ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ else //disable clk ++ { ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=1 ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_30, BIT1); //disable clk ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/msys/infinity6e/platform_msys.c b/drivers/sstar/msys/infinity6e/platform_msys.c +new file mode 100755 +index 000000000000..faeef1ed75ee +--- /dev/null ++++ b/drivers/sstar/msys/infinity6e/platform_msys.c +@@ -0,0 +1,72 @@ ++/* ++* platform_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include "ms_platform.h" ++#include "gpio.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info) ++{ ++ if(freq_info->padnum != PAD_CLOCK_OUT) ++ { ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bEnable) ++ { ++ if(freq_info->freq != FREQ_24MHZ) ++ { ++ MSYS_ERROR("Not implement FREQ: %d for this platform\n", freq_info->freq); ++ return -EINVAL; ++ } ++ ++ if(freq_info->bInvert != false) ++ MSYS_WARN("Not support invert clock in this platform"); ++ ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=0 ++ CLRREG16(BASE_REG_XTAL_ATOP_PA + REG_ID_06, BIT0);//enable clock ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ else //disable clk ++ { ++ switch(freq_info->padnum) ++ { ++ case PAD_CLOCK_OUT: ++ // reg_ext_xtali_se_enb[1]=1 ++ SETREG16(BASE_REG_XTAL_ATOP_PA + REG_ID_06, BIT1); //disable clk ++ break; ++ default: ++ MSYS_ERROR("Not implement PAD: %d for this platform\n", freq_info->padnum); ++ break; ++ } ++ } ++ return 0; ++} +diff --git a/drivers/sstar/msys/macro.include b/drivers/sstar/msys/macro.include +new file mode 100755 +index 000000000000..bd2e3d80fb60 +--- /dev/null ++++ b/drivers/sstar/msys/macro.include +@@ -0,0 +1,102 @@ ++//* ++//* $Id: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/include/macro.include#1 $ ++//* $Header: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/include/macro.include#1 $ ++//* $Date: 2015/05/27 $ ++//* $DateTime: 2015/05/27 17:11:47 $ ++//* $Change: 1236156 $ ++//* $File: //DAILEO/Columbus/IPCamera/source/iNfinity/iNfinity_ROM/source/include/macro.include $ ++//* $Revision: #1 $ ++//* ++ ++ ++////WREG ++.macro WREG reg_addr32, vall ++ ldr r7, =\reg_addr32 ++ ldr r6, =\vall ++ str r6, [r7] ++ b 1011f ++ .ltorg ++1011: ++.endm ++ ++ ++////REG_C2M ++.macro REG_C2M cpu_reg, reg_addr32 ++ ldr r7, =\reg_addr32 ++ str \cpu_reg, [r7] ++.endm ++ ++ ++////WREG_B ++.macro WREG_B reg_addr32, val ++ ldr r7, =\reg_addr32 ++ ldr r6, =\val ++ strb r6, [r7] ++.endm ++ ++ ++////RREG ++.macro RREG dest_reg, reg_addr32 ++ ldr r7, =\reg_addr32 ++ ldr \dest_reg, [r7] ++.endm ++ ++////RREG_B ++.macro RREG_B dest_reg, reg_addr32 ++ ldr r7, =\reg_addr32 ++ ldrb \dest_reg, [r7] ++.endm ++ ++////LOOP_DELAY ++.macro LOOP_DELAY val ++ ldr r7, =\val ++1012: ++ nop ++ subs r7,r7, #1 ++ bne 1012b ++.endm ++ ++////DELAYUS ++.macro DELAYUS val ++ ldr r7, =\val ++1013: ++ // in AMBER3, we set subtrahend from 1 to 40 ++ subs r7, r7, #40 ++ bgt 1013b ++.endm ++ ++ ++////_HOLD_ ++.macro _HOLD_ ++ b . ++.endm ++ ++////MEMCPY32 ++.macro MEMCPY32 ++1015: ++ ldr r9, [r10], #4 ++ str r9, [r11], #4 ++ subs r12, r12, #4 ++ bne 1015b ++.endm ++ ++////MMUSET ++.macro MMUSET ++1016: ++ str r3, [r2], #4 ++ add r3, r3, #0x00100000 ++ subs r4, r4, #1 ++ cmp r4, #0 ++ bne 1016b ++.endm ++ ++////MEMCPY32 ++.macro MEMCPY32_T ++1017: ++ ldr r4, [r5] ++ str r4, [r6] ++ add r5, #4 ++ add r6, #4 ++ sub r7, #4 ++ bne 1017b ++.endm +\ No newline at end of file +diff --git a/drivers/sstar/msys/memcpy.S b/drivers/sstar/msys/memcpy.S +new file mode 100755 +index 000000000000..b5d92fffe41a +--- /dev/null ++++ b/drivers/sstar/msys/memcpy.S +@@ -0,0 +1,683 @@ ++/* ++ * Copyright (C) 2008 The Android Open Source Project ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ++ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ++ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS ++ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED ++ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ++ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ++ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++//#include ++#include "arm.include" ++#include "macro.include" ++ ++#if 1 //defined(__ARM_NEON__) && !defined(ARCH_ARM_USE_NON_NEON_MEMCPY) ++ ++.text ++.fpu neon ++ ++#ifdef HAVE_32_BYTE_CACHE_LINE ++/* a prefetch distance of 2 cache-lines */ ++#define CACHE_LINE_SIZE 32 ++#else ++/* a prefetch distance of 4 cache-lines works best experimentally */ ++#define CACHE_LINE_SIZE 64 ++#endif ++ ++ENTRY(_bench_neon_memcpy) ++ .save {r0, lr} ++ /* start preloading as early as possible */ ++ pld [r1, #(CACHE_LINE_SIZE * 0)] ++ stmfd sp!, {r0, lr} ++ pld [r1, #(CACHE_LINE_SIZE * 1)] ++ ++/* If Neon supports unaligned access then remove the align code, ++ * unless a size limit has been specified. ++ */ ++#ifndef NEON_UNALIGNED_ACCESS ++ /* do we have at least 16-bytes to copy (needed for alignment below) */ ++ cmp r2, #16 ++ blo 5f ++ ++ /* check if buffers are aligned. If so, run arm-only version */ ++ eor r3, r0, r1 ++ ands r3, r3, #0x3 ++ beq 11f ++ ++ /* align destination to cache-line for the write-buffer */ ++ rsb r3, r0, #0 ++ ands r3, r3, #0xF ++ beq 2f ++ ++ /* copy up to 15-bytes (count in r3) */ ++ sub r2, r2, r3 ++ movs ip, r3, lsl #31 ++ ldrmib lr, [r1], #1 ++ strmib lr, [r0], #1 ++ ldrcsb ip, [r1], #1 ++ ldrcsb lr, [r1], #1 ++ strcsb ip, [r0], #1 ++ strcsb lr, [r0], #1 ++ movs ip, r3, lsl #29 ++ bge 1f ++ // copies 4 bytes, destination 32-bits aligned ++ vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! ++ vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]! ++1: bcc 2f ++ // copies 8 bytes, destination 64-bits aligned ++ vld1.8 {d0}, [r1]! ++ vst1.8 {d0}, [r0, :64]! ++2: ++ /* preload immediately the next cache line, which we may need */ ++ pld [r1, #(CACHE_LINE_SIZE * 0)] ++ pld [r1, #(CACHE_LINE_SIZE * 1)] ++ ++#ifdef HAVE_32_BYTE_CACHE_LINE ++ /* make sure we have at least 32 bytes to copy */ ++ subs r2, r2, #32 ++ blo 4f ++ ++ /* preload all the cache lines we need. ++ * NOTE: the number of pld below depends on PREFETCH_DISTANCE, ++ * ideally would would increase the distance in the main loop to ++ * avoid the goofy code below. In practice this doesn't seem to make ++ * a big difference. ++ */ ++ pld [r1, #(PREFETCH_DISTANCE)] ++ ++1: /* The main loop copies 32 bytes at a time */ ++ vld1.8 {d0 - d3}, [r1]! ++ pld [r1, #(PREFETCH_DISTANCE)] ++ subs r2, r2, #32 ++ vst1.8 {d0 - d3}, [r0, :128]! ++ bhs 1b ++#else ++ /* make sure we have at least 64 bytes to copy */ ++ subs r2, r2, #64 ++ blo 2f ++ ++ /* preload all the cache lines we need. */ ++ pld [r1, #(CACHE_LINE_SIZE * 2)] ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++ ++1: /* The main loop copies 64 bytes at a time */ ++ vld1.8 {d0 - d3}, [r1]! ++ vld1.8 {d4 - d7}, [r1]! ++#ifdef HAVE_32_BYTE_CACHE_LINE ++ pld [r1, #(CACHE_LINE_SIZE * 2)] ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++#else ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++#endif ++ subs r2, r2, #64 ++ vst1.8 {d0 - d3}, [r0, :128]! ++ vst1.8 {d4 - d7}, [r0, :128]! ++ bhs 1b ++ ++2: /* fix-up the remaining count and make sure we have >= 32 bytes left */ ++ add r2, r2, #64 ++ subs r2, r2, #32 ++ blo 4f ++ ++3: /* 32 bytes at a time. These cache lines were already preloaded */ ++ vld1.8 {d0 - d3}, [r1]! ++ subs r2, r2, #32 ++ vst1.8 {d0 - d3}, [r0, :128]! ++ bhs 3b ++#endif ++4: /* less than 32 left */ ++ add r2, r2, #32 ++ tst r2, #0x10 ++ beq 5f ++ // copies 16 bytes, 128-bits aligned ++ vld1.8 {d0, d1}, [r1]! ++ vst1.8 {d0, d1}, [r0, :128]! ++5: /* copy up to 15-bytes (count in r2) */ ++ movs ip, r2, lsl #29 ++ bcc 1f ++ vld1.8 {d0}, [r1]! ++ vst1.8 {d0}, [r0]! ++1: bge 2f ++ vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! ++ vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! ++2: movs ip, r2, lsl #31 ++ ldrmib r3, [r1], #1 ++ ldrcsb ip, [r1], #1 ++ ldrcsb lr, [r1], #1 ++ strmib r3, [r0], #1 ++ strcsb ip, [r0], #1 ++ strcsb lr, [r0], #1 ++ ++ ldmfd sp!, {r0, lr} ++ bx lr ++ ++#else /* NEON_UNALIGNED_ACCESS */ ++ ++ // Check so divider is at least 16 bytes, needed for alignment code. ++ cmp r2, #16 ++ blo 5f ++ ++#ifdef NEON_MEMCPY_ALIGNMENT_DIVIDER ++ /* Check the upper size limit for Neon unaligned memory access in memcpy */ ++#if NEON_MEMCPY_ALIGNMENT_DIVIDER >= 16 ++ cmp r2, #NEON_MEMCPY_ALIGNMENT_DIVIDER ++ blo 3f ++#endif ++ /* check if buffers are aligned. If so, run arm-only version */ ++ eor r3, r0, r1 ++ ands r3, r3, #0x3 ++ beq 11f ++ ++ /* align destination to 16 bytes for the write-buffer */ ++ rsb r3, r0, #0 ++ ands r3, r3, #0xF ++ beq 3f ++ ++ /* copy up to 15-bytes (count in r3) */ ++ sub r2, r2, r3 ++ movs ip, r3, lsl #31 ++ ldrmib lr, [r1], #1 ++ strmib lr, [r0], #1 ++ ldrcsb ip, [r1], #1 ++ ldrcsb lr, [r1], #1 ++ strcsb ip, [r0], #1 ++ strcsb lr, [r0], #1 ++ movs ip, r3, lsl #29 ++ bge 1f ++ // copies 4 bytes, destination 32-bits aligned ++ vld1.32 {d0[0]}, [r1]! ++ vst1.32 {d0[0]}, [r0, :32]! ++1: bcc 2f ++ // copies 8 bytes, destination 64-bits aligned ++ vld1.8 {d0}, [r1]! ++ vst1.8 {d0}, [r0, :64]! ++2: ++ /* preload immediately the next cache line, which we may need */ ++ pld [r1, #(CACHE_LINE_SIZE * 0)] ++ pld [r1, #(CACHE_LINE_SIZE * 1)] ++3: ++#endif ++ /* make sure we have at least 64 bytes to copy */ ++ subs r2, r2, #64 ++ blo 2f ++ ++ /* preload all the cache lines we need */ ++ pld [r1, #(CACHE_LINE_SIZE * 2)] ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++ ++1: /* The main loop copies 64 bytes at a time */ ++ vld1.8 {d0 - d3}, [r1]! ++ vld1.8 {d4 - d7}, [r1]! ++#ifdef HAVE_32_BYTE_CACHE_LINE ++ pld [r1, #(CACHE_LINE_SIZE * 2)] ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++#else ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++#endif ++ subs r2, r2, #64 ++ vst1.8 {d0 - d3}, [r0]! ++ vst1.8 {d4 - d7}, [r0]! ++ bhs 1b ++ ++2: /* fix-up the remaining count and make sure we have >= 32 bytes left */ ++ add r2, r2, #64 ++ subs r2, r2, #32 ++ blo 4f ++ ++3: /* 32 bytes at a time. These cache lines were already preloaded */ ++ vld1.8 {d0 - d3}, [r1]! ++ subs r2, r2, #32 ++ vst1.8 {d0 - d3}, [r0]! ++ bhs 3b ++ ++4: /* less than 32 left */ ++ add r2, r2, #32 ++ tst r2, #0x10 ++ beq 5f ++ // copies 16 bytes, 128-bits aligned ++ vld1.8 {d0, d1}, [r1]! ++ vst1.8 {d0, d1}, [r0]! ++5: /* copy up to 15-bytes (count in r2) */ ++ movs ip, r2, lsl #29 ++ bcc 1f ++ vld1.8 {d0}, [r1]! ++ vst1.8 {d0}, [r0]! ++1: bge 2f ++ vld1.32 {d0[0]}, [r1]! ++ vst1.32 {d0[0]}, [r0]! ++2: movs ip, r2, lsl #31 ++ ldrmib r3, [r1], #1 ++ ldrcsb ip, [r1], #1 ++ ldrcsb lr, [r1], #1 ++ strmib r3, [r0], #1 ++ strcsb ip, [r0], #1 ++ strcsb lr, [r0], #1 ++ ++ ldmfd sp!, {r0, lr} ++ bx lr ++#endif /* NEON_UNALIGNED_ACCESS */ ++11: ++ /* Simple arm-only copy loop to handle aligned copy operations */ ++ stmfd sp!, {r4, r5, r6, r7, r8} ++ pld [r1, #(CACHE_LINE_SIZE * 2)] ++ ++ /* Check alignment */ ++ rsb r3, r1, #0 ++ ands r3, #3 ++ beq 2f ++ ++ /* align source to 32 bits. We need to insert 2 instructions between ++ * a ldr[b|h] and str[b|h] because byte and half-word instructions ++ * stall 2 cycles. ++ */ ++ movs r12, r3, lsl #31 ++ sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */ ++ ldrmib r3, [r1], #1 ++ ldrcsb r4, [r1], #1 ++ ldrcsb r5, [r1], #1 ++ strmib r3, [r0], #1 ++ strcsb r4, [r0], #1 ++ strcsb r5, [r0], #1 ++2: ++ subs r2, #32 ++ blt 5f ++ pld [r1, #(CACHE_LINE_SIZE * 3)] ++3: /* Main copy loop, copying 32 bytes at a time */ ++ pld [r1, #(CACHE_LINE_SIZE * 4)] ++ ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr} ++ subs r2, r2, #32 ++ stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr} ++ bge 3b ++5: /* Handle any remaining bytes */ ++ adds r2, #32 ++ beq 6f ++ ++ movs r12, r2, lsl #28 ++ ldmcsia r1!, {r3, r4, r5, r6} /* 16 bytes */ ++ ldmmiia r1!, {r7, r8} /* 8 bytes */ ++ stmcsia r0!, {r3, r4, r5, r6} ++ stmmiia r0!, {r7, r8} ++ movs r12, r2, lsl #30 ++ ldrcs r3, [r1], #4 /* 4 bytes */ ++ ldrmih r4, [r1], #2 /* 2 bytes */ ++ strcs r3, [r0], #4 ++ strmih r4, [r0], #2 ++ tst r2, #0x1 ++ ldrneb r3, [r1] /* last byte */ ++ strneb r3, [r0] ++6: ++ ldmfd sp!, {r4, r5, r6, r7, r8} ++ ldmfd sp!, {r0, pc} ++END(_bench_neon_memcpy) ++ ++ ++ /* ++ * Optimized memcpy() for ARM. ++ * ++ * note that memcpy() always returns the destination pointer, ++ * so we have to preserve R0. ++ */ ++ ++ENTRY(_bench_memcpy) ++ /* The stack must always be 64-bits aligned to be compliant with the ++ * ARM ABI. Since we have to save R0, we might as well save R4 ++ * which we can use for better pipelining of the reads below ++ */ ++ .save {r0, r4, lr} ++ stmfd sp!, {r0, r4, lr} ++ /* Making room for r5-r11 which will be spilled later */ ++ .pad #28 ++ sub sp, sp, #28 ++ ++ /* preload the destination because we'll align it to a cache line ++ with small writes. Also start the source "pump". */ ++ pld [r0, #0] ++ pld [r1, #0] ++ pld [r1, #32] ++ ++ /* it simplifies things to take care of len<4 early */ ++ cmp r2, #4 ++ blo copy_last_3_and_return ++ ++ /* compute the offset to align the source ++ * offset = (4-(src&3))&3 = -src & 3 ++ */ ++ rsb r3, r1, #0 ++ ands r3, r3, #3 ++ beq src_aligned ++ ++ /* align source to 32 bits. We need to insert 2 instructions between ++ * a ldr[b|h] and str[b|h] because byte and half-word instructions ++ * stall 2 cycles. ++ */ ++ movs r12, r3, lsl #31 ++ sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */ ++ ldrmib r3, [r1], #1 ++ ldrcsb r4, [r1], #1 ++ ldrcsb r12,[r1], #1 ++ strmib r3, [r0], #1 ++ strcsb r4, [r0], #1 ++ strcsb r12,[r0], #1 ++ ++src_aligned: ++ ++ /* see if src and dst are aligned together (congruent) */ ++ eor r12, r0, r1 ++ tst r12, #3 ++ bne non_congruent ++ ++ /* Use post-incriment mode for stm to spill r5-r11 to reserved stack ++ * frame. Don't update sp. ++ */ ++ stmea sp, {r5-r11} ++ ++ /* align the destination to a cache-line */ ++ rsb r3, r0, #0 ++ ands r3, r3, #0x1C ++ beq congruent_aligned32 ++ cmp r3, r2 ++ andhi r3, r2, #0x1C ++ ++ /* conditionnaly copies 0 to 7 words (length in r3) */ ++ movs r12, r3, lsl #28 ++ ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */ ++ ldmmiia r1!, {r8, r9} /* 8 bytes */ ++ stmcsia r0!, {r4, r5, r6, r7} ++ stmmiia r0!, {r8, r9} ++ tst r3, #0x4 ++ ldrne r10,[r1], #4 /* 4 bytes */ ++ strne r10,[r0], #4 ++ sub r2, r2, r3 ++ ++congruent_aligned32: ++ /* ++ * here source is aligned to 32 bytes. ++ */ ++ ++cached_aligned32: ++ subs r2, r2, #32 ++ blo less_than_32_left ++ ++ /* ++ * We preload a cache-line up to 64 bytes ahead. On the 926, this will ++ * stall only until the requested world is fetched, but the linefill ++ * continues in the the background. ++ * While the linefill is going, we write our previous cache-line ++ * into the write-buffer (which should have some free space). ++ * When the linefill is done, the writebuffer will ++ * start dumping its content into memory ++ * ++ * While all this is going, we then load a full cache line into ++ * 8 registers, this cache line should be in the cache by now ++ * (or partly in the cache). ++ * ++ * This code should work well regardless of the source/dest alignment. ++ * ++ */ ++ ++ // Align the preload register to a cache-line because the cpu does ++ // "critical word first" (the first word requested is loaded first). ++ bic r12, r1, #0x1F ++ add r12, r12, #64 ++ ++1: ldmia r1!, { r4-r11 } ++ pld [r12, #64] ++ subs r2, r2, #32 ++ ++ // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi ++ // for ARM9 preload will not be safely guarded by the preceding subs. ++ // When it is safely guarded the only possibility to have SIGSEGV here ++ // is because the caller overstates the length. ++ ldrhi r3, [r12], #32 /* cheap ARM9 preload */ ++ stmia r0!, { r4-r11 } ++ bhs 1b ++ ++ add r2, r2, #32 ++ ++ ++ ++ ++less_than_32_left: ++ /* ++ * less than 32 bytes left at this point (length in r2) ++ */ ++ ++ /* skip all this if there is nothing to do, which should ++ * be a common case (if not executed the code below takes ++ * about 16 cycles) ++ */ ++ tst r2, #0x1F ++ beq 1f ++ ++ /* conditionnaly copies 0 to 31 bytes */ ++ movs r12, r2, lsl #28 ++ ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */ ++ ldmmiia r1!, {r8, r9} /* 8 bytes */ ++ stmcsia r0!, {r4, r5, r6, r7} ++ stmmiia r0!, {r8, r9} ++ movs r12, r2, lsl #30 ++ ldrcs r3, [r1], #4 /* 4 bytes */ ++ ldrmih r4, [r1], #2 /* 2 bytes */ ++ strcs r3, [r0], #4 ++ strmih r4, [r0], #2 ++ tst r2, #0x1 ++ ldrneb r3, [r1] /* last byte */ ++ strneb r3, [r0] ++ ++ /* we're done! restore everything and return */ ++1: ldmfd sp!, {r5-r11} ++ ldmfd sp!, {r0, r4, lr} ++ bx lr ++ ++ /********************************************************************/ ++ ++non_congruent: ++ /* ++ * here source is aligned to 4 bytes ++ * but destination is not. ++ * ++ * in the code below r2 is the number of bytes read ++ * (the number of bytes written is always smaller, because we have ++ * partial words in the shift queue) ++ */ ++ cmp r2, #4 ++ blo copy_last_3_and_return ++ ++ /* Use post-incriment mode for stm to spill r5-r11 to reserved stack ++ * frame. Don't update sp. ++ */ ++ stmea sp, {r5-r11} ++ ++ /* compute shifts needed to align src to dest */ ++ rsb r5, r0, #0 ++ and r5, r5, #3 /* r5 = # bytes in partial words */ ++ mov r12, r5, lsl #3 /* r12 = right */ ++ rsb lr, r12, #32 /* lr = left */ ++ ++ /* read the first word */ ++ ldr r3, [r1], #4 ++ sub r2, r2, #4 ++ ++ /* write a partial word (0 to 3 bytes), such that destination ++ * becomes aligned to 32 bits (r5 = nb of words to copy for alignment) ++ */ ++ movs r5, r5, lsl #31 ++ strmib r3, [r0], #1 ++ movmi r3, r3, lsr #8 ++ strcsb r3, [r0], #1 ++ movcs r3, r3, lsr #8 ++ strcsb r3, [r0], #1 ++ movcs r3, r3, lsr #8 ++ ++ cmp r2, #4 ++ blo partial_word_tail ++ ++ /* Align destination to 32 bytes (cache line boundary) */ ++1: tst r0, #0x1c ++ beq 2f ++ ldr r5, [r1], #4 ++ sub r2, r2, #4 ++ orr r4, r3, r5, lsl lr ++ mov r3, r5, lsr r12 ++ str r4, [r0], #4 ++ cmp r2, #4 ++ bhs 1b ++ blo partial_word_tail ++ ++ /* copy 32 bytes at a time */ ++2: subs r2, r2, #32 ++ blo less_than_thirtytwo ++ ++ /* Use immediate mode for the shifts, because there is an extra cycle ++ * for register shifts, which could account for up to 50% of ++ * performance hit. ++ */ ++ ++ cmp r12, #24 ++ beq loop24 ++ cmp r12, #8 ++ beq loop8 ++ ++loop16: ++ ldr r12, [r1], #4 ++1: mov r4, r12 ++ ldmia r1!, { r5,r6,r7, r8,r9,r10,r11} ++ pld [r1, #64] ++ subs r2, r2, #32 ++ ldrhs r12, [r1], #4 ++ orr r3, r3, r4, lsl #16 ++ mov r4, r4, lsr #16 ++ orr r4, r4, r5, lsl #16 ++ mov r5, r5, lsr #16 ++ orr r5, r5, r6, lsl #16 ++ mov r6, r6, lsr #16 ++ orr r6, r6, r7, lsl #16 ++ mov r7, r7, lsr #16 ++ orr r7, r7, r8, lsl #16 ++ mov r8, r8, lsr #16 ++ orr r8, r8, r9, lsl #16 ++ mov r9, r9, lsr #16 ++ orr r9, r9, r10, lsl #16 ++ mov r10, r10, lsr #16 ++ orr r10, r10, r11, lsl #16 ++ stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10} ++ mov r3, r11, lsr #16 ++ bhs 1b ++ b less_than_thirtytwo ++ ++loop8: ++ ldr r12, [r1], #4 ++1: mov r4, r12 ++ ldmia r1!, { r5,r6,r7, r8,r9,r10,r11} ++ pld [r1, #64] ++ subs r2, r2, #32 ++ ldrhs r12, [r1], #4 ++ orr r3, r3, r4, lsl #24 ++ mov r4, r4, lsr #8 ++ orr r4, r4, r5, lsl #24 ++ mov r5, r5, lsr #8 ++ orr r5, r5, r6, lsl #24 ++ mov r6, r6, lsr #8 ++ orr r6, r6, r7, lsl #24 ++ mov r7, r7, lsr #8 ++ orr r7, r7, r8, lsl #24 ++ mov r8, r8, lsr #8 ++ orr r8, r8, r9, lsl #24 ++ mov r9, r9, lsr #8 ++ orr r9, r9, r10, lsl #24 ++ mov r10, r10, lsr #8 ++ orr r10, r10, r11, lsl #24 ++ stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10} ++ mov r3, r11, lsr #8 ++ bhs 1b ++ b less_than_thirtytwo ++ ++loop24: ++ ldr r12, [r1], #4 ++1: mov r4, r12 ++ ldmia r1!, { r5,r6,r7, r8,r9,r10,r11} ++ pld [r1, #64] ++ subs r2, r2, #32 ++ ldrhs r12, [r1], #4 ++ orr r3, r3, r4, lsl #8 ++ mov r4, r4, lsr #24 ++ orr r4, r4, r5, lsl #8 ++ mov r5, r5, lsr #24 ++ orr r5, r5, r6, lsl #8 ++ mov r6, r6, lsr #24 ++ orr r6, r6, r7, lsl #8 ++ mov r7, r7, lsr #24 ++ orr r7, r7, r8, lsl #8 ++ mov r8, r8, lsr #24 ++ orr r8, r8, r9, lsl #8 ++ mov r9, r9, lsr #24 ++ orr r9, r9, r10, lsl #8 ++ mov r10, r10, lsr #24 ++ orr r10, r10, r11, lsl #8 ++ stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10} ++ mov r3, r11, lsr #24 ++ bhs 1b ++ ++ ++less_than_thirtytwo: ++ /* copy the last 0 to 31 bytes of the source */ ++ rsb r12, lr, #32 /* we corrupted r12, recompute it */ ++ add r2, r2, #32 ++ cmp r2, #4 ++ blo partial_word_tail ++ ++1: ldr r5, [r1], #4 ++ sub r2, r2, #4 ++ orr r4, r3, r5, lsl lr ++ mov r3, r5, lsr r12 ++ str r4, [r0], #4 ++ cmp r2, #4 ++ bhs 1b ++ ++partial_word_tail: ++ /* we have a partial word in the input buffer */ ++ movs r5, lr, lsl #(31-3) ++ strmib r3, [r0], #1 ++ movmi r3, r3, lsr #8 ++ strcsb r3, [r0], #1 ++ movcs r3, r3, lsr #8 ++ strcsb r3, [r0], #1 ++ ++ /* Refill spilled registers from the stack. Don't update sp. */ ++ ldmfd sp, {r5-r11} ++ ++copy_last_3_and_return: ++ movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */ ++ ldrmib r2, [r1], #1 ++ ldrcsb r3, [r1], #1 ++ ldrcsb r12,[r1] ++ strmib r2, [r0], #1 ++ strcsb r3, [r0], #1 ++ strcsb r12,[r0] ++ ++ /* we're done! restore sp and spilled registers and return */ ++ add sp, sp, #28 ++ ldmfd sp!, {r0, r4, lr} ++ bx lr ++END(_bench_memcpy) ++ ++ ++#endif /* __ARM_ARCH__ < 7 */ +diff --git a/drivers/sstar/msys/miu_monitor.c b/drivers/sstar/msys/miu_monitor.c +new file mode 100755 +index 000000000000..7d0fb6ab2f95 +--- /dev/null ++++ b/drivers/sstar/msys/miu_monitor.c +@@ -0,0 +1,80 @@ ++/* ++* miu_monitor.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "registers.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Function prototype with weak symbol ++//------------------------------------------------------------------------------------------------- ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++ ++struct timer_list monitor_timer; ++extern const char* miu_client_id_to_name(U16 id); ++static void MDev_timer_callback(unsigned long value) ++{ ++ u16 u16status; ++ u32 u32hit_address; ++ u16status=INREG16( (BASE_REG_MIU_PA+REG_ID_6F)); ++ if(u16status & BIT4) ++ { ++ u32hit_address = (INREG16( (BASE_REG_MIU_PA+REG_ID_6D)) + ((INREG16( (BASE_REG_MIU_PA+REG_ID_6E)))<<16) )<<5; ++ printk("WARN! addr:0x%08x stat:0x%04x\n",u32hit_address, u16status); ++ printk("WARN! Check %s\n", miu_client_id_to_name((u16status>>8)&0x7f) ); ++ } ++ mod_timer(&monitor_timer, jiffies+3*HZ); ++} ++ ++static int __init mstar_miu_drv_init_module(void) ++{ ++ ++ int ret = 0; ++ init_timer( &monitor_timer ); ++ monitor_timer.function = MDev_timer_callback; ++ monitor_timer.expires = jiffies+HZ; ++ add_timer(&monitor_timer); ++ return ret; ++} ++ ++static void __exit mstar_miu_drv_exit_module(void) ++{ ++ ++ del_timer(&monitor_timer); ++} ++ ++module_init(mstar_miu_drv_init_module); ++module_exit(mstar_miu_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MIU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/msys/ms_msys.c b/drivers/sstar/msys/ms_msys.c +new file mode 100755 +index 000000000000..42e02577f122 +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys.c +@@ -0,0 +1,2544 @@ ++/* ++* ms_msys.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * mdrv_system.c ++ * ++ * Created on: 2012/9/21 ++ * Author: Administrator ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++#include "mdrv_msys_io.h" ++#include "platform_msys.h" ++#include "mdrv_verchk.h" ++#include "ms_msys.h" ++ ++#include "mdrv_system.h" ++#ifdef CONFIG_MS_CPU_FREQ ++#include "tsensor.h" ++#endif ++#include "cam_os_wrapper.h" ++ ++//#define CONFIG_MS_SYSTEM_PART_STRING /*used to in I3*/ ++//#define CONFIG_MSYS_REQUEST_PROC /*used to in I3*/ ++//#define CONFIG_MSYS_KFILE_API /*used to in I3*/ ++//#define CONFIG_IOCTL_MSYS_MIU_PROTECT /*used to in I3*/ ++//#define CONFIG_MS_US_TICK_API ++//#define CONFIG_MS_PIU_TICK_API ++#define CONFIG_IOCTL_MSYS_USER_TO_PHYSICAL ++#define CONFIG_IOCTL_MSYS_DMEM ++#define CONFIG_IOCTL_MSYS_GET_UDID ++#define CONFIG_IOCTL_MSYS_ADDR_TRANS ++#define CONFIG_IOCTL_FLUSH_CACHE ++//#define CONFIG_IOCTL_IPCM_USELESS ++ ++ ++ ++#define MSYS_DEBUG 0 ++#define MINOR_SYS_NUM 128 ++#define MAJOR_SYS_NUM 233 ++ ++ ++#if MSYS_DEBUG ++#define MSYS_PRINT(fmt, args...) printk("[MSYS] " fmt, ## args) ++#else ++#define MSYS_PRINT(fmt, args...) ++#endif ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++extern void Chip_Flush_Memory(void); ++ ++static int msys_open(struct inode *inode, struct file *filp); ++static int msys_release(struct inode *inode, struct file *filp); ++static long msys_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++ ++typedef struct ++{ ++ MSYS_PROC_DEVICE proc_dev; ++ void *proc_addr; ++ struct proc_dir_entry* proc_entry; ++ struct list_head list; ++} PROC_INFO_LIST; ++ ++#ifdef CONFIG_MSYS_REQUEST_PROC ++static int msys_request_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr); ++static int msys_release_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr); ++static int msys_request_proc_dev(MSYS_PROC_DEVICE* proc_dev); ++static int msys_release_proc_dev(MSYS_PROC_DEVICE* proc_dev); ++#endif ++ ++ ++static struct file_operations msys_fops = { ++ .owner = THIS_MODULE, ++ .open = msys_open, ++ .release = msys_release, ++ .unlocked_ioctl=msys_ioctl, ++}; ++ ++ ++struct miscdevice sys_dev = { ++ .minor = MINOR_SYS_NUM, ++ .name = "msys", ++ .fops = &msys_fops, ++}; ++ ++#ifdef CONFIG_MS_SYSTEM_PART_STRING ++static unsigned char data_part_string[32]={0}; ++static unsigned char system_part_string[32]={0}; ++static unsigned char mstar_property_path[32]="/data"; ++#endif ++ ++ ++static u64 sys_dma_mask = 0xffffffffUL; ++struct list_head kept_mem_head; ++struct list_head fixed_mem_head; ++static struct mutex dmem_mutex; ++static unsigned char fixed_dmem_enabled=0; ++static unsigned char dmem_realloc_enabled=0; ++static unsigned int dmem_retry_count=16; ++ ++ ++struct DMEM_INFO_LIST ++{ ++ struct list_head list; ++ MSYS_DMEM_INFO dmem_info; ++}; ++#if 0 ++//port from fs/proc/meminfo.c ++unsigned int meminfo_free_in_K(void) ++{ ++ struct sysinfo i; ++#if 0 ++ unsigned long committed; ++ struct vmalloc_info vmi; ++ long cached; ++ long available; ++ unsigned long pagecache; ++ unsigned long wmark_low = 0; ++ unsigned long pages[NR_LRU_LISTS]; ++ struct zone *zone; ++ int lru; ++#endif ++ /* ++ * display in kilobytes. ++ */ ++ #define K(x) ((x) << (PAGE_SHIFT - 10)) ++ si_meminfo(&i); ++ si_swapinfo(&i); ++#if 0 ++ committed = percpu_counter_read_positive(&vm_committed_as); ++ cached = global_page_state(NR_FILE_PAGES) - ++ total_swapcache_pages() - i.bufferram; ++ if (cached < 0) ++ cached = 0; ++ ++ get_vmalloc_info(&vmi); ++ ++ for (lru = LRU_BASE; lru < NR_LRU_LISTS; lru++) ++ pages[lru] = global_page_state(NR_LRU_BASE + lru); ++ ++ for_each_zone(zone) ++ wmark_low += zone->watermark[WMARK_LOW]; ++ ++ /* ++ * Estimate the amount of memory available for userspace allocations, ++ * without causing swapping. ++ * ++ * Free memory cannot be taken below the low watermark, before the ++ * system starts swapping. ++ */ ++ available = i.freeram - wmark_low; ++ ++ /* ++ * Not all the page cache can be freed, otherwise the system will ++ * start swapping. Assume at least half of the page cache, or the ++ * low watermark worth of cache, needs to stay. ++ */ ++ pagecache = pages[LRU_ACTIVE_FILE] + pages[LRU_INACTIVE_FILE]; ++ pagecache -= min(pagecache / 2, wmark_low); ++ available += pagecache; ++ ++ /* ++ * Part of the reclaimable slab consists of items that are in use, ++ * and cannot be freed. Cap this estimate at the low watermark. ++ */ ++ available += global_page_state(NR_SLAB_RECLAIMABLE) - ++ min(global_page_state(NR_SLAB_RECLAIMABLE) / 2, wmark_low); ++ ++ if (available < 0) ++ available = 0; ++#endif ++ return K(i.freeram); ++ ++} ++EXPORT_SYMBOL(meminfo_free_in_K); ++#endif ++ ++ ++//static void *mm_mem_virt = NULL; /* virtual address of frame buffer 1 */ ++ ++ ++static int msys_open(struct inode *inode, struct file *filp) ++{ ++// printk(KERN_WARNING"%s():\n", __FUNCTION__); ++ return 0; ++} ++ ++static int msys_release(struct inode *inode, struct file *filp) ++{ ++// MSYS_PRINT(KERN_WARNING"%s():\n", __FUNCTION__); ++ return 0; ++} ++ ++ ++int msys_fix_dmem(char* name) ++{ ++ int err=0; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry,*match_entry; ++ match_entry=NULL; ++ ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(name!=NULL && name[0]!=0) ++ { ++ struct DMEM_INFO_LIST *new=NULL; ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (0==strncmp(entry->dmem_info.name, name,strnlen(name,15))) ++ { ++ match_entry=entry; ++ goto BEACH; ++ } ++ } ++ ++ ++ new=(struct DMEM_INFO_LIST *)kmalloc(sizeof(struct DMEM_INFO_LIST),GFP_KERNEL); ++ if(new==NULL) ++ { ++ MSYS_ERROR("allocate memory for fixed_mem_list entry error\n" ) ; ++ err = -ENOMEM; ++ goto BEACH; ++ } ++ memset(new->dmem_info.name,0,16); ++ memcpy(new->dmem_info.name,name,strnlen(name,15)); ++ //memcpy(&new->dmem_info,&mem_info,sizeof(MSYS_DMEM_INFO)); ++ ++ list_add(&new->list, &fixed_mem_head); ++ } ++ ++BEACH: ++ mutex_unlock(&dmem_mutex); ++ return err; ++} ++EXPORT_SYMBOL(msys_fix_dmem); ++ ++int msys_unfix_dmem(char* name) ++{ ++ ++ //MSYS_DMEM_INFO mem_info; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry,*match_entry; ++ match_entry=NULL; ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(name!=NULL && name[0]!=0) ++ { ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (0==strncmp(entry->dmem_info.name, name,strnlen(name,15))) ++ { ++ match_entry=entry; ++ break; ++ } ++ } ++ } ++ ++ if(match_entry!=NULL) ++ { ++ list_del_init(&match_entry->list); ++ kfree(match_entry); ++ } ++ ++//BEACH: ++ mutex_unlock(&dmem_mutex); ++ return 0; ++ ++} ++EXPORT_SYMBOL(msys_unfix_dmem); ++ ++ ++int msys_find_dmem_by_phys(unsigned long long phys,MSYS_DMEM_INFO *mem_info) ++{ ++ ++ //MSYS_DMEM_INFO mem_info; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ ++ int res=-EINVAL; ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(0!=phys) ++ { ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if ((entry->dmem_info.phys<=phys) && phys<(entry->dmem_info.phys+entry->dmem_info.length)) ++ { ++ memcpy(mem_info,&entry->dmem_info,sizeof(MSYS_DMEM_INFO)); ++ res=0; ++ goto BEACH; ++ ; ++ } ++ } ++ } ++ ++ ++BEACH: ++ mutex_unlock(&dmem_mutex); ++ return res; ++} ++EXPORT_SYMBOL(msys_find_dmem_by_phys); ++ ++int msys_find_dmem_by_name(const char *name, MSYS_DMEM_INFO *mem_info) ++{ ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry, *match_entry=NULL; ++ int res=-EINVAL; ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(name!=NULL && name[0]!=0) ++ { ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ res=strncmp(entry->dmem_info.name, name, 16); ++ if (0==res) ++ { ++ //MSYS_ERROR("%s: Find name\n", __func__); ++ match_entry=entry; ++ break; ++ } ++ } ++ } ++ else ++ { ++ MSYS_ERROR("%s: Invalid name\n", __func__); ++ } ++ ++ if(match_entry!=NULL) ++ { ++ memcpy(mem_info, &match_entry->dmem_info, sizeof(MSYS_DMEM_INFO)); ++ } ++ else ++ { ++ memset(mem_info->name,0,16); ++ } ++ ++ mutex_unlock(&dmem_mutex); ++ ++ return res; ++} ++ ++ ++int msys_release_dmem(MSYS_DMEM_INFO *mem_info) ++{ ++ ++ //MSYS_DMEM_INFO mem_info; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry,*match_entry; ++ ++ int dmem_fixed=0; ++ ++ mutex_lock(&dmem_mutex); ++ match_entry=NULL; ++ ++// MSYS_PRINT("\nFREEING DMEM [%s]\n\n",mem_info->name); ++ if(mem_info->name[0]!=0) ++ { ++ list_for_each(ptr, &kept_mem_head) ++ { ++ int res=0; ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ res=strncmp(entry->dmem_info.name, mem_info->name,strnlen(mem_info->name,15)); ++// MSYS_PRINT("DMEM0 [%s],%s %d\n",entry->dmem_info.name,match_entry->dmem_info.name,res); ++ if (0==res) ++ { ++ match_entry=entry; ++ break; ++ } ++ } ++ } ++ ++ ++ if(match_entry==NULL && (0!=mem_info->phys)) ++ { ++ MSYS_ERROR("WARNING!! DMEM [%s]@0x%08X can not be found by name, try to find by phys address\n",mem_info->name, (unsigned int)mem_info->phys); ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (entry->dmem_info.phys==mem_info->phys) ++ { ++ match_entry=entry; ++ break; ++ } ++ } ++ ++ } ++ ++ ++ if(match_entry==NULL) ++ { ++ MSYS_ERROR("DMEM [%s]@0x%08X not found, skipping release...\n",mem_info->name, (unsigned int)mem_info->phys); ++ goto BEACH; ++ } ++ ++ if(fixed_dmem_enabled) ++ { ++ //check if entry is fixed ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ int res=0; ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ res=strcmp(entry->dmem_info.name, match_entry->dmem_info.name); ++ if (0==res) ++ { ++ dmem_fixed=1; ++ MSYS_PRINT("DMEM [%s]@0x%08X is fixed, skipping release...\n",match_entry->dmem_info.name,(unsigned int)match_entry->dmem_info.phys); ++ goto BEACH; ++ } ++ } ++ } ++ ++ ++ dma_free_coherent(sys_dev.this_device, PAGE_ALIGN(match_entry->dmem_info.length),(void *)(uintptr_t)match_entry->dmem_info.kvirt,match_entry->dmem_info.phys); ++ ++ MSYS_PRINT("DMEM [%s]@0x%08X successfully released\n",match_entry->dmem_info.name,(unsigned int)match_entry->dmem_info.phys); ++ ++ list_del_init(&match_entry->list); ++ kfree(match_entry); ++ ++ ++ ++ ++BEACH: ++ mutex_unlock(&dmem_mutex); ++ return 0; ++ ++} ++EXPORT_SYMBOL(msys_release_dmem); ++ ++int msys_request_dmem(MSYS_DMEM_INFO *mem_info) ++{ ++ dma_addr_t phys_addr; ++ int err=0; ++ int retry=0; ++ ++ if(mem_info->name[0]==0||strlen(mem_info->name)>15) ++ { ++ MSYS_ERROR( "Invalid DMEM name!! Either garbage or empty name!!\n"); ++ return -EINVAL; ++ } ++ ++ /*if(mem_info->length<=0) ++ { ++ MSYS_ERROR( "Invalid DMEM length!! [%s]:0x%08X\n",mem_info->name,(unsigned int)mem_info->length); ++ return -EFAULT; ++ }*/ ++ ++ MSYS_ERROR("DMEM request: [%s]:0x%08X\n",mem_info->name,(unsigned int)mem_info->length); ++ ++ mutex_lock(&dmem_mutex); ++// if(mem_info->name[0]!=0) ++ { ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (0==strncmp(entry->dmem_info.name, mem_info->name,strnlen(mem_info->name,15))) ++ { ++ if(dmem_realloc_enabled && (entry->dmem_info.length != mem_info->length)) ++ { ++ MSYS_ERROR("dmem realloc %s", entry->dmem_info.name); ++ dma_free_coherent(sys_dev.this_device, PAGE_ALIGN(entry->dmem_info.length),(void *)(uintptr_t)entry->dmem_info.kvirt,entry->dmem_info.phys); ++ MSYS_ERROR("DMEM [%s]@0x%08X successfully released\n",entry->dmem_info.name,(unsigned int)entry->dmem_info.phys); ++ list_del_init(&entry->list); ++ break; ++ } ++ else ++ { ++ memcpy(mem_info,&entry->dmem_info,sizeof(MSYS_DMEM_INFO)); ++ MSYS_ERROR("DMEM kept entry found: name=%s, phys=0x%08X, length=0x%08X\n",mem_info->name,(unsigned int)mem_info->phys,(unsigned int)mem_info->length); ++ goto BEACH_ENTRY_FOUND; ++ } ++ } ++ } ++ ++ //MSYS_PRINT(KERN_WARNING"can not found kept direct requested memory entry name=%s\n",mem_info.name); ++ ++ } ++// else ++// { ++// MSYS_PRINT(" !!ERROR!! Anonymous DMEM request is forbidden !!\n"); ++// return -EFAULT; ++// } ++ ++ while( !(mem_info->kvirt = (u64)(uintptr_t)dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(mem_info->length), &phys_addr, GFP_KERNEL)) ) ++ { ++ if(retry >= dmem_retry_count) ++ { ++ MSYS_ERROR( "unable to allocate direct memory\n"); ++ err = -ENOMEM; ++ goto BEACH_ALLOCATE_FAILED; ++ } ++ MSYS_ERROR( "retry ALLOC_DMEM %d [%s]:0x%08X\n", retry, mem_info->name, (unsigned int)mem_info->length); ++ sysctl_compaction_handler(NULL, 1, NULL, NULL, NULL); ++ msleep(1000); ++ retry++; ++ } ++ ++ mem_info->phys=(u64)phys_addr; ++ ++ ++ { ++ struct DMEM_INFO_LIST *new=(struct DMEM_INFO_LIST *)kmalloc(sizeof(struct DMEM_INFO_LIST),GFP_KERNEL); ++ if(new==NULL) ++ { ++ MSYS_ERROR("allocate memory for mem_list entry error\n" ) ; ++ err = -ENOMEM; ++ goto BEACH; ++ ++ } ++ ++ memset(new->dmem_info.name,0,16); ++/* ++ new->dmem_info.kvirt=mem_info->kvirt; ++ new->dmem_info.phys=mem_info->phys; ++ new->dmem_info.length=mem_info->length; ++ if(mem_info->name!=NULL){ ++ memcpy(new->dmem_info.name,mem_info->name,strnlen(mem_info->name,15)); ++ } ++*/ ++ memcpy(&new->dmem_info,mem_info,sizeof(MSYS_DMEM_INFO)); ++ ++ list_add(&new->list, &kept_mem_head); ++ ++ } ++ ++ if(retry) ++ MSYS_ERROR("DMEM request: [%s]:0x%08X success, @0x%08X (retry=%d)\n",mem_info->name,(unsigned int)mem_info->length, (unsigned int)mem_info->phys, retry); ++ else ++ MSYS_ERROR("DMEM request: [%s]:0x%08X success, CPU phy:@0x%08X, virt:@0x%08X\n",mem_info->name,(unsigned int)mem_info->length, (unsigned int)mem_info->phys, (unsigned int)mem_info->kvirt); ++ ++ ++BEACH: ++ if(err==-ENOMEM) ++ { ++ msys_release_dmem(mem_info); ++ } ++ ++BEACH_ALLOCATE_FAILED: ++BEACH_ENTRY_FOUND: ++ if(err) ++ { ++ MSYS_ERROR("DMEM request: [%s]:0x%08X FAILED!! (retry=%d)\n",mem_info->name,(unsigned int)mem_info->length, retry); ++ } ++ ++#if 0 ++ if(0==err){ ++ memset((void *)((unsigned int)mem_info->kvirt),0,mem_info->length); ++ Chip_Flush_CacheAll(); ++ MSYS_PRINT("DMEM CLEAR!!\n"); ++ } ++ ++#endif ++ ++ mutex_unlock(&dmem_mutex); ++ return err; ++ ++} ++EXPORT_SYMBOL(msys_request_dmem); ++ ++#ifdef CONFIG_MS_PIU_TICK_API ++unsigned int get_PIU_tick_count(void) ++{ ++ return ( INREG16(0x1F006050) | (INREG16(0x1F006054)<<16) ); ++} ++ ++EXPORT_SYMBOL(get_PIU_tick_count); ++ ++static ssize_t PIU_T_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%X\n",get_PIU_tick_count()); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(PIU_T, 0444, PIU_T_show, NULL); ++#endif ++ ++#ifdef CONFIG_IOCTL_MSYS_USER_TO_PHYSICAL ++int msys_user_to_physical(unsigned long addr,unsigned long *phys) ++{ ++ ++ unsigned long paddr=0; ++ struct page *page; ++ down_read(¤t->mm->mmap_sem); ++ //if (get_user_pages(current, current->mm, addr, 1, 1, 0, &page, NULL) <= 0)//3.18 ++ if (get_user_pages(addr, 1, FOLL_WRITE, &page, NULL) <= 0) ++ { ++ up_read(¤t->mm->mmap_sem); ++ printk(KERN_WARNING"ERR!!\n"); ++ return -EINVAL; ++ } ++ up_read(¤t->mm->mmap_sem); ++ ++ paddr= page_to_phys(page); ++ ++ *phys=paddr; ++// if(paddr>0x21E00000) ++// { ++// printk(KERN_WARNING"\nKXX:0x%08X,0x%08X\n",(unsigned int)addr,(unsigned int)paddr); ++// } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msys_user_to_physical); ++#endif ++ ++#ifdef CONFIG_IOCTL_MSYS_DMEM ++int msys_find_dmem_by_name_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(mem_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(mem_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ mem_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(mem_info.VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (mem_info.VerChk_Size)); ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ if( (err=msys_find_dmem_by_name(mem_info.name, &mem_info)) ) ++ { ++ //return -ENOENT; ++ } ++ ++ if(copy_to_user((void __user *)arg, (void*)&mem_info, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_request_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(mem_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(mem_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ mem_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(mem_info.VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (mem_info.VerChk_Size)); ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ if( (err=msys_request_dmem(&mem_info)) ) ++ { ++ //MSYS_ERROR("request direct memory failed!!\n" ); ++ return err; ++ } ++ ++ if(copy_to_user((void __user *)arg, (void*)&mem_info, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_release_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(mem_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(mem_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ mem_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(mem_info.VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (mem_info.VerChk_Size)); ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return msys_release_dmem(&mem_info); ++ ++} ++#endif ++ ++int msys_flush_cache(unsigned long arg) ++{ ++ MSYS_DUMMY_INFO info; ++ if(copy_from_user((void*)&info, (void __user *)arg, sizeof(MSYS_DUMMY_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(info.VerChk_Size), sizeof(MSYS_DUMMY_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DUMMY_INFO), (info.VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ Chip_Flush_CacheAll(); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_IOCTL_MSYS_ADDR_TRANS ++int msys_addr_translation_verchk(unsigned long arg, bool direction) ++{ ++ MSYS_ADDR_TRANSLATION_INFO addr_info; ++ ++ if(copy_from_user((void*)&addr_info, (void __user *)arg, sizeof(addr_info))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(addr_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(addr_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ addr_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(addr_info.VerChk_Size), sizeof(MSYS_ADDR_TRANSLATION_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_ADDR_TRANSLATION_INFO), (addr_info.VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ if(direction) ++ addr_info.addr=Chip_MIU_to_Phys(addr_info.addr); ++ else ++ addr_info.addr=Chip_Phys_to_MIU(addr_info.addr); ++ ++ if(copy_to_user((void __user *)arg, (void*)&addr_info, sizeof(addr_info))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++#endif ++ ++int msys_get_riu_map_verchk(unsigned long arg) ++{ ++ MSYS_MMIO_INFO mmio_info; ++ if( copy_from_user((void*)&mmio_info, (void __user *)arg, sizeof(MSYS_MMIO_INFO)) ) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(mmio_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&mmio_info, IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ mmio_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(mmio_info.VerChk_Size), sizeof(MSYS_MMIO_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_MMIO_INFO), (mmio_info.VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ mmio_info.addr=Chip_Get_RIU_Phys(); ++ mmio_info.size=Chip_Get_RIU_Size(); ++ if( copy_to_user((void __user *)arg, (void*)&mmio_info, sizeof(MSYS_MMIO_INFO)) ) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_IOCTL_MSYS_DMEM ++int msys_fix_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(mem_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(mem_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ mem_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(mem_info.VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (mem_info.VerChk_Size)); ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ if( (err=msys_fix_dmem(mem_info.name)) ) ++ { ++ MSYS_ERROR("fix direct memory failed!! %s\n", mem_info.name); ++ return err; ++ } ++ ++ return 0; ++} ++ ++int msys_unfix_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(mem_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(mem_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ mem_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(mem_info.VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (mem_info.VerChk_Size)); ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ if( (err=msys_unfix_dmem(mem_info.name)) ) ++ { ++ MSYS_ERROR("unfix direct memory failed!! %s\n", mem_info.name); ++ return err; ++ } ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_IOCTL_MSYS_MIU_PROTECT ++int msys_miu_protect_verchk(unsigned long arg) ++{ ++ MSYS_MIU_PROTECT_INFO protect_info; ++ u64 miu_addr_start; ++ u64 miu_addr_end; ++ u32 start_unit, end_unit; ++ u8 i=0; ++ ++ if(copy_from_user((void*)&protect_info, (void __user *)arg, sizeof(MSYS_MIU_PROTECT_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(protect_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(protect_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ protect_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(protect_info.VerChk_Size), sizeof(MSYS_MIU_PROTECT_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_MIU_PROTECT_INFO), (((MSYS_MIU_PROTECT_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ miu_addr_start = Chip_Phys_to_MIU(protect_info.phys); ++ miu_addr_end = Chip_Phys_to_MIU(protect_info.phys + protect_info.length) - 1; ++ ++ if(miu_addr_start & (0x2000-1)) /*check 8KB align*/ ++ { ++ MSYS_WARN("MIU protect start=0x%08X is not 8KB aligned!\n", (u32)miu_addr_start); ++ } ++ ++ start_unit = (u32)((miu_addr_start & ~(0x2000-1)) >> 13); // 8KB unit ++ ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_60, (u16)(start_unit & 0xFFFF)); ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_68, (INREG16(BASE_REG_MIU_PA + REG_ID_68)) | ((start_unit>>16) & 0x3)); ++ ++ if( (miu_addr_end & (0x2000-1)) != (0x2000-1) ) /*check 8KB align*/ ++ { ++ MSYS_WARN("MIU protect end=0x%08X is not 8KB aligned!\n", (u32)miu_addr_end); ++ } ++ ++ end_unit = (u32)((miu_addr_end & ~(0x2000-1)) >> 13); // 8KB unit ++ ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_61, (u16)(end_unit & 0xFFFF)); ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_68, (INREG16(BASE_REG_MIU_PA + REG_ID_68)) | (((end_unit>>16) & 0x3) << 2)); ++ ++ printk("\n\tMIU protect start=0x%08X\n", start_unit << 13); ++ printk("\tMIU protect end=0x%08X\n", ((end_unit+1) << 13) -1); ++ printk("\tMIU protect id="); ++ ++ do ++ { ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_17 + (i*2), (protect_info.id[i] & 0x7F) | (protect_info.id[i+1]&0x7F)<<8 ); ++ printk(" 0x%02X 0x%02X", protect_info.id[i], protect_info.id[i+1]); ++ i+=2; ++ } while(protect_info.id[i]!=0x00 && i<16); ++ ++ printk("\n"); ++ ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_10, 0xFFFF); // for test, we set all id enable ++ ++ if(protect_info.w_protect) ++ SETREG16(BASE_REG_MIU_PA + REG_ID_69, BIT0); ++ if(protect_info.r_protect) ++ SETREG16(BASE_REG_MIU_PA + REG_ID_69, BIT4); ++ if(protect_info.inv_protect) ++ SETREG16(BASE_REG_MIU_PA + REG_ID_69, BIT8); ++ ++ printk("\tMIU protect W_protect=%d\n", protect_info.w_protect); ++ printk("\tMIU protect R_protect=%d\n", protect_info.r_protect); ++ printk("\tMIU protect INV_protect=%d\n", protect_info.inv_protect); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_MS_SYSTEM_PART_STRING ++int msys_string_verchk(unsigned long arg, unsigned int op) ++{ ++ MSYS_STRING_INFO info; ++ ++ if(copy_from_user((void*)&info, (void __user *)arg, sizeof(MSYS_STRING_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(info.VerChk_Size), sizeof(MSYS_STRING_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_STRING_INFO), (info.VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ if(op==0) ++ { ++ if(copy_to_user(&(((MSYS_STRING_INFO __user *)arg)->str[0]), (void*)system_part_string, sizeof(system_part_string))) ++ { ++ return -EFAULT; ++ } ++ } ++ else if(op==1) ++ { ++ if(copy_to_user(&(((MSYS_STRING_INFO __user *)arg)->str[0]), (void*)data_part_string, sizeof(data_part_string))) ++ { ++ return -EFAULT; ++ } ++ } ++ else if(op==2) ++ { ++ if(copy_to_user(&(((MSYS_STRING_INFO __user *)arg)->str[0]), (void*)mstar_property_path, sizeof(mstar_property_path))) ++ { ++ return -EFAULT; ++ } ++ } ++ else if(op==3) ++ { ++ if(copy_from_user((void*)mstar_property_path, &(((MSYS_STRING_INFO __user *)arg)->str[0]), sizeof(mstar_property_path))) ++ { ++ return -EFAULT; ++ } ++ printk("set mstar_property_path=%s\n", mstar_property_path); ++ } ++ else ++ { ++ MSYS_ERROR("[%s] unsupport op=%d!!\n", __FUNCTION__, op); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++#endif ++ ++int msys_read_uuid(unsigned long long* udid) ++{ ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ *udid = (u64)INREG16(BASE_REG_PMTOP_PA + REG_ID_00) ; ++#elif defined(CONFIG_ARCH_INFINITY6E) ++ *udid = (u64)INREG16(BASE_REG_OTP_PA + REG_ID_54) | ++ ((u64)INREG16(BASE_REG_OTP_PA + REG_ID_55) << 16) | ++ ((u64)INREG16(BASE_REG_OTP_PA + REG_ID_56) << 32) ; ++#else ++ CLRREG16(BASE_REG_EFUSE_PA + REG_ID_03, BIT8); //reg_sel_read_256[8]=0 to read a/b/c/d ++ *udid = (u64)INREG16(BASE_REG_EFUSE_PA + REG_ID_16) | ++ ((u64)(INREG16(BASE_REG_EFUSE_PA + REG_ID_17)) << 16) | ++ ((u64)INREG16(BASE_REG_EFUSE_PA + REG_ID_18) << 32); ++#endif ++ return 0; ++} ++EXPORT_SYMBOL(msys_read_uuid); ++ ++void msys_set_rebootType(u16 arg) ++{ ++ if (arg==MSYS_REBOOT_BY_SW_RST) ++ { ++ SETREG16(BASE_REG_PMPOR_PA+REG_ID_01, BIT0); ++ SETREG16(BASE_REG_WDT_PA+REG_ID_02,BIT0); ++ } ++} ++EXPORT_SYMBOL(msys_set_rebootType); ++ ++int msys_get_rebootType(void) ++{ ++ U16 RegVal=0, rebootType=0; ++ ++ RegVal = INREG16(BASE_REG_WDT_PA+REG_ID_02); ++ if(RegVal&0x01) ++ rebootType=MSYS_REBOOT_BY_WDT_RST; ++ else ++ { ++ RegVal = INREG16(BASE_REG_PMPOR_PA+REG_ID_01); ++ if(RegVal&0x01) ++ rebootType=MSYS_REBOOT_BY_SW_RST; ++ else ++ rebootType=MSYS_REBOOT_BY_HW_RST; ++ } ++ return rebootType; ++} ++EXPORT_SYMBOL(msys_get_rebootType); ++ ++CHIP_VERSION msys_get_chipVersion(void) ++{ ++ CHIP_VERSION eRet = U01; ++ eRet = (INREG16(BASE_REG_PMTOP_PA + REG_ID_01)>>8); ++ return eRet; ++} ++EXPORT_SYMBOL(msys_get_chipVersion); ++ ++#ifdef CONFIG_IOCTL_IPCM_USELESS ++int msys_get_chipVersion_verchk(unsigned long arg) ++{ ++ MSYS_CHIPVER_INFO chipVer_info; ++ if(copy_from_user((void*)&chipVer_info, (void __user *)arg, sizeof(chipVer_info))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(chipVer_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(chipVer_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ chipVer_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(chipVer_info.VerChk_Size), sizeof(MSYS_CHIPVER_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_CHIPVER_INFO), chipVer_info.VerChk_Size); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ chipVer_info.chipVersion = msys_get_chipVersion(); ++ if(copy_to_user((void __user *)arg, (void*)&chipVer_info, sizeof(chipVer_info))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++#endif ++#ifdef CONFIG_IOCTL_MSYS_GET_UDID ++int msys_get_udid_verchk(unsigned long arg) ++{ ++ MSYS_UDID_INFO udid_info; ++ if(copy_from_user((void*)&udid_info, (void __user *)arg, sizeof(udid_info))) ++ { ++ return -EFAULT; ++ } ++ ++ if ( CHK_VERCHK_HEADER(&(udid_info.VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(udid_info.VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ udid_info.VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(udid_info.VerChk_Size), sizeof(MSYS_UDID_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_UDID_INFO), (udid_info.VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ msys_read_uuid(&(udid_info.udid)); ++ ++ if(copy_to_user((void __user *)arg, (void*)&udid_info, sizeof(udid_info))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++#endif ++#ifdef CONFIG_IOCTL_IPCM_USELESS ++static int msys_check_freq_cfg(unsigned long arg) ++{ ++ MSYS_FREQGEN_INFO freq_info; ++ ++ if(copy_from_user((void*)&freq_info, (void __user *)arg, sizeof(MSYS_FREQGEN_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ return msys_request_freq(&freq_info); ++} ++#endif ++static long msys_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int err= 0; ++ ++ // wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ if (_IOC_TYPE(cmd) != MSYS_IOCTL_MAGIC) return -ENOTTY; ++ if (_IOC_NR(cmd) > IOCTL_SYS_MAXNR) return -ENOTTY; ++ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ ++ ++ switch(cmd) ++ { ++#ifdef CONFIG_IOCTL_MSYS_DMEM ++ case IOCTL_MSYS_REQUEST_DMEM: ++ { ++ if((err=msys_request_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_REQUEST_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_RELEASE_DMEM: ++ { ++ if((err=msys_release_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_RELEASE_DMEM error!\n"); ++ } ++ break; ++ case IOCTL_MSYS_FIX_DMEM: ++ { ++ if((err=msys_fix_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_FIX_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_UNFIX_DMEM: ++ { ++ if((err=msys_unfix_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_UNFIX_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_FIND_DMEM_BY_NAME: ++ { ++ if((err=msys_find_dmem_by_name_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_FIND_DMEM_BY_NAME error!\n"); ++ msys_find_dmem_by_name_verchk(arg); ++ err=0; ++ } ++ break; ++#endif ++ ++#ifdef CONFIG_IOCTL_MSYS_ADDR_TRANS ++ case IOCTL_MSYS_PHYS_TO_MIU: ++ { ++ if((err=msys_addr_translation_verchk(arg, 0))) ++ MSYS_ERROR("IOCTL_MSYS_PHYS_TO_MIU error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_MIU_TO_PHYS: ++ { ++ if((err=msys_addr_translation_verchk(arg, 1))) ++ MSYS_ERROR("IOCTL_MSYS_MIU_TO_PHYS error!\n"); ++ } ++ break; ++#endif ++ case IOCTL_MSYS_GET_RIU_MAP: ++ { ++ if((err=msys_get_riu_map_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_GET_RIU_MAP error!\n"); ++ } ++ break; ++#ifdef CONFIG_IOCTL_MSYS_MIU_PROTECT ++ case IOCTL_MSYS_MIU_PROTECT: ++ { ++ if((err=msys_miu_protect_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_MIU_PROTECT error!\n"); ++ } ++ break; ++#endif ++#ifdef CONFIG_IOCTL_MSYS_USER_TO_PHYSICAL ++ case IOCTL_MSYS_USER_TO_PHYSICAL: ++ { ++ unsigned long addr,paddr; ++ ++ ++ if(copy_from_user((void*)&addr, (void __user *)arg, sizeof(addr))) ++ { ++ return -EFAULT; ++ } ++ ++ if((err=msys_user_to_physical(addr,&paddr))) ++ MSYS_ERROR("IOCTL_MSYS_GET_USER_PAGE error!\n"); ++ ++ if(copy_to_user((void __user *)arg, (void*)&paddr, sizeof(paddr))) ++ { ++ return -EFAULT; ++ } ++ } ++ break; ++#endif ++#ifdef CONFIG_MS_SYSTEM_PART_STRING ++ case IOCTL_MSYS_GET_SYSP_STRING: ++ { ++ if((err=msys_string_verchk(arg, 0))) ++ MSYS_ERROR("IOCTL_MSYS_GET_SYSP_STRING error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_DATAP_STRING: ++ { ++ if((err=msys_string_verchk(arg, 1))) ++ MSYS_ERROR("IOCTL_MSYS_GET_DATAP_STRING error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_PROPERTY_PATH: ++ { ++ if((err=msys_string_verchk(arg, 2))) ++ MSYS_ERROR("IOCTL_MSYS_GET_PROPERTY_PATH error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_SET_PROPERTY_PATH: ++ { ++ if((err=msys_string_verchk(arg, 3))) ++ MSYS_ERROR("IOCTL_MSYS_SET_PROPERTY_PATH error!\n"); ++ } ++ break; ++#endif ++ ++#ifdef CONFIG_MS_US_TICK_API ++ case IOCTL_MSYS_GET_US_TICKS: ++ { ++ ++ u64 us_ticks=Chip_Get_US_Ticks(); ++ if(copy_to_user((void __user *)arg, (void*)&us_ticks, sizeof(us_ticks))) ++ { ++ return -EFAULT; ++ } ++ return -EPERM; ++ } ++ break; ++#endif ++#ifdef CONFIG_IOCTL_MSYS_GET_UDID ++ case IOCTL_MSYS_GET_UDID: ++ { ++ if((err=msys_get_udid_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_GET_UDID error!\n"); ++ } ++ break; ++#endif ++#ifdef CONFIG_MS_PIU_TICK_API ++ case IOCTL_MSYS_PRINT_PIU_TIMER_TICKS: ++ { ++ int id=arg; ++ printk(KERN_WARNING"PIU_T:%X#%d#\n",get_PIU_tick_count(),id); ++ } ++ break; ++#endif ++#ifdef CONFIG_MSYS_BENCH_MEMORY_FUNC ++ case IOCTL_MSYS_BENCH_MEMORY: ++ { ++ int test_mem_size_in_MB=arg; ++ extern void msys_bench_memory(unsigned int uMemSize); ++ msys_bench_memory((unsigned int)test_mem_size_in_MB); ++ } ++ break; ++#endif ++ ++#ifdef CONFIG_MSYS_REQUEST_PROC ++ case IOCTL_MSYS_REQUEST_PROC_DEVICE: ++ { ++ MSYS_PROC_DEVICE proc_dev; ++ if(copy_from_user((void*)&proc_dev, (void __user *)arg, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ ++ if((err = msys_request_proc_dev(&proc_dev)) == -EEXIST) { ++ MSYS_PRINT("skip since device %s exist\n" , proc_attr->name); ++ } else if(err != 0) { ++ MSYS_ERROR("msys_request_proc_dev failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_dev, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_RELEASE_PROC_DEVICE: ++ { ++ MSYS_PROC_DEVICE proc_dev; ++ if(copy_from_user((void*)&proc_dev, (void __user *)arg, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ ++ if((err = msys_release_proc_dev(&proc_dev)) != 0) { ++ MSYS_ERROR("msys_release_proc_dev failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_dev, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_REQUEST_PROC_ATTRIBUTE: ++ { ++ MSYS_PROC_ATTRIBUTE proc_attr; ++ ++ if(copy_from_user((void*)&proc_attr, (void __user *)arg, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ if((err = msys_request_proc_attr(&proc_attr)) == -EEXIST) { ++ MSYS_PRINT("skip since attribute %s exist\n" , proc_attr.name); ++ } else if(err != 0) { ++ MSYS_ERROR("msys_request_proc_attribute failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_attr, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_RELEASE_PROC_ATTRIBUTE: ++ { ++ MSYS_PROC_ATTRIBUTE proc_attr; ++ ++ if(copy_from_user((void*)&proc_attr, (void __user *)arg, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ ++ if((err = msys_release_proc_attr(&proc_attr)) != 0) { ++ MSYS_ERROR("msys_release_proc_attr failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_attr, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ } ++ break; ++#endif ++#ifdef CONFIG_IOCTL_FLUSH_CACHE ++ case IOCTL_MSYS_FLUSH_CACHE: ++ { ++ if((err = msys_flush_cache(arg))) ++ MSYS_ERROR("IOCTL_MSYS_FLUSH_CACHE error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_FLUSH_MEMORY: ++ { ++ __cpuc_flush_kern_all();//L1 ++ Chip_Flush_Memory();//L3 ++ } ++#endif ++#ifdef CONFIG_IOCTL_IPCM_USELESS ++ case IOCTL_MSYS_RESET_TO_UBOOT: ++ { ++ do ++ { ++ SETREG16(REG_ADDR_STATUS, FORCE_UBOOT_BIT); ++ } while(!(INREG16(REG_ADDR_STATUS) & FORCE_UBOOT_BIT)); ++ OUTREG16(BASE_REG_PMSLEEP_PA + REG_ID_2E, 0x79); ++ } ++ break; ++ ++ case IOCTL_MSYS_REQUEST_FREQUENCY: ++ { ++ if((err = msys_check_freq_cfg(arg))) ++ MSYS_ERROR("IOCTL_MSYS_REQUEST_FREQUENCY error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_CHIPVERSION: ++ { ++ if((err = msys_get_chipVersion_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_GET_CHIPVERSION error!\n"); ++ } ++ break; ++#endif ++#ifdef CONFIG_MS_CPU_FREQ ++ case IOCTL_MSYS_READ_PM_TSENSOR: ++ { ++ int temp = ms_get_temp(); ++ if(copy_to_user( (void __user *)arg, &temp, sizeof(temp) )) ++ return -EFAULT; ++ } ++#endif ++ break; ++ ++ default: ++ MSYS_ERROR("Unknown IOCTL Command 0x%08X\n", cmd); ++ return -ENOTTY; ++ } ++ ++ ++ return err; ++} ++ ++#ifdef CONFIG_MS_SYSTEM_PART_STRING ++static int __init setup_system_part_string(char *arg) ++{ ++ memcpy(system_part_string,(arg+1),strlen(arg)> 13); // test base address[15:0] ++ CLRREG16(BASE_REG_MIU_PA + REG_ID_6F, BIT2|BIT3); // test base address[17:16] ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_72, (mem_info.length >> 4) & 0xFFFF); // test length[15:0] ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_73, (mem_info.length >> 20) & 0x0FFF); // test length[27:16] ++ } ++ return n; ++ } ++ return n; ++} ++DEVICE_ATTR(dmem_alloc, 0200, NULL, alloc_dmem); ++ ++static ssize_t dmem_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ int i=0; ++ unsigned int total=0; ++ ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ str += scnprintf(str, end - str, "%04d : 0x%08X@%08X [%s]\n",i,(unsigned int)entry->dmem_info.length,(unsigned int)entry->dmem_info.phys,entry->dmem_info.name); ++ ++ total+=(unsigned int)entry->dmem_info.length; ++ i++; ++ } ++ ++ str += scnprintf(str, end - str, "\nTOTAL: 0x%08X\n\n",total); ++ ++ return (str - buf); ++} ++DEVICE_ATTR(dmem, 0444, dmem_show, NULL); ++ ++static ssize_t release_dmem_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ int error = 0; ++ const char *str = buf; ++ MSYS_DMEM_INFO mem_info; ++ memset(mem_info.name,0,16); ++ mem_info.phys=0; ++ ++ while (*str && !isspace(*str)) str++; ++ ++ len = str - buf; ++ if (!len) return -EINVAL; ++ ++ len=(len<15)?len:15; ++ memcpy(mem_info.name,buf,len); ++ ++ error = msys_release_dmem(&mem_info); ++ return n; ++ } ++ ++ return 0; ++} ++DEVICE_ATTR(release_dmem, 0200, NULL, release_dmem_store); ++ ++#ifdef CONFIG_MSYS_DMEM_SYSFS_ALL ++static ssize_t dmem_realloc_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", dmem_realloc_enabled); ++ return (str - buf); ++} ++ ++static ssize_t dmem_realloc_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ ++ if(1==len) ++ { ++ if('0'==buf[0]) ++ { ++ dmem_realloc_enabled=0; ++ MSYS_PRINT("dmem realloc disabled\n"); ++ } ++ else if('1'==buf[0]) ++ { ++ dmem_realloc_enabled=1; ++ MSYS_PRINT("dmem realloc enabled\n"); ++ } ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++DEVICE_ATTR(dmem_realloc, 0644, dmem_realloc_show, dmem_realloc_store); ++ ++static ssize_t unfix_dmem_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ int error = 0; ++ const char *str = buf; ++ char nbuf[16]={0}; ++ ++ while (*str && !isspace(*str)) str++; ++ ++ len = str - buf; ++ if (!len) return -EINVAL; ++ ++ len=(len<15)?len:15; ++ memcpy(nbuf,buf,len); ++ ++ error = msys_unfix_dmem(nbuf); ++ return error ? error : n; ++ } ++ ++ return 0; ++} ++DEVICE_ATTR(unfix_dmem, 0200, NULL, unfix_dmem_store); ++ ++static ssize_t fixed_dmem_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ int error = 0; ++ const char *str = buf; ++ char nbuf[16]={0}; ++ ++ while (*str && !isspace(*str)) str++; ++ ++ len = str - buf; ++ if (!len) return -EINVAL; ++ ++ len=(len<15)?len:15; ++ memcpy(nbuf,buf,len); ++ ++ if(1==len){ ++ if('0'==nbuf[0]){ ++ fixed_dmem_enabled=0; ++ MSYS_ERROR("fix_dmem disabled\n" ) ; ++ }else if('1'==nbuf[0]){ ++ fixed_dmem_enabled=1; ++ MSYS_ERROR("fix_dmem enabled\n" ) ; ++ } ++ } ++ ++ error = msys_fix_dmem((char *)nbuf); ++ return error ? error : n; ++ } ++ ++ return 0; ++} ++ ++static ssize_t fixed_dmem_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ int i=0; ++ ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ str += scnprintf(str, end - str, "%04d: %s\n",i,entry->dmem_info.name); ++ i++; ++ } ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(fixed_dmem, 0644, fixed_dmem_show, fixed_dmem_store); ++ ++static ssize_t dmem_retry_count_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ dmem_retry_count = simple_strtoul(buf, NULL, 10); ++ //MSYS_ERROR("dmem_retry_count=%d\n", dmem_retry_count); ++ return n; ++ /* ++ if('0'==buf[0]) ++ { ++ cma_monitor_enabled=0; ++ return n; ++ } ++ else if('1'==buf[0]) ++ { ++ cma_monitor_enabled=1; ++ return n; ++ } ++ else ++ { ++ return -EINVAL; ++ }*/ ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++ ++static ssize_t dmem_retry_count_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", dmem_retry_count); ++ return (str - buf); ++} ++DEVICE_ATTR(dmem_retry_count, 0644, dmem_retry_count_show, dmem_retry_count_store); ++#endif //END of CONFIG_MSYS_DMEM_SYSFS_ALL ++ ++#ifdef CONFIG_MS_CPU_FREQ ++static ssize_t TEMP_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temperature %d\n", ms_get_temp()); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(TEMP_R, 0444, TEMP_show, NULL); ++#endif ++ ++static ssize_t ms_dump_reboot_type(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Reboot_Type: %d\n", msys_get_rebootType()); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(REBOOT_TYPE, 0444, ms_dump_reboot_type, NULL); ++ ++static ssize_t ms_dump_chip_id(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Chip_ID: 0x%X\n", Chip_Get_Device_ID()); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(CHIP_ID, 0444, ms_dump_chip_id, NULL); ++ ++static ssize_t ms_dump_chip_version(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Chip_Version: %d\n", msys_get_chipVersion()); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(CHIP_VERSION, 0444, ms_dump_chip_version, NULL); ++ ++ ++#ifdef CONFIG_SS_PROFILING_TIME ++extern void recode_timestamp(int mark, const char* name); ++extern void recode_show(void); ++static ssize_t profiling_booting_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ int mark=0; ++ ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ ++ if(len) ++ { ++ mark = simple_strtoul(buf, NULL, 10); ++ recode_timestamp(mark, "timestamp"); ++ return n; ++ ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++ ++static ssize_t profiling_booting_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ recode_show(); ++ return 0; ++} ++DEVICE_ATTR(booting_time, 0644, profiling_booting_show, profiling_booting_store); ++#endif ++ ++ ++#ifdef CONFIG_MSYS_REQUEST_PROC ++struct list_head proc_info_head; ++static struct mutex proc_info_mutex; ++static struct proc_dir_entry* proc_class=NULL; ++static struct proc_dir_entry* proc_zen_kernel=NULL; ++ ++struct proc_dir_entry* msys_get_proc_class(void) ++{ ++ return proc_class; ++} ++ ++struct proc_dir_entry* msys_get_proc_zen_kernel(void) ++{ ++ return proc_zen_kernel; ++} ++EXPORT_SYMBOL(msys_get_proc_class); ++ ++static int msys_seq_show(struct seq_file*m, void *p) ++{ ++ struct inode *inode = (struct inode *)m->private; ++ ++ PROC_INFO_LIST *proc_list = proc_get_parent_data(inode); ++ MSYS_PROC_ATTRIBUTE* proc_attr = PDE_DATA(inode); ++ ++ switch(proc_attr->type) ++ { ++ case MSYS_PROC_ATTR_CHAR: ++ seq_printf(m, "%c\n", *(unsigned int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_UINT: ++ seq_printf(m, "%u\n", *(unsigned int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_INT: ++ seq_printf(m, "%d\n", *(int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_XINT: ++ seq_printf(m, "0x%x\n", *(unsigned int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_ULONG: ++ seq_printf(m, "%lu\n", *(unsigned long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_LONG: ++ seq_printf(m, "%ld\n", *(long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_XLONG: ++ seq_printf(m, "0x%lx\n", *(unsigned long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_ULLONG: ++ seq_printf(m, "%llu\n", *(unsigned long long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_LLONG: ++ seq_printf(m, "%lld\n", *(long long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_XLLONG: ++ seq_printf(m, "0x%llx\n", *(unsigned long long*)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_STRING: ++ seq_printf(m, "%s\n", (unsigned char *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int msys_proc_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, msys_seq_show, inode); ++} ++ ++static int msys_proc_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ int ret = 0; ++ struct page *page = NULL; ++ ++ struct inode *inode = (struct inode *)(((struct seq_file *)file->private_data)->private); ++ ++ PROC_INFO_LIST *proc_list = proc_get_parent_data(inode); ++ ++ size_t size = vma->vm_end - vma->vm_start; ++ ++ if (size > proc_list->proc_dev.size) ++ { ++ MSYS_ERROR("msys_proc_mmap - invalid size = %d\n", size); ++ return -EINVAL; ++ } ++ ++ page = virt_to_page((unsigned long)proc_list->proc_addr + (vma->vm_pgoff << PAGE_SHIFT)); ++ ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); ++ if (ret) ++ { ++ MSYS_ERROR("msys_proc_mmap - remap_pfn_range failed.\n"); ++ return ret; ++ } ++ //vma->vm_start = (unsigned long)info_addr; ++ //vma->vm_end = vma->vm_start + PAGE_ALIGN(MAX_LEN); ++ //vma->vm_flags |= VM_SHARED | VM_WRITE | VM_READ; ++ ++ //vma->vm_ops = &rpr_vm_ops; ++ ++ //if (remap_page_range(start, page, PAGE_SIZE, PAGE_SHARED)) ++ // return -EAGAIN; ++ return 0 ; ++} ++ ++ ++static const struct file_operations msys_proc_fops = { ++ .owner = THIS_MODULE, ++ .open = msys_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct file_operations msys_proc_mmap_fops = { ++ .owner = THIS_MODULE, ++ .open = msys_proc_open, ++ .mmap = msys_proc_mmap, ++ .release = single_release, ++}; ++ ++static PROC_INFO_LIST *msys_get_proc_info(MSYS_PROC_DEVICE* proc_dev) ++{ ++ struct list_head *tmp_proc_entry = NULL; ++ PROC_INFO_LIST *tmp_proc_info = NULL; ++ ++ list_for_each(tmp_proc_entry, &proc_info_head) { ++ tmp_proc_info = list_entry(tmp_proc_entry, PROC_INFO_LIST, list); ++ if (tmp_proc_info->proc_dev.parent == proc_dev->parent ++ && strcmp(tmp_proc_info->proc_dev.name, proc_dev->name) == 0) { ++ //MSYS_ERROR("%s: Find %s handle = %p\n", __func__, proc_dev->name, tmp_proc_info); ++ return tmp_proc_info; ++ } ++ } ++ return NULL; ++} ++ ++static PROC_INFO_LIST *msys_get_child_proc_info(PROC_INFO_LIST *parent_proc_info) ++{ ++ struct list_head *tmp_proc_entry = NULL; ++ PROC_INFO_LIST *tmp_proc_info = NULL; ++ ++ list_for_each(tmp_proc_entry, &proc_info_head) { ++ tmp_proc_info = list_entry(tmp_proc_entry, PROC_INFO_LIST, list); ++ if (tmp_proc_info->proc_dev.parent == parent_proc_info) { ++ //MSYS_ERROR("%s; Find %s has child %s = %p\n", __func__, parent_proc_info->proc_dev.name, tmp_proc_info->proc_dev.name, tmp_proc_info); ++ return tmp_proc_info; ++ } ++ } ++ return NULL; ++} ++ ++ ++static int msys_request_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr) ++{ ++ int err = 0; ++ struct proc_dir_entry* tmp_proc_entry; ++ PROC_INFO_LIST *parent_proc_info; ++ MSYS_PROC_ATTRIBUTE *new_proc_attr; ++ ++ mutex_lock(&proc_info_mutex); ++ if(/*proc_attr->name != NULL &&*/ proc_attr->name[0] != 0) { ++ new_proc_attr = (MSYS_PROC_ATTRIBUTE *)kmalloc(sizeof(MSYS_PROC_ATTRIBUTE), GFP_KERNEL); ++ if (!new_proc_attr) { ++ MSYS_ERROR("kmalloc MSYS_PROC_ATTRIBUTE failed!!\n" ); ++ BUG(); ++ } ++ *new_proc_attr = *proc_attr; //It will be freed when release device/attributes. ++ ++ parent_proc_info = new_proc_attr->handle; ++ tmp_proc_entry = proc_create_data(new_proc_attr->name, 0, parent_proc_info->proc_entry, &msys_proc_fops, new_proc_attr); ++ if (!tmp_proc_entry) { ++ //MSYS_ERROR("Skip since attribute %s exists\n", proc_attr->name); ++ err = -EEXIST; ++ kfree(new_proc_attr); ++ } else { ++ //MSYS_ERROR("Set attribute %s handle = %p\n", proc_attr->name, proc_attr->handle); ++ } ++ } ++ mutex_unlock(&proc_info_mutex); ++ return err; ++} ++ ++static int msys_release_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr) ++{ ++ return 0; ++} ++ ++static int msys_request_proc_dev(MSYS_PROC_DEVICE* proc_dev) ++{ ++ int err = 0; ++ PROC_INFO_LIST *new_proc_info = NULL; ++ ++ mutex_lock(&proc_info_mutex); ++ ++ if(/*proc_dev->name != NULL && */proc_dev->name[0] != 0) { ++ if((proc_dev->handle = msys_get_proc_info(proc_dev)) != NULL) { ++ //MSYS_ERROR("Device proc_info %s exist, return original handle = %p\n" , proc_dev->name, proc_dev->handle); ++ err = -EEXIST; ++ goto GG; ++ } ++ ++ new_proc_info = (PROC_INFO_LIST *)kmalloc(sizeof(PROC_INFO_LIST), GFP_KERNEL); ++ if (!new_proc_info) { ++ MSYS_ERROR("kmalloc PROC_INFO_LIST failed!!\n" ); ++ err = -ENOMEM; ++ goto GG; ++ } ++ ++ new_proc_info->proc_entry = proc_mkdir_data(proc_dev->name, 0, ++ (proc_dev->parent)?((PROC_INFO_LIST *)proc_dev->parent)->proc_entry:proc_class, new_proc_info); ++ if (!new_proc_info->proc_entry) { ++ MSYS_ERROR("Skip since device proc_entry %s exists\n", proc_dev->name); ++ err = -EEXIST; ++ kfree(new_proc_info); ++ goto GG; ++ } ++ ++ if (proc_dev->parent && proc_dev->size == 0) { //subdevice case ++ new_proc_info->proc_addr = ((PROC_INFO_LIST *)proc_dev->parent)->proc_addr; ++ } ++ else { //device case ++ if (proc_dev->size & ~PAGE_MASK) { ++ proc_dev->size &= PAGE_MASK; ++ proc_dev->size += PAGE_SIZE; ++ //MSYS_ERROR("Size not align with %ld, resize to %ld\n", PAGE_SIZE, proc_dev->size); ++ } ++ if(proc_dev->size > KMALLOC_MAX_SIZE) ++ { ++ MSYS_ERROR("allocate %lu kernel memory for proc data error\n", proc_dev->size); ++ err = -ENOMEM; ++ kfree(new_proc_info); ++ goto GG; ++ } ++ new_proc_info->proc_addr = kmalloc(proc_dev->size, GFP_KERNEL); ++ if(!new_proc_info->proc_addr) { ++ MSYS_ERROR("allocate %lu kernel memory for proc data error\n", proc_dev->size); ++ err = -ENOMEM; ++ kfree(new_proc_info); ++ goto GG; ++ } ++ proc_create(".mmap", 0, new_proc_info->proc_entry, &msys_proc_mmap_fops); //It will be freed when relealse device. ++ } ++ ++ proc_dev->handle = new_proc_info; ++ new_proc_info->proc_dev = *proc_dev; ++ list_add(&new_proc_info->list, &proc_info_head); ++ //MSYS_ERROR("Set device %s handle = %p\n", new_proc_info->proc_dev.name, new_proc_info->proc_dev.handle); ++ } ++GG: ++ mutex_unlock(&proc_info_mutex); ++ return err; ++} ++ ++static int msys_release_proc_dev(MSYS_PROC_DEVICE* proc_dev) ++{ ++ int err = 0; ++ PROC_INFO_LIST *tmp_proc_info = NULL; ++ PROC_INFO_LIST *target_proc_info = NULL; ++ PROC_INFO_LIST *parent_proc_info = NULL; ++ PROC_INFO_LIST *child_proc_info = NULL; ++ ++ target_proc_info = msys_get_proc_info(proc_dev); ++ mutex_lock(&proc_info_mutex); ++ if(target_proc_info == NULL) { ++ MSYS_ERROR("%s: Cannot find handle of %s\n", __func__, proc_dev->name); ++ err = -ENODEV; ++ } else { ++ //Remove proc_entry ++ proc_remove(target_proc_info->proc_entry); ++ tmp_proc_info = target_proc_info; ++ //Find all proc_info's child from proc_info_list and remove proc_info from bottom which doesn't have child. ++ do { ++ child_proc_info = msys_get_child_proc_info(tmp_proc_info); ++ if(child_proc_info == NULL) { ++ parent_proc_info = tmp_proc_info->proc_dev.parent; ++ //MSYS_ERROR("%s: Free %s handle = %p\n", __func__, tmp_proc_info->proc_dev.name, tmp_proc_info->proc_dev.handle); ++ __list_del_entry(&tmp_proc_info->list); ++ kfree(tmp_proc_info); ++ if(tmp_proc_info != target_proc_info) { ++ tmp_proc_info = parent_proc_info; ++ } else { ++ break; ++ } ++ }else ++ tmp_proc_info = child_proc_info; ++ } while(1); ++ } ++ mutex_unlock(&proc_info_mutex); ++ return err; ++} ++#endif ++static struct class *msys_sysfs_class = NULL; ++ ++struct class *msys_get_sysfs_class(void) ++{ ++ if (!msys_sysfs_class) ++ { ++ msys_sysfs_class = class_create(THIS_MODULE, "mstar"); ++ if (!msys_sysfs_class) ++ MSYS_ERROR("cannot get class for sysfs\n"); ++ } ++ return msys_sysfs_class; ++} ++EXPORT_SYMBOL(msys_get_sysfs_class); ++#if defined(CONFIG_ARCH_INFINITY2) ++extern int msys_dma_copy(MSYS_DMA_COPY *cfg); ++extern int msys_dma_fill(MSYS_DMA_FILL *pstDmaCfg); ++extern int msys_dma_blit(MSYS_DMA_BLIT *pstMdmaCfg); ++ ++#if defined(CONFIG_MS_MOVE_DMA) ++static ssize_t movedma(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ unsigned long long phyaddr_src; // MIU address of source ++ unsigned long long phyaddr_dst; // MIU address of destination ++ unsigned int lineofst_src; // line-offset of source, set 0 to disable line offset ++ unsigned int lineofst_dst; // line-offset of destination, set 0 to disable line offset ++ unsigned int width_src; // width of source, set 0 to disable line offset ++ unsigned int width_dst; // width of destination, set 0 to disable line offset ++ unsigned int length; // total size (bytes) ++ MSYS_DMA_BLIT dmaBlit_info; ++ /* parsing input data */ ++ sscanf(buf, "%llu %llu %d %d %d %d %d", &phyaddr_src, &phyaddr_dst, &lineofst_src, &lineofst_dst, &width_src, &width_dst, &length); ++ ++ dmaBlit_info.phyaddr_src=phyaddr_src; ++ dmaBlit_info.phyaddr_dst=phyaddr_dst; ++ dmaBlit_info.lineofst_src=lineofst_src; ++ dmaBlit_info.lineofst_dst=lineofst_dst; ++ dmaBlit_info.width_src=width_src; ++ dmaBlit_info.width_dst=width_dst; ++ dmaBlit_info.length=length; ++ msys_dma_blit(&dmaBlit_info); ++ printk("msys_dma_blit end \n"); ++ } ++ return n; ++} ++DEVICE_ATTR(movedma, 0200, NULL, movedma); ++#endif ++ ++static ssize_t bytedmacp(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ unsigned long long phyaddr; // MIU address of source ++ unsigned long long desaddr; // MIU address of source ++// unsigned int pattern; // width of destination, set 0 to disable line offset ++ unsigned int length; // total size (bytes) ++ MSYS_DMA_COPY dmaCopy_info; ++ /* parsing input data */ ++ sscanf(buf, "%llu %d %llu", &phyaddr, &length, &desaddr); ++ printk("phyaddr=%llu length=%x desaddr=%llu\n", phyaddr, length, desaddr); ++ dmaCopy_info.phyaddr_src=phyaddr; ++ dmaCopy_info.length=length; ++ dmaCopy_info.phyaddr_dst=desaddr; ++ msys_dma_copy(&dmaCopy_info); ++ printk("msys_dma_copy end \n"); ++ } ++ return n; ++} ++DEVICE_ATTR(bytedmacp, 0200, NULL, bytedmacp); ++ ++static ssize_t bytedma(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ unsigned long long phyaddr; // MIU address of source ++ unsigned int pattern; // width of destination, set 0 to disable line offset ++ unsigned int length; // total size (bytes) ++ MSYS_DMA_FILL dmaFill_info; ++ /* parsing input data */ ++ sscanf(buf, "%llu %d %d", &phyaddr, &length, &pattern); ++ printk("phyaddr=%llu length=%x pattern=%x\n", phyaddr, length, pattern); ++ dmaFill_info.phyaddr=phyaddr; ++ dmaFill_info.length=length; ++ dmaFill_info.pattern=pattern; ++ msys_dma_fill(&dmaFill_info); ++ printk("msys_dma_fill end \n"); ++ } ++ return n; ++} ++DEVICE_ATTR(bytedma, 0200, NULL, bytedma); ++ ++#endif ++static int __init msys_init(void) ++{ ++ int ret; ++ ++ //ret = misc_register(&sys_dev); ++ ret = register_chrdev(MAJOR_SYS_NUM, "msys", &msys_fops); ++ if (ret != 0) { ++ MSYS_ERROR("cannot register msys (err=%d)\n", ret); ++ } ++ ++ sys_dev.this_device = device_create(msys_get_sysfs_class(), NULL, ++ MKDEV(MAJOR_SYS_NUM, MINOR_SYS_NUM), NULL, "msys"); ++ ++ sys_dev.this_device->dma_mask=&sys_dma_mask; ++ sys_dev.this_device->coherent_dma_mask=sys_dma_mask; ++ ++ mutex_init(&dmem_mutex); ++ INIT_LIST_HEAD(&kept_mem_head); ++ INIT_LIST_HEAD(&fixed_mem_head); ++ ++ device_create_file(sys_dev.this_device, &dev_attr_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_dmem_alloc); ++ device_create_file(sys_dev.this_device, &dev_attr_release_dmem); ++#ifdef CONFIG_MSYS_DMEM_SYSFS_ALL ++ device_create_file(sys_dev.this_device, &dev_attr_fixed_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_unfix_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_dmem_retry_count); ++ device_create_file(sys_dev.this_device, &dev_attr_dmem_realloc); ++#endif ++ ++#ifdef CONFIG_MS_PIU_TICK_API ++ device_create_file(sys_dev.this_device, &dev_attr_PIU_T); ++#endif ++ ++#ifdef CONFIG_MS_CPU_FREQ ++ device_create_file(sys_dev.this_device, &dev_attr_TEMP_R); ++#endif ++ ++ device_create_file(sys_dev.this_device, &dev_attr_REBOOT_TYPE); ++ device_create_file(sys_dev.this_device, &dev_attr_CHIP_ID); ++ device_create_file(sys_dev.this_device, &dev_attr_CHIP_VERSION); ++ ++#ifdef CONFIG_MS_US_TICK_API ++ device_create_file(sys_dev.this_device, &dev_attr_us_ticks); ++#endif ++ ++#ifdef CONFIG_SS_PROFILING_TIME ++ device_create_file(sys_dev.this_device, &dev_attr_booting_time); ++#endif ++#if defined(CONFIG_ARCH_INFINITY2) ++#if defined(CONFIG_MS_MOVE_DMA) ++ device_create_file(sys_dev.this_device, &dev_attr_movedma); ++#endif ++ device_create_file(sys_dev.this_device, &dev_attr_bytedma); ++ device_create_file(sys_dev.this_device, &dev_attr_bytedmacp); ++#endif ++#if defined(CONFIG_PROC_FS) && defined(CONFIG_MSYS_REQUEST_PROC) ++ mutex_init(&proc_info_mutex); ++ INIT_LIST_HEAD(&proc_info_head); ++ proc_class=proc_mkdir("mstar",NULL); ++ proc_zen_kernel=proc_mkdir("kernel",proc_class); ++#endif ++ ++ return 0; ++} ++ ++#ifdef CONFIG_MSYS_KFILE_API ++//!!!! msys_kfile_* API has not been tested as they are not used. 2016/07/18 ++struct file* msys_kfile_open(const char* path, int flags, int rights) ++{ ++ struct file* filp = NULL; ++ mm_segment_t oldfs; ++ int err = 0; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ filp = filp_open(path, flags, rights); ++ set_fs(oldfs); ++ if(IS_ERR(filp)) { ++ err = PTR_ERR(filp); ++ return NULL; ++ } ++ return filp; ++} ++EXPORT_SYMBOL(msys_kfile_open); ++ ++void msys_kfile_close(struct file* fp) ++{ ++ if(fp) ++ { ++ filp_close(fp,NULL); ++ } ++} ++EXPORT_SYMBOL(msys_kfile_close); ++ ++int msys_kfile_write(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size) ++{ ++ mm_segment_t oldfs; ++ int ret=-EINVAL; ++ ++ if(fp) ++ { ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_write(fp, data, size, &offset); ++ set_fs(oldfs); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(msys_kfile_write); ++ ++int msys_kfile_read(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ ret = vfs_read(fp, data, size, &offset); ++ ++ set_fs(oldfs); ++ return ret; ++} ++EXPORT_SYMBOL(msys_kfile_read); ++#endif ++ ++#if 0 ++int ssys_get_HZ(void) ++{ ++ return HZ; ++} ++EXPORT_SYMBOL(ssys_get_HZ); ++#endif ++ ++subsys_initcall(msys_init); ++ ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("SYSTEM driver"); ++MODULE_LICENSE("SSTAR"); +diff --git a/drivers/sstar/msys/ms_msys_dma_wrapper.c b/drivers/sstar/msys/ms_msys_dma_wrapper.c +new file mode 100755 +index 000000000000..69f1b9ecafb0 +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys_dma_wrapper.c +@@ -0,0 +1,286 @@ ++#include ++#include /* for get_fs*/ ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include /* for sysctl_compaction_handler*/ ++#include ++ ++#include "registers.h" ++#include "ms_platform.h" ++#include "mdrv_msys_io_st.h" ++#include "mdrv_msys_io.h" ++#include "platform_msys.h" ++#include "hal_bdma.h" ++#include "hal_movedma.h" ++#include "cam_os_wrapper.h" ++ ++extern struct miscdevice sys_dev; ++#if defined(CONFIG_MS_BDMA) ++static CamOsTsem_t m_stBdmaDoneSem[HAL_BDMA_CH_NUM]; ++#endif ++#if defined(CONFIG_MS_MOVE_DMA) ++static CamOsTsem_t m_stMdmaDoneSem; ++#endif ++ ++#if defined(CONFIG_MS_MOVE_DMA) ++void msys_mdma_done(u32 argu) ++{ ++ CamOsTsemUp(&m_stMdmaDoneSem); ++} ++ ++int msys_dma_blit(MSYS_DMA_BLIT *pstMdmaCfg) ++{ ++ HalMoveDmaParam_t tMoveDmaParam; ++ HalMoveDmaLineOfst_t tMoveDmaLineOfst; ++ ++ memset(&tMoveDmaParam, 0, sizeof(HalMoveDmaParam_t)); ++ tMoveDmaParam.u32SrcAddr = pstMdmaCfg->phyaddr_src; ++ tMoveDmaParam.u32SrcMiuSel = (pstMdmaCfg->phyaddr_src < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32DstAddr = pstMdmaCfg->phyaddr_dst; ++ tMoveDmaParam.u32DstMiuSel = (pstMdmaCfg->phyaddr_dst < ARM_MIU1_BASE_ADDR) ? (0) : (1); ++ tMoveDmaParam.u32Count = pstMdmaCfg->length; ++ tMoveDmaParam.CallBackFunc = msys_mdma_done; ++ tMoveDmaParam.CallBackArg = 0; ++ ++ ++ if (pstMdmaCfg->lineofst_src && pstMdmaCfg->lineofst_dst) ++ { ++ if((pstMdmaCfg->lineofst_srcwidth_src) ++ || (pstMdmaCfg->lineofst_dstwidth_dst) ) ++ { ++ printk("[MDMA] CAUTION: line offset is less than width\n" ++ "width_src=0x%x lineofst_src=0x%x, DstWidth=0x%x lineofst_dst=0x%x\n", ++ pstMdmaCfg->width_src, pstMdmaCfg->lineofst_src, pstMdmaCfg->width_dst, pstMdmaCfg->lineofst_dst); ++ dump_stack(); ++ return -1; ++ } ++ ++ tMoveDmaLineOfst.u32SrcWidth = pstMdmaCfg->width_src; ++ tMoveDmaLineOfst.u32SrcOffset = pstMdmaCfg->lineofst_src; ++ tMoveDmaLineOfst.u32DstWidth = pstMdmaCfg->width_dst; ++ tMoveDmaLineOfst.u32DstOffset = pstMdmaCfg->lineofst_dst; ++ ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_LINE_OFFSET; ++ tMoveDmaParam.pstLineOfst = &tMoveDmaLineOfst; ++ } ++ else { ++ tMoveDmaParam.u32Mode = HAL_MOVEDMA_LINEAR; ++ tMoveDmaParam.pstLineOfst = NULL; ++ } ++ ++ if (HAL_MOVEDMA_NO_ERR != HalMoveDma_MoveData(&tMoveDmaParam)) { ++ return -1; ++ } ++ ++ CamOsTsemDownInterruptible(&m_stMdmaDoneSem); ++ ++ return 0; ++} ++EXPORT_SYMBOL(msys_dma_blit); ++#endif ++#if defined(CONFIG_MS_BDMA) ++static void msys_bdma_done(u32 u32DmaCh) ++{ ++ CamOsTsemUp(&m_stBdmaDoneSem[u32DmaCh]); ++} ++ ++int msys_dma_fill(MSYS_DMA_FILL *pstDmaCfg) ++{ ++ HalBdmaParam_t tBdmaParam; ++ u8 u8DmaCh = HAL_BDMA_CH1; ++ memset(&tBdmaParam, 0, sizeof(HalBdmaParam_t)); ++ tBdmaParam.ePathSel = (pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MEM_TO_MIU0) : (HAL_BDMA_MEM_TO_MIU1); ++ tBdmaParam.bIntMode = 1; ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = pstDmaCfg->length; ++ tBdmaParam.pSrcAddr = (void*)0; ++ tBdmaParam.pDstAddr = (pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (void *)((U32)pstDmaCfg->phyaddr) : (void *)((U32)pstDmaCfg->phyaddr - ARM_MIU1_BASE_ADDR); ++ tBdmaParam.pfTxCbFunc = msys_bdma_done; ++ tBdmaParam.u32Pattern = pstDmaCfg->pattern; ++ ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &tBdmaParam)) { ++ return -1; ++ } ++ ++ if (tBdmaParam.bIntMode) { ++ CamOsTsemDownInterruptible(&m_stBdmaDoneSem[u8DmaCh]); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msys_dma_fill); ++ ++int msys_dma_copy(MSYS_DMA_COPY *cfg) ++{ ++ HalBdmaParam_t tBdmaParam; ++#if defined(CONFIG_ARCH_INFINITY2) ++ u8 u8DmaCh = HAL_BDMA_CH1; ++#else ++ u8 u8DmaCh = HAL_BDMA_CH2; ++#endif ++ memset(&tBdmaParam, 0, sizeof(HalBdmaParam_t)); ++ tBdmaParam.ePathSel = ((U32)cfg->phyaddr_src < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MIU0_TO_MIU0) : (HAL_BDMA_MIU1_TO_MIU0); ++ tBdmaParam.ePathSel = ((U32)cfg->phyaddr_dst < ARM_MIU1_BASE_ADDR) ? tBdmaParam.ePathSel : tBdmaParam.ePathSel+1; ++ tBdmaParam.pSrcAddr = ((U32)cfg->phyaddr_src < ARM_MIU1_BASE_ADDR) ? (void *)((U32)cfg->phyaddr_src) : (void *)((U32)cfg->phyaddr_src - ARM_MIU1_BASE_ADDR); ++ tBdmaParam.pDstAddr = ((U32)cfg->phyaddr_dst < ARM_MIU1_BASE_ADDR) ? (void *)((U32)cfg->phyaddr_dst) : (void *)((U32)cfg->phyaddr_dst - ARM_MIU1_BASE_ADDR); ++ tBdmaParam.bIntMode = 1; ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = cfg->length; ++ tBdmaParam.pfTxCbFunc = msys_bdma_done; ++ tBdmaParam.u32Pattern = 0; ++ ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer(u8DmaCh, &tBdmaParam)) { ++ return -1; ++ } ++ ++ if (tBdmaParam.bIntMode) { ++ CamOsTsemDownInterruptible(&m_stBdmaDoneSem[u8DmaCh]); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msys_dma_copy); ++ ++#if defined(CONFIG_MS_BDMA_LINE_OFFSET_ON) ++int msys_dma_fill_lineoffset(MSYS_DMA_FILL_BILT *pstDmaCfg) ++{ ++ HalBdmaParam_t tBdmaParam; ++ HalBdmaLineOfst_t tBdmaLineOfst; ++ u8 u8DmaCh = HAL_BDMA_CH1; ++ ++ memset(&tBdmaParam, 0, sizeof(HalBdmaParam_t)); ++ memset(&tBdmaLineOfst, 0, sizeof(HalBdmaLineOfst_t)); ++ tBdmaParam.ePathSel = (pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MEM_TO_MIU0) : (HAL_BDMA_MEM_TO_MIU1); ++ tBdmaParam.bIntMode = 1; ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = pstDmaCfg->length; ++ tBdmaParam.pSrcAddr = (void*)0; ++ tBdmaParam.pDstAddr = (pstDmaCfg->phyaddr < ARM_MIU1_BASE_ADDR) ? (void *)((U32)pstDmaCfg->phyaddr) : (void *)((U32)pstDmaCfg->phyaddr - ARM_MIU1_BASE_ADDR); ++ tBdmaParam.pfTxCbFunc = msys_bdma_done; ++ tBdmaParam.u32Pattern = pstDmaCfg->pattern; ++ ++ if (pstDmaCfg->lineofst_dst) ++ { ++ if (pstDmaCfg->lineofst_dst < pstDmaCfg->width_dst) ++ { ++ printk("[BDMA] CAUTION: line offset is less than width\n" ++ "DstWidth=0x%x lineofst_dst=0x%x\n", ++ pstDmaCfg->width_dst, pstDmaCfg->lineofst_dst); ++ dump_stack(); ++ return -1; ++ } ++ ++ tBdmaParam.pstLineOfst = &tBdmaLineOfst; ++ tBdmaParam.pstLineOfst->u32SrcWidth = pstDmaCfg->width_dst; ++ tBdmaParam.pstLineOfst->u32SrcOffset = pstDmaCfg->lineofst_dst; ++ tBdmaParam.pstLineOfst->u32DstWidth = pstDmaCfg->width_dst; ++ tBdmaParam.pstLineOfst->u32DstOffset = pstDmaCfg->lineofst_dst; ++ ++ tBdmaParam.bEnLineOfst = 1; ++ } ++ else { ++ tBdmaParam.bEnLineOfst = 0; ++ tBdmaParam.pstLineOfst = NULL; ++ } ++ ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer_LineOffset(u8DmaCh, &tBdmaParam)) { ++ return -1; ++ } ++ ++ if (tBdmaParam.bIntMode) { ++ CamOsTsemDownInterruptible(&m_stBdmaDoneSem[u8DmaCh]); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msys_dma_fill_lineoffset); ++ ++int msys_dma_copy_lineoffset(MSYS_DMA_BLIT *cfg) ++{ ++ HalBdmaParam_t tBdmaParam; ++ HalBdmaLineOfst_t tBdmaLineOfst; ++#if defined(CONFIG_ARCH_INFINITY2) ++ u8 u8DmaCh = HAL_BDMA_CH1; ++#else ++ u8 u8DmaCh = HAL_BDMA_CH2; ++#endif ++ ++ memset(&tBdmaParam, 0, sizeof(HalBdmaParam_t)); ++ memset(&tBdmaLineOfst, 0, sizeof(HalBdmaLineOfst_t)); ++ tBdmaParam.ePathSel = ((U32)cfg->phyaddr_src < ARM_MIU1_BASE_ADDR) ? (HAL_BDMA_MIU0_TO_MIU0) : (HAL_BDMA_MIU1_TO_MIU0); ++ tBdmaParam.ePathSel = ((U32)cfg->phyaddr_dst < ARM_MIU1_BASE_ADDR) ? tBdmaParam.ePathSel : tBdmaParam.ePathSel+1; ++ tBdmaParam.pSrcAddr = ((U32)cfg->phyaddr_src < ARM_MIU1_BASE_ADDR) ? (void *)((U32)cfg->phyaddr_src) : (void *)((U32)cfg->phyaddr_src - ARM_MIU1_BASE_ADDR); ++ tBdmaParam.pDstAddr = ((U32)cfg->phyaddr_dst < ARM_MIU1_BASE_ADDR) ? (void *)((U32)cfg->phyaddr_dst) : (void *)((U32)cfg->phyaddr_dst - ARM_MIU1_BASE_ADDR); ++ tBdmaParam.bIntMode = 1; ++ tBdmaParam.eDstAddrMode = HAL_BDMA_ADDR_INC; ++ tBdmaParam.u32TxCount = cfg->length; ++ tBdmaParam.pfTxCbFunc = msys_bdma_done; ++ tBdmaParam.u32Pattern = 0; ++ ++ if (cfg->lineofst_src && cfg->lineofst_dst) ++ { ++ if((cfg->lineofst_src < cfg->width_src) ++ || (cfg->lineofst_dst < cfg->width_dst) ) ++ { ++ printk("[BDMA] CAUTION: line offset is less than width\n" ++ "width_src=0x%x lineofst_src=0x%x, DstWidth=0x%x lineofst_dst=0x%x\n", ++ cfg->width_src, cfg->lineofst_src, cfg->width_dst, cfg->lineofst_dst); ++ dump_stack(); ++ return -1; ++ } ++ ++ tBdmaParam.pstLineOfst = &tBdmaLineOfst; ++ tBdmaParam.pstLineOfst->u32SrcWidth = cfg->width_src; ++ tBdmaParam.pstLineOfst->u32SrcOffset = cfg->lineofst_src; ++ tBdmaParam.pstLineOfst->u32DstWidth = cfg->width_dst; ++ tBdmaParam.pstLineOfst->u32DstOffset = cfg->lineofst_dst; ++ ++ tBdmaParam.bEnLineOfst = 1; ++ } ++ else { ++ tBdmaParam.bEnLineOfst = 0; ++ tBdmaParam.pstLineOfst = NULL; ++ } ++ ++ if (HAL_BDMA_PROC_DONE != HalBdma_Transfer_LineOffset(u8DmaCh, &tBdmaParam)) { ++ return -1; ++ } ++ ++ if (tBdmaParam.bIntMode) { ++ CamOsTsemDownInterruptible(&m_stBdmaDoneSem[u8DmaCh]); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msys_dma_copy_lineoffset); ++ ++#endif ++ ++#endif ++ ++static int __init ms_msys_dma_wrapper_init(void) ++{ ++#if defined(CONFIG_MS_MOVE_DMA) ++ CamOsTsemInit(&m_stMdmaDoneSem, 0); ++ ++ HalMoveDma_Initialize(); ++#endif ++ ++#if defined(CONFIG_MS_BDMA) ++ CamOsTsemInit(&m_stBdmaDoneSem[0], 0); ++ CamOsTsemInit(&m_stBdmaDoneSem[1], 0); ++ CamOsTsemInit(&m_stBdmaDoneSem[2], 0); ++ CamOsTsemInit(&m_stBdmaDoneSem[3], 0); ++ ++ //HalBdma_Initialize(0); ++ HalBdma_Initialize(1); ++ HalBdma_Initialize(2); ++ HalBdma_Initialize(3); ++#endif ++ return 0; ++} ++subsys_initcall(ms_msys_dma_wrapper_init) +diff --git a/drivers/sstar/msys/ms_msys_irq_stat.c b/drivers/sstar/msys/ms_msys_irq_stat.c +new file mode 100755 +index 000000000000..e98c1e9a930f +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys_irq_stat.c +@@ -0,0 +1,274 @@ ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++ ++#define IRQ_LIST 1000 ++#define KEPT_IRQ_LATENCY_SIZE 50 ++struct list_head kept_irq_head; ++struct list_head kept_sirq_head; ++int sirq_head_initialized =0; ++ ++static DEFINE_SPINLOCK(irq_latency_lock); ++static unsigned int iIrqLatencyCount = 0; ++ ++static DEFINE_SPINLOCK(irq_lock); ++int IRQ_COUNTER = 0; ++int SIRQ_COUNTER = 0; ++extern struct miscdevice sys_dev; ++ ++struct IRQ_INFO_LIST ++{ ++ MSYS_IRQ_INFO irq_info; ++ struct list_head list; ++}; ++ ++struct IRQ_INFO_LIST kept_irq_latency[KEPT_IRQ_LATENCY_SIZE]; ++ ++ ++ ++void msys_dump_irq_latency_info(void) ++{ ++ int i = 0; ++ unsigned long cost; ++ int counter = 0; ++ printk("Irq latency larger than 2ms: %u\n", iIrqLatencyCount); ++ for (i = 0; i< KEPT_IRQ_LATENCY_SIZE; i++) ++ { ++ cost = kept_irq_latency[i].irq_info.timeEnd - kept_irq_latency[i].irq_info.timeStart; ++ ++ counter += 1; ++ if (kept_irq_latency[i].irq_info.IRQNumber <= 32) ++ break; ++ printk( "No: %d, IRQ: %d, cost: %lu us\n", counter, kept_irq_latency[i].irq_info.IRQNumber, (unsigned long)cost >> 10); ++ } ++} ++ ++EXPORT_SYMBOL(msys_dump_irq_latency_info); ++ ++void ms_record_large_latency_in_top(MSYS_IRQ_INFO *irq_info) ++{ ++ unsigned int i = 0; ++ spin_lock(&irq_latency_lock); ++ ++ i = iIrqLatencyCount % KEPT_IRQ_LATENCY_SIZE; ++ ++ iIrqLatencyCount ++; ++ memcpy(&kept_irq_latency[i].irq_info, irq_info, sizeof(MSYS_IRQ_INFO)); ++ ++ spin_unlock(&irq_latency_lock); ++} ++ ++ ++ ++void ms_records_irq(MSYS_IRQ_INFO *irq_info) ++{ ++ struct IRQ_INFO_LIST *new, *old_entry = NULL; ++ struct list_head *ptr; ++ spin_lock(&irq_lock); ++ new=(struct IRQ_INFO_LIST *)kmalloc(sizeof(struct IRQ_INFO_LIST), GFP_KERNEL); ++ ++ if(new!=NULL) ++ { ++ if (IRQ_COUNTER > IRQ_LIST) ++ { ++ list_for_each_prev(ptr, &kept_irq_head) ++ { ++ ++ old_entry = list_entry(ptr, struct IRQ_INFO_LIST, list); ++ break; ++ } ++ list_del_init(&old_entry->list); ++ kfree(old_entry); ++ } ++ memcpy(&new->irq_info, irq_info, sizeof(MSYS_IRQ_INFO)); ++ list_add(&new->list, &kept_irq_head); ++ IRQ_COUNTER += 1; ++ ++ } ++ else ++ goto BEACH; ++ ++BEACH: ++ spin_unlock(&irq_lock); ++} ++ ++#define IRQ_SIZE 512 ++unsigned int count[IRQ_SIZE] ={0}; ++void ms_records_irq_count(int irq_num) ++{ ++ count[irq_num]++; ++} ++void ms_dump_irq_count(void) ++{ ++ int i; ++ printk("ms_dump_irq_count\n"); ++ for(i=0; i0) ++ { ++ printk( "irq:%03d count:%8d\n",i, count[i]); ++ } ++ } ++} ++ ++static ssize_t ms_dump_irqcnt_records(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ char *str = buf; ++// char *end = buf + PAGE_SIZE; ++ ++ //str += scnprintf(str, end - str, "Start Dump IRQ\n"); ++ ms_dump_irq_count(); ++ return (str - buf); ++} ++ ++DEVICE_ATTR(IRQ_COUNT, 0444, ms_dump_irqcnt_records, NULL); ++ ++void ms_records_sirq(MSYS_IRQ_INFO *irq_info) ++{ ++ struct IRQ_INFO_LIST *new, *old_entry = NULL; ++ struct list_head *ptr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&irq_lock, flags); ++ new=(struct IRQ_INFO_LIST *)kmalloc(sizeof(struct IRQ_INFO_LIST), GFP_ATOMIC); ++ ++ if(new!=NULL) ++ { ++ if (SIRQ_COUNTER > IRQ_LIST) ++ { ++ list_for_each_prev(ptr, &kept_sirq_head) ++ { ++ ++ old_entry = list_entry(ptr, struct IRQ_INFO_LIST, list); ++ break; ++ } ++ list_del_init(&old_entry->list); ++ kfree(old_entry); ++ } ++ memcpy(&new->irq_info, irq_info, sizeof(MSYS_IRQ_INFO)); ++ list_add(&new->list, &kept_sirq_head); ++ SIRQ_COUNTER += 1; ++ ++ } ++ else ++ goto BEACH; ++ ++BEACH: ++ spin_unlock_irqrestore(&irq_lock, flags); ++} ++ ++ ++void msys_dump_irq_info(void) ++{ ++ struct list_head *ptr; ++ struct IRQ_INFO_LIST *entry; ++ unsigned long nanosec_rem = 0; ++ unsigned long nanosec_end_rem = 0; ++ unsigned long long start = 0; ++ unsigned long long end = 0; ++ unsigned long cost; ++ ++ int counter = 0; ++ printk("IRQ_COUNTER:%d \n",IRQ_COUNTER); ++ ++ list_for_each(ptr, &kept_irq_head) ++ { ++ entry = list_entry(ptr, struct IRQ_INFO_LIST, list); ++ cost = entry->irq_info.timeEnd - (unsigned long) entry->irq_info.timeStart; ++ start = entry->irq_info.timeStart; ++ end = entry->irq_info.timeEnd; ++ ++ nanosec_rem = do_div(start, 1000000000); ++ nanosec_end_rem = do_div(end, 1000000000); ++ counter += 1; ++ printk( "No: %03d, IRQ: %02d, cost: %lu ns, timestamp: (%5lu.%06lu) - (%5lu.%06lu) \n", counter, entry->irq_info.IRQNumber, (unsigned long)cost, ( ++ unsigned long)start, nanosec_rem / 1000, (unsigned long)end, nanosec_end_rem / 1000); ++ ++ } ++} ++ ++void msys_dump_sirq_info(void) ++{ ++ struct list_head *ptr; ++ struct IRQ_INFO_LIST *entry; ++ unsigned long nanosec_rem = 0; ++ unsigned long nanosec_end_rem = 0; ++ unsigned long long start = 0; ++ unsigned long long end = 0; ++ unsigned long cost; ++ ++ int counter = 0; ++ printk("Soft IRQ_COUNTER:%d \n",SIRQ_COUNTER); ++ ++ list_for_each(ptr, &kept_sirq_head) ++ { ++ entry = list_entry(ptr, struct IRQ_INFO_LIST, list); ++ cost = entry->irq_info.timeEnd - (unsigned long) entry->irq_info.timeStart; ++ start = entry->irq_info.timeStart; ++ end = entry->irq_info.timeEnd; ++ ++ nanosec_rem = do_div(start, 1000000000); ++ nanosec_end_rem = do_div(end, 1000000000); ++ counter += 1; ++ printk( "No: %03d, vec_nr: %02d, cost: %lu ns, action: %p\n", counter, entry->irq_info.IRQNumber, (unsigned long)cost, entry->irq_info.action); ++ ++ } ++} ++ ++static ssize_t ms_dump_irq_records(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Start Dump IRQ\n"); ++ msys_dump_irq_info(); ++ return (str - buf); ++} ++ ++DEVICE_ATTR(IRQ_INFO, 0444, ms_dump_irq_records, NULL); ++static ssize_t ms_dump_sirq_records(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Start Dump Soft IRQ\n"); ++ msys_dump_sirq_info(); ++ return (str - buf); ++} ++ ++DEVICE_ATTR(SIRQ_INFO, 0444, ms_dump_sirq_records, NULL); ++ ++ ++static ssize_t ms_dump_irq_latency_records(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Start Dump IRQ Latency Info\n"); ++ msys_dump_irq_latency_info(); ++ return (str - buf); ++} ++ ++DEVICE_ATTR(IRQ_Latency_in_top, 0444, ms_dump_irq_latency_records, NULL); ++ ++int msys_irq_stat_init(void) ++{ ++ sirq_head_initialized=1; ++ INIT_LIST_HEAD(&kept_irq_head); ++ INIT_LIST_HEAD(&kept_sirq_head); ++ device_create_file(sys_dev.this_device, &dev_attr_IRQ_INFO); ++ device_create_file(sys_dev.this_device, &dev_attr_SIRQ_INFO); ++ device_create_file(sys_dev.this_device, &dev_attr_IRQ_COUNT); ++ device_create_file(sys_dev.this_device, &dev_attr_IRQ_Latency_in_top); ++ ++ return 0; ++} ++device_initcall(msys_irq_stat_init); +diff --git a/drivers/sstar/msys/ms_msys_log.c b/drivers/sstar/msys/ms_msys_log.c +new file mode 100755 +index 000000000000..37f297d210a7 +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys_log.c +@@ -0,0 +1,1393 @@ ++/* ++* ms_msys_log.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//#define FUNC_DEBUG_LEVEL ++//#define FUNC_STORE_PATH ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// @file mi_vdec_impl.c ++/// @brief vdec module impl ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++/* Porting ++#include "mi/mi_sys_datatype.h" ++#include "mi/mi_common.h" ++*/ ++ ++#if !defined(TRUE) && !defined(FALSE) ++#define TRUE 1 ++#define FALSE 0 ++#endif ++#define MI_SUCCESS (0) ++#define MI_ERR_SYS_FAILED (-1) ++#define MI_ERR_SYS_NOT_PERM (-1) ++typedef unsigned char MI_U8; // 1 byte ++typedef unsigned int MI_U32; // 4 bytes ++typedef signed char MI_S8; // 1 byte ++typedef signed int MI_S32; // 4 bytes ++typedef unsigned long long MI_PHY; // 8 bytes ++typedef unsigned char MI_BOOL; ++#define MSG_FROM_USER 0 ++#define MSG_FROM_KERNEL 1 ++ ++ ++#define LOG_RINGBUFFER_SIZE (256 * 1024) ++#define DEBUG_MSG_BUF_SIZE (1024 * 4) ++#define MI_LOG_LEVEL_DEFAULT E_MI_ERR_LEVEL_ERROR ++#define MAX_FILENAME_LENTH 256 ++ ++ ++ ++#ifdef FUNC_DEBUG_LEVEL ++#include "mi/mi_print.h" ++#include "mi/mi_common_macro.h" ++ ++void _MSYS_IMPL_ModuleIdToPrefixName(MI_ModuleId_e eModuleId , char *prefix_name) ++{ ++ switch(eModuleId) ++ { ++ case E_MI_MODULE_ID_IVE: ++ strcpy(prefix_name,"mi_ive"); ++ break; ++ case E_MI_MODULE_ID_VDF: ++ strcpy(prefix_name,"mi_vdf"); ++ break; ++ case E_MI_MODULE_ID_VENC: ++ strcpy(prefix_name,"mi_venc"); ++ break; ++ case E_MI_MODULE_ID_RGN: ++ strcpy(prefix_name,"mi_rgn"); ++ break; ++ case E_MI_MODULE_ID_AI: ++ strcpy(prefix_name,"mi_ai"); ++ break; ++ case E_MI_MODULE_ID_AO: ++ strcpy(prefix_name,"mi_ao"); ++ break; ++ case E_MI_MODULE_ID_VIF: ++ strcpy(prefix_name,"mi_vif"); ++ break; ++ case E_MI_MODULE_ID_VPE: ++ strcpy(prefix_name,"mi_vpe"); ++ break; ++ case E_MI_MODULE_ID_VDEC: ++ strcpy(prefix_name,"mi_vdec"); ++ break; ++ case E_MI_MODULE_ID_SYS: ++ strcpy(prefix_name,"mi_sys"); ++ break; ++ case E_MI_MODULE_ID_FB: ++ strcpy(prefix_name,"mi_fb"); ++ break; ++ case E_MI_MODULE_ID_HDMI: ++ strcpy(prefix_name,"mi_hdmi"); ++ break; ++ case E_MI_MODULE_ID_DIVP: ++ strcpy(prefix_name,"mi_divp"); ++ break; ++ case E_MI_MODULE_ID_GFX: ++ strcpy(prefix_name,"mi_gfx"); ++ break; ++ case E_MI_MODULE_ID_VDISP: ++ strcpy(prefix_name,"mi_vdisp"); ++ break; ++ case E_MI_MODULE_ID_DISP: ++ strcpy(prefix_name,"mi_disp"); ++ break; ++ case E_MI_MODULE_ID_OS: ++ strcpy(prefix_name,"mi_os"); ++ break; ++ case E_MI_MODULE_ID_IAE: ++ strcpy(prefix_name,"mi_iae"); ++ break; ++ case E_MI_MODULE_ID_MD: ++ strcpy(prefix_name,"mi_md"); ++ break; ++ case E_MI_MODULE_ID_OD: ++ strcpy(prefix_name,"mi_od"); ++ break; ++ case E_MI_MODULE_ID_SHADOW: ++ strcpy(prefix_name,"mi_shadow"); ++ break; ++ case E_MI_MODULE_ID_WARP: ++ strcpy(prefix_name,"mi_warp"); ++ break; ++ case E_MI_MODULE_ID_UAC: ++ strcpy(prefix_name,"mi_uac"); ++ break; ++ case E_MI_MODULE_ID_LDC: ++ strcpy(prefix_name,"mi_ldc"); ++ break; ++ case E_MI_MODULE_ID_SD: ++ strcpy(prefix_name,"mi_sd"); ++ break; ++ default: ++ DBG_ERR("fail,error!!! eModuleId is %d ,bigger than E_MI_MODULE_ID_MAX=%d\n",eModuleId,E_MI_MODULE_ID_MAX); ++ MI_SYS_BUG_ON(1); ++ break; ++ ++ } ++ return; ++} ++ ++#else ++#define MI_PRINT printk ++#define DBG_INFO printk ++#define DBG_WRN printk ++#define DBG_ERR printk ++#endif ++ ++ ++typedef struct MI_SYS_LogBufferInfo_S ++{ ++ MI_PHY phyStartAddrPhy; /*start physic address*/ /*CNcomment:»º³åÇøÆðʼÎïÀíµØÖ·*/ ++ MI_U8 *pu8StartAddrVir; /*start virtual address*/ /*CNcomment:»º³åÇøÆðʼÃéÄâµØÖ·*/ ++ MI_U32 u32BufSize; /*buffer size*/ /*CNcomment:»º³åÇø´óá*/ ++ MI_U32 u32WriteAddr; /*write offset*/ /*CNcomment:ôµØÖ·Æ«ÒÆ*/ ++ MI_U32 u32ReadAddr; /*read offset*/ /*CNcomment:¶ÃµØÖ·Æ«ÒÆ*/ ++ MI_U32 u32ResetFlag; /*reset count*/ /*CNcomment:¸´Î»´ÎÊý*/ ++ MI_U32 u32WriteCount; /*write count*/ /*CNcomment:ôÈë´ÎÊý*/ ++ wait_queue_head_t wqNoData; /*no wait queque*/ /*CNcomment:ûÓÃÊý¾ÃµÈ´ý¶ÓÃÃ*/ ++ struct semaphore semWrite; /*write semaphore*/ /*CNcomment:ôbufferÃźÅÿ*/ ++}MI_SYS_LogBufferInfo_t; ++ ++#ifdef FUNC_DEBUG_LEVEL ++/*structure of mode log level */ ++typedef struct MI_SYS_LogConfigInfo_S ++{ ++ MI_U8 u8ModName[16+12]; /*mode name 16 + '_' 1 + pid 10 */ ++ MI_DBG_LEVEL_e eLogLevel; /*log level*//*CNcomment: Ä£¿é´òÓ¡¼¶±ð¿ØÖÆ */ ++ MI_SYS_LogOutputPos_e eLogPrintPos; /*log output location, 0:serial port; 1:network;2:u-disk*//*CNcomment: Ä£¿é´òӡλÖÿØÖÆ 0:´®¿Ú 1:ÃøÂç 2:UÃ…ÃŒ */ ++ MI_U8 u8UdiskFlag; /* u-disk log flag */ ++ MI_U8 reserved; /* u-disk log flag */ ++}MI_SYS_LogConfigInfo_t; ++#define LOG_CONFIG_BUF_SIZE (sizeof(MI_SYS_LogConfigInfo_t) * E_MI_MODULE_ID_MAX) ++static MI_SYS_LogConfigInfo_t *_gpstLogConfigInfo = NULL; ++char *DebugLevelName[MI_DBG_ALL+1] = { ++ "NONE", ++ "ERR", ++ "WRN", ++ "INFO", ++ "ALL", ++}; ++typedef struct MSYS_LogBuffer_s ++{ ++ void* pStartVirAddr; ++ MI_PHY phyStartPhyAddr; ++ MI_U32 u32Size; ++}MSYS_LogBuffer_t; ++static MSYS_LogBuffer_t _gstLogBuffer; ++ ++#endif ++#if 0 ++typedef struct MI_SYS_LogBufRead_S ++{ ++ MI_PHY pHyAddr; ++ MI_U32 u32BufLen; ++ MI_U32 u32CopyedLen; ++}MI_SYS_LogBufRead_t; ++ ++typedef struct MI_SYS_LogBufWrite_S ++{ ++ MI_PHY pHyAddr; ++ MI_U32 u32BufLen; ++}MI_SYS_LogBufWrite_t; ++#endif ++ ++ ++ ++typedef enum ++{ ++ E_MI_SYS_LOG_OUTPUT_SERIAL = 0, ++ E_MI_SYS_LOG_OUTPUT_NETWORK, ++ E_MI_SYS_LOG_OUTPUT_UDISK, ++ E_MI_SYS_LOG_OUTPUT_DBG, ++}MI_SYS_LogOutputPos_e; ++ ++ ++ ++static MI_SYS_LogBufferInfo_t _gstLogBufferInfo; ++static struct task_struct *gpLogUdiskTask = NULL; ++static MI_U8 _gu8LogInit = 0; ++static MI_BOOL _gbSetLogFileFlag = FALSE; ++static MI_BOOL _gbLogOutDbg = FALSE; ++static char g_szPathBuf[MAX_FILENAME_LENTH] = {0}; ++static char *UdiskLogFile = g_szPathBuf; ++static MI_U8 _gu8LogLevel = 7; ++ ++#ifdef FUNC_STORE_PATH ++static char g_szStorePathBuf[MAX_FILENAME_LENTH] = "/mnt"; ++char *StorePath = g_szStorePathBuf; ++#endif ++struct proc_dir_entry *g_pCMPI_proc = NULL; ++ ++DEFINE_SEMAPHORE(_gLogFileMutex); ++DEFINE_SPINLOCK(_gLogFileLock); ++ ++#define LOG_FILE_LOCK() down_interruptible(&_gLogFileMutex) ++#define LOG_FILE_UNLOCK() up(&_gLogFileMutex) ++#define LOG_MAX_TRACE_LEN 256 ++ ++ ++struct file* FileOpen(const MI_S8* ps8FileName, MI_S32 s32Flags) ++{ ++ struct file *pFile = NULL; ++ ++ if (NULL == ps8FileName) ++ { ++ return NULL; ++ } ++ ++ if (s32Flags == 0) ++ { ++ s32Flags = O_RDONLY; ++ } ++ else ++ { ++ s32Flags = O_WRONLY | O_CREAT | O_APPEND; ++ } ++ ++ pFile = filp_open(ps8FileName, s32Flags | O_LARGEFILE, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++ ++ return (IS_ERR(pFile)) ? NULL : pFile; ++} ++ ++ ++void FileClose(struct file * pFile) ++{ ++ if ( NULL != pFile ) ++ { ++ filp_close(pFile, NULL); ++ } ++ ++ return; ++} ++ ++MI_S32 FileRead(struct file * pFile, MI_U8* ps8Buf, MI_U32 u32Len) ++{ ++ MI_S32 s32ReadLen = 0; ++ mm_segment_t stOld_FS = {0}; ++ ++ if (pFile == NULL || NULL == ps8Buf) ++ { ++ return -ENOENT; /* No such file or directory */ ++ } ++ ++#if LINUX_VERSION_CODE == KERNEL_VERSION(3,10,40) || LINUX_VERSION_CODE == KERNEL_VERSION(3,18,30) ++ if (pFile->f_op->read == NULL) ++ { ++ return -ENOSYS; /* Function not implemented */ ++ } ++#endif ++ ++ if (((pFile->f_flags & O_ACCMODE) & (O_RDONLY | O_RDWR)) != 0) ++ { ++ return -EACCES; /* Permission denied */ ++ } ++ ++ /* saved the original file space */ ++ stOld_FS = get_fs(); ++ ++ /* extend to the kernel data space */ ++ set_fs(KERNEL_DS); ++ ++#if LINUX_VERSION_CODE == KERNEL_VERSION(3,10,40) || LINUX_VERSION_CODE == KERNEL_VERSION(3,18,30) ++ s32ReadLen = pFile->f_op->read(pFile, ps8Buf, u32Len, &pFile->f_pos); ++#elif LINUX_VERSION_CODE == KERNEL_VERSION(4,9,84) ++ s32ReadLen = vfs_read(pFile, ps8Buf, u32Len, &pFile->f_pos); ++#else ++#error not support this kernel version ++#endif ++ /* Restore the original file space */ ++ set_fs(stOld_FS); ++ ++ return s32ReadLen; ++} ++ ++ ++MI_S32 FileWrite(struct file* pFile, MI_S8* ps8Buf, MI_U32 u32Len , MI_BOOL bFlag) ++{ ++ MI_S32 s32WriteLen = 0; ++ mm_segment_t stOld_FS = {0}; ++ ++ if (pFile == NULL || ps8Buf == NULL) ++ { ++ return -ENOENT; /* No such file or directory */ ++ } ++ ++#if LINUX_VERSION_CODE == KERNEL_VERSION(3,10,40) || LINUX_VERSION_CODE == KERNEL_VERSION(3,18,30) ++ if (pFile->f_op->write == NULL) ++ { ++ return -ENOSYS; /* Function not implemented */ ++ } ++#endif ++ ++ if (((pFile->f_flags & O_ACCMODE) & (O_WRONLY | O_RDWR)) == 0) ++ { ++ return -EACCES; /* Permission denied */ ++ } ++ ++ stOld_FS = get_fs(); ++ set_fs(KERNEL_DS); ++ ++#if LINUX_VERSION_CODE == KERNEL_VERSION(3,10,40) || LINUX_VERSION_CODE == KERNEL_VERSION(3,18,30) ++ if(bFlag) ++ pFile->f_op->llseek(pFile, 0, SEEK_SET); ++ ++ s32WriteLen = pFile->f_op->write(pFile, ps8Buf, u32Len, &pFile->f_pos); ++#elif LINUX_VERSION_CODE == KERNEL_VERSION(4,9,84) ++ if(bFlag) ++ vfs_llseek(pFile, 0, SEEK_SET); ++ ++ s32WriteLen =vfs_write(pFile, ps8Buf, u32Len, &pFile->f_pos); ++#else ++#error not support this kernel version ++#endif ++ set_fs(stOld_FS); ++ ++ return s32WriteLen; ++} ++ ++ ++MI_S32 FileLseek(struct file *pFile, MI_S32 s32Offset, MI_S32 s32Whence) ++{ ++ MI_S32 s32Ret; ++ ++ loff_t res = vfs_llseek(pFile, s32Offset, s32Whence); ++ s32Ret = res; ++ if (res != (loff_t)s32Ret) ++ s32Ret = -EOVERFLOW; ++ ++ return s32Ret; ++} ++ ++ ++static int SeperateString(char *s, char **left, char **right) ++{ ++ char *p = s; ++ /* find '=' */ ++ while(*p != '\0' && *p++ != '='); ++ ++ if (*--p != '=') ++ return -1; ++ ++ /* seperate left from right vaule by '=' */ ++ *p = '\0'; ++ *left = s; ++ *right = p + 1; ++ return 0; ++} ++ ++static char *StripString(char *s, char *d) ++{ ++ char *p = d; ++ do{ ++ if (*s == '\n') ++ *s = '\0'; ++ if (*s != ' ') ++ *p++ = *s; ++ }while(*s++ != '\0'); ++ return d; ++} ++MI_S32 MSYS_LOG_IMPL_Snprintf(MI_U8 *pu8Str, MI_U32 u32Len, const MI_U8 *pszFormat, ...) ++{ ++ MI_S32 s32Len = 0; ++ va_list stArgs = {0}; ++ ++ va_start(stArgs, pszFormat); ++ s32Len = vsnprintf(pu8Str, u32Len, pszFormat, stArgs); ++ va_end(stArgs); ++ ++ return s32Len; ++} ++ ++#ifdef FUNC_DEBUG_LEVEL ++ ++static int SearchMod(char *s) ++{ ++ int i= 0; ++ int cnt = (int)E_MI_MODULE_ID_MAX; ++ ++ for (i = 0; i < cnt; i++){ ++ if (!strncasecmp(_gpstLogConfigInfo[i].u8ModName, s, sizeof(_gpstLogConfigInfo[i].u8ModName))) ++ return i; ++ } ++ return -1; ++} ++ ++ ++ ++static char *strlwr(char *s) ++{ ++ char *str; ++ str = s; ++ while(*str != '\0') ++ { ++ if(*str >= 'A' && *str <= 'Z') ++ { ++ *str += 'a'-'A'; ++ } ++ str++; ++ } ++ return s; ++} ++ ++MI_DBG_LEVEL_e GetModuleLevel(MI_U8* szProcName) ++{ ++ MI_DBG_LEVEL_e eLevel = MI_LOG_LEVEL_DEFAULT; ++ char path[256]; ++ struct file *pFile = NULL; ++ MI_S8 s8buf = 0; ++ ++ snprintf(path, sizeof(path), "/sys/module/%s/parameters/debug_level", strlwr(szProcName)); ++ ++ pFile = FileOpen(path , 1); ++ if(pFile) ++ { ++ FileRead(pFile , &s8buf , 1); ++ FileClose(pFile); ++ eLevel = (MI_DBG_LEVEL_e)(s8buf - 48); ++ } ++ else ++ { ++ eLevel = MI_LOG_LEVEL_DEFAULT; ++ } ++ return eLevel; ++} ++ ++MI_S32 SetModuleLevel(MI_U8* szProcName , int level) ++{ ++ char path[256]; ++ struct file *pFile = NULL; ++ MI_S8 s8buf = 0; ++ ++ snprintf(path, sizeof(path), "/sys/module/%s/parameters/debug_level", strlwr(szProcName)); ++ pFile = FileOpen(path , 1); ++ if(pFile) ++ { ++ s8buf = 48 + level; ++ FileWrite(pFile , &s8buf , 1 , 1); ++ FileClose(pFile); ++ return 0; ++ } ++ return -1; ++} ++ ++ ++MI_S32 _MSYS_LOG_IMPL_ConfigInfoInit(void) ++{ ++ int ModuleIdx = 0; ++ #if 0 ++ if(MI_SUCCESS != mi_sys_MMA_Alloc(NULL,LOG_CONFIG_BUF_SIZE,&_gstLogBuffer.phyStartPhyAddr)) ++ { ++ DBG_ERR("mma alloc fail\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ _gstLogBuffer.pStartVirAddr = mi_sys_Vmap(_gstLogBuffer.phyStartPhyAddr,LOG_CONFIG_BUF_SIZE,FALSE); ++ if(!_gstLogBuffer.pStartVirAddr) ++ { ++ DBG_ERR("call mi_sys_Vmap fail\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ #else ++ _gstLogBuffer.pStartVirAddr = kmalloc(LOG_CONFIG_BUF_SIZE, GFP_KERNEL); ++ if(_gstLogBuffer.pStartVirAddr==NULL) ++ { ++ DBG_ERR("mma alloc fail\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ #endif ++ ++ memset(_gstLogBuffer.pStartVirAddr , 0 , LOG_CONFIG_BUF_SIZE); ++ ++ _gpstLogConfigInfo = (MI_SYS_LogConfigInfo_t *)_gstLogBuffer.pStartVirAddr; ++ ++ for(ModuleIdx = 0 ; ModuleIdx < (int)E_MI_MODULE_ID_MAX ; ModuleIdx ++) ++ { ++ _gpstLogConfigInfo[ModuleIdx].eLogLevel = MI_LOG_LEVEL_DEFAULT; ++ _gpstLogConfigInfo[ModuleIdx].eLogPrintPos = E_MI_SYS_LOG_OUTPUT_SERIAL; ++ MSYS_LOG_IMPL_Snprintf(_gpstLogConfigInfo[ModuleIdx].u8ModName, sizeof(_gpstLogConfigInfo[ModuleIdx].u8ModName), "modulemax"); ++ } ++ ++ return MI_SUCCESS; ++} ++#endif ++ ++MI_S32 _MSYS_LOG_IMPL_LogBufferInit(void) ++{ ++ memset(&_gstLogBufferInfo , 0 , sizeof(_gstLogBufferInfo)); ++ ++ _gstLogBufferInfo.u32BufSize = LOG_RINGBUFFER_SIZE; ++ ++ ++ init_waitqueue_head(&(_gstLogBufferInfo.wqNoData)); ++ sema_init(&_gstLogBufferInfo.semWrite, 1); ++ #if 0 ++ if(MI_SUCCESS != mi_sys_MMA_Alloc(NULL,LOG_RINGBUFFER_SIZE,&_gstLogBufferInfo.phyStartAddrPhy)) ++ { ++ DBG_ERR("mma alloc fail\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ _gstLogBufferInfo.pu8StartAddrVir = mi_sys_Vmap(_gstLogBufferInfo.phyStartAddrPhy,256 * DEBUG_MSG_BUF_SIZE ,FALSE); ++ if(!_gstLogBufferInfo.pu8StartAddrVir) ++ { ++ DBG_ERR("call mi_sys_Vmap fail\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ #else ++ _gstLogBufferInfo.pu8StartAddrVir = kmalloc(_gstLogBufferInfo.u32BufSize, GFP_KERNEL); ++ if(_gstLogBufferInfo.pu8StartAddrVir==NULL) ++ { ++ DBG_ERR("memory alloc fail\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ #endif ++ return MI_SUCCESS; ++} ++ ++MI_S32 LogUdiskSave(const MI_S8* pFileName, MI_S8* pData, MI_U32 u32DataLen) ++{ ++ MI_S32 s32WriteLen = 0; ++ struct file* pFile = NULL; ++ ++ pFile = FileOpen(pFileName, 1); ++ if(pFile == NULL) ++ { ++ DBG_ERR("FileOpen %s failure..............\n", pFileName); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ s32WriteLen = FileWrite(pFile, pData, u32DataLen , FALSE); ++ ++ FileClose(pFile); ++ ++ return MI_SUCCESS; ++} ++ ++static void LOGBufferReset(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&_gLogFileLock, flags); ++ _gstLogBufferInfo.u32ReadAddr = _gstLogBufferInfo.u32WriteAddr; ++ _gstLogBufferInfo.u32ResetFlag++; ++ spin_unlock_irqrestore(&_gLogFileLock, flags); ++} ++ ++static MI_SYS_LogOutputPos_e GetLogPrintMode(void) ++{ ++ MI_SYS_LogOutputPos_e ePos = 0; ++ ++ if (0 == _gu8LogInit) ++ { ++ return E_MI_SYS_LOG_OUTPUT_SERIAL; ++ } ++ if (_gbSetLogFileFlag == TRUE) ++ { ++ ePos = E_MI_SYS_LOG_OUTPUT_UDISK; ++ } ++ else ++ ePos = E_MI_SYS_LOG_OUTPUT_SERIAL; ++ ++ ++ if (_gbLogOutDbg == TRUE) ++ { ++ ePos = E_MI_SYS_LOG_OUTPUT_DBG; ++ } ++ ++ return ePos; ++} ++inline MI_U32 GetTimeMs(void) ++{ ++ struct timeval tv; ++ do_gettimeofday(&tv); ++ return (((MI_U32)tv.tv_sec)*1000 + ((MI_U32)tv.tv_usec)/1000); ++} ++ ++ ++MI_S32 MSYS_LOG_IMPL_WriteBuf(MI_U8 *pu8Buf, MI_U32 u32MsgLen, MI_U32 u32UserOrKer) ++{ ++ MI_U32 u32CopyLen1; ++ MI_U32 u32CopyLen2; ++ MI_U32 u32NewWriteAddr; ++ ++ if (0 == _gstLogBufferInfo.u32BufSize) ++ { ++ return MI_SUCCESS; ++ } ++ down(&_gstLogBufferInfo.semWrite); ++ if(_gstLogBufferInfo.u32WriteAddr < _gstLogBufferInfo.u32ReadAddr) ++ { ++ if ((_gstLogBufferInfo.u32ReadAddr - _gstLogBufferInfo.u32WriteAddr) ++ < DEBUG_MSG_BUF_SIZE) ++ { ++ LOGBufferReset(); ++ } ++ } ++ else ++ { ++ if ((_gstLogBufferInfo.u32WriteAddr - _gstLogBufferInfo.u32ReadAddr) ++ > (_gstLogBufferInfo.u32BufSize - DEBUG_MSG_BUF_SIZE)) ++ { ++ LOGBufferReset(); ++ } ++ } ++ ++ if ((u32MsgLen + _gstLogBufferInfo.u32WriteAddr) >= _gstLogBufferInfo.u32BufSize) ++ { ++ u32CopyLen1 = _gstLogBufferInfo.u32BufSize - _gstLogBufferInfo.u32WriteAddr; ++ u32CopyLen2 = u32MsgLen - u32CopyLen1; ++ u32NewWriteAddr = u32CopyLen2; ++ } ++ else ++ { ++ u32CopyLen1 = u32MsgLen; ++ u32CopyLen2 = 0; ++ u32NewWriteAddr = u32MsgLen + _gstLogBufferInfo.u32WriteAddr; ++ } ++ ++ if(u32CopyLen1 > 0) ++ { ++ if(MSG_FROM_KERNEL == u32UserOrKer) ++ { ++ memcpy((_gstLogBufferInfo.pu8StartAddrVir + _gstLogBufferInfo.u32WriteAddr),pu8Buf, u32CopyLen1); ++ } ++ else ++ { ++ if(copy_from_user((_gstLogBufferInfo.u32WriteAddr+_gstLogBufferInfo.pu8StartAddrVir), ++ pu8Buf, u32CopyLen1)) ++ { ++ DBG_ERR("copy_from_user error\n"); ++ } ++ } ++ } ++ if(u32CopyLen2 > 0) ++ { ++ if(MSG_FROM_KERNEL == u32UserOrKer) ++ { ++ memcpy(_gstLogBufferInfo.pu8StartAddrVir, (pu8Buf + u32CopyLen1), u32CopyLen2); ++ } ++ else ++ { ++ if(copy_from_user(_gstLogBufferInfo.pu8StartAddrVir, ++ (pu8Buf + u32CopyLen1), u32CopyLen2)) ++ { ++ DBG_ERR("copy_from_user error\n"); ++ } ++ } ++ } ++ ++ _gstLogBufferInfo.u32WriteAddr = u32NewWriteAddr; ++ ++ if (_gbSetLogFileFlag != TRUE) ++ { ++ wake_up_interruptible(&_gstLogBufferInfo.wqNoData); ++ } ++ up(&_gstLogBufferInfo.semWrite); ++ ++ return MI_SUCCESS; ++} ++ ++ ++MI_S32 MSYS_LOG_IMPL_ReadBuf(MI_U8 *pu8Buf, MI_U32 u32BufLen, MI_U32 *pu32CopyLen, MI_BOOL bKernelCopy) ++{ ++ MI_SYS_LogBufferInfo_t stCurryMsgInfo; ++ MI_U32 u32BufUsedLen; ++ MI_U32 u32DataLen1; ++ MI_U32 u32DataLen2; ++ MI_U32 u32CopyLen; ++ MI_U32 u32NewReadAddr; ++ unsigned long flags; ++ ++ if (0 == _gstLogBufferInfo.u32BufSize) ++ { ++ DBG_ERR("Log Buffer size is 0, Please confige the Buffer size\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ if(_gstLogBufferInfo.u32WriteAddr == _gstLogBufferInfo.u32ReadAddr) ++ { ++ if (_gbSetLogFileFlag == TRUE) ++ { ++ return MI_ERR_SYS_FAILED; ++ } ++ else ++ { ++ wait_event_interruptible(_gstLogBufferInfo.wqNoData, ++ (_gstLogBufferInfo.u32WriteAddr != _gstLogBufferInfo.u32ReadAddr)); ++ } ++ } ++ ++ spin_lock_irqsave(&_gLogFileLock, flags); ++ memcpy(&stCurryMsgInfo, &_gstLogBufferInfo, sizeof(_gstLogBufferInfo)); ++ spin_unlock_irqrestore(&_gLogFileLock, flags); ++ ++ if(stCurryMsgInfo.u32WriteAddr < stCurryMsgInfo.u32ReadAddr) ++ { ++ u32BufUsedLen = stCurryMsgInfo.u32BufSize - stCurryMsgInfo.u32ReadAddr ++ + stCurryMsgInfo.u32WriteAddr; ++ u32DataLen1 = stCurryMsgInfo.u32BufSize - stCurryMsgInfo.u32ReadAddr; ++ u32DataLen2 = stCurryMsgInfo.u32WriteAddr; ++ } ++ else ++ { ++ u32BufUsedLen = stCurryMsgInfo.u32WriteAddr - stCurryMsgInfo.u32ReadAddr; ++ u32DataLen1 = u32BufUsedLen; ++ u32DataLen2 = 0; ++ } ++ ++ if (u32BufLen <= (u32DataLen1 + u32DataLen2)) ++ { ++ u32CopyLen = u32BufLen; ++ } ++ else ++ { ++ u32CopyLen = u32DataLen1 + u32DataLen2; ++ } ++ ++ if (u32DataLen1 >= u32CopyLen) ++ { ++ if (bKernelCopy == FALSE) ++ { ++ if(copy_to_user(pu8Buf, (stCurryMsgInfo.u32ReadAddr+stCurryMsgInfo.pu8StartAddrVir), u32CopyLen)) ++ { ++ DBG_ERR("copy_to_user error\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ } ++ else ++ { ++ memcpy(pu8Buf, (stCurryMsgInfo.u32ReadAddr+stCurryMsgInfo.pu8StartAddrVir), u32CopyLen); ++ } ++ ++ u32NewReadAddr = stCurryMsgInfo.u32ReadAddr + u32CopyLen; ++ } ++ else ++ { ++ if (bKernelCopy == FALSE) ++ { ++ if(copy_to_user(pu8Buf, (stCurryMsgInfo.u32ReadAddr+stCurryMsgInfo.pu8StartAddrVir), u32DataLen1)) ++ { ++ DBG_ERR("copy_to_user error\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ } ++ else ++ { ++ memcpy(pu8Buf, (stCurryMsgInfo.u32ReadAddr+stCurryMsgInfo.pu8StartAddrVir), u32DataLen1); ++ } ++ ++ if (bKernelCopy == FALSE) ++ { ++ if(copy_to_user((pu8Buf + u32DataLen1), stCurryMsgInfo.pu8StartAddrVir, (u32CopyLen - u32DataLen1))) ++ { ++ DBG_ERR("copy_to_user error\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ } ++ else ++ { ++ memcpy((pu8Buf + u32DataLen1), stCurryMsgInfo.pu8StartAddrVir, (u32CopyLen - u32DataLen1)); ++ } ++ ++ u32NewReadAddr = u32CopyLen - u32DataLen1; ++ } ++ ++ *pu32CopyLen = u32CopyLen; ++ ++ if (u32NewReadAddr >= stCurryMsgInfo.u32BufSize) ++ u32NewReadAddr = 0; ++ ++ spin_lock_irqsave(&_gLogFileLock, flags); ++ if (stCurryMsgInfo.u32ResetFlag == _gstLogBufferInfo.u32ResetFlag) ++ { ++ _gstLogBufferInfo.u32ReadAddr = u32NewReadAddr; ++ } ++ spin_unlock_irqrestore(&_gLogFileLock, flags); ++ ++ return MI_SUCCESS; ++} ++#if 0 ++static MI_S32 MSYS_LOG_IMPL_PrintLogToBuf(const char *format, ...) ++{ ++ char log_str[LOG_MAX_TRACE_LEN] = {0}; ++ MI_U32 MsgLen = 0; ++ va_list args; ++ ++ if (0 == _gu8LogInit) ++ { ++ DBG_ERR("log device not init!\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ va_start(args, format); ++ MsgLen = vsnprintf(log_str, LOG_MAX_TRACE_LEN-1, format, args); ++ va_end(args); ++ ++ if (MsgLen >= (LOG_MAX_TRACE_LEN-1)) ++ { ++ log_str[LOG_MAX_TRACE_LEN-1] = '\0'; /* even the 'vsnprintf' commond will do it */ ++ log_str[LOG_MAX_TRACE_LEN-2] = '\n'; ++ log_str[LOG_MAX_TRACE_LEN-3] = '.'; ++ log_str[LOG_MAX_TRACE_LEN-4] = '.'; ++ log_str[LOG_MAX_TRACE_LEN-5] = '.'; ++ } ++ ++ return MSYS_LOG_IMPL_WriteBuf((MI_U8 *)log_str, MsgLen, MSG_FROM_KERNEL); ++} ++#endif ++void msys_print(const char *format, ...) ++{ ++ va_list args; ++ MI_U32 u32MsgLen = 0; ++ char log_str[LOG_MAX_TRACE_LEN]={'a'}; ++ ++ { ++ log_str[LOG_MAX_TRACE_LEN-1] = 'b'; ++ log_str[LOG_MAX_TRACE_LEN-2] = 'c'; ++ ++ va_start(args, format); ++ u32MsgLen = vsnprintf(log_str, LOG_MAX_TRACE_LEN, format, args); ++ va_end(args); ++ ++ if (u32MsgLen >= LOG_MAX_TRACE_LEN) ++ { ++ log_str[LOG_MAX_TRACE_LEN-1] = '\0'; /* even the 'vsnprintf' commond will do it */ ++ log_str[LOG_MAX_TRACE_LEN-2] = '\n'; ++ log_str[LOG_MAX_TRACE_LEN-3] = '.'; ++ log_str[LOG_MAX_TRACE_LEN-4] = '.'; ++ log_str[LOG_MAX_TRACE_LEN-5] = '.'; ++ } ++ /* log module has Initialized. */ ++ if (_gu8LogInit) ++ { ++ MI_SYS_LogOutputPos_e ePos = GetLogPrintMode(); ++ ++ switch(ePos) ++ { ++ case E_MI_SYS_LOG_OUTPUT_SERIAL: ++ MI_PRINT(log_str); ++ break; ++ case E_MI_SYS_LOG_OUTPUT_NETWORK: ++ case E_MI_SYS_LOG_OUTPUT_UDISK: ++ MSYS_LOG_IMPL_WriteBuf(log_str, u32MsgLen, MSG_FROM_KERNEL); ++ break; ++ case E_MI_SYS_LOG_OUTPUT_DBG: ++ /* No Output */ ++ break; ++ } ++ } ++ else /* log module has not Initialized. */ ++ { ++ MI_PRINT(log_str); ++ } ++ } ++ ++} ++ ++EXPORT_SYMBOL(msys_print); ++ ++static inline int get_log_level(const char *buffer) ++{ ++ if (buffer[0] == KERN_SOH_ASCII && buffer[1]) { ++ switch (buffer[1]) { ++ case '0' ... '7': ++ return buffer[1]-'0'; ++ } ++ } ++ return 7; ++} ++ ++ ++void msys_prints(const char *string, int length) ++{ ++ /* log module has Initialized. */ ++ if (_gu8LogInit) ++ { ++ MI_SYS_LogOutputPos_e ePos = GetLogPrintMode(); ++ ++ switch(ePos) ++ { ++ case E_MI_SYS_LOG_OUTPUT_SERIAL: ++ printk(string); ++ break; ++ case E_MI_SYS_LOG_OUTPUT_NETWORK: ++ case E_MI_SYS_LOG_OUTPUT_UDISK: ++ MSYS_LOG_IMPL_WriteBuf((MI_U8 *)string, length, MSG_FROM_KERNEL); ++ break; ++ case E_MI_SYS_LOG_OUTPUT_DBG: ++ if (get_log_level(string)<=_gu8LogLevel) ++ printk(string); ++ break; ++ } ++ } ++ else /* log module has not Initialized. */ ++ { ++ printk(string); ++ } ++ ++} ++ ++EXPORT_SYMBOL(msys_prints); ++ ++#ifdef FUNC_DEBUG_LEVEL ++MI_S32 MSYS_LOG_IMPL_LogAddModule(const MI_U8* szProcName, MI_ModuleId_e eModuleID) ++{ ++ if (NULL == _gpstLogConfigInfo || eModuleID >= E_MI_MODULE_ID_MAX) ++ { ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ MSYS_LOG_IMPL_Snprintf(_gpstLogConfigInfo[eModuleID].u8ModName, sizeof(_gpstLogConfigInfo[eModuleID].u8ModName),"%s", szProcName); ++ ++ _gpstLogConfigInfo[eModuleID].eLogLevel = GetModuleLevel(strlwr(_gpstLogConfigInfo[eModuleID].u8ModName)); ++ ++ return MI_SUCCESS; ++} ++ ++MI_S32 MSYS_LOG_IMPL_LogRemoveModule(const MI_U8* szProcName, MI_ModuleId_e eModuleID) ++{ ++ ++ if (NULL == _gpstLogConfigInfo || eModuleID >= E_MI_MODULE_ID_MAX) ++ { ++ return MI_ERR_SYS_FAILED; ++ } ++ ++ _gpstLogConfigInfo[eModuleID].eLogLevel = E_MI_ERR_LEVEL_ERROR; ++ MSYS_LOG_IMPL_Snprintf(_gpstLogConfigInfo[eModuleID].u8ModName, sizeof(_gpstLogConfigInfo[eModuleID].u8ModName), "ModuleMax"); ++ ++ return MI_SUCCESS; ++} ++#endif ++ ++ ++ ++int MSYS_LOG_IMPL_ProcRead(struct seq_file *s, void *pArg) ++{ ++#ifdef FUNC_DEBUG_LEVEL ++ MI_U32 i; ++ MI_U8 u8Level; ++ MI_U32 u32Total = E_MI_MODULE_ID_MAX; ++#endif ++ if (0 == _gu8LogInit) ++ { ++ seq_printf(s," Log module not init\n"); ++ return 0; ++ } ++ seq_printf(s,"---------------- Log Path ------------------------\n"); ++ seq_printf(s,"log path: %s\n", UdiskLogFile); ++ ++#ifdef FUNC_STORE_PATH ++ seq_printf(s,"---------------- Store Path ----------------------\n"); ++ seq_printf(s,"store path: %s\n", StorePath); ++#endif ++#ifdef FUNC_DEBUG_LEVEL ++ seq_printf(s,"---------------- Module Log Level ----------------\n"); ++ seq_printf(s,"Log module\t Level\n"); ++ seq_printf(s,"--------------------------\n"); ++ for (i = 0; i < u32Total; i++) ++ { ++ if (strncmp(_gpstLogConfigInfo[i].u8ModName, "modulemax", 10)) ++ { ++ _gpstLogConfigInfo[i].eLogLevel = GetModuleLevel(_gpstLogConfigInfo[i].u8ModName); ++ u8Level = _gpstLogConfigInfo[i].eLogLevel; ++ seq_printf(s,"%-16s %d(%s)\n", ++ _gpstLogConfigInfo[i].u8ModName, u8Level, DebugLevelName[u8Level]); ++ } ++ } ++ ++ seq_printf(s,"\nhelp example:\n"); ++ seq_printf(s,"echo mi_sys=2 > /proc/mi_modules/mi_log_info \n"); ++ seq_printf(s,"echo mi_vdisp=1 > /proc/mi_modules/mi_log_info \n"); ++#endif ++ seq_printf(s,"echo log=/mnt > /proc/msys/msys_log_info \n"); ++ seq_printf(s,"echo log=/dev/null > /proc/msys/msys_log_info \n"); ++ seq_printf(s,"echo log=dbg_lv_2 > /proc/msys/msys_log_info \n"); ++#ifdef FUNC_STORE_PATH ++ seq_printf(s,"echo storepath=/mnt > /proc/msys/msys_log_info \n"); ++#endif ++ ++ return 0; ++} ++ ++ ++ ++ ++ssize_t MSYS_LOG_IMPL_ProcWrite( struct file * file, const char __user * buf, ++ size_t count, loff_t *ppos) ++{ ++ char m[MAX_FILENAME_LENTH] = {0}; ++ char d[MAX_FILENAME_LENTH] = {0}; ++ size_t len = MAX_FILENAME_LENTH; ++ char *left, *right; ++ int log_level = 7; ++// int idx, level; ++ int nRet = 0; ++ if (*ppos >= MAX_FILENAME_LENTH) ++ return -EFBIG; ++ ++ len = min(len, count); ++ if(copy_from_user(m, buf, len )) ++ return -EFAULT; ++ ++ if (0 == _gu8LogInit) ++ { ++ DBG_ERR(" Log module not init!\n"); ++ goto out; ++ } ++ ++ StripString(m, d); ++ ++ /* echo help info to current terinmal */ ++ if (!strncasecmp("help", m, 4)) ++ { ++#ifndef DISABLE_FUNC_DEBUG_LEVEL ++ printk("To modify the level, use command line in shell: \n"); ++ printk(" echo module_name = level_number > /proc/msp/log\n"); ++ printk(" level_number: 0-fatal, 1-error, 2-warning, 3-info\n"); ++ printk(" example: 'echo HI_DEMUX=3 > /proc/msp/log'\n"); ++ printk(" will change log levle of module \"HI_DEMUX\" to 3, then, \n"); ++ printk("all message with level higher than \"info\" will be printed.\n"); ++ printk("Use 'echo \"all = x\" > /proc/msp/log' to change all modules.\n"); ++ ++ printk("\n\nTo modify the log path, use command line in shell: \n"); ++ printk("Use 'echo \"log = x\" > /proc/msp/log' to set log path.\n"); ++ printk("Use 'echo \"log = /dev/null\" > /proc/msp/log' to close log udisk output.\n"); ++ printk("Use 'echo \"log = dbg_lv_#\" > /proc/msys/msys_log_info' to configure log output level. #=0~7\n"); ++ printk(" example: 'echo log=/home > /proc/msp/log'\n"); ++ printk(" example: 'echo log=dbg_lv_4 > /proc/msys/msys_log_info'\n"); ++#endif ++ printk("\n\nTo modify the debug file store path, use command line in shell: \n"); ++ printk("Use 'echo \"storepath = x\" > /proc/msp/log' to set debug file path.\n"); ++ printk(" example: 'echo storepath=/tmp > /proc/msp/log'\n"); ++ } ++ ++ if (SeperateString(d, &left, &right)){ ++ DBG_WRN("string is unkown!\n"); ++ goto out; ++ } ++ ++ if (!strncasecmp("log", left, 4)) ++ { ++ if (strlen(right) >= sizeof(g_szPathBuf)) ++ { ++ DBG_ERR(" Log path length is over than %d!\n",sizeof(g_szPathBuf)); ++ goto out; ++ } ++ ++ nRet = LOG_FILE_LOCK(); ++ ++ memset(g_szPathBuf, 0, sizeof(g_szPathBuf)); ++ memcpy(g_szPathBuf, right, strlen(right)); ++ ++ if ( memcmp(g_szPathBuf, "/dev/null", strlen("/dev/null")) != 0 ) ++ { ++ if ( strncasecmp(g_szPathBuf, "dbg_lv_", strlen("dbg_lv_")) != 0 ) ++ { ++ _MSYS_LOG_IMPL_LogBufferInit(); ++ if(!IS_ERR(gpLogUdiskTask)) ++ { ++ wake_up_process(gpLogUdiskTask); ++ } ++ _gbSetLogFileFlag = TRUE; ++ _gbLogOutDbg = FALSE; ++ } ++ else ++ { ++ sscanf(g_szPathBuf,"dbg_lv_%d", &log_level); ++ _gu8LogLevel = log_level; ++ _gbLogOutDbg = TRUE; ++ } ++ } ++ else ++ { ++ _gbSetLogFileFlag = FALSE; ++ _gbLogOutDbg = FALSE; ++ } ++#ifdef FUNC_DEBUG_LEVEL ++ //bug?? ++ _gpstLogConfigInfo->u8UdiskFlag = (MI_U8)_gbSetLogFileFlag; ++#endif ++ UdiskLogFile = g_szPathBuf; ++ ++ LOG_FILE_UNLOCK(); ++ ++ DBG_INFO("set log path is g_szPathBuf = %s\n", UdiskLogFile); ++ ++ goto out; ++ } ++#ifdef FUNC_STORE_PATH ++ else if (!strncasecmp("storepath", left, strlen("storepath")+1)) ++ { ++ if (strlen(right) >= sizeof(g_szStorePathBuf)) ++ { ++ DBG_ERR(" Store path length is over than %d!\n",sizeof(g_szStorePathBuf)); ++ goto out; ++ } ++ ++ nRet = LOG_FILE_LOCK(); ++ ++ memset(g_szStorePathBuf, 0, sizeof(g_szStorePathBuf)); ++ memcpy(g_szStorePathBuf, right, strlen(right)); ++ ++ StorePath = g_szStorePathBuf; ++ ++ LOG_FILE_UNLOCK(); ++ ++ DBG_ERR("set output path is StorePath = %s\n", g_szStorePathBuf); ++ ++ goto out; ++ } ++#endif ++ ++#ifdef FUNC_DEBUG_LEVEL ++ else ++ { ++ level = simple_strtol(right, NULL, 10); ++ if (!level && *right != '0'){ ++ DBG_WRN("invalid value!\n"); ++ goto out; ++ } ++ if (!strncasecmp("all", left, 4)){ ++ int i = 0; ++ MI_U32 u32Total = E_MI_MODULE_ID_MAX; ++ for (i = 0; i < u32Total; i++) ++ { ++ _gpstLogConfigInfo[i].eLogLevel = (MI_DBG_LEVEL_e)level; ++ SetModuleLevel(strlwr(_gpstLogConfigInfo[i].u8ModName) , level); ++ } ++ goto out; ++ } ++ ++ idx = SearchMod(left); ++ if (-1 == idx){ ++ DBG_WRN("%s not found in array!\n", left); ++ return count; ++ } ++ _gpstLogConfigInfo[idx].eLogLevel = (MI_DBG_LEVEL_e)level; ++ if(!SetModuleLevel(strlwr(_gpstLogConfigInfo[idx].u8ModName) , level)) ++ { ++ goto out; ++ } ++ return count; ++ } ++#endif ++ ++out: ++ *ppos = len; ++ return len; ++} ++ ++ ++int LogUdiskWriteThread(void* pArg) ++{ ++ MI_U8 szBuf[700] = {0}; ++ MI_U32 u32ReadLen = 0; ++ MI_U32 s32Ret = 0; ++ MI_U8 szFileName[MAX_FILENAME_LENTH] = {0}; ++ MI_BOOL bSetFileFlag = FALSE; ++ ++ while (1) ++ { ++ s32Ret = LOG_FILE_LOCK(); ++ ++ bSetFileFlag = _gbSetLogFileFlag; ++ ++ MSYS_LOG_IMPL_Snprintf(szFileName, sizeof(szFileName)-1, "%s/msys.log", (const MI_S8*)UdiskLogFile); ++ ++ LOG_FILE_UNLOCK(); ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ if(kthread_should_stop()) ++ { ++ break; ++ } ++ ++ if ( bSetFileFlag == FALSE) ++ { ++ msleep(10); ++ continue; ++ } ++ ++ memset(szBuf, 0, sizeof(szBuf)); ++ ++ s32Ret = MSYS_LOG_IMPL_ReadBuf(szBuf, sizeof(szBuf)-1, &u32ReadLen, TRUE); ++ if (s32Ret == MI_SUCCESS) ++ { ++ LogUdiskSave((const MI_S8*)szFileName, szBuf, u32ReadLen); ++ } ++ ++ msleep(100); ++ } ++ ++ return 0; ++} ++ ++MI_S32 _MSYS_LOG_IMPL_LogUdiskInit(const MI_U8* pUdiskFolder) ++{ ++ int err; ++ ++ if (pUdiskFolder == NULL ) ++ { ++ return MI_ERR_SYS_NOT_PERM; ++ } ++ ++ if (gpLogUdiskTask == NULL) ++ { ++ gpLogUdiskTask = kthread_create(LogUdiskWriteThread, (void*)pUdiskFolder, "msysLodUdiskTask"); ++ if(IS_ERR(gpLogUdiskTask)) ++ { ++ DBG_ERR("create log Udisk write thread failed\n"); ++ ++ err = PTR_ERR(gpLogUdiskTask); ++ gpLogUdiskTask = NULL; ++ ++ return err; ++ } ++ ++ wake_up_process(gpLogUdiskTask); ++ } ++ ++ return MI_SUCCESS; ++} ++ ++ ++static int log_info_open(struct inode *inode, struct file *file) ++{ ++ single_open(file,MSYS_LOG_IMPL_ProcRead,PDE_DATA(inode)); ++ return MI_SUCCESS; ++} ++ ++static const struct file_operations mi_log_info_fops = { ++ .owner = THIS_MODULE, ++ .open = log_info_open, ++ .read = seq_read, ++ .write = MSYS_LOG_IMPL_ProcWrite, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++MI_S32 MSYS_LOG_Init(void) ++{ ++#ifdef FUNC_DEBUG_LEVEL ++ MI_U32 u32ModuleId = 0; ++ MI_U8 u8ModuleName[10] = {0}; ++#endif ++ struct proc_dir_entry *entry; ++ ++ g_pCMPI_proc = proc_mkdir("msys", NULL); ++ ++ entry = proc_create("msys_log_info", 0666, g_pCMPI_proc, &mi_log_info_fops); ++ if (!entry) ++ { ++ printk(KERN_ERR "failed to create procfs file mi_log_info.\n"); ++ return MI_ERR_SYS_FAILED; ++ } ++ ++#ifdef FUNC_DEBUG_LEVEL ++ _MSYS_LOG_IMPL_ConfigInfoInit(); ++ ++ while(u32ModuleId < E_MI_MODULE_ID_MAX) ++ { ++ _MSYS_IMPL_ModuleIdToPrefixName((MI_ModuleId_e)u32ModuleId , u8ModuleName); ++ MSYS_LOG_IMPL_LogAddModule(u8ModuleName , (MI_ModuleId_e)u32ModuleId); ++ u32ModuleId ++; ++ } ++#endif ++ //_MSYS_LOG_IMPL_LogBufferInit(); //move to proc_wirite to trigger ++ _MSYS_LOG_IMPL_LogUdiskInit(UdiskLogFile); ++ ++ _gu8LogInit = 1; ++ ++ return MI_SUCCESS; ++} ++ ++MI_S32 _MSYS_LOG_IMPL_LogBufferExit(void) ++{ ++ if(NULL != _gstLogBufferInfo.pu8StartAddrVir) ++ { ++ //mi_sys_UnVmap(_gstLogBufferInfo.pu8StartAddrVir); ++ //mi_sys_MMA_Free(_gstLogBufferInfo.phyStartAddrPhy); ++ kfree(_gstLogBufferInfo.pu8StartAddrVir); ++ ++ _gstLogBufferInfo.pu8StartAddrVir = NULL; ++ _gstLogBufferInfo.phyStartAddrPhy = 0; ++ } ++ return MI_SUCCESS; ++} ++#ifdef FUNC_DEBUG_LEVEL ++ ++MI_S32 _MSYS_LOG_IMPL_ConfigInfoExit(void) ++{ ++ if (NULL != _gstLogBuffer.pStartVirAddr) ++ { ++ //mi_sys_UnVmap(_gstLogBuffer.pStartVirAddr); ++ //mi_sys_MMA_Free(_gstLogBuffer.phyStartPhyAddr); ++ kfree(_gstLogBuffer.pStartVirAddr); ++ _gstLogBuffer.pStartVirAddr = NULL; ++ _gstLogBuffer.phyStartPhyAddr = 0; ++ //_gpstLogConfigInfo = NULL; ++ } ++ return MI_SUCCESS; ++} ++#endif ++ ++MI_S32 MSYS_LOG_Exit(void) ++{ ++#ifdef FUNC_DEBUG_LEVEL ++ ++ MI_U32 u32ModuleId = 0; ++ MI_U8 u8ModuleName[10] = {0}; ++ ++ while(u32ModuleId < E_MI_MODULE_ID_MAX) ++ { ++ _MSYS_IMPL_ModuleIdToPrefixName((MI_ModuleId_e)u32ModuleId , u8ModuleName); ++ MSYS_LOG_IMPL_LogRemoveModule(u8ModuleName , (MI_ModuleId_e)u32ModuleId); ++ u32ModuleId ++; ++ } ++ _gu8LogInit = 0; ++ _MSYS_LOG_IMPL_ConfigInfoExit(); ++#endif ++ _MSYS_LOG_IMPL_LogBufferExit(); ++ ++ remove_proc_entry("msys_log_info",g_pCMPI_proc); ++ ++ return MI_SUCCESS; ++} ++ ++ ++subsys_initcall(MSYS_LOG_Init); +diff --git a/drivers/sstar/msys/ms_msys_memory_bench.c b/drivers/sstar/msys/ms_msys_memory_bench.c +new file mode 100755 +index 000000000000..425b643eb9fa +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys_memory_bench.c +@@ -0,0 +1,392 @@ ++#include ++#include /* for get_fs*/ ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include /* for sysctl_compaction_handler*/ ++#include ++ ++#include "registers.h" ++#include "cam_os_wrapper.h" ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++#define MSYS_WARNING(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++ ++ ++extern struct miscdevice sys_dev; ++typedef unsigned int volatile ulv; ++typedef unsigned long int volatile ullv; ++ ++/****************************************** ++ * Function prototypes and Global variables ++ ******************************************/ ++//int TEST_SolidBitsComparison(ulv *pSrc, ulv *pDest, unsigned int nCount); ++ ++ ++/****************************************** ++ * Extern ++ ******************************************/ ++ ++/****************************************** ++ * Functions ++ ******************************************/ ++ ++static int TEST_Memwrite(ulv * pDest, unsigned int nCount) ++{ ++ register unsigned int val = 0xA5A4B5B4; ++ ulv *p2 = NULL; ++ unsigned int nTest, i; ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p2 = (ulv *) pDest; ++ for (i = 0; i < nCount; i++) ++ *p2++ = val; ++ } ++ return nTest; ++} ++ ++static int TEST_Memread(ulv * pSrc, unsigned int nCount) ++{ ++ register unsigned int val; ++ ulv *p1 = NULL; ++ unsigned int nTest, i; ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ for (i = 0; i < nCount; i++) ++ val = *p1++; ++ } ++ return nTest; ++} ++ ++static int TEST_Memcpy_mips(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ int nTest = 0; ++// for (nTest = 0; nTest < 10; nTest++) ++// memcpy_MIPS((void*)pDest, (void*)pSrc, nCount*sizeof(unsigned int)); ++ return nTest; ++} ++ ++static int TEST_Memcpy(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ int nTest; ++ for (nTest = 0; nTest < 10; nTest++) ++ memcpy((void*)pDest, (void*)pSrc, nCount*sizeof(unsigned int)); ++ return nTest; ++} ++ ++static int TEST_MemBandWidth_long(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ ullv *p1 = NULL; ++ ullv *p2 = NULL; ++ unsigned int i; ++ unsigned int nTest; ++ ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p1 = (ullv *) pSrc; ++ p2 = (ullv *) pDest; ++ ++ for (i = 0; i < nCount; i++) ++ *p2++ = *p1++; ++ } ++ ++ return nTest; ++} ++ ++int TEST_MemBandWidth(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ unsigned int i; ++ unsigned int nTest; ++ ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ ++ for (i = 0; i < nCount; i++) ++ *p2++ = *p1++; ++ } ++ ++ return nTest; ++} ++ ++ ++int TEST_MemBandWidthRW(ulv * pSrc, ulv * pDest, unsigned int nCount, unsigned int step_size) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ //unsigned int i; ++ unsigned int nTest; ++ int Count; ++ ++ for (nTest = 0; nTest < 10 * step_size; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ Count = nCount / step_size; ++ //memcpy((void*)p2, (void*)p1, nCount*4); ++ while(Count--) ++ { ++ *p2 = *p1; ++ p2 += step_size; ++ p1 += step_size; ++ } ++ } ++ ++ return nTest; ++} ++ ++static int TEST_MemBandWidthR(ulv * pSrc, ulv * pDest, unsigned int nCount, unsigned int step_size) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ //unsigned int i; ++ unsigned int nTest; ++ int Count; ++ ++ for (nTest = 0; nTest < 10 * step_size; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ Count = nCount / step_size; ++ //memcpy((void*)p2, (void*)p1, nCount*4); ++ while(Count--) ++ { ++ *p2 = *p1; ++ p1 += step_size; ++ } ++ } ++ ++ return nTest; ++} ++ ++static int TEST_MemBandWidthW(ulv * pSrc, ulv * pDest, unsigned int nCount, unsigned int step_size) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ //unsigned int i; ++ unsigned int nTest; ++ int Count; ++ ++ for (nTest = 0; nTest < 10 * step_size; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ Count = nCount / step_size; ++ //memcpy((void*)p2, (void*)p1, nCount*4); ++ while(Count--) ++ { ++ *p2 = *p1; ++ p2 += step_size; ++ } ++ } ++ ++ return nTest; ++} ++ ++ ++ ++void msys_bench_memory(unsigned int uMemSize) ++{ ++ unsigned int nLoop = 0; ++ unsigned int nAllocBytes; ++ unsigned int nBufSize; ++ unsigned int nCount; ++ unsigned int PAGE_MASK1 = 0x0FFF; ++ void *pBuf = NULL; ++ volatile void *pAlignedBuf = NULL; ++ volatile unsigned int *pSrc; ++ volatile unsigned int *pDest; ++ unsigned int bus_addr; ++ struct timespec tss, tse; ++ int nDelay; ++ int nTestCount = 0; ++ int nSize; ++ int i = 0; ++ ++ nBufSize = (unsigned int) (uMemSize << 20); ++ nAllocBytes = nBufSize + 4096; ++ ++ MSYS_WARNING("\n>>>> sys_memory_benchmark0\n"); ++ pBuf=dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(nAllocBytes), &bus_addr, GFP_KERNEL); ++ ++ if(pBuf==NULL) ++ { ++ MSYS_ERROR("error while allocating DMA buffer for benchmark...\n"); ++ return; ++ } ++ ++ MSYS_WARNING(" Allocated %d bytes at 0x%08x\n", nAllocBytes, (unsigned int) pBuf); ++ ++ if ((unsigned int) pBuf % 4096) { ++ pAlignedBuf = (void volatile *) (((unsigned int) pBuf + 4096) ++ & PAGE_MASK1); ++ MSYS_WARNING(" Aligned at 0x%08x\n", (unsigned int) pAlignedBuf); ++ } else { ++ pAlignedBuf = pBuf; ++ } ++ ++ /* Show information */ ++ nCount = (nBufSize / 2) / sizeof(unsigned int); ++ ++ pSrc = (ulv *) pAlignedBuf; ++ pDest = (ulv *) ((unsigned int) pAlignedBuf + (nBufSize / 2)); ++ ++ MSYS_WARNING(" Read from : %p\n", pSrc); ++ MSYS_WARNING(" Write to : %p\n", pDest); ++ ++ nSize = nCount * sizeof(unsigned int); ++ ++ MSYS_WARNING(" Size : %x\n", nSize); ++ ++ MSYS_WARNING("\nMemory read/write test\n"); ++ nLoop = 0; ++ ++ MSYS_WARNING("\n(1) Memory read/write test through 32-bit pointer access\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_MemBandWidth(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(2) Memory read/write test through 32-bit pointer access\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_MemBandWidth_long(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(3) Memory read/write test through memcpy()\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memcpy(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(4) Memory read/write test through memcpy(prefetch version)\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memcpy_mips(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(5) Memory read test\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memread(pSrc, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", nLoop, ++ nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(6) Memory write test\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memwrite(pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", nLoop, ++ nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ //============================= ++ ++ MSYS_WARNING("\n(7) Memory read/write test\n"); ++ ++ for (i = 1; i < 513; i = i << 1) ++ { ++ tss = CURRENT_TIME; ++ ++ nTestCount = TEST_MemBandWidthRW(pSrc, pDest, nCount, i); ++ ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %8d bytes, skip %4d bytes %4d msec => %6d KB/sec\n", ++ nSize, i * 4, nDelay, ++ ((((nSize / i) * nTestCount) / 1024) * 1000) / nDelay); ++ } ++ ++ MSYS_WARNING("\n(8) Memory read test\n"); ++ ++ for (i = 1; i < 513; i = i << 1) ++ { ++ tss = CURRENT_TIME; ++ ++ nTestCount = TEST_MemBandWidthR(pSrc, pDest, nCount, i); ++ ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read %8d bytes, skip %4d bytes %4d msec => %6d KB/sec\n", ++ nSize, i * 4, nDelay, ++ ((((nSize / i) * nTestCount) / 1024) * 1000) / nDelay); ++ } ++ ++ MSYS_WARNING("\n(9) Memory write test\n"); ++ ++ for (i = 1; i < 513; i = i << 1) ++ { ++ tss = CURRENT_TIME; ++ ++ nTestCount = TEST_MemBandWidthW(pSrc, pDest, nCount, i); ++ ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Write %8d bytes, skip %4d bytes %4d msec => %6d KB/sec\n", ++ nSize, i * 4, nDelay, ++ ((((nSize / i) * nTestCount) / 1024) * 1000) / nDelay); ++ } ++ ++ ++ MSYS_WARNING("\n<<<< sys_memory_benchmark0\n"); ++ dma_free_coherent(sys_dev.this_device, nAllocBytes,pBuf,bus_addr); ++ // munlock((void *) pBuf, nAllocBytes); ++ // free((void *) pBuf); ++} +diff --git a/drivers/sstar/msys/ms_msys_miu_protect.c b/drivers/sstar/msys/ms_msys_miu_protect.c +new file mode 100755 +index 000000000000..5c153f51dfa5 +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys_miu_protect.c +@@ -0,0 +1,84 @@ ++#include ++#include /* for get_fs*/ ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include /* for sysctl_compaction_handler*/ ++#include ++ ++#include "registers.h" ++#include "mdrv_miu.h" ++extern struct miscdevice sys_dev; ++ ++ ++static ssize_t miu_protect_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ int n; ++ ++ n = sprintf(str, "[%s][%d]: OK!\n", __FUNCTION__, __LINE__); ++ return n; ++} ++ ++static ssize_t miu_protect_entry(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ unsigned char Result = FALSE; ++ unsigned char u8Blockx; ++ unsigned short u8ProtectId[16] = {0}; ++ unsigned long long u64BusStart; ++ unsigned long long u64BusEnd; ++ unsigned char bSetFlag; ++ ++ unsigned char token[16]; ++ ++ sscanf(buf, "%s", token); ++ if (0 == strcasecmp(token, "set")) ++ { ++ sscanf(buf, "%s %hhu %hu %llx %llx %hhu", token, &u8Blockx, &u8ProtectId[0], &u64BusStart, &u64BusEnd, &bSetFlag); ++ ++ printk("%s(%d) INPUT: (u8Blockx,u8ProtectId,u64BusStart,u64BusEnd,bSetFlag)=(%hhu,%hu,0x%08llx,0x%08llx,%hhu)\n", __FUNCTION__, __LINE__, u8Blockx, u8ProtectId[0], u64BusStart, u64BusEnd, bSetFlag); ++ ++ Result = MDrv_MIU_Protect(u8Blockx, &u8ProtectId[0], u64BusStart, u64BusEnd, bSetFlag); ++ ++ if(Result == FALSE ) { ++ printk("ERR: Result = %d", Result); ++ } ++ } ++ else if (0 == strcasecmp(token, "test")) ++ { ++ unsigned int* _va; ++ sscanf(buf, "%s %llx", token, &u64BusStart); ++ ++ _va = ioremap((unsigned int)u64BusStart, 0x1000); ++ printk("%s(%d) Write: MIU @ 0x%08llx, VA @ 0x%08x\n", __FUNCTION__, __LINE__, u64BusStart, (unsigned int)_va); ++ ++ *(_va) = 0xDEADBEEF; ++ } ++ else if (0 == strcasecmp(token, "test1")) ++ { ++ sscanf(buf, "%s %llx", token, &u64BusStart); ++ ++ printk("%s(%d) Write: MIU @ 0x%08llx\n", __FUNCTION__, __LINE__, u64BusStart); ++ ++ *(unsigned int*)((void*)(unsigned int)u64BusStart) = 0xDEADBEEF; ++ } ++ else ++ { ++ printk("%s(%d) Wrong parameter:\n", __FUNCTION__, __LINE__); ++ printk("%s(%d) Usage: echo [CMD] [miublk] [client id] [start addr] [end addr] [enable] > miu_protect\n", __FUNCTION__, __LINE__); ++ printk("%s(%d) Ex: echo set 0 1 0x20000000 0x20100000 1 > miu_protect\n", __FUNCTION__, __LINE__); ++ } ++ ++ return n; ++} ++DEVICE_ATTR(miu_protect, 0644, miu_protect_show, miu_protect_entry); ++ ++int msys_miu_protect_init(void) ++{ ++ device_create_file(sys_dev.this_device, &dev_attr_miu_protect); ++ return 0; ++} ++device_initcall(msys_miu_protect_init); +\ No newline at end of file +diff --git a/drivers/sstar/msys/ms_msys_perf_test.c b/drivers/sstar/msys/ms_msys_perf_test.c +new file mode 100755 +index 000000000000..61df93899f56 +--- /dev/null ++++ b/drivers/sstar/msys/ms_msys_perf_test.c +@@ -0,0 +1,1034 @@ ++#include ++#include /* for get_fs*/ ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include /* for sysctl_compaction_handler*/ ++#include ++ ++#include "registers.h" ++#include "ms_platform.h" ++ ++extern struct miscdevice sys_dev; ++ ++#if 1 ++#define dmac_map_area __glue(_CACHE,_dma_map_area) ++#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) ++extern void dmac_map_area(const void *, size_t, int); ++extern void dmac_unmap_area(const void *, size_t, int); ++#else ++#define dmac_map_area(a, b, c) {} ++#define dmac_unmap_area(a, b, c) {} ++#endif ++ ++ ++#include ++ ++#define STR_IMI "IMI" ++#define STR_MIU "MIU" ++#define STR_CACHE "CACHE" ++#define STR_CPUINFO "CPUINFO" ++#define STR_ALL "ALL" ++ ++//////////////////////////////////////////// ++#define STR_CPUINFO_CA9 "ARMv7 CA9" ++#define STR_CPUINFO_CA7 "ARMv7 CA7" ++#define STR_CPUINFO_CA53 "ARMv8 CA53" ++#define STR_CPUINFO_NULL "CPU_NULL" ++#define CPU_PART_CA7 0xC07 ++#define CPU_PART_CA9 0xC09 ++#define CPU_PART_CA53 0xD03 ++#define CPU_PART_NULL 0x000 ++ ++#define IMI_ADDR_INVALID 0xFFFFFFFF ++#define IMI_SIZE_INVALID 0xFFFFFFFF ++ ++ ++ ++static char* _perf_fileBuf = NULL; ++static char* _perf_fileptr_write = NULL; ++static char* _perf_fileptr_read = NULL; ++static struct file *_fp = NULL; ++#define FILEBUF_SIZE 8192 ++ ++////////////////////////////////////////////////////////////////// ++/// performance test file buffer ++////////////////////////////////////////////////////////////////// ++#define PERF_BUF_ALLOC() \ ++({ \ ++ _perf_fileptr_read = _perf_fileptr_write = _perf_fileBuf = kzalloc(FILEBUF_SIZE, GFP_KERNEL); \ ++ (_perf_fileBuf); \ ++}) ++ ++#define PERF_BUF_FREE() \ ++{ \ ++ if (_perf_fileBuf) \ ++ { \ ++ kfree(_perf_fileBuf); \ ++ _perf_fileptr_read = _perf_fileptr_write = _perf_fileBuf = NULL; \ ++ } \ ++} ++ ++ ++#if 0 ++ ++#define PERF_BUF_SYNC() \ ++{ \ ++ if ((_perf_fileptr_read) && (_perf_fileptr_read != _perf_fileptr_write) && (_fp)) \ ++ { \ ++ _fp->f_op->write(_fp, _perf_fileptr_read, strlen(_perf_fileptr_read), &_fp->f_pos); \ ++ _perf_fileptr_read = _perf_fileptr_write; \ ++ } \ ++} ++ ++#else ++ ++#define PERF_BUF_SYNC() \ ++{ \ ++ if ((_perf_fileptr_read) && (_perf_fileptr_read != _perf_fileptr_write) && (_fp)) \ ++ { \ ++ vfs_write(_fp, _perf_fileptr_read, strlen(_perf_fileptr_read), &_fp->f_pos); \ ++ _perf_fileptr_read = _perf_fileptr_write; \ ++ } \ ++} ++ ++#endif ++ ++#define PERF_BUF_RESET() { _perf_fileptr_read = _perf_fileptr_write = _perf_fileBuf; memset(_perf_fileBuf, 0, FILEBUF_SIZE); } ++ ++#define PERF_BUF_PUT(format, ...) \ ++{ \ ++ if (_perf_fileptr_write) \ ++ { \ ++ _perf_fileptr_write += sprintf(_perf_fileptr_write, format, ##__VA_ARGS__); \ ++ } \ ++} ++ ++////////////////////////////////////////////////////////////////// ++/// performance test command maker ++////////////////////////////////////////////////////////////////// ++#define PERF_TEST_CMD_MAKE_CPUINFO(cmdBuf) \ ++ sprintf((cmdBuf), "%s", STR_CPUINFO) ++#define PERF_TEST_CMD_MAKE_CACHE(cmdBuf, size, loop) \ ++ sprintf((cmdBuf), "%s %d %d", STR_CACHE, (size), (loop)) ++#define PERF_TEST_CMD_MAKE_MIU(cmdBuf, cache, size, loop, scheme) \ ++ sprintf((cmdBuf), "%s %d %s %d %d %d %d", STR_MIU, (cache), STR_MIU, (cache), (loop), (size), (scheme)) ++#define PERF_TEST_CMD_MAKE_IMI(cmdBuf, cache, size, loop, scheme) \ ++ sprintf((cmdBuf), "%s %d %s %d %d %d %d", STR_IMI, (cache), STR_IMI, (cache), (loop), (size), (scheme)) ++ ++////////////////////////////////////////////////////////////////// ++/// performance test file ++////////////////////////////////////////////////////////////////// ++#define PERF_TEST_FILENAME_MAKE(prefix, pattern, postfix) \ ++{ \ ++ strcat((prefix), "_"); \ ++ strcat((prefix), (pattern)); \ ++ strcat((prefix), (postfix)); \ ++} ++ ++#define PERF_TEST_FILE_OPEN(filename) \ ++({ \ ++ _fp = filp_open((filename), O_CREAT|O_RDWR|O_TRUNC, 0777); \ ++ (_fp); \ ++}) ++ ++#define PERF_TEST_FILE_CLOSE() \ ++{ \ ++ if (_fp) \ ++ { \ ++ filp_close(_fp, NULL); \ ++ _fp = NULL; \ ++ } \ ++} ++ ++static struct timespec time_start; ++static void _time_start(void) ++{ ++ getnstimeofday(&time_start); ++} ++ ++static unsigned long _time_end_us(void) ++{ ++ unsigned long delta; ++ struct timespec ct; ++ ++ getnstimeofday(&ct); ++ delta = (ct.tv_sec - time_start.tv_sec)*1000000 + (ct.tv_nsec - time_start.tv_nsec)/1000; ++ // printk("[%s][%d] (start, end, delta) = (%d, %d) (%d, %d) %d\n", __FUNCTION__, __LINE__, (int)time_start.tv_sec, (int)time_start.tv_nsec, (int)ct.tv_sec, (int)ct.tv_nsec, (int)delta); ++ return delta; ++} ++ ++static unsigned long long _time_end_ns(void) ++{ ++ unsigned long long delta; ++ struct timespec ct; ++ ++ getnstimeofday(&ct); ++ delta = (ct.tv_sec - time_start.tv_sec)*1000000000 + (ct.tv_nsec - time_start.tv_nsec); ++ return delta; ++} ++ ++#if 0 ++static void hex_dump(char* pBuf, int size) ++{ ++ int i; ++ ++ for (i = 0; i < size; i++) ++ { ++ if ((i&0xF) == 0x0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", pBuf[i]); ++ } ++ printk("\n"); ++} ++#endif ++ ++ ++#define ALLOC_RETRY_COUNT 16 ++static int perf_test_malloc(void** ppBuf, dma_addr_t* pPhys_addr, int size, int bCache) ++{ ++ void* pBuf = NULL; ++ dma_addr_t phys_addr = 0; ++ int i; ++ ++ for (i = 0; i < ALLOC_RETRY_COUNT; i++) ++ { ++ if (bCache) ++ { ++ pBuf = (void*)__get_free_pages(GFP_KERNEL, get_order(size)); ++ phys_addr = __pa(pBuf); ++ } ++ else ++ { ++ // pBuf = (void*)dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(size), &phys_addr, GFP_DMA); ++ pBuf = (void*)dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(size), &phys_addr, GFP_KERNEL); ++ } ++ if (pBuf) ++ { ++ break; ++ } ++ sysctl_compaction_handler(NULL, 1, NULL, NULL, NULL); ++ msleep(1000); ++ } ++ if (NULL == pBuf) ++ { ++ return 0; ++ } ++ *ppBuf = pBuf; ++ *pPhys_addr = phys_addr; ++ return 1; ++} ++ ++static void perf_test_mfree(void* pBuf, dma_addr_t phys_addr, int size, int bCache) ++{ ++ if (NULL == pBuf) ++ { ++ return; ++ } ++ if (bCache) ++ { ++ free_pages((long)pBuf, get_order(size)); ++ } ++ else ++ { ++ // pBuf = (void*)dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(size), &phys_addr, GFP_DMA); ++ dma_free_coherent(sys_dev.this_device, PAGE_ALIGN(size), pBuf, phys_addr); ++ } ++} ++ ++typedef struct ++{ ++ int bCache; ++ int bIMI; ++ void* pBuf; ++ dma_addr_t phys_addr; ++} bufInfo; ++ ++#ifndef CONFIG_THUMB2_KERNEL ++void _bench_neon_memcpy(void*, void*, unsigned int); ++void _bench_memcpy(void*, void*, unsigned int); ++#endif ++typedef enum { ++ PERF_TEST_SCHEME_CRT_MEMCPY, ++ PERF_TEST_SCHEME_BENCH_MEMCPY, ++ PERF_TEST_SCHEME_BENCH_NEON_MEMCPY, ++ PERF_TEST_SCHEME_ASSIGN_WRITE_ONLY, ++ PERF_TEST_SCHEME_ASSIGN_READ_ONLY, ++} perf_test_scheme_t; ++ ++static ssize_t perf_test_memcpy(const char* buf, size_t n) ++{ ++ int i; ++ unsigned long duration = 0; ++ int bitrate; ++ unsigned char dst[16]; ++ unsigned char src[16]; ++ unsigned long long iteration, size; ++ unsigned int scheme = 0; // 0: CRT memcpy, 1: _bench_memcpy, 2: _bench_neon_memcpy ++ ++ bufInfo bufInfoDst = {0} , bufInfoSrc = {0}; ++ ++ sscanf(buf, "%s %d %s %d %lld %lld %d", dst, &bufInfoDst.bCache, src, &bufInfoSrc.bCache, &iteration, &size, &scheme); ++ printk("INPUT: dst(%s) bCache(%d) src(%s) bCache(%d) iteration(%lld) size(%lld) scheme(%d)\n", dst, bufInfoDst.bCache, src, bufInfoSrc.bCache, iteration, size, scheme); ++ ++ if (0 == strcasecmp(dst, STR_IMI)) ++ { ++ bufInfoDst.bIMI = 1; ++ if ((IMI_ADDR_PHYS_1 == IMI_ADDR_INVALID) || (IMI_SIZE_1 == IMI_SIZE_INVALID)) ++ { ++ printk("[%s][%d] invalid IMI address, size 0x%08x, 0x%08x\n", __FUNCTION__, __LINE__, IMI_ADDR_PHYS_1, IMI_SIZE_1); ++ goto jump_fail; ++ } ++ if (bufInfoDst.bCache) ++ { ++ bufInfoDst.pBuf = (void*)ioremap_cache(IMI_ADDR_PHYS_1, IMI_SIZE_1); ++ } ++ else ++ { ++ bufInfoDst.pBuf = (void*)ioremap_nocache(IMI_ADDR_PHYS_1, IMI_SIZE_1); ++ } ++ } ++ else ++ { ++ bufInfoDst.bIMI = 0; ++ perf_test_malloc(&(bufInfoDst.pBuf), &(bufInfoDst.phys_addr), size, bufInfoDst.bCache); ++ } ++ if (0 == strcasecmp(src, STR_IMI)) ++ { ++ bufInfoSrc.bIMI = 1; ++ if ((IMI_ADDR_PHYS_2 == IMI_ADDR_INVALID) || (IMI_SIZE_2 == IMI_SIZE_INVALID)) ++ { ++ printk("[%s][%d] invalid IMI address, size 0x%08x, 0x%08x\n", __FUNCTION__, __LINE__, IMI_ADDR_PHYS_2, IMI_SIZE_2); ++ goto jump_fail; ++ } ++ if (bufInfoSrc.bCache) ++ { ++ bufInfoSrc.pBuf = (void*)ioremap_cache(IMI_ADDR_PHYS_2, IMI_SIZE_2); ++ } ++ else ++ { ++ bufInfoSrc.pBuf = (void*)ioremap_nocache(IMI_ADDR_PHYS_2, IMI_SIZE_2); ++ } ++ } ++ else ++ { ++ bufInfoSrc.bIMI = 0; ++ perf_test_malloc(&(bufInfoSrc.pBuf), &(bufInfoSrc.phys_addr), size, bufInfoSrc.bCache); ++ } ++ if ((NULL == bufInfoSrc.pBuf) || (NULL == bufInfoDst.pBuf)) ++ { ++ printk("[%s][%d] alloc/ioremap fail\n", __FUNCTION__, __LINE__); ++ goto jump_fail; ++ } ++ printk("[%s][%d] ==============================================\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] dst (tag, cache, addr) = (%s, %d, 0x%08x)\n", __FUNCTION__, __LINE__, dst, bufInfoDst.bCache, (int)bufInfoDst.pBuf); ++ printk("[%s][%d] src (tag, cache, addr) = (%s, %d, 0x%08x)\n", __FUNCTION__, __LINE__, src, bufInfoSrc.bCache, (int)bufInfoSrc.pBuf); ++ ++ local_irq_disable(); ++ preempt_disable(); ++ ++ //make sure the first data have cached ++ for (i=0; i< size; i++) ++ { ++ *((char*)(bufInfoSrc.pBuf)+i) = 0xA5; ++ *((char*)(bufInfoDst.pBuf)+i) = *((char*)(bufInfoSrc.pBuf)+i); ++ } ++ ++ _time_start(); ++ for (i= 0; i< iteration; i++) ++ { ++ switch(scheme) { ++ case PERF_TEST_SCHEME_CRT_MEMCPY: ++ memcpy((void*)bufInfoDst.pBuf, (void*)bufInfoSrc.pBuf, size); ++ break; ++ case PERF_TEST_SCHEME_BENCH_MEMCPY: ++#ifndef CONFIG_THUMB2_KERNEL ++ _bench_memcpy((void*)bufInfoDst.pBuf, (void*)bufInfoSrc.pBuf, size); ++#else ++ printk("CONFIG_THUMB2_KERNEL defined, NEON memcpy not supported!"); ++#endif ++ break; ++ case PERF_TEST_SCHEME_BENCH_NEON_MEMCPY: ++#ifndef CONFIG_THUMB2_KERNEL ++ _bench_neon_memcpy((void*)bufInfoDst.pBuf, (void*)bufInfoSrc.pBuf, size); ++#else ++ printk("CONFIG_THUMB2_KERNEL defined, NEON memcpy not supported!"); ++#endif ++ break; ++ case PERF_TEST_SCHEME_ASSIGN_WRITE_ONLY: ++ { ++ register unsigned int j = 0; ++ unsigned int v = 0x55; ++ for(j=0;j> 31) & 0x00000001; \ ++ (WB) = ((CCSIDR) >> 30) & 0x00000001; \ ++ (RA) = ((CCSIDR) >> 29) & 0x00000001; \ ++ (WA) = ((CCSIDR) >> 28) & 0x00000001; \ ++ (NumSet) = ((CCSIDR) >> 13) & 0x00007FFF; \ ++ (Associate) = ((CCSIDR) >> 3) & 0x000003FF; \ ++ (LineSize) = ((CCSIDR) >> 0) & 0x00000007; \ ++ } ++#define CACHE_SIZE(NumSet, Associate, LineSize) (((((NumSet)+1) * (LineSize))*((Associate)+1))>>5) ++#define CCSIDR_DUMP(str, WT, WB, RA, WA, NumSet, Associate, LineSize) \ ++ { \ ++ printk("[%s][%d] %s\n", __FUNCTION__, __LINE__, (str)); \ ++ PERF_BUF_PUT("%s\n", (str)); \ ++ printk("[%s][%d] (WT, WB, RA, WA) = (%d, %d, %d, %d)\n", __FUNCTION__, __LINE__, (WT), (WB), (RA), (WA)); \ ++ PERF_BUF_PUT(",Write through, %d\n", (WT)); \ ++ PERF_BUF_PUT(",Write back, %d\n", (WB)); \ ++ PERF_BUF_PUT(",Read allocate, %d\n", (RA)); \ ++ PERF_BUF_PUT(",Write allocate, %d\n", (WA)); \ ++ printk("[%s][%d] %d NumSet\n", __FUNCTION__, __LINE__, ((NumSet)+1)); \ ++ PERF_BUF_PUT(",NumSet, %d\n", ((NumSet)+1)); \ ++ printk("[%s][%d] %d ways\n", __FUNCTION__, __LINE__, ((Associate)+1)); \ ++ PERF_BUF_PUT(",Ways, %d\n", ((Associate)+1)); \ ++ printk("[%s][%d] line size = %d bytes\n", __FUNCTION__, __LINE__, ((LineSize)<<5) ); \ ++ PERF_BUF_PUT(",Line size (Bytes), %d\n", ((LineSize)<<5) ); \ ++ printk("[%s][%d] cache size = %d KB\n", __FUNCTION__, __LINE__, CACHE_SIZE((NumSet), (Associate), (LineSize))); \ ++ PERF_BUF_PUT(",Cache size (KBytes), %d\n", CACHE_SIZE((NumSet), (Associate), (LineSize))); \ ++ } ++ ++u32 msys_l2x0_size = 0; ++u32 msys_l2x0_ways = 0; ++u32 msys_l2x0_linesize = 32; // constant for PL310 ++ ++static ssize_t perf_test_cpuinfo(const char* buf, size_t n) ++{ ++ unsigned int MIDR = 0; ++ unsigned int MPIDR = 0; ++ unsigned int CCSIDR_L1_I = 0; ++ unsigned int CCSIDR_L1_D = 0; ++ unsigned int CCSIDR_L2 = 0; ++ unsigned int CTR = 0; ++ unsigned int cpuPart = 0; ++ char* strCPU = STR_CPUINFO_NULL; ++ int WT, WB, RA, WA, NumSet, Associate, LineSize; ++ int cpu; ++ int cpuNR = 0; ++ unsigned int CLIDR = ARM_CLIDR_READ(); ++ ++ for_each_online_cpu(cpu) ++ { ++ cpuNR++; ++ } ++ MIDR = ARM_MIDR_READ(); ++ MPIDR = ARM_MPIDR_READ(); ++ CCSIDR_L1_I = ARM_CCSIDR_L1_I_READ(); ++ CCSIDR_L1_D = ARM_CCSIDR_L1_D_READ(); ++ CCSIDR_L2 = 0; ++ if (CLIDR & 0x00000038) ++ CCSIDR_L2 = ARM_CCSIDR_L2_READ(); ++ // CCSIDR_L2 = ARM_CCSIDR_L2_READ(); ++ CTR = ARM_CTR_READ(); ++ cpuPart = ((MIDR >> 4) & 0x00000FFF); ++ switch (cpuPart) ++ { ++ case CPU_PART_CA7: ++ strCPU = STR_CPUINFO_CA7; ++ break; ++ case CPU_PART_CA9: ++ strCPU = STR_CPUINFO_CA9; ++ break; ++ case CPU_PART_CA53: ++ strCPU = STR_CPUINFO_CA53; ++ break; ++ default: ++ break; ++ } ++ // printk("[%s][%d] (MIDR, MPIDR) = (0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, MIDR, MPIDR); ++ printk("[%s][%d] (CPU type, core) = (%s, %d)\n", __FUNCTION__, __LINE__, strCPU, cpuNR); ++ PERF_BUF_PUT("CPU,%s\n", strCPU); ++ PERF_BUF_PUT("Core number,%d\n", cpuNR); ++ CCSIDR_DECODE(CCSIDR_L1_I, WT, WB, RA, WA, NumSet, Associate, LineSize); ++ CCSIDR_DUMP("L1 instruction cache information", WT, WB, RA, WA, NumSet, Associate, LineSize); ++ CCSIDR_DECODE(CCSIDR_L1_D, WT, WB, RA, WA, NumSet, Associate, LineSize); ++ CCSIDR_DUMP("L1 data cache information", WT, WB, RA, WA, NumSet, Associate, LineSize); ++ if (CPU_PART_CA9 != cpuPart) ++ { ++ CCSIDR_DECODE(CCSIDR_L2, WT, WB, RA, WA, NumSet, Associate, LineSize); ++ CCSIDR_DUMP("L2 cache information", WT, WB, RA, WA, NumSet, Associate, LineSize); ++ } ++ else ++ { ++ printk("[%s][%d] %s\n", __FUNCTION__, __LINE__, "L2 cache information"); ++ PERF_BUF_PUT("%s\n", "L2 cache information"); ++ printk("[%s][%d] %d ways\n", __FUNCTION__, __LINE__, msys_l2x0_ways); ++ PERF_BUF_PUT(",Ways,%d\n", msys_l2x0_ways); ++ printk("[%s][%d] line size = %d bytes\n", __FUNCTION__, __LINE__, msys_l2x0_linesize); ++ PERF_BUF_PUT(",Line size (Bytes), %d\n", msys_l2x0_linesize); ++ printk("[%s][%d] cache size = %d KB\n", __FUNCTION__, __LINE__, (msys_l2x0_size >> 10)); ++ PERF_BUF_PUT(",Cache size(KBytes), %d\n", (msys_l2x0_size >> 10)); ++ } ++ ++ { ++ unsigned int CLIDR = ARM_CLIDR_READ(); ++ printk("[%s][%d] CLIDR = 0x%08x\n", __FUNCTION__, __LINE__, CLIDR); ++ } ++ ++ ++ return n; ++} ++ ++ ++// all /vendor/2222.txt ++// cpuinfo ++// MIU 1 MIU 1 10000 65536 0 ++// IMI 1 IMI 1 10000 65536 0 ++// cache 32768 100000 ++ ++char cmdBuf[128] = { 0 }; ++ ++static ssize_t perf_test_all(const char* buf, size_t n) ++{ ++ // char buf[100]; ++ char temp[8]; ++ char filename[128]; ++ char filename_org[128]; ++ mm_segment_t old_fs; ++ ++ if (NULL == PERF_BUF_ALLOC()) ++ { ++ printk("[%s][%d] kzalloc fail with size %d\n", __FUNCTION__, __LINE__, FILEBUF_SIZE); ++ return n; ++ } ++ sscanf(buf, "%s %s", temp, filename_org); ++ ++ // cpu information ++ strcpy(filename, filename_org); ++ PERF_TEST_FILENAME_MAKE(filename, STR_CPUINFO, ".csv"); ++ if (PERF_TEST_FILE_OPEN(filename)) ++ { ++ old_fs = get_fs(); ++ set_fs(get_ds()); ++ PERF_TEST_CMD_MAKE_CPUINFO(cmdBuf); ++ perf_test_cpuinfo(cmdBuf, strlen(cmdBuf)); ++ PERF_BUF_SYNC(); ++ PERF_BUF_RESET(); ++ PERF_TEST_FILE_CLOSE(); // filp_close(fp, NULL); ++ set_fs(old_fs); ++ } ++ // cache testing ++ strcpy(filename, filename_org); ++ PERF_TEST_FILENAME_MAKE(filename, STR_CACHE, ".csv"); ++ if (PERF_TEST_FILE_OPEN(filename)) ++ { ++ int size[] = { 4096, 8192, 16394, 32768, 65536, 131072 }; ++ int i = 0; ++ int iteration = 10000; ++ ++ old_fs = get_fs(); ++ set_fs(get_ds()); ++ PERF_BUF_PUT("Size,Bytes\n"); ++ PERF_BUF_PUT("Iteration,%d\n", iteration); ++ PERF_BUF_PUT("Time,Nanoseconds\n"); ++ PERF_BUF_PUT("Size,L1(Inv),L2(Inv),L1(Clean),L2(Clean),L1(Inv dirty),L2(Inv dirty),L1(Clean dirty),L2(Clean dirty)\n"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_TEST_CMD_MAKE_CACHE(cmdBuf, size[i], iteration); ++ perf_test_cache(cmdBuf, strlen(cmdBuf)); ++ } ++ PERF_BUF_SYNC(); ++ PERF_BUF_RESET(); ++ PERF_TEST_FILE_CLOSE(); // filp_close(fp, NULL); ++ set_fs(old_fs); ++ } ++ ++ // MIU testing ++ strcpy(filename, filename_org); ++ PERF_TEST_FILENAME_MAKE(filename, STR_MIU, ".csv"); ++ if (PERF_TEST_FILE_OPEN(filename)) ++ { ++ int size[] = { 4096, 8192, 16384, 32768, 65536, 131072, 262144, 524288, 1048576, 2097152 }; ++ int iter_noncache[] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000, 500, 500, 500}; ++ int iter[] = { 10000, 10000, 10000, 10000, 10000, 10000, 5000, 5000, 1000, 1000}; ++ int i = 0; ++ int iteration = 10000; ++ ++ old_fs = get_fs(); ++ set_fs(get_ds()); ++ PERF_BUF_PUT("Size,Bytes\n"); ++ PERF_BUF_PUT("Iteration,%d\n", iteration); ++ PERF_BUF_PUT("Bit rate,MBytes/Sec\n\n\n\n"); ++ // non-cache ++ PERF_BUF_PUT("%s noncache\n", STR_MIU); ++ PERF_BUF_PUT("Size,"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_BUF_PUT("%d,", size[i]); ++ } ++ PERF_BUF_PUT("\n"); ++ PERF_BUF_PUT("Bit rate,"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_TEST_CMD_MAKE_MIU(cmdBuf, 0, size[i], iter_noncache[i], 0); ++ perf_test_memcpy(cmdBuf, strlen(cmdBuf)); ++ } ++ PERF_BUF_PUT("\n"); ++ PERF_BUF_PUT("\n"); ++ // cache ++ PERF_BUF_PUT("%s cache\n", STR_MIU); ++ PERF_BUF_PUT("Size,"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_BUF_PUT("%d,", size[i]); ++ } ++ PERF_BUF_PUT("\n"); ++ PERF_BUF_PUT("Bit rate,"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_TEST_CMD_MAKE_MIU(cmdBuf, 1, size[i], iter[i], 0); ++ perf_test_memcpy(cmdBuf, strlen(cmdBuf)); ++ } ++ PERF_BUF_PUT("\n"); ++ PERF_BUF_SYNC(); ++ PERF_BUF_RESET(); ++ PERF_TEST_FILE_CLOSE(); // filp_close(fp, NULL); ++ set_fs(old_fs); ++ } ++ ++ // IMI testing ++ strcpy(filename, filename_org); ++ PERF_TEST_FILENAME_MAKE(filename, STR_IMI, ".csv"); ++ if (PERF_TEST_FILE_OPEN(filename)) ++ { ++ int size[] = { 32768}; // , 65536, 131072, 262144, 524288, 1048576, 2097152 }; ++ int i = 0; ++ int iteration = 10000; ++ ++ old_fs = get_fs(); ++ set_fs(get_ds()); ++ ++ PERF_BUF_PUT("Size,Bytes\n"); ++ PERF_BUF_PUT("Iteration,%d\n", iteration); ++ PERF_BUF_PUT("Bit rate,MBytes/Sec\n\n\n\n"); ++ // non-cache ++ PERF_BUF_PUT("%s noncache\n", STR_IMI); ++ PERF_BUF_PUT("Size,"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_BUF_PUT("%d,", size[i]); ++ } ++ PERF_BUF_PUT("\n"); ++ PERF_BUF_PUT("Bit rate,"); ++ for (i = 0 ; i < sizeof(size)/sizeof(size[0]); i++) ++ { ++ PERF_TEST_CMD_MAKE_IMI(cmdBuf, 0, size[i], 10000, 0); ++ perf_test_memcpy(cmdBuf, strlen(cmdBuf)); ++ } ++ PERF_BUF_PUT("\n"); ++ PERF_BUF_SYNC(); ++ PERF_BUF_RESET(); ++ PERF_TEST_FILE_CLOSE(); // filp_close(fp, NULL); ++ set_fs(old_fs); ++ } ++ ++ PERF_BUF_FREE(); ++ return n; ++} ++ ++static ssize_t perf_test_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ int n; ++ ++ n = sprintf(str, "[%s][%d] this is a perf_test_show\n", __FUNCTION__, __LINE__); ++ return n; ++} ++ ++static ssize_t perf_test_entry(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ unsigned char token[16]; ++ sscanf(buf, "%s", token); ++ if (0 == strcasecmp(token, STR_CPUINFO)) ++ { ++ return perf_test_cpuinfo(buf, n); ++ } ++ else if (0 == strcasecmp(token, STR_IMI)) ++ { ++ return perf_test_memcpy(buf, n); ++ } ++ else if (0 == strcasecmp(token, STR_MIU)) ++ { ++ return perf_test_memcpy(buf, n); ++ } ++ else if (0 == strcasecmp(token, STR_CACHE)) ++ { ++ return perf_test_cache(buf, n); ++ } ++ else if (0 == strcasecmp(token, STR_ALL)) ++ { ++ return perf_test_all(buf, n); ++ } ++ else if (0 == strcasecmp(token, "tc")) ++ { ++ return perf_test_memcpy_cacheable(buf, n); ++ } ++ else if (0 == strcasecmp(token, "L1RADIS")) ++ { ++ return perf_test_L1RADIS(buf, n); ++ } ++ ++ return n; ++} ++DEVICE_ATTR(perf_test, 0644, perf_test_show, perf_test_entry); ++ ++int msys_perf_test_init(void) ++{ ++ device_create_file(sys_dev.this_device, &dev_attr_perf_test); ++ return 0; ++} ++device_initcall(msys_perf_test_init); +diff --git a/drivers/sstar/msys/platform_msys.h b/drivers/sstar/msys/platform_msys.h +new file mode 100644 +index 000000000000..d9d5cfd6b86b +--- /dev/null ++++ b/drivers/sstar/msys/platform_msys.h +@@ -0,0 +1,23 @@ ++/* ++* platform_msys.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _PLATFORM_MSYS_H_ ++#define _PLATFORM_MSYS_H_ ++ ++int msys_request_freq(MSYS_FREQGEN_INFO *freq_info); ++ ++#endif +diff --git a/drivers/sstar/netphy/Kconfig b/drivers/sstar/netphy/Kconfig +new file mode 100755 +index 000000000000..777196076435 +--- /dev/null ++++ b/drivers/sstar/netphy/Kconfig +@@ -0,0 +1,6 @@ ++config SSTAR_NETPHY ++ tristate "SSTAR 10/100 PHYs" ++ default y ++ ---help--- ++ Currently supports the SSTAR ALBANY(10/100) ++ +diff --git a/drivers/sstar/netphy/Makefile b/drivers/sstar/netphy/Makefile +new file mode 100755 +index 000000000000..8156e5159cc7 +--- /dev/null ++++ b/drivers/sstar/netphy/Makefile +@@ -0,0 +1,6 @@ ++# ++# Makefile for MStar EMAC device drivers. ++# ++ ++obj-$(CONFIG_SSTAR_NETPHY) += sstar_100_phy.o ++ +diff --git a/drivers/sstar/netphy/sstar_100_phy.c b/drivers/sstar/netphy/sstar_100_phy.c +new file mode 100755 +index 000000000000..ce70251d6582 +--- /dev/null ++++ b/drivers/sstar/netphy/sstar_100_phy.c +@@ -0,0 +1,409 @@ ++#include ++#include ++#include ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++#define NETPHYINFO_ENABLE 0 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if NETPHYINFO_ENABLE ++ #define NETPHY_PRINT(x, args...) { printk(x, ##args); } ++#else ++ #define NETPHY_PRINT(x, args...) { } ++#endif ++ ++#define SSTAR_100_PHY_ID 0x11112222 ++#define SSTAR_100_PHY_ID_MSK 0xffffffff ++ ++typedef struct ++{ ++ int cnt_restart; ++} sstar_phy_priv_t; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Implementation ++//------------------------------------------------------------------------------------------------- ++static int sstar_phy_config_init(struct phy_device *phydev) ++{ ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++ // phy_write(phydev, MII_BMCR, 0x1000); ++ // phy_write(phydev, MII_BMCR, 0x1000); ++ return genphy_config_init(phydev); ++ // return 0; ++} ++ ++static int sstar_phy_reset(struct phy_device *phydev) ++{ ++#if 0 ++ phy_write(phydev, MII_BMCR, BMCR_RESET); ++ msleep(50); ++ phy_write(phydev, MII_BMCR, 0); ++ msleep(10); ++ phy_write(phydev, MII_BMCR, 0x1000); ++ phy_write(phydev, MII_BMCR, 0x1000); ++#endif ++ return 0; ++} ++ ++#define PHY_AN(phydev, cnt) \ ++{ \ ++ (cnt)++; \ ++ if (10 < (cnt)) \ ++ { \ ++ phy_write((phydev), MII_BMCR, 0x1200); \ ++ NETPHY_PRINT("[%s][%d] restart an process\n", __FUNCTION__, __LINE__); \ ++ (cnt) = 0; \ ++ return 1; \ ++ } \ ++} ++ ++static int sstar_phy_patch(struct phy_device *phydev) ++{ ++ u32 hcd_link_st_ok, an_100t_link_st = 0; ++ // static unsigned int phy_restart_cnt = 0; ++ u32 an_state1 = 0; ++ u32 an_state2 = 0; ++ u32 an_state3 = 0; ++ sstar_phy_priv_t* priv = (sstar_phy_priv_t*)phydev->priv; ++ ++ if (0 == phydev->link) ++ return 0; ++ if (SPEED_100 != phydev->speed) ++ return 0; ++ ++ if (0xffff == (hcd_link_st_ok = phy_read(phydev, 0x21))) ++ return 0; ++ if (0xffff == (an_100t_link_st = phy_read(phydev, 0x22))) ++ return 0; ++ ++ if ((!(hcd_link_st_ok & 0x100) && ((an_100t_link_st & 0x300) == 0x200))) ++ { ++ // phy_restart_cnt++; ++ // gu32PhyResetCount1++; ++ NETPHY_PRINT("[%s][%d] hcd_link_st_ok:0x%08x, an_100t_link_st:0x%08x\n", __FUNCTION__, __LINE__, hcd_link_st_ok, an_100t_link_st); ++ PHY_AN(phydev, priv->cnt_restart); ++ } ++ else if (((hcd_link_st_ok & 0x100) && !(an_100t_link_st & 0x300))) ++ { ++ // phy_restart_cnt++; ++ // gu32PhyResetCount1++; ++ NETPHY_PRINT("[%s][%d] hcd_link_st_ok:0x%08x, an_100t_link_st:0x%08x\n", __FUNCTION__, __LINE__, hcd_link_st_ok, an_100t_link_st); ++ PHY_AN(phydev, priv->cnt_restart); ++ } ++ ++ /* Monitor AN state*/ ++ if (0xffff == (an_state1 = phy_read(phydev, 0x2e))) ++ return 0; ++ if (0xffff == (an_state2 = phy_read(phydev, 0x2e))) ++ return 0; ++ if (0xffff == (an_state3 = phy_read(phydev, 0x2e))) ++ return 0; ++ ++ if ((an_state1 != an_state2) || (an_state1 != an_state3)) ++ { ++ NETPHY_PRINT("[%s][%d] an_state 1:0x%08x, 2:0x%08x, 3:0x%08x\n", __FUNCTION__, __LINE__, an_state1, an_state2, an_state3); ++ return 0; ++ } ++ ++ if ((an_state1 & 0xf000) == 0x3000) ++ { ++ // phy_restart_cnt++; ++ // gu32PhyResetCount3++; ++ NETPHY_PRINT("[%s][%d] an_state=0x%x\n", __FUNCTION__, __LINE__, an_state1); ++ PHY_AN(phydev, priv->cnt_restart); ++ } ++ else if ((an_state1 & 0xf000) == 0x2000) ++ { ++ // phy_restart_cnt++; ++ // gu32PhyResetCount4++; ++ NETPHY_PRINT("[%s][%d] an_state=0x%x\n", __FUNCTION__, __LINE__, an_state1); ++ PHY_AN(phydev, priv->cnt_restart); ++ } ++ return 0; ++} ++ ++static int sstar_phy_update_speed_patch(struct phy_device *phydev) ++{ ++ u32 hcd_link_st_ok = 0; ++ u32 phy_speed = 0; ++ u32 detect_100m = 0; ++ ++ if (0 == phydev->link) ++ { ++ NETPHY_PRINT("[%s][%d] link fail! phydev_link:%d\n", __FUNCTION__, __LINE__, phydev->link); ++ return 0; ++ } ++ ++ if (0xffff == (phy_speed = phy_read(phydev, 0x00))) ++ return 0; ++ if (0xffff == (hcd_link_st_ok = phy_read(phydev, 0x21))) ++ return 0; ++ if (0xffff == (detect_100m = phy_read(phydev, 0x22))) ++ return 0; ++ ++ if( !(hcd_link_st_ok & 0x100) ) ++ { ++ NETPHY_PRINT("[%s][%d] link fail! hcd_link_st:0x%08x\n", __FUNCTION__, __LINE__, hcd_link_st_ok); ++ return 0; ++ } ++ ++ if ( !(phy_speed & 0x2000) && (detect_100m & 0x20) ) ++ { ++ NETPHY_PRINT("[%s][%d] speed change 10 -> 100\n", __FUNCTION__, __LINE__); ++ phy_write((phydev), MII_BMCR, 0x1200); ++ } ++ ++ if (phy_speed & 0x2000) ++ { ++ phydev->speed = SPEED_100; ++ NETPHY_PRINT("[%s] SPEED_100 \n", __FUNCTION__); ++ } ++ else ++ { ++ phydev->speed = SPEED_10; ++ NETPHY_PRINT("[%s] SPEED_10 \n", __FUNCTION__); ++ } ++ ++ if (phy_speed & 0x100) ++ { ++ phydev->duplex = DUPLEX_FULL; ++ NETPHY_PRINT("[%s] DUPLEX_FULL \n", __FUNCTION__); ++ } ++ else ++ { ++ phydev->duplex = DUPLEX_HALF; ++ NETPHY_PRINT("[%s] DUPLEX_HALF \n", __FUNCTION__); ++ } ++ ++ return 0; ++} ++ ++#if 0 ++static int sstar_phy_update_link(struct phy_device *phydev) ++{ ++ int status; ++ ++ /* Do a fake read */ ++ status = phy_read(phydev, MII_BMSR); ++ if (status < 0) ++ return status; ++ ++ /* Read link and autonegotiation status */ ++ status = phy_read(phydev, MII_BMSR); ++ if (status < 0) ++ return status; ++ ++ if ((status & BMSR_LSTATUS) == 0) ++ phydev->link = 0; ++ else ++ phydev->link = 1; ++ ++ return 0; ++} ++#endif ++ ++#if 0 ++static int _sstar_phy_read_status(struct phy_device *phydev) ++{ ++ int adv; ++ // int err; ++ int lpa; ++ // int lpagb = 0; ++ // int common_adv; ++ // int common_adv_gb = 0; ++ int bmcr = 0; ++ int bmsr = 0; ++ unsigned int neg; ++ ++#if 0 ++ /* Update the link, but return if there was an error */ ++ err = sstar_phy_update_link(phydev); ++ if (err) ++ return err; ++#else ++ bmsr = phy_read(phydev, MII_BMSR); ++ bmsr = phy_read(phydev, MII_BMSR); ++ if (bmsr < 0) ++ return bmsr; ++ ++ if ((bmsr & BMSR_LSTATUS) == 0) ++ { ++ phydev->link = 0; ++ } ++ else ++ { ++ phydev->link = 1; ++ } ++#endif ++ ++ phydev->lp_advertising = 0; ++ bmcr = phy_read(phydev, MII_BMCR); ++ // phydev->autoneg = (bmcr & BMCR_ANENABLE) ? BMCR_ANENABLE : AUTONEG_DISABLE; ++ // if (AUTONEG_ENABLE != phydev->autoneg) { ++ if (!(bmcr & BMCR_ANENABLE)) ++ { ++ if (bmcr < 0) ++ return bmcr; ++ ++ if (bmcr & BMCR_FULLDPLX) ++ phydev->duplex = DUPLEX_FULL; ++ else ++ phydev->duplex = DUPLEX_HALF; ++ ++ if (bmcr & BMCR_SPEED100) ++ phydev->speed = SPEED_100; ++ else ++ phydev->speed = SPEED_10; ++ ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ return 0; ++ } ++ ++ // if (AUTONEG_ENABLE == phydev->autoneg) { ++ // if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ lpa = phy_read(phydev, MII_LPA); ++ /* For Link Parterner adopts force mode and EPHY used, ++ * EPHY LPA reveals all zero value. ++ * EPHY would be forced to Full-Duplex mode. ++ */ ++ if (!lpa) ++ { ++ /* 100Mbps Full-Duplex */ ++ if (bmcr & BMCR_SPEED100) ++ lpa |= LPA_100FULL; ++ else /* 10Mbps Full-Duplex */ ++ lpa |= LPA_10FULL; ++ } ++ if (lpa < 0) ++ return lpa; ++ ++ phydev->lp_advertising |= mii_lpa_to_ethtool_lpa_t(lpa); ++ ++ adv = phy_read(phydev, MII_ADVERTISE); ++ if (adv < 0) ++ return adv; ++ ++ neg = lpa & adv; ++ ++ phydev->speed = SPEED_10; ++ phydev->duplex = DUPLEX_HALF; ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ ++ if (neg & LPA_100FULL) ++ { ++ phydev->speed = SPEED_100; ++ phydev->duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_100HALF) ++ { ++ phydev->speed = SPEED_100; ++ phydev->duplex = DUPLEX_HALF; ++ } ++ else if (neg & LPA_10FULL) ++ { ++ phydev->speed = SPEED_10; ++ phydev->duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_10HALF) ++ { ++ phydev->speed = SPEED_10; ++ phydev->duplex = DUPLEX_HALF; ++ } ++ else ++ { ++ phydev->speed = SPEED_10; ++ phydev->duplex = DUPLEX_HALF; ++ NETPHY_PRINT("[%s][%d] No speed and mode found (LPA=0x%8x, ADV=0x%8x)\n", __FUNCTION__, __LINE__, lpa, adv); ++ } ++ if (phydev->duplex == DUPLEX_FULL) { ++ phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; ++ phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; ++ } ++ return 0; ++ } ++ return 0; ++} ++#endif ++ ++static int sstar_phy_read_status(struct phy_device *phydev) ++{ ++ int ret; ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++ ++ ret = genphy_read_status(phydev); ++ // ret = _sstar_phy_read_status(phydev); ++ if ((0 == ret) && (1 == phydev->link)) ++ { ++ sstar_phy_patch(phydev); ++ sstar_phy_update_speed_patch(phydev); ++ } ++ return ret; ++} ++ ++static int sstar_phy_config_aneg(struct phy_device *phydev) ++{ ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++#if 0 ++ phy_write(phydev, MII_BMCR, 0x1000); ++ phy_write(phydev, MII_BMCR, 0x1000); ++#endif ++ // genphy_config_aneg(phydev); ++ return genphy_config_aneg(phydev); ++ // genphy_restart_aneg(phydev); ++ // return 0; ++} ++ ++ ++static int sstar_phy_probe(struct phy_device *phydev) ++{ ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++ if (NULL == (phydev->priv = kzalloc(sizeof(sstar_phy_priv_t), GFP_KERNEL))) ++ return -ENOMEM; ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++static void sstar_phy_remove(struct phy_device *phydev) ++{ ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++ if (phydev->priv) ++ kfree(phydev->priv); ++ // printk("[%s][%d]\n", __FUNCTION__, __LINE__); ++} ++ ++ ++static struct phy_driver __maybe_unused sstar_phy_drvs[] = { ++ { ++ .phy_id = SSTAR_100_PHY_ID, ++ .phy_id_mask = SSTAR_100_PHY_ID_MSK, ++ .name = "SStar 10/100 Ethernet Phy", ++ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause), ++ .config_aneg = sstar_phy_config_aneg, ++ .read_status = sstar_phy_read_status, ++ .config_init = sstar_phy_config_init, ++ .soft_reset = sstar_phy_reset, ++ .probe = sstar_phy_probe, ++ .remove = sstar_phy_remove, ++ }, ++}; ++ ++module_phy_driver(sstar_phy_drvs); ++ ++static struct mdio_device_id __maybe_unused sstar_phy_tbl[] = { ++ { SSTAR_100_PHY_ID, SSTAR_100_PHY_ID_MSK }, ++ { } ++}; ++MODULE_DEVICE_TABLE(mdio, sstar_phy_tbl); ++ ++MODULE_DESCRIPTION("SStar 100 PHY driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/noe/Kconfig b/drivers/sstar/noe/Kconfig +new file mode 100755 +index 000000000000..66390bf05256 +--- /dev/null ++++ b/drivers/sstar/noe/Kconfig +@@ -0,0 +1,19 @@ ++config MS_NOE ++ tristate "Sstar NOE driver" ++ depends on ARCH_INFINITY2 ++ help ++ MStar NOE driver function ++ ++if MS_NOE ++ ++menu "SStar Network Offload Engine" ++source "drivers/sstar/noe/drv/eth/Kconfig" ++if NETFILTER ++config NOE_NAT_HW ++ bool "HW NAT support (Module Mode Only)" ++ depends on NOE ++source "drivers/sstar/noe/drv/nat/hw_nat/Kconfig" ++endif # if NETFILTER ++endmenu #"MStar Network Offload Engine" ++ ++endif +diff --git a/drivers/sstar/noe/Makefile b/drivers/sstar/noe/Makefile +new file mode 100755 +index 000000000000..9006ecd40afc +--- /dev/null ++++ b/drivers/sstar/noe/Makefile +@@ -0,0 +1,13 @@ ++# ++# Makefile for MStar device drivers. ++# ++ ++# noe ++obj-$(CONFIG_NOE) += drv/eth/ ++ ++ifeq ($(CONFIG_NOE_NAT_HW),y) ++obj-$(CONFIG_NOE_NAT_HW) += drv/nat/hook/ ++obj-m += drv/nat/hw_nat/ ++endif ++ ++ +diff --git a/drivers/sstar/noe/drv/eth/Kconfig b/drivers/sstar/noe/drv/eth/Kconfig +new file mode 100755 +index 000000000000..2e65c72cc9d2 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/Kconfig +@@ -0,0 +1,173 @@ ++config NOE ++# bool "Ethernet GMAC" ++ tristate ++ depends on MS_NOE ++ default MS_NOE ++ ---help--- ++ This driver support gigabit ethernet family of adapters. ++ ++if NOE ++ ++config NOE_FPGA_VERIFY ++ bool ++ ++config NOE_NO_CHECK_ACTIVE_SETMAC ++ bool "Not check active when setting MAC address" ++ default y ++ ++choice ++ prompt "GMAC1 is connected to" ++ depends on NOE ++ default GE1_GMII_AN_EXTPHY ++ ++config GE1_GMII_AN_EXTPHY ++ bool "GMII_AN (External GigaPhy)" ++ ++endchoice ++ ++config MAC_TO_GIGAPHY_MODE_ADDR ++ hex "GE1 Phy Address" ++ default 0x1 if GE1_GMII_AN_EXTPHY ++ ++ ++config NOE_GMAC2 ++ bool "GMAC2 Support" ++ depends on NOE ++ default y ++ ++choice ++ prompt "GMAC2 is connected to" ++ depends on NOE_GMAC2 ++ default GE2_GMII_AN_EXTPHY ++ ++config GE2_GMII_AN_EXTPHY ++ bool "GMII (External GigaPhy)" ++ depends on NOE_GMAC2 ++endchoice ++ ++config MAC_TO_GIGAPHY_MODE_ADDR2 ++ hex "GE2 Phy Address" ++ default 0x3 if GE2_GMII_AN_EXTPHY ++ depends on NOE_GMAC2 ++ ++config MDIO_IC1819 ++ bool "MDIO_IC1819 (SW MDIO TO CONTROL IC1819)" ++ depends on NOE_GMAC2 ++ select MS_MDIO ++ ++config NOE_RGMII_TX_DELAY_2NS ++ bool "RGMII tx delay 2ns default" ++ depends on NOE ++ default y ++ ++#choice ++# prompt "Network BottomHalves" ++# depends on NOE ++# default NOE_NETWORK_TASKLET_BH ++ ++config NOE_NETWORK_TASKLET_BH ++# bool "Tasklet" ++ bool ++ default n ++ ++config NOE_NETWORK_WORKQUEUE_BH ++# bool "Work Queue" ++ bool ++ default n ++ ++config NOE_NAPI ++# bool "NAPI" ++ bool ++ default y ++#endchoice ++ ++#config NOE_SPECIAL_TAG ++# bool "Special Tag (0x810x)" ++# depends on NOE ++ ++config NOE_CHECKSUM_OFFLOAD ++ bool ++ default y ++ depends on NOE ++ ++#config NOE_HW_IOCOHERENT ++# bool ++# default n ++# depends on NOE ++ ++config NOE_HW_LRO ++# bool "HW LRO" ++ bool ++ default y ++ depends on NOE ++ ++config NOE_HW_VLAN_TX ++ bool ++ default y ++ depends on NOE ++ ---help--- ++ Please disable HW_VLAN_TX if you need double vlan ++ ++config NOE_HW_VLAN_RX ++ bool ++ default n ++ depends on NOE ++ ---help--- ++ Please disable HW_VLAN_RX if you need double vlan ++ ++config NOE_TSO ++ bool ++ default y ++ depends on NOE_HW_VLAN_TX ++ ++config NOE_ETHTOOL ++ select MII ++ bool "support ethtool" ++ default n ++ depends on NOE ++ ++config NOE_QDMA ++ bool "Choose QDMA istead PDMA" ++ bool ++ default y ++ depends on NOE ++ ++config NOE_QDMATX_QDMARX ++ bool ++ depends on NOE_QDMA ++ ++config HW_SFQ ++ bool ++ depends on NOE_QDMA ++ ++config ESW_DOUBLE_VLAN_TAG ++ bool ++ default n ++ ++config ETH_SKB_ALLOC_SELECT ++ bool ++ default y ++ ++#choice ++# prompt "SKB Allocation API Selection" ++# depends on ETH_SKB_ALLOC_SELECT ++# default ETH_SLAB_ALLOC_SKB ++ ++config ETH_SLAB_ALLOC_SKB ++ #bool "SLAB skb allocation" ++ bool ++ default y ++ ++config ETH_PAGE_ALLOC_SKB ++ #bool "Page skb allocation" ++ bool ++ default n ++ ++#endchoice ++ ++#config NOE_TX_RX_INT_SEPARATION ++# bool "Interrupt Separation" ++# default y ++ ++ ++endif # NOE +diff --git a/drivers/sstar/noe/drv/eth/Makefile b/drivers/sstar/noe/drv/eth/Makefile +new file mode 100755 +index 000000000000..7d00e971da20 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/Makefile +@@ -0,0 +1,44 @@ ++# ++# Makefile for SStar NOE device drivers. ++# ++ ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/noe/drv/eth ++EXTRA_CFLAGS += -Idrivers/sstar/noe/hal/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++ ++EXTRA_CFLAGS += -DMDRV_NOE_DBG_SKB_DUMP ++ ++obj-$(CONFIG_NOE) += mdrv-noe.o ++mdrv-noe-objs := mdrv_noe_mac.o mdrv_noe_phy.o mdrv_noe_log.o mdrv_noe_proc.o mdrv_noe.o mdrv_noe_pdma.o mdrv_noe_utils.o ++ ++ ++ifeq ($(CONFIG_NOE_QDMA),y) ++mdrv-noe-objs += mdrv_noe_qdma.o ++endif ++ ++ifeq ($(CONFIG_NOE_ETHTOOL),y) ++mdrv-noe-objs += mdrv_noe_ethtool.o ++endif ++ ++mdrv-noe-objs += mdrv_noe_lro.o ++mdrv-noe-objs += mdrv_noe_lro_proc.o ++ ++ ++ ++ifeq ($(CONFIG_NOE_NAT_HW),y) ++EXTRA_CFLAGS += -Idrivers/sstar/noe/drv/nat/hw_nat ++endif ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++ccflags-y += -Werror ++ ++mdrv-noe-objs += ../../hal/$(CONFIG_SSTAR_CHIP_NAME)/mhal_noe.o ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe.c b/drivers/sstar/noe/drv/eth/mdrv_noe.c +new file mode 100755 +index 000000000000..5c903fce08f8 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe.c +@@ -0,0 +1,2365 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mdrv_noe.h" ++#include "mdrv_noe_ioctl.h" ++#include "mdrv_noe_ethtool.h" ++#include "irqs.h" ++#include "mdrv_noe_nat.h" ++#include "mdrv_noe_dma.h" ++#include ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++#if NETDEV_LRO_SUPPORTED ++#define IS_TRAFFIC_RECEIVED_OFFLOAD(rx_skb, napi) likely((rx_skb)->ip_summed == CHECKSUM_UNNECESSARY) ++#define TRAFFIC_RECEIVED_OFFLOAD(ei_local, napi, rx_skb) lro_receive_skb(&ei_local->lro_mgr, rx_skb, NULL); ++#else ++#define IS_TRAFFIC_RECEIVED_OFFLOAD(rx_skb, napi) likely(((rx_skb)->ip_summed == CHECKSUM_UNNECESSARY) && ((napi) != NULL)) ++#define TRAFFIC_RECEIVED_OFFLOAD(ei_local, napi, rx_skb) napi_gro_receive(napi, rx_skb); ++#endif /* NETDEV_LRO_SUPPORTED */ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Variable and Functions ++//-------------------------------------------------------------------------------------------------- ++struct device *gdebug_class_dev; ++struct net_device *g_dev_noe; ++#ifdef CONFIG_NOE_NAT_HW ++EXPORT_SYMBOL(g_dev_noe); ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++ ++static int MDrv_NOE_Set_Mac2_Addr(struct net_device *dev, void *p); ++static int MDrv_NOE_Set_Mac_Addr(struct net_device *dev, void *p); ++static void MDrv_NOE_Set_Mac2(struct net_device *dev); ++static void MDrv_NOE_Set_Mac(struct net_device *dev); ++#if NETDEV_LRO_SUPPORTED ++static int MDrv_NOE_Get_Skb_Header(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv); ++#endif ++static int MDrv_NOE_Full_Poll(struct napi_struct *napi, int budget); ++static int MDrv_NOE_RX_Poll(struct napi_struct *napi, int budget); ++static int MDrv_NOE_TX_Poll(struct napi_struct *napi, int budget); ++static void MDrv_NOE_Register_Func(struct END_DEVICE *ei_local); ++static int __init MDrv_NOE_Init(struct net_device *dev); ++static inline int MDrv_NOE_Init_Txp_Rxp(struct net_device *dev); ++static inline int MDrv_NOE_Init_Txq_Rxp(struct net_device *dev); ++static inline int MDrv_NOE_Init_Txq_Rxq(struct net_device *dev); ++static int MDrv_NOE_Init_Dma(struct net_device *dev); ++static void MDrv_NOE_Uninit(struct net_device *dev); ++void virtif_setup_statistics(struct PSEUDO_ADAPTER *p_ad); ++int MDrv_NOE_Virtif_Open(struct net_device *dev); ++int MDrv_NOE_Virtif_Close(struct net_device *dev); ++int MDrv_NOE_Virtif_Start_Xmit(struct sk_buff *p_skb, struct net_device *dev); ++struct net_device_stats *MDrv_NOE_Virtif_Get_Stats(struct net_device *dev); ++int MDrv_NOE_Virtif_Ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd); ++static int MDrv_NOE_Change_Mtu(struct net_device *dev, int new_mtu); ++static int MDrv_NOE_Disable_Clock(struct END_DEVICE *ei_local); ++void MDrv_NOE_Virtif_Init(struct END_DEVICE *p_ad, struct net_device *net_dev); ++int MDrv_NOE_Open(struct net_device *dev); ++int MDrv_NOE_Close(struct net_device *dev); ++static int MDrv_NOE_Start_Xmit(struct sk_buff *skb, struct net_device *dev); ++struct net_device_stats *MDrv_NOE_Get_Stats(struct net_device *dev); ++int MDrv_NOE_Ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++void MDrv_NOE_Setup_Fptable(struct net_device *dev); ++static int MDrv_NOE_Eth_Recv(struct net_device *dev, struct napi_struct *napi, int budget); ++static void MDrv_NOE_Reset_Statistics(struct END_DEVICE *ei_local); ++static inline void MDrv_NOE_Init_Rx_Desc(struct PDMA_rxdesc *rx_ring, dma_addr_t dma_addr); ++static void MDrv_NOE_Deinit_Dma(struct net_device *dev); ++static irqreturn_t MDrv_NOE_NAPI_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_NAPI_Separate_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_NAPI_RX_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_NAPI_Separate_RX_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_RX_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_NAPI_TX_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_NAPI_Separate_TX_Interrupt(int irq, void *dev_id); ++static irqreturn_t MDrv_NOE_TX_Interrupt(int irq, void *dev_id); ++static inline void MDrv_NOE_Recv(void); ++static void MDrv_NOE_Tasklet_Recv(unsigned long unused); ++static void MDrv_NOE_Workq_Recv(struct work_struct *work); ++static int MDrv_NOE_Enable_Intr(struct net_device *dev); ++static int MDrv_NOE_Disable_Intr(struct net_device *dev); ++int MDrv_NOE_Set_Forward_Cfg(struct net_device *dev); ++static int MDrv_NOE_Enable_Clock(struct END_DEVICE *ei_local); ++void MDrv_NOE_Set_Io_Coherence(struct END_DEVICE *ei_local); ++static int MDrv_NOE_Probe(struct platform_device *pdev); ++static int MDrv_NOE_Remove(struct platform_device *pdev); ++ ++ ++#if NETDEV_LRO_SUPPORTED ++static void MDrv_NOE_Init_Napi_Lro(struct net_device *dev); ++static int MDrv_NOE_Get_Skb_Header(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv); ++#ifdef CONFIG_INET_LRO ++static inline void _MDrv_NOE_Flush_Lro_All(struct net_lro_mgr *lro_mgr) { lro_flush_all(lro_mgr); } ++#else ++static inline void _MDrv_NOE_Flush_Lro_All(struct net_lro_mgr *lro_mgr) { } ++#endif ++#endif /* NETDEV_LRO_SUPPORTED */ ++ ++#ifdef CONFIG_PM ++static int MDrv_NOE_Resume(struct platform_device *pdev); ++static int MDrv_NOE_Suspend(struct platform_device *pdev, pm_message_t state); ++#endif ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++static u64 noe_dmamask = ~(u32)0; ++static int pending_recv; ++unsigned char mac_uboot[6]; ++unsigned char mac1_uboot[6]; ++ ++ ++/* LRO support */ ++unsigned int lan_ip; ++struct lro_para_struct lro_para; ++int lro_flush_needed; ++ ++static const char *const _mdrv_noe_clk_source_name[] = { ++ "ethif", ++ "esw", ++ "gp0", ++ "gp1", ++ "gp2", ++ "sgmii_tx250m", ++ "sgmii_rx250m", ++ "sgmii_cdr_ref", ++ "sgmii_cdr_fb", ++ "trgpll", ++ "sgmipll", ++ "eth1pll", ++ "eth2pll" ++}; ++ ++static const char noe_string[] = NOE_DRV_STRING; ++ ++static const struct of_device_id mstar_noe_of_ids[] = { ++ {.compatible = NOE_COMPATIBLE_DEV_ID}, ++ {}, ++}; ++ ++static struct platform_driver mstar_noe_driver = { ++ .probe = MDrv_NOE_Probe, ++ .remove = MDrv_NOE_Remove, ++#ifdef CONFIG_PM ++ .resume = MDrv_NOE_Resume, ++ .suspend = MDrv_NOE_Suspend, ++#endif ++ .driver = { ++ .name = noe_string, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_noe_of_ids, ++ }, ++}; ++ ++ ++static inline MS_BOOL _MDrv_NOE_Is_IRQ0_Handler_Available(struct END_DEVICE *ei_local) ++{ ++ if ((ei_local->irq_num < E_NOE_IRQ_MAX) && (ei_local->features & FE_IRQ_SEPARATE)) { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++ ++/* Set the hardware MAC address. */ ++static int MDrv_NOE_Set_Mac_Addr(struct net_device *dev, void *p) ++{ ++ struct sockaddr *addr = p; ++ ++ if (!is_valid_ether_addr(addr->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++#ifndef CONFIG_NOE_NO_CHECK_ACTIVE_SETMAC ++ if (netif_running(dev)) ++ return -EBUSY; ++#endif ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ MHal_NOE_Set_MAC_Address(E_NOE_GE_MAC1, dev->dev_addr); ++ return 0; ++} ++ ++static int MDrv_NOE_Set_Mac2_Addr(struct net_device *dev, void *p) ++{ ++ struct sockaddr *addr = p; ++ ++ if (!is_valid_ether_addr(addr->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++#ifndef CONFIG_NOE_NO_CHECK_ACTIVE_SETMAC ++ if (netif_running(dev)) ++ return -EBUSY; ++#endif ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ MHal_NOE_Set_MAC_Address(E_NOE_GE_MAC2, dev->dev_addr); ++ return 0; ++} ++ ++#if NETDEV_LRO_SUPPORTED ++static int MDrv_NOE_Get_Skb_Header(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv) ++{ ++ struct iphdr *iph = NULL; ++ int vhdr_len = 0; ++ ++ /* Make sure that this packet is Ethernet II, is not VLAN ++ * tagged, is IPv4, has a valid IP header, and is TCP. ++ */ ++ if (skb->protocol == 0x0081) ++ vhdr_len = VLAN_HLEN; ++ ++ iph = (struct iphdr *)(skb->data + vhdr_len); ++ if (iph->daddr != lro_para.lan_ip1) ++ return -1; ++ if (iph->protocol != IPPROTO_TCP) ++ return -1; ++ ++ *iphdr = iph; ++ *tcph = skb->data + (iph->ihl << 2) + vhdr_len; ++ *hdr_flags = LRO_IPV4 | LRO_TCP; ++ ++ lro_flush_needed = 1; ++ return 0; ++} ++ ++static void MDrv_NOE_Init_Napi_Lro(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ ei_local->lro_mgr.dev = dev; ++ memset(&ei_local->lro_mgr.stats, 0, sizeof(ei_local->lro_mgr.stats)); ++ ei_local->lro_mgr.features = LRO_F_NAPI; ++ ei_local->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; ++ ei_local->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; ++ ei_local->lro_mgr.max_desc = ARRAY_SIZE(ei_local->lro_arr); ++ ei_local->lro_mgr.max_aggr = 64; ++ ei_local->lro_mgr.frag_align_pad = 0; ++ ei_local->lro_mgr.lro_arr = ei_local->lro_arr; ++ ei_local->lro_mgr.get_skb_header = MDrv_NOE_Get_Skb_Header; ++ lro_flush_needed = 0; ++} ++#endif /* NETDEV_LRO_SUPPORTED */ ++ ++static void MDrv_NOE_Reset_Statistics(struct END_DEVICE *ei_local) ++{ ++ ei_local->stat.tx_packets = 0; ++ ei_local->stat.tx_bytes = 0; ++ ei_local->stat.tx_dropped = 0; ++ ei_local->stat.tx_errors = 0; ++ ei_local->stat.tx_aborted_errors = 0; ++ ei_local->stat.tx_carrier_errors = 0; ++ ei_local->stat.tx_fifo_errors = 0; ++ ei_local->stat.tx_heartbeat_errors = 0; ++ ei_local->stat.tx_window_errors = 0; ++ ++ ei_local->stat.rx_packets = 0; ++ ei_local->stat.rx_bytes = 0; ++ ei_local->stat.rx_dropped = 0; ++ ei_local->stat.rx_errors = 0; ++ ei_local->stat.rx_length_errors = 0; ++ ei_local->stat.rx_over_errors = 0; ++ ei_local->stat.rx_crc_errors = 0; ++ ei_local->stat.rx_frame_errors = 0; ++ ei_local->stat.rx_fifo_errors = 0; ++ ei_local->stat.rx_missed_errors = 0; ++ ++ ei_local->stat.collisions = 0; ++} ++ ++static inline void MDrv_NOE_Init_Rx_Desc(struct PDMA_rxdesc *rx_ring, dma_addr_t dma_addr) ++{ ++ rx_ring->rxd_info1.PDP0 = dma_addr; ++ rx_ring->rxd_info2.PLEN0 = MAX_RX_LENGTH; ++ rx_ring->rxd_info2.LS0 = 0; ++ rx_ring->rxd_info2.DDONE_bit = 0; ++} ++ ++static int MDrv_NOE_Eth_Recv(struct net_device *dev, struct napi_struct *napi, int budget) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev); ++ struct sk_buff *rx_skb; ++ unsigned int length = 0; ++ int rx_processed = 0; ++ struct PDMA_rxdesc *rx_ring, *rx_ring_next; ++ unsigned int rx_dma_owner_idx, rx_next_idx; ++ void *rx_data, *rx_data_next, *new_data; ++ unsigned int skb_size; ++ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx = (ei_local->rx_calc_idx[0] + 1) % NUM_RX_DESC; ++#else ++ rx_dma_owner_idx = (MHal_NOE_DMA_Get_Calc_Idx(E_NOE_DIR_RX) + 1) % NUM_RX_DESC; ++#endif ++ rx_ring = &ei_local->rx_ring[0][rx_dma_owner_idx]; ++ rx_data = ei_local->netrx_skb_data[0][rx_dma_owner_idx]; ++ ++ skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ ++ for (;;) { ++ dma_addr_t dma_addr; ++ ++ if ((rx_processed++ > budget) || (rx_ring->rxd_info2.DDONE_bit == 0)) ++ break; ++ ++ rx_next_idx = (rx_dma_owner_idx + 1) % NUM_RX_DESC; ++ rx_ring_next = &ei_local->rx_ring[0][rx_next_idx]; ++ rx_data_next = ei_local->netrx_skb_data[0][rx_next_idx]; ++ prefetch(rx_ring_next); ++ ++ /* We have to check the free memory size is big enough ++ * before pass the packet to cpu ++ */ ++ new_data = MDrv_NOE_SkbData_Alloc(skb_size, GFP_ATOMIC); ++ ++ if (unlikely(!new_data)) { ++ NOE_MSG_ERR("skb not available...\n"); ++ goto skb_err; ++ } ++ ++ dma_addr = dma_map_single(dev->dev.parent, new_data + NET_SKB_PAD, MAX_RX_LENGTH, DMA_FROM_DEVICE); ++ ++ if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) { ++ NOE_MSG_ERR("[%s]dma_map_single() failed...\n", __func__); ++ MDrv_NOE_SkbData_Free(new_data); ++ goto skb_err; ++ } ++ ++ rx_skb = MDrv_NOE_Skb_Build(rx_data, skb_size); ++ ++ if (unlikely(!rx_skb)) { ++ put_page(virt_to_head_page(rx_data)); ++ NOE_MSG_ERR("build_skb failed\n"); ++ goto skb_err; ++ } ++ skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN); ++ ++ length = rx_ring->rxd_info2.PLEN0; ++ dma_unmap_single(dev->dev.parent, rx_ring->rxd_info1.PDP0, length, DMA_FROM_DEVICE); ++ ++ prefetch(rx_skb->data); ++ ++ /* skb processing */ ++ skb_put(rx_skb, length); ++ ++ /* rx packet from GE2 */ ++ if (rx_ring->rxd_info4.SP == 2) { ++ if (likely(ei_local->pseudo_dev)) { ++ rx_skb->dev = ei_local->pseudo_dev; ++ rx_skb->protocol = eth_type_trans(rx_skb, ei_local->pseudo_dev); ++ } else { ++ NOE_MSG_ERR("pseudo_dev is still not initialize "); ++ NOE_MSG_ERR("but receive packet from GMAC2\n"); ++ } ++ } else { ++ rx_skb->dev = dev; ++ rx_skb->protocol = eth_type_trans(rx_skb, dev); ++ } ++ ++ /* rx checksum offload */ ++ if (rx_ring->rxd_info4.L4VLD) ++ rx_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ else ++ rx_skb->ip_summed = CHECKSUM_NONE; ++ ++#ifdef CONFIG_NOE_NAT_HW ++ if (IS_VALID_NOE_HWNAT_HOOK_RX) { ++ *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) = *(uint32_t *)&rx_ring->rxd_info4; ++ *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) = *(uint32_t *)&rx_ring->rxd_info4; ++ FOE_ALG_HEAD(rx_skb) = 0; ++ FOE_ALG_TAIL(rx_skb) = 0; ++ FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE; ++ FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE; ++ FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT; ++ FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT; ++ } ++#endif ++ ++ MDrv_NOE_LOG_Dump_Skb(rx_skb); ++/* IS_VALID_NOE_HWNAT_HOOK_RX return 1 --> continue ++ * IS_VALID_NOE_HWNAT_HOOK_RX return 0 --> FWD & without netif_rx ++ */ ++#ifdef CONFIG_NOE_NAT_HW ++ if ((IS_NOT_VALID_NOE_HWNAT_HOOK_RX) || (IS_VALID_NOE_HWNAT_HOOK_RX && NOE_HWNAT_HOOK_RX(rx_skb))) { ++#endif ++ if (!(ei_local->features & FE_SW_LRO)) { ++ if (ei_local->features & FE_INT_NAPI) { ++ /* napi_gro_receive(napi, rx_skb); */ ++ netif_receive_skb(rx_skb); ++ } ++ else ++ netif_rx(rx_skb); ++ } ++ else { ++ if (IS_TRAFFIC_RECEIVED_OFFLOAD(rx_skb , napi)) { ++ TRAFFIC_RECEIVED_OFFLOAD(ei_local, napi, rx_skb); ++ } ++ else ++ { ++ if (ei_local->features & FE_INT_NAPI) ++ netif_receive_skb(rx_skb); ++ else ++ netif_rx(rx_skb); ++ } ++ } ++#ifdef CONFIG_NOE_NAT_HW ++ } ++#endif ++ ++ if (rx_ring->rxd_info4.SP == 2) { ++ p_ad->stat.rx_packets++; ++ p_ad->stat.rx_bytes += length; ++ } else { ++ ei_local->stat.rx_packets++; ++ ei_local->stat.rx_bytes += length; ++ } ++ ++ /* init RX desc. */ ++ MDrv_NOE_Init_Rx_Desc(rx_ring, dma_addr); ++ ei_local->netrx_skb_data[0][rx_dma_owner_idx] = new_data; ++ /* make sure that all changes to the dma ring are flushed before ++ * we continue ++ */ ++ wmb(); ++ ++ MHal_NOE_DMA_Update_Calc_Idx(E_NOE_DIR_RX, rx_dma_owner_idx); ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ ei_local->rx_calc_idx[0] = rx_dma_owner_idx; ++#endif ++ ++ /* Update to Next packet point that was received. ++ */ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx = rx_next_idx; ++#else ++ rx_dma_owner_idx = (MHal_NOE_DMA_Get_Calc_Idx(E_NOE_DIR_RX) + 1) % NUM_RX_DESC; ++#endif ++ ++ /* use prefetched variable */ ++ rx_ring = rx_ring_next; ++ rx_data = rx_data_next; ++ } /* for */ ++ ++ if (lro_flush_needed) { ++#if NETDEV_LRO_SUPPORTED ++ _MDrv_NOE_Flush_Lro_All(&ei_local->lro_mgr); ++#endif /* NETDEV_LRO_SUPPORTED */ ++ lro_flush_needed = 0; ++ } ++ ++ return rx_processed; ++ ++skb_err: ++ /* rx packet from GE2 */ ++ if (rx_ring->rxd_info4.SP == 2) ++ p_ad->stat.rx_dropped++; ++ else ++ ei_local->stat.rx_dropped++; ++ ++ /* Discard the rx packet */ ++ MDrv_NOE_Init_Rx_Desc(rx_ring, rx_ring->rxd_info1.PDP0); ++ ++ /* make sure that all changes to the dma ring ++ * are flushed before we continue ++ */ ++ wmb(); ++ ++ MHal_NOE_DMA_Update_Calc_Idx(E_NOE_DIR_RX, rx_dma_owner_idx); ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ ei_local->rx_calc_idx[0] = rx_dma_owner_idx; ++#endif ++ ++ return (budget + 1); ++} ++ ++static int MDrv_NOE_Full_Poll(struct napi_struct *napi, int budget) ++{ ++ struct END_DEVICE *ei_local = container_of(napi, struct END_DEVICE, napi); ++ struct net_device *netdev = ei_local->netdev; ++ //unsigned long reg_int_val_rx, reg_int_val_tx; ++ //unsigned long reg_int_mask_rx, reg_int_mask_tx; ++ unsigned long flags; ++ int tx_done = 0, rx_done = 0; ++ ++ if (MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_TX) == NOE_TRUE) { ++ tx_done = ei_local->ei_xmit_housekeeping(netdev, NUM_TX_MAX_PROCESS); ++ } ++ if (MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_RX) == NOE_TRUE) { ++ rx_done = ei_local->ei_eth_recv(netdev, napi, budget); ++ } ++ ++ if (rx_done >= budget) ++ return budget; ++ ++ napi_complete(napi); ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_TX); ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_RX); ++ MHal_NOE_Enable_Sep_Intr(E_NOE_DIR_TX); ++ MHal_NOE_Enable_Sep_Intr(E_NOE_DIR_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ return rx_done; ++} ++ ++static int MDrv_NOE_RX_Poll(struct napi_struct *napi, int budget) ++{ ++ struct END_DEVICE *ei_local = container_of(napi, struct END_DEVICE, napi_rx); ++ struct net_device *netdev = ei_local->netdev; ++ //unsigned long reg_int_val_rx; ++ //unsigned long reg_int_mask_rx; ++ unsigned long flags; ++ int rx_done = 0; ++ ++ if (MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_RX) == NOE_TRUE) { ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_RX); ++ rx_done = ei_local->ei_eth_recv(netdev, napi, budget); ++ } ++ ++ if (rx_done >= budget) ++ return budget; ++ ++ napi_complete(napi); ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ MHal_NOE_Enable_Sep_Intr(E_NOE_DIR_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ return rx_done; ++} ++ ++static int MDrv_NOE_TX_Poll(struct napi_struct *napi, int budget) ++{ ++ struct END_DEVICE *ei_local = ++ container_of(napi, struct END_DEVICE, napi_tx); ++ struct net_device *netdev = ei_local->netdev; ++ //unsigned long reg_int_val_tx; ++ //unsigned long reg_int_mask_tx; ++ unsigned long flags; ++ int tx_done = 0; ++ ++ if (MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_TX) == NOE_TRUE) { ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_TX); ++ tx_done = ei_local->ei_xmit_housekeeping(netdev, NUM_TX_MAX_PROCESS); ++ } ++ napi_complete(napi); ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ MHal_NOE_Enable_Sep_Intr(E_NOE_DIR_TX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ return 1; ++} ++ ++static void MDrv_NOE_Register_Func(struct END_DEVICE *ei_local) ++{ ++ /* TX handling */ ++ ++ if (ei_local->features & FE_QDMA_TX) { ++ ei_local->ei_start_xmit = MDrv_NOE_QDMA_Start_Xmit; ++ ei_local->ei_xmit_housekeeping = MDrv_NOE_QDMA_Xmit_Housekeeping; ++ MHal_NOE_Init_Sep_Intr(E_NOE_DMA_QUEUE, E_NOE_DIR_TX); ++ } ++ else { ++ ei_local->ei_start_xmit = MDrv_NOE_PDMA_Start_Xmit; ++ ei_local->ei_xmit_housekeeping = MDrv_NOE_PDMA_Xmit_Housekeeping; ++ MHal_NOE_Init_Sep_Intr(E_NOE_DMA_PACKET, E_NOE_DIR_TX); ++ } ++ ++ /* RX handling */ ++ if (ei_local->features & FE_QDMA_RX) { ++ MHal_NOE_Init_Sep_Intr(E_NOE_DMA_QUEUE, E_NOE_DIR_RX); ++ } else { ++ MHal_NOE_Init_Sep_Intr(E_NOE_DMA_PACKET, E_NOE_DIR_RX); ++ } ++ ++ /* HW LRO handling */ ++ if (ei_local->features & FE_HW_LRO) ++ ei_local->ei_eth_recv = MDrv_NOE_LRO_Recv; ++ else ++ ei_local->ei_eth_recv = MDrv_NOE_Eth_Recv; ++ ++ /* HW NAT handling */ ++ if (!(ei_local->features & FE_HW_NAT)) { ++#ifdef CONFIG_NOE_NAT_HW ++ NOE_HWNAT_HOOK_RX_INIT; ++ NOE_HWNAT_HOOK_TX_INIT; ++#endif ++ } ++} ++ ++static int __init MDrv_NOE_Init(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ MHal_NOE_Reset_FE(); ++ ++ if (ei_local->features & FE_INT_NAPI) { ++ /* we run 2 devices on the same DMA ring */ ++ /* so we need a dummy device for NAPI to work */ ++ init_dummy_netdev(&ei_local->dummy_dev); ++ ++ if (ei_local->features & FE_INT_NAPI_TX_RX) { ++ netif_napi_add(&ei_local->dummy_dev, &ei_local->napi_rx, MDrv_NOE_RX_Poll, NOE_NAPI_WEIGHT); ++ netif_napi_add(&ei_local->dummy_dev, &ei_local->napi_tx, MDrv_NOE_TX_Poll, NOE_NAPI_WEIGHT); ++ } ++ else if (ei_local->features & FE_INT_NAPI_RX_ONLY) { ++ netif_napi_add(&ei_local->dummy_dev, &ei_local->napi_rx, MDrv_NOE_RX_Poll, NOE_NAPI_WEIGHT); ++ } ++ else { ++ netif_napi_add(&ei_local->dummy_dev, &ei_local->napi, MDrv_NOE_Full_Poll, NOE_NAPI_WEIGHT); ++ } ++ } ++ ++ spin_lock_init(&ei_local->page_lock); ++ spin_lock_init(&ei_local->irq_lock); ++ ether_setup(dev); ++ ++#if NETDEV_LRO_SUPPORTED ++ if (ei_local->features & FE_SW_LRO) ++ MDrv_NOE_Init_Napi_Lro(dev); ++#endif /* NETDEV_LRO_SUPPORTED */ ++ ++ MDrv_NOE_Register_Func(ei_local); ++ ++ /* init my IP */ ++ strncpy(ei_local->lan_ip4_addr, FE_DEFAULT_LAN_IP, IP4_ADDR_LEN); ++ ++ return 0; ++} ++ ++static void MDrv_NOE_Uninit(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ unregister_netdev(dev); ++ free_netdev(dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ unregister_netdevice(ei_local->pseudo_dev); ++ free_netdev(ei_local->pseudo_dev); ++ } ++ ++ NOE_MSG_DBG("Free ei_local and unregister netdev...\n"); ++ ++ MDrv_NOE_PROC_Exit(); ++} ++ ++static void MDrv_NOE_Set_Mac(struct net_device *dev) ++{ ++ /* If the mac address is invalid, use random mac address */ ++ if (is_valid_ether_addr(mac_uboot)) ++ { ++ ether_addr_copy(dev->dev_addr, mac_uboot); ++ NOE_MSG_ERR("Get MAC address from u-boot\n"); ++ }else ++ if (!is_valid_ether_addr(dev->dev_addr)) { ++ random_ether_addr(dev->dev_addr); ++ NOE_MSG_DBG("generated random MAC address %pM\n", dev->dev_addr); ++ dev->addr_assign_type = NET_ADDR_RANDOM; ++ } ++ NOE_MSG_DBG("MAC address %pM\n", dev->dev_addr); ++ MHal_NOE_Set_MAC_Address(E_NOE_GE_MAC1, dev->dev_addr); ++} ++ ++static void MDrv_NOE_Set_Mac2(struct net_device *dev) ++{ ++ if (is_valid_ether_addr(mac1_uboot)) ++ { ++ ether_addr_copy(dev->dev_addr, mac1_uboot); ++ NOE_MSG_ERR("Get MAC address from u-boot\n"); ++ ++ }else ++ /* If the mac address is invalid, use random mac address */ ++ if (!is_valid_ether_addr(dev->dev_addr)) { ++ random_ether_addr(dev->dev_addr); ++ NOE_MSG_DBG("generated random MAC address %pM\n", dev->dev_addr); ++ dev->addr_assign_type = NET_ADDR_RANDOM; ++ } ++ NOE_MSG_DBG("MAC2 address %pM\n", dev->dev_addr); ++ MHal_NOE_Set_MAC_Address(E_NOE_GE_MAC2, dev->dev_addr); ++} ++ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++static void MDrv_NOE_Init_Rx_Cal_Idx(struct END_DEVICE *ei_local) ++{ ++ struct noe_lro_calc_idx calc_idx; ++ ei_local->rx_calc_idx[0] = MHal_NOE_DMA_Get_Calc_Idx(E_NOE_DIR_RX); ++ if (ei_local->features & FE_HW_LRO) { ++ MHal_NOE_LRO_Get_Calc_Idx(&calc_idx); ++ ei_local->rx_calc_idx[1] = calc_idx.ring1; ++ ei_local->rx_calc_idx[2] = calc_idx.ring2; ++ ei_local->rx_calc_idx[3] = calc_idx.ring3; ++ } ++} ++#endif ++ ++static inline int MDrv_NOE_Init_Txp_Rxp(struct net_device *dev) ++{ ++ int err; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (MHal_NOE_Dma_Is_Idle(E_NOE_DMA_PACKET) != E_NOE_RET_TRUE) ++ return -1; ++ ++ err = MDrv_NOE_PDMA_Init_Rx(dev); ++ if (err) ++ return err; ++ ++ if (ei_local->features & FE_HW_LRO) { ++ err = MDrv_NOE_LRO_Init(dev); ++ if (err) ++ return err; ++ } ++ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ MDrv_NOE_Init_Rx_Cal_Idx(ei_local); ++#endif ++ ++ err = MDrv_NOE_PDMA_Init_Tx(dev); ++ if (err) ++ return err; ++ ++ MHal_NOE_Dma_Init_Global_Config(E_NOE_DMA_PACKET); ++ ++ /* enable RXD prefetch of ADMA */ ++ MHal_NOE_LRO_Set_Prefetch(); ++ return 0; ++} ++ ++static inline int MDrv_NOE_Init_Txq_Rxp(struct net_device *dev) ++{ ++ int err; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (MHal_NOE_Dma_Is_Idle(E_NOE_DMA_PACKET) != E_NOE_RET_TRUE) { ++ NOE_MSG_DBG("PDMA is busy!\n"); ++ return -1; ++ } ++ ++ if (MHal_NOE_Dma_Is_Idle(E_NOE_DMA_QUEUE) != E_NOE_RET_TRUE) { ++ NOE_MSG_DBG("QDMA is busy!\n"); ++ return -1; ++ } ++ NOE_MSG_DBG("[%s][%d] feature = 0x%x \n", __FUNCTION__, __LINE__, ei_local->features); ++ err = MDrv_NOE_QDMA_Init_Rx(dev); ++ if (err) ++ return err; ++ ++ err = MDrv_NOE_PDMA_Init_Rx(dev); ++ if (err) ++ return err; ++ ++ if (ei_local->features & FE_HW_LRO) { ++ err = MDrv_NOE_LRO_Init(dev); ++ if (err) ++ return err; ++ } ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ MDrv_NOE_Init_Rx_Cal_Idx(ei_local); ++#endif ++ ++ err = MDrv_NOE_QDMA_Init_Tx(dev); ++ if (err) ++ return err; ++ ++ MHal_NOE_Dma_Init_Global_Config(E_NOE_DMA_PACKET); ++ MHal_NOE_Dma_Init_Global_Config((ei_local->features & FE_HW_SFQ)? E_NOE_DMA_QUEUE_WITH_SFQ :E_NOE_DMA_QUEUE); ++ ++ /* enable RXD prefetch of ADMA */ ++ MHal_NOE_LRO_Set_Prefetch(); ++ return 0; ++} ++ ++static inline int MDrv_NOE_Init_Txq_Rxq(struct net_device *dev) ++{ ++ int err; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ ++ if (MHal_NOE_Dma_Is_Idle(E_NOE_DMA_QUEUE) != E_NOE_RET_TRUE) ++ return -1; ++ ++ err = MDrv_NOE_QDMA_Init_Rx(dev); ++ if (err) ++ return err; ++ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ MDrv_NOE_Init_Rx_Cal_Idx(ei_local); ++#endif ++ ++ err = MDrv_NOE_QDMA_Init_Tx(dev); ++ if (err) ++ return err; ++ ++ MHal_NOE_Dma_Init_Global_Config((ei_local->features & FE_HW_SFQ)? E_NOE_DMA_QUEUE_WITH_SFQ :E_NOE_DMA_QUEUE); ++ ++ return 0; ++} ++ ++static int MDrv_NOE_Init_Dma(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if ((ei_local->features & FE_QDMA_TX) && (ei_local->features & FE_QDMA_RX)) { ++ return MDrv_NOE_Init_Txq_Rxq(dev); ++ } ++ ++ if (ei_local->features & FE_QDMA_TX) { ++ return MDrv_NOE_Init_Txq_Rxp(dev); ++ } ++ else { ++ return MDrv_NOE_Init_Txp_Rxp(dev); ++ } ++} ++ ++static void MDrv_NOE_Deinit_Dma(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (ei_local->features & FE_QDMA_TX) ++ MDrv_NOE_QDMA_Deinit_Tx(dev); ++ else ++ MDrv_NOE_PDMA_Deinit_Tx(dev); ++ ++ if (!(ei_local->features & FE_QDMA_RX)) ++ MDrv_NOE_PDMA_Deinit_Rx(dev); ++#ifdef CONFIG_NOE_QDMA ++ MDrv_NOE_QDMA_Deinit_Rx(dev); ++#endif ++ if (ei_local->features & FE_HW_LRO) ++ MDrv_NOE_LRO_Deinit(dev); ++ ++ NOE_MSG_DBG("Free TX/RX Ring Memory!\n"); ++} ++ ++static int MDrv_NOE_Reset_Thread(void *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ unsigned long flags; ++ for (;;) { ++ ei_local->fe_reset_times++; ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++ MHal_NOE_Do_Reset(); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ ++ msleep(FE_RESET_POLLING_MS); ++ if (kthread_should_stop()) ++ break; ++ } ++ return 0; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_RxOnly_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long flags; ++ ++ ++ if (likely(napi_schedule_prep(&ei_local->napi_rx))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ /* Clear RX interrupt status */ ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_RX); ++ ++ /* Disable RX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_RX); ++ ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ __napi_schedule(&ei_local->napi_rx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long flags; ++ ++ MDrv_NOE_MAC_Detect_Link_Status(dev); ++ ++ if (likely(napi_schedule_prep(&ei_local->napi))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Disable TX/RX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_BOTH); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ __napi_schedule(&ei_local->napi); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_Separate_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ //unsigned int reg_int_mask; ++ unsigned long flags; ++ ++ MDrv_NOE_MAC_Detect_Link_Status(dev); ++ ++ if (likely(napi_schedule_prep(&ei_local->napi_tx))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Disable TX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_TX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ __napi_schedule(&ei_local->napi_tx); ++ } ++ ++ if (likely(napi_schedule_prep(&ei_local->napi_rx))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Disable RX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ __napi_schedule(&ei_local->napi_rx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_Interrupt(int irq, void *dev_id) ++{ ++ unsigned int recv = 0; ++ ++ unsigned int transmit __maybe_unused = 0; ++ unsigned long flags; ++ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (!dev) { ++ NOE_MSG_ERR("net_interrupt(): irq for unknown device.\n"); ++ return IRQ_NONE; ++ } ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ MHal_NOE_Get_Intr_Status((ei_local->features & FE_QDMA)?(E_NOE_DMA_PACKET|E_NOE_DMA_QUEUE):E_NOE_DMA_PACKET, &recv, &transmit); ++ ei_local->ei_xmit_housekeeping(dev, NUM_TX_MAX_PROCESS); ++ MHal_NOE_Clear_Intr_Status((ei_local->features & FE_QDMA)?(E_NOE_DMA_PACKET|E_NOE_DMA_QUEUE):E_NOE_DMA_PACKET); ++ ++ ++ if (((recv == 1) || (pending_recv == 1)) && (ei_local->tx_ring_full == 0)) { ++ MHal_NOE_Enable_Intr_Status(E_NOE_DMA_PACKET); ++ pending_recv = 0; ++ ++ if (ei_local->features & FE_INT_WORKQ) ++ schedule_work(&ei_local->rx_wq); ++ else ++ tasklet_hi_schedule(&ei_local->rx_tasklet); ++ } ++ else if (recv == 1 && ei_local->tx_ring_full == 1) { ++ pending_recv = 1; ++ } ++ else if ((recv == 0) && (transmit == 0)) { ++ MDrv_NOE_MAC_Detect_Link_Status(dev); ++ } ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_RX_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *netdev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local; ++ unsigned long flags; ++ ++ if (unlikely(!netdev)) { ++ NOE_MSG_ERR("net_interrupt(): irq %x for unknown device.\n", irq); ++ return IRQ_NONE; ++ } ++ ei_local = netdev_priv(netdev); ++ ++ if (likely(MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_RX) == NOE_TRUE)) { ++ if (likely(napi_schedule_prep(&ei_local->napi))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Disable RX/TX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_BOTH); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ __napi_schedule(&ei_local->napi); ++ } ++ } ++ else { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Ack other interrupt status except TX irqs */ ++ MHal_NOE_Clear_Sep_Intr_Specific_Status(E_NOE_DIR_RX, E_NOE_INTR_CLR_EXCEPT_TX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_Separate_RX_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *netdev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local; ++ unsigned long flags; ++ ++ if (unlikely(!netdev)) { ++ NOE_MSG_ERR("%s: irq %x for unknown device.\n", __FUNCTION__, irq); ++ return IRQ_NONE; ++ } ++ ei_local = netdev_priv(netdev); ++ if (likely(MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_RX) == NOE_TRUE )) { ++ if (likely(napi_schedule_prep(&ei_local->napi_rx))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Clear RX interrupt status */ ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_RX); ++ /* Clear RX interrupt status */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ __napi_schedule(&ei_local->napi_rx); ++ } ++ } else { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Ack other interrupt status except TX irqs */ ++ MHal_NOE_Clear_Sep_Intr_Specific_Status(E_NOE_DIR_RX, E_NOE_INTR_CLR_EXCEPT_TX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_RX_Interrupt(int irq, void *dev_id) ++{ ++ unsigned int recv = 0; ++ unsigned long flags; ++ ++ struct net_device *netdev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local; ++ ++ if (unlikely(!netdev)) { ++ NOE_MSG_ERR("%s: irq %x for unknown device.\n", __FUNCTION__, irq); ++ return IRQ_NONE; ++ } ++ ei_local = netdev_priv(netdev); ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ if (MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_RX) == NOE_TRUE) ++ recv = 1; ++ ++ /* Clear RX interrupt status */ ++ MHal_NOE_Clear_Sep_Intr_Status(E_NOE_DIR_RX); ++ ++ if (likely(((recv == 1) || (pending_recv == 1)) && (ei_local->tx_ring_full == 0))) { ++ /* Disable RX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_RX); ++ pending_recv = 0; ++ ++ if (likely(ei_local->features & FE_INT_TASKLET)) ++ tasklet_hi_schedule(&ei_local->rx_tasklet); ++ else ++ schedule_work(&ei_local->rx_wq); ++ } ++ else if (recv == 1 && ei_local->tx_ring_full == 1) { ++ pending_recv = 1; ++ } ++ else if ((recv == 0)) { ++ MDrv_NOE_MAC_Detect_Link_Status(netdev); ++ } ++ ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_TX_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *netdev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local; ++ unsigned long flags; ++ ++ if (unlikely(!netdev)) { ++ NOE_MSG_ERR("%s: irq %x for unknown device.\n", __FUNCTION__, irq); ++ return IRQ_NONE; ++ } ++ ++ MDrv_NOE_MAC_Detect_Link_Status(netdev); ++ ei_local = netdev_priv(netdev); ++ if (likely(MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_TX) == NOE_TRUE)) { ++ if (likely(napi_schedule_prep(&ei_local->napi))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_BOTH); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ __napi_schedule(&ei_local->napi); ++ } ++ } ++ else { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Ack other interrupt status except RX irqs */ ++ MHal_NOE_Clear_Sep_Intr_Specific_Status(E_NOE_DIR_TX, E_NOE_INTR_CLR_EXCEPT_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_NAPI_Separate_TX_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *netdev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local; ++ unsigned long flags; ++ ++ if (unlikely(!netdev)) { ++ NOE_MSG_ERR("%s: irq %x for unknown device.\n", __FUNCTION__, irq); ++ return IRQ_NONE; ++ } ++ ei_local = netdev_priv(netdev); ++ ++ if (likely(MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_TX) == NOE_TRUE)) { ++ if (likely(napi_schedule_prep(&ei_local->napi_tx))) { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ /* Disable TX interrupt */ ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_TX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ __napi_schedule(&ei_local->napi_tx); ++ } ++ } else { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ /* Ack other interrupt status except RX irqs */ ++ MHal_NOE_Clear_Sep_Intr_Specific_Status(E_NOE_DIR_TX, E_NOE_INTR_CLR_EXCEPT_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t MDrv_NOE_TX_Interrupt(int irq, void *dev_id) ++{ ++ struct net_device *netdev = (struct net_device *)dev_id; ++ struct END_DEVICE *ei_local; ++ unsigned long flags; ++ ++ if (unlikely(!netdev)) { ++ NOE_MSG_ERR("%s: irq %x for unknown device.\n", __FUNCTION__, irq); ++ return IRQ_NONE; ++ } ++ ++ ei_local = netdev_priv(netdev); ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ ++ if (likely(MHal_NOE_Get_Sep_Intr_Status(E_NOE_DIR_TX) == NOE_TRUE)) { ++ MHal_NOE_Disable_Sep_Intr(E_NOE_DIR_TX); ++ ei_local->ei_xmit_housekeeping(netdev, NUM_TX_MAX_PROCESS); ++ /* Enable TX interrupt */ ++ MHal_NOE_Enable_Sep_Intr(E_NOE_DIR_TX); ++ } ++ /* Ack other interrupt status except RX irqs */ ++ MHal_NOE_Clear_Sep_Intr_Specific_Status(E_NOE_DIR_TX, E_NOE_INTR_CLR_EXCEPT_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static inline void MDrv_NOE_Recv(void) ++{ ++ struct net_device *dev = g_dev_noe; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int rx_processed; ++ unsigned long flags; ++ ++ if (ei_local->tx_ring_full == 0) { ++ rx_processed = ei_local->ei_eth_recv(dev, NULL, NUM_RX_MAX_PROCESS); ++ if (rx_processed > NUM_RX_MAX_PROCESS) { ++ if (likely(ei_local->features & FE_INT_TASKLET)) ++ tasklet_hi_schedule(&ei_local->rx_tasklet); ++ else ++ schedule_work(&ei_local->rx_wq); ++ } else { ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ /* Enable RX interrupt */ ++ MHal_NOE_Enable_Sep_Intr(E_NOE_DIR_RX); ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ } ++ } else { ++ if (likely(ei_local->features & FE_INT_TASKLET)) ++ tasklet_schedule(&ei_local->rx_tasklet); ++ else ++ schedule_work(&ei_local->rx_wq); ++ } ++} ++ ++static void MDrv_NOE_Tasklet_Recv(unsigned long unused) ++{ ++ MDrv_NOE_Recv(); ++} ++ ++static void MDrv_NOE_Workq_Recv(struct work_struct *work) ++{ ++ MDrv_NOE_Recv(); ++} ++ ++static int MDrv_NOE_Enable_Intr(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int err0 = 0, err1 = 0, err2 = 0; ++ unsigned long flags; ++ ++ if (ei_local->irq_attached == TRUE) ++ return 0; ++ ++ if (_MDrv_NOE_Is_IRQ0_Handler_Available(ei_local)) { ++ if (ei_local->features & FE_INT_NAPI) ++ if (ei_local->features & FE_INT_NAPI_TX_RX) ++ err0 = request_irq(ei_local->irq0, MDrv_NOE_NAPI_Separate_Interrupt, IRQF_TRIGGER_HIGH, dev->name, dev); ++ else if (ei_local->features & FE_INT_NAPI_RX_ONLY) ++ err0 = request_irq(ei_local->irq0, MDrv_NOE_NAPI_RxOnly_Interrupt, IRQF_TRIGGER_HIGH, dev->name, dev); ++ else ++ err0 = request_irq(ei_local->irq0, MDrv_NOE_NAPI_Interrupt, IRQF_TRIGGER_HIGH, dev->name, dev); ++ else ++ err0 = request_irq(ei_local->irq0, MDrv_NOE_Interrupt, IRQF_TRIGGER_HIGH, dev->name, dev); ++ ++#if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) ++ irq_set_affinity_hint(ei_local->irq0, cpu_online_mask); ++ irq_set_affinity(ei_local->irq0, cpu_online_mask); ++#endif ++ } ++ ++ if (ei_local->features & FE_IRQ_SEPARATE) { ++ if (ei_local->features & FE_INT_NAPI) { ++ if (ei_local->features & FE_INT_NAPI_TX_RX) { ++ NOE_MSG_DBG("TX/RX NAPI Sep\n"); ++ err1 = request_irq(ei_local->irq1, MDrv_NOE_NAPI_Separate_TX_Interrupt, IRQF_TRIGGER_HIGH, "eth_tx", dev); ++ err2 = request_irq(ei_local->irq2, MDrv_NOE_NAPI_Separate_RX_Interrupt, IRQF_TRIGGER_HIGH, "eth_rx", dev); ++ } ++ else if (ei_local->features & FE_INT_NAPI_RX_ONLY) { ++ NOE_MSG_DBG("RX NAPI\n"); ++ err1 = request_irq(ei_local->irq1, MDrv_NOE_TX_Interrupt, IRQF_TRIGGER_HIGH, "eth_tx", dev); ++ err2 = request_irq(ei_local->irq2, MDrv_NOE_NAPI_Separate_RX_Interrupt, IRQF_TRIGGER_HIGH, "eth_rx", dev); ++ } ++ else { ++ NOE_MSG_DBG("TX/RX NAPI\n"); ++ err1 = request_irq(ei_local->irq1, MDrv_NOE_NAPI_TX_Interrupt, IRQF_TRIGGER_HIGH, "eth_tx", dev); ++ err2 = request_irq(ei_local->irq2, MDrv_NOE_NAPI_RX_Interrupt, IRQF_TRIGGER_HIGH, "eth_rx", dev); ++ } ++ } ++ else { ++ err1 = request_irq(ei_local->irq1, MDrv_NOE_TX_Interrupt, IRQF_TRIGGER_HIGH, "eth_tx", dev); ++ err2 = request_irq(ei_local->irq2, MDrv_NOE_RX_Interrupt, IRQF_TRIGGER_HIGH, "eth_rx", dev); ++ } ++#if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) ++ irq_set_affinity_hint(ei_local->irq1, cpu_online_mask); ++ irq_set_affinity_hint(ei_local->irq2, cpu_online_mask); ++ irq_set_affinity(ei_local->irq1, cpu_online_mask); ++ irq_set_affinity(ei_local->irq2, cpu_online_mask); ++#endif ++ ++ } ++ ++ if (err0 | err1 | err2) { ++ NOE_MSG_ERR("Fail to request irq. %d, %d, %d\n", err0, err1, err2); ++ return (err0 | err1 | err2); ++ } ++ MHal_NOE_Enable_Link_Intr(); ++ ++ spin_lock_irqsave(&ei_local->irq_lock, flags); ++ ++ MHal_NOE_Set_Intr_Mask((ei_local->features & FE_DLY_INT)?E_NOE_DLY_ENABLE:E_NOE_DLY_DISABLE); ++ ++ /* Enable PDMA interrupts */ ++ if (ei_local->features & FE_DLY_INT) ++ MHal_NOE_Enable_Sep_Delay_Intr(E_NOE_DMA_PACKET, E_NOE_DLY_ENABLE); ++ else ++ MHal_NOE_Enable_Sep_Delay_Intr(E_NOE_DMA_PACKET, E_NOE_DLY_DISABLE); ++ ++ if (ei_local->features & FE_QDMA) { ++ /* Enable QDMA interrupts */ ++ if ((ei_local->features & FE_DLY_INT) || (ei_local->features & FE_INT_NAPI_RX_ONLY)) ++ MHal_NOE_Enable_Sep_Delay_Intr(E_NOE_DMA_QUEUE, E_NOE_DLY_ENABLE); ++ else ++ MHal_NOE_Enable_Sep_Delay_Intr(E_NOE_DMA_QUEUE, E_NOE_DLY_DISABLE); ++ } ++ ++ /* IRQ separation settings */ ++ if (ei_local->features & FE_IRQ_SEPARATE) { ++ if (ei_local->features & FE_DLY_INT) ++ MHal_NOE_Set_Grp_Intr(NOE_TRUE, (ei_local->features & FE_INT_NAPI_RX_ONLY)?TRUE:FALSE); ++ else ++ MHal_NOE_Set_Grp_Intr(NOE_FALSE, FALSE); ++ } ++ ++ if (ei_local->features & FE_INT_TASKLET) { ++ tasklet_init(&ei_local->rx_tasklet, MDrv_NOE_Tasklet_Recv, 0); ++ } ++ else if (ei_local->features & FE_INT_WORKQ) { ++ INIT_WORK(&ei_local->rx_wq, MDrv_NOE_Workq_Recv); ++ } ++ else { ++ if (ei_local->features & FE_INT_NAPI_TX_RX) { ++ napi_enable(&ei_local->napi_tx); ++ napi_enable(&ei_local->napi_rx); ++ } ++ else if (ei_local->features & FE_INT_NAPI_RX_ONLY) { ++ napi_enable(&ei_local->napi_rx); ++ } ++ else { ++ napi_enable(&ei_local->napi); ++ } ++ } ++ ++ ei_local->irq_attached = TRUE; ++ spin_unlock_irqrestore(&ei_local->irq_lock, flags); ++ return 0; ++} ++ ++static int MDrv_NOE_Disable_Intr(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (ei_local->irq_attached == FALSE) ++ return 0; ++ ++ if (_MDrv_NOE_Is_IRQ0_Handler_Available(ei_local)) { ++ #if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) ++ irq_set_affinity_hint(ei_local->irq0, NULL); ++ #endif ++ free_irq(ei_local->irq0, dev); ++ } ++ ++ if (ei_local->features & FE_IRQ_SEPARATE) { ++ #if defined(CONFIG_MP_PLATFORM_GIC_SET_MULTIPLE_CPUS) ++ irq_set_affinity_hint(ei_local->irq1, NULL); ++ irq_set_affinity_hint(ei_local->irq2, NULL); ++ #endif ++ free_irq(ei_local->irq1, dev); ++ free_irq(ei_local->irq2, dev); ++ } ++ ++ cancel_work_sync(&ei_local->reset_task); ++ ++ if (ei_local->features & FE_INT_WORKQ) ++ cancel_work_sync(&ei_local->rx_wq); ++ else if (ei_local->features & FE_INT_TASKLET) ++ tasklet_kill(&ei_local->rx_tasklet); ++ if (ei_local->features & FE_INT_NAPI) { ++ if (ei_local->features & FE_INT_NAPI_TX_RX) { ++ napi_disable(&ei_local->napi_tx); ++ napi_disable(&ei_local->napi_rx); ++ } ++ else if (ei_local->features & FE_INT_NAPI_RX_ONLY) { ++ napi_disable(&ei_local->napi_rx); ++ } ++ else { ++ napi_disable(&ei_local->napi); ++ } ++ } ++ ++ ei_local->irq_attached = FALSE; ++ return 0; ++} ++ ++int MDrv_NOE_Set_Forward_Cfg(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (ei_local->features & FE_HW_VLAN_TX) { ++ MHal_NOE_Set_Vlan_Info(); ++ } ++ ++ MHal_NOE_Offoad_Checksum(E_NOE_GE_MAC1, (ei_local->features & FE_CSUM_OFFLOAD)?NOE_ENABLE:NOE_DISABLE); ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ MHal_NOE_Offoad_Checksum(E_NOE_GE_MAC2, (ei_local->features & FE_CSUM_OFFLOAD)?NOE_ENABLE:NOE_DISABLE); ++ } ++ ++ if (ei_local->features & FE_HW_VLAN_TX) ++ dev->features |= NETIF_F_HW_VLAN_CTAG_TX; ++ ++ if (ei_local->features & FE_HW_VLAN_RX) ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX; ++ ++ if (ei_local->features & FE_CSUM_OFFLOAD) { ++ if (ei_local->features & FE_HW_LRO) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ /* Can checksum TCP/UDP over IPv4 */ ++ dev->features |= NETIF_F_IP_CSUM; ++ if (ei_local->features & FE_TSO) { ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_TSO; ++#ifdef CONFIG_HIGHMEM /* To avoid doing __skb_linearize */ ++ dev->features |=NETIF_F_HIGHDMA; ++#endif ++ } ++ ++ if (ei_local->features & FE_TSO_V6) { ++ dev->features |= NETIF_F_TSO6; ++ /* Can checksum TCP/UDP over IPv6 */ ++ dev->features |= NETIF_F_IPV6_CSUM; ++ } ++ } ++ else { ++ /* disable checksum TCP/UDP over IPv4 */ ++ dev->features &= ~NETIF_F_IP_CSUM; ++ } ++ ++ dev->vlan_features = dev->features; ++ ++ MHal_NOE_GLO_Reset(); ++ ++ return 1; ++} ++ ++ ++ ++void virtif_setup_statistics(struct PSEUDO_ADAPTER *p_ad) ++{ ++ p_ad->stat.tx_packets = 0; ++ p_ad->stat.tx_bytes = 0; ++ p_ad->stat.tx_dropped = 0; ++ p_ad->stat.tx_errors = 0; ++ p_ad->stat.tx_aborted_errors = 0; ++ p_ad->stat.tx_carrier_errors = 0; ++ p_ad->stat.tx_fifo_errors = 0; ++ p_ad->stat.tx_heartbeat_errors = 0; ++ p_ad->stat.tx_window_errors = 0; ++ ++ p_ad->stat.rx_packets = 0; ++ p_ad->stat.rx_bytes = 0; ++ p_ad->stat.rx_dropped = 0; ++ p_ad->stat.rx_errors = 0; ++ p_ad->stat.rx_length_errors = 0; ++ p_ad->stat.rx_over_errors = 0; ++ p_ad->stat.rx_crc_errors = 0; ++ p_ad->stat.rx_frame_errors = 0; ++ p_ad->stat.rx_fifo_errors = 0; ++ p_ad->stat.rx_missed_errors = 0; ++ ++ p_ad->stat.collisions = 0; ++} ++ ++int MDrv_NOE_Virtif_Open(struct net_device *dev) ++{ ++ struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev); ++ ++ NOE_MSG_DBG("open %s\n", dev->name); ++ ++ virtif_setup_statistics(p_pseudo_ad); ++ ++ netif_start_queue(p_pseudo_ad->pseudo_dev); ++ ++ return 0; ++} ++ ++int MDrv_NOE_Virtif_Close(struct net_device *dev) ++{ ++ struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev); ++ ++ NOE_MSG_DBG("%s: ===> MDrv_NOE_Virtif_Close\n", dev->name); ++ ++ netif_stop_queue(p_pseudo_ad->pseudo_dev); ++ ++ return 0; ++} ++ ++int MDrv_NOE_Virtif_Start_Xmit(struct sk_buff *p_skb, struct net_device *dev) ++{ ++ struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev); ++ struct END_DEVICE *ei_local; ++ ++ if (!(p_pseudo_ad->primary_dev->flags & IFF_UP)) { ++ NOE_MSG_ERR("primary dev is not up!\n"); ++ dev_kfree_skb_any(p_skb); ++ return 0; ++ } ++ /* p_skb->cb[40]=0x5a; */ ++ p_skb->dev = p_pseudo_ad->primary_dev; ++ ei_local = netdev_priv(p_pseudo_ad->primary_dev); ++ ei_local->ei_start_xmit(p_skb, p_pseudo_ad->primary_dev, 2); ++ return 0; ++} ++ ++struct net_device_stats *MDrv_NOE_Virtif_Get_Stats(struct net_device *dev) ++{ ++ struct PSEUDO_ADAPTER *p_ad = netdev_priv(dev); ++ ++ return &p_ad->stat; ++} ++ ++int MDrv_NOE_Virtif_Ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) ++{ ++ struct ra_mii_ioctl_data mii; ++ unsigned long ret; ++ ++ switch (cmd) { ++ case NOE_MII_READ: ++ ret = copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ MHal_NOE_Read_Mii_Mgr(mii.phy_id, mii.reg_num, &mii.val_out); ++ ret = copy_to_user(ifr->ifr_data, &mii, sizeof(mii)); ++ break; ++ ++ case NOE_MII_WRITE: ++ ret = copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ MHal_NOE_Write_Mii_Mgr(mii.phy_id, mii.reg_num, mii.val_in); ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static int MDrv_NOE_Change_Mtu(struct net_device *dev, int new_mtu) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (!ei_local) { ++ pr_emerg("%s: %s passed a non-existent private pointer from net_dev!\n", dev->name, __func__); ++ return -ENXIO; ++ } ++ ++ if ((new_mtu > 4096) || (new_mtu < 64)) ++ return -EINVAL; ++ ++ if (new_mtu > 1500) ++ return -EINVAL; ++ ++ dev->mtu = new_mtu; ++ ++ return 0; ++} ++ ++static void _MDrv_NOE_Enable(struct END_DEVICE *ei_local) ++{ ++ ++ struct noe_sys sys_info; ++ /* Set sysctl addr base */ ++ if (netif_running(ei_local->netdev)) { ++ MHal_NOE_Init(NULL); ++ } ++ else { ++ sys_info.sysctl_base = (void __iomem *)(ei_local->netdev->base_addr ); ++ MHal_NOE_Init(&sys_info); ++ } ++ //backup MAC address which uboot set before software reset ++ MHal_NOE_Get_MAC_Address(E_NOE_GE_MAC1, mac_uboot); ++ MHal_NOE_Get_MAC_Address(E_NOE_GE_MAC2, mac1_uboot); ++ ++ MHal_NOE_Reset_SW(); ++ ++ /* Set Pin Mux */ ++ MHal_NOE_Set_Pin_Mux(ei_local->pin_mux); ++ ++ MDrv_NOE_Enable_Clock(ei_local); ++ ++ MDrv_NOE_Set_Io_Coherence(ei_local); ++ ++ MDrv_NOE_Set_Mac(ei_local->netdev); ++} ++ ++static int MDrv_NOE_Enable_Clock(struct END_DEVICE *ei_local) ++{ ++#ifndef CONFIG_MSTAR_ARM_BD_FPGA ++ ++#endif ++ return 0; ++} ++ ++static int MDrv_NOE_Disable_Clock(struct END_DEVICE *ei_local) ++{ ++#ifndef CONFIG_MSTAR_ARM_BD_FPGA ++#endif ++ return 0; ++} ++ ++static struct ethtool_ops mdrv_noe_ethtool_ops = { ++ .set_settings = MDrv_NOE_ETHTOOL_Set_Settings, ++ .get_settings = MDrv_NOE_ETHTOOL_Get_Settings, ++ .get_link = MDrv_NOE_ETHTOOL_Get_Link, ++}; ++ ++static struct ethtool_ops mdrv_noe_virt_ethtool_ops = { ++ .set_settings = MDrv_NOE_ETHTOOL_Virt_Set_Settings, ++ .get_settings = MDrv_NOE_ETHTOOL_Virt_Get_Settings, ++ .get_link = MDrv_NOE_ETHTOOL_Virt_Get_Link, ++}; ++ ++static const struct net_device_ops virtualif_netdev_ops = { ++ .ndo_open = MDrv_NOE_Virtif_Open, ++ .ndo_stop = MDrv_NOE_Virtif_Close, ++ .ndo_start_xmit = MDrv_NOE_Virtif_Start_Xmit, ++ .ndo_get_stats = MDrv_NOE_Virtif_Get_Stats, ++ .ndo_set_mac_address = MDrv_NOE_Set_Mac2_Addr, ++ .ndo_change_mtu = MDrv_NOE_Change_Mtu, ++ .ndo_do_ioctl = MDrv_NOE_Virtif_Ioctl, ++ .ndo_validate_addr = eth_validate_addr, ++}; ++ ++void MDrv_NOE_Virtif_Init(struct END_DEVICE *p_ad, struct net_device *net_dev) ++{ ++ int index; ++ struct net_device *dev; ++ struct PSEUDO_ADAPTER *p_pseudo_ad; ++ struct END_DEVICE *ei_local = netdev_priv(net_dev); ++ ++ ++ for (index = 0; index < MAX_PSEUDO_ENTRY; index++) { ++ dev = alloc_etherdev_mqs(sizeof(struct PSEUDO_ADAPTER), GMAC2_TXQ_NUM, 1); ++ netif_carrier_off(dev); ++ if (!dev) { ++ NOE_MSG_ERR("alloc_etherdev for PSEUDO_ADAPTER failed.\n"); ++ return; ++ } ++ ++ netif_set_real_num_tx_queues(dev, GMAC2_TXQ_NUM); ++ netif_set_real_num_rx_queues(dev, 1); ++ ++ MDrv_NOE_Set_Mac2(dev); ++ ++ ether_setup(dev); ++ p_pseudo_ad = netdev_priv(dev); ++ ++ p_pseudo_ad->pseudo_dev = dev; ++ p_pseudo_ad->primary_dev = net_dev; ++ p_ad->pseudo_dev = dev; ++ ++ dev->netdev_ops = &virtualif_netdev_ops; ++ ++ if (ei_local->features & FE_HW_LRO) ++ dev->features |= NETIF_F_HW_CSUM; ++ else ++ /* Can checksum TCP/UDP over IPv4 */ ++ dev->features |= NETIF_F_IP_CSUM; ++ if (ei_local->features & FE_TSO) { ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_TSO; ++#ifdef CONFIG_HIGHMEM /* To avoid doing __skb_linearize */ ++ dev->features |=NETIF_F_HIGHDMA; ++#endif ++ } ++ ++ if (ei_local->features & FE_TSO_V6) { ++ dev->features |= NETIF_F_TSO6; ++ /* Can checksum TCP/UDP over IPv6 */ ++ dev->features |= NETIF_F_IPV6_CSUM; ++ } ++ ++ dev->vlan_features = dev->features; ++ ++ if (ei_local->features & FE_ETHTOOL) { ++ dev->ethtool_ops = &mdrv_noe_virt_ethtool_ops; ++ MDrv_NOE_ETHTOOL_Virt_Init(dev); ++ } ++ ++ /* Register this device */ ++ register_netdevice(dev); ++ } ++} ++ ++void MDrv_NOE_Set_Lro_Ip(char *lan_ip_addr) ++{ ++ unsigned int lan_ip; ++ MDrv_NOE_UTIL_Str_To_Ip(&lan_ip, lan_ip_addr); ++ lan_ip = htonl(lan_ip); ++ lro_para.lan_ip1 = lan_ip; ++ ++ NOE_MSG_DBG("[%s]lan_ip_addr = %s (lan_ip = 0x%x)\n", __func__, lan_ip_addr, lan_ip); ++} ++ ++int MDrv_NOE_Open(struct net_device *dev) ++{ ++ int err; ++ struct END_DEVICE *ei_local; ++ ++ ei_local = netdev_priv(dev); ++ if (!ei_local) { ++ NOE_MSG_ERR("%s: MDrv_NOE_Open passed a non-existent device!\n", dev->name); ++ return -ENXIO; ++ } ++ ++ if (!try_module_get(THIS_MODULE)) { ++ NOE_MSG_ERR("%s: Cannot reserve module\n", __func__); ++ return -1; ++ } ++ ++ if (ei_local->features & FE_INT_NAPI) ++ NOE_MSG_MUST("Bottom Half : NAPI\n"); ++ else if (ei_local->features & FE_INT_TASKLET) ++ NOE_MSG_MUST("Bottom Half : Tasklet\n"); ++ else if (ei_local->features & FE_INT_WORKQ) ++ NOE_MSG_MUST("Bottom Half : Workqueue\n"); ++ ++ MDrv_NOE_Reset_Statistics(ei_local); ++ err = MDrv_NOE_Init_Dma(dev); ++ if (err) ++ return err; ++ ++ MHal_NOE_Reset_GMAC(); ++ ++ /* initialize fe and switch register */ ++ MDrv_NOE_MAC_Init(dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ if (!ei_local->pseudo_dev) ++ MDrv_NOE_Virtif_Init(ei_local, dev); ++ ++ if (!ei_local->pseudo_dev) { ++ NOE_MSG_ERR("Open pseudo_dev failed.\n"); ++ } ++ else ++ MDrv_NOE_Virtif_Open(ei_local->pseudo_dev); ++ } ++ ++ if (ei_local->features & FE_SW_LRO) ++ MDrv_NOE_Set_Lro_Ip(ei_local->lan_ip4_addr); ++ ++ MDrv_NOE_Set_Forward_Cfg(dev); ++ ++ if ((MHal_NOE_Need_Reset() == E_NOE_RET_TRUE) && (ei_local->features & FE_HW_LRO)) { ++ ei_local->kreset_task = kthread_create(MDrv_NOE_Reset_Thread, NULL, "FE_reset_kthread"); ++ if (IS_ERR(ei_local->kreset_task)) ++ return PTR_ERR(ei_local->kreset_task); ++ wake_up_process(ei_local->kreset_task); ++ } ++ ++ netif_start_queue(dev); ++ MDrv_NOE_Enable_Intr(dev); ++ ++ return 0; ++} ++ ++int MDrv_NOE_Close(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ MHal_NOE_Reset_FE(); ++ if ((MHal_NOE_Need_Reset() == E_NOE_RET_TRUE) && (ei_local->features & FE_HW_LRO)) ++ kthread_stop(ei_local->kreset_task); ++ ++ netif_stop_queue(dev); ++ MHal_NOE_Stop(); ++ ++ MDrv_NOE_Disable_Intr(dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) ++ MDrv_NOE_Virtif_Close(ei_local->pseudo_dev); ++ ++ MDrv_NOE_Deinit_Dma(dev); ++ ++ ++ module_put(THIS_MODULE); ++ ++ return 0; ++} ++ ++static int MDrv_NOE_Start_Xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ return ei_local->ei_start_xmit(skb, dev, 1); ++} ++ ++struct net_device_stats *MDrv_NOE_Get_Stats(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ return &ei_local->stat; ++} ++ ++ ++ ++int MDrv_NOE_Ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ unsigned int lan_ip; ++ int ret = 0; ++ unsigned long result; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct ra_mii_ioctl_data mii; ++ ++ if (ei_local->features & FE_QDMA) { ++ ret = MDrv_NOE_QDMA_Ioctl(dev, ifr, cmd); ++ if (ret <= 0) ++ return ret; ++ } ++ ++ spin_lock_irq(&ei_local->page_lock); ++ switch (cmd) { ++ case NOE_MII_READ: ++ result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ MHal_NOE_Read_Mii_Mgr(mii.phy_id, mii.reg_num, &mii.val_out); ++ result = copy_to_user(ifr->ifr_data, &mii, sizeof(mii)); ++ break; ++ ++ case NOE_MII_WRITE: ++ result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ MHal_NOE_Write_Mii_Mgr(mii.phy_id, mii.reg_num, mii.val_in); ++ break; ++ case NOE_MII_READ_CL45: ++ result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ MHal_NOE_Read45_Mii_Mgr(mii.port_num, mii.dev_addr, mii.reg_addr, &mii.val_out); ++ result = copy_to_user(ifr->ifr_data, &mii, sizeof(mii)); ++ break; ++ case NOE_MII_WRITE_CL45: ++ result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ MHal_NOE_Write45_Mii_Mgr(mii.port_num, mii.dev_addr, mii.reg_addr, mii.val_in); ++ break; ++ case NOE_SET_LAN_IP: ++ result = copy_from_user(ei_local->lan_ip4_addr, ifr->ifr_data, IP4_ADDR_LEN); ++ NOE_MSG_DUMP("NOE_SET_LAN_IP: %s\n", ei_local->lan_ip4_addr); ++ ++ if (ei_local->features & FE_SW_LRO) ++ MDrv_NOE_Set_Lro_Ip(ei_local->lan_ip4_addr); ++ ++ if (ei_local->features & FE_HW_LRO) { ++ MDrv_NOE_UTIL_Str_To_Ip(&lan_ip, ei_local->lan_ip4_addr); ++ MHal_NOE_LRO_Set_Ip(lan_ip); ++ } ++ ++ break; ++ ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ spin_unlock_irq(&ei_local->page_lock); ++ return ret; ++} ++ ++static const struct net_device_ops mdrv_noe_netdev_ops = { ++ .ndo_init = MDrv_NOE_Init, ++ .ndo_uninit = MDrv_NOE_Uninit, ++ .ndo_open = MDrv_NOE_Open, ++ .ndo_stop = MDrv_NOE_Close, ++ .ndo_start_xmit = MDrv_NOE_Start_Xmit, ++ .ndo_get_stats = MDrv_NOE_Get_Stats, ++ .ndo_set_mac_address = MDrv_NOE_Set_Mac_Addr, ++ .ndo_change_mtu = MDrv_NOE_Change_Mtu, ++ .ndo_do_ioctl = MDrv_NOE_Ioctl, ++ .ndo_validate_addr = eth_validate_addr, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = MDrv_NOE_Full_Poll, ++#endif ++}; ++ ++void MDrv_NOE_Setup_Fptable(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ dev->netdev_ops = &mdrv_noe_netdev_ops; ++ ++ if (ei_local->features & FE_ETHTOOL) ++ dev->ethtool_ops = &mdrv_noe_ethtool_ops; ++ ++#define TX_TIMEOUT (5 * HZ) ++ dev->watchdog_timeo = TX_TIMEOUT; ++} ++ ++void MDrv_NOE_Set_Io_Coherence(struct END_DEVICE *ei_local) ++{ ++ if (ei_local->features & FE_HW_IOCOHERENT) { ++ NOE_MSG_DBG("[NOE] HW IO coherent is enabled !\n"); ++ MHal_NOE_IO_Enable_Coherence((ei_local->features & FE_QDMA_FQOS)?TRUE:FALSE); ++ NOE_SETUP_COHERENT_DMA_OPS(ei_local->dev); ++ } else { ++ NOE_MSG_DBG("[NOE] HW IO coherent is disabled !\n"); ++ NOE_SETUP_NONCOHERENT_DMA_OPS(ei_local->dev); ++ } ++} ++ ++#ifdef CONFIG_PM ++static int MDrv_NOE_Resume(struct platform_device *pdev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ NOE_MSG_DBG("[NOE] Resume!\n"); ++ _MDrv_NOE_Enable(ei_local); ++ if (netif_running(ei_local->netdev)) { ++ NOE_MSG_DBG("noe open\n"); ++ MDrv_NOE_Open(ei_local->netdev); ++ } ++ return 0; ++} ++ ++static inline void _MDrv_NOE_Dma_DeInit(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ MHal_NOE_Dma_DeInit_Global_Config(E_NOE_DMA_PACKET); ++ ++ MHal_NOE_Dma_DeInit_Global_Config((ei_local->features & FE_HW_SFQ)? E_NOE_DMA_QUEUE_WITH_SFQ :E_NOE_DMA_QUEUE); ++} ++ ++ ++static int MDrv_NOE_Suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ NOE_MSG_DBG("[NOE] Suspend!\n"); ++ MDrv_NOE_Close(ei_local->netdev); ++ MDrv_NOE_Disable_Clock(ei_local); ++ _MDrv_NOE_Dma_DeInit(ei_local->netdev); ++ return 0; ++} ++#endif ++/* static struct wakeup_source eth_wake_lock; */ ++ ++static ssize_t ms_noe_debug_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ ++ return (str - buf); ++} ++ ++static ssize_t ms_noe_debug_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ ++ u32 input; ++ input = simple_strtoul(buf, NULL, 10); ++ NOE_MSG_ERR("debug input=%d\n", input); ++ ++ if(input == 0) ++ { ++ MHal_NOE_Reset_FE(); ++ return n; ++ } ++ else if(input == 1) ++ { ++ MHal_NOE_Stop(); ++ return n; ++ } ++ else if(input == 2) ++ { ++ MDrv_NOE_Disable_Intr(g_dev_noe); ++ return n; ++ } ++ else if(input == 3) ++ { ++ MDrv_NOE_Deinit_Dma(g_dev_noe); ++ return n; ++ } ++ else if(input == 4) ++ { ++ MDrv_NOE_Init_Dma(g_dev_noe); ++ return n; ++ } ++ else if(input == 5) ++ { ++ MDrv_NOE_Enable_Intr(g_dev_noe); ++ return n; ++ } ++ else if(input == 6) ++ { ++ MDrv_NOE_MAC_Init(g_dev_noe); ++ MDrv_NOE_Set_Forward_Cfg(g_dev_noe); ++ return n; ++ } ++ else if(input == 7) ++ { ++ MHal_NOE_Reset_SW(); ++ return n; ++ } ++ else if (input == 8) ++ { ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ _MDrv_NOE_Enable(ei_local); ++ } ++ return n; ++ ++ } ++ return -EINVAL; ++} ++DEVICE_ATTR(debug, 0644, ms_noe_debug_show, ms_noe_debug_store); ++ ++ ++static ssize_t noe_mdio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ unsigned int physaddr, reg=0, value=0; ++ ++ physaddr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR; ++ str += scnprintf(str, end - str, "%s physaddr:%d\n",g_dev_noe->name , physaddr); ++ for(reg=0; reg<32; reg++) ++ { ++ if(reg%8==0) str += scnprintf(str, end - str, "%02d: ", reg); ++ MHal_NOE_Read_Mii_Mgr(physaddr, reg, &value); ++ str += scnprintf(str, end - str, "0x%04x ", value); ++ if(reg%8==7) str += scnprintf(str, end - str, "\n"); ++ } ++ ++ if (ei_local->features & FE_GE2_SUPPORT) ++ { ++ physaddr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2; ++ str += scnprintf(str, end - str, "%s physaddr:%d\n",ei_local->pseudo_dev->name , physaddr); ++ for(reg=0; reg<32; reg++) ++ { ++ if(reg%8==0) str += scnprintf(str, end - str, "%02d: ", reg); ++ MHal_NOE_Read_Mii_Mgr(physaddr, reg, &value); ++ str += scnprintf(str, end - str, "0x%04x ", value); ++ if(reg%8==7) str += scnprintf(str, end - str, "\n"); ++ } ++ ++ } ++ return (str - buf); ++} ++ ++static ssize_t noe_mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ unsigned int physaddr, reg=0, value=0; ++ unsigned char token[16]; ++ ++ sscanf(buf, "%s", token); ++ if (0 == strcasecmp(token, "r")) ++ { ++ sscanf(buf, "%s %d %d", token, &physaddr, ®); ++ MHal_NOE_Read_Mii_Mgr(physaddr, reg, &value); ++ printk("mdio %s phyaddr:%d reg:%d val:0x%04x\n", token, physaddr, reg, value); ++ } ++ else if (0 == strcasecmp(token, "w")) ++ { ++ sscanf(buf, "%s %d %d 0x%x", token, &physaddr, ®, &value); ++ MHal_NOE_Write_Mii_Mgr(physaddr, reg, value); ++ printk("mdio %s phyaddr:%d reg:%d val:0x%04x\n", token, physaddr, reg, value); ++ } ++ else ++ { ++ printk("\nUsage: echo r [phyaddr] [reg] > mdio (r 3 0)\n"); ++ printk("Usage: echo w [phyaddr] [reg] [value_hex] > mdio (w 3 0 0x9140)\n"); ++ } ++ ++ return n; ++} ++DEVICE_ATTR(mdio, 0644, noe_mdio_show, noe_mdio_store); ++ ++#ifdef CONFIG_MDIO_IC1819 ++static ssize_t noe_mdio_sw_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ unsigned int i, physaddr, reg=0, value=0; ++ ++ for(i = 0; i < 1; i++) ++ { ++ physaddr = i; ++ str += scnprintf(str, end - str, "%s physaddr:%d\n",ei_local->pseudo_dev->name , physaddr); ++ for(reg=0; reg<32; reg++) ++ { ++ if(reg%8==0) str += scnprintf(str, end - str, "%02d: ", reg); ++ value = mdio_bb_read(physaddr, reg); ++ str += scnprintf(str, end - str, "0x%04x ", value); ++ if(reg%8==7) str += scnprintf(str, end - str, "\n"); ++ } ++ } ++ return (str - buf); ++} ++ ++static ssize_t noe_mdio_sw_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ unsigned int physaddr, reg=0, value=0; ++ unsigned char token[16]; ++ ++ sscanf(buf, "%s", token); ++ if (0 == strcasecmp(token, "r")) ++ { ++ sscanf(buf, "%s %d %d", token, &physaddr, ®); ++ value = mdio_bb_read(physaddr, reg); ++ printk("mdio %s phyaddr:%d reg:%d val:0x%04x\n", token, physaddr, reg, value); ++ } ++ else if (0 == strcasecmp(token, "w")) ++ { ++ sscanf(buf, "%s %d %d 0x%x", token, &physaddr, ®, &value); ++ mdio_bb_write(physaddr, reg, value); ++ printk("mdio %s phyaddr:%d reg:%d val:0x%04x\n", token, physaddr, reg, value); ++ } ++ else ++ { ++ printk("\nUsage: echo r [phyaddr] [reg] > mdio (r 3 0)\n"); ++ printk("Usage: echo w [phyaddr] [reg] [value_hex] > mdio (w 3 0 0x9140)\n"); ++ } ++ ++ return n; ++} ++DEVICE_ATTR(mdio_sw, 0644, noe_mdio_sw_show, noe_mdio_sw_store); ++#endif ++ ++static ssize_t noe_io_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ unsigned int addr=0, value=0; ++ unsigned char token[16]; ++ ++ sscanf(buf, "%s", token); ++ if (0 == strcasecmp(token, "r")) ++ { ++ sscanf(buf, "%s 0x%x", token, &addr); ++ value = (*(volatile unsigned int *)(g_dev_noe->base_addr+addr)); ++ printk("noe_io %s addr:0x%08x val:0x%08x\n", token, addr, value); ++ } ++ else if (0 == strcasecmp(token, "w")) ++ { ++ sscanf(buf, "%s 0x%x 0x%x", token, &addr, &value); ++ (*(volatile unsigned int *)(g_dev_noe->base_addr+addr)) = (value); ++ printk("noe_io %s addr:0x%08x val:0x%08x\n", token, addr, value); ++ } ++ else ++ { ++ printk("\nUsage: echo r [addr_hex] > noe_io\n"); ++ printk("Usage: echo w [addr_hex] [value_hex] > noe_io\n"); ++ } ++ ++ return n; ++} ++DEVICE_ATTR(noe_io, 0200, NULL, noe_io_store); ++ ++static int MDrv_NOE_Probe(struct platform_device *pdev) ++{ ++ struct END_DEVICE *ei_local; ++ struct net_device *netdev; ++ struct device_node *node = NULL; ++ const char *mac_addr; ++ int ret; ++ void __iomem *ethdma_sysctl_base = NULL; ++ struct noe_irq irq_info; ++ ++ netdev = alloc_etherdev_mqs(sizeof(struct END_DEVICE), GMAC1_TXQ_NUM, 1); ++ netif_carrier_off(netdev); ++ if (!netdev) ++ return -ENOMEM; ++ ++ MDrv_NOE_LOG_Init(netdev); ++ SET_NETDEV_DEV(netdev, &pdev->dev); ++ ++ g_dev_noe = netdev; ++ ei_local = netdev_priv(netdev); ++ ei_local->dev = &pdev->dev; ++ ei_local->dev->dma_mask = &noe_dmamask; ++ ei_local->dev->coherent_dma_mask = 0xffffffff; ++ ei_local->netdev = netdev; ++ ei_local->irq_attached = FALSE; ++ MDrv_NOE_CONFIG_Set_Features(ei_local); ++ ++ MDrv_NOE_CONFIG_Set_Architecture(ei_local); ++ MDrv_NOE_LOG_Init(netdev); ++ MDrv_NOE_LOG_Set_Level(E_MDRV_NOE_MSG_CTRL_DBG); ++ ++ NOE_MSG_DBG("features=0x%x,architecture=0x%x\n", ei_local->features, ei_local->architecture); ++ ++ if ((ei_local->features & FE_HW_IOCOHERENT) && (ei_local->features & FE_QDMA_FQOS)) { ++ ei_local->qdma_pdev = platform_device_alloc("QDMA", PLATFORM_DEVID_AUTO); ++ if (!ei_local->qdma_pdev) { ++ dev_err(&pdev->dev, "QDMA platform device allocate fail!\n"); ++ ret = -ENOMEM; ++ goto err_free_dev; ++ } ++ ++ ei_local->qdma_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); ++ ei_local->qdma_pdev->dev.dma_mask = &ei_local->qdma_pdev->dev.coherent_dma_mask; ++ } ++ else { ++ ei_local->qdma_pdev = pdev; ++ } ++ /* iomap registers */ ++#ifdef CONFIG_OF ++ node = of_parse_phandle(pdev->dev.of_node, NOE_COMPATIBLE_ETHSYS, 0); ++ if (node != NULL) { ++ ethdma_sysctl_base = of_iomap(node, 0); ++ } ++ else { ++ ethdma_sysctl_base = (void *)ioremap(NOE_PHYS, NOE_SIZE); ++ } ++#endif ++ ++ if (ethdma_sysctl_base == NULL) { ++ ethdma_sysctl_base = (void *)ioremap(NOE_PHYS, NOE_SIZE); ++ } ++ ++ if (IS_ERR(ethdma_sysctl_base)) { ++ NOE_MSG_ERR("no ethdma_sysctl_base found\n"); ++ return -ENOMEM; ++ } ++ NOE_MSG_DBG("ethdma_sysctl_base = 0x%p\n", ethdma_sysctl_base); ++ ++ /* get MAC address */ ++#ifdef CONFIG_OF ++ mac_addr = of_get_mac_address(pdev->dev.of_node); ++#endif ++ if (mac_addr) ++ ether_addr_copy(netdev->dev_addr, mac_addr); ++ ++ /* Set Pin Mux */ ++ ei_local->pin_mux = NOE_CFG_PIN_MUX_SEL; ++ ++ NOE_MSG_DBG("pin sel = %4d\n", ei_local->pin_mux); ++ /* get IRQs */ ++ MHAL_NOE_Get_Interrupt(&irq_info); ++ ei_local->irq_num = irq_info.num; ++#ifdef CONFIG_OF ++ if (_MDrv_NOE_Is_IRQ0_Handler_Available(ei_local) == FALSE) { ++ ei_local->irq1 = platform_get_irq(pdev, 0); ++ ei_local->irq2 = platform_get_irq(pdev, 1); ++ } ++ else { ++ ei_local->irq0 = platform_get_irq(pdev, 0); ++ ei_local->irq1 = platform_get_irq(pdev, 1); ++ ei_local->irq2 = platform_get_irq(pdev, 2); ++ ++ if ((int)ei_local->irq0 < 0) { ++ NOE_MSG_DBG("no irq0 info in dts. set by irq_info\n"); ++ ei_local->irq0 = irq_info.irq[E_NOE_IRQ_0]; ++ } ++ } ++ ++ if ((int)ei_local->irq1 < 0) { ++ NOE_MSG_DBG("no irq1 info in dts. set by irq_info\n"); ++ ei_local->irq1 = irq_info.irq[E_NOE_IRQ_1]; ++ } ++ ++ if ((int)ei_local->irq2 < 0) { ++ NOE_MSG_DBG("no irq2 info in dts. set by irq_info\n"); ++ ei_local->irq2 = irq_info.irq[E_NOE_IRQ_2]; ++ } ++#else ++ ei_local->irq0 = irq_info.irq[E_NOE_IRQ_0]; ++ ei_local->irq1 = irq_info.irq[E_NOE_IRQ_1]; ++ ei_local->irq2 = irq_info.irq[E_NOE_IRQ_2]; ++#endif ++ ++ NOE_MSG_DBG("irqs(%d) = %4d, %4d, %4d\n", ei_local->irq_num, ei_local->irq0, ei_local->irq1, ei_local->irq2); ++ ++ MDrv_NOE_Setup_Fptable(netdev); ++ ++ netif_set_real_num_tx_queues(netdev, GMAC1_TXQ_NUM); ++ netif_set_real_num_rx_queues(netdev, 1); ++ ++ netdev->addr_len = 6; ++ netdev->base_addr = (unsigned long)(ethdma_sysctl_base); ++ ++ _MDrv_NOE_Enable(ei_local); ++ ++ gdebug_class_dev = device_create(msys_get_sysfs_class(), NULL, MKDEV(241, 2), NULL, "noe"); ++ device_create_file(gdebug_class_dev, &dev_attr_debug); ++ device_create_file(gdebug_class_dev, &dev_attr_mdio); ++ device_create_file(gdebug_class_dev, &dev_attr_noe_io); ++ ++ #ifdef CONFIG_MDIO_IC1819 ++ device_create_file(gdebug_class_dev, &dev_attr_mdio_sw); ++ ++ //set ic1819 force link ++ mdio_bb_write(0, 255, 3); //change to page3, reg:0xff, val:0x03 ++ mdio_bb_write(0, 93, 256); //reg:5D, val:0x100 ++ mdio_bb_write(0, 255, 0); //change back to page0 ++ #endif ++ ++ /* net_device structure Init */ ++ NOE_MSG_DBG("NOE Ethernet Driver Initialization.\n"); ++ NOE_MSG_DBG("%s %d rx/%d tx descriptors allocated, mtu = %d!\n", "noe", NUM_RX_DESC, NUM_TX_DESC, netdev->mtu); ++ ++ if (ei_local->features & FE_INT_NAPI) ++ NOE_MSG_DBG("NAPI enable, Tx Ring = %d, Rx Ring = %d\n", NUM_TX_DESC, NUM_RX_DESC); ++ ++ if (ei_local->features & FE_ETHTOOL) ++ MDrv_NOE_ETHTOOL_Init(netdev); ++ ++ ret = MDrv_NOE_PROC_Init(netdev); ++ if (ret) { ++ dev_err(&pdev->dev, "error set debug proc\n"); ++ goto err_free_dev; ++ } ++ /* Register net device for the driver */ ++ ret = register_netdev(netdev); ++ if (ret) { ++ dev_err(&pdev->dev, "error bringing up device\n"); ++ goto err_free_dev; ++ } ++ ++ /*keep power domain on*/ ++ device_init_wakeup(&pdev->dev, true); ++ ++ return 0; ++ ++err_free_dev: ++ free_netdev(netdev); ++ return ret; ++} ++ ++static int MDrv_NOE_Remove(struct platform_device *pdev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ MDrv_NOE_Disable_Clock(ei_local); ++ return 0; ++} ++ ++struct net_device *MDrv_NOE_Get_Dev(EN_NOE_DEV_IDX idx) ++{ ++ ++ struct END_DEVICE *ei_local = netdev_priv(g_dev_noe); ++ char ifname[IFNAMSIZ]; ++ ++ if (idx == E_NOE_DEV_MAIN) { ++ if ((ei_local != NULL) && (ei_local->netdev != NULL)) { ++ return ei_local->netdev; ++ } ++ } ++ else if (idx == E_NOE_DEV_PSEUDO) { ++ if ((ei_local != NULL) && (ei_local->pseudo_dev != NULL)) { ++ return ei_local->pseudo_dev; ++ } ++ } ++ else if (idx == E_NOE_DEV_LAN) { ++ if ((ei_local != NULL) && (ei_local->netdev != NULL)) { ++ sprintf(ifname,"%s.1",ei_local->netdev->name); ++ return dev_get_by_name(&init_net, ifname); ++ } ++ } ++ else if (idx == E_NOE_DEV_WAN) { ++ if ((ei_local != NULL) && (ei_local->netdev != NULL)) { ++ sprintf(ifname,"%s.2",ei_local->netdev->name); ++ return dev_get_by_name(&init_net, ifname); ++ } ++ } ++ ++ return NULL; ++} ++ ++EXPORT_SYMBOL(MDrv_NOE_Get_Dev); ++ ++module_platform_driver(mstar_noe_driver); ++MODULE_DESCRIPTION("NOE Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe.h b/drivers/sstar/noe/drv/eth/mdrv_noe.h +new file mode 100755 +index 000000000000..a2064b6e28ea +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe.h +@@ -0,0 +1,309 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_NOE_H_ ++#define _MDRV_NOE_H_ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) ++/* LRO support */ ++#include ++#include ++#else ++#include ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION... */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "ms_msys.h" //msys_request_dmem ++ ++#include ++#include ++ ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "mdrv_noe_def.h" ++#include "mdrv_types.h" ++#include "mhal_noe.h" ++#include "mhal_noe_dma.h" ++#include "mdrv_noe_dma.h" ++#include "mdrv_noe_config.h" ++#include "mdrv_noe_proc.h" ++#include "mdrv_noe_lro.h" ++#include "mdrv_noe_mac.h" ++#include "mdrv_noe_ioctl.h" ++#include "mdrv_noe_utils.h" ++#include "mdrv_noe_log.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define FE_RESET_POLLING_MS (5000) ++ ++#define IP4_ADDR_LEN 16 ++#define FE_DEFAULT_LAN_IP "10.10.10.254" ++#define NOE_NAPI_WEIGHT 64 ++ ++#define NOE_DRV_STRING "NOE_DRV" ++#define NOE_COMPATIBLE_DEV_ID "eth,noe" ++#define NOE_COMPATIBLE_SWITCH "noe,switch" ++#define NOE_COMPATIBLE_ETHSYS "noe,ethsys" ++ ++ ++#if defined(CONFIG_MSTAR_ARM_BD_FPGA) || defined(CONFIG_NOE_FPGA_VERIFY) ++#ifdef NOE_CFG_PIN_MUX_SEL ++#undef NOE_CFG_PIN_MUX_SEL ++#define NOE_CFG_PIN_MUX_SEL (E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP_GE2_TO_CHIPTOP) ++#endif ++#define FPGA_NOE_MAC_SPEED E_NOE_SPEED_100 // SPEED_1000 ++#define FPGA_NOE_PHY_SPEED E_NOE_SPEED_10 ++#define FPGA_NOE_PHY_DUPLEX E_NOE_DUPLEX_FULL ++#endif /* CONFIG_MSTAR_ARM_BD_FPGA */ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++enum noe_clks_map { ++ E_NOE_CLK_ETHIF, ++ E_NOE_CLK_ESW, ++ E_NOE_CLK_GP0, ++ E_NOE_CLK_GP1, ++ E_NOE_CLK_GP2, ++ E_NOE_CLK_SGMII_TX250M, ++ E_NOE_CLK_SGMII_RX250M, ++ E_NOE_CLK_SGMII_CDR_REF, ++ E_NOE_CLK_SGMII_CDR_FB, ++ E_NOE_CLK_TRGPLL, ++ E_NOE_CLK_SGMIPLL, ++ E_NOE_CLK_ETH1PLL, ++ E_NOE_CLK_ETH2PLL, ++ E_NOE_CLK_MAX ++}; ++ ++struct lro_counters { ++ u32 lro_aggregated; ++ u32 lro_flushed; ++ u32 lro_no_desc; ++}; ++ ++struct lro_para_struct { ++ unsigned int lan_ip1; ++}; ++ ++struct PSEUDO_ADAPTER { ++ struct net_device *primary_dev; ++ struct net_device *pseudo_dev; ++ struct net_device_stats stat; ++ struct mii_if_info mii_info; ++}; ++ ++ ++struct noe_stats { ++ unsigned int min_free_txd[TOTAL_TXQ_NUM]; ++}; ++ ++ ++struct END_DEVICE { ++ struct device *dev; ++ unsigned int tx_cpu_owner_idx0; ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ unsigned int rx_calc_idx[MAX_RX_RING_NUM]; ++#endif ++ unsigned int tx_ring_full; ++ unsigned int tx_full; /* NOTE(Nelso): unused, can remove */ ++ ++ /* PDMA TX PTR */ ++ dma_addr_t phy_tx_ring0; ++ ++ /* QDMA TX PTR */ ++ struct platform_device *qdma_pdev; ++ struct sk_buff *free_skb[NUM_TX_DESC]; ++ unsigned int tx_dma_ptr; ++ unsigned int tx_cpu_ptr; ++ unsigned int tx_cpu_idx; ++ unsigned int rls_cpu_idx; ++ atomic_t free_txd_num[TOTAL_TXQ_NUM]; ++ unsigned int free_txd_head[TOTAL_TXQ_NUM]; ++ unsigned int free_txd_tail[TOTAL_TXQ_NUM]; ++ struct QDMA_txdesc *txd_pool; ++ dma_addr_t phy_txd_pool; ++ unsigned int txd_pool_info[NUM_TX_DESC]; ++ struct QDMA_txdesc *free_head; ++ unsigned int phy_free_head; ++ unsigned int *free_page_head; ++ dma_addr_t phy_free_page_head; ++ struct PDMA_rxdesc *qrx_ring; ++ dma_addr_t phy_qrx_ring; ++ ++ /* TSO */ ++ unsigned int skb_txd_num; ++ ++ /* MT7623 workaround */ ++ struct work_struct reset_task; ++ ++ /* workqueue_bh */ ++ struct work_struct rx_wq; ++ ++ /* tasklet_bh */ ++ struct tasklet_struct rx_tasklet; ++ ++ struct sk_buff *skb_free[NUM_TX_DESC]; ++ unsigned int free_idx; ++ ++ struct net_device_stats stat; /* The new statistics table. */ ++ spinlock_t page_lock; /* spin_lock for cr access critial section */ ++ spinlock_t irq_lock; /* spin_lock for isr critial section */ ++ struct PDMA_txdesc *tx_ring0; ++ struct PDMA_rxdesc *rx_ring[MAX_RX_RING_NUM]; ++ dma_addr_t phy_rx_ring[MAX_RX_RING_NUM]; ++ void *netrx_skb_data[MAX_RX_RING_NUM][NUM_RX_DESC]; ++ struct sk_buff *netrx0_skbuf[NUM_RX_DESC]; ++ ++ /* napi */ ++ struct napi_struct napi; ++ struct napi_struct napi_rx; ++ struct napi_struct napi_tx; ++ struct net_device dummy_dev; ++ ++ /* clock control */ ++ struct clk *clks[E_NOE_CLK_MAX]; ++ ++ /* GE1 support */ ++ struct net_device *netdev; ++ /* GE2 support */ ++ struct net_device *pseudo_dev; ++ unsigned int is_pseudo; ++ ++ struct mii_if_info mii_info; ++#if NETDEV_LRO_SUPPORTED ++ struct lro_counters lro_counters; ++ struct net_lro_mgr lro_mgr; ++ struct net_lro_desc lro_arr[8]; ++#endif /* NETDEV_LRO_SUPPORTED */ ++ struct vlan_group *vlgrp; ++ ++ /* virtual base addr from device tree */ ++ void __iomem *ethdma_sysctl_base; ++ ++ unsigned int irq0; ++ unsigned int irq1; ++ unsigned int irq2; ++ ++ unsigned int features; ++ unsigned int architecture; ++ ++ /* IP address */ ++ char lan_ip4_addr[IP4_ADDR_LEN]; ++ ++ /* Function pointers */ ++ int (*ei_start_xmit)(struct sk_buff *skb, struct net_device *netdev, int gmac_no); ++ int (*ei_xmit_housekeeping)(struct net_device *netdev, int budget); ++ int (*ei_eth_recv)(struct net_device *dev, struct napi_struct *napi, int budget); ++ int (*ei_fill_tx_desc)(struct net_device *dev, unsigned long *tx_cpu_owner_idx, struct sk_buff *skb, int gmac_no); ++ ++ struct task_struct *kreset_task; ++ unsigned int fe_reset_times; ++ ++ EN_NOE_SEL_PIN_MUX pin_mux; ++ unsigned char log_level; ++ struct noe_stats stats; ++ unsigned char irq_num; ++ unsigned char irq_attached; ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void MDrv_NOE_Set_Lro_Ip(char *lan_ip_addr); ++static inline void *MDrv_NOE_SkbData_Alloc(size_t size, gfp_t flags) ++{ ++#ifdef CONFIG_ETH_SLAB_ALLOC_SKB ++ return kmalloc(size, flags); ++#else ++ return netdev_alloc_frag(size); ++#endif ++} ++ ++static inline void MDrv_NOE_SkbData_Free(void *addr) ++{ ++#ifdef CONFIG_ETH_SLAB_ALLOC_SKB ++ kfree(addr); ++#else ++ skb_free_frag(addr); ++#endif ++} ++ ++static inline struct sk_buff *MDrv_NOE_Skb_Build(void *data, unsigned int frag_size) ++{ ++#ifdef CONFIG_ETH_SLAB_ALLOC_SKB ++ return build_skb(data, 0); ++#else ++ return build_skb(data, frag_size); ++#endif ++} ++ ++ ++#endif /* _MDRV_NOE_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_config.h b/drivers/sstar/noe/drv/eth/mdrv_noe_config.h +new file mode 100755 +index 000000000000..6447a4571635 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_config.h +@@ -0,0 +1,371 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDrv_NOE_CONFIG.H ++/// @author MStar Semiconductor Inc. ++/// @brief NOE Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_NOE_CONFIG_H_ ++#define _MDRV_NOE_CONFIG_H_ ++ ++ ++// ----------------------------------------------------------------------------- ++// define start ++// ----------------------------------------------------------------------------- ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)) ++#define NETDEV_LRO_SUPPORTED (1) ++#else ++#define NETDEV_LRO_SUPPORTED (0) ++#endif ++ ++ ++#define CONFIG_NOE_PM_SUPPORTED (0) ++//------------------------------------------------------------------------------------------------- ++// CONFIG ++//------------------------------------------------------------------------------------------------- ++ ++ ++/* compile flag for features */ ++#define DELAY_INT ++#define CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++/*#define CONFIG_QDMA_QOS_WEB*/ ++#define CONFIG_QDMA_QOS_MARK ++/*#define CONFIG_NOE_NAPI_TX_RX*/ ++/*#define CONFIG_NOE_NAPI_RX_ONLY*/ ++ ++/***** FEATURE *****/ ++#ifdef DELAY_INT ++#define FE_DLY_INT BIT(0) ++#else ++#define FE_DLY_INT (0) ++#endif /* DELAY_INT */ ++#ifdef CONFIG_NOE_HW_LRO ++#define FE_HW_LRO BIT(1) ++#else ++#define FE_HW_LRO (0) ++#endif /* CONFIG_NOE_HW_LRO */ ++#ifdef CONFIG_NOE_HW_LRO_FORCE ++#define FE_HW_LRO_FPORT BIT(2) ++#else ++#define FE_HW_LRO_FPORT (0) ++#endif /* CONFIG_NOE_HW_LRO_FORCE */ ++#ifdef CONFIG_NOE_LRO ++#define FE_SW_LRO BIT(3) ++#else ++#define FE_SW_LRO (0) ++#endif /* CONFIG_NOE_LRO */ ++#ifdef CONFIG_NOE_QDMA ++#define FE_QDMA BIT(4) ++#else ++#define FE_QDMA (0) ++#endif/* CONFIG_NOE_QDMA */ ++#ifdef CONFIG_NOE_NAPI ++#define FE_INT_NAPI BIT(5) ++#else ++#define FE_INT_NAPI (0) ++#endif /* CONFIG_NOE_NAPI */ ++#ifdef CONFIG_NOE_NETWORK_WORKQUEUE_BH ++#define FE_INT_WORKQ BIT(6) ++#else ++#define FE_INT_WORKQ (0) ++#endif /* CONFIG_NOE_NETWORK_WORKQUEUE_BH */ ++#ifdef CONFIG_NOE_NETWORK_TASKLET_BH ++#define FE_INT_TASKLET BIT(7) ++#else ++#define FE_INT_TASKLET (0) ++#endif /* CONFIG_NOE_NETWORK_TASKLET_BH */ ++#ifdef CONFIG_NOE_TX_RX_INT_SEPARATION ++#define FE_IRQ_SEPARATE BIT(8) ++#else ++#define FE_IRQ_SEPARATE (0) ++#endif /* CONFIG_NOE_TX_RX_INT_SEPARATION */ ++#ifdef CONFIG_NOE_GMAC2 ++#define FE_GE2_SUPPORT BIT(9) ++#else ++#define FE_GE2_SUPPORT (0) ++#endif /* CONFIG_NOE_GMAC2 */ ++#ifdef CONFIG_NOE_ETHTOOL ++#define FE_ETHTOOL BIT(10) ++#else ++#define FE_ETHTOOL (0) ++#endif /* CONFIG_NOE_ETHTOOL */ ++#ifdef CONFIG_NOE_CHECKSUM_OFFLOAD ++#define FE_CSUM_OFFLOAD BIT(11) ++#else ++#define FE_CSUM_OFFLOAD (0) ++#endif /* CONFIG_NOE_CHECKSUM_OFFLOAD */ ++#ifdef CONFIG_NOE_TSO ++#define FE_TSO BIT(12) ++#else ++#define FE_TSO (0) ++#endif /* CONFIG_NOE_TSO */ ++#ifdef CONFIG_NOE_TSOV6 ++#define FE_TSO_V6 BIT(13) ++#else ++#define FE_TSO_V6 (0) ++#endif /* CONFIG_NOE_TSOV6 */ ++#ifdef CONFIG_NOE_HW_VLAN_TX ++#define FE_HW_VLAN_TX BIT(14) ++#else ++#define FE_HW_VLAN_TX (0) ++#endif /* CONFIG_NOE_HW_VLAN_TX */ ++#ifdef CONFIG_NOE_HW_VLAN_RX ++#define FE_HW_VLAN_RX BIT(15) ++#else ++#define FE_HW_VLAN_RX (0) ++#endif /* CONFIG_NOE_HW_VLAN_RX */ ++#ifdef CONFIG_NOE_QDMA ++#define FE_QDMA_TX BIT(16) ++#else ++#define FE_QDMA_TX (0) ++#endif /* CONFIG_NOE_QDMA */ ++#ifdef CONFIG_NOE_QDMATX_QDMARX ++#define FE_QDMA_RX BIT(17) ++#else ++#define FE_QDMA_RX (0) ++#endif /* CONFIG_NOE_QDMATX_QDMARX */ ++#ifdef CONFIG_HW_SFQ ++#define FE_HW_SFQ BIT(18) ++#else ++#define FE_HW_SFQ (0) ++#endif /* CONFIG_HW_SFQ */ ++#ifdef CONFIG_NOE_HW_IOCOHERENT ++#define FE_HW_IOCOHERENT BIT(19) ++#else ++#define FE_HW_IOCOHERENT (0) ++#endif /* CONFIG_NOE_HW_IOCOHERENT */ ++#if defined(CONFIG_MSTAR_ARM_BD_FPGA) || defined(CONFIG_NOE_FPGA_VERIFY) ++#define FE_FPGA_MODE BIT(20) ++#else ++#define FE_FPGA_MODE (0) ++#endif /* CONFIG_MSTAR_ARM_BD_FPGA */ ++#ifdef CONFIG_NOE_HW_LRO ++#define FE_HW_LRO_DBG BIT(21) ++#else ++#define FE_HW_LRO_DBG 0 ++#endif /* CONFIG_NOE_HW_LRO */ ++#ifdef CONFIG_NOE_INT_DBG ++#define FE_NOE_INT_DBG BIT(22) ++#else ++#define FE_NOE_INT_DBG (0) ++#endif/* CONFIG_NOE_INT_DBG */ ++#ifdef CONFIG_USER_SNMPD ++#define USER_SNMPD BIT(23) ++#else ++#define USER_SNMPD (0) ++#endif /* CONFIG_USER_SNMPD */ ++#ifdef CONFIG_TASKLET_WORKQUEUE_SW ++#define TASKLET_WORKQUEUE_SW BIT(24) ++#else ++#define TASKLET_WORKQUEUE_SW (0) ++#endif /* CONFIG_TASKLET_WORKQUEUE_SW */ ++#if defined(CONFIG_NOE_HW_NAT) || defined(CONFIG_NOE_HW_NAT_MODULE) || defined(CONFIG_NOE_NAT_HW) ++#define FE_HW_NAT BIT(25) ++#else ++#define FE_HW_NAT (0) ++#endif /* CONFIG_NOE_HW_NAT ...*/ ++#ifdef CONFIG_NOE_NAPI_TX_RX ++#define FE_INT_NAPI_TX_RX BIT(26) ++#else ++#define FE_INT_NAPI_TX_RX (0) ++#endif /* CONFIG_NOE_NAPI_TX_RX */ ++#ifdef CONFIG_QDMA_MQ ++#define QDMA_MQ BIT(27) ++#else ++#define QDMA_MQ (0) ++#endif /* CONFIG_QDMA_MQ */ ++#ifdef CONFIG_NOE_NAPI_RX_ONLY ++#define FE_INT_NAPI_RX_ONLY BIT(28) ++#else ++#define FE_INT_NAPI_RX_ONLY (0) ++#endif ++#ifdef CONFIG_QDMA_SUPPORT_QOS ++#define FE_QDMA_FQOS BIT(29) ++#else ++#define FE_QDMA_FQOS (0) ++#endif ++ ++#ifdef CONFIG_QDMA_QOS_WEB ++#define QDMA_QOS_WEB BIT(30) ++#else ++#define QDMA_QOS_WEB (0) ++#endif ++ ++#ifdef CONFIG_QDMA_QOS_MARK ++#define QDMA_QOS_MARK BIT(31) ++#else ++#define QDMA_QOS_MARK (0) ++#endif ++ ++ ++/***** ARCHITECTURE *****/ ++#ifdef CONFIG_NOE_GMAC2 ++#define GMAC2 BIT(0) ++#else ++#define GMAC2 (0) ++#endif /* CONFIG_NOE_GMAC2 */ ++#ifdef CONFIG_LAN_WAN_SUPPORT ++#define LAN_WAN_SUPPORT BIT(1) ++#else ++#define LAN_WAN_SUPPORT (0) ++#endif /* CONFIG_LAN_WAN_SUPPORT */ ++#if (defined(CONFIG_GE1_RGMII_AN) || defined(CONFIG_GE1_GMII_AN_INTPHY) || defined(CONFIG_GE1_GMII_AN_EXTPHY)) ++#define GE1_RGMII_AN BIT(2) ++#else ++#define GE1_RGMII_AN (0) ++#endif /* CONFIG_GE1_RGMII_AN */ ++#ifdef CONFIG_GE1_RGMII_ONE_EPHY ++#define GE1_RGMII_ONE_EPHY BIT(3) ++#else ++#define GE1_RGMII_ONE_EPHY (0) ++#endif /* CONFIG_GE1_RGMII_ONE_EPHY */ ++#if (defined(CONFIG_GE2_RGMII_AN) || defined(CONFIG_GE2_GMII_AN_EXTPHY)) ++#define GE2_RGMII_AN BIT(4) ++#else ++#define GE2_RGMII_AN (0) ++#endif /* CONFIG_GE2_RGMII_AN */ ++#ifdef CONFIG_GE2_INTERNAL_GPHY ++#define GE2_INTERNAL_GPHY BIT(5) ++#else ++#define GE2_INTERNAL_GPHY (0) ++#endif /* CONFIG_GE2_INTERNAL_GPHY */ ++ ++ ++ ++#ifndef CONFIG_MAC_TO_GIGAPHY_MODE_ADDR ++#define CONFIG_MAC_TO_GIGAPHY_MODE_ADDR (0) ++#endif /* CONFIG_MAC_TO_GIGAPHY_MODE_ADDR */ ++#ifndef CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 ++#define CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 (0) ++#endif /* CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 */ ++ ++#if ((!defined(CONFIG_GE1_RGMII_NONE)) && (!defined(CONFIG_NOE_GMAC2))) ++ #define NOE_CFG_PIN_MUX_SEL (E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP) ++#elif (defined(CONFIG_GE1_RGMII_NONE) && (defined(CONFIG_NOE_GMAC2))) ++ #define NOE_CFG_PIN_MUX_SEL (E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP) ++#elif ((!defined(CONFIG_GE1_RGMII_NONE)) && (defined(CONFIG_NOE_GMAC2))) ++ #define NOE_CFG_PIN_MUX_SEL (E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP_GE2_TO_CHIPTOP) ++#endif ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// COMPATIBILITY ++//------------------------------------------------------------------------------------------------- ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ++ #define skb_vlan_tag_present(__skb) vlan_tx_tag_present(__skb) ++ #define skb_vlan_tag_get(__skb) vlan_tx_tag_get(__skb) ++ #define skb_vlan_tag_get_id(__skb) vlan_tx_tag_get_id(__skb) ++ #define skb_free_frag(new_data) dev_kfree_skb_any(new_data) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) ++ #define ether_addr_copy(dst, src) memcpy(dst, src, ETH_ALEN) ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) */ ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) */ ++ ++ ++ ++#if 1 ++ #define NOE_SETUP_COHERENT_DMA_OPS(dev_ptr) ++ #define NOE_SETUP_NONCOHERENT_DMA_OPS(dev_ptr) ++#elif defined(CONFIG_ARM) ++ #define NOE_SETUP_COHERENT_DMA_OPS(dev_ptr) set_dma_ops(dev_ptr, &coherent_swiotlb_dma_ops) ++ #define NOE_SETUP_NONCOHERENT_DMA_OPS(dev_ptr) set_dma_ops(dev_ptr, &noncoherent_swiotlb_dma_ops); ++#elif defined(CONFIG_ARM64) ++ #define NOE_SETUP_COHERENT_DMA_OPS(dev_ptr) arch_setup_dma_ops(dev_ptr, 0, 0, NULL, TRUE) ++ #define NOE_SETUP_NONCOHERENT_DMA_OPS(dev_ptr) arch_setup_dma_ops(dev_ptr, 0, 0, NULL, FALSE) ++#endif /* CONFIG_ARM64 */ ++ ++ ++#if 0/// defined(CONFIG_MIPS) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ #define NOE_MAP_VA_TO_PA(dev, va, size, dir) MHAL_NOE_MAP_VA_TO_PA(dev, va, size, dir) ++ #define NOE_MAP_IS_ERROR_PA(dev, pa) (0) ++#else ++ #define NOE_MAP_VA_TO_PA(dev, va, size, dir) dma_map_single(dev, va, size, dir) ++ #define NOE_MAP_IS_ERROR_PA(dev, pa) dma_mapping_error(dev, pa) ++#endif ++ ++ ++#if defined(CONFIG_MIPS) || defined(CONFIG_ARM) ++#define NOE_DEV_DMA_MASK (0xFFFFFFFF) ++#define NOE_DEV_COHERENT_DMA_MASK (0xFFFFFFFF) ++#elif defined(CONFIG_ARM64) ++#define NOE_DEV_DMA_MASK (0xFFFFFFFF) ++#define NOE_DEV_COHERENT_DMA_MASK (0xFFFFFFFF) ++#else ++#define NOE_DEV_DMA_MASK (0xFFFFFFFF) ++#define NOE_DEV_COHERENT_DMA_MASK (0xFFFFFFFF) ++#endif ++ ++// ----------------------------------------------------------------------------- ++// DBG ++// ----------------------------------------------------------------------------- ++#define MAX_PSEUDO_ENTRY 1 ++#define NOE_DBG_PRINT ++ ++//------------------------------------------------------------------------------------------------- ++// MACRO ++//------------------------------------------------------------------------------------------------- ++ ++#define MDrv_NOE_CONFIG_Set_Features(end_device) \ ++{ \ ++end_device->features = 0; \ ++end_device->features |= FE_DLY_INT; \ ++end_device->features |= FE_HW_LRO; \ ++end_device->features |= FE_HW_LRO_FPORT;\ ++end_device->features |= FE_HW_LRO_DBG; \ ++end_device->features |= FE_SW_LRO; \ ++end_device->features |= FE_QDMA; \ ++end_device->features |= FE_INT_NAPI; \ ++end_device->features |= FE_INT_WORKQ; \ ++end_device->features |= FE_INT_TASKLET; \ ++end_device->features |= FE_IRQ_SEPARATE;\ ++end_device->features |= FE_GE2_SUPPORT; \ ++end_device->features |= FE_ETHTOOL; \ ++end_device->features |= FE_CSUM_OFFLOAD;\ ++end_device->features |= FE_TSO; \ ++end_device->features |= FE_TSO_V6; \ ++end_device->features |= FE_HW_VLAN_TX; \ ++end_device->features |= FE_HW_VLAN_RX; \ ++end_device->features |= FE_QDMA_TX; \ ++end_device->features |= FE_QDMA_RX; \ ++end_device->features |= FE_HW_SFQ; \ ++end_device->features |= FE_HW_IOCOHERENT; \ ++end_device->features |= FE_FPGA_MODE; \ ++end_device->features |= FE_HW_NAT; \ ++end_device->features |= FE_INT_NAPI_TX_RX; \ ++end_device->features |= FE_INT_NAPI_RX_ONLY; \ ++end_device->features |= FE_QDMA_FQOS; \ ++end_device->features |= QDMA_QOS_WEB; \ ++end_device->features |= QDMA_QOS_MARK; \ ++} ++ ++#define MDrv_NOE_CONFIG_Set_Architecture(end_device) \ ++{ \ ++end_device->architecture = 0; \ ++end_device->architecture |= GMAC2; \ ++end_device->architecture |= LAN_WAN_SUPPORT; \ ++end_device->architecture |= GE1_RGMII_AN; \ ++end_device->architecture |= GE1_RGMII_ONE_EPHY; \ ++end_device->architecture |= GE2_RGMII_AN; \ ++end_device->architecture |= GE2_INTERNAL_GPHY; \ ++} ++ ++#endif /* _MDRV_NOE_CONFIG_H_ */ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_def.h b/drivers/sstar/noe/drv/eth/mdrv_noe_def.h +new file mode 100755 +index 000000000000..400248bb2819 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_def.h +@@ -0,0 +1,40 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_DEF.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_NOE_DEF_H_ ++#define _MDRV_NOE_DEF_H_ ++ ++ ++typedef enum { ++ E_NOE_DEV_MAIN = 0, ++ E_NOE_DEV_PSEUDO, ++ E_NOE_DEV_LAN, ++ E_NOE_DEV_WAN ++}EN_NOE_DEV_IDX; ++ ++ ++ ++struct net_device *MDrv_NOE_Get_Dev(EN_NOE_DEV_IDX idx); ++#endif +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_dma.h b/drivers/sstar/noe/drv/eth/mdrv_noe_dma.h +new file mode 100755 +index 000000000000..377a9a144fce +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_dma.h +@@ -0,0 +1,81 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_DMA.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++#ifndef _MDRV_NOE_DMA_H_ ++#define _MDRV_NOE_DMA_H_ ++ ++ ++ ++ ++struct parse_result { ++ /* layer2 header */ ++ u8 dmac[6]; ++ u8 smac[6]; ++ ++ /* vlan header */ ++ u16 vlan_tag; ++ u16 vlan1_gap; ++ u16 vlan1; ++ u16 vlan2_gap; ++ u16 vlan2; ++ u16 vlan_layer; ++ ++ /* pppoe header */ ++ u32 pppoe_gap; ++ u16 ppp_tag; ++ u16 pppoe_sid; ++ ++ /* layer3 header */ ++ u16 eth_type; ++ struct iphdr iph; ++ struct ipv6hdr ip6h; ++ ++ /* layer4 header */ ++ struct tcphdr th; ++ struct udphdr uh; ++ ++ u32 pkt_type; ++ u8 is_mcast; ++}; ++ ++int MDrv_NOE_PDMA_Init_Rx(struct net_device *dev); ++int MDrv_NOE_PDMA_Init_Tx(struct net_device *dev); ++void MDrv_NOE_PDMA_Deinit_Rx(struct net_device *dev); ++void MDrv_NOE_PDMA_Deinit_Tx(struct net_device *dev); ++int MDrv_NOE_PDMA_Start_Xmit(struct sk_buff *skb, struct net_device *dev, int gmac_no); ++int MDrv_NOE_PDMA_Xmit_Housekeeping(struct net_device *netdev, int budget); ++ ++int MDrv_NOE_QDMA_Init_Rx(struct net_device *dev); ++int MDrv_NOE_QDMA_Init_Tx(struct net_device *dev); ++void MDrv_NOE_QDMA_Deinit_Rx(struct net_device *dev); ++void MDrv_NOE_QDMA_Deinit_Tx(struct net_device *dev); ++int MDrv_NOE_QDMA_Start_Xmit(struct sk_buff *skb, struct net_device *dev, int gmac_no); ++int MDrv_NOE_QDMA_Xmit_Housekeeping(struct net_device *netdev, int budget); ++int MDrv_NOE_QDMA_Ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++ ++ ++#endif /* _MDRV_NOE_DMA_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_ethtool.c b/drivers/sstar/noe/drv/eth/mdrv_noe_ethtool.c +new file mode 100755 +index 000000000000..c9431bd26b1d +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_ethtool.c +@@ -0,0 +1,196 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_ETHTOOL.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mdrv_noe.h" ++#include ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++static struct net_device *ethtool_dev = NULL; ++ ++ ++ ++ ++ ++unsigned char MDrv_NOE_ETHTOOL_Get_Phy_Address(void) ++{ ++ struct END_DEVICE *ei_local; ++ ++ if (ethtool_dev != NULL) { ++ ei_local = netdev_priv(ethtool_dev); ++ if (!ei_local->netdev) ++ return 0; ++ return ei_local->mii_info.phy_id; ++ } ++ return 0; ++} ++ ++u32 MDrv_NOE_ETHTOOL_Get_Link(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ return mii_link_ok(&ei_local->mii_info); ++} ++ ++int MDrv_NOE_ETHTOOL_Set_Settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ mii_ethtool_sset(&ei_local->mii_info, cmd); ++ NOE_MSG_DUMP("%s,%d %d,%d,%d\n",__FUNCTION__,__LINE__,cmd->duplex, cmd->port ,cmd->autoneg); ++ ++ return 0; ++} ++ ++int MDrv_NOE_ETHTOOL_Get_Settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ mii_ethtool_gset(&ei_local->mii_info, cmd); ++ NOE_MSG_DUMP("%s,%d %d,%d,%d\n",__FUNCTION__,__LINE__,cmd->duplex, cmd->port ,cmd->autoneg); ++ return 0; ++} ++ ++static int _MDrv_NOE_ETHTOOL_MDIO_Read(struct net_device *dev, int phy_id, int location) ++{ ++ unsigned int result; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ MHal_NOE_Read_Mii_Mgr((unsigned int)ei_local->mii_info.phy_id, (unsigned int)location, &result); ++ NOE_MSG_DUMP("\n%s mii.o query= phy_id:%d\n",dev->name, phy_id); ++ NOE_MSG_DUMP("address:%d retval:%x\n", location, result); ++ return (int)result; ++} ++ ++ ++static void _MDrv_NOE_ETHTOOL_MDIO_Write(struct net_device *dev, int phy_id, int location, int value) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ MHal_NOE_Write_Mii_Mgr((unsigned int)ei_local->mii_info.phy_id, (unsigned int)location, (unsigned int)value); ++ NOE_MSG_DUMP("mii.o write= phy_id:%d\n", phy_id); ++ NOE_MSG_DUMP("address:%d value:%x\n", location, value); ++} ++ ++ ++ ++u32 MDrv_NOE_ETHTOOL_Virt_Get_Link(struct net_device *dev) ++{ ++ struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++ struct END_DEVICE *ei_local = netdev_priv(ethtool_dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) ++ return mii_link_ok(&pseudo->mii_info); ++ else ++ return 0; ++} ++ ++ ++int MDrv_NOE_ETHTOOL_Virt_Set_Settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++ struct END_DEVICE *ei_local = netdev_priv(ethtool_dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) ++ mii_ethtool_sset(&pseudo->mii_info, cmd); ++ return 0; ++} ++ ++ ++int MDrv_NOE_ETHTOOL_Virt_Get_Settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++ struct END_DEVICE *ei_local = netdev_priv(ethtool_dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) ++ mii_ethtool_gset(&pseudo->mii_info, cmd); ++ return 0; ++} ++ ++static int _MDrv_NOE_ETHTOOL_MDIO_Virt_Read(struct net_device *dev, int phy_id, int location) ++{ ++ unsigned int result; ++ struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++ struct END_DEVICE *ei_local = netdev_priv(ethtool_dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ MHal_NOE_Read_Mii_Mgr((unsigned int)pseudo->mii_info.phy_id, (unsigned int)location, &result); ++ NOE_MSG_DUMP("%s mii.o query= phy_id:%d,\n", dev->name, phy_id); ++ NOE_MSG_DUMP("address:%d retval:%d\n", location, result); ++ return (int)result; ++ } ++ return 0; ++} ++ ++static void _MDrv_NOE_ETHTOOL_MDIO_Virt_Write(struct net_device *dev, int phy_id, int location, int value) ++{ ++ struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++ struct END_DEVICE *ei_local = netdev_priv(ethtool_dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ MHal_NOE_Write_Mii_Mgr((unsigned int)pseudo->mii_info.phy_id, (unsigned int)location, (unsigned int)value); ++ } ++ ++ NOE_MSG_DUMP("mii.o write= phy_id:%d\n", phy_id); ++ NOE_MSG_DUMP("address:%d value:%d\n)", location, value); ++} ++ ++void MDrv_NOE_ETHTOOL_Init(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ /* store global info */ ++ ethtool_dev = dev; ++ /* init mii structure */ ++ ei_local->mii_info.dev = dev; ++ ei_local->mii_info.mdio_read = _MDrv_NOE_ETHTOOL_MDIO_Read; ++ ei_local->mii_info.mdio_write = _MDrv_NOE_ETHTOOL_MDIO_Write; ++ ei_local->mii_info.phy_id_mask = 0x1f; ++ ei_local->mii_info.reg_num_mask = 0x1f; ++ ei_local->mii_info.supports_gmii = mii_check_gmii_support(&ei_local->mii_info); ++ ++ /* TODO: phy_id: 0~4 */ ++ ei_local->mii_info.phy_id = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR; ++} ++ ++void MDrv_NOE_ETHTOOL_Virt_Init(struct net_device *dev) ++{ ++ struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev); ++ ++ /* init mii structure */ ++ p_pseudo_ad->mii_info.dev = dev; ++ p_pseudo_ad->mii_info.mdio_read = _MDrv_NOE_ETHTOOL_MDIO_Virt_Read; ++ p_pseudo_ad->mii_info.mdio_write = _MDrv_NOE_ETHTOOL_MDIO_Virt_Write; ++ p_pseudo_ad->mii_info.phy_id_mask = 0x1f; ++ p_pseudo_ad->mii_info.reg_num_mask = 0x1f; ++ p_pseudo_ad->mii_info.phy_id = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2; ++ p_pseudo_ad->mii_info.supports_gmii = mii_check_gmii_support(&p_pseudo_ad->mii_info); ++ ++} ++ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_ethtool.h b/drivers/sstar/noe/drv/eth/mdrv_noe_ethtool.h +new file mode 100755 +index 000000000000..be1219b2b7ff +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_ethtool.h +@@ -0,0 +1,43 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_ETHTOOL.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++#ifndef _MDRV_NOE_ETHTOOL_H_ ++#define _MDRV_NOE_ETHTOOL_H_ ++ ++unsigned char MDrv_NOE_ETHTOOL_Get_Phy_Address(void); ++u32 MDrv_NOE_ETHTOOL_Get_Link(struct net_device *dev); ++int MDrv_NOE_ETHTOOL_Get_Settings(struct net_device *dev, struct ethtool_cmd *cmd); ++int MDrv_NOE_ETHTOOL_Set_Settings(struct net_device *dev, struct ethtool_cmd *cmd); ++void MDrv_NOE_ETHTOOL_Init(struct net_device *dev); ++u32 MDrv_NOE_ETHTOOL_Virt_Get_Link(struct net_device *dev); ++int MDrv_NOE_ETHTOOL_Virt_Set_Settings(struct net_device *dev, struct ethtool_cmd *cmd); ++int MDrv_NOE_ETHTOOL_Virt_Get_Settings(struct net_device *dev, struct ethtool_cmd *cmd); ++void MDrv_NOE_ETHTOOL_Virt_Init(struct net_device *dev); ++ ++#endif /* _MDRV_NOE_ETHTOOL_H_ */ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_ioctl.h b/drivers/sstar/noe/drv/eth/mdrv_noe_ioctl.h +new file mode 100755 +index 000000000000..8c7a2a0f9720 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_ioctl.h +@@ -0,0 +1,150 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_IOCTL.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_NOE_IOCTL_H_ ++#define _MDRV_NOE_IOCTL_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mdrv_noe_def.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++/* ioctl commands */ ++#define NOE_SW_IOCTL 0x89F0 ++#define NOE_ESW_REG_READ 0x89F1 ++#define NOE_ESW_REG_WRITE 0x89F2 ++#define NOE_MII_READ 0x89F3 ++#define NOE_MII_WRITE 0x89F4 ++#define NOE_ESW_INGRESS_RATE 0x89F5 ++#define NOE_ESW_EGRESS_RATE 0x89F6 ++#define NOE_ESW_PHY_DUMP 0x89F7 ++#define NOE_QDMA_REG_READ 0x89F8 ++#define NOE_QDMA_REG_WRITE 0x89F9 ++#define NOE_QDMA_QUEUE_MAPPING 0x89FA ++#define NOE_QDMA_READ_CPU_CLK 0x89FB ++#define NOE_MII_READ_CL45 0x89FC ++#define NOE_MII_WRITE_CL45 0x89FD ++#define NOE_QDMA_SFQ_WEB_ENABLE 0x89FE ++#define NOE_SET_LAN_IP 0x89FF ++ ++/* switch ioctl commands */ ++#define SW_IOCTL_SET_EGRESS_RATE 0x0000 ++#define SW_IOCTL_SET_INGRESS_RATE 0x0001 ++#define SW_IOCTL_SET_VLAN 0x0002 ++#define SW_IOCTL_DUMP_VLAN 0x0003 ++#define SW_IOCTL_DUMP_TABLE 0x0004 ++#define SW_IOCTL_ADD_L2_ADDR 0x0005 ++#define SW_IOCTL_DEL_L2_ADDR 0x0006 ++#define SW_IOCTL_ADD_MCAST_ADDR 0x0007 ++#define SW_IOCTL_DEL_MCAST_ADDR 0x0008 ++#define SW_IOCTL_DUMP_MIB 0x0009 ++#define SW_IOCTL_ENABLE_IGMPSNOOP 0x000A ++#define SW_IOCTL_DISABLE_IGMPSNOOP 0x000B ++#define SW_IOCTL_SET_PORT_TRUNKING 0x000C ++#define SW_IOCTL_GET_PORT_TRUNKING 0x000D ++#define SW_IOCTL_SET_PORT_MIRROR 0x000E ++#define SW_IOCTL_GET_PHY_STATUS 0x000F ++#define SW_IOCTL_READ_REG 0x0010 ++#define SW_IOCTL_WRITE_REG 0x0011 ++#define SW_IOCTL_QOS_EN 0x0012 ++#define SW_IOCTL_QOS_SET_TABLE2TYPE 0x0013 ++#define SW_IOCTL_QOS_GET_TABLE2TYPE 0x0014 ++#define SW_IOCTL_QOS_SET_PORT2TABLE 0x0015 ++#define SW_IOCTL_QOS_GET_PORT2TABLE 0x0016 ++#define SW_IOCTL_QOS_SET_PORT2PRI 0x0017 ++#define SW_IOCTL_QOS_GET_PORT2PRI 0x0018 ++#define SW_IOCTL_QOS_SET_DSCP2PRI 0x0019 ++#define SW_IOCTL_QOS_GET_DSCP2PRI 0x001a ++#define SW_IOCTL_QOS_SET_PRI2QUEUE 0x001b ++#define SW_IOCTL_QOS_GET_PRI2QUEUE 0x001c ++#define SW_IOCTL_QOS_SET_QUEUE_WEIGHT 0x001d ++#define SW_IOCTL_QOS_GET_QUEUE_WEIGHT 0x001e ++#define SW_IOCTL_SET_PHY_TEST_MODE 0x001f ++#define SW_IOCTL_GET_PHY_REG 0x0020 ++#define SW_IOCTL_SET_PHY_REG 0x0021 ++#define SW_IOCTL_VLAN_TAG 0x0022 ++ ++ ++ ++#define REG_ESW_WT_MAC_MFC 0x0010 ++#define REG_ESW_ISC 0x0018 ++#define REG_ESW_WT_MAC_ATA1 0x0074 ++#define REG_ESW_WT_MAC_ATA2 0x0078 ++#define REG_ESW_WT_MAC_ATWD 0x007C ++#define REG_ESW_WT_MAC_ATC 0x0080 ++#define REG_ESW_TABLE_TSRA1 0x0084 ++#define REG_ESW_TABLE_TSRA2 0x0088 ++#define REG_ESW_TABLE_ATRD 0x008C ++#define REG_ESW_VLAN_VTCR 0x0090 ++#define REG_ESW_VLAN_VAWD1 0x0094 ++#define REG_ESW_VLAN_VAWD2 0x0098 ++#define REG_ESW_VLAN_ID_BASE 0x0100 ++ ++#define REG_ESW_VLAN_MEMB_BASE 0x0070 ++#define REG_ESW_TABLE_SEARCH 0x0024 ++#define REG_ESW_TABLE_STATUS0 0x0028 ++#define REG_ESW_TABLE_STATUS1 0x002C ++#define REG_ESW_TABLE_STATUS2 0x0030 ++#define REG_ESW_WT_MAC_AD0 0x0034 ++#define REG_ESW_WT_MAC_AD1 0x0038 ++#define REG_ESW_WT_MAC_AD2 0x003C ++ ++/*10/100 phy cal*/ ++#define NOE_VBG_IEXT_CALIBRATION 0x0040 ++#define NOE_TXG_R50_CALIBRATION 0x0041 ++#define NOE_TXG_OFFSET_CALIBRATION 0x0042 ++#define NOE_TXG_AMP_CALIBRATION 0x0043 ++ ++ ++ ++ ++#define REG_ESW_MAX 0x00FC ++#define REG_HQOS_MAX 0x3FFF ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++struct ra_mii_ioctl_data { ++ unsigned int phy_id; ++ unsigned int reg_num; ++ unsigned int val_in; ++ unsigned int val_out; ++ unsigned int port_num; ++ unsigned int dev_addr; ++ unsigned int reg_addr; ++}; ++ ++ ++struct noe_reg { ++ unsigned int off; ++ unsigned int val; ++}; ++ ++#endif /* _MDRV_NOE_IOCTL_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_log.c b/drivers/sstar/noe/drv/eth/mdrv_noe_log.c +new file mode 100755 +index 000000000000..7c517dea3241 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_log.c +@@ -0,0 +1,120 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_LOG.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include "mdrv_noe.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++#define SKB_DUMP_LAYER_II 0 ++#if SKB_DUMP_LAYER_II ++#define SKB_START_OFFSET (-14) /* dump Layer II*/ ++#else ++#define SKB_START_OFFSET (0) /* dump Layer III*/ ++#endif ++ ++#define SKB_END_OFFSET (32) // (40) ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++static struct net_device *_noe_dev = NULL; ++ ++void MDrv_NOE_LOG_Set_Level(unsigned char level) ++{ ++ struct END_DEVICE *ei_local = NULL; ++ ++ if (_noe_dev == NULL) ++ return; ++ ++ ei_local = netdev_priv(_noe_dev); ++ ++ if (ei_local->log_level == level) ++ return; ++ ++ ei_local->log_level = level; ++ NOE_MSG_DBG("Set Log Level = 0x%x \n", ei_local->log_level); ++ if (level >= E_MDRV_NOE_MSG_CTRL_DUMP) { ++ MHal_NOE_Set_DBG(E_NOE_HAL_LOG_DBG); ++ } ++ else { ++ MHal_NOE_Set_DBG(E_NOE_HAL_LOG_NONE); ++ } ++ ++} ++ ++unsigned char MDrv_NOE_LOG_Get_Level(void) ++{ ++ struct END_DEVICE *ei_local = NULL; ++ ++ if (_noe_dev == NULL) ++ return E_MDRV_NOE_MSG_CTRL_NONE; ++ ++ ei_local = netdev_priv(_noe_dev); ++ ++ return ei_local->log_level; ++} ++ ++void MDrv_NOE_LOG_Init(struct net_device *dev) ++{ ++ _noe_dev = dev; ++} ++ ++void MDrv_NOE_LOG_Dump_Skb(struct sk_buff* sk) ++{ ++ int num = sk->len; //(sk->len < SKB_END_OFFSET)? sk->len : SKB_END_OFFSET; ++ unsigned char *i; ++ unsigned int j = 0; ++ NOE_MSG_DUMP("[%s][%d] =========> \n",__FUNCTION__,__LINE__); ++#if 0 ++ NOE_MSG_DUMP("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n", ++ sk->dev? sk->dev->name:"ip stack", sk->len, sk->truesize, ++ skb_headroom(sk),skb_tailroom(sk)); ++#endif ++ NOE_MSG_DUMP("%s: head = 0x%p, data = 0x%p with len %d (%d)\n", ++ sk->dev? sk->dev->name:" ", ++ sk->head, sk->data, sk->len, sk->truesize); ++ for(i = sk->data + SKB_START_OFFSET; i < sk->data + num; i++) { ++ ++ if ((j % 16) == 8) ++ NOE_MSG_DUMP("\t"); ++ if ((j % 16) == 0) ++ NOE_MSG_DUMP("\n"); ++ ++ NOE_MSG_DUMP("%02x ", *(sk->data + j)); ++ j++; ++ } ++ NOE_MSG_DUMP("\n"); ++} ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_log.h b/drivers/sstar/noe/drv/eth/mdrv_noe_log.h +new file mode 100755 +index 000000000000..c323f634b083 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_log.h +@@ -0,0 +1,55 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_LOG.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_NOE_LOG_H_ ++#define _MDRV_NOE_LOG_H_ ++ ++ ++typedef enum { ++ E_MDRV_NOE_MSG_CTRL_NONE = 0, ++ E_MDRV_NOE_MSG_CTRL_ERR, ++ E_MDRV_NOE_MSG_CTRL_DBG, ++ E_MDRV_NOE_MSG_CTRL_DUMP, ++}EN_MDRV_NOE_MSG_CTRL; ++ ++ ++#define MDRV_NOE_MSG(type, format , args...) \ ++ do{ \ ++ if (MDrv_NOE_LOG_Get_Level() >= type) \ ++ { \ ++ printk(format , ##args ); \ ++ } \ ++ }while(0); ++ ++#define NOE_MSG_ERR(format, args...) MDRV_NOE_MSG(E_MDRV_NOE_MSG_CTRL_ERR, format, ##args) ++#define NOE_MSG_DBG(format, args...) MDRV_NOE_MSG(E_MDRV_NOE_MSG_CTRL_DBG, format, ##args) ++#define NOE_MSG_DUMP(format, args...) MDRV_NOE_MSG(E_MDRV_NOE_MSG_CTRL_DUMP, format, ##args) ++#define NOE_MSG_MUST(format, args...) printk(format, ##args) ++ ++ ++void MDrv_NOE_LOG_Set_Level(unsigned char level); ++unsigned char MDrv_NOE_LOG_Get_Level(void); ++void MDrv_NOE_LOG_Init(struct net_device *dev); ++void MDrv_NOE_LOG_Dump_Skb(struct sk_buff* sk); ++#endif /* _MDRV_NOE_LOG_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_lro.c b/drivers/sstar/noe/drv/eth/mdrv_noe_lro.c +new file mode 100755 +index 000000000000..b5fc3829613f +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_lro.c +@@ -0,0 +1,381 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDrv_NOE_Lro.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++ ++#include "mdrv_noe.h" ++#include "mdrv_noe_nat.h" ++#include "mdrv_noe_dma.h" ++#include "mhal_noe_reg.h" ++#include "mhal_noe_lro.h" ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++ ++static int _MDrv_NOE_LRO_Alloc_Mem(struct net_device *dev, int i, int j, int skb_size) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ei_local->netrx_skb_data[i][j] = MDrv_NOE_SkbData_Alloc(skb_size, GFP_KERNEL); ++ if (!ei_local->netrx_skb_data[i][j]) { ++ NOE_MSG_ERR("rx skbuff buffer allocation failed!\n"); ++ return 0; ++ } ++ return 1; ++} ++ ++int MDrv_NOE_LRO_Init(struct net_device *dev) ++{ ++ struct noe_dma_info info; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int skb_size; ++ int i, j; ++ unsigned int sip, dip, lan_ip; ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++ ++ skb_size = SKB_DATA_ALIGN(MAX_LRO_RX_LENGTH + NET_IP_ALIGN) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ ++ /* Initial RX Ring 1 ~ 3 */ ++ for (i = 1; i < MAX_RX_RING_NUM; i++) { ++ //ei_local->rx_ring[i] = dma_alloc_coherent(dev->dev.parent, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring[i], GFP_ATOMIC | __GFP_ZERO); ++ mem_info.length = NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc); ++ snprintf(mem_info.name, 16, "rx_ring%d", i); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ NOE_MSG_ERR("unable to allocate DMEM for %s!! error=%d\n", mem_info.name ,ret); ++ } ++ ei_local->phy_rx_ring[i] = (dma_addr_t)((size_t)mem_info.phys); ++ ei_local->rx_ring[i] = (void *)((size_t)mem_info.kvirt); ++ ++ for (j = 0; j < NUM_LRO_RX_DESC; j++) { ++ if(!_MDrv_NOE_LRO_Alloc_Mem(dev, i, j, skb_size)) { ++ goto no_rx_mem; ++ } ++ ++ memset(&ei_local->rx_ring[i][j], 0, sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring[i][j].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring[i][j].rxd_info2.LS0 = 0; ++ ei_local->rx_ring[i][j].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH); ++ ei_local->rx_ring[i][j].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14); ++ ei_local->rx_ring[i][j].rxd_info1.PDP0 = dma_map_single(dev->dev.parent, ei_local->netrx_skb_data[i][j] + NET_SKB_PAD, MAX_LRO_RX_LENGTH, DMA_FROM_DEVICE); ++ if (unlikely(dma_mapping_error(ei_local->dev, ei_local->rx_ring[i][j].rxd_info1.PDP0))) { ++ NOE_MSG_ERR("[%s]dma_map_single() failed...\n",__FUNCTION__); ++ goto no_rx_mem; ++ } ++ } ++ NOE_MSG_DUMP("\nphy_rx_ring[%d] = 0x%08x, rx_ring[%d] = 0x%p, NUM_LRO_RX_DESC=%d\n", i, (unsigned int)ei_local->phy_rx_ring[i], i, ei_local->rx_ring[i], NUM_LRO_RX_DESC); ++ } ++ ++ info.ring_st.base_adr = (MS_U32) ei_local->phy_rx_ring[3]; ++ info.ring_st.max_cnt = cpu_to_le32((u32)NUM_LRO_RX_DESC); ++ info.ring_st.cpu_idx = cpu_to_le32((u32)(NUM_LRO_RX_DESC - 1)); ++ MHal_NOE_DMA_Init(E_NOE_DMA_PACKET, E_NOE_DIR_RX, E_NOE_RING_NO3, &info); ++ info.ring_st.base_adr = (MS_U32) ei_local->phy_rx_ring[2]; ++ MHal_NOE_DMA_Init(E_NOE_DMA_PACKET, E_NOE_DIR_RX, E_NOE_RING_NO2, &info); ++ info.ring_st.base_adr = (MS_U32) ei_local->phy_rx_ring[1]; ++ MHal_NOE_DMA_Init(E_NOE_DMA_PACKET, E_NOE_DIR_RX, E_NOE_RING_NO1, &info); ++ ++ if (ei_local->features & FE_HW_LRO_FPORT) { ++ MDrv_NOE_UTIL_Str_To_Ip(&sip, "10.10.10.3"); ++ MDrv_NOE_UTIL_Str_To_Ip(&dip, "10.10.10.254"); ++ MHal_NOE_LRO_Set_Ring_Cfg(E_NOE_RING_NO1, sip, 1122, dip, 3344); ++ MHal_NOE_LRO_Set_Ring_Cfg(E_NOE_RING_NO2, sip, 5566, dip, 7788); ++ MHal_NOE_LRO_Set_Ring_Cfg(E_NOE_RING_NO3, sip, 9900, dip, 99); ++ MHal_NOE_LRO_Set_Cfg(); ++ } else { ++ MDrv_NOE_UTIL_Str_To_Ip(&lan_ip, ei_local->lan_ip4_addr); ++ MHal_NOE_LRO_Set_Ip(lan_ip); ++ MHal_NOE_LRO_Set_Auto_Learn_Cfg(); ++ } ++ ++ return 0; ++ ++no_rx_mem: ++ NOE_MSG_ERR("%s fail \n", __FUNCTION__); ++ return -ENOMEM; ++} ++ ++ ++ ++void MDrv_NOE_LRO_Deinit(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int i, j; ++ ++ for (i = 1; i < MAX_RX_RING_NUM; i++) { ++ /* free RX Ring */ ++ //dma_free_coherent(dev->dev.parent, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc), ei_local->rx_ring[i], ei_local->phy_rx_ring[i]); ++ /* free RX data */ ++ for (j = 0; j < NUM_LRO_RX_DESC; j++) { ++ MDrv_NOE_SkbData_Free(ei_local->netrx_skb_data[i][j]); ++ ei_local->netrx_skb_data[i][j] = NULL; ++ } ++ } ++} ++ ++static inline void _MDrv_NOE_LRO_Init_Rx_Desc(struct END_DEVICE *ei_local, struct PDMA_rxdesc *rx_ring, unsigned int rx_ring_no, dma_addr_t dma_addr) ++{ ++ if (rx_ring_no != 0) { ++ /* lro ring */ ++ rx_ring->rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH); ++ rx_ring->rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14); ++ } ++ else{ ++ /* normal ring */ ++ rx_ring->rxd_info2.PLEN0 = MAX_RX_LENGTH; ++ } ++ rx_ring->rxd_info1.PDP0 = dma_addr; ++ rx_ring->rxd_info2.LS0 = 0; ++ rx_ring->rxd_info2.DDONE_bit = 0; ++ ++ memset(&rx_ring->rxd_info3, 0 ,sizeof(struct PDMA_RXD_INFO3_T)); ++ memset(&rx_ring->rxd_info4, 0 ,sizeof(struct PDMA_RXD_INFO4_T)); ++ ++ Chip_Flush_MIU_Pipe(); //L3 ++} ++ ++static int _MDrv_NOE_LRO_Get_Rx_Ring(struct END_DEVICE *ei_local, unsigned int rx_idx[]) ++{ ++ int i; ++ ++ for (i = 0; i < MAX_RX_RING_NUM; i++) { ++ if (ei_local->rx_ring[i][rx_idx[i]].rxd_info2.DDONE_bit == 1){ ++ return i; ++ } ++ } ++ return 0; ++} ++ ++int MDrv_NOE_LRO_Recv(struct net_device *dev, struct napi_struct *napi, int budget) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev); ++ struct sk_buff *rx_skb; ++ struct PDMA_rxdesc *rx_ring, *rx_ring_next; ++ void *rx_data, *rx_data_next, *new_data; ++ unsigned int length = 0; ++ unsigned int rx_ring_no = 0, rx_ring_no_next = 0; ++ unsigned int rx_dma_owner_idx, rx_dma_owner_idx_next; ++ unsigned int rx_dma_owner_lro[MAX_RX_RING_NUM]; ++ unsigned int skb_size, map_size; ++ int rx_processed = 0; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) ++ DEFINE_DMA_ATTRS(attrs); ++#else ++ unsigned long attrs; ++#endif ++ ++ ++ /* get cpu owner indexes of rx rings */ ++ rx_dma_owner_lro[0] = (ei_local->rx_calc_idx[0] + 1) % NUM_RX_DESC; ++ rx_dma_owner_lro[1] = (ei_local->rx_calc_idx[1] + 1) % NUM_LRO_RX_DESC; ++ rx_dma_owner_lro[2] = (ei_local->rx_calc_idx[2] + 1) % NUM_LRO_RX_DESC; ++ rx_dma_owner_lro[3] = (ei_local->rx_calc_idx[3] + 1) % NUM_LRO_RX_DESC; ++ rx_ring_no = _MDrv_NOE_LRO_Get_Rx_Ring(ei_local, rx_dma_owner_lro); ++ rx_dma_owner_idx = rx_dma_owner_lro[rx_ring_no]; ++ rx_ring = &ei_local->rx_ring[rx_ring_no][rx_dma_owner_idx]; ++ rx_data = ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx]; ++ ++ for (;;) { ++ dma_addr_t dma_addr; ++ ++ if ((rx_processed++ > budget) || (rx_ring->rxd_info2.DDONE_bit == 0)) { ++ break; ++ } ++ ++ /* prefetch the next handling RXD */ ++ if (rx_ring_no == 0) { ++ rx_dma_owner_lro[rx_ring_no] = (rx_dma_owner_idx + 1) % NUM_RX_DESC; ++ skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ map_size = MAX_RX_LENGTH; ++ } ++ else { ++ rx_dma_owner_lro[rx_ring_no] = (rx_dma_owner_idx + 1) % NUM_LRO_RX_DESC; ++ skb_size = SKB_DATA_ALIGN(MAX_LRO_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ map_size = MAX_LRO_RX_LENGTH; ++ } ++ ++ rx_ring_no_next = _MDrv_NOE_LRO_Get_Rx_Ring(ei_local, rx_dma_owner_lro); ++ rx_dma_owner_idx_next = rx_dma_owner_lro[rx_ring_no_next]; ++ rx_ring_next = &ei_local->rx_ring[rx_ring_no_next][rx_dma_owner_idx_next]; ++ rx_data_next = ei_local->netrx_skb_data[rx_ring_no_next][rx_dma_owner_idx_next]; ++ prefetch(rx_ring_next); ++ ++ /* We have to check the free memory size is big enough ++ * before pass the packet to cpu ++ */ ++ new_data = MDrv_NOE_SkbData_Alloc(skb_size, GFP_ATOMIC); ++ ++ if (unlikely(!new_data)) { ++ NOE_MSG_ERR("skb not available...\n"); ++ goto skb_err; ++ } ++ ++ //dma_addr = dma_map_single(dev->dev.parent, new_data + NET_SKB_PAD, map_size, DMA_FROM_DEVICE); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) ++ dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);//edie.chen--4.9 not support ++ dma_addr = dma_map_single_attrs(dev->dev.parent, new_data + NET_SKB_PAD, map_size, DMA_FROM_DEVICE, &attrs); //edie.chen--4.9 not support ++#else ++ attrs = DMA_ATTR_SKIP_CPU_SYNC; ++ dma_addr = dma_map_single_attrs(dev->dev.parent, new_data + NET_SKB_PAD, map_size, DMA_FROM_DEVICE, attrs); ++#endif ++ ++ if (unlikely(dma_mapping_error(ei_local->dev, dma_addr))) { ++ NOE_MSG_ERR("[%s]dma_map_single() failed...\n", __func__); ++ MDrv_NOE_SkbData_Free(new_data); ++ goto skb_err; ++ } ++ ++ rx_skb = MDrv_NOE_Skb_Build(rx_data, skb_size); ++ if (unlikely(!rx_skb)) { ++ NOE_MSG_ERR("[%s][%d]build_skb failed\n",__FUNCTION__,__LINE__); ++ dma_unmap_single(dev->dev.parent, dma_addr, map_size, DMA_FROM_DEVICE); ++ MDrv_NOE_SkbData_Free(new_data); ++ NOE_MSG_ERR("call MDrv_NOE_SkbData_Free to free\n"); ++ goto skb_err; ++ } ++ ++ skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN); ++ ++ length = (rx_ring->rxd_info2.PLEN1 << 14) | rx_ring->rxd_info2.PLEN0; ++ ++ dma_unmap_single(dev->dev.parent, rx_ring->rxd_info1.PDP0, length, DMA_FROM_DEVICE); ++ ++ prefetch(rx_skb->data); ++ ++ /* skb processing */ ++ skb_put(rx_skb, length); ++ ++ /* rx packet from GE2 */ ++ if (rx_ring->rxd_info4.SP == 2) { ++ if (ei_local->pseudo_dev) { ++ rx_skb->dev = ei_local->pseudo_dev; ++ rx_skb->protocol = eth_type_trans(rx_skb, ei_local->pseudo_dev); ++ } ++ else { ++ NOE_MSG_ERR("pseudo_dev is still not initialize "); ++ NOE_MSG_ERR("but receive packet from GMAC2\n"); ++ } ++ } ++ else { ++ rx_skb->dev = dev; ++ rx_skb->protocol = eth_type_trans(rx_skb, dev); ++ } ++ ++ /* rx checksum offload */ ++ if (likely(rx_ring->rxd_info4.L4VLD)) ++ rx_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ else ++ rx_skb->ip_summed = CHECKSUM_NONE; ++ ++ if (ei_local->features & FE_HW_NAT) { ++#ifdef CONFIG_NOE_NAT_HW ++ if (IS_VALID_NOE_HWNAT_HOOK_RX) { ++ *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) = *(uint32_t *)&rx_ring->rxd_info4; ++ *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) = *(uint32_t *)&rx_ring->rxd_info4; ++ FOE_ALG_HEAD(rx_skb) = 0; ++ FOE_ALG_TAIL(rx_skb) = 0; ++ FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE; ++ FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE; ++ FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT; ++ FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT; ++ } ++#endif ++ } ++ /* HW LRO aggregation statistics */ ++ if (ei_local->features & FE_HW_LRO_DBG) { ++ MDrv_NOE_LRO_PROC_Update_Stats(rx_ring_no, rx_ring); ++ MDrv_NOE_LRO_PROC_Update_Flush_Stats(rx_ring_no, rx_ring); ++ } ++ ++/* IS_VALID_NOE_HWNAT_HOOK_RX return 1 --> continue ++ * IS_VALID_NOE_HWNAT_HOOK_RX return 0 --> FWD & without netif_rx ++ */ ++#ifdef CONFIG_NOE_NAT_HW ++ if ((IS_NOT_VALID_NOE_HWNAT_HOOK_RX) || (IS_VALID_NOE_HWNAT_HOOK_RX && NOE_HWNAT_HOOK_RX(rx_skb))) { ++#endif ++ if (ei_local->features & FE_INT_NAPI) { ++ /* napi_gro_receive(napi, rx_skb); */ ++ netif_receive_skb(rx_skb); ++ } ++ else { ++ netif_rx(rx_skb); ++ } ++#ifdef CONFIG_NOE_NAT_HW ++ } ++#endif ++ ++ if (rx_ring->rxd_info4.SP == 2) { ++ p_ad->stat.rx_packets++; ++ p_ad->stat.rx_bytes += length; ++ } ++ else { ++ ei_local->stat.rx_packets++; ++ ei_local->stat.rx_bytes += length; ++ } ++ ++ /* Init RX desc. */ ++ _MDrv_NOE_LRO_Init_Rx_Desc(ei_local, rx_ring, rx_ring_no, dma_addr); ++ ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx] = new_data; ++ /* make sure that all changes to the dma ring are flushed before ++ * we continue ++ */ ++ wmb(); ++ MHal_NOE_LRO_Update_Calc_Idx(rx_ring_no, rx_dma_owner_idx); ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx; ++#endif ++ /* use prefetched variable */ ++ rx_dma_owner_idx = rx_dma_owner_idx_next; ++ rx_ring_no = rx_ring_no_next; ++ rx_ring = rx_ring_next; ++ rx_data = rx_data_next; ++ } /* for */ ++ ++ return rx_processed; ++ ++skb_err: ++ /* rx packet from GE2 */ ++ if (rx_ring->rxd_info4.SP == 2) ++ p_ad->stat.rx_dropped++; ++ else ++ ei_local->stat.rx_dropped++; ++ ++ /* Discard the rx packet */ ++ _MDrv_NOE_LRO_Init_Rx_Desc(ei_local, rx_ring, rx_ring_no, rx_ring->rxd_info1.PDP0); ++ MHal_NOE_LRO_Update_Calc_Idx(rx_ring_no, rx_dma_owner_idx); ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx; ++#endif ++ return (budget + 1); ++} ++ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_lro.h b/drivers/sstar/noe/drv/eth/mdrv_noe_lro.h +new file mode 100755 +index 000000000000..951c3d4003ca +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_lro.h +@@ -0,0 +1,38 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_LRO.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_NOE_LRO_H_ ++#define _MDRV_NOE_LRO_H_ ++ ++#if FE_HW_LRO ++int MDrv_NOE_LRO_Init(struct net_device *dev); ++int MDrv_NOE_LRO_Recv(struct net_device *dev, struct napi_struct *napi, int budget); ++void MDrv_NOE_LRO_Deinit(struct net_device *dev); ++#else ++static inline int MDrv_NOE_LRO_Init(struct net_device *dev) {return -ENOMEM;} ++static inline int MDrv_NOE_LRO_Recv(struct net_device *dev, struct napi_struct *napi, int budget) {return (budget + 1);} ++static inline void MDrv_NOE_LRO_Deinit(struct net_device *dev) {} ++#endif ++#endif /* _MDRV_NOE_LRO_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_lro_proc.c b/drivers/sstar/noe/drv/eth/mdrv_noe_lro_proc.c +new file mode 100755 +index 000000000000..52c1b10fe05b +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_lro_proc.c +@@ -0,0 +1,630 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_LRO_PROC.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#elif defined(CONFIG_ARM64) ++#include ++#include ++#endif ++#include ++ ++#include "mdrv_noe.h" ++#include "mdrv_noe_proc.h" ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++#define HW_LRO_RING_NUM 3 ++#define MAX_HW_LRO_AGGR 64 ++#define HW_LRO_AGG_FLUSH (1) ++#define HW_LRO_AGE_FLUSH (2) ++#define HW_LRO_NOT_IN_SEQ_FLUSH (3) ++#define HW_LRO_TIMESTAMP_FLUSH (4) ++#define HW_LRO_NON_RULE_FLUSH (5) ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef int (*LRO_PROC_OPEN) (struct inode *, struct file *); ++typedef int (*LRO_PROC_SET) (int); ++ ++enum { ++ E_LRO_PROC_RING1 = 0, ++ E_LRO_PROC_RING2, ++ E_LRO_PROC_RING3, ++ E_LRO_PROC_STATS, ++ E_LRO_PROC_ATTLB, ++ E_LRO_PROC_MAX, ++}; ++ ++ ++enum { ++ E_AGG_CNT = 0, ++ E_AGG_TIME, ++ E_AGE_TIME, ++ E_BW_THRESHOLD, ++ E_RING_CONTROL, ++}; ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++static int _MDrv_NOE_LRO_PROC_Show_Rx_Ring1(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_LRO_PROC_Show_Rx_Ring2(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_LRO_PROC_Show_Rx_Ring3(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_LRO_PROC_Show_Auto_Tlb(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_LRO_PROC_Show_Stats(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_LRO_PROC_Open_Rx_Ring1(struct inode *inode, struct file *file); ++static int _MDrv_NOE_LRO_PROC_Open_Rx_Ring2(struct inode *inode, struct file *file); ++static int _MDrv_NOE_LRO_PROC_Open_Rx_Ring3(struct inode *inode, struct file *file); ++static int _MDrv_NOE_LRO_PROC_Open_Auto_Tlb(struct inode *inode, struct file *file); ++static int _MDrv_NOE_LRO_PROC_Open_Stats(struct inode *inode, struct file *file); ++static ssize_t _MDrv_NOE_LRO_PROC_Write_Stats(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static ssize_t _MDrv_NOE_LRO_PROC_Write_Auto_Tlb(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_LRO_PROC_Update_Len(unsigned int agg_size); ++static int _MDrv_NOE_LRO_PROC_Set_Agg_Cnt(int par2); ++static int _MDrv_NOE_LRO_PROC_Set_Agg_Time(int par2); ++static int _MDrv_NOE_LRO_PROC_Set_Age_Time(int par2); ++static int _MDrv_NOE_LRO_PROC_Set_Threshold(int par2); ++static int _MDrv_NOE_LRO_PROC_Enable_Ring_Ctrl(int par2); ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++static struct net_device *lro_proc_dev; ++static unsigned int lro_agg_num_cnt[HW_LRO_RING_NUM][MAX_HW_LRO_AGGR + 1]; ++static unsigned int lro_agg_size_cnt[HW_LRO_RING_NUM][16]; ++static unsigned int lro_tot_agg_cnt[HW_LRO_RING_NUM]; ++static unsigned int lro_flush_cnt_tot[HW_LRO_RING_NUM]; ++static unsigned int lro_flush_cnt_agg[HW_LRO_RING_NUM]; ++static unsigned int lro_flush_cnt_age[HW_LRO_RING_NUM]; ++static unsigned int lro_flush_cnt_unseq[HW_LRO_RING_NUM]; ++static unsigned int lro_flush_cnt_timestamp[HW_LRO_RING_NUM]; ++static unsigned int lro_flush_cnt_norule[HW_LRO_RING_NUM]; ++static const LRO_PROC_SET lro_proc_set[] = { ++ [E_AGG_CNT] = _MDrv_NOE_LRO_PROC_Set_Agg_Cnt, ++ [E_AGG_TIME] = _MDrv_NOE_LRO_PROC_Set_Agg_Time, ++ [E_AGE_TIME] = _MDrv_NOE_LRO_PROC_Set_Age_Time, ++ [E_BW_THRESHOLD] = _MDrv_NOE_LRO_PROC_Set_Threshold, ++ [E_RING_CONTROL] = _MDrv_NOE_LRO_PROC_Enable_Ring_Ctrl ++}; ++ ++static struct proc_dir_entry *lro_proc_entry[E_LRO_PROC_MAX] = {NULL, NULL, NULL, NULL, NULL}; ++ ++static const char lro_proc_name[E_LRO_PROC_MAX][16] = { ++ NOE_PROC_LRO_RX_RING1, ++ NOE_PROC_LRO_RX_RING2, ++ NOE_PROC_LRO_RX_RING3, ++ NOE_PROC_HW_LRO_STATS, ++ NOE_PROC_HW_LRO_AUTO_TLB ++}; ++ ++static const struct file_operations lro_file_fops[E_LRO_PROC_MAX] = { ++ [E_LRO_PROC_RING1] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_LRO_PROC_Open_Rx_Ring1, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_LRO_PROC_RING2] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_LRO_PROC_Open_Rx_Ring2, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_LRO_PROC_RING3] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_LRO_PROC_Open_Rx_Ring3, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_LRO_PROC_STATS] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_LRO_PROC_Open_Stats, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_LRO_PROC_Write_Stats, ++ .release = single_release ++ }, ++ [E_LRO_PROC_ATTLB] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_LRO_PROC_Open_Auto_Tlb, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_LRO_PROC_Write_Auto_Tlb, ++ .release = single_release ++ }, ++}; ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// ++//-------------------------------------------------------------------------------------------------- ++ ++static int _MDrv_NOE_LRO_PROC_Set_Agg_Cnt(int par2) ++{ ++ MHal_NOE_LRO_Control(E_NOE_LRO_CTRL_AGG_CNT, par2); ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Set_Agg_Time(int par2) ++{ ++ MHal_NOE_LRO_Control(E_NOE_LRO_CTRL_AGG_TIME, par2); ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Set_Age_Time(int par2) ++{ ++ MHal_NOE_LRO_Control(E_NOE_LRO_CTRL_AGE_TIME, par2); ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Set_Threshold(int par2) ++{ ++ MHal_NOE_LRO_Control(E_NOE_LRO_CTRL_BW_THRESHOLD, par2); ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Enable_Ring_Ctrl(int par2) ++{ ++ MHal_NOE_LRO_Control(E_NOE_LRO_CTRL_SWITCH, (!par2)?NOE_DISABLE:NOE_ENABLE); ++ return 0; ++} ++ ++ ++ ++static int _MDrv_NOE_LRO_PROC_Update_Len(unsigned int agg_size) ++{ ++ int len_idx; ++ ++ if (agg_size > 65000) ++ len_idx = 13; ++ else if (agg_size > 60000) ++ len_idx = 12; ++ else if (agg_size > 55000) ++ len_idx = 11; ++ else if (agg_size > 50000) ++ len_idx = 10; ++ else if (agg_size > 45000) ++ len_idx = 9; ++ else if (agg_size > 40000) ++ len_idx = 8; ++ else if (agg_size > 35000) ++ len_idx = 7; ++ else if (agg_size > 30000) ++ len_idx = 6; ++ else if (agg_size > 25000) ++ len_idx = 5; ++ else if (agg_size > 20000) ++ len_idx = 4; ++ else if (agg_size > 15000) ++ len_idx = 3; ++ else if (agg_size > 10000) ++ len_idx = 2; ++ else if (agg_size > 5000) ++ len_idx = 1; ++ else ++ len_idx = 0; ++ ++ return len_idx; ++} ++ ++void MDrv_NOE_LRO_PROC_Update_Flush_Stats(unsigned int ring_num, struct PDMA_rxdesc *rx_ring) ++{ ++ unsigned int flush_reason = rx_ring->rxd_info2.REV; ++ ++ if ((ring_num > 0) && (ring_num < 4)) { ++ if ((flush_reason & 0x7) == HW_LRO_AGG_FLUSH) ++ lro_flush_cnt_agg[ring_num - 1]++; ++ else if ((flush_reason & 0x7) == HW_LRO_AGE_FLUSH) ++ lro_flush_cnt_age[ring_num - 1]++; ++ else if ((flush_reason & 0x7) == HW_LRO_NOT_IN_SEQ_FLUSH) ++ lro_flush_cnt_unseq[ring_num - 1]++; ++ else if ((flush_reason & 0x7) == HW_LRO_TIMESTAMP_FLUSH) ++ lro_flush_cnt_timestamp[ring_num - 1]++; ++ else if ((flush_reason & 0x7) == HW_LRO_NON_RULE_FLUSH) ++ lro_flush_cnt_norule[ring_num - 1]++; ++ } ++} ++ ++void MDrv_NOE_LRO_PROC_Update_Stats(unsigned int ring_num, struct PDMA_rxdesc *rx_ring) ++{ ++ unsigned int agg_cnt = rx_ring->rxd_info2.LRO_AGG_CNT; ++ unsigned int agg_size = (rx_ring->rxd_info2.PLEN1 << 14) | rx_ring->rxd_info2.PLEN0; ++ ++ if ((ring_num > 0) && (ring_num < 4)) { ++ lro_agg_size_cnt[ring_num - 1][_MDrv_NOE_LRO_PROC_Update_Len(agg_size)]++; ++ lro_agg_num_cnt[ring_num - 1][agg_cnt]++; ++ lro_flush_cnt_tot[ring_num - 1]++; ++ lro_tot_agg_cnt[ring_num - 1] += agg_cnt; ++ } ++} ++ ++void _MDrv_NOE_LRO_PROC_Dump_Auto_Tlb(struct seq_file *seq, unsigned int index) ++{ ++ struct lro_tbl info; ++ struct PDMA_LRO_AUTO_TLB_INFO pdma_lro_auto_tlb; ++ ++ MHAL_NOE_LRO_Get_Table(index, &info); ++ if (info.valid == FALSE) { ++ return; ++ } ++ memcpy(&pdma_lro_auto_tlb, &(info.tlb_info), sizeof(struct PDMA_LRO_AUTO_TLB_INFO)); ++ ++ if (index >= 4) ++ seq_printf(seq, "\n===== TABLE Entry: %d (Act) =====\n", index); ++ else ++ seq_printf(seq, "\n===== TABLE Entry: %d (LRU) =====\n", index); ++ if (pdma_lro_auto_tlb.auto_tlb_info8.IPV4) { ++ seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv4)\n", ++ pdma_lro_auto_tlb.auto_tlb_info4.SIP3, ++ pdma_lro_auto_tlb.auto_tlb_info3.SIP2, ++ pdma_lro_auto_tlb.auto_tlb_info2.SIP1, ++ pdma_lro_auto_tlb.auto_tlb_info1.SIP0); ++ } ++ else { ++ seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv6)\n", ++ pdma_lro_auto_tlb.auto_tlb_info4.SIP3, ++ pdma_lro_auto_tlb.auto_tlb_info3.SIP2, ++ pdma_lro_auto_tlb.auto_tlb_info2.SIP1, ++ pdma_lro_auto_tlb.auto_tlb_info1.SIP0); ++ } ++ seq_printf(seq, "DIP_ID = %d\n", ++ pdma_lro_auto_tlb.auto_tlb_info8.DIP_ID); ++ seq_printf(seq, "TCP SPORT = %d | TCP DPORT = %d\n", ++ pdma_lro_auto_tlb.auto_tlb_info0.STP, ++ pdma_lro_auto_tlb.auto_tlb_info0.DTP); ++ seq_printf(seq, "VLAN_VID_VLD = %d\n", ++ pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID_VLD); ++ seq_printf(seq, "VLAN1 = %d | VLAN2 = %d | VLAN3 = %d | VLAN4 =%d\n", ++ (pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 & 0xfff), ++ ((pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 >> 12) & 0xfff), ++ ((pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID1 << 8) | ++ ((pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 >> 24) ++ & 0xfff)), ++ ((pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID1 >> 4) & 0xfff)); ++ seq_printf(seq, "TPUT = %d | FREQ = %d\n", pdma_lro_auto_tlb.auto_tlb_info7.DW_LEN, pdma_lro_auto_tlb.auto_tlb_info6.CNT); ++ seq_printf(seq, "PRIORITY = %d\n", info.priority); ++ ++} ++ ++static ssize_t _MDrv_NOE_LRO_PROC_Write_Auto_Tlb(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ char buf[32]; ++ char *p_buf; ++ int len = count; ++ long x = 0, y = 0; ++ char *p_token = NULL; ++ char *p_delimiter = " \t"; ++ int ret; ++ ++ NOE_MSG_DUMP("[hw_lro_auto_tlb_write]write parameter len = %d\n\r", (int)len); ++ if (len >= sizeof(buf)) { ++ NOE_MSG_ERR("input handling fail!\n"); ++ len = sizeof(buf) - 1; ++ return -1; ++ } ++ ++ if (copy_from_user(buf, buffer, len)) ++ return -EFAULT; ++ ++ buf[len] = '\0'; ++ NOE_MSG_DUMP("[hw_lro_auto_tlb_write]write parameter data = %s\n\r", buf); ++ ++ p_buf = buf; ++ p_token = strsep(&p_buf, p_delimiter); ++ if (!p_token) ++ x = 0; ++ else ++ ret = kstrtol(p_token, 10, &x); ++ ++ p_token = strsep(&p_buf, "\t\n "); ++ if (p_token) { ++ ret = kstrtol(p_token, 10, &y); ++ NOE_MSG_DUMP("y = %ld\n\r", y); ++ } ++ ++ if (lro_proc_set[x] && ++ (ARRAY_SIZE(lro_proc_set) > x)) { ++ (*lro_proc_set[x]) (y); ++ } ++ ++ return count; ++} ++ ++static ssize_t _MDrv_NOE_LRO_PROC_Write_Stats(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ memset(lro_agg_num_cnt, 0, sizeof(lro_agg_num_cnt)); ++ memset(lro_agg_size_cnt, 0, sizeof(lro_agg_size_cnt)); ++ memset(lro_tot_agg_cnt, 0, sizeof(lro_tot_agg_cnt)); ++ memset(lro_flush_cnt_tot, 0, sizeof(lro_flush_cnt_tot)); ++ memset(lro_flush_cnt_agg, 0, sizeof(lro_flush_cnt_agg)); ++ memset(lro_flush_cnt_age, 0, sizeof(lro_flush_cnt_age)); ++ memset(lro_flush_cnt_unseq, 0, sizeof(lro_flush_cnt_unseq)); ++ memset(lro_flush_cnt_timestamp, 0, sizeof(lro_flush_cnt_timestamp)); ++ memset(lro_flush_cnt_norule, 0, sizeof(lro_flush_cnt_norule)); ++ NOE_MSG_DUMP("clear lro cnt table\n"); ++ return count; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Show_Auto_Tlb(struct seq_file *seq, void *offset) ++{ ++ int i; ++ struct lro_ctrl info; ++ ++ if (MDrv_NOE_LOG_Get_Level() >= E_MDRV_NOE_MSG_CTRL_DUMP) { ++ seq_puts(seq, "Usage of /proc/" NOE_PROC_DIR "/hw_lro_auto_tlb:\n"); ++ seq_puts(seq, "echo [function] [setting] > /proc/" NOE_PROC_DIR "/hw_lro_auto_tlb\n"); ++ seq_puts(seq, "Functions:\n"); ++ seq_puts(seq, "[0] = _MDrv_NOE_LRO_PROC_Set_Agg_Cnt\n"); ++ seq_puts(seq, "[1] = _MDrv_NOE_LRO_PROC_Set_Agg_Time\n"); ++ seq_puts(seq, "[2] = _MDrv_NOE_LRO_PROC_Set_Age_Time\n"); ++ seq_puts(seq, "[3] = _MDrv_NOE_LRO_PROC_Set_Threshold\n"); ++ seq_puts(seq, "[4] = _MDrv_NOE_LRO_PROC_Enable_Ring_Ctrl\n\n"); ++ } ++ ++ /* Read valid entries of the auto-learn table */ ++ seq_printf(seq, "HW LRO Auto-learn Table:\n"); ++ ++ for (i = (MHAL_NOE_MAX_ENTRIES_IN_LRO_TABLE - 1); i >= 0; i--) { ++ _MDrv_NOE_LRO_PROC_Dump_Auto_Tlb(seq, i); ++ } ++ ++ /* Read the agg_time/age_time/agg_cnt of LRO rings */ ++ seq_puts(seq, "\nHW LRO Ring Settings\n"); ++ for (i = E_NOE_RING_NO1; i <= E_NOE_RING_NO3; i++) { ++ MHAL_NOE_LRO_Get_Control(i, &info); ++ seq_printf(seq, "Ring[%d]: MAX_AGG_CNT=%d, AGG_TIME=%d, AGE_TIME=%d, Threshold=%d\n", i, info.agg_cnt, info.agg_time, info.age_time, info.threshold); ++ } ++ ++ seq_puts(seq, "\n"); ++ ++ return 0; ++} ++ ++ ++ ++static int _MDrv_NOE_LRO_PROC_Open_Auto_Tlb(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_LRO_PROC_Show_Auto_Tlb, NULL); ++} ++ ++ ++static int _MDrv_NOE_LRO_PROC_Show_Stats(struct seq_file *seq, void *offset) ++{ ++ int i; ++ struct END_DEVICE *ei_local = netdev_priv(lro_proc_dev); ++ ++ seq_puts(seq, "HW LRO statistic dump:\n"); ++ ++ /* Agg number count */ ++ seq_puts(seq, "Cnt: RING1 | RING2 | RING3 | Total\n"); ++ for (i = 0; i <= MAX_HW_LRO_AGGR; i++) { ++ seq_printf(seq, " %d : %d %d %d %d\n", ++ i, lro_agg_num_cnt[0][i], ++ lro_agg_num_cnt[1][i], lro_agg_num_cnt[2][i], ++ lro_agg_num_cnt[0][i] + lro_agg_num_cnt[1][i] + ++ lro_agg_num_cnt[2][i]); ++ } ++ ++ /* Total agg count */ ++ seq_puts(seq, "Total agg: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, " %d %d %d %d\n", ++ lro_tot_agg_cnt[0], lro_tot_agg_cnt[1], ++ lro_tot_agg_cnt[2], ++ lro_tot_agg_cnt[0] + lro_tot_agg_cnt[1] + ++ lro_tot_agg_cnt[2]); ++ ++ /* Total flush count */ ++ seq_puts(seq, "Total flush: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, " %d %d %d %d\n", ++ lro_flush_cnt_tot[0], lro_flush_cnt_tot[1], ++ lro_flush_cnt_tot[2], ++ lro_flush_cnt_tot[0] + lro_flush_cnt_tot[1] + ++ lro_flush_cnt_tot[2]); ++ ++ /* Avg agg count */ ++ seq_puts(seq, "Avg agg: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, " %d %d %d %d\n", ++ (lro_flush_cnt_tot[0]) ? lro_tot_agg_cnt[0] / lro_flush_cnt_tot[0] : 0, ++ (lro_flush_cnt_tot[1]) ? lro_tot_agg_cnt[1] / lro_flush_cnt_tot[1] : 0, ++ (lro_flush_cnt_tot[2]) ? lro_tot_agg_cnt[2] / lro_flush_cnt_tot[2] : 0, ++ (lro_flush_cnt_tot[0] + lro_flush_cnt_tot[1] + lro_flush_cnt_tot[2]) ? ((lro_tot_agg_cnt[0] + lro_tot_agg_cnt[1] + lro_tot_agg_cnt[2]) / ++ (lro_flush_cnt_tot[0] + lro_flush_cnt_tot[1] + lro_flush_cnt_tot[2])) : 0); ++ ++ /* Statistics of aggregation size counts */ ++ seq_puts(seq, "HW LRO flush pkt len:\n"); ++ seq_puts(seq, " Length | RING1 | RING2 | RING3 | Total\n"); ++ for (i = 0; i < 15; i++) { ++ seq_printf(seq, "%d~%d: %d %d %d %d\n", i * 5000, ++ (i + 1) * 5000, lro_agg_size_cnt[0][i], ++ lro_agg_size_cnt[1][i], lro_agg_size_cnt[2][i], ++ lro_agg_size_cnt[0][i] + ++ lro_agg_size_cnt[1][i] + ++ lro_agg_size_cnt[2][i]); ++ } ++ ++ /* CONFIG_NOE_HW_LRO_REASON_DBG */ ++ if (ei_local->features & FE_HW_LRO_DBG) { ++ seq_puts(seq, "Flush reason: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, "AGG timeout: %d %d %d %d\n", ++ lro_flush_cnt_agg[0], lro_flush_cnt_agg[1], ++ lro_flush_cnt_agg[2], ++ (lro_flush_cnt_agg[0] + lro_flush_cnt_agg[1] + ++ lro_flush_cnt_agg[2]) ++ ); ++ seq_printf(seq, "AGE timeout: %d %d %d %d\n", ++ lro_flush_cnt_age[0], lro_flush_cnt_age[1], ++ lro_flush_cnt_age[2], ++ (lro_flush_cnt_age[0] + lro_flush_cnt_age[1] + ++ lro_flush_cnt_age[2]) ++ ); ++ seq_printf(seq, "Not in-sequence: %d %d %d %d\n", ++ lro_flush_cnt_unseq[0], lro_flush_cnt_unseq[1], ++ lro_flush_cnt_unseq[2], ++ (lro_flush_cnt_unseq[0] + lro_flush_cnt_unseq[1] + ++ lro_flush_cnt_unseq[2]) ++ ); ++ seq_printf(seq, "Timestamp: %d %d %d %d\n", ++ lro_flush_cnt_timestamp[0], ++ lro_flush_cnt_timestamp[1], ++ lro_flush_cnt_timestamp[2], ++ (lro_flush_cnt_timestamp[0] + ++ lro_flush_cnt_timestamp[1] + ++ lro_flush_cnt_timestamp[2]) ++ ); ++ seq_printf(seq, "No LRO rule: %d %d %d %d\n", ++ lro_flush_cnt_norule[0], ++ lro_flush_cnt_norule[1], ++ lro_flush_cnt_norule[2], ++ (lro_flush_cnt_norule[0] + ++ lro_flush_cnt_norule[1] + ++ lro_flush_cnt_norule[2]) ++ ); ++ } ++ ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_LRO_PROC_Read_Ring(struct seq_file *seq, void *offset, struct PDMA_rxdesc *rx_ring_p) ++{ ++ int i = 0; ++ ++ for (i = 0; i < NUM_LRO_RX_DESC; i++) { ++ seq_printf(seq, "%4d: %08x %08x %08x %08x\n", i, ++ *(int *)&rx_ring_p[i].rxd_info1, ++ *(int *)&rx_ring_p[i].rxd_info2, ++ *(int *)&rx_ring_p[i].rxd_info3, ++ *(int *)&rx_ring_p[i].rxd_info4); ++ } ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Open_Stats(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_LRO_PROC_Show_Stats, NULL); ++} ++ ++static int _MDrv_NOE_LRO_PROC_Show_Rx_Ring1(struct seq_file *seq, void *offset) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(lro_proc_dev); ++ _MDrv_NOE_LRO_PROC_Read_Ring(seq, offset, ei_local->rx_ring[1]); ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Show_Rx_Ring2(struct seq_file *seq, void *offset) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(lro_proc_dev); ++ _MDrv_NOE_LRO_PROC_Read_Ring(seq, offset, ei_local->rx_ring[2]); ++ return 0; ++} ++ ++static int _MDrv_NOE_LRO_PROC_Show_Rx_Ring3(struct seq_file *seq, void *offset) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(lro_proc_dev); ++ _MDrv_NOE_LRO_PROC_Read_Ring(seq, offset, ei_local->rx_ring[3]); ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_LRO_PROC_Open_Rx_Ring1(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_LRO_PROC_Show_Rx_Ring1, NULL); ++} ++ ++static int _MDrv_NOE_LRO_PROC_Open_Rx_Ring2(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_LRO_PROC_Show_Rx_Ring2, NULL); ++} ++ ++static int _MDrv_NOE_LRO_PROC_Open_Rx_Ring3(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_LRO_PROC_Show_Rx_Ring3, NULL); ++} ++ ++int MDrv_NOE_LRO_PROC_Init(struct proc_dir_entry *proc_reg_dir, struct net_device *dev) ++{ ++ unsigned char i = 0; ++ lro_proc_dev = dev; ++ for (i = 0; i < E_LRO_PROC_MAX; i++){ ++ lro_proc_entry[i] = proc_create(lro_proc_name[i], 0, proc_reg_dir, &lro_file_fops[i]); ++ if (!lro_proc_entry[i]) ++ NOE_MSG_ERR("!! FAIL to create %s PROC !!\n", lro_proc_name[i]); ++ } ++ return 0; ++} ++ ++void MDrv_NOE_LRO_PROC_Exit(struct proc_dir_entry *proc_reg_dir) ++{ ++ unsigned char i = 0; ++ for (i = 0; i < E_LRO_PROC_MAX; i++){ ++ if (lro_proc_entry[i]) ++ remove_proc_entry(lro_proc_name[i], proc_reg_dir); ++ lro_proc_entry[i] = NULL; ++ } ++} ++ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_mac.c b/drivers/sstar/noe/drv/eth/mdrv_noe_mac.c +new file mode 100755 +index 000000000000..d7248a515d96 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_mac.c +@@ -0,0 +1,200 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#elif defined(CONFIG_ARM64) ++#include ++#include ++#endif ++ ++ ++#include "mdrv_types.h" ++ ++#include "irqs.h" ++#include "mdrv_noe.h" ++#include "mdrv_noe_phy.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Variable and Functions ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++static void _MDrv_NOE_MAC_Set_Link(struct END_DEVICE *ei_local) ++{ ++ MS_BOOL bAnSupported = MHal_NOE_Support_Auto_Polling(); ++ struct st_drv_phy_config phy_cfg[E_NOE_GE_MAC_MAX]; ++ phy_cfg[E_NOE_GE_MAC1].ge = E_NOE_GE_MAC1; ++ phy_cfg[E_NOE_GE_MAC2].ge = E_NOE_GE_MAC2; ++ ++ if(ei_local->architecture & GE1_RGMII_AN) { ++ phy_cfg[E_NOE_GE_MAC1].mii_force_mode = (bAnSupported == TRUE)?NOE_DISABLE:NOE_ENABLE; ++ if (bAnSupported == FALSE) { ++ phy_cfg[E_NOE_GE_MAC1].speed = E_NOE_SPEED_1000; ++ phy_cfg[E_NOE_GE_MAC1].duplex = E_NOE_DUPLEX_FULL; ++ } ++ if (phy_cfg[E_NOE_GE_MAC1].mii_force_mode == NOE_DISABLE) { ++ phy_cfg[E_NOE_GE_MAC1].speed = E_NOE_SPEED_INVALID; ++ phy_cfg[E_NOE_GE_MAC1].duplex = E_NOE_DUPLEX_INVALID; ++ } ++ #if defined(CONFIG_NOE_FPGA_VERIFY) || defined(CONFIG_MSTAR_ARM_BD_FPGA) ++ phy_cfg[E_NOE_GE_MAC1].mii_force_mode = NOE_ENABLE; ++ phy_cfg[E_NOE_GE_MAC1].speed = FPGA_NOE_PHY_SPEED; ++ phy_cfg[E_NOE_GE_MAC1].duplex = FPGA_NOE_PHY_DUPLEX; ++ #endif /* CONFIG_NOE_FPGA_VERIFY */ ++ } ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ if (ei_local->architecture & GE2_RGMII_AN) { ++ #ifdef CONFIG_MDIO_IC1819 ++ phy_cfg[E_NOE_GE_MAC2].mii_force_mode = NOE_ENABLE; ++ if (NOE_ENABLE) ++ #else ++ phy_cfg[E_NOE_GE_MAC2].mii_force_mode = (bAnSupported == TRUE)?NOE_DISABLE:NOE_ENABLE; ++ if (bAnSupported == FALSE) ++ #endif ++ { ++ phy_cfg[E_NOE_GE_MAC2].speed = E_NOE_SPEED_1000; ++ phy_cfg[E_NOE_GE_MAC2].duplex = E_NOE_DUPLEX_FULL; ++ } ++ if (phy_cfg[E_NOE_GE_MAC2].mii_force_mode == NOE_DISABLE) { ++ phy_cfg[E_NOE_GE_MAC2].speed = E_NOE_SPEED_INVALID; ++ phy_cfg[E_NOE_GE_MAC2].duplex = E_NOE_DUPLEX_INVALID; ++ } ++ #if defined(CONFIG_NOE_FPGA_VERIFY) || defined(CONFIG_MSTAR_ARM_BD_FPGA) ++ phy_cfg[E_NOE_GE_MAC2].mii_force_mode = NOE_ENABLE; ++ phy_cfg[E_NOE_GE_MAC2].speed = FPGA_NOE_PHY_SPEED; ++ phy_cfg[E_NOE_GE_MAC2].duplex = FPGA_NOE_PHY_DUPLEX; ++ #endif /* CONFIG_NOE_FPGA_VERIFY */ ++ } ++ } ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ MDrv_NOE_PHY_Set_Config(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, &phy_cfg[E_NOE_GE_MAC2]); ++ MHal_NOE_Force_Link_Mode(E_NOE_GE_MAC2, phy_cfg[E_NOE_GE_MAC2].speed, phy_cfg[E_NOE_GE_MAC2].duplex); ++ } ++ ++ if (ei_local->architecture & GE1_RGMII_AN) { ++ MDrv_NOE_PHY_Set_Config(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, &phy_cfg[E_NOE_GE_MAC1]); ++ MHal_NOE_Force_Link_Mode(E_NOE_GE_MAC1, phy_cfg[E_NOE_GE_MAC1].speed, phy_cfg[E_NOE_GE_MAC1].duplex); ++ } ++ ++ if (bAnSupported == TRUE) { ++ if ((phy_cfg[E_NOE_GE_MAC1].mii_force_mode != NOE_ENABLE) || (phy_cfg[E_NOE_GE_MAC2].mii_force_mode != NOE_ENABLE)) ++ MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ else ++ MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++} ++ ++ ++void MDrv_NOE_MAC_Init(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ _MDrv_NOE_MAC_Set_Link(ei_local); ++} ++ ++ ++void MDrv_NOE_MAC_Detect_Link_Status(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev); ++ struct noe_mac_link_status status; ++ ++ ++ if (MHal_NOE_Get_Link_Intr_Status()) { ++ MHal_NOE_Disable_Link_Intr(); ++ MHal_NOE_MAC_Get_Link_Status(E_NOE_GE_MAC1, &status); ++ ++ if (!netif_carrier_ok(dev)) { ++ if (status.link_up == TRUE) ++ netif_carrier_on(dev); ++ } ++ else { ++ if (status.link_up == FALSE) ++ netif_carrier_off(dev); ++ } ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ MHal_NOE_MAC_Get_Link_Status(E_NOE_GE_MAC2, &status); ++ if (!netif_carrier_ok(ei_local->pseudo_dev)) { ++ if (status.link_up == TRUE) ++ netif_carrier_on(ei_local->pseudo_dev); ++ } ++ else { ++ if (status.link_up == FALSE) ++ netif_carrier_off(ei_local->pseudo_dev); ++ } ++ } ++ MHal_NOE_Enable_Link_Intr(); ++ } ++ ++} ++ ++ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_mac.h b/drivers/sstar/noe/drv/eth/mdrv_noe_mac.h +new file mode 100755 +index 000000000000..d6e48269fff2 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_mac.h +@@ -0,0 +1,32 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_MAC.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MDRV_NOE_MAC_H_ ++#define _MDRV_NOE_MAC_H_ ++void MDrv_NOE_MAC_Init(struct net_device *dev); ++void MDrv_NOE_MAC_Detect_Link_Status(struct net_device *dev); ++#endif /* _MDRV_NOE_MAC_H_ */ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_nat.h b/drivers/sstar/noe/drv/eth/mdrv_noe_nat.h +new file mode 100755 +index 000000000000..c56f641762ab +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_nat.h +@@ -0,0 +1,58 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_NOE_NAT_H_ ++#define _MDRV_NOE_NAT_H_ ++ ++#ifdef CONFIG_NOE_NAT_HW ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include "mdrv_hwnat.h" ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++extern int (*noe_nat_hook_rx)(struct sk_buff *skb); ++extern int (*noe_nat_hook_tx)(struct sk_buff *skb, int gmac_no); ++#define NOE_HWNAT_HOOK_RX(skb) noe_nat_hook_rx(skb) ++#define NOE_HWNAT_HOOK_TX(skb,no) noe_nat_hook_tx(skb, no) ++#define IS_VALID_NOE_HWNAT_HOOK_RX (noe_nat_hook_rx != NULL) ++#define IS_VALID_NOE_HWNAT_HOOK_TX (noe_nat_hook_tx != NULL) ++#define IS_NOT_VALID_NOE_HWNAT_HOOK_RX (noe_nat_hook_rx == NULL) ++#define IS_NOT_VALID_NOE_HWNAT_HOOK_TX (noe_nat_hook_tx == NULL) ++#define NOE_HWNAT_HOOK_RX_INIT (noe_nat_hook_rx = NULL) ++#define NOE_HWNAT_HOOK_TX_INIT (noe_nat_hook_tx = NULL) ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++ ++#endif /* CONFIG_NOE_NAT_HW */ ++#endif /* _MDRV_NOE_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_pdma.c b/drivers/sstar/noe/drv/eth/mdrv_noe_pdma.c +new file mode 100755 +index 000000000000..d303372da486 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_pdma.c +@@ -0,0 +1,696 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDrv_NOE_PDMA.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include "mdrv_noe.h" ++#include "mdrv_noe_nat.h" ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++ ++int MDrv_NOE_PDMA_Init_Rx(struct net_device *dev) ++{ ++ int i; ++ unsigned int skb_size; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct noe_dma_info dma_info; ++ ++ skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ ++ /* Initial RX Ring 0 */ ++#if 0 ++ ei_local->rx_ring[0] = dma_alloc_coherent(dev->dev.parent, NUM_RX_DESC *sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring[0], GFP_ATOMIC | __GFP_ZERO); ++#else ++{ ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++ mem_info.length = NUM_RX_DESC *sizeof(struct PDMA_rxdesc); ++ strcpy(mem_info.name, "rx_ring0"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ NOE_MSG_ERR("unable to allocate DMEM for %s!! error=%d\n", mem_info.name ,ret); ++ } ++ ei_local->phy_rx_ring[0] = (dma_addr_t)((size_t)mem_info.phys); ++ ei_local->rx_ring[0] = (void *)((size_t)mem_info.kvirt); ++} ++#endif ++ ++ NOE_MSG_DBG("[PKT_RX_DESC] phy_rx_ring[0] = 0x%08x, rx_ring[0] = 0x%p\n", (unsigned int)ei_local->phy_rx_ring[0], (void *)ei_local->rx_ring[0]); ++ ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ ei_local->netrx_skb_data[0][i] = MDrv_NOE_SkbData_Alloc(skb_size, GFP_KERNEL); ++ if (!ei_local->netrx_skb_data[0][i]) { ++ NOE_MSG_ERR("rx skbuff buffer allocation failed!"); ++ goto no_rx_mem; ++ } ++ ++ memset(&ei_local->rx_ring[0][i], 0, sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring[0][i].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring[0][i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring[0][i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++ ei_local->rx_ring[0][i].rxd_info1.PDP0 = dma_map_single(dev->dev.parent, ei_local->netrx_skb_data[0][i] + NET_SKB_PAD, MAX_RX_LENGTH, DMA_FROM_DEVICE); ++ ++ if (unlikely(dma_mapping_error(ei_local->dev, ei_local->rx_ring[0][i].rxd_info1.PDP0))) { ++ NOE_MSG_ERR("[%s]dma_map_single() failed...\n", __func__); ++ goto no_rx_mem; ++ } ++ NOE_MSG_DUMP("va=0x%p ,pa =0x%x \n", (ei_local->netrx_skb_data[0][i] + NET_SKB_PAD), ei_local->rx_ring[0][i].rxd_info1.PDP0); ++ } ++ Chip_Flush_MIU_Pipe(); //L3 ++ ++ /* Tell the adapter where the RX rings are located. */ ++ dma_info.ring_st.base_adr = (MS_U32)ei_local->phy_rx_ring[0]; ++ dma_info.ring_st.max_cnt = cpu_to_le32((u32)NUM_RX_DESC); ++ dma_info.ring_st.cpu_idx = cpu_to_le32((u32)(NUM_RX_DESC - 1)); ++ ++ MHal_NOE_DMA_Init(E_NOE_DMA_PACKET, E_NOE_DIR_RX, E_NOE_RING_NO0, &dma_info); ++ return 0; ++ ++no_rx_mem: ++ return -ENOMEM; ++} ++ ++int MDrv_NOE_PDMA_Init_Tx(struct net_device *dev) ++{ ++ int i; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct noe_dma_info dma_info; ++ for (i = 0; i < NUM_TX_DESC; i++) ++ ei_local->skb_free[i] = 0; ++ ++ ei_local->tx_ring_full = 0; ++ ei_local->free_idx = 0; ++ ei_local->tx_ring0 = dma_alloc_coherent(dev->dev.parent, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0, GFP_ATOMIC | __GFP_ZERO); ++ NOE_MSG_DBG("[PKT][TX_DESC] phy_tx_ring = 0x%08x, tx_ring = 0x%p\n", (unsigned int)ei_local->phy_tx_ring0, (void *)ei_local->tx_ring0); ++ ++ for (i = 0; i < NUM_TX_DESC; i++) { ++ memset(&ei_local->tx_ring0[i], 0, sizeof(struct PDMA_txdesc)); ++ ei_local->tx_ring0[i].txd_info2.LS0_bit = 1; ++ ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1; ++ } ++ ++ dma_info.ring_st.base_adr = (MS_U32)ei_local->phy_tx_ring0; ++ dma_info.ring_st.max_cnt = cpu_to_le32((MS_U32)NUM_TX_DESC); ++ dma_info.ring_st.cpu_idx = 0; ++ MHal_NOE_DMA_Init(E_NOE_DMA_PACKET, E_NOE_DIR_TX, E_NOE_RING_NO0, &dma_info); ++ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ ei_local->tx_cpu_owner_idx0 = 0; ++#endif ++ return 0; ++} ++ ++void MDrv_NOE_PDMA_Deinit_Rx(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int i; ++ ++ /* free RX Ring */ ++ ++ //if (ei_local->rx_ring[0]) ++ // dma_free_coherent(dev->dev.parent, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), ei_local->rx_ring[0], ei_local->phy_rx_ring[0]); ++ /* free RX data */ ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ if (ei_local->netrx_skb_data[0][i]) { ++ MDrv_NOE_SkbData_Free(ei_local->netrx_skb_data[0][i]); ++ ei_local->netrx_skb_data[0][i] = NULL; ++ } ++ } ++} ++ ++void MDrv_NOE_PDMA_Deinit_Tx(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int i; ++ ++ /* free TX Ring */ ++ if (ei_local->tx_ring0) ++ dma_free_coherent(dev->dev.parent, NUM_TX_DESC * sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0); ++ ++ /* free TX data */ ++ for (i = 0; i < NUM_TX_DESC; i++) { ++ if ((ei_local->skb_free[i] != 0) && (ei_local->skb_free[i] != (struct sk_buff *)0xFFFFFFFF)) ++ dev_kfree_skb_any(ei_local->skb_free[i]); ++ } ++} ++ ++ ++ ++/* @brief cal txd number for a page ++ * ++ * @parm size ++ * ++ * @return frag_txd_num ++ */ ++static inline unsigned int _MDrv_NOE_PDMA_Calc_Frag_Txd_Num(unsigned int size) ++{ ++ unsigned int frag_txd_num = 0; ++ ++ if (size == 0) ++ return 0; ++ while (size > 0) { ++ if (size > MAX_PTXD_LEN) { ++ frag_txd_num++; ++ size -= MAX_PTXD_LEN; ++ } else { ++ frag_txd_num++; ++ size = 0; ++ } ++ } ++ return frag_txd_num; ++} ++ ++static int _MDrv_NOE_PDMA_Fill_Txd(struct net_device *dev, unsigned long *tx_cpu_owner_idx, struct sk_buff *skb, int gmac_no) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct PDMA_txdesc *tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx]; ++ struct PDMA_TXD_INFO2_T txd_info2_tmp; ++ struct PDMA_TXD_INFO4_T txd_info4_tmp; ++ ++ tx_ring->txd_info1.SDP0 = virt_to_phys(skb->data); ++ txd_info2_tmp.SDL0 = skb->len; ++ txd_info4_tmp.FPORT = gmac_no; ++ txd_info4_tmp.TSO = 0; ++ ++ if (ei_local->features & FE_CSUM_OFFLOAD) { ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ txd_info4_tmp.TUI_CO = 7; ++ else ++ txd_info4_tmp.TUI_CO = 0; ++ } ++ ++ if (ei_local->features & FE_HW_VLAN_TX) { ++ if (skb_vlan_tag_present(skb)) ++ txd_info4_tmp.VLAN_TAG = 0x10000 | skb_vlan_tag_get(skb); ++ else ++ txd_info4_tmp.VLAN_TAG = 0; ++ } ++#ifdef CONFIG_NOE_NAT_HW ++ if (FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if (IS_VALID_NOE_HWNAT_HOOK_RX) { ++ /* PPE */ ++ txd_info4_tmp.FPORT = 4; ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++ txd_info2_tmp.LS0_bit = 1; ++ txd_info2_tmp.DDONE_bit = 0; ++ ++ tx_ring->txd_info4 = txd_info4_tmp; ++ tx_ring->txd_info2 = txd_info2_tmp; ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PDMA_Tso_Fill_Data(struct END_DEVICE *ei_local, unsigned int frag_offset, unsigned int frag_size, unsigned long *tx_cpu_owner_idx, unsigned int nr_frags, int gmac_no) ++{ ++ struct PSEUDO_ADAPTER *p_ad; ++ unsigned int size; ++ unsigned int frag_txd_num; ++ struct PDMA_txdesc *tx_ring; ++ ++ frag_txd_num = _MDrv_NOE_PDMA_Calc_Frag_Txd_Num(frag_size); ++ tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx]; ++ ++ while (frag_txd_num > 0) { ++ if (frag_size < MAX_PTXD_LEN) ++ size = frag_size; ++ else ++ size = MAX_PTXD_LEN; ++ ++ if (ei_local->skb_txd_num % 2 == 0) { ++ *tx_cpu_owner_idx = (*tx_cpu_owner_idx + 1) % NUM_TX_DESC; ++ tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx]; ++ ++ while (tx_ring->txd_info2.DDONE_bit == 0) { ++ if (gmac_no == 2) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_errors++; ++ } else { ++ ei_local->stat.tx_errors++; ++ } ++ } ++ tx_ring->txd_info1.SDP0 = frag_offset; ++ tx_ring->txd_info2.SDL0 = size; ++ if (((nr_frags == 0)) && (frag_txd_num == 1)) ++ tx_ring->txd_info2.LS0_bit = 1; ++ else ++ tx_ring->txd_info2.LS0_bit = 0; ++ tx_ring->txd_info2.DDONE_bit = 0; ++ tx_ring->txd_info4.FPORT = gmac_no; ++ } else { ++ tx_ring->txd_info3.SDP1 = frag_offset; ++ tx_ring->txd_info2.SDL1 = size; ++ if (((nr_frags == 0)) && (frag_txd_num == 1)) ++ tx_ring->txd_info2.LS1_bit = 1; ++ else ++ tx_ring->txd_info2.LS1_bit = 0; ++ } ++ frag_offset += size; ++ frag_size -= size; ++ frag_txd_num--; ++ ei_local->skb_txd_num++; ++ } ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PDMA_Tso_Fill_Frag(struct net_device *netdev, struct sk_buff *skb, unsigned long *tx_cpu_owner_idx, int gmac_no) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(netdev); ++ struct PSEUDO_ADAPTER *p_ad; ++ unsigned int size; ++ unsigned int frag_txd_num; ++ struct skb_frag_struct *frag; ++ unsigned int nr_frags; ++ unsigned int frag_offset, frag_size; ++ struct PDMA_txdesc *tx_ring; ++ int i = 0, j = 0, unmap_idx = 0; ++ ++ nr_frags = skb_shinfo(skb)->nr_frags; ++ tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx]; ++ ++ for (i = 0; i < nr_frags; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ frag_offset = frag->page_offset; ++ frag_size = frag->size; ++ frag_txd_num = _MDrv_NOE_PDMA_Calc_Frag_Txd_Num(frag_size); ++ ++ while (frag_txd_num > 0) { ++ if (frag_size < MAX_PTXD_LEN) ++ size = frag_size; ++ else ++ size = MAX_PTXD_LEN; ++ ++ if (ei_local->skb_txd_num % 2 == 0) { ++ *tx_cpu_owner_idx = (*tx_cpu_owner_idx + 1) % NUM_TX_DESC; ++ tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx]; ++ ++ while (tx_ring->txd_info2.DDONE_bit == 0) { ++ if (gmac_no == 2) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_errors++; ++ } else { ++ ei_local->stat.tx_errors++; ++ } ++ } ++ ++ tx_ring->txd_info1.SDP0 = dma_map_page(netdev->dev.parent, frag->page.p, frag_offset, size, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(netdev->dev.parent, tx_ring->txd_info1.SDP0))) { ++ NOE_MSG_ERR("[%s]dma_map_page() failed\n", __func__); ++ goto err_dma; ++ } ++ ++ tx_ring->txd_info2.SDL0 = size; ++ ++ if ((frag_txd_num == 1) && (i == (nr_frags - 1))) ++ tx_ring->txd_info2.LS0_bit = 1; ++ else ++ tx_ring->txd_info2.LS0_bit = 0; ++ tx_ring->txd_info2.DDONE_bit = 0; ++ tx_ring->txd_info4.FPORT = gmac_no; ++ } else { ++ tx_ring->txd_info3.SDP1 = dma_map_page(netdev->dev.parent, frag->page.p, frag_offset, size, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(netdev->dev.parent, tx_ring->txd_info3.SDP1))) { ++ NOE_MSG_ERR("[%s]dma_map_page() failed\n", __func__); ++ goto err_dma; ++ } ++ tx_ring->txd_info2.SDL1 = size; ++ if ((frag_txd_num == 1) && (i == (nr_frags - 1))) ++ tx_ring->txd_info2.LS1_bit = 1; ++ else ++ tx_ring->txd_info2.LS1_bit = 0; ++ } ++ frag_offset += size; ++ frag_size -= size; ++ frag_txd_num--; ++ ei_local->skb_txd_num++; ++ } ++ } ++ ++ return 0; ++ ++err_dma: ++ /* unmap dma */ ++ j = *tx_cpu_owner_idx; ++ unmap_idx = i; ++ for (i = 0; i < unmap_idx; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ frag_offset = frag->page_offset; ++ frag_size = frag->size; ++ frag_txd_num = _MDrv_NOE_PDMA_Calc_Frag_Txd_Num(frag_size); ++ ++ while (frag_txd_num > 0) { ++ if (frag_size < MAX_PTXD_LEN) ++ size = frag_size; ++ else ++ size = MAX_PTXD_LEN; ++ if (ei_local->skb_txd_num % 2 == 0) { ++ j = (j + 1) % NUM_TX_DESC; ++ dma_unmap_page(netdev->dev.parent, ei_local->tx_ring0[j].txd_info1.SDP0, ei_local->tx_ring0[j].txd_info2.SDL0, DMA_TO_DEVICE); ++ /* reinit txd */ ++ ei_local->tx_ring0[j].txd_info2.LS0_bit = 1; ++ ei_local->tx_ring0[j].txd_info2.DDONE_bit = 1; ++ } else { ++ dma_unmap_page(netdev->dev.parent, ei_local->tx_ring0[j].txd_info3.SDP1, ei_local->tx_ring0[j].txd_info2.SDL1, DMA_TO_DEVICE); ++ /* reinit txd */ ++ ei_local->tx_ring0[j].txd_info2.LS1_bit = 1; ++ } ++ frag_offset += size; ++ frag_size -= size; ++ frag_txd_num--; ++ ei_local->skb_txd_num++; ++ } ++ } ++ ++ return -1; ++} ++ ++static int _MDrv_NOE_PDMA_Tso_Fill_Txd(struct net_device *dev, unsigned long *tx_cpu_owner_idx, struct sk_buff *skb, int gmac_no) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ struct iphdr *iph = NULL; ++ struct ipv6hdr *ip6h = NULL; ++ struct tcphdr *th = NULL; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags; ++ unsigned int len, offset; ++ int err; ++ struct PDMA_txdesc *tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx]; ++ ++ tx_ring->txd_info4.FPORT = gmac_no; ++ tx_ring->txd_info4.TSO = 0; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ tx_ring->txd_info4.TUI_CO = 7; ++ else ++ tx_ring->txd_info4.TUI_CO = 0; ++ ++ if (ei_local->features & FE_HW_VLAN_TX) { ++ if (skb_vlan_tag_present(skb)) ++ tx_ring->txd_info4.VLAN_TAG = 0x10000 | skb_vlan_tag_get(skb); ++ else ++ tx_ring->txd_info4.VLAN_TAG = 0; ++ } ++#ifdef CONFIG_NOE_NAT_HW ++ if (FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if (IS_VALID_NOE_HWNAT_HOOK_RX) { ++ /* PPE */ ++ tx_ring->txd_info4.FPORT = 4; ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ei_local->skb_txd_num = 1; ++ ++ /* skb data handle */ ++ len = skb->len - skb->data_len; ++ offset = virt_to_phys(skb->data); ++ tx_ring->txd_info1.SDP0 = offset; ++ if (len < MAX_PTXD_LEN) { ++ tx_ring->txd_info2.SDL0 = len; ++ tx_ring->txd_info2.LS0_bit = nr_frags ? 0 : 1; ++ len = 0; ++ } else { ++ tx_ring->txd_info2.SDL0 = MAX_PTXD_LEN; ++ tx_ring->txd_info2.LS0_bit = 0; ++ len -= MAX_PTXD_LEN; ++ offset += MAX_PTXD_LEN; ++ } ++ ++ if (len > 0) ++ _MDrv_NOE_PDMA_Tso_Fill_Data(ei_local, offset, len, tx_cpu_owner_idx, nr_frags, gmac_no); ++ ++ /* skb fragments handle */ ++ if (nr_frags > 0) { ++ err = _MDrv_NOE_PDMA_Tso_Fill_Frag(dev, skb, tx_cpu_owner_idx, gmac_no); ++ if (unlikely(err)) ++ return err; ++ } ++ ++ /* fill in MSS info in tcp checksum field */ ++ if (skb_shinfo(skb)->gso_segs > 1) { ++ MDrv_NOE_Update_Tso_Len(skb->len); ++ /* TCP over IPv4 */ ++ iph = (struct iphdr *)skb_network_header(skb); ++ if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++ tx_ring->txd_info4.TSO = 1; ++ th->check = htons(skb_shinfo(skb)->gso_size); ++ dma_sync_single_for_device(dev->dev.parent, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++ } ++ ++ /* TCP over IPv6 */ ++ if (ei_local->features & FE_TSO_V6) { ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++ if ((ip6h->nexthdr == NEXTHDR_TCP) && (ip6h->version == 6)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++ tx_ring->txd_info4.TSO = 1; ++ th->check = htons(skb_shinfo(skb)->gso_size); ++ dma_sync_single_for_device(dev->dev.parent, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++ } ++ } ++ } ++ tx_ring->txd_info2.DDONE_bit = 0; ++ ++ return 0; ++} ++ ++static inline int MDrv_NOE_PDMA_Eth_Send(struct net_device *dev, struct sk_buff *skb, int gmac_no, unsigned int num_of_frag) ++{ ++ unsigned int length = skb->len; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ unsigned long tx_cpu_owner_idx0 = ei_local->tx_cpu_owner_idx0; ++#else ++ unsigned long tx_cpu_owner_idx0 = MHal_NOE_DMA_Get_Calc_Idx(E_NOE_DIR_TX); ++#endif ++ struct PSEUDO_ADAPTER *p_ad; ++ int err; ++ ++ while (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) { ++ if (gmac_no == 2) { ++ if (ei_local->pseudo_dev) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_errors++; ++ } else { ++ NOE_MSG_ERR("pseudo_dev is still not initialize "); ++ NOE_MSG_ERR("but receive packet from GMAC2\n"); ++ } ++ } else { ++ ei_local->stat.tx_errors++; ++ } ++ } ++ ++ if (num_of_frag > 1) ++ err = _MDrv_NOE_PDMA_Tso_Fill_Txd(dev, &tx_cpu_owner_idx0, skb, gmac_no); ++ else ++ err = _MDrv_NOE_PDMA_Fill_Txd(dev, &tx_cpu_owner_idx0, skb, gmac_no); ++ if (err) ++ return err; ++ ++ tx_cpu_owner_idx0 = (tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; ++ while (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) { ++ if (gmac_no == 2) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_errors++; ++ } else { ++ ei_local->stat.tx_errors++; ++ } ++ } ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ ei_local->tx_cpu_owner_idx0 = tx_cpu_owner_idx0; ++#endif ++ /* make sure that all changes to the dma ring are flushed before we ++ * continue ++ */ ++ wmb(); ++ ++ MHal_NOE_DMA_Update_Calc_Idx(E_NOE_DIR_TX,cpu_to_le32((u32)tx_cpu_owner_idx0)); ++ ++ if (gmac_no == 2) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_packets++; ++ p_ad->stat.tx_bytes += length; ++ } ++ else { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += length; ++ } ++ ++ return length; ++} ++ ++int MDrv_NOE_PDMA_Start_Xmit(struct sk_buff *skb, struct net_device *dev, int gmac_no) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long tx_cpu_owner_idx; ++ unsigned int tx_cpu_owner_idx_next, tx_cpu_owner_idx_next2; ++ unsigned int num_of_txd, num_of_frag; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i; ++ struct skb_frag_struct *frag; ++ struct PSEUDO_ADAPTER *p_ad; ++ unsigned int tx_cpu_cal_idx; ++ ++#ifdef CONFIG_NOE_NAT_HW ++ if (IS_VALID_NOE_HWNAT_HOOK_TX) { ++ if (FOE_MAGIC_TAG(skb) != FOE_MAGIC_PPE) ++ if (NOE_HWNAT_HOOK_TX(skb, gmac_no) != 1) { ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ } ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) ++ dev->trans_start = jiffies; /* save the timestamp */ ++#else ++ { ++ struct netdev_queue *txq = netdev_get_tx_queue(dev, 0); ++ ++ if (txq->trans_start != jiffies) ++ txq->trans_start = jiffies; ++ } ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) */ ++ ++ ++ spin_lock(&ei_local->page_lock); ++ dma_sync_single_for_device(dev->dev.parent, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++ ++#ifdef CONFIG_NOE_RW_PDMAPTR_FROM_VAR ++ tx_cpu_owner_idx = ei_local->tx_cpu_owner_idx0; ++#else ++ tx_cpu_owner_idx = MHal_NOE_DMA_Get_Calc_Idx(E_NOE_DIR_TX); ++#endif ++ ++ if (ei_local->features & FE_TSO) { ++ num_of_txd = _MDrv_NOE_PDMA_Calc_Frag_Txd_Num(skb->len - skb->data_len); ++ if (nr_frags != 0) { ++ for (i = 0; i < nr_frags; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ num_of_txd += _MDrv_NOE_PDMA_Calc_Frag_Txd_Num(frag->size); ++ } ++ } ++ num_of_frag = num_of_txd; ++ num_of_txd = (num_of_txd + 1) >> 1; ++ } else { ++ num_of_frag = 1; ++ num_of_txd = 1; ++ } ++ ++ tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC; ++ ++ if ((ei_local->skb_free[tx_cpu_owner_idx_next] == 0) && ++ (ei_local->skb_free[tx_cpu_owner_idx] == 0)) { ++ if (MDrv_NOE_PDMA_Eth_Send(dev, skb, gmac_no, num_of_frag) < 0) { ++ dev_kfree_skb_any(skb); ++ if (gmac_no == 2) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_dropped++; ++ } else { ++ ei_local->stat.tx_dropped++; ++ } ++ goto tx_err; ++ } ++ ++ tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC; ++ ++ if (ei_local->skb_free[tx_cpu_owner_idx_next2] != 0) ++ ei_local->tx_ring_full = 1; ++ } ++ else { ++ if (gmac_no == 2) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_dropped++; ++ } else { ++ ei_local->stat.tx_dropped++; ++ } ++ ++ dev_kfree_skb_any(skb); ++ spin_unlock(&ei_local->page_lock); ++ return NETDEV_TX_OK; ++ } ++ ++ /* SG: use multiple TXD to send the packet (only have one skb) */ ++ tx_cpu_cal_idx = (tx_cpu_owner_idx + num_of_txd - 1) % NUM_TX_DESC; ++ ei_local->skb_free[tx_cpu_cal_idx] = skb; ++ while (--num_of_txd) { ++ /* MAGIC ID */ ++ ei_local->skb_free[(--tx_cpu_cal_idx) % NUM_TX_DESC] = (struct sk_buff *)0xFFFFFFFF; ++ } ++tx_err: ++ spin_unlock(&ei_local->page_lock); ++ return NETDEV_TX_OK; ++} ++ ++int MDrv_NOE_PDMA_Xmit_Housekeeping(struct net_device *netdev, int budget) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(netdev); ++ struct PDMA_txdesc *tx_desc; ++ unsigned long skb_free_idx; ++ int tx_processed = 0; ++ ++ tx_desc = ei_local->tx_ring0; ++ skb_free_idx = ei_local->free_idx; ++ ++ while (budget && (ei_local->skb_free[skb_free_idx] != 0) && (tx_desc[skb_free_idx].txd_info2.DDONE_bit == 1)) { ++ if (ei_local->skb_free[skb_free_idx] != (struct sk_buff *)0xFFFFFFFF) ++ dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]); ++ ++ ei_local->skb_free[skb_free_idx] = 0; ++ skb_free_idx = (skb_free_idx + 1) % NUM_TX_DESC; ++ budget--; ++ tx_processed++; ++ } ++ ++ ei_local->tx_ring_full = 0; ++ ei_local->free_idx = skb_free_idx; ++ ++ return tx_processed; ++} ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_phy.c b/drivers/sstar/noe/drv/eth/mdrv_noe_phy.c +new file mode 100755 +index 000000000000..bc1cf133ca0f +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_phy.c +@@ -0,0 +1,255 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_PHY.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mdrv_noe.h" ++#include "mdrv_noe_phy.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++typedef void (*PFN_SET_CFG)(u32, struct st_drv_phy_config *); ++ ++typedef enum { ++ E_NOE_PHY_ID_MARVELL = 0, ++ E_NOE_PHY_ID_VTSS, ++ E_NOE_PHY_ID_ATHEROS, ++ E_NOE_PHY_ID_REALTEK, ++ /* add id below */ ++ ++ /* add id above */ ++ E_NOE_PHY_ID_MAX, ++ E_NOE_PHY_ID_INVALID = E_NOE_PHY_ID_MAX, ++}EN_NOE_PHY_ID; ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++static void _MDrv_NOE_PHY_Set_Vtss_Config(u32 phy_address, struct st_drv_phy_config *info); ++static void _MDrv_NOE_PHY_Set_Marvell_Config(u32 phy_address, struct st_drv_phy_config *info); ++static void _MDrv_NOE_PHY_Set_Atheros_Config(u32 phy_address, struct st_drv_phy_config *info); ++static void _MDrv_NOE_PHY_Set_Realtek_Config(u32 phy_address, struct st_drv_phy_config *info); ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++static PFN_SET_CFG _pfn_set_config[E_NOE_PHY_ID_MAX] = { ++ [E_NOE_PHY_ID_MARVELL] = _MDrv_NOE_PHY_Set_Marvell_Config, ++ [E_NOE_PHY_ID_VTSS] = _MDrv_NOE_PHY_Set_Vtss_Config, ++ [E_NOE_PHY_ID_ATHEROS] = _MDrv_NOE_PHY_Set_Atheros_Config, ++ [E_NOE_PHY_ID_REALTEK] = _MDrv_NOE_PHY_Set_Realtek_Config, ++}; ++ ++ ++static EN_NOE_PHY_ID _MDrv_NOE_PHY_Get_PHY_ID(u32 phy_address) ++{ ++ u32 phy_id0 = 0, phy_id1 = 0; ++ ++ if (MHal_NOE_Read_Mii_Mgr(phy_address, MII_PHYSID1, &phy_id0) != E_NOE_RET_TRUE) { ++ NOE_MSG_ERR("\n Read PhyID 1 is Fail!! 0x%x\n", phy_id0); ++ phy_id0 = 0; ++ } ++ if (MHal_NOE_Read_Mii_Mgr(phy_address, MII_PHYSID2, &phy_id1) != E_NOE_RET_TRUE) { ++ NOE_MSG_ERR("\n Read PhyID 1 is Fail!! 0x%x\n", phy_id1); ++ phy_id1 = 0; ++ } ++ ++ if ((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_ID1)) ++ return E_NOE_PHY_ID_MARVELL; ++ ++ if ((phy_id0 == EV_ATHEROS_PHY_ID0) && (phy_id1 == EV_ATHEROS_PHY_ID1)) ++ return E_NOE_PHY_ID_ATHEROS; ++ ++ if ((phy_id0 == EV_VTSS_PHY_ID0) && (phy_id1 == EV_VTSS_PHY_ID1)) ++ return E_NOE_PHY_ID_VTSS; ++ ++ if ((phy_id0 == EV_REALTEK_PHY_ID0) && ((phy_id1 & EV_REALTEK_PHY_ID1) == EV_REALTEK_PHY_ID1)) ++ return E_NOE_PHY_ID_REALTEK; ++ ++ return E_NOE_PHY_ID_INVALID; ++ ++} ++ ++static void _MDrv_NOE_PHY_Set_Vtss_Config(u32 phy_address, struct st_drv_phy_config *info) ++{ ++ u32 reg_value; ++ MHal_NOE_Write_Mii_Mgr(phy_address, 31, 1); ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_NCONFIG, ®_value); ++ NOE_MSG_DBG("Vitesse phy skew: %x --> ", reg_value); ++ reg_value |= (0x3 << 12); ++ reg_value &= ~(0x3 << 14); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_NCONFIG, reg_value); ++ MHal_NOE_Write_Mii_Mgr(phy_address, 31, 0); ++} ++ ++static void _MDrv_NOE_PHY_Set_Marvell_Config(u32 phy_address, struct st_drv_phy_config *info) ++{ ++ u32 reg_value; ++ if (phy_address == CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2) { ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_CTRL1000, ®_value); ++ /* turn off 1000Base-T Advertisement ++ * (9.9=1000Full, 9.8=1000Half) ++ */ ++ reg_value &= ~(3 << 8); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_CTRL1000, reg_value); ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_NWAYTEST, ®_value); ++ /* Add delay to RX_CLK for RXD Outputs */ ++ reg_value |= 1 << 7; ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_NWAYTEST, reg_value); ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, ®_value); ++ reg_value |= 1 << 15; /* PHY Software Reset */ ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_BMCR, reg_value); ++ } ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_CTRL1000, ®_value); ++ /* turn off 1000Base-T Advertisement ++ * (9.9=1000Full, 9.8=1000Half) ++ */ ++ reg_value &= ~(3 << 8); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_CTRL1000, reg_value); ++ ++ /*10Mbps, debug */ ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_ADVERTISE, 0x461); ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, ®_value); ++ reg_value |= 1 << 9; /* restart AN */ ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_BMCR, reg_value); ++ ++} ++ ++static void _MDrv_NOE_PHY_Set_Atheros_Config(u32 phy_address, struct st_drv_phy_config *info) ++{ ++ u32 reg_value; ++ if (info->mii_force_mode == NOE_ENABLE) { ++#if defined(CONFIG_NOE_FPGA_VERIFY) || defined(CONFIG_MSTAR_ARM_BD_FPGA) ++ /* turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) */ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_CTRL1000, ®_value); ++ reg_value &= ~(ADVERTISE_1000HALF|ADVERTISE_1000FULL); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_CTRL1000, reg_value); ++ ++ /*10Mbps, debug*/ ++ reg_value = ADVERTISE_PAUSE_CAP|ADVERTISE_10FULL|ADVERTISE_10HALF|ADVERTISE_CSMA; ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_ADVERTISE, reg_value); ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, ®_value); ++ reg_value |= BMCR_ANENABLE|BMCR_ANENABLE; //restart AN ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_BMCR, reg_value); ++ ++ NOE_MSG_DBG("phy addr: %d, Setup 10Mbps\n", phy_address); ++#endif /* CONFIG_NOE_FPGA_VERIFY */ ++ } ++ else { ++ /* Set Auto Polling Mode */ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_CTRL1000, ®_value); ++ reg_value |= (3<<8); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_CTRL1000, reg_value); ++ ++ reg_value = ADVERTISE_PAUSE_CAP|ADVERTISE_100FULL|ADVERTISE_100HALF|ADVERTISE_10FULL|ADVERTISE_10HALF|ADVERTISE_CSMA; ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_ADVERTISE, reg_value); ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, ®_value); ++ reg_value |= (BMCR_ANENABLE | BMCR_ANRESTART) ; ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_BMCR, reg_value); ++ } ++ ++ ++} ++ ++static int phy_poll_reset(u32 phy_address) ++{ ++ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ ++ unsigned int retries = 12; ++ int ret; ++ ++ do { ++ msleep(50); ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, &ret); ++ } while (ret & BMCR_RESET && --retries); ++ if (ret & BMCR_RESET) ++ return -ETIMEDOUT; ++ ++ /* Some chips (smsc911x) may still need up to another 1ms after the ++ * BMCR_RESET bit is cleared before they are usable. ++ */ ++ msleep(1); ++ return 0; ++} ++ ++static void _MDrv_NOE_PHY_Set_Realtek_Config(u32 phy_address, struct st_drv_phy_config *info) ++{ ++ u32 reg_value; ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, ®_value); ++ reg_value |= BMCR_RESET; ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_BMCR, reg_value); ++ phy_poll_reset(phy_address); ++ ++ /* Set Speed */ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_ADVERTISE, ®_value); ++ reg_value |= ADVERTISE_10FULL | ADVERTISE_10HALF; ++ reg_value |= ADVERTISE_100HALF | ADVERTISE_100FULL; ++ reg_value &= (~ADVERTISE_PAUSE_CAP); ++ reg_value |= ADVERTISE_CSMA; ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_ADVERTISE, reg_value); ++ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_CTRL1000, ®_value); ++ reg_value |= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_CTRL1000, reg_value); ++ ++ ++ /* restart AN */ ++ MHal_NOE_Read_Mii_Mgr(phy_address, MII_BMCR, ®_value); ++ reg_value |= (BMCR_ANENABLE | BMCR_ANRESTART); ++ MHal_NOE_Write_Mii_Mgr(phy_address, MII_BMCR, reg_value); ++ ++} ++ ++ ++void MDrv_NOE_PHY_Set_Config(u32 phy_addr, struct st_drv_phy_config *info) ++{ ++ EN_NOE_PHY_ID id; ++ MHal_NOE_Init_Mii_Mgr(info->ge, phy_addr, info->mii_force_mode); ++ ++ id = _MDrv_NOE_PHY_Get_PHY_ID(phy_addr); ++ NOE_MSG_DBG("[GE%d] phy id: %d, phy addr: %d\n", (info->ge +1), id, phy_addr); ++ ++ if (id == E_NOE_PHY_ID_INVALID) { ++ NOE_MSG_ERR("Invalid phy id in GE%d\n", (info->ge +1)); ++ return; ++ } ++ _pfn_set_config[id](phy_addr, info); ++} ++ ++ ++ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_phy.h b/drivers/sstar/noe/drv/eth/mdrv_noe_phy.h +new file mode 100755 +index 000000000000..88ce88b3b3d0 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_phy.h +@@ -0,0 +1,51 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_PHY.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MDRV_NOE_PHY_ ++#define _MDRV_NOE_PHY_ ++ ++#define EV_ICPLUS_PHY_ID0 0x0243 ++#define EV_ICPLUS_PHY_ID1 0x0D90 ++#define EV_MARVELL_PHY_ID0 0x0141 ++#define EV_MARVELL_PHY_ID1 0x0CC2 ++#define EV_VTSS_PHY_ID0 0x0007 ++#define EV_VTSS_PHY_ID1 0x0421 ++#define EV_ATHEROS_PHY_ID0 0x004d ++#define EV_ATHEROS_PHY_ID1 0xd072 ++#define EV_REALTEK_PHY_ID0 0x001C ++#define EV_REALTEK_PHY_ID1 0xC800 ++ ++struct st_drv_phy_config { ++ EN_NOE_GE_MAC ge; ++ unsigned char mii_force_mode; ++ EN_NOE_SPEED speed; ++ EN_NOE_DUPLEX duplex; ++}; ++ ++void MDrv_NOE_PHY_Set_Config(u32 phy_addr, struct st_drv_phy_config *info); ++ ++#endif /* _MDRV_NOE_PHY_ */ ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_proc.c b/drivers/sstar/noe/drv/eth/mdrv_noe_proc.c +new file mode 100755 +index 000000000000..ae6700342307 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_proc.c +@@ -0,0 +1,1455 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV NOE PROC c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#elif defined(CONFIG_ARM64) ++#include ++#include ++#endif ++ ++ ++#include ++ ++#include "mdrv_types.h" ++#include "mhal_noe.h" ++#include "mdrv_noe.h" ++#include "mdrv_noe_proc.h" ++#include "mdrv_noe_ethtool.h" ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define MAX_AGGR 64 ++#define MAX_DESC 8 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++enum { ++ E_NOE_PROC_RING0 = 0, ++ E_NOE_PROC_RING1, ++ E_NOE_PROC_RING2, ++ E_NOE_PROC_RING3, ++}; ++enum { ++ E_NOE_PROC_TX = 1, ++ E_NOE_PROC_RX = 2, ++}; ++ ++enum { ++ E_NOE_PROC_GMAC1 = 0, ++ E_NOE_PROC_GMAC2, ++ E_NOE_PROC_SKB_FREE, ++ E_NOE_PROC_TX_RING, ++ E_NOE_PROC_RX_RING, ++ E_NOE_PROC_NUM_OF_TXD, ++ E_NOE_PROC_TSO_LEN, ++ E_NOE_PROC_LRO_STATS, ++ E_NOE_PROC_SNMP, ++ E_NOE_PROC_ESW_CNT, ++ E_NOE_PROC_ETH_CNT, ++ E_NOE_PROC_SCHE, ++ E_NOE_PROC_INT_DBG, ++ E_NOE_PROC_SET_LAN_IP, ++ E_NOE_PROC_PIN_MUX, ++ E_NOE_PROC_LOG_CTRL, ++ E_NOE_PROC_QSCH, ++ E_NOE_PROC_MAX, ++}; ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++static ssize_t _MDrv_NOE_PROC_Write_Log_Ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Open_Log_Ctrl(struct inode *inode, struct file *file); ++ ++static ssize_t _MDrv_NOE_PROC_Write_Pin_Mux(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Open_Pin_Mux(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Open_Gmac(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Open_Gmac2(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Read_Regs(struct seq_file *seq, void *offset); ++static void _MDrv_NOE_PROC_Dump_Reg(struct seq_file *s); ++static ssize_t _MDrv_NOE_PROC_Set_Gmac2_Phyid(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static ssize_t _MDrv_NOE_PROC_Set_Gmac1_Phyid(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Open_Skb_Free(struct inode *inode, struct file *file); ++static void *_MDrv_NOE_PROC_Start_Skb_Free(struct seq_file *seq, loff_t *pos); ++static void *_MDrv_NOE_PROC_Get_Next_Skb_Free(struct seq_file *seq, void *offset, loff_t *pos); ++static void _MDrv_NOE_PROC_Stop_Skb_Free(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Show_Skb_Free(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Open_Tx_Ring(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Open_Rx_Ring(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Open_Tso_Txd_Num(struct inode *inode, struct file *file); ++static void *_MDrv_NOE_PROC_Start_Tso_Txd_Num(struct seq_file *seq, loff_t *pos); ++static void *_MDrv_NOE_PROC_Get_Next_Tso_Txd_Num(struct seq_file *seq, void *offset, loff_t *pos); ++static void _MDrv_NOE_PROC_Stop_Tso_Txd_Num(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Show_Tso_Txd_Num(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Open_Tso_Len(struct inode *inode, struct file *file); ++static void *_MDrv_NOE_PROC_Get_Next_Tso_Len(struct seq_file *seq, void *offset, loff_t *pos); ++static void _MDrv_NOE_PROC_Stop_Tso_Len(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Show_Tso_Len(struct seq_file *seq, void *offset); ++static void *_MDrv_NOE_PROC_Start_Tso_Len(struct seq_file *seq, loff_t *pos); ++ssize_t _MDrv_NOE_PROC_Write_Lro_Stats(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Open_Lro_Stats(struct inode *inode, struct file *file); ++int _MDrv_NOE_PROC_Show_Lro_Stats(struct seq_file *seq, void *offset); ++ssize_t _MDrv_NOE_PROC_Write_Tso_Len(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Open_Snmp(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Show_Snmp(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Open_Switch_Count(struct inode *inode, struct file *file); ++int _MDrv_NOE_PROC_Show_Switch_Count(struct seq_file *seq, void *offset); ++int _MDrv_NOE_PROC_Show_Eth_Count(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Open_Eth_Count(struct inode *inode, struct file *file); ++static int _MDrv_NOE_PROC_Open_Schedule(struct inode *inode, struct file *file); ++static ssize_t _MDrv_NOE_PROC_Write_Schedule(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Read_Schedule(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Read_Lan_Ip_Setting(struct seq_file *seq, void *offset); ++static int _MDrv_NOE_PROC_Open_Lan_Ip_Setting(struct inode *inode, struct file *file); ++static ssize_t _MDrv_NOE_PROC_Write_Lan_Ip_Setting(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Read_Intr_Dbg(struct seq_file *seq, void *offset); ++static ssize_t _MDrv_NOE_PROC_Write_Intr_Dbg(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++static int _MDrv_NOE_PROC_Open_Intr_Dbg(struct inode *inode, struct file *file); ++static ssize_t _MDrv_NOE_PROC_Write_Txd_Num(struct file *file, const char __user *buffer, size_t count, loff_t *data); ++void _MDrv_NOE_PROC_Dump_Qdma_Cnt(void); ++static int _MDrv_NOE_PROC_Get_Ring_Usage(int dma, int mode, int i); ++static int _MDrv_NOE_PROC_Open_QoS(struct inode *inode, struct file *file); ++ ++//-------------------------------------------------------------------------------------------------- ++// External Variable ++//-------------------------------------------------------------------------------------------------- ++ ++extern unsigned int M2Q_table[64]; ++extern struct QDMA_txdesc *free_head; ++extern struct SFQ_table *sfq0; ++extern struct SFQ_table *sfq1; ++extern struct SFQ_table *sfq2; ++extern struct SFQ_table *sfq3; ++extern int init_schedule; ++extern int working_schedule; ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++struct proc_dir_entry *proc_reg_dir = NULL; ++static struct mdrv_noe_proc_intr mdrv_noe_proc_intr; ++int tso_cnt[16]; ++int lro_stats_cnt[MAX_AGGR + 1]; ++int txd_cnt[MAX_SKB_FRAGS / 2 + 1]; ++int lro_stats_cnt[MAX_AGGR + 1]; ++int lro_flush_cnt[MAX_AGGR + 1]; ++int lro_len_cnt1[16]; ++/* int lro_len_cnt2[16]; */ ++int aggregated[MAX_DESC]; ++int lro_aggregated; ++int lro_flushed; ++int lro_nodesc; ++int force_flush; ++int tot_called1; ++int tot_called2; ++static struct net_device *_noe_proc_dev = NULL; ++static struct proc_dir_entry *proc_entry[E_NOE_PROC_MAX] = {NULL}; ++static const struct seq_operations _MDrv_NOE_PROC_Set_Skb_free_Ops = { ++ .start = _MDrv_NOE_PROC_Start_Skb_Free, ++ .next = _MDrv_NOE_PROC_Get_Next_Skb_Free, ++ .stop = _MDrv_NOE_PROC_Stop_Skb_Free, ++ .show = _MDrv_NOE_PROC_Show_Skb_Free ++}; ++ ++static const struct seq_operations _MDrv_NOE_PROC_Set_Tso_Txd_Num_Ops = { ++ .start = _MDrv_NOE_PROC_Start_Tso_Txd_Num, ++ .next = _MDrv_NOE_PROC_Get_Next_Tso_Txd_Num, ++ .stop = _MDrv_NOE_PROC_Stop_Tso_Txd_Num, ++ .show = _MDrv_NOE_PROC_Show_Tso_Txd_Num ++}; ++ ++static const struct seq_operations _MDrv_NOE_PROC_Set_Tso_Len_Ops = { ++ .start = _MDrv_NOE_PROC_Start_Tso_Len, ++ .next = _MDrv_NOE_PROC_Get_Next_Tso_Len, ++ .stop = _MDrv_NOE_PROC_Stop_Tso_Len, ++ .show = _MDrv_NOE_PROC_Show_Tso_Len ++}; ++ ++ ++ ++static const char noe_proc_name[E_NOE_PROC_MAX][16] = { ++ [E_NOE_PROC_GMAC1] = { NOE_PROC_GMAC }, ++ [E_NOE_PROC_GMAC2] = { NOE_PROC_GMAC2 }, ++ [E_NOE_PROC_SKB_FREE] = { NOE_PROC_SKBFREE }, ++ [E_NOE_PROC_TX_RING] = { NOE_PROC_TX_RING }, ++ [E_NOE_PROC_RX_RING] = { NOE_PROC_RX_RING }, ++ [E_NOE_PROC_NUM_OF_TXD] = { NOE_PROC_NUM_OF_TXD }, ++ [E_NOE_PROC_TSO_LEN] = { NOE_PROC_TSO_LEN }, ++ [E_NOE_PROC_LRO_STATS] = { NOE_PROC_LRO_STATS }, ++ [E_NOE_PROC_SNMP] = { NOE_PROC_SNMP }, ++ [E_NOE_PROC_ESW_CNT] = { NOE_PROC_ESW_CNT }, ++ [E_NOE_PROC_ETH_CNT] = { NOE_PROC_ETH_CNT }, ++ [E_NOE_PROC_SCHE] = { NOE_PROC_SCHE }, ++ [E_NOE_PROC_INT_DBG] = { NOE_PROC_INT_DBG }, ++ [E_NOE_PROC_SET_LAN_IP] = { NOE_PROC_SET_LAN_IP }, ++ [E_NOE_PROC_PIN_MUX] = { NOE_PROC_PIN_MUX }, ++ [E_NOE_PROC_LOG_CTRL] = { NOE_PROC_LOG_CTRL }, ++ [E_NOE_PROC_QSCH] = { NOE_PROC_QSCH }, ++}; ++ ++static const struct file_operations noe_proc_fops[E_NOE_PROC_MAX] = { ++ [E_NOE_PROC_GMAC1] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Gmac, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_PROC_Set_Gmac1_Phyid, ++ .release = single_release ++ }, ++ [E_NOE_PROC_GMAC2] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Gmac2, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_PROC_Set_Gmac2_Phyid ++ }, ++ [E_NOE_PROC_SKB_FREE] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Skb_Free, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++ }, ++ [E_NOE_PROC_TX_RING] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Tx_Ring, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_NOE_PROC_RX_RING] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Rx_Ring, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_NOE_PROC_NUM_OF_TXD] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Tso_Txd_Num, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_PROC_Write_Txd_Num, ++ .release = seq_release ++ }, ++ [E_NOE_PROC_TSO_LEN] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Tso_Len, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_PROC_Write_Tso_Len, ++ .release = seq_release ++ }, ++ [E_NOE_PROC_LRO_STATS] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Lro_Stats, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = _MDrv_NOE_PROC_Write_Lro_Stats, ++ .release = single_release ++ }, ++ [E_NOE_PROC_SNMP] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Snmp, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_NOE_PROC_ESW_CNT] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Switch_Count, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_NOE_PROC_ETH_CNT] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Eth_Count, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_NOE_PROC_SCHE] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Schedule, ++ .read = seq_read, ++ .write = _MDrv_NOE_PROC_Write_Schedule, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++ [E_NOE_PROC_INT_DBG] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Intr_Dbg, ++ .read = seq_read, ++ .write = _MDrv_NOE_PROC_Write_Intr_Dbg ++ }, ++ [E_NOE_PROC_SET_LAN_IP] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Lan_Ip_Setting, ++ .read = seq_read, ++ .write = _MDrv_NOE_PROC_Write_Lan_Ip_Setting ++ }, ++ [E_NOE_PROC_PIN_MUX] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Pin_Mux, ++ .read = seq_read, ++ .write = _MDrv_NOE_PROC_Write_Pin_Mux, ++ }, ++ [E_NOE_PROC_LOG_CTRL] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_Log_Ctrl, ++ .read = seq_read, ++ .write = _MDrv_NOE_PROC_Write_Log_Ctrl, ++ ++ }, ++ [E_NOE_PROC_QSCH] = { ++ .owner = THIS_MODULE, ++ .open = _MDrv_NOE_PROC_Open_QoS, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++ }, ++}; ++ ++//-------------------------------------------------------------------------------------------------- ++// ++//-------------------------------------------------------------------------------------------------- ++ ++static int _MDrv_NOE_PROC_Get_Ring_Usage(int dma, int mode, int ring_no) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ unsigned long tx_ctx_idx, tx_dtx_idx, tx_usage; ++ unsigned long rx_calc_idx, rx_drx_idx, rx_usage; ++ struct PDMA_rxdesc *rxring; ++ struct PDMA_txdesc *txring; ++ struct noe_dma_info ring_info; ++ ++ if (mode == E_NOE_PROC_RX) { ++ /* cpu point to the next descriptor of rx dma ring */ ++ MHal_NOE_LRO_Get_Ring_Info(dma, E_NOE_DIR_RX, E_NOE_RING_NO0, &ring_info); ++ rx_calc_idx = ring_info.ring_st.cpu_idx; ++ rx_drx_idx = ring_info.ring_st.dma_idx; ++ rxring = ei_local->rx_ring[0]; ++ ++ rx_usage = (rx_drx_idx - rx_calc_idx - 1 + NUM_RX_DESC) % NUM_RX_DESC; ++ if (rx_calc_idx == rx_drx_idx) { ++ if (rxring[rx_drx_idx].rxd_info2.DDONE_bit == 1) ++ tx_usage = NUM_RX_DESC; ++ else ++ tx_usage = 0; ++ } ++ return rx_usage; ++ } ++ ++ switch (ring_no) { ++ case E_NOE_PROC_RING0: ++ MHal_NOE_LRO_Get_Ring_Info(dma, E_NOE_DIR_TX, E_NOE_RING_NO0, &ring_info); ++ tx_ctx_idx = ring_info.ring_st.cpu_idx; ++ tx_dtx_idx = ring_info.ring_st.dma_idx; ++ txring = ei_local->tx_ring0; ++ break; ++ default: ++ NOE_MSG_ERR("get_tx_idx failed %d %d\n", mode, ring_no); ++ return 0; ++ }; ++ ++ tx_usage = (tx_ctx_idx - tx_dtx_idx + NUM_TX_DESC) % NUM_TX_DESC; ++ if (tx_ctx_idx == tx_dtx_idx) { ++ if (txring[tx_ctx_idx].txd_info2.DDONE_bit == 1) ++ tx_usage = 0; ++ else ++ tx_usage = NUM_TX_DESC; ++ } ++ return tx_usage; ++} ++ ++static ssize_t _MDrv_NOE_PROC_Write_Txd_Num(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ memset(txd_cnt, 0, sizeof(txd_cnt)); ++ NOE_MSG_DUMP("clear txd cnt table\n"); ++ return count; ++ } else { ++ return 0; ++ } ++} ++ ++static int _MDrv_NOE_PROC_Read_Lan_Ip_Setting(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ seq_printf(seq, "ei_local->lan_ip4_addr = %s\n", ei_local->lan_ip4_addr); ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Lan_Ip_Setting(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Lan_Ip_Setting, NULL); ++} ++ ++static ssize_t _MDrv_NOE_PROC_Write_Lan_Ip_Setting(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ unsigned int lan_ip; ++ ++ if (count > IP4_ADDR_LEN) ++ return -EFAULT; ++ ++ memset(&ei_local->lan_ip4_addr[0], 0, IP4_ADDR_LEN); ++ if (copy_from_user(ei_local->lan_ip4_addr, buffer, count)) ++ return -EFAULT; ++ ++ NOE_MSG_DUMP("LAN IP = %s\n", ei_local->lan_ip4_addr); ++ ++ if (ei_local->features & FE_SW_LRO) { ++ MDrv_NOE_Set_Lro_Ip(ei_local->lan_ip4_addr); ++ } ++ ++ if (ei_local->features & FE_HW_LRO) { ++ MDrv_NOE_UTIL_Str_To_Ip(&lan_ip, ei_local->lan_ip4_addr); ++ MHal_NOE_LRO_Set_Ip(lan_ip); ++ } ++ ++ return count; ++} ++ ++ ++static int _MDrv_NOE_PROC_Read_Intr_Dbg(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_NOE_INT_DBG) { ++ seq_puts(seq, "Raether Interrupt Statistics\n"); ++ seq_printf(seq, "RX_COHERENT = %d\n", mdrv_noe_proc_intr.RX_COHERENT_CNT); ++ seq_printf(seq, "RX_DLY_INT = %d\n", mdrv_noe_proc_intr.RX_DLY_INT_CNT); ++ seq_printf(seq, "TX_COHERENT = %d\n", mdrv_noe_proc_intr.TX_COHERENT_CNT); ++ seq_printf(seq, "TX_DLY_INT = %d\n", mdrv_noe_proc_intr.TX_DLY_INT_CNT); ++ seq_printf(seq, "RING3_RX_DLY_INT = %d\n", mdrv_noe_proc_intr.RING3_RX_DLY_INT_CNT); ++ seq_printf(seq, "RING2_RX_DLY_INT = %d\n", mdrv_noe_proc_intr.RING2_RX_DLY_INT_CNT); ++ seq_printf(seq, "RING1_RX_DLY_INT = %d\n", mdrv_noe_proc_intr.RING1_RX_DLY_INT_CNT); ++ seq_printf(seq, "RXD_ERROR = %d\n", mdrv_noe_proc_intr.RXD_ERROR_CNT); ++ seq_printf(seq, "ALT_RPLC_INT3 = %d\n", mdrv_noe_proc_intr.ALT_RPLC_INT3_CNT); ++ seq_printf(seq, "ALT_RPLC_INT2 = %d\n", mdrv_noe_proc_intr.ALT_RPLC_INT2_CNT); ++ seq_printf(seq, "ALT_RPLC_INT1 = %d\n", mdrv_noe_proc_intr.ALT_RPLC_INT1_CNT); ++ seq_printf(seq, "RX_DONE_INT3 = %d\n", mdrv_noe_proc_intr.RX_DONE_INT3_CNT); ++ seq_printf(seq, "RX_DONE_INT2 = %d\n", mdrv_noe_proc_intr.RX_DONE_INT2_CNT); ++ seq_printf(seq, "RX_DONE_INT1 = %d\n", mdrv_noe_proc_intr.RX_DONE_INT1_CNT); ++ seq_printf(seq, "RX_DONE_INT0 = %d\n", mdrv_noe_proc_intr.RX_DONE_INT0_CNT); ++ seq_printf(seq, "TX_DONE_INT3 = %d\n", mdrv_noe_proc_intr.TX_DONE_INT3_CNT); ++ seq_printf(seq, "TX_DONE_INT2 = %d\n", mdrv_noe_proc_intr.TX_DONE_INT2_CNT); ++ seq_printf(seq, "TX_DONE_INT1 = %d\n", mdrv_noe_proc_intr.TX_DONE_INT1_CNT); ++ seq_printf(seq, "TX_DONE_INT0 = %d\n", mdrv_noe_proc_intr.TX_DONE_INT0_CNT); ++ ++ memset(&mdrv_noe_proc_intr, 0, sizeof(mdrv_noe_proc_intr)); ++ } ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Intr_Dbg(struct inode *inode, struct file *file) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_NOE_INT_DBG) { ++ /* memset(&mdrv_noe_proc_intr, 0, sizeof(mdrv_noe_proc_intr)); */ ++ return single_open(file, _MDrv_NOE_PROC_Read_Intr_Dbg, NULL); ++ } else { ++ return 0; ++ } ++} ++ ++static ssize_t _MDrv_NOE_PROC_Write_Intr_Dbg(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ return 0; ++} ++ ++ ++ ++static int _MDrv_NOE_PROC_Read_Schedule(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & TASKLET_WORKQUEUE_SW) { ++ if (init_schedule == 1) ++ seq_printf(seq, ++ "Initialize Raeth with workqueque<%d>\n", ++ init_schedule); ++ else ++ seq_printf(seq, ++ "Initialize Raeth with tasklet<%d>\n", ++ init_schedule); ++ if (working_schedule == 1) ++ seq_printf(seq, ++ "Raeth is running at workqueque<%d>\n", ++ working_schedule); ++ else ++ seq_printf(seq, ++ "Raeth is running at tasklet<%d>\n", ++ working_schedule); ++ } ++ ++ return 0; ++} ++ ++static ssize_t _MDrv_NOE_PROC_Write_Schedule(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & TASKLET_WORKQUEUE_SW) { ++ char buf[2]; ++ int old; ++ ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ old = init_schedule; ++ init_schedule = kstrtol(buf, 10, NULL); ++ NOE_MSG_DUMP("ChangeRaethInitScheduleFrom <%d> to <%d>\n", old, init_schedule); ++ NOE_MSG_DUMP("Not running schedule at present !\n"); ++ ++ return count; ++ } else { ++ return 0; ++ } ++} ++ ++static int _MDrv_NOE_PROC_Open_Schedule(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Schedule, NULL); ++} ++ ++ ++ ++int _MDrv_NOE_PROC_Show_Eth_Count(struct seq_file *seq, void *v) ++{ ++ u8 i; ++ struct noe_pse_info pse; ++ struct noe_qdma_cnt info; ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ MHal_NOE_Get_Pse_Info(&pse); ++ seq_printf(seq, " <>\n"); ++ seq_printf(seq, "| FQ_PCNT_MIN : %010u |\n", pse.min_free_cnt); ++ seq_printf(seq, "| FQ_PCNT : %010u |\n", pse.free_cnt); ++ seq_printf(seq, "| FE_DROP_FQ : %010u |\n", pse.fq_drop_cnt); ++ seq_printf(seq, "| FE_DROP_FC : %010u |\n", pse.fc_drop_cnt); ++ seq_printf(seq, "| FE_DROP_PPE : %010u |\n", pse.ppe_drop_cnt); ++ seq_printf(seq, "\n <>\n"); ++ ++ if (ei_local->features & FE_QDMA) { ++ for (i = 0; i < NUM_PQ; i++) { ++ info.pq_no = i; ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_CNT, &info); ++ seq_printf(seq, "QDMA Q%02d PKT CNT: %010u, DROP CNT: %010u\n", i, info.pkt_cnt , info.drop_cnt); ++ } ++ } ++ seq_puts(seq, "\n"); ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Eth_Count(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Show_Eth_Count, NULL); ++} ++ ++int _MDrv_NOE_PROC_Show_Switch_Count(struct seq_file *seq, void *v) ++{ ++ int i =0; ++ struct noe_mac_info info; ++ for (i = 0; i < E_NOE_GE_MAC_MAX; i++) ++ { ++ memset(&info, 0, sizeof(struct noe_mac_info)); ++ MHal_NOE_Get_Mac_Info(i, &info); ++ seq_printf(seq, " GDMA%d: \n", i+1); ++ seq_printf(seq, " RX_GBCNT : %010u (Rx Good Bytes) \n", info.rx.good_cnt); ++ seq_printf(seq, " RX_GPCNT : %010u (Rx Good Pkts) \n", info.rx.good_pkt ); ++ seq_printf(seq, " RX_OERCNT : %010u (overflow error) \n", info.rx.overflow_err); ++ seq_printf(seq, " RX_FERCNT : %010u (FCS error) \n", info.rx.fcs_err); ++ seq_printf(seq, " RX_SERCNT : %010u (too short) \n", info.rx.ser_cnt); ++ seq_printf(seq, " RX_LERCNT : %010u (too long) \n", info.rx.ler_pkt); ++ seq_printf(seq, " RX_CERCNT : %010u (checksum error) \n", info.rx.chk_err); ++ seq_printf(seq, " RX_FCCNT : %010u (flow control) \n", info.rx.flow_ctrl); ++ seq_printf(seq, " TX_SKIPCNT: %010u (skip count) \n", info.tx.skip_cnt); ++ seq_printf(seq, " TX_COLCNT : %010u (collision count) \n", info.tx.collision_cnt); ++ seq_printf(seq, " TX_GBCNT : %010u (Tx Good Bytes) \n", info.tx.good_cnt); ++ seq_printf(seq, " TX_GPCNT : %010u (Tx Good Pkts) \n", info.tx.good_pkt); ++ seq_printf(seq, " ST_MCTRL : %010x (Control) \n", info.stat.control); ++ seq_printf(seq, " ST_STATUS : %010x (Status) \n", info.stat.status); ++ ++ } ++ ++ ++ seq_puts(seq, "\n"); ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Switch_Count(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Show_Switch_Count, NULL); ++} ++ ++ ++static int _MDrv_NOE_PROC_Show_Snmp(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & USER_SNMPD) { ++ ++ } ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Snmp(struct inode *inode, struct file *file) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & USER_SNMPD) ++ return single_open(file, _MDrv_NOE_PROC_Show_Snmp, NULL); ++ else ++ return 0; ++} ++ ++ ++ ++ ++ssize_t _MDrv_NOE_PROC_Write_Lro_Stats(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_SW_LRO) { ++ memset(lro_stats_cnt, 0, sizeof(lro_stats_cnt)); ++ memset(lro_flush_cnt, 0, sizeof(lro_flush_cnt)); ++ memset(lro_len_cnt1, 0, sizeof(lro_len_cnt1)); ++ /* memset(lro_len_cnt2, 0, sizeof(lro_len_cnt2)); */ ++ memset(aggregated, 0, sizeof(aggregated)); ++ lro_aggregated = 0; ++ lro_flushed = 0; ++ lro_nodesc = 0; ++ force_flush = 0; ++ tot_called1 = 0; ++ tot_called2 = 0; ++ NOE_MSG_DBG("clear lro cnt table\n"); ++ ++ return count; ++ } else { ++ return 0; ++ } ++} ++ ++int _MDrv_NOE_PROC_Show_Lro_Stats(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_SW_LRO) { ++ int i; ++ int tot_cnt = 0; ++ int tot_aggr = 0; ++ int ave_aggr = 0; ++ ++ seq_puts(seq, "LRO statistic dump:\n"); ++ seq_puts(seq, "Cnt: Kernel | Driver\n"); ++ for (i = 0; i <= MAX_AGGR; i++) { ++ tot_cnt = tot_cnt + lro_stats_cnt[i] + lro_flush_cnt[i]; ++ seq_printf(seq, " %d : %d %d\n", i, ++ lro_stats_cnt[i], lro_flush_cnt[i]); ++ tot_aggr = ++ tot_aggr + i * (lro_stats_cnt[i] + ++ lro_flush_cnt[i]); ++ } ++ ave_aggr = lro_aggregated / lro_flushed; ++ seq_printf(seq, "Total aggregated pkt: %d\n", lro_aggregated); ++ seq_printf(seq, "Flushed pkt: %d %d\n", lro_flushed, ++ force_flush); ++ seq_printf(seq, "Average flush cnt: %d\n", ave_aggr); ++ seq_printf(seq, "No descriptor pkt: %d\n\n\n", lro_nodesc); ++ ++ seq_puts(seq, "Driver flush pkt len:\n"); ++ seq_puts(seq, " Length | Count\n"); ++ for (i = 0; i < 15; i++) { ++ seq_printf(seq, "%d~%d: %d\n", i * 5000, ++ (i + 1) * 5000, lro_len_cnt1[i]); ++ } ++ seq_printf(seq, "Kernel flush: %d; Driver flush: %d\n", ++ tot_called2, tot_called1); ++ return 0; ++ } else { ++ return 0; ++ } ++} ++ ++static int _MDrv_NOE_PROC_Open_Lro_Stats(struct inode *inode, struct file *file) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_SW_LRO) ++ return single_open(file, _MDrv_NOE_PROC_Show_Lro_Stats, NULL); ++ else ++ return 0; ++} ++ ++ ++ ++ ++static void *_MDrv_NOE_PROC_Start_Tso_Len(struct seq_file *seq, loff_t *pos) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ seq_puts(seq, " Length | Count\n"); ++ if (*pos < 15) ++ return pos; ++ } ++ return NULL; ++} ++ ++static void *_MDrv_NOE_PROC_Get_Next_Tso_Len(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ (*pos)++; ++ if (*pos >= 15) ++ return NULL; ++ return pos; ++ } else { ++ return NULL; ++ } ++} ++ ++static void _MDrv_NOE_PROC_Stop_Tso_Len(struct seq_file *seq, void *v) ++{ ++ /* Nothing to do */ ++} ++ ++static int _MDrv_NOE_PROC_Show_Tso_Len(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ int i = *(loff_t *)v; ++ seq_printf(seq, "%8d ~ %8d: %8d\n", i * 5000, (i + 1) * 5000, tso_cnt[i]); ++ } ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_PROC_Open_Tso_Len(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &_MDrv_NOE_PROC_Set_Tso_Len_Ops); ++} ++ ++ssize_t _MDrv_NOE_PROC_Write_Tso_Len(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ memset(tso_cnt, 0, sizeof(tso_cnt)); ++ NOE_MSG_DBG("clear tso cnt table\n"); ++ return count; ++ } ++ else { ++ return 0; ++ } ++} ++ ++ ++static void *_MDrv_NOE_PROC_Start_Tso_Txd_Num(struct seq_file *seq, loff_t *pos) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ seq_puts(seq, "TXD | Count\n"); ++ if (*pos < (MAX_SKB_FRAGS / 2 + 1)) ++ return pos; ++ } ++ return NULL; ++} ++ ++static void *_MDrv_NOE_PROC_Get_Next_Tso_Txd_Num(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ (*pos)++; ++ if (*pos >= (MAX_SKB_FRAGS / 2 + 1)) ++ return NULL; ++ return pos; ++ } else { ++ return NULL; ++ } ++} ++ ++static void _MDrv_NOE_PROC_Stop_Tso_Txd_Num(struct seq_file *seq, void *v) ++{ ++ /* Nothing to do */ ++} ++ ++static int _MDrv_NOE_PROC_Show_Tso_Txd_Num(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_TSO) { ++ int i = *(loff_t *)v; ++ ++ seq_printf(seq, "%8d: %8d\n", i, txd_cnt[i]); ++ } ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_PROC_Open_Tso_Txd_Num(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &_MDrv_NOE_PROC_Set_Tso_Txd_Num_Ops); ++} ++ ++int _MDrv_NOE_PROC_Read_Rx_Ring(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ int i = 0, j = 0; ++ ++ seq_printf(seq, " 0x%08x , 0x%p\n", (unsigned int)ei_local->phy_rx_ring[0], (void *)ei_local->rx_ring[0]); ++ ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ seq_printf(seq, "%8d: %08x %08x %08x %08x\n", i, ++ *(int *)&ei_local->rx_ring[j][i].rxd_info1, ++ *(int *)&ei_local->rx_ring[j][i].rxd_info2, ++ *(int *)&ei_local->rx_ring[j][i].rxd_info3, ++ *(int *)&ei_local->rx_ring[j][i].rxd_info4); ++ } ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Rx_Ring(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Rx_Ring, NULL); ++} ++ ++ ++ ++ ++int _MDrv_NOE_PROC_Show_Tx_Ring(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ struct PDMA_txdesc *tx_ring; ++ int i = 0; ++ ++ ++ if (ei_local->features & FE_QDMA_TX) { ++ seq_printf(seq, "%8p,%8p \n", ei_local, ei_local->txd_pool); ++ seq_printf(seq, "cpu:%4d/rls:%4d \n",ei_local->tx_cpu_idx, ei_local->rls_cpu_idx); ++ for (i = 0; i < TOTAL_TXQ_NUM; i++) { ++ seq_printf(seq, "%4d: %4d/%4d(%4d)/%4d(%4d)/%d\n", ++ i, atomic_read(&ei_local->free_txd_num[i]), ++ ei_local->free_txd_head[i], ei_local->txd_pool_info[ei_local->free_txd_head[i]], ++ ei_local->free_txd_tail[i], ei_local->txd_pool_info[ei_local->free_txd_tail[i]], ++ ei_local->stats.min_free_txd[i]); ++ } ++ ++ for (i = 0; i < (GMAC1_TXQ_TXD_NUM + GMAC2_TXQ_TXD_NUM); i++) { ++ seq_printf(seq, "%4d:[%08x] %08x %08x %08x %08x \n", ++ i, ++ (ei_local->phy_txd_pool + i * QTXD_LEN), ++ *(int *)&ei_local->txd_pool[i].txd_info1, ++ *(int *)&ei_local->txd_pool[i].txd_info2, ++ *(int *)&ei_local->txd_pool[i].txd_info3, ++ *(int *)&ei_local->txd_pool[i].txd_info4); ++ } ++ } ++ else { ++ for (i = 0; i < NUM_TX_DESC; i++) { ++ tx_ring = &ei_local->tx_ring0[i]; ++ seq_printf(seq, "%4d: %08x %08x %08x %08x\n", i, ++ *(int *)&tx_ring->txd_info1, ++ *(int *)&tx_ring->txd_info2, ++ *(int *)&tx_ring->txd_info3, ++ *(int *)&tx_ring->txd_info4); ++ } ++ ++ ++ } ++ ++ return 0; ++} ++ ++static int _MDrv_NOE_PROC_Open_Tx_Ring(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Show_Tx_Ring, NULL); ++} ++ ++ ++static ssize_t _MDrv_NOE_PROC_Set_Gmac1_Phyid(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ int val = 0; ++ char if_name[64]; ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->netdev == NULL) ++ return 0; ++ strcpy(if_name, ei_local->netdev->name); ++ ++ if (ei_local->features & (FE_ETHTOOL)) { ++ char buf[32]; ++ struct net_device *cur_dev_p; ++ struct END_DEVICE *ei_local; ++ unsigned int phy_id; ++ ++ if (count > 32) ++ count = 32; ++ memset(buf, 0, 32); ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ ++ /* determine interface name */ ++ if (isalpha(buf[0])) { ++ val = sscanf(buf, "%4s %1d", if_name, &phy_id); ++ if (val == -1) ++ return -EFAULT; ++ } ++ else { ++ phy_id = kstrtol(buf, 10, NULL); ++ } ++ cur_dev_p = dev_get_by_name(&init_net, if_name); ++ ++ if (!cur_dev_p) ++ return -EFAULT; ++ ++ ei_local = netdev_priv(cur_dev_p); ++ ++ ei_local->mii_info.phy_id = (unsigned char)phy_id; ++ return count; ++ } else { ++ return 0; ++ } ++} ++ ++static ssize_t _MDrv_NOE_PROC_Set_Gmac2_Phyid(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ int val = 0; ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & (FE_ETHTOOL | FE_GE2_SUPPORT)) { ++ char buf[32]; ++ struct net_device *cur_dev_p; ++ struct PSEUDO_ADAPTER *p_pseudo_ad; ++ char if_name[64]; ++ unsigned int phy_id; ++ ++ if (count > 32) ++ count = 32; ++ memset(buf, 0, 32); ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ /* determine interface name */ ++ strcpy(if_name, ei_local->pseudo_dev->name); ++ if (isalpha(buf[0])) { ++ val = sscanf(buf, "%4s %1d", if_name, &phy_id); ++ if (val == -1) ++ return -EFAULT; ++ } else { ++ phy_id = kstrtol(buf, 10, NULL); ++ } ++ cur_dev_p = dev_get_by_name(&init_net, if_name); ++ ++ if (!cur_dev_p) ++ return -EFAULT; ++ p_pseudo_ad = netdev_priv(cur_dev_p); ++ p_pseudo_ad->mii_info.phy_id = (unsigned char)(phy_id & 0xFF); ++ return count; ++ } else { ++ return 0; ++ } ++} ++ ++static void *_MDrv_NOE_PROC_Start_Skb_Free(struct seq_file *seq, loff_t *pos) ++{ ++ if (*pos < NUM_TX_DESC) ++ return pos; ++ return NULL; ++} ++ ++static void *_MDrv_NOE_PROC_Get_Next_Skb_Free(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ (*pos)++; ++ if (*pos >= NUM_TX_DESC) ++ return NULL; ++ return pos; ++} ++ ++static void _MDrv_NOE_PROC_Stop_Skb_Free(struct seq_file *seq, void *offset) ++{ ++ /* Nothing to do */ ++} ++ ++static int _MDrv_NOE_PROC_Show_Skb_Free(struct seq_file *seq, void *offset) ++{ ++ int i = *(loff_t *)offset; ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ seq_printf(seq, "%8d: %08x\n", i, *(int *)&ei_local->skb_free[i]); ++ ++ return 0; ++} ++ ++ ++ ++static int _MDrv_NOE_PROC_Open_Skb_Free(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &_MDrv_NOE_PROC_Set_Skb_free_Ops); ++} ++ ++static void _MDrv_NOE_PROC_Dump_Reg(struct seq_file *s) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ struct noe_dma_info tx_ring[E_NOE_RING_MAX]; ++ struct noe_dma_info rx_ring; ++ struct noe_intr_info intr; ++ struct noe_pdma_dbg dbg_info; ++ int rx_usage; ++ int tx_usage = 0; ++ int i; ++ ++ seq_printf(s, "FEATURES : 0x%08x\n", ei_local->features); ++ seq_printf(s, "ARCH : 0x%08x\n", ei_local->architecture); ++ MHal_NOE_Get_Intr_Info(&intr); ++ rx_usage = _MDrv_NOE_PROC_Get_Ring_Usage(E_NOE_DMA_PACKET, E_NOE_PROC_RX, E_NOE_PROC_RING0); ++ ++ if (!(ei_local->features & FE_QDMA)) { ++ tx_usage = _MDrv_NOE_PROC_Get_Ring_Usage(E_NOE_DMA_PACKET, E_NOE_PROC_TX, E_NOE_PROC_RING0); ++ for (i = 0; i < E_NOE_RING_MAX; i++) { ++ MHal_NOE_LRO_Get_Ring_Info(E_NOE_DMA_PACKET, E_NOE_DIR_TX, E_NOE_RING_NO0, &tx_ring[i]); ++ } ++ } ++ else { ++ MHal_NOE_LRO_Get_Ring_Info(E_NOE_DMA_QUEUE, E_NOE_DIR_TX, E_NOE_RING_NO0, &tx_ring[0]); ++ } ++ ++ seq_printf(s, "P_INT_ENABLE : 0x%08x\n", intr.fe_intr_enable); ++ seq_printf(s, "P_INT_MASK : 0x%08x\n", intr.fe_intr_mask); ++ seq_printf(s, "P_INT_STATUS : 0x%08x\n", intr.fe_intr_status); ++ seq_printf(s, "Q_INT_ENABLE : 0x%08x\n", intr.qfe_intr_enable); ++ seq_printf(s, "Q_INT_MASK : 0x%08x\n", intr.qfe_intr_mask); ++ seq_printf(s, "Q_INT_STATUS : 0x%08x\n", intr.qfe_intr_status); ++ ++ if (!(ei_local->features & FE_QDMA)) ++ seq_printf(s, "TxRing PktCnt : %d/%d\n", tx_usage, NUM_TX_DESC); ++ ++ seq_printf(s, "RxRing PktCnt: %d/%d\n\n", rx_usage, NUM_RX_DESC); ++ seq_printf(s, "DLY_INT_CFG : 0x%08x\n\n", intr.delay_intr_cfg); ++ ++ if (!(ei_local->features & FE_QDMA)) { ++ for (i = 0; i < 4; i++) { ++ seq_printf(s, "TX_BASE_PTR%02d : 0x%08x\n", i, (unsigned int)tx_ring[i].ring_st.base_adr); ++ seq_printf(s, "TX_MAX_CNT%02d : 0x%08x\n", i, tx_ring[i].ring_st.max_cnt); ++ seq_printf(s, "TX_CTX_IDX%02d : 0x%08x\n", i, tx_ring[i].ring_st.cpu_idx); ++ seq_printf(s, "TX_DTX_IDX%02d : 0x%08x\n\n", i, tx_ring[i].ring_st.dma_idx); ++ } ++ } ++ else { ++ i = 0; ++ seq_printf(s, "CTX_PTR%02d : 0x%08x\n", i, (unsigned int)tx_ring[i].adr_st.ctx_adr); ++ seq_printf(s, "DTX_PTR%02d : 0x%08x\n", i, (unsigned int)tx_ring[i].adr_st.dtx_adr); ++ seq_printf(s, "CRX_PTR%02d : 0x%08x\n", i, (unsigned int)tx_ring[i].adr_st.crx_adr); ++ seq_printf(s, "DRX_PTR%02d : 0x%08x\n\n", i, (unsigned int)tx_ring[i].adr_st.drx_adr); ++ } ++ ++ for (i = 0; i < 4; i++) { ++ if ((i >= 1) && (!(ei_local->features & FE_HW_LRO))) { ++ break; ++ } ++ MHal_NOE_LRO_Get_Ring_Info(E_NOE_DMA_PACKET, E_NOE_DIR_RX, i, &rx_ring); ++ seq_printf(s, "RX_BASE_PTR%02d : 0x%08x\n", i, (unsigned int)rx_ring.ring_st.base_adr); ++ seq_printf(s, "RX_MAX_CNT%02d : 0x%08x\n", i, rx_ring.ring_st.max_cnt); ++ seq_printf(s, "RX_CALC_IDX%02d : 0x%08x\n", i, rx_ring.ring_st.cpu_idx); ++ seq_printf(s, "RX_DRX_IDX%02d : 0x%08x\n\n", i, rx_ring.ring_st.dma_idx); ++ } ++ ++ MHal_NOE_Get_Pdma_Info(E_NOE_PDMA_INFO_DBG, &dbg_info); ++ seq_printf(s, "RX_DBG0 : 0x%08x\n", dbg_info.rx[0]); ++ seq_printf(s, "RX_DBG1 : 0x%08x\n", dbg_info.rx[1]); ++ ++ if (ei_local->features & FE_ETHTOOL) ++ seq_printf(s, "The current PHY address selected by ethtool is %d\n", MDrv_NOE_ETHTOOL_Get_Phy_Address()); ++} ++ ++static int _MDrv_NOE_PROC_Read_Regs(struct seq_file *seq, void *offset) ++{ ++ _MDrv_NOE_PROC_Dump_Reg(seq); ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_PROC_Open_Gmac(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Regs, NULL); ++} ++ ++static int _MDrv_NOE_PROC_Read_Gmac2(struct seq_file *seq, void *offset) ++{ ++ struct net_device *cur_dev_p; ++ struct PSEUDO_ADAPTER *p_pseudo_ad; ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ cur_dev_p = dev_get_by_name(&init_net, ei_local->pseudo_dev->name); ++ ++ if (!cur_dev_p) ++ return -EFAULT; ++ p_pseudo_ad = netdev_priv(cur_dev_p); ++ ++ seq_printf(seq, "%d\n", p_pseudo_ad->mii_info.phy_id); ++ return 0; ++ } ++ return -EFAULT; ++} ++ ++static int _MDrv_NOE_PROC_Open_Gmac2(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Gmac2, NULL); ++} ++ ++ ++static int _MDrv_NOE_PROC_Read_Pin_Mux(struct seq_file *seq, void *offset) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ seq_printf(seq, "Current Setting : \"%d\" \n", ei_local->pin_mux); ++ seq_printf(seq, "%d: MAC1 TO ChipTop\n", E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP); ++ seq_printf(seq, "%d: MAC2 TO ChipTop\n", E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP); ++ seq_printf(seq, "%d: MAC1 TO ChipTop, MAC2 TO CHIPTOP\n", E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP_GE2_TO_CHIPTOP); ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_PROC_Open_Pin_Mux(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Pin_Mux, NULL); ++} ++ ++static ssize_t _MDrv_NOE_PROC_Write_Pin_Mux(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ char buf[4]; ++ int mux = NOE_CFG_PIN_MUX_SEL; ++ ++ if (count > 2) ++ return -EFAULT; ++ ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ ++ if ((buf[0] <='0') || (buf[0] >= '9')) ++ return -EFAULT; ++ ++ mux = buf[0] - '0'; ++ NOE_MSG_DUMP("Pin Mux = %d, %s, %c, %zu\n", mux, buf, buf[0], count); ++ ++ if ((mux <= E_NOE_SEL_PIN_MUX_INVALID) || (mux >= E_NOE_SEL_PIN_MUX_MAX)) ++ return -EFAULT; ++ ++ ei_local->pin_mux = mux; ++ MHal_NOE_Set_Pin_Mux(ei_local->pin_mux); ++ ++ return 0; ++} ++ ++static ssize_t _MDrv_NOE_PROC_Write_Log_Ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *data) ++{ ++#define NOE_LOG_MAX_CNT (2) ++ char buf[4]; ++ unsigned char level = 0xFF; ++ ++ if (count > (NOE_LOG_MAX_CNT + 1)) ++ return -EFAULT; ++ ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ ++ if ((buf[0] >='0') && (buf[0] <= '9')) ++ level = buf[0] - '0'; ++ else if ((buf[0] >='A') && (buf[0] <= 'F')) ++ level = buf[0] - 'A' + 10; ++ else if ((buf[0] >='a') && (buf[0] <= 'f')) ++ level = buf[0] - 'a' + 10; ++ ++ if (strlen(buf) >= NOE_LOG_MAX_CNT) { ++ if ((buf[1] >='0') && (buf[1] <= '9')) ++ level = (buf[1] - '0')+ (level << 4); ++ else if ((buf[1] >='A') && (buf[1] <= 'F')) ++ level = (buf[1] - 'A' + 10) + (level << 4); ++ else if ((buf[1] >='a') && (buf[0] <= 'f')) ++ level = (buf[1] - 'a' + 10) + (level << 4); ++ } ++ ++ if (level != 0xFF) { ++ MDrv_NOE_LOG_Set_Level(level); ++ return 0; ++ } ++ ++ return -EFAULT; ++} ++ ++static int _MDrv_NOE_PROC_Read_Log_Ctrl(struct seq_file *seq, void *offset) ++{ ++ seq_printf(seq, "0x%X\n", MDrv_NOE_LOG_Get_Level()); ++ return 0; ++} ++ ++ ++static int _MDrv_NOE_PROC_Open_Log_Ctrl(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Read_Log_Ctrl, NULL); ++} ++ ++static int _MDrv_NOE_PROC_Show_QoS(struct seq_file *seq, void *v) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ struct noe_qdma_fq qdma_fq; ++ struct noe_qdma_sch qdma_sch; ++ struct noe_qdma_fsm qdma_fsm; ++ struct noe_qdma_fc qdma_fc; ++ struct noe_qdma_vq qdma_vq; ++ struct noe_qdma_pq qdma_pq; ++ unsigned int i, queue; ++ ++ if (ei_local->features & FE_QDMA) { ++ seq_puts(seq, "==== General Information ====\n"); ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_FQ, &qdma_fq); ++ seq_printf(seq, "SW TXD: %d/%d; HW TXD: %d/%d\n", qdma_fq.sw_fq, NUM_TX_DESC, qdma_fq.hw_fq, NUM_QDMA_PAGE); ++ seq_printf(seq, "SW TXD virtual start address: 0x%p\n", ei_local->txd_pool); ++ seq_printf(seq, "HW TXD virtual start address: 0x%p\n\n", free_head); ++ ++ seq_puts(seq, "==== Scheduler Information ====\n"); ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_SCH, &qdma_sch); ++ seq_printf(seq, "SCH1 rate control:%d. Rate is %dKbps.\n", qdma_sch.sch[0].max_en,qdma_sch.sch[0].max_rate); ++ seq_printf(seq, "SCH2 rate control:%d. Rate is %dKbps.\n\n", qdma_sch.sch[1].max_en, qdma_sch.sch[1].max_rate); ++ ++ seq_puts(seq, "==== Physical Queue Information ====\n"); ++ for (queue = 0; queue < NUM_PQ; queue++) { ++ qdma_pq.queue = queue; ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_PQ, &qdma_pq); ++ seq_printf(seq, "Queue#%d Information:\n", queue); ++ seq_printf(seq, "%d packets in the queue; head address is 0x%08x, tail address is 0x%08x.\n", qdma_pq.txd_cnt, qdma_pq.queue_head, qdma_pq.queue_tail); ++ seq_printf(seq, "HW_RESV: %d; SW_RESV: %d; SCH: %d; Weighting: %d\n", qdma_pq.hw_resv, qdma_pq.sw_resv, qdma_pq.sch, qdma_pq.weight); ++ seq_printf(seq, "Min_Rate_En is %d, Min_Rate is %dKbps; Max_Rate_En is %d, Max_Rate is %dKbps.\n\n", qdma_pq.min_en, qdma_pq.min_rate, qdma_pq.max_en, qdma_pq.max_rate); ++ } ++ if (ei_local->features & FE_HW_SFQ) { ++ seq_puts(seq, "==== Virtual Queue Information ====\n"); ++ seq_printf(seq, "VQTX_TB_BASE_0:0x%p;VQTX_TB_BASE_1:0x%p;VQTX_TB_BASE_2:0x%p;VQTX_TB_BASE_3:0x%p\n", sfq0, sfq1, sfq2, sfq3); ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_VQ, &qdma_vq); ++ seq_printf(seq, "VQTX_NUM_0:0x%01x;VQTX_NUM_1:0x%01x;VQTX_NUM_2:0x%01x;VQTX_NUM_3:0x%01x\n\n", ++ qdma_vq.vq_num[E_NOE_VQ_NO0], qdma_vq.vq_num[E_NOE_VQ_NO1], qdma_vq.vq_num[E_NOE_VQ_NO2], qdma_vq.vq_num[E_NOE_VQ_NO3] ); ++ } ++ ++ seq_puts(seq, "==== Flow Control Information ====\n"); ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_FC, &qdma_fc); ++ seq_printf(seq, "SW_DROP_EN:%x; SW_DROP_FFA:%d; SW_DROP_MODE:%d\n", qdma_fc.sw.en, qdma_fc.sw.ffa, qdma_fc.sw.mode); ++ seq_printf(seq, "HW_DROP_EN:%x; HW_DROP_FFA:%d; HW_DROP_MODE:%d\n", qdma_fc.hw.en, qdma_fc.hw.ffa, qdma_fc.hw.mode); ++ seq_printf(seq, "SW_DROP_FSTVQ_MODE:%d;SW_DROP_FSTVQ:%d\n", qdma_fc.sw.fst_vq_mode, qdma_fc.sw.fst_vq_en); ++ seq_printf(seq, "HW_DROP_FSTVQ_MODE:%d;HW_DROP_FSTVQ:%d\n", qdma_fc.hw.fst_vq_mode, qdma_fc.hw.fst_vq_en); ++ ++ seq_puts(seq, "\n==== FSM Information\n"); ++ MHal_NOE_Get_Qdma_Info(E_NOE_QDMA_INFO_FSM, &qdma_fsm); ++ seq_printf(seq, "VQTB_FSM:0x%01x\n", qdma_fsm.vqtb); ++ seq_printf(seq, "FQ_FSM:0x%01x\n", qdma_fsm.fq); ++ seq_printf(seq, "TX_FSM:0x%01x\n", qdma_fsm.tx); ++ seq_printf(seq, "RX_FSM:0x%01x\n", qdma_fsm.rx); ++ seq_printf(seq, "RLS_FSM:0x%01x\n", qdma_fsm.rls); ++ seq_printf(seq, "FWD_FSM:0x%01x\n", qdma_fsm.fwd); ++ ++ seq_puts(seq, "==== M2Q Information ====\n"); ++ for (i = 0; i < NUM_PQ; i += 8) { ++ seq_printf(seq, "(%2d,%2d)(%2d,%2d)(%2d,%2d)(%2d,%2d)(%2d,%2d)(%2d,%2d)(%2d,%2d)(%2d,%2d)\n", ++ i, M2Q_table[i], i + 1, M2Q_table[i + 1], ++ i + 2, M2Q_table[i + 2], i + 3, ++ M2Q_table[i + 3], i + 4, M2Q_table[i + 4], ++ i + 5, M2Q_table[i + 5], i + 6, ++ M2Q_table[i + 6], i + 7, M2Q_table[i + 7]); ++ } ++ ++ return 0; ++ } ++ else { ++ return 0; ++ } ++} ++ ++static int _MDrv_NOE_PROC_Open_QoS(struct inode *inode, struct file *file) ++{ ++ return single_open(file, _MDrv_NOE_PROC_Show_QoS, NULL); ++} ++ ++ ++ ++int MDrv_NOE_Update_Tso_Len(int tso_len) ++{ ++ ++ if(tso_len > 70000) { ++ tso_cnt[14]++; ++ }else if(tso_len > 65000) { ++ tso_cnt[13]++; ++ }else if(tso_len > 60000) { ++ tso_cnt[12]++; ++ }else if(tso_len > 55000) { ++ tso_cnt[11]++; ++ }else if(tso_len > 50000) { ++ tso_cnt[10]++; ++ }else if(tso_len > 45000) { ++ tso_cnt[9]++; ++ }else if(tso_len > 40000) { ++ tso_cnt[8]++; ++ }else if(tso_len > 35000) { ++ tso_cnt[7]++; ++ }else if(tso_len > 30000) { ++ tso_cnt[6]++; ++ }else if(tso_len > 25000) { ++ tso_cnt[5]++; ++ }else if(tso_len > 20000) { ++ tso_cnt[4]++; ++ }else if(tso_len > 15000) { ++ tso_cnt[3]++; ++ }else if(tso_len > 10000) { ++ tso_cnt[2]++; ++ }else if(tso_len > 5000) { ++ tso_cnt[1]++; ++ }else { ++ tso_cnt[0]++; ++ } ++ ++ return 0; ++} ++ ++ ++int MDrv_NOE_PROC_Init(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = NULL; ++ int i = 0; ++ unsigned char enable = 0; ++ _noe_proc_dev = dev; ++ ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (!proc_reg_dir) ++ proc_reg_dir = proc_mkdir(NOE_PROC_DIR, NULL); ++ ++ if (ei_local->features & FE_HW_LRO) ++ MDrv_NOE_LRO_PROC_Init(proc_reg_dir, dev); ++ ++ for (i = 0; i < E_NOE_PROC_MAX; i++) { ++ enable = 0; ++ switch(i) { ++ case E_NOE_PROC_GMAC2: ++ if (ei_local->features & (FE_ETHTOOL | FE_GE2_SUPPORT)) ++ enable = 1; ++ break; ++ case E_NOE_PROC_NUM_OF_TXD: ++ case E_NOE_PROC_TSO_LEN: ++ if (ei_local->features & FE_TSO) ++ enable = 1; ++ break; ++ case E_NOE_PROC_LRO_STATS: ++ if (ei_local->features & FE_SW_LRO) ++ enable = 1; ++ break; ++ case E_NOE_PROC_SNMP: ++ if (ei_local->features & USER_SNMPD) ++ enable = 1; ++ break; ++ case E_NOE_PROC_SCHE: ++ if (ei_local->features & TASKLET_WORKQUEUE_SW) ++ enable = 1; ++ break; ++ case E_NOE_PROC_INT_DBG: ++ if (ei_local->features & FE_NOE_INT_DBG) ++ enable = 1; ++ break; ++ default: ++ enable = 1; ++ break; ++ } ++ ++ if (enable == 1) { ++ proc_entry[i] = proc_create(noe_proc_name[i], 0, proc_reg_dir, &noe_proc_fops[i]); ++ if (!proc_entry[i]) ++ NOE_MSG_ERR("!! FAIL to create %s PROC !!\n", noe_proc_name[i]); ++ } ++ } ++ return 0; ++} ++ ++ ++ ++void MDrv_NOE_PROC_Exit(void) ++{ ++ int i = 0; ++ struct END_DEVICE *ei_local = netdev_priv(_noe_proc_dev); ++ ++ if (ei_local->features & FE_HW_LRO) ++ MDrv_NOE_LRO_PROC_Exit(proc_reg_dir); ++ ++ for (i = 0; i < E_NOE_PROC_MAX; i++) { ++ if (!proc_entry[i]) { ++ remove_proc_entry(noe_proc_name[i], proc_reg_dir); ++ proc_entry[i] = NULL; ++ } ++ } ++} ++ ++ ++EXPORT_SYMBOL(proc_reg_dir); ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_proc.h b/drivers/sstar/noe/drv/eth/mdrv_noe_proc.h +new file mode 100755 +index 000000000000..2416888c321f +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_proc.h +@@ -0,0 +1,161 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_PROC.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_NOE_PROC_H_ ++#define _MDRV_NOE_PROC_H_ ++ ++ ++#define NOE_PROC_LRO_STATS "lro_stats" ++#define NOE_PROC_TSO_LEN "tso_len" ++#define NOE_PROC_DIR "noe" ++#define NOE_PROC_SKBFREE "skb_free" ++#define NOE_PROC_TX_RING "tx_ring" ++#define NOE_PROC_RX_RING "rx_ring" ++#define NOE_PROC_LRO_RX_RING1 "lro_rx_ring1" ++#define NOE_PROC_LRO_RX_RING2 "lro_rx_ring2" ++#define NOE_PROC_LRO_RX_RING3 "lro_rx_ring3" ++#define NOE_PROC_NUM_OF_TXD "num_of_txd" ++#define NOE_PROC_TSO_LEN "tso_len" ++#define NOE_PROC_LRO_STATS "lro_stats" ++#define NOE_PROC_HW_LRO_STATS "hw_lro_stats" ++#define NOE_PROC_HW_LRO_AUTO_TLB "hw_lro_auto_tlb" ++#define NOE_PROC_HW_IO_COHERENT "hw_iocoherent" ++#define NOE_PROC_GMAC "gmac" ++#define NOE_PROC_GMAC2 "gmac2" ++#define NOE_PROC_CP0 "cp0" ++#define NOE_PROC_QSCH "qsch" ++#define NOE_PROC_READ_VAL "regread_value" ++#define NOE_PROC_WRITE_VAL "regwrite_value" ++#define NOE_PROC_ADDR "reg_addr" ++#define NOE_PROC_CTL "procreg_control" ++#define NOE_PROC_RXDONE_INTR "rxdone_intr_count" ++#define NOE_PROC_ESW_INTR "esw_intr_count" ++#define NOE_PROC_ESW_CNT "esw_cnt" ++#define NOE_PROC_ETH_CNT "eth_cnt" ++#define NOE_PROC_SNMP "snmp" ++#define NOE_PROC_SET_LAN_IP "set_lan_ip" ++#define NOE_PROC_SCHE "schedule" /* TASKLET_WORKQUEUE_SW */ ++#define NOE_PROC_QDMA "qdma" ++#define NOE_PROC_INT_DBG "int_dbg" ++#define NOE_PROC_PIN_MUX "mux" ++#define NOE_PROC_LOG_CTRL "log" ++ ++struct mdrv_noe_proc_intr { ++ unsigned int RX_COHERENT_CNT; ++ unsigned int RX_DLY_INT_CNT; ++ unsigned int TX_COHERENT_CNT; ++ unsigned int TX_DLY_INT_CNT; ++ unsigned int RING3_RX_DLY_INT_CNT; ++ unsigned int RING2_RX_DLY_INT_CNT; ++ unsigned int RING1_RX_DLY_INT_CNT; ++ unsigned int RXD_ERROR_CNT; ++ unsigned int ALT_RPLC_INT3_CNT; ++ unsigned int ALT_RPLC_INT2_CNT; ++ unsigned int ALT_RPLC_INT1_CNT; ++ unsigned int RX_DONE_INT3_CNT; ++ unsigned int RX_DONE_INT2_CNT; ++ unsigned int RX_DONE_INT1_CNT; ++ unsigned int RX_DONE_INT0_CNT; ++ unsigned int TX_DONE_INT3_CNT; ++ unsigned int TX_DONE_INT2_CNT; ++ unsigned int TX_DONE_INT1_CNT; ++ unsigned int TX_DONE_INT0_CNT; ++}; ++ ++ ++ ++struct PDMA_LRO_AUTO_TLB_INFO0_T { ++ unsigned int DTP:16; ++ unsigned int STP:16; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO1_T { ++ unsigned int SIP0:32; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO2_T { ++ unsigned int SIP1:32; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO3_T { ++ unsigned int SIP2:32; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO4_T { ++ unsigned int SIP3:32; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO5_T { ++ unsigned int VLAN_VID0:32; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO6_T { ++ unsigned int VLAN_VID1:16; ++ unsigned int VLAN_VID_VLD:4; ++ unsigned int CNT:12; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO7_T { ++ unsigned int DW_LEN:32; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO8_T { ++ unsigned int DIP_ID:2; ++ unsigned int IPV6:1; ++ unsigned int IPV4:1; ++ unsigned int RESV:27; ++ unsigned int VALID:1; ++}; ++ ++struct PDMA_LRO_AUTO_TLB_INFO { ++ struct PDMA_LRO_AUTO_TLB_INFO0_T auto_tlb_info0; ++ struct PDMA_LRO_AUTO_TLB_INFO1_T auto_tlb_info1; ++ struct PDMA_LRO_AUTO_TLB_INFO2_T auto_tlb_info2; ++ struct PDMA_LRO_AUTO_TLB_INFO3_T auto_tlb_info3; ++ struct PDMA_LRO_AUTO_TLB_INFO4_T auto_tlb_info4; ++ struct PDMA_LRO_AUTO_TLB_INFO5_T auto_tlb_info5; ++ struct PDMA_LRO_AUTO_TLB_INFO6_T auto_tlb_info6; ++ struct PDMA_LRO_AUTO_TLB_INFO7_T auto_tlb_info7; ++ struct PDMA_LRO_AUTO_TLB_INFO8_T auto_tlb_info8; ++}; ++ ++ ++ ++int MDrv_NOE_Update_Tso_Len(int tso_len); ++int MDrv_NOE_PROC_Init(struct net_device *dev); ++void MDrv_NOE_PROC_Exit(void); ++#if FE_HW_LRO ++int MDrv_NOE_LRO_PROC_Init(struct proc_dir_entry *proc_reg_dir, struct net_device *dev); ++void MDrv_NOE_LRO_PROC_Exit(struct proc_dir_entry *proc_reg_dir); ++void MDrv_NOE_LRO_PROC_Update_Flush_Stats(unsigned int ring_num, struct PDMA_rxdesc *rx_ring); ++void MDrv_NOE_LRO_PROC_Update_Stats(unsigned int ring_num, struct PDMA_rxdesc *rx_ring); ++#else ++static inline int MDrv_NOE_LRO_PROC_Init(struct proc_dir_entry *proc_reg_dir, struct net_device *dev) { return 0;} ++static inline void MDrv_NOE_LRO_PROC_Exit(struct proc_dir_entry *proc_reg_dir) {} ++static inline void MDrv_NOE_LRO_PROC_Update_Flush_Stats(unsigned int ring_num, struct PDMA_rxdesc *rx_ring) {} ++static inline void MDrv_NOE_LRO_PROC_Update_Stats(unsigned int ring_num, struct PDMA_rxdesc *rx_ring) {} ++#endif /* FE_HW_LRO */ ++ ++#endif /* _MDRV_NOE_PROC_H_ */ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_qdma.c b/drivers/sstar/noe/drv/eth/mdrv_noe_qdma.c +new file mode 100755 +index 000000000000..42f8a3c8c56b +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_qdma.c +@@ -0,0 +1,1280 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 Mstar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDrv_NOE_PDMA.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include "mdrv_noe.h" ++#include "mdrv_noe_nat.h" ++#include "mdrv_noe_dma.h" ++#include "mhal_noe_reg.h" ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++/* skb->mark to queue mapping table */ ++struct QDMA_txdesc *free_head; ++ ++/* ioctl */ ++unsigned int M2Q_table[64] = { 0 }; ++EXPORT_SYMBOL(M2Q_table); ++unsigned int lan_wan_separate; ++EXPORT_SYMBOL(lan_wan_separate); ++struct sk_buff *magic_id = (struct sk_buff *)0xFFFFFFFF; ++ ++/* CONFIG_HW_SFQ */ ++unsigned int web_sfq_enable; ++#define HW_SFQ_UP 3 ++#define HW_SFQ_DL 1 ++ ++#define sfq_debug 0 ++struct SFQ_table *sfq0; ++struct SFQ_table *sfq1; ++struct SFQ_table *sfq2; ++struct SFQ_table *sfq3; ++ ++#define KSEG1 0xa0000000 ++#define PHYS_TO_VIRT(x) phys_to_virt(x) ++#define VIRT_TO_PHYS(x) virt_to_phys(x) ++/* extern void set_fe_dma_glo_cfg(void); */ ++struct parse_result sfq_parse_result; ++ ++ ++ ++ ++static inline unsigned int _MDrv_NOE_QDMA_Calc_Frag_Txd_Num(unsigned int size) ++{ ++ unsigned int frag_txd_num = 0; ++ ++ if (size == 0) ++ return 0; ++ while (size > 0) { ++ if (size > MAX_QTXD_LEN) { ++ frag_txd_num++; ++ size -= MAX_QTXD_LEN; ++ } else { ++ frag_txd_num++; ++ size = 0; ++ } ++ } ++ return frag_txd_num; ++} ++ ++ ++static inline int _MDrv_NOE_QDMA_Get_Free_Txd(struct END_DEVICE *ei_local, int ring_no) ++{ ++ unsigned int tmp_idx; ++ ++ tmp_idx = ei_local->free_txd_head[ring_no]; ++ ei_local->free_txd_head[ring_no] = ei_local->txd_pool_info[tmp_idx]; ++ atomic_sub(1, &ei_local->free_txd_num[ring_no]); ++ return tmp_idx; ++} ++ ++static inline unsigned int _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(struct END_DEVICE *ei_local, unsigned int idx) ++{ ++ return ei_local->phy_txd_pool + (idx * QTXD_LEN); ++} ++ ++ ++static inline void _MDrv_NOE_QDMA_Put_Back_Free_Txd(struct END_DEVICE *ei_local, int ring_no, int free_txd_idx) ++{ ++ ei_local->txd_pool_info[ei_local->free_txd_tail[ring_no]] = free_txd_idx; ++ ei_local->free_txd_tail[ring_no] = free_txd_idx; ++} ++ ++static void _MDrv_NOE_QDMA_Init_Free_Txd(struct END_DEVICE *ei_local) ++{ ++ int i; ++ ++ for (i = 0; i < GMAC1_TXQ_NUM; i++) { ++ atomic_set(&ei_local->free_txd_num[i], GMAC1_TXQ_TXD_NUM); ++ ei_local->free_txd_head[i] = GMAC1_TXQ_TXD_NUM * i; ++ ei_local->free_txd_tail[i] = GMAC1_TXQ_TXD_NUM * (i + 1) - 1; ++ ei_local->stats.min_free_txd[i] = GMAC1_TXQ_TXD_NUM; ++ } ++ for (i = 0; i < GMAC2_TXQ_NUM; i++) { ++ atomic_set(&ei_local->free_txd_num[i + GMAC1_TXQ_NUM], GMAC2_TXQ_TXD_NUM); ++ ei_local->free_txd_head[i + GMAC1_TXQ_NUM] = GMAC1_TXD_NUM + GMAC2_TXQ_TXD_NUM * i; ++ ei_local->free_txd_tail[i + GMAC1_TXQ_NUM] = GMAC1_TXD_NUM + GMAC2_TXQ_TXD_NUM * (i + 1) - 1; ++ ei_local->stats.min_free_txd[i + GMAC1_TXQ_NUM] = GMAC2_TXQ_TXD_NUM; ++ } ++} ++ ++static inline int _MDrv_NOE_QDMA_Map_Ring_No(int txd_idx) ++{ ++ int i; ++ ++ if (txd_idx < GMAC1_TXD_NUM) { ++ for (i = 0; i < GMAC1_TXQ_NUM; i++) { ++ if (txd_idx < (GMAC1_TXQ_TXD_NUM * (i + 1))) ++ return i; ++ } ++ } ++ ++ txd_idx -= GMAC1_TXD_NUM; ++ for (i = 0; i < GMAC2_TXQ_NUM; i++) { ++ if (txd_idx < (GMAC2_TXQ_TXD_NUM * (i + 1))) ++ return (i + GMAC1_TXQ_NUM); ++ } ++ NOE_MSG_ERR("txd index out of range\n"); ++ return 0; ++} ++ ++bool _MDrv_NOE_QDMA_Alloc_Txd(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned int txd_idx; ++ struct noe_dma_info dma_info; ++ int i = 0; ++#if 0 ++ ei_local->txd_pool = dma_alloc_coherent(&ei_local->qdma_pdev->dev, QTXD_LEN * NUM_TX_DESC, &ei_local->phy_txd_pool, GFP_KERNEL); ++#else ++{ ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++ mem_info.length = QTXD_LEN * NUM_TX_DESC; ++ strcpy(mem_info.name, "txd_pool"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ NOE_MSG_ERR("unable to allocate DMEM for %s!! error=%d\n", mem_info.name ,ret); ++ } ++ ei_local->phy_txd_pool = (dma_addr_t)((size_t)mem_info.phys); ++ ei_local->txd_pool = (void *)((size_t)mem_info.kvirt); ++} ++#endif ++ ++ NOE_MSG_DBG("[QUE][TX_DESC] num=%d vir=0x%p phy_txd_pool=0x%p len=%x\n", NUM_TX_DESC, ei_local->txd_pool, (void *)ei_local->phy_txd_pool, QTXD_LEN); ++ ++ if (!ei_local->txd_pool) { ++ NOE_MSG_ERR("adapter->txd_pool allocation failed!\n"); ++ return 0; ++ } ++ NOE_MSG_DBG("skb_free: 0x%p.\n", ei_local->skb_free); ++ /* set all txd_pool_info to 0. */ ++ for (i = 0; i < NUM_TX_DESC; i++) { ++ ei_local->skb_free[i] = 0; ++ ei_local->txd_pool_info[i] = i + 1; ++ ei_local->txd_pool[i].txd_info3.LS_bit = 1; ++ ei_local->txd_pool[i].txd_info3.OWN_bit = 1; ++ } ++ Chip_Flush_MIU_Pipe(); //L3 ++ ++ _MDrv_NOE_QDMA_Init_Free_Txd(ei_local); ++ ++ /* get free txd from txd pool */ ++ txd_idx = _MDrv_NOE_QDMA_Get_Free_Txd(ei_local, 0); ++ ei_local->tx_cpu_idx = txd_idx; ++ NOE_MSG_DBG("tx_cpu_idx = 0x%x \n", ei_local->tx_cpu_idx); ++ /* add null TXD for transmit */ ++ dma_info.adr_st.ctx_adr = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, txd_idx); ++ dma_info.adr_st.dtx_adr = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, txd_idx); ++ ++ /* get free txd from txd pool */ ++ txd_idx = _MDrv_NOE_QDMA_Get_Free_Txd(ei_local, 0); ++ ei_local->rls_cpu_idx = txd_idx; ++ NOE_MSG_DBG("rls_cpu_idx = 0x%x \n", ei_local->rls_cpu_idx); ++ /* add null TXD for release */ ++ dma_info.adr_st.crx_adr = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, txd_idx); ++ dma_info.adr_st.drx_adr = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, txd_idx); ++ ++ MHal_NOE_DMA_Init(E_NOE_DMA_QUEUE, E_NOE_DIR_TX, E_NOE_RING_NO0, &dma_info); ++ ++ return 1; ++} ++ ++bool _MDrv_NOE_QDMA_SFQ_Init(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ dma_addr_t sfq_phy[8]; ++ struct SFQ_table *sfq[8] = {NULL}; ++ struct noe_sfq_base adr_info; ++ int i = 0, j = 0; ++ int vq_num[8] = { ++ VQ_NUM0, ++ VQ_NUM1, ++ VQ_NUM2, ++ VQ_NUM3, ++ VQ_NUM4, ++ VQ_NUM5, ++ VQ_NUM6, ++ VQ_NUM7, ++ }; ++ ++ for (i = 0; i< 8; i++) { ++ sfq[i] = dma_alloc_coherent(&ei_local->qdma_pdev->dev, vq_num[i] * sizeof(struct SFQ_table), &sfq_phy[i], GFP_KERNEL); ++ if (unlikely(!sfq[i])) { ++ NOE_MSG_ERR("QDMA SFQ%d VQ not available...\n",i); ++ return 1; ++ } ++ memset(&sfq[i], 0x0, vq_num[i] * sizeof(struct SFQ_table)); ++ for (j = 0; j < vq_num[i]; j++) { ++ sfq[i][j].sfq_info1.VQHPTR = 0xdeadbeef; ++ sfq[i][j].sfq_info2.VQTPTR = 0xdeadbeef; ++ } ++ adr_info.phy_adr[i] = (MS_U32) sfq_phy[i]; ++ //NOE_MSG_DUMP("*****(sfq_phy,sfq_virt)[%d] = (0x%lx ,0x%llx)*******\n", i, sfq_phy[0], sfq[i]); ++ ++ } ++ ++ MHal_NOE_DMA_SFQ_Init(&adr_info); ++ return 0; ++} ++ ++static bool _MDrv_NOE_QDMA_Init_Fq(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ /* struct QDMA_txdesc *free_head = NULL; */ ++ dma_addr_t phy_free_head; ++ dma_addr_t phy_free_tail; ++ unsigned int *free_page_head = NULL; ++ dma_addr_t phy_free_page_head; ++ int i; ++ struct noe_fq_base info; ++#if 0 ++ free_head = dma_alloc_coherent(&ei_local->qdma_pdev->dev, NUM_QDMA_PAGE * QTXD_LEN, &phy_free_head, GFP_KERNEL); ++#else ++{ ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++ mem_info.length = NUM_QDMA_PAGE * QTXD_LEN; ++ strcpy(mem_info.name, "QDMA_DFQ"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ NOE_MSG_ERR("unable to allocate DMEM for %s!! error=%d\n", mem_info.name ,ret); ++ } ++ phy_free_head = (dma_addr_t)((size_t)mem_info.phys); ++ free_head = (void *)((size_t)mem_info.kvirt); ++} ++#endif ++ if (unlikely(!free_head)) { ++ NOE_MSG_ERR("QDMA FQ decriptor not available...\n"); ++ return 0; ++ } ++ ++ NOE_MSG_DBG("[QUE_TX][FreeQueue] phy=0x%x ,vir= 0x%p \n", phy_free_head, free_head); ++ memset(free_head, 0x0, QTXD_LEN * NUM_QDMA_PAGE); ++ Chip_Flush_MIU_Pipe(); //L3 ++ ++#if 0 ++ free_page_head = dma_alloc_coherent(&ei_local->qdma_pdev->dev, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &phy_free_page_head, GFP_KERNEL); ++#else ++ { ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++ mem_info.length = NUM_QDMA_PAGE * QDMA_PAGE_SIZE; ++ strcpy(mem_info.name, "QDMA_FQ"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ NOE_MSG_ERR("unable to allocate DMEM for %s!! error=%d\n", mem_info.name ,ret); ++ } ++ phy_free_page_head = mem_info.phys; ++ free_page_head = (phys_addr_t *)((size_t)mem_info.kvirt); ++ } ++#endif ++ if (unlikely(!free_page_head)) { ++ NOE_MSG_ERR("QDMA FQ page not available...\n"); ++ return 0; ++ } ++ for (i = 0; i < NUM_QDMA_PAGE; i++) { ++ free_head[i].txd_info1.SDP = (phy_free_page_head + (i * QDMA_PAGE_SIZE)); ++ if (i < (NUM_QDMA_PAGE - 1)) { ++ free_head[i].txd_info2.NDP = (phy_free_head + ((i + 1) * QTXD_LEN)); ++ NOE_MSG_DUMP("NDP[%4d] = 0x%x \n", i, free_head[i].txd_info2.NDP); ++ } ++ free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE; ++ } ++ Chip_Flush_MIU_Pipe(); //L3 ++ phy_free_tail = (phy_free_head + (u32)((NUM_QDMA_PAGE - 1) * QTXD_LEN)); ++ ++ NOE_MSG_DBG("phy_free(head, tail):(0x%p,0x%p)\n",(void *)phy_free_head, (void *)phy_free_tail); ++ ++ info.head = (MS_U32)phy_free_head; ++ info.tail = (MS_U32)phy_free_tail; ++ info.txd_num = NUM_TX_DESC; ++ info.page_num = NUM_QDMA_PAGE; ++ info.page_size = QDMA_PAGE_SIZE; ++ ++ MHal_NOE_DMA_FQ_Init(&info); ++ NOE_MSG_DBG("[TXD_NUM]GMAC1:%d; GMAC2:%d; Total:%d\n", GMAC1_TXD_NUM, GMAC2_TXD_NUM, NUM_TX_DESC); ++ ei_local->free_head = free_head; ++ ei_local->phy_free_head = phy_free_head; ++ ei_local->free_page_head = free_page_head; ++ ei_local->phy_free_page_head = phy_free_page_head; ++ ei_local->tx_ring_full = 0; ++ return 1; ++} ++ ++int sfq_prot; ++ ++#if (sfq_debug) ++int udp_source_port; ++int tcp_source_port; ++int ack_packt; ++#endif ++static int _MDrv_NOE_QDMA_SFQ_Parse_Net_Layer(struct sk_buff *skb) ++{ ++ struct vlan_hdr *vh_sfq = NULL; ++ struct ethhdr *eth_sfq = NULL; ++ struct iphdr *iph_sfq = NULL; ++ struct ipv6hdr *ip6h_sfq = NULL; ++ struct tcphdr *th_sfq = NULL; ++ struct udphdr *uh_sfq = NULL; ++ ++ memset(&sfq_parse_result, 0, sizeof(sfq_parse_result)); ++ eth_sfq = (struct ethhdr *)skb->data; ++ ether_addr_copy(sfq_parse_result.dmac, eth_sfq->h_dest); ++ ether_addr_copy(sfq_parse_result.smac, eth_sfq->h_source); ++ /* memcpy(sfq_parse_result.dmac, eth_sfq->h_dest, ETH_ALEN); */ ++ /* memcpy(sfq_parse_result.smac, eth_sfq->h_source, ETH_ALEN); */ ++ sfq_parse_result.eth_type = eth_sfq->h_proto; ++ ++ if (sfq_parse_result.eth_type == htons(ETH_P_8021Q)) { ++ sfq_parse_result.vlan1_gap = VLAN_HLEN; ++ vh_sfq = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ sfq_parse_result.eth_type = vh_sfq->h_vlan_encapsulated_proto; ++ } else { ++ sfq_parse_result.vlan1_gap = 0; ++ } ++ ++ /* set layer4 start addr */ ++ if ((sfq_parse_result.eth_type == htons(ETH_P_IP)) || (sfq_parse_result.eth_type == htons(ETH_P_PPP_SES) && sfq_parse_result.ppp_tag == htons(PPP_IP))) { ++ iph_sfq = (struct iphdr *)(skb->data + ETH_HLEN + (sfq_parse_result.vlan1_gap)); ++ ++ /* prepare layer3/layer4 info */ ++ memcpy(&sfq_parse_result.iph, iph_sfq, sizeof(struct iphdr)); ++ if (iph_sfq->protocol == IPPROTO_TCP) { ++ th_sfq = (struct tcphdr *)(skb->data + ETH_HLEN + (sfq_parse_result.vlan1_gap) + (iph_sfq->ihl * 4)); ++ memcpy(&sfq_parse_result.th, th_sfq, sizeof(struct tcphdr)); ++#if (sfq_debug) ++ tcp_source_port = ntohs(sfq_parse_result.th.source); ++ udp_source_port = 0; ++ /* tcp ack packet */ ++ if (ntohl(sfq_parse_result.iph.saddr) == 0xa0a0a04) ++ ack_packt = 1; ++ else ++ ack_packt = 0; ++#endif ++ sfq_prot = 2; /* IPV4_HNAPT */ ++ if (iph_sfq->frag_off & htons(IP_MF | IP_OFFSET)) ++ return 1; ++ } else if (iph_sfq->protocol == IPPROTO_UDP) { ++ uh_sfq = (struct udphdr *)(skb->data + ETH_HLEN + (sfq_parse_result.vlan1_gap) + iph_sfq->ihl * 4); ++ memcpy(&sfq_parse_result.uh, uh_sfq, sizeof(struct udphdr)); ++#if (sfq_debug) ++ udp_source_port = ntohs(sfq_parse_result.uh.source); ++ tcp_source_port = 0; ++ ack_packt = 0; ++#endif ++ sfq_prot = 2; /* IPV4_HNAPT */ ++ if (iph_sfq->frag_off & htons(IP_MF | IP_OFFSET)) ++ return 1; ++ } else { ++ sfq_prot = 1; ++ } ++ } else if (sfq_parse_result.eth_type == htons(ETH_P_IPV6) || (sfq_parse_result.eth_type == htons(ETH_P_PPP_SES) && sfq_parse_result.ppp_tag == htons(PPP_IPV6))) { ++ ip6h_sfq = (struct ipv6hdr *)(skb->data + ETH_HLEN + (sfq_parse_result.vlan1_gap)); ++ if (ip6h_sfq->nexthdr == NEXTHDR_TCP) { ++ sfq_prot = 4; /* IPV6_5T */ ++#if (sfq_debug) ++ if (ntohl(sfq_parse_result.ip6h.saddr.s6_addr32[3]) == ++ 8) ++ ack_packt = 1; ++ else ++ ack_packt = 0; ++#endif ++ } else if (ip6h_sfq->nexthdr == NEXTHDR_UDP) { ++#if (sfq_debug) ++ ack_packt = 0; ++#endif ++ sfq_prot = 4; /* IPV6_5T */ ++ ++ } else { ++ sfq_prot = 3; /* IPV6_3T */ ++ } ++ } ++ return 0; ++} ++ ++ ++ ++static int MDrv_NOE_QDMA_Eth_Send(struct END_DEVICE *ei_local, struct net_device *dev, struct sk_buff *skb, int gmac_no, int ring_no) ++{ ++ unsigned int length = skb->len; ++ struct QDMA_txdesc *cpu_ptr, *prev_cpu_ptr; ++ struct QDMA_txdesc dummy_desc; ++ struct PSEUDO_ADAPTER *p_ad; ++ unsigned long flags; ++ unsigned int next_txd_idx, qidx; ++ ++ cpu_ptr = &dummy_desc; ++ /* 2. prepare data */ ++ dma_sync_single_for_device(&ei_local->qdma_pdev->dev, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++ /* cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data); */ ++ cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data); ++ cpu_ptr->txd_info3.SDL = skb->len; ++ cpu_ptr->txd_info4.SDL = ((skb->len) >> 14); ++ if (ei_local->features & FE_HW_SFQ) { ++ _MDrv_NOE_QDMA_SFQ_Parse_Net_Layer(skb); ++ cpu_ptr->txd_info4.VQID0 = 1; /* 1:HW hash 0:CPU */ ++ cpu_ptr->txd_info3.PROT = sfq_prot; ++ /* no vlan */ ++ cpu_ptr->txd_info3.IPOFST = 14 + (sfq_parse_result.vlan1_gap); ++ } ++ cpu_ptr->txd_info4.FPORT = gmac_no; ++ ++ if (ei_local->features & FE_CSUM_OFFLOAD) { ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ cpu_ptr->txd_info4.TUI_CO = 7; ++ else ++ cpu_ptr->txd_info4.TUI_CO = 0; ++ } ++ ++ if (ei_local->features & FE_HW_VLAN_TX) { ++ if (skb_vlan_tag_present(skb)) { ++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | skb_vlan_tag_get(skb); ++ } else { ++ cpu_ptr->txd_info4.VLAN_TAG = 0; ++ } ++ } ++ cpu_ptr->txd_info4.QID = 0; ++ cpu_ptr->txd_info3.QID = ring_no; ++ ++ if ((ei_local->features & QDMA_QOS_MARK) && (skb->mark != 0)) { ++ if (skb->mark < 64) { ++ qidx = M2Q_table[skb->mark]; ++ cpu_ptr->txd_info4.QID = ((qidx & 0x30) >> 4); ++ cpu_ptr->txd_info3.QID = (qidx & 0x0f); ++ } else { ++ NOE_MSG_ERR("skb->mark out of range\n"); ++ cpu_ptr->txd_info3.QID = 0; ++ cpu_ptr->txd_info4.QID = 0; ++ } ++ } ++ /* QoS Web UI used */ ++ ++ if ((ei_local->features & QDMA_QOS_WEB) && (lan_wan_separate == 1)) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) { ++ if (gmac_no == 1) ++ cpu_ptr->txd_info3.QID = HW_SFQ_DL; ++ else ++ cpu_ptr->txd_info3.QID = HW_SFQ_UP; ++ } else if (gmac_no == 2) { ++ cpu_ptr->txd_info3.QID += 8; ++ } ++ } ++ ++#ifdef CONFIG_NOE_NAT_HW ++ if (FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if (IS_VALID_NOE_HWNAT_HOOK_RX) { ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++ /* dma_sync_single_for_device(NULL, virt_to_phys(skb->data), */ ++ /* skb->len, DMA_TO_DEVICE); */ ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ ++ /* 5. move CPU_PTR to new TXD */ ++ cpu_ptr->txd_info4.TSO = 0; ++ cpu_ptr->txd_info3.LS_bit = 1; ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ next_txd_idx = _MDrv_NOE_QDMA_Get_Free_Txd(ei_local, ring_no); ++ cpu_ptr->txd_info2.NDP = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, next_txd_idx); ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++ prev_cpu_ptr = ei_local->txd_pool + ei_local->tx_cpu_idx; ++ /* update skb_free */ ++ ei_local->skb_free[ei_local->tx_cpu_idx] = skb; ++ /* update tx cpu idx */ ++ ei_local->tx_cpu_idx = next_txd_idx; ++ /* update txd info */ ++ prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1; ++ prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2; ++ prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4; ++ prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3; ++ Chip_Flush_MIU_Pipe(); //L3 ++ /* NOTE: add memory barrier to avoid ++ * DMA access memory earlier than memory written ++ */ ++ wmb(); ++ /* update CPU pointer */ ++ MHal_NOE_QDMA_Update_Tx(E_NOE_QDMA_TX_FORWARD, _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, ei_local->tx_cpu_idx)); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ if (gmac_no == 2) { ++ if (ei_local->pseudo_dev) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_packets++; ++ ++ p_ad->stat.tx_bytes += length; ++ } ++ } else { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += skb->len; ++ } ++ } else { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += skb->len; ++ } ++ if (ei_local->features & FE_INT_NAPI) { ++ if (ei_local->tx_full == 1) { ++ ei_local->tx_full = 0; ++ netif_wake_queue(dev); ++ } ++ } ++ ++ return length; ++} ++ ++static int MDrv_NOE_QDMA_Eth_Tso_Send(struct END_DEVICE *ei_local, struct net_device *dev, struct sk_buff *skb, int gmac_no, int ring_no) ++{ ++ unsigned int length = skb->len; ++ struct QDMA_txdesc *cpu_ptr, *prev_cpu_ptr; ++ struct QDMA_txdesc dummy_desc; ++ struct QDMA_txdesc init_dummy_desc; ++ int ctx_idx; ++ struct iphdr *iph = NULL; ++ struct QDMA_txdesc *init_cpu_ptr; ++ struct tcphdr *th = NULL; ++ struct skb_frag_struct *frag; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags; ++ unsigned int len, size, offset, frag_txd_num, qidx; ++ unsigned long flags; ++ int i; ++ int init_qid, init_qid1; ++ struct ipv6hdr *ip6h = NULL; ++ struct PSEUDO_ADAPTER *p_ad; ++ ++ init_cpu_ptr = &init_dummy_desc; ++ cpu_ptr = &init_dummy_desc; ++ ++ len = length - skb->data_len; ++ dma_sync_single_for_device(&ei_local->qdma_pdev->dev, virt_to_phys(skb->data), len, DMA_TO_DEVICE); ++ offset = virt_to_phys(skb->data); ++ cpu_ptr->txd_info1.SDP = offset; ++ if (len > MAX_QTXD_LEN) { ++ cpu_ptr->txd_info3.SDL = 0x3FFF; ++ cpu_ptr->txd_info4.SDL = 0x3; ++ cpu_ptr->txd_info3.LS_bit = 0; ++ len -= MAX_QTXD_LEN; ++ offset += MAX_QTXD_LEN; ++ } else { ++ cpu_ptr->txd_info3.SDL = (len & 0x3FFF); ++ cpu_ptr->txd_info4.SDL = len >> 14; ++ cpu_ptr->txd_info3.LS_bit = nr_frags ? 0 : 1; ++ len = 0; ++ } ++ if (ei_local->features & FE_HW_SFQ) { ++ _MDrv_NOE_QDMA_SFQ_Parse_Net_Layer(skb); ++ ++ cpu_ptr->txd_info4.VQID0 = 1; ++ cpu_ptr->txd_info3.PROT = sfq_prot; ++ /* no vlan */ ++ cpu_ptr->txd_info3.IPOFST = 14 + (sfq_parse_result.vlan1_gap); ++ } ++ if (gmac_no == 1) ++ cpu_ptr->txd_info4.FPORT = 1; ++ else ++ cpu_ptr->txd_info4.FPORT = 2; ++ ++ cpu_ptr->txd_info4.TSO = 0; ++ cpu_ptr->txd_info4.QID = 0; ++ cpu_ptr->txd_info3.QID = ring_no; ++ if ((ei_local->features & QDMA_QOS_MARK) && (skb->mark != 0)) { ++ if (skb->mark < 64) { ++ qidx = M2Q_table[skb->mark]; ++ cpu_ptr->txd_info4.QID = ((qidx & 0x30) >> 4); ++ cpu_ptr->txd_info3.QID = (qidx & 0x0f); ++ } else { ++ NOE_MSG_DUMP("skb->mark out of range\n"); ++ cpu_ptr->txd_info3.QID = 0; ++ cpu_ptr->txd_info4.QID = 0; ++ } ++ } ++ ++ if (ei_local->features & FE_CSUM_OFFLOAD) { ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ cpu_ptr->txd_info4.TUI_CO = 7; ++ else ++ cpu_ptr->txd_info4.TUI_CO = 0; ++ } ++ ++ if (ei_local->features & FE_HW_VLAN_TX) { ++ if (skb_vlan_tag_present(skb)) { ++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | skb_vlan_tag_get(skb); ++ } else { ++ cpu_ptr->txd_info4.VLAN_TAG = 0; ++ } ++ } ++ if ((ei_local->features & FE_GE2_SUPPORT) && (lan_wan_separate == 1)) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) { ++ if (gmac_no == 1) ++ cpu_ptr->txd_info3.QID = HW_SFQ_DL; ++ else ++ cpu_ptr->txd_info3.QID = HW_SFQ_UP; ++ } else if (gmac_no == 2) { ++ cpu_ptr->txd_info3.QID += 8; ++ } ++ } ++ ++ /*debug multi tx queue */ ++ init_qid = cpu_ptr->txd_info3.QID; ++ init_qid1 = cpu_ptr->txd_info4.QID; ++ ++#ifdef CONFIG_NOE_NAT_HW ++ if (FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if (IS_VALID_NOE_HWNAT_HOOK_RX) { ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ ++ ctx_idx = _MDrv_NOE_QDMA_Get_Free_Txd(ei_local, ring_no); ++ cpu_ptr->txd_info2.NDP = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, ctx_idx); ++ /*prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1; ++ *prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2; ++ *prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3; ++ *prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4; ++ */ ++ if (len > 0) { ++ frag_txd_num = _MDrv_NOE_QDMA_Calc_Frag_Txd_Num(len); ++ for (frag_txd_num = frag_txd_num; frag_txd_num > 0; ++ frag_txd_num--) { ++ if (len < MAX_QTXD_LEN) ++ size = len; ++ else ++ size = MAX_QTXD_LEN; ++ ++ cpu_ptr = (ei_local->txd_pool + (ctx_idx)); ++ dummy_desc.txd_info1 = cpu_ptr->txd_info1; ++ dummy_desc.txd_info2 = cpu_ptr->txd_info2; ++ dummy_desc.txd_info3 = cpu_ptr->txd_info3; ++ dummy_desc.txd_info4 = cpu_ptr->txd_info4; ++ prev_cpu_ptr = cpu_ptr; ++ cpu_ptr = &dummy_desc; ++ cpu_ptr->txd_info3.QID = init_qid; ++ cpu_ptr->txd_info4.QID = init_qid1; ++ cpu_ptr->txd_info1.SDP = offset; ++ cpu_ptr->txd_info3.SDL = (size & 0x3FFF); ++ cpu_ptr->txd_info4.SDL = size >> 14; ++ if ((nr_frags == 0) && (frag_txd_num == 1)) ++ cpu_ptr->txd_info3.LS_bit = 1; ++ else ++ cpu_ptr->txd_info3.LS_bit = 0; ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ if (cpu_ptr->txd_info3.LS_bit == 1) ++ ei_local->skb_free[ctx_idx] = skb; ++ else ++ ei_local->skb_free[ctx_idx] = magic_id; ++ ctx_idx = _MDrv_NOE_QDMA_Get_Free_Txd(ei_local, ring_no); ++ cpu_ptr->txd_info2.NDP = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, ctx_idx); ++ prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1; ++ prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2; ++ prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3; ++ prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4; ++ offset += size; ++ len -= size; ++ } ++ } ++ ++ for (i = 0; i < nr_frags; i++) { ++ /* 1. set or get init value for current fragment */ ++ offset = 0; ++ frag = &skb_shinfo(skb)->frags[i]; ++ len = frag->size; ++ frag_txd_num = _MDrv_NOE_QDMA_Calc_Frag_Txd_Num(len); ++ for (frag_txd_num = frag_txd_num; ++ frag_txd_num > 0; frag_txd_num--) { ++ /* 2. size will be assigned to SDL ++ * and can't be larger than MAX_TXD_LEN ++ */ ++ if (len < MAX_QTXD_LEN) ++ size = len; ++ else ++ size = MAX_QTXD_LEN; ++ ++ /* 3. Update TXD info */ ++ cpu_ptr = (ei_local->txd_pool + (ctx_idx)); ++ dummy_desc.txd_info1 = cpu_ptr->txd_info1; ++ dummy_desc.txd_info2 = cpu_ptr->txd_info2; ++ dummy_desc.txd_info3 = cpu_ptr->txd_info3; ++ dummy_desc.txd_info4 = cpu_ptr->txd_info4; ++ prev_cpu_ptr = cpu_ptr; ++ cpu_ptr = &dummy_desc; ++ cpu_ptr->txd_info3.QID = init_qid; ++ cpu_ptr->txd_info4.QID = init_qid1; ++ cpu_ptr->txd_info1.SDP = dma_map_page(&ei_local->qdma_pdev->dev, frag->page.p, frag->page_offset + offset, size, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error (&ei_local->qdma_pdev->dev, cpu_ptr->txd_info1.SDP))) { ++ NOE_MSG_ERR("[%s] dma_map_page() failed...\n", __func__); ++ } ++ ++ cpu_ptr->txd_info3.SDL = (size & 0x3FFF); ++ cpu_ptr->txd_info4.SDL = size >> 14; ++ cpu_ptr->txd_info4.SDL = (size >> 14); ++ if ((i == (nr_frags - 1)) && (frag_txd_num == 1)) ++ cpu_ptr->txd_info3.LS_bit = 1; ++ else ++ cpu_ptr->txd_info3.LS_bit = 0; ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ /* 4. Update skb_free for housekeeping */ ++ if (cpu_ptr->txd_info3.LS_bit == 1) ++ ei_local->skb_free[ctx_idx] = skb; ++ else ++ ei_local->skb_free[ctx_idx] = magic_id; ++ ++ /* 5. Get next TXD */ ++ ctx_idx = _MDrv_NOE_QDMA_Get_Free_Txd(ei_local, ring_no); ++ cpu_ptr->txd_info2.NDP = _MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, ctx_idx); ++ prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1; ++ prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2; ++ prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3; ++ prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4; ++ Chip_Flush_MIU_Pipe(); //L3 ++ /* 6. Update offset and len. */ ++ offset += size; ++ len -= size; ++ } ++ } ++ ++ if (skb_shinfo(skb)->gso_segs > 1) { ++ MDrv_NOE_Update_Tso_Len(skb->len); ++ /* TCP over IPv4 */ ++ iph = (struct iphdr *)skb_network_header(skb); ++ if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++ init_cpu_ptr->txd_info4.TSO = 1; ++ th->check = htons(skb_shinfo(skb)->gso_size); ++ dma_sync_single_for_device(&ei_local->qdma_pdev->dev, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++ } ++ ++ if (ei_local->features & FE_TSO_V6) { ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++ if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++ init_cpu_ptr->txd_info4.TSO = 1; ++ th->check = htons(skb_shinfo(skb)->gso_size); ++ ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++ } ++ } ++ if (ei_local->features & FE_HW_SFQ) { ++ init_cpu_ptr->txd_info4.VQID0 = 1; ++ init_cpu_ptr->txd_info3.PROT = sfq_prot; ++ /* no vlan */ ++ init_cpu_ptr->txd_info3.IPOFST = 14 + (sfq_parse_result.vlan1_gap); ++ } ++ } ++ /* dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); */ ++ ++ init_cpu_ptr->txd_info3.OWN_bit = 0; ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++ prev_cpu_ptr = ei_local->txd_pool + ei_local->tx_cpu_idx; ++ ei_local->skb_free[ei_local->tx_cpu_idx] = magic_id; ++ ei_local->tx_cpu_idx = ctx_idx; ++ prev_cpu_ptr->txd_info1 = init_dummy_desc.txd_info1; ++ prev_cpu_ptr->txd_info2 = init_dummy_desc.txd_info2; ++ prev_cpu_ptr->txd_info4 = init_dummy_desc.txd_info4; ++ prev_cpu_ptr->txd_info3 = init_dummy_desc.txd_info3; ++ Chip_Flush_MIU_Pipe(); //L3 ++ ++ /* NOTE: add memory barrier to avoid ++ * DMA access memory earlier than memory written ++ */ ++ wmb(); ++ MHal_NOE_QDMA_Update_Tx(E_NOE_QDMA_TX_FORWARD,_MDrv_NOE_QDMA_Get_Txd_Phy_Adr(ei_local, ei_local->tx_cpu_idx)); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ if (gmac_no == 2) { ++ if (ei_local->pseudo_dev) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_packets++; ++ p_ad->stat.tx_bytes += length; ++ } ++ } else { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += skb->len; ++ } ++ } else { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += skb->len; ++ } ++ if (ei_local->features & FE_INT_NAPI) { ++ if (ei_local->tx_full == 1) { ++ ei_local->tx_full = 0; ++ netif_wake_queue(dev); ++ } ++ } ++ ++ return length; ++} ++ ++/* QDMA functions */ ++ ++ ++int MDrv_NOE_QDMA_Init_Rx(struct net_device *dev) ++{ ++ int i; ++ struct noe_dma_info dma_info; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ /* Initial QDMA RX Ring */ ++#if 0 ++ ei_local->qrx_ring = dma_alloc_coherent(&ei_local->qdma_pdev->dev, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_qrx_ring, GFP_ATOMIC | __GFP_ZERO); ++#else ++{ ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++ mem_info.length = NUM_QRX_DESC * sizeof(struct PDMA_rxdesc); ++ strcpy(mem_info.name, "qrx_ring"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ NOE_MSG_ERR("unable to allocate DMEM for %s!! error=%d\n", mem_info.name ,ret); ++ } ++ ei_local->phy_qrx_ring = (dma_addr_t)((size_t)mem_info.phys); ++ ei_local->qrx_ring = (void *)((size_t)mem_info.kvirt); ++} ++#endif ++ ++ ++ if(ei_local->qrx_ring == NULL) ++ { ++ NOE_MSG_ERR("[%s][%d]dma alloc FAIL!! %u\n",__FUNCTION__,__LINE__, NUM_QRX_DESC*sizeof(struct PDMA_rxdesc)); ++ goto no_rx_mem; ++ } ++ ++ for (i = 0; i < NUM_QRX_DESC; i++) { ++ ei_local->netrx0_skbuf[i] = netdev_alloc_skb(dev, MAX_RX_LENGTH + NET_IP_ALIGN); ++ if (!ei_local->netrx0_skbuf[i]) { ++ NOE_MSG_ERR("rx skbuff buffer allocation failed!"); ++ goto no_rx_mem; ++ } ++ ++ memset(&ei_local->qrx_ring[i], 0, sizeof(struct PDMA_rxdesc)); ++ ei_local->qrx_ring[i].rxd_info2.DDONE_bit = 0; ++ ei_local->qrx_ring[i].rxd_info2.LS0 = 0; ++ ei_local->qrx_ring[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++ ei_local->qrx_ring[i].rxd_info1.PDP0 = dma_map_single(&ei_local->qdma_pdev->dev, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH + NET_IP_ALIGN, PCI_DMA_FROMDEVICE); ++ NOE_MSG_DUMP("%p ,PDP0 = 0x%X \n", ei_local->netrx0_skbuf[i]->data, ei_local->qrx_ring[i].rxd_info1.PDP0); ++ if (unlikely(dma_mapping_error(ei_local->dev, ei_local->qrx_ring[i].rxd_info1.PDP0))) { ++ NOE_MSG_ERR("[%s]dma_map_single() failed...\n", __func__); ++ goto no_rx_mem; ++ } ++ } ++ Chip_Flush_MIU_Pipe(); //L3 ++ ++ NOE_MSG_DBG("\n[QUE_RX] phy = 0x%p, vir = 0x%p\n", (void *)ei_local->phy_qrx_ring, ei_local->qrx_ring); ++ ++ /* Tell the adapter where the RX rings are located. */ ++ dma_info.ring_st.base_adr = ((MS_U32)ei_local->phy_qrx_ring); ++ dma_info.ring_st.max_cnt = cpu_to_le32((MS_U32)NUM_QRX_DESC); ++ dma_info.ring_st.cpu_idx = cpu_to_le32((MS_U32)(NUM_QRX_DESC - 1)); ++ ++ MHal_NOE_DMA_Init(E_NOE_DMA_QUEUE, E_NOE_DIR_RX, E_NOE_RING_NO0, &dma_info); ++ ei_local->rx_ring[0] = ei_local->qrx_ring; ++ ++ return 0; ++ ++no_rx_mem: ++ return -ENOMEM; ++} ++ ++int MDrv_NOE_QDMA_Init_Tx(struct net_device *dev) ++{ ++ bool pass; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ if (ei_local->features & FE_HW_SFQ) ++ _MDrv_NOE_QDMA_SFQ_Init(dev); ++ ++ /*tx desc alloc, add a NULL TXD to HW */ ++ pass = _MDrv_NOE_QDMA_Alloc_Txd(dev); ++ if (!pass) { ++ NOE_MSG_ERR("fail to allocate qdma txd!\n"); ++ return -1; ++ } ++ ++ pass = _MDrv_NOE_QDMA_Init_Fq(dev); ++ if (!pass) { ++ NOE_MSG_ERR("fail to allocate qdma free desc!\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++void MDrv_NOE_QDMA_Deinit_Rx(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int i; ++ ++ /* free RX Ring */ ++#if 0 ++ if (ei_local->qrx_ring) ++ dma_free_coherent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), ei_local->qrx_ring, ei_local->phy_qrx_ring); ++#endif ++ /* free RX data */ ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ if (ei_local->netrx0_skbuf[i]) { ++ dev_kfree_skb_any(ei_local->netrx0_skbuf[i]); ++ ei_local->netrx0_skbuf[i] = NULL; ++ } ++ } ++} ++ ++void MDrv_NOE_QDMA_Deinit_Tx(struct net_device *dev) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ int i; ++ ++ /* free TX Ring */ ++#if 0 ++ if (ei_local->txd_pool) ++ dma_free_coherent(&ei_local->qdma_pdev->dev, NUM_TX_DESC * QTXD_LEN, ei_local->txd_pool, ei_local->phy_txd_pool); ++ if (ei_local->free_head) ++ dma_free_coherent(&ei_local->qdma_pdev->dev, NUM_QDMA_PAGE * QTXD_LEN, ei_local->free_head, ei_local->phy_free_head); ++ if (ei_local->free_page_head) ++ dma_free_coherent(&ei_local->qdma_pdev->dev, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, ei_local->free_page_head, ei_local->phy_free_page_head); ++#endif ++ ++ /* free TX data */ ++ for (i = 0; i < NUM_TX_DESC; i++) { ++ if ((ei_local->skb_free[i] != (struct sk_buff *)0xFFFFFFFF) && (ei_local->skb_free[i] != 0)) ++ dev_kfree_skb_any(ei_local->skb_free[i]); ++ } ++} ++ ++ ++ ++int MDrv_NOE_QDMA_Start_Xmit(struct sk_buff *skb, struct net_device *dev, int gmac_no) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned int num_of_txd = 0; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i; ++ struct skb_frag_struct *frag; ++ struct PSEUDO_ADAPTER *p_ad; ++ int ring_no; ++ ++ ring_no = skb->queue_mapping + (gmac_no - 1) * GMAC1_TXQ_NUM; ++#ifdef CONFIG_NOE_NAT_HW ++ if (IS_VALID_NOE_HWNAT_HOOK_TX) { ++ if (NOE_HWNAT_HOOK_TX(skb, gmac_no) != 1) { ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ } ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) ++ dev->trans_start = jiffies; /* save the timestamp */ ++#else ++ { ++ struct netdev_queue *txq = netdev_get_tx_queue(dev, 0); ++ ++ if (txq->trans_start != jiffies) ++ txq->trans_start = jiffies; ++ } ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) */ ++ ++ /*spin_lock_irqsave(&ei_local->page_lock, flags); */ ++ ++ /* check free_txd_num before calling rt288_eth_send() */ ++ ++ if (ei_local->features & FE_TSO) { ++ num_of_txd += _MDrv_NOE_QDMA_Calc_Frag_Txd_Num(skb->len - skb->data_len); ++ if (nr_frags != 0) { ++ for (i = 0; i < nr_frags; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ num_of_txd += _MDrv_NOE_QDMA_Calc_Frag_Txd_Num(frag->size); ++ } ++ } ++ } else { ++ num_of_txd = 1; ++ } ++ ++ if (likely(atomic_read(&ei_local->free_txd_num[ring_no]) > (num_of_txd + 1))) { ++ if (num_of_txd == 1) ++ MDrv_NOE_QDMA_Eth_Send(ei_local, dev, skb, gmac_no, ring_no); ++ else ++ MDrv_NOE_QDMA_Eth_Tso_Send(ei_local, dev, skb, gmac_no, ring_no); ++ } else { ++ if (ei_local->features & FE_GE2_SUPPORT) { ++ if (gmac_no == 2) { ++ if (ei_local->pseudo_dev) { ++ p_ad = netdev_priv(ei_local->pseudo_dev); ++ p_ad->stat.tx_dropped++; ++ } ++ } else { ++ ei_local->stat.tx_dropped++; ++ } ++ } else { ++ ei_local->stat.tx_dropped++; ++ } ++ /* kfree_skb(skb); */ ++ dev_kfree_skb_any(skb); ++ /* spin_unlock_irqrestore(&ei_local->page_lock, flags); */ ++ return 0; ++ } ++ /* spin_unlock_irqrestore(&ei_local->page_lock, flags); */ ++ return 0; ++} ++ ++int MDrv_NOE_QDMA_Xmit_Housekeeping(struct net_device *netdev, int budget) ++{ ++ struct END_DEVICE *ei_local = netdev_priv(netdev); ++ ++ dma_addr_t dma_ptr; ++ struct QDMA_txdesc *cpu_ptr = NULL; ++ unsigned int tmp_offset = 0; ++ unsigned int ctx_offset = 0; ++ unsigned int dtx_offset = 0; ++ unsigned int rls_cnt[TOTAL_TXQ_NUM] = { 0 }; ++ int ring_no; ++ int i; ++ dma_addr_t tmp_ptr; ++ //unsigned long u32VAddr = (unsigned long)ei_local->txd_pool; ++ //unsigned long u32Size = NUM_TX_DESC * QTXD_LEN; ++ ++ dma_ptr = (dma_addr_t)MHal_NOE_QDMA_Get_Tx(); ++ ctx_offset = ei_local->rls_cpu_idx; ++ dtx_offset = (dma_ptr - ei_local->phy_txd_pool) / QTXD_LEN; ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ ++ //Chip_Inv_Cache_Range(u32VAddr, u32Size); ++#ifdef CONFIG_NOE_FLUSH_MEM ++ Chip_Flush_Cache_Range(u32VAddr, u32Size); ++#endif ++ ++ while (ctx_offset != dtx_offset) { ++ /* 1. keep cpu next TXD */ ++ if (MHAL_NOE_IS_TXD_NOT_AVAILABLE(cpu_ptr)) { ++ break; ++ } ++ tmp_ptr = (dma_addr_t)cpu_ptr->txd_info2.NDP; ++ if (tmp_ptr == 0) ++ break; ++ /* atomic_add(1, &ei_local->free_txd_num[ring_no]); */ ++ /* 3. update ctx_offset and free skb memory */ ++ tmp_offset = ctx_offset; ++ ctx_offset = (tmp_ptr - ei_local->phy_txd_pool) / QTXD_LEN; ++ ++ if (ei_local->features & FE_TSO) { ++ if (ei_local->skb_free[ctx_offset] != magic_id) { ++ if (ei_local->skb_free[ctx_offset] != NULL) { ++ dev_kfree_skb_any(ei_local->skb_free[ctx_offset]); ++ } ++ else { ++ ctx_offset = tmp_offset; ++ break; ++ } ++ } ++ } ++ else { ++ if (ei_local->skb_free[ctx_offset] != NULL) { ++ dev_kfree_skb_any(ei_local->skb_free[ctx_offset]); ++ } ++ else { ++ ctx_offset = tmp_offset; ++ break; ++ } ++ } ++ /* 3. release TXD */ ++ ring_no = _MDrv_NOE_QDMA_Map_Ring_No(tmp_offset); ++ rls_cnt[ring_no]++; ++ _MDrv_NOE_QDMA_Put_Back_Free_Txd(ei_local, ring_no, tmp_offset); ++ ei_local->skb_free[ctx_offset] = 0; ++ cpu_ptr->txd_info1.SDP = 0; ++ /* 4. update cpu_ptr */ ++ cpu_ptr = (ei_local->txd_pool + ctx_offset); ++ Chip_Flush_MIU_Pipe(); //L3 ++ } ++ ++ for (i = 0; i < TOTAL_TXQ_NUM; i++) { ++ if (rls_cnt[i] > 0) ++ atomic_add(rls_cnt[i], &ei_local->free_txd_num[i]); ++ if (atomic_read(&ei_local->free_txd_num[i]) < ei_local->stats.min_free_txd[i]) ++ ei_local->stats.min_free_txd[i] = atomic_read(&ei_local->free_txd_num[i]); ++ } ++ ei_local->rls_cpu_idx = ctx_offset; ++ netif_wake_queue(netdev); ++ if (ei_local->features & FE_GE2_SUPPORT) ++ netif_wake_queue(ei_local->pseudo_dev); ++ ei_local->tx_ring_full = 0; ++ MHal_NOE_QDMA_Update_Tx(E_NOE_QMDA_TX_RELEASE, (ei_local->phy_txd_pool + (ctx_offset * QTXD_LEN))); ++ ++ return 0; ++} ++ ++int MDrv_NOE_QDMA_Ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct noe_reg reg; ++#ifdef NOE_IOCTL_VERSION_4 ++ unsigned int page = 0, pq_no; ++#endif ++ int ret = 0; ++ struct END_DEVICE *ei_local = netdev_priv(dev); ++ ++ spin_lock_irq(&ei_local->page_lock); ++ ++ switch (cmd) { ++ case NOE_QDMA_REG_READ: ++ ret = copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (ret) { ++ ret = -EFAULT; ++ break; ++ } ++ if (reg.off > REG_HQOS_MAX) { ++ ret = -EINVAL; ++ break; ++ } ++#ifdef NOE_IOCTL_VERSION_4 ++ /* q16~q31: 0x100 <= reg.off < 0x200 ++ * q32~q47: 0x200 <= reg.off < 0x300 ++ * q48~q63: 0x300 <= reg.off < 0x400 ++ */ ++ if (reg.off >= 0x100 && reg.off < 0x200) { ++ page = 1; ++ reg.off = reg.off - 0x100; ++ pq_no = 16 + reg.off / 16; ++ } else if (reg.off >= 0x200 && reg.off < 0x300) { ++ page = 2; ++ reg.off = reg.off - 0x200; ++ pq_no = 32 + reg.off / 16; ++ } else if (reg.off >= 0x300 && reg.off < 0x400) { ++ page = 3; ++ reg.off = reg.off - 0x300; ++ pq_no = 48 + reg.off / 16; ++ } else { ++ page = 0; ++ pq_no = reg.off / 16; ++ } ++ ++ NOE_MSG_DUMP("page=%d, reg.off =%x\n", page, reg.off); ++ reg.val = MHal_NOE_DMA_Get_Queue_Cfg(pq_no); ++#else ++ reg.val = MHal_NOE_DMA_Get_Queue_Cfg(reg.off); ++ NOE_MSG_DUMP("[%s][%d]read reg off:%x val:%x\n",__FUNCTION__,__LINE__, reg.off, reg.val); ++#endif ++ ret = copy_to_user(ifr->ifr_data, ®, sizeof(reg)); ++ if (ret) ++ ret = -EFAULT; ++ break; ++ case NOE_QDMA_REG_WRITE: ++ ret = copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (ret) { ++ ret = -EFAULT; ++ break; ++ } ++ if (reg.off > REG_HQOS_MAX) { ++ ret = -EINVAL; ++ break; ++ } ++#ifdef NOE_IOCTL_VERSION_4 ++ /* q16~q31: 0x100 <= reg.off < 0x200 ++ * q32~q47: 0x200 <= reg.off < 0x300 ++ * q48~q63: 0x300 <= reg.off < 0x400 ++ */ ++ if (reg.off >= 0x100 && reg.off < 0x200) { ++ page = 1; ++ reg.off = reg.off - 0x100; ++ pq_no = 16 + reg.off / 16; ++ } else if (reg.off >= 0x200 && reg.off < 0x300) { ++ page = 2; ++ reg.off = reg.off - 0x200; ++ pq_no = 32 + reg.off / 16; ++ } else if (reg.off >= 0x300 && reg.off < 0x400) { ++ page = 3; ++ reg.off = reg.off - 0x300; ++ pq_no = 48 + reg.off / 16; ++ } else { ++ page = 0; ++ pq_no = reg.off / 16; ++ } ++ NOE_MSG_DUMP("reg.val =%x\n", reg.val); ++ MHal_NOE_DMA_Set_Queue_Cfg(pq_no, reg.val); ++ /* NOE_MSG_DUMP("write reg off:%x val:%x\n", reg.off, reg.val); */ ++#else ++ NOE_MSG_DUMP("[%s][%d]reg.off,val =0x%x,0x%x\n",__FUNCTION__,__LINE__,reg.off, reg.val); ++ MHal_NOE_DMA_Set_Queue_Cfg(reg.off, reg.val); ++ NOE_MSG_DUMP("[%s][%d]write reg off:%x val:%x\n",__FUNCTION__,__LINE__, reg.off, reg.val); ++#endif ++ break; ++ case NOE_QDMA_QUEUE_MAPPING: ++ ret = copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (ret) { ++ ret = -EFAULT; ++ break; ++ } ++ if ((reg.off & 0x100) == 0x100) { ++ lan_wan_separate = 1; ++ reg.off &= 0xff; ++ } else { ++ lan_wan_separate = 0; ++ } ++ M2Q_table[reg.off] = reg.val; ++ break; ++ case NOE_QDMA_SFQ_WEB_ENABLE: ++ if (ei_local->features & FE_HW_SFQ) { ++ ret = copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (ret) { ++ ret = -EFAULT; ++ break; ++ } ++ if ((reg.val) == 0x1) ++ web_sfq_enable = 1; ++ else ++ web_sfq_enable = 0; ++ } else { ++ ret = -EINVAL; ++ } ++ break; ++ default: ++ ret = 1; ++ break; ++ } ++ ++ spin_unlock_irq(&ei_local->page_lock); ++ return ret; ++} +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_utils.c b/drivers/sstar/noe/drv/eth/mdrv_noe_utils.c +new file mode 100755 +index 000000000000..c4d15eb9380b +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_utils.c +@@ -0,0 +1,80 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV NOE UTILS .c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mdrv_noe.h" ++ ++ ++ ++static int _MDrv_NOE_UTIL_Getnext(const char *src, int separator, char *dest) ++{ ++ char *c; ++ int len; ++ ++ if (!src || !dest) ++ return -1; ++ ++ c = strchr(src, separator); ++ if (!c) { ++ strcpy(dest, src); ++ return -1; ++ } ++ len = c - src; ++ strncpy(dest, src, len); ++ dest[len] = '\0'; ++ return len + 1; ++} ++ ++int MDrv_NOE_UTIL_Str_To_Ip(unsigned int *ip, const char *str) ++{ ++ int len; ++ const char *ptr = str; ++ char buf[128]; ++ unsigned char c[4]; ++ int i; ++ int ret; ++ ++ for (i = 0; i < 3; ++i) { ++ len = _MDrv_NOE_UTIL_Getnext(ptr, '.', buf); ++ if (len == -1) ++ return 1; /* parse error */ ++ ++ ret = kstrtoul(buf, 10, (unsigned long *)&c[i]); ++ if (ret) ++ return ret; ++ ++ ptr += len; ++ } ++ ret = kstrtoul(ptr, 0, (unsigned long *)&c[3]); ++ if (ret) ++ return ret; ++ ++ *ip = (c[0] << 24) + (c[1] << 16) + (c[2] << 8) + c[3]; ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/noe/drv/eth/mdrv_noe_utils.h b/drivers/sstar/noe/drv/eth/mdrv_noe_utils.h +new file mode 100755 +index 000000000000..ebe3d049cdf2 +--- /dev/null ++++ b/drivers/sstar/noe/drv/eth/mdrv_noe_utils.h +@@ -0,0 +1,33 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_UTILS.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++#ifndef _MDRV_NOE_UTILITY_H_ ++#define _MDRV_NOE_UTILITY_H_ ++ ++int MDrv_NOE_UTIL_Str_To_Ip(unsigned int *ip, const char *str); ++ ++#endif /* _MDRV_NOE_UTILITY_H_ */ +diff --git a/drivers/sstar/noe/drv/nat/hook/Makefile b/drivers/sstar/noe/drv/nat/hook/Makefile +new file mode 100755 +index 000000000000..a17ad2faac6a +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hook/Makefile +@@ -0,0 +1,3 @@ ++obj-y += foe_hook.o ++foe_hook-objs := mdrv_hook.o ++EXTRA_CFLAGS += -Idrivers/mstar/noe/drv/nat/hw_nat +diff --git a/drivers/sstar/noe/drv/nat/hook/mdrv_hook.c b/drivers/sstar/noe/drv/nat/hook/mdrv_hook.c +new file mode 100755 +index 000000000000..ef249a73db2e +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hook/mdrv_hook.c +@@ -0,0 +1,146 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file hook.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_hwnat.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Variable ++//-------------------------------------------------------------------------------------------------- ++ ++ ++struct net_device *dst_port[MAX_IF_NUM]; ++EXPORT_SYMBOL(dst_port); ++ ++struct foe_entry *ppe_virt_foe_base_tmp; ++EXPORT_SYMBOL(ppe_virt_foe_base_tmp); ++ ++int (*noe_nat_hook_rx)(struct sk_buff *skb) = NULL; ++EXPORT_SYMBOL(noe_nat_hook_rx); ++ ++int (*noe_nat_hook_tx)(struct sk_buff *skb, int gmac_no) = NULL; ++EXPORT_SYMBOL(noe_nat_hook_tx); ++ ++void (*ppe_dev_register_hook)(struct net_device *dev); ++EXPORT_SYMBOL(ppe_dev_register_hook); ++ ++void (*ppe_dev_unregister_hook)(struct net_device *dev); ++EXPORT_SYMBOL(ppe_dev_unregister_hook); ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Function ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++void MDrv_NOE_NAT_Set_Magic_Tag_Zero(struct sk_buff *skb) ++{ ++ if ((FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PCI) || ++ (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_WLAN) || ++ (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_GE)) { ++ if (IS_SPACE_AVAILABLE_HEAD(skb)) ++ FOE_MAGIC_TAG_HEAD(skb) = 0; ++ } ++ if ((FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PCI) || ++ (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_WLAN) || ++ (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_GE)) { ++ if (IS_SPACE_AVAILABLE_TAIL(skb)) ++ FOE_MAGIC_TAG_TAIL(skb) = 0; ++ } ++} ++ ++void MDrv_NOE_NAT_Check_Magic_Tag(struct sk_buff *skb) ++{ ++ if (IS_SPACE_AVAILABLE_HEAD(skb)) { ++ FOE_MAGIC_TAG_HEAD(skb) = 0; ++ FOE_AI_HEAD(skb) = UN_HIT; ++ } ++ if (IS_SPACE_AVAILABLE_TAIL(skb)) { ++ FOE_MAGIC_TAG_TAIL(skb) = 0; ++ FOE_AI_TAIL(skb) = UN_HIT; ++ } ++} ++ ++void MDrv_NOE_NAT_Set_Headroom_Zero(struct sk_buff *skb) ++{ ++ if (skb->cloned != 1) { ++ if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb) || ++ (FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE)) { ++ if (IS_SPACE_AVAILABLE_HEAD(skb)) ++ memset(FOE_INFO_START_ADDR_HEAD(skb), 0, FOE_INFO_LEN); ++ } ++ } ++} ++ ++void MDrv_NOE_NAT_Set_Tailroom_Zero(struct sk_buff *skb) ++{ ++ if (skb->cloned != 1) { ++ if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb) || ++ (FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE)) { ++ if (IS_SPACE_AVAILABLE_TAIL(skb)) ++ memset(FOE_INFO_START_ADDR_TAIL(skb), 0, FOE_INFO_LEN); ++ } ++ } ++} ++ ++void MDrv_NOE_NAT_Copy_Headroom(u8 *data, struct sk_buff *skb) ++{ ++ memcpy(data, skb->head, FOE_INFO_LEN); ++} ++ ++void MDrv_NOE_NAT_Copy_Tailroom(u8 *data, int size, struct sk_buff *skb) ++{ ++ memcpy((data + size - FOE_INFO_LEN), (skb_end_pointer(skb) - FOE_INFO_LEN), FOE_INFO_LEN); ++} ++ ++void MDrv_NOE_NAT_Set_Dma_Ops(struct device *dev, bool coherent) ++{ ++#if defined(CONFIG_ARM64) ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) ++ if(coherent) ++ set_dma_ops(dev, &coherent_swiotlb_dma_ops); ++ else ++ set_dma_ops(dev, &noncoherent_swiotlb_dma_ops); ++ #else ++ arch_setup_dma_ops(dev, 0, 0, NULL, coherent); ++ #endif ++#endif ++} ++ ++EXPORT_SYMBOL(MDrv_NOE_NAT_Set_Dma_Ops); ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/Kconfig b/drivers/sstar/noe/drv/nat/hw_nat/Kconfig +new file mode 100755 +index 000000000000..8935490554a9 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/Kconfig +@@ -0,0 +1,512 @@ ++config NOE_HW_NAT ++# tristate "HW NAT(** Work At Module Mode ONLY **)" ++ tristate ++ depends on NOE_NAT_HW ++ default m if NOE_NAT_HW ++ ++ ++config NOE_HW_NAT_LAN_VLANID ++# int "VLAN ID of LAN Ports" ++ int ++ depends on NOE_HW_NAT && !NOE_HW_NAT_MANUAL_BIND ++ default 1 ++# help ++# please choose any one of your LAN side VLAN IDs if you use different VLAN ID for each LAN port ++ ++config NOE_HW_NAT_WAN_VLANID ++# int "VLAN ID of WAN Ports" ++ int ++ depends on NOE_HW_NAT && !NOE_HW_NAT_MANUAL_BIND ++ default 2 ++# help ++# please choose any one of your WAN side VLAN IDs if you use different VLAN ID for each WAN port ++ ++config NOE_HW_NAT_BINDING_THRESHOLD ++# int "Binding Threshold (Unit:Packet Per Second)" ++ int ++ depends on NOE_HW_NAT ++ default 30 ++# help ++# When flow rate > Binding Threshold (# Packets Per Second), ++# the state will change to bind state ++ ++#choice ++# prompt "Foe Table Size" ++# depends on NOE_HW_NAT ++# default NOE_HW_NAT_TBL_4K ++# help ++# Number of entries in FoE Table ++ ++config NOE_HW_NAT_TBL_1K ++# bool "1K" ++ bool ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_TBL_2K ++# bool "2K" ++ bool ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_TBL_4K ++# bool "4K" ++ bool ++ default y ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_TBL_8K ++# bool "8K" ++ bool ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_TBL_16K ++# bool "16K" ++ bool ++ depends on NOE_HW_NAT ++#endchoice ++ ++config HNAT_V2 ++ bool ++ default y ++ depends on NOE_HW_NAT ++ ++#choice ++# prompt "Hash Algorithm" ++# depends on NOE_HW_NAT ++# default NOE_HW_NAT_HASH1 ++ ++config NOE_HW_NAT_HASH0 ++# bool "Hash0-Simple" ++ bool ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_HASH1 ++# bool "Hash1-Complex" ++ bool ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_HASH2 ++# bool "Hash2-Complex" ++ bool ++ default y ++ depends on NOE_HW_NAT && HNAT_V2 ++ ++config NOE_HW_NAT_HASH3 ++# bool "Hash3-Complex" ++ bool ++ depends on NOE_HW_NAT && HNAT_V2 ++ ++config NOE_HW_NAT_HASH_DBG ++# bool "Hash-Debug" ++ bool ++ depends on NOE_HW_NAT ++ ++#endchoice ++ ++#choice ++# prompt "HW_NAT OP MODE" ++# depends on NOE_HW_NAT && (NOE_HW_NAT_HASH1 || NOE_HW_NAT_HASH2) ++# default HW_NAT_AUTO_MODE ++# help ++# HWNAT Operation mode. There is three type operation mode you can choose. ++ ++config NOE_HW_NAT_AUTO_MODE ++ bool ++ default y ++# bool "AUTO_MODE" ++# help ++# Say Y here if you want to enable HWNAT Operation auto mode ++# There is hwnat auto learn mode, driver fill ppetable, ++# and set entry bind. ++ ++config NOE_HW_NAT_SEMI_AUTO_MODE ++ bool ++ default n ++# bool "SEMI_AUTO_MODE" ++# help ++# There is hwnat semi-auto learn mode, driver fill ppetable, ++# but user set entry bind. ++ ++config NOE_HW_NAT_MANUAL_MODE ++ bool ++ default n ++# bool "MANUAL_MODE" ++# help ++# There is hwnat manual mode, user fill ppetable, ++# but user set entry bind. ++ ++#endchoice ++ ++ ++ ++choice ++ prompt "Hash DBG Mode" ++ depends on NOE_HW_NAT_HASH_DBG ++ default NOE_HW_NAT_HASH_DBG_SPORT ++ ++config NOE_HW_NAT_HASH_DBG_IPV6_SIP ++ bool "IPv6 source IP[15:0]" ++ ++config NOE_HW_NAT_HASH_DBG_IPV4_SIP ++ bool "IPv4 source IP[15:0]" ++ ++config NOE_HW_NAT_HASH_DBG_SPORT ++ bool "source port[15:0]" ++ ++endchoice ++ ++config NOE_HW_NAT_PRE_ACL_SIZE ++ int "Pre ACL Table Size" ++ depends on NOE_HW_NAT && !HNAT_V2 ++ default 383 ++ help ++ Pre ACL + Pre/Post MTR + Pre/Post AC Must less than 512 ++ ++config NOE_HW_NAT_PRE_MTR_SIZE ++ int "Pre Meter Table Size" ++ depends on NOE_HW_NAT && !HNAT_V2 ++ default 32 ++ help ++ Pre ACL + Pre/Post MTR + Pre/Post AC Must less than 512 ++ ++config NOE_HW_NAT_PRE_AC_SIZE ++ int "Pre AC Table Size" ++ depends on NOE_HW_NAT && !HNAT_V2 ++ default 32 ++ help ++ Pre ACL + Pre/Post MTR + Pre/Post AC Must less than 512 ++ ++config NOE_HW_NAT_POST_MTR_SIZE ++ int "Post Meter Table Size" ++ depends on NOE_HW_NAT && !HNAT_V2 ++ default 32 ++ help ++ Pre ACL + Pre/Post MTR + Pre/Post AC Must less than 512 ++ ++config NOE_HW_NAT_POST_AC_SIZE ++ int "Post AC Table Size" ++ depends on NOE_HW_NAT && !HNAT_V2 ++ default 32 ++ help ++ Pre ACL + Pre/Post MTR + Pre/Post AC Must less than 512 ++ ++ ++config NOE_HW_NAT_TCP_KA ++# int "TCP KeepAlive Interval(Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_1K ++ default 5 ++ help ++ HW will duplicate one TCP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_UDP_KA ++# int "UDP KeepAlive Interval(Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_1K ++ default 5 ++ help ++ HW will duplicate one UDP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_NTU_KA ++# int "Non-TCP/UDP KeepAlive Interval(Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_1K && HNAT_V2 ++ default 5 ++ help ++ HW will duplicate one packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_TCP_KA ++# int "TCP KeepAlive Interval(Unit:2Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_2K ++ default 3 ++ help ++ HW will duplicate one TCP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++ ++ ++config NOE_HW_NAT_UDP_KA ++# int "UDP KeepAlive Interval(Unit:2Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_2K ++ default 3 ++ help ++ HW will duplicate one UDP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_NTU_KA ++# int "None-TCP/UDP KeepAlive Interval(Unit:2Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_2K && HNAT_V2 ++ default 3 ++ help ++ HW will duplicate one packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_TCP_KA ++# int "TCP KeepAlive Interval(Unit:4Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_4K ++ default 1 ++ help ++ HW will duplicate one TCP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++ ++ ++config NOE_HW_NAT_UDP_KA ++# int "UDP KeepAlive Interval(Unit:4Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_4K ++ default 1 ++ help ++ HW will duplicate one UDP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_NTU_KA ++# int "Non-TCP/UDP KeepAlive Interval(Unit:4Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_4K && HNAT_V2 ++ default 1 ++ help ++ HW will duplicate one packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_TCP_KA ++# int "TCP KeepAlive Interval(Unit:8Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_8K ++ default 1 ++ help ++ HW will duplicate one TCP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++ ++config NOE_HW_NAT_UDP_KA ++# int "UDP KeepAlive Interval(Unit:8Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_8K ++ default 1 ++ help ++ HW will duplicate one UDP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_NTU_KA ++# int "None-TCP/UDP KeepAlive Interval(Unit:8Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_8K && HNAT_V2 ++ default 1 ++ help ++ HW will duplicate one packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_TCP_KA ++# int "TCP KeepAlive Interval(Unit:16Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_16K ++ default 1 ++ help ++ HW will duplicate one TCP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++ ++config NOE_HW_NAT_UDP_KA ++# int "UDP KeepAlive Interval(Unit:16Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_16K ++ default 1 ++ help ++ HW will duplicate one UDP packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_NTU_KA ++# int "None-TCP/UDP KeepAlive Interval(Unit:16Sec)" ++ int ++ depends on NOE_HW_NAT_TBL_16K && HNAT_V2 ++ default 1 ++ help ++ HW will duplicate one packet from tcp bind flow to CPU ++ in order to refresh Linux conntrack table. ++ ++config NOE_HW_NAT_ACL_DLTA ++# int "Life time of ACL link to FOE entry(Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT && !HNAT_V2 ++ default 3 ++ help ++ Set ageout time for ACL link to FoE entry ++ ++config NOE_HW_NAT_UNB_DLTA ++# int "Life time of Unbind entry (Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT ++ default 3 ++ help ++ set ageout time for bind Unbind entry ++ ++config NOE_HW_NAT_UNB_MNP ++# int "Min threshold for unbind state(Pkt count)" ++ int ++ depends on NOE_HW_NAT ++ default 1000 ++ help ++ An unbind flow whose pkt counts < Min threshold and idle time > Life time ++ => This unbind entry would be aged out ++ [Notes: Idle time = current time - last packet receive time] ++ ++config NOE_HW_NAT_UDP_DLTA ++# int "Life time of Bind UDP entry (Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT ++ default 5 ++ help ++ Set ageout time for bind UDP entry ++ ++config NOE_HW_NAT_TCP_DLTA ++# int "Life time of Bind TCP entry (Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT ++ default 5 ++ help ++ Set ageout time for bind TCP entry ++ ++config NOE_HW_NAT_FIN_DLTA ++# int "Life time of Bind FIN entry (Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT ++ default 5 ++ help ++ Set ageout time for FIN entry ++ ++config NOE_HW_NAT_NTU_DLTA ++# int "Life time of Non-TCP/UDP entry (Unit:1Sec)" ++ int ++ depends on NOE_HW_NAT && HNAT_V2 ++ default 5 ++ help ++ Set ageout time for Non-TCP/UDP entry ++ ++config NOE_HW_NAT_IPV6 ++# bool "IPv6 Acceleration" ++ bool ++ depends on NOE_HW_NAT ++ default y ++ help ++ "ipv6 routing accelerated by HNAT" ++ ++config NOE_HW_NAT_ACL2UP_HELPER ++# bool "ACL -> UP helper" ++ bool ++ depends on NOE_HW_NAT && !HNAT_V2 ++ help ++ "use ACL rule to get user priority" ++ ++config NOE_HW_NAT_PREBIND ++# bool "Pre-bind support" ++ bool ++ default n ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_PBND_RD_PRD ++# int "check interval in pause state (us) Max:65535" ++ int ++ default 1000 ++ depends on NOE_HW_NAT_PREBIND ++ default 1 if (!NOE_HW_NAT_PREBIND) ++ ++config NOE_HW_NAT_PBND_RD_LMT ++ int "max retyr count" ++ default 10 ++ depends on NOE_HW_NAT_PREBIND ++ ++config PPE_MCAST ++# bool "PPE built-in multicast table support" ++ bool ++ default y ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_WIFI ++# bool "WiFi Acceleration" ++ bool ++ default y if NOE_HW_NAT ++ depends on NOE_HW_NAT ++ select NOE_HW_NAT_WIFI_NEW_ARCH ++ ++config NOE_HW_NAT_WIFI_NEW_ARCH ++# bool "WiFi Acceleration New Architecture / New Dev if" ++ bool ++ default y if NOE_HW_NAT_WIFI ++ depends on NOE_HW_NAT_WIFI ++ ++config HW_NAT_NEW_ARCH_WDMA ++# bool "WiFi Acceleration with WDMA" ++ bool ++ default y if NOE_HW_NAT_WIFI ++ depends on NOE_HW_NAT_WIFI ++ ++config NOE_HW_NAT_NIC_USB ++# bool "PCIe Ethernet NIC/USB Acceleration" ++ bool ++ default y ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_PPTP_L2TP ++# bool "PPTP_L2TP Acceleration" ++ bool ++ default n ++ ++config NOE_HW_NAT_PACKET_SAMPLING ++# bool "Packet Sampling to CPU" ++ bool ++ default n ++ depends on NOE_HW_NAT ++ ++config NOE_HW_NAT_ACCNT_MAINTAINER ++# bool "byte/pkt count for LAN/WAN port" ++ bool ++ default n ++ depends on NOE_HW_NAT && HNAT_V2 ++ help ++ "if you need 64bits bytes/pkts counter, and ask HNAT module to get statistic counter periodically, please enable it" ++ ++config PPE_MIB ++# bool "byte/pkt count for flow" ++ bool ++ default n ++ depends on NOE_HW_NAT && HNAT_V2 ++ help ++ "if you need bytes/pkts counter per flow entry, and ask HNAT module to get statistic counter periodically, please enable it" ++ ++config QDMA_SUPPORT_QOS ++# bool "qdma support qos" ++ bool ++ depends on NOE_HW_NAT ++ default y ++ help ++ "if you need qdma binding support qos, please enable it" ++ ++config WAN_TO_WLAN_SUPPORT_QOS ++# bool "wan to wlan support qos" ++ bool ++ depends on NOE_HW_NAT ++ select QDMA_SUPPORT_QoS ++ default y ++ help ++ "if you need qdma wan t0 wlan binding support qos, please enable it" ++ ++config SUPPORT_WLAN_OPTIMIZE ++# bool "bridge not binding" ++ bool ++ default n ++ ++config NOE_HW_NAT_IPI ++ bool ++# bool "Dispatch packets to CPUs" ++ default n ++ depends on NOE_HW_NAT && HNAT_V2 ++ help ++ "if you need hwnat ipi, must EXPORT_SYMBOL(get_rps_cpu)(net/core/dev.c)" ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/Makefile b/drivers/sstar/noe/drv/nat/hw_nat/Makefile +new file mode 100755 +index 000000000000..3c0a1ae55b83 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/Makefile +@@ -0,0 +1,39 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ifdef CONFIG_SSTAR_PROJECT_NAME ++ CONFIG_SSTAR_PROJECT_NAME := $(subst ",,$(CONFIG_SSTAR_PROJECT_NAME)) ++endif ++ ++ ++# general options ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/noe/drv/eth ++EXTRA_CFLAGS += -Idrivers/sstar/noe/hal/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++EXTRA_CFLAGS += -Idrivers/sstar/noe/drv/nat/hw_nat ++ ++ ++ifeq ($(CONFIG_NOE_QDMA),y) ++EXTRA_CFLAGS += -DCONFIG_RAETH_QDMA ++endif ++ ++ifeq ($(CONFIG_NOE_GMAC2),y) ++EXTRA_CFLAGS += -DCONFIG_RAETH_GMAC2 ++EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT ++endif ++EXTRA_CFLAGS += -DCONFIG_RA_NAT_HW ++ ++ ++obj-$(CONFIG_NOE_HW_NAT) += hw_nat.o ++hw_nat-objs := mdrv_hwnat.o ++hw_nat-objs += mdrv_hwnat_foe.o ++hw_nat-objs += mdrv_hwnat_util.o ++hw_nat-objs += mdrv_hwnat_ioctl.o ++hw_nat-objs += mdrv_hwnat_log.o ++hw_nat-objs += mdrv_hwnat_api.o ++ ++ ++hw_nat-objs += mdrv_hwnat_mcast.o ++hw_nat-objs += ../../../hal/$(CONFIG_SSTAR_CHIP_NAME)/mhal_hwnat.o ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat.c b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat.c +new file mode 100755 +index 000000000000..1f6fa56dd921 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat.c +@@ -0,0 +1,3261 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_NAT.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_hwnat.h" ++#include "mdrv_hwnat.h" ++#include "mdrv_hwnat_log.h" ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_util.h" ++#include "mdrv_hwnat_ioctl.h" ++#include "mdrv_hwnat_define.h" ++#include "mdrv_hwnat_mcast.h" ++#include "mdrv_hwnat_fast_path.h" ++#include "mdrv_noe_def.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define CB_OFF 10 ++#define HWNAT_GET_PACKET_IF(skb) skb->cb[CB_OFF + 6] ++#define MIN_NET_DEVICE_FOR_MBSSID 0x00 ++#define MIN_NET_DEVICE_FOR_WDS 0x10 ++#define MIN_NET_DEVICE_FOR_APCLI 0x20 ++#define MIN_NET_DEVICE_FOR_MESH 0x30 ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Variable and Functions ++//-------------------------------------------------------------------------------------------------- ++struct foe_entry *ppe_foe_base; ++EXPORT_SYMBOL(ppe_foe_base); ++extern unsigned int web_sfq_enable; ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++ ++static void _MDrv_HWNAT_Clear_Bind_Entry(struct neighbour *neigh); ++static void _MDrv_HWNAT_Handle_Ac_Update(unsigned long unused); ++ ++void _MDrv_HWNAT_Set_Entry_Bind(struct sk_buff *skb, struct foe_entry *entry); ++int32_t MDrv_HWNAT_Set_Force_Port(struct sk_buff *skb, struct foe_entry *entry, int gmac_no); ++static int32_t _MDrv_HWNAT_Fill_L2(struct sk_buff *skb, struct foe_entry *entry); ++static int32_t _MDrv_HWNAT_Fill_L3(struct sk_buff *skb, struct foe_entry *entry); ++static int32_t _MDrv_HWNAT_Fill_L4(struct sk_buff *skb, struct foe_entry *entry); ++void MDrv_NOE_NAT_Set_Dma_Ops(struct device *dev, bool coherent); ++static int MDrv_HWNAT_Handle_NetEvent(struct notifier_block *unused, unsigned long event, void *ptr); ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++/*for 16 queue test*/ ++unsigned char queue_number; ++ ++static u64 hwnat_dmamask = ~(u32)0; ++struct HWNAT_DEVICE _hwnat_info = { ++ .pdev = NULL, ++ .ppe_foe_base = NULL, ++ .ppe_ps_base = NULL, ++ .ppe_mib_base = NULL, ++ .table_entries = FOE_4TB_SIZ, ++ .hash_mode = DFL_FOE_HASH_MODE, ++ .hash_debug = DEF_HASH_DBG_MODE, ++ .lan_vid = CONFIG_NOE_HW_NAT_LAN_VLANID, ++ .wan_vid = CONFIG_NOE_HW_NAT_WAN_VLANID, ++ .bind_dir = BIDIRECTION, ++ .debug_level = 0, ++ .log_level = E_MDRV_HWNAT_MSG_CTRL_DBG, ++}; ++ ++static struct notifier_block Hnat_netevent_nb __read_mostly = { ++ .notifier_call = MDrv_HWNAT_Handle_NetEvent, ++}; ++ ++ ++ ++DEFINE_TIMER(update_foe_ac_timer, _MDrv_HWNAT_Handle_Ac_Update, 0, 0); ++ ++int hwnat_info_region; ++int getBrLan = 0; ++uint32_t brNetmask; ++uint32_t br0Ip; ++char br0_mac_address[6]; ++ ++ ++struct timer_list hwnat_clear_entry_timer; ++ ++u8 USE_3T_UDP_FRAG; ++ ++struct pkt_parse_result ppe_parse_result; ++ ++struct hwnat_ac_args ac_info[64]; /* 1 for LAN, 2 for WAN */ ++ ++struct net_device *dev; ++int fast_bind; ++u8 hash_cnt; ++int DP_GMAC1; ++int DPORT_GMAC2; ++ ++/*for 16 queue test*/ ++unsigned char queue_number; ++u32 pptp_fast_path = 0; ++u32 l2tp_fast_path = 0; ++ ++ ++/* #define DSCP_REMARK_TEST */ ++/* #define PREBIND_TEST */ ++ ++static int _MDrv_HWNAT_Get_Dev_Handler_Idx(struct net_device *dev) ++{ ++ int i; ++ if (dev == NULL) ++ return -1; ++ ++ for (i = 0; i < MAX_IF_NUM; i++) { ++ if (dst_port[i] == dev) { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("%s dst_port table has beed registered(%d)\n", dev->name, i); ++ return i; ++ } ++ } ++ return -1; ++} ++ ++static void _MDrv_HWNAT_Clear_Entry(unsigned long data) ++{ ++ HWNAT_MSG_DBG("HW_NAT work normally\n"); ++ MHal_HWNAT_Set_Miss_Action(E_HWNAT_FOE_SEARCH_MISS_FWD_CPU_BUILD_ENTRY); ++ //del_timer_sync(&hwnat_clear_entry_timer); ++} ++ ++uint16_t IS_IF_PCIE_WLAN(struct sk_buff *skb) ++{ ++ if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) ++ return IS_IF_PCIE_WLAN_HEAD(skb); ++ else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) ++ return IS_IF_PCIE_WLAN_TAIL(skb); ++ else if (IS_MAGIC_TAG_PROTECT_VALID_CB(skb)) ++ return IS_IF_PCIE_WLAN_CB(skb); ++ else ++ return 0; ++} ++ ++uint16_t IS_IF_PCIE_WLAN_RX(struct sk_buff *skb) ++{ ++ return IS_IF_PCIE_WLAN_HEAD(skb); ++} ++ ++uint16_t IS_MAGIC_TAG_PROTECT_VALID(struct sk_buff *skb) ++{ ++ if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) ++ return IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb); ++ else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) ++ return IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb); ++ else if (IS_MAGIC_TAG_PROTECT_VALID_CB(skb)) ++ return IS_MAGIC_TAG_PROTECT_VALID_CB(skb); ++ else ++ return 0; ++} ++ ++unsigned char *FOE_INFO_START_ADDR(struct sk_buff *skb) ++{ ++ if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) ++ return FOE_INFO_START_ADDR_HEAD(skb); ++ else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) ++ return FOE_INFO_START_ADDR_TAIL(skb); ++ else if (IS_MAGIC_TAG_PROTECT_VALID_CB(skb)) ++ return FOE_INFO_START_ADDR_CB(skb); ++ ++ NAT_PRINT("!!!FOE_INFO_START_ADDR Error!!!!\n"); ++ return FOE_INFO_START_ADDR_HEAD(skb); ++} ++ ++ ++uint16_t _MDrv_HWNAT_Get_Tx_Region(struct sk_buff *skb) ++{ ++ if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb) && IS_SPACE_AVAILABLE_HEAD(skb)) { ++ FOE_INFO_START_ADDR(skb); ++ FOE_TAG_PROTECT(skb) = FOE_TAG_PROTECT_HEAD(skb); ++ FOE_ENTRY_NUM(skb) = FOE_ENTRY_NUM_HEAD(skb); ++ FOE_ALG(skb) = FOE_ALG_HEAD(skb); ++ FOE_AI(skb) = FOE_AI_HEAD(skb); ++ FOE_SP(skb) = FOE_SP_HEAD(skb); ++ FOE_MAGIC_TAG(skb) = FOE_MAGIC_TAG_HEAD(skb); ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ FOE_WDMA_ID(skb) = FOE_WDMA_ID_HEAD(skb); ++ FOE_RX_ID(skb) = FOE_RX_ID_HEAD(skb); ++ FOE_WC_ID(skb) = FOE_WC_ID_HEAD(skb); ++ FOE_BSS_ID(skb) = FOE_BSS_ID_HEAD(skb); ++ } ++ if (_hwnat_info.features & PPTP_L2TP) { ++ FOE_SOURCE(skb) = FOE_SOURCE_HEAD(skb); ++ FOE_DEST(skb) = FOE_DEST_HEAD(skb); ++ } ++ hwnat_info_region = USE_HEAD_ROOM; ++ return USE_HEAD_ROOM; /* use headroom */ ++ } ++ else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb) && IS_SPACE_AVAILABLE_TAIL(skb)) { ++ FOE_INFO_START_ADDR(skb); ++ FOE_TAG_PROTECT(skb) = FOE_TAG_PROTECT_TAIL(skb); ++ FOE_ENTRY_NUM(skb) = FOE_ENTRY_NUM_TAIL(skb); ++ FOE_ALG(skb) = FOE_ALG_TAIL(skb); ++ FOE_AI(skb) = FOE_AI_TAIL(skb); ++ FOE_SP(skb) = FOE_SP_TAIL(skb); ++ FOE_MAGIC_TAG(skb) = FOE_MAGIC_TAG_TAIL(skb); ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ FOE_WDMA_ID(skb) = FOE_WDMA_ID_TAIL(skb); ++ FOE_RX_ID(skb) = FOE_RX_ID_TAIL(skb); ++ FOE_WC_ID(skb) = FOE_WC_ID_TAIL(skb); ++ FOE_BSS_ID(skb) = FOE_BSS_ID_TAIL(skb); ++ } ++ if (_hwnat_info.features & PPTP_L2TP) { ++ FOE_SOURCE(skb) = FOE_SOURCE_TAIL(skb); ++ FOE_DEST(skb) = FOE_DEST_TAIL(skb); ++ } ++ hwnat_info_region = USE_TAIL_ROOM; ++ return USE_TAIL_ROOM; /* use tailroom */ ++ } ++ else if (IS_MAGIC_TAG_PROTECT_VALID_CB(skb)) { ++ FOE_INFO_START_ADDR(skb); ++ FOE_TAG_PROTECT(skb) = FOE_TAG_PROTECT_CB0(skb); ++ FOE_ENTRY_NUM(skb) = FOE_ENTRY_NUM_CB(skb); ++ FOE_ALG(skb) = FOE_ALG_CB(skb); ++ FOE_AI(skb) = FOE_AI_CB(skb); ++ FOE_SP(skb) = FOE_SP_CB(skb); ++ FOE_MAGIC_TAG(skb) = FOE_MAGIC_TAG_CB(skb); ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ FOE_WDMA_ID(skb) = FOE_WDMA_ID_CB(skb); ++ FOE_RX_ID(skb) = FOE_RX_ID_CB(skb); ++ FOE_WC_ID(skb) = FOE_WC_ID_CB(skb); ++ FOE_BSS_ID(skb) = FOE_BSS_ID_CB(skb); ++ } ++ if (_hwnat_info.features & PPTP_L2TP) { ++ //FOE_SOURCE(skb) = FOE_SOURCE_CB(skb); ++ //FOE_DEST(skb) = FOE_DEST_CB(skb); ++ } ++ hwnat_info_region = USE_CB; ++ return USE_CB; /* use CB */ ++ } ++ hwnat_info_region = ALL_INFO_ERROR; ++ return ALL_INFO_ERROR; ++} ++ ++uint16_t _MDrv_HWNAT_Remove_Vlan_Tag(struct sk_buff *skb) ++{ ++ struct ethhdr *eth; ++ struct vlan_ethhdr *veth; ++ u16 vir_if_idx; ++ ++ veth = (struct vlan_ethhdr *)skb_mac_header(skb); ++ /* something wrong */ ++ if ((veth->h_vlan_proto != htons(ETH_P_8021Q)) && (veth->h_vlan_proto != 0x5678)) { ++ //if (pr_debug_ratelimited()) ++ NAT_PRINT("HNAT: Reentry packet is untagged frame?\n"); ++ return 65535; ++ } ++ ++ vir_if_idx = ntohs(veth->h_vlan_TCI) & 0x3FFFF; ++ ++ if (skb_cloned(skb) || skb_shared(skb)) { ++ struct sk_buff *new_skb; ++ ++ new_skb = skb_copy(skb, GFP_ATOMIC); ++ kfree_skb(skb); ++ if (!new_skb) ++ return 65535; ++ skb = new_skb; ++ } ++ ++ /* remove VLAN tag */ ++ skb->data = skb_mac_header(skb); ++ skb->mac_header = skb->mac_header + VLAN_HLEN; ++ memmove(skb_mac_header(skb), skb->data, ETH_ALEN * 2); ++ ++ skb_pull(skb, VLAN_HLEN); ++ skb->data += ETH_HLEN; /* pointer to layer3 header */ ++ eth = (struct ethhdr *)skb_mac_header(skb); ++ ++ skb->protocol = eth->h_proto; ++ ++ return vir_if_idx; ++} ++ ++ ++static int _MDrv_HWNAT_Alloc_Tbl( struct HWNAT_DEVICE *phwnat) ++{ ++ //int ret = 1; ++ u32 ppe_phy_foebase_tmp; ++ struct foe_entry *entry; ++ struct device *dev = NULL; ++ ++ phwnat->foe_tbl_size = phwnat->table_entries* sizeof(struct foe_entry); ++ MHAL_HWNAT_Get_Addr(&ppe_phy_foebase_tmp); ++ dev = &(phwnat->pdev->dev); ++ ++ if (ppe_phy_foebase_tmp) { ++ phwnat->ppe_phy_foe_base = (dma_addr_t)ppe_phy_foebase_tmp; ++ phwnat->ppe_foe_base = (struct foe_entry *)ppe_virt_foe_base_tmp; ++ HWNAT_MSG_DBG("***ppe_foe_base = %p\n", phwnat->ppe_foe_base); ++ HWNAT_MSG_DBG("***PpeVirtFoeBase_tmp = %p\n", ppe_virt_foe_base_tmp); ++ if (!phwnat->ppe_foe_base) { ++ MHAL_HWNAT_Get_Addr(&ppe_phy_foebase_tmp); ++ HWNAT_MSG_ERR("ioremap fail!!!!, Base Addr=%x\n", ppe_phy_foebase_tmp); ++ return 0; ++ } ++ } ++ else { ++ phwnat->ppe_foe_base = dma_alloc_coherent(dev, phwnat->foe_tbl_size, &(phwnat->ppe_phy_foe_base), GFP_KERNEL); ++ ppe_foe_base = phwnat->ppe_foe_base; ++ ppe_virt_foe_base_tmp = phwnat->ppe_foe_base; ++ HWNAT_MSG_DBG("init PpeVirtFoeBase_tmp = %p\n", ppe_virt_foe_base_tmp); ++ HWNAT_MSG_DBG("init ppe_foe_base = %p\n", phwnat->ppe_foe_base); ++ ++ if (!phwnat->ppe_foe_base) { ++ HWNAT_MSG_ERR("first ppe_phy_foe_base fail\n"); ++ return 0; ++ } ++ } ++ ++ if (!phwnat->ppe_foe_base) { ++ HWNAT_MSG_ERR("ppe_foe_base== NULL\n"); ++ return 0; ++ } ++ ++ memset(phwnat->ppe_foe_base, 0, phwnat->foe_tbl_size); ++ entry = ((struct foe_entry *)phwnat->ppe_foe_base); ++ ++ ++ if (phwnat->features & PACKET_SAMPLING) { ++ phwnat->ps_tbl_size = phwnat->table_entries * sizeof(struct ps_entry); ++ phwnat->ppe_ps_base = dma_alloc_coherent(dev, phwnat->ps_tbl_size, &phwnat->ppe_phy_ps_base, GFP_KERNEL); ++ ++ if (!phwnat->ppe_ps_base) ++ return 0; ++ ++ memset(phwnat->ppe_ps_base, 0, phwnat->ps_tbl_size); ++ } ++ else { ++ phwnat->ppe_ps_base = 0; ++ phwnat->ppe_phy_ps_base = HWNAT_INVALID_PHY_ADDR; ++ } ++ ++ if (phwnat->features & PPE_MIB) { ++ phwnat->mib_tbl_size = phwnat->table_entries * sizeof(struct mib_entry); ++ phwnat->ppe_mib_base = dma_alloc_coherent(dev, phwnat->mib_tbl_size, &phwnat->ppe_phy_mib_base, GFP_KERNEL); ++ if (!phwnat->ppe_mib_base) { ++ HWNAT_MSG_ERR("PPE MIB allocate memory fail"); ++ return 0; ++ } ++ memset(phwnat->ppe_mib_base, 0, phwnat->mib_tbl_size); ++ } ++ else { ++ phwnat->ppe_mib_base = 0; ++ phwnat->ppe_phy_mib_base = HWNAT_INVALID_PHY_ADDR; ++ } ++ ++ HWNAT_MSG_DBG("ppe_mib_base = %p\n", phwnat->ppe_mib_base); ++ HWNAT_MSG_DBG("ppe_phy_mib_base = %x\n", phwnat->ppe_phy_mib_base); ++ HWNAT_MSG_DBG("num_of_entry = %u\n", phwnat->table_entries); ++ HWNAT_MSG_DBG("sizeof(struct mib_entry) = %u\n", sizeof(struct mib_entry)); ++ HWNAT_MSG_DBG("mib_tbl_size = %d\n", phwnat->mib_tbl_size); ++ ++ return 1; ++} ++ ++ ++ ++ ++ ++static MS_BOOL _MDrv_HWNAT_Get_Bridge_Info(void) ++{ ++ struct net_device *br0_dev; ++ struct in_device *br0_in_dev; ++ ++ br0_dev = dev_get_by_name(&init_net,"br0"); ++ if (br0_dev == NULL) { ++ if (_hwnat_info.debug_level >= 7) { ++ NAT_PRINT("br0_dev = NULL\n"); ++ } ++ return FALSE; ++ } ++ br0_in_dev = in_dev_get(br0_dev); ++ if (br0_in_dev == NULL) { ++ if (_hwnat_info.debug_level >= 7) { ++ NAT_PRINT("br0_in_dev = NULL\n"); ++ } ++ return FALSE; ++ } ++ brNetmask = ntohl(br0_in_dev->ifa_list->ifa_mask); ++ br0Ip = ntohl(br0_in_dev->ifa_list->ifa_address); ++ ++ if(br0_dev != NULL) { ++ dev_put(br0_dev); ++ } ++ ++ if (br0_in_dev != NULL) { ++ in_dev_put(br0_in_dev); ++ } ++ ++ NAT_PRINT("br0Ip = %x\n", br0Ip); ++ NAT_PRINT("brNetmask = %x\n", brNetmask); ++ getBrLan = 1; ++ ++ return TRUE; ++} ++ ++ ++static int _MDrv_HWNAT_Is_BrLan_Subnet(struct sk_buff *skb) ++{ ++ struct iphdr *iph = NULL; ++ uint32_t daddr = 0; ++ uint32_t saddr = 0; ++ u32 eth_type, ppp_tag = 0; ++ struct vlan_hdr *vh = NULL; ++ struct ethhdr *eth = NULL; ++ struct pppoe_hdr *peh = NULL; ++ u8 vlan1_gap = 0; ++ u8 vlan2_gap = 0; ++ u8 pppoe_gap = 0; ++ ++ struct vlan_hdr pseudo_vhdr; ++ ++ eth = (struct ethhdr *)skb->data; ++ if(is_multicast_ether_addr(ð->h_dest[0])) ++ return 0; ++ eth_type = eth->h_proto; ++ if ((eth_type == htons(ETH_P_8021Q)) || ++ (((eth_type) & 0x00FF) == htons(ETH_P_8021Q)) || hwnat_vlan_tx_tag_present(skb)) { ++ ++ if (_hwnat_info.features & HW_NAT_VLAN_TX) { ++ pseudo_vhdr.h_vlan_TCI = htons(hwnat_vlan_tag_get(skb)); ++ pseudo_vhdr.h_vlan_encapsulated_proto = eth->h_proto; ++ vh = (struct vlan_hdr *)&pseudo_vhdr; ++ vlan1_gap = VLAN_HLEN; ++ } ++ else { ++ vlan1_gap = VLAN_HLEN; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ } ++ /* VLAN + PPPoE */ ++ if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_PPP_SES) { ++ pppoe_gap = 8; ++ eth_type = vh->h_vlan_encapsulated_proto; ++ /* Double VLAN = VLAN + VLAN */ ++ } ++ else if ((vh->h_vlan_encapsulated_proto == htons(ETH_P_8021Q)) || ++ ((vh->h_vlan_encapsulated_proto) & 0x00FF) == htons(ETH_P_8021Q)) { ++ ++ vlan2_gap = VLAN_HLEN; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN + VLAN_HLEN); ++ /* VLAN + VLAN + PPPoE */ ++ if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_PPP_SES) { ++ pppoe_gap = 8; ++ eth_type = vh->h_vlan_encapsulated_proto; ++ }else ++ eth_type = vh->h_vlan_encapsulated_proto; ++ } ++ } ++ else if (ntohs(eth_type) == ETH_P_PPP_SES) { ++ /* PPPoE + IP */ ++ pppoe_gap = 8; ++ peh = (struct pppoe_hdr *)(skb->data + ETH_HLEN + vlan1_gap); ++ ppp_tag = peh->tag[0].tag_type; ++ } ++ ++ if (getBrLan == 0) { ++ if (_MDrv_HWNAT_Get_Bridge_Info() == FALSE) /*br0 get fail*/ ++ return 0; ++ } ++ /* set layer4 start addr */ ++ if ((eth_type == htons(ETH_P_IP)) || (eth_type == htons(ETH_P_PPP_SES) && ppp_tag == htons(PPP_IP))) { ++ iph = (struct iphdr *)(skb->data + ETH_HLEN + vlan1_gap + vlan2_gap + pppoe_gap); ++ daddr = ntohl(iph->daddr); ++ saddr = ntohl(iph->saddr); ++ } ++ ++ if (((br0Ip & brNetmask) == (daddr & brNetmask)) && ((daddr & brNetmask) == (saddr & brNetmask))) ++ return 1; ++ return 0; ++} ++ ++static int _MDrv_HWNAT_Is_Rx_Short_Cut(struct sk_buff *skb) ++{ ++ struct iphdr *iph = NULL; ++ uint32_t daddr; ++ ++ if (getBrLan == 0) { ++ if (_MDrv_HWNAT_Get_Bridge_Info() == FALSE) /*br0 get fail*/ ++ return 0; ++ } ++ ++ iph = (struct iphdr *)(skb->data); ++ daddr = ntohl(iph->daddr); ++ if ((br0Ip & brNetmask) == (daddr & brNetmask)) ++ return 1; ++ else ++ return 0; ++} ++ ++static uint32_t _MDrv_HWNAT_Get_Extif_Idx(struct net_device *dev) ++{ ++ ++ if (_hwnat_info.features & HW_NAT_MBSS_SUPPORT) { ++ if (dev == dst_port[DP_RA1]) ++ return DP_RA1; ++ else if (dev == dst_port[DP_RA2]) ++ return DP_RA2; ++ else if (dev == dst_port[DP_RA3]) ++ return DP_RA3; ++ else if (dev == dst_port[DP_RA4]) ++ return DP_RA4; ++ else if (dev == dst_port[DP_RA5]) ++ return DP_RA5; ++ else if (dev == dst_port[DP_RA6]) ++ return DP_RA6; ++ else if (dev == dst_port[DP_RA7]) ++ return DP_RA7; ++ else if (dev == dst_port[DP_RA8]) ++ return DP_RA8; ++ else if (dev == dst_port[DP_RA9]) ++ return DP_RA9; ++ else if (dev == dst_port[DP_RA10]) ++ return DP_RA10; ++ else if (dev == dst_port[DP_RA11]) ++ return DP_RA11; ++ else if (dev == dst_port[DP_RA12]) ++ return DP_RA12; ++ else if (dev == dst_port[DP_RA13]) ++ return DP_RA13; ++ else if (dev == dst_port[DP_RA14]) ++ return DP_RA14; ++ else if (dev == dst_port[DP_RA15]) ++ return DP_RA15; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_WDS_SUPPORT) { ++ if (dev == dst_port[DP_WDS0]) ++ return DP_WDS0; ++ else if (dev == dst_port[DP_WDS1]) ++ return DP_WDS1; ++ else if (dev == dst_port[DP_WDS2]) ++ return DP_WDS2; ++ else if (dev == dst_port[DP_WDS3]) ++ return DP_WDS3; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_APCLI_SUPPORT) { ++ if (dev == dst_port[DP_APCLI0]) ++ return DP_APCLI0; ++ else if (dev == dst_port[DP_APCLII0]) ++ return DP_APCLII0; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_AP_MESH_SUPPORT) { ++ if (dev == dst_port[DP_MESH0]) ++ return DP_MESH0; ++ else if (dev == dst_port[DP_MESHI0]) ++ return DP_MESHI0; ++ ++ } ++ ++ if (IS_SPECIAL_DEV_OR_AP(_hwnat_info.features)) { ++ if (dev == dst_port[DP_RAI0]) ++ return DP_RAI0; ++ ++ if (_hwnat_info.features & HW_NAT_AP_MBSS_SUPPORT) { ++ if (dev == dst_port[DP_RAI1]) ++ return DP_RAI1; ++ else if (dev == dst_port[DP_RAI2]) ++ return DP_RAI2; ++ else if (dev == dst_port[DP_RAI3]) ++ return DP_RAI3; ++ else if (dev == dst_port[DP_RAI4]) ++ return DP_RAI4; ++ else if (dev == dst_port[DP_RAI5]) ++ return DP_RAI5; ++ else if (dev == dst_port[DP_RAI6]) ++ return DP_RAI6; ++ else if (dev == dst_port[DP_RAI7]) ++ return DP_RAI7; ++ else if (dev == dst_port[DP_RAI8]) ++ return DP_RAI8; ++ else if (dev == dst_port[DP_RAI9]) ++ return DP_RAI9; ++ else if (dev == dst_port[DP_RAI10]) ++ return DP_RAI10; ++ else if (dev == dst_port[DP_RAI11]) ++ return DP_RAI11; ++ else if (dev == dst_port[DP_RAI12]) ++ return DP_RAI12; ++ else if (dev == dst_port[DP_RAI13]) ++ return DP_RAI13; ++ else if (dev == dst_port[DP_RAI14]) ++ return DP_RAI14; ++ else if (dev == dst_port[DP_RAI15]) ++ return DP_RAI15; ++ } ++ } ++ ++ if (_hwnat_info.features & HW_NAT_WDS_SUPPORT) { ++ if (dev == dst_port[DP_WDSI0]) ++ return DP_WDSI0; ++ else if (dev == dst_port[DP_WDSI1]) ++ return DP_WDSI1; ++ else if (dev == dst_port[DP_WDSI2]) ++ return DP_WDSI2; ++ else if (dev == dst_port[DP_WDSI3]) ++ return DP_WDSI3; ++ } ++ ++ ++ if (_hwnat_info.features & HW_NAT_NIC_USB) { ++ if (dev == dst_port[DP_PCI]) ++ return DP_PCI; ++ else if (dev == dst_port[DP_USB]) ++ return DP_USB; ++ } ++ ++ if (dev == dst_port[DP_RA0]) ++ return DP_RA0; ++ ++ NAT_PRINT("HNAT: %s The interface %p is unknown \n", __func__, dev); ++ ++ return 0; ++} ++ ++ ++/* push different VID for WiFi pseudo interface or USB external NIC */ ++uint32_t _MDrv_HWNAT_Handle_Extif_Rx(struct sk_buff *skb) ++{ ++ u16 vir_if_idx = 0; ++ int i = 0; ++ int dev_match = 0; ++ struct ethhdr *eth = NULL; ++ ++ if (((_hwnat_info.features & HW_NAT_WIFI) == 0) && ((_hwnat_info.features & HW_NAT_NIC_USB) == 0)) { ++ return 1; ++ } ++ ++ eth = (struct ethhdr *)skb_mac_header(skb); ++ ++ /* PPE can only handle IPv4/IPv6/PPP packets */ ++ if (((skb->protocol != htons(ETH_P_8021Q)) && ++ (skb->protocol != htons(ETH_P_IP)) && (skb->protocol != htons(ETH_P_IPV6)) && ++ (skb->protocol != htons(ETH_P_PPP_SES)) && (skb->protocol != htons(ETH_P_PPP_DISC))) || ++ is_multicast_ether_addr(ð->h_dest[0])) { ++ return 1; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) { ++ for (i = 0; i < MAX_IF_NUM; i++) { ++ if (dst_port[i] == skb->dev) { ++ vir_if_idx = i; ++ dev_match = 1; ++ /* NAT_PRINT("Interface=%s, vir_if_idx=%x\n", skb->dev->name, vir_if_idx); */ ++ break; ++ } ++ } ++ if (dev_match == 0) { ++ if (pr_debug_ratelimited()) ++ NAT_PRINT("UnKnown Interface (%s), vir_if_idx=%x\n", skb->dev->name, vir_if_idx); ++ /* kfree_skb(skb); */ ++ return 1; ++ } ++ } ++ else { ++ vir_if_idx = _MDrv_HWNAT_Get_Extif_Idx(skb->dev); ++ skb_set_network_header(skb, 0); ++ if (_hwnat_info.features & WLAN_OPTIMIZE) { ++ /*ppe_rx_parse_layer_info(skb);*/ ++ if (_MDrv_HWNAT_Is_Rx_Short_Cut(skb)) ++ return 1; /* Bridge ==> sw path (rps) */ ++ } ++ } ++ /* push vlan tag to stand for actual incoming interface, */ ++ /* so HNAT module can know the actual incoming interface from vlan id. */ ++ skb_push(skb, ETH_HLEN);/* pointer to layer2 header before calling hard_start_xmit */ ++#ifdef CONFIG_SUPPORT_WLAN_QOS ++ MDrv_HWNAT_Set_Qid(skb); ++#endif ++ ++ skb->vlan_proto = htons(ETH_P_8021Q); ++ if (_hwnat_info.features & HW_NAT_VLAN_TX) { ++ skb->vlan_tci |= VLAN_TAG_PRESENT; ++ skb->vlan_tci |= vir_if_idx; ++ } ++ else { ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) ++ skb = __vlan_put_tag(skb, skb->vlan_proto, vir_if_idx); ++ #else ++ skb = vlan_insert_tag(skb, skb->vlan_proto, vir_if_idx); ++ #endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) */ ++ } ++ /* redirect to PPE */ ++ FOE_AI_HEAD(skb) = UN_HIT; ++ FOE_AI_TAIL(skb) = UN_HIT; ++ FOE_TAG_PROTECT_HEAD(skb) = TAG_PROTECT; ++ FOE_TAG_PROTECT_TAIL(skb) = TAG_PROTECT; ++ FOE_MAGIC_TAG_HEAD(skb) = FOE_MAGIC_PPE; ++ FOE_MAGIC_TAG_TAIL(skb) = FOE_MAGIC_PPE; ++ ++ ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) ++ skb->dev = dst_port[DP_GMAC1]; /* we use GMAC1 to send the packet to PPE */ ++ else ++ skb->dev = dst_port[DP_GMAC]; /* we use GMAC1 to send the packet to PPE */ ++ ++#ifdef CONFIG_SUPPORT_WLAN_QOS ++ if (_hwnat_info.debug_level >= 2) ++ NAT_PRINT("skb->dev = %s\n", skb->dev); ++ if ((skb->dev == NULL) || ((skb->dev != dst_port[DPORT_GMAC2]) && (skb->dev != dst_port[DP_GMAC1]))) { ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) ++ skb->dev = dst_port[DP_GMAC1]; /* we use GMAC1 to send the packet to PPE */ ++ else ++ skb->dev = dst_port[DP_GMAC]; /* we use GMAC1 to send the packet to PPE */ ++ } ++#endif ++ ++ ++ dev_queue_xmit(skb); ++ return 0; ++} ++ ++uint32_t _MDrv_HWNAT_Handle_Pptp_L2tp_Pingpong(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ unsigned int addr = 0; ++ unsigned int src_ip = 0; ++ ++ /* PPTP/L2TP use this pingpong tech */ ++ /* NAT_PRINT("get fast_path ping pong skb_length is %d\n", skb->len); */ ++ if ((pptp_fast_path || l2tp_fast_path) && ((skb->len == 110) || (skb->len == 98))) { ++ if (FOE_AI(skb) == UN_HIT) { ++ dev_kfree_skb_any(skb); /*avoid memory leak */ ++ return 0; ++ } ++ /* wan->lan ping-pong, pass up to tx handler for binding */ ++ /* NAT_PRINT("Parse ping pong packets FOE_AI(skb)= 0x%2x!!\n", FOE_AI(skb)); */ ++ /* get start addr for each layer */ ++ if (MDrv_HWNAT_Pptp_Lan_Parse_Layer(skb)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("_MDrv_HWNAT_Fill_L2\n"); ++ /* Set Layer2 Info */ ++ if (_MDrv_HWNAT_Fill_L2(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("_MDrv_HWNAT_Fill_L3\n"); ++ /* Set Layer3 Info */ ++ if (_MDrv_HWNAT_Fill_L3(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("_MDrv_HWNAT_Fill_L4\n"); ++ /* Set Layer4 Info */ ++ if (_MDrv_HWNAT_Fill_L4(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ ++ /* Set force port info to 1 */ ++ /* if (MDrv_HWNAT_Set_Force_Port(skb, entry, gmac_no)) */ ++ if (MDrv_HWNAT_Set_Force_Port(skb, entry, 1)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ /* Enter binding state */ ++ _MDrv_HWNAT_Set_Entry_Bind(skb, entry); ++ fast_bind = 1; ++ addr = ((htons(entry->ipv4_hnapt.sport) << 16) | htons(entry->ipv4_hnapt.dport)); ++ src_ip = (htonl(entry->ipv4_hnapt.sip)); ++ MDrv_HWNAT_Pptp_L2tp_Update_Entry(ppe_parse_result.iph.protocol, addr, src_ip, FOE_ENTRY_NUM(skb)); ++ /*free pingpong packet */ ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ return 1; ++} ++ ++uint32_t _MDrv_HWNAT_Handle_Extif_Pingpong(struct sk_buff *skb) ++{ ++ struct ethhdr *eth = NULL; ++ u16 vir_if_idx = 0; ++ struct net_device *dev; ++ ++ if (((_hwnat_info.features & HW_NAT_WIFI) == 0) && ((_hwnat_info.features & HW_NAT_NIC_USB) == 0)) { ++ return 1; ++ } ++ vir_if_idx = _MDrv_HWNAT_Remove_Vlan_Tag(skb); ++ ++ /* recover to right incoming interface */ ++ if (vir_if_idx < MAX_IF_NUM && dst_port[vir_if_idx]) { ++ skb->dev = dst_port[vir_if_idx]; ++ } ++ else { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("%s : HNAT: unknown interface (vir_if_idx=%d)\n", __func__, vir_if_idx); ++ return 1; ++ } ++ ++ eth = (struct ethhdr *)skb_mac_header(skb); ++ ++ if (eth->h_dest[0] & 1) { ++ if (memcmp(eth->h_dest, skb->dev->broadcast, ETH_ALEN) == 0) { ++ skb->pkt_type = PACKET_BROADCAST; ++ } else { ++ skb->pkt_type = PACKET_MULTICAST; ++ } ++ } ++ else { ++ ++ skb->pkt_type = PACKET_OTHERHOST; ++ for (vir_if_idx = 0; vir_if_idx < MAX_IF_NUM; vir_if_idx++) { ++ dev = dst_port[vir_if_idx]; ++ if (dev !=NULL && memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN) == 0) { ++ skb->pkt_type = PACKET_HOST; ++ break; ++ } ++ } ++ } ++ ++ return 1; ++} ++ ++uint32_t _MDrv_HWNAT_Handle_Keep_Alive(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ struct ethhdr *eth = NULL; ++ u16 eth_type = ntohs(skb->protocol); ++ u32 vlan1_gap = 0; ++ u32 vlan2_gap = 0; ++ u32 pppoe_gap = 0; ++ struct vlan_hdr *vh; ++ struct iphdr *iph = NULL; ++ struct tcphdr *th = NULL; ++ struct udphdr *uh = NULL; ++ ++/* try to recover to original SMAC/DMAC, but we don't have such information.*/ ++/* just use SMAC as DMAC and set Multicast address as SMAC.*/ ++ eth = (struct ethhdr *)(skb->data - ETH_HLEN); ++ ++ MDrv_HWNAT_Util_Memcpy(eth->h_dest, eth->h_source, ETH_ALEN); ++ MDrv_HWNAT_Util_Memcpy(eth->h_source, eth->h_dest, ETH_ALEN); ++ eth->h_source[0] = 0x1; /* change to multicast packet, make bridge not learn this packet */ ++ if (eth_type == ETH_P_8021Q) { ++ vlan1_gap = VLAN_HLEN; ++ vh = (struct vlan_hdr *)skb->data; ++ ++ if (ntohs(vh->h_vlan_TCI) == _hwnat_info.wan_vid) { ++ /* It make packet like coming from LAN port */ ++ vh->h_vlan_TCI = htons(_hwnat_info.lan_vid); ++ } ++ else { ++ /* It make packet like coming from WAN port */ ++ vh->h_vlan_TCI = htons(_hwnat_info.wan_vid); ++ } ++ ++ if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_PPP_SES) { ++ pppoe_gap = 8; ++ } ++ else if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_8021Q) { ++ vlan2_gap = VLAN_HLEN; ++ vh = (struct vlan_hdr *)(skb->data + VLAN_HLEN); ++ ++ /* VLAN + VLAN + PPPoE */ ++ if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_PPP_SES) { ++ pppoe_gap = 8; ++ } ++ else { ++ /* VLAN + VLAN + IP */ ++ eth_type = ntohs(vh->h_vlan_encapsulated_proto); ++ } ++ } ++ else { ++ /* VLAN + IP */ ++ eth_type = ntohs(vh->h_vlan_encapsulated_proto); ++ } ++ } ++ ++ /* Only Ipv4 NAT need KeepAlive Packet to refresh iptable */ ++ if (eth_type == ETH_P_IP) { ++ iph = (struct iphdr *)(skb->data + vlan1_gap + vlan2_gap + pppoe_gap); ++ /* Recover to original layer 4 header */ ++ if (iph->protocol == IPPROTO_TCP) { ++ th = (struct tcphdr *)((uint8_t *)iph + iph->ihl * 4); ++ MDrv_HWNAT_Util_Calc_Tcphdr(entry, iph, th); ++ } ++ else if (iph->protocol == IPPROTO_UDP) { ++ uh = (struct udphdr *)((uint8_t *)iph + iph->ihl * 4); ++ MDrv_HWNAT_Util_Calc_Udphdr(entry, iph, uh); ++ } ++ /* Recover to original layer 3 header */ ++ MDrv_HWNAT_Util_Calc_Iphdr(entry, iph); ++ skb->pkt_type = PACKET_HOST; ++ } ++ else if (eth_type == ETH_P_IPV6) { ++ skb->pkt_type = PACKET_HOST; ++ } ++ else { ++ skb->pkt_type = PACKET_HOST; ++ } ++/* Ethernet driver will call eth_type_trans() to update skb->pkt_type.*/ ++/* If(destination mac != my mac)*/ ++/* skb->pkt_type=PACKET_OTHERHOST;*/ ++/* In order to pass ip_rcv() check, we change pkt_type to PACKET_HOST here*/ ++/* skb->pkt_type = PACKET_HOST;*/ ++ return 1; ++} ++ ++int _MDrv_HWNAT_Handle_Hitbind_Force_Cpu(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ u16 vir_if_idx = 0; ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ vir_if_idx = _MDrv_HWNAT_Remove_Vlan_Tag(skb); ++ if (vir_if_idx != 65535) { ++ if (vir_if_idx >= FOE_4TB_SIZ) { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("%s, entry_index error(%u)\n", __func__, vir_if_idx); ++ vir_if_idx = FOE_ENTRY_NUM(skb); ++ kfree_skb(skb); ++ return 0; ++ } ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, vir_if_idx); ++ } ++ } ++ if (IS_IPV4_HNAT(entry) || IS_IPV4_HNAPT(entry)) ++ skb->dev = dst_port[entry->ipv4_hnapt.act_dp]; ++ else if (IS_IPV4_DSLITE(entry)) ++ skb->dev = dst_port[entry->ipv4_dslite.act_dp]; ++ else if (IS_IPV6_3T_ROUTE(entry)) ++ skb->dev = dst_port[entry->ipv6_3t_route.act_dp]; ++ else if (IS_IPV6_5T_ROUTE(entry)) ++ skb->dev = dst_port[entry->ipv6_5t_route.act_dp]; ++ else if (IS_IPV6_6RD(entry)) ++ skb->dev = dst_port[entry->ipv6_6rd.act_dp]; ++ else ++ return 1; ++ /* interface is unknown */ ++ if (!skb->dev) { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("%s, interface is unknown\n", __func__); ++ kfree_skb(skb); ++ return 0; ++ } ++ skb_set_network_header(skb, 0); ++ skb_push(skb, ETH_HLEN); /* pointer to layer2 header */ ++ dev_queue_xmit(skb); ++ return 0; ++} ++ ++int _MDrv_HWNAT_Handle_Hitbind_Force_Mcast_To_Wifi(struct sk_buff *skb) ++{ ++ int i = 0; ++ struct sk_buff *skb2; ++ ++ if (((_hwnat_info.features & HW_NAT_WIFI) == 0) && ((_hwnat_info.features & HW_NAT_NIC_USB) == 0)) { ++ kfree_skb(skb); ++ return 0; ++ } ++ ++ if ((_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) == 0) { ++ /*if we only use GMAC1, we need to use vlan id to identify LAN/WAN port*/ ++ /*otherwise, CPU send untag packet to switch so we don't need to*/ ++ /*remove vlan tag before sending to WiFi interface*/ ++ _MDrv_HWNAT_Remove_Vlan_Tag(skb); /* pointer to layer3 header */ ++ } ++ skb_set_network_header(skb, 0); ++ skb_push(skb, ETH_HLEN); /* pointer to layer2 header */ ++ ++ if (_hwnat_info.features & HW_NAT_WIFI) { ++ for (i = DP_RA0; i < MAX_WIFI_IF_NUM; i++) { ++ if (dst_port[i]) { ++ skb2 = skb_clone(skb, GFP_ATOMIC); ++ ++ if (!skb2) ++ return -ENOMEM; ++ ++ skb2->dev = dst_port[i]; ++ dev_queue_xmit(skb2); ++ } ++ } ++ } ++ ++ if (_hwnat_info.features & HW_NAT_NIC_USB) { ++ if (dst_port[DP_PCI]) { ++ skb2 = skb_clone(skb, GFP_ATOMIC); ++ ++ if (!skb2) ++ return -ENOMEM; ++ ++ skb2->dev = dst_port[DP_PCI]; ++ dev_queue_xmit(skb2); ++ } ++ } ++ kfree_skb(skb); ++ ++ return 0; ++} ++ ++int32_t MDrv_HWNAT_Handle_Rx(struct sk_buff *skb) ++{ ++ struct foe_entry *entry = FOE_ENTRY_BASE_BY_PKT(_hwnat_info.ppe_foe_base, skb); ++ struct vlan_ethhdr *veth; ++ if (_hwnat_info.debug_level >= 7) ++ MDrv_HWNAT_Dump_Skb(skb); ++ ++ ++#if PPTP_L2TP ++ /*FP to-lan on/off*/ ++ if (_hwnat_info.features & PPTP_L2TP) { ++ if (pptp_fast_path && (skb->len != (124 - 14))) { ++ int ret = 1000; ++ /*remove pptp/l2tp header, tx to PPE */ ++ ret = MDrv_HWNAT_Pptp_Lan(skb); ++ /*ret 0, remove header ok */ ++ if (ret == 0) ++ return ret; ++ } ++ if (l2tp_fast_path && (skb->len != (124 - 14))) { ++ int ret = 1000; ++ /*remove pptp/l2tp header, tx to PPE */ ++ ret = MDrv_HWNAT_L2tp_Lan(skb); ++ if (ret == 0) ++ return ret; ++ } ++ } ++#endif ++ if (_hwnat_info.debug_level >= 7) ++ NAT_PRINT("[%s][%d] FOE_SP(skb) = %d \n",__FUNCTION__,__LINE__, FOE_SP(skb)); ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ /* QDMA QoS remove CPU reason, we use special tag to identify force to CPU ++ * Notes: CPU reason & Entry ID fileds are invalid at this moment ++ */ ++ if (FOE_SP(skb) == 5) { ++ veth = (struct vlan_ethhdr *)skb_mac_header(skb); ++ ++ if (veth->h_vlan_proto == 0x5678) { ++ if (_hwnat_info.features & PPTP_L2TP) { ++ u16 vir_if_idx = 0; ++ vir_if_idx = _MDrv_HWNAT_Remove_Vlan_Tag(skb); ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, vir_if_idx); ++ } ++ else { ++ return _MDrv_HWNAT_Handle_Hitbind_Force_Cpu(skb, entry); ++ } ++ } ++ } ++ } ++ /* the incoming packet is from PCI or WiFi interface */ ++ if (((FOE_MAGIC_TAG(skb) == FOE_MAGIC_PCI) || (FOE_MAGIC_TAG(skb) == FOE_MAGIC_WLAN))) { ++ return _MDrv_HWNAT_Handle_Extif_Rx(skb); ++ } ++ else if (FOE_AI(skb) == HIT_BIND_FORCE_TO_CPU) { ++ if (_hwnat_info.features & PPTP_L2TP) { ++ if (pptp_fast_path) { ++ /*to ppp0, add pptp/l2tp header and send out */ ++ int ret = 1000; ++ /* NAT_PRINT("PPTP LAN->WAN get bind packet!!\n"); */ ++ ret = MDrv_HWNAT_Pptp_Wan(skb); ++ return ret; ++ } ++ else if (l2tp_fast_path) { ++ /*to ppp0, add pptp/l2tp header and send out */ ++ int ret = 1000; ++ ++ ret = MDrv_HWNAT_L2tp_Wan(skb); ++ /* NAT_PRINT("L2TP LAN->WAN fast send bind packet and return %d!!\n", ret); */ ++ return ret; ++ } ++ } ++ return _MDrv_HWNAT_Handle_Hitbind_Force_Cpu(skb, entry); ++ ++ /* handle the incoming packet which came back from PPE */ ++ } ++ else if ((IS_IF_PCIE_WLAN_RX(skb) && ((FOE_SP(skb) == 0) || (FOE_SP(skb) == 5))) && ++ (FOE_AI(skb) != HIT_BIND_KEEPALIVE_UC_OLD_HDR) && ++ (FOE_AI(skb) != HIT_BIND_KEEPALIVE_MC_NEW_HDR) && ++ (FOE_AI(skb) != HIT_BIND_KEEPALIVE_DUP_OLD_HDR)) { ++ if (_hwnat_info.features & PPTP_L2TP) { ++ if (_MDrv_HWNAT_Handle_Pptp_L2tp_Pingpong(skb, entry) == 0) { ++ return 0; ++ } ++ } ++ return _MDrv_HWNAT_Handle_Extif_Pingpong(skb); ++ } ++ else if (FOE_AI(skb) == HIT_BIND_KEEPALIVE_UC_OLD_HDR) { ++ if (_hwnat_info.debug_level >= 3) ++ NAT_PRINT("Got HIT_BIND_KEEPALIVE_UC_OLD_HDR packet (hash index=%d)\n", FOE_ENTRY_NUM(skb)); ++ if (_hwnat_info.features & PPTP_L2TP) { ++ if (pptp_fast_path) { ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ } ++ return 1; ++ } ++ else if (FOE_AI(skb) == HIT_BIND_MULTICAST_TO_CPU || FOE_AI(skb) == HIT_BIND_MULTICAST_TO_GMAC_CPU) { ++ return _MDrv_HWNAT_Handle_Hitbind_Force_Mcast_To_Wifi(skb); ++ } ++ else if (FOE_AI(skb) == HIT_BIND_KEEPALIVE_MC_NEW_HDR) { ++ if (_hwnat_info.debug_level >= 3) { ++ NAT_PRINT("Got HIT_BIND_KEEPALIVE_MC_NEW_HDR packet (hash index=%d)\n", FOE_ENTRY_NUM(skb)); ++ } ++ ++ if (_MDrv_HWNAT_Handle_Keep_Alive(skb, entry)) { ++ return 1; ++ } ++ } else if (FOE_AI(skb) == HIT_BIND_KEEPALIVE_DUP_OLD_HDR) { ++ if (_hwnat_info.debug_level >= 3) ++ NAT_PRINT("RxGot HIT_BIND_KEEPALIVE_DUP_OLD_HDR packe (hash index=%d)\n", FOE_ENTRY_NUM(skb)); ++ if (_hwnat_info.features & PPTP_L2TP) { ++ if (pptp_fast_path) { ++ dev_kfree_skb_any(skb); ++ return 0; ++ } ++ } ++ return 1; ++ } ++ return 1; ++} ++ ++int32_t _MDrv_HWNAT_Get_Pppoe_Sid(struct sk_buff *skb, uint32_t vlan_gap, u16 *sid, uint16_t *ppp_tag) ++{ ++ struct pppoe_hdr *peh = NULL; ++ ++ peh = (struct pppoe_hdr *)(skb->data + ETH_HLEN + vlan_gap); ++ ++ if (_hwnat_info.debug_level >= 6) { ++ NAT_PRINT("\n==============\n"); ++ NAT_PRINT(" Ver=%d\n", peh->ver); ++ NAT_PRINT(" Type=%d\n", peh->type); ++ NAT_PRINT(" Code=%d\n", peh->code); ++ NAT_PRINT(" sid=%x\n", ntohs(peh->sid)); ++ NAT_PRINT(" Len=%d\n", ntohs(peh->length)); ++ NAT_PRINT(" tag_type=%x\n", ntohs(peh->tag[0].tag_type)); ++ NAT_PRINT(" tag_len=%d\n", ntohs(peh->tag[0].tag_len)); ++ NAT_PRINT("=================\n"); ++ } ++ ++ *ppp_tag = peh->tag[0].tag_type; ++ if (_hwnat_info.features & NAT_IPV6) { ++ if (peh->ver != 1 || peh->type != 1 || (*ppp_tag != htons(PPP_IP) && *ppp_tag != htons(PPP_IPV6))) { ++ return 1; ++ } ++ } ++ else { ++ if (peh->ver != 1 || peh->type != 1 || *ppp_tag != htons(PPP_IP)) ++ return 1; ++ } ++ ++ *sid = peh->sid; ++ return 0; ++} ++ ++/* HNAT_V2 can push special tag */ ++int32_t _MDrv_HWNAT_Is_Special_Tag(uint16_t eth_type) ++{ ++ /* Please modify this function to speed up the packet with special tag ++ * Ex: ++ * Ralink switch = 0x81xx ++ * Realtek switch = 0x8899 ++ */ ++ if ((eth_type & 0x00FF) == htons(ETH_P_8021Q)) { /* Ralink Special Tag: 0x81xx */ ++ ppe_parse_result.vlan_tag = eth_type; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++int32_t _MDrv_HWNAT_Is_802_1q(uint16_t eth_type) ++{ ++ if (eth_type == htons(ETH_P_8021Q)) { ++ ppe_parse_result.vlan_tag = eth_type; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++int32_t _MDrv_HWNAT_Is_Hw_Vlan_Tx(struct sk_buff *skb) ++{ ++ if (_hwnat_info.features & HW_NAT_VLAN_TX) { ++ if (hwnat_vlan_tx_tag_present(skb)) { ++ ppe_parse_result.vlan_tag = htons(ETH_P_8021Q); ++ return 1; ++ } else { ++ return 0; ++ } ++ } ++ return 0; ++} ++ ++int32_t _MDrv_HWNAT_Parse_Pkt_Layer(struct sk_buff *skb) ++{ ++ struct vlan_hdr *vh = NULL; ++ struct ethhdr *eth = NULL; ++ struct iphdr *iph = NULL; ++ struct ipv6hdr *ip6h = NULL; ++ struct tcphdr *th = NULL; ++ struct udphdr *uh = NULL; ++ u8 ipv6_head_len = 0; ++ struct vlan_hdr pseudo_vhdr; ++ ++ memset(&ppe_parse_result, 0, sizeof(ppe_parse_result)); ++ ++ eth = (struct ethhdr *)skb->data; ++ MDrv_HWNAT_Util_Memcpy(ppe_parse_result.dmac, eth->h_dest, ETH_ALEN); ++ MDrv_HWNAT_Util_Memcpy(ppe_parse_result.smac, eth->h_source, ETH_ALEN); ++ ppe_parse_result.eth_type = eth->h_proto; ++/* we cannot speed up multicase packets because both wire and wireless PCs might join same multicast group. */ ++ if (is_multicast_ether_addr(ð->h_dest[0])) ++ ppe_parse_result.is_mcast = 1; ++ else ++ ppe_parse_result.is_mcast = 0; ++ if (_MDrv_HWNAT_Is_802_1q(ppe_parse_result.eth_type) || ++ _MDrv_HWNAT_Is_Special_Tag(ppe_parse_result.eth_type) || _MDrv_HWNAT_Is_Hw_Vlan_Tx(skb)) { ++ if (_hwnat_info.features & HW_NAT_VLAN_TX) { ++ ppe_parse_result.vlan1_gap = 0; ++ ppe_parse_result.vlan_layer++; ++ pseudo_vhdr.h_vlan_TCI = htons(hwnat_vlan_tag_get(skb)); ++ pseudo_vhdr.h_vlan_encapsulated_proto = eth->h_proto; ++ vh = (struct vlan_hdr *)&pseudo_vhdr; ++ } ++ else { ++ ppe_parse_result.vlan1_gap = VLAN_HLEN; ++ ppe_parse_result.vlan_layer++; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ } ++ ppe_parse_result.vlan1 = vh->h_vlan_TCI; ++ /* VLAN + PPPoE */ ++ if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_PPP_SES) { ++ ppe_parse_result.pppoe_gap = 8; ++ if (_MDrv_HWNAT_Get_Pppoe_Sid(skb, ppe_parse_result.vlan1_gap, ++ &ppe_parse_result.pppoe_sid, ++ &ppe_parse_result.ppp_tag)) { ++ return 1; ++ } ++ ppe_parse_result.eth_type = vh->h_vlan_encapsulated_proto; ++ /* Double VLAN = VLAN + VLAN */ ++ } else if (_MDrv_HWNAT_Is_802_1q(vh->h_vlan_encapsulated_proto) || ++ _MDrv_HWNAT_Is_Special_Tag(vh->h_vlan_encapsulated_proto)) { ++ ppe_parse_result.vlan2_gap = VLAN_HLEN; ++ ppe_parse_result.vlan_layer++; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN + ppe_parse_result.vlan1_gap); ++ ppe_parse_result.vlan2 = vh->h_vlan_TCI; ++ ++ /* VLAN + VLAN + PPPoE */ ++ if (ntohs(vh->h_vlan_encapsulated_proto) == ETH_P_PPP_SES) { ++ ppe_parse_result.pppoe_gap = 8; ++ if (_MDrv_HWNAT_Get_Pppoe_Sid ++ (skb, ++ (ppe_parse_result.vlan1_gap + ppe_parse_result.vlan2_gap), ++ &ppe_parse_result.pppoe_sid, &ppe_parse_result.ppp_tag)) { ++ return 1; ++ } ++ ppe_parse_result.eth_type = vh->h_vlan_encapsulated_proto; ++ } else if (_MDrv_HWNAT_Is_802_1q(vh->h_vlan_encapsulated_proto)) { ++ /* VLAN + VLAN + VLAN */ ++ ppe_parse_result.vlan_layer++; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN + ++ ppe_parse_result.vlan1_gap + VLAN_HLEN); ++ ++ /* VLAN + VLAN + VLAN */ ++ if (_MDrv_HWNAT_Is_802_1q(vh->h_vlan_encapsulated_proto)) ++ ppe_parse_result.vlan_layer++; ++ } else { ++ /* VLAN + VLAN + IP */ ++ ppe_parse_result.eth_type = vh->h_vlan_encapsulated_proto; ++ } ++ } else { ++ /* VLAN + IP */ ++ ppe_parse_result.eth_type = vh->h_vlan_encapsulated_proto; ++ } ++ } else if (ntohs(ppe_parse_result.eth_type) == ETH_P_PPP_SES) { ++ /* PPPoE + IP */ ++ ppe_parse_result.pppoe_gap = 8; ++ if (_MDrv_HWNAT_Get_Pppoe_Sid(skb, ppe_parse_result.vlan1_gap, ++ &ppe_parse_result.pppoe_sid, ++ &ppe_parse_result.ppp_tag)) { ++ return 1; ++ } ++ } ++ /* set layer2 start addr */ ++ ++ skb_set_mac_header(skb, 0); ++ ++ /* set layer3 start addr */ ++ skb_set_network_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ppe_parse_result.pppoe_gap); ++ ++ /* set layer4 start addr */ ++ if ((ppe_parse_result.eth_type == htons(ETH_P_IP)) || ++ (ppe_parse_result.eth_type == htons(ETH_P_PPP_SES) && ++ (ppe_parse_result.ppp_tag == htons(PPP_IP)))) { ++ iph = (struct iphdr *)skb_network_header(skb); ++ memcpy(&ppe_parse_result.iph, iph, sizeof(struct iphdr)); ++ ++ if (iph->protocol == IPPROTO_TCP) { ++ skb_set_transport_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ++ ppe_parse_result.pppoe_gap + (iph->ihl * 4)); ++ th = (struct tcphdr *)skb_transport_header(skb); ++ ++ memcpy(&ppe_parse_result.th, th, sizeof(struct tcphdr)); ++ ppe_parse_result.pkt_type = IPV4_HNAPT; ++ if (iph->frag_off & htons(IP_MF | IP_OFFSET)) ++ return 1; ++ } ++ else if (iph->protocol == IPPROTO_UDP) { ++ skb_set_transport_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ++ ppe_parse_result.pppoe_gap + (iph->ihl * 4)); ++ uh = (struct udphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_result.uh, uh, sizeof(struct udphdr)); ++ ppe_parse_result.pkt_type = IPV4_HNAPT; ++ if (iph->frag_off & htons(IP_MF | IP_OFFSET)) ++ { ++ if (USE_3T_UDP_FRAG == 0) ++ return 1; ++ } ++ } ++ else if (iph->protocol == IPPROTO_GRE) { ++ if ((_hwnat_info.features & PPTP_L2TP) == 0) { ++ /* do nothing */ ++ return 1; ++ } ++ } ++ else if (iph->protocol == IPPROTO_IPV6) { ++ ip6h = (struct ipv6hdr *)((uint8_t *)iph + iph->ihl * 4); ++ memcpy(&ppe_parse_result.ip6h, ip6h, sizeof(struct ipv6hdr)); ++ ++ if (ip6h->nexthdr == NEXTHDR_TCP) { ++ skb_set_transport_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ++ ppe_parse_result.pppoe_gap + ++ (sizeof(struct ipv6hdr))); ++ ++ th = (struct tcphdr *)skb_transport_header(skb); ++ ++ memcpy(&ppe_parse_result.th.source, &th->source, sizeof(th->source)); ++ memcpy(&ppe_parse_result.th.dest, &th->dest, sizeof(th->dest)); ++ } ++ else if (ip6h->nexthdr == NEXTHDR_UDP) { ++ skb_set_transport_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ++ ppe_parse_result.pppoe_gap + ++ (sizeof(struct ipv6hdr))); ++ ++ uh = (struct udphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_result.uh.source, &uh->source, sizeof(uh->source)); ++ memcpy(&ppe_parse_result.uh.dest, &uh->dest, sizeof(uh->dest)); ++ } ++ ppe_parse_result.pkt_type = IPV6_6RD; ++ } ++ else { ++ /* Packet format is not supported */ ++ return 1; ++ } ++ ++ } ++ else if (ppe_parse_result.eth_type == htons(ETH_P_IPV6) || ++ (ppe_parse_result.eth_type == htons(ETH_P_PPP_SES) && ++ ppe_parse_result.ppp_tag == htons(PPP_IPV6))) { ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++ memcpy(&ppe_parse_result.ip6h, ip6h, sizeof(struct ipv6hdr)); ++ ++ if (ip6h->nexthdr == NEXTHDR_TCP) { ++ skb_set_transport_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ++ ppe_parse_result.pppoe_gap + ++ (sizeof(struct ipv6hdr))); ++ ++ th = (struct tcphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_result.th, th, sizeof(struct tcphdr)); ++ ppe_parse_result.pkt_type = IPV6_5T_ROUTE; ++ } ++ else if (ip6h->nexthdr == NEXTHDR_UDP) { ++ skb_set_transport_header(skb, ETH_HLEN + ppe_parse_result.vlan1_gap + ++ ppe_parse_result.vlan2_gap + ++ ppe_parse_result.pppoe_gap + ++ (sizeof(struct ipv6hdr))); ++ uh = (struct udphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_result.uh, uh, sizeof(struct udphdr)); ++ ppe_parse_result.pkt_type = IPV6_5T_ROUTE; ++ } ++ else if (ip6h->nexthdr == NEXTHDR_IPIP) { ++ ipv6_head_len = sizeof(struct iphdr); ++ memcpy(&ppe_parse_result.iph, ip6h + ipv6_head_len, sizeof(struct iphdr)); ++ ppe_parse_result.pkt_type = IPV4_DSLITE; ++ } ++ else { ++ ppe_parse_result.pkt_type = IPV6_3T_ROUTE; ++ } ++ ++ } ++ else { ++ return 1; ++ } ++ ++ if (_hwnat_info.debug_level >= 6) { ++ NAT_PRINT("--------------\n"); ++ NAT_PRINT("DMAC:%02X:%02X:%02X:%02X:%02X:%02X\n", ++ ppe_parse_result.dmac[0], ppe_parse_result.dmac[1], ++ ppe_parse_result.dmac[2], ppe_parse_result.dmac[3], ++ ppe_parse_result.dmac[4], ppe_parse_result.dmac[5]); ++ NAT_PRINT("SMAC:%02X:%02X:%02X:%02X:%02X:%02X\n", ++ ppe_parse_result.smac[0], ppe_parse_result.smac[1], ++ ppe_parse_result.smac[2], ppe_parse_result.smac[3], ++ ppe_parse_result.smac[4], ppe_parse_result.smac[5]); ++ NAT_PRINT("Eth_Type=%x\n", ppe_parse_result.eth_type); ++ if (ppe_parse_result.vlan1_gap > 0) ++ NAT_PRINT("VLAN1 ID=%x\n", ntohs(ppe_parse_result.vlan1)); ++ ++ if (ppe_parse_result.vlan2_gap > 0) ++ NAT_PRINT("VLAN2 ID=%x\n", ntohs(ppe_parse_result.vlan2)); ++ ++ if (ppe_parse_result.pppoe_gap > 0) { ++ NAT_PRINT("PPPOE Session ID=%x\n", ppe_parse_result.pppoe_sid); ++ NAT_PRINT("PPP Tag=%x\n", ntohs(ppe_parse_result.ppp_tag)); ++ } ++ NAT_PRINT("PKT_TYPE=%s\n", ++ ppe_parse_result.pkt_type == ++ 0 ? "IPV4_HNAT" : ppe_parse_result.pkt_type == ++ 1 ? "IPV4_HNAPT" : ppe_parse_result.pkt_type == ++ 3 ? "IPV4_DSLITE" : ppe_parse_result.pkt_type == ++ 5 ? "IPV6_ROUTE" : ppe_parse_result.pkt_type == 7 ? "IPV6_6RD" : "Unknown"); ++ if (ppe_parse_result.pkt_type == IPV4_HNAT) { ++ NAT_PRINT("SIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(ntohl(ppe_parse_result.iph.saddr))); ++ NAT_PRINT("DIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(ntohl(ppe_parse_result.iph.daddr))); ++ NAT_PRINT("TOS=%x\n", ntohs(ppe_parse_result.iph.tos)); ++ } else if (ppe_parse_result.pkt_type == IPV4_HNAPT) { ++ NAT_PRINT("SIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(ntohl(ppe_parse_result.iph.saddr))); ++ NAT_PRINT("DIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(ntohl(ppe_parse_result.iph.daddr))); ++ NAT_PRINT("TOS=%x\n", ntohs(ppe_parse_result.iph.tos)); ++ ++ if (ppe_parse_result.iph.protocol == IPPROTO_TCP) { ++ NAT_PRINT("TCP SPORT=%d, %d\n", ntohs(ppe_parse_result.th.source), ntohs(th->source)); ++ NAT_PRINT("TCP DPORT=%d, %d\n", ntohs(ppe_parse_result.th.dest), ntohs(th->dest)); ++ } else if (ppe_parse_result.iph.protocol == IPPROTO_UDP) { ++ NAT_PRINT("UDP SPORT=%d, %d\n", ntohs(ppe_parse_result.uh.source), ntohs(uh->source)); ++ NAT_PRINT("UDP DPORT=%d, %d\n", ntohs(ppe_parse_result.uh.dest), ntohs(uh->dest)); ++ } ++ } else if (ppe_parse_result.pkt_type == IPV6_5T_ROUTE) { ++ NAT_PRINT("ING SIPv6->DIPv6: %08X:%08X:%08X:%08X:%d-> %08X:%08X:%08X:%08X:%d\n", ++ ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[0]), ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[1]), ++ ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[2]), ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[3]), ++ ntohs(ppe_parse_result.th.source), ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[0]), ++ ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[1]), ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[2]), ++ ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[3]), ntohs(ppe_parse_result.th.dest)); ++ } else if (ppe_parse_result.pkt_type == IPV6_6RD) { ++ /* fill in ipv4 6rd entry */ ++ NAT_PRINT("packet_type = IPV6_6RD\n"); ++ NAT_PRINT("SIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(ntohl(ppe_parse_result.iph.saddr))); ++ NAT_PRINT("DIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(ntohl(ppe_parse_result.iph.daddr))); ++ ++ NAT_PRINT("Checksum=%x\n", ntohs(ppe_parse_result.iph.check)); ++ NAT_PRINT("ipV4 ID =%x\n", ntohs(ppe_parse_result.iph.id)); ++ NAT_PRINT("Flag=%x\n", ntohs(ppe_parse_result.iph.frag_off) >> 13); ++ NAT_PRINT("TTL=%x\n", ppe_parse_result.iph.ttl); ++ NAT_PRINT("TOS=%x\n", ppe_parse_result.iph.tos); ++ } ++ } ++ ++ return 0; ++} ++ ++static int32_t _MDrv_HWNAT_Fill_L2(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ /* if this entry is already in binding state, skip it */ ++ if (entry->bfib1.state == BIND) { ++ return 1; ++ } ++ ++ /* Set VLAN Info - VLAN1/VLAN2 */ ++ /* Set Layer2 Info - DMAC, SMAC */ ++ if ((ppe_parse_result.pkt_type == IPV4_HNAT) || (ppe_parse_result.pkt_type == IPV4_HNAPT)) { ++ if (entry->ipv4_hnapt.bfib1.pkt_type == IPV4_DSLITE) { /* DS-Lite WAN->LAN */ ++ if (_hwnat_info.features & NAT_IPV6) { ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv4_dslite.dmac_hi, ppe_parse_result.dmac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv4_dslite.dmac_lo, ppe_parse_result.dmac); ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv4_dslite.smac_hi, ppe_parse_result.smac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv4_dslite.smac_lo, ppe_parse_result.smac); ++ entry->ipv4_dslite.vlan1 = ntohs(ppe_parse_result.vlan1); ++ entry->ipv4_dslite.pppoe_id = ntohs(ppe_parse_result.pppoe_sid); ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) ++ entry->ipv4_dslite.vlan2_winfo = ntohs(ppe_parse_result.vlan2); ++ else ++ entry->ipv4_dslite.vlan2 = ntohs(ppe_parse_result.vlan2); ++ entry->ipv4_dslite.etype = ntohs(ppe_parse_result.vlan_tag); ++ } ++ else { ++ return 1; ++ } ++ } ++ else { /* IPv4 WAN<->LAN */ ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv4_hnapt.dmac_hi, ppe_parse_result.dmac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv4_hnapt.dmac_lo, ppe_parse_result.dmac); ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv4_hnapt.smac_hi, ppe_parse_result.smac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv4_hnapt.smac_lo, ppe_parse_result.smac); ++ entry->ipv4_hnapt.vlan1 = ntohs(ppe_parse_result.vlan1); ++ entry->ipv4_hnapt.pppoe_id = ntohs(ppe_parse_result.pppoe_sid); ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) ++ entry->ipv4_dslite.vlan2_winfo = ntohs(ppe_parse_result.vlan2); ++ else ++ entry->ipv4_hnapt.vlan2 = ntohs(ppe_parse_result.vlan2); ++ entry->ipv4_hnapt.etype = ntohs(ppe_parse_result.vlan_tag); ++ } ++ } ++ else { ++ if (_hwnat_info.features & NAT_IPV6) { ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv6_5t_route.dmac_hi, ppe_parse_result.dmac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv6_5t_route.dmac_lo, ppe_parse_result.dmac); ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv6_5t_route.smac_hi, ppe_parse_result.smac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv6_5t_route.smac_lo, ppe_parse_result.smac); ++ entry->ipv6_5t_route.vlan1 = ntohs(ppe_parse_result.vlan1); ++ entry->ipv6_5t_route.pppoe_id = ntohs(ppe_parse_result.pppoe_sid); ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) ++ entry->ipv4_dslite.vlan2_winfo = ntohs(ppe_parse_result.vlan2); ++ else ++ entry->ipv6_5t_route.vlan2 = ntohs(ppe_parse_result.vlan2); ++ entry->ipv6_5t_route.etype = ntohs(ppe_parse_result.vlan_tag); ++ } ++ else { ++ return 1; ++ } ++ } ++ ++/* VLAN Layer:*/ ++/* 0: outgoing packet is untagged packet*/ ++/* 1: outgoing packet is tagged packet*/ ++/* 2: outgoing packet is double tagged packet*/ ++/* 3: outgoing packet is triple tagged packet*/ ++/* 4: outgoing packet is fourfold tagged packet*/ ++ entry->bfib1.vlan_layer = ppe_parse_result.vlan_layer; ++ ++ if (ppe_parse_result.pppoe_gap) ++ entry->bfib1.psn = 1; ++ else ++ entry->bfib1.psn = 0; ++ entry->ipv4_hnapt.bfib1.vpm = 1; /* 0x8100 */ ++ return 0; ++} ++ ++static uint16_t _MDrv_HWNAT_Get_Chkbase(struct iphdr *iph) ++{ ++ u16 org_chksum = ntohs(iph->check); ++ u16 org_tot_len = ntohs(iph->tot_len); ++ u16 org_id = ntohs(iph->id); ++ u16 chksum_tmp, tot_len_tmp, id_tmp; ++ u32 tmp = 0; ++ u16 chksum_base = 0; ++ ++ chksum_tmp = ~(org_chksum); ++ tot_len_tmp = ~(org_tot_len); ++ id_tmp = ~(org_id); ++ tmp = chksum_tmp + tot_len_tmp + id_tmp; ++ tmp = ((tmp >> 16) & 0x7) + (tmp & 0xFFFF); ++ tmp = ((tmp >> 16) & 0x7) + (tmp & 0xFFFF); ++ chksum_base = tmp & 0xFFFF; ++ ++ return chksum_base; ++} ++ ++static int32_t _MDrv_HWNAT_Fill_L3(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ /* IPv4 or IPv4 over PPPoE */ ++ if ((ppe_parse_result.eth_type == htons(ETH_P_IP)) || ++ (ppe_parse_result.eth_type == htons(ETH_P_PPP_SES) && ++ ppe_parse_result.ppp_tag == htons(PPP_IP))) { ++ if ((ppe_parse_result.pkt_type == IPV4_HNAT) || ++ (ppe_parse_result.pkt_type == IPV4_HNAPT)) { ++ if (entry->ipv4_hnapt.bfib1.pkt_type == IPV4_DSLITE) { /* DS-Lite WAN->LAN */ ++ if (_hwnat_info.features & NAT_IPV6) { ++ if (_hwnat_info.features & PPE_MIB) { ++ entry->ipv4_dslite.iblk2.mibf = 1; ++ } ++ entry->ipv4_dslite.bfib1.rmt = 1; /* remove outer IPv6 header */ ++ entry->ipv4_dslite.iblk2.dscp = ppe_parse_result.iph.tos; ++ } ++ ++ } else { ++ ++ entry->ipv4_hnapt.new_sip = ntohl(ppe_parse_result.iph.saddr); ++ entry->ipv4_hnapt.new_dip = ntohl(ppe_parse_result.iph.daddr); ++ entry->ipv4_hnapt.iblk2.dscp = ppe_parse_result.iph.tos; ++ if (_hwnat_info.features & PPE_MIB) { ++ entry->ipv4_dslite.iblk2.mibf = 1; ++ } ++ } ++ } ++ else if (ppe_parse_result.pkt_type == IPV6_6RD) { ++ /* fill in ipv4 6rd entry */ ++ entry->ipv6_6rd.tunnel_sipv4 = ntohl(ppe_parse_result.iph.saddr); ++ entry->ipv6_6rd.tunnel_dipv4 = ntohl(ppe_parse_result.iph.daddr); ++ entry->ipv6_6rd.hdr_chksum = _MDrv_HWNAT_Get_Chkbase(&ppe_parse_result.iph); ++ entry->ipv6_6rd.flag = (ntohs(ppe_parse_result.iph.frag_off) >> 13); ++ entry->ipv6_6rd.ttl = ppe_parse_result.iph.ttl; ++ entry->ipv6_6rd.dscp = ppe_parse_result.iph.tos; ++ if (_hwnat_info.features & PPE_MIB) { ++ entry->ipv4_dslite.iblk2.mibf = 1; ++ } ++ MHal_HWNAT_Set_Hash_Seed(ntohs(ppe_parse_result.iph.id)); ++ entry->ipv6_6rd.per_flow_6rd_id = 1; ++ /* IPv4 DS-Lite and IPv6 6RD shall be turn on by SW during initialization */ ++ entry->bfib1.pkt_type = IPV6_6RD; ++ } ++ } ++ /* IPv6 or IPv6 over PPPoE */ ++ else if ((_hwnat_info.features & NAT_IPV6) && (ppe_parse_result.eth_type == htons(ETH_P_IPV6) || ++ (ppe_parse_result.eth_type == htons(ETH_P_PPP_SES) && ++ ppe_parse_result.ppp_tag == htons(PPP_IPV6)))) { ++ if (ppe_parse_result.pkt_type == IPV6_3T_ROUTE || ++ ppe_parse_result.pkt_type == IPV6_5T_ROUTE) { ++ /* incoming packet is 6RD and need to remove outer IPv4 header */ ++ if (entry->bfib1.pkt_type == IPV6_6RD) { ++ entry->ipv6_3t_route.bfib1.rmt = 1; ++ entry->ipv6_3t_route.iblk2.dscp = (ppe_parse_result.ip6h.priority << 4 | (ppe_parse_result.ip6h.flow_lbl[0] >> 4)); ++ if (_hwnat_info.features & PPE_MIB) { ++ entry->ipv4_dslite.iblk2.mibf = 1; ++ } ++ ++ } else { ++ /* fill in ipv6 routing entry */ ++ entry->ipv6_3t_route.ipv6_sip0 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[0]); ++ entry->ipv6_3t_route.ipv6_sip1 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[1]); ++ entry->ipv6_3t_route.ipv6_sip2 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[2]); ++ entry->ipv6_3t_route.ipv6_sip3 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[3]); ++ ++ entry->ipv6_3t_route.ipv6_dip0 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[0]); ++ entry->ipv6_3t_route.ipv6_dip1 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[1]); ++ entry->ipv6_3t_route.ipv6_dip2 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[2]); ++ entry->ipv6_3t_route.ipv6_dip3 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[3]); ++ entry->ipv6_3t_route.iblk2.dscp = (ppe_parse_result.ip6h.priority << 4 | (ppe_parse_result.ip6h.flow_lbl[0] >> 4)); ++ if (_hwnat_info.features & PPE_MIB) { ++ entry->ipv4_dslite.iblk2.mibf = 1; ++ } ++ } ++ ++ } else if (ppe_parse_result.pkt_type == IPV4_DSLITE) { ++ /* fill in DSLite entry */ ++ entry->ipv4_dslite.tunnel_sipv6_0 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[0]); ++ entry->ipv4_dslite.tunnel_sipv6_1 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[1]); ++ entry->ipv4_dslite.tunnel_sipv6_2 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[2]); ++ entry->ipv4_dslite.tunnel_sipv6_3 = ntohl(ppe_parse_result.ip6h.saddr.s6_addr32[3]); ++ ++ entry->ipv4_dslite.tunnel_dipv6_0 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[0]); ++ entry->ipv4_dslite.tunnel_dipv6_1 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[1]); ++ entry->ipv4_dslite.tunnel_dipv6_2 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[2]); ++ entry->ipv4_dslite.tunnel_dipv6_3 = ntohl(ppe_parse_result.ip6h.daddr.s6_addr32[3]); ++ if (_hwnat_info.features & PPE_MIB) { ++ entry->ipv4_dslite.iblk2.mibf = 1; ++ } ++ memcpy(entry->ipv4_dslite.flow_lbl, ppe_parse_result.ip6h.flow_lbl, sizeof(ppe_parse_result.ip6h.flow_lbl)); ++ entry->ipv4_dslite.priority = ppe_parse_result.ip6h.priority; ++ entry->ipv4_dslite.hop_limit = ppe_parse_result.ip6h.hop_limit; ++ /* IPv4 DS-Lite and IPv6 6RD shall be turn on by SW during initialization */ ++ entry->bfib1.pkt_type = IPV4_DSLITE; ++ }; ++ } ++ else ++ return 1; ++ ++ return 0; ++} ++ ++static int32_t _MDrv_HWNAT_Fill_L4(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ if (ppe_parse_result.pkt_type == IPV4_HNAPT) { ++ /* DS-LIte WAN->LAN */ ++ if (entry->ipv4_hnapt.bfib1.pkt_type == IPV4_DSLITE) ++ return 0; ++ /* Set Layer4 Info - NEW_SPORT, NEW_DPORT */ ++ if (ppe_parse_result.iph.protocol == IPPROTO_TCP) { ++ entry->ipv4_hnapt.new_sport = ntohs(ppe_parse_result.th.source); ++ entry->ipv4_hnapt.new_dport = ntohs(ppe_parse_result.th.dest); ++ entry->ipv4_hnapt.bfib1.udp = TCP; ++ } else if (ppe_parse_result.iph.protocol == IPPROTO_UDP) { ++ entry->ipv4_hnapt.new_sport = ntohs(ppe_parse_result.uh.source); ++ entry->ipv4_hnapt.new_dport = ntohs(ppe_parse_result.uh.dest); ++ entry->ipv4_hnapt.bfib1.udp = UDP; ++ ++ /* if UDP checksum is zero, it cannot be accelerated by HNAT */ ++ /* we found some protocols, such as IPSEC-NAT-T, are possible to hybrid ++ * udp zero checksum and non-zero checksum in the same session, ++ * so we disable HNAT acceleration for all UDP flows ++ */ ++ /* if(entry->ipv4_hnapt.new_sport==4500 && entry->ipv4_hnapt.new_dport==4500) */ ++ } ++ } ++ else if (ppe_parse_result.pkt_type == IPV4_HNAT) { ++ /* do nothing */ ++ } ++ else if (ppe_parse_result.pkt_type == IPV6_1T_ROUTE) { ++ /* do nothing */ ++ } ++ else if ((_hwnat_info.features & NAT_IPV6) && (ppe_parse_result.pkt_type == IPV6_3T_ROUTE)) { ++ /* do nothing */ ++ } ++ else if ((_hwnat_info.features & NAT_IPV6) && (ppe_parse_result.pkt_type == IPV6_5T_ROUTE)) { ++ /* do nothing */ ++ } ++ ++ return 0; ++} ++ ++static void _MDrv_HWNAT_Set_InfoBlock2(struct _info_blk2 *iblk2, uint32_t fpidx, uint32_t port_mg, uint32_t port_ag) ++{ ++ /* we need to lookup another multicast table if this is multicast flow */ ++ if (ppe_parse_result.is_mcast) { ++ iblk2->mcast = 1; ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (fpidx == 3) ++ fpidx = 0; /* multicast flow not go to WDMA */ ++ } ++ } ++ else { ++ iblk2->mcast = 0; ++ } ++ ++ /* 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */ ++ iblk2->dp = fpidx; ++ ++ if ((_hwnat_info.features & HW_NAT_QDMA) == 0) ++ iblk2->fqos = 0; /* PDMA MODE should not goes to QoS */ ++ ++ iblk2->acnt = port_ag; ++} ++ ++ ++ ++static void _MDrv_HWNAT_Set_Blk2_Qid(struct sk_buff *skb, struct foe_entry *entry, int gmac_no) ++{ ++ unsigned int qidx; ++ if (IS_IPV4_GRP(entry)) { ++ if (skb->mark > 63) ++ skb->mark = 0; ++ qidx = M2Q_table[skb->mark]; ++ entry->ipv4_hnapt.iblk2.qid1 = ((qidx & 0x30) >> 4); ++ entry->ipv4_hnapt.iblk2.qid = (qidx & 0x0f); ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ if (lan_wan_separate == 1 && gmac_no == 2) { ++ entry->ipv4_hnapt.iblk2.qid += 8; ++ if (_hwnat_info.features & HW_NAT_HW_SFQ) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) ++ entry->ipv4_hnapt.iblk2.qid = HWSFQUP; ++ } ++ } ++ if ((lan_wan_separate == 1) && (gmac_no == 1)) { ++ if (_hwnat_info.features & HW_NAT_HW_SFQ) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) ++ entry->ipv4_hnapt.iblk2.qid = HWSFQDL; ++ } ++ } ++ } ++ } ++ else if (IS_IPV6_GRP(entry)) { ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ if (skb->mark > 63) ++ skb->mark = 0; ++ qidx = M2Q_table[skb->mark]; ++ entry->ipv6_3t_route.iblk2.qid1 = ((qidx & 0x30) >> 4); ++ entry->ipv6_3t_route.iblk2.qid = (qidx & 0x0f); ++ if (lan_wan_separate == 1 && gmac_no == 2) { ++ entry->ipv6_3t_route.iblk2.qid += 8; ++ if (_hwnat_info.features & HW_NAT_HW_SFQ) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) ++ entry->ipv6_3t_route.iblk2.qid = HWSFQUP; ++ } ++ } ++ if ((lan_wan_separate == 1) && (gmac_no == 1)) { ++ if (_hwnat_info.features & HW_NAT_HW_SFQ) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) ++ entry->ipv6_3t_route.iblk2.qid = HWSFQDL; ++ } ++ } ++ } ++ } ++} ++ ++int32_t MDrv_HWNAT_Set_Force_Port(struct sk_buff *skb, struct foe_entry *entry, int gmac_no) ++{ ++ /* Set force port info */ ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ _MDrv_HWNAT_Set_Blk2_Qid(skb, entry, gmac_no); ++ } ++ ++ /* CPU need to handle traffic between WLAN/PCI and GMAC port */ ++ if ((strncmp(skb->dev->name, "eth", 3) != 0)) { ++ if (((_hwnat_info.features & HW_NAT_WIFI) == 0) && ++ ((_hwnat_info.features & HW_NAT_NIC_USB) == 0) && ++ ((_hwnat_info.features & PPTP_L2TP) == 0)) { ++ return 1; ++ } ++ ++ /*PPTP/L2TP LAN->WAN bind to CPU*/ ++ if (IS_IPV4_GRP(entry)) { ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ entry->ipv4_hnapt.bfib1.vpm = 0; /* etype remark */ ++ ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (gmac_no == 3) { ++ entry->ipv4_hnapt.iblk2.fqos = 0;/*wifi hw_nat not support QoS */ ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 3, 0x3F, 0x3F); /* 3=WDMA */ ++ } ++ else { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 0, 0x3F, 0x3F); /* 0=PDMA */ ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv4_hnapt.iblk2.fqos = 1; ++ else ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ } ++ } ++ else { ++ if (_hwnat_info.features & HW_NAT_QDMATX_QDMARX) ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 5, 0x3F, 0x3F); /* 5=QDMA */ ++ else ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 0, 0x3F, 0x3F); /* 0=PDMA */ ++ ++ if (FOE_SP(skb) == 5) /* wifi to wifi not go to pse port6 */ ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ else { ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv4_hnapt.iblk2.fqos = 1; ++ else ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (gmac_no == 3) { ++ entry->ipv4_hnapt.iblk2.wdmaid = (FOE_WDMA_ID(skb) & 0x01); ++ entry->ipv4_hnapt.iblk2.winfo = 1; ++ entry->ipv4_hnapt.vlan2_winfo = ++ ((FOE_RX_ID(skb) & 0x03) << 14) | ((FOE_WC_ID(skb) & 0xff) << 6) | ++ (FOE_BSS_ID(skb) & 0x3f); ++ }else { ++ if (ppe_parse_result.vlan1 == 0) { ++ entry->ipv4_hnapt.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv4_hnapt.etype = ntohs(0x5678); ++ entry->bfib1.vlan_layer = 1; ++ }else if (ppe_parse_result.vlan2 == 0) { ++ entry->ipv4_hnapt.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv4_hnapt.etype = ntohs(0x5678); ++ entry->ipv4_hnapt.vlan2_winfo = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 2; ++ } else { ++ entry->ipv4_hnapt.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv4_hnapt.etype = ntohs(0x5678); ++ entry->ipv4_hnapt.vlan2_winfo = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 3; ++ } ++ } ++ } ++ else { ++ if (ppe_parse_result.vlan1 == 0) { ++ entry->ipv4_hnapt.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv4_hnapt.etype = ntohs(0x5678); ++ entry->bfib1.vlan_layer = 1; ++ }else if (ppe_parse_result.vlan2 == 0) { ++ entry->ipv4_hnapt.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv4_hnapt.etype = ntohs(0x5678); ++ entry->ipv4_hnapt.vlan2 = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 2; ++ } else { ++ entry->ipv4_hnapt.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv4_hnapt.etype = ntohs(0x5678); ++ entry->ipv4_hnapt.vlan2 = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 3; ++ } ++ } ++ } ++ } ++ else { ++ if (gmac_no == 3) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 3, 0x3F, 0x3F); /* 3=WDMA */ ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ entry->ipv4_hnapt.iblk2.wdmaid = (FOE_WDMA_ID(skb) & 0x01); ++ entry->ipv4_hnapt.iblk2.winfo = 1; ++ entry->ipv4_hnapt.vlan2_winfo = ++ ((FOE_RX_ID(skb) & 0x03) << 14) | ((FOE_WC_ID(skb) & 0xff) << 6) | ++ (FOE_BSS_ID(skb) & 0x3f); ++ } ++ else { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 0, 0x3F, 0x3F); /* 0=CPU fastpath*/ ++ } ++ entry->ipv4_hnapt.iblk2.fqos = 0; /* PDMA MODE should not goes to QoS */ ++ } ++ } ++ else if (IS_IPV6_GRP(entry)) { ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ if (_hwnat_info.features & HW_NAT_QDMATX_QDMARX) { ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (gmac_no == 3) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 3, 0x3F, 0x3F); /* 3=WDMA */ ++ entry->ipv6_3t_route.iblk2.fqos = 0; /* wifi hw_nat not support qos */ ++ } ++ else ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 5, 0x3F, 0x3F);/* 0=CPU fastpath */ ++ } ++ else { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 5, 0x3F, 0x3F);/* 0=CPU fastpath */ ++ if (FOE_SP(skb) == 5) { ++ entry->ipv6_3t_route.iblk2.fqos = 0; /* wifi to wifi not go to pse port6 */ ++ } ++ else { ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv6_3t_route.iblk2.fqos = 1; ++ else ++ entry->ipv6_3t_route.iblk2.fqos = 0; ++ } ++ ++ } ++ ++ } ++ else { ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (gmac_no == 3) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 3, 0x3F, 0x3F);/* 3=WDMA */ ++ entry->ipv6_3t_route.iblk2.fqos = 0; /* wifi hw_nat not support qos */ ++ } ++ else { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 0, 0x3F, 0x3F); ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv6_3t_route.iblk2.fqos = 1; ++ else ++ entry->ipv6_3t_route.iblk2.fqos = 0; ++ ++ } ++ } ++ else { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 0, 0x3F, 0x3F); /* 0=PDMA */ ++ if (FOE_SP(skb) == 5) { ++ entry->ipv6_3t_route.iblk2.fqos = 0; /* wifi to wifi not go to pse port6 */ ++ } ++ else { ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv6_3t_route.iblk2.fqos = 1; ++ else ++ entry->ipv6_3t_route.iblk2.fqos = 0; ++ } ++ } ++ } ++ ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (gmac_no == 3) { ++ entry->ipv6_3t_route.iblk2.wdmaid = (FOE_WDMA_ID(skb) & 0x01); ++ entry->ipv6_3t_route.iblk2.winfo = 1; ++ entry->ipv6_3t_route.vlan2_winfo = ++ ((FOE_RX_ID(skb) & 0x03) << 14) | ((FOE_WC_ID(skb) & 0xff) << 6) | ++ (FOE_BSS_ID(skb) & 0x3f); ++ }else { ++ if (ppe_parse_result.vlan1 == 0) { ++ entry->ipv6_3t_route.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv6_3t_route.etype = ntohs(0x5678); ++ entry->bfib1.vlan_layer = 1; ++ }else if (ppe_parse_result.vlan2 == 0) { ++ entry->ipv6_3t_route.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv6_3t_route.etype = ntohs(0x5678); ++ entry->ipv6_3t_route.vlan2_winfo = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 2; ++ } else { ++ entry->ipv6_3t_route.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv6_3t_route.etype = ntohs(0x5678); ++ entry->ipv6_3t_route.vlan2_winfo = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 3; ++ } ++ } ++ } ++ else { ++ if (ppe_parse_result.vlan1 == 0) { ++ entry->ipv6_3t_route.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv6_3t_route.etype = ntohs(0x5678); ++ entry->bfib1.vlan_layer = 1; ++ }else if (ppe_parse_result.vlan2 == 0) { ++ entry->ipv6_3t_route.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv6_3t_route.etype = ntohs(0x5678); ++ entry->ipv6_3t_route.vlan2 = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 2; ++ } else { ++ entry->ipv6_3t_route.vlan1 = FOE_ENTRY_NUM(skb); ++ entry->ipv6_3t_route.etype = ntohs(0x5678); ++ entry->ipv6_3t_route.vlan2 = ntohs(ppe_parse_result.vlan1); ++ entry->bfib1.vlan_layer = 3; ++ } ++ } ++ } ++ else { ++ ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ if (gmac_no == 3) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 3, 0x3F, 0x3F);/* 3=WDMA */ ++ entry->ipv6_3t_route.iblk2.wdmaid = (FOE_WDMA_ID(skb) & 0x01); ++ entry->ipv6_3t_route.iblk2.winfo = 1; ++ entry->ipv6_3t_route.vlan2_winfo = ++ ((FOE_RX_ID(skb) & 0x03) << 14) | ((FOE_WC_ID(skb) & 0xff) << 6) | ++ (FOE_BSS_ID(skb) & 0x3f); ++ } else ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 0, 0x3F, 0x3F); /* 0=cpu fastpath */ ++ } ++ else ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_3t_route.iblk2, 0, 0x3F, 0x3F); /* 0=cpu fastpath */ ++ } ++ } ++ ++ } ++ else { ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ if (IS_IPV4_GRP(entry)) { ++ if (((FOE_MAGIC_TAG(skb) == FOE_MAGIC_PCI) || ++ (FOE_MAGIC_TAG(skb) == FOE_MAGIC_WLAN))) { ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv4_hnapt.iblk2.fqos = 1; ++ else ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ ++ } ++ else { ++ if (FOE_SP(skb) == 5) { ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ } ++ else { ++ ++ if ((_hwnat_info.features & QDMA_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) { ++ entry->ipv4_hnapt.iblk2.fqos = 1; ++ } ++ else { ++ entry->ipv4_hnapt.iblk2.fqos = 0; ++ } ++ } ++ } ++ } ++ else if (IS_IPV6_GRP(entry)) { ++ if (((FOE_MAGIC_TAG(skb) == FOE_MAGIC_PCI) || ++ (FOE_MAGIC_TAG(skb) == FOE_MAGIC_WLAN))) { ++ if ((_hwnat_info.features & WAN_TO_WLAN_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) ++ entry->ipv6_5t_route.iblk2.fqos = 1; ++ else ++ entry->ipv6_5t_route.iblk2.fqos = 0; ++ ++ } ++ else { ++ if (FOE_SP(skb) == 5) { ++ entry->ipv6_5t_route.iblk2.fqos = 0; ++ } ++ else { ++ if ((_hwnat_info.features & QDMA_SUPPORT_QOS) && (MHal_HWNAT_Get_QoS_Status() == TRUE)) { ++ entry->ipv6_5t_route.iblk2.fqos = 1; ++ } ++ else { ++ entry->ipv6_5t_route.iblk2.fqos = 0; ++ } ++ } ++ } ++ } ++ } ++ ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ if (gmac_no == 1) { ++ if ((_hwnat_info.bind_dir == DOWNSTREAM_ONLY) || (_hwnat_info.bind_dir == BIDIRECTION)) { ++ if (IS_IPV4_GRP(entry)) ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 1, 0x3F, 1); ++ else if (IS_IPV6_GRP(entry)) ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_5t_route.iblk2, 1, 0x3F, 1); ++ } ++ else { ++ return 1; ++ } ++ } ++ else if (gmac_no == 2) { ++ if ((_hwnat_info.bind_dir == UPSTREAM_ONLY) || (_hwnat_info.bind_dir == BIDIRECTION)) { ++ if (IS_IPV4_GRP(entry)) ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 2, 0x3F, 2); ++ else if (IS_IPV6_GRP(entry)) ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_5t_route.iblk2, 2, 0x3F, 2); ++ } ++ else { ++ return 1; ++ } ++ } ++ } ++ else { ++ if (IS_IPV4_GRP(entry)) { ++ if ((entry->ipv4_hnapt.vlan1 & VLAN_VID_MASK) == _hwnat_info.lan_vid) { ++ if ((_hwnat_info.bind_dir == DOWNSTREAM_ONLY) || (_hwnat_info.bind_dir == BIDIRECTION)) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 1, 0x3F, 1); ++ } else { ++ return 1; ++ } ++ } else if ((entry->ipv4_hnapt.vlan1 & VLAN_VID_MASK) == _hwnat_info.wan_vid) { ++ if ((_hwnat_info.bind_dir == UPSTREAM_ONLY) || (_hwnat_info.bind_dir == BIDIRECTION)) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 1, 0x3F, 2); ++ } else { ++ return 1; ++ } ++ } else { /* one-arm */ ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv4_hnapt.iblk2, 1, 0x3F, 1); ++ } ++ } ++ else if (IS_IPV6_GRP(entry)) { ++ if ((entry->ipv6_5t_route.vlan1 & VLAN_VID_MASK) == _hwnat_info.lan_vid) { ++ if ((_hwnat_info.bind_dir == DOWNSTREAM_ONLY) || (_hwnat_info.bind_dir == BIDIRECTION)) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_5t_route.iblk2, 1, 0x3F, 1); ++ } ++ else { ++ return 1; ++ } ++ } ++ else if ((entry->ipv6_5t_route.vlan1 & VLAN_VID_MASK) == _hwnat_info.wan_vid) { ++ if ((_hwnat_info.bind_dir == UPSTREAM_ONLY) || (_hwnat_info.bind_dir == BIDIRECTION)) { ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_5t_route.iblk2, 1, 0x3F, 2); ++ } ++ else { ++ return 1; ++ } ++ } ++ else { /* one-arm */ ++ _MDrv_HWNAT_Set_InfoBlock2(&entry->ipv6_5t_route.iblk2, 1, 0x3F, 1); ++ } ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static MS_BOOL _MDrv_HWNAT_Get_Extif_Offset(struct sk_buff *skb, u32 *retoff) ++{ ++ u32 offset = 0; ++ ++ *retoff = 0; ++ /* Set actual output port info */ ++ if (IS_SPECIAL_DEV(_hwnat_info.features) && (strncmp(skb->dev->name, "rai", 3) == 0)) { ++ if (_hwnat_info.features & HW_NAT_AP_MESH_SUPPORT) { ++ if (HWNAT_GET_PACKET_IF(skb) >= MIN_NET_DEVICE_FOR_MESH) ++ offset = (HWNAT_GET_PACKET_IF(skb) - MIN_NET_DEVICE_FOR_MESH + DP_MESHI0); ++ else ++ offset = HWNAT_GET_PACKET_IF(skb) + DP_RAI0; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_APCLI_SUPPORT) { ++ if (HWNAT_GET_PACKET_IF(skb) >= MIN_NET_DEVICE_FOR_APCLI) ++ offset = (HWNAT_GET_PACKET_IF(skb) - MIN_NET_DEVICE_FOR_APCLI + DP_APCLII0); ++ else ++ offset = HWNAT_GET_PACKET_IF(skb) + DP_RAI0; ++ } ++ if (_hwnat_info.features & HW_NAT_WDS_SUPPORT) { ++ if (HWNAT_GET_PACKET_IF(skb) >= MIN_NET_DEVICE_FOR_WDS) ++ offset = (HWNAT_GET_PACKET_IF(skb) - MIN_NET_DEVICE_FOR_WDS + DP_WDSI0); ++ else ++ offset = HWNAT_GET_PACKET_IF(skb) + DP_RAI0; ++ } ++ ++ } ++ else if (strncmp(skb->dev->name, "ra", 2) == 0) { ++ if (_hwnat_info.features & HW_NAT_AP_MESH_SUPPORT) { ++ if (HWNAT_GET_PACKET_IF(skb) >= MIN_NET_DEVICE_FOR_MESH) ++ offset = (HWNAT_GET_PACKET_IF(skb) - MIN_NET_DEVICE_FOR_MESH + DP_MESH0); ++ else ++ offset = HWNAT_GET_PACKET_IF(skb) + DP_RA0; ++ } ++ if (_hwnat_info.features & HW_NAT_APCLI_SUPPORT) { ++ if (HWNAT_GET_PACKET_IF(skb) >= MIN_NET_DEVICE_FOR_APCLI) ++ offset = (HWNAT_GET_PACKET_IF(skb) - MIN_NET_DEVICE_FOR_APCLI + DP_APCLI0); ++ else ++ offset = HWNAT_GET_PACKET_IF(skb) + DP_RA0; ++ } ++ if (_hwnat_info.features & HW_NAT_WDS_SUPPORT) { ++ if (HWNAT_GET_PACKET_IF(skb) >= MIN_NET_DEVICE_FOR_WDS) ++ offset = (HWNAT_GET_PACKET_IF(skb) - MIN_NET_DEVICE_FOR_WDS + DP_WDS0); ++ else ++ offset = HWNAT_GET_PACKET_IF(skb) + DP_RA0; ++ } ++ } ++ else if (_hwnat_info.features & HW_NAT_NIC_USB) { ++ if (strncmp(skb->dev->name, "eth0", 4) == 0) ++ offset = DP_PCI; ++ else if (strncmp(skb->dev->name, "eth1", 4) == 0) ++ offset = DP_USB; ++ } ++ else if (strncmp(skb->dev->name, "eth2", 4) == 0) ++ offset = DP_GMAC; ++ else if ((_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) && (strncmp(skb->dev->name, "eth3", 4) == 0)) ++ offset = DP_GMAC2; ++ else { ++ if (pr_debug_ratelimited()) ++ NAT_PRINT("HNAT: unknown interface %s\n", skb->dev->name); ++ return FALSE; ++ } ++ ++ *retoff = offset; ++ ++ return TRUE; ++} ++ ++ ++uint32_t _MDrv_HWNAT_Set_Extif_Num(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ u32 offset = 0; ++ ++ if (((_hwnat_info.features & HW_NAT_WIFI) == 0) && ((_hwnat_info.features & HW_NAT_NIC_USB) == 0)) { ++ return 0; ++ } ++ ++ if ((_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) == 0x0) { ++ /* Set actual output port info */ ++ if (_MDrv_HWNAT_Get_Extif_Offset(skb, &offset) == FALSE) { ++ return 1; ++ } ++ } ++ ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) { ++ int dev_match = -1; ++ ++ dev_match = _MDrv_HWNAT_Get_Dev_Handler_Idx(skb->dev); ++ if (dev_match < 0) { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("UnKnown Interface %s \n", skb->dev->name); ++ return 1; ++ } ++ else { ++ offset = dev_match; ++ } ++ } ++ ++ if (IS_IPV4_HNAT(entry) || IS_IPV4_HNAPT(entry)) ++ entry->ipv4_hnapt.act_dp = offset; ++ else if (IS_IPV4_DSLITE(entry)) { ++ entry->ipv4_dslite.act_dp = offset; ++ } ++ else if (IS_IPV6_3T_ROUTE(entry)) { ++ entry->ipv6_3t_route.act_dp = offset; ++ } ++ else if (IS_IPV6_5T_ROUTE(entry)) { ++ entry->ipv6_5t_route.act_dp = offset; ++ } ++ else if (IS_IPV6_6RD(entry)) { ++ entry->ipv6_6rd.act_dp = offset; ++ } ++ else { ++ return 1; ++ } ++ return 0; ++} ++ ++void _MDrv_HWNAT_Set_Entry_Bind(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ u32 current_time; ++ /* Set Current time to time_stamp field in information block 1 */ ++ current_time = MHAL_HWNAT_Get_TimeStamp() & 0xFFFF; ++ entry->bfib1.time_stamp = (uint16_t)current_time; ++ ++ /* Ipv4: TTL / Ipv6: Hot Limit filed */ ++ entry->ipv4_hnapt.bfib1.ttl = DFL_FOE_TTL_REGEN; ++ /* enable cache by default */ ++ entry->ipv4_hnapt.bfib1.cah = 1; ++ ++ ++ if (_hwnat_info.features & PACKET_SAMPLING) { ++ entry->ipv4_hnapt.bfib1.ps = 1; ++ } ++ ++ if (_hwnat_info.features & NAT_PREBIND) { ++ entry->udib1.preb = 1; ++ } ++ else { ++ /* Change Foe Entry State to Binding State */ ++ entry->bfib1.state = BIND; ++ /* Dump Binding Entry */ ++ if (_hwnat_info.debug_level >= 1) { ++ NAT_PRINT(" Bind \n"); ++ MDrv_HWNAT_Foe_Dump_Entry(FOE_ENTRY_NUM(skb)); ++ } ++ } ++ ++ /*make sure write dram correct*/ ++ wmb(); ++} ++ ++void _MDrv_HWNAT_Regist_Dev_Handler(struct net_device *dev) ++{ ++ int i; ++ for (i = 0; i < MAX_IF_NUM; i++) { ++ if (dst_port[i] == dev) { ++ NAT_PRINT("%s dst_port table has beed registered(%d)\n", dev->name, i); ++ return; ++ } ++ if (dst_port[i] == NULL) { ++ dst_port[i] = dev; ++ break; ++ } ++ } ++ NAT_PRINT("ineterface %s register (%d)\n", dev->name, i); ++} ++ ++void _MDrv_HWNAT_Unregist_Dev_Handler(struct net_device *dev) ++{ ++ int i; ++ for (i = 0; i < MAX_IF_NUM; i++) { ++ if (dst_port[i] == dev) { ++ dst_port[i] = NULL; ++ break; ++ } ++ } ++ NAT_PRINT("ineterface %s unregister (%d)\n", dev->name, i); ++} ++ ++ ++ ++int _MDrv_HWNAT_Get_Done_Bit(struct sk_buff *skb, struct foe_entry * entry) ++{ ++ int done_bit = 0; ++ if (IS_IPV4_HNAT(entry) || IS_IPV4_HNAPT(entry)) { ++ done_bit = entry->ipv4_hnapt.resv1; ++ } ++ else if (_hwnat_info.features & NAT_IPV6) { ++ if (IS_IPV4_DSLITE(entry)) { ++ done_bit = entry->ipv4_dslite.resv1; ++ } else if (IS_IPV6_3T_ROUTE(entry)) { ++ done_bit = entry->ipv6_3t_route.resv1; ++ } else if (IS_IPV6_5T_ROUTE(entry)) { ++ done_bit = entry->ipv6_5t_route.resv1; ++ } else if (IS_IPV6_6RD(entry)) { ++ done_bit = entry->ipv6_6rd.resv1; ++ } else { ++ HWNAT_MSG_ERR("get packet format something wrong\n"); ++ return 0; ++ } ++ } ++ if ((done_bit != 0) && (done_bit !=1)){ ++ HWNAT_MSG_DBG("done bit something wrong, done_bit = %d\n", done_bit); ++ done_bit = 0; ++ } ++ //HWNAT_MSG_DBG("index = %d, done_bit=%d\n", FOE_ENTRY_NUM(skb), done_bit); ++ return done_bit; ++} ++ ++void _MDrv_HWNAT_Set_Done_Bit(struct foe_entry * entry) ++{ ++ if (IS_IPV4_HNAT(entry) || IS_IPV4_HNAPT(entry)) { ++ entry->ipv4_hnapt.resv1 = 1; ++ } ++ else if (_hwnat_info.features & NAT_IPV6) { ++ if (IS_IPV4_DSLITE(entry)) { ++ entry->ipv4_dslite.resv1 = 1; ++ } else if (IS_IPV6_3T_ROUTE(entry)) { ++ entry->ipv6_3t_route.resv1 = 1; ++ } else if (IS_IPV6_5T_ROUTE(entry)) { ++ entry->ipv6_5t_route.resv1 = 1; ++ } else if (IS_IPV6_6RD(entry)) { ++ entry->ipv6_6rd.resv1 = 1; ++ } else { ++ HWNAT_MSG_ERR("set packet format something wrong\n"); ++ } ++ } ++ wmb(); ++} ++ ++int _MDrv_HWNAT_Is_Wireless_Interface(struct sk_buff *skb) ++{ ++ if ((strncmp(skb->dev->name, "rai", 3) == 0) || ++ (strncmp(skb->dev->name, "apclii", 6) == 0) || ++ (strncmp(skb->dev->name, "wdsi", 4) == 0) || ++ (strncmp(skb->dev->name, "wlan", 4) == 0)) ++ return 1; ++ else ++ return 0; ++} ++ ++ ++ ++static void _MDrv_HWNAT_Handle_Mcast_Entry(struct sk_buff *skb, int gmac_no) ++{ ++ if (ppe_parse_result.is_mcast) { ++ MDrv_HWNAT_Mcast_Update_Qid(ppe_parse_result.vlan1, ppe_parse_result.dmac, M2Q_table[skb->mark]); ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ if (lan_wan_separate == 1 && gmac_no == 2) { ++ MDrv_HWNAT_Mcast_Update_Qid(ppe_parse_result.vlan1, ppe_parse_result.dmac, M2Q_table[skb->mark] + 8); ++ if (_hwnat_info.features & HW_NAT_HW_SFQ) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) ++ MDrv_HWNAT_Mcast_Update_Qid(ppe_parse_result.vlan1, ppe_parse_result.dmac, HWSFQUP); ++ /* queue3 */ ++ } ++ } ++ if ((lan_wan_separate == 1) && (gmac_no == 1)) { ++ if (_hwnat_info.features & HW_NAT_HW_SFQ) { ++ if (web_sfq_enable == 1 && (skb->mark == 2)) ++ MDrv_HWNAT_Mcast_Update_Qid(ppe_parse_result.vlan1, ppe_parse_result.dmac, HWSFQDL); ++ /* queue0 */ ++ } ++ } ++ } ++ ++ ++ } ++} ++ ++static MS_BOOL _MDrv_HWNAT_Set_UDP_Frag(struct sk_buff *skb) ++{ ++ if (_hwnat_info.features & WLAN_OPTIMIZE) { ++ if (_MDrv_HWNAT_Is_BrLan_Subnet(skb) == FALSE) { ++ if (!_MDrv_HWNAT_Is_Wireless_Interface(skb)) { ++ USE_3T_UDP_FRAG = 0; ++ return FALSE; ++ } ++ else ++ USE_3T_UDP_FRAG = 1; ++ } ++ else ++ USE_3T_UDP_FRAG = 0; ++ } ++ else { ++ if (_MDrv_HWNAT_Is_BrLan_Subnet(skb)) { ++ USE_3T_UDP_FRAG = 1; ++ } ++ else ++ USE_3T_UDP_FRAG = 0; ++ ++ } ++ return TRUE; ++} ++ ++static MS_BOOL _MDrv_HWNAT_Reach_Unbind_Rate(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ if (_hwnat_info.features & HW_NAT_SEMI_AUTO_MODE) { ++ if (IS_MAGIC_TAG_PROTECT_VALID(skb) && ++ (FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && ++ (FOE_ALG(skb) == 0) && (_MDrv_HWNAT_Get_Done_Bit(skb, entry) == 0)) { ++ HWNAT_MSG_DUMP("ppe driver set entry index = %d\n", FOE_ENTRY_NUM(skb)); ++ return TRUE; ++ } ++ } ++ else { ++ if (IS_MAGIC_TAG_PROTECT_VALID(skb) && ++ (FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && ++ (FOE_ALG(skb) == 0)) { ++ return TRUE; ++ } ++ } ++ return FALSE; ++} ++ ++static int32_t _MDrv_HWNAT_Handle_PPTP_L2TP_Tx(struct sk_buff *skb, struct foe_entry *entry) ++{ ++ if (pptp_fast_path) { ++ if (FOE_MAGIC_TAG(skb) == FOE_MAGIC_FASTPATH) { ++ FOE_MAGIC_TAG(skb) = 0; ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("MDrv_HWNAT_Handle_Tx FOE_MAGIC_FASTPATH\n"); ++ hash_cnt++; ++ if ((FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && ++ (skb->len > 128) && (hash_cnt % 32 == 1)) { ++ MDrv_HWNAT_Send_Hash_Pkt(skb); ++ } ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ } ++ /*WAN->LAN accelerate*/ ++ if (l2tp_fast_path) { ++ if (FOE_MAGIC_TAG(skb) == FOE_MAGIC_FASTPATH) { ++ FOE_MAGIC_TAG(skb) = 0; ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("MDrv_HWNAT_Handle_Tx FOE_MAGIC_FASTPATH\n"); ++ hash_cnt++; ++ /* if((FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && (skb->len > 1360)) */ ++ if ((FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && ++ (skb->len > 1360) && (hash_cnt % 32 == 1)) { ++ /* NAT_PRINT("hash_cnt is %d\n", hash_cnt); */ ++ MDrv_HWNAT_L2tp_Send_Hash_Pkt(skb); ++ } ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ } ++ ++ if (IS_MAGIC_TAG_PROTECT_VALID(skb) && ++ (FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && ++ (FOE_ALG(skb) == 0)) { ++ struct iphdr *iph = NULL; ++ struct udphdr *uh = NULL; ++ ++ iph = (struct iphdr *)(skb->data + 14 + VLAN_LEN); ++ uh = (struct udphdr *)(skb->data + 14 + VLAN_LEN + 20); ++ ++ /* NAT_PRINT("iph->protocol is 0x%2x\n",iph->protocol); */ ++ /* NAT_PRINT("uh->dest is %4x\n",uh->dest); */ ++ /* NAT_PRINT("uh->source is %4x\n",uh->source); */ ++ /* NAT_PRINT("FOE_AI(skb) is 0x%x\n",FOE_AI(skb)); */ ++ ++ /* skb_dump(skb); */ ++ if ((iph->protocol == IPPROTO_GRE) || (ntohs(uh->dest) == 1701)) { ++ /*BIND flow using pptp/l2tp packets info */ ++ /* skb_dump(skb); */ ++ /* NAT_PRINT("LAN->WAN TxH HIT_UNBIND_RATE_REACH\n"); */ ++ /* MDrv_HWNAT_Foe_Dump_Entry(FOE_ENTRY_NUM(skb)); */ ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("LAN->WAN TxH PMDrv_HWNAT_Pptp_Wan_Parse_Layer\n"); ++ ++ if (pptp_fast_path) { ++ if (MDrv_HWNAT_Pptp_Wan_Parse_Layer(skb)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ } ++ ++ if (l2tp_fast_path) { ++ if (MDrv_HWNAT_L2tp_Wan_Parse_Layer(skb)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ } ++ ++ /*layer2 keep original */ ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("Lan -> Wan _MDrv_HWNAT_Fill_L2\n"); ++ /* Set Layer2 Info */ ++ if (_MDrv_HWNAT_Fill_L2(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ /*already bind packet, return 1 to go out */ ++ return 1; ++ } ++ ++ /* Set Layer3 Info */ ++ if (_MDrv_HWNAT_Fill_L3(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ ++ /* Set Layer4 Info */ ++ if (_MDrv_HWNAT_Fill_L4(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ ++ /* Set force port to CPU!!! */ ++ if (MDrv_HWNAT_Set_Force_Port(skb, entry, 777)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("_MDrv_HWNAT_Set_Entry_Bind\n"); ++ /* Set Pseudo Interface info in Foe entry */ ++ /* Enter binding state */ ++ _MDrv_HWNAT_Set_Entry_Bind(skb, entry); ++ return 1; ++ } ++ } ++ return 0; ++} ++ ++ ++int32_t MDrv_HWNAT_Handle_Tx(struct sk_buff *skb, int gmac_no) ++{ ++ struct foe_entry *entry = FOE_ENTRY_BASE_BY_PKT(_hwnat_info.ppe_foe_base, skb); ++ struct ps_entry *ps_entry = NULL; ++ u8 which_region; ++ ++ if (_hwnat_info.features & PACKET_SAMPLING) ++ ps_entry = PS_ENTRY_BASE_BY_PKT(_hwnat_info.ppe_ps_base, skb); ++ ++ which_region = _MDrv_HWNAT_Get_Tx_Region(skb); ++ if (which_region == ALL_INFO_ERROR) { ++ if (pr_debug_ratelimited()) ++ NAT_PRINT("MDrv_HWNAT_Handle_Tx : ALL_INFO_ERROR %04X,%04X\n", FOE_TAG_PROTECT_HEAD(skb), FOE_TAG_PROTECT_TAIL(skb)); ++ return 1; ++ } ++ if (FOE_ENTRY_NUM(skb) == 0x3fff) { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("FOE_ENTRY_NUM(skb)= 0x%x\n", FOE_ENTRY_NUM(skb)); ++ return 1; ++ } ++ ++ if (FOE_ENTRY_NUM(skb) > FOE_4TB_SIZ) { ++ if (_hwnat_info.debug_level >= 1) ++ NAT_PRINT("FOE_ENTRY_NUM(skb)= 0x%x\n", FOE_ENTRY_NUM(skb)); ++ return 1; ++ } ++ ++ if (_hwnat_info.debug_level >= 7) ++ MDrv_HWNAT_Dump_TxSkb(skb); ++ ++ /* Packet is interested by ALG?*/ ++ /* Yes: Don't enter binind state*/ ++ /* No: If flow rate exceed binding threshold, enter binding state.*/ ++ if (_hwnat_info.features & PPTP_L2TP) { ++ if (_MDrv_HWNAT_Handle_PPTP_L2TP_Tx(skb, entry) == 1) { ++ return 1; ++ } ++ } ++ ++ if (_MDrv_HWNAT_Reach_Unbind_Rate(skb, entry)) { ++ ++ if (_MDrv_HWNAT_Set_UDP_Frag(skb) == FALSE) { ++ return 1; ++ } ++ ++ if (_hwnat_info.debug_level >= 6) { ++ NAT_PRINT(" which_region = %d\n", which_region); ++ } ++ ++ /* get start addr for each layer */ ++ if (_MDrv_HWNAT_Parse_Pkt_Layer(skb)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ /* Set Layer2 Info */ ++ if (_MDrv_HWNAT_Fill_L2(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ /* Set Layer3 Info */ ++ if (_MDrv_HWNAT_Fill_L3(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ ++ /* Set Layer4 Info */ ++ if (_MDrv_HWNAT_Fill_L4(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ ++ /* Set force port info */ ++ if (MDrv_HWNAT_Set_Force_Port(skb, entry, gmac_no)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ ++ /* Set Pseudo Interface info in Foe entry */ ++ if (_MDrv_HWNAT_Set_Extif_Num(skb, entry)) { ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 1; ++ } ++ if (IS_QDMA_MCAST_SUPPORT(_hwnat_info.features)) { ++ _MDrv_HWNAT_Handle_Mcast_Entry(skb, gmac_no); ++ } ++ ++ if (_hwnat_info.features & PPE_MIB) { ++ MHal_HWNAT_Clear_MIB_Counter(FOE_ENTRY_NUM(skb)); ++ } ++ ++ if (_hwnat_info.features & HW_NAT_AUTO_MODE) { ++ /* Enter binding state */ ++ _MDrv_HWNAT_Set_Entry_Bind(skb, entry); ++ } ++ else if (_hwnat_info.features & HW_NAT_SEMI_AUTO_MODE) { ++ _MDrv_HWNAT_Set_Done_Bit(entry); ++ } ++ ++ if (_hwnat_info.features & PACKET_SAMPLING) { ++ /*add sampling policy here*/ ++ ps_entry->en = 0x1 << 1; ++ ps_entry->pkt_cnt = 0x10; ++ } ++ ++ } ++ else if (IS_MAGIC_TAG_PROTECT_VALID(skb) && (FOE_AI(skb) == HIT_BIND_PACKET_SAMPLING)) { ++ /* this is duplicate packet in PS function*/ ++ /* just drop it */ ++ NAT_PRINT("PS drop#%d\n", FOE_ENTRY_NUM(skb)); ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 0; ++ } ++ else if (IS_MAGIC_TAG_PROTECT_VALID(skb) && ++ (FOE_AI(skb) == HIT_BIND_KEEPALIVE_MC_NEW_HDR || ++ (FOE_AI(skb) == HIT_BIND_KEEPALIVE_DUP_OLD_HDR))) { ++ /*this is duplicate packet in keepalive new header mode*/ ++ /*just drop it */ ++ if (_hwnat_info.debug_level >= 3) ++ NAT_PRINT("TxGot HITBIND_KEEPALIVE_DUP_OLD packe (%d)\n", FOE_ENTRY_NUM(skb)); ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 0; ++ } ++ else if (IS_MAGIC_TAG_PROTECT_VALID(skb) && ++ (FOE_AI(skb) == HIT_UNBIND_RATE_REACH) && (FOE_ALG(skb) == 1)) { ++ if (_hwnat_info.debug_level >= 3) ++ NAT_PRINT("FOE_ALG=1 (Entry=%d)\n", FOE_ENTRY_NUM(skb)); ++ } ++ else if ((_hwnat_info.features & NAT_PREBIND) && (FOE_AI(skb) == HIT_PRE_BIND)) { ++ if (entry->udib1.preb && entry->bfib1.state != BIND) { ++ entry->bfib1.state = BIND; ++ entry->udib1.preb = 0; ++ /* Dump Binding Entry */ ++ if (_hwnat_info.debug_level >= 1) ++ MDrv_HWNAT_Foe_Dump_Entry(FOE_ENTRY_NUM(skb)); ++ } ++ else { ++ /* drop duplicate prebind notify packet */ ++ memset(FOE_INFO_START_ADDR(skb), 0, FOE_INFO_LEN); ++ return 0; ++ } ++ } ++ ++ return 1; ++} ++ ++ ++static int _MDrv_HWNAT_Init_Hash_Mode(struct HWNAT_DEVICE *phwnat) ++{ ++ struct mhal_table_info info = {0}; ++ /* Allocate FOE table base */ ++ if (!_MDrv_HWNAT_Alloc_Tbl(phwnat)) ++ return 0; ++ ++ info.foe_adr = phwnat->ppe_phy_foe_base; ++ info.ps_adr = phwnat->ppe_phy_ps_base; ++ info.mib_adr = phwnat->ppe_phy_mib_base; ++ info.entries = phwnat->table_entries; ++ info.hash_dbg = phwnat->hash_debug; ++ info.ipv6 = TRUE; ++ info.prebind = (phwnat->features & NAT_PREBIND)?TRUE:FALSE; ++ info.hash_mode = phwnat->hash_mode; ++ info.mcast = (phwnat->features & PPE_MCAST)?TRUE:FALSE; ++ info.qtx_qrx = (phwnat->features & HW_NAT_QDMATX_QDMARX)?TRUE:FALSE; ++ ++ if (phwnat->features == HW_NAT_SEMI_AUTO_MODE) ++ info.op_mode = E_HWNAT_OPMODE_SEMI_AUTO; ++ else if (phwnat->features == HW_NAT_MANUAL_MODE) ++ info.op_mode = E_HWNAT_OPMODE_MANUAL; ++ else ++ info.op_mode = E_HWNAT_OPMODE_AUTO; ++ ++ MHal_HWNAT_Init(&info); ++ ++ return 1; ++} ++ ++ ++static void _MDrv_HWNAT_Set_Dst_Port(uint32_t ebl) ++{ ++ if (ebl) { ++ if ((_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) == 0x0) { ++ if (_hwnat_info.features & HW_NAT_WIFI) { ++ dst_port[DP_RA0] = dev_get_by_name(&init_net,"ra0"); ++ if (IS_APMBSS_MBSS_DEV(_hwnat_info.features)) { ++ dst_port[DP_RA1] = dev_get_by_name(&init_net,"ra1"); ++ dst_port[DP_RA2] = dev_get_by_name(&init_net,"ra2"); ++ dst_port[DP_RA3] = dev_get_by_name(&init_net,"ra3"); ++ dst_port[DP_RA4] = dev_get_by_name(&init_net,"ra4"); ++ dst_port[DP_RA5] = dev_get_by_name(&init_net,"ra5"); ++ dst_port[DP_RA6] = dev_get_by_name(&init_net,"ra6"); ++ dst_port[DP_RA7] = dev_get_by_name(&init_net,"ra7"); ++ if (_hwnat_info.features & HW_NAT_MBSS_SUPPORT) { ++ dst_port[DP_RA8] = dev_get_by_name(&init_net,"ra8"); ++ dst_port[DP_RA9] = dev_get_by_name(&init_net,"ra9"); ++ dst_port[DP_RA10] = dev_get_by_name(&init_net,"ra10"); ++ dst_port[DP_RA11] = dev_get_by_name(&init_net,"ra11"); ++ dst_port[DP_RA12] = dev_get_by_name(&init_net,"ra12"); ++ dst_port[DP_RA13] = dev_get_by_name(&init_net,"ra13"); ++ dst_port[DP_RA14] = dev_get_by_name(&init_net,"ra14"); ++ dst_port[DP_RA15] = dev_get_by_name(&init_net,"ra15"); ++ } ++ } ++ if (_hwnat_info.features & HW_NAT_WDS_SUPPORT) { ++ dst_port[DP_WDS0] = dev_get_by_name(&init_net,"wds0"); ++ dst_port[DP_WDS1] = dev_get_by_name(&init_net,"wds1"); ++ dst_port[DP_WDS2] = dev_get_by_name(&init_net,"wds2"); ++ dst_port[DP_WDS3] = dev_get_by_name(&init_net,"wds3"); ++ } ++ ++ if (_hwnat_info.features & HW_NAT_APCLI_SUPPORT) ++ dst_port[DP_APCLI0] = dev_get_by_name(&init_net,"apcli0"); ++ ++ if (_hwnat_info.features & HW_NAT_AP_MESH_SUPPORT) ++ dst_port[DP_MESH0] = dev_get_by_name(&init_net,"mesh0"); ++ if (IS_SPECIAL_DEV(_hwnat_info.features)) { ++ dst_port[DP_RAI0] = dev_get_by_name(&init_net,"rai0"); ++ if (_hwnat_info.features & HW_NAT_AP_MBSS_SUPPORT) { ++ dst_port[DP_RAI1] = dev_get_by_name(&init_net,"rai1"); ++ dst_port[DP_RAI2] = dev_get_by_name(&init_net,"rai2"); ++ dst_port[DP_RAI3] = dev_get_by_name(&init_net,"rai3"); ++ dst_port[DP_RAI4] = dev_get_by_name(&init_net,"rai4"); ++ dst_port[DP_RAI5] = dev_get_by_name(&init_net,"rai5"); ++ dst_port[DP_RAI6] = dev_get_by_name(&init_net,"rai6"); ++ dst_port[DP_RAI7] = dev_get_by_name(&init_net,"rai7"); ++ dst_port[DP_RAI8] = dev_get_by_name(&init_net,"rai8"); ++ dst_port[DP_RAI9] = dev_get_by_name(&init_net,"rai9"); ++ dst_port[DP_RAI10] = dev_get_by_name(&init_net,"rai10"); ++ dst_port[DP_RAI11] = dev_get_by_name(&init_net,"rai11"); ++ dst_port[DP_RAI12] = dev_get_by_name(&init_net,"rai12"); ++ dst_port[DP_RAI13] = dev_get_by_name(&init_net,"rai13"); ++ dst_port[DP_RAI14] = dev_get_by_name(&init_net,"rai14"); ++ dst_port[DP_RAI15] = dev_get_by_name(&init_net,"rai15"); ++ } ++ } ++ if (_hwnat_info.features & HW_NAT_APCLI_SUPPORT) ++ dst_port[DP_APCLII0] = dev_get_by_name(&init_net,"apclii0"); ++ if (_hwnat_info.features & HW_NAT_WDS_SUPPORT) { ++ dst_port[DP_WDSI0] = dev_get_by_name(&init_net,"wdsi0"); ++ dst_port[DP_WDSI1] = dev_get_by_name(&init_net,"wdsi1"); ++ dst_port[DP_WDSI2] = dev_get_by_name(&init_net,"wdsi2"); ++ dst_port[DP_WDSI3] = dev_get_by_name(&init_net,"wdsi3"); ++ } ++ ++ if (_hwnat_info.features & HW_NAT_AP_MESH_SUPPORT) ++ dst_port[DP_MESHI0] = dev_get_by_name(&init_net,"meshi0"); ++ ++ if (_hwnat_info.features & HW_NAT_NIC_USB) { ++ dst_port[DP_PCI] = dev_get_by_name(&init_net,"eth0"); /* PCI interface name */ ++ dst_port[DP_USB] = dev_get_by_name(&init_net,"eth1"); /* USB interface name */ ++ } ++ } ++ } ++ ++ ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) { ++ struct net_device *dev; ++ dev = MDrv_NOE_Get_Dev(E_NOE_DEV_MAIN); ++ _MDrv_HWNAT_Regist_Dev_Handler(dev); ++ DP_GMAC1 = _MDrv_HWNAT_Get_Dev_Handler_Idx(dev); ++ HWNAT_MSG_DBG("%s ifindex =%x\n", dev->name, DP_GMAC1); ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ dev = MDrv_NOE_Get_Dev(E_NOE_DEV_PSEUDO); ++ if (dev != NULL) { ++ _MDrv_HWNAT_Regist_Dev_Handler(dev); ++ DPORT_GMAC2 = _MDrv_HWNAT_Get_Dev_Handler_Idx(dev); ++ HWNAT_MSG_DBG("%s ifindex =%x\n", dev->name, DPORT_GMAC2); ++ } ++ else { ++ HWNAT_MSG_WARN("cannot find noe gmac2\n"); ++ } ++ } ++ } ++ else { ++ dst_port[DP_GMAC] = MDrv_NOE_Get_Dev(E_NOE_DEV_MAIN); ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ dst_port[DP_GMAC2] = MDrv_NOE_Get_Dev(E_NOE_DEV_PSEUDO); ++ } ++ } ++ } ++ else { ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) { ++ int j = 0; ++ for (j = 0; j < MAX_IF_NUM; j++) { ++ if (dst_port[j]) { ++ dev_put(dst_port[j]); ++ dst_port[j] = NULL; ++ } ++ } ++ } ++ else { ++ ++ if (_hwnat_info.features & HW_NAT_WIFI) { ++ if (dst_port[DP_RA0]) ++ dev_put(dst_port[DP_RA0]); ++ if (dst_port[DP_RA1]) ++ dev_put(dst_port[DP_RA1]); ++ if (dst_port[DP_RA2]) ++ dev_put(dst_port[DP_RA2]); ++ if (dst_port[DP_RA3]) ++ dev_put(dst_port[DP_RA3]); ++ if (dst_port[DP_RA4]) ++ dev_put(dst_port[DP_RA4]); ++ if (dst_port[DP_RA5]) ++ dev_put(dst_port[DP_RA5]); ++ if (dst_port[DP_RA6]) ++ dev_put(dst_port[DP_RA6]); ++ if (dst_port[DP_RA7]) ++ dev_put(dst_port[DP_RA7]); ++ if (dst_port[DP_RA8]) ++ dev_put(dst_port[DP_RA8]); ++ if (dst_port[DP_RA9]) ++ dev_put(dst_port[DP_RA9]); ++ if (dst_port[DP_RA10]) ++ dev_put(dst_port[DP_RA10]); ++ if (dst_port[DP_RA11]) ++ dev_put(dst_port[DP_RA11]); ++ if (dst_port[DP_RA12]) ++ dev_put(dst_port[DP_RA12]); ++ if (dst_port[DP_RA13]) ++ dev_put(dst_port[DP_RA13]); ++ if (dst_port[DP_RA14]) ++ dev_put(dst_port[DP_RA14]); ++ if (dst_port[DP_RA15]) ++ dev_put(dst_port[DP_RA15]); ++ if (dst_port[DP_WDS0]) ++ dev_put(dst_port[DP_WDS0]); ++ if (dst_port[DP_WDS1]) ++ dev_put(dst_port[DP_WDS1]); ++ if (dst_port[DP_WDS2]) ++ dev_put(dst_port[DP_WDS2]); ++ if (dst_port[DP_WDS3]) ++ dev_put(dst_port[DP_WDS3]); ++ if (dst_port[DP_APCLI0]) ++ dev_put(dst_port[DP_APCLI0]); ++ if (dst_port[DP_MESH0]) ++ dev_put(dst_port[DP_MESH0]); ++ if (dst_port[DP_RAI0]) ++ dev_put(dst_port[DP_RAI0]); ++ if (dst_port[DP_RAI1]) ++ dev_put(dst_port[DP_RAI1]); ++ if (dst_port[DP_RAI2]) ++ dev_put(dst_port[DP_RAI2]); ++ if (dst_port[DP_RAI3]) ++ dev_put(dst_port[DP_RAI3]); ++ if (dst_port[DP_RAI4]) ++ dev_put(dst_port[DP_RAI4]); ++ if (dst_port[DP_RAI5]) ++ dev_put(dst_port[DP_RAI5]); ++ if (dst_port[DP_RAI6]) ++ dev_put(dst_port[DP_RAI6]); ++ if (dst_port[DP_RAI7]) ++ dev_put(dst_port[DP_RAI7]); ++ if (dst_port[DP_RAI8]) ++ dev_put(dst_port[DP_RAI8]); ++ if (dst_port[DP_RAI9]) ++ dev_put(dst_port[DP_RAI9]); ++ if (dst_port[DP_RAI10]) ++ dev_put(dst_port[DP_RAI10]); ++ if (dst_port[DP_RAI11]) ++ dev_put(dst_port[DP_RAI11]); ++ if (dst_port[DP_RAI12]) ++ dev_put(dst_port[DP_RAI12]); ++ if (dst_port[DP_RAI13]) ++ dev_put(dst_port[DP_RAI13]); ++ if (dst_port[DP_RAI14]) ++ dev_put(dst_port[DP_RAI14]); ++ if (dst_port[DP_RAI15]) ++ dev_put(dst_port[DP_RAI15]); ++ if (dst_port[DP_APCLII0]) ++ dev_put(dst_port[DP_APCLII0]); ++ if (dst_port[DP_WDSI0]) ++ dev_put(dst_port[DP_WDSI0]); ++ if (dst_port[DP_WDSI1]) ++ dev_put(dst_port[DP_WDSI1]); ++ if (dst_port[DP_WDSI2]) ++ dev_put(dst_port[DP_WDSI2]); ++ if (dst_port[DP_WDSI3]) ++ dev_put(dst_port[DP_WDSI3]); ++ ++ ++ if (dst_port[DP_MESHI0]) ++ dev_put(dst_port[DP_MESHI0]); ++ if (dst_port[DP_GMAC]) ++ dev_put(dst_port[DP_GMAC]); ++ if (_hwnat_info.features & HW_NAT_PSEUDO_SUPPORT) { ++ if (dst_port[DP_GMAC2]) ++ dev_put(dst_port[DP_GMAC2]); ++ } ++ } ++ if (_hwnat_info.features & HW_NAT_NIC_USB) { ++ if (dst_port[DP_PCI]) ++ dev_put(dst_port[DP_PCI]); ++ if (dst_port[DP_USB]) ++ dev_put(dst_port[DP_USB]); ++ } ++ } ++ } ++} ++ ++ ++ ++static void _MDrv_HWNAT_Handle_Ac_Update(unsigned long unused) ++{ ++ int i = 0; ++ struct mhal_hwnat_ac_info info; ++ ++ for (i = 1; i <= 2; i++) { ++ memset(&info, 0, sizeof(struct mhal_hwnat_ac_info)); ++ info.idx = i; ++ MHal_HWNAT_Get_Ac_Info(&info); ++ ac_info[i].ag_byte_cnt += info.bytes; ++ ac_info[i].ag_pkt_cnt += info.pkts; ++ } ++ update_foe_ac_timer.expires = jiffies + 16 * HZ; ++ add_timer(&update_foe_ac_timer); ++} ++ ++static void _MDrv_HWNAT_Init_Ac_Update(void) ++{ ++ ac_info[1].ag_byte_cnt = 0; ++ ac_info[1].ag_pkt_cnt = 0; ++ ac_info[2].ag_byte_cnt = 0; ++ ac_info[2].ag_pkt_cnt = 0; ++ ac_info[3].ag_byte_cnt = 0; ++ ac_info[3].ag_pkt_cnt = 0; ++ ac_info[4].ag_byte_cnt = 0; ++ ac_info[4].ag_pkt_cnt = 0; ++ ac_info[5].ag_byte_cnt = 0; ++ ac_info[5].ag_pkt_cnt = 0; ++ ac_info[6].ag_byte_cnt = 0; ++ ac_info[6].ag_pkt_cnt = 0; ++} ++ ++static void _MDrv_HWNAT_Set_Ac_Update(int ebl) ++{ ++ if (_hwnat_info.features & ACCNT_MAINTAINER) { ++ if (ebl) { ++ _MDrv_HWNAT_Init_Ac_Update(); ++ update_foe_ac_timer.expires = jiffies + HZ; ++ add_timer(&update_foe_ac_timer); ++ } else { ++ if (timer_pending(&update_foe_ac_timer)) ++ del_timer_sync(&update_foe_ac_timer); ++ } ++ } ++} ++ ++static void _MDrv_HWNAT_Clear_Bind_Entry(struct neighbour *neigh) ++{ ++ int hash_index, clear; ++ struct foe_entry *entry; ++ u32 * daddr = (u32 *)neigh->primary_key; ++ const u8 *addrtmp; ++ u8 mac0,mac1,mac2,mac3,mac4,mac5; ++ u32 dip; ++ dip = (u32)(*daddr); ++ clear = 0; ++ addrtmp = neigh->ha; ++ mac0 = (u8)(*addrtmp); ++ mac1 = (u8)(*(addrtmp+1)); ++ mac2 = (u8)(*(addrtmp+2)); ++ mac3 = (u8)(*(addrtmp+3)); ++ mac4 = (u8)(*(addrtmp+4)); ++ mac5 = (u8)(*(addrtmp+5)); ++ ++ for (hash_index = 0; hash_index < FOE_4TB_SIZ; hash_index++) { ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, hash_index); ++ if(entry->bfib1.state == BIND) { ++ /*NAT_PRINT("before old mac= %x:%x:%x:%x:%x:%x, new_dip=%x\n", ++ entry->ipv4_hnapt.dmac_hi[3], ++ entry->ipv4_hnapt.dmac_hi[2], ++ entry->ipv4_hnapt.dmac_hi[1], ++ entry->ipv4_hnapt.dmac_hi[0], ++ entry->ipv4_hnapt.dmac_lo[1], ++ entry->ipv4_hnapt.dmac_lo[0], entry->ipv4_hnapt.new_dip); ++ */ ++ if (entry->ipv4_hnapt.new_dip == ntohl(dip)) { ++ if ((entry->ipv4_hnapt.dmac_hi[3] != mac0) || ++ (entry->ipv4_hnapt.dmac_hi[2] != mac1) || ++ (entry->ipv4_hnapt.dmac_hi[1] != mac2) || ++ (entry->ipv4_hnapt.dmac_hi[0] != mac3) || ++ (entry->ipv4_hnapt.dmac_lo[1] != mac4) || ++ (entry->ipv4_hnapt.dmac_lo[0] != mac5)) { ++ NAT_PRINT("%s: state=%d\n",__func__,neigh->nud_state); ++ MHal_HWNAT_Set_Miss_Action(E_HWNAT_FOE_SEARCH_MISS_ONLY_FWD_CPU); ++ ++ entry->ipv4_hnapt.udib1.state = INVALID; ++ entry->ipv4_hnapt.udib1.time_stamp = MHAL_HWNAT_Get_TimeStamp() & 0xFF; ++ MHal_HWNAT_Enable_Cache(); ++ mod_timer(&hwnat_clear_entry_timer, jiffies + 3 * HZ); ++ ++ NAT_PRINT("delete old entry: dip =%x\n", ntohl(dip)); ++ ++ NAT_PRINT("old mac= %x:%x:%x:%x:%x:%x, dip=%x\n", ++ entry->ipv4_hnapt.dmac_hi[3], ++ entry->ipv4_hnapt.dmac_hi[2], ++ entry->ipv4_hnapt.dmac_hi[1], ++ entry->ipv4_hnapt.dmac_hi[0], ++ entry->ipv4_hnapt.dmac_lo[1], ++ entry->ipv4_hnapt.dmac_lo[0], ++ ntohl(dip)); ++ NAT_PRINT("new mac= %x:%x:%x:%x:%x:%x, dip=%x\n", mac0, mac1, mac2, mac3, mac4, mac5, ntohl(dip)); ++ ++ } ++ } ++ } ++ } ++} ++ ++static int MDrv_HWNAT_Handle_NetEvent(struct notifier_block *unused, unsigned long event, void *ptr) ++{ ++ struct net_device *dev = NULL; ++ struct neighbour *neigh = NULL; ++ int err = 0; ++ ++ switch (event) { ++ case NETEVENT_NEIGH_UPDATE: ++ neigh = ptr; ++ dev = neigh->dev; ++ if (dev) ++ _MDrv_HWNAT_Clear_Bind_Entry(neigh); ++ if (err) ++ HWNAT_MSG_ERR("failed to handle neigh update (err %d)\n", err); ++ break; ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++ ++ ++ ++ ++static int32_t _MDrv_HWNAT_Module_Init(void) ++{ ++ /*PPE Enabled: GMAC<->PPE<->CPU*/ ++ /*PPE Disabled: GMAC<->CPU*/ ++ struct mhal_hwnat_engine engine; ++ HWNAT_MSG_DBG("NOE HW NAT Module Enabled\n"); ++ ++ _hwnat_info.pdev = platform_device_alloc("HW_NAT", PLATFORM_DEVID_AUTO); ++ ++ if (!_hwnat_info.pdev) { ++ HWNAT_MSG_ERR("[%s][%d] NULL dev \n",__FUNCTION__,__LINE__); ++ return -ENOMEM; ++ } ++ _hwnat_info.pdev->dev.dma_mask = &hwnat_dmamask; ++ _hwnat_info.pdev->dev.coherent_dma_mask = 0xffffffff; ++ MDrv_NOE_NAT_Set_Dma_Ops(&_hwnat_info.pdev->dev, FALSE); ++ MDRV_HWNAT_CONFIG_SET_FEATURES(_hwnat_info); ++ MDRV_HWNAT_CONFIG_SET_TEST(_hwnat_info); ++ ++ MDrv_HWNAT_LOG_Init(&_hwnat_info); ++ /* Register ioctl handler */ ++ //MDrv_HWNAT_IOCTL_Init(&_hwnat_info); ++ /* Set PPE FOE Hash Mode */ ++ if (!_MDrv_HWNAT_Init_Hash_Mode(&_hwnat_info)) { ++ HWNAT_MSG_ERR("memory allocation failed\n"); ++ return -ENOMEM; /* memory allocation failed */ ++ } ++ ++ /* Get net_device structure of Dest Port */ ++ _MDrv_HWNAT_Set_Dst_Port(1); ++ ++ /* Register ioctl handler */ ++ MDrv_HWNAT_IOCTL_Register_Handler(); ++ ++ MHal_HWNAT_Map_ForcePort(); ++ MHal_HWNAT_Set_Pkt_Prot(); ++ MHal_HWNAT_Enable_Cache(); ++ MHal_HWNAT_Check_Switch_Vlan(FALSE); ++ _MDrv_HWNAT_Set_Ac_Update(1); ++ /* Initialize PPE related register */ ++ engine.rate.bind_rate = DFL_FOE_BNDR; ++ engine.rate.tbl_read_rate = DFL_PBND_RD_PRD; ++ engine.ka.cfg = DFL_FOE_KA; ++ engine.ka.udp = DFL_FOE_TCP_KA; ++ engine.ka.tcp = DFL_FOE_UDP_KA; ++ engine.ka.ntu = DFL_FOE_NTU_KA; ++ engine.ka.pbnd_limit = DFL_PBND_RD_LMT; ++ engine.age_out.udp_time = DFL_FOE_UDP_DLTA; ++ engine.age_out.tcp_time = DFL_FOE_TCP_DLTA; ++ engine.age_out.fin_time = DFL_FOE_FIN_DLTA; ++ engine.age_out.ntu_time = DFL_FOE_NTU_DLTA; ++ engine.age_out.unb_time = DFL_FOE_UNB_DLTA; ++ engine.age_out.unb_pkt_cnt = DFL_FOE_UNB_MNP; ++ ++ MHal_HWNAT_Start_Engine(&engine); ++ /* In manual mode, PPE always reports UN-HIT CPU reason, so we don't need to process it */ ++ /* Register RX/TX hook point */ ++ if ((_hwnat_info.features & HW_NAT_MANUAL_MODE) == 0x0) { ++ noe_nat_hook_tx = MDrv_HWNAT_Handle_Tx; ++ noe_nat_hook_rx = MDrv_HWNAT_Handle_Rx; ++ } ++ ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) { ++ ppe_dev_register_hook = _MDrv_HWNAT_Regist_Dev_Handler; ++ ppe_dev_unregister_hook = _MDrv_HWNAT_Unregist_Dev_Handler; ++ } ++ /* Set GMAC fowrards packet to PPE */ ++ MHal_HWNAT_Set_Pkt_Dst(E_NOE_GE_MAC1, E_HWNAT_PKT_DST_ENGINE); ++ MHal_HWNAT_Set_Pkt_Dst(E_NOE_GE_MAC2, E_HWNAT_PKT_DST_ENGINE); ++ ++ if (_hwnat_info.features & PPTP_L2TP) { ++ MDrv_HWNAT_Pptp_L2tp_Init(); ++ } ++ register_netevent_notifier(&Hnat_netevent_nb); ++ init_timer(&hwnat_clear_entry_timer); ++ hwnat_clear_entry_timer.function = _MDrv_HWNAT_Clear_Entry ; ++ return 0; ++} ++ ++static void _MDrv_HWNAT_Module_Exit(void) ++{ ++ HWNAT_MSG_DBG("Ralink HW NAT Module Disabled\n"); ++ ++ /* Set GMAC fowrards packet to CPU */ ++ MHal_HWNAT_Set_Pkt_Dst(E_NOE_GE_MAC1, E_HWNAT_PKT_DST_CPU); ++ MHal_HWNAT_Set_Pkt_Dst(E_NOE_GE_MAC2, E_HWNAT_PKT_DST_CPU); ++ ++ /* Unregister RX/TX hook point */ ++ noe_nat_hook_rx = NULL; ++ noe_nat_hook_tx = NULL; ++ if (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH) { ++ ppe_dev_register_hook = NULL; ++ ppe_dev_unregister_hook = NULL; ++ } ++ ++ /* Restore PPE related register */ ++ /* ppe_eng_stop(); */ ++ /* iounmap(ppe_foe_base); */ ++ ++ /* Unregister ioctl handler */ ++ MDrv_HWNAT_IOCTL_Unregister_Handler(); ++ MHal_HWNAT_Check_Switch_Vlan(1); ++ _MDrv_HWNAT_Set_Ac_Update(0); ++ ++ if (IS_QDMA_MCAST_SUPPORT(_hwnat_info.features)) { ++ MDrv_HWNAT_Mcast_Delete_All(); ++ } ++ ++ /* Release net_device structure of Dest Port */ ++ _MDrv_HWNAT_Set_Dst_Port(0); ++ ++ if (_hwnat_info.features & PPTP_L2TP) { ++ MDrv_HWNAT_Pptp_L2tp_Clean(); ++ } ++ unregister_netevent_notifier(&Hnat_netevent_nb); ++} ++ ++module_init(_MDrv_HWNAT_Module_Init); ++module_exit(_MDrv_HWNAT_Module_Exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("HWNAT\n"); +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat.h +new file mode 100755 +index 000000000000..c38e4e147e08 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat.h +@@ -0,0 +1,404 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_NAT.h ++/// @brief NOE NAT Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_NOE_HWNAT_H_ ++#define _MDRV_NOE_HWNAT_H_ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mdrv_hwnat_config.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++#define hwnat_vlan_tx_tag_present(__skb) ((__skb)->vlan_tci & VLAN_TAG_PRESENT) ++#define hwnat_vlan_tag_get(__skb) ((__skb)->vlan_tci & ~VLAN_TAG_PRESENT) ++ ++enum foe_cpu_reason { ++ TTL_0 = 0x02, /* IPv4(IPv6) TTL(hop limit) = 0 */ ++ HAS_OPTION_HEADER = 0x03, /* IPv4(IPv6) has option(extension) header */ ++ NO_FLOW_IS_ASSIGNED = 0x07, /* No flow is assigned */ ++ IPV4_WITH_FRAGMENT = 0x08, /* IPv4 HNAT doesn't support IPv4 /w fragment */ ++ IPV4_HNAPT_DSLITE_WITH_FRAGMENT = 0x09, /* IPv4 HNAPT/DS-Lite doesn't support IPv4 /w fragment */ ++ IPV4_HNAPT_DSLITE_WITHOUT_TCP_UDP = 0x0A, /* IPv4 HNAPT/DS-Lite can't find TCP/UDP sport/dport */ ++ IPV6_5T_6RD_WITHOUT_TCP_UDP = 0x0B, /* IPv6 5T-route/6RD can't find TCP/UDP sport/dport */ ++ TCP_FIN_SYN_RST = 0x0C, /* Ingress packet is TCP fin/syn/rst (for IPv4 NAPT/DS-Lite or IPv6 5T-route/6RD) */ ++ UN_HIT = 0x0D, /* FOE Un-hit */ ++ HIT_UNBIND = 0x0E, /* FOE Hit unbind */ ++ HIT_UNBIND_RATE_REACH = 0x0F, /* FOE Hit unbind & rate reach */ ++ HIT_BIND_TCP_FIN = 0x10, /* Hit bind PPE TCP FIN entry */ ++ HIT_BIND_TTL_1 = 0x11, /* Hit bind PPE entry and TTL(hop limit) = 1 and TTL(hot limit) - 1 */ ++ HIT_BIND_WITH_VLAN_VIOLATION = 0x12, /* Hit bind and VLAN replacement violation (Ingress 1(0) VLAN layers and egress 4(3 or 4) VLAN layers) */ ++ HIT_BIND_KEEPALIVE_UC_OLD_HDR = 0x13, /* Hit bind and keep alive with unicast old-header packet */ ++ HIT_BIND_KEEPALIVE_MC_NEW_HDR = 0x14, /* Hit bind and keep alive with multicast new-header packet */ ++ HIT_BIND_KEEPALIVE_DUP_OLD_HDR = 0x15, /* Hit bind and keep alive with duplicate old-header packet */ ++ HIT_BIND_FORCE_TO_CPU = 0x16, /* FOE Hit bind & force to CPU */ ++ HIT_BIND_WITH_OPTION_HEADER = 0x17, /* Hit bind and remove tunnel IP header, but inner IP has option/next header */ ++ HIT_BIND_EXCEED_MTU = 0x1C, /* Hit bind and exceed MTU */ ++ HIT_BIND_PACKET_SAMPLING = 0x1B, /* PS packet */ ++ HIT_BIND_MULTICAST_TO_CPU = 0x18, /* Switch clone multicast packet to CPU */ ++ HIT_BIND_MULTICAST_TO_GMAC_CPU = 0x19, /* Switch clone multicast packet to GMAC1 & CPU */ ++ HIT_PRE_BIND = 0x1A /* Pre-bind */ ++}; ++ ++ ++ ++enum dst_port_num { ++ DP_RA0 = 11, ++ DP_RA1 = 12, ++ DP_RA2 = 13, ++ DP_RA3 = 14, ++ DP_RA4 = 15, ++ DP_RA5 = 16, ++ DP_RA6 = 17, ++ DP_RA7 = 18, ++ DP_RA8 = 19, ++ DP_RA9 = 20, ++ DP_RA10 = 21, ++ DP_RA11 = 22, ++ DP_RA12 = 23, ++ DP_RA13 = 24, ++ DP_RA14 = 25, ++ DP_RA15 = 26, ++ DP_WDS0 = 27, ++ DP_WDS1 = 28, ++ DP_WDS2 = 29, ++ DP_WDS3 = 30, ++ DP_APCLI0 = 31, ++ DP_MESH0 = 32, ++ DP_RAI0 = 33, ++ DP_RAI1 = 34, ++ DP_RAI2 = 35, ++ DP_RAI3 = 36, ++ DP_RAI4 = 37, ++ DP_RAI5 = 38, ++ DP_RAI6 = 39, ++ DP_RAI7 = 40, ++ DP_RAI8 = 41, ++ DP_RAI9 = 42, ++ DP_RAI10 = 43, ++ DP_RAI11 = 44, ++ DP_RAI12 = 45, ++ DP_RAI13 = 46, ++ DP_RAI14 = 47, ++ DP_RAI15 = 48, ++ DP_WDSI0 = 49, ++ DP_WDSI1 = 50, ++ DP_WDSI2 = 51, ++ DP_WDSI3 = 52, ++ DP_APCLII0 = 53, ++ DP_MESHI0 = 54, ++ MAX_WIFI_IF_NUM = 59, ++ DP_GMAC = 60, ++ DP_GMAC2 = 61, ++ DP_PCI = 62, ++ DP_USB = 63, ++ MAX_IF_NUM ++}; ++ ++struct pdma_rx_desc_info4 { ++ u16 MAGIC_TAG_PROTECT; ++ uint32_t foe_entry_num:14; ++ uint32_t CRSN:5; ++ uint32_t SPORT:4; ++ uint32_t ALG:1; ++ uint16_t IF:8; ++ u8 WDMAID; ++ uint16_t RXID:2; ++ uint16_t WCID:8; ++ uint16_t BSSID:6; ++ u16 SOURCE; ++ u16 DEST; ++} __packed; ++ ++struct head_rx_descinfo4 { ++ uint32_t foe_entry_num:14; ++ uint32_t CRSN:5; ++ uint32_t SPORT:4; ++ uint32_t ALG:1; ++ uint32_t IF:8; ++ u16 MAGIC_TAG_PROTECT; ++ u8 WDMAID; ++ uint16_t RXID:2; ++ uint16_t WCID:8; ++ uint16_t BSSID:6; ++ u16 SOURCE; ++ u16 DEST; ++} __packed; ++ ++struct cb_rx_desc_info4 { ++ u16 MAGIC_TAG_PROTECT0; ++ uint32_t foe_entry_num:14; ++ uint32_t CRSN:5; ++ uint32_t SPORT:4; ++ uint32_t ALG:1; ++ uint32_t IF:8; ++ u16 MAGIC_TAG_PROTECT1; ++ u8 WDMAID; ++ uint16_t RXID:2; ++ uint16_t WCID:8; ++ uint16_t BSSID:6; ++ u16 SOURCE; ++ u16 DEST; ++} __packed; ++ ++#ifndef NEXTHDR_IPIP ++#define NEXTHDR_IPIP (4) ++#endif /* NEXTHDR_IPIP */ ++ ++#define FOE_MAGIC_PCI (0x73) ++#define FOE_MAGIC_WLAN (0x74) ++#define FOE_MAGIC_GE (0x75) ++#define FOE_MAGIC_PPE (0x76) ++#define TAG_PROTECT (0x6789) ++#define USE_HEAD_ROOM (0) ++#define USE_TAIL_ROOM (1) ++#define USE_CB (2) ++#define ALL_INFO_ERROR (3) ++ ++ ++#define FOE_TAG_PROTECT(skb) (((struct head_rx_descinfo4 *)((skb)->head))->MAGIC_TAG_PROTECT) ++#define FOE_ENTRY_NUM(skb) (((struct head_rx_descinfo4 *)((skb)->head))->foe_entry_num) ++#define FOE_ALG(skb) (((struct head_rx_descinfo4 *)((skb)->head))->ALG) ++#define FOE_AI(skb) (((struct head_rx_descinfo4 *)((skb)->head))->CRSN) ++#define FOE_SP(skb) (((struct head_rx_descinfo4 *)((skb)->head))->SPORT) ++#define FOE_MAGIC_TAG(skb) (((struct head_rx_descinfo4 *)((skb)->head))->IF) ++#define FOE_WDMA_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->RXID) ++#define FOE_WC_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->BSSID) ++#define FOE_SOURCE(skb) (((struct head_rx_descinfo4 *)((skb)->head))->SOURCE) ++#define FOE_DEST(skb) (((struct head_rx_descinfo4 *)((skb)->head))->DEST) ++ ++#define IS_SPACE_AVAILABLED_HEAD(skb) ((((skb_headroom(skb) >= FOE_INFO_LEN) ? 1 : 0))) ++#define IS_SPACE_AVAILABLE_HEAD(skb) ((((skb_headroom(skb) >= FOE_INFO_LEN) ? 1 : 0))) ++#define FOE_INFO_START_ADDR_HEAD(skb) (skb->head) ++ ++#define FOE_TAG_PROTECT_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->MAGIC_TAG_PROTECT) ++#define FOE_ENTRY_NUM_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->foe_entry_num) ++#define FOE_ALG_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->ALG) ++#define FOE_AI_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->CRSN) ++#define FOE_SP_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->SPORT) ++#define FOE_MAGIC_TAG_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->IF) ++ ++#define FOE_WDMA_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->RXID) ++#define FOE_WC_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->BSSID) ++ ++#define FOE_SOURCE_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->SOURCE) ++#define FOE_DEST_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->DEST) ++#define IS_SPACE_AVAILABLED_TAIL(skb) (((skb_tailroom(skb) >= FOE_INFO_LEN) ? 1 : 0)) ++#define IS_SPACE_AVAILABLE_TAIL(skb) (((skb_tailroom(skb) >= FOE_INFO_LEN) ? 1 : 0)) ++#define FOE_INFO_START_ADDR_TAIL(skb) ((unsigned char *)(long)(skb_end_pointer(skb) - FOE_INFO_LEN)) ++ ++#define FOE_TAG_PROTECT_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->MAGIC_TAG_PROTECT) ++#define FOE_ENTRY_NUM_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->foe_entry_num) ++#define FOE_ALG_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->ALG) ++#define FOE_AI_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->CRSN) ++#define FOE_SP_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->SPORT) ++#define FOE_MAGIC_TAG_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->IF) ++ ++#define FOE_SOURCE_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->SOURCE) ++#define FOE_DEST_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->DEST) ++ ++#define FOE_WDMA_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->RXID) ++#define FOE_WC_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->BSSID) ++ ++/* change the position of skb_CB if necessary */ ++#define CB_OFFSET (40) ++#define IS_SPACE_AVAILABLE_CB(skb) (1) ++#define FOE_INFO_START_ADDR_CB(skb) (skb->cb + CB_OFFSET) ++#define FOE_TAG_PROTECT_CB0(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->MAGIC_TAG_PROTECT0) ++#define FOE_TAG_PROTECT_CB1(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->MAGIC_TAG_PROTECT1) ++#define FOE_ENTRY_NUM_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->foe_entry_num) ++#define FOE_ALG_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->ALG) ++#define FOE_AI_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->CRSN) ++#define FOE_SP_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->SPORT) ++#define FOE_MAGIC_TAG_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->IF) ++ ++#if defined(CONFIG_NOE_HW_NAT_PPTP_L2TP) ++#define FOE_SOURCE_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->SOURCE) ++#define FOE_DEST_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->cb + CB_OFFSET))->DEST) ++#endif ++ ++ ++#define FOE_WDMA_ID_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->head))->RXID) ++#define FOE_WC_ID_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID_CB(skb) (((struct cb_rx_desc_info4 *)((skb)->head))->BSSID) ++ ++#define IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb) (FOE_TAG_PROTECT_HEAD(skb) == TAG_PROTECT) ++#define IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb) (FOE_TAG_PROTECT_TAIL(skb) == TAG_PROTECT) ++#define IS_MAGIC_TAG_PROTECT_VALID_CB(skb) ((FOE_TAG_PROTECT_CB0(skb) == TAG_PROTECT) && (FOE_TAG_PROTECT_CB0(skb) == FOE_TAG_PROTECT_CB1(skb))) ++ ++#define IS_IF_PCIE_WLAN_HEAD(skb) ((FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PCI) || (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_WLAN) || (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_GE)) ++#define IS_IF_PCIE_WLAN_TAIL(skb) ((FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PCI) || (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_WLAN)) ++#define IS_IF_PCIE_WLAN_CB(skb) ((FOE_MAGIC_TAG_CB(skb) == FOE_MAGIC_PCI) || (FOE_MAGIC_TAG_CB(skb) == FOE_MAGIC_WLAN)) ++ ++ ++ ++#define FOE_SOURCE(skb) (((struct head_rx_descinfo4 *)((skb)->head))->SOURCE) ++#define FOE_DEST(skb) (((struct head_rx_descinfo4 *)((skb)->head))->DEST) ++#define FOE_SOURCE_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->SOURCE) ++#define FOE_DEST_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->DEST) ++#define FOE_SOURCE_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->SOURCE) ++#define FOE_DEST_TAIL(skb) (((struct pdma_rx_desc_info4 *)((long)((skb_end_pointer(skb)) - FOE_INFO_LEN)))->DEST) ++ ++ ++ ++#define FOE_WDMA_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->RXID) ++#define FOE_WC_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID(skb) (((struct head_rx_descinfo4 *)((skb)->head))->BSSID) ++ ++#define FOE_WDMA_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->RXID) ++#define FOE_WC_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID_HEAD(skb) (((struct head_rx_descinfo4 *)((skb)->head))->BSSID) ++ ++#define FOE_WDMA_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->WDMAID) ++#define FOE_RX_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->RXID) ++#define FOE_WC_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->WCID) ++#define FOE_BSS_ID_TAIL(skb) (((struct pdma_rx_desc_info4 *)((skb)->head))->BSSID) ++ ++ ++ ++/* macros */ ++#define magic_tag_set_zero(skb) \ ++{ \ ++ if ((FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PCI) || (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_WLAN) || (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_GE)) { \ ++ if (IS_SPACE_AVAILABLE_HEAD(skb)) \ ++ FOE_MAGIC_TAG_HEAD(skb) = 0; \ ++ } \ ++ if ((FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PCI) || (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_WLAN) || (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_GE)) { \ ++ if (IS_SPACE_AVAILABLE_TAIL(skb)) \ ++ FOE_MAGIC_TAG_TAIL(skb) = 0; \ ++ } \ ++} ++ ++ ++ ++#define FOE_ENTRY_BASE_BY_PKT(base, skb) (&((struct foe_entry *)base)[FOE_ENTRY_NUM(skb)]) ++#define FOE_ENTRY_BASE_BY_IDX(base, idx) (&((struct foe_entry *)base)[idx]) ++#define PS_ENTRY_BASE_BY_PKT(base, skb) (&((struct ps_entry *)base)[FOE_ENTRY_NUM(skb)]) ++#define PS_ENTRY_BASE_BY_IDX(base, idx) (&((struct ps_entry *)base)[idx]) ++#define MIB_ENTRY_BASE_BY_PKT(base, skb) (&((struct mib_entry *)base)[FOE_ENTRY_NUM(skb)]) ++#define MIB_ENTRY_BASE_BY_IDX(base, idx) (&((struct mib_entry *)base)[idx]) ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++ ++#if defined(CONFIG_NOE_NAT_HW) ++void MDrv_NOE_NAT_Set_Magic_Tag_Zero(struct sk_buff *skb); ++void MDrv_NOE_NAT_Check_Magic_Tag(struct sk_buff *skb); ++void MDrv_NOE_NAT_Set_Headroom_Zero(struct sk_buff *skb); ++void MDrv_NOE_NAT_Set_Tailroom_Zero(struct sk_buff *skb); ++void MDrv_NOE_NAT_Copy_Headroom(u8 *data, struct sk_buff *skb); ++void MDrv_NOE_NAT_Copy_Tailroom(u8 *data, int size, struct sk_buff *skb); ++#else ++static inline void MDrv_NOE_NAT_Set_Magic_Tag_Zero(struct sk_buff *skb) {} ++static inline void MDrv_NOE_NAT_Check_Magic_Tag(struct sk_buff *skb) {} ++static inline void MDrv_NOE_NAT_Set_Headroom_Zero(struct sk_buff *skb) {} ++static inline void MDrv_NOE_NAT_Set_Tailroom_Zero(struct sk_buff *skb) {} ++static inline void MDrv_NOE_NAT_Copy_Headroom(u8 *data, struct sk_buff *skb) {} ++static inline void MDrv_NOE_NAT_Copy_Tailroom(u8 *data, int size, struct sk_buff *skb) {} ++#endif /* CONFIG_NOE_NAT_HW */ ++ ++ ++ ++static inline void MDrv_NOE_NAT_Set_L2tp_Unhit(struct iphdr *iph, struct sk_buff *skb) ++{ ++#if PPTP_L2TP ++ /* only clear headeroom for TCP OR not L2TP packets */ ++ if ((iph->protocol == 0x6) || (ntohs(udp_hdr(skb)->dest) != 1701)) { ++ if (IS_SPACE_AVAILABLED_HEAD(skb)) { ++ FOE_MAGIC_TAG(skb) = 0; ++ FOE_AI(skb) = UN_HIT; ++ } ++ } ++#endif ++} ++ ++static inline void MDrv_NOE_NAT_Set_L2tp_Fast_Path(u32 l2tp_fast_path, u32 pptp_fast_path) ++{ ++#if PPTP_L2TP ++ l2tp_fast_path = 1; ++ pptp_fast_path = 0; ++#endif ++} ++ ++static inline void MDrv_NOE_NAT_Clear_L2tp_Fast_Path(u32 l2tp_fast_path) ++{ ++#if PPTP_L2TP ++ l2tp_fast_path = 0; ++#endif ++} ++ ++ ++ ++struct HWNAT_DEVICE { ++ struct platform_device *pdev; ++ dma_addr_t ppe_phy_foe_base; ++ void *ppe_foe_base; //struct foe_entry * ++ dma_addr_t ppe_phy_ps_base; ++ void *ppe_ps_base; //struct ps_entry * ++ dma_addr_t ppe_phy_mib_base; ++ void *ppe_mib_base; //struct mib_entry * ++ uint64_t features; ++ u8 test; ++ u32 table_entries; ++ int fast_bind; ++ u8 hash_cnt; ++ int DP_GMAC1; ++ int DPORT_GMAC2; ++ u8 hash_mode; ++ u8 hash_debug; ++ u32 foe_tbl_size; ++ u32 ps_tbl_size; ++ u32 mib_tbl_size; ++ uint16_t lan_vid; ++ uint16_t wan_vid; ++ unsigned char bind_dir; ++ int debug_level; ++ u8 log_level; ++}; ++ ++ ++extern struct HWNAT_DEVICE _hwnat_info; ++extern struct net_device *dst_port[MAX_IF_NUM]; ++extern u32 pptp_fast_path; ++extern u32 l2tp_fast_path; ++extern int (*noe_nat_hook_rx)(struct sk_buff *skb); ++extern int (*noe_nat_hook_tx)(struct sk_buff *skb, int gmac_no); ++extern void (*ppe_dev_register_hook)(struct net_device *dev); ++extern void (*ppe_dev_unregister_hook)(struct net_device *dev); ++ ++#endif /* _MDRV_NOE_HWNAT_H_ */ ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_api.c b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_api.c +new file mode 100755 +index 000000000000..cf7c0f0c7ba1 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_api.c +@@ -0,0 +1,451 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_HWNAT_API.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_hwnat.h" ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_util.h" ++#include "mdrv_hwnat_ioctl.h" ++#include "mdrv_hwnat_api.h" ++#include "mdrv_hwnat_define.h" ++#include "mdrv_hwnat_log.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Variable and Functions ++//-------------------------------------------------------------------------------------------------- ++extern struct foe_entry *ppe_foe_base; ++ ++int _MDrv_HWNAT_Get_Ipv6_Hash(struct foe_pri_key *key, struct foe_entry *entry, int del) ++{ ++ uint32_t t_hvt_31, t_hvt_63, t_hvt_95, t_hvt_sd; ++ uint32_t t_hvt_sd_23, t_hvt_sd_31_24, t_hash_32, t_hashs_16, t_ha16k, hash_index; ++ uint32_t ppeSaddr_127_96, ppeSaddr_95_64, ppeSaddr_63_32, ppeSaddr_31_0; ++ uint32_t ppeDaddr_127_96, ppeDaddr_95_64, ppeDaddr_63_32, ppeDaddr_31_0; ++ uint32_t ipv6_sip_127_96, ipv6_sip_95_64, ipv6_sip_63_32, ipv6_sip_31_0; ++ uint32_t ipv6_dip_127_96, ipv6_dip_95_64, ipv6_dip_63_32, ipv6_dip_31_0; ++ uint32_t sport, dport, ppeSportV6, ppeDportV6; ++ ++ ipv6_sip_127_96 = key->ipv6_routing.sip0; ++ ipv6_sip_95_64 = key->ipv6_routing.sip1; ++ ipv6_sip_63_32 = key->ipv6_routing.sip2; ++ ipv6_sip_31_0 = key->ipv6_routing.sip3; ++ ipv6_dip_127_96 = key->ipv6_routing.dip0; ++ ipv6_dip_95_64 = key->ipv6_routing.dip1; ++ ipv6_dip_63_32 = key->ipv6_routing.dip2; ++ ipv6_dip_31_0 = key->ipv6_routing.dip3; ++ sport = key->ipv6_routing.sport; ++ dport = key->ipv6_routing.dport; ++ ++ t_hvt_31 = ipv6_sip_31_0 ^ ipv6_dip_31_0 ^ (sport << 16 | dport); ++ t_hvt_63 = ipv6_sip_63_32 ^ ipv6_dip_63_32 ^ ipv6_dip_127_96; ++ t_hvt_95 = ipv6_sip_95_64 ^ ipv6_dip_95_64 ^ ipv6_sip_127_96; ++ if (DFL_FOE_HASH_MODE == 1) // hash mode 1 ++ t_hvt_sd = (t_hvt_31 & t_hvt_63) | ((~t_hvt_31) & t_hvt_95); ++ else // hash mode 2 ++ t_hvt_sd = t_hvt_63 ^ ( t_hvt_31 & (~t_hvt_95)); ++ ++ t_hvt_sd_23 = t_hvt_sd & 0xffffff; ++ t_hvt_sd_31_24 = t_hvt_sd & 0xff000000; ++ t_hash_32 = t_hvt_31 ^ t_hvt_63 ^ t_hvt_95 ^ ( (t_hvt_sd_23 << 8) | (t_hvt_sd_31_24 >> 24)); ++ t_hashs_16 = ((t_hash_32 & 0xffff0000) >> 16 ) ^ (t_hash_32 & 0xfffff); ++ ++ if (FOE_4TB_SIZ == 16384) ++ t_ha16k = t_hashs_16 & 0x1fff; // FOE_16k ++ else if (FOE_4TB_SIZ == 8192) ++ t_ha16k = t_hashs_16 & 0xfff; // FOE_8k ++ else if (FOE_4TB_SIZ == 4096) ++ t_ha16k = t_hashs_16 & 0x7ff; // FOE_4k ++ else if (FOE_4TB_SIZ == 2048) ++ t_ha16k = t_hashs_16 & 0x3ff; // FOE_2k ++ else ++ t_ha16k = t_hashs_16 & 0x1ff; // FOE_1k ++ hash_index = (uint32_t)t_ha16k *2; ++ ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr_127_96 = entry->ipv6_5t_route.ipv6_sip0; ++ ppeSaddr_95_64 = entry->ipv6_5t_route.ipv6_sip1; ++ ppeSaddr_63_32 = entry->ipv6_5t_route.ipv6_sip2; ++ ppeSaddr_31_0 = entry->ipv6_5t_route.ipv6_sip3; ++ ++ ppeDaddr_127_96 = entry->ipv6_5t_route.ipv6_dip0; ++ ppeDaddr_95_64 = entry->ipv6_5t_route.ipv6_dip1; ++ ppeDaddr_63_32 = entry->ipv6_5t_route.ipv6_dip2; ++ ppeDaddr_31_0 = entry->ipv6_5t_route.ipv6_dip3; ++ ++ ppeSportV6 = entry->ipv6_5t_route.sport; ++ ppeDportV6 = entry->ipv6_5t_route.dport; ++ if (del !=1) { ++ if (entry->ipv6_5t_route.bfib1.state == BIND) ++ { ++ NAT_PRINT("IPV6 Hash collision, hash index +1\n"); ++ hash_index = hash_index + 1; ++ entry = &ppe_foe_base[hash_index]; ++ } ++ if (entry->ipv6_5t_route.bfib1.state == BIND) ++ { ++ NAT_PRINT("IPV6 Hash collision can not bind\n"); ++ return -1; ++ } ++ }else if(del == 1) { ++ if ((ipv6_sip_127_96 == ppeSaddr_127_96) && (ipv6_sip_95_64 == ppeSaddr_95_64) ++ && (ipv6_sip_63_32 == ppeSaddr_63_32) && (ipv6_sip_31_0 == ppeSaddr_31_0) && ++ (ipv6_dip_127_96 == ppeDaddr_127_96) && (ipv6_dip_95_64 == ppeDaddr_95_64) ++ && (ipv6_dip_63_32 == ppeDaddr_63_32) && (ipv6_dip_31_0 == ppeDaddr_31_0) && ++ (sport == ppeSportV6) && (dport == ppeDportV6)) { ++ } else { ++ hash_index = hash_index + 1; ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr_127_96 = entry->ipv6_5t_route.ipv6_sip0; ++ ppeSaddr_95_64 = entry->ipv6_5t_route.ipv6_sip1; ++ ppeSaddr_63_32 = entry->ipv6_5t_route.ipv6_sip2; ++ ppeSaddr_31_0 = entry->ipv6_5t_route.ipv6_sip3; ++ ++ ppeDaddr_127_96 = entry->ipv6_5t_route.ipv6_dip0; ++ ppeDaddr_95_64 = entry->ipv6_5t_route.ipv6_dip1; ++ ppeDaddr_63_32 = entry->ipv6_5t_route.ipv6_dip2; ++ ppeDaddr_31_0 = entry->ipv6_5t_route.ipv6_dip3; ++ ++ ppeSportV6 = entry->ipv6_5t_route.sport; ++ ppeDportV6 = entry->ipv6_5t_route.dport; ++ if ((ipv6_sip_127_96 == ppeSaddr_127_96) && (ipv6_sip_95_64 == ppeSaddr_95_64) ++ && (ipv6_sip_63_32 == ppeSaddr_63_32) && (ipv6_sip_31_0 == ppeSaddr_31_0) && ++ (ipv6_dip_127_96 == ppeDaddr_127_96) && (ipv6_dip_95_64 == ppeDaddr_95_64) ++ && (ipv6_dip_63_32 == ppeDaddr_63_32) && (ipv6_dip_31_0 == ppeDaddr_31_0) && ++ (sport == ppeSportV6) && (dport == ppeDportV6)) { ++ } else { ++ if (_hwnat_info.features & HW_NAT_SEMI_AUTO_MODE) ++ NAT_PRINT("Ipv6 Entry delete : Entry Not found\n"); ++ else if (_hwnat_info.features & HW_NAT_MANUAL_MODE) ++ NAT_PRINT("Ipv6 hash collision hwnat can not found\n"); ++ return -1; ++ } ++ } ++ ++ } ++ return hash_index; ++} ++ ++int _MDrv_HWNAT_Get_Ipv6_Mib_Hash(struct foe_pri_key *key, struct foe_entry *entry) ++{ ++ uint32_t t_hvt_31, t_hvt_63, t_hvt_95, t_hvt_sd; ++ uint32_t t_hvt_sd_23, t_hvt_sd_31_24, t_hash_32, t_hashs_16, t_ha16k, hash_index; ++ uint32_t ppeSaddr_127_96, ppeSaddr_95_64, ppeSaddr_63_32, ppeSaddr_31_0; ++ uint32_t ppeDaddr_127_96, ppeDaddr_95_64, ppeDaddr_63_32, ppeDaddr_31_0; ++ uint32_t ipv6_sip_127_96, ipv6_sip_95_64, ipv6_sip_63_32, ipv6_sip_31_0; ++ uint32_t ipv6_dip_127_96, ipv6_dip_95_64, ipv6_dip_63_32, ipv6_dip_31_0; ++ uint32_t sport, dport, ppeSportV6, ppeDportV6; ++ ++ ipv6_sip_127_96 = key->ipv6_routing.sip0; ++ ipv6_sip_95_64 = key->ipv6_routing.sip1; ++ ipv6_sip_63_32 = key->ipv6_routing.sip2; ++ ipv6_sip_31_0 = key->ipv6_routing.sip3; ++ ipv6_dip_127_96 = key->ipv6_routing.dip0; ++ ipv6_dip_95_64 = key->ipv6_routing.dip1; ++ ipv6_dip_63_32 = key->ipv6_routing.dip2; ++ ipv6_dip_31_0 = key->ipv6_routing.dip3; ++ sport = key->ipv6_routing.sport; ++ dport = key->ipv6_routing.dport; ++ ++ t_hvt_31 = ipv6_sip_31_0 ^ ipv6_dip_31_0 ^ (sport << 16 | dport); ++ t_hvt_63 = ipv6_sip_63_32 ^ ipv6_dip_63_32 ^ ipv6_dip_127_96; ++ t_hvt_95 = ipv6_sip_95_64 ^ ipv6_dip_95_64 ^ ipv6_sip_127_96; ++ if (DFL_FOE_HASH_MODE == 1) // hash mode 1 ++ t_hvt_sd = (t_hvt_31 & t_hvt_63) | ((~t_hvt_31) & t_hvt_95); ++ else // hash mode 2 ++ t_hvt_sd = t_hvt_63 ^ ( t_hvt_31 & (~t_hvt_95)); ++ ++ t_hvt_sd_23 = t_hvt_sd & 0xffffff; ++ t_hvt_sd_31_24 = t_hvt_sd & 0xff000000; ++ t_hash_32 = t_hvt_31 ^ t_hvt_63 ^ t_hvt_95 ^ ( (t_hvt_sd_23 << 8) | (t_hvt_sd_31_24 >> 24)); ++ t_hashs_16 = ((t_hash_32 & 0xffff0000) >> 16 ) ^ (t_hash_32 & 0xfffff); ++ ++ if (FOE_4TB_SIZ == 16384) ++ t_ha16k = t_hashs_16 & 0x1fff; // FOE_16k ++ else if (FOE_4TB_SIZ == 8192) ++ t_ha16k = t_hashs_16 & 0xfff; // FOE_8k ++ else if (FOE_4TB_SIZ == 4096) ++ t_ha16k = t_hashs_16 & 0x7ff; // FOE_4k ++ else if (FOE_4TB_SIZ == 2048) ++ t_ha16k = t_hashs_16 & 0x3ff; // FOE_2k ++ else ++ t_ha16k = t_hashs_16 & 0x1ff; // FOE_1k ++ hash_index = (uint32_t)t_ha16k *2; ++ ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr_127_96 = entry->ipv6_5t_route.ipv6_sip0; ++ ppeSaddr_95_64 = entry->ipv6_5t_route.ipv6_sip1; ++ ppeSaddr_63_32 = entry->ipv6_5t_route.ipv6_sip2; ++ ppeSaddr_31_0 = entry->ipv6_5t_route.ipv6_sip3; ++ ++ ppeDaddr_127_96 = entry->ipv6_5t_route.ipv6_dip0; ++ ppeDaddr_95_64 = entry->ipv6_5t_route.ipv6_dip1; ++ ppeDaddr_63_32 = entry->ipv6_5t_route.ipv6_dip2; ++ ppeDaddr_31_0 = entry->ipv6_5t_route.ipv6_dip3; ++ ++ ppeSportV6 = entry->ipv6_5t_route.sport; ++ ppeDportV6 = entry->ipv6_5t_route.dport; ++ ++ if ((ipv6_sip_127_96 == ppeSaddr_127_96) && (ipv6_sip_95_64 == ppeSaddr_95_64) ++ && (ipv6_sip_63_32 == ppeSaddr_63_32) && (ipv6_sip_31_0 == ppeSaddr_31_0) && ++ (ipv6_dip_127_96 == ppeDaddr_127_96) && (ipv6_dip_95_64 == ppeDaddr_95_64) ++ && (ipv6_dip_63_32 == ppeDaddr_63_32) && (ipv6_dip_31_0 == ppeDaddr_31_0) && ++ (sport == ppeSportV6) && (dport == ppeDportV6)) { ++ return hash_index; ++ } else { ++ hash_index = hash_index + 1; ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr_127_96 = entry->ipv6_5t_route.ipv6_sip0; ++ ppeSaddr_95_64 = entry->ipv6_5t_route.ipv6_sip1; ++ ppeSaddr_63_32 = entry->ipv6_5t_route.ipv6_sip2; ++ ppeSaddr_31_0 = entry->ipv6_5t_route.ipv6_sip3; ++ ++ ppeDaddr_127_96 = entry->ipv6_5t_route.ipv6_dip0; ++ ppeDaddr_95_64 = entry->ipv6_5t_route.ipv6_dip1; ++ ppeDaddr_63_32 = entry->ipv6_5t_route.ipv6_dip2; ++ ppeDaddr_31_0 = entry->ipv6_5t_route.ipv6_dip3; ++ ++ ppeSportV6 = entry->ipv6_5t_route.sport; ++ ppeDportV6 = entry->ipv6_5t_route.dport; ++ if ((ipv6_sip_127_96 == ppeSaddr_127_96) && (ipv6_sip_95_64 == ppeSaddr_95_64) ++ && (ipv6_sip_63_32 == ppeSaddr_63_32) && (ipv6_sip_31_0 == ppeSaddr_31_0) && ++ (ipv6_dip_127_96 == ppeDaddr_127_96) && (ipv6_dip_95_64 == ppeDaddr_95_64) ++ && (ipv6_dip_63_32 == ppeDaddr_63_32) && (ipv6_dip_31_0 == ppeDaddr_31_0) && ++ (sport == ppeSportV6) && (dport == ppeDportV6)) { ++ return hash_index; ++ } else { ++ if (_hwnat_info.debug_level >= 1) ++ HWNAT_MSG_DBG("mib: ipv6 entry not found\n"); ++ return -1; ++ } ++ } ++ ++ ++ return -1; ++} ++ ++int _MDrv_HWNAT_Get_Ipv4_Hash(struct foe_pri_key *key, struct foe_entry *entry, int del) ++{ ++ uint32_t t_hvt_31; ++ uint32_t t_hvt_63; ++ uint32_t t_hvt_95; ++ uint32_t t_hvt_sd; ++ ++ uint32_t t_hvt_sd_23; ++ uint32_t t_hvt_sd_31_24; ++ uint32_t t_hash_32; ++ uint32_t t_hashs_16; ++ uint32_t t_ha16k; ++ uint32_t hash_index; ++ uint32_t ppeSaddr, ppeDaddr, ppeSport, ppeDport, saddr, daddr, sport, dport; ++ saddr = key->ipv4_hnapt.sip; ++ daddr = key->ipv4_hnapt.dip; ++ sport = key->ipv4_hnapt.sport; ++ dport = key->ipv4_hnapt.dport; ++ ++ t_hvt_31 = sport << 16 | dport; ++ t_hvt_63 = daddr; ++ t_hvt_95 = saddr; ++ ++ //NAT_PRINT("saddr = %x, daddr=%x, sport=%d, dport=%d\n", saddr, daddr, sport, dport); ++ if (DFL_FOE_HASH_MODE == 1) // hash mode 1 ++ t_hvt_sd = (t_hvt_31 & t_hvt_63) | ((~t_hvt_31) & t_hvt_95); ++ else // hash mode 2 ++ t_hvt_sd = t_hvt_63 ^ ( t_hvt_31 & (~t_hvt_95)); ++ ++ t_hvt_sd_23 = t_hvt_sd & 0xffffff; ++ t_hvt_sd_31_24 = t_hvt_sd & 0xff000000; ++ t_hash_32 = t_hvt_31 ^ t_hvt_63 ^ t_hvt_95 ^ ( (t_hvt_sd_23 << 8) | (t_hvt_sd_31_24 >> 24)); ++ t_hashs_16 = ((t_hash_32 & 0xffff0000) >> 16 ) ^ (t_hash_32 & 0xfffff); ++ ++ if (FOE_4TB_SIZ == 16384) ++ t_ha16k = t_hashs_16 & 0x1fff; // FOE_16k ++ else if (FOE_4TB_SIZ == 8192) ++ t_ha16k = t_hashs_16 & 0xfff; // FOE_8k ++ else if (FOE_4TB_SIZ == 4096) ++ t_ha16k = t_hashs_16 & 0x7ff; // FOE_4k ++ else if (FOE_4TB_SIZ == 2048) ++ t_ha16k = t_hashs_16 & 0x3ff; // FOE_2k ++ else ++ t_ha16k = t_hashs_16 & 0x1ff; // FOE_1k ++ hash_index = (uint32_t)t_ha16k *2; ++ ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr = entry->ipv4_hnapt.sip; ++ ppeDaddr = entry->ipv4_hnapt.dip; ++ ppeSport = entry->ipv4_hnapt.sport; ++ ppeDport = entry->ipv4_hnapt.dport; ++ ++ if (del !=1) { ++ if (entry->ipv4_hnapt.bfib1.state == BIND) ++ { ++ NAT_PRINT("Hash collision, hash index +1\n"); ++ hash_index = hash_index + 1; ++ entry = &ppe_foe_base[hash_index]; ++ } ++ if (entry->ipv4_hnapt.bfib1.state == BIND) ++ { ++ NAT_PRINT("Hash collision can not bind\n"); ++ return -1; ++ } ++ } else if(del == 1) { ++ if ((saddr == ppeSaddr) && (daddr == ppeDaddr) && (sport == ppeSport) ++ && (dport == ppeDport)){ ++ } else { ++ hash_index = hash_index + 1; ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr = entry->ipv4_hnapt.sip; ++ ppeDaddr = entry->ipv4_hnapt.dip; ++ ppeSport = entry->ipv4_hnapt.sport; ++ ppeDport = entry->ipv4_hnapt.dport; ++ if ((saddr == ppeSaddr) && (daddr == ppeDaddr) && (sport == ppeSport) && (dport == ppeDport)){ ++ ++ } else { ++ if (_hwnat_info.features & HW_NAT_SEMI_AUTO_MODE) { ++ NAT_PRINT("hash collision hwnat can not foundn"); ++ } ++ else if (_hwnat_info.features & HW_NAT_MANUAL_MODE) { ++ NAT_PRINT("Entry delete : Entry Not found\n"); ++ } ++ return -1; ++ } ++ } ++ } ++ return hash_index; ++} ++ ++int _MDrv_HWNAT_Get_Ipv4_Mib_Hash(struct foe_pri_key *key, struct foe_entry *entry) ++{ ++ uint32_t t_hvt_31; ++ uint32_t t_hvt_63; ++ uint32_t t_hvt_95; ++ uint32_t t_hvt_sd; ++ ++ uint32_t t_hvt_sd_23; ++ uint32_t t_hvt_sd_31_24; ++ uint32_t t_hash_32; ++ uint32_t t_hashs_16; ++ uint32_t t_ha16k; ++ uint32_t hash_index; ++ uint32_t ppeSaddr, ppeDaddr, ppeSport, ppeDport, saddr, daddr, sport, dport; ++ saddr = key->ipv4_hnapt.sip; ++ daddr = key->ipv4_hnapt.dip; ++ sport = key->ipv4_hnapt.sport; ++ dport = key->ipv4_hnapt.dport; ++ ++ t_hvt_31 = sport << 16 | dport; ++ t_hvt_63 = daddr; ++ t_hvt_95 = saddr; ++ ++ //NAT_PRINT("saddr = %x, daddr=%x, sport=%d, dport=%d\n", saddr, daddr, sport, dport); ++ if (DFL_FOE_HASH_MODE == 1) // hash mode 1 ++ t_hvt_sd = (t_hvt_31 & t_hvt_63) | ((~t_hvt_31) & t_hvt_95); ++ else // hash mode 2 ++ t_hvt_sd = t_hvt_63 ^ ( t_hvt_31 & (~t_hvt_95)); ++ ++ t_hvt_sd_23 = t_hvt_sd & 0xffffff; ++ t_hvt_sd_31_24 = t_hvt_sd & 0xff000000; ++ t_hash_32 = t_hvt_31 ^ t_hvt_63 ^ t_hvt_95 ^ ( (t_hvt_sd_23 << 8) | (t_hvt_sd_31_24 >> 24)); ++ t_hashs_16 = ((t_hash_32 & 0xffff0000) >> 16 ) ^ (t_hash_32 & 0xfffff); ++ ++ if (FOE_4TB_SIZ == 16384) ++ t_ha16k = t_hashs_16 & 0x1fff; // FOE_16k ++ else if (FOE_4TB_SIZ == 8192) ++ t_ha16k = t_hashs_16 & 0xfff; // FOE_8k ++ else if (FOE_4TB_SIZ == 4096) ++ t_ha16k = t_hashs_16 & 0x7ff; // FOE_4k ++ else if (FOE_4TB_SIZ == 2048) ++ t_ha16k = t_hashs_16 & 0x3ff; // FOE_2k ++ else ++ t_ha16k = t_hashs_16 & 0x1ff; // FOE_1k ++ hash_index = (uint32_t)t_ha16k *2; ++ ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr = entry->ipv4_hnapt.sip; ++ ppeDaddr = entry->ipv4_hnapt.dip; ++ ppeSport = entry->ipv4_hnapt.sport; ++ ppeDport = entry->ipv4_hnapt.dport; ++ ++ ++ ++ if ((saddr == ppeSaddr) && (daddr == ppeDaddr) && (sport == ppeSport) ++ && (dport == ppeDport)){ ++ return hash_index; ++ } else { ++ hash_index = hash_index + 1; ++ entry = &ppe_foe_base[hash_index]; ++ ppeSaddr = entry->ipv4_hnapt.sip; ++ ppeDaddr = entry->ipv4_hnapt.dip; ++ ppeSport = entry->ipv4_hnapt.sport; ++ ppeDport = entry->ipv4_hnapt.dport; ++ if ((saddr == ppeSaddr) && (daddr == ppeDaddr) && (sport == ppeSport) ++ && (dport == ppeDport)){ ++ return hash_index; ++ } else { ++ if (_hwnat_info.debug_level >= 1) ++ HWNAT_MSG_DBG("mib: ipv4 entry not found\n"); ++ return -1; ++ } ++ } ++ ++ return -1; ++} ++ ++int MDrv_HWNAT_Get_Ppe_Entry_Idx(struct foe_pri_key *key, struct foe_entry *entry, int del) ++{ ++ if ((key->pkt_type) == IPV4_NAPT) ++ return _MDrv_HWNAT_Get_Ipv4_Hash(key, entry, del); ++ else if ((_hwnat_info.features & NAT_IPV6) && ((key->pkt_type) == IPV6_ROUTING)) ++ return _MDrv_HWNAT_Get_Ipv6_Hash(key, entry, del); ++ else ++ return -1; ++} ++ ++int MDrv_HWNAT_Get_Mib_Entry_Idx(struct foe_pri_key *key, struct foe_entry *entry) ++{ ++ if ((key->pkt_type) == IPV4_NAPT) ++ return _MDrv_HWNAT_Get_Ipv4_Mib_Hash(key, entry); ++ else if ((_hwnat_info.features & NAT_IPV6) && ((key->pkt_type) == IPV6_ROUTING)) ++ return _MDrv_HWNAT_Get_Ipv6_Mib_Hash(key, entry); ++ else ++ return -1; ++} ++EXPORT_SYMBOL(MDrv_HWNAT_Get_Mib_Entry_Idx); ++ ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_api.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_api.h +new file mode 100755 +index 000000000000..0118b92f4a92 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_api.h +@@ -0,0 +1,30 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_HWNAT_API.h ++/// @brief NOE NAT Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_HWNAT_API_H ++#define _MDRV_HWNAT_API_H ++ ++int MDrv_HWNAT_Get_Ppe_Entry_Idx(struct foe_pri_key *key, struct foe_entry *entry, int del); ++int MDrv_HWNAT_Get_Mib_Entry_Idx(struct foe_pri_key *key, struct foe_entry *entry); ++#endif /* _MDRV_HWNAT_API_H */ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_config.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_config.h +new file mode 100755 +index 000000000000..805af13b8123 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_config.h +@@ -0,0 +1,466 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_NAT_CONFIG.h ++/// @brief NOE NAT Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_NOE_HWNAT_CONFIG_H_ ++#define _MDRV_NOE_HWNAT_CONFIG_H_ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// CONFIG ++//------------------------------------------------------------------------------------------------- ++#define HWNAT_BIT(x) (((uint64_t) 1) << x) ++ ++#define HNAT_V2 HWNAT_BIT(0) ++#ifdef CONFIG_NOE_HW_NAT_PACKET_SAMPLING ++#define PACKET_SAMPLING HWNAT_BIT(1) ++#else ++#define PACKET_SAMPLING (0) ++#endif /*CONFIG_NOE_HW_NAT_PACKET_SAMPLING */ ++#ifdef CONFIG_PPE_MIB ++#define PPE_MIB HWNAT_BIT(2) ++#else ++#define PPE_MIB (0) ++#endif /* CONFIG_PPE_MIB */ ++#define NAT_IPV6 HWNAT_BIT(3) ++#ifdef CONFIG_NOE_HW_NAT_PREBIND ++#define NAT_PREBIND HWNAT_BIT(4) ++#else ++#define NAT_PREBIND 0 ++#endif /* CONFIG_NOE_HW_NAT_PREBINDi */ ++#ifdef CONFIG_NOE_HW_NAT_ACCNT_MAINTAINER ++#define ACCNT_MAINTAINER HWNAT_BIT(5) ++#else ++#define ACCNT_MAINTAINER 0 ++#endif /* CONFIG_NOE_HW_NAT_ACCNT_MAINTAINER */ ++#ifdef CONFIG_PPE_MCAST ++#define PPE_MCAST HWNAT_BIT(6) ++#else ++#define PPE_MCAST 0 ++#endif /*CONFIG_PPE_MCAST*/ ++#ifdef CONFIG_NOE_HW_NAT_PPTP_L2TP ++#define PPTP_L2TP HWNAT_BIT(7) ++#else ++#define PPTP_L2TP 0 ++#endif /*CONFIG_NOE_HW_NAT_PPTP_L2TP*/ ++#ifdef CONFIG_QDMA_SUPPORT_QOS ++#define QDMA_SUPPORT_QOS HWNAT_BIT(8) ++#else ++#define QDMA_SUPPORT_QOS 0 ++#endif /*CONFIG_QDMA_SUPPORT_QOS*/ ++#ifdef CONFIG_WAN_TO_WLAN_SUPPORT_QOS ++#define WAN_TO_WLAN_SUPPORT_QOS HWNAT_BIT(9) ++#else ++#define WAN_TO_WLAN_SUPPORT_QOS 0 ++#endif /*CONFIG_WAN_TO_WLAN_SUPPORT_QOS*/ ++#ifdef CONFIG_SUPPORT_WLAN_OPTIMIZE ++#define WLAN_OPTIMIZE HWNAT_BIT(10) ++#else ++#define WLAN_OPTIMIZE 0 ++#endif /* CONFIG_SUPPORT_WLAN_OPTIMIZE_RX */ ++#ifdef CONFIG_NOE_HW_NAT_WIFI ++#define HW_NAT_WIFI HWNAT_BIT(11) ++#else ++#define HW_NAT_WIFI 0 ++#endif /*CONFIG_NOE_HW_NAT_WIFI*/ ++#ifdef CONFIG_NOE_HW_NAT_WIFI_NEW_ARCH ++#define HW_NAT_WIFI_NEW_ARCH HWNAT_BIT(12) ++#else ++#define HW_NAT_WIFI_NEW_ARCH 0 ++#endif /*CONFIG_NOE_HW_NAT_WIFI_NEW_ARCH*/ ++#ifdef CONFIG_NOE_QDMA ++#define HW_NAT_QDMA HWNAT_BIT(13) ++#else ++#define HW_NAT_QDMA 0 ++#endif /*CONFIG_NOE_QDMA*/ ++#ifdef CONFIG_HW_NAT_NEW_ARCH_WDMA ++#define HW_NAT_ARCH_WIFI_WDMA HWNAT_BIT(14) ++#else ++#define HW_NAT_ARCH_WIFI_WDMA 0 ++#endif /* CONFIG_HW_NAT_NEW_ARCH_WDMA */ ++#ifdef CONFIG_NOE_QDMATX_QDMARX ++#define HW_NAT_QDMATX_QDMARX HWNAT_BIT(15) ++#else ++#define HW_NAT_QDMATX_QDMARX 0 ++#endif /* CONFIG_NOE_QDMATX_QDMARX */ ++#ifdef CONFIG_PSEUDO_SUPPORT ++#define HW_NAT_PSEUDO_SUPPORT HWNAT_BIT(16) ++#else ++#define HW_NAT_PSEUDO_SUPPORT 0 ++#endif /* CONFIG_PSEUDO_SUPPORT */ ++#ifdef CONFIG_HW_SFQ ++#define HW_NAT_HW_SFQ HWNAT_BIT(17) ++#else ++#define HW_NAT_HW_SFQ 0 ++#endif /* CONFIG_HW_SFQ */ ++#ifdef CONFIG_APCLI_SUPPORT ++#define HW_NAT_APCLI_SUPPORT HWNAT_BIT(18) ++#else ++#define HW_NAT_APCLI_SUPPORT 0 ++#endif /* CONFIG_APCLI_SUPPORT */ ++#ifdef CONFIG_WDS_SUPPORT ++#define HW_NAT_WDS_SUPPORT HWNAT_BIT(19) ++#else ++#define HW_NAT_WDS_SUPPORT 0 ++#endif /* CONFIG_WDS_SUPPORT */ ++#ifdef CONFIG_MBSS_SUPPORT ++#define HW_NAT_MBSS_SUPPORT HWNAT_BIT(20) ++#else ++#define HW_NAT_MBSS_SUPPORT 0 ++#endif /* CONFIG_MBSS_SUPPORT */ ++#ifdef CONFIG_NOE_HW_VLAN_TX ++#define HW_NAT_VLAN_TX HWNAT_BIT(21) ++#else ++#define HW_NAT_VLAN_TX 0 ++#endif /* CONFIG_NOE_HW_VLAN_TX */ ++#ifdef CONFIG_NOE_HW_NAT_NIC_USB ++#define HW_NAT_NIC_USB HWNAT_BIT(22) ++#else ++#define HW_NAT_NIC_USB 0 ++#endif /* CONFIG_NOE_HW_NAT_NIC_USB */ ++#ifdef CONFIG_NOE_GMAC2 ++#define HW_NAT_GMAC2 HWNAT_BIT(23) ++#else ++#define HW_NAT_GMAC2 0 ++#endif /* CONFIG_NOE_GMAC2 */ ++#ifdef CONFIG_NOE_SPECIAL_TAG ++#define HW_NAT_SPECIAL_TAG HWNAT_BIT(24) ++#else ++#define HW_NAT_SPECIAL_TAG 0 ++#endif /* CONFIG_NOE_SPECIAL_TAG */ ++#ifdef CONFIG_IMQ ++#define HW_NAT_IMQ HWNAT_BIT(25) ++#else ++#define HW_NAT_IMQ 0 ++#endif /* CONFIG_IMQ */ ++#ifdef CONFIG_RTDEV_MII ++#define HW_NAT_MII HWNAT_BIT(26) ++#else ++#define HW_NAT_MII 0 ++#endif /* CONFIG_RTDEV_MII */ ++#ifdef CONFIG_RTDEV_PCI ++#define HW_NAT_PCI HWNAT_BIT(27) ++#else ++#define HW_NAT_PCI 0 ++#endif /* CONFIG_RTDEV_PCI */ ++#ifdef CONFIG_RTDEV_USB ++#define HW_NAT_USB HWNAT_BIT(28) ++#else ++#define HW_NAT_USB 0 ++#endif /* CONFIG_RTDEV_USB */ ++#ifdef CONFIG_RTDEV ++#define HW_NAT_SP_DEV HWNAT_BIT(29) ++#else ++#define HW_NAT_SP_DEV 0 ++#endif /* CONFIG_RTDEV */ ++#ifdef CONFIG_RLT_AP_SUPPORT ++#define HW_NAT_AP_SUPPORT HWNAT_BIT(30) ++#else ++#define HW_NAT_AP_SUPPORT 0 ++#endif /* CONFIG_RLT_AP_SUPPORT */ ++#ifdef CONFIG_AP_MESH_SUPPORT ++#define HW_NAT_AP_MESH_SUPPORT HWNAT_BIT(31) ++#else ++#define HW_NAT_AP_MESH_SUPPORT 0 ++#endif /* CONFIG_RLT_AP_SUPPORT */ ++#ifdef CONFIG_AP_MBSS_SUPPORT ++#define HW_NAT_AP_MBSS_SUPPORT HWNAT_BIT(32) ++#else ++#define HW_NAT_AP_MBSS_SUPPORT 0 ++#endif /* CONFIG_AP_MBSS_SUPPORT */ ++#ifdef CONFIG_NOE_HW_NAT_AUTO_MODE ++#define HW_NAT_AUTO_MODE HWNAT_BIT(33) ++#else ++#define HW_NAT_AUTO_MODE 0 ++#endif /* NOE_HW_NAT_AUTO_MODE */ ++#ifdef CONFIG_NOE_HW_NAT_SEMI_AUTO_MODE ++#define HW_NAT_SEMI_AUTO_MODE HWNAT_BIT(34) ++#else ++#define HW_NAT_SEMI_AUTO_MODE 0 ++#endif /* CONFIG_HW_NAT_SEMI_AUTO_MODE */ ++#ifdef CONFIG_NOE_HW_NAT_MANUAL_MODE ++#define HW_NAT_MANUAL_MODE HWNAT_BIT(35) ++#else ++#define HW_NAT_MANUAL_MODE 0 ++#endif /* CONFIG_HW_NAT_MANUAL_MODE*/ ++#ifdef CONFIG_NOE_HW_NAT_IPI ++#define HW_NAT_IPI HWNAT_BIT(36) ++#else ++#define HW_NAT_IPI 0 ++#endif /* CONFIG_NOE_HW_NAT_IPI */ ++ ++#define MDRV_HWNAT_CONFIG_SET_FEATURES(hwnat_device) \ ++{ \ ++hwnat_device.features = 0; \ ++hwnat_device.features |= HNAT_V2; \ ++hwnat_device.features |= PACKET_SAMPLING; \ ++hwnat_device.features |= PPE_MIB; \ ++hwnat_device.features |= NAT_IPV6; \ ++hwnat_device.features |= NAT_PREBIND; \ ++hwnat_device.features |= ACCNT_MAINTAINER; \ ++hwnat_device.features |= PPE_MCAST; \ ++hwnat_device.features |= PPTP_L2TP; \ ++hwnat_device.features |= QDMA_SUPPORT_QOS; \ ++hwnat_device.features |= WAN_TO_WLAN_SUPPORT_QOS; \ ++hwnat_device.features |= WLAN_OPTIMIZE; \ ++hwnat_device.features |= HW_NAT_WIFI; \ ++hwnat_device.features |= HW_NAT_WIFI_NEW_ARCH; \ ++hwnat_device.features |= HW_NAT_QDMA; \ ++hwnat_device.features |= HW_NAT_ARCH_WIFI_WDMA; \ ++hwnat_device.features |= HW_NAT_QDMATX_QDMARX; \ ++hwnat_device.features |= HW_NAT_PSEUDO_SUPPORT; \ ++hwnat_device.features |= HW_NAT_HW_SFQ; \ ++hwnat_device.features |= HW_NAT_APCLI_SUPPORT; \ ++hwnat_device.features |= HW_NAT_WDS_SUPPORT; \ ++hwnat_device.features |= HW_NAT_MBSS_SUPPORT; \ ++hwnat_device.features |= HW_NAT_VLAN_TX; \ ++hwnat_device.features |= HW_NAT_NIC_USB; \ ++hwnat_device.features |= HW_NAT_PCI; \ ++hwnat_device.features |= HW_NAT_GMAC2; \ ++hwnat_device.features |= HW_NAT_SPECIAL_TAG; \ ++hwnat_device.features |= HW_NAT_IMQ; \ ++hwnat_device.features |= HW_NAT_MII; \ ++hwnat_device.features |= HW_NAT_PCI; \ ++hwnat_device.features |= HW_NAT_USB; \ ++hwnat_device.features |= HW_NAT_SP_DEV; \ ++hwnat_device.features |= HW_NAT_AP_SUPPORT; \ ++hwnat_device.features |= HW_NAT_AP_MESH_SUPPORT; \ ++hwnat_device.features |= HW_NAT_AP_MBSS_SUPPORT; \ ++hwnat_device.features |= HW_NAT_AUTO_MODE; \ ++hwnat_device.features |= HW_NAT_SEMI_AUTO_MODE; \ ++hwnat_device.features |= HW_NAT_MANUAL_MODE; \ ++hwnat_device.features |= HW_NAT_IPI; \ ++} ++ ++ ++#define MDRV_HWNAT_CONFIG_DUMP_FEATURES() \ ++{\ ++HWNAT_MSG_MUST("HNAT_V2 :%d\n", HNAT_V2?1:0); \ ++HWNAT_MSG_MUST("PACKET_SAMPLING :%d\n", PACKET_SAMPLING?1:0); \ ++HWNAT_MSG_MUST("PPE_MIB :%d\n", PPE_MIB?1:0); \ ++HWNAT_MSG_MUST("NAT_IPV6 :%d\n", NAT_IPV6?1:0); \ ++HWNAT_MSG_MUST("NAT_PREBIND :%d\n", NAT_PREBIND?1:0); \ ++HWNAT_MSG_MUST("ACCNT_MAINTAINER :%d\n", ACCNT_MAINTAINER?1:0); \ ++HWNAT_MSG_MUST("PPE_MCAST :%d\n", PPE_MCAST?1:0); \ ++HWNAT_MSG_MUST("PPTP_L2TP :%d\n", PPTP_L2TP?1:0); \ ++HWNAT_MSG_MUST("QDMA_SUPPORT_QOS :%d\n", QDMA_SUPPORT_QOS?1:0); \ ++HWNAT_MSG_MUST("WAN_TO_WLAN_SUPPORT_QOS :%d\n", WAN_TO_WLAN_SUPPORT_QOS?1:0); \ ++HWNAT_MSG_MUST("WLAN_OPTIMIZE :%d\n", WLAN_OPTIMIZE?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_WIFI :%d\n", HW_NAT_WIFI?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_WIFI_NEW_ARCH :%d\n", HW_NAT_WIFI_NEW_ARCH?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_QDMA :%d\n", HW_NAT_QDMA?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_ARCH_WIFI_WDMA :%d\n", HW_NAT_ARCH_WIFI_WDMA?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_QDMATX_QDMARX :%d\n", HW_NAT_QDMATX_QDMARX?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_PSEUDO_SUPPORT :%d\n", HW_NAT_PSEUDO_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_HW_SFQ :%d\n", HW_NAT_HW_SFQ?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_APCLI_SUPPORT :%d\n", HW_NAT_APCLI_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_WDS_SUPPORT :%d\n", HW_NAT_WDS_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_MBSS_SUPPORT :%d\n", HW_NAT_MBSS_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_VLAN_TX :%d\n", HW_NAT_VLAN_TX?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_NIC_USB :%d\n", HW_NAT_NIC_USB?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_PCI :%d\n", HW_NAT_PCI?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_GMAC2 :%d\n", HW_NAT_GMAC2?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_SPECIAL_TAG :%d\n", HW_NAT_SPECIAL_TAG?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_IMQ :%d\n", HW_NAT_IMQ?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_MII :%d\n", HW_NAT_MII?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_PCI :%d\n", HW_NAT_PCI?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_USB :%d\n", HW_NAT_USB?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_SP_DEV :%d\n", HW_NAT_SP_DEV?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_AP_SUPPORT :%d\n", HW_NAT_AP_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_AP_MESH_SUPPORT :%d\n", HW_NAT_AP_MESH_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_AP_MBSS_SUPPORT :%d\n", HW_NAT_AP_MBSS_SUPPORT?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_AUTO_MODE :%d\n", HW_NAT_AUTO_MODE?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_SEMI_AUTO_MODE :%d\n", HW_NAT_SEMI_AUTO_MODE?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_MANUAL_MODE :%d\n", HW_NAT_MANUAL_MODE?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_IPI :%d\n", HW_NAT_IPI?1:0); \ ++} ++ ++ ++ ++#ifdef DSCP_REMARK_TEST ++#define HW_NAT_DSCP_REMARK_TEST BIT(0) ++#else ++#define HW_NAT_DSCP_REMARK_TEST 0 ++#endif /* DSCP_REMARK_TEST */ ++#ifdef VLAN_LAYER_TEST ++#define HW_NAT_VLAN_LAYER_TEST BIT(1) ++#else ++#define HW_NAT_VLAN_LAYER_TEST 0 ++#endif /* VLAN_LAYER_TEST */ ++#ifdef FORCE_UP_TEST ++#define HW_NAT_FORCE_UP_TEST BIT(2) ++#else ++#define HW_NAT_FORCE_UP_TEST 0 ++#endif /* HW_NAT_FORCE_UP_TEST */ ++#ifdef VPRI_REMARK_TEST ++#define HW_NAT_VPRI_REMARK_TEST BIT(3) ++#else ++#define HW_NAT_VPRI_REMARK_TEST 0 ++#endif /* VPRI_REMARK_TEST */ ++#ifdef PREBIND_TEST ++#define HW_NAT_PREBIND_TEST BIT(4) ++#else ++#define HW_NAT_PREBIND_TEST 0 ++#endif /* PREBIND_TEST */ ++ ++ ++ ++#define MDRV_HWNAT_CONFIG_SET_TEST(hwnat_device) \ ++{ \ ++hwnat_device.test = 0; \ ++hwnat_device.test |= HW_NAT_DSCP_REMARK_TEST; \ ++hwnat_device.test |= HW_NAT_VLAN_LAYER_TEST; \ ++hwnat_device.test |= HW_NAT_FORCE_UP_TEST; \ ++hwnat_device.test |= HW_NAT_VPRI_REMARK_TEST; \ ++hwnat_device.test |= HW_NAT_PREBIND_TEST; \ ++} ++ ++ ++#define MDRV_HWNAT_CONFIG_DUMP_TEST() \ ++{\ ++HWNAT_MSG_MUST("HW_NAT_DSCP_REMARK_TEST :%d\n", HW_NAT_DSCP_REMARK_TEST?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_VLAN_LAYER_TEST :%d\n", HW_NAT_VLAN_LAYER_TEST?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_FORCE_UP_TEST :%d\n", HW_NAT_FORCE_UP_TEST?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_VPRI_REMARK_TEST :%d\n", HW_NAT_VPRI_REMARK_TEST?1:0); \ ++HWNAT_MSG_MUST("HW_NAT_PREBIND_TEST :%d\n", HW_NAT_PREBIND_TEST?1:0); \ ++} ++ ++ ++#if defined(CONFIG_NOE_HW_NAT_TBL_1K) ++#define FOE_4TB_SIZ 1024 ++#elif defined(CONFIG_NOE_HW_NAT_TBL_2K) ++#define FOE_4TB_SIZ 2048 ++#elif defined(CONFIG_NOE_HW_NAT_TBL_4K) ++#define FOE_4TB_SIZ 4096 ++#elif defined(CONFIG_NOE_HW_NAT_TBL_8K) ++#define FOE_4TB_SIZ 8192 ++#elif defined(CONFIG_NOE_HW_NAT_TBL_16K) ++#define FOE_4TB_SIZ 16384 ++#endif /*CONFIG_NOE_HW_NAT_TBL*/ ++ ++#if defined(CONFIG_NOE_HW_NAT_HASH0) ++#define DFL_FOE_HASH_MODE 0 ++#elif defined(CONFIG_NOE_HW_NAT_HASH1) ++#define DFL_FOE_HASH_MODE 1 ++#elif defined(CONFIG_NOE_HW_NAT_HASH2) ++#define DFL_FOE_HASH_MODE 2 ++#elif defined(CONFIG_NOE_HW_NAT_HASH3) ++#define DFL_FOE_HASH_MODE 3 ++#elif defined(CONFIG_NOE_HW_NAT_HASH_DBG) ++#define DFL_FOE_HASH_MODE 0 ++#endif /*CONFIG_NOE_HW_NAT_HASH*/ ++ ++#if defined(CONFIG_NOE_HW_NAT_HASH_DBG_SPORT) ++#define DEF_HASH_DBG_MODE 1 ++#elif defined(CONFIG_NOE_HW_NAT_HASH_DBG_IPV6_SIP) ++#define DEF_HASH_DBG_MODE 3 ++#elif defined(CONFIG_NOE_HW_NAT_HASH_DBG_IPV4_SIP) ++#define DEF_HASH_DBG_MODE 2 ++#else ++#define DEF_HASH_DBG_MODE 0 ++#endif /*CONFIG_NOE_HW_NAT_HASH_DBG*/ ++ ++ ++ ++#define IS_SPECIAL_DEV(x) ((x) & (HW_NAT_MII | HW_NAT_PCI | HW_NAT_USB | HW_NAT_SP_DEV)) ++#define IS_APMBSS_MBSS_DEV(x) ((x) & (HW_NAT_AP_MBSS_SUPPORT | HW_NAT_MBSS_SUPPORT)) ++#define IS_SPECIAL_DEV_OR_AP(x) ((x) & (HW_NAT_MII | HW_NAT_PCI | HW_NAT_USB | HW_NAT_SP_DEV | HW_NAT_AP_SUPPORT)) ++ ++#define IS_QDMA_MCAST_SUPPORT(x) ((x & HW_NAT_QDMA) && (x & PPE_MCAST)) ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++#define HWSFQUP (3) ++#define HWSFQDL (1) ++ ++ ++enum BindDir { ++ UPSTREAM_ONLY = 0, /* only speed up upstream flow */ ++ DOWNSTREAM_ONLY = 1, /* only speed up downstream flow */ ++ BIDIRECTION = 2 /* speed up bi-direction flow */ ++}; ++ ++#ifndef CONFIG_NOE_HW_NAT_ACL_DLTA ++#define CONFIG_NOE_HW_NAT_ACL_DLTA 3 ++#endif ++ ++ ++ ++#define DFL_FOE_TTL_REGEN (1) /* TTL = TTL -1 */ ++#define DFL_FOE_TCP_KA (CONFIG_NOE_HW_NAT_TCP_KA) ++#define DFL_FOE_UDP_KA (CONFIG_NOE_HW_NAT_UDP_KA) ++#define DFL_FOE_NTU_KA (CONFIG_NOE_HW_NAT_NTU_KA) ++#define DFL_FOE_BNDR (CONFIG_NOE_HW_NAT_BINDING_THRESHOLD) ++ ++#ifndef CONFIG_NOE_HW_NAT_PBND_RD_LMT ++#define DFL_PBND_RD_LMT (1) ++#else ++#define DFL_PBND_RD_LMT (CONFIG_NOE_HW_NAT_PBND_RD_LMT) ++#endif ++ ++#ifndef CONFIG_NOE_HW_NAT_PBND_RD_PRD ++#define DFL_PBND_RD_PRD (1) ++#else ++#define DFL_PBND_RD_PRD (CONFIG_NOE_HW_NAT_PBND_RD_PRD) ++#endif ++#define DFL_FOE_UNB_MNP (CONFIG_NOE_HW_NAT_UNB_MNP) ++#define DFL_FOE_ACL_DLTA (CONFIG_NOE_HW_NAT_ACL_DLTA) ++#define DFL_FOE_UNB_DLTA (CONFIG_NOE_HW_NAT_UNB_DLTA) ++#define DFL_FOE_NTU_DLTA (CONFIG_NOE_HW_NAT_NTU_DLTA) ++#define DFL_FOE_UDP_DLTA (CONFIG_NOE_HW_NAT_UDP_DLTA) ++#define DFL_FOE_FIN_DLTA (CONFIG_NOE_HW_NAT_FIN_DLTA) ++#define DFL_FOE_TCP_DLTA (CONFIG_NOE_HW_NAT_TCP_DLTA) ++ ++#define WIFI_INFO_LEN ((HW_NAT_ARCH_WIFI_WDMA)?3:0) ++#define FOE_INFO_LEN ((PPTP_L2TP)? (10 + WIFI_INFO_LEN):(6 + WIFI_INFO_LEN)) ++#define FOE_MAGIC_FASTPATH (0x77) ++#define FOE_MAGIC_L2TPPATH (0x78) ++#define DFL_FOE_KA ((HNAT_V2)?E_HWNAT_KA_CFG_ALOPKT2CPU:E_HWNAT_KA_CFG_NONE) ++ ++ ++#define MDRV_HWNAT_CONFIG_DUMP_VALUE() \ ++{\ ++HWNAT_MSG_MUST("DFL_FOE_TTL_REGEN :%d\n", DFL_FOE_TTL_REGEN); \ ++HWNAT_MSG_MUST("DFL_FOE_TCP_KA :%d\n", DFL_FOE_TCP_KA ); \ ++HWNAT_MSG_MUST("DFL_FOE_UDP_KA :%d\n", DFL_FOE_UDP_KA ); \ ++HWNAT_MSG_MUST("DFL_FOE_NTU_KA :%d\n", DFL_FOE_NTU_KA ); \ ++HWNAT_MSG_MUST("DFL_FOE_BNDR :%d\n", DFL_FOE_BNDR ); \ ++HWNAT_MSG_MUST("DFL_PBND_RD_LMT :%d\n", DFL_PBND_RD_LMT ); \ ++HWNAT_MSG_MUST("DFL_PBND_RD_PRD :%d\n", DFL_PBND_RD_PRD ); \ ++HWNAT_MSG_MUST("DFL_FOE_UNB_MNP :%d\n", DFL_FOE_UNB_MNP ); \ ++HWNAT_MSG_MUST("DFL_FOE_ACL_DLTA :%d\n", DFL_FOE_ACL_DLTA ); \ ++HWNAT_MSG_MUST("DFL_FOE_UNB_DLTA :%d\n", DFL_FOE_UNB_DLTA ); \ ++HWNAT_MSG_MUST("DFL_FOE_NTU_DLTA :%d\n", DFL_FOE_NTU_DLTA ); \ ++HWNAT_MSG_MUST("DFL_FOE_UDP_DLTA :%d\n", DFL_FOE_UDP_DLTA ); \ ++HWNAT_MSG_MUST("DFL_FOE_FIN_DLTA :%d\n", DFL_FOE_FIN_DLTA ); \ ++HWNAT_MSG_MUST("DFL_FOE_TCP_DLTA :%d\n", DFL_FOE_TCP_DLTA ); \ ++} ++ ++#endif /* _MDRV_NOE_HWNAT_CONFIG_H_ */ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_define.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_define.h +new file mode 100755 +index 000000000000..2eef5e036a2f +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_define.h +@@ -0,0 +1,21 @@ ++/* ++ Module Name: ++ foe_fdb.h ++ ++ Abstract: ++ ++ Revision History: ++ Who When What ++ -------- ---------- ---------------------------------------------- ++ Name Date Modification logs ++ Steven Liu 2006-10-06 Initial version ++*/ ++ ++#ifndef _FOE_DEFINE_WANTED ++#define _FOE_DEFINE_WANTED ++ ++extern unsigned int M2Q_table[64]; ++extern unsigned int lan_wan_separate; ++extern unsigned int web_sfq_enable; ++extern struct foe_entry * ppe_virt_foe_base_tmp; ++#endif +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_fast_path.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_fast_path.h +new file mode 100755 +index 000000000000..89489f58c4d0 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_fast_path.h +@@ -0,0 +1,42 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_NAT.h ++/// @brief NOE NAT Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MDRV_HWNAT_FASTPATH_H ++#define _MDRV_HWNAT_FASTPATH_H ++ ++inline int32_t MDrv_HWNAT_Pptp_Lan(struct sk_buff *skb) {return 1;} ++inline int32_t MDrv_HWNAT_Pptp_Wan(struct sk_buff *skb) {return 1;} ++inline int32_t MDrv_HWNAT_L2tp_Lan(struct sk_buff *skb) {return 1;} ++inline int32_t MDrv_HWNAT_L2tp_Wan(struct sk_buff *skb) {return 1;} ++inline int32_t MDrv_HWNAT_Pptp_Lan_Parse_Layer(struct sk_buff * skb) {return 1;} ++inline int32_t MDrv_HWNAT_Pptp_Wan_Parse_Layer(struct sk_buff * skb) {return 1;} ++inline int32_t MDrv_HWNAT_L2tp_Wan_Parse_Layer(struct sk_buff * skb) {return 1;} ++inline void MDrv_HWNAT_Pptp_L2tp_Update_Entry(uint8_t protocol, uint32_t addr,uint32_t src_ip, uint32_t foe_hash_index){} ++inline int32_t MDrv_HWNAT_Send_Hash_Pkt(struct sk_buff *pskb) {return 1;} ++inline int32_t MDrv_HWNAT_L2tp_Send_Hash_Pkt(struct sk_buff *pskb) {return 1;} ++inline int32_t MDrv_HWNAT_Pptp_L2tp_Init(void) {return 1;} ++inline int32_t MDrv_HWNAT_Pptp_L2tp_Clean(void) {return 1;} ++#endif /* _MDRV_HWNAT_FASTPATH_H */ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_foe.c b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_foe.c +new file mode 100755 +index 000000000000..31820556e62a +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_foe.c +@@ -0,0 +1,1092 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_HWNAT_FOE.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_hwnat.h" ++#include "mdrv_hwnat.h" ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_ioctl.h" ++#include "mdrv_hwnat_util.h" ++#include "mdrv_hwnat_log.h" ++#include "mdrv_hwnat_define.h" ++#if (PPTP_L2TP) ++#include "pptp_l2tp_fdb.h" ++#endif ++#include "mdrv_hwnat_api.h" ++ ++ ++struct pkt_rx_parse_result ppe_parse_rx_result; ++extern u8 USE_3T_UDP_FRAG; ++extern int DP_GMAC1; ++extern int DPORT_GMAC2; ++ ++void MDrv_HWNAT_Foe_Set_High_Mac(u8 *dst, uint8_t *src) ++{ ++ dst[3] = src[0]; ++ dst[2] = src[1]; ++ dst[1] = src[2]; ++ dst[0] = src[3]; ++} ++ ++void MDrv_HWNAT_Foe_Set_Low_Mac(u8 *dst, uint8_t *src) ++{ ++ dst[1] = src[4]; ++ dst[0] = src[5]; ++} ++ ++ ++ ++void MDrv_HWNAT_Foe_Dump_Entry(uint32_t index) ++{ ++ struct foe_entry *entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, index); ++ struct ps_entry *ps_entry = NULL; ++ u32 *p = (uint32_t *)entry; ++ u32 i = 0; ++ ++ if (_hwnat_info.features & PACKET_SAMPLING) ++ ps_entry = PS_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_ps_base, index); ++ ++ ++ NAT_PRINT("\033[0;32;32m" " =========================\n""\033[m", index, entry); ++ if (_hwnat_info.debug_level >= 2) { ++ for (i = 0; i < 20; i++) { ++ NAT_PRINT("%02d: %08X\n", i, *(p + i)); ++ } ++ } ++ NAT_PRINT("-----------------------------------\n"); ++ NAT_PRINT("Information Block 1: %08X\n", entry->ipv4_hnapt.info_blk1); ++ ++ if (IS_IPV4_HNAPT(entry)) { ++ if (_hwnat_info.features & HW_NAT_QDMA) { ++ NAT_PRINT("Information Block 2=%x (FP=%d FQOS=%d QID=%d)", ++ entry->ipv4_hnapt.info_blk2, ++ entry->ipv4_hnapt.info_blk2 >> 5 & 0x7, ++ entry->ipv4_hnapt.info_blk2 >> 4 & 0x1, ++ (entry->ipv4_hnapt.iblk2.qid) + ++ ((entry->ipv4_hnapt.iblk2.qid1 & 0x03) << 4)); ++ } ++ else { ++ NAT_PRINT("Information Block 2: %08X (FP=%d)\n", entry->ipv4_hnapt.info_blk2, ++ entry->ipv4_hnapt.info_blk2 >> 5 & 0x7); ++ } ++ NAT_PRINT("Create IPv4 HNAPT entry\n"); ++ NAT_PRINT ++ ("IPv4 Org IP/Port: %u.%u.%u.%u:%d->%u.%u.%u.%u:%d\n", ++ IP_FORMAT3(entry->ipv4_hnapt.sip), IP_FORMAT2(entry->ipv4_hnapt.sip), ++ IP_FORMAT1(entry->ipv4_hnapt.sip), IP_FORMAT0(entry->ipv4_hnapt.sip), ++ entry->ipv4_hnapt.sport, ++ IP_FORMAT3(entry->ipv4_hnapt.dip), IP_FORMAT2(entry->ipv4_hnapt.dip), ++ IP_FORMAT1(entry->ipv4_hnapt.dip), IP_FORMAT0(entry->ipv4_hnapt.dip), ++ entry->ipv4_hnapt.dport); ++ NAT_PRINT ++ ("IPv4 New IP/Port: %u.%u.%u.%u:%d->%u.%u.%u.%u:%d\n", ++ IP_FORMAT3(entry->ipv4_hnapt.new_sip), IP_FORMAT2(entry->ipv4_hnapt.new_sip), ++ IP_FORMAT1(entry->ipv4_hnapt.new_sip), IP_FORMAT0(entry->ipv4_hnapt.new_sip), ++ entry->ipv4_hnapt.new_sport, ++ IP_FORMAT3(entry->ipv4_hnapt.new_dip), IP_FORMAT2(entry->ipv4_hnapt.new_dip), ++ IP_FORMAT1(entry->ipv4_hnapt.new_dip), IP_FORMAT0(entry->ipv4_hnapt.new_dip), ++ entry->ipv4_hnapt.new_dport); ++ } ++ else if (IS_IPV4_HNAT(entry)) { ++ NAT_PRINT("Information Block 2: %08X\n", entry->ipv4_hnapt.info_blk2); ++ NAT_PRINT("Create IPv4 HNAT entry\n"); ++ NAT_PRINT("IPv4 Org IP: %u.%u.%u.%u->%u.%u.%u.%u\n", ++ IP_FORMAT3(entry->ipv4_hnapt.sip), IP_FORMAT2(entry->ipv4_hnapt.sip), ++ IP_FORMAT1(entry->ipv4_hnapt.sip), IP_FORMAT0(entry->ipv4_hnapt.sip), ++ IP_FORMAT3(entry->ipv4_hnapt.dip), IP_FORMAT2(entry->ipv4_hnapt.dip), ++ IP_FORMAT1(entry->ipv4_hnapt.dip), IP_FORMAT0(entry->ipv4_hnapt.dip)); ++ NAT_PRINT("IPv4 New IP: %u.%u.%u.%u->%u.%u.%u.%u\n", ++ IP_FORMAT3(entry->ipv4_hnapt.new_sip), IP_FORMAT2(entry->ipv4_hnapt.new_sip), ++ IP_FORMAT1(entry->ipv4_hnapt.new_sip), IP_FORMAT0(entry->ipv4_hnapt.new_sip), ++ IP_FORMAT3(entry->ipv4_hnapt.new_dip), IP_FORMAT2(entry->ipv4_hnapt.new_dip), ++ IP_FORMAT1(entry->ipv4_hnapt.new_dip), IP_FORMAT0(entry->ipv4_hnapt.new_dip)); ++ } ++ else if (IS_IPV6_1T_ROUTE(entry)) { ++ NAT_PRINT("Information Block 2: %08X\n", entry->ipv6_1t_route.info_blk2); ++ NAT_PRINT("Create IPv6 Route entry\n"); ++ NAT_PRINT("Destination IPv6: %08X:%08X:%08X:%08X", ++ entry->ipv6_1t_route.ipv6_dip3, entry->ipv6_1t_route.ipv6_dip2, ++ entry->ipv6_1t_route.ipv6_dip1, entry->ipv6_1t_route.ipv6_dip0); ++ } ++ else if (IS_IPV4_DSLITE(entry)) { ++ NAT_PRINT("Information Block 2: %08X\n", entry->ipv4_dslite.info_blk2); ++ NAT_PRINT("Create IPv4 Ds-Lite entry\n"); ++ NAT_PRINT ++ ("IPv4 Ds-Lite: %u.%u.%u.%u.%d->%u.%u.%u.%u:%d\n ", ++ IP_FORMAT3(entry->ipv4_dslite.sip), IP_FORMAT2(entry->ipv4_dslite.sip), ++ IP_FORMAT1(entry->ipv4_dslite.sip), IP_FORMAT0(entry->ipv4_dslite.sip), ++ entry->ipv4_dslite.sport, ++ IP_FORMAT3(entry->ipv4_dslite.dip), IP_FORMAT2(entry->ipv4_dslite.dip), ++ IP_FORMAT1(entry->ipv4_dslite.dip), IP_FORMAT0(entry->ipv4_dslite.dip), ++ entry->ipv4_dslite.dport); ++ NAT_PRINT("EG DIPv6: %08X:%08X:%08X:%08X->%08X:%08X:%08X:%08X\n", ++ entry->ipv4_dslite.tunnel_sipv6_0, entry->ipv4_dslite.tunnel_sipv6_1, ++ entry->ipv4_dslite.tunnel_sipv6_2, entry->ipv4_dslite.tunnel_sipv6_3, ++ entry->ipv4_dslite.tunnel_dipv6_0, entry->ipv4_dslite.tunnel_dipv6_1, ++ entry->ipv4_dslite.tunnel_dipv6_2, entry->ipv4_dslite.tunnel_dipv6_3); ++ } ++ else if (IS_IPV6_3T_ROUTE(entry)) { ++ NAT_PRINT("Information Block 2: %08X\n", entry->ipv6_3t_route.info_blk2); ++ NAT_PRINT("Create IPv6 3-Tuple entry\n"); ++ NAT_PRINT ++ ("ING SIPv6->DIPv6: %08X:%08X:%08X:%08X-> %08X:%08X:%08X:%08X (Prot=%d)\n", ++ entry->ipv6_3t_route.ipv6_sip0, entry->ipv6_3t_route.ipv6_sip1, ++ entry->ipv6_3t_route.ipv6_sip2, entry->ipv6_3t_route.ipv6_sip3, ++ entry->ipv6_3t_route.ipv6_dip0, entry->ipv6_3t_route.ipv6_dip1, ++ entry->ipv6_3t_route.ipv6_dip2, entry->ipv6_3t_route.ipv6_dip3, ++ entry->ipv6_3t_route.prot); ++ } ++ else if (IS_IPV6_5T_ROUTE(entry)) { ++ NAT_PRINT("Information Block 2: %08X\n", entry->ipv6_5t_route.info_blk2); ++ NAT_PRINT("Create IPv6 5-Tuple entry\n"); ++ if (IS_IPV6_FLAB_EBL()) { ++ NAT_PRINT ++ ("ING SIPv6->DIPv6: %08X:%08X:%08X:%08X-> %08X:%08X:%08X:%08X (Flow Label=%08X)\n", ++ entry->ipv6_5t_route.ipv6_sip0, entry->ipv6_5t_route.ipv6_sip1, ++ entry->ipv6_5t_route.ipv6_sip2, entry->ipv6_5t_route.ipv6_sip3, ++ entry->ipv6_5t_route.ipv6_dip0, entry->ipv6_5t_route.ipv6_dip1, ++ entry->ipv6_5t_route.ipv6_dip2, entry->ipv6_5t_route.ipv6_dip3, ++ ((entry->ipv6_5t_route.sport << 16) | (entry->ipv6_5t_route. ++ dport)) & 0xFFFFF); ++ } else { ++ NAT_PRINT ++ ("ING SIPv6->DIPv6: %08X:%08X:%08X:%08X:%d-> %08X:%08X:%08X:%08X:%d\n", ++ entry->ipv6_5t_route.ipv6_sip0, entry->ipv6_5t_route.ipv6_sip1, ++ entry->ipv6_5t_route.ipv6_sip2, entry->ipv6_5t_route.ipv6_sip3, ++ entry->ipv6_5t_route.sport, entry->ipv6_5t_route.ipv6_dip0, ++ entry->ipv6_5t_route.ipv6_dip1, entry->ipv6_5t_route.ipv6_dip2, ++ entry->ipv6_5t_route.ipv6_dip3, entry->ipv6_5t_route.dport); ++ } ++ } ++ else if (IS_IPV6_6RD(entry)) { ++ NAT_PRINT("Information Block 2: %08X\n", entry->ipv6_6rd.info_blk2); ++ NAT_PRINT("Create IPv6 6RD entry\n"); ++ if (IS_IPV6_FLAB_EBL()) { ++ NAT_PRINT ++ ("ING SIPv6->DIPv6: %08X:%08X:%08X:%08X-> %08X:%08X:%08X:%08X (Flow Label=%08X)\n", ++ entry->ipv6_6rd.ipv6_sip0, entry->ipv6_6rd.ipv6_sip1, ++ entry->ipv6_6rd.ipv6_sip2, entry->ipv6_6rd.ipv6_sip3, ++ entry->ipv6_6rd.ipv6_dip0, entry->ipv6_6rd.ipv6_dip1, ++ entry->ipv6_6rd.ipv6_dip2, entry->ipv6_6rd.ipv6_dip3, ++ ((entry->ipv6_5t_route.sport << 16) | (entry->ipv6_5t_route. ++ dport)) & 0xFFFFF); ++ } else { ++ NAT_PRINT ++ ("ING SIPv6->DIPv6: %08X:%08X:%08X:%08X:%d-> %08X:%08X:%08X:%08X:%d\n", ++ entry->ipv6_6rd.ipv6_sip0, entry->ipv6_6rd.ipv6_sip1, ++ entry->ipv6_6rd.ipv6_sip2, entry->ipv6_6rd.ipv6_sip3, ++ entry->ipv6_6rd.sport, entry->ipv6_6rd.ipv6_dip0, ++ entry->ipv6_6rd.ipv6_dip1, entry->ipv6_6rd.ipv6_dip2, ++ entry->ipv6_6rd.ipv6_dip3, entry->ipv6_6rd.dport); ++ } ++ ++ } ++ if (IS_IPV4_HNAPT(entry) || IS_IPV4_HNAT(entry)) { ++ NAT_PRINT("DMAC=%02X:%02X:%02X:%02X:%02X:%02X SMAC=%02X:%02X:%02X:%02X:%02X:%02X\n", ++ entry->ipv4_hnapt.dmac_hi[3], entry->ipv4_hnapt.dmac_hi[2], ++ entry->ipv4_hnapt.dmac_hi[1], entry->ipv4_hnapt.dmac_hi[0], ++ entry->ipv4_hnapt.dmac_lo[1], entry->ipv4_hnapt.dmac_lo[0], ++ entry->ipv4_hnapt.smac_hi[3], entry->ipv4_hnapt.smac_hi[2], ++ entry->ipv4_hnapt.smac_hi[1], entry->ipv4_hnapt.smac_hi[0], ++ entry->ipv4_hnapt.smac_lo[1], entry->ipv4_hnapt.smac_lo[0]); ++ NAT_PRINT("=========================================\n\n"); ++ } ++ else { ++ NAT_PRINT("DMAC=%02X:%02X:%02X:%02X:%02X:%02X SMAC=%02X:%02X:%02X:%02X:%02X:%02X\n", ++ entry->ipv6_5t_route.dmac_hi[3], entry->ipv6_5t_route.dmac_hi[2], ++ entry->ipv6_5t_route.dmac_hi[1], entry->ipv6_5t_route.dmac_hi[0], ++ entry->ipv6_5t_route.dmac_lo[1], entry->ipv6_5t_route.dmac_lo[0], ++ entry->ipv6_5t_route.smac_hi[3], entry->ipv6_5t_route.smac_hi[2], ++ entry->ipv6_5t_route.smac_hi[1], entry->ipv6_5t_route.smac_hi[0], ++ entry->ipv6_5t_route.smac_lo[1], entry->ipv6_5t_route.smac_lo[0]); ++ NAT_PRINT("=========================================\n\n"); ++ } ++ ++ if (_hwnat_info.features & PACKET_SAMPLING) { ++ p = (uint32_t *)ps_entry; ++ ++ NAT_PRINT("=========================\n", index, ps_entry); ++ for (i = 0; i < 4; i++) ++ pr_debug("%02d: %08X\n", i, *(p + i)); ++ } ++} ++ ++int MDrv_HWNAT_Foe_Get_All_Entries(struct hwnat_args *opt1) ++{ ++ struct foe_entry *entry; ++ int hash_index = 0; ++ int count = 0; /* valid entry count */ ++ ++ for (hash_index = 0; hash_index < FOE_4TB_SIZ; hash_index++) { ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, hash_index); ++ if (entry->bfib1.state == opt1->entry_state) { ++ opt1->entries[count].hash_index = hash_index; ++ opt1->entries[count].pkt_type = entry->ipv4_hnapt.bfib1.pkt_type; ++ ++ if (IS_IPV4_HNAT(entry)) { ++ opt1->entries[count].ing_sipv4 = entry->ipv4_hnapt.sip; ++ opt1->entries[count].ing_dipv4 = entry->ipv4_hnapt.dip; ++ opt1->entries[count].eg_sipv4 = entry->ipv4_hnapt.new_sip; ++ opt1->entries[count].eg_dipv4 = entry->ipv4_hnapt.new_dip; ++ count++; ++ } ++ else if (IS_IPV4_HNAPT(entry)) { ++ opt1->entries[count].ing_sipv4 = entry->ipv4_hnapt.sip; ++ opt1->entries[count].ing_dipv4 = entry->ipv4_hnapt.dip; ++ opt1->entries[count].eg_sipv4 = entry->ipv4_hnapt.new_sip; ++ opt1->entries[count].eg_dipv4 = entry->ipv4_hnapt.new_dip; ++ opt1->entries[count].ing_sp = entry->ipv4_hnapt.sport; ++ opt1->entries[count].ing_dp = entry->ipv4_hnapt.dport; ++ opt1->entries[count].eg_sp = entry->ipv4_hnapt.new_sport; ++ opt1->entries[count].eg_dp = entry->ipv4_hnapt.new_dport; ++ count++; ++ } ++ else if (IS_IPV6_1T_ROUTE(entry)) { ++ opt1->entries[count].ing_dipv6_0 = entry->ipv6_1t_route.ipv6_dip3; ++ opt1->entries[count].ing_dipv6_1 = entry->ipv6_1t_route.ipv6_dip2; ++ opt1->entries[count].ing_dipv6_2 = entry->ipv6_1t_route.ipv6_dip1; ++ opt1->entries[count].ing_dipv6_3 = entry->ipv6_1t_route.ipv6_dip0; ++ count++; ++ } ++ else if (IS_IPV4_DSLITE(entry)) { ++ opt1->entries[count].ing_sipv4 = entry->ipv4_dslite.sip; ++ opt1->entries[count].ing_dipv4 = entry->ipv4_dslite.dip; ++ opt1->entries[count].ing_sp = entry->ipv4_dslite.sport; ++ opt1->entries[count].ing_dp = entry->ipv4_dslite.dport; ++ opt1->entries[count].eg_sipv6_0 = entry->ipv4_dslite.tunnel_sipv6_0; ++ opt1->entries[count].eg_sipv6_1 = entry->ipv4_dslite.tunnel_sipv6_1; ++ opt1->entries[count].eg_sipv6_2 = entry->ipv4_dslite.tunnel_sipv6_2; ++ opt1->entries[count].eg_sipv6_3 = entry->ipv4_dslite.tunnel_sipv6_3; ++ opt1->entries[count].eg_dipv6_0 = entry->ipv4_dslite.tunnel_dipv6_0; ++ opt1->entries[count].eg_dipv6_1 = entry->ipv4_dslite.tunnel_dipv6_1; ++ opt1->entries[count].eg_dipv6_2 = entry->ipv4_dslite.tunnel_dipv6_2; ++ opt1->entries[count].eg_dipv6_3 = entry->ipv4_dslite.tunnel_dipv6_3; ++ count++; ++ } ++ else if (IS_IPV6_3T_ROUTE(entry)) { ++ opt1->entries[count].ing_sipv6_0 = entry->ipv6_3t_route.ipv6_sip0; ++ opt1->entries[count].ing_sipv6_1 = entry->ipv6_3t_route.ipv6_sip1; ++ opt1->entries[count].ing_sipv6_2 = entry->ipv6_3t_route.ipv6_sip2; ++ opt1->entries[count].ing_sipv6_3 = entry->ipv6_3t_route.ipv6_sip3; ++ opt1->entries[count].ing_dipv6_0 = entry->ipv6_3t_route.ipv6_dip0; ++ opt1->entries[count].ing_dipv6_1 = entry->ipv6_3t_route.ipv6_dip1; ++ opt1->entries[count].ing_dipv6_2 = entry->ipv6_3t_route.ipv6_dip2; ++ opt1->entries[count].ing_dipv6_3 = entry->ipv6_3t_route.ipv6_dip3; ++ opt1->entries[count].prot = entry->ipv6_3t_route.prot; ++ count++; ++ } ++ else if (IS_IPV6_5T_ROUTE(entry)) { ++ opt1->entries[count].ing_sipv6_0 = entry->ipv6_5t_route.ipv6_sip0; ++ opt1->entries[count].ing_sipv6_1 = entry->ipv6_5t_route.ipv6_sip1; ++ opt1->entries[count].ing_sipv6_2 = entry->ipv6_5t_route.ipv6_sip2; ++ opt1->entries[count].ing_sipv6_3 = entry->ipv6_5t_route.ipv6_sip3; ++ opt1->entries[count].ing_sp = entry->ipv6_5t_route.sport; ++ opt1->entries[count].ing_dp = entry->ipv6_5t_route.dport; ++ ++ opt1->entries[count].ing_dipv6_0 = entry->ipv6_5t_route.ipv6_dip0; ++ opt1->entries[count].ing_dipv6_1 = entry->ipv6_5t_route.ipv6_dip1; ++ opt1->entries[count].ing_dipv6_2 = entry->ipv6_5t_route.ipv6_dip2; ++ opt1->entries[count].ing_dipv6_3 = entry->ipv6_5t_route.ipv6_dip3; ++ opt1->entries[count].ipv6_flowlabel = IS_IPV6_FLAB_EBL(); ++ count++; ++ } ++ else if (IS_IPV6_6RD(entry)) { ++ opt1->entries[count].ing_sipv6_0 = entry->ipv6_6rd.ipv6_sip0; ++ opt1->entries[count].ing_sipv6_1 = entry->ipv6_6rd.ipv6_sip1; ++ opt1->entries[count].ing_sipv6_2 = entry->ipv6_6rd.ipv6_sip2; ++ opt1->entries[count].ing_sipv6_3 = entry->ipv6_6rd.ipv6_sip3; ++ ++ opt1->entries[count].ing_dipv6_0 = entry->ipv6_6rd.ipv6_dip0; ++ opt1->entries[count].ing_dipv6_1 = entry->ipv6_6rd.ipv6_dip1; ++ opt1->entries[count].ing_dipv6_2 = entry->ipv6_6rd.ipv6_dip2; ++ opt1->entries[count].ing_dipv6_3 = entry->ipv6_6rd.ipv6_dip3; ++ opt1->entries[count].ing_sp = entry->ipv6_6rd.sport; ++ opt1->entries[count].ing_dp = entry->ipv6_6rd.dport; ++ opt1->entries[count].ipv6_flowlabel = IS_IPV6_FLAB_EBL(); ++ ++ opt1->entries[count].eg_sipv4 = entry->ipv6_6rd.tunnel_sipv4; ++ opt1->entries[count].eg_dipv4 = entry->ipv6_6rd.tunnel_dipv4; ++ count++; ++ } ++ } ++ } ++ opt1->num_of_entries = count; ++ if (_hwnat_info.features & PPTP_L2TP) { ++ /* pptp_l2tp_fdb_dump(); */ ++ } ++ ++ if (opt1->num_of_entries > 0) ++ return HWNAT_SUCCESS; ++ else ++ return HWNAT_ENTRY_NOT_FOUND; ++} ++ ++int MDrv_HWNAT_Foe_Set_Bind(struct hwnat_args *opt1) ++{ ++ struct foe_entry *entry; ++ ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, opt1->entry_num); ++ ++ /* restore right information block1 */ ++ entry->bfib1.time_stamp = MHAL_HWNAT_Get_TimeStamp(); ++ entry->bfib1.state = BIND; ++ ++ return HWNAT_SUCCESS; ++} ++ ++int MDrv_HWNAT_Foe_Set_Unbind(struct hwnat_args *opt) ++{ ++ struct foe_entry *entry; ++ ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, opt->entry_num); ++ ++ entry->ipv4_hnapt.udib1.state = INVALID; ++ entry->ipv4_hnapt.udib1.time_stamp = MHAL_HWNAT_Get_TimeStamp() & 0xFF; ++ ++ MHal_HWNAT_Enable_Cache(); /*clear HWNAT cache */ ++ ++ return HWNAT_SUCCESS; ++} ++ ++ ++int MDrv_HWNAT_Foe_Drop_Entry(struct hwnat_args *opt) ++{ ++ struct foe_entry *entry; ++ unsigned int entry_num = opt->entry_num; ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, entry_num); ++ ++ entry->ipv4_hnapt.iblk2.dp = 7; ++ ++ MHal_HWNAT_Enable_Cache(); /*clear HWNAT cache */ ++ ++ return HWNAT_SUCCESS; ++} ++ ++int MDrv_HWNAT_Foe_Delete_Entry(uint32_t entry_num) ++{ ++ struct foe_entry *entry; ++ ++ entry = FOE_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_foe_base, entry_num); ++ memset(entry, 0, sizeof(struct foe_entry)); ++ MHal_HWNAT_Enable_Cache(); /*clear HWNAT cache */ ++ ++ return HWNAT_SUCCESS; ++} ++ ++void MDrv_HWNAT_Foe_Clean_All_Entries(void) ++{ ++ u32 foe_tbl_size; ++ ++ foe_tbl_size = FOE_4TB_SIZ * sizeof(struct foe_entry); ++ memset(_hwnat_info.ppe_foe_base, 0, foe_tbl_size); ++ MHal_HWNAT_Enable_Cache(); /*clear HWNAT cache */ ++} ++EXPORT_SYMBOL(MDrv_HWNAT_Foe_Clean_All_Entries); ++ ++ ++void _MDrv_HWNAT_Set_L2_Info(struct foe_entry *entry, struct hwnat_tuple *opt) ++{ ++ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv4_hnapt.dmac_hi, opt->dmac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv4_hnapt.dmac_lo, opt->dmac); ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv4_hnapt.smac_hi, opt->smac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv4_hnapt.smac_lo, opt->smac); ++ entry->ipv4_hnapt.vlan1 = opt->vlan1; ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ /* not support vlan2*/ ++ } ++ else { ++ entry->ipv4_hnapt.vlan2 = opt->vlan2; ++ } ++ entry->ipv4_hnapt.pppoe_id = opt->pppoe_id; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv6_5t_route.dmac_hi, opt->dmac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv6_5t_route.dmac_lo, opt->dmac); ++ MDrv_HWNAT_Foe_Set_High_Mac(entry->ipv6_5t_route.smac_hi, opt->smac); ++ MDrv_HWNAT_Foe_Set_Low_Mac(entry->ipv6_5t_route.smac_lo, opt->smac); ++ entry->ipv6_5t_route.vlan1 = opt->vlan1; ++ if (_hwnat_info.features & HW_NAT_ARCH_WIFI_WDMA) { ++ /*wifi hwnat not support vlan2*/ ++ } ++ else { ++ entry->ipv6_5t_route.vlan2 = opt->vlan2; ++ } ++ entry->ipv6_5t_route.pppoe_id = opt->pppoe_id; ++ } ++ } ++} ++ ++void _MDrv_HWNAT_Set_L3_Info(struct foe_entry *entry, struct hwnat_tuple *opt) ++{ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ entry->ipv4_hnapt.sip=opt->ing_sipv4; ++ entry->ipv4_hnapt.dip=opt->ing_dipv4; ++ entry->ipv4_hnapt.new_sip = opt->eg_sipv4; ++ entry->ipv4_hnapt.new_dip = opt->eg_dipv4; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ entry->ipv6_5t_route.ipv6_sip0 = opt->ing_sipv6_0; ++ entry->ipv6_5t_route.ipv6_sip1 = opt->ing_sipv6_1; ++ entry->ipv6_5t_route.ipv6_sip2 = opt->ing_sipv6_2; ++ entry->ipv6_5t_route.ipv6_sip3 = opt->ing_sipv6_3; ++ ++ entry->ipv6_5t_route.ipv6_dip0 = opt->ing_dipv6_0; ++ entry->ipv6_5t_route.ipv6_dip1 = opt->ing_dipv6_1; ++ entry->ipv6_5t_route.ipv6_dip2 = opt->ing_dipv6_2; ++ entry->ipv6_5t_route.ipv6_dip3 = opt->ing_dipv6_3; ++ } ++/* ++ NAT_PRINT("opt->ing_sipv6_0 = %x\n", opt->ing_sipv6_0); ++ NAT_PRINT("opt->ing_sipv6_1 = %x\n", opt->ing_sipv6_1); ++ NAT_PRINT("opt->ing_sipv6_2 = %x\n", opt->ing_sipv6_2); ++ NAT_PRINT("opt->ing_sipv6_3 = %x\n", opt->ing_sipv6_3); ++ NAT_PRINT("opt->ing_dipv6_0 = %x\n", opt->ing_dipv6_0); ++ NAT_PRINT("opt->ing_dipv6_1 = %x\n", opt->ing_dipv6_1); ++ NAT_PRINT("opt->ing_dipv6_2 = %x\n", opt->ing_dipv6_2); ++ NAT_PRINT("opt->ing_dipv6_3 = %x\n", opt->ing_dipv6_3); ++ ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_sip0 = %x\n", entry->ipv6_5t_route.ipv6_sip0); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_sip1 = %x\n", entry->ipv6_5t_route.ipv6_sip1); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_sip2 = %x\n", entry->ipv6_5t_route.ipv6_sip2); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_sip3 = %x\n", entry->ipv6_5t_route.ipv6_sip3); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_dip0 = %x\n", entry->ipv6_5t_route.ipv6_dip0); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_dip1 = %x\n", entry->ipv6_5t_route.ipv6_dip1); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_dip2 = %x\n", entry->ipv6_5t_route.ipv6_dip2); ++ NAT_PRINT("entry->ipv6_5t_route.ipv6_dip3 = %x\n", entry->ipv6_5t_route.ipv6_dip3); ++*/ ++ } ++} ++ ++void _MDrv_HWNAT_Set_L4_Info(struct foe_entry *entry, struct hwnat_tuple *opt) ++{ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ entry->ipv4_hnapt.dport = opt->ing_dp; ++ entry->ipv4_hnapt.sport = opt->ing_sp; ++ entry->ipv4_hnapt.new_dport = opt->eg_dp; ++ entry->ipv4_hnapt.new_sport = opt->eg_sp; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ entry->ipv6_5t_route.dport = opt->ing_dp; ++ entry->ipv6_5t_route.sport = opt->ing_sp; ++ } ++ ++ } ++} ++ ++void _MDrv_HWNAT_Set_Ib1_Info(struct foe_entry *entry, struct hwnat_tuple *opt) ++{ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ entry->ipv4_hnapt.bfib1.pkt_type = IPV4_NAPT; ++ entry->ipv4_hnapt.bfib1.sta = 1; ++ entry->ipv4_hnapt.bfib1.udp = opt->is_udp; /* tcp/udp */ ++ entry->ipv4_hnapt.bfib1.state = BIND; ++ entry->ipv4_hnapt.bfib1.ka = 1; /* keepalive */ ++ entry->ipv4_hnapt.bfib1.ttl = 0; /* TTL-1 */ ++ entry->ipv4_hnapt.bfib1.psn = opt->pppoe_act; /* insert / remove */ ++ entry->ipv4_hnapt.bfib1.vlan_layer = opt->vlan_layer; ++ entry->ipv4_hnapt.bfib1.time_stamp = MHAL_HWNAT_Get_TimeStamp()&0xFFFF; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ entry->ipv6_5t_route.bfib1.pkt_type = IPV6_ROUTING; ++ entry->ipv6_5t_route.bfib1.sta = 1; ++ entry->ipv6_5t_route.bfib1.udp = opt->is_udp; /* tcp/udp */ ++ entry->ipv6_5t_route.bfib1.state = BIND; ++ entry->ipv6_5t_route.bfib1.ka = 1; /* keepalive */ ++ entry->ipv6_5t_route.bfib1.ttl = 0; /* TTL-1 */ ++ entry->ipv6_5t_route.bfib1.psn = opt->pppoe_act; /* insert / remove */ ++ entry->ipv6_5t_route.bfib1.vlan_layer = opt->vlan_layer; ++ entry->ipv6_5t_route.bfib1.time_stamp = MHAL_HWNAT_Get_TimeStamp()&0xFFFF; ++ } ++ } ++} ++ ++void _MDrv_HWNAT_Set_Ib2_Info(struct foe_entry *entry, struct hwnat_tuple *opt) ++{ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ entry->ipv4_hnapt.iblk2.dp = opt->dst_port; /* 0:cpu, 1:GE1 */ ++ entry->ipv4_hnapt.iblk2.dscp = opt->dscp; ++ entry->ipv4_hnapt.iblk2.acnt = opt->dst_port; ++ ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ entry->ipv6_5t_route.iblk2.dp = opt->dst_port; /* 0:cpu, 1:GE1 */ ++ entry->ipv6_5t_route.iblk2.dscp = opt->dscp; ++ entry->ipv6_5t_route.iblk2.acnt = opt->dst_port; ++ } ++ } ++} ++ ++void _MDrv_HWNAT_Semi_Mode_Set_Bind(struct foe_entry *entry, struct hwnat_tuple *opt) ++{ ++ uint32_t current_time; ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ /* Set Current time to time_stamp field in information block 1 */ ++ current_time = MHAL_HWNAT_Get_TimeStamp() & 0xFFFF; ++ entry->bfib1.time_stamp = (uint16_t) current_time; ++ /* Ipv4: TTL / Ipv6: Hot Limit filed */ ++ entry->ipv4_hnapt.bfib1.ttl = DFL_FOE_TTL_REGEN; ++ /* enable cache by default */ ++ entry->ipv4_hnapt.bfib1.cah = 1; ++ /* Change Foe Entry State to Binding State */ ++ entry->bfib1.state = BIND; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ /* Set Current time to time_stamp field in information block 1 */ ++ current_time = MHAL_HWNAT_Get_TimeStamp() & 0xFFFF; ++ entry->bfib1.time_stamp = (uint16_t) current_time; ++ /* Ipv4: TTL / Ipv6: Hot Limit filed */ ++ entry->ipv4_hnapt.bfib1.ttl = DFL_FOE_TTL_REGEN; ++ /* enable cache by default */ ++ entry->ipv4_hnapt.bfib1.cah = 1; ++ /* Change Foe Entry State to Binding State */ ++ entry->bfib1.state = BIND; ++ } ++ } ++} ++ ++ ++int _MDrv_HWNAT_Zero_DoneBit(struct foe_entry * foe_entry) ++{ ++ if (IS_IPV4_HNAT(foe_entry) || IS_IPV4_HNAPT(foe_entry)) { ++ foe_entry->ipv4_hnapt.resv1 = 0; ++ } ++ else if (_hwnat_info.features & NAT_IPV6) { ++ if (IS_IPV4_DSLITE(foe_entry)) { ++ foe_entry->ipv4_dslite.resv1 = 0; ++ } else if (IS_IPV6_3T_ROUTE(foe_entry)) { ++ foe_entry->ipv6_3t_route.resv1 = 0; ++ } else if (IS_IPV6_5T_ROUTE(foe_entry)) { ++ foe_entry->ipv6_5t_route.resv1 = 0; ++ } else if (IS_IPV6_6RD(foe_entry)) { ++ foe_entry->ipv6_6rd.resv1 = 0; ++ } else { ++ NAT_PRINT("%s:get packet format something wrong\n", __func__); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++int _MDrv_HWNAT_Get_DoneBit(struct foe_entry * foe_entry) ++{ ++ int done_bit = 0; ++ ++ if (IS_IPV4_HNAT(foe_entry) || IS_IPV4_HNAPT(foe_entry)) { ++ done_bit = foe_entry->ipv4_hnapt.resv1; ++ } ++ else if (_hwnat_info.features & NAT_IPV6) { ++ if (IS_IPV4_DSLITE(foe_entry)) { ++ done_bit = foe_entry->ipv4_dslite.resv1; ++ } else if (IS_IPV6_3T_ROUTE(foe_entry)) { ++ done_bit = foe_entry->ipv6_3t_route.resv1; ++ } else if (IS_IPV6_5T_ROUTE(foe_entry)) { ++ done_bit = foe_entry->ipv6_5t_route.resv1; ++ } else if (IS_IPV6_6RD(foe_entry)) { ++ done_bit = foe_entry->ipv6_6rd.resv1; ++ } else { ++ NAT_PRINT("%s:get packet format something wrong\n", __func__); ++ return -1; ++ } ++ } ++ return done_bit; ++} ++ ++int MDrv_HWNAT_Add_Foe_Entry(struct hwnat_tuple *opt) ++{ ++ struct foe_pri_key key; ++ struct foe_entry *entry = NULL; ++ int32_t hash_index; ++ int done_bit; ++ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ key.ipv4_hnapt.sip=opt->ing_sipv4; ++ key.ipv4_hnapt.dip=opt->ing_dipv4; ++ key.ipv4_hnapt.sport=opt->ing_sp; ++ key.ipv4_hnapt.dport=opt->ing_dp; ++ key.ipv4_hnapt.is_udp=opt->is_udp; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ key.ipv6_routing.sip0=opt->ing_sipv6_0; ++ key.ipv6_routing.sip1=opt->ing_sipv6_1; ++ key.ipv6_routing.sip2=opt->ing_sipv6_2; ++ key.ipv6_routing.sip3=opt->ing_sipv6_3; ++ key.ipv6_routing.dip0=opt->ing_dipv6_0; ++ key.ipv6_routing.dip1=opt->ing_dipv6_1; ++ key.ipv6_routing.dip2=opt->ing_dipv6_2; ++ key.ipv6_routing.dip3=opt->ing_dipv6_3; ++ key.ipv6_routing.sport=opt->ing_sp; ++ key.ipv6_routing.dport=opt->ing_dp; ++ key.ipv6_routing.is_udp=opt->is_udp; ++ } ++ ++ key.pkt_type=opt->pkt_type; ++ if (_hwnat_info.features & HW_NAT_MANUAL_MODE) { ++ hash_index = MDrv_HWNAT_Get_Ppe_Entry_Idx(&key, entry, 0); ++ } ++ else { ++ hash_index = MDrv_HWNAT_Get_Ppe_Entry_Idx(&key, entry, 1); ++ } ++ ++ if(hash_index != -1) { ++ ++ opt->hash_index=hash_index; ++ entry=&ppe_foe_base[hash_index]; ++ ++ if (_hwnat_info.features & HW_NAT_MANUAL_MODE) { ++ _MDrv_HWNAT_Set_L2_Info(entry, opt); ++ _MDrv_HWNAT_Set_L3_Info(entry, opt); ++ _MDrv_HWNAT_Set_L4_Info(entry, opt); ++ _MDrv_HWNAT_Set_Ib1_Info(entry, opt); ++ _MDrv_HWNAT_Set_Ib2_Info(entry, opt); ++ } ++ ++ if (_hwnat_info.features & HW_NAT_SEMI_AUTO_MODE) { ++ done_bit = _MDrv_HWNAT_Get_DoneBit(entry); ++ if (done_bit == 1) { ++ NAT_PRINT("mtk_entry_add number =%d\n", hash_index); ++ } else if (done_bit == 0){ ++ NAT_PRINT("ppe table not ready\n"); ++ return HWNAT_FAIL; ++ } else { ++ NAT_PRINT("%s: done_bit something wrong\n", __func__); ++ return HWNAT_FAIL; ++ } ++ _MDrv_HWNAT_Semi_Mode_Set_Bind(entry, opt); ++ } ++ MDrv_HWNAT_Foe_Dump_Entry(hash_index); ++ return HWNAT_SUCCESS; ++ } ++ ++ return HWNAT_FAIL; ++ ++} ++ ++int MDrv_HWNAT_Delete_Foe_Entry(struct hwnat_tuple *opt) ++{ ++ struct foe_pri_key key; ++ int32_t hash_index; ++ struct foe_entry *entry = NULL; ++ int32_t rply_idx; ++ int done_bit; ++ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ key.ipv4_hnapt.sip=opt->ing_sipv4; ++ key.ipv4_hnapt.dip=opt->ing_dipv4; ++ key.ipv4_hnapt.sport=opt->ing_sp; ++ key.ipv4_hnapt.dport=opt->ing_dp; ++ //key.ipv4_hnapt.is_udp=opt->is_udp; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ key.ipv6_routing.sip0=opt->ing_sipv6_0; ++ key.ipv6_routing.sip1=opt->ing_sipv6_1; ++ key.ipv6_routing.sip2=opt->ing_sipv6_2; ++ key.ipv6_routing.sip3=opt->ing_sipv6_3; ++ key.ipv6_routing.dip0=opt->ing_dipv6_0; ++ key.ipv6_routing.dip1=opt->ing_dipv6_1; ++ key.ipv6_routing.dip2=opt->ing_dipv6_2; ++ key.ipv6_routing.dip3=opt->ing_dipv6_3; ++ key.ipv6_routing.sport=opt->ing_sp; ++ key.ipv6_routing.dport=opt->ing_dp; ++ //key.ipv6_routing.is_udp=opt->is_udp; ++ } ++ ++ key.pkt_type=opt->pkt_type; ++ ++ // find bind entry ++ //hash_index = FoeHashFun(&key,BIND); ++ hash_index = MDrv_HWNAT_Get_Ppe_Entry_Idx(&key, entry, 1);; ++ if(hash_index != -1) { ++ opt->hash_index=hash_index; ++ rply_idx = MDrv_HWNAT_Reply_Ppe_Entry_Idx(opt, hash_index); ++ if (_hwnat_info.features & HW_NAT_SEMI_AUTO_MODE) { ++ entry=&ppe_foe_base[hash_index]; ++ done_bit = _MDrv_HWNAT_Get_DoneBit(entry); ++ if (done_bit == 1) { ++ _MDrv_HWNAT_Zero_DoneBit(entry); ++ } else if (done_bit == 0){ ++ NAT_PRINT("%s : ppe table not ready\n", __func__); ++ return HWNAT_FAIL; ++ } else { ++ NAT_PRINT("%s: done_bit something wrong\n", __func__); ++ _MDrv_HWNAT_Zero_DoneBit(entry); ++ return HWNAT_FAIL; ++ } ++ } ++ MDrv_HWNAT_Foe_Delete_Entry(hash_index); ++ NAT_PRINT("Clear Entry index = %d\n", hash_index); ++ if(rply_idx != -1) { ++ NAT_PRINT("Clear Entry index = %d\n", rply_idx); ++ MDrv_HWNAT_Foe_Delete_Entry(rply_idx); ++ } ++ ++ return HWNAT_SUCCESS; ++ } ++ NAT_PRINT("HWNAT ENTRY NOT FOUND\n"); ++ return HWNAT_ENTRY_NOT_FOUND; ++} ++EXPORT_SYMBOL(MDrv_HWNAT_Delete_Foe_Entry); ++ ++int _MDrv_HWNAT_Get_Five_Tuple(struct sk_buff *skb) ++{ ++ struct ethhdr *eth = NULL; ++ struct iphdr *iph = NULL; ++ struct ipv6hdr *ip6h = NULL; ++ struct tcphdr *th = NULL; ++ struct udphdr *uh = NULL; ++ u8 ipv6_head_len = 0; ++ ++ memset(&ppe_parse_rx_result, 0, sizeof(ppe_parse_rx_result)); ++ eth = (struct ethhdr *)skb->data; ++ ppe_parse_rx_result.eth_type = eth->h_proto; ++ /* set layer4 start addr */ ++ if ((ppe_parse_rx_result.eth_type == htons(ETH_P_IP)) || ++ (ppe_parse_rx_result.eth_type == htons(ETH_P_PPP_SES) && ++ (ppe_parse_rx_result.ppp_tag == htons(PPP_IP)))) { ++ ++ iph = (struct iphdr *)(skb->data + ETH_HLEN); ++ memcpy(&ppe_parse_rx_result.iph, iph, sizeof(struct iphdr)); ++ if (iph->protocol == IPPROTO_TCP) { ++ skb_set_transport_header(skb, ETH_HLEN + (iph->ihl * 4)); ++ th = (struct tcphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_rx_result.th, th, sizeof(struct tcphdr)); ++ ppe_parse_rx_result.pkt_type = IPV4_HNAPT; ++ if (iph->frag_off & htons(IP_MF | IP_OFFSET)) { ++ return 1; ++ } ++ } else if (iph->protocol == IPPROTO_UDP) { ++ skb_set_transport_header(skb, ETH_HLEN + (iph->ihl * 4)); ++ uh = (struct udphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_rx_result.uh, uh, sizeof(struct udphdr)); ++ ppe_parse_rx_result.pkt_type = IPV4_HNAPT; ++ if (iph->frag_off & htons(IP_MF | IP_OFFSET)) ++ { ++ if (USE_3T_UDP_FRAG == 0) ++ return 1; ++ } ++ } else if (iph->protocol == IPPROTO_GRE) { ++ if ((_hwnat_info.features & PPTP_L2TP) == 0) { ++ if (_hwnat_info.debug_level >= 2) ++ NAT_PRINT("PPTP L2TP is disabled\n"); ++ /* do nothing */ ++ return 1; ++ } ++ } ++ else if ((_hwnat_info.features & NAT_IPV6) && (iph->protocol == IPPROTO_IPV6)) { ++ ip6h = (struct ipv6hdr *)((uint8_t *)iph + iph->ihl * 4); ++ memcpy(&ppe_parse_rx_result.ip6h, ip6h, sizeof(struct ipv6hdr)); ++ if (ip6h->nexthdr == NEXTHDR_TCP) { ++ skb_set_transport_header(skb, ETH_HLEN + (sizeof(struct ipv6hdr))); ++ th = (struct tcphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_rx_result.th.source, &th->source, sizeof(th->source)); ++ memcpy(&ppe_parse_rx_result.th.dest, &th->dest, sizeof(th->dest)); ++ } else if (ip6h->nexthdr == NEXTHDR_UDP) { ++ skb_set_transport_header(skb, ETH_HLEN + (sizeof(struct ipv6hdr))); ++ uh = (struct udphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_rx_result.uh.source, &uh->source, sizeof(uh->source)); ++ memcpy(&ppe_parse_rx_result.uh.dest, &uh->dest, sizeof(uh->dest)); ++ } ++ ppe_parse_rx_result.pkt_type = IPV6_6RD; ++ } ++ else { ++ /* Packet format is not supported */ ++ return 1; ++ } ++ ++ } else if (ppe_parse_rx_result.eth_type == htons(ETH_P_IPV6) || ++ (ppe_parse_rx_result.eth_type == htons(ETH_P_PPP_SES) && ++ ppe_parse_rx_result.ppp_tag == htons(PPP_IPV6))) { ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++ memcpy(&ppe_parse_rx_result.ip6h, ip6h, sizeof(struct ipv6hdr)); ++ if (ip6h->nexthdr == NEXTHDR_TCP) { ++ skb_set_transport_header(skb, ETH_HLEN + (sizeof(struct ipv6hdr))); ++ th = (struct tcphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_rx_result.th, th, sizeof(struct tcphdr)); ++ ppe_parse_rx_result.pkt_type = IPV6_5T_ROUTE; ++ } else if (ip6h->nexthdr == NEXTHDR_UDP) { ++ skb_set_transport_header(skb, ETH_HLEN + (sizeof(struct ipv6hdr))); ++ uh = (struct udphdr *)skb_transport_header(skb); ++ memcpy(&ppe_parse_rx_result.uh, uh, sizeof(struct udphdr)); ++ ppe_parse_rx_result.pkt_type = IPV6_5T_ROUTE; ++ } else if (ip6h->nexthdr == NEXTHDR_IPIP) { ++ ipv6_head_len = sizeof(struct iphdr); ++ memcpy(&ppe_parse_rx_result.iph, ip6h + ipv6_head_len, ++ sizeof(struct iphdr)); ++ ppe_parse_rx_result.pkt_type = IPV4_DSLITE; ++ } else { ++ ppe_parse_rx_result.pkt_type = IPV6_3T_ROUTE; ++ } ++ ++ } else { ++ return 1; ++ } ++#if(0) ++if (_hwnat_info.debug_level >= 2) { ++ HWNAT_MSG_DBG("--------------\n"); ++ HWNAT_MSG_DBG("DMAC:%02X:%02X:%02X:%02X:%02X:%02X\n", ++ ppe_parse_rx_result.dmac[0], ppe_parse_rx_result.dmac[1], ++ ppe_parse_rx_result.dmac[2], ppe_parse_rx_result.dmac[3], ++ ppe_parse_rx_result.dmac[4], ppe_parse_rx_result.dmac[5]); ++ HWNAT_MSG_DBG("SMAC:%02X:%02X:%02X:%02X:%02X:%02X\n", ++ ppe_parse_rx_result.smac[0], ppe_parse_rx_result.smac[1], ++ ppe_parse_rx_result.smac[2], ppe_parse_rx_result.smac[3], ++ ppe_parse_rx_result.smac[4], ppe_parse_rx_result.smac[5]); ++ HWNAT_MSG_DBG("Eth_Type=%x\n", ppe_parse_rx_result.eth_type); ++ ++ HWNAT_MSG_DBG("PKT_TYPE=%s\n", ++ ppe_parse_rx_result.pkt_type == ++ 0 ? "IPV4_HNAT" : ppe_parse_rx_result.pkt_type == ++ 1 ? "IPV4_HNAPT" : ppe_parse_rx_result.pkt_type == ++ 3 ? "IPV4_DSLITE" : ppe_parse_rx_result.pkt_type == ++ 4 ? "IPV6_ROUTE" : ppe_parse_rx_result.pkt_type == 5 ? "IPV6_6RD" : "Unknown"); ++ if (ppe_parse_rx_result.pkt_type == IPV4_HNAT) { ++ HWNAT_MSG_DBG("SIP=%s\n", ip_to_str(ntohl(ppe_parse_rx_result.iph.saddr))); ++ HWNAT_MSG_DBG("DIP=%s\n", ip_to_str(ntohl(ppe_parse_rx_result.iph.daddr))); ++ HWNAT_MSG_DBG("TOS=%x\n", ntohs(ppe_parse_rx_result.iph.tos)); ++ } else if (ppe_parse_rx_result.pkt_type == IPV4_HNAPT) { ++ HWNAT_MSG_DBG("SIP=%s\n", ip_to_str(ntohl(ppe_parse_rx_result.iph.saddr))); ++ HWNAT_MSG_DBG("DIP=%s\n", ip_to_str(ntohl(ppe_parse_rx_result.iph.daddr))); ++ HWNAT_MSG_DBG("TOS=%x\n", ntohs(ppe_parse_rx_result.iph.tos)); ++ ++ if (ppe_parse_rx_result.iph.protocol == IPPROTO_TCP) { ++ HWNAT_MSG_DBG("TCP SPORT=%d\n", ntohs(ppe_parse_rx_result.th.source)); ++ HWNAT_MSG_DBG("TCP DPORT=%d\n", ntohs(ppe_parse_rx_result.th.dest)); ++ } else if (ppe_parse_rx_result.iph.protocol == IPPROTO_UDP) { ++ HWNAT_MSG_DBG("UDP SPORT=%d\n", ntohs(ppe_parse_rx_result.uh.source)); ++ HWNAT_MSG_DBG("UDP DPORT=%d\n", ntohs(ppe_parse_rx_result.uh.dest)); ++ } ++ } else if (ppe_parse_rx_result.pkt_type == IPV6_6RD) { ++ /* fill in ipv4 6rd entry */ ++ HWNAT_MSG_DBG("packet_type = IPV6_6RD\n"); ++ HWNAT_MSG_DBG("SIP=%s\n", ip_to_str(ntohl(ppe_parse_rx_result.iph.saddr))); ++ HWNAT_MSG_DBG("DIP=%s\n", ip_to_str(ntohl(ppe_parse_rx_result.iph.daddr))); ++ ++ HWNAT_MSG_DBG("Checksum=%x\n", ntohs(ppe_parse_rx_result.iph.check)); ++ HWNAT_MSG_DBG("ipV4 ID =%x\n", ntohs(ppe_parse_rx_result.iph.id)); ++ HWNAT_MSG_DBG("Flag=%x\n", ntohs(ppe_parse_rx_result.iph.frag_off) >> 13); ++ HWNAT_MSG_DBG("TTL=%x\n", ppe_parse_rx_result.iph.ttl); ++ HWNAT_MSG_DBG("TOS=%x\n", ppe_parse_rx_result.iph.tos); ++ } ++ } ++#endif ++ return 0; ++} ++ ++int _MDrv_HWNAT_Decide_Qid(uint16_t hash_index, struct sk_buff * skb) ++{ ++ struct foe_entry *entry; ++ uint32_t saddr; ++ uint32_t daddr; ++ ++ uint32_t ppeSaddr; ++ uint32_t ppeDaddr; ++ uint32_t ppeSport; ++ uint32_t ppeDport; ++ ++ uint32_t sport = 0; ++ uint32_t dport = 0; ++ ++ uint32_t ipv6_sip_127_96; ++ uint32_t ipv6_sip_95_64; ++ uint32_t ipv6_sip_63_32; ++ uint32_t ipv6_sip_31_0; ++ ++ uint32_t ipv6_dip_127_96; ++ uint32_t ipv6_dip_95_64; ++ uint32_t ipv6_dip_63_32; ++ uint32_t ipv6_dip_31_0; ++ ++ uint32_t ppeSaddr_127_96; ++ uint32_t ppeSaddr_95_64; ++ uint32_t ppeSaddr_63_32; ++ uint32_t ppeSaddr_31_0; ++ ++ uint32_t ppeDaddr_127_96; ++ uint32_t ppeDaddr_95_64; ++ uint32_t ppeDaddr_63_32; ++ uint32_t ppeDaddr_31_0; ++ ++ uint32_t ppeSportV6; ++ uint32_t ppeDportV6; ++ ++ entry = &ppe_foe_base[hash_index]; ++ if (IS_IPV4_HNAPT(entry)) { ++ saddr = ntohl(ppe_parse_rx_result.iph.saddr); ++ daddr = ntohl(ppe_parse_rx_result.iph.daddr); ++ if (ppe_parse_rx_result.iph.protocol == IPPROTO_TCP) { ++ sport = ntohs(ppe_parse_rx_result.th.source); ++ dport = ntohs(ppe_parse_rx_result.th.dest); ++ }else if(ppe_parse_rx_result.iph.protocol == IPPROTO_UDP) { ++ sport = ntohs(ppe_parse_rx_result.uh.source); ++ dport = ntohs(ppe_parse_rx_result.uh.dest); ++ } ++ ppeSaddr = entry->ipv4_hnapt.sip; ++ ppeDaddr = entry->ipv4_hnapt.dip; ++ ppeSport = entry->ipv4_hnapt.sport; ++ ppeDport = entry->ipv4_hnapt.dport; ++ if (_hwnat_info.debug_level >= 2) { ++ HWNAT_MSG_DBG("ppeSaddr = %x, ppeDaddr=%x, ppeSport=%d, ppeDport=%d, saddr=%x, daddr=%x, sport= %d, dport=%d\n", ++ ppeSaddr, ppeDaddr, ppeSport, ppeDport, saddr, daddr, sport, dport); ++ } ++ if ((saddr == ppeSaddr) && (daddr == ppeDaddr) ++ && (sport == ppeSport) && (dport == ppeDport) && (entry->bfib1.state == BIND)){ ++ ++ if (entry->ipv4_hnapt.iblk2.dp == 2){ ++ skb->dev = (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH)?dst_port[DPORT_GMAC2]:dst_port[DP_GMAC2]; ++ //if (entry->ipv4_hnapt.iblk2.qid >= 11) ++ if (_hwnat_info.debug_level >= 2) ++ HWNAT_MSG_DBG("qid = %d\n", entry->ipv4_hnapt.iblk2.qid); ++ skb->mark = entry->ipv4_hnapt.iblk2.qid; ++ }else{ ++ skb->dev = (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH)?dst_port[DP_GMAC1]:dst_port[DP_GMAC]; ++ if (_hwnat_info.debug_level >= 2) ++ HWNAT_MSG_DBG("qid = %d\n", entry->ipv4_hnapt.iblk2.qid); ++ skb->mark = entry->ipv4_hnapt.iblk2.qid; ++ } ++ return 0; ++ }else { ++ return -1; ++ } ++ ++ } ++ else if ((_hwnat_info.features & NAT_IPV6)&&(IS_IPV6_5T_ROUTE(entry))) { ++ ipv6_sip_127_96 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[0]); ++ ipv6_sip_95_64 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[1]); ++ ipv6_sip_63_32 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[2]); ++ ipv6_sip_31_0 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[3]); ++ ++ ipv6_dip_127_96 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[0]);; ++ ipv6_dip_95_64 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[1]); ++ ipv6_dip_63_32 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[2]); ++ ipv6_dip_31_0 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[3]); ++ ++ ++ ppeSaddr_127_96 = entry->ipv6_5t_route.ipv6_sip0; ++ ppeSaddr_95_64 = entry->ipv6_5t_route.ipv6_sip1; ++ ppeSaddr_63_32 = entry->ipv6_5t_route.ipv6_sip2; ++ ppeSaddr_31_0 = entry->ipv6_5t_route.ipv6_sip3; ++ ++ ppeDaddr_127_96 = entry->ipv6_5t_route.ipv6_dip0; ++ ppeDaddr_95_64 = entry->ipv6_5t_route.ipv6_dip1; ++ ppeDaddr_63_32 = entry->ipv6_5t_route.ipv6_dip2; ++ ppeDaddr_31_0 = entry->ipv6_5t_route.ipv6_dip3; ++ ++ ppeSportV6 = entry->ipv6_5t_route.sport; ++ ppeDportV6 = entry->ipv6_5t_route.dport; ++ if (ppe_parse_rx_result.iph.protocol == IPPROTO_TCP) { ++ sport = ntohs(ppe_parse_rx_result.th.source); ++ dport = ntohs(ppe_parse_rx_result.th.dest); ++ }else if(ppe_parse_rx_result.iph.protocol == IPPROTO_UDP) { ++ sport = ntohs(ppe_parse_rx_result.uh.source); ++ dport = ntohs(ppe_parse_rx_result.uh.dest); ++ } ++ if ((ipv6_sip_127_96 == ppeSaddr_127_96) && (ipv6_sip_95_64 == ppeSaddr_95_64) ++ && (ipv6_sip_63_32 == ppeSaddr_63_32) && (ipv6_sip_31_0 == ppeSaddr_31_0) && ++ (ipv6_dip_127_96 == ppeDaddr_127_96) && (ipv6_dip_95_64 == ppeDaddr_95_64) ++ && (ipv6_dip_63_32 == ppeDaddr_63_32) && (ipv6_dip_31_0 == ppeDaddr_31_0) && ++ (sport == ppeSportV6) && (dport == ppeDportV6) && ++ (entry->bfib1.state == BIND)){ ++ if (entry->ipv6_5t_route.iblk2.dp == 2){ ++ skb->dev = (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH)?dst_port[DPORT_GMAC2]:dst_port[DP_GMAC2]; ++ ++ //if (entry->ipv6_3t_route.iblk2.qid >= 11) ++ skb->mark = (entry->ipv6_3t_route.iblk2.qid); ++ }else{ ++ skb->dev = (_hwnat_info.features & HW_NAT_WIFI_NEW_ARCH)?dst_port[DP_GMAC1]:dst_port[DP_GMAC]; ++ skb->mark = (entry->ipv6_3t_route.iblk2.qid ); ++ } ++ }else { ++ return -1; ++ } ++ ++ } ++ ++ return 0; ++} ++ ++void MDrv_HWNAT_Set_Qid(struct sk_buff *skb) ++{ ++ struct foe_pri_key key; ++ int32_t hash_index; ++ struct foe_entry *entry = NULL; ++ ++ _MDrv_HWNAT_Get_Five_Tuple(skb); ++ if (ppe_parse_rx_result.pkt_type == IPV4_HNAPT){ ++ key.ipv4_hnapt.sip = ntohl(ppe_parse_rx_result.iph.saddr); ++ key.ipv4_hnapt.dip = ntohl(ppe_parse_rx_result.iph.daddr); ++ ++ if (ppe_parse_rx_result.iph.protocol == IPPROTO_TCP) { ++ key.ipv4_hnapt.sport = ntohs(ppe_parse_rx_result.th.source); ++ key.ipv4_hnapt.dport = ntohs(ppe_parse_rx_result.th.dest); ++ }else if(ppe_parse_rx_result.iph.protocol == IPPROTO_UDP) { ++ key.ipv4_hnapt.sport = ntohs(ppe_parse_rx_result.uh.source); ++ key.ipv4_hnapt.dport = ntohs(ppe_parse_rx_result.uh.dest); ++ } ++ //key.ipv4_hnapt.is_udp=opt->is_udp; ++ }else if (ppe_parse_rx_result.pkt_type == IPV6_5T_ROUTE){ ++ key.ipv6_routing.sip0 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[0]); ++ key.ipv6_routing.sip1 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[1]); ++ key.ipv6_routing.sip2 = ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[2]); ++ key.ipv6_routing.sip3= ntohl(ppe_parse_rx_result.ip6h.saddr.s6_addr32[3]); ++ key.ipv6_routing.dip0 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[0]);; ++ key.ipv6_routing.dip1 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[1]); ++ key.ipv6_routing.dip2 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[2]); ++ key.ipv6_routing.dip3 = ntohl(ppe_parse_rx_result.ip6h.daddr.s6_addr32[3]); ++ if (ppe_parse_rx_result.ip6h.nexthdr == IPPROTO_TCP) { ++ key.ipv6_routing.sport = ntohs(ppe_parse_rx_result.th.source); ++ key.ipv6_routing.dport = ntohs(ppe_parse_rx_result.th.dest); ++ }else if(ppe_parse_rx_result.ip6h.nexthdr == IPPROTO_UDP) { ++ key.ipv6_routing.sport = ntohs(ppe_parse_rx_result.uh.source); ++ key.ipv6_routing.dport = ntohs(ppe_parse_rx_result.uh.dest); ++ } ++ ++ ++ } ++ ++ key.pkt_type = ppe_parse_rx_result.pkt_type; ++ ++ // find bind entry ++ //hash_index = FoeHashFun(&key,BIND); ++ hash_index = MDrv_HWNAT_Get_Ppe_Entry_Idx(&key, entry, 1); ++ if(hash_index != -1) ++ _MDrv_HWNAT_Decide_Qid(hash_index, skb); ++ if (_hwnat_info.debug_level >= 6) ++ HWNAT_MSG_DBG("hash_index = %d\n", hash_index); ++} ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_foe.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_foe.h +new file mode 100755 +index 000000000000..1d5fbecab38d +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_foe.h +@@ -0,0 +1,655 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_HWNAT_FDB.h ++/// @brief HWNAT Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++#ifndef _MDRV_HWNAT_FOE_ ++#define _MDRV_HWNAT_FOE_ ++ ++#include ++#include "mdrv_hwnat_ioctl.h" ++ ++extern struct foe_entry *ppe_foe_base; ++extern struct ps_entry *ppe_ps_base; ++ ++/* DEFINITIONS AND MACROS*/ ++#define FOE_ENTRY_LIFE_TIME 5 ++#define FOE_THRESHOLD 1000 ++#define FOE_HASH_MASK 0x00001FFF ++#define FOE_HASH_WAY 2 ++#define FOE_1K_SIZ_MASK 0x000001FF ++#define FOE_2K_SIZ_MASK 0x000003FF ++#define FOE_4K_SIZ_MASK 0x000007FF ++#define FOE_8K_SIZ_MASK 0x00000FFF ++#define FOE_16K_SIZ_MASK 0x00001FFF ++ ++#if defined(CONFIG_RA_HW_NAT_TBL_1K) ++#define FOE_4TB_SIZ 1024 ++#define FOE_4TB_BIT 10 ++#elif defined(CONFIG_RA_HW_NAT_TBL_2K) ++#define FOE_4TB_SIZ 2048 ++#define FOE_4TB_BIT 11 ++#elif defined(CONFIG_RA_HW_NAT_TBL_4K) ++#define FOE_4TB_SIZ 4096 ++#define FOE_4TB_BIT 12 ++#elif defined(CONFIG_RA_HW_NAT_TBL_8K) ++#define FOE_4TB_SIZ 8192 ++#define FOE_4TB_BIT 13 ++#elif defined(CONFIG_RA_HW_NAT_TBL_16K) ++#define FOE_4TB_SIZ 16384 ++#define FOE_4TB_BIT 14 ++#endif ++ ++#define FOE_ENTRY_SIZ 128 /* for ipv6 backward compatible */ ++ ++#define IP_FORMAT3(addr) (((unsigned char *)&addr)[3]) ++#define IP_FORMAT2(addr) (((unsigned char *)&addr)[2]) ++#define IP_FORMAT1(addr) (((unsigned char *)&addr)[1]) ++#define IP_FORMAT0(addr) (((unsigned char *)&addr)[0]) ++ ++struct pkt_parse_result { ++ /*layer2 header */ ++ u8 dmac[6]; ++ u8 smac[6]; ++ ++ /*vlan header */ ++ u16 vlan_tag; ++ u16 vlan1_gap; ++ u16 vlan1; ++ u16 vlan2_gap; ++ u16 vlan2; ++ u16 vlan_layer; ++ ++ /*pppoe header */ ++ u32 pppoe_gap; ++ u16 ppp_tag; ++ u16 pppoe_sid; ++ ++ /*layer3 header */ ++ u16 eth_type; ++ struct iphdr iph; ++ struct ipv6hdr ip6h; ++ ++ /*layer4 header */ ++ struct tcphdr th; ++ struct udphdr uh; ++ ++ u32 pkt_type; ++ u8 is_mcast; ++ ++}; ++ ++struct pkt_rx_parse_result { ++ /*layer2 header */ ++ u8 dmac[6]; ++ u8 smac[6]; ++ ++ /*vlan header */ ++ u16 vlan_tag; ++ u16 vlan1_gap; ++ u16 vlan1; ++ u16 vlan2_gap; ++ u16 vlan2; ++ u16 vlan_layer; ++ ++ /*pppoe header */ ++ u32 pppoe_gap; ++ u16 ppp_tag; ++ u16 pppoe_sid; ++ ++ /*layer3 header */ ++ u16 eth_type; ++ struct iphdr iph; ++ struct ipv6hdr ip6h; ++ ++ /*layer4 header */ ++ struct tcphdr th; ++ struct udphdr uh; ++ ++ u32 pkt_type; ++ u8 is_mcast; ++ ++}; ++ ++ /* TYPEDEFS AND STRUCTURES*/ ++enum FOE_TBL_SIZE { ++ FOE_TBL_SIZE_1K, ++ FOE_TBL_SIZE_2K, ++ FOE_TBL_SIZE_4K, ++ FOE_TBL_SIZE_8K, ++ FOE_TBL_SIZE_16K ++}; ++ ++enum VLAN_ACTION { ++ NO_ACT = 0, ++ MODIFY = 1, ++ INSERT = 2, ++ DELETE = 3 ++}; ++ ++enum FOE_ENTRY_STATE { ++ INVALID = 0, ++ UNBIND = 1, ++ BIND = 2, ++ FIN = 3 ++}; ++ ++enum FOE_TBL_TCP_UDP { ++ TCP = 0, ++ UDP = 1, ++ ANY = 2 ++}; ++ ++enum FOE_TBL_EE { ++ NOT_ENTRY_END = 0, ++ ENTRY_END_FP = 1, ++ ENTRY_END_FOE = 2 ++}; ++ ++enum FOE_LINK_TYPE { ++ LINK_TO_FOE = 0, ++ LINK_TO_FP = 1 ++}; ++ ++enum FOE_IP_ACT { ++ IPV4_HNAPT = 0, ++ IPV4_HNAT = 1, ++ IPV6_1T_ROUTE = 2, ++ IPV4_DSLITE = 3, ++ IPV6_3T_ROUTE = 4, ++ IPV6_5T_ROUTE = 5, ++ IPV6_6RD = 7, ++}; ++ ++enum FOE_ENTRY_FMT { ++ IPV4_NAPT=0, ++ IPV4_NAT=1, ++ IPV6_ROUTING=5 ++}; ++ ++#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1 : 0) ++#define IS_IPV4_HNAT(x) (((x)->bfib1.pkt_type == IPV4_HNAT) ? 1 : 0) ++#define IS_IPV6_1T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_1T_ROUTE) ? 1 : 0) ++#define IS_IPV4_DSLITE(x) (((x)->bfib1.pkt_type == IPV4_DSLITE) ? 1 : 0) ++#define IS_IPV6_3T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_3T_ROUTE) ? 1 : 0) ++#define IS_IPV6_5T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_5T_ROUTE) ? 1 : 0) ++#define IS_IPV6_6RD(x) (((x)->bfib1.pkt_type == IPV6_6RD) ? 1 : 0) ++#define IS_IPV4_GRP(x) (IS_IPV4_HNAPT(x) | IS_IPV4_HNAT(x)) ++#define IS_IPV6_GRP(x) (IS_IPV6_1T_ROUTE(x) | IS_IPV6_3T_ROUTE(x) | IS_IPV6_5T_ROUTE(x) | IS_IPV6_6RD(x) | IS_IPV4_DSLITE(x)) ++ ++ ++/* state = unbind & dynamic */ ++struct ud_info_blk1 { ++ uint32_t time_stamp:8; ++ uint32_t pcnt:16; /* packet count */ ++ uint32_t preb:1; ++ uint32_t pkt_type:3; ++ uint32_t state:2; ++ uint32_t udp:1; ++ uint32_t sta:1; /* static entry */ ++}; ++ ++/* state = bind & fin */ ++struct bf_info_blk1 { ++ uint32_t time_stamp:15; ++ uint32_t ka:1; /* keep alive */ ++ uint32_t vlan_layer:3; ++ uint32_t psn:1; /* egress packet has PPPoE session */ ++ uint32_t vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */ ++ uint32_t ps:1; /* packet sampling */ ++ uint32_t cah:1; /* cacheable flag */ ++ uint32_t rmt:1; /* remove tunnel ip header (6rd/dslite only) */ ++ uint32_t ttl:1; ++ uint32_t pkt_type:3; ++ uint32_t state:2; ++ uint32_t udp:1; ++ uint32_t sta:1; /* static entry */ ++}; ++ ++struct _info_blk2 { ++ uint32_t qid:4; /* QID in Qos Port */ ++ uint32_t fqos:1; /* force to PSE QoS port */ ++ uint32_t dp:3; /* force to PSE port x *//*0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */ ++ uint32_t mcast:1; /* multicast this packet to CPU */ ++ uint32_t pcpl:1; /* OSBN */ ++ uint32_t mibf:1; ++ uint32_t alen:1; ++ uint32_t qid1:2; ++ uint32_t noused:2; ++ uint32_t wdmaid:1; ++ uint32_t winfo:1; ++ uint32_t acnt:6; ++ uint32_t dscp:8; /* DSCP value */ ++}; ++ ++/* Foe Entry (64B) */ ++/* IPV4: IPV6: */ ++/* +-----------------------+ +-----------------------+ */ ++/* | Information Block 1 | | Information Block 1 | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | SIP(4B) | | IPv6_DIP0(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | DIP(4B) | | IPv6_DIP1(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | SPORT(2B) | DPORT(2B) | | Rev(4B) | */ ++/* +-----------+-----------+ +-----------------------+ */ ++/* | Information Block 2 | | Information Block 2 | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | New SIP(4B) | | IPv6_DIP2(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | New DIP(4B) | | IPv6_DIP3(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | New SPORT | New DPORT | | Rev(4B) | */ ++/* +-----------+-----------+ +-----------------------+ */ ++/* | VLAN1(2B) |DMAC[47:32]| | VLAN1(2B) |DMAC[47:32]| */ ++/* +-----------|-----------+ +-----------|-----------+ */ ++/* | DMAC[31:0] | | DMAC[31:0] | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | PPPoE_ID |SMAC[47:32]| | PPPoE_ID |SMAC[47:32]| */ ++/* +-----------+-----------+ +-----------+-----------+ */ ++/* | SMAC[31:0] | | SMAC[31:0] | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | Rev | SNAP_Ctrl(3B) | | Rev | SNAP_Ctrl(3B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | Rev | VLAN2(2B) | | Rev | VLAN2(2B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | Rev(4B) | | Rev(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | tmp_buf(4B) | | tmp_buf(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* Foe Entry (80) */ ++/* */ ++/* IPV4 HNAPT: IPV4: */ ++/* +-----------------------+ +-----------------------+ */ ++/* | Information Block 1 | | Information Block 1 | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | SIP(4B) | | SIP(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | DIP(4B) | | DIP(4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | SPORT(2B) | DPORT(2B) | | Rev(4B) | */ ++/* +-----------+-----------+ +-----------------------+ */ ++/* | EG DSCP| Info Block 2 | | Information Block 2 | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | New SIP(4B) | | New SIP (4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | New DIP(4B) | | New DIP (4B) | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | New SPORT | New DPORT | | New SPORT | New DPORT | */ ++/* +-----------+-----------+ +-----------------------+ */ ++/* | REV | | REV | */ ++/* +-----------------------+ +-----------------------+ */ ++/* |Act_dp| REV | |Act_dp| REV | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | tmp_buf(4B) | | temp_buf(4B) | */ ++/* +-----------------------+ +-----------|-----------+ */ ++/* | ETYPE | VLAN1 ID | | ETYPE | VLAN1 | */ ++/* +-----------+-----------+ +-----------+-----------+ */ ++/* | DMAC[47:16] | | SMAC[47:16] | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | DMAC[15:0]| VLAN2 ID | | DMAC[15:0]| VLAN2 | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | SMAC[47:16] | | SMAC[47:16] | */ ++/* +-----------------------+ +-----------------------+ */ ++/* | SMAC[15:0]| PPPOE ID | | SMAC[15:0]| PPPOE ID | */ ++/* +-----------------------+ +-----------------------+ */ ++/* */ ++ ++struct _ipv4_hnapt { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; ++ u32 info_blk1; ++ }; ++ u32 sip; ++ u32 dip; ++ u16 dport; ++ u16 sport; ++ union { ++ struct _info_blk2 iblk2; ++ u32 info_blk2; ++ }; ++ u32 new_sip; ++ u32 new_dip; ++ u16 new_dport; ++ u16 new_sport; ++ u32 resv1; ++ u32 resv2; ++ uint32_t resv3:26; ++ uint32_t act_dp:6; /* UDF */ ++ u16 vlan1; ++ u16 etype; ++ u8 dmac_hi[4]; ++ union { ++ u16 vlan2_winfo; ++ u16 vlan2; ++ }; ++ u8 dmac_lo[2]; ++ u8 smac_hi[4]; ++ u16 pppoe_id; ++ u8 smac_lo[2]; ++}; ++ ++struct _ipv4_dslite { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; ++ u32 info_blk1; ++ }; ++ u32 sip; ++ u32 dip; ++ u16 dport; ++ u16 sport; ++ ++ u32 tunnel_sipv6_0; ++ u32 tunnel_sipv6_1; ++ u32 tunnel_sipv6_2; ++ u32 tunnel_sipv6_3; ++ ++ u32 tunnel_dipv6_0; ++ u32 tunnel_dipv6_1; ++ u32 tunnel_dipv6_2; ++ u32 tunnel_dipv6_3; ++ ++ u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */ ++ uint16_t priority:4; /* in order to consist with Linux kernel (should be 8bits) */ ++ uint16_t resv1:4; ++ uint32_t hop_limit:8; ++ uint32_t resv2:18; ++ uint32_t act_dp:6; /* UDF */ ++ ++ union { ++ struct _info_blk2 iblk2; ++ u32 info_blk2; ++ }; ++ ++ u16 vlan1; ++ u16 etype; ++ u8 dmac_hi[4]; ++ union { ++ u16 vlan2_winfo; ++ u16 vlan2; ++ }; ++ u8 dmac_lo[2]; ++ u8 smac_hi[4]; ++ u16 pppoe_id; ++ u8 smac_lo[2]; ++}; ++ ++struct _ipv6_1t_route { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; ++ u32 info_blk1; ++ }; ++ u32 ipv6_dip0; ++ u32 ipv6_dip1; ++ u32 resv; ++ ++ union { ++ struct _info_blk2 iblk2; ++ u32 info_blk2; ++ }; ++ ++ u32 ipv6_dip2; ++ u32 ipv6_dip3; ++ u32 resv1; ++ ++ uint32_t act_dp:6; /* UDF */ ++ u16 vlan1; ++ u16 etype; ++ u8 dmac_hi[4]; ++ union { ++ u16 vlan2_winfo; ++ u16 vlan2; ++ }; ++ u8 dmac_lo[2]; ++ u8 smac_hi[4]; ++ u16 pppoe_id; ++ u8 smac_lo[2]; ++}; ++ ++struct _ipv6_3t_route { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; ++ u32 info_blk1; ++ }; ++ u32 ipv6_sip0; ++ u32 ipv6_sip1; ++ u32 ipv6_sip2; ++ u32 ipv6_sip3; ++ u32 ipv6_dip0; ++ u32 ipv6_dip1; ++ u32 ipv6_dip2; ++ u32 ipv6_dip3; ++ uint32_t prot:8; ++ uint32_t resv:24; ++ ++ u32 resv1; ++ u32 resv2; ++ u32 resv3; ++ uint32_t resv4:26; ++ uint32_t act_dp:6; /* UDF */ ++ ++ union { ++ struct _info_blk2 iblk2; ++ u32 info_blk2; ++ }; ++ u16 vlan1; ++ u16 etype; ++ u8 dmac_hi[4]; ++ union { ++ u16 vlan2_winfo; ++ u16 vlan2; ++ }; ++ u8 dmac_lo[2]; ++ u8 smac_hi[4]; ++ u16 pppoe_id; ++ u8 smac_lo[2]; ++}; ++ ++struct _ipv6_5t_route { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; ++ u32 info_blk1; ++ }; ++ u32 ipv6_sip0; ++ u32 ipv6_sip1; ++ u32 ipv6_sip2; ++ u32 ipv6_sip3; ++ u32 ipv6_dip0; ++ u32 ipv6_dip1; ++ u32 ipv6_dip2; ++ u32 ipv6_dip3; ++ u16 dport; ++ u16 sport; ++ ++ u32 resv1; ++ u32 resv2; ++ u32 resv3; ++ uint32_t resv4:26; ++ uint32_t act_dp:6; /* UDF */ ++ ++ union { ++ struct _info_blk2 iblk2; ++ u32 info_blk2; ++ }; ++ ++ u16 vlan1; ++ u16 etype; ++ u8 dmac_hi[4]; ++ union { ++ u16 vlan2_winfo; ++ u16 vlan2; ++ }; ++ u8 dmac_lo[2]; ++ u8 smac_hi[4]; ++ u16 pppoe_id; ++ u8 smac_lo[2]; ++}; ++ ++struct _ipv6_6rd { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; ++ u32 info_blk1; ++ }; ++ u32 ipv6_sip0; ++ u32 ipv6_sip1; ++ u32 ipv6_sip2; ++ u32 ipv6_sip3; ++ u32 ipv6_dip0; ++ u32 ipv6_dip1; ++ u32 ipv6_dip2; ++ u32 ipv6_dip3; ++ u16 dport; ++ u16 sport; ++ ++ u32 tunnel_sipv4; ++ u32 tunnel_dipv4; ++ uint32_t hdr_chksum:16; ++ uint32_t dscp:8; ++ uint32_t ttl:8; ++ uint32_t flag:3; ++ uint32_t resv1:13; ++ uint32_t per_flow_6rd_id:1; ++ uint32_t resv2:9; ++ uint32_t act_dp:6; /* UDF */ ++ ++ union { ++ struct _info_blk2 iblk2; ++ u32 info_blk2; ++ }; ++ ++ u16 vlan1; ++ u16 etype; ++ u8 dmac_hi[4]; ++ union { ++ u16 vlan2_winfo; ++ u16 vlan2; ++ }; ++ u8 dmac_lo[2]; ++ u8 smac_hi[4]; ++ u16 pppoe_id; ++ u8 smac_lo[2]; ++ ++}; ++ ++struct foe_entry { ++ union { ++ struct ud_info_blk1 udib1; ++ struct bf_info_blk1 bfib1; /* common header */ ++ struct _ipv4_hnapt ipv4_hnapt; /* nat & napt share same data structure */ ++ struct _ipv4_dslite ipv4_dslite; ++ struct _ipv6_1t_route ipv6_1t_route; ++ struct _ipv6_3t_route ipv6_3t_route; ++ struct _ipv6_5t_route ipv6_5t_route; ++ struct _ipv6_6rd ipv6_6rd; ++ }; ++}; ++ ++struct ps_entry { ++ u8 en; ++ u8 acl; ++ u16 pkt_len; ++ u16 pkt_cnt; ++ u8 time_period; ++ u8 resv0; ++ u32 resv1; ++ u16 hw_pkt_cnt; ++ u16 hw_time; ++ ++}; ++ ++struct mib_entry { ++ u32 byt_cnt_l; ++ u16 byt_cnt_h; ++ u32 pkt_cnt_l; ++ u8 pkt_cnt_h; ++ u8 resv0; ++ u32 resv1; ++} __packed; ++ ++struct foe_pri_key { ++ /* TODO: add new primary key to support dslite, 6rd */ ++ ++ /* Ipv4 */ ++ struct { ++ uint32_t sip; ++ uint32_t dip; ++ uint16_t sport; ++ uint16_t dport; ++ uint32_t is_udp:1; ++ } ipv4_hnapt; ++ ++ struct { ++ uint32_t sip; ++ uint32_t dip; ++ /* TODO */ ++ } ipv4_hnat; ++ ++ struct { ++ uint32_t sip; ++ uint32_t dip; ++ /* TODO */ ++ } ipv4_dslite; ++ ++ /* IPv6 */ ++ struct { ++ uint32_t sip0; ++ uint32_t sip1; ++ uint32_t sip2; ++ uint32_t sip3; ++ uint32_t dip0; ++ uint32_t dip1; ++ uint32_t dip2; ++ uint32_t dip3; ++ uint16_t sport; ++ uint16_t dport; ++ uint32_t is_udp:1; ++ } ipv6_routing; ++ ++ struct { ++ /* TODO */ ++ } ipv6_6rd; ++ ++ uint32_t pkt_type; /* entry format */ ++}; ++ ++void MDrv_HWNAT_Foe_Dump_Entry(uint32_t index); ++int MDrv_HWNAT_Foe_Get_All_Entries(struct hwnat_args *opt); ++int MDrv_HWNAT_Foe_Set_Bind(struct hwnat_args *opt); ++int MDrv_HWNAT_Foe_Set_Unbind(struct hwnat_args *opt); ++int MDrv_HWNAT_Foe_Drop_Entry(struct hwnat_args *opt); ++int MDrv_HWNAT_Foe_Delete_Entry(uint32_t entry_num); ++void MDrv_HWNAT_Foe_Clean_All_Entries(void); ++void MDrv_HWNAT_Foe_Set_High_Mac(u8 *dst, uint8_t *src); ++void MDrv_HWNAT_Foe_Set_Low_Mac(u8 *dst, uint8_t *src); ++int MDrv_HWNAT_Add_Foe_Entry(struct hwnat_tuple *opt); ++int MDrv_HWNAT_Delete_Foe_Entry(struct hwnat_tuple *opt); ++ ++#endif /* _MDRV_HWNAT_FOE_ */ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_ioctl.c b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_ioctl.c +new file mode 100755 +index 000000000000..6218aeb11546 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_ioctl.c +@@ -0,0 +1,476 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_HWNAT_IOCTL.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++ ++#include "mhal_hwnat.h" ++#include "mdrv_hwnat.h" ++#include "mdrv_hwnat_ioctl.h" ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_util.h" ++#include "mdrv_hwnat_log.h" ++#include "mdrv_hwnat_mcast.h" ++#include "mdrv_hwnat_api.h" ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++static long MDrv_HWNAT_IOCTL_Control_Device(struct file *file, unsigned int cmd, unsigned long arg); ++static void MDrv_HWNAT_IOCTL_Dump_Entry(unsigned int entry_num, unsigned long *pkt_cnt, unsigned long *byte_cnt); ++static int MDrv_HWNAT_IOCTL_Clear_All_Entries(void); ++static void MDrv_HWNAT_IOCTL_Dump_Dram_Entry(uint32_t entry_num); ++static int32_t MDrv_HWNAT_IOCTL_Get_Ac_Info(struct hwnat_ac_args *opt3); ++ ++ ++const struct file_operations hw_nat_fops = { ++ unlocked_ioctl:MDrv_HWNAT_IOCTL_Control_Device, ++ compat_ioctl:MDrv_HWNAT_IOCTL_Control_Device, ++}; ++ ++static long MDrv_HWNAT_IOCTL_Control_Device(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ struct hwnat_args *opt = (struct hwnat_args *)arg; ++ struct hwnat_tuple *opt2 =(struct hwnat_tuple *)arg; ++ struct hwnat_tuple *opt2_k; ++ struct hwnat_ac_args *opt3 = (struct hwnat_ac_args *)arg; ++ struct hwnat_ac_args *opt3_k; ++ struct hwnat_config_args *opt4 = (struct hwnat_config_args *)arg; ++ struct hwnat_config_args *opt4_k; ++ struct hwnat_mcast_args *opt5 = (struct hwnat_mcast_args *)arg; ++ struct hwnat_mcast_args *opt5_k; ++ struct hwnat_mib_args *opt6 = (struct hwnat_mib_args *)arg; ++ struct hwnat_mib_args *opt6_k; ++ unsigned long tx_pkt_cnt; ++ unsigned long tx_byte_cnt; ++ unsigned long rx_pkt_cnt; ++ unsigned long rx_byte_cnt; ++ struct hwnat_args *opt1; ++ int size; ++ ++ size = sizeof(struct hwnat_args) + sizeof(struct hwnat_tuple) * 1024 * 16; ++ ++ switch (cmd) { ++ case HW_NAT_ADD_ENTRY: ++ opt2_k = kmalloc(sizeof(*opt2_k), GFP_KERNEL); ++ if (copy_from_user(opt2_k, opt2, sizeof(*opt2_k))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt2_k->result = MDrv_HWNAT_Add_Foe_Entry(opt2_k); ++ kfree(opt2_k); ++ break; ++ case HW_NAT_DEL_ENTRY: ++ HWNAT_MSG_DBG("HW_NAT_DEL_ENTRY\n"); ++ opt2_k = kmalloc(sizeof(*opt2_k), GFP_KERNEL); ++ if (copy_from_user(opt2_k, opt2, sizeof(*opt2_k))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt2_k->result = MDrv_HWNAT_Delete_Foe_Entry(opt2_k); ++ kfree(opt2_k); ++ break; ++ case HW_NAT_GET_ALL_ENTRIES: ++ ++ opt1 = kmalloc(size, GFP_KERNEL); ++ if (copy_from_user(opt1, opt, size)) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt1->result = MDrv_HWNAT_Foe_Get_All_Entries(opt1); ++ if (copy_to_user(opt, opt1, size)) ++ HWNAT_MSG_ERR("copy_to_user fail\n"); ++ ++ kfree(opt1); ++ break; ++ case HW_NAT_BIND_ENTRY: ++ opt1 = kmalloc(sizeof(*opt1), GFP_KERNEL); ++ if (copy_from_user(opt1, opt, sizeof(struct hwnat_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt1->result = MDrv_HWNAT_Foe_Set_Bind(opt1); ++ kfree(opt1); ++ break; ++ case HW_NAT_UNBIND_ENTRY: ++ opt1 = kmalloc(sizeof(*opt1), GFP_KERNEL); ++ if (copy_from_user(opt1, opt, sizeof(struct hwnat_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt1->result = MDrv_HWNAT_Foe_Set_Unbind(opt1); ++ kfree(opt1); ++ break; ++ case HW_NAT_DROP_ENTRY: ++ opt1 = kmalloc(sizeof(*opt1), GFP_KERNEL); ++ if (copy_from_user(opt1, opt, sizeof(struct hwnat_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt1->result = MDrv_HWNAT_Foe_Drop_Entry(opt1); ++ kfree(opt1); ++ break; ++ case HW_NAT_INVALID_ENTRY: ++ opt1 = kmalloc(sizeof(*opt1), GFP_KERNEL); ++ if (copy_from_user(opt1, opt, sizeof(struct hwnat_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt1->result = MDrv_HWNAT_Foe_Delete_Entry(opt1->entry_num); ++ kfree(opt1); ++ break; ++ case HW_NAT_DUMP_ENTRY: ++ opt1 = kmalloc(size, GFP_KERNEL); ++ if (copy_from_user(opt1, opt, sizeof(struct hwnat_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MDrv_HWNAT_Foe_Dump_Entry(opt1->entry_num); ++ kfree(opt1); ++ break; ++ case HW_NAT_DUMP_CACHE_ENTRY: ++ MHal_HWNAT_Dump_Cache_Entry(); ++ break; ++ case HW_NAT_DEBUG: /* For Debug */ ++ opt1 = kmalloc(size, GFP_KERNEL); ++ if (copy_from_user(opt1, opt, sizeof(struct hwnat_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ _hwnat_info.debug_level = opt1->debug; ++ kfree(opt1); ++ break; ++ case HW_NAT_GET_AC_CNT: ++ opt3_k = kmalloc(sizeof(*opt3_k), GFP_KERNEL); ++ if (copy_from_user(opt3_k, opt3, sizeof(*opt3_k))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt3_k->result = MDrv_HWNAT_IOCTL_Get_Ac_Info(opt3_k); ++ kfree(opt3_k); ++ break; ++ case HW_NAT_BIND_THRESHOLD: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MHal_HWNAT_Set_Bind_Threshold(opt4_k->bind_threshold); ++ opt4_k->result = HWNAT_SUCCESS; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_MAX_ENTRY_LMT: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MHal_HWNAT_Set_Max_Entry_Limit(opt4_k->foe_full_lmt, opt4_k->foe_half_lmt, opt4_k->foe_qut_lmt); ++ opt4_k->result = HWNAT_SUCCESS; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_KA_INTERVAL: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MHal_HWNAT_Set_KeepAlive_Interval(opt4->foe_tcp_ka, opt4->foe_udp_ka); ++ opt4_k->result = HWNAT_SUCCESS; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_UB_LIFETIME: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MHal_HWNAT_Set_Unbind_Lifetime(opt4_k->foe_unb_dlta); ++ opt4_k->result = HWNAT_SUCCESS; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_BIND_LIFETIME: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MHal_HWNAT_Set_Bind_Lifetime(opt4_k->foe_tcp_dlta, opt4_k->foe_udp_dlta, opt4_k->foe_fin_dlta); ++ opt4_k->result = HWNAT_SUCCESS; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_BIND_DIRECTION: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ _hwnat_info.bind_dir = opt4_k->bind_dir; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_VLAN_ID: ++ opt4_k = kmalloc(sizeof(*opt4_k), GFP_KERNEL); ++ if (copy_from_user(opt4_k, opt4, sizeof(struct hwnat_config_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ _hwnat_info.wan_vid = opt4_k->wan_vid; ++ _hwnat_info.lan_vid = opt4_k->lan_vid; ++ kfree(opt4_k); ++ break; ++ case HW_NAT_MCAST_INS: ++ opt5_k = kmalloc(sizeof(*opt5_k), GFP_KERNEL); ++ if (copy_from_user(opt5_k, opt5, sizeof(struct hwnat_mcast_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MDrv_HWNAT_Mcast_Insert_Entry(opt5_k->mc_vid, opt5_k->dst_mac, opt5_k->mc_px_en, opt5_k->mc_px_qos_en, opt5_k->mc_qos_qid); ++ kfree(opt5_k); ++ break; ++ case HW_NAT_MCAST_DEL: ++ opt5_k = kmalloc(sizeof(*opt5_k), GFP_KERNEL); ++ if (copy_from_user(opt5_k, opt5, sizeof(struct hwnat_mcast_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MDrv_HWNAT_Mcast_Delete_Entry(opt5->mc_vid, opt5->dst_mac, opt5->mc_px_en, opt5->mc_px_qos_en, opt5->mc_qos_qid); ++ kfree(opt5_k); ++ break; ++ case HW_NAT_MCAST_DUMP: ++ MDrv_HWNAT_Mcast_Dump(); ++ break; ++ case HW_NAT_MIB_DUMP: ++ opt6_k = kmalloc(sizeof(*opt6_k), GFP_KERNEL); ++ if (copy_from_user(opt6_k, opt6, sizeof(struct hwnat_mib_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MDrv_HWNAT_IOCTL_Dump_Entry(opt6_k->entry_num, &tx_pkt_cnt, &tx_byte_cnt); ++ kfree(opt6_k); ++ break; ++ case HW_NAT_MIB_DRAM_DUMP: ++ opt6_k = kmalloc(sizeof(*opt6_k), GFP_KERNEL); ++ if (copy_from_user(opt6_k, opt6, sizeof(struct hwnat_mib_args))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ MDrv_HWNAT_IOCTL_Dump_Dram_Entry(opt6_k->entry_num); ++ kfree(opt6_k); ++ break; ++ case HW_NAT_MIB_GET: ++ opt2_k = kmalloc(sizeof(*opt2_k), GFP_KERNEL); ++ if (copy_from_user(opt2_k, opt2, sizeof(*opt2_k))) ++ HWNAT_MSG_ERR("copy_from_user fail\n"); ++ opt2_k->result = MDrv_HWNAT_Get_Ppe_Mib_Info(opt2_k, &tx_pkt_cnt, &tx_byte_cnt, &rx_pkt_cnt, &rx_byte_cnt); ++ HWNAT_MSG_DBG("!!!!, tx byte = %lu\n", tx_byte_cnt); ++ HWNAT_MSG_DBG("!!!!, tx pkt = %lu\n", tx_pkt_cnt); ++ HWNAT_MSG_DBG("!!!!, rx byte = %lu\n", rx_byte_cnt); ++ HWNAT_MSG_DBG("!!!!, rx pkt = %lu\n", rx_pkt_cnt); ++ kfree(opt2_k); ++ break; ++ case HW_NAT_TBL_CLEAR: ++ MDrv_HWNAT_IOCTL_Clear_All_Entries(); ++ break; ++ case HW_NAT_DPORT: ++ MDrv_HWNAT_Dump_Dev_Handler(); ++ break; ++ case HW_NAT_SYS_CONFIG: ++ MDRV_HWNAT_CONFIG_DUMP_FEATURES(); ++ MDRV_HWNAT_CONFIG_DUMP_TEST(); ++ MDRV_HWNAT_CONFIG_DUMP_VALUE(); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++ ++ ++int MDrv_HWNAT_IOCTL_Register_Handler(void) ++{ ++ int result = 0; ++ ++ result = register_chrdev(HW_NAT_MAJOR, HW_NAT_DEVNAME, &hw_nat_fops); ++ if (result < 0) { ++ NAT_PRINT(KERN_WARNING "hw_nat: can't get major %d\n", HW_NAT_MAJOR); ++ return result; ++ } ++ ++ if (HW_NAT_MAJOR == 0) ++ HWNAT_MSG_ERR("HNAT Major num=%d\n", result); ++ ++ return 0; ++} ++ ++void MDrv_HWNAT_IOCTL_Unregister_Handler(void) ++{ ++ unregister_chrdev(HW_NAT_MAJOR, HW_NAT_DEVNAME); ++} ++ ++ ++ ++ ++int MDrv_HWNAT_Reply_Ppe_Entry_Idx(struct hwnat_tuple *opt, unsigned int entry_num) ++{ ++ struct foe_entry *entry = &ppe_foe_base[entry_num]; ++ struct foe_pri_key key; ++ int32_t hash_index; ++ ++ if(opt->pkt_type == IPV4_NAPT) { ++ key.ipv4_hnapt.sip = entry->ipv4_hnapt.new_dip; ++ key.ipv4_hnapt.dip = entry->ipv4_hnapt.new_sip; ++ key.ipv4_hnapt.sport = entry->ipv4_hnapt.new_dport; ++ key.ipv4_hnapt.dport = entry->ipv4_hnapt.new_sport; ++ key.ipv4_hnapt.is_udp = opt->is_udp; ++ ++ } ++ else if (opt->pkt_type == IPV6_ROUTING) { ++ if (_hwnat_info.features & NAT_IPV6) { ++ key.ipv6_routing.sip0 = entry->ipv6_5t_route.ipv6_dip0; ++ key.ipv6_routing.sip1 = entry->ipv6_5t_route.ipv6_dip1; ++ key.ipv6_routing.sip2 = entry->ipv6_5t_route.ipv6_dip2; ++ key.ipv6_routing.sip3 = entry->ipv6_5t_route.ipv6_dip3; ++ key.ipv6_routing.dip0 = entry->ipv6_5t_route.ipv6_sip0; ++ key.ipv6_routing.dip1 = entry->ipv6_5t_route.ipv6_sip1; ++ key.ipv6_routing.dip2 = entry->ipv6_5t_route.ipv6_sip2; ++ key.ipv6_routing.dip3 = entry->ipv6_5t_route.ipv6_sip3; ++ key.ipv6_routing.sport = entry->ipv6_5t_route.dport; ++ key.ipv6_routing.dport = entry->ipv6_5t_route.sport; ++ key.ipv6_routing.is_udp=opt->is_udp; ++ } ++ } ++ entry = NULL; ++ key.pkt_type = opt->pkt_type; ++ hash_index = MDrv_HWNAT_Get_Mib_Entry_Idx(&key, entry); ++ if (_hwnat_info.debug_level >= 1) { ++ HWNAT_MSG_DBG("reply entry idx = %d\n", hash_index); ++ } ++ return hash_index; ++} ++ ++ ++static void MDrv_HWNAT_IOCTL_Dump_Dram_Entry(uint32_t entry_num) ++{ ++ struct mib_entry *mib_entry = NULL; ++ ++ if (_hwnat_info.features & PPE_MIB) { ++ mib_entry = MIB_ENTRY_BASE_BY_IDX(_hwnat_info.ppe_mib_base, entry_num); ++ ++ HWNAT_MSG_MUST("***********DRAM PPE Entry = %d*********\n", entry_num); ++ HWNAT_MSG_MUST("PpeMibBase = %p\n", _hwnat_info.ppe_mib_base); ++ HWNAT_MSG_MUST("DRAM Packet_CNT H = %u\n", mib_entry->pkt_cnt_h); ++ HWNAT_MSG_MUST("DRAM Packet_CNT L = %u\n", mib_entry->pkt_cnt_l); ++ HWNAT_MSG_MUST("DRAM Byte_CNT H = %u\n", mib_entry->byt_cnt_h); ++ HWNAT_MSG_MUST("DRAM Byte_CNT L = %u\n", mib_entry->byt_cnt_l); ++ } ++ ++} ++ ++static void MDrv_HWNAT_IOCTL_Dump_Entry(unsigned int entry_num, unsigned long *pkt_cnt, unsigned long *byte_cnt) ++{ ++ MS_U64 bytes = 0; ++ MS_U64 pkts = 0; ++ ++ MHal_HWNAT_Get_Mib_Info(entry_num, &bytes, &pkts); ++ HWNAT_MSG_MUST("************PPE Entry = %d ************\n", entry_num); ++ HWNAT_MSG_MUST("Packet Cnt = %llu\n", pkts); ++ HWNAT_MSG_MUST("Byte Cnt = %llu\n", bytes); ++ *pkt_cnt = pkts; ++ *byte_cnt = bytes; ++} ++ ++ ++int MDrv_HWNAT_Get_Ppe_Mib_Info(struct hwnat_tuple *opt, unsigned long *tx_pkt_cnt, unsigned long *tx_byte_cnt, ++ unsigned long *rx_pkt_cnt, unsigned long *rx_byte_cnt) ++{ ++ struct foe_pri_key key; ++ struct foe_entry *entry = NULL; ++ int32_t hash_index; ++ int32_t rply_idx; ++ /*HWNAT_MSG_DBG("sip = %x, dip=%x, sp=%d, dp=%d\n", opt->ing_sipv4, opt->ing_dipv4, opt->ing_sp, opt->ing_dp);*/ ++ if ((opt->pkt_type) == IPV4_NAPT) { ++ key.ipv4_hnapt.sip=opt->ing_sipv4; ++ key.ipv4_hnapt.dip=opt->ing_dipv4; ++ key.ipv4_hnapt.sport=opt->ing_sp; ++ key.ipv4_hnapt.dport=opt->ing_dp; ++ key.ipv4_hnapt.is_udp=opt->is_udp; ++ } else if ((opt->pkt_type) == IPV6_ROUTING) { ++ key.ipv6_routing.sip0=opt->ing_sipv6_0; ++ key.ipv6_routing.sip1=opt->ing_sipv6_1; ++ key.ipv6_routing.sip2=opt->ing_sipv6_2; ++ key.ipv6_routing.sip3=opt->ing_sipv6_3; ++ key.ipv6_routing.dip0=opt->ing_dipv6_0; ++ key.ipv6_routing.dip1=opt->ing_dipv6_1; ++ key.ipv6_routing.dip2=opt->ing_dipv6_2; ++ key.ipv6_routing.dip3=opt->ing_dipv6_3; ++ key.ipv6_routing.sport=opt->ing_sp; ++ key.ipv6_routing.dport=opt->ing_dp; ++ key.ipv6_routing.is_udp=opt->is_udp; ++ } ++ ++ key.pkt_type = opt->pkt_type; ++ hash_index = MDrv_HWNAT_Get_Mib_Entry_Idx(&key, entry); ++ ++ if(hash_index != -1) { ++ MDrv_HWNAT_IOCTL_Dump_Entry(hash_index, tx_pkt_cnt, tx_byte_cnt); ++ rply_idx = MDrv_HWNAT_Reply_Ppe_Entry_Idx(opt, hash_index); ++ if(rply_idx != -1) { ++ MDrv_HWNAT_IOCTL_Dump_Entry(rply_idx, rx_pkt_cnt, rx_byte_cnt); ++ } else if (rply_idx == -1) { ++ *rx_pkt_cnt = 0; ++ *rx_byte_cnt = 0; ++ } ++ return HWNAT_SUCCESS; ++ } ++ ++ return HWNAT_FAIL; ++ ++} ++EXPORT_SYMBOL(MDrv_HWNAT_Get_Ppe_Mib_Info); ++ ++ ++ ++ ++static int32_t MDrv_HWNAT_IOCTL_Get_Ac_Info(struct hwnat_ac_args *opt3) ++{ ++ extern struct hwnat_ac_args ac_info[64]; ++ struct mhal_hwnat_ac_info info; ++ unsigned int ag_idx = 0; ++ ag_idx = opt3->ag_index; ++ if (ag_idx > 63) ++ return HWNAT_FAIL; ++ memset(&info, 0, sizeof(struct mhal_hwnat_ac_info)); ++ MHal_HWNAT_Get_Ac_Info(&info); ++ if (_hwnat_info.features & ACCNT_MAINTAINER) { ++ ac_info[ag_idx].ag_byte_cnt += info.bytes; ++ ac_info[ag_idx].ag_pkt_cnt += info.pkts; ++ opt3->ag_byte_cnt = ac_info[ag_idx].ag_byte_cnt; ++ opt3->ag_pkt_cnt = ac_info[ag_idx].ag_pkt_cnt; ++ } ++ else { ++ opt3->ag_byte_cnt = info.bytes; ++ opt3->ag_pkt_cnt = info.pkts; ++ } ++ return HWNAT_SUCCESS; ++} ++ ++ ++ ++ ++static int MDrv_HWNAT_IOCTL_Clear_All_Entries(void) ++{ ++ u32 foe_tbl_size; ++ MHal_HWNAT_Set_Miss_Action(E_HWNAT_FOE_SEARCH_MISS_ONLY_FWD_CPU); ++ foe_tbl_size = FOE_4TB_SIZ * sizeof(struct foe_entry); ++ memset(_hwnat_info.ppe_foe_base, 0, foe_tbl_size); ++ MHal_HWNAT_Enable_Cache(); /*clear HWNAT cache */ ++ MHal_HWNAT_Set_Miss_Action(E_HWNAT_FOE_SEARCH_MISS_FWD_CPU_BUILD_ENTRY); ++ ++ return HWNAT_SUCCESS; ++} ++ ++ ++void MDrv_HWNAT_Dump_Dev_Handler(void) ++{ ++ int i; ++ for (i = 0; i < MAX_IF_NUM; i++) { ++ if (dst_port[i] != NULL) ++ HWNAT_MSG_MUST("dst_port[%d] = %s\n", i, dst_port[i]->name); ++ } ++} ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_ioctl.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_ioctl.h +new file mode 100755 +index 000000000000..82a54b3b1108 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_ioctl.h +@@ -0,0 +1,215 @@ ++/* Module Name: ++* hwnat_ioctl.h ++* ++* Abstract: ++* ++* Revision History: ++* Who When What ++* -------- ---------- ---------------------------------------------- ++* Name Date Modification logs ++* Steven Liu 2006-10-06 Initial version ++*/ ++ ++#ifndef __HW_NAT_IOCTL_H__ ++#define __HW_NAT_IOCTL_H__ ++ ++#define HW_NAT_ADD_ENTRY (0x01) ++#define HW_NAT_DUMP_ENTRY (0x03) ++#define HW_NAT_GET_ALL_ENTRIES (0x04) ++#define HW_NAT_BIND_ENTRY (0x05) ++#define HW_NAT_UNBIND_ENTRY (0x06) ++#define HW_NAT_INVALID_ENTRY (0x07) ++#define HW_NAT_DEBUG (0x08) ++#define HW_NAT_GET_AC_CNT (0x09) ++#define HW_NAT_DSCP_REMARK (0x09) ++#define HW_NAT_VPRI_REMARK (0x0a) ++#define HW_NAT_FOE_WEIGHT (0x0b) ++#define HW_NAT_ACL_WEIGHT (0x0c) ++#define HW_NAT_DSCP_WEIGHT (0x0d) ++#define HW_NAT_VPRI_WEIGHT (0x0e) ++#define HW_NAT_DSCP_UP (0x0f) ++#define HW_NAT_UP_IDSCP (0x10) ++#define HW_NAT_UP_ODSCP (0x11) ++#define HW_NAT_UP_VPRI (0x12) ++#define HW_NAT_UP_AC (0x13) ++#define HW_NAT_SCH_MODE (0x14) ++#define HW_NAT_SCH_WEIGHT (0x15) ++#define HW_NAT_BIND_THRESHOLD (0x16) ++#define HW_NAT_MAX_ENTRY_LMT (0x17) ++#define HW_NAT_RULE_SIZE (0x18) ++#define HW_NAT_KA_INTERVAL (0x19) ++#define HW_NAT_UB_LIFETIME (0x1A) ++#define HW_NAT_BIND_LIFETIME (0x1B) ++#define HW_NAT_BIND_DIRECTION (0x1C) ++#define HW_NAT_VLAN_ID (0x1D) ++#define HW_NAT_MCAST_INS (0x20) ++#define HW_NAT_MCAST_DEL (0x21) ++#define HW_NAT_MCAST_DUMP (0x22) ++#define HW_NAT_MIB_DUMP (0x23) ++#define HW_NAT_DUMP_CACHE_ENTRY (0x24) ++#define HW_NAT_MIB_DRAM_DUMP (0x25) ++#define HW_NAT_MIB_GET (0x26) ++#define HW_NAT_DROP_ENTRY (0x36) ++#define HW_NAT_TBL_CLEAR (0x37) ++#define HW_NAT_DEL_ENTRY (0x38) ++#define HW_NAT_SYS_CONFIG (0x41) ++#define HW_NAT_IPI_CTRL_FROM_EXTIF (0x50) ++#define HW_NAT_IPI_CTRL_FROM_PPEHIT (0x51) ++#define HW_NAT_DPORT (0x52) ++ ++#define HW_NAT_DEVNAME "hwnat0" ++#define HW_NAT_MAJOR (220) ++ ++extern unsigned int debug_PPP; ++ ++/* extern struct hwnat_ac_args ac_info[64]; */ ++//extern struct mib_entry *ppe_mib_base; ++enum hwnat_status { ++ HWNAT_SUCCESS = 0, ++ HWNAT_FAIL = 1, ++ HWNAT_ENTRY_NOT_FOUND = 2 ++}; ++ ++struct hwnat_tuple { ++ unsigned short hash_index; ++ unsigned int pkt_type; ++ unsigned int is_udp; ++ /* egress layer2 */ ++ unsigned char dmac[6]; ++ unsigned char smac[6]; ++ unsigned short vlan1; ++ unsigned short vlan2; ++ unsigned short pppoe_id; ++ ++ /* ingress layer3 */ ++ unsigned int ing_sipv4; ++ unsigned int ing_dipv4; ++ ++ unsigned int ing_sipv6_0; ++ unsigned int ing_sipv6_1; ++ unsigned int ing_sipv6_2; ++ unsigned int ing_sipv6_3; ++ ++ unsigned int ing_dipv6_0; ++ unsigned int ing_dipv6_1; ++ unsigned int ing_dipv6_2; ++ unsigned int ing_dipv6_3; ++ ++ /* egress layer3 */ ++ unsigned int eg_sipv4; ++ unsigned int eg_dipv4; ++ ++ unsigned int eg_sipv6_0; ++ unsigned int eg_sipv6_1; ++ unsigned int eg_sipv6_2; ++ unsigned int eg_sipv6_3; ++ ++ unsigned int eg_dipv6_0; ++ unsigned int eg_dipv6_1; ++ unsigned int eg_dipv6_2; ++ unsigned int eg_dipv6_3; ++ ++ unsigned char prot; ++ ++ /* ingress layer4 */ ++ unsigned short ing_sp; ++ unsigned short ing_dp; ++ ++ /* egress layer4 */ ++ unsigned short eg_sp; ++ unsigned short eg_dp; ++ ++ unsigned char ipv6_flowlabel; ++ unsigned char pppoe_act; ++ unsigned int vlan_layer; ++ unsigned char dst_port; ++ unsigned int dscp; ++ enum hwnat_status result; ++}; ++ ++struct hwnat_args { ++ enum hwnat_status result; ++ unsigned int entry_num:16; ++ unsigned int num_of_entries:16; ++ struct hwnat_tuple entries[0]; ++ unsigned int debug:3; ++ unsigned int entry_state:2; /* invalid=0, unbind=1, bind=2, fin=3 */ ++} __packed; ++ ++/*hnat qos*/ ++struct hwnat_qos_args { ++ unsigned int enable:1; ++ unsigned int up:3; ++ unsigned int weight:3; /*UP resolution */ ++ unsigned int dscp:6; ++ unsigned int dscp_set:3; ++ unsigned int vpri:3; ++ unsigned int ac:2; ++ unsigned int mode:2; ++ unsigned int weight0:4; /*WRR 4 queue weight */ ++ unsigned int weight1:4; ++ unsigned int weight2:4; ++ unsigned int weight3:4; ++ enum hwnat_status result; ++}; ++ ++/*hnat config*/ ++struct hwnat_config_args { ++ unsigned int bind_threshold:16; ++ unsigned int foe_full_lmt:14; ++ unsigned int foe_half_lmt:14; ++ unsigned int foe_qut_lmt:14; ++ unsigned int pre_acl:9; ++ unsigned int pre_meter:9; ++ unsigned int pre_ac:9; ++ unsigned int post_meter:9; ++ unsigned int post_ac:9; ++ unsigned int foe_tcp_ka:8; /*unit 4 sec */ ++ unsigned int foe_udp_ka:8; /*unit 4 sec */ ++ unsigned int foe_unb_dlta:8; /*unit 1 sec */ ++ unsigned int foe_tcp_dlta:16; /*unit 1 sec */ ++ unsigned int foe_udp_dlta:16; /*unit 1 sec */ ++ unsigned int foe_fin_dlta:16; /*unit 1 sec */ ++ unsigned int wan_vid:16; ++ unsigned int lan_vid:16; ++ unsigned int bind_dir:2; /* 0=upstream, 1=downstream, 2=bi-direction */ ++ enum hwnat_status result; ++}; ++ ++struct hwnat_ac_args { ++ unsigned int ag_index; ++ unsigned long long ag_byte_cnt; ++ unsigned long long ag_pkt_cnt; ++ enum hwnat_status result; ++}; ++ ++struct hwnat_mcast_args { ++ unsigned int mc_vid:16; ++ unsigned int mc_px_en:4; ++ unsigned int valid:1; ++ unsigned int rev2:3; ++ unsigned int mc_px_qos_en:4; ++ unsigned int mc_qos_qid:4; ++ unsigned char dst_mac[6]; ++}; ++ ++struct hwnat_mib_args { ++ unsigned int entry_num:16; ++}; ++ ++struct hwnat_ipi_args { ++ unsigned int hnat_ipi_enable; ++ unsigned int drop_pkt; ++ unsigned int queue_thresh; ++ unsigned int ipi_cnt_mod; ++}; ++ ++ ++int MDrv_HWNAT_IOCTL_Register_Handler(void); ++void MDrv_HWNAT_IOCTL_Unregister_Handler(void); ++void MDrv_HWNAT_IOCTL_Init(void *info); ++void MDrv_HWNAT_Dump_Dev_Handler(void); ++int MDrv_HWNAT_Reply_Ppe_Entry_Idx(struct hwnat_tuple *opt, unsigned int entry_num); ++int MDrv_HWNAT_Get_Ppe_Mib_Info(struct hwnat_tuple *opt, unsigned long *tx_pkt_cnt, unsigned long *tx_byte_cnt, unsigned long *rx_pkt_cnt, unsigned long *rx_byte_cnt); ++ ++#endif /* __HW_NAT_IOCTL_H__ */ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_log.c b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_log.c +new file mode 100755 +index 000000000000..0c6a06d9eec9 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_log.c +@@ -0,0 +1,265 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_NAT.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_hwnat.h" ++#include "mdrv_hwnat.h" ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_util.h" ++#include "mdrv_hwnat_ioctl.h" ++#include "mdrv_hwnat_log.h" ++ ++#include "mdrv_hwnat_mcast.h" ++ ++#if (PPTP_L2TP) ++#include "fast_path.h" ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Variable and Functions ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++static struct HWNAT_DEVICE *_p_hwnat_info = NULL; ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++void FOE_INFO_DUMP(struct sk_buff *skb) ++{ ++ //HWNAT_MSG_DBG("FOE_INFO_START_ADDR(skb) =%p\n", FOE_INFO_START_ADDR(skb)); ++ HWNAT_MSG_DBG("FOE_TAG_PROTECT(skb) =%x\n", FOE_TAG_PROTECT(skb)); ++ HWNAT_MSG_DBG("FOE_ENTRY_NUM(skb) =%x\n", FOE_ENTRY_NUM(skb)); ++ HWNAT_MSG_DBG("FOE_ALG(skb) =%x\n", FOE_ALG(skb)); ++ HWNAT_MSG_DBG("FOE_AI(skb) =%x\n", FOE_AI(skb)); ++ HWNAT_MSG_DBG("FOE_SP(skb) =%x\n", FOE_SP(skb)); ++ HWNAT_MSG_DBG("FOE_MAGIC_TAG(skb) =%x\n", FOE_MAGIC_TAG(skb)); ++ ++#if defined(CONFIG_NOE_HW_NAT_PPTP_L2TP) ++ HWNAT_MSG_DBG("FOE_SOURCE(skb) =%x\n", FOE_SOURCE(skb)); ++ HWNAT_MSG_DBG("FOE_SOURCE(skb) =%x\n", FOE_SOURCE(skb)); ++#endif ++} ++ ++void FOE_INFO_DUMP_TAIL(struct sk_buff *skb) ++{ ++#if 0 ++ HWNAT_MSG_DBG("FOE_INFO_START_ADDR_TAIL(skb) =%p\n", FOE_INFO_START_ADDR_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_TAG_PROTECT_TAIL(skb) =%x\n", FOE_TAG_PROTECT_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_ENTRY_NUM_TAIL(skb) =%x\n", FOE_ENTRY_NUM_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_ALG_TAIL(skb) =%x\n", FOE_ALG_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_AI_TAIL(skb) =%x\n", FOE_AI_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_SP_TAIL(skb) =%x\n", FOE_SP_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_MAGIC_TAG_TAIL(skb) =%x\n", FOE_MAGIC_TAG_TAIL(skb)); ++#if defined(CONFIG_NOE_HW_NAT_PPTP_L2TP) ++ HWNAT_MSG_DBG("FOE_SOURCE_TAIL(skb) =%x\n", FOE_SOURCE_TAIL(skb)); ++ HWNAT_MSG_DBG("FOE_SOURCE_TAIL(skb) =%x\n", FOE_SOURCE_TAIL(skb)); ++#endif ++#endif ++} ++ ++ ++static uint8_t *show_cpu_reason(struct sk_buff *skb) ++{ ++ static u8 buf[32]; ++ ++ switch (FOE_AI(skb)) { ++ case TTL_0: ++ return "IPv4(IPv6) TTL(hop limit)\n"; ++ case HAS_OPTION_HEADER: ++ return "Ipv4(IPv6) has option(extension) header\n"; ++ case NO_FLOW_IS_ASSIGNED: ++ return "No flow is assigned\n"; ++ case IPV4_WITH_FRAGMENT: ++ return "IPv4 HNAT doesn't support IPv4 /w fragment\n"; ++ case IPV4_HNAPT_DSLITE_WITH_FRAGMENT: ++ return "IPv4 HNAPT/DS-Lite doesn't support IPv4 /w fragment\n"; ++ case IPV4_HNAPT_DSLITE_WITHOUT_TCP_UDP: ++ return "IPv4 HNAPT/DS-Lite can't find TCP/UDP sport/dport\n"; ++ case IPV6_5T_6RD_WITHOUT_TCP_UDP: ++ return "IPv6 5T-route/6RD can't find TCP/UDP sport/dport\n"; ++ case TCP_FIN_SYN_RST: ++ return "Ingress packet is TCP fin/syn/rst\n"; ++ case UN_HIT: ++ return "FOE Un-hit\n"; ++ case HIT_UNBIND: ++ return "FOE Hit unbind\n"; ++ case HIT_UNBIND_RATE_REACH: ++ return "FOE Hit unbind & rate reach\n"; ++ case HIT_BIND_TCP_FIN: ++ return "Hit bind PPE TCP FIN entry\n"; ++ case HIT_BIND_TTL_1: ++ return "Hit bind PPE entry and TTL(hop limit) = 1 and TTL(hot limit) - 1\n"; ++ case HIT_BIND_WITH_VLAN_VIOLATION: ++ return "Hit bind and VLAN replacement violation\n"; ++ case HIT_BIND_KEEPALIVE_UC_OLD_HDR: ++ return "Hit bind and keep alive with unicast old-header packet\n"; ++ case HIT_BIND_KEEPALIVE_MC_NEW_HDR: ++ return "Hit bind and keep alive with multicast new-header packet\n"; ++ case HIT_BIND_KEEPALIVE_DUP_OLD_HDR: ++ return "Hit bind and keep alive with duplicate old-header packet\n"; ++ case HIT_BIND_FORCE_TO_CPU: ++ return "FOE Hit bind & force to CPU\n"; ++ case HIT_BIND_EXCEED_MTU: ++ return "Hit bind and exceed MTU\n"; ++ case HIT_BIND_MULTICAST_TO_CPU: ++ return "Hit bind multicast packet to CPU\n"; ++ case HIT_BIND_MULTICAST_TO_GMAC_CPU: ++ return "Hit bind multicast packet to GMAC & CPU\n"; ++ case HIT_PRE_BIND: ++ return "Pre bind\n"; ++ } ++ ++ sprintf(buf, "CPU Reason Error - %X\n", FOE_AI(skb)); ++ return buf; ++} ++ ++uint32_t MDrv_HWNAT_Dump_TxSkb(struct sk_buff *skb) ++{ ++ int i; ++ ++ HWNAT_MSG_DBG("\nTx========\n", FOE_ENTRY_NUM(skb)); ++ HWNAT_MSG_DBG("Tx handler skb_headroom size = %u, skb->head = %p, skb->data = %p\n", ++ skb_headroom(skb), skb->head, skb->data); ++ for (i = 0; i < skb_headroom(skb); i++) { ++ HWNAT_MSG_DBG("tx_skb->head[%d]=%x\n", i, *(unsigned char *)(skb->head + i)); ++ /* HWNAT_MSG_DBG("%02X-",*((unsigned char*)i)); */ ++ } ++ ++ HWNAT_MSG_DBG("==================================\n"); ++ return 1; ++} ++ ++uint32_t MDrv_HWNAT_Dump_Skb(struct sk_buff *skb) ++{ ++ struct foe_entry *entry; ++ ++ if (_p_hwnat_info == NULL) ++ return 0; ++ ++ entry = (((struct foe_entry *)(_p_hwnat_info->ppe_foe_base)) + FOE_ENTRY_NUM(skb)); ++ ++ HWNAT_MSG_DBG("\nRx========\n", FOE_ENTRY_NUM(skb)); ++ HWNAT_MSG_DBG("RcvIF=%s\n", skb->dev->name); ++ HWNAT_MSG_DBG("FOE_Entry=%d\n", FOE_ENTRY_NUM(skb)); ++ HWNAT_MSG_DBG("CPU Reason=%s", show_cpu_reason(skb)); ++ HWNAT_MSG_DBG("ALG=%d\n", FOE_ALG(skb)); ++ HWNAT_MSG_DBG("SP=%d\n", FOE_SP(skb)); ++ ++ /* some special alert occurred, so entry_num is useless (just skip it) */ ++ if (FOE_ENTRY_NUM(skb) == 0x3fff) ++ return 1; ++ ++ /* PPE: IPv4 packet=IPV4_HNAT IPv6 packet=IPV6_ROUTE */ ++ if (IS_IPV4_GRP(entry)) { ++ HWNAT_MSG_DBG("Information Block 1=%x\n", entry->ipv4_hnapt.info_blk1); ++ HWNAT_MSG_DBG("SIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(entry->ipv4_hnapt.sip)); ++ HWNAT_MSG_DBG("DIP=%s\n", MDrv_HWNAT_Util_Ip_To_Str(entry->ipv4_hnapt.dip)); ++ HWNAT_MSG_DBG("SPORT=%d\n", entry->ipv4_hnapt.sport); ++ HWNAT_MSG_DBG("DPORT=%d\n", entry->ipv4_hnapt.dport); ++ HWNAT_MSG_DBG("Information Block 2=%x\n", entry->ipv4_hnapt.info_blk2); ++ } ++ else if ((_hwnat_info.features & NAT_IPV6) && (IS_IPV6_GRP(entry))) { ++ HWNAT_MSG_DBG("Information Block 1=%x\n", entry->ipv6_5t_route.info_blk1); ++ HWNAT_MSG_DBG("IPv6_SIP=%08X:%08X:%08X:%08X\n", ++ entry->ipv6_5t_route.ipv6_sip0, ++ entry->ipv6_5t_route.ipv6_sip1, ++ entry->ipv6_5t_route.ipv6_sip2, entry->ipv6_5t_route.ipv6_sip3); ++ HWNAT_MSG_DBG("IPv6_DIP=%08X:%08X:%08X:%08X\n", ++ entry->ipv6_5t_route.ipv6_dip0, ++ entry->ipv6_5t_route.ipv6_dip1, ++ entry->ipv6_5t_route.ipv6_dip2, entry->ipv6_5t_route.ipv6_dip3); ++ if (IS_IPV6_FLAB_EBL()) { ++ HWNAT_MSG_DBG("Flow Label=%08X\n", (entry->ipv6_5t_route.sport << 16) | ++ (entry->ipv6_5t_route.dport)); ++ } else { ++ HWNAT_MSG_DBG("SPORT=%d\n", entry->ipv6_5t_route.sport); ++ HWNAT_MSG_DBG("DPORT=%d\n", entry->ipv6_5t_route.dport); ++ } ++ HWNAT_MSG_DBG("Information Block 2=%x\n", entry->ipv6_5t_route.info_blk2); ++ } ++ else ++ HWNAT_MSG_DBG("unknown Pkt_type=%d\n", entry->bfib1.pkt_type); ++ HWNAT_MSG_DBG("==================================\n"); ++ return 1; ++} ++ ++void MDrv_HWNAT_LOG_Set_Level(unsigned char level) ++{ ++ ++ if (_p_hwnat_info == NULL) ++ return; ++ ++ ++ _p_hwnat_info->log_level = level; ++ ++ if (level & E_MDRV_HWNAT_MSG_CTRL_DUMP) { ++ MHal_HWNAT_Set_DBG(E_NOE_SEL_ENABLE); ++ } ++ else { ++ MHal_HWNAT_Set_DBG(E_NOE_SEL_DISABLE); ++ } ++} ++ ++unsigned char MDrv_HWNAT_LOG_Get_Level(void) ++{ ++ ++ if (_p_hwnat_info == NULL) ++ return E_MDRV_HWNAT_MSG_CTRL_NONE; ++ ++ ++ return _p_hwnat_info->log_level; ++} ++ ++void MDrv_HWNAT_LOG_Init(void *info) ++{ ++ _p_hwnat_info = (struct HWNAT_DEVICE *)info; ++} ++ ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_log.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_log.h +new file mode 100755 +index 000000000000..4a75b596fd32 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_log.h +@@ -0,0 +1,71 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_LOG.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_HWNAT_LOG_H_ ++#define _MDRV_HWNAT_LOG_H_ ++ ++#define HWNAT_DBG 1 ++ ++#if HWNAT_DBG ++#define NAT_PRINT(fmt, args...) printk(fmt, ## args) ++#else ++#define NAT_PRINT(fmt, args...) { } ++#endif ++ ++ ++typedef enum { ++ E_MDRV_HWNAT_MSG_CTRL_NONE = 0, ++ E_MDRV_HWNAT_MSG_CTRL_ERR , ++ E_MDRV_HWNAT_MSG_CTRL_WARN , ++ E_MDRV_HWNAT_MSG_CTRL_DBG , ++ E_MDRV_HWNAT_MSG_CTRL_DUMP , ++}EN_MDRV_HWNAT_MSG_CTRL; ++ ++ ++#define MDRV_HWNAT_DUMP_ALL (E_MDRV_HWNAT_MSG_CTRL_DBG) ++ ++#define MDRV_HWNAT_MSG(type, format , args...) \ ++ do{ \ ++ if (MDrv_HWNAT_LOG_Get_Level() >= type) \ ++ { \ ++ printk(format , ##args ); \ ++ } \ ++ }while(0); ++ ++#define HWNAT_MSG_ERR(format, args...) MDRV_HWNAT_MSG(E_MDRV_HWNAT_MSG_CTRL_ERR, format, ##args) ++#define HWNAT_MSG_WARN(format, args...) MDRV_HWNAT_MSG(E_MDRV_HWNAT_MSG_CTRL_WARN, format, ##args) ++#define HWNAT_MSG_DBG(format, args...) MDRV_HWNAT_MSG(E_MDRV_HWNAT_MSG_CTRL_DBG, format, ##args) ++#define HWNAT_MSG_DUMP(format, args...) MDRV_HWNAT_MSG(E_MDRV_HWNAT_MSG_CTRL_DUMP, format, ##args) ++#define HWNAT_MSG_MUST(format, args...) printk(format, ##args) ++ ++void MDrv_HWNAT_LOG_Set_Level(unsigned char level); ++unsigned char MDrv_HWNAT_LOG_Get_Level(void); ++void MDrv_HWNAT_LOG_Init(void *dev); ++void MDrv_HWNAT_LOG_Dump_Skb(struct sk_buff* sk); ++uint32_t MDrv_HWNAT_Dump_Skb(struct sk_buff *skb); ++uint32_t MDrv_HWNAT_Dump_TxSkb(struct sk_buff *skb); ++void FOE_INFO_DUMP_TAIL(struct sk_buff *skb); ++void FOE_INFO_DUMP(struct sk_buff *skb); ++ ++#endif /* _MDRV_NOE_LOG_H_ */ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_mcast.c b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_mcast.c +new file mode 100755 +index 000000000000..e6e04df9d156 +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_mcast.c +@@ -0,0 +1,349 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_NOE_MCAST_TBL.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++ ++#include "mhal_hwnat.h" ++#include "mdrv_hwnat_mcast.h" ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_util.h" ++#include "mdrv_hwnat_log.h" ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++#define MCAST_UPDATE_EXISTING_ENTRY(mcast_h, mcast_l, dst_mac, mc_px_en, mc_px_qos_en, mc_qos_qid) \ ++{ \ ++ if(dst_mac[0]==0x1 && dst_mac[1]==0x00) \ ++ mcast_h->mc_mpre_sel = 0; \ ++ else if(dst_mac[0]==0x33 && dst_mac[1]==0x33) \ ++ mcast_h->mc_mpre_sel = 1; \ ++ else \ ++ return 0; \ ++ mcast_h->mc_px_en = mc_px_en; \ ++ mcast_h->mc_px_qos_en = mc_px_qos_en; \ ++ mcast_h->mc_qos_qid = mc_qos_qid & 0xf; \ ++ mcast_h->mc_qos_qid54 = (mc_qos_qid & 0x30) >> 4; \ ++} ++ ++#define MCAST_SET_VALID_ENTRY(mcast_h, mcast_l, vlan_id, dst_mac, mc_px_en, mc_px_qos_en, mc_qos_qid) \ ++{\ ++ if(dst_mac[0]==0x1 && dst_mac[1]==0x00) \ ++ mcast_h->mc_mpre_sel = 0; \ ++ else if(dst_mac[0]==0x33 && dst_mac[1]==0x33) \ ++ mcast_h->mc_mpre_sel = 1; \ ++ else \ ++ return 0; \ ++ mcast_h->mc_vid = vlan_id;\ ++ mcast_h->mc_px_en = mc_px_en;\ ++ mcast_h->mc_px_qos_en = mc_px_qos_en;\ ++ mcast_l->mc_mac_addr[3] = dst_mac[2];\ ++ mcast_l->mc_mac_addr[2] = dst_mac[3];\ ++ mcast_l->mc_mac_addr[1] = dst_mac[4];\ ++ mcast_l->mc_mac_addr[0] = dst_mac[5];\ ++ mcast_h->valid = 1; \ ++ mcast_h->mc_qos_qid = mc_qos_qid & 0xf; \ ++ mcast_h->mc_qos_qid54 = (mc_qos_qid & 0x30) >> 4;\ ++ return 1; \ ++} ++ ++ ++#define MCAST_DELETE_ENTRY(mcast_h, mcast_l, mc_px_en, mc_px_qos_en) \ ++{ \ ++ mcast_h->mc_px_en &= ~mc_px_en; \ ++ mcast_h->mc_px_qos_en &= ~mc_px_qos_en; \ ++ if(mcast_h->mc_px_en == 0 && mcast_h->mc_px_qos_en == 0) { \ ++ mcast_h->valid = 0; \ ++ mcast_h->mc_vid = 0; \ ++ mcast_h->mc_qos_qid = 0; \ ++ mcast_h->mc_qos_qid54 = 0; \ ++ memset(&mcast_l->mc_mac_addr, 0, 4); \ ++ }\ ++} ++ ++#define MCAST_INVALIDATE_ENTRY(mcast_h, mcast_l) \ ++{ \ ++ mcast_h->mc_px_en = 0; \ ++ mcast_h->mc_px_qos_en = 0; \ ++ mcast_h->valid = 0; \ ++ mcast_h->mc_vid = 0; \ ++ mcast_h->mc_qos_qid = 0; \ ++ mcast_h->mc_mpre_sel = 0; \ ++ memset(&mcast_l->mc_mac_addr, 0, 4); \ ++} ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++ ++ ++static int32_t _MDrv_HWNAT_Mcast_Get_Entry(uint16_t vlan_id, uint8_t *dst_mac) ++{ ++ int i=0; ++ ++ for(i=0;imc_vid == vlan_id ) && ++ GET_PPE_MCAST_L(i)->mc_mac_addr[3] == dst_mac[2] && ++ GET_PPE_MCAST_L(i)->mc_mac_addr[2] == dst_mac[3] && ++ GET_PPE_MCAST_L(i)->mc_mac_addr[1] == dst_mac[4] && ++ GET_PPE_MCAST_L(i)->mc_mac_addr[0] == dst_mac[5]) { ++ if(GET_PPE_MCAST_H(i)->mc_mpre_sel==0) { ++ if(dst_mac[0]==0x1 && dst_mac[1]==0x00) { ++ return i; ++ } ++ } ++ else if(GET_PPE_MCAST_H(i)->mc_mpre_sel==1) { ++ if(dst_mac[0]==0x33 && dst_mac[1]==0x33) { ++ return i; ++ } ++ } ++ else ++ continue; ++ } ++ } ++ for(i=0;imc_vid == vlan_id ) && ++ GET_PPE_MCAST_L10(i)->mc_mac_addr[3] == dst_mac[2] && ++ GET_PPE_MCAST_L10(i)->mc_mac_addr[2] == dst_mac[3] && ++ GET_PPE_MCAST_L10(i)->mc_mac_addr[1] == dst_mac[4] && ++ GET_PPE_MCAST_L10(i)->mc_mac_addr[0] == dst_mac[5]) { ++ if(GET_PPE_MCAST_H10(i)->mc_mpre_sel==0) { ++ if(dst_mac[0]==0x1 && dst_mac[1]==0x00) { ++ return (i + 16); ++ } ++ } ++ else if(GET_PPE_MCAST_H10(i)->mc_mpre_sel==1) { ++ if(dst_mac[0]==0x33 && dst_mac[1]==0x33) { ++ return (i + 16); ++ } ++ } ++ else ++ continue; ++ } ++ } ++ return -1; ++} ++ ++ ++ ++ ++int MDrv_HWNAT_Mcast_Insert_Entry(uint16_t vlan_id, uint8_t *dst_mac, uint8_t mc_px_en, uint8_t mc_px_qos_en, uint8_t mc_qos_qid) ++{ ++ int i=0; ++ int entry_num; ++ ppe_mcast_h *mcast_h; ++ ppe_mcast_l *mcast_l; ++ ++ NAT_PRINT("[%s][%d]: vid=%x mac=%x:%x:%x:%x:%x:%x mc_px_en=%x mc_px_qos_en=%x, mc_qos_qid=%d \n", ++ __FUNCTION__, __LINE__, vlan_id, ++ dst_mac[0], dst_mac[1], dst_mac[2], dst_mac[3], dst_mac[4], dst_mac[5], ++ mc_px_en, mc_px_qos_en,mc_qos_qid); ++ ++ if((entry_num = _MDrv_HWNAT_Mcast_Get_Entry(vlan_id, dst_mac)) >= 0) { ++ MCAST_PRINT("update exist entry %d\n", entry_num); ++ if(entry_num < MAX_MCAST_ENTRY) { ++ mcast_h = GET_PPE_MCAST_H(entry_num); ++ mcast_l = GET_PPE_MCAST_L(entry_num); ++ MCAST_UPDATE_EXISTING_ENTRY(mcast_h, mcast_l, dst_mac, mc_px_en, mc_px_qos_en, mc_qos_qid); ++ } ++ else { ++ mcast_h = GET_PPE_MCAST_H10(entry_num - 16); ++ mcast_l = GET_PPE_MCAST_L10(entry_num - 16); ++ MCAST_UPDATE_EXISTING_ENTRY(mcast_h, mcast_l, dst_mac, mc_px_en, mc_px_qos_en, mc_qos_qid); ++ } ++ return 1; ++ } ++ else { //create new entry ++ for(i = 0; i < MAX_MCAST_ENTRY; i++) { // entry0 ~ entry15 ++ mcast_h = GET_PPE_MCAST_H(i); ++ mcast_l = GET_PPE_MCAST_L(i); ++ if(mcast_h->valid == 0) { ++ MCAST_SET_VALID_ENTRY(mcast_h, mcast_l, vlan_id, dst_mac, mc_px_en, mc_px_qos_en, mc_qos_qid); ++ } ++ } ++ for(i = 0; i < MAX_MCAST_ENTRY16_63; i++) { // entry16 ~ entry63 ++ mcast_h = GET_PPE_MCAST_H10(i); ++ mcast_l = GET_PPE_MCAST_L10(i); ++ if(mcast_h->valid == 0) { ++ MCAST_SET_VALID_ENTRY(mcast_h, mcast_l, vlan_id, dst_mac, mc_px_en, mc_px_qos_en, mc_qos_qid); ++ } ++ } ++ } ++ ++ MCAST_PRINT("HNAT: Multicast Table is FULL!!\n"); ++ return 0; ++} ++ ++int MDrv_HWNAT_Mcast_Update_Qid(uint16_t vlan_id, uint8_t *dst_mac, uint8_t mc_qos_qid) ++{ ++ int entry_num; ++ ppe_mcast_h *mcast_h; ++ NAT_PRINT("%s: vid=%x mac=%x:%x:%x:%x:%x:%x mc_qos_qid=%d\n", __FUNCTION__, vlan_id, ++ dst_mac[0],dst_mac[1],dst_mac[2],dst_mac[3],dst_mac[4],dst_mac[5], mc_qos_qid); ++ //update exist entry ++ if((entry_num = _MDrv_HWNAT_Mcast_Get_Entry(vlan_id, dst_mac)) >= 0) { ++ if(entry_num <= 15) ++ mcast_h = GET_PPE_MCAST_H(entry_num); ++ else ++ mcast_h = GET_PPE_MCAST_H10(entry_num - 16); ++ ++ if (mc_qos_qid < 16){ ++ mcast_h->mc_qos_qid = mc_qos_qid; ++ } ++ else if (mc_qos_qid > 15){ ++ mcast_h->mc_qos_qid = mc_qos_qid & 0xf; ++ mcast_h->mc_qos_qid54 = (mc_qos_qid & 0x30) >> 4; ++ } ++ else { ++ NAT_PRINT("Error qid = %d\n", mc_qos_qid); ++ return 0; ++ } ++ ++ ++ return 1; ++ } ++ return 0; ++} ++ ++/* ++ * Return: ++ * 0: entry found ++ * 1: entry not found ++ */ ++int MDrv_HWNAT_Mcast_Delete_Entry(uint16_t vlan_id, uint8_t *dst_mac, uint8_t mc_px_en, uint8_t mc_px_qos_en, uint8_t mc_qos_qid) ++{ ++ int entry_num; ++ ppe_mcast_h *mcast_h; ++ ppe_mcast_l *mcast_l; ++ NAT_PRINT("%s: vid=%x mac=%x:%x:%x:%x:%x:%x mc_px_en=%x mc_px_qos_en=%x mc_qos_qid=%d\n", __FUNCTION__, vlan_id, dst_mac[0],dst_mac[1],dst_mac[2],dst_mac[3],dst_mac[4],dst_mac[5], mc_px_en, mc_px_qos_en, mc_qos_qid); ++ if((entry_num = _MDrv_HWNAT_Mcast_Get_Entry(vlan_id, dst_mac)) >= 0) { ++ NAT_PRINT("entry_num = %d\n", entry_num); ++ if (entry_num <= 15){ ++ mcast_h = GET_PPE_MCAST_H(entry_num); ++ mcast_l = GET_PPE_MCAST_L(entry_num); ++ MCAST_DELETE_ENTRY(mcast_h, mcast_l, mc_px_en, mc_px_qos_en); ++ } ++ else if (entry_num > 15){ ++ mcast_h = GET_PPE_MCAST_H10(entry_num - 16); ++ mcast_l = GET_PPE_MCAST_L10(entry_num - 16); ++ MCAST_DELETE_ENTRY(mcast_h, mcast_l, mc_px_en, mc_px_qos_en); ++ } ++ return 0; ++ } ++ else { ++ NAT_PRINT("MDrv_HWNAT_Mcast_Delete_Entry fail: entry_number = %d\n", entry_num); ++ return 1; ++ } ++} ++ ++void MDrv_HWNAT_Mcast_Dump(void) ++{ ++ int i; ++ ppe_mcast_h *mcast_h; ++ ppe_mcast_l *mcast_l; ++ NAT_PRINT("MAC | VID | PortMask | QosPortMask \n"); ++ for(i=0;imc_mac_addr[3], ++ mcast_l->mc_mac_addr[2], ++ mcast_l->mc_mac_addr[1], ++ mcast_l->mc_mac_addr[0], ++ mcast_h->mc_vid, ++ (mcast_h->mc_px_en & 0x08)?'1':'-', ++ (mcast_h->mc_px_en & 0x04)?'1':'-', ++ (mcast_h->mc_px_en & 0x02)?'1':'-', ++ (mcast_h->mc_px_en & 0x01)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x08)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x04)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x02)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x01)?'1':'-', ++ mcast_h->mc_qos_qid + ((mcast_h->mc_qos_qid54) << 4), ++ mcast_h->mc_mpre_sel); ++ } ++ for(i=0;imc_mac_addr[3], ++ mcast_l->mc_mac_addr[2], ++ mcast_l->mc_mac_addr[1], ++ mcast_l->mc_mac_addr[0], ++ mcast_h->mc_vid, ++ (mcast_h->mc_px_en & 0x08)?'1':'-', ++ (mcast_h->mc_px_en & 0x04)?'1':'-', ++ (mcast_h->mc_px_en & 0x02)?'1':'-', ++ (mcast_h->mc_px_en & 0x01)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x08)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x04)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x02)?'1':'-', ++ (mcast_h->mc_px_qos_en & 0x01)?'1':'-', ++ mcast_h->mc_qos_qid + ((mcast_h->mc_qos_qid54) << 4), ++ mcast_h->mc_mpre_sel); ++ } ++ ++} ++ ++void MDrv_HWNAT_Mcast_Delete_All(void) ++{ ++ int i; ++ ppe_mcast_h *mcast_h; ++ ppe_mcast_l *mcast_l; ++ for(i=0;i ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_hwnat_foe.h" ++#include "mdrv_hwnat_util.h" ++ ++void MacReverse(uint8_t * Mac) ++{ ++ uint8_t tmp; ++ uint8_t i; ++ ++ for (i = 5; i > 2; i--) { ++ tmp = Mac[i]; ++ Mac[i] = Mac[5 - i]; ++ Mac[5 - i] = tmp; ++ } ++} ++ ++static int _GetNext(char *src, int separator, char *dest) ++{ ++ char *c; ++ int len = 0; ++ ++ if ((src == NULL) || (dest == NULL)) { ++ return -1; ++ } ++ ++ c = strchr(src, separator); ++ if (c == NULL) { ++ strncpy(dest, src, len); ++ return -1; ++ } ++ len = c - src; ++ strncpy(dest, src, len); ++ dest[len] = '\0'; ++ return len + 1; ++} ++ ++static inline int atoi(char *s) ++{ ++ int i = 0; ++ while (isdigit(*s)) { ++ i = i * 10 + *(s++) - '0'; ++ } ++ return i; ++} ++ ++ ++ ++unsigned int MDrv_HWNAT_Str2Ip(char *str) ++{ ++ int len; ++ char *ptr = str; ++ char buf[128]; ++ unsigned char c[4]; ++ int i; ++ for (i = 0; i < 3; ++i) { ++ if ((len = _GetNext(ptr, '.', buf)) == -1) { ++ return 1; /* parsing error */ ++ } ++ c[i] = atoi(buf); ++ ptr += len; ++ } ++ c[3] = atoi(ptr); ++ return ((c[0] << 24) + (c[1] << 16) + (c[2] << 8) + c[3]); ++} ++ ++void reg_modify_bits(unsigned int *Addr, uint32_t Data, uint32_t Offset, uint32_t Len) ++{ ++#if 0 ++ unsigned int mask = 0; ++ unsigned int value; ++ unsigned int i; ++ ++ for (i = 0; i < len; i++) { ++ mask |= 1 << (offset + i); ++ } ++ ++ value = sysregread(addr); ++ value &= ~mask; ++ value |= (data << offset) & mask;; ++ sysregwrite(addr, value); ++#endif ++} ++static inline uint16_t CsumPart(uint32_t o, uint32_t n, uint16_t old) ++{ ++ uint32_t d[] = { o, n }; ++ return csum_fold(csum_partial((char *)d, sizeof(d), old ^ 0xFFFF)); ++} ++ ++/* ++ * KeepAlive with new header mode will pass the modified packet to cpu. ++ * We must change to original packet to refresh NAT table. ++ */ ++ ++/* ++ * Recover TCP Src/Dst Port and recalculate tcp checksum ++ */ ++void foe_to_org_tcphdr(struct foe_entry *entry, struct iphdr *iph, ++ struct tcphdr *th) ++{ ++ /* TODO: how to recovery 6rd/dslite packet */ ++ th->check = ++ CsumPart((th->source) ^ 0xffff, ++ htons(entry->ipv4_hnapt.sport), th->check); ++ th->check = ++ CsumPart((th->dest) ^ 0xffff, ++ htons(entry->ipv4_hnapt.dport), th->check); ++ th->check = ++ CsumPart(~(iph->saddr), htonl(entry->ipv4_hnapt.sip), ++ th->check); ++ th->check = ++ CsumPart(~(iph->daddr), htonl(entry->ipv4_hnapt.dip), ++ th->check); ++ th->source = htons(entry->ipv4_hnapt.sport); ++ th->dest = htons(entry->ipv4_hnapt.dport); ++} ++ ++/* ++ * Recover UDP Src/Dst Port and recalculate udp checksum ++ */ ++void ++foe_to_org_udphdr(struct foe_entry *entry, struct iphdr *iph, ++ struct udphdr *uh) ++{ ++ /* TODO: how to recovery 6rd/dslite packet */ ++ ++ uh->check = ++ CsumPart((uh->source) ^ 0xffff, ++ htons(entry->ipv4_hnapt.sport), uh->check); ++ uh->check = ++ CsumPart((uh->dest) ^ 0xffff, ++ htons(entry->ipv4_hnapt.dport), uh->check); ++ uh->check = ++ CsumPart(~(iph->saddr), htonl(entry->ipv4_hnapt.sip), ++ uh->check); ++ uh->check = ++ CsumPart(~(iph->daddr), htonl(entry->ipv4_hnapt.dip), ++ uh->check); ++ uh->source = htons(entry->ipv4_hnapt.sport); ++ uh->dest = htons(entry->ipv4_hnapt.dport); ++} ++ ++/* ++ * Recover Src/Dst IP and recalculate ip checksum ++ */ ++void foe_to_org_iphdr(struct foe_entry *entry, struct iphdr *iph) ++{ ++ /* TODO: how to recovery 6rd/dslite packet */ ++ iph->saddr = htonl(entry->ipv4_hnapt.sip); ++ iph->daddr = htonl(entry->ipv4_hnapt.dip); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)(iph), iph->ihl); ++} ++ ++void hwnat_memcpy(void *dest, void *src, u32 n) ++{ ++ memcpy(dest, src, n); ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++/* Convert IP address from Hex to string */ ++uint8_t *MDrv_HWNAT_Util_Ip_To_Str(uint32_t Ip) ++{ ++ static uint8_t Buf[32]; ++ uint8_t *ptr = (char *)&Ip; ++ uint8_t c[4]; ++ ++ c[0] = *(ptr); ++ c[1] = *(ptr + 1); ++ c[2] = *(ptr + 2); ++ c[3] = *(ptr + 3); ++ sprintf(Buf, "%d.%d.%d.%d", c[3], c[2], c[1], c[0]); ++ return Buf; ++} ++ ++ ++unsigned int MDrv_HWNAT_Util_Str_To_Ip(char *str) ++{ ++ int len; ++ char *ptr = str; ++ char buf[128]; ++ unsigned char c[4]; ++ int i; ++ for (i = 0; i < 3; ++i) { ++ if ((len = _GetNext(ptr, '.', buf)) == -1) { ++ return 1; /* parsing error */ ++ } ++ c[i] = atoi(buf); ++ ptr += len; ++ } ++ c[3] = atoi(ptr); ++ return ((c[0] << 24) + (c[1] << 16) + (c[2] << 8) + c[3]); ++} ++ ++void MDrv_HWNAT_Util_Calc_Tcphdr(struct foe_entry *entry, struct iphdr *iph, struct tcphdr *th) ++{ ++ /* TODO: how to recovery 6rd/dslite packet */ ++ th->check = CsumPart((th->source) ^ 0xffff, htons(entry->ipv4_hnapt.sport), th->check); ++ th->check = CsumPart((th->dest) ^ 0xffff, htons(entry->ipv4_hnapt.dport), th->check); ++ th->check = CsumPart(~(iph->saddr), htonl(entry->ipv4_hnapt.sip), th->check); ++ th->check = CsumPart(~(iph->daddr), htonl(entry->ipv4_hnapt.dip), th->check); ++ th->source = htons(entry->ipv4_hnapt.sport); ++ th->dest = htons(entry->ipv4_hnapt.dport); ++ ++} ++ ++void MDrv_HWNAT_Util_Calc_Udphdr(struct foe_entry *entry, struct iphdr *iph, struct udphdr *uh) ++{ ++ /* TODO: how to recovery 6rd/dslite packet */ ++ uh->check = CsumPart((uh->source) ^ 0xffff, htons(entry->ipv4_hnapt.sport), uh->check); ++ uh->check = CsumPart((uh->dest) ^ 0xffff, htons(entry->ipv4_hnapt.dport), uh->check); ++ uh->check = CsumPart(~(iph->saddr), htonl(entry->ipv4_hnapt.sip), uh->check); ++ uh->check = CsumPart(~(iph->daddr), htonl(entry->ipv4_hnapt.dip), uh->check); ++ uh->source = htons(entry->ipv4_hnapt.sport); ++ uh->dest = htons(entry->ipv4_hnapt.dport); ++} ++ ++void MDrv_HWNAT_Util_Calc_Iphdr(struct foe_entry *entry, struct iphdr *iph) ++{ ++ /* TODO: how to recovery 6rd/dslite packet */ ++ iph->saddr = htonl(entry->ipv4_hnapt.sip); ++ iph->daddr = htonl(entry->ipv4_hnapt.dip); ++ iph->check = 0; ++ iph->check = ip_fast_csum((unsigned char *)(iph), iph->ihl); ++ ++} ++ ++ ++void MDrv_HWNAT_Util_Memcpy(void *dest, void *src, u32 n) ++{ ++#if 0 ++ ether_addr_copy(dest, src); ++#else ++ memcpy(dest, src, n); ++#endif ++} ++ ++ +diff --git a/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_util.h b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_util.h +new file mode 100755 +index 000000000000..a96f08a8864d +--- /dev/null ++++ b/drivers/sstar/noe/drv/nat/hw_nat/mdrv_hwnat_util.h +@@ -0,0 +1,49 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MDRV_HWNAT_UTIL.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_HWNAT_UTIL_H_ ++#define _MDRV_HWNAT_UTIL_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include ++ ++ ++ ++uint8_t *MDrv_HWNAT_Util_Ip_To_Str(uint32_t Ip); ++unsigned int MDrv_HWNAT_Util_Str_To_Ip(char *str); ++void MDrv_HWNAT_Util_Calc_Tcphdr(struct foe_entry *entry, struct iphdr *iph, struct tcphdr *th); ++void MDrv_HWNAT_Util_Calc_Udphdr(struct foe_entry *entry, struct iphdr *iph, struct udphdr *uh); ++void MDrv_HWNAT_Util_Calc_Iphdr(struct foe_entry *entry, struct iphdr *iph); ++void MDrv_HWNAT_Util_Memcpy(void *dest, void *src, u32 n); ++void MDrv_HWNAT_CalIpRange(uint32_t StartIp, uint32_t EndIp, uint8_t * M, uint8_t * E); ++unsigned int MDrv_HWNAT_Str2Ip(char *str); ++ ++ ++ ++#endif +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_hwnat.c b/drivers/sstar/noe/hal/infinity2/mhal_hwnat.c +new file mode 100755 +index 000000000000..d63830ed89cf +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_hwnat.c +@@ -0,0 +1,793 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_hwnat.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mhal_noe_reg.h" ++#include "mhal_noe.h" ++#include "mhal_noe_lro.h" ++#include "mhal_hwnat_cfg.h" ++#include "mhal_hwnat.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++enum { ++ E_HWNAT_FOE_TBL_NUM_1K = 0, ++ E_HWNAT_FOE_TBL_NUM_2K = 1, ++ E_HWNAT_FOE_TBL_NUM_4K = 2, ++ E_HWNAT_FOE_TBL_NUM_8K = 3, ++ E_HWNAT_FOE_TBL_NUM_16K = 4, ++}; ++ ++enum { ++ E_HWNAT_FOE_TBL_SIZE_64B = 0, ++ E_HWNAT_FOE_TBL_SIZE_80B = 1, ++}; ++ ++struct mhal_hwnat_config { ++ EN_NOE_SEL dbg_enable; ++ EN_NOE_SEL prebind; ++ EN_NOE_SEL mib; ++ EN_NOE_SEL ps; ++ EN_NOE_SEL pptp_l2tp; ++ EN_NOE_SEL mcast; ++ EN_NOE_SEL qtx_qrx; ++ EN_HWNAT_OPMODE op_mode; ++}; ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define MHAL_HWNAT_MUST(fmt, args...) printk(fmt, ##args) ++#define MHAL_HWNAT_DBG_INFO(fmt, args...) \ ++{\ ++ if (_hwnat_config.dbg_enable == E_NOE_SEL_ENABLE)\ ++ printk(fmt, ##args);\ ++} ++ ++#define MAX_CACHE_LINE_NUM 32 ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Variable ++//-------------------------------------------------------------------------------------------------- ++ ++ ++static struct mhal_hwnat_config _hwnat_config = { ++ .dbg_enable = E_NOE_SEL_DISABLE, ++ .prebind = E_NOE_SEL_DISABLE, ++ .mib = E_NOE_SEL_DISABLE, ++ .ps = E_NOE_SEL_DISABLE, ++ .pptp_l2tp = E_NOE_SEL_DISABLE, ++ .mcast = E_NOE_SEL_DISABLE, ++ .qtx_qrx = E_NOE_SEL_DISABLE, ++ .op_mode = E_HWNAT_OPMODE_AUTO, ++}; ++ ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++static void _NOE_HWNAT_RIU_REG_BITS_WRITE(void __iomem *Addr, MS_U32 Data, MS_U32 Offset, MS_U32 Len) ++{ ++ unsigned int Mask = 0; ++ unsigned int Value; ++ unsigned int i; ++ ++ for (i = 0; i < Len; i++) { ++ Mask |= 1 << (Offset + i); ++ } ++ ++ Value = MHal_NOE_Read_Reg(Addr); ++ Value &= ~Mask; ++ Value |= (Data << Offset) & Mask;; ++ MHal_NOE_Write_Reg(Addr, Value); ++} ++ ++ ++ ++void MHal_HWNAT_Init(struct mhal_table_info *info) ++{ ++ MHal_NOE_Write_Reg(PPE_FOE_BASE, info->foe_adr); ++ if (info->ps_adr != HWNAT_INVALID_PHY_ADDR) { ++ MHal_NOE_Write_Reg(PS_TB_BASE, info->ps_adr); ++ _hwnat_config.ps = E_NOE_SEL_ENABLE; ++ } ++ if (info->mib_adr != HWNAT_INVALID_PHY_ADDR) { ++ MHal_NOE_Write_Reg(MIB_TB_BASE, info->mib_adr); ++ _hwnat_config.mib = E_NOE_SEL_ENABLE; ++ } ++ ++ switch (info->entries) { ++ case 1024: ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_TBL_NUM_1K, 0, 3); ++ break; ++ case 2048: ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_TBL_NUM_2K, 0, 3); ++ break; ++ case 4096: ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_TBL_NUM_4K, 0, 3); ++ break; ++ case 8192: ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_TBL_NUM_8K, 0, 3); ++ break; ++ case 16384: ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_TBL_NUM_16K, 0, 3); ++ break; ++ default: ++ MHAL_HWNAT_MUST("Set as default value \n"); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_TBL_NUM_4K, 0, 3); ++ break; ++ } ++ /* Set Hash Mode */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, info->hash_mode, 14, 2); ++ MHal_NOE_Write_Reg(PPE_HASH_SEED, HASH_SEED); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, info->hash_dbg, 18, 2); ++ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, E_HWNAT_FOE_TBL_SIZE_80B, 3, 1); /* entry size = 80bytes */ ++ ++ if (info->prebind == TRUE) { ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, 1, 6, 1); /* pre-bind age enable */ ++ _hwnat_config.prebind = E_NOE_SEL_ENABLE; ++ } ++ _hwnat_config.pptp_l2tp = (info->pptp_l2tp == TRUE)?E_NOE_SEL_ENABLE:E_NOE_SEL_DISABLE; ++ _hwnat_config.prebind = (info->prebind == TRUE)?E_NOE_SEL_ENABLE:E_NOE_SEL_DISABLE; ++ _hwnat_config.mcast = (info->mcast == TRUE)?E_NOE_SEL_ENABLE:E_NOE_SEL_DISABLE; ++ _hwnat_config.qtx_qrx = (info->qtx_qrx == TRUE)?E_NOE_SEL_ENABLE:E_NOE_SEL_DISABLE; ++ _hwnat_config.op_mode = info->op_mode; ++ /* Set action for FOE search miss */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, FOE_SEARCH_MISS_FWD_CPU_BUILD_ENTRY, 4, 2); ++} ++ ++ ++void MHal_HWNAT_Enable_Cache(void) ++{ ++ /* clear cache table before enabling cache */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 9, 1); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 0, 9, 1); ++ ++ /* Cache enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 0, 1); ++} ++ ++void MHal_HWNAT_Set_Miss_Action(EN_HWNAT_FOE_SEARCH_MISS_CFG cfg) ++{ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, cfg, 4, 2); ++} ++ ++void MHal_HWNAT_Set_Hash_Seed(MS_U16 seed) ++{ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_HASH_SEED, seed, 0, 16); ++} ++ ++MS_BOOL MHal_HWNAT_Is_Ipv6_Hash_Label(void) ++{ ++ return (MHal_NOE_Read_Reg(PPE_FLOW_SET) & BIT_IPV6_HASH_FLAB)? TRUE : FALSE; ++ ++} ++ ++static void _MHal_HWNAT_Set_KA(struct mhal_hwnat_ka *info) ++{ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, info->cfg, 12, 2); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_KA, MHAL_HWNAT_KA_T, 0, 16); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_KA, info->tcp, 16, 8); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_KA, info->udp, 24, 8); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_BIND_LMT_1, info->ntu, 16, 8); ++ ++ if (_hwnat_config.prebind == E_NOE_SEL_ENABLE) ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_BIND_LMT_1, info->pbnd_limit, 24, 8); ++} ++ ++static void _MHal_HWNAT_Set_Flow(MS_BOOL enable) ++{ ++ u32 ppe_flow_set = MHal_NOE_Read_Reg(PPE_FLOW_SET); ++ ++ /* FOE engine need to handle unicast/multicast/broadcast flow */ ++ if (enable) { ++ ppe_flow_set |= (BIT_IPV4_NAPT_EN | BIT_IPV4_NAT_EN); ++ ++ ppe_flow_set |= (BIT_IPV4_NAT_FRAG_EN | BIT_UDP_IP4F_NAT_EN); /* ip fragment */ ++ if (_hwnat_config.pptp_l2tp == E_NOE_SEL_DISABLE) { ++ ppe_flow_set |= (BIT_IPV4_HASH_GREK); ++ } ++ ppe_flow_set |= (BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN | BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN); ++ /* ppe_flow_set |= (BIT_IPV6_HASH_FLAB); // flow label */ ++ ppe_flow_set |= (BIT_IPV6_HASH_GREK); ++ ++ } else { ++ ppe_flow_set &= ~(BIT_IPV4_NAPT_EN | BIT_IPV4_NAT_EN); ++ ppe_flow_set &= ~(BIT_IPV4_NAT_FRAG_EN); ++ ++ ppe_flow_set &= ~(BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN | BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN); ++ /* ppe_flow_set &= ~(BIT_IPV6_HASH_FLAB); */ ++ ppe_flow_set &= ~(BIT_IPV6_HASH_GREK); ++ ++ ++ } ++ ++ MHal_NOE_Write_Reg(PPE_FLOW_SET, ppe_flow_set); ++} ++ ++ ++static void _MHal_HWNAT_Set_Ageout(struct mhal_hwnat_age_out *info) ++{ ++ /* set Bind Non-TCP/UDP Age Enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, DFL_FOE_NTU_AGE, 7, 1); ++ ++ /* set Unbind State Age Enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, DFL_FOE_UNB_AGE, 8, 1); ++ ++ /* set min threshold of packet count for aging out at unbind state */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_UNB_AGE, info->unb_pkt_cnt, 16, 16); ++ ++ /* set Delta time for aging out an unbind FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_UNB_AGE, info->unb_time, 0, 8); ++ ++ if (_hwnat_config.op_mode != E_HWNAT_OPMODE_MANUAL) { ++ /* set Bind TCP Age Enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, DFL_FOE_TCP_AGE, 9, 1); ++ ++ /* set Bind UDP Age Enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, DFL_FOE_UDP_AGE, 10, 1); ++ ++ /* set Bind TCP FIN Age Enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, DFL_FOE_FIN_AGE, 11, 1); ++ ++ /* set Delta time for aging out an bind UDP FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE0, info->udp_time, 0, 16); ++ ++ /* set Delta time for aging out an bind Non-TCP/UDP FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE0, info->udp_time, 16, 16); ++ ++ /* set Delta time for aging out an bind TCP FIN FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE1, info->fin_time, 16, 16); ++ ++ /* set Delta time for aging out an bind TCP FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE1, info->tcp_time, 0, 16); ++ } ++ else { ++ /* fix TCP last ACK issue */ ++ /* Only need to enable Bind TCP FIN aging out function */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_CFG, DFL_FOE_FIN_AGE, 11, 1); ++ /* set Delta time for aging out an bind TCP FIN FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE1, info->fin_time, 16, 16); ++ } ++} ++ ++static void _MHal_HWNAT_Set_Global_Config(MS_BOOL enable) ++{ ++ if (enable == TRUE) { ++ /* Use default values on P7 */ ++ /* PPE Engine Enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_GLO_CFG, 1, 0, 1); ++ ++ /* TSID Enable */ ++ MHAL_HWNAT_DBG_INFO("TSID Enable\n"); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_GLO_CFG, 1, 1, 1); ++ ++ if (_hwnat_config.mcast == E_NOE_SEL_ENABLE) { ++ /* Enable multicast table lookup */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_GLO_CFG, 1, 7, 1); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_GLO_CFG, 0, 12, 2); /* Decide by PPE entry hash index */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_MCAST_PPSE, 0, 0, 4); /* multicast port0 map to PDMA */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_MCAST_PPSE, 1, 4, 4); /* multicast port1 map to GMAC1 */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_MCAST_PPSE, 2, 8, 4); /* multicast port2 map to GMAC2 */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_MCAST_PPSE, 5, 12, 4); /* multicast port3 map to QDMA */ ++ } ++ ++ if (_hwnat_config.qtx_qrx == E_NOE_SEL_ENABLE) { ++ MHal_NOE_Write_Reg(PPE_DFT_CPORT, 0x55555555); /* default CPU port is port5 (QDMA) */ ++ } ++ else { ++ MHal_NOE_Write_Reg(PPE_DFT_CPORT, 0); /* default CPU port is port0 (PDMA) */ ++ } ++ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_DFT_CPORT, 1, 31, 1); ++ ++ if(_hwnat_config.ps == E_NOE_SEL_ENABLE) { ++ /* MHal_NOE_Write_Reg(PS_CFG, 1); //Enable PacketSampling */ ++ MHal_NOE_Write_Reg(PS_CFG, 0x3); /* Enable PacketSampling, Disable Aging */ ++ } ++ ++ if (_hwnat_config.mib == E_NOE_SEL_ENABLE) { ++ MHal_NOE_Write_Reg(MIB_CFG, 0x03); /* Enable MIB & read clear */ ++ MHal_NOE_Write_Reg(MIB_CAH_CTRL, 0x01); /* enable mib cache */ ++ } ++ ++ ++ /* PPE Packet with TTL=0 */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_GLO_CFG, DFL_TTL0_DRP, 4, 1); ++ ++ } else { ++ ++ /* PPE Engine Disable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_GLO_CFG, 0, 0, 1); ++ ++ if(_hwnat_config.ps == E_NOE_SEL_ENABLE) { ++ MHal_NOE_Write_Reg(PS_CFG, 0); /* Disable PacketSampling */ ++ } ++ if (_hwnat_config.mib == E_NOE_SEL_ENABLE) { ++ MHal_NOE_Write_Reg(MIB_CFG, 0x00); /* Disable MIB */ ++ } ++ } ++} ++ ++void MHal_HWNAT_Set_KeepAlive_Interval(MS_U8 tcp_ka, MS_U8 udp_ka) ++{ ++ /* Keep alive time for bind FOE TCP entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_KA, tcp_ka, 16, 8); ++ ++ /* Keep alive timer for bind FOE UDP entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_KA, udp_ka, 24, 8); ++ ++} ++ ++ ++void MHal_HWNAT_Set_Bind_Lifetime(MS_U16 tcp_life, MS_U16 udp_life, MS_U16 fin_life) ++{ ++ /* set Delta time for aging out an bind UDP FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE0, udp_life, 0, 16); ++ ++ /* set Delta time for aging out an bind TCP FIN FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE1, fin_life, 16, 16); ++ ++ /* set Delta time for aging out an bind TCP FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BND_AGE1, tcp_life, 0, 16); ++ ++} ++ ++ ++void MHal_HWNAT_Set_Unbind_Lifetime(MS_U8 lifetime) ++{ ++ /* set Delta time for aging out an unbind FOE entry */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_UNB_AGE, lifetime, 0, 8); ++ ++} ++ ++void MHal_HWNAT_Set_Max_Entry_Limit(MS_U32 full, MS_U32 half, MS_U32 qurt) ++{ ++ /* Allowed max entries to be build during a time stamp unit */ ++ ++ /* smaller than 1/4 of total entries */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_LMT1, qurt, 0, 14); ++ ++ /* between 1/2 and 1/4 of total entries */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_LMT1, half, 16, 14); ++ ++ /* between full and 1/2 of total entries */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_LMT2, full, 0, 14); ++ ++} ++ ++static void _MHal_HWNAT_Set_Bind_Rate(struct mhal_hwnat_rate * rate) ++{ ++ /* Allowed max entries to be build during a time stamp unit */ ++ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_LMT1, MHAL_HWNAT_LMT_QURT, 0, 14); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_LMT1, MHAL_HWNAT_LMT_HALF, 16, 14); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_LMT2, MHAL_HWNAT_LMT_FULL, 0, 14); ++ ++ /* Set reach bind rate for unbind state */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BNDR, rate->bind_rate, 0, 16); ++ ++ if (_hwnat_config.prebind == E_NOE_SEL_ENABLE) { ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_FOE_BNDR, rate->tbl_read_rate, 16, 16); ++ } ++} ++ ++ ++void MHal_HWNAT_Start_Engine(struct mhal_hwnat_engine *info) ++{ ++ /* 0~63 Metering group */ ++ /* PpeSetMtrByteInfo(1, 500, 3); //TokenRate=500=500KB/s, MaxBkSize= 3 (32K-1B) */ ++ /* PpeSetMtrPktInfo(1, 5, 3); //1 pkts/sec, MaxBkSize=3 (32K-1B) */ ++ /* Set PPE Flow Set */ ++ _MHal_HWNAT_Set_Flow(TRUE); ++ ++ /* Set Auto Age-Out Function */ ++ _MHal_HWNAT_Set_Ageout(&(info->age_out)); ++ ++ /* Set PPE FOE KEEPALIVE TIMER */ ++ _MHal_HWNAT_Set_KA(&(info->ka)); ++ /* Set PPE FOE Bind Rate */ ++ _MHal_HWNAT_Set_Bind_Rate(&(info->rate)); ++ ++ /* Set PPE Global Configuration */ ++ _MHal_HWNAT_Set_Global_Config(TRUE); ++} ++ ++ ++ ++ ++void MHal_HWNAT_Stop_Engine(void) ++{ ++ /* Set PPE FOE ENABLE */ ++ _MHal_HWNAT_Set_Global_Config(FALSE); ++ ++ /* Set PPE Flow Set */ ++ _MHal_HWNAT_Set_Flow(FALSE); ++ ++ /* Free FOE table */ ++ ///foe_free_tbl(FOE_4TB_SIZ); ++} ++ ++ ++void MHal_HWNAT_Map_ForcePort(void) ++{ ++#if 0 ++ if (0) ++ { ++ /* index 0 = force port 0 ++ * index 1 = force port 1 ++ * ........... ++ * index 7 = force port 7 ++ * index 8 = no force port ++ * index 9 = force to all ports ++ */ ++ MHal_NOE_Write_Reg(PPE_FP_BMAP_0, 0x00020001); ++ MHal_NOE_Write_Reg(PPE_FP_BMAP_1, 0x00080004); ++ MHal_NOE_Write_Reg(PPE_FP_BMAP_2, 0x00200010); ++ MHal_NOE_Write_Reg(PPE_FP_BMAP_3, 0x00800040); ++ MHal_NOE_Write_Reg(PPE_FP_BMAP_4, 0x003F0000); ++ } ++#endif ++} ++ ++ ++void MHal_HWNAT_Get_Mib_Info(MS_U32 entry_num, MS_U64 *bytes, MS_U64 *pkts) ++{ ++ MHal_NOE_Write_Reg(MIB_SER_CR, entry_num | (1 << 16)); ++ while (1) { ++ if (!((MHal_NOE_Read_Reg(MIB_SER_CR) & 0x10000) >> 16)) ++ break; ++ } ++ wmb(); ++ *bytes = MHal_NOE_Read_Reg(MIB_SER_R1) & 0xffff; /* byte cnt bit47 ~ bit32 */ ++ *bytes = (*bytes << 32) | MHal_NOE_Read_Reg(MIB_SER_R0); /* byte cnt bit31~ bit0 */ ++ *pkts = MHal_NOE_Read_Reg(MIB_SER_R2) & 0xffffff; /* packet cnt bit39 ~ bit16 */ ++ *pkts = (*pkts << 16) |((MHal_NOE_Read_Reg(MIB_SER_R1) & 0xffff0000) >> 16); ++ ++} ++ ++ ++ ++void MHal_HWNAT_Set_Pkt_Prot(void) ++{ ++ /* IP Protocol Field for IPv4 NAT or IPv6 3-tuple flow */ ++ /* Don't forget to turn on related bits in PPE_IP_PROT_CHK register if you want to support ++ * another IP protocol. ++ */ ++ /* FIXME: enable it to support IP fragement */ ++ MHal_NOE_Write_Reg(PPE_IP_PROT_CHK, 0xFFFFFFFF); /* IPV4_NXTH_CHK and IPV6_NXTH_CHK */ ++ if (_hwnat_config.pptp_l2tp) ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_IP_PROT_0, IP_PROTO_GRE, 0, 8); ++ /* _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_IP_PROT_0, IP_PROTO_GRE, 0, 8); */ ++ /* _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_IP_PROT_0, IP_PROTO_TCP, 8, 8); */ ++ /* _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_IP_PROT_0, IP_PROTO_UDP, 16, 8); */ ++ /* _NOE_HWNAT_RIU_REG_BITS_WRITE(PPE_IP_PROT_0, IP_PROTO_IPV6, 24, 8); */ ++} ++ ++void MHal_HWNAT_Check_Switch_Vlan(MS_BOOL enable) ++{ ++ ++} ++ ++ ++void MHal_HWNAT_Get_Ac_Info(struct mhal_hwnat_ac_info *info) ++{ ++ info->bytes = MHal_NOE_Read_Reg(NOE_REG_AC_BASE + (info->idx * 16)); ++ info->bytes += ((MS_U64)(MHal_NOE_Read_Reg(NOE_REG_AC_BASE + (info->idx * 16) + 4)) << 32); /* 64bit bytes cnt */ ++ info->pkts = MHal_NOE_Read_Reg(NOE_REG_AC_BASE + info->idx * 16 +8); ++} ++ ++void MHAL_HWNAT_Get_Addr(MS_U32 *pAddr) ++{ ++ *pAddr = MHal_NOE_Read_Reg(PPE_FOE_BASE); ++} ++ ++void MHAL_HWNAT_Dump_Mib(MS_U32 entry_num) ++{ ++ unsigned int byt_l = 0; ++ unsigned long long byt_h = 0; ++ unsigned int pkt_l = 0; ++ ++ unsigned int long pkt_h = 0; ++ ++ MHal_NOE_Write_Reg(MIB_SER_CR, entry_num | (1 << 16)); ++ while (1) { ++ if (!((MHal_NOE_Read_Reg(MIB_SER_CR) & 0x10000) >> 16)) ++ break; ++ } ++ /*make sure write dram correct*/ ++ wmb(); ++ byt_l = MHal_NOE_Read_Reg(MIB_SER_R0); /* byte cnt bit31~ bit0 */ ++ byt_h = MHal_NOE_Read_Reg(MIB_SER_R1) & 0xffff; /* byte cnt bit47 ~ bit0 */ ++ pkt_l = (MHal_NOE_Read_Reg(MIB_SER_R1) & 0xffff0000) >> 16; ++ pkt_h = MHal_NOE_Read_Reg(MIB_SER_R2) & 0xffffff; /* packet cnt bit39 ~ bit16 */ ++ ++ MHAL_HWNAT_DBG_INFO("************PPE Entry = %d ************\n", entry_num); ++ MHAL_HWNAT_DBG_INFO("Packet Cnt = %lu\n", (pkt_h << 16) + pkt_l); ++ ++ MHAL_HWNAT_DBG_INFO("Byte Cnt h = %llu\n", byt_h); ++ MHAL_HWNAT_DBG_INFO("Byte Cnt l = %u\n", byt_l); ++} ++ ++ ++MS_U32 MHAL_HWNAT_Get_TimeStamp(void) ++{ ++ return MHal_NOE_Read_Reg(FOE_TS_T); ++} ++ ++ ++void MHal_HWNAT_Set_DBG(EN_NOE_SEL enable) ++{ ++ _hwnat_config.dbg_enable = enable; ++} ++ ++ ++void MHal_HWNAT_Set_Pkt_Dst(EN_NOE_GE_MAC ge, EN_HWNAT_PKT_DST_CFG dst) ++{ ++ u32 data = 0; ++ ++ if (ge == E_NOE_GE_MAC1) { ++ data = MHal_NOE_Read_Reg(FE_GDMA1_FWD_CFG); ++ if (dst == E_HWNAT_PKT_DST_ENGINE) { ++ data &= ~0x7777; ++ /* Uni-cast frames forward to PPE */ ++ data |= GDM1_UFRC_P_PPE; ++ /* Broad-cast MAC address frames forward to PPE */ ++ data |= GDM1_BFRC_P_PPE; ++ /* Multi-cast MAC address frames forward to PPE */ ++ data |= GDM1_MFRC_P_PPE; ++ /* Other MAC address frames forward to PPE */ ++ data |= GDM1_OFRC_P_PPE; ++ ++ } else { ++ data &= ~0x7777; ++ /* Uni-cast frames forward to CPU */ ++ data |= GDM1_UFRC_P_CPU; ++ /* Broad-cast MAC address frames forward to CPU */ ++ data |= GDM1_BFRC_P_CPU; ++ /* Multi-cast MAC address frames forward to CPU */ ++ data |= GDM1_MFRC_P_CPU; ++ /* Other MAC address frames forward to CPU */ ++ data |= GDM1_OFRC_P_CPU; ++ } ++ ++ MHal_NOE_Write_Reg(FE_GDMA1_FWD_CFG, data); ++ } ++ if (ge == E_NOE_GE_MAC2) { ++ data = MHal_NOE_Read_Reg(FE_GDMA2_FWD_CFG); ++ ++ if (dst == E_HWNAT_PKT_DST_ENGINE) { ++ data &= ~0x7777; ++ /* Uni-cast frames forward to PPE */ ++ data |= GDM1_UFRC_P_PPE; ++ /* Broad-cast MAC address frames forward to PPE */ ++ data |= GDM1_BFRC_P_PPE; ++ /* Multi-cast MAC address frames forward to PPE */ ++ data |= GDM1_MFRC_P_PPE; ++ /* Other MAC address frames forward to PPE */ ++ data |= GDM1_OFRC_P_PPE; ++ } ++ else { ++ data &= ~0x7777; ++ /* Uni-cast frames forward to CPU */ ++ data |= GDM1_UFRC_P_CPU; ++ /* Broad-cast MAC address frames forward to CPU */ ++ data |= GDM1_BFRC_P_CPU; ++ /* Multi-cast MAC address frames forward to CPU */ ++ data |= GDM1_MFRC_P_CPU; ++ /* Other MAC address frames forward to CPU */ ++ data |= GDM1_OFRC_P_CPU; ++ } ++ MHal_NOE_Write_Reg(FE_GDMA2_FWD_CFG, data); ++ } ++} ++ ++ ++static MS_BOOL _MHal_HWNAT_Is_CacheReq_Done(void) ++{ ++ int count = 1000; ++ ++ /* waiting for 1sec to make sure action was finished */ ++ do { ++ if (((MHal_NOE_Read_Reg(CAH_CTRL) >> 8) & 0x1) == 0) ++ return 1; ++ msleep(1); ++ } while (--count); ++ ++ return 0; ++} ++ ++ ++void MHal_HWNAT_Dump_Cache_Entry(void) ++{ ++ int line = 0; ++ int state = 0; ++ int tag = 0; ++ int cah_en = 0; ++ int i = 0; ++ ++ cah_en = MHal_NOE_Read_Reg(CAH_CTRL) & 0x1; ++ ++ if (!cah_en) { ++ MHAL_HWNAT_MUST("Cache is not enabled\n"); ++ return; ++ } ++ ++ /* cache disable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 0, 0, 1); ++ ++ MHAL_HWNAT_MUST(" No--|---State---|----Tag-----\n"); ++ MHAL_HWNAT_MUST("-----+-----------+------------\n"); ++ for (line = 0; line < MAX_CACHE_LINE_NUM; line++) { ++ /* set line number */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_LINE_RW, line, 0, 15); ++ ++ /* OFFSET_RW = 0x1F (Get Entry Number) */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_LINE_RW, 0x1F, 16, 8); ++ ++ /* software access cache command = read */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 2, 12, 2); ++ ++ /* trigger software access cache request */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 8, 1); ++ ++ if (_MHal_HWNAT_Is_CacheReq_Done()) { ++ tag = (MHal_NOE_Read_Reg(CAH_RDATA) & 0xFFFF); ++ state = ((MHal_NOE_Read_Reg(CAH_RDATA) >> 16) & 0x3); ++ MHAL_HWNAT_MUST("%04d | %s | %05d\n", line, ++ (state == 3) ? " Lock " : ++ (state == 2) ? " Dirty " : ++ (state == 1) ? " Valid " : "Invalid", tag); ++ } ++ else { ++ MHAL_HWNAT_MUST("%s is timeout (%d)\n", __func__, line); ++ } ++ ++ /* software access cache command = read */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 3, 12, 2); ++ ++ MHal_NOE_Write_Reg(CAH_WDATA, 0); ++ ++ /* trigger software access cache request */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 8, 1); ++ ++ if (!_MHal_HWNAT_Is_CacheReq_Done()) ++ MHAL_HWNAT_MUST("%s is timeout (%d)\n", __func__, line); ++ /* dump first 16B for each foe entry */ ++ MHAL_HWNAT_MUST("=========================\n", tag); ++ for (i = 0; i < 16; i++) { ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_LINE_RW, i, 16, 8); ++ ++ /* software access cache command = read */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 2, 12, 2); ++ ++ /* trigger software access cache request */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 8, 1); ++ ++ if (_MHal_HWNAT_Is_CacheReq_Done()) ++ MHAL_HWNAT_MUST("%02d %08X\n", i, MHal_NOE_Read_Reg(CAH_RDATA)); ++ else ++ MHAL_HWNAT_MUST("%s is timeout (%d)\n", __func__, line); ++ ++ /* software access cache command = write */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 3, 12, 2); ++ ++ MHal_NOE_Write_Reg(CAH_WDATA, 0); ++ ++ /* trigger software access cache request */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 8, 1); ++ ++ if (!_MHal_HWNAT_Is_CacheReq_Done()) ++ MHAL_HWNAT_MUST("%s is timeout (%d)\n", __func__, line); ++ } ++ MHAL_HWNAT_MUST("=========================================\n"); ++ } ++ ++ /* clear cache table before enabling cache */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 9, 1); ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 0, 9, 1); ++ ++ /* cache enable */ ++ _NOE_HWNAT_RIU_REG_BITS_WRITE(CAH_CTRL, 1, 0, 1); ++ ++} ++ ++ ++void MHal_HWNAT_Set_Bind_Threshold(MS_U32 threshold) ++{ ++ MHal_NOE_Write_Reg(PPE_FOE_BNDR, threshold); ++} ++ ++ ++ ++void MHal_HWNAT_Clear_MIB_Counter(MS_U16 addr) ++{ ++ int count = 100000; ++ ++ MHal_NOE_Write_Reg(MIB_SER_CR, addr | (1 << 16)); ++ do{ ++ if (!((MHal_NOE_Read_Reg(MIB_SER_CR) & 0x10000) >> 16)) ++ break; ++ //usleep_range(100, 110); ++ }while (--count); ++ MHal_NOE_Read_Reg(MIB_SER_R0); ++ MHal_NOE_Read_Reg(MIB_SER_R1); ++ MHal_NOE_Read_Reg(MIB_SER_R1); ++ MHal_NOE_Read_Reg(MIB_SER_R2); ++ ++} ++ ++ ++ ++MS_BOOL MHal_HWNAT_Get_QoS_Status(void) ++{ ++ unsigned int queue, queue_no; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_TX_SCH); ++ if ((temp & 0x00000800) || (temp & 0x08000000)) { ++ return TRUE; ++ } ++ for (queue = 0; queue < NUM_PQ; queue++) { ++ queue_no = queue % 16; ++ if (queue < 16) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ } ++ else if (queue > 15 && queue <= 31) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 1); ++ } ++ else if (queue > 31 && queue <= 47) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 2); ++ } ++ else if (queue > 47 && queue <= 63) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 3); ++ } ++ temp = MHal_NOE_Read_Reg(QTX_CFG_0 + (QUEUE_OFFSET * queue_no) + 0x4); ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ if ((temp & 0x8000000) || (temp & 0x800)) { ++ return TRUE; ++ } ++ } ++ return FALSE; ++} ++ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_hwnat.h b/drivers/sstar/noe/hal/infinity2/mhal_hwnat.h +new file mode 100755 +index 000000000000..6a587c752ed7 +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_hwnat.h +@@ -0,0 +1,170 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_hwnat.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++#ifndef _MHAL_HWNAT_H_ ++#define _MHAL_HWNAT_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mhal_porting.h" ++//#include "mach/memory.h" ++//#include "mstar/mstar_chip.h" ++//#include "chip_setup.h" ++#include "mhal_noe.h" ++#include "mhal_noe_reg.h" ++#include "mhal_noe_dma.h" ++#include "mhal_hwnat_cfg.h" ++#include "mhal_hwnat_entry.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define HWNAT_INVALID_PHY_ADDR (0xFFFFFFFF) ++#define IS_IPV6_FLAB_EBL() ((MHal_HWNAT_Is_Ipv6_Hash_Label() == TRUE)?1:0) ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++typedef enum { ++ E_HWNAT_PKT_DST_ENGINE = 0, ++ E_HWNAT_PKT_DST_CPU = 1, ++}EN_HWNAT_PKT_DST_CFG; ++ ++typedef enum { ++ E_HWNAT_FOE_SEARCH_MISS_DROP = 0, ++ E_HWNAT_FOE_SEARCH_MISS_DROP2 = 1, ++ E_HWNAT_FOE_SEARCH_MISS_ONLY_FWD_CPU = 2, ++ E_HWNAT_FOE_SEARCH_MISS_FWD_CPU_BUILD_ENTRY = 3, ++}EN_HWNAT_FOE_SEARCH_MISS_CFG; ++ ++typedef enum { ++ E_HWNAT_HASH_DBG_NONE = 0, ++ E_HWNAT_HASH_DBG_SRC_PORT, ++ E_HWNAT_HASH_DBG_IPV4_SIP, ++ E_HWNAT_HASH_DBG_IPV6_SIP, ++}EN_HWNAT_HASH_DBG; ++ ++typedef enum { ++ E_HWNAT_KA_CFG_NONE = 0, ++ E_HWNAT_KA_CFG_UCOPKT2CPU = 1, ++ E_HWNAT_KA_CFG_MCNPKT2CPU = 2, ++ E_HWNAT_KA_CFG_ALOPKT2CPU = 3, ++}EN_HWNAT_KA_CFG; ++ ++typedef enum { ++ E_HWNAT_OPMODE_AUTO = 0, ++ E_HWNAT_OPMODE_SEMI_AUTO = 1, ++ E_HWNAT_OPMODE_MANUAL = 2, ++}EN_HWNAT_OPMODE; ++ ++ ++struct mhal_table_info { ++ MS_U32 foe_adr; ++ MS_U32 ps_adr; ++ MS_U32 mib_adr; ++ MS_U32 entries; ++ MS_U8 hash_mode; ++ MS_U8 hash_dbg; ++ MS_BOOL ipv6; ++ MS_BOOL prebind; ++ MS_BOOL pptp_l2tp; ++ MS_BOOL mcast; ++ MS_BOOL qtx_qrx; ++ MS_U8 op_mode; ++}; ++ ++struct mhal_hwnat_ka { ++ MS_U8 cfg; /* EN_HWNAT_KA_CFG */ ++ MS_U32 udp; ++ MS_U32 tcp; ++ MS_U32 ntu; ++ MS_U8 pbnd_limit; ++}; ++ ++struct mhal_hwnat_age_out { ++ MS_U16 udp_time; ++ MS_U16 tcp_time; ++ MS_U16 fin_time; ++ MS_U16 ntu_time; ++ MS_U8 unb_time; ++ MS_U16 unb_pkt_cnt; ++}; ++ ++struct mhal_hwnat_rate { ++ MS_U16 tbl_read_rate; ++ MS_U16 bind_rate; ++}; ++ ++struct mhal_hwnat_engine { ++ struct mhal_hwnat_ka ka; ++ struct mhal_hwnat_age_out age_out; ++ struct mhal_hwnat_rate rate; ++}; ++ ++ ++struct mhal_hwnat_ac_info { ++ MS_U8 idx; ++ MS_U64 bytes; ++ MS_U32 pkts; ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_HWNAT_Init(struct mhal_table_info *info); ++void MHal_HWNAT_Set_DBG(EN_NOE_SEL enable); ++void MHal_HWNAT_Enable_Cache(void); ++void MHal_HWNAT_Map_ForcePort(void); ++void MHal_HWNAT_Set_Pkt_Prot(void); ++void MHal_HWNAT_Check_Switch_Vlan(MS_BOOL enable); ++void MHal_HWNAT_Get_Ac_Info(struct mhal_hwnat_ac_info *info); ++void MHal_HWNAT_Start_Engine(struct mhal_hwnat_engine *info); ++void MHal_HWNAT_Stop_Engine(void); ++void MHAL_HWNAT_Get_Addr(MS_U32 *pAddr); ++void MHAL_HWNAT_Dump_Mib(MS_U32 entry_num); ++MS_U32 MHAL_HWNAT_Get_TimeStamp(void); ++void MHal_HWNAT_Set_Pkt_Dst(EN_NOE_GE_MAC ge, EN_HWNAT_PKT_DST_CFG dst); ++ ++void MHal_HWNAT_Get_Mib_Info(MS_U32 entry_num, MS_U64 *bytes, MS_U64 *pkts); ++void MHal_HWNAT_Set_Unbind_Lifetime(MS_U8 lifetime); ++void MHal_HWNAT_Set_KeepAlive_Interval(MS_U8 tcp_ka, MS_U8 udp_ka); ++void MHal_HWNAT_Set_Bind_Lifetime(MS_U16 tcp_life, MS_U16 udp_life, MS_U16 fin_life); ++void MHal_HWNAT_Set_Max_Entry_Limit(MS_U32 full, MS_U32 half, MS_U32 qurt); ++void MHal_HWNAT_Set_Bind_Threshold(MS_U32 threshold); ++MS_BOOL MHal_HWNAT_Is_Ipv6_Hash_Label(void); ++void MHal_HWNAT_Set_Hash_Seed(MS_U16 seed); ++void MHal_HWNAT_Set_Miss_Action(EN_HWNAT_FOE_SEARCH_MISS_CFG cfg); ++void MHal_HWNAT_Dump_Cache_Entry(void); ++void MHal_HWNAT_Clear_MIB_Counter(MS_U16 addr); ++ ++MS_BOOL MHal_HWNAT_Get_QoS_Status(void); ++#endif /* _MHAL_HWNAT_H_ */ ++ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_hwnat_cfg.h b/drivers/sstar/noe/hal/infinity2/mhal_hwnat_cfg.h +new file mode 100755 +index 000000000000..d0f37cc5a1f4 +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_hwnat_cfg.h +@@ -0,0 +1,48 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MHAL_NOE_HWNAT_CFG.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MHAL_NOE_HWNAT_CFG_H_ ++#define _MHAL_NOE_HWNAT_CFG_H_ ++ ++ ++ ++#define MHAL_HWNAT_LMT_QURT (16383) ++#define MHAL_HWNAT_LMT_HALF (16383) ++#define MHAL_HWNAT_LMT_FULL (16383) ++#define MHAL_HWNAT_KA_T (1) ++ ++#define HASH_SEED (0x12345678) ++#define DFL_FOE_UNB_AGE 1 /* Unbind state age enable */ ++#define DFL_FOE_TCP_AGE 1 /* Bind TCP age enable */ ++#define DFL_FOE_NTU_AGE 1 /* Bind TCP age enable */ ++#define DFL_FOE_UDP_AGE 1 /* Bind UDP age enable */ ++#define DFL_FOE_FIN_AGE 1 /* Bind TCP FIN age enable */ ++ ++ ++ ++ ++#endif /* _MHAL_NOE_HWNAT_CFG_H_ */ ++ ++ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_hwnat_entry.h b/drivers/sstar/noe/hal/infinity2/mhal_hwnat_entry.h +new file mode 100755 +index 000000000000..1ded7eed66d5 +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_hwnat_entry.h +@@ -0,0 +1,344 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_hwnat_entry.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef MHAL_HWNAT_ENTRY_H ++#define MHAL_HWNAT_ENTRY_H ++ ++#ifndef ETH_HLEN ++#define ETH_HLEN (14) ++#endif ++ ++#ifndef VLAN_LEN ++#define VLAN_LEN (4) ++#endif ++ ++ ++#define MAX_MCAST_ENTRY 16 ++#define MAX_MCAST_ENTRY16_63 48 ++#define MAX_MCAST_ENTRY_TOTOAL 64 ++ ++typedef struct { ++ uint32_t mc_vid:12; ++ uint32_t mc_qos_qid54:2; ++ uint32_t valid:1; ++ uint32_t rev1:1; ++ uint32_t mc_px_en:4; ++ uint32_t mc_mpre_sel:2; //0=01:00, 2=33:33 ++ uint32_t mc_vid_cmp:1; ++ uint32_t rev2:1; ++ uint32_t mc_px_qos_en:4; ++ uint32_t mc_qos_qid:4; ++} ppe_mcast_h; ++ ++typedef struct { ++ uint8_t mc_mac_addr[4]; //mc_mac_addr[31:0] ++} ppe_mcast_l; ++ ++ ++#define GET_PPE_MCAST_H(idx) ((ppe_mcast_h *)(PPE_MCAST_H_0 + ((idx) * 8))) ++#define GET_PPE_MCAST_L(idx) ((ppe_mcast_l *)(PPE_MCAST_L_0 + ((idx) * 8))) ++#define GET_PPE_MCAST_H10(idx) ((ppe_mcast_h *)(PPE_MCAST_H_10 + ((idx) * 8))) ++#define GET_PPE_MCAST_L10(idx) ((ppe_mcast_l *)(PPE_MCAST_L_10 + ((idx) * 8))) ++ ++ ++ ++#define PPTP_TCP_PORT 1723 ++#define PPP_ADDRESS_CONTROL 0xff03 ++/* gre header structure: -------------------------------------------- */ ++ ++#define PPTP_GRE_PROTO 0x880B ++#define PPTP_GRE_VER 0x1 ++ ++#define PPTP_GRE_FLAG_C 0x80 ++#define PPTP_GRE_FLAG_R 0x40 ++#define PPTP_GRE_FLAG_K 0x20 ++#define PPTP_GRE_FLAG_S 0x10 ++#define PPTP_GRE_FLAG_A 0x80 ++ ++#define PPTP_GRE_IS_C(f) ((f)&PPTP_GRE_FLAG_C) ++#define PPTP_GRE_IS_R(f) ((f)&PPTP_GRE_FLAG_R) ++#define PPTP_GRE_IS_K(f) ((f)&PPTP_GRE_FLAG_K) ++#define PPTP_GRE_IS_S(f) ((f)&PPTP_GRE_FLAG_S) ++#define PPTP_GRE_IS_A(f) ((f)&PPTP_GRE_FLAG_A) ++ ++/* 16 bytes GRE header */ ++struct pptp_gre_header { ++ u8 flags; /* bitfield */ ++ u8 ver; /* should be PPTP_GRE_VER (enhanced GRE) */ ++ u16 protocol; /* should be PPTP_GRE_PROTO (ppp-encaps) */ ++ u16 payload; /* size of ppp payload, not inc. gre header */ ++ u16 cid; /* peer's call_id for this session */ ++ u32 seq; /* sequence number. Present if S==1 */ ++ u32 ack; /* seq number of highest packet recieved by */ ++ /* sender in this session */ ++} __packed; ++ ++ ++struct hnat_pptp ++{ ++ uint32_t tx_seqno; ++ uint32_t rx_seqno; ++ uint32_t saddr; ++ uint32_t daddr; ++ uint16_t call_id; ++ uint16_t call_id_udp;/*tcp udp with different ID*/ ++ uint16_t call_id_tcp; ++ uint16_t tx_ip_id; ++ uint8_t eth_header[ETH_HLEN]; ++ uint32_t key;/*MT7620:add key*/ ++}; ++ ++/*L2TP*/ ++struct hnat_l2tp ++{ ++ uint32_t daddr; /* DIP */ ++ uint32_t saddr; /* SIP */ ++ uint16_t tid; /* Tunnel ID */ ++ uint16_t sid; /* Session ID */ ++ uint16_t source; /* UDP source port */ ++ uint16_t dest; /* UDP dest port */ ++ uint8_t eth_header[ETH_HLEN]; ++}; ++ ++struct l2tp_add_hdr ++{ ++ uint16_t source; /* UDP */ ++ uint16_t dest; ++ uint16_t len; ++ uint16_t checksum; ++ uint16_t type; /* L2TP */ ++ uint16_t tid; ++ uint16_t sid; ++}; ++ ++ ++struct hnat_l2tp_parse ++{ ++ uint16_t ver; /* Packets Type */ ++ uint16_t length; /* Length (Optional)*/ ++ uint16_t tid; /* Tunnel ID */ ++ uint16_t sid; /* Session ID */ ++}; ++ ++struct ppp_hdr { ++ uint16_t addr_ctrl; ++ uint16_t protocol; ++}; ++ ++ ++ ++enum L2RuleDir { ++ OTHERS = 0, ++ DMAC = 1, ++ SMAC = 2, ++ SDMAC = 3 ++}; ++ ++enum L3RuleDir { ++ IP_QOS = 0, ++ DIP = 1, ++ SIP = 2, ++ SDIP = 3 ++}; ++ ++enum L4RuleDir { ++ DONT_CARE = 0, ++ DPORT = 1, ++ SPORT = 2, ++ SDPORT = 3 ++}; ++ ++enum RuleType { ++ L2_RULE = 0, ++ L3_RULE = 1, ++ L4_RULE = 2, ++ PT_RULE = 3 ++}; ++ ++enum PortNum { ++ PN_CPU = 0, ++ PN_GE1 = 1, ++ PN_DONT_CARE = 7 ++}; ++ ++enum OpCode { ++ AND = 0, ++ OR = 1 ++}; ++ ++enum TcpFlag { ++ TCP_FIN = 1, ++ TCP_SYN = 2, ++ TCP_RESET = 4, ++ TCP_PUSH = 8, ++ TCP_ACK = 16, ++ TCP_URGENT = 32 ++}; ++ ++enum TcpFlagOp { ++ EQUAL = 0, ++ NOT_EQUAL = 1, ++ IN_SET = 2, ++ NOT_IN_SET = 3 ++}; ++ ++enum L4Type { ++ FLT_IP_PROT = 0, ++ FLT_UDP = 1, ++ FLT_TCP = 2, ++ FLT_TCP_UDP = 3 ++}; ++ ++enum FpnType { ++ FPN_CPU = 0, ++ FPN_GE1 = 1, ++ FPN_GE2 = 2, ++ FPN_FRC_PRI_ONLY = 5, ++ FPN_ALLOW = 4, ++ FPN_DROP = 7 ++}; ++ ++struct common_field { ++ ++ union { ++ struct { ++ uint8_t ee:1; /* entry end */ ++ uint8_t resv:6; ++ uint8_t logic:1; /* logic operation with next rule (AND or OR) */ ++ } ee_0; /* entry end =0 */ ++ ++ struct { ++ uint8_t ee:1; /* entry end */ ++ uint8_t dop:1; /* drop out profile */ ++ uint8_t mg:6; /* meter group */ ++ } mtr; /* meter */ ++ ++ struct { ++ uint8_t ee:1; /* entry end */ ++ uint8_t rsv:1; ++ uint8_t ag:6; /* accounting group */ ++ } ac; /* account */ ++ ++ struct { ++ uint8_t ee:1; /* entry end */ ++ uint8_t fpp:1; /* Force Destination Port */ ++ uint8_t fpn:3; /* Force Port Number */ ++ uint8_t up:3; /* User Perority */ ++ } fpp; /* force destination port & force new user priority */ ++ ++ struct { ++ uint8_t ee:1; /* entry end */ ++ uint8_t foe:1; /* is Foe entry */ ++ uint8_t foe_tb:6; /* FoE Table Entry */ ++ } foe; ++ }; ++ ++ uint8_t match:1; /* 0: non-equal, 1: equal */ ++ uint8_t pn:3; /* port number, Pre: ingress port/Post: egress port */ ++ uint8_t rt:2; /* Rule type */ ++ uint8_t dir:2; /* Direction */ ++}; ++ ++struct l2_rule { ++ ++ struct common_field com; ++ ++ union { ++ uint8_t mac[6]; ++ struct { ++ uint16_t v:1; /* compare VIDX */ ++ uint16_t s:1; /* compare special tag */ ++ uint16_t e:1; /* compare ethernet type */ ++ uint16_t p:1; /* compare pppoe session id */ ++ uint16_t vid:12; /* vlan id */ ++ uint16_t etyp_pprot; /* ethernet type(p=0) or pppoe protocol(p=1) */ ++ uint16_t pppoe_id; ++ } others; ++ }; ++} __attribute__ ((packed)); ++ ++ ++struct l3_rule { ++ ++ struct common_field com; ++ ++ union { ++ ++ /* ip boundary = ip ~ ip + (ip_rng_m << ip_rng_e) */ ++ struct { ++ uint32_t ip; ++ uint16_t ip_rng_m:8; /* ip range mantissa part */ ++ uint16_t ip_rng_e:5; /* ip range exponent part */ ++ uint16_t v4:1; /* ipv4/ipv6 */ ++ uint16_t ip_seg:2; /* segment for ipv */ ++ } ip; ++ ++ struct { ++ uint32_t tos_s:8; /* start of ipv4 tos range */ ++ uint32_t tos_e:8; /* end of ipv4 tos range */ ++ uint32_t resv:16; ++ uint16_t resv1:4; ++ uint16_t foz:1; /* IPv4 fragment offset zero */ ++ uint16_t mf:1; /* Ipv4 more fragments flag */ ++ uint16_t fov:1; /* IPv4 fragment offset valid */ ++ uint16_t mfv:1; /*IPv4 more fragments flag valid */ ++ uint16_t rsv:5; ++ uint16_t v4:1; /* this rule is for ipv4 or ipv6 */ ++ uint16_t rsv1:2; ++ } qos; ++ }; ++} __attribute__ ((packed)); ++ ++struct l4_rule { ++ ++ struct common_field com; ++ ++ uint16_t p_start; /* start of port range */ ++ uint16_t p_end; /* end of port range */ ++ ++ union { ++ struct { ++ uint16_t tcp_fop:2; /* TCP flag operations */ ++ uint16_t tcp_f:6; /* Expected value of TCP flags (U/A/P/R/S/F) */ ++ uint16_t tcp_fm:6; /* Mask of TCP flags */ ++ uint16_t tu:2; /* 11:tcp/udp, 10:tcp, 01:udp, 00:ip_proto */ ++ } tcp; ++ ++ struct { ++ uint16_t resv:14; ++ uint16_t tu:2; /* 11:tcp/udp, 10:tcp, 01:udp, 00:ip_proto */ ++ } udp; ++ ++ struct { ++ uint16_t prot:8; /* ip protocol field */ ++ uint16_t resv:6; ++ uint16_t tu:2; /* 11:tcp/udp, 10:tcp, 01:udp, 00:ip_proto */ ++ } ip; ++ }; ++} __attribute__ ((packed)); ++ ++ ++ ++#endif /* MHAL_HWNAT_ENTRY_H */ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_noe.c b/drivers/sstar/noe/hal/infinity2/mhal_noe.c +new file mode 100755 +index 000000000000..2bc1aee690e8 +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_noe.c +@@ -0,0 +1,2336 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_noe.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "registers.h" ++#include "irqs.h" ++#include "mhal_noe_reg.h" ++#include "mhal_noe.h" ++#include "mhal_noe_lro.h" ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++typedef enum { ++ E_NOE_INTERFACE_RGMII_MODE = 0, ++ E_NOE_INTERFACE_MII_MODE, ++ E_NOE_INTERFACE_RMII_MODE, ++ E_NOE_INTERFACE_INVALID_MODE, ++}EN_NOE_INTERFACE; ++ ++ ++typedef enum { ++ E_MHAL_NOE_DELAY_NS_0, ++ E_MHAL_NOE_DELAY_NS_2, ++}EN_MHAL_NOE_DELAY_TIME; ++ ++struct _mhal_mii_info{ ++ unsigned char noe_mii_force_mode; ++ u32 phy_addr; ++ EN_NOE_SPEED speed; ++ EN_NOE_DUPLEX duplex; ++ EN_NOE_INTERFACE mode; ++}; ++ ++struct _mhal_intr_info { ++ void __iomem *fe_tx_int_status; ++ void __iomem *fe_tx_int_enable; ++ void __iomem *fe_rx_int_status; ++ void __iomem *fe_rx_int_enable; ++ MS_U32 reg_int_val_p; ++ MS_U32 reg_int_val_q; ++ unsigned int tx_mask; ++ unsigned int rx_mask; ++}; ++ ++struct _mhal_noe_config{ ++ struct _mhal_mii_info mii_info[E_NOE_GE_MAC_MAX]; ++ EN_NOE_HAL_LOG noe_dbg_enable; ++ struct _mhal_intr_info intr_info; ++ EN_NOE_SEL noe_internal_phy_enable; ++ EN_NOE_SEL_PIN_MUX pin_mux; ++ MS_U8 bAN_Supported; /* 0: FALSE, 1:TRUE*/ ++ EN_MHAL_NOE_DELAY_TIME delay; ++ MS_BOOL bGPHY_Inited; ++ MS_BOOL bQoS_SetMode; ++ EN_NOE_HAL_STATUS status; ++}; ++ ++ ++typedef void (*_MHAL_DMA_GET_INFO) (void *); ++typedef void (*_MHAL_PINMUX_SEL) (void ); ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define NOE_WAIT_IDLE_THRESHOLD (1000) ++#define NOE_QOS_SET_REG(x) (*((volatile u32 *)(NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + x))) ++#define NOE_AUTO_POLLING_IS_NOT_SUPPORTED() (0) ++ ++#define NOE_IS_INVALID_MUX(mux) ((mux <= E_NOE_SEL_PIN_MUX_INVALID) || (mux >= E_NOE_SEL_PIN_MUX_MAX)) ++ ++ ++#define MHAL_NOE_WARN_INFO(fmt, args...) printk(fmt, ##args) ++ ++#define MHAL_NOE_DBG_INFO(fmt, args...) \ ++{\ ++ if (noe_config.noe_dbg_enable & E_NOE_HAL_LOG_DBG)\ ++ printk(fmt, ##args);\ ++} ++ ++#define MHAL_NOE_INTR_INFO(fmt, args...) \ ++{\ ++ if (noe_config.noe_dbg_enable & E_NOE_HAL_LOG_INTR)\ ++ printk(fmt, ##args);\ ++} ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++static void _MHal_NOE_PDMA_Get_Dbg(void *dbg_info); ++static void _MHal_NOE_QDMA_Get_Cnt(void *cnt_info); ++static void _MHal_NOE_QDMA_Get_Fq(void *fq_info); ++static void _MHal_NOE_QDMA_Get_Sch(void *rate_info); ++static void _MHal_NOE_QDMA_Get_Fc(void *fc_info); ++static void _MHal_NOE_QDMA_Get_Fsm(void *fsm_info); ++static void _MHal_NOE_QDMA_Get_Vq(void *vq_info); ++static void _MHal_NOE_QDMA_Get_Pq(void *pq_info); ++static void _MHal_NOE_GE1_To_CT0(void); ++static void _MHal_NOE_GE2_To_CT1(void); ++static void _MHal_NOE_GE1_To_CT0_GE2_To_CT1(void); ++static void _MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable); ++ ++//-------------------------------------------------------------------------------------------------- ++// Variable ++//-------------------------------------------------------------------------------------------------- ++ ++void __iomem *ethdma_sysctl_base; ++EXPORT_SYMBOL(ethdma_sysctl_base); ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++static _MHAL_DMA_GET_INFO _mhal_noe_qdma_get_info_pfn[E_NOE_QDMA_INFO_MAX] = { ++ [E_NOE_QDMA_INFO_CNT] = _MHal_NOE_QDMA_Get_Cnt, ++ [E_NOE_QDMA_INFO_FQ] = _MHal_NOE_QDMA_Get_Fq, ++ [E_NOE_QDMA_INFO_SCH] = _MHal_NOE_QDMA_Get_Sch, ++ [E_NOE_QDMA_INFO_FC] = _MHal_NOE_QDMA_Get_Fc, ++ [E_NOE_QDMA_INFO_FSM] = _MHal_NOE_QDMA_Get_Fsm, ++ [E_NOE_QDMA_INFO_VQ] = _MHal_NOE_QDMA_Get_Vq, ++ [E_NOE_QDMA_INFO_PQ] = _MHal_NOE_QDMA_Get_Pq, ++}; ++ ++static _MHAL_DMA_GET_INFO _mhal_noe_pdma_get_info_pfn[E_NOE_PDMA_INFO_MAX] = { ++ [E_NOE_PDMA_INFO_DBG] = _MHal_NOE_PDMA_Get_Dbg, ++}; ++ ++static _MHAL_PINMUX_SEL _mhal_noe_pinmux_pfn[E_NOE_SEL_PIN_MUX_MAX] = { ++ [E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP] = _MHal_NOE_GE1_To_CT0, ++ [E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP] = _MHal_NOE_GE2_To_CT1, ++ [E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP_GE2_TO_CHIPTOP] = _MHal_NOE_GE1_To_CT0_GE2_To_CT1, ++}; ++ ++static struct _mhal_noe_config noe_config = { ++ .mii_info = { ++ [E_NOE_GE_MAC1] = { ++ .noe_mii_force_mode = NOE_DISABLE, ++ .phy_addr = NOE_INVALID_PHY_ADDR, ++ .speed = E_NOE_SPEED_INVALID, ++ .duplex = E_NOE_DUPLEX_INVALID, ++ .mode = E_NOE_INTERFACE_INVALID_MODE, ++ }, ++ [E_NOE_GE_MAC2] = { ++ .noe_mii_force_mode = NOE_DISABLE, ++ .phy_addr = NOE_INVALID_PHY_ADDR, ++ .speed = E_NOE_SPEED_INVALID, ++ .duplex = E_NOE_DUPLEX_INVALID, ++ .mode = E_NOE_INTERFACE_INVALID_MODE, ++ }, ++ }, ++ .noe_dbg_enable = NOE_DISABLE, ++ .intr_info = { ++ .fe_tx_int_status = NULL, ++ .fe_tx_int_enable = NULL, ++ .fe_rx_int_status = NULL, ++ .fe_rx_int_enable = NULL, ++ }, ++ .bAN_Supported = FALSE, ++ .delay = E_MHAL_NOE_DELAY_NS_2, ++ .bGPHY_Inited = FALSE, ++ .bQoS_SetMode = TRUE, ++ .pin_mux = E_NOE_SEL_PIN_MUX_INVALID, ++}; ++ ++static inline void _MHal_NOE_Switch_MDIO(u32 addr) ++{ ++} ++ ++static inline void _MHal_NOE_Reset_SW(void) ++{ ++ unsigned int val; ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x00 << 1) = 0x0002; ++ udelay(1); ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x00 << 1) = 0x0000; ++ ++ val = MHal_NOE_Read_Reg(RSTCTRL); ++ val = val | RSTCTL_SYS_RST; ++ MHal_NOE_Write_Reg(RSTCTRL, val); ++ udelay(10); ++ MHal_NOE_Write_Reg(RSTSTAT, RSTSTAT_SWSYSRST); ++} ++ ++void MHal_NOE_Reset_SW(void) ++{ ++ _MHal_NOE_Reset_SW(); ++} ++ ++static void _MHal_NOE_Init_Clock(void) ++{ ++ /* NOE */ ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN1, 0x26) = 0x0400; ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN1, 0x28) = 0x0004; ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN1, 0x2a) = 0x0000; ++ ++ /* Reset */ ++ //_MHal_NOE_Reset_SW(); ++ ++ /* GMACPLL */ ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN1, 0x15 << 1) = 0x0000; ++ NOE_RIU_REG(NOE_RIU_BANK_ANA_MISC_GMAC, 0x69 << 1) = 0x0014; ++ NOE_RIU_REG(NOE_RIU_BANK_ANA_MISC_GMAC, 0x68 << 1) = 0xBC4F; ++ MHal_NOE_Write8_Reg(NOE_RIU_BANK_CLKGEN0, (0x63 << 1), 0x00); ++ NOE_RIU_REG(NOE_RIU_BANK_ANA_MISC_GMAC, 0x63 << 1) &= 0xFF00; ++} ++ ++static void _MHal_NOE_Set_MDIO(void) ++{ ++ NOE_RIU8_REG(0x1224, 0x04) |= 0x03; ++ NOE_RIU8_REG(0x1026, 0x0a) |= 0x40; ++ ++} ++ ++static void _MHal_NOE_GE1_To_CT0(void) ++{ ++ // Clock ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x02) = (NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x02) & 0x00FF) | 0x0C00; ++ NOE_RIU_REG(0x1026, 0x0a) |= 0x00c0; ++ NOE_RIU8_REG(0x1026, 0x00)= 0x00; ++ NOE_RIU8_REG(0x121f, 0x23)= 0x00; ++ NOE_RIU_REG(0x1224, 0x6e) = 0x1108; ++ NOE_RIU_REG(0x1224, 0x22) = 0x0088; ++ NOE_RIU_REG(0x1224, 0x24) = 0x2191; ++#ifdef CONFIG_NOE_RGMII_TX_DELAY_2NS ++ NOE_RIU_REG(0x1224, 0x26) = 0x6EE2; ++#else ++ NOE_RIU_REG(0x1224, 0x26) = 0x6CE2; ++#endif ++ NOE_RIU_REG(0x1224, 0x20) = 0xa200; ++ NOE_RIU_REG(0x1224, 0x04) = 0x0103; ++} ++ ++ ++ ++ ++ ++static void _MHal_NOE_GE2_To_CT1(void) ++{ ++ // Clock ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0xA0) = (NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0xA0) & 0x00FF) | 0x0C00; ++ ++ NOE_RIU8_REG(0x1026, 0x0b) |= 0x02; ++ NOE_RIU8_REG(0x1026, 0x00) = 0x00; ++ NOE_RIU8_REG(0x121f, 0x23) = 0x00; ++ NOE_RIU_REG(0x1224, 0xee) = 0x1108; ++ NOE_RIU_REG(0x1224, 0xa2) = 0x0088; ++ NOE_RIU_REG(0x1224, 0xa4) = 0x2191; ++#ifdef CONFIG_NOE_RGMII_TX_DELAY_2NS ++ NOE_RIU_REG(0x1224, 0xa6) = 0x6EE2; ++#else ++ NOE_RIU_REG(0x1224, 0xa6) = 0x6CE2; ++#endif ++ NOE_RIU_REG(0x1224, 0xa0) = 0xa200; ++ NOE_RIU_REG(0x1224, 0x84) = 0x0103; ++} ++ ++ ++static void _MHal_NOE_GE1_To_CT0_GE2_To_CT1(void) ++{ ++ _MHal_NOE_GE1_To_CT0(); ++ _MHal_NOE_GE2_To_CT1(); ++} ++ ++static inline void _MHal_NOE_Enable_Mdio(EN_NOE_SEL enable) ++{ ++ ++} ++ ++ ++void MHal_NOE_Write_Bits_Zero(void __iomem *addr, MS_U32 bit, MS_U32 len) ++{ ++ int reg_val; ++ int i; ++ ++ reg_val = MHal_NOE_Read_Reg(addr); ++ for (i = 0; i < len; i++) ++ reg_val &= ~(1 << (bit + i)); ++ MHal_NOE_Write_Reg(addr, reg_val); ++} ++ ++void MHal_NOE_Write_Bits_One(void __iomem *addr, MS_U32 bit, MS_U32 len) ++{ ++ unsigned int reg_val; ++ unsigned int i; ++ ++ reg_val = MHal_NOE_Read_Reg(addr); ++ for (i = 0; i < len; i++) ++ reg_val |= 1 << (bit + i); ++ MHal_NOE_Write_Reg(addr, reg_val); ++} ++ ++EN_NOE_RET MHal_NOE_Set_Pin_Mux(EN_NOE_SEL_PIN_MUX mux) ++{ ++ if (NOE_IS_INVALID_MUX(mux)) { ++ return E_NOE_RET_INVALID_PARAM; ++ } ++ MHAL_NOE_DBG_INFO("mux=%d\n",mux); ++ ++ noe_config.pin_mux = mux; ++ if (_mhal_noe_pinmux_pfn[mux] == NULL) { ++ return E_NOE_RET_INVALID_PARAM; ++ } ++ _mhal_noe_pinmux_pfn[mux](); ++ _MHal_NOE_Set_MDIO(); ++ return E_NOE_RET_TRUE; ++} ++ ++void MHal_NOE_Set_MAC_Address(EN_NOE_GE_MAC ge, unsigned char p[6]) ++{ ++ unsigned long reg_value; ++ reg_value = (p[0] << 8) | (p[1]); ++ if (ge == E_NOE_GE_MAC1) { ++ MHal_NOE_Write_Reg(GDMA1_MAC_ADRH, reg_value); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ MHal_NOE_Write_Reg(GDMA2_MAC_ADRH, reg_value); ++ } ++ reg_value = (unsigned long)((p[2] << 24) | (p[3] << 16) | (p[4] << 8) | p[5]); ++ if(ge == E_NOE_GE_MAC1) { ++ MHal_NOE_Write_Reg(GDMA1_MAC_ADRL, reg_value); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ MHal_NOE_Write_Reg(GDMA2_MAC_ADRL, reg_value); ++ } ++ MHAL_NOE_DBG_INFO("GMAC%d_MAC_ADRH -- : 0x%08x\n", ge+1, (ge == E_NOE_GE_MAC1)?MHal_NOE_Read_Reg(GDMA1_MAC_ADRH):MHal_NOE_Read_Reg(GDMA2_MAC_ADRH)); ++ MHAL_NOE_DBG_INFO("GMAC%d_MAC_ADRL -- : 0x%08x\n", ge+1, (ge == E_NOE_GE_MAC1)?MHal_NOE_Read_Reg(GDMA1_MAC_ADRL):MHal_NOE_Read_Reg(GDMA2_MAC_ADRL)); ++} ++ ++void MHal_NOE_Get_MAC_Address(EN_NOE_GE_MAC ge, unsigned char* p) ++{ ++ unsigned long reg_value; ++ unsigned long address; ++ ++ if (ge == E_NOE_GE_MAC1) { ++ address = (unsigned long)GDMA1_MAC_ADRH; ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ address = (unsigned long)GDMA2_MAC_ADRH; ++ } ++ ++ reg_value = MHal_NOE_Read_Reg(address); ++ p[0]= (reg_value>>8)&0xFF; ++ p[1]= (reg_value)&0xFF; ++ ++ if (ge == E_NOE_GE_MAC1) { ++ address = (unsigned long)GDMA1_MAC_ADRL; ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ address = (unsigned long)GDMA2_MAC_ADRL; ++ } ++ ++ reg_value = MHal_NOE_Read_Reg(address); ++ p[5]= (reg_value)&0xFF; ++ p[4]= (reg_value>>8)&0xFF; ++ p[3]= (reg_value>>16)&0xFF; ++ p[2]= (reg_value>>24)&0xFF; ++} ++ ++void MHal_NOE_Stop(void) ++{ ++ unsigned int reg_value; ++ ++ MHAL_NOE_DBG_INFO("%s()...",__FUNCTION__); ++ reg_value = MHal_NOE_Read_Reg(DMA_GLO_CFG); ++ reg_value &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); ++ MHal_NOE_Write_Reg(DMA_GLO_CFG, reg_value); ++ ++ MHAL_NOE_DBG_INFO("Done\n"); ++} ++ ++ ++void MHal_NOE_Reset_FE(void) ++{ ++ unsigned int val; ++ val = MHal_NOE_Read_Reg(RSTCTRL); ++ val = val | RSTCTL_FE_RST; ++ MHal_NOE_Write_Reg(RSTCTRL, val); ++ ++ val = val & ~(RSTCTL_FE_RST); ++ MHal_NOE_Write_Reg(RSTCTRL, val); ++} ++ ++ ++void MHal_NOE_Set_DBG(EN_NOE_HAL_LOG level) ++{ ++ noe_config.noe_dbg_enable = level; ++} ++ ++void MHal_NOE_Reset_GMAC(void) ++{ ++} ++ ++static EN_NOE_RET _MHal_NOE_Write_Mii_Mgr(u32 addr, u32 reg, u32 write_data) ++{ ++ unsigned long t_start = jiffies; ++ u32 data; ++ ++ _MHal_NOE_Switch_MDIO(addr); ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ /* make sure previous write operation is complete */ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation ongoing\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ data = (0x01 << 16) | (1 << 18) | (addr << 20) | (reg << 25) | write_data; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); /*start*/ ++ /* MHAL_NOE_DBG_INFO("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); */ ++ ++ t_start = jiffies; ++ ++ /* make sure write operation is complete */ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation Time Out\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++static EN_NOE_RET _MHal_NOE_Read_Mii_Mgr(u32 addr, u32 reg, u32 *read_data) ++{ ++ MS_U32 status = 0; ++ unsigned long t_start = jiffies; ++ MS_U32 data = 0; ++ ++ _MHal_NOE_Switch_MDIO(addr); ++ /* We enable mdio gpio purpose register, and disable it when exit. */ ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ /* make sure previous read operation is complete */ ++ while (1) { ++ /* 0 : Read/write operation complete */ ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ ++ data = (0x01 << 16) | (0x02 << 18) | (addr << 20) | (reg << 25); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ ++ /* make sure read operation is complete */ ++ t_start = jiffies; ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ status = MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0); ++ *read_data = (MS_U32)(status & 0x0000FFFF); ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation Time Out!!\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++ ++static void _MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable) ++{ ++ if (enable == E_NOE_SEL_ENABLE) ++ { ++ MHal_NOE_Write_Reg(ESW_PHY_POLLING, MHal_NOE_Read_Reg(ESW_PHY_POLLING)|(1 << 31)); ++ } ++ else{ ++ MHal_NOE_Write_Reg(ESW_PHY_POLLING, MHal_NOE_Read_Reg(ESW_PHY_POLLING)&(~(1 << 31))); ++ } ++} ++ ++ ++static MS_U8 MHal_NOE_Is_Mii_Mgr_Force_Mode(u32 addr) ++{ ++ unsigned char i = 0; ++ for (i = 0; i < E_NOE_GE_MAC_MAX; i++) ++ { ++ if (noe_config.mii_info[i].phy_addr == addr) { ++ return noe_config.mii_info[i].noe_mii_force_mode; ++ } ++ } ++ return NOE_DISABLE; ++} ++ ++static EN_NOE_RET _MHal_NOE_Set45_Mii_Mgr_Addr(u32 port_num, u32 dev_addr, u32 reg_addr) ++{ ++ unsigned long t_start = jiffies; ++ MS_U32 data = 0; ++ ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ data = (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) | reg_addr; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ ++ t_start = jiffies; ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation Time Out\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++ ++EN_NOE_RET MHal_NOE_Write45_Mii_Mgr(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data) ++{ ++ unsigned long t_start = jiffies; ++ u32 data = 0; ++ MS_U32 an_status = 0; ++ an_status = (MHal_NOE_Read_Reg(ESW_PHY_POLLING) & (1 << 31)); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++ } ++ ++ /* set address first */ ++ _MHal_NOE_Set45_Mii_Mgr_Addr(port_num, dev_addr, reg_addr); ++ udelay(10); ++ ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ ++ data = (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) | write_data; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ ++ t_start = jiffies; ++ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation Time Out\n"); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++EN_NOE_RET MHal_NOE_Read45_Mii_Mgr(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data) ++{ ++ u32 status = 0; ++ unsigned long t_start = jiffies; ++ u32 data = 0; ++ MS_U32 an_status = 0; ++ an_status = (MHal_NOE_Read_Reg(ESW_PHY_POLLING) & (1 << 31)); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++ } ++ ++ /* set address first */ ++ _MHal_NOE_Set45_Mii_Mgr_Addr(port_num, dev_addr, reg_addr); ++ udelay(10); ++ ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ data = (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) | reg_addr; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ t_start = jiffies; ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ *read_data = (MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & 0x0000FFFF); ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ _MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation Time Out!!\n"); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TIMEOUT; ++ } ++ status = MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0); ++ } ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++EN_NOE_RET MHal_NOE_Write_Mii_Mgr(u32 addr, u32 reg, u32 write_data) ++{ ++ MS_U32 an_status = 0; ++ an_status = (MHal_NOE_Read_Reg(ESW_PHY_POLLING) & (1 << 31)); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++ } ++ if (MHal_NOE_Is_Mii_Mgr_Force_Mode(addr) == NOE_ENABLE) { ++ if (addr == 31) { ++ if(_MHal_NOE_Write_Mii_Mgr(addr, 0x1f, (reg>>6)&0x3FFF) == E_NOE_RET_TRUE) { ++ if(_MHal_NOE_Write_Mii_Mgr(addr, (reg>>2) & 0xF, write_data & 0xFFFF) == E_NOE_RET_TRUE) { ++ if(_MHal_NOE_Write_Mii_Mgr(addr, (0x1 << 4), write_data >> 16) == E_NOE_RET_TRUE) { ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ } ++ } ++ else { ++ if (_MHal_NOE_Write_Mii_Mgr(addr, reg, write_data) == E_NOE_RET_TRUE) { ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ } ++ else { ++ if (_MHal_NOE_Write_Mii_Mgr(addr, reg, write_data) == E_NOE_RET_TRUE) { ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++EN_NOE_RET MHal_NOE_Read_Mii_Mgr(u32 addr, u32 reg, u32 *read_data) ++{ ++ u32 low_word; ++ u32 high_word; ++ u32 an_status = 0; ++ ++ an_status = (MHal_NOE_Read_Reg(ESW_PHY_POLLING) & (1 << 31)); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++ } ++ ++ if (MHal_NOE_Is_Mii_Mgr_Force_Mode(addr) == NOE_ENABLE) { ++ if (addr == 31) { ++ if (_MHal_NOE_Write_Mii_Mgr(addr, 0x1f, (reg >> 6) & 0x3FFF) == E_NOE_RET_TRUE) { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, (reg >> 2) & 0xF, &low_word) == E_NOE_RET_TRUE ) { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, (0x1 << 4), &high_word) == E_NOE_RET_TRUE) { ++ *read_data = (high_word << 16) | (low_word & 0xFFFF); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ } ++ } ++ else { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, reg, read_data) == E_NOE_RET_TRUE) { ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ } ++ else ++ { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, reg, read_data) == E_NOE_RET_TRUE) { ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ ++ return E_NOE_RET_FALSE; ++} ++ ++ ++ ++MS_BOOL MHal_NOE_Support_Auto_Polling(void) ++{ ++ return TRUE; ++} ++ ++void MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable) ++{ ++ MS_U32 reg_value; ++ ++ /* FIXME: we don't know how to deal with PHY end addr */ ++ reg_value = MHal_NOE_Read_Reg(ESW_PHY_POLLING); ++ reg_value &= ~(0x1f); ++ reg_value &= ~(0x1f << 8); ++ ++ if (E_NOE_SEL_ENABLE == enable) { ++ reg_value |= (1 << 31); ++ } ++ else { ++ reg_value &= 0x7FFFFFFF; ++ } ++ ++ /* setup PHY address for auto polling (Start Addr). */ ++ reg_value |= noe_config.mii_info[E_NOE_GE_MAC1].phy_addr & 0x1F; ++ ++ /* setup PHY address for auto polling (End Addr). */ ++ reg_value |= (noe_config.mii_info[E_NOE_GE_MAC2].phy_addr & 0x1F) << 8; ++ ++ ++ MHAL_NOE_DBG_INFO("[%s][%d] reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value); ++ MHal_NOE_Write_Reg(ESW_PHY_POLLING, reg_value); ++} ++ ++void MHal_NOE_Force_Link_Mode(EN_NOE_GE_MAC ge, EN_NOE_SPEED speed, EN_NOE_DUPLEX duplex) ++{ ++ MS_U32 reg_value = 0; ++ ++ if(ge == E_NOE_GE_MAC1) { ++ reg_value = MHal_NOE_Read_Reg(NOE_MAC_P1_MCR); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ reg_value = MHal_NOE_Read_Reg(NOE_MAC_P2_MCR); ++ } ++ ++ MHAL_NOE_DBG_INFO("GMAC%d: 0x%x \n", ge+1 , reg_value); ++ if ((duplex == E_NOE_DUPLEX_INVALID) && (speed == E_NOE_SPEED_INVALID)) { ++ reg_value &= (~0x8031); ++ } ++ else { ++ reg_value &= (~(0x2|0xC)); ++ reg_value |= (0x01 | 0x30 | 0xE000); ++ ++ if(speed == E_NOE_SPEED_1000) { ++ reg_value |= 0x8; ++ if (duplex == E_NOE_DUPLEX_FULL) { ++ reg_value |= 0x2; ++ } ++ } ++ else if(speed == E_NOE_SPEED_100) { ++ reg_value |= 0x4; ++ if (duplex == E_NOE_DUPLEX_FULL) { ++ reg_value |= 0x2; ++ } ++ } ++ else { ++ if (duplex == E_NOE_DUPLEX_FULL) { ++ reg_value |= 0x2; ++ } ++ } ++ } ++ ++ if(ge == E_NOE_GE_MAC1) { ++ MHal_NOE_Write_Reg(NOE_MAC_P1_MCR, reg_value); ++ MHAL_NOE_DBG_INFO("GMAC1: 0x%x \n",MHal_NOE_Read_Reg(NOE_MAC_P1_MCR)); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ MHal_NOE_Write_Reg(NOE_MAC_P2_MCR, reg_value); ++ MHAL_NOE_DBG_INFO("GMAC2: 0x%x \n",MHal_NOE_Read_Reg(NOE_MAC_P2_MCR)); ++ } ++} ++ ++static void _MHal_NOE_Set_Interface_Mode(EN_NOE_GE_MAC ge, EN_NOE_INTERFACE mode) ++{ ++ MS_U32 val = 0; ++ if(ge == E_NOE_GE_MAC1) { ++ val = MHal_NOE_Read_Reg(SYSCFG1) & (~(0x3 << 12)); /* E_NOE_INTERFACE_RGMII_MODE */ ++ if (mode == E_NOE_INTERFACE_MII_MODE) ++ val = val | BIT(12); ++ else if (mode == E_NOE_INTERFACE_RMII_MODE) ++ val = val | BIT(13); ++ MHal_NOE_Write_Reg(SYSCFG1, val); ++ noe_config.mii_info[E_NOE_GE_MAC1].mode = mode; ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ val = MHal_NOE_Read_Reg(SYSCFG1) & (~(0x3 << 14)); /* E_NOE_INTERFACE_RGMII_MODE */ ++ if (mode == E_NOE_INTERFACE_MII_MODE) ++ val = val | BIT(14); ++ else if (mode == E_NOE_INTERFACE_RMII_MODE) ++ val = val | BIT(15)| BIT(14); ++ MHal_NOE_Write_Reg(SYSCFG1, val); ++ noe_config.mii_info[E_NOE_GE_MAC2].mode = mode; ++ } ++} ++ ++void MHal_NOE_Init_Mii_Mgr(EN_NOE_GE_MAC ge, u32 phy_addr, unsigned char force_mode) ++{ ++ if (ge >= E_NOE_GE_MAC_MAX) { ++ return; ++ } ++ noe_config.mii_info[ge].noe_mii_force_mode = force_mode; ++ noe_config.mii_info[ge].phy_addr = phy_addr; ++} ++ ++ ++EN_NOE_RET MHal_NOE_LRO_Set_Ring_Cfg(EN_NOE_RING ring_no, unsigned int sip, unsigned int dip, unsigned int sport, unsigned int dport) ++{ ++ MS_U32 ring_idx; ++ if ((ring_no != E_NOE_RING_NO1) && ++ (ring_no != E_NOE_RING_NO2) && ++ (ring_no != E_NOE_RING_NO3)) { ++ MHAL_NOE_DBG_INFO("invalid ring_no=%d\n", ring_no); ++ return E_NOE_RET_INVALID_PARAM; ++ } ++ ++ ++ if (ring_no == E_NOE_RING_NO1) ++ ring_idx = ADMA_RX_RING1; ++ else if (ring_no == E_NOE_RING_NO2) ++ ring_idx = ADMA_RX_RING2; ++ else if (ring_no == E_NOE_RING_NO3) ++ ring_idx = ADMA_RX_RING3; ++ ++ MHAL_NOE_DBG_INFO("set_fe_lro_ring%d_cfg()\n", ring_idx); ++ ++ /* 1. Set RX ring mode to force port */ ++ SET_PDMA_RXRING_MODE(ring_idx, PDMA_RX_FORCE_PORT); ++ ++ /* 2. Configure lro ring */ ++ /* 2.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ring_idx, sport); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ring_idx, dport); ++ /* 2.2 set src/destination IPs */ ++ if(ring_idx == E_NOE_RING_NO1) { ++ MHal_NOE_Write_Reg(LRO_RX_RING1_SIP_DW0, sip); ++ MHal_NOE_Write_Reg(LRO_RX_RING1_DIP_DW0, dip); ++ } ++ else if(ring_idx == E_NOE_RING_NO2) { ++ MHal_NOE_Write_Reg(LRO_RX_RING2_SIP_DW0, sip); ++ MHal_NOE_Write_Reg(LRO_RX_RING2_DIP_DW0, dip); ++ } ++ else if(ring_idx == E_NOE_RING_NO3) { ++ MHal_NOE_Write_Reg(LRO_RX_RING3_SIP_DW0, sip); ++ MHal_NOE_Write_Reg(LRO_RX_RING3_DIP_DW0, dip); ++ } ++ /* 2.3 IPv4 force port mode */ ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ring_idx, 1); ++ /* 2.4 IPv6 force port mode */ ++ SET_PDMA_RXRING_IPV6_FORCE_MODE(ring_idx, 1); ++ ++ /* 3. Set Age timer: 10 msec. */ ++ SET_PDMA_RXRING_AGE_TIME(ring_idx, HW_LRO_AGE_TIME); ++ ++ /* 4. Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ring_idx, 1); ++ ++ return E_NOE_RET_TRUE; ++} ++ ++ ++void MHal_NOE_LRO_Set_Cfg(void) ++{ ++ unsigned int reg_val = 0; ++ ++ MHAL_NOE_DBG_INFO("set_fe_lro_glo_cfg()\n"); ++ ++ /* 1 Set max AGG timer: 10 msec. */ ++ SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME); ++ ++ /* 2. Set max LRO agg count */ ++ SET_PDMA_LRO_MAX_AGG_CNT(HW_LRO_MAX_AGG_CNT); ++ ++ /* PDMA prefetch enable setting */ ++ SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN | ADMA_MULTI_RXD_PREFETCH_EN); ++ /* 2.1 IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3. Polling relinguish */ ++ while (1) { ++ if (MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) { ++ MHAL_NOE_DBG_INFO("Polling HW LRO RELINGUISH...\n"); ++ } ++ else ++ break; ++ } ++ ++ /* 4. Enable LRO */ ++ reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); ++ reg_val |= PDMA_LRO_EN; ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); ++} ++ ++ ++void MHal_NOE_LRO_Set_Ip(unsigned int lan_ip) ++{ ++ /* Set IP: LAN IP */ ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW0, lan_ip); ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW1, 0); ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW2, 0); ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(E_NOE_RING_NO0, 1); ++} ++ ++ ++void MHal_NOE_LRO_Set_Auto_Learn_Cfg(void) ++{ ++ unsigned int reg_val = 0; ++ ++ /* Set RX ring1~3 to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(E_NOE_RING_NO1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(E_NOE_RING_NO2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(E_NOE_RING_NO3, PDMA_RX_AUTO_LEARN); ++ ++ /* Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO0, 1); ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO1, 1); ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO2, 1); ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO3, 1); ++ ++ /* Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(E_NOE_RING_NO1, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(E_NOE_RING_NO2, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(E_NOE_RING_NO3, HW_LRO_AGE_TIME); ++ ++ /* Set max AGG timer */ ++ SET_PDMA_RXRING_AGG_TIME(E_NOE_RING_NO1, HW_LRO_AGG_TIME); ++ SET_PDMA_RXRING_AGG_TIME(E_NOE_RING_NO2, HW_LRO_AGG_TIME); ++ SET_PDMA_RXRING_AGG_TIME(E_NOE_RING_NO3, HW_LRO_AGG_TIME); ++ ++ /* Set max LRO agg count */ ++ SET_PDMA_RXRING_MAX_AGG_CNT(E_NOE_RING_NO1, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(E_NOE_RING_NO2, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(E_NOE_RING_NO3, HW_LRO_MAX_AGG_CNT); ++ ++ /* IPv6 LRO enable */ ++ SET_PDMA_LRO_IPV6_EN(1); ++ ++ /* IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* TCP push option check disable */ ++ /* SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(0); */ ++ /* PDMA prefetch enable setting */ ++ SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN | ADMA_MULTI_RXD_PREFETCH_EN); ++ /* switch priority comparison to packet count mode */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_PKT_CNT_MODE); ++ ++ /* bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(HW_LRO_BW_THRE); ++ ++ /* auto-learn score delta setting */ ++ MHal_NOE_Write_Reg(LRO_ALT_SCORE_DELTA, HW_LRO_REPLACE_DELTA); ++ ++ /* Set ALT timer to 20us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT); ++ /* Set ALT refresh timer to 1 sec. (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME); ++ ++ /* the least remaining room of SDL0 in RXD for lro aggregation */ ++ SET_PDMA_LRO_MIN_RXD_SDL(HW_LRO_SDL_REMAIN_ROOM); ++ ++ /* Polling relinguish */ ++ while (1) { ++ if (MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) { ++ MHAL_NOE_DBG_INFO("Polling HW LRO RELINGUISH...\n"); ++ } ++ else ++ break; ++ } ++ ++ /* Enable HW LRO */ ++ reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); ++ reg_val |= PDMA_LRO_EN; ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); ++ ++} ++ ++ ++ ++ ++void MHal_NOE_LRO_Update_Calc_Idx(MS_U32 ring_no, MS_U32 dma_owner_idx) ++{ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_RX_CALC_IDX0 + (ring_no << 4) , dma_owner_idx); ++} ++ ++ ++void MHal_NOE_LRO_Reset_Rx_Ring(EN_NOE_RING rx_ring_no, u32 phy_addr, u32 desc_num, u32 desc_idx) ++{ ++ if (rx_ring_no == E_NOE_RING_NO3) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR3, phy_addr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT3, desc_num); ++ MHal_NOE_Write_Reg(RX_CALC_IDX3, desc_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX3); ++ } ++ else if (rx_ring_no == E_NOE_RING_NO2) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR2, phy_addr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT2, desc_num); ++ MHal_NOE_Write_Reg(RX_CALC_IDX2, desc_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX2); ++ } ++ else if (rx_ring_no == E_NOE_RING_NO1) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR1, phy_addr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT1, desc_num); ++ MHal_NOE_Write_Reg(RX_CALC_IDX1, desc_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX1); ++ } ++} ++ ++ ++EN_NOE_RET MHal_NOE_LRO_Get_Ring_Info(EN_NOE_DMA dma, EN_NOE_DIR dir, EN_NOE_RING ring_no, struct noe_dma_info * info) ++{ ++ EN_NOE_RET ret = E_NOE_RET_FALSE; ++ if (E_NOE_DIR_TX == dir) { ++ if (dma & E_NOE_DMA_PACKET) { ++ if (ring_no == E_NOE_RING_NO0) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR0); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT0); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX0); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX0); ++ } ++ else if (ring_no == E_NOE_RING_NO1) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR1); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT1); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX1); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX1); ++ } ++ else if (ring_no == E_NOE_RING_NO2) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR2); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT2); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX2); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX2); ++ } ++ else if (ring_no == E_NOE_RING_NO3) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR3); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT3); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX3); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX3); ++ } ++ } ++ else if (dma & E_NOE_DMA_QUEUE) { ++ ret = E_NOE_RET_TRUE; ++ info->adr_st.ctx_adr = MHal_NOE_Read_Reg(QTX_CTX_PTR); ++ info->adr_st.dtx_adr = MHal_NOE_Read_Reg(QTX_DTX_PTR); ++ info->adr_st.crx_adr = MHal_NOE_Read_Reg(QTX_CRX_PTR); ++ info->adr_st.drx_adr = MHal_NOE_Read_Reg(QTX_DRX_PTR); ++ ++ } ++ } ++ else if (E_NOE_DIR_RX == dir){ ++ if (dma & E_NOE_DMA_PACKET) { ++ if (ring_no == E_NOE_RING_NO0) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR0); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT0); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX0); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX0); ++ } ++ else if (ring_no == E_NOE_RING_NO1) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR1); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT1); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX1); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX1); ++ } ++ else if (ring_no == E_NOE_RING_NO2) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR2); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT2); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX2); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX2); ++ } ++ else if (ring_no == E_NOE_RING_NO3) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR3); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT3); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX3); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX3); ++ } ++ } ++ else if (dma & E_NOE_DMA_QUEUE) { ++ if (ring_no == E_NOE_RING_NO0) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(QRX_BASE_PTR_0); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(QRX_MAX_CNT_0); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(QRX_CRX_IDX_0); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(QRX_DRX_IDX_0); ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++ ++ ++void MHal_NOE_LRO_Get_Calc_Idx(struct noe_lro_calc_idx *calc_idx) ++{ ++ calc_idx->ring1 = MHal_NOE_Read_Reg(RX_CALC_IDX1); ++ calc_idx->ring2 = MHal_NOE_Read_Reg(RX_CALC_IDX2); ++ calc_idx->ring3 = MHal_NOE_Read_Reg(RX_CALC_IDX3); ++} ++ ++void MHal_NOE_Dump_Mii_Mgr(int port_no, int from, int to, int is_local, int page_no) ++{ ++/// do nothing ++} ++ ++ ++ ++void MHal_NOE_Init_Sep_Intr(EN_NOE_DMA dma, EN_NOE_DIR dir) ++{ ++ if (E_NOE_DIR_TX == dir) { ++ if (E_NOE_DMA_PACKET == dma) { ++ noe_config.intr_info.fe_tx_int_status = (void __iomem *)CONFIG_NOE_REG_FE_INT_STATUS; ++ noe_config.intr_info.fe_tx_int_enable = (void __iomem *)CONFIG_NOE_REG_FE_INT_ENABLE; ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ noe_config.intr_info.fe_tx_int_status = (void __iomem *)QFE_INT_STATUS; ++ noe_config.intr_info.fe_tx_int_enable = (void __iomem *)QFE_INT_ENABLE; ++ } ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ if (E_NOE_DMA_PACKET == dma) { ++ noe_config.intr_info.fe_rx_int_status = (void __iomem *)CONFIG_NOE_REG_FE_INT_STATUS; ++ noe_config.intr_info.fe_rx_int_enable = (void __iomem *)CONFIG_NOE_REG_FE_INT_ENABLE; ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ noe_config.intr_info.fe_rx_int_status = (void __iomem *)QFE_INT_STATUS; ++ noe_config.intr_info.fe_rx_int_enable = (void __iomem *)QFE_INT_ENABLE; ++ } ++ } ++} ++ ++ ++ ++MS_U8 MHal_NOE_Get_Sep_Intr_Status(EN_NOE_DIR dir) ++{ ++ unsigned int reg_int_val; ++ if (E_NOE_DIR_TX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_status); ++ if (reg_int_val & TX_INT_ALL) { ++ return NOE_TRUE; ++ } ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_status); ++ if (reg_int_val & RX_INT_ALL) { ++ return NOE_TRUE; ++ } ++ } ++ ++ return NOE_FALSE; ++} ++ ++void MHal_NOE_Clear_Sep_Intr_Status(EN_NOE_DIR dir) ++{ ++ if (E_NOE_DIR_TX == dir) { ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_status, TX_INT_ALL); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_status, RX_INT_ALL); ++ } ++} ++ ++void MHal_NOE_Clear_Sep_Intr_Specific_Status(EN_NOE_DIR dir, EN_NOE_INTR_CLR_STATUS status) ++{ ++ MS_U32 reg_int_val; ++ if (E_NOE_DIR_TX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_status); ++ if(status == E_NOE_INTR_CLR_EXCEPT_RX) { ++ reg_int_val &= ~(RX_INT_ALL); ++ } ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_status, reg_int_val); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_status); ++ if(status == E_NOE_INTR_CLR_EXCEPT_TX) { ++ reg_int_val &= ~(TX_INT_ALL); ++ } ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_status, reg_int_val); ++ } ++} ++ ++void MHal_NOE_Enable_Sep_Intr(EN_NOE_DIR dir) ++{ ++ unsigned int reg_int_mask; ++ ++ if (E_NOE_DIR_TX == dir) { ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_enable); ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, reg_int_mask | noe_config.intr_info.tx_mask); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_enable); ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, reg_int_mask | noe_config.intr_info.rx_mask); ++ } ++} ++ ++ ++void MHal_NOE_Disable_Sep_Intr(EN_NOE_DIR dir) ++{ ++ unsigned int reg_int_mask; ++ if (E_NOE_DIR_TX == dir) { ++ /* Disable TX interrupt */ ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_enable); ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, reg_int_mask & ~(TX_INT_ALL)); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ /* Disable RX interrupt */ ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_enable); ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, reg_int_mask & ~(RX_INT_ALL)); ++ } ++ else if (E_NOE_DIR_BOTH == dir) { ++ /* Disable TX interrupt */ ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, 0); ++ /* Disable RX interrupt */ ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, 0); ++ } ++} ++ ++ ++void MHal_NOE_Enable_Sep_Delay_Intr(EN_NOE_DMA dma, EN_NOE_DELAY delay_intr) ++{ ++ if (E_NOE_DMA_PACKET & dma) { ++ if(delay_intr == E_NOE_DLY_ENABLE) { ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_DLY_INT_CFG, DELAY_INT_INIT); ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, FE_INT_DLY_INIT); ++ } ++ else{ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, FE_INT_ALL); ++ } ++ } ++ else if (E_NOE_DMA_QUEUE & dma){ ++ if(delay_intr == E_NOE_DLY_ENABLE) { ++ MHal_NOE_Write_Reg(QDMA_DELAY_INT, DELAY_INT_INIT); ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, QFE_INT_DLY_INIT); ++ MHAL_NOE_DBG_INFO("[%s][%d] QFE_INT_ENABLE = %0X\n",__FUNCTION__,__LINE__, MHal_NOE_Read_Reg(QFE_INT_ENABLE)); ++ } ++ else { ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, QFE_INT_ALL); ++ MHAL_NOE_DBG_INFO("[%s][%d] QFE_INT_ENABLE = %0X\n",__FUNCTION__,__LINE__, MHal_NOE_Read_Reg(QFE_INT_ENABLE)); ++ } ++ } ++} ++ ++ ++void MHal_NOE_Set_Grp_Intr(unsigned char delay_intr, unsigned char rx_only) ++{ ++ if (delay_intr == NOE_TRUE) { ++ /* PDMA setting */ ++ MHal_NOE_Write_Reg(PDMA_INT_GRP1, TX_DLY_INT); ++ MHal_NOE_Write_Reg(PDMA_INT_GRP2, RX_DLY_INT); ++ /* QDMA setting */ ++ MHal_NOE_Write_Reg(QDMA_INT_GRP1, RLS_DLY_INT); ++ MHal_NOE_Write_Reg(QDMA_INT_GRP2, RX_DLY_INT); ++ } ++ else { ++ /* PDMA setting */ ++ MHal_NOE_Write_Reg(PDMA_INT_GRP1, TX_DONE_INT0); ++ MHal_NOE_Write_Reg(PDMA_INT_GRP2, RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3); ++ ++ if (rx_only) { ++ /* QDMA setting */ ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220, RLS_DLY_INT); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224, RX_DLY_INT); ++ } ++ else { ++ /* QDMA setting */ ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, QFE_INT_ALL); ++ MHal_NOE_Write_Reg(QDMA_INT_GRP1, RLS_DONE_INT); ++ MHal_NOE_Write_Reg(QDMA_INT_GRP2, RX_DONE_INT0 | RX_DONE_INT1); ++ } ++ } ++ ++ MHal_NOE_Write_Reg(FE_INT_GRP, 0x21021001); ++ /* FE[0] */ ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x1D << 1) |= 0x00A0; ++ /* FE[1] */ ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x33 << 1) |= 0x0060; ++} ++ ++ ++ ++void MHal_NOE_Set_Vlan_Info(void) ++{ ++ /*VLAN_IDX 0 = VLAN_ID 0 ++ * ......... ++ * VLAN_IDX 15 = VLAN ID 15 ++ * ++ */ ++ /* frame engine will push VLAN tag ++ * regarding to VIDX feild in Tx desc. ++ */ ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xa8, 0x00010000); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xac, 0x00030002); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xb0, 0x00050004); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xb4, 0x00070006); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xb8, 0x00090008); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xbc, 0x000b000a); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xc0, 0x000d000c); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xc4, 0x000f000e); ++} ++ ++ ++void MHal_NOE_Offoad_Checksum(EN_NOE_GE_MAC ge, unsigned char offload) ++{ ++ unsigned int reg_val, reg_csg; ++ unsigned int reg_val2 = 0; ++ ++ reg_csg = MHal_NOE_Read_Reg(CDMA_CSG_CFG); ++ reg_val = MHal_NOE_Read_Reg(GDMA1_FWD_CFG); ++ reg_val2 = MHal_NOE_Read_Reg(GDMA2_FWD_CFG); ++ if(ge == E_NOE_GE_MAC1) { ++ /* set unicast/multicast/broadcast frame to cpu */ ++ reg_val &= ~0xFFFF; ++ reg_val |= GDMA1_FWD_PORT; ++ reg_csg &= ~0x7; ++ if (offload == NOE_ENABLE) { ++ /* enable ipv4 header checksum check */ ++ reg_val |= GDM1_ICS_EN; ++ reg_csg |= ICS_GEN_EN; ++ ++ /* enable tcp checksum check */ ++ reg_val |= GDM1_TCS_EN; ++ reg_csg |= TCS_GEN_EN; ++ ++ /* enable udp checksum check */ ++ reg_val |= GDM1_UCS_EN; ++ reg_csg |= UCS_GEN_EN; ++ } ++ else { ++ /* disable ipv4 header checksum check */ ++ reg_val &= ~GDM1_ICS_EN; ++ reg_csg &= ~ICS_GEN_EN; ++ ++ /* disable tcp checksum check */ ++ reg_val &= ~GDM1_TCS_EN; ++ reg_csg &= ~TCS_GEN_EN; ++ ++ /* disable udp checksum check */ ++ reg_val &= ~GDM1_UCS_EN; ++ reg_csg &= ~UCS_GEN_EN; ++ } ++ MHal_NOE_Write_Reg(GDMA1_FWD_CFG, reg_val); ++ MHal_NOE_Write_Reg(CDMA_CSG_CFG, reg_csg); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ ++ if (offload == NOE_ENABLE) { ++ reg_val2 &= ~0xFFFF; ++ reg_val2 |= GDMA2_FWD_PORT; ++ reg_val2 |= GDM1_ICS_EN; ++ reg_val2 |= GDM1_TCS_EN; ++ reg_val2 |= GDM1_UCS_EN; ++ } ++ else { ++ reg_val2 &= ~GDM1_ICS_EN; ++ reg_val2 &= ~GDM1_TCS_EN; ++ reg_val2 &= ~GDM1_UCS_EN; ++ } ++ MHal_NOE_Write_Reg(GDMA2_FWD_CFG, reg_val2); ++ } ++} ++ ++ ++void MHal_NOE_GLO_Reset(void) ++{ ++ /*FE_RST_GLO register definition - ++ *Bit 0: PSE Rest ++ *Reset PSE after re-programming PSE_FQ_CFG. ++ */ ++ MS_U32 reg_val = 0x1; ++ MHal_NOE_Write_Reg(FE_RST_GL, reg_val); ++ MHal_NOE_Write_Reg(FE_RST_GL, 0); /* update for RSTCTL issue */ ++ ++ MHAL_NOE_DBG_INFO("CDMA_CSG_CFG = %0X\n", MHal_NOE_Read_Reg(CDMA_CSG_CFG)); ++ MHAL_NOE_DBG_INFO("GDMA1_FWD_CFG = %0X\n", MHal_NOE_Read_Reg(GDMA1_FWD_CFG)); ++ MHAL_NOE_DBG_INFO("GDMA2_FWD_CFG = %0X\n", MHal_NOE_Read_Reg(GDMA2_FWD_CFG)); ++} ++ ++ ++void MHal_NOE_LRO_Set_Prefetch(void) ++{ ++ /* enable RXD prefetch of ADMA */ ++ unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); ++ reg_val &= ~PDMA_LRO_RXD_PREFETCH_EN; ++ reg_val |= (ADMA_RXD_PREFETCH_EN | ADMA_MULTI_RXD_PREFETCH_EN); ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); ++ MHAL_NOE_DBG_INFO("[%s][%d]ADMA_LRO_CTRL_DW0=0x%X\n",__FUNCTION__,__LINE__,MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0)); ++} ++ ++EN_NOE_RET MHal_NOE_Dma_Is_Idle(EN_NOE_DMA dma) ++{ ++ unsigned int reg_val, loop_cnt = 0; ++ void __iomem *phy_adr = PDMA_GLO_CFG; ++ ++ MHAL_NOE_DBG_INFO("[%s][%d]dma = 0x%x \n",__FUNCTION__,__LINE__,dma); ++ if (E_NOE_DMA_PACKET & dma) { ++ phy_adr = PDMA_GLO_CFG; ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ phy_adr = QDMA_GLO_CFG; ++ } ++ else { ++ return E_NOE_RET_FALSE; ++ } ++ while (1) { ++ if (loop_cnt++ > NOE_WAIT_IDLE_THRESHOLD) ++ break; ++ reg_val = MHal_NOE_Read_Reg(phy_adr); ++ if ((reg_val & RX_DMA_BUSY)) { ++ MHAL_NOE_DBG_INFO("\n RX_DMA_BUSY !!! "); ++ continue; ++ } ++ if ((reg_val & TX_DMA_BUSY)) { ++ MHAL_NOE_DBG_INFO("\n TX_DMA_BUSY !!! "); ++ continue; ++ } ++ return E_NOE_RET_TRUE; ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++void MHal_NOE_Dma_Init_Global_Config(EN_NOE_DMA dma) ++{ ++ unsigned int reg_val; ++ if (E_NOE_DMA_PACKET == dma) { ++ reg_val = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS | MULTI_EN | ADMA_RX_BT_SIZE_32DWORDS); ++ reg_val |= (RX_2B_OFFSET); ++ MHal_NOE_Write_Reg(PDMA_GLO_CFG, reg_val); ++ MHAL_NOE_DBG_INFO("[%s][%d]PDMA_GLO_CFG=0x%x\n",__FUNCTION__,__LINE__,MHal_NOE_Read_Reg(PDMA_GLO_CFG)); ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ reg_val = MHal_NOE_Read_Reg(QDMA_GLO_CFG); ++ reg_val &= 0x000000FF; ++ ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, reg_val); ++ reg_val = MHal_NOE_Read_Reg(QDMA_GLO_CFG); ++ ++ /* Enable randon early drop and set drop threshold automatically */ ++ if (E_NOE_DMA_QUEUE_WITH_SFQ != dma) ++ MHal_NOE_Write_Reg(QDMA_FC_THRES, 0x4444); ++ ++ MHal_NOE_Write_Reg(QDMA_HRED2, 0x0); ++ ++ reg_val = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS); ++ reg_val |= (RX_2B_OFFSET); ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, reg_val); ++ ++ MHAL_NOE_DBG_INFO("Enable QDMA TX NDP coherence check and re-read mechanism\n"); ++ reg_val = MHal_NOE_Read_Reg(QDMA_GLO_CFG); ++ reg_val = reg_val | 0x400 | 0x100000; ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, reg_val); ++ MHAL_NOE_DBG_INFO("***********QDMA_GLO_CFG=0x%x\n", MHal_NOE_Read_Reg(QDMA_GLO_CFG)); ++ } ++} ++ ++void MHal_NOE_DMA_Init(EN_NOE_DMA dma, EN_NOE_DIR dir, EN_NOE_RING ring_no, struct noe_dma_info *dma_info) ++{ ++ int i = 0; ++ int page, queue; ++ ++ MHAL_NOE_DBG_INFO("dma,dir = 0x%0X,0x%0X \n",dma,dir); ++ if ((dma & E_NOE_DMA_QUEUE) && (dir == E_NOE_DIR_TX)) { ++ MHAL_NOE_DBG_INFO("ctx = 0x%0X \n",(MS_U32) dma_info->adr_st.ctx_adr); ++ MHAL_NOE_DBG_INFO("dtx = 0x%0X \n",(MS_U32) dma_info->adr_st.dtx_adr); ++ MHAL_NOE_DBG_INFO("crx = 0x%0X \n",(MS_U32) dma_info->adr_st.crx_adr); ++ MHAL_NOE_DBG_INFO("drx = 0x%0X \n",(MS_U32) dma_info->adr_st.drx_adr); ++ } ++ else { ++ MHAL_NOE_DBG_INFO("base_adr = 0x%0X\n",(MS_U32)dma_info->ring_st.base_adr); ++ MHAL_NOE_DBG_INFO("max_cnt = 0x%0X\n",dma_info->ring_st.max_cnt); ++ MHAL_NOE_DBG_INFO("cpu_idx = 0x%0X \n\n",dma_info->ring_st.cpu_idx); ++ } ++ ++ ++ if(dma & E_NOE_DMA_PACKET) { ++ if (dir == E_NOE_DIR_RX) { ++ if (ring_no == E_NOE_RING_NO0) { ++ /* Tell the adapter where the RX rings are located. */ ++ MHal_NOE_Write_Reg(RX_BASE_PTR0, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT0, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX0, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX0); ++ } ++ else if (ring_no == E_NOE_RING_NO3) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR3, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT3, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX3, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX3); ++ } ++ else if (ring_no == E_NOE_RING_NO2) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR2, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT2, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX2, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX2); ++ } ++ else if (ring_no == E_NOE_RING_NO1) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR1, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT1, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX1, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX1); ++ } ++ } ++ else if (dir == E_NOE_DIR_TX) { ++ /* Tell the adapter where the TX rings are located. */ ++ MHal_NOE_Write_Reg(TX_BASE_PTR0, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(TX_MAX_CNT0, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(TX_CTX_IDX0, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DTX_IDX0); ++ } ++ } ++ else if(dma & E_NOE_DMA_QUEUE) { ++ if (dir == E_NOE_DIR_RX) { ++ /* Tell the adapter where the RX rings are located. */ ++ MHal_NOE_Write_Reg(QRX_BASE_PTR_0, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(QRX_MAX_CNT_0, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(QRX_CRX_IDX_0, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(QDMA_RST_CFG, PST_DRX_IDX0); ++ } ++ else if (dir == E_NOE_DIR_TX) { ++ MHal_NOE_Write_Reg(QTX_CTX_PTR, dma_info->adr_st.ctx_adr); ++ MHal_NOE_Write_Reg(QTX_DTX_PTR, dma_info->adr_st.dtx_adr); ++ MHal_NOE_Write_Reg(QTX_CRX_PTR, dma_info->adr_st.crx_adr); ++ MHal_NOE_Write_Reg(QTX_DRX_PTR, dma_info->adr_st.drx_adr); ++ MHal_NOE_Write_Reg(QTX_SCH_1, 0x80000000); ++ for (i = 0; i < NUM_PQ; i++) { ++ page = i / QUEUE_OFFSET; ++ queue = i & (QUEUE_OFFSET - 1); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page); ++ MHal_NOE_Write_Reg(QTX_CFG_0 + QUEUE_OFFSET * queue, (NUM_PQ_RESV | (NUM_PQ_RESV << 8))); ++ } ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ } ++ } ++} ++ ++ ++ ++void MHal_NOE_Get_Intr_Info(struct noe_intr_info *info) ++{ ++ info->fe_intr_enable = MHal_NOE_Read_Reg(FE_INT_ENABLE); ++ info->fe_intr_mask = MHal_NOE_Read_Reg(INT_MASK); ++ info->fe_intr_status = MHal_NOE_Read_Reg(FE_INT_STATUS); ++ info->delay_intr_cfg = MHal_NOE_Read_Reg(DLY_INT_CFG); ++ info->qfe_intr_enable = MHal_NOE_Read_Reg(QFE_INT_ENABLE); ++ info->qfe_intr_mask = MHal_NOE_Read_Reg(QDMA_INT_MASK); ++ info->qfe_intr_status = MHal_NOE_Read_Reg(QFE_INT_STATUS); ++} ++ ++ ++ ++void MHal_NOE_Get_Mac_Info(EN_NOE_GE_MAC ge, struct noe_mac_info *info) ++{ ++ void __iomem *reg_base; ++ ++ if(ge == E_NOE_GE_MAC1) { ++ reg_base = NOE_REG_FRAME_ENGINE_BASE + 0x2400; ++ info->stat.control = MHal_NOE_Read_Reg(NOE_MAC_P1_MCR); ++ info->stat.status = MHal_NOE_Read_Reg(NOE_MAC_P1_SR); ++ } ++ else if (ge == E_NOE_GE_MAC2) { ++ reg_base = NOE_REG_FRAME_ENGINE_BASE + 0x2440; ++ info->stat.control = MHal_NOE_Read_Reg(NOE_MAC_P2_MCR); ++ info->stat.status = MHal_NOE_Read_Reg(NOE_MAC_P2_SR); ++ } ++ else ++ return; ++ ++ info->rx.good_cnt = MHal_NOE_Read_Reg(reg_base); ++ info->rx.good_pkt = MHal_NOE_Read_Reg(reg_base + 0x08); ++ info->rx.overflow_err = MHal_NOE_Read_Reg(reg_base + 0x10); ++ info->rx.fcs_err = MHal_NOE_Read_Reg(reg_base + 0x14); ++ info->rx.ser_cnt = MHal_NOE_Read_Reg(reg_base + 0x18); ++ info->rx.ler_pkt = MHal_NOE_Read_Reg(reg_base + 0x1C); ++ info->rx.chk_err = MHal_NOE_Read_Reg(reg_base + 0x20); ++ info->rx.flow_ctrl = MHal_NOE_Read_Reg(reg_base + 0x24); ++ ++ info->tx.skip_cnt = MHal_NOE_Read_Reg(reg_base + 0x28); ++ info->tx.collision_cnt = MHal_NOE_Read_Reg(reg_base + 0x2C); ++ info->tx.good_cnt = MHal_NOE_Read_Reg(reg_base + 0x30); ++ info->tx.good_pkt = MHal_NOE_Read_Reg(reg_base + 0x38); ++} ++ ++void MHal_NOE_Get_Pse_Info(struct noe_pse_info *info) ++{ ++ info->min_free_cnt = (MHal_NOE_Read_Reg(FE_PSE_FREE) & 0xff0000) >> 16; ++ info->free_cnt = MHal_NOE_Read_Reg(FE_PSE_FREE) & 0x00ff; ++ info->fq_drop_cnt = MHal_NOE_Read_Reg(FE_DROP_FQ); ++ info->fc_drop_cnt = MHal_NOE_Read_Reg(FE_DROP_FC); ++ info->ppe_drop_cnt = MHal_NOE_Read_Reg(FE_DROP_PPE); ++} ++ ++static void _MHal_NOE_PDMA_Get_Dbg(void *dbg_info) ++{ ++ struct noe_pdma_dbg *info = (struct noe_pdma_dbg *)dbg_info; ++ info->rx[0] = MHal_NOE_Read_Reg(INT_MASK + 0x10); ++ info->rx[1] = MHal_NOE_Read_Reg(INT_MASK + 0x14); ++ info->tx[0] = MHal_NOE_Read_Reg(INT_MASK + 0x8); ++ info->tx[1] = MHal_NOE_Read_Reg(INT_MASK + 0xC); ++} ++ ++ ++static void _MHal_NOE_QDMA_Get_Cnt(void *cnt_info) ++{ ++ struct noe_qdma_cnt *info = (struct noe_qdma_cnt *) cnt_info; ++ unsigned int page_no = 0, queue_no = 0; ++ if (queue_no >= NUM_PQ) ++ return; ++ ++ page_no = info->pq_no / QUEUE_OFFSET; ++ queue_no = info->pq_no & (QUEUE_OFFSET - 1); ++ ++ MHal_NOE_Write_Reg(QTX_MIB_IF, 0x90000000); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page_no); ++ info->pkt_cnt = MHal_NOE_Read_Reg(QTX_CFG_0 + queue_no * QUEUE_OFFSET); ++ info->drop_cnt = MHal_NOE_Read_Reg(QTX_SCH_0 + queue_no * QUEUE_OFFSET); ++ ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ MHal_NOE_Write_Reg(QTX_MIB_IF, 0x0); ++} ++ ++static void _MHal_NOE_QDMA_Get_Fq(void *fq_info) ++{ ++ struct noe_qdma_fq *info = (struct noe_qdma_fq *) fq_info; ++ info->sw_fq = (MHal_NOE_Read_Reg(QDMA_FQ_CNT) & 0xFFFF0000) >> 16; ++ info->hw_fq = MHal_NOE_Read_Reg(QDMA_FQ_CNT) & 0x0000FFFF; ++} ++ ++static void _MHal_NOE_QDMA_Get_Sch(void *rate_info) ++{ ++ struct noe_qdma_sch *info = (struct noe_qdma_sch *) rate_info; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_TX_SCH); ++ unsigned int max_rate, i; ++ info->sch[0].max_en = (temp & 0x00000800) >> 11; ++ max_rate = (temp & 0x000007F0) >> 4; ++ for (i = 0; i < (temp & 0x0000000F); i++) ++ max_rate *= 10; ++ info->sch[0].max_rate = max_rate; ++ ++ info->sch[1].max_en = (temp & 0x08000000) >> 27; ++ max_rate = (temp & 0x07F00000) >> 20; ++ for (i = 0; i < (temp & 0x000F0000); i++) ++ max_rate *= 10; ++ info->sch[1].max_rate = max_rate; ++} ++ ++static void _MHal_NOE_QDMA_Get_Fc(void *fc_info) ++{ ++ struct noe_qdma_fc *info = (struct noe_qdma_fc *) fc_info; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_FC_THRES); ++ info->sw.en = (temp & 0x1000000) >> 24; ++ info->sw.ffa = (temp & 0x2000000) >> 25; ++ info->sw.mode = (temp & 0x30000000) >> 28; ++ info->sw.fst_vq_en = (temp & 0x08000000) >> 27; ++ info->sw.fst_vq_mode = (temp & 0xC0000000) >> 30; ++ info->hw.en = (temp & 0x10000) >> 16; ++ info->hw.ffa = (temp & 0x20000) >> 17; ++ info->hw.mode = (temp & 0x300000) >> 20; ++ info->hw.fst_vq_en = (temp & 0x080000) >> 19; ++ info->hw.fst_vq_mode = (temp & 0xC00000) >> 22; ++} ++ ++static void _MHal_NOE_QDMA_Get_Fsm(void *fsm_info) ++{ ++ struct noe_qdma_fsm *info = (struct noe_qdma_fsm *) fsm_info; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_DMA); ++ info->vqtb = (temp & 0x0F000000) >> 24; ++ info->fq = (temp & 0x000F0000) >> 16; ++ info->tx = (temp & 0x00000F00) >> 8; ++ info->rx = temp & 0x0000001F; ++ temp = MHal_NOE_Read_Reg(QDMA_BMU); ++ info->rls = (temp & 0x07FF0000) >> 16; ++ info->fwd = temp & 0x00007FFF; ++} ++ ++static void _MHal_NOE_QDMA_Get_Vq(void *vq_info) ++{ ++ struct noe_qdma_vq *info = (struct noe_qdma_vq *) vq_info; ++ unsigned int temp = MHal_NOE_Read_Reg(VQTX_NUM); ++ info->vq_num[E_NOE_VQ_NO0]=temp & 0xF; ++ info->vq_num[E_NOE_VQ_NO1]=(temp & 0xF0) >> 4; ++ info->vq_num[E_NOE_VQ_NO2]=(temp & 0xF00) >> 8; ++ info->vq_num[E_NOE_VQ_NO3]=(temp & 0xF000) >> 12; ++} ++ ++static void _MHal_NOE_QDMA_Get_Pq(void *pq_info) ++{ ++ struct noe_qdma_pq *info = (struct noe_qdma_pq *) pq_info; ++ unsigned int temp, i, rate, queue, queue_no; ++ queue = info->queue; ++ queue_no = queue % 16; ++ ++ if (queue < 16) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ } ++ else if (queue > 15 && queue <= 31) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 1); ++ } ++ else if (queue > 31 && queue <= 47) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 2); ++ } ++ else if (queue > 47 && queue <= 63) { ++ MHal_NOE_Write_Reg(QDMA_PAGE, 3); ++ } ++ ++ ++ ++ temp = MHal_NOE_Read_Reg(QTX_CFG_0 + QUEUE_OFFSET * queue_no); ++ info->txd_cnt = (temp & 0xffff0000) >> 16; ++ info->hw_resv = (temp & 0xff00) >> 8; ++ info->sw_resv = (temp & 0xff); ++ temp = MHal_NOE_Read_Reg(QTX_CFG_0 + (QUEUE_OFFSET * queue_no) + 0x4); ++ info->sch = (temp >> 31) + 1; ++ info->min_en = (temp & 0x8000000) >> 27; ++ rate = (temp & 0x7f00000) >> 20; ++ for (i = 0; i < (temp & 0xf0000) >> 16; i++) ++ rate *= 10; ++ info->min_rate = rate; ++ info->max_en = (temp & 0x800) >> 11; ++ rate = (temp & 0x7f0) >> 4; ++ for (i = 0; i < (temp & 0xf); i++) ++ rate *= 10; ++ info->max_rate = rate; ++ info->weight = (temp & 0xf000) >> 12; ++ info->queue_head = MHal_NOE_Read_Reg(QTX_HEAD_0 + QUEUE_OFFSET * queue_no); ++ info->queue_tail = MHal_NOE_Read_Reg(QTX_TAIL_0 + QUEUE_OFFSET * queue_no); ++ ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++} ++ ++void MHal_NOE_Get_Qdma_Info(EN_NOE_QDMA_INFO_TYPE type, void *info) ++{ ++ if ((info == NULL) || (type >= E_NOE_QDMA_INFO_MAX) || (_mhal_noe_qdma_get_info_pfn[type] == NULL)) ++ return; ++ _mhal_noe_qdma_get_info_pfn[type](info); ++} ++ ++ ++void MHal_NOE_IO_Enable_Coherence(MS_BOOL qos) ++{ ++ MS_U32 reg_val = MHal_NOE_Read_Reg(REG_NOE_IOC_ETH); ++ ++ reg_val |= IOC_ETH_PDMA; ++ if (qos) { ++ reg_val |= IOC_ETH_QDMA; ++ } ++ MHal_NOE_Write_Reg(REG_NOE_IOC_ETH, reg_val); ++} ++ ++ ++ ++void MHal_NOE_Enable_Link_Intr(void) ++{ ++ MS_U32 val; ++ ++ if (NOE_IS_INVALID_MUX(noe_config.pin_mux)) { ++ MHAL_NOE_WARN_INFO("Invalid mux = %d.\n", noe_config.pin_mux); ++ return ; ++ } ++ ++ val = MHal_NOE_Read_Reg(FE_INT_ENABLE2); ++ if (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP) ++ val |= (0x1 << 24); ++ else if (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP) ++ val |= (0x1 << 25); ++ else ++ val |= (0x3 << 24) ; ++ ++ MHal_NOE_Write_Reg(FE_INT_ENABLE2, val); ++} ++ ++void MHal_NOE_Clear_Link_Intr_Status(void) ++{ ++ u32 val = MHal_NOE_Read_Reg(FE_INT_STATUS2) & (MAC1_LINK | MAC2_LINK); ++ MHal_NOE_Write_Reg(FE_INT_STATUS2, val ); ++} ++ ++MS_BOOL MHal_NOE_Get_Link_Intr_Status(void) ++{ ++ int val = 0; ++ MS_BOOL link_changed = FALSE; ++ val = MHal_NOE_Read_Reg(FE_INT_STATUS2); ++ if ((val & MAC2_LINK) || (val & MAC1_LINK)) { ++ link_changed = TRUE; ++ } ++ MHal_NOE_Clear_Link_Intr_Status(); ++ return link_changed; ++} ++ ++void MHal_NOE_Disable_Link_Intr(void) ++{ ++ MS_U32 mask = 0; ++ ++ if (NOE_IS_INVALID_MUX(noe_config.pin_mux)) { ++ MHAL_NOE_WARN_INFO("Invalid mux = %d.\n", noe_config.pin_mux); ++ return ; ++ } ++ ++ mask = MHal_NOE_Read_Reg(FE_INT_ENABLE2); ++ if (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP) ++ mask &= ~(MAC1_LINK); ++ else if (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP) ++ mask &= ~(MAC2_LINK); ++ else ++ mask &= ~(MAC1_LINK | MAC2_LINK) ; ++ ++ MHal_NOE_Write_Reg(FE_INT_ENABLE2, mask); ++ ++} ++ ++ ++void MHal_NOE_DMA_Update_Calc_Idx(EN_NOE_DIR dir, MS_U32 owner_idx) ++{ ++ if (dir == E_NOE_DIR_RX) ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_RX_CALC_IDX0, owner_idx); ++ else if (dir == E_NOE_DIR_TX) ++ MHal_NOE_Write_Reg(TX_CTX_IDX0, owner_idx); ++} ++ ++MS_U32 MHal_NOE_DMA_Get_Calc_Idx(EN_NOE_DIR dir) ++{ ++ if (dir == E_NOE_DIR_RX) ++ return MHal_NOE_Read_Reg(CONFIG_NOE_REG_RX_CALC_IDX0); ++ else if (dir == E_NOE_DIR_TX) ++ return MHal_NOE_Read_Reg(TX_CTX_IDX0); ++ return NOE_INVALID_CALC_IDX; ++} ++ ++ ++void MHal_NOE_Get_Intr_Status(EN_NOE_DMA dma, MS_U32 *recv, MS_U32 *xmit) ++{ ++ MS_U32 reg_int_val; ++ noe_config.intr_info.reg_int_val_q = 0; ++ noe_config.intr_info.reg_int_val_p = MHal_NOE_Read_Reg(CONFIG_NOE_REG_FE_INT_STATUS); ++ if (dma & E_NOE_DMA_QUEUE) { ++ noe_config.intr_info.reg_int_val_q = MHal_NOE_Read_Reg(QFE_INT_STATUS); ++ } ++ reg_int_val = noe_config.intr_info.reg_int_val_p | noe_config.intr_info.reg_int_val_q; ++ if ((reg_int_val & noe_config.intr_info.rx_mask)) ++ *recv = 1; ++ if (reg_int_val & noe_config.intr_info.tx_mask) ++ *xmit = 1; ++ ++} ++ ++void MHal_NOE_Clear_Intr_Status(EN_NOE_DMA dma) ++{ ++ /* Clear Interrupt */ ++ if (dma & E_NOE_DMA_QUEUE) { ++ MHal_NOE_Write_Reg(QFE_INT_STATUS, noe_config.intr_info.reg_int_val_q); ++ } ++ /* QWERT */ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_STATUS, noe_config.intr_info.reg_int_val_p); ++} ++ ++ ++void MHal_NOE_Enable_Intr_Status(EN_NOE_DMA dma) ++{ ++ MS_U32 reg_int_mask; ++ reg_int_mask = MHal_NOE_Read_Reg(CONFIG_NOE_REG_FE_INT_ENABLE); ++ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, reg_int_mask & ~(noe_config.intr_info.rx_mask)); ++ ++ if (dma & E_NOE_DMA_QUEUE) { ++ reg_int_mask = MHal_NOE_Read_Reg(QFE_INT_ENABLE); ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_int_mask & ~(noe_config.intr_info.rx_mask)); ++ } ++ ++} ++ ++void MHal_NOE_MAC_Get_Link_Status(EN_NOE_GE_MAC ge, struct noe_mac_link_status *link_status) ++{ ++ u32 data = 0; ++ if (NOE_AUTO_POLLING_IS_NOT_SUPPORTED()) { ++ if ((ge == E_NOE_GE_MAC1) || (ge == E_NOE_GE_MAC2)) { ++ if (noe_config.mii_info[ge].phy_addr != NOE_INVALID_PHY_ADDR) { ++ MHal_NOE_Read_Mii_Mgr(noe_config.mii_info[ge].phy_addr, GPHY_REG_STATUS, &data); ++ /* ++ the register indicates whether the link was lost since the last read. ++ for the current link status, read this register twice. ++ */ ++ MHal_NOE_Read_Mii_Mgr(noe_config.mii_info[ge].phy_addr, GPHY_REG_STATUS, &data); ++ link_status->link_up = ((data & BIT(2)) == BIT(2))? TRUE: FALSE; ++ } ++ } ++ } ++ else { ++ if (ge == E_NOE_GE_MAC1) { ++ link_status->link_up = (MHal_NOE_Read_Reg(NOE_MAC_P1_SR) & 0x1)?TRUE:FALSE; ++ } ++ else if (ge == E_NOE_GE_MAC2) { ++ link_status->link_up = (MHal_NOE_Read_Reg(NOE_MAC_P2_SR) & 0x1)?TRUE:FALSE; ++ } ++ } ++} ++ ++EN_NOE_RET MHal_NOE_Need_Reset(void) ++{ ++ unsigned int val_1, val_2, info; ++ unsigned int tmp[4]; ++ val_1 = MHal_NOE_Read_Reg(NOE_REG_SYSCTL_BASE); ++ val_2 = MHal_NOE_Read_Reg(NOE_REG_SYSCTL_BASE + 4); ++ tmp[3] = ((val_1 >> 16) & 0xff) - 0x30; ++ tmp[2] = ((val_1 >> 24) & 0xff) - 0x30; ++ tmp[1] = ((val_2 >> 0) & 0xff) - 0x30; ++ tmp[0] = ((val_2 >> 8) & 0xff) - 0x30; ++ info = (tmp[3] * 1000) + (tmp[2] * 100) + (tmp[1] * 10) + tmp[0]; ++ /* reset is not necessary */ ++ return E_NOE_RET_FALSE; ++} ++ ++static void _MHal_NOE_FE_Reset(void) ++{ ++ MS_U32 adma_rx_dbg0_r = 0; ++ MS_U32 dbg_rx_curr_state, rx_fifo_wcnt; ++ MS_U32 dbg_cdm_lro_rinf_afifo_rempty, dbg_cdm_eof_rdy_afifo_empty; ++ MS_U32 reg_tmp, loop_count; ++ ++ /* do CDM/PDMA reset */ ++ reg_tmp = MHal_NOE_Read_Reg(FE_GLO_MISC); ++ MHal_NOE_Write_Reg(FE_GLO_MISC, reg_tmp | reg_tmp); ++ mdelay(10); ++ reg_tmp = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW3); ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW3, reg_tmp | (0x1 << 14)); ++ loop_count = 0; ++ do { ++ adma_rx_dbg0_r = MHal_NOE_Read_Reg(ADMA_RX_DBG0); ++ dbg_rx_curr_state = (adma_rx_dbg0_r >> 16) & 0x7f; ++ rx_fifo_wcnt = (adma_rx_dbg0_r >> 8) & 0x3f; ++ dbg_cdm_lro_rinf_afifo_rempty = (adma_rx_dbg0_r >> 7) & 0x1; ++ dbg_cdm_eof_rdy_afifo_empty = (adma_rx_dbg0_r >> 6) & 0x1; ++ loop_count++; ++ if (loop_count >= 100) { ++ MHAL_NOE_DBG_INFO("[%s] loop_count timeout!!!\n", __func__); ++ break; ++ } ++ mdelay(10); ++ } while (((dbg_rx_curr_state != 0x17) && (dbg_rx_curr_state != 0x00)) || (rx_fifo_wcnt != 0) || (!dbg_cdm_lro_rinf_afifo_rempty) || (!dbg_cdm_eof_rdy_afifo_empty)); ++ reg_tmp = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW3); ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW3, reg_tmp & 0xffffbfff); ++ reg_tmp = MHal_NOE_Read_Reg(FE_GLO_MISC); ++ MHal_NOE_Write_Reg(FE_GLO_MISC, reg_tmp & 0xfffffffe); ++ ++} ++ ++void MHal_NOE_Do_Reset(void) ++{ ++ ++ MS_U32 adma_rx_dbg0_r = 0; ++ MS_U32 dbg_rx_curr_state, rx_fifo_wcnt; ++ MS_U32 dbg_cdm_lro_rinf_afifo_rempty, dbg_cdm_eof_rdy_afifo_empty; ++ ++ adma_rx_dbg0_r = MHal_NOE_Read_Reg(ADMA_RX_DBG0); ++ dbg_rx_curr_state = (adma_rx_dbg0_r >> 16) & 0x7f; ++ rx_fifo_wcnt = (adma_rx_dbg0_r >> 8) & 0x3f; ++ dbg_cdm_lro_rinf_afifo_rempty = (adma_rx_dbg0_r >> 7) & 0x1; ++ dbg_cdm_eof_rdy_afifo_empty = (adma_rx_dbg0_r >> 6) & 0x1; ++ ++ /* check if PSE P0 hang */ ++ if (dbg_cdm_lro_rinf_afifo_rempty && dbg_cdm_eof_rdy_afifo_empty && (rx_fifo_wcnt & 0x20) && ((dbg_rx_curr_state == 0x17) || (dbg_rx_curr_state == 0x00))) { ++ _MHal_NOE_FE_Reset(); ++ } ++} ++ ++ ++void MHal_NOE_DMA_SFQ_Init(struct noe_sfq_base *adr_info) ++{ ++ MS_U32 reg_val; ++ reg_val = MHal_NOE_Read_Reg(VQTX_GLO); ++ reg_val = reg_val | VQTX_MIB_EN; ++ /* Virtual table extends to 32bytes */ ++ MHal_NOE_Write_Reg(VQTX_GLO, reg_val); ++ reg_val = MHal_NOE_Read_Reg(VQTX_GLO); ++ MHal_NOE_Write_Reg(VQTX_NUM, (VQTX_NUM_0) | (VQTX_NUM_1) | (VQTX_NUM_2) | (VQTX_NUM_3) | (VQTX_NUM_4) | (VQTX_NUM_5) | (VQTX_NUM_6) | (VQTX_NUM_7)); ++ ++ /* 10 s change hash algorithm */ ++ MHal_NOE_Write_Reg(VQTX_HASH_CFG, 0xF002710); ++ MHal_NOE_Write_Reg(VQTX_VLD_CFG, 0xeca86420); ++ MHal_NOE_Write_Reg(VQTX_HASH_SD, 0x0D); ++ MHal_NOE_Write_Reg(QDMA_FC_THRES, 0x9b9b4444); ++ MHal_NOE_Write_Reg(QDMA_HRED1, 0); ++ MHal_NOE_Write_Reg(QDMA_HRED2, 0); ++ MHal_NOE_Write_Reg(QDMA_SRED1, 0); ++ MHal_NOE_Write_Reg(QDMA_SRED2, 0); ++ MHal_NOE_Write_Reg(VQTX_0_3_BIND_QID, (VQTX_0_BIND_QID) | (VQTX_1_BIND_QID) | (VQTX_2_BIND_QID) | (VQTX_3_BIND_QID)); ++ MHal_NOE_Write_Reg(VQTX_4_7_BIND_QID, (VQTX_4_BIND_QID) | (VQTX_5_BIND_QID) | (VQTX_6_BIND_QID) | (VQTX_7_BIND_QID)); ++ MHAL_NOE_DBG_INFO("VQTX_0_3_BIND_QID =%x\n", MHal_NOE_Read_Reg(VQTX_0_3_BIND_QID)); ++ MHAL_NOE_DBG_INFO("VQTX_4_7_BIND_QID =%x\n", MHal_NOE_Read_Reg(VQTX_4_7_BIND_QID)); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE0, (MS_U32)adr_info->phy_adr[0]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE1, (MS_U32)adr_info->phy_adr[1]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE2, (MS_U32)adr_info->phy_adr[2]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE3, (MS_U32)adr_info->phy_adr[3]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE4, (MS_U32)adr_info->phy_adr[4]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE5, (MS_U32)adr_info->phy_adr[5]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE6, (MS_U32)adr_info->phy_adr[6]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE7, (MS_U32)adr_info->phy_adr[7]); ++} ++ ++MS_U32 MHal_NOE_DMA_Get_Queue_Cfg(MS_U32 pq_no) ++{ ++ int page_no = 0, queue_no = 0; ++ ++ if (noe_config.bQoS_SetMode == TRUE) { ++ return NOE_QOS_SET_REG(pq_no); ++ } ++ else { ++ if (pq_no >= NUM_PQ) ++ return 0; ++ ++ page_no = pq_no / QUEUE_OFFSET; ++ queue_no = pq_no & (QUEUE_OFFSET - 1); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page_no); ++ return MHal_NOE_Read_Reg(QTX_CFG_0 + queue_no * QUEUE_OFFSET); ++ } ++} ++ ++void MHal_NOE_DMA_Set_Queue_Cfg(MS_U32 pq_no, MS_U32 cfg) ++{ ++ int page = 0, queue = 0; ++ ++ if (noe_config.bQoS_SetMode == TRUE) { ++ NOE_QOS_SET_REG(pq_no) = cfg; ++ MHAL_NOE_DBG_INFO(" 0x%x = 0x%x\n", QDMA_RELATED + pq_no, cfg); ++ } ++ else { ++ if (pq_no >= NUM_PQ) ++ return ; ++ ++ page = pq_no / QUEUE_OFFSET; ++ queue = pq_no & (QUEUE_OFFSET - 1); ++ MHAL_NOE_DBG_INFO("page: 0x%x, queue = 0x%x\n", page, queue); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page); ++ MHal_NOE_Write_Reg(QTX_CFG_0 + QUEUE_OFFSET * queue, cfg); ++ } ++} ++ ++ ++void MHal_NOE_DMA_Enable_Specific_Intr(EN_NOE_DMA dma, EN_NOE_INTR_INFO e_intr) ++{ ++ MS_U32 reg_val; ++ if (dma & E_NOE_DMA_QUEUE) { ++ reg_val = MHal_NOE_Read_Reg(QFE_INT_ENABLE); ++ if (e_intr == E_NOE_INTR_INFO_RLS_DLY) { ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_val | RLS_DLY_INT); ++ } ++ else { ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_val | RLS_DONE_INT); ++ } ++ } ++} ++ ++ ++void MHal_NOE_DMA_FQ_Init(struct noe_fq_base *info) ++{ ++ MHal_NOE_Write_Reg(QDMA_FQ_HEAD, (MS_U32) info->head); ++ MHal_NOE_Write_Reg(QDMA_FQ_TAIL, (MS_U32) info->tail); ++ MHal_NOE_Write_Reg(QDMA_FQ_CNT, ((info->txd_num << 16) | info->page_num)); ++ MHal_NOE_Write_Reg(QDMA_FQ_BLEN, info->page_size << 16); ++} ++ ++MS_U32 MHal_NOE_QDMA_Get_Tx(void) ++{ ++ return MHal_NOE_Read_Reg(QTX_DRX_PTR); ++} ++ ++void MHal_NOE_QDMA_Update_Tx(EN_NOE_QDMA_TX_TYPE type, MS_U32 adr) ++{ ++ if (type == E_NOE_QDMA_TX_FORWARD) ++ MHal_NOE_Write_Reg(QTX_CTX_PTR, adr); ++ else if (type == E_NOE_QMDA_TX_RELEASE) ++ MHal_NOE_Write_Reg(QTX_CRX_PTR, adr); ++} ++ ++void MHal_NOE_LRO_Control(EN_NOE_LRO_CTRL_TYPE type, MS_U32 param) ++{ ++ if (type == E_NOE_LRO_CTRL_AGG_CNT) { ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, param); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, param); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, param); ++ } ++ else if (type == E_NOE_LRO_CTRL_AGG_TIME) { ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, param); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, param); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, param); ++ } ++ else if (type == E_NOE_LRO_CTRL_AGE_TIME) { ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, param); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, param); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, param); ++ } ++ else if (type == E_NOE_LRO_CTRL_BW_THRESHOLD) { ++ SET_PDMA_LRO_BW_THRESHOLD(param); ++ } ++ else if (type == E_NOE_LRO_CTRL_SWITCH) { ++ if (param == NOE_DISABLE) { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0); ++ } ++ else { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ } ++ } ++} ++ ++ ++void MHal_NOE_Get_Pdma_Info(EN_NOE_PDMA_INFO_TYPE type, void *info) ++{ ++ if ((type >= E_NOE_PDMA_INFO_MAX) || (_mhal_noe_pdma_get_info_pfn[type] == NULL)) ++ return; ++ _mhal_noe_pdma_get_info_pfn[type](info); ++} ++ ++void _MHal_NOE_Disable_WED_Interrupt(void) ++{ ++ /* only enable FE[0] interrupt for NOE */ ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x1D << 1) = 0xFF1F; ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x1E << 1) = 0xFFFF; ++ ++ /* only enable FE[1] interrupt for NOE */ ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x33 << 1) = 0xFF1F; ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x34 << 1) = 0xFFFF; ++ ++ /* nly enable FE[2] interrupt for NOE */ ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x27 << 1) |= 0xFFFF; ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x28 << 1) |= 0xFFFF; ++} ++ ++void MHal_NOE_Init(struct noe_sys *info) ++{ ++ ethdma_sysctl_base = info->sysctl_base; ++ _MHal_NOE_Init_Clock(); ++ _MHal_NOE_Disable_WED_Interrupt(); ++ /* GMAC1/2 RGMII mode First */ ++ _MHal_NOE_Set_Interface_Mode(E_NOE_GE_MAC1, E_NOE_INTERFACE_RGMII_MODE); ++ _MHal_NOE_Set_Interface_Mode(E_NOE_GE_MAC2, E_NOE_INTERFACE_RGMII_MODE); ++ ++ noe_config.bAN_Supported = 1; ++ ++} ++ ++void MHAL_NOE_Get_Interrupt(struct noe_irq *info) ++{ ++ info->num = 2; ++ info->irq[E_NOE_IRQ_0] = INT_IRQ_115_NOE_IRQ0; ++ info->irq[E_NOE_IRQ_1] = INT_IRQ_116_NOE_IRQ1; ++ info->irq[E_NOE_IRQ_2] = INT_IRQ_117_NOE_IRQ2; ++} ++ ++void MHAL_NOE_LRO_Get_Control(EN_NOE_RING ring, struct lro_ctrl *info) ++{ ++ MS_U32 reg1, reg2, reg3; ++ ++ if ((ring >=E_NOE_RING_MAX) || (info == NULL)) { ++ return; ++ } ++ ++ reg1 = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW1 + (ring * 0x40)); ++ reg2 = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW2 + (ring * 0x40)); ++ reg3 = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW3 + (ring * 0x40)); ++ ++ ++ info->agg_cnt = ((reg3 & 0x03) << PDMA_LRO_AGG_CNT_H_OFFSET) | ((reg2 >> PDMA_LRO_RING_AGG_CNT1_OFFSET) & 0x3f); ++ info->agg_time = (reg2 >> PDMA_LRO_RING_AGG_OFFSET) & 0xffff; ++ info->age_time = ((reg2 & 0x03f) << PDMA_LRO_AGE_H_OFFSET) | ((reg1 >> PDMA_LRO_RING_AGE1_OFFSET) & 0x3ff); ++ info->threshold = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW2); ++} ++ ++ ++void MHAL_NOE_LRO_Get_Table(MS_U32 entry, struct lro_tbl *info) ++{ ++ int i = 0; ++ MS_U32 reg_val; ++ ++ if (entry >= MHAL_NOE_MAX_ENTRIES_IN_LRO_TABLE) { ++ info->valid = FALSE; ++ return; ++ } ++ ++ MHal_NOE_Write_Reg(PDMA_FE_ALT_CF8, 0); ++ reg_val = MHal_NOE_Read_Reg(PDMA_FE_ALT_SEQ_CFC); ++ ++ info->valid = (reg_val & (1 << entry))?TRUE:FALSE; ++ ++ if (entry > 4) ++ entry = entry - 1; ++ entry = (entry * 9) + 1; ++ ++ /* read valid entries of the auto-learn table */ ++ MHal_NOE_Write_Reg(PDMA_FE_ALT_CF8, entry); ++ ++ for (i = 0; i < MHAL_NOE_MAX_INFO_FOR_EACH_ENTRY_IN_LRO_TABLE; i++) { ++ info->tlb_info[i] = MHal_NOE_Read_Reg(PDMA_FE_ALT_SEQ_CFC); ++ } ++ ++ if (MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0) & PDMA_LRO_ALT_SCORE_MODE) ++ info->priority = info->tlb_info[6] >> 20; /* packet count */ ++ else ++ info->priority = info->tlb_info[7]; /* byte count */ ++} ++ ++void MHal_NOE_Set_Intr_Mask(EN_NOE_DELAY e_dly) ++{ ++ if (e_dly != E_NOE_DLY_DISABLE) { ++ noe_config.intr_info.tx_mask = RLS_DLY_INT; ++ noe_config.intr_info.rx_mask = RX_DLY_INT; ++ } ++ else { ++ noe_config.intr_info.tx_mask = TX_DONE_INT0; ++ noe_config.intr_info.rx_mask = RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3; ++ } ++} ++ ++ ++void MHal_NOE_Set_WoL(MS_BOOL enable) ++{ ++ unsigned int reg_value = 0; ++ ++ if (enable) { ++ reg_value = MHal_NOE_Read_Reg(MAC1_WOL); ++ reg_value |= (WOL_INT_CLR | WOL_INT_EN | WOL_EN); ++ MHal_NOE_Write_Reg(MAC1_WOL, reg_value); ++ ++ } ++ else { ++ reg_value = MHal_NOE_Read_Reg(MAC1_WOL); ++ reg_value &= ~(WOL_INT_EN | WOL_EN); ++ MHal_NOE_Write_Reg(MAC1_WOL, reg_value); ++ } ++ ++} ++ ++void MHal_NOE_Dma_DeInit_Global_Config(EN_NOE_DMA dma) ++{ ++ if (E_NOE_DMA_PACKET == dma) { ++ MHal_NOE_Write_Reg(PDMA_GLO_CFG, 0); ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, 0); ++ } ++ ++ noe_config.status = E_NOE_HAL_STATUS_SUSPEND; ++} +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_noe.c.an b/drivers/sstar/noe/hal/infinity2/mhal_noe.c.an +new file mode 100755 +index 000000000000..378fd2f13f1b +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_noe.c.an +@@ -0,0 +1,3577 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_noe.c ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++#include "mdrv_types.h" ++#include "mst_platform.h" ++#include "mdrv_system.h" ++//#include "chip_int.h" ++#include "mstar/mstar_chip.h" ++#include "mhal_noe_reg.h" ++#include "mhal_noe.h" ++#include "mhal_noe_lro.h" ++ ++ ++#define NEW_GPHY 1 ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum { ++ E_MHAL_NOE_DELAY_NS_0, ++ E_MHAL_NOE_DELAY_NS_2, ++}EN_MHAL_NOE_DELAY_TIME; ++ ++struct _mhal_mii_info{ ++ unsigned char noe_mii_force_mode; ++ u32 phy_addr; ++ EN_NOE_SPEED speed; ++ EN_NOE_DUPLEX duplex; ++}; ++ ++struct _mhal_intr_info { ++ void __iomem *fe_tx_int_status; ++ void __iomem *fe_tx_int_enable; ++ void __iomem *fe_rx_int_status; ++ void __iomem *fe_rx_int_enable; ++ MS_U32 reg_int_val_p; ++ MS_U32 reg_int_val_q; ++}; ++ ++struct _mhal_noe_config{ ++ struct _mhal_mii_info mii_info[E_NOE_GE_MAC_MAX]; ++ EN_NOE_HAL_LOG noe_dbg_enable; ++ struct _mhal_intr_info intr_info; ++ EN_NOE_SEL noe_internal_phy_enable; ++ MS_BOOL mdio_n; ++ EN_NOE_SEL_PIN_MUX pin_mux; ++ MS_U16 version; ++ EN_MHAL_NOE_DELAY_TIME delay; ++}; ++ ++ ++typedef void (*_MHAL_DMA_GET_INFO) (void *); ++typedef void (*_MHAL_PINMUX_SEL) (void ); ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define NOE_WAIT_IDLE_THRESHOLD (1000) ++ ++ ++#define MHAL_NOE_DBG_INFO(fmt, args...) \ ++{\ ++ if (noe_config.noe_dbg_enable & E_NOE_HAL_LOG_DBG)\ ++ printk(fmt, ##args);\ ++} ++ ++#define MHAL_NOE_INTR_INFO(fmt, args...) \ ++{\ ++ if (noe_config.noe_dbg_enable & E_NOE_HAL_LOG_INTR)\ ++ printk(fmt, ##args);\ ++} ++//-------------------------------------------------------------------------------------------------- ++// Local Functions ++//-------------------------------------------------------------------------------------------------- ++static void _MHal_NOE_PDMA_Get_Dbg(void *dbg_info); ++static void _MHal_NOE_QDMA_Get_Cnt(void *cnt_info); ++static void _MHal_NOE_QDMA_Get_Fq(void *fq_info); ++static void _MHal_NOE_QDMA_Get_Sch(void *rate_info); ++static void _MHal_NOE_QDMA_Get_Fc(void *fc_info); ++static void _MHal_NOE_QDMA_Get_Fsm(void *fsm_info); ++static void _MHal_NOE_QDMA_Get_Vq(void *vq_info); ++static void _MHal_NOE_QDMA_Get_Pq(void *pq_info); ++static void _MHal_NOE_GE1ToGPHY_GE2ToPM(void); ++static void _MHal_NOE_GE1ToPM_GE2ToCHIPTOP(void); ++static void _MHal_NOE_GE1ToGPHY_GE2ToCHIPTOP(void); ++static void _MHal_NOE_GE1ToGPHY(void); ++static void _MHal_NOE_GE1ToPM(void); ++static void _MHal_NOE_GE2ToPM(void); ++static void _MHal_NOE_GE2ToCHIPTOP(void); ++static void _MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable); ++ ++//-------------------------------------------------------------------------------------------------- ++// Variable ++//-------------------------------------------------------------------------------------------------- ++ ++void __iomem *ethdma_sysctl_base; ++EXPORT_SYMBOL(ethdma_sysctl_base); ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Local Variable ++//-------------------------------------------------------------------------------------------------- ++ ++static _MHAL_DMA_GET_INFO _mhal_noe_qdma_get_info_pfn[E_NOE_QDMA_INFO_MAX] = { ++ [E_NOE_QDMA_INFO_CNT] = _MHal_NOE_QDMA_Get_Cnt, ++ [E_NOE_QDMA_INFO_FQ] = _MHal_NOE_QDMA_Get_Fq, ++ [E_NOE_QDMA_INFO_SCH] = _MHal_NOE_QDMA_Get_Sch, ++ [E_NOE_QDMA_INFO_FC] = _MHal_NOE_QDMA_Get_Fc, ++ [E_NOE_QDMA_INFO_FSM] = _MHal_NOE_QDMA_Get_Fsm, ++ [E_NOE_QDMA_INFO_VQ] = _MHal_NOE_QDMA_Get_Vq, ++ [E_NOE_QDMA_INFO_PQ] = _MHal_NOE_QDMA_Get_Pq, ++}; ++ ++static _MHAL_DMA_GET_INFO _mhal_noe_pdma_get_info_pfn[E_NOE_PDMA_INFO_MAX] = { ++ [E_NOE_PDMA_INFO_DBG] = _MHal_NOE_PDMA_Get_Dbg, ++}; ++ ++static _MHAL_PINMUX_SEL _mhal_noe_pinmux_pfn[E_NOE_SEL_PIN_MUX_MAX] = { ++ [E_NOE_SEL_PIN_MUX_GE1_TO_GPHY] = _MHal_NOE_GE1ToGPHY, ++ [E_NOE_SEL_PIN_MUX_GE1_TO_PM] = _MHal_NOE_GE1ToPM, ++ [E_NOE_SEL_PIN_MUX_GE2_TO_PM] = _MHal_NOE_GE2ToPM, ++ [E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP] = _MHal_NOE_GE2ToCHIPTOP, ++ [E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM] = _MHal_NOE_GE1ToGPHY_GE2ToPM, ++ [E_NOE_SEL_PIN_MUX_GE1_TO_PM_GE2_TO_CHIPTOP] = _MHal_NOE_GE1ToPM_GE2ToCHIPTOP, ++ [E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_CHIPTOP] = _MHal_NOE_GE1ToGPHY_GE2ToCHIPTOP, ++}; ++ ++static struct _mhal_noe_config noe_config = { ++ .mii_info = { ++ [E_NOE_GE_MAC1] = { ++ .noe_mii_force_mode = NOE_DISABLE, ++ .phy_addr = NOE_INVALID_PHY_ADDR, ++ .speed = E_NOE_SPEED_INVALID, ++ .duplex = E_NOE_DUPLEX_INVALID, ++ }, ++ [E_NOE_GE_MAC2] = { ++ .noe_mii_force_mode = NOE_DISABLE, ++ .phy_addr = NOE_INVALID_PHY_ADDR, ++ .speed = E_NOE_SPEED_INVALID, ++ .duplex = E_NOE_DUPLEX_INVALID, ++ }, ++ }, ++ .noe_dbg_enable = NOE_DISABLE, ++ .intr_info = { ++ .fe_tx_int_status = NULL, ++ .fe_tx_int_enable = NULL, ++ .fe_rx_int_status = NULL, ++ .fe_rx_int_enable = NULL, ++ }, ++#if CONFIG_NOE_MDIO_NEW_MODE ++ .mdio_n = 1, ++#else ++ .mdio_n = 0, ++#endif ++ .version = 0xFFFF, ++ .delay = E_MHAL_NOE_DELAY_NS_2, ++}; ++ ++static void _MHal_NOE_Init_Mdio(EN_NOE_SEL_PIN_MUX sel) ++{ ++ if (sel == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY) { ++ //NOE_RIU_REG(0x121E, 0x06 << 1) = NOE_RIU_REG(0x121F, 0x3C) | BIT(0); ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM) { ++ /* PAD_PM */ ++ //NOE_RIU_REG(0x121F, 0x1E << 1) = NOE_RIU_REG(0x121F, 0x1E << 1) | BIT(14); ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE1_TO_PM) { ++ ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE1_TO_PM_GE2_TO_CHIPTOP) { ++ //NOE_RIU_REG(0x121E, 0x06 << 1) = NOE_RIU_REG(0x121F, 0x3C) & (~BIT(0)); ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE2_TO_PM) { ++ ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM) { ++ ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP) { ++ ++ } ++ else if (sel == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_CHIPTOP) { ++ ++ } ++} ++ ++static void _MHal_NOE_Reset_SW(void) ++{ ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x00 << 1) = 0x0003; ++ udelay(1); ++ NOE_RIU_REG(NOE_RIU_BANK_NOE_MISC, 0x00 << 1) = 0x0000; ++} ++ ++static void _MHal_NOE_Init_Clock(void) ++{ ++ /* NOE */ ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x70 << 1) = 0x0404; ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x71 << 1) = 0x0000; ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x74 << 1) = 0x0000; ++ ++ /* WED */ ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x72 << 1) = 0x0004; ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x73 << 1) = 0x0004; ++ ++ /* Reset */ ++ _MHal_NOE_Reset_SW(); ++ ++ /* GMACPLL */ ++ MHal_NOE_Write8_Reg(NOE_RIU_BANK_CLKGEN0, (0x63 << 1), 0x00); ++ NOE_RIU_REG(NOE_RIU_BANK_ANA_MISC_GMAC, 0x68 << 1) = 0xBC4F; ++ NOE_RIU_REG(NOE_RIU_BANK_ANA_MISC_GMAC, 0x69 << 1) = 0x0014; ++ NOE_RIU_REG(NOE_RIU_BANK_ANA_MISC_GMAC, 0x63 << 1) = 0x0000; ++ udelay(50); ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_CLKGEN2, 0x01 << 1), 0xFF00, 0x0C00); ++ NOE_RIU_REG(NOE_RIU_BANK_CLKGEN1, 0x32 << 1) = 0x0000; ++} ++ ++ ++static void _MHal_NOE_GPHY_Set_Addr(MS_U8 addr) ++{ ++ MS_U16 regValue; ++ regValue = NOE_RIU_REG(0x0035, 0x68) & 0xFFF0; ++ NOE_RIU_REG(0x0035, 0x68) = regValue | addr; ++ MHAL_NOE_DBG_INFO("GPHY ADDR = 0x%x \n", NOE_RIU_REG(0x0035, 0x68)); ++} ++ ++ ++static inline void MHal_NOE_GPHY_Write45_Mii_Mgr(MS_U8 phy_addr, MS_U8 device, MS_U32 address, MS_U32 value) ++{ ++ u16 uVal; ++ u8 uRegVal; ++ ++ uVal = (GPHY_MDIO_START_CL45 << GPHY_MDIO_START_SHIFT) ++ | (GPHY_MDIO_OPCODE_CL45_ADDRESS << GPHY_MDIO_OPCODE_SHIFT) ++ | ((phy_addr & 0x1f) << GPHY_MDIO_PHY_ADDRESS_SHIFT) ++ | ((device & 0x1f) << GPHY_MDIO_REG_ADDRESS_SHIFT) ++ | GPHY_MDIO_TA; ++ ++ printk("[%s][%d] address = 0x%04x, uVal=0x%04x \n",__FUNCTION__,__LINE__,address, uVal); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03); ++ NOE_RIU_REG(0x0035, 0xf2) = address & 0xFFFF; ++ NOE_RIU_REG(0x0035, 0xf4) = uVal; ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01); ++ ++ udelay(200); ++ ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ ++ while(!(uRegVal & 0x80)) ++ { ++ printk("uRegVal = 0x%02x\n", uRegVal); ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ barrier (); ++ } ++ ++ uVal = (GPHY_MDIO_START_CL45 << GPHY_MDIO_START_SHIFT) ++ | (GPHY_MDIO_OPCODE_WRITE << GPHY_MDIO_OPCODE_SHIFT) ++ | ((phy_addr & 0x1f) << GPHY_MDIO_PHY_ADDRESS_SHIFT) ++ | ((device & 0x1f) << GPHY_MDIO_REG_ADDRESS_SHIFT) ++ | GPHY_MDIO_TA; ++ ++ printk("[%s][%d] value = 0x%04X, uVal=0x%04X \n",__FUNCTION__,__LINE__,value, uVal); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03); ++ NOE_RIU_REG(0x0035, 0xf2) = value & 0xFFFF; ++ NOE_RIU_REG(0x0035, 0xf4) = uVal; ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01); ++ ++ udelay(200); ++ ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ ++ while(!(uRegVal & 0x80)) ++ { ++ printk("uRegVal = 0x%02x\n", uRegVal); ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ barrier (); ++ } ++ ++} ++ ++ ++static inline void _MHal_NOE_GPHY_Set_Config(MS_U8 phy_addr) ++{ ++ ++ //// reg_led_mode = 2'b01 ++ MHal_NOE_Write8_Reg(0x000e, 0x50, 0x10);////wriu 0x00000e50 0x10 ++ MHal_NOE_Write8_Reg(0x000e, 0x51, 0x00);////wriu 0x00000e51 0x00 ++ ++ ////Set LED0 on control ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h024, 16'hc007); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0024, 0xc007); ++ udelay(200); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0024, 0xc007); ++ ++ ////Set LED3 on control ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h02a, 16'hc007); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x002a, 0xc007); ++ ++ ////Set LED3 Blinking ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h02b, 16'h003f); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x002b, 0x003f); ++ ++ //Set LED Basic control ++ //reg_mdio_cl45_write(addr, 16'h1f, 16'h021, 16'h800a); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0021, 0x800a); ++ ++#if 0 ++ ////By mode setting Start ++ ++ //// DA_AD_CORE_PWD_C TBT=1, HBT=1 ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h0e4, 16'h1101); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x00e4, 0x1101); ++ ++ //// DA_AD_CORE_PWD_D TBT=1, HBT=1 ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h0e5, 16'h1101); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x00e5, 0x1101); ++ ++ ////DA_TX_CM1_OP ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h26a, 16'h0440); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x026a, 0x0440); ++ ++ ////Set cr_da_tx_cm1_op_tsmode ++ ////Set cr_da_tx_rm1_op_tsmode ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h26b, 16'h0000); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x026b, 0x0000); ++ ++ ////Set cr_da_tx_cm1_op_gbe_slp ++ ////Set cr_da_tx_cm2_op_gbe_slp ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h302, 16'h0004); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0302, 0x0004); ++ ++ ////Set DA_TX_FILTER_CAP_A ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h023, 16'h0555); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0023, 0x0555); ++ ++ ////Set DA_TX_FILTER_CAP_B ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h024, 16'h0555); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0024, 0x0555); ++ ++ ////Set DA_TX_FILTER_CAP_C ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h025, 16'h0555); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0025, 0x0555); ++ ++ ////Set DA_TX_FILTER_CAP_D ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h026, 16'h0555); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0026, 0x0555); ++ ++ ////Set DA_TX_OVERSHOOT_EN ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h011, 16'h0f00); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0011, 0x0f00); ++ ++ ////Set CR_DA_TX_PS_DRIR0 ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h269, 16'h444f); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0269, 0x444f); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h268, 16'h03f4); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0268, 0x03f4); ++ ++ ////Set CR_DA_TX_PS_OP ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h272, 16'h35bf); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0272, 0x35bf); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h271, 16'h7e94); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x0271, 0x7e94); ++ ++ ////Set DA_TX_I2MPB_A ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h016, 16'h4010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0016, 0x4010); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h012, 16'h4010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0012, 0x4010); ++ ++ ////Set DA_TX_I2MPB_B ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h018, 16'h1010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0018, 0x1010); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h017, 16'h1010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0017, 0x1010); ++ ++ ////Set DA_TX_I2MPB_C ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h019, 16'h1010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0019, 0x1010); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h020, 16'h1010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0020, 0x1010); ++ ++ ////Set DA_TX_I2MPB_D ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h022, 16'h1010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0022, 0x1010); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h021, 16'h1010); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1e, 0x0021, 0x1010); ++ ++ ////Set CR_DA_TX_I2MPB_10M ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h27c, 16'h0000); ++ MHal_NOE_GPHY_Write45_Mii_Mgr(phy_addr, 0x1f, 0x027c, 0x0000); ++#endif ++} ++ ++void MHal_NOE_GPHY_Read_Mii_Mgr(unsigned char phy_addr, unsigned char address,u32 *value) ++{ ++ u32 uVal; ++ u8 uRegVal; ++ ++ uVal = (GPHY_MDIO_START_CL22 << GPHY_MDIO_START_SHIFT) ++ | (GPHY_MDIO_OPCODE_CL22_READ << GPHY_MDIO_OPCODE_SHIFT) ++ | ((phy_addr & 0x1f) << GPHY_MDIO_PHY_ADDRESS_SHIFT) ++ | ((address & 0x1f) << GPHY_MDIO_REG_ADDRESS_SHIFT) ++ | GPHY_MDIO_TA; ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03); ++ NOE_RIU_REG(0x0035, 0xf2) = 0x0; ++ NOE_RIU_REG(0x0035, 0xf4) = uVal; ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01); ++ ++ udelay(200); ++ ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ ++ while(!(uRegVal & 0x80)) ++ { ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ barrier (); ++ } ++ ++ *value = (u32)NOE_RIU_REG(0x0035, 0xf6); ++ ++ printk("%s(phy_addr = 0x%x, address = 0x%02x, value = 0x%04x)\n", __FUNCTION__, (u32)phy_addr, (u32)address, *value); ++} ++ ++void MHal_NOE_GPHY_Write_Mii_Mgr(unsigned char phy_addr, unsigned char address, u32 value) ++{ ++ u16 uVal; ++ u8 uRegVal; ++ ++ uVal = (GPHY_MDIO_START_CL22 << GPHY_MDIO_START_SHIFT) ++ | (GPHY_MDIO_OPCODE_WRITE << GPHY_MDIO_OPCODE_SHIFT) ++ | ((phy_addr & 0x1f) << GPHY_MDIO_PHY_ADDRESS_SHIFT) ++ | ((address & 0x1f) << GPHY_MDIO_REG_ADDRESS_SHIFT) ++ | GPHY_MDIO_TA; ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03); ++ NOE_RIU_REG(0x0035, 0xf2) = value & 0xFFFF; ++ NOE_RIU_REG(0x0035, 0xf4) = uVal; ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01); ++ ++ udelay(200); ++ ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ ++ while(!(uRegVal & 0x80)) ++ { ++ printk("uRegVal = 0x%02x\n", uRegVal); ++ uRegVal = MHal_NOE_Read8_Reg(0x0035, 0xf0); ++ barrier (); ++ } ++ ++ printk("%s(phy_addr = 0x%x, address = 0x%02x, value = 0x%04x)\n", __FUNCTION__, (u32)phy_addr, (u32)address, value); ++} ++ ++MS_BOOL MHal_NOE_GPHY_Get_Link_Info(MS_U8 phy_addr) ++{ ++ MS_U32 value; ++ MS_U8 counter = 0; ++ MHal_NOE_GPHY_Read_Mii_Mgr(phy_addr, GPHY_REG_STATUS, &value); ++ while(!(value & GPHY_AN_DONE)) ++ { ++ //wait 4 secs ++ counter++; ++ if(counter > 20) ++ { ++ printk("AN fail \n"); ++ return FALSE; ++ } ++ ++ mdelay(200); ++ MHal_NOE_GPHY_Read_Mii_Mgr(phy_addr, GPHY_REG_STATUS, &value); ++ } ++ counter = 0; ++ MHal_NOE_GPHY_Read_Mii_Mgr(phy_addr, GPHY_REG_STATUS, &value); ++ while(!(value & GPHY_LINK_UP)) ++ { ++ //wait 4 secs ++ counter++; ++ if(counter > 20) ++ { ++ printk("Link up fail \n"); ++ return FALSE; ++ } ++ ++ mdelay(200); ++ MHal_NOE_GPHY_Read_Mii_Mgr(phy_addr, GPHY_REG_STATUS, &value); ++ } ++ ++ MHal_NOE_GPHY_Read_Mii_Mgr(phy_addr, GPHY_REG_STAT1000, &value); ++ if(value & LPA_1000FULL) { ++ printk(" 1000 FUll\n"); ++ } ++ else { ++ MHal_NOE_GPHY_Read_Mii_Mgr(phy_addr, GPHY_REG_LINK_PARTNER, &value); ++ if(value & (LPA_100FULL | LPA_100HALF)) { ++ if(value & LPA_100FULL){ ++ printk(" 100 FUll\n"); ++ //MHalThisBCE.duplex = 1; ++ } ++ else { ++ printk(" 100 Half\n"); ++ //MHalThisBCE.duplex = 0; ++ } ++ } ++ else { ++ if(value & LPA_10FULL) { ++ printk(" 10 FUll\n"); ++ //MHalThisBCE.duplex = 1; ++ } ++ else { ++ printk(" 10 Half\n"); ++ //MHalThisBCE.duplex = 0; ++ } ++ ++ } ++ ++ } ++ return TRUE; ++} ++ ++static void _MHal_NOE_GPHY_Init(void) ++{ ++#if NEW_GPHY ++ //swch 3 ++ MHal_NOE_Write8_Reg(0x000e, 0x7a, 0x00);////wriu 0x00000e7a 0x00 ++ MHal_NOE_Write8_Reg(0x000e, 0x7b, 0x00);////wriu 0x00000e7b 0x00 ++ //swch 4 ++ MHal_NOE_Write8_Reg(0x110b, 0x03, 0x00);////wriu 0x00110b03 0x00 ++ MHal_NOE_Write8_Reg(0x110a, 0xc4, 0x01);////wriu 0x00110ac4 0x01 ++ MHal_NOE_Write8_Reg(0x110a, 0xc5, 0x00);////wriu 0x00110ac5 0x00 ++ MHal_NOE_Write8_Reg(0x110a, 0x23, 0x00);////wriu 0x00110a23 0x00 ++ MHal_NOE_Write8_Reg(0x1124, 0xc4, 0x01);////wriu 0x001124c4 0x01 ++ MHal_NOE_Write8_Reg(0x1124, 0xc5, 0x00);////wriu 0x001124c5 0x00 ++ MHal_NOE_Write8_Reg(0x1124, 0x23, 0x00);////wriu 0x00112423 0x00 ++ MHal_NOE_Write8_Reg(0x1109, 0x63, 0x00);////wriu 0x00110963 0x00 ++ MHal_NOE_Write8_Reg(0x1109, 0x73, 0x00);////wriu 0x00110973 0x00 ++ MHal_NOE_Write8_Reg(0x1109, 0x83, 0x00);////wriu 0x00110983 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0x00, 0x04);////wriu 0x00100b00 0x04 ++ MHal_NOE_Write8_Reg(0x100b, 0x01, 0x00);////wriu 0x00100b01 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0x2e, 0x00);////wriu 0x00100b2e 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0x2f, 0x03);////wriu 0x00100b2f 0x03 ++ MHal_NOE_Write8_Reg(0x100b, 0x3e, 0x18);////wriu 0x00100b3e 0x18 ++ MHal_NOE_Write8_Reg(0x100b, 0x3f, 0x00);////wriu 0x00100b3f 0x00 ++ MHal_NOE_Write8_Reg(0x100a, 0x40, 0x18);////wriu 0x00100a40 0x18 ++ MHal_NOE_Write8_Reg(0x100a, 0x41, 0x00);////wriu 0x00100a41 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0x20, 0x00);////wriu 0x00100b20 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0x21, 0x00);////wriu 0x00100b21 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0x20, 0x01);////wriu 0x00100b20 0x01 ++ MHal_NOE_Write8_Reg(0x100b, 0x21, 0x00);////wriu 0x00100b21 0x00 ++ MHal_NOE_Write8_Reg(0x100b, 0xfa, 0x04);////wriu 0x00100bfa 0x04 ++ //swch 3 ++ MHal_NOE_Write8_Reg(0x000e, 0x40, 0x80);////wriu 0x00000e40 0x80 ++ MHal_NOE_Write8_Reg(0x000e, 0x41, 0x00);////wriu 0x00000e41 0x00 ++ //swch 4 ++ MHal_NOE_Write8_Reg(0x1008, 0x00, 0xc0);////wriu 0x00100800 0xc0 ++ MHal_NOE_Write8_Reg(0x1008, 0x0e, 0x01);////wriu 0x0010080e 0x01 ++ MHal_NOE_Write8_Reg(0x1008, 0x04, 0x10);////wriu 0x00100804 0x10 ++ MHal_NOE_Write8_Reg(0x1008, 0x05, 0x01);////wriu 0x00100805 0x01 ++ MHal_NOE_Write8_Reg(0x1008, 0x40, 0xc0);////wriu 0x00100840 0xc0 ++ MHal_NOE_Write8_Reg(0x1008, 0x4e, 0x01);////wriu 0x0010084e 0x01 ++ MHal_NOE_Write8_Reg(0x1008, 0x44, 0x10);////wriu 0x00100844 0x10 ++ MHal_NOE_Write8_Reg(0x1008, 0x45, 0x01);////wriu 0x00100845 0x01 ++ MHal_NOE_Write8_Reg(0x103a, 0x88, 0x0f);////wriu 0x00103a88 0x0f ++ MHal_NOE_Write8_Reg(0x103a, 0x89, 0x04);////wriu 0x00103a89 0x04 ++ MHal_NOE_Write8_Reg(0x103a, 0x80, 0x01);////wriu 0x00103a80 0x01 ++ MHal_NOE_Write8_Reg(0x103a, 0x81, 0x00);////wriu 0x00103a81 0x00 ++ MHal_NOE_Write8_Reg(0x103a, 0x08, 0x0f);////wriu 0x00103a08 0x0f ++ MHal_NOE_Write8_Reg(0x103a, 0x09, 0x04);////wriu 0x00103a09 0x04 ++ MHal_NOE_Write8_Reg(0x103a, 0x00, 0x01);////wriu 0x00103a00 0x01 ++ MHal_NOE_Write8_Reg(0x103a, 0x01, 0x00);////wriu 0x00103a01 0x00 ++ MHal_NOE_Write8_Reg(0x123e, 0x08, 0x0f);////wriu 0x00123e08 0x0f ++ MHal_NOE_Write8_Reg(0x123e, 0x09, 0x04);////wriu 0x00123e09 0x04 ++ MHal_NOE_Write8_Reg(0x123e, 0x00, 0x01);////wriu 0x00123e00 0x01 ++ MHal_NOE_Write8_Reg(0x123e, 0x01, 0x00);////wriu 0x00123e01 0x00 ++ MHal_NOE_Write8_Reg(0x1038, 0x08, 0x0f);////wriu 0x00103808 0x0f ++ MHal_NOE_Write8_Reg(0x1038, 0x09, 0x04);////wriu 0x00103809 0x04 ++ MHal_NOE_Write8_Reg(0x1038, 0x00, 0x01);////wriu 0x00103800 0x01 ++ MHal_NOE_Write8_Reg(0x1038, 0x01, 0x00);////wriu 0x00103801 0x00 ++ MHal_NOE_Write8_Reg(0x1038, 0x88, 0x0f);////wriu 0x00103888 0x0f ++ MHal_NOE_Write8_Reg(0x1038, 0x89, 0x04);////wriu 0x00103889 0x04 ++ MHal_NOE_Write8_Reg(0x1038, 0x80, 0x01);////wriu 0x00103880 0x01 ++ MHal_NOE_Write8_Reg(0x1038, 0x81, 0x00);////wriu 0x00103881 0x00 ++ MHal_NOE_Write8_Reg(0x141a, 0x08, 0x0f);////wriu 0x00141a08 0x0f ++ MHal_NOE_Write8_Reg(0x141a, 0x09, 0x04);////wriu 0x00141a09 0x04 ++ MHal_NOE_Write8_Reg(0x141a, 0x00, 0x01);////wriu 0x00141a00 0x01 ++ MHal_NOE_Write8_Reg(0x141a, 0x01, 0x00);////wriu 0x00141a01 0x00 ++ MHal_NOE_Write8_Reg(0x101e, 0xa0, 0x00);////wriu 0x00101ea0 0x00 ++ MHal_NOE_Write8_Reg(0x101e, 0xa1, 0x00);////wriu 0x00101ea1 0x00 ++ //swch 3 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x08);////wriu 0x00003640 0x08 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x00);////wriu 0x00003640 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0x1e, 0x00);////wriu 0x0000351e 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0x1f, 0x00);////wriu 0x0000351f 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x42, 0x01);////wriu 0x00003642 0x01 ++ MHal_NOE_Write8_Reg(0x0036, 0x43, 0x00);////wriu 0x00003643 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xda, 0x11);////wriu 0x000036da 0x11 ++ MHal_NOE_Write8_Reg(0x0036, 0xdb, 0x00);////wriu 0x000036db 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xde, 0x00);////wriu 0x000036de 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xdf, 0x00);////wriu 0x000036df 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfc, 0x00);////wriu 0x000036fc 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfd, 0x00);////wriu 0x000036fd 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x08, 0x00);////wriu 0x00003608 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x09, 0x00);////wriu 0x00003609 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x06, 0x04);////wriu 0x00003606 0x04 ++ MHal_NOE_Write8_Reg(0x0036, 0x07, 0x00);////wriu 0x00003607 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xd8, 0x11);////wriu 0x000036d8 0x11 ++ MHal_NOE_Write8_Reg(0x0036, 0xd9, 0x80);////wriu 0x000036d9 0x80 ++ MHal_NOE_Write8_Reg(0x0036, 0xf2, 0x00);////wriu 0x000036f2 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xf3, 0x02);////wriu 0x000036f3 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0xf4, 0x3c);////wriu 0x000036f4 0x3c ++ MHal_NOE_Write8_Reg(0x0036, 0xf5, 0x00);////wriu 0x000036f5 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xf6, 0x02);////wriu 0x000036f6 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0xf7, 0x00);////wriu 0x000036f7 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xf8, 0x38);////wriu 0x000036f8 0x38 ++ MHal_NOE_Write8_Reg(0x0036, 0xf9, 0x20);////wriu 0x000036f9 0x20 ++ MHal_NOE_Write8_Reg(0x0036, 0xfa, 0x05);////wriu 0x000036fa 0x05 ++ MHal_NOE_Write8_Reg(0x0036, 0xfb, 0x00);////wriu 0x000036fb 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfc, 0x00);////wriu 0x000036fc 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfd, 0x02);////wriu 0x000036fd 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0x8e, 0x05);////wriu 0x0000368e 0x05 ++ MHal_NOE_Write8_Reg(0x0036, 0x8f, 0x00);////wriu 0x0000368f 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x46, 0x91);////wriu 0x00003646 0x91 ++ MHal_NOE_Write8_Reg(0x0036, 0x47, 0x00);////wriu 0x00003647 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x5e, 0x34);////wriu 0x0000365e 0x34 ++ MHal_NOE_Write8_Reg(0x0036, 0x5f, 0x34);////wriu 0x0000365f 0x34 ++ MHal_NOE_Write8_Reg(0x0036, 0x60, 0x34);////wriu 0x00003660 0x34 ++ MHal_NOE_Write8_Reg(0x0036, 0x61, 0x34);////wriu 0x00003661 0x34 ++ ++ ////Set clock to AHB clock ++ //swch 4 ++ MHal_NOE_Write8_Reg(0x1033, 0x64, 0x00);////wriu 0x00103364 0x00 ++ //swch 3 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x08);////wriu 0x00003640 0x08 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x00);////wriu 0x00003640 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ ++ ////Pattern : GPHY Initial ++ MHal_NOE_Write8_Reg(0x0036, 0x8e, 0x05);////wriu 0x0000368e 0x05 ++ MHal_NOE_Write8_Reg(0x0036, 0x8f, 0x00);////wriu 0x0000368f 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x64, 0x00);////wriu 0x00003664 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x65, 0x00);////wriu 0x00003665 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x66, 0x00);////wriu 0x00003666 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x67, 0x00);////wriu 0x00003667 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xc4, 0xc1);////wriu 0x000036c4 0xc1 ++ MHal_NOE_Write8_Reg(0x0036, 0xc5, 0x02);////wriu 0x000036c5 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0x80, 0x0c);////wriu 0x00003680 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x81, 0x0c);////wriu 0x00003681 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x82, 0x0c);////wriu 0x00003682 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x83, 0x0c);////wriu 0x00003683 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x7e, 0x44);////wriu 0x0000367e 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x7f, 0x44);////wriu 0x0000367f 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x68, 0x44);////wriu 0x00003668 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x69, 0x44);////wriu 0x00003669 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x76, 0x10);////wriu 0x00003676 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0x77, 0x10);////wriu 0x00003677 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0x78, 0x10);////wriu 0x00003678 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0x79, 0x10);////wriu 0x00003679 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0xb6, 0xc4);////wriu 0x000036b6 0xc4 ++ MHal_NOE_Write8_Reg(0x0036, 0xb7, 0xcc);////wriu 0x000036b7 0xcc ++ MHal_NOE_Write8_Reg(0x0036, 0x8a, 0x00);////wriu 0x0000368a 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x8b, 0x00);////wriu 0x0000368b 0x00 ++ ++ //// reg_led_mode = 2'b01 ++ MHal_NOE_Write8_Reg(0x000e, 0x50, 0x10);////wriu 0x00000e50 0x10 ++ MHal_NOE_Write8_Reg(0x000e, 0x51, 0x00);////wriu 0x00000e51 0x00 ++ _MHal_NOE_GPHY_Set_Config(0); ++ ++#else ++ MS_U8 regValue; ++ //swch 3 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x08);////wriu 0x00003640 0x08 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x00);////wriu 0x00003640 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0x1e, 0x00);////wriu 0x0000351e 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0x1f, 0x00);////wriu 0x0000351f 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x42, 0x01);////wriu 0x00003642 0x01 ++ MHal_NOE_Write8_Reg(0x0036, 0x43, 0x00);////wriu 0x00003643 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xda, 0x11);////wriu 0x000036da 0x11 ++ MHal_NOE_Write8_Reg(0x0036, 0xdb, 0x00);////wriu 0x000036db 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xde, 0x00);////wriu 0x000036de 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xdf, 0x00);////wriu 0x000036df 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfc, 0x00);////wriu 0x000036fc 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfd, 0x00);////wriu 0x000036fd 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x08, 0x00);////wriu 0x00003608 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x09, 0x00);////wriu 0x00003609 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x06, 0x04);////wriu 0x00003606 0x04 ++ MHal_NOE_Write8_Reg(0x0036, 0x07, 0x00);////wriu 0x00003607 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xd8, 0x11);////wriu 0x000036d8 0x11 ++ MHal_NOE_Write8_Reg(0x0036, 0xd9, 0x80);////wriu 0x000036d9 0x80 ++ MHal_NOE_Write8_Reg(0x0036, 0xf2, 0x00);////wriu 0x000036f2 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xf3, 0x02);////wriu 0x000036f3 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0xf4, 0x3c);////wriu 0x000036f4 0x3c ++ MHal_NOE_Write8_Reg(0x0036, 0xf5, 0x00);////wriu 0x000036f5 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xf6, 0x02);////wriu 0x000036f6 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0xf7, 0x00);////wriu 0x000036f7 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xf8, 0x38);////wriu 0x000036f8 0x38 ++ MHal_NOE_Write8_Reg(0x0036, 0xf9, 0x20);////wriu 0x000036f9 0x20 ++ MHal_NOE_Write8_Reg(0x0036, 0xfa, 0x05);////wriu 0x000036fa 0x05 ++ MHal_NOE_Write8_Reg(0x0036, 0xfb, 0x00);////wriu 0x000036fb 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfc, 0x00);////wriu 0x000036fc 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xfd, 0x02);////wriu 0x000036fd 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0x8e, 0x05);////wriu 0x0000368e 0x05 ++ MHal_NOE_Write8_Reg(0x0036, 0x8f, 0x00);////wriu 0x0000368f 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x46, 0x91);////wriu 0x00003646 0x91 ++ MHal_NOE_Write8_Reg(0x0036, 0x47, 0x00);////wriu 0x00003647 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x5e, 0x34);////wriu 0x0000365e 0x34 ++ MHal_NOE_Write8_Reg(0x0036, 0x5f, 0x34);////wriu 0x0000365f 0x34 ++ MHal_NOE_Write8_Reg(0x0036, 0x60, 0x34);////wriu 0x00003660 0x34 ++ MHal_NOE_Write8_Reg(0x0036, 0x61, 0x34);////wriu 0x00003661 0x34 ++ ++ regValue = MHal_NOE_Read8_Reg(0x0036, 0x60); ++ MHAL_NOE_DBG_INFO("MHal_NOE_Read8_Reg(0x0036, 0x60) : %x\r\n", regValue); ++ ++ ////Set clock to AHB clock ++ //swch 4 ++ MHal_NOE_Write8_Reg(0x1033, 0x64, 0x00);////wriu 0x00103364 0x00 ++ //swch 3 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x08);////wriu 0x00003640 0x08 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x40, 0x00);////wriu 0x00003640 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x41, 0x00);////wriu 0x00003641 0x00 ++ ++ ////Pattern : GPHY Initial ++ MHal_NOE_Write8_Reg(0x0036, 0x8e, 0x05);////wriu 0x0000368e 0x05 ++ MHal_NOE_Write8_Reg(0x0036, 0x8f, 0x00);////wriu 0x0000368f 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x64, 0x00);////wriu 0x00003664 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x65, 0x00);////wriu 0x00003665 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x66, 0x00);////wriu 0x00003666 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x67, 0x00);////wriu 0x00003667 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0xc4, 0xc1);////wriu 0x000036c4 0xc1 ++ MHal_NOE_Write8_Reg(0x0036, 0xc5, 0x02);////wriu 0x000036c5 0x02 ++ MHal_NOE_Write8_Reg(0x0036, 0x80, 0x0c);////wriu 0x00003680 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x81, 0x0c);////wriu 0x00003681 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x82, 0x0c);////wriu 0x00003682 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x83, 0x0c);////wriu 0x00003683 0x0c ++ MHal_NOE_Write8_Reg(0x0036, 0x7e, 0x44);////wriu 0x0000367e 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x7f, 0x44);////wriu 0x0000367f 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x68, 0x44);////wriu 0x00003668 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x69, 0x44);////wriu 0x00003669 0x44 ++ MHal_NOE_Write8_Reg(0x0036, 0x76, 0x10);////wriu 0x00003676 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0x77, 0x10);////wriu 0x00003677 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0x78, 0x10);////wriu 0x00003678 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0x79, 0x10);////wriu 0x00003679 0x10 ++ MHal_NOE_Write8_Reg(0x0036, 0xb6, 0xc4);////wriu 0x000036b6 0xc4 ++ MHal_NOE_Write8_Reg(0x0036, 0xb7, 0xcc);////wriu 0x000036b7 0xcc ++ MHal_NOE_Write8_Reg(0x0036, 0x8a, 0x00);////wriu 0x0000368a 0x00 ++ MHal_NOE_Write8_Reg(0x0036, 0x8b, 0x00);////wriu 0x0000368b 0x00 ++ ++ //// reg_led_mode = 2'b01 ++ MHal_NOE_Write8_Reg(0x000e, 0x50, 0x10);////wriu 0x00000e50 0x10 ++ MHal_NOE_Write8_Reg(0x000e, 0x51, 0x00);////wriu 0x00000e51 0x00 ++ ++ ////Set LED0 on control ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h024, 16'h8007); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x24);////wriu 0x000035f2 0x24 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x07);////wriu 0x000035f2 0x07 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x80);////wriu 0x000035f3 0x80 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set LED0 Blinking ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h025, 16'h003f); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x25);////wriu 0x000035f2 0x25 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x3f);////wriu 0x000035f2 0x3f ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set LED3 on control ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h02a, 16'h8007); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x2a);////wriu 0x000035f2 0x2a ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x07);////wriu 0x000035f2 0x07 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x80);////wriu 0x000035f3 0x80 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set LED3 Blinking ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h02b, 16'h003f); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x2b);////wriu 0x000035f2 0x2b ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x3f);////wriu 0x000035f2 0x3f ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////By mode setting Start ++ ++ //// DA_AD_CORE_PWD_C TBT=1, HBT=1 ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h0e4, 16'h1101); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0xe4);////wriu 0x000035f2 0xe4 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x01);////wriu 0x000035f2 0x01 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x11);////wriu 0x000035f3 0x11 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ //// DA_AD_CORE_PWD_D TBT=1, HBT=1 ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h0e5, 16'h1101); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0xe5);////wriu 0x000035f2 0xe5 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x01);////wriu 0x000035f2 0x01 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x11);////wriu 0x000035f3 0x11 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////DA_TX_CM1_OP ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h26a, 16'h0440); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x6a);////wriu 0x000035f2 0x6a ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x40);////wriu 0x000035f2 0x40 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x04);////wriu 0x000035f3 0x04 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set cr_da_tx_cm1_op_tsmode ++ ////Set cr_da_tx_rm1_op_tsmode ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h26b, 16'h0000); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x6b);////wriu 0x000035f2 0x6b ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x00);////wriu 0x000035f2 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set cr_da_tx_cm1_op_gbe_slp ++ ////Set cr_da_tx_cm2_op_gbe_slp ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h302, 16'h0004); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x02);////wriu 0x000035f2 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x03);////wriu 0x000035f3 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x04);////wriu 0x000035f2 0x04 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_FILTER_CAP_A ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h023, 16'h0555); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x23);////wriu 0x000035f2 0x23 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x55);////wriu 0x000035f2 0x55 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x05);////wriu 0x000035f3 0x05 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_FILTER_CAP_B ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h024, 16'h0555); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x24);////wriu 0x000035f2 0x24 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x55);////wriu 0x000035f2 0x55 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x05);////wriu 0x000035f3 0x05 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_FILTER_CAP_C ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h025, 16'h0555); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x25);////wriu 0x000035f2 0x25 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x55);////wriu 0x000035f2 0x55 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x05);////wriu 0x000035f3 0x05 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_FILTER_CAP_D ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h026, 16'h0555); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x26);////wriu 0x000035f2 0x26 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x55);////wriu 0x000035f2 0x55 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x05);////wriu 0x000035f3 0x05 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_OVERSHOOT_EN ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h011, 16'h0f00); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x11);////wriu 0x000035f2 0x11 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x00);////wriu 0x000035f2 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x0f);////wriu 0x000035f3 0x0f ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set CR_DA_TX_PS_DRIR0 ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h269, 16'h444f); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x69);////wriu 0x000035f2 0x69 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x4f);////wriu 0x000035f2 0x4f ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x44);////wriu 0x000035f3 0x44 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h268, 16'h03f4); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x68);////wriu 0x000035f2 0x68 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0xf4);////wriu 0x000035f2 0xf4 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x03);////wriu 0x000035f3 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set CR_DA_TX_PS_OP ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h272, 16'h35bf); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x72);////wriu 0x000035f2 0x72 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0xbf);////wriu 0x000035f2 0xbf ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x35);////wriu 0x000035f3 0x35 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h271, 16'h7e94); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x71);////wriu 0x000035f2 0x71 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x94);////wriu 0x000035f2 0x94 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x7e);////wriu 0x000035f3 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_I2MPB_A ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h016, 16'h4010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x16);////wriu 0x000035f2 0x16 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x40);////wriu 0x000035f3 0x40 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h012, 16'h4010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x12);////wriu 0x000035f2 0x12 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x40);////wriu 0x000035f3 0x40 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_I2MPB_B ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h018, 16'h1010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x18);////wriu 0x000035f2 0x18 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x10);////wriu 0x000035f3 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h017, 16'h1010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x17);////wriu 0x000035f2 0x17 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x10);////wriu 0x000035f3 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_I2MPB_C ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h019, 16'h1010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x19);////wriu 0x000035f2 0x19 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x10);////wriu 0x000035f3 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h020, 16'h1010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x20);////wriu 0x000035f2 0x20 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x10);////wriu 0x000035f3 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set DA_TX_I2MPB_D ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h022, 16'h1010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x22);////wriu 0x000035f2 0x22 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x10);////wriu 0x000035f3 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////reg_mdio_cl45_write(addr, 16'h1e, 16'h021, 16'h1010); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x21);////wriu 0x000035f2 0x21 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x10);////wriu 0x000035f2 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x10);////wriu 0x000035f3 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7a);////wriu 0x000035f4 0x7a ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ ////Set CR_DA_TX_I2MPB_10M ++ ////reg_mdio_cl45_write(addr, 16'h1f, 16'h27c, 16'h0000); ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x7c);////wriu 0x000035f2 0x7c ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x02);////wriu 0x000035f3 0x02 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x00);////wriu 0x000035f5 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x03);////wriu 0x000035f0 0x03 ++ MHal_NOE_Write8_Reg(0x0035, 0xf2, 0x00);////wriu 0x000035f2 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf3, 0x00);////wriu 0x000035f3 0x00 ++ MHal_NOE_Write8_Reg(0x0035, 0xf4, 0x7e);////wriu 0x000035f4 0x7e ++ MHal_NOE_Write8_Reg(0x0035, 0xf5, 0x10);////wriu 0x000035f5 0x10 ++ MHal_NOE_Write8_Reg(0x0035, 0xf1, 0x01);////wriu 0x000035f1 0x01 ++ udelay(200); ++ ++ MHal_NOE_Write8_Reg(0x0035, 0xf0, 0x00); //change mdio access mode from m* proprietary to generic ++#endif ++} ++ ++ ++static void _MHal_NOE_GE1ToGPHY(void) ++{ ++ //NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x30 << 1) &= ~0x0003; ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1), 0x0F00, 0x0C00); ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1), 0x000F, 0x0008); ++ ++ if (noe_config.mdio_n == 1) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x9044, 0x1044); ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_1000) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x9044, 0x1044); ++ } ++ else if ((noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) || ++ (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10)) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x9044, 0x9044); ++ } ++ } ++ else { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0xD044, 0x5044); ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_1000) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0xD044, 0x5044); ++ } ++ else if ((noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) || ++ (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10)) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0xD044, 0xD044); ++ } ++ } ++ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1), 0x0077, 0x0000); ++} ++ ++static void _MHal_NOE_GE1ToPM(void) ++{ ++ MHAL_NOE_DBG_INFO("[%s][%d] GE1 To PM\n",__FUNCTION__,__LINE__); ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1) & (~0x0F00)) | 0x0C00; ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1) & (~0x000F)) | 0x0000; ++ if (noe_config.mdio_n == 1) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x1024)) | 0x1024; ++ } ++ else { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = 0x5024; //(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x5024)) | 0x5024; ++ } ++ ++#if 0 ++///////////////// Add for test /////////////// ++ printk("cell mode\n"); ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x13 << 1) = 0x0CC0; ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x13 << 1) = 0x0EE0; ++ ++ ++ if (noe_config.version == 0x0) ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x13 << 1) = 0x0000; ++ ++//////////////// End //////////////////////// ++#endif ++ printk("io mode \n"); ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) = 0x0088; ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) = 0x8088; ++ ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x60 << 1) = 0x008C; ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) & (~0x0004)) | 0x0004; ++ ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) & (~0x0003)) | 0x0003; ++ } ++ else if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) & (~0x0003)) | 0x0001; ++ } ++ NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) = (NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) & (~0x0100)) | 0x0000; ++ ++} ++ ++static void _MHal_NOE_GE2ToPM(void) ++{ ++#if 0 //New ++ printk("[%s][%d] \n",__FUNCTION__,__LINE__); ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) & (~0x0F00)) | 0x0C00; ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) & (~0x000F)) | 0x0000; ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x2028)) | 0x2008; ++ ++ ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) &= (~0xFF8F); ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) |= 0x0088; ++ } ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) |= 0x8088; ++ } ++ ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x60 << 1) = 0x00AC; ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x69 << 1) = 0x8088; ++ ++ if (noe_config.version == 0x0) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x68 << 1) = 0x008C; ++ } ++ else { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x68 << 1) = 0x00AC; ++ } ++ //IO Mode ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) &(~0x0004)) | 0x000; ++ NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) = (NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) & (~0x0100)) | 0x0000; ++ ++#else ++ printk("[%s][%d] \n",__FUNCTION__,__LINE__); ++ if (noe_config.mii_info[E_NOE_GE_MAC2].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) & (~0xC000)) | 0x0C00; ++ } ++ else if (noe_config.mii_info[E_NOE_GE_MAC2].speed == E_NOE_SPEED_10) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) & (~0xC000)) | 0x0400; ++ } ++ ++ ++ /* ### Clkgen ### */ ++ // reg_ckg_gmac_ahb ++ NOE_RIU_REG(0x100a, 0x02) = 0x0c00; ++ // reg_ckg_secgmac_ahb ++ NOE_RIU_REG(0x1033, 0x64) = 0x0000; ++ // reg_ckg_syn_gmac ++ NOE_RIU_REG(0x100b, 0xc6) = 0x0000; ++ // reg_ckadj_rx ++ NOE_RIU_REG(0x121f, 0x22) = 0x0000; ++ // reg_xmii_10_100_when_slow ... ++ NOE_RIU_REG(0x121f, 0x24) = 0x0000; ++ // reg_2x_mode_clk_pol ++ NOE_RIU_REG(0x0035, 0xc2) = 0x8088; ++ // reg_rgmii_sl_mode ++ NOE_RIU_REG(0x0035, 0xc0) = 0x00ac; ++ // reg_rmii_cken_sec ... ++ NOE_RIU_REG(0x0035, 0xd2) = 0x8088; ++ // req_fifo_qu1_sec ... ++ NOE_RIU_REG(0x0035, 0xd0) = 0x00ac; ++ ++ /* ### Settings of mux with NOE ### */ ++ NOE_RIU_REG(0x121f, 0x3c) = 0x2018; ++ ++ /* ### Settings of GMAC mux ### */ ++ // reg_ckadj_rx ++ NOE_RIU_REG(0x121f, 0x22) = 0x0c88; ++ // reg_ckg_gmac_rx_ref ++ NOE_RIU_REG(0x121f, 0x24) = 0x2880; ++ // DDR mode ++ NOE_RIU_REG(0x121f, 0x26) = 0x0ee2; ++ // reg_tx_padclk_sel ++ NOE_RIU_REG(0x121f, 0x20) = 0x0200; ++#endif ++} ++ ++static void _MHal_NOE_GE2ToCHIPTOP(void) ++{ ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) = 0x0C88; ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2880; ++ if (noe_config.mdio_n == 1) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x2028)) | 0x2028; ++ } ++ else { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x6068)) | 0x2068; ++ } ++ ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0CE0; ++ else if(noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0EE0; ++ ++ ++ if (noe_config.version == 0) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x10 << 1) = 0x0000; ++ } ++ else { ++ /* Need to Check */ ++ } ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) & (~0xC000)) | 0xC000; ++ } ++ else if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10) { ++ /* 100 or 10 */ ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) & (~0xC000)) | 0x4000; ++ } ++ NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1) = NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1)| 0x0001; ++} ++ ++static void _MHal_NOE_GE1ToGPHY_GE2ToPM(void) ++{ ++ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(0x000E, 0x38) , 0xFF00, 0x0000); ++ ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1) = 0x0000; ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1) = 0x0008; ++ NOE_RIU_REG(0x121F, 0x11 << 1) = 0x0000; ++ NOE_RIU_REG(0x121F, 0x12 << 1) = 0x0000; ++ NOE_RIU_REG(0x0031, 0x69 << 1) = 0x8088; ++ NOE_RIU_REG(0x0031, 0x68 << 1) = 0x00AC; ++ ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_1000) { ++ NOE_RIU_REG(0x121F, 0x1E << 1) = 0x1064 | 0x2018; ++ } ++ else { ++ /* 100 or 10 */ ++ NOE_RIU_REG(0x121F, 0x1E << 1) = 0x9064 | 0x2018; ++ } ++ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(0x101E, 0x50 << 1), 0xFF00, 0x0000); ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(0x101E, 0x06 << 1), 0x00FF, 0x0001); ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1) = 0x0C88; ++ NOE_RIU_REG(0x121F, 0x11 << 1) = 0x0C88; ++ NOE_RIU_REG(0x121F, 0x12 << 1) = 0x2880; ++ NOE_RIU_REG(0x121F, 0x13 << 1) = 0x0EE2; ++ NOE_RIU_REG(0x121F, 0x10 << 1) = 0x0200; ++} ++ ++static void _MHal_NOE_GE1ToGPHY_GE2ToCHIPTOP(void) ++{ ++#if 1 ++ printk("[%s][%d]!!!!! GE2 To CHIPTOP, noe_config.mdio_n=%d\n",__FUNCTION__,__LINE__,noe_config.mdio_n); ++ _MHal_NOE_GE1ToGPHY(); ++ ++#if 0 ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) = 0x0C88; ++ ++#if 1 ++ printk("[%s][%d]!!!!! GE2 To CHIPTOP, noe_config.mdio_n=%d\n",__FUNCTION__,__LINE__,noe_config.mdio_n); ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2080; // original 2880, but gphy cannot works ++ if (noe_config.version == 0) { ++ //NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) &= ~0x0002; ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2080; ++ //NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1) |= BIT(6); ++ } ++ else { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2880; // original 2880, but gphy cannot works ++ } ++ if (noe_config.mdio_n == 1) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) |= 0x2028; ++ else ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) |= 0x2068; ++#else ++ printk("[%s][%d]xxxxxx GE2 To CHIPTOP, noe_config.mdio_n=%d\n",__FUNCTION__,__LINE__,noe_config.mdio_n); ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2080; // original 2880, but gphy cannot works ++ if (noe_config.mdio_n == 1) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x2028, 0x2028); ++ else ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x6068, 0x2068); ++#endif ++ ++ ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0CE0; ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0EE0; ++ ++ if (noe_config.version == 0) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x10 << 1), 0x0004, 0x0000); ++ else /* Need to Check */ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x10 << 1), 0x0004 , 0x0004); ++ ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1), 0xC000, 0xC000); ++ else if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1), 0xC000, 0x4000); ++ ++ NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1) |= 0x0001; ++#endif ++ ++#else ++ /* GE2 To Chiptop*/ ++ printk("[%s][%d]!!!!! GE2 To CHIPTOP, noe_config.mdio_n=%d\n",__FUNCTION__,__LINE__,noe_config.mdio_n); ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) = 0x0C88; ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2880; ++ if (noe_config.mdio_n == 1) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x2028, 0x2028); ++ else ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x6068, 0x2068); ++ ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0CE0; ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0EE0; ++ ++ if (noe_config.version == 0) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x10 << 1), 0x0004, 0x0000); ++ else /* Need to Check */ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x10 << 1), 0x0004 , 0x0004); ++ ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1), 0xC000, 0xC000); ++ else if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10) ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1), 0xC000, 0x4000); ++ ++ NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1) |= 0x0001; ++ ++ /* GE1 To GPHY*/ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1), 0x0F00, 0x0C00); ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1), 0x000F, 0x0008); ++ ++#if 1 ++ printk("why?????????????????????? \n"); ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x0002, 0x0000); ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) |= 0x1044; ++ //NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1), 0x0077, 0x0000); ++#else ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1), 0x0F00, 0x0C00); ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1), 0x000F, 0x0008); ++ ++ if (noe_config.mdio_n == 1) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x9044, 0x1044); ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_1000) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x9044, 0x1044); ++ } ++ else if ((noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) || ++ (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10)) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0x9044, 0x9044); ++ } ++ } ++ else { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0xD044, 0x5044); ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_1000) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0xD044, 0x5044); ++ } ++ else if ((noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) || ++ (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10)) { ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1), 0xD044, 0xD044); ++ } ++ } ++ ++ NOE_RIU_REG_MASK_WRITE(NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1), 0x0077, 0x0000); ++ ++ ++#endif ++#endif ++} ++ ++static void _MHal_NOE_GE1ToPM_GE2ToCHIPTOP(void) ++{ ++ ++ printk("[%s][%d] GE1 To PM and GE2 To CHIPTOP \n",__FUNCTION__,__LINE__); ++ /* GE1 TO PM*/ ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x11 << 1) & (~0x0F00)) | 0x0C00; ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x12 << 1) & (~0x000F)) | 0x0000; ++ if (noe_config.mdio_n == 1) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x1024)) | 0x1024; ++ } ++ else { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) & (~0x5024)) | 0x5024; ++ } ++ ++#if 0 ++///////////////// Add for test /////////////// ++ printk("cell mode\n"); ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x13 << 1) = 0x0CC0; ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x13 << 1) = 0x0EE0; ++ ++ ++ if (noe_config.version == 0x0) ++ NOE_RIU_REG(NOE_RIU_BANK_SECGMAC4, 0x13 << 1) = 0x0000; ++ ++//////////////// End //////////////////////// ++#endif ++ ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) = 0x0088; ++ } ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x61 << 1) = 0x8088; ++ } ++ ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x60 << 1) = 0x008C; ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) & (~0x0004)) | 0x0004; ++ ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) & (~0x0003)) | 0x0003; ++ } ++ else if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_ALBANY0, 0x62 << 1) & (~0x0003)) | 0x0001; ++ } ++ NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) = (NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) & (~0x0100)) | 0x0000; ++ ++ /* GE2 To CHIPTOP*/ ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x11 << 1) = 0x0C88; ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = 0x2880; ++ if (noe_config.mdio_n == 1) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) |= 0x2028; ++ } ++ else { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x1E << 1) |= 0x2028; ++ } ++ ++ if (noe_config.delay == E_MHAL_NOE_DELAY_NS_0) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0CE0; ++ else if (noe_config.delay == E_MHAL_NOE_DELAY_NS_2) ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x13 << 1) = 0x0EE0; ++ ++ ++ if (noe_config.version == 0) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x10 << 1) = 0x0000; ++ } ++ else { ++ /* Need to Check */ ++ } ++ if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_100) { ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) & (~0xC000)) | 0xC000; ++ } ++ else if (noe_config.mii_info[E_NOE_GE_MAC1].speed == E_NOE_SPEED_10) { ++ /* 100 or 10 */ ++ NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) = (NOE_RIU_REG(NOE_RIU_BANK_GMAC4, 0x12 << 1) & (~0xC000)) | 0x4000; ++ } ++ NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1) = NOE_RIU_REG(NOE_RIU_BANK_CHIPTOP, 0x06 << 1)| 0x0001; ++ ++#if 0 // remove Kevin's script ++ NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0xF2) = (NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0xF2) & (~0x20)) | 0x20; ++ NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0xC5) = (NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0xF5) & (~0xF0)) | 0x00; ++ NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0xF3) = (NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0xF3) & (~0x04)) | 0x04; ++ NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0x63) = (NOE_RIU8_REG(NOE_RIU_BANK_ALBANY1, 0x63) & (~0x03)) | 0x03; ++#endif ++} ++ ++static inline void MHal_NOE_Enable_Mdio(EN_NOE_SEL enable) ++{ ++ ++} ++ ++ ++void MHal_NOE_Write_Bits_Zero(void __iomem *addr, MS_U32 bit, MS_U32 len) ++{ ++ int reg_val; ++ int i; ++ ++ reg_val = MHal_NOE_Read_Reg(addr); ++ for (i = 0; i < len; i++) ++ reg_val &= ~(1 << (bit + i)); ++ MHal_NOE_Write_Reg(addr, reg_val); ++} ++ ++void MHal_NOE_Write_Bits_One(void __iomem *addr, MS_U32 bit, MS_U32 len) ++{ ++ unsigned int reg_val; ++ unsigned int i; ++ ++ reg_val = MHal_NOE_Read_Reg(addr); ++ for (i = 0; i < len; i++) ++ reg_val |= 1 << (bit + i); ++ MHal_NOE_Write_Reg(addr, reg_val); ++} ++ ++EN_NOE_RET MHal_NOE_Set_Pin_Mux(EN_NOE_SEL_PIN_MUX mux) ++{ ++ if(mux >= E_NOE_SEL_PIN_MUX_MAX) { ++ return E_NOE_RET_INVALID_PARAM; ++ } ++ MHAL_NOE_DBG_INFO("mux=%d\n",mux); ++ ++ if ((mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY) || ++ (mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM) || ++ (mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_CHIPTOP)) { ++ MHAL_NOE_DBG_INFO(" start internal PHY \n"); ++ _MHal_NOE_GPHY_Init(); ++ } ++ noe_config.pin_mux = mux; ++ _mhal_noe_pinmux_pfn[mux](); ++ _MHal_NOE_Init_Mdio(mux); ++ return E_NOE_RET_TRUE; ++} ++ ++void MHal_NOE_Set_MAC_Address(EN_NOE_GE_MAC ge, unsigned char p[6]) ++{ ++ unsigned long reg_value; ++ reg_value = (p[0] << 8) | (p[1]); ++ if (ge == E_NOE_GE_MAC1) { ++ MHal_NOE_Write_Reg(GDMA1_MAC_ADRH, reg_value); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ MHal_NOE_Write_Reg(GDMA2_MAC_ADRH, reg_value); ++ } ++ reg_value = (p[2] << 24) | (p[3] << 16) | (p[4] << 8) | p[5]; ++ if(ge == E_NOE_GE_MAC1) { ++ MHal_NOE_Write_Reg(GDMA1_MAC_ADRL, reg_value); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ MHal_NOE_Write_Reg(GDMA2_MAC_ADRL, reg_value); ++ } ++ ++ MHAL_NOE_DBG_INFO("GMAC%d_MAC_ADRH -- : 0x%08x\n", ge+1, (ge == E_NOE_GE_MAC1)?MHal_NOE_Read_Reg(GDMA1_MAC_ADRH):MHal_NOE_Read_Reg(GDMA2_MAC_ADRH)); ++ MHAL_NOE_DBG_INFO("GMAC%d_MAC_ADRL -- : 0x%08x\n", ge+1, (ge == E_NOE_GE_MAC1)?MHal_NOE_Read_Reg(GDMA1_MAC_ADRL):MHal_NOE_Read_Reg(GDMA2_MAC_ADRL)); ++} ++ ++ ++void MHal_NOE_Stop(void) ++{ ++ unsigned int reg_value; ++ ++ MHAL_NOE_DBG_INFO("%s()...",__FUNCTION__); ++ reg_value = MHal_NOE_Read_Reg(DMA_GLO_CFG); ++ reg_value &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); ++ MHal_NOE_Write_Reg(DMA_GLO_CFG, reg_value); ++ ++ MHAL_NOE_DBG_INFO("Done\n"); ++} ++ ++ ++void MHal_NOE_Reset_FE(void) ++{ ++ unsigned int val; ++ val = MHal_NOE_Read_Reg(RSTCTRL); ++ val = val | RSTCTL_FE_RST; ++ MHal_NOE_Write_Reg(RSTCTRL, val); ++ ++ val = val & ~(RSTCTL_FE_RST); ++ MHal_NOE_Write_Reg(RSTCTRL, val); ++} ++ ++ ++void MHal_NOE_Set_DBG(EN_NOE_HAL_LOG level) ++{ ++ noe_config.noe_dbg_enable = level; ++} ++ ++void MHal_NOE_Reset_GMAC(void) ++{ ++#if 0 ++ MHal_NOE_Write_Reg(RSTCTRL, 0x00800000); ++ MHal_NOE_Write_Reg(RSTCTRL, 0x00000000); ++#endif ++} ++ ++static EN_NOE_RET _MHal_NOE_Write_Mii_Mgr(u32 addr, u32 reg, u32 write_data) ++{ ++ unsigned long t_start = jiffies; ++ u32 data; ++ ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ /* make sure previous write operation is complete */ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation ongoing\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ data = (0x01 << 16) | (1 << 18) | (addr << 20) | (reg << 25) | write_data; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); /*start*/ ++ /* MHAL_NOE_DBG_INFO("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); */ ++ ++ t_start = jiffies; ++ ++ /* make sure write operation is complete */ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation Time Out\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++static EN_NOE_RET _MHal_NOE_Read_Mii_Mgr(u32 addr, u32 reg, u32 *read_data) ++{ ++ MS_U32 status = 0; ++ unsigned long t_start = jiffies; ++ MS_U32 data = 0; ++ ++ /* We enable mdio gpio purpose register, and disable it when exit. */ ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ /* make sure previous read operation is complete */ ++ while (1) { ++ /* 0 : Read/write operation complete */ ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ ++ data = (0x01 << 16) | (0x02 << 18) | (addr << 20) | (reg << 25); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ ++ /* make sure read operation is complete */ ++ t_start = jiffies; ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ status = MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0); ++ *read_data = (MS_U32)(status & 0x0000FFFF); ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation Time Out!!\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++ ++static void _MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable) ++{ ++ if (enable == E_NOE_SEL_ENABLE) ++ { ++ MHal_NOE_Write_Reg(ESW_PHY_POLLING, MHal_NOE_Read_Reg(ESW_PHY_POLLING)|(1 << 31)); ++ } ++ else{ ++ MHal_NOE_Write_Reg(ESW_PHY_POLLING, MHal_NOE_Read_Reg(ESW_PHY_POLLING)&(~(1 << 31))); ++ } ++} ++ ++ ++static MS_U8 MHal_NOE_Is_Mii_Mgr_Force_Mode(u32 addr) ++{ ++ unsigned char i = 0; ++ for (i = 0; i < E_NOE_GE_MAC_MAX; i++) ++ { ++ if (noe_config.mii_info[i].phy_addr == addr) { ++ return noe_config.mii_info[i].noe_mii_force_mode; ++ } ++ } ++ return NOE_DISABLE; ++} ++ ++static EN_NOE_RET _MHal_NOE_Set45_Mii_Mgr_Addr(u32 port_num, u32 dev_addr, u32 reg_addr) ++{ ++ unsigned long t_start = jiffies; ++ MS_U32 data = 0; ++ ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ data = (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) | reg_addr; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ ++ t_start = jiffies; ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation Time Out\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++ ++EN_NOE_RET MHal_NOE_Write45_Mii_Mgr(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data) ++{ ++ unsigned long t_start = jiffies; ++ u32 data = 0; ++ ++ /* set address first */ ++ _MHal_NOE_Set45_Mii_Mgr_Addr(port_num, dev_addr, reg_addr); ++ udelay(10); ++ ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ ++ data = (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) | write_data; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ ++ t_start = jiffies; ++ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Write operation Time Out\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++EN_NOE_RET MHal_NOE_Read45_Mii_Mgr(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data) ++{ ++ u32 status = 0; ++ unsigned long t_start = jiffies; ++ u32 data = 0; ++ ++ /* set address first */ ++ _MHal_NOE_Set45_Mii_Mgr_Addr(port_num, dev_addr, reg_addr); ++ udelay(10); ++ ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_ENABLE); ++ ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ break; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation is ongoing !!\n"); ++ return E_NOE_RET_DEVICE_BUSY; ++ } ++ } ++ data = (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) | reg_addr; ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, data); ++ MHal_NOE_Write_Reg(MDIO_PHY_CONTROL_0, (data | (1 << 31))); ++ t_start = jiffies; ++ while (1) { ++ if (!(MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ *read_data = (MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0) & 0x0000FFFF); ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ return E_NOE_RET_TRUE; ++ } else if (time_after(jiffies, t_start + 5 * HZ)) { ++ MHal_NOE_Enable_Mdio(E_NOE_SEL_DISABLE); ++ MHAL_NOE_DBG_INFO("\n MDIO Read operation Time Out!!\n"); ++ return E_NOE_RET_TIMEOUT; ++ } ++ status = MHal_NOE_Read_Reg(MDIO_PHY_CONTROL_0); ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++EN_NOE_RET MHal_NOE_Write_Mii_Mgr(u32 addr, u32 reg, u32 write_data) ++{ ++ MS_U32 an_status = 0; ++ if ((MHal_NOE_Is_Mii_Mgr_Force_Mode(addr) == NOE_ENABLE) && (addr == 31)) { ++ an_status = (MHal_NOE_Read_Reg(ESW_PHY_POLLING) & (1 << 31)); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++ } ++ if(_MHal_NOE_Write_Mii_Mgr(addr, 0x1f, (reg>>6)&0x3FFF) == E_NOE_RET_TRUE) { ++ if(_MHal_NOE_Write_Mii_Mgr(addr, (reg>>2) & 0xF, write_data & 0xFFFF) == E_NOE_RET_TRUE) { ++ if(_MHal_NOE_Write_Mii_Mgr(addr, (0x1 << 4), write_data >> 16) == E_NOE_RET_TRUE) { ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ } ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ } ++ else { ++ if (_MHal_NOE_Write_Mii_Mgr(addr, reg, write_data) == E_NOE_RET_TRUE) { ++ return E_NOE_RET_TRUE; ++ } ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++EN_NOE_RET MHal_NOE_Read_Mii_Mgr(u32 addr, u32 reg, u32 *read_data) ++{ ++ u32 low_word; ++ u32 high_word; ++ u32 an_status = 0; ++ if ((MHal_NOE_Is_Mii_Mgr_Force_Mode(addr) == NOE_ENABLE) && (addr == 31)) { ++ an_status = (MHal_NOE_Read_Reg(ESW_PHY_POLLING) & (1 << 31)); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_DISABLE); ++ } ++ ++ if (_MHal_NOE_Write_Mii_Mgr(addr, 0x1f, (reg >> 6) & 0x3FFF)) { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, (reg >> 2) & 0xF, &low_word)) { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, (0x1 << 4), &high_word)) { ++ *read_data = (high_word << 16) | (low_word & 0xFFFF); ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ return E_NOE_RET_TRUE; ++ } ++ } ++ } ++ if (an_status) { ++ _MHal_NOE_Set_Auto_Polling(E_NOE_SEL_ENABLE); ++ } ++ } ++ else ++ { ++ if (_MHal_NOE_Read_Mii_Mgr(addr, reg, read_data)) { ++ return E_NOE_RET_TRUE; ++ } ++ } ++ ++ return E_NOE_RET_FALSE; ++} ++ ++void MHal_NOE_Get_GSW_Delay_Setting(void) ++{ ++ int reg_int_val = 0; ++ int link_speed = 0; ++ reg_int_val = MHal_NOE_Read_Reg(FE_INT_STATUS2); ++ if (reg_int_val & BIT(25)) { ++ /* if link up */ ++ if (MHal_NOE_Read_Reg(NOE_REG_ETH_SW_BASE + 0x0208) & 0x1) { ++ link_speed = (MHal_NOE_Read_Reg(NOE_REG_ETH_SW_BASE + 0x0208) >> 2 & 0x3); ++ if (link_speed == 1) { ++ /* delay setting for 100M */ ++ MHAL_NOE_DBG_INFO("GE2 link rate to 100M\n"); ++ } else if (link_speed == 0) { ++ /* delay setting for 10M */ ++ MHAL_NOE_DBG_INFO("GE2 link rate to 10M\n"); ++ } else if (link_speed == 2) { ++ /* delay setting for 1G */ ++ MHAL_NOE_DBG_INFO("GE2 link rate to 1G\n"); ++ } ++ } ++ } ++ MHal_NOE_Write_Reg(FE_INT_STATUS2, reg_int_val); ++} ++ ++ ++MS_BOOL MHal_NOE_Support_Auto_Polling(void) ++{ ++ if (noe_config.version == 0) { ++ if ((noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM) || ++ (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_CHIPTOP)) { ++ return FALSE; ++ } ++ } ++ return TRUE; ++} ++ ++void MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable) ++{ ++ MS_U32 reg_value; ++ ++ if (noe_config.version == 0) { ++ if ((noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM) || ++ (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_CHIPTOP)) { ++ return; ++ } ++ } ++ ++ /* FIXME: we don't know how to deal with PHY end addr */ ++ reg_value = MHal_NOE_Read_Reg(ESW_PHY_POLLING); ++ reg_value &= ~(0x1f); ++ reg_value &= ~(0x1f << 8); ++ ++ if (E_NOE_SEL_ENABLE == enable) { ++ reg_value |= (1 << 31); ++ } ++ else { ++ reg_value &= 0x7FFFFFFF; ++ } ++ ++ /* setup PHY address for auto polling (Start Addr). */ ++ reg_value |= noe_config.mii_info[E_NOE_GE_MAC1].phy_addr & 0x1F; ++ ++ /* setup PHY address for auto polling (End Addr). */ ++ reg_value |= (noe_config.mii_info[E_NOE_GE_MAC2].phy_addr & 0x1F) << 8; ++ ++ ++ MHAL_NOE_DBG_INFO("[%s][%d] reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value); ++ MHal_NOE_Write_Reg(ESW_PHY_POLLING, reg_value); ++} ++ ++void MHal_NOE_Force_Link_Mode(EN_NOE_GE_MAC ge, EN_NOE_SPEED speed, EN_NOE_DUPLEX duplex) ++{ ++ MS_U32 reg_value = 0; ++ ++ if(ge == E_NOE_GE_MAC1) { ++ reg_value = MHal_NOE_Read_Reg(NOE_MAC_P1_MCR); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ reg_value = MHal_NOE_Read_Reg(NOE_MAC_P2_MCR); ++ } ++ ++ MHAL_NOE_DBG_INFO("GMAC%d: 0x%x \n", ge+1 , reg_value); ++ if ((duplex == E_NOE_DUPLEX_INVALID) && (speed == E_NOE_SPEED_INVALID)) { ++ reg_value &= (~0x8031); ++ } ++ else { ++ reg_value &= (~(0x2|0xC)); ++ reg_value |= (0x01 | 0x30 | 0xE000); ++ ++ if(speed == E_NOE_SPEED_1000) { ++ reg_value |= 0x8; ++ if (duplex == E_NOE_DUPLEX_FULL) { ++ reg_value |= 0x2; ++ } ++ } ++ else if(speed == E_NOE_SPEED_100) { ++ reg_value |= 0x4; ++ if (duplex == E_NOE_DUPLEX_FULL) { ++ reg_value |= 0x2; ++ } ++ } ++ else { ++ if (duplex == E_NOE_DUPLEX_FULL) { ++ reg_value |= 0x2; ++ } ++ } ++ } ++ ++ if(ge == E_NOE_GE_MAC1) { ++ MHal_NOE_Write_Reg(NOE_MAC_P1_MCR, reg_value); ++ MHAL_NOE_DBG_INFO("GMAC1: 0x%x \n",MHal_NOE_Read_Reg(NOE_MAC_P1_MCR)); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ MHal_NOE_Write_Reg(NOE_MAC_P2_MCR, reg_value); ++ MHAL_NOE_DBG_INFO("GMAC2: 0x%x \n",MHal_NOE_Read_Reg(NOE_MAC_P2_MCR)); ++ } ++ ++ //FPGA is clock /10 , so 100M Mac vs 10M Phy ++ //MHAL_NOE_DBG_INFO("GMAC: Force mode, Link Up, 100Mbps, Full-Duplex, FC ON\n"); ++ //MHal_NOE_Write_Reg(NOE_MAC_P1_MCR, 0x2105e337);//(P0, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++ //MHal_NOE_Write_Reg(NOE_MAC_P2_MCR, 0x2105e337);//(P1, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++} ++ ++void MHal_NOE_Set_Interface_Mode(EN_NOE_GE_MAC ge, EN_NOE_INTERFACE mode) ++{ ++ MS_U32 val = 0; ++ if(ge == E_NOE_GE_MAC1) { ++ val = MHal_NOE_Read_Reg(SYSCFG1) & (~(0x3 << 12)); /* E_NOE_INTERFACE_RGMII_MODE */ ++ if (mode == E_NOE_INTERFACE_MII_MODE) ++ val = val | BIT(12); ++ else if (mode == E_NOE_INTERFACE_RMII_MODE) ++ val = val | BIT(13); ++ MHal_NOE_Write_Reg(SYSCFG1, val); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ val = MHal_NOE_Read_Reg(SYSCFG1) & (~(0x3 << 14)); /* E_NOE_INTERFACE_RGMII_MODE */ ++ if (mode == E_NOE_INTERFACE_MII_MODE) ++ val = val | BIT(14); ++ else if (mode == E_NOE_INTERFACE_RMII_MODE) ++ val = val | BIT(15); ++ MHal_NOE_Write_Reg(SYSCFG1, val); ++ } ++} ++ ++void MHal_NOE_Init_Mii_Mgr(EN_NOE_GE_MAC ge, u32 phy_addr, unsigned char force_mode) ++{ ++ if (ge >= E_NOE_GE_MAC_MAX) { ++ return; ++ } ++ noe_config.mii_info[ge].noe_mii_force_mode = force_mode; ++ noe_config.mii_info[ge].phy_addr = phy_addr; ++ ++ if (ge == E_NOE_GE_MAC1) { ++ if ((noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY) || ++ (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_PM) || ++ (noe_config.pin_mux == E_NOE_SEL_PIN_MUX_GE1_TO_GPHY_GE2_TO_CHIPTOP)) { ++ _MHal_NOE_GPHY_Set_Addr(phy_addr); ++ MHal_NOE_GPHY_Write_Mii_Mgr((MS_U8)phy_addr&0xFF, GPHY_REG_BASIC, 0x1000); ++ MHal_NOE_GPHY_Get_Link_Info((MS_U8)phy_addr&0xFF); ++ printk(" Emma PHY \n"); ++ } ++ } ++} ++ ++ ++EN_NOE_RET MHal_NOE_LRO_Set_Ring_Cfg(EN_NOE_RING ring_no, unsigned int sip, unsigned int dip, unsigned int sport, unsigned int dport) ++{ ++ MS_U32 ring_idx; ++ if ((ring_no != E_NOE_RING_NO1) && ++ (ring_no != E_NOE_RING_NO2) && ++ (ring_no != E_NOE_RING_NO3)) { ++ ++ MHAL_NOE_DBG_INFO("invalid ring_no=%d\n", ring_no); ++ return E_NOE_RET_INVALID_PARAM; ++ } ++ ++ ++ if (ring_no == E_NOE_RING_NO1) ++ ring_idx = ADMA_RX_RING1; ++ else if (ring_no == E_NOE_RING_NO2) ++ ring_idx = ADMA_RX_RING2; ++ else if (ring_no == E_NOE_RING_NO3) ++ ring_idx = ADMA_RX_RING3; ++ ++ MHAL_NOE_DBG_INFO("set_fe_lro_ring%d_cfg()\n", ring_idx); ++ ++ /* 1. Set RX ring mode to force port */ ++ SET_PDMA_RXRING_MODE(ring_idx, PDMA_RX_FORCE_PORT); ++ ++ /* 2. Configure lro ring */ ++ /* 2.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ring_idx, sport); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ring_idx, dport); ++ /* 2.2 set src/destination IPs */ ++ if(ring_idx == E_NOE_RING_NO1) { ++ MHal_NOE_Write_Reg(LRO_RX_RING1_SIP_DW0, sip); ++ MHal_NOE_Write_Reg(LRO_RX_RING1_DIP_DW0, dip); ++ } ++ else if(ring_idx == E_NOE_RING_NO2) { ++ MHal_NOE_Write_Reg(LRO_RX_RING2_SIP_DW0, sip); ++ MHal_NOE_Write_Reg(LRO_RX_RING2_DIP_DW0, dip); ++ } ++ else if(ring_idx == E_NOE_RING_NO3) { ++ MHal_NOE_Write_Reg(LRO_RX_RING3_SIP_DW0, sip); ++ MHal_NOE_Write_Reg(LRO_RX_RING3_DIP_DW0, dip); ++ } ++ /* 2.3 IPv4 force port mode */ ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ring_idx, 1); ++ /* 2.4 IPv6 force port mode */ ++ SET_PDMA_RXRING_IPV6_FORCE_MODE(ring_idx, 1); ++ ++ /* 3. Set Age timer: 10 msec. */ ++ SET_PDMA_RXRING_AGE_TIME(ring_idx, HW_LRO_AGE_TIME); ++ ++ /* 4. Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ring_idx, 1); ++ ++ return E_NOE_RET_TRUE; ++} ++ ++ ++void MHal_NOE_LRO_Set_Cfg(void) ++{ ++ unsigned int reg_val = 0; ++ ++ MHAL_NOE_DBG_INFO("set_fe_lro_glo_cfg()\n"); ++ ++ /* 1 Set max AGG timer: 10 msec. */ ++ SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME); ++ ++ /* 2. Set max LRO agg count */ ++ SET_PDMA_LRO_MAX_AGG_CNT(HW_LRO_MAX_AGG_CNT); ++ ++ /* PDMA prefetch enable setting */ ++ SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN | ADMA_MULTI_RXD_PREFETCH_EN); ++ /* 2.1 IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3. Polling relinguish */ ++ while (1) { ++ if (MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) { ++ MHAL_NOE_DBG_INFO("Polling HW LRO RELINGUISH...\n"); ++ } ++ else ++ break; ++ } ++ ++ /* 4. Enable LRO */ ++ reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); ++ reg_val |= PDMA_LRO_EN; ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); ++} ++ ++ ++void MHal_NOE_LRO_Set_Ip(unsigned int lan_ip) ++{ ++ /* Set IP: LAN IP */ ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW0, lan_ip); ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW1, 0); ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW2, 0); ++ MHal_NOE_Write_Reg(LRO_RX_RING0_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(E_NOE_RING_NO0, 1); ++} ++ ++ ++void MHal_NOE_LRO_Set_Auto_Learn_Cfg(void) ++{ ++ unsigned int reg_val = 0; ++ ++ /* Set RX ring1~3 to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(E_NOE_RING_NO1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(E_NOE_RING_NO2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(E_NOE_RING_NO3, PDMA_RX_AUTO_LEARN); ++ ++ /* Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO0, 1); ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO1, 1); ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO2, 1); ++ SET_PDMA_RXRING_VALID(E_NOE_RING_NO3, 1); ++ ++ /* Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(E_NOE_RING_NO1, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(E_NOE_RING_NO2, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(E_NOE_RING_NO3, HW_LRO_AGE_TIME); ++ ++ /* Set max AGG timer */ ++ SET_PDMA_RXRING_AGG_TIME(E_NOE_RING_NO1, HW_LRO_AGG_TIME); ++ SET_PDMA_RXRING_AGG_TIME(E_NOE_RING_NO2, HW_LRO_AGG_TIME); ++ SET_PDMA_RXRING_AGG_TIME(E_NOE_RING_NO3, HW_LRO_AGG_TIME); ++ ++ /* Set max LRO agg count */ ++ SET_PDMA_RXRING_MAX_AGG_CNT(E_NOE_RING_NO1, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(E_NOE_RING_NO2, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(E_NOE_RING_NO3, HW_LRO_MAX_AGG_CNT); ++ ++ /* IPv6 LRO enable */ ++ SET_PDMA_LRO_IPV6_EN(1); ++ ++ /* IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* TCP push option check disable */ ++ /* SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(0); */ ++ /* PDMA prefetch enable setting */ ++ SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN | ADMA_MULTI_RXD_PREFETCH_EN); ++ /* switch priority comparison to packet count mode */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_PKT_CNT_MODE); ++ ++ /* bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(HW_LRO_BW_THRE); ++ ++ /* auto-learn score delta setting */ ++ MHal_NOE_Write_Reg(LRO_ALT_SCORE_DELTA, HW_LRO_REPLACE_DELTA); ++ ++ /* Set ALT timer to 20us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT); ++ /* Set ALT refresh timer to 1 sec. (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME); ++ ++ /* the least remaining room of SDL0 in RXD for lro aggregation */ ++ SET_PDMA_LRO_MIN_RXD_SDL(HW_LRO_SDL_REMAIN_ROOM); ++ ++ /* Polling relinguish */ ++ while (1) { ++ if (MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) { ++ MHAL_NOE_DBG_INFO("Polling HW LRO RELINGUISH...\n"); ++ } ++ else ++ break; ++ } ++ ++ /* Enable HW LRO */ ++ reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); ++ reg_val |= PDMA_LRO_EN; ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); ++ ++} ++ ++ ++ ++ ++void MHal_NOE_LRO_Update_Calc_Idx(MS_U32 ring_no, MS_U32 dma_owner_idx) ++{ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_RX_CALC_IDX0 + (ring_no << 4) , dma_owner_idx); ++} ++ ++ ++void MHal_NOE_LRO_Reset_Rx_Ring(EN_NOE_RING rx_ring_no, u32 phy_addr, u32 desc_num, u32 desc_idx) ++{ ++ if (rx_ring_no == E_NOE_RING_NO3) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR3, phy_addr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT3, desc_num); ++ MHal_NOE_Write_Reg(RX_CALC_IDX3, desc_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX3); ++ } ++ else if (rx_ring_no == E_NOE_RING_NO2) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR2, phy_addr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT2, desc_num); ++ MHal_NOE_Write_Reg(RX_CALC_IDX2, desc_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX2); ++ } ++ else if (rx_ring_no == E_NOE_RING_NO1) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR1, phy_addr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT1, desc_num); ++ MHal_NOE_Write_Reg(RX_CALC_IDX1, desc_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX1); ++ } ++} ++ ++ ++EN_NOE_RET MHal_NOE_LRO_Get_Ring_Info(EN_NOE_DMA dma, EN_NOE_DIR dir, EN_NOE_RING ring_no, struct noe_dma_info * info) ++{ ++ EN_NOE_RET ret = E_NOE_RET_FALSE; ++ if (E_NOE_DIR_TX == dir) { ++ if (dma & E_NOE_DMA_PACKET) { ++ if (ring_no == E_NOE_RING_NO0) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR0); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT0); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX0); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX0); ++ } ++ else if (ring_no == E_NOE_RING_NO1) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR1); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT1); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX1); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX1); ++ } ++ else if (ring_no == E_NOE_RING_NO2) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR2); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT2); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX2); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX2); ++ } ++ else if (ring_no == E_NOE_RING_NO3) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(TX_BASE_PTR3); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(TX_MAX_CNT3); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(TX_CTX_IDX3); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(TX_DTX_IDX3); ++ } ++ } ++ else if (dma & E_NOE_DMA_QUEUE) { ++ ret = E_NOE_RET_TRUE; ++ info->adr_st.ctx_adr = MHal_NOE_Read_Reg(QTX_CTX_PTR); ++ info->adr_st.dtx_adr = MHal_NOE_Read_Reg(QTX_DTX_PTR); ++ info->adr_st.crx_adr = MHal_NOE_Read_Reg(QTX_CRX_PTR); ++ info->adr_st.drx_adr = MHal_NOE_Read_Reg(QTX_DRX_PTR); ++ ++ } ++ } ++ else if (E_NOE_DIR_RX == dir){ ++ if (dma & E_NOE_DMA_PACKET) { ++ if (ring_no == E_NOE_RING_NO0) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR0); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT0); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX0); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX0); ++ } ++ else if (ring_no == E_NOE_RING_NO1) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR1); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT1); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX1); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX1); ++ } ++ else if (ring_no == E_NOE_RING_NO2) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR2); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT2); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX2); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX2); ++ } ++ else if (ring_no == E_NOE_RING_NO3) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(RX_BASE_PTR3); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(RX_MAX_CNT3); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(RX_CALC_IDX3); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(RX_DRX_IDX3); ++ } ++ } ++ else if (dma & E_NOE_DMA_QUEUE) { ++ if (ring_no == E_NOE_RING_NO0) { ++ ret = E_NOE_RET_TRUE; ++ info->ring_st.base_adr = MHal_NOE_Read_Reg(QRX_BASE_PTR_0); ++ info->ring_st.max_cnt = MHal_NOE_Read_Reg(QRX_MAX_CNT_0); ++ info->ring_st.cpu_idx = MHal_NOE_Read_Reg(QRX_CRX_IDX_0); ++ info->ring_st.dma_idx = MHal_NOE_Read_Reg(QRX_DRX_IDX_0); ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++ ++ ++void MHal_NOE_LRO_Get_Calc_Idx(struct noe_lro_calc_idx *calc_idx) ++{ ++ calc_idx->ring1 = MHal_NOE_Read_Reg(RX_CALC_IDX1); ++ calc_idx->ring2 = MHal_NOE_Read_Reg(RX_CALC_IDX2); ++ calc_idx->ring3 = MHal_NOE_Read_Reg(RX_CALC_IDX3); ++} ++ ++void MHal_NOE_Dump_Mii_Mgr(int port_no, int from, int to, int is_local, int page_no) ++{ ++/// do nothing ++} ++ ++ ++ ++void MHal_NOE_Init_Sep_Intr(EN_NOE_DMA dma, EN_NOE_DIR dir) ++{ ++ if (E_NOE_DIR_TX == dir) { ++ if (E_NOE_DMA_PACKET == dma) { ++ noe_config.intr_info.fe_tx_int_status = (void __iomem *)CONFIG_NOE_REG_FE_INT_STATUS; ++ noe_config.intr_info.fe_tx_int_enable = (void __iomem *)CONFIG_NOE_REG_FE_INT_ENABLE; ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ noe_config.intr_info.fe_tx_int_status = (void __iomem *)QFE_INT_STATUS; ++ noe_config.intr_info.fe_tx_int_enable = (void __iomem *)QFE_INT_ENABLE; ++ } ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ if (E_NOE_DMA_PACKET == dma) { ++ noe_config.intr_info.fe_rx_int_status = (void __iomem *)CONFIG_NOE_REG_FE_INT_STATUS; ++ noe_config.intr_info.fe_rx_int_enable = (void __iomem *)CONFIG_NOE_REG_FE_INT_ENABLE; ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ noe_config.intr_info.fe_rx_int_status = (void __iomem *)QFE_INT_STATUS; ++ noe_config.intr_info.fe_rx_int_enable = (void __iomem *)QFE_INT_ENABLE; ++ } ++ } ++} ++ ++ ++ ++MS_U8 MHal_NOE_Get_Sep_Intr_Status(EN_NOE_DIR dir) ++{ ++ unsigned int reg_int_val; ++ if (E_NOE_DIR_TX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_status); ++ if (reg_int_val & (TX_DLY_INT | TX_DONE_INT0)) { ++ return NOE_TRUE; ++ } ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_status); ++ if (reg_int_val & (RX_DLY_INT | RX_DONE_INT3 | RX_DONE_INT2 | RX_DONE_INT1 | RX_DONE_INT0)) { ++ return NOE_TRUE; ++ } ++ } ++ ++ return NOE_FALSE; ++} ++ ++void MHal_NOE_Clear_Sep_Intr_Status(EN_NOE_DIR dir) ++{ ++ if (E_NOE_DIR_TX == dir) { ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_status, (TX_DLY_INT | TX_DONE_INT0)); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_status, (RX_DLY_INT | RX_DONE_INT3 | RX_DONE_INT2 | RX_DONE_INT1 | RX_DONE_INT0)); ++ } ++} ++ ++void MHal_NOE_Clear_Sep_Intr_Specific_Status(EN_NOE_DIR dir, EN_NOE_INTR_CLR_STATUS status) ++{ ++ MS_U32 reg_int_val; ++ if (E_NOE_DIR_TX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_status); ++ if(status == E_NOE_INTR_CLR_EXCEPT_RX) { ++ reg_int_val &= ~(RX_DLY_INT | RX_DONE_INT2 | RX_DONE_INT3 | RX_DONE_INT1 | RX_DONE_INT0); ++ } ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_status, reg_int_val); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ reg_int_val = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_status); ++ if(status == E_NOE_INTR_CLR_EXCEPT_TX) { ++ reg_int_val &= ~(TX_DLY_INT | TX_DONE_INT0); ++ } ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_status, reg_int_val); ++ } ++} ++ ++void MHal_NOE_Enable_Sep_Intr(EN_NOE_DIR dir, EN_NOE_DELAY e_dly) ++{ ++ unsigned int reg_int_mask; ++ ++ if (E_NOE_DIR_TX == dir) { ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_enable); ++ if (e_dly == E_NOE_DLY_ONLY) ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, reg_int_mask | TX_DLY_INT); ++ else if (e_dly == E_NOE_DLY_DISABLE) ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, reg_int_mask | TX_DONE_INT0); ++ ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_enable); ++ if (e_dly == E_NOE_DLY_ONLY) ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, reg_int_mask | RX_DLY_INT); ++ else if (e_dly == E_NOE_DLY_DISABLE) ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, reg_int_mask | RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3); ++ } ++} ++ ++ ++void MHal_NOE_Disable_Sep_Intr(EN_NOE_DIR dir) ++{ ++ unsigned int reg_int_mask; ++ if (E_NOE_DIR_TX == dir) { ++ /* Disable TX interrupt */ ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_tx_int_enable); ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, reg_int_mask & ~(TX_DLY_INT | TX_DONE_INT0)); ++ } ++ else if (E_NOE_DIR_RX == dir) { ++ /* Disable RX interrupt */ ++ reg_int_mask = MHal_NOE_Read_Reg(noe_config.intr_info.fe_rx_int_enable); ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, reg_int_mask & ~(RX_DLY_INT | RX_DONE_INT2 | RX_DONE_INT3 | RX_DONE_INT1 | RX_DONE_INT0)); ++ } ++ else if (E_NOE_DIR_BOTH == dir) { ++ /* Disable TX interrupt */ ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_tx_int_enable, 0); ++ /* Disable RX interrupt */ ++ MHal_NOE_Write_Reg(noe_config.intr_info.fe_rx_int_enable, 0); ++ } ++} ++ ++ ++void MHal_NOE_Enable_Sep_Delay_Intr(EN_NOE_DMA dma, EN_NOE_DELAY delay_intr) ++{ ++ if (E_NOE_DMA_PACKET & dma) { ++ if(delay_intr == E_NOE_DLY_ONLY) { ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_DLY_INT_CFG, DELAY_INT_INIT); ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, FE_INT_DLY_INIT); ++ } ++ else{ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, FE_INT_ALL); ++ } ++ } ++ else if (E_NOE_DMA_QUEUE & dma){ ++ if(delay_intr == E_NOE_DLY_ONLY) { ++ MHal_NOE_Write_Reg(QDMA_DELAY_INT, DELAY_INT_INIT); ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, QFE_INT_DLY_INIT); ++ MHAL_NOE_DBG_INFO("[%s][%d] QFE_INT_ENABLE = %0X\n",__FUNCTION__,__LINE__, MHal_NOE_Read_Reg(QFE_INT_ENABLE)); ++ } ++ else { ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, QFE_INT_ALL); ++ MHAL_NOE_DBG_INFO("[%s][%d] QFE_INT_ENABLE = %0X\n",__FUNCTION__,__LINE__, MHal_NOE_Read_Reg(QFE_INT_ENABLE)); ++ } ++ } ++} ++ ++ ++void MHal_NOE_Set_Grp_Intr(unsigned char delay_intr) ++{ ++ if (delay_intr == NOE_TRUE) { ++ /* PDMA setting */ ++ MHal_NOE_Write_Reg(PDMA_INT_GRP1 /*NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x250*/ , TX_DLY_INT); ++ MHal_NOE_Write_Reg(PDMA_INT_GRP2 /*NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x254*/, RX_DLY_INT); ++ /* QDMA setting */ ++ MHal_NOE_Write_Reg(QDMA_INT_GRP1 /*NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220*/, RLS_DLY_INT); ++ MHal_NOE_Write_Reg(QDMA_INT_GRP2 /*NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224*/, RX_DLY_INT); ++ } ++ else { ++ /* PDMA setting */ ++ MHal_NOE_Write_Reg(PDMA_INT_GRP1 /*NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x250*/, TX_DONE_INT0); ++ MHal_NOE_Write_Reg(PDMA_INT_GRP2 /*NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x254*/, RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3); ++ /* QDMA setting */ ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, QFE_INT_ALL); ++ MHal_NOE_Write_Reg(QDMA_INT_GRP1/* NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220 */, RLS_DONE_INT); ++ MHal_NOE_Write_Reg(QDMA_INT_GRP2/* NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224 */, RX_DONE_INT0 | RX_DONE_INT1); ++ } ++ MHal_NOE_Write_Reg(FE_INT_GRP /* NOE_REG_FRAME_ENGINE_BASE + 0x20 */, 0x21021000); ++} ++ ++ ++ ++void MHal_NOE_Set_Vlan_Info(void) ++{ ++ /*VLAN_IDX 0 = VLAN_ID 0 ++ * ......... ++ * VLAN_IDX 15 = VLAN ID 15 ++ * ++ */ ++ /* frame engine will push VLAN tag ++ * regarding to VIDX feild in Tx desc. ++ */ ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xa8, 0x00010000); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xac, 0x00030002); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xb0, 0x00050004); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xb4, 0x00070006); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xb8, 0x00090008); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xbc, 0x000b000a); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xc0, 0x000d000c); ++ MHal_NOE_Write_Reg(NOE_REG_FRAME_ENGINE_BASE + 0xc4, 0x000f000e); ++} ++ ++ ++void MHal_NOE_Offoad_Checksum(EN_NOE_GE_MAC ge, unsigned char offload) ++{ ++ unsigned int reg_val, reg_csg; ++ unsigned int reg_val2 = 0; ++ ++ reg_csg = MHal_NOE_Read_Reg(CDMA_CSG_CFG); ++ reg_val = MHal_NOE_Read_Reg(GDMA1_FWD_CFG); ++ reg_val2 = MHal_NOE_Read_Reg(GDMA2_FWD_CFG); ++ if(ge == E_NOE_GE_MAC1) { ++ /* set unicast/multicast/broadcast frame to cpu */ ++ reg_val &= ~0xFFFF; ++ reg_val |= GDMA1_FWD_PORT; ++ reg_csg &= ~0x7; ++ if (offload == NOE_ENABLE) { ++ /* enable ipv4 header checksum check */ ++ reg_val |= GDM1_ICS_EN; ++ reg_csg |= ICS_GEN_EN; ++ ++ /* enable tcp checksum check */ ++ reg_val |= GDM1_TCS_EN; ++ reg_csg |= TCS_GEN_EN; ++ ++ /* enable udp checksum check */ ++ reg_val |= GDM1_UCS_EN; ++ reg_csg |= UCS_GEN_EN; ++ } ++ else { ++ /* disable ipv4 header checksum check */ ++ reg_val &= ~GDM1_ICS_EN; ++ reg_csg &= ~ICS_GEN_EN; ++ ++ /* disable tcp checksum check */ ++ reg_val &= ~GDM1_TCS_EN; ++ reg_csg &= ~TCS_GEN_EN; ++ ++ /* disable udp checksum check */ ++ reg_val &= ~GDM1_UCS_EN; ++ reg_csg &= ~UCS_GEN_EN; ++ } ++ MHal_NOE_Write_Reg(GDMA1_FWD_CFG, reg_val); ++ MHal_NOE_Write_Reg(CDMA_CSG_CFG, reg_csg); ++ } ++ else if(ge == E_NOE_GE_MAC2) { ++ ++ if (offload == NOE_ENABLE) { ++ reg_val2 &= ~0xFFFF; ++ reg_val2 |= GDMA2_FWD_PORT; ++ reg_val2 |= GDM1_ICS_EN; ++ reg_val2 |= GDM1_TCS_EN; ++ reg_val2 |= GDM1_UCS_EN; ++ } ++ else { ++ reg_val2 &= ~GDM1_ICS_EN; ++ reg_val2 &= ~GDM1_TCS_EN; ++ reg_val2 &= ~GDM1_UCS_EN; ++ } ++ MHal_NOE_Write_Reg(GDMA2_FWD_CFG, reg_val2); ++ } ++} ++ ++ ++void MHal_NOE_GLO_Reset(void) ++{ ++ /*FE_RST_GLO register definition - ++ *Bit 0: PSE Rest ++ *Reset PSE after re-programming PSE_FQ_CFG. ++ */ ++ MS_U32 reg_val = 0x1; ++ MHal_NOE_Write_Reg(FE_RST_GL, reg_val); ++ MHal_NOE_Write_Reg(FE_RST_GL, 0); /* update for RSTCTL issue */ ++ ++ MHAL_NOE_DBG_INFO("CDMA_CSG_CFG = %0X\n", MHal_NOE_Read_Reg(CDMA_CSG_CFG)); ++ MHAL_NOE_DBG_INFO("GDMA1_FWD_CFG = %0X\n", MHal_NOE_Read_Reg(GDMA1_FWD_CFG)); ++ MHAL_NOE_DBG_INFO("GDMA2_FWD_CFG = %0X\n", MHal_NOE_Read_Reg(GDMA2_FWD_CFG)); ++} ++ ++ ++void MHal_NOE_LRO_Set_Prefetch(void) ++{ ++ /* enable RXD prefetch of ADMA */ ++ unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); ++ reg_val &= ~PDMA_LRO_RXD_PREFETCH_EN; ++ reg_val |= (ADMA_RXD_PREFETCH_EN | ADMA_MULTI_RXD_PREFETCH_EN); ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); ++ MHAL_NOE_DBG_INFO("[%s][%d]ADMA_LRO_CTRL_DW0=0x%X\n",__FUNCTION__,__LINE__,MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0)); ++} ++ ++EN_NOE_RET MHal_NOE_Dma_Is_Idle(EN_NOE_DMA dma) ++{ ++ unsigned int reg_val, loop_cnt = 0; ++ void __iomem *phy_adr = PDMA_GLO_CFG; ++ ++ MHAL_NOE_DBG_INFO("[%s][%d]dma = 0x%x \n",__FUNCTION__,__LINE__,dma); ++ if (E_NOE_DMA_PACKET & dma) { ++ phy_adr = PDMA_GLO_CFG; ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ phy_adr = QDMA_GLO_CFG; ++ } ++ else { ++ return E_NOE_RET_FALSE; ++ } ++ while (1) { ++ if (loop_cnt++ > NOE_WAIT_IDLE_THRESHOLD) ++ break; ++ reg_val = MHal_NOE_Read_Reg(phy_adr); ++ if ((reg_val & RX_DMA_BUSY)) { ++ MHAL_NOE_DBG_INFO("\n RX_DMA_BUSY !!! "); ++ continue; ++ } ++ if ((reg_val & TX_DMA_BUSY)) { ++ MHAL_NOE_DBG_INFO("\n TX_DMA_BUSY !!! "); ++ continue; ++ } ++ return E_NOE_RET_TRUE; ++ } ++ return E_NOE_RET_FALSE; ++} ++ ++void MHal_NOE_Dma_Init_Global_Config(EN_NOE_DMA dma) ++{ ++ unsigned int reg_val; ++ if (E_NOE_DMA_PACKET == dma) { ++ reg_val = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS | MULTI_EN | ADMA_RX_BT_SIZE_32DWORDS); ++ reg_val |= (RX_2B_OFFSET); ++ MHal_NOE_Write_Reg(PDMA_GLO_CFG, reg_val); ++ MHAL_NOE_DBG_INFO("[%s][%d]PDMA_GLO_CFG=0x%x\n",__FUNCTION__,__LINE__,MHal_NOE_Read_Reg(PDMA_GLO_CFG)); ++ } ++ else if (E_NOE_DMA_QUEUE & dma) { ++ reg_val = MHal_NOE_Read_Reg(QDMA_GLO_CFG); ++ reg_val &= 0x000000FF; ++ ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, reg_val); ++ reg_val = MHal_NOE_Read_Reg(QDMA_GLO_CFG); ++ ++ /* Enable randon early drop and set drop threshold automatically */ ++ if (E_NOE_DMA_QUEUE_WITH_SFQ != dma) ++ MHal_NOE_Write_Reg(QDMA_FC_THRES, 0x174444); ++ ++ MHal_NOE_Write_Reg(QDMA_HRED2, 0x0); ++ ++ reg_val = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS); ++ reg_val |= (RX_2B_OFFSET); ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, reg_val); ++ ++ MHAL_NOE_DBG_INFO("Enable QDMA TX NDP coherence check and re-read mechanism\n"); ++ reg_val = MHal_NOE_Read_Reg(QDMA_GLO_CFG); ++ reg_val = reg_val | 0x400 | 0x100000; ++ MHal_NOE_Write_Reg(QDMA_GLO_CFG, reg_val); ++ MHAL_NOE_DBG_INFO("***********QDMA_GLO_CFG=0x%x\n", MHal_NOE_Read_Reg(QDMA_GLO_CFG)); ++ } ++} ++ ++void MHal_NOE_DMA_Init(EN_NOE_DMA dma, EN_NOE_DIR dir, EN_NOE_RING ring_no, struct noe_dma_info *dma_info) ++{ ++ int i = 0; ++ int page, queue; ++ ++ MHAL_NOE_DBG_INFO("dma,dir = 0x%0X,0x%0X \n",dma,dir); ++ if ((dma & E_NOE_DMA_QUEUE) && (dir == E_NOE_DIR_TX)) { ++ MHAL_NOE_DBG_INFO("ctx = 0x%0X \n",(MS_U32) dma_info->adr_st.ctx_adr); ++ MHAL_NOE_DBG_INFO("dtx = 0x%0X \n",(MS_U32) dma_info->adr_st.dtx_adr); ++ MHAL_NOE_DBG_INFO("crx = 0x%0X \n",(MS_U32) dma_info->adr_st.crx_adr); ++ MHAL_NOE_DBG_INFO("drx = 0x%0X \n",(MS_U32) dma_info->adr_st.drx_adr); ++ } ++ else { ++ MHAL_NOE_DBG_INFO("base_adr = 0x%0X\n",(MS_U32)dma_info->ring_st.base_adr); ++ MHAL_NOE_DBG_INFO("max_cnt = 0x%0X\n",dma_info->ring_st.max_cnt); ++ MHAL_NOE_DBG_INFO("cpu_idx = 0x%0X \n\n",dma_info->ring_st.cpu_idx); ++ } ++ ++ ++ if(dma & E_NOE_DMA_PACKET) { ++ if (dir == E_NOE_DIR_RX) { ++ if (ring_no == E_NOE_RING_NO0) { ++ /* Tell the adapter where the RX rings are located. */ ++ MHal_NOE_Write_Reg(RX_BASE_PTR0, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT0, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX0, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX0); ++ } ++ else if (ring_no == E_NOE_RING_NO3) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR3, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT3, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX3, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX3); ++ } ++ else if (ring_no == E_NOE_RING_NO2) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR2, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT2, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX2, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX2); ++ } ++ else if (ring_no == E_NOE_RING_NO1) { ++ MHal_NOE_Write_Reg(RX_BASE_PTR1, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(RX_MAX_CNT1, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(RX_CALC_IDX1, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DRX_IDX1); ++ } ++ } ++ else if (dir == E_NOE_DIR_TX) { ++ /* Tell the adapter where the TX rings are located. */ ++ MHal_NOE_Write_Reg(TX_BASE_PTR0, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(TX_MAX_CNT0, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(TX_CTX_IDX0, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(PDMA_RST_CFG, PST_DTX_IDX0); ++ } ++ } ++ else if(dma & E_NOE_DMA_QUEUE) { ++ if (dir == E_NOE_DIR_RX) { ++ /* Tell the adapter where the RX rings are located. */ ++ MHal_NOE_Write_Reg(QRX_BASE_PTR_0, dma_info->ring_st.base_adr); ++ MHal_NOE_Write_Reg(QRX_MAX_CNT_0, dma_info->ring_st.max_cnt); ++ MHal_NOE_Write_Reg(QRX_CRX_IDX_0, dma_info->ring_st.cpu_idx); ++ MHal_NOE_Write_Reg(QDMA_RST_CFG, PST_DRX_IDX0); ++ } ++ else if (dir == E_NOE_DIR_TX) { ++ MHal_NOE_Write_Reg(QTX_CTX_PTR, dma_info->adr_st.ctx_adr); ++ MHal_NOE_Write_Reg(QTX_DTX_PTR, dma_info->adr_st.dtx_adr); ++ MHal_NOE_Write_Reg(QTX_CRX_PTR, dma_info->adr_st.crx_adr); ++ MHal_NOE_Write_Reg(QTX_DRX_PTR, dma_info->adr_st.drx_adr); ++ ++ for (i = 0; i < NUM_PQ; i++) { ++ page = i / QUEUE_OFFSET; ++ queue = i & (QUEUE_OFFSET - 1); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page); ++ MHal_NOE_Write_Reg(QTX_CFG_0 + QUEUE_OFFSET * queue, (NUM_PQ_RESV | (NUM_PQ_RESV << 8))); ++ } ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ } ++ } ++} ++ ++ ++ ++void MHal_NOE_Get_Intr_Info(struct noe_intr_info *info) ++{ ++ info->fe_intr_enable = MHal_NOE_Read_Reg(FE_INT_ENABLE); ++ info->fe_intr_mask = MHal_NOE_Read_Reg(INT_MASK); ++ info->fe_intr_status = MHal_NOE_Read_Reg(FE_INT_STATUS); ++ info->delay_intr_cfg = MHal_NOE_Read_Reg(DLY_INT_CFG); ++ info->qfe_intr_enable = MHal_NOE_Read_Reg(QFE_INT_ENABLE); ++ info->qfe_intr_mask = MHal_NOE_Read_Reg(QDMA_INT_MASK); ++ info->qfe_intr_status = MHal_NOE_Read_Reg(QFE_INT_STATUS); ++} ++ ++ ++ ++void MHal_NOE_Get_Mac_Info(EN_NOE_GE_MAC ge, struct noe_mac_info *info) ++{ ++ void __iomem *reg_base; ++ ++ if(ge == E_NOE_GE_MAC1) { ++ reg_base = NOE_REG_FRAME_ENGINE_BASE + 0x2400; ++ info->stat.control = MHal_NOE_Read_Reg(NOE_MAC_P1_MCR); ++ info->stat.status = MHal_NOE_Read_Reg(NOE_MAC_P1_SR); ++ } ++ else if (ge == E_NOE_GE_MAC2) { ++ reg_base = NOE_REG_FRAME_ENGINE_BASE + 0x2440; ++ info->stat.control = MHal_NOE_Read_Reg(NOE_MAC_P2_MCR); ++ info->stat.status = MHal_NOE_Read_Reg(NOE_MAC_P2_SR); ++ } ++ else ++ return; ++ ++ info->rx.good_cnt = MHal_NOE_Read_Reg(reg_base); ++ info->rx.good_pkt = MHal_NOE_Read_Reg(reg_base + 0x08); ++ info->rx.overflow_err = MHal_NOE_Read_Reg(reg_base + 0x10); ++ info->rx.fcs_err = MHal_NOE_Read_Reg(reg_base + 0x14); ++ info->rx.ser_cnt = MHal_NOE_Read_Reg(reg_base + 0x18); ++ info->rx.ler_pkt = MHal_NOE_Read_Reg(reg_base + 0x1C); ++ info->rx.chk_err = MHal_NOE_Read_Reg(reg_base + 0x20); ++ info->rx.flow_ctrl = MHal_NOE_Read_Reg(reg_base + 0x24); ++ ++ info->tx.skip_cnt = MHal_NOE_Read_Reg(reg_base + 0x28); ++ info->tx.collision_cnt = MHal_NOE_Read_Reg(reg_base + 0x2C); ++ info->tx.good_cnt = MHal_NOE_Read_Reg(reg_base + 0x30); ++ info->tx.good_pkt = MHal_NOE_Read_Reg(reg_base + 0x38); ++} ++ ++void MHal_NOE_Get_Pse_Info(struct noe_pse_info *info) ++{ ++ info->min_free_cnt = (MHal_NOE_Read_Reg(FE_PSE_FREE) & 0xff0000) >> 16; ++ info->free_cnt = MHal_NOE_Read_Reg(FE_PSE_FREE) & 0x00ff; ++ info->fq_drop_cnt = MHal_NOE_Read_Reg(FE_DROP_FQ); ++ info->fc_drop_cnt = MHal_NOE_Read_Reg(FE_DROP_FC); ++ info->ppe_drop_cnt = MHal_NOE_Read_Reg(FE_DROP_PPE); ++} ++ ++static void _MHal_NOE_PDMA_Get_Dbg(void *dbg_info) ++{ ++ struct noe_pdma_dbg *info = (struct noe_pdma_dbg *)dbg_info; ++ info->rx[0] = MHal_NOE_Read_Reg(INT_MASK + 0x10); ++ info->rx[1] = MHal_NOE_Read_Reg(INT_MASK + 0x14); ++ info->tx[0] = MHal_NOE_Read_Reg(INT_MASK + 0x8); ++ info->tx[1] = MHal_NOE_Read_Reg(INT_MASK + 0xC); ++} ++ ++ ++static void _MHal_NOE_QDMA_Get_Cnt(void *cnt_info) ++{ ++ struct noe_qdma_cnt *info = (struct noe_qdma_cnt *) cnt_info; ++ unsigned int page_no = 0, queue_no = 0; ++ if (queue_no >= NUM_PQ) ++ return; ++ ++ page_no = info->pq_no / QUEUE_OFFSET; ++ queue_no = info->pq_no & (QUEUE_OFFSET - 1); ++ ++ MHal_NOE_Write_Reg(QTX_MIB_IF, 0x90000000); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page_no); ++ info->pkt_cnt = MHal_NOE_Read_Reg(QTX_CFG_0 + queue_no * QUEUE_OFFSET); ++ info->drop_cnt = MHal_NOE_Read_Reg(QTX_SCH_0 + queue_no * QUEUE_OFFSET); ++ ++ MHal_NOE_Write_Reg(QDMA_PAGE, 0); ++ MHal_NOE_Write_Reg(QTX_MIB_IF, 0x0); ++} ++ ++static void _MHal_NOE_QDMA_Get_Fq(void *fq_info) ++{ ++ struct noe_qdma_fq *info = (struct noe_qdma_fq *) fq_info; ++ info->sw_fq = (MHal_NOE_Read_Reg(QDMA_FQ_CNT) & 0xFFFF0000) >> 16; ++ info->hw_fq = MHal_NOE_Read_Reg(QDMA_FQ_CNT) & 0x0000FFFF; ++} ++ ++static void _MHal_NOE_QDMA_Get_Sch(void *rate_info) ++{ ++ struct noe_qdma_sch *info = (struct noe_qdma_sch *) rate_info; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_TX_SCH); ++ unsigned int max_rate, i; ++ info->sch[0].max_en = (temp & 0x00000800) >> 11; ++ max_rate = (temp & 0x000007F0) >> 4; ++ for (i = 0; i < (temp & 0x0000000F); i++) ++ max_rate *= 10; ++ info->sch[0].max_rate = max_rate; ++ ++ info->sch[1].max_en = (temp & 0x08000000) >> 27; ++ max_rate = (temp & 0x07F00000) >> 20; ++ for (i = 0; i < (temp & 0x000F0000); i++) ++ max_rate *= 10; ++ info->sch[1].max_rate = max_rate; ++} ++ ++static void _MHal_NOE_QDMA_Get_Fc(void *fc_info) ++{ ++ struct noe_qdma_fc *info = (struct noe_qdma_fc *) fc_info; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_FC_THRES); ++ info->sw.en = (temp & 0x1000000) >> 24; ++ info->sw.ffa = (temp & 0x200000) >> 25; ++ info->sw.mode = (temp & 0x30000000) >> 28; ++ info->sw.fst_vq_en = (temp & 0x08000000) >> 27; ++ info->sw.fst_vq_mode = (temp & 0xC0000000) >> 30; ++ info->hw.en = (temp & 0x10000) >> 16; ++ info->hw.ffa = (temp & 0x2000) >> 17; ++ info->hw.mode = (temp & 0x300000) >> 20; ++ info->hw.fst_vq_en = (temp & 0x080000) >> 19; ++ info->hw.fst_vq_mode = (temp & 0xC00000) >> 22; ++} ++ ++static void _MHal_NOE_QDMA_Get_Fsm(void *fsm_info) ++{ ++ struct noe_qdma_fsm *info = (struct noe_qdma_fsm *) fsm_info; ++ unsigned int temp = MHal_NOE_Read_Reg(QDMA_DMA); ++ info->vqtb = (temp & 0x0F000000) >> 24; ++ info->fq = (temp & 0x000F0000) >> 16; ++ info->tx = (temp & 0x00000F00) >> 8; ++ info->rx = temp & 0x0000001F; ++ temp = MHal_NOE_Read_Reg(QDMA_BMU); ++ info->rls = (temp & 0x07FF0000) >> 16; ++ info->fwd = temp & 0x00007FFF; ++} ++ ++static void _MHal_NOE_QDMA_Get_Vq(void *vq_info) ++{ ++ struct noe_qdma_vq *info = (struct noe_qdma_vq *) vq_info; ++ unsigned int temp = MHal_NOE_Read_Reg(VQTX_NUM); ++ info->vq_num[E_NOE_VQ_NO0]=temp & 0xF; ++ info->vq_num[E_NOE_VQ_NO1]=(temp & 0xF0) >> 4; ++ info->vq_num[E_NOE_VQ_NO2]=(temp & 0xF00) >> 8; ++ info->vq_num[E_NOE_VQ_NO3]=(temp & 0xF000) >> 12; ++} ++ ++static void _MHal_NOE_QDMA_Get_Pq(void *pq_info) ++{ ++ struct noe_qdma_pq *info = (struct noe_qdma_pq *) pq_info; ++ unsigned int temp, i, rate, queue; ++ queue = info->queue; ++ temp = MHal_NOE_Read_Reg(QTX_CFG_0 + QUEUE_OFFSET * queue); ++ info->txd_cnt = (temp & 0xffff0000) >> 16; ++ info->hw_resv = (temp & 0xff00) >> 8; ++ info->sw_resv = (temp & 0xff); ++ temp = MHal_NOE_Read_Reg(QTX_CFG_0 + (QUEUE_OFFSET * queue) + 0x4); ++ info->sch = (temp >> 31) + 1; ++ info->min_en = (temp & 0x8000000) >> 27; ++ rate = (temp & 0x7f00000) >> 20; ++ for (i = 0; i < (temp & 0xf0000) >> 16; i++) ++ rate *= 10; ++ info->min_rate = rate; ++ info->max_en = (temp & 0x800) >> 11; ++ rate = (temp & 0x7f0) >> 4; ++ for (i = 0; i < (temp & 0xf); i++) ++ rate *= 10; ++ info->max_rate = rate; ++ info->weight = (temp & 0xf000) >> 12; ++ info->queue_head = MHal_NOE_Read_Reg(QTX_HEAD_0 + 0x10 * queue); ++ info->queue_tail = MHal_NOE_Read_Reg(QTX_TAIL_0 + 0x10 * queue); ++} ++ ++void MHal_NOE_Get_Qdma_Info(EN_NOE_QDMA_INFO_TYPE type, void *info) ++{ ++ if ((type >= E_NOE_QDMA_INFO_MAX) || (_mhal_noe_qdma_get_info_pfn[type] == NULL)) ++ return; ++ _mhal_noe_qdma_get_info_pfn[type](info); ++} ++ ++ ++void MHal_NOE_IO_Enable_Coherence(void) ++{ ++ MS_U32 reg_val = MHal_NOE_Read_Reg(REG_NOE_IOC_ETH); ++ reg_val |= IOC_ETH_PDMA | IOC_ETH_QDMA; ++ MHal_NOE_Write_Reg(REG_NOE_IOC_ETH, reg_val); ++} ++ ++ ++ ++void MHal_NOE_MAC_Enable_Link_Intr(EN_NOE_GE_MAC ge) ++{ ++ MS_U32 val; ++ val = MHal_NOE_Read_Reg(FE_INT_ENABLE2); ++ if (ge == E_NOE_GE_MAC1) { ++ val = val | (1 << 24); ++ } ++ else if (ge == E_NOE_GE_MAC2) { ++ val = val | (1 << 25); ++ } ++ MHal_NOE_Write_Reg(FE_INT_ENABLE2, val); ++} ++ ++ ++void MHal_NOE_DMA_Update_Calc_Idx(EN_NOE_DIR dir, MS_U32 owner_idx) ++{ ++ if (dir == E_NOE_DIR_RX) ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_RX_CALC_IDX0, owner_idx); ++ else if (dir == E_NOE_DIR_TX) ++ MHal_NOE_Write_Reg(TX_CTX_IDX0, owner_idx); ++} ++ ++MS_U32 MHal_NOE_DMA_Get_Calc_Idx(EN_NOE_DIR dir) ++{ ++ if (dir == E_NOE_DIR_RX) ++ return MHal_NOE_Read_Reg(CONFIG_NOE_REG_RX_CALC_IDX0); ++ else if (dir == E_NOE_DIR_TX) ++ return MHal_NOE_Read_Reg(TX_CTX_IDX0); ++ return NOE_INVALID_CALC_IDX; ++} ++ ++ ++void MHal_NOE_Get_Intr_Status(EN_NOE_DMA dma, MS_BOOL dly, MS_U32 *recv, MS_U32 *xmit) ++{ ++ MS_U32 reg_int_val; ++ noe_config.intr_info.reg_int_val_q = 0; ++ noe_config.intr_info.reg_int_val_p = MHal_NOE_Read_Reg(CONFIG_NOE_REG_FE_INT_STATUS); ++ if (dma & E_NOE_DMA_QUEUE) { ++ noe_config.intr_info.reg_int_val_q = MHal_NOE_Read_Reg(QFE_INT_STATUS); ++ if (MHal_NOE_Read_Reg(QFE_INT_STATUS) != 0) ++ MHAL_NOE_INTR_INFO("QQ.STATUS = 0x%08x \n", MHal_NOE_Read_Reg(QFE_INT_STATUS)); ++ } ++ reg_int_val = noe_config.intr_info.reg_int_val_p | noe_config.intr_info.reg_int_val_q; ++ if (dly == NOE_TRUE) { ++ if ((reg_int_val & RX_DLY_INT)) ++ *recv = 1; ++ if (reg_int_val & CONFIG_NOE_REG_TX_DLY_INT) ++ *xmit = 1; ++ } ++ else { ++ if ((reg_int_val & (RX_DONE_INT0 | RX_DONE_INT3 | RX_DONE_INT2 | RX_DONE_INT1))) ++ *recv = 1; ++ if (reg_int_val & CONFIG_NOE_REG_TX_DONE_INT0) ++ *xmit |= CONFIG_NOE_REG_TX_DONE_INT0; ++ } ++} ++ ++void MHal_NOE_Clear_Intr_Status(EN_NOE_DMA dma) ++{ ++ ++ if (MHal_NOE_Read_Reg(QFE_INT_STATUS) != 0) ++ MHAL_NOE_INTR_INFO("0.STATUS = 0x%08x \n", MHal_NOE_Read_Reg(QFE_INT_STATUS)); ++ /* Clear Interrupt */ ++ if (dma & E_NOE_DMA_QUEUE) { ++ MHal_NOE_Write_Reg(QFE_INT_STATUS, noe_config.intr_info.reg_int_val_q); ++ } ++ /* QWERT */ ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_STATUS, noe_config.intr_info.reg_int_val_p); ++} ++ ++ ++void MHal_NOE_Enable_Intr_Status(EN_NOE_DMA dma, MS_BOOL dly) ++{ ++ MS_U32 reg_int_mask; ++ reg_int_mask = MHal_NOE_Read_Reg(CONFIG_NOE_REG_FE_INT_ENABLE); ++ if (dly == NOE_TRUE) ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT)); ++ else ++ MHal_NOE_Write_Reg(CONFIG_NOE_REG_FE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)); ++ ++ if (dma & E_NOE_DMA_QUEUE) { ++ reg_int_mask = MHal_NOE_Read_Reg(QFE_INT_ENABLE); ++ //MHAL_NOE_DBG_INFO("[%s][%d] dly=%d, QFE_INT_ENABLE = %0X\n",__FUNCTION__,__LINE__, dly, MHal_NOE_Read_Reg(QFE_INT_ENABLE)); ++ ++ if (dly == NOE_TRUE) ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT)); ++ else ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)); ++ } ++ ++} ++ ++void MHal_NOE_MAC_Get_Link_Status(EN_NOE_GE_MAC ge, struct noe_mac_link_status *link_status) ++{ ++ ++ ++} ++ ++EN_NOE_RET MHal_NOE_Need_Reset(void) ++{ ++ unsigned int val_1, val_2, info; ++ unsigned int tmp[4]; ++ val_1 = MHal_NOE_Read_Reg(NOE_REG_SYSCTL_BASE); ++ val_2 = MHal_NOE_Read_Reg(NOE_REG_SYSCTL_BASE + 4); ++ tmp[3] = ((val_1 >> 16) & 0xff) - 0x30; ++ tmp[2] = ((val_1 >> 24) & 0xff) - 0x30; ++ tmp[1] = ((val_2 >> 0) & 0xff) - 0x30; ++ tmp[0] = ((val_2 >> 8) & 0xff) - 0x30; ++ info = (tmp[3] * 1000) + (tmp[2] * 100) + (tmp[1] * 10) + tmp[0]; ++ /* reset is not necessary */ ++ return E_NOE_RET_FALSE; ++} ++ ++static void _MHal_NOE_FE_Reset(void) ++{ ++ MS_U32 adma_rx_dbg0_r = 0; ++ MS_U32 dbg_rx_curr_state, rx_fifo_wcnt; ++ MS_U32 dbg_cdm_lro_rinf_afifo_rempty, dbg_cdm_eof_rdy_afifo_empty; ++ MS_U32 reg_tmp, loop_count; ++ ++ /* do CDM/PDMA reset */ ++ reg_tmp = MHal_NOE_Read_Reg(FE_GLO_MISC); ++ MHal_NOE_Write_Reg(FE_GLO_MISC, reg_tmp | reg_tmp); ++ //mdelay(10); ++ reg_tmp = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW3); ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW3, reg_tmp | (0x1 << 14)); ++ loop_count = 0; ++ do { ++ adma_rx_dbg0_r = MHal_NOE_Read_Reg(ADMA_RX_DBG0); ++ dbg_rx_curr_state = (adma_rx_dbg0_r >> 16) & 0x7f; ++ rx_fifo_wcnt = (adma_rx_dbg0_r >> 8) & 0x3f; ++ dbg_cdm_lro_rinf_afifo_rempty = (adma_rx_dbg0_r >> 7) & 0x1; ++ dbg_cdm_eof_rdy_afifo_empty = (adma_rx_dbg0_r >> 6) & 0x1; ++ loop_count++; ++ if (loop_count >= 100) { ++ MHAL_NOE_DBG_INFO("[%s] loop_count timeout!!!\n", __func__); ++ break; ++ } ++ //mdelay(10); ++ } while (((dbg_rx_curr_state != 0x17) && (dbg_rx_curr_state != 0x00)) || (rx_fifo_wcnt != 0) || (!dbg_cdm_lro_rinf_afifo_rempty) || (!dbg_cdm_eof_rdy_afifo_empty)); ++ reg_tmp = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW3); ++ MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW3, reg_tmp & 0xffffbfff); ++ reg_tmp = MHal_NOE_Read_Reg(FE_GLO_MISC); ++ MHal_NOE_Write_Reg(FE_GLO_MISC, reg_tmp & 0xfffffffe); ++ ++} ++ ++void MHal_NOE_Do_Reset(void) ++{ ++ ++ MS_U32 adma_rx_dbg0_r = 0; ++ MS_U32 dbg_rx_curr_state, rx_fifo_wcnt; ++ MS_U32 dbg_cdm_lro_rinf_afifo_rempty, dbg_cdm_eof_rdy_afifo_empty; ++ ++ adma_rx_dbg0_r = MHal_NOE_Read_Reg(ADMA_RX_DBG0); ++ dbg_rx_curr_state = (adma_rx_dbg0_r >> 16) & 0x7f; ++ rx_fifo_wcnt = (adma_rx_dbg0_r >> 8) & 0x3f; ++ dbg_cdm_lro_rinf_afifo_rempty = (adma_rx_dbg0_r >> 7) & 0x1; ++ dbg_cdm_eof_rdy_afifo_empty = (adma_rx_dbg0_r >> 6) & 0x1; ++ ++ /* check if PSE P0 hang */ ++ if (dbg_cdm_lro_rinf_afifo_rempty && dbg_cdm_eof_rdy_afifo_empty && (rx_fifo_wcnt & 0x20) && ((dbg_rx_curr_state == 0x17) || (dbg_rx_curr_state == 0x00))) { ++ _MHal_NOE_FE_Reset(); ++ } ++} ++ ++ ++void MHal_NOE_DMA_SFQ_Init(struct noe_sfq_base *adr_info) ++{ ++ MS_U32 reg_val; ++ reg_val = MHal_NOE_Read_Reg(VQTX_GLO); ++ reg_val = reg_val | VQTX_MIB_EN; ++ /* Virtual table extends to 32bytes */ ++ MHal_NOE_Write_Reg(VQTX_GLO, reg_val); ++ reg_val = MHal_NOE_Read_Reg(VQTX_GLO); ++ MHal_NOE_Write_Reg(VQTX_NUM, (VQTX_NUM_0) | (VQTX_NUM_1) | (VQTX_NUM_2) | (VQTX_NUM_3) | (VQTX_NUM_4) | (VQTX_NUM_5) | (VQTX_NUM_6) | (VQTX_NUM_7)); ++ ++ /* 10 s change hash algorithm */ ++ MHal_NOE_Write_Reg(VQTX_HASH_CFG, 0xF002710); ++ MHal_NOE_Write_Reg(VQTX_VLD_CFG, 0xeca86420); ++ MHal_NOE_Write_Reg(VQTX_HASH_SD, 0x0D); ++ MHal_NOE_Write_Reg(QDMA_FC_THRES, 0x9b9b4444); ++ MHal_NOE_Write_Reg(QDMA_HRED1, 0); ++ MHal_NOE_Write_Reg(QDMA_HRED2, 0); ++ MHal_NOE_Write_Reg(QDMA_SRED1, 0); ++ MHal_NOE_Write_Reg(QDMA_SRED2, 0); ++ MHal_NOE_Write_Reg(VQTX_0_3_BIND_QID, (VQTX_0_BIND_QID) | (VQTX_1_BIND_QID) | (VQTX_2_BIND_QID) | (VQTX_3_BIND_QID)); ++ MHal_NOE_Write_Reg(VQTX_4_7_BIND_QID, (VQTX_4_BIND_QID) | (VQTX_5_BIND_QID) | (VQTX_6_BIND_QID) | (VQTX_7_BIND_QID)); ++ MHAL_NOE_DBG_INFO("VQTX_0_3_BIND_QID =%x\n", MHal_NOE_Read_Reg(VQTX_0_3_BIND_QID)); ++ MHAL_NOE_DBG_INFO("VQTX_4_7_BIND_QID =%x\n", MHal_NOE_Read_Reg(VQTX_4_7_BIND_QID)); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE0, (MS_U32)adr_info->phy_adr[0]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE1, (MS_U32)adr_info->phy_adr[1]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE2, (MS_U32)adr_info->phy_adr[2]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE3, (MS_U32)adr_info->phy_adr[3]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE4, (MS_U32)adr_info->phy_adr[4]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE5, (MS_U32)adr_info->phy_adr[5]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE6, (MS_U32)adr_info->phy_adr[6]); ++ MHal_NOE_Write_Reg(VQTX_TB_BASE7, (MS_U32)adr_info->phy_adr[7]); ++} ++ ++MS_U32 MHal_NOE_DMA_Get_Queue_Cfg(MS_U32 pq_no) ++{ ++#if 1 ++ #define _HQOS_REG(x) (*((volatile u32 *)(NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + x))) ++ return _HQOS_REG(pq_no); ++ ++#else ++ ++ ++ int page_no = 0, queue_no = 0; ++ ++ if (pq_no >= NUM_PQ) ++ return 0; ++ ++ page_no = pq_no / QUEUE_OFFSET; ++ queue_no = pq_no & (QUEUE_OFFSET - 1); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page_no); ++ return MHal_NOE_Read_Reg(QTX_CFG_0 + queue_no * QUEUE_OFFSET); ++#endif ++ ++} ++ ++void MHal_NOE_DMA_Set_Queue_Cfg(MS_U32 pq_no, MS_U32 cfg) ++{ ++ ++#if 1 ++ #define _HQOS_REG(x) (*((volatile u32 *)(NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + x))) ++ _HQOS_REG(pq_no) = cfg; ++ MHAL_NOE_DBG_INFO(" 0x%x = 0x%x\n", QDMA_RELATED + pq_no, cfg); ++#else ++ int page = 0, queue = 0; ++ ++ if (pq_no >= NUM_PQ) ++ return ; ++ ++ page = pq_no / QUEUE_OFFSET; ++ queue = pq_no & (QUEUE_OFFSET - 1); ++ MHAL_NOE_DBG_INFO("page: 0x%x, queue = 0x%x\n", page, queue); ++ MHal_NOE_Write_Reg(QDMA_PAGE, page); ++ MHal_NOE_Write_Reg(QTX_CFG_0 + QUEUE_OFFSET * queue, cfg); ++#endif ++} ++ ++ ++void MHal_NOE_DMA_Enable_Specific_Intr(EN_NOE_DMA dma, EN_NOE_INTR_INFO e_intr) ++{ ++ MS_U32 reg_val; ++ if (dma & E_NOE_DMA_QUEUE) { ++ reg_val = MHal_NOE_Read_Reg(QFE_INT_ENABLE); ++ if (MHal_NOE_Read_Reg(QFE_INT_STATUS) != 0) ++ MHAL_NOE_INTR_INFO("MASK = 0x%08x, STATUS = 0x%08x \n", MHal_NOE_Read_Reg(QFE_INT_ENABLE),MHal_NOE_Read_Reg(QFE_INT_STATUS)); ++ if (e_intr == E_NOE_INTR_INFO_RLS_DLY) { ++#if 1 //EMMA Modify ++ reg_val |= (BIT(15)|BIT(14)|BIT(13)|BIT(12)|BIT(8)|BIT(4)|BIT(0)|BIT(29)); ++#endif //AMME ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_val | RLS_DLY_INT); ++ } ++ else { ++ MHal_NOE_Write_Reg(QFE_INT_ENABLE, reg_val | RLS_DONE_INT); ++ } ++ //MHAL_NOE_INTR_INFO("2. 0x%x QFE_INT_ENABLE = 0x%08x\n", e_intr, MHal_NOE_Read_Reg(QFE_INT_ENABLE)); ++ } ++} ++ ++ ++void MHal_NOE_DMA_FQ_Init(struct noe_fq_base *info) ++{ ++ MHal_NOE_Write_Reg(QDMA_FQ_HEAD, (MS_U32) info->head); ++ MHal_NOE_Write_Reg(QDMA_FQ_TAIL, (MS_U32) info->tail); ++ MHal_NOE_Write_Reg(QDMA_FQ_CNT, ((info->txd_num << 16) | info->page_num)); ++ MHal_NOE_Write_Reg(QDMA_FQ_BLEN, info->page_size << 16); ++} ++ ++MS_U32 MHal_NOE_QDMA_Get_Tx(void) ++{ ++ return MHal_NOE_Read_Reg(QTX_DRX_PTR); ++} ++ ++void MHal_NOE_QDMA_Update_Tx(EN_NOE_QDMA_TX_TYPE type, MS_U32 adr) ++{ ++ if (type == E_NOE_QDMA_TX_FORWARD) ++ MHal_NOE_Write_Reg(QTX_CTX_PTR, adr); ++ else if (type == E_NOE_QMDA_TX_RELEASE) ++ MHal_NOE_Write_Reg(QTX_CRX_PTR, adr); ++} ++ ++void MHal_NOE_LRO_Control(EN_NOE_LRO_CTRL_TYPE type, MS_U32 param) ++{ ++ if (type == E_NOE_LRO_CTRL_AGG_CNT) { ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, param); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, param); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, param); ++ } ++ else if (type == E_NOE_LRO_CTRL_AGG_TIME) { ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, param); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, param); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, param); ++ } ++ else if (type == E_NOE_LRO_CTRL_AGE_TIME) { ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, param); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, param); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, param); ++ } ++ else if (type == E_NOE_LRO_CTRL_BW_THRESHOLD) { ++ SET_PDMA_LRO_BW_THRESHOLD(param); ++ } ++ else if (type == E_NOE_LRO_CTRL_SWITCH) { ++ if (param == NOE_DISABLE) { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0); ++ } ++ else { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ } ++ } ++} ++ ++ ++void MHal_NOE_Get_Pdma_Info(EN_NOE_PDMA_INFO_TYPE type, void *info) ++{ ++ if ((type >= E_NOE_PDMA_INFO_MAX) || (_mhal_noe_pdma_get_info_pfn[type] == NULL)) ++ return; ++ _mhal_noe_pdma_get_info_pfn[type](info); ++} ++ ++void _MHal_NOE_Disable_Miu_Protect(void) ++{ ++#if 0 ++ printk(" Remove MIU Protect \n"); ++#else ++ /* MIU */ ++ NOE_RIU_REG(0x1012, 0x20) = 0x0000; ++ NOE_RIU_REG(0x1012, 0x22) = 0x0000; ++ NOE_RIU_REG(0x1012, 0x24) = 0x0000; ++ NOE_RIU_REG(0x1012, 0x26) = 0x0000; ++ ++ NOE_RIU_REG(0x1012, 0x30) = NOE_RIU_REG(0x1012, 0x30) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x32) = NOE_RIU_REG(0x1012, 0x32) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x34) = NOE_RIU_REG(0x1012, 0x34) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x36) = NOE_RIU_REG(0x1012, 0x36) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x38) = NOE_RIU_REG(0x1012, 0x38) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x3A) = NOE_RIU_REG(0x1012, 0x3A) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x3C) = NOE_RIU_REG(0x1012, 0x3C) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0x2E) = NOE_RIU_REG(0x1012, 0x2E) & 0xFF00; ++ NOE_RIU_REG(0x1012, 0xD2) = NOE_RIU_REG(0x1012, 0xD2) & 0xFF00; ++ ++ NOE_RIU_REG(0x1012, 0xC0) = 0x0000; ++ NOE_RIU_REG(0x1012, 0xC2) = 0x0000; ++ NOE_RIU_REG(0x1012, 0xC4) = 0x0000; ++ NOE_RIU_REG(0x1012, 0xC6) = 0x0000; ++ ++ /* MIU2 */ ++ NOE_RIU_REG(0x1006, 0x20) = 0x0000; ++ NOE_RIU_REG(0x1006, 0x22) = 0x0000; ++ NOE_RIU_REG(0x1006, 0x24) = 0x0000; ++ NOE_RIU_REG(0x1006, 0x26) = 0x0000; ++ ++ NOE_RIU_REG(0x1006, 0x30) = NOE_RIU_REG(0x1006, 0x30) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x32) = NOE_RIU_REG(0x1006, 0x32) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x34) = NOE_RIU_REG(0x1006, 0x34) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x36) = NOE_RIU_REG(0x1006, 0x36) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x38) = NOE_RIU_REG(0x1006, 0x38) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x3A) = NOE_RIU_REG(0x1006, 0x3A) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x3C) = NOE_RIU_REG(0x1006, 0x3C) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0x2E) = NOE_RIU_REG(0x1006, 0x2E) & 0xFF00; ++ NOE_RIU_REG(0x1006, 0xD2) = NOE_RIU_REG(0x1006, 0xD2) & 0xFF00; ++ ++ NOE_RIU_REG(0x1006, 0xC0) = 0x0000; ++ NOE_RIU_REG(0x1006, 0xC2) = 0x0000; ++ NOE_RIU_REG(0x1006, 0xC4) = 0x0000; ++ NOE_RIU_REG(0x1006, 0xC6) = 0x0000; ++#endif ++} ++ ++ ++ ++ ++void MHal_NOE_Init(struct noe_sys *info) ++{ ++ ethdma_sysctl_base = info->sysctl_base; ++ _MHal_NOE_Disable_Miu_Protect(); ++ _MHal_NOE_Init_Clock(); ++ ++ /* GMAC1/2 RGMII mode */ ++ MHal_NOE_Write_Reg(SYSCFG1, MHal_NOE_Read_Reg(SYSCFG1) & (~(0x3 << 12))); ++ MHal_NOE_Write_Reg(SYSCFG1, MHal_NOE_Read_Reg(SYSCFG1) & (~(0x3 << 14))); ++ ++ /* GMAC Mux of GPIO */ ++ NOE_RIU_REG(NOE_RIU_BANK_PMSLEEP, 0x1C << 1) = 0x0000; ++ ++ noe_config.version = NOE_RIU_REG(NOE_RIU_BANK_PMTOP, 0x1 << 1) >> 8; ++ MHAL_NOE_DBG_INFO("Revision: 0x%x\n", noe_config.version); ++} ++ ++ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_noe.h b/drivers/sstar/noe/hal/infinity2/mhal_noe.h +new file mode 100755 +index 000000000000..9f4022766c8f +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_noe.h +@@ -0,0 +1,510 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_noe.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef MHAL_NOE_H ++#define MHAL_NOE_H ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include "mhal_porting.h" ++ ++#include "mhal_noe_dma.h" ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define NOE_PHYS 0x1fc00000 ++#define NOE_SIZE 0x00200000 ++ ++ ++ ++#define NOE_FALSE (0) ++#define NOE_TRUE (1) ++ ++#define NOE_DISABLE (0) ++#define NOE_ENABLE (1) ++ ++#define NOE_INVALID_PHY_ADDR (0xFFFFFFFF) ++#define NOE_INVALID_CALC_IDX (0xFFFFFFFF) ++#define NOE_SFQ_MAX_NUM (8) ++ ++ ++/* ++#if defined(CONFIG_MIPS) ++ #define MHAL_NOE_MAP_VA_TO_PA(dev, va, size, dir) ((MS_U32)virt_to_phys((MS_U32) (va)) - MSTAR_MIU0_BUS_BASE) ++#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++ #define MHAL_NOE_MAP_VA_TO_PA(dev, va, size, dir) \ ++ (((u32)__virt_to_phys(va)) > MSTAR_MIU1_BUS_BASE)? ((va) - MSTAR_MIU1_BUS_BASE): ((va) - MSTAR_MIU0_BUS_BASE) ++#else ++ #error "ARCH is not supported" ++#endif ++*/ ++ ++#define MHAL_NOE_IS_TXD_NOT_AVAILABLE(cpu_ptr) \ ++ ((cpu_ptr->txd_info2.NDP & 0x1) ||(cpu_ptr->txd_info3.OWN_bit == 0)) ++ ++ ++#define MHAL_NOE_MAX_ENTRIES_IN_LRO_TABLE (8) ++#define MHAL_NOE_MAX_INFO_FOR_EACH_ENTRY_IN_LRO_TABLE (9) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++typedef enum { ++ E_NOE_HAL_LOG_NONE = 0, ++ E_NOE_HAL_LOG_DBG = BIT(0), ++ E_NOE_HAL_LOG_INTR = BIT(1), ++}EN_NOE_HAL_LOG; ++ ++typedef enum { ++ E_NOE_SEL_DISABLE = 0, ++ E_NOE_SEL_ENABLE = 1, ++}EN_NOE_SEL; ++ ++typedef enum { ++ E_NOE_RET_TRUE = 0, ++ E_NOE_RET_FALSE = 1, ++ E_NOE_RET_INVALID_PARAM, /* the input param is not valid */ ++ E_NOE_RET_DEVICE_BUSY, /* dev is busy */ ++ E_NOE_RET_TIMEOUT, /* operation is timeout */ ++}EN_NOE_RET; ++ ++typedef enum { ++ E_NOE_SEL_PIN_MUX_INVALID = 0, ++ E_NOE_SEL_PIN_MUX_GE2_TO_CHIPTOP, ++ E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP, ++ E_NOE_SEL_PIN_MUX_GE1_TO_CHIPTOP_GE2_TO_CHIPTOP, ++ E_NOE_SEL_PIN_MUX_MAX, ++}EN_NOE_SEL_PIN_MUX; ++ ++typedef enum { ++ E_NOE_INTR_CLR_EXCEPT_RX = 0, ++ E_NOE_INTR_CLR_EXCEPT_TX = 1, ++}EN_NOE_INTR_CLR_STATUS; ++ ++typedef enum { ++ E_NOE_INTR_INFO_RLS_DLY = 0, ++ E_NOE_INTR_INFO_RLS_DONE = 1, ++}EN_NOE_INTR_INFO; ++ ++ ++typedef enum { ++ E_NOE_DLY_DISABLE = 0, ++ E_NOE_DLY_ENABLE = 1, ++}EN_NOE_DELAY; ++ ++ ++typedef enum { ++ E_NOE_GE_MAC1 = 0, ++ E_NOE_GE_MAC2 = 1, ++ E_NOE_GE_MAC_MAX, ++}EN_NOE_GE_MAC; ++ ++typedef enum { ++ E_NOE_DIR_RX = BIT(0), ++ E_NOE_DIR_TX = BIT(1), ++ E_NOE_DIR_BOTH = (E_NOE_DIR_RX | E_NOE_DIR_TX), ++}EN_NOE_DIR; ++ ++typedef enum { ++ E_NOE_DMA_PACKET = BIT(0), ++ E_NOE_DMA_QUEUE = BIT(1), ++ E_NOE_DMA_QUEUE_WITH_SFQ = (E_NOE_DMA_QUEUE | BIT(2)), ++}EN_NOE_DMA; ++ ++typedef enum { ++ E_NOE_RING_NO0 = 0, ++ E_NOE_RING_NO1 = 1, ++ E_NOE_RING_NO2 = 2, ++ E_NOE_RING_NO3 = 3, ++ E_NOE_RING_MAX, ++}EN_NOE_RING; ++ ++typedef enum { ++ E_NOE_VQ_NO0 = 0, ++ E_NOE_VQ_NO1 = 1, ++ E_NOE_VQ_NO2 = 2, ++ E_NOE_VQ_NO3 = 3, ++ E_NOE_VQ_MAX, ++}EN_NOE_VQ; ++ ++typedef enum { ++ E_NOE_QDMA_INFO_CNT = 0, ++ E_NOE_QDMA_INFO_FQ, ++ E_NOE_QDMA_INFO_SCH, ++ E_NOE_QDMA_INFO_FC, ++ E_NOE_QDMA_INFO_FSM, ++ E_NOE_QDMA_INFO_VQ, ++ E_NOE_QDMA_INFO_PQ, ++ E_NOE_QDMA_INFO_MAX, ++}EN_NOE_QDMA_INFO_TYPE; ++ ++typedef enum { ++ E_NOE_PDMA_INFO_DBG = 0, ++ E_NOE_PDMA_INFO_MAX, ++}EN_NOE_PDMA_INFO_TYPE; ++ ++typedef enum { ++ E_NOE_QDMA_TX_FORWARD = 0, ++ E_NOE_QMDA_TX_RELEASE, ++}EN_NOE_QDMA_TX_TYPE; ++ ++typedef enum { ++ E_NOE_LRO_CTRL_AGG_CNT = 0, ++ E_NOE_LRO_CTRL_AGG_TIME, ++ E_NOE_LRO_CTRL_AGE_TIME, ++ E_NOE_LRO_CTRL_BW_THRESHOLD, ++ E_NOE_LRO_CTRL_SWITCH, /* enable /disable */ ++}EN_NOE_LRO_CTRL_TYPE; ++ ++ ++typedef enum { ++ E_NOE_SPEED_1000, ++ E_NOE_SPEED_100, ++ E_NOE_SPEED_10, ++ E_NOE_SPEED_INVALID ++}EN_NOE_SPEED; ++ ++typedef enum { ++ E_NOE_DUPLEX_FULL, ++ E_NOE_DUPLEX_HALF, ++ E_NOE_DUPLEX_INVALID ++}EN_NOE_DUPLEX; ++ ++ ++typedef enum { ++ E_NOE_GDM_FWD_CPU = 0, ++ E_NOE_GDM_FWD_ENG ++}EN_NOE_GDM_FWD; ++ ++typedef enum { ++ E_NOE_IRQ_0 = 0, ++ E_NOE_IRQ_1 = 1, ++ E_NOE_IRQ_2 = 2, ++ E_NOE_IRQ_MAX ++}EN_NOE_IRQ; ++ ++typedef enum { ++ E_NOE_HAL_STATUS_IDLE = 0, ++ E_NOE_HAL_STATUS_RUNNING, ++ E_NOE_HAL_STATUS_SUSPEND, ++}EN_NOE_HAL_STATUS; ++ ++struct noe_dma_adr { ++ MS_PHYADDR ctx_adr; ++ MS_PHYADDR dtx_adr; ++ MS_PHYADDR crx_adr; ++ MS_PHYADDR drx_adr; ++}; ++ ++struct noe_ring_info { ++ MS_PHYADDR base_adr; ++ MS_U32 max_cnt; ++ MS_U32 cpu_idx; ++ MS_U32 dma_idx; ++}; ++ ++ ++struct noe_dma_info { ++ union { ++ struct noe_ring_info ring_st; ++ struct noe_dma_adr adr_st; ++ }; ++}; ++ ++ ++struct noe_intr_info { ++ MS_U32 fe_intr_enable; ++ MS_U32 fe_intr_status; ++ MS_U32 fe_intr_mask; ++ MS_U32 delay_intr_cfg; ++ MS_U32 qfe_intr_enable; ++ MS_U32 qfe_intr_status; ++ MS_U32 qfe_intr_mask; ++ ++}; ++ ++struct noe_rx_mac_info { ++ MS_U32 good_cnt; ++ MS_U32 good_pkt; ++ MS_U32 overflow_err; ++ MS_U32 fcs_err; ++ MS_U32 ser_cnt; ++ MS_U32 ler_pkt; ++ MS_U32 chk_err; ++ MS_U32 flow_ctrl; ++}; ++ ++struct noe_tx_mac_info { ++ MS_U32 skip_cnt; ++ MS_U32 collision_cnt; ++ MS_U32 good_cnt; ++ MS_U32 good_pkt; ++}; ++ ++struct noe_mac_status { ++ MS_U32 control; ++ MS_U32 status; ++}; ++ ++struct noe_mac_info { ++ struct noe_rx_mac_info rx; ++ struct noe_tx_mac_info tx; ++ struct noe_mac_status stat; ++}; ++ ++struct noe_pse_info { ++ MS_U32 min_free_cnt; ++ MS_U32 free_cnt; ++ MS_U32 fq_drop_cnt; ++ MS_U32 fc_drop_cnt; ++ MS_U32 ppe_drop_cnt; ++}; ++ ++struct noe_qdma_cnt { ++ MS_U8 pq_no; ++ MS_U32 pkt_cnt; ++ MS_U32 drop_cnt; ++}; ++ ++struct noe_qdma_fq { ++ MS_U32 sw_fq; ++ MS_U32 hw_fq; ++}; ++ ++ ++struct noe_sch_rate { ++ MS_U32 max_rate; ++ MS_U8 max_en; ++}; ++ ++struct noe_qdma_sch { ++ struct noe_sch_rate sch[2]; ++}; ++ ++ ++struct noe_qdma_drop_thres { ++ MS_U8 en; ++ MS_U8 ffa; ++ MS_U8 mode; ++ MS_U8 fst_vq_en; ++ MS_U8 fst_vq_mode; ++}; ++ ++struct noe_qdma_fc { ++ struct noe_qdma_drop_thres sw; ++ struct noe_qdma_drop_thres hw; ++}; ++ ++struct noe_qdma_fsm { ++ MS_U8 vqtb; ++ MS_U8 fq; ++ MS_U8 tx; ++ MS_U8 rx; ++ MS_U16 rls; ++ MS_U16 fwd; ++}; ++ ++struct noe_qdma_vq { ++ MS_U8 vq_num[E_NOE_VQ_MAX]; ++}; ++ ++struct noe_qdma_pq { ++ MS_U8 queue; ++ MS_U8 min_en; ++ MS_U32 min_rate; ++ MS_U8 max_en; ++ MS_U32 max_rate; ++ MS_U32 queue_head; ++ MS_U32 queue_tail; ++ MS_U8 sch; ++ MS_U8 weight; ++ MS_U8 hw_resv; ++ MS_U8 sw_resv; ++ MS_U16 txd_cnt; ++}; ++ ++struct noe_mac_link_status { ++ MS_BOOL link_up; ++ EN_NOE_SPEED speed; ++ EN_NOE_DUPLEX duplex; ++}; ++ ++struct noe_sfq_base { ++ MS_PHYADDR phy_adr[NOE_SFQ_MAX_NUM]; ++}; ++ ++struct noe_pdma_dbg { ++ MS_U32 rx[2]; ++ MS_U32 tx[2]; ++}; ++ ++struct noe_fq_base { ++ MS_U32 head; ++ MS_U32 tail; ++ MS_U32 txd_num; ++ MS_U32 page_num; ++ MS_U32 page_size; ++}; ++ ++struct noe_lro_calc_idx { ++ MS_U32 ring1; ++ MS_U32 ring2; ++ MS_U32 ring3; ++}; ++ ++struct noe_sys { ++ void __iomem *sysctl_base; ++}; ++ ++struct noe_irq { ++ MS_U8 num; ++ unsigned int irq[E_NOE_IRQ_MAX]; ++}; ++ ++struct lro_ctrl { ++ MS_U32 agg_cnt; ++ MS_U32 agg_time; ++ MS_U32 age_time; ++ MS_U32 threshold; ++}; ++ ++struct lro_tbl{ ++ MS_BOOL valid; ++ MS_U32 tlb_info[MHAL_NOE_MAX_INFO_FOR_EACH_ENTRY_IN_LRO_TABLE]; ++ MS_U32 priority; ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++ ++/* NOE SYS Init Information */ ++void MHal_NOE_Init(struct noe_sys *info); ++void MHAL_NOE_Get_Interrupt(struct noe_irq *info); ++ ++ ++void MHal_NOE_Write_Bits_Zero(void __iomem *addr, MS_U32 bit, MS_U32 len); ++void MHal_NOE_Write_Bits_One(void __iomem *addr, MS_U32 bit, MS_U32 len); ++EN_NOE_RET MHal_NOE_Set_Pin_Mux(EN_NOE_SEL_PIN_MUX mux); ++void MHal_NOE_Set_MAC_Address(EN_NOE_GE_MAC ge, unsigned char p[6]); ++void MHal_NOE_Get_MAC_Address(EN_NOE_GE_MAC ge, unsigned char* p); ++void MHal_NOE_Reset_SW(void); ++void MHal_NOE_Stop(void); ++void MHal_NOE_Reset_FE(void); ++void MHal_NOE_Reset_GMAC(void); ++MS_BOOL MHal_NOE_Support_Auto_Polling(void); ++void MHal_NOE_Set_Auto_Polling(EN_NOE_SEL enable); ++void MHal_NOE_Force_Link_Mode(EN_NOE_GE_MAC ge, EN_NOE_SPEED speed, EN_NOE_DUPLEX duplex); ++void MHal_NOE_MAC_Get_Link_Status(EN_NOE_GE_MAC ge, struct noe_mac_link_status *link_status); ++void MHal_NOE_Set_Vlan_Info(void); ++ ++MS_BOOL MHal_NOE_GPHY_Get_Link_Info(MS_U8 phy_addr); ++ ++/* DMA */ ++void MHal_NOE_Offoad_Checksum(EN_NOE_GE_MAC ge, unsigned char offload); ++void MHal_NOE_GLO_Reset(void); ++void MHal_NOE_LRO_Set_Prefetch(void); ++void MHal_NOE_DMA_Init(EN_NOE_DMA dma, EN_NOE_DIR dir, EN_NOE_RING ring_no, struct noe_dma_info *dma_info); ++void MHal_NOE_Dma_Init_Global_Config(EN_NOE_DMA dma); ++EN_NOE_RET MHal_NOE_Dma_Is_Idle(EN_NOE_DMA dma); ++MS_U32 MHal_NOE_DMA_Get_Calc_Idx(EN_NOE_DIR dir); ++void MHal_NOE_DMA_Update_Calc_Idx(EN_NOE_DIR dir, MS_U32 rx_dma_owner_idx); ++void MHal_NOE_DMA_SFQ_Init(struct noe_sfq_base *adr_info); ++void MHal_NOE_DMA_FQ_Init(struct noe_fq_base *info); ++MS_U32 MHal_NOE_QDMA_Get_Tx(void); ++void MHal_NOE_QDMA_Update_Tx(EN_NOE_QDMA_TX_TYPE type, MS_U32 adr); ++EN_NOE_RET MHal_NOE_LRO_Set_Ring_Cfg(EN_NOE_RING ring_idx, unsigned int sip, unsigned int dip, unsigned int sport, unsigned int dport); ++void MHal_NOE_LRO_Set_Cfg(void); ++void MHal_NOE_LRO_Set_Auto_Learn_Cfg(void); ++void MHal_NOE_LRO_Set_Ip(unsigned int lan_ip); ++void MHal_NOE_LRO_Reset_Rx_Ring(EN_NOE_RING ring_no, u32 phy_addr, u32 desc_num, u32 desc_idx); ++void MHal_NOE_LRO_Get_Calc_Idx(struct noe_lro_calc_idx *idx); ++void MHal_NOE_LRO_Update_Calc_Idx(MS_U32 ring_no, MS_U32 dma_owner_idx); ++void MHal_NOE_LRO_Control(EN_NOE_LRO_CTRL_TYPE type, MS_U32 param); ++void MHAL_NOE_LRO_Get_Control(EN_NOE_RING ring, struct lro_ctrl *info); ++void MHAL_NOE_LRO_Get_Table(MS_U32 entry, struct lro_tbl *info); ++/* IO Coherence */ ++void MHal_NOE_IO_Enable_Coherence(MS_BOOL qos); ++ ++/* Reset Engine */ ++EN_NOE_RET MHal_NOE_Need_Reset(void); ++void MHal_NOE_Do_Reset(void); ++ ++/* MII MGR */ ++void MHal_NOE_Init_Mii_Mgr(EN_NOE_GE_MAC ge, u32 addr, unsigned char force_mode); ++void MHal_NOE_Dump_Mii_Mgr(int port_no, int from, int to, int is_local, int page_no); ++EN_NOE_RET MHal_NOE_Write_Mii_Mgr(u32 addr, u32 reg, u32 write_data); ++EN_NOE_RET MHal_NOE_Read_Mii_Mgr(u32 addr, u32 reg, u32 *read_data); ++EN_NOE_RET MHal_NOE_Write45_Mii_Mgr(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data); ++EN_NOE_RET MHal_NOE_Read45_Mii_Mgr(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data); ++ ++/* Interrupt */ ++void MHal_NOE_Set_Grp_Intr(unsigned char delay_intr, unsigned char rx_only); ++ ++void MHal_NOE_Init_Sep_Intr(EN_NOE_DMA dma, EN_NOE_DIR dir); ++void MHal_NOE_Clear_Sep_Intr_Status(EN_NOE_DIR dir); ++void MHal_NOE_Enable_Sep_Intr(EN_NOE_DIR dir); ++void MHal_NOE_Disable_Sep_Intr(EN_NOE_DIR dir); ++void MHal_NOE_Enable_Sep_Delay_Intr(EN_NOE_DMA dma, EN_NOE_DELAY delay_intr); ++void MHal_NOE_Clear_Sep_Intr_Specific_Status(EN_NOE_DIR dir, EN_NOE_INTR_CLR_STATUS status); ++MS_U8 MHal_NOE_Get_Sep_Intr_Status(EN_NOE_DIR dir); ++ ++void MHal_NOE_Enable_Link_Intr(void); ++void MHal_NOE_Disable_Link_Intr(void); ++MS_BOOL MHal_NOE_Get_Link_Intr_Status(void); ++void MHal_NOE_Clear_Link_Intr_Status(void); ++ ++void MHal_NOE_Get_Intr_Status(EN_NOE_DMA dma, MS_U32 *recv, MS_U32 *xmit); ++void MHal_NOE_Clear_Intr_Status(EN_NOE_DMA dma); ++void MHal_NOE_Enable_Intr_Status(EN_NOE_DMA dma); ++void MHal_NOE_DMA_Enable_Specific_Intr(EN_NOE_DMA dma, EN_NOE_INTR_INFO e_intr); ++ ++void MHal_NOE_Set_Intr_Mask(EN_NOE_DELAY e_dly); ++ ++ ++/* Dump DBG Info */ ++void MHal_NOE_Set_DBG(EN_NOE_HAL_LOG level); ++EN_NOE_RET MHal_NOE_LRO_Get_Ring_Info(EN_NOE_DMA dma, EN_NOE_DIR dir, EN_NOE_RING ring_no, struct noe_dma_info *info); ++void MHal_NOE_Get_Intr_Info(struct noe_intr_info *info); ++void MHal_NOE_Get_Mac_Info(EN_NOE_GE_MAC ge, struct noe_mac_info *info); ++void MHal_NOE_Get_Pse_Info(struct noe_pse_info *info); ++void MHal_NOE_Get_Qdma_Info(EN_NOE_QDMA_INFO_TYPE type, void *info); ++void MHal_NOE_Get_Pdma_Info(EN_NOE_PDMA_INFO_TYPE type, void *info); ++ ++/* I/O Control for QDMA */ ++MS_U32 MHal_NOE_DMA_Get_Queue_Cfg(MS_U32 queue_no); ++void MHal_NOE_DMA_Set_Queue_Cfg(MS_U32 queue_no, MS_U32 cfg); ++ ++ ++void MHal_NOE_Set_WoL(MS_BOOL enable); ++void MHal_NOE_Dma_DeInit_Global_Config(EN_NOE_DMA dma); ++#ifdef CONFIG_MDIO_IC1819 ++extern unsigned int mdio_bb_read(int phy,int reg); ++extern unsigned int mdio_bb_write(unsigned int phy,unsigned int reg,unsigned int val); ++#endif ++#endif /* MHAL_NOE_H */ ++ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_noe_dma.h b/drivers/sstar/noe/hal/infinity2/mhal_noe_dma.h +new file mode 100755 +index 000000000000..fbd54401cdff +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_noe_dma.h +@@ -0,0 +1,273 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MHAL_NOE_DMA.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MHAL_NOE_DMA_H_ ++#define _MHAL_NOE_DMA_H_ ++ ++ ++ ++#if defined(CONFIG_QDMA_MQ) ++#define GMAC1_TXQ_NUM 3 ++#define GMAC1_TXQ_TXD_NUM 512 ++#define GMAC1_TXD_NUM (GMAC1_TXQ_NUM * GMAC1_TXQ_TXD_NUM) ++#define GMAC2_TXQ_NUM 1 ++#define GMAC2_TXQ_TXD_NUM 128 ++#define GMAC2_TXD_NUM (GMAC2_TXQ_NUM * GMAC2_TXQ_TXD_NUM) ++#define NUM_TX_DESC (GMAC1_TXD_NUM + GMAC2_TXD_NUM) ++#define TOTAL_TXQ_NUM (GMAC1_TXQ_NUM + GMAC2_TXQ_NUM) ++#else ++#define GMAC1_TXQ_NUM 1 ++#define GMAC1_TXQ_TXD_NUM 2048 ++#define GMAC1_TXD_NUM (GMAC1_TXQ_NUM * GMAC1_TXQ_TXD_NUM) ++#define GMAC2_TXQ_NUM 1 ++#define GMAC2_TXQ_TXD_NUM 1024 ++#define GMAC2_TXD_NUM (GMAC2_TXQ_NUM * GMAC2_TXQ_TXD_NUM) ++#define NUM_TX_DESC (GMAC1_TXD_NUM + GMAC2_TXD_NUM) ++#define TOTAL_TXQ_NUM (GMAC1_TXQ_NUM + GMAC2_TXQ_NUM) ++#endif ++ ++#define NUM_RX_DESC 2048 ++#define NUM_QRX_DESC 16 ++#define NUM_PQ 64 ++#define NUM_PQ_RESV 4 ++#define FFA 512 ++#define QUEUE_OFFSET 0x10 ++/* #define NUM_TX_DESC (NUM_PQ * NUM_PQ_RESV + FFA) */ ++ ++#define NUM_TX_MAX_PROCESS NUM_TX_DESC ++#define NUM_RX_MAX_PROCESS 16 ++ ++#define MAX_RX_RING_NUM 4 ++#define NUM_LRO_RX_DESC 16 ++ ++#define MAX_RX_LENGTH 1536 ++ ++#define NUM_QDMA_PAGE 512 ++#define QDMA_PAGE_SIZE 2048 ++ ++#define MAX_PACKET_SIZE 1514 ++#define MIN_PACKET_SIZE 60 ++ ++#define MAX_PTXD_LEN 0x3fff /* 16k */ ++#define MAX_QTXD_LEN 0xffff ++ ++ ++ ++/*========================================= ++ * SFQ Table Format define ++ *========================================= ++ */ ++struct SFQ_INFO1_T { ++ unsigned int VQHPTR; ++}; ++ ++struct SFQ_INFO2_T { ++ unsigned int VQTPTR; ++}; ++ ++struct SFQ_INFO3_T { ++ unsigned int QUE_DEPTH:16; ++ unsigned int DEFICIT_CNT:16; ++}; ++ ++struct SFQ_INFO4_T { ++ unsigned int RESV; ++}; ++ ++struct SFQ_INFO5_T { ++ unsigned int PKT_CNT; ++}; ++ ++struct SFQ_INFO6_T { ++ unsigned int BYTE_CNT; ++}; ++ ++struct SFQ_INFO7_T { ++ unsigned int BYTE_CNT; ++}; ++ ++struct SFQ_INFO8_T { ++ unsigned int RESV; ++}; ++ ++struct SFQ_table { ++ struct SFQ_INFO1_T sfq_info1; ++ struct SFQ_INFO2_T sfq_info2; ++ struct SFQ_INFO3_T sfq_info3; ++ struct SFQ_INFO4_T sfq_info4; ++ struct SFQ_INFO5_T sfq_info5; ++ struct SFQ_INFO6_T sfq_info6; ++ struct SFQ_INFO7_T sfq_info7; ++ struct SFQ_INFO8_T sfq_info8; ++}; ++ ++ ++/*========================================= ++ * PDMA RX Descriptor Format define ++ *========================================= ++ */ ++ ++struct PDMA_RXD_INFO1_T { ++ unsigned int PDP0; ++}; ++ ++struct PDMA_RXD_INFO2_T { ++ unsigned int PLEN1:2; ++ unsigned int LRO_AGG_CNT:8; ++ unsigned int REV:5; ++ unsigned int TAG:1; ++ unsigned int PLEN0:14; ++ unsigned int LS0:1; ++ unsigned int DDONE_bit:1; ++}; ++ ++struct PDMA_RXD_INFO3_T { ++ unsigned int VID:16; ++ unsigned int TPID:16; ++}; ++ ++struct PDMA_RXD_INFO4_T { ++ unsigned int FOE_ENTRY:14; ++ unsigned int CRSN:5; ++ unsigned int SP:4; ++ unsigned int L4F:1; ++ unsigned int L4VLD:1; ++ unsigned int TACK:1; ++ unsigned int IP4F:1; ++ unsigned int IP4:1; ++ unsigned int IP6:1; ++ unsigned int UN_USE1:3; ++}; ++ ++struct PDMA_rxdesc { ++ struct PDMA_RXD_INFO1_T rxd_info1; ++ struct PDMA_RXD_INFO2_T rxd_info2; ++ struct PDMA_RXD_INFO3_T rxd_info3; ++ struct PDMA_RXD_INFO4_T rxd_info4; ++#ifdef CONFIG_32B_DESC ++ unsigned int rxd_info5; ++ unsigned int rxd_info6; ++ unsigned int rxd_info7; ++ unsigned int rxd_info8; ++#endif ++}; ++ ++/*========================================= ++ * PDMA TX Descriptor Format define ++ *========================================= ++ */ ++struct PDMA_TXD_INFO1_T { ++ unsigned int SDP0; ++}; ++ ++struct PDMA_TXD_INFO2_T { ++ unsigned int SDL1:14; ++ unsigned int LS1_bit:1; ++ unsigned int BURST_bit:1; ++ unsigned int SDL0:14; ++ unsigned int LS0_bit:1; ++ unsigned int DDONE_bit:1; ++}; ++ ++struct PDMA_TXD_INFO3_T { ++ unsigned int SDP1; ++}; ++ ++struct PDMA_TXD_INFO4_T { ++ unsigned int VLAN_TAG:17; /* INSV(1)+VPRI(3)+CFI(1)+VID(12) */ ++ unsigned int RESV:2; ++ unsigned int UDF:6; ++ unsigned int FPORT:3; ++ unsigned int TSO:1; ++ unsigned int TUI_CO:3; ++}; ++ ++struct PDMA_txdesc { ++ struct PDMA_TXD_INFO1_T txd_info1; ++ struct PDMA_TXD_INFO2_T txd_info2; ++ struct PDMA_TXD_INFO3_T txd_info3; ++ struct PDMA_TXD_INFO4_T txd_info4; ++#ifdef CONFIG_32B_DESC ++ unsigned int txd_info5; ++ unsigned int txd_info6; ++ unsigned int txd_info7; ++ unsigned int txd_info8; ++#endif ++}; ++ ++/*========================================= ++ * QDMA TX Descriptor Format define ++ *========================================= ++ */ ++struct QDMA_TXD_INFO1_T { ++ unsigned int SDP; ++}; ++ ++struct QDMA_TXD_INFO2_T { ++ unsigned int NDP; ++}; ++ ++struct QDMA_TXD_INFO3_T { ++ unsigned int QID:4; /* Q0~Q15 */ ++ /* unsigned int VQID : 10; */ ++ unsigned int PROT:3; ++ unsigned int IPOFST:7; ++ unsigned int SWC_bit:1; ++ unsigned int BURST_bit:1; ++ unsigned int SDL:14; ++ unsigned int LS_bit:1; ++ unsigned int OWN_bit:1; ++}; ++ ++struct QDMA_TXD_INFO4_T { ++ unsigned int VLAN_TAG:17; /* INSV(1)+VPRI(3)+CFI(1)+VID(12) */ ++ unsigned int VQID0:1; ++ unsigned int SDL:2; ++ unsigned int QID:2; /* Q16~Q63 */ ++ unsigned int RESV:3; ++ unsigned int FPORT:3; ++ unsigned int TSO:1; ++ unsigned int TUI_CO:3; ++}; ++ ++struct QDMA_txdesc { ++ struct QDMA_TXD_INFO1_T txd_info1; ++ struct QDMA_TXD_INFO2_T txd_info2; ++ struct QDMA_TXD_INFO3_T txd_info3; ++ struct QDMA_TXD_INFO4_T txd_info4; ++#ifdef CONFIG_32B_DESC ++ unsigned int txd_info5; ++ unsigned int txd_info6; ++ unsigned int txd_info7; ++ unsigned int txd_info8; ++#endif ++}; ++ ++#define QTXD_LEN (sizeof(struct QDMA_txdesc)) ++ ++ ++#endif /* _MHAL_NOE_DMA_H_ */ ++ ++ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_noe_lro.h b/drivers/sstar/noe/hal/infinity2/mhal_noe_lro.h +new file mode 100755 +index 000000000000..4a64b3700750 +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_noe_lro.h +@@ -0,0 +1,386 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MHAL_NOE_LRO.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MHAL_NOE_LRO_H_ ++#define _MHAL_NOE_LRO_H_ ++ ++#define HW_LRO_TIMER_UNIT 1 ++#define HW_LRO_REFRESH_TIME 50000 ++#define HW_LRO_MAX_AGG_CNT 64 ++#define HW_LRO_AGG_DELTA 1 ++#define MAX_LRO_RX_LENGTH (PAGE_SIZE * 3) ++#define HW_LRO_AGG_TIME 10 /* 200us */ ++#define HW_LRO_AGE_TIME 50 /* 1ms */ ++#define HW_LRO_BW_THRE 3000 ++#define HW_LRO_REPLACE_DELTA 1000 ++#define HW_LRO_SDL_REMAIN_ROOM 1522 ++ ++ ++ ++#define PDMA_LRO_EN BIT(0) ++#define PDMA_LRO_IPV6_EN BIT(1) ++#define PDMA_LRO_IPV4_CSUM_UPDATE_EN BIT(7) ++#define PDMA_LRO_IPV4_CTRL_PUSH_EN BIT(23) ++#define PDMA_LRO_RXD_PREFETCH_EN BITS(3, 4) ++#define PDMA_NON_LRO_MULTI_EN BIT(2) ++#define PDMA_LRO_DLY_INT_EN BIT(5) ++#define PDMA_LRO_FUSH_REQ BITS(26, 28) ++#define PDMA_LRO_RELINGUISH BITS(29, 31) ++#define PDMA_LRO_FREQ_PRI_ADJ BITS(16, 19) ++#define PDMA_LRO_TPUT_PRE_ADJ BITS(8, 11) ++#define PDMA_LRO_TPUT_PRI_ADJ BITS(12, 15) ++#define PDMA_LRO_ALT_SCORE_MODE BIT(21) ++#define PDMA_LRO_RING_AGE1 BITS(22, 31) ++#define PDMA_LRO_RING_AGE2 BITS(0, 5) ++#define PDMA_LRO_RING_AGG BITS(10, 25) ++#define PDMA_LRO_RING_AGG_CNT1 BITS(26, 31) ++#define PDMA_LRO_RING_AGG_CNT2 BITS(0, 1) ++#define PDMA_LRO_ALT_TICK_TIMER BITS(16, 20) ++#define PDMA_LRO_LRO_MIN_RXD_SDL0 BITS(16, 31) ++ ++#define PDMA_LRO_DLY_INT_EN_OFFSET (5) ++#define PDMA_LRO_TPUT_PRE_ADJ_OFFSET (8) ++#define PDMA_LRO_FREQ_PRI_ADJ_OFFSET (16) ++#define PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET (16) ++#define PDMA_LRO_TPUT_PRI_ADJ_OFFSET (12) ++#define PDMA_LRO_ALT_SCORE_MODE_OFFSET (21) ++#define PDMA_LRO_FUSH_REQ_OFFSET (26) ++#define PDMA_NON_LRO_MULTI_EN_OFFSET (2) ++#define PDMA_LRO_IPV6_EN_OFFSET (1) ++#define PDMA_LRO_RXD_PREFETCH_EN_OFFSET (3) ++#define PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET (7) ++#define PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET (23) ++#define PDMA_LRO_ALT_TICK_TIMER_OFFSET (16) ++ ++#define PDMA_LRO_TPUT_OVERFLOW_ADJ BITS(12, 31) ++#define PDMA_LRO_CNT_OVERFLOW_ADJ BITS(0, 11) ++ ++#define PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET (12) ++#define PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET (0) ++ ++#define PDMA_LRO_ALT_BYTE_CNT_MODE (0) ++#define PDMA_LRO_ALT_PKT_CNT_MODE (1) ++ ++/* LRO_RX_RING1_CTRL_DW1 offsets */ ++#define PDMA_LRO_AGE_H_OFFSET (10) ++#define PDMA_LRO_RING_AGE1_OFFSET (22) ++#define PDMA_LRO_RING_AGG_CNT1_OFFSET (26) ++/* LRO_RX_RING1_CTRL_DW2 offsets */ ++#define PDMA_RX_MODE_OFFSET (6) ++#define PDMA_RX_PORT_VALID_OFFSET (8) ++#define PDMA_RX_MYIP_VALID_OFFSET (9) ++#define PDMA_LRO_RING_AGE2_OFFSET (0) ++#define PDMA_LRO_RING_AGG_OFFSET (10) ++#define PDMA_LRO_RING_AGG_CNT2_OFFSET (0) ++/* LRO_RX_RING1_CTRL_DW3 offsets */ ++#define PDMA_LRO_AGG_CNT_H_OFFSET (6) ++/* LRO_RX_RING1_STP_DTP_DW offsets */ ++#define PDMA_RX_TCP_SRC_PORT_OFFSET (16) ++#define PDMA_RX_TCP_DEST_PORT_OFFSET (0) ++ ++ ++/* LRO_RX_RING1_CTRL_DW0 offsets */ ++#define PDMA_RX_IPV4_FORCE_OFFSET (1) ++#define PDMA_RX_IPV6_FORCE_OFFSET (0) ++ ++#define ADMA_MULTI_RXD_PREFETCH_EN BIT(3) ++#define ADMA_RXD_PREFETCH_EN BIT(4) ++ ++//-------------------------------------------------------------------------------------------------- ++ ++#define SET_PDMA_LRO_MAX_AGG_CNT(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW3); \ ++reg_val &= ~0xff; \ ++reg_val |= ((x) & 0xff); \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW3, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_FLUSH_REQ(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_FUSH_REQ; \ ++reg_val |= ((x) & 0x7) << PDMA_LRO_FUSH_REQ_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_IPV6_EN(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_IPV6_EN; \ ++reg_val |= ((x) & 0x1) << PDMA_LRO_IPV6_EN_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_RXD_PREFETCH_EN(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_RXD_PREFETCH_EN; \ ++reg_val |= (x); \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++ ++ ++#define SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_IPV4_CSUM_UPDATE_EN; \ ++reg_val |= ((x) & 0x1) << PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_IPV4_CTRL_PUSH_EN; \ ++reg_val |= ((x) & 0x1) << PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_NON_LRO_MULTI_EN(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~(PDMA_NON_LRO_MULTI_EN); \ ++reg_val |= ((x) & 0x1) << PDMA_NON_LRO_MULTI_EN_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_FREQ_PRI_ADJ(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_FREQ_PRI_ADJ; \ ++reg_val |= ((x) & 0xf) << PDMA_LRO_FREQ_PRI_ADJ_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_TPUT_PRE_ADJ(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_TPUT_PRE_ADJ; \ ++reg_val |= ((x) & 0xf) << PDMA_LRO_TPUT_PRE_ADJ_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++#define SET_PDMA_LRO_TPUT_PRI_ADJ(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_TPUT_PRI_ADJ; \ ++reg_val |= ((x) & 0xf) << PDMA_LRO_TPUT_PRI_ADJ_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_ALT_SCORE_MODE(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_ALT_SCORE_MODE; \ ++reg_val |= ((x) & 0x1) << PDMA_LRO_ALT_SCORE_MODE_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_DLY_INT_EN(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW0); \ ++reg_val &= ~PDMA_LRO_DLY_INT_EN; \ ++reg_val |= ((x) & 0x1) << PDMA_LRO_DLY_INT_EN_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW0, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_BW_THRESHOLD(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW2); \ ++reg_val = (x); \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW2, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_MIN_RXD_SDL(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(ADMA_LRO_CTRL_DW3); \ ++reg_val &= ~PDMA_LRO_LRO_MIN_RXD_SDL0; \ ++reg_val |= ((x) & 0xffff) << PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET; \ ++MHal_NOE_Write_Reg(ADMA_LRO_CTRL_DW3, reg_val); \ ++} ++ ++ ++ ++#define SET_PDMA_LRO_TPUT_OVERFLOW_ADJ(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(PDMA_LRO_ATL_OVERFLOW_ADJ); \ ++reg_val &= ~PDMA_LRO_TPUT_OVERFLOW_ADJ; \ ++reg_val |= ((x) & 0xfffff) << PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET; \ ++MHal_NOE_Write_Reg(PDMA_LRO_ATL_OVERFLOW_ADJ, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_CNT_OVERFLOW_ADJ(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(PDMA_LRO_ATL_OVERFLOW_ADJ); \ ++reg_val &= ~PDMA_LRO_CNT_OVERFLOW_ADJ; \ ++reg_val |= ((x) & 0xfff) << PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET; \ ++MHal_NOE_Write_Reg(PDMA_LRO_ATL_OVERFLOW_ADJ, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_ALT_REFRESH_TIMER); \ ++reg_val &= ~PDMA_LRO_ALT_TICK_TIMER; \ ++reg_val |= ((x) & 0x1f) << PDMA_LRO_ALT_TICK_TIMER_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_ALT_REFRESH_TIMER, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_ALT_REFRESH_TIMER(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_ALT_REFRESH_TIMER); \ ++reg_val &= ~0xffff; \ ++reg_val |= ((x) & 0xffff); \ ++MHal_NOE_Write_Reg(LRO_ALT_REFRESH_TIMER, reg_val); \ ++} ++ ++#define SET_PDMA_LRO_MAX_AGG_TIME(x) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_MAX_AGG_TIME); \ ++reg_val &= ~0xffff; \ ++reg_val |= ((x) & 0xffff); \ ++MHal_NOE_Write_Reg(LRO_MAX_AGG_TIME, reg_val); \ ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++#define SET_PDMA_RXRING_MODE(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \ ++reg_val &= ~(0x3 << PDMA_RX_MODE_OFFSET); \ ++reg_val |= (y) << PDMA_RX_MODE_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_MYIP_VALID(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \ ++reg_val &= ~(0x1 << PDMA_RX_MYIP_VALID_OFFSET); \ ++reg_val |= ((y) & 0x1) << PDMA_RX_MYIP_VALID_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_VALID(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \ ++reg_val &= ~(0x1 << PDMA_RX_PORT_VALID_OFFSET); \ ++reg_val |= ((y) & 0x1) << PDMA_RX_PORT_VALID_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_TCP_SRC_PORT(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING1_STP_DTP_DW + \ ++ (((x) - 1) << 6)); \ ++reg_val &= ~(0xffff << PDMA_RX_TCP_SRC_PORT_OFFSET); \ ++reg_val |= (y) << PDMA_RX_TCP_SRC_PORT_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING1_STP_DTP_DW + (((x) - 1) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_TCP_DEST_PORT(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING1_STP_DTP_DW + \ ++ (((x) - 1) << 6)); \ ++reg_val &= ~(0xffff << PDMA_RX_TCP_DEST_PORT_OFFSET); \ ++reg_val |= (y) << PDMA_RX_TCP_DEST_PORT_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING1_STP_DTP_DW + (((x) - 1) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_IPV4_FORCE_MODE(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6)); \ ++reg_val &= ~(0x1 << PDMA_RX_IPV4_FORCE_OFFSET); \ ++reg_val |= (y) << PDMA_RX_IPV4_FORCE_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_IPV6_FORCE_MODE(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6)); \ ++reg_val &= ~(0x1 << PDMA_RX_IPV6_FORCE_OFFSET); \ ++reg_val |= (y) << PDMA_RX_IPV6_FORCE_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6), reg_val); \ ++} ++ ++#define SET_PDMA_RXRING_AGE_TIME(x, y) \ ++{ \ ++unsigned int reg_val1 = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW1 + ((x) << 6)); \ ++unsigned int reg_val2 = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \ ++reg_val1 &= ~PDMA_LRO_RING_AGE1; \ ++reg_val2 &= ~PDMA_LRO_RING_AGE2; \ ++reg_val1 |= ((y) & 0x3ff) << PDMA_LRO_RING_AGE1_OFFSET; \ ++reg_val2 |= (((y) >> PDMA_LRO_AGE_H_OFFSET) & 0x03f) << \ ++ PDMA_LRO_RING_AGE2_OFFSET;\ ++MHal_NOE_Write_Reg(LRO_RX_RING0_CTRL_DW1 + ((x) << 6), reg_val1); \ ++MHal_NOE_Write_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val2); \ ++} ++ ++#define SET_PDMA_RXRING_AGG_TIME(x, y) \ ++{ \ ++unsigned int reg_val = MHal_NOE_Read_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \ ++reg_val &= ~PDMA_LRO_RING_AGG; \ ++reg_val |= ((y) & 0xffff) << PDMA_LRO_RING_AGG_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \ ++} ++ ++ ++#define SET_PDMA_RXRING_MAX_AGG_CNT(x, y) \ ++{ \ ++unsigned int reg_val1 = MHal_NOE_Read_Reg(LRO_RX_RING1_CTRL_DW2 + \ ++ (((x) - 1) << 6)); \ ++unsigned int reg_val2 = MHal_NOE_Read_Reg(LRO_RX_RING1_CTRL_DW3 + \ ++ (((x) - 1) << 6)); \ ++reg_val1 &= ~PDMA_LRO_RING_AGG_CNT1; \ ++reg_val2 &= ~PDMA_LRO_RING_AGG_CNT2; \ ++reg_val1 |= ((y) & 0x3f) << PDMA_LRO_RING_AGG_CNT1_OFFSET; \ ++reg_val2 |= (((y) >> PDMA_LRO_AGG_CNT_H_OFFSET) & 0x03) << \ ++ PDMA_LRO_RING_AGG_CNT2_OFFSET; \ ++MHal_NOE_Write_Reg(LRO_RX_RING1_CTRL_DW2 + (((x) - 1) << 6), reg_val1); \ ++MHal_NOE_Write_Reg(LRO_RX_RING1_CTRL_DW3 + (((x) - 1) << 6), reg_val2); \ ++} ++ ++ ++ ++ ++#endif /* _MHAL_NOE_LRO_H_ */ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_noe_reg.h b/drivers/sstar/noe/hal/infinity2/mhal_noe_reg.h +new file mode 100755 +index 000000000000..6f03b711592c +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_noe_reg.h +@@ -0,0 +1,1110 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipien ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MHAL_NOE_REG.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef MHAL_NOE_REG_H ++#define MHAL_NOE_REG_H ++ ++/* bits range: for example BITS(4,0) = 0x0000001F */ ++#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) ++ ++#define ETHER_ADDR_LEN 6 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Register ++//------------------------------------------------------------------------------------------------- ++#if defined(CONFIG_ARM64) ++#define NOE_RIU_REG_BASE(bank) (mstar_pm_base+ (bank << 9)) ++#else ++#ifndef RIU_VIRT_BASE ++#define RIU_VIRT_BASE 0xFD000000 ++#endif ++#define NOE_RIU_REG_BASE(bank) (RIU_VIRT_BASE + (bank << 9)) ++#endif /* defined(CONFIG_ARM64) */ ++ ++#define NOE_RIU_REG8_ADDR(reg) ((reg << 1) - (reg & 1)) ++#define NOE_RIU_REG_ADDR(reg) ((reg) << 1) ++#define NOE_RIU_BANK_ADR(x) (GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, (x)<<8)) ++#define NOE_RIU_REG(bank,oct_reg) INREG16( (NOE_RIU_BANK_ADR(bank)) + (NOE_RIU_REG_ADDR(oct_reg)) ) ++ ++#define MHal_NOE_Read_Reg(phys) (*(volatile unsigned int *)(phys)) ++#define MHal_NOE_Write_Reg(phys, val) ((*(volatile unsigned int *)(phys)) = (val)) ++ ++#define NOE_RIU_REG_MASK_WRITE(reg, mask, value) (reg) = ((reg) & (~(mask))) | (value) ++#define NOE_RIU_REG_BITS_WRITE(reg, value, offset, len) \ ++{\ ++ MS_U32 mask = BITS((len - 1 + offset), offset);\ ++ MS_U32 tmp = MHal_NOE_Read_Reg(reg) & (~mask);\ ++ tmp = (value << offset) & mask; \ ++ MHal_NOE_Write_Reg(reg,tmp);\ ++} ++ ++ ++#define NOE_RIU8_REG(bank,oct_reg) INREG8( (NOE_RIU_BANK_ADR(bank)) + (NOE_RIU_REG8_ADDR(oct_reg)) ) ++#define MHal_NOE_Read8_Reg(bank, oct_reg) NOE_RIU8_REG(bank,oct_reg) ++#define MHal_NOE_Write8_Reg(bank, oct_reg, val) NOE_RIU8_REG(bank,oct_reg) = (val) ++ ++//------------------------------------------------------------------------------------------------- ++// SYS BANK ++//------------------------------------------------------------------------------------------------- ++ ++#define NOE_RIU_BANK_SECGMAC4 (0x1224) ++#define NOE_RIU_BANK_GMAC4 (0x121F) ++#define NOE_RIU_BANK_ALBANY0 (0x0035) ++#define NOE_RIU_BANK_ALBANY1 (0x0036) ++#define NOE_RIU_BANK_CHIPTOP (0x101E) ++#define NOE_RIU_BANK_CLKGEN2 (0x100A) ++#define NOE_RIU_BANK_PMSLEEP (0x000E) ++#define NOE_RIU_BANK_PMTOP (0x001E) ++#define NOE_RIU_BANK_ANA_MISC_GMAC (0x110C) ++#define NOE_RIU_BANK_CLKGEN0 (0x100B) ++#define NOE_RIU_BANK_CLKGEN1 (0x1033) ++#define NOE_RIU_BANK_NOE_MISC (0x1214) ++ ++//------------------------------------------------------------------------------------------------- ++// GPHY Register Detail ++//------------------------------------------------------------------------------------------------- ++#define GPHY_MDIO_START_CL22 0x1 ++#define GPHY_MDIO_START_CL45 0x0 ++#define GPHY_MDIO_OPCODE_WRITE 0x1 ++#define GPHY_MDIO_OPCODE_CL22_READ 0x2 ++#define GPHY_MDIO_OPCODE_CL45_READ 0x3 ++#define GPHY_MDIO_OPCODE_CL45_ADDRESS 0x0 ++#define GPHY_MDIO_TA 0x2 ++#define GPHY_MDIO_START_SHIFT 14 ++#define GPHY_MDIO_OPCODE_SHIFT 12 ++#define GPHY_MDIO_PHY_ADDRESS_SHIFT 7 ++#define GPHY_MDIO_REG_ADDRESS_SHIFT 2 ++ ++ ++ ++#define GPHY_REG_BASIC (0) ++#define GPHY_REG_STATUS (1) ++#define GPHY_REG_LINK_PARTNER (5) ++#define GPHY_REG_CTRL1000 0x09 /* 1000BASE-T control */ ++#define GPHY_REG_STAT1000 0x0a /* 1000BASE-T status */ ++#define GPHY_REG_PHYSR 0x11 ++ ++ ++ ++#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ ++#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ ++#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ ++#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ ++#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ ++ ++#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) ++#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) ++#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ ++ ++#define DUPLEX_HALF 0x00 ++#define DUPLEX_FULL 0x01 ++ ++#define PHY_CODE_SHIFT (16) ++#define PHY_REG_SHIFT (18) ++#define PHY_ADDR_SHIFT (23) ++#define PHY_RW_SHIFT (28) ++#define PHY_LOW_HIGH_SHIFT (30) ++ ++#define PHY_CODE (0x02) ++#define PHY_LOW_HIGH (0x01) ++#define PHY_WRITE_OP (0x01) ++#define PHY_READ_OP (0x02) ++ ++#define GPHY_AN_DONE (0x1 << 5) ++#define GPHY_LINK_UP (0x1 << 2) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// NOE Register ++//------------------------------------------------------------------------------------------------- ++ ++/* Base Address */ ++extern void __iomem *ethdma_sysctl_base; ++#define NOE_REG_SYSCTL_BASE ethdma_sysctl_base ++#define NOE_REG_FRAME_ENGINE_BASE (NOE_REG_SYSCTL_BASE + 0x100000) ++#define NOE_REG_PPE_BASE (NOE_REG_FRAME_ENGINE_BASE + 0x00C00) ++#define NOE_REG_AC_BASE (NOE_REG_FRAME_ENGINE_BASE + 0x02000) ++#define NOE_REG_METER_BASE (NOE_REG_FRAME_ENGINE_BASE + 0x02000) ++#define NOE_REG_ETH_MAC_BASE (NOE_REG_FRAME_ENGINE_BASE + 0x10000) ++#define NOE_REG_ETH_SW_BASE (NOE_REG_FRAME_ENGINE_BASE + 0x18000) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// SYSCTL_BASE Register Detail ++//------------------------------------------------------------------------------------------------- ++#define SYSCFG1 (NOE_REG_SYSCTL_BASE + 0x14) ++#define CLK_CFG_0 (NOE_REG_SYSCTL_BASE + 0x2C) ++#define RSTCTRL (NOE_REG_SYSCTL_BASE + 0x34) ++#define RSTSTAT (NOE_REG_SYSCTL_BASE + 0x38) ++#define AGPIOCFG_REG (NOE_REG_SYSCTL_BASE + 0x3C) ++#define PAD_RGMII2_MDIO_CFG (NOE_REG_SYSCTL_BASE + 0x58) ++#define REG_NOE_IOC_ETH (NOE_REG_SYSCTL_BASE + 0x408) ++ #define IOC_ETH_PDMA BIT(0) ++ #define IOC_ETH_QDMA BIT(1) ++ ++#define METER_BASE NOE_REG_METER_BASE ++//------------------------------------------------------------------------------------------------- ++// FRAME_ENGINE_BASE Register Detail ++//------------------------------------------------------------------------------------------------- ++/* Register Categories Definition */ ++#define RAFRAMEENGINE_OFFSET (0x0000) ++#define RAGDMA_OFFSET (0x0020) ++#define PSE_RELATED (0x0040) ++#define RAPSE_OFFSET (0x0040) ++#define RAGDMA2_OFFSET (0x0060) ++#define RACDMA_OFFSET (0x0080) ++#define FE_GDM_RXID1_OFFSET (0x0130) ++#define FE_GDM_RXID2_OFFSET (0x0134) ++#define CDMA_RELATED (0x0400) ++#define GDMA1_RELATED (0x0500) ++#define PDMA_RELATED (0x0800) ++#define RAPDMA_OFFSET (0x0800) ++#define SDM_OFFSET (0x0C00) ++#define RAPPE_OFFSET (0x0200) ++#define RACMTABLE_OFFSET (0x0400) ++#define ADMA_LRO_CTRL_OFFSET (0x0980) ++#define PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET (0x0990) ++#define ADMA_DBG_OFFSET (0x0A30) ++#define LRO_RXRING0_OFFSET (0x0B00) ++#define LRO_RXRING1_OFFSET (0x0B40) ++#define LRO_RXRING2_OFFSET (0x0B80) ++#define LRO_RXRING3_OFFSET (0x0BC0) ++#define POLICYTABLE_OFFSET (0x1000) ++#define GDMA2_RELATED (0x1500) ++#define QDMA_RELATED (0x1800) ++#define SFQ_OFFSET (0x1A80) ++ ++ ++ ++ ++#define FE_GLO_CFG (NOE_REG_FRAME_ENGINE_BASE + 0x000) ++#define FE_RST_GL (NOE_REG_FRAME_ENGINE_BASE + 0x004) ++#define FE_INT_STATUS2 (NOE_REG_FRAME_ENGINE_BASE + 0x008) ++#define FE_INT_ENABLE2 (NOE_REG_FRAME_ENGINE_BASE + 0x00C) ++ #define MAC2_LINK BIT(25) ++ #define MAC1_LINK BIT(24) ++#define FOE_TS_T (NOE_REG_FRAME_ENGINE_BASE + 0x010) ++#define FOE_TS FOE_TS_T ++#define FC_DROP_STA (NOE_REG_FRAME_ENGINE_BASE + 0x018) ++#define LRO_ALT_REFRESH_TIMER (NOE_REG_FRAME_ENGINE_BASE + 0x01C) ++#define FE_INT_GRP (NOE_REG_FRAME_ENGINE_BASE + 0x020) ++#define PSE_FQ_CFG (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x00) ++#define CDMA_FC_CFG (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x04) ++#define GDMA1_FC_CFG (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x08) ++#define GDMA2_FC_CFG (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C) ++#define CDMA_OQ_STA (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x10) ++#define GDMA1_OQ_STA (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x14) ++#define GDMA2_OQ_STA (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x18) ++#define PSE_IQ_STA (NOE_REG_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C) ++ ++#define FE_GDMA1_FWD_CFG (NOE_REG_FRAME_ENGINE_BASE + 0x500) ++#define FE_GDMA2_FWD_CFG (NOE_REG_FRAME_ENGINE_BASE + 0x1500) ++ ++#define PDMA_FC_CFG (NOE_REG_FRAME_ENGINE_BASE + 0x100) ++#define FE_GLO_MISC (NOE_REG_FRAME_ENGINE_BASE + 0x124) ++#define FE_PSE_FREE (NOE_REG_FRAME_ENGINE_BASE + 0x240) ++#define FE_DROP_FQ (NOE_REG_FRAME_ENGINE_BASE + 0x244) ++#define FE_DROP_FC (NOE_REG_FRAME_ENGINE_BASE + 0x248) ++#define FE_DROP_PPE (NOE_REG_FRAME_ENGINE_BASE + 0x24c) ++#define PDMA_FE_ALT_CF8 (NOE_REG_FRAME_ENGINE_BASE + 0x0300) ++#define PDMA_FE_ALT_SGL_CFC (NOE_REG_FRAME_ENGINE_BASE + 0x0304) ++#define PDMA_FE_ALT_SEQ_CFC (NOE_REG_FRAME_ENGINE_BASE + 0x0308) ++#define CDMA_CSG_CFG (NOE_REG_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) ++#define CDMP_IG_CTRL (NOE_REG_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) ++#define CDMP_EG_CTRL (NOE_REG_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04) ++#define PPE_AC_BCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x000) ++#define PPE_AC_PCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x004) ++#define PPE_MTR_CNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x200) ++#define PPE_MTR_CNT63 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x2FC) ++#define GDMA_TX_GBCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x300) ++#define GDMA_TX_GPCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x304) ++#define GDMA_TX_SKIPCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x308) ++#define GDMA_TX_COLCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x30C) ++#define GDMA_RX_GBCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x320) ++#define GDMA_RX_GPCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x324) ++#define GDMA_RX_OERCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x328) ++#define GDMA_RX_FERCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x32C) ++#define GDMA_RX_SERCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x330) ++#define GDMA_RX_LERCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x334) ++#define GDMA_RX_CERCNT0 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x338) ++#define GDMA_RX_FCCNT1 (NOE_REG_FRAME_ENGINE_BASE + RACMTABLE_OFFSET + 0x33C) ++#define ADMA_LRO_CTRL_DW0 (NOE_REG_FRAME_ENGINE_BASE + ADMA_LRO_CTRL_OFFSET + 0x00) ++#define ADMA_LRO_CTRL_DW1 (NOE_REG_FRAME_ENGINE_BASE + ADMA_LRO_CTRL_OFFSET + 0x04) ++#define ADMA_LRO_CTRL_DW2 (NOE_REG_FRAME_ENGINE_BASE + ADMA_LRO_CTRL_OFFSET + 0x08) ++#define ADMA_LRO_CTRL_DW3 (NOE_REG_FRAME_ENGINE_BASE + ADMA_LRO_CTRL_OFFSET + 0x0C) ++ ++#define TX_BASE_PTR0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x000) ++#define TX_MAX_CNT0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x004) ++#define TX_CTX_IDX0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x008) ++#define TX_DTX_IDX0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x00C) ++#define TX_BASE_PTR1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x010) ++#define TX_MAX_CNT1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x014) ++#define TX_CTX_IDX1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x018) ++#define TX_DTX_IDX1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x01C) ++#define TX_BASE_PTR2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x020) ++#define TX_MAX_CNT2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x024) ++#define TX_CTX_IDX2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x028) ++#define TX_DTX_IDX2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x02C) ++#define TX_BASE_PTR3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x030) ++#define TX_MAX_CNT3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x034) ++#define TX_CTX_IDX3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x038) ++#define TX_DTX_IDX3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x03C) ++#define RX_BASE_PTR0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x100) ++#define RX_MAX_CNT0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x104) ++#define RX_CALC_IDX0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x108) ++#define RX_DRX_IDX0 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x10C) ++#define RX_BASE_PTR1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x110) ++#define RX_MAX_CNT1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x114) ++#define RX_CALC_IDX1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x118) ++#define RX_DRX_IDX1 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x11C) ++#define RX_BASE_PTR2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x120) ++#define RX_MAX_CNT2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x124) ++#define RX_CALC_IDX2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x128) ++#define RX_DRX_IDX2 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x12C) ++#define RX_BASE_PTR3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x130) ++#define RX_MAX_CNT3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x134) ++#define RX_CALC_IDX3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x138) ++#define RX_DRX_IDX3 (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x13C) ++#define PDMA_INFO (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x200) ++#define PDMA_GLO_CFG (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x204) ++#define PDMA_RST_IDX (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x208) ++#define PDMA_RST_CFG (PDMA_RST_IDX) ++#define DLY_INT_CFG (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x20C) ++#define FREEQ_THRES (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x210) ++#define INT_STATUS (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x220) ++#define FE_INT_STATUS (INT_STATUS) ++ #define RX_COHERENT BIT(31) ++ #define RX_DLY_INT BIT(30) ++ #define TX_COHERENT BIT(29) ++ #define TX_DLY_INT BIT(28) ++ #define RING3_RX_DLY_INT BIT(27) ++ #define RING2_RX_DLY_INT BIT(26) ++ #define RING1_RX_DLY_INT BIT(25) ++ #define RXD_ERROR BIT(24) ++ #define ALT_RPLC_INT3 BIT(23) ++ #define ALT_RPLC_INT2 BIT(22) ++ #define ALT_RPLC_INT1 BIT(21) ++ #define RX_DONE_INT3 BIT(19) ++ #define RX_DONE_INT2 BIT(18) ++ #define RX_DONE_INT1 BIT(17) ++ #define RX_DONE_INT0 BIT(16) ++ #define TX_DONE_INT3 BIT(3) ++ #define TX_DONE_INT2 BIT(2) ++ #define TX_DONE_INT1 BIT(1) ++ #define TX_DONE_INT0 BIT(0) ++#define INT_MASK (NOE_REG_FRAME_ENGINE_BASE + PDMA_RELATED + 0x228) ++#define FE_INT_ENABLE (INT_MASK) ++#define PDMA_INT_GRP1 (NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x250) ++#define PDMA_INT_GRP2 (NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x254) ++#define SCH_Q01_CFG (NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x280) ++#define SCH_Q23_CFG (NOE_REG_FRAME_ENGINE_BASE + RAPDMA_OFFSET + 0x284) ++#define GDMA1_FWD_CFG (NOE_REG_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00) ++#define GDMA1_SHPR_CFG (NOE_REG_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04) ++#define GDMA1_SCH_CFG GDMA1_SHPR_CFG ++ ++#define GDMA1_MAC_ADRL (NOE_REG_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08) ++#define GDMA1_MAC_ADRH (NOE_REG_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C) ++ ++#define GDMA2_FWD_CFG (NOE_REG_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00) ++#define GDMA2_SHPR_CFG (NOE_REG_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04) ++#define GDMA2_SCH_CFG GDMA2_SHPR_CFG ++#define GDMA2_MAC_ADRL (NOE_REG_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08) ++#define GDMA2_MAC_ADRH (NOE_REG_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C) ++ ++ ++#define QTX_CFG_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000) ++#define QTX_SCH_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004) ++#define QTX_HEAD_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008) ++#define QTX_TAIL_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C) ++#define QTX_CFG_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010) ++#define QTX_SCH_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014) ++#define QTX_HEAD_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018) ++#define QTX_TAIL_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C) ++#define QTX_CFG_2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020) ++#define QTX_SCH_2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024) ++#define QTX_HEAD_2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028) ++#define QTX_TAIL_2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C) ++#define QTX_CFG_3 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030) ++#define QTX_SCH_3 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034) ++#define QTX_HEAD_3 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038) ++#define QTX_TAIL_3 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C) ++#define QTX_CFG_4 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040) ++#define QTX_SCH_4 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044) ++#define QTX_HEAD_4 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048) ++#define QTX_TAIL_4 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C) ++#define QTX_CFG_5 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050) ++#define QTX_SCH_5 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054) ++#define QTX_HEAD_5 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058) ++#define QTX_TAIL_5 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C) ++#define QTX_CFG_6 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060) ++#define QTX_SCH_6 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064) ++#define QTX_HEAD_6 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068) ++#define QTX_TAIL_6 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C) ++#define QTX_CFG_7 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070) ++#define QTX_SCH_7 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074) ++#define QTX_HEAD_7 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078) ++#define QTX_TAIL_7 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C) ++#define QTX_CFG_8 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080) ++#define QTX_SCH_8 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084) ++#define QTX_HEAD_8 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088) ++#define QTX_TAIL_8 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C) ++#define QTX_CFG_9 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090) ++#define QTX_SCH_9 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094) ++#define QTX_HEAD_9 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098) ++#define QTX_TAIL_9 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C) ++#define QTX_CFG_10 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0) ++#define QTX_SCH_10 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4) ++#define QTX_HEAD_10 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8) ++#define QTX_TAIL_10 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC) ++#define QTX_CFG_11 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0) ++#define QTX_SCH_11 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4) ++#define QTX_HEAD_11 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8) ++#define QTX_TAIL_11 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC) ++#define QTX_CFG_12 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0) ++#define QTX_SCH_12 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4) ++#define QTX_HEAD_12 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8) ++#define QTX_TAIL_12 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC) ++#define QTX_CFG_13 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0) ++#define QTX_SCH_13 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4) ++#define QTX_HEAD_13 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8) ++#define QTX_TAIL_13 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC) ++#define QTX_CFG_14 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0) ++#define QTX_SCH_14 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4) ++#define QTX_HEAD_14 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8) ++#define QTX_TAIL_14 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC) ++#define QTX_CFG_15 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0) ++#define QTX_SCH_15 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4) ++#define QTX_HEAD_15 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8) ++#define QTX_TAIL_15 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC) ++#define QRX_BASE_PTR_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100) ++#define QRX_MAX_CNT_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104) ++#define QRX_CRX_IDX_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108) ++#define QRX_DRX_IDX_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C) ++#define QRX_BASE_PTR_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110) ++#define QRX_MAX_CNT_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114) ++#define QRX_CRX_IDX_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118) ++#define QRX_DRX_IDX_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C) ++ ++#define VQTX_TB_BASE_0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x180) ++#define VQTX_TB_BASE_1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x184) ++#define VQTX_TB_BASE_2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x188) ++#define VQTX_TB_BASE_3 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x18C) ++ ++#define QDMA_INFO (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200) ++#define QDMA_GLO_CFG (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204) ++#define QDMA_RST_IDX (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208) ++#define QDMA_RST_CFG (QDMA_RST_IDX) ++#define QDMA_DELAY_INT (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C) ++#define QDMA_FC_THRES (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210) ++#define QDMA_TX_SCH (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214) ++#define QDMA_INT_STS (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218) ++#define QFE_INT_STATUS (QDMA_INT_STS) ++#define QDMA_INT_MASK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C) ++#define QFE_INT_ENABLE (QDMA_INT_MASK) ++#define QDMA_TRTCM (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220) ++#define QDMA_INT_GRP1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220) ++#define QDMA_DATA0 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224) ++#define QDMA_INT_GRP2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224) ++#define QDMA_DATA1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228) ++#define QDMA_RED_THRES (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C) ++#define QDMA_TEST (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230) ++#define QDMA_DMA (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234) ++#define QDMA_BMU (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238) ++#define QDMA_HRED1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240) ++#define QDMA_HRED2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244) ++#define QDMA_SRED1 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248) ++#define QDMA_SRED2 (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C) ++#define QTX_MIB_IF (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x2BC) ++#define QTX_CTX_PTR (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300) ++#define QTX_DTX_PTR (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304) ++#define QTX_FWD_CNT (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308) ++#define QTX_CRX_PTR (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310) ++#define QTX_DRX_PTR (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314) ++#define QTX_RLS_CNT (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318) ++#define QDMA_FQ_HEAD (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320) ++#define QDMA_FQ_TAIL (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324) ++#define QDMA_FQ_CNT (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328) ++#define QDMA_FQ_BLEN (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C) ++#define QTX_Q0MIN_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350) ++#define QTX_Q1MIN_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354) ++#define QTX_Q2MIN_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358) ++#define QTX_Q3MIN_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C) ++#define QTX_Q0MAX_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360) ++#define QTX_Q1MAX_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364) ++#define QTX_Q2MAX_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368) ++#define QTX_Q3MAX_BK (NOE_REG_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C) ++ ++ ++#define LRO_RX1_DLY_INT (NOE_REG_FRAME_ENGINE_BASE + 0x0a70) ++#define LRO_RX2_DLY_INT (NOE_REG_FRAME_ENGINE_BASE + 0x0a74) ++#define LRO_RX3_DLY_INT (NOE_REG_FRAME_ENGINE_BASE + 0x0a78) ++ ++ ++#define PDMA_LRO_ATL_OVERFLOW_ADJ (NOE_REG_FRAME_ENGINE_BASE + PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET) ++#define LRO_ALT_SCORE_DELTA (NOE_REG_FRAME_ENGINE_BASE + 0x0a4c) ++#define LRO_MAX_AGG_TIME (NOE_REG_FRAME_ENGINE_BASE + 0x0a5c) ++ ++ ++#define LRO_RX_RING0_DIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x04) ++#define LRO_RX_RING0_DIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x08) ++#define LRO_RX_RING0_DIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x0C) ++#define LRO_RX_RING0_DIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x10) ++#define LRO_RX_RING0_CTRL_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x28) ++#define LRO_RX_RING0_CTRL_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x2C) ++#define LRO_RX_RING0_CTRL_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING0_OFFSET + 0x30) ++#define LRO_RX_RING1_STP_DTP_DW (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x00) ++#define LRO_RX_RING1_DIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x04) ++#define LRO_RX_RING1_DIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x08) ++#define LRO_RX_RING1_DIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x0C) ++#define LRO_RX_RING1_DIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x10) ++#define LRO_RX_RING1_SIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x14) ++#define LRO_RX_RING1_SIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x18) ++#define LRO_RX_RING1_SIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x1C) ++#define LRO_RX_RING1_SIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x20) ++#define LRO_RX_RING1_CTRL_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x24) ++#define LRO_RX_RING1_CTRL_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x28) ++#define LRO_RX_RING1_CTRL_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x2C) ++#define LRO_RX_RING1_CTRL_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING1_OFFSET + 0x30) ++#define LRO_RX_RING2_STP_DTP_DW (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x00) ++#define LRO_RX_RING2_DIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x04) ++#define LRO_RX_RING2_DIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x08) ++#define LRO_RX_RING2_DIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x0C) ++#define LRO_RX_RING2_DIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x10) ++#define LRO_RX_RING2_SIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x14) ++#define LRO_RX_RING2_SIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x18) ++#define LRO_RX_RING2_SIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x1C) ++#define LRO_RX_RING2_SIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x20) ++#define LRO_RX_RING2_CTRL_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x24) ++#define LRO_RX_RING2_CTRL_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x28) ++#define LRO_RX_RING2_CTRL_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x2C) ++#define LRO_RX_RING2_CTRL_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING2_OFFSET + 0x30) ++ ++#define LRO_RX_RING3_STP_DTP_DW (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x00) ++#define LRO_RX_RING3_DIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x04) ++#define LRO_RX_RING3_DIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x08) ++#define LRO_RX_RING3_DIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x0C) ++#define LRO_RX_RING3_DIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x10) ++#define LRO_RX_RING3_SIP_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x14) ++#define LRO_RX_RING3_SIP_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x18) ++#define LRO_RX_RING3_SIP_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x1C) ++#define LRO_RX_RING3_SIP_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x20) ++#define LRO_RX_RING3_CTRL_DW0 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x24) ++#define LRO_RX_RING3_CTRL_DW1 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x28) ++#define LRO_RX_RING3_CTRL_DW2 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x2C) ++#define LRO_RX_RING3_CTRL_DW3 (NOE_REG_FRAME_ENGINE_BASE + LRO_RXRING3_OFFSET + 0x30) ++#define ADMA_TX_DBG0 (NOE_REG_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x00) ++#define ADMA_TX_DBG1 (NOE_REG_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x04) ++#define ADMA_RX_DBG0 (NOE_REG_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x08) ++#define ADMA_RX_DBG1 (NOE_REG_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x0C) ++ ++ ++#define FE_GDM_RXID1 (NOE_REG_FRAME_ENGINE_BASE + FE_GDM_RXID1_OFFSET) ++ #define GDM_VLAN_PRI7_RXID_SEL BITS(30, 31) ++ #define GDM_VLAN_PRI6_RXID_SEL BITS(28, 29) ++ #define GDM_VLAN_PRI5_RXID_SEL BITS(26, 27) ++ #define GDM_VLAN_PRI4_RXID_SEL BITS(24, 25) ++ #define GDM_VLAN_PRI3_RXID_SEL BITS(22, 23) ++ #define GDM_VLAN_PRI2_RXID_SEL BITS(20, 21) ++ #define GDM_VLAN_PRI1_RXID_SEL BITS(18, 19) ++ #define GDM_VLAN_PRI0_RXID_SEL BITS(16, 17) ++ #define GDM_TCP_ACK_RXID_SEL BITS(4, 5) ++ #define GDM_TCP_ACK_WZPC BIT(3) ++ #define GDM_RXID_PRI_SEL BITS(0, 2) ++ ++ ++#define FE_GDM_RXID2 (NOE_REG_FRAME_ENGINE_BASE + FE_GDM_RXID2_OFFSET) ++ #define GDM_STAG7_RXID_SEL BITS(30, 31) ++ #define GDM_STAG6_RXID_SEL BITS(28, 29) ++ #define GDM_STAG5_RXID_SEL BITS(26, 27) ++ #define GDM_STAG4_RXID_SEL BITS(24, 25) ++ #define GDM_STAG3_RXID_SEL BITS(22, 23) ++ #define GDM_STAG2_RXID_SEL BITS(20, 21) ++ #define GDM_STAG1_RXID_SEL BITS(18, 19) ++ #define GDM_STAG0_RXID_SEL BITS(16, 17) ++ #define GDM_PID2_RXID_SEL BITS(2, 3) ++ #define GDM_PID1_RXID_SEL BITS(0, 1) ++ ++ ++#define QDMA_PAGE (NOE_REG_FRAME_ENGINE_BASE + 0x19f0) ++ ++/*SFQ use*/ ++#define VQTX_TB_BASE0 (NOE_REG_FRAME_ENGINE_BASE + 0x1980) ++#define VQTX_TB_BASE1 (NOE_REG_FRAME_ENGINE_BASE + 0x1984) ++#define VQTX_TB_BASE2 (NOE_REG_FRAME_ENGINE_BASE + 0x1988) ++#define VQTX_TB_BASE3 (NOE_REG_FRAME_ENGINE_BASE + 0x198C) ++ ++#define VQTX_GLO (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET) ++#define VQTX_INVLD_PTR (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x0C) ++#define VQTX_NUM (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x10) ++#define VQTX_SCH (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x18) ++#define VQTX_HASH_CFG (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x20) ++#define VQTX_HASH_SD (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x24) ++#define VQTX_VLD_CFG (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x30) ++#define VQTX_MIB_IF (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x3C) ++#define VQTX_MIB_PCNT (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x40) ++#define VQTX_MIB_BCNT0 (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x44) ++#define VQTX_MIB_BCNT1 (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x48) ++ #define VQTX_0_BIND_QID (PQ0 << 0) ++ #define VQTX_1_BIND_QID (PQ1 << 8) ++ #define VQTX_2_BIND_QID (PQ2 << 16) ++ #define VQTX_3_BIND_QID (PQ3 << 24) ++ #define VQTX_4_BIND_QID (PQ4 << 0) ++ #define VQTX_5_BIND_QID (PQ5 << 8) ++ #define VQTX_6_BIND_QID (PQ6 << 16) ++ #define VQTX_7_BIND_QID (PQ7 << 24) ++ ++#define VQTX_TB_BASE4 (NOE_REG_FRAME_ENGINE_BASE + 0x1990) ++#define VQTX_TB_BASE5 (NOE_REG_FRAME_ENGINE_BASE + 0x1994) ++#define VQTX_TB_BASE6 (NOE_REG_FRAME_ENGINE_BASE + 0x1998) ++#define VQTX_TB_BASE7 (NOE_REG_FRAME_ENGINE_BASE + 0x199C) ++#define VQTX_0_3_BIND_QID (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x140) ++#define VQTX_4_7_BIND_QID (NOE_REG_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x144) ++ ++ ++#define POLICY_TBL_BASE (NOE_REG_FRAME_ENGINE_BASE + POLICYTABLE_OFFSET) ++#define AC_BASE (NOE_REG_FRAME_ENGINE_BASE + 0x2000) ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// PPE_BASE Register Detail ++//------------------------------------------------------------------------------------------------- ++#define PPE_GLO_CFG (NOE_REG_PPE_BASE + 0x200) ++ #define DFL_TTL0_DRP (0) ++#define PPE_FLOW_CFG (NOE_REG_PPE_BASE + 0x204) ++#define PPE_FLOW_SET PPE_FLOW_CFG ++ #define BIT_FBC_FOE (1<<0) ++ #define BIT_FMC_FOE (1<<1) ++ #define BIT_FUC_FOE (1<<2) ++ #define BIT_UDP_IP4F_NAT_EN (1<<7) ++ #define BIT_IPV6_3T_ROUTE_EN (1<<8) ++ #define BIT_IPV6_5T_ROUTE_EN (1<<9) ++ #define BIT_IPV6_6RD_EN (1<<10) ++ #define BIT_IPV4_NAT_EN (1<<12) ++ #define BIT_IPV4_NAPT_EN (1<<13) ++ #define BIT_IPV4_DSL_EN (1<<14) ++ #define BIT_IP_PROT_CHK_BLIST (1<<16) ++ #define BIT_IPV4_NAT_FRAG_EN (1<<17) ++ #define BIT_IPV6_HASH_FLAB (1<<18) ++ #define BIT_IPV4_HASH_GREK (1<<19) ++ #define BIT_IPV6_HASH_GREK (1<<20) ++ ++#define PPE_IP_PROT_CHK (NOE_REG_PPE_BASE + 0x208) ++#define PPE_IP_PROT_0 (NOE_REG_PPE_BASE + 0x20C) ++#define PPE_IP_PROT_1 (NOE_REG_PPE_BASE + 0x210) ++#define PPE_IP_PROT_2 (NOE_REG_PPE_BASE + 0x214) ++#define PPE_IP_PROT_3 (NOE_REG_PPE_BASE + 0x218) ++#define PPE_TB_CFG (NOE_REG_PPE_BASE + 0x21C) ++#define PPE_FOE_CFG PPE_TB_CFG ++ #define FOE_SEARCH_MISS_DROP (0) ++ #define FOE_SEARCH_MISS_DROP2 (1) ++ #define FOE_SEARCH_MISS_ONLY_FWD_CPU (2) ++ #define FOE_SEARCH_MISS_FWD_CPU_BUILD_ENTRY (3) ++ ++ #define FOE_TBL_NUM_1K (0) ++ #define FOE_TBL_NUM_2K (1) ++ #define FOE_TBL_NUM_4K (2) ++ #define FOE_TBL_NUM_8K (3) ++ #define FOE_TBL_NUM_16K (4) ++ ++#define PPE_TB_BASE (NOE_REG_PPE_BASE + 0x220) ++#define PPE_FOE_BASE (PPE_TB_BASE) ++#define PPE_TB_USED (NOE_REG_PPE_BASE + 0x224) ++#define PPE_BNDR (NOE_REG_PPE_BASE + 0x228) ++#define PPE_FOE_BNDR PPE_BNDR ++#define PPE_BIND_LMT_0 (NOE_REG_PPE_BASE + 0x22C) ++#define PPE_FOE_LMT1 (PPE_BIND_LMT_0) ++#define PPE_BIND_LMT_1 (NOE_REG_PPE_BASE + 0x230) ++#define PPE_FOE_LMT2 PPE_BIND_LMT_1 ++#define PPE_KA (NOE_REG_PPE_BASE + 0x234) ++#define PPE_FOE_KA PPE_KA ++#define PPE_UNB_AGE (NOE_REG_PPE_BASE + 0x238) ++#define PPE_FOE_UNB_AGE PPE_UNB_AGE ++#define PPE_BND_AGE_0 (NOE_REG_PPE_BASE + 0x23C) ++#define PPE_FOE_BND_AGE0 PPE_BND_AGE_0 ++#define PPE_BND_AGE_1 (NOE_REG_PPE_BASE + 0x240) ++#define PPE_FOE_BND_AGE1 PPE_BND_AGE_1 ++#define PPE_HASH_SEED (NOE_REG_PPE_BASE + 0x244) ++ ++#define PPE_MCAST_L_10 (NOE_REG_PPE_BASE + 0x00) ++#define PPE_MCAST_H_10 (NOE_REG_PPE_BASE + 0x04) ++#define PPE_DFT_CPORT (NOE_REG_PPE_BASE + 0x248) ++#define PPE_MCAST_PPSE (NOE_REG_PPE_BASE + 0x284) ++#define PPE_MCAST_L_0 (NOE_REG_PPE_BASE + 0x288) ++#define PPE_MCAST_H_0 (NOE_REG_PPE_BASE + 0x28C) ++#define PPE_MCAST_L_1 (NOE_REG_PPE_BASE + 0x290) ++#define PPE_MCAST_H_1 (NOE_REG_PPE_BASE + 0x294) ++#define PPE_MCAST_L_2 (NOE_REG_PPE_BASE + 0x298) ++#define PPE_MCAST_H_2 (NOE_REG_PPE_BASE + 0x29C) ++#define PPE_MCAST_L_3 (NOE_REG_PPE_BASE + 0x2A0) ++#define PPE_MCAST_H_3 (NOE_REG_PPE_BASE + 0x2A4) ++#define PPE_MCAST_L_4 (NOE_REG_PPE_BASE + 0x2A8) ++#define PPE_MCAST_H_4 (NOE_REG_PPE_BASE + 0x2AC) ++#define PPE_MCAST_L_5 (NOE_REG_PPE_BASE + 0x2B0) ++#define PPE_MCAST_H_5 (NOE_REG_PPE_BASE + 0x2B4) ++#define PPE_MCAST_L_6 (NOE_REG_PPE_BASE + 0x2BC) ++#define PPE_MCAST_H_6 (NOE_REG_PPE_BASE + 0x2C0) ++#define PPE_MCAST_L_7 (NOE_REG_PPE_BASE + 0x2C4) ++#define PPE_MCAST_H_7 (NOE_REG_PPE_BASE + 0x2C8) ++#define PPE_MCAST_L_8 (NOE_REG_PPE_BASE + 0x2CC) ++#define PPE_MCAST_H_8 (NOE_REG_PPE_BASE + 0x2D0) ++#define PPE_MCAST_L_9 (NOE_REG_PPE_BASE + 0x2D4) ++#define PPE_MCAST_H_9 (NOE_REG_PPE_BASE + 0x2D8) ++#define PPE_MCAST_L_A (NOE_REG_PPE_BASE + 0x2DC) ++#define PPE_MCAST_H_A (NOE_REG_PPE_BASE + 0x2E0) ++#define PPE_MCAST_L_B (NOE_REG_PPE_BASE + 0x2E4) ++#define PPE_MCAST_H_B (NOE_REG_PPE_BASE + 0x2E8) ++#define PPE_MCAST_L_C (NOE_REG_PPE_BASE + 0x2EC) ++#define PPE_MCAST_H_C (NOE_REG_PPE_BASE + 0x2F0) ++#define PPE_MCAST_L_D (NOE_REG_PPE_BASE + 0x2F4) ++#define PPE_MCAST_H_D (NOE_REG_PPE_BASE + 0x2F8) ++#define PPE_MCAST_L_E (NOE_REG_PPE_BASE + 0x2FC) ++#define PPE_MCAST_H_E (NOE_REG_PPE_BASE + 0x2E0) ++#define PPE_MCAST_L_F (NOE_REG_PPE_BASE + 0x300) ++#define PPE_MCAST_H_F (NOE_REG_PPE_BASE + 0x304) ++#define PPE_MTU_DRP (NOE_REG_PPE_BASE + 0x308) ++#define PPE_MTU_VLYR_0 (NOE_REG_PPE_BASE + 0x30C) ++#define PPE_MTU_VLYR_1 (NOE_REG_PPE_BASE + 0x310) ++#define PPE_MTU_VLYR_2 (NOE_REG_PPE_BASE + 0x314) ++#define PPE_VPM_TPID (NOE_REG_PPE_BASE + 0x318) ++#define CAH_CTRL (NOE_REG_PPE_BASE + 0x320) ++#define CAH_TAG_SRH (NOE_REG_PPE_BASE + 0x324) ++#define CAH_LINE_RW (NOE_REG_PPE_BASE + 0x328) ++#define CAH_WDATA (NOE_REG_PPE_BASE + 0x32C) ++#define CAH_RDATA (NOE_REG_PPE_BASE + 0x330) ++ ++#define PS_CFG (NOE_REG_PPE_BASE + 0x400) ++#define PS_FBC (NOE_REG_PPE_BASE + 0x404) ++#define PS_TB_BASE (NOE_REG_PPE_BASE + 0x408) ++#define PS_TME_SMP (NOE_REG_PPE_BASE + 0x40C) ++ ++#define MIB_CFG (NOE_REG_PPE_BASE + 0x334) ++#define MIB_TB_BASE (NOE_REG_PPE_BASE + 0x338) ++#define MIB_SER_CR (NOE_REG_PPE_BASE + 0x33C) ++#define MIB_SER_R0 (NOE_REG_PPE_BASE + 0x340) ++#define MIB_SER_R1 (NOE_REG_PPE_BASE + 0x344) ++#define MIB_SER_R2 (NOE_REG_PPE_BASE + 0x348) ++#define MIB_CAH_CTRL (NOE_REG_PPE_BASE + 0x350) ++ ++//------------------------------------------------------------------------------------------------- ++// ETH_MAC_BASE Register Detail ++//------------------------------------------------------------------------------------------------- ++ ++#define PHY_CONTROL_0 0x0004 ++ ++ ++/* SW_INT_STATUS */ ++#define ESW_PHY_POLLING (NOE_REG_ETH_MAC_BASE + 0x0000) ++#define MDIO_PHY_CONTROL_0 (NOE_REG_ETH_MAC_BASE + PHY_CONTROL_0) ++#define NOE_MAC_P1_MCR (NOE_REG_ETH_MAC_BASE + 0x0100) ++#define NOE_MAC_P1_SR (NOE_REG_ETH_MAC_BASE + 0x0108) ++#define MAC1_WOL (NOE_REG_ETH_MAC_BASE + 0x0110) ++ #define WOL_INT_CLR BIT(17) ++ #define WOL_INT_EN BIT(1) ++ #define WOL_EN BIT(0) ++#define NOE_MAC_P2_MCR (NOE_REG_ETH_MAC_BASE + 0x0200) ++#define NOE_MAC_P2_SR (NOE_REG_ETH_MAC_BASE + 0x0208) ++ ++//------------------------------------------------------------------------------------------------- ++// ETH_SW_BASE Register Detail ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++ ++ ++ ++#define RSTCTL_FE_RST BIT(6) ++#define RSTCTL_SYS_RST BIT(0) ++#define RSTSTAT_SWSYSRST BIT(2) ++#define RLS_COHERENT BIT(29) ++#define RLS_DLY_INT BIT(28) ++#define RLS_DONE_INT BIT(0) ++ ++#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | TX_DONE_INT1 | TX_DONE_INT0 | RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3) ++#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3) ++#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT) ++#define RX_INT_ALL (RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3 | RX_DLY_INT) ++#define TX_INT_ALL (TX_DONE_INT0 | TX_DLY_INT) ++#define RX_INT_DONE (RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3) ++#define TX_INT_DONE (TX_DONE_INT3 | TX_DONE_INT2 | TX_DONE_INT1 | TX_DONE_INT0) ++ ++ ++ ++#define P5_LINK_CH BIT(5) ++#define P4_LINK_CH BIT(4) ++#define P3_LINK_CH BIT(3) ++#define P2_LINK_CH BIT(2) ++#define P1_LINK_CH BIT(1) ++#define P0_LINK_CH BIT(0) ++ ++#define RX_BUF_ALLOC_SIZE 2000 ++#define FASTPATH_HEADROOM 64 ++ ++#define ETHER_BUFFER_ALIGN 32 /* /// Align on a cache line */ ++ ++#define ETHER_ALIGNED_RX_SKB_ADDR(addr) ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr)) ++ ++ ++#define MAX_PSEUDO_ENTRY 1 ++ ++ ++ ++ ++ ++ ++#define DELAY_INT_INIT 0x8F0FBF1F //0x8F0FBF0F ++#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT) ++ ++ ++ ++/* LRO RX ring mode */ ++#define PDMA_RX_NORMAL_MODE (0x0) ++#define PDMA_RX_PSE_MODE (0x1) ++#define PDMA_RX_FORCE_PORT (0x2) ++#define PDMA_RX_AUTO_LEARN (0x3) ++ ++#define ADMA_RX_RING0 (0) ++#define ADMA_RX_RING1 (1) ++#define ADMA_RX_RING2 (2) ++#define ADMA_RX_RING3 (3) ++ ++#define ADMA_RX_LEN0_MASK (0x3fff) ++#define ADMA_RX_LEN1_MASK (0x3) ++ ++#define SET_ADMA_RX_LEN0(x) ((x) & ADMA_RX_LEN0_MASK) ++#define SET_ADMA_RX_LEN1(x) ((x) & ADMA_RX_LEN1_MASK) ++ ++#define PQ0 0 ++#define PQ1 1 ++#define PQ2 15 ++#define PQ3 16 ++#define PQ4 30 ++#define PQ5 31 ++#define PQ6 43 ++#define PQ7 63 ++ ++ ++#define VQ_NUM0 128 ++#define VQ_NUM1 128 ++#define VQ_NUM2 128 ++#define VQ_NUM3 128 ++#define VQ_NUM4 128 ++#define VQ_NUM5 128 ++#define VQ_NUM6 128 ++#define VQ_NUM7 128 ++#define VQTX_NUM_0 (3 << 0) ++#define VQTX_NUM_1 (3 << 4) ++#define VQTX_NUM_2 (3 << 8) ++#define VQTX_NUM_3 (3 << 12) ++#define VQTX_NUM_4 (3 << 16) ++#define VQTX_NUM_5 (3 << 20) ++#define VQTX_NUM_6 (3 << 24) ++#define VQTX_NUM_7 (3 << 28) ++ ++ ++#define VQTX_MIB_EN BIT(17) ++ ++ ++ ++ ++ ++#define GDM_PRI_PID (0) ++#define GDM_PRI_VLAN_PID (1) ++#define GDM_PRI_ACK_PID (2) ++#define GDM_PRI_VLAN_ACK_PID (3) ++#define GDM_PRI_ACK_VLAN_PID (4) ++ ++#define SET_GDM_VLAN_PRI_RXID_SEL(x, y) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ ++reg_val &= ~(0x03 << (((x) << 1) + 16)); \ ++reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \ ++sys_reg_write(FE_GDM_RXID1, reg_val); \ ++} ++ ++#define SET_GDM_TCP_ACK_RXID_SEL(x) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ ++reg_val &= ~(GDM_TCP_ACK_RXID_SEL); \ ++reg_val |= ((x) & 0x3) << 4; \ ++sys_reg_write(FE_GDM_RXID1, reg_val); \ ++} ++ ++#define SET_GDM_TCP_ACK_WZPC(x) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ ++reg_val &= ~(GDM_TCP_ACK_WZPC); \ ++reg_val |= ((x) & 0x1) << 3; \ ++sys_reg_write(FE_GDM_RXID1, reg_val); \ ++} ++ ++#define SET_GDM_RXID_PRI_SEL(x) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \ ++reg_val &= ~(GDM_RXID_PRI_SEL); \ ++reg_val |= (x) & 0x7; \ ++sys_reg_write(FE_GDM_RXID1, reg_val); \ ++} ++ ++#define GDM_STAG_RXID_SEL(x, y) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \ ++reg_val &= ~(0x03 << (((x) << 1) + 16)); \ ++reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \ ++sys_reg_write(FE_GDM_RXID2, reg_val); \ ++} ++ ++#define SET_GDM_PID2_RXID_SEL(x) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \ ++reg_val &= ~(GDM_PID2_RXID_SEL); \ ++reg_val |= ((x) & 0x3) << 2; \ ++sys_reg_write(FE_GDM_RXID2, reg_val); \ ++} ++ ++#define SET_GDM_PID1_RXID_SEL(x) \ ++{ \ ++unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \ ++reg_val &= ~(GDM_PID1_RXID_SEL); \ ++reg_val |= ((x) & 0x3); \ ++sys_reg_write(FE_GDM_RXID2, reg_val); \ ++} ++ ++ ++ ++#define PORT0_PKCOUNT (0xb01100e8) ++#define PORT1_PKCOUNT (0xb01100ec) ++#define PORT2_PKCOUNT (0xb01100f0) ++#define PORT3_PKCOUNT (0xb01100f4) ++#define PORT4_PKCOUNT (0xb01100f8) ++#define PORT5_PKCOUNT (0xb01100fc) ++ ++ ++/* ====================================== */ ++#define GDM1_DISPAD BIT(18) ++#define GDM1_DISCRC BIT(17) ++ ++#define GDM1_ICS_EN (0x1 << 22) ++#define GDM1_TCS_EN (0x1 << 21) ++#define GDM1_UCS_EN (0x1 << 20) ++#define GDM1_JMB_EN (0x1 << 19) ++#define GDM1_STRPCRC (0x1 << 16) ++ ++#if defined (CONFIG_NOE_QDMATX_QDMARX) ++#define GDM1_UFRC_P_CPU (5 << 12) ++#else ++#define GDM1_UFRC_P_CPU (0 << 12) ++#endif /* CONFIG_NOE_QDMATX_QDMARX */ ++#define GDM1_UFRC_P_PPE (4 << 12) ++ ++#if defined (CONFIG_NOE_QDMATX_QDMARX) ++#define GDM1_BFRC_P_CPU (5 << 8) ++#else ++#define GDM1_BFRC_P_CPU (0 << 8) ++#endif /* CONFIG_NOE_QDMATX_QDMARX */ ++#define GDM1_BFRC_P_PPE (4 << 8) ++ ++#if defined (CONFIG_NOE_QDMATX_QDMARX) ++#define GDM1_MFRC_P_CPU (5 << 4) ++#else ++#define GDM1_MFRC_P_CPU (0 << 4) ++#endif /* CONFIG_NOE_QDMATX_QDMARX */ ++#define GDM1_MFRC_P_PPE (4 << 4) ++ ++#if defined (CONFIG_NOE_QDMATX_QDMARX) ++#define GDM1_OFRC_P_CPU (5 << 0) ++#else ++#define GDM1_OFRC_P_CPU (0 << 0) ++#endif /* CONFIG_NOE_QDMATX_QDMARX */ ++#define GDM1_OFRC_P_PPE (4 << 0) ++ ++#define ICS_GEN_EN (0 << 2) ++#define UCS_GEN_EN (0 << 1) ++#define TCS_GEN_EN (0 << 0) ++ ++#define MDIO_CFG_GP1_FC_TX BIT(11) ++#define MDIO_CFG_GP1_FC_RX BIT(10) ++ ++/* ====================================== */ ++/* ====================================== */ ++#define GP1_LNK_DWN BIT(9) ++#define GP1_AN_FAIL BIT(8) ++/* ====================================== */ ++/* ====================================== */ ++#define PSE_RESET BIT(0) ++/* ====================================== */ ++#define PST_DRX_IDX3 BIT(19) ++#define PST_DRX_IDX2 BIT(18) ++#define PST_DRX_IDX1 BIT(17) ++#define PST_DRX_IDX0 BIT(16) ++#define PST_DTX_IDX3 BIT(3) ++#define PST_DTX_IDX2 BIT(2) ++#define PST_DTX_IDX1 BIT(1) ++#define PST_DTX_IDX0 BIT(0) ++ ++#define RX_2B_OFFSET BIT(31) ++#define CSR_CLKGATE_BYP BIT(30) ++#define MULTI_EN BIT(10) ++#define DESC_32B_EN BIT(8) ++#define TX_WB_DDONE BIT(6) ++#define RX_DMA_BUSY BIT(3) ++#define TX_DMA_BUSY BIT(1) ++#define RX_DMA_EN BIT(2) ++#define TX_DMA_EN BIT(0) ++ ++#define PDMA_BT_SIZE_4DWORDS (0 << 4) ++#define PDMA_BT_SIZE_8DWORDS (1 << 4) ++#define PDMA_BT_SIZE_16DWORDS (2 << 4) ++#define PDMA_BT_SIZE_32DWORDS (3 << 4) ++ ++#define ADMA_RX_BT_SIZE_4DWORDS (0 << 11) ++#define ADMA_RX_BT_SIZE_8DWORDS (1 << 11) ++#define ADMA_RX_BT_SIZE_16DWORDS (2 << 11) ++#define ADMA_RX_BT_SIZE_32DWORDS (3 << 11) ++ ++/* Register bits. ++ */ ++ ++#define MACCFG_RXEN BIT(2) ++#define MACCFG_TXEN BIT(3) ++#define MACCFG_PROMISC BIT(18) ++#define MACCFG_RXMCAST BIT(19) ++#define MACCFG_FDUPLEX BIT(20) ++#define MACCFG_PORTSEL BIT(27) ++#define MACCFG_HBEATDIS BIT(28) ++ ++#define DMACTL_SR BIT(1) /* Start/Stop Receive */ ++#define DMACTL_ST BIT(13) /* Start/Stop Transmission Command */ ++ ++#define DMACFG_SWR BIT(0) /* Software Reset */ ++#define DMACFG_BURST32 (32 << 8) ++ ++#define DMASTAT_TS 0x00700000 /* Transmit Process State */ ++#define DMASTAT_RS 0x000e0000 /* Receive Process State */ ++ ++#define MACCFG_INIT 0 /* (MACCFG_FDUPLEX) // | MACCFG_PORTSEL) */ ++ ++/* Descriptor bits. ++ */ ++#define R_OWN 0x80000000 /* Own Bit */ ++#define RD_RER 0x02000000 /* Receive End Of Ring */ ++#define RD_LS 0x00000100 /* Last Descriptor */ ++#define RD_ES 0x00008000 /* Error Summary */ ++#define RD_CHAIN 0x01000000 /* Chained */ ++ ++/* Word 0 */ ++#define T_OWN 0x80000000 /* Own Bit */ ++#define TD_ES 0x00008000 /* Error Summary */ ++ ++/* Word 1 */ ++#define TD_LS 0x40000000 /* Last Segment */ ++#define TD_FS 0x20000000 /* First Segment */ ++#define TD_TER 0x08000000 /* Transmit End Of Ring */ ++#define TD_CHAIN 0x01000000 /* Chained */ ++ ++#define TD_SET 0x08000000 /* Setup Packet */ ++ ++#define POLL_DEMAND 1 ++ ++#define RSTCTL (0x34) ++#define RSTCTL_RSTENET1 BIT(19) ++#define RSTCTL_RSTENET2 BIT(20) ++ ++//#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000 ++#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000 ++#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01 ++#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01 ++ ++ ++ ++ ++ ++#define PHY_ENABLE_AUTO_NEGO 0x1000 ++#define PHY_RESTART_AUTO_NEGO 0x0200 ++ ++/* PHY_STAT_REG = 1; */ ++#define PHY_AUTO_NEGO_COMP 0x0020 ++#define PHY_LINK_STATUS 0x0004 ++ ++/* PHY_AUTO_NEGO_REG = 4; */ ++#define PHY_CAP_10_HALF 0x0020 ++#define PHY_CAP_10_FULL 0x0040 ++#define PHY_CAP_100_HALF 0x0080 ++#define PHY_CAP_100_FULL 0x0100 ++ ++ ++ ++ ++ ++ ++#define DMA_GLO_CFG PDMA_GLO_CFG ++ ++#if defined(CONFIG_NOE_QDMATX_QDMARX) ++#define GDMA1_FWD_PORT 0x5555 ++#define GDMA2_FWD_PORT 0x5555 ++#elif defined(CONFIG_NOE_PDMATX_QDMARX) ++#define GDMA1_FWD_PORT 0x5555 ++#define GDMA2_FWD_PORT 0x5555 ++#else ++#define GDMA1_FWD_PORT 0x0000 ++#define GDMA2_FWD_PORT 0x0000 ++#endif ++ ++#if defined(CONFIG_NOE_QDMATX_QDMARX) ++#define CONFIG_NOE_REG_RX_CALC_IDX0 QRX_CRX_IDX_0 ++#define CONFIG_NOE_REG_RX_CALC_IDX1 QRX_CRX_IDX_1 ++#elif defined(CONFIG_NOE_PDMATX_QDMARX) ++#define CONFIG_NOE_REG_RX_CALC_IDX0 QRX_CRX_IDX_0 ++#define CONFIG_NOE_REG_RX_CALC_IDX1 QRX_CRX_IDX_1 ++#else ++#define CONFIG_NOE_REG_RX_CALC_IDX0 RX_CALC_IDX0 ++#define CONFIG_NOE_REG_RX_CALC_IDX1 RX_CALC_IDX1 ++#endif ++#define CONFIG_NOE_REG_RX_CALC_IDX2 RX_CALC_IDX2 ++#define CONFIG_NOE_REG_RX_CALC_IDX3 RX_CALC_IDX3 ++#define CONFIG_NOE_REG_FE_INT_STATUS FE_INT_STATUS ++#define CONFIG_NOE_REG_FE_INT_ALL FE_INT_ALL ++#define CONFIG_NOE_REG_FE_INT_ENABLE FE_INT_ENABLE ++#define CONFIG_NOE_REG_FE_INT_DLY_INIT FE_INT_DLY_INIT ++#define CONFIG_NOE_REG_FE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3) ++#define QFE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3) ++#define CONFIG_NOE_REG_TX_DLY_INT TX_DLY_INT ++#define CONFIG_NOE_REG_TX_DONE_INT0 TX_DONE_INT0 ++#define CONFIG_NOE_REG_DLY_INT_CFG DLY_INT_CFG ++ ++ ++#define QUEUE_OFFSET 0x10 ++ ++ ++#define IP_PROTO_GRE 47 ++#define IP_PROTO_TCP 6 ++#define IP_PROTO_UDP 17 ++#define IP_PROTO_IPV6 41 ++ ++ ++ ++#endif /* MHAL_NOE_REG_H */ +diff --git a/drivers/sstar/noe/hal/infinity2/mhal_porting.h b/drivers/sstar/noe/hal/infinity2/mhal_porting.h +new file mode 100755 +index 000000000000..c97f1fc3407c +--- /dev/null ++++ b/drivers/sstar/noe/hal/infinity2/mhal_porting.h +@@ -0,0 +1,50 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (“MStar Confidential Informationâ€) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_porting.h ++/// @brief NOE Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef MHAL_NOE_PORTING_H ++#define MHAL_NOE_PORTING_H ++ ++#include "mdrv_types.h" ++ ++#ifndef MS_BOOL ++#define MS_BOOL BOOL ++#endif ++#ifndef MS_PHYADDR ++typedef size_t MS_PHYADDR; ++#endif ++#ifndef MS_U8 ++#define MS_U8 U8 ++#endif ++#ifndef MS_U16 ++#define MS_U16 U16 ++#endif ++#ifndef MS_U32 ++#define MS_U32 U32 ++#endif ++#ifndef MS_U64 ++#define MS_U64 U64 ++#endif ++ ++ ++#endif +diff --git a/drivers/sstar/notify/Kconfig b/drivers/sstar/notify/Kconfig +new file mode 100755 +index 000000000000..bb3bf60e9111 +--- /dev/null ++++ b/drivers/sstar/notify/Kconfig +@@ -0,0 +1,2 @@ ++config MS_NOTIFY ++ tristate "Mstar NOTIFY driver" +diff --git a/drivers/sstar/notify/Makefile b/drivers/sstar/notify/Makefile +new file mode 100755 +index 000000000000..0c751b06053e +--- /dev/null ++++ b/drivers/sstar/notify/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MS_NOTIFY) += ms_notify.o +diff --git a/drivers/sstar/notify/ms_notify.c b/drivers/sstar/notify/ms_notify.c +new file mode 100755 +index 000000000000..213cd830b3cb +--- /dev/null ++++ b/drivers/sstar/notify/ms_notify.c +@@ -0,0 +1,114 @@ ++/* ++* ms_notify.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAX_PAYLOAD 256 ++ ++static struct sock *_st_notify_sock; ++ ++static void _notify_reply(struct sk_buff * __skb) ++{ ++ struct nlmsghdr *nlh; ++ struct sk_buff *skb; ++ ++ unsigned char msg[MAX_PAYLOAD] = {0}; ++ ++ //int res; ++ ++ do ++ { ++ skb = skb_get(__skb); ++ ++ if (skb->len < NLMSG_SPACE(0)) ++ { ++ break; ++ } ++ ++ nlh = nlmsg_hdr(skb); ++ ++ #if 0 ++ printk("recv skb from user space uid: %d pid: %d seq: %d\n", NETLINK_CREDS(skb)->uid, NETLINK_CREDS(skb)->pid, nlh->nlmsg_seq); ++ #endif ++ ++ memcpy(msg, NLMSG_DATA(nlh), sizeof(msg)); ++ ++ kfree_skb(skb); ++ ++ if (NULL == (skb = alloc_skb(NLMSG_SPACE(MAX_PAYLOAD), GFP_ATOMIC))) ++ { ++ break; ++ } ++ ++ if (NULL == (nlh = nlmsg_put(skb, 0, 0, 0, MAX_PAYLOAD, 0))) ++ { ++ break; ++ } ++ ++ nlh->nlmsg_flags = 0; ++ memcpy(NLMSG_DATA(nlh), msg, MAX_PAYLOAD); ++ NETLINK_CB(skb).portid = 0; ++ NETLINK_CB(skb).dst_group = 1; ++ netlink_broadcast(_st_notify_sock, skb, 0, 1, GFP_ATOMIC); ++ //kfree_skb(skb); ++ return; ++ } while (0); ++ ++//nlmsg_failure: /* Used by NLMSG_PUT */ ++ if (skb) ++ { ++ kfree_skb(skb); ++ } ++ ++} ++ ++static int __init _notify_init(void) ++{ ++ struct netlink_kernel_cfg cfg = { ++ .groups = 0, ++ .input = _notify_reply, ++ }; ++ ++ if (NULL == (_st_notify_sock = netlink_kernel_create(&init_net, NETLINK_USERSOCK, &cfg))) ++ { ++ return -1; ++ } ++ ++ printk("mstar notify driver install successfully\n"); ++ return 0; ++} ++ ++static void __exit _notify_exit(void) ++{ ++ ++ netlink_kernel_release(_st_notify_sock); ++ ++ printk("mstar notify driver remove successfully\n"); ++} ++ ++module_init(_notify_init); ++module_exit(_notify_exit); ++ ++MODULE_DESCRIPTION("notify reply server module"); ++MODULE_AUTHOR("SSTAR"); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/sstar/padmux/Kconfig b/drivers/sstar/padmux/Kconfig +new file mode 100755 +index 000000000000..782426081e32 +--- /dev/null ++++ b/drivers/sstar/padmux/Kconfig +@@ -0,0 +1,4 @@ ++config MS_PADMUX ++ bool ++ default y ++ +diff --git a/drivers/sstar/padmux/Makefile b/drivers/sstar/padmux/Makefile +new file mode 100755 +index 000000000000..532975c0d678 +--- /dev/null ++++ b/drivers/sstar/padmux/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for MStar padmux device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/padmux ++EXTRA_CFLAGS += -Idrivers/sstar/padmux/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mdrv_padmux.o ++# obj-$(CONFIG_MS_GPIO) += $(CONFIG_SSTAR_CHIP_NAME)/mhal_gpio.o ++# obj-$(CONFIG_MS_GPIO) += $(CONFIG_SSTAR_CHIP_NAME)/mhal_pinmux.o ++# obj-$(CONFIG_MS_SW_I2C) += ms_gpioi2c.o mdrv_sw_iic.o +diff --git a/drivers/sstar/padmux/mdrv_padmux.c b/drivers/sstar/padmux/mdrv_padmux.c +new file mode 100755 +index 000000000000..e7870dfb2f5c +--- /dev/null ++++ b/drivers/sstar/padmux/mdrv_padmux.c +@@ -0,0 +1,200 @@ ++/* ++* mdrv_padmux.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_types.h" ++#include "mdrv_puse.h" ++#include "gpio.h" ++#include "padmux.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++#define PADINFO_ENABLE 0 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if PADINFO_ENABLE ++ #define PAD_PRINT(x, args...) { printk(x, ##args); } ++#else ++ #define PAD_PRINT(x, args...) { } ++#endif ++ ++ ++#define PADINFO_NAME "schematic" ++ ++typedef struct ++{ ++ U32 u32PadId; ++ U32 u32Mode; ++ U32 u32Puse; ++} __attribute__ ((__packed__)) pad_info_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static int _nPad = 0; ++static pad_info_t* _pPadInfo = NULL; ++ ++//------------------------------------------------------------------------------------------------- ++// Implementation ++//------------------------------------------------------------------------------------------------- ++int mdrv_padmux_active(void) ++{ ++ return (_pPadInfo) ? 1: 0; ++} ++EXPORT_SYMBOL(mdrv_padmux_active); ++ ++int mdrv_padmux_getpad(int puse) ++{ ++ int i; ++ ++ if (MDRV_PUSE_NA == puse) ++ return PAD_UNKNOWN; ++ ++ for (i = 0; i < _nPad; i++) ++ { ++ if (_pPadInfo[i].u32Puse == puse) ++ return _pPadInfo[i].u32PadId; ++ } ++ return PAD_UNKNOWN; ++} ++EXPORT_SYMBOL(mdrv_padmux_getpad); ++ ++int mdrv_padmux_getmode(int puse) ++{ ++ int i; ++ ++ if (MDRV_PUSE_NA == puse) ++ return PINMUX_FOR_UNKNOWN_MODE; ++ ++ for (i = 0; i < _nPad; i++) ++ { ++ if (_pPadInfo[i].u32Puse == puse) ++ return _pPadInfo[i].u32Mode; ++ } ++ return PINMUX_FOR_UNKNOWN_MODE; ++} ++EXPORT_SYMBOL(mdrv_padmux_getmode); ++ ++extern int MDrv_GPIO_PadVal_Set(U8 u8IndexGPIO, U32 u32PadMode); ++static int _mdrv_padmux_dts(struct device_node* np) ++{ ++ int nPad; ++ ++ if (0 >= (nPad = of_property_count_elems_of_size(np, PADINFO_NAME, sizeof(pad_info_t)))) ++ { ++ PAD_PRINT("[%s][%d] invalid dts of padmux.schematic\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ if (NULL == (_pPadInfo = kmalloc(nPad*sizeof(pad_info_t), GFP_KERNEL))) ++ { ++ PAD_PRINT("[%s][%d] kmalloc fail\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ if (of_property_read_u32_array(np, PADINFO_NAME, (u32*)_pPadInfo, nPad*sizeof(pad_info_t)/sizeof(U32))) ++ { ++ PAD_PRINT("[%s][%d] of_property_read_u32_array fail\n", __FUNCTION__, __LINE__); ++ kfree(_pPadInfo); ++ _pPadInfo = NULL; ++ return -1; ++ } ++ _nPad = nPad; ++#if 1 ++ { ++ int i; ++ PAD_PRINT("[%s][%d] *******************************\n", __FUNCTION__, __LINE__); ++ for (i = 0; i < _nPad; i++) ++ { ++ PAD_PRINT("[%s][%d] (PadId, Mode, Puse) = (%d, 0x%02x, 0x%08x)\n", __FUNCTION__, __LINE__, ++ _pPadInfo[i].u32PadId, ++ _pPadInfo[i].u32Mode, ++ _pPadInfo[i].u32Puse); ++ MDrv_GPIO_PadVal_Set((U8)_pPadInfo[i].u32PadId & 0xFF, _pPadInfo[i].u32Mode); ++ } ++ PAD_PRINT("[%s][%d] *******************************\n", __FUNCTION__, __LINE__); ++ } ++#endif ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int sstar_padmux_suspend(struct device *dev) ++{ ++ PAD_PRINT("%s\r\n", __FUNCTION__); ++ if (_pPadInfo) { ++ kfree(_pPadInfo); ++ _pPadInfo = NULL; ++ } ++ return 0; ++} ++ ++static int sstar_padmux_resume(struct device *dev) ++{ ++ PAD_PRINT("%s\r\n", __FUNCTION__); ++ _mdrv_padmux_dts(dev->of_node); ++ return 0; ++} ++#else ++#define sstar_padmux_suspend NULL ++#define sstar_padmux_resume NULL ++#endif ++ ++ ++static int sstar_padmux_probe(struct platform_device *pdev) ++{ ++ _mdrv_padmux_dts(pdev->dev.of_node); ++ return 0; ++} ++ ++static const struct of_device_id sstar_padmux_of_match[] = { ++ { .compatible = "sstar-padmux" }, ++ { }, ++}; ++ ++static const struct dev_pm_ops sstar_padmux_pm_ops = { ++ .suspend = sstar_padmux_suspend, ++ .resume = sstar_padmux_resume, ++}; ++ ++static struct platform_driver sstar_padmux_driver = { ++ .driver = { ++ .name = "padmux", ++ .owner = THIS_MODULE, ++ .of_match_table = sstar_padmux_of_match, ++ .pm = &sstar_padmux_pm_ops, ++ }, ++ .probe = sstar_padmux_probe, ++}; ++ ++static int __init sstar_padmux_init(void) ++{ ++ return platform_driver_register(&sstar_padmux_driver); ++} ++postcore_initcall_sync(sstar_padmux_init); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("padmux driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/pwm/Kconfig b/drivers/sstar/pwm/Kconfig +new file mode 100755 +index 000000000000..7ccfe59e9af6 +--- /dev/null ++++ b/drivers/sstar/pwm/Kconfig +@@ -0,0 +1,25 @@ ++config MS_PWM ++ ++tristate "SSTAR_PWM" ++ ++ help ++ Say Y here to enable the driver for the PWM. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mdrv_ts. ++ ++select PWM ++ ++help ++ SStar PWM driver function ++ ++if MS_PWM ++config PWM_NEW ++ bool "Support NEW PWM configuration" ++ default n ++ help ++ Support NEW PWM configuration ++endif ++ +diff --git a/drivers/sstar/pwm/Makefile b/drivers/sstar/pwm/Makefile +new file mode 100755 +index 000000000000..c40532cfea62 +--- /dev/null ++++ b/drivers/sstar/pwm/Makefile +@@ -0,0 +1,14 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# specific options ++#EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/pwm/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# files ++obj-$(CONFIG_MS_PWM) += ms_pwm.o ++ms_pwm-y += mdrv_pwm.o $(CONFIG_SSTAR_CHIP_NAME)/mhal_pwm.o ++ +diff --git a/drivers/sstar/pwm/infinity/mhal_pwm.c b/drivers/sstar/pwm/infinity/mhal_pwm.c +new file mode 100644 +index 000000000000..6eea632f2934 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity/mhal_pwm.c +@@ -0,0 +1,372 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "registers.h" ++#include "mhal_pwm.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ //Dummy func ++} ++//---[Only4I6e] ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDuty ++// ++// Description ++// Set Duty value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Duty value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetDuty( U8 u8Id, U16 u16Val ) ++{ ++ U32 u32Period = 0x00000000; ++ U16 u16Duty = 0x0000; ++ ++ u16Val = u16Val & PWM_DUTY_MASK; ++ ++ if( PWM0 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM0_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM0_DUTY, u16Duty); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM1_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM1_DUTY, u16Duty); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM2_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM2_DUTY, u16Duty); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM3_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM3_DUTY, u16Duty); ++ } ++ else ++ { ++ printk(KERN_INFO "DrvPWMSetDuty error!!!! (%x, %x)\r\n", u8Id, u16Val); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetPeriod( U8 u8Id, U16 u16Val ) ++{ ++ U32 u32TempValue; ++ ++ u32TempValue=DEFAULT_PWM_CLK/u16Val; ++ u16Val = u32TempValue & PWM_PERIOD_MASK; ++ ++ printk(KERN_INFO "DrvPWMSetPeriod !!!! (%x, %x)\r\n", u32TempValue, u16Val); ++ ++ if( PWM0 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM0_PERIOD, u16Val); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM1_PERIOD, u16Val); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM2_PERIOD, u16Val); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM3_PERIOD, u16Val); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetPeriod error!!!! (%x, %x)\r\n", u8Id, u16Val); ++ } ++ ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetPolarity( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM0_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM1_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM2_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM3_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetPolarity error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++ ++} ++ ++void DrvPWMSetFreqDiv( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM0_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM1_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM2_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM3_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetDiv error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++ ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDben ++// ++// Description ++// Enable/Disable Dben function ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] On/Off value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetDben( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM0_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM1_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM2_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM3_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetDben error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++ ++} ++ ++void DrvPWMEnable( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ //reg_pwm0_mode = BIT[1:0] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, u8Val, 0x3); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ //reg_pwm1_mode=BIT[3:2] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, (u8Val<<2), 0xC); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ //reg_pwm2_mode=BIT[4] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, (u8Val<<4), 0x10); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ //reg_pwm3_mode=BIT[6] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, (u8Val<<6), 0x40); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMEnable error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++} ++ ++//+++[Only4I6e] ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip) ++{ ++#if 0 ++ return INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 0 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMInit ++// ++// Description ++// PWM init function ++// ++// Parameters ++// u8CustLevel: [in] Cust Level ++// ++// Return Value ++// None ++//------------------------------------------------------------------------------ ++void DrvPWMInit( U8 u8Id ) ++{ ++ //printk(KERN_INFO "+DrvPWMInit\r\n"); ++ ++ DrvPWMSetFreqDiv( u8Id, DEFAULT_DIV_CNT ); ++ //DrvPWMSetPeriod( u8Id, DEFAULT_PERIOD ); ++ ++ DrvPWMSetPolarity( u8Id, DEFAULT_POLARITY ); ++ ++ DrvPWMSetDben( u8Id, DEFAULT_DBEN ); ++ ++ //printk(KERN_INFO "-DrvPWMInit\r\n"); ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++ //Only4i6e ++ return IRQ_NONE; ++} +\ No newline at end of file +diff --git a/drivers/sstar/pwm/infinity/mhal_pwm.h b/drivers/sstar/pwm/infinity/mhal_pwm.h +new file mode 100755 +index 000000000000..c72184657e0c +--- /dev/null ++++ b/drivers/sstar/pwm/infinity/mhal_pwm.h +@@ -0,0 +1,126 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++//PWM0 ++#define u16REG_PWM0_DIV BK_REG(0x68) ++#define u16REG_RESERVED_4 BK_REG(0x68) ++ ++#define u16REG_PWM0_DUTY BK_REG(0x69) ++#define u16REG_RESERVED_3 BK_REG(0x69) ++ ++#define u16REG_PWM0_PERIOD BK_REG(0x6A) ++#define u16REG_RESERVED_2 BK_REG(0x6A) ++ ++//PWM1 ++#define u16REG_PWM1_DIV BK_REG(0x6B) ++#define u16REG_RESERVED_7 BK_REG(0x6B) ++ ++#define u16REG_PWM1_DUTY BK_REG(0x6C) ++#define u16REG_RESERVED_6 BK_REG(0x6C) ++ ++#define u16REG_PWM1_PERIOD BK_REG(0x6D) ++#define u16REG_RESERVED_5 BK_REG(0x6D) ++ ++//PWM2 ++#define u16REG_PWM2_DIV BK_REG(0x78) ++#define u16REG_RESERVED_A BK_REG(0x78) ++ ++#define u16REG_PWM2_DUTY BK_REG(0x79) ++#define u16REG_RESERVED_9 BK_REG(0x79) ++ ++#define u16REG_PWM2_PERIOD BK_REG(0x7A) ++#define u16REG_RESERVED_8 BK_REG(0x7A) ++ ++//PWM3 ++#define u16REG_PWM3_PERIOD BK_REG(0x7B) ++#define u16REG_RESERVED_B BK_REG(0x7B) ++ ++#define u16REG_PWM3_DUTY BK_REG(0x7C) ++#define u16REG_RESERVED_C BK_REG(0x7C) ++ ++#define u16REG_PWM3_DIV BK_REG(0x7D) ++#define u16REG_RESERVED_D BK_REG(0x7D) ++ ++///////////////////////////////////////// ++ ++//#define DEFAULT_PWM_ID ++ ++// For future reference ++#define DEFAULT_PWM_CLK 12000000 ++#define DEFAULT_DIV_CNT 0// 0.000001 X 250 = 0.00025 sec = 0.25 ms ++#define DEFAULT_PERIOD 101//=0X2EE0 => 1ms{1000HZ=12000000/12000} ++ ++ ++#define DEFAULT_POLARITY 1 // 1 => 0 - L - duty - H - period, 0 => 0 - H - duty - L - period ++#define DEFAULT_DBEN 0 // double buffer for Period Reset ++ ++#define PWM0 0x00 ++#define PWM1 0x01 ++#define PWM2 0x02 ++#define PWM3 0x03 ++#define PWM4 0x04 ++#define PWM5 0x05 ++#define PMW_DEFAULT 0xFF ++ ++//PWMX_CTRL ++#define PWM_CTRL_DIV_MSAK 0x000000FF ++#define PWM_CTRL_POLARITY 0x00000100 ++#define PWM_CTRL_DBEN 0x00001000 ++ ++//Mask ++#define PWM_PERIOD_MASK 0x0000FFFF ++#define PWM_DUTY_MASK PWM_PERIOD_MASK ++#define PWM_CTRL_MASK 0x000015FF //0001 0101 1111 1111, BIT9,11,12 will not be tested ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriod( U8 u8Id, U16 u16Val ); ++void DrvPWMSetDuty( U8 u8Id, U16 u16Val ); ++void DrvPWMEnable( U8 u8Id, U8 u8Val); ++void DrvPWMSetPolarity( U8 u8Id, U8 u8Val ); ++ ++//+++[Only4I6e] ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val); ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity2/mhal_pwm.c b/drivers/sstar/pwm/infinity2/mhal_pwm.c +new file mode 100644 +index 000000000000..44008010e12c +--- /dev/null ++++ b/drivers/sstar/pwm/infinity2/mhal_pwm.c +@@ -0,0 +1,865 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++#define BASE_REG_NULL 0xFFFFFFFF ++ ++static U8 _pwmEnSatus[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod[PWM_NUM] = { 0 }; ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ //Dummy func ++} ++//---[Only4I6e] ++ ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id) ++{ ++ U32 reset, u32Period; ++ ++ if (PWM_NUM <= u8Id) ++ return; ++ ++ reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++ ++ if (_pwmEnSatus[u8Id]) ++ { ++ U32 reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, 1<base + (u8Id*0x80) + u16REG_PWM_DUTY_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if (u32Duty) ++ { ++ U32 u32Period = _pwmPeriod[u8Id]; ++ // DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++ if (u32Period) ++ { ++ *pu32Val = (u32Duty * 100)/u32Period; ++ } ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) { ++ u32Period = 2; ++ } ++ else if(u32Period > 262144) { ++ u32Period = 262144; ++ } ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Period; ++ ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if ((0 == _pwmPeriod[u8Id]) && (u32Period)) ++ { ++ _pwmPeriod[u8Id] = u32Period; ++ } ++ *pu32Val = 0; ++ if (u32Period) ++ { ++ *pu32Val = (U32)(clk_get_rate(ms_chip->clk))/(u32Period+1); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL) & (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_DUTY_L); ++ U32 u32DutyH = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H); ++ if (u32DutyL || u32DutyH) ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<regSet; ++// printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++// printk("[%s][%d] pad Id = %d\n", __FUNCTION__, __LINE__, pTbl->u32PadId); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++// if (PAD_UNKNOWN == pTbl->u32PadId) ++// { ++// break; ++// } ++// pTbl++; ++// } ++// } ++//} ++ ++void DrvPWMPadSet(U8 u8Id, U8 u8Val) ++{ ++ //reg_pwm0_mode [1:0] ++ //reg_pwm1_mode [3:2] ++ //reg_pwm2_mode [5:4] ++ //reg_pwm3_mode [7:6] ++ //reg_pwm4_mode [9:8] ++ //reg_pwm5_mode [11:10] ++ //reg_pwm6_mode [13:12] ++ //reg_pwm7_mode [15:14] ++ if( 0 == u8Id ) ++ { ++ if(u8Val==PAD_PWM0){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT0, BIT1|BIT0); ++ }else if(u8Val==PAD_MIPI_TX_IO0){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT1, BIT1|BIT0); ++ }else if(u8Val==PAD_SNR3_D0){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT1|BIT0, BIT1|BIT0); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT1|BIT0); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ } ++ } ++ else if( 1 == u8Id ) ++ { ++ if(u8Val==PAD_PWM1){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT2, BIT2|BIT3); ++ }else if(u8Val==PAD_MIPI_TX_IO1){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT3, BIT2|BIT3); ++ }else if(u8Val==PAD_SNR3_D1){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT2|BIT3, BIT2|BIT3); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT2|BIT3); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ } ++ ++ } ++ else if( 2 == u8Id ) ++ { ++ if(u8Val==PAD_GPIO8){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT4, BIT5|BIT4); ++ }else if(u8Val==PAD_MIPI_TX_IO2){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT5, BIT5|BIT4); ++ }else if(u8Val==PAD_SNR3_D2){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT5|BIT4, BIT5|BIT4); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT5|BIT4); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ ++ } ++ } ++ else if( 3 == u8Id ) ++ { ++ if(u8Val==PAD_GPIO9){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT6, BIT7|BIT6); ++ }else if(u8Val==PAD_MIPI_TX_IO3){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT7, BIT7|BIT6); ++ }else if(u8Val==PAD_SNR3_D3){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT7|BIT6, BIT7|BIT6); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT7|BIT6); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ } ++ } ++ else if( 4 == u8Id ) ++ { ++ if(u8Val==PAD_GPIO10){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT8, BIT9|BIT8); ++ }else if(u8Val==PAD_MIPI_TX_IO4){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT9, BIT9|BIT8); ++ }else if(u8Val==PAD_SNR3_D8){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT9|BIT8, BIT9|BIT8); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT9|BIT8); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ } ++ } ++ else if( 5 == u8Id ) ++ { ++ if(u8Val==PAD_GPIO11){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT10, BIT11|BIT10); ++ }else if(u8Val==PAD_MIPI_TX_IO5){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT11, BIT11|BIT10); ++ }else if(u8Val==PAD_SNR3_D9){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT11|BIT10, BIT11|BIT10); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT11|BIT10); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ ++ } ++ } ++ else if( 6 == u8Id ) ++ { ++ if(u8Val==PAD_GPIO12){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT12, BIT13|BIT12); ++ }else if(u8Val==PAD_MIPI_TX_IO6){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT13, BIT13|BIT12); ++ }else if(u8Val==PAD_PM_LED0){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT13|BIT12, BIT13|BIT12); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT13|BIT12); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ ++ } ++ } ++ else if( 7 == u8Id ) ++ { ++ if(u8Val==PAD_GPIO13){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT14, BIT15|BIT14); ++ }else if(u8Val==PAD_MIPI_TX_IO7){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT15, BIT15|BIT14); ++ }else if(u8Val==PAD_PM_LED1){ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, BIT15|BIT14, BIT15|BIT14); ++ }else{ ++ OUTREGMSK16(BASE_REG_PADTOP1_PA + REG_ID_09, 0x0, BIT15|BIT14); ++ if(u8Val!=PAD_UNKNOWN) ++ printk("PWM pad set failed\n"); ++ ++ } ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMEnable error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++} ++ ++int DrvPWMGroupCap(void) ++{ ++ return (PWM_GROUP_NUM) ? 1 : 0; ++} ++ ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val) ++{ ++ if (PWM_NUM <= u8PWMId) ++ return 0; ++ if(u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ return 1; ++} ++ ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U32 u32JoinMask; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32JoinMask = 0xF << ((u8GroupId << 2) + REG_GROUP_JOIN_SHFT); ++ u32JoinMask = INREG16(ms_chip->base + REG_GROUP_JOIN) & u32JoinMask; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ return 1; ++} ++ ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val) ++{ ++ *pu8Val = 0; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ *pu8Val = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> (u8GroupId + REG_GROUP_ENABLE_SHFT)) & 0x1; ++ return 1; ++} ++ ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* pu16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ *pu16Val = INREG16(ms_chip->base + u32Reg) & 0xFFFF; ++ return 1; ++} ++ ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ OUTREG16(ms_chip->base + u32Reg, u16Val); ++ return 1; ++} ++ ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ ++ return 1; ++} ++ ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ ++ return 1; ++} ++ ++//+++[Only4I6e] ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip) ++{ ++#if 0 ++ return INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 0 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++ ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Duty; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++/* ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Duty = ((u32Period * u32Val) / 1000); ++ ++ if (u32Duty & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large duty 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Duty); ++ } ++/* ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++*/ ++ if (0 == u8DutyId) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (u8DutyId << 3) + 28, (u32Duty&0xFFFF)); ++ } ++ return 1; ++} ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Shft; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++/* ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Shft = ((u32Period * u32Val) / 1000); ++ ++ if (u32Shft & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large shift 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Shft); ++ } ++/* ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++*/ ++ if (0 == u8ShftId) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_L, (u32Shft&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_H, ((u32Shft>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (u8ShftId << 3) + 24, (u32Shft&0xFFFF)); ++ } ++ return 1; ++} ++ ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV); // workaround ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ u32Period /= (u32Div + 1); // workaround ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV, u8Val); ++ return 1; ++} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ // U32 tmp; ++ U32 u32Period, u32Polarity; // , u32MPluse; ++ // U32 u32Shft0, u32Shft1, u32Shft2, u32Shft3; ++ U32 u32Shft0; ++ // U32 u32Duty0, u32Duty1, u32Duty2, u32Duty3; ++ U32 u32Duty0; ++ U32 u32SyncStatus; ++ U32 u32ResetStatus; ++ U32 u32GroupEnable, u32GroupReset, u32GroupHold, u32GroupStop, u32GroupRound; ++ U32 clk = (U32)clk_get_rate(ms_chip->clk); ++ U32 u32Div; ++ ++ if (0 == DrvPWMGroupCap()) ++ { ++ str += scnprintf(str, end - str, "This chip does not support motor interface\n"); ++ return (str - buf_start); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_GROUP_NUM; i++) ++ { ++ U32 pwmIdx; ++ U32 j; ++ ++ // group enable ++ u32GroupEnable = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> i) & 0x1; ++ // group reset ++ u32GroupReset = (INREG16(ms_chip->base + u16REG_SW_RESET) >> (i + PWM_NUM)) & 0x1; ++ // hold ++ u32GroupHold = (INREG16(ms_chip->base + REG_GROUP_HOLD) >> (i + REG_GROUP_HOLD_SHFT)) & 0x1; ++ // stop ++ u32GroupStop = (INREG16(ms_chip->base + REG_GROUP_STOP) >> (i + REG_GROUP_STOP_SHFT)) & 0x1; ++ // round ++ u32GroupRound = INREG16(ms_chip->base + ((i << 0x7) + 0x40)) & 0xFFFF; ++ ++ str += scnprintf(str, end - str, "Group %d\n", i); ++ pwmIdx = (i << 2); ++ str += scnprintf(str, end - str, "\tmember\t\t"); ++ for (j = pwmIdx; j < pwmIdx + 4; j++) ++ { ++ if (j < PWM_NUM) ++ { ++ str += scnprintf(str, end - str, "%d ", j); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "\tenable status\t%d\n", u32GroupEnable); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32GroupReset); ++ str += scnprintf(str, end - str, "\tHold\t\t%d\n", u32GroupHold); ++ str += scnprintf(str, end - str, "\tStop\t\t%d\n", u32GroupStop); ++ str += scnprintf(str, end - str, "\tRound\t\t%d\n", u32GroupRound); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ // Polarity ++ u32Polarity = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> POLARITY_BIT) & 0x1; ++ // u32MPluse = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> DIFF_P_EN_BIT) & 0x1; ++ // Period ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_H))) ++ printk("[%s][%d] pwmId %d period_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Period = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_L); ++ // Shift ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_H))) ++ printk("[%s][%d] pwmId %d shift_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Shft0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_L); ++ // u32Shft1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT2); ++ // u32Shft2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT3); ++ // u32Shft3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT4); ++ // Duty ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_H))) ++ printk("[%s][%d] pwmId %d duty_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Duty0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_L); ++ // u32Duty1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY2); ++ // u32Duty2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY3); ++ // u32Duty3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY4); ++ // sync mode status ++ u32SyncStatus = (INREG16(ms_chip->base + REG_GROUP_JOIN) >> (i + REG_GROUP_JOIN_SHFT)) & 0x1; ++ // rest status ++ u32ResetStatus = (INREG16(ms_chip->base + u16REG_SW_RESET) >> i) & 0x1; ++ u32Div = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DIV); // workaround ++ ++ ++ // output to buffer ++ str += scnprintf(str, end - str, "Pwm %d\n", i); ++ str += scnprintf(str, end - str, "\tPad\t\t0x%08x\n", ms_chip->pad_ctrl[i]); ++ str += scnprintf(str, end - str, "\tSync status\t%d\n", u32SyncStatus); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32ResetStatus); ++ str += scnprintf(str, end - str, "\tPolarity\t%d\n", u32Polarity); ++#if 0 ++ str += scnprintf(str, end - str, "\tPeriod\t\t0x%08x\n", u32Period); ++ str += scnprintf(str, end - str, "\tBegin\t\t0x%08x\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t0x%08x\n", u32Duty0); ++#endif ++ u32Period++; ++ u32Shft0++; ++ u32Duty0++; ++ u32Shft0 = (1000 * u32Shft0)/u32Period; ++ u32Duty0 = (1000 * u32Duty0)/u32Period; ++ // u32Period = ((u32Div+1)*clk)/u32Period; ++ u32Period = clk/u32Period/(u32Div+1); ++ ++ str += scnprintf(str, end - str, "\tPeriod\t\t%d\n", u32Period); ++ // str += scnprintf(str, end - str, "\tBegin\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Shft0, u32Shft1, u32Shft2, u32Shft3); ++ // str += scnprintf(str, end - str, "\tEnd\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Duty0, u32Duty1, u32Duty2, u32Duty3); ++ str += scnprintf(str, end - str, "\tBegin\t\t%d\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t%d\n", u32Duty0); ++ } ++ // str += scnprintf(str, end - str, "This is a test\n"); ++ return (str - buf_start); ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++ //Only4i6e ++ return IRQ_NONE; ++} +diff --git a/drivers/sstar/pwm/infinity2/mhal_pwm.h b/drivers/sstar/pwm/infinity2/mhal_pwm.h +new file mode 100755 +index 000000000000..073315ec3221 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity2/mhal_pwm.h +@@ -0,0 +1,136 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 0 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (3) ++#define PWM_PER_GROUP (4) ++#define PWM_NUM (8) ++//Common PWM registers ++#define PWM_SHIFT_ARG_MAX_NUM (4) ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++#define REG_GROUP_HOLD (0x71 << 2) ++ #define REG_GROUP_HOLD_SHFT (0x0) ++ ++#define REG_GROUP_STOP (0x72 << 2) ++ #define REG_GROUP_STOP_SHFT (0x0) ++ ++#define REG_GROUP_ENABLE (0x73 << 2) ++ #define REG_GROUP_ENABLE_SHFT (0x0) ++ ++#define REG_GROUP_JOIN (0x74 << 2) ++ #define REG_GROUP_JOIN_SHFT (0x0) ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id); ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMEnableGet(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMGetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++void DrvPWMSetDben(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* pu16Val); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity2m/mhal_pwm.c b/drivers/sstar/pwm/infinity2m/mhal_pwm.c +new file mode 100755 +index 000000000000..f53e23d98fd7 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity2m/mhal_pwm.c +@@ -0,0 +1,831 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++#define BASE_REG_NULL 0xFFFFFFFF ++ ++typedef struct ++{ ++ u32 u32Adr; ++ u32 u32Val; ++ u32 u32Msk; ++} regSet_t; ++ ++typedef struct ++{ ++ u32 u32PadId; ++ regSet_t regSet[2]; ++} pwmPadTbl_t; ++ ++static pwmPadTbl_t padTbl_0[] = ++{ ++ { PAD_GPIO0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_TTL23, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_GPIO4, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_GPIO14, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_TTL0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_PM_LED0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 0), GENMASK(1, 0) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_1[] = ++{ ++ { PAD_GPIO1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_TTL12, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_TTL22, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_GPIO5, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_SATA_GPIO, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_PM_LED1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 2), GENMASK(3, 2) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_2[] = ++{ ++ { PAD_GPIO2, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_GPIO11, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_HDMITX_HPD, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_TTL21, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_FUART_TX, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_SD_D1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (6 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_PM_IRIN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 6), GENMASK(7, 6) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_3[] = ++{ ++ { PAD_GPIO3, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_GPIO7, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_GPIO12, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_TTL20, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_FUART_RX, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_PM_SD_CDZ, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 8), GENMASK(9, 8) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++}; ++ ++ ++static pwmPadTbl_t* padTbl[] = ++{ ++ padTbl_0, ++ padTbl_1, ++ padTbl_2, ++ padTbl_3, ++}; ++ ++static U8 _pwmEnSatus[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod[PWM_NUM] = { 0 }; ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ //Dummy func ++} ++//---[Only4I6e] ++ ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id) ++{ ++ U32 reset, u32Period; ++ ++ if (PWM_NUM <= u8Id) ++ return; ++ ++ reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++ ++ if (_pwmEnSatus[u8Id]) ++ { ++ U32 reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, 1<base + (u8Id*0x80) + u16REG_PWM_DUTY_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if (u32Duty) ++ { ++ U32 u32Period = _pwmPeriod[u8Id]; ++ // DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++ if (u32Period) ++ { ++ *pu32Val = (u32Duty * 100)/u32Period; ++ } ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period; ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Period; ++ ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if ((0 == _pwmPeriod[u8Id]) && (u32Period)) ++ { ++ _pwmPeriod[u8Id] = u32Period; ++ } ++ *pu32Val = 0; ++ if (u32Period) ++ { ++ *pu32Val = (U32)(clk_get_rate(ms_chip->clk))/(u32Period+1); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL) & (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_DUTY_L); ++ U32 u32DutyH = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H); ++ if (u32DutyL || u32DutyH) ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<regSet; ++// printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++// printk("[%s][%d] pad Id = %d\n", __FUNCTION__, __LINE__, pTbl->u32PadId); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++// if (PAD_UNKNOWN == pTbl->u32PadId) ++// { ++// break; ++// } ++// pTbl++; ++// } ++// } ++//} ++ ++void DrvPWMPadSet(U8 u8Id, U8 u8Val) ++{ ++ pwmPadTbl_t* pTbl = NULL; ++ if (PWM_NUM <= u8Id) ++ { ++ // printk(KERN_ERR "[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ return; ++ } ++ // printk("[%s][%d] (pwmId, padId) = (%d, %d)\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ pTbl = padTbl[u8Id]; ++ while (1) ++ { ++ if (u8Val == pTbl->u32PadId) ++ { ++ regSet_t* pRegSet = pTbl->regSet; ++ if (BASE_REG_NULL != pRegSet[0].u32Adr) ++ { ++ OUTREGMSK16(pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++ } ++ if (BASE_REG_NULL != pRegSet[1].u32Adr) ++ { ++ OUTREGMSK16(pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++ } ++ break; ++ } ++ if (PAD_UNKNOWN == pTbl->u32PadId) ++ { ++ printk(KERN_ERR "[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ break; ++ } ++ pTbl++; ++ } ++} ++ ++int DrvPWMGroupCap(void) ++{ ++ return (PWM_GROUP_NUM) ? 1 : 0; ++} ++ ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val) ++{ ++ if (PWM_NUM <= u8PWMId) ++ return 0; ++ if(u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ return 1; ++} ++ ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U32 u32JoinMask; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32JoinMask = 0xF << ((u8GroupId << 2) + REG_GROUP_JOIN_SHFT); ++ u32JoinMask = INREG16(ms_chip->base + REG_GROUP_JOIN) & u32JoinMask; ++ u32JoinMask |= 1 << (u8GroupId + 11); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ return 1; ++} ++ ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val) ++{ ++ *pu8Val = 0; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ *pu8Val = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> (u8GroupId + REG_GROUP_ENABLE_SHFT)) & 0x1; ++ return 1; ++} ++ ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ OUTREG16(ms_chip->base + u32Reg, u16Val); ++ return 1; ++} ++ ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ ++ return 1; ++} ++ ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ ++ return 1; ++} ++ ++//+++[Only4I6e] ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val) ++{ ++return 0; ++} ++ ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip) ++{ ++#if 0 ++ return INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 0 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++ ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Duty; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++/* ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Duty = ((u32Period * u32Val) / 1000); ++ ++ if (u32Duty & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large duty 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Duty); ++ } ++/* ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++*/ ++ if (0 == u8DutyId) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (u8DutyId << 3) + 28, (u32Duty&0xFFFF)); ++ } ++ return 1; ++} ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Shft; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++/* ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Shft = ((u32Period * u32Val) / 1000); ++ ++ if (u32Shft & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large shift 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Shft); ++ } ++/* ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++*/ ++ if (0 == u8ShftId) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_L, (u32Shft&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_H, ((u32Shft>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (u8ShftId << 3) + 24, (u32Shft&0xFFFF)); ++ } ++ return 1; ++} ++ ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV); // workaround ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ u32Period /= (u32Div + 1); // workaround ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV, u8Val); ++ return 1; ++} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ // U32 tmp; ++ U32 u32Period, u32Polarity; // , u32MPluse; ++ // U32 u32Shft0, u32Shft1, u32Shft2, u32Shft3; ++ U32 u32Shft0; ++ // U32 u32Duty0, u32Duty1, u32Duty2, u32Duty3; ++ U32 u32Duty0; ++ U32 u32SyncStatus; ++ U32 u32ResetStatus; ++ U32 u32GroupEnable, u32GroupReset, u32GroupHold, u32GroupStop, u32GroupRound; ++ U32 clk = (U32)clk_get_rate(ms_chip->clk); ++ U32 u32Div; ++ ++ if (0 == DrvPWMGroupCap()) ++ { ++ str += scnprintf(str, end - str, "This chip does not support motor interface\n"); ++ return (str - buf_start); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_GROUP_NUM; i++) ++ { ++ U32 pwmIdx; ++ U32 j; ++ ++ // group enable ++ u32GroupEnable = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> i) & 0x1; ++ // group reset ++ u32GroupReset = (INREG16(ms_chip->base + u16REG_SW_RESET) >> (i + 11)) & 0x1; ++ // hold ++ u32GroupHold = (INREG16(ms_chip->base + REG_GROUP_HOLD) >> (i + REG_GROUP_HOLD_SHFT)) & 0x1; ++ // stop ++ u32GroupStop = (INREG16(ms_chip->base + REG_GROUP_STOP) >> (i + REG_GROUP_STOP_SHFT)) & 0x1; ++ // round ++ u32GroupRound = INREG16(ms_chip->base + ((i << 0x7) + 0x40)) & 0xFFFF; ++ ++ str += scnprintf(str, end - str, "Group %d\n", i); ++ pwmIdx = (i << 2); ++ str += scnprintf(str, end - str, "\tmember\t\t"); ++ for (j = pwmIdx; j < pwmIdx + 4; j++) ++ { ++ if (j < PWM_NUM) ++ { ++ str += scnprintf(str, end - str, "%d ", j); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "\tenable status\t%d\n", u32GroupEnable); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32GroupReset); ++ str += scnprintf(str, end - str, "\tHold\t\t%d\n", u32GroupHold); ++ str += scnprintf(str, end - str, "\tStop\t\t%d\n", u32GroupStop); ++ str += scnprintf(str, end - str, "\tRound\t\t%d\n", u32GroupRound); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ // Polarity ++ u32Polarity = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> POLARITY_BIT) & 0x1; ++ // u32MPluse = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> DIFF_P_EN_BIT) & 0x1; ++ // Period ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_H))) ++ printk("[%s][%d] pwmId %d period_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Period = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_L); ++ // Shift ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_H))) ++ printk("[%s][%d] pwmId %d shift_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Shft0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_L); ++ // u32Shft1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT2); ++ // u32Shft2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT3); ++ // u32Shft3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT4); ++ // Duty ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_H))) ++ printk("[%s][%d] pwmId %d duty_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Duty0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_L); ++ // u32Duty1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY2); ++ // u32Duty2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY3); ++ // u32Duty3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY4); ++ // sync mode status ++ u32SyncStatus = (INREG16(ms_chip->base + REG_GROUP_JOIN) >> (i + REG_GROUP_JOIN_SHFT)) & 0x1; ++ // rest status ++ u32ResetStatus = (INREG16(ms_chip->base + u16REG_SW_RESET) >> i) & 0x1; ++ u32Div = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DIV); // workaround ++ ++ ++ // output to buffer ++ str += scnprintf(str, end - str, "Pwm %d\n", i); ++ str += scnprintf(str, end - str, "\tPad\t\t0x%08x\n", ms_chip->pad_ctrl[i]); ++ str += scnprintf(str, end - str, "\tSync status\t%d\n", u32SyncStatus); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32ResetStatus); ++ str += scnprintf(str, end - str, "\tPolarity\t%d\n", u32Polarity); ++#if 0 ++ str += scnprintf(str, end - str, "\tPeriod\t\t0x%08x\n", u32Period); ++ str += scnprintf(str, end - str, "\tBegin\t\t0x%08x\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t0x%08x\n", u32Duty0); ++#endif ++ u32Period++; ++ u32Shft0++; ++ u32Duty0++; ++ u32Shft0 = (1000 * u32Shft0)/u32Period; ++ u32Duty0 = (1000 * u32Duty0)/u32Period; ++ // u32Period = ((u32Div+1)*clk)/u32Period; ++ u32Period = clk/u32Period/(u32Div+1); ++ ++ str += scnprintf(str, end - str, "\tPeriod\t\t%d\n", u32Period); ++ // str += scnprintf(str, end - str, "\tBegin\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Shft0, u32Shft1, u32Shft2, u32Shft3); ++ // str += scnprintf(str, end - str, "\tEnd\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Duty0, u32Duty1, u32Duty2, u32Duty3); ++ str += scnprintf(str, end - str, "\tBegin\t\t%d\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t%d\n", u32Duty0); ++ } ++ // str += scnprintf(str, end - str, "This is a test\n"); ++ return (str - buf_start); ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++ //Only4i6e ++ return IRQ_NONE; ++} +\ No newline at end of file +diff --git a/drivers/sstar/pwm/infinity2m/mhal_pwm.h b/drivers/sstar/pwm/infinity2m/mhal_pwm.h +new file mode 100755 +index 000000000000..00ae242bae13 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity2m/mhal_pwm.h +@@ -0,0 +1,153 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 0 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (1) ++#define PWM_NUM (4) ++//Common PWM registers ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++#define REG_GROUP_HOLD (0x71 << 2) ++ #define REG_GROUP_HOLD_SHFT (0x0) ++ ++#define REG_GROUP_STOP (0x72 << 2) ++ #define REG_GROUP_STOP_SHFT (0x0) ++ ++#define REG_GROUP_ENABLE (0x73 << 2) ++ #define REG_GROUP_ENABLE_SHFT (0x0) ++ ++#define REG_GROUP_JOIN (0x74 << 2) ++ #define REG_GROUP_JOIN_SHFT (0x0) ++ ++//+++[Only4I6e] ++#define REG_GROUP_INT (0x75 << 2) ++ #define REG_GROUP_HOLD_INT_SHFT (0x0) ++ #define REG_GROUP_RUND_INT_SHFT (0x3) ++ ++#define REG_PWM_DUTY_QE0 (0x76 << 2) ++ #define REG_PWM_DUTY_QE0_SHFT (0x0) ++ ++#define REG_GROUP_HOLD_MODE1 (0x77 << 2) ++ #define REG_GROUP_HALD_MD1_SHFT (0x0) ++ ++#define REG_PWM_OUT (0x7E << 2) ++ #define REG_PWM_OUT_SHFT (0x0) ++//---[Only4I6e] ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id); ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMEnableGet(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMGetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++void DrvPWMSetDben(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++ ++//+++[Only4I6e] ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val); ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity3/mhal_pwm.c b/drivers/sstar/pwm/infinity3/mhal_pwm.c +new file mode 100755 +index 000000000000..bf95784cd2ce +--- /dev/null ++++ b/drivers/sstar/pwm/infinity3/mhal_pwm.c +@@ -0,0 +1,496 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ //Dummy func ++} ++//---[Only4I6e] ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDuty ++// ++// Description ++// Set Duty value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Duty value ++// ++// Return Value ++// None ++// ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ U32 u32Duty = 0x00000000; ++ ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Duty = ((u32Period * u32Val) / 100); ++ ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period; ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 0 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++ ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ return 0; ++} ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ return 0; ++} ++ ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ return 0; ++} ++ ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ return; ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ return 0; ++} ++#endif ++ ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++ //Only4i6e ++ return IRQ_NONE; ++} +\ No newline at end of file +diff --git a/drivers/sstar/pwm/infinity3/mhal_pwm.h b/drivers/sstar/pwm/infinity3/mhal_pwm.h +new file mode 100755 +index 000000000000..68ed19af9842 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity3/mhal_pwm.h +@@ -0,0 +1,135 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 1 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (0) ++ ++//Common PWM registers ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++//+++[Only4I6e] ++#define REG_GROUP_INT (0x75 << 2) ++ #define REG_GROUP_HOLD_INT_SHFT (0x0) ++ #define REG_GROUP_RUND_INT_SHFT (0x3) ++ ++#define REG_PWM_DUTY_QE0 (0x76 << 2) ++ #define REG_PWM_DUTY_QE0_SHFT (0x0) ++ ++#define REG_GROUP_HOLD_MODE1 (0x77 << 2) ++ #define REG_GROUP_HALD_MD1_SHFT (0x0) ++ ++#define REG_PWM_OUT (0x7E << 2) ++ #define REG_PWM_OUT_SHFT (0x0) ++//---[Only4I6e] ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++ ++//+++[Only4I6e] ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val); ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity5/mhal_pwm.c b/drivers/sstar/pwm/infinity5/mhal_pwm.c +new file mode 100755 +index 000000000000..0be224cf6d52 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity5/mhal_pwm.c +@@ -0,0 +1,601 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++static U8 _pwmEnSatus[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod[PWM_NUM] = { 0 }; ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ //Dummy func ++} ++//---[Only4I6e] ++ ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id) ++{ ++ U32 reset, u32Period; ++ ++ if (PWM_NUM <= u8Id) ++ return; ++ ++ reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, BIT0<> PMSLEEP_86MHz_POS; ++ ++ u32Period = _pwmPeriod[u8Id]; ++ u32Duty = ((u32Period * u32Val) / 100); ++ ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), u8ClK86MHz == PMSLEEP_86MHz_VAL ? CLOCK_SRC_86MHZ : (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++ ++ if (_pwmEnSatus[u8Id]) ++ { ++ U32 reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, 1<base + (u8Id*0x80) + u16REG_PWM_DUTY_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if (u32Duty) ++ { ++ U32 u32Period = _pwmPeriod[u8Id]; ++ // DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++ if (u32Period) ++ { ++ *pu32Val = (u32Duty * 100)/u32Period; ++ } ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ // Original clock source(12MHz) is unable to generate the frequency higher than 6MHz(12MHz/2). So use 86MHz as source. ++ if(u32Val > (U32)(clk_get_rate(ms_chip->clk)) / 2) { ++ u32Period = CLOCK_SRC_86MHZ / u32Val; ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + REG_ID_1C, (PMSLEEP_86MHz_VAL << PMSLEEP_86MHz_POS), (PMSLEEP_86MHz_VAL << PMSLEEP_86MHz_POS)); ++ CLRREG16( BASE_REG_CLKGEN_PA + REG_ID_6D, 0x1 << DIGPM_86MHz_POS); ++ } ++ else { ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ CLRREG16( BASE_REG_PMSLEEP_PA + REG_ID_1C, (PMSLEEP_86MHz_VAL << PMSLEEP_86MHz_POS)); ++ OUTREGMSK16( BASE_REG_CLKGEN_PA + REG_ID_6D, 0x1 << DIGPM_86MHz_POS, 0x1 << DIGPM_86MHz_POS); ++ } ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) { ++ u32Period = 2; ++ } ++ else if(u32Period > 262144) { ++ u32Period = 262144; ++ } ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), u32Val > (U32)(clk_get_rate(ms_chip->clk)) / 2 ? CLOCK_SRC_86MHZ :(U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Period; ++ ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if ((0 == _pwmPeriod[u8Id]) && (u32Period)) ++ { ++ _pwmPeriod[u8Id] = u32Period; ++ } ++ *pu32Val = 0; ++ if (u32Period) ++ { ++ *pu32Val = (U32)(clk_get_rate(ms_chip->clk))/(u32Period+1); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL) & (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_DUTY_L); ++ U32 u32DutyH = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H); ++ if (u32DutyL || u32DutyH) ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 0 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++ ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ return 0; ++} ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ return 0; ++} ++ ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ return 0; ++} ++ ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ return; ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ return 0; ++} ++#endif ++ ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++ //Only4i6e ++ return IRQ_NONE; ++} +\ No newline at end of file +diff --git a/drivers/sstar/pwm/infinity5/mhal_pwm.h b/drivers/sstar/pwm/infinity5/mhal_pwm.h +new file mode 100755 +index 000000000000..88bb8587462e +--- /dev/null ++++ b/drivers/sstar/pwm/infinity5/mhal_pwm.h +@@ -0,0 +1,147 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 0 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (0) ++#define PWM_NUM (8) ++//Common PWM registers ++#define PWM_SHIFT_ARG_MAX_NUM (4) ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++//+++[Only4I6e] ++#define REG_GROUP_INT (0x75 << 2) ++ #define REG_GROUP_HOLD_INT_SHFT (0x0) ++ #define REG_GROUP_RUND_INT_SHFT (0x3) ++ ++#define REG_PWM_DUTY_QE0 (0x76 << 2) ++ #define REG_PWM_DUTY_QE0_SHFT (0x0) ++ ++#define REG_GROUP_HOLD_MODE1 (0x77 << 2) ++ #define REG_GROUP_HALD_MD1_SHFT (0x0) ++ ++#define REG_PWM_OUT (0x7E << 2) ++ #define REG_PWM_OUT_SHFT (0x0) ++//---[Only4I6e] ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++// 86MHz related definitions ++#define CLOCK_SRC_86MHZ 86000000 ++#define PMSLEEP_86MHz_VAL 0x5 ++#define PMSLEEP_86MHz_POS 12 ++#define DIGPM_86MHz_POS 5 ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id); ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMEnableGet(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMGetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++void DrvPWMSetDben(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++ ++//+++[Only4I6e] ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val); ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity6/mhal_pwm.c b/drivers/sstar/pwm/infinity6/mhal_pwm.c +new file mode 100755 +index 000000000000..db4c85a2e473 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity6/mhal_pwm.c +@@ -0,0 +1,919 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++#define BASE_REG_NULL 0xFFFFFFFF ++ ++typedef struct ++{ ++ u32 u32Adr; ++ u32 u32Val; ++ u32 u32Msk; ++} regSet_t; ++ ++typedef struct ++{ ++ u32 u32PadId; ++ regSet_t regSet[2]; ++} pwmPadTbl_t; ++ ++static pwmPadTbl_t padTbl_0[] = ++{ ++ { PAD_PWM0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_GPIO14, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_FUART_RX, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_GPIO0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ //// { PAD_SD1_IO0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ // { PAD_PM_GPIO0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 0), GENMASK(1, 0) } } }, ++ { PAD_PM_GPIO0, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 0), GENMASK(1, 0) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_1[] = ++{ ++ { PAD_PWM1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_GPIO15, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_FUART_TX, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_GPIO1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ //// { PAD_SD1_IO1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ // { PAD_PM_GPIO1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 2), GENMASK(3, 2) } } }, ++ { PAD_PM_GPIO1, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 2), GENMASK(3, 2) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 3), GENMASK(5, 3)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_2[] = ++{ ++ { PAD_GPIO14, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_FUART_CTS, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ //// { PAD_SD1_IO0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_GPIO2, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ //// { PAD_SD1_IO2, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ // { PAD_PM_GPIO2, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 6), GENMASK(7, 6) } } }, ++ // { PAD_PM_GPIO9, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (2 << 6), GENMASK(7, 6) } } }, ++ { PAD_PM_GPIO2, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 6), GENMASK(7, 6) } } }, ++ { PAD_PM_GPIO9, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (2 << 6), GENMASK(7, 6) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 6), GENMASK(8, 6)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_3[] = ++{ ++ { PAD_GPIO15, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_FUART_RTS, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ //// { PAD_SD1_IO1, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_GPIO3, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ //// { PAD_SD1_IO3, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (5 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ // { PAD_PM_GPIO3, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 8), GENMASK(9, 8) } } }, ++ // { PAD_PM_GPIO7, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (2 << 8), GENMASK(9, 8) } } }, ++ { PAD_PM_GPIO3, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 8), GENMASK(9, 8) } } }, ++ { PAD_PM_GPIO7, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (2 << 8), GENMASK(9, 8) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_4[] = ++{ ++ //// { PAD_SD1_IO2, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (1 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ { PAD_SPI0_CZ, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (2 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ { PAD_GPIO4, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (3 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ //// { PAD_SD1_IO4, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (4 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ // { PAD_PM_LED0, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 0), GENMASK(0, 0) } } }, ++ { PAD_PM_LED0, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 0), GENMASK(0, 0) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_07, (0 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_5[] = ++{ ++ //// { PAD_SD1_IO3, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (1 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ { PAD_SPI0_CK, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (2 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ { PAD_GPIO5, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (3 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ //// { PAD_SD1_IO5, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (4 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ // { PAD_PM_LED1, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 1), GENMASK(1, 1) } } }, ++ { PAD_PM_LED1, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 1), GENMASK(1, 1) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_6[] = ++{ ++ //// { PAD_SD1_IO4, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (1 << 3), GENMASK(5, 3)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_SPI0_DI, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (2 << 3), GENMASK(5, 3)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_GPIO6, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (3 << 3), GENMASK(5, 3)}, { BASE_REG_NULL, 0, 0 } } }, ++ //// { PAD_SD1_IO6, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (4 << 3), GENMASK(5, 3)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 3), GENMASK(5, 3)}, { BASE_REG_NULL, 0, 0 } } }, ++}; ++ ++static pwmPadTbl_t padTbl_7[] = ++{ ++ //// { PAD_SD1_IO5, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (1 << 6), GENMASK(8, 6)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_SPI0_DO, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (2 << 6), GENMASK(8, 6)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_GPIO7, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (3 << 6), GENMASK(8, 6)}, { BASE_REG_NULL, 0, 0 } } }, ++ //// { PAD_SD1_IO7, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (4 << 6), GENMASK(8, 6)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 6), GENMASK(8, 6)}, { BASE_REG_NULL, 0, 0 } } }, ++}; ++ ++static pwmPadTbl_t padTbl_8[] = ++{ ++ { PAD_GPIO0, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (1 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_GPIO8, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (2 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ //// { PAD_SD1_IO8, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (3 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ //// { PAD_SR_IO14, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (4 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ // { PAD_PM_GPIO9, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 2), GENMASK(2, 2) } } }, ++ { PAD_PM_GPIO9, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 2), GENMASK(2, 2) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 9), GENMASK(11, 9)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_9[] = ++{ ++ { PAD_GPIO1, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (1 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_PWM0, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (2 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_GPIO14, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (3 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ //// { PAD_SR_IO15, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (4 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ // { PAD_PM_LED0, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 3), GENMASK(3, 3) } } }, ++ { PAD_PM_LED0, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 3), GENMASK(3, 3) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_02, (0 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_10[] = ++{ ++ //// { PAD_SD1_IO2, { { BASE_REG_CHIPTOP_PA + REG_ID_04, (1 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 4), GENMASK(4, 4) } } }, ++ { PAD_SPI0_CZ, { { BASE_REG_CHIPTOP_PA + REG_ID_04, (2 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 4), GENMASK(4, 4) } } }, ++ { PAD_GPIO4, { { BASE_REG_CHIPTOP_PA + REG_ID_04, (3 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 4), GENMASK(4, 4) } } }, ++ //// { PAD_SD1_IO4, { { BASE_REG_CHIPTOP_PA + REG_ID_04, (4 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 4), GENMASK(4, 4) } } }, ++ // { PAD_PM_LED0, { { BASE_REG_CHIPTOP_PA + REG_ID_04, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 4), GENMASK(4, 4) } } }, ++ { PAD_PM_LED1, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 4), GENMASK(4, 4) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_CHIPTOP_PA + REG_ID_04, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 4), GENMASK(4, 4) } } }, ++}; ++ ++static pwmPadTbl_t* padTbl[] = ++{ ++ padTbl_0, ++ padTbl_1, ++ padTbl_2, ++ padTbl_3, ++ padTbl_4, ++ padTbl_5, ++ padTbl_6, ++ padTbl_7, ++ padTbl_8, ++ padTbl_9, ++ padTbl_10, ++}; ++ ++static U8 _pwmEnSatus[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod[PWM_NUM] = { 0 }; ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ //Dummy func ++} ++//---[Only4I6e] ++ ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id) ++{ ++ U32 reset, u32Period; ++ ++ if (PWM_NUM <= u8Id) ++ return; ++ ++ reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++ ++ if (_pwmEnSatus[u8Id]) ++ { ++ U32 reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, 1<base + (u8Id*0x80) + u16REG_PWM_DUTY_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if (u32Duty) ++ { ++ U32 u32Period = _pwmPeriod[u8Id]; ++ // DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++ if (u32Period) ++ { ++ *pu32Val = (u32Duty * 100)/u32Period; ++ } ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) { ++ u32Period = 2; ++ } ++ else if(u32Period > 262144) { ++ u32Period = 262144; ++ } ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Period; ++ ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if ((0 == _pwmPeriod[u8Id]) && (u32Period)) ++ { ++ _pwmPeriod[u8Id] = u32Period; ++ } ++ *pu32Val = 0; ++ if (u32Period) ++ { ++ *pu32Val = (U32)(clk_get_rate(ms_chip->clk))/(u32Period+1); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL) & (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_DUTY_L); ++ U32 u32DutyH = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H); ++ if (u32DutyL || u32DutyH) ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<regSet; ++// printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++// printk("[%s][%d] pad Id = %d\n", __FUNCTION__, __LINE__, pTbl->u32PadId); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++// if (PAD_UNKNOWN == pTbl->u32PadId) ++// { ++// break; ++// } ++// pTbl++; ++// } ++// } ++//} ++ ++void DrvPWMPadSet(U8 u8Id, U8 u8Val) ++{ ++ pwmPadTbl_t* pTbl = NULL; ++ if (PWM_NUM <= u8Id) ++ { ++ // printk(KERN_ERR "[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ return; ++ } ++ // printk("[%s][%d] (pwmId, padId) = (%d, %d)\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ pTbl = padTbl[u8Id]; ++ while (1) ++ { ++ if (u8Val == pTbl->u32PadId) ++ { ++ regSet_t* pRegSet = pTbl->regSet; ++ if (BASE_REG_NULL != pRegSet[0].u32Adr) ++ { ++ OUTREGMSK16(pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++ } ++ if (BASE_REG_NULL != pRegSet[1].u32Adr) ++ { ++ OUTREGMSK16(pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++ } ++ break; ++ } ++ if (PAD_UNKNOWN == pTbl->u32PadId) ++ { ++ printk(KERN_ERR "[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ break; ++ } ++ pTbl++; ++ } ++} ++ ++int DrvPWMGroupCap(void) ++{ ++ return (PWM_GROUP_NUM) ? 1 : 0; ++} ++ ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val) ++{ ++ if (PWM_NUM <= u8PWMId) ++ return 0; ++ if(u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ return 1; ++} ++ ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U32 u32JoinMask; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32JoinMask = 0xF << ((u8GroupId << 2) + REG_GROUP_JOIN_SHFT); ++ u32JoinMask = INREG16(ms_chip->base + REG_GROUP_JOIN) & u32JoinMask; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ return 1; ++} ++ ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val) ++{ ++ *pu8Val = 0; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ *pu8Val = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> (u8GroupId + REG_GROUP_ENABLE_SHFT)) & 0x1; ++ return 1; ++} ++ ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ OUTREG16(ms_chip->base + u32Reg, u16Val); ++ return 1; ++} ++ ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ ++ return 1; ++} ++ ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ ++ return 1; ++} ++ ++//+++[Only4I6e] ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ *u16Val = INREG16(ms_chip->base + u32Reg) & 0xFFFF; ++ return 1; ++} ++ ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip) ++{ ++#if 0 ++ return INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 0 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++ ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Duty; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++/* ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Duty = ((u32Period * u32Val) / 1000); ++ ++ if (u32Duty & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large duty 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Duty); ++ } ++/* ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++*/ ++ if (0 == u8DutyId) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (u8DutyId << 3) + 28, (u32Duty&0xFFFF)); ++ } ++ return 1; ++} ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Shft; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++/* ++ if (0 == u32Val) ++ { ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Shft = ((u32Period * u32Val) / 1000); ++ ++ if (u32Shft & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large shift 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Shft); ++ } ++/* ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++*/ ++ if (0 == u8ShftId) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_L, (u32Shft&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_H, ((u32Shft>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (u8ShftId << 3) + 24, (u32Shft&0xFFFF)); ++ } ++ return 1; ++} ++ ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV); // workaround ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ u32Period /= (u32Div + 1); // workaround ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV, u8Val); ++ return 1; ++} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ // U32 tmp; ++ U32 u32Period, u32Polarity; // , u32MPluse; ++ // U32 u32Shft0, u32Shft1, u32Shft2, u32Shft3; ++ U32 u32Shft0; ++ // U32 u32Duty0, u32Duty1, u32Duty2, u32Duty3; ++ U32 u32Duty0; ++ U32 u32SyncStatus; ++ U32 u32ResetStatus; ++ U32 u32GroupEnable, u32GroupReset, u32GroupHold, u32GroupStop, u32GroupRound; ++ U32 clk = (U32)clk_get_rate(ms_chip->clk); ++ U32 u32Div; ++ ++ if (0 == DrvPWMGroupCap()) ++ { ++ str += scnprintf(str, end - str, "This chip does not support motor interface\n"); ++ return (str - buf_start); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_GROUP_NUM; i++) ++ { ++ U32 pwmIdx; ++ U32 j; ++ ++ // group enable ++ u32GroupEnable = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> i) & 0x1; ++ // group reset ++ u32GroupReset = (INREG16(ms_chip->base + u16REG_SW_RESET) >> (i + PWM_NUM)) & 0x1; ++ // hold ++ u32GroupHold = (INREG16(ms_chip->base + REG_GROUP_HOLD) >> (i + REG_GROUP_HOLD_SHFT)) & 0x1; ++ // stop ++ u32GroupStop = (INREG16(ms_chip->base + REG_GROUP_STOP) >> (i + REG_GROUP_STOP_SHFT)) & 0x1; ++ // round ++ u32GroupRound = INREG16(ms_chip->base + ((i << 0x7) + 0x40)) & 0xFFFF; ++ ++ str += scnprintf(str, end - str, "Group %d\n", i); ++ pwmIdx = (i << 2); ++ str += scnprintf(str, end - str, "\tmember\t\t"); ++ for (j = pwmIdx; j < pwmIdx + 4; j++) ++ { ++ if (j < PWM_NUM) ++ { ++ str += scnprintf(str, end - str, "%d ", j); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "\tenable status\t%d\n", u32GroupEnable); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32GroupReset); ++ str += scnprintf(str, end - str, "\tHold\t\t%d\n", u32GroupHold); ++ str += scnprintf(str, end - str, "\tStop\t\t%d\n", u32GroupStop); ++ str += scnprintf(str, end - str, "\tRound\t\t%d\n", u32GroupRound); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ // Polarity ++ u32Polarity = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> POLARITY_BIT) & 0x1; ++ // u32MPluse = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> DIFF_P_EN_BIT) & 0x1; ++ // Period ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_H))) ++ printk("[%s][%d] pwmId %d period_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Period = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_L); ++ // Shift ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_H))) ++ printk("[%s][%d] pwmId %d shift_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Shft0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_L); ++ // u32Shft1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT2); ++ // u32Shft2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT3); ++ // u32Shft3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT4); ++ // Duty ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_H))) ++ printk("[%s][%d] pwmId %d duty_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Duty0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_L); ++ // u32Duty1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY2); ++ // u32Duty2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY3); ++ // u32Duty3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY4); ++ // sync mode status ++ u32SyncStatus = (INREG16(ms_chip->base + REG_GROUP_JOIN) >> (i + REG_GROUP_JOIN_SHFT)) & 0x1; ++ // rest status ++ u32ResetStatus = (INREG16(ms_chip->base + u16REG_SW_RESET) >> i) & 0x1; ++ u32Div = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DIV); // workaround ++ ++ ++ // output to buffer ++ str += scnprintf(str, end - str, "Pwm %d\n", i); ++ str += scnprintf(str, end - str, "\tPad\t\t0x%08x\n", ms_chip->pad_ctrl[i]); ++ str += scnprintf(str, end - str, "\tSync status\t%d\n", u32SyncStatus); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32ResetStatus); ++ str += scnprintf(str, end - str, "\tPolarity\t%d\n", u32Polarity); ++#if 0 ++ str += scnprintf(str, end - str, "\tPeriod\t\t0x%08x\n", u32Period); ++ str += scnprintf(str, end - str, "\tBegin\t\t0x%08x\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t0x%08x\n", u32Duty0); ++#endif ++ u32Period++; ++ u32Shft0++; ++ u32Duty0++; ++ u32Shft0 = (1000 * u32Shft0)/u32Period; ++ u32Duty0 = (1000 * u32Duty0)/u32Period; ++ // u32Period = ((u32Div+1)*clk)/u32Period; ++ u32Period = clk/u32Period/(u32Div+1); ++ ++ str += scnprintf(str, end - str, "\tPeriod\t\t%d\n", u32Period); ++ // str += scnprintf(str, end - str, "\tBegin\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Shft0, u32Shft1, u32Shft2, u32Shft3); ++ // str += scnprintf(str, end - str, "\tEnd\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Duty0, u32Duty1, u32Duty2, u32Duty3); ++ str += scnprintf(str, end - str, "\tBegin\t\t%d\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t%d\n", u32Duty0); ++ } ++ // str += scnprintf(str, end - str, "This is a test\n"); ++ return (str - buf_start); ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++ //Only4i6e ++ return IRQ_NONE; ++} +diff --git a/drivers/sstar/pwm/infinity6/mhal_pwm.h b/drivers/sstar/pwm/infinity6/mhal_pwm.h +new file mode 100755 +index 000000000000..c7c1c9acc478 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity6/mhal_pwm.h +@@ -0,0 +1,155 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 0 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (3) ++#define PWM_PER_GROUP (4) ++#define PWM_NUM (11) ++//Common PWM registers ++#define PWM_SHIFT_ARG_MAX_NUM (4) ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++#define REG_GROUP_HOLD (0x71 << 2) ++ #define REG_GROUP_HOLD_SHFT (0x0) ++ ++#define REG_GROUP_STOP (0x72 << 2) ++ #define REG_GROUP_STOP_SHFT (0x0) ++ ++#define REG_GROUP_ENABLE (0x73 << 2) ++ #define REG_GROUP_ENABLE_SHFT (0x0) ++ ++#define REG_GROUP_JOIN (0x74 << 2) ++ #define REG_GROUP_JOIN_SHFT (0x0) ++ ++//+++[Only4I6e] ++#define REG_GROUP_INT (0x75 << 2) ++ #define REG_GROUP_HOLD_INT_SHFT (0x0) ++ #define REG_GROUP_RUND_INT_SHFT (0x3) ++ ++#define REG_PWM_DUTY_QE0 (0x76 << 2) ++ #define REG_PWM_DUTY_QE0_SHFT (0x0) ++ ++#define REG_GROUP_HOLD_MODE1 (0x77 << 2) ++ #define REG_GROUP_HALD_MD1_SHFT (0x0) ++ ++#define REG_PWM_OUT (0x7E << 2) ++ #define REG_PWM_OUT_SHFT (0x0) ++//---[Only4I6e] ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id); ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMEnableGet(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMGetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++void DrvPWMSetDben(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++ ++//+++[Only4I6e] ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val); ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity6b0/mhal_pwm.c b/drivers/sstar/pwm/infinity6b0/mhal_pwm.c +new file mode 100755 +index 000000000000..e7c5884d9eb7 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity6b0/mhal_pwm.c +@@ -0,0 +1,1666 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include "padmux.h" ++ ++extern S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++#define BASE_REG_NULL 0xFFFFFFFF ++ ++typedef struct ++{ ++ u32 u32Adr; ++ u32 u32Val; ++ u32 u32Msk; ++} regSet_t; ++ ++typedef struct ++{ ++ u32 u32PadId; ++ u32 u32Mode; ++} pwmPadTbl_t; ++ ++static pwmPadTbl_t padTbl_0[] = ++{ ++ { PAD_PWM0, PINMUX_FOR_PWM0_MODE_1}, ++ { PAD_GPIO14, PINMUX_FOR_PWM0_MODE_2}, ++ { PAD_FUART_RX, PINMUX_FOR_PWM0_MODE_3}, ++ { PAD_GPIO0, PINMUX_FOR_PWM0_MODE_4}, ++ { PAD_SD1_IO0, PINMUX_FOR_PWM0_MODE_5}, ++ { PAD_PM_GPIO0, PINMUX_FOR_PM_PWM0_MODE_1}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_1[] = ++{ ++ { PAD_PWM1, PINMUX_FOR_PWM1_MODE_1}, ++ { PAD_GPIO15, PINMUX_FOR_PWM1_MODE_2}, ++ { PAD_FUART_TX, PINMUX_FOR_PWM1_MODE_3}, ++ { PAD_GPIO1, PINMUX_FOR_PWM1_MODE_4}, ++ { PAD_SD1_IO1, PINMUX_FOR_PWM1_MODE_5}, ++ { PAD_PM_GPIO1, PINMUX_FOR_PM_PWM1_MODE_1}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_2[] = ++{ ++ { PAD_GPIO14, PINMUX_FOR_PWM2_MODE_1}, ++ { PAD_FUART_CTS, PINMUX_FOR_PWM2_MODE_2}, ++ { PAD_SD1_IO0, PINMUX_FOR_PWM2_MODE_3}, ++ { PAD_GPIO2, PINMUX_FOR_PWM2_MODE_4}, ++ { PAD_SD1_IO2, PINMUX_FOR_PWM2_MODE_5}, ++ { PAD_PM_GPIO2, PINMUX_FOR_PM_PWM2_MODE_1}, ++ { PAD_PM_GPIO9, PINMUX_FOR_PM_PWM2_MODE_2}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_3[] = ++{ ++ { PAD_GPIO15, PINMUX_FOR_PWM3_MODE_1}, ++ { PAD_FUART_RTS, PINMUX_FOR_PWM3_MODE_2}, ++ { PAD_SD1_IO1, PINMUX_FOR_PWM3_MODE_3}, ++ { PAD_GPIO3, PINMUX_FOR_PWM3_MODE_4}, ++ { PAD_SD1_IO3, PINMUX_FOR_PWM3_MODE_5}, ++ { PAD_PM_GPIO3, PINMUX_FOR_PM_PWM3_MODE_1}, ++ { PAD_PM_GPIO7, PINMUX_FOR_PM_PWM3_MODE_2}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_4[] = ++{ ++ { PAD_SD1_IO2, PINMUX_FOR_PWM4_MODE_1}, ++ { PAD_SPI0_CZ, PINMUX_FOR_PWM4_MODE_2}, ++ { PAD_GPIO4, PINMUX_FOR_PWM4_MODE_3}, ++ { PAD_SD1_IO4, PINMUX_FOR_PWM4_MODE_4}, ++ { PAD_PM_LED0, PINMUX_FOR_PM_PWM4_MODE}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_5[] = ++{ ++ { PAD_SD1_IO3, PINMUX_FOR_PWM5_MODE_1}, ++ { PAD_SPI0_CK, PINMUX_FOR_PWM5_MODE_2}, ++ { PAD_GPIO5, PINMUX_FOR_PWM5_MODE_3}, ++ { PAD_SD1_IO5, PINMUX_FOR_PWM5_MODE_4}, ++ { PAD_PM_LED1, PINMUX_FOR_PM_PWM5_MODE}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_6[] = ++{ ++ { PAD_SD1_IO4, PINMUX_FOR_PWM6_MODE_1}, ++ { PAD_SPI0_DI, PINMUX_FOR_PWM6_MODE_2}, ++ { PAD_GPIO6, PINMUX_FOR_PWM6_MODE_3}, ++ { PAD_SD1_IO6, PINMUX_FOR_PWM6_MODE_4}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_7[] = ++{ ++ { PAD_SD1_IO5, PINMUX_FOR_PWM7_MODE_1}, ++ { PAD_SPI0_DO, PINMUX_FOR_PWM7_MODE_2}, ++ { PAD_GPIO7, PINMUX_FOR_PWM7_MODE_3}, ++ { PAD_SD1_IO7, PINMUX_FOR_PWM7_MODE_4}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_8[] = ++{ ++ { PAD_GPIO0, PINMUX_FOR_PWM8_MODE_1}, ++ { PAD_GPIO8, PINMUX_FOR_PWM8_MODE_2}, ++ { PAD_SD1_IO8, PINMUX_FOR_PWM8_MODE_3}, ++ { PAD_SR_IO14, PINMUX_FOR_PWM8_MODE_4}, ++ { PAD_PM_GPIO9, PINMUX_FOR_PM_PWM2_MODE_2}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_9[] = ++{ ++ { PAD_GPIO1, PINMUX_FOR_PWM9_MODE_1}, ++ { PAD_PWM0, PINMUX_FOR_PWM9_MODE_2}, ++ { PAD_GPIO14, PINMUX_FOR_PWM9_MODE_3}, ++ { PAD_SR_IO15, PINMUX_FOR_PWM9_MODE_4}, ++ { PAD_PM_LED0, PINMUX_FOR_PM_PWM9_MODE}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t padTbl_10[] = ++{ ++ { PAD_GPIO3, PINMUX_FOR_PWM10_MODE_1}, ++ { PAD_PWM1, PINMUX_FOR_PWM10_MODE_2}, ++ { PAD_GPIO15, PINMUX_FOR_PWM10_MODE_3}, ++ { PAD_SR_IO16, PINMUX_FOR_PWM10_MODE_4}, ++ { PAD_PM_LED1, PINMUX_FOR_PM_PWM10_MODE}, ++ { PAD_UNKNOWN, BASE_REG_NULL}, ++}; ++ ++static pwmPadTbl_t* padTbl[] = ++{ ++ padTbl_0, ++ padTbl_1, ++ padTbl_2, ++ padTbl_3, ++ padTbl_4, ++ padTbl_5, ++ padTbl_6, ++ padTbl_7, ++ padTbl_8, ++ padTbl_9, ++ padTbl_10, ++}; ++static bool _pwmDutyeq0[PWM_NUM] = { 0 }; ++static U8 _pwmEnSatus[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod[PWM_NUM] = { 0 }; ++static U8 _pwmPolarity[PWM_NUM] = { 0 }; ++static U32 _pwmDuty[PWM_NUM][4] = {{0}}; //end ( hardware support 4 set of duty ) ++static U8 _pwmDutyId[PWM_NUM] = { 0 }; ++static U32 _pwmShft[PWM_NUM][4] = {{0}}; //begin ( hardware support 4 set of shift ) ++static U8 _pwmShftId[PWM_NUM] = { 0 }; ++static U32 _pwmFreq[PWM_NUM] = { 0 }; ++static U32 _pwmStopFreq[PWM_NUM] = { 0 }; ++ ++static bool isSync=1; // isSync=0 --> need to sync register data from mem ++#ifdef CONFIG_PWM_NEW ++static U32 _pwmDiv[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod_ns[PWM_NUM] = { 0 }; ++static U32 _pwmDuty_ns[PWM_NUM] = { 0 }; ++static U16 clk_pwm_div[7] = {1, 2, 4, 8, 32, 64, 128}; ++#endif ++//static bool isHolding = 0; ++//static bool isEmptyRnd=0; //for get round num ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++ ++//matt ++#define PWM_GROUP0_HOLD_INT (1<<0) ++#define PWM_GROUP1_HOLD_INT (1<<1) ++#define PWM_GROUP2_HOLD_INT (1<<2) ++#define PWM_GROUP0_ROUND_INT (1<<3) ++#define PWM_GROUP1_ROUND_INT (1<<4) ++#define PWM_GROUP2_ROUND_INT (1<<5) ++ ++int DrvPWMSetEndToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Duty[3][4]); ++int DrvPWMSetBeginToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Shft[3][4]); ++int DrvPWMSetPolarityExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Period); ++ ++unsigned long long timeStart[PWM_GROUP_NUM]={ 0 },timeStop,timeVal; ++static int totalRounds[PWM_NUM]={0}; ++#if 0 ++static int totalRounds_Stop[PWM_NUM]={0}; ++#endif ++static unsigned long long getCurNs(void) ++{ ++ return sched_clock(); ++} ++ ++ ++void showBit(void *dev) ++{ ++ struct mstar_pwm_chip *ms_chip = (struct mstar_pwm_chip*) dev; ++ U16 test; ++ test=INREG16(ms_chip->base +u16REG_PWM_INT )&0x3; ++ (test&(1<<1))?(MS_PWM_DBG(" [ round int=1 ]\n")):(MS_PWM_DBG(" [ round int=0 ]\n")); ++ (test&(1<<0))?(MS_PWM_DBG(" [ hold int=1 ]\n\n")):(MS_PWM_DBG(" [ hold int=0 ]\n\n")); ++} ++void MDEV_PWM_MemToReg(struct mstar_pwm_chip* ms_chip, U8 u8Id) ++{ ++ U8 u8GroupId=u8Id, pwmId; ++ int idx; ++ ++ for(idx=0;idx<4;idx++) ++ { ++ pwmId=(u8GroupId<<2)+idx; //idx+(groupid*4) ++ if(pwmIdbase + REG_GROUP_ENABLE, (1 << (group_round_id+ REG_GROUP_ENABLE_SHFT))); ++ u32Reg = (group_round_id << 0x7) + 0x40; // round bit ++ ++ for(i = 0; i < 4 ;i++){ ++ if(_pwmFreq[(group_round_id * PWM_PER_GROUP) + i]){ ++ ++ totalRounds[(group_round_id * PWM_PER_GROUP) + i] += INREG16(ms_chip->base + u32Reg) & 0xFFFF; ++ } ++ } ++ ++ OUTREG16(ms_chip->base + u32Reg, 0); // set round=0 ++ MS_PWM_DBG("\nNONE of ROUND ! \n"); ++ showBit(ms_chip); ++ } ++ else //have new data ++ { ++ MS_PWM_DBG("Create New Round !\n"); ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (group_round_id+ REG_GROUP_ENABLE_SHFT))); ++ MDEV_PWM_MemToReg(ms_chip, group_round_id); ++ /* ++ DrvPWMSetPolarityExToReg(ms_chip,group_round_id,_pwmPolarity[group_round_id]); ++ DrvPWMSetPeriodExToReg(ms_chip, group_round_id, _pwmPeriod[group_round_id]); ++ DrvPWMSetBeginToReg(ms_chip, group_round_id,_pwmShftId[group_round_id],_pwmShft); ++ DrvPWMSetEndToReg(ms_chip,group_round_id,_pwmDutyId[group_round_id],_pwmDuty); ++ */ ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (group_round_id + REG_GROUP_ENABLE_SHFT))); ++ isSync=1; ++ MS_PWM_DBG("You can set Parameter now !\n"); ++ timeStart[group_round_id]=getCurNs(); //new start round ms ++ } ++} ++ ++void MDev_PWM_isr_hold_Act(void *dev,U16 val,U16 u16Id) ++{ ++ U16 group_hold_id=u16Id; ++ U16 group_hold_mode=val; ++ struct mstar_pwm_chip *ms_chip = (struct mstar_pwm_chip*) dev; ++ ++ ++ if(group_hold_mode==0) ++ { ++ // (3.1) if mode 0 ++ // function, group_round_status --> return group_round_status[group_id]; ++ // I6b0 --> period/begin/end/polar --> arguement in memory to HW register ++ MDEV_PWM_MemToReg(ms_chip, group_hold_id); ++ MS_PWM_DBG("3.1 done\n"); ++ } ++ else if (group_hold_mode==1) ++ { ++ // (3.2) if mode 1, do nothing and return ++ MS_PWM_DBG("3.2 done\n"); ++ } ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *dev) ++{ ++ struct mstar_pwm_chip *ms_chip = (struct mstar_pwm_chip*) dev; ++ U16 group_id,group_hold_mode; ++ ++ // (1) read 0x75 --> reg_pwm_int, group_id = which group meet; both hold+round ++ group_id = INREG16(ms_chip->base + u16REG_PWM_INT)&0x3F; ++ // (2) read 0x77 --> hold mode 0 or 1, (?) each group should have its own mode, not share one mode (check with Ray and report to Oliver) ++ group_hold_mode = INREG16(ms_chip->base + u16REG_PWM_HOLD_MODE1) & BIT0; ++ ++ // 3 types of isr below. ++ /////////////////////////////////////////////////////// ++ // Part 1: use group_enable without sync. ++ /* ++ if(group_id&PWM_GROUP0_HOLD_INT && group_id&PWM_GROUP0_ROUND_INT) ++ { ++ if (!(INREG16(ms_chip->base + REG_GROUP_JOIN)&0xF)) ++ { ++ printk("Please sync first !"); ++ return IRQ_HANDLED; ++ } ++ } ++ if(group_id&PWM_GROUP1_HOLD_INT && group_id&PWM_GROUP1_ROUND_INT) ++ { ++ if (!(INREG16(ms_chip->base + REG_GROUP_JOIN)&0xF0)) ++ { ++ printk("Please sync first !"); ++ return IRQ_HANDLED; ++ } ++ } ++ if(group_id&PWM_GROUP2_HOLD_INT && group_id&PWM_GROUP2_ROUND_INT) ++ { ++ if (!(INREG16(ms_chip->base + REG_GROUP_JOIN)&0x700) ++ { ++ printk("Please sync first !"); ++ return IRQ_HANDLED; ++ } ++ } ++ */ ++ /////////////////////////////////////////////////////// ++ // Part 2 : Hold interrupt isr ++ ++ if(group_id&PWM_GROUP0_HOLD_INT) ++ { ++ // (3) ++ MDev_PWM_isr_hold_Act(ms_chip,group_hold_mode,0); ++ // (4) 0x71 --> hold release ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (0+ REG_GROUP_HOLD_SHFT))); ++ MS_PWM_DBG("Release hold mode done 1-0 !\n"); ++ showBit(ms_chip); ++ isSync=1; ++ } ++ if(group_id&PWM_GROUP1_HOLD_INT) ++ { ++ MDev_PWM_isr_hold_Act(ms_chip,group_hold_mode,1); ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (1+ REG_GROUP_HOLD_SHFT))); ++ MS_PWM_DBG("Release hold mode done 1-1 !\n"); ++ showBit(ms_chip); ++ isSync=1; ++ } ++ if(group_id&PWM_GROUP2_HOLD_INT) ++ { ++ MDev_PWM_isr_hold_Act(ms_chip,group_hold_mode,2); ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (2+ REG_GROUP_HOLD_SHFT))); ++ MS_PWM_DBG("Release hold mode done 1-2 !\n"); ++ showBit(ms_chip); ++ isSync=1; ++ } ++ ++ /////////////////////////////////////////////////////// ++ // Part 3 : Round interrupt isr ++ ++ if(group_id&PWM_GROUP0_ROUND_INT) ++ { ++ MS_PWM_DBG("2-0 done \n"); ++ MDev_PWM_isr_round_Act(ms_chip,0); ++ } ++ if(group_id&PWM_GROUP1_ROUND_INT) ++ { ++ MS_PWM_DBG("2-1 done \n"); ++ MDev_PWM_isr_round_Act(ms_chip,1); ++ } ++ if(group_id&PWM_GROUP2_ROUND_INT) ++ { ++ MS_PWM_DBG("2-2 done \n"); ++ MDev_PWM_isr_round_Act(ms_chip,2); ++ } ++ ++ return IRQ_HANDLED; ++ ++} ++ ++int DrvGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U16 u32JoinMask = 0X0000; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ //MDEV_PWM_SetSyncFlag(1); //dont need to sync until new data in ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ return 1; ++} ++ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++#if 0 //I6B0 no need ++ U8 i=0; ++ //MDEV_PWM_SetClock(); ++ for (i = 0; i < PWM_GROUP_NUM; i++) { ++ //Suggest driver owner default open each group_enable(h'73) and ++ //each group bit0 sync_mode for general mode. ++ DrvGroupEnable(ms_chip, i, 1); ++ //printk(KERN_NOTICE "[NOTICE]Each grp enable must be enabled!\r\n"); ++ } ++#endif ++} ++//---[Only4I6e] ++ ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id) ++{ ++ U32 reset, u32Period; ++ ++ if (PWM_NUM <= u8Id) ++ return; ++ reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<= PWM_NUM) ++ return; ++ _pwmDutyeq0[u8Id] = (duty==0)?TRUE:FALSE; ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ ++ /* select div */ ++ for(i = 0;i<(sizeof(clk_pwm_div)/sizeof(U16));i++){ ++ periodmax = (clk_pwm_div[i] * 262144 / pwmclk) * common; ++ if(period < periodmax) ++ { ++ u16Div = clk_pwm_div[i]; ++ _pwmDiv[u8Id] = clk_pwm_div[i]; ++ break; ++ } ++ } ++ ++ /* select period */ ++ if(period < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Period= (pwmclk * period) / (u16Div * common); ++ if(((pwmclk * period) % (u16Div * common)) > (u16Div * common / 2)) ++ { ++ u32Period++; ++ } ++ _pwmPeriod_ns[u8Id] = (u32Period * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Period= (period / u16Div) * pwmclk / common; ++ u32Period++; ++ _pwmPeriod_ns[u8Id] = (u32Period * common / pwmclk) * u16Div; ++ } ++ ++ /* select duty */ ++ if(duty == 0) ++ { ++ if(_pwmEnSatus[u8Id]) ++ { ++ SETREG16(ms_chip->base + u16REG_SW_RESET,BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ } ++ else ++ { ++ if(_pwmEnSatus[u8Id]) ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ } ++ ++ if(duty < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Duty= (pwmclk * duty) / (u16Div * common); ++ if((((pwmclk * duty) % (u16Div * common)) > (u16Div * common / 2)) || (u32Duty == 0)) ++ { ++ u32Duty++; ++ } ++ _pwmDuty_ns[u8Id] = (u32Duty * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Duty= (duty / u16Div) * pwmclk / common; ++ u32Duty++; ++ _pwmPeriod_ns[u8Id] = (u32Duty * common / pwmclk) * u16Div; ++ } ++ ++ /* set div period duty */ ++ u16Div--; ++ u32Period--; ++ u32Duty--; ++ pr_err("clk=%d, u16Div=%d u32Duty=0x%x u32Period=0x%x\n", (U32)(clk_get_rate(ms_chip->clk)), u16Div, u32Duty, u32Period); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DIV, (u16Div & 0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++} ++ ++void DrvPWMGetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* Duty,U32* Period) ++{ ++ U16 u16Div = 0; ++ U32 u32Duty = 0; ++ U32 u32Period = 0; ++ U32 pwmclk = 0; ++ U32 common = 0; ++ ++ if(u8Id >= PWM_NUM) ++ return; ++ ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ ++ u16Div = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DIV); ++ u16Div++; ++ ++ if(Period != NULL) ++ { ++ if(_pwmPeriod_ns[u8Id] == 0) ++ { ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if(u32Period) ++ { ++ u32Period++; ++ } ++ _pwmPeriod_ns[u8Id] = (u32Period * u16Div * common) / pwmclk; ++ } ++ *Period = _pwmPeriod_ns[u8Id]; ++ } ++ ++ if(Duty != NULL) ++ { ++ if(_pwmDuty_ns[u8Id] == 0) ++ { ++ u32Duty = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if(u32Duty) ++ { ++ u32Duty++; ++ } ++ _pwmDuty_ns[u8Id] = (u32Duty * u16Div * common) / pwmclk; ++ } ++ *Duty = _pwmDuty_ns[u8Id]; ++ } ++ ++} ++ ++#else ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ U32 u32Duty = 0x00000000; ++ ++ if (PWM_NUM <= u8Id){ ++ return; ++ } ++ ++ _pwmDutyeq0[u8Id] = (u32Val==0)?TRUE:FALSE; ++ if (_pwmEnSatus[u8Id]) ++ { ++ if (_pwmDutyeq0[u8Id]) ++ OUTREGMSK16(ms_chip->base + u16REG_SW_RESET, BIT0<base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++ ++ if (_pwmEnSatus[u8Id]) ++ { ++ U32 reset = INREG16(ms_chip->base + u16REG_SW_RESET) & (BIT0<base + u16REG_SW_RESET, 1<base + (u8Id*0x80) + u16REG_PWM_DUTY_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if (u32Duty) ++ { ++ U32 u32Period = _pwmPeriod[u8Id]; ++ // DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++ if (u32Period) ++ { ++ *pu32Val = (u32Duty * 100)/u32Period; ++ } ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ U16 u16Div = 0; ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ ++ //[APN] range 2<=Period<=262144 ++ ++ if(u32Period > 262144){ ++ u16Div = u32Period/262144; ++ u16Div--; ++ u32Period = 262144; ++ } ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DIV, (u16Div & 0xFFFF)); ++ ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Period; ++ U16 u16Div; ++ ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) | ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if ((0 == _pwmPeriod[u8Id]) && (u32Period)) ++ { ++ _pwmPeriod[u8Id] = u32Period; ++ } ++ u16Div = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DIV) + 1; ++ ++ *pu32Val = 0; ++ if (u32Period) ++ { ++ *pu32Val = (U32)(clk_get_rate(ms_chip->clk))/(u32Period+1) * u16Div; ++ } ++} ++#endif ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL) & (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1<regSet; ++ printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++ printk("[%s][%d] pad Id = %d\n", __FUNCTION__, __LINE__, pTbl->u32PadId); ++ printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++ printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++ if (PAD_UNKNOWN == pTbl->u32PadId) ++ { ++ break; ++ } ++ pTbl++; ++ } ++ } ++} ++*/ ++ ++void DrvPWMPadSet(U8 u8Id, U8 u8Val) ++{ ++ pwmPadTbl_t* pTbl = NULL; ++// U16 u16Temp; ++ ++ if (PWM_NUM < u8Id) ++ { ++ return; ++ } ++ ++ printk("[%s][%d] (pwmId, padId) = (%d, %d)\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ ++ pTbl = padTbl[u8Id]; ++ while (1) ++ { ++ if (u8Val == pTbl->u32PadId) ++ { ++ if (BASE_REG_NULL != pTbl->u32Mode) ++ { ++ HalPadSetVal(u8Val, pTbl->u32Mode); ++ } ++ break; ++ } ++ if (PAD_UNKNOWN == pTbl->u32PadId) ++ { ++ printk("[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ break; ++ } ++ pTbl++; ++ } ++} ++ ++int DrvPWMGroupCap(void) ++{ ++ return (PWM_GROUP_NUM) ? 1 : 0; ++} ++ ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val) ++{ ++ if (PWM_NUM <= u8PWMId) ++ return 0; ++ if(u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ return 1; ++} ++ ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U32 u32JoinMask; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if(!isSync) ++ { ++ MDEV_PWM_MemToReg(ms_chip, u8GroupId); ++ MS_PWM_DBG("MEM to REG done !\n"); ++ } ++ ++ u32JoinMask = 0xF << ((u8GroupId << 2) + REG_GROUP_JOIN_SHFT); ++ u32JoinMask = INREG16(ms_chip->base + REG_GROUP_JOIN) & u32JoinMask; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ isSync=1; //dont need to sync until new data in ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); //ori ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ ++ } ++ ++ timeStart[u8GroupId]=getCurNs(); // start round ns ++ ++ return 1; ++} ++ ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val) ++{ ++ *pu8Val = 0; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ *pu8Val = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> (u8GroupId + REG_GROUP_ENABLE_SHFT)) & 0x1; ++ return 1; ++} ++ ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8PwmId, U16* u16Val) ++{ ++ U32 u32GroupRound = 0; ++ U8 enable_status = 0; ++ timeStop=getCurNs(); //ns ++ ++ if (PWM_NUM <= u8PwmId) ++ return 0; ++ ++ timeVal=(timeStop-timeStart[u8PwmId/4])*_pwmFreq[u8PwmId]; ++ timeVal/=1000000000; ++ ++ //do_div(timeVal,1000000000); ++ u32GroupRound = INREG16(ms_chip->base + (((u8PwmId>>2) << 0x7) + 0x40)) & 0xFFFF; ++ timeVal = (timeVal > u32GroupRound)? u32GroupRound: timeVal; ++ ++ if (!DrvPWMGroupIsEnable(ms_chip, u8PwmId/4, &enable_status)) ++ { ++ printk("[%s][%d] unable to get enable status of group %d\n", __FUNCTION__, __LINE__, u8PwmId/4); ++ } ++ ++ if((u32GroupRound)&&(enable_status)){ ++ timeVal+=totalRounds[u8PwmId]; ++ } ++ else{ ++// printk("Please set round!"); ++ timeVal=totalRounds[u8PwmId]; ++ } ++ *u16Val = timeVal; ++ printk("round take %lld times \n",timeVal); ++ ++ return 1; ++} ++ ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; //(GroupId * 0x20<<2) + 0x10<<2 ++ OUTREG16(ms_chip->base + u32Reg, u16Val); ++ ++ //isEmptyRnd=0; ++ //timeStart[u8GroupId]=getCurNs(); //new start round ns ++ return 1; ++} ++#if 0 ++int DrvPWMGroupShowStopRound(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ str += scnprintf(str, end - str, "PWM%d\t Round = \t%d\n", i, totalRounds_Stop[i]); ++ } ++ return (str - buf_start); ++} ++ ++void DrvPWMGroupGetStopRound(U8 u8PwmId) ++{ ++ printk("totalRounds_stop: %d", totalRounds_Stop[u8PwmId]); ++} ++#endif ++ ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ int idx; ++ U32 u32JoinMask; ++ #if 0 ++ U16 round_set; ++ #endif ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ u32JoinMask = 0xF << ((u8GroupId << 2) + REG_GROUP_JOIN_SHFT); ++ u32JoinMask = INREG16(ms_chip->base + REG_GROUP_JOIN) & u32JoinMask; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ ++ for (idx = (u8GroupId * PWM_PER_GROUP); idx < ((u8GroupId+1) * PWM_PER_GROUP); idx++) ++ { ++ if ((u8Val) && (idx < PWM_NUM)) ++ { ++ //Keep round ++ #if 0 ++ DrvPWMGroupGetRoundNum(ms_chip, idx, &round_set); ++ totalRounds_Stop[idx]=round_set; ++ #endif ++ ++ totalRounds[idx] = 0; ++// _pwmStopFreq[idx]= _pwmFreq[idx]; ++ _pwmFreq[idx] = 0; ++ } ++ else{ ++ timeStart[u8GroupId]=getCurNs(); ++ _pwmFreq[idx]= _pwmStopFreq[idx];// recover freq ++ } ++ } ++ return 1; ++} ++ ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ ++ return 1; ++} ++//+++[Only4I6e] ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip) ++{ ++#if 0 ++ return INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 0 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++#if 1 ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ printk("[%s L%d] grp:%d x%x(%d)\n", __FUNCTION__, __LINE__, u8GroupId, u8Val, u8Val); ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << (u8GroupId + REG_PWM_DUTY_QE0_SHFT))); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e id:%d\n", __FUNCTION__, __LINE__, u8GroupId); ++#endif ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 0 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++#ifdef CONFIG_PWM_NEW ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U16 u16Div = 0; ++ U32 common = 0; ++ U32 pwmclk = 0; ++ U32 u32Duty = 0x00000000; ++ ++ pwmclk = 3; ++ common = 250; ++ u16Div = (_pwmDiv[u8Id] + 1); ++ ++ /* select duty */ ++ if(u32Val == 0) ++ { ++ SETREG16(ms_chip->base + u16REG_SW_RESET,BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ ++ if(u32Val < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Duty= (pwmclk * u32Val) / (u16Div * common); ++ ++ if((((pwmclk * u32Val) % (u16Div * common)) > (u16Div * common / 2)) || (u32Duty == 0)) ++ { ++ u32Duty++; ++ } ++ _pwmDuty_ns[u8Id] = (u32Duty * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Duty= (u32Val / u16Div) * pwmclk / common; ++ u32Duty++; ++ _pwmDuty_ns[u8Id] = (u32Duty * common / pwmclk) * u16Div; ++ } ++ ++ u32Duty--; ++ //matt ++ _pwmDutyId[u8Id]=u8DutyId; ++ _pwmDuty[u8Id][u8DutyId]=u32Duty; ++ ++ isSync=0; ++ return 1; ++} ++#else ++//---[Only4I6e] ++// I6b0 --> end --> arguement in memory ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Duty; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ ++ // u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Duty = ((u32Period * u32Val) / 1000); ++ //matt ++ _pwmDutyId[u8Id]=u8DutyId; ++ _pwmDuty[u8Id][u8DutyId]=u32Duty; ++ isSync=0; ++ ++ if (u32Duty & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large duty 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Duty); ++ } ++ return 1; ++} ++#endif ++ ++int DrvPWMSetEndToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Duty[3][4]) ++{ ++ int id; ++ for(id=0; id<=u8DutyId;id++){ ++ if (0 == id) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty[u8Id][id]&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty[u8Id][id]>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (id << 3) + 28, (u32Duty[u8Id][id]&0xFFFF)); ++ } ++ return 1; ++ } ++return 1; ++} ++ ++#ifdef CONFIG_PWM_NEW ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U16 u16Div = 0; ++ U32 common = 0; ++ U32 pwmclk = 0; ++ U32 u32Shift = 0x00000000; ++ ++ pwmclk = 3; ++ common = 250; ++ u16Div = (_pwmDiv[u8Id] + 1); ++ ++ /* select duty */ ++ if(u32Val == 0) ++ { ++ SETREG16(ms_chip->base + u16REG_SW_RESET,BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ ++ if(u32Val < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Shift= (pwmclk * u32Val) / (u16Div * common); ++ ++ if((((pwmclk * u32Val) % (u16Div * common)) > (u16Div * common / 2)) || (u32Shift == 0)) ++ { ++ u32Shift++; ++ } ++ } ++ else ++ { ++ u32Shift= (u32Val / u16Div) * pwmclk / common; ++ u32Shift++; ++ } ++ ++ u32Shift--; ++ //matt ++ _pwmShftId[u8Id]=u8ShftId; ++ _pwmShft[u8Id][u8ShftId]=u32Shift; ++ ++ isSync=0; ++ return 1; ++ ++} ++#else ++// I6b0 --> begin --> arguement in memory ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Shft; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ ++ u32Period = _pwmPeriod[u8Id]; ++ u32Shft = ((u32Period * u32Val) / 1000); ++//matt ++ _pwmShftId[u8Id]=u8ShftId; ++ _pwmShft[u8Id][u8ShftId]=u32Shft; ++ isSync=0; ++ ++ if (u32Shft & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large shift 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Shft); ++ } ++ ++ return 1; ++} ++#endif ++ ++int DrvPWMSetBeginToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Shft[3][4]) ++{ ++ int id; ++ for(id=0; id<=u8ShftId;id++){ ++ if (0 == id) ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_L, (u32Shft[u8Id][id]&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_SHIFT_H, ((u32Shft[u8Id][id]>> 16)&0x0003)); ++ } ++ else ++ { ++ OUTREG16(ms_chip->base + (u8Id*0x80) + (id << 3) + 24, (u32Shft[u8Id][id]&0xFFFF)); ++ } ++ return 1; ++ } ++ return 1; ++} ++ ++// I6b0 --> polarity --> arguement in memory ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM<= u8Id) ++ return 0; ++ //matt ++ _pwmPolarity[u8Id]=u8Val; ++ isSync=0; ++ ++ return 1; ++} ++ ++int DrvPWMSetPolarityExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<= PWM_NUM) ++ return; ++ ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ ++ /* select div */ ++ for(i = 0;i<(sizeof(clk_pwm_div)/sizeof(U16));i++){ ++ periodmax = (clk_pwm_div[i] * 262144 / pwmclk) * common; ++ if(period < periodmax) ++ { ++ u16Div = clk_pwm_div[i]; ++ break; ++ } ++ } ++ ++ /* select period */ ++ if(period < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Period= (pwmclk * period) / (u16Div * common); ++ if(((pwmclk * period) % (u16Div * common)) > (u16Div * common / 2)) ++ { ++ u32Period++; ++ } ++ _pwmPeriod_ns[u8Id] = (u32Period * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Period= (period / u16Div) * pwmclk / common; ++ u32Period++; ++ _pwmPeriod_ns[u8Id] = (u32Period * common / pwmclk) * u16Div; ++ } ++ u16Div--; ++ u32Period--; ++ ++ //matt ++ _pwmDiv[u8Id] = u16Div; ++ _pwmPeriod[u8Id] = u32Period; ++ _pwmFreq[u8Id]=1000000000/period; ++ _pwmStopFreq[u8Id]=1000000000/period; ++ isSync=0; ++ ++ printk("Period 0x%x ", _pwmPeriod[u8Id]); ++ printk("Freq %d Hz", _pwmFreq[u8Id]); ++ printk("Div 0x%x \r\n", _pwmDiv[u8Id]); ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++} ++ ++#else ++// I6b0 --> period --> arguement in memory ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Div; ++ ++ u32Div = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DIV); // workaround ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ u32Period /= (u32Div + 1); // workaround ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ //matt ++ _pwmPeriod[u8Id] = u32Period; ++ //_pwmFreq[u8Id] = (U32)(clk_get_rate(ms_chip->clk))/(_pwmPeriod[u8Id] * (u32Div+1));//for round number ++ _pwmFreq[u8Id]=u32Val; ++ _pwmStopFreq[u8Id]=u32Val; ++ isSync=0; ++ ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++} ++#endif ++ ++void DrvPWMSetPeriodExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Period) ++{ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_DIV, u8Val); ++ MS_PWM_DBG("mhal DrvPWMDiv done !\n"); ++ return 1; ++} ++/*Get pwm's round number*/ ++//int DrvPWMGetRoundNum(int pwmID) ++//{ ++// int i; ++// U32 u32GroupRound; ++// int PerRound=0; ++ ++// timeStop=getCurNs(); //ns ++// ++// for (i = 0; i < PWM_NUM; i++) ++// { ++// u32GroupRound = INREG16(ms_chip->base + (((pwmID/4) << 0x7) + 0x40)) & 0xFFFF; ++// PerRound = (timeStop-timeStart[pwmID/4])*_pwmFreq[pwmID]; ++// PerRound /= 1000000000; ++// PerRound = (PerRound > u32GroupRound) ? u32GroupRound : PerRound; ++// } ++// return PerRound; ++//} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ U32 u32GroupRound; ++ U8 enable_status=0; ++ ++ timeStop=getCurNs(); //ns ++ ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ u32GroupRound = INREG16(ms_chip->base + (((i>>2) << 0x7) + 0x40)) & 0xFFFF; ++ timeVal = (timeStop-timeStart[i/4])*_pwmFreq[i]; ++ timeVal /= 1000000000; ++ timeVal = (timeVal > u32GroupRound) ? u32GroupRound : timeVal; ++ DrvPWMGroupIsEnable(ms_chip, i/4, &enable_status); ++ ++ if(enable_status) ++ timeVal+=totalRounds[i]; ++ else ++ timeVal = totalRounds[i]; ++ str += scnprintf(str, end - str, "PWM%d\t Round = \t%lld\n", i, timeVal); ++ } ++ ++ return (str - buf_start); ++} ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ // U32 tmp; ++ U32 u32Period, u32Polarity; // , u32MPluse; ++ // U32 u32Shft0, u32Shft1, u32Shft2, u32Shft3; ++ U32 u32Shft0; ++ // U32 u32Duty0, u32Duty1, u32Duty2, u32Duty3; ++ U32 u32Duty0; ++ U32 u32SyncStatus; ++ U32 u32ResetStatus; ++ U32 u32GroupEnable, u32GroupReset, u32GroupHold, u32GroupStop, u32GroupRound; ++ U32 clk = (U32)clk_get_rate(ms_chip->clk); ++ U32 u32Div; ++ ++ if (0 == DrvPWMGroupCap()) ++ { ++ str += scnprintf(str, end - str, "This chip does not support motor interface\n"); ++ return (str - buf_start); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_GROUP_NUM; i++) ++ { ++ U32 pwmIdx; ++ U32 j; ++ ++ // group enable ++ u32GroupEnable = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> i) & 0x1; ++ // group reset ++ u32GroupReset = (INREG16(ms_chip->base + u16REG_SW_RESET) >> (i + PWM_NUM)) & 0x1; ++ // hold ++ u32GroupHold = (INREG16(ms_chip->base + REG_GROUP_HOLD) >> (i + REG_GROUP_HOLD_SHFT)) & 0x1; ++ // stop ++ u32GroupStop = (INREG16(ms_chip->base + REG_GROUP_STOP) >> (i + REG_GROUP_STOP_SHFT)) & 0x1; ++ // round ++ u32GroupRound = INREG16(ms_chip->base + ((i << 0x7) + 0x40)) & 0xFFFF; ++ ++ str += scnprintf(str, end - str, "Group %d\n", i); ++ pwmIdx = (i << 2); ++ str += scnprintf(str, end - str, "\tmember\t\t"); ++ for (j = pwmIdx; j < pwmIdx + 4; j++) ++ { ++ if (j < PWM_NUM) ++ { ++ str += scnprintf(str, end - str, "%d ", j); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "\tenable status\t%d\n", u32GroupEnable); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32GroupReset); ++ str += scnprintf(str, end - str, "\tHold\t\t%d\n", u32GroupHold); ++ str += scnprintf(str, end - str, "\tStop\t\t%d\n", u32GroupStop); ++ str += scnprintf(str, end - str, "\tRound\t\t%d\n", u32GroupRound); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ // Polarity ++ u32Polarity = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> POLARITY_BIT) & 0x1; ++ // u32MPluse = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> DIFF_P_EN_BIT) & 0x1; ++ // Period ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_H))) ++ printk("[%s][%d] pwmId %d period_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Period = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_L); ++ // Shift ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_H))) ++ printk("[%s][%d] pwmId %d shift_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Shft0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_L); ++ // u32Shft1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT2); ++ // u32Shft2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT3); ++ // u32Shft3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT4); ++ // Duty ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_H))) ++ printk("[%s][%d] pwmId %d duty_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Duty0 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_L); ++ // u32Duty1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY2); ++ // u32Duty2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY3); ++ // u32Duty3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY4); ++ // sync mode status ++ u32SyncStatus = (INREG16(ms_chip->base + REG_GROUP_JOIN) >> (i + REG_GROUP_JOIN_SHFT)) & 0x1; ++ // rest status ++ u32ResetStatus = (INREG16(ms_chip->base + u16REG_SW_RESET) >> i) & 0x1; ++ u32Div = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DIV); // workaround ++ ++ ++ // output to buffer ++ str += scnprintf(str, end - str, "Pwm %d\n", i); ++ str += scnprintf(str, end - str, "\tPad\t\t0x%08x\n", ms_chip->pad_ctrl[i]); ++ str += scnprintf(str, end - str, "\tSync status\t%d\n", u32SyncStatus); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32ResetStatus); ++ str += scnprintf(str, end - str, "\tPolarity\t%d\n", u32Polarity); ++#if 0 ++ str += scnprintf(str, end - str, "\tPeriod\t\t0x%08x\n", u32Period); ++ str += scnprintf(str, end - str, "\tBegin\t\t0x%08x\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t0x%08x\n", u32Duty0); ++#endif ++ u32Period++; ++ u32Shft0++; ++ u32Duty0++; ++ u32Shft0 = (1000 * u32Shft0)/u32Period; ++ u32Duty0 = (1000 * u32Duty0)/u32Period; ++ // u32Period = ((u32Div+1)*clk)/u32Period; ++ u32Period = clk/u32Period/(u32Div+1); ++ ++ str += scnprintf(str, end - str, "\tPeriod\t\t%d\n", u32Period); ++ // str += scnprintf(str, end - str, "\tBegin\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Shft0, u32Shft1, u32Shft2, u32Shft3); ++ // str += scnprintf(str, end - str, "\tEnd\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Duty0, u32Duty1, u32Duty2, u32Duty3); ++ str += scnprintf(str, end - str, "\tBegin\t\t%d\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t%d\n", u32Duty0); ++ } ++ // str += scnprintf(str, end - str, "This is a test\n"); ++ return (str - buf_start); ++} +diff --git a/drivers/sstar/pwm/infinity6b0/mhal_pwm.h b/drivers/sstar/pwm/infinity6b0/mhal_pwm.h +new file mode 100755 +index 000000000000..f8ba7078d4f9 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity6b0/mhal_pwm.h +@@ -0,0 +1,152 @@ ++/* ++* mhal_pwm.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 0 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (3) ++#define PWM_PER_GROUP (4) ++#define PWM_NUM (11) ++//Common PWM registers ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++#define u16REG_SW_RESET (0x7F << 2) ++#define u16REG_PWM_INT (0x75 << 2) ++#define u16REG_PWM_DUTY_QE0 (0x76 << 2) ++#define u16REG_PWM_HOLD_MODE1 (0x77 << 2) ++ ++#define REG_GROUP_HOLD (0x71 << 2) ++ #define REG_GROUP_HOLD_SHFT (0x0) ++ ++#define REG_GROUP_STOP (0x72 << 2) ++ #define REG_GROUP_STOP_SHFT (0x0) ++ ++#define REG_GROUP_ENABLE (0x73 << 2) ++ #define REG_GROUP_ENABLE_SHFT (0x0) ++ ++#define REG_GROUP_JOIN (0x74 << 2) ++ #define REG_GROUP_JOIN_SHFT (0x0) ++ ++#define REG_PWM_DUTY_QE0 (0x76 << 2) ++ #define REG_PWM_DUTY_QE0_SHFT (0x0) ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id); ++#ifdef CONFIG_PWM_NEW ++void DrvPWMSetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 duty,U32 period); ++void DrvPWMGetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* Duty,U32* Period); ++#else ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++#endif ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMEnableGet(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMGetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++void DrvPWMSetDben(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++ ++//+++[Only4I6e] ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* u16Val); ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++#if 0 ++int DrvPWMGroupShowStopRound(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++void DrvPWMGroupGetStopRound(U8 u8PwmId); ++#endif ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/infinity6e/mhal_pwm.c b/drivers/sstar/pwm/infinity6e/mhal_pwm.c +new file mode 100755 +index 000000000000..e5fc758d2402 +--- /dev/null ++++ b/drivers/sstar/pwm/infinity6e/mhal_pwm.c +@@ -0,0 +1,1478 @@ ++/* ++* mhal_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_pwm.h" ++#include "gpio.h" ++#include ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++#define BASE_REG_NULL 0xFFFFFFFF ++ ++typedef struct ++{ ++ u32 u32Adr; ++ u32 u32Val; ++ u32 u32Msk; ++} regSet_t; ++ ++typedef struct ++{ ++ u32 u32PadId; ++ regSet_t regSet[2]; ++} pwmPadTbl_t; ++ ++#define PADDEFALUT (0x1F000000) ++#define PMPADTOP (0x3f<<9) ++#define PAD_EXT_MODE (0x55<<2) ++ ++/* ++static pwmPadTbl_t padTbl_0[] = ++{ ++ { PAD_GPIO8, { { BASE_REG_PADTOP_PA + REG_ID_65, (1 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_GPIO0, { { BASE_REG_PADTOP_PA + REG_ID_65, (2 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ //{ PAD_PM_GPIO0, { { BASE_REG_PADTOP_PA + REG_ID_65, (3 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_SR1_IO00, { { BASE_REG_PADTOP_PA + REG_ID_65, (4 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_I2C0_SCL, { { BASE_REG_PADTOP_PA + REG_ID_65, (5 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_FUART_RX, { { BASE_REG_PADTOP_PA + REG_ID_65, (6 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++ { PAD_PM_GPIO1, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_28, (1 << 2), GENMASK(3, 2) } } }, ++ { PAD_PM_GPIO4, { { BASE_REG_NULL, 0, 0 }, { BASE_REG_PMSLEEP_PA + REG_ID_27, (1 << 0), GENMASK(0, 0) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_65, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 0), GENMASK(1, 0) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_1[] = ++{ ++ { PAD_GPIO9, { { BASE_REG_PADTOP_PA + REG_ID_65, (1 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_GPIO1, { { BASE_REG_PADTOP_PA + REG_ID_65, (2 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ //{ PAD_PM_GPIO1, { { BASE_REG_PADTOP_PA + REG_ID_65, (3 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_SR1_IO01, { { BASE_REG_PADTOP_PA + REG_ID_65, (4 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_I2C0_SDA, { { BASE_REG_PADTOP_PA + REG_ID_65, (5 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_FUART_TX, { { BASE_REG_PADTOP_PA + REG_ID_65, (6 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_65, (0 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 2), GENMASK(3, 2) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_2[] = ++{ ++ { PAD_GPIO10, { { BASE_REG_PADTOP_PA + REG_ID_65, (1 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_GPIO2, { { BASE_REG_PADTOP_PA + REG_ID_65, (2 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ //{ PAD_PM_GPIO2, { { BASE_REG_PADTOP_PA + REG_ID_65, (3 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_SR1_IO02, { { BASE_REG_PADTOP_PA + REG_ID_65, (4 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_ETH_LED0, { { BASE_REG_PADTOP_PA + REG_ID_65, (5 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_FUART_CTS, { { BASE_REG_PADTOP_PA + REG_ID_65, (6 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_65, (0 << 8), GENMASK(10, 8)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 6), GENMASK(7, 6) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_3[] = ++{ ++ { PAD_GPIO11, { { BASE_REG_PADTOP_PA + REG_ID_65, (1 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_GPIO3, { { BASE_REG_PADTOP_PA + REG_ID_65, (2 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ //{ PAD_PM_GPIO3, { { BASE_REG_PADTOP_PA + REG_ID_65, (3 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_SR1_IO03, { { BASE_REG_PADTOP_PA + REG_ID_65, (4 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_ETH_LED1, { { BASE_REG_PADTOP_PA + REG_ID_65, (5 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_FUART_RTS, { { BASE_REG_PADTOP_PA + REG_ID_65, (6 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_65, (0 << 12), GENMASK(14, 12)}, { BASE_REG_PMSLEEP_PA + REG_ID_28, (0 << 8), GENMASK(9, 8) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_4[] = ++{ ++ { PAD_GPIO12, { { BASE_REG_PADTOP_PA + REG_ID_66, (1 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ { PAD_GPIO4, { { BASE_REG_PADTOP_PA + REG_ID_66, (2 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ //{ PAD_PM_UART_RX1, { { BASE_REG_PADTOP_PA + REG_ID_66, (3 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ //{ PAD_PM_GPIO4, { { BASE_REG_PADTOP_PA + REG_ID_66, (4 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ { PAD_I2S0_BCK, { { BASE_REG_PADTOP_PA + REG_ID_66, (5 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ //{ PAD_PM_SPI_CZ, { { BASE_REG_PADTOP_PA + REG_ID_66, (6 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_66, (0 << 0), GENMASK(2, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 0), GENMASK(0, 0) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_5[] = ++{ ++ { PAD_GPIO13, { { BASE_REG_PADTOP_PA + REG_ID_66, (1 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ { PAD_GPIO5, { { BASE_REG_PADTOP_PA + REG_ID_66, (2 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ //{ PAD_PM_UART_TX1, { { BASE_REG_PADTOP_PA + REG_ID_66, (3 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ //{ PAD_PM_GPIO5, { { BASE_REG_PADTOP_PA + REG_ID_66, (4 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ { PAD_I2S0_WCK, { { BASE_REG_PADTOP_PA + REG_ID_66, (5 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ //{ PAD_PM_SPI_CK, { { BASE_REG_PADTOP_PA + REG_ID_66, (6 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_66, (0 << 4), GENMASK(6, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 1), GENMASK(1, 1) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_6[] = ++{ ++ { PAD_GPIO14, { { BASE_REG_PADTOP_PA + REG_ID_66, (1 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_GPIO6, { { BASE_REG_PADTOP_PA + REG_ID_66, (2 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++ //{ PAD_PM_I2CM_SCL, { { BASE_REG_PADTOP_PA + REG_ID_66, (3 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++ //{ PAD_PM_GPIO6, { { BASE_REG_PADTOP_PA + REG_ID_66, (4 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_I2S0_DI, { { BASE_REG_PADTOP_PA + REG_ID_66, (5 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++ //{ PAD_PM_SPI_DI, { { BASE_REG_PADTOP_PA + REG_ID_66, (6 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_66, (0 << 8), GENMASK(10, 8)}, { BASE_REG_NULL, 0, 0 } } }, ++}; ++ ++static pwmPadTbl_t padTbl_7[] = ++{ ++ { PAD_GPIO15, { { BASE_REG_PADTOP_PA + REG_ID_66, (1 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_GPIO7, { { BASE_REG_PADTOP_PA + REG_ID_66, (2 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++ //{ PAD_PM_I2CM_SDA, { { BASE_REG_PADTOP_PA + REG_ID_66, (3 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++ //{ PAD_PM_GPIO7, { { BASE_REG_PADTOP_PA + REG_ID_66, (4 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_I2S0_DO, { { BASE_REG_PADTOP_PA + REG_ID_66, (5 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++ //{ PAD_PM_SPI_DO, { { BASE_REG_PADTOP_PA + REG_ID_66, (6 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_66, (0 << 12), GENMASK(14, 12)}, { BASE_REG_NULL, 0, 0 } } }, ++}; ++ ++static pwmPadTbl_t padTbl_8[] = ++{ ++ //{ PAD_PM_GPIO10, { { BASE_REG_PADTOP_PA + REG_ID_67, (1 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_SD0_GPIO0, { { BASE_REG_PADTOP_PA + REG_ID_67, (2 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_ETH_LED1, { { BASE_REG_PADTOP_PA + REG_ID_67, (3 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_SR1_IO00, { { BASE_REG_PADTOP_PA + REG_ID_67, (4 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_GPIO12, { { BASE_REG_PADTOP_PA + REG_ID_67, (5 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_I2C0_SCL, { { BASE_REG_PADTOP_PA + REG_ID_67, (6 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_SR0_IO13, { { BASE_REG_PADTOP_PA + REG_ID_67, (7 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ //{ PAD_PM_GPIO0, { { BASE_REG_PADTOP_PA + REG_ID_67, (8 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_67, (0 << 0), GENMASK(3, 0)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 2), GENMASK(2, 2) } } }, ++}; ++ ++static pwmPadTbl_t padTbl_9[] = ++{ ++ //{ PAD_PM_GPIO9, { { BASE_REG_PADTOP_PA + REG_ID_67, (1 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_FUART_CTS, { { BASE_REG_PADTOP_PA + REG_ID_67, (2 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_ETH_LED0, { { BASE_REG_PADTOP_PA + REG_ID_67, (3 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_SR1_IO12, { { BASE_REG_PADTOP_PA + REG_ID_67, (4 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_GPIO13, { { BASE_REG_PADTOP_PA + REG_ID_67, (5 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_I2C0_SDA, { { BASE_REG_PADTOP_PA + REG_ID_67, (6 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_I2S0_MCLK, { { BASE_REG_PADTOP_PA + REG_ID_67, (7 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ //{ PAD_PM_GPIO1, { { BASE_REG_PADTOP_PA + REG_ID_67, (8 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++ { PAD_UNKNOWN, { { BASE_REG_PADTOP_PA + REG_ID_67, (0 << 4), GENMASK(7, 4)}, { BASE_REG_PMSLEEP_PA + REG_ID_27, (0 << 3), GENMASK(3, 3) } } }, ++}; ++ ++static pwmPadTbl_t* padTbl[] = ++{ ++ padTbl_0, ++ padTbl_1, ++ padTbl_2, ++ padTbl_3, ++ padTbl_4, ++ padTbl_5, ++ padTbl_6, ++ padTbl_7, ++ padTbl_8, ++ padTbl_9, ++}; ++*/ ++static bool _pwmDutyeq0[PWM_NUM] = { 0 }; ++static U8 _pwmEnSatus[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod[PWM_NUM] = { 0 }; ++static U8 _pwmPolarity[PWM_NUM] = { 0 }; ++static U32 _pwmDuty[PWM_NUM][PWM_SHIFT_ARG_MAX_NUM] = {{ 0 }}; //end ( hardware support 0~4 set of duty ) ++static U8 _pwmDutyArgNum[PWM_NUM] = { 0 }; ++static U32 _pwmShft[PWM_NUM][PWM_SHIFT_ARG_MAX_NUM] = {{ 0 }}; //begin ( hardware support 0~4 set of shift ) ++static U8 _pwmShftArgNum[PWM_NUM] = { 0 }; ++static U32 _pwmFreq[PWM_NUM] = { 0 }; ++static bool isSync=1; // isSync=0 --> need to sync register data from mem ++#ifdef CONFIG_PWM_NEW ++static U32 _pwmDiv[PWM_NUM] = { 0 }; ++static U32 _pwmPeriod_ns[PWM_NUM] = { 0 }; ++static U32 _pwmDuty_ns[PWM_NUM] = { 0 }; ++static U16 clk_pwm_div[7] = {1, 2, 4, 8, 32, 64, 128}; ++#endif ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++static void DrvPWMGetGrpAddr(struct mstar_pwm_chip* ms_chip,U32 *u32addr,U32 *u32PwmOffs,U8 u8Id) ++{ ++ if( u8Id < (PWM_NUM - 1)) ++ { ++ *u32addr = (U32 )ms_chip->base; ++ *u32PwmOffs = (u8Id < 4) ? (u8Id * 0x80) : ((4 * 0x80) + ((u8Id - 4) * 0x40)); ++ } ++ else ++ { ++ if(ms_chip->group_data != NULL) ++ { ++ *u32addr = (U32 )ms_chip->group_data; ++ *u32PwmOffs = 0; ++ } ++ else ++ { ++ *u32addr = (U32 )ms_chip->base; ++ *u32PwmOffs = 0; ++ } ++ } ++} ++ ++ ++void MDEV_PWM_MemToReg(struct mstar_pwm_chip* ms_chip, U8 u8GrpId) ++{ ++ U8 pwmId, idx; ++ for(idx=0; idxpad_ctrl[u8Id] >= PAD_PM_GPIO0) && (ms_chip->pad_ctrl[u8Id] <= PAD_PM_GPIO7)) ++ { ++ //printk("[NOTICE]ms_chip->pad_ctrl[%d]=%d 1<< %d \n",u8Id,ms_chip->pad_ctrl[u8Id],ms_chip->pad_ctrl[u8Id]-2); ++ SETREG16(PADDEFALUT + PMPADTOP + PAD_EXT_MODE, BIT0<<(ms_chip->pad_ctrl[u8Id]-2)); ++ } ++ return 0; ++} ++ ++int DrvGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U16 u32JoinMask = 0X0000; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ MDEV_PWM_SetSyncFlag(1); //dont need to sync until new data in ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ } ++ return 1; ++} ++ ++//+++[Only4I6e] ++void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip) ++{ ++ U8 i=0; ++ MDEV_PWM_SetClock(); ++ for (i = 0; i < PWM_GROUP_NUM; i++) { ++ //Suggest driver owner default open each group_enable(h'73) and ++ //each group bit0 sync_mode for general mode. ++ DrvGroupEnable(ms_chip, i, 1); ++ //printk(KERN_NOTICE "[NOTICE]Each grp enable must be enabled!\r\n"); ++ } ++} ++ ++//---[Only4I6e] ++ ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id) ++{ ++ U32 reset, u32Period=0, U32PwmAddr=0,u32PwmOffs=0; ++ if (!u8Id) { ++ U8 i; ++ for (i = 0; i < PWM_GROUP_NUM; i++) { ++ //[interrupt function] ++ //Each group bit0 must enable for interrupt function ++ //please see sync mode description for detail ++ //SW owner default need to enable h'74 bit0, bit4, bit8 ++ DrvPWMGroupJoin(ms_chip, (i*PWM_PER_GROUP), 1); ++ OUTREGMSK16( BASE_REG_CHIPTOP_PA + REG_ID_12, 0x00, BIT4|BIT5); //reg_test_out_mode=0 ++ } ++ printk(KERN_DEBUG "[NOTICE]Each grp bit0 must be enabled!\r\n"); ++ } ++ if (PWM_NUM <= u8Id) ++ return; ++ DrvPm_PWMSet(ms_chip,u8Id); ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ reset = INREG16( U32PwmAddr + u16REG_SW_RESET) & (BIT0<<((u8Id==10)?0:u8Id)); ++ DrvPWMDutyQE0(ms_chip, 0, 0); ++ ++#ifdef CONFIG_PWM_NEW ++ DrvPWMGetConfig(ms_chip, u8Id, NULL ,&u32Period); ++#else ++ DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++#endif ++ ++ if ((0 == reset) && (u32Period)) ++ { ++ _pwmEnSatus[u8Id] = 1; ++ } ++ else ++ { ++ DrvPWMEnable(ms_chip, u8Id, 0); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDuty ++// ++// Description ++// Set Duty value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Duty value (percentage) ++// ++// Return Value ++// None ++// ++#ifdef CONFIG_PWM_NEW ++void DrvPWMSetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 duty,U32 period) ++{ ++ U8 i; ++ U16 u16Div = 0; ++ U32 common = 0; ++ U32 pwmclk = 0; ++ U32 periodmax = 0; ++ U32 u32Period = 0x00000000; ++ U32 u32Duty = 0x00000000; ++ U32 U32PwmAddr = 0; ++ U32 u32PwmOffs = 0; ++ ++ if(u8Id >= PWM_NUM) ++ return; ++ _pwmDutyeq0[u8Id] = (duty == 0) ? TRUE : FALSE; ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ ++ /* select div */ ++ for(i = 0;i<(sizeof(clk_pwm_div)/sizeof(U16));i++){ ++ periodmax = (clk_pwm_div[i] * 262144 / pwmclk) * common; ++ if(period < periodmax) ++ { ++ u16Div = clk_pwm_div[i]; ++ _pwmDiv[u8Id] = clk_pwm_div[i]; ++ break; ++ } ++ } ++ ++ /* select period */ ++ if(period < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Period= (pwmclk * period) / (u16Div * common); ++ if(((pwmclk * period) % (u16Div * common)) > (u16Div * common / 2)) ++ { ++ u32Period++; ++ } ++ _pwmPeriod_ns[u8Id] = (u32Period * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Period= (period / u16Div) * pwmclk / common; ++ u32Period++; ++ _pwmPeriod_ns[u8Id] = (u32Period * common / pwmclk) * u16Div; ++ } ++ ++ /* select duty */ ++ if(duty == 0) ++ { ++ if(_pwmEnSatus[u8Id]) ++ { ++ SETREG16(U32PwmAddr + u16REG_SW_RESET,BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ } ++ else ++ { ++ if(_pwmEnSatus[u8Id]) ++ { ++ CLRREG16(U32PwmAddr + u16REG_SW_RESET, BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ } ++ ++ if(duty < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Duty= (pwmclk * duty) / (u16Div * common); ++ if((((pwmclk * duty) % (u16Div * common)) > (u16Div * common / 2)) || (u32Duty == 0)) ++ { ++ u32Duty++; ++ } ++ _pwmDuty_ns[u8Id] = (u32Duty * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Duty= (duty / u16Div) * pwmclk / common; ++ u32Duty++; ++ _pwmPeriod_ns[u8Id] = (u32Duty * common / pwmclk) * u16Div; ++ } ++ ++ /* set div period duty */ ++ u16Div--; ++ u32Period--; ++ u32Duty--; ++ pr_err("clk=%d, u16Div=%d u32Duty=0x%x u32Period=0x%x\n", (U32)(clk_get_rate(ms_chip->clk)), u16Div, u32Duty, u32Period); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DIV, (u16Div & 0xFFFF)); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++} ++ ++void DrvPWMGetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* Duty,U32* Period) ++{ ++ U16 u16Div = 0; ++ U32 u32Duty = 0; ++ U32 u32Period = 0; ++ U32 U32PwmAddr= 0; ++ U32 pwmclk = 0; ++ U32 common = 0; ++ U32 u32PwmOffs = 0; ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ ++ if(u8Id >= PWM_NUM) ++ return; ++ ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ ++ u16Div = INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DIV); ++ u16Div++; ++ ++ if(Period != NULL) ++ { ++ if(_pwmPeriod_ns[u8Id] == 0) ++ { ++ u32Period = INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_L) | ((INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if(u32Period) ++ { ++ u32Period++; ++ } ++ _pwmPeriod_ns[u8Id] = (u32Period * u16Div * common) / pwmclk; ++ } ++ *Period = _pwmPeriod_ns[u8Id]; ++ } ++ ++ if(Duty != NULL) ++ { ++ if(_pwmDuty_ns[u8Id] == 0) ++ { ++ u32Duty = INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_L) | ((INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if(u32Duty) ++ { ++ u32Duty++; ++ } ++ _pwmDuty_ns[u8Id] = (u32Duty * u16Div * common) / pwmclk; ++ } ++ *Duty = _pwmDuty_ns[u8Id]; ++ } ++ ++} ++ ++#else ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ U32 u32Duty = 0x00000000; ++ U32 U32PwmAddr=0; ++ U32 u32PwmOffs = 0; ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ ++ if (PWM_NUM <= u8Id){ ++ return; ++ } ++ ++ _pwmDutyeq0[u8Id] = (u32Val == 0) ? TRUE : FALSE; ++ MDEV_PWM_SetClock(); ++ if (_pwmEnSatus[u8Id]) ++ { ++ if (_pwmDutyeq0[u8Id]) ++ OUTREGMSK16(U32PwmAddr + u16REG_SW_RESET, BIT0<<((u8Id==10)?0:u8Id),BIT0<<((u8Id==10)?0:u8Id)); ++ } ++ if(u32Val == 0) ++ { ++ u32Duty = 0; ++ }else ++ { ++ if(u32Val > 100) ++ { ++ u32Val = 100; ++ } ++ u32Period = _pwmPeriod[u8Id]; ++ u32Period++; ++ u32Duty = ((u32Period * u32Val) / 100); ++ if(((u32Period * u32Val) % 100) < 50) ++ { ++ u32Duty--; ++ } ++ } ++ pr_err("reg=x%08X(x%x) clk=%d, u32Duty=x%x\n", (U32)(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_L), ++ ((U32)(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_L)&0xFFFFFF)>>9, ++ (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++ ++ if (_pwmEnSatus[u8Id]) ++ { ++ U32 reset = INREG16(U32PwmAddr + u16REG_SW_RESET) & (BIT0<<((u8Id==10)?0:u8Id)); ++ if (u32Val && reset) ++ CLRREG16(U32PwmAddr + u16REG_SW_RESET, BIT0<<((u8Id==10)?0:u8Id)); ++ } ++} ++ ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Duty,U32PwmAddr=0; ++ U32 u32PwmOffs = 0; ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ ++ *pu32Val = 0; ++ if (PWM_NUM <= u8Id) ++ return; ++ u32Duty = INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_L) | ((INREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ if (u32Duty) ++ { ++ U32 u32Period = _pwmPeriod[u8Id]; ++ // DrvPWMGetPeriod(ms_chip, u8Id, &u32Period); ++ if (u32Period) ++ { ++ *pu32Val = (u32Duty * 100)/u32Period; ++ } ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value (hz) ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period = 0x00000000; ++ U32 U32PwmAddr=0; ++ U32 u32FrqHz = u32Val; ++ U32 u32PwmOffs = 0; ++ ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ MDEV_PWM_SetClock(); ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32FrqHz; ++ ++ //[APN] range 2<=Period<=262144 ++// if(u32Period < 100) { ++// u32Period = 100; ++// } ++// else ++ if(u32Period > 262144) { ++ u32Period = 262144; ++ } ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ ++ pr_err("reg=x%08X(x%x) clk=%d, period=x%x\n", (U32)(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_L), ++ ((U32)(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_L)&0xFFFFFF)>>9, ++ (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++ _pwmPeriod[u8Id] = u32Period; ++} ++ ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val) ++{ ++ U32 u32Period, u32PwmAddr=0; ++ U32 u32PwmOffs = 0; ++ ++ DrvPWMGetGrpAddr(ms_chip,&u32PwmAddr,&u32PwmOffs,u8Id); ++ ++ u32Period = INREG16(u32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_L) | ((INREG16(u32PwmAddr + (u32PwmOffs) + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ if ((0 == _pwmPeriod[u8Id]) && (u32Period)) ++ { ++ _pwmPeriod[u8Id] = u32Period; ++ } ++ *pu32Val = 0; ++ if (u32Period) ++ { ++ *pu32Val = (U32)(clk_get_rate(ms_chip->clk))/(u32Period+1); ++ } ++} ++#endif ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ U32 U32PwmAddr=0; ++ U32 u32PwmOffs = 0; ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,u8Id); ++ OUTREGMSK16(U32PwmAddr + (u32PwmOffs) + u16REG_PWM_CTRL, (u8Val<base + (u32PwmOffs) + u16REG_PWM_CTRL) & (0x1<regSet; ++// printk("[%s][%d] ******************************\n", __FUNCTION__, __LINE__); ++// printk("[%s][%d] pad Id = %d\n", __FUNCTION__, __LINE__, pTbl->u32PadId); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++// printk("[%s][%d] (reg, val, msk) = (0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++// if (PAD_UNKNOWN == pTbl->u32PadId) ++// { ++// break; ++// } ++// pTbl++; ++// } ++// } ++//} ++ ++void DrvPWMPadSet(U8 u8Id, U8 u8Val) ++{ ++ /* ++ pwmPadTbl_t* pTbl = NULL; ++ if (PWM_NUM <= u8Id) ++ { ++ printk(KERN_ERR "[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ return; ++ } ++ printk("[%s][%d] (pwmId, padId) = (%d, %d)\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ pTbl = padTbl[u8Id]; ++ while (1) ++ { ++ if (u8Val == pTbl->u32PadId) ++ { ++ regSet_t* pRegSet = pTbl->regSet; ++ U32 Reg0=(pRegSet[0].u32Adr&0xFFFFFF), Reg1=(pRegSet[1].u32Adr&0xFFFFFF); ++ printk("[%s][%d]PDTOP x%x(x%x_x%x), x%x(x%x_x%x)\n", __FUNCTION__, __LINE__, ++ pRegSet[0].u32Adr, Reg0>>9, (Reg0-((Reg0>>9)<<9))>>2, ++ pRegSet[1].u32Adr, Reg1>>9, (Reg1-((Reg1>>9)<<9))>>2); ++ if (BASE_REG_NULL != pRegSet[0].u32Adr) ++ { ++ OUTREGMSK16(pRegSet[0].u32Adr, pRegSet[0].u32Val, pRegSet[0].u32Msk); ++ } ++ if (BASE_REG_NULL != pRegSet[1].u32Adr) ++ { ++ OUTREGMSK16(pRegSet[1].u32Adr, pRegSet[1].u32Val, pRegSet[1].u32Msk); ++ } ++ MDEV_PWM_SetClock(); ++ break; ++ } ++ if (PAD_UNKNOWN == pTbl->u32PadId) ++ { ++ printk(KERN_ERR "[%s][%d] void DrvPWMEnable error!!!! (%x, %x)\r\n", __FUNCTION__, __LINE__, u8Id, u8Val); ++ break; ++ } ++ pTbl++; ++ } ++ */ ++} ++ ++int DrvPWMGroupCap(void) ++{ ++ return (PWM_GROUP_NUM) ? 1 : 0; ++} ++ ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val) ++{ ++ if (PWM_NUM <= u8PWMId) ++ return 0; ++ if(u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ } ++ else { ++ //[interrupt function] ++ //Each group bit0 must enable for interrupt function ++ //please see sync mode description for detail ++ //SW owner default need to enable h74 bit0, bit4, bit8 ++ if (!(u8PWMId%4)) { ++ printk(KERN_WARNING "[%s][%d] Always enable BIT_%2d for sync mode!\r\n", __FUNCTION__, __LINE__, u8PWMId); ++ return 0; ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_JOIN, (1 << (u8PWMId + REG_GROUP_JOIN_SHFT))); ++ } ++ } ++ return 1; ++} ++ ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ U32 u32JoinMask; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if(!MDEV_PWM_GetSyncFlag()) ++ { ++ MDEV_PWM_MemToReg(ms_chip, u8GroupId); ++ printk("MEM to REG done !\n"); ++ } ++ ++ u32JoinMask = ((u8GroupId == 2)?0x7:0xF) << ((u8GroupId << 2) + REG_GROUP_JOIN_SHFT); ++ u32JoinMask = INREG16(ms_chip->base + REG_GROUP_JOIN) & u32JoinMask; ++ u32JoinMask |= 1 << (u8GroupId + PWM_NUM); ++ ++ if (u8Val) ++ { ++ SETREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ CLRREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ MDEV_PWM_SetSyncFlag(1); //dont need to sync until new data in ++ } ++ else ++ { ++ CLRREG16(ms_chip->base + REG_GROUP_ENABLE, (1 << (u8GroupId + REG_GROUP_ENABLE_SHFT))); ++ SETREG16(ms_chip->base + u16REG_SW_RESET, u32JoinMask); ++ ++ } ++ if(u32JoinMask & (BIT0<<(PWM_NUM-1))){ ++ if(ms_chip->group_data != NULL){ ++ if(u8Val){ ++ CLRREG16(((U32)ms_chip->group_data) + u16REG_SW_RESET, BIT0); ++ }else{ ++ SETREG16(((U32)ms_chip->group_data) + u16REG_SW_RESET, BIT0); ++ } ++ } ++ } ++ return 1; ++} ++ ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val) ++{ ++ *pu8Val = 0; ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ *pu8Val = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> (u8GroupId + REG_GROUP_ENABLE_SHFT)) & 0x1; ++ return 1; ++} ++ ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* pu16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ *pu16Val = INREG16(ms_chip->base + u32Reg) & 0xFFFF; ++ return 1; ++} ++ ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val) ++{ ++ U32 u32Reg; ++ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ u32Reg = (u8GroupId << 0x7) + 0x40; ++ OUTREG16(ms_chip->base + u32Reg, u16Val); ++ return 1; ++} ++ ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_STOP, (1 << (u8GroupId + REG_GROUP_STOP_SHFT))); ++ ++ return 1; ++} ++ ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ if (PWM_GROUP_NUM <= u8GroupId) ++ return 0; ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ else ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD, (1 << (u8GroupId + REG_GROUP_HOLD_SHFT))); ++ ++ return 1; ++} ++ ++//+++[Only4I6e] ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip) ++{ ++#if 1 ++ return INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++ return 1; ++#endif ++} ++ ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val) ++{ ++#if 1 ++ if (u8Val) { ++ SETREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 1); ++ printk("[%s L%d] hold mode1 en!(keep low)\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ CLRREG16(ms_chip->base + REG_GROUP_HOLD_MODE1, 0); ++ printk("[%s L%d] hold mode1 dis!\n", __FUNCTION__, __LINE__); ++ } ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++ ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val) ++{ ++ ++ if (u8Val) ++ SETREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << REG_PWM_DUTY_QE0_SHFT)); ++ else ++ CLRREG16(ms_chip->base + REG_PWM_DUTY_QE0, (1 << REG_PWM_DUTY_QE0_SHFT)); ++ ++ return 1; ++} ++ ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output) ++{ ++#if 1 ++ *pu8Output = INREG16(ms_chip->base + REG_PWM_OUT); ++ printk("[%s L%d] output:x%x\n", __FUNCTION__, __LINE__, *pu8Output); ++#else ++ //printk("\n[WARN][%s L%d] Only4i6e\n", __FUNCTION__, __LINE__); ++#endif ++ return 1; ++} ++//---[Only4I6e] ++#ifdef CONFIG_PWM_NEW ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U16 u16Div = 0; ++ U32 common = 0; ++ U32 pwmclk = 0; ++ U32 duty = u32Val; ++ U32 u32Duty = 0; ++ if(u8Id >= PWM_NUM) ++ return 0; ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ u16Div = (_pwmDiv[u8Id] + 1); ++ if(duty < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Duty= (pwmclk * duty) / (u16Div * common); ++ if((((pwmclk * duty) % (u16Div * common)) > (u16Div * common / 2)) || (u32Duty == 0)) ++ { ++ u32Duty++; ++ } ++ _pwmDuty_ns[u8Id] = (u32Duty * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Duty= (duty / u16Div) * pwmclk / common; ++ u32Duty++; ++ _pwmDuty_ns[u8Id] = (u32Duty * common / pwmclk) * u16Div; ++ } ++ u32Duty--; ++ _pwmDutyArgNum[u8Id] = u8DutyId; ++ _pwmDuty[u8Id][u8DutyId] = u32Duty; ++ return 1; ++} ++#else ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Duty; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ ++ // u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ u32Period = _pwmPeriod[u8Id]; ++ u32Duty = ((u32Period * u32Val) / 1000); ++ _pwmDutyArgNum[u8Id] = u8DutyId; ++ _pwmDuty[u8Id][u8DutyId] = u32Duty; ++ MDEV_PWM_SetSyncFlag(0); ++ ++ if (u32Duty & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large duty 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Duty); ++ } ++ return 1; ++} ++#endif ++int DrvPWMSetEndToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyArgNum) ++{ ++ U8 arg_no; ++ for(arg_no=0; arg_no <= u8DutyArgNum; arg_no++) ++ { ++ if (0 == arg_no) { ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_DUTY_L, (_pwmDuty[u8Id][arg_no]&0xFFFF)); ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_DUTY_H, ((_pwmDuty[u8Id][arg_no]>> 16)&0x0003)); ++ } ++ else { ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + (arg_no << 3) + 28, (_pwmDuty[u8Id][arg_no]&0xFFFF)); ++ } ++ } ++ return 1; ++} ++#ifdef CONFIG_PWM_NEW ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U16 u16Div = 0; ++ U32 common = 0; ++ U32 pwmclk = 0; ++ U32 shift = u32Val; ++ U32 u32Shift = 0; ++ if(u8Id >= PWM_NUM) ++ return 0; ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ u16Div = (_pwmDiv[u8Id] + 1); ++ if(shift < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Shift= (pwmclk * shift) / (u16Div * common); ++ if((((pwmclk * shift) % (u16Div * common)) > (u16Div * common / 2)) || (u32Shift == 0)) ++ { ++ u32Shift++; ++ } ++ } ++ else ++ { ++ u32Shift= (shift / u16Div) * pwmclk / common; ++ u32Shift++; ++ } ++ u32Shift--; ++ _pwmShftArgNum[u8Id] = u8ShftId; ++ _pwmShft[u8Id][u8ShftId] = u32Shift; ++ MDEV_PWM_SetSyncFlag(0); ++ return 1; ++} ++#else ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Shft; ++ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ ++ u32Period = _pwmPeriod[u8Id]; ++ u32Shft = ((u32Period * u32Val) / 1000); ++ _pwmShftArgNum[u8Id] = u8ShftId; ++ _pwmShft[u8Id][u8ShftId] = u32Shft; ++ MDEV_PWM_SetSyncFlag(0); ++ ++ if (u32Shft & 0xFFFC0000) ++ { ++ printk("[%s][%d] too large shift 0x%08x (18 bits in max)\n", __FUNCTION__, __LINE__, u32Shft); ++ } ++ ++ return 1; ++} ++#endif ++int DrvPWMSetBeginToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftArgNum) ++{ ++ U8 arg_no; ++ for(arg_no=0; arg_no <= u8ShftArgNum; arg_no++) ++ { ++ if (0 == arg_no) { ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_SHIFT_L, (_pwmShft[u8Id][arg_no]&0xFFFF)); ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_SHIFT_H, ((_pwmShft[u8Id][arg_no]>> 16)&0x0003)); ++ } ++ else { ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + (arg_no << 3) + 24, (_pwmShft[u8Id][arg_no]&0xFFFF)); ++ } ++ } ++ return 1; ++} ++ ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ _pwmPolarity[u8Id] = u8Val; ++ MDEV_PWM_SetSyncFlag(0); ++ return 1; ++} ++ ++int DrvPWMSetPolarityExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (u8Val) ++ SETREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_CTRL, (0x1<base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_CTRL, (0x1<= PWM_NUM) ++ return; ++ pwmclk = (U32)(clk_get_rate(ms_chip->clk)); ++ switch(pwmclk) ++ { ++ case 12000000: ++ pwmclk = 3; ++ common = 250; ++ break; ++ default: ++ pwmclk = 3; ++ common = 250; ++ } ++ ++ /* select div */ ++ for(i = 0;i<(sizeof(clk_pwm_div)/sizeof(U16));i++){ ++ periodmax = (clk_pwm_div[i] * 262144 / pwmclk) * common; ++ if(period < periodmax) ++ { ++ u16Div = clk_pwm_div[i]; ++ break; ++ } ++ } ++ ++ /* select period */ ++ if(period < (0xFFFFFFFF / pwmclk)) ++ { ++ u32Period= (pwmclk * period) / (u16Div * common); ++ if(((pwmclk * period) % (u16Div * common)) > (u16Div * common / 2)) ++ { ++ u32Period++; ++ } ++ _pwmPeriod_ns[u8Id] = (u32Period * u16Div * common) / pwmclk; ++ } ++ else ++ { ++ u32Period= (period / u16Div) * pwmclk / common; ++ u32Period++; ++ _pwmPeriod_ns[u8Id] = (u32Period * common / pwmclk) * u16Div; ++ } ++ u16Div--; ++ u32Period--; ++ _pwmDiv[u8Id] = u16Div; ++ _pwmPeriod[u8Id] = u32Period; ++ _pwmFreq[u8Id] = 1000000000/u32Val; ++ MDEV_PWM_SetSyncFlag(0); ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++} ++ ++#else ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Div; ++ ++ u32Div = INREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_DIV); // workaround ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ u32Period /= (u32Div + 1); // workaround ++ ++ //[APN] range 2<=Period<=262144 ++ if(u32Period < 2) ++ u32Period = 2; ++ if(u32Period > 262144) ++ u32Period = 262144; ++ ++ //[APN] PWM _PERIOD= (REG_PERIOD+1) ++ u32Period--; ++ _pwmPeriod[u8Id] = u32Period; ++ _pwmFreq[u8Id] = u32Val; ++ MDEV_PWM_SetSyncFlag(0); ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++} ++#endif ++void DrvPWMSetPeriodExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Period) ++{ ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++} ++ ++#if 0 ++int DrvPWMSetMPluse(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ if (PWM_NUM <= u8Id) ++ return 0; ++ if (u8Val) ++ SETREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + (u8Id*0x80) + u16REG_PWM_CTRL, (0x1<base + ((u8Id < 4) ? (u8Id*0x80) : (u8Id*0x40 + 4*0x40)) + u16REG_PWM_DIV, u8Val); ++ printk("mhal DrvPWMDiv done !\n"); ++ ++ return 1; ++} ++ ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ return 0; ++} ++ ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end) ++{ ++ char *str = buf_start; ++ char *end = buf_end; ++ int i; ++ // U32 tmp; ++ U32 u32Period, u32Polarity; // , u32MPluse; ++ // U32 u32Shft0, u32Shft1, u32Shft2, u32Shft3; ++ U32 u32Shft0; ++ // U32 u32Duty0, u32Duty1, u32Duty2, u32Duty3; ++ U32 u32Duty0; ++ U32 u32SyncStatus; ++ U32 u32ResetStatus; ++ U32 u32GroupEnable, u32GroupReset, u32GroupHold, u32GroupStop, u32GroupRound; ++ U32 clk = (U32)clk_get_rate(ms_chip->clk); ++ U32 u32Div; ++ U32 u32PwmOffs; ++ U32 U32PwmAddr; ++ if (0 == DrvPWMGroupCap()) ++ { ++ str += scnprintf(str, end - str, "This chip does not support motor interface\n"); ++ return (str - buf_start); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ str += scnprintf(str, end - str, "HoldM1\t\t%d\n", INREG16(ms_chip->base + REG_GROUP_HOLD_MODE1)); ++ for (i = 0; i < PWM_GROUP_NUM; i++) ++ { ++ U32 pwmIdx; ++ U32 j; ++ ++ // group enable ++ u32GroupEnable = (INREG16(ms_chip->base + REG_GROUP_ENABLE) >> i) & 0x1; ++ // group reset ++ u32GroupReset = (INREG16(ms_chip->base + u16REG_SW_RESET) >> (i + PWM_NUM)) & 0x1; ++ // hold ++ u32GroupHold = (INREG16(ms_chip->base + REG_GROUP_HOLD) >> (i + REG_GROUP_HOLD_SHFT)) & 0x1; ++ // stop ++ u32GroupStop = (INREG16(ms_chip->base + REG_GROUP_STOP) >> (i + REG_GROUP_STOP_SHFT)) & 0x1; ++ // round ++ u32GroupRound = INREG16(ms_chip->base + ((i << 0x7) + 0x40)) & 0xFFFF; ++ ++ str += scnprintf(str, end - str, "Group %d\n", i); ++ pwmIdx = (i << 2); ++ str += scnprintf(str, end - str, "\tmember\t\t"); ++ for (j = pwmIdx; j < pwmIdx + 4; j++) ++ { ++ if (j < PWM_NUM) ++ { ++ str += scnprintf(str, end - str, "%d ", j); ++ } ++ } ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "\tenable status\t%d\n", u32GroupEnable); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32GroupReset); ++ str += scnprintf(str, end - str, "\tHold\t\t%d\n", u32GroupHold); ++ str += scnprintf(str, end - str, "\tStop\t\t%d\n", u32GroupStop); ++ str += scnprintf(str, end - str, "\tRound\t\t%d\n", u32GroupRound); ++ } ++ ++ str += scnprintf(str, end - str, "================================================\n"); ++ ++ for (i = 0; i < PWM_NUM; i++) ++ { ++ DrvPWMGetGrpAddr(ms_chip,&U32PwmAddr,&u32PwmOffs,i); ++ ++ // Polarity ++ u32Polarity = (INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_CTRL) >> POLARITY_BIT) & 0x1; ++ // u32MPluse = (INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_CTRL) >> DIFF_P_EN_BIT) & 0x1; ++ // Period ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_PERIOD_H))) ++ printk("[%s][%d] pwmId %d period_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ ++ u32Period = INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_PERIOD_L)|((INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_PERIOD_H) & 0x3) << 16); ++ // Shift ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT_H))) ++ printk("[%s][%d] pwmId %d shift_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Shft0 = INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_SHIFT_L) | ((INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_SHIFT_H) & 0x3) << 16); ++ // u32Shft1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT2); ++ // u32Shft2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT3); ++ // u32Shft3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_SHIFT4); ++ // Duty ++#if 0 ++ if ((tmp = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY_H))) ++ printk("[%s][%d] pwmId %d duty_h is not zero (0x%08x)\n", __FUNCTION__, __LINE__, i, tmp); ++#endif ++ u32Duty0 = INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_DUTY_L) | ((INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_DUTY_H) & 0x3) << 16); ++ u32Duty0 -=u32Shft0; ++ // u32Duty1 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY2); ++ // u32Duty2 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY3); ++ // u32Duty3 = INREG16(ms_chip->base + (i*0x80) + u16REG_PWM_DUTY4); ++ // sync mode status ++ u32SyncStatus = (INREG16(U32PwmAddr + REG_GROUP_JOIN) >> (i + REG_GROUP_JOIN_SHFT)) & 0x1; ++ // rest status ++ u32ResetStatus = (INREG16(U32PwmAddr + u16REG_SW_RESET)>>((i==10)?0:i)) & BIT0; ++ u32Div = INREG16(U32PwmAddr + u32PwmOffs + u16REG_PWM_DIV); // workaround ++ ++ ++ // output to buffer ++ str += scnprintf(str, end - str, "Pwm %d\n", i); ++ str += scnprintf(str, end - str, "\tPad\t\t0x%08x\n", ms_chip->pad_ctrl[i]); ++ str += scnprintf(str, end - str, "\tSync status\t%d\n", u32SyncStatus); ++ str += scnprintf(str, end - str, "\tReset status\t%d\n", u32ResetStatus); ++ str += scnprintf(str, end - str, "\tPolarity\t%d\n", u32Polarity); ++#if 0 ++ str += scnprintf(str, end - str, "\tPeriod\t\t0x%08x\n", u32Period); ++ str += scnprintf(str, end - str, "\tBegin\t\t0x%08x\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t0x%08x\n", u32Duty0); ++#endif ++ u32Period++; ++ u32Shft0++; ++ u32Duty0++; ++ u32Shft0 = (1000 * u32Shft0)/u32Period; ++ u32Duty0 = (1000 * u32Duty0)/u32Period; ++ // u32Period = ((u32Div+1)*clk)/u32Period; ++ u32Period = clk/u32Period/(u32Div+1); ++ ++ str += scnprintf(str, end - str, "\tPeriod\t\t%d\n", u32Period); ++ // str += scnprintf(str, end - str, "\tBegin\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Shft0, u32Shft1, u32Shft2, u32Shft3); ++ // str += scnprintf(str, end - str, "\tEnd\t\t0x%08x 0x%08x 0x%08x 0x%08x\n", u32Duty0, u32Duty1, u32Duty2, u32Duty3); ++ str += scnprintf(str, end - str, "\tBegin\t\t%d\n", u32Shft0); ++ str += scnprintf(str, end - str, "\tEnd\t\t%d\n", u32Duty0); ++ } ++ // str += scnprintf(str, end - str, "This is a test\n"); ++ return (str - buf_start); ++} ++ ++irqreturn_t PWM_IRQ(int irq, void *data) ++{ ++#if 1 //Only4i6e ++ volatile u16 u16_Events = 0x0000; ++ volatile u16 gid = 0x0000; ++ struct mstar_pwm_chip *ms_chip = (struct mstar_pwm_chip *)data; ++ ++ u16_Events = INREG16(ms_chip->base + REG_GROUP_INT); ++ if ((u16_Events&PWM_INT_GRP_MASK)) { ++ for (gid = 0; gid>REG_GROUP_HOLD_INT_SHFT) & (1<>REG_GROUP_RUND_INT_SHFT)) { ++ for (gid = 0; gid>REG_GROUP_RUND_INT_SHFT) & (1< ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#if 1 ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++#else ++#define MS_PWM_INFO(x, args...) {} ++#define MS_PWM_DBG(x, args...) {} ++#endif ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++ void* group_data; ++ int irq; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++#define PWM_GROUP_NUM (3) ++#define PWM_PER_GROUP (4) ++#define PWM_NUM (11) ++//Common PWM registers ++#define PWM_SHIFT_ARG_MAX_NUM (4) ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++#define REG_GROUP_HOLD (0x71 << 2) ++ #define REG_GROUP_HOLD_SHFT (0x0) ++ ++#define REG_GROUP_STOP (0x72 << 2) ++ #define REG_GROUP_STOP_SHFT (0x0) ++ ++#define REG_GROUP_ENABLE (0x73 << 2) ++ #define REG_GROUP_ENABLE_SHFT (0x0) ++ ++#define REG_GROUP_JOIN (0x74 << 2) ++ #define REG_GROUP_JOIN_SHFT (0x0) ++ ++//+++[Only4I6e] ++#define REG_GROUP_INT (0x75 << 2) ++ #define REG_GROUP_HOLD_INT_SHFT (0x0) ++ #define REG_GROUP_RUND_INT_SHFT (0x3) ++ #define PWM_INT_GRP0 (BIT0) ++ #define PWM_INT_GRP1 (BIT1) ++ #define PWM_INT_GRP2 (BIT2) ++ #define PWM_INT_GRP_MASK (0x07) //GRP0~GRP2 ++ ++#define REG_PWM_DUTY_QE0 (0x76 << 2) ++ #define REG_PWM_DUTY_QE0_SHFT (0x0) ++ ++#define REG_GROUP_HOLD_MODE1 (0x77 << 2) ++ #define REG_GROUP_HALD_MD1_SHFT (0x0) ++ ++#define REG_PWM_OUT (0x7E << 2) ++ #define REG_PWM_OUT_SHFT (0x0) ++//---[Only4I6e] ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++// 86MHz related definitions ++#define CLOCK_SRC_86MHZ 86000000 ++#define PMSLEEP_86MHz_VAL 0x5 ++#define PMSLEEP_86MHz_POS 12 ++#define DIGPM_86MHz_POS 5 ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMInit(struct mstar_pwm_chip *ms_chip, U8 u8Id); ++#ifdef CONFIG_PWM_NEW ++void DrvPWMSetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 duty,U32 period); ++void DrvPWMGetConfig(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* Duty,U32* Period); ++#else ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMGetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32* pu32Val); ++#endif ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMEnableGet(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMGetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8* pu8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++void DrvPWMSetDben(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++ ++int DrvPWMSetBegin(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId, U32 u32Val); ++int DrvPWMSetEnd(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId, U32 u32Val); ++int DrvPWMSetPolarityEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodEx(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++int DrvPWMDiv(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); // workaround for group hold/round malfunctional when div is zero ++ ++ ++int DrvPWMGroupCap(void); ++int DrvPWMGroupJoin(struct mstar_pwm_chip* ms_chip, U8 u8PWMId, U8 u8Val); ++int DrvPWMGroupEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupIsEnable(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U8* pu8Val); ++int DrvPWMGroupGetRoundNum(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16* pu16Val); ++int DrvPWMGroupShowRoundNum(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++int DrvPWMGroupSetRound(struct mstar_pwm_chip* ms_chip, U8 u8GroupId, U16 u16Val); ++int DrvPWMGroupStop(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupHold(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGroupInfo(struct mstar_pwm_chip *ms_chip, char* buf_start, char* buf_end); ++ ++//+++[Only4I6e] ++int DrvPWMSetEndToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8DutyId); ++int DrvPWMSetBeginToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8ShftId); ++int DrvPWMSetPolarityExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriodExToReg(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Period); ++ ++int DrvPWMGroupGetHoldM1(struct mstar_pwm_chip *ms_chip); ++int DrvPWMGroupHoldM1(struct mstar_pwm_chip *ms_chip, U8 u8Val); ++int DrvPWMDutyQE0(struct mstar_pwm_chip *ms_chip, U8 u8GroupId, U8 u8Val); ++int DrvPWMGetOutput(struct mstar_pwm_chip *ms_chip, U8* pu8Output); ++//---[Only4I6e] ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/sstar/pwm/mdrv_pwm.c b/drivers/sstar/pwm/mdrv_pwm.c +new file mode 100755 +index 000000000000..8461646baa20 +--- /dev/null ++++ b/drivers/sstar/pwm/mdrv_pwm.c +@@ -0,0 +1,700 @@ ++/* ++* mdrv_pwm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_msys.h" ++#include "mhal_pwm.h" ++ ++#if defined(CONFIG_MS_PADMUX) ++#include "mdrv_padmux.h" ++#include "padmux.h" ++#include "mdrv_puse.h" ++#include "gpio.h" ++#endif ++ ++static ssize_t group_mode_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_period_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_begin_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_end_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_round_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_enable_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_hold_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_stop_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_polarity_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_info_out(struct device *dev, struct device_attribute *attr, char *buf); ++//+++[Only4I6e] ++static ssize_t group_hold_mode1_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_duty_qe0_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count); ++static ssize_t group_round_out(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); ++static ssize_t group_round_show(struct device *dev, struct device_attribute *attr, char *buf); ++static ssize_t group_output_out(struct device *dev, struct device_attribute *attr, char *buf); ++extern irqreturn_t PWM_IRQ(int irq, void *dummy); ++extern void MDEV_PWM_AllGrpEnable(struct mstar_pwm_chip *ms_chip); ++//---[Only4I6e] ++ ++ ++DEVICE_ATTR(group_mode, 0200, NULL, group_mode_in); ++DEVICE_ATTR(group_period, 0200, NULL, group_period_in); ++DEVICE_ATTR(group_begin, 0200, NULL, group_begin_in); ++DEVICE_ATTR(group_end, 0200, NULL, group_end_in); ++DEVICE_ATTR(group_round, 0200, NULL, group_round_in); ++DEVICE_ATTR(group_enable, 0200, NULL, group_enable_in); ++DEVICE_ATTR(group_hold, 0200, NULL, group_hold_in); ++DEVICE_ATTR(group_stop, 0200, NULL, group_stop_in); ++DEVICE_ATTR(group_polarity, 0200, NULL, group_polarity_in); ++DEVICE_ATTR(group_info, 0444, group_info_out, NULL); ++//+++[Only4I6e] ++DEVICE_ATTR(group_hold_mode1, 0200, NULL, group_hold_mode1_in); ++DEVICE_ATTR(group_duty_qe0, 0200, NULL, group_duty_qe0_in); ++DEVICE_ATTR(group_round_get, 0644, group_round_show, group_round_out); ++DEVICE_ATTR(group_output, 0444, group_output_out, NULL); ++//---[Only4I6e] ++ ++static inline struct mstar_pwm_chip *to_mstar_pwm_chip(struct pwm_chip *c) ++{ ++ return container_of(c, struct mstar_pwm_chip, chip); ++} ++ ++static int mstar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ ++ MS_PWM_DBG("[PWM] %s duty_ns=%d, period_ns=%d\n", __func__, duty_ns, period_ns); ++ ++ MDEV_PWM_AllGrpEnable(ms_pwm); ++#ifdef CONFIG_PWM_NEW ++ DrvPWMSetConfig(ms_pwm, pwm->hwpwm, duty_ns, period_ns); ++#else ++ DrvPWMSetPeriod(ms_pwm, pwm->hwpwm, period_ns); ++ DrvPWMSetDuty(ms_pwm, pwm->hwpwm, duty_ns); ++ //DrvPWMPadSet(pwm->hwpwm, (U8)ms_pwm->pad_ctrl[pwm->hwpwm]); ++#endif ++ return 0; ++} ++ ++#if defined(CONFIG_MS_PADMUX) ++static int _pwm_is_pad_set(U8 u8PwmId) ++{ ++ // important: need to modify if more MDRV_PUSE_PWM? defined ++ if ((u8PwmId == 0 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM0)) || ++ (u8PwmId == 1 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM1)) || ++ (u8PwmId == 2 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM2)) || ++ (u8PwmId == 3 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM3)) || ++ (u8PwmId == 4 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM4)) || ++ (u8PwmId == 5 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM5)) || ++ (u8PwmId == 6 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM6)) || ++ (u8PwmId == 7 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM7)) || ++ (u8PwmId == 8 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM8)) || ++ (u8PwmId == 9 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_PWM9))) ++ { ++ return TRUE; ++ } ++ else ++ return FALSE; ++} ++#endif ++ ++static int mstar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ MS_PWM_DBG("[PWM] %s\n", __func__); ++ DrvPWMEnable(ms_pwm, pwm->hwpwm, 1); ++ ++ return 0; ++} ++ ++static void mstar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ MS_PWM_DBG("[PWM] %s\n", __func__); ++ DrvPWMEnable(ms_pwm, pwm->hwpwm, 0); ++} ++ ++static int mstar_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ MS_PWM_DBG("[PWM] %s %d\n", __func__, (U8)polarity); ++ DrvPWMSetPolarity(ms_pwm, pwm->hwpwm, (U8)polarity); ++ return 0; ++} ++ ++static void mstar_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ U32 u32Period = 0x00000000, u32Duty = 0x00000000; ++ U8 enable = 0x00, polarity = 0x00; ++ ++#ifdef CONFIG_PWM_NEW ++ DrvPWMGetConfig(ms_pwm, pwm->hwpwm, &u32Duty, &u32Period); ++#else ++ DrvPWMGetPeriod(ms_pwm, pwm->hwpwm, &u32Period); ++ DrvPWMGetDuty(ms_pwm, pwm->hwpwm, &u32Duty); ++#endif ++ DrvPWMEnableGet(ms_pwm, pwm->hwpwm, &enable); ++ DrvPWMGetPolarity(ms_pwm, pwm->hwpwm, &polarity); ++ state->period = u32Period; ++ state->duty_cycle = u32Duty; ++ state->polarity = polarity; ++ state->enabled = enable; ++} ++ ++static const struct pwm_ops mstar_pwm_ops = { ++ .config = mstar_pwm_config, ++ .enable = mstar_pwm_enable, ++ .disable = mstar_pwm_disable, ++ .set_polarity = mstar_pwm_set_polarity, ++ .get_state = mstar_pwm_get_state, ++ .owner = THIS_MODULE, ++}; ++ ++static int ms_pwm_probe(struct platform_device *pdev) ++{ ++ struct mstar_pwm_chip *ms_pwm; ++ struct resource *res; ++ U32 U32Pm_Addr=0; ++ int ret=0; ++ int i; ++ ++ ms_pwm = devm_kzalloc(&pdev->dev, sizeof(*ms_pwm), GFP_KERNEL); ++ if (ms_pwm == NULL) ++ { ++ dev_err(&pdev->dev, "failed to allocate memory\n"); ++ return -ENOMEM; ++ } ++ if (DrvPWMGroupCap()) ++ { ++ struct device *mstar_class_pwm_device = NULL; ++ if (!(mstar_class_pwm_device = device_create(msys_get_sysfs_class(), NULL, MKDEV(0, 0), NULL, "motor"))) ++ { ++ // printk("[%s][%d] create device file fail\n", __FUNCTION__, __LINE__); ++ return -ENOMEM; ++ } ++ // printk("[%s][%d] 0x%08x\n", __FUNCTION__, __LINE__, (int)ms_pwm); ++ ms_pwm->group_data = (void*)mstar_class_pwm_device; ++ dev_set_drvdata(mstar_class_pwm_device, (void*)ms_pwm); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_mode); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_period); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_begin); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_end); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_round); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_enable); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_hold); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_stop); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_polarity); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_info); ++ //+++[Only4I6e] ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_hold_mode1); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_duty_qe0); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_round_get); ++ device_create_file(mstar_class_pwm_device, &dev_attr_group_output); ++ //---[Only4I6e] ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "Can't get I/O resource regs for pwm\n"); ++ return 0; ++ } ++ ++ //ms_pwm->base = devm_ioremap_resource(&pdev->dev, res); ++ ms_pwm->base = (void *)res->start; ++ ++ if (IS_ERR(ms_pwm->base)) ++ return PTR_ERR(ms_pwm->base); ++#ifndef CONFIG_CAM_CLK ++ ms_pwm->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(ms_pwm->clk)) ++ return PTR_ERR(ms_pwm->clk); ++ ++ ret = clk_prepare_enable(ms_pwm->clk); ++ if (ret) ++ return ret; ++#endif ++ platform_set_drvdata(pdev, ms_pwm); ++ ++ ms_pwm->chip.dev = &pdev->dev; ++ ms_pwm->chip.ops = &mstar_pwm_ops; ++ ms_pwm->chip.base = -1; ++ if(of_property_read_u32(pdev->dev.of_node, "npwm", &ms_pwm->chip.npwm)) ++ ms_pwm->chip.npwm = 4; ++ ms_pwm->pad_ctrl = devm_kzalloc(&pdev->dev, ms_pwm->chip.npwm * sizeof(*ms_pwm->pad_ctrl), GFP_KERNEL); ++ if (ms_pwm->pad_ctrl == NULL) ++ { ++ dev_err(&pdev->dev, "failed to allocate memory\n"); ++ return -ENOMEM; ++ } ++ if(of_property_read_u32(pdev->dev.of_node, "pm_group_base", &U32Pm_Addr)) ++ { ++ ms_pwm->group_data = NULL; ++ } ++ else ++ { ++ if(U32Pm_Addr != FALSE) ++ ms_pwm->group_data = (void *)U32Pm_Addr; ++ printk("[i6e][pwm] use ms_pwm->group_data\n"); ++ } ++ ++ if((ret=of_property_read_u32_array(pdev->dev.of_node, "pad-ctrl", ms_pwm->pad_ctrl, ms_pwm->chip.npwm))) ++ dev_err(&pdev->dev, "read pad-ctrl failed\n"); ++ ++ // improve boot-up speed, remove print log ++#if 1 ++ for(i=0; ichip.npwm; i++) ++ { ++ DrvPWMInit(ms_pwm, i); ++#if defined(CONFIG_MS_PADMUX) ++ if ( 0 == mdrv_padmux_active() || ++ FALSE == _pwm_is_pad_set(i) ) ++#endif ++ { ++ DrvPWMPadSet(i, (U8)ms_pwm->pad_ctrl[i]); ++ } ++ // MS_PWM_DBG("ms_pwm->pad_ctrl[%d]=%d\n", i, ms_pwm->pad_ctrl[i]); ++ } ++#endif ++ ++ ret = pwmchip_add(&ms_pwm->chip); ++ if (ret < 0) ++ { ++#ifndef CONFIG_CAM_CLK ++ clk_disable_unprepare(ms_pwm->clk); ++ devm_clk_put(&pdev->dev, ms_pwm->clk); ++#endif ++ dev_err(&pdev->dev, "pwmchip_add failed\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < PWM_GROUP_NUM; i++) ++ { ++ DrvPWMGroupEnable(ms_pwm, i, 0); ++ } ++ ++ //+++[Only4I6e and I6b0] ++ /* Register interrupt handler */ ++ ms_pwm->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (ms_pwm->irq) { ++ ret = request_irq(ms_pwm->irq, PWM_IRQ, 0, "pwm-isr", ms_pwm); ++ if (ret) { ++ dev_err(&pdev->dev, "pwm request irq fail(x%x)\n",ret); ++ return ret; ++ } ++ printk(KERN_NOTICE "[NOTICE]pwm-isr(%d) success. If not i6e or i6b0, pls confirm it on .dtsi\n", ms_pwm->irq); ++ } ++ //---[Only4I6e] ++ ++ // improve boot-up speed, remove print log ++ //dev_info(&pdev->dev, "probe successful\n"); ++ ++ return 0; ++} ++ ++static int ms_pwm_remove(struct platform_device *pdev) ++{ ++ struct mstar_pwm_chip *ms_pwm = dev_get_drvdata(&pdev->dev); ++ int err; ++#ifndef CONFIG_CAM_CLK ++ clk_disable_unprepare(ms_pwm->clk); ++ if (!IS_ERR(ms_pwm->clk)) ++ devm_clk_put(&pdev->dev, ms_pwm->clk); ++#endif ++ err = pwmchip_remove(&ms_pwm->chip); ++ if (err < 0) ++ return err; ++/* ++ device_remove_file(hemac->mstar_class_emac_device, &dev_attr_sw_led_flick_speed); ++ if (ms_pwm->group_data) ++ device_destroy(msys_get_sysfs_class(), MKDEV(0, 0)); ++*/ ++ free_irq(ms_pwm->irq, ms_pwm); ++ devm_kfree(&pdev->dev, ms_pwm); ++ dev_info(&pdev->dev, "remove successful\n"); ++ return 0; ++} ++ ++static ssize_t group_mode_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int pwmId = 0; ++ int enable = 0; ++ ++ nArg = sscanf(buf, "%d %d", &pwmId, &enable); ++ if (2 != nArg) ++ { ++ printk("[%s][%d] invalid argument (pwm_id, enable)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ enable = (enable) ? 1 : 0; ++ DrvPWMGroupJoin(ms_pwm, pwmId, enable); ++ DrvPWMSetDben(ms_pwm, pwmId, 1); ++ DrvPWMEnable(ms_pwm, pwmId, 0); ++#if defined(CONFIG_MS_PADMUX) ++ if ( 0 == mdrv_padmux_active() || ++ FALSE == _pwm_is_pad_set(pwmId) ) ++#endif ++ { ++ DrvPWMPadSet(pwmId, (U8)ms_pwm->pad_ctrl[pwmId]); ++ } ++out: ++ return count; ++} ++ ++static ssize_t group_period_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int pwmId = 0; ++ int period = 0; ++ // printk("[%s][%d] 0x%08x\n", __FUNCTION__, __LINE__, (int)ms_pwm); ++ ++ nArg = sscanf(buf, "%d %d", &pwmId, &period); ++ if (2 != nArg) ++ { ++ printk("[%s][%d] invalid argument (pwm_id, period)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ // printk("[%s][%d] (pwm_id, period) = (%d, %d)\n", __FUNCTION__, __LINE__, pwmId, period); ++ DrvPWMSetPeriodEx(ms_pwm, pwmId, period); ++out: ++ return count; ++} ++ ++static ssize_t group_polarity_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int pwmId = 0; ++ int polarity = 0; ++ ++ nArg = sscanf(buf, "%d %d", &pwmId, &polarity); ++ if (2 != nArg) ++ { ++ printk("[%s][%d] invalid argument (pwm_id, polarity)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ polarity = (polarity) ? 1 : 0; ++ // printk("[%s][%d] (pwm_id, polarity) = (%d, %d)\n", __FUNCTION__, __LINE__, pwmId, polarity); ++ DrvPWMSetPolarityEx(ms_pwm, pwmId, polarity); ++out: ++ return count; ++} ++ ++static ssize_t group_end_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int pwmId = 0; ++ int end[5] = {0}; ++ int i; ++ ++ nArg = sscanf(buf, "%d %d %d %d %d %d", &pwmId, &end[0], &end[1], &end[2], &end[3], &end[4]); ++ // if ((2 > nArg) || (5 < nArg)) ++ if ((2 > nArg) || (2 < nArg)) // limit to on duty/shift ++ { ++ printk("[%s][%d] invalid argument (pwm_id, end[0.. 3])\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ for (i = 2; i <= nArg; i++) ++ DrvPWMSetEnd(ms_pwm, pwmId, i - 2, end[i - 2]); ++out: ++ return count; ++} ++ ++static ssize_t group_begin_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int pwmId = 0; ++ int begin[5] = {0}; ++ int i; ++ ++ nArg = sscanf(buf, "%d %d %d %d %d %d", &pwmId, &begin[0], &begin[1], &begin[2], &begin[3], &begin[4]); ++ // if ((2 > nArg) || (5 < nArg)) ++ if ((2 > nArg) || (2 < nArg)) // limit to on duty/shift ++ { ++ printk("[%s][%d] invalid argument (pwm_id, begin[0.. 3])\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ for (i = 2; i <= nArg; i++) ++ DrvPWMSetBegin(ms_pwm, pwmId, i - 2, begin[i - 2]); ++out: ++ return count; ++} ++ ++static ssize_t group_round_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int groupId = 0; ++ int round = 0; ++ ++ nArg = sscanf(buf, "%d %d", &groupId, &round); ++ if (2 != nArg) ++ { ++ printk("[%s][%d] invalid argument (pwm_id, round)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ // printk("[%s][%d] (pwm_id, round) = (%d, %d)\n", __FUNCTION__, __LINE__, groupId, round); ++ DrvPWMGroupSetRound(ms_pwm, groupId, round); ++out: ++ return count; ++} ++ ++static ssize_t group_enable_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0x00000000; ++ int groupId = 0x00000000; ++ int enable = 0x00000000; ++ U8 enable_status = 0x00; ++ ++ nArg = sscanf(buf, "%d %d", &groupId, &enable); ++ if (2 != nArg) ++ { ++ printk("[%s][%d] invalid argument (group_id, enable)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ if (!DrvPWMGroupIsEnable(ms_pwm, groupId, &enable_status)) ++ { ++ printk("[%s][%d] unable to get enable status of group %d\n", __FUNCTION__, __LINE__, groupId); ++ goto out; ++ } ++ enable = (enable) ? 1 : 0; ++ if (enable == enable_status) ++ { ++ printk("[%s][%d] cannot enable/disable group %d again. enable status = %d\n", __FUNCTION__, __LINE__, groupId, enable_status); ++ goto out; ++ } ++ ++ if (enable) ++ { ++ DrvPWMGroupStop(ms_pwm, groupId, 0); ++ DrvPWMGroupHold(ms_pwm, groupId, 0); ++ DrvPWMGroupEnable(ms_pwm, groupId, 1); ++ } ++ else ++ { ++ DrvPWMGroupEnable(ms_pwm, groupId, 0); ++ DrvPWMGroupStop(ms_pwm, groupId, 0); ++ DrvPWMGroupHold(ms_pwm, groupId, 0); ++ } ++out: ++ return count; ++} ++ ++static ssize_t group_hold_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int groupId = 0; ++ int enable = 0; ++ ++ nArg = sscanf(buf, "%d %d", &groupId, &enable); ++ if (2 != nArg) { ++ printk("[%s][%d] invalid argument (group_id, enable)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ // printk("[%s][%d] (groupId, enable) = (%d, %d)\n", __FUNCTION__, __LINE__, groupId, enable); ++ DrvPWMGroupHold(ms_pwm, groupId, enable); ++out: ++ return count; ++} ++ ++static ssize_t group_stop_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0; ++ int groupId = 0; ++ int enable = 0; ++ ++ nArg = sscanf(buf, "%d %d", &groupId, &enable); ++ if (2 != nArg) ++ //if (1 != nArg) ++ { ++ printk("[%s][%d] invalid argument (groud_id, enable?)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ // printk("[%s][%d] (pwm_id, enable) = (%d, %d)\n", __FUNCTION__, __LINE__, groupId, enable); ++ DrvPWMGroupStop(ms_pwm, groupId, enable); ++ DrvPWMGroupEnable(ms_pwm, groupId, 0); ++// DrvPWMGroupStop(ms_pwm, groupId, 1); ++out: ++ return count; ++} ++ ++static ssize_t group_info_out(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ return DrvPWMGroupInfo(ms_pwm, buf, buf + PAGE_SIZE); ++} ++ ++//+++[Only4I6e] ++static ssize_t group_hold_mode1_in(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0x00000000; ++ int enable = 0x00000000; ++ ++ nArg = sscanf(buf, "%d", &enable); ++ if (1 != nArg) { ++ printk("[%s][%d] invalid argument (enable)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ // printk("[%s][%d] enable = %d\n", __FUNCTION__, __LINE__, enable); ++ DrvPWMGroupHoldM1(ms_pwm, enable); ++out: ++ return count; ++} ++ ++static ssize_t group_duty_qe0_in(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0x00000000; ++ int groupId = 0x00000000; ++ int enable = 0x00000000; ++ ++ nArg = sscanf(buf, "%d %d", &groupId, &enable); ++ if (2 != nArg) { ++ printk("[%s][%d] invalid argument (group_id, enable)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ // printk("[%s][%d] (groupId, enable) = (%d, %d)\n", __FUNCTION__, __LINE__, groupId, enable); ++ DrvPWMDutyQE0(ms_pwm, groupId, enable); ++out: ++ return count; ++} ++ ++static ssize_t group_round_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ return DrvPWMGroupShowRoundNum(ms_pwm, buf, buf + PAGE_SIZE); ++} ++ ++static ssize_t group_round_out(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ int nArg = 0x00000000; ++ int groupId = 0x00000000; ++ short round_set = 0x0000; ++ ++ //i6b0 ++ nArg = sscanf(buf, "%d %hd", &groupId, &round_set); ++ if (2 != nArg) ++ { ++ printk("[%s][%d] invalid argument (group_id, round)\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ ++ DrvPWMGroupGetRoundNum(ms_pwm, groupId, &round_set); ++ ++out: ++ return count; ++ ++ //i6e ++ /*if (PWM_GROUP_NUM == 0) { ++ printk("[%s][%d] WARNING:PWM_GROUP_NUM = 0!\n", __FUNCTION__, __LINE__); ++ } ++ else { ++ for (groupId = 0x00; groupId < PWM_GROUP_NUM; groupId++) { ++ DrvPWMGroupGetRoundNum(ms_pwm, groupId, &round_set); ++ printk("[%s][%d] grpId:%d round:%d-%s\n", __FUNCTION__, __LINE__, groupId, round_set, (round_set)?"END":"BUSY"); ++ } ++ } ++ return 1;*/ ++} ++ ++static ssize_t group_output_out(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct mstar_pwm_chip* ms_pwm = (struct mstar_pwm_chip*)dev_get_drvdata(dev); ++ char u8Output = 0x00; ++ ++ //printk("[%s][%d] output = x%x\n", __FUNCTION__, __LINE__, u8Output); ++ DrvPWMGetOutput(ms_pwm, &u8Output); ++ return 1; ++} ++//---[Only4I6e] ++ ++#ifdef CONFIG_PM_SLEEP ++static int infinity_pwm_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct mstar_pwm_chip *pwm = platform_get_drvdata(pdev); ++ ++ pr_debug("[PWM] suspend\n"); ++ if (pwm->irq) { ++ //free_irq(pwm->irq,PWM_IRQ); ++ disable_irq(pwm->irq); ++ pr_debug("[NOTICE]Disable Pwm Irq %d\n", pwm->irq); ++ } ++ if (pwm && pwm->clk) { ++ clk_disable_unprepare(pwm->clk); ++ } ++ return 0; ++} ++ ++static int infinity_pwm_resume(struct platform_device *pdev) ++{ ++ int i = 0; ++ struct mstar_pwm_chip *pwm = platform_get_drvdata(pdev); ++ ++ pr_debug("[PWM] resume\n"); ++ if (pwm && pwm->clk) { ++ clk_prepare_enable(pwm->clk); ++ } ++ for(i=0; ichip.npwm; i++) ++ { ++ DrvPWMInit(pwm, i); ++ // MS_PWM_DBG("ms_pwm->pad_ctrl[%d]=%d\n", i, ms_pwm->pad_ctrl[i]); ++ } ++ if (pwm->irq) { ++ enable_irq(pwm->irq); ++ } ++ return 0; ++} ++#endif /* CONFIG_PM_SLEEP */ ++ ++static const struct of_device_id ms_pwm_of_match_table[] = { ++ { .compatible = "sstar,infinity-pwm" }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, ms_pwm_of_match_table); ++ ++static struct platform_driver ms_pwm_driver = { ++ .remove = ms_pwm_remove, ++ .probe = ms_pwm_probe, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = infinity_pwm_suspend, ++ .resume = infinity_pwm_resume, ++#endif ++ .driver = { ++ .name = "sstar-pwm", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_pwm_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_pwm_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MStar PWM Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/rebootstate/Kconfig b/drivers/sstar/rebootstate/Kconfig +new file mode 100755 +index 000000000000..7d7f21814184 +--- /dev/null ++++ b/drivers/sstar/rebootstate/Kconfig +@@ -0,0 +1,7 @@ ++config REBOOT_STATE ++ ++tristate "REBOOT_STATE" ++ ++help ++ SStar reboot state driver function ++ +diff --git a/drivers/sstar/rebootstate/Makefile b/drivers/sstar/rebootstate/Makefile +new file mode 100755 +index 000000000000..deb1b92e2f45 +--- /dev/null ++++ b/drivers/sstar/rebootstate/Makefile +@@ -0,0 +1,19 @@ ++# ++# Makefile for MStar rebootstate device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/rebootstate ++ ++# specific options ++EXTRA_CFLAGS += -DTITANIA ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_REBOOT_STATE) += reboot_state.o ++#export header files ++ ++ +diff --git a/drivers/sstar/rebootstate/reboot_state.c b/drivers/sstar/rebootstate/reboot_state.c +new file mode 100755 +index 000000000000..04f8c540184c +--- /dev/null ++++ b/drivers/sstar/rebootstate/reboot_state.c +@@ -0,0 +1,139 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_types.h" ++ ++#define BUFFER_LEN 0x40 ++static char reboot_type[BUFFER_LEN]; ++static char reboot_time[BUFFER_LEN]; ++static struct proc_dir_entry *proc_reboot_state_dir; ++ ++static U16 mstar_read_reg16( u32 bank, u32 reg) ++{ ++ u16 val = 0; ++ ++ u32 address = 0xfd000000 + bank*0x100*2 + (reg << 2); ++ val = *( ( volatile u16* ) address ); ++ ++ return val; ++} ++ ++static int reboot_type_open(struct inode *inode, struct file *fp) ++{ ++ memset(reboot_type, 0, BUFFER_LEN); ++ return 0; ++} ++ ++// 1: watchdog reboot ++// 2: reboot ++// 3: ac on ++static ssize_t reboot_type_read(struct file *fp, char * buf, size_t size, loff_t *ppos) ++{ ++ U16 RegVal = 0; ++ ++ if (!size || *ppos != 0) ++ return 0; ++ ++ RegVal = mstar_read_reg16(0x30,0x02); ++ if(RegVal&0x01) ++ { ++ memcpy(reboot_type,"1",1); ++ } ++ else ++ { ++ RegVal = mstar_read_reg16(0x06,0x0); ++ if(RegVal&0x01) ++ memcpy(reboot_type,"2",1); ++ else ++ memcpy(reboot_type,"3",1); ++ } ++ ++ if (copy_to_user(buf, reboot_type, 1)) ++ return -EFAULT; ++ ++ *ppos += 1; ++ ++ return 1; ++} ++ ++static int reboot_type_release(struct inode *inode, struct file *fp) ++{ ++ printk("\n"); ++ return 0; ++} ++ ++static int reboot_time_open(struct inode *inode, struct file *fp) ++{ ++ memset(reboot_time, 0, BUFFER_LEN); ++ return 0; ++} ++ ++static ssize_t reboot_time_read(struct file *fp, char * buf, size_t size, loff_t *ppos) ++{ ++ int len = 0; ++ U16 RegVal = 0; ++ struct tm tlocal; ++ ++ if (!size || *ppos != 0) ++ return 0; ++ ++ RegVal = mstar_read_reg16(0x06,0x1); ++ tlocal.tm_year = RegVal; ++ ++ RegVal = mstar_read_reg16(0x06,0x2); ++ tlocal.tm_mon = (RegVal&0xff00) >> 8; ++ tlocal.tm_mday = RegVal&0xff; ++ ++ RegVal = mstar_read_reg16(0x06,0x3); ++ tlocal.tm_hour = RegVal; ++ ++ RegVal = mstar_read_reg16(0x06,0x4); ++ tlocal.tm_min = (RegVal&0xff00) >> 8; ++ tlocal.tm_sec = RegVal&0xff; ++ ++ len = sprintf(reboot_time+len, "%ld-%d-%d %d:%d:%d", ++ tlocal.tm_year, tlocal.tm_mon, tlocal.tm_mday, tlocal.tm_hour, tlocal.tm_min, tlocal.tm_sec); ++ ++ *ppos += len; ++ ++ if (copy_to_user(buf, reboot_time, len)) ++ return -EFAULT; ++ ++ return len; ++} ++ ++static int reboot_time_release(struct inode *inode, struct file *fp) ++{ ++ printk("\n"); ++ return 0; ++} ++ ++static const struct file_operations proc_reboot_type_operations = { ++ .open = reboot_type_open, ++ .read = reboot_type_read, ++ .release = reboot_type_release, ++}; ++ ++static const struct file_operations proc_reboot_time_operations = { ++ .open = reboot_time_open, ++ .read = reboot_time_read, ++ .release = reboot_time_release, ++}; ++ ++static int __init proc_reboot_state_init(void) ++{ ++ proc_reboot_state_dir = proc_mkdir("reboot_state", NULL); ++ proc_create("type", S_IRUSR | S_IWUSR, proc_reboot_state_dir,&proc_reboot_type_operations); ++ proc_create("time", S_IRUSR | S_IWUSR, proc_reboot_state_dir,&proc_reboot_time_operations); ++ return 0; ++} ++ ++module_init(proc_reboot_state_init); ++ +diff --git a/drivers/sstar/rtc/Kconfig b/drivers/sstar/rtc/Kconfig +new file mode 100644 +index 000000000000..c3fad896e72e +--- /dev/null ++++ b/drivers/sstar/rtc/Kconfig +@@ -0,0 +1,33 @@ ++config MS_RTC ++ bool "MS_RTC" ++ default n ++ help ++ ++config RTC_INNER ++ select RTC_CLASS ++ tristate "Mstar RTC driver" ++ depends on MS_RTC ++ default n ++ help ++ ++config RTCPWC_INNER ++ select RTC_CLASS ++ tristate "Mstar RTCWC driver" ++ depends on MS_RTC ++ default y ++ help ++ ++config RTCPWC_SW_RST_OFF ++ select RTC_CLASS ++ bool "Mstar RTCPWC driver no SW-reset on Set-Base-Time" ++ depends on RTCPWC_INNER ++ default n ++ help ++ ++config RTCPWC_INNER_EHHE ++ select RTC_CLASS ++ bool "Mstar RTCPWC driver Error Handle on Hw Exception" ++ depends on MS_RTC && RTCPWC_INNER ++ default n ++ help ++ +diff --git a/drivers/sstar/rtc/Makefile b/drivers/sstar/rtc/Makefile +new file mode 100644 +index 000000000000..6bf4b192a9ff +--- /dev/null ++++ b/drivers/sstar/rtc/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/rtc/reg ++# files ++obj-$(CONFIG_RTC_INNER) += ms_rtc.o ++obj-$(CONFIG_RTCPWC_INNER) += ms_rtcpwc.o +diff --git a/drivers/sstar/rtc/ms_rtc.c b/drivers/sstar/rtc/ms_rtc.c +new file mode 100755 +index 000000000000..aba27a02d77a +--- /dev/null ++++ b/drivers/sstar/rtc/ms_rtc.c +@@ -0,0 +1,415 @@ ++/* ++* ms_rtc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "ms_msys.h" ++ ++#define RTC_DEBUG 0 ++ ++#if RTC_DEBUG ++#define RTC_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define RTC_DBG(fmt, arg...) ++#endif ++#define RTC_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#define REG_RTC_CTRL 0x00 ++ #define SOFT_RSTZ_BIT BIT0 ++ #define CNT_EN_BIT BIT1 ++ #define WRAP_EN_BIT BIT2 ++ #define LOAD_EN_BIT BIT3 ++ #define READ_EN_BIT BIT4 ++ #define INT_MASK_BIT BIT5 ++ #define INT_FORCE_BIT BIT6 ++ #define INT_CLEAR_BIT BIT7 ++ ++#define REG_RTC_FREQ_CW_L 0x04 ++#define REG_RTC_FREQ_CW_H 0x08 ++ ++#define REG_RTC_LOAD_VAL_L 0x0C ++#define REG_RTC_LOAD_VAL_H 0x10 ++ ++#define REG_RTC_MATCH_VAL_L 0x14 ++#define REG_RTC_MATCH_VAL_H 0x18 ++ ++#define REG_RTC_CNT_VAL_L 0x20 ++#define REG_RTC_CNT_VAL_H 0x24 ++ ++struct ms_rtc_info { ++ struct platform_device *pdev; ++ struct rtc_device *rtc_dev; ++ struct device* rtc_devnode; ++ void __iomem *rtc_base; ++}; ++ ++int auto_wakeup_delay_seconds = 0; ++ ++static ssize_t auto_wakeup_timer_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ auto_wakeup_delay_seconds = simple_strtoul(buf, NULL, 10); ++ //printk("\nauto_wakeup_delay_seconds=%d\n", auto_wakeup_delay_seconds); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t auto_wakeup_timer_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", auto_wakeup_delay_seconds); ++ return (str - buf); ++} ++DEVICE_ATTR(auto_wakeup_timer, 0644, auto_wakeup_timer_show, auto_wakeup_timer_store); ++ ++ ++static int ms_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ ++ seconds = readw(info->rtc_base + REG_RTC_MATCH_VAL_L) | (readw(info->rtc_base + REG_RTC_MATCH_VAL_H) << 16); ++ ++ rtc_time_to_tm(seconds, &alarm->time); ++ ++ if( !(readw(info->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT) ) ++ alarm->enabled = 1; ++ ++ RTC_DBG("ms_rtc_read_alarm[%d,%d,%d,%d,%d,%d], alarm_en=%d\n", ++ alarm->time.tm_year,alarm->time.tm_mon,alarm->time.tm_mday,alarm->time.tm_hour,alarm->time.tm_min,alarm->time.tm_sec, alarm->enabled); ++ ++ ++ return 0; ++} ++ ++static int ms_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ RTC_DBG("ms_rtc_set_alarm[%d,%d,%d,%d,%d,%d], alarm_en=%d\n", ++ alarm->time.tm_year,alarm->time.tm_mon,alarm->time.tm_mday,alarm->time.tm_hour,alarm->time.tm_min,alarm->time.tm_sec, alarm->enabled); ++ ++ rtc_tm_to_time(&alarm->time, &seconds); ++ ++ writew((seconds & 0xFFFF), info->rtc_base + REG_RTC_MATCH_VAL_L); ++ writew((seconds>>16) & 0xFFFF, info->rtc_base + REG_RTC_MATCH_VAL_H); ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ if(alarm->enabled) ++ { ++ writew(reg & ~(INT_MASK_BIT), info->rtc_base + REG_RTC_CTRL); ++ } ++ else ++ { ++ writew(reg | INT_MASK_BIT, info->rtc_base + REG_RTC_CTRL); ++ } ++ ++ return 0; ++} ++ ++static int ms_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ writew(reg | READ_EN_BIT, info->rtc_base + REG_RTC_CTRL); ++ while(readw(info->rtc_base + REG_RTC_CTRL) & READ_EN_BIT); //wait for HW latch done ++ ++ seconds = readw(info->rtc_base + REG_RTC_CNT_VAL_L) | (readw(info->rtc_base + REG_RTC_CNT_VAL_H) << 16); ++ ++ rtc_time_to_tm(seconds, tm); ++ ++ RTC_DBG("ms_rtc_read_time[%d,%d,%d,%d,%d,%d]\n", ++ tm->tm_year,tm->tm_mon,tm->tm_mday,tm->tm_hour,tm->tm_min,tm->tm_sec); ++ ++ return rtc_valid_tm(tm); ++} ++ ++static int ms_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ RTC_DBG("ms_rtc_set_time[%d,%d,%d,%d,%d,%d]\n", ++ tm->tm_year,tm->tm_mon,tm->tm_mday,tm->tm_hour,tm->tm_min,tm->tm_sec); ++ ++ rtc_tm_to_time(tm, &seconds); ++ writew(seconds & 0xFFFF, info->rtc_base + REG_RTC_LOAD_VAL_L); ++ writew((seconds >> 16) & 0xFFFF, info->rtc_base + REG_RTC_LOAD_VAL_H); ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ writew(reg | LOAD_EN_BIT, info->rtc_base + REG_RTC_CTRL); ++ /* need to check carefully if we want to clear REG_RTC_LOAD_VAL_H for customer*/ ++ while(readw(info->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT); ++ writew(0, info->rtc_base + REG_RTC_LOAD_VAL_H); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops ms_rtc_ops = { ++ .read_time = ms_rtc_read_time, ++ .set_time = ms_rtc_set_time, ++ .read_alarm = ms_rtc_read_alarm, ++ .set_alarm = ms_rtc_set_alarm, ++}; ++ ++static irqreturn_t ms_rtc_interrupt(s32 irq, void *dev_id) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev_id); ++ u16 reg; ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ reg |= INT_CLEAR_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ RTC_DBG("RTC INTERRUPT\n"); ++ ++ return IRQ_HANDLED; ++} ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++ void *pvRtcClk = NULL; ++#endif ++ ++#ifdef CONFIG_PM ++static s32 ms_rtc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ if(auto_wakeup_delay_seconds) ++ { ++ struct rtc_time tm; ++ struct rtc_wkalrm alarm; ++ unsigned long seconds; ++ ms_rtc_read_time(&pdev->dev, &tm); ++ rtc_tm_to_time(&tm, &seconds); ++ RTC_DBG("[%s]: Ready to use RTC alarm, time=%ld\n", __func__, seconds); ++ seconds += auto_wakeup_delay_seconds; ++ rtc_time_to_tm(seconds, &alarm.time); ++ alarm.enabled=1; ++ ms_rtc_set_alarm(&pdev->dev, &alarm); ++ } ++ return 0; ++} ++ ++static s32 ms_rtc_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++#endif ++ ++ ++static int ms_rtc_remove(struct platform_device *pdev) ++{ ++#ifdef CONFIG_CAM_CLK ++ if(pvRtcClk) ++ { ++ CamClkSetOnOff(pvRtcClk,0); ++ CamClkUnregister(pvRtcClk); ++ } ++#else ++ struct clk *clk = of_clk_get(pdev->dev.of_node, 0); ++ int ret = 0; ++ ++ if(IS_ERR(clk)) ++ { ++ ret = PTR_ERR(clk); ++ RTC_ERR("[%s]: of_clk_get failed\n", __func__); ++ return ret; ++ } ++ clk_disable_unprepare(clk); ++ clk_put(clk); ++#endif ++ return 0; ++} ++ ++static int ms_rtc_probe(struct platform_device *pdev) ++{ ++ struct ms_rtc_info *info; ++ struct resource *res; ++#ifdef CONFIG_CAM_CLK ++ u32 RtcClk = 0; ++ CAMCLK_Set_Attribute stSetCfg; ++#else ++ struct clk *clk; ++#endif ++ dev_t dev; ++ int ret = 0; ++ u16 reg; ++ u32 rate; ++ int rc; ++ ++ info = devm_kzalloc(&pdev->dev, sizeof(struct ms_rtc_info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ RTC_ERR("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ info->rtc_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(info->rtc_base)) ++ return PTR_ERR(info->rtc_base); ++ info->pdev = pdev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) ++ { ++ RTC_ERR("[%s]: failed to get IORESOURCE_IRQ\n", __func__); ++ return -ENODEV; ++ } ++ rc = request_irq(res->start, ms_rtc_interrupt, IRQF_SHARED, "ms_rtc", &pdev->dev); ++ if (rc) ++ { ++ RTC_ERR("[%s]: request_irq()is failed. return code=%d\n", __func__, rc); ++ } ++ platform_set_drvdata(pdev, info); ++ ++ info->rtc_dev = devm_rtc_device_register(&pdev->dev, ++ dev_name(&pdev->dev), &ms_rtc_ops, ++ THIS_MODULE); ++ ++ if (IS_ERR(info->rtc_dev)) { ++ ret = PTR_ERR(info->rtc_dev); ++ RTC_ERR("[%s]: unable to register device (err=%d).\n", __func__, ret); ++ return ret; ++ } ++ ++ //Note: is it needed? ++ //device_set_wakeup_capable(&pdev->dev, 1); ++ //device_wakeup_enable(&pdev->dev); ++ ++ //init rtc ++ RTC_DBG("[%s]: hardware initialize\n", __func__); ++ //1. release reset ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ if( !(reg & SOFT_RSTZ_BIT) ) ++ { ++ reg |= SOFT_RSTZ_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ } ++ //2. set frequency ++#ifdef CONFIG_CAM_CLK ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", 0,&(RtcClk)); ++ if (!RtcClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ if(CamClkRegister("Rtc",RtcClk,&(pvRtcClk))==CAMCLK_RET_OK) ++ { ++ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", &rate)) ++ { ++ rate = CamClkRateGet(RtcClk); ++ } ++ else ++ { ++ CAMCLK_SETRATE_ROUNDUP(stSetCfg,rate); ++ CamClkAttrSet(pvRtcClk,&stSetCfg); ++ } ++ CamClkSetOnOff(pvRtcClk,1); ++ } ++ } ++#else ++ clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(clk)) ++ { ++ ret = PTR_ERR(clk); ++ RTC_ERR("[%s]: of_clk_get failed\n", __func__); ++ return ret; ++ } ++ ++ /* Try to determine the frequency from the device tree */ ++ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", &rate)) ++ { ++ rate = clk_get_rate(clk); ++ } ++ else ++ { ++ clk_set_rate(clk, rate); ++ } ++ ++ clk_prepare_enable(clk); ++ RTC_ERR("[%s]: rtc setup, frequency=%lu\n", __func__, clk_get_rate(clk)); ++ clk_put(clk); ++#endif ++ writew(rate & 0xFFFF, info->rtc_base + REG_RTC_FREQ_CW_L); ++ writew((rate >>16) & 0xFFFF, info->rtc_base + REG_RTC_FREQ_CW_H); ++ ++ //3. enable counter ++ reg |= CNT_EN_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ ++ if (0 != (ret = alloc_chrdev_region(&dev, 0, 1, "ms_rtc"))) ++ return ret; ++ ++ info->rtc_devnode = device_create(msys_get_sysfs_class(), NULL, dev, NULL, "ms_rtc"); ++ device_create_file(info->rtc_devnode, &dev_attr_auto_wakeup_timer); ++ ++ return ret; ++} ++ ++static const struct of_device_id ms_rtc_of_match_table[] = { ++ { .compatible = "sstar,infinity-rtc" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_rtc_of_match_table); ++ ++static struct platform_driver ms_rtc_driver = { ++ .remove = ms_rtc_remove, ++ .probe = ms_rtc_probe, ++#ifdef CONFIG_PM ++ .suspend = ms_rtc_suspend, ++ .resume = ms_rtc_resume, ++#endif ++ .driver = { ++ .name = "ms_rtc", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_rtc_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_rtc_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MStar RTC Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/rtc/ms_rtcpwc.c b/drivers/sstar/rtc/ms_rtcpwc.c +new file mode 100755 +index 000000000000..8a988f68fd00 +--- /dev/null ++++ b/drivers/sstar/rtc/ms_rtcpwc.c +@@ -0,0 +1,1111 @@ ++/* ++* ms_rtcpwc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "ms_msys.h" ++#include "reg_rtcpwc.h" ++ ++#define DTS_DEFAULT_DATE "default_date" ++ ++#define RTC_DEBUG 0 ++// #define RTC_CHECK_STATUS_DELAY_TIME_MS 2 ++#define RTC_CHECK_STATUS_DELAY_TIME_US 100 ++ ++#define ISO_S0 0x00 ++#define ISO_S1 0x01 ++#define ISO_S2 0x03 ++#define ISO_S3 0x07 ++#define ISO_S4 0x05 ++#define ISO_S5 0x01 ++ ++#define RTC_PASSWORD 0xBABE ++ ++#define ISO_ACK_RETRY_TIME 20 ++ ++#if RTC_DEBUG ++#define RTC_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define RTC_DBG(fmt, arg...) ++#endif ++#define RTC_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++ ++struct ms_rtc_info { ++ struct platform_device *pdev; ++ struct rtc_device *rtc_dev; ++ void __iomem *rtc_base; ++ u32 default_base; ++ struct mutex mutex; ++}; ++static struct platform_device* g_pdev; ++static unsigned long g_alarm_time = 0; ++int auto_wakeup_delay_seconds = 0; ++//static AUTL_DATETIME m_ShadowTime = {0}; ++static char _bInit = 0; ++static char _bIsoctl_fail = 0; ++ ++void ms_rtc_set_alarm(struct device *dev, unsigned long seconds); ++void ms_rtc_alarm_init(struct device *dev); ++ ++static ssize_t isoctl_check_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "ISO EN sequence: %d\n", _bIsoctl_fail); ++ return (str - buf); ++} ++DEVICE_ATTR(isoctl_check, 0444, isoctl_check_show, NULL); ++ ++static ssize_t auto_wakeup_timer_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ auto_wakeup_delay_seconds = simple_strtoul(buf, NULL, 10); ++ //printk("\nauto_wakeup_delay_seconds=%d\n", auto_wakeup_delay_seconds); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t auto_wakeup_timer_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", auto_wakeup_delay_seconds); ++ return (str - buf); ++} ++DEVICE_ATTR(auto_wakeup_timer, 0644, auto_wakeup_timer_show, auto_wakeup_timer_store); ++ ++static ssize_t alarm_timer_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ int seconds = 0; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ seconds = simple_strtoul(buf, NULL, 10); ++ ms_rtc_alarm_init(&g_pdev->dev); ++ ms_rtc_set_alarm(&g_pdev->dev,seconds); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t alarm_timer_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ int rest = 0; ++ unsigned long run_sec=0; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct ms_rtc_info *info = dev_get_drvdata(&g_pdev->dev); ++ ++ run_sec = (readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_H) << 16) | (readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_L)); ++ rest = (g_alarm_time > run_sec)? (g_alarm_time - run_sec) : 0; ++ ++ if (rest < 0) rest = 0; ++ ++ str += scnprintf(str, end - str, "countdown time = %d\n", rest); ++ return (str - buf); ++} ++DEVICE_ATTR(alarm_timer, 0644, alarm_timer_show, alarm_timer_store); ++ ++#if 0 ++static int ms_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ ++ seconds = readw(info->rtc_base + REG_RTC_MATCH_VAL_L) | (readw(info->rtc_base + REG_RTC_MATCH_VAL_H) << 16); ++ ++ rtc_time_to_tm(seconds, &alarm->time); ++ ++ if( !(readw(info->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT) ) ++ alarm->enabled = 1; ++ ++ RTC_DBG("ms_rtc_read_alarm[%d,%d,%d,%d,%d,%d], alarm_en=%d\n", ++ alarm->time.tm_year,alarm->time.tm_mon,alarm->time.tm_mday,alarm->time.tm_hour,alarm->time.tm_min,alarm->time.tm_sec, alarm->enabled); ++ ++ ++ return 0; ++} ++ ++static int ms_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ RTC_DBG("ms_rtc_set_alarm[%d,%d,%d,%d,%d,%d], alarm_en=%d\n", ++ alarm->time.tm_year,alarm->time.tm_mon,alarm->time.tm_mday,alarm->time.tm_hour,alarm->time.tm_min,alarm->time.tm_sec, alarm->enabled); ++ ++ rtc_tm_to_time(&alarm->time, &seconds); ++ ++ writew((seconds & 0xFFFF), info->rtc_base + REG_RTC_MATCH_VAL_L); ++ writew((seconds>>16) & 0xFFFF, info->rtc_base + REG_RTC_MATCH_VAL_H); ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ if(alarm->enabled) ++ { ++ writew(reg & ~(INT_MASK_BIT), info->rtc_base + REG_RTC_CTRL); ++ } ++ else ++ { ++ writew(reg | INT_MASK_BIT, info->rtc_base + REG_RTC_CTRL); ++ } ++ ++ return 0; ++} ++#endif ++//------------------------------------------------------------------------------ ++// Function : ms_RTC_IsValid ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief The function check if current RTC is valid ++ ++The function verify the RTC status ++@return It reports the status of the operation. ++*/ ++//BOOL ms_rtc_IsValid(struct device *dev) ++//{ ++// struct ms_rtc_info *info = dev_get_drvdata(dev); ++// U16 reg; ++ ++// reg = readw(info->rtc_base + RTCPWC_RTC2DIG_VAILD); ++// printk("ms_rtc_IsValid %x\n", reg); ++// reg = reg & RTCPWC_RTC2DIG_VAILD_BIT; ++// printk("ms_rtc_IsValid %x\n", reg); ++// return (reg) ? TRUE : FALSE; ++//} ++//------------------------------------------------------------------------------ ++// Function : ms_rtc_ISOCTL ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief The internal function to send ISO_EN control signal. ++ ++The function to enable ISO cell ++@return It reports the status of the operation. ++*/ ++bool ms_rtc_ISOCTL_EX(struct device *dev) ++{ ++ U8 ubCheck = ISO_ACK_RETRY_TIME; ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ U16 reg = 0 ; ++ // Input ISO ctrl sequence , 3'b000(S0) -> 3'b001(S1) -> 3'b011(S2) -> 3'b111(S3) -> 3'b101(S4) -> 3'b001(S5) -> 3'b000(S0) ++ // Following notes is from MV2 ++ // The switch of state needs delay, 1ms at least according to designer, ++ // but in our test, set to 3ms will still causes incorrect data read. ++ // And the sequence should be finished within 1 sec. ++ ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg & ISO_S0, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg ) && (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ubCheck = ISO_ACK_RETRY_TIME; ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg | ISO_S1, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg != RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT)&& (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ++ ubCheck = ISO_ACK_RETRY_TIME; ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg | ISO_S2, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg )&& (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ubCheck = ISO_ACK_RETRY_TIME; ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg | ISO_S3, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg != RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT) && (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ubCheck = ISO_ACK_RETRY_TIME; ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg & ISO_S4, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg )&& (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ubCheck = ISO_ACK_RETRY_TIME; ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg & ISO_S5, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg != RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT )&& (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ubCheck = ISO_ACK_RETRY_TIME; ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ writew(reg & ISO_S0, info->rtc_base + RTCPWC_DIG2RTC_ISO_CTRL); ++ ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ ++ while((reg )&& (--ubCheck)) { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ reg = readw(info->rtc_base + RTCPWC_RTC2DIG_ISO_CTRL_ACK); ++ reg = reg & RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT; ++ } ++ if(ubCheck == 0) ++ return FALSE; ++ ++ ubCheck = 22; ++ do ++ { ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_RTC_TESTBUS); ++ if (reg & RTCPWC_ISO_EN) ++ { ++ break; ++ } ++ udelay(100); ++ ubCheck--; ++ } ++ while (ubCheck); ++ ++ if(ubCheck == 0) ++ return FALSE; ++ ++ // [from designer Belon.Chen] wait 2 ms is must since read/write base/counter/SW0/SW1 is valid after iso state complete ++ mdelay(2); ++ return TRUE; ++} ++ ++static int _ms_rtc_has_1k_clk(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ U8 ubCheck = 22; /// delay 22 * 100 = 2200 us ++ U16 reg = 0 ; ++ ++ do ++ { ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_RTC_TESTBUS); ++ if (reg & RTCPWC_CLK_1K) ++ { ++ return 1; ++ } ++ udelay(100); ++ ubCheck--; ++ } ++ while (ubCheck); ++ return 0; ++} ++ ++void ms_rtc_ISOCTL(struct device *dev) ++{ ++ static int warn_once = 0; ++ U8 ubCheck = ISO_ACK_RETRY_TIME; ++ ++ if (0 == _ms_rtc_has_1k_clk(dev)) ++ { ++ if (!warn_once) ++ { ++ warn_once = 1; ++ printk("[%s][%d] RTCPWC fail to enter correct state and possibly caused by no power supplied\n", __FUNCTION__, __LINE__); ++ } ++ return; ++ } ++ while (!ms_rtc_ISOCTL_EX(dev) && (--ubCheck)) ++ { ++ // mdelay(RTC_CHECK_STATUS_DELAY_TIME_MS); ++ udelay(RTC_CHECK_STATUS_DELAY_TIME_US); ++ } ++ if(ubCheck == 0) ++ _bIsoctl_fail = 1; ++} ++ ++ ++//------------------------------------------------------------------------------ ++// Function : ms_RTC_SetAlarmTime ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief This function is used for setting RTC AlarmTime. ++ ++This function is used for setting RTC AlarmTime. ++@param[out] The value of RTC AlarmTime. ++@return It reports the status of the operation. ++*/ ++static void ms_rtc_SetAlarmTime(struct device *dev, unsigned long seconds) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 reg; ++ ++ //Clear ALARM Interrupt ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg | RTCPWC_DIG2RTC_INT_CLR_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ ++ //Set Base time bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_ALARM_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ++ // Set RTC Alarm Time ++ writew(seconds, info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L); ++ writew((seconds) >> 16, info->rtc_base + RTCPWC_DIG2RTC_WRDATA_H); ++ RTC_DBG("Set RTC Alarm Time=%x\r\n", readw(info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L)); ++ RTC_DBG("Set RTC Alarm Time=%x\r\n", readw(info->rtc_base + RTCPWC_DIG2RTC_WRDATA_H)); ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ ++ //Reset control bits ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_ALARM_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++} ++ ++static unsigned long ms_rtc_GetRTCCounter(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 reg = 0; ++ u32 run_sec = 0; ++ u32 chk_times = 5; ++ u16 counterH = 0, counterL = 0; ++ ++ mutex_lock(&info->mutex); ++ ++ //Set read bit of RTC counter ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg | RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ chk_times = 5; ++ ++ //Latch RTC counter and Check valid bit of RTC counter ++ do ++ { ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD_TRIG); ++ writew(reg | RTCPWC_DIG2RTC_CNT_RD_TRIG_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD_TRIG); ++ //Note : The first to retrieve RTC counter will failed without below delay ++ mdelay(5); ++ }while((readw(info->rtc_base + RTCPWC_RTC2DIG_CNT_UPDATING) & RTCPWC_RTC2DIG_CNT_UPDATING_BIT) && (chk_times--)); ++ ++ if(chk_times == 0) ++ { ++ RTC_ERR("Check valid bit of RTC counter failed!\n"); ++ //Reset read bit of RTC counter ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ mutex_unlock(&info->mutex); ++ return 0; ++ } ++ ++ //read RTC counter ++ { ++ counterH = readw(info->rtc_base + RTCPWC_REG_RTC2DIG_RDDATA_CNT_H); ++ counterL = readw(info->rtc_base + RTCPWC_REG_RTC2DIG_RDDATA_CNT_L); ++ run_sec = counterH << 16; ++ run_sec |= counterL; ++ RTC_DBG("CounterL = 0x%x\r\n", counterL); ++ RTC_DBG("CounterH = 0x%x\r\n", counterH); ++ } ++ //Reset read bit of RTC counter ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ ++ mutex_unlock(&info->mutex); ++ return run_sec; ++} ++ ++void ms_rtc_set_alarm(struct device *dev, unsigned long seconds) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ //unsigned long alarm_time = 0; ++ u16 reg; ++ ++ //set alarm time ++ g_alarm_time = ms_rtc_GetRTCCounter(dev)+seconds; ++ ++ ms_rtc_SetAlarmTime(dev, g_alarm_time); ++ ++ //pull down io4/io5 ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_PWR_EN_CTRL); ++ writew(reg & ~RTCPWC_PWR_EN, info->rtc_base + RTCPWC_DIG2PWC_PWR_EN_CTRL); ++ ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_PWR2_EN_CTRL); ++ writew(reg & ~RTCPWC_PWR2_EN, info->rtc_base + RTCPWC_DIG2PWC_PWR2_EN_CTRL); ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ ++} ++ ++ ++void ms_rtc_alarm_init(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ int ret = 0; ++ u16 reg; ++ int val = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "rtcpwc_io4_en", &val); ++ if (ret < 0 && ret != -EINVAL) ++ { ++ RTC_DBG("[%s][%d] of_property_read_u32 (rtcpwc_io4_en) fail\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ RTC_DBG("[%s][%d] rtcpwc_io4_en= (%d)\n", __FUNCTION__, __LINE__, val); ++ ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_PWR_EN_CTRL); ++ if (!val) ++ { ++ writew(reg & ~RTCPWC_ALARM_ON_EN, info->rtc_base + RTCPWC_DIG2PWC_PWR_EN_CTRL); ++ } ++ else ++ { ++ writew(reg | RTCPWC_ALARM_ON_EN, info->rtc_base + RTCPWC_DIG2PWC_PWR_EN_CTRL); ++ } ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "rtcpwc_io5_en", &val); ++ if (ret < 0 && ret != -EINVAL) ++ { ++ RTC_DBG("[%s][%d] of_property_read_u32 fail (rtcpwc_io5_en)\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ RTC_DBG("[%s][%d] rtcpwc_io5_en (%d)\n", __FUNCTION__, __LINE__, val); ++ ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_PWR2_EN_CTRL); ++ if (!val) ++ { ++ writew(reg & ~RTCPWC_ALARM2_ON_EN, info->rtc_base + RTCPWC_DIG2PWC_PWR2_EN_CTRL); ++ } ++ else ++ { ++ writew(reg | RTCPWC_ALARM2_ON_EN, info->rtc_base + RTCPWC_DIG2PWC_PWR2_EN_CTRL); ++ } ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "rtcpwc_alarm_en", &val); ++ if (ret < 0 && ret != -EINVAL) ++ { ++ RTC_DBG("[%s][%d] of_property_read_u32 fail (rtcpwc_alarm_en)\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ RTC_DBG("[%s][%d] rtcpwc_alarm_en (%d)\n", __FUNCTION__, __LINE__, val); ++ ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ if (!val) ++ { ++ writew(reg & ~RTCPWC_DIG2RTC_ALARM_EN_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ } ++ else ++ { ++ writew(reg | RTCPWC_DIG2RTC_ALARM_EN_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ } ++ } ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++} ++ ++//------------------------------------------------------------------------------ ++// Function : ms_RTC_GetSW0 ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief This function is used for getting RTC SW0. ++ ++This function is used for getting RTC SW0. ++@param[out] The value of RTC SW0(magic number). ++@return It reports the status of the operation. ++*/ ++// SW0 has only 16 bits ++u32 ms_rtc_GetSW0(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 BaseH = 0, BaseL = 0; ++ u32 ulBaseTime = 0; ++ u16 reg = 0; ++ // I. read SW0 ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew( reg | RTCPWC_DIG2RTC_SW0_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ms_rtc_ISOCTL(dev); ++ // read base time ++ BaseH = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_H); ++ BaseL = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_L); ++ RTC_DBG("SW0 BaseH %x \n", BaseH); ++ RTC_DBG("SW0 BaseL %x \n", BaseL); ++ ulBaseTime = BaseH << 16; ++ ulBaseTime |= BaseL; ++ //reset read bit of base time ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_SW0_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ return ulBaseTime; ++} ++ ++// SW0 has only 16 bits ++void ms_rtc_SetSW0(struct device *dev, u32 val) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 reg = 0; ++ //Set sw bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_SW0_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ // Set sw password ++ writew(((val>> 0) & 0xFFFF), info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L); ++ RTC_DBG("Set RTC SetSW0=%x\r\n", readw(info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L)); ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ //reset control bits ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_SW0_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++} ++ ++#ifdef CONFIG_RTCPWC_INNER_EHHE ++// SW1 has only 16 bits ++u32 ms_rtc_GetSW1(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 BaseH = 0, BaseL = 0; ++ u32 ulBaseTime = 0; ++ u16 reg = 0; ++ // I. read SW1 ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew( reg | RTCPWC_DIG2RTC_SW1_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ms_rtc_ISOCTL(dev); ++ // read base time ++ BaseH = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_H); ++ BaseL = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_L); ++ ulBaseTime = BaseH << 16; ++ ulBaseTime |= BaseL; ++ //reset read bit of base time ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_SW1_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ return ulBaseTime; ++} ++ ++// SW1 has only 16 bits ++void ms_rtc_SetSW1(struct device *dev, u32 val) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 reg = 0; ++ //Set sw bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_SW1_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ // Set sw password ++ writew(((val>> 0) & 0xFFFF), info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L); ++ RTC_DBG("Set RTC SetSW1=%x\r\n", readw(info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L)); ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ //reset control bits ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_SW1_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++} ++#endif ++ ++//------------------------------------------------------------------------------ ++// Function : ms_RTC_SetBaseTime ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief This function is used for getting RTC BaseTime. ++ ++This function is used for getting RTC BaseTime. ++@param[out] The value of RTC BaseTime. ++@return It reports the status of the operation. ++*/ ++void ms_rtc_SetBaseTime(struct device *dev, unsigned long seconds) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 reg; ++ ++ // Toggle reset ++ reg = readw(info->rtc_base + RTCPWC_DIG2PWC_OPT); ++#ifndef CONFIG_RTCPWC_SW_RST_OFF ++ RTC_DBG("%s: RTC SW reset\r\n", __FUNCTION__); ++ writew(reg | RTCPWC_SW_RST, info->rtc_base + RTCPWC_DIG2PWC_OPT); ++ mdelay(1); ++#endif ++ writew(reg, info->rtc_base + RTCPWC_DIG2PWC_OPT); ++ ++ //Set Base time bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_BASE_WR_BIT, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ++ // Set RTC Base Time ++ writew(seconds, info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L); ++ writew((seconds) >> 16, info->rtc_base + RTCPWC_DIG2RTC_WRDATA_H); ++ RTC_DBG("Set RTC Base Time=%x\r\n", readw(info->rtc_base + RTCPWC_DIG2RTC_WRDATA_L)); ++ RTC_DBG("Set RTC Base Time=%x\r\n", readw(info->rtc_base + RTCPWC_DIG2RTC_WRDATA_H)); ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ ++ //Set counter RST bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_CNT_RST_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RST_WR, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ++ //reset control bits ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_SET); ++ writew(reg & ~RTCPWC_DIG2RTC_SET_BIT, info->rtc_base + RTCPWC_DIG2RTC_SET); ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_BASE_WR_BIT, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++} ++ ++#ifdef CONFIG_RTCPWC_INNER_EHHE ++u32 _ms_rtc_GetBaseTime(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 BaseH = 0, BaseL = 0; ++ u32 ulBaseTime = 0; ++ u16 reg; ++ ++ //reset read bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ ++ // Set read bit of base time ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_BASE_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ms_rtc_ISOCTL(dev); ++ // read base time ++ BaseH = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_H); ++ BaseL = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_L); ++ RTC_DBG("BaseH %x \n", BaseH); ++ RTC_DBG("BaseL %x \n", BaseL); ++ ulBaseTime = BaseH << 16; ++ ulBaseTime |= BaseL; ++ //reset read bit of base time ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_BASE_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ++ return ulBaseTime; ++} ++#endif ++ ++//------------------------------------------------------------------------------ ++// Function : ms_RTC_GetBaseTime ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief This function is used for getting RTC BaseTime. ++ ++This function is used for getting RTC BaseTime. ++@param[out] The value of RTC BaseTime. ++@return It reports the status of the operation. ++*/ ++u32 ms_rtc_GetBaseTime(struct device *dev) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u32 ulBaseTime = 0; ++ u32 password = 0; ++ password = ms_rtc_GetSW0(dev); ++ ++#ifdef CONFIG_RTCPWC_INNER_EHHE ++ if ((password == RTC_PASSWORD) && ++ ((ms_rtc_GetSW1(dev) & 0xFFFF) == ((ulBaseTime = _ms_rtc_GetBaseTime(dev)) & 0xFFFF))) ++#else ++ if(password == RTC_PASSWORD) ++#endif ++ { ++#ifndef CONFIG_RTCPWC_INNER_EHHE ++ u16 reg; ++ u16 BaseH = 0, BaseL = 0; ++ ++ //reset read bit ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ ++ // Set read bit of base time ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg | RTCPWC_DIG2RTC_BASE_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ ms_rtc_ISOCTL(dev); ++ // read base time ++ BaseH = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_H); ++ BaseL = readw(info->rtc_base + RTCPWC_RTC2DIG_RDDATA_L); ++ RTC_DBG("BaseH %x \n", BaseH); ++ RTC_DBG("BaseL %x \n", BaseL); ++ ulBaseTime = BaseH << 16; ++ ulBaseTime |= BaseL; ++ //reset read bit of base time ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++ writew(reg & ~RTCPWC_DIG2RTC_BASE_RD, info->rtc_base + RTCPWC_DIG2RTC_BASE_WR); ++#endif ++ } ++ else ++ { ++ RTC_ERR("Please set rtc timer (hwclock -w) \n"); ++ ms_rtc_SetBaseTime(dev, info->default_base); ++ ms_rtc_SetSW0(dev, RTC_PASSWORD); ++ ulBaseTime = info->default_base; ++#ifdef CONFIG_RTCPWC_INNER_EHHE ++ ms_rtc_SetSW1(dev, info->default_base); ++#endif // #ifdef CONFIG_RTCPWC_INNER_EHHE ++ } ++ return ulBaseTime; ++} ++ ++//------------------------------------------------------------------------------ ++// Function : ms_rtc_read_time ++// Description : ++//------------------------------------------------------------------------------ ++/** @brief This function is used for getting RTC information. ++ ++This function is used for getting RTC time information. ++@warning This function uses OS sleep, please don't call this function in ISR. ++@param[in] pointer of structure AUTL_DATETIME. ++@return It reports the status of the operation. ++*/ ++static int ms_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ u16 reg = 0; ++ u32 run_sec = 0; ++ u32 chk_times = 5; ++ u64 ullSeconds = 0; ++ u16 counterH = 0, counterL = 0; ++ int m_ulBaseTimeInSeconds = 0; ++ ++ if (0 == _bInit) ++ return 0; ++ ++ mutex_lock(&info->mutex); ++ ++ m_ulBaseTimeInSeconds = ms_rtc_GetBaseTime(dev); ++ ++ RTC_DBG("m_ulBaseTimeInSeconds= 0x%x\r\n", m_ulBaseTimeInSeconds); ++ ++ if(RTC_PASSWORD == ms_rtc_GetSW0(dev)) ++ { ++ // Read RTC Counter ++ do ++ { ++ //Set read bit of RTC counter ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg | RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ ++ //Trigger ISO ++ ms_rtc_ISOCTL(dev); ++ chk_times = 5; ++ ++ //Latch RTC counter and Check valid bit of RTC counter ++ do ++ { ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD_TRIG); ++ writew(reg | RTCPWC_DIG2RTC_CNT_RD_TRIG_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD_TRIG); ++ //Note : The first to retrieve RTC counter will failed without below delay ++ mdelay(5); ++ }while((readw(info->rtc_base + RTCPWC_RTC2DIG_CNT_UPDATING) & RTCPWC_RTC2DIG_CNT_UPDATING_BIT) && (chk_times--)); ++ ++ if(chk_times == 0) ++ { ++ RTC_ERR("Check valid bit of RTC counter failed!\n"); ++ //Reset read bit of RTC counter ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ mutex_unlock(&info->mutex); ++ return 0; ++ } ++ ++ //read RTC counter ++ { ++ counterH = readw(info->rtc_base + RTCPWC_REG_RTC2DIG_RDDATA_CNT_H); ++ counterL = readw(info->rtc_base + RTCPWC_REG_RTC2DIG_RDDATA_CNT_L); ++ run_sec = counterH << 16; ++ run_sec |= counterL; ++ RTC_DBG("CounterL = 0x%x\r\n", counterL); ++ RTC_DBG("CounterH = 0x%x\r\n", counterH); ++ } ++ //Reset read bit of RTC counter ++ reg = readw(info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ writew(reg & ~RTCPWC_DIG2RTC_CNT_RD_BIT, info->rtc_base + RTCPWC_DIG2RTC_CNT_RD); ++ } while(0); ++ } ++ RTC_DBG("run_sec = 0x%x\r\n", run_sec); ++ RTC_DBG("m_ulBaseTimeInSeconds = 0x%x\r\n", m_ulBaseTimeInSeconds); ++ ullSeconds = m_ulBaseTimeInSeconds + run_sec; ++ ++ //_RTC_PRINT("Base = 0x%x, counter = 0x%x, ullSeconds = 0x%x\n",m_ulBaseTimeInSeconds,run_sec,ullSeconds); ++ ++ if (ullSeconds > 0xFFFFFFFF) { ++ ullSeconds = 0xFFFFFFFF; ++ } ++ ++ rtc_time_to_tm(ullSeconds, tm); ++ ++ RTC_DBG("ms_rtc_read_time[%d,%d,%d,%d,%d,%d]\n", ++ tm->tm_year,tm->tm_mon,tm->tm_mday,tm->tm_hour,tm->tm_min,tm->tm_sec); ++ ++ mutex_unlock(&info->mutex); ++ return rtc_valid_tm(tm); ++} ++ ++static int ms_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ ++ if (0 == _bInit) ++ return 0; ++ ++ mutex_lock(&info->mutex); ++ RTC_DBG("ms_rtc_set_time[%d,%d,%d,%d,%d,%d]\n", ++ tm->tm_year,tm->tm_mon,tm->tm_mday,tm->tm_hour,tm->tm_min,tm->tm_sec); ++ ++ rtc_tm_to_time(tm, &seconds); ++ RTC_DBG("RTC Set Time: Base=%ld\r\n", seconds); ++ ms_rtc_SetBaseTime(dev, seconds); ++ ms_rtc_SetSW0(dev, RTC_PASSWORD); ++#ifdef CONFIG_RTCPWC_INNER_EHHE ++ ms_rtc_SetSW1(dev, seconds); ++#endif // #ifdef CONFIG_RTCPWC_INNER_EHHE ++ mutex_unlock(&info->mutex); ++ return 0; ++} ++ ++static const struct rtc_class_ops ms_rtcpwc_ops = { ++ .read_time = ms_rtc_read_time, ++ .set_time = ms_rtc_set_time, ++ /*.read_alarm = ms_rtc_read_alarm, ++ .set_alarm = ms_rtc_set_alarm,*/ ++}; ++#if 0 ++static irqreturn_t ms_rtc_interrupt(s32 irq, void *dev_id) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev_id); ++ u16 reg; ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ reg |= INT_CLEAR_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ RTC_DBG("RTC INTERRUPT\n"); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++#ifdef CONFIG_PM_SLEEP ++static s32 ms_rtcpwc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static s32 ms_rtcpwc_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++#endif ++ ++static int ms_rtcpwc_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ ++ if (info) { ++ devm_kfree(dev, info); ++ } ++ return 0; ++} ++ ++static int ms_rtcpwc_probe(struct platform_device *pdev) ++{ ++ struct ms_rtc_info *info; ++ struct resource *res; ++ struct device* rtc_dev; ++ dev_t dev; ++ int ret = 0; ++// u16 reg; ++// u32 rate; ++// int rc; ++ ++ info = devm_kzalloc(&pdev->dev, sizeof(struct ms_rtc_info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ RTC_DBG("RTC initial\n"); ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ RTC_ERR("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ info->rtc_base = devm_ioremap_resource(&pdev->dev, res); ++ ++ if (IS_ERR(info->rtc_base)) ++ return PTR_ERR(info->rtc_base); ++ ++ info->pdev = pdev; ++ ++/* ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ ++ if (!res) ++ { ++ RTC_ERR("[%s]: failed to get IORESOURCE_IRQ\n", __func__); ++ return -ENODEV; ++ } ++ ++ rc = request_irq(res->start, ms_rtc_interrupt, IRQF_SHARED, "ms_rtc", &pdev->dev); ++ ++ if (rc) ++ { ++ RTC_ERR("[%s]: request_irq()is failed. return code=%d\n", __func__, rc); ++ } ++*/ ++ platform_set_drvdata(pdev, info); ++ g_pdev = pdev; ++ ++ info->rtc_dev = devm_rtc_device_register(&pdev->dev, ++ dev_name(&pdev->dev), &ms_rtcpwc_ops, ++ THIS_MODULE); ++ ++ if (IS_ERR(info->rtc_dev)) { ++ ret = PTR_ERR(info->rtc_dev); ++ RTC_ERR("[%s]: unable to register device (err=%d).\n", __func__, ret); ++ return ret; ++ } ++ ++ //Note: is it needed? ++ //device_set_wakeup_capable(&pdev->dev, 1); ++ //device_wakeup_enable(&pdev->dev); ++ ++ //init rtc ++ RTC_DBG("[%s]: hardware initialize\n", __func__); ++ ++ if (0 != (ret = alloc_chrdev_region(&dev, 0, 1, "ms_rtcwc"))) ++ return ret; ++ ++ rtc_dev = device_create(msys_get_sysfs_class(), NULL, dev, NULL, "ms_rtcwc"); ++ ++ device_create_file(rtc_dev, &dev_attr_auto_wakeup_timer); ++ device_create_file(rtc_dev, &dev_attr_alarm_timer); ++ device_create_file(rtc_dev, &dev_attr_isoctl_check); ++ { ++ int num = 0; ++ struct rtc_time tm = { 0 }; ++ ++ info->default_base = 0; // 1970/1/1 00:00:00 ++ if (0 < (num = of_property_count_elems_of_size(pdev->dev.of_node, DTS_DEFAULT_DATE, sizeof(int)))) ++ { ++ if (!of_property_read_u32_array(pdev->dev.of_node, DTS_DEFAULT_DATE, (u32*)&tm, num)) ++ { ++ rtc_tm_to_time(&tm, (unsigned long*)&info->default_base); ++ } ++ } ++ } ++ _bInit = 1; ++ mutex_init(&info->mutex); ++ ++ return ret; ++} ++ ++static const struct of_device_id ms_rtcpwc_of_match_table[] = { ++ { .compatible = "sstar,infinity-rtcpwc" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_rtcpwc_of_match_table); ++ ++static struct platform_driver ms_rtcpwc_driver = { ++ .remove = ms_rtcpwc_remove, ++ .probe = ms_rtcpwc_probe, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = ms_rtcpwc_suspend, ++ .resume = ms_rtcpwc_resume, ++#endif ++ .driver = { ++ .name = "ms_rtcpwc", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_rtcpwc_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_rtcpwc_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("MStar RTC Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/rtc/reg/reg_rtcpwc.h b/drivers/sstar/rtc/reg/reg_rtcpwc.h +new file mode 100755 +index 000000000000..3992950ef4ce +--- /dev/null ++++ b/drivers/sstar/rtc/reg/reg_rtcpwc.h +@@ -0,0 +1,84 @@ ++/* ++* reg_rtcpwc.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* ++ * kernel_rtcpwc.h ++ * ++ * Created on: 2017/8/29 ++ * Author: titan.huang ++ */ ++ ++#ifndef __KERNEL_RTC_PWC_H__ ++#define __KERNEL_RTC_PWC_H__ ++ ++ ++#define RTCPWC_DIG2RTC_BASE_WR (0x00 << 2) ++ #define RTCPWC_DIG2RTC_BASE_WR_BIT BIT1 ++ #define RTCPWC_DIG2RTC_BASE_RD BIT2 ++ #define RTCPWC_DIG2RTC_CNT_RST_WR BIT3 ++ #define RTCPWC_DIG2RTC_ALARM_WR BIT4 ++ #define RTCPWC_DIG2RTC_SW0_WR BIT5 ++ #define RTCPWC_DIG2RTC_SW1_WR BIT6 ++ #define RTCPWC_DIG2RTC_SW0_RD BIT7 ++ #define RTCPWC_DIG2RTC_SW1_RD BIT8 ++//#define RTCPWC_DIG2RTC_CNT_RST_WR (0x00 << 2) ++// #define RTCPWC_DIG2RTC_CNT_RST_WR_BIT BIT3 ++#define RTCPWC_DIG2RTC_CNT_RD (0x04) //(0x01 << 2) ++ #define RTCPWC_DIG2RTC_CNT_RD_BIT BIT0 ++ #define RTCPWC_DIG2RTC_ALARM_RD_BIT BIT1 ++ #define RTCPWC_DIG2RTC_ALARM_EN_BIT BIT2 ++ #define RTCPWC_DIG2RTC_INT_CLR_BIT BIT3 ++ ++#define RTCPWC_DIG2RTC_ISO_CTRL (0x0C) //(0x03 << 2) ++ #define RTCPWC_DIG2RTC_BASE_WR_MASK BIT0|BIT1|BIT2 ++#define RTCPWC_DIG2RTC_WRDATA_L (0x10) //(0x04 << 2) ++#define RTCPWC_DIG2RTC_WRDATA_H (0x14) //(0x05 << 2) ++ ++#define RTCPWC_DIG2RTC_SET (0x18) //(0x06 << 2) ++ #define RTCPWC_DIG2RTC_SET_BIT BIT0 ++#define RTCPWC_RTC2DIG_VAILD (0x1C) //(0x07 << 2) ++ #define RTCPWC_RTC2DIG_VAILD_BIT BIT0 ++#define RTCPWC_RTC2DIG_ISO_CTRL_ACK (0x20) //(0x08 << 2) ++ #define RTCPWC_RTC2DIG_ISO_CTRL_ACK_BIT BIT3 ++ ++#define RTCPWC_RTC2DIG_RDDATA_L (0x24) //(0x09 << 2) ++#define RTCPWC_RTC2DIG_RDDATA_H (0x28) //(0x0A<< 2) ++ ++#define RTCPWC_RTC2DIG_CNT_UPDATING (0x2C) //(0x0B << 2) ++ #define RTCPWC_RTC2DIG_CNT_UPDATING_BIT BIT0 ++#define RTCPWC_REG_RTC2DIG_RDDATA_CNT_L (0x30) //(0x0C << 2) ++#define RTCPWC_REG_RTC2DIG_RDDATA_CNT_H (0x34) //(0x0D << 2) ++ ++#define RTCPWC_DIG2RTC_CNT_RD_TRIG (0x38) //(0x0E << 2) ++ #define RTCPWC_DIG2RTC_CNT_RD_TRIG_BIT BIT0 ++ ++#define RTCPWC_DIG2PWC_OPT (0x40) //(0x10 << 2) ++ #define RTCPWC_SW_RST BIT8 ++ ++#define RTCPWC_DIG2PWC_RTC_TESTBUS (0x54) //(0x15 << 2) ++ #define RTCPWC_ISO_EN BIT0 ++ #define RTCPWC_CLK_1K BIT5 ++ ++#define RTCPWC_DIG2PWC_PWR_EN_CTRL (0x3C) //(0xF << 2) ++ #define RTCPWC_PWR_EN BIT0 ++ #define RTCPWC_ALARM_ON_EN BIT1 ++#define RTCPWC_DIG2PWC_PWR2_EN_CTRL (0x80) //(0x20 << 2) ++ #define RTCPWC_PWR2_EN BIT0 ++ #define RTCPWC_ALARM2_ON_EN BIT1 ++ ++#endif /* __KERNEL_RTC_PWC_H__ */ ++ +diff --git a/drivers/sstar/samples/README b/drivers/sstar/samples/README +new file mode 100755 +index 000000000000..6d365be8f7c9 +--- /dev/null ++++ b/drivers/sstar/samples/README +@@ -0,0 +1,24 @@ ++Compile these small test program then execute them on target ++EX: arm-linux-gnueabihf-gcc -DPLATFORM_NAME=INFINITY -static -o regio.bin regio.c ++ ++Basically one C file should generate one test application ++ ++Use the "PLATFORM_NAME" define to check chip difference(CEDRIC, CHICAGO, INFINITY) ++Use "uname()" C API in code to check kernel version ++Application may need to be recompiled for different PLATFORM_NAME ++Application "SHOULD NOT" need to be recompiled for different kernel version ++ ++Check the unametest.c, the output is as following: ++ ++system name = Linux ++node name = (none) ++release = 3.18.14 ++version = #421 SMP PREEMPT Thu Jun 11 07:05:52 CST 2015 ++machine = armv7l ++ ++ ++ajtc.c network socket test client, packet generator ++ajts.c network socket test server, packet receiver ++us_ticks.c check the wrapping of IOCTL_MSYS_GET_US_TICKS ++regio.c userspace register w/r sample ++dmem.c userspace DMEM allocation & w/r sample +\ No newline at end of file +diff --git a/drivers/sstar/samples/ajtc.c b/drivers/sstar/samples/ajtc.c +new file mode 100755 +index 000000000000..34fe119b8d1d +--- /dev/null ++++ b/drivers/sstar/samples/ajtc.c +@@ -0,0 +1,206 @@ ++/* ++* ajtc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++unsigned int checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++int d=0; ++int generate_aj_packet(char **buf,int dataLen, int packetid ) ++{ ++ char *pkt=malloc(dataLen+8); ++ int ckm=0; ++ int i=0; ++ if(pkt==NULL) ++ { ++ printf("malloc aj_packet failed!!\n"); ++ return -1; ++ } ++ pkt[0]=(char)0x51; ++ pkt[1]=(char)0x58; ++ pkt[2]=(char)0x91; ++ pkt[3]=(char)0x58; ++ pkt[4]=(char)(dataLen&0xFF); ++ pkt[5]=(char)((dataLen>>8)&0xFF); ++ pkt[6]=(char)((dataLen>>16)&0xFF); ++ pkt[7]=(char)((dataLen>>24)&0xFF); ++ d=0; ++// System.out.println("dataLen="+dataLen+", "+String.format("0x%02X,0x%02X,0x%02X,0x%02X",pkt[4],pkt[5],pkt[6],pkt[7])); ++ pkt[8]=(char)(packetid&0xFF); ++ pkt[9]=(char)((packetid>>8)&0xFF); ++ pkt[10]=(char)((packetid>>16)&0xFF); ++ pkt[11]=(char)((packetid>>24)&0xFF); ++ ++ pkt[12]=(char)('A'); ++ pkt[13]=(char)('J'); ++ pkt[14]=(char)('S'); ++ pkt[15]=(char)('X'); ++ ++ pkt[16]=(char)('X'); ++ pkt[17]=(char)('S'); ++ pkt[18]=(char)('J'); ++ pkt[19]=(char)('A'); ++ ++ pkt[20]=(char)(0); ++ pkt[21]=(char)(0); ++ pkt[22]=(char)(0); ++ pkt[23]=(char)(0); ++ ++ ++ for(i=16;i>8)&0xFF);; ++ pkt[dataLen+6]=(char)((ckm>>16)&0xFF);; ++ pkt[dataLen+7]=(char)((ckm>>24)&0xFF);; ++ //System.out.println("dataLen="+dataLen+", "+String.format("0x%02X,0x%02X,0x%02X,0x%02X, 0x%08X, 0x%02X,0x%02X,0x%02X,0x%02X",pkt[4],pkt[5],pkt[6],pkt[7],ckm,pkt[dataLen+4],pkt[dataLen+5],pkt[dataLen+6],pkt[dataLen+7])); ++ //System.out.println("pktid="+packetid+", checksum=0x"+Integer.toHexString(ckm).toUpperCase()); ++ *buf=pkt; ++ return (dataLen+8); ++} ++ ++int pktcount; ++int main(int argc , char **argv) ++{ ++ ++ int sock; ++ const char* default_ip="10.10.10.107"; ++ int port=3333; ++ int count=100000; ++ int loop=0; ++ int option=0; ++ int packet_size_fixed=0; ++ char server_ip[128]; ++ struct sockaddr_in server; ++ srand( (unsigned)time(NULL) ); ++ ++ ++ ++ ++ printf("[AJ Test Client(packet sender)]\n"); ++ ++ memset(server_ip,0,sizeof(server_ip)); ++ memcpy(server_ip,default_ip,strlen(default_ip)); ++ ++ ++ while ((option = getopt(argc, argv,"p:s:c:f")) != -1) { ++ switch (option) { ++ case 's' : //server ip ++ { ++ memset(server_ip,0,sizeof(server_ip)); ++ memcpy(server_ip,optarg,strlen(optarg)); ++ } ++ break; ++ case 'p' : port = atoi(optarg); //port ++ break; ++ case 'c' : count = atoi(optarg); // test packet count ++ break; ++ ++ case 'f' : packet_size_fixed=1; ++ break; ++ ++ ++ default: printf("invalide args\n"); ++ exit(EXIT_FAILURE); ++ } ++ } ++ ++ if(0==count)loop=1; ++ ++ //Create socket ++ sock = socket(AF_INET , SOCK_STREAM , 0); ++ if (sock == -1) ++ { ++ printf("Could not create socket"); ++ } ++ ++ bzero(&server,sizeof(server)); ++ server.sin_addr.s_addr = inet_addr(server_ip); ++ server.sin_family = AF_INET; ++ server.sin_port = htons( port ); ++ ++ //Connect to remote server ++ if (connect(sock , (struct sockaddr *)&server , sizeof(server)) < 0) ++ { ++ perror("connect failed. Error"); ++ return 1; ++ } ++ ++ printf("Connected\n"); ++ ++ //keep communicating with server ++ while((count>0) || loop) ++ { ++ char *abuf[1]={0}; ++ int packet_size=1024; ++ int alen=0; ++ if(!packet_size_fixed) ++ { ++ packet_size= 64+(int)(((double)(rand()) / (RAND_MAX + 1.0))*128*1024); ++ } ++ ++ if((alen=generate_aj_packet(abuf, packet_size, pktcount))<=0) ++ { ++ printf("generate_aj_packet error!!\n"); ++ goto DONE; ++ } ++ send(sock,*abuf,alen,0); ++ free(*abuf); ++ if(!loop)count--; ++ pktcount++; ++ if((pktcount%1000)==0)printf("%d ajtest packet sent...\n",pktcount); ++ ++ } ++DONE: ++ close(sock); ++ return 0; ++} +diff --git a/drivers/sstar/samples/ajts.c b/drivers/sstar/samples/ajts.c +new file mode 100755 +index 000000000000..ed0cb082e52f +--- /dev/null ++++ b/drivers/sstar/samples/ajts.c +@@ -0,0 +1,293 @@ ++/* ++* ajts.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++#include ++#include ++#include ++#define __ERR printf ++volatile sig_atomic_t flag = 0; ++int outfd; ++char* fName=NULL; ++void finish_function(int sig){ // can be called asynchronously ++ flag = 1; // set flag ++ if(NULL!=fName) ++ { ++ free(fName); ++ } ++ close(outfd); ++ exit(-3); ++} ++ ++//using namespace std; ++int recv_with_header(int fd, char **buf) ++{ ++ unsigned char flag[4]; ++ int ret=recv(fd,flag,4,0); ++ int len; ++ int offset=0; ++ if(ret<=0) ++ { ++ ++ if(errno==0) ++ { ++ return 0; ++ } ++ __ERR("recv flag error, err=%s, %d\n",strerror(errno),errno); ++ return -3; ++ } ++ ++ if(flag[0]!=0x51 || flag[1]!=0x58 || flag[2]!=0x91 || flag[3]!=0x58) ++ { ++ __ERR("recv bad flag: 0x%02x 0x%02x 0x%02x 0x%02x\n",flag[0],flag[1],flag[2],flag[3]); ++ return -4; ++ } ++ ++ ++ ret=recv(fd,flag,4,0); ++ if(ret<=0) ++ { ++ __ERR("recv len error, err=%s\n",strerror(errno)); ++ return -5; ++ } ++ ++ len=(flag[3]<<24) + (flag[2]<<16)+(flag[1]<<8) + (flag[0]); ++ if(len<=0) ++ { ++ __ERR("recv bad len: %d, 0x%02x 0x%02x 0x%02x 0x%02x\n",len, flag[0],flag[1],flag[2],flag[3]); ++ return -6; ++ } ++// printf(" len=0x%08X\n",len); ++ ++ if(len>=(15*1024*1024)) ++ { ++ __ERR("recv bad len: %d\n",len); ++ return -7; ++ } ++ ++ ++ *buf=(char *)malloc(len + 2); ++ if(*buf==NULL) ++ { ++ __ERR("new buf failed.\n"); ++ return -8; ++ } ++// printf(" malloc success, 0x%08X 0x%08X!!\n",*buf, tbuf); ++ memset( *buf, 0, len+2); ++// printf(" memset success!!\n"); ++ ++ while(len) ++ { ++ ret=recv(fd, *buf + offset,len,0); ++// printf(" ret=%d\n",ret); ++ if(ret<=0) ++ { ++ __ERR("recv data error, err=%s\n",strerror(errno)); ++ return -9; ++ } ++ else ++ { ++ offset+=ret; ++ len-=ret; ++ } ++ } ++// printf(" recv: %d bytes success\n",offset); ++ return offset; ++} ++ ++unsigned int checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++ ++int main(int argc, char** argv) ++{ ++ int option = 0; ++ int port =3333; ++ ++ char *tbuf[1]={0}; ++ int sockfd; ++ struct sockaddr_in dest; ++ ++ printf("[AJ Test Server]\n"); ++ ++ ++ //The two options l and b expect numbers as argument ++ while ((option = getopt(argc, argv,"p:f:")) != -1) { ++ switch (option) { ++ case 'f' : ++ { ++ int len=strlen(optarg)+1; ++ fName=(char *)malloc(strlen(optarg)+1); ++ if(NULL==fName) ++ { ++ printf("failed to allocate memory, exit -1!!\n"); ++ exit(-1); ++ } ++ memset(fName,0,len); ++ memcpy(fName,optarg,(len-1)); ++ ++ } ++ break; ++ case 'p' : port = atoi(optarg); ++ break; ++ ++ default: printf("invalide args\n"); ++ exit(EXIT_FAILURE); ++ } ++ } ++#if 0 ++ outfd = open(fName,O_RDWR|O_CREAT|O_TRUNC,0777); ++ ++ if(outfd<0) ++ { ++ printf("open file:%s error!!\n",fName); ++ perror("error:"); ++ return -1; ++ } ++#endif ++ if(NULL!=fName) ++ { ++ printf("Server ready!! fName: %s, socket_port: %d\n",fName,port); ++ }else ++ { ++ printf("Server ready!! socket_port: %d\n",port); ++ } ++ sleep(1); ++ ++ sockfd=socket(AF_INET,SOCK_STREAM,0); ++ bzero(&dest,sizeof(dest)); ++ dest.sin_family=AF_INET; ++ dest.sin_port=htons(port); ++ dest.sin_addr.s_addr=INADDR_ANY; ++ signal(SIGINT, finish_function); ++ bind(sockfd,(struct sockaddr*)&dest,sizeof(dest)); ++ listen(sockfd,20); ++ ++ ++ while(1) ++ { ++ int clientfd; ++ struct sockaddr_in client_addr; ++ int addrlen=sizeof(client_addr); ++ int pktCount=0; ++ ++ clientfd=accept(sockfd,(struct sockaddr*)&client_addr,(socklen_t*)&addrlen); ++ if (clientfd < 0) ++ { ++ perror("accept failed"); ++ return -1; ++ } ++ printf("client connection accepted\n"); ++ while(1) ++ { ++ int ret=0; ++ ++ ret=recv_with_header(clientfd,tbuf); ++ ++ if(ret>0) ++ { ++#if 0 ++ write(outfd,*tbuf,ret); ++#endif ++ unsigned char *buf=(unsigned char*)tbuf[0];//(unsigned char *)(*tbuf); ++ int pktid=0; ++ int pktcs=0;//((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ int cs=0; ++// if(0==pktCount%100) ++// { ++// printf("pktCount: %08d\n",pktCount); ++// } ++ pktcs=((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ cs=checksum(buf,ret-4); ++ pktid=(buf[3]<<24) + (buf[2]<<16)+(buf[1]<<8) + (buf[0]); ++ if(pktcs!=cs || pktid!=pktCount) ++ { ++ int j=0; ++ unsigned int lc=0; ++ printf(" ERROR!! pktCount[%d, %d]: cs=0x%08X, pktcs=0x%08X\n\n",pktCount,pktid,cs,pktcs); ++ for(j=0;j 0 ) ++// { ++// //Send the message back to client ++// write(client_sock , client_message , strlen(client_message)); ++// } ++ ++ } ++ ++ if(NULL!=fName) ++ { ++ free(fName); ++ } ++ close(outfd); ++ return 0; ++} +diff --git a/drivers/sstar/samples/build_riu.sh b/drivers/sstar/samples/build_riu.sh +new file mode 100755 +index 000000000000..ea1928c40099 +--- /dev/null ++++ b/drivers/sstar/samples/build_riu.sh +@@ -0,0 +1,9 @@ ++rm -rf output ++mkdir output ++$CROSS_COMPILE\gcc riu.c -o output/riu_r ++$CROSS_COMPILE\strip --strip-unneeded output/riu_r ++ ++cd output ++ln -s riu_r riu_w ++ln -s riu_r riux32_w ++ln -s riu_r riux32_r +diff --git a/drivers/sstar/samples/dmem.c b/drivers/sstar/samples/dmem.c +new file mode 100755 +index 000000000000..7cce04b0780a +--- /dev/null ++++ b/drivers/sstar/samples/dmem.c +@@ -0,0 +1,180 @@ ++/* ++* dmem.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++ ++ ++ ++#include "../../../drivers/sstar/include/mdrv_msys_io.h" ++#include "../../../drivers/sstar/include/mdrv_msys_io_st.h" ++#include "../../../drivers/sstar/include/mdrv_verchk.h" ++ ++//void sleep_ms(int milliseconds) // cross-platform sleep function ++//{ ++//#ifdef WIN32 ++// Sleep(milliseconds); ++//#elif _POSIX_C_SOURCE >= 199309L ++// struct timespec ts; ++// ts.tv_sec = 0; ++// ts.tv_nsec = milliseconds * 1000000; ++// nanosleep(&ts, NULL); ++//#else ++// usleep(milliseconds * 1000); ++//#endif ++//} ++ ++ ++ ++ ++int main ( int argc, char **argv ) ++{ ++ int msys_fd=open("/dev/msys",O_RDWR|O_SYNC); ++ int mem_fd=open("/dev/mem",O_RDWR|O_SYNC); ++// int kmem_fd=open("/dev/kmem",O_RDWR|O_SYNC); ++ unsigned char * map_base; ++ MSYS_DMEM_INFO info; ++ char **ptr=NULL; ++ unsigned long addr; ++ unsigned char content; ++ int i = 0; ++ FILL_VERCHK_TYPE(info, info.VerChk_Version, info.VerChk_Size, IOCTL_MSYS_VERSION); ++ if(-1==msys_fd) ++ { ++ printf("can't open /dev/msys\n"); ++ goto OPEN_FAILED; ++ } ++ ++ if(-1==mem_fd) ++ { ++ printf("can't open /dev/mem\n"); ++ goto FAILED; ++ } ++// ++// if(-1==kmem_fd){ ++// printf("can't open /dev/kmem\n"); ++// goto OPEN_FAILED; ++// } ++ ++ if(0==strncmp("-req",argv[1],4)) ++ { ++ ++ if(0==strncmp("0x",argv[2],2)) ++ { ++ info.length=strtol(argv[2],ptr,16); ++ } ++ else ++ { ++ info.length=atoi(argv[2]); ++ } ++ ++ memset(info.name,16,0); ++ if(argc>3) ++ { ++ strncpy(info.name,argv[3],15); ++ } ++ ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_REQUEST_DMEM, &info)) ++ { ++ printf("DMEM request failed!!\n"); ++ goto FAILED; ++ } ++ printf("PHYS=0x%08X,KVIRT=0x%08X, LENGTH=0x%08X\n",(unsigned int)info.phys,(unsigned int)info.kvirt,(unsigned int)info.length); ++ ++ map_base = mmap(NULL, info.length, PROT_READ|PROT_WRITE, MAP_SHARED, mem_fd, info.phys); ++ ++ if (map_base == 0) ++ { ++ printf("NULL pointer!\n"); ++ goto FAILED; ++ ++ } ++ else ++ { ++ printf("Successfull!\n"); ++ } ++ ++ ++ //for (; i < 0xff; ++i) ++ //{ ++ // addr = (unsigned long)(map_base + i); ++ // content = map_base[i]; ++ // printf("address: 0x%lx content 0x%x\t\t", addr, (unsigned int)content); ++ // ++ // map_base[i] = (unsigned char)i; ++ // content = map_base[i]; ++ // printf("updated address: 0x%lx content 0x%x\n", addr, (unsigned int)content); ++ //} ++ munmap(map_base, 0xff); ++ ++ } ++ else if(0==strncmp("-rel",argv[1],4)) ++ { ++ if(0==strncmp("0x",argv[2],2)) ++ { ++ info.phys=strtol(argv[2],ptr,16); ++ } ++ else ++ { ++ info.phys=atoi(argv[2]); ++ } ++ ++ memset(info.name,16,0); ++ if(argc>3) ++ { ++ strncpy(info.name,argv[3],15); ++ } ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_RELEASE_DMEM, &info)) ++ { ++ printf("DMEM release failed!!\n"); ++ goto FAILED; ++ } ++ } ++ else ++ { ++ printf("unsupported usage for dmem\n"); ++ printf("usage:\n"); ++ printf(" -req [name]\n"); ++ printf(" -rel [name]\n"); ++ ++ ++ } ++ ++ ++ close(msys_fd); ++ close(mem_fd); ++// close(kmem_fd); ++ return 0; // Indicates that everything vent well. ++ ++FAILED: ++ if(-1!=msys_fd)close(msys_fd); ++ if(-1!=mem_fd)close(mem_fd); ++// if(-1!=kmem_fd)close(kmem_fd); ++ ++OPEN_FAILED: ++ return -1; ++ ++} +diff --git a/drivers/sstar/samples/regio.c b/drivers/sstar/samples/regio.c +new file mode 100755 +index 000000000000..e9c10a69c79e +--- /dev/null ++++ b/drivers/sstar/samples/regio.c +@@ -0,0 +1,130 @@ ++/* ++* regio.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++#include "../../drivers/sstar/include/mdrv_msys_io.h" ++#include "../../drivers/sstar/include/mdrv_msys_io_st.h" ++ ++int main(int argc, char *argv[]) ++{ ++ int msys_fd=-1; ++ int mem_fd=-1; ++ void *reg_map; ++ char **ptr=NULL; ++ int rlen=8; ++ int roffset; ++ MSYS_MMIO_INFO reg_map_info; ++ //printf("[mmio]START\n"); ++ ++ msys_fd = open("/dev/msys", O_RDWR|O_SYNC); ++ if (msys_fd == -1) ++ { ++ printf("Can't open /dev/msys\n"); ++ goto OUT; ++ } ++ mem_fd = open("/dev/mem", O_RDWR|O_SYNC); ++ if (mem_fd == -1) ++ { ++ printf("Can't open /dev/mem\n"); ++ goto OUT; ++ } ++ ++ //printf("devices open success!!\n"); ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_GET_RIU_MAP, ®_map_info)) ++ { ++ printf("IOCTL_MSYS_GET_RIU_MAP failed!!\n"); ++ goto OUT; ++ } ++// printf("reg_map_info: addr=0x%08X, size=0x%08X\n",(unsigned int)reg_map_info.addr,reg_map_info.size); ++ ++ if(((unsigned int)(reg_map=mmap (NULL, reg_map_info.size, PROT_READ|PROT_WRITE, MAP_SHARED , mem_fd, reg_map_info.addr))) == (unsigned int)MAP_FAILED) ++ { ++ printf("reg_map failed!!\n"); ++ goto OUT; ++ } ++ ++ sleep(1); ++// printf("The reg_map is ready, addr=0x%08X\n",(unsigned int)reg_map); ++ ++ if(0==strncmp("-r",argv[1],4)) ++ { ++ int i=0; ++ if(0==strncmp("0x",argv[2],2)) ++ { ++ roffset=strtol(argv[2],ptr,16); ++ } ++ else ++ { ++ roffset=atoi(argv[2]); ++ } ++ ++ ++ if(0==strncmp("0x",argv[3],2)) ++ { ++ rlen=strtol(argv[3],ptr,16); ++ } ++ else ++ { ++ rlen=atoi(argv[3]); ++ } ++ ++ rlen=(rlen<8)?8:rlen; ++ ++ ++ int *p=(int *)(reg_map+roffset); ++ for(i=0;i(32bit reg offset) (8 aligned)\n"); ++ printf(" -w
(32bit reg offset) \n"); ++ ++ } ++ ++ ++ ++ if(0!=munmap(reg_map,reg_map_info.size-1)) ++ { ++ printf("munmap failed!!\n"); ++ reg_map=NULL; ++ } ++ ++OUT: ++ if(msys_fd!=-1)close(msys_fd); ++ if(mem_fd!=-1)close(mem_fd); ++ ++// printf("[regio]END\n"); ++} +diff --git a/drivers/sstar/samples/regio.png b/drivers/sstar/samples/regio.png +new file mode 100755 +index 000000000000..d488954b66e8 +Binary files /dev/null and b/drivers/sstar/samples/regio.png differ +diff --git a/drivers/sstar/samples/riu.c b/drivers/sstar/samples/riu.c +new file mode 100755 +index 000000000000..7c9b294d5550 +--- /dev/null ++++ b/drivers/sstar/samples/riu.c +@@ -0,0 +1,175 @@ ++/* ++* riu.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++ ++#include "../../../drivers/sstar/include/mdrv_msys_io.h" ++#include "../../../drivers/sstar/include/mdrv_msys_io_st.h" ++#include "../../../drivers/sstar/include/mdrv_verchk.h" ++ ++int main ( int argc, char **argv ) ++{ ++ int msys_fd=0; ++ int mem_fd=0; ++ unsigned char * map_base=NULL; ++ MSYS_MMIO_INFO info; ++ char **ptr=NULL; ++ unsigned long addr; ++ unsigned short content; ++ unsigned int content_x32; ++ ++ int i = 0; ++ FILL_VERCHK_TYPE(info, info.VerChk_Version, info.VerChk_Size, IOCTL_MSYS_VERSION); ++ unsigned long bank=0, offset=0; ++ ++ msys_fd=open("/dev/msys",O_RDWR|O_SYNC); ++ if(-1==msys_fd) ++ { ++ printf("can't open /dev/msys\n"); ++ goto OPEN_FAILED; ++ } ++ mem_fd=open("/dev/mem",O_RDWR|O_SYNC); ++ if(-1==mem_fd) ++ { ++ printf("can't open /dev/mem\n"); ++ goto FAILED; ++ } ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_GET_RIU_MAP, &info)) ++ { ++ printf("DMEM request failed!!\n"); ++ goto FAILED; ++ } ++ //printf("PHYS=0x%08X, LENGTH=0x%08X\n",(unsigned int)info.addr, (unsigned int)info.size); ++ ++ map_base = mmap(NULL, info.size, PROT_READ|PROT_WRITE, MAP_SHARED, mem_fd, info.addr); ++ if (map_base == 0) ++ { ++ printf("NULL pointer!\n"); ++ goto FAILED; ++ ++ } ++ //printf("PHYS=0x%08X, LENGTH=0x%08X\n",(unsigned int)map_base, (unsigned int)info.size); ++ ++ if (!strcmp((const char *)basename(argv[0]), "riu_w")) ++ { ++ if(argc == 4) ++ { ++ bank=strtol(argv[1],ptr,16); ++ offset=strtol(argv[2],ptr,16); ++ content=strtol(argv[3],ptr,16); ++ printf("BANK:0x%04X 16bit-offset 0x%02X\n", bank, offset); ++ addr = (unsigned long)(map_base + bank*0x200 + offset*4); ++ *(unsigned short *)addr = content; ++ content = *(unsigned short *)addr; ++ printf("0x%04X\n", (unsigned int)content); ++ } ++ } ++ else if (!strcmp((const char *)basename(argv[0]), "riu_r")) ++ { ++ if(argc == 2) ++ { ++ bank=strtol(argv[1],ptr,16); ++ printf("BANK:0x%04X\n", bank); ++ for (i=0; i <= 0x7f; i+=1) ++ { ++ if(i%0x8==0x0) printf("%02X: ", i); ++ addr = (unsigned long)(map_base + bank*0x200 + i*4); ++ content = *(unsigned short *)addr; ++ printf("0x%04X ", (unsigned int)content); ++ if(i%0x8==0x7) printf("\n"); ++ } ++ } ++ else if(argc == 3) ++ { ++ bank=strtol(argv[1],ptr,16); ++ offset=strtol(argv[2],ptr,16); ++ printf("BANK:0x%04X 16bit-offset 0x%02X\n", bank, offset); ++ addr = (unsigned long)(map_base + bank*0x200 + offset*4); ++ content = *(unsigned short *)addr; ++ printf("0x%04X\n", (unsigned int)content); ++ } ++ } ++ else if (!strcmp((const char *)basename(argv[0]), "riux32_w")) ++ { ++ if(argc == 4) ++ { ++ bank=strtol(argv[1],ptr,16); ++ offset=strtol(argv[2],ptr,16); ++ content_x32=strtol(argv[3],ptr,16); ++ printf("BANK:0x%04X 16bit-offset 0x%02X\n", bank, offset); ++ addr = (unsigned long)(map_base + bank*0x200 + offset*4); ++ *(unsigned int *)addr = content_x32; ++ content_x32 = *(unsigned int *)addr; ++ printf("0x%08X\n", (unsigned int)content_x32); ++ } ++ } ++ else if (!strcmp((const char *)basename(argv[0]), "riux32_r")) ++ { ++ if(argc == 2) ++ { ++ bank=strtol(argv[1],ptr,16); ++ printf("BANK:0x%04X\n", bank); ++ for (i=0; i <= 0x7f; i+=1) ++ { ++ if(i%0x8==0x0) printf("%02X: ", i); ++ addr = (unsigned long)(map_base + bank*0x200 + i*4); ++ content_x32 = *(unsigned int *)addr; ++ printf("0x%08X ", content_x32); ++ if(i%0x8==0x7) printf("\n"); ++ } ++ } ++ else if(argc == 3) ++ { ++ bank=strtol(argv[1],ptr,16); ++ offset=strtol(argv[2],ptr,16); ++ printf("BANK:0x%04X 16bit-offset 0x%02X\n", bank, offset); ++ addr = (unsigned long)(map_base + bank*0x200 + offset*4); ++ content_x32 = *(unsigned int *)addr; ++ printf("0x%08X\n", content_x32); ++ } ++ } ++ else ++ { ++ printf("argument error\n"); ++ } ++ ++ if(map_base!= NULL) ++ munmap(map_base, 0xff); ++ ++ close(msys_fd); ++ close(mem_fd); ++ return 0; // Indicates that everything vent well. ++ ++FAILED: ++ if(-1!=msys_fd)close(msys_fd); ++ if(-1!=mem_fd)close(mem_fd); ++ ++ ++OPEN_FAILED: ++ return -1; ++ ++} +diff --git a/drivers/sstar/samples/unametest.c b/drivers/sstar/samples/unametest.c +new file mode 100755 +index 000000000000..0a80ab416219 +--- /dev/null ++++ b/drivers/sstar/samples/unametest.c +@@ -0,0 +1,51 @@ ++/* ++* unametest.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++/* ++The output is as following: ++system name = Linux ++node name = (none) ++release = 3.18.14 ++version = #421 SMP PREEMPT Thu Jun 11 07:05:52 CST 2015 ++machine = armv7l ++*/ ++int main(void) { ++ ++ struct utsname buffer; ++ ++ errno = 0; ++ if (uname(&buffer) != 0) { ++ perror("uname"); ++ exit(EXIT_FAILURE); ++ } ++ ++ printf("system name = %s\n", buffer.sysname); ++ printf("node name = %s\n", buffer.nodename); ++ printf("release = %s\n", buffer.release); ++ printf("version = %s\n", buffer.version); ++ printf("machine = %s\n", buffer.machine); ++ ++ #ifdef _GNU_SOURCE ++ printf("domain name = %s\n", buffer.domainname); ++ #endif ++ ++ return EXIT_SUCCESS; ++} +diff --git a/drivers/sstar/samples/us_ticks.c b/drivers/sstar/samples/us_ticks.c +new file mode 100755 +index 000000000000..4b3353f48cfa +--- /dev/null ++++ b/drivers/sstar/samples/us_ticks.c +@@ -0,0 +1,65 @@ ++/* ++* us_ticks.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++ ++#define MSYS_IOCTL_MAGIC 'S' ++ ++#define IOCTL_MSYS_GET_US_TICKS _IO(MSYS_IOCTL_MAGIC, 0x31) ++ ++int main(int argc, char** argv) ++{ ++ int msys_fd=open("/dev/msys",O_RDWR|O_SYNC); ++ unsigned long long t0=0,t1=0; ++ int count=0; ++ if(-1==msys_fd) ++ { ++ printf("can't open /dev/msys\n"); ++ goto OPEN_FAILED; ++ } ++ ++ while(1) ++ { ++ ioctl(msys_fd, IOCTL_MSYS_GET_US_TICKS, &t0); ++ if(t0 ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "ms_msys.h" ++#include "mdrv_sar.h" ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++#endif ++ ++//#define OPEN_SAR_DEBUG ++static U32 _gMIO_MapBase = 0; ++static U8 m_u8Init = 0; ++ ++#ifdef OPEN_SAR_DEBUG //switch printk ++#define sarDbg printk ++#else ++#define sarDbg(...) ++#endif ++ ++struct ms_sar ++{ ++ struct device *dev; ++ struct device *msysdev; ++ void __iomem *reg_base; ++#ifdef CONFIG_CAM_CLK ++ void *pvSarClk; ++#else ++ struct clk *clk; ++#endif ++}; ++ ++static int ms_sar_open(struct inode *inode, struct file *file); ++int ms_sar_get(int ch); ++static long ms_sar_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++void ms_sar_hw_init(void); ++ ++ ++static const struct file_operations sar_fops = ++{ ++ .open = ms_sar_open, ++ .unlocked_ioctl = ms_sar_ioctl, ++ ++}; ++static struct miscdevice sar_miscdev = {MISC_DYNAMIC_MINOR, DEVICE_NAME, &sar_fops}; ++ ++ ++BOOL HAL_SAR_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++U16 HAL_SAR_Read2Byte(U32 u32RegAddr) ++{ ++ return (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_SAR_Write2ByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ u16Val = (HAL_SAR_Read2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ //sarDbg("sar IOMap base:%16llx u16Val:%4x\n", _gMIO_MapBase, u16Val); ++ HAL_SAR_Write2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++ ++static long ms_sar_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ S32 s32Err= 0; ++ SAR_ADC_CONFIG_READ adcCfg; ++ ++ //printk("%s is invoked\n", __FUNCTION__); ++ ++ /* ++ * extract the type and number bitfields, and don't decode ++ * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ */ ++ if ((SARADC_IOC_MAGIC!= _IOC_TYPE(cmd)) || (_IOC_NR(cmd)> SARADC_IOC_MAXNR)) ++ { ++ return -ENOTTY; ++ } ++ ++ /* ++ * the direction is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. `Type' is user-oriented, while ++ * access_ok is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ { ++ s32Err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ { ++ s32Err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ if (s32Err) ++ { ++ return -EFAULT; ++ } ++ ++ ++ ++ switch(cmd) ++ { ++ case IOCTL_SAR_INIT: ++ ms_sar_hw_init(); ++ break; ++ ++ case IOCTL_SAR_SET_CHANNEL_READ_VALUE: ++ if(copy_from_user(&adcCfg, (SAR_ADC_CONFIG_READ __user *)arg, sizeof(SAR_ADC_CONFIG_READ))) ++ { ++ return EFAULT; ++ } ++ ++ channel = adcCfg.channel_value & 3; ++ ++ adcCfg.adc_value = ms_sar_get(channel); ++ sarDbg("channel = %d , adc =%d \n",channel, adcCfg.adc_value); ++ ++ if(copy_to_user((SAR_ADC_CONFIG_READ __user *)arg, &adcCfg, sizeof( SAR_ADC_CONFIG_READ))) ++ { ++ return EFAULT; ++ } ++ break; ++ ++ default: ++ printk("ioctl: unknown command\n"); ++ return -ENOTTY; ++ } ++ return 0; ++ ++} ++ ++static int ms_sar_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++void ms_sar_hw_init(void) ++{ ++ if (!m_u8Init) { ++ HAL_SAR_Write2Byte(REG_SAR_CTRL0,0x0a20); ++ //HAL_SAR_Write2Byte(REG_SAR_CKSAMP_PRD,0x0005); ++ //HAL_SAR_Write2ByteMask(REG_SAR_CTRL0,0x4000,0x4000); ++ m_u8Init = 1; ++ } ++} ++EXPORT_SYMBOL(ms_sar_hw_init); ++ ++int ms_sar_get(int ch) ++{ ++ U16 value=0; ++ U32 count=0; ++ HAL_SAR_Write2ByteMask(REG_SAR_CTRL0,BIT14, 0x4000); ++ while(HAL_SAR_Read2Byte(REG_SAR_CTRL0)&BIT14 && count<100000) ++ { ++ udelay(1); ++ count++; ++ } ++ ++ switch(ch) ++ { ++ case 0: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT0, BIT0); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH1_DATA); ++ break; ++ case 1: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT1, BIT1); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH2_DATA); ++ break; ++ case 2: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT2, BIT2); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH3_DATA); ++ break; ++ case 3: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT3, BIT3); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH4_DATA); ++ break; ++ default: ++ printk(KERN_ERR "error channel,support SAR0,SAR1,SAR2,SAR3\n"); ++ break; ++ } ++ return value; ++} ++EXPORT_SYMBOL(ms_sar_get); ++ ++static ssize_t channel_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ channel = simple_strtoul(buf, NULL, 10); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t channel_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", channel); ++ return (str - buf); ++} ++DEVICE_ATTR(channel, 0644, channel_show, channel_store); ++ ++static ssize_t value_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ ms_sar_hw_init(); ++ str += scnprintf(str, end - str, "%d\n", ms_sar_get(channel & 3)); ++ return (str - buf); ++} ++DEVICE_ATTR(value, 0444, value_show, NULL); ++ ++static int infinity_sar_probe(struct platform_device *pdev) ++{ ++ struct device *dev; ++ struct ms_sar *sar; ++ struct resource *res; ++#ifdef CONFIG_CAM_CLK ++ u32 SarClk = 0; ++ CAMCLK_Set_Attribute stSetCfg; ++ CAMCLK_Get_Attribute stGetCfg; ++#else ++ int retval; ++ struct clk *clk; ++ struct clk_hw *hw_parent; ++#endif ++ sarDbg("[SAR] probe\n"); ++ // printk("[SAR] infinity_sar_probe \n"); ++ dev = &pdev->dev; ++ sar = devm_kzalloc(dev, sizeof(*sar), GFP_KERNEL); ++ if (!sar) ++ return -ENOMEM; ++ ++ m_u8Init = 0; ++ channel = 0; ++ sar->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ sarDbg("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ sar->reg_base = devm_ioremap_resource(&pdev->dev, res); ++ _gMIO_MapBase=(U32)sar->reg_base; ++#ifdef CONFIG_CAM_CLK ++ of_property_read_u32_index(dev->of_node,"camclk", 0,&(SarClk)); ++ if (!SarClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ if(CamClkRegister("Sar",SarClk,&(sar->pvSarClk))==CAMCLK_RET_OK) ++ { ++ CamClkAttrGet(sar->pvSarClk,&stGetCfg); ++ CAMCLK_SETPARENT(stSetCfg,stGetCfg.u32Parent[0]); ++ CamClkAttrSet(sar->pvSarClk,&stSetCfg); ++ CamClkSetOnOff(sar->pvSarClk,1); ++ } ++ } ++#else ++ //2. set clk ++ clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(clk)) ++ { ++ retval = PTR_ERR(clk); ++ sarDbg("[%s]: of_clk_get failed\n", __func__); ++ } ++ else ++ { ++ /* select clock mux */ ++ hw_parent = clk_hw_get_parent_by_index(__clk_get_hw(clk), 0); // select mux 0 ++ sarDbg( "[%s]parent_num:%d parent[0]:%s\n", __func__, ++ clk_hw_get_num_parents(__clk_get_hw(clk)), clk_hw_get_name(hw_parent)); ++ clk_set_parent(clk, hw_parent->clk); ++ ++ clk_prepare_enable(clk); ++ sar->clk = clk; ++ sarDbg("[SAR] clk_prepare_enable\n"); ++ } ++#endif ++ platform_set_drvdata(pdev, sar); ++ misc_register(&sar_miscdev); ++ ++ sar->msysdev = device_create(msys_get_sysfs_class(), NULL, sar->dev->devt, NULL, "sar"); ++ if (sar->msysdev) { ++ device_create_file(sar->msysdev, &dev_attr_channel); ++ device_create_file(sar->msysdev, &dev_attr_value); ++ } ++ return 0; ++} ++ ++static int infinity_sar_remove(struct platform_device *pdev) ++{ ++ struct ms_sar *sar = platform_get_drvdata(pdev); ++ struct device *dev = &pdev->dev; ++ ++ sarDbg("[SAR] remove\n"); ++ device_destroy(msys_get_sysfs_class(), sar->dev->devt); ++ misc_deregister(&sar_miscdev); ++ if (sar) { ++#ifdef CONFIG_CAM_CLK ++ if(sar->pvSarClk) ++ { ++ CamClkSetOnOff(sar->pvSarClk,0); ++ CamClkUnregister(sar->pvSarClk); ++ } ++#else ++ ++ if (sar->clk) ++ { ++ clk_disable_unprepare(sar->clk); ++ clk_put(sar->clk); ++ } ++#endif ++ devm_kfree(dev, sar); ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int infinity_sar_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct ms_sar *sar = platform_get_drvdata(pdev); ++ ++ sarDbg("[SAR] suspend\n"); ++#ifdef CONFIG_CAM_CLK ++ if(sar && sar->pvSarClk) ++ { ++ CamClkSetOnOff(sar->pvSarClk,0); ++ } ++#else ++ if (sar && sar->clk) { ++ clk_disable_unprepare(sar->clk); ++ } ++#endif ++ return 0; ++} ++ ++static int infinity_sar_resume(struct platform_device *pdev) ++{ ++ struct ms_sar *sar = platform_get_drvdata(pdev); ++ ++ sarDbg("[SAR] resume\n"); ++#ifdef CONFIG_CAM_CLK ++ if(sar && sar->pvSarClk) ++ { ++ CamClkSetOnOff(sar->pvSarClk,1); ++ } ++#else ++ if (sar && sar->clk) { ++ clk_prepare_enable(sar->clk); ++ } ++#endif ++ return 0; ++} ++#endif /* CONFIG_PM_SLEEP */ ++ ++ ++ ++ ++static const struct of_device_id ms_sar_of_match_table[] = ++{ ++ { .compatible = "sstar,infinity-sar" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_sar_of_match_table); ++ ++static struct platform_driver infinity_sar_driver = ++{ ++ .probe = infinity_sar_probe, ++ .remove = infinity_sar_remove, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = infinity_sar_suspend, ++ .resume = infinity_sar_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "infinity-sar", ++ .of_match_table = ms_sar_of_match_table, ++ }, ++}; ++ ++module_platform_driver(infinity_sar_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("infinity Sar Device Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:infinity-sar"); +diff --git a/drivers/sstar/sar/mdrv_sar.h b/drivers/sstar/sar/mdrv_sar.h +new file mode 100755 +index 000000000000..1a96d143e99a +--- /dev/null ++++ b/drivers/sstar/sar/mdrv_sar.h +@@ -0,0 +1,95 @@ ++/* ++* mdrv_sar.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_SAR_H ++#define __MDRV_SAR_H ++ ++//#include ++//#include "mach/platform.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "mdrv_sar_io.h" ++ ++#define DEVICE_NAME "sar" ++ ++#define BASE_REG_RIU_PA (0x1F000000) ++//#define BASE_REG_WDT_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x001800) ++//#define BASE_REG_PM_PA GET_REG_ADDR(CHICAGO_BASE_REG_RIU_PA, 0x000700) ++#define BK_REG(reg) ((reg) << 2) ++ ++static int channel = 1; ++//static int mode = 0; ++ ++#define SARADC_IOC_MAXNR 2 ++ ++#define REG_SAR_CTRL0 0x00*2 ++#define REG_SAR_CKSAMP_PRD 0x01*2 ++#define REG_SAR_GCR_SAR_CH8 0x02*2 ++#define REG_SAR_AISEL_CTRL 0x11*2 ++#define REG_SAR_GPIO_CTRL 0x12*2 ++#define REG_SAR_INT_MASK 0x14*2 ++#define REG_SAR_INT_CLR 0x15*2 ++#define REG_SAR_INT_FORCE 0x16*2 ++#define REG_SAR_INT_STATUS 0x17*2 ++#define REG_SAR_CMP_OUT_RDY 0x18*2 ++#define REG_SAR_CH_REF_V_SEL 0x19*2 ++#define REG_SAR_CH1_UPB 0x20*2 ++#define REG_SAR_CH2_UPB 0x21*2 ++#define REG_SAR_CH3_UPB 0x22*2 ++#define REG_SAR_CH4_UPB 0x23*2 ++#define REG_SAR_CH5_UPB 0x24*2 ++#define REG_SAR_CH6_UPB 0x25*2 ++#define REG_SAR_CH7_UPB 0x26*2 ++#define REG_SAR_CH8_UPB 0x27*2 ++#define REG_SAR_CH1_LOB 0x30*2 ++#define REG_SAR_CH2_LOB 0x31*2 ++#define REG_SAR_CH3_LOB 0x32*2 ++#define REG_SAR_CH4_LOB 0x33*2 ++#define REG_SAR_CH5_LOB 0x34*2 ++#define REG_SAR_CH6_LOB 0x35*2 ++#define REG_SAR_CH7_LOB 0x36*2 ++#define REG_SAR_CH8_LOB 0x37*2 ++#define REG_SAR_CH1_DATA 0x40*2 ++#define REG_SAR_CH2_DATA 0x41*2 ++#define REG_SAR_CH3_DATA 0x42*2 ++#define REG_SAR_CH4_DATA 0x43*2 ++#define REG_SAR_CH5_DATA 0x44*2 ++#define REG_SAR_CH6_DATA 0x45*2 ++#define REG_SAR_CH7_DATA 0x46*2 ++#define REG_SAR_CH8_DATA 0x47*2 ++#define REG_SAR_SMCARD_CTRL 0x50*2 ++#define REG_SAR_FCIE_INT_CTRL 0x51*2 ++#define REG_SAR_INT_DIRECT2TOP_SEL 0x60*2 ++ ++#define BIT_0 0x1 ++#define BIT_1 0x2 ++#define BIT_2 0x4 ++#define BIT_3 0x8 ++#define BIT_4 0x10 ++#define BIT_5 0x20 ++#define BIT_6 0x40 ++#define BIT_7 0x80 ++#define BIT_8 0x100 ++#define BIT_9 0x200 ++#define BIT_10 0x400 ++#define BIT_11 0x800 ++#define BIT_12 0x1000 ++#define BIT_13 0x2000 ++#define BIT_14 0x4000 ++#define BIT_15 0x8000 ++ ++#endif +diff --git a/drivers/sstar/sar_key/Kconfig b/drivers/sstar/sar_key/Kconfig +new file mode 100644 +index 000000000000..2295d913d30e +--- /dev/null ++++ b/drivers/sstar/sar_key/Kconfig +@@ -0,0 +1,9 @@ ++config MS_SARKEY ++ tristate "sar key driver" ++ help ++ Say Y here to enable the driver for the sar key. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mdrv_sar. +diff --git a/drivers/sstar/sar_key/Makefile b/drivers/sstar/sar_key/Makefile +new file mode 100644 +index 000000000000..0666463bea79 +--- /dev/null ++++ b/drivers/sstar/sar_key/Makefile +@@ -0,0 +1,3 @@ ++# general options ++ ++obj-$(CONFIG_MS_SARKEY) += adc-keys.o +diff --git a/drivers/sstar/sar_key/adc-keys.c b/drivers/sstar/sar_key/adc-keys.c +new file mode 100644 +index 000000000000..588f29a5413f +--- /dev/null ++++ b/drivers/sstar/sar_key/adc-keys.c +@@ -0,0 +1,210 @@ ++/* ++ * Input driver for resistor ladder connected on ADC ++ * ++ * Copyright (c) 2016 Alexandre Belloni ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++#include ++//#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include "../sar/mdrv_sar.h" ++ ++struct adc_keys_button { ++ u32 voltage; ++ u32 keycode; ++}; ++ ++struct adc_keys_state { ++ //struct iio_channel *channel; ++ int chan; ++ u32 num_keys; ++ u32 last_key; ++ u32 keyup_voltage; ++ const struct adc_keys_button *map; ++}; ++extern int ms_sar_get(int ch); ++extern void ms_sar_hw_init(void); ++ ++static void adc_keys_poll(struct input_polled_dev *dev) ++{ ++ struct adc_keys_state *st = dev->private; ++ int i, value; ++ u32 diff, closest = 0xffffffff; ++ int keycode = 0; ++ ++ //ret = iio_read_channel_processed(st->channel, &value); ++ value = ms_sar_get(st->chan); ++ value = (value * 325) / 100; ++ if (unlikely(value < 0)) { ++ /* Forcibly release key if any was pressed */ ++ value = st->keyup_voltage; ++ } else { ++ for (i = 0; i < st->num_keys; i++) { ++ diff = abs(st->map[i].voltage - value); ++ if (diff < closest) { ++ closest = diff; ++ keycode = st->map[i].keycode; ++ } ++ } ++ } ++ ++ if (abs(st->keyup_voltage - value) < closest) ++ keycode = 0; ++ ++ if (st->last_key && st->last_key != keycode) ++ input_report_key(dev->input, st->last_key, 0); ++ ++ if (keycode){ ++ printk("keycode = %d value=%d \n", keycode,value); ++ input_report_key(dev->input, keycode, 1); ++ } ++ ++ input_sync(dev->input); ++ st->last_key = keycode; ++} ++ ++static int adc_keys_load_keymap(struct device *dev, struct adc_keys_state *st) ++{ ++ struct adc_keys_button *map; ++ struct fwnode_handle *child; ++ int i; ++ ++ st->num_keys = device_get_child_node_count(dev); ++ if (st->num_keys == 0) { ++ dev_err(dev, "keymap is missing\n"); ++ return -EINVAL; ++ } ++ ++ map = devm_kmalloc_array(dev, st->num_keys, sizeof(*map), GFP_KERNEL); ++ if (!map) ++ return -ENOMEM; ++ ++ i = 0; ++ device_for_each_child_node(dev, child) { ++ if (fwnode_property_read_u32(child, "press-threshold-microvolt", ++ &map[i].voltage)) { ++ dev_err(dev, "Key with invalid or missing voltage\n"); ++ fwnode_handle_put(child); ++ return -EINVAL; ++ } ++ map[i].voltage /= 1000; ++ ++ if (fwnode_property_read_u32(child, "linux,code", ++ &map[i].keycode)) { ++ dev_err(dev, "Key with invalid or missing linux,code\n"); ++ fwnode_handle_put(child); ++ return -EINVAL; ++ } ++ ++ i++; ++ } ++ ++ st->map = map; ++ return 0; ++} ++ ++static int adc_keys_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct adc_keys_state *st; ++ struct input_polled_dev *poll_dev; ++ struct input_dev *input; ++ //enum iio_chan_type type; ++ int i, value,chan; ++ int error; ++ ++ st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); ++ if (!st){ ++ return -ENOMEM; ++ } ++ ++ if (!device_property_read_u32(dev, "io-channels", &chan)) ++ st->chan = chan; ++ else{ ++ //set default ++ st->chan = 0; ++ } ++ ++ if (device_property_read_u32(dev, "keyup-threshold-microvolt", ++ &st->keyup_voltage)) { ++ dev_err(dev, "Invalid or missing keyup voltage\n"); ++ return -EINVAL; ++ } ++ st->keyup_voltage /= 1000; ++ ++ error = adc_keys_load_keymap(dev, st); ++ if (error) ++ return error; ++ ++ platform_set_drvdata(pdev, st); ++ ++ poll_dev = devm_input_allocate_polled_device(dev); ++ if (!poll_dev) { ++ dev_err(dev, "failed to allocate input device\n"); ++ return -ENOMEM; ++ } ++ ++ if (!device_property_read_u32(dev, "poll-interval", &value)) ++ poll_dev->poll_interval = value; ++ ++ poll_dev->poll = adc_keys_poll; ++ poll_dev->private = st; ++ ++ input = poll_dev->input; ++ ++ input->name = pdev->name; ++ input->phys = "adc-keys/input0"; ++ ++ input->id.bustype = BUS_HOST; ++ input->id.vendor = 0x0001; ++ input->id.product = 0x0001; ++ input->id.version = 0x0100; ++ ++ __set_bit(EV_KEY, input->evbit); ++ for (i = 0; i < st->num_keys; i++) ++ __set_bit(st->map[i].keycode, input->keybit); ++ ++ if (device_property_read_bool(dev, "autorepeat")) ++ __set_bit(EV_REP, input->evbit); ++ ++ error = input_register_polled_device(poll_dev); ++ if (error) { ++ dev_err(dev, "Unable to register input device: %d\n", error); ++ return error; ++ } ++ ms_sar_hw_init(); ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id adc_keys_of_match[] = { ++ { .compatible = "adc-keys", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, adc_keys_of_match); ++#endif ++ ++static struct platform_driver __refdata adc_keys_driver = { ++ .driver = { ++ .name = "adc_keys", ++ .of_match_table = of_match_ptr(adc_keys_of_match), ++ }, ++ .probe = adc_keys_probe, ++}; ++module_platform_driver(adc_keys_driver); ++ ++MODULE_AUTHOR("Alexandre Belloni "); ++MODULE_DESCRIPTION("Input driver for resistor ladder connected on ADC"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/sata_host/Kconfig b/drivers/sstar/sata_host/Kconfig +new file mode 100755 +index 000000000000..e5f8aec80e50 +--- /dev/null ++++ b/drivers/sstar/sata_host/Kconfig +@@ -0,0 +1,39 @@ ++config SS_SATA_HOST ++ tristate "SStar SATA HOST" ++ help ++ SStar SATA Host driver function ++ ++menu "Support Linux Ahci Platfrom Driver" ++ depends on SS_SATA_HOST ++config SS_SATA_AHCI_PLATFORM_HOST ++ depends on SATA_AHCI_PLATFORM ++ tristate "SSTAR SATA AHCI PLATFORM" ++ default y ++ help ++ Sstar sata driver supports linux ahci platform driver ++endmenu ++ ++menu "Select Sata Host Port" ++ depends on SS_SATA_HOST ++config SATA_HOST_0 ++ tristate "SStar SATA HOST Port 0" ++ default n ++ help ++ Sstar sata host port number selection ++ ++config SATA_HOST_1 ++ depends on ARCH_INFINITY2 ++ tristate "SStar SATA HOST Port 1" ++ default n ++ help ++ Sstar sata host port number selection ++endmenu ++ ++#menu "Sata Host Bench Test Program" ++# depends on SS_SATA_HOST ++#config SS_SATA_BENCH_TEST ++# tristate "Enable SATA Bench Test" ++# default n ++# help ++# Sstar sata host bench test code ++#endmenu +diff --git a/drivers/sstar/sata_host/Makefile b/drivers/sstar/sata_host/Makefile +new file mode 100755 +index 000000000000..947a766034e5 +--- /dev/null ++++ b/drivers/sstar/sata_host/Makefile +@@ -0,0 +1,52 @@ ++# ++# Makefile for SStar Sata Host device drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ifdef CONFIG_SSTAR_PROJECT_NAME ++ CONFIG_SSTAR_PROJECT_NAME := $(subst ",,$(CONFIG_SSTAR_PROJECT_NAME)) ++endif ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/ata ++EXTRA_CFLAGS += -Idrivers/sstar/sata_host ++EXTRA_CFLAGS += -Idrivers/sstar/sata_host/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++# specific options ++EXTRA_CFLAGS += ++ ++# files ++obj-$(CONFIG_SATA_HOST_0) += mdrv-sata-host.o ++ ++ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++mdrv-sata-host-objs := mdr_sata_host_ahci_platform.o ++ ++ifeq ($(CONFIG_SSTAR_CHIP_NAME), infinity2) ++ mdrv-sata-host-objs += $(CONFIG_SSTAR_CHIP_NAME)/mhal_sata_host_ahci.o ++else ifeq ($(CONFIG_SSTAR_CHIP_NAME), infinity2m) ++ mdrv-sata-host-objs += $(CONFIG_SSTAR_CHIP_NAME)/mhal_sata_host_ahci.o ++endif ++ ++else ++mdrv-sata-host-objs := mdrv_sata_host.o ++endif ++ ++ifeq ($(CONFIG_SSTAR_CHIP_NAME), infinity2m) ++ mdrv-sata-host-objs += $(CONFIG_SSTAR_CHIP_NAME)/mhal_sata_host.o ++endif ++ ++#i2 sata1 files ++obj-$(CONFIG_SATA_HOST_1) += mdrv-sata-host1.o ++ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++mdrv-sata-host1-objs := mdr_sata_host_ahci_platform1.o ++ifndef CONFIG_SATA_HOST_0 ++ mdrv-sata-host1-objs += $(CONFIG_SSTAR_CHIP_NAME)/mhal_sata_host_ahci.o ++endif ++ ++else ++mdrv-sata-host1-objs := mdrv_sata_host1.o ++endif ++ ++obj-$(CONFIG_SS_SATA_BENCH_TEST) += bench_test/ +diff --git a/drivers/sstar/sata_host/bench/Makefile b/drivers/sstar/sata_host/bench/Makefile +new file mode 100755 +index 000000000000..35462f772d68 +--- /dev/null ++++ b/drivers/sstar/sata_host/bench/Makefile +@@ -0,0 +1,15 @@ ++ ++KDIR=${PWD}/../../../../ ++ ++EXTRA_CFLAGS += -I$(KDIR)/include/linux ++EXTRA_CFLAGS += -I$(KDIR)/drivers/ata ++EXTRA_CFLAGS += -I$(KDIR)/drivers/sstar/include ++EXTRA_CFLAGS += -Wno-pointer-to-int-cast -Wno-unused-variable -Wno-unused-function -Wno-return-type ++ ++obj-m += sata_bench.o ++ ++all: ++ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -C $(KDIR) SUBDIRS=$(shell pwd) modules ++ ++clean: ++ rm -rf *.ko module* Module* +diff --git a/drivers/sstar/sata_host/bench/sata_bench.c b/drivers/sstar/sata_host/bench/sata_bench.c +new file mode 100644 +index 000000000000..6d6da2a2ff04 +--- /dev/null ++++ b/drivers/sstar/sata_host/bench/sata_bench.c +@@ -0,0 +1,152 @@ ++/* ++* sata_bench.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include "ahci.h" ++#include "cam_os_wrapper.h" ++ ++//============================================================================== ++// ++// GLOBAL VARIABLES ++// ++//============================================================================== ++static unsigned int comreset_interval_us = 300; ++module_param(comreset_interval_us, uint, 0); ++ ++static unsigned int comreset_repeat_times = 0; ++module_param(comreset_repeat_times, uint, 0); ++ ++static unsigned int sata_preset = 1; ++module_param(sata_preset, uint, 0); ++ ++ ++//============================================================================== ++// ++// DEFINES ++// ++//============================================================================== ++#define SSTAR_RIU_BASE 0xFD000000 ++#define SSTAR_HBA_BASE (SSTAR_RIU_BASE+0x345000) ++#define SSTAR_PORT_BASE (SSTAR_RIU_BASE+0x345100) ++ ++//============================================================================== ++// ++// FUNCTIONS ++// ++//============================================================================== ++ ++CamOsThread tBenchTaskHandle; ++ ++static void ss_sata_preset(void) ++{ ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((0x152500 + (0x00 << 1)) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((0x103800 + (0x6E << 1)) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((0x103800 + (0x6C << 1)) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((0x103800 + (0x46 << 1)) << 1)); ++ writew(0x0100, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x20 << 1)) << 1)); ++ writew(0x1008, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x30 << 1)) << 1)); ++ writew(0x0500, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x33 << 1)) << 1)); ++ writew(0x0001, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x05 << 1)) << 1)); ++ writew(0x0002, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x60 << 1)) << 1)); ++ writew(0x0062, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x70 << 1)) << 1)); ++ writew(0x8000, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x3E << 1)) << 1)); ++ writew(0x0002, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x04 << 1)) << 1)); ++ writew(0x0001, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x44 << 1)) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x44 << 1)) << 1)); ++ ++ writew(0x440A, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x0A << 1)) << 1)); ++ writew(0x1905, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x26 << 1)) << 1)); ++ writew(0xB659, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x3E << 1)) << 1)); ++ writew(0xD819, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x40 << 1)) << 1)); ++ writew(0x4000, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x61 << 1)) << 1)); ++ writew(0x0044, (volatile void *)SSTAR_RIU_BASE + ((0x152700 + (0x64 << 1)) << 1)); ++} ++ ++static void ss_sata_oob(void) ++{ ++ writel(0x00000001, (volatile void *)SSTAR_HBA_BASE + (HOST_CTL)); ++ writel(0x00000000, (volatile void *)SSTAR_HBA_BASE + (HOST_CAP)); ++ writel(0x00000001, (volatile void *)SSTAR_HBA_BASE + (HOST_PORTS_IMPL)); ++ writel(0x00000001, (volatile void *)SSTAR_PORT_BASE + (PORT_SCR_CTL)); ++ writel(0x00000000, (volatile void *)SSTAR_PORT_BASE + (PORT_SCR_CTL)); ++ writel(0x02100000, (volatile void *)SSTAR_PORT_BASE + (PORT_LST_ADDR)); ++ writel(0x02000000, (volatile void *)SSTAR_PORT_BASE + (PORT_FIS_ADDR)); ++ writel(0x00000016, (volatile void *)SSTAR_PORT_BASE + (PORT_CMD)); ++} ++ ++static void ss_sata_bench(void) ++{ ++ unsigned int counter=0; ++ int i; ++ ++ if (sata_preset) ++ ss_sata_preset(); ++ ++ if (!comreset_repeat_times) ++ { ++ while (1) ++ { ++ ss_sata_oob(); ++ udelay(comreset_interval_us); ++ if (CAM_OS_OK == CamOsThreadShouldStop()) ++ break; ++ } ++ } ++ else ++ { ++ while (counter < comreset_repeat_times) ++ { ++ ss_sata_oob(); ++ udelay(comreset_interval_us); ++ if (CAM_OS_OK == CamOsThreadShouldStop()) ++ break; ++ counter++; ++ } ++ } ++} ++ ++static int __init ss_sata_bench_init(void) ++{ ++ CamOsThreadAttrb_t tAttr = {0}; ++ ++ CamOsPrintf("[SATA Bench] Init()\r\n"); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&tBenchTaskHandle, &tAttr, (void *)ss_sata_bench, NULL); ++ ++ return 0; ++} ++ ++static void __exit ss_sata_bench_exit(void) ++{ ++ CamOsPrintf("[SATA Bench] Remove()\r\n"); ++ ++ CamOsThreadStop(tBenchTaskHandle); ++ ++ return; ++} ++module_init(ss_sata_bench_init); ++module_exit(ss_sata_bench_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("SIGMASTAR"); ++MODULE_DESCRIPTION("SATA BENCH"); +diff --git a/drivers/sstar/sata_host/bench_test/Makefile b/drivers/sstar/sata_host/bench_test/Makefile +new file mode 100755 +index 000000000000..72d3a07c7605 +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/Makefile +@@ -0,0 +1,22 @@ ++# ++# Makefile for MStar dip device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/sata_host/bench_test/include ++EXTRA_CFLAGS += -Idrivers/mstar/sata_host/bench_test/drv ++ ++# specific options ++EXTRA_CFLAGS += ++ ++#ccflags-y += -DMSOS_TYPE_LINUX_KERNEL ++#ccflags-y += -DDIP_REG_DUMP ++#ccflags-y += -DDIP_UT_MFDEC_SIM_MODE ++#ccflags-y += -DDIP_UT_ALLOC_MEM_FOR_3DDI ++#ccflags-y += -DDIP_UT_ENABLE_RIU ++#ccflags-y += -DDIP_UT_WO_IRQ ++ ++#--------------------- sources --------------------- ++obj-$(CONFIG_MS_SATA_BENCH_TEST) += sata_bench_test.o ++sata_bench_test-y := mdrv_sata_io.o ++sata_bench_test-y += drv/mhal_sata_bench_test.o +\ No newline at end of file +diff --git a/drivers/sstar/sata_host/bench_test/drv/mhal_sata_bench_test.c b/drivers/sstar/sata_host/bench_test/drv/mhal_sata_bench_test.c +new file mode 100755 +index 000000000000..ae07e9bb55e5 +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/drv/mhal_sata_bench_test.c +@@ -0,0 +1,487 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file mhal_sata_host.c ++/// @brief SATA Host Hal Driver ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++extern ptrdiff_t mstar_pm_base; ++#define sata_reg_write16(val, addr) { (*((volatile unsigned short*)(addr))) = (unsigned short)(val); } ++#define sata_reg_write8(val, addr) { (*((volatile unsigned char*)(addr))) = (unsigned char)(val);} ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++#define RIU_BASE_ADDR 0xFD000000 ++ ++#define _PK_L_(bank, addr) ((((u32)bank) << 8) | (u32)((addr)*2)) ++ ++void HAL_SATA_INFO_dump_Reg(u32 BankNo, u16 RegOffset, u32 len) ++{ ++ u32 addr, l_offset; ++ u8 l_buf[128], token_buf[8]; ++ u32 start; ++ ++ start = _PK_L_(BankNo, RegOffset); ++ ++ for (addr = start, l_offset = 0; addr < (start + (len * 2)); addr += 2) ++ { ++ if ((addr & 0xFF) == 0) ++ { ++ printk(KERN_INFO "BK x%04X :", (addr >> 8)); ++ } ++ if ((addr & 0xF) == 0) ++ { ++ l_offset = 0; ++ snprintf(token_buf, 8, "%02X:", ((0xFF & addr) >> 1)); ++ strcpy(l_buf + l_offset, token_buf); ++ l_offset += strlen(token_buf); ++ } ++ ++ snprintf(token_buf, 8, " %04X", readw((volatile void *)MSTAR_RIU_BASE + (addr << 1))); ++ strcpy(l_buf + l_offset, token_buf); ++ l_offset += strlen(token_buf); ++ ++ if ((addr & 0xF) == 0xE) ++ { ++ printk(KERN_INFO "%s\n", l_buf); ++ } ++ } ++ printk(KERN_INFO "Dump End\n"); ++} ++ ++ ++int MHal_SATA_LoopBack_Test(u8 port_base, u8 gen_num) ++{ ++ u16 u16Temp; ++ u32 GHC_PHY = 0x0; ++ u8 u8Temp; ++ u32 timeout = 0; ++ //u32 GHC_CLK; ++ // unsigned volatile short debreg; ++ //unsigned volatile char debreg_b; ++ int bTestResult = 0; ++ ++ //printk("MHal_SATA_LoopBack_Test: port = %d, gen = %d\n", port_base, gen_num); ++ ++ if((port_base >= 2) || ((gen_num == 0) || (gen_num >= 4))) ++ { ++ printk("Invalid port base(%d) and gen number(%d).\n", port_base, gen_num); ++ return 0; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Enable MAC Clock, bank is chip dependent ++ writew(0x0c0c, (volatile void *)MSTAR_RIU_BASE + (0x100b64 << 1)); // [0] gate ++ ++ ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x10) << 1)); ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x33) << 1) - 1); ++ ++ //Syhtnesizer setup ++ writew(0x0a3d, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ writeb(0x17, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ ++ //TX loopback RX ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x22) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x24) << 1)); ++ ++ // Override speed ++ if(gen_num == 1) // for Gen1 ++ { ++ writeb(0x00, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else if(gen_num == 2) // for Gen2 ++ { ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else // for Gen3 ++ { ++ writeb(0xA0, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ ++ writeb(0x03, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x20) << 1)); ++ ++ writeb(0x8c, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x03) << 1) - 1); ++ writew(0x9103, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0c) << 1)); ++ writeb(0x06, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3e) << 1)); ++ ++ timeout = 0; ++ //Wait TXPLL lock (300us) => Bit 5 = 1 (when lock) ++ // Detection clock is stable or not. 0: No, 1: Yes ++ do ++ { ++ msleep_interruptible(1); // sleep 1 ms ++ u8Temp = readb((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0d) << 1) - 1); ++ } ++ while(((u8Temp & 0x20) == 0) && (timeout++ <= 100)); ++ if(timeout >= 100) ++ { ++ printk("[Port%d][Gen%d]Wait TXPLL lock Time out!!!!!!\n", port_base, gen_num); ++ } ++ ++ //Read TXPLL frequency count => 13'h31c +/- 2, Detection clock count [13:0] ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x1a) << 1)); ++ u16Temp &= 0x3fff; ++ //printk("[Port%d][Gen%d]TXPLL frequency count = 0x%x\n", port_base, gen_num, u16Temp); ++ ++ ++ writeb(0x83, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x7c) << 1)); ++ writew(0x5555, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x34) << 1)); ++ writeb(0x05, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x36) << 1)); ++ writeb(0x00, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x15) << 1) - 1); ++ ++ //Refresh clock stable ++ writeb(0x38, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0f) << 1) - 1); ++ writeb(0x40, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x13) << 1) - 1); ++ writeb(0x88, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x03) << 1) - 1); ++ writew(0x5183, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x32) << 1)); ++ ++ timeout = 0; ++ //Wait RXPLL lock (300us) => Bit 5 (when lock) ++ // Detection clock is stable or not. 0: No, 1: Yes ++ do ++ { ++ msleep_interruptible(1); // sleep 1 ms ++ u8Temp = readb((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0d) << 1) - 1); ++ } ++ while(((u8Temp & 0x20) == 0) && (timeout++ <= 100)); ++ if(timeout >= 100) ++ { ++ printk("[Port%d][Gen%d]Wait RXPLL lock Time out!!!!!!\n", port_base, gen_num); ++ } ++ ++ //Read RXPLL frequency count => 13'h31c +/- 2, Detection clock count [13:0] ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x1a) << 1)); ++ u16Temp &= 0x3fff; ++ //printk("[Port%d][Gen%d]RXPLL frequency count = 0x%x\n", port_base, gen_num, u16Temp); ++ ++ //[4]: Enable PRBS7 pattern ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x13) << 1) - 1); ++ msleep_interruptible(1); // sleep 1 ms ++ ++ //TE: Check Error count valid or not => Bit 5 = 1 or not ++ //If fail bad phase and ignore error count check ++ u8Temp = readb((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x13) << 1) - 1); ++ //printk("[Port%d][Gen%d]RX PRBS7 error count[5] = 0x%x\n", port_base, gen_num, u8Temp); ++ if(u8Temp & 0x20) ++ { ++ bTestResult = 1; ++ printk("================ [Port%d][Gen%d]RX PRBS7 loopback check success ================\n", port_base, gen_num); ++ } ++ else ++ { ++ bTestResult = 0; ++ printk("!!!!!!!!!!!!!!!!!!!! [Port%d][Gen%d]RX PRBS7 loopback check error!!!!!!!!!!!!!!!!!!!!!!\n", port_base, gen_num); ++ } ++ ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x16) << 1)); ++ //printk("[Port%d][Gen%d]RX PRBS7 error count (20b) = 0x%x\n", port_base, gen_num, u16Temp); ++ ++ //HAL_SATA_INFO_dump_Reg((GHC_PHY >> 8), 0, 0x80); ++ ++ return bTestResult; ++} ++EXPORT_SYMBOL_GPL(MHal_SATA_LoopBack_Test); ++ ++int MHal_SATA_Tx_Test_Phy_Initialize(u8 port_base, u8 gen_num) ++{ ++ u32 GHC_PHY = 0x0; ++ u8 u8Temp; ++ u32 timeout = 0; ++ int bTestResult = 0; ++ ++ //printk("[MHal_SATA_Tx_Test_Phy_Initialize]: port = %d, gen = %d\n", port_base, gen_num); ++ ++ if((port_base >= 2) || ((gen_num == 0) || (gen_num >= 4))) ++ { ++ printk("Invalid port base(%d) and gen number(%d).\n", port_base, gen_num); ++ return 0; ++ } ++ ++ // Enable MAC Clock, bank is chip dependent ++ writew(0x0c0c, (volatile void *)MSTAR_RIU_BASE + (0x100b64 << 1)); // [0] gate ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Initial (If initial code is load ready, ignore it) ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x22) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x24) << 1)); ++ writew(0x8104, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0c) << 1)); ++ writew(0x2200, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x10) << 1)); ++ writeb(0x0f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); ++ ++ writew(0x848f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x848e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writeb(0x20, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x19) << 1) - 1); ++ ++ if(gen_num == 1) // for Gen1 ++ { ++ writew(0x9115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); ++ } ++ else if(gen_num == 2) // for Gen2 ++ { ++ writew(0x9114, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); ++ } ++ else // for Gen3 ++ { ++ writew(0x9115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); ++ } ++ ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x33) << 1) - 1); ++ writeb(0x03, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ ++ writew(0xc023, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ writeb(0x03, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x26) << 1)); ++ ++ writew(0x5e03, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ ++ if(gen_num == 1) // for Gen1 ++ { ++ writew(0x0811, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x1115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x1108, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ } ++ else if(gen_num == 2) // for Gen2 ++ { ++ writew(0x0811, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x1115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x1108, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ } ++ else // for Gen3 ++ { ++ writew(0x0811, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x111a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x110a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ } ++ ++ writew(0x1001, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x96) << 1)); ++ writew(0x1108, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2e) << 1)); ++ writew(0x50c0, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x30) << 1)); ++ writeb(0x58, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x43) << 1) - 1); ++ writeb(0x0b, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x7f) << 1) - 1); ++ writew(0x5003, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x32) << 1)); ++ writeb(0x08, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x4d) << 1) - 1); ++ // Initial end ++ ++ // Synthesizer setup ++ writew(0x0aff, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ writeb(0x17, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ ++ ++ writeb(0x03, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x20) << 1)); ++ // Override speed ++ if(gen_num == 1) // for Gen1 ++ { ++ writeb(0x00, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else if(gen_num == 2) // for Gen2 ++ { ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else // for Gen3 ++ { ++ writeb(0xA0, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ ++ writeb(0x3a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0f) << 1) - 1); ++ ++ bTestResult = 1; ++ timeout = 0; ++ //Wait TXPLL lock (300us) => Bit 5 = 1 (when lock) ++ // Detection clock is stable or not. 0: No, 1: Yes ++ do ++ { ++ msleep_interruptible(1); // sleep 1 ms ++ u8Temp = readb((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0d) << 1) - 1); ++ } ++ while(((u8Temp & 0x20) == 0) && (timeout++ <= 100)); ++ if(timeout >= 100) ++ { ++ printk("[Port%d][Gen%d]Wait TXPLL lock Time out!!!!!!\n", port_base, gen_num); ++ return 0; ++ } ++ ++ // Switch to test mode ++ writeb(0xe9, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x7c) << 1)); ++ ++ return bTestResult; ++} ++ ++void MHal_SATA_Tx_Test_SSC(u8 port_base, u8 bEnable) ++{ ++ u32 GHC_PHY = 0x0; ++ ++ if(port_base >= 2) ++ { ++ printk("Invalid port base(%d).\n", port_base); ++ return; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ if(bEnable) ++ { ++ // SSC setup ++ // STEP1[10:0] ++ writew(0x2002, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x64) << 1)); // [12]: 0 Stop sequence mode, 1: Reverse sequence mode ++ // SET[15:0] ++ writew(0x0aff, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ // SET[23:16] ++ writeb(0x17, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ // SPAN[14:0] ++ writew(0x0495, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x66) << 1)); ++ } ++ else ++ { ++ // SSC setup ++ // STEP1[10:0] ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x64) << 1)); // [12]: 0 Stop sequence mode, 1: Reverse sequence mode ++ } ++ ++} ++ ++void MHal_SATA_Tx_Test_Pattern_HFTP(u8 port_base) ++{ ++ u32 GHC_PHY = 0x0; ++ ++ if(port_base >= 2) ++ { ++ printk("Invalid port base(%d).\n", port_base); ++ return; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Program pattern as HFTP ++ writew(0x4a4a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x34) << 1)); ++ writew(0x4a4a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x36) << 1)); ++ writew(0x4a4a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x38) << 1)); ++ writew(0x4a4a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3a) << 1)); ++ ++} ++ ++void MHal_SATA_Tx_Test_Pattern_MFTP(u8 port_base) ++{ ++ u32 GHC_PHY = 0x0; ++ ++ if(port_base >= 2) ++ { ++ printk("Invalid port base(%d).\n", port_base); ++ return; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Program pattern as MFTP ++ writew(0x7878, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x34) << 1)); ++ writew(0x7878, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x36) << 1)); ++ writew(0x7878, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x38) << 1)); ++ writew(0x7878, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3a) << 1)); ++ ++} ++ ++void MHal_SATA_Tx_Test_Pattern_LFTP(u8 port_base) ++{ ++ u32 GHC_PHY = 0x0; ++ ++ if(port_base >= 2) ++ { ++ printk("Invalid port base(%d).\n", port_base); ++ return; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Program pattern as LFTP ++ writew(0x7e7e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x34) << 1)); ++ writew(0x7e7e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x36) << 1)); ++ writew(0x7e7e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x38) << 1)); ++ writew(0x7e7e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3a) << 1)); ++ ++} ++ ++void MHal_SATA_Tx_Test_Pattern_LBP(u8 port_base) ++{ ++ u32 GHC_PHY = 0x0; ++ ++ if(port_base >= 2) ++ { ++ printk("Invalid port base(%d).\n", port_base); ++ return; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Program pattern as LBP ++ writew(0x8b0c, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x34) << 1)); ++ writew(0x6b0c, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x36) << 1)); ++ writew(0x8b0c, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x38) << 1)); ++ writew(0x6b0c, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3a) << 1)); ++ ++} ++ ++void MHal_SATA_Tx_Test_Pattern_SSOP(u8 port_base) ++{ ++ u32 GHC_PHY = 0x0; ++ ++ if(port_base >= 2) ++ { ++ printk("Invalid port base(%d).\n", port_base); ++ return; ++ } ++ ++ if(port_base == 0) ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ else if(port_base == 1) ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ ++ // Program pattern as SSOP ++ writew(0x7f7f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x34) << 1)); ++ writew(0x7f7f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x36) << 1)); ++ writew(0x7f7f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x38) << 1)); ++ writew(0x7f7f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3a) << 1)); ++ ++} +diff --git a/drivers/sstar/sata_host/bench_test/drv/mhal_sata_bench_test.h b/drivers/sstar/sata_host/bench_test/drv/mhal_sata_bench_test.h +new file mode 100755 +index 000000000000..e7e2c729d47f +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/drv/mhal_sata_bench_test.h +@@ -0,0 +1,284 @@ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// * Copyright (c) 2006 - 2007 MStar Semiconductor, Inc. ++// This program is free software. ++// You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; ++// either version 2 of the License, or (at your option) any later version. ++// ++// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; ++// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++// See the GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License along with this program; ++// if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file mhal_sata_host.h ++/// @author MStar Semiconductor Inc. ++/// @brief SATA Host HAL Driver ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MHAL_SATA_HOST_H_ ++#define _MHAL_SATA_HOST_H_ ++ ++#if defined(CONFIG_ARM64) ++ extern ptrdiff_t mstar_pm_base; ++ #define MSTAR_RIU_BASE mstar_pm_base ++#else ++ //#define MSTAR_RIU_BASE 0xBF200000 ++ //#define MSTAR_RIU_BASE 0x1F000000 ++ //#define MSTAR_RIU_BASE 0x1F000000 //JFY ++ #define MSTAR_RIU_BASE 0xFD000000 //JFY ++#endif ++ ++#define SATA_PORT_BASE_0 0x100000 ++#define SATA_PORT_BASE_1 0x110000 ++ ++#define SATA_GHC_0 0x102B00 ++#define SATA_GHC_0_P0 0x102C00 ++#define SATA_GHC_0_MISC 0x102D00 ++#define SATA_GHC_0_MIUPORT 0x103700 ++#define SATA_GHC_0_PHY 0x103900 ++ ++#define SATA_GHC_1 0x113100 ++#define SATA_GHC_1_P0 0x113200 ++#define SATA_GHC_1_MISC 0x113300 ++#define SATA_GHC_1_MIUPORT 0x113800 ++#define SATA_GHC_1_PHY 0x162A00//0x113900 ++/* ++u32 virtAddr(u32 addr){ ++ addr=MSTAR_RIU_BASE+addr<<9; ++ return (u32)ioremap(addr,0x200); ++} ++*/ ++/* ++#define SATA_GHC_0_ADDRESS_START ioremap(MSTAR_RIU_BASE + (0x102B << 9),512) ++#define SATA_GHC_0_ADDRESS_END SATA_GHC_0_ADDRESS_START+0xFE ++#define SATA_GHC_0_P0_ADDRESS_START (MSTAR_RIU_BASE + (0x113200 << 1)) ++#define SATA_GHC_0_P0_ADDRESS_END (MSTAR_RIU_BASE + (0x1132FE << 1)) ++#define SATA_MISC_0_ADDRESS_START (MSTAR_RIU_BASE + (0x113300 << 1)) ++#define SATA_MISC_0_ADDRESS_END (MSTAR_RIU_BASE + (0x1133FE << 1)) ++*/ ++/* ++u32 SATA_GHC_0_ADDRESS_START=(u32)virtAddr(0x102B);//(MSTAR_RIU_BASE + (0x102B00 << 1))//0xFD000000 ++u32 SATA_GHC_0_ADDRESS_END=SATA_GHC_0_ADDRESS_START+0xFE;//(MSTAR_RIU_BASE + (0x102BFE << 1)) ++u32 SATA_GHC_0_P0_ADDRESS_START=virtAddr(MSTAR_RIU_BASE+0x102C<<9);//(MSTAR_RIU_BASE + (0x102C00 << 1)) ++u32 SATA_GHC_0_P0_ADDRESS_END=SATA_GHC_0_P0_ADDRESS_START+0xFE;//(MSTAR_RIU_BASE + (0x102CFE << 1)) ++u32 SATA_MISC_0_ADDRESS_START=virtAddr(MSTAR_RIU_BASE+0x102D<<9);//(MSTAR_RIU_BASE + (0x102D00 << 1)) ++u32 SATA_MISC_0_ADDRESS_END=SATA_MISC_0_ADDRESS_START+0xFE;//(MSTAR_RIU_BASE + (0x102DFE << 1)) ++ ++ ++ ++*/ ++ ++#define SATA_GHC_0_ADDRESS_START (MSTAR_RIU_BASE + (0x102B00 << 1)) ++#define SATA_GHC_0_ADDRESS_END (MSTAR_RIU_BASE + (0x102BFE << 1)) ++#define SATA_GHC_0_P0_ADDRESS_START (MSTAR_RIU_BASE + (0x102C00 << 1)) ++#define SATA_GHC_0_P0_ADDRESS_END (MSTAR_RIU_BASE + (0x102CFE << 1)) ++#define SATA_MISC_0_ADDRESS_START (MSTAR_RIU_BASE + (0x102D00 << 1)) ++#define SATA_MISC_0_ADDRESS_END (MSTAR_RIU_BASE + (0x102DFE << 1)) ++ ++ ++#define SATA_GHC_1_ADDRESS_START (MSTAR_RIU_BASE + (0x113100 << 1)) ++#define SATA_GHC_1_ADDRESS_END (MSTAR_RIU_BASE + (0x1131FE << 1)) ++#define SATA_GHC_1_P0_ADDRESS_START (MSTAR_RIU_BASE + (0x113200 << 1)) ++#define SATA_GHC_1_P0_ADDRESS_END (MSTAR_RIU_BASE + (0x1132FE << 1)) ++#define SATA_MISC_1_ADDRESS_START (MSTAR_RIU_BASE + (0x113300 << 1)) ++#define SATA_MISC_1_ADDRESS_END (MSTAR_RIU_BASE + (0x1133FE << 1)) ++ ++/* ++#define SATA_GHC_0_ADDRESS_START (0xFD000000 + (0x102B00 << 1)) ++#define SATA_GHC_0_ADDRESS_END (0xFD000000 + (0x102BFE << 1)) ++#define SATA_GHC_1_ADDRESS_START (0xFD000000 + (0x102C00 << 1)) ++#define SATA_GHC_1_ADDRESS_END (0xFD000000 + (0x102CFE << 1)) ++#define SATA_MISC_ADDRESS_START (0xFD000000 + (0x102D00 << 1)) ++#define SATA_MISC_ADDRESS_END (0xFD000000 + (0x102DFE << 1)) ++*/ ++ ++// FIXME: Needs to be removed since K6 does not support XIU mode. ++#if defined(CONFIG_ARM64) ++ #define SATA_SDMAP_RIU_BASE mstar_pm_base ++#else ++ #define SATA_SDMAP_RIU_BASE MSTAR_RIU_BASE //0xFD000000 ++#endif ++ ++// MIU interval, the gap between MIU0 and MIU1, chip dependent ++#define MIU_INTERVAL_SATA 0x60000000 // for K6 ++ ++// Local Definition, internal SATA MAC SRAM address ++#define AHCI_P0CLB 0x18001000 ++#define AHCI_P0FB 0x18001100 ++#define AHCI_CTBA0 0x18001200 ++ ++#define SATA_PORT_NUM 1 ++#define SATA_CMD_HEADER_SIZE 0x400 ++#define SATA_FIS_SIZE 0x100 ++ ++enum ++{ ++ /* global controller registers */ ++ MS_HOST_CAP = 0x00, /* host capabilities */ ++ MS_HOST_CTL = (0x04 << 1), /* global host control */ ++ MS_HOST_IRQ_STAT = (0x08 << 1), /* interrupt status */ ++ MS_HOST_PORTS_IMPL = (0x0c << 1), /* bitmap of implemented ports */ ++ MS_HOST_VERSION = (0x10 << 1), /* AHCI spec. version compliancy */ ++ MS_HOST_CAP2 = (0x24 << 1), /* host capabilities, extended */ ++ ++ /* HOST_CTL bits - HOST_CAP, 0x00 */ ++ //MS_HOST_RESET = (1 << 0), /* reset controller; self-clear */ ++ //MS_HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ ++ // MS_HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ ++ ++ /* Registers for each SATA port */ ++ MS_PORT_LST_ADDR = 0x00, /* command list DMA addr */ ++ MS_PORT_LST_ADDR_HI = (0x04 << 1), /* command list DMA addr hi */ ++ MS_PORT_FIS_ADDR = (0x08 << 1), /* FIS rx buf addr */ ++ MS_PORT_FIS_ADDR_HI = (0x0c << 1), /* FIS rx buf addr hi */ ++ MS_PORT_IRQ_STAT = (0x10 << 1), /* interrupt status */ ++ MS_PORT_IRQ_MASK = (0x14 << 1), /* interrupt enable/disable mask */ ++ MS_PORT_CMD = (0x18 << 1), /* port command */ ++ MS_PORT_TFDATA = (0x20 << 1), /* taskfile data */ ++ MS_PORT_SIG = (0x24 << 1), /* device TF signature */ ++ MS_PORT_SCR_STAT = (0x28 << 1), /* SATA phy register: SStatus */ ++ MS_PORT_SCR_CTL = (0x2c << 1), /* SATA phy register: SControl */ ++ MS_PORT_SCR_ERR = (0x30 << 1), /* SATA phy register: SError */ ++ MS_PORT_SCR_ACT = (0x34 << 1), /* SATA phy register: SActive */ ++ MS_PORT_CMD_ISSUE = (0x38 << 1), /* command issue */ ++ MS_PORT_SCR_NTF = (0x3c << 1), /* SATA phy register: SNotification */ ++ MS_PORT_DMA_CTRL = (0x70 << 1), /* SATA phy register: SNotification */ ++ ++ /* PORT_CMD bits */ ++ MS_PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ ++ MS_PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ ++ MS_PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ ++ MS_PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ ++ MS_PORT_CMD_PMP = (1 << 17), /* PMP attached */ ++ MS_PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ ++ MS_PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ ++ MS_PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ ++ MS_PORT_CMD_CLO = (1 << 3), /* Command list override */ ++ MS_PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ ++ MS_PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ ++ MS_PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ ++ ++ MS_PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ ++ MS_PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ ++ MS_PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ ++ MS_PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ ++ ++ /* Status Error */ ++ MS_AHCI_PORT_SERR_RDIE = (1 << 0), /* Recovered Data Integrity Error */ ++ MS_AHCI_PORT_SERR_RCE = (1 << 1), /* Recovered Communications Error */ ++ /* Bit 2 ~ 7 Reserved */ ++ MS_AHCI_PORT_SERR_TDIE = (1 << 8), /* Transient Data Integrity Error */ ++ MS_AHCI_PORT_SERR_PCDIE = (1 << 9), /* Persistent Communication or Data Integrity Error */ ++ MS_AHCI_PORT_SERR_PE = (1 << 10), /* Protocol Error */ ++ MS_AHCI_PORT_SERR_IE = (1 << 11), /* Internal Error */ ++ /* Bit 15 ~ 12 Reserved */ ++ MS_AHCI_PORT_SERR_PRDYC = (1 << 16), /* PhyRdy Change */ ++ MS_AHCI_PORT_SERR_PIE = (1 << 17), /* Phy Internal Error */ ++ MS_AHCI_PORT_SERR_COMW = (1 << 18), /* Comm Wake Detect */ ++ MS_AHCI_PORT_SERR_TDE = (1 << 19), /* 10B to 8B Decode Error */ ++ MS_AHCI_PORT_SERR_DE = (1 << 20), /* Disparity Error <= Not Use by AHCI */ ++ MS_AHCI_PORT_SERR_CRCE = (1 << 21), /* CRC Error */ ++ MS_AHCI_PORT_SERR_HE = (1 << 22), /* Handshake Error */ ++ MS_AHCI_PORT_SERR_LSE = (1 << 23), /* Link Sequence Error */ ++ MS_AHCI_PORT_SERR_TSTE = (1 << 24), /* Transport state transition error */ ++ MS_AHCI_PORT_SERR_UFIS = (1 << 25), /* Unknown FIS Type */ ++ MS_AHCI_PORT_SERR_EXC = (1 << 26), /* Exchanged : a change in device presence has been detected */ ++ /* Bit 31 ~ 27 Reserved */ ++}; ++ ++enum ++{ ++ E_PORT_SPEED_MASK = (0xF << 4), ++ E_PORT_SPEED_NO_RESTRICTION = (0x0 < 4), ++ E_PORT_SPEED_GEN1 = (0x1 << 4), ++ E_PORT_SPEED_GEN2 = (0x2 << 4), ++ E_PORT_SPEED_GEN3 = (0x3 << 4), ++ ++ E_PORT_DET_MASK = (0xF << 0), //Device Detection Initialization ++ E_PORT_DET_NODEVICE_DETECT = 0x0, ++ E_PORT_DET_HW_RESET = 0x1, // Cause HW send initial sequence ++ E_PORT_DET_DISABLE_PHY = 0x4, // Put PHY into Offline ++ E_PORT_DET_DEVICE_NOEST = 0x1, // not established ++ E_PORT_DET_DEVICE_EST = 0x3, // established ++ E_PORT_DET_PHY_OFFLINE = 0x4, // Put PHY into Offline ++ ++ DATA_COMPLETE_INTERRUPT = (1 << 31), ++ ++ /* PORT_IRQ_{STAT,MASK} bits */ ++ //PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ ++ //PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ ++ //PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ ++ //PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ ++ //PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ ++ //PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ ++ //PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ ++ //PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ ++ ++ //PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ ++ //PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ ++ //PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ ++ //PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ ++ //PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ ++ //PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ ++ //PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ ++ //PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ ++ //PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ ++ ++ //PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | ++ // PORT_IRQ_IF_ERR | ++ // PORT_IRQ_CONNECT | ++ // PORT_IRQ_PHYRDY | ++ // PORT_IRQ_UNK_FIS | ++ // PORT_IRQ_BAD_PMP, ++ //PORT_IRQ_ERROR = PORT_IRQ_FREEZE | ++ // PORT_IRQ_TF_ERR | ++ // PORT_IRQ_HBUS_DATA_ERR, ++ //DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | ++ // PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | ++ // PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, ++}; ++ ++/* ++ * Host Controller MISC Register ++ */ ++enum ++{ ++ SATA_MISC_CFIFO_ADDRL = ((0x10 << 1 ) << 1), ++ SATA_MISC_CFIFO_ADDRH = ((0x11 << 1 ) << 1), ++ SATA_MISC_CFIFO_WDATAL = ((0x12 << 1 ) << 1), ++ SATA_MISC_CFIFO_WDATAH = ((0x13 << 1 ) << 1), ++ SATA_MISC_CFIFO_RDATAL = ((0x14 << 1 ) << 1), ++ SATA_MISC_CFIFO_RDATAH = ((0x15 << 1 ) << 1), ++ SATA_MISC_CFIFO_RORW = ((0x16 << 1 ) << 1), ++ SATA_MISC_CFIFO_ACCESS = ((0x17 << 1 ) << 1), ++ SATA_MISC_ACCESS_MODE = ((0x18 << 1 ) << 1), ++ SATA_MISC_AMBA_MUXRST = ((0x21 << 1 ) << 1), ++ SATA_MISC_HBA_LADDR = ((0x24 << 1 ) << 1), ++ SATA_MISC_HBA_HADDR = ((0x25 << 1 ) << 1), ++ SATA_MISC_CMD_LADDR = ((0x26 << 1 ) << 1), ++ SATA_MISC_CMD_HADDR = ((0x27 << 1 ) << 1), ++ SATA_MISC_DATA_ADDR = ((0x28 << 1 ) << 1), ++ SATA_MISC_ENRELOAD = ((0x29 << 1 ) << 1), ++ SATA_MISC_AMBA_ARBIT = ((0x2A << 1 ) << 1), ++ SATA_MISC_AMBA_PGEN = ((0x30 << 1 ) << 1), ++ SATA_MISC_AGEN_F_VAL = ((0x35 << 1 ) << 1), ++ SATA_MISC_HOST_SWRST = ((0x50 << 1 ) << 1), ++ SATA_MISC_HOST_NEAR = ((0x51 << 1 ) << 1), ++ SATA_MISC_FPGA_EN = ((0x55 << 1 ) << 1), ++}; ++ ++int MHal_SATA_LoopBack_Test(u8 port_base, u8 gen_num); ++int MHal_SATA_Tx_Test_Phy_Initialize(u8 port_base, u8 gen_num); ++void MHal_SATA_Tx_Test_SSC(u8 port_base, u8 bEnable); ++void MHal_SATA_Tx_Test_Pattern_HFTP(u8 port_base); ++void MHal_SATA_Tx_Test_Pattern_MFTP(u8 port_base); ++void MHal_SATA_Tx_Test_Pattern_LFTP(u8 port_base); ++void MHal_SATA_Tx_Test_Pattern_LBP(u8 port_base); ++void MHal_SATA_Tx_Test_Pattern_SSOP(u8 port_base); ++#endif +diff --git a/drivers/sstar/sata_host/bench_test/include/mdrv_sata_io.h b/drivers/sstar/sata_host/bench_test/include/mdrv_sata_io.h +new file mode 100755 +index 000000000000..86ca4198905f +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/include/mdrv_sata_io.h +@@ -0,0 +1,68 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_SATA_IO_H ++#define _MDRV_SATA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_SATA_LIB_CODE {'S','A','T','\0'} ++#define MSIF_SATA_BUILDNUM {'_','0','1','\0'} ++#define MSIF_SATA_LIBVER (2) ++#define MSIF_SATA_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++ ++#define IOCTL_SATA_SET_LOOPBACK_TEST_NR (0) ++#define IOCTL_SATA_SET_CONFIG_NR (1) ++#define IOCTL_SATA_GET_INTERRUPT_STATUS_NR (2) ++#define IOCTL_SATA_SET_TX_TEST_HFTP_NR (3) ++#define IOCTL_SATA_SET_TX_TEST_MFTP_NR (4) ++#define IOCTL_SATA_SET_TX_TEST_LFTP_NR (5) ++#define IOCTL_SATA_SET_TX_TEST_LBP_NR (6) ++#define IOCTL_SATA_SET_TX_TEST_SSOP_NR (7) ++ ++#define IOCTL_SATA_MAX_NR (8) ++ ++ ++// use 'm' as magic number ++#define IOCTL_SATA_MAGIC ('3') ++ ++ ++#define IOCTL_SATA_SET_LOOPBACK_TEST _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_LOOPBACK_TEST_NR) ++#define IOCTL_SATA_SET_CONFIG _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_CONFIG_NR) ++#define IOCTL_SATA_GET_INTERRUPT_STATUS _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_GET_INTERRUPT_STATUS_NR) ++#define IOCTL_SATA_SET_TX_TEST_HFTP _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_TX_TEST_HFTP_NR) ++#define IOCTL_SATA_SET_TX_TEST_MFTP _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_TX_TEST_MFTP_NR) ++#define IOCTL_SATA_SET_TX_TEST_LFTP _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_TX_TEST_LFTP_NR) ++#define IOCTL_SATA_SET_TX_TEST_LBP _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_TX_TEST_LBP_NR) ++#define IOCTL_SATA_SET_TX_TEST_SSOP _IO(IOCTL_SATA_MAGIC, IOCTL_SATA_SET_TX_TEST_SSOP_NR) ++ ++ ++#endif //_MDRV_GFLIP_IO_H +diff --git a/drivers/sstar/sata_host/bench_test/include/mdrv_sata_io_st.h b/drivers/sstar/sata_host/bench_test/include/mdrv_sata_io_st.h +new file mode 100755 +index 000000000000..577286bd2b9a +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/include/mdrv_sata_io_st.h +@@ -0,0 +1,66 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sata_io_st.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_SATA_IO_ST_H ++#define _MDRV_SATA_IO_ST_H ++ ++//============================================================================= ++// enum ++//============================================================================= ++ ++//============================================================================= ++// struct ++//============================================================================= ++typedef struct ++{ ++ unsigned short u16PortNo; ++ unsigned short u16GenNo; ++ int s32Result; ++} stSata_Loopback_Test, *pstSata_Loopback_Test; ++ ++typedef struct ++{ ++ unsigned short u16PortNo; ++ unsigned short u16GenNo; ++ unsigned int u32SSCEnable; ++ int s32Result; ++} stSata_Tx_Test, *pstSata_Tx_Test; ++ ++typedef struct ++{ ++ unsigned short x; ++ unsigned short y; /// ++#include "ms_platform.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++ ++ ++#define FUNC_MSG(fmt, args...) ({do{printf(ASCII_COLOR_END"%s[%d] ",__FUNCTION__,__LINE__);printf(fmt, ##args);printf(ASCII_COLOR_END);}while(0);}) ++#define FUNC_ERR(fmt, args...) ({do{printf(ASCII_COLOR_RED"%s[%d] ",__FUNCTION__,__LINE__);printf(fmt, ##args);printf(ASCII_COLOR_END);}while(0);}) ++ ++#define DIP_DEBUG 0 ++ ++#if (DIP_DEBUG==1) ++ #define DIPDBG(fmt, args...) printf(fmt, ## args) ++#else ++ #define DIPDBG(fmt, args...) ++#endif ++ ++//#define DIPIO_DEBUG_ENABLE ++ ++#define DIP_DBG_LV_IOCTL 1 ++#define DIP_DBG_LV_0 1 ++ ++ ++#ifdef DIPIO_DEBUG_ENABLE ++#define DIPIO_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++/* ++#define DIP_DBG(dbglv, _fmt, args...) \ ++ do{\ ++ printk(KERN_INFO _fmt, ##args);\ ++ } while(0) ++*/ ++//#define DIP_DBG(dbglv, fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define DIP_DBG(dbglv, _fmt, _args...) printk(KERN_DEBUG fmt, ##arg) ++ ++#else ++#define DIPIO_ASSERT(arg) ++#define DIP_DBG(dbglv, _fmt, _args...) ++ ++#endif +diff --git a/drivers/sstar/sata_host/bench_test/mdrv_sata_io.c b/drivers/sstar/sata_host/bench_test/mdrv_sata_io.c +new file mode 100755 +index 000000000000..4e04c0a4de71 +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/mdrv_sata_io.c +@@ -0,0 +1,536 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "irqs.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++ ++#include "mdrv_sata.h" ++#include "mdrv_sata_io_st.h" ++#include "mdrv_sata_io.h" ++//#include "MsTypes.h" ++#include "mhal_sata_bench_test.h" ++ ++int debug_level; ++module_param(debug_level, int, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(debug_level, "\nLevels:\n" ++ " [1] Debug level 1\n" ++ " [2] Debug level 2\n" ++ " [3] Debug level 3\n" ++ " [4] Debug level 4"); ++ ++#define MDRV_SATA_DEVICE_COUNT 1 ++#define MDRV_SATA_NAME "msata" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SATA "msata" ++#define MDRV_MAJOR_SATA 0xea ++#define MDRV_MINOR_SATA 0x09 ++ ++#define CMD_PARSING(x) (x==IOCTL_SATA_SET_LOOPBACK_TEST ? "IOCTL_SATA_SET_LOOPBACK_TEST" : \ ++ x==IOCTL_SATA_SET_CONFIG ? "IOCTL_SATA_SET_CONFIG" : \ ++ x==IOCTL_SATA_GET_INTERRUPT_STATUS ? "IOCTL_SATA_GET_INTERRUPT_STATUS" : \ ++ "unknown") ++ ++int sstar_sata_drv_open(struct inode *inode, struct file *filp); ++int sstar_sata_drv_release(struct inode *inode, struct file *filp); ++long sstar_sata_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int sstar_sata_drv_probe(struct platform_device *pdev); ++static int sstar_sata_drv_remove(struct platform_device *pdev); ++static int sstar_sata_drv_suspend(struct platform_device *dev, pm_message_t state); ++static int sstar_sata_drv_resume(struct platform_device *dev); ++static void sstar_sata_drv_platfrom_release(struct device *device); ++static unsigned int sstar_sata_drv_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++} SATA_DEV; ++ ++static SATA_DEV _devSATA = ++{ ++ .s32Major = MDRV_MAJOR_SATA, ++ .s32Minor = MDRV_MINOR_SATA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name = MDRV_NAME_SATA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = sstar_sata_drv_open, ++ .release = sstar_sata_drv_release, ++ .unlocked_ioctl = sstar_sata_drv_ioctl, ++ .poll = sstar_sata_drv_poll, ++ } ++}; ++ ++static struct class * sata_class; ++static char * sata_classname = "sstar_sata_class"; ++ ++static struct platform_driver Sstar_sata_driver = ++{ ++ .probe = sstar_sata_drv_probe, ++ .remove = sstar_sata_drv_remove, ++ .suspend = sstar_sata_drv_suspend, ++ .resume = sstar_sata_drv_resume, ++ ++ .driver = { ++ .name = "msata", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static u64 sg_sstar_device_sata_dmamask = 0xffffffffUL; ++ ++static struct platform_device sg_mdrv_sata_device = ++{ ++ .name = "msata", ++ .id = 0, ++ .dev = ++ { ++ .release = sstar_sata_drv_platfrom_release, ++ .dma_mask = &sg_sstar_device_sata_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//---------------------------------------------------------------------------------------------- ++ ++int _MDrv_SATAIO_IOC_Set_LoopbackTest(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ stSata_Loopback_Test stCfg; ++ int result = 0; ++ if(copy_from_user(&stCfg, (stSata_Loopback_Test __user *)arg, sizeof(stSata_Loopback_Test))) ++ { ++ printk("SATA FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ //printk("[%s][%d] Port = %d, Gen = %d\n", __func__, __LINE__, stCfg.u16PortNo, stCfg.u16GenNo); ++ result = (int)MHal_SATA_LoopBack_Test((u8)stCfg.u16PortNo, (u8)stCfg.u16GenNo); ++ stCfg.s32Result = result; ++ ++ if (copy_to_user((stSata_Loopback_Test __user *)arg, &stCfg, sizeof(stSata_Loopback_Test))) ++ { ++ printk("SATA FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int _MDrv_SATAIO_IOC_Set_SATA_Config(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ return ret; ++} ++ ++int _MDrv_SATAIO_IO_Get_Interrupt_Status(struct file *filp, unsigned long arg) ++{ ++ //SATA_INTR_STATUS stIntrStatus; ++ ++ return 0; ++} ++ ++int _MDrv_SATAIO_IOC_Set_TxTest_HFTP(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ stSata_Tx_Test stCfg; ++ int result = 0; ++ if(copy_from_user(&stCfg, (stSata_Tx_Test __user *)arg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST HFTP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ //printk("[%s][%d] Port = %d, Gen = %d\n", __func__, __LINE__, stCfg.u16PortNo, stCfg.u16GenNo); ++ result = (int)MHal_SATA_Tx_Test_Phy_Initialize((u8)stCfg.u16PortNo, (u8)stCfg.u16GenNo); ++ stCfg.s32Result = result; ++ MHal_SATA_Tx_Test_Pattern_HFTP((u8)stCfg.u16PortNo); ++ MHal_SATA_Tx_Test_SSC((u8)stCfg.u16PortNo, (u8)stCfg.u32SSCEnable); ++ ++ if (copy_to_user((stSata_Tx_Test __user *)arg, &stCfg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST HFTP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int _MDrv_SATAIO_IOC_Set_TxTest_MFTP(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ stSata_Tx_Test stCfg; ++ int result = 0; ++ if(copy_from_user(&stCfg, (stSata_Tx_Test __user *)arg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST MFTP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ result = (int)MHal_SATA_Tx_Test_Phy_Initialize((u8)stCfg.u16PortNo, (u8)stCfg.u16GenNo); ++ stCfg.s32Result = result; ++ MHal_SATA_Tx_Test_Pattern_MFTP((u8)stCfg.u16PortNo); ++ MHal_SATA_Tx_Test_SSC((u8)stCfg.u16PortNo, (u8)stCfg.u32SSCEnable); ++ ++ if (copy_to_user((stSata_Tx_Test __user *)arg, &stCfg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST MFTP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int _MDrv_SATAIO_IOC_Set_TxTest_LFTP(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ stSata_Tx_Test stCfg; ++ int result = 0; ++ if(copy_from_user(&stCfg, (stSata_Tx_Test __user *)arg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST LFTP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ result = (int)MHal_SATA_Tx_Test_Phy_Initialize((u8)stCfg.u16PortNo, (u8)stCfg.u16GenNo); ++ stCfg.s32Result = result; ++ MHal_SATA_Tx_Test_Pattern_LFTP((u8)stCfg.u16PortNo); ++ MHal_SATA_Tx_Test_SSC((u8)stCfg.u16PortNo, (u8)stCfg.u32SSCEnable); ++ ++ if (copy_to_user((stSata_Tx_Test __user *)arg, &stCfg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST LFTP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int _MDrv_SATAIO_IOC_Set_TxTest_LBP(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ stSata_Tx_Test stCfg; ++ int result = 0; ++ if(copy_from_user(&stCfg, (stSata_Tx_Test __user *)arg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST LBP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ result = (int)MHal_SATA_Tx_Test_Phy_Initialize((u8)stCfg.u16PortNo, (u8)stCfg.u16GenNo); ++ stCfg.s32Result = result; ++ MHal_SATA_Tx_Test_Pattern_LBP((u8)stCfg.u16PortNo); ++ MHal_SATA_Tx_Test_SSC((u8)stCfg.u16PortNo, (u8)stCfg.u32SSCEnable); ++ ++ if (copy_to_user((stSata_Tx_Test __user *)arg, &stCfg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST LBP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int _MDrv_SATAIO_IOC_Set_TxTest_SSOP(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ stSata_Tx_Test stCfg; ++ int result = 0; ++ if(copy_from_user(&stCfg, (stSata_Tx_Test __user *)arg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST SSOP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ result = (int)MHal_SATA_Tx_Test_Phy_Initialize((u8)stCfg.u16PortNo, (u8)stCfg.u16GenNo); ++ stCfg.s32Result = result; ++ MHal_SATA_Tx_Test_Pattern_SSOP((u8)stCfg.u16PortNo); ++ MHal_SATA_Tx_Test_SSC((u8)stCfg.u16PortNo, (u8)stCfg.u32SSCEnable); ++ ++ if (copy_to_user((stSata_Tx_Test __user *)arg, &stCfg, sizeof(stSata_Tx_Test))) ++ { ++ printk("SATA SET TX TEST SSOP FAIL %d ...\n", __LINE__); ++ return -EFAULT; ++ } ++ ++ return ret; ++} ++ ++//============================================================================== ++long sstar_sata_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ // int err = 0; ++ int retval = 0; ++ ++ if(_devSATA.refCnt <= 0) ++ { ++ printk("[SATA] SATAIO_IOCTL refCnt =%d!!! \n", _devSATA.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SATA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SATA_MAX_NR) ++ { ++ printk("[SATA] IOCtl NR Error!!! (Cmd=%x)\n", u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ printk("[SATA] IOCtl MAGIC Error!!! (Cmd=%x)\n", u32Cmd); ++ return -ENOTTY; ++ } ++#if 0 ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++#endif ++ ++ /* not allow query or command once driver suspend */ ++ ++ //printk("[SATA] IOCTL: ==%s==\n", (CMD_PARSING(u32Cmd))); ++ //printk("[SATA] === SATAIO_IOCTL %d === \n", (u32Cmd)); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SATA_SET_LOOPBACK_TEST: ++ retval = _MDrv_SATAIO_IOC_Set_LoopbackTest(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_SET_CONFIG: ++ retval = _MDrv_SATAIO_IOC_Set_SATA_Config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_GET_INTERRUPT_STATUS: ++ retval = _MDrv_SATAIO_IO_Get_Interrupt_Status(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_SET_TX_TEST_HFTP: ++ retval = _MDrv_SATAIO_IOC_Set_TxTest_HFTP(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_SET_TX_TEST_MFTP: ++ retval = _MDrv_SATAIO_IOC_Set_TxTest_MFTP(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_SET_TX_TEST_LFTP: ++ retval = _MDrv_SATAIO_IOC_Set_TxTest_LFTP(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_SET_TX_TEST_LBP: ++ retval = _MDrv_SATAIO_IOC_Set_TxTest_LBP(filp, u32Arg); ++ break; ++ ++ case IOCTL_SATA_SET_TX_TEST_SSOP: ++ retval = _MDrv_SATAIO_IOC_Set_TxTest_SSOP(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ printk("[SATA] ERROR IOCtl number %x\n ", u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int sstar_sata_drv_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++#if 0 ++ if (atomic_read(&SATAW_intr_count) > 0) ++ { ++ atomic_set(&SATAW_intr_count, 0); ++ return POLLIN | POLLRDNORM; /* readable */ ++ } ++#endif ++ return 0; ++} ++ ++static int sstar_sata_drv_probe(struct platform_device *pdev) ++{ ++ printk("[SATA] sstar_sata_drv_probe\n"); ++ ++ return 0; ++} ++ ++static int sstar_sata_drv_remove(struct platform_device *pdev) ++{ ++ printk("[SATA] sstar_sata_drv_remove\n"); ++ ++ return 0; ++} ++ ++static int sstar_sata_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ printk("[SATA] sstar_sata_drv_suspend\n"); ++ ++ return 0; ++} ++ ++static int sstar_sata_drv_resume(struct platform_device *dev) ++{ ++ printk("[SATA] sstar_sata_drv_resume\n"); ++ ++ return 0; ++} ++ ++static void sstar_sata_drv_platfrom_release(struct device *device) ++{ ++ printk("[SATA] sstar_sata_drv_platfrom_release\n"); ++} ++ ++int sstar_sata_drv_open(struct inode *inode, struct file *filp) ++{ ++ //printk("[SATA] SATA DRIVER OPEN\n"); ++ ++ _devSATA.refCnt++; ++ ++ //printk("[SATA] Open refCnt = %d\n", _devSATA.refCnt); ++ ++ return 0; ++} ++ ++int sstar_sata_drv_release(struct inode *inode, struct file *filp) ++{ ++ //printk("[SATA] SATA DRIVER RELEASE\n"); ++ _devSATA.refCnt--; ++ ++ // free_irq(INT_IRQ_SATAW, MDrv_SATAW_isr); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_SATAIO_ModuleInit(void) ++{ ++ int ret = 0; ++ dev_t dev; ++ int s32Ret; ++ printk("[SATAIO]_Init \n"); ++ ++ if(_devSATA.s32Major) ++ { ++ dev = MKDEV(_devSATA.s32Major, _devSATA.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_SATA_DEVICE_COUNT, MDRV_SATA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _devSATA.s32Minor, MDRV_SATA_DEVICE_COUNT, MDRV_SATA_NAME); ++ _devSATA.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ printk("[SATA] Unable to get major %d\n", _devSATA.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_devSATA.cdev, &_devSATA.fops); ++ if (0 != (s32Ret = cdev_add(&_devSATA.cdev, dev, MDRV_SATA_DEVICE_COUNT))) ++ { ++ printk("[SATA] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_SATA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ sata_class = class_create(THIS_MODULE, sata_classname); ++ if(IS_ERR(sata_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(sata_class, NULL, dev, NULL, "msata"); ++ } ++ /* initial the whole SATA Driver */ ++ ret = platform_driver_register(&Sstar_sata_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&sg_mdrv_sata_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&Sstar_sata_driver); ++ printk("[SATA] register failed\n"); ++ ++ } ++ else ++ { ++ printk("[SATA] register success\n"); ++ } ++ } ++ ++ return ret; ++} ++ ++ ++void _MDrv_SATAIO_ModuleExit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ printk("[SATAIO]_Exit \n"); ++ cdev_del(&_devSATA.cdev); ++ device_destroy(sata_class, MKDEV(_devSATA.s32Major, _devSATA.s32Minor)); ++ class_destroy(sata_class); ++ unregister_chrdev_region(MKDEV(_devSATA.s32Major, _devSATA.s32Minor), MDRV_SATA_DEVICE_COUNT); ++ platform_device_unregister(&sg_mdrv_sata_device); ++ platform_driver_unregister(&Sstar_sata_driver); ++} ++ ++module_init(_MDrv_SATAIO_ModuleInit); ++module_exit(_MDrv_SATAIO_ModuleExit); ++ ++MODULE_AUTHOR("SIGMASTAR"); ++MODULE_DESCRIPTION("SATA Bench test driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/sata_host/bench_test/verify/Makefile b/drivers/sstar/sata_host/bench_test/verify/Makefile +new file mode 100755 +index 000000000000..5378ad37a2fe +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/verify/Makefile +@@ -0,0 +1,12 @@ ++export CROSS_COMPILE=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++ ++INCLUDES := -I../include/ ++ ++TARGET := sata_test ++ ++all: ++ $(CC) -o $(TARGET) $(TARGET).c $(INCLUDES) ++ ++clean: ++ rm -rf $(TARGET) +diff --git a/drivers/sstar/sata_host/bench_test/verify/sata_test b/drivers/sstar/sata_host/bench_test/verify/sata_test +new file mode 100755 +index 000000000000..54514fd93d08 +Binary files /dev/null and b/drivers/sstar/sata_host/bench_test/verify/sata_test differ +diff --git a/drivers/sstar/sata_host/bench_test/verify/sata_test.c b/drivers/sstar/sata_host/bench_test/verify/sata_test.c +new file mode 100755 +index 000000000000..e30c4fd689f3 +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/verify/sata_test.c +@@ -0,0 +1,475 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#else ++// #define do_div(x,y) ((x)/=(y)) ++//#endif ++ ++//#include "apiXC.h" ++#include "sata_test.h" ++#include "mdrv_sata_io.h" ++#include "mdrv_sata_io_st.h" ++ ++//--------------------------------------------------------------- ++// enum ++//--------------------------------------------------------------- ++typedef enum ++{ ++ E_DRV_ID_SATA = 0, ++ E_DRV_ID_MSYS, ++ E_DRV_ID_MEM, ++ E_DRV_ID_NUM, ++} EN_DRV_ID_TYPE; ++ ++ ++static int g_FD[E_DRV_ID_NUM] = {-1, -1, -1}; ++ ++typedef struct __Param ++{ ++ MS_U16 u16PortNo; ++ MS_U16 u16GenNo; ++ MS_U16 u16LoopbackEnable; ++ MS_U16 u16TxTestMode; ++ MS_U16 u16TxTestSSCEnable; ++} Param; ++ ++ST_SATA_Test_Property stSATATestProperty = ++{ ++ 0, // u16PortNo ++ 3, // u16GenNo ++ 0, ++ 0, ++ 0 ++}; ++ ++unsigned long long _GetSystemTimeStamp (void) ++{ ++ struct timeval tv; ++ struct timezone tz; ++ unsigned long long u64TimeStamp; ++ gettimeofday(&tv, &tz); ++ u64TimeStamp = tv.tv_sec * 1000000ULL + tv.tv_usec; ++ return u64TimeStamp; ++} ++ ++int Open_Device(EN_DRV_ID_TYPE enDrvID) ++{ ++ int ret = 1; ++ char device_name[E_DRV_ID_NUM][50] = ++ { ++ {"/dev/msata"}, ++ {"/dev/msys"}, ++ {"/dev/mem"}, ++ }; ++ ++ //FUNC_MSG("Open_Device: id=%d\n", enDrvID); ++ if(enDrvID >= E_DRV_ID_NUM) ++ { ++ printf("ID is not correct\n"); ++ return 0; ++ } ++ ++ //FUNC_MSG("Open_Device handle: %d\n", g_FD[enDrvID]); ++ if(g_FD[enDrvID] != -1) ++ { ++ } ++ else ++ { ++ //FUNC_MSG("Open_Device: %s\n", &device_name[enDrvID][0]); ++ //printf("Open: %s\n", &device_name[enDrvID][0]); ++ g_FD[enDrvID] = open(&device_name[enDrvID][0], O_RDWR | O_SYNC, S_IRUSR | S_IWUSR); ++ ++ if(g_FD[enDrvID] == -1) ++ { ++ printf("open %s fail\n", &device_name[enDrvID][0]); ++ ret = 0; ++ } ++ else ++ { ++ //printf("open %s %d sucess\n", &device_name[enDrvID][0], g_FD[enDrvID]); ++ ret = 1; ++ } ++ } ++ return ret; ++} ++ ++ ++#if 1 ++MS_BOOL _SysInit(void) ++{ ++ MS_BOOL ret = TRUE; ++ ++ //FUNC_MSG("System Init Finish\n"); ++ ++ return ret; ++} ++ ++MS_BOOL _SysDeInit(void) ++{ ++ MS_BOOL ret = TRUE; ++ ++ return ret; ++} ++#endif ++ ++MS_BOOL Test_SATA_Set_LoopbackTest(MS_U16 u16PortNo, MS_U16 u16GenNo) ++{ ++ stSata_Loopback_Test stInCfg; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ if((u16PortNo >= 2) || ((u16GenNo == 0) || (u16GenNo >= 4) )) ++ { ++ return FALSE; ++ } ++ ++ stInCfg.u16PortNo = u16PortNo; ++ stInCfg.u16GenNo = u16GenNo; ++ stInCfg.s32Result = 0; ++ ++ ioctl(g_FD[E_DRV_ID_SATA], IOCTL_SATA_SET_LOOPBACK_TEST, &stInCfg); ++ ++ printf("SATA loopback test result = %d\n", stInCfg.s32Result); ++ ++ return TRUE; ++} ++ ++MS_BOOL Test_SATA_Set_TxTest_HFTP(MS_U16 u16PortNo, MS_U16 u16GenNo, MS_U16 u16SSCEn) ++{ ++ stSata_Tx_Test stInCfg; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ if((u16PortNo >= 2) || ((u16GenNo == 0) || (u16GenNo >= 4) )) ++ { ++ return FALSE; ++ } ++ ++ stInCfg.u16PortNo = u16PortNo; ++ stInCfg.u16GenNo = u16GenNo; ++ stInCfg.u32SSCEnable = u16SSCEn; ++ stInCfg.s32Result = 0; ++ ++ ioctl(g_FD[E_DRV_ID_SATA], IOCTL_SATA_SET_TX_TEST_HFTP, &stInCfg); ++ ++ printf("SATA SET TX TEST HFTP result = %d\n", stInCfg.s32Result); ++ ++ return TRUE; ++} ++ ++MS_BOOL Test_SATA_Set_TxTest_MFTP(MS_U16 u16PortNo, MS_U16 u16GenNo, MS_U16 u16SSCEn) ++{ ++ stSata_Tx_Test stInCfg; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ if((u16PortNo >= 2) || ((u16GenNo == 0) || (u16GenNo >= 4) )) ++ { ++ return FALSE; ++ } ++ ++ stInCfg.u16PortNo = u16PortNo; ++ stInCfg.u16GenNo = u16GenNo; ++ stInCfg.u32SSCEnable = u16SSCEn; ++ stInCfg.s32Result = 0; ++ ++ ioctl(g_FD[E_DRV_ID_SATA], IOCTL_SATA_SET_TX_TEST_MFTP, &stInCfg); ++ ++ printf("SATA SET TX TEST MFTP result = %d\n", stInCfg.s32Result); ++ ++ return TRUE; ++} ++ ++MS_BOOL Test_SATA_Set_TxTest_LFTP(MS_U16 u16PortNo, MS_U16 u16GenNo, MS_U16 u16SSCEn) ++{ ++ stSata_Tx_Test stInCfg; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ if((u16PortNo >= 2) || ((u16GenNo == 0) || (u16GenNo >= 4) )) ++ { ++ return FALSE; ++ } ++ ++ stInCfg.u16PortNo = u16PortNo; ++ stInCfg.u16GenNo = u16GenNo; ++ stInCfg.u32SSCEnable = u16SSCEn; ++ stInCfg.s32Result = 0; ++ ++ ioctl(g_FD[E_DRV_ID_SATA], IOCTL_SATA_SET_TX_TEST_LFTP, &stInCfg); ++ ++ printf("SATA SET TX TEST LFTP result = %d\n", stInCfg.s32Result); ++ ++ return TRUE; ++} ++ ++MS_BOOL Test_SATA_Set_TxTest_LBP(MS_U16 u16PortNo, MS_U16 u16GenNo, MS_U16 u16SSCEn) ++{ ++ stSata_Tx_Test stInCfg; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ if((u16PortNo >= 2) || ((u16GenNo == 0) || (u16GenNo >= 4) )) ++ { ++ return FALSE; ++ } ++ ++ stInCfg.u16PortNo = u16PortNo; ++ stInCfg.u16GenNo = u16GenNo; ++ stInCfg.u32SSCEnable = u16SSCEn; ++ stInCfg.s32Result = 0; ++ ++ ioctl(g_FD[E_DRV_ID_SATA], IOCTL_SATA_SET_TX_TEST_LBP, &stInCfg); ++ ++ printf("SATA SET TX TEST LBP result = %d\n", stInCfg.s32Result); ++ ++ return TRUE; ++} ++ ++MS_BOOL Test_SATA_Set_TxTest_SSOP(MS_U16 u16PortNo, MS_U16 u16GenNo, MS_U16 u16SSCEn) ++{ ++ stSata_Tx_Test stInCfg; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ if((u16PortNo >= 2) || ((u16GenNo == 0) || (u16GenNo >= 4) )) ++ { ++ return FALSE; ++ } ++ ++ stInCfg.u16PortNo = u16PortNo; ++ stInCfg.u16GenNo = u16GenNo; ++ stInCfg.u32SSCEnable = u16SSCEn; ++ stInCfg.s32Result = 0; ++ ++ ioctl(g_FD[E_DRV_ID_SATA], IOCTL_SATA_SET_TX_TEST_SSOP, &stInCfg); ++ ++ printf("SATA SET TX TEST SSOP result = %d\n", stInCfg.s32Result); ++ ++ return TRUE; ++} ++ ++MS_S32 fnAlloc(MS_U8 *pnMMAHeapName, MS_U32 nSize, MS_U64 *pnAddr) ++{ ++ //kmalloc((nSize), GFP_KERNEL); ++ return TRUE; ++} ++ ++MS_S32 fnFree(MS_U64 nAddr) ++{ ++ //kfree((MS_U8 *)nAddr); ++ return TRUE; ++} ++ ++MS_BOOL _SATAInit(void) ++{ ++ MS_BOOL ret = TRUE; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ return ret; ++} ++ ++MS_BOOL _SATADeInit(void) ++{ ++ MS_BOOL ret = TRUE; ++ ++ if(Open_Device(E_DRV_ID_SATA) == 0) ++ { ++ return FALSE; ++ } ++ ++ return ret; ++} ++ ++MS_BOOL _SATATest(void) ++{ ++ MS_BOOL ret = TRUE; ++ MS_U16 u16PortNo = stSATATestProperty.u16PortNo; ++ MS_U16 u16GenNo = stSATATestProperty.u16GenNo; ++ MS_U16 u16SSCEn = stSATATestProperty.u16TxTestSSCEnable; ++ ++ if(stSATATestProperty.u16LoopbackEnable == TRUE) ++ { ++ ret = Test_SATA_Set_LoopbackTest(u16PortNo, u16GenNo); ++ } ++ else if((stSATATestProperty.u16TxTestMode > 0) && (stSATATestProperty.u16TxTestMode <= 5)) ++ { ++ switch (stSATATestProperty.u16TxTestMode) ++ { ++ case 1: ++ ret = Test_SATA_Set_TxTest_HFTP(u16PortNo, u16GenNo, u16SSCEn); ++ break; ++ case 2: ++ ret = Test_SATA_Set_TxTest_MFTP(u16PortNo, u16GenNo, u16SSCEn); ++ break; ++ case 3: ++ ret = Test_SATA_Set_TxTest_LFTP(u16PortNo, u16GenNo, u16SSCEn); ++ break; ++ case 4: ++ ret = Test_SATA_Set_TxTest_LBP(u16PortNo, u16GenNo, u16SSCEn); ++ break; ++ case 5: ++ ret = Test_SATA_Set_TxTest_SSOP(u16PortNo, u16GenNo, u16SSCEn); ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static void UsingGuide(int argc, char **argv) ++{ ++ fprintf(stdout, "Usage: %s [-loopback PortNo GenNo]\n" ++ "like : '%s -loopback 0 3 '\n" ++ "Arguments:\n", argc ? argv[0] : NULL, argc ? argv[0] : NULL); ++ /* loopback test */ ++ fprintf(stdout, "-loopback\t: loopback test,\n" ++ "\t '-loopback ', : 0 or 1, : 1 ~ 3\n"); ++ ++ /* Tx test */ ++ fprintf(stdout, "-txmode\t: Tx test,\n" ++ "\t '-txmode ', : 0 or 1, : 1 ~ 3\n" ++ "\t : 1 : HFTP, 2: MFTP, 3: LFTP, 4: LBP, 5: SSOP\n" ++ "\t : 0 : disable SSC, 1: enable SSC\n"); ++ ++ exit(EXIT_FAILURE); ++} ++ ++static void get_opt(Param *SetParam, int argc, char **argv) ++{ ++ char *endptr = NULL; ++ int i = 0; ++ ++ /* Default value */ ++ memset(SetParam, 0x0, sizeof(Param)); ++ stSATATestProperty.u16LoopbackEnable = FALSE; ++ stSATATestProperty.u16TxTestMode = 0; ++ ++ if(argc > 1) ++ { ++ if ( argc == 2 && (!strcmp(argv[1], "-h") || !strcmp(argv[1], "--help")) ) ++ UsingGuide(argc, argv); ++ ++ for (i = 1; i < argc; i++) ++ { ++ /* Loopback test */ ++ if (!strcmp(argv[i], "-loopback")) ++ { ++ SetParam->u16PortNo = strtol(argv[++i], &endptr, 10); ++ SetParam->u16GenNo = strtol(argv[++i], &endptr, 10); ++ if ((SetParam->u16PortNo > 1) || ((SetParam->u16GenNo == 0) || (SetParam->u16GenNo >= 4))) ++ { ++ fprintf(stderr, "Invalid loopback test parameter(port=%d, gen=%d).\n", SetParam->u16PortNo, SetParam->u16GenNo); ++ UsingGuide(argc, argv); ++ } ++ stSATATestProperty.u16PortNo = SetParam->u16PortNo; ++ stSATATestProperty.u16GenNo = SetParam->u16GenNo; ++ stSATATestProperty.u16LoopbackEnable = TRUE; ++ } ++ /* */ ++ else if (!strcmp(argv[i], "-txmode")) ++ { ++ SetParam->u16PortNo = strtol(argv[++i], &endptr, 10); ++ SetParam->u16GenNo = strtol(argv[++i], &endptr, 10); ++ SetParam->u16TxTestMode = strtol(argv[++i], &endptr, 10); ++ SetParam->u16TxTestSSCEnable = strtol(argv[++i], &endptr, 10); ++ if ((SetParam->u16PortNo > 1) || ((SetParam->u16GenNo == 0) || (SetParam->u16GenNo >= 4)) || (SetParam->u16TxTestMode >= 6)) ++ { ++ fprintf(stderr, "Invalid Tx test parameter(port=%d, gen=%d, Tx mode=%d).\n", SetParam->u16PortNo, SetParam->u16GenNo, SetParam->u16TxTestMode); ++ UsingGuide(argc, argv); ++ } ++ stSATATestProperty.u16PortNo = SetParam->u16PortNo; ++ stSATATestProperty.u16GenNo = SetParam->u16GenNo; ++ stSATATestProperty.u16TxTestMode = SetParam->u16TxTestMode; ++ stSATATestProperty.u16TxTestSSCEnable = SetParam->u16TxTestSSCEnable; ++ } ++ else ++ { ++ fprintf(stderr, "Invalid input parameter(%s).\n", argv[i]); ++ UsingGuide(argc, argv); ++ } ++ } ++ } ++ else ++ { ++ UsingGuide(argc, argv); ++ } ++} ++ ++int main(int argc, char *argv[]) ++{ ++ Param SetParam; ++ ++ get_opt(&SetParam, argc, argv); ++ ++ if (!_SysInit()) ++ goto SATA_TEST_EXIT; ++ ++ if (!_SATAInit()) ++ goto SATA_TEST_EXIT; ++ ++ if (!_SATATest()) ++ goto SATA_TEST_EXIT; ++ ++SATA_TEST_EXIT: ++ _SATADeInit(); ++ _SysDeInit(); ++ ++ return 0; ++} +diff --git a/drivers/sstar/sata_host/bench_test/verify/sata_test.h b/drivers/sstar/sata_host/bench_test/verify/sata_test.h +new file mode 100755 +index 000000000000..366c3ea719bd +--- /dev/null ++++ b/drivers/sstar/sata_host/bench_test/verify/sata_test.h +@@ -0,0 +1,79 @@ ++#ifndef SATA_TEST_H ++#define SATA_TEST_H ++ ++/// data type unsigned char, data length 1 byte ++typedef unsigned char MS_U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short MS_U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int MS_U32; // 4 bytes ++/// data type unsigned int, data length 8 byte ++typedef unsigned long long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int, data length 8 byte ++typedef signed long long MS_S64; // 8 bytes ++/// data type float, data length 4 byte ++typedef float MS_FLOAT; // 4 bytes ++/// data type pointer content ++typedef size_t MS_VIRT; // 8 bytes ++/// data type hardware physical address ++typedef size_t MS_PHYADDR; // 8 bytes ++/// data type 64bit physical address ++typedef MS_U64 MS_PHY; // 8 bytes ++/// data type size_t ++typedef size_t MS_SIZE; // 8 bytes ++/// definition for MS_BOOL ++typedef unsigned char MS_BOOL; // 1 byte ++/// print type MPRI_PHY ++#define MPRI_PHY "%x" ++/// print type MPRI_PHY ++#define MPRI_VIRT "%tx" ++ ++typedef unsigned char bool; ++ ++#ifdef NULL ++ #undef NULL ++#endif ++#define NULL 0 ++ ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#define ENABLE 1 ++#define DISABLE 0 ++ ++// Debug Message ++///ASCII color code ++#define ASCII_COLOR_RED "\033[1;31m" ++#define ASCII_COLOR_WHITE "\033[1;37m" ++#define ASCII_COLOR_YELLOW "\033[1;33m" ++#define ASCII_COLOR_BLUE "\033[1;36m" ++#define ASCII_COLOR_GREEN "\033[1;32m" ++#define ASCII_COLOR_END "\033[0m" ++ ++#if 1 ++ //#define FUNC_MSG(fmt, args...) ({do{printf(ASCII_COLOR_GREEN"%s[%d] ",__FUNCTION__,__LINE__);printf(fmt, ##args);printf(ASCII_COLOR_END);}while(0);}) ++ #define FUNC_MSG(fmt, args...) ({do{printf(fmt, ##args);}while(0);}) ++ #define FUNC_ERR(fmt, args...) ({do{printf(ASCII_COLOR_RED"%s[%d] ",__FUNCTION__,__LINE__);printf(fmt, ##args);printf(ASCII_COLOR_END);}while(0);}) ++#else ++ #define FUNC_MSG(fmt, args...) ++ #define FUNC_ERR(fmt, args...) ++#endif ++// Buffer Management ++#define SATA_MIU 0 ++ ++typedef struct ++{ ++ MS_U16 u16PortNo; ++ MS_U16 u16GenNo; ++ MS_U16 u16LoopbackEnable; ++ MS_U16 u16TxTestMode; ++ MS_U16 u16TxTestSSCEnable; ++} ST_SATA_Test_Property; ++ ++#endif // SATA_TEST_H +diff --git a/drivers/sstar/sata_host/infinity2/mhal_sata_host.c b/drivers/sstar/sata_host/infinity2/mhal_sata_host.c +new file mode 100755 +index 000000000000..16334b904b1d +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2/mhal_sata_host.c +@@ -0,0 +1,343 @@ ++/* ++* mhal_sata_host.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++extern ptrdiff_t mstar_pm_base; ++#define sata_reg_write16(val, addr) { (*((volatile unsigned short*)(addr))) = (unsigned short)(val); } ++#define sata_reg_write8(val, addr) { (*((volatile unsigned char*)(addr))) = (unsigned char)(val);} ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++#define RIU_BASE_ADDR 0xFD000000 ++ ++static void MHal_SATA_Clock_Config(phys_addr_t misc_base, phys_addr_t port_base, bool enable) ++{ ++ u16 u16Temp; ++ ++ // Enable MAC Clock, bank is chip dependent ++ // [0] clk gated ++ // [1] clk invert ++ // [4:2] 0: 240M, 1: 216M, 3: clk_miu ++ ++ if(enable) ++ { ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~(CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED); ++ u16Temp |= CKG_SATA_FCLK_MIU_P; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~((CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED) << 8); ++ u16Temp |= (CKG_SATA_FCLK_MIU_P << 8); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ } ++ else ++ { ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~(CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED); ++ u16Temp |= CKG_SATA_FCLK_GATED; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~((CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED) << 8); ++ u16Temp |= (CKG_SATA_FCLK_GATED << 8); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ } ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ printk("[SATA0] Clock : %s\n", (enable ? "ON" : "OFF")); ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ printk("[SATA1] Clock : %s\n", (enable ? "ON" : "OFF")); ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_Clock_Config); ++ ++static u32 MHal_SATA_get_max_speed(void) ++{ ++ return E_PORT_SPEED_GEN3; ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_get_max_speed); ++ ++static void MHal_SATA_HW_Inital(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base) ++{ ++ u16 u16Temp; ++ u32 GHC_PHY = 0x0; ++ int phy_mode; ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ } ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ } ++ ++ MHal_SATA_Clock_Config(misc_base,port_base, 1); ++ //u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ //printk("SATA_CLK_REG = 0x%x\n", u16Temp); ++ ++ printk("RIU_BASE = 0x%x, GHC_PHY = 0x%x\n", SSTAR_RIU_BASE, GHC_PHY); ++ //RIU_BASE = xfd000000, misc_base : xfd205a00 , hba_base : xfd205800 , port_base : xfd226400 , GHC_PHY : 103900 ++ ++ // ECO bit, to fix 1k boundary issue. ++ ++ //u16Temp = readw((const volatile void *)SSTAR_RIU_BASE + (0x2d35 << 1)); ++ u16Temp = readw((volatile void *)misc_base + SATA_MISC_AGEN_F_VAL); ++ u16Temp |= 0x8000; ++ writew(u16Temp, (volatile void *)misc_base + SATA_MISC_AGEN_F_VAL); ++ ++ writew(0x0001, (volatile void *)misc_base + SATA_MISC_HOST_SWRST);//25 ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_HOST_SWRST);//25 ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_AMBA_MUXRST);//21 ++ writew(0x008C, (volatile void *)misc_base + SATA_MISC_AMBA_ARBIT);//2 ++ //writew(0x0003, (volatile void *)misc_base +(0x55<<2));//FPGA mode ++ // AHB Data FIFO Setting ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_HBA_HADDR); ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_HBA_LADDR); ++ writew(0x1800, (volatile void *)misc_base + SATA_MISC_CMD_HADDR); ++ writew(0x1000, (volatile void *)misc_base + SATA_MISC_CMD_LADDR); ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_DATA_ADDR); ++ writew(0x0001, (volatile void *)misc_base + SATA_MISC_ENRELOAD); ++ writew(0x0001, (volatile void *)misc_base + SATA_MISC_ACCESS_MODE); ++ ++ //printk("check sata speed !!!!!!\n"); ++ u16Temp = readw((volatile void *)port_base + (0x2c << 1)); ++ u16Temp = u16Temp & (~E_PORT_SPEED_MASK); ++ u16Temp = u16Temp | MHal_SATA_get_max_speed(); ++ writew(u16Temp, (volatile void *)port_base + (0x2c << 1)); ++ u16Temp = readw((volatile void *)port_base + (0x2c << 1)); ++ printk("MAC SATA SPEED= 0x%x\n", u16Temp); ++ ++ if((u16Temp & E_PORT_SPEED_MASK) == E_PORT_SPEED_GEN1) ++ phy_mode = 0; ++ else if((u16Temp & E_PORT_SPEED_MASK) == E_PORT_SPEED_GEN2) ++ phy_mode = 1; ++ else ++ phy_mode = 2; ++ ++ //printk("sata hal PHY init !!!!!!\n"); ++ //printk("Gen1 Tx swing\n"); ++ writew(0x2031, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x3803, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x96) << 1)); ++ // EQ BW ++ //printk("Gen1 EQ BW\n"); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ u16Temp &= ~0x0060; ++ u16Temp |= 0x0020; // default is 0x01 ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ // EQ STR ++ //printk("Gen1 EQ STR\n"); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ u16Temp &= ~0x001f; ++ u16Temp |= 0x0003; // default is 0x03 ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ ++ // Gen2 ++ // Tx swing ++ //printk("Gen2 Tx swing\n"); ++ writew(0x3935, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); ++ writew(0x3920, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x2e) << 1)); ++ // EQ BW ++ //printk("Gen2 EQ BW\n"); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x50) << 1)); ++ u16Temp &= ~0x1800; ++ u16Temp |= 0x0800; // default is 0x01 ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x50) << 1)); ++ // EQ STR ++ //printk("Gen2 EQ STR\n"); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x26) << 1)); ++ u16Temp &= ~0x001f; ++ u16Temp |= 0x0003; // default is 0x03 ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x26) << 1)); ++ ++ // Gen3 ++ // Tx swing ++ //printk("Gen3 Tx swing\n"); ++ writew(0x3937, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x3921, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // EQ BW ++ //printk("Gen3 EQ BW\n"); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ u16Temp &= ~0x0060; ++ u16Temp |= 0x0000; // default is 0x00 ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ // EQ STR ++ //printk("Gen3 EQ EQ STR\n"); ++ //printk("EQ BW\n"); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ u16Temp &= ~0x001f; ++ u16Temp |= 0x0003; // default is 0x03 ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ ++ // SSC setup ++#if 1 // new settting to fixed PMP mode issue with JMB575 ++ // STEP1[10:0] ++ writew(0x2002, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x64) << 1)); // [12]: 0 Stop sequence mode, 1: Reverse sequence mode ++ // SET[15:0] ++ writew(0x0aff, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ // SET[23:16] ++ writeb(0x17, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ // SPAN[14:0] ++ writew(0x0495, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x66) << 1)); ++#else ++ writew(0x3007, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x64) << 1)); ++ writew(0xdf0a, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ writeb(0x24, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ writew(0x02e8, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x66) << 1)); ++#endif ++ ++ ++ //printk("sata SATA PHY OOB setting ..\n"); ++ writew(0x96de, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ //writew(0x031e, SSTAR_RIU_BASE + (0x103934 << 1)); ++ writew(0x0f20, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x06) << 1)); ++ writew(0x341f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x08) << 1)); ++ ++ //printk("sata SATA PHY setting ..\n"); ++ //asm volatile( "loop: b loop"); ++ ++#if 1 // new setting ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x22) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x24) << 1)); ++ //writew(0x0a3d, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ //writeb(0x17, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ writew(0x9103, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0c) << 1)); ++ writeb(0x06, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x3e) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x10) << 1)); // Enable clocks ++#if 0 // ++ writeb(0x0f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); // [10]: OOB pattern select ++ writew(0x848f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x848e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++#else ++ writeb(0x0b, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); // [10]: OOB pattern select ++ writew(0x9a8f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); // [0]: Reset ++ writew(0x9a8e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++#endif ++ writew(0x831e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x68) << 1)); ++ writew(0x031e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0xc0) << 1)); ++ writew(0x031e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0xc2) << 1)); ++ writeb(0x30, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x19) << 1) - 1); ++ //writew(0x9110, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); // new add ++ writeb(0x80, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x3c) << 1)); ++ writeb(0x50, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x33) << 1) - 1); // [12]: reg_force_tx_oob_pat ++ ++ if(phy_mode == 1) // Gen2 ++ writew(0x9114, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1));// for Gen2 ++ else ++ writew(0x9115, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1));// for Gen3 and Gen1 ++ ++ if(phy_mode == 0) // for Gen1 ++ { ++ writew(0x080e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x1115, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x1108, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // Override speed ++ writeb(0x00, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else if(phy_mode == 1) // for Gen2 ++ { ++ writew(0x0811, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x1115, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x1108, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // Override speed ++ writeb(0x50, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else // for Gen3 ++ { ++ writew(0x0811, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x111a, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x110a, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // Override speed ++ writeb(0xA0, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ ++ writew(0x2200, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); // [9]: Enable host ++ ++#else ++ ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x22) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x24) << 1)); ++ writew(0x0a3d, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ writeb(0x17, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ writew(0x9103, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0c) << 1)); ++ writeb(0x06, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x3e) << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x10) << 1)); // Enable clocks ++ writeb(0x0b, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); // [10]: OOB pattern select ++ writew(0x9a8f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); // [0]: Reset ++ writew(0x9a8e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x831e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x68) << 1)); ++ writew(0x031e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0xc0) << 1)); ++ writew(0x031e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0xc2) << 1)); ++ writeb(0x30, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x19) << 1) - 1); ++ //writew(0x9110, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); // new add ++ writeb(0x80, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x3c) << 1)); ++ writeb(0x50, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x33) << 1) - 1); // [12]: reg_force_tx_oob_pat ++ writew(0x2200, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); // [9]: Enable host ++ ++#endif ++ ++ writew(0x0001, (volatile void *) hba_base + SS_HOST_CTL); // reset HBA ++ ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_HW_Inital); ++ ++static void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base) ++{ ++ // Init FW to trigger controller ++ writew(0x0000, (volatile void *)hba_base + (SS_HOST_CAP)); ++ writew(0x0000, (volatile void *)hba_base + (SS_HOST_CAP + 0x4)); ++ ++ // Port Implement ++ writew(0x0001, (volatile void *)hba_base + (SS_HOST_PORTS_IMPL)); ++ writew(0x0000, (volatile void *)port_base + (SS_PORT_CMD)); ++ writew(0x0000, (volatile void *)port_base + (SS_PORT_CMD + 0x4)); ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_Setup_Port_Implement); ++ ++static phys_addr_t MHal_SATA_bus_address(phys_addr_t phy_address) ++{ ++ //phys_addr_t bus_address; ++ ++ //printk("phy addr = 0x%llx\n", phy_address); ++ if (phy_address >= MIU_INTERVAL_SATA) ++ { ++ //printk("select MIU1, bus addr = 0x%8.8x\n", phy_address + 0x20000000); ++ //return phy_address + MIU_INTERVAL_SATA; ++ return phy_address + 0x20000000; ++ } ++ else ++ { ++ //printk("select MIU0, bus addr = 0x%8.8x\n", phy_address - 0x20000000); ++ //return phy_address - MIU_INTERVAL_SATA; ++ return phy_address - 0x20000000; ++ } ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_bus_address); +diff --git a/drivers/sstar/sata_host/infinity2/mhal_sata_host.h b/drivers/sstar/sata_host/infinity2/mhal_sata_host.h +new file mode 100755 +index 000000000000..e08e7ea67df9 +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2/mhal_sata_host.h +@@ -0,0 +1,293 @@ ++/* ++* mhal_sata_host.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MHAL_SATA_HOST_H_ ++#define _MHAL_SATA_HOST_H_ ++ ++#if defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++#define SSTAR_RIU_BASE mstar_pm_base ++#else ++//#define MSTAR_RIU_BASE 0xBF200000 ++//#define MSTAR_RIU_BASE 0x1F000000 ++//#define MSTAR_RIU_BASE 0x1F000000 //JFY ++#define SSTAR_RIU_BASE 0xFD000000 //JFY ++#endif ++ ++#define REG_CHIPTOP_BASE 0x100B00 ++ ++#ifndef BIT //for Linux_kernel type, BIT redefined in ++ #define BIT(_bit_) (1 << (_bit_)) ++#endif ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++#define REG_CKG_SATA_FCLK (REG_CHIPTOP_BASE + (0x32<<1)) ++#define CKG_SATA_FCLK_GATED BIT(0) ++#define CKG_SATA_FCLK_INVERT BIT(1) ++#define CKG_SATA_FCLK_MASK BMASK(4:2) ++#define CKG_SATA_FCLK_240MHZ (0 << 2) ++#define CKG_SATA_FCLK_216MHZ (1 << 2) ++#define CKG_SATA_FCLK_MIU_P (3 << 2) ++ ++#define SATA_PORT_BASE_0 0x100000 ++#define SATA_PORT_BASE_1 0x110000 ++ ++#define SATA_GHC_0 0x102B00 ++#define SATA_GHC_0_P0 0x102C00 ++#define SATA_GHC_0_MISC 0x102D00 ++#define SATA_GHC_0_MIUPORT 0x103700 ++#define SATA_GHC_0_PHY 0x103900 ++ ++#define SATA_GHC_1 0x113100 ++#define SATA_GHC_1_P0 0x113200 ++#define SATA_GHC_1_MISC 0x113300 ++#define SATA_GHC_1_MIUPORT 0x113800 ++#define SATA_GHC_1_PHY 0x162A00//0x113900 ++/* ++u32 virtAddr(u32 addr){ ++ addr=MSTAR_RIU_BASE+addr<<9; ++ return (u32)ioremap(addr,0x200); ++} ++*/ ++/* ++#define SATA_GHC_0_ADDRESS_START ioremap(MSTAR_RIU_BASE + (0x102B << 9),512) ++#define SATA_GHC_0_ADDRESS_END SATA_GHC_0_ADDRESS_START+0xFE ++#define SATA_GHC_0_P0_ADDRESS_START (MSTAR_RIU_BASE + (0x113200 << 1)) ++#define SATA_GHC_0_P0_ADDRESS_END (MSTAR_RIU_BASE + (0x1132FE << 1)) ++#define SATA_MISC_0_ADDRESS_START (MSTAR_RIU_BASE + (0x113300 << 1)) ++#define SATA_MISC_0_ADDRESS_END (MSTAR_RIU_BASE + (0x1133FE << 1)) ++*/ ++/* ++u32 SATA_GHC_0_ADDRESS_START=(u32)virtAddr(0x102B);//(MSTAR_RIU_BASE + (0x102B00 << 1))//0xFD000000 ++u32 SATA_GHC_0_ADDRESS_END=SATA_GHC_0_ADDRESS_START+0xFE;//(MSTAR_RIU_BASE + (0x102BFE << 1)) ++u32 SATA_GHC_0_P0_ADDRESS_START=virtAddr(MSTAR_RIU_BASE+0x102C<<9);//(MSTAR_RIU_BASE + (0x102C00 << 1)) ++u32 SATA_GHC_0_P0_ADDRESS_END=SATA_GHC_0_P0_ADDRESS_START+0xFE;//(MSTAR_RIU_BASE + (0x102CFE << 1)) ++u32 SATA_MISC_0_ADDRESS_START=virtAddr(MSTAR_RIU_BASE+0x102D<<9);//(MSTAR_RIU_BASE + (0x102D00 << 1)) ++u32 SATA_MISC_0_ADDRESS_END=SATA_MISC_0_ADDRESS_START+0xFE;//(MSTAR_RIU_BASE + (0x102DFE << 1)) ++ ++ ++ ++*/ ++ ++#define SATA_GHC_0_ADDRESS_START (SSTAR_RIU_BASE + (0x102B00 << 1)) ++#define SATA_GHC_0_ADDRESS_END (SSTAR_RIU_BASE + (0x102BFE << 1)) ++#define SATA_GHC_0_P0_ADDRESS_START (SSTAR_RIU_BASE + (0x102C00 << 1)) ++#define SATA_GHC_0_P0_ADDRESS_END (SSTAR_RIU_BASE + (0x102CFE << 1)) ++#define SATA_MISC_0_ADDRESS_START (SSTAR_RIU_BASE + (0x102D00 << 1)) ++#define SATA_MISC_0_ADDRESS_END (SSTAR_RIU_BASE + (0x102DFE << 1)) ++ ++ ++#define SATA_GHC_1_ADDRESS_START (SSTAR_RIU_BASE + (0x113100 << 1)) ++#define SATA_GHC_1_ADDRESS_END (SSTAR_RIU_BASE + (0x1131FE << 1)) ++#define SATA_GHC_1_P0_ADDRESS_START (SSTAR_RIU_BASE + (0x113200 << 1)) ++#define SATA_GHC_1_P0_ADDRESS_END (SSTAR_RIU_BASE + (0x1132FE << 1)) ++#define SATA_MISC_1_ADDRESS_START (SSTAR_RIU_BASE + (0x113300 << 1)) ++#define SATA_MISC_1_ADDRESS_END (SSTAR_RIU_BASE + (0x1133FE << 1)) ++ ++/* ++#define SATA_GHC_0_ADDRESS_START (0xFD000000 + (0x102B00 << 1)) ++#define SATA_GHC_0_ADDRESS_END (0xFD000000 + (0x102BFE << 1)) ++#define SATA_GHC_1_ADDRESS_START (0xFD000000 + (0x102C00 << 1)) ++#define SATA_GHC_1_ADDRESS_END (0xFD000000 + (0x102CFE << 1)) ++#define SATA_MISC_ADDRESS_START (0xFD000000 + (0x102D00 << 1)) ++#define SATA_MISC_ADDRESS_END (0xFD000000 + (0x102DFE << 1)) ++*/ ++ ++// FIXME: Needs to be removed since K6 does not support XIU mode. ++#if defined(CONFIG_ARM64) ++#define SATA_SDMAP_RIU_BASE mstar_pm_base ++#else ++#define SATA_SDMAP_RIU_BASE MSTAR_RIU_BASE //0xFD000000 ++#endif ++ ++// MIU interval, the gap between MIU0 and MIU1, chip dependent ++#define MIU_INTERVAL_SATA 0x60000000 // for K6 ++ ++// Local Definition, internal SATA MAC SRAM address ++#define AHCI_P0CLB 0x18001000 ++#define AHCI_P0FB 0x18001100 ++#define AHCI_CTBA0 0x18001200 ++ ++#define SATA_PORT_NUM 1 ++#define SATA_CMD_HEADER_SIZE 0x400 ++#define SATA_FIS_SIZE 0x100 ++ ++enum { ++ /* global controller registers */ ++ SS_HOST_CAP = 0x00, /* host capabilities */ ++ SS_HOST_CTL = (0x04 << 1), /* global host control */ ++ SS_HOST_IRQ_STAT = (0x08 << 1), /* interrupt status */ ++ SS_HOST_PORTS_IMPL = (0x0c << 1), /* bitmap of implemented ports */ ++ SS_HOST_VERSION = (0x10 << 1), /* AHCI spec. version compliancy */ ++ SS_HOST_CAP2 = (0x24 << 1), /* host capabilities, extended */ ++ ++ /* HOST_CTL bits - HOST_CAP, 0x00 */ ++ //MS_HOST_RESET = (1 << 0), /* reset controller; self-clear */ ++ //MS_HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ ++ // MS_HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ ++ ++ /* Registers for each SATA port */ ++ SS_PORT_LST_ADDR = 0x00, /* command list DMA addr */ ++ SS_PORT_LST_ADDR_HI = (0x04 << 1), /* command list DMA addr hi */ ++ SS_PORT_FIS_ADDR = (0x08 << 1), /* FIS rx buf addr */ ++ SS_PORT_FIS_ADDR_HI = (0x0c << 1), /* FIS rx buf addr hi */ ++ SS_PORT_IRQ_STAT = (0x10 << 1), /* interrupt status */ ++ SS_PORT_IRQ_MASK = (0x14 << 1), /* interrupt enable/disable mask */ ++ SS_PORT_CMD = (0x18 << 1), /* port command */ ++ SS_PORT_TFDATA = (0x20 << 1), /* taskfile data */ ++ SS_PORT_SIG = (0x24 << 1), /* device TF signature */ ++ SS_PORT_SCR_STAT = (0x28 << 1), /* SATA phy register: SStatus */ ++ SS_PORT_SCR_CTL = (0x2c << 1), /* SATA phy register: SControl */ ++ SS_PORT_SCR_ERR = (0x30 << 1), /* SATA phy register: SError */ ++ SS_PORT_SCR_ACT = (0x34 << 1), /* SATA phy register: SActive */ ++ SS_PORT_CMD_ISSUE = (0x38 << 1), /* command issue */ ++ SS_PORT_SCR_NTF = (0x3c << 1), /* SATA phy register: SNotification */ ++ SS_PORT_DMA_CTRL = (0x70 << 1), /* SATA phy register: SNotification */ ++ ++ /* PORT_CMD bits */ ++ SS_PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ ++ SS_PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ ++ SS_PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ ++ SS_PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ ++ SS_PORT_CMD_PMP = (1 << 17), /* PMP attached */ ++ SS_PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ ++ SS_PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ ++ SS_PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ ++ SS_PORT_CMD_CLO = (1 << 3), /* Command list override */ ++ SS_PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ ++ SS_PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ ++ SS_PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ ++ ++ SS_PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ ++ SS_PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ ++ SS_PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ ++ SS_PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ ++ ++ /* Status Error */ ++ SS_AHCI_PORT_SERR_RDIE = (1 << 0), /* Recovered Data Integrity Error */ ++ SS_AHCI_PORT_SERR_RCE = (1 << 1), /* Recovered Communications Error */ ++ /* Bit 2 ~ 7 Reserved */ ++ SS_AHCI_PORT_SERR_TDIE = (1 << 8), /* Transient Data Integrity Error */ ++ SS_AHCI_PORT_SERR_PCDIE = (1 << 9), /* Persistent Communication or Data Integrity Error */ ++ SS_AHCI_PORT_SERR_PE = (1 << 10), /* Protocol Error */ ++ SS_AHCI_PORT_SERR_IE = (1 << 11), /* Internal Error */ ++ /* Bit 15 ~ 12 Reserved */ ++ SS_AHCI_PORT_SERR_PRDYC = (1 << 16), /* PhyRdy Change */ ++ SS_AHCI_PORT_SERR_PIE = (1 << 17), /* Phy Internal Error */ ++ SS_AHCI_PORT_SERR_COMW = (1 << 18), /* Comm Wake Detect */ ++ SS_AHCI_PORT_SERR_TDE = (1 << 19), /* 10B to 8B Decode Error */ ++ SS_AHCI_PORT_SERR_DE = (1 << 20), /* Disparity Error <= Not Use by AHCI */ ++ SS_AHCI_PORT_SERR_CRCE = (1 << 21), /* CRC Error */ ++ SS_AHCI_PORT_SERR_HE = (1 << 22), /* Handshake Error */ ++ SS_AHCI_PORT_SERR_LSE = (1 << 23), /* Link Sequence Error */ ++ SS_AHCI_PORT_SERR_TSTE = (1 << 24), /* Transport state transition error */ ++ SS_AHCI_PORT_SERR_UFIS = (1 << 25), /* Unknown FIS Type */ ++ SS_AHCI_PORT_SERR_EXC = (1 << 26), /* Exchanged : a change in device presence has been detected */ ++ /* Bit 31 ~ 27 Reserved */ ++}; ++ ++enum { ++ E_PORT_SPEED_MASK = (0xF << 4), ++ E_PORT_SPEED_NO_RESTRICTION = (0x0 < 4), ++ E_PORT_SPEED_GEN1 = (0x1 << 4), ++ E_PORT_SPEED_GEN2 = (0x2 << 4), ++ E_PORT_SPEED_GEN3 = (0x3 << 4), ++ ++ E_PORT_DET_MASK = (0xF << 0), //Device Detection Initialization ++ E_PORT_DET_NODEVICE_DETECT = 0x0, ++ E_PORT_DET_HW_RESET = 0x1, // Cause HW send initial sequence ++ E_PORT_DET_DISABLE_PHY = 0x4, // Put PHY into Offline ++ E_PORT_DET_DEVICE_NOEST = 0x1, // not established ++ E_PORT_DET_DEVICE_EST = 0x3, // established ++ E_PORT_DET_PHY_OFFLINE = 0x4, // Put PHY into Offline ++ ++ DATA_COMPLETE_INTERRUPT = (1 << 31), ++ ++ /* PORT_IRQ_{STAT,MASK} bits */ ++ //PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ ++ //PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ ++ //PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ ++ //PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ ++ //PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ ++ //PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ ++ //PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ ++ //PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ ++ ++ //PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ ++ //PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ ++ //PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ ++ //PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ ++ //PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ ++ //PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ ++ //PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ ++ //PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ ++ //PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ ++ ++ //PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | ++ // PORT_IRQ_IF_ERR | ++ // PORT_IRQ_CONNECT | ++ // PORT_IRQ_PHYRDY | ++ // PORT_IRQ_UNK_FIS | ++ // PORT_IRQ_BAD_PMP, ++ //PORT_IRQ_ERROR = PORT_IRQ_FREEZE | ++ // PORT_IRQ_TF_ERR | ++ // PORT_IRQ_HBUS_DATA_ERR, ++ //DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | ++ // PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | ++ // PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, ++}; ++ ++/* ++ * Host Controller MISC Register ++ */ ++enum ++{ ++ SATA_MISC_CFIFO_ADDRL =((0x10 <<1 )<<1), ++ SATA_MISC_CFIFO_ADDRH =((0x11 <<1 )<<1), ++ SATA_MISC_CFIFO_WDATAL =((0x12 <<1 )<<1), ++ SATA_MISC_CFIFO_WDATAH =((0x13 <<1 )<<1), ++ SATA_MISC_CFIFO_RDATAL =((0x14 <<1 )<<1), ++ SATA_MISC_CFIFO_RDATAH =((0x15 <<1 )<<1), ++ SATA_MISC_CFIFO_RORW =((0x16 <<1 )<<1), ++ SATA_MISC_CFIFO_ACCESS =((0x17 <<1 )<<1), ++ SATA_MISC_ACCESS_MODE =((0x18 <<1 )<<1), ++ SATA_MISC_AMBA_MUXRST =((0x21 <<1 )<<1), ++ SATA_MISC_HBA_LADDR =((0x24 <<1 )<<1), ++ SATA_MISC_HBA_HADDR =((0x25 <<1 )<<1), ++ SATA_MISC_CMD_LADDR =((0x26 <<1 )<<1), ++ SATA_MISC_CMD_HADDR =((0x27 <<1 )<<1), ++ SATA_MISC_DATA_ADDR =((0x28 <<1 )<<1), ++ SATA_MISC_ENRELOAD =((0x29 <<1 )<<1), ++ SATA_MISC_AMBA_ARBIT =((0x2A <<1 )<<1), ++ SATA_MISC_AMBA_PGEN =((0x30 <<1 )<<1), ++ SATA_MISC_AGEN_F_VAL =((0x35 <<1 )<<1), ++ SATA_MISC_HOST_SWRST =((0x50 <<1 )<<1), ++ SATA_MISC_HOST_NEAR =((0x51 <<1 )<<1), ++ SATA_MISC_FPGA_EN =((0x55 <<1 )<<1), ++}; ++ ++//void MHal_SATA_Clock_Config(phys_addr_t port_base, bool enable); ++//void MHal_SATA_HW_Inital(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++//void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++//phys_addr_t MHal_SATA_bus_address(phys_addr_t phy_address); ++//u32 MHal_SATA_get_max_speed(void); ++ ++#define SSTAR_SATA_DTS_NAME "sstar,sata" ++#define SSTAR_SATA1_DTS_NAME "sstar,sata1" ++ ++#endif +diff --git a/drivers/sstar/sata_host/infinity2/mhal_sata_host_ahci.c b/drivers/sstar/sata_host/infinity2/mhal_sata_host_ahci.c +new file mode 100755 +index 000000000000..362220140790 +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2/mhal_sata_host_ahci.c +@@ -0,0 +1,401 @@ ++/* ++* mdrv_sata_host_ahci.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++//#include "mhal_sata_host_ahci.h" ++#include "mhal_sata_host_ahci.h" ++ ++ ++#if 0 ++u32 ahci_reg_read(void __iomem * p_reg_addr) ++{ ++ u32 data; ++ phys_addr_t reg_addr = (phys_addr_t)p_reg_addr; ++ ++#if defined(CONFIG_ARM64) ++ data = (readw(reg_addr + 0x04) << 16) + readw(reg_addr); ++#else ++ data = (ioread16((void __iomem *)(reg_addr + 0x04))<<16) + ioread16((void __iomem *)reg_addr); ++#endif ++ return data; ++} ++EXPORT_SYMBOL(ahci_reg_read); ++ ++ ++void ahci_reg_write(u32 data, void __iomem * p_reg_addr) ++{ ++ phys_addr_t reg_addr = (phys_addr_t)p_reg_addr; ++ ++#if defined(CONFIG_ARM64) ++ writew(data & 0xFFFF, reg_addr); ++ writew((data >> 16) & 0xFFFF, (reg_addr + 0x04)); ++ ++#else ++ iowrite16(data&0xFFFF, (void __iomem *)reg_addr); ++ iowrite16((data >> 16)&0xFFFF,(void __iomem *)(reg_addr + 0x04)); ++#endif ++} ++EXPORT_SYMBOL(ahci_reg_write); ++#endif ++ ++ ++void MHal_SATA_Clock_Config(phys_addr_t port_base, bool enable) ++{ ++ u16 u16Temp; ++ ++ // Enable MAC Clock, bank is chip dependent ++ // [0] clk gated ++ // [1] clk invert ++ // [4:2] 0: 240M, 1: 216M, 3: clk_miu ++ ++ printk("6+1 [SATA0] Clock : %s\n", (enable ? "ON" : "OFF")); ++ ++ if(enable) ++ { ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~(CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED); ++ u16Temp |= CKG_SATA_FCLK_MIU_P; ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~((CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED) << 8); ++ u16Temp |= (CKG_SATA_FCLK_MIU_P << 8); ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ } ++ else ++ { ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~(CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED); ++ u16Temp |= CKG_SATA_FCLK_GATED; ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~((CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED) << 8); ++ u16Temp |= (CKG_SATA_FCLK_GATED << 8); ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ } ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ printk("[SATA0] Clock : %s\n", (enable ? "ON" : "OFF")); ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ printk("[SATA1] Clock : %s\n", (enable ? "ON" : "OFF")); ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_Clock_Config); ++EXPORT_SYMBOL(MHal_SATA_Clock_Config); ++ ++ ++ ++ ++void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base) ++{ ++ printk("%s misc_base = 0x%X , port_base = 0x%X , hba_base = 0x%X \n", __func__ , misc_base, port_base, hba_base ); ++ // Init FW to trigger controller ++ writew(0x0000, (volatile void *)hba_base + (MS_HOST_CAP)); ++ writew(0x0000, (volatile void *)hba_base + (MS_HOST_CAP + 0x4)); ++ ++ printk("%s host_cap = 0x%X , host_cap + 4 = 0x%X \n", __func__ , readw( (volatile void *)hba_base + (MS_HOST_CAP)) , readw( (volatile void *)hba_base + (MS_HOST_CAP+0x04)) ); ++ ++ // Port Implement ++ writew(0x0001, (volatile void *)hba_base + (MS_HOST_PORTS_IMPL)); ++ writew(0x0000, (volatile void *)port_base + (MS_PORT_CMD)); ++ writew(0x0000, (volatile void *)port_base + (MS_PORT_CMD + 0x4)); ++} ++EXPORT_SYMBOL(MHal_SATA_Setup_Port_Implement); ++#if 0 ++static void ms_sata_clk_enable(void) ++{ ++ // Enable Clock, bank is chip dependent ++ writew(0x000c, (volatile void *)MSTAR_RIU_BASE + (0x100b64 << 1)); // [0] gate ++ // [1] clk invert ++ // [4:2] 0:240M, 1:216M, [3:clk_miu] ++} ++#endif ++#if 0 ++static void ms_sata_clk_disable(void) ++{ ++ MHal_SATA_Clock_Config(SATA_GHC_0_P0_ADDRESS_START, FALSE); ++} ++#endif ++ ++u32 MHal_SATA_get_max_speed(void) ++{ ++ return E_PORT_SPEED_GEN3; ++} ++EXPORT_SYMBOL(MHal_SATA_get_max_speed); ++ ++void ss_sata_misc_init(void *mmio, int phy_mode, int n_ports) ++{ ++ void __iomem *port_base = mmio + 0x200; //102C00<<2 ++ void __iomem *misc_base = mmio + 0x400; //102D00<<2 ++ u16 u16Temp; ++ ++ MHal_SATA_Clock_Config((phys_addr_t)port_base, TRUE); ++ ++ // ECO bit, to fix 1k boundary issue. ++ u16Temp = readw((volatile void *)misc_base + SATA_MISC_AGEN_F_VAL);// ++ u16Temp |= 0x8000;// ++ writew(u16Temp, (volatile void *)misc_base + SATA_MISC_AGEN_F_VAL);// ++ ++ // [1] clk invert ++ // [4:2] 0:240M, 1:216M, [3:clk_miu] ++ writew(0x0001, (volatile void *)misc_base + SATA_MISC_HOST_SWRST);//0x50 a0 ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_HOST_SWRST);//0x50 a0 ++ //writew(0x0001, (volatile void *)misc_base + SATA_MISC_ACCESS_MODE);//0x18 30 ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_AMBA_MUXRST);//0x21 42 ++ writew(0x008C, (volatile void *)misc_base + SATA_MISC_AMBA_ARBIT);//0x2A 54 ++ ++ // AHB Data FIFO Setting ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_HBA_HADDR);//0x25 4a// ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_HBA_LADDR);//0x24 48// ++ writew(0x1800, (volatile void *)misc_base + SATA_MISC_CMD_HADDR);//0x27 4E// ++ writew(0x1000, (volatile void *)misc_base + SATA_MISC_CMD_LADDR);//0x26 4C// ++ writew(0x0000, (volatile void *)misc_base + SATA_MISC_DATA_ADDR);//0x28 50// ++ writew(0x0001, (volatile void *)misc_base + SATA_MISC_ENRELOAD);//0x29 52// ++ writew(0x0001, (volatile void *)misc_base + SATA_MISC_ACCESS_MODE);//0x18 30// ++#if 1 ++ u16Temp = readw((volatile void *)port_base + (0x2c << 1)); ++ u16Temp = u16Temp & (~E_PORT_SPEED_MASK); ++ if(phy_mode == 0) ++ { ++ u16Temp = u16Temp | E_PORT_SPEED_GEN1; ++ } ++ else if(phy_mode == 1) ++ { ++ u16Temp = u16Temp | E_PORT_SPEED_GEN2; ++ } ++ else if(phy_mode == 2) ++ { ++ u16Temp = u16Temp | E_PORT_SPEED_GEN3; ++ } ++ else ++ { ++ u16Temp = u16Temp | MHal_SATA_get_max_speed(); ++ } ++ writew(u16Temp, (volatile void *)port_base + (0x2c << 1)); ++ u16Temp = readw((volatile void *)port_base + (0x2c << 1)); ++ printk("%s MAC SATA SPEED= 0x%x\n", __func__ ,u16Temp); ++#endif ++} ++EXPORT_SYMBOL(ss_sata_misc_init); ++ ++void ss_sata_phy_init(void *mmio, int phy_mode, int n_ports) ++{ ++ u16 u16Temp; ++ phys_addr_t hba_base = (phys_addr_t)mmio; //102B00<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x200); //102C00<<1 ++ u32 GHC_PHY = 0x0; ++ ++ if ((n_ports < 1) || (n_ports > 4)) ++ pr_err("ERROR: PORT num you set is WRONG!!!\n"); ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ } ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ } ++ ++ //printk("sata phy init A\n"); ++ //printk("Gen1 Tx swing\n"); ++ writew(0x2031, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x3803, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x96) << 1)); ++ // EQ BW ++ //printk("Gen1 EQ BW\n"); ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ u16Temp &= ~0x0060; ++ u16Temp |= 0x0020; // default is 0x01 ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ // EQ STR ++ //printk("Gen1 EQ STR\n"); ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ u16Temp &= ~0x001f; ++ u16Temp |= 0x0003; // default is 0x03 ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x92) << 1)); ++ ++ // Gen2 ++ // Tx swing ++ //printk("Gen2 Tx swing\n"); ++ writew(0x3935, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); ++ writew(0x3920, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2e) << 1)); ++ // EQ BW ++ //printk("Gen2 EQ BW\n"); ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x50) << 1)); ++ u16Temp &= ~0x1800; ++ u16Temp |= 0x0800; // default is 0x01 ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x50) << 1)); ++ // EQ STR ++ //printk("Gen2 EQ STR\n"); ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x26) << 1)); ++ u16Temp &= ~0x001f; ++ u16Temp |= 0x0003; // default is 0x03 ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x26) << 1)); ++ ++ // Gen3 ++ // Tx swing ++ //printk("Gen3 Tx swing\n"); ++ writew(0x3937, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x3921, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // EQ BW ++ //printk("Gen3 EQ BW\n"); ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ u16Temp &= ~0x0060; ++ u16Temp |= 0x0000; // default is 0x00 ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ // EQ STR ++ //printk("Gen3 EQ EQ STR\n"); ++ //printk("EQ BW\n"); ++ u16Temp = readw((volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ u16Temp &= ~0x001f; ++ u16Temp |= 0x0003; // default is 0x03 ++ writew(u16Temp, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x98) << 1)); ++ ++ // SSC setup ++#if 1 // new settting to fixed PMP mode issue with JMB575 ++ // STEP1[10:0] ++ writew(0x2002, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x64) << 1)); // [12]: 0 Stop sequence mode, 1: Reverse sequence mode ++ // SET[15:0] ++ writew(0x0aff, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ // SET[23:16] ++ writeb(0x17, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ // SPAN[14:0] ++ writew(0x0495, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x66) << 1)); ++#else ++ writew(0x3007, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x64) << 1)); ++ writew(0xdf0a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ writeb(0x24, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ writew(0x02e8, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x66) << 1)); ++#endif ++ ++ ++ //printk("sata SATA PHY OOB setting ..\n"); ++ writew(0x96de, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ //writew(0x031e, MSTAR_RIU_BASE + (0x103934 << 1)); ++ writew(0x0f20, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x06) << 1)); ++ writew(0x341f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x08) << 1)); ++ ++ //printk("sata SATA PHY setting ..\n"); ++ //asm volatile( "loop: b loop"); ++ ++#if 1 // new setting ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x22) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x24) << 1)); ++ //writew(0x0a3d, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ //writeb(0x17, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ writew(0x9103, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0c) << 1)); ++ writeb(0x06, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3e) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x10) << 1)); // Enable clocks ++#if 0 // ++ writeb(0x0f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); // [10]: OOB pattern select ++ writew(0x848f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x848e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++#else ++ writeb(0x0b, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); // [10]: OOB pattern select ++ writew(0x9a8f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); // [0]: Reset ++ writew(0x9a8e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++#endif ++ writew(0x831e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x68) << 1)); ++ writew(0x031e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0xc0) << 1)); ++ writew(0x031e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0xc2) << 1)); ++ writeb(0x30, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x19) << 1) - 1); ++ //writew(0x9110, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); // new add ++ writeb(0x80, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3c) << 1)); ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x33) << 1) - 1); // [12]: reg_force_tx_oob_pat ++ ++ if(phy_mode == 1) // Gen2 ++ writew(0x9114, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1));// for Gen2 ++ else ++ writew(0x9115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1));// for Gen3 and Gen1 ++ ++ if(phy_mode == 0) // for Gen1 ++ { ++ writew(0x0811, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x1115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x1108, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // Override speed ++ writeb(0x00, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else if(phy_mode == 1) // for Gen2 ++ { ++ writew(0x0811, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x1115, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x1108, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // Override speed ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ else // for Gen3 ++ { ++ writew(0x0811, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x94) << 1)); ++ writew(0x111a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9a) << 1)); ++ writew(0x110a, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x9c) << 1)); ++ // Override speed ++ writeb(0xA0, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x25) << 1) - 1); // 0x00:Gen1, 0x50:Gen2, 0xA0:Gen3 ++ } ++ ++ writew(0x2200, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); // [9]: Enable host ++ ++#else ++ ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x22) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x24) << 1)); ++ writew(0x0a3d, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x60) << 1)); ++ writeb(0x17, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x62) << 1)); ++ writew(0x9103, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0c) << 1)); ++ writeb(0x06, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3e) << 1)); ++ writew(0x0000, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x10) << 1)); // Enable clocks ++ writeb(0x0b, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0b) << 1) - 1); // [10]: OOB pattern select ++ writew(0x9a8f, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); // [0]: Reset ++ writew(0x9a8e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x831e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x68) << 1)); ++ writew(0x031e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0xc0) << 1)); ++ writew(0x031e, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0xc2) << 1)); ++ writeb(0x30, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x19) << 1) - 1); ++ //writew(0x9110, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x2c) << 1)); // new add ++ writeb(0x80, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x3c) << 1)); ++ writeb(0x50, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x33) << 1) - 1); // [12]: reg_force_tx_oob_pat ++ writew(0x2200, (volatile void *)MSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); // [9]: Enable host ++ ++#endif ++ ++ writew(0x0001, (volatile void *) hba_base + MS_HOST_CTL); // reset HBA ++ ++} ++EXPORT_SYMBOL(ss_sata_phy_init); +diff --git a/drivers/sstar/sata_host/infinity2/mhal_sata_host_ahci.h b/drivers/sstar/sata_host/infinity2/mhal_sata_host_ahci.h +new file mode 100755 +index 000000000000..fef08d04e6d4 +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2/mhal_sata_host_ahci.h +@@ -0,0 +1,243 @@ ++/* ++* mhal_sata_host_ahci.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/* MStar reg & func */ ++#ifndef _SATA_AHCI_H ++#define _SATA_AHCI_H ++ ++#if defined(CONFIG_ARM64) ++extern ptrdiff_t mstar_pm_base; ++#define MSTAR_RIU_BASE mstar_pm_base ++#else ++//#define MSTAR_RIU_BASE 0xBF200000 ++//#define MSTAR_RIU_BASE 0x1F000000 ++//#define MSTAR_RIU_BASE 0x1F000000 //JFY ++#define MSTAR_RIU_BASE 0xFD000000 ++#endif ++ ++#define REG_CHIPTOP_BASE 0x100B00 ++ ++#ifndef BIT //for Linux_kernel type, BIT redefined in ++ #define BIT(_bit_) (1 << (_bit_)) ++#endif ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++#define REG_CKG_SATA_FCLK (REG_CHIPTOP_BASE + (0x32<<1)) ++#define CKG_SATA_FCLK_GATED BIT(0) ++#define CKG_SATA_FCLK_INVERT BIT(1) ++#define CKG_SATA_FCLK_MASK BMASK(4:2) ++#define CKG_SATA_FCLK_240MHZ (0 << 2) ++#define CKG_SATA_FCLK_216MHZ (1 << 2) ++#define CKG_SATA_FCLK_MIU_P (3 << 2) ++ ++#define SATA_PORT_BASE_0 0x100000 ++#define SATA_PORT_BASE_1 0x110000 ++ ++#define SATA_GHC_0 0x102B00 ++#define SATA_GHC_0_P0 0x102C00 ++#define SATA_GHC_0_MISC 0x102D00 ++#define SATA_GHC_0_MIUPORT 0x103700 ++#define SATA_GHC_0_PHY 0x103900 ++ ++#define SATA_GHC_1 0x113100 ++#define SATA_GHC_1_P0 0x113200 ++#define SATA_GHC_1_MISC 0x113300 ++#define SATA_GHC_1_MIUPORT 0x113800 ++#define SATA_GHC_1_PHY 0x162A00//0x113900 ++ ++#define SATA_GHC_0_ADDRESS_START (MSTAR_RIU_BASE + (0x102B00 << 1)) ++#define SATA_GHC_0_ADDRESS_END (MSTAR_RIU_BASE + (0x102BFE << 1)) ++#define SATA_GHC_0_P0_ADDRESS_START (MSTAR_RIU_BASE + (0x102C00 << 1)) ++#define SATA_GHC_0_P0_ADDRESS_END (MSTAR_RIU_BASE + (0x102CFE << 1)) ++#define SATA_MISC_0_ADDRESS_START (MSTAR_RIU_BASE + (0x102D00 << 1)) ++#define SATA_MISC_0_ADDRESS_END (MSTAR_RIU_BASE + (0x102DFE << 1)) ++ ++ ++#define SATA_GHC_1_ADDRESS_START (MSTAR_RIU_BASE + (0x113100 << 1)) ++#define SATA_GHC_1_ADDRESS_END (MSTAR_RIU_BASE + (0x1131FE << 1)) ++#define SATA_GHC_1_P0_ADDRESS_START (MSTAR_RIU_BASE + (0x113200 << 1)) ++#define SATA_GHC_1_P0_ADDRESS_END (MSTAR_RIU_BASE + (0x1132FE << 1)) ++#define SATA_MISC_1_ADDRESS_START (MSTAR_RIU_BASE + (0x113300 << 1)) ++#define SATA_MISC_1_ADDRESS_END (MSTAR_RIU_BASE + (0x1133FE << 1)) ++ ++// FIXME: Needs to be removed since K6 does not support XIU mode. ++#if defined(CONFIG_ARM64) ++#define SATA_SDMAP_RIU_BASE mstar_pm_base ++#else ++#define SATA_SDMAP_RIU_BASE MSTAR_RIU_BASE //0xFD000000 ++#endif ++ ++// MIU interval, the gap between MIU0 and MIU1, chip dependent ++#define MIU_INTERVAL_SATA 0x60000000 // for K6 ++ ++// Local Definition, internal SATA MAC SRAM address ++#define AHCI_P0CLB 0x18001000 ++#define AHCI_P0FB 0x18001100 ++#define AHCI_CTBA0 0x18001200 ++ ++#define SATA_PORT_NUM 1 ++#define SATA_CMD_HEADER_SIZE 0x400 ++#define SATA_FIS_SIZE 0x100 ++ ++enum { ++ /* global controller registers */ ++ MS_HOST_CAP = 0x00, /* host capabilities */ ++ MS_HOST_CTL = (0x04 << 1), /* global host control */ ++ MS_HOST_IRQ_STAT = (0x08 << 1), /* interrupt status */ ++ MS_HOST_PORTS_IMPL = (0x0c << 1), /* bitmap of implemented ports */ ++ MS_HOST_VERSION = (0x10 << 1), /* AHCI spec. version compliancy */ ++ MS_HOST_CAP2 = (0x24 << 1), /* host capabilities, extended */ ++ ++ /* HOST_CTL bits - HOST_CAP, 0x00 */ ++ //MS_HOST_RESET = (1 << 0), /* reset controller; self-clear */ ++ //MS_HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ ++ // MS_HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ ++ ++ /* Registers for each SATA port */ ++ MS_PORT_LST_ADDR = 0x00, /* command list DMA addr */ ++ MS_PORT_LST_ADDR_HI = (0x04 << 1), /* command list DMA addr hi */ ++ MS_PORT_FIS_ADDR = (0x08 << 1), /* FIS rx buf addr */ ++ MS_PORT_FIS_ADDR_HI = (0x0c << 1), /* FIS rx buf addr hi */ ++ MS_PORT_IRQ_STAT = (0x10 << 1), /* interrupt status */ ++ MS_PORT_IRQ_MASK = (0x14 << 1), /* interrupt enable/disable mask */ ++ MS_PORT_CMD = (0x18 << 1), /* port command */ ++ MS_PORT_TFDATA = (0x20 << 1), /* taskfile data */ ++ MS_PORT_SIG = (0x24 << 1), /* device TF signature */ ++ MS_PORT_SCR_STAT = (0x28 << 1), /* SATA phy register: SStatus */ ++ MS_PORT_SCR_CTL = (0x2c << 1), /* SATA phy register: SControl */ ++ MS_PORT_SCR_ERR = (0x30 << 1), /* SATA phy register: SError */ ++ MS_PORT_SCR_ACT = (0x34 << 1), /* SATA phy register: SActive */ ++ MS_PORT_CMD_ISSUE = (0x38 << 1), /* command issue */ ++ MS_PORT_SCR_NTF = (0x3c << 1), /* SATA phy register: SNotification */ ++ MS_PORT_DMA_CTRL = (0x70 << 1), /* SATA phy register: SNotification */ ++ ++ /* PORT_CMD bits */ ++ MS_PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ ++ MS_PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ ++ MS_PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ ++ MS_PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ ++ MS_PORT_CMD_PMP = (1 << 17), /* PMP attached */ ++ MS_PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ ++ MS_PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ ++ MS_PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ ++ MS_PORT_CMD_CLO = (1 << 3), /* Command list override */ ++ MS_PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ ++ MS_PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ ++ MS_PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ ++ ++ MS_PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ ++ MS_PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ ++ MS_PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ ++ MS_PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ ++ ++ /* Status Error */ ++ MS_AHCI_PORT_SERR_RDIE = (1 << 0), /* Recovered Data Integrity Error */ ++ MS_AHCI_PORT_SERR_RCE = (1 << 1), /* Recovered Communications Error */ ++ /* Bit 2 ~ 7 Reserved */ ++ MS_AHCI_PORT_SERR_TDIE = (1 << 8), /* Transient Data Integrity Error */ ++ MS_AHCI_PORT_SERR_PCDIE = (1 << 9), /* Persistent Communication or Data Integrity Error */ ++ MS_AHCI_PORT_SERR_PE = (1 << 10), /* Protocol Error */ ++ MS_AHCI_PORT_SERR_IE = (1 << 11), /* Internal Error */ ++ /* Bit 15 ~ 12 Reserved */ ++ MS_AHCI_PORT_SERR_PRDYC = (1 << 16), /* PhyRdy Change */ ++ MS_AHCI_PORT_SERR_PIE = (1 << 17), /* Phy Internal Error */ ++ MS_AHCI_PORT_SERR_COMW = (1 << 18), /* Comm Wake Detect */ ++ MS_AHCI_PORT_SERR_TDE = (1 << 19), /* 10B to 8B Decode Error */ ++ MS_AHCI_PORT_SERR_DE = (1 << 20), /* Disparity Error <= Not Use by AHCI */ ++ MS_AHCI_PORT_SERR_CRCE = (1 << 21), /* CRC Error */ ++ MS_AHCI_PORT_SERR_HE = (1 << 22), /* Handshake Error */ ++ MS_AHCI_PORT_SERR_LSE = (1 << 23), /* Link Sequence Error */ ++ MS_AHCI_PORT_SERR_TSTE = (1 << 24), /* Transport state transition error */ ++ MS_AHCI_PORT_SERR_UFIS = (1 << 25), /* Unknown FIS Type */ ++ MS_AHCI_PORT_SERR_EXC = (1 << 26), /* Exchanged : a change in device presence has been detected */ ++ /* Bit 31 ~ 27 Reserved */ ++}; ++ ++enum { ++ E_PORT_SPEED_MASK = (0xF << 4), ++ E_PORT_SPEED_NO_RESTRICTION = (0x0 < 4), ++ E_PORT_SPEED_GEN1 = (0x1 << 4), ++ E_PORT_SPEED_GEN2 = (0x2 << 4), ++ E_PORT_SPEED_GEN3 = (0x3 << 4), ++ ++ E_PORT_DET_MASK = (0xF << 0), //Device Detection Initialization ++ E_PORT_DET_NODEVICE_DETECT = 0x0, ++ E_PORT_DET_HW_RESET = 0x1, // Cause HW send initial sequence ++ E_PORT_DET_DISABLE_PHY = 0x4, // Put PHY into Offline ++ E_PORT_DET_DEVICE_NOEST = 0x1, // not established ++ E_PORT_DET_DEVICE_EST = 0x3, // established ++ E_PORT_DET_PHY_OFFLINE = 0x4, // Put PHY into Offline ++ ++ DATA_COMPLETE_INTERRUPT = (1 << 31), ++}; ++ ++enum ++{ ++ SATA_MISC_CFIFO_ADDRL =((0x10 <<1 )<<1), ++ SATA_MISC_CFIFO_ADDRH =((0x11 <<1 )<<1), ++ SATA_MISC_CFIFO_WDATAL =((0x12 <<1 )<<1), ++ SATA_MISC_CFIFO_WDATAH =((0x13 <<1 )<<1), ++ SATA_MISC_CFIFO_RDATAL =((0x14 <<1 )<<1), ++ SATA_MISC_CFIFO_RDATAH =((0x15 <<1 )<<1), ++ SATA_MISC_CFIFO_RORW =((0x16 <<1 )<<1), ++ SATA_MISC_CFIFO_ACCESS =((0x17 <<1 )<<1), ++ SATA_MISC_ACCESS_MODE =((0x18 <<1 )<<1), ++ SATA_MISC_AMBA_MUXRST =((0x21 <<1 )<<1), ++ SATA_MISC_HBA_LADDR =((0x24 <<1 )<<1), ++ SATA_MISC_HBA_HADDR =((0x25 <<1 )<<1), ++ SATA_MISC_CMD_LADDR =((0x26 <<1 )<<1), ++ SATA_MISC_CMD_HADDR =((0x27 <<1 )<<1), ++ SATA_MISC_DATA_ADDR =((0x28 <<1 )<<1), ++ SATA_MISC_ENRELOAD =((0x29 <<1 )<<1), ++ SATA_MISC_AMBA_ARBIT =((0x2A <<1 )<<1), ++ SATA_MISC_AMBA_PGEN =((0x30 <<1 )<<1), ++ SATA_MISC_AGEN_F_VAL =((0x35 <<1 )<<1), ++ SATA_MISC_HOST_SWRST =((0x50 <<1 )<<1), ++ SATA_MISC_HOST_NEAR =((0x51 <<1 )<<1), ++ SATA_MISC_FPGA_EN =((0x55 <<1 )<<1), ++}; ++ ++struct ahci_platform_data { ++#if defined(CONFIG_ARCH_INFINITY2) ++ int (*init)(struct device *dev, void __iomem *addr , int id); ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ int (*init)(struct device *dev, void __iomem *addr); ++#endif ++ void (*exit)(struct device *dev); ++ int (*suspend)(struct device *dev); ++ int (*resume)(struct device *dev); ++ const struct ata_port_info *ata_port_info; ++ unsigned int force_port_map; ++ unsigned int mask_port_map; ++}; ++ ++//void mssata_misc_init(void *mmio, int phy_mode, int n_ports); ++//void mssata_phy_init(void __iomem *mmio, int phy_mode, int n_port); ++ ++void MHal_SATA_Clock_Config(phys_addr_t port_base, bool enable); ++void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++u32 MHal_SATA_get_max_speed(void); ++void ss_sata_misc_init(void __iomem *mmio, int phy_mode, int n_ports); ++void ss_sata_phy_init(void __iomem *mmio, int phy_mode, int n_ports); ++ ++#define SSTAR_SATA_DTS_NAME "sstar,sata" ++#define SSTAR_SATA1_DTS_NAME "sstar,sata1" ++ ++u32 ahci_reg_read (void __iomem * p_reg_addr); ++void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ ++#endif +diff --git a/drivers/sstar/sata_host/infinity2m/mhal_sata_host.c b/drivers/sstar/sata_host/infinity2m/mhal_sata_host.c +new file mode 100755 +index 000000000000..aa25ebfda2dc +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2m/mhal_sata_host.c +@@ -0,0 +1,425 @@ ++/* ++* mhal_sata_host.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++#endif ++#define sata_reg_write16(val, addr) { (*((volatile unsigned short*)(addr))) = (unsigned short)(val); } ++#define sata_reg_write8(val, addr) { (*((volatile unsigned char*)(addr))) = (unsigned char)(val);} ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++#define RIU_BASE_ADDR 0xFD000000 ++ ++void _MHal_SATA_Trim_init(void) ++{ ++ u32 u32Efuse_2, u32Efuse_d, u32Efuse_e, u32Efuse_f; ++ u16 u16Temp; ++ ++ CLRREG16(BASE_REG_EFUSE_PA + REG_ID_03, BIT8); //select efuse section 0~7 ++ u32Efuse_2 = INREG16(BASE_REG_EFUSE_PA + REG_ID_08) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_09)) << 16); ++ ++ SETREG16(BASE_REG_EFUSE_PA + REG_ID_03, BIT8); //select efuse section 8,9,A,B,C,D,E,F ++ u32Efuse_d = INREG16(BASE_REG_EFUSE_PA + REG_ID_18) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_19)) << 16); ++ u32Efuse_e = INREG16(BASE_REG_EFUSE_PA + REG_ID_1A) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_1B)) << 16); ++ u32Efuse_f = INREG16(BASE_REG_EFUSE_PA + REG_ID_1C) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_1D)) << 16); ++ ++ if ((u32Efuse_f >> 16) & (0x1<<14)) ++ { ++ // SATA_TX_R50 trim ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0B << 1)); ++ u16Temp |= 0x0010; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0B << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_2A << 1)); ++ u16Temp &= ~(0x0F80); ++ u16Temp |= (u16)(((u32Efuse_2 & 0x03E0) >> 5) << 7); //read bit[9:5] to bit[11:7] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_2A << 1)); ++ printk("SATA_TX_R50 trim=0x%04X\n", (u16)((u32Efuse_2 & 0x03E0) >> 5)); ++ ++ // SATA_RX_R50 trim ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0E << 1)); ++ u16Temp |= 0x0004; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0E << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_3C << 1)); ++ u16Temp &= ~(0x01F0); ++ u16Temp |= (u16)((((u32Efuse_e >> 16) & 0xF800) >> 11) << 4); //read bit[15:11] to bit[8:4] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_3C << 1)); ++ printk("SATA_RX_R50 trim=0x%04X\n", (u16)(((u32Efuse_e >> 16) & 0xF800) >> 11)); ++ ++ // SATA_TX_R50_IBIAS trim ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_46 << 1)); ++ u16Temp |= (0x01 <<13); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_46 << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_50 << 1)); ++ u16Temp &= ~(0xFC00); ++ u16Temp |= (u16)((((u32Efuse_f >> 16) & 0x3F00) >> 8) << 10); //read bit[13:8] to bit[15:10] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_50 << 1)); ++ printk("SATA_TX_R50_IBIAS trim=0x%04X\n", (u16)(((u32Efuse_f >> 16) & 0x3F00) >> 8)); ++ ++ // SATA_RXPLL_ICTRL_CDR trim ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CHIP_INFORM_SHADOW << 1)); ++ if( (u16Temp >> 8 ) == 0 ) ++ u32Efuse_d = 0 ; ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ u16Temp &= ~(0x0070); ++ u16Temp |= (u16)(((u32Efuse_d & 0x00E0) >> 5) << 4); //read bit[7:5] to bit[6:4] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ printk("SATA_RXPLL_ICTRL_CDR trim=0x%04X\n", (u16)((u32Efuse_d & 0x00E0) >> 5) ); ++ } ++ else ++ { ++ // SATA_TX_R50 trim , bit11:7 = 0x10 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0B << 1)); ++ u16Temp |= 0x0010; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0B << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_2A << 1)); ++ u16Temp &= ~(0x0F80); ++ u16Temp |= (u16)( 0x10 << 7); //read bit[9:5] to bit[11:7] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_2A << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_2A << 1)); ++ printk("SATA_TX_R50 trim , trim=0x%04X \n", (u16Temp >> 7) &0x1F ); ++ ++ ++ // SATA_RX_R50 trim , bit8:4 = 0x10 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0E << 1)); ++ u16Temp |= 0x0004; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0E << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_3C << 1)); ++ u16Temp &= ~(0x01F0); ++ u16Temp |= (u16)( 0x10 << 4); //read bit[15:11] to bit[8:4] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_3C << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_3C << 1)); ++ printk("SATA_RX_R50 trim , trim=0x%04X \n", (u16Temp>>4) &0x1F ); ++ ++ ++ // SATA_TX_R50_IBIAS trim , bit15:10 = 0x20 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_46 << 1)); ++ u16Temp |= (0x01 <<13); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_46 << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_50 << 1)); ++ u16Temp &= ~(0xFC00); ++ u16Temp |= (u16)(0x20 << 10); //read bit[13:8] to bit[15:10] ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_50 << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_50 << 1)); ++ printk("SATA_TX_R50_IBIAS trim , trim=0x%04X \n", (u16Temp>>10) &0x3F ); ++ ++ // SATA_RXPLL_ICTRL_CDR trim, U01 bit6:4 = 0x00 , U02 bit6:4 = 0x03 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ u16Temp &= ~(0x0070); ++ if(Chip_Get_Revision() == 0x2) ++ { ++ u16Temp |= (0x3 << 4); // bit[6:4] ++ } ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ printk("SATA_RXPLL_ICTRL_CDR trim=0x%04X \n", (u16Temp>>4) &0x07 ); ++ ++ } ++} ++ ++int _MHal_SATA_Power_On(void) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0; ++ u32 SataClk; ++ struct device_node *dev_node; ++ void *pvSataclk = NULL; ++ u32 SataParentCnt = 1; ++ CAMCLK_Set_Attribute stSetCfg; ++ CAMCLK_Get_Attribute stGetCfg; ++ ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ if(of_find_property(dev_node,"camclk",&SataParentCnt)) ++ { ++ SataParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(SataParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, SataParentCnt); ++ return -ENODEV; ++ } ++ for(u32clknum = 0; u32clknum < SataParentCnt; u32clknum++) ++ { ++ SataClk = 0; ++ of_property_read_u32_index(dev_node,"camclk", u32clknum,&(SataClk)); ++ if (!SataClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamClkRegister("Sata",SataClk,&(pvSataclk)); ++ CamClkAttrGet(pvSataclk,&stGetCfg); ++ CAMCLK_SETPARENT(stSetCfg,stGetCfg.u32Parent[0]); ++ CamClkAttrSet(pvSataclk,&stSetCfg); ++ CamClkSetOnOff(pvSataclk,1); ++ CamClkUnregister(pvSataclk); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ return -ENODEV; ++ } ++ return 0; ++#else ++ struct device_node *dev_node; ++ struct clk **sata_clks; ++ struct clk *clk_parent; ++ int num_parents, i; ++ ++#if CONFIG_OF ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ if (!dev_node) ++ return -ENODEV; ++ ++ num_parents = of_clk_get_parent_count(dev_node); ++ if(num_parents > 0) ++ { ++ sata_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(sata_clks == NULL) ++ { ++ printk( "[SATA0]kzalloc failed!\n" ); ++ return -ENOMEM; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ sata_clks[i] = of_clk_get(dev_node, i); ++ if (IS_ERR(sata_clks[i])) ++ { ++ printk( "Fail to get SATA clk!\n" ); ++ clk_put(sata_clks[i]); ++ kfree(sata_clks); ++ return -ENXIO; ++ } ++ ++ /* Get parent clock */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) ++ clk_parent = clk_hw_get_parent_by_index(__clk_get_hw(sata_clks[i]), 0)->clk; ++#else ++ clk_parent = clk_get_parent_by_index(sata_clks[i], 0); ++#endif ++ if(IS_ERR(clk_parent)) ++ { ++ printk( "[SATA0]can't get parent clock\n" ); ++ clk_put(sata_clks[i]); ++ kfree(sata_clks); ++ return -ENXIO; ++ } ++ /* Set clock parent */ ++ clk_set_parent(sata_clks[i], clk_parent); ++ clk_prepare_enable(sata_clks[i]); ++ clk_put(sata_clks[i]); ++ } ++ kfree(sata_clks); ++ } ++ ++ return 0; ++#else ++ return -1; ++#endif ++#endif ++} ++ ++void MHal_SATA_Clock_Config(phys_addr_t misc_base, phys_addr_t port_base, bool enable) ++{ ++ u16 u16Temp; ++ ++ // Enable MAC Clock, bank is chip dependent ++ // [0] phy clk gated ++ // [1] phy clk invert ++ // [3:2] 0: 108M ++ // [8] clk gated ++ // [9] clk invert ++ // [11:10] 0: 432M ++ ++ if(enable) ++ { ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ //*** Bank 0x1525 h0000 => clear bit 12 ++ u16Temp = readw((volatile void *)misc_base + (0x00 << 2)); ++ u16Temp &= ~(0x1000); // reg_sata_swrst_all ++ writew(u16Temp, (volatile void *)misc_base + (0x00 << 2)); ++ ++ _MHal_SATA_Trim_init();// This function must run after "Bank 0x1525 h0000 => clear bit 12" ++ ++ //*** Bank 0x000E h003D => clear bit 0~5 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_PD_XTAL_HV << 1)); ++ u16Temp &= ~(SATA_HV_CRYSTAL_CLK_MASK); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_PD_XTAL_HV << 1)); ++ ++ if (_MHal_SATA_Power_On()) ++ { ++ printk("[SATA0] Can't control clock with dtb, set registers directly!\n"); ++ ++ //*** Bank 0x1038 h006E => 0x0000 ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_AXI << 1)); ++ ++ //*** Bank 0x1038 h006C => 0x0000 ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_PM << 1)); ++ ++ //*** Bank 0x1038 h0046 => 0x0000 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~(CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED | CKG_SATA_FCLK_PHY_MASK | CKG_SATA_FCLK_PHY_GATED); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ } ++ } ++ } ++ else ++ { ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ //*** Bank 0x000E h003D => set bit 0~5 ++ //u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_PD_XTAL_HV << 1)); ++ //u16Temp |= SATA_HV_CRYSTAL_CLK_MASK; ++ //writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_PD_XTAL_HV << 1)); ++ ++ //*** Bank 0x1038 h0046 => 0x0101 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ u16Temp &= ~(CKG_SATA_FCLK_MASK | CKG_SATA_FCLK_GATED | CKG_SATA_FCLK_PHY_MASK | CKG_SATA_FCLK_PHY_GATED); ++ u16Temp |= (CKG_SATA_FCLK_GATED | CKG_SATA_FCLK_PHY_GATED); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ ++ //*** Bank 0x1525 h0000 => set bit 12 ++ u16Temp = readw((volatile void *)misc_base + (0x00 << 2)); ++ u16Temp |= 0x1000; // reg_sata_swrst_all ++ writew(u16Temp, (volatile void *)misc_base + (0x00 << 2)); ++ } ++ } ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ printk("[SATA0] Clock : %s\n", (enable ? "ON" : "OFF")); ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_Clock_Config); ++ ++u32 MHal_SATA_get_max_speed(void) ++{ ++ return E_PORT_SPEED_GEN3; ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_get_max_speed); ++ ++void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base) ++{ ++ // Init FW to trigger controller ++ writel(0x00000000, (volatile void *)hba_base + (SS_HOST_CAP)); ++ ++ // Port Implement ++ writel(0x00000001, (volatile void *)hba_base + (SS_HOST_PORTS_IMPL)); ++ writel(0x00000000, (volatile void *)port_base + (SS_PORT_CMD)); ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_Setup_Port_Implement); ++ ++#ifndef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++void MHal_SATA_HW_Inital(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base) ++{ ++ //u16 u16Temp; ++ u32 GHC_PHY_ANA = 0x0, u32Temp; ++ int phy_mode; ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ GHC_PHY_ANA = SATA_GHC_0_PHY_ANA;//0x152700 ++ } ++ ++ MHal_SATA_Clock_Config(misc_base, port_base, 1); ++ //u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_CKG_SATA_FCLK << 1)); ++ //printk("SATA_CLK_REG = 0x%x\n", u16Temp); ++ ++ printk("RIU_BASE = 0x%x, GHC_PHY_ANA = 0x%x\n", SSTAR_RIU_BASE, GHC_PHY_ANA); ++ //RIU_BASE = xfd000000, misc_base : xfd205a00 , hba_base : xfd345000 , port_base : xfd345080 , GHC_PHY : 152600 ++ ++ //printk("check sata speed !!!!!!\n"); ++ u32Temp = readl((volatile void *)port_base + 0x2c); ++ u32Temp = u32Temp & (~E_PORT_SPEED_MASK); ++ u32Temp = u32Temp | MHal_SATA_get_max_speed(); ++ writel(u32Temp, (volatile void *)port_base + 0x2c); ++ u32Temp = readl((volatile void *)port_base + 0x2c); ++ printk("MAC SATA SPEED= 0x%x\n", u32Temp); ++ ++ if((u32Temp & E_PORT_SPEED_MASK) == E_PORT_SPEED_GEN1) ++ phy_mode = 0; ++ else if((u32Temp & E_PORT_SPEED_MASK) == E_PORT_SPEED_GEN2) ++ phy_mode = 1; ++ else ++ phy_mode = 2; ++ ++ //printk("sata hal PHY init !!!!!!\n"); ++ //*** Bank 0x1527 h0005 => 0x00:Gen1, 0x01:Gen2, 0x10:Gen3 ++ switch (phy_mode) ++ { ++ case 0: ++ writew(0x00, (volatile void *) GHC_PHY_ANA + (0x05 << 1)); ++ break; ++ case 1: ++ writew(0x01, (volatile void *) GHC_PHY_ANA + (0x05 << 1)); ++ break; ++ case 2: ++ default: ++ writew(0x10, (volatile void *) GHC_PHY_ANA + (0x05 << 1)); ++ break; ++ } ++ ++ writel(0x00000001, (volatile void *) hba_base + SS_HOST_CTL); // reset HBA ++ ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_HW_Inital); ++ ++phys_addr_t MHal_SATA_bus_address(phys_addr_t phy_address) ++{ ++ //phys_addr_t bus_address; ++ ++ //printk("phy addr = 0x%llx\n", phy_address); ++ if (phy_address >= MIU_INTERVAL_SATA) ++ { ++ //printk("select MIU1, bus addr = 0x%8.8x\n", phy_address + 0x20000000); ++ //return phy_address + MIU_INTERVAL_SATA; ++ return phy_address + 0x20000000; ++ } ++ else ++ { ++ //printk("select MIU0, bus addr = 0x%8.8x\n", phy_address - 0x20000000); ++ //return phy_address - MIU_INTERVAL_SATA; ++ return phy_address - 0x20000000; ++ } ++} ++//EXPORT_SYMBOL_GPL(MHal_SATA_bus_address); ++#endif +diff --git a/drivers/sstar/sata_host/infinity2m/mhal_sata_host.h b/drivers/sstar/sata_host/infinity2m/mhal_sata_host.h +new file mode 100755 +index 000000000000..f6c725e414d1 +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2m/mhal_sata_host.h +@@ -0,0 +1,282 @@ ++/* ++* mhal_sata_host.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MHAL_SATA_HOST_H_ ++#define _MHAL_SATA_HOST_H_ ++ ++#define SSTAR_SATA_DTS_NAME "sstar,sata" ++ ++#define SSTAR_RIU_BASE 0xFD000000 ++ ++#define REG_PM_SLEEP_BASE 0x000E00 ++#define REG_PM_TOP_BASE 0x001E00 ++#define REG_CLKGEN_BASE 0x103800 ++ ++#ifndef BIT //for Linux_kernel type, BIT redefined in ++ #define BIT(_bit_) (1 << (_bit_)) ++#endif ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++#define REG_PD_XTAL_HV (REG_PM_SLEEP_BASE + (0x3D<<1)) ++#define SATA_HV_CRYSTAL_CLK_MASK BMASK(5:0) ++ ++#define REG_CHIP_INFORM_SHADOW (REG_PM_TOP_BASE + (0x67<<1)) ++ ++#define REG_CKG_SATA_FCLK (REG_CLKGEN_BASE + (0x46<<1)) ++#define REG_CKG_SATA_PM (REG_CLKGEN_BASE + (0x6C<<1)) ++#define REG_CKG_SATA_AXI (REG_CLKGEN_BASE + (0x6E<<1)) ++#define CKG_SATA_FCLK_PHY_GATED BIT(0) ++#define CKG_SATA_FCLK_PHY_INVERT BIT(1) ++#define CKG_SATA_FCLK_PHY_MASK BMASK(3:2) ++#define CKG_SATA_FCLK_108MHZ (0 << 2) ++#define CKG_SATA_FCLK_GATED BIT(8) ++#define CKG_SATA_FCLK_INVERT BIT(9) ++#define CKG_SATA_FCLK_MASK BMASK(11:10) ++#define CKG_SATA_FCLK_432MHZ (0 << 2) ++ ++#define SATA_GHC_0 0x1A2800 ++#define SATA_GHC_0_P0 0x1A2840 ++#define SATA_GHC_0_MISC 0x152500 ++#define SATA_GHC_0_PHY 0x152600 ++#define SATA_GHC_0_PHY_ANA 0x152700 ++ ++#define REG_SATA_PHYD_REG_0A (SATA_GHC_0_PHY + (0x0A<<1)) ++#define REG_SATA_PHYD_REG_0B (SATA_GHC_0_PHY + (0x0B<<1)) ++#define REG_SATA_PHYD_REG_0E (SATA_GHC_0_PHY + (0x0E<<1)) ++#define REG_SATA_PHYD_REG_26 (SATA_GHC_0_PHY + (0x26<<1)) ++#define REG_SATA_PHYD_REG_2A (SATA_GHC_0_PHY + (0x2A<<1)) ++#define REG_SATA_PHYD_REG_3C (SATA_GHC_0_PHY + (0x3C<<1)) ++#define REG_SATA_PHYD_REG_3E (SATA_GHC_0_PHY + (0x3E<<1)) ++#define REG_SATA_PHYD_REG_40 (SATA_GHC_0_PHY + (0x40<<1)) ++#define REG_SATA_PHYD_REG_46 (SATA_GHC_0_PHY + (0x46<<1)) ++#define REG_SATA_PHYD_REG_50 (SATA_GHC_0_PHY + (0x50<<1)) ++#define REG_SATA_PHYD_REG_61 (SATA_GHC_0_PHY + (0x61<<1)) ++#define REG_SATA_PHYD_REG_64 (SATA_GHC_0_PHY + (0x64<<1)) ++ ++ ++#define REG_SATA_PHY_CLK_PMALIVE_SEL (SATA_GHC_0_PHY_ANA + (0x04<<1)) ++#define REG_SATA_PHY_REG_20 (SATA_GHC_0_PHY_ANA + (0x20<<1)) ++#define REG_SATA_PHY_REG_30 (SATA_GHC_0_PHY_ANA + (0x30<<1)) ++#define REG_SATA_PHY_REG_33 (SATA_GHC_0_PHY_ANA + (0x33<<1)) ++#define REG_SATA_PHY_REG_3E (SATA_GHC_0_PHY_ANA + (0x3E<<1)) ++#define REG_SATA_PHY_SYNTH_SLD (SATA_GHC_0_PHY_ANA + (0x44<<1)) ++#define REG_SATA_PHY_TXPLL_DET_SW (SATA_GHC_0_PHY_ANA + (0x60<<1)) ++#define REG_SATA_PHY_REG_70 (SATA_GHC_0_PHY_ANA + (0x70<<1)) ++ ++// Bank 0x1A28 is x32 riu(32bit) ++#define SATA_GHC_0_ADDRESS_START (SSTAR_RIU_BASE + (0x1A2800 << 1)) ++#define SATA_GHC_0_ADDRESS_END (SSTAR_RIU_BASE + (0x1A283F << 1)) ++#define SATA_GHC_0_P0_ADDRESS_START (SSTAR_RIU_BASE + (0x1A2880 << 1)) ++#define SATA_GHC_0_P0_ADDRESS_END (SSTAR_RIU_BASE + (0x1A28BF << 1)) ++#define SATA_MISC_0_ADDRESS_START (SSTAR_RIU_BASE + (0x152500 << 1)) ++#define SATA_MISC_0_ADDRESS_END (SSTAR_RIU_BASE + (0x1525FE << 1)) ++ ++#define SATA_SDMAP_RIU_BASE SSTAR_RIU_BASE //0xFD000000 ++ ++// MIU interval, the gap between MIU0 and MIU1, chip dependent ++#define MIU_INTERVAL_SATA 0x60000000 // for K6 ++ ++// Local Definition, internal SATA MAC SRAM address ++#define AHCI_P0CLB 0x18001000 ++#define AHCI_P0FB 0x18001100 ++#define AHCI_CTBA0 0x18001200 ++ ++#define SATA_PORT_NUM 1 ++#define SATA_CMD_HEADER_SIZE 0x400 ++#define SATA_FIS_SIZE 0x100 ++ ++enum ++{ ++ /* global controller registers */ ++ SS_HOST_CAP = 0x00, /* host capabilities */ ++ SS_HOST_CTL = 0x04, /* global host control */ ++ SS_HOST_IRQ_STAT = 0x08, /* interrupt status */ ++ SS_HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ ++ SS_HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ ++ SS_HOST_CAP2 = 0x24, /* host capabilities, extended */ ++ ++ /* HOST_CTL bits - HOST_CAP, 0x00 */ ++ //SS_HOST_RESET = (1 << 0), /* reset controller; self-clear */ ++ //SS_HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ ++ //SS_HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ ++ ++ /* Registers for each SATA port */ ++ SS_PORT_LST_ADDR = 0x00, /* command list DMA addr */ ++ SS_PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ ++ SS_PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ ++ SS_PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ ++ SS_PORT_IRQ_STAT = 0x10, /* interrupt status */ ++ SS_PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ ++ SS_PORT_CMD = 0x18, /* port command */ ++ SS_PORT_TFDATA = 0x20, /* taskfile data */ ++ SS_PORT_SIG = 0x24, /* device TF signature */ ++ SS_PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ ++ SS_PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ ++ SS_PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ ++ SS_PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ ++ SS_PORT_CMD_ISSUE = 0x38, /* command issue */ ++ SS_PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ ++ SS_PORT_DMA_CTRL = 0x70, /* SATA phy register: SNotification */ ++ ++ /* PORT_CMD bits */ ++ SS_PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ ++ SS_PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ ++ SS_PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ ++ SS_PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ ++ SS_PORT_CMD_PMP = (1 << 17), /* PMP attached */ ++ SS_PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ ++ SS_PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ ++ SS_PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ ++ SS_PORT_CMD_CLO = (1 << 3), /* Command list override */ ++ SS_PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ ++ SS_PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ ++ SS_PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ ++ ++ SS_PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ ++ SS_PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ ++ SS_PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ ++ SS_PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ ++ ++ /* Status Error */ ++ SS_AHCI_PORT_SERR_RDIE = (1 << 0), /* Recovered Data Integrity Error */ ++ SS_AHCI_PORT_SERR_RCE = (1 << 1), /* Recovered Communications Error */ ++ /* Bit 2 ~ 7 Reserved */ ++ SS_AHCI_PORT_SERR_TDIE = (1 << 8), /* Transient Data Integrity Error */ ++ SS_AHCI_PORT_SERR_PCDIE = (1 << 9), /* Persistent Communication or Data Integrity Error */ ++ SS_AHCI_PORT_SERR_PE = (1 << 10), /* Protocol Error */ ++ SS_AHCI_PORT_SERR_IE = (1 << 11), /* Internal Error */ ++ /* Bit 15 ~ 12 Reserved */ ++ SS_AHCI_PORT_SERR_PRDYC = (1 << 16), /* PhyRdy Change */ ++ SS_AHCI_PORT_SERR_PIE = (1 << 17), /* Phy Internal Error */ ++ SS_AHCI_PORT_SERR_COMW = (1 << 18), /* Comm Wake Detect */ ++ SS_AHCI_PORT_SERR_TDE = (1 << 19), /* 10B to 8B Decode Error */ ++ SS_AHCI_PORT_SERR_DE = (1 << 20), /* Disparity Error <= Not Use by AHCI */ ++ SS_AHCI_PORT_SERR_CRCE = (1 << 21), /* CRC Error */ ++ SS_AHCI_PORT_SERR_HE = (1 << 22), /* Handshake Error */ ++ SS_AHCI_PORT_SERR_LSE = (1 << 23), /* Link Sequence Error */ ++ SS_AHCI_PORT_SERR_TSTE = (1 << 24), /* Transport state transition error */ ++ SS_AHCI_PORT_SERR_UFIS = (1 << 25), /* Unknown FIS Type */ ++ SS_AHCI_PORT_SERR_EXC = (1 << 26), /* Exchanged : a change in device presence has been detected */ ++ /* Bit 31 ~ 27 Reserved */ ++}; ++ ++enum ++{ ++ E_PORT_SPEED_MASK = (0xF << 4), ++ E_PORT_SPEED_NO_RESTRICTION = (0x0 < 4), ++ E_PORT_SPEED_GEN1 = (0x1 << 4), ++ E_PORT_SPEED_GEN2 = (0x2 << 4), ++ E_PORT_SPEED_GEN3 = (0x3 << 4), ++ ++ E_PORT_DET_MASK = (0xF << 0), //Device Detection Initialization ++ E_PORT_DET_NODEVICE_DETECT = 0x0, ++ E_PORT_DET_HW_RESET = 0x1, // Cause HW send initial sequence ++ E_PORT_DET_DISABLE_PHY = 0x4, // Put PHY into Offline ++ E_PORT_DET_DEVICE_NOEST = 0x1, // not established ++ E_PORT_DET_DEVICE_EST = 0x3, // established ++ E_PORT_DET_PHY_OFFLINE = 0x4, // Put PHY into Offline ++ ++ DATA_COMPLETE_INTERRUPT = (1 << 31), ++ ++ /* PORT_IRQ_{STAT,MASK} bits */ ++ //PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ ++ //PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ ++ //PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ ++ //PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ ++ //PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ ++ //PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ ++ //PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ ++ //PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ ++ ++ //PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ ++ //PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ ++ //PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ ++ //PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ ++ //PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ ++ //PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ ++ //PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ ++ //PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ ++ //PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ ++ ++ //PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | ++ // PORT_IRQ_IF_ERR | ++ // PORT_IRQ_CONNECT | ++ // PORT_IRQ_PHYRDY | ++ // PORT_IRQ_UNK_FIS | ++ // PORT_IRQ_BAD_PMP, ++ //PORT_IRQ_ERROR = PORT_IRQ_FREEZE | ++ // PORT_IRQ_TF_ERR | ++ // PORT_IRQ_HBUS_DATA_ERR, ++ //DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | ++ // PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | ++ // PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, ++}; ++ ++ ++/* ++ * Host Controller MISC Register ++ */ ++enum ++{ ++ SATA_MISC_CFIFO_ADDRL =((0x10 <<1 )<<1), ++ SATA_MISC_CFIFO_ADDRH =((0x11 <<1 )<<1), ++ SATA_MISC_CFIFO_WDATAL =((0x12 <<1 )<<1), ++ SATA_MISC_CFIFO_WDATAH =((0x13 <<1 )<<1), ++ SATA_MISC_CFIFO_RDATAL =((0x14 <<1 )<<1), ++ SATA_MISC_CFIFO_RDATAH =((0x15 <<1 )<<1), ++ SATA_MISC_CFIFO_RORW =((0x16 <<1 )<<1), ++ SATA_MISC_CFIFO_ACCESS =((0x17 <<1 )<<1), ++ SATA_MISC_ACCESS_MODE =((0x18 <<1 )<<1), ++ SATA_MISC_AMBA_MUXRST =((0x21 <<1 )<<1), ++ SATA_MISC_HBA_LADDR =((0x24 <<1 )<<1), ++ SATA_MISC_HBA_HADDR =((0x25 <<1 )<<1), ++ SATA_MISC_CMD_LADDR =((0x26 <<1 )<<1), ++ SATA_MISC_CMD_HADDR =((0x27 <<1 )<<1), ++ SATA_MISC_DATA_ADDR =((0x28 <<1 )<<1), ++ SATA_MISC_ENRELOAD =((0x29 <<1 )<<1), ++ SATA_MISC_AMBA_ARBIT =((0x2A <<1 )<<1), ++ SATA_MISC_AMBA_PGEN =((0x30 <<1 )<<1), ++ SATA_MISC_AGEN_F_VAL =((0x35 <<1 )<<1), ++ SATA_MISC_HOST_SWRST =((0x50 <<1 )<<1), ++ SATA_MISC_HOST_NEAR =((0x51 <<1 )<<1), ++ SATA_MISC_FPGA_EN =((0x55 <<1 )<<1), ++}; ++ ++#define INT_SATA_PHY_RST_DONE BIT0 ++#define INT_SATA_PHY_COWAKE BIT1 ++#define INT_SATA_PHY_COMINIT BIT2 ++#define INT_SATA_PHY_SIG_DET BIT3 ++#define INT_SATA_PHY_CALIBRATED BIT5 ++#define INT_SATA_PHY_RX_DATA_VLD_PRE_0 BIT6 ++#define INT_SATA_SYMBOL_LOCK BIT7 ++#define INT_SATA_PHY_RXPLL_LOCK BIT8 ++#define INT_SATA_PHY_RXPLL_FREQ_DET_DONE_FLAG BIT9 ++#define INT_SATA_PHY_RXPLL_FREQ_LOCK_FLAG BIT10 ++#define INT_SATA_PHY_RXPLL_FREQ_UNLOCK_FLAG BIT11 ++#define INT_SATA_PHY_TXPLL_LOCK BIT12 ++#define INT_SATA_PHY_TXPLL_FREQ_DET_DONE_FLAG BIT13 ++#define INT_SATA_PHY_TXPLL_FREQ_LOCK_FLAG BIT14 ++#define INT_SATA_PHY_TXPLL_FREQ_UNLOCK_FLAG BIT15 ++ ++void MHal_SATA_Clock_Config(phys_addr_t misc_base, phys_addr_t port_base, bool enable); ++void MHal_SATA_HW_Inital(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++phys_addr_t MHal_SATA_bus_address(phys_addr_t phy_address); ++u32 MHal_SATA_get_max_speed(void); ++ ++#endif +diff --git a/drivers/sstar/sata_host/infinity2m/mhal_sata_host_ahci.c b/drivers/sstar/sata_host/infinity2m/mhal_sata_host_ahci.c +new file mode 100755 +index 000000000000..08b630a61d55 +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2m/mhal_sata_host_ahci.c +@@ -0,0 +1,133 @@ ++/* ++* mhal_sata_host_ahci.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "mhal_sata_host.h" ++#include "mhal_sata_host_ahci.h" ++ ++//#define USE_MIPSPLL ++ ++#if 0 ++static void ss_sata_clk_enable(void) ++{ ++ // Enable Clock, bank is chip dependent ++ writew(0x000c, (volatile void *)SSTAR_RIU_BASE + (0x100b64 << 1)); // [0] gate ++ // [1] clk invert ++ // [4:2] 0:240M, 1:216M, [3:clk_miu] ++} ++#endif ++#if 0 ++static void ss_sata_clk_disable(void) ++{ ++ MHal_SATA_Clock_Config(SATA_MISC_0_ADDRESS_START, SATA_GHC_0_P0_ADDRESS_START, FALSE); ++} ++#endif ++ ++void ss_sata_misc_init(void *mmio, int n_ports) ++{ ++ void __iomem *port_base = mmio + 0x100; //1A2880<<2 ++ void __iomem *misc_base = mmio - 0xA0600; //152500<<2 ++ ++ MHal_SATA_Clock_Config((phys_addr_t)misc_base, (phys_addr_t)port_base, TRUE); ++} ++ ++void ss_sata_phy_init(void *mmio,int phy_mode, int n_ports) ++{ ++ //phys_addr_t hba_base = (phys_addr_t)mmio; //1A2800<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x100); //1A2880<<1 ++ u32 GHC_PHY_ANA = 0x0; ++ u16 u16Temp; ++ ++ if ((n_ports < 1) || (n_ports > 4)) ++ pr_err("ERROR: PORT num you set is WRONG!!!\n"); ++ ++ if ((phy_mode < 0) || (phy_mode > 2)) ++ { ++ pr_err("%s ERROR: phy_mode set to default!\n" , __func__ ); ++ phy_mode = 2; ++ } ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ GHC_PHY_ANA = SATA_GHC_0_PHY_ANA;//0x152700 ++ } ++ ++ //printk("sata phy init A\n"); ++ ++ //*** Bank 0x1527 h0020 => 0x0100 ++ writew(0x0100, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_20 << 1)); ++ ++ //*** bringup script setting , Bank 0x1527 h0030 => 0x1008 , and need to apply efuse SATA_RXPLL_ICTRL_CDR trim setting ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ u16Temp = (u16Temp & ~0x0F) | 0x0008; ++ u16Temp = u16Temp | 0x1000; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_30 << 1)); ++ ++ //*** Bank 0x1527 h0033 => 0x0500 ++ writew(0x0500, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_33 << 1)); ++ ++ //*** Bank 0x1527 h0060 => 0x0002 ++ writew(0x0002, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_TXPLL_DET_SW << 1)); ++ ++ //*** Bank 0x1527 h0070 => 0x0062 ++ writew(0x0062, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_70 << 1)); ++ ++ //*** Bank 0x1527 h003E => 0x8000 ++ writew(0x8000, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_REG_3E << 1)); ++#ifdef USE_MIPSPLL ++ //*** Bank 0x1032 h0011 => enable bit11 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + ((0x103200 + (0x11<<1)) << 1)); ++ u16Temp |= 0x0800; ++ printk("Bank 0x1032 0x11 = 0x%x\n", u16Temp); ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + ((0x103200 + (0x11<<1)) << 1)); ++ ++ //*** Bank 0x1527 h0004 => 0x0000 ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_CLK_PMALIVE_SEL << 1)); ++#else ++ //*** Bank 0x1527 h0004 => 0x0002 ++ writew(0x0002, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_CLK_PMALIVE_SEL << 1)); ++#endif ++ ++ //*** Bank 0x1527 h0044 => set bit 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_SYNTH_SLD << 1)); ++ u16Temp |= 0x1; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_SYNTH_SLD << 1)); ++ u16Temp &= ~0x1; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHY_SYNTH_SLD << 1)); ++ ++ //*** Bank 0x1526 h000A => 0x440A ++ writew(0x440A, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_0A << 1)); ++ //*** Bank 0x1526 h0026 => 0x1905 ++ writew(0x1905, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_26 << 1)); ++ //*** Bank 0x1526 h003E => 0xB659 ++ writew(0xB659, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_3E << 1)); ++ //*** Bank 0x1526 h0040 => 0xD819 ++ writew(0xD819, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_40 << 1)); ++ //*** Bank 0x1526 h0061 => 0x4000 ++ writew(0x4000, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_61 << 1)); ++ //*** Bank 0x1526 h0064 => 0x0044 ++ writew(0x0044, (volatile void *)SSTAR_RIU_BASE + (REG_SATA_PHYD_REG_64 << 1)); ++ ++ //*** Bank 0x1527 h0005 => 0x0001 ++ writew(phy_mode, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY_ANA + (0x5 << 1)) << 1)); ++ ++} +diff --git a/drivers/sstar/sata_host/infinity2m/mhal_sata_host_ahci.h b/drivers/sstar/sata_host/infinity2m/mhal_sata_host_ahci.h +new file mode 100755 +index 000000000000..94148549ad68 +--- /dev/null ++++ b/drivers/sstar/sata_host/infinity2m/mhal_sata_host_ahci.h +@@ -0,0 +1,47 @@ ++/* ++* mhal_sata_host_ahci.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MHAL_SATA_HOST_AHCI_H ++#define _MHAL_SATA_HOST_AHCI_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct ahci_platform_data { ++#if defined(CONFIG_ARCH_INFINITY2) ++ int (*init)(struct device *dev, void __iomem *addr , int id); ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ int (*init)(struct device *dev, void __iomem *addr); ++#endif ++ void (*exit)(struct device *dev); ++ int (*suspend)(struct device *dev); ++ int (*resume)(struct device *dev); ++ const struct ata_port_info *ata_port_info; ++ unsigned int force_port_map; ++ unsigned int mask_port_map; ++}; ++ ++ ++void ss_sata_misc_init(void *mmio, int n_ports); ++void ss_sata_phy_init(void *mmio,int phy_mode, int n_ports); ++#endif +diff --git a/drivers/sstar/sata_host/mdr_sata_host_ahci_platform.c b/drivers/sstar/sata_host/mdr_sata_host_ahci_platform.c +new file mode 100755 +index 000000000000..ec14a909f380 +--- /dev/null ++++ b/drivers/sstar/sata_host/mdr_sata_host_ahci_platform.c +@@ -0,0 +1,720 @@ ++/* ++* mdrv_sata_host_ahci_platform.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ahci.h" ++ ++ ++//#include "mhal_sata_common.c" ++ ++#include "mhal_sata_host_ahci.h" ++//#include "mhal_sata_host_ahci.c" ++ ++ ++#if defined( CONFIG_ARCH_INFINITY2M) ++#include "mhal_sata_host.h" ++#include "mdrv_sata_host_ahci.h" ++#endif ++ ++ ++#define DRV_NAME "ahci_sstar" ++#define SW_OOB_MODE 0 ++ ++static int n_ports = 1;//config sata ports //TBD ++ ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ //extern u32 ahci_reg_read(phys_addr_t reg_addr); ++ //extern void ahci_reg_write(u32 data, phys_addr_t p_reg_addr);; ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++#endif ++ ++extern void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++ ++ ++ ++ ++struct sstar_ahci_priv { ++ struct device *dev; ++ void __iomem *res_ahci; ++ void __iomem *res_ahci_port0; ++ void __iomem *res_ahci_misc; ++ u32 port_mask; ++}; ++ ++ ++#define SSTAR_AHCI_SHT(drv_name) \ ++ ATA_NCQ_SHT(drv_name), \ ++ .shost_attrs = ahci_shost_attrs, \ ++ .sdev_attrs = ahci_sdev_attrs ++ ++ ++#define SATA_SSTAR_HOST_FLAGS (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | ATA_FLAG_NCQ ) ++ ++ ++//static int ahci_port_max_speed = E_PORT_SPEED_GEN3; ++ ++ ++phys_addr_t sstar_ahci_sata_bus_address(phys_addr_t phy_address) ++{ ++ if (phy_address >= MIU_INTERVAL_SATA) ++ { ++ return phy_address + 0x20000000; ++ } ++ else ++ { ++ return phy_address - 0x20000000; ++ } ++} ++ ++ ++static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) ++{ ++ struct scatterlist *sg; ++ struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; ++ unsigned int si; ++ ++ VPRINTK("ENTER\n"); ++ ++ /* ++ * Next, the S/G list. ++ */ ++ for_each_sg(qc->sg, sg, qc->n_elem, si) { ++ dma_addr_t addr = sg_dma_address(sg); ++ u32 sg_len = sg_dma_len(sg); ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ ahci_sg[si].addr = (u32)(sstar_ahci_sata_bus_address(cpu_to_le32(addr & 0xffffffff))); ++ ahci_sg[si].addr_hi = (u32)(sstar_ahci_sata_bus_address(cpu_to_le32((addr >> 16) >> 16))); ++#else ++ ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); ++ ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); ++#endif ++ ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); ++ } ++ ++ return si; ++} ++ ++#if 0 ++static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct ahci_port_priv *pp = ap->private_data; ++ ++ if (!sata_pmp_attached(ap) || pp->fbs_enabled) ++ return ata_std_qc_defer(qc); ++ else ++ return sata_pmp_qc_defer_cmd_switch(qc); ++} ++#endif ++ ++static void sstar_ahci_qc_prep(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct ahci_port_priv *pp = ap->private_data; ++ int is_atapi = ata_is_atapi(qc->tf.protocol); ++ void *cmd_tbl; ++ u32 opts; ++ const u32 cmd_fis_len = 5; /* five dwords */ ++ unsigned int n_elem; ++ ++ /* ++ * Fill in command table information. First, the header, ++ * a SATA Register - Host to Device command FIS. ++ */ ++ cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; ++ ++ ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); ++ if (is_atapi) { ++ memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); ++ memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); ++ } ++ ++ n_elem = 0; ++ if (qc->flags & ATA_QCFLAG_DMAMAP) ++ n_elem = ahci_fill_sg(qc, cmd_tbl); ++ ++ /* ++ * Fill in command slot information. ++ */ ++ opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); ++ if (qc->tf.flags & ATA_TFLAG_WRITE) ++ opts |= AHCI_CMD_WRITE; ++ if (is_atapi) ++ opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; ++ ++ ahci_fill_cmd_slot(pp, qc->tag, opts); ++} ++ ++static void sstar_ahci_host_stop(struct ata_host *host) ++{ ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ struct device *dev = host->dev; ++ struct ahci_platform_data *pdata = dev_get_platdata(dev); ++#endif ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ if (pdata && pdata->exit) ++ pdata->exit(dev); ++#endif ++ ++ ahci_platform_disable_resources(hpriv); ++} ++ ++static int sstar_ahci_port_start(struct ata_port *ap) ++{ ++ struct ahci_host_priv *hpriv = ap->host->private_data; ++ struct device *dev = ap->host->dev; ++ struct ahci_port_priv *pp; ++ void *mem; ++ dma_addr_t mem_dma; ++ size_t dma_sz, rx_fis_sz; ++ ++ pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); ++ if (!pp) ++ return -ENOMEM; ++ ++ if (ap->host->n_ports > 1) { ++ pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); ++ if (!pp->irq_desc) { ++ devm_kfree(dev, pp); ++ return -ENOMEM; ++ } ++ snprintf(pp->irq_desc, 8, ++ "%s%d", dev_driver_string(dev), ap->port_no); ++ } ++ ++ /* check FBS capability */ ++ if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { ++ void __iomem *port_mmio = ahci_port_base(ap); ++ u32 cmd = readl(port_mmio + PORT_CMD); ++ if (cmd & PORT_CMD_FBSCP) ++ pp->fbs_supported = true; ++ else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { ++ dev_info(dev, "port %d can do FBS, forcing FBSCP\n", ++ ap->port_no); ++ pp->fbs_supported = true; ++ } else ++ dev_warn(dev, "port %d is not capable of FBS\n", ++ ap->port_no); ++ } ++ ++ if (pp->fbs_supported) { ++ dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; ++ rx_fis_sz = AHCI_RX_FIS_SZ * 16; ++ } else { ++ dma_sz = AHCI_PORT_PRIV_DMA_SZ; ++ rx_fis_sz = AHCI_RX_FIS_SZ; ++ } ++ ++ mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); ++ if (!mem) ++ return -ENOMEM; ++ memset(mem, 0, dma_sz); ++ ++ /* ++ * First item in chunk of DMA memory: 32-slot command table, ++ * 32 bytes each in size ++ */ ++ pp->cmd_slot = mem; ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ // Translate physical address to bus address since SATA engine uses bus address. ++ mem_dma = (dma_addr_t)sstar_ahci_sata_bus_address(mem_dma); ++#endif ++ pp->cmd_slot_dma = mem_dma; ++ ++ mem += AHCI_CMD_SLOT_SZ; ++ mem_dma += AHCI_CMD_SLOT_SZ; ++ ++ /* ++ * Second item: Received-FIS area ++ */ ++ pp->rx_fis = mem; ++ pp->rx_fis_dma = mem_dma; ++ ++ mem += rx_fis_sz; ++ mem_dma += rx_fis_sz; ++ ++ /* ++ * Third item: data area for storing a single command ++ * and its scatter-gather table ++ */ ++ pp->cmd_tbl = mem; ++ pp->cmd_tbl_dma = mem_dma; ++ ++ /* ++ * Save off initial list of interrupts to be enabled. ++ * This could be changed later ++ */ ++ pp->intr_mask = DEF_PORT_IRQ; ++ ++ /* ++ * Switch to per-port locking in case each port has its own MSI vector. ++ */ ++ if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { ++ spin_lock_init(&pp->lock); ++ ap->lock = &pp->lock; ++ } ++ ++ ap->private_data = pp; ++ ++ /* engage engines, captain */ ++ return ahci_port_resume(ap); ++} ++ ++ ++struct ata_port_operations sstar_ahci_platform_ops = { ++ .inherits = &ahci_ops, ++ .qc_prep = sstar_ahci_qc_prep, ++// .thaw = sstar_ahci_thaw, ++ //.softreset = sstar_ahci_softreset, ++ //.pmp_softreset = sstar_ahci_softreset, ++ .host_stop = sstar_ahci_host_stop, ++#ifdef CONFIG_PM ++// .port_suspend = ahci_port_suspend, this no need ++// .port_resume = sstar_ahci_port_resume, ++#endif ++ .port_start = sstar_ahci_port_start, ++}; ++ ++ ++static const struct ata_port_info ahci_port_info = ++{ ++ .flags = SATA_SSTAR_HOST_FLAGS, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &sstar_ahci_platform_ops, ++}; ++ ++ ++static struct scsi_host_template ahci_platform_sht = { ++ SSTAR_AHCI_SHT(DRV_NAME), ++ .can_queue = 31,//SATA_SSTAR_QUEUE_DEPTH, ++ .sg_tablesize = 128, //SATA_SSTAR_USED_PRD, ++ .dma_boundary = 0xffffUL, //ATA_DMA_BOUNDARY, ++}; ++ ++ ++ ++static u32 sstar_sata_wait_reg(phys_addr_t reg_addr, u32 mask, u32 val, unsigned long interval, unsigned long timeout) ++{ ++ u32 temp; ++ unsigned long timeout_vale = 0; ++ ++ temp = readl((void *)reg_addr); ++ ++ while((temp & mask) == val) ++ { ++ msleep(interval); ++ timeout_vale += interval; ++ if (timeout_vale > timeout) ++ break; ++ temp = readl((void *)reg_addr); ++ } ++ return temp; ++} ++ ++int __ss_sata_get_phy_mode(void) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int phy_mode = 2; ++ ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ ++ of_property_read_u32(dev_node, "phy_mode", &phy_mode); ++ ++ printk("[SATA] phy_mode =%d\n", phy_mode); ++ return phy_mode; ++} ++ ++ ++//int ss_sata_init(void __iomem *mmio) ++//int ss_sata_init(struct device *dev, void __iomem *mmio, int id) ++static int ss_sata_init(void __iomem *mmio) ++{ ++ u32 i; ++ u32 u32Temp = 0; ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ phys_addr_t hba_base = (phys_addr_t)mmio; //102B00<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x200); //102C00<<1 ++ phys_addr_t misc_base = (phys_addr_t)(mmio + 0x400); //102D00<<1 ++ int port_num; ++ int phy_mode =2; ++ ++ port_num = n_ports; ++ ++ pr_info("[%s] , hba_base =0x%X \n", __func__ , hba_base ); ++ pr_info("[%s] , port_base =0x%X \n", __func__ , port_base ); ++ pr_info("[%s] , misc_base =0x%X \n", __func__ , misc_base ); ++ ++ //printk("sstar sata HW settings start!!!\n"); ++ ss_sata_misc_init(mmio, phy_mode, port_num); ++ ss_sata_phy_init(mmio, phy_mode, port_num); ++ ++ // AHCI init ++ writew(HOST_RESET, (volatile void *)mmio + (HOST_CTL)); ++ ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ phys_addr_t hba_base = (phys_addr_t)mmio; //1A2800<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x100); //1A2880<<1 ++ phys_addr_t misc_base = (phys_addr_t)(mmio - 0xA0600); //152500<<1 ++ int port_num; ++ int phy_mode =2; ++ ++ port_num = n_ports; ++ ++ phy_mode = __ss_sata_get_phy_mode(); ++ ++ //printk("sstar sata HW settings start!!!\n"); ++ ss_sata_misc_init(mmio, port_num); ++ ss_sata_phy_init(mmio, phy_mode,port_num); ++ ++ // AHCI init ++ writew(HOST_RESET, (volatile void *)hba_base + (HOST_CTL)); ++#endif ++ ++ ++ #if 0 ++ writel(0x00000000, (volatile void *)hba_base + (HOST_CAP)); ++ writel(0x00000001, (volatile void *)hba_base + (HOST_PORTS_IMPL)); ++ writel(0x00000001, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x00000000, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x02100000, (volatile void *)port_base + (PORT_LST_ADDR)); ++ writel(0x02000000, (volatile void *)port_base + (PORT_FIS_ADDR)); ++ writel(0x00000016, (volatile void *)port_base + (PORT_CMD)); ++ #endif ++ #if (SW_OOB_MODE == 1) ++ sstar_sata_sw_oob_mode1(); ++ #elif (SW_OOB_MODE == 2) ++ sstar_sata_sw_oob_mode2(); ++ #else ++ u32Temp = sstar_sata_wait_reg(HOST_CTL + (phys_addr_t)mmio, HOST_RESET, HOST_RESET, 1, 500); ++ if (u32Temp & HOST_RESET) ++ { ++ printk("SATA host reset fail!\n"); ++ return -1; ++ } ++ #endif ++ ++ // Turn on AHCI_EN ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ { ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ goto SS_HOST_AHCI_EN_DONE; ++ } ++ ++ // Try AHCI_EN Trurn on for a few time ++ for (i = 0; i < 5; i++) ++ { ++ u32Temp |= HOST_AHCI_EN; ++ writel(u32Temp, (void *)HOST_CTL + (phys_addr_t)hba_base); ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ break; ++ msleep(10); ++ } ++ ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ ++SS_HOST_AHCI_EN_DONE: ++ printk("sstar sata HW settings done!!!\n"); ++ return 0; ++} ++//EXPORT_SYMBOL(ss_sata_init); ++ ++ ++ ++#if defined(CONFIG_ARCH_INFINITY2M) && defined(CONFIG_PM_SLEEP) ++static int sstar_ahci_suspend(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ struct brcm_ahci_priv *priv = hpriv->plat_data; ++ int ret; ++ ++ ret = ahci_platform_suspend(dev); ++ ++ //brcm_sata_phys_disable(priv); ++ return ret; ++} ++ ++static int sstar_ahci_resume(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ struct brcm_ahci_priv *priv = hpriv->plat_data; ++ ++ //brcm_sata_init(priv); ++ //brcm_sata_phys_enable(priv); ++ //brcm_sata_alpm_init(hpriv); ++ return ahci_platform_resume(dev); ++} ++#endif ++ ++ ++#if defined(CONFIG_ARCH_INFINITY2) && defined(CONFIG_PM_SLEEP) ++static int sstar_ahci_suspend(struct device *dev) ++{ ++ struct ahci_platform_data *pdata = dev_get_platdata(dev); ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ void __iomem *mmio = hpriv->mmio; ++ u32 ctl; ++ int rc; ++ ++ if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) ++ { ++ dev_err(dev, "firmware update required for suspend/resume\n"); ++ return -EIO; ++ } ++ ++ /* ++ * AHCI spec rev1.1 section 8.3.3: ++ * Software must disable interrupts prior to requesting a ++ * transition of the HBA to D3 state. ++ */ ++ ctl = readl(mmio + HOST_CTL); ++ ctl &= ~HOST_IRQ_EN; ++ writel(ctl, mmio + HOST_CTL); ++ readl(mmio + HOST_CTL); /* flush */ ++ ++ rc = ata_host_suspend(host, PMSG_SUSPEND); ++ if (rc) ++ return rc; ++ ++ if (pdata && pdata->suspend) ++ return pdata->suspend(dev); ++ ++ if (!IS_ERR(hpriv->clk)) ++ clk_disable_unprepare(hpriv->clk); ++ ++ return 0; ++} ++ ++static int sstar_ahci_resume(struct device *dev) ++{ ++ struct ahci_platform_data *pdata = dev_get_platdata(dev); ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ int rc; ++ ++ if (!IS_ERR(hpriv->clk)) ++ { ++ rc = clk_prepare_enable(hpriv->clk); ++ if (rc) ++ { ++ dev_err(dev, "clock prepare enable failed"); ++ return rc; ++ } ++ } ++ ++ if (pdata && pdata->resume) ++ { ++ rc = pdata->resume(dev); ++ if (rc) ++ goto disable_unprepare_clk; ++ } ++ ++ if (dev->power.power_state.event == PM_EVENT_SUSPEND) ++ { ++ rc = ahci_reset_controller(host); ++ if (rc) ++ goto disable_unprepare_clk; ++ ++ ahci_init_controller(host); ++ } ++ ++ ata_host_resume(host); ++ ++ return 0; ++ ++disable_unprepare_clk: ++ if (!IS_ERR(hpriv->clk)) ++ clk_disable_unprepare(hpriv->clk); ++ ++ return rc; ++} ++#endif ++ ++ ++ ++ ++static SIMPLE_DEV_PM_OPS(ahci_sstar_pm_ops, sstar_ahci_suspend, sstar_ahci_resume); ++ ++static const struct of_device_id ahci_of_match[] = { ++// { .compatible = "generic-ahci", }, ++ { .compatible = "sstar,sata", }, ++ /* Keep the following compatibles for device tree compatibility */ ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, ahci_of_match); ++ ++ ++static int ahci_sstar_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *of_id; ++ struct device *dev = &pdev->dev; ++ struct sstar_ahci_priv *priv; ++ struct ahci_host_priv *hpriv; ++ struct resource *res; ++ int phy_mode = 2; ++ int ret; ++ // int rc; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ of_id = of_match_node(ahci_of_match, pdev->dev.of_node); ++ if (!of_id) ++ return -ENODEV; ++ ++ priv->dev = dev; ++ ++// res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci"); ++// priv->res_ahci = devm_ioremap_resource(dev, res); ++// if (IS_ERR(priv->res_ahci)) ++// return PTR_ERR(priv->res_ahci); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci_port0"); ++ priv->res_ahci_port0 = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->res_ahci_port0)) ++ return PTR_ERR(priv->res_ahci_port0); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci_misc"); ++ priv->res_ahci_misc = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->res_ahci_misc)) ++ return PTR_ERR(priv->res_ahci_misc); ++ ++ // pr_info("[%s] , priv->res_ahci =0x%p \n", __func__ , priv->res_ahci ); ++ pr_info("[%s] , priv->res_ahci_port0 =0x%p \n", __func__ , priv->res_ahci_port0 ); ++ pr_info("[%s] , priv->res_ahci_misc =0x%p \n", __func__ , priv->res_ahci_misc ); ++ ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ ss_sata_init(priv->res_ahci_port0 - 0x200 ); ++#else ++ ss_sata_init(priv->res_ahci_port0 - 0x100 ); ++#endif ++ ++ hpriv = ahci_platform_get_resources(pdev); ++ if (IS_ERR(hpriv)) ++ return PTR_ERR(hpriv); ++ ++ hpriv->plat_data = priv; ++ hpriv->bFirstOOB= 1; ++ phy_mode = __ss_sata_get_phy_mode(); ++ hpriv->phy_mode = phy_mode; ++ ++ ret = ahci_platform_enable_resources(hpriv); ++ if (ret) ++ return ret; ++ ++ ret = ahci_platform_init_host(pdev, hpriv, &ahci_port_info, &ahci_platform_sht); ++ if (ret) ++ { ++ goto disable_resources; ++ } ++ ++ ++ pr_info("[%s] , SSTAR AHCI SATA registered \n", __func__ ); ++ ++ return 0; ++ ++disable_resources: ++ ahci_platform_disable_resources(hpriv); ++ return ret; ++} ++ ++ ++ ++static const struct acpi_device_id ahci_acpi_match[] = { ++ { ACPI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff) }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(acpi, ahci_acpi_match); ++ ++ ++ ++ ++ ++ ++static int sstar_ahci_remove(struct platform_device *pdev) ++{ ++// struct ata_host *host = dev_get_drvdata(&pdev->dev); ++// struct ahci_host_priv *hpriv = host->private_data; ++// struct brcm_ahci_priv *priv = hpriv->plat_data; ++ int ret; ++ ++ ret = ata_platform_remove_one(pdev); ++ if (ret) ++ return ret; ++ ++ //brcm_sata_phys_disable(priv); ++ ++ return 0; ++} ++ ++static struct platform_driver ahci_driver = { ++ .probe = ahci_sstar_probe, ++ .remove = sstar_ahci_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .of_match_table = ahci_of_match, ++ .acpi_match_table = ahci_acpi_match, ++ .pm = &ahci_sstar_pm_ops, ++ }, ++}; ++module_platform_driver(ahci_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("sstar Semiconductor"); ++MODULE_DESCRIPTION("AHCI SATA platform driver"); ++ ++ +diff --git a/drivers/sstar/sata_host/mdr_sata_host_ahci_platform1.c b/drivers/sstar/sata_host/mdr_sata_host_ahci_platform1.c +new file mode 100755 +index 000000000000..bc734327614e +--- /dev/null ++++ b/drivers/sstar/sata_host/mdr_sata_host_ahci_platform1.c +@@ -0,0 +1,671 @@ ++/* ++* mdrv_sata_host_ahci_platform1.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ahci.h" ++ ++//#include "mhal_sata_common.c" ++#include "mhal_sata_host_ahci.h" ++//#include "mhal_sata_host_ahci.c" ++ ++ ++#if defined( CONFIG_ARCH_INFINITY2M) ++#include "mhal_sata_host.h" ++#include "mdrv_sata_host_ahci.h" ++#endif ++ ++ ++#define DRV_NAME1 "ahci_sstar1" ++#define SW_OOB_MODE 0 ++ ++static int n_ports = 1;//config sata ports //TBD ++ ++ ++//#ifdef CONFIG_ARCH_INFINITY2 ++#if 1 ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ //extern u32 ahci_reg_read(phys_addr_t reg_addr); ++ //extern void ahci_reg_write(u32 data, phys_addr_t p_reg_addr);; ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++#endif ++ ++//extern void MHal_SATA_Setup_Port_Implement(phys_addr_t misc_base, phys_addr_t port_base, phys_addr_t hba_base); ++ ++ ++struct sstar_ahci_priv { ++ struct device *dev; ++ void __iomem *res_ahci; ++ void __iomem *res_ahci_port0; ++ void __iomem *res_ahci_misc; ++ u32 port_mask; ++}; ++ ++ ++#define SSTAR_AHCI_SHT(drv_name) \ ++ ATA_NCQ_SHT(drv_name), \ ++ .shost_attrs = ahci_shost_attrs, \ ++ .sdev_attrs = ahci_sdev_attrs ++ ++ ++#define SATA_SSTAR_HOST_FLAGS (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | ATA_FLAG_NCQ ) ++ ++ ++//static int ahci_port_max_speed = E_PORT_SPEED_GEN3; ++ ++ ++ ++phys_addr_t sstar_ahci_sata_bus_address1(phys_addr_t phy_address) ++{ ++ if (phy_address >= MIU_INTERVAL_SATA) ++ { ++ return phy_address + 0x20000000; ++ } ++ else ++ { ++ return phy_address - 0x20000000; ++ } ++} ++ ++ ++static unsigned int ahci_fill_sg1(struct ata_queued_cmd *qc, void *cmd_tbl) ++{ ++ struct scatterlist *sg; ++ struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; ++ unsigned int si; ++ ++ VPRINTK("ENTER\n"); ++ ++ /* ++ * Next, the S/G list. ++ */ ++ for_each_sg(qc->sg, sg, qc->n_elem, si) { ++ dma_addr_t addr = sg_dma_address(sg); ++ u32 sg_len = sg_dma_len(sg); ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ ahci_sg[si].addr = (u32)(sstar_ahci_sata_bus_address1(cpu_to_le32(addr & 0xffffffff))); ++ ahci_sg[si].addr_hi = (u32)(sstar_ahci_sata_bus_address1(cpu_to_le32((addr >> 16) >> 16))); ++#else ++ ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); ++ ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); ++#endif ++ ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); ++ } ++ ++ return si; ++} ++ ++#if 0 ++static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct ahci_port_priv *pp = ap->private_data; ++ ++ if (!sata_pmp_attached(ap) || pp->fbs_enabled) ++ return ata_std_qc_defer(qc); ++ else ++ return sata_pmp_qc_defer_cmd_switch(qc); ++} ++#endif ++ ++static void sstar_ahci_qc_prep1(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct ahci_port_priv *pp = ap->private_data; ++ int is_atapi = ata_is_atapi(qc->tf.protocol); ++ void *cmd_tbl; ++ u32 opts; ++ const u32 cmd_fis_len = 5; /* five dwords */ ++ unsigned int n_elem; ++ ++ /* ++ * Fill in command table information. First, the header, ++ * a SATA Register - Host to Device command FIS. ++ */ ++ cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; ++ ++ ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); ++ if (is_atapi) { ++ memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); ++ memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); ++ } ++ ++ n_elem = 0; ++ if (qc->flags & ATA_QCFLAG_DMAMAP) ++ n_elem = ahci_fill_sg1(qc, cmd_tbl); ++ ++ /* ++ * Fill in command slot information. ++ */ ++ opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); ++ if (qc->tf.flags & ATA_TFLAG_WRITE) ++ opts |= AHCI_CMD_WRITE; ++ if (is_atapi) ++ opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; ++ ++ ahci_fill_cmd_slot(pp, qc->tag, opts); ++} ++ ++static void sstar_ahci_host_stop1(struct ata_host *host) ++{ ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ struct device *dev = host->dev; ++ struct ahci_platform_data *pdata = dev_get_platdata(dev); ++#endif ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ if (pdata && pdata->exit) ++ pdata->exit(dev); ++#endif ++ ++ ahci_platform_disable_resources(hpriv); ++} ++ ++static int sstar_ahci_port_start1(struct ata_port *ap) ++{ ++ struct ahci_host_priv *hpriv = ap->host->private_data; ++ struct device *dev = ap->host->dev; ++ struct ahci_port_priv *pp; ++ void *mem; ++ dma_addr_t mem_dma; ++ size_t dma_sz, rx_fis_sz; ++ ++ pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); ++ if (!pp) ++ return -ENOMEM; ++ ++ if (ap->host->n_ports > 1) { ++ pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); ++ if (!pp->irq_desc) { ++ devm_kfree(dev, pp); ++ return -ENOMEM; ++ } ++ snprintf(pp->irq_desc, 8, ++ "%s%d", dev_driver_string(dev), ap->port_no); ++ } ++ ++ /* check FBS capability */ ++ if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { ++ void __iomem *port_mmio = ahci_port_base(ap); ++ u32 cmd = readl(port_mmio + PORT_CMD); ++ if (cmd & PORT_CMD_FBSCP) ++ pp->fbs_supported = true; ++ else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { ++ dev_info(dev, "port %d can do FBS, forcing FBSCP\n", ++ ap->port_no); ++ pp->fbs_supported = true; ++ } else ++ dev_warn(dev, "port %d is not capable of FBS\n", ++ ap->port_no); ++ } ++ ++ if (pp->fbs_supported) { ++ dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; ++ rx_fis_sz = AHCI_RX_FIS_SZ * 16; ++ } else { ++ dma_sz = AHCI_PORT_PRIV_DMA_SZ; ++ rx_fis_sz = AHCI_RX_FIS_SZ; ++ } ++ ++ mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); ++ if (!mem) ++ return -ENOMEM; ++ memset(mem, 0, dma_sz); ++ ++ /* ++ * First item in chunk of DMA memory: 32-slot command table, ++ * 32 bytes each in size ++ */ ++ pp->cmd_slot = mem; ++#ifdef CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++ // Translate physical address to bus address since SATA engine uses bus address. ++ mem_dma = (dma_addr_t)sstar_ahci_sata_bus_address1(mem_dma); ++#endif ++ pp->cmd_slot_dma = mem_dma; ++ ++ mem += AHCI_CMD_SLOT_SZ; ++ mem_dma += AHCI_CMD_SLOT_SZ; ++ ++ /* ++ * Second item: Received-FIS area ++ */ ++ pp->rx_fis = mem; ++ pp->rx_fis_dma = mem_dma; ++ ++ mem += rx_fis_sz; ++ mem_dma += rx_fis_sz; ++ ++ /* ++ * Third item: data area for storing a single command ++ * and its scatter-gather table ++ */ ++ pp->cmd_tbl = mem; ++ pp->cmd_tbl_dma = mem_dma; ++ ++ /* ++ * Save off initial list of interrupts to be enabled. ++ * This could be changed later ++ */ ++ pp->intr_mask = DEF_PORT_IRQ; ++ ++ /* ++ * Switch to per-port locking in case each port has its own MSI vector. ++ */ ++ if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { ++ spin_lock_init(&pp->lock); ++ ap->lock = &pp->lock; ++ } ++ ++ ap->private_data = pp; ++ ++ /* engage engines, captain */ ++ return ahci_port_resume(ap); ++} ++ ++ ++struct ata_port_operations sstar_ahci_platform_ops1 = { ++ .inherits = &ahci_ops, ++ .qc_prep = sstar_ahci_qc_prep1, ++// .thaw = sstar_ahci_thaw, ++ //.softreset = sstar_ahci_softreset, ++ //.pmp_softreset = sstar_ahci_softreset, ++ .host_stop = sstar_ahci_host_stop1, ++#ifdef CONFIG_PM ++// .port_suspend = ahci_port_suspend, this no need ++// .port_resume = sstar_ahci_port_resume, ++#endif ++ .port_start = sstar_ahci_port_start1, ++}; ++ ++ ++static const struct ata_port_info ahci_port_info1 = ++{ ++ .flags = SATA_SSTAR_HOST_FLAGS, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &sstar_ahci_platform_ops1, ++}; ++ ++ ++static struct scsi_host_template ahci_platform_sht1 = { ++ SSTAR_AHCI_SHT(DRV_NAME1), ++ .can_queue = 31,//SATA_SSTAR_QUEUE_DEPTH, ++ .sg_tablesize = 128, //SATA_SSTAR_USED_PRD, ++ .dma_boundary = 0xffffUL, //ATA_DMA_BOUNDARY, ++}; ++ ++ ++ ++static u32 sstar_sata_wait_reg1(phys_addr_t reg_addr, u32 mask, u32 val, unsigned long interval, unsigned long timeout) ++{ ++ u32 temp; ++ unsigned long timeout_vale = 0; ++ ++ temp = readl((void *)reg_addr); ++ ++ while((temp & mask) == val) ++ { ++ msleep(interval); ++ timeout_vale += interval; ++ if (timeout_vale > timeout) ++ break; ++ temp = readl((void *)reg_addr); ++ } ++ return temp; ++} ++ ++//int ss_sata_init(void __iomem *mmio) ++//int ss_sata_init(struct device *dev, void __iomem *mmio, int id) ++static int ss_sata_init1(void __iomem *mmio) ++{ ++ u32 i; ++ u32 u32Temp = 0; ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ phys_addr_t hba_base = (phys_addr_t)mmio; //102B00<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x200); //102C00<<1 ++ phys_addr_t misc_base = (phys_addr_t)(mmio + 0x400); //102D00<<1 ++ int port_num; ++ int phy_mode =2; ++ ++ port_num = n_ports; ++ ++ pr_info("[%s] , hba_base =0x%X \n", __func__ , hba_base ); ++ pr_info("[%s] , port_base =0x%X \n", __func__ , port_base ); ++ pr_info("[%s] , misc_base =0x%X \n", __func__ , misc_base ); ++ ++ //printk("sstar sata HW settings start!!!\n"); ++ ss_sata_misc_init(mmio, phy_mode, port_num); ++ ss_sata_phy_init(mmio, phy_mode, port_num); ++ ++ // AHCI init ++ writew(HOST_RESET, (volatile void *)mmio + (HOST_CTL)); ++#endif ++ ++ #if 0 ++ writel(0x00000000, (volatile void *)hba_base + (HOST_CAP)); ++ writel(0x00000001, (volatile void *)hba_base + (HOST_PORTS_IMPL)); ++ writel(0x00000001, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x00000000, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x02100000, (volatile void *)port_base + (PORT_LST_ADDR)); ++ writel(0x02000000, (volatile void *)port_base + (PORT_FIS_ADDR)); ++ writel(0x00000016, (volatile void *)port_base + (PORT_CMD)); ++ #endif ++ #if (SW_OOB_MODE == 1) ++ sstar_sata_sw_oob_mode1(); ++ #elif (SW_OOB_MODE == 2) ++ sstar_sata_sw_oob_mode2(); ++ #else ++ u32Temp = sstar_sata_wait_reg1(HOST_CTL + (phys_addr_t)mmio, HOST_RESET, HOST_RESET, 1, 500); ++ if (u32Temp & HOST_RESET) ++ { ++ printk("SATA host reset fail!\n"); ++ return -1; ++ } ++ #endif ++ ++ // Turn on AHCI_EN ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ { ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ goto SS_HOST_AHCI_EN_DONE; ++ } ++ ++ // Try AHCI_EN Trurn on for a few time ++ for (i = 0; i < 5; i++) ++ { ++ u32Temp |= HOST_AHCI_EN; ++ writel(u32Temp, (void *)HOST_CTL + (phys_addr_t)hba_base); ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ break; ++ msleep(10); ++ } ++ ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ ++SS_HOST_AHCI_EN_DONE: ++ printk("sstar sata HW settings done!!!\n"); ++ return 0; ++} ++//EXPORT_SYMBOL(ss_sata_init); ++ ++ ++ ++#if defined(CONFIG_ARCH_INFINITY2M) && defined(CONFIG_PM_SLEEP) ++static int sstar_ahci_suspend1(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ struct brcm_ahci_priv *priv = hpriv->plat_data; ++ int ret; ++ ++ ret = ahci_platform_suspend(dev); ++ ++ //brcm_sata_phys_disable(priv); ++ return ret; ++} ++ ++static int sstar_ahci_resume1(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ struct brcm_ahci_priv *priv = hpriv->plat_data; ++ ++ //brcm_sata_init(priv); ++ //brcm_sata_phys_enable(priv); ++ //brcm_sata_alpm_init(hpriv); ++ return ahci_platform_resume(dev); ++} ++#endif ++ ++ ++#if defined(CONFIG_ARCH_INFINITY2) && defined(CONFIG_PM_SLEEP) ++static int sstar_ahci_suspend1(struct device *dev) ++{ ++ struct ahci_platform_data *pdata = dev_get_platdata(dev); ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ void __iomem *mmio = hpriv->mmio; ++ u32 ctl; ++ int rc; ++ ++ if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) ++ { ++ dev_err(dev, "firmware update required for suspend/resume\n"); ++ return -EIO; ++ } ++ ++ /* ++ * AHCI spec rev1.1 section 8.3.3: ++ * Software must disable interrupts prior to requesting a ++ * transition of the HBA to D3 state. ++ */ ++ ctl = readl(mmio + HOST_CTL); ++ ctl &= ~HOST_IRQ_EN; ++ writel(ctl, mmio + HOST_CTL); ++ readl(mmio + HOST_CTL); /* flush */ ++ ++ rc = ata_host_suspend(host, PMSG_SUSPEND); ++ if (rc) ++ return rc; ++ ++ if (pdata && pdata->suspend) ++ return pdata->suspend(dev); ++ ++ if (!IS_ERR(hpriv->clk)) ++ clk_disable_unprepare(hpriv->clk); ++ ++ return 0; ++} ++ ++static int sstar_ahci_resume1(struct device *dev) ++{ ++ struct ahci_platform_data *pdata = dev_get_platdata(dev); ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ int rc; ++ ++ if (!IS_ERR(hpriv->clk)) ++ { ++ rc = clk_prepare_enable(hpriv->clk); ++ if (rc) ++ { ++ dev_err(dev, "clock prepare enable failed"); ++ return rc; ++ } ++ } ++ ++ if (pdata && pdata->resume) ++ { ++ rc = pdata->resume(dev); ++ if (rc) ++ goto disable_unprepare_clk; ++ } ++ ++ if (dev->power.power_state.event == PM_EVENT_SUSPEND) ++ { ++ rc = ahci_reset_controller(host); ++ if (rc) ++ goto disable_unprepare_clk; ++ ++ ahci_init_controller(host); ++ } ++ ++ ata_host_resume(host); ++ ++ return 0; ++ ++disable_unprepare_clk: ++ if (!IS_ERR(hpriv->clk)) ++ clk_disable_unprepare(hpriv->clk); ++ ++ return rc; ++} ++#endif ++ ++ ++ ++ ++static SIMPLE_DEV_PM_OPS(ahci_sstar_pm_ops1, sstar_ahci_suspend1, sstar_ahci_resume1); ++ ++static const struct of_device_id ahci_of_match1[] = { ++// { .compatible = "generic-ahci", }, ++ { .compatible = "sstar,sata1", }, ++ /* Keep the following compatibles for device tree compatibility */ ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, ahci_of_match1); ++ ++ ++static int ahci_sstar_probe1(struct platform_device *pdev) ++{ ++ const struct of_device_id *of_id; ++ struct device *dev = &pdev->dev; ++ struct sstar_ahci_priv *priv; ++ struct ahci_host_priv *hpriv; ++ struct resource *res; ++ int ret; ++ // int rc; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ of_id = of_match_node(ahci_of_match1, pdev->dev.of_node); ++ if (!of_id) ++ return -ENODEV; ++ ++ priv->dev = dev; ++ ++// res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci"); ++// priv->res_ahci = devm_ioremap_resource(dev, res); ++// if (IS_ERR(priv->res_ahci)) ++// return PTR_ERR(priv->res_ahci); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci_port0"); ++ priv->res_ahci_port0 = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->res_ahci_port0)) ++ return PTR_ERR(priv->res_ahci_port0); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci_misc"); ++ priv->res_ahci_misc = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->res_ahci_misc)) ++ return PTR_ERR(priv->res_ahci_misc); ++ ++ // pr_info("[%s] , priv->res_ahci =0x%p \n", __func__ , priv->res_ahci ); ++ pr_info("[%s] , priv->res_ahci_port0 =0x%p \n", __func__ , priv->res_ahci_port0 ); ++ pr_info("[%s] , priv->res_ahci_misc =0x%p \n", __func__ , priv->res_ahci_misc ); ++ ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ ss_sata_init1(priv->res_ahci_port0 - 0x200 ); ++#else ++ ss_sata_init(priv->res_ahci_port0 - 0x100 ); ++#endif ++ ++ hpriv = ahci_platform_get_resources(pdev); ++ if (IS_ERR(hpriv)) ++ return PTR_ERR(hpriv); ++ ++ hpriv->plat_data = priv; ++ ++ ret = ahci_platform_enable_resources(hpriv); ++ if (ret) ++ return ret; ++ ++ ret = ahci_platform_init_host(pdev, hpriv, &ahci_port_info1, &ahci_platform_sht1); ++ if (ret) ++ { ++ goto disable_resources; ++ } ++ ++ ++ pr_info("[%s] , SSTAR AHCI SATA registered \n", __func__ ); ++ ++ return 0; ++ ++disable_resources: ++ ahci_platform_disable_resources(hpriv); ++ return ret; ++ ++} ++ ++ ++ ++static const struct acpi_device_id ahci_acpi_match1[] = { ++ { ACPI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff) }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(acpi, ahci_acpi_match1); ++ ++ ++ ++ ++ ++ ++static int sstar_ahci_remove1(struct platform_device *pdev) ++{ ++// struct ata_host *host = dev_get_drvdata(&pdev->dev); ++// struct ahci_host_priv *hpriv = host->private_data; ++// struct brcm_ahci_priv *priv = hpriv->plat_data; ++ int ret; ++ ++ ret = ata_platform_remove_one(pdev); ++ if (ret) ++ return ret; ++ ++ //brcm_sata_phys_disable(priv); ++ ++ return 0; ++} ++ ++static struct platform_driver ahci_driver1 = { ++ .probe = ahci_sstar_probe1, ++ .remove = sstar_ahci_remove1, ++ .driver = { ++ .name = DRV_NAME1, ++ .of_match_table = ahci_of_match1, ++ .acpi_match_table = ahci_acpi_match1, ++ .pm = &ahci_sstar_pm_ops1, ++ }, ++}; ++module_platform_driver(ahci_driver1); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("sstar Semiconductor"); ++MODULE_DESCRIPTION("AHCI SATA platform driver"); ++ ++ +diff --git a/drivers/sstar/sata_host/mdrv_sata_host.c b/drivers/sstar/sata_host/mdrv_sata_host.c +new file mode 100755 +index 000000000000..85ad6497df14 +--- /dev/null ++++ b/drivers/sstar/sata_host/mdrv_sata_host.c +@@ -0,0 +1,1785 @@ ++/* ++* mdrv_sata_host.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include "MsIRQ.h" ++//#include "chip_int.h" ++//#include "chip_setup.h" ++#include <../../../drivers/ata/ahci.h> ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++#include "mhal_sata_host.c" ++#endif ++ ++#define SW_OOB_MODE 0 ++ ++#define sata_reg_write16(val, addr) { (*((volatile unsigned short*)(addr))) = (unsigned short)(val); } ++ ++#ifdef CONFIG_OF ++ #include ++ #include ++#endif ++ ++//#ifdef CONFIG_ARCH_INFINITY2 ++#if 0 ++extern void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv, unsigned int force_port_map, unsigned int mask_port_map); ++#else ++extern void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv); ++#endif ++ ++extern int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); ++extern int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); ++extern unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg); ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ //extern u32 ahci_reg_read(phys_addr_t reg_addr); ++ //extern void ahci_reg_write(u32 data, phys_addr_t p_reg_addr);; ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++#endif ++ ++#define SATA_DEBUG ++#ifdef SATA_DEBUG ++ #define sata_debug(fmt, args...) printk("[SATA0][%s] " fmt, __FUNCTION__, ##args) ++#else ++ #define sata_debug(fmt, args...) do {} while(0) ++#endif ++#define sata_info(fmt, args...) printk("[SATA0][INFO] " fmt, ##args) ++#define sata_error(fmt, args...) printk("[SATA0][ERR] " fmt, ##args) ++ ++//#define SPEED_TEST1 ++ ++#ifdef SPEED_TEST1 ++ struct timespec proc_start; ++ u32 g_u32Diff1; ++ u32 u32Diff[10]; ++ static u32 u32Cnt = 0; ++#endif ++ ++struct prdte ++{ ++ u32 dba; ++ u32 dbau; ++ u32 rev1; ++ ++ u32 dbc: 22; ++ u32 rev2: 9; ++ u32 i: 1; ++}; ++ ++struct sata_sstar_host_priv *ss_hpriv; ++ ++#if 0 ++static void print_fis(hal_cmd_h2dfis *pfis) ++{ ++ hal_cmd_h2dfis * p = pfis; ++ ++ printk("fis @ 0x%8.8x, fis size = 0x%x\n", (unsigned int)pfis, sizeof(hal_cmd_h2dfis)); ++ printk("fis phys @ 0x%8.8x\n", virt_to_phys(pfis)); ++ printk("fis type = 0x%x\n", p->u8fis_type); ++ printk("PMP:4\t = 0x%x\n", p->u8MPM); ++ printk("rev:3\t = 0x%x\n", p->reserved_0); ++ printk("iscmd:1\t = 0x%x\n", p->isclear); ++ printk("ata cmd\t = 0x%x\n", p->ata_cmd); ++ printk("feat.\t = 0x%x\n", p->fearure); ++ printk("lba_l\t = 0x%x\n", p->lba_l); ++ printk("lba_m\t = 0x%x\n", p->lba_m); ++ printk("lba_h\t = 0x%x\n", p->lba_h); ++ printk("dev\t = 0x%x\n", p->device); ++ printk("lba_l_e\t = 0x%x\n", p->lba_l_exp); ++ printk("lba_m_e\t = 0x%x\n", p->lba_m_exp); ++ printk("lba_h_e\t = 0x%x\n", p->lba_h_exp); ++ printk("feat. ex = 0x%x\n", p->fearure_exp); ++ printk("sector\t = 0x%x (u16)\n", p->u16sector_cnt); ++ printk("rev\t = 0x%x\n", p->reserved_1); ++ printk("ctrl\t = 0x%x\n", p->control); ++ printk("rev \t = 0x%x (u32)\n", p->reserved_2); ++} ++ ++static void print_prdt(struct prdte * pt, u32 num) ++{ ++ struct prdte * p = pt; ++ int i; ++ printk("prdt @ 0x%8.8x, prdte size = 0x%x, total = 0x%x\n", (unsigned int)pt, sizeof(struct prdte), sizeof(struct prdte) * num); ++ ++ printk("prdt @ phys 0x%8.8x\n", virt_to_phys(pt)); ++ for (i = 0; i < num; i++, p++) ++ { ++ printk("dba\t = 0x%x (u32)\n", p->dba); ++ printk("dbau\t = 0x%x (u32)\n", p->dbau); ++ printk("rev1\t = 0x%x (u32)\n", p->rev1); ++ printk("dbc\t = 0x%x (:22)\n", p->dbc); ++ printk("rev2\t = 0x%x (:9)\n", p->rev2); ++ printk("i\t = 0x%x (:1)\n", p->i); ++ } ++} ++static void p_prdt(struct prdte * pt) ++{ ++ struct prdte * p = pt; ++ int i; ++ printk("prdt @ 0x%8.8x, prdte size = 0x%x\n", (unsigned int)pt, sizeof(struct prdte)); ++ ++ printk("dba\t = 0x%x (u32)\n", p->dba); ++ printk("dbau\t = 0x%x (u32)\n", p->dbau); ++ printk("rev1\t = 0x%x (u32)\n", p->rev1); ++ printk("dbc\t = 0x%x (:22)\n", p->dbc); ++ printk("rev2\t = 0x%x (:9)\n", p->rev2); ++ printk("i\t = 0x%x (:1)\n", p->i); ++} ++#endif ++#if 0 ++static void print_cmd_header(hal_cmd_header *p) ++{ ++ printk(KERN_DEBUG "command header @ 0x%8.8x, cmd header size = 0x%x\n", (unsigned int)p, sizeof(hal_cmd_header)); ++ ++ // printk(KERN_DEBUG "cmd fis len\t = 0x%x (:5)\n", p->cmd_fis_len); ++ // printk(KERN_DEBUG "isATAPI\t = 0x%x (:1)\n", p->isATA_PI); ++ // printk(KERN_DEBUG "isWrite\t = 0x%x (:1)\n", p->iswrite); ++ // printk(KERN_DEBUG "isprefetch\t = 0x%x (:1)\n", p->isprefetch); ++ // printk(KERN_DEBUG "isswrst\t = 0x%x (:1)\n", p->issoftreset); ++ // printk(KERN_DEBUG "isbist\t = 0x%x (:1)\n", p->isbist); ++ // printk(KERN_DEBUG "isclrok\t = 0x%x (:1)\n", p->isclearok); ++ // printk(KERN_DEBUG "rev1\t = 0x%x (:1)\n", p->reserverd); ++ // printk(KERN_DEBUG "PMPid\t = 0x%x (:4)\n", p->PMPid); ++ // printk(KERN_DEBUG "PRDlen\t = 0x%x (16)\n", p->PRDTlength); ++ // printk(KERN_DEBUG "PRDbyte\t = 0x%x (32)\n", p->PRDBytes); ++ // printk(KERN_DEBUG "ctbal\t = 0x%x (32)\n", p->ctba_lbase); ++ // printk(KERN_DEBUG "ctbah\t = 0x%x (32)\n", p->ctba_hbase); ++ // printk("resv1\t = 0x%x (32)\n", p->resv[0]); ++ // printk("resv2\t = 0x%x (32)\n", p->resv[1]); ++ // printk("resv3\t = 0x%x (32)\n", p->resv[2]); ++ // printk("resv4\t = 0x%x (32)\n", p->resv[3]); ++} ++#endif ++ ++static void build_cmd_fis(void *cmd_tbl, hal_cmd_h2dfis *pfis, phys_addr_t misc_base) ++{ ++#if (SATA_CMD_TYPE != TYPE_RIU) ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ unsigned long u32MiscAddr = misc_base; ++ ++ writew(0x00, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++ ++ memcpy(cmd_tbl, pfis, sizeof(hal_cmd_h2dfis)); ++ //print_fis((hal_cmd_h2dfis *)cmd_tbl); ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ writew(0x01, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++#else // TYPE_RIU mode ++ u32 address = (u32)cmd_tbl; ++ u32 * dptr = (u32 *)pfis; ++ u32 offset; ++ ++ address = (u32)cmd_tbl; ++ ++ // loop through data ++ for (offset = 0; offset < sizeof(hal_cmd_h2dfis); offset += 4) ++ { ++ // which address to write? ++ writel(address, (void*)misc_base + SATA_MISC_CFIFO_ADDRL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", address, misc_base + SATA_MISC_CFIFO_ADDRL); ++ ++ // what data to write? ++ writel(*dptr, (void*)misc_base + SATA_MISC_CFIFO_WDATAL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", *dptr, misc_base + SATA_MISC_CFIFO_WDATAL); ++ ++ // read(0) or write(1)? normally write ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_RORW); ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_RORW); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_RORW); ++ ++ // trigger ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_ACCESS); ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_ACCESS); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_ACCESS); ++ ++ address += 4; ++ dptr++; ++ } ++ ++#endif ++} ++ ++static void build_cmd_prdt(void *base_address, u32 *pprdt, phys_addr_t misc_base, u32 prdt_num) ++{ ++#if (SATA_CMD_TYPE != TYPE_RIU) ++ void *cmd_address = base_address + SATA_KA9_CMD_DESC_OFFSET_TO_PRDT; ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ unsigned long u32MiscAddr = misc_base; ++ ++ ++ writew(0x00, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++ ++ memcpy(cmd_address, pprdt, sizeof(u32)*prdt_num * 4); ++ //print_prdt(cmd_address, prdt_num); ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ writew(0x01, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++#else // TYPE_RIU ++ u32 address = (u32)base_address + SATA_KA9_CMD_DESC_OFFSET_TO_PRDT; ++ u32 * dptr = pprdt; ++ u32 offset; ++ ++ //p_prdt((struct prdte *)pprdt); ++ ++ for (offset = 0; offset < sizeof(u32) * prdt_num * 4; offset += 4) ++ { ++ // which address to write? ++ writel(address, (void*)misc_base + SATA_MISC_CFIFO_ADDRL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", address, misc_base + SATA_MISC_CFIFO_ADDRL); ++ ++ // what data to write? ++ writel(*dptr, (void*)misc_base + SATA_MISC_CFIFO_WDATAL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", *dptr, misc_base + SATA_MISC_CFIFO_WDATAL); ++ ++ // read(0) or write(1)? normally write ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_RORW); ++ //printf("write data 0x0001 to addr 0x%8.8x\n", misc_base + SATA_MISC_CFIFO_RORW); ++ ++ // trigger ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_ACCESS); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_ACCESS); ++ ++ address += 4; ++ dptr++; ++ } ++#endif ++} ++ ++static void build_cmd_header(void *cmd_slot, u32 u32offset_address, u32 *pcmdheader, phys_addr_t misc_base) ++{ ++#if (SATA_CMD_TYPE != TYPE_RIU) ++ void *cmd_address = cmd_slot + u32offset_address; ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ unsigned long u32MiscAddr = misc_base; ++ ++ writew(0x00, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++ ++ memcpy(cmd_address, pcmdheader, SATA_KA9_CMD_HDR_SIZE); ++ //print_cmd_header(cmd_address); ++ Chip_Flush_MIU_Pipe(); ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ writew(0x01, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++#else ++ u32 address = (u32)cmd_slot + u32offset_address; ++ u32 * dptr = pcmdheader; ++ u32 offset; ++ ++ for (offset = 0; offset < SATA_KA9_CMD_HDR_SIZE; offset += 4) ++ { ++ // which address to write? ++ writel(address, (void*)misc_base + SATA_MISC_CFIFO_ADDRL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", address, misc_base + SATA_MISC_CFIFO_ADDRL); ++ ++ // what data to write? ++ writel(*dptr, (void*)misc_base + SATA_MISC_CFIFO_WDATAL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", *dptr, misc_base + SATA_MISC_CFIFO_WDATAL); ++ ++ // read(0) or write(1)? normally write ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_RORW); ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_RORW); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_RORW); ++ ++ // trigger ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_ACCESS); ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_ACCESS); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_ACCESS); ++ ++ address += 4; ++ dptr++; ++ } ++#endif ++} ++ ++ ++static irqreturn_t sstar_ahci_single_level_irq_intr(int irq, void *dev_instance) ++{ ++ struct ata_host *host = dev_instance; ++ struct ahci_host_priv *hpriv; ++ unsigned int rc = 0; ++ void __iomem *mmio; ++ u32 irq_stat, irq_masked; ++ ++ VPRINTK("ENTER\n"); ++ ++ hpriv = host->private_data; ++ mmio = hpriv->mmio; ++ ++ /* sigh. 0xffffffff is a valid return from h/w */ ++ irq_stat = readl(mmio + HOST_IRQ_STAT); ++ if (!irq_stat) ++ return IRQ_NONE; ++ ++ irq_masked = irq_stat & hpriv->port_map; ++ ++ spin_lock(&host->lock); ++ ++ rc = ahci_handle_port_intr(host, irq_masked); ++ ++ /* HOST_IRQ_STAT behaves as level triggered latch meaning that ++ * it should be cleared after all the port events are cleared; ++ * otherwise, it will raise a spurious interrupt after each ++ * valid one. Please read section 10.6.2 of ahci 1.1 for more ++ * information. ++ * ++ * Also, use the unmasked value to clear interrupt as spurious ++ * pending event on a dummy port might cause screaming IRQ. ++ */ ++ writel(irq_stat, mmio + HOST_IRQ_STAT); ++ ++ spin_unlock(&host->lock); ++ ++ VPRINTK("EXIT\n"); ++ ++ return IRQ_RETVAL(rc); ++} ++ ++static inline unsigned int sata_sstar_tag(unsigned int tag) ++{ ++ /* all non NCQ/queued commands should have tag#0 */ ++ if (ata_tag_internal(tag)) ++ { ++ return 0; ++ } ++ ++ if (unlikely(tag >= SATA_SSTAR_QUEUE_DEPTH)) ++ { ++ DPRINTK("tag %d invalid : out of range\n", tag); ++ //printk("[%s][%d]\n",__FUNCTION__,__LINE__); ++ return 0; ++ } ++ return tag; ++} ++ ++static void sata_sstar_setup_cmd_hdr_entry(struct sata_sstar_port_priv *pp, ++ unsigned int tag, u32 data_xfer_len, u8 num_prde, ++ u8 fis_len, phys_addr_t misc_base) ++{ ++ dma_addr_t cmd_descriptor_address; ++ hal_cmd_header cmd_header = {0}; ++ void *cmd_slot = pp->cmd_slot; ++ ++ cmd_descriptor_address = pp->cmd_tbl_dma + tag * SATA_KA9_CMD_DESC_SIZE; ++ ++ cmd_header.cmd_fis_len = fis_len; ++ cmd_header.PRDTlength = num_prde; ++ cmd_header.isclearok = 0; ++ cmd_header.PRDBytes = data_xfer_len; ++ cmd_header.ctba_hbase = 0; ++ cmd_header.ctba_lbase = cmd_descriptor_address; ++ ++ build_cmd_header(cmd_slot, tag * SATA_KA9_CMD_HDR_SIZE, (u32 *)&cmd_header, misc_base); ++} ++ ++static unsigned int sata_sstar_fill_sg(struct ata_queued_cmd *qc, ++ u32 *ttl, void *cmd_tbl, phys_addr_t misc_base) ++{ ++ struct scatterlist *sg; ++ u32 ttl_dwords = 0; ++ u32 prdt[SATA_KA9_USED_PRD * 4] = {0}; ++ unsigned int si; ++ ++ for_each_sg(qc->sg, sg, qc->n_elem, si) ++ { ++ dma_addr_t sg_addr = sg_dma_address(sg); ++ u32 sg_len = sg_dma_len(sg); ++ ++ if (si == (SATA_KA9_USED_PRD - 1) && ((sg_next(sg)) != NULL)) ++ { ++ sata_error("setting indirect prde , out of prdt\n"); ++ } ++ ttl_dwords += sg_len; ++ ++ prdt[si * 4 + 0] = (u32)(MHal_SATA_bus_address(cpu_to_le32(sg_addr))); ++ prdt[si * 4 + 1] = (u32)(MHal_SATA_bus_address(cpu_to_le32(sg_addr)) >> 16); ++ prdt[si * 4 + 2] = 0xFFFFFFFF; ++ prdt[si * 4 + 3] = (cpu_to_le32(sg_len) - 1); ++ } ++ build_cmd_prdt(cmd_tbl, &prdt[0], misc_base, si); ++ *ttl = ttl_dwords; ++ return si; ++} ++ ++static u32 sstar_sata_wait_reg(phys_addr_t reg_addr, u32 mask, u32 val, unsigned long interval, unsigned long timeout) ++{ ++ u32 temp; ++ unsigned long timeout_vale = 0; ++ ++ temp = readl((void*)reg_addr); ++ ++ while((temp & mask) == val) ++ { ++ msleep(interval); ++ timeout_vale += interval; ++ if (timeout_vale > timeout) ++ break; ++ temp = readl((void*)reg_addr); ++ } ++ return temp; ++} ++ ++static int sstar_ahci_stop_engine(phys_addr_t port_base) ++{ ++ u32 temp; ++ ++ temp = readl((void*)SS_PORT_CMD + port_base); ++ ++ /* check if the HBA is idle */ ++ if ((temp & (SS_PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) ++ return 0; ++ ++ /* setting HBA to idle */ ++ temp &= ~PORT_CMD_START; ++ writel(temp, (void*)SS_PORT_CMD + port_base); ++ ++ temp = sstar_sata_wait_reg(SS_PORT_CMD + port_base, PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); ++ ++ if (temp & PORT_CMD_LIST_ON) ++ return -EIO; ++ ++ return 0; ++} ++ ++static void sstar_ahci_start_engine(phys_addr_t port_base) ++{ ++ u32 temp; ++ ++ /* Start Port DMA */ ++ temp = readl((void*)SS_PORT_CMD + port_base); ++ temp |= PORT_CMD_START; ++ writel(temp, (void*)SS_PORT_CMD + port_base); ++ readl((void*)SS_PORT_CMD + port_base); /* Flush */ ++} ++ ++static void sstar_ahci_start_fis_rx(struct ata_port *ap) ++{ ++ struct sata_sstar_port_priv *pp = ap->private_data; ++ phys_addr_t port_base =ss_hpriv->port_base;//SATA_GHC_1_ADDRESS_START; ++ u32 tmp; ++ ++ // set FIS registers ++ tmp = pp->cmd_slot_dma; ++ writel(tmp, (void*)SS_PORT_LST_ADDR + port_base); ++ ++ tmp = pp->rx_fis_dma; ++ writel(tmp, (void*)SS_PORT_FIS_ADDR + port_base); ++ ++ // enable FIS reception ++ tmp = readl((void*)SS_PORT_CMD + port_base); ++ tmp |= PORT_CMD_FIS_RX; ++ writel(tmp, (void*)SS_PORT_CMD + port_base); ++ ++ // flush ++ tmp = readl((void*)SS_PORT_CMD + port_base); ++} ++ ++static int sstar_ahci_stop_fis_rx(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ u32 tmp; ++ ++ // Disable FIS reception ++ tmp = readl((void*)SS_PORT_CMD + port_base); ++ tmp &= ~PORT_CMD_FIS_RX; ++ writel(tmp, (void*)SS_PORT_CMD + port_base); ++ ++ // Wait FIS reception Stop for 1000ms ++ tmp = sstar_sata_wait_reg(SS_PORT_CMD + port_base, PORT_CMD_FIS_ON, PORT_CMD_FIS_ON, 10, 1000); ++ ++ if (tmp & PORT_CMD_FIS_ON) ++ return -EBUSY; ++ ++ return 0; ++} ++ ++void GetStartTime(void) ++{ ++#ifdef SPEED_TEST1 ++ getnstimeofday(&proc_start); ++#endif ++} ++ ++void GetEndTime(void) ++{ ++#ifdef SPEED_TEST1 ++ u32 delta; ++ struct timespec ct; ++ ++ getnstimeofday(&ct); ++ delta = ct.tv_nsec + ((proc_start.tv_sec != ct.tv_sec) ? NSEC_PER_SEC : 0) ++ - proc_start.tv_nsec; ++ ++ //if((delta / 1000) <= 100000) ++ { ++ //if((delta / 1000) > g_u32Diff1) ++ g_u32Diff1 = (delta / 1000); ++ } ++#endif ++} ++ ++void PrintTime(void) ++{ ++#ifdef SPEED_TEST1 ++ //int i; ++ ++ //if((h2dfis.u8fis_type == 0x27) && ((h2dfis.ata_cmd == 0x60) || (h2dfis.ata_cmd == 0x61))) ++ { ++ u32Diff[u32Cnt] = g_u32Diff1; ++ u32Cnt++; ++ if(u32Cnt >= 10) ++ u32Cnt = 0; ++ ++ if((u32Cnt % 10) == 9) ++ { ++ //for(i = 0 ; i < 10 ; i++) ++ printk("%d, %d, %d, %d, %d, %d\n", (int)(u32Diff[2]), (int)(u32Diff[3]), (int)(u32Diff[4]), (int)(u32Diff[5]), (int)(u32Diff[6]), (int)(u32Diff[7])); // 246, 209,209 ++ } ++ } ++#endif ++} ++ ++static void sata_sstar_qc_prep(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct sata_sstar_port_priv *pp = ap->private_data; ++ u32 misc_base = ss_hpriv->misc_base; ++ unsigned int tag = sata_sstar_tag(qc->tag); ++ hal_cmd_h2dfis h2dfis; ++ u32 num_prde = 0; ++ u32 ttl_dwords = 0; ++ void *cmd_tbl; ++ ++#ifdef SPEED_TEST1 ++ //GetEndTime(); ++#endif ++ ++ //printk("%s\n", __func__); ++#ifdef SPEED_TEST1 ++ //GetStartTime(); ++#endif ++ ++ cmd_tbl = pp->cmd_tbl + (tag * SATA_KA9_CMD_DESC_SIZE); ++ ++ ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *)&h2dfis); ++ ++ build_cmd_fis(cmd_tbl, &h2dfis, misc_base); ++ ++ if (qc->flags & ATA_QCFLAG_DMAMAP) ++ { ++ num_prde = sata_sstar_fill_sg(qc, &ttl_dwords, cmd_tbl, misc_base); ++ } ++ ++ sata_sstar_setup_cmd_hdr_entry(pp, tag, ttl_dwords, ++ num_prde, 5, misc_base); ++ ++} ++ ++static unsigned int sata_sstar_qc_issue(struct ata_queued_cmd *qc) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ unsigned int tag = sata_sstar_tag(qc->tag); ++ struct ata_port *ap = qc->ap->host->ports[0]; ++ struct ata_link *link = qc->dev->link; ++ struct ahci_port_priv *pp = ap->private_data; ++ ++ //printk("%s\n", __func__); ++ ++ if (qc->tf.protocol == ATA_PROT_NCQ) ++ { ++ //printk("NCQ device- %d\n", qc->tag); ++ writel(1 << qc->tag, (void*)SS_PORT_SCR_ACT + port_base); ++// ap->sactive = link->sactive; // save ncq active tag ++ //ap->sactive = link->sactive; // save ncq active tag ++ pp->active_link->sactive = link->sactive; ++ //sata_info("sactive = 0x%x\n", ap->sactive); ++ } ++ writel(1 << tag, (void*)SS_PORT_CMD_ISSUE + port_base); ++ ++#ifdef SPEED_TEST1 ++ //GetStartTime(); ++#endif ++ ++ return 0; ++} ++ ++static bool sata_sstar_qc_fill_rtf(struct ata_queued_cmd *qc) ++{ ++ struct sata_sstar_port_priv *pp = qc->ap->private_data; ++ //struct sata_sstar_host_priv *host_priv = qc->ap->host->private_data; ++ //unsigned int tag = sata_sstar_tag(qc->tag); ++ //hal_cmd_h2dfis cd; ++ //phys_addr_t misc_base = host_priv->misc_base; ++ //void *rx_fis; ++ u8 *rx_fis; ++ ++ rx_fis = pp->rx_fis; ++#if 0 ++ read_cmd_fis(rx_fis, (tag * SATA_KA9_CMD_DESC_SIZE), &cd, misc_base); ++ ata_tf_from_fis((const u8 *)&cd, &qc->result_tf); ++#endif ++ if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && ++ !(qc->flags & ATA_QCFLAG_FAILED)) ++ { ++ ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); ++ qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; ++ DPRINTK("--- result_tf.command = 0x%x\n", qc->result_tf.command); ++ } ++ else ++ { ++ ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); ++ } ++ return true; ++} ++ ++ ++static unsigned sata_sstar_scr_offset(struct ata_port *ap, unsigned int sc_reg) ++{ ++ static const int offset[] = { ++ [SCR_STATUS] = PORT_SCR_STAT, ++ [SCR_CONTROL] = PORT_SCR_CTL, ++ [SCR_ERROR] = PORT_SCR_ERR, ++ [SCR_ACTIVE] = PORT_SCR_ACT, ++ [SCR_NOTIFICATION] = PORT_SCR_NTF, ++ }; ++ struct ahci_host_priv *hpriv = ap->host->private_data; ++ ++ if (sc_reg < ARRAY_SIZE(offset) && ++ (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) ++ return offset[sc_reg]; ++ return 0; ++} ++ ++ ++static int sata_sstar_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) ++{ ++ int offset = sata_sstar_scr_offset(link->ap, sc_reg); ++ phys_addr_t port_base = ss_hpriv->port_base; ++ if (offset) ++ { ++ *val = readl((void*)offset + port_base); ++ return 0; ++ } ++ return -1; ++} ++ ++static int sata_sstar_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) ++{ ++ int offset = sata_sstar_scr_offset(link->ap, sc_reg_in); ++ phys_addr_t port_base = ss_hpriv->port_base; ++ //struct sata_sstar_host_priv *host_priv = link->ap->host->private_data; ++ if (offset) ++ { ++ writel(val, (void*)offset + port_base); ++ return 0; ++ } ++ return -1; ++} ++ ++static void sata_sstar_freeze(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ writel(0, (void*)SS_PORT_IRQ_MASK + port_base); ++} ++ ++static void sata_sstar_thaw(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ phys_addr_t hba_base = ss_hpriv->hba_base; ++ u32 u32Temp = 0; ++ ++ // clear IRQ ++ u32Temp = readl((void*)SS_PORT_IRQ_STAT + port_base); ++ writel(u32Temp, (void*)SS_PORT_IRQ_STAT + port_base); ++ ++ // Clear Port 0 IRQ on HBA ++ u32Temp = readl((void*)SS_HOST_IRQ_STAT + hba_base); ++ writel(u32Temp, (void*)SS_HOST_IRQ_STAT + hba_base); ++ ++ // Enable Host Interrupt ++ u32Temp = readl((void*)SS_HOST_CTL + hba_base); ++ u32Temp |= HOST_IRQ_EN; ++ writel(u32Temp, (void*)SS_HOST_CTL + hba_base); ++ ++ // Enable Port Interrupt ++ writel(DEF_PORT_IRQ, (void*)SS_PORT_IRQ_MASK + port_base); ++ readl((void*)SS_PORT_IRQ_MASK + port_base); ++} ++ ++static unsigned int sata_sstar_dev_classify(struct ata_port *ap) ++{ ++ struct ata_taskfile tf; ++ u32 temp = 0; ++ phys_addr_t port_base = ss_hpriv->port_base; ++ temp = readl((void*)PORT_SIG + port_base/*SATA_GHC_0_P0_ADDRESS_START*/); ++ ++ tf.lbah = (temp >> 24) & 0xff; ++ tf.lbam = (temp >> 16) & 0xff; ++ tf.lbal = (temp >> 8) & 0xff; ++ tf.nsect = temp & 0xff; ++ return ata_dev_classify(&tf); ++} ++ ++int sstar_ahci_check_ready(struct ata_link *link) ++{ ++ u8 status; ++ phys_addr_t port_base = ss_hpriv->port_base; ++ ++ status = readl((void*)SS_PORT_TFDATA + port_base) & 0xFF; ++ ++ return ata_check_ready(status); ++} ++ ++#define CONNECTION_RETRY 5 ++static int sata_sstar_hardreset(struct ata_link *link, unsigned int *class, ++ unsigned long deadline) ++{ ++ struct ata_port *ap = link->ap; ++ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); ++ phys_addr_t port_base = ss_hpriv->port_base; ++ phys_addr_t misc_base = ss_hpriv->misc_base; ++ bool online; ++ int rc; ++ //u32 sstatus; ++ //u32 retry = 0; ++ //u16 u16Temp; ++ ++ //printk("%s:port_base:%X\n", __func__, port_base); ++ //printk("%s:host_priv->port_base:%X\n", __func__, host_priv->port_base); ++ ++ //hard_reset: ++ sstar_ahci_stop_engine(port_base); ++ ++ rc = sata_link_hardreset(link, timing, deadline, &online, ++ sstar_ahci_check_ready); ++ ++ sstar_ahci_start_engine(port_base); ++ ++#if 0//CONFIG_sstar_K6Lite // sw patch for gen3 ++ if (online) ++ { ++ rc = sata_sstar_scr_read(link, SCR_STATUS, &sstatus); ++ sata_info("SStatus = 0x%x\n", sstatus); ++ if (rc == 0 && ((sstatus & 0xf) == 0x3)) // 0x3 => device presence detected and Phy communication established ++ { ++ if ((((sstatus >> 4) & 0xf) == 0x01) && retry++ < CONNECTION_RETRY) // gen1 ++ { ++ sata_info("Gen1 connection detected, SATA PHY retrain %d\n", retry); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ u16Temp &= ~0x200; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ u16Temp |= 0x200; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ goto hard_reset; ++ } ++ } ++ } ++ if (retry >= CONNECTION_RETRY) ++ sata_info("Gen1 HDD detected\n"); ++#endif ++ ++ if (online) ++ *class = sata_sstar_dev_classify(ap); ++ else ++ MHal_SATA_Clock_Config(misc_base, port_base, FALSE); ++ ++ printk(KERN_INFO "[%s][port_base:0x%08x] done : %s\n", __func__, port_base, (online ? "online" : "offline")); ++ return rc; ++} ++ ++static int sata_sstar_softreset(struct ata_link *link, unsigned int *class, ++ unsigned long deadline) ++{ ++ // Unused Function ++ return 0; ++} ++ ++static void sata_sstar_error_handler(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ struct ata_device *dev = ap->link.device; ++ ++ DPRINTK("%s begin\n", __func__); ++ if (!(ap->pflags & ATA_PFLAG_FROZEN)) ++ { ++ sstar_ahci_stop_engine(port_base); ++ sstar_ahci_start_engine(port_base); ++ } ++ sata_pmp_error_handler(ap); ++ ++ //if (!ata_dev_enable(ap->link.device)) ++ if (!(dev->class == ATA_DEV_ATA || ++ dev->class == ATA_DEV_ATAPI || ++ dev->class == ATA_DEV_PMP || ++ dev->class == ATA_DEV_SEMB)) ++ sstar_ahci_stop_engine(port_base); ++ ++ DPRINTK("%s end\n", __func__); ++} ++ ++static int sstar_ahci_kick_engine(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ struct ahci_host_priv *hpriv = ap->host->private_data; ++ u8 status = readl((void*)port_base + SS_PORT_TFDATA); ++ u32 tmp; ++ int busy, rc; ++ ++ rc = sstar_ahci_stop_engine(port_base); ++ if (rc) ++ goto out_restart; ++ ++ busy = status & (ATA_BUSY | ATA_DRQ); ++ if (!busy && !sata_pmp_attached(ap)) ++ { ++ rc = 0; ++ goto out_restart; ++ } ++ if (!(hpriv->cap & HOST_CAP_CLO)) ++ { ++ rc = -EOPNOTSUPP; ++ goto out_restart; ++ } ++ ++ tmp = readl((void*)port_base + SS_PORT_CMD); ++ tmp |= PORT_CMD_CLO; ++ writel(tmp, (void*)port_base + SS_PORT_CMD); ++ ++ rc = 0; ++ tmp = ata_wait_register(ap, (void __iomem *) port_base + SS_PORT_CMD, ++ (u32)PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); ++ if (tmp & PORT_CMD_CLO) ++ rc = -EIO; ++out_restart: ++ sstar_ahci_start_engine(port_base); ++ return rc; ++} ++ ++static void sata_sstar_post_internal_cmd(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ ++ if (qc->flags & ATA_QCFLAG_FAILED) ++ sstar_ahci_kick_engine(ap); ++ //qc->err_mask |= AC_ERR_OTHER; ++#if 0 ++ if (qc->err_mask) ++ { ++ /* make DMA engine forget about the failed command */ ++ } ++#endif ++} ++ ++static int sata_sstar_port_start(struct ata_port *ap) ++{ ++ struct sata_sstar_port_priv *pp; ++// struct sata_sstar_host_priv *host_priv = ap->host->ports[0]->private_data; ++ u32 temp; ++ phys_addr_t port_base = ss_hpriv->port_base; ++ u32 GHC_PHY = 0x0; ++ ++#if (SATA_CMD_TYPE == TYPE_DRAM) ++ struct device *dev = ap->host->dev; ++ void *mem; ++ dma_addr_t mem_dma; ++ size_t dma_sz; ++#endif ++ ++ // Allocate SATA Port Private Data ++ pp = kzalloc(sizeof(*pp), GFP_KERNEL); ++ if (!pp) ++ { ++ printk("[%s][Error] SATA Allocate Port Private Data Fail\n", __func__); ++ return -ENOMEM; ++ } ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ printk(KERN_INFO "SATA cmd type: XIU\n"); ++ pp->cmd_slot = (void *)(SATA_SDMAP_RIU_BASE + (AHCI_P0CLB & 0xfff)); ++ pp->rx_fis = (void *)(SATA_SDMAP_RIU_BASE + (AHCI_P0FB & 0xfff)); ++ pp->cmd_tbl = (void *)(SATA_SDMAP_RIU_BASE + (AHCI_CTBA0 & 0xfff)); ++ ++ pp->cmd_slot_dma = AHCI_P0CLB; ++ pp->rx_fis_dma = AHCI_P0FB; ++ pp->cmd_tbl_dma = AHCI_CTBA0; ++ ++#elif (SATA_CMD_TYPE == TYPE_DRAM) ++ sata_info("SATA cmd type: DRAM\n"); ++ dma_sz = 0x10000; ++ mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); ++ if (!mem) ++ return -ENOMEM; ++ memset(mem, 0, dma_sz); ++ ++ pp->cmd_slot = mem; ++ // Translate physical address to bus address since SATA engine uses bus address. ++ mem_dma = (dma_addr_t)MHal_SATA_bus_address(mem_dma); ++ pp->cmd_slot_dma = mem_dma; ++ ++ mem += SATA_CMD_HEADER_SIZE; ++ mem_dma += SATA_CMD_HEADER_SIZE; ++ ++ pp->rx_fis = mem; ++ pp->rx_fis_dma = mem_dma; ++ ++ mem += SATA_FIS_SIZE; ++ mem_dma += SATA_FIS_SIZE; ++ ++ pp->cmd_tbl = mem; ++ pp->cmd_tbl_dma = mem_dma; ++ ++#elif (SATA_CMD_TYPE == TYPE_RIU) ++ sata_info("SATA cmd type: RIU\n"); ++ pp->cmd_slot = (void *)(AHCI_P0CLB); ++ pp->rx_fis = (void *)(AHCI_P0FB); ++ pp->cmd_tbl = (void *)(AHCI_CTBA0); ++ ++ pp->cmd_slot_dma = AHCI_P0CLB; ++ pp->rx_fis_dma = AHCI_P0FB; ++ pp->cmd_tbl_dma = AHCI_CTBA0; ++#else ++#error "SATA_CMD_TYPE Unknown" ++#endif ++ ++ sata_info("cmd_slot = 0x%x ; cmd_slot_dma = 0x%x\n", (u32)pp->cmd_slot, (u32)pp->cmd_slot_dma); ++ sata_info("rx_fis = 0x%x ; rx_fis_dma = 0x%x\n", (u32)pp->rx_fis, (u32)pp->rx_fis_dma); ++ sata_info("cmd_tbl = 0x%x ; cmd_tbl_dma = 0x%x\n", (u32)pp->cmd_tbl, (u32)pp->cmd_tbl_dma); ++ ++ //sata_info("port_base= 0x%x ;\n", port_base); ++ ++ ap->private_data = pp; ++// ap->ss_private_data = host_priv; ++ temp = readl((void*)SS_PORT_CMD + port_base) & ~PORT_CMD_ICC_MASK; ++ ++ // spin up device ++ temp |= PORT_CMD_SPIN_UP; ++ writel(temp, (void*)SS_PORT_CMD + port_base); ++ ++ // wake up link ++ writel((temp | PORT_CMD_ICC_ACTIVE), (void*)SS_PORT_CMD + port_base); ++ ++ // start FIS RX ++ sstar_ahci_start_fis_rx(ap); ++ ++ // Clear IS , Interrupt Status ++ writel(0xFFFFFFFF, (void*)SS_PORT_IRQ_STAT + port_base); ++ writel(0xFFFFFFFF, (void*)SS_PORT_SCR_ERR + port_base); ++ ++ // set to speed limit with gen 1, gen 2 or auto ++ temp = readl((void*)SS_PORT_SCR_CTL + port_base); ++ temp = temp & (~E_PORT_SPEED_MASK); // clear speed ++ temp = temp | MHal_SATA_get_max_speed(); ++ writel(temp,(void*) SS_PORT_SCR_CTL + port_base); ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ } ++#ifdef CONFIG_ARCH_INFINITY2 ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ } ++#endif ++ // test: enable PHY ++ writew(0x9a8f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); // [0]: Reset ++ writew(0x9a8e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x2200, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); // [9]: Enable host ++ ++ printk("sstar_ahci_start_engine\n"); ++ // MHal_SATA_HW_Inital(misc_base, port_base, hba_base); ++ ++ // Start DMA Engine ++ sstar_ahci_start_engine(port_base); ++ ++ return 0; ++} ++ ++static void sata_sstar_port_stop(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv->port_base; ++ int ret; ++ ++ sata_info("[%s]\n", __func__); ++ // Stop DMA Engine ++ ret = sstar_ahci_stop_engine(port_base); ++ if (ret) ++ { ++ sata_error("[%s][Error] Fail to Stop SATA Port\n", __func__); ++ } ++ ++ // Disable FIS reception ++ ret = sstar_ahci_stop_fis_rx(ap); ++ if (ret) ++ { ++ sata_error("[%s][Error] Fail to Stop FIS RX\n", __func__); ++ } ++} ++ ++#if 0 ++irqreturn_t sata_sstar_interrupt(int irq, void *dev_instance) ++{ ++ struct ata_host *host = dev_instance; ++ struct ata_port *ap = host->ports[0]; ++ struct sata_sstar_host_priv *host_priv = host->private_data; ++ struct ata_link *link = NULL; ++ struct ata_eh_info *active_ehi; ++ struct ata_eh_info *host_ehi = &ap->link.eh_info; ++ struct ata_queued_cmd *active_qc; ++ u32 serror = 0; ++ ++ ++ phys_addr_t port_base = host_priv->port_base; ++ phys_addr_t hba_base = host_priv->hba_base; ++ u32 host_status = 0; ++ u32 port_status = 0; ++ u32 qc_active; ++ //u32 port_ie; ++ u32 port_err; ++ u32 clr_port_err = 0; ++ ++#if 0 ++ link = &ap->link; ++ ehi = &link->eh_info; ++ ata_ehi_clear_desc(ehi); ++#endif ++ ++ host_status = sstar_sata_reg_read(HOST_IRQ_STAT + hba_base); ++ if (host_status) ++ printk("host_status = 0x%x\n", host_status); ++ else ++ return IRQ_NONE; ++ ++ spin_lock(&host->lock); ++ port_status = sstar_sata_reg_read(PORT_IRQ_STAT + port_base); ++ ++ sstar_sata_reg_write(port_status, PORT_IRQ_STAT + port_base); ++ if (port_status) ++ printk("port_status = 0x%x\n", port_status); ++ ++ if (port_status & (1 << 6)) // PORT_IRQ_CONNECT ++ { ++ printk(KERN_WARNING "HDD inserted (Device presence change, clear diag.X)\n"); ++ sstar_sata_reg_write((1 << 26), PORT_SCR_ERR + port_base); ++ } ++ if (port_status & (1 << 22)) // PORT_IRQ_PHYRDY ++ { ++ printk(KERN_WARNING "HDD removed (PhyRdy change, clear diag.N)\n"); ++ sstar_sata_reg_write((1 << 16), PORT_SCR_ERR + port_base); ++ //ata_ehi_hotplugged(ehi); ++ //ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); ++ } ++ ++ if (unlikely(port_status & PORT_IRQ_ERROR)) ++ { ++ link = &ap->link; ++ ++ active_qc = ata_qc_from_tag(ap, link->active_tag); ++ active_ehi = &link->eh_info; ++ ++ ata_ehi_clear_desc(host_ehi); ++ ata_ehi_push_desc(host_ehi, "irq_status 0x%08x", port_status); ++ ++ serror = sstar_sata_reg_read(PORT_SCR_ERR + port_base); ++ sstar_sata_reg_write(serror, PORT_SCR_ERR + port_base); ++ host_ehi->serror |= serror; ++ ++ if (port_status & PORT_IRQ_TF_ERR) ++ { ++ printk("IRQ TF ERROR\n"); ++ if (active_qc) ++ { ++ printk("active_qc on\n"); ++ active_qc->err_mask |= AC_ERR_DEV; ++ } ++ else ++ { ++ printk("active link on\n"); ++ active_ehi->err_mask |= AC_ERR_DEV; ++ } ++ } ++ if (port_status & PORT_IRQ_FREEZE) ++ { ++ printk("ata_port_freeze now\n"); ++ ata_port_freeze(ap); ++ } ++ else ++ { ++ printk("ata_port_abort now\n"); ++ ata_port_abort(ap); ++ } ++ goto irq_out; ++ } ++ ++ port_err = sstar_sata_reg_read(PORT_SCR_ERR + port_base); ++ if (port_err) ++ printk("port_err = 0x%x\n", port_err); ++ if (port_err & (1 << 1)) ++ { ++ printk(KERN_WARNING "SATA recovered from communication error\n"); ++ clr_port_err |= (1 << 1); ++ } ++ if (port_err & (1 << 9)) ++ { ++ printk(KERN_WARNING "SATA Persistent comm error/data integrity error\n"); ++ clr_port_err |= (1 << 9); ++ } ++ if (clr_port_err) ++ sstar_sata_reg_write(clr_port_err, PORT_SCR_ERR + port_base); ++ ++#if 0 ++ if (port_status) ++ { ++ printk("port status = 0x%x\n", port_status); ++ } ++#endif ++ ++ // clear interrupt ++ //sstar_sata_reg_write(port_status, PORT_IRQ_STAT + port_base); ++irq_out: ++ qc_active = sstar_sata_reg_read(PORT_SCR_ACT + port_base); ++ qc_active |= sstar_sata_reg_read(PORT_CMD_ISSUE + port_base); ++ ++ ata_qc_complete_multiple(ap, qc_active); ++ sstar_sata_reg_write(host_status, HOST_IRQ_STAT + hba_base); ++ spin_unlock(&host->lock); ++ ++ return IRQ_RETVAL(1); ++} ++#endif ++ ++ ++ ++#if (SW_OOB_MODE == 1) ++static void sstar_sata_sw_oob_mode1(void) ++{ ++ u16 u16Temp, u16IrqRetry, u16Irq2Retry=2; ++ ++ // Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE1_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 5; u16IrqRetry++) ++ { ++ // Check if IRQ1 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_LOCK_FLAG) ++ break; ++ ++ udelay(2); ++ } ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq2Retry--; ++ // Check if IRQ2 no ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_UNLOCK_FLAG) || u16Irq2Retry == 0) ++ goto SW_OOB_MODE1_STAGE0; ++ ++ udelay(2); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 2; u16IrqRetry++) ++ { ++ // Check if IRQ3 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) ++ break; ++ ++ udelay(1); ++ } ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#elif (SW_OOB_MODE == 2) ++static void sstar_sata_sw_oob_mode2(void) ++{ ++ u16 u16Temp, u16Irq3Retry=2; ++ ++ //Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE2_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq3Retry--; ++ // Check if IRQ3 is yes ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) || u16Irq3Retry == 0) ++ break; ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#endif ++ ++static int sstar_sata_hardware_init(phys_addr_t hba_base, phys_addr_t port_base, phys_addr_t misc_base) ++{ ++ u32 i; ++ u32 u32Temp = 0; ++ ++ MHal_SATA_HW_Inital(misc_base, port_base, hba_base); ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ writew(HOST_RESET, (volatile void *)hba_base + (HOST_CTL)); ++#else ++ writel(HOST_RESET, (volatile void *)hba_base + (HOST_CTL)); ++#endif ++ ++ #if (SW_OOB_MODE == 1) ++ sstar_sata_sw_oob_mode1(); ++ #elif (SW_OOB_MODE == 2) ++ sstar_sata_sw_oob_mode2(); ++ #else ++ u32Temp = sstar_sata_wait_reg(SS_HOST_CTL + hba_base, HOST_RESET, HOST_RESET, 1, 500); ++ ++ if (u32Temp & HOST_RESET) ++ return -1; ++ #endif ++ // Turn on AHCI_EN ++ u32Temp = readl((void*)SS_HOST_CTL + (phys_addr_t) hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ { ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ return 0; ++ } ++ ++ // Try AHCI_EN Trurn on for a few time ++ for (i = 0; i < 5; i++) ++ { ++ u32Temp |= HOST_AHCI_EN; ++ writel(u32Temp, (void*)SS_HOST_CTL + (phys_addr_t)hba_base); ++ u32Temp = readl((void*)SS_HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ break; ++ msleep(10); ++ } ++ ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t) port_base, (phys_addr_t) hba_base); ++ ++ //printk("sstar_sata_hardware_init done !!!!!!!!!\n"); ++ return 0; ++} ++ ++static struct scsi_host_template sstar_sata_sht = ++{ ++#if defined(USE_NCQ) ++ ATA_NCQ_SHT("sstar_sata"), ++#else ++ ATA_BASE_SHT("sstar_sata"), ++#endif ++ .can_queue = SATA_SSTAR_QUEUE_DEPTH, ++ .sg_tablesize = SATA_KA9_USED_PRD, ++ .dma_boundary = ATA_DMA_BOUNDARY, ++}; ++ ++static struct ata_port_operations sstar_sata_ops = ++{ ++ .inherits = &sata_pmp_port_ops, ++ ++ .qc_defer = ata_std_qc_defer, ++ .qc_prep = sata_sstar_qc_prep, ++ .qc_issue = sata_sstar_qc_issue, ++ .qc_fill_rtf = sata_sstar_qc_fill_rtf, ++ ++ .scr_read = sata_sstar_scr_read, ++ .scr_write = sata_sstar_scr_write, ++ ++ .freeze = sata_sstar_freeze, ++ .thaw = sata_sstar_thaw, ++ ++ .softreset = sata_sstar_softreset, ++ .hardreset = sata_sstar_hardreset, ++ ++ .pmp_softreset = sata_sstar_softreset, ++ .error_handler = sata_sstar_error_handler, ++ .post_internal_cmd = sata_sstar_post_internal_cmd, ++ ++ .port_start = sata_sstar_port_start, ++ .port_stop = sata_sstar_port_stop, ++ ++}; ++ ++static const struct ata_port_info sstar_sata_port_info[] = ++{ ++ { ++ .flags = SATA_SSTAR_HOST_FLAGS, ++ .pio_mask = ATA_PIO6, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &sstar_sata_ops, ++ }, ++}; ++ ++int __ss_sata_get_irq_number_host(void) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int irq = 0; ++ ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ printk("[SATA] Virtual IRQ: %d\n", irq); ++ return irq; ++} ++ ++static int sstar_sata_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ata_port_info pi = sstar_sata_port_info[0]; ++ const struct ata_port_info *ppi[] = { &pi, NULL }; ++ struct ahci_host_priv *hpriv; ++ struct ata_host *host; ++ int irq = 0; ++ int ret = 0; ++ ++#if 0 // defined(CONFIG_OF) ++ struct device_node *np = dev->of_node; ++ int hba_base; ++ int port_base; ++ int misc_base; ++#else ++ struct resource *port_mem; ++ struct resource *misc_mem; ++ struct resource *hba_mem; ++#endif ++ ++ //sata_info("sstar SATA Host Controller Probing...\n"); ++ sata_info("SATA %d probing...\n", pdev->id); ++ ++#if 0 // defined(CONFIG_OF) ++ ret = of_property_read_u32(np, "sstar,hba-base", &hba_base); ++ if (ret) ++ { ++ printk("[%s][Error] SATA Get HBA Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ printk("dtb hba_base = %x\n", hba_base); ++ ++ ret = of_property_read_u32(np, "sstar,port-base", &port_base); ++ if (ret) ++ { ++ printk("[%s][Error] SATA Get Port Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ printk("dtb port_base= %x\n", port_base); ++ ++ ret = of_property_read_u32(np, "sstar,misc-base", &misc_base); ++ if (ret) ++ { ++ printk("[%s][Error] SATA Get MISC Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ printk("dtb misc_base= %x\n", misc_base); ++ ++ ret = of_property_read_u32(np, "interrupts", &irq); ++ if ((ret) && (irq <= 0)) ++ { ++ printk("[%s][Error] SATA Get IRQ Fail\n", __func__); ++ return -EINVAL; ++ } ++#else ++ hba_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ port_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ misc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ ++ sata_debug("HBA = 0x%08x, PORT = 0x%08x, MISC = 0x%08x\n", hba_mem->start, port_mem->start, misc_mem->start); ++ if (!hba_mem) ++ { ++ sata_error("[%s]SATA Get HBA Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ if (!port_mem) ++ { ++ sata_error("[%s]SATA Get Port Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ if (!misc_mem) ++ { ++ sata_error("[%s]SATA Get MISC Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ ++#if 0 ++ irq = platform_get_irq(pdev, 0); ++#else ++ irq = __ss_sata_get_irq_number_host(); ++#endif ++ if (irq <= 0) ++ { ++ sata_error("[%s]SATA Get IRQ Fail\n", __func__); ++ return -EINVAL; ++ } ++#endif ++ ++ // Allocate Host Private Data ++ hpriv = devm_kzalloc(dev, sizeof(struct ahci_host_priv), GFP_KERNEL); ++ if (!hpriv) ++ { ++ sata_error("[%s] SATA Allocate Host Private Data Fail\n", __func__); ++ return -ENOMEM; ++ } ++ ss_hpriv = devm_kzalloc(dev, sizeof(struct sata_sstar_host_priv), GFP_KERNEL); ++ if (!ss_hpriv) ++ { ++ sata_error("[%s]SATA Allocate SS Host Private Data Fail\n", __func__); ++ return -ENOMEM; ++ } ++ ++ // printk("SSTAR_RIU_BASE = 0x%llx..\n", SSTAR_RIU_BASE); // sstar_pm_base ++ // FIXME: need a way to set DMA mask in DTB, otherwise we will get dma allocation fail. ++#if 0 //defined(CONFIG_OF) ++ printk("CONFIG_OF\n"); ++ printk("SSTAR_RIU_BASE = 0x%llx..\n", SSTAR_RIU_BASE); // sstar_pm_base ++ hpriv->hba_base = (SSTAR_RIU_BASE + (hba_base << 1)); // (mstar_pm_base + (hba_base << 1)); ++ hpriv->port_base = (SSTAR_RIU_BASE + (port_base << 1)); // (mstar_pm_base + (port_base << 1)); ++ hpriv->misc_base = (SSTAR_RIU_BASE + (misc_base << 1)); // (mstar_pm_base + (misc_base << 1)); ++#else ++ ss_hpriv->hba_base = hba_mem->start; ++ ss_hpriv->port_base = port_mem->start; ++ ss_hpriv->misc_base = misc_mem->start; ++#endif ++ ++ sata_debug("IRQ = %d\n", irq); ++ ++#if defined(USE_NCQ) ++ if(ppi[0]->flags & ATA_FLAG_NCQ) ++ sata_info("== NCQ enable ==\n"); ++#endif ++#ifdef CONFIG_SATA_PMP ++ if(ppi[0]->flags & ATA_FLAG_PMP) ++ sata_info("== PMP support ==\n"); ++#endif ++ ++ // Initial SATA Hardware ++ if (sstar_sata_hardware_init(hba_mem->start, port_mem->start, misc_mem->start)) ++ { ++ sata_error("[%s]SATA Hardware Initial Failed\n", __func__); ++ return -EINVAL; ++ } ++ ++ host = ata_host_alloc_pinfo(dev, ppi, SATA_PORT_NUM); ++ if (!host) ++ { ++ ret = -ENOMEM; ++ sata_error("[%s]SATA Allocate ATA Host Fail\n", __func__); ++ goto out_devm_kzalloc_hpriv; ++ } ++ ++ hpriv->flags |= (unsigned long)pi.private_data; ++ hpriv->mmio = (void __iomem *) hba_mem->start; ++ hpriv->irq = irq; ++ ++//#ifdef CONFIG_ARCH_INFINITY2 ++#if 0 ++ ahci_save_initial_config(dev, hpriv, 0, 0); ++#else ++ ahci_save_initial_config(dev, hpriv); ++#endif ++ ++ /* DH test */ ++ if (hpriv->cap & HOST_CAP_NCQ) ++ pi.flags |= ATA_FLAG_NCQ; ++ // if (!ncq_en) ++ // pi.flags &= ~ATA_FLAG_NCQ; ++ if (hpriv->cap & HOST_CAP_PMP) ++ pi.flags |= ATA_FLAG_PMP; ++ ++ host->private_data = hpriv; ++ host->ports[0]->private_data = ss_hpriv; ++ ++ //sata_info("host->ports[0] addr = [0x%x]\n", (u32)host->ports[0]); ++ ++ //return ata_host_activate(host, irq, sata_sstar_interrupt, IRQF_SHARED, &sstar_sata_sht); ++ //return ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED, &sstar_sata_sht); ++#ifdef CONFIG_ARCH_INFINITY2 ++ return ata_host_activate(host, irq, sstar_ahci_single_level_irq_intr, IRQF_SHARED, &sstar_sata_sht); ++#else ++ return ahci_host_activate(host, &sstar_sata_sht); ++#endif ++ ++out_devm_kzalloc_hpriv: ++ devm_kfree(dev, hpriv); ++ devm_kfree(dev, ss_hpriv); ++ ++ return ret; ++} ++ ++static int sstar_sata_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *host_priv = host->private_data; ++// struct sata_sstar_host_priv *ss_hpriv = host->ports[0]->ss_private_data; ++ ++ ata_host_detach(host); ++ ++ devm_kfree(dev, host_priv); ++ devm_kfree(dev, ss_hpriv); ++ ++ sata_info("[%s]\n", __func__); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int sstar_sata_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ //struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ ++ sata_info("[%s]\n", __func__); ++ //return ata_host_suspend(host, state); ++ return 0; ++} ++ ++static int sstar_sata_resume(struct platform_device *pdev) ++{ ++ struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ //struct sata_sstar_host_priv *hpriv = host->private_data; ++ struct resource *port_mem; ++ struct resource *misc_mem; ++ struct resource *hba_mem; ++ sata_info("[%s]\n", __func__); ++ ++ hba_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ port_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ misc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ ++ if (sstar_sata_hardware_init(hba_mem->start, port_mem->start, misc_mem->start)/*sstar_sata_hardware_init()*/) ++ { ++ sata_error("[%s][Error] SATA Hardware Initial Failed, SATA resume failed!\n", __func__); ++ return -EINVAL; ++ } ++ //sata_sstar_port_start(struct ata_port *ap) ++ sata_sstar_port_start(host->ports[0]); ++ ++ //ata_host_resume(host); ++ sata_info("[%s] done\n", __func__); ++ return 0; ++} ++#endif ++ ++static void sstar_sata_drv_platfrom_release(struct device *device) ++{ ++ phys_addr_t port_base = SATA_GHC_0_P0_ADDRESS_START; ++ phys_addr_t misc_base = SATA_MISC_0_ADDRESS_START; ++ ++ sata_info("[%s]\n", __func__); ++ MHal_SATA_Clock_Config(misc_base, port_base, FALSE); ++} ++ ++#if defined(CONFIG_ARM64) ++#if 0 // defined(CONFIG_OF) ++static const struct of_device_id sstar_satahost_dt_match[] = ++{ ++ { .compatible = "sstar-sata", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sstar_satahost_dt_match); ++#endif ++#endif ++ ++static struct platform_driver sstar_sata_driver = ++{ ++ .probe = sstar_sata_probe, ++ .remove = sstar_sata_remove, ++#ifdef CONFIG_PM ++ .suspend = sstar_sata_suspend, ++ .resume = sstar_sata_resume, ++#endif ++ .driver = { ++ .name = "sstar-sata", ++#if defined(CONFIG_ARM64) ++#if 0 // defined(CONFIG_OF) ++ .of_match_table = sstar_satahost_dt_match, ++#endif ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++#if defined(CONFIG_ARM64) ++ static u64 sata_dmamask = DMA_BIT_MASK(64); ++#else ++ static u64 sata_dmamask = DMA_BIT_MASK(32); ++#endif ++ ++static struct resource satahost_resources[] = ++{ ++ [0] = { ++ .start = SATA_GHC_0_ADDRESS_START, ++ .end = SATA_GHC_0_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SATA_GHC_0_P0_ADDRESS_START, ++ .end = SATA_GHC_0_P0_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = SATA_MISC_0_ADDRESS_START, ++ .end = SATA_MISC_0_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++#if defined(CONFIG_ARCH_INFINITY2) ++ [3] = { ++ .start = INT_IRQ_15_SATA_INTRQ, //15 + 32, //E_IRQ_SATA_INT, ++ .end = INT_IRQ_15_SATA_INTRQ, //15 + 32, //E_IRQ_SATA_INT, ++ .flags = IORESOURCE_IRQ, ++ }, ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ [3] = { ++ .start = INT_IRQ_SATA, ++ .end = INT_IRQ_SATA, ++ .flags = IORESOURCE_IRQ, ++ }, ++#endif ++}; ++ ++struct platform_device sstar_satahost_device = ++{ ++ .name = "sstar-sata", ++ .id = 0, ++ .dev = { ++ .release = sstar_sata_drv_platfrom_release, ++ .dma_mask = &sata_dmamask, ++#if defined(CONFIG_ARM64) ++ .coherent_dma_mask = DMA_BIT_MASK(64), ++#else ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++#endif ++ }, ++ .num_resources = ARRAY_SIZE(satahost_resources), ++ .resource = satahost_resources, ++}; ++ ++static int __init sstar_sata_drv_init(void) ++{ ++ int ret = 0; ++ ++ //sata_info("===== [SATA 0] register platform driver START =====\n"); ++ ret = platform_driver_register(&sstar_sata_driver); ++ if (ret < 0) ++ { ++ sata_error("Unable to register SATA 0 platform driver, %d\n", ret); ++ return ret; ++ } ++ ++ ret = platform_device_register(&sstar_satahost_device); ++ if (ret < 0) ++ { ++ sata_error("Unable to register SATA 0 platform device, %d\n", ret); ++ platform_driver_unregister(&sstar_sata_driver); ++ return -ret; ++ } ++ sata_info("===== [SATA 0] register platform device END =====\n"); ++ ++ return ret; ++} ++ ++static void __exit sstar_sata_drv_exit(void) ++{ ++ sata_info("[%s]\n", __func__); ++ ++ platform_device_unregister(&sstar_satahost_device); ++ platform_driver_unregister(&sstar_sata_driver); ++} ++ ++MODULE_AUTHOR("sstar Semiconductor"); ++MODULE_DESCRIPTION("sstar 3.0Gbps SATA controller low level driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION("1.00"); ++ ++module_init(sstar_sata_drv_init); ++module_exit(sstar_sata_drv_exit); +diff --git a/drivers/sstar/sata_host/mdrv_sata_host.h b/drivers/sstar/sata_host/mdrv_sata_host.h +new file mode 100644 +index 000000000000..446757e4aafd +--- /dev/null ++++ b/drivers/sstar/sata_host/mdrv_sata_host.h +@@ -0,0 +1,120 @@ ++/* ++* mdrv_sata_host.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MDRV_SATA_HOST_H_ ++#define _MDRV_SATA_HOST_H_ ++ ++#define TYPE_XIU 0 ++#define TYPE_DRAM 1 ++#define TYPE_RIU 2 ++ ++#define SATA_CMD_TYPE TYPE_DRAM ++//#define SATA_CMD_TYPE TYPE_RIU ++//#define SATA_CMD_TYPE TYPE_XIU ++ ++#define USE_NCQ //Only Support at TYPE DRAM Mode ++ ++enum ++{ ++#if defined(USE_NCQ) ++ SATA_SSTAR_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ++ ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | ATA_FLAG_NCQ, ++ SATA_SSTAR_QUEUE_DEPTH = 31, ++#else ++ SATA_SSTAR_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ++ ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, ++ SATA_SSTAR_QUEUE_DEPTH = 1, ++#endif ++ SATA_KA9_USED_PRD = 24, ++ SATA_KA9_MAX_PRD = 24, ++ SATA_KA9_CMD_HDR_SIZE = 0x20, ++ ++ SATA_KA9_CMD_DESC_CFIS_SZ = 64, ++ SATA_KA9_CMD_DESC_ACMD_SZ = 16, ++ SATA_KA9_CMD_DESC_RSRVD = 48, ++ ++ SATA_KA9_CMD_DESC_SIZE = (SATA_KA9_CMD_DESC_CFIS_SZ + ++ SATA_KA9_CMD_DESC_ACMD_SZ + ++ SATA_KA9_CMD_DESC_RSRVD + ++ SATA_KA9_MAX_PRD * 16), ++ ++ SATA_KA9_CMD_DESC_OFFSET_TO_PRDT = ++ (SATA_KA9_CMD_DESC_CFIS_SZ + ++ SATA_KA9_CMD_DESC_ACMD_SZ + ++ SATA_KA9_CMD_DESC_RSRVD), ++}; ++ ++typedef struct sata_cmd_header ++{ ++ u8 cmd_fis_len : 5; ++ u8 isATA_PI : 1; ++ u8 iswrite : 1; ++ u8 isprefetch : 1; // enable only PRDT not zero ++ u8 issoftreset : 1; ++ u8 isbist : 1; ++ u8 isclearok : 1; ++ u8 reserverd : 1; ++ u8 PMPid : 4; ++ u16 PRDTlength ; ++ u32 PRDBytes ; ++ u32 ctba_lbase ; // 0~6 is reserved ++ u32 ctba_hbase ; ++ ++} hal_cmd_header; ++ ++ ++typedef struct sata_cmd_h2dfis ++{ ++ u8 u8fis_type ; ++ u8 u8MPM : 4; ++ u8 reserved_0 : 3; ++ u8 isclear : 1; ++ u8 ata_cmd ; ++ u8 fearure ; ++ u8 lba_l ; ++ u8 lba_m ; ++ u8 lba_h ; ++ u8 device ; ++ u8 lba_l_exp ; ++ u8 lba_m_exp ; ++ u8 lba_h_exp ; ++ u8 fearure_exp ; ++ u16 u16sector_cnt ; ++ u8 reserved_1 ; ++ u8 control ; ++ u32 reserved_2 ; ++} hal_cmd_h2dfis; ++ ++struct sata_sstar_port_priv ++{ ++ void *cmd_slot; ++ void *cmd_tbl; ++ void *rx_fis; ++ dma_addr_t cmd_slot_dma; ++ dma_addr_t cmd_tbl_dma; ++ dma_addr_t rx_fis_dma; ++}; ++ ++struct sata_sstar_host_priv ++{ ++ phys_addr_t hba_base; ++ phys_addr_t port_base; ++ phys_addr_t misc_base; ++}; ++ ++#endif +diff --git a/drivers/sstar/sata_host/mdrv_sata_host1.c b/drivers/sstar/sata_host/mdrv_sata_host1.c +new file mode 100755 +index 000000000000..f2b996b97c40 +--- /dev/null ++++ b/drivers/sstar/sata_host/mdrv_sata_host1.c +@@ -0,0 +1,1862 @@ ++/* ++* mdrv_sata_host1.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include "MsIRQ.h" ++//#include "chip_int.h" ++//#include "chip_setup.h" ++#include <../../../drivers/ata/ahci.h> ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++#include "mhal_sata_host.c" ++#endif ++ ++#define SW_OOB_MODE 0 ++ ++#define sata_reg_write16(val, addr) { (*((volatile unsigned short*)(addr))) = (unsigned short)(val); } ++ ++#ifdef CONFIG_OF ++ #include ++ #include ++#endif ++ ++//#ifdef CONFIG_ARCH_INFINITY2 ++#if 0 ++extern void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv, unsigned int force_port_map, unsigned int mask_port_map); ++#else ++extern void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv); ++#endif ++ ++extern int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); ++extern int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); ++extern unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg); ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ //extern u32 ahci_reg_read(phys_addr_t reg_addr); ++ //extern void ahci_reg_write(u32 data, phys_addr_t p_reg_addr);; ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++#endif ++ ++#define SATA_DEBUG ++#ifdef SATA_DEBUG ++ #define sata_debug(fmt, args...) printk("[SATA0][%s] " fmt, __FUNCTION__, ##args) ++#else ++ #define sata_debug(fmt, args...) do {} while(0) ++#endif ++#define sata_info(fmt, args...) printk("[SATA0][INFO] " fmt, ##args) ++#define sata_error(fmt, args...) printk("[SATA0][ERR] " fmt, ##args) ++ ++//#define SPEED_TEST1 ++ ++#ifdef SPEED_TEST1 ++ struct timespec proc_start; ++ u32 g_u32Diff1; ++ u32 u32Diff[10]; ++ static u32 u32Cnt = 0; ++#endif ++ ++struct prdte ++{ ++ u32 dba; ++ u32 dbau; ++ u32 rev1; ++ ++ u32 dbc: 22; ++ u32 rev2: 9; ++ u32 i: 1; ++}; ++ ++struct sata_sstar_host_priv *ss_hpriv1; ++ ++#if 0 ++static void print_fis(hal_cmd_h2dfis *pfis) ++{ ++ hal_cmd_h2dfis * p = pfis; ++ ++ printk("fis @ 0x%8.8x, fis size = 0x%x\n", (unsigned int)pfis, sizeof(hal_cmd_h2dfis)); ++ printk("fis phys @ 0x%8.8x\n", virt_to_phys(pfis)); ++ printk("fis type = 0x%x\n", p->u8fis_type); ++ printk("PMP:4\t = 0x%x\n", p->u8MPM); ++ printk("rev:3\t = 0x%x\n", p->reserved_0); ++ printk("iscmd:1\t = 0x%x\n", p->isclear); ++ printk("ata cmd\t = 0x%x\n", p->ata_cmd); ++ printk("feat.\t = 0x%x\n", p->fearure); ++ printk("lba_l\t = 0x%x\n", p->lba_l); ++ printk("lba_m\t = 0x%x\n", p->lba_m); ++ printk("lba_h\t = 0x%x\n", p->lba_h); ++ printk("dev\t = 0x%x\n", p->device); ++ printk("lba_l_e\t = 0x%x\n", p->lba_l_exp); ++ printk("lba_m_e\t = 0x%x\n", p->lba_m_exp); ++ printk("lba_h_e\t = 0x%x\n", p->lba_h_exp); ++ printk("feat. ex = 0x%x\n", p->fearure_exp); ++ printk("sector\t = 0x%x (u16)\n", p->u16sector_cnt); ++ printk("rev\t = 0x%x\n", p->reserved_1); ++ printk("ctrl\t = 0x%x\n", p->control); ++ printk("rev \t = 0x%x (u32)\n", p->reserved_2); ++} ++ ++static void print_prdt(struct prdte * pt, u32 num) ++{ ++ struct prdte * p = pt; ++ int i; ++ printk("prdt @ 0x%8.8x, prdte size = 0x%x, total = 0x%x\n", (unsigned int)pt, sizeof(struct prdte), sizeof(struct prdte) * num); ++ ++ printk("prdt @ phys 0x%8.8x\n", virt_to_phys(pt)); ++ for (i = 0; i < num; i++, p++) ++ { ++ printk("dba\t = 0x%x (u32)\n", p->dba); ++ printk("dbau\t = 0x%x (u32)\n", p->dbau); ++ printk("rev1\t = 0x%x (u32)\n", p->rev1); ++ printk("dbc\t = 0x%x (:22)\n", p->dbc); ++ printk("rev2\t = 0x%x (:9)\n", p->rev2); ++ printk("i\t = 0x%x (:1)\n", p->i); ++ } ++} ++static void p_prdt(struct prdte * pt) ++{ ++ struct prdte * p = pt; ++ int i; ++ printk("prdt @ 0x%8.8x, prdte size = 0x%x\n", (unsigned int)pt, sizeof(struct prdte)); ++ ++ printk("dba\t = 0x%x (u32)\n", p->dba); ++ printk("dbau\t = 0x%x (u32)\n", p->dbau); ++ printk("rev1\t = 0x%x (u32)\n", p->rev1); ++ printk("dbc\t = 0x%x (:22)\n", p->dbc); ++ printk("rev2\t = 0x%x (:9)\n", p->rev2); ++ printk("i\t = 0x%x (:1)\n", p->i); ++} ++#endif ++#if 0 ++static void print_cmd_header(hal_cmd_header *p) ++{ ++ printk(KERN_DEBUG "command header @ 0x%8.8x, cmd header size = 0x%x\n", (unsigned int)p, sizeof(hal_cmd_header)); ++ ++ // printk(KERN_DEBUG "cmd fis len\t = 0x%x (:5)\n", p->cmd_fis_len); ++ // printk(KERN_DEBUG "isATAPI\t = 0x%x (:1)\n", p->isATA_PI); ++ // printk(KERN_DEBUG "isWrite\t = 0x%x (:1)\n", p->iswrite); ++ // printk(KERN_DEBUG "isprefetch\t = 0x%x (:1)\n", p->isprefetch); ++ // printk(KERN_DEBUG "isswrst\t = 0x%x (:1)\n", p->issoftreset); ++ // printk(KERN_DEBUG "isbist\t = 0x%x (:1)\n", p->isbist); ++ // printk(KERN_DEBUG "isclrok\t = 0x%x (:1)\n", p->isclearok); ++ // printk(KERN_DEBUG "rev1\t = 0x%x (:1)\n", p->reserverd); ++ // printk(KERN_DEBUG "PMPid\t = 0x%x (:4)\n", p->PMPid); ++ // printk(KERN_DEBUG "PRDlen\t = 0x%x (16)\n", p->PRDTlength); ++ // printk(KERN_DEBUG "PRDbyte\t = 0x%x (32)\n", p->PRDBytes); ++ // printk(KERN_DEBUG "ctbal\t = 0x%x (32)\n", p->ctba_lbase); ++ // printk(KERN_DEBUG "ctbah\t = 0x%x (32)\n", p->ctba_hbase); ++ // printk("resv1\t = 0x%x (32)\n", p->resv[0]); ++ // printk("resv2\t = 0x%x (32)\n", p->resv[1]); ++ // printk("resv3\t = 0x%x (32)\n", p->resv[2]); ++ // printk("resv4\t = 0x%x (32)\n", p->resv[3]); ++} ++#endif ++ ++static void build_cmd_fis1(void *cmd_tbl, hal_cmd_h2dfis *pfis, phys_addr_t misc_base) ++{ ++#if (SATA_CMD_TYPE != TYPE_RIU) ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ unsigned long u32MiscAddr = misc_base; ++ ++ writew(0x00, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++ ++ memcpy(cmd_tbl, pfis, sizeof(hal_cmd_h2dfis)); ++ //print_fis((hal_cmd_h2dfis *)cmd_tbl); ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ writew(0x01, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++#else // TYPE_RIU mode ++ u32 address = (u32)cmd_tbl; ++ u32 * dptr = (u32 *)pfis; ++ u32 offset; ++ ++ address = (u32)cmd_tbl; ++ ++ // loop through data ++ for (offset = 0; offset < sizeof(hal_cmd_h2dfis); offset += 4) ++ { ++ // which address to write? ++ writel(address, (void*)misc_base + SATA_MISC_CFIFO_ADDRL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", address, misc_base + SATA_MISC_CFIFO_ADDRL); ++ ++ // what data to write? ++ writel(*dptr, (void*)misc_base + SATA_MISC_CFIFO_WDATAL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", *dptr, misc_base + SATA_MISC_CFIFO_WDATAL); ++ ++ // read(0) or write(1)? normally write ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_RORW); ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_RORW); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_RORW); ++ ++ // trigger ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_ACCESS); ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_ACCESS); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_ACCESS); ++ ++ address += 4; ++ dptr++; ++ } ++ ++#endif ++} ++ ++static void build_cmd_prdt1(void *base_address, u32 *pprdt, phys_addr_t misc_base, u32 prdt_num) ++{ ++#if (SATA_CMD_TYPE != TYPE_RIU) ++ void *cmd_address = base_address + SATA_KA9_CMD_DESC_OFFSET_TO_PRDT; ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ unsigned long u32MiscAddr = misc_base; ++ ++ ++ writew(0x00, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++ ++ memcpy(cmd_address, pprdt, sizeof(u32)*prdt_num * 4); ++ //print_prdt(cmd_address, prdt_num); ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ writew(0x01, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++#else // TYPE_RIU ++ u32 address = (u32)base_address + SATA_KA9_CMD_DESC_OFFSET_TO_PRDT; ++ u32 * dptr = pprdt; ++ u32 offset; ++ ++ //p_prdt((struct prdte *)pprdt); ++ ++ for (offset = 0; offset < sizeof(u32) * prdt_num * 4; offset += 4) ++ { ++ // which address to write? ++ writel(address, (void*)misc_base + SATA_MISC_CFIFO_ADDRL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", address, misc_base + SATA_MISC_CFIFO_ADDRL); ++ ++ // what data to write? ++ writel(*dptr, (void*)misc_base + SATA_MISC_CFIFO_WDATAL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", *dptr, misc_base + SATA_MISC_CFIFO_WDATAL); ++ ++ // read(0) or write(1)? normally write ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_RORW); ++ //printf("write data 0x0001 to addr 0x%8.8x\n", misc_base + SATA_MISC_CFIFO_RORW); ++ ++ // trigger ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_ACCESS); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_ACCESS); ++ ++ address += 4; ++ dptr++; ++ } ++#endif ++} ++ ++ ++static void build_cmd_header1(void *cmd_slot, u32 u32offset_address, u32 *pcmdheader, phys_addr_t misc_base) ++{ ++#if (SATA_CMD_TYPE != TYPE_RIU) ++ void *cmd_address = cmd_slot + u32offset_address; ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ unsigned long u32MiscAddr = misc_base; ++ ++ writew(0x00, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++ ++ memcpy(cmd_address, pcmdheader, SATA_KA9_CMD_HDR_SIZE); ++ //print_cmd_header(cmd_address); ++ Chip_Flush_MIU_Pipe(); ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ writew(0x01, u32MiscAddr + SATA_MISC_ACCESS_MODE); ++#endif ++#else ++ u32 address = (u32)cmd_slot + u32offset_address; ++ u32 * dptr = pcmdheader; ++ u32 offset; ++ ++ for (offset = 0; offset < SATA_KA9_CMD_HDR_SIZE; offset += 4) ++ { ++ // which address to write? ++ writel(address, (void*)misc_base + SATA_MISC_CFIFO_ADDRL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", address, misc_base + SATA_MISC_CFIFO_ADDRL); ++ ++ // what data to write? ++ writel(*dptr, (void*)misc_base + SATA_MISC_CFIFO_WDATAL); ++ //printf("write data 0x%8.8x to addr 0x%x\n", *dptr, misc_base + SATA_MISC_CFIFO_WDATAL); ++ ++ // read(0) or write(1)? normally write ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_RORW); ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_RORW); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_RORW); ++ ++ // trigger ++ //sata_reg_write16(0x01, misc_base + SATA_MISC_CFIFO_ACCESS); ++ writew(0x01, (volatile void *)misc_base + SATA_MISC_CFIFO_ACCESS); ++ //printf("write data 0x0001 to addr 0x%x\n", misc_base + SATA_MISC_CFIFO_ACCESS); ++ ++ address += 4; ++ dptr++; ++ } ++#endif ++} ++ ++ ++static irqreturn_t sstar_ahci_single_level_irq_intr1(int irq, void *dev_instance) ++{ ++ struct ata_host *host = dev_instance; ++ struct ahci_host_priv *hpriv; ++ unsigned int rc = 0; ++ void __iomem *mmio; ++ u32 irq_stat, irq_masked; ++ ++ VPRINTK("ENTER\n"); ++ ++ hpriv = host->private_data; ++ mmio = hpriv->mmio; ++ ++ /* sigh. 0xffffffff is a valid return from h/w */ ++ irq_stat = readl(mmio + HOST_IRQ_STAT); ++ if (!irq_stat) ++ return IRQ_NONE; ++ ++ irq_masked = irq_stat & hpriv->port_map; ++ ++ spin_lock(&host->lock); ++ ++ rc = ahci_handle_port_intr(host, irq_masked); ++ ++ /* HOST_IRQ_STAT behaves as level triggered latch meaning that ++ * it should be cleared after all the port events are cleared; ++ * otherwise, it will raise a spurious interrupt after each ++ * valid one. Please read section 10.6.2 of ahci 1.1 for more ++ * information. ++ * ++ * Also, use the unmasked value to clear interrupt as spurious ++ * pending event on a dummy port might cause screaming IRQ. ++ */ ++ writel(irq_stat, mmio + HOST_IRQ_STAT); ++ ++ spin_unlock(&host->lock); ++ ++ VPRINTK("EXIT\n"); ++ ++ return IRQ_RETVAL(rc); ++} ++ ++static inline unsigned int sata_sstar_tag1(unsigned int tag) ++{ ++ /* all non NCQ/queued commands should have tag#0 */ ++ if (ata_tag_internal(tag)) ++ { ++ return 0; ++ } ++ ++ if (unlikely(tag >= SATA_SSTAR_QUEUE_DEPTH)) ++ { ++ DPRINTK("tag %d invalid : out of range\n", tag); ++ //printk("[%s][%d]\n",__FUNCTION__,__LINE__); ++ return 0; ++ } ++ return tag; ++} ++ ++static void sata_sstar_setup_cmd_hdr_entry1(struct sata_sstar_port_priv *pp, ++ unsigned int tag, u32 data_xfer_len, u8 num_prde, ++ u8 fis_len, phys_addr_t misc_base) ++{ ++ dma_addr_t cmd_descriptor_address; ++ hal_cmd_header cmd_header = {0}; ++ void *cmd_slot = pp->cmd_slot; ++ ++ cmd_descriptor_address = pp->cmd_tbl_dma + tag * SATA_KA9_CMD_DESC_SIZE; ++ ++ cmd_header.cmd_fis_len = fis_len; ++ cmd_header.PRDTlength = num_prde; ++ cmd_header.isclearok = 0; ++ cmd_header.PRDBytes = data_xfer_len; ++ cmd_header.ctba_hbase = 0; ++ cmd_header.ctba_lbase = cmd_descriptor_address; ++ ++ build_cmd_header1(cmd_slot, tag * SATA_KA9_CMD_HDR_SIZE, (u32 *)&cmd_header, misc_base); ++} ++ ++static unsigned int sata_sstar_fill_sg1(struct ata_queued_cmd *qc, ++ u32 *ttl, void *cmd_tbl, phys_addr_t misc_base) ++{ ++ struct scatterlist *sg; ++ u32 ttl_dwords = 0; ++ u32 prdt[SATA_KA9_USED_PRD * 4] = {0}; ++ unsigned int si; ++ ++ for_each_sg(qc->sg, sg, qc->n_elem, si) ++ { ++ dma_addr_t sg_addr = sg_dma_address(sg); ++ u32 sg_len = sg_dma_len(sg); ++ ++ if (si == (SATA_KA9_USED_PRD - 1) && ((sg_next(sg)) != NULL)) ++ { ++ sata_error("setting indirect prde , out of prdt\n"); ++ } ++ ttl_dwords += sg_len; ++ ++ prdt[si * 4 + 0] = (u32)(MHal_SATA_bus_address(cpu_to_le32(sg_addr))); ++ prdt[si * 4 + 1] = (u32)(MHal_SATA_bus_address(cpu_to_le32(sg_addr)) >> 16); ++ prdt[si * 4 + 2] = 0xFFFFFFFF; ++ prdt[si * 4 + 3] = (cpu_to_le32(sg_len) - 1); ++ } ++ build_cmd_prdt1(cmd_tbl, &prdt[0], misc_base, si); ++ *ttl = ttl_dwords; ++ return si; ++} ++ ++static u32 sstar_sata_wait_reg1(phys_addr_t reg_addr, u32 mask, u32 val, unsigned long interval, unsigned long timeout) ++{ ++ u32 temp; ++ unsigned long timeout_vale = 0; ++ ++ temp = readl((void*)reg_addr); ++ ++ while((temp & mask) == val) ++ { ++ msleep(interval); ++ timeout_vale += interval; ++ if (timeout_vale > timeout) ++ break; ++ temp = readl((void*)reg_addr); ++ } ++ return temp; ++} ++ ++static int sstar_ahci_stop_engine1(phys_addr_t port_base) ++{ ++ u32 temp; ++ ++ temp = readl((void*)SS_PORT_CMD + port_base); ++ ++ /* check if the HBA is idle */ ++ if ((temp & (SS_PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) ++ return 0; ++ ++ /* setting HBA to idle */ ++ temp &= ~PORT_CMD_START; ++ writel(temp, (void*)SS_PORT_CMD + port_base); ++ ++ temp = sstar_sata_wait_reg1(SS_PORT_CMD + port_base, PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); ++ ++ if (temp & PORT_CMD_LIST_ON) ++ return -EIO; ++ ++ return 0; ++} ++ ++static void sstar_ahci_start_engine1(phys_addr_t port_base) ++{ ++ u32 temp; ++ ++ /* Start Port DMA */ ++ temp = readl((void*)SS_PORT_CMD + port_base); ++ temp |= PORT_CMD_START; ++ writel(temp, (void*)SS_PORT_CMD + port_base); ++ readl((void*)SS_PORT_CMD + port_base); /* Flush */ ++} ++ ++static void sstar_ahci_start_fis_rx1(struct ata_port *ap) ++{ ++ struct sata_sstar_port_priv *pp = ap->private_data; ++ phys_addr_t port_base =ss_hpriv1->port_base;//SATA_GHC_1_ADDRESS_START; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; //SATA_GHC_0_P0_ADDRESS_START; ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ ++ u32 tmp; ++ ++ // set FIS registers ++ tmp = pp->cmd_slot_dma; ++ writel(tmp, (void*)SS_PORT_LST_ADDR + port_base); ++ ++ tmp = pp->rx_fis_dma; ++ writel(tmp, (void*)SS_PORT_FIS_ADDR + port_base); ++ ++ // enable FIS reception ++ tmp = readl((void*)SS_PORT_CMD + port_base); ++ tmp |= PORT_CMD_FIS_RX; ++ writel(tmp, (void*)SS_PORT_CMD + port_base); ++ ++ // flush ++ tmp = readl((void*)SS_PORT_CMD + port_base); ++} ++ ++static int sstar_ahci_stop_fis_rx1(struct ata_port *ap) ++{ ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ phys_addr_t port_base =ss_hpriv1->port_base;//SATA_GHC_1_ADDRESS_START; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base =SATA_GHC_0_P0_ADDRESS_START;//host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ u32 tmp; ++ ++ // Disable FIS reception ++ tmp = readl((void*)SS_PORT_CMD + port_base); ++ tmp &= ~PORT_CMD_FIS_RX; ++ writel(tmp, (void*)SS_PORT_CMD + port_base); ++ ++ // Wait FIS reception Stop for 1000ms ++ tmp = sstar_sata_wait_reg1(SS_PORT_CMD + port_base, PORT_CMD_FIS_ON, PORT_CMD_FIS_ON, 10, 1000); ++ ++ if (tmp & PORT_CMD_FIS_ON) ++ return -EBUSY; ++ ++ return 0; ++} ++ ++void GetStartTime1(void) ++{ ++#ifdef SPEED_TEST1 ++ getnstimeofday(&proc_start); ++#endif ++} ++ ++void GetEndTime1(void) ++{ ++#ifdef SPEED_TEST1 ++ u32 delta; ++ struct timespec ct; ++ ++ getnstimeofday(&ct); ++ delta = ct.tv_nsec + ((proc_start.tv_sec != ct.tv_sec) ? NSEC_PER_SEC : 0) ++ - proc_start.tv_nsec; ++ ++ //if((delta / 1000) <= 100000) ++ { ++ //if((delta / 1000) > g_u32Diff1) ++ g_u32Diff1 = (delta / 1000); ++ } ++#endif ++} ++ ++void PrintTime1(void) ++{ ++#ifdef SPEED_TEST1 ++ //int i; ++ ++ //if((h2dfis.u8fis_type == 0x27) && ((h2dfis.ata_cmd == 0x60) || (h2dfis.ata_cmd == 0x61))) ++ { ++ u32Diff[u32Cnt] = g_u32Diff1; ++ u32Cnt++; ++ if(u32Cnt >= 10) ++ u32Cnt = 0; ++ ++ if((u32Cnt % 10) == 9) ++ { ++ //for(i = 0 ; i < 10 ; i++) ++ printk("%d, %d, %d, %d, %d, %d\n", (int)(u32Diff[2]), (int)(u32Diff[3]), (int)(u32Diff[4]), (int)(u32Diff[5]), (int)(u32Diff[6]), (int)(u32Diff[7])); // 246, 209,209 ++ } ++ } ++#endif ++} ++ ++static void sata_sstar_qc_prep1(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct sata_sstar_port_priv *pp = ap->private_data; ++ u32 misc_base = ss_hpriv1->misc_base; ++ //struct sata_sstar_host_priv *host_priv = qc->ap->ss_private_data; ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ unsigned int tag = sata_sstar_tag1(qc->tag); ++ hal_cmd_h2dfis h2dfis; ++ u32 num_prde = 0; ++ u32 ttl_dwords = 0; ++ void *cmd_tbl; ++ ++#ifdef SPEED_TEST1 ++ //GetEndTime1(); ++#endif ++ ++ //printk("%s\n", __func__); ++#ifdef SPEED_TEST1 ++ //GetStartTime1(); ++#endif ++ ++ cmd_tbl = pp->cmd_tbl + (tag * SATA_KA9_CMD_DESC_SIZE); ++ ++ ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *)&h2dfis); ++ ++ build_cmd_fis1(cmd_tbl, &h2dfis, misc_base); ++ ++ if (qc->flags & ATA_QCFLAG_DMAMAP) ++ { ++ num_prde = sata_sstar_fill_sg1(qc, &ttl_dwords, cmd_tbl, misc_base); ++ } ++ ++ sata_sstar_setup_cmd_hdr_entry1(pp, tag, ttl_dwords, ++ num_prde, 5, misc_base); ++ ++} ++ ++static unsigned int sata_sstar_qc_issue1(struct ata_queued_cmd *qc) ++{ ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ unsigned int tag = sata_sstar_tag1(qc->tag); ++ //struct sata_mstar_host_priv *host_priv = qc->ap->host->private_data; ++ //struct sata_sstar_host_priv *host_priv = qc->ap->ss_private_data; ++ //struct sata_mstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base =SATA_GHC_0_P0_ADDRESS_START;// host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ ++ struct ata_port *ap = qc->ap->host->ports[0]; ++ struct ata_link *link = qc->dev->link; ++ struct ahci_port_priv *pp = ap->private_data; ++ ++ //printk("%s\n", __func__); ++ ++ if (qc->tf.protocol == ATA_PROT_NCQ) ++ { ++ //printk("NCQ device- %d\n", qc->tag); ++ writel(1 << qc->tag, (void*)SS_PORT_SCR_ACT + port_base); ++// ap->sactive = link->sactive; // save ncq active tag ++ pp->active_link->sactive = link->sactive; ++ //sata_info("sactive = 0x%x\n", ap->sactive); ++ } ++ writel(1 << tag, (void*)SS_PORT_CMD_ISSUE + port_base); ++ ++#ifdef SPEED_TEST1 ++ //GetStartTime1(); ++#endif ++ ++ return 0; ++} ++ ++static bool sata_sstar_qc_fill_rtf1(struct ata_queued_cmd *qc) ++{ ++ struct sata_sstar_port_priv *pp = qc->ap->private_data; ++ //struct sata_mstar_host_priv *host_priv = qc->ap->host->private_data; ++ //unsigned int tag = sata_mstar_tag(qc->tag); ++ //hal_cmd_h2dfis cd; ++ //phys_addr_t misc_base = host_priv->misc_base; ++ //void *rx_fis; ++ u8 *rx_fis; ++ ++ rx_fis = pp->rx_fis; ++#if 0 ++ read_cmd_fis(rx_fis, (tag * SATA_KA9_CMD_DESC_SIZE), &cd, misc_base); ++ ata_tf_from_fis((const u8 *)&cd, &qc->result_tf); ++#endif ++ if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && ++ !(qc->flags & ATA_QCFLAG_FAILED)) ++ { ++ ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); ++ qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; ++ DPRINTK("--- result_tf.command = 0x%x\n", qc->result_tf.command); ++ } ++ else ++ { ++ ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); ++ } ++ return true; ++} ++ ++static unsigned sata_sstar_scr_offset1(struct ata_port *ap, unsigned int sc_reg) ++{ ++ static const int offset[] = { ++ [SCR_STATUS] = PORT_SCR_STAT, ++ [SCR_CONTROL] = PORT_SCR_CTL, ++ [SCR_ERROR] = PORT_SCR_ERR, ++ [SCR_ACTIVE] = PORT_SCR_ACT, ++ [SCR_NOTIFICATION] = PORT_SCR_NTF, ++ }; ++ struct ahci_host_priv *hpriv = ap->host->private_data; ++ ++ if (sc_reg < ARRAY_SIZE(offset) && ++ (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) ++ return offset[sc_reg]; ++ return 0; ++} ++ ++static int sata_sstar_scr_read1(struct ata_link *link, unsigned int sc_reg, u32 *val) ++{ ++ int offset = sata_sstar_scr_offset1(link->ap, sc_reg); ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_mstar_host_priv *host_priv = link->ap->host->private_data; ++ //struct sata_sstar_host_priv *host_priv = link->ap->ss_private_data; ++ //struct sata_mstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base =SATA_GHC_0_P0_ADDRESS_START; ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ if (offset) ++ { ++ *val = readl((void*)offset + port_base); ++ return 0; ++ } ++ return -1; ++} ++ ++static int sata_sstar_scr_write1(struct ata_link *link, unsigned int sc_reg_in, u32 val) ++{ ++ int offset = sata_sstar_scr_offset1(link->ap, sc_reg_in); ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_mstar_host_priv *host_priv = ap->ms_private_data; ++ //struct sata_sstar_host_priv *host_priv = link->ap->ss_private_data; ++ ++ //phys_addr_t port_base = host_priv->port_base; ++ //struct sata_mstar_host_priv *host_priv = link->ap->host->private_data; ++ //phys_addr_t port_base =SATA_GHC_0_P0_ADDRESS_START;//= host_priv->port_base; ++ // phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ if (offset) ++ { ++ writel(val, (void*)offset + port_base); ++ return 0; ++ } ++ return -1; ++} ++ ++static void sata_sstar_freeze1(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ // phys_addr_t port_base = host_priv->port_base; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base =SATA_GHC_0_P0_ADDRESS_START; ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ writel(0, (void*)SS_PORT_IRQ_MASK + port_base); ++} ++ ++static void sata_sstar_thaw1(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ phys_addr_t hba_base = ss_hpriv1->hba_base; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //struct sata_sstar_host_priv *host_priv = ap->host->private_data; ++ //phys_addr_t hba_base = host_priv->hba_base; ++ //phys_addr_t hba_base = host_priv->hba_base;//SATA_GHC_0_ADDRESS_START; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_0_P0_ADDRESS_START;//SATA_GHC_1_ADDRESS_START; ++ u32 u32Temp = 0; ++ ++ // clear IRQ ++ u32Temp = readl((void*)SS_PORT_IRQ_STAT + port_base); ++ writel(u32Temp, (void*)SS_PORT_IRQ_STAT + port_base); ++ ++ // Clear Port 0 IRQ on HBA ++ u32Temp = readl((void*)SS_HOST_IRQ_STAT + hba_base); ++ writel(u32Temp, (void*)SS_HOST_IRQ_STAT + hba_base); ++ ++ // Enable Host Interrupt ++ u32Temp = readl((void*)SS_HOST_CTL + hba_base); ++ u32Temp |= HOST_IRQ_EN; ++ writel(u32Temp, (void*)SS_HOST_CTL + hba_base); ++ ++ // Enable Port Interrupt ++ writel(DEF_PORT_IRQ, (void*)SS_PORT_IRQ_MASK + port_base); ++ readl((void*)SS_PORT_IRQ_MASK + port_base); ++} ++ ++static unsigned int sata_sstar_dev_classify1(struct ata_port *ap) ++{ ++ struct ata_taskfile tf; ++ u32 temp = 0; ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ ++ //temp = mstar_sata_reg_read(PORT_SIG + host_priv->port_base); ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ temp = readl((void*)PORT_SIG + port_base/*SATA_GHC_0_P0_ADDRESS_START*/); ++ ++ tf.lbah = (temp >> 24) & 0xff; ++ tf.lbam = (temp >> 16) & 0xff; ++ tf.lbal = (temp >> 8) & 0xff; ++ tf.nsect = temp & 0xff; ++ return ata_dev_classify(&tf); ++} ++ ++int sstar_ahci_check_ready1(struct ata_link *link) ++{ ++ ++ u8 status; ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_mstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //struct ata_port *ap = link->ap; ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ //struct sata_sstar_host_priv *host_priv = link->ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_0_P0_ADDRESS_START; ++ status = readl((void*)SS_PORT_TFDATA + port_base) & 0xFF; ++ ++ return ata_check_ready(status); ++} ++ ++#define CONNECTION_RETRY 5 ++static int sata_sstar_hardreset1(struct ata_link *link, unsigned int *class, ++ unsigned long deadline) ++{ ++ struct ata_port *ap = link->ap; ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ phys_addr_t misc_base = ss_hpriv1->misc_base; ++ ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_0_P0_ADDRESS_START; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t misc_base = host_priv->misc_base; ++ bool online; ++ int rc; ++ //u32 sstatus; ++ //u32 retry = 0; ++ //u16 u16Temp; ++ ++ //printk("%s:port_base:%X\n", __func__, port_base); ++ //printk("%s:host_priv->port_base:%X\n", __func__, host_priv->port_base); ++ ++ //hard_reset: ++ sstar_ahci_stop_engine1(port_base); ++ ++ rc = sata_link_hardreset(link, timing, deadline, &online, ++ sstar_ahci_check_ready1); ++ ++ sstar_ahci_start_engine1(port_base); ++ ++#if 0//CONFIG_sstar_K6Lite // sw patch for gen3 ++ if (online) ++ { ++ rc = sata_sstar_scr_read1(link, SCR_STATUS, &sstatus); ++ sata_info("SStatus = 0x%x\n", sstatus); ++ if (rc == 0 && ((sstatus & 0xf) == 0x3)) // 0x3 => device presence detected and Phy communication established ++ { ++ if ((((sstatus >> 4) & 0xf) == 0x01) && retry++ < CONNECTION_RETRY) // gen1 ++ { ++ sata_info("Gen1 connection detected, SATA PHY retrain %d\n", retry); ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ u16Temp &= ~0x200; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ u16Temp |= 0x200; ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x10390e << 1)); ++ goto hard_reset; ++ } ++ } ++ } ++ if (retry >= CONNECTION_RETRY) ++ sata_info("Gen1 HDD detected\n"); ++#endif ++ ++ if (online) ++ *class = sata_sstar_dev_classify1(ap); ++ else ++ MHal_SATA_Clock_Config(misc_base, port_base, FALSE); ++ ++ printk(KERN_INFO "[%s][port_base:0x%08x] done : %s\n", __func__, port_base, (online ? "online" : "offline")); ++ return rc; ++} ++ ++static int sata_sstar_softreset1(struct ata_link *link, unsigned int *class, ++ unsigned long deadline) ++{ ++ // Unused Function ++ return 0; ++} ++ ++static void sata_sstar_error_handler1(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ struct ata_device *dev = ap->link.device; ++ ++ DPRINTK("%s begin\n", __func__); ++ if (!(ap->pflags & ATA_PFLAG_FROZEN)) ++ { ++ sstar_ahci_stop_engine1(port_base); ++ sstar_ahci_start_engine1(port_base); ++ } ++ sata_pmp_error_handler(ap); ++ ++ //if (!ata_dev_enable(ap->link.device)) ++ if (!(dev->class == ATA_DEV_ATA || ++ dev->class == ATA_DEV_ATAPI || ++ dev->class == ATA_DEV_PMP || ++ dev->class == ATA_DEV_SEMB)) ++ sstar_ahci_stop_engine1(port_base); ++ ++ DPRINTK("%s end\n", __func__); ++} ++ ++static int sstar_ahci_kick_engine1(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_1_ADDRESS_START; ++ struct ahci_host_priv *hpriv = ap->host->private_data; ++ u8 status = readl((void*)port_base + SS_PORT_TFDATA); ++ u32 tmp; ++ int busy, rc; ++ ++ rc = sstar_ahci_stop_engine1(port_base); ++ if (rc) ++ goto out_restart; ++ ++ busy = status & (ATA_BUSY | ATA_DRQ); ++ if (!busy && !sata_pmp_attached(ap)) ++ { ++ rc = 0; ++ goto out_restart; ++ } ++ if (!(hpriv->cap & HOST_CAP_CLO)) ++ { ++ rc = -EOPNOTSUPP; ++ goto out_restart; ++ } ++ ++ tmp = readl((void*)port_base + SS_PORT_CMD); ++ tmp |= PORT_CMD_CLO; ++ writel(tmp, (void*)port_base + SS_PORT_CMD); ++ ++ rc = 0; ++ tmp = ata_wait_register(ap, (void __iomem *) port_base + SS_PORT_CMD, ++ (u32)PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); ++ if (tmp & PORT_CMD_CLO) ++ rc = -EIO; ++out_restart: ++ sstar_ahci_start_engine1(port_base); ++ return rc; ++} ++ ++static void sata_sstar_post_internal_cmd1(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ ++ if (qc->flags & ATA_QCFLAG_FAILED) ++ sstar_ahci_kick_engine1(ap); ++ //qc->err_mask |= AC_ERR_OTHER; ++#if 0 ++ if (qc->err_mask) ++ { ++ /* make DMA engine forget about the failed command */ ++ } ++#endif ++} ++ ++static int sata_sstar_port_start1(struct ata_port *ap) ++{ ++ struct sata_sstar_port_priv *pp; ++ //struct sata_sstar_host_priv *host_priv = ap->host->ports[0]->private_data; ++ u32 temp; ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //phys_addr_t port_base = host_priv->port_base; ++ ++ u32 GHC_PHY = 0x0; ++ ++#if (SATA_CMD_TYPE == TYPE_DRAM) ++ struct device *dev = ap->host->dev; ++ void *mem; ++ dma_addr_t mem_dma; ++ size_t dma_sz; ++#endif ++ ++ // Allocate SATA Port Private Data ++ pp = kzalloc(sizeof(*pp), GFP_KERNEL); ++ if (!pp) ++ { ++ printk("[%s][Error] SATA Allocate Port Private Data Fail\n", __func__); ++ return -ENOMEM; ++ } ++ ++#if (SATA_CMD_TYPE == TYPE_XIU) ++ printk(KERN_INFO "SATA cmd type: XIU\n"); ++ pp->cmd_slot = (void *)(SATA_SDMAP_RIU_BASE + (AHCI_P0CLB & 0xfff)); ++ pp->rx_fis = (void *)(SATA_SDMAP_RIU_BASE + (AHCI_P0FB & 0xfff)); ++ pp->cmd_tbl = (void *)(SATA_SDMAP_RIU_BASE + (AHCI_CTBA0 & 0xfff)); ++ ++ pp->cmd_slot_dma = AHCI_P0CLB; ++ pp->rx_fis_dma = AHCI_P0FB; ++ pp->cmd_tbl_dma = AHCI_CTBA0; ++ ++#elif (SATA_CMD_TYPE == TYPE_DRAM) ++ sata_info("SATA cmd type: DRAM\n"); ++ dma_sz = 0x10000; ++ mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); ++ if (!mem) ++ return -ENOMEM; ++ memset(mem, 0, dma_sz); ++ ++ pp->cmd_slot = mem; ++ // Translate physical address to bus address since SATA engine uses bus address. ++ mem_dma = (dma_addr_t)MHal_SATA_bus_address(mem_dma); ++ pp->cmd_slot_dma = mem_dma; ++ ++ mem += SATA_CMD_HEADER_SIZE; ++ mem_dma += SATA_CMD_HEADER_SIZE; ++ ++ pp->rx_fis = mem; ++ pp->rx_fis_dma = mem_dma; ++ ++ mem += SATA_FIS_SIZE; ++ mem_dma += SATA_FIS_SIZE; ++ ++ pp->cmd_tbl = mem; ++ pp->cmd_tbl_dma = mem_dma; ++ ++#elif (SATA_CMD_TYPE == TYPE_RIU) ++ sata_info("SATA cmd type: RIU\n"); ++ pp->cmd_slot = (void *)(AHCI_P0CLB); ++ pp->rx_fis = (void *)(AHCI_P0FB); ++ pp->cmd_tbl = (void *)(AHCI_CTBA0); ++ ++ pp->cmd_slot_dma = AHCI_P0CLB; ++ pp->rx_fis_dma = AHCI_P0FB; ++ pp->cmd_tbl_dma = AHCI_CTBA0; ++#else ++#error "SATA_CMD_TYPE Unknown" ++#endif ++ ++ sata_info("cmd_slot = 0x%x ; cmd_slot_dma = 0x%x\n", (u32)pp->cmd_slot, (u32)pp->cmd_slot_dma); ++ sata_info("rx_fis = 0x%x ; rx_fis_dma = 0x%x\n", (u32)pp->rx_fis, (u32)pp->rx_fis_dma); ++ sata_info("cmd_tbl = 0x%x ; cmd_tbl_dma = 0x%x\n", (u32)pp->cmd_tbl, (u32)pp->cmd_tbl_dma); ++ ++ //sata_info("port_base= 0x%x ;\n", port_base); ++ ++ ap->private_data = pp; ++// ap->ss_private_data = host_priv; ++ temp = readl((void*)SS_PORT_CMD + port_base) & ~PORT_CMD_ICC_MASK; ++ ++ // spin up device ++ temp |= PORT_CMD_SPIN_UP; ++ writel(temp, (void*)SS_PORT_CMD + port_base); ++ ++ // wake up link ++ writel((temp | PORT_CMD_ICC_ACTIVE), (void*)SS_PORT_CMD + port_base); ++ ++ // start FIS RX ++ sstar_ahci_start_fis_rx1(ap); ++ ++ // Clear IS , Interrupt Status ++ writel(0xFFFFFFFF, (void*)SS_PORT_IRQ_STAT + port_base); ++ writel(0xFFFFFFFF, (void*)SS_PORT_SCR_ERR + port_base); ++ ++ // set to speed limit with gen 1, gen 2 or auto ++ temp = readl((void*)SS_PORT_SCR_CTL + port_base); ++ temp = temp & (~E_PORT_SPEED_MASK); // clear speed ++ temp = temp | MHal_SATA_get_max_speed(); ++ writel(temp,(void*) SS_PORT_SCR_CTL + port_base); ++ ++ if(port_base == SATA_GHC_0_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_0_PHY;//0x103900 ++ } ++#ifdef CONFIG_ARCH_INFINITY2 ++ else if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ GHC_PHY = SATA_GHC_1_PHY;//0x162A00 ++ } ++#endif ++ // test: enable PHY ++ writew(0x9a8f, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); // [0]: Reset ++ writew(0x9a8e, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x02) << 1)); ++ writew(0x2200, (volatile void *)SSTAR_RIU_BASE + ((GHC_PHY | 0x0e) << 1)); // [9]: Enable host ++ ++ printk("sstar_ahci_start_engine1\n"); ++ // MHal_SATA_HW_Inital(misc_base, port_base, hba_base); ++ ++ // Start DMA Engine ++ sstar_ahci_start_engine1(port_base); ++ ++ return 0; ++} ++ ++static void sata_sstar_port_stop1(struct ata_port *ap) ++{ ++ phys_addr_t port_base = ss_hpriv1->port_base; ++ //struct sata_mstar_host_priv *host_priv = ap->host->private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ //phys_addr_t port_base = SATA_GHC_0_P0_ADDRESS_START; ++ //struct sata_sstar_host_priv *host_priv = ap->ss_private_data; ++ //phys_addr_t port_base = host_priv->port_base; ++ int ret; ++ ++ sata_info("[%s]\n", __func__); ++ // Stop DMA Engine ++ ret = sstar_ahci_stop_engine1(port_base); ++ if (ret) ++ { ++ sata_error("[%s][Error] Fail to Stop SATA Port\n", __func__); ++ } ++ ++ // Disable FIS reception ++ ret = sstar_ahci_stop_fis_rx1(ap); ++ if (ret) ++ { ++ sata_error("[%s][Error] Fail to Stop FIS RX\n", __func__); ++ } ++} ++ ++#if 0 ++irqreturn_t sata_sstar_interrupt(int irq, void *dev_instance) ++{ ++ struct ata_host *host = dev_instance; ++ struct ata_port *ap = host->ports[0]; ++ struct sata_sstar_host_priv *host_priv = host->private_data; ++ struct ata_link *link = NULL; ++ struct ata_eh_info *active_ehi; ++ struct ata_eh_info *host_ehi = &ap->link.eh_info; ++ struct ata_queued_cmd *active_qc; ++ u32 serror = 0; ++ ++ ++ phys_addr_t port_base = host_priv->port_base; ++ phys_addr_t hba_base = host_priv->hba_base; ++ u32 host_status = 0; ++ u32 port_status = 0; ++ u32 qc_active; ++ //u32 port_ie; ++ u32 port_err; ++ u32 clr_port_err = 0; ++ ++#if 0 ++ link = &ap->link; ++ ehi = &link->eh_info; ++ ata_ehi_clear_desc(ehi); ++#endif ++ ++ host_status = sstar_sata_reg_read(HOST_IRQ_STAT + hba_base); ++ if (host_status) ++ printk("host_status = 0x%x\n", host_status); ++ else ++ return IRQ_NONE; ++ ++ spin_lock(&host->lock); ++ port_status = sstar_sata_reg_read(PORT_IRQ_STAT + port_base); ++ ++ sstar_sata_reg_write(port_status, PORT_IRQ_STAT + port_base); ++ if (port_status) ++ printk("port_status = 0x%x\n", port_status); ++ ++ if (port_status & (1 << 6)) // PORT_IRQ_CONNECT ++ { ++ printk(KERN_WARNING "HDD inserted (Device presence change, clear diag.X)\n"); ++ sstar_sata_reg_write((1 << 26), PORT_SCR_ERR + port_base); ++ } ++ if (port_status & (1 << 22)) // PORT_IRQ_PHYRDY ++ { ++ printk(KERN_WARNING "HDD removed (PhyRdy change, clear diag.N)\n"); ++ sstar_sata_reg_write((1 << 16), PORT_SCR_ERR + port_base); ++ //ata_ehi_hotplugged(ehi); ++ //ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); ++ } ++ ++ if (unlikely(port_status & PORT_IRQ_ERROR)) ++ { ++ link = &ap->link; ++ ++ active_qc = ata_qc_from_tag(ap, link->active_tag); ++ active_ehi = &link->eh_info; ++ ++ ata_ehi_clear_desc(host_ehi); ++ ata_ehi_push_desc(host_ehi, "irq_status 0x%08x", port_status); ++ ++ serror = sstar_sata_reg_read(PORT_SCR_ERR + port_base); ++ sstar_sata_reg_write(serror, PORT_SCR_ERR + port_base); ++ host_ehi->serror |= serror; ++ ++ if (port_status & PORT_IRQ_TF_ERR) ++ { ++ printk("IRQ TF ERROR\n"); ++ if (active_qc) ++ { ++ printk("active_qc on\n"); ++ active_qc->err_mask |= AC_ERR_DEV; ++ } ++ else ++ { ++ printk("active link on\n"); ++ active_ehi->err_mask |= AC_ERR_DEV; ++ } ++ } ++ if (port_status & PORT_IRQ_FREEZE) ++ { ++ printk("ata_port_freeze now\n"); ++ ata_port_freeze(ap); ++ } ++ else ++ { ++ printk("ata_port_abort now\n"); ++ ata_port_abort(ap); ++ } ++ goto irq_out; ++ } ++ ++ port_err = sstar_sata_reg_read(PORT_SCR_ERR + port_base); ++ if (port_err) ++ printk("port_err = 0x%x\n", port_err); ++ if (port_err & (1 << 1)) ++ { ++ printk(KERN_WARNING "SATA recovered from communication error\n"); ++ clr_port_err |= (1 << 1); ++ } ++ if (port_err & (1 << 9)) ++ { ++ printk(KERN_WARNING "SATA Persistent comm error/data integrity error\n"); ++ clr_port_err |= (1 << 9); ++ } ++ if (clr_port_err) ++ sstar_sata_reg_write(clr_port_err, PORT_SCR_ERR + port_base); ++ ++#if 0 ++ if (port_status) ++ { ++ printk("port status = 0x%x\n", port_status); ++ } ++#endif ++ ++ // clear interrupt ++ //sstar_sata_reg_write(port_status, PORT_IRQ_STAT + port_base); ++irq_out: ++ qc_active = sstar_sata_reg_read(PORT_SCR_ACT + port_base); ++ qc_active |= sstar_sata_reg_read(PORT_CMD_ISSUE + port_base); ++ ++ ata_qc_complete_multiple(ap, qc_active); ++ sstar_sata_reg_write(host_status, HOST_IRQ_STAT + hba_base); ++ spin_unlock(&host->lock); ++ ++ return IRQ_RETVAL(1); ++} ++#endif ++ ++ ++ ++#if (SW_OOB_MODE == 1) ++static void sstar_sata_sw_oob_mode1(void) ++{ ++ u16 u16Temp, u16IrqRetry, u16Irq2Retry=2; ++ ++ // Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE1_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 5; u16IrqRetry++) ++ { ++ // Check if IRQ1 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_LOCK_FLAG) ++ break; ++ ++ udelay(2); ++ } ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq2Retry--; ++ // Check if IRQ2 no ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_UNLOCK_FLAG) || u16Irq2Retry == 0) ++ goto SW_OOB_MODE1_STAGE0; ++ ++ udelay(2); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 2; u16IrqRetry++) ++ { ++ // Check if IRQ3 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) ++ break; ++ ++ udelay(1); ++ } ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#elif (SW_OOB_MODE == 2) ++static void sstar_sata_sw_oob_mode2(void) ++{ ++ u16 u16Temp, u16Irq3Retry=2; ++ ++ //Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE2_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq3Retry--; ++ // Check if IRQ3 is yes ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) || u16Irq3Retry == 0) ++ break; ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#endif ++ ++static int sstar_sata_hardware_init1(phys_addr_t hba_base, phys_addr_t port_base, phys_addr_t misc_base) ++{ ++ u32 i; ++ u32 u32Temp = 0; ++ ++ MHal_SATA_HW_Inital(misc_base, port_base, hba_base); ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ writew(HOST_RESET, (volatile void *)hba_base + (HOST_CTL)); ++#else ++ writel(HOST_RESET, (volatile void *)hba_base + (HOST_CTL)); ++#endif ++ ++ #if (SW_OOB_MODE == 1) ++ sstar_sata_sw_oob_mode1(); ++ #elif (SW_OOB_MODE == 2) ++ sstar_sata_sw_oob_mode2(); ++ #else ++ u32Temp = sstar_sata_wait_reg1(SS_HOST_CTL + hba_base, HOST_RESET, HOST_RESET, 1, 500); ++ ++ if (u32Temp & HOST_RESET) ++ return -1; ++ #endif ++ // Turn on AHCI_EN ++ u32Temp = readl((void*)SS_HOST_CTL + (phys_addr_t) hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ { ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ return 0; ++ } ++ ++ // Try AHCI_EN Trurn on for a few time ++ for (i = 0; i < 5; i++) ++ { ++ u32Temp |= HOST_AHCI_EN; ++ writel(u32Temp, (void*)SS_HOST_CTL + (phys_addr_t)hba_base); ++ u32Temp = readl((void*)SS_HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ break; ++ msleep(10); ++ } ++ ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t) port_base, (phys_addr_t) hba_base); ++ ++ //printk("sstar_sata_hardware_init1 done !!!!!!!!!\n"); ++ return 0; ++} ++ ++static struct scsi_host_template sstar_sata_sht1 = ++{ ++#if defined(USE_NCQ) ++ ATA_NCQ_SHT("sstar_sata"), ++#else ++ ATA_BASE_SHT("sstar_sata"), ++#endif ++ .can_queue = SATA_SSTAR_QUEUE_DEPTH, ++ .sg_tablesize = SATA_KA9_USED_PRD, ++ .dma_boundary = ATA_DMA_BOUNDARY, ++}; ++ ++static struct ata_port_operations sstar_sata_ops1 = ++{ ++ .inherits = &sata_pmp_port_ops, ++ ++ .qc_defer = ata_std_qc_defer, ++ .qc_prep = sata_sstar_qc_prep1, ++ .qc_issue = sata_sstar_qc_issue1, ++ .qc_fill_rtf = sata_sstar_qc_fill_rtf1, ++ ++ .scr_read = sata_sstar_scr_read1, ++ .scr_write = sata_sstar_scr_write1, ++ ++ .freeze = sata_sstar_freeze1, ++ .thaw = sata_sstar_thaw1, ++ ++ .softreset = sata_sstar_softreset1, ++ .hardreset = sata_sstar_hardreset1, ++ ++ .pmp_softreset = sata_sstar_softreset1, ++ .error_handler = sata_sstar_error_handler1, ++ .post_internal_cmd = sata_sstar_post_internal_cmd1, ++ ++ .port_start = sata_sstar_port_start1, ++ .port_stop = sata_sstar_port_stop1, ++ ++}; ++ ++static const struct ata_port_info sstar_sata_port_info1[] = ++{ ++ { ++ .flags = SATA_SSTAR_HOST_FLAGS, ++ .pio_mask = ATA_PIO6, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &sstar_sata_ops1, ++ }, ++}; ++ ++int __ss_sata_get_irq_number_host1(void) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int irq = 0; ++ ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA1_DTS_NAME); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ printk("[SATA] Virtual IRQ: %d\n", irq); ++ return irq; ++} ++ ++static int sstar_sata_probe1(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ata_port_info pi = sstar_sata_port_info1[0]; ++ const struct ata_port_info *ppi[] = { &pi, NULL }; ++ //struct ata_port *ap; ++ //struct sata_sstar_host_priv *hpriv; ++ //struct sata_sstar_host_priv *ss_hpriv; ++ struct ahci_host_priv *hpriv; ++ struct ata_host *host; ++ int irq = 0; ++ int ret = 0; ++ ++#if 0 // defined(CONFIG_OF) ++ struct device_node *np = dev->of_node; ++ int hba_base; ++ int port_base; ++ int misc_base; ++#else ++ struct resource *port_mem; ++ struct resource *misc_mem; ++ struct resource *hba_mem; ++#endif ++ ++ //sata_info("sstar SATA Host Controller Probing...\n"); ++ sata_info("SATA %d probing...\n", pdev->id); ++ ++#if 0 // defined(CONFIG_OF) ++ ret = of_property_read_u32(np, "sstar,hba-base", &hba_base); ++ if (ret) ++ { ++ printk("[%s][Error] SATA Get HBA Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ printk("dtb hba_base = %x\n", hba_base); ++ ++ ret = of_property_read_u32(np, "sstar,port-base", &port_base); ++ if (ret) ++ { ++ printk("[%s][Error] SATA Get Port Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ printk("dtb port_base= %x\n", port_base); ++ ++ ret = of_property_read_u32(np, "sstar,misc-base", &misc_base); ++ if (ret) ++ { ++ printk("[%s][Error] SATA Get MISC Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ printk("dtb misc_base= %x\n", misc_base); ++ ++ ret = of_property_read_u32(np, "interrupts", &irq); ++ if ((ret) && (irq <= 0)) ++ { ++ printk("[%s][Error] SATA Get IRQ Fail\n", __func__); ++ return -EINVAL; ++ } ++#else ++ hba_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ port_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ misc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ ++ sata_debug("HBA = 0x%08x, PORT = 0x%08x, MISC = 0x%08x\n", hba_mem->start, port_mem->start, misc_mem->start); ++ if (!hba_mem) ++ { ++ sata_error("[%s]SATA Get HBA Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ if (!port_mem) ++ { ++ sata_error("[%s]SATA Get Port Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ if (!misc_mem) ++ { ++ sata_error("[%s]SATA Get MISC Resource Fail\n", __func__); ++ return -EINVAL; ++ } ++ ++#if 0 ++ irq = platform_get_irq(pdev, 0); ++#else ++ irq = __ss_sata_get_irq_number_host1(); ++#endif ++ if (irq <= 0) ++ { ++ sata_error("[%s]SATA Get IRQ Fail\n", __func__); ++ return -EINVAL; ++ } ++#endif ++ ++ // Allocate Host Private Data ++ hpriv = devm_kzalloc(dev, sizeof(struct ahci_host_priv), GFP_KERNEL); ++ if (!hpriv) ++ { ++ sata_error("[%s] SATA Allocate Host Private Data Fail\n", __func__); ++ return -ENOMEM; ++ } ++ ss_hpriv1 = devm_kzalloc(dev, sizeof(struct sata_sstar_host_priv), GFP_KERNEL); ++ if (!ss_hpriv1) ++ { ++ sata_error("[%s]SATA Allocate SS Host Private Data Fail\n", __func__); ++ return -ENOMEM; ++ } ++ ++ // printk("SSTAR_RIU_BASE = 0x%llx..\n", SSTAR_RIU_BASE); // sstar_pm_base ++ // FIXME: need a way to set DMA mask in DTB, otherwise we will get dma allocation fail. ++#if 0 //defined(CONFIG_OF) ++ printk("CONFIG_OF\n"); ++ printk("SSTAR_RIU_BASE = 0x%llx..\n", SSTAR_RIU_BASE); // sstar_pm_base ++ hpriv->hba_base = (SSTAR_RIU_BASE + (hba_base << 1)); // (mstar_pm_base + (hba_base << 1)); ++ hpriv->port_base = (SSTAR_RIU_BASE + (port_base << 1)); // (mstar_pm_base + (port_base << 1)); ++ hpriv->misc_base = (SSTAR_RIU_BASE + (misc_base << 1)); // (mstar_pm_base + (misc_base << 1)); ++#else ++ ss_hpriv1->hba_base = hba_mem->start; ++ ss_hpriv1->port_base = port_mem->start; ++ ss_hpriv1->misc_base = misc_mem->start; ++#endif ++ ++ sata_debug("IRQ = %d\n", irq); ++ ++#if defined(USE_NCQ) ++ if(ppi[0]->flags & ATA_FLAG_NCQ) ++ sata_info("== NCQ enable ==\n"); ++#endif ++#ifdef CONFIG_SATA_PMP ++ if(ppi[0]->flags & ATA_FLAG_PMP) ++ sata_info("== PMP support ==\n"); ++#endif ++ ++ // Initial SATA Hardware ++ if (sstar_sata_hardware_init1(hba_mem->start, port_mem->start, misc_mem->start)) ++ { ++ sata_error("[%s]SATA Hardware Initial Failed\n", __func__); ++ return -EINVAL; ++ } ++ ++ host = ata_host_alloc_pinfo(dev, ppi, SATA_PORT_NUM); ++ if (!host) ++ { ++ ret = -ENOMEM; ++ sata_error("[%s]SATA Allocate ATA Host Fail\n", __func__); ++ goto out_devm_kzalloc_hpriv; ++ } ++ ++ hpriv->flags |= (unsigned long)pi.private_data; ++ hpriv->mmio = (void __iomem *) hba_mem->start; ++ hpriv->irq = irq; ++ ++//#ifdef CONFIG_ARCH_INFINITY2 ++#if 0 ++ ahci_save_initial_config(dev, hpriv, 0, 0); ++#else ++ ahci_save_initial_config(dev, hpriv); ++#endif ++ ++ /* DH test */ ++ if (hpriv->cap & HOST_CAP_NCQ) ++ pi.flags |= ATA_FLAG_NCQ; ++ // if (!ncq_en) ++ // pi.flags &= ~ATA_FLAG_NCQ; ++ if (hpriv->cap & HOST_CAP_PMP) ++ pi.flags |= ATA_FLAG_PMP; ++ ++ host->private_data = hpriv; ++ host->ports[0]->private_data = ss_hpriv1; ++ ++ //sata_info("host->ports[0] addr = [0x%x]\n", (u32)host->ports[0]); ++ ++ //return ata_host_activate(host, irq, sata_sstar_interrupt, IRQF_SHARED, &sstar_sata_sht); ++ //return ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED, &sstar_sata_sht); ++#ifdef CONFIG_ARCH_INFINITY2 ++ return ata_host_activate(host, irq, sstar_ahci_single_level_irq_intr1, IRQF_SHARED, &sstar_sata_sht1); ++#else ++ return ahci_host_activate(host, &sstar_sata_sht); ++#endif ++ ++out_devm_kzalloc_hpriv: ++ devm_kfree(dev, hpriv); ++ devm_kfree(dev, ss_hpriv1); ++ ++ return ret; ++} ++ ++static int sstar_sata_remove1(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *host_priv = host->private_data; ++ //struct sata_sstar_host_priv *ss_hpriv = host->ports[0]->ss_private_data; ++ ++ ata_host_detach(host); ++ ++ devm_kfree(dev, host_priv); ++ devm_kfree(dev, ss_hpriv1); ++ ++ sata_info("[%s]\n", __func__); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int sstar_sata_suspend1(struct platform_device *pdev, pm_message_t state) ++{ ++ //struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ ++ sata_info("[%s]\n", __func__); ++ //return ata_host_suspend(host, state); ++ return 0; ++} ++ ++static int sstar_sata_resume1(struct platform_device *pdev) ++{ ++ struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ //struct sata_sstar_host_priv *hpriv = host->private_data; ++ struct resource *port_mem; ++ struct resource *misc_mem; ++ struct resource *hba_mem; ++ sata_info("[%s]\n", __func__); ++ ++ hba_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ port_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ misc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ ++ if (sstar_sata_hardware_init1(hba_mem->start, port_mem->start, misc_mem->start)/*mstar_sata_hardware_init1()*/) ++ { ++ sata_error("[%s][Error] SATA Hardware Initial Failed, SATA resume failed!\n", __func__); ++ return -EINVAL; ++ } ++ //sata_sstar_port_start1(struct ata_port *ap) ++ sata_sstar_port_start1(host->ports[0]); ++ ++ //ata_host_resume(host); ++ sata_info("[%s] done\n", __func__); ++ return 0; ++} ++#endif ++ ++static void sstar_sata_drv_platfrom_release1(struct device *device) ++{ ++ phys_addr_t port_base = SATA_GHC_1_P0_ADDRESS_START; ++ phys_addr_t misc_base = SATA_MISC_1_ADDRESS_START; ++ ++ sata_info("[%s]\n", __func__); ++ MHal_SATA_Clock_Config(misc_base, port_base, FALSE); ++} ++ ++#if defined(CONFIG_ARM64) ++#if 0 // defined(CONFIG_OF) ++static const struct of_device_id sstar_satahost_dt_match[] = ++{ ++ { .compatible = "sstar-sata", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sstar_satahost_dt_match); ++#endif ++#endif ++ ++static struct platform_driver sstar_sata_driver1 = ++{ ++ .probe = sstar_sata_probe1, ++ .remove = sstar_sata_remove1, ++#ifdef CONFIG_PM ++ .suspend = sstar_sata_suspend1, ++ .resume = sstar_sata_resume1, ++#endif ++ .driver = { ++ .name = "sstar-sata1", ++#if defined(CONFIG_ARM64) ++#if 0 // defined(CONFIG_OF) ++ .of_match_table = sstar_satahost_dt_match, ++#endif ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++#if defined(CONFIG_ARM64) ++ static u64 sata_dmamask = DMA_BIT_MASK(64); ++#else ++ static u64 sata_dmamask = DMA_BIT_MASK(32); ++#endif ++ ++static struct resource satahost_resources1[] = ++{ ++ [0] = { ++ .start = SATA_GHC_1_ADDRESS_START, ++ .end = SATA_GHC_1_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SATA_GHC_1_P0_ADDRESS_START, ++ .end = SATA_GHC_1_P0_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = SATA_MISC_1_ADDRESS_START, ++ .end = SATA_MISC_1_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++#if defined(CONFIG_ARCH_INFINITY2) ++ [3] = { ++ .start = INT_IRQ_16_SATA_P1_INTRQ, //16 + 32, //E_IRQ_SATA_INT, ++ .end = INT_IRQ_16_SATA_P1_INTRQ, //16 + 32, //E_IRQ_SATA_INT, ++ .flags = IORESOURCE_IRQ, ++ }, ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ [3] = { ++ .start = INT_IRQ_SATA, ++ .end = INT_IRQ_SATA, ++ .flags = IORESOURCE_IRQ, ++ }, ++#endif ++}; ++ ++struct platform_device sstar_satahost_device1 = ++{ ++ .name = "sstar-sata1", ++ .id = 1, ++ .dev = { ++ .release = sstar_sata_drv_platfrom_release1, ++ .dma_mask = &sata_dmamask, ++#if defined(CONFIG_ARM64) ++ .coherent_dma_mask = DMA_BIT_MASK(64), ++#else ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++#endif ++ }, ++ .num_resources = ARRAY_SIZE(satahost_resources1), ++ .resource = satahost_resources1, ++}; ++ ++static int __init sstar_sata_drv_init1(void) ++{ ++ int ret = 0; ++ ++ //sata_info("===== [SATA 1] register platform driver START=====\n"); ++ ret = platform_driver_register(&sstar_sata_driver1); ++ if (ret < 0) ++ { ++ sata_error("Unable to register SATA 1 platform driver, %d\n", ret); ++ return ret; ++ } ++ ++ ret = platform_device_register(&sstar_satahost_device1); ++ if (ret < 0) ++ { ++ sata_error("Unable to register SATA 1 platform device, %d\n", ret); ++ platform_driver_unregister(&sstar_sata_driver1); ++ return -ret; ++ } ++ sata_info("===== [SATA 1] register platform device END =====\n"); ++ ++ return ret; ++} ++ ++static void __exit sstar_sata_drv_exit1(void) ++{ ++ sata_info("[%s]\n", __func__); ++ ++ platform_device_unregister(&sstar_satahost_device1); ++ platform_driver_unregister(&sstar_sata_driver1); ++} ++ ++MODULE_AUTHOR("sstar Semiconductor"); ++MODULE_DESCRIPTION("sstar 3.0Gbps SATA controller low level driver for sata port 1"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION("1.00"); ++ ++module_init(sstar_sata_drv_init1); ++module_exit(sstar_sata_drv_exit1); +diff --git a/drivers/sstar/sata_host/mdrv_sata_host_ahci.c b/drivers/sstar/sata_host/mdrv_sata_host_ahci.c +new file mode 100755 +index 000000000000..98e2b1dabc76 +--- /dev/null ++++ b/drivers/sstar/sata_host/mdrv_sata_host_ahci.c +@@ -0,0 +1,514 @@ ++/* ++* mdrv_sata_host_ahci.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ahci.h" ++ ++//#include "mhal_sata_host_ahci.h" ++ ++#if defined( CONFIG_ARCH_INFINITY2) ++#include "mhal_sata_host_ahci.c" ++ ++#elif defined( CONFIG_ARCH_INFINITY2M) ++#include "mhal_sata_host.h" ++#include "mdrv_sata_host_ahci.h" ++#endif ++ ++ ++ ++ ++#include "mhal_sata_host_ahci.h" ++ ++static int n_ports = 1;//config sata ports //TBD ++static int phy_mode = 2;//config sata mode //TBD ++ ++#define SW_OOB_MODE 0 ++#if 0 ++ #ifdef MODULE//TBD ++ module_param(phy_config, uint, 0600); ++ MODULE_PARM_DESC(phy_config, "sata phy config");//(default:0x0e180000) ++ module_param(n_ports, uint, 0600); ++ MODULE_PARM_DESC(n_ports, "sata port number");//(default:2) ++ module_param(mode_3g, uint, 0600); ++ MODULE_PARM_DESC(phy_mode, "sata phy mode ");//(0:1.5G;1:3G(default);2:6G) ++ #endif ++#endif ++module_param(phy_mode, int, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(phy_mode, "\nSATA Max Speed:\n" ++ " [0] 1.5 Gbps\n" ++ " [1] 3.0 Gbps(default)\n" ++ " [2] 6.0 Gbps"); ++ ++extern int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); ++extern int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); ++extern unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg); ++ ++#define SSTAR_SATA_DTS_NAME "sstar,sata" ++#define SSTAR_SATA1_DTS_NAME "sstar,sata1" ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ //extern u32 ahci_reg_read(phys_addr_t reg_addr); ++ //extern void ahci_reg_write(u32 data, phys_addr_t p_reg_addr);; ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++ ++#endif ++ ++static u32 sstar_sata_wait_reg(phys_addr_t reg_addr, u32 mask, u32 val, unsigned long interval, unsigned long timeout) ++{ ++ u32 temp; ++ unsigned long timeout_vale = 0; ++ ++ temp = readl((void *)reg_addr); ++ ++ while((temp & mask) == val) ++ { ++ msleep(interval); ++ timeout_vale += interval; ++ if (timeout_vale > timeout) ++ break; ++ temp = readl((void *)reg_addr); ++ } ++ return temp; ++} ++ ++#if (SW_OOB_MODE == 1) ++static void sstar_sata_sw_oob_mode1(void) ++{ ++ u16 u16Temp, u16IrqRetry, u16Irq2Retry=2; ++ ++ // Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE1_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 5; u16IrqRetry++) ++ { ++ // Check if IRQ1 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_LOCK_FLAG) ++ break; ++ ++ udelay(2); ++ } ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq2Retry--; ++ // Check if IRQ2 no ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_UNLOCK_FLAG) || u16Irq2Retry == 0) ++ goto SW_OOB_MODE1_STAGE0; ++ ++ udelay(2); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 2; u16IrqRetry++) ++ { ++ // Check if IRQ3 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) ++ break; ++ ++ udelay(1); ++ } ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#elif (SW_OOB_MODE == 2) ++static void sstar_sata_sw_oob_mode2(void) ++{ ++ u16 u16Temp, u16Irq3Retry=2; ++ ++ //Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE2_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq3Retry--; ++ // Check if IRQ3 is yes ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) || u16Irq3Retry == 0) ++ break; ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#endif ++ ++#ifdef CONFIG_ARCH_INFINITY2M ++int __ss_sata_get_phy_mode(void) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int phy_mode = 2; ++ ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ ++ of_property_read_u32(dev_node, "phy_mode", &phy_mode); ++ ++ printk("[SATA] phy_mode =%d\n", phy_mode); ++ return phy_mode; ++} ++#endif ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++int ss_sata_init(struct device *dev, void __iomem *mmio, int id) ++#elif defined(CONFIG_ARCH_INFINITY2M) ++int ss_sata_init(struct device *dev, void __iomem *mmio) ++#endif ++{ ++ u32 i; ++ u32 u32Temp = 0; ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ phys_addr_t hba_base = (phys_addr_t)mmio; //102B00<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x200); //102C00<<1 ++ phys_addr_t misc_base = (phys_addr_t)(mmio + 0x400); //102D00<<1 ++ int port_num; ++ ++ port_num = n_ports; ++ ++ //printk("sstar sata HW settings start!!!\n"); ++ ss_sata_misc_init(mmio, phy_mode, port_num); ++ ss_sata_phy_init(mmio, phy_mode, port_num); ++ ++ // AHCI init ++ writew(HOST_RESET, (volatile void *)mmio + (HOST_CTL)); ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ phys_addr_t hba_base = (phys_addr_t)mmio; //1A2800<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x100); //1A2880<<1 ++ phys_addr_t misc_base = (phys_addr_t)(mmio - 0xA0600); //152500<<1 ++ int port_num; ++ ++ port_num = n_ports; ++ ++ //printk("sstar sata HW settings start!!!\n"); ++ ss_sata_misc_init(mmio, port_num); ++ ss_sata_phy_init(mmio, phy_mode,port_num); ++ ++ // AHCI init ++ writew(HOST_RESET, (volatile void *)hba_base + (HOST_CTL)); ++#endif ++ ++ #if 0 ++ writel(0x00000000, (volatile void *)hba_base + (HOST_CAP)); ++ writel(0x00000001, (volatile void *)hba_base + (HOST_PORTS_IMPL)); ++ writel(0x00000001, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x00000000, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x02100000, (volatile void *)port_base + (PORT_LST_ADDR)); ++ writel(0x02000000, (volatile void *)port_base + (PORT_FIS_ADDR)); ++ writel(0x00000016, (volatile void *)port_base + (PORT_CMD)); ++ #endif ++ #if (SW_OOB_MODE == 1) ++ sstar_sata_sw_oob_mode1(); ++ #elif (SW_OOB_MODE == 2) ++ sstar_sata_sw_oob_mode2(); ++ #else ++ u32Temp = sstar_sata_wait_reg(HOST_CTL + (phys_addr_t)mmio, HOST_RESET, HOST_RESET, 1, 500); ++ if (u32Temp & HOST_RESET) ++ { ++ printk("SATA host reset fail!\n"); ++ return -1; ++ } ++ #endif ++ ++ // Turn on AHCI_EN ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ { ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ return 0; ++ } ++ ++ // Try AHCI_EN Trurn on for a few time ++ for (i = 0; i < 5; i++) ++ { ++ u32Temp |= HOST_AHCI_EN; ++ writel(u32Temp, (void *)HOST_CTL + (phys_addr_t)hba_base); ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ break; ++ msleep(10); ++ } ++ ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ ++ printk("sstar sata HW settings done!!!\n"); ++ return 0; ++} ++//EXPORT_SYMBOL(ss_sata_init); ++ ++void ss_sata_exit(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ phys_addr_t port_base = (phys_addr_t)(hpriv->mmio + 0x200); ++ ++ pr_info("[%s] port_base = 0x%x\n", __func__, port_base); ++ MHal_SATA_Clock_Config(port_base, FALSE); ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ phys_addr_t port_base = (phys_addr_t)(hpriv->mmio + 0x100); //(0x1A2880 << 1) ++ phys_addr_t misc_base = (phys_addr_t)(hpriv->mmio - 0xA0600);//(0x152500 << 1) ++ ++ pr_info("[%s] port_base = 0x%x\n", __func__, port_base); ++ MHal_SATA_Clock_Config(misc_base, port_base, FALSE); ++#endif ++} ++//EXPORT_SYMBOL(ss_sata_exit); ++ ++ ++static int ss_sata_suspend(struct device *dev) ++{ ++ pr_info("[%s]\n", __func__); ++ ss_sata_exit(dev); ++ ++ return 0; ++} ++ ++static int ss_sata_resume(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++ pr_info("[%s]\n", __func__); ++ ++#if defined(CONFIG_ARCH_INFINITY2) ++ ss_sata_init(dev, hpriv->mmio, 0); ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ ss_sata_init(dev, hpriv->mmio); ++#endif ++ ++ return 0; ++} ++ ++struct ahci_platform_data ss_ahci_platdata = ++{ ++ .init = ss_sata_init, ++ .exit = ss_sata_exit, ++ .suspend = ss_sata_suspend, ++ .resume = ss_sata_resume, ++}; ++ ++static struct resource ss_sata_ahci_resources[] = ++{ ++ [0] = { ++ .start = SATA_GHC_0_ADDRESS_START, // i2 (0xFD000000 + 0x102B00 << 1), //SATA_GHC_0_ADDRESS_START/*-0xFD000000*/, ++ .end = SATA_GHC_0_ADDRESS_END, // i2 0xFD000000 + 0x102BFE << 1, /*-0xFD000000*/ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SATA_GHC_0_P0_ADDRESS_START, // i2 0xFD000000 + 0x102C00 << 1, //SATA_GHC_0_ADDRESS_START/*-0xFD000000*/, ++ .end = SATA_GHC_0_P0_ADDRESS_END, // i2 0xFD000000 + 0x102CFE << 1, /*-0xFD000000*/ ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = SATA_MISC_0_ADDRESS_START, // i2 0xFD000000 + 0x102D00 << 1, //SATA_GHC_0_ADDRESS_START/*-0xFD000000*/, ++ .end = SATA_MISC_0_ADDRESS_END, // i2 0xFD000000 + 0x102DFE << 1, /*-0xFD000000*/ ++ .flags = IORESOURCE_MEM, ++ }, ++#if defined(CONFIG_ARCH_INFINITY2) ++ [3] = { ++ .start = INT_IRQ_15_SATA_INTRQ, //15 + 32, //E_IRQ_SATA_INT, ++ .end = INT_IRQ_15_SATA_INTRQ, //15 + 32, //E_IRQ_SATA_INT, ++ .flags = IORESOURCE_IRQ, ++ }, ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ [3] = { ++ .start = INT_IRQ_SATA, ++ .end = INT_IRQ_SATA, ++ .flags = IORESOURCE_IRQ, ++ }, ++#endif ++}; ++ ++#if defined(CONFIG_ARM64) ++ static u64 ahci_dmamask = ~(u64)0; ++#else ++ static u64 ahci_dmamask = ~(u32)0; ++#endif ++ ++static void ss_satav100_ahci_platdev_release(struct device *dev) ++{ ++#if defined(CONFIG_ARCH_INFINITY2) ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ phys_addr_t port_base = (phys_addr_t)(hpriv->mmio + 0x200); //SATA_GHC_0_P0_ADDRESS_START ++ ++ pr_info("[%s] port_base = 0x%x\n", __func__, port_base); ++ MHal_SATA_Clock_Config(port_base, FALSE); ++ ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ phys_addr_t port_base = (phys_addr_t)(hpriv->mmio + 0x100); //SATA_GHC_0_P0_ADDRESS_START ++ phys_addr_t misc_base = (phys_addr_t)(hpriv->mmio - 0xA0600);//(0x152500 << 1) ++ ++ pr_info("[%s] port_base = 0x%x\n", __func__, port_base); ++ MHal_SATA_Clock_Config(misc_base, port_base, FALSE); ++ ++#endif ++ ++ return; ++} ++ ++static struct platform_device ss_sata_ahci_device = ++{ ++ .name = "ahci", ++ .id = 0, ++ .dev = { ++ .platform_data = &ss_ahci_platdata, ++ .dma_mask = &ahci_dmamask, ++#if defined(CONFIG_ARM64) ++ .coherent_dma_mask = 0xffffffffffffffff, ++#else ++ .coherent_dma_mask = 0xffffffff, ++#endif ++ .release = ss_satav100_ahci_platdev_release, ++ }, ++ .num_resources = ARRAY_SIZE(ss_sata_ahci_resources), ++ .resource = ss_sata_ahci_resources, ++}; ++ ++ ++int __ss_sata_get_irq_number(int id) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int irq = 0; ++ ++ ++ if(id == 0) ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ else if(id == 1) ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA1_DTS_NAME); ++ else ++ printk("[SATA] %s get irq fail \n", __func__); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ printk("[SATA] Virtual IRQ: %d\n", irq); ++ return irq; ++} ++ ++static int __init ss_ahci_init(void) ++{ ++ int ret = 0; ++ ++ pr_info("[%s]\n", __func__); ++ ++ ++ // Get SATA irq number from dts ++ ss_sata_ahci_device.resource[3].start = __ss_sata_get_irq_number(0); ++ ss_sata_ahci_device.resource[3].end = ss_sata_ahci_device.resource[3].start; ++ ++ ret = platform_device_register(&ss_sata_ahci_device); ++ if (ret) ++ { ++ pr_err("[%s %d] sstar sata platform device register is failed!!!\n", ++ __func__, __LINE__); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static void __exit ss_ahci_exit(void) ++{ ++ pr_info("[%s]\n", __func__); ++ ++ platform_device_unregister(&ss_sata_ahci_device); ++ return; ++} ++module_init(ss_ahci_init); ++module_exit(ss_ahci_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("sstar Semiconductor"); ++MODULE_DESCRIPTION("sstar SATA controller low level driver"); ++MODULE_VERSION("1.00"); +diff --git a/drivers/sstar/sata_host/mdrv_sata_host_ahci.h b/drivers/sstar/sata_host/mdrv_sata_host_ahci.h +new file mode 100755 +index 000000000000..bbfa4de86be8 +--- /dev/null ++++ b/drivers/sstar/sata_host/mdrv_sata_host_ahci.h +@@ -0,0 +1,32 @@ ++/* ++* mdrv_sata_host_ahci.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MDRV_SATA_HOST_AHCI_H_ ++#define _MDRV_SATA_HOST_AHCI_H_ ++ ++struct sstar_platform_data { ++ int (*init)(struct device *dev, void __iomem *addr , int id); ++ void (*exit)(struct device *dev); ++ int (*suspend)(struct device *dev); ++ int (*resume)(struct device *dev); ++ const struct ata_port_info *ata_port_info; ++ unsigned int force_port_map; ++ unsigned int mask_port_map; ++}; ++ ++#endif +diff --git a/drivers/sstar/sata_host/mdrv_sata_host_ahci1.c b/drivers/sstar/sata_host/mdrv_sata_host_ahci1.c +new file mode 100755 +index 000000000000..80aeb3ff154e +--- /dev/null ++++ b/drivers/sstar/sata_host/mdrv_sata_host_ahci1.c +@@ -0,0 +1,454 @@ ++/* ++* mdrv_sata_host_ahci1.c - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ahci.h" ++ ++#include "mhal_sata_host_ahci.h" ++#include "mhal_sata_host_ahci.c" ++ ++static int n_ports = 1;//config sata ports //TBD ++static int phy_mode = 1;//config sata mode //TBD ++ ++#define SW_OOB_MODE 0 ++#if 0 ++ #ifdef MODULE//TBD ++ module_param(phy_config, uint, 0600); ++ MODULE_PARM_DESC(phy_config, "sata phy config");//(default:0x0e180000) ++ module_param(n_ports, uint, 0600); ++ MODULE_PARM_DESC(n_ports, "sata port number");//(default:2) ++ module_param(mode_3g, uint, 0600); ++ MODULE_PARM_DESC(phy_mode, "sata phy mode ");//(0:1.5G;1:3G(default);2:6G) ++ #endif ++#endif ++module_param(phy_mode, int, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(phy_mode, "\nSATA Max Speed:\n" ++ " [0] 1.5 Gbps\n" ++ " [1] 3.0 Gbps(default)\n" ++ " [2] 6.0 Gbps"); ++ ++extern int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); ++extern int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); ++extern unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg); ++ ++#define SSTAR_SATA_DTS_NAME "sstar,sata" ++#define SSTAR_SATA1_DTS_NAME "sstar,sata1" ++ ++#ifdef CONFIG_ARCH_INFINITY2 ++ ++ #undef writel ++ #undef readl ++ ++ extern u32 ahci_reg_read(void __iomem * p_reg_addr); ++ extern void ahci_reg_write(u32 data, void __iomem * p_reg_addr); ++ //extern u32 ahci_reg_read(phys_addr_t reg_addr); ++ //extern void ahci_reg_write(u32 data, phys_addr_t p_reg_addr);; ++ ++ #define writel ahci_reg_write ++ #define readl ahci_reg_read ++ ++#endif ++ ++static u32 sstar_sata_wait_reg1(phys_addr_t reg_addr, u32 mask, u32 val, unsigned long interval, unsigned long timeout) ++ ++{ ++ u32 temp; ++ unsigned long timeout_vale = 0; ++ ++ temp = readl((void *)reg_addr); ++ ++ while((temp & mask) == val) ++ { ++ msleep(interval); ++ timeout_vale += interval; ++ if (timeout_vale > timeout) ++ break; ++ temp = readl((void *)reg_addr); ++ } ++ return temp; ++} ++ ++#if (SW_OOB_MODE == 1) ++static void sstar_sata_sw_oob_mode1(void) ++{ ++ u16 u16Temp, u16IrqRetry, u16Irq2Retry=2; ++ ++ // Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE1_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 5; u16IrqRetry++) ++ { ++ // Check if IRQ1 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_LOCK_FLAG) ++ break; ++ ++ udelay(2); ++ } ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq2Retry--; ++ // Check if IRQ2 no ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RXPLL_FREQ_UNLOCK_FLAG) || u16Irq2Retry == 0) ++ goto SW_OOB_MODE1_STAGE0; ++ ++ udelay(2); ++ ++ for (u16IrqRetry = 0; u16IrqRetry < 2; u16IrqRetry++) ++ { ++ // Check if IRQ3 is yes ++ if (readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) ++ break; ++ ++ udelay(1); ++ } ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#elif (SW_OOB_MODE == 2) ++static void sstar_sata_sw_oob_mode2(void) ++{ ++ u16 u16Temp, u16Irq3Retry=2; ++ ++ //Enable all SATA interrupt ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++ ++SW_OOB_MODE2_STAGE0: ++ // Clear all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ writew(0x0000, (volatile void *)SSTAR_RIU_BASE + (0x15273C << 1)); ++ ++ // Force reg_sata_rxpll_pd_cdr = 1 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp |= 0x400; // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(22); ++ ++ // Force reg_sata_rxpll_pd_cdr = 0 ++ u16Temp = readw((volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ u16Temp &= ~(0x400); // [10]: reg_sata_rxpll_pd_cdr ++ writew(u16Temp, (volatile void *)SSTAR_RIU_BASE + (0x152762 << 1)); ++ ++ udelay(3); ++ ++ u16Irq3Retry--; ++ // Check if IRQ3 is yes ++ if ((readw((volatile void *)SSTAR_RIU_BASE + (0x15273E << 1)) & INT_SATA_PHY_RX_DATA_VLD_PRE_0) || u16Irq3Retry == 0) ++ break; ++ ++ // Data Ready ++ ++ // Disable all SATA interrupt ++ writew(0xFFFF, (volatile void *)SSTAR_RIU_BASE + (0x15273A << 1)); ++} ++#endif ++ ++#ifdef CONFIG_ARCH_INFINITY2M ++int __ss_sata_get_phy_mode(void) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int phy_mode = 2; ++ ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ ++ of_property_read_u32(dev_node, "phy_mode", &phy_mode); ++ ++ printk("[SATA] phy_mode =%d\n", phy_mode); ++ return phy_mode; ++} ++#endif ++ ++int ss_sata_init1(struct device *dev, void __iomem *mmio, int id) ++{ ++ u32 i; ++ u32 u32Temp = 0; ++ ++ phys_addr_t hba_base = (phys_addr_t)mmio; //102B00<<1 ++ phys_addr_t port_base = (phys_addr_t)(mmio + 0x200); //102C00<<1 ++ phys_addr_t misc_base = (phys_addr_t)(mmio + 0x400); //102D00<<1 ++ int port_num; ++ ++ port_num = n_ports; ++ ++ if(port_base == SATA_GHC_1_P0_ADDRESS_START) ++ { ++ phy_mode = 2; // 0: GEN1, 1: GEN2(default), 2: GEN3 ++ } ++ ++ //printk("sstar sata HW settings start!!!\n"); ++ ss_sata_misc_init(mmio, phy_mode, port_num); ++ ss_sata_phy_init(mmio, phy_mode, port_num); ++ ++ // AHCI init ++ writew(HOST_RESET, (volatile void *)mmio + (HOST_CTL)); ++ #if 0 ++ writel(0x00000000, (volatile void *)hba_base + (HOST_CAP)); ++ writel(0x00000001, (volatile void *)hba_base + (HOST_PORTS_IMPL)); ++ writel(0x00000001, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x00000000, (volatile void *)port_base + (PORT_SCR_CTL)); ++ writel(0x02100000, (volatile void *)port_base + (PORT_LST_ADDR)); ++ writel(0x02000000, (volatile void *)port_base + (PORT_FIS_ADDR)); ++ writel(0x00000016, (volatile void *)port_base + (PORT_CMD)); ++ #endif ++ #if (SW_OOB_MODE == 1) ++ sstar_sata_sw_oob_mode1(); ++ #elif (SW_OOB_MODE == 2) ++ sstar_sata_sw_oob_mode2(); ++ #else ++ ++ u32Temp = sstar_sata_wait_reg1(HOST_CTL + (phys_addr_t)mmio, HOST_RESET, HOST_RESET, 1, 500); ++ if (u32Temp & HOST_RESET) ++ { ++ printk("SATA host reset fail!\n"); ++ return -1; ++ } ++ #endif ++ ++ ++ // Turn on AHCI_EN ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ { ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ return 0; ++ } ++ ++ // Try AHCI_EN Trurn on for a few time ++ for (i = 0; i < 5; i++) ++ { ++ u32Temp |= HOST_AHCI_EN; ++ writel(u32Temp, (void *)HOST_CTL + (phys_addr_t)hba_base); ++ u32Temp = readl((void *)HOST_CTL + (phys_addr_t)hba_base); ++ if (u32Temp & HOST_AHCI_EN) ++ break; ++ msleep(10); ++ } ++ ++ MHal_SATA_Setup_Port_Implement((phys_addr_t)misc_base, (phys_addr_t)port_base, (phys_addr_t)hba_base); ++ ++ printk("sstar sata HW settings done!!!\n"); ++ return 0; ++} ++//EXPORT_SYMBOL(ss_sata_init1); ++ ++void ss_sata_exit1(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++ phys_addr_t port_base = (phys_addr_t)(hpriv->mmio + 0x200); ++ ++ pr_info("[%s] port_base = 0x%x\n", __func__, port_base); ++ MHal_SATA_Clock_Config(port_base, FALSE); ++} ++//EXPORT_SYMBOL(ss_sata_exit1); ++ ++ ++static int ss_sata_suspend1(struct device *dev) ++{ ++ pr_info("[%s]\n", __func__); ++ ss_sata_exit1(dev); ++ ++ return 0; ++} ++ ++static int ss_sata_resume1(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ ++ pr_info("[%s]\n", __func__); ++ ss_sata_init1(dev, hpriv->mmio,0); ++ ++ return 0; ++} ++ ++struct ahci_platform_data ss_ahci_platdata1 = ++{ ++ .init = ss_sata_init1, ++ .exit = ss_sata_exit1, ++ .suspend = ss_sata_suspend1, ++ .resume = ss_sata_resume1, ++}; ++ ++static struct resource ss_sata_ahci_resources1[] = ++{ ++ [0] = { ++ .start = SATA_GHC_1_ADDRESS_START, //(0xFD000000 + 0x102B00 << 1), //SATA_GHC_0_ADDRESS_START/*-0xFD000000*/, ++ .end = SATA_GHC_1_ADDRESS_END, //0xFD000000 + 0x102BFE << 1, /*-0xFD000000*/ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SATA_GHC_1_P0_ADDRESS_START, //0xFD000000 + 0x102C00 << 1, //SATA_GHC_0_ADDRESS_START/*-0xFD000000*/, ++ .end = SATA_GHC_1_P0_ADDRESS_END, //0xFD000000 + 0x102CFE << 1, /*-0xFD000000*/ ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = SATA_MISC_1_ADDRESS_START, //0xFD000000 + 0x102D00 << 1, //SATA_GHC_0_ADDRESS_START/*-0xFD000000*/, ++ .end = SATA_MISC_1_ADDRESS_END, //0xFD000000 + 0x102DFE << 1, /*-0xFD000000*/ ++ .flags = IORESOURCE_MEM, ++ }, ++ [3] = { ++ .start = INT_IRQ_16_SATA_P1_INTRQ, // 16 + 32, //E_IRQ_SATA_INT, ++ .end = INT_IRQ_16_SATA_P1_INTRQ, // 16 + 32, //E_IRQ_SATA_INT, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++#if defined(CONFIG_ARM64) ++ static u64 ahci_dmamask = ~(u64)0; ++#else ++ static u64 ahci_dmamask = ~(u32)0; ++#endif ++ ++static void sssatav100_ahci_platdev_release1(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ phys_addr_t port_base = (phys_addr_t)(hpriv->mmio + 0x200); //SATA_GHC_1_P0_ADDRESS_START ++ ++ pr_info("[%s] port_base = 0x%x\n", __func__, port_base); ++ MHal_SATA_Clock_Config(port_base, FALSE); ++ return; ++} ++ ++static struct platform_device ss_sata_ahci_device1 = ++{ ++ .name = "ahci", ++ .id = 1, ++ .dev = { ++ .platform_data = &ss_ahci_platdata1, ++ .dma_mask = &ahci_dmamask, ++#if defined(CONFIG_ARM64) ++ .coherent_dma_mask = 0xffffffffffffffff, ++#else ++ .coherent_dma_mask = 0xffffffff, ++#endif ++ .release = sssatav100_ahci_platdev_release1, ++ }, ++ .num_resources = ARRAY_SIZE(ss_sata_ahci_resources1), ++ .resource = ss_sata_ahci_resources1, ++}; ++ ++ ++int __ss_sata_get_irq_number1(int id) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ int irq = 0; ++ ++ ++ if(id == 0) ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA_DTS_NAME); ++ else if(id == 1) ++ dev_node = of_find_compatible_node(NULL, NULL, SSTAR_SATA1_DTS_NAME); ++ else ++ printk("[SATA] %s get irq fail \n", __func__); ++ ++ if (!dev_node) ++ return -ENODEV; ++ ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) ++ { ++ of_node_put(dev_node); ++ return -ENODEV; ++ } ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ printk("[SATA] Virtual IRQ: %d\n", irq); ++ return irq; ++} ++ ++static int __init ss_ahci_init1(void) ++{ ++ int ret = 0; ++ ++ pr_info("[%s]\n", __func__); ++ ++ // Get SATA irq number from dts ++ ss_sata_ahci_device1.resource[3].start = __ss_sata_get_irq_number1(1); ++ ss_sata_ahci_device1.resource[3].end = ss_sata_ahci_device1.resource[3].start; ++ ++ ret = platform_device_register(&ss_sata_ahci_device1); ++ if (ret) ++ { ++ pr_err("[%s %d] sstar sata platform device register is failed!!!\n", ++ __func__, __LINE__); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static void __exit ss_ahci_exit1(void) ++{ ++ pr_info("[%s]\n", __func__); ++ ++ platform_device_unregister(&ss_sata_ahci_device1); ++ return; ++} ++module_init(ss_ahci_init1); ++module_exit(ss_ahci_exit1); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("sstar Semiconductor"); ++MODULE_DESCRIPTION("sstar SATA controller low level driver"); ++MODULE_VERSION("1.00"); +diff --git a/drivers/sstar/sdmmc/Kconfig b/drivers/sstar/sdmmc/Kconfig +new file mode 100755 +index 000000000000..35af1e223fa7 +--- /dev/null ++++ b/drivers/sstar/sdmmc/Kconfig +@@ -0,0 +1,6 @@ ++config MS_SDMMC ++ tristate "SStar SD/MMC Card Interface Support" ++ depends on MMC ++ default n ++ ---help--- ++ Enable SD/MMC Driver Support for SStar Product +\ No newline at end of file +diff --git a/drivers/sstar/sdmmc/Makefile b/drivers/sstar/sdmmc/Makefile +new file mode 100755 +index 000000000000..9bc2e13954eb +--- /dev/null ++++ b/drivers/sstar/sdmmc/Makefile +@@ -0,0 +1,13 @@ ++obj-$(CONFIG_MS_SDMMC) += kdrv_sdmmc.o ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/sdmmc/inc ++EXTRA_CFLAGS += -Idrivers/sstar/sdmmc/inc/$(CONFIG_SSTAR_CHIP_NAME) ++ ++kdrv_sdmmc-y = src/hal_card_regs.o src/hal_card_timer.o ++kdrv_sdmmc-y += src/hal_card_intr_v5.o ++kdrv_sdmmc-y += src/hal_sdmmc_v5.o ++kdrv_sdmmc-y += src/$(subst ",,$(CONFIG_SSTAR_CHIP_NAME))/hal_card_platform.o ++ ++kdrv_sdmmc-y += ms_sdmmc_lnx.o +diff --git a/drivers/sstar/sdmmc/inc/hal_card_base.h b/drivers/sstar/sdmmc/inc/hal_card_base.h +new file mode 100755 +index 000000000000..0d0d8b9b2630 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_card_base.h +@@ -0,0 +1,269 @@ ++/* ++* hal_card_base.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_base.h ++ * @author jeremy.wang (2015/05/29) ++ * Desc: ++ * This header file is independent. ++ * We could put different hal_card_base.h in different build code folder but the same name. ++ * We want to distinguish between this and others settings but the same project. ++ * Specific define is freedom for each project, but we need to put it at inner code of project define. ++ * ++ * For Base Setting: ++ * (1) BASE Project/OS/CPU/FCIE/Ver.. Option Type Define ++ * (2) BASE TYPE Define ++ * (3) BASE OS/CPU define and Include Files for Different OS/CPU ++ * (4) BASE Debug System ++ * (5) BASE Project/FCIE/Ver.. Define ++ * ++ * P.S. D_XX for define and D_XX__ two under line("__") to distinguish define and its define option. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_BASE_H ++#define __HAL_CARD_BASE_H ++ ++//*********************************************************************************************************** ++// (1) BASE Project/OS/CPU/FCIE/ICVer.. Option Type Define ++//*********************************************************************************************************** ++ ++// OS Type Option ++//----------------------------------------------------------------------------------------------------------- ++#define D_OS__LINUX 1 ++#define D_OS__UBOOT 2 ++#define D_OS__WINCE 3 ++#define D_OS__EBOOT 4 ++#define D_OS__YBOX 5 ++#define D_OS__NONE 6 ++ ++// CPU Type Option ++//----------------------------------------------------------------------------------------------------------- ++#define D_CPU__ARM 1 ++#define D_CPU__MIPS 2 ++ ++// FCIE Type Major Version ++//----------------------------------------------------------------------------------------------------------- ++#define D_FCIE_M_VER__04 1 ++#define D_FCIE_M_VER__05 2 ++ ++// FCIE Type Revision Version ++//----------------------------------------------------------------------------------------------------------- ++#define D_FCIE_R_VER__00 0 ++#define D_FCIE_R_VER__01 1 ++#define D_FCIE_R_VER__02 2 ++#define D_FCIE_R_VER__03 3 ++#define D_FCIE_R_VER__04 4 ++#define D_FCIE_R_VER__05 5 ++ ++// BOARD Type Version ++//----------------------------------------------------------------------------------------------------------- ++#define D_BOARD_VER__00 0 ++#define D_BOARD_VER__01 1 ++#define D_BOARD_VER__02 2 ++#define D_BOARD_VER__03 3 ++#define D_BOARD_VER__04 4 ++#define D_BOARD_VER__05 5 ++ ++// IC Version Option ++//----------------------------------------------------------------------------------------------------------- ++#define D_ICVER__00 0 ++#define D_ICVER__01 1 ++#define D_ICVER__02 2 ++#define D_ICVER__03 3 ++#define D_ICVER__04 4 ++#define D_ICVER__05 5 ++#define D_ICVER__06 6 ++#define D_ICVER__07 7 ++#define D_ICVER__08 8 ++#define D_ICVER__09 9 ++ ++ ++//*********************************************************************************************************** ++// (2) BASE Type Define ++//*********************************************************************************************************** ++typedef unsigned char U8_T; ++typedef unsigned short U16_T; ++typedef unsigned int U32_T; ++typedef unsigned long long U64_T; ++typedef signed char S8_T; ++typedef signed short S16_T; ++typedef signed int S32_T; ++typedef signed long long S64_T; ++typedef unsigned char BOOL_T; ++ ++#define FALSE 0 ++#define TRUE 1 ++ ++#define BIT00_T 0x0001 ++#define BIT01_T 0x0002 ++#define BIT02_T 0x0004 ++#define BIT03_T 0x0008 ++#define BIT04_T 0x0010 ++#define BIT05_T 0x0020 ++#define BIT06_T 0x0040 ++#define BIT07_T 0x0080 ++#define BIT08_T 0x0100 ++#define BIT09_T 0x0200 ++#define BIT10_T 0x0400 ++#define BIT11_T 0x0800 ++#define BIT12_T 0x1000 ++#define BIT13_T 0x2000 ++#define BIT14_T 0x4000 ++#define BIT15_T 0x8000 ++#define BIT16_T 0x00010000 ++#define BIT17_T 0x00020000 ++#define BIT18_T 0x00040000 ++#define BIT19_T 0x00080000 ++#define BIT20_T 0x00100000 ++#define BIT21_T 0x00200000 ++#define BIT22_T 0x00400000 ++#define BIT23_T 0x00800000 ++#define BIT24_T 0x01000000 ++#define BIT25_T 0x02000000 ++#define BIT26_T 0x04000000 ++#define BIT27_T 0x08000000 ++#define BIT28_T 0x10000000 ++#define BIT29_T 0x20000000 ++#define BIT30_T 0x40000000 ++#define BIT31_T 0x80000000 ++ ++#define SD_RED "\e[1;31m" ++#define SD_DEF "\e[0m" ++ ++ ++ ++typedef enum ++{ ++ IP_ORDER_0 = 0, ++ IP_ORDER_1, ++ IP_ORDER_2, ++ ++} IpOrder; ++ ++typedef enum ++{ ++ IP_TYPE_FCIE = 0, ++ IP_TYPE_SDIO, ++ IP_TYPE_NONE, ++ ++} IpType; ++ ++typedef enum ++{ ++ PAD_ORDER_0 = 0, ++ PAD_ORDER_1, ++ PAD_ORDER_2, ++ PAD_ORDER_3, ++ PAD_ORDER_4, ++ PAD_ORDER_5, ++ ++} PadOrder; ++ ++ ++ ++ ++typedef enum ++{ ++ EV_BUS_LOW = 0, ++ EV_BUS_DEF = 1, ++ EV_BUS_HS = 2, ++ EV_BUS_SDR12 = 3, ++ EV_BUS_SDR25 = 4, ++ EV_BUS_SDR50 = 5, ++ EV_BUS_SDR104 = 6, ++ EV_BUS_DDR50 = 7, ++ EV_BUS_HS200 = 8, ++ ++} BusTimingEmType; ++ ++ ++typedef enum ++{ ++ EV_OK = 0, ++ EV_FAIL = 1, ++ ++} RetEmType; ++ ++ ++//*********************************************************************************************************** ++// (3) BASE OS/CPU define and Include Files for Different OS/CPU ++//*********************************************************************************************************** ++#define D_OS D_OS__LINUX ++#define D_CPU D_CPU__ARM ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++//########################################################################################################### ++#elif (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++#include ++//########################################################################################################### ++#elif (D_OS == D_OS__NONE) ++//########################################################################################################### ++#include ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++ ++//*********************************************************************************************************** ++// (4) BASE Debug System ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#define sdmmc_print printk ++ ++//########################################################################################################### ++#elif (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++#define sdmmc_print printf ++ ++//########################################################################################################### ++#elif (D_OS == D_OS__NONE) ++//########################################################################################################### ++#define sdmmc_print(s) uart_write_string((unsigned char*)s) ++ ++//########################################################################################################### ++#elif (D_OS == D_OS__YBOX) ++//########################################################################################################### ++#define sdmmc_print(s) printf ++ ++//########################################################################################################### ++#else ++//########################################################################################################### ++#define sdmmc_print(s) printf ++ ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++ ++//*********************************************************************************************************** ++// (5) BASE Project/FCIE/Ver.. Define ++//*********************************************************************************************************** ++ ++#define D_ICVER D_ICVER_00 ++#define D_FCIE_R_VER D_FCIE_R_VER__00 ++//#define D_BDVER 0 ++ ++#endif //End of __HAL_CARD_BASE_H +diff --git a/drivers/sstar/sdmmc/inc/hal_card_intr_v5.h b/drivers/sstar/sdmmc/inc/hal_card_intr_v5.h +new file mode 100755 +index 000000000000..985c16efa01a +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_card_intr_v5.h +@@ -0,0 +1,88 @@ ++/* ++* hal_card_intr_v5.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_intr.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of hal_card_intr.c. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_INTR_H ++#define __HAL_CARD_INTR_H ++ ++#include "hal_card_regs.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++//#if (D_PROJECT == D_PROJECT__CB2) //For Columbus2 ++//########################################################################################################### ++ ++//########################################################################################################### ++//#elif (D_PROJECT == D_PROJECT__G2) //For G2 ++//########################################################################################################### ++ ++#define WT_INT_RISKTIME 10 //(ms) Add Risk Time for wait_event_timer ++ ++//########################################################################################################### ++//#endif ++ ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++ ++typedef struct ++{ ++ U32_T slotNo; ++ IpOrder eIP; ++ void * p_data; ++ ++} IntSourceStruct; ++ ++ ++void Hal_CARD_INT_MIEIntCtrl(IpOrder eIP, BOOL_T bEnable); ++BOOL_T Hal_CARD_INT_MIEIntRunning(IpOrder eIP); ++ ++void Hal_CARD_INT_SetMIEIntEn(IpOrder eIP, U16_T u16RegMIEIntEN); ++void Hal_CARD_INT_SetMIEIntEn_ForSDIO(IpOrder eIP, BOOL_T bEnable); ++void Hal_CARD_INT_ClearMIEEvent(IpOrder eIP); ++U16_T Hal_CARD_INT_GetMIEEvent(IpOrder eIP); ++ ++BOOL_T Hal_CARD_INT_WaitMIEEvent(IpOrder eIP, U16_T u16ReqEvent, U32_T u32WaitMs); ++void Hal_CARD_INT_StopWaitMIEEventCtrl(IpOrder eIP, BOOL_T bEnable); ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include ++#include ++ ++irqreturn_t Hal_CARD_INT_MIE(int irq, void *p_dev_id); ++ ++#endif ++//########################################################################################################### ++ ++ ++ ++ ++#endif //End of __HAL_CARD_INTR_H +diff --git a/drivers/sstar/sdmmc/inc/hal_card_platform.h b/drivers/sstar/sdmmc/inc/hal_card_platform.h +new file mode 100755 +index 000000000000..dee04dea2d5a +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_card_platform.h +@@ -0,0 +1,86 @@ ++/* ++* hal_card_platform.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of hal_card_platform_XX.c. ++ * Every project has the same header file. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_PLATFORM_H ++#define __HAL_CARD_PLATFORM_H ++ ++#include "hal_card_regs.h" ++ ++typedef enum ++{ ++ EV_PULLDOWN, ++ EV_PULLUP, ++ ++} PinPullEmType; ++ ++typedef enum ++{ ++ EV_GPIO_OPT1 = 0, ++ EV_GPIO_OPT2 = 1, ++ EV_GPIO_OPT3 = 2, ++ EV_GPIO_OPT4 = 3, ++ EV_GPIO_OPT5 = 4, ++ ++} GPIOOptEmType; ++ ++ ++ ++void Hal_CARD_IPOnceSetting(IpOrder eIP); ++ ++// PAD Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_InitPADPin(IpOrder eIP, PadOrder ePAD); ++BOOL_T Hal_CARD_GetPadInfoCdzPad(IpOrder eIP, U32_T *nPadNum); ++BOOL_T Hal_CARD_GetPadInfoPowerPad(IpOrder eIP, U32_T *nPadNum); ++void Hal_CARD_ConfigSdPad(IpOrder eIP, PadOrder ePAD); ++void Hal_CARD_ConfigPowerPad(IpOrder eIP, U16_T nPadNum); ++void Hal_CARD_PullPADPin(IpOrder eIP, PadOrder ePAD, PinPullEmType ePinPull); ++ ++// Clock Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_SetClock(IpOrder eIP, U32_T u32ClkFromIPSet); ++U32_T Hal_CARD_FindClockSetting(IpOrder eIP, U32_T u32ReffClk); ++#ifdef CONFIG_PM_SLEEP ++void Hal_CARD_devpm_GetClock(U32_T u32SlotNo, U32_T *pu32PmIPClk, U32_T *pu32PmBlockClk); ++void Hal_CARD_devpm_setClock(U32_T u32SlotNo, U32_T u32PmIPClk, U32_T u32PmBlockClk); ++#endif ++ ++// Power and Voltage Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_PowerOn(IpOrder eIP, U16_T u16DelayMs); ++void Hal_CARD_PowerOff(IpOrder eIP, U16_T u16DelayMs); ++ ++// Card Detect and GPIO Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_ConfigCdzPad(IpOrder eIP, U16_T nPadNum); //Hal_CARD_InitGPIO ++BOOL_T Hal_CARD_GetCdzState(IpOrder eIP); //Hal_CARD_GetGPIOState ++ ++// MIU Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr, U8_T* pu8MIUSel); ++ ++#endif //End of __HAL_CARD_PLATFORM_H +diff --git a/drivers/sstar/sdmmc/inc/hal_card_regs.h b/drivers/sstar/sdmmc/inc/hal_card_regs.h +new file mode 100755 +index 000000000000..823b0020e763 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_card_regs.h +@@ -0,0 +1,95 @@ ++/* ++* hal_card_regs.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_regs.h ++ * @author jeremy.wang (2015/08/12) ++ * Desc: ++ * This file is the header file of hal_card_regs.c. ++ * ++ * For Base RegisterSetting: ++ * (1) BASE Register Address ++ * (2) BASE Register Operation ++ * (3) BASE FCIE Reg Meaning Position (Including File) ++ * ++ * P.S. If you want to use only IP for single card or dual cards, ++ * please modify FCIE1 and FCIE2 setting to the same reg position. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_REGS_H ++#define __HAL_CARD_REGS_H ++ ++#include "hal_card_base.h" ++ ++//*********************************************************************************************************** ++// (1) BASE Register Address ++//*********************************************************************************************************** ++#include "hal_card_platform_regs.h" ++ ++//*********************************************************************************************************** ++// (2) BASE Register Operation ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ #include "../../../sstar/include/ms_platform.h" //IO_ADDRESS // IO Mapping Address ++ #define IO_MAPADDR(Reg_Addr) IO_ADDRESS(Reg_Addr) ++ //#endif ++//########################################################################################################### ++#else ++//########################################################################################################### ++#define IO_MAPADDR(Reg_Addr) Reg_Addr ++//########################################################################################################### ++#endif ++ ++#define D_MIU_WIDTH 8 // Special MIU WIDTH for FCIE4 ++#define REG_OFFSET_BITS 2 // Register Offset Byte (2= 4byte = 32bits) ++#define GET_CARD_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_BITS)) ++ ++#define CARD_REG(Reg_Addr) (*(volatile U16_T*)(IO_MAPADDR(Reg_Addr)) ) ++#define CARD_REG_L8(Reg_Addr) (*(volatile U8_T*)(IO_MAPADDR(Reg_Addr)) ) ++#define CARD_REG_H8(Reg_Addr) (*( (volatile U8_T*)(IO_MAPADDR(Reg_Addr))+1) ) ++ ++#define CARD_REG_SETBIT(Reg_Addr, Value) CARD_REG(Reg_Addr) |= (Value) ++#define CARD_REG_CLRBIT(Reg_Addr, Value) CARD_REG(Reg_Addr) &= (~(Value)) ++ ++#define CARD_REG_L8_SETBIT(Reg_Addr, Value) CARD_REG_L8(Reg_Addr) |= (Value) ++#define CARD_REG_H8_SETBIT(Reg_Addr, Value) CARD_REG_H8(Reg_Addr) |= (Value) ++#define CARD_REG_L8_CLRBIT(Reg_Addr, Value) CARD_REG_L8(Reg_Addr) &= (~(Value)) ++#define CARD_REG_H8_CLRBIT(Reg_Addr, Value) CARD_REG_H8(Reg_Addr) &= (~(Value)) ++ ++#define CARD_BANK(Bank_Addr) IO_MAPADDR(Bank_Addr) ++ ++volatile void* Hal_CREG_GET_REG_BANK(IpOrder eIP, U8_T u8Bank); ++ ++#define GET_CARD_BANK Hal_CREG_GET_REG_BANK ++ ++//*********************************************************************************************************** ++// (3) BASE FCIE Reg Meaning Position (Including File) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#include "hal_card_regs_v5.h" ++//########################################################################################################### ++ ++ ++#endif //End of __HAL_CARD_REGS_H ++ ++ +diff --git a/drivers/sstar/sdmmc/inc/hal_card_regs_v5.h b/drivers/sstar/sdmmc/inc/hal_card_regs_v5.h +new file mode 100644 +index 000000000000..75bb5de682a0 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_card_regs_v5.h +@@ -0,0 +1,243 @@ ++/* ++* hal_card_regs_v5.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_regs_v5.h ++ * @author jeremy.wang (2015/06/03) ++ * Desc: ++ * This file is the header file for hal_card_regs.h ++ * ++ * We add a new header file to describe the meaning positions of fcie5 registers ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_REGS_V5_H ++#define __HAL_CARD_REGS_V5_H ++ ++//============================================ ++//MIE_EVENT: offset 0x00 ++//============================================ ++#define R_DATA_END BIT00_T ++#define R_CMD_END BIT01_T ++#define R_ERR_STS BIT02_T ++#define R_SDIO_INT BIT03_T ++#define R_BUSY_END_INT BIT04_T ++#define R_R2N_RDY_INT BIT05_T ++#define R_CARD_CHANGE BIT06_T ++#define R_CARD2_CHANGE BIT07_T ++ ++ ++//============================================ ++//MIE_INT_EN: offset 0x01 ++//============================================ ++#define R_DATA_END_IEN BIT00_T ++#define R_CMD_END_IEN BIT01_T ++#define R_ERR_STS_IEN BIT02_T ++#define R_SDIO_INT_IEN BIT03_T ++#define R_BUSY_END_IEN BIT04_T ++#define R_R2N_RDY_INT_IEN BIT05_T ++#define R_CARD_CHANGE_IEN BIT06_T ++#define R_CARD2_CHANGE_IEN BIT07_T ++ ++//============================================ ++//MMA_PRI_REG: offset 0x02 ++//============================================ ++#define R_MIU_R_PRIORITY BIT00_T ++#define R_MIU_W_PRIORITY BIT01_T ++ ++#define R_MIU1_SELECT BIT02_T ++#define R_MIU2_SELECT BIT03_T ++#define R_MIU3_SELECT (BIT03_T|BIT02_T) ++ ++#define R_MIU_BUS_BURST2 BIT04_T ++#define R_MIU_BUS_BURST4 BIT05_T ++#define R_MIU_BUS_BURST8 (BIT05_T|BIT04_T) ++ ++//============================================ ++//MIE_FUNC_CTL: offset 0x07 ++//============================================ ++#define R_EMMC_EN BIT00_T ++#define R_SD_EN BIT01_T ++#define R_SDIO_MODE BIT02_T ++ ++ ++//============================================ ++//SD_MODE: offset 0x0B ++//============================================ ++#define R_CLK_EN BIT00_T ++#define R_BUS_WIDTH_4 BIT01_T ++#define R_BUS_WIDTH_8 BIT02_T ++#define R_DEST_R2N BIT04_T ++#define R_DATASYNC BIT05_T ++#define R_DMA_RD_CLK_STOP BIT07_T ++#define R_DIS_WR_BUSY_CHK BIT08_T ++#define R_STOP_BLK BIT09_T ++ ++//============================================ ++//SD_CTL: offset 0x0C ++//============================================ ++#define R_RSPR2_EN BIT00_T ++#define R_RSP_EN BIT01_T ++#define R_CMD_EN BIT02_T ++#define R_DTRX_EN BIT03_T ++#define R_JOB_DIR BIT04_T ++#define R_ADMA_EN BIT05_T ++#define R_JOB_START BIT06_T ++#define R_CHK_CMD BIT07_T ++#define R_BUSY_DET_ON BIT08_T ++#define R_ERR_DET_ON BIT09_T ++ ++ ++//============================================ ++//SD_STS: offset 0x0D ++//============================================ ++#define R_DAT_RD_CERR BIT00_T ++#define R_DAT_WR_CERR BIT01_T ++#define R_DAT_WR_TOUT BIT02_T ++#define R_CMD_NORSP BIT03_T ++#define R_CMDRSP_CERR BIT04_T ++#define R_DAT_RD_TOUT BIT05_T ++#define R_CARD_BUSY BIT06_T ++#define R_DAT0 BIT08_T ++#define R_DAT1 BIT09_T ++#define R_DAT2 BIT10_T ++#define R_DAT3 BIT11_T ++#define R_DAT4 BIT12_T ++#define R_DAT5 BIT13_T ++#define R_DAT6 BIT14_T ++#define R_DAT7 BIT15_T ++ ++ ++//============================================ ++//BOOT_MOD:offset 0x0E ++//============================================ ++#define R_BOOT_MODE BIT02_T ++ ++ ++//============================================ ++//DDR_MOD: offset 0x0F ++//============================================ ++#define R_PAD_IN_BYPASS BIT00_T ++#define R_PAD_IN_RDY_SEL BIT01_T ++#define R_PRE_FULL_SEL0 BIT02_T ++#define R_PRE_FULL_SEL1 BIT03_T ++#define R_DDR_MACRO_EN BIT07_T ++#define R_DDR_EN BIT08_T ++#define R_PAD_CLK_SEL BIT10_T ++#define R_PAD_IN_SEL_IP BIT11_T ++#define R_DDR_MACRO32_EN BIT12_T ++#define R_PAD_IN_SEL BIT13_T ++#define R_FALL_LATCH BIT14_T ++#define R_PAD_IN_MASK BIT15_T ++ ++ ++//============================================ ++//SDIO_MOD: offset 0x11 ++//============================================ ++#define R_SDIO_INT_MOD0 BIT00_T ++#define R_SDIO_INT_MOD1 BIT01_T ++#define R_SDIO_INT_MOD_SW_EN BIT02_T ++#define R_SDIO_DET_INT_SRC BIT03_T ++#define R_SDIO_INT_TUNE0 BIT04_T ++#define R_SDIO_INT_TUNE1 BIT05_T ++#define R_SDIO_INT_TUNE2 BIT06_T ++#define R_SDIO_INT_TUNE_CLR0 BIT07_T ++#define R_SDIO_INT_TUNE_CLR1 BIT08_T ++#define R_SDIO_INT_TUNE_CLR2 BIT09_T ++#define R_SDIO_RDWAIT_EN BIT11_T ++#define R_SDIO_BLK_GAP_DIS BIT12_T ++#define R_SDIO_INT_STOP_DMA BIT13_T ++#define R_SDIO_INT_TUNE_SW BIT14_T ++#define R_SDIO_INT_ASYN_EN BIT15_T ++ ++ ++//============================================ ++//TEST_MOD: offset 0x15 ++//============================================ ++#define R_SDDR1 BIT00_T ++#define R_SD_DEBUG_MOD0 BIT01_T ++#define R_SD_DEBUG_MOD1 BIT02_T ++#define R_SD_DEBUG_MOD2 BIT03_T ++#define R_BIST_MODE BIT04_T ++ ++ ++//============================================ ++//WR_SBIT_TIMER: offset 0x17 ++//============================================ ++#define R_WR_SBIT_TIMER_EN BIT15_T ++ ++ ++//============================================ ++//RD_SBIT_TIMER: offset 0x18 ++//============================================ ++#define R_RD_SBIT_TIMER_EN BIT15_T ++ ++ ++//============================================ ++//SDIO_DET_ON: offset 0x2F ++//============================================ ++#define R_SDIO_DET_ON BIT00_T ++ ++ ++//============================================ ++//CIFD_EVENT: offset 0x30 ++//============================================ ++#define R_WBUF_FULL BIT00_T ++#define R_WBUF_EMPTY_TRIG BIT01_T ++#define R_RBUF_FULL_TRIG BIT02_T ++#define R_RBUF_EMPTY BIT03_T ++ ++ ++//============================================ ++//CIFD_INT_EN: offset 0x31 ++//============================================ ++#define R_WBUF_FULL_IEN BIT00_T ++#define R_RBUF_EMPTY_IEN BIT01_T ++#define R_F_WBUF_FULL_INT BIT08_T ++#define R_F_RBUF_EMPTY_INT BIT09_T ++ ++ ++//============================================ ++//BOOT_MODE:offset 0x37 ++//============================================ ++#define R_NAND_BOOT_EN BIT00_T ++#define R_BOOTSRAM_ACCESS_SEL BIT01_T ++#define R_IMI_SEL BIT02_T ++ ++ ++//============================================ ++//CIFD_INT_EN: offset 0x39 ++//============================================ ++#define R_DEBUG_MOD0 BIT08_T ++#define R_DEBUG_MOD1 BIT09_T ++#define R_DEBUG_MOD2 BIT10_T ++#define R_DEBUG_MOD3 BIT11_T ++ ++ ++//============================================ ++//FCIE_RST:offset 0x3F ++//============================================ ++#define R_FCIE_SOFT_RST BIT00_T ++#define R_RST_MIU_STS BIT01_T ++#define R_RST_MIE_STS BIT02_T ++#define R_RST_MCU_STS BIT03_T ++#define R_RST_ECC_STS BIT04_T ++ ++ ++ ++#endif //End of __HAL_CARD_FCIE5_H +diff --git a/drivers/sstar/sdmmc/inc/hal_card_timer.h b/drivers/sstar/sdmmc/inc/hal_card_timer.h +new file mode 100755 +index 000000000000..ecec03f4054b +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_card_timer.h +@@ -0,0 +1,35 @@ ++/* ++* hal_card_timer.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_CARD_TIMER_H ++#define __HAL_CARD_TIMER_H ++ ++#include "hal_card_regs.h" ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include ++//########################################################################################################### ++#endif ++ ++U32_T Hal_Timer_mDelay(U32_T u32_msec); ++U32_T Hal_Timer_uDelay(U32_T u32_usec); ++U32_T Hal_Timer_mSleep(U32_T u32_msec); ++ ++#endif //End of __HAL_CARD_TIMER_H +diff --git a/drivers/sstar/sdmmc/inc/hal_sdmmc_v5.h b/drivers/sstar/sdmmc/inc/hal_sdmmc_v5.h +new file mode 100755 +index 000000000000..d2f870c3969a +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/hal_sdmmc_v5.h +@@ -0,0 +1,198 @@ ++/* ++* hal_sdmmc_v5.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __HAL_SDMMC_V5_H ++#define __HAL_SDMMC_V5_H ++ ++#include "hal_card_regs.h" ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++#include "hal_card_platform_config.h" ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) //For LInux ++//########################################################################################################### ++#define EN_BIND_CARD_INT (TRUE) ++//########################################################################################################### ++#else ++//########################################################################################################### ++#define EN_BIND_CARD_INT (FALSE) ++//########################################################################################################### ++#endif ++ ++ ++ ++typedef enum ++{ ++ //SD_STS Reg Error ++ EV_STS_OK = 0x0000, ++ EV_STS_RD_CERR = BIT00_T, ++ EV_STS_WD_CERR = BIT01_T, ++ EV_STS_WR_TOUT = BIT02_T, ++ EV_STS_NORSP = BIT03_T, ++ EV_STS_RSP_CERR = BIT04_T, ++ EV_STS_RD_TOUT = BIT05_T, ++ ++ //SD IP Error ++ EV_STS_RIU_ERR = BIT06_T, ++ EV_STS_DAT0_BUSY = BIT07_T, ++ EV_STS_MIE_TOUT = BIT08_T, ++ ++ //Stop Wait Process Error ++ EV_SWPROC_ERR = BIT09_T, ++ ++ //SD Check Error ++ EV_CMD8_PERR = BIT10_T, ++ EV_OCR_BERR = BIT11_T, ++ EV_OUT_VOL_RANGE = BIT12_T, ++ EV_STATE_ERR = BIT13_T, ++ ++ //Other Error ++ EV_OTHER_ERR = BIT15_T, ++ ++ ++} RspErrEmType; ++ ++typedef enum ++{ ++ EV_CMDRSP =0x000, ++ EV_CMDREAD =0x001, ++ EV_CMDWRITE =0x101, ++ ++} CmdEmType; ++ ++typedef enum ++{ ++ EV_EMP = 0x0000, ++ EV_ADMA = 0x0020, //Add at FCIE5 ++ EV_DMA = 0x0080, //Change at FCIE5 ++ EV_CIF = 0x1000, //Change at FCIE5 ++ ++} TransEmType; ++ ++//(2bits: Rsp Mapping to SD_CTL) (4bits: Identity) (8bits: RspSize) ++typedef enum ++{ ++ EV_NO = 0x0000, //No response type ++ EV_R1 = 0x2105, ++ EV_R1B = 0x2205, ++ EV_R2 = 0x3310, ++ EV_R3 = 0x2405, ++ EV_R4 = 0x2505, ++ EV_R5 = 0x2605, ++ EV_R6 = 0x2705, ++ EV_R7 = 0x2805, ++ ++} SDMMCRspEmType; ++ ++typedef enum ++{ ++ EV_BUS_1BIT = 0x00, ++ EV_BUS_4BITS = 0x02, ++ EV_BUS_8BITS = 0x04, ++ ++} SDMMCBusWidthEmType; ++ ++typedef enum ++{ ++ EV_MIE = 0x0, ++ EV_CIFD = 0x1, ++ ++} IPEventEmType; ++ ++ ++typedef enum ++{ ++ EV_EGRP_OK = 0x0, ++ EV_EGRP_TOUT = 0x1, ++ EV_EGRP_COMM = 0x2, ++ EV_EGRP_OTHER = 0x3, ++ ++} ErrGrpEmType; ++ ++typedef struct ++{ ++ U8_T u8Cmd; ++ U32_T u32Arg; //Mark for ROM ++ U32_T u32ErrLine; //Mark for ROM ++ RspErrEmType eErrCode; ++ U8_T u8RspSize; //Mark for ROM ++ U8_T u8ArrRspToken[0x10]; //U8_T u8ArrRspToken[0x10]; //Mark for ROM ++ ++} RspStruct; ++ ++ ++typedef struct ++{ ++ U32_T u32_End : 1; ++ U32_T u32_MiuSel : 2; ++ U32_T : 13; ++ U32_T u32_JobCnt : 16; ++ U32_T u32_Address; ++ U32_T u32_DmaLen; ++ U32_T u32_Dummy; ++ ++} AdmaDescStruct; ++ ++ ++// SDMMC Operation Function ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_SetDataWidth(IpOrder eIP, SDMMCBusWidthEmType eBusWidth); ++void Hal_SDMMC_SetBusTiming(IpOrder eIP, BusTimingEmType eBusTiming); ++void Hal_SDMMC_SetNrcDelay(IpOrder eIP, U32_T u32RealClk); ++ ++void Hal_SDMMC_SetCmdToken(IpOrder eIP, U8_T u8Cmd, U32_T u32Arg); ++RspStruct* Hal_SDMMC_GetRspToken(IpOrder eIP); ++void Hal_SDMMC_TransCmdSetting(IpOrder eIP, TransEmType eTransType, U16_T u16BlkCnt, U16_T u16BlkSize, volatile U32_T u32BufAddr, volatile U8_T *pu8Buf); ++RspErrEmType Hal_SDMMC_SendCmdAndWaitProcess(IpOrder eIP, TransEmType eTransType, CmdEmType eCmdType, SDMMCRspEmType eRspType, BOOL_T bCloseClk); ++RspErrEmType Hal_SDMMC_RunBrokenDmaAndWaitProcess(IpOrder eIP, CmdEmType eCmdType); ++void Hal_SDMMC_ADMASetting(volatile void *pDMATable, U8_T u8Item, U32_T u32SubLen, U16_T u16SubBCnt, U32_T u32SubAddr, U8_T u8MIUSel, BOOL_T bEnd); ++ ++// SDMMC Special Operation Function ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_ClkCtrl(IpOrder eIP, BOOL_T bEnable, U16_T u16DelayMs); ++void Hal_SDMMC_Reset(IpOrder eIP); ++void Hal_SDMMC_StopProcessCtrl(IpOrder eIP, BOOL_T bEnable); ++BOOL_T Hal_SDMMC_OtherPreUse(IpOrder eIP); ++ErrGrpEmType Hal_SDMMC_ErrGroup(RspErrEmType eErrType); ++ ++// SDMMC Information ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_DumpMemTool(U8_T u8ListNum, volatile U8_T *pu8Buf); ++U8_T Hal_SDMMC_GetDATBusLevel(IpOrder eIP); ++U16_T Hal_SDMMC_GetMIEEvent(IpOrder eIP); ++ ++// SDMMC SDIO Setting ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_SDIODeviceCtrl(IpOrder eIP, BOOL_T bEnable); ++void Hal_SDMMC_SDIOIntDetCtrl(IpOrder eIP, BOOL_T bEnable); ++void Hal_SDMMC_SetSDIOIntBeginSetting(IpOrder eIP, U8_T u8Cmd, U32_T u32Arg, CmdEmType eCmdType, U16_T u16BlkCnt); ++void Hal_SDMMC_SetSDIOIntEndSetting(IpOrder eIP, RspErrEmType eRspErr, U16_T u16BlkCnt); ++ ++// SDMMC Interrupt Setting ++//---------------------------------------------------------------------------------------------------------- ++#if(EN_BIND_CARD_INT) ++ ++void Hal_SDMMC_MIEIntCtrl(IpOrder eIP, BOOL_T bEnable); ++ ++ ++#endif //End of EN_BIND_CARD_INT ++ ++ ++ ++#endif //End of __HAL_SDMMC_V5_H +diff --git a/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_config.h b/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_config.h +new file mode 100755 +index 000000000000..05cddc6a2bb8 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_config.h +@@ -0,0 +1,62 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++// ++#include "gpio.h" ++ ++// ++#define IP_0_TYPE IP_TYPE_SDIO ++#define IP_1_TYPE IP_TYPE_NONE ++#define IP_2_TYPE IP_TYPE_NONE ++ ++/* -------------------------------------------------------- ++< WT_POWERUP > ++SD Spec: ++- This delay should be sufficient to allow the power supply to reach the minimum voltage. ++HW measure: ++- About 5x us is enough. ++ ++< WT_POWERON > ++SD Spec: ++- This delay must be at least 74 clock sizes, or 1 ms, or the time required to reach a stable voltage. ++ ++< WT_POWEROFF > ++SD Spec: ++- the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms. ++HW measure: ++- SD_3V3 has 2K resistance to gnd: 30 ms. ++- SD_3V3 does Not have any resistance to gnd: 1500 ms. ++-------------------------------------------------------- */ ++#define WT_POWERUP 1 //(ms) ++#define WT_POWERON 1 //(ms) ++#define WT_POWEROFF 30 //(ms) Here is only for default, real value will be from DTS. ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++#define DEF_CDZ_PAD_SLOT0 (PAD_PM_SD_CDZ) ++#define DEF_CDZ_PAD_SLOT1 0 ++#define DEF_CDZ_PAD_SLOT2 0 ++ ++#define DEF_PWR_PAD_SLOT0 (PAD_TTL0) ++#define DEF_PWR_PAD_SLOT1 0 ++#define DEF_PWR_PAD_SLOT2 0 ++ ++#define EN_MSYS_REQ_DMEM (FALSE) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_pri_config.h b/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_pri_config.h +new file mode 100755 +index 000000000000..d199a2f5992a +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_pri_config.h +@@ -0,0 +1,56 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++ ++// PADMUX_SET ++#define PADMUX_SET_BY_FUNC (0) ++#define PADMUX_SET_BY_REG (1) ++ ++//GPIO_SET ++#define GPIO_SET_BY_FUNC (0) ++#define GPIO_SET_BY_REG (1) ++ ++#if (D_OS == D_OS__LINUX) ++#define PADMUX_SET (PADMUX_SET_BY_FUNC) ++#define GPIO_SET (GPIO_SET_BY_FUNC) ++ ++#define FORCE_SWITCH_PAD (FALSE) ++#else ++#define PADMUX_SET (PADMUX_SET_BY_REG) ++#define GPIO_SET (GPIO_SET_BY_REG) ++ ++#define FORCE_SWITCH_PAD (TRUE) ++#endif ++ ++ ++ ++typedef enum ++{ ++ IP_SDIO = IP_ORDER_0, ++ IP_TOTAL, ++ ++} IpSelect; ++ ++typedef enum ++{ ++ PAD_SD = PAD_ORDER_0, // PAD_SD ++ PAD_GPIO = PAD_ORDER_1, // PAD_GPIO4 ~ PAD_GPIO9 ++ ++} PadSelect; ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_regs.h b/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_regs.h +new file mode 100644 +index 000000000000..5675b395a47d +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity2m/hal_card_platform_regs.h +@@ -0,0 +1,32 @@ ++/* ++* hal_card_paltform_regs.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#define A_RIU_BASE (0x1F000000) ++//but this does send command error: EV_STS_MIE_TOUT ++//---- sd & sdio ---- ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //SDIO0_0_BANK 1410h (SD on i6) ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //SDIO0_1_BANK 1411h ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //SDIO0_2_BANK 1412h ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //FCIE0_0_BANK 1410h (SD1 on i6) ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //FCIE0_1_BANK 1411h ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //FCIE0_2_BANK 1412h ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //not used ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_config.h b/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_config.h +new file mode 100755 +index 000000000000..eda55c2ed1a0 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_config.h +@@ -0,0 +1,62 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++// ++#include "gpio.h" ++ ++// ++#define IP_0_TYPE IP_TYPE_SDIO ++#define IP_1_TYPE IP_TYPE_FCIE ++#define IP_2_TYPE IP_TYPE_NONE ++ ++/* -------------------------------------------------------- ++< WT_POWERUP > ++SD Spec: ++- This delay should be sufficient to allow the power supply to reach the minimum voltage. ++HW measure: ++- About 5x us is enough. ++ ++< WT_POWERON > ++SD Spec: ++- This delay must be at least 74 clock sizes, or 1 ms, or the time required to reach a stable voltage. ++ ++< WT_POWEROFF > ++SD Spec: ++- the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms. ++HW measure: ++- SD_3V3 has 2K resistance to gnd: 30 ms. ++- SD_3V3 does Not have any resistance to gnd: 1500 ms. ++-------------------------------------------------------- */ ++#define WT_POWERUP 1 //(ms) ++#define WT_POWERON 1 //(ms) ++#define WT_POWEROFF 30 //(ms) Here is only for default, real value will be from DTS. ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++#define DEF_CDZ_PAD_SLOT0 (PAD_PM_SD_CDZ) ++#define DEF_CDZ_PAD_SLOT1 (PAD_PM_IRIN) ++#define DEF_CDZ_PAD_SLOT2 0 ++ ++#define DEF_PWR_PAD_SLOT0 (PAD_FUART_RTS) ++#define DEF_PWR_PAD_SLOT1 (PAD_PM_GPIO6) ++#define DEF_PWR_PAD_SLOT2 0 ++ ++#define EN_MSYS_REQ_DMEM (FALSE) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_pri_config.h b/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_pri_config.h +new file mode 100755 +index 000000000000..5ce5db22d235 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_pri_config.h +@@ -0,0 +1,58 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++ ++// PADMUX_SET ++#define PADMUX_SET_BY_FUNC (0) ++#define PADMUX_SET_BY_REG (1) ++ ++//GPIO_SET ++#define GPIO_SET_BY_FUNC (0) ++#define GPIO_SET_BY_REG (1) ++ ++#if (D_OS == D_OS__LINUX) ++#define PADMUX_SET (PADMUX_SET_BY_REG) // PADMUX_SET_BY_FUNC i5 kernel NOT support padmux function. ++#define GPIO_SET (GPIO_SET_BY_REG) // GPIO_SET_BY_FUNC i5 kernel NOT yet implement. ++ ++#define FORCE_SWITCH_PAD (FALSE) ++#else ++#define PADMUX_SET (PADMUX_SET_BY_REG) ++#define GPIO_SET (GPIO_SET_BY_REG) ++ ++#define FORCE_SWITCH_PAD (TRUE) ++#endif ++ ++ ++ ++typedef enum ++{ ++ IP_SDIO = IP_ORDER_0, ++ IP_FCIE = IP_ORDER_1, ++ IP_TOTAL, ++ ++} IpSelect; ++ ++typedef enum ++{ ++ PAD_SD = PAD_ORDER_0, // PAD_SD ++ PAD_NAND = PAD_ORDER_1, // PAD_NAND ++ PAD_LCD = PAD_ORDER_2, // PAD_LCD ++ PAD_SNR = PAD_ORDER_3, // PAD_SNR ++ ++} PadSelect; +diff --git a/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_regs.h b/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_regs.h +new file mode 100644 +index 000000000000..aaa560c4134e +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity5/hal_card_platform_regs.h +@@ -0,0 +1,32 @@ ++/* ++* hal_card_paltform_regs.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#define A_RIU_BASE (0x1F000000) ++ ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //SDIO0_0_BANK ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //SDIO0_1_BANK ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //SDIO0_2_BANK ++ ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //FCIE0_0_BANK ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) //FCIE0_1_BANK ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) //FCIE0_2_BANK ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_config.h b/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_config.h +new file mode 100755 +index 000000000000..8d83df02182d +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_config.h +@@ -0,0 +1,62 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++// ++#include "gpio.h" ++ ++// ++#define IP_0_TYPE IP_TYPE_SDIO ++#define IP_1_TYPE IP_TYPE_SDIO ++#define IP_2_TYPE IP_TYPE_NONE ++ ++/* -------------------------------------------------------- ++< WT_POWERUP > ++SD Spec: ++- This delay should be sufficient to allow the power supply to reach the minimum voltage. ++HW measure: ++- About 5x us is enough. ++ ++< WT_POWERON > ++SD Spec: ++- This delay must be at least 74 clock sizes, or 1 ms, or the time required to reach a stable voltage. ++ ++< WT_POWEROFF > ++SD Spec: ++- the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms. ++HW measure: ++- SD_3V3 has 2K resistance to gnd: 30 ms. ++- SD_3V3 does Not have any resistance to gnd: 1500 ms. ++-------------------------------------------------------- */ ++#define WT_POWERUP 1 //(ms) ++#define WT_POWERON 1 //(ms) ++#define WT_POWEROFF 30 //(ms) Here is only for default, real value will be from DTS. ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++#define DEF_CDZ_PAD_SLOT0 (PAD_PM_SD_CDZ) ++#define DEF_CDZ_PAD_SLOT1 (PAD_SD1_IO6) ++#define DEF_CDZ_PAD_SLOT2 0 ++ ++#define DEF_PWR_PAD_SLOT0 (PAD_FUART_RTS) ++#define DEF_PWR_PAD_SLOT1 (PAD_PM_GPIO9) ++#define DEF_PWR_PAD_SLOT2 0 ++ ++#define EN_MSYS_REQ_DMEM (FALSE) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_pri_config.h b/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_pri_config.h +new file mode 100755 +index 000000000000..d23560db68c7 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_pri_config.h +@@ -0,0 +1,57 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++ ++// PADMUX_SET ++#define PADMUX_SET_BY_FUNC (0) ++#define PADMUX_SET_BY_REG (1) ++ ++//GPIO_SET ++#define GPIO_SET_BY_FUNC (0) ++#define GPIO_SET_BY_REG (1) ++ ++#if (D_OS == D_OS__LINUX) ++#define PADMUX_SET (PADMUX_SET_BY_FUNC) ++#define GPIO_SET (GPIO_SET_BY_FUNC) ++ ++#define FORCE_SWITCH_PAD (FALSE) ++#else ++#define PADMUX_SET (PADMUX_SET_BY_REG) ++#define GPIO_SET (GPIO_SET_BY_REG) ++ ++#define FORCE_SWITCH_PAD (TRUE) ++#endif ++ ++ ++ ++typedef enum ++{ ++ IP_SD = IP_ORDER_0, ++ IP_SDIO = IP_ORDER_1, ++ IP_TOTAL, ++ ++} IpSelect; ++ ++typedef enum ++{ ++ PAD_SD = PAD_ORDER_0, // PAD_SD ++ PAD_SD1 = PAD_ORDER_1, // PAD_SD1 ++ ++} PadSelect; ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_regs.h b/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_regs.h +new file mode 100644 +index 000000000000..d9bb817bbac4 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6/hal_card_platform_regs.h +@@ -0,0 +1,32 @@ ++/* ++* hal_card_paltform_regs.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#define A_RIU_BASE (0x1F000000) ++//but this does send command error: EV_STS_MIE_TOUT ++//---- sd & sdio ---- ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0980) //SDIO0_0_BANK 1413h (SD on i6) ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0A00) //SDIO0_1_BANK 1414h ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0A80) //SDIO0_2_BANK 1415h ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //FCIE0_0_BANK 1410h (SD1 on i6) ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //FCIE0_1_BANK 1411h ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //FCIE0_2_BANK 1412h ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //not used ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_config.h b/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_config.h +new file mode 100755 +index 000000000000..8d83df02182d +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_config.h +@@ -0,0 +1,62 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++// ++#include "gpio.h" ++ ++// ++#define IP_0_TYPE IP_TYPE_SDIO ++#define IP_1_TYPE IP_TYPE_SDIO ++#define IP_2_TYPE IP_TYPE_NONE ++ ++/* -------------------------------------------------------- ++< WT_POWERUP > ++SD Spec: ++- This delay should be sufficient to allow the power supply to reach the minimum voltage. ++HW measure: ++- About 5x us is enough. ++ ++< WT_POWERON > ++SD Spec: ++- This delay must be at least 74 clock sizes, or 1 ms, or the time required to reach a stable voltage. ++ ++< WT_POWEROFF > ++SD Spec: ++- the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms. ++HW measure: ++- SD_3V3 has 2K resistance to gnd: 30 ms. ++- SD_3V3 does Not have any resistance to gnd: 1500 ms. ++-------------------------------------------------------- */ ++#define WT_POWERUP 1 //(ms) ++#define WT_POWERON 1 //(ms) ++#define WT_POWEROFF 30 //(ms) Here is only for default, real value will be from DTS. ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++#define DEF_CDZ_PAD_SLOT0 (PAD_PM_SD_CDZ) ++#define DEF_CDZ_PAD_SLOT1 (PAD_SD1_IO6) ++#define DEF_CDZ_PAD_SLOT2 0 ++ ++#define DEF_PWR_PAD_SLOT0 (PAD_FUART_RTS) ++#define DEF_PWR_PAD_SLOT1 (PAD_PM_GPIO9) ++#define DEF_PWR_PAD_SLOT2 0 ++ ++#define EN_MSYS_REQ_DMEM (FALSE) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_pri_config.h b/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_pri_config.h +new file mode 100755 +index 000000000000..d23560db68c7 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_pri_config.h +@@ -0,0 +1,57 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++ ++// PADMUX_SET ++#define PADMUX_SET_BY_FUNC (0) ++#define PADMUX_SET_BY_REG (1) ++ ++//GPIO_SET ++#define GPIO_SET_BY_FUNC (0) ++#define GPIO_SET_BY_REG (1) ++ ++#if (D_OS == D_OS__LINUX) ++#define PADMUX_SET (PADMUX_SET_BY_FUNC) ++#define GPIO_SET (GPIO_SET_BY_FUNC) ++ ++#define FORCE_SWITCH_PAD (FALSE) ++#else ++#define PADMUX_SET (PADMUX_SET_BY_REG) ++#define GPIO_SET (GPIO_SET_BY_REG) ++ ++#define FORCE_SWITCH_PAD (TRUE) ++#endif ++ ++ ++ ++typedef enum ++{ ++ IP_SD = IP_ORDER_0, ++ IP_SDIO = IP_ORDER_1, ++ IP_TOTAL, ++ ++} IpSelect; ++ ++typedef enum ++{ ++ PAD_SD = PAD_ORDER_0, // PAD_SD ++ PAD_SD1 = PAD_ORDER_1, // PAD_SD1 ++ ++} PadSelect; ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_regs.h b/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_regs.h +new file mode 100644 +index 000000000000..d9bb817bbac4 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6b0/hal_card_platform_regs.h +@@ -0,0 +1,32 @@ ++/* ++* hal_card_paltform_regs.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#define A_RIU_BASE (0x1F000000) ++//but this does send command error: EV_STS_MIE_TOUT ++//---- sd & sdio ---- ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0980) //SDIO0_0_BANK 1413h (SD on i6) ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0A00) //SDIO0_1_BANK 1414h ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0A80) //SDIO0_2_BANK 1415h ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //FCIE0_0_BANK 1410h (SD1 on i6) ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //FCIE0_1_BANK 1411h ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //FCIE0_2_BANK 1412h ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //not used ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_config.h b/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_config.h +new file mode 100755 +index 000000000000..6d0c869fe299 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_config.h +@@ -0,0 +1,62 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++// ++#include "gpio.h" ++ ++// ++#define IP_0_TYPE IP_TYPE_SDIO ++#define IP_1_TYPE IP_TYPE_SDIO ++#define IP_2_TYPE IP_TYPE_NONE ++ ++/* -------------------------------------------------------- ++< WT_POWERUP > ++SD Spec: ++- This delay should be sufficient to allow the power supply to reach the minimum voltage. ++HW measure: ++- About 5x us is enough. ++ ++< WT_POWERON > ++SD Spec: ++- This delay must be at least 74 clock sizes, or 1 ms, or the time required to reach a stable voltage. ++ ++< WT_POWEROFF > ++SD Spec: ++- the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms. ++HW measure: ++- SD_3V3 has 2K resistance to gnd: 30 ms. ++- SD_3V3 does Not have any resistance to gnd: 1500 ms. ++-------------------------------------------------------- */ ++#define WT_POWERUP 1 //(ms) ++#define WT_POWERON 1 //(ms) ++#define WT_POWEROFF 30 //(ms) Here is only for default, real value will be from DTS. ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++#define DEF_CDZ_PAD_SLOT0 (PAD_SD0_CDZ) ++#define DEF_CDZ_PAD_SLOT1 (PAD_SD1_CDZ) ++#define DEF_CDZ_PAD_SLOT2 0 ++ ++#define DEF_PWR_PAD_SLOT0 (PAD_SD0_GPIO0) ++#define DEF_PWR_PAD_SLOT1 (PAD_SD1_GPIO0) ++#define DEF_PWR_PAD_SLOT2 0 ++ ++#define EN_MSYS_REQ_DMEM (FALSE) ++ +diff --git a/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_pri_config.h b/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_pri_config.h +new file mode 100644 +index 000000000000..e1dedff3d5d2 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_pri_config.h +@@ -0,0 +1,57 @@ ++/* ++* hal_card_paltform_config.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++ ++// PADMUX_SET ++#define PADMUX_SET_BY_FUNC (0) ++#define PADMUX_SET_BY_REG (1) ++ ++//GPIO_SET ++#define GPIO_SET_BY_FUNC (0) ++#define GPIO_SET_BY_REG (1) ++ ++#if (D_OS == D_OS__LINUX) ++#define PADMUX_SET (PADMUX_SET_BY_FUNC) ++#define GPIO_SET (GPIO_SET_BY_FUNC) ++ ++#define FORCE_SWITCH_PAD (FALSE) ++#else ++#define PADMUX_SET (PADMUX_SET_BY_REG) ++#define GPIO_SET (GPIO_SET_BY_REG) ++ ++#define FORCE_SWITCH_PAD (TRUE) ++#endif ++ ++ ++ ++typedef enum ++{ ++ IP_SD = IP_ORDER_0, ++ IP_SDIO = IP_ORDER_1, ++ IP_TOTAL, ++ ++} IpSelect; ++ ++typedef enum ++{ ++ PAD_SD = PAD_ORDER_0, // PAD_SD ++ PAD_SD1 = PAD_ORDER_1, // PAD_SD1 ++ PAD_SD1_MD2 = PAD_ORDER_2, // PAD_SD1_MD2 ++ ++} PadSelect; +diff --git a/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_regs.h b/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_regs.h +new file mode 100644 +index 000000000000..a737b30e7264 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/infinity6e/hal_card_platform_regs.h +@@ -0,0 +1,32 @@ ++/* ++* hal_card_paltform_regs.h - Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#define A_RIU_BASE (0x1F000000) ++//but this does send command error: EV_STS_MIE_TOUT ++//---- sd & sdio ---- ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0980) //SDIO0_0_BANK 1413h (SD on i6) ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0A00) //SDIO0_1_BANK 1414h ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0A80) //SDIO0_2_BANK 1415h ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //FCIE0_0_BANK 1410h (SD1 on i6) ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //FCIE0_1_BANK 1411h ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //FCIE0_2_BANK 1412h ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //not used ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ +diff --git a/drivers/sstar/sdmmc/inc/ms_sdmmc_lnx.h b/drivers/sstar/sdmmc/inc/ms_sdmmc_lnx.h +new file mode 100755 +index 000000000000..8727b9d15389 +--- /dev/null ++++ b/drivers/sstar/sdmmc/inc/ms_sdmmc_lnx.h +@@ -0,0 +1,107 @@ ++/* ++* ms_sdmmc_lnx.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName ms_sdmmc_lnx.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of ms_sdmmc_lnx.c. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __MS_SDMMC_LNX_H ++#define __MS_SDMMC_LNX_H ++ ++#include ++#include ++#include "hal_card_base.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++#include "hal_card_platform_config.h" ++ ++ ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++typedef enum ++{ ++ EV_SDMMC1 = 0, ++ EV_SDMMC2 = 1, ++ EV_SDMMC3 = 2, ++ ++} SlotEmType; ++ ++typedef enum ++{ ++ EV_MUTEX1 = 0, ++ EV_MUTEX2 = 1, ++ EV_MUTEX3 = 2, ++ EV_NOMUTEX = 3, ++ ++} MutexEmType; ++ ++struct ms_sdmmc_host ++{ ++ struct platform_device *pdev; ++ struct ms_sdmmc_slot *sdmmc_slot[3]; ++}; ++ ++struct ms_sdmmc_slot ++{ ++ struct mmc_host *mmc; ++ ++ unsigned int slotNo; //Slot No. ++ unsigned int mieIRQNo; //MIE IRQ No. ++ unsigned int cdzIRQNo; //CDZ IRQ No. ++ unsigned int pwrGPIONo; //PWR GPIO No. ++ unsigned int pmrsaveClk; //Power Saving Clock ++ ++ unsigned int initFlag; //First Time Init Flag ++ unsigned int sdioFlag; //SDIO Device Flag ++ ++ unsigned int currClk; //Current Clock ++ unsigned int currRealClk; //Current Real Clock ++ unsigned char currWidth; //Current Bus Width ++ unsigned char currTiming; //Current Bus Timning ++ unsigned char currPowrMode; //Current PowerMode ++ unsigned char currBusMode; //Current Bus Mode ++ unsigned short currVdd; //Current Vdd ++ unsigned char currDDR; //Current DDR ++ unsigned char currTimeoutCnt; //Current Timeout Count ++ ++ int read_only; //WP ++ int card_det; //Card Detect ++ ++ /****** DMA buffer used for transmitting *******/ ++ u32 *dma_buffer; ++ dma_addr_t dma_phy_addr; ++ ++ /****** ADMA buffer used for transmitting *******/ ++ u32 *adma_buffer; ++ dma_addr_t adma_phy_addr; ++ ++ /***** Tasklet for hotplug ******/ ++ struct tasklet_struct hotplug_tasklet; ++ ++}; /* struct ms_sdmmc_hot*/ ++ ++ ++#endif // End of __MS_SDMMC_LNX_H ++ +diff --git a/drivers/sstar/sdmmc/ms_sdmmc_lnx.c b/drivers/sstar/sdmmc/ms_sdmmc_lnx.c +new file mode 100755 +index 000000000000..5a80d210f3d5 +--- /dev/null ++++ b/drivers/sstar/sdmmc/ms_sdmmc_lnx.c +@@ -0,0 +1,2209 @@ ++/* ++* ms_sdmmc_lnx.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName ms_sdmmc_lnx.c ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This layer between Linux SD Driver layer and IP Hal layer. ++ * (1) The goal is we don't need to change any Linux SD Driver code, but we can handle here. ++ * (2) You could define Function/Ver option for using, but don't add Project option here. ++ * (3) You could use function option by Project option, but please add to ms_sdmmc.h ++ * ++ ***************************************************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "inc/ms_sdmmc_lnx.h" ++#include "inc/hal_card_timer.h" ++#include "inc/hal_card_platform.h" ++ ++#include "inc/hal_sdmmc_v5.h" ++#include "inc/hal_card_intr_v5.h" ++ ++#include "mdrv_padmux.h" ++ ++#ifdef CONFIG_CAM_CLK ++#include "drv_camclk_Api.h" ++#endif ++ ++//########################################################################################################### ++#if (EN_MSYS_REQ_DMEM) ++//########################################################################################################### ++#include "../include/ms_msys.h" ++//########################################################################################################### ++#endif ++ ++ ++#if defined(CONFIG_OF) ++#include ++#include ++#include ++#include ++#endif ++ ++#define FORCE_HAL_CLK (1) //Set 1 to use HAL driver rather than DTB. Turn this on for debugging. ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++#define EN_SDMMC_TRFUNC (FALSE) ++#define EN_SDMMC_TRSDIO (FALSE) ++#define EN_SDMMC_BRO_DMA (TRUE) ++#define EN_SDMMC_DCACHE_FLUSH (TRUE) ++ ++#define EN_SDMMC_NOCDZ_NDERR (FALSE) ++ ++/****** For Allocation buffer *******/ ++#define MAX_BLK_SIZE 512 //Maximum Transfer Block Size ++#define MAX_BLK_COUNT 1024 //Maximum Transfer Block Count ++#define MAX_SEG_CNT 128 ++ ++/****** For broken DMA *******/ ++#define MAX_BRO_BLK_COUNT 1024 //Maximum Broken DMA Transfer Block Count ++ ++/****** For SD Debounce Setting *******/ ++#define WT_DB_PLUG 30 //Waiting time for Insert Debounce ++#define WT_DB_UNPLUG 30 //Waiting time for Unplug Debounce ++#define WT_DB_SW_PLUG 300 //Waiting time for Plug Delay Process ++#define WT_DB_SW_UNPLUG 0 //Waiting time for Uplug Delay Process ++ ++//*********************************************************************************************************** ++ ++// DTS related ++static U8_T gu8_SlotNums = 0; ++static BOOL_T gb_ReverseCDZ = FALSE; ++static IpOrder ge_IPOrderSlot[3] = {IP_ORDER_0, IP_ORDER_1, IP_ORDER_2}; ++static PadOrder ge_PADOrderSlot[3] = {PAD_ORDER_0, PAD_ORDER_1, PAD_ORDER_2}; ++static U32_T gu32_MaxClkSlot[3] = {400000, 400000, 400000}; ++static BOOL_T gb_IntCDZSlot[3] = {FALSE, FALSE, FALSE}; ++static BOOL_T gb_FakeCDZSlot[3] = {FALSE, FALSE, FALSE}; ++static U32_T gu32_CdzNoSlot[3] = {DEF_CDZ_PAD_SLOT0, DEF_CDZ_PAD_SLOT1, DEF_CDZ_PAD_SLOT2}; ++static U32_T gu32_PwrNoSlot[3] = {DEF_PWR_PAD_SLOT0, DEF_PWR_PAD_SLOT1, DEF_PWR_PAD_SLOT2}; ++static U32_T gu32_PwrOffDelaySlot[3] = {WT_POWEROFF, WT_POWEROFF, WT_POWEROFF}; ++static BOOL_T gb_SdioUseSlot[3] = {FALSE, FALSE, FALSE}; ++static BOOL_T gb_RemovableSlot[3] = {FALSE, FALSE, FALSE}; ++static U16_T gu16_MieIntNoSlot[3] = {0}; ++static U16_T gu16_CdzIntNoSlot[3] = {0}; ++ ++#ifdef CONFIG_PM_SLEEP ++static U16_T gu16_SlotIPClk[3] = {0}; ++static U16_T gu16_SlotBlockClk[3] = {0}; ++#endif ++ ++static const char gu8_mie_irq_name[3][20] = {"mie0_irq", "mie1_irq", "mie2_irq"}; ++static const char gu8_irq_name[3][20] = {"cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"}; ++ ++// ++static MutexEmType ge_MutexSlot[3] = {EV_MUTEX1, EV_MUTEX2, EV_MUTEX3}; ++ ++static IntSourceStruct gst_IntSourceSlot[3]; ++static spinlock_t g_RegLockSlot[3]; ++ ++static volatile IpType geIpTypeIp[3] = {IP_0_TYPE, IP_1_TYPE, IP_2_TYPE}; ++ ++#if defined(CONFIG_OF) ++ ++#ifdef CONFIG_CAM_CLK ++void* gp_clkSlot[3] = {NULL}; ++#else ++struct clk* gp_clkSlot[3]; ++#endif ++ ++#endif ++ ++ ++// Global Variable for All Slot: ++//----------------------------------------------------------------------------------------------------------- ++static volatile BOOL_T gb_RejectSuspend = (FALSE); ++ ++DEFINE_MUTEX(sdmmc1_mutex); ++DEFINE_MUTEX(sdmmc2_mutex); ++DEFINE_MUTEX(sdmmc3_mutex); ++ ++// String Name ++//----------------------------------------------------------------------------------------------------------- ++#define DRIVER_NAME "ms_sdmmc" ++#define DRIVER_DESC "Mstar SD/MMC Card Interface driver" ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_SDMMC_TRFUNC) ++ #define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ #define pr_sd_main(fmt, arg...) printk(fmt, ##arg) ++ #define pr_sd_dbg(fmt, arg...) //printk(fmt, ##arg) ++#else ++ #define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ #define pr_sd_main(fmt, arg...) //printk(fmt, ##arg) ++ #define pr_sd_dbg(fmt, arg...) //printk(fmt, ##arg) ++#endif ++ ++#if (EN_SDMMC_TRSDIO) ++ #define pr_sdio_main(fmt, arg...) printk(fmt, ##arg) ++#else ++ #define pr_sdio_main(fmt, arg...) ++#endif ++ ++ ++ ++void Hal_CARD_SetGPIOIntAttr(GPIOOptEmType eGPIOOPT, unsigned int irq) ++{ ++#if (D_OS == D_OS__LINUX) ++ if(eGPIOOPT==EV_GPIO_OPT1) //clear interrupt ++ { ++ struct irq_data *sd_irqdata = irq_get_irq_data(irq); ++ struct irq_chip *chip = irq_get_chip(irq); ++ ++ chip->irq_ack(sd_irqdata); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) //sd polarity _HI Trig for remove ++ { ++ irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) //sd polarity _LO Trig for insert ++ { ++ irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); ++ } ++#endif ++} ++ ++// Section Process Begin ++//------------------------------------------------------------------------------------------------ ++static void _CRIT_SECT_BEGIN(SlotEmType eSlot) ++{ ++ MutexEmType eMutex = ge_MutexSlot[eSlot]; ++ ++ if(eMutex == EV_MUTEX1) ++ mutex_lock(&sdmmc1_mutex); ++ else if(eMutex == EV_MUTEX2) ++ mutex_lock(&sdmmc2_mutex); ++ else if(eMutex == EV_MUTEX3) ++ mutex_lock(&sdmmc3_mutex); ++} ++ ++ ++// Section Process End ++//------------------------------------------------------------------------------------------------ ++static void _CRIT_SECT_END(SlotEmType eSlot) ++{ ++ MutexEmType eMutex = ge_MutexSlot[eSlot]; ++ ++ if(eMutex == EV_MUTEX1) ++ mutex_unlock(&sdmmc1_mutex); ++ else if(eMutex == EV_MUTEX2) ++ mutex_unlock(&sdmmc2_mutex); ++ else if(eMutex == EV_MUTEX3) ++ mutex_unlock(&sdmmc3_mutex); ++ ++} ++ ++ ++// Switch PAD ++//------------------------------------------------------------------------------------------------ ++static void _SwitchPAD(SlotEmType eSlot) ++{ ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ PadOrder ePAD = ge_PADOrderSlot[eSlot]; ++ U32_T nPwrPadNum = gu32_PwrNoSlot[eSlot]; ++ U32_T nCdzPadNum = gu32_CdzNoSlot[eSlot]; ++ BOOL_T bIsFakeCdz = gb_FakeCDZSlot[eSlot]; ++ ++ Hal_CARD_ConfigSdPad(eIP, ePAD); ++ Hal_CARD_ConfigPowerPad(eIP, (U16_T)nPwrPadNum); ++ if (!bIsFakeCdz) ++ { ++ Hal_CARD_ConfigCdzPad(eIP, nCdzPadNum); ++ } ++ Hal_CARD_InitPADPin(eIP, ePAD); ++} ++ ++// Set Power ++//------------------------------------------------------------------------------------------------ ++static void _SetPower(SlotEmType eSlot, U8_T u8PowerMode) ++{ ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ PadOrder ePAD = ge_PADOrderSlot[eSlot]; ++ ++ if(u8PowerMode == MMC_POWER_OFF) ++ { ++ // ++ Hal_SDMMC_ClkCtrl(eIP, FALSE, 0); ++ ++ // ++ Hal_CARD_PowerOff(eIP, 0); ++ ++ // ++ Hal_CARD_PullPADPin(eIP, ePAD, EV_PULLDOWN); ++ ++ // ++ Hal_Timer_mSleep(gu32_PwrOffDelaySlot[eSlot]); ++ } ++ else if(u8PowerMode == MMC_POWER_UP) ++ { ++ // ++ Hal_CARD_PowerOn(eIP, 0); ++ ++ Hal_Timer_uDelay(10); // For power-up waveform looks fine. ++ Hal_CARD_PullPADPin(eIP, ePAD, EV_PULLUP); ++ ++ // ++ Hal_Timer_mSleep(WT_POWERUP); ++ } ++ else if(u8PowerMode == MMC_POWER_ON) ++ { ++ // ++ Hal_SDMMC_ClkCtrl(eIP, TRUE, 0); ++ Hal_SDMMC_Reset(eIP); ++ ++ // ++ Hal_Timer_mSleep(WT_POWERON); ++ } ++} ++ ++ ++//------------------------------------------------------------------------------------------------ ++static U32_T _SetClock(SlotEmType eSlot, unsigned int u32ReffClk) ++{ ++ U32_T u32RealClk =0 ; ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ ++ if(u32ReffClk) ++ { ++ u32RealClk = Hal_CARD_FindClockSetting(eIP, (U32_T)u32ReffClk); ++ ++ Hal_SDMMC_ClkCtrl(eIP, FALSE, 0); // disable clock first to avoid unexpected clock rate output ++ #if (!FORCE_HAL_CLK) && (defined(CONFIG_OF)) ++ #ifdef CONFIG_CAM_CLK ++ // ++ #else ++ clk_set_rate(gp_clkSlot[eSlot], u32RealClk); ++ #endif ++ #else ++ Hal_CARD_SetClock(eIP, u32RealClk); ++ #endif ++ Hal_SDMMC_ClkCtrl(eIP, TRUE, 0); // enable clock ++ ++ Hal_SDMMC_SetNrcDelay(eIP, u32RealClk); ++ } ++ ++ return u32RealClk; ++} ++ ++ ++//------------------------------------------------------------------------------------------------ ++static void _SetBusWidth(SlotEmType eSlot, U8_T u8BusWidth) ++{ ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ ++ switch(u8BusWidth) ++ { ++ case MMC_BUS_WIDTH_1: ++ Hal_SDMMC_SetDataWidth(eIP, EV_BUS_1BIT); ++ break; ++ case MMC_BUS_WIDTH_4: ++ Hal_SDMMC_SetDataWidth(eIP, EV_BUS_4BITS); ++ break; ++ case MMC_BUS_WIDTH_8: ++ Hal_SDMMC_SetDataWidth(eIP, EV_BUS_8BITS); ++ break; ++ } ++} ++ ++ ++//------------------------------------------------------------------------------------------------ ++static void _SetBusTiming(SlotEmType eSlot, U8_T u8BusTiming) ++{ ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ ++ switch(u8BusTiming) ++ { ++ case MMC_TIMING_UHS_SDR12: ++ case MMC_TIMING_LEGACY: ++ /****** For Default Speed ******/ ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_DEF); ++ break; ++ ++ case MMC_TIMING_UHS_SDR25: ++ case MMC_TIMING_SD_HS: ++ case MMC_TIMING_MMC_HS: ++ case MMC_TIMING_UHS_SDR50: ++ case MMC_TIMING_UHS_SDR104: ++ case MMC_TIMING_MMC_HS200: ++ /****** For High Speed ******/ ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_HS); ++ break; ++ ++ case MMC_TIMING_UHS_DDR50: ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_DDR50); ++ break; ++ ++ default: ++ /****** For 300KHz IP Issue but not for Default Speed ******/ ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_LOW); ++ break; ++ } ++} ++ ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _GetCardDetect(SlotEmType eSlot) ++{ ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ ++ if (gb_FakeCDZSlot[eSlot]) ++ { ++ return (TRUE); ++ } ++ else ++ { ++ if (gb_ReverseCDZ) ++ return !Hal_CARD_GetCdzState(eIP); ++ else ++ return Hal_CARD_GetCdzState(eIP); ++ } ++ ++ return (FALSE); ++} ++ ++static BOOL_T _GetWriteProtect(SlotEmType eSlot) ++{ ++ return FALSE; ++} ++ ++static BOOL_T _CardDetect_PlugDebounce(SlotEmType eSlot, U32_T u32WaitMs, BOOL_T bPrePlugStatus) ++{ ++ BOOL_T bCurrPlugStatus = bPrePlugStatus; ++ U32_T u32DiffTime = 0; ++ ++ while(u32DiffTime < u32WaitMs) ++ { ++ mdelay(1); ++ u32DiffTime++; ++ ++ bCurrPlugStatus = _GetCardDetect(eSlot); ++ ++ if (bPrePlugStatus != bCurrPlugStatus) ++ { ++ /****** Print the Debounce ******/ ++ /*if(bPrePlugStatus) ++ printk("#"); ++ else ++ printk("$");*/ ++ /*********************************/ ++ break; ++ } ++ } ++ return bCurrPlugStatus; ++} ++ ++//------------------------------------------------------------------------------------------------ ++static U16_T _PreDataBufferProcess(TransEmType eTransType, struct mmc_data *data, struct ms_sdmmc_slot *sdmmchost, volatile U32_T *pu32AddrArr) ++{ ++ struct scatterlist *p_sg = 0; ++ U8_T u8Dir = ( (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE ); ++ U16_T u16sg_idx = 0; ++#if (!EN_SDMMC_BRO_DMA) ++ U32_T *pSGbuf = 0; ++ U32_T u32TranBytes = 0; ++ U32_T u32TotalSize = data->blksz * data->blocks; ++ unsigned *pDMAbuf = sdmmchost->dma_buffer; ++ ++#else ++ U16_T u16SubBCnt = 0; ++ U32_T u32SubLen = 0; ++ BOOL_T bEnd = (FALSE); ++ unsigned *pADMAbuf = sdmmchost->adma_buffer; ++ U8_T u8MIUSel = 0; ++ ++#endif ++ ++ if(eTransType == EV_CIF) ++ { ++ p_sg = &data->sg[0]; ++ pu32AddrArr[0] = (U32_T)( page_address(sg_page(p_sg)) + p_sg->offset ); ++ return 1; ++ } ++ ++#if (EN_SDMMC_BRO_DMA) ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++#else ++ if(data->sg_len==1) ++#endif ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ ++ // dma_map_page will flush cache in DMA_TO_DEVICE or invalidate cache in DMA_FROM_DEVICE. (only L1,L2) ++ p_sg->dma_address = dma_map_page(NULL, sg_page(p_sg), p_sg->offset, p_sg->length, u8Dir); ++ ++ if(dma_mapping_error(NULL, p_sg->dma_address)) //Add to avoid unmap warning! ++ return 0; ++ ++ if((p_sg->dma_address==0) || (p_sg->dma_address==~0)) //Mapping Error! ++ return 0; ++ ++ pu32AddrArr[u16sg_idx] = (U32_T)p_sg->dma_address; ++ } ++ ++#if (EN_SDMMC_BRO_DMA) ++ if (eTransType == EV_ADMA) ++ { ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++ { ++ if( u16sg_idx==((data->sg_len)-1) ) ++ bEnd = (TRUE); ++ ++ u32SubLen = data->sg[u16sg_idx].length; ++ u16SubBCnt = (U16_T)(u32SubLen/data->blksz); ++ Hal_SDMMC_ADMASetting((volatile void *)pADMAbuf, u16sg_idx, u32SubLen, u16SubBCnt, Hal_CARD_TransMIUAddr((U32_T)pu32AddrArr[u16sg_idx], &u8MIUSel), u8MIUSel, bEnd); ++ } ++ ++ // Flush L3 ++ // 1. For sg_buffer DMA_TO_DEVICE. ++ // 2. For sg_buffer DMA_FROM_DEVICE(invalidate L1,L2 is not enough). ++ // 3. For ADMA descriptor(non-cache). ++ Chip_Flush_MIU_Pipe(); ++ ++ pu32AddrArr[0] = (U32_T) sdmmchost->adma_phy_addr; ++ return 1; ++ } ++ else { ++ ++ // Flush L3 ++ // 1. For sg_buffer DMA_TO_DEVICE. ++ // 2. For sg_buffer DMA_FROM_DEVICE(invalidate L1,L2 is not enough). ++ Chip_Flush_MIU_Pipe(); ++ ++ return (U16_T)data->sg_len; ++ } ++#else ++ else ++ { ++ if(data->flags & MMC_DATA_WRITE) //SGbuf => DMA buf ++ { ++ while(u16sg_idx < data->sg_len) ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ ++ pSGbuf = kmap_atomic(sg_page(p_sg), KM_BIO_SRC_IRQ) + p_sg->offset; ++ u32TranBytes = min(u32TotalSize, p_sg->length); ++ memcpy(pDMAbuf, pSGbuf, u32TranBytes); ++ u32TotalSize -= u32TranBytes; ++ pDMAbuf += (u32TranBytes >> 2) ; ++ kunmap_atomic(pSGbuf, KM_BIO_SRC_IRQ); ++ ++ u16sg_idx++; ++ } ++ } ++ ++ // Flush L3 ++ // 1. For sg_buffer DMA_TO_DEVICE. ++ // 2. For sg_buffer DMA_FROM_DEVICE(invalidate L1,L2 is not enough). ++ Chip_Flush_MIU_Pipe(); ++ ++ pu32AddrArr[0] = (U32_T) sdmmchost->dma_phy_addr; ++ } ++ ++ return 1; ++ ++#endif ++ ++} ++//------------------------------------------------------------------------------------------------ ++static void _PostDataBufferProcess(TransEmType eTransType, struct mmc_data *data, struct ms_sdmmc_slot *sdmmchost) ++{ ++ struct scatterlist *p_sg = 0; ++ U8_T u8Dir = ( (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE ); ++ U16_T u16sg_idx = 0; ++ ++#if (!EN_SDMMC_BRO_DMA) ++ U32_T *pSGbuf = 0; ++ U32_T u32TranBytes = 0; ++ U32_T u32TotalSize = data->blksz * data->blocks; ++ unsigned *pDMAbuf = sdmmchost->dma_buffer; ++#endif ++ ++ if(eTransType == EV_CIF) ++ return; ++ ++ ++#if (EN_SDMMC_BRO_DMA) ++ ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ dma_unmap_page(NULL, p_sg->dma_address, p_sg->length, u8Dir); ++ } ++ ++#else ++ ++ if(data->sg_len==1) ++ { ++ p_sg = &data->sg[0]; ++ dma_unmap_page(NULL, p_sg->dma_address, p_sg->length, u8Dir); ++ } ++ else ++ { ++ if(data->flags & MMC_DATA_READ) //SGbuf => DMA buf ++ { ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ ++ pSGbuf = kmap_atomic(sg_page(p_sg), KM_BIO_SRC_IRQ) + p_sg->offset; ++ u32TranBytes = min(u32TotalSize, p_sg->length); ++ memcpy(pSGbuf, pDMAbuf, u32TranBytes); ++ u32TotalSize -= u32TranBytes; ++ pDMAbuf += (u32TranBytes >> 2) ; ++ ++ kunmap_atomic(pSGbuf, KM_BIO_SRC_IRQ); ++ } ++ } ++ } ++ ++#endif ++ ++} ++ ++//------------------------------------------------------------------------------------------------ ++static U32_T _TransArrToUInt(U8_T u8Sep1, U8_T u8Sep2, U8_T u8Sep3, U8_T u8Sep4) ++{ ++ return ((((uint)u8Sep1)<<24) | (((uint)u8Sep2)<<16) | (((uint)u8Sep3)<<8) | ((uint)u8Sep4)); ++} ++//------------------------------------------------------------------------------------------------ ++static SDMMCRspEmType _TransRspType(unsigned int u32Rsp) ++{ ++ ++ switch(u32Rsp) ++ { ++ case MMC_RSP_NONE: ++ return EV_NO; ++ case MMC_RSP_R1: ++ //case MMC_RSP_R5: ++ //case MMC_RSP_R6: ++ //case MMC_RSP_R7: ++ return EV_R1; ++ case MMC_RSP_R1B: ++ return EV_R1B; ++ case MMC_RSP_R2: ++ return EV_R2; ++ case MMC_RSP_R3: ++ //case MMC_RSP_R4: ++ return EV_R3; ++ default: ++ return EV_R1; ++ } ++} ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _PassPrintCMD(SlotEmType eSlot, U8_T u32Cmd, U32_T u32Arg, BOOL_T bSDIODev) ++{ ++ ++ if( (u32Cmd == SD_IO_RW_DIRECT) && bSDIODev) ++ return (FALSE); ++ ++ ++ if (gb_SdioUseSlot[eSlot]) ++ { ++ if(u32Cmd == SD_SEND_IF_COND) ++ { ++ return (TRUE); ++ } ++ else if(u32Cmd == SD_IO_RW_DIRECT) ++ { ++ if( (u32Arg == 0x00000C00) || (u32Arg == 0x80000C08)) ++ return (TRUE); ++ } ++ return (FALSE); ++ } ++ ++ // SD Use ++ switch(u32Cmd) ++ { ++ case MMC_SEND_OP_COND: //MMC =>Cmd_1 ++ case SD_IO_SEND_OP_COND: //SDIO =>Cmd_5 ++ case SD_SEND_IF_COND: //SD =>Cmd_8 ++ case SD_IO_RW_DIRECT: //SDIO =>Cmd_52 ++ case MMC_SEND_STATUS: //SD =>CMD13 ++ case MMC_APP_CMD: //SD =>Cmd55 ++ return (TRUE); ++ break; ++ ++ } ++ ++ return (FALSE); ++ ++} ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _IsAdmaMode(SlotEmType eSlot) ++{ ++ return (gb_SdioUseSlot[eSlot])? FALSE: TRUE; ++} ++//------------------------------------------------------------------------------------------------ ++static int _RequestEndProcess(CmdEmType eCmdType, RspErrEmType eErrType, struct ms_sdmmc_slot *p_sdmmc_slot, struct mmc_data *data) ++{ ++ int nErr = 0; ++ ErrGrpEmType eErrGrp; ++ ++ if( eErrType == EV_STS_OK ) ++ { ++ pr_sdio_main("_[%01X]", Hal_SDMMC_GetDATBusLevel(ge_IPOrderSlot[p_sdmmc_slot->slotNo])); ++ pr_sd_main("@\n"); ++ } ++ else ++ { ++ pr_sd_main("=> (Err: 0x%04X)", (U16_T)eErrType); ++ nErr = (U32_T) eErrType; ++ ++ if(eCmdType != EV_CMDRSP) ++ { ++ eErrGrp = Hal_SDMMC_ErrGroup(eErrType); ++ ++ switch((U16_T)eErrGrp) ++ { ++ case EV_EGRP_TOUT: ++ nErr = -ETIMEDOUT; ++ break; ++ ++ case EV_EGRP_COMM: ++ nErr = -EILSEQ; ++ break; ++ } ++ } ++ } ++ ++ if( eErrType == EV_STS_OK ) ++ return nErr; ++ ++ ++ /****** (2) Special Error Process for Stop Wait Process ******/ ++ if(eErrType == EV_SWPROC_ERR && data && EN_SDMMC_NOCDZ_NDERR) ++ { ++ data->bytes_xfered = data->blksz * data->blocks; ++ nErr = 0; ++ pr_sd_main("_Pass"); ++ } ++ ++ pr_sd_main("\n"); ++ ++ return nErr; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_cdzint ++ * @author jeremy.wang (2012/5/8) ++ * Desc: Int funtion for GPIO Card Detection ++ * ++ * @param irq : ++ * @param p_dev_id : ++ * ++ * @return irqreturn_t : ++ ----------------------------------------------------------------------------------------------------------*/ ++static irqreturn_t ms_sdmmc_cdzint(int irq, void *p_dev_id) ++{ ++ irqreturn_t irq_t = IRQ_NONE; ++ IntSourceStruct* pstIntSource = p_dev_id; ++ struct ms_sdmmc_slot *p_sdmmc_slot = pstIntSource->p_data; ++ ++ // ++ disable_irq_nosync(irq); ++ ++ // ++ tasklet_schedule(&p_sdmmc_slot->hotplug_tasklet); ++ irq_t = IRQ_HANDLED; ++ ++ return irq_t; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_hotplug ++ * @author jeremy.wang (2012/1/5) ++ * Desc: Hotplug function for Card Detection ++ * ++ * @param data : ms_sdmmc_slot struct pointer ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_hotplug(unsigned long data) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = (struct ms_sdmmc_slot *) data; ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ GPIOOptEmType eINSOPT = EV_GPIO_OPT3; ++ GPIOOptEmType eEJTOPT = EV_GPIO_OPT4; ++ ++ ++ if (gb_ReverseCDZ) ++ { ++ eINSOPT = EV_GPIO_OPT4; ++ eEJTOPT = EV_GPIO_OPT3; ++ } ++ ++ ++ pr_sd_dbg("\n>> [sdmmc_%u] CDZ... ", eSlot); ++ ++LABEL_LOOP_HOTPLUG: ++ ++ if( _GetCardDetect(eSlot) ) // Insert (CDZ) ++ { ++ if( (FALSE) == _CardDetect_PlugDebounce(eSlot, WT_DB_PLUG, TRUE) ) ++ goto LABEL_LOOP_HOTPLUG; ++ ++ mmc_detect_change(p_sdmmc_slot->mmc, msecs_to_jiffies(WT_DB_SW_PLUG)); ++ pr_sd_dbg("(INS) OK!\n"); ++ ++ Hal_CARD_SetGPIOIntAttr(EV_GPIO_OPT1, p_sdmmc_slot->cdzIRQNo); ++ Hal_CARD_SetGPIOIntAttr(eINSOPT, p_sdmmc_slot->cdzIRQNo); ++ ++ ++ } ++ else // Remove (CDZ) ++ { ++ if( (TRUE) == _CardDetect_PlugDebounce(eSlot, WT_DB_UNPLUG, FALSE) ) ++ goto LABEL_LOOP_HOTPLUG; ++ ++ if (p_sdmmc_slot->mmc->card) ++ mmc_card_set_removed(p_sdmmc_slot->mmc->card); ++ ++ Hal_SDMMC_StopProcessCtrl(eIP, TRUE); ++ mmc_detect_change(p_sdmmc_slot->mmc, msecs_to_jiffies(WT_DB_SW_UNPLUG)); ++ pr_sd_dbg("(EJT) OK!\n"); ++ ++ Hal_CARD_SetGPIOIntAttr(EV_GPIO_OPT1, p_sdmmc_slot->cdzIRQNo); ++ Hal_CARD_SetGPIOIntAttr(eEJTOPT, p_sdmmc_slot->cdzIRQNo); ++ ++ } ++ ++ enable_irq(p_sdmmc_slot->cdzIRQNo); ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_request ++ * @author jeremy.wang (2011/5/19) ++ * Desc: Request funciton for any commmand ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * @param p_mmc_req : mmc_request structure pointer ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_request(struct mmc_host *p_mmc_host, struct mmc_request *p_mmc_req) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ struct mmc_command *cmd = p_mmc_req->cmd; ++ struct mmc_command *stop = p_mmc_req->stop; ++ struct mmc_data *data = p_mmc_req->data; ++ ++ RspStruct * eRspSt; ++ RspErrEmType eErr = EV_STS_OK; ++ CmdEmType eCmdType = EV_CMDRSP; ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ #if (EN_SDMMC_BRO_DMA) ++ TransEmType eTransType = (_IsAdmaMode(eSlot)) ? EV_ADMA : EV_DMA; ++ #else ++ TransEmType eTransType = EV_DMA; ++ #endif ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ volatile U32_T au32Addr[MAX_SEG_CNT]; ++ ++ BOOL_T bCloseClock = FALSE; ++ U8_T u8CMD = 0; ++ U16_T u16BlkSize = 0, u16BlkCnt = 0, u16SubBlkCnt = 0; ++ U16_T u16ProcCnt = 0, u16Idx= 0; ++ U32_T u32Arg = 0, u32SubLen = 0; ++ _CRIT_SECT_BEGIN(eSlot); ++ ++ u8CMD =(U8_T)cmd->opcode; ++ u32Arg = (U32_T)cmd->arg; ++ ++ if(!p_sdmmc_slot->mmc->card) ++ Hal_SDMMC_StopProcessCtrl(eIP, FALSE); ++ ++#if (!FORCE_HAL_CLK) && (defined(CONFIG_OF)) ++ ++#ifdef CONFIG_CAM_CLK ++ // ++#else ++ clk_set_rate(gp_clkSlot[eSlot], p_sdmmc_slot->currRealClk); ++#endif ++ ++#else ++ Hal_CARD_SetClock(eIP, p_sdmmc_slot->currRealClk); ++#endif ++ ++ pr_sdio_main("_[%01X]_", Hal_SDMMC_GetDATBusLevel(eIP)); ++ pr_sd_main(">> [sdmmc_%u] CMD_%u (0x%08X)", eSlot, u8CMD, u32Arg); ++ ++ Hal_SDMMC_SetCmdToken(eIP, u8CMD, u32Arg); ++ /****** Simple SD command *******/ ++ if(!data) ++ { ++ Hal_SDMMC_SetSDIOIntBeginSetting(eIP, u8CMD, u32Arg, EV_CMDRSP, 0); ++ eErr = Hal_SDMMC_SendCmdAndWaitProcess(eIP, EV_EMP, EV_CMDRSP, _TransRspType(mmc_resp_type(cmd)), TRUE); ++ Hal_SDMMC_SetSDIOIntEndSetting(eIP, eErr, 0); ++ } ++ else // R/W SD Command ++ { ++ u16BlkSize = (U16_T)data->blksz; ++ u16BlkCnt = (U16_T)data->blocks; ++ u32SubLen = (U32_T) data->sg[0].length; ++ u16SubBlkCnt = (U16_T)(u32SubLen/u16BlkSize); ++ ++ eCmdType = ( (data->flags & MMC_DATA_READ) ? EV_CMDREAD : EV_CMDWRITE ); ++ bCloseClock = ( (stop) ? FALSE : TRUE ); ++ ++ pr_sd_main("__[Sgl: %u] (TB: %u)(BSz: %u)", (U16_T)data->sg_len, u16BlkCnt, u16BlkSize); ++ ++ u16ProcCnt = _PreDataBufferProcess(eTransType, data, p_sdmmc_slot, au32Addr); ++ if(u16ProcCnt==0) ++ { ++ pr_err("\n>> [sdmmc_%u] Err: DMA Mapping Addr Error!\n", eSlot); ++ eErr = EV_OTHER_ERR; ++ goto LABEL_SD_ERR; ++ } ++ else if(u16ProcCnt==1) ++ { ++ u32SubLen = u16BlkSize * u16BlkCnt; ++ u16SubBlkCnt = u16BlkCnt; ++ } ++ ++ pr_sd_dbg("\n____[0] =>> (SBCnt: %u)__[Addr: 0x%08X]", u16SubBlkCnt, au32Addr[0]); ++ ++ Hal_SDMMC_TransCmdSetting(eIP, eTransType, u16SubBlkCnt, u16BlkSize, Hal_CARD_TransMIUAddr(au32Addr[0], NULL), (volatile U8_T*)au32Addr[0]); ++ Hal_SDMMC_SetSDIOIntBeginSetting(eIP, u8CMD, u32Arg, eCmdType, u16BlkCnt); ++ eErr = Hal_SDMMC_SendCmdAndWaitProcess(eIP, eTransType, eCmdType, _TransRspType(mmc_resp_type(cmd)), bCloseClock); ++ ++ ++ if( ((U16_T)eErr) == EV_STS_OK ) ++ { ++ data->bytes_xfered += u32SubLen; ++ ++ /****** Broken DMA *******/ ++ for(u16Idx=1 ; u16Idxsg[u16Idx].length; ++ u16SubBlkCnt = (U16_T)(u32SubLen/u16BlkSize); ++ pr_sd_dbg("\n____[%u] =>> (SBCnt: %u)__[Addr: 0x%08X]", u16Idx, u16SubBlkCnt, au32Addr[u16Idx]); ++ ++ Hal_SDMMC_TransCmdSetting(eIP, eTransType, u16SubBlkCnt, u16BlkSize, Hal_CARD_TransMIUAddr(au32Addr[u16Idx], NULL), (volatile U8_T *)au32Addr[u16Idx]); ++ eErr = Hal_SDMMC_RunBrokenDmaAndWaitProcess(eIP, eCmdType); ++ ++ if((U16_T)eErr) break; ++ data->bytes_xfered += u32SubLen; ++ } ++ } ++ ++ Hal_SDMMC_SetSDIOIntEndSetting(eIP, eErr, u16BlkCnt); ++ ++ _PostDataBufferProcess(eTransType, data, p_sdmmc_slot); ++ ++ } ++ ++LABEL_SD_ERR: ++ ++ cmd->error = _RequestEndProcess(eCmdType, eErr, p_sdmmc_slot, data); ++ ++ if(data) ++ data->error = cmd->error; ++ ++ eRspSt = Hal_SDMMC_GetRspToken(eIP); ++ cmd->resp[0] = _TransArrToUInt(eRspSt->u8ArrRspToken[1], eRspSt->u8ArrRspToken[2], eRspSt->u8ArrRspToken[3], eRspSt->u8ArrRspToken[4]); ++ if(eRspSt->u8RspSize == 0x10) ++ { ++ cmd->resp[1] = _TransArrToUInt(eRspSt->u8ArrRspToken[5], eRspSt->u8ArrRspToken[6], eRspSt->u8ArrRspToken[7], eRspSt->u8ArrRspToken[8]); ++ cmd->resp[2] = _TransArrToUInt(eRspSt->u8ArrRspToken[9], eRspSt->u8ArrRspToken[10], eRspSt->u8ArrRspToken[11], eRspSt->u8ArrRspToken[12]); ++ cmd->resp[3] = _TransArrToUInt(eRspSt->u8ArrRspToken[13], eRspSt->u8ArrRspToken[14], eRspSt->u8ArrRspToken[15], 0); ++ } ++ ++ /****** Print Error Message******/ ++ if(!data && cmd->error && !_PassPrintCMD(eSlot, u8CMD, u32Arg, (BOOL_T)p_sdmmc_slot->sdioFlag)) //Cmd Err but Pass Print Some Cmds ++ { ++ if(cmd->error == -EILSEQ) { ++ pr_sd_err(">> [sdmmc_%u] Warn: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)\n", eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine); ++ } ++ else { ++ pr_sd_err(">> [sdmmc_%u] Err: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)\n", eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine); ++ } ++ } ++ else if(data && data->error) //Data Err ++ { ++ if(data->error == -EILSEQ) { ++ pr_sd_err(">> [sdmmc_%u] Warn: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)(B:%u/%u)(I:%u/%u)\n", \ ++ eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine, u16SubBlkCnt, u16BlkCnt, u16Idx, u16ProcCnt); ++ } ++ else { ++ pr_sd_err(">> [sdmmc_%u] Err: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)(B:%u/%u)(I:%u/%u)\n", \ ++ eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine, u16SubBlkCnt, u16BlkCnt, u16Idx, u16ProcCnt); ++ } ++ } ++ ++ /****** Send Stop Cmd ******/ ++ if(stop) ++ { ++ u8CMD = (U8_T)stop->opcode; ++ u32Arg = (U32_T)stop->arg; ++ pr_sd_main(">> [sdmmc_%u]_CMD_%u (0x%08X)", eSlot, u8CMD, u32Arg); ++ ++ Hal_SDMMC_SetCmdToken(eIP, u8CMD, u32Arg); ++ Hal_SDMMC_SetSDIOIntBeginSetting(eIP, u8CMD, u32Arg, EV_CMDRSP, 0); ++ eErr = Hal_SDMMC_SendCmdAndWaitProcess(eIP, EV_EMP, EV_CMDRSP, _TransRspType(mmc_resp_type(stop)), TRUE); ++ Hal_SDMMC_SetSDIOIntEndSetting(eIP, eErr, 0); ++ ++ stop->error = _RequestEndProcess(EV_CMDRSP, eErr, p_sdmmc_slot, data); ++ ++ eRspSt = Hal_SDMMC_GetRspToken(eIP); ++ stop->resp[0] = _TransArrToUInt(eRspSt->u8ArrRspToken[1], eRspSt->u8ArrRspToken[2], eRspSt->u8ArrRspToken[3], eRspSt->u8ArrRspToken[4]); ++ ++ if(stop->error) ++ pr_sd_err(">> [sdmmc_%u] Err: #Cmd_12 => (E: 0x%04X)(S: 0x%08X)__(L:%u)\n", eSlot, (U16_T)eErr, stop->resp[0], eRspSt->u32ErrLine); ++ ++ ++ } ++ ++ //Hal_CARD_SetClock(eIP, p_sdmmc_slot->pmrsaveClk); // For Power Saving ++ ++ _CRIT_SECT_END(eSlot); ++ mmc_request_done(p_mmc_host, p_mmc_req); ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_set_ios ++ * @author jeremy.wang (2011/5/19) ++ * Desc: Set IO bus Behavior ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * @param p_mmc_ios : mmc_ios structure pointer ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_set_ios(struct mmc_host *p_mmc_host, struct mmc_ios *p_mmc_ios) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ _CRIT_SECT_BEGIN(eSlot); ++ ++ /****** Clock Setting*******/ ++ if(p_sdmmc_slot->currClk != p_mmc_ios->clock) ++ { ++/* Modified by Spade: enable clk in probe ++ #if defined(CONFIG_OF) ++ if(p_mmc_ios->clock>0) ++ clk_prepare_enable(gp_clkSlot[eSlot]); ++ else ++ clk_disable_unprepare(gp_clkSlot[eSlot]); ++ #endif ++*/ ++ p_sdmmc_slot->currClk = p_mmc_ios->clock; ++ p_sdmmc_slot->currRealClk = _SetClock(eSlot, p_sdmmc_slot->currClk); ++ ++ if( (p_sdmmc_slot->currRealClk==0) && (p_sdmmc_slot->currClk!=0) ) ++ { ++ pr_sd_err(">> [sdmmc_%u] Set IOS => Clk=Error\n", eSlot); ++ } ++ else if(p_sdmmc_slot->currRealClk <= 400000) ++ { ++ _SetBusTiming(eSlot, 0xFF); ++ } ++ else ++ { ++ pr_sd_dbg(">> [sdmmc_%u] Set IOS => Clk=%u (Real=%u)\n", eSlot, p_sdmmc_slot->currClk, p_sdmmc_slot->currRealClk); ++ } ++ } ++ ++ /****** Power Switch Setting *******/ ++ if(p_sdmmc_slot->currPowrMode != p_mmc_ios->power_mode) ++ { ++ p_sdmmc_slot->currPowrMode = p_mmc_ios->power_mode; ++ pr_sd_main(">> [sdmmc_%u] Set IOS => Power=%u\n", eSlot, p_sdmmc_slot->currPowrMode); ++ _SetPower(eSlot, p_sdmmc_slot->currPowrMode); ++ ++ if(p_sdmmc_slot->currPowrMode == MMC_POWER_OFF) ++ { ++ p_sdmmc_slot->initFlag = 0; ++ p_sdmmc_slot->sdioFlag = 0; ++ } ++ } ++ ++ /****** Bus Width Setting*******/ ++ if( (p_sdmmc_slot->currWidth != p_mmc_ios->bus_width) || !p_sdmmc_slot->initFlag) ++ { ++ p_sdmmc_slot->currWidth = p_mmc_ios->bus_width; ++ _SetBusWidth(eSlot, p_sdmmc_slot->currWidth); ++ pr_sd_main(">> [sdmmc_%u] Set IOS => BusWidth=%u\n", eSlot, p_sdmmc_slot->currWidth); ++ } ++ ++ /****** Bus Timing Setting*******/ ++ if( (p_sdmmc_slot->currTiming != p_mmc_ios->timing) || !p_sdmmc_slot->initFlag) ++ { ++ p_sdmmc_slot->currTiming = p_mmc_ios->timing; ++ _SetBusTiming(eSlot, p_sdmmc_slot->currTiming); ++ pr_sd_main(">> [sdmmc_%u] Set IOS => BusTiming=%u\n", eSlot, p_sdmmc_slot->currTiming); ++ } ++ ++#if 0 ++ /****** Voltage Setting *******/ ++ if( (p_sdmmc_slot->currVdd != p_mmc_ios->signal_voltage) || !p_sdmmc_slot->initFlag) ++ { ++ p_sdmmc_slot->currVdd = p_mmc_ios->signal_voltage; ++ ++ // set voltage function ++ } ++#endif ++ ++ p_sdmmc_slot->initFlag = 1; ++ ++ _CRIT_SECT_END(eSlot); ++ ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_get_ro ++ * @author jeremy.wang (2011/5/19) ++ * Desc: Get SD card read/write permission ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * ++ * @return int : 1 = read-only, 0 = read-write. ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_get_ro(struct mmc_host *p_mmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ _CRIT_SECT_BEGIN(eSlot); ++ ++ if( _GetWriteProtect(eSlot) ) //For CB2 HW Circuit, WP=>NWP ++ p_sdmmc_slot->read_only = 1; ++ else ++ p_sdmmc_slot->read_only = 0; ++ ++ _CRIT_SECT_END(eSlot); ++ ++ pr_sd_main(">> [sdmmc_%u] Get RO => (%d)\n", eSlot, p_sdmmc_slot->read_only); ++ ++ return p_sdmmc_slot->read_only; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_get_cd ++ * @author jeremy.wang (2011/6/17) ++ * Desc: Get SD card detection status ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * ++ * @return int : 1 = Present ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_get_cd(struct mmc_host *p_mmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ ++ if( _GetCardDetect(eSlot) ) ++ p_sdmmc_slot->card_det = 1; ++ else ++ p_sdmmc_slot->card_det = 0; ++ ++ return p_sdmmc_slot->card_det; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_init_card ++ * @author jeremy.wang (2012/2/20) ++ * Desc: ++ * ++ * @param p_mmc_host : ++ * @param p_mmc_card : ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_init_card(struct mmc_host *p_mmc_host, struct mmc_card *p_mmc_card) ++{ ++#if 0 //Modify this step to ms_sdmmc_init_slot ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ ++ Hal_SDMMC_SDIODeviceCtrl(eIP, TRUE); ++ p_sdmmc_slot->sdioFlag = 1; ++ ++ pr_sd_dbg(">> [sdmmc_%u] Found SDIO Device!\n", eSlot); ++#endif ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_enable_sdio_irq ++ * @author jeremy.wang (2012/2/20) ++ * Desc: ++ * ++ * @param p_mmc_host : ++ * @param enable : ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_enable_sdio_irq(struct mmc_host *p_mmc_host, int enable) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ ++ // Remove Original VER_04 spin lock ++ // TODO: SMP consideration!!! ++ // should add spin lock here? ++ ++ Hal_SDMMC_SDIOIntDetCtrl(eIP, (BOOL_T)enable); ++ ++ if(enable) ++ { ++ pr_sdio_main(">> [sdmmc_%u] =========> SDIO IRQ EN=> (%d)\n", eSlot, enable); ++ } ++} ++ ++/********************************************************************************************************** ++ * Define Static Global Structs ++ **********************************************************************************************************/ ++/*---------------------------------------------------------------------------------------------------------- ++ * st_mmc_ops ++ ----------------------------------------------------------------------------------------------------------*/ ++static const struct mmc_host_ops st_mmc_ops = ++{ ++ .request = ms_sdmmc_request, ++ .set_ios = ms_sdmmc_set_ios, ++ .get_ro = ms_sdmmc_get_ro, ++ .get_cd = ms_sdmmc_get_cd, ++ .init_card = ms_sdmmc_init_card, ++ .enable_sdio_irq = ms_sdmmc_enable_sdio_irq, ++}; ++ ++ ++ ++#if defined(CONFIG_OF) ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_dts_init ++ * @author jeremy.wang (2017/3/24) ++ * Desc: Device Tree Init ++ * ++ * @param p_dev : platform device ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_dts_init(struct platform_device *p_dev) ++{ ++ U8_T slotNo = 0 , ipidx = 0; ++ SlotEmType eSlot; ++ ++ U32_T u32_SlotNums = 0; ++ U32_T u32_ReverseCDZ = 0; ++ U32_T u32_IPOrderSlot[3]; ++ U32_T u32_PADOrderSlot[3]; ++ U32_T u32_MaxClkSlot[3]; ++ U32_T u32_IntCDZSlot[3]; ++ U32_T u32_FakeCDZSlot[3]; ++ U32_T u32_CdzNoSlot[3]; ++ U32_T u32_PwrNoSlot[3]; ++ U32_T u32_PwrOffDelaySlot[3]; ++ U32_T u32_SdioUseSlot[3]; ++ U32_T u32_RemovableSlot[3]; ++#ifdef CONFIG_CAM_CLK ++ U32_T SdmmcClk = 0; ++#endif ++ ++ // Get u32_SlotNums first for getting other DTS entry ! ++ if (of_property_read_u32(p_dev->dev.of_node, "slotnum" , &u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slotnum] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32(p_dev->dev.of_node, "revcdz" , &u32_ReverseCDZ)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [revcdz] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-ip-orders", (U32_T*)u32_IPOrderSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-ip-orders] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-pad-orders", (U32_T*)u32_PADOrderSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-pad-orders] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-max-clks", (U32_T*)u32_MaxClkSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-max-clks] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-intcdzs", (U32_T*)u32_IntCDZSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-intcdzs] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-fakecdzs", (U32_T*)u32_FakeCDZSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-fakecdzs] option!\n"); ++ return 1; ++ } ++ ++ if (mdrv_padmux_active() == 0) ++ { ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-cdzs-gpios", (U32_T *)u32_CdzNoSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-cdzs-gpios] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-pwr-gpios", (U32_T *)u32_PwrNoSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-pwr-gpios] option!\n"); ++ return 1; ++ } ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-pwr-off-delay", (U32_T *)u32_PwrOffDelaySlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-pwr-off-delay] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-sdio-use", (U32_T *)u32_SdioUseSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-sdio-use] option!\n"); ++ return 1; ++ } ++ ++ if (of_property_read_u32_array(p_dev->dev.of_node, "slot-removable", (U32_T *)u32_RemovableSlot, u32_SlotNums)) ++ { ++ pr_err(">> [sdmmc] Err: Could not get dts [slot-removable] option!\n"); ++ return 1; ++ } ++ ++ // ++ gu8_SlotNums = (U8_T)u32_SlotNums; ++ gb_ReverseCDZ = (BOOL_T)u32_ReverseCDZ; ++ ++ for (slotNo =0; slotNo> [sdmmc] Err: slotNo = %u, Could not get dts from Padmux dts [slot-cdzs-gpios] option!\n", slotNo); ++ return 1; ++ } ++ ++ if (Hal_CARD_GetPadInfoPowerPad((IpOrder)u32_IPOrderSlot[eSlot], &u32_PwrNoSlot[eSlot]) == 0 ) ++ { ++ pr_err(">> [sdmmc] Err: slotNo = %u, Could not get dts from Padmux dts [slot-pwr-gpios] option!\n", slotNo); ++ return 1; ++ } ++ } ++ ++ // Check conflict ++ if (u32_SdioUseSlot[eSlot] == TRUE) ++ { ++ if (geIpTypeIp[u32_IPOrderSlot[eSlot]] != IP_TYPE_SDIO) ++ { ++ pr_err(">> [sdmmc] slotNo = %u, When SDIO is used, IpType need to be IP_TYPE_SDIO, current setting = %u\n", slotNo, (U8_T)geIpTypeIp[u32_IPOrderSlot[eSlot]]); ++ return 1; ++ } ++ } ++ ++ // Transfer to Global variable ++ ge_IPOrderSlot[eSlot] = (IpOrder)u32_IPOrderSlot[eSlot]; ++ ge_PADOrderSlot[eSlot] = (PadOrder)u32_PADOrderSlot[eSlot]; ++ gu32_MaxClkSlot[eSlot] = (U32_T)u32_MaxClkSlot[eSlot]; ++ gb_IntCDZSlot[eSlot] = (BOOL_T)u32_IntCDZSlot[eSlot]; ++ gb_FakeCDZSlot[eSlot] = (BOOL_T)u32_FakeCDZSlot[eSlot]; ++ gu32_CdzNoSlot[eSlot] = (U32_T)u32_CdzNoSlot[eSlot]; ++ gu32_PwrNoSlot[eSlot] = (U32_T)u32_PwrNoSlot[eSlot]; ++ gu32_PwrOffDelaySlot[eSlot] = (U32_T)u32_PwrOffDelaySlot[eSlot]; ++ gb_SdioUseSlot[eSlot] = (BOOL_T)u32_SdioUseSlot[eSlot]; ++ gb_RemovableSlot[eSlot] = (BOOL_T)u32_RemovableSlot[eSlot]; ++ ++ // MIE irq depend on which IP ++ gu16_MieIntNoSlot[eSlot] = of_irq_get_byname(p_dev->dev.of_node, gu8_mie_irq_name[u32_IPOrderSlot[eSlot]]); ++ ++ // CDZ irq ++ gu16_CdzIntNoSlot[eSlot] = of_irq_get_byname(p_dev->dev.of_node, gu8_irq_name[slotNo]); ++ } ++ ++ //Debug ++ pr_sd_dbg(">> [sdmmc] SlotNums= %u\n", gu8_SlotNums); ++ pr_sd_dbg(">> [sdmmc] RevCDZ= %u\n", gb_ReverseCDZ); ++ pr_sd_dbg(">> [sdmmc] SlotIPs[0-2]= %u, %u, %u \n", (U8_T)ge_IPOrderSlot[0], (U8_T)ge_IPOrderSlot[1], (U8_T)ge_IPOrderSlot[2]); ++ pr_sd_dbg(">> [sdmmc] SlotPADs[0-2]= %u, %u, %u \n", (U8_T)ge_PADOrderSlot[0], (U8_T)ge_PADOrderSlot[1], (U8_T)ge_PADOrderSlot[2]); ++ pr_sd_dbg(">> [sdmmc] SlotMaxClk[0-2]= %u, %u, %u \n", gu32_MaxClkSlot[0], gu32_MaxClkSlot[1], gu32_MaxClkSlot[2]); ++ pr_sd_dbg(">> [sdmmc] IntCDZSlot[0-2]= %u, %u, %u \n", gb_IntCDZSlot[0], gb_IntCDZSlot[1], gb_IntCDZSlot[2]); ++ pr_sd_dbg(">> [sdmmc] SlotFakeCDZ[0-2]= %u, %u, %u \n", gb_FakeCDZSlot[0], gb_FakeCDZSlot[1], gb_FakeCDZSlot[2]); ++ pr_sd_dbg(">> [sdmmc] gu32_CdzNoSlot[0-2]= %u, %u, %u \n", gu32_CdzNoSlot[0], gu32_CdzNoSlot[1], gu32_CdzNoSlot[2]); ++ pr_sd_dbg(">> [sdmmc] PwrNoSlot[0-2]= %u, %u, %u \n", gu32_PwrNoSlot[0], gu32_PwrNoSlot[1], gu32_PwrNoSlot[2]); ++ pr_sd_dbg(">> [sdmmc] PwrOffDelaySlot[0-2]= %u, %u, %u \n", gu32_PwrOffDelaySlot[0], gu32_PwrOffDelaySlot[1], gu32_PwrOffDelaySlot[2]); ++ pr_sd_dbg(">> [sdmmc] gb_SdioUseSlot[0-2]= %u, %u, %u \n", gb_SdioUseSlot[0], gb_SdioUseSlot[1], gb_SdioUseSlot[2]); ++ pr_sd_dbg(">> [sdmmc] gb_RemovableSlot[0-2]= %u, %u, %u \n", gb_RemovableSlot[0], gb_RemovableSlot[1], gb_RemovableSlot[2]); ++ pr_sd_dbg(">> [sdmmc] MieIntNoSlot[0-2]= %u, %u, %u \n", gu16_MieIntNoSlot[0], gu16_MieIntNoSlot[1], gu16_MieIntNoSlot[2]); ++ pr_sd_dbg(">> [sdmmc] CdzIntNoSlot[0-2]= %u, %u, %u \n", gu16_CdzIntNoSlot[0], gu16_CdzIntNoSlot[1], gu16_CdzIntNoSlot[2]); ++ ++#ifdef CONFIG_CAM_CLK ++ // ++ for(slotNo =0; slotNodev.of_node,"camclk", ipidx, &(SdmmcClk)); ++ ++ if (!SdmmcClk) ++ { ++ //printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ pr_err(">> [sdmmc_%u] Err: Failed to get dts clock tree!\n", slotNo); ++ return 1; ++ } ++ ++ CamClkRegister("Sdmmc",SdmmcClk,&(gp_clkSlot[slotNo])); ++ CamClkSetOnOff(gp_clkSlot[slotNo], 1); ++ } ++#else ++ // ++ for(slotNo =0; slotNodev.of_node, ipidx); ++ ++ if(IS_ERR(gp_clkSlot[slotNo])) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to get dts clock tree!\n", slotNo); ++ return 1; ++ } ++ ++ clk_prepare_enable(gp_clkSlot[slotNo]); ++ } ++#endif ++ ++ return 0; ++} ++ ++#endif ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_init_slot ++ * @author jeremy.wang (2015/12/9) ++ * Desc: Init Slot Setting ++ * ++ * @param slotNo : Slot Number ++ * @param p_sdmmc_host : ms_sdmmc_host ++ * ++ * @return int : Error Status; Return 0 if no error ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_init_slot(unsigned int slotNo, struct ms_sdmmc_host *p_sdmmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot; ++ struct mmc_host *p_mmc_host; ++ SlotEmType eSlot = (SlotEmType)slotNo; ++ IpOrder eIP = ge_IPOrderSlot[eSlot]; ++ int nRet = 0; ++ ++ ++//########################################################################################################### ++#if (EN_MSYS_REQ_DMEM) ++ //########################################################################################################### ++ MSYS_DMEM_INFO mem_info; ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++ ++ /****** (1) Allocte MMC and SDMMC host ******/ ++ p_mmc_host = mmc_alloc_host(sizeof(struct ms_sdmmc_slot), &p_sdmmc_host->pdev->dev); ++ ++ if (!p_mmc_host) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate mmc_host!\n", slotNo); ++ return -ENOMEM; ++ } ++ ++ /****** (2) SDMMC host setting ******/ ++ p_sdmmc_slot = mmc_priv(p_mmc_host); ++ ++#if (!EN_SDMMC_BRO_DMA) ++ ++ //########################################################################################################### ++ #if !(EN_MSYS_REQ_DMEM) ++ //########################################################################################################### ++ p_sdmmc_slot->dma_buffer = dma_alloc_coherent(NULL, MAX_BLK_COUNT * MAX_BLK_SIZE, &p_sdmmc_slot->dma_phy_addr, GFP_KERNEL); ++ if (!p_sdmmc_slot->dma_buffer) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate sdmmc_host DMA buffer\n", slotNo); ++ return -ENOMEM; ++ } ++ //########################################################################################################### ++ #else ++ //########################################################################################################### ++ mem_info.length = MAX_BLK_COUNT * MAX_BLK_SIZE; ++ strcpy(mem_info.name, "SDMMC_SGBUF"); ++ if(msys_request_dmem(&mem_info)) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate sdmmc_host DMA buffer\n", slotNo); ++ return -ENOMEM; ++ } ++ ++ p_sdmmc_slot->dma_phy_addr = (dma_addr_t)mem_info.phys; ++ p_sdmmc_slot->dma_buffer = (U32_T*)((U32_T)mem_info.kvirt); ++ //########################################################################################################### ++ #endif ++ ++#else ++ if (_IsAdmaMode(slotNo)) { ++ //########################################################################################################### ++ #if !(EN_MSYS_REQ_DMEM) ++ //########################################################################################################### ++ p_sdmmc_slot->adma_buffer = dma_alloc_coherent(NULL, sizeof(AdmaDescStruct) * MAX_SEG_CNT, &p_sdmmc_slot->adma_phy_addr, GFP_KERNEL); ++ if (!p_sdmmc_slot->adma_buffer) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate sdmmc_host ADMA buffer\n", slotNo); ++ return -ENOMEM; ++ } ++ //########################################################################################################### ++ #else ++ //########################################################################################################### ++ mem_info.length = sizeof(AdmaDescStruct) * MAX_SEG_CNT; ++ sprintf(mem_info.name,"%s%01d","SDMMC_ADMABUF",slotNo); ++ if(msys_request_dmem(&mem_info)) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate sdmmc_host ADMA buffer\n", slotNo); ++ return -ENOMEM; ++ } ++ ++ p_sdmmc_slot->adma_phy_addr = (dma_addr_t)mem_info.phys; ++ p_sdmmc_slot->adma_buffer = (U32_T*)((U32_T)mem_info.kvirt); ++ ++ //########################################################################################################### ++ #endif ++ } ++#endif ++ ++ p_sdmmc_slot->mmc = p_mmc_host; ++ p_sdmmc_slot->slotNo = slotNo; ++ p_sdmmc_slot->pmrsaveClk = Hal_CARD_FindClockSetting(eIP, 400000); ++ p_sdmmc_slot->mieIRQNo = gu16_MieIntNoSlot[eSlot]; ++ p_sdmmc_slot->cdzIRQNo = gu16_CdzIntNoSlot[eSlot]; ++ p_sdmmc_slot->pwrGPIONo = gu32_PwrNoSlot[eSlot]; ++ p_sdmmc_slot->initFlag = 0; ++ p_sdmmc_slot->sdioFlag = 0; ++ ++ p_sdmmc_slot->currClk = 0; ++ p_sdmmc_slot->currWidth = 0; ++ p_sdmmc_slot->currTiming = 0; ++ p_sdmmc_slot->currPowrMode = MMC_POWER_OFF; ++ p_sdmmc_slot->currVdd = 0; ++ p_sdmmc_slot->currDDR = 0; ++ ++ ++ /***** (3) MMC host setting ******/ ++ p_mmc_host->ops = &st_mmc_ops; ++ p_mmc_host->f_min = p_sdmmc_slot->pmrsaveClk; ++ ++ p_mmc_host->f_max = gu32_MaxClkSlot[eSlot]; ++ ++ p_mmc_host->ocr_avail = MMC_VDD_32_33|MMC_VDD_31_32|MMC_VDD_30_31|MMC_VDD_29_30|MMC_VDD_28_29|MMC_VDD_27_28|MMC_VDD_165_195; ++ p_mmc_host->caps = MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED; ++ ++ ++ // SDIO Card is non-removable ++ if (!gb_RemovableSlot[eSlot]) ++ { ++ p_mmc_host->caps |= MMC_CAP_NONREMOVABLE; ++ } ++ ++ // CDZ int is unavailable, then just use polling mode. ++ if (!gb_IntCDZSlot[eSlot]) ++ { ++ p_mmc_host->caps |= MMC_CAP_NEEDS_POLL; ++ } ++ ++#if (EN_SDMMC_BRO_DMA) ++ p_mmc_host->max_blk_count = MAX_BRO_BLK_COUNT; ++#else ++ p_mmc_host->max_blk_count = MAX_BLK_COUNT; ++#endif ++ p_mmc_host->max_blk_size = MAX_BLK_SIZE; ++ ++ p_mmc_host->max_req_size = p_mmc_host->max_blk_count * p_mmc_host->max_blk_size; ++ p_mmc_host->max_seg_size = p_mmc_host->max_req_size; ++ ++ p_mmc_host->max_segs = MAX_SEG_CNT; ++ ++ p_sdmmc_host->sdmmc_slot[slotNo] = p_sdmmc_slot; ++ ++ /****** (4) IP Once Setting for Different Platform ******/ ++ Hal_CARD_IPOnceSetting(eIP); ++ ++ ++ /****** (5) Init GPIO Setting ******/ ++ _SwitchPAD(eSlot); ++ ++#if 0 // Not all platform's power come from sdmmc DTS, so mask it. ++ if (1) ++ { ++ nRet = gpio_request(p_sdmmc_slot->pwrGPIONo, "SD Power Pin"); ++ ++ if (nRet) ++ { ++ pr_sd_err(">> [sdmmc_%u] Err: Failed to request PWR GPIO (%u)\n", slotNo, p_sdmmc_slot->pwrGPIONo); ++ goto INIT_FAIL_2; ++ } ++ } ++#endif ++ ++ /****** (6) Interrupt Source Setting ******/ ++ gst_IntSourceSlot[eSlot].slotNo = slotNo; ++ gst_IntSourceSlot[eSlot].eIP = eIP; ++ gst_IntSourceSlot[eSlot].p_data = p_sdmmc_slot; ++ ++ /***** (7) Spinlock Init for Reg Protection ******/ ++ spin_lock_init(&g_RegLockSlot[slotNo]); ++ ++ /****** (8) Register IP IRQ *******/ ++#if(EN_BIND_CARD_INT) ++ Hal_SDMMC_MIEIntCtrl(eIP, FALSE); ++ ++#if 1 // MIE ++ nRet = request_irq(p_sdmmc_slot->mieIRQNo, Hal_CARD_INT_MIE, IRQF_TRIGGER_NONE, DRIVER_NAME "_mie", &gst_IntSourceSlot[eSlot]); ++ if (nRet) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to request MIE Interrupt (%u)!\n", slotNo, p_sdmmc_slot->mieIRQNo); ++ goto INIT_FAIL_2; ++ } ++ ++ Hal_SDMMC_MIEIntCtrl(eIP, TRUE); ++ ++ if (gb_SdioUseSlot[eSlot]) // When SDIO Card is used, we enable SDIO int. ++ { ++ p_mmc_host->caps |= MMC_CAP_SDIO_IRQ; ++ Hal_CARD_INT_SetMIEIntEn_ForSDIO(eIP, TRUE); ++ Hal_SDMMC_SDIODeviceCtrl(eIP, TRUE); ++ p_sdmmc_slot->sdioFlag = 1; ++ ++ pr_sd_dbg(">> [sdmmc_%u] Enable SDIO Interrupt Mode! \n", slotNo); ++ } ++ else ++ { ++ p_mmc_host->caps2 = MMC_CAP2_NO_SDIO; ++ Hal_SDMMC_SDIODeviceCtrl(eIP, FALSE); ++ p_sdmmc_slot->sdioFlag = 0; ++ } ++#endif ++ ++#endif ++ ++ // Don't pre power up ++ p_mmc_host->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; ++ ++ // ++ mmc_add_host(p_mmc_host); ++ ++ // CDZ IRQ ++ if (gb_IntCDZSlot[eSlot]) ++ { ++ tasklet_init(&p_sdmmc_slot->hotplug_tasklet, ms_sdmmc_hotplug, (unsigned long)p_sdmmc_slot); ++ ++ // ++ Hal_CARD_SetGPIOIntAttr((_GetCardDetect(eSlot)? EV_GPIO_OPT3 : EV_GPIO_OPT4), p_sdmmc_slot->cdzIRQNo); ++ Hal_CARD_SetGPIOIntAttr(EV_GPIO_OPT1, p_sdmmc_slot->cdzIRQNo); ++ ++ nRet = request_irq(p_sdmmc_slot->cdzIRQNo, ms_sdmmc_cdzint, IRQF_TRIGGER_NONE, DRIVER_NAME "_cdz", &gst_IntSourceSlot[eSlot]); ++ if (nRet) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to request CDZ Interrupt (%u)!\n", slotNo, p_sdmmc_slot->cdzIRQNo); ++ goto INIT_FAIL_1; ++ } ++ ++ pr_sd_dbg(">> [sdmmc_%u] Int CDZ use Ext GPIO IRQ: (%u)\n", slotNo, p_sdmmc_slot->cdzIRQNo); ++ ++ Hal_CARD_SetGPIOIntAttr( EV_GPIO_OPT2, p_sdmmc_slot->cdzIRQNo); ++ ++#if 0 // Make irq wake up system from suspend. ++ irq_set_irq_wake(p_sdmmc_slot->cdzIRQNo, TRUE); ++#endif ++ } ++ ++ // Return Success ++ return 0; ++ ++INIT_FAIL_1: ++ tasklet_kill(&p_sdmmc_slot->hotplug_tasklet); ++ free_irq(p_sdmmc_slot->mieIRQNo, &gst_IntSourceSlot[eSlot]); ++ ++ mmc_remove_host(p_mmc_host); ++ mmc_free_host(p_mmc_host); ++ ++#if(EN_BIND_CARD_INT) ++INIT_FAIL_2: ++#endif ++#if (!EN_SDMMC_BRO_DMA) ++ ++//########################################################################################################### ++#if !(EN_MSYS_REQ_DMEM) ++ //########################################################################################################### ++ if (p_sdmmc_slot->dma_buffer) ++ dma_free_coherent(NULL, MAX_BLK_COUNT * MAX_BLK_SIZE, p_sdmmc_slot->dma_buffer, p_sdmmc_slot->dma_phy_addr); ++//########################################################################################################### ++#else ++//########################################################################################################### ++ mem_info.length = MAX_BLK_COUNT * MAX_BLK_SIZE; ++ strcpy(mem_info.name, "SDMMC_SGBUF"); ++ mem_info.phys = (unsigned long long)p_sdmmc_slot->dma_phy_addr; ++ msys_release_dmem(&mem_info); ++//########################################################################################################### ++#endif ++ ++ ++#endif ++ ++ return nRet; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_probe ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Probe Platform Device ++ * ++ * @param p_dev : platform_device ++ * ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++//struct ms_sdmmc_host *p_sdmmc_host; ++static int ms_sdmmc_probe(struct platform_device *p_dev) ++{ ++ struct ms_sdmmc_host *p_sdmmc_host; ++ unsigned int slotNo = 0; ++ int ret = 0; ++ ++ pr_info(">> [sdmmc] ms_sdmmc_probe \n"); ++ ++ p_sdmmc_host = kzalloc(sizeof(struct ms_sdmmc_host), GFP_KERNEL); ++ ++ if (!p_sdmmc_host) ++ { ++ pr_err(">> [sdmmc] Err: Failed to Allocate p_sdmmc_host!\n\n"); ++ return -ENOMEM; ++ } ++ ++ p_sdmmc_host->pdev = p_dev; ++ ++ /***** device data setting ******/ ++ platform_set_drvdata(p_dev, p_sdmmc_host); ++ ++ /***** device PM wakeup setting ******/ ++ device_init_wakeup(&p_dev->dev, 1); ++ ++#if defined(CONFIG_OF) ++ if (ms_sdmmc_dts_init(p_dev)) ++ { ++ pr_err(">> [sdmmc] Err: Failed to use DTS function!\n\n"); ++ return -EINVAL; ++ } ++#else ++ // CONFIG_OF is necessary ++ return 1; ++#endif ++ ++ for (slotNo=0; slotNo> [sdmmc_%u] Probe Platform Devices\n", slotNo); ++ if (ret!=0) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to init slot!\n",slotNo); ++ kfree(p_sdmmc_host); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_remove_slot ++ * @author jeremy.wang (2015/12/9) ++ * Desc: Remove Slot Setting ++ * ++ * @param slotNo : Slot Number ++ * @param p_sdmmc_host : ms_sdmmc_host ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_remove_slot(unsigned int slotNo, struct ms_sdmmc_host *p_sdmmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = p_sdmmc_host->sdmmc_slot[slotNo]; ++ struct mmc_host *p_mmc_host = p_sdmmc_slot->mmc; ++ SlotEmType eSlot = (SlotEmType)slotNo; ++ ++//########################################################################################################### ++#if (EN_MSYS_REQ_DMEM) ++//########################################################################################################### ++ MSYS_DMEM_INFO mem_info; ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++//########################################################################################################### ++#if !(EN_MSYS_REQ_DMEM) ++//########################################################################################################### ++ if (!_IsAdmaMode(eSlot)) { ++ if (p_sdmmc_slot->dma_buffer) ++ dma_free_coherent(NULL, MAX_BLK_COUNT*MAX_BLK_SIZE, p_sdmmc_slot->dma_buffer, p_sdmmc_slot->dma_phy_addr); ++ } ++ else { ++ if (p_sdmmc_slot->adma_buffer) ++ dma_free_coherent(NULL, sizeof(AdmaDescStruct) * MAX_SEG_CNT, p_sdmmc_slot->adma_buffer, p_sdmmc_slot->adma_phy_addr); ++ } ++//########################################################################################################### ++#else ++//########################################################################################################### ++ mem_info.length = MAX_BLK_COUNT * MAX_BLK_SIZE; ++ strcpy(mem_info.name, "SDMMC_SGBUF"); ++ mem_info.phys = (unsigned long long)p_sdmmc_slot->dma_phy_addr; ++ msys_release_dmem(&mem_info); ++//########################################################################################################### ++#endif ++ ++ ++#if 1 // MIE ++ free_irq(p_sdmmc_slot->mieIRQNo, &gst_IntSourceSlot[eSlot]); ++#endif ++ ++ if (gb_IntCDZSlot[eSlot]) ++ { ++ tasklet_kill(&p_sdmmc_slot->hotplug_tasklet); ++ if(p_sdmmc_slot->cdzIRQNo) ++ { ++ free_irq(p_sdmmc_slot->cdzIRQNo, &gst_IntSourceSlot[eSlot]); ++ ++ // Set irq type IRQ_TYPE_NONE for of_irq_get_byname() works fine next time. ++ //Hal_CARD_SetGPIOIntAttr(EV_GPIO_OPT5, p_sdmmc_slot->cdzIRQNo); ++ irq_dispose_mapping(p_sdmmc_slot->cdzIRQNo); // for irq_create_fwspec_mapping ++ } ++ } ++ ++ // ++ mmc_remove_host(p_mmc_host); ++ mmc_free_host(p_mmc_host); ++ ++ // ++#if defined(CONFIG_OF) ++#ifdef CONFIG_CAM_CLK ++ if(gp_clkSlot[eSlot]) ++ { ++ CamClkUnregister(gp_clkSlot[slotNo]); ++ gp_clkSlot[eSlot] = NULL; ++ } ++#else ++ if(gp_clkSlot[eSlot]) ++ { ++ clk_put(gp_clkSlot[eSlot]); ++ gp_clkSlot[eSlot] = NULL; ++ } ++#endif ++#endif ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_remove ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Revmoe MMC host ++ * ++ * @param p_dev : platform device structure ++ * ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_remove(struct platform_device *p_dev) ++{ ++ struct ms_sdmmc_host *p_sdmmc_host = platform_get_drvdata(p_dev); ++ unsigned int slotNo = 0; ++ ++ platform_set_drvdata(p_dev, NULL); ++ ++ for(slotNo=0; slotNo> [sdmmc_%u] Remove devices...\n", slotNo); ++ ++ } ++ ++ kfree(p_sdmmc_host); ++ ++ return 0; ++} ++ ++ ++#if defined(CONFIG_OF) ++ ++ #ifdef CONFIG_PM_SLEEP ++ static int ms_sdmmc_devpm_prepare(struct device *dev) ++ { ++ return 0; ++ } ++ ++ static void ms_sdmmc_devpm_complete(struct device *dev) ++ { ++ ++ } ++ ++ static int ms_sdmmc_devpm_suspend(struct device *dev) ++ { ++ unsigned int slotNo = 0; ++ int tret = 0; ++ unsigned int TmpIPClk = 0; ++ unsigned int TmpBlockClk = 0; ++ ++ for(slotNo=0; slotNo> [sdmmc_%u] Suspend device pm...(Ret:%u) \n", slotNo); ++ } ++ ++ return tret; ++ } ++ ++ static int ms_sdmmc_devpm_resume(struct device *dev) ++ { ++ unsigned int slotNo = 0; ++#ifdef CONFIG_CAM_CLK ++ int tret = 0; ++#else ++ int ret = 0, tret = 0; ++#endif ++ ++ for(slotNo=0; slotNo> [sdmmc_%u] Resume device pm...(Ret:%u) \n", slotNo, ret); ++ } ++ ++ return tret; ++ } ++ ++ #else ++ ++ #define ms_sdmmc_devpm_prepare NULL ++ #define ms_sdmmc_devpm_complete NULL ++ #define ms_sdmmc_devpm_suspend NULL ++ #define ms_sdmmc_devpm_resume NULL ++ ++ #endif ++ ++ static int ms_sdmmc_devpm_runtime_suspend(struct device *dev) ++ { ++ pr_sd_dbg(">> [sdmmc] Runtime Suspend device pm...\n"); ++ return 0; ++ } ++ ++ static int ms_sdmmc_devpm_runtime_resume(struct device *dev) ++ { ++ pr_sd_dbg(">> [sdmmc] Runtime Resume device pm...\n"); ++ return 0; ++ } ++ ++ #define ms_sdmmc_suspend NULL ++ #define ms_sdmmc_resume NULL ++ ++ ++#else ++ ++ #ifdef CONFIG_PM_SLEEP ++ ++ #if 0 //( LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) ) // CONFIG_PM ++ ++ /*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_suspend ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Suspend MMC host ++ * ++ * @param p_dev : platform device structure ++ * @param state : Power Management Transition State ++ * ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++ static int ms_sdmmc_suspend(struct platform_device *p_dev, pm_message_t state) ++ { ++ struct ms_sdmmc_host *p_sdmmc_host = platform_get_drvdata(p_dev); ++ struct mmc_host *p_mmc_host; ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ ++ for(slotNo=0; slotNosdmmc_slot[slotNo]->mmc; ++ ++ if (p_mmc_host) ++ { ++ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) ++ ret = mmc_suspend_host(p_mmc_host); ++ #else ++ ret = mmc_suspend_host(p_mmc_host, state); ++ #endif ++ pr_sd_dbg(">> [sdmmc_%u] Suspend host...(Ret:%u) \n", slotNo, ret); ++ ++ if(ret!=0) ++ tret = ret; ++ } ++ ++ } ++ ++ return tret; ++ } ++ ++ /*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_resume ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Resume MMC host ++ * ++ * @param p_dev : platform device structure ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++ static int ms_sdmmc_resume(struct platform_device *p_dev) ++ { ++ struct ms_sdmmc_host *p_sdmmc_host = platform_get_drvdata(p_dev); ++ struct mmc_host *p_mmc_host; ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ for(slotNo=0; slotNosdmmc_slot[slotNo]->mmc; ++ if (p_mmc_host) ++ { ++ ret = mmc_resume_host(p_mmc_host); ++ pr_sd_dbg(">> [sdmmc_%u] Resume host...(Ret:%u) \n", slotNo, ret); ++ if(ret!=0) ++ tret = ret; ++ } ++ } ++ ++ return tret; ++ } ++ ++ #else ++ ++ static int ms_sdmmc_suspend(struct platform_device *p_dev, pm_message_t state) ++ { ++ int ret = 0; ++ return ret; ++ } ++ ++ static int ms_sdmmc_resume(struct platform_device *p_dev) ++ { ++ int ret = 0; ++ return ret; ++ } ++ ++ #endif ++ ++ #else // !CONFIG_PM ++ ++ //Current driver does not support following two functions, therefore set them to NULL. ++ #define ms_sdmmc_suspend NULL ++ #define ms_sdmmc_resume NULL ++ ++ #endif // End of CONFIG_PM ++ ++ ++ ++#endif ++ ++ ++/********************************************************************************************************** ++ * Define Static Global Structs ++ **********************************************************************************************************/ ++ ++#if defined(CONFIG_OF) ++/*---------------------------------------------------------------------------------------------------------- ++ * ms_sdmmc_of_match_table ++ ----------------------------------------------------------------------------------------------------------*/ ++static const struct of_device_id ms_sdmmc_of_match_table[] = { ++ { .compatible = "sstar,sdmmc" }, ++ {} ++}; ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ms_sdmmc_dev_pm_ops ++ ----------------------------------------------------------------------------------------------------------*/ ++static struct dev_pm_ops ms_sdmmc_dev_pm_ops = { ++ .suspend = ms_sdmmc_devpm_suspend, ++ .resume = ms_sdmmc_devpm_resume, ++ .prepare = ms_sdmmc_devpm_prepare, ++ .complete = ms_sdmmc_devpm_complete, ++ .runtime_suspend = ms_sdmmc_devpm_runtime_suspend, ++ .runtime_resume = ms_sdmmc_devpm_runtime_resume, ++}; ++ ++#else ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * st_ms_sdmmc_device ++ ----------------------------------------------------------------------------------------------------------*/ ++static u64 mmc_dmamask = 0xffffffffUL; ++static struct platform_device ms_sdmmc_pltdev = ++{ ++ .name = DRIVER_NAME, ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &mmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL, ++ }, ++}; ++ ++#endif //End of (defined(CONFIG_OF)) ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * st_ms_sdmmc_driver ++ ----------------------------------------------------------------------------------------------------------*/ ++static struct platform_driver ms_sdmmc_pltdrv = ++{ ++ .remove = ms_sdmmc_remove,/*__exit_p(ms_sdmmc_remove)*/ ++ .suspend = ms_sdmmc_suspend, ++ .resume = ms_sdmmc_resume, ++ .probe = ms_sdmmc_probe, ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ ++#if defined(CONFIG_OF) ++ .of_match_table = of_match_ptr(ms_sdmmc_of_match_table), ++ .pm = &ms_sdmmc_dev_pm_ops, ++#endif ++ ++ }, ++}; ++ ++ ++/********************************************************************************************************** ++ * Init & Exit Modules ++ **********************************************************************************************************/ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_mci_init ++ * @author jeremy.wang (2011/7/18) ++ * Desc: Linux Module Function for Init ++ * ++ * @return s32 __init : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++static s32 ms_sdmmc_init(void) ++{ ++ pr_sd_dbg(KERN_INFO ">> [sdmmc] %s Driver Initializing... \n", DRIVER_NAME); ++ ++#if !(defined(CONFIG_OF)) ++ platform_device_register(&ms_sdmmc_pltdev); ++#endif ++ ++ return platform_driver_register(&ms_sdmmc_pltdrv); ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_exit ++ * @author jeremy.wang (2011/9/8) ++ * Desc: Linux Module Function for Exit ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_exit(void) ++{ ++ platform_driver_unregister(&ms_sdmmc_pltdrv); ++} ++ ++ ++ ++module_init(ms_sdmmc_init); ++module_exit(ms_sdmmc_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_AUTHOR("SSTAR"); +diff --git a/drivers/sstar/sdmmc/src/hal_card_intr_v5.c b/drivers/sstar/sdmmc/src/hal_card_intr_v5.c +new file mode 100755 +index 000000000000..53846dc445e0 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/hal_card_intr_v5.c +@@ -0,0 +1,347 @@ ++/* ++* hal_card_intr_v5.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_intr_v5.c ++ * @author jeremy.wang (2015/10/29) ++ * Desc: ++ * The Interrupt behavior of all cards will run here. ++ * The goal is that we don't need to change HAL Level code (But its h file code) ++ * ++ * The limitations were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API or HAL level, not driver flow process. ++ * (3) MIE Event Int and Card Change Event Int function belong to here. ++ * (4) FCIE/SDIO IP interrupt register function belong to here. ++ * (5) Because ISR belongs to OS design, so we must use OS define option to separate them. ++ * (6) This c file could not use project/cpu/icver/specific define option here, but its h file could. ++ * ++ * P.S. EN_XX for ON/OFF Define, V_XX for Value Define, ++ * RT_XX for Retry Times Define, WT_XX for Wait Time Define, M_XX for Mask Value Define ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_intr_v5.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Enable Setting ++//----------------------------------------------------------------------------------------------------------- ++#define EN_TRFUNC (FALSE) ++ ++// Value Setting ++//----------------------------------------------------------------------------------------------------------- ++#define V_MAXSLOTS 2 ++ ++ ++//*********************************************************************************************************** ++ ++ ++// Reg Static Init Setting ++//----------------------------------------------------------------------------------------------------------- ++//#define V_SD_MIE_INT_INIT (R_SD_CMD_END_EN|R_SD_DATA_END_EN|R_CARD_DMA_END_EN|R_MMA_LSDONE_END_EN) ++ ++// Mask Range ++//----------------------------------------------------------------------------------------------------------- ++#define M_CARD_INT_EN (R_DATA_END_IEN|R_CMD_END_IEN|R_BUSY_END_IEN) ++ ++// Mask Reg Value ++//----------------------------------------------------------------------------------------------------------- ++#define M_REG_DCRCERR(IP) (CARD_REG(A_SD_STS_REG(IP)) & M_SD_DCRCSTS) //0x1F ++ ++ ++//IP_FCIE or IP_SDIO Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_SD_REG_POS(IP) GET_CARD_BANK(IP, 0) ++ ++#define A_MIE_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x00) ++#define A_MIE_INT_EN_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x01) ++ ++#define A_MIE_FUNC_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x07) ++#define A_SD_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0C) ++#define A_SD_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0D) ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile U16_T gu16_MIEINT_Mode[3] = {0}; ++static volatile U16_T gu16_MIEEvent_ForInt[3] = {0}; //MIEEvent for Interrupt ++static volatile U16_T gu16_MIEIntEN_ForSDIO[3] = {0}; ++static volatile BOOL_T gb_StopWaitMIE[3] = {0}; ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_TRFUNC) ++ #define TR_INT(p) p ++#else ++ #define TR_INT(p) ++#endif ++ ++BOOL_T _CARD_INT_SaveMIEEvent(IpOrder eIP) ++{ ++ U16_T u16Reg = CARD_REG(A_MIE_EVENT_REG(eIP)); ++ ++ if ( CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) & R_EMMC_EN ) //Emmc Event ++ return (FALSE); ++ ++ gu16_MIEEvent_ForInt[eIP] |= u16Reg; //Summary All 0x00Reg Event ++ ++ u16Reg &= CARD_REG(A_MIE_INT_EN_REG(eIP)); ++ ++ /****** Clean Card MIE Event *******/ ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = 0; ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = (M_CARD_INT_EN & u16Reg); ++ ++ if(gu16_MIEEvent_ForInt[eIP] & R_BUSY_END_INT) ++ { ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_BUSY_DET_ON ); ++ CARD_REG_CLRBIT(A_MIE_INT_EN_REG(eIP), R_BUSY_END_INT ); ++ } ++ ++#if 0 // For Debug whether event clear or not ++ sdmmc_print("Debug: [MIE_EVENT_REG]= "); ++ sdmmc_print("0x%04X", CARD_REG(A_MIE_EVENT_REG(eIP))); ++ sdmmc_print("\r\n"); ++ ++ while(1) ++ { ++ } ++#endif ++ ++ return (TRUE); ++} ++ ++static BOOL_T _CARD_INT_DetectSDIOInt(IpOrder eIP) ++{ ++ U16_T u16Reg = CARD_REG(A_MIE_EVENT_REG(eIP)); ++ ++ if( (u16Reg & R_SDIO_INT) && (gu16_MIEIntEN_ForSDIO[eIP] == R_SDIO_INT_IEN) ) ++ { ++ //printk("_M[%04X]_", CARD_REG(A_MIE_EVENT_REG(eIP))); ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = R_SDIO_INT; //Clear SDIO_EVENT to avoid trig int again ++ ++ return (TRUE); ++ } ++ ++ return (FALSE); ++ ++} ++ ++void Hal_CARD_INT_MIEIntCtrl(IpOrder eIP, BOOL_T bEnable) ++{ ++ gu16_MIEINT_Mode[eIP] = bEnable; ++} ++ ++BOOL_T Hal_CARD_INT_MIEIntRunning(IpOrder eIP) ++{ ++ return gu16_MIEINT_Mode[eIP]; ++} ++ ++void Hal_CARD_INT_SetMIEIntEn(IpOrder eIP, U16_T u16RegMIEIntEN) ++{ ++ if (gu16_MIEINT_Mode[eIP]) ++ { ++ //Enable MIE_INT_EN ++ CARD_REG(A_MIE_INT_EN_REG(eIP)) = (u16RegMIEIntEN | gu16_MIEIntEN_ForSDIO[eIP]); ++ } ++ else ++ { ++ //Clear MIE_INT_EN to Avoid Interrupt ++ CARD_REG(A_MIE_INT_EN_REG(eIP)) = 0; ++ } ++} ++ ++void Hal_CARD_INT_SetMIEIntEn_ForSDIO(IpOrder eIP, BOOL_T bEnable) ++{ ++ if (bEnable) ++ { ++ //Clear SDIO Int to avoid trig Int after SDIO Int Enable ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = R_SDIO_INT; ++ ++ gu16_MIEIntEN_ForSDIO[eIP] = R_SDIO_INT_IEN; ++ CARD_REG_SETBIT(A_MIE_INT_EN_REG(eIP), R_SDIO_INT_IEN); ++ } ++ else ++ { ++ gu16_MIEIntEN_ForSDIO[eIP] = 0; ++ CARD_REG_CLRBIT(A_MIE_INT_EN_REG(eIP), R_SDIO_INT_IEN); ++ } ++} ++ ++void Hal_CARD_INT_ClearMIEEvent(IpOrder eIP) ++{ ++ gu16_MIEEvent_ForInt[eIP] = 0; ++} ++ ++U16_T Hal_CARD_INT_GetMIEEvent(IpOrder eIP) ++{ ++ return gu16_MIEEvent_ForInt[eIP]; ++} ++ ++ ++//*********************************************************************************************************** ++// Interrupt Handler Function ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++static DECLARE_WAIT_QUEUE_HEAD(fcie1_mieint_wait); ++static DECLARE_WAIT_QUEUE_HEAD(fcie2_mieint_wait); ++static DECLARE_WAIT_QUEUE_HEAD(fcie3_mieint_wait); ++ ++#endif ++//########################################################################################################### ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_WaitMIEEvent ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Set WaitQueue Handler to Wait MIE Event ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u16ReqEvent : MIE Event for waiting ++ * @param u32WaitMs : Waiting Time (ms) ++ * ++ * @return BOOL_T : TRUE (Success), FALSE (Timeout) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_INT_WaitMIEEvent(IpOrder eIP, U16_T u16ReqEvent, U32_T u32WaitMs) ++{ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ long ret; ++ if (eIP == IP_ORDER_0) ++ ret = wait_event_timeout(fcie1_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ else if (eIP == IP_ORDER_1) ++ ret = wait_event_timeout(fcie2_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ else if (eIP == IP_ORDER_2) ++ ret = wait_event_timeout(fcie3_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ ++ if (ret == 0) ++ { ++ // It "may" be time out. ++ } ++ ++ if ((gu16_MIEEvent_ForInt[eIP] & u16ReqEvent) != u16ReqEvent) ++ return FALSE; ++ ++ return TRUE; ++//########################################################################################################### ++#endif ++ ++ /****** Not Support (Ex: D_OS_ARCH = D_OS_UBOOT) ******/ ++ return FALSE; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_StopWaitMIEEventCtrl ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Stop Wait MIE Event to Avoid Long Time Waiting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_StopWaitMIEEventCtrl(IpOrder eIP, BOOL_T bEnable) ++{ ++ gb_StopWaitMIE[eIP] = bEnable; ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ if(gb_StopWaitMIE[eIP]) ++ { ++ /****** Break Current Wait Event *******/ ++ if (eIP == IP_ORDER_0) ++ wake_up(&fcie1_mieint_wait); ++ else if (eIP == IP_ORDER_1) ++ wake_up(&fcie2_mieint_wait); ++ else if (eIP == IP_ORDER_2) ++ wake_up(&fcie3_mieint_wait); ++ } ++#endif ++//########################################################################################################### ++ ++} ++ ++ ++//*********************************************************************************************************** ++// Interrupt Function ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include "../inc/ms_sdmmc_lnx.h" ++#include "linux/moduleparam.h" ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIE ++ * @author jeremy.wang (2012/2/13) ++ * Desc: ++ * ++ * @param irq : ++ * @param p_dev_id : ++ * ++ * @return irqreturn_t : ++ ----------------------------------------------------------------------------------------------------------*/ ++unsigned int gu32_sdio_int_count=0; ++module_param(gu32_sdio_int_count, uint, S_IRUGO); ++unsigned int gu32_sd_irq_count=0; ++module_param(gu32_sd_irq_count, uint, S_IRUGO); ++ ++irqreturn_t Hal_CARD_INT_MIE(int irq, void *p_dev_id) ++{ ++ irqreturn_t irq_t = IRQ_NONE; ++ IntSourceStruct* pstIntSource = p_dev_id; ++ IpOrder eIP = pstIntSource->eIP; ++ struct ms_sdmmc_slot *p_sdmmc_slot = pstIntSource->p_data; ++ ++ gu32_sd_irq_count++; ++ ++ if(_CARD_INT_DetectSDIOInt(eIP)) ++ { ++ mmc_signal_sdio_irq(p_sdmmc_slot->mmc); ++ irq_t = IRQ_HANDLED; ++ gu32_sdio_int_count++; ++ } ++ ++ if(_CARD_INT_SaveMIEEvent(eIP)) ++ { ++ if (eIP == IP_ORDER_0) ++ wake_up(&fcie1_mieint_wait); ++ else if (eIP == IP_ORDER_1) ++ wake_up(&fcie2_mieint_wait); ++ else if (eIP == IP_ORDER_2) ++ wake_up(&fcie3_mieint_wait); ++ ++ irq_t = IRQ_HANDLED; ++ } ++ ++ return irq_t; ++} ++ ++ ++//########################################################################################################### ++#endif +diff --git a/drivers/sstar/sdmmc/src/hal_card_regs.c b/drivers/sstar/sdmmc/src/hal_card_regs.c +new file mode 100755 +index 000000000000..d466143d8735 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/hal_card_regs.c +@@ -0,0 +1,46 @@ ++/* ++* hal_card_regs.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include "../inc/hal_card_regs.h" ++ ++ ++ ++volatile void* Hal_CREG_GET_REG_BANK(IpOrder eIP, U8_T u8Bank) ++{ ++ static IpOrder ip; ++ static U8_T bank; ++ void* pIPBANKArr[3][3] = { ++ {(void*)(A_FCIE1_0_BANK), (void*)(A_FCIE1_1_BANK), (void*)(A_FCIE1_2_BANK)}, \ ++ {(void*)(A_FCIE2_0_BANK), (void*)(A_FCIE2_1_BANK), (void*)(A_FCIE2_2_BANK)}, \ ++ {(void*)(A_FCIE3_0_BANK), (void*)(A_FCIE3_1_BANK), (void*)(A_FCIE3_2_BANK)}\ ++ }; ++ ++ if (eIP != ip) ++ { ++ /*printk("Get IP%d\n", eIP);*/ ++ ip = eIP; ++ } ++ ++ if (u8Bank != bank) ++ { ++ //printk("new bank%d\n", u8Bank); bank = u8Bank; ++ } ++ ++ return pIPBANKArr[eIP][u8Bank]; ++ ++} +diff --git a/drivers/sstar/sdmmc/src/hal_card_timer.c b/drivers/sstar/sdmmc/src/hal_card_timer.c +new file mode 100755 +index 000000000000..58eb8412f223 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/hal_card_timer.c +@@ -0,0 +1,120 @@ ++/* ++* hal_card_timer.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_timer.c ++ * @author jeremy.wang (2012/01/13) ++ * Desc: ++ * All of timer behavior will run here. ++ * The goal is that we don't need to change HAL Level code (But its h file code) ++ * ++ * The limitation were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API level, not driver flow process. ++ * (2) Delay and GetTimerTick function belong to here. ++ * (3) Because timer may belong to OS design or HW timer, so we could use OS define option to separate them. ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_timer.h" ++#if (D_OS == D_OS__LINUX) ++#include "linux/sched.h" ++#endif ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_Timer_mDelay ++ * @author jeremy.wang (2013/7/19) ++ * Desc: Run millisecond delay ++ * ++ * @param u32_msec : Millisecond for Delay ++ * ++ * @return U32_T : Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_Timer_mDelay(U32_T u32_msec) ++{ ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) || (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++ mdelay(u32_msec); ++ return u32_msec; ++//########################################################################################################### ++#endif ++ return 0; ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_Timer_uDelay ++ * @author jeremy.wang (2013/7/19) ++ * Desc: Run micro-second delay ++ * ++ * @param u32_usec : Micro-second for Delay ++ * ++ * @return U32_T : Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_Timer_uDelay(U32_T u32_usec) ++{ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) || (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++ udelay(u32_usec); ++ return u32_usec; ++//########################################################################################################### ++#endif ++ ++ return 0; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_Timer_mSleep ++ * @author jeremy.wang (2015/1/15) ++ * Desc: Run millisecond sleep ++ * ++ * @param u32_msec : Millisecond for Sleep ++ * ++ * @return U32_T : Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_Timer_mSleep(U32_T u32_msec) ++{ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#if (HZ) <= 100 ++ if (u32_msec < 1000 / HZ) ++ { ++ cond_resched(); ++ mdelay(u32_msec); ++ } ++ else ++ { ++ msleep(u32_msec); ++ } ++#else ++ msleep(u32_msec); ++#endif ++ return u32_msec; ++//########################################################################################################### ++#endif ++ return 0; ++ ++} ++ +diff --git a/drivers/sstar/sdmmc/src/hal_sdmmc_v5.c b/drivers/sstar/sdmmc/src/hal_sdmmc_v5.c +new file mode 100644 +index 000000000000..6e2b055a5dcd +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/hal_sdmmc_v5.c +@@ -0,0 +1,1309 @@ ++/* ++* hal_sdmmc_v5.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_sdmmc_v5.c (Driver Version) ++ * @author jeremy.wang (2015/07/06) ++ * Desc: ++ * HAL SD Driver will support basic SD function but not flow process. ++ * (1) It included Register and Buffer opertion code. ++ * (2) h file will has APIs for Driver, but just SD abstract, not register abstract. ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_sdmmc_v5.h" ++#include "../inc/hal_card_timer.h" ++ ++#if(EN_BIND_CARD_INT) ++#include "../inc/hal_card_intr_v5.h" //inlcue but may not use ++#endif ++ ++ ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++ ++// Enable Setting ++//----------------------------------------------------------------------------------------------------------- ++#define EN_TRFUNC (FALSE) ++#define EN_DUMPREG (TRUE) ++#define EN_BYPASSMODE (FALSE) //BYPASS MODE or ADVANCE MODE(SDR/DDR) ++#define EN_HALT (FALSE) ++ ++// Retry Times ++//----------------------------------------------------------------------------------------------------------- ++#define RT_CLEAN_SDSTS 3 ++#define RT_CLEAN_MIEEVENT 3 ++ ++// Wait Time ++//----------------------------------------------------------------------------------------------------------- ++#define WT_DAT0HI_END 1000 //(ms) ++#define WT_EVENT_CIFD 500 //(ms) ++#define WT_RESET 100 //(ms) ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++ ++// Reg Static Init Setting ++//----------------------------------------------------------------------------------------------------------- ++#define V_MIE_PATH_INIT 0 ++#define V_MMA_PRI_INIT (R_MIU_R_PRIORITY|R_MIU_W_PRIORITY|R_MIU_BUS_BURST8) ++#define V_MIE_INT_EN_INIT (R_DATA_END_IEN|R_CMD_END_IEN|R_SDIO_INT_IEN|R_BUSY_END_IEN) ++#define V_RSP_SIZE_INIT 0 ++#define V_CMD_SIZE_INIT (5<<8) ++#define V_SD_CTL_INIT 0 ++#define V_SD_MODE_INIT (R_CLK_EN) // Add ++#define V_SDIO_MODE_INIT (1 << 3) //Low level trigger from Joe's email. Was 0 before. ++#define V_DDR_MODE_INIT 0 ++ ++ ++// Mask Range ++//----------------------------------------------------------------------------------------------------------- ++#define M_SD_ERRSTS (R_DAT_RD_CERR|R_DAT_WR_CERR|R_DAT_WR_TOUT|R_CMD_NORSP|R_CMDRSP_CERR|R_DAT_RD_TOUT) ++#define M_SD_MIEEVENT (R_DATA_END|R_CMD_END|R_ERR_STS|R_BUSY_END_INT|R_R2N_RDY_INT) ++#define M_RST_STS (R_RST_MIU_STS|R_RST_MIE_STS|R_RST_MCU_STS) ++ ++ ++// Mask Reg Value ++//----------------------------------------------------------------------------------------------------------- ++#define M_REG_STSERR(IP) (CARD_REG(A_SD_STS_REG(IP)) & M_SD_ERRSTS) ++#define M_REG_SDMIEEvent(IP) (CARD_REG(A_MIE_EVENT_REG(IP)) & M_SD_MIEEVENT) ++#define M_REG_GETDAT0(IP) (CARD_REG(A_SD_STS_REG(IP)) & R_DAT0) ++ ++ ++//----------------------------------------------------------------------------------------------------------- ++//IP_FCIE or IP_SDIO Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_SD_REG_POS(IP) GET_CARD_BANK(IP, 0) ++#define A_SD_CFIFO_POS(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x20) //Always at FCIE5 ++#define A_SD_CIFD_POS(IP) GET_CARD_BANK(IP, 1) ++ ++#define A_SD_CIFD_R_POS(IP) GET_CARD_REG_ADDR(A_SD_CIFD_POS(IP), 0x00) ++#define A_SD_CIFD_W_POS(IP) GET_CARD_REG_ADDR(A_SD_CIFD_POS(IP), 0x20) ++ ++#define A_MIE_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x00) ++#define A_MIE_INT_ENABLE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x01) ++#define A_MMA_PRI_REG_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x02) ++#define A_DMA_ADDR_15_0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x03) ++#define A_DMA_ADDR_31_16_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x04) ++#define A_DMA_LEN_15_0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x05) ++#define A_DMA_LEN_31_16_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x06) ++#define A_MIE_FUNC_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x07) ++#define A_JOB_BLK_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x08) ++#define A_BLK_SIZE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x09) ++#define A_CMD_RSP_SIZE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0A) ++#define A_SD_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0B) ++#define A_SD_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0C) ++#define A_SD_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0D) ++#define A_BOOT_MOD_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0E) ++#define A_DDR_MOD_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0F) ++#define A_DDR_TOGGLE_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x10) ++#define A_SDIO_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x11) ++#define A_TEST_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x15) ++ ++#define A_WR_SBIT_TIMER_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x17) ++#define A_RD_SBIT_TIMER_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x18) ++ ++#define A_SDIO_DET_ON(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x2F) ++ ++#define A_CIFD_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x30) ++#define A_CIFD_INT_EN_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x31) ++ ++#define A_BOOT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x37) ++ ++#define A_DBG_BUS0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x38) ++#define A_DBG_BUS1_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x39) ++#define A_FCIE_RST_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x3F) ++ ++#define A_CFIFO_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CFIFO_POS(IP), OFFSET) ++#define A_CIFD_R_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CIFD_R_POS(IP), OFFSET) ++#define A_CIFD_W_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CIFD_W_POS(IP), OFFSET) ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static RspStruct gst_RspStruct[3]; ++static volatile BOOL_T gb_StopWProc[3] = {0}; ++static volatile U16_T gu16_WT_NRC[3] = {0}; //Waiting Time for Nrc (us) ++ ++static volatile U16_T gu16_SD_MODE_DatLine[3] = {0}; ++ ++static volatile U16_T gu16_DDR_MODE_REG[3] = {0}; ++static volatile U16_T gu16_DDR_MODE_REG_ForR2N[3] = {0}; ++ ++static volatile BOOL_T gb_SDIODevice[3] = {0}; ++static volatile U16_T gu16_SDIO_MODE_IntMode[3] = {0}; ++ ++ ++static volatile U8_T* gpu8Buf[3]; ++ ++ ++static volatile IpType geIpTypeIp[3] = {IP_0_TYPE, IP_1_TYPE, IP_2_TYPE}; ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_TRFUNC) ++ #define TR_H_SDMMC(p) p ++#else ++ #define TR_H_SDMMC(p) ++#endif ++ ++ ++// Register Opertation Define ==> For FCIE5 Special FCIE/SDIO Function Ctrl Setting ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_GetMIEFunCtlSetting(IpOrder eIP) ++{ ++ if (geIpTypeIp[eIP] == IP_TYPE_FCIE) ++ { ++ return R_SD_EN; // FCIE don't have SDIO function. ++ } ++ ++ return R_SDIO_MODE; ++} ++ ++ ++// Register Operation Define ==> For Clean Reg and Special Case ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_ClearSDSTS(IpOrder eIP, U8_T u8Retry) ++{ ++ do ++ { ++ CARD_REG_SETBIT(A_SD_STS_REG(eIP), M_SD_ERRSTS); ++ ++ if ( gb_StopWProc[eIP] ) ++ break; ++ ++ if ( !M_REG_STSERR(eIP) ) ++ return EV_OK; ++ else if(!u8Retry) ++ break; ++ ++ } while(u8Retry--); ++ ++ return EV_FAIL; //mark for coverity scan ++} ++ ++ ++// Register Operation Define ==> For Clear MIE Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_ClearMIEEvent(IpOrder eIP, U8_T u8Retry) ++{ ++ /****** Clean global MIEEvent for Interrupt ******/ ++#if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_ClearMIEEvent(eIP); ++#endif ++ ++ /****** Clean MIEEvent Reg *******/ ++ do ++ { ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = M_SD_MIEEVENT; ++ ++ if ( gb_StopWProc[eIP] ) ++ break; ++ ++ if ( !M_REG_SDMIEEvent(eIP) ) ++ return EV_OK; ++ else if( !u8Retry ) ++ break; ++ ++ }while( u8Retry-- ); ++ return EV_FAIL; //mark for coverity scan ++ ++} ++ ++ ++// Register Operation Define ==> For Wait DAT0 High ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitDat0HI(IpOrder eIP, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++#if(EN_BIND_CARD_INT) ++ if (Hal_CARD_INT_MIEIntRunning(eIP)) // Interrupt Mode ++ { ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_BUSY_DET_ON ); ++ ++ if ( !Hal_CARD_INT_WaitMIEEvent(eIP, R_BUSY_END_INT, u32WaitMs) ) ++ return EV_FAIL; ++ else ++ return EV_OK; ++ ++ } ++ else // Polling Mode ++#endif ++ { ++ do ++ { ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if ( M_REG_GETDAT0(eIP) ) ++ return EV_OK; ++ ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while( u32DiffTime <= (u32WaitMs*1000) ); ++ } ++ return EV_FAIL; ++} ++ ++ ++// Register Operation Define ==> For Wait MIE Event or CIFD Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitEvent(IpOrder eIP, IPEventEmType eEvent, U16_T u16ReqEvent, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++#if(EN_BIND_CARD_INT) ++ if (Hal_CARD_INT_MIEIntRunning(eIP)) // Interrupt Mode ++ { ++ if(eEvent == EV_MIE) ++ { ++ if ( !Hal_CARD_INT_WaitMIEEvent(eIP, u16ReqEvent, u32WaitMs) ) { ++ return EV_FAIL; ++ } ++ else { ++ return EV_OK; ++ } ++ } ++ ++ } ++ else // Polling Mode ++#endif ++ { ++ do ++ { ++ if ( gb_StopWProc[eIP] ) { ++ return EV_FAIL; ++ } ++ if(eEvent == EV_MIE) ++ { ++ if ( (CARD_REG(A_MIE_EVENT_REG(eIP))&u16ReqEvent) == u16ReqEvent ) ++ { ++ return EV_OK; ++ } ++ } ++ else if(eEvent == EV_CIFD ) ++ { ++ if ( (CARD_REG(A_CIFD_EVENT_REG(eIP))&u16ReqEvent) == u16ReqEvent ) ++ { ++ return EV_OK; ++ } ++ } ++ ++ Hal_Timer_mDelay(1); ++ u32DiffTime++; ++ }while(u32DiffTime <= u32WaitMs); ++ ++ } ++ ++ return EV_FAIL; ++ ++} ++ ++ ++// Register Operation Define ==> For Software Reset ++//----------------------------------------------------------------------------------------------------------- ++static void _REG_ResetIP(IpOrder eIP) ++{ ++ U32_T u32DiffTime = 0; ++ ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_JOB_START); //Clear For Safe ? ++ ++ CARD_REG_CLRBIT(A_FCIE_RST_REG(eIP), R_FCIE_SOFT_RST); ++ ++ do ++ { ++ if( (CARD_REG(A_FCIE_RST_REG(eIP)) & M_RST_STS) == M_RST_STS ) ++ break; ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while ( u32DiffTime <= (1000*WT_RESET) ); ++ ++ if ( u32DiffTime > (1000*WT_RESET) ) ++ sdmmc_print("[HSD] IP Reset Switch Low Fail !\r\n"); ++ ++ ++ u32DiffTime = 0; ++ CARD_REG_SETBIT(A_FCIE_RST_REG(eIP), R_FCIE_SOFT_RST); ++ ++ do ++ { ++ if( (CARD_REG(A_FCIE_RST_REG(eIP)) & M_RST_STS) == 0 ) ++ break; ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ ++ }while ( u32DiffTime <= (1000* WT_RESET) ); ++ ++ if ( u32DiffTime > (1000*WT_RESET) ) ++ sdmmc_print("[HSD] IP Reset Switch High Fail !\r\n"); ++} ++ ++ ++// IP Buffer Operation => Get Byte Value form Register ++//----------------------------------------------------------------------------------------------------------- ++static U8_T _BUF_GetByteFromRegAddr(volatile void *pBuf, U16_T u16Pos) ++{ ++ if(u16Pos & 0x1) ++ return CARD_REG_H8(GET_CARD_REG_ADDR(pBuf, u16Pos>>1)); ++ else ++ return CARD_REG_L8(GET_CARD_REG_ADDR(pBuf, u16Pos>>1)); ++ ++} ++ ++ ++// IP Buffer Operation => CIFD FIFO Buffer Operation Define ++//----------------------------------------------------------------------------------------------------------- ++void _BUF_CIFD_DATA_IO(IpOrder eIP, CmdEmType eCmdType, volatile U16_T *pu16Buf, U8_T u8WordCnt) ++{ ++ U8_T u8Pos = 0; ++ ++ for ( u8Pos = 0; u8Pos < u8WordCnt; u8Pos++ ) ++ { ++ if ( eCmdType==EV_CMDREAD ) ++ pu16Buf[u8Pos] = CARD_REG(A_CIFD_R_OFFSET(eIP, u8Pos)); ++ else ++ CARD_REG(A_CIFD_W_OFFSET(eIP, u8Pos)) = pu16Buf[u8Pos]; ++ } ++ ++} ++ ++ ++// IP Buffer Operation => CIFD FIFO Buffer Operation for waiting FCIE5 special Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _BUF_CIFD_WaitEvent(IpOrder eIP, CmdEmType eCmdType, volatile U8_T *pu8R2NBuf) ++{ ++ U8_T u8RegionNo = 0, u8RegionMax = 0, u8RemainByte = 0; ++ U32_T u32_TranLen = CARD_REG(A_DMA_LEN_15_0_REG(eIP)) + ( CARD_REG(A_DMA_LEN_31_16_REG(eIP)) << 16 ); ++ ++ u8RemainByte = u32_TranLen & (64-1); // u32_TranLen % 64 ++ u8RegionMax = (u32_TranLen>>6) + (u8RemainByte ? 1: 0); ++ ++ for(u8RegionNo=0; u8RegionNo0) ) ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), u8RemainByte/2); ++ else ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), 32); ++ ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_WBUF_FULL; ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_WBUF_EMPTY_TRIG; ++ } ++ else // Write ++ { ++ if ( (u8RegionNo == (u8RegionMax-1)) && (u8RemainByte>0) ) ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), u8RemainByte/2); ++ else ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), 32); ++ ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_RBUF_FULL_TRIG; ++ ++ if ( _REG_WaitEvent(eIP, EV_CIFD, R_RBUF_EMPTY, WT_EVENT_CIFD) ) ++ return EV_FAIL; ++ ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_RBUF_EMPTY; ++ ++ } ++ ++ } ++ ++ return EV_OK; ++ ++} ++ ++ ++// SDMMC Internel Logic Function ++//----------------------------------------------------------------------------------------------------------- ++static void _SDMMC_REG_Dump(IpOrder eIP) ++{ ++ ++#if (EN_DUMPREG) ++ ++ U8_T u8Pos, u8DGMode; ++ sdmmc_print("\n------\r\n"); ++ sdmmc_print("0x%08X", ((U32_T)A_SD_REG_POS(eIP) & 0x00FFFF00) >> 9); ++ sdmmc_print("CMD_%u", gst_RspStruct[eIP].u8Cmd); ++ sdmmc_print("(Arg: 0x%08X)", gst_RspStruct[eIP].u32Arg); ++ sdmmc_print("[Line: %u]\r\n", gst_RspStruct[eIP].u32ErrLine); ++ sdmmc_print("\n------\r\n"); ++ ++ for(u8Pos = 0; u8Pos < gst_RspStruct[eIP].u8RspSize; u8Pos++) ++ { ++ if( (u8Pos == 0) || (u8Pos == 8) ) ++ sdmmc_print("["); ++ ++ sdmmc_print("0x%02X,", _BUF_GetByteFromRegAddr((volatile void *)A_SD_CFIFO_POS(eIP), u8Pos)); ++ ++ if( (u8Pos == 7) || (u8Pos == (gst_RspStruct[eIP].u8RspSize-1)) ) ++ sdmmc_print("]\n"); ++ } ++ ++ sdmmc_print("---DumpReg---\r\n"); ++ ++ sdmmc_print("[0x07][MIE_FUNC_CTL_REG]= 0x%04X\r\n", CARD_REG(A_MIE_FUNC_CTL_REG(eIP))); ++ sdmmc_print("[0x0B][SD_MODE_REG]= 0x%04X\r\n", CARD_REG(A_SD_MODE_REG(eIP))); ++ sdmmc_print("[0x0C][SD_CTL_REG]= 0x%04X\r\n", CARD_REG(A_SD_CTL_REG(eIP))); ++ sdmmc_print("[0x0F][DDR_MOD_REG]= 0x%04X\r\n", CARD_REG(A_DDR_MOD_REG(eIP))); ++ sdmmc_print("[0x0D][SD_STS_REG]= 0x%04X\r\n", CARD_REG(A_SD_STS_REG(eIP))); ++ ++#if(EN_BIND_CARD_INT) ++ if (Hal_CARD_INT_MIEIntRunning(eIP)) // Interrupt Mode ++ { ++ sdmmc_print("[gu16_MIEEvent_ForInt]= 0x%04X\r\n", Hal_CARD_INT_GetMIEEvent(eIP)); ++ } ++#endif ++ ++ sdmmc_print("[0x00][MIE_EVENT_REG]= 0x%04X\r\n", CARD_REG(A_MIE_EVENT_REG(eIP))); ++ sdmmc_print("[0x03][MMA_ADDR_15_0_REG]= 0x%04X\r\n", CARD_REG(A_DMA_ADDR_15_0_REG(eIP))); ++ sdmmc_print("[0x04][MMA_ADDR_31_16_REG]= 0x%04X\r\n", CARD_REG(A_DMA_ADDR_31_16_REG(eIP))); ++ sdmmc_print("[0x05][MMA_LEN_15_0_REG]= 0x%04X\r\n", CARD_REG(A_DMA_LEN_15_0_REG(eIP))); ++ sdmmc_print("[0x06][MMA_LEN_31_16_REG]= 0x%04X\r\n", CARD_REG(A_DMA_LEN_31_16_REG(eIP))); ++ sdmmc_print("[0x08][JOB_BLK_CNT]= 0x%04X\r\n", CARD_REG(A_JOB_BLK_CNT_REG(eIP))); ++ sdmmc_print("[0x09][BLK_SIZE]= 0x%04X\r\n", CARD_REG(A_BLK_SIZE_REG(eIP))); ++ ++ CARD_REG_CLRBIT(A_DBG_BUS1_REG(eIP), R_DEBUG_MOD0 | R_DEBUG_MOD1 | R_DEBUG_MOD2 | R_DEBUG_MOD3 ); ++ CARD_REG_SETBIT(A_DBG_BUS1_REG(eIP), R_DEBUG_MOD0 | R_DEBUG_MOD2); //Mode 5 ++ ++ sdmmc_print("[0x38][DEBUG_BUS0]= "); ++ for(u8DGMode = 1; u8DGMode <=4; u8DGMode++) ++ { ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_SD_DEBUG_MOD0 | R_SD_DEBUG_MOD1 | R_SD_DEBUG_MOD2); ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), (u8DGMode<<1)); ++ sdmmc_print("0x%04X, ", CARD_REG(A_DBG_BUS0_REG(eIP))); ++ } ++ sdmmc_print("\r\n"); ++ sdmmc_print("[0x39][DEBUG_BUS1]= "); ++ ++ for(u8DGMode = 1; u8DGMode <=4; u8DGMode++) ++ { ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_SD_DEBUG_MOD0 | R_SD_DEBUG_MOD1 | R_SD_DEBUG_MOD2); ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), (u8DGMode<<1)); ++ sdmmc_print("0x%04X, ", CARD_REG(A_DBG_BUS1_REG(eIP))); ++ } ++ ++ sdmmc_print("\r\n"); ++ sdmmc_print("------\r\n"); ++ ++#endif //End #if(EN_DUMPREG) ++ ++ ++} ++ ++ ++static RspErrEmType _SDMMC_EndProcess(IpOrder eIP, CmdEmType eCmdType, RspErrEmType eRspErr, BOOL_T bCloseClk, int Line) ++{ ++ U16_T u16RspErr = (U16_T)eRspErr; ++ U16_T u16IPErr = EV_STS_RIU_ERR | EV_STS_MIE_TOUT | EV_STS_DAT0_BUSY; ++ ++ /****** (1) Record Information *******/ ++ gst_RspStruct[eIP].u32ErrLine = (U32_T)Line; ++ gst_RspStruct[eIP].u8RspSize = (U8_T)CARD_REG(A_CMD_RSP_SIZE_REG(eIP)); ++ gst_RspStruct[eIP].eErrCode = eRspErr; ++ ++ /****** (2) Dump and the Reg Info + Reset IP *******/ ++ if ( u16RspErr && gb_StopWProc[eIP] ) ++ { ++ eRspErr = EV_SWPROC_ERR; ++ _REG_ResetIP(eIP); ++ } ++ else if( u16RspErr & u16IPErr ) //SD IP Error ++ { ++ _SDMMC_REG_Dump(eIP); ++ _REG_ResetIP(eIP); ++ } ++ else if( u16RspErr & M_SD_ERRSTS ) //SD_STS Reg Error ++ { ++ //Do Nothing ++ } ++ ++ /****** (3) Close clock and DMA Stop function ******/ ++ if(bCloseClk && !gb_SDIODevice[eIP]) ++ CARD_REG_CLRBIT(A_SD_MODE_REG(eIP), R_CLK_EN | R_DMA_RD_CLK_STOP); ++ ++ return eRspErr; ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC HAL Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetDataWidth ++* @author jeremy.wang (2015/7/9) ++* Desc: According as Data Bus Width to Set IP DataWidth ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eBusWidth : 1BIT/4BITs/8BITs ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetDataWidth(IpOrder eIP, SDMMCBusWidthEmType eBusWidth) ++{ ++ gu16_SD_MODE_DatLine[eIP] = (U16_T)eBusWidth; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetBusTiming ++* @author jeremy.wang (2015/7/29) ++* Desc: ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetBusTiming(IpOrder eIP, BusTimingEmType eBusTiming) ++{ ++ switch ( eBusTiming ) ++ { ++ ++#if (EN_BYPASSMODE) ++ ++ case EV_BUS_LOW: ++ case EV_BUS_DEF: ++ gu16_DDR_MODE_REG[eIP] = 0; ++ gu16_DDR_MODE_REG_ForR2N[eIP] = gu16_DDR_MODE_REG[eIP] | R_PAD_IN_BYPASS; ++ break; ++ case EV_BUS_HS: ++ gu16_DDR_MODE_REG[eIP] = 0; ++ gu16_DDR_MODE_REG_ForR2N[eIP] = gu16_DDR_MODE_REG[eIP] | 0; ++ break; ++ default: ++ break; ++#else ++ //ADVANCE MODE(SDR/DDR) ==> Other can't run bypass mode ++ ++ case EV_BUS_LOW: ++ case EV_BUS_DEF: ++ case EV_BUS_HS: ++ gu16_DDR_MODE_REG[eIP] = (R_PAD_CLK_SEL|R_PAD_IN_SEL|R_FALL_LATCH); ++ gu16_DDR_MODE_REG_ForR2N[eIP] = gu16_DDR_MODE_REG[eIP] | R_PAD_IN_RDY_SEL | R_PRE_FULL_SEL0 | R_PRE_FULL_SEL1; ++ break; ++ case EV_BUS_SDR12: ++ break; ++ case EV_BUS_SDR25: ++ break; ++ case EV_BUS_SDR50: ++ break; ++ case EV_BUS_SDR104: ++ break; ++ case EV_BUS_DDR50: ++ break; ++ case EV_BUS_HS200: ++ break; ++ default: ++ break; ++#endif ++ ++ ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetNrcDelay ++* @author jeremy.wang (2015/7/9) ++* Desc: According as Current Clock to Set Nrc Delay ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param u32RealClk : Real Clock ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetNrcDelay(IpOrder eIP, U32_T u32RealClk) ++{ ++ ++ if( u32RealClk >= 8000000 ) //>=8MHz ++ gu16_WT_NRC[eIP] = 1; ++ else if( u32RealClk >= 4000000 ) //>=4MHz ++ gu16_WT_NRC[eIP] = 2; ++ else if( u32RealClk >= 2000000 ) //>=2MHz ++ gu16_WT_NRC[eIP] = 4; ++ else if( u32RealClk >= 1000000 ) //>=1MHz ++ gu16_WT_NRC[eIP] = 8; ++ else if( u32RealClk >= 400000 ) //>=400KHz ++ gu16_WT_NRC[eIP] = 20; ++ else if( u32RealClk >= 300000 ) //>=300KHz ++ gu16_WT_NRC[eIP] = 27; ++ else if( u32RealClk >= 100000 ) //>=100KHz ++ gu16_WT_NRC[eIP] = 81; ++ else if(u32RealClk==0) ++ gu16_WT_NRC[eIP] = 100; //Default ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetCmdToken ++* @author jeremy.wang (2015/7/8) ++* Desc: Set Cmd Token ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param u8Cmd : SD Command ++* @param u32Arg : SD Argument ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetCmdToken(IpOrder eIP, U8_T u8Cmd, U32_T u32Arg) ++{ ++ gst_RspStruct[eIP].u8Cmd = u8Cmd; ++ gst_RspStruct[eIP].u32Arg = u32Arg; ++ ++ CARD_REG(A_CFIFO_OFFSET(eIP, 0)) = (((U8_T)(u32Arg>>24))<<8) | (0x40 + u8Cmd); ++ CARD_REG(A_CFIFO_OFFSET(eIP, 1)) = (((U8_T)(u32Arg>>8))<<8) | ((U8_T)(u32Arg>>16)); ++ CARD_REG(A_CFIFO_OFFSET(eIP, 2)) = (U8_T)u32Arg; ++ ++ TR_H_SDMMC(sdmmc_print("[S_")); ++ TR_H_SDMMC(sdmmc_print("%u", eIP)); ++ TR_H_SDMMC(sdmmc_print("] CMD_")); ++ TR_H_SDMMC(sdmmc_print("%u", u8Cmd)); ++ ++ TR_H_SDMMC(sdmmc_print(" (")); ++ TR_H_SDMMC(sdmmc_print("0x%08X", u32Arg)); ++ TR_H_SDMMC(sdmmc_print(")")); ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_GetRspToken ++* @author jeremy.wang (2015/7/9) ++* Desc: Get Command Response Info ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return RspStruct* : Response Struct ++----------------------------------------------------------------------------------------------------------*/ ++RspStruct* Hal_SDMMC_GetRspToken(IpOrder eIP) ++{ ++ U8_T u8Pos; ++ ++ TR_H_SDMMC(sdmmc_print(" =>RSP: (")); ++ TR_H_SDMMC(sdmmc_print("0x%04X", (U16_T)gst_RspStruct[eIP].eErrCode)); ++ TR_H_SDMMC(sdmmc_print(")\r\n")); ++ ++ for(u8Pos=0; u8Pos<0x10; u8Pos++ ) ++ gst_RspStruct[eIP].u8ArrRspToken[u8Pos] = 0; ++ ++ TR_H_SDMMC(sdmmc_print("[")); ++ ++ for(u8Pos=0; u8Pos< gst_RspStruct[eIP].u8RspSize; u8Pos++) ++ { ++ gst_RspStruct[eIP].u8ArrRspToken[u8Pos] = _BUF_GetByteFromRegAddr((volatile void *)A_SD_CFIFO_POS(eIP), u8Pos); ++ TR_H_SDMMC(sdmmc_print("0x%02X", gst_RspStruct[eIP].u8ArrRspToken[u8Pos])); ++ TR_H_SDMMC(sdmmc_print(", ")); ++ ++ } ++ ++ TR_H_SDMMC(sdmmc_print("]\r\n\r\n")); ++ ++ return &gst_RspStruct[eIP]; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_TransCmdSetting ++* @author jeremy.wang (2015/7/15) ++* Desc: For Data Transfer Setting ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eTransType : CIFD/DMA/ADMA/NONE ++* @param u16BCnt : Block Cnt ++* @param u16BlkSize : Block Size ++* @param u32BufAddr : Memory Address or DMA Table Address (32bits) ++* @param pu8Buf : If run CIFD, it neet the buf pointer to do io between CIFD and Buf ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_TransCmdSetting(IpOrder eIP, TransEmType eTransType, U16_T u16BlkCnt, U16_T u16BlkSize, volatile U32_T u32BufAddr, volatile U8_T *pu8Buf) ++{ ++ U32_T u32_TranLen = u16BlkCnt * u16BlkSize; ++ ++ CARD_REG(A_BLK_SIZE_REG(eIP)) = u16BlkSize; ++ ++ if (eTransType==EV_ADMA) ++ { ++ CARD_REG(A_JOB_BLK_CNT_REG(eIP)) = 1; //ADMA BLK_CNT = 1 ++ CARD_REG(A_DMA_LEN_15_0_REG(eIP)) = 0x10; //ADMA Fixed Value = 0x10 ++ CARD_REG(A_DMA_LEN_31_16_REG(eIP)) = 0; ++ } ++ else //R2N or DMA ++ { ++ CARD_REG(A_JOB_BLK_CNT_REG(eIP)) = u16BlkCnt; ++ CARD_REG(A_DMA_LEN_15_0_REG(eIP)) = (U16_T)(u32_TranLen & 0xFFFF); ++ CARD_REG(A_DMA_LEN_31_16_REG(eIP)) = (U16_T)(u32_TranLen >> 16); ++ } ++ ++ if( (eTransType== EV_DMA) || (eTransType==EV_ADMA) ) ++ { ++ CARD_REG(A_DMA_ADDR_15_0_REG(eIP)) = (U16_T)(u32BufAddr & 0xFFFF); ++ CARD_REG(A_DMA_ADDR_31_16_REG(eIP)) = (U16_T)(u32BufAddr >> 16); ++ } ++ else //CIFD (R2N) ++ { ++ gpu8Buf[eIP] = pu8Buf; ++ } ++ ++} ++ ++#if EN_HALT ++//dump current key registers status and disable UART for debugging. ++void halt(int eIP) ++{ ++ _SDMMC_REG_Dump(eIP); ++ msleep(1000); ++ *((U16_T*)0xFD001C24) &= ~BIT11_T; ++ while(1); ++} ++#else ++#define HALT(eIP) ++#endif ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SendCmdAndWaitProcess ++* @author jeremy.wang (2015/7/14) ++* Desc: Send SD Command and Waiting for Process ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eTransType : CIFD/DMA/ADMA/NONE ++* @param eCmdType : CMDRSP/READ/WRITIE ++* @param eRspType : R1/R2/R3/... ++* @param bCloseClk : Close Clock or not ++* ++* @return RspErrEmType : Response Error Code ++----------------------------------------------------------------------------------------------------------*/ ++RspErrEmType Hal_SDMMC_SendCmdAndWaitProcess(IpOrder eIP, TransEmType eTransType, CmdEmType eCmdType, SDMMCRspEmType eRspType, BOOL_T bCloseClk) ++{ ++ U32_T u32WaitMS = WT_EVENT_RSP; ++ U16_T u16WaitMIEEvent = R_CMD_END; ++ CARD_REG(A_CMD_RSP_SIZE_REG(eIP)) = V_CMD_SIZE_INIT | ((U8_T)eRspType); ++ CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) = V_MIE_PATH_INIT | _REG_GetMIEFunCtlSetting(eIP); ++ if (eTransType == EV_ADMA) { ++ CARD_REG(A_SD_MODE_REG(eIP)) = V_SD_MODE_INIT | (eTransType>>8) | gu16_SD_MODE_DatLine[eIP] | ((U8_T)(eTransType & R_DMA_RD_CLK_STOP)); // R_STOP_BLK); ++ } ++ else { ++ CARD_REG(A_SD_MODE_REG(eIP)) = V_SD_MODE_INIT | (eTransType>>8) | gu16_SD_MODE_DatLine[eIP]; ++ } ++ CARD_REG(A_SD_CTL_REG(eIP)) = V_SD_CTL_INIT | (eRspType>>12) | (eCmdType>>4) | ((U8_T)(eTransType & R_ADMA_EN) | BIT09_T | R_CMD_EN); ++ CARD_REG(A_SDIO_MODE_REG(eIP)) = V_SDIO_MODE_INIT | gu16_SDIO_MODE_IntMode[eIP]; ++ ++ CARD_REG_CLRBIT(A_BOOT_MOD_REG(eIP), R_BOOT_MODE); ++ CARD_REG_CLRBIT(A_BOOT_REG(eIP), (R_NAND_BOOT_EN | R_BOOTSRAM_ACCESS_SEL | R_IMI_SEL)); ++ ++ CARD_REG(A_MMA_PRI_REG_REG(eIP)) = V_MMA_PRI_INIT; ++ CARD_REG(A_DDR_MOD_REG(eIP)) = V_DDR_MODE_INIT | (eTransType==EV_CIF ? gu16_DDR_MODE_REG_ForR2N[eIP] : gu16_DDR_MODE_REG[eIP]); ++ ++ Hal_Timer_uDelay(gu16_WT_NRC[eIP]); ++ ++ if( _REG_ClearSDSTS(eIP, RT_CLEAN_SDSTS) || _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__);; ++ ++#if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_SetMIEIntEn(eIP, V_MIE_INT_EN_INIT);//consider do this only once ++#endif ++ ++#if EN_HALT ++ if(gst_RspStruct[eIP].u8Cmd == 8) ++ { ++ printk("stop for cmd:%d\n", gst_RspStruct[eIP].u8Cmd); ++ halt(eIP); ++ } ++#endif ++ ++ if(eCmdType==EV_CMDREAD) ++ { ++ if (eTransType!=EV_CIF) ++ { ++ u16WaitMIEEvent |= R_DATA_END; ++ u32WaitMS += WT_EVENT_READ; ++ } ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_DTRX_EN ); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_DTRX_EN | R_JOB_START) ); ++ } ++ else ++ { ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_JOB_START) ); ++ } ++ ++ if(_REG_WaitEvent(eIP, EV_MIE, u16WaitMIEEvent, u32WaitMS)) { ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ } ++ //====== Special Case for R2N CIFD Read Transfer ====== ++ if( (eCmdType==EV_CMDREAD) && (eTransType==EV_CIF) ) ++ { ++ if(_BUF_CIFD_WaitEvent(eIP, eCmdType, gpu8Buf[eIP])) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ if(_REG_WaitEvent(eIP, EV_MIE, R_DATA_END, WT_EVENT_READ)) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ } ++ ++ if( (eRspType == EV_R1B)) ++ { ++ if( _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__); ++ if( _REG_WaitDat0HI(eIP, WT_DAT0HI_END) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_DAT0_BUSY, bCloseClk, __LINE__); ++ } ++ else if( (eRspType == EV_R3) || (eRspType == EV_R4) ) // For IP CRC bug ++ CARD_REG(A_SD_STS_REG(eIP)) = R_CMDRSP_CERR; //Clear CMD CRC Error ++ ++ if( (eCmdType == EV_CMDWRITE) && (!M_REG_STSERR(eIP)) ) ++ { ++ if( _REG_ClearSDSTS(eIP, RT_CLEAN_SDSTS) || _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__); ++ ++ CARD_REG(A_SD_CTL_REG(eIP)) = V_SD_CTL_INIT |(eCmdType>>4) | ((U8_T)(eTransType & R_ADMA_EN)); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_DTRX_EN ); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_DTRX_EN | R_JOB_START) ); ++ ++ //====== Special Case for R2N CIFD Write Transfer ====== ++ if ( (eTransType==EV_CIF) && _BUF_CIFD_WaitEvent(eIP, eCmdType, gpu8Buf[eIP]) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ if(_REG_WaitEvent(eIP, EV_MIE, R_DATA_END, WT_EVENT_WRITE)) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ } ++ ++ return _SDMMC_EndProcess(eIP, eCmdType, (RspErrEmType)M_REG_STSERR(eIP), bCloseClk, __LINE__); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_RunBrokenDmaAndWaitProcess ++* @author jeremy.wang (2015/7/29) ++* Desc: For Broken DMA Data Transfer ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eCmdType : READ/WRITE ++* ++* @return RspErrEmType : Response Error Code ++----------------------------------------------------------------------------------------------------------*/ ++RspErrEmType Hal_SDMMC_RunBrokenDmaAndWaitProcess(IpOrder eIP, CmdEmType eCmdType) ++{ ++ U32_T u32WaitMS = 0; ++ ++ if(eCmdType==EV_CMDREAD) ++ u32WaitMS = WT_EVENT_READ; ++ else if(eCmdType==EV_CMDWRITE) ++ u32WaitMS = WT_EVENT_WRITE; ++ ++ if ( _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, FALSE, __LINE__); ++ ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_CMD_EN ); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_DTRX_EN | R_JOB_START) ); ++ ++ if ( _REG_WaitEvent(eIP, EV_MIE, R_DATA_END, u32WaitMS) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, FALSE, __LINE__); ++ ++ return _SDMMC_EndProcess(eIP, eCmdType, (RspErrEmType)M_REG_STSERR(eIP), FALSE, __LINE__); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_ADMASetting ++* @author jeremy.wang (2015/7/13) ++* Desc: For ADMA Data Transfer Settings ++* ++* @param pDMATable : DMA Table memory address pointer ++* @param u8Item : DMA Table Item 0 ~ ++* @param u32SubLen : DMA Table DMA Len ++* @param u32SubBCnt : DMA Table Job Blk Cnt ++* @param u32SubAddr : DMA Table DMA Addr ++* @param u8MIUSel : MIU Select ++* @param bEnd : End Flag ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_ADMASetting(volatile void *pDMATable, U8_T u8Item, U32_T u32SubLen, U16_T u16SubBCnt, U32_T u32SubAddr, U8_T u8MIUSel, BOOL_T bEnd) ++{ ++ //U16_T u16Pos; ++ ++ AdmaDescStruct* pst_AdmaDescStruct = (AdmaDescStruct*) pDMATable; ++ ++ pst_AdmaDescStruct = (pst_AdmaDescStruct+u8Item); ++ memset(pst_AdmaDescStruct, 0, sizeof(AdmaDescStruct)); ++ ++ pst_AdmaDescStruct->u32_DmaLen = u32SubLen; ++ pst_AdmaDescStruct->u32_Address = u32SubAddr; ++ pst_AdmaDescStruct->u32_JobCnt = u16SubBCnt; ++ pst_AdmaDescStruct->u32_MiuSel = u8MIUSel; ++ pst_AdmaDescStruct->u32_End = bEnd; ++ ++ /*sdmmc_print("\r\n"); ++ sdmmc_print("gpst_AdmaDescStruct Pos=("); ++ sdmmc_print("0x%08X", (U32_T)pst_AdmaDescStruct); ++ sdmmc_print(")\r\n"); ++ ++ for(u16Pos=0; u16Pos<192 ; u16Pos++) ++ { ++ if( (u16Pos%12)==0) ++ (sdmmc_print("\r\n")); ++ ++ (sdmmc_print("[")); ++ (sdmmc_print("0x%02X", *(pu8Buf+u16Pos))); ++ (sdmmc_print("]")); ++ ++ }*/ ++ ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Operation Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_ClkCtrl ++ * @author jeremy.wang (2015/11/4) ++ * Desc: Enable IP clock output ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ * @param u16DelayMs : Delay ms to Specail Purpose ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_ClkCtrl(IpOrder eIP, BOOL_T bEnable, U16_T u16DelayMs) ++{ ++ CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) = V_MIE_PATH_INIT | _REG_GetMIEFunCtlSetting(eIP); ++ ++ if( bEnable ) ++ CARD_REG_SETBIT(A_SD_MODE_REG(eIP), R_CLK_EN); ++ else ++ CARD_REG_CLRBIT(A_SD_MODE_REG(eIP), R_CLK_EN); ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_Reset ++* @author jeremy.wang (2015/7/17) ++* Desc: Reset IP to avoid IP dead ++* ++* @param eIP : FCIE1/FCIE2/... ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_Reset(IpOrder eIP) ++{ ++ _REG_ResetIP(eIP); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_StopProcessCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Stop process to avoid long time waiting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_StopProcessCtrl(IpOrder eIP, BOOL_T bEnable) ++{ ++ gb_StopWProc[eIP] = bEnable; ++ ++#if(EN_BIND_CARD_INT) ++ if ( gb_StopWProc[eIP] ) ++ Hal_CARD_INT_StopWaitMIEEventCtrl(eIP, TRUE); ++ else ++ Hal_CARD_INT_StopWaitMIEEventCtrl(eIP, FALSE); ++#endif ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_OtherPreUse ++* @author jeremy.wang (2015/7/17) ++* Desc: Use this for avoid SD/EMMC to use FCIE at the same time ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return BOOL_T : (TRUE: Other driver usnig) ++----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_SDMMC_OtherPreUse(IpOrder eIP) ++{ ++ ++ if ( CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) & R_EMMC_EN ) ++ return (TRUE); ++ ++ if ( !(CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) & (R_SD_EN | R_SDIO_MODE)) ) //Not SD Path ++ return (TRUE); ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_ErrGroup ++ * @author jeremy.wang (2015/10/28) ++ * Desc: transfer response error type to group error type ++ * ++ * @param eRspErrType : Response Error Type ++ * ++ * @return ErrGrpEmType : Group Error Type ++ ----------------------------------------------------------------------------------------------------------*/ ++ErrGrpEmType Hal_SDMMC_ErrGroup(RspErrEmType eRspErrType) ++{ ++ ++ switch((U16_T)eRspErrType) ++ { ++ case EV_STS_OK: ++ return EV_EGRP_OK; ++ ++ case EV_STS_WR_TOUT: ++ case EV_STS_NORSP: ++ case EV_STS_RD_TOUT: ++ case EV_STS_RIU_ERR: ++ case EV_STS_DAT0_BUSY: ++ case EV_STS_MIE_TOUT: ++ return EV_EGRP_TOUT; ++ ++ case EV_STS_RD_CERR: ++ case EV_STS_WD_CERR: ++ case EV_STS_RSP_CERR: ++ return EV_EGRP_COMM; ++ ++ default: ++ return EV_EGRP_OTHER; ++ } ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Information ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_DumpMemTool ++* @author jeremy.wang (2015/7/29) ++* Desc: Help us to dump memory ++* ++* @param u8ListNum : Each List Num include 16 bytes ++* @param pu8Buf : Buffer Pointer ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_DumpMemTool(U8_T u8ListNum, volatile U8_T *pu8Buf) ++{ ++ U16_T u16Pos=0; ++ U8_T u8ListPos; ++ U32_T u32BufAddr = (U32_T)pu8Buf; ++ sdmmc_print("\r\n $[Prt MEM_DATA: 0x%08X ]\r\n", u32BufAddr); ++ ++ for(u8ListPos=0 ; u8ListPos >8); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_GetMIEEvent ++* @author jeremy.wang (2015/7/31) ++* Desc: Monitor MIE Event for debug ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return U16_T : Return MIE Event ++----------------------------------------------------------------------------------------------------------*/ ++U16_T Hal_SDMMC_GetMIEEvent(IpOrder eIP) ++{ ++ return CARD_REG(A_MIE_EVENT_REG(eIP)); ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC SDIO Setting ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SDIODeviceCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Enable SDIO device for do something for SDIO case ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SDIODeviceCtrl(IpOrder eIP, BOOL_T bEnable) ++{ ++ if(bEnable) ++ gb_SDIODevice[eIP] = TRUE; ++ else ++ gb_SDIODevice[eIP] = FALSE; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SDIOIntDetCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Enable SDIO interrupt detection ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SDIOIntDetCtrl(IpOrder eIP, BOOL_T bEnable) ++{ ++ if (gb_SDIODevice[eIP]) ++ { ++ if(bEnable) ++ { ++ CARD_REG_SETBIT(A_SDIO_DET_ON(eIP), R_SDIO_DET_ON); ++ } ++ else ++ { ++ CARD_REG_CLRBIT(A_SDIO_DET_ON(eIP), R_SDIO_DET_ON); ++ } ++ } ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetSDIOIntBeginSetting ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Set SDIO Int begin setting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u8Cmd : SDIO Command ++ * @param u32Arg : SDIO Argument ++ * @param eCmdType : CMDRSP/READ/WRITE ++ * @param u16BlkCnt : Block Cnt ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetSDIOIntBeginSetting(IpOrder eIP, U8_T u8Cmd, U32_T u32Arg, CmdEmType eCmdType, U16_T u16BlkCnt) ++{ ++ BOOL_T bSDIOAbortMode = (u8Cmd == 52) && ( (u32Arg & 0x83FFFE00) == 0x80000C00); ++ ++ gu16_SDIO_MODE_IntMode[eIP] = 0; ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(eCmdType != EV_CMDRSP) ++ { ++ if(u16BlkCnt == 1) ++ gu16_SDIO_MODE_IntMode[eIP] = R_SDIO_INT_MOD1; ++ else ++ gu16_SDIO_MODE_IntMode[eIP] = R_SDIO_INT_MOD0 | R_SDIO_INT_MOD1; ++ } ++ else if ( (u8Cmd == 12) || bSDIOAbortMode) ++ { ++ gu16_SDIO_MODE_IntMode[eIP] = R_SDIO_INT_MOD0; ++ } ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetSDIOIntEndSetting ++ * @author jeremy.wang (2015/10/29) ++ * Desc: ++ * ++ * @param eIP : ++ * @param eRspErr : ++ * @param u16BlkCnt : ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetSDIOIntEndSetting(IpOrder eIP, RspErrEmType eRspErr, U16_T u16BlkCnt) ++{ ++ U16_T u16RspErr = (U16_T)eRspErr; ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(u16BlkCnt>1) ++ { ++ ++ } ++ if(u16RspErr>0) ++ { ++ } ++ } ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Interrupt Setting ++//*********************************************************************************************************** ++ ++#if(EN_BIND_CARD_INT) ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_MIEIntCtrl ++ * @author jeremy.wang (2015/11/2) ++ * Desc: Enable MIE event interrupt control ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_MIEIntCtrl(IpOrder eIP, BOOL_T bEnable) ++{ ++ Hal_CARD_INT_MIEIntCtrl(eIP, bEnable); ++} ++#endif // End of EN_BIND_CARD_INT +diff --git a/drivers/sstar/sdmmc/src/infinity2m/hal_card_platform.c b/drivers/sstar/sdmmc/src/infinity2m/hal_card_platform.c +new file mode 100755 +index 000000000000..c9b65a0dbcc9 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/infinity2m/hal_card_platform.c +@@ -0,0 +1,808 @@ ++/* ++* hal_card_platform_iNF6.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF5.c ++ * @author jeremy.wang (2016/11/29) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++#include "gpio.h" ++#include "padmux.h" ++#include "mdrv_gpio.h" ++#include "mdrv_padmux.h" ++#include "hal_card_platform_pri_config.h" ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++#include "mdrv_puse.h" ++#endif ++ ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00)//1038h ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00)//103Ch ++#define A_GPI_INT_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E80)//103Dh ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700)//0Eh ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780)//0Fh ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00)//101Eh ++//#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900)//1132h ++#define A_SC_GP_CTRL_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89980)//1133h ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++ ++#define REG_CLK_IP_SDIO (0x45) ++ ++ ++#define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ ++static volatile U16_T _gu16PowerPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++static volatile U16_T _gu16CdzPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_IPOnceSetting(IpOrder eIP) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++#if (FORCE_SWITCH_PAD) ++ // reg_all_pad_in => Close ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); ++#endif ++ ++ // Clock Source ++ if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT03_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_InitPADPin(IpOrder eIP, PadOrder ePAD) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD) ++ { ++ // Driving for PAD_SD_CLK, PAD_SD_CMD, PAD_SD_D0 ~ PAD_SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 low , 1 high ++ } ++ else if (ePadSel == PAD_GPIO) ++ { ++ // Driving can't be adjusted (Always be 4mA) ++ } ++ ++ // Pull Down ++ Hal_CARD_PullPADPin(eIP, ePAD, EV_PULLDOWN); ++} ++ ++BOOL_T Hal_CARD_GetPadInfoCdzPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ int puse; ++ ++ if (eIP == IP_ORDER_0) ++ { ++ puse = MDRV_PUSE_SDIO0_CDZ; ++ } ++ else ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ ++ *nPadNum = PAD_UNKNOWN; ++ return FALSE; ++ } ++ ++ *nPadNum = mdrv_padmux_getpad(puse); ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++BOOL_T Hal_CARD_GetPadInfoPowerPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ int puse; ++ ++ if (eIP == IP_ORDER_0) ++ { ++ puse = MDRV_PUSE_SDIO0_PWR; ++ } ++ else ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ ++ *nPadNum = PAD_UNKNOWN; ++ return FALSE; ++ } ++ ++ *nPadNum = mdrv_padmux_getpad(puse); ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++void Hal_CARD_ConfigSdPad(IpOrder eIP, PadOrder ePAD) //Hal_CARD_SetPADToPortPath ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE_1); ++ } ++ else if (ePadSel == PAD_GPIO) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE_2); ++ } ++ } ++ } ++ ++#else // ++ ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), (BIT09_T|BIT08_T)); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); ++ } ++ else if (ePadSel == PAD_GPIO) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), (BIT09_T|BIT08_T)); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT09_T); ++ } ++ } ++ ++#endif ++} ++ ++void Hal_CARD_ConfigPowerPad(IpOrder eIP, U16_T nPadNum) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_TTL0: ++ ++ //make sure it's reg_fuart_mode != 3 ++ if ((CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03)) & (BIT02_T | BIT01_T | BIT00_T)) == (BIT01_T | BIT00_T)) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), (BIT02_T | BIT01_T | BIT00_T)); ++ } ++ ++ break; ++ ++ case PAD_GPIO0: ++ // ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++ ++ // Default power off ++ Hal_CARD_PowerOff(eIP, 0); ++} ++ ++void Hal_CARD_PullPADPin(IpOrder eIP, PadOrder ePAD, PinPullEmType ePinPull) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ // Pull Disable - D3, D2, D1, D0, CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); ++ ++ // PAD -> GPIO mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD_CLK, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_CMD, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D0, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D1, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D2, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D3, PINMUX_FOR_GPIO_MODE); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT09_T|BIT08_T); // SDIO mode = 0 ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD_CLK); ++ MDrv_GPIO_Set_Low(PAD_SD_CMD); ++ MDrv_GPIO_Set_Low(PAD_SD_D0); ++ MDrv_GPIO_Set_Low(PAD_SD_D1); ++ MDrv_GPIO_Set_Low(PAD_SD_D2); ++ MDrv_GPIO_Set_Low(PAD_SD_D3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT04_T); // output:0 ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT04_T); // output:0 ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT04_T); // output:0 ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT04_T); // output:0 ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT04_T); // output:0 ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT04_T); // output:0 ++#endif ++ } ++ else if (ePinPull == EV_PULLUP) ++ { ++ // Pull Enable - D3, D2, D1, D0, CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD_CLK); ++ MDrv_GPIO_Pad_Odn(PAD_SD_CMD); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D0); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D1); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D2); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE_1); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT09_T|BIT08_T); // SDIO mode = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); // SDIO mode = 1 ++#endif ++ } ++ } ++ else if (ePadSel == PAD_GPIO) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ // PAD -> GPIO mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_GPIO6, PINMUX_FOR_GPIO_MODE); // CLK ++ MDrv_GPIO_PadVal_Set(PAD_GPIO7, PINMUX_FOR_GPIO_MODE); // CMD ++ MDrv_GPIO_PadVal_Set(PAD_GPIO5, PINMUX_FOR_GPIO_MODE); // D0 ++ MDrv_GPIO_PadVal_Set(PAD_GPIO4, PINMUX_FOR_GPIO_MODE); // D1 ++ MDrv_GPIO_PadVal_Set(PAD_GPIO9, PINMUX_FOR_GPIO_MODE); // D2 ++ MDrv_GPIO_PadVal_Set(PAD_GPIO8, PINMUX_FOR_GPIO_MODE); // D3 ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT09_T|BIT08_T); // SDIO mode = 0 ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_GPIO6); // CLK ++ MDrv_GPIO_Set_Low(PAD_GPIO7); // CMD ++ MDrv_GPIO_Set_Low(PAD_GPIO5); // D0 ++ MDrv_GPIO_Set_Low(PAD_GPIO4); // D1 ++ MDrv_GPIO_Set_Low(PAD_GPIO9); // D2 ++ MDrv_GPIO_Set_Low(PAD_GPIO8); // D3 ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x06), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x06), BIT04_T); // output:0 ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x07), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x07), BIT04_T); // output:0 ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x05), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x05), BIT04_T); // output:0 ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x04), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x04), BIT04_T); // output:0 ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x09), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x09), BIT04_T); // output:0 ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x08), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x08), BIT04_T); // output:0 ++#endif ++ } ++ else if (ePinPull == EV_PULLUP) ++ { ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_GPIO6); // CLK ++ MDrv_GPIO_Pad_Odn(PAD_GPIO7); // CMD ++ MDrv_GPIO_Pad_Odn(PAD_GPIO5); // D0 ++ MDrv_GPIO_Pad_Odn(PAD_GPIO4); // D1 ++ MDrv_GPIO_Pad_Odn(PAD_GPIO9); // D2 ++ MDrv_GPIO_Pad_Odn(PAD_GPIO8); // D3 ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x06), BIT05_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x07), BIT05_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x05), BIT05_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x04), BIT05_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x09), BIT05_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x08), BIT05_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE_2); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT09_T|BIT08_T); // SDIO mode = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT09_T); // SDIO mode = 1 ++#endif ++ } ++ } ++ } ++} ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_SetClock(IpOrder eIP, U32_T u32ClkFromIPSet) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++ if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT03_T); //[7]: select BOOT clock source (glitch free) - 0: select BOOT clock 12MHz (xtali), 1: select FCIE/SPI clock source ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK, 0x45), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++} ++ ++#ifdef CONFIG_PM_SLEEP ++//*********************************************************************************************************** ++// Get pm clock from Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_GetClock(U32_T u32SlotNo, U32_T *pu32PmIPClk, U32_T *pu32PmBlockClk) ++{ ++ ++} ++ ++//*********************************************************************************************************** ++// Set pm clock to Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_setClock(U32_T u32SlotNo, U32_T u32PmIPClk, U32_T u32PmBlockClk) ++{ ++ ++} ++#endif ++ ++U32_T Hal_CARD_FindClockSetting(IpOrder eIP, U32_T u32ReffClk) ++{ ++ U8_T u8LV = 0; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ return u32RealClk; ++} ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_PowerOn(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_Low(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_TTL0: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x20), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x20), BIT04_T); // output:0 ++ break; ++ ++ case PAD_GPIO0: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x00), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x00), BIT04_T); // output:0 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++void Hal_CARD_PowerOff(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_High(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_TTL0: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x20), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x20), BIT04_T); // output:1 ++ break; ++ ++ case PAD_GPIO0: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x00), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x00), BIT04_T); // output:1 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_ConfigCdzPad(IpOrder eIP, U16_T nPadNum) // Hal_CARD_InitGPIO ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++// PADMUX ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ // ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++// GPIO ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ // Whatever mdrv_padmux_active is ON or OFF, just set it to input mode. ++ MDrv_GPIO_Pad_Odn(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // This is a special case, SD_CDZ mode ON/OFF status will use different GIC path. ++ // We must switch ON - SD_CDZ mode ++ if (nPadNo == PAD_PM_SD_CDZ) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ } ++ ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++} ++ ++BOOL_T Hal_CARD_GetCdzState(IpOrder eIP) // Hal_CARD_GetGPIOState ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ U8_T nLv = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ } ++ ++ nPadNo = _gu16CdzPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use CDZ pin. ++ goto fail; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ nLv = MDrv_GPIO_Pad_Read(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ break; ++ } ++ ++#endif ++ ++ if (!nLv) // Low Active ++ { ++ return TRUE; ++ } ++ ++fail: ++ ++ return FALSE; ++} ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr, U8_T* pu8MIUSel) ++{ ++ return u32Addr-0x20000000; ++} +diff --git a/drivers/sstar/sdmmc/src/infinity5/hal_card_platform.c b/drivers/sstar/sdmmc/src/infinity5/hal_card_platform.c +new file mode 100755 +index 000000000000..d0f67b1c01d7 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/infinity5/hal_card_platform.c +@@ -0,0 +1,967 @@ ++/* ++* hal_card_platform_iNF5.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF5.c ++ * @author jeremy.wang (2016/11/29) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++#include "gpio.h" ++ ++// #include "padmux.h" ++// Mask it, beacuse of ++// drivers/sstar/include/infinity5/padmux.h:81:1: error: unknown type name ¡¥S32¡¦ ++// S32 HalPadSetVal(U32 u32PadID, U32 u32Mode); ++ ++#include "mdrv_gpio.h" ++#include "mdrv_padmux.h" ++#include "hal_card_platform_pri_config.h" ++ ++#include "mstar_chip.h" // For Hal_CARD_TransMIUAddr ++ ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00)//1038h ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00)//103Ch ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700)//0Eh ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780)//0Fh ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00)//101Eh ++#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900)//1132h ++#define A_SC_GP_CTRL_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89980)//1133h ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++#define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ ++static volatile U16_T _gu16PowerPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++static volatile U16_T _gu16CdzPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_IPOnceSetting(IpOrder eIP) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++#if (FORCE_SWITCH_PAD) ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); // reg_all_pad_in => Close ++#endif ++ ++ if (eIpSel == IP_SDIO) ++ { ++ //Enable Clock Source to avoid reset fail ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T | BIT09_T | BIT10_T); //sdio mode = 0 ++ } ++ else if (eIpSel == IP_FCIE) ++ { ++ //Enable Clock Source to avoid reset fail ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); //sd mode = 0 ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_InitPADPin(IpOrder eIP, PadOrder ePAD) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 ++ } ++ else if (ePadSel == PAD_NAND) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x30), BIT06_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 ++ } ++ else if (ePadSel == PAD_LCD) ++ { ++ // D0 - pe:[0x4c]bit0, se:[0x4e]bit0 ++ // D1 - pe:[0x4c]bit1, se:[0x4e]bit1 ++ // D2 - pe:[0x4c]bit2, se:[0x4e]bit2 ++ // D3 - pe:[0x4c]bit3, se:[0x4e]bit3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4c), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4e), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ // D0 - drv:[0x48]bit0, ie:[0x4a]bit0 ++ // D1 - drv:[0x48]bit1, ie:[0x4a]bit1 ++ // D2 - drv:[0x48]bit2, ie:[0x4a]bit2 ++ // D3 - drv:[0x48]bit3, ie:[0x4a]bit3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x48), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ // FIXME: This is very important to ENABLE input, or BLOCK CMDs (4-bit mode) will failed... ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4a), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ // CMD - pe:bit8, se:bit12 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT08_T|BIT12_T); ++ // CMD - drv:bit0, ie:bit4 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT00_T|BIT04_T); ++ // FIXME: This is very important to ENABLE input, or there'll no RSP for every CMDs... ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT04_T); ++ // FIXME: This is important to intialize all PADs before CLK to prevent a "FAKE" start bit '0' issued... ++ // CLK - pe:bit10, se:bit14 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT10_T|BIT14_T); ++ // CLK - drv:bit2, ie:bit6 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT02_T|BIT06_T); ++ } ++ else if (ePadSel == PAD_SNR) ++ { ++ // TODO: ++ } ++} ++ ++BOOL_T Hal_CARD_GetPadInfoCdzPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++BOOL_T Hal_CARD_GetPadInfoPowerPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++void Hal_CARD_ConfigSdPad(IpOrder eIP, PadOrder ePAD) //Hal_CARD_SetPADToPortPath ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sdio mode = 1 ++ } ++ else if (ePadSel == PAD_NAND) ++ { ++ // ++ } ++ else if (ePadSel == PAD_LCD) ++ { ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T | BIT08_T | BIT09_T | BIT10_T); //sd mode = 0, clear sdio mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T | BIT09_T); //sdio mode = 3 ++ } ++ else if (ePadSel == PAD_SNR) ++ { ++ // ++ } ++ } ++ else if (eIpSel == IP_FCIE) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode = 2 ++ } ++ else if (ePadSel == PAD_NAND) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT00_T); //reg_emmc_mode = 0 ++ ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd_mode2 = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd_mode1 = 1 ++ } ++ } ++} ++ ++void Hal_CARD_ConfigPowerPad(IpOrder eIP, U16_T nPadNum) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ // Not support ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ break; ++ ++ case PAD_PM_GPIO6: ++ break; ++ ++ case PAD_PM_GPIO12: ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++ ++ // Default power off ++ Hal_CARD_PowerOff(eIP, 0); ++} ++ ++void Hal_CARD_PullPADPin(IpOrder eIP, PadOrder ePAD, PinPullEmType ePinPull) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull dis ++ ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x78), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x78), BIT04_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x79), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x79), BIT04_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7A), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7A), BIT04_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7B), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7B), BIT04_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7C), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7C), BIT04_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7D), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7D), BIT04_T); // output:0 ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sdio mode1 = 0 ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull en ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sdio mode1 =1 ++ ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x78), BIT05_T); // input mode ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x79), BIT05_T); // input mode ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7A), BIT05_T); // input mode ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7B), BIT05_T); // input mode ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7C), BIT05_T); // input mode ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x7D), BIT05_T); // input mode ++ } ++ } ++ else if (ePadSel == PAD_NAND) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull dis ++ ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT01_T|BIT00_T); //reg_emmc_mode = 0 //rst=0 ++ // ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 // ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd mode1 = 0 ++ ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT04_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT04_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT04_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT04_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT04_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT04_T); // output:0 ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull en ++ ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // input mode ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // input mode ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // input mode ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // input mode ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // input mode ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT05_T); // input mode ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT00_T); //reg_emmc_mode = 0 ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd_mode2 = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd_mode1 = 1 ++ } ++ } ++ else if (ePadSel == PAD_LCD) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ // CLK - pe:bit10, se:bit14 ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT10_T|BIT14_T); ++ // CMD - pe:bit8, se:bit12 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT08_T|BIT12_T); ++ // D0 - pe:[0x4c]bit2, se:[0x4e]bit2 ++ // D1 - pe:[0x4c]bit3, se:[0x4e]bit3 ++ // D2 - pe:[0x4c]bit4, se:[0x4e]bit4 ++ // D3 - pe:[0x4c]bit5, se:[0x4e]bit5 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4c), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4e), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6a), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6a), BIT04_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x69), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x69), BIT04_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT04_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT04_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT04_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT04_T); // output:0 ++ ++ // Mode switch ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T | BIT09_T | BIT10_T); //sdio mode = 0 ++ ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ // D0 - pe:[0x4c]bit2, se:[0x4e]bit2 ++ // D1 - pe:[0x4c]bit3, se:[0x4e]bit3 ++ // D2 - pe:[0x4c]bit4, se:[0x4e]bit4 ++ // D3 - pe:[0x4c]bit5, se:[0x4e]bit5 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4c), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x4e), BIT00_T|BIT01_T|BIT02_T|BIT03_T); ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // input mode ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // input mode ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // input mode ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // input mode ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT00_T); //reg_emmc_mode = 0 ++ ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); //sd_mode = 0 ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x69), BIT05_T); // input mode ++ ++ // CMD - pe:bit8, se:bit12 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT08_T|BIT12_T); ++ ++ // TODO: This is important to intialize all PADs before CLK to prevent a "FAKE" start bit '0' issued... ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6a), BIT05_T); // input mode ++ ++ // CLK - pe:bit10, se:bit14 ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x47), BIT10_T|BIT14_T); ++ ++ // Mode switch ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T | BIT09_T| BIT10_T); //sdio mode = 3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T | BIT09_T); //sdio mode = 3 ++ } ++ } ++ else if (ePadSel == PAD_SNR) ++ { ++ // ++ } ++} ++ ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_SetClock(IpOrder eIP, U32_T u32ClkFromIPSet) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++ if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ /* ++ case CLK1_7: ++ break; ++ case CLK1_6: ++ break; ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ if (eIpSel == IP_FCIE) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T); // select clk_fcie_p ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK2_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK2_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK2_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ case CLK2_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T); //8 ++ break; ++ case CLK2_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT02_T); //9 ++ break; ++ case CLK2_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT03_T); //10 ++ break; ++ case CLK2_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK2_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T); //12 ++ break; ++ /* ++ case CLK1_7: ++ break; ++ case CLK1_6: ++ break; ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ } ++} ++ ++#ifdef CONFIG_PM_SLEEP ++//*********************************************************************************************************** ++// Get pm clock from Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_GetClock(U32_T u32SlotNo, U32_T *pu32PmIPClk, U32_T *pu32PmBlockClk) ++{ ++ ++} ++ ++//*********************************************************************************************************** ++// Set pm clock to Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_setClock(U32_T u32SlotNo, U32_T u32PmIPClk, U32_T u32PmBlockClk) ++{ ++ ++} ++#endif ++ ++U32_T Hal_CARD_FindClockSetting(IpOrder eIP, U32_T u32ReffClk) ++{ ++ U8_T u8LV = 0; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ return u32RealClk; ++} ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_PowerOn(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_Low(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:0 ++ break; ++ ++ case PAD_PM_GPIO6: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT00_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT01_T); // output:0 ++ break; ++ ++ case PAD_PM_GPIO12: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x0C), BIT00_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x0C), BIT01_T); // output:0 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++void Hal_CARD_PowerOff(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_High(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:1 ++ break; ++ ++ case PAD_PM_GPIO6: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT00_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT01_T); // output:1 ++ break; ++ ++ case PAD_PM_GPIO12: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x0C), BIT00_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x0C), BIT01_T); // output:1 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_ConfigCdzPad(IpOrder eIP, U16_T nPadNum) // Hal_CARD_InitGPIO ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++// PADMUX ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ // ++ break; ++ ++ case PAD_PM_IRIN: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x1C), BIT04_T); // PM_IRIN as GPIO ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++// GPIO ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ // Whatever mdrv_padmux_active is ON or OFF, just set it to input mode. ++ MDrv_GPIO_Pad_Odn(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ break; ++ ++ case PAD_PM_IRIN: ++ // ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x14), BIT00_T); // input mode ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // This is a special case, SD_CDZ mode ON/OFF status will use different GIC path. ++ // We must switch ON - SD_CDZ mode ++ if (nPadNo == PAD_PM_SD_CDZ) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ } ++ ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++} ++ ++BOOL_T Hal_CARD_GetCdzState(IpOrder eIP) // Hal_CARD_GetGPIOState ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ U8_T nLv = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ } ++ ++ nPadNo = _gu16CdzPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use CDZ pin. ++ goto fail; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ nLv = MDrv_GPIO_Pad_Read(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ break; ++ ++ case PAD_PM_IRIN: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x14)) & BIT02_T; ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ break; ++ } ++ ++#endif ++ ++ if (!nLv) // Low Active ++ { ++ return TRUE; ++ } ++ ++fail: ++ ++ return FALSE; ++} ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr, U8_T* pu8MIUSel) ++{ ++#ifdef MSTAR_MIU2_BUS_BASE ++ if( u32Addr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ u32Addr -= MSTAR_MIU2_BUS_BASE; ++ if(pu8MIUSel) *pu8MIUSel = 2; ++ } ++ else ++#endif ++#ifdef MSTAR_MIU1_BUS_BASE ++ if( u32Addr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ u32Addr -= MSTAR_MIU1_BUS_BASE; ++ if(pu8MIUSel) *pu8MIUSel = 1; ++ } ++ else // MIU0 ++#endif ++ { ++ u32Addr -= MSTAR_MIU0_BUS_BASE; ++ if(pu8MIUSel) *pu8MIUSel = 0; ++ } ++ ++ return u32Addr; ++} +diff --git a/drivers/sstar/sdmmc/src/infinity6/hal_card_platform.c b/drivers/sstar/sdmmc/src/infinity6/hal_card_platform.c +new file mode 100755 +index 000000000000..e37db4373181 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/infinity6/hal_card_platform.c +@@ -0,0 +1,903 @@ ++/* ++* hal_card_platform_iNF6.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF5.c ++ * @author jeremy.wang (2016/11/29) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++#include "gpio.h" ++#include "padmux.h" ++#include "mdrv_gpio.h" ++#include "mdrv_padmux.h" ++#include "hal_card_platform_pri_config.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00)//1038h ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00)//103Ch ++#define A_GPI_INT_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E80)//103Dh ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700)//0Eh ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780)//0Fh ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00)//101Eh ++//#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900)//1132h ++#define A_SC_GP_CTRL_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89980)//1133h ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++ ++#define REG_CLK_IP_SD (0x43) ++#define REG_CLK_IP_SDIO (0x45) ++ ++ ++#define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ ++static volatile U16_T _gu16PowerPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++static volatile U16_T _gu16CdzPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_IPOnceSetting(IpOrder eIP) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++#if (FORCE_SWITCH_PAD) ++ // reg_all_pad_in => Close ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); ++#endif ++ ++ // Clock Source ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT05_T); // boot sel ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT03_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_InitPADPin(IpOrder eIP, PadOrder ePAD) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD) ++ { ++ // Driving for PAD_SD_CLK, PAD_SD_CMD, PAD_SD_D0 ~ PAD_SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 low , 1 high ++ } ++ else if (ePadSel == PAD_SD1) ++ { ++ // PAD_SD1_IO0 ~ PAD_SD1_IO5 -> Driving for D0,D1,D2,D3,CMD,CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x30), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ } ++ ++ // Pull Down ++ Hal_CARD_PullPADPin(eIP, ePAD, EV_PULLDOWN); ++} ++ ++BOOL_T Hal_CARD_GetPadInfoCdzPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++BOOL_T Hal_CARD_GetPadInfoPowerPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++void Hal_CARD_ConfigSdPad(IpOrder eIP, PadOrder ePAD) //Hal_CARD_SetPADToPortPath ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD_MODE); ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE); ++ } ++ } ++ } ++ ++#else // ++ ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ // SD mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); ++ ++ // Make sure reg_spi1_mode != 3 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C) & (BIT06_T | BIT05_T | BIT04_T)) == (BIT05_T | BIT04_T)) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C), BIT06_T | BIT05_T | BIT04_T); ++ } ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ U16_T temp; ++ ++ // SD mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); ++ ++ // Make sure reg_spi0_mode != 4 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C) & (BIT02_T | BIT01_T | BIT00_T)) == BIT02_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C), BIT02_T | BIT01_T | BIT00_T); ++ } ++ ++ // Make sure reg_uart0_mode != 4 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03) & (BIT06_T | BIT05_T | BIT04_T)) == BIT06_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), BIT06_T | BIT05_T | BIT04_T); ++ } ++ ++ // Make sure reg_fuart_mode != 4 && 6 ++ temp = CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03)) & (BIT02_T | BIT01_T | BIT00_T); ++ if(temp == (BIT02_T) || temp == (BIT02_T|BIT01_T) ) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), BIT02_T | BIT01_T | BIT00_T); ++ } ++ ++ // PWM is not cleared ++ // ... ++ ++ //Make sure reg_ttl_mode != 1 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F) & (BIT07_T | BIT06_T)) == BIT06_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F), BIT06_T | BIT07_T); ++ } ++ ++ //Make sure reg_dmic_mode != 2 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F) & (BIT09_T | BIT08_T)) == BIT09_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F), BIT09_T | BIT08_T); ++ } ++ ++ //Make sure reg_i2s_mode != 2 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F) & (BIT11_T | BIT10_T)) == BIT11_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F), BIT11_T | BIT10_T); ++ } ++ } ++ } ++ ++#endif ++} ++ ++void Hal_CARD_ConfigPowerPad(IpOrder eIP, U16_T nPadNum) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ ++ //make sure it's reg_fuart_mode != 1 ++ if ((CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03)) & (BIT02_T | BIT01_T | BIT00_T)) == BIT00_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), (BIT02_T | BIT01_T | BIT00_T)); ++ } ++ ++ break; ++ ++ case PAD_PM_GPIO9: ++ ++ // ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++ ++ // Default power off ++ Hal_CARD_PowerOff(eIP, 0); ++} ++ ++void Hal_CARD_PullPADPin(IpOrder eIP, PadOrder ePAD, PinPullEmType ePinPull) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ // Whatever if using padmux dts, we need to switch the pad mode. ++ ++ // IP_SD ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ // Pull Disable - D3, D2, D1, D0, CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); ++ ++ // PAD -> GPIO mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD_CLK, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_CMD, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D0, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D1, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D2, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D3, PINMUX_FOR_GPIO_MODE); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); // SDIO mode = 0 ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD_CLK); ++ MDrv_GPIO_Set_Low(PAD_SD_CMD); ++ MDrv_GPIO_Set_Low(PAD_SD_D0); ++ MDrv_GPIO_Set_Low(PAD_SD_D1); ++ MDrv_GPIO_Set_Low(PAD_SD_D2); ++ MDrv_GPIO_Set_Low(PAD_SD_D3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT04_T); // output:0 ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT04_T); // output:0 ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT04_T); // output:0 ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT04_T); // output:0 ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT04_T); // output:0 ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT04_T); // output:0 ++#endif ++ } ++ else if (ePinPull == EV_PULLUP) ++ { ++ // Pull Enable - D3, D2, D1, D0, CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD_CLK); ++ MDrv_GPIO_Pad_Odn(PAD_SD_CMD); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D0); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D1); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D2); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD_MODE); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); // SDIO mode = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T ); // SDIO mode = 1 ++#endif ++ } ++ } ++ } ++ ++ // IP_SDIO ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ // Pull Disable - D3, D2, D1, D0, CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ // PAD -> GPIO mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO5, PINMUX_FOR_GPIO_MODE); // CLK ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO4, PINMUX_FOR_GPIO_MODE); // CMD ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO0, PINMUX_FOR_GPIO_MODE); // D0 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO1, PINMUX_FOR_GPIO_MODE); // D1 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO2, PINMUX_FOR_GPIO_MODE); // D2 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO3, PINMUX_FOR_GPIO_MODE); // D3 ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); // SDIO mode = 0 ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD1_IO5); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO4); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO0); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO1); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO2); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT04_T); // output:0 ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT04_T); // output:0 ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT04_T); // output:0 ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x41), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x41), BIT04_T); // output:0 ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT04_T); // output:0 ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT04_T); // output:0 ++#endif ++ } ++ else if (ePinPull == EV_PULLUP) ++ { ++ // Pull Enable - D3, D2, D1, D0, CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO5); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO4); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO0); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO1); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO2); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x41), BIT05_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE); ++#else ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); // SDIO mode = 1 ++#endif ++ } ++ } ++ } ++} ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_SetClock(IpOrder eIP, U32_T u32ClkFromIPSet) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK2_F: //48000KHz ++ break; ++ case CLK2_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT02_T); //1 ++ break; ++ case CLK2_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T); //2 ++ break; ++ case CLK2_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK2_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T); //4 ++ break; ++ case CLK2_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK2_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK2_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++} ++ ++#ifdef CONFIG_PM_SLEEP ++//*********************************************************************************************************** ++// Get pm clock from Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_GetClock(U32_T u32SlotNo, U32_T *pu32PmIPClk, U32_T *pu32PmBlockClk) ++{ ++ ++} ++ ++//*********************************************************************************************************** ++// Set pm clock to Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_setClock(U32_T u32SlotNo, U32_T u32PmIPClk, U32_T u32PmBlockClk) ++{ ++ ++} ++#endif ++ ++U32_T Hal_CARD_FindClockSetting(IpOrder eIP, U32_T u32ReffClk) ++{ ++ U8_T u8LV = 0; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ return u32RealClk; ++} ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_PowerOn(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_Low(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:0 ++ break; ++ ++ case PAD_PM_GPIO9: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT00_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT01_T); // output:0 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++void Hal_CARD_PowerOff(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_High(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:1 ++ break; ++ ++ case PAD_PM_GPIO9: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT00_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT01_T); // output:1 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_ConfigCdzPad(IpOrder eIP, U16_T nPadNum) // Hal_CARD_InitGPIO ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++// PADMUX ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ // ++ break; ++ ++ case PAD_SD1_IO6: ++ // ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++// GPIO ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ // Whatever mdrv_padmux_active is ON or OFF, just set it to input mode. ++ MDrv_GPIO_Pad_Odn(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ break; ++ ++ case PAD_SD1_IO6: ++ ++ // ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT05_T); // input mode ++ ++#if 0 // reg_gpi_glhrm ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_GPI_INT_BANK, 0x42), BIT10_T); // For PAD_SD1_IO6 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_GPI_INT_BANK, 0x45), 8); ++#endif ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // This is a special case, SD_CDZ mode ON/OFF status will use different GIC path. ++ // We must switch ON - SD_CDZ mode ++ if (nPadNo == PAD_PM_SD_CDZ) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ } ++ ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++} ++ ++BOOL_T Hal_CARD_GetCdzState(IpOrder eIP) // Hal_CARD_GetGPIOState ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ U8_T nLv = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ } ++ ++ nPadNo = _gu16CdzPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use CDZ pin. ++ goto fail; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ nLv = MDrv_GPIO_Pad_Read(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ break; ++ ++ case PAD_SD1_IO6: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46)) & BIT00_T; ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ break; ++ } ++ ++#endif ++ ++ if (!nLv) // Low Active ++ { ++ return TRUE; ++ } ++ ++fail: ++ ++ return FALSE; ++} ++ ++ ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr, U8_T* pu8MIUSel) ++{ ++ return u32Addr-0x20000000; ++} +diff --git a/drivers/sstar/sdmmc/src/infinity6b0/hal_card_platform.c b/drivers/sstar/sdmmc/src/infinity6b0/hal_card_platform.c +new file mode 100755 +index 000000000000..e37db4373181 +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/infinity6b0/hal_card_platform.c +@@ -0,0 +1,903 @@ ++/* ++* hal_card_platform_iNF6.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: joe.su ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF5.c ++ * @author jeremy.wang (2016/11/29) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++#include "gpio.h" ++#include "padmux.h" ++#include "mdrv_gpio.h" ++#include "mdrv_padmux.h" ++#include "hal_card_platform_pri_config.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00)//1038h ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00)//103Ch ++#define A_GPI_INT_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E80)//103Dh ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700)//0Eh ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780)//0Fh ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00)//101Eh ++//#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900)//1132h ++#define A_SC_GP_CTRL_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89980)//1133h ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++ ++#define REG_CLK_IP_SD (0x43) ++#define REG_CLK_IP_SDIO (0x45) ++ ++ ++#define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ ++static volatile U16_T _gu16PowerPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++static volatile U16_T _gu16CdzPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_IPOnceSetting(IpOrder eIP) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++#if (FORCE_SWITCH_PAD) ++ // reg_all_pad_in => Close ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); ++#endif ++ ++ // Clock Source ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT05_T); // boot sel ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT03_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_InitPADPin(IpOrder eIP, PadOrder ePAD) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD) ++ { ++ // Driving for PAD_SD_CLK, PAD_SD_CMD, PAD_SD_D0 ~ PAD_SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 low , 1 high ++ } ++ else if (ePadSel == PAD_SD1) ++ { ++ // PAD_SD1_IO0 ~ PAD_SD1_IO5 -> Driving for D0,D1,D2,D3,CMD,CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x30), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ } ++ ++ // Pull Down ++ Hal_CARD_PullPADPin(eIP, ePAD, EV_PULLDOWN); ++} ++ ++BOOL_T Hal_CARD_GetPadInfoCdzPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++BOOL_T Hal_CARD_GetPadInfoPowerPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++void Hal_CARD_ConfigSdPad(IpOrder eIP, PadOrder ePAD) //Hal_CARD_SetPADToPortPath ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD_MODE); ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE); ++ } ++ } ++ } ++ ++#else // ++ ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ // SD mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); ++ ++ // Make sure reg_spi1_mode != 3 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C) & (BIT06_T | BIT05_T | BIT04_T)) == (BIT05_T | BIT04_T)) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C), BIT06_T | BIT05_T | BIT04_T); ++ } ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ U16_T temp; ++ ++ // SD mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); ++ ++ // Make sure reg_spi0_mode != 4 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C) & (BIT02_T | BIT01_T | BIT00_T)) == BIT02_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C), BIT02_T | BIT01_T | BIT00_T); ++ } ++ ++ // Make sure reg_uart0_mode != 4 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03) & (BIT06_T | BIT05_T | BIT04_T)) == BIT06_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), BIT06_T | BIT05_T | BIT04_T); ++ } ++ ++ // Make sure reg_fuart_mode != 4 && 6 ++ temp = CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03)) & (BIT02_T | BIT01_T | BIT00_T); ++ if(temp == (BIT02_T) || temp == (BIT02_T|BIT01_T) ) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), BIT02_T | BIT01_T | BIT00_T); ++ } ++ ++ // PWM is not cleared ++ // ... ++ ++ //Make sure reg_ttl_mode != 1 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F) & (BIT07_T | BIT06_T)) == BIT06_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F), BIT06_T | BIT07_T); ++ } ++ ++ //Make sure reg_dmic_mode != 2 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F) & (BIT09_T | BIT08_T)) == BIT09_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F), BIT09_T | BIT08_T); ++ } ++ ++ //Make sure reg_i2s_mode != 2 ++ if((GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F) & (BIT11_T | BIT10_T)) == BIT11_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F), BIT11_T | BIT10_T); ++ } ++ } ++ } ++ ++#endif ++} ++ ++void Hal_CARD_ConfigPowerPad(IpOrder eIP, U16_T nPadNum) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ ++ //make sure it's reg_fuart_mode != 1 ++ if ((CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03)) & (BIT02_T | BIT01_T | BIT00_T)) == BIT00_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), (BIT02_T | BIT01_T | BIT00_T)); ++ } ++ ++ break; ++ ++ case PAD_PM_GPIO9: ++ ++ // ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++ ++ // Default power off ++ Hal_CARD_PowerOff(eIP, 0); ++} ++ ++void Hal_CARD_PullPADPin(IpOrder eIP, PadOrder ePAD, PinPullEmType ePinPull) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ // Whatever if using padmux dts, we need to switch the pad mode. ++ ++ // IP_SD ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ // Pull Disable - D3, D2, D1, D0, CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); ++ ++ // PAD -> GPIO mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD_CLK, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_CMD, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D0, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D1, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D2, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD_D3, PINMUX_FOR_GPIO_MODE); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); // SDIO mode = 0 ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD_CLK); ++ MDrv_GPIO_Set_Low(PAD_SD_CMD); ++ MDrv_GPIO_Set_Low(PAD_SD_D0); ++ MDrv_GPIO_Set_Low(PAD_SD_D1); ++ MDrv_GPIO_Set_Low(PAD_SD_D2); ++ MDrv_GPIO_Set_Low(PAD_SD_D3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT04_T); // output:0 ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT04_T); // output:0 ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT04_T); // output:0 ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT04_T); // output:0 ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT04_T); // output:0 ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT04_T); // output:0 ++#endif ++ } ++ else if (ePinPull == EV_PULLUP) ++ { ++ // Pull Enable - D3, D2, D1, D0, CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD_CLK); ++ MDrv_GPIO_Pad_Odn(PAD_SD_CMD); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D0); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D1); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D2); ++ MDrv_GPIO_Pad_Odn(PAD_SD_D3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD_MODE); ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T | BIT03_T); // SDIO mode = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T ); // SDIO mode = 1 ++#endif ++ } ++ } ++ } ++ ++ // IP_SDIO ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ // Pull Disable - D3, D2, D1, D0, CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ // PAD -> GPIO mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO5, PINMUX_FOR_GPIO_MODE); // CLK ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO4, PINMUX_FOR_GPIO_MODE); // CMD ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO0, PINMUX_FOR_GPIO_MODE); // D0 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO1, PINMUX_FOR_GPIO_MODE); // D1 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO2, PINMUX_FOR_GPIO_MODE); // D2 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_IO3, PINMUX_FOR_GPIO_MODE); // D3 ++#else ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); // SDIO mode = 0 ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD1_IO5); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO4); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO0); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO1); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO2); ++ MDrv_GPIO_Set_Low(PAD_SD1_IO3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT04_T); // output:0 ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT04_T); // output:0 ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT04_T); // output:0 ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x41), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x41), BIT04_T); // output:0 ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT04_T); // output:0 ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT04_T); // output:0 ++#endif ++ } ++ else if (ePinPull == EV_PULLUP) ++ { ++ // Pull Enable - D3, D2, D1, D0, CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO5); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO4); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO0); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO1); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO2); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_IO3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x41), BIT05_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SDIO_MODE); ++#else ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); // SDIO mode = 1 ++#endif ++ } ++ } ++ } ++} ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_SetClock(IpOrder eIP, U32_T u32ClkFromIPSet) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK2_F: //48000KHz ++ break; ++ case CLK2_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT02_T); //1 ++ break; ++ case CLK2_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T); //2 ++ break; ++ case CLK2_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK2_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T); //4 ++ break; ++ case CLK2_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK2_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK2_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++} ++ ++#ifdef CONFIG_PM_SLEEP ++//*********************************************************************************************************** ++// Get pm clock from Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_GetClock(U32_T u32SlotNo, U32_T *pu32PmIPClk, U32_T *pu32PmBlockClk) ++{ ++ ++} ++ ++//*********************************************************************************************************** ++// Set pm clock to Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_setClock(U32_T u32SlotNo, U32_T u32PmIPClk, U32_T u32PmBlockClk) ++{ ++ ++} ++#endif ++ ++U32_T Hal_CARD_FindClockSetting(IpOrder eIP, U32_T u32ReffClk) ++{ ++ U8_T u8LV = 0; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ return u32RealClk; ++} ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_PowerOn(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_Low(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:0 ++ break; ++ ++ case PAD_PM_GPIO9: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT00_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT01_T); // output:0 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++void Hal_CARD_PowerOff(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_High(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:1 ++ break; ++ ++ case PAD_PM_GPIO9: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT00_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x09), BIT01_T); // output:1 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_ConfigCdzPad(IpOrder eIP, U16_T nPadNum) // Hal_CARD_InitGPIO ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++// PADMUX ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ // ++ break; ++ ++ case PAD_SD1_IO6: ++ // ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++// GPIO ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ // Whatever mdrv_padmux_active is ON or OFF, just set it to input mode. ++ MDrv_GPIO_Pad_Odn(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ break; ++ ++ case PAD_SD1_IO6: ++ ++ // ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT05_T); // input mode ++ ++#if 0 // reg_gpi_glhrm ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_GPI_INT_BANK, 0x42), BIT10_T); // For PAD_SD1_IO6 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_GPI_INT_BANK, 0x45), 8); ++#endif ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // This is a special case, SD_CDZ mode ON/OFF status will use different GIC path. ++ // We must switch ON - SD_CDZ mode ++ if (nPadNo == PAD_PM_SD_CDZ) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ } ++ ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++} ++ ++BOOL_T Hal_CARD_GetCdzState(IpOrder eIP) // Hal_CARD_GetGPIOState ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ U8_T nLv = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ } ++ ++ nPadNo = _gu16CdzPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use CDZ pin. ++ goto fail; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ nLv = MDrv_GPIO_Pad_Read(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_PM_SD_CDZ: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ break; ++ ++ case PAD_SD1_IO6: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46)) & BIT00_T; ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ break; ++ } ++ ++#endif ++ ++ if (!nLv) // Low Active ++ { ++ return TRUE; ++ } ++ ++fail: ++ ++ return FALSE; ++} ++ ++ ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr, U8_T* pu8MIUSel) ++{ ++ return u32Addr-0x20000000; ++} +diff --git a/drivers/sstar/sdmmc/src/infinity6e/hal_card_platform.c b/drivers/sstar/sdmmc/src/infinity6e/hal_card_platform.c +new file mode 100755 +index 000000000000..5de93125218a +--- /dev/null ++++ b/drivers/sstar/sdmmc/src/infinity6e/hal_card_platform.c +@@ -0,0 +1,1199 @@ ++/* ++* hal_card_platform_iNF6.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: tunglin.hsieh ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF5.c ++ * @author jeremy.wang (2016/11/29) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++#include "gpio.h" ++#include "padmux.h" ++#include "mdrv_gpio.h" ++#include "mdrv_padmux.h" ++#include "hal_card_platform_pri_config.h" ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++#include "mdrv_puse.h" ++#endif ++ ++//*********************************************************************************************************** ++// Config Setting (Internal) ++//*********************************************************************************************************** ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00)//1038h ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00)//103Ch ++//#define A_GPI_INT_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E80)//103Dh ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700)//0Eh ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780)//0Fh ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00)//101Eh ++//#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900)//1132h ++#define A_SC_GP_CTRL_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89980)//1133h ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++ ++#define REG_CLK_IP_SD (0x43) ++#define REG_CLK_IP_SDIO (0x45) ++#define REG_CKG_CLK (0x25) ++ ++ ++#define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ ++static volatile U16_T _gu16PowerPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++static volatile U16_T _gu16CdzPadNumForEachIp[IP_TOTAL] = {PAD_UNKNOWN}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_IPOnceSetting(IpOrder eIP) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++#if (FORCE_SWITCH_PAD) ++ // reg_all_pad_in => Close ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); ++#endif ++ ++ // Clock Source ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T); //BK:x1133(sc_gp_ctrl)[B7] [0:1]/[boot_clk(12M):sd_clk] ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT05_T); //BK:x1038(reg_ckg_sd)[B5] [0:1]/[boot_clk(12M):sd_clk] ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT03_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT05_T); ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_InitPADPin(IpOrder eIP, PadOrder ePAD) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD) ++ { ++ //reg_sd0_pe:D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT04_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT04_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT04_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT04_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); //D2 ++ ++ //reg_sd0_drv: CLK, D3, D2, D1, D0, CMD => drv: 1 for vCore 0.9V->0.85V ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT07_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT07_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x14), BIT07_T); //CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT07_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT07_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT07_T); //D2 ++ } ++ else if (ePadSel == PAD_SD1) ++ { ++ //reg_sd1_pe:D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT04_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT04_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT04_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT04_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT04_T); //D2 ++ ++ //reg_sd1_drv: CLK, D3, D2, D1, D0, CMD => drv: 1 for vCore 0.9V->0.85V ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT07_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT07_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT07_T); //CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT07_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT07_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT07_T); //D2 ++ } ++ else if (ePadSel == PAD_SD1_MD2) ++ { ++ //reg_sd1_pe:D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x18), BIT04_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x19), BIT04_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1A), BIT04_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1C), BIT04_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1d), BIT04_T); //D2 ++ ++ //reg_sd1_drv: CLK, D3, D2, D1, D0, CMD => drv: 1 for vCore 0.9V->0.85V ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x18), BIT07_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x19), BIT07_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1A), BIT07_T); //CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1B), BIT07_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1C), BIT07_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1D), BIT07_T); //D2 ++ } ++ ++ // Pull Down ++ Hal_CARD_PullPADPin(eIP, ePAD, EV_PULLDOWN); ++} ++ ++BOOL_T Hal_CARD_GetPadInfoCdzPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ int puse; ++ ++ if (eIP == IP_ORDER_0) ++ { ++ puse = MDRV_PUSE_SDIO0_CDZ; ++ } ++ else if (eIP == IP_ORDER_1) ++ { ++ puse = MDRV_PUSE_SDIO1_CDZ; ++ } ++ else ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ ++ *nPadNum = PAD_UNKNOWN; ++ return FALSE; ++ } ++ ++ *nPadNum = mdrv_padmux_getpad(puse); ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++BOOL_T Hal_CARD_GetPadInfoPowerPad(IpOrder eIP, U32_T *nPadNum) ++{ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ int puse; ++ ++ if (eIP == IP_ORDER_0) ++ { ++ puse = MDRV_PUSE_SDIO0_PWR; ++ } ++ else if (eIP == IP_ORDER_1) ++ { ++ puse = MDRV_PUSE_SDIO1_PWR; ++ } ++ else ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ ++ *nPadNum = PAD_UNKNOWN; ++ return FALSE; ++ } ++ ++ *nPadNum = mdrv_padmux_getpad(puse); ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++void Hal_CARD_ConfigSdPad(IpOrder eIP, PadOrder ePAD) //Hal_CARD_SetPADToPortPath ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD0_MODE); ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD0_CDZ_MODE); ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_MODE_1); ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_CDZ_MODE_1); ++ } ++ else if (ePadSel == PAD_SD1_MD2) ++ { ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_MODE_2); ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_CDZ_MODE_2); ++ } ++ } ++ } ++ ++#else // ++ ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ // SD mode ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT13_T | BIT12_T | BIT09_T | BIT08_T); ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68), BIT08_T | BIT09_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT08_T | BIT09_T); ++ ++ //Make sure reg_spi0_mode != 3 ++ if((GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68) & (BIT02_T | BIT01_T | BIT00_T)) == (BIT01_T | BIT00_T)) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68), BIT02_T | BIT01_T | BIT00_T); ++ } ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ //SD mode ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT12_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68), BIT08_T); ++ ++ // Make sure reg_uart1_mode != 4 ++ if((GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6D) & (BIT06_T | BIT05_T | BIT04_T)) == BIT06_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6D), BIT06_T | BIT05_T | BIT04_T); ++ } ++ ++ // Make sure reg_fuart_mode != 2 && 4 ++ if((GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6E) & (BIT06_T | BIT05_T | BIT04_T)) == BIT05_T || ++ (GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6E) & (BIT06_T | BIT05_T | BIT04_T)) == BIT06_T ) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6E), BIT06_T | BIT05_T | BIT04_T); ++ } ++ ++ // Make sure reg_spi0_mode != 4 ++ if((GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68) & (BIT02_T | BIT01_T | BIT00_T)) == BIT02_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68), BIT02_T | BIT01_T | BIT00_T); ++ } ++ ++ //Make sure reg_i2c2_mode != 2 ++ if((GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6F) & (BIT10_T | BIT09_T| BIT08_T)) == BIT09_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x6F), BIT10_T | BIT09_T| BIT08_T); ++ } ++ } ++ } ++ ++#endif ++} ++ ++void Hal_CARD_ConfigPowerPad(IpOrder eIP, U16_T nPadNum) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ MDrv_GPIO_PadVal_Set(nPadNo, PINMUX_FOR_GPIO_MODE); ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ ++ //make sure it's reg_fuart_mode != 1 ++ if ((CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03)) & (BIT02_T | BIT01_T | BIT00_T)) == BIT00_T) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03), (BIT02_T | BIT01_T | BIT00_T)); ++ } ++ ++ break; ++ ++ case PAD_SD0_GPIO0: ++ break; ++ ++ case PAD_SD1_GPIO0: ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // Save Power PadNum ++ _gu16PowerPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++ ++ // Default power off ++ Hal_CARD_PowerOff(eIP, 0); ++} ++ ++void Hal_CARD_PullPADPin(IpOrder eIP, PadOrder ePAD, PinPullEmType ePinPull) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ // Whatever if using padmux dts, we need to switch the pad mode. ++ ++ // IP_SD ++ if (eIpSel == IP_SD) ++ { ++ if (ePadSel == PAD_SD) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ //reg_sd0_pe: D3, D2, D1, D0, CMD=> pull dis ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT04_T); //D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT04_T); //D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT04_T); //CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT04_T); //D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); //D2 ++ ++ // PAD -> GPIO mode ++#if 0//(PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD0_CLK, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD0_CMD, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD0_D0, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD0_D1, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD0_D2, PINMUX_FOR_GPIO_MODE); ++ MDrv_GPIO_PadVal_Set(PAD_SD0_D3, PINMUX_FOR_GPIO_MODE); ++#else ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT08_T); ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD0_CLK); ++ MDrv_GPIO_Set_Low(PAD_SD0_CMD); ++ MDrv_GPIO_Set_Low(PAD_SD0_D0); ++ MDrv_GPIO_Set_Low(PAD_SD0_D1); ++ MDrv_GPIO_Set_Low(PAD_SD0_D2); ++ MDrv_GPIO_Set_Low(PAD_SD0_D3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x14), BIT02_T); //reg_sd0_gpio_oen_4 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x14), BIT01_T); //reg_sd0_gpio_out_4 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT02_T); //reg_sd0_gpio_oen_5 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT01_T); //reg_sd0_gpio_out_5 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT02_T); //reg_sd0_gpio_oen_3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT01_T); //reg_sd0_gpio_out_3 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT02_T); //reg_sd0_gpio_oen_2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT01_T); //reg_sd0_gpio_out_2 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT02_T); //reg_sd0_gpio_oen_7 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT01_T); //reg_sd0_gpio_out_7 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT02_T); //reg_sd0_gpio_oen_6 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT01_T); //reg_sd0_gpio_out_6 ++#endif ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ //reg_sd0_pe:D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT04_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT04_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT04_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT04_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); //D2 ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD0_CLK); ++ MDrv_GPIO_Pad_Odn(PAD_SD0_CMD); ++ MDrv_GPIO_Pad_Odn(PAD_SD0_D0); ++ MDrv_GPIO_Pad_Odn(PAD_SD0_D1); ++ MDrv_GPIO_Pad_Odn(PAD_SD0_D2); ++ MDrv_GPIO_Pad_Odn(PAD_SD0_D3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x14), BIT02_T); // reg_sd0_gpio_oen_4 ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x15), BIT02_T); // reg_sd0_gpio_oen_5 ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x13), BIT02_T); // reg_sd0_gpio_oen_3 ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x12), BIT02_T); // reg_sd0_gpio_oen_2 ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT02_T); // reg_sd0_gpio_oen_7 ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x16), BIT02_T); // reg_sd0_gpio_oen_6 ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD0_MODE); ++#else ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT08_T); ++#endif ++ } ++ } ++ } ++ ++ // IP_SDIO ++ if (eIpSel == IP_SDIO) ++ { ++ if (ePadSel == PAD_SD1) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ //D3, D2, D1, D0, CMD=> pull dis ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT04_T); //D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT04_T); //D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT04_T); //CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT04_T); //D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT04_T); //D2 ++ ++ // PAD -> GPIO mode ++#if 0//(PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_SD1_CLK, PINMUX_FOR_GPIO_MODE); // CLK ++ MDrv_GPIO_PadVal_Set(PAD_SD1_CMD, PINMUX_FOR_GPIO_MODE); // CMD ++ MDrv_GPIO_PadVal_Set(PAD_SD1_D0, PINMUX_FOR_GPIO_MODE); // D0 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_D1, PINMUX_FOR_GPIO_MODE); // D1 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_D2, PINMUX_FOR_GPIO_MODE); // D2 ++ MDrv_GPIO_PadVal_Set(PAD_SD1_D3, PINMUX_FOR_GPIO_MODE); // D3 ++#else ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT12_T | BIT13_T); ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_SD1_CLK); ++ MDrv_GPIO_Set_Low(PAD_SD1_CMD); ++ MDrv_GPIO_Set_Low(PAD_SD1_D0); ++ MDrv_GPIO_Set_Low(PAD_SD1_D1); ++ MDrv_GPIO_Set_Low(PAD_SD1_D2); ++ MDrv_GPIO_Set_Low(PAD_SD1_D3); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT01_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT01_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT01_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT01_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT01_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT01_T); // output:0 ++#endif ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT04_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT04_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT04_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT04_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT04_T); //D2 ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_SD1_CLK); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_CMD); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_D0); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_D1); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_D2); ++ MDrv_GPIO_Pad_Odn(PAD_SD1_D3); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT02_T); // input mode ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT02_T); // input mode ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT02_T); // input mode ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT02_T); // input mode ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT02_T); // input mode ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT02_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_MODE_1); ++#else ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT12_T); ++#endif ++ } ++ } ++ else if (ePadSel == PAD_SD1_MD2) ++ { ++ if (ePinPull == EV_PULLDOWN) ++ { ++ //D3, D2, D1, D0, CMD=> pull dis ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x18), BIT04_T); //D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x19), BIT04_T); //D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1A), BIT04_T); //CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1C), BIT04_T); //D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1D), BIT04_T); //D2 ++ ++ // PAD -> GPIO mode ++#if 0//(PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadVal_Set(PAD_I2S0_WCK, PINMUX_FOR_GPIO_MODE); // CLK ++ MDrv_GPIO_PadVal_Set(PAD_I2S0_DI, PINMUX_FOR_GPIO_MODE); // CMD ++ MDrv_GPIO_PadVal_Set(PAD_I2S0_BCK, PINMUX_FOR_GPIO_MODE); // D0 ++ MDrv_GPIO_PadVal_Set(PAD_I2S0_MCLK, PINMUX_FOR_GPIO_MODE); // D1 ++ MDrv_GPIO_PadVal_Set(PAD_I2C0_SDA, PINMUX_FOR_GPIO_MODE); // D2 ++ MDrv_GPIO_PadVal_Set(PAD_I2C0_SCL, PINMUX_FOR_GPIO_MODE); // D3 ++#else ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT12_T | BIT13_T); ++#endif ++ ++ // Output Low ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Set_Low(PAD_I2S0_WCK); ++ MDrv_GPIO_Set_Low(PAD_I2S0_DI); ++ MDrv_GPIO_Set_Low(PAD_I2S0_BCK); ++ MDrv_GPIO_Set_Low(PAD_I2S0_MCLK); ++ MDrv_GPIO_Set_Low(PAD_I2C0_SDA); ++ MDrv_GPIO_Set_Low(PAD_I2C0_SCL); ++#else ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT01_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT01_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT01_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT01_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT01_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT02_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT01_T); // output:0 ++#endif ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x18), BIT04_T); //D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x19), BIT04_T); //D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1A), BIT04_T); //CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1C), BIT04_T); //D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x1D), BIT04_T); //D2 ++ ++ // Input ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ MDrv_GPIO_Pad_Odn(PAD_I2S0_WCK); ++ MDrv_GPIO_Pad_Odn(PAD_I2S0_DI); ++ MDrv_GPIO_Pad_Odn(PAD_I2S0_BCK); ++ MDrv_GPIO_Pad_Odn(PAD_I2S0_MCLK); ++ MDrv_GPIO_Pad_Odn(PAD_I2C0_SDA); ++ MDrv_GPIO_Pad_Odn(PAD_I2C0_SCL); ++#else ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x29), BIT02_T); // input mode ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2A), BIT02_T); // input mode ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x28), BIT02_T); // input mode ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x27), BIT02_T); // input mode ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2C), BIT02_T); // input mode ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2B), BIT02_T); // input mode ++#endif ++ // SD Mode ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_MODE_2); ++#else ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT13_T); ++#endif ++ } ++ } ++ } ++} ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_SetClock(IpOrder eIP, U32_T u32ClkFromIPSet) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5]Boot_Sel [4:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT05_T); //boot sel ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T); //[B3/B7]:[SDIO/SD] select BOOT clock source (glitch free) - 0: select BOOT clock 12MHz (xtali), 1: select FCIE/SPI clock source ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SD), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5]Boot_Sel [4:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT05_T); //boot sel ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T | BIT03_T); //[B3/B7]:[SDIO/SD] select BOOT clock source (glitch free) - 0: select BOOT clock 12MHz (xtali), 1: select FCIE/SPI clock source ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK2_F: //48000KHz ++ break; ++ case CLK2_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT02_T); //1 ++ break; ++ case CLK2_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T); //2 ++ break; ++ case CLK2_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK2_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T); //4 ++ break; ++ case CLK2_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK2_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK2_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,REG_CLK_IP_SDIO), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ } ++ } ++} ++ ++#ifdef CONFIG_PM_SLEEP ++//*********************************************************************************************************** ++// Get pm clock from Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_GetClock(U32_T u32SlotNo, U32_T *pu32PmIPClk, U32_T *pu32PmBlockClk) ++{ ++ IpSelect eIpSel = (IpSelect)u32SlotNo; ++ ++ *pu32PmBlockClk = CARD_REG(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK, REG_CKG_CLK)); ++ ++ if (eIpSel == IP_SD) ++ { ++ *pu32PmIPClk = CARD_REG(GET_CARD_REG_ADDR(A_CLKGEN_BANK, REG_CLK_IP_SD)); ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ *pu32PmIPClk = CARD_REG(GET_CARD_REG_ADDR(A_CLKGEN_BANK, REG_CLK_IP_SDIO)); ++ } ++} ++ ++//*********************************************************************************************************** ++// Set pm clock to Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_devpm_setClock(U32_T u32SlotNo, U32_T u32PmIPClk, U32_T u32PmBlockClk) ++{ ++ IpSelect eIpSel = (IpSelect)u32SlotNo; ++ ++ CARD_REG(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK, REG_CKG_CLK)) = u32PmBlockClk; ++ ++ if (eIpSel == IP_SD) ++ { ++ CARD_REG(GET_CARD_REG_ADDR(A_CLKGEN_BANK, REG_CLK_IP_SD)) = u32PmIPClk; ++ } ++ else if (eIpSel == IP_SDIO) ++ { ++ CARD_REG(GET_CARD_REG_ADDR(A_CLKGEN_BANK, REG_CLK_IP_SDIO)) = u32PmIPClk; ++ } ++} ++#endif ++ ++U32_T Hal_CARD_FindClockSetting(IpOrder eIP, U32_T u32ReffClk) ++{ ++ U8_T u8LV = 0; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ return u32RealClk; ++} ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_PowerOn(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_Low(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ //Before I6E: sd card power pin is PAD_FUART_RTS ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x25), BIT02_T); // reg_fuart_gpio_oen_3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x25), BIT01_T); // reg_fuart_gpio_out_3 ++ break; ++ ++ case PAD_SD0_GPIO0: ++ //I6E_ECO: sd card power enable. (Change fuart_gpio to sd0_gpio0) ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x10), BIT02_T); // reg_sd0_gpio_oen_0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x10), BIT01_T); // reg_sd0_gpio_out_0 ++ break; ++ ++ case PAD_SD1_GPIO0: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2D), BIT02_T); // reg_sd1_gpio_oen_7 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2D), BIT01_T); // reg_sd1_gpio_out_7 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++void Hal_CARD_DumpPadMux(PadOrder ePAD) ++{ ++ PadSelect ePadSel = (PadSelect)ePAD; ++ ++ if (ePadSel == PAD_SD1) ++ { ++ printk("reg_allpad_in; reg[101EA1]#7=0b\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50))); ++ printk("reg_test_in_mode; reg[101E24]#1 ~ #0=0b\n"); ++ printk("reg_test_out_mode; reg[101E24]#5 ~ #4=0b\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x12))); ++ printk("reg_spi0_mode; reg[101E18]#2 ~ #0=0b\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0C))); ++ printk("reg_fuart_mode; reg[101E06]#2 ~ #0=0b !=4,!=6\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x03))); ++ printk("reg_sdio_mode; reg[101E11]#0=0b ==0x100\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08))); ++ printk("reg_pwm0_mode; reg[101E0E]#2 ~ #0=0b\n"); ++ printk("reg_pwm2_mode; reg[101E0F]#0 ~ #-2=0b\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x07))); ++ printk("reg_i2s_mode; reg[101E1F]#3 ~ #2=0b\n"); ++ printk("reg_ttl_mode; reg[101E1E]#7 ~ #6=0b\n"); ++ printk("%8X\n", CARD_REG(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x0F))); ++ } ++} ++ ++void Hal_CARD_PowerOff(IpOrder eIP, U16_T u16DelayMs) ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ nPadNo = _gu16PowerPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use power pin. ++ return; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ ++ // Whatever mdrv_padmux_active is ON or OFF, just do GPIO_set. ++ MDrv_GPIO_Set_High(nPadNo); ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_FUART_RTS: ++ //Before I6E: sd card power pin is PAD_FUART_RTS ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x25), BIT02_T); // reg_fuart_gpio_oen_3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x25), BIT01_T); // reg_fuart_gpio_out_3 ++ break; ++ ++ case PAD_SD0_GPIO0: ++ //I6E_ECO: sd card power enable. (Change fuart_gpio to sd0_gpio0) ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x10), BIT02_T); // reg_sd0_gpio_oen_0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x10), BIT01_T); // reg_sd0_gpio_out_0 ++ break; ++ ++ case PAD_SD1_GPIO0: ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2D), BIT02_T); // reg_sd1_gpio_oen_7 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x2D), BIT01_T); // reg_sd1_gpio_out_7 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ ++#endif ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++void Hal_CARD_ConfigCdzPad(IpOrder eIP, U16_T nPadNum) // Hal_CARD_InitGPIO ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = nPadNum; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = PAD_UNKNOWN; ++ return; ++ } ++ ++// PADMUX ++#if (PADMUX_SET == PADMUX_SET_BY_FUNC) ++ ++ if (0 == mdrv_padmux_active()) ++ { ++ switch (nPadNo) ++ { ++ case PAD_SD0_CDZ: ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD0_CDZ_MODE); ++ break; ++ ++ case PAD_SD1_CDZ: ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_CDZ_MODE_1); ++ break; ++ ++ case PAD_I2C0_SDA: ++ MDrv_GPIO_PadGroupMode_Set(PINMUX_FOR_SD1_CDZ_MODE_2); ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ } ++ ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_SD0_CDZ: ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x67), BIT09_T); ++ break; ++ ++ case PAD_SD1_CDZ: ++ //OFF:x67 [B8]reg_sd0_mode [B9]reg_sd0_cdz_mode [B13:B12]reg_sd1_mode ++ //OFF:x68 [B9:B8]reg_sd1_cdz_mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68), BIT08_T | BIT09_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x68), BIT08_T); ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++// GPIO ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ // Whatever mdrv_padmux_active is ON or OFF, just set it to input mode. ++ MDrv_GPIO_Pad_Odn(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_SD0_CDZ: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x11), BIT02_T); // PAD_SD0_CDZ:reg_sd0_gpio_oen_1 ++ break; ++ ++ case PAD_SD1_CDZ: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x26), BIT02_T); // PAD_SD1_CDZ:reg_sd1_gpio_oen_0 ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ return; ++ break; ++ } ++ ++#endif ++ ++ // Save CDZ PadNum ++ _gu16CdzPadNumForEachIp[(U16_T)eIpSel] = nPadNo; ++} ++ ++BOOL_T Hal_CARD_GetCdzState(IpOrder eIP) // Hal_CARD_GetGPIOState ++{ ++ IpSelect eIpSel = (IpSelect)eIP; ++ U16_T nPadNo = 0; ++ U8_T nLv = 0; ++ ++ if (eIpSel >= IP_TOTAL) ++ { ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ } ++ ++ nPadNo = _gu16CdzPadNumForEachIp[(U16_T)eIpSel]; ++ ++ if (nPadNo == PAD_UNKNOWN) ++ { ++ // Maybe we don't use CDZ pin. ++ goto fail; ++ } ++ ++#if (GPIO_SET == GPIO_SET_BY_FUNC) ++ nLv = MDrv_GPIO_Pad_Read(nPadNo); ++#else ++ ++ switch (nPadNo) ++ { ++ case PAD_SD0_CDZ: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x11)) & BIT00_T; ++ break; ++ ++ case PAD_SD1_CDZ: ++ nLv = CARD_REG(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x26)) & BIT00_T; ++ break; ++ ++ default: ++ pr_sd_err("sdmmc error ! [%s][%d]\n", __FUNCTION__, __LINE__); ++ goto fail; ++ break; ++ } ++ ++#endif ++ ++ if (!nLv) // Low Active ++ { ++ return TRUE; ++ } ++ ++fail: ++ ++ return FALSE; ++} ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr, U8_T* pu8MIUSel) ++{ ++ return u32Addr-0x20000000; ++} +diff --git a/drivers/sstar/serial/Kconfig b/drivers/sstar/serial/Kconfig +new file mode 100755 +index 000000000000..f4659822220c +--- /dev/null ++++ b/drivers/sstar/serial/Kconfig +@@ -0,0 +1,5 @@ ++config MS_SERIAL ++ bool "Serial / UART driver" ++ select SERIAL_CORE ++ select SERIAL_CORE_CONSOLE ++ default y +\ No newline at end of file +diff --git a/drivers/sstar/serial/Makefile b/drivers/sstar/serial/Makefile +new file mode 100755 +index 000000000000..59eadaa5b09a +--- /dev/null ++++ b/drivers/sstar/serial/Makefile +@@ -0,0 +1,9 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/serial/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_MS_SERIAL) += ms_uart.o ++obj-$(CONFIG_MS_SERIAL) += $(CONFIG_SSTAR_CHIP_NAME)/uart_pads.o +diff --git a/drivers/sstar/serial/infinity2/ms_uart.h b/drivers/sstar/serial/infinity2/ms_uart.h +new file mode 100755 +index 000000000000..b249233dea94 +--- /dev/null ++++ b/drivers/sstar/serial/infinity2/ms_uart.h +@@ -0,0 +1,52 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define CONFIG_MS_SUPPORT_UART2 ++#define CONFIG_MS_SUPPORT_EXT_PADMUX // use external padmux driver ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++#define MUX_UART2 4 ++#define UART_NA 0 ++#define UART_PIU_UART1 1 ++#define UART_VD_MHEG5 2 ++#define UART_PIU_UART2 3 ++#define UART_PIU_UART0 4 ++#define UART_PIU_FUART 7 ++#define DIG_MUX_SEL0 0 ++#define DIG_MUX_SEL1 1 ++#define DIG_MUX_SEL2 2 ++#define DIG_MUX_SEL3 3 ++#define DIG_MUX_SEL4 4 ++ ++#define REG_FUART_MODE 0x1F204C14 /*0x1026, h05*/ ++#define REG_UART_MODE 0x1F204C04 /*0x1026, h01*/ ++#define REG_FUART_SEL 0x1F203D50 /*0x101E, h54*/ ++#define REG_UART_SEL 0x1F203D4C /*0x101E, h53*/ ++#define REG_FORCE_RX_DISABLE 0x1F203D5C /*0x101E, h57*/ ++#define REG_UART2_CLK 0x1F201650 /*0x100B, h14*/ ++#define REG_FUART_CLK 0x1F20165c /*0x100B, h17*/ ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode); ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++#endif +diff --git a/drivers/sstar/serial/infinity2/uart_pads.c b/drivers/sstar/serial/infinity2/uart_pads.c +new file mode 100755 +index 000000000000..28f110429d07 +--- /dev/null ++++ b/drivers/sstar/serial/infinity2/uart_pads.c +@@ -0,0 +1,154 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++#include "ms_platform.h" ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode) ++{ ++ /* u8 select=0; ++ ++ if(p->line == 0) ++ select=UART_PIU_UART0; //PIU UART0 ++ else if(p->line == 1) ++ select=UART_PIU_UART1; //PIU UART1 ++ else if(p->line == 2) ++ select=UART_PIU_UART2; //PIU UART2 ++ else if(p->line == 3) ++ select=UART_PIU_FUART; //PIU FUART ++ else ++ { ++ UART_ERR("[%s] port line %d is not supported\n", __func__, p->line); ++ return; ++ } ++*/ ++//printk("ms_select_pad padmux:%d: pad_mode:%d: select:%d \n", padmux, pad_mode, select); ++ ++ switch(padmux) ++ { ++ case DIG_MUX_SEL0: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0 ++ break; ++ case DIG_MUX_SEL1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 3, 0x7 << 3); ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel1 ++ break; ++ case DIG_MUX_SEL2: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 6, 0x7 << 6); ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel2 ++ break; ++ case DIG_MUX_SEL3: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x3 << 0); ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel3 ++ break; ++ case DIG_MUX_SEL4: ++ OUTREGMSK16(REG_FUART_MODE, pad_mode << 0, 0x3 << 0); ++ OUTREGMSK16(REG_FUART_SEL, select << 0, 0xF << 0); //reg_uart_sel4 ++ break; ++ default: ++ //UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(tx_pad) ++ { ++ case PAD_UART0_TX: ++ *padmux=DIG_MUX_SEL1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_I2C2_SDA: ++ *padmux=DIG_MUX_SEL1; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_SNR1_GPIO2: ++ *padmux=DIG_MUX_SEL1; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_UART1_TX: ++ *padmux=DIG_MUX_SEL2; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_SPI0_CK: ++ *padmux=DIG_MUX_SEL2; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_SNR3_D4: ++ *padmux=DIG_MUX_SEL2; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_HSYNC_OUT: ++ *padmux=DIG_MUX_SEL2; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_UART2_TX: ++ *padmux=DIG_MUX_SEL3; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_TTL_HSYNC: ++ *padmux=DIG_MUX_SEL3; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_FUART_RTS: ++ *padmux=DIG_MUX_SEL3; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_SPI0_DO: ++ *padmux=DIG_MUX_SEL3; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_FUART_TX: ++ *padmux=DIG_MUX_SEL4; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_NAND_DA4: ++ *padmux=DIG_MUX_SEL4; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_SNR3_D0: ++ *padmux=DIG_MUX_SEL4; ++ *pad_mode=0x3; ++ break; ++ ++ default: ++ //UART_ERR("[%s] Use undefined pad number %d\n", __func__, tx_pad); ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/infinity2m/ms_uart.h b/drivers/sstar/serial/infinity2m/ms_uart.h +new file mode 100755 +index 000000000000..068ade308955 +--- /dev/null ++++ b/drivers/sstar/serial/infinity2m/ms_uart.h +@@ -0,0 +1,33 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define CONFIG_MS_SUPPORT_UART2 ++#define CONFIG_MS_SUPPORT_EXT_PADMUX // use external padmux driver ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++#define MUX_UART2 4 ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode); ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++#endif +diff --git a/drivers/sstar/serial/infinity2m/uart_pads.c b/drivers/sstar/serial/infinity2m/uart_pads.c +new file mode 100755 +index 000000000000..cc24bfc357a6 +--- /dev/null ++++ b/drivers/sstar/serial/infinity2m/uart_pads.c +@@ -0,0 +1,168 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++#include "ms_platform.h" ++ ++#define REG_UART_MODE 0x1F203C0C ++#define REG_UART_SEL 0x1F203D4C ++#define REG_UART_SEL4 0x1F203D50 ++#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0[3:0] ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x7 << 0); //reg_uart_mode[2:0] ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel0[7:4] ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 4, 0x7 << 4); //reg_uart_mode[6:4] ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel0[11:8] ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 8, 0x7 << 8); //reg_uart_mode[10:8] ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel0[15:12] ++ break; ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ case MUX_UART2: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 12, 0x7 << 12);//reg_uart_mode[14:12] ++ OUTREGMSK16(REG_UART_SEL4, select << 0, 0xF << 0); //reg_uart_sel4[3:0] ++ break; ++#endif ++ default: ++ // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(tx_pad) ++ { ++ case PAD_FUART_CTS: ++ *padmux=MUX_FUART; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RX: ++ *padmux=MUX_FUART; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_TTL1: ++ *padmux=MUX_FUART; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_TTL21: ++ *padmux=MUX_FUART; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_GPIO1: ++ *padmux=MUX_FUART; ++ *pad_mode=0x5; ++ break; ++ ++ case PAD_GPIO5: ++ *padmux=MUX_FUART; ++ *pad_mode=0x6; ++ break; ++ ++ case PAD_SD_D0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x7; ++ break; ++ ++ case PAD_UART0_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RTS: ++ *padmux=MUX_UART0; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_TTL13: ++ *padmux=MUX_UART0; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_GPIO9: ++ *padmux=MUX_UART0; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_UART1_TX: ++ *padmux=MUX_UART1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_TTL15: ++ *padmux=MUX_UART1; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO14: ++ *padmux=MUX_UART1; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_GPIO11: ++ *padmux=MUX_UART1; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_FUART_TX: ++ *padmux=MUX_UART2; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO8: ++ *padmux=MUX_UART2; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_VSYNC_OUT: ++ *padmux=MUX_UART2; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_SD_D2: ++ *padmux=MUX_UART2; ++ *pad_mode=0x4; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/infinity3e/ms_uart.h b/drivers/sstar/serial/infinity3e/ms_uart.h +new file mode 100755 +index 000000000000..fb9c545ec5ba +--- /dev/null ++++ b/drivers/sstar/serial/infinity3e/ms_uart.h +@@ -0,0 +1,29 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++ ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++ ++#endif +diff --git a/drivers/sstar/serial/infinity3e/uart_pads.c b/drivers/sstar/serial/infinity3e/uart_pads.c +new file mode 100755 +index 000000000000..01442fc16cc6 +--- /dev/null ++++ b/drivers/sstar/serial/infinity3e/uart_pads.c +@@ -0,0 +1,76 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++ ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(tx_pad) ++ { ++ case PAD_FUART_RX: ++ *padmux=MUX_FUART; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_UART0_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO4: ++ *padmux=MUX_UART0; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_UART1_TX: ++ *padmux=MUX_UART1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RTS: ++ *padmux=MUX_UART1; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO6: ++ *padmux=MUX_UART1; ++ *pad_mode=0x3; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/infinity5/ms_uart.h b/drivers/sstar/serial/infinity5/ms_uart.h +new file mode 100755 +index 000000000000..26e81b0b37a9 +--- /dev/null ++++ b/drivers/sstar/serial/infinity5/ms_uart.h +@@ -0,0 +1,30 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode); ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++ ++#endif +diff --git a/drivers/sstar/serial/infinity5/uart_pads.c b/drivers/sstar/serial/infinity5/uart_pads.c +new file mode 100755 +index 000000000000..c7bdc6702971 +--- /dev/null ++++ b/drivers/sstar/serial/infinity5/uart_pads.c +@@ -0,0 +1,114 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++#include "ms_platform.h" ++ ++#define REG_UART_MODE 0x1F203C0C ++#define REG_UART_SEL 0x1F203D4C ++#define REG_UART_SEL4 0x1F203D50 ++#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0[3:0] ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x7 << 0); //reg_uart_mode[2:0] ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel0[7:4] ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 4, 0x7 << 4); //reg_uart_mode[6:4] ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel0[11:8] ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 8, 0x7 << 8); //reg_uart_mode[10:8] ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel0[15:12] ++ break; ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ case MUX_UART2: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 12, 0x7 << 12);//reg_uart_mode[14:12] ++ OUTREGMSK16(REG_UART_SEL4, select << 0, 0xF << 0); //reg_uart_sel4[3:0] ++ break; ++#endif ++ default: ++ // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(tx_pad) ++ { ++ case PAD_FUART_RX: ++ *padmux=MUX_FUART; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_UART0_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO4: ++ *padmux=MUX_UART0; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_UART1_TX: ++ *padmux=MUX_UART1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RTS: ++ *padmux=MUX_UART1; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO6: ++ *padmux=MUX_UART1; ++ *pad_mode=0x3; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/infinity6/ms_uart.h b/drivers/sstar/serial/infinity6/ms_uart.h +new file mode 100755 +index 000000000000..26e81b0b37a9 +--- /dev/null ++++ b/drivers/sstar/serial/infinity6/ms_uart.h +@@ -0,0 +1,30 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode); ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++ ++#endif +diff --git a/drivers/sstar/serial/infinity6/uart_pads.c b/drivers/sstar/serial/infinity6/uart_pads.c +new file mode 100755 +index 000000000000..c7bdc6702971 +--- /dev/null ++++ b/drivers/sstar/serial/infinity6/uart_pads.c +@@ -0,0 +1,114 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++#include "ms_platform.h" ++ ++#define REG_UART_MODE 0x1F203C0C ++#define REG_UART_SEL 0x1F203D4C ++#define REG_UART_SEL4 0x1F203D50 ++#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0[3:0] ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x7 << 0); //reg_uart_mode[2:0] ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel0[7:4] ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 4, 0x7 << 4); //reg_uart_mode[6:4] ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel0[11:8] ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 8, 0x7 << 8); //reg_uart_mode[10:8] ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel0[15:12] ++ break; ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ case MUX_UART2: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 12, 0x7 << 12);//reg_uart_mode[14:12] ++ OUTREGMSK16(REG_UART_SEL4, select << 0, 0xF << 0); //reg_uart_sel4[3:0] ++ break; ++#endif ++ default: ++ // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(tx_pad) ++ { ++ case PAD_FUART_RX: ++ *padmux=MUX_FUART; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_UART0_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO4: ++ *padmux=MUX_UART0; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_UART1_TX: ++ *padmux=MUX_UART1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RTS: ++ *padmux=MUX_UART1; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO6: ++ *padmux=MUX_UART1; ++ *pad_mode=0x3; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/infinity6b0/ms_uart.h b/drivers/sstar/serial/infinity6b0/ms_uart.h +new file mode 100755 +index 000000000000..26e81b0b37a9 +--- /dev/null ++++ b/drivers/sstar/serial/infinity6b0/ms_uart.h +@@ -0,0 +1,30 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode); ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++ ++#endif +diff --git a/drivers/sstar/serial/infinity6b0/uart_pads.c b/drivers/sstar/serial/infinity6b0/uart_pads.c +new file mode 100755 +index 000000000000..43ef93acf3ff +--- /dev/null ++++ b/drivers/sstar/serial/infinity6b0/uart_pads.c +@@ -0,0 +1,144 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++#include "ms_platform.h" ++ ++#define REG_UART_MODE 0x1F203C0C /*0x101E, h03*/ ++#define REG_UART_SEL 0x1F203D4C /*0x101E, h53*/ ++#define REG_UART_SEL4 0x1F203D50 ++#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0[3:0] ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x7 << 0); //reg_uart_mode[2:0] ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel0[7:4] ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 4, 0x7 << 4); //reg_uart_mode[6:4] ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel0[11:8] ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 8, 0x7 << 8); //reg_uart_mode[10:8] ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel0[15:12] ++ break; ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ case MUX_UART2: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 12, 0x7 << 12);//reg_uart_mode[14:12] ++ OUTREGMSK16(REG_UART_SEL4, select << 0, 0xF << 0); //reg_uart_sel4[3:0] ++ break; ++#endif ++ default: ++ // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ ++ switch(tx_pad) ++ { ++ case PAD_FUART_CTS: ++ *padmux=MUX_FUART; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO15: ++ *padmux=MUX_FUART; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_SD1_IO1: ++ *padmux=MUX_FUART; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_FUART_RX: ++ *padmux=MUX_FUART; ++ *pad_mode=0x5; ++ break; ++ ++ case PAD_SD1_IO0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x6; ++ break; ++ ++ case PAD_UART0_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_TX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO4: ++ *padmux=MUX_UART0; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_SD1_IO7: ++ *padmux=MUX_UART0; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_UART1_TX: ++ *padmux=MUX_UART1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RTS: ++ *padmux=MUX_UART1; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO6: ++ *padmux=MUX_UART1; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_GPIO13: ++ *padmux=MUX_UART1; ++ *pad_mode=0x4; ++ break; ++ ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/infinity6e/ms_uart.h b/drivers/sstar/serial/infinity6e/ms_uart.h +new file mode 100755 +index 000000000000..ddb82d2a5977 +--- /dev/null ++++ b/drivers/sstar/serial/infinity6e/ms_uart.h +@@ -0,0 +1,31 @@ ++/* ++* ms_uart.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MS_UART_H_ ++#define _MS_UART_H_ ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++#define MUX_PM_UART1 4 ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode); ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode); ++ ++#endif +diff --git a/drivers/sstar/serial/infinity6e/uart_pads.c b/drivers/sstar/serial/infinity6e/uart_pads.c +new file mode 100755 +index 000000000000..a7d93b49368b +--- /dev/null ++++ b/drivers/sstar/serial/infinity6e/uart_pads.c +@@ -0,0 +1,246 @@ ++/* ++* uart_pads.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#include ++ ++#include "ms_uart.h" ++#include "gpio.h" ++#include "ms_platform.h" ++ ++#define REG_UART_MODE 0x1F2079B4 ++#define REG_FUART_MODE 0x1F2079B8 ++#define REG_UART_SEL 0x1F203D4C ++#define REG_UART_SEL4 0x1F203D50 ++//#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++ ++void ms_uart_select_pad( u8 select, u8 padmux, u8 pad_mode) ++{ ++ switch(padmux) ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0[3:0] ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_FUART_MODE, pad_mode << 4, 0x7 << 4); //reg_uart_mode[2:0] ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel0[7:4] ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x7 << 0); //reg_uart_mode[6:4] ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel0[11:8] ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 4, 0x7 << 4); //reg_uart_mode[10:8] ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel0[15:12] ++ break; ++ case MUX_PM_UART1: ++ break; ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ case MUX_UART2: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 8, 0x7 << 8);//reg_uart_mode[14:12] ++ OUTREGMSK16(REG_UART_SEL4, select << 0, 0xF << 0); //reg_uart_sel4[3:0] ++ break; ++#endif ++ default: ++ // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++int ms_uart_get_padmux(int tx_pad, u8 *padmux, u8 *pad_mode) ++{ ++ int ret = 0; ++ unsigned short TempU16 = 0; ++ ++ switch(tx_pad) ++ { ++ //reg_uart0_mode 1~4 ++ case PAD_PM_UART_RX: ++ *padmux=MUX_UART0; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_ETH_LED0: ++ *padmux=MUX_UART0; ++ *pad_mode=0x2; ++ break; ++ ++ case PAD_I2S0_BCK: ++ *padmux=MUX_UART0; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_GPIO14: ++ *padmux=MUX_UART0; ++ *pad_mode=0x4; ++ break; ++ ++ //reg_fuart_mode 1~7 ++ case PAD_FUART_RX: ++ //reg_ckg_fuart0_synth_in ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ); ++ TempU16 &= 0xFF00; //172.8m 432m ++ ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x22 << 2) ) ); ++ TempU16 &= 0xFFF0;//PAD_FUART_CTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x22 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x23 << 2) ) ); ++ TempU16 &= 0xFFF0; //PAD_FUART_RTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x23 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x24 << 2) ) ); ++ TempU16 &= 0xFFF0;//PAD_FUART_CTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x24 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x25 << 2) ) ); ++ TempU16 &= 0xFFF0; //PAD_FUART_RTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x25 << 2) ) ) = TempU16; ++ ++ *padmux=MUX_FUART; ++ *pad_mode=0x1; ++ break; ++ ++ /*case PAD_GPIO0: ++ *padmux=MUX_FUART; ++ *pad_mode=0x2; ++ break;*/ ++ ++ case PAD_PM_GPIO0: ++ //reg_ckg_fuart0_synth_in ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ); ++ TempU16 &= 0xFF00; //172.8m 432m ++ ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ) = TempU16; ++ ++ //PADPMTOP setting ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x55 << 2) ) ); ++ TempU16 |= 0xF0; // reg_pm_pad_ext_mode #4~#7 =1 ++ ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x55 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x00 << 2) ) ); ++ TempU16 &= 0xFFF0;//PAD_FUART_CTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x00 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x01 << 2) ) ); ++ TempU16 &= 0xFFF0; //PAD_FUART_RTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x01 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x02 << 2) ) ); ++ TempU16 &= 0xFFF0;//PAD_FUART_CTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x02 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x03 << 2) ) ); ++ TempU16 &= 0xFFF0; //PAD_FUART_RTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x03 << 2) ) ) = TempU16; ++ ++ *padmux=MUX_FUART; ++ *pad_mode=0x3; ++ break; ++ ++ case PAD_SD1_D1: ++ //reg_ckg_fuart0_synth_in ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ); ++ TempU16 &= 0xFF00; //172.8m 432m ++ ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ) = TempU16; ++ ++ *padmux=MUX_FUART; ++ *pad_mode=0x4; ++ break; ++ ++ /*case PAD_FUART_RX: ++ *padmux=MUX_FUART; ++ *pad_mode=0x5; ++ break;*/ ++ ++ case PAD_PM_GPIO2: ++ //reg_ckg_fuart0_synth_in ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ); ++ TempU16 &= 0xFF00; //172.8m 432m ++ ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ) = TempU16; ++ ++ //PADPMTOP setting ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x55 << 2) ) ); ++ TempU16 |= 0xc0; // reg_pm_pad_ext_mode #6~#7 =1 ++ ( *(volatile unsigned short *)(0xFD000000 +(0x003F * 0x0200) +(0x55 << 2) ) ) = TempU16; ++ ++ ++ *padmux=MUX_FUART; ++ *pad_mode=0x6; ++ break; ++ ++ case PAD_PM_SPI_CZ: ++ //reg_ckg_fuart0_synth_in ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ); ++ TempU16 &= 0xFF00; //172.8m 432m ++ ( *(volatile unsigned short *)(0xFD000000 +(0x1038 * 0x0200) +(0x34 << 2) ) ) = TempU16; ++ ++ *padmux=MUX_FUART; ++ *pad_mode=0x7; ++ break; ++ ++ //reg_uart1_mode 1~6 ++ case PAD_GPIO0: ++ *padmux=MUX_UART1; ++ *pad_mode=0x1; ++ break; ++ ++ case PAD_I2S0_DI: ++ *padmux=MUX_UART1; ++ *pad_mode=0x2; ++ break; ++ ++ /*case PAD_ETH_LED0: ++ *padmux=MUX_UART1; ++ *pad_mode=0x3; ++ break;*/ ++ ++ case PAD_GPIO4: ++ *padmux=MUX_UART1; ++ *pad_mode=0x4; ++ break; ++ ++ case PAD_FUART_CTS: ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x24 << 2) ) ); ++ TempU16 &= 0xFFF0;//PAD_FUART_CTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x24 << 2) ) ) = TempU16; ++ ++ TempU16 = ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x25 << 2) ) ); ++ TempU16 &= 0xFFF0; //PAD_FUART_RTS ++ ( *(volatile unsigned short *)(0xFD000000 +(0x103C * 0x0200) +(0x25 << 2) ) ) = TempU16; ++ ++ *padmux=MUX_UART1; ++ *pad_mode=0x5; ++ break; ++ ++ case PAD_GPIO8: ++ *padmux=MUX_UART1; ++ *pad_mode=0x6; ++ break; ++ case PAD_PM_UART_RX1: ++ *padmux=MUX_PM_UART1; ++ *pad_mode=0xf; ++ break; ++ default: ++ ret = -1; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/sstar/serial/ms_uart.c b/drivers/sstar/serial/ms_uart.c +new file mode 100755 +index 000000000000..86657b846fe8 +--- /dev/null ++++ b/drivers/sstar/serial/ms_uart.c +@@ -0,0 +1,2848 @@ ++/* ++* ms_uart.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "gpio.h" ++#include "ms_uart.h" ++#include "drv_camclk_Api.h" ++#define CONSOLE_DMA 1 ++#define DEBUG_PAD_MUX 0 ++ ++#define SUPPORT_TX_LEVEL 1 ++#define UART_DEBUG 0 ++#define MS_UART_8250_BUG_THRE 0 ++#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ ++ ++#if UART_DEBUG ++#define UART_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define UART_DBG(fmt, arg...) ++#endif ++#define UART_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++//#define REG_UART_MODE 0x1F203C0C ++//#define REG_UART_SEL 0x1F203D4C ++//#define REG_UART_SEL4 0x1F203D50 ++#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++#define UART_TX_TASK 0 /* use tasklet to send TX char */ ++#define UART_USE_LOOPBACK 0 /* use UART loopback mode to avoid external input */ ++#define UART_USE_SPINLOCK 0 /* set IER use spinlock to ensure atomic */ ++ ++#if CONSOLE_DMA ++#define NR_CONSOLE_PORTS 4 ++#else ++#define NR_CONSOLE_PORTS 1 ++#endif ++#define MS_CONSOLE_DEV "ttyS" ++ ++#define REG_DLL_THR_RBR(p) GET_REG_ADDR((u32)p->membase, (0x00)) ++#define REG_DLH_IER(p) GET_REG_ADDR((u32)p->membase, (0x02)) ++#define REG_IIR_FCR(p) GET_REG_ADDR((u32)p->membase, (0x04)) ++#define REG_LCR(p) GET_REG_ADDR((u32)p->membase, (0x06)) ++#define REG_MCR(p) GET_REG_ADDR((u32)p->membase, (0x08)) ++#define REG_LSR(p) GET_REG_ADDR((u32)p->membase, (0x0A)) ++#define REG_MSR(p) GET_REG_ADDR((u32)p->membase, (0x0C)) ++#define REG_USR(p) GET_REG_ADDR((u32)p->membase, (0x0E)) ++#define REG_TFL(p) GET_REG_ADDR((u32)p->membase, (0x10)) ++#define REG_RFL(p) GET_REG_ADDR((u32)p->membase, (0x12)) ++#define REG_RST(p) GET_REG_ADDR((u32)p->membase, (0x14)) ++ ++/* Interrupt Enable Register (IER)*/ ++#define UART_IER_RDI 0x01 /* Received Data Available Interrupt */ ++#define UART_IER_THRI 0x02 /* Transmitter Holding Register Empty Interrupt */ ++#define UART_IER_RLSI 0x04 /* Receiver Line Status Interrupt */ ++#define UART_IER_MSI 0x08 /* Modem Status Interrupt */ ++#if SUPPORT_TX_LEVEL ++ #define UART_IER_PTHRI 0x80 /* Programmable THRE Interrupt */ ++#else ++ #define UART_IER_PTHRI 0x00 /* Don't Set Programmable THRE Interrupt */ ++#endif ++ ++/* Interrupt Identification Register (IIR) */ ++#define UART_IIR_MSI 0x00 /* 0000: Modem Status */ ++#define UART_IIR_NO_INT 0x01 /* 0001: No pending interrupts */ ++#define UART_IIR_THRI 0x02 /* 0010: Transmitter Holding Register Empty */ ++#define UART_IIR_RDI 0x04 /* 0100: Receiver Data Available */ ++#define UART_IIR_RLSI 0x06 /* 0110: Receiver Line Status */ ++#define UART_IIR_BUSY 0x07 /* 0111: Busy detect indication (try to write LCR while UART is busy) */ ++#define UART_IIR_RX_TIMEOUT 0x0C /* 1100: Character timeout */ ++#define UART_IIR_ID_MASK 0x0F /* Mask Bit[3:0] for IIR */ ++ ++/* FIFO Control Register (FCR) */ ++#define UART_FCR_FIFO_ENABLE 0x01 /* Clear & Reset Rx FIFO buffer */ ++#define UART_FCR_CLEAR_RCVR 0x02 /* Clear & Reset Rx FIFO buffer */ ++#define UART_FCR_CLEAR_XMIT 0x04 /* Clear & Reset Tx FIFO buffer */ ++#define UART_FCR_TRIGGER_TX_L0 0x00 /* Trigger Write when emtpy */ ++#define UART_FCR_TRIGGER_TX_L1 0x10 /* Trigger Write when 2 characters */ ++#define UART_FCR_TRIGGER_TX_L2 0x20 /* Trigger Write when 1/4 full */ ++#define UART_FCR_TRIGGER_TX_L3 0x30 /* Trigger Write when 1/2 full */ ++#define UART_FCR_TRIGGER_RX_L0 0x00 /* Trigger Read when there is 1 char*/ ++#define UART_FCR_TRIGGER_RX_L1 0x40 /* Trigger Read when 1/4 full */ ++#define UART_FCR_TRIGGER_RX_L2 0x80 /* Trigger Read when 1/2 full */ ++#define UART_FCR_TRIGGER_RX_L3 0xC0 /* Trigger Read when 2 less then full */ ++ ++/* Line Control Register (LCR) */ ++#define UART_LCR_WL_MASK 0x03 /* Word length mask */ ++#define UART_LCR_WLEN5 0x00 /* Word length is 5 bits */ ++#define UART_LCR_WLEN6 0x01 /* Word length is 6 bits */ ++#define UART_LCR_WLEN7 0x02 /* Word length is 7 bits */ ++#define UART_LCR_WLEN8 0x03 /* Word length is 8 bits */ ++#define UART_LCR_STOP_MASK 0x04 /* Stop bit mask */ ++#define UART_LCR_STOP1 0x00 /* Stop length is 1 bit */ ++#define UART_LCR_STOP2 0x04 /* Stop length is 1.5 bits (5-bit char), 2 bits (otherwise) */ ++#define UART_LCR_PARITY_EN 0x08 /* Parity Enable */ ++#define UART_LCR_PARITY_SEL 0x10 /* Even Parity Select */ ++#define UART_LCR_SBC 0x40 /* Set break control */ ++#define UART_LCR_DLAB 0x80 /* Divisor Latch Access bit, 1=Divisor Latch, 0=Normal Register */ ++ ++#define UART_MCR_DTR 0x01 ++#define UART_MCR_RTS 0x02 ++#define UART_MCR_OUT1 0x04 ++#define UART_MCR_OUT2 0x08 ++#define UART_MCR_LOOPBACK 0x10 ++#define UART_MCR_AFCE 0x20 ++ ++/* Line Status Register */ ++#define UART_LSR_DR 0x01 /* Data Ready, at least one char in FIFO buffer*/ ++#define UART_LSR_OE 0x02 /* Overrun Error, FIFO buffer is full */ ++#define UART_LSR_PE 0x04 /* Parity Error */ ++#define UART_LSR_FE 0x08 /* Framing Error, no valid stop bit */ ++#define UART_LSR_BI 0x10 /* Break Interrupt */ ++#define UART_LSR_THRE 0x20 /* Tx FIFO buffer is empty*/ ++#define UART_LSR_TEMT 0x40 /* Both TX FIFO buffer & shift register are empty */ ++#define UART_LSR_TX_ERROR 0x80 /* Tx FIFO buffer is error */ ++ ++#define UART_USR_BUSY 0x01 ++#define UART_USR_TXFIFO_NOT_FULL 0x02 ++#define UART_USR_TXFIFO_EMPTY 0x04 ++ ++ ++#define UR2DMA_TX_BUF_LENGTH 0x1000 //must be 8 byte aligned, linux should better be PAGE_ALIGN ++#define UR2DMA_TX_BUF_MASK 0x0FFF ++#define UR2DMA_RX_BUF_LENGTH 0x1000 //must be 8 byte aligned, linux should better be PAGE_ALIGN ++ ++#define URDMA_RX_TIMEOUT 0x0F ++#define URDMA_TX_TIMEOUT 0x0F ++ ++#define URDMA_RX_INTR_LEVEL 0x500 //need to think ++ ++#define URDMA_RX_INTR_TYPE_TIMEOUT 1 ++#define URDMA_RX_INTR_TYPE_THRESHOLD 2 ++ ++#define URDMA_INTR_STATUS_RX 1 ++#define URDMA_INTR_STATUS_TX 2 ++ ++#define URDMA_LOU16(u32Val) ((U16)(u32Val)&0xFFFF) ++#define URDMA_HIU16(u32Val) ((U16)((u32Val) >> 16)&0x0FFF) ++ ++#define URDMA_logical2bus(x) (x&0x0FFFFFFF) ++ ++/* Warning: Little Endian */ ++typedef struct reg_urdma ++{ ++ union ++ { ++ volatile U16 reg00; ++ struct ++ { ++ volatile U16 sw_rst : 1; /* BIT0 */ ++ volatile U16 urdma_mode : 1; /* BIT1 */ ++ volatile U16 tx_urdma_en : 1; /* BIT2 */ ++ volatile U16 rx_urdma_en : 1; /* BIT3 */ ++ volatile U16 tx_endian : 1; /* BIT4 */ ++ volatile U16 rx_endian : 1; /* BIT5 */ ++ volatile U16 tx_sw_rst : 1; /* BIT6 */ ++ volatile U16 rx_sw_rst : 1; /* BIT7 */ ++ volatile U16 reserve00 : 3; /* BIT8 ~ BIT10 */ ++ volatile U16 rx_op_mode : 1; /* BIT11 */ ++ volatile U16 tx_busy : 1; /* BIT12 */ ++ volatile U16 rx_busy : 1; /* BIT13 */ ++ volatile U16 reserve01 : 2; /* BIT14 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space00; ++ ++ union ++ { ++ volatile U16 reg01; ++ struct ++ { ++ volatile U16 intr_threshold : 12; /* BIT0 ~ BIT11 */ ++ volatile U16 reserve02 : 4; /* BIT12 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space01; ++ ++ union ++ { ++ volatile U16 reg02; ++ struct ++ { ++ volatile U16 tx_buf_base_h : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space02; ++ ++ union ++ { ++ volatile U16 reg03; ++ struct ++ { ++ volatile U16 tx_buf_base_l : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space03; ++ ++ union ++ { ++ volatile U16 reg04; ++ struct ++ { ++ volatile U16 tx_buf_size : 13; /* BIT0 ~ BIT12 */ ++ volatile U16 reserve04 : 3; /* BIT13 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space04; ++ ++ union ++ { ++ volatile U16 reg05; ++ struct ++ { ++ volatile U16 tx_buf_rptr : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space05; ++ ++ union ++ { ++ volatile U16 reg06; ++ struct ++ { ++ volatile U16 tx_buf_wptr : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space06; ++ ++ union ++ { ++ volatile U16 reg07; ++ struct ++ { ++ volatile U16 tx_timeout : 4; /* BIT0 ~ BIT3 */ ++ volatile U16 reserve05 : 12; /* BIT4 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space07; ++ ++ union ++ { ++ volatile U16 reg08; ++ struct ++ { ++ volatile U16 rx_buf_base_h : 16; /* BIT0 ~ BIT7 */ ++ } ; ++ } ; ++ U16 space08; ++ ++ union ++ { ++ volatile U16 reg09; ++ struct ++ { ++ volatile U16 rx_buf_base_l : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space09; ++ ++ union ++ { ++ volatile U16 reg0a; ++ struct ++ { ++ volatile U16 rx_buf_size : 13; /* BIT0 ~ BIT12 */ ++ volatile U16 reserve07 : 3; /* BIT13 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space0a; ++ ++ union ++ { ++ volatile U16 reg0b; ++ struct ++ { ++ volatile U16 rx_buf_wptr : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space0b; ++ ++ union ++ { ++ volatile U16 reg0c; ++ struct ++ { ++ volatile U16 rx_timeout : 4; /* BIT0 ~ BIT3 */ ++ volatile U16 reserve08 : 12; /* BIT4 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space0c; ++ ++ union ++ { ++ volatile U16 reg0d; ++ struct ++ { ++ volatile U16 rx_intr_clr : 1; /* BIT0 */ ++ volatile U16 rx_intr1_en : 1; /* BIT1 */ ++ volatile U16 rx_intr2_en : 1; /* BIT2 */ ++ volatile U16 reserve09 : 1; /* BIT3 */ ++ volatile U16 rx_intr1 : 1; /* BIT4 */ ++ volatile U16 rx_intr2 : 1; /* BIT5 */ ++ volatile U16 reserve0a : 1; /* BIT6 */ ++ volatile U16 rx_mcu_intr : 1; /* BIT7 */ ++ volatile U16 tx_intr_clr : 1; /* BIT8 */ ++ volatile U16 tx_intr_en : 1; /* BIT9 */ ++ volatile U16 reserve0b : 5; /* BIT10 ~ BIT14 */ ++ volatile U16 tx_mcu_intr : 1; /* BIT15 */ ++ } ; ++ } ; ++} reg_urdma; ++ ++struct ms_urdma ++{ ++ reg_urdma *reg_base; ++ unsigned int urdma_irq; ++ u8 *rx_buf; ++ u8 *tx_buf; ++ dma_addr_t rx_urdma_base; ++ dma_addr_t tx_urdma_base; ++ u32 rx_urdma_size; ++ u32 tx_urdma_size; ++ u16 sw_rx_rptr; ++}; ++ ++ ++struct ms_uart_port { ++ struct uart_port port; ++ struct ms_urdma *urdma; ++ struct device *dev; ++ struct clk *clk; ++#ifdef CONFIG_CAM_CLK ++ CAMCLK_Get_Attribute stCfg; ++ void *pvclk; ++#endif ++ int use_dma; ++#if UART_TX_TASK ++ struct tasklet_struct xmit_tasklet; ++#endif ++ int rx_guard; ++ u8 backupIER; ++ u8 backupLCR; ++ u8 backupMCR; ++ u16 backupDivisor; ++ u8 padmux; ++ u8 pad_mode; ++ struct timer_list timer; /* "no irq" timer */ ++ u16 bugs; /* port bugs */ ++ struct task_struct *urdma_task; ++}; ++ ++static u32 ms_uart_tx_empty(struct uart_port *p); ++static void ms_uart_set_mctrl(struct uart_port *pPort_st, u32 mctrl); ++static u32 ms_uart_get_mctrl(struct uart_port *pPort_st); ++static void ms_uart_stop_tx(struct uart_port *p); ++static void ms_uart_start_tx(struct uart_port *p); ++static void ms_uart_stop_rx(struct uart_port *p); ++static void ms_uart_enable_ms(struct uart_port *pPort_st); ++static void ms_uart_break_ctl(struct uart_port *pPort_st, s32 break_state); ++static s32 ms_uart_startup(struct uart_port *p); ++static void ms_uart_shutdown(struct uart_port *p); ++static void ms_uart_set_termios(struct uart_port *p, struct ktermios *pTermios_st, struct ktermios *pOld_st); ++static const char * ms_uart_type(struct uart_port *pPort_st); ++static void ms_uart_release_port(struct uart_port *pPort_st); ++static void ms_uart_release_port(struct uart_port *pPort_st); ++static s32 ms_uart_request_port(struct uart_port *pPort_st); ++static void ms_uart_config_port(struct uart_port *pPort_st, s32 flags); ++static s32 ms_uart_verify_port(struct uart_port *pPort_st, struct serial_struct *ser); ++ ++/* UART Operations */ ++static struct uart_ops ms_uart_ops = ++{ ++ .tx_empty = ms_uart_tx_empty, ++ .set_mctrl = ms_uart_set_mctrl, /* Not supported in MSB2501 */ ++ .get_mctrl = ms_uart_get_mctrl, /* Not supported in MSB2501 */ ++ .stop_tx = ms_uart_stop_tx, ++ .start_tx = ms_uart_start_tx, ++ .stop_rx = ms_uart_stop_rx, ++ .enable_ms = ms_uart_enable_ms, /* Not supported in MSB2501 */ ++ .break_ctl = ms_uart_break_ctl, /* Not supported in MSB2501 */ ++ .startup = ms_uart_startup, ++ .shutdown = ms_uart_shutdown, ++ .set_termios = ms_uart_set_termios, ++ .type = ms_uart_type, /* Not supported in MSB2501 */ ++ .release_port = ms_uart_release_port, /* Not supported in MSB2501 */ ++ .request_port = ms_uart_request_port, /* Not supported in MSB2501 */ ++ .config_port = ms_uart_config_port, /* Not supported in MSB2501 */ ++ .verify_port = ms_uart_verify_port, /* Not supported in MSB2501 */ ++}; ++ ++static void ms_uart_console_write(struct console *co, const char *str, u32 count); ++static s32 ms_uart_console_setup(struct console *co, char *options); ++#if CONSOLE_DMA ++static s32 _ms_uart_console_prepare(int idx); ++static int ms_uart_console_match(struct console *co, char *name, int idx, char *options); ++static int urdma_tx_thread(void * arg); ++static int _urdma_tx(struct ms_uart_port *mp, unsigned char* buf, int buf_size); ++static DEFINE_SPINLOCK(mutex_console_2_dma); ++#else ++static void ms_uart_add_console_port(struct ms_uart_port *ur); ++static struct ms_uart_port *console_ports[NR_CONSOLE_PORTS]; ++#endif ++static struct ms_uart_port console_port; ++static struct uart_driver ms_uart_driver; ++ ++/* Serial Console Structure Definition */ ++static struct console ms_uart_console = ++{ ++ .name = MS_CONSOLE_DEV, ++ .write = ms_uart_console_write, ++ .setup = ms_uart_console_setup, ++ .flags = CON_PRINTBUFFER, ++ .device = uart_console_device, ++ .data = &ms_uart_driver, ++ .index = -1, ++#if CONSOLE_DMA ++ .match = ms_uart_console_match, ++#endif ++}; ++ ++ ++static struct uart_driver ms_uart_driver = { ++ .owner = THIS_MODULE, ++ .driver_name = "ms_uart", ++ .dev_name = "ttyS", ++ .nr = 8, ++ .cons = &ms_uart_console, ++}; ++ ++static DECLARE_WAIT_QUEUE_HEAD(urdma_wait); ++static volatile int urdma_conditions = 0; ++ ++// extern void Chip_UART_Disable_Line(int line); ++// extern void Chip_UART_Enable_Line(int line); ++ ++static void URDMA_Reset(struct uart_port *p); ++static void URDMA_Activate(struct uart_port *p,BOOL bEnable); ++static void URDMA_TxEnable(struct uart_port *p,BOOL bEnable); ++static void URDMA_RxEnable(struct uart_port *p,BOOL bEnable); ++static U8 URDMA_GetInterruptStatus(struct uart_port *p); ++static void URDMA_TxInit(struct uart_port *p); ++static void URDMA_RxInit(struct uart_port *p); ++static void URDMA_TxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnable); ++static void URDMA_TxClearInterrupt(struct uart_port *p); ++static void URDMA_RxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnableTimeout); ++static void URDMA_RxSetupThresholdInterrupt(struct uart_port *p,BOOL bEnableThreshold); ++static U8 URDMA_RxGetInterrupt(struct uart_port *p); ++static void URDMA_RxClearInterrupt(struct uart_port *p); ++static void URDMA_StartTx(struct uart_port *p); ++static void URDMA_StartRx(struct uart_port *p); ++ ++ ++void inline ms_uart_clear_fifos(struct uart_port *p) ++{ ++ unsigned int timeout=0; ++ while( ((INREG8(REG_USR(p)) & UART_USR_BUSY)) && timeout < 2000) ++ { ++ udelay(2); ++ OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); ++ timeout++; ++ } ++ if(timeout == 2000) ++ UART_ERR("Clean FIFO failed, buad rate set may failed\n"); ++} ++ ++static u8 u8SelectPad[] = { 2, 3, 1, 4 }; ++void ms_select_pad(struct uart_port *p, u8 padmux, u8 pad_mode) ++{ ++#if 0 ++ u8 select=0; ++ ++ if(p->line == 0) ++ select=2; ++ else if(p->line == 1) ++ select=3; ++ else if(p->line == 2) ++ select=1; ++ else if(p->line == 3) ++ select=4; ++ else ++ { ++ // UART_ERR("[%s] port line %d is not supported\n", __func__, p->line); ++ return; ++ } ++ ++ ms_uart_select_pad(select, padmux, pad_mode); ++#else ++ ms_uart_select_pad(u8SelectPad[p->line], padmux, pad_mode); ++#endif ++} ++ ++void ms_force_rx_disable(u8 padmux, BOOL status) ++{ ++ switch(padmux) //set 0 for disable, 1 for enable ++ { ++ case MUX_FUART: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 1, 1 << 1); ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 2, 1 << 2); ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 3, 1 << 3); ++ break; ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ case MUX_UART2: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 4, 1 << 4); ++ break; ++#endif ++ default: ++ // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++U16 ms_uart_set_clk(struct uart_port *p, u32 request_baud) ++{ ++ unsigned int num_parents; ++ unsigned int tolerance, rate, divisor = 0, real_baud; ++ struct ms_uart_port *mp; ++ int i; ++ //int pm_uart = 0; ++#ifndef CONFIG_CAM_CLK ++ //struct clk *clk; ++ struct clk **clk_parents; ++ int pm_uart = 0; ++ ++ if(!p->dev) ++ { ++ //do nothing because clk and device node not ready ++ return 0; ++ } ++ else ++ { ++ mp = (struct ms_uart_port*)(p->dev->driver_data); ++ if (IS_ERR(mp->clk)) { ++ // UART_ERR("%s: of_clk_get failed\n", p->dev->of_node->full_name); ++ p->uartclk=172800000; ++ return 0; ++ } ++ if(of_property_read_u32(p->dev->of_node, "tolerance", &tolerance)) ++ { ++ UART_DBG("%s: use default tolerance 3%%\n", __func__); ++ tolerance = 3; ++ } ++ ++ of_property_read_u32(p->dev->of_node, "pm_uart", &pm_uart); ++ if(pm_uart) ++ { ++ rate = 108000000; ++ divisor = (rate + (8*request_baud)) / (16*request_baud); ++ real_baud = rate / (16 * divisor); ++ if( (abs(real_baud - request_baud)*100/request_baud) < tolerance) ++ { ++ p->uartclk=rate; ++ // UART_ERR("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor); ++ } ++ else ++ { ++ divisor = 0; ++ } ++ return divisor; ++ } ++ ++ num_parents = clk_hw_get_num_parents(__clk_get_hw(mp->clk)); ++ ++ if(!num_parents) ++ { ++ rate=clk_get_rate(mp->clk); ++ divisor = (rate + (8*request_baud)) / (16*request_baud); ++ real_baud = rate / (16 * divisor); ++ // UART_ERR("[uart%d]divisor=0x%02X, real_baud=%d,uart_clk=%d\n", p->line, divisor, real_baud,rate); ++ if( (abs(real_baud - request_baud)*100/request_baud) < tolerance) ++ { ++ p->uartclk=rate; ++ // UART_ERR("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor); ++ } ++ return divisor; ++ } ++ else ++ { ++ clk_parents = kzalloc((sizeof(*clk_parents) * num_parents), GFP_KERNEL); ++ if(!clk_parents) ++ { ++ // UART_ERR("%s: failed to allocate memory\n", __func__); ++ kfree(clk_parents); ++ p->uartclk=clk_get_rate(mp->clk); ++ return 0; ++ } ++ ++ for(i = 0; i < num_parents; i++) ++ { ++ clk_parents[i] = clk_hw_get_parent_by_index(__clk_get_hw(mp->clk), i)->clk; ++ rate = clk_get_rate(clk_parents[i]); ++ divisor = (rate + (8*request_baud)) / (16*request_baud); ++ real_baud = rate / (16 * divisor); ++ ++ UART_DBG("[uart%d]foreach parent divisor=0x%02X, real_baud=%d,uart_clk=%d\n", p->line, divisor, real_baud,rate); ++ if( (abs(real_baud - request_baud)*100/request_baud) < tolerance) ++ { ++ clk_set_parent(mp->clk, clk_parents[i]); ++ p->uartclk=rate; ++ UART_DBG("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor); ++ break; ++ } ++ } ++ ++ if(i >= num_parents) ++ { ++ // UART_ERR("[uart%d] can't find suitable clk for baud=%d tolerance=%d%%, will not changed\n", p->line, request_baud, tolerance); ++ divisor = 0; ++ } ++ kfree(clk_parents); ++ return divisor; ++ } ++ } ++#else ++ CAMCLK_Set_Attribute stCfg; ++ if(!p->dev) ++ { ++ //do nothing because clk and device node not ready ++ return 0; ++ } ++ else ++ { ++ mp = (struct ms_uart_port*)(p->dev->driver_data); ++ if (!mp->pvclk) { ++ // UART_ERR("%s: of_clk_get failed\n", p->dev->of_node->full_name); ++ p->uartclk=172800000; ++ return 0; ++ } ++ if(of_property_read_u32(p->dev->of_node, "tolerance", &tolerance)) ++ { ++ UART_DBG("%s: use default tolerance 3%%\n", __func__); ++ tolerance = 3; ++ } ++ num_parents = mp->stCfg.u32NodeCount; ++ if(num_parents==1) ++ { ++ rate=mp->stCfg.u32Rate; ++ divisor = (rate + (8*request_baud)) / (16*request_baud); ++ real_baud = rate / (16 * divisor); ++ // UART_ERR("[uart%d]divisor=0x%02X, real_baud=%d,uart_clk=%d\n", p->line, divisor, real_baud,rate); ++ if( (abs(real_baud - request_baud)*100/request_baud) < tolerance) ++ { ++ p->uartclk=rate; ++ // UART_ERR("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor); ++ } ++ return divisor; ++ } ++ else ++ { ++ for(i = 0; i < num_parents; i++) ++ { ++ if(mp->stCfg.u32Parent[i]) ++ { ++ rate = CamClkRateGet(mp->stCfg.u32Parent[i]); ++ divisor = (rate + (8*request_baud)) / (16*request_baud); ++ real_baud = rate / (16 * divisor); ++ ++ UART_DBG("[uart%d]foreach parent divisor=0x%02X, real_baud=%d,uart_clk=%d\n", p->line, divisor, real_baud,rate); ++ if( (abs(real_baud - request_baud)*100/request_baud) < tolerance) ++ { ++ CAMCLK_SETPARENT(stCfg,mp->stCfg.u32Parent[i]); ++ CamClkAttrSet(mp->pvclk,&stCfg); ++ p->uartclk=rate; ++ UART_DBG("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor); ++ break; ++ } ++ } ++ } ++ return divisor; ++ } ++ } ++#endif ++} ++ ++void ms_uart_set_divisor(struct uart_port *p, u16 divisor) ++{ ++ ms_uart_clear_fifos(p); ++ ++ // enable Divisor Latch Access, so Divisor Latch register can be accessed ++ OUTREG8(REG_LCR(p), INREG8(REG_LCR(p)) | UART_LCR_DLAB); ++ OUTREG8(REG_DLH_IER(p), (u8 )((divisor >> 8) & 0xff)); // CAUTION: this causes IER being overwritten also ++ OUTREG8(REG_DLL_THR_RBR(p), (u8 )(divisor & 0xff)); ++ // disable Divisor Latch Access ++ OUTREG8(REG_LCR(p), INREG8(REG_LCR(p)) & ~UART_LCR_DLAB); ++} ++ ++static void ms_uart_console_putchar(struct uart_port *p, s32 ch) ++{ ++#if SUPPORT_TX_LEVEL ++ u8 usr_u8 = 0; /* UART Status Register (USR) */ ++ /* Check if Transmit FIFO full */ ++ /* We always enable FIFO mode */ ++ ++ usr_u8 = INREG8(REG_USR(p)); ++ while(!(usr_u8 & UART_USR_TXFIFO_NOT_FULL)) ++ { ++ usr_u8 = INREG8(REG_USR(p)); ++ } ++#else ++ u8 lsr_u8 = 0; /* Line Status Register (LSR) */ ++ ++ /* Check if Transmit FIFO full */ ++ /* we can not modify the Tx FIFO size, default is 1 byte size*/ ++ ++ lsr_u8 = INREG8(REG_LSR(p)); ++ while(!(lsr_u8 & UART_LSR_THRE)) ++ { ++ lsr_u8 = INREG8(REG_LSR(p)); ++ } ++#endif ++ OUTREG8(REG_DLL_THR_RBR(p),ch); ++ ++ /* Check if both TX FIFO buffer & shift register are empty */ ++ //lsr_u8 = INREG8(REG_LSR(p)); ++ //while((lsr_u8 & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)) ++ //{ ++ // lsr_u8 = INREG8(REG_LSR(p)); ++ //} ++} ++ ++#if CONSOLE_DMA ++static void __maybe_unused ms_uart_console_putchar_dma(struct uart_port *p, s32 ch) ++{ ++ unsigned char c = (unsigned char)(ch & 0xFF); ++ ++ while (1 != _urdma_tx(&console_port, &c, 1)); ++} ++ ++static int ms_uart_console_match(struct console *co, char *name, int idx, char *options) ++{ ++ co->index = idx; ++ return -ENODEV; ++} ++#endif ++ ++#if CONSOLE_DMA ++static s32 _ms_uart_console_prepare(int idx) ++{ ++ struct device_node *console_np; ++ struct resource res; ++ ++ char* uart_name[] = ++ { ++ "/soc/uart0@1F221000", ++ "/soc/uart1@1F221200", ++ "/soc/uart2@1F220400", ++ "/soc/uart2@1F221400", ++ }; ++ if ((0 > idx) || (NR_CONSOLE_PORTS <= idx)) ++ return -ENODEV; ++ console_np=of_find_node_by_path(uart_name[idx]); ++ if(!console_np) ++ { ++ console_np =of_find_node_by_path("console"); ++ idx = 0; ++ } ++ if(!console_np) ++ return -ENODEV; ++ ++ BUG_ON( of_address_to_resource(console_np,0,&res) ); ++ ++ console_port.port.membase = (void *)res.start; ++ ++ console_port.port.type = PORT_8250; ++ ++ console_port.port.ops=&ms_uart_ops; ++ console_port.port.regshift = 0; ++ console_port.port.fifosize = 32; //HW FIFO is 32Bytes ++ console_port.port.cons=&ms_uart_console; ++ ++ console_port.port.line= idx; ++ ms_uart_console.index = console_port.port.line; ++ ++ return 0; ++} ++ ++#define UART_RX (0 * 2) // In: Receive buffer (DLAB=0) ++#define UART_TX (0 * 2) // Out: Transmit buffer (DLAB=0) ++#define UART_DLL (0 * 2) // Out: Divisor Latch Low (DLAB=1) ++#define UART_DLM (1 * 2) // Out: Divisor Latch High (DLAB=1) ++#define UART_IER (1 * 2) // Out: Interrupt Enable Register ++#define UART_IIR (2 * 2) // In: Interrupt ID Register ++#define UART_FCR (2 * 2) // Out: FIFO Control Register ++#define UART_LCR (3 * 2) // Out: Line Control Register ++#define UART_MCR (4 * 2) // Out: Modem Control Register ++#define UART_LSR (5 * 2) // In: Line Status Register ++#define UART_MSR (6 * 2) // In: Modem Status Register ++#define UART_USR (7 * 2) // Out: USER Status Register ++#define UART_RST (14 * 2) // Out: SW rstz ++ ++// #define REG_ADDR_BASE_UART1 0xFD221200 ++// #define REG_ADDR_BASE_FUART 0xFD220400 ++#define UART_BASE IO_ADDRESS(console_port.port.membase) ++#define UART_REG8(_x_) ((U8 volatile *)(UART_BASE))[((_x_) * 4) - ((_x_) & 1)] ++ ++ #define UART_BAUDRATE 115200 ++ #define UART_CLK 172800000 ++ ++#define UART_LCR_PARITY 0x08 ++#define UART_FCR_ENABLE_FIFO 0x01 ++ ++// #define REG_UART_SEL3210 GET_REG16_ADDR(REG_ADDR_BASE_CHIPTOP, 0x53) ++// #define REG_RX_ENABLE GET_REG16_ADDR(REG_ADDR_BASE_PM_SLEEP, 0x09) ++// #define REG_UART0_CLK GET_REG16_ADDR(REG_ADDR_BASE_CLKGEN, 0x31) ++ ++void uart_init(void) ++{ ++ U8 count=0; ++ ++#if 0 ++ // Enable uart0 clock ++ OUTREG8(REG_UART0_CLK, 0x09); //clk_xtal and gating ++ CLRREG8(REG_UART0_CLK, 0x01); //clear gating ++ ++ // Reset RX_enable ++ CLRREG16(REG_RX_ENABLE, BIT11); ++ ++ // Reset PM uart pad digmux ++ OUTREG16(REG_UART_SEL3210, 0x3210); ++#endif ++ ++ // Toggle SW reset ++ UART_REG8(UART_RST) &= ~0x01; ++ UART_REG8(UART_RST) |= 0x01; ++ ++ // Disable all interrupts ++ UART_REG8(UART_IER) = 0x00; ++ ++ // Set "reg_mcr_loopback"; ++ UART_REG8(UART_MCR) |= 0x10; ++ ++ // Poll "reg_usr_busy" till 0; (10 times) ++ while(UART_REG8(UART_USR) & 0x01 && count++ < 10) ++ ; ++ ++ if(count == 10) ++ { ++ // SetDebugFlag(FLAG_INIT_UART_BUSY); /* 0x0BF1 */ ++ } ++ else // Set divisor ++ { ++ U16 DLR = ((UART_CLK+(8*UART_BAUDRATE)) / (16 * UART_BAUDRATE)); ++ UART_REG8(UART_LCR) |= UART_LCR_DLAB; ++ UART_REG8(UART_DLL) = DLR & 0xFF; ++ UART_REG8(UART_DLM) = (DLR >> 8) & 0xFF; ++ UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB); ++ } ++ ++ // Set 8 bit char, 1 stop bit, no parity ++ UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY); ++ ++ // Unset loopback ++ UART_REG8(UART_MCR) &= ~0x10; ++ ++ // Enable TX/RX fifo ++ UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;; ++#if 0 ++ // Set PM uart pad digmux to UART0 ++ OUTREG16(REG_UART_SEL3210, 0x3012); ++ ++ // Set RX_enable ++ SETREG16(REG_RX_ENABLE, BIT11); ++#endif ++} ++#endif ++ ++ ++#if CONSOLE_DMA ++static void ms_uart_console_write(struct console *co, const char *str, u32 count) ++{ ++ struct ms_uart_port *mp; ++ struct uart_port *p; ++ unsigned long flags; ++ int locked = 1; ++#if SUPPORT_TX_LEVEL ++ unsigned int step_count; ++#endif ++ ++ if( (!str )|| co->index>=NR_CONSOLE_PORTS || co->index < 0) ++ { ++ return; ++ } ++ ++ mp = &console_port; ++ p = &(mp->port); ++ ++#if SUPPORT_TX_LEVEL ++ while(count) //shorten the time of interrupt closed by console log need verify ++ { ++ if(count < 16) ++ { ++ step_count = count; ++ count = 0; ++ } ++ else ++ { ++ step_count = 16; ++ count -= 16; ++ } ++ ++ if (p->sysrq || oops_in_progress) ++ locked = spin_trylock_irqsave(&p->lock, flags); ++ else ++ spin_lock_irqsave(&p->lock, flags); ++ ++ if(!mp->use_dma) ++ uart_console_write(p, str, step_count, ms_uart_console_putchar); ++ else if (mp->urdma) ++ { ++ uart_console_write(p, str, step_count, ms_uart_console_putchar_dma); ++ } ++ ++ if (locked) ++ spin_unlock_irqrestore(&p->lock, flags); ++ str += step_count; ++ } ++#else ++ if (p->sysrq || oops_in_progress) ++ locked = spin_trylock_irqsave(&p->lock, flags); ++ else ++ spin_lock_irqsave(&p->lock, flags); ++ ++ if(!mp->use_dma) ++ uart_console_write(p, str, count, ms_uart_console_putchar); ++ else if (mp->urdma) ++ { ++ uart_console_write(p, str, count, ms_uart_console_putchar_dma); ++ } ++ ++ if (locked) ++ spin_unlock_irqrestore(&p->lock, flags); ++#endif ++ return; ++} ++ ++static s32 __init ms_uart_console_setup(struct console *co, char *options) ++{ ++ /* Define Local Variables */ ++ s32 baud =115200; ++ s32 bits = 8; ++ s32 parity = 'n'; ++ s32 flow = 'n'; ++ ++ if(!options) ++ { ++ options = "115200n8r"; /* Set default baudrate for console*/ ++ } ++ ++ /* parsing the command line arguments */ ++ uart_parse_options(options, &baud, &parity, &bits, &flow); ++ _ms_uart_console_prepare(co->index); ++ if (co->index) ++ uart_init(); ++#if DEBUG_PAD_MUX ++ { ++ *((volatile int*)(0xFD203D4C)) &= 0xFFF0; ++ // *((volatile int*)(0xFD203D4C)) |= 0x0003; ++ *((volatile int*)(0xFD203D4C)) |= (u8SelectPad[co->index] & 0xF); ++ } ++#endif ++ ++ return uart_set_options(&(console_port.port), co, baud, parity, bits, flow); ++} ++#else // #if CONSOLE_DMA ++ ++static void ms_uart_console_write(struct console *co, const char *str, u32 count) ++{ ++ struct ms_uart_port *mp; ++ struct uart_port *p; ++ unsigned long flags; ++ int locked = 1; ++#if SUPPORT_TX_LEVEL ++ unsigned int step_count; ++#endif ++ ++ if( (!str )|| co->index>=NR_CONSOLE_PORTS || co->index < 0) ++ { ++ return; ++ } ++ ++ mp = console_ports[co->index]; ++ p = &(mp->port); ++ ++#if SUPPORT_TX_LEVEL ++ while(count) //shorten the time of interrupt closed by console log need verify ++ { ++ if(count < 16) ++ { ++ step_count = count; ++ count = 0; ++ } ++ else ++ { ++ step_count = 16; ++ count -= 16; ++ } ++ ++ if (p->sysrq || oops_in_progress) ++ locked = spin_trylock_irqsave(&p->lock, flags); ++ else ++ spin_lock_irqsave(&p->lock, flags); ++ ++ if(!mp->use_dma) ++ uart_console_write(p, str, step_count, ms_uart_console_putchar); ++ else if (mp->urdma) ++ { ++ uart_console_write(p, str, step_count, ms_uart_console_putchar_dma); ++ } ++ ++ if (locked) ++ spin_unlock_irqrestore(&p->lock, flags); ++ str += step_count; ++ } ++#else ++ if (p->sysrq || oops_in_progress) ++ locked = spin_trylock_irqsave(&p->lock, flags); ++ else ++ spin_lock_irqsave(&p->lock, flags); ++ ++ if(!mp->use_dma) ++ uart_console_write(p, str, count, ms_uart_console_putchar); ++ ++ if (locked) ++ spin_unlock_irqrestore(&p->lock, flags); ++#endif ++ return; ++} ++ ++static s32 __init ms_uart_console_setup(struct console *co, char *options) ++{ ++ /* Define Local Variables */ ++ s32 baud =115200; ++ s32 bits = 8; ++ s32 parity = 'n'; ++ s32 flow = 'n'; ++ ++ if(!options) ++ { ++ options = "115200n8r"; /* Set default baudrate for console*/ ++ } ++ ++ /* validate console port index */ ++ if(co->index == -1 || co->index >= NR_CONSOLE_PORTS) ++ { ++ co->index = 0; ++ } ++ /* parsing the command line arguments */ ++ uart_parse_options(options, &baud, &parity, &bits, &flow); ++ ++ if(console_ports[co->index]==NULL){ ++ return -ENODEV; ++ } ++ ++ return uart_set_options(&(console_ports[co->index]->port), co, baud, parity, bits, flow); ++} ++ ++static void ms_uart_add_console_port(struct ms_uart_port *ur) ++{ ++ if(ur->port.line < NR_CONSOLE_PORTS ) ++ { ++ console_ports[ur->port.line] = ur; ++ } ++} ++#endif // #if CONSOLE_DMA ++ ++static const char * ms_uart_type(struct uart_port *pPort_st) ++{ ++ return NULL; ++} ++ ++static void ms_uart_release_port(struct uart_port *pPort_st) ++{ ++ ++} ++ ++static s32 ms_uart_request_port(struct uart_port *pPort_st) ++{ ++ int ret=0; ++ return ret; ++} ++ ++static void ms_uart_config_port(struct uart_port *pPort_st, s32 flags) ++{ ++ ++} ++ ++static s32 ms_uart_verify_port(struct uart_port *pPort_st, struct serial_struct *ser) ++{ ++ int ret=0; ++ return ret; ++} ++ ++ ++static void ms_uart_enable_ms(struct uart_port *pPort_st) ++{ ++ ++} ++ ++static u32 ms_uart_get_mctrl(struct uart_port *pPort_st) ++{ ++ return (TIOCM_CAR|TIOCM_CTS|TIOCM_DSR); ++} ++ ++static void ms_uart_set_mctrl(struct uart_port *pPort_st, u32 mctrl) ++{ ++ ++} ++ ++ ++static void ms_uart_break_ctl(struct uart_port *pPort_st, s32 break_state) ++{ ++ ++} ++ ++ ++static void ms_uart_stop_tx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp = (struct ms_uart_port*)(p->dev->driver_data); ++ ++ if(!mp->use_dma) ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); //set PTHRI to enable tx_trigger lever ++ //NOTE: Read IIR to clear dummy THRI after disable THRI occurred at ZEBU -- Spade ++ INREG8(REG_IIR_FCR(p)); ++#endif ++ } ++ else ++ { ++// printk(KERN_ERR "DMA_TX_STOP\n"); ++ URDMA_TxSetupTimeoutInterrupt(p, FALSE); ++ } ++} ++ ++static void ms_uart_stop_rx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ if(!mp->use_dma) ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ CLRREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ CLRREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++#endif ++ } ++} ++ ++static void ms_uart_start_tx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ if(!mp->use_dma) ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); //set PTHRI to enable tx_trigger lever ++#endif ++ } ++ else ++ { ++// pr_err("DMA_TX_START\n"); ++ URDMA_TxSetupTimeoutInterrupt(p, TRUE); ++ URDMA_StartTx(p); ++ } ++} ++ ++static u32 ms_uart_tx_empty(struct uart_port *p) ++{ ++ int ret=0; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ if(!mp->use_dma) ++ { ++ /* Check if both TX FIFO buffer & shift register are empty */ ++ if((INREG8(REG_LSR(p)) & (UART_LSR_TEMT | UART_LSR_THRE)) == (UART_LSR_TEMT | UART_LSR_THRE)) ++ { ++ ret=TIOCSER_TEMT; /*if no support, also return this */ ++ } ++ ++ } ++ else ++ { ++ if(mp->urdma->reg_base->tx_buf_rptr == mp->urdma->reg_base->tx_buf_wptr) ++ { ++ return TIOCSER_TEMT; /*if no support, also return this */ ++ } ++ else ++ { ++ return 0; ++ } ++ } ++ ++ return ret; ++} ++ ++#if UART_TX_TASK ++static void ms_do_xmit_task(unsigned long port_address) ++{ ++ /* Define Local Variables */ ++ s32 count = 0; ++ struct circ_buf *xmit; ++ u8 u8USR = 0; ++ struct uart_port* p = (struct uart_port*) ((void *) port_address); ++ ++ /* Parameter out-of-bound check */ ++ if (!p) ++ { ++ // UART_ERR("ms_do_xmit_task: port is NULL\n"); ++ return; ++ } ++ ++ xmit = &p->state->xmit; ++ ++ if (p->x_char) ++ { ++ ++ while( !( INREG8(REG_LSR(p)) & UART_LSR_THRE ) ) ++ { ++ //nothing to do ++ } ++ ++ OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]); ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ p->icount.tx++; ++ p->x_char = 0; ++ return; ++ } ++ ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ return; ++ } ++ ++ u8USR = INREG8(REG_USR(p)); ++ if (UART_USR_TXFIFO_EMPTY == (u8USR & (UART_USR_TXFIFO_EMPTY))) // Tx FIFO Empty ++ { ++ count = p->fifosize; ++ } ++ else if (UART_USR_TXFIFO_NOT_FULL == (u8USR & (UART_USR_TXFIFO_NOT_FULL))) // not empty, but not full ++ { ++ count = 1; ++ } ++ ++ do { ++ OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]); ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ p->icount.tx++; ++ ++ if (uart_circ_empty(xmit)) ++ { ++ break; ++ } ++ } while (--count > 0); ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(p); ++ ++ if (uart_circ_empty(xmit)) ++ { ++ ms_uart_stop_tx(p); ++ return; ++ } ++ ++#if UART_USE_SPINLOCK ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++ } ++#else ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); ++#endif ++ return; ++} ++ ++#else // UART_TX_TASK = 0 ++static void ms_putchar(struct uart_port *p) ++{ ++ ++ /* Define Local Variables */ ++ int count; ++ struct circ_buf *xmit; ++ u8 u8USR = 0; ++ ++ /* Parameter out-of-bound check */ ++ if (!p) ++ { ++ // UART_ERR("ms_putchar: port is NULL\n"); ++ return; ++ } ++ ++ xmit = &p->state->xmit; ++ ++ if (p->x_char) ++ { ++ while( !( INREG8(REG_USR(p)) & UART_USR_TXFIFO_NOT_FULL ) ) ++ { ++ //nothing to do ++ } ++ OUTREG8(REG_DLL_THR_RBR(p), p->x_char); ++ p->icount.tx++; ++ p->x_char = 0; ++ return; ++ } ++ ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ return; ++ } ++ ++ u8USR = INREG8(REG_USR(p)); ++ ++ if (UART_USR_TXFIFO_EMPTY == (u8USR & (UART_USR_TXFIFO_EMPTY))) // Tx FIFO Empty ++ { ++ count = p->fifosize; ++ } ++ else if (UART_USR_TXFIFO_NOT_FULL == (u8USR & (UART_USR_TXFIFO_NOT_FULL))) // not empty, but not full ++ { ++ count = 1; ++ }else ++ { ++ count = 1; ++ } ++ ++ do { ++ OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]); ++ ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ p->icount.tx++; ++ ++ if (uart_circ_empty(xmit)) ++ { ++ break; ++ } ++ } while (--count > 0); ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(p); ++ ++ if (uart_circ_empty(xmit)) ++ { ++ ms_uart_stop_tx(p); ++ } ++} ++#endif ++ ++static int silent_state = 0; ++static void ms_getchar(struct uart_port *p) ++{ ++ u8 lsr = 0; /* Line Status Register (LSR) */ ++ u32 flag = 0; ++ u32 ch = 0; /* Character read from UART port */ ++ int max_count = p->fifosize; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ static u8 rx_disable = 0, pad_disable = 0; ++ unsigned long flags; ++ char isConsole = (console_port.port.line == mp->port.line) ? 1 : 0; ++ ++ spin_lock_irqsave(&p->lock, flags); ++ ++ /* Read Line Status Register */ ++ lsr = INREG8(REG_LSR(p)); ++ ++ /* check if Receiver Data Ready */ ++ if((lsr & UART_LSR_DR) != UART_LSR_DR) ++ { ++ mp->rx_guard++; ++ if(unlikely(mp->rx_guard>2000)) ++ { ++ ch=INREG8(REG_DLL_THR_RBR(p)); ++ UART_ERR("rx interrupts error!!!!!"); ++ mp->rx_guard=0; ++ } ++ /* Data NOT Ready */ ++ spin_unlock_irqrestore(&p->lock, flags); ++ return ; ++ } ++ mp->rx_guard=0; ++ ++ /* while data ready, start to read data from UART FIFO */ ++ do{ ++ flag = TTY_NORMAL; ++ /* read data from UART IP */ ++ ch = INREG8(REG_DLL_THR_RBR(p)); ++ p->icount.rx++; ++ ++ if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | UART_LSR_FE | UART_LSR_OE))) ++ { ++ if (lsr & UART_LSR_BI) { ++ lsr &= ~(UART_LSR_FE | UART_LSR_PE); ++ p->icount.brk++; ++ /* ++ * We do the SysRQ and SAK checking ++ * here because otherwise the break ++ * may get masked by ignore_status_mask ++ * or read_status_mask. ++ */ ++ if (uart_handle_break(p)) ++ goto IGNORE_CHAR; ++ } ++ else if (lsr & UART_LSR_PE) ++ { ++ p->icount.parity++; ++ } ++ else if (lsr & UART_LSR_FE) ++ { ++ p->icount.frame++; ++ } ++ else if (lsr & UART_LSR_OE) ++ { ++ p->icount.overrun++; ++ } ++ ++ /* ++ * Mask off conditions which should be ingored. ++ */ ++ lsr &= p->read_status_mask; ++ ++ if (lsr & UART_LSR_BI) { ++ UART_DBG("handling break....\n"); ++ flag = TTY_BREAK; ++ } ++ else if (lsr & UART_LSR_PE) ++ { ++ flag = TTY_PARITY; ++ } ++ else if (lsr & UART_LSR_FE) ++ { ++ flag = TTY_FRAME; ++ } ++ } ++ if (silent_state==0) ++ { ++ #ifdef SUPPORT_SYSRQ ++ if (uart_handle_sysrq_char(p, ch)) ++ { ++ goto IGNORE_CHAR; ++ } ++ #endif ++ uart_insert_char(p, lsr, UART_LSR_OE, ch, flag); ++ } ++ if (isConsole) ++ { ++ //when receive '11111', disable UART RX to use TV tool ++ if(ch == '1') ++ rx_disable++; ++ else ++ rx_disable=0; ++ ++ if(rx_disable == 5) ++ { ++ silent_state = 1 - silent_state; ++ ++ if (silent_state) ++ { ++ printk("disable uart\n"); ++ ch = 0; ++ } ++ else ++ { ++ printk("enable uart\n"); ++ } ++ ++ //CLRREG16(0x1F001C24, 0x1<<11); ++ rx_disable=0; ++ } ++ //when receive '22222', disable UART PAD to use TV tool ++ if(ch == '2') ++ pad_disable++; ++ else ++ pad_disable=0; ++ ++ if(pad_disable == 5) ++ { ++#if defined(CONFIG_ARCH_INFINITY2) ++ CLRREG16(0x1F001C24, 0x1<<11); ++#else ++ CLRREG16(0x1F203D4C, 0x000F); ++#endif ++ pad_disable=0; ++ } ++ } ++ ++IGNORE_CHAR: ++ lsr = INREG8(REG_LSR(p)); ++ }while((max_count-- >0)&&(lsr & UART_LSR_DR)); ++ ++ spin_unlock_irqrestore(&p->lock, flags); ++ tty_flip_buffer_push(&p->state->port); ++} ++ ++static irqreturn_t ms_uart_interrupt(s32 irq, void *dev_id) ++{ ++ /* Define Local Variables */ ++ u8 iir_fcr = 0; /* Interrupt Identification Register (IIR) */ ++ struct uart_port *p = dev_id; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ u8 count=0, retry=100; ++ local_fiq_disable(); ++ if(mp->use_dma) ++ { ++ u8 status = URDMA_GetInterruptStatus(p); ++ if(status & URDMA_INTR_STATUS_RX) ++ { ++ u8 intr_type = URDMA_RxGetInterrupt(p); ++ ++ if(intr_type & URDMA_RX_INTR_TYPE_TIMEOUT) ++ { ++ URDMA_RxSetupTimeoutInterrupt(p,FALSE); ++ } ++ ++ if(intr_type & URDMA_RX_INTR_TYPE_THRESHOLD) ++ { ++ URDMA_RxSetupThresholdInterrupt(p,FALSE); ++ } ++ URDMA_RxClearInterrupt(p); ++ ++ URDMA_StartRx(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ } ++ else if(status & URDMA_INTR_STATUS_TX) ++ { ++#if CONSOLE_DMA ++ URDMA_TxClearInterrupt(p); ++ urdma_conditions = 1; ++ wake_up_interruptible(&urdma_wait); ++#else ++ URDMA_TxClearInterrupt(p); ++ //do nothing ++#endif ++ } ++ else ++ UART_ERR("URDMA dummy interrupt!\n"); ++ } ++ else ++ { ++ /* Read Interrupt Identification Register */ ++ iir_fcr = INREG8(REG_IIR_FCR(p)) & UART_IIR_ID_MASK; ++ ++ if( (iir_fcr == UART_IIR_RDI || iir_fcr == UART_IIR_RX_TIMEOUT || iir_fcr == UART_IIR_RLSI) ) /* Receive Data Available or Character timeout or Receiver line status */ ++ { ++ ms_getchar(p); ++ } ++ else if( iir_fcr == UART_IIR_THRI ) /* Transmitter Holding Register Empty */ ++ { ++ #if UART_TX_TASK ++ #if UART_USE_SPINLOCK ++ unsigned long flags=0; ++ spin_lock_irqsave(&p->lock, flags); ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++ #else ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI | UART_IER_PTHRI); ++ #endif ++ ++ tasklet_schedule(&mp->xmit_tasklet); ++ #else ++ ++ if (silent_state==0) ++ ms_putchar(p); ++ #endif ++ } ++ else if( iir_fcr == UART_IIR_MSI ) /* Modem Status */ ++ { ++ // UART_ERR("UART Interrupt: Modem status\n"); ++ // Read MSR to clear ++ INREG8(REG_MSR(p)); ++ } ++ else if( iir_fcr == UART_IIR_BUSY ) /* Busy detect indication */ ++ { ++ // Read USR to clear ++ INREG8(REG_USR(p)); ++ ++ while( ((INREG8(REG_IIR_FCR(p)) & UART_IIR_ID_MASK) == UART_IIR_BUSY) && (count < retry)) ++ { ++ // Read USR to clear ++ INREG8(REG_USR(p)); ++ count++; ++ } ++ if (count == retry) ++ UART_ERR("UART Interrupt: UART_IIR_BUSY\n"); ++ ++ } ++// else if( iir_fcr == UART_IIR_RLSI ) /* Receiver line status */ ++// { ++// // Read LSR to clear //for recognize break signal ++// INREG8(REG_LSR(p)); ++// } ++ else if( iir_fcr == UART_IIR_NO_INT ) /* No pending interrupts */ ++ { ++ while( ((INREG8(REG_USR(p)) & UART_USR_BUSY) == UART_USR_BUSY) && (count < retry)) ++ { ++ count++; ++ } ++// if (count == retry) ++// UART_ERR("UART%d Interrupt: No IRQ rasied by UART, but come in to UART ISR. IIR:0x%02X USR:0x%02X\n", p->line, iir_fcr, INREG8(REG_USR(p))); ++ } ++ else /* Unknown Status */ ++ { ++ UART_ERR("UART Unknown Interrupt, IIR:0x%02X\n", iir_fcr); ++ } ++ } ++ local_fiq_enable(); ++ return IRQ_HANDLED; ++} ++ ++u32 gu32_console_bug_thre_hits = 0; ++module_param(gu32_console_bug_thre_hits, uint, S_IRUGO); ++ ++static void serial8250_backup_timeout(unsigned long data) ++{ ++ struct ms_uart_port *up = (struct ms_uart_port *)data; ++ u16 iir, ier = 0, lsr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&up->port.lock, flags); ++ ++ iir = INREG8(REG_IIR_FCR((&up->port))); ++ ier = INREG8(REG_DLH_IER((&up->port))); ++ ++ /* ++ * This should be a safe test for anyone who doesn't trust the ++ * IIR bits on their UART, but it's specifically designed for ++ * the "Diva" UART used on the management processor on many HP ++ * ia64 and parisc boxes. ++ */ ++ lsr = INREG8(REG_LSR((&up->port)));; ++ if ((iir & UART_IIR_NO_INT) && (ier & UART_IER_THRI) && ++ (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && ++ (lsr & UART_LSR_THRE)) { ++ CLRREG8(REG_DLH_IER((&up->port)), UART_IER_THRI | UART_IER_PTHRI); ++ SETREG8(REG_DLH_IER((&up->port)), UART_IER_THRI | UART_IER_PTHRI); ++ gu32_console_bug_thre_hits++; ++ ms_putchar((&up->port)); ++ } ++ ++ spin_unlock_irqrestore(&up->port.lock, flags); ++ ++ /* Standard timer interval plus 0.2s to keep the port running */ ++ mod_timer(&up->timer, ++ jiffies + uart_poll_timeout(&up->port) + HZ / 5); ++} ++ ++static s32 ms_uart_startup(struct uart_port *p) ++{ ++ /* Define Local Variables */ ++ int rc = 0; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ ms_uart_clear_fifos(p); ++ ++ /*we do not support CTS now*/ ++ p->flags &= ~ASYNC_CTS_FLOW; ++ ++#if UART_TX_TASK ++ tasklet_init(&mp->xmit_tasklet, ms_do_xmit_task, (unsigned long)p); ++#endif ++ ++ if(mp->use_dma) ++ { ++ rc = request_irq(mp->urdma->urdma_irq, ms_uart_interrupt, IRQF_SHARED, "ms_serial_dma",p); ++ } ++ else ++ { ++ OUTREG8(REG_DLH_IER(p), 0); ++ INREG8(REG_LSR(p)); ++ INREG8(REG_DLL_THR_RBR(p)); ++ INREG8(REG_IIR_FCR(p)); ++ INREG8(REG_MSR(p)); ++ rc = request_irq(p->irq, ms_uart_interrupt, IRQF_SHARED, "ms_serial", p); ++ } ++ ++ /* Print UART interrupt request status */ ++ if (rc) { ++ /* UART interrupt request failed */ ++ //UART_ERR("ms_startup(): UART%d request_irq()is failed. return code=%d\n", p->line, rc); ++ } else { ++ /* UART interrupt request passed */ ++ //UART_ERR("ms_startup(): UART%d request_irq() is passed.\n", p->line); ++ } ++ ++ mp->rx_guard=0; ++ ++ ++ if(mp->use_dma) ++ { ++#if CONSOLE_DMA ++ unsigned char bConsole = (mp->port.membase == console_port.port.membase) ? 1 : 0; ++ ++ if (bConsole) ++ { ++ console_lock(); ++ } ++#endif ++ URDMA_Reset(p); ++ URDMA_Activate(p,TRUE); ++ URDMA_TxInit(p); ++ URDMA_TxEnable(p,TRUE); ++ URDMA_RxInit(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ URDMA_RxEnable(p,TRUE); ++#if CONSOLE_DMA ++ if (bConsole) ++ { ++ console_port.use_dma = 1; ++ console_unlock(); ++ } ++#endif ++ } ++ else ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ SETREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ SETREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++#endif ++ } ++ ++ ms_force_rx_disable(mp->padmux, ENABLE); ++#ifndef CONFIG_MS_SUPPORT_EXT_PADMUX ++ ms_select_pad(p, mp->padmux, mp->pad_mode); ++#endif ++#if MS_UART_8250_BUG_THRE ++ mp->bugs = UART_BUG_THRE; ++#endif ++ /* ++ * [PATCH] from drivers/tty/serial/8250/8250_core.c ++ * The above check will only give an accurate result the first time ++ * the port is opened so this value needs to be preserved. ++ */ ++ if (mp->bugs & UART_BUG_THRE) { ++ UART_ERR("ms_startup(): enable UART_BUG_THRE\n"); ++ init_timer(&mp->timer); ++ mp->timer.function = serial8250_backup_timeout; ++ mp->timer.data = (unsigned long)mp; ++ mod_timer(&mp->timer, jiffies + ++ uart_poll_timeout(&mp->port) + HZ / 5); ++ } ++ return rc; ++} ++ ++ ++static void ms_uart_shutdown(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ ++ if(mp->use_dma) ++ { ++ URDMA_RxEnable(p,FALSE); ++ URDMA_TxEnable(p,FALSE); ++ URDMA_TxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_TxClearInterrupt(p); ++ URDMA_RxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_RxSetupThresholdInterrupt(p,FALSE); ++ URDMA_RxClearInterrupt(p); ++ URDMA_Activate(p,FALSE); ++ disable_irq(mp->urdma->urdma_irq); ++ free_irq(mp->urdma->urdma_irq, p); ++ } ++ else ++ { ++#if UART_USE_LOOPBACK ++ //set loopback mode ++ SETREG8(REG_MCR(p), 0x10); ++#endif ++ CLRREG8(REG_LCR(p), UART_LCR_SBC); ++ ms_uart_clear_fifos(p); ++ INREG8(REG_DLL_THR_RBR(p)); ++ ++#if UART_USE_LOOPBACK ++ //clear loopback mode ++ CLRREG8(REG_MCR(p), 0x10); ++#endif ++ //OUTREG8(REG_DLH_IER(p), 0); ++ disable_irq(p->irq); ++ free_irq(p->irq, p); ++ } ++ ++ if (mp->bugs & UART_BUG_THRE) { ++ del_timer_sync(&mp->timer); ++ } ++} ++ ++static void ms_uart_set_termios(struct uart_port *p, struct ktermios *pTermios_st, struct ktermios *pOld_st) ++{ ++ /* Define Local Variables */ ++ struct ms_uart_port *mp = NULL; ++ u8 uartflag = 0; ++ u16 divisor = 0; ++ u32 baudrate = 0; ++ u32 sctp_enable = 0; ++ ++ //OUTREG8(REG_DLH_IER(p), 0); ++ ++ if(p->dev) ++ { ++ mp=(struct ms_uart_port*)p->dev->driver_data; ++ if(mp->use_dma) ++ URDMA_Activate(p,FALSE); ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ } ++ ++ /*------- Configure Chararacter Size --------*/ ++ switch (pTermios_st->c_cflag & CSIZE) ++ { ++ case CS5: /* Word length is 5 bits */ ++ uartflag |= UART_LCR_WLEN5; ++ break; ++ case CS6: /* Word length is 6 bits */ ++ uartflag |= UART_LCR_WLEN6; ++ break; ++ case CS7: /* Word length is 7 bits */ ++ uartflag |= UART_LCR_WLEN7; ++ break; ++ case CS8: /* Word length is 8 bits */ ++ uartflag |= UART_LCR_WLEN8; ++ break; ++ default: ++ UART_ERR("%s unsupported bits:%d\n", __FUNCTION__, pTermios_st->c_cflag & CSIZE); ++ break; ++ } ++ ++ /*------------ Configure Stop bit -----------*/ ++ if (pTermios_st->c_cflag & CSTOPB) ++ { ++ /* Stop length is 1.5 bits (5-bit char), 2 bits (otherwise) */ ++ uartflag |= UART_LCR_STOP2; ++ } ++ else ++ { ++ /* Stop length is 1 bit */ ++ uartflag |= UART_LCR_STOP1; ++ } ++ ++ /*----------- Configure Parity --------------*/ ++ if (pTermios_st->c_cflag & PARENB) ++ { ++ /* Parity Enable */ ++ uartflag |= UART_LCR_PARITY_EN; ++ ++ /* Set Odd/Even Parity */ ++ if (pTermios_st->c_cflag & PARODD) ++ { ++ /* Odd Parity */ ++ uartflag &= (~UART_LCR_PARITY_SEL); ++ } ++ else ++ { ++ /* Even Parity */ ++ uartflag |= UART_LCR_PARITY_SEL; ++ } ++ } ++ else ++ { ++ /* Parity Disable */ ++ uartflag &= (~UART_LCR_PARITY_EN); ++ } ++ if(INREG8(REG_LCR(p)) != uartflag) ++ { ++ ms_uart_clear_fifos(p); ++ OUTREG8(REG_LCR(p), uartflag); ++ } ++ ++ //NOTE: we are going to set LCR, be carefully here ++ if (!pOld_st || (tty_termios_baud_rate(pOld_st) != tty_termios_baud_rate(pTermios_st))) { ++ baudrate = uart_get_baud_rate(p, pTermios_st, pOld_st, 0, 115200 * 14); ++ divisor = ms_uart_set_clk(p, baudrate); ++ if(divisor) { ++ ms_uart_set_divisor(p, divisor); ++ } ++ } ++ ++ OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_TRIGGER_TX_L1 | UART_FCR_TRIGGER_RX_L0); ++ INREG8(REG_DLL_THR_RBR(p)); ++ ++ if(p->dev != NULL){ ++ of_property_read_u32(p->dev->of_node, "sctp_enable", &sctp_enable); ++ if(sctp_enable == 1) ++ { ++ if(pTermios_st->c_cflag & CRTSCTS) ++ { ++ //rts cts enable ++ OUTREG8(REG_MCR(p), UART_MCR_AFCE | UART_MCR_RTS); ++ OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_TRIGGER_TX_L0 | UART_FCR_TRIGGER_RX_L3); ++ } ++ else ++ { ++ //rts cts disable ++ OUTREG8(REG_MCR(p), INREG8(REG_MCR(p)) & ~ (UART_LCR_DLAB| UART_MCR_RTS ) ); ++ } ++ } ++ } ++ ++ if(p->dev) ++ { ++ if(mp->use_dma) ++ { ++ URDMA_Reset(p); ++ URDMA_Activate(p,TRUE); ++ URDMA_TxInit(p); ++ URDMA_TxEnable(p,TRUE); ++ URDMA_RxInit(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ URDMA_RxEnable(p,TRUE); ++ } ++ ms_force_rx_disable(mp->padmux, ENABLE); ++ } ++} ++ ++#ifdef CONFIG_PM ++static s32 ms_uart_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct ms_uart_port *mp=platform_get_drvdata(pdev); ++ struct uart_port *p=&mp->port; ++ ++ UART_DBG("[%s] uart%d\n", __func__, p->line); ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ ++ if(mp->use_dma) ++ { ++ URDMA_RxEnable(p,FALSE); ++ URDMA_TxEnable(p,FALSE); ++ URDMA_TxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_TxClearInterrupt(p); ++ URDMA_RxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_RxSetupThresholdInterrupt(p,FALSE); ++ URDMA_RxClearInterrupt(p); ++ URDMA_Activate(p,FALSE); ++ } ++ ++ uart_suspend_port(&ms_uart_driver, p); ++ ++ mp->backupIER = INREG8(REG_DLH_IER(p)); ++ mp->backupLCR = INREG8(REG_LCR(p)); ++ mp->backupMCR = INREG8(REG_MCR(p)); ++ ++ OUTREG8(REG_DLH_IER(p), 0); ++ ms_uart_clear_fifos(p); ++ ++ OUTREG8(REG_LCR(p) , mp->backupLCR | UART_LCR_DLAB); ++ ++ mp->backupDivisor = (INREG8(REG_DLH_IER(p)) << 8); ++ mp->backupDivisor |= (INREG8(REG_DLL_THR_RBR(p)) & 0xFF); ++ ++#ifndef CONFIG_CAM_CLK ++ if (!IS_ERR(mp->clk)) ++ { ++ clk_disable_unprepare(mp->clk); ++#if 0 ++ clk_put(mp->clk); ++#endif ++ } ++#else ++ if(mp->pvclk) ++ { ++ CamClkSetOnOff(mp->pvclk,0); ++ } ++#endif ++ return 0; ++} ++ ++static s32 ms_uart_resume(struct platform_device *pdev) ++{ ++ struct ms_uart_port *mp=platform_get_drvdata(pdev); ++ struct uart_port *p=&mp->port; ++#ifndef CONFIG_CAM_CLK ++ if (!IS_ERR(mp->clk)) ++ clk_prepare_enable(mp->clk); ++#else ++ if(mp->pvclk) ++ { ++ CamClkSetOnOff(mp->pvclk,1); ++ } ++#endif ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ ++ ms_uart_set_divisor(p, mp->backupDivisor); ++ ++ OUTREG8(REG_MCR(p), mp->backupMCR); ++ OUTREG8(REG_LCR(p), mp->backupLCR); ++ OUTREG8(REG_DLH_IER(p), mp->backupIER); ++ ++ uart_resume_port(&ms_uart_driver, &mp->port); ++ ++ ms_force_rx_disable(mp->padmux, ENABLE); ++ UART_DBG("[%s] uart%d\n", __func__, p->line); ++ ++ return 0; ++} ++#endif ++ ++static s32 ms_uart_remove(struct platform_device *pdev) ++{ ++ struct ms_uart_port *mp=platform_get_drvdata(pdev); ++ ++ uart_remove_one_port(&ms_uart_driver,&mp->port); ++ ++ if(mp->use_dma) ++ { ++ dma_free_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH), &mp->urdma->rx_urdma_base, GFP_KERNEL); ++ dma_free_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH), &mp->urdma->tx_urdma_base, GFP_KERNEL); ++ kthread_stop(mp->urdma_task); ++ } ++#ifndef CONFIG_CAM_CLK ++ if (!IS_ERR(mp->clk)) ++ { ++ clk_disable_unprepare(mp->clk); ++ clk_put(mp->clk); ++ } ++#else ++ if(mp->pvclk) ++ { ++ CamClkSetOnOff(mp->pvclk,0); ++ CamClkUnregister(mp->pvclk); ++ mp->pvclk = NULL; ++ } ++#endif ++ ++ ++ return 0; ++} ++ ++static s32 ms_uart_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct ms_uart_port *mp; ++ struct ms_urdma *urdma; ++ struct resource *res; ++ int tx_pad; ++#ifdef CONFIG_CAM_CLK ++ int UartClk; ++#endif ++ if(!pdev) ++ { ++ // UART_ERR("ms_uart_probe() parameter pdev is NULL\n"); ++ return -ENOMEM; ++ } ++ mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL); ++ if (!mp) ++ return -ENOMEM; ++ ++ spin_lock_init(&mp->port.lock); ++ ++ mp->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); ++ /*if (mp->port.line < 0) { ++ UART_ERR("[%s] failed to get alias/pdev id = %d\n", __func__, mp->port.line); ++ return -EINVAL; ++ }*/ ++ pdev->id=mp->port.line; ++#ifndef CONFIG_CAM_CLK ++ mp->clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(mp->clk)) ++ { ++ //UART_ERR("[%s] of_clk_get failed\n", __func__); ++ return -EINVAL; ++ } ++ //enable clk in probe, because if UART no clk, it can not be accessed. ++ clk_prepare_enable(mp->clk); ++ mp->port.uartclk = clk_get_rate(mp->clk); ++#else ++ UartClk = 0; ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", 0,&UartClk); ++ if (!UartClk) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ ret = -ENOENT; ++ } ++ else ++ { ++ CamClkRegister((u8 *)pdev->name,UartClk,&mp->pvclk); ++ CamClkSetOnOff(mp->pvclk,1); ++ CamClkAttrGet(mp->pvclk,&mp->stCfg); ++ mp->port.uartclk = mp->stCfg.u32Rate; ++ } ++#endif ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ // UART_ERR("no memory resource defined\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ mp->port.membase = (void *)res->start; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (res == NULL) { ++ // UART_ERR("no irq resource defined\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ mp->port.irq = res->start; ++ ++ of_property_read_u32(pdev->dev.of_node, "dma", &mp->use_dma); ++ ++ if (mp->use_dma) ++ { ++#if CONSOLE_DMA ++ unsigned char bConsole = (mp->port.membase == console_port.port.membase) ? 1 : 0; ++ if (bConsole) ++ { ++ console_lock(); ++ } ++#endif ++ mp->urdma = devm_kzalloc(&pdev->dev, sizeof(*urdma), GFP_KERNEL); ++ if (!mp->urdma) ++ { ++ mp->use_dma=0; ++ goto dma_err; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (res == NULL) ++ { ++ mp->use_dma = 0; ++ // UART_ERR("no urdma memory resource defined...\n"); ++ goto dma_err; ++ } ++ mp->urdma->reg_base = (reg_urdma *)IO_ADDRESS(res->start); ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); ++ if (res == NULL) ++ { ++ mp->use_dma = 0; ++ // UART_ERR("no urdma irq resource defined\n"); ++ goto dma_err; ++ } ++ mp->urdma->urdma_irq = res->start; ++ mp->port.irq = res->start; ++ ++ mp->urdma->rx_buf = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH), ++ &mp->urdma->rx_urdma_base, GFP_KERNEL); ++ mp->urdma->tx_buf = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH), ++ &mp->urdma->tx_urdma_base, GFP_KERNEL); ++ if(!mp->urdma->rx_buf || !mp->urdma->tx_buf) ++ { ++ mp->use_dma = 0; ++ // UART_ERR("Allocate urdma rx_buffer/tx_buffer failed, use UART mode\n"); ++ goto dma_err; ++ } ++ mp->urdma->rx_urdma_size = PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH); ++ mp->urdma->tx_urdma_size = PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH); ++ UART_DBG("[%s] URDMA mode enable, reg_base=0x%08X, irq=%d\n", __func__, (unsigned int)(mp->urdma->reg_base), mp->urdma->urdma_irq); ++ // UART_ERR("URDMA rx_buf=0x%08X(phy:0x%08X) tx_buf=0x%08X(phy:0x%08X) size=0x%X\n", (unsigned int)mp->urdma->rx_buf, (unsigned int)mp->urdma->rx_urdma_base, (unsigned int)mp->urdma->tx_buf, (unsigned int)mp->urdma->tx_urdma_base, mp->urdma->rx_urdma_size); ++#if CONSOLE_DMA ++dma_err: ++ if (bConsole) ++ { ++ // console_port.use_dma = mp->use_dma; ++ if ((!mp->use_dma) && (mp->urdma)) ++ { ++ devm_kfree(&pdev->dev, mp->urdma); ++ mp->urdma = NULL; ++ } ++ console_port.urdma= mp->urdma; ++ console_unlock(); ++ } ++#endif ++ mp->urdma_task = kthread_run(urdma_tx_thread,(void *)&mp->port,"urdma_tx_thread"); ++ } ++#if !CONSOLE_DMA ++dma_err: ++#endif ++ mp->port.type = PORT_8250; ++ mp->port.dev = &pdev->dev; ++ mp->port.ops=&ms_uart_ops; ++ mp->port.regshift = 0; ++ mp->port.fifosize = 32; //HW FIFO is 32Bytes ++ mp->port.timeout =HZ; ++ mp->port.iotype=UPIO_MEM; ++ ++ UART_DBG("[%s] line=%d name=%s\n", __func__, mp->port.line, pdev->name); ++ ++ ++ //[2016.11.15] Add padmux select from DTB by Spade ++ if(of_property_read_u32(pdev->dev.of_node, "pad", &tx_pad)) //read property failed ++ { ++ //set default pad ++ if(mp->port.line==0) ++ { ++ // improve boot-up speed, remove print log ++ UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_PM_UART"); ++ //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_PM_UART"); ++ mp->padmux=MUX_PM_UART; ++ } ++ else if(mp->port.line==1) ++ { ++ // improve boot-up speed, remove print log ++ UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART1"); ++ //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART1"); ++ mp->padmux=MUX_UART1; ++ } ++ else if(mp->port.line==2) ++ { ++ // improve boot-up speed, remove print log ++ UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_FUART"); ++ //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_FUART"); ++ mp->padmux=MUX_FUART; ++ } ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ else if(mp->port.line==3) ++ { ++ // improve boot-up speed, remove print log ++ UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART2"); ++ //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART2"); ++ mp->padmux=MUX_UART2; ++ } ++#endif ++ else ++ { ++ // improve boot-up speed, remove print log ++ UART_DBG("[%s] port line %d is not supported\n", __func__, mp->port.line); ++ //UART_ERR("[%s] port line %d is not supported\n", __func__, mp->port.line); ++ ret = -EINVAL; ++ goto out; ++ } ++ } ++ else //read property successfully ++ { ++ if (ms_uart_get_padmux(tx_pad, &(mp->padmux), &(mp->pad_mode)) != 0) ++ { ++ // UART_ERR("[%s] Use undefined pad number %d\n", __func__, tx_pad); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ // improve boot-up speed, remove print log ++#ifdef CONFIG_MS_SUPPORT_UART2 ++ UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":(mp->padmux==MUX_UART1)?"MUX_UART1":"MUX_UART2"); ++ //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":(mp->padmux==MUX_UART1)?"MUX_UART1":"MUX_UART2"); ++#else ++ UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":"MUX_UART1"); ++ //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":"MUX_UART1"); ++#endif ++ } ++ ++ platform_set_drvdata(pdev, mp); ++ ++ ret = uart_add_one_port(&ms_uart_driver, &mp->port); ++ if (ret != 0) ++ goto out; ++ ++ return 0; ++out: ++ // UART_ERR("[UART%d]: failure [%s]: %d\n", mp->port.line, __func__, ret); ++#ifndef CONFIG_CAM_CLK ++ clk_disable_unprepare(mp->clk); ++ clk_put(mp->clk); ++#else ++ CamClkSetOnOff(mp->pvclk,0); ++ CamClkUnregister(mp->pvclk); ++ mp->pvclk = NULL; ++#endif ++ return ret; ++} ++ ++static const struct of_device_id ms_uart_of_match_table[] = { ++ { .compatible = "sstar,uart" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_uart_of_match_table); ++ ++static struct platform_driver ms_uart_platform_driver = { ++ .remove = ms_uart_remove, ++ .probe = ms_uart_probe, ++#ifdef CONFIG_PM ++ .suspend = ms_uart_suspend, ++ .resume = ms_uart_resume, ++#endif ++ .driver = { ++ .name = "ms_uart", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_uart_of_match_table), ++ }, ++}; ++ ++static s32 __init ms_uart_module_init(void) ++{ ++ int ret; ++ ++ ret = uart_register_driver(&ms_uart_driver); ++ if (ret != 0) ++ return ret; ++ ret = platform_driver_register(&ms_uart_platform_driver); ++ if (ret != 0) ++ { ++ // UART_ERR("[ms_uart]platform_driver_register failed!!\n"); ++ uart_unregister_driver(&ms_uart_driver); ++ } ++ return ret; ++} ++ ++ ++static void __exit ms_uart_module_exit(void) ++{ ++ platform_driver_unregister(&ms_uart_platform_driver); ++ uart_unregister_driver(&ms_uart_driver); ++} ++ ++module_init(ms_uart_module_init); ++module_exit(ms_uart_module_exit); ++ ++ ++static int __init ms_early_console_init(void) ++{ ++#if !CONSOLE_DMA ++ struct device_node *console_np; ++ struct resource res; ++ ++ console_np=of_find_node_by_path("console"); ++ if(!console_np) ++ return -ENODEV; ++ ++ ++ BUG_ON( of_address_to_resource(console_np,0,&res) ); ++ ++ console_port.port.membase = (void *)res.start; ++ ++ console_port.port.type = PORT_8250; ++ ++ console_port.port.ops=&ms_uart_ops; ++ console_port.port.regshift = 0; ++ console_port.port.fifosize = 32; //HW FIFO is 32Bytes ++ console_port.port.line=0; ++ console_port.port.cons=&ms_uart_console; ++ ms_uart_add_console_port(&console_port); ++#endif ++ register_console(&ms_uart_console); ++ return 0; ++} ++ ++console_initcall(ms_early_console_init); ++ ++void URDMA_Reset(struct uart_port *p) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->urdma_mode=1; ++ ++ mp->urdma->reg_base->tx_urdma_en = 0; ++ mp->urdma->reg_base->rx_urdma_en = 0; ++ ++ mp->urdma->reg_base->tx_intr_en = 0; ++ mp->urdma->reg_base->rx_intr1_en = 0; ++ mp->urdma->reg_base->rx_intr2_en = 0; ++ ++ /* clear interrupt status */ ++ mp->urdma->reg_base->tx_intr_clr = 1; ++ mp->urdma->reg_base->rx_intr_clr = 1; ++ ++ ++ /* software reset */ ++ mp->urdma->reg_base->sw_rst = 1; ++ ++ /* make sure rx_busy is off */ ++ for(i=0; (mp->urdma->reg_base->rx_busy || mp->urdma->reg_base->tx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ break; ++ } ++ } ++ ++#if !CONSOLE_DMA ++ mdelay(10); ++#endif ++ mp->urdma->reg_base->sw_rst = 0; ++ ++ mp->urdma->reg_base->urdma_mode=0; ++} ++ ++void URDMA_Activate(struct uart_port *p,BOOL bEnable) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->urdma_mode=bEnable?TRUE:FALSE; ++ UART_DBG("URDMA_Activate: %d\n", bEnable); ++ ++} ++ ++void URDMA_TxEnable(struct uart_port *p,BOOL bEnable) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(bEnable) ++ { ++ mp->urdma->reg_base->tx_urdma_en = 1; ++ } ++ else ++ { ++ mp->urdma->reg_base->tx_urdma_en = 0; ++ for(i=0; (mp->urdma->reg_base->tx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ } ++} ++ ++void URDMA_RxEnable(struct uart_port *p,BOOL bEnable) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(bEnable) ++ { ++ mp->urdma->reg_base->rx_urdma_en = 1; ++ } ++ else ++ { ++ mp->urdma->reg_base->rx_urdma_en = 0; ++ for(i=0; (mp->urdma->reg_base->rx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ } ++} ++ ++U8 URDMA_GetInterruptStatus(struct uart_port *p) ++{ ++ U8 stat=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(mp->urdma->reg_base->rx_mcu_intr) ++ { ++ stat|=URDMA_INTR_STATUS_RX; ++ } ++ ++ if(mp->urdma->reg_base->tx_mcu_intr) ++ { ++ stat|=URDMA_INTR_STATUS_TX; ++ } ++ ++ return stat; ++} ++ ++void URDMA_TxInit(struct uart_port *p) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->tx_urdma_en = 0; /* disable dma */ ++ mp->urdma->reg_base->tx_sw_rst = 1; ++ for(i=0; (mp->urdma->reg_base->tx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ ++ mp->urdma->reg_base->tx_sw_rst = 0; ++ mp->urdma->reg_base->tx_buf_base_h = URDMA_HIU16((U32)mp->urdma->tx_urdma_base); ++ mp->urdma->reg_base->tx_buf_base_l = URDMA_LOU16((U32)mp->urdma->tx_urdma_base); ++ mp->urdma->reg_base->tx_buf_size = (mp->urdma->tx_urdma_size/8); ++ mp->urdma->reg_base->tx_timeout = URDMA_TX_TIMEOUT; ++ mp->urdma->reg_base->tx_buf_wptr = 0x0; ++ ++ //2015.10.21 Refine: initialize tx_buf_wptr to 1 because HW behavior is not correct from 0 to 1 ++ //2016.11.27 Refine: remove initial value for tx_buf_wptr ++ //mp->urdma->reg_base->tx_buf_wptr = 0x1; ++} ++ ++void URDMA_RxInit(struct uart_port *p) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_urdma_en = 0; /* disable dma */ ++ mp->urdma->reg_base->rx_sw_rst = 1; ++ for(i=0; (mp->urdma->reg_base->rx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ ++ mp->urdma->reg_base->rx_sw_rst=0; ++ mp->urdma->reg_base->rx_buf_base_h = URDMA_HIU16((U32)mp->urdma->rx_urdma_base); ++ mp->urdma->reg_base->rx_buf_base_l = URDMA_LOU16((U32)mp->urdma->rx_urdma_base); ++ mp->urdma->reg_base->rx_buf_size = (mp->urdma->rx_urdma_size/8); ++ mp->urdma->reg_base->intr_threshold = URDMA_RX_INTR_LEVEL; ++ mp->urdma->reg_base->rx_timeout = URDMA_RX_TIMEOUT; /* receive timeout. */ ++ ++ //need to clear buffer? ++ //memset(dma_rx_buf[fuartNum].Buffer,0,dma_rx_buf[fuartNum].Length); ++ ++ //2016.11.27 Refine: sw_rx_rptr is the index of rx_buf we have read ++ //Give initial value (size-1) according to HW behavior ++ mp->urdma->sw_rx_rptr = mp->urdma->rx_urdma_size - 1; ++} ++ ++void URDMA_TxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnable) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->tx_intr_en = bEnable?1:0; ++} ++ ++void URDMA_TxClearInterrupt(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->tx_intr_clr = 1; /* clear int status */ ++} ++ ++void URDMA_RxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnableTimeout) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_intr1_en=bEnableTimeout?1:0; ++} ++ ++void URDMA_RxSetupThresholdInterrupt(struct uart_port *p,BOOL bEnableThreshold) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_intr2_en=bEnableThreshold?1:0; ++} ++ ++U8 URDMA_RxGetInterrupt(struct uart_port *p) ++{ ++ U8 intr=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(mp->urdma->reg_base->rx_intr1) ++ { ++ intr |= URDMA_RX_INTR_TYPE_TIMEOUT; ++ } ++ ++ if(mp->urdma->reg_base->rx_intr2) ++ { ++ intr |= URDMA_RX_INTR_TYPE_THRESHOLD; ++ } ++ ++ return intr; ++} ++ ++void URDMA_RxClearInterrupt(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_intr_clr = 1; /* clear int status */ ++} ++ ++/* ++U32 URDMA_GetWritableSize(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ return (U32)((mp->urdma->reg_base->tx_buf_rptr - mp->urdma->reg_base->tx_buf_wptr - 1) & (mp->urdma->rx_urdma_size - 1)); ++} ++*/ ++ ++#if CONSOLE_DMA ++static int urdma_tx_thread(void *arg) ++{ ++ struct uart_port *p = (struct uart_port *)arg; ++ struct circ_buf *xmit; ++ while(!kthread_should_stop()){ ++ wait_event_interruptible(urdma_wait, urdma_conditions); ++ urdma_conditions = 0; ++ xmit = &p->state->xmit; ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ } ++ ++ if (uart_circ_chars_pending(xmit)) ++ { ++ URDMA_StartTx(p); ++ }else ++ { ++ uart_write_wakeup(p); ++ } ++ } ++ return 0; ++} ++ ++static int _urdma_tx(struct ms_uart_port *mp, unsigned char* buf, int buf_size) ++{ ++ int complete_size = 0; ++ int size_cp; ++ U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr; ++ U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr; ++ unsigned long flags1; ++ ++ spin_lock_irqsave(&mutex_console_2_dma, flags1); ++ if(mp->urdma->reg_base->tx_buf_wptr == 0 && mp->urdma->reg_base->tx_buf_rptr == 0){ ++ sw_tx_wptr = (sw_tx_wptr) & UR2DMA_TX_BUF_MASK; ++ } ++ else ++ { ++ sw_tx_wptr = (sw_tx_wptr +1) & UR2DMA_TX_BUF_MASK; ++ } ++ if (sw_tx_wptr >= sw_tx_rptr) ++ { ++ size_cp = min_t(int, (mp->urdma->tx_urdma_size - sw_tx_wptr), buf_size); ++ if (size_cp) ++ { ++ memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), buf, size_cp); ++ buf += size_cp; ++ buf_size -= size_cp; ++ complete_size += size_cp; ++ sw_tx_wptr = (sw_tx_wptr + size_cp) & UR2DMA_TX_BUF_MASK; ++ } ++ } ++ if (buf_size) ++ { ++ size_cp = min_t(int, (sw_tx_rptr - sw_tx_wptr), buf_size); ++ if (size_cp) ++ { ++ memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), buf, size_cp); ++ complete_size += size_cp; ++ } ++ } ++ if (complete_size) ++ { ++ Chip_Flush_MIU_Pipe(); ++ if(mp->urdma->reg_base->tx_buf_wptr == 0 && mp->urdma->reg_base->tx_buf_rptr == 0) ++ { ++ mp->urdma->reg_base->tx_buf_wptr = ((mp->urdma->reg_base->tx_buf_wptr + complete_size -1 ) & UR2DMA_TX_BUF_MASK); ++ } ++ else ++ { ++ mp->urdma->reg_base->tx_buf_wptr = ((mp->urdma->reg_base->tx_buf_wptr + complete_size) & UR2DMA_TX_BUF_MASK); ++ } ++ } ++ spin_unlock_irqrestore(&mutex_console_2_dma, flags1); ++ return complete_size; ++} ++ ++void URDMA_StartTx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ struct circ_buf *xmit = &p->state->xmit; ++ U16 circ_buf_out_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); ++ int complete_size = 0; ++ U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr; ++ U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr; ++ int space = (sw_tx_rptr > sw_tx_wptr) ? (sw_tx_rptr - sw_tx_wptr) : (mp->urdma->tx_urdma_size - sw_tx_wptr + sw_tx_rptr); ++ ++ if (circ_buf_out_size && (space > circ_buf_out_size)) ++ { ++ complete_size = _urdma_tx(mp, &xmit->buf[xmit->tail], circ_buf_out_size); ++ p->icount.tx += complete_size; ++ xmit->tail = (xmit->tail + complete_size) & (UART_XMIT_SIZE - 1); ++ } ++ ++ return; ++} ++#else // #if CONSOLE_DMA ++void URDMA_StartTx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ struct circ_buf *xmit = &p->state->xmit; ++ U16 circ_buf_out_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); ++ U16 tx_buf_space, tx_end; ++ ++ /* tx_buf_wptr point to the byte have been written to buffer */ ++ /* tx_buf_rptr point to the byte have been sent */ ++ /* if tx_buf_rptr meets tx_buf_wptr, it means all written bytes in buffer have been sent */ ++ /* In this case, the space equal to buffer size */ ++ ++ U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr; ++ U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr; ++ ++ if(sw_tx_wptr == (mp->urdma->tx_urdma_size-1)) //wptr meet the end of buffer, start from (0), end at (rptr) ++ { ++ sw_tx_wptr = 0; ++ tx_buf_space = sw_tx_rptr; ++ } ++ else if(sw_tx_wptr >= sw_tx_rptr) //start from (wptr+1), end at (buffer_size-1) ++ { ++ sw_tx_wptr+=1; ++ tx_buf_space = mp->urdma->tx_urdma_size - sw_tx_wptr; ++ } ++ else //start from (wptr+1), end at (rptr) ++ { ++ sw_tx_wptr+=1; ++ tx_buf_space = sw_tx_rptr - sw_tx_wptr; ++ } ++ ++ //pr_debug("sw_wp=%4x, sw_rp=%4x, tx_space=%4x, circ_buf_out_size=%4x, head=%4x, tail=%4x\n", sw_tx_wptr, sw_tx_rptr, tx_space, circ_buf_out_size, xmit->head, xmit->tail); ++ ++ if(circ_buf_out_size > tx_buf_space) //tx_cnt > tx_space ++ { ++ memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), &xmit->buf[xmit->tail], tx_buf_space); ++ p->icount.tx += tx_buf_space; ++ xmit->tail += tx_buf_space; ++ circ_buf_out_size -= tx_buf_space; ++ ++ //now we can start write from (0), end at (min[sw_tx_rptr,circ_buf_out_size]) ++ tx_end = circ_buf_out_size >= sw_tx_rptr ? sw_tx_rptr : circ_buf_out_size; ++ memcpy((void *)(&mp->urdma->tx_buf[0]), &xmit->buf[xmit->tail], tx_end); ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ p->icount.tx += tx_end; ++ xmit->tail = (xmit->tail + tx_end) & (UART_XMIT_SIZE - 1); ++ mp->urdma->reg_base->tx_buf_wptr = tx_end; ++ } ++ else //tx_cnt <= tx_space ++ { ++ memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]),&xmit->buf[xmit->tail], circ_buf_out_size); ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ p->icount.tx += circ_buf_out_size; ++ xmit->tail = (xmit->tail + circ_buf_out_size) & (UART_XMIT_SIZE - 1); ++ //mp->urdma->reg_base->tx_buf_wptr += circ_buf_out_size; ++ if(mp->urdma->reg_base->tx_buf_wptr == mp->urdma->tx_urdma_size-1) ++ mp->urdma->reg_base->tx_buf_wptr = circ_buf_out_size -1; ++ else ++ mp->urdma->reg_base->tx_buf_wptr += circ_buf_out_size; ++ } ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(p); ++ ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ } ++ return; ++} ++#endif ++ ++void URDMA_StartRx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ U16 sw_rx_wptr = mp->urdma->reg_base->rx_buf_wptr; ++ U16 sw_rx_rptr = mp->urdma->sw_rx_rptr; ++ U16 in_size = (sw_rx_wptr - sw_rx_rptr) & (mp->urdma->rx_urdma_size - 1); //read from (sw_rx_rptr+1), end at (sw_rx_wptr) ++ U16 rptr_to_end = mp->urdma->rx_urdma_size - sw_rx_rptr - 1; ++ ++ /* sw_rx_wptr point to the byte already read from UART */ ++ /* sw_rx_rptr point to the byte have been read */ ++ /* if sw_rx_rptr equal to sw_rx_wptr, it means all bytes in buffer have been read */ ++ ++ if(sw_rx_rptr==mp->urdma->rx_urdma_size - 1) //initial case ++ { ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[0], in_size - rptr_to_end); ++ p->icount.rx += in_size - rptr_to_end; ++ //update global sw_rx_rptr ++ mp->urdma->sw_rx_rptr = in_size - rptr_to_end -1; ++ tty_flip_buffer_push(&p->state->port); ++ pr_debug("(0) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size); ++ } ++ else if(in_size > rptr_to_end) ++ { ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[sw_rx_rptr+1], rptr_to_end); ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[0], in_size - rptr_to_end); ++ p->icount.rx += in_size; ++ //update global sw_rx_rptr ++ mp->urdma->sw_rx_rptr = (in_size - rptr_to_end - 1); ++ tty_flip_buffer_push(&p->state->port); ++ pr_debug("(1) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size); ++ } ++ else ++ { ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[(sw_rx_rptr+1)&(mp->urdma->rx_urdma_size-1)], in_size); ++ p->icount.rx += in_size; ++ //update global sw_rx_rptr ++ mp->urdma->sw_rx_rptr += in_size & (mp->urdma->rx_urdma_size - 1); //avoid sw_rx_rptr overflow ++ tty_flip_buffer_push(&p->state->port); ++ pr_debug("(2) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size); ++ } ++ return; ++} ++ ++ +diff --git a/drivers/sstar/spi/Kconfig b/drivers/sstar/spi/Kconfig +new file mode 100755 +index 000000000000..df55e75a5a7e +--- /dev/null ++++ b/drivers/sstar/spi/Kconfig +@@ -0,0 +1,5 @@ ++config MS_SPI_INFINITY ++ tristate "MS SPI driver" ++ default n ++ help ++ Enable support for SPI Driver +diff --git a/drivers/sstar/spi/Makefile b/drivers/sstar/spi/Makefile +new file mode 100755 +index 000000000000..a7df26a3b7da +--- /dev/null ++++ b/drivers/sstar/spi/Makefile +@@ -0,0 +1,9 @@ ++# ++# Makefile for kernel SPI drivers. ++# ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG ++ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_MS_SPI_INFINITY) += $(CONFIG_SSTAR_CHIP_NAME)/ +diff --git a/drivers/sstar/spi/infinity2/Makefile b/drivers/sstar/spi/infinity2/Makefile +new file mode 100755 +index 000000000000..3a1701d1c868 +--- /dev/null ++++ b/drivers/sstar/spi/infinity2/Makefile +@@ -0,0 +1,3 @@ ++# SPI master controller drivers (bus) ++ ++obj-$(CONFIG_MS_SPI_INFINITY) += mdrv_spi.o +diff --git a/drivers/sstar/spi/infinity2/mdrv_spi.c b/drivers/sstar/spi/infinity2/mdrv_spi.c +new file mode 100755 +index 000000000000..c1dbeb64dc37 +--- /dev/null ++++ b/drivers/sstar/spi/infinity2/mdrv_spi.c +@@ -0,0 +1,738 @@ ++/* ++ * Driver for Broadcom BCM2835 SPI Controllers ++ * ++ * Copyright (C) 2012 Chris Boot ++ * Copyright (C) 2013 Stephen Warren ++ * ++ * This driver is inspired by: ++ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos ++ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "ms_platform.h" ++ ++#include "mdrv_spi.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++#define U8 u8 ++#define U16 u16 ++#define U32 u32 ++#define BOOL bool ++#define TRUE true ++#define FALSE false ++ ++#define MSPI_DBG 1 ++#if MSPI_DBG ++ #define mspi_dbg(args...) printk(args) ++#else ++ #define mspi_dbg(args...) ++#endif ++ ++struct mstar_spi_dev { ++ int spinum; ++ int padmode; ++ int irq; ++ void __iomem *spibase; ++ void __iomem *chipbase; ++ void __iomem *clkbase; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ struct completion done; ++}; ++ ++static struct mutex hal_mspi_lock; ++ ++#define CLK_NUM 4 ++#define DIV_NUM 8 ++#define CFG_NUM 32 ++static U16 spi_clk[CLK_NUM] = {108, 54, 24, 12}; //bank 100b h16 ++static U16 spi_div[DIV_NUM] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static mspi_clk_cfg clk_cfg[CFG_NUM]; ++ ++void _mspi_clk_init(void) ++{ ++ U8 i = 0; ++ U8 j = 0; ++ mspi_clk_cfg cfg; ++ ++ memset(&cfg,0,sizeof(mspi_clk_cfg)); ++ memset(&clk_cfg,0,sizeof(mspi_clk_cfg)*CFG_NUM); ++ ++ for(i = 0; i < CLK_NUM; i++) ++ { ++ for(j = 0; j < DIV_NUM; j++) ++ { ++ clk_cfg[i*DIV_NUM+j].spi_clk = i; ++ clk_cfg[i*DIV_NUM+j].spi_div = j ; ++ clk_cfg[i*DIV_NUM+j].spi_speed = spi_clk[i]*1000000/spi_div[j]; ++ } ++ } ++ ++ for(i = 0; i < CFG_NUM; i++) ++ { ++ for(j = i; j < CFG_NUM; j++) ++ { ++ if(clk_cfg[i].spi_speed > clk_cfg[j].spi_speed) ++ { ++ memcpy(&cfg, &clk_cfg[i], sizeof(mspi_clk_cfg)); ++ memcpy(&clk_cfg[i], &clk_cfg[j], sizeof(mspi_clk_cfg)); ++ memcpy(&clk_cfg[j], &cfg, sizeof(mspi_clk_cfg)); ++ } ++ } ++ } ++} ++ ++U16 HAL_MSPI_GetDoneFlag(struct mstar_spi_dev *mspi_dev) ++{ ++ return READ_WORD(mspi_dev->spibase, REG_MSPI_DONE_FLAG); ++} ++ ++void HAL_MSPI_ClearDoneFlag(struct mstar_spi_dev *mspi_dev) ++{ ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_CLEAR_DONE_FLAG, MSPI_CLEAR_DONE); ++} ++ ++void HAL_MSPI_SetSpiEnable(struct mstar_spi_dev *mspi_dev, BOOL enable) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_CTRL); ++ if(enable) ++ { ++ u16regval |= (MSPI_INT_EN_BIT|MSPI_RESET_BIT | MSPI_ENABLE_BIT); ++ } ++ else ++ { ++ u16regval &= (~(MSPI_INT_EN_BIT | MSPI_ENABLE_BIT)); ++ } ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_CTRL, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetPadMode(struct mstar_spi_dev *mspi_dev) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ ++ if(mspi_dev->spinum == E_MSPI0) ++ { ++ u16regval = READ_WORD(mspi_dev->chipbase, REG_MSPI0_MODE); ++ u16regval = u16regval & (~MSPI_MSPI0_MODE_MASK); ++ u16regval = u16regval | (mspi_dev->padmode<< MSPI_MSPI0_MODE_SHIFT); ++ WRITE_WORD(mspi_dev->chipbase, REG_MSPI0_MODE, u16regval); ++ } ++ else if(mspi_dev->spinum == E_MSPI1) ++ { ++ u16regval = READ_WORD(mspi_dev->chipbase, REG_MSPI1_MODE); ++ u16regval = u16regval & (~MSPI_MSPI1_MODE_MASK); ++ u16regval = u16regval | (mspi_dev->padmode<< MSPI_MSPI1_MODE_SHIFT); ++ WRITE_WORD(mspi_dev->chipbase, REG_MSPI1_MODE, u16regval); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetSpiMode(struct mstar_spi_dev *mspi_dev, MSPI_MODE mode) ++{ ++ U16 u16regval = 0; ++ ++ if (mode >= E_MSPI_MODE_MAX) ++ { ++ return; ++ } ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_CTRL); ++ u16regval = u16regval & (~MSPI_MODE_MASK); ++ u16regval = u16regval | (mode << MSPI_MODE_SHIFT); ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_CTRL, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLsb(struct mstar_spi_dev *mspi_dev, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_LSB_FIRST, enable); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetClk(struct mstar_spi_dev *mspi_dev, U8 clk) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->clkbase, REG_MSPI_CKGEN); ++ if(mspi_dev->spinum == E_MSPI0)//mspi0 ++ { ++ u16regval &= (~MSPI_CKG_MSPI0_MASK); ++ u16regval |= (clk << MSPI_CKG_MSPI0_SHIFT); ++ } ++ else if(mspi_dev->spinum == E_MSPI1)//mspi1 ++ { ++ u16regval &= (~MSPI_CKG_MSPI1_MASK); ++ u16regval |= (clk << MSPI_CKG_MSPI1_SHIFT); ++ } ++ WRITE_WORD(mspi_dev->clkbase, REG_MSPI_CKGEN, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetClkDiv(struct mstar_spi_dev *mspi_dev, U8 div) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_CTRL); ++ u16regval &= MSPI_CLK_DIV_MASK; ++ u16regval |= div << MSPI_CLK_DIV_SHIFT; ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_CTRL, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_ChipSelect(struct mstar_spi_dev *mspi_dev, BOOL enable ,U8 select) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_CHIP_SELECT); ++ if(enable) ++ { ++ u16regval = (~(1 << select)); ++ } ++ else ++ { ++ u16regval = (1 << select); ++ } ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_CHIP_SELECT, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetBufSize(struct mstar_spi_dev *mspi_dev, MSPI_RW_DIR direct, U8 size) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_RW_BUF_SIZE); ++ if(direct == E_MSPI_READ) ++ { ++ u16regval &= MSPI_RW_BUF_MASK; ++ u16regval |= size << MSPI_READ_BUF_SHIFT; ++ } ++ else ++ { ++ u16regval &= (~MSPI_RW_BUF_MASK); ++ u16regval |= size; ++ } ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_RW_BUF_SIZE, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++BOOL HAL_MSPI_Trigger(struct mstar_spi_dev *mspi_dev) ++{ ++ unsigned int timeout = 0; ++ ++ reinit_completion(&mspi_dev->done); ++ ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_TRIGGER, MSPI_TRIGGER); ++ ++ timeout = wait_for_completion_timeout(&mspi_dev->done, msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_RW_BUF_SIZE, 0x0); ++ ++ if (!timeout) ++ { ++ mspi_dbg("%s:%d timeout\n",__func__, __LINE__); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++BOOL HAL_MSPI_Write(struct mstar_spi_dev *mspi_dev , U8 *pdata, U16 u16size) ++{ ++ U16 i = 0; ++ U16 *u16val = (U16*)pdata; ++ ++ u16size = u16size < MSPI_MAX_RW_BUF_SIZE ? u16size : MSPI_MAX_RW_BUF_SIZE; ++ ++ mutex_lock(&hal_mspi_lock); ++ ++ for(i = 0; i < u16size/2; i++) ++ { ++ WRITE_WORD(mspi_dev->spibase, (REG_MSPI_WRITE_BUF + i), u16val[i]); ++ } ++ ++ if(u16size%2) ++ { ++ WRITE_WORD(mspi_dev->spibase, (REG_MSPI_WRITE_BUF + u16size/2), pdata[u16size-1]); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ ++ HAL_MSPI_SetBufSize(mspi_dev,E_MSPI_WRITE, u16size); ++ ++ return HAL_MSPI_Trigger(mspi_dev); ++ ++} ++ ++BOOL HAL_MSPI_Read(struct mstar_spi_dev *mspi_dev , U8 *pdata, U16 u16size) ++{ ++ U16 i = 0; ++ U16 u16val = 0; ++ U16 *u16pdata = (U16*)pdata; ++ ++ u16size = u16size < MSPI_MAX_RW_BUF_SIZE ? u16size : MSPI_MAX_RW_BUF_SIZE; ++ ++ HAL_MSPI_SetBufSize(mspi_dev,E_MSPI_READ, u16size); ++ ++ if(!HAL_MSPI_Trigger(mspi_dev)) ++ return FALSE; ++ ++ mutex_lock(&hal_mspi_lock); ++ for(i = 0; i < u16size/2; i++) ++ { ++ u16val = READ_WORD(mspi_dev->spibase, (REG_MSPI_READ_BUF+i)); ++ u16pdata[i] = u16val; ++ } ++ ++ if(u16size%2) ++ { ++ u16val = READ_WORD(mspi_dev->spibase, (REG_MSPI_READ_BUF + u16size/2)); ++ pdata[u16size-1] = (u16val&0xFF); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ ++ return TRUE; ++} ++ ++void HAL_MSPI_SetTrTime(struct mstar_spi_dev *mspi_dev, MSPI_TIME_CFG cfg, U8 time) ++{ ++ U16 u16regval = 0; ++ ++ if(time > MSPI_CFG_TIME_MAX) ++ return; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_TR_TIME); ++ if(cfg == E_MSPI_TR_START_TIME) ++ { ++ u16regval &= (~MSPI_TIME_MASK); ++ u16regval |= time; ++ } ++ else if(cfg == E_MSPI_TR_END_TIME) ++ { ++ u16regval &= MSPI_TIME_MASK; ++ u16regval |= time << MSPI_TIME_SHIFT; ++ } ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_TR_TIME, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++ ++void HAL_MSPI_SetTbTime(struct mstar_spi_dev *mspi_dev, MSPI_TIME_CFG cfg, U8 time) ++{ ++ U16 u16regval = 0; ++ ++ if(time > MSPI_CFG_TIME_MAX) ++ return; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, REG_MSPI_TB_TIME); ++ if(cfg == E_MSPI_TB_INTERVAL_TIME) ++ { ++ u16regval &= (~MSPI_TIME_MASK); ++ u16regval |= time; ++ } ++ else if(cfg == E_MSPI_RW_TURN_AROUND_TIME) ++ { ++ u16regval &= MSPI_TIME_MASK; ++ u16regval |= time << MSPI_TIME_SHIFT; ++ } ++ WRITE_WORD(mspi_dev->spibase, REG_MSPI_TB_TIME, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetFrameSize(struct mstar_spi_dev *mspi_dev, U16 regaddr, U8 offset, U8 size) ++{ ++ U16 u16regval = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ u16regval = READ_WORD(mspi_dev->spibase, regaddr); ++ u16regval &= (~(MSPI_FRAME_SIZE_MASK << offset)); ++ u16regval |= (size&MSPI_FRAME_SIZE_MASK) << offset; ++ WRITE_WORD(mspi_dev->spibase, regaddr, u16regval); ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void MDrv_MSPI_FrameSizeInit(struct mstar_spi_dev *mspi_dev) ++{ ++ U8 i = 0; ++ U16 regoff = 0; ++ ++ // read buffer bit config ++ for(i = 0; i < MSPI_MAX_FRAME_BUF_NUM; i++) ++ { ++ regoff = (i/4) * 4; ++ HAL_MSPI_SetFrameSize(mspi_dev, REG_MSPI_READ_FRAME_SIZE+regoff, MSPI_FRAME_FIELD_BITS*i, 0x07); ++ } ++ ++ //write buffer bit config ++ for(i = 0; i < MSPI_MAX_FRAME_BUF_NUM; i++) ++ { ++ regoff = (i/4) * 4; ++ HAL_MSPI_SetFrameSize(mspi_dev, REG_MSPI_WRITE_FRAME_SIZE+regoff, MSPI_FRAME_FIELD_BITS*i, 0x07); ++ } ++} ++ ++U32 MDrv_MSPI_SetSpeed(struct mstar_spi_dev *mspi_dev, U32 speed) ++{ ++ U8 i = 0; ++ ++ for(i = 0; i < CFG_NUM; i++) ++ { ++ if(speed <= clk_cfg[i].spi_speed) ++ { ++ break; ++ } ++ } ++ ++ //match Closer clk ++ if((speed - clk_cfg[i-1].spi_speed) < (clk_cfg[i].spi_speed - speed)) ++ { ++ i--; ++ } ++ ++ mspi_dbg("%s:%d clk=%d,div=%d,speed=%d,spi_speed=%d\n",__func__, __LINE__, ++ clk_cfg[i].spi_clk, clk_cfg[i].spi_div, speed, clk_cfg[i].spi_speed); ++ ++ HAL_MSPI_SetClk(mspi_dev, clk_cfg[i].spi_clk); ++ HAL_MSPI_SetClkDiv(mspi_dev, clk_cfg[i].spi_div); ++ ++ return clk_cfg[i].spi_speed; ++} ++ ++void MDrv_MSPI_Init(struct mstar_spi_dev *mspi_dev) ++{ ++ mutex_init(&hal_mspi_lock); ++ HAL_MSPI_SetTrTime(mspi_dev, E_MSPI_TR_START_TIME, 0); ++ HAL_MSPI_SetTrTime(mspi_dev, E_MSPI_TR_END_TIME, 0); ++ HAL_MSPI_SetTbTime(mspi_dev, E_MSPI_TB_INTERVAL_TIME, 0); ++ HAL_MSPI_SetTbTime(mspi_dev, E_MSPI_RW_TURN_AROUND_TIME, 0); ++ ++ MDrv_MSPI_FrameSizeInit(mspi_dev); ++ ++ HAL_MSPI_SetSpiMode(mspi_dev, E_MSPI_MODE0); ++ HAL_MSPI_SetLsb(mspi_dev, 0); ++ HAL_MSPI_ChipSelect(mspi_dev, FALSE, 0); ++ ++ MDrv_MSPI_SetSpeed(mspi_dev, 54000000); ++ ++ HAL_MSPI_SetPadMode(mspi_dev); ++ HAL_MSPI_SetSpiEnable(mspi_dev, 1); ++ ++} ++ ++BOOL MDrv_MSPI_Write(struct mstar_spi_dev *mspi_dev, U8 *pdata, U16 u16size) ++{ ++ U8 i = 0; ++ U8 frmcnt = 0; ++ U8 lastfrmsize = 0; ++ ++ frmcnt = u16size/MSPI_MAX_RW_BUF_SIZE; ++ lastfrmsize = u16size%MSPI_MAX_RW_BUF_SIZE; ++ ++ for (i = 0; i < frmcnt; i++) ++ { ++ if(!HAL_MSPI_Write(mspi_dev, pdata+i*MSPI_MAX_RW_BUF_SIZE, MSPI_MAX_RW_BUF_SIZE)) ++ { ++ return FALSE; ++ } ++ } ++ ++ if(!lastfrmsize) ++ return TRUE; ++ ++ return HAL_MSPI_Write(mspi_dev, pdata+frmcnt*MSPI_MAX_RW_BUF_SIZE, lastfrmsize); ++ ++} ++ ++BOOL MDrv_MSPI_Read(struct mstar_spi_dev *mspi_dev, U8 *pdata, U16 u16size) ++{ ++ U8 i = 0; ++ U8 frmcnt = 0; ++ U8 lastfrmsize = 0; ++ ++ frmcnt = u16size/MSPI_MAX_RW_BUF_SIZE; ++ lastfrmsize = u16size%MSPI_MAX_RW_BUF_SIZE; ++ ++ for (i = 0; i < frmcnt; i++) ++ { ++ if(!HAL_MSPI_Read(mspi_dev, pdata+i*MSPI_MAX_RW_BUF_SIZE, MSPI_MAX_RW_BUF_SIZE)) ++ { ++ return FALSE;; ++ } ++ } ++ ++ if(!lastfrmsize) ++ return TRUE; ++ ++ return HAL_MSPI_Read(mspi_dev, pdata+frmcnt*MSPI_MAX_RW_BUF_SIZE, lastfrmsize); ++ ++} ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi_dev *mspi_dev = spi_master_get_devdata(spi->master); ++ ++ //HAL_MSPI_SetSpiEnable(mspi_dev, 0); ++ HAL_MSPI_SetSpiMode(mspi_dev, spi->mode & MSTAR_SPI_MODE_BITS); ++ HAL_MSPI_SetLsb(mspi_dev, (spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetSpeed(mspi_dev, spi->max_speed_hz); ++ //HAL_MSPI_SetSpiEnable(mspi_dev, 1); ++ mspi_dbg("%s:%d mode=%d,speed=%d\n",__func__, __LINE__, spi->mode, spi->max_speed_hz); ++ return 0; ++} ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, struct spi_transfer *tfr) ++{ ++ struct mstar_spi_dev *mspi_dev = spi_master_get_devdata(spi->master); ++ ++ //mspi_dbg("%s:%d\n",__func__, __LINE__); ++ ++ mspi_dev->tx_buf = tfr->tx_buf; ++ mspi_dev->rx_buf = tfr->rx_buf; ++ mspi_dev->len = tfr->len; ++ ++ HAL_MSPI_ChipSelect(mspi_dev, 1, spi->chip_select); ++ ++ if(mspi_dev->tx_buf != NULL) ++ { ++ if(!MDrv_MSPI_Write(mspi_dev, (U8 *)mspi_dev->tx_buf, (U16)mspi_dev->len)) ++ return E_MSPI_WRITE_ERR; ++ } ++ ++ if(mspi_dev->rx_buf != NULL) ++ { ++ if(!MDrv_MSPI_Read(mspi_dev, mspi_dev->rx_buf,(U16)mspi_dev->len)) ++ return E_MSPI_READ_ERR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ ++ struct mstar_spi_dev *mspi_dev = spi_master_get_devdata(spi->master); ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ HAL_MSPI_ChipSelect(mspi_dev , 0, spi->chip_select); ++ } ++ ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, struct spi_message *mesg) ++{ ++ struct mstar_spi_dev *mspi_dev = spi_master_get_devdata(master); ++ struct spi_device *spi = mesg->spi; ++ struct spi_transfer *tfr; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbg("%s:%d\n",__func__, __LINE__); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list){ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbg("%s:%d start_transfer error\n",__func__, __LINE__); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbg("%s:%d finish transfer error\n",__func__, __LINE__); ++ goto out; ++ } ++ mesg->actual_length += mspi_dev->len; ++ mspi_dbg("%s:%d transfered:%d\n",__func__, __LINE__, mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct mstar_spi_dev *mspi_dev = dev_id; ++ int flag = 0; ++ ++ flag = HAL_MSPI_GetDoneFlag(mspi_dev); ++ if(flag == 1) ++ { ++ complete(&mspi_dev->done); ++ //mspi_dbg("%s:%d spi done!\n",__func__, __LINE__); ++ } ++ ++ HAL_MSPI_ClearDoneFlag(mspi_dev); ++ ++ return IRQ_HANDLED; ++} ++ ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ int err = 0; ++ int proval = 0; ++ struct resource *res; ++ struct spi_master *master; ++ struct mstar_spi_dev *mspi_dev; ++ ++ mspi_dbg("%s:%d enter\n",__func__, __LINE__); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*mspi_dev)); ++ if (!master) ++ { ++ mspi_dbg("%s:%d spi_alloc_master() failed\n",__func__, __LINE__); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, master); ++ ++ master->dev.of_node = pdev->dev.of_node; ++ master->bus_num = pdev->id; ++ master->mode_bits = MSTAR_SPI_MODE_BITS; ++ master->num_chipselect = 3; ++ master->max_speed_hz = 54000000; // 108M/2 ++ master->min_speed_hz = 46875; // 12M/256 ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->setup = mstar_spi_setup; ++ master->transfer_one_message = mstar_spi_transfer_one; ++ ++ mspi_dev = spi_master_get_devdata(master); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mspi_dev->spibase = (void *)(IO_ADDRESS(res->start)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ mspi_dev->chipbase = (void *)(IO_ADDRESS(res->start)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ mspi_dev->clkbase= (void *)(IO_ADDRESS(res->start)); ++ ++ of_property_read_u32(pdev->dev.of_node, "spi-num", &proval); ++ mspi_dev->spinum = proval; ++ master->bus_num = proval; ++ ++ of_property_read_u32(pdev->dev.of_node, "pad-mode", &proval); ++ mspi_dev->padmode = proval; ++ ++ init_completion(&mspi_dev->done); ++ ++ _mspi_clk_init(); ++ ++ mspi_dev->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (!mspi_dev->irq) ++ { ++ mspi_dbg("%s:%d irq_of_parse_and_map() failed\n",__func__, __LINE__); ++ goto err0; ++ } ++ ++ if (devm_request_irq(&pdev->dev, mspi_dev->irq, mstar_spi_interrupt, 0/*SA_INTERRUPT*/, pdev->name, mspi_dev)) ++ { ++ mspi_dbg("%s:%d request_irq() failed\n",__func__, __LINE__); ++ goto err0; ++ } ++ ++ MDrv_MSPI_Init(mspi_dev); ++ ++ err = devm_spi_register_master(&pdev->dev, master); ++ if (err) ++ { ++ mspi_dbg("%s:%d register error(%d)\n",__func__, __LINE__, err); ++ goto err0; ++ } ++ ++ mspi_dbg("%s:%d exit\n",__func__, __LINE__); ++ ++ return 0; ++ ++err0: ++ spi_master_put(master); ++ mspi_dbg("%s:%d spi error exit\n",__func__, __LINE__); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ ++ spi_master_put(master); ++ ++ return 0; ++} ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "mstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("mstar Boot "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/spi/infinity2/mdrv_spi.h b/drivers/sstar/spi/infinity2/mdrv_spi.h +new file mode 100755 +index 000000000000..ae7467b957a4 +--- /dev/null ++++ b/drivers/sstar/spi/infinity2/mdrv_spi.h +@@ -0,0 +1,144 @@ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// mdrv_spi.h ++// ++// DESCRIPTION ++// ++// ++// HISTORY ++// ++//----------------------------------------------------------------------------- ++ ++#ifndef __MDRV_SPI_H ++#define __MDRV_SPI_H ++ ++//#include "ms_types.h" ++ ++#define DRV_NAME "spi" ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSPI_CFG_TIME_MAX 0xFF ++ ++#define MS_IO_OFFSET 0xDE000000 ++/* macro to get at MMIO space when running virtually */ ++#define IO_ADDRESS(x) ( (u32)(x) + MS_IO_OFFSET ) ++//bank spi ++#define REG_MSPI_WRITE_BUF 0x40 ++ #define MSPI_MAX_RW_BUF_SIZE 0x8 ++ ++#define REG_MSPI_READ_BUF 0x44 ++ ++#define REG_MSPI_RW_BUF_SIZE 0x48 ++ #define MSPI_RW_BUF_MASK 0xFF ++ #define MSPI_READ_BUF_SHIFT 8 ++ ++#define REG_MSPI_CTRL 0x49 ++ #define MSPI_ENABLE_BIT 0x1 ++ #define MSPI_RESET_BIT 0x2 ++ #define MSPI_INT_EN_BIT 0x4 ++ #define MSPI_MODE_SHIFT 6 ++ #define MSPI_MODE_MASK (3 << 6) ++ #define MSPI_CLK_DIV_SHIFT 8 ++ #define MSPI_CLK_DIV_MASK 0xFF ++ ++#define REG_MSPI_TR_TIME 0x4A ++#define REG_MSPI_TB_TIME 0x4B ++ #define MSPI_TIME_MASK 0xFF ++ #define MSPI_TIME_SHIFT 8 ++ ++#define REG_MSPI_WRITE_FRAME_SIZE 0x4C ++#define REG_MSPI_READ_FRAME_SIZE 0x4E ++ #define MSPI_FRAME_SIZE_MASK 0x07 ++ #define MSPI_MAX_FRAME_BUF_NUM 8 ++ #define MSPI_FRAME_FIELD_BITS 3 ++ ++#define REG_MSPI_LSB_FIRST 0x50 ++ ++#define REG_MSPI_TRIGGER 0x5A ++ #define MSPI_TRIGGER 0x01 ++ ++#define REG_MSPI_DONE_FLAG 0x5B ++ ++#define REG_MSPI_CLEAR_DONE_FLAG 0x5C ++ #define MSPI_CLEAR_DONE 0x01 ++ ++#define REG_MSPI_CHIP_SELECT 0x5F ++ ++ ++//bank clock gen0 ++#define REG_MSPI_CKGEN 0x16 ++ #define MSPI_CKG_MSPI0_SHIFT 10 ++ #define MSPI_CKG_MSPI0_MASK (0x0F << 8) ++ #define MSPI_CKG_MSPI1_SHIFT 14 ++ #define MSPI_CKG_MSPI1_MASK (0x0F << 12) ++ ++//bank chiptop ++#define REG_MSPI0_MODE 0x08 ++ #define MSPI_MSPI0_MODE_SHIFT 0 ++ #define MSPI_MSPI0_MODE_MASK 3 ++ ++#define REG_MSPI1_MODE 0x08 ++ #define MSPI_MSPI1_MODE_SHIFT 6 ++ #define MSPI_MSPI1_MODE_MASK (3 << 6) ++ ++typedef enum { ++ E_MSPI_OK = 0 ++ ,E_MSPI_PARAM_ERR = 1 ++ ,E_MSPI_INIT_ERR = 2 ++ ,E_MSPI_READ_ERR = 4 ++ ,E_MSPI_WRITE_ERR = 8 ++ ,E_MSPI_NULL ++} MSPI_ERR_NO; ++ ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++typedef enum ++{ ++ E_MSPI_READ, ++ E_MSPI_WRITE ++}MSPI_RW_DIR; ++ ++typedef enum ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}MSPI_CFG; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_MODE; ++ ++typedef enum ++{ ++ E_MSPI_TR_START_TIME, ++ E_MSPI_TR_END_TIME, ++ E_MSPI_TB_INTERVAL_TIME, ++ E_MSPI_RW_TURN_AROUND_TIME ++}MSPI_TIME_CFG; ++ ++typedef struct ++{ ++ u8 spi_clk; ++ u8 spi_div; ++ u32 spi_speed; ++}mspi_clk_cfg; ++ ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA) ++ ++#define READ_WORD(baseaddr, bank) (*(volatile u16*)(baseaddr + ((bank)<<2))) ++#define WRITE_WORD(baseaddr, bank, val) (*((volatile u16*)(baseaddr + ((bank)<<2)))) = (u16)(val) ++ ++#endif //__MDRV_SPI_H +diff --git a/drivers/sstar/spi/infinity2m/Makefile b/drivers/sstar/spi/infinity2m/Makefile +new file mode 100755 +index 000000000000..b221509020cb +--- /dev/null ++++ b/drivers/sstar/spi/infinity2m/Makefile +@@ -0,0 +1,7 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_MS_SPI_INFINITY) += mspi.o +diff --git a/drivers/sstar/spi/infinity2m/mspi.c b/drivers/sstar/spi/infinity2m/mspi.c +new file mode 100755 +index 000000000000..cf6e85e5fafb +--- /dev/null ++++ b/drivers/sstar/spi/infinity2m/mspi.c +@@ -0,0 +1,1833 @@ ++/* ++* spi-infinity.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#if defined(CONFIG_MS_PADMUX) ++#include "mdrv_padmux.h" ++#include "mdrv_puse.h" ++#include "gpio.h" ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++bool gbInitFlag = false; ++static struct mutex hal_mspi_lock; ++bool SUPPORT_DMA = false; ++ ++//------------------------------------------------------------------------------------------------- ++// RegbaseAddr Disc ++//------------------------------------------------------------------------------------------------- ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk(args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++ ++#define U8 u8 ++#define U16 u16 ++#define U32 u32 ++#define BOOL bool ++#define TRUE true ++#define FALSE false ++ ++#define SUPPORT_SPI_1 0 ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++ ++#define MSPI0_BANK_ADDR 0x1110 ++#define MSPI1_BANK_ADDR 0x1111 ++#define CLK__BANK_ADDR 0x1038 ++#define CHIPTOP_BANK_ADDR 0x101E ++#define MOVDMA_BANK_ADDR 0x100B ++ ++#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) ++#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) ++#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) ++#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++//------------------------------------------------------------------------------------------------- ++// Hardware Register Capability ++//------------------------------------------------------------------------------------------------- ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_RD00 (0x78) ++#define MSPI_FULL_DEPLUX_RD01 (0x78) ++#define MSPI_FULL_DEPLUX_RD02 (0x79 ++#define MSPI_FULL_DEPLUX_RD03 (0x79) ++#define MSPI_FULL_DEPLUX_RD04 (0x7a) ++#define MSPI_FULL_DEPLUX_RD05 (0x7a) ++#define MSPI_FULL_DEPLUX_RD06 (0x7b) ++#define MSPI_FULL_DEPLUX_RD07 (0x7b) ++ ++#define MSPI_FULL_DEPLUX_RD08 (0x7c) ++#define MSPI_FULL_DEPLUX_RD09 (0x7c) ++#define MSPI_FULL_DEPLUX_RD10 (0x7d) ++#define MSPI_FULL_DEPLUX_RD11 (0x7d) ++#define MSPI_FULL_DEPLUX_RD12 (0x7e) ++#define MSPI_FULL_DEPLUX_RD13 (0x7e) ++#define MSPI_FULL_DEPLUX_RD14 (0x7f) ++#define MSPI_FULL_DEPLUX_RD15 (0x7f) ++ ++//chip select bit map ++ #define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++// clk_mspi0 ++#define MSPI0_CLK_CFG 0x33//bit 2 ~bit 3 ++ #define MSPI0_CLK_108M 0x00 ++ #define MSPI0_CLK_54M 0x04 ++ #define MSPI0_CLK_12M 0x08 ++ #define MSPI0_CLK_MASK 0x0F ++// clk_mspi1 ++#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 ++ #define MSPI1_CLK_108M 0x0000 ++ #define MSPI1_CLK_54M 0x0400 ++ #define MSPI1_CLK_12M 0x0800 ++ #define MSPI1_CLK_MASK 0x0F00 ++ ++// clk_mspi ++#define MSPI_CLK_CFG 0x33 ++ #define MSPI_SELECT_0 0x0000 ++ #define MSPI_SELECT_1 0x4000 ++ #define MSPI_CLK_MASK 0xF000 ++ ++//CHITOP 101E mspi mode select ++#define MSPI0_MODE 0x0C //bit0~bit1 ++ #define MSPI0_MODE_MASK 0x07 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ #define MSPI1_MODE_MASK 0x70 ++#define EJTAG_MODE 0xF ++ #define EJTAG_MODE_1 0x01 ++ #define EJTAG_MODE_2 0x02 ++ #define EJTAG_MODE_3 0x03 ++ #define EJTAG_MODE_MASK 0x03 ++ ++//MOVDMA 100B ++#define MOV_DMA_SRC_ADDR_L 0x03 ++#define MOV_DMA_SRC_ADDR_H 0x04 ++#define MOV_DMA_DST_ADDR_L 0x05 ++#define MOV_DMA_DST_ADDR_H 0x06 ++#define MOV_DMA_BYTE_CNT_L 0x07 ++#define MOV_DMA_BYTE_CNT_H 0x08 ++#define DMA_MOVE0_ENABLE 0x00 ++#define DMA_RW 0x50 //0 for dma write to device, 1 for dma read from device ++ #define DMA_READ 0x01 ++ #define DMA_WRITE 0x00 ++#define DMA_DEVICE_MODE 0x51 ++#define DMA_DEVICE_SEL 0x52 ++ ++//spi dma ++#define MSPI_DMA_DATA_LENGTH_L 0x30 ++#define MSPI_DMA_DATA_LENGTH_H 0x31 ++#define MSPI_DMA_ENABLE 0x32 ++#define MSPI_DMA_RW_MODE 0x33 ++ #define MSPI_DMA_WRITE 0x00 ++ #define MSPI_DMA_READ 0x01 ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile u32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } ++ ++// read 2 byte ++#define MSPI_READ(_reg_) READ_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2)) ++// write 2 byte ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_)) ++//write 2 byte mask ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_), (mask)) ++ ++#define CLK_READ(_reg_) READ_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2)) ++#define CLK_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define CHIPTOP_READ(_reg_) READ_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2)) ++#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define MOVDMA_READ(_reg_) READ_WORD(bs->VirtMovdmaBaseAddr + ((_reg_)<<2)) ++#define MOVDMA_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMovdmaBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) ++#define MAX_CHECK_CNT 2000 ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++#define SPI_MIU0_BUS_BASE 0x20000000 ++#define SPI_MIU1_BUS_BASE 0xFFFFFFFF ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef struct ++{ ++ u32 u32Clock; ++ u8 u8Clock; ++ bool BClkPolarity; ++ bool BClkPhase; ++ u32 u32MAXClk; ++} MSPI_CLKConfig; ++ ++ ++typedef struct ++{ ++ u8 u8ClkSpi_cfg; ++ u8 u8ClkSpi_DIV; ++ u32 u32ClkSpi; ++}ST_DRV_MSPI_CLK; ++ ++typedef enum ++{ ++ E_MSPI_DBGLV_NONE, //disable all the debug message ++ E_MSPI_DBGLV_INFO, //information ++ E_MSPI_DBGLV_NOTICE, //normal but significant condition ++ E_MSPI_DBGLV_WARNING, //warning conditions ++ E_MSPI_DBGLV_ERR, //error conditions ++ E_MSPI_DBGLV_CRIT, //critical conditions ++ E_MSPI_DBGLV_ALERT, //action must be taken immediately ++ E_MSPI_DBGLV_EMERG, //system is unusable ++ E_MSPI_DBGLV_DEBUG, //debug-level messages ++} MSPI_DbgLv; ++ ++typedef enum _MSPI_ERRORNOn { ++ E_MSPI_OK = 0 ++ ,E_MSPI_INIT_FLOW_ERROR =1 ++ ,E_MSPI_DCCONFIG_ERROR =2 ++ ,E_MSPI_CLKCONFIG_ERROR =4 ++ ,E_MSPI_FRAMECONFIG_ERROR =8 ++ ,E_MSPI_OPERATION_ERROR = 0x10 ++ ,E_MSPI_PARAM_OVERFLOW = 0x20 ++ ,E_MSPI_MMIO_ERROR = 0x40 ++ ,E_MSPI_HW_NOT_SUPPORT = 0x80 ++ ,E_MSPI_NULL ++} MSPI_ErrorNo; ++ ++typedef struct ++{ ++ MSPI_CH eCurrentCH; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char *VirtMovdmaBaseAddr; ++} MSPI_BaseAddr_st; ++ ++static MSPI_BaseAddr_st _hal_msp = { ++ .eCurrentCH = E_MSPI0, ++ //.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR, ++ //.VirtClkBaseAddr = BASE_REG_CLK_ADDR, ++ //.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) ++ ++#define DRV_NAME "spi" ++struct mstar_spi { ++ void __iomem *regs; ++ struct clk *clk; ++#ifdef _EN_MSPI_INTC_ ++ int irq; ++ struct completion done; ++#endif ++ int use_dma; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char *VirtMovdmaBaseAddr; ++ char u8channel; ++ int u32spi_mode; ++}; ++ ++static struct spi_board_info mstar_info = { ++ .modalias = "spidev", ++}; ++ ++static void _HAL_MSPI_CheckandSetBaseAddr(MSPI_CH eChannel) ++{ ++ ++#if 0 ++ if(eChannel == _hal_msp.eCurrentCH) ++ { ++ return; ++ } else if(eChannel == E_MSPI0) ++ { ++ _hal_msp.eCurrentCH = E_MSPI0; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi0 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else if(eChannel == E_MSPI1) ++ { ++ _hal_msp.eCurrentCH = E_MSPI1; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI1_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi1 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else ++ { ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("[Mspi Error]FUN:%s MSPI Channel is out of range!\n",__FUNCTION__)); ++ printk("[Mspi Error]FUN: MSPI Channel is out of range!\n"); ++ return ; ++ } ++ ++#endif ++} ++//------------------------------------------------------------------------------ ++/// Description : Reset Frame register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_FrameConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : MSPI interrupt enable ++/// @param bEnable \b OUT: enable or disable mspi interrupt ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_IntEnable(struct mstar_spi *bs,MSPI_CH eChannel,bool bEnable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++#if defined(CONFIG_MS_PADMUX) ++static int _MSPI_IsPadSet(MSPI_CH eChannel) ++{ ++ // important: need to modify if more MDRV_PUSE_SPI? defined ++ if (eChannel == E_MSPI0 && PAD_UNKNOWN != mdrv_padmux_getpad(MDRV_PUSE_SPI0_CK) ) ++ { ++ //printk("SPI: %d pad set by padmux driver!!\n", eChannel); ++ return TRUE; ++ } ++ else ++ return FALSE; ++} ++#endif ++ ++void HAL_MSPI_Init(struct mstar_spi *bs,MSPI_CH eChannel,u8 u8Mode) ++{ ++ u16 TempData; ++ //init MSP ++ //DEBUG_MSPI(E_MSPI_DBGLV_INFO,printk("HAL_MSPI_Init\n")); ++ mspi_dbgmsg("HAL_MSPI_Init : Channel=%d spi mode=%d\n",eChannel,u8Mode); ++ mutex_init(&hal_mspi_lock); ++ if((eChannel > E_MSPI1) || (u8Mode < 1)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI0) && (u8Mode > 6)) ++ { ++ return; ++ } ++#if SUPPORT_SPI_1 ++ else if((eChannel == E_MSPI1) && (u8Mode > 6)) ++ { ++ return; ++ } ++#endif ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++ if(eChannel == E_MSPI0) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= MSPI0_CLK_108M; ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ ++#if defined(CONFIG_MS_PADMUX) ++ if (0 == mdrv_padmux_active() || ++ FALSE == _MSPI_IsPadSet(E_MSPI0) ) ++#endif ++ { ++ //printk("SPI: %d pad set by SPI driver!!\n", eChannel); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI0_MODE); ++ TempData &= ~(MSPI0_MODE_MASK); ++ TempData |= u8Mode; ++ CHIPTOP_WRITE(MSPI0_MODE,TempData); ++ ++ //Disable jtag mode // IO PAD conflict turn off jtag ++ TempData = CHIPTOP_READ(EJTAG_MODE); ++ if((u8Mode == 4 && TempData == EJTAG_MODE_1) || ++ (u8Mode == 3 && TempData == EJTAG_MODE_3) ){ ++ TempData &= ~(EJTAG_MODE_MASK); ++ CHIPTOP_WRITE(EJTAG_MODE,TempData); ++ } ++ } ++ } ++#if SUPPORT_SPI_1 ++ else if (eChannel == E_MSPI1) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ ++#if defined(CONFIG_MS_PADMUX) ++ if (0 == mdrv_padmux_active() || ++ FALSE == _MSPI_IsPadSet(E_MSPI1) ) ++#endif ++ { ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI1_MODE); ++ TempData &= ~(MSPI1_MODE_MASK); ++ TempData |= (u8Mode << 4); ++ CHIPTOP_WRITE(MSPI1_MODE,TempData); ++ } ++ } ++#endif ++ mutex_unlock(&hal_mspi_lock); ++ return; ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return NONE ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetDcTiming (struct mstar_spi *bs,MSPI_CH eChannel, eDC_config eDCField, U8 u8DCtiming) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ switch(eDCField) { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static void _HAL_MSPI_RWBUFSize(struct mstar_spi *bs,BOOL Direct, U8 Size) ++{ ++ U16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++//------------------------------------------------------------------------------ ++/// Description : check MSPI operation complete ++/// @return TRUE : operation complete ++/// @return FAIL : failed timeout ++//------------------------------------------------------------------------------ ++static U16 _HAL_MSPI_CheckDone(struct mstar_spi *bs) ++{ ++/* ++ U16 uCheckDoneCnt = 0; ++ U16 uDoneFlag = 0; ++ while(uCheckDoneCnt < MAX_CHECK_CNT) { ++ uDoneFlag = MSPI_READ(MSPI_DONE_OFFSET); ++ if(uDoneFlag & MSPI_DONE_FLAG) { ++ printk("Done flag success!!!!!!!!!!!!!!!!!!!!!!!!\n"); ++ return TRUE; ++ } ++ // printk("..."); ++ uCheckDoneCnt++; ++ } ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("ERROR:MSPI Operation Timeout!!!!!\n")); ++ printk("ERROR:MSPI Operation asasTimeout!!!!!\n"); ++ return FALSE; ++*/ ++ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++//------------------------------------------------------------------------------ ++/// Description : SPI chip select enable and disable ++/// @param Enable \b OUT: enable or disable chip select ++//------------------------------------------------------------------------------ ++static void _HAL_MSPI_ChipSelect(struct mstar_spi *bs,BOOL Enable ,U8 eSelect) ++{ ++ U16 regdata = 0; ++ U8 bitmask = 0; ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } else { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Trigger MSPI operation ++/// @return TRUE : operation success ++/// @return FALSE : operation timeout ++//------------------------------------------------------------------------------ ++#ifdef _EN_MSPI_INTC_ ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&bs->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ ++ timeout = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) { ++ mspi_dbgmsg("timeout\n"); ++ //goto out; ++ } ++ ++ // check operation complete ++// if(!_HAL_MSPI_CheckDone()) { ++// return FALSE; ++// } ++ // clear done flag ++// _HAL_MSPI_ClearDone(); ++ // reset read/write buffer size ++// MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ return TRUE; ++} ++#else ++#define HW_MSPI_WAIT_TIMEOUT (30000) ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++ U16 volatile time_remain = HW_MSPI_WAIT_TIMEOUT; ++ // trigger operation ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ ++ while (time_remain--) { ++ ++ if (_HAL_MSPI_CheckDone(bs) == 1) { //done ++ if(SUPPORT_DMA){ ++ mspi_dbgmsg("< Chip Select Disable >\r\n"); ++ _HAL_MSPI_ChipSelect(bs,0,0);//disable chip select for device0 (pulled high) ++ } ++ _HAL_MSPI_ClearDone(); // for debug ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_Done >>>>>>>>>>>>>>>>>\n"); ++ break; ++ } ++ } ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!time_remain) { ++ mspi_dbgmsg("timeout\n"); ++ return FALSE; ++ } ++ return TRUE; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return TRUE : read data success ++/// @return FALSE : read data fail ++//------------------------------------------------------------------------------------------------- ++BOOL HAL_MSPI_Read(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U16 i =0, j = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) { ++ j = MAX_READ_BUF_SIZE; ++ } else { ++ j = u16TempBuf; ++ } ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, j); ++ ++ _HAL_MSPI_Trigger(bs); ++ ++ for(u8Index = 0; u8Index < j; u8Index++) { ++ ++ if(u8Index & 1) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } else if(u8Index == (j -1)) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ ++ //printk("******************* read Buf data %x index %d\n",u16TempBuf, u8Index); ++ } ++ pData+= j; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : read data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return TRUE : write data success ++/// @return FALSE : wirte data fail ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Write(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) { ++ if(u8Index & 1) { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",u16TempBuf, u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } else if(u8Index == (u16Size -1)) { ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",pData[u8Index], u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, u16Size); ++ _HAL_MSPI_Trigger(bs); ++ // set write data size ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset CLK register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_CLKConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ U16 Tempbuf; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++U8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set TrStart timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrStart timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrStartSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrStart) ++{ ++ U8 u8TrStartMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset DC register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_DCConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set MSPI chip select ++/// @param u8CS \u8 OUT: MSPI chip select ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetChipSelect(struct mstar_spi *bs,MSPI_CH eChannel, BOOL Enable, U8 u8CS) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ _HAL_MSPI_ChipSelect(bs, Enable, u8CS); ++ mutex_unlock(&hal_mspi_lock); ++} ++// add to sync code from utopia for localdimming to set clk ++void MDrv_MSPI_ChipSelect(struct mstar_spi *bs,U8 u8Channel, BOOL Enable, U8 u8CS) ++{ ++ HAL_MSPI_SetChipSelect(bs,(MSPI_CH)u8Channel,Enable,u8CS); ++ return; ++} ++ ++U32 HAL_MSPI_SelectCLK(struct mstar_spi *bs,U8 u8Channel) //Enable DMA CLK ++{ ++ u16 TempData; ++ ++ TempData = CLK_READ(MSPI_CLK_CFG); ++ if(u8Channel == E_MSPI0)//mspi0 ++ { ++ // CLK SETTING ++ TempData &= ~(MSPI_CLK_MASK); ++ TempData |= MSPI_SELECT_0; ++ } ++ else if(u8Channel == E_MSPI1)//mspi1 ++ { ++ // CLK SETTING ++ TempData &= ~(MSPI_CLK_MASK); ++ TempData |= MSPI_SELECT_1; ++ } ++ CLK_WRITE(MSPI_CLK_CFG, TempData); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_MSPI_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ int ret = 0; ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(U8TempLastFrameCnt) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++//------------------------------------------------------------------------------ ++/// Description : write data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ BOOL ret = false; ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(U8TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++U8 MDrv_MSPI_DMA_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ dma_addr_t data_addr; ++ ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ mutex_lock(&hal_mspi_lock); ++ ++ HAL_MSPI_SelectCLK(bs, u8Channel); ++ ++ MOVDMA_WRITE( DMA_RW, DMA_READ); // 1 for dma read from device ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_READ); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u16Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, (u16Size>>16)& 0x00FF); // 24bit ++ ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_L, u16Size & 0xFFFF ); ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_H, u16Size>>16 ); ++ ++ data_addr=dma_map_single(NULL, pData, u16Size, DMA_TO_DEVICE); ++ if(data_addr > SPI_MIU1_BUS_BASE) ++ data_addr -= SPI_MIU1_BUS_BASE; ++ else ++ data_addr -= SPI_MIU0_BUS_BASE; ++ ++ MOVDMA_WRITE(MOV_DMA_DST_ADDR_L, data_addr & 0x0000FFFF ); ++ MOVDMA_WRITE(MOV_DMA_DST_ADDR_H, data_addr >>16 ); ++ ++ MOVDMA_WRITE(0x00,0x01);//dma enable ++ _HAL_MSPI_ChipSelect(bs,1,0);//enable chip select for device0 (pulled low) ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, 0); //spi length = 0 ++ _HAL_MSPI_Trigger(bs); ++ ++ mutex_unlock(&hal_mspi_lock); ++ return E_MSPI_OK; ++} ++ ++U8 MDrv_MSPI_DMA_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ dma_addr_t data_addr; ++ mutex_lock(&hal_mspi_lock); ++ ++ //printk("### MDrv_MSPI_DMA_Write\r\n"); ++ ++ HAL_MSPI_SelectCLK(bs, u8Channel); ++ ++ MOVDMA_WRITE( DMA_RW, DMA_WRITE );//0 for dma write to device ++ MOVDMA_WRITE( DMA_DEVICE_MODE, 0x0001 ); // 1 to enable dma device mode ++ MOVDMA_WRITE( DMA_DEVICE_SEL, bs->u8channel); //0 select mspi0 , 1 select mspi1 ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_WRITE); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u16Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, u16Size>>16 ); ++ ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_L, u16Size & 0xFFFF ); ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_H, u16Size>>16 ); ++ ++ data_addr=dma_map_single(NULL, pData, u16Size, DMA_FROM_DEVICE); ++ if(data_addr > SPI_MIU1_BUS_BASE) ++ data_addr -= SPI_MIU1_BUS_BASE; ++ else ++ data_addr -= SPI_MIU0_BUS_BASE; ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ MOVDMA_WRITE(MOV_DMA_SRC_ADDR_L, data_addr & 0x0000FFFF ); ++ MOVDMA_WRITE(MOV_DMA_SRC_ADDR_H, data_addr >>16); ++ ++ ++ MOVDMA_WRITE(0x00,0x01);//dma enable ++ _HAL_MSPI_ChipSelect(bs,1,0);//enable chip select for device0 (pulled low) ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, 0); ++ _HAL_MSPI_Trigger(bs); ++ ++ mutex_unlock(&hal_mspi_lock); ++ return E_MSPI_OK; ++} ++ ++ ++u8 MDrv_MSPI_Init(struct mstar_spi *bs,u8 u8Channel,u8 u8Mode) ++{ ++ u8 errorno = E_MSPI_OK; ++ HAL_MSPI_Init(bs,(MSPI_CH)u8Channel,u8Mode); ++ HAL_MSPI_IntEnable(bs,(MSPI_CH)u8Channel,true); ++ gbInitFlag = true; ++ return errorno; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TrEnd timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrEnd timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrEndSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrEnd) ++{ ++ U8 u8TrEndMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TREND ,TrEnd); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TB timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TB timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TBSetting(struct mstar_spi *bs,U8 u8Channel,U8 TB) ++{ ++ U8 u8TBMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TB ,TB); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TRW timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TRW timging ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TRWSetting(struct mstar_spi *bs,U8 u8Channel,U8 TRW) ++{ ++ U8 u8TRWMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRW ,TRW); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of transfer timing config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_DCCONFIG_ERROR : failed to config transfer timing ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_DCConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_DCConfig *ptDCConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_INIT_FLOW_ERROR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ errnum = _MDrv_DC_TrStartSetting(bs,u8Channel,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TrEndSetting(bs,u8Channel,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TBSetting(bs,u8Channel,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TRWSetting(bs,u8Channel,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++void HAL_MSPI_SetCLKTiming(struct mstar_spi *bs,MSPI_CH eChannel, eCLK_config eCLKField, U8 u8CLKVal) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ switch(eCLKField) { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLSB(struct mstar_spi *bs,MSPI_CH eChannel, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++#define NUM_SPI_CKG 4 ++#define NUM_SPI_CLKDIV 8 ++#define NUM_SPI_CLKRATES 32 //NUM_SPI_CKG * NUM_SPI_CLKDIVRATE ++static U8 clk_spi_ckg[NUM_SPI_CKG] = {108, 54, 12, 144}; ++static U16 clk_spi_div[NUM_SPI_CLKDIV] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static ST_DRV_MSPI_CLK clk_buffer[NUM_SPI_CLKRATES]; ++ ++U32 HAL_MSPI_CLK_Config(struct mstar_spi *bs,U8 u8Chanel,U32 u32MspiClk) ++{ ++ U8 i = 0; ++ U8 j= 0; ++ U16 TempData = 0; ++ U32 clk =0; ++ ST_DRV_MSPI_CLK temp; ++ if(u8Chanel >=2) ++ return FALSE; ++ memset(&temp,0,sizeof(ST_DRV_MSPI_CLK)); ++ memset(&clk_buffer,0,sizeof(ST_DRV_MSPI_CLK)*NUM_SPI_CLKRATES); ++ for(i = 0;i < NUM_SPI_CKG;i++)//clk_spi_m_p1 ++ { ++ for(j = 0;j clk_buffer[j].u32ClkSpi) ++ { ++ memcpy(&temp,&clk_buffer[i],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[i],&clk_buffer[j],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[j],&temp,sizeof(ST_DRV_MSPI_CLK)); ++ } ++ } ++ } ++ for(i = 0;i= E_MSPI_MODE_MAX) { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++void HAL_MSPI_SetPerFrameSize(struct mstar_spi *bs,MSPI_CH eChannel, BOOL bDirect, U8 u8BufOffset, U8 u8PerFrameSize) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U8 u8BitOffset = 0; ++ U16 u16regIndex = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ if(bDirect == MSPI_READ_INDEX) { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } else { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ mutex_unlock(&hal_mspi_lock); ++ ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_FRAMECONFIG_ERROR : failed to config transfered bit per buffer ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_FRAMEConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ U8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) { ++ HAL_MSPI_Reset_FrameConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++// add to sync code from utopia for localdimming to set clk ++U32 MDrv_MSPI_SetCLK(struct mstar_spi *bs,U8 u8Channel, U32 u32MspiClk) ++{ ++ int u32SpiClk; ++ u32SpiClk = HAL_MSPI_CLK_Config(bs,(MSPI_CH)u8Channel,u32MspiClk); ++ return u32SpiClk; ++} ++ ++void mspi_config(struct mstar_spi *bs,u8 u8Channel) ++{ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ MDrv_MSPI_Init(bs,u8Channel,bs->u32spi_mode); ++ MDrv_MSPI_DCConfig(bs,u8Channel, &stDCConfig); ++ MDrv_MSPI_SetMode(bs,u8Channel, mspimode); ++ MDrv_MSPI_FRAMEConfig(bs,u8Channel,&stFrameConfig); ++ MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ MDrv_MSPI_ChipSelect(bs,u8Channel,0,0); ++ HAL_MSPI_SetLSB(bs,u8Channel, 0); ++ return; ++} ++ ++#ifdef _EN_MSPI_INTC_ ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_0 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++#if SUPPORT_SPI_1 ++static irqreturn_t mstar_spi_interrupt_spi1(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_1 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_start_transfer]\n"); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ //reinit_completion(&bs->done); ++ bs->tx_buf = tfr->tx_buf; ++ bs->rx_buf = tfr->rx_buf; ++ bs->len = tfr->len; ++ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,1,0); ++ ++ /*if(tfr->speed_hz != NULL){ ++ MDrv_MSPI_SetCLK(_hal_msp.eCurrentCH,tfr->speed_hz); ++ }*/ ++ ++ if(bs->tx_buf != NULL){ ++ mspi_dbgmsg("bs->tx_buf=%x,%x\n",bs->tx_buf[0],bs->tx_buf[1]); ++ ++ if(SUPPORT_DMA) ++ MDrv_MSPI_DMA_Write(bs, spi->master->bus_num,(U8 *)bs->tx_buf,(U16)bs->len); ++ else ++ MDrv_MSPI_Write(bs, _hal_msp.eCurrentCH,(U8 *)bs->tx_buf,(U16)bs->len); ++ } ++ ++ if(bs->rx_buf != NULL){ ++ ++ if(SUPPORT_DMA) ++ MDrv_MSPI_DMA_Read(bs,spi->master->bus_num,(U8 *)bs->rx_buf,(U16)bs->len); ++ else ++ MDrv_MSPI_Read(bs,_hal_msp.eCurrentCH,(U8 *)bs->rx_buf,(U16)bs->len); ++ ++ mspi_dbgmsg("bs->rx_buf=%x,%x\n",bs->rx_buf[0],bs->rx_buf[1]); ++ } ++ ++ //printk("bs->len=%d\n",bs->len); ++ ++ ++ return 0; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_finish_transfer] cs_change=%d\n",cs_change); ++ ++#if 1 ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,0,0); ++ //MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, 0xFFFF); ++ } ++#endif ++ return 0; ++} ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbgmsg("[mstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) { ++ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ mesg->actual_length += bs->len;//(tfr->len - bs->len); ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++ void *pvSpiClk = NULL; ++#endif ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct mstar_spi *bs; ++ int err; ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4spi_bank[5]; ++#ifdef _EN_MSPI_INTC_ ++ int irq; ++#if SUPPORT_SPI_1 ++ struct spi_master *master_spi1; ++ int irq2; ++#endif ++#endif ++#ifdef CONFIG_CAM_CLK ++ u32 SpiClk = 0; ++ CAMCLK_Set_Attribute stSetCfg; ++ CAMCLK_Get_Attribute stGetCfg; ++#else ++ struct clk *clk; ++ struct clk_hw *hw_parent; ++#endif ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#if SUPPORT_SPI_1 ++ master_spi1 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master_spi1) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#endif ++ mspi_dbgmsg( "spi_alloc_master\n"); ++ platform_set_drvdata(pdev, master); ++#if SUPPORT_SPI_1 ++ platform_set_drvdata(pdev, master_spi1); ++#endif ++ ++ master->mode_bits = MSTAR_SPI_MODE_BITS; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->num_chipselect = 3; ++ master->transfer_one_message = mstar_spi_transfer_one; ++ master->dev.of_node = pdev->dev.of_node; ++ master->setup = mstar_spi_setup; ++ master->max_speed_hz = 54000000; ++ master->min_speed_hz = 46875; ++ master->bus_num = 0; ++ ++#if SUPPORT_SPI_1 ++ master_spi1->mode_bits = MSTAR_SPI_MODE_BITS; ++ master_spi1->bits_per_word_mask = SPI_BPW_MASK(8); ++ master_spi1->num_chipselect = 3; ++ master_spi1->transfer_one_message = mstar_spi_transfer_one; ++ master_spi1->dev.of_node = pdev->dev.of_node; ++ master_spi1->setup = mstar_spi_setup; ++ master_spi1->max_speed_hz = 54000000; ++ master_spi1->min_speed_hz = 46875; ++ master_spi1->bus_num = 1; ++#endif ++ ++#ifdef _EN_MSPI_INTC_ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq); ++ if (request_irq(irq, mstar_spi_interrupt, 0, "MSPI_0 interrupt", (void*)master) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt failed"); ++#if SUPPORT_SPI_1 ++ irq2 = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq2); ++ if (request_irq(irq2, mstar_spi_interrupt_spi1, 0, "MSPI_1 interrupt", (void*)master_spi1) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt failed"); ++#endif ++#endif ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4spi_bank, 5); ++ ++ //_hal_msp.eCurrentCH = E_MSPI1; ++ //_hal_msp.VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[_hal_msp.eCurrentCH])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ ++ mspi_dbgmsg("u4IO_PHY_BASE %x\n",u4IO_PHY_BASE); ++ mspi_dbgmsg("u4spi_bank[0] %x\n",u4spi_bank[0]); ++ mspi_dbgmsg("u4spi_bank[1] %x\n",u4spi_bank[1]); ++ mspi_dbgmsg("u4spi_bank[2] %x\n",u4spi_bank[2]); ++ mspi_dbgmsg("u4spi_bank[3] %x\n",u4spi_bank[3]); ++ mspi_dbgmsg("u4spi_bank[4] %x\n",u4spi_bank[4]); ++ ++ bs = spi_master_get_devdata(master); ++ ++#ifdef _EN_MSPI_INTC_ ++ init_completion(&bs->done); ++#endif ++ ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[0])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtMovdmaBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[4])+u4IO_PHY_BASE, BANK_SIZE); ++ ++ bs->u8channel = E_MSPI0; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi0_mode", &bs->u32spi_mode); ++ of_property_read_u32(pdev->dev.of_node, "dma", &bs->use_dma); ++ if(bs->use_dma) ++ { ++ SUPPORT_DMA=true; ++ } ++ ++ /* initialise the hardware */ ++ mspi_config(bs,0); ++ ++#if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(master_spi1); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[1])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtMovdmaBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[4])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI1; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi1_mode", &bs->u32spi_mode); ++ of_property_read_u32(pdev->dev.of_node, "dma", &bs->use_dma); ++ if(bs->use_dma) ++ { ++ SUPPORT_DMA=true; ++ } ++ /* initialise the hardware */ ++ mspi_config(bs,1); ++#endif ++#ifdef CONFIG_CAM_CLK ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", 0,&(SpiClk)); ++ if (!SpiClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ if(CamClkRegister("Spi",SpiClk,&(pvSpiClk))==CAMCLK_RET_OK) ++ { ++ CamClkAttrGet(pvSpiClk,&stGetCfg); ++ CAMCLK_SETPARENT(stSetCfg,stGetCfg.u32Parent[0]); ++ CamClkAttrSet(pvSpiClk,&stSetCfg); ++ CamClkSetOnOff(pvSpiClk,1); ++ } ++ } ++#else ++ //2. set clk ++ clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(clk)) ++ { ++ err = PTR_ERR(clk); ++ mspi_dbgmsg("[%s]: of_clk_get failed\n", __func__); ++ } ++ else ++ { ++ /* select clock mux */ ++ hw_parent = clk_hw_get_parent_by_index(__clk_get_hw(clk), 0); // select clock mux=0 ++ mspi_dbgmsg( "[%s]parent_num:%d parent[0]:%s\n", __func__, ++ clk_hw_get_num_parents(__clk_get_hw(clk)), clk_hw_get_name(hw_parent)); ++ clk_set_parent(clk, hw_parent->clk); ++ ++ clk_prepare_enable(clk); ++ mspi_dbgmsg("[mspi] clk_prepare_enable\n"); ++ } ++#endif ++ err = devm_spi_register_master(&pdev->dev, master); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_0 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#if SUPPORT_SPI_1 ++ err = devm_spi_register_master(&pdev->dev, master_spi1); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_1 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#endif ++ spi_new_device(master, &mstar_info); ++#if SUPPORT_SPI_1 ++ spi_new_device(master_spi1, &mstar_info); ++#endif ++ return 0; ++ ++//out_clk_disable: ++// clk_disable_unprepare(bs->clk); ++out_master_put: ++ spi_master_put(master); ++ mspi_dbgmsg( "((((((((((( err:%d\n", err); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++#ifdef CONFIG_CAM_CLK ++ if(pvSpiClk) ++ { ++ CamClkSetOnOff(pvSpiClk,0); ++ CamClkUnregister(pvSpiClk); ++ } ++#else ++ struct clk *clk; ++ ++#if 0 ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ ++ /* Clear FIFOs, and disable the HW block */ ++ ++ clk_disable_unprepare(bs->clk); ++#endif ++ ++ clk = of_clk_get(pdev->dev.of_node, 0); ++ if (IS_ERR(clk)) ++ { ++ mspi_dbgmsg( "[SAR] Fail to get clk!\n" ); ++ ++ } ++ else ++ { ++ clk_disable_unprepare(clk); ++ clk_put(clk); ++ } ++#endif ++ return 0; ++} ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "sstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/spi/infinity3/Makefile b/drivers/sstar/spi/infinity3/Makefile +new file mode 100755 +index 000000000000..858e8817ca73 +--- /dev/null ++++ b/drivers/sstar/spi/infinity3/Makefile +@@ -0,0 +1,2 @@ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_MS_SPI_INFINITY) += mspi.o +diff --git a/drivers/sstar/spi/infinity3/mspi.c b/drivers/sstar/spi/infinity3/mspi.c +new file mode 100755 +index 000000000000..338ef3db5c20 +--- /dev/null ++++ b/drivers/sstar/spi/infinity3/mspi.c +@@ -0,0 +1,1503 @@ ++/* ++* spi-infinity.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++bool gbInitFlag = false; ++static struct mutex hal_mspi_lock; ++//------------------------------------------------------------------------------------------------- ++// RegbaseAddr Disc ++//------------------------------------------------------------------------------------------------- ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk(args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++ ++#define U8 u8 ++#define U16 u16 ++#define U32 u32 ++#define BOOL bool ++#define TRUE true ++#define FALSE false ++ ++#define SUPPORT_SPI_1 1 ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++ ++#define MSPI0_BANK_ADDR 0x1110 ++#define MSPI1_BANK_ADDR 0x1111 ++#define CLK__BANK_ADDR 0x1038 ++#define CHIPTOP_BANK_ADDR 0x101E ++ ++#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) ++#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) ++#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) ++#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++//------------------------------------------------------------------------------------------------- ++// Hardware Register Capability ++//------------------------------------------------------------------------------------------------- ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_RD00 (0x78) ++#define MSPI_FULL_DEPLUX_RD01 (0x78) ++#define MSPI_FULL_DEPLUX_RD02 (0x79 ++#define MSPI_FULL_DEPLUX_RD03 (0x79) ++#define MSPI_FULL_DEPLUX_RD04 (0x7a) ++#define MSPI_FULL_DEPLUX_RD05 (0x7a) ++#define MSPI_FULL_DEPLUX_RD06 (0x7b) ++#define MSPI_FULL_DEPLUX_RD07 (0x7b) ++ ++#define MSPI_FULL_DEPLUX_RD08 (0x7c) ++#define MSPI_FULL_DEPLUX_RD09 (0x7c) ++#define MSPI_FULL_DEPLUX_RD10 (0x7d) ++#define MSPI_FULL_DEPLUX_RD11 (0x7d) ++#define MSPI_FULL_DEPLUX_RD12 (0x7e) ++#define MSPI_FULL_DEPLUX_RD13 (0x7e) ++#define MSPI_FULL_DEPLUX_RD14 (0x7f) ++#define MSPI_FULL_DEPLUX_RD15 (0x7f) ++ ++//chip select bit map ++ #define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++// clk_mspi0 ++#define MSPI0_CLK_CFG 0x33//bit 2 ~bit 3 ++ #define MSPI0_CLK_108M 0x00 ++ #define MSPI0_CLK_54M 0x04 ++ #define MSPI0_CLK_12M 0x08 ++ #define MSPI0_CLK_MASK 0x0F ++// clk_mspi1 ++#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 ++ #define MSPI1_CLK_108M 0x0000 ++ #define MSPI1_CLK_54M 0x0400 ++ #define MSPI1_CLK_12M 0x0800 ++ #define MSPI1_CLK_MASK 0x0F00 ++ ++//CHITOP 101E mspi mode select ++#define MSPI0_MODE 0x0C //bit0~bit1 ++ #define MSPI0_MODE_MASK 0x03 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ #define MSPI1_MODE_MASK 0x70 ++#define EJTAG_MODE 0xF ++ #define EJTAG_MODE_2 0x02 ++ #define EJTAG_MODE_MASK 0x03 ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile u32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } ++ ++// read 2 byte ++#define MSPI_READ(_reg_) READ_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2)) ++// write 2 byte ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_)) ++//write 2 byte mask ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_), (mask)) ++ ++#define CLK_READ(_reg_) READ_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2)) ++#define CLK_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define CHIPTOP_READ(_reg_) READ_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2)) ++#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) ++#define MAX_CHECK_CNT 2000 ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef struct ++{ ++ u32 u32Clock; ++ u8 u8Clock; ++ bool BClkPolarity; ++ bool BClkPhase; ++ u32 u32MAXClk; ++} MSPI_CLKConfig; ++ ++ ++typedef struct ++{ ++ u8 u8ClkSpi_cfg; ++ u8 u8ClkSpi_DIV; ++ u32 u32ClkSpi; ++}ST_DRV_MSPI_CLK; ++ ++typedef enum ++{ ++ E_MSPI_DBGLV_NONE, //disable all the debug message ++ E_MSPI_DBGLV_INFO, //information ++ E_MSPI_DBGLV_NOTICE, //normal but significant condition ++ E_MSPI_DBGLV_WARNING, //warning conditions ++ E_MSPI_DBGLV_ERR, //error conditions ++ E_MSPI_DBGLV_CRIT, //critical conditions ++ E_MSPI_DBGLV_ALERT, //action must be taken immediately ++ E_MSPI_DBGLV_EMERG, //system is unusable ++ E_MSPI_DBGLV_DEBUG, //debug-level messages ++} MSPI_DbgLv; ++ ++typedef enum _MSPI_ERRORNOn { ++ E_MSPI_OK = 0 ++ ,E_MSPI_INIT_FLOW_ERROR =1 ++ ,E_MSPI_DCCONFIG_ERROR =2 ++ ,E_MSPI_CLKCONFIG_ERROR =4 ++ ,E_MSPI_FRAMECONFIG_ERROR =8 ++ ,E_MSPI_OPERATION_ERROR = 0x10 ++ ,E_MSPI_PARAM_OVERFLOW = 0x20 ++ ,E_MSPI_MMIO_ERROR = 0x40 ++ ,E_MSPI_HW_NOT_SUPPORT = 0x80 ++ ,E_MSPI_NULL ++} MSPI_ErrorNo; ++ ++typedef struct ++{ ++ MSPI_CH eCurrentCH; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++} MSPI_BaseAddr_st; ++ ++static MSPI_BaseAddr_st _hal_msp = { ++ .eCurrentCH = E_MSPI0, ++ //.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR, ++ //.VirtClkBaseAddr = BASE_REG_CLK_ADDR, ++ //.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) ++ ++#define DRV_NAME "spi" ++struct mstar_spi { ++ void __iomem *regs; ++ struct clk *clk; ++ int irq; ++ struct completion done; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char u8channel; ++ int u32spi_mode; ++}; ++ ++static struct spi_board_info mstar_info = { ++ .modalias = "spidev", ++}; ++ ++static void _HAL_MSPI_CheckandSetBaseAddr(MSPI_CH eChannel) ++{ ++ ++#if 0 ++ if(eChannel == _hal_msp.eCurrentCH) ++ { ++ return; ++ } else if(eChannel == E_MSPI0) ++ { ++ _hal_msp.eCurrentCH = E_MSPI0; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi0 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else if(eChannel == E_MSPI1) ++ { ++ _hal_msp.eCurrentCH = E_MSPI1; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI1_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi1 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else ++ { ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("[Mspi Error]FUN:%s MSPI Channel is out of range!\n",__FUNCTION__)); ++ printk("[Mspi Error]FUN: MSPI Channel is out of range!\n"); ++ return ; ++ } ++ ++#endif ++} ++//------------------------------------------------------------------------------ ++/// Description : Reset Frame register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_FrameConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : MSPI interrupt enable ++/// @param bEnable \b OUT: enable or disable mspi interrupt ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_IntEnable(struct mstar_spi *bs,MSPI_CH eChannel,bool bEnable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_Init(struct mstar_spi *bs,MSPI_CH eChannel,u8 u8Mode) ++{ ++ u16 TempData; ++ //init MSP ++ //DEBUG_MSPI(E_MSPI_DBGLV_INFO,printk("HAL_MSPI_Init\n")); ++ mspi_dbgmsg("HAL_MSPI_Init : Channel=%d spi mode=%d\n",eChannel,u8Mode); ++ mutex_init(&hal_mspi_lock); ++ if((eChannel > E_MSPI1) || (u8Mode < 1)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI0) && (u8Mode > 3)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI1) && (u8Mode > 6)) ++ { ++ return; ++ } ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++ if(eChannel == E_MSPI0) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI0_MODE); ++ TempData &= ~(MSPI0_MODE_MASK); ++ TempData |= u8Mode; ++ CHIPTOP_WRITE(MSPI0_MODE,TempData); ++ ++ //Disable jtag mode // IO PAD conflict turn off jtag ++ TempData = CHIPTOP_READ(EJTAG_MODE); ++ if(TempData == EJTAG_MODE_2) { ++ TempData &= ~(EJTAG_MODE_MASK); ++ CHIPTOP_WRITE(EJTAG_MODE,TempData); ++ } ++ } ++ else if (eChannel == E_MSPI1) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI1_MODE); ++ TempData &= ~(MSPI1_MODE_MASK); ++ TempData |= (u8Mode << 4); ++ CHIPTOP_WRITE(MSPI1_MODE,TempData); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return; ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return NONE ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetDcTiming (struct mstar_spi *bs,MSPI_CH eChannel, eDC_config eDCField, U8 u8DCtiming) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ switch(eDCField) { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static void _HAL_MSPI_RWBUFSize(struct mstar_spi *bs,BOOL Direct, U8 Size) ++{ ++ U16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++//------------------------------------------------------------------------------ ++/// Description : check MSPI operation complete ++/// @return TRUE : operation complete ++/// @return FAIL : failed timeout ++//------------------------------------------------------------------------------ ++static U16 _HAL_MSPI_CheckDone(struct mstar_spi *bs) ++{ ++/* ++ U16 uCheckDoneCnt = 0; ++ U16 uDoneFlag = 0; ++ while(uCheckDoneCnt < MAX_CHECK_CNT) { ++ uDoneFlag = MSPI_READ(MSPI_DONE_OFFSET); ++ if(uDoneFlag & MSPI_DONE_FLAG) { ++ printk("Done flag success!!!!!!!!!!!!!!!!!!!!!!!!\n"); ++ return TRUE; ++ } ++ // printk("..."); ++ uCheckDoneCnt++; ++ } ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("ERROR:MSPI Operation Timeout!!!!!\n")); ++ printk("ERROR:MSPI Operation asasTimeout!!!!!\n"); ++ return FALSE; ++*/ ++ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++//------------------------------------------------------------------------------ ++/// Description : Trigger MSPI operation ++/// @return TRUE : operation success ++/// @return FALSE : operation timeout ++//------------------------------------------------------------------------------ ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&bs->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ ++ timeout = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) { ++ mspi_dbgmsg("timeout\n"); ++ //goto out; ++ } ++ ++ // check operation complete ++// if(!_HAL_MSPI_CheckDone()) { ++// return FALSE; ++// } ++ // clear done flag ++// _HAL_MSPI_ClearDone(); ++ // reset read/write buffer size ++// MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return TRUE : read data success ++/// @return FALSE : read data fail ++//------------------------------------------------------------------------------------------------- ++BOOL HAL_MSPI_Read(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U16 i =0, j = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) { ++ j = MAX_READ_BUF_SIZE; ++ } else { ++ j = u16TempBuf; ++ } ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, j); ++ ++ _HAL_MSPI_Trigger(bs); ++ ++ for(u8Index = 0; u8Index < j; u8Index++) { ++ ++ if(u8Index & 1) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } else if(u8Index == (j -1)) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ ++ //printk("******************* read Buf data %x index %d\n",u16TempBuf, u8Index); ++ } ++ pData+= j; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : read data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return TRUE : write data success ++/// @return FALSE : wirte data fail ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Write(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) { ++ if(u8Index & 1) { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",u16TempBuf, u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } else if(u8Index == (u16Size -1)) { ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",pData[u8Index], u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, u16Size); ++ _HAL_MSPI_Trigger(bs); ++ // set write data size ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset CLK register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_CLKConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ U16 Tempbuf; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++U8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set TrStart timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrStart timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrStartSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrStart) ++{ ++ U8 u8TrStartMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset DC register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_DCConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++//------------------------------------------------------------------------------ ++/// Description : SPI chip select enable and disable ++/// @param Enable \b OUT: enable or disable chip select ++//------------------------------------------------------------------------------ ++static void _HAL_MSPI_ChipSelect(struct mstar_spi *bs,BOOL Enable ,U8 eSelect) ++{ ++ U16 regdata = 0; ++ U8 bitmask = 0; ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } else { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set MSPI chip select ++/// @param u8CS \u8 OUT: MSPI chip select ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetChipSelect(struct mstar_spi *bs,MSPI_CH eChannel, BOOL Enable, U8 u8CS) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ _HAL_MSPI_ChipSelect(bs, Enable, u8CS); ++ mutex_unlock(&hal_mspi_lock); ++} ++// add to sync code from utopia for localdimming to set clk ++void MDrv_MSPI_ChipSelect(struct mstar_spi *bs,U8 u8Channel, BOOL Enable, U8 u8CS) ++{ ++ HAL_MSPI_SetChipSelect(bs,(MSPI_CH)u8Channel,Enable,u8CS); ++ return; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_MSPI_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ int ret = 0; ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(U8TempLastFrameCnt) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++//------------------------------------------------------------------------------ ++/// Description : write data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ BOOL ret = false; ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(U8TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 MDrv_MSPI_Init(struct mstar_spi *bs,u8 u8Channel,u8 u8Mode) ++{ ++ u8 errorno = E_MSPI_OK; ++ HAL_MSPI_Init(bs,(MSPI_CH)u8Channel,u8Mode); ++ HAL_MSPI_IntEnable(bs,(MSPI_CH)u8Channel,true); ++ gbInitFlag = true; ++ return errorno; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TrEnd timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrEnd timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrEndSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrEnd) ++{ ++ U8 u8TrEndMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TREND ,TrEnd); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TB timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TB timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TBSetting(struct mstar_spi *bs,U8 u8Channel,U8 TB) ++{ ++ U8 u8TBMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TB ,TB); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TRW timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TRW timging ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TRWSetting(struct mstar_spi *bs,U8 u8Channel,U8 TRW) ++{ ++ U8 u8TRWMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRW ,TRW); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of transfer timing config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_DCCONFIG_ERROR : failed to config transfer timing ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_DCConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_DCConfig *ptDCConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_INIT_FLOW_ERROR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ errnum = _MDrv_DC_TrStartSetting(bs,u8Channel,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TrEndSetting(bs,u8Channel,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TBSetting(bs,u8Channel,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TRWSetting(bs,u8Channel,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++void HAL_MSPI_SetCLKTiming(struct mstar_spi *bs,MSPI_CH eChannel, eCLK_config eCLKField, U8 u8CLKVal) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ switch(eCLKField) { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLSB(struct mstar_spi *bs,MSPI_CH eChannel, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static U8 clk_spi_ckg[3] = {108, 54, 12}; ++static U16 clk_spi_div[8] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static ST_DRV_MSPI_CLK clk_buffer[24]; ++ ++U32 HAL_MSPI_CLK_Config(struct mstar_spi *bs,U8 u8Chanel,U32 u32MspiClk) ++{ ++ U8 i = 0; ++ U8 j= 0; ++ U16 TempData = 0; ++ U32 clk =0; ++ ST_DRV_MSPI_CLK temp; ++ if(u8Chanel >=2) ++ return FALSE; ++ memset(&temp,0,sizeof(ST_DRV_MSPI_CLK)); ++ memset(&clk_buffer,0,sizeof(ST_DRV_MSPI_CLK)*24); ++ for(i = 0;i < 3;i++)//clk_spi_m_p1 ++ { ++ for(j = 0;j<8;j++)//spi div ++ { ++ clk = clk_spi_ckg[i]*1000000; ++ clk_buffer[j+8*i].u8ClkSpi_cfg = i; ++ clk_buffer[j+8*i].u8ClkSpi_DIV = j ; ++ clk_buffer[j+8*i].u32ClkSpi = clk/clk_spi_div[j]; ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ for(j = i;j<24;j++) ++ { ++ if(clk_buffer[i].u32ClkSpi > clk_buffer[j].u32ClkSpi) ++ { ++ memcpy(&temp,&clk_buffer[i],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[i],&clk_buffer[j],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[j],&temp,sizeof(ST_DRV_MSPI_CLK)); ++ } ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ if(u32MspiClk <= clk_buffer[i].u32ClkSpi) ++ { ++ break; ++ } ++ } ++ if (24 == i) ++ { ++ i--; ++ } ++ //match Closer clk ++ if ((i) && ((u32MspiClk - clk_buffer[i-1].u32ClkSpi)<(clk_buffer[i].u32ClkSpi - u32MspiClk))) ++ { ++ i -= 1; ++ } ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_P1 =%d\n",clk_buffer[i].u8ClkSpi_cfg); ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_DIV =%d\n",clk_buffer[i].u8ClkSpi_DIV); ++ mspi_dbgmsg("[Lwc Debug] u32ClkSpi = %d\n",clk_buffer[i].u32ClkSpi); ++ ++ if(u8Chanel == E_MSPI0)//mspi0 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<2); ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ } ++ else if(u8Chanel == E_MSPI1)//mspi1 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<10); ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ } ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= clk_buffer[i].u8ClkSpi_DIV << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return clk_buffer[i].u32ClkSpi; ++} ++ ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi clock setting ++/// @param ptCLKConfig \b OUT struct pointer of clock config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_CLKCONFIG_ERROR : failed to config spi clock ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_SetMode(struct mstar_spi *bs,U8 u8Channel, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++void HAL_MSPI_SetPerFrameSize(struct mstar_spi *bs,MSPI_CH eChannel, BOOL bDirect, U8 u8BufOffset, U8 u8PerFrameSize) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U8 u8BitOffset = 0; ++ U16 u16regIndex = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ if(bDirect == MSPI_READ_INDEX) { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } else { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ mutex_unlock(&hal_mspi_lock); ++ ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_FRAMECONFIG_ERROR : failed to config transfered bit per buffer ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_FRAMEConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ U8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) { ++ HAL_MSPI_Reset_FrameConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++// add to sync code from utopia for localdimming to set clk ++U32 MDrv_MSPI_SetCLK(struct mstar_spi *bs,U8 u8Channel, U32 u32MspiClk) ++{ ++ int u32SpiClk; ++ u32SpiClk = HAL_MSPI_CLK_Config(bs,(MSPI_CH)u8Channel,u32MspiClk); ++ return u32SpiClk; ++} ++ ++void mspi_config(struct mstar_spi *bs,u8 u8Channel) ++{ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ MDrv_MSPI_Init(bs,u8Channel,bs->u32spi_mode); ++ MDrv_MSPI_DCConfig(bs,u8Channel, &stDCConfig); ++ MDrv_MSPI_SetMode(bs,u8Channel, mspimode); ++ MDrv_MSPI_FRAMEConfig(bs,u8Channel,&stFrameConfig); ++ MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ MDrv_MSPI_ChipSelect(bs,u8Channel,0,0); ++ HAL_MSPI_SetLSB(bs,u8Channel, 0); ++ return; ++} ++ ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_0 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static irqreturn_t mstar_spi_interrupt_spi1(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_1 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_start_transfer]\n"); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ //reinit_completion(&bs->done); ++ bs->tx_buf = tfr->tx_buf; ++ bs->rx_buf = tfr->rx_buf; ++ bs->len = tfr->len; ++ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,1,0); ++ ++ /*if(tfr->speed_hz != NULL){ ++ MDrv_MSPI_SetCLK(_hal_msp.eCurrentCH,tfr->speed_hz); ++ }*/ ++ ++ if(bs->tx_buf != NULL){ ++ mspi_dbgmsg("bs->tx_buf=%x,%x\n",bs->tx_buf[0],bs->tx_buf[1]); ++ MDrv_MSPI_Write(bs, _hal_msp.eCurrentCH,(U8 *)bs->tx_buf,(U16)bs->len); ++ } ++ ++ if(bs->rx_buf != NULL){ ++ ++ MDrv_MSPI_Read(bs,_hal_msp.eCurrentCH,(U8 *)bs->rx_buf,(U16)bs->len); ++ ++ mspi_dbgmsg("bs->rx_buf=%x,%x\n",bs->rx_buf[0],bs->rx_buf[1]); ++ } ++ ++ //printk("bs->len=%d\n",bs->len); ++ ++ ++ return 0; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_finish_transfer] cs_change=%d\n",cs_change); ++ ++#if 1 ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,0,0); ++ //MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, 0xFFFF); ++ } ++#endif ++ return 0; ++} ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbgmsg("[mstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) { ++ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ mesg->actual_length += bs->len;//(tfr->len - bs->len); ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_master *master_spi1; ++ struct mstar_spi *bs; ++ int err; ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4spi_bank[4]; ++ int irq,irq2; ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#if SUPPORT_SPI_1 ++ master_spi1 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master_spi1) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#endif ++ mspi_dbgmsg( "spi_alloc_master\n"); ++ platform_set_drvdata(pdev, master); ++#if SUPPORT_SPI_1 ++ platform_set_drvdata(pdev, master_spi1); ++#endif ++ ++ master->mode_bits = MSTAR_SPI_MODE_BITS; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->num_chipselect = 3; ++ master->transfer_one_message = mstar_spi_transfer_one; ++ master->dev.of_node = pdev->dev.of_node; ++ master->setup = mstar_spi_setup; ++ master->max_speed_hz = 54000000; ++ master->min_speed_hz = 46875; ++ master->bus_num = 0; ++ ++#if SUPPORT_SPI_1 ++ master_spi1->mode_bits = MSTAR_SPI_MODE_BITS; ++ master_spi1->bits_per_word_mask = SPI_BPW_MASK(8); ++ master_spi1->num_chipselect = 3; ++ master_spi1->transfer_one_message = mstar_spi_transfer_one; ++ master_spi1->dev.of_node = pdev->dev.of_node; ++ master_spi1->setup = mstar_spi_setup; ++ master_spi1->max_speed_hz = 54000000; ++ master_spi1->min_speed_hz = 46875; ++ master_spi1->bus_num = 1; ++#endif ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq); ++ if (request_irq(irq, mstar_spi_interrupt, 0, "MSPI_0 interrupt", (void*)master) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt failed"); ++#if SUPPORT_SPI_1 ++ irq2 = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq2); ++ if (request_irq(irq2, mstar_spi_interrupt_spi1, 0, "MSPI_1 interrupt", (void*)master_spi1) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt failed"); ++#endif ++ ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4spi_bank, 4); ++ ++ _hal_msp.eCurrentCH = E_MSPI1; ++ //_hal_msp.VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[_hal_msp.eCurrentCH])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ ++ mspi_dbgmsg("u4IO_PHY_BASE %x\n",u4IO_PHY_BASE); ++ mspi_dbgmsg("u4spi_bank[0] %x\n",u4spi_bank[0]); ++ mspi_dbgmsg("u4spi_bank[1] %x\n",u4spi_bank[1]); ++ mspi_dbgmsg("u4spi_bank[2] %x\n",u4spi_bank[2]); ++ mspi_dbgmsg("u4spi_bank[3] %x\n",u4spi_bank[3]); ++ ++ bs = spi_master_get_devdata(master); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[0])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI0; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi0_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,0); ++ ++#if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(master_spi1); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[1])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI1; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi1_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,1); ++#endif ++ ++ ++ err = devm_spi_register_master(&pdev->dev, master); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_0 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#if SUPPORT_SPI_1 ++ err = devm_spi_register_master(&pdev->dev, master_spi1); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_1 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#endif ++ spi_new_device(master, &mstar_info); ++#if SUPPORT_SPI_1 ++ spi_new_device(master_spi1, &mstar_info); ++#endif ++ return 0; ++ ++//out_clk_disable: ++// clk_disable_unprepare(bs->clk); ++out_master_put: ++ spi_master_put(master); ++ mspi_dbgmsg( "((((((((((( err:%d\n", err); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++ ++#if 0 ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ ++ /* Clear FIFOs, and disable the HW block */ ++ ++ clk_disable_unprepare(bs->clk); ++#endif ++ return 0; ++} ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "sstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/spi/infinity5/Makefile b/drivers/sstar/spi/infinity5/Makefile +new file mode 100755 +index 000000000000..858e8817ca73 +--- /dev/null ++++ b/drivers/sstar/spi/infinity5/Makefile +@@ -0,0 +1,2 @@ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_MS_SPI_INFINITY) += mspi.o +diff --git a/drivers/sstar/spi/infinity5/mspi.c b/drivers/sstar/spi/infinity5/mspi.c +new file mode 100755 +index 000000000000..14031fb9fbc0 +--- /dev/null ++++ b/drivers/sstar/spi/infinity5/mspi.c +@@ -0,0 +1,1535 @@ ++/* ++* spi-infinity.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++bool gbInitFlag = false; ++static struct mutex hal_mspi_lock; ++//------------------------------------------------------------------------------------------------- ++// RegbaseAddr Disc ++//------------------------------------------------------------------------------------------------- ++//#define WAIT_DONE_BY_ISR ++#define WAIT_DONE_BY_BUSY_POLL ++ ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk(args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++ ++#define U8 u8 ++#define U16 u16 ++#define U32 u32 ++#define BOOL bool ++#define TRUE true ++#define FALSE false ++ ++#define SUPPORT_SPI_1 1 ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++ ++#define MSPI0_BANK_ADDR 0x1110 ++#define MSPI1_BANK_ADDR 0x1111 ++#define CLK__BANK_ADDR 0x1038 ++#define CHIPTOP_BANK_ADDR 0x101E ++ ++#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) ++#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) ++#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) ++#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++//------------------------------------------------------------------------------------------------- ++// Hardware Register Capability ++//------------------------------------------------------------------------------------------------- ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_RD00 (0x78) ++#define MSPI_FULL_DEPLUX_RD01 (0x78) ++#define MSPI_FULL_DEPLUX_RD02 (0x79 ++#define MSPI_FULL_DEPLUX_RD03 (0x79) ++#define MSPI_FULL_DEPLUX_RD04 (0x7a) ++#define MSPI_FULL_DEPLUX_RD05 (0x7a) ++#define MSPI_FULL_DEPLUX_RD06 (0x7b) ++#define MSPI_FULL_DEPLUX_RD07 (0x7b) ++ ++#define MSPI_FULL_DEPLUX_RD08 (0x7c) ++#define MSPI_FULL_DEPLUX_RD09 (0x7c) ++#define MSPI_FULL_DEPLUX_RD10 (0x7d) ++#define MSPI_FULL_DEPLUX_RD11 (0x7d) ++#define MSPI_FULL_DEPLUX_RD12 (0x7e) ++#define MSPI_FULL_DEPLUX_RD13 (0x7e) ++#define MSPI_FULL_DEPLUX_RD14 (0x7f) ++#define MSPI_FULL_DEPLUX_RD15 (0x7f) ++ ++//chip select bit map ++ #define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++// clk_mspi0 ++#define MSPI0_CLK_CFG 0x33//bit 2 ~bit 3 ++ #define MSPI0_CLK_108M 0x00 ++ #define MSPI0_CLK_54M 0x04 ++ #define MSPI0_CLK_12M 0x08 ++ #define MSPI0_CLK_MASK 0x0F ++// clk_mspi1 ++#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 ++ #define MSPI1_CLK_108M 0x0000 ++ #define MSPI1_CLK_54M 0x0400 ++ #define MSPI1_CLK_12M 0x0800 ++ #define MSPI1_CLK_MASK 0x0F00 ++ ++//CHITOP 101E mspi mode select ++#define MSPI0_MODE 0x0C //bit0~bit1 ++ #define MSPI0_MODE_MASK 0x03 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ #define MSPI1_MODE_MASK 0x70 ++#define EJTAG_MODE 0xF ++ #define EJTAG_MODE_2 0x02 ++ #define EJTAG_MODE_MASK 0x03 ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile u32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } ++ ++// read 2 byte ++#define MSPI_READ(_reg_) READ_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2)) ++// write 2 byte ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_)) ++//write 2 byte mask ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_), (mask)) ++ ++#define CLK_READ(_reg_) READ_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2)) ++#define CLK_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define CHIPTOP_READ(_reg_) READ_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2)) ++#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) ++#define MAX_CHECK_CNT 2000 ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef struct ++{ ++ u32 u32Clock; ++ u8 u8Clock; ++ bool BClkPolarity; ++ bool BClkPhase; ++ u32 u32MAXClk; ++} MSPI_CLKConfig; ++ ++ ++typedef struct ++{ ++ u8 u8ClkSpi_cfg; ++ u8 u8ClkSpi_DIV; ++ u32 u32ClkSpi; ++}ST_DRV_MSPI_CLK; ++ ++typedef enum ++{ ++ E_MSPI_DBGLV_NONE, //disable all the debug message ++ E_MSPI_DBGLV_INFO, //information ++ E_MSPI_DBGLV_NOTICE, //normal but significant condition ++ E_MSPI_DBGLV_WARNING, //warning conditions ++ E_MSPI_DBGLV_ERR, //error conditions ++ E_MSPI_DBGLV_CRIT, //critical conditions ++ E_MSPI_DBGLV_ALERT, //action must be taken immediately ++ E_MSPI_DBGLV_EMERG, //system is unusable ++ E_MSPI_DBGLV_DEBUG, //debug-level messages ++} MSPI_DbgLv; ++ ++typedef enum _MSPI_ERRORNOn { ++ E_MSPI_OK = 0 ++ ,E_MSPI_INIT_FLOW_ERROR =1 ++ ,E_MSPI_DCCONFIG_ERROR =2 ++ ,E_MSPI_CLKCONFIG_ERROR =4 ++ ,E_MSPI_FRAMECONFIG_ERROR =8 ++ ,E_MSPI_OPERATION_ERROR = 0x10 ++ ,E_MSPI_PARAM_OVERFLOW = 0x20 ++ ,E_MSPI_MMIO_ERROR = 0x40 ++ ,E_MSPI_HW_NOT_SUPPORT = 0x80 ++ ,E_MSPI_NULL ++} MSPI_ErrorNo; ++ ++typedef struct ++{ ++ MSPI_CH eCurrentCH; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++} MSPI_BaseAddr_st; ++ ++static MSPI_BaseAddr_st _hal_msp = { ++ .eCurrentCH = E_MSPI0, ++ //.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR, ++ //.VirtClkBaseAddr = BASE_REG_CLK_ADDR, ++ //.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) ++ ++#define DRV_NAME "spi" ++struct mstar_spi { ++ void __iomem *regs; ++ struct clk *clk; ++ int irq; ++ struct completion done; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char u8channel; ++ int u32spi_mode; ++}; ++ ++static struct spi_board_info mstar_info = { ++ .modalias = "spidev", ++}; ++ ++static void _HAL_MSPI_CheckandSetBaseAddr(MSPI_CH eChannel) ++{ ++ ++#if 0 ++ if(eChannel == _hal_msp.eCurrentCH) ++ { ++ return; ++ } else if(eChannel == E_MSPI0) ++ { ++ _hal_msp.eCurrentCH = E_MSPI0; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi0 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else if(eChannel == E_MSPI1) ++ { ++ _hal_msp.eCurrentCH = E_MSPI1; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI1_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi1 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else ++ { ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("[Mspi Error]FUN:%s MSPI Channel is out of range!\n",__FUNCTION__)); ++ printk("[Mspi Error]FUN: MSPI Channel is out of range!\n"); ++ return ; ++ } ++ ++#endif ++} ++//------------------------------------------------------------------------------ ++/// Description : Reset Frame register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_FrameConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : MSPI interrupt enable ++/// @param bEnable \b OUT: enable or disable mspi interrupt ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_IntEnable(struct mstar_spi *bs,MSPI_CH eChannel,bool bEnable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_Init(struct mstar_spi *bs,MSPI_CH eChannel,u8 u8Mode) ++{ ++ u16 TempData; ++ //init MSP ++ //DEBUG_MSPI(E_MSPI_DBGLV_INFO,printk("HAL_MSPI_Init\n")); ++ mspi_dbgmsg("HAL_MSPI_Init : Channel=%d spi mode=%d\n",eChannel,u8Mode); ++ mutex_init(&hal_mspi_lock); ++ if((eChannel > E_MSPI1) || (u8Mode < 1)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI0) && (u8Mode > 3)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI1) && (u8Mode > 6)) ++ { ++ return; ++ } ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++ if(eChannel == E_MSPI0) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI0_MODE); ++ TempData &= ~(MSPI0_MODE_MASK); ++ TempData |= u8Mode; ++ CHIPTOP_WRITE(MSPI0_MODE,TempData); ++ ++ //Disable jtag mode // IO PAD conflict turn off jtag ++ TempData = CHIPTOP_READ(EJTAG_MODE); ++ if(TempData == EJTAG_MODE_2) { ++ TempData &= ~(EJTAG_MODE_MASK); ++ CHIPTOP_WRITE(EJTAG_MODE,TempData); ++ } ++ } ++ else if (eChannel == E_MSPI1) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI1_MODE); ++ TempData &= ~(MSPI1_MODE_MASK); ++ TempData |= (u8Mode << 4); ++ CHIPTOP_WRITE(MSPI1_MODE,TempData); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return; ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return NONE ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetDcTiming (struct mstar_spi *bs,MSPI_CH eChannel, eDC_config eDCField, U8 u8DCtiming) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ switch(eDCField) { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static void _HAL_MSPI_RWBUFSize(struct mstar_spi *bs,BOOL Direct, U8 Size) ++{ ++ U16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++//------------------------------------------------------------------------------ ++/// Description : check MSPI operation complete ++/// @return TRUE : operation complete ++/// @return FAIL : failed timeout ++//------------------------------------------------------------------------------ ++static U16 _HAL_MSPI_CheckDone(struct mstar_spi *bs) ++{ ++/* ++ U16 uCheckDoneCnt = 0; ++ U16 uDoneFlag = 0; ++ while(uCheckDoneCnt < MAX_CHECK_CNT) { ++ uDoneFlag = MSPI_READ(MSPI_DONE_OFFSET); ++ if(uDoneFlag & MSPI_DONE_FLAG) { ++ printk("Done flag success!!!!!!!!!!!!!!!!!!!!!!!!\n"); ++ return TRUE; ++ } ++ // printk("..."); ++ uCheckDoneCnt++; ++ } ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("ERROR:MSPI Operation Timeout!!!!!\n")); ++ printk("ERROR:MSPI Operation asasTimeout!!!!!\n"); ++ return FALSE; ++*/ ++ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++//------------------------------------------------------------------------------ ++/// Description : Trigger MSPI operation ++/// @return TRUE : operation success ++/// @return FALSE : operation timeout ++//------------------------------------------------------------------------------ ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++#ifdef WAIT_DONE_BY_BUSY_POLL ++ unsigned long start; ++#endif ++ unsigned long timeout; ++ ++ // trigger operation ++#ifdef WAIT_DONE_BY_ISR ++ reinit_completion(&bs->done); ++#endif ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++#ifdef WAIT_DONE_BY_ISR ++ timeout = wait_for_completion_timeout(&bs->done, msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++#endif ++ ++#ifdef WAIT_DONE_BY_BUSY_POLL ++ start = jiffies; ++ timeout = start + msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS); ++ while(!(_HAL_MSPI_CheckDone(bs) & 1)) { ++ //usleep_range(5, 10); ++ if(time_after_eq(jiffies, timeout)) ++ { ++ timeout = 0; ++ break; ++ } ++ } ++ _HAL_MSPI_ClearDone(); ++#endif ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) { ++ mspi_dbgmsg("timeout\n"); ++ //goto out; ++ } ++ ++ // check operation complete ++// if(!_HAL_MSPI_CheckDone()) { ++// return FALSE; ++// } ++ // clear done flag ++// _HAL_MSPI_ClearDone(); ++ // reset read/write buffer size ++// MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return TRUE : read data success ++/// @return FALSE : read data fail ++//------------------------------------------------------------------------------------------------- ++BOOL HAL_MSPI_Read(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U16 i =0, j = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) { ++ j = MAX_READ_BUF_SIZE; ++ } else { ++ j = u16TempBuf; ++ } ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, j); ++ ++ _HAL_MSPI_Trigger(bs); ++ ++ for(u8Index = 0; u8Index < j; u8Index++) { ++ ++ if(u8Index & 1) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } else if(u8Index == (j -1)) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ ++ //printk("******************* read Buf data %x index %d\n",u16TempBuf, u8Index); ++ } ++ pData+= j; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : read data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return TRUE : write data success ++/// @return FALSE : wirte data fail ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Write(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) { ++ if(u8Index & 1) { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",u16TempBuf, u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } else if(u8Index == (u16Size -1)) { ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",pData[u8Index], u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, u16Size); ++ _HAL_MSPI_Trigger(bs); ++ // set write data size ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset CLK register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_CLKConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ U16 Tempbuf; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++U8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set TrStart timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrStart timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrStartSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrStart) ++{ ++ U8 u8TrStartMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset DC register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_DCConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++//------------------------------------------------------------------------------ ++/// Description : SPI chip select enable and disable ++/// @param Enable \b OUT: enable or disable chip select ++//------------------------------------------------------------------------------ ++static void _HAL_MSPI_ChipSelect(struct mstar_spi *bs,BOOL Enable ,U8 eSelect) ++{ ++ U16 regdata = 0; ++ U8 bitmask = 0; ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } else { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set MSPI chip select ++/// @param u8CS \u8 OUT: MSPI chip select ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetChipSelect(struct mstar_spi *bs,MSPI_CH eChannel, BOOL Enable, U8 u8CS) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ _HAL_MSPI_ChipSelect(bs, Enable, u8CS); ++ mutex_unlock(&hal_mspi_lock); ++} ++// add to sync code from utopia for localdimming to set clk ++void MDrv_MSPI_ChipSelect(struct mstar_spi *bs,U8 u8Channel, BOOL Enable, U8 u8CS) ++{ ++ HAL_MSPI_SetChipSelect(bs,(MSPI_CH)u8Channel,Enable,u8CS); ++ return; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_MSPI_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ int ret = 0; ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(U8TempLastFrameCnt) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++//------------------------------------------------------------------------------ ++/// Description : write data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ BOOL ret = false; ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(U8TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 MDrv_MSPI_Init(struct mstar_spi *bs,u8 u8Channel,u8 u8Mode) ++{ ++ u8 errorno = E_MSPI_OK; ++ HAL_MSPI_Init(bs,(MSPI_CH)u8Channel,u8Mode); ++ HAL_MSPI_IntEnable(bs,(MSPI_CH)u8Channel,true); ++ gbInitFlag = true; ++ return errorno; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TrEnd timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrEnd timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrEndSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrEnd) ++{ ++ U8 u8TrEndMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TREND ,TrEnd); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TB timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TB timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TBSetting(struct mstar_spi *bs,U8 u8Channel,U8 TB) ++{ ++ U8 u8TBMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TB ,TB); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TRW timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TRW timging ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TRWSetting(struct mstar_spi *bs,U8 u8Channel,U8 TRW) ++{ ++ U8 u8TRWMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRW ,TRW); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of transfer timing config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_DCCONFIG_ERROR : failed to config transfer timing ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_DCConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_DCConfig *ptDCConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_INIT_FLOW_ERROR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ errnum = _MDrv_DC_TrStartSetting(bs,u8Channel,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TrEndSetting(bs,u8Channel,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TBSetting(bs,u8Channel,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TRWSetting(bs,u8Channel,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++void HAL_MSPI_SetCLKTiming(struct mstar_spi *bs,MSPI_CH eChannel, eCLK_config eCLKField, U8 u8CLKVal) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ switch(eCLKField) { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLSB(struct mstar_spi *bs,MSPI_CH eChannel, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static U8 clk_spi_ckg[3] = {108, 54, 12}; ++static U16 clk_spi_div[8] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static ST_DRV_MSPI_CLK clk_buffer[24]; ++ ++U32 HAL_MSPI_CLK_Config(struct mstar_spi *bs,U8 u8Chanel,U32 u32MspiClk) ++{ ++ U8 i = 0; ++ U8 j= 0; ++ U16 TempData = 0; ++ U32 clk =0; ++ ST_DRV_MSPI_CLK temp; ++ if(u8Chanel >=2) ++ return FALSE; ++ memset(&temp,0,sizeof(ST_DRV_MSPI_CLK)); ++ memset(&clk_buffer,0,sizeof(ST_DRV_MSPI_CLK)*24); ++ for(i = 0;i < 3;i++)//clk_spi_m_p1 ++ { ++ for(j = 0;j<8;j++)//spi div ++ { ++ clk = clk_spi_ckg[i]*1000000; ++ clk_buffer[j+8*i].u8ClkSpi_cfg = i; ++ clk_buffer[j+8*i].u8ClkSpi_DIV = j ; ++ clk_buffer[j+8*i].u32ClkSpi = clk/clk_spi_div[j]; ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ for(j = i;j<24;j++) ++ { ++ if(clk_buffer[i].u32ClkSpi > clk_buffer[j].u32ClkSpi) ++ { ++ memcpy(&temp,&clk_buffer[i],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[i],&clk_buffer[j],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[j],&temp,sizeof(ST_DRV_MSPI_CLK)); ++ } ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ if(u32MspiClk <= clk_buffer[i].u32ClkSpi) ++ { ++ break; ++ } ++ } ++ if (24 == i) ++ { ++ i--; ++ } ++ //match Closer clk ++ if ((i) && ((u32MspiClk - clk_buffer[i-1].u32ClkSpi)<(clk_buffer[i].u32ClkSpi - u32MspiClk))) ++ { ++ i -= 1; ++ } ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_P1 =%d\n",clk_buffer[i].u8ClkSpi_cfg); ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_DIV =%d\n",clk_buffer[i].u8ClkSpi_DIV); ++ mspi_dbgmsg("[Lwc Debug] u32ClkSpi = %d\n",clk_buffer[i].u32ClkSpi); ++ ++ if(u8Chanel == E_MSPI0)//mspi0 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<2); ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ } ++ else if(u8Chanel == E_MSPI1)//mspi1 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<10); ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ } ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= clk_buffer[i].u8ClkSpi_DIV << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return clk_buffer[i].u32ClkSpi; ++} ++ ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi clock setting ++/// @param ptCLKConfig \b OUT struct pointer of clock config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_CLKCONFIG_ERROR : failed to config spi clock ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_SetMode(struct mstar_spi *bs,U8 u8Channel, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++void HAL_MSPI_SetPerFrameSize(struct mstar_spi *bs,MSPI_CH eChannel, BOOL bDirect, U8 u8BufOffset, U8 u8PerFrameSize) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U8 u8BitOffset = 0; ++ U16 u16regIndex = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ if(bDirect == MSPI_READ_INDEX) { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } else { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ mutex_unlock(&hal_mspi_lock); ++ ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_FRAMECONFIG_ERROR : failed to config transfered bit per buffer ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_FRAMEConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ U8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) { ++ HAL_MSPI_Reset_FrameConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++// add to sync code from utopia for localdimming to set clk ++U32 MDrv_MSPI_SetCLK(struct mstar_spi *bs,U8 u8Channel, U32 u32MspiClk) ++{ ++ int u32SpiClk; ++ u32SpiClk = HAL_MSPI_CLK_Config(bs,(MSPI_CH)u8Channel,u32MspiClk); ++ return u32SpiClk; ++} ++ ++void mspi_config(struct mstar_spi *bs,u8 u8Channel) ++{ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ MDrv_MSPI_Init(bs,u8Channel,bs->u32spi_mode); ++ MDrv_MSPI_DCConfig(bs,u8Channel, &stDCConfig); ++ MDrv_MSPI_SetMode(bs,u8Channel, mspimode); ++ MDrv_MSPI_FRAMEConfig(bs,u8Channel,&stFrameConfig); ++ MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ MDrv_MSPI_ChipSelect(bs,u8Channel,0,0); ++ HAL_MSPI_SetLSB(bs,u8Channel, 0); ++ return; ++} ++ ++#ifdef WAIT_DONE_BY_ISR ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_0 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static irqreturn_t mstar_spi_interrupt_spi1(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_1 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_start_transfer]\n"); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ //reinit_completion(&bs->done); ++ bs->tx_buf = tfr->tx_buf; ++ bs->rx_buf = tfr->rx_buf; ++ bs->len = tfr->len; ++ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,1,0); ++ ++ /*if(tfr->speed_hz != NULL){ ++ MDrv_MSPI_SetCLK(_hal_msp.eCurrentCH,tfr->speed_hz); ++ }*/ ++ ++ if(bs->tx_buf != NULL){ ++ mspi_dbgmsg("bs->tx_buf=%x,%x\n",bs->tx_buf[0],bs->tx_buf[1]); ++ MDrv_MSPI_Write(bs, _hal_msp.eCurrentCH,(U8 *)bs->tx_buf,(U16)bs->len); ++ } ++ ++ if(bs->rx_buf != NULL){ ++ ++ MDrv_MSPI_Read(bs,_hal_msp.eCurrentCH,(U8 *)bs->rx_buf,(U16)bs->len); ++ ++ mspi_dbgmsg("bs->rx_buf=%x,%x\n",bs->rx_buf[0],bs->rx_buf[1]); ++ } ++ ++ //printk("bs->len=%d\n",bs->len); ++ ++ ++ return 0; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_finish_transfer] cs_change=%d\n",cs_change); ++ ++#if 1 ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,0,0); ++ //MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, 0xFFFF); ++ } ++#endif ++ return 0; ++} ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbgmsg("[mstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) ++ { ++ if (1) ++ { ++ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ } ++ mesg->actual_length += bs->len;//(tfr->len - bs->len); ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_master *master_spi1; ++ struct mstar_spi *bs; ++ int err; ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4spi_bank[4]; ++ int irq,irq2; ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#if SUPPORT_SPI_1 ++ master_spi1 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master_spi1) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#endif ++ mspi_dbgmsg( "spi_alloc_master\n"); ++ platform_set_drvdata(pdev, master); ++#if SUPPORT_SPI_1 ++ platform_set_drvdata(pdev, master_spi1); ++#endif ++ ++ master->mode_bits = MSTAR_SPI_MODE_BITS; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->num_chipselect = 3; ++ master->transfer_one_message = mstar_spi_transfer_one; ++ master->dev.of_node = pdev->dev.of_node; ++ master->setup = mstar_spi_setup; ++ master->max_speed_hz = 54000000; ++ master->min_speed_hz = 46875; ++ master->bus_num = 0; ++ ++#if SUPPORT_SPI_1 ++ master_spi1->mode_bits = MSTAR_SPI_MODE_BITS; ++ master_spi1->bits_per_word_mask = SPI_BPW_MASK(8); ++ master_spi1->num_chipselect = 3; ++ master_spi1->transfer_one_message = mstar_spi_transfer_one; ++ master_spi1->dev.of_node = pdev->dev.of_node; ++ master_spi1->setup = mstar_spi_setup; ++ master_spi1->max_speed_hz = 54000000; ++ master_spi1->min_speed_hz = 46875; ++ master_spi1->bus_num = 1; ++#endif ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++#ifdef WAIT_DONE_BY_ISR ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq); ++ if (request_irq(irq, mstar_spi_interrupt, 0, "MSPI_0 interrupt", (void*)master) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt failed"); ++#endif ++#if SUPPORT_SPI_1 ++ irq2 = irq_of_parse_and_map(pdev->dev.of_node, 1); ++#ifdef WAIT_DONE_BY_ISR ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq2); ++ if (request_irq(irq2, mstar_spi_interrupt_spi1, 0, "MSPI_1 interrupt", (void*)master_spi1) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt failed"); ++#endif ++#endif ++ ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4spi_bank, 4); ++ ++ _hal_msp.eCurrentCH = E_MSPI1; ++ //_hal_msp.VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[_hal_msp.eCurrentCH])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ ++ mspi_dbgmsg("u4IO_PHY_BASE %x\n",u4IO_PHY_BASE); ++ mspi_dbgmsg("u4spi_bank[0] %x\n",u4spi_bank[0]); ++ mspi_dbgmsg("u4spi_bank[1] %x\n",u4spi_bank[1]); ++ mspi_dbgmsg("u4spi_bank[2] %x\n",u4spi_bank[2]); ++ mspi_dbgmsg("u4spi_bank[3] %x\n",u4spi_bank[3]); ++ ++ bs = spi_master_get_devdata(master); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[0])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI0; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi0_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,0); ++ ++#if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(master_spi1); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[1])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI1; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi1_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,1); ++#endif ++ ++ ++ err = devm_spi_register_master(&pdev->dev, master); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_0 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#if SUPPORT_SPI_1 ++ err = devm_spi_register_master(&pdev->dev, master_spi1); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_1 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#endif ++ spi_new_device(master, &mstar_info); ++#if SUPPORT_SPI_1 ++ spi_new_device(master_spi1, &mstar_info); ++#endif ++ return 0; ++ ++//out_clk_disable: ++// clk_disable_unprepare(bs->clk); ++out_master_put: ++ spi_master_put(master); ++ mspi_dbgmsg( "((((((((((( err:%d\n", err); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++ ++#if 0 ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ ++ /* Clear FIFOs, and disable the HW block */ ++ ++ clk_disable_unprepare(bs->clk); ++#endif ++ return 0; ++} ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "sstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/spi/infinity6/Makefile b/drivers/sstar/spi/infinity6/Makefile +new file mode 100755 +index 000000000000..858e8817ca73 +--- /dev/null ++++ b/drivers/sstar/spi/infinity6/Makefile +@@ -0,0 +1,2 @@ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_MS_SPI_INFINITY) += mspi.o +diff --git a/drivers/sstar/spi/infinity6/mspi.c b/drivers/sstar/spi/infinity6/mspi.c +new file mode 100755 +index 000000000000..338ef3db5c20 +--- /dev/null ++++ b/drivers/sstar/spi/infinity6/mspi.c +@@ -0,0 +1,1503 @@ ++/* ++* spi-infinity.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++bool gbInitFlag = false; ++static struct mutex hal_mspi_lock; ++//------------------------------------------------------------------------------------------------- ++// RegbaseAddr Disc ++//------------------------------------------------------------------------------------------------- ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk(args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++ ++#define U8 u8 ++#define U16 u16 ++#define U32 u32 ++#define BOOL bool ++#define TRUE true ++#define FALSE false ++ ++#define SUPPORT_SPI_1 1 ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++ ++#define MSPI0_BANK_ADDR 0x1110 ++#define MSPI1_BANK_ADDR 0x1111 ++#define CLK__BANK_ADDR 0x1038 ++#define CHIPTOP_BANK_ADDR 0x101E ++ ++#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) ++#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) ++#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) ++#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++//------------------------------------------------------------------------------------------------- ++// Hardware Register Capability ++//------------------------------------------------------------------------------------------------- ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_RD00 (0x78) ++#define MSPI_FULL_DEPLUX_RD01 (0x78) ++#define MSPI_FULL_DEPLUX_RD02 (0x79 ++#define MSPI_FULL_DEPLUX_RD03 (0x79) ++#define MSPI_FULL_DEPLUX_RD04 (0x7a) ++#define MSPI_FULL_DEPLUX_RD05 (0x7a) ++#define MSPI_FULL_DEPLUX_RD06 (0x7b) ++#define MSPI_FULL_DEPLUX_RD07 (0x7b) ++ ++#define MSPI_FULL_DEPLUX_RD08 (0x7c) ++#define MSPI_FULL_DEPLUX_RD09 (0x7c) ++#define MSPI_FULL_DEPLUX_RD10 (0x7d) ++#define MSPI_FULL_DEPLUX_RD11 (0x7d) ++#define MSPI_FULL_DEPLUX_RD12 (0x7e) ++#define MSPI_FULL_DEPLUX_RD13 (0x7e) ++#define MSPI_FULL_DEPLUX_RD14 (0x7f) ++#define MSPI_FULL_DEPLUX_RD15 (0x7f) ++ ++//chip select bit map ++ #define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++// clk_mspi0 ++#define MSPI0_CLK_CFG 0x33//bit 2 ~bit 3 ++ #define MSPI0_CLK_108M 0x00 ++ #define MSPI0_CLK_54M 0x04 ++ #define MSPI0_CLK_12M 0x08 ++ #define MSPI0_CLK_MASK 0x0F ++// clk_mspi1 ++#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 ++ #define MSPI1_CLK_108M 0x0000 ++ #define MSPI1_CLK_54M 0x0400 ++ #define MSPI1_CLK_12M 0x0800 ++ #define MSPI1_CLK_MASK 0x0F00 ++ ++//CHITOP 101E mspi mode select ++#define MSPI0_MODE 0x0C //bit0~bit1 ++ #define MSPI0_MODE_MASK 0x03 ++#define MSPI1_MODE 0x0C //bit4~bit5 ++ #define MSPI1_MODE_MASK 0x70 ++#define EJTAG_MODE 0xF ++ #define EJTAG_MODE_2 0x02 ++ #define EJTAG_MODE_MASK 0x03 ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile u32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } ++ ++// read 2 byte ++#define MSPI_READ(_reg_) READ_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2)) ++// write 2 byte ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_)) ++//write 2 byte mask ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_), (mask)) ++ ++#define CLK_READ(_reg_) READ_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2)) ++#define CLK_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define CHIPTOP_READ(_reg_) READ_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2)) ++#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) ++#define MAX_CHECK_CNT 2000 ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef struct ++{ ++ u32 u32Clock; ++ u8 u8Clock; ++ bool BClkPolarity; ++ bool BClkPhase; ++ u32 u32MAXClk; ++} MSPI_CLKConfig; ++ ++ ++typedef struct ++{ ++ u8 u8ClkSpi_cfg; ++ u8 u8ClkSpi_DIV; ++ u32 u32ClkSpi; ++}ST_DRV_MSPI_CLK; ++ ++typedef enum ++{ ++ E_MSPI_DBGLV_NONE, //disable all the debug message ++ E_MSPI_DBGLV_INFO, //information ++ E_MSPI_DBGLV_NOTICE, //normal but significant condition ++ E_MSPI_DBGLV_WARNING, //warning conditions ++ E_MSPI_DBGLV_ERR, //error conditions ++ E_MSPI_DBGLV_CRIT, //critical conditions ++ E_MSPI_DBGLV_ALERT, //action must be taken immediately ++ E_MSPI_DBGLV_EMERG, //system is unusable ++ E_MSPI_DBGLV_DEBUG, //debug-level messages ++} MSPI_DbgLv; ++ ++typedef enum _MSPI_ERRORNOn { ++ E_MSPI_OK = 0 ++ ,E_MSPI_INIT_FLOW_ERROR =1 ++ ,E_MSPI_DCCONFIG_ERROR =2 ++ ,E_MSPI_CLKCONFIG_ERROR =4 ++ ,E_MSPI_FRAMECONFIG_ERROR =8 ++ ,E_MSPI_OPERATION_ERROR = 0x10 ++ ,E_MSPI_PARAM_OVERFLOW = 0x20 ++ ,E_MSPI_MMIO_ERROR = 0x40 ++ ,E_MSPI_HW_NOT_SUPPORT = 0x80 ++ ,E_MSPI_NULL ++} MSPI_ErrorNo; ++ ++typedef struct ++{ ++ MSPI_CH eCurrentCH; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++} MSPI_BaseAddr_st; ++ ++static MSPI_BaseAddr_st _hal_msp = { ++ .eCurrentCH = E_MSPI0, ++ //.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR, ++ //.VirtClkBaseAddr = BASE_REG_CLK_ADDR, ++ //.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) ++ ++#define DRV_NAME "spi" ++struct mstar_spi { ++ void __iomem *regs; ++ struct clk *clk; ++ int irq; ++ struct completion done; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char u8channel; ++ int u32spi_mode; ++}; ++ ++static struct spi_board_info mstar_info = { ++ .modalias = "spidev", ++}; ++ ++static void _HAL_MSPI_CheckandSetBaseAddr(MSPI_CH eChannel) ++{ ++ ++#if 0 ++ if(eChannel == _hal_msp.eCurrentCH) ++ { ++ return; ++ } else if(eChannel == E_MSPI0) ++ { ++ _hal_msp.eCurrentCH = E_MSPI0; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi0 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else if(eChannel == E_MSPI1) ++ { ++ _hal_msp.eCurrentCH = E_MSPI1; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI1_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi1 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else ++ { ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("[Mspi Error]FUN:%s MSPI Channel is out of range!\n",__FUNCTION__)); ++ printk("[Mspi Error]FUN: MSPI Channel is out of range!\n"); ++ return ; ++ } ++ ++#endif ++} ++//------------------------------------------------------------------------------ ++/// Description : Reset Frame register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_FrameConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : MSPI interrupt enable ++/// @param bEnable \b OUT: enable or disable mspi interrupt ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_IntEnable(struct mstar_spi *bs,MSPI_CH eChannel,bool bEnable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_Init(struct mstar_spi *bs,MSPI_CH eChannel,u8 u8Mode) ++{ ++ u16 TempData; ++ //init MSP ++ //DEBUG_MSPI(E_MSPI_DBGLV_INFO,printk("HAL_MSPI_Init\n")); ++ mspi_dbgmsg("HAL_MSPI_Init : Channel=%d spi mode=%d\n",eChannel,u8Mode); ++ mutex_init(&hal_mspi_lock); ++ if((eChannel > E_MSPI1) || (u8Mode < 1)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI0) && (u8Mode > 3)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI1) && (u8Mode > 6)) ++ { ++ return; ++ } ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++ if(eChannel == E_MSPI0) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI0_MODE); ++ TempData &= ~(MSPI0_MODE_MASK); ++ TempData |= u8Mode; ++ CHIPTOP_WRITE(MSPI0_MODE,TempData); ++ ++ //Disable jtag mode // IO PAD conflict turn off jtag ++ TempData = CHIPTOP_READ(EJTAG_MODE); ++ if(TempData == EJTAG_MODE_2) { ++ TempData &= ~(EJTAG_MODE_MASK); ++ CHIPTOP_WRITE(EJTAG_MODE,TempData); ++ } ++ } ++ else if (eChannel == E_MSPI1) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI1_MODE); ++ TempData &= ~(MSPI1_MODE_MASK); ++ TempData |= (u8Mode << 4); ++ CHIPTOP_WRITE(MSPI1_MODE,TempData); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return; ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return NONE ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetDcTiming (struct mstar_spi *bs,MSPI_CH eChannel, eDC_config eDCField, U8 u8DCtiming) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ switch(eDCField) { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static void _HAL_MSPI_RWBUFSize(struct mstar_spi *bs,BOOL Direct, U8 Size) ++{ ++ U16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++//------------------------------------------------------------------------------ ++/// Description : check MSPI operation complete ++/// @return TRUE : operation complete ++/// @return FAIL : failed timeout ++//------------------------------------------------------------------------------ ++static U16 _HAL_MSPI_CheckDone(struct mstar_spi *bs) ++{ ++/* ++ U16 uCheckDoneCnt = 0; ++ U16 uDoneFlag = 0; ++ while(uCheckDoneCnt < MAX_CHECK_CNT) { ++ uDoneFlag = MSPI_READ(MSPI_DONE_OFFSET); ++ if(uDoneFlag & MSPI_DONE_FLAG) { ++ printk("Done flag success!!!!!!!!!!!!!!!!!!!!!!!!\n"); ++ return TRUE; ++ } ++ // printk("..."); ++ uCheckDoneCnt++; ++ } ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("ERROR:MSPI Operation Timeout!!!!!\n")); ++ printk("ERROR:MSPI Operation asasTimeout!!!!!\n"); ++ return FALSE; ++*/ ++ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++//------------------------------------------------------------------------------ ++/// Description : Trigger MSPI operation ++/// @return TRUE : operation success ++/// @return FALSE : operation timeout ++//------------------------------------------------------------------------------ ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&bs->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ ++ timeout = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) { ++ mspi_dbgmsg("timeout\n"); ++ //goto out; ++ } ++ ++ // check operation complete ++// if(!_HAL_MSPI_CheckDone()) { ++// return FALSE; ++// } ++ // clear done flag ++// _HAL_MSPI_ClearDone(); ++ // reset read/write buffer size ++// MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return TRUE : read data success ++/// @return FALSE : read data fail ++//------------------------------------------------------------------------------------------------- ++BOOL HAL_MSPI_Read(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U16 i =0, j = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) { ++ j = MAX_READ_BUF_SIZE; ++ } else { ++ j = u16TempBuf; ++ } ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, j); ++ ++ _HAL_MSPI_Trigger(bs); ++ ++ for(u8Index = 0; u8Index < j; u8Index++) { ++ ++ if(u8Index & 1) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf >> 8; ++ pData[u8Index-1] = u16TempBuf & 0xFF; ++ } else if(u8Index == (j -1)) { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("read Buf data %x index %d\n",u16TempBuf, u8Index)); ++ pData[u8Index] = u16TempBuf & 0xFF; ++ } ++ ++ //printk("******************* read Buf data %x index %d\n",u16TempBuf, u8Index); ++ } ++ pData+= j; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : read data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return TRUE : write data success ++/// @return FALSE : wirte data fail ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Write(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) { ++ if(u8Index & 1) { ++ u16TempBuf = (pData[u8Index] << 8) | pData[u8Index-1]; ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",u16TempBuf, u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } else if(u8Index == (u16Size -1)) { ++ //DEBUG_MSPI(E_MSPI_DBGLV_DEBUG,printk("write Buf data %x index %d\n",pData[u8Index], u8Index)); ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index]); ++ } ++ } ++ ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, u16Size); ++ _HAL_MSPI_Trigger(bs); ++ // set write data size ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset CLK register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_CLKConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ U16 Tempbuf; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++U8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set TrStart timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrStart timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrStartSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrStart) ++{ ++ U8 u8TrStartMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset DC register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_DCConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++//------------------------------------------------------------------------------ ++/// Description : SPI chip select enable and disable ++/// @param Enable \b OUT: enable or disable chip select ++//------------------------------------------------------------------------------ ++static void _HAL_MSPI_ChipSelect(struct mstar_spi *bs,BOOL Enable ,U8 eSelect) ++{ ++ U16 regdata = 0; ++ U8 bitmask = 0; ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } else { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set MSPI chip select ++/// @param u8CS \u8 OUT: MSPI chip select ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetChipSelect(struct mstar_spi *bs,MSPI_CH eChannel, BOOL Enable, U8 u8CS) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ _HAL_MSPI_ChipSelect(bs, Enable, u8CS); ++ mutex_unlock(&hal_mspi_lock); ++} ++// add to sync code from utopia for localdimming to set clk ++void MDrv_MSPI_ChipSelect(struct mstar_spi *bs,U8 u8Channel, BOOL Enable, U8 u8CS) ++{ ++ HAL_MSPI_SetChipSelect(bs,(MSPI_CH)u8Channel,Enable,u8CS); ++ return; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_MSPI_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ int ret = 0; ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(U8TempLastFrameCnt) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++//------------------------------------------------------------------------------ ++/// Description : write data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ BOOL ret = false; ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(U8TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 MDrv_MSPI_Init(struct mstar_spi *bs,u8 u8Channel,u8 u8Mode) ++{ ++ u8 errorno = E_MSPI_OK; ++ HAL_MSPI_Init(bs,(MSPI_CH)u8Channel,u8Mode); ++ HAL_MSPI_IntEnable(bs,(MSPI_CH)u8Channel,true); ++ gbInitFlag = true; ++ return errorno; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TrEnd timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrEnd timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrEndSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrEnd) ++{ ++ U8 u8TrEndMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TREND ,TrEnd); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TB timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TB timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TBSetting(struct mstar_spi *bs,U8 u8Channel,U8 TB) ++{ ++ U8 u8TBMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TB ,TB); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TRW timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TRW timging ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TRWSetting(struct mstar_spi *bs,U8 u8Channel,U8 TRW) ++{ ++ U8 u8TRWMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRW ,TRW); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of transfer timing config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_DCCONFIG_ERROR : failed to config transfer timing ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_DCConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_DCConfig *ptDCConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_INIT_FLOW_ERROR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ errnum = _MDrv_DC_TrStartSetting(bs,u8Channel,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TrEndSetting(bs,u8Channel,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TBSetting(bs,u8Channel,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TRWSetting(bs,u8Channel,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++void HAL_MSPI_SetCLKTiming(struct mstar_spi *bs,MSPI_CH eChannel, eCLK_config eCLKField, U8 u8CLKVal) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ switch(eCLKField) { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLSB(struct mstar_spi *bs,MSPI_CH eChannel, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static U8 clk_spi_ckg[3] = {108, 54, 12}; ++static U16 clk_spi_div[8] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static ST_DRV_MSPI_CLK clk_buffer[24]; ++ ++U32 HAL_MSPI_CLK_Config(struct mstar_spi *bs,U8 u8Chanel,U32 u32MspiClk) ++{ ++ U8 i = 0; ++ U8 j= 0; ++ U16 TempData = 0; ++ U32 clk =0; ++ ST_DRV_MSPI_CLK temp; ++ if(u8Chanel >=2) ++ return FALSE; ++ memset(&temp,0,sizeof(ST_DRV_MSPI_CLK)); ++ memset(&clk_buffer,0,sizeof(ST_DRV_MSPI_CLK)*24); ++ for(i = 0;i < 3;i++)//clk_spi_m_p1 ++ { ++ for(j = 0;j<8;j++)//spi div ++ { ++ clk = clk_spi_ckg[i]*1000000; ++ clk_buffer[j+8*i].u8ClkSpi_cfg = i; ++ clk_buffer[j+8*i].u8ClkSpi_DIV = j ; ++ clk_buffer[j+8*i].u32ClkSpi = clk/clk_spi_div[j]; ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ for(j = i;j<24;j++) ++ { ++ if(clk_buffer[i].u32ClkSpi > clk_buffer[j].u32ClkSpi) ++ { ++ memcpy(&temp,&clk_buffer[i],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[i],&clk_buffer[j],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[j],&temp,sizeof(ST_DRV_MSPI_CLK)); ++ } ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ if(u32MspiClk <= clk_buffer[i].u32ClkSpi) ++ { ++ break; ++ } ++ } ++ if (24 == i) ++ { ++ i--; ++ } ++ //match Closer clk ++ if ((i) && ((u32MspiClk - clk_buffer[i-1].u32ClkSpi)<(clk_buffer[i].u32ClkSpi - u32MspiClk))) ++ { ++ i -= 1; ++ } ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_P1 =%d\n",clk_buffer[i].u8ClkSpi_cfg); ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_DIV =%d\n",clk_buffer[i].u8ClkSpi_DIV); ++ mspi_dbgmsg("[Lwc Debug] u32ClkSpi = %d\n",clk_buffer[i].u32ClkSpi); ++ ++ if(u8Chanel == E_MSPI0)//mspi0 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<2); ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ } ++ else if(u8Chanel == E_MSPI1)//mspi1 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<10); ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ } ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= clk_buffer[i].u8ClkSpi_DIV << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return clk_buffer[i].u32ClkSpi; ++} ++ ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi clock setting ++/// @param ptCLKConfig \b OUT struct pointer of clock config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_CLKCONFIG_ERROR : failed to config spi clock ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_SetMode(struct mstar_spi *bs,U8 u8Channel, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++void HAL_MSPI_SetPerFrameSize(struct mstar_spi *bs,MSPI_CH eChannel, BOOL bDirect, U8 u8BufOffset, U8 u8PerFrameSize) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U8 u8BitOffset = 0; ++ U16 u16regIndex = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ if(bDirect == MSPI_READ_INDEX) { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } else { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ mutex_unlock(&hal_mspi_lock); ++ ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_FRAMECONFIG_ERROR : failed to config transfered bit per buffer ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_FRAMEConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ U8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) { ++ HAL_MSPI_Reset_FrameConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++// add to sync code from utopia for localdimming to set clk ++U32 MDrv_MSPI_SetCLK(struct mstar_spi *bs,U8 u8Channel, U32 u32MspiClk) ++{ ++ int u32SpiClk; ++ u32SpiClk = HAL_MSPI_CLK_Config(bs,(MSPI_CH)u8Channel,u32MspiClk); ++ return u32SpiClk; ++} ++ ++void mspi_config(struct mstar_spi *bs,u8 u8Channel) ++{ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ MDrv_MSPI_Init(bs,u8Channel,bs->u32spi_mode); ++ MDrv_MSPI_DCConfig(bs,u8Channel, &stDCConfig); ++ MDrv_MSPI_SetMode(bs,u8Channel, mspimode); ++ MDrv_MSPI_FRAMEConfig(bs,u8Channel,&stFrameConfig); ++ MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ MDrv_MSPI_ChipSelect(bs,u8Channel,0,0); ++ HAL_MSPI_SetLSB(bs,u8Channel, 0); ++ return; ++} ++ ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_0 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static irqreturn_t mstar_spi_interrupt_spi1(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_1 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_start_transfer]\n"); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ //reinit_completion(&bs->done); ++ bs->tx_buf = tfr->tx_buf; ++ bs->rx_buf = tfr->rx_buf; ++ bs->len = tfr->len; ++ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,1,0); ++ ++ /*if(tfr->speed_hz != NULL){ ++ MDrv_MSPI_SetCLK(_hal_msp.eCurrentCH,tfr->speed_hz); ++ }*/ ++ ++ if(bs->tx_buf != NULL){ ++ mspi_dbgmsg("bs->tx_buf=%x,%x\n",bs->tx_buf[0],bs->tx_buf[1]); ++ MDrv_MSPI_Write(bs, _hal_msp.eCurrentCH,(U8 *)bs->tx_buf,(U16)bs->len); ++ } ++ ++ if(bs->rx_buf != NULL){ ++ ++ MDrv_MSPI_Read(bs,_hal_msp.eCurrentCH,(U8 *)bs->rx_buf,(U16)bs->len); ++ ++ mspi_dbgmsg("bs->rx_buf=%x,%x\n",bs->rx_buf[0],bs->rx_buf[1]); ++ } ++ ++ //printk("bs->len=%d\n",bs->len); ++ ++ ++ return 0; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_finish_transfer] cs_change=%d\n",cs_change); ++ ++#if 1 ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,0,0); ++ //MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, 0xFFFF); ++ } ++#endif ++ return 0; ++} ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbgmsg("[mstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) { ++ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ mesg->actual_length += bs->len;//(tfr->len - bs->len); ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_master *master_spi1; ++ struct mstar_spi *bs; ++ int err; ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4spi_bank[4]; ++ int irq,irq2; ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#if SUPPORT_SPI_1 ++ master_spi1 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master_spi1) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#endif ++ mspi_dbgmsg( "spi_alloc_master\n"); ++ platform_set_drvdata(pdev, master); ++#if SUPPORT_SPI_1 ++ platform_set_drvdata(pdev, master_spi1); ++#endif ++ ++ master->mode_bits = MSTAR_SPI_MODE_BITS; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); ++ master->num_chipselect = 3; ++ master->transfer_one_message = mstar_spi_transfer_one; ++ master->dev.of_node = pdev->dev.of_node; ++ master->setup = mstar_spi_setup; ++ master->max_speed_hz = 54000000; ++ master->min_speed_hz = 46875; ++ master->bus_num = 0; ++ ++#if SUPPORT_SPI_1 ++ master_spi1->mode_bits = MSTAR_SPI_MODE_BITS; ++ master_spi1->bits_per_word_mask = SPI_BPW_MASK(8); ++ master_spi1->num_chipselect = 3; ++ master_spi1->transfer_one_message = mstar_spi_transfer_one; ++ master_spi1->dev.of_node = pdev->dev.of_node; ++ master_spi1->setup = mstar_spi_setup; ++ master_spi1->max_speed_hz = 54000000; ++ master_spi1->min_speed_hz = 46875; ++ master_spi1->bus_num = 1; ++#endif ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq); ++ if (request_irq(irq, mstar_spi_interrupt, 0, "MSPI_0 interrupt", (void*)master) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt failed"); ++#if SUPPORT_SPI_1 ++ irq2 = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq2); ++ if (request_irq(irq2, mstar_spi_interrupt_spi1, 0, "MSPI_1 interrupt", (void*)master_spi1) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt failed"); ++#endif ++ ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4spi_bank, 4); ++ ++ _hal_msp.eCurrentCH = E_MSPI1; ++ //_hal_msp.VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[_hal_msp.eCurrentCH])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ ++ mspi_dbgmsg("u4IO_PHY_BASE %x\n",u4IO_PHY_BASE); ++ mspi_dbgmsg("u4spi_bank[0] %x\n",u4spi_bank[0]); ++ mspi_dbgmsg("u4spi_bank[1] %x\n",u4spi_bank[1]); ++ mspi_dbgmsg("u4spi_bank[2] %x\n",u4spi_bank[2]); ++ mspi_dbgmsg("u4spi_bank[3] %x\n",u4spi_bank[3]); ++ ++ bs = spi_master_get_devdata(master); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[0])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI0; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi0_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,0); ++ ++#if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(master_spi1); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[1])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI1; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi1_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,1); ++#endif ++ ++ ++ err = devm_spi_register_master(&pdev->dev, master); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_0 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#if SUPPORT_SPI_1 ++ err = devm_spi_register_master(&pdev->dev, master_spi1); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_1 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#endif ++ spi_new_device(master, &mstar_info); ++#if SUPPORT_SPI_1 ++ spi_new_device(master_spi1, &mstar_info); ++#endif ++ return 0; ++ ++//out_clk_disable: ++// clk_disable_unprepare(bs->clk); ++out_master_put: ++ spi_master_put(master); ++ mspi_dbgmsg( "((((((((((( err:%d\n", err); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++ ++#if 0 ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ ++ /* Clear FIFOs, and disable the HW block */ ++ ++ clk_disable_unprepare(bs->clk); ++#endif ++ return 0; ++} ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "sstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/spi/infinity6b0/Makefile b/drivers/sstar/spi/infinity6b0/Makefile +new file mode 100755 +index 000000000000..254d6b5f177d +--- /dev/null ++++ b/drivers/sstar/spi/infinity6b0/Makefile +@@ -0,0 +1,5 @@ ++# SPI master controller drivers (bus) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_MS_SPI_INFINITY) += mspi.o +diff --git a/drivers/sstar/spi/infinity6b0/mspi.c b/drivers/sstar/spi/infinity6b0/mspi.c +new file mode 100755 +index 000000000000..aca8dece85b4 +--- /dev/null ++++ b/drivers/sstar/spi/infinity6b0/mspi.c +@@ -0,0 +1,1784 @@ ++/* ++* spi-infinity.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "registers.h" ++#include ++#include ++#include "ms_platform.h" ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++bool gbInitFlag = false; ++static struct mutex hal_mspi_lock; ++bool SUPPORT_DMA = false; ++//------------------------------------------------------------------------------------------------- ++// RegbaseAddr Disc ++//------------------------------------------------------------------------------------------------- ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk(args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++ ++#define SUPPORT_SPI_1 1 ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++ ++#define MSPI0_BANK_ADDR 0x1110 ++#define MSPI1_BANK_ADDR 0x1111 ++#define CLK__BANK_ADDR 0x1038 ++#define CHIPTOP_BANK_ADDR 0x101E ++#define MOVDMA_BANK_ADDR 0x100B ++ ++#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) ++#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) ++#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) ++#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++//------------------------------------------------------------------------------------------------- ++// Hardware Register Capability ++//------------------------------------------------------------------------------------------------- ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_RD00 (0x78) ++#define MSPI_FULL_DEPLUX_RD01 (0x78) ++#define MSPI_FULL_DEPLUX_RD02 (0x79 ++#define MSPI_FULL_DEPLUX_RD03 (0x79) ++#define MSPI_FULL_DEPLUX_RD04 (0x7a) ++#define MSPI_FULL_DEPLUX_RD05 (0x7a) ++#define MSPI_FULL_DEPLUX_RD06 (0x7b) ++#define MSPI_FULL_DEPLUX_RD07 (0x7b) ++ ++#define MSPI_FULL_DEPLUX_RD08 (0x7c) ++#define MSPI_FULL_DEPLUX_RD09 (0x7c) ++#define MSPI_FULL_DEPLUX_RD10 (0x7d) ++#define MSPI_FULL_DEPLUX_RD11 (0x7d) ++#define MSPI_FULL_DEPLUX_RD12 (0x7e) ++#define MSPI_FULL_DEPLUX_RD13 (0x7e) ++#define MSPI_FULL_DEPLUX_RD14 (0x7f) ++#define MSPI_FULL_DEPLUX_RD15 (0x7f) ++ ++//chip select bit map ++ #define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++// clk_mspi0 ++#define MSPI0_CLK_CFG 0x33//bit 2 ~bit 3 ++ #define MSPI0_CLK_108M 0x00 ++ #define MSPI0_CLK_54M 0x04 ++ #define MSPI0_CLK_12M 0x08 ++ #define MSPI0_CLK_MASK 0x0F ++// clk_mspi1 ++#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 ++ #define MSPI1_CLK_108M 0x0000 ++ #define MSPI1_CLK_54M 0x0400 ++ #define MSPI1_CLK_12M 0x0800 ++ #define MSPI1_CLK_MASK 0x0F00 ++ ++//CHITOP 101E mspi mode select ++#define MSPI0_MODE 0x68 //bit0~bit1 ++ #define MSPI0_MODE_MASK 0x07 ++#define MSPI1_MODE 0x68 //bit4~bit5 ++ #define MSPI1_MODE_MASK 0x70 ++#define EJTAG_MODE 0x60 ++ #define EJTAG_MODE_1 0x0080 ++ #define EJTAG_MODE_MASK 0x0180 ++ ++//MOVDMA 100B ++#define MOV_DMA_SRC_ADDR_L 0x03 ++#define MOV_DMA_SRC_ADDR_H 0x04 ++#define MOV_DMA_DST_ADDR_L 0x05 ++#define MOV_DMA_DST_ADDR_H 0x06 ++#define MOV_DMA_BYTE_CNT_L 0x07 ++#define MOV_DMA_BYTE_CNT_H 0x08 ++#define DMA_MOVE0_ENABLE 0x00 ++#define DMA_RW 0x50 //0 for dma write to device, 1 for dma read from device ++ #define DMA_READ 0x01 ++ #define DMA_WRITE 0x00 ++#define DMA_DEVICE_MODE 0x51 ++#define DMA_DEVICE_SEL 0x52 ++ ++//spi dma ++#define MSPI_DMA_DATA_LENGTH_L 0x30 ++#define MSPI_DMA_DATA_LENGTH_H 0x31 ++#define MSPI_DMA_ENABLE 0x32 ++#define MSPI_DMA_RW_MODE 0x33 ++ #define MSPI_DMA_WRITE 0x00 ++ #define MSPI_DMA_READ 0x01 ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile u32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } ++ ++// read 2 byte ++#define MSPI_READ(_reg_) READ_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2)) ++// write 2 byte ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_)) ++//write 2 byte mask ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_), (mask)) ++ ++#define CLK_READ(_reg_) READ_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2)) ++#define CLK_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define CHIPTOP_READ(_reg_) READ_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2)) ++#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define MOVDMA_READ(_reg_) READ_WORD(bs->VirtMovdmaBaseAddr + ((_reg_)<<2)) ++#define MOVDMA_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMovdmaBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) ++#define MAX_CHECK_CNT 2000 ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++#define MSPI_MAX_SUPPORT_BITS 16 ++ ++#define SPI_MIU0_BUS_BASE ARM_MIU0_BUS_BASE ++#define SPI_MIU1_BUS_BASE ARM_MIU1_BUS_BASE ++ ++ ++#ifdef CONFIG_SS_PROFILING_TIME ++extern void recode_timestamp(int mark, const char* name); ++extern unsigned int read_timestamp(void); ++extern void recode_timestamp_ext(int mark, const char* name, unsigned int timestamp); ++#endif ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef struct ++{ ++ u32 u32Clock; ++ u8 u8Clock; ++ bool BClkPolarity; ++ bool BClkPhase; ++ u32 u32MAXClk; ++} MSPI_CLKConfig; ++ ++ ++typedef struct ++{ ++ u8 u8ClkSpi_cfg; ++ u8 u8ClkSpi_DIV; ++ u32 u32ClkSpi; ++}ST_DRV_MSPI_CLK; ++ ++typedef enum ++{ ++ E_MSPI_DBGLV_NONE, //disable all the debug message ++ E_MSPI_DBGLV_INFO, //information ++ E_MSPI_DBGLV_NOTICE, //normal but significant condition ++ E_MSPI_DBGLV_WARNING, //warning conditions ++ E_MSPI_DBGLV_ERR, //error conditions ++ E_MSPI_DBGLV_CRIT, //critical conditions ++ E_MSPI_DBGLV_ALERT, //action must be taken immediately ++ E_MSPI_DBGLV_EMERG, //system is unusable ++ E_MSPI_DBGLV_DEBUG, //debug-level messages ++} MSPI_DbgLv; ++ ++typedef enum _MSPI_ERRORNOn { ++ E_MSPI_OK = 0 ++ ,E_MSPI_INIT_FLOW_ERROR =1 ++ ,E_MSPI_DCCONFIG_ERROR =2 ++ ,E_MSPI_CLKCONFIG_ERROR =4 ++ ,E_MSPI_FRAMECONFIG_ERROR =8 ++ ,E_MSPI_OPERATION_ERROR = 0x10 ++ ,E_MSPI_PARAM_OVERFLOW = 0x20 ++ ,E_MSPI_MMIO_ERROR = 0x40 ++ ,E_MSPI_HW_NOT_SUPPORT = 0x80 ++ ,E_MSPI_NULL ++} MSPI_ErrorNo; ++ ++typedef struct ++{ ++ MSPI_CH eCurrentCH; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char *VirtMovdmaBaseAddr; ++} MSPI_BaseAddr_st; ++ ++static MSPI_BaseAddr_st _hal_msp = { ++ .eCurrentCH = E_MSPI0, ++ //.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR, ++ //.VirtClkBaseAddr = BASE_REG_CLK_ADDR, ++ //.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++}; ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) ++ ++#define DRV_NAME "spi" ++struct mstar_spi { ++ void __iomem *regs; ++ struct clk *clk; ++ int irq; ++ int use_dma; ++ struct completion done; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char *VirtMovdmaBaseAddr; ++ char u8channel; ++ int u32spi_mode; ++ u32 bits_per_word; ++ u32 word_size; ++}; ++ ++static struct spi_board_info mstar_info = { ++ .modalias = "spidev", ++}; ++ ++static void _HAL_MSPI_CheckandSetBaseAddr(MSPI_CH eChannel) ++{ ++ ++#if 0 ++ if(eChannel == _hal_msp.eCurrentCH) ++ { ++ return; ++ } else if(eChannel == E_MSPI0) ++ { ++ _hal_msp.eCurrentCH = E_MSPI0; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi0 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else if(eChannel == E_MSPI1) ++ { ++ _hal_msp.eCurrentCH = E_MSPI1; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI1_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi1 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else ++ { ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("[Mspi Error]FUN:%s MSPI Channel is out of range!\n",__FUNCTION__)); ++ printk("[Mspi Error]FUN: MSPI Channel is out of range!\n"); ++ return ; ++ } ++ ++#endif ++} ++//------------------------------------------------------------------------------ ++/// Description : Reset Frame register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_FrameConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : MSPI interrupt enable ++/// @param bEnable \b OUT: enable or disable mspi interrupt ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_IntEnable(struct mstar_spi *bs,MSPI_CH eChannel,bool bEnable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_Init(struct mstar_spi *bs,MSPI_CH eChannel,u8 u8Mode) ++{ ++ u16 TempData; ++ //init MSP ++ //DEBUG_MSPI(E_MSPI_DBGLV_INFO,printk("HAL_MSPI_Init\n")); ++ mspi_dbgmsg("HAL_MSPI_Init : Channel=%d spi mode=%d\n",eChannel,u8Mode); ++ mutex_init(&hal_mspi_lock); ++ if((eChannel > E_MSPI1) || (u8Mode < 1)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI0) && (u8Mode > 3)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI1) && (u8Mode > 6)) ++ { ++ return; ++ } ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++ if(eChannel == E_MSPI0) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= MSPI0_CLK_108M; ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI0_MODE); ++ TempData &= ~(MSPI0_MODE_MASK); ++ TempData |= u8Mode; ++ CHIPTOP_WRITE(MSPI0_MODE,TempData); ++ ++ //Disable jtag mode // IO PAD conflict turn off jtag ++ TempData = CHIPTOP_READ(EJTAG_MODE); ++ if(TempData == EJTAG_MODE_1) { ++ TempData &= ~(EJTAG_MODE_MASK); ++ CHIPTOP_WRITE(EJTAG_MODE,TempData); ++ } ++ } ++ else if (eChannel == E_MSPI1) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI1_MODE); ++ TempData &= ~(MSPI1_MODE_MASK); ++ TempData |= (u8Mode << 4); ++ CHIPTOP_WRITE(MSPI1_MODE,TempData); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return; ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return NONE ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetDcTiming (struct mstar_spi *bs,MSPI_CH eChannel, eDC_config eDCField, U8 u8DCtiming) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ switch(eDCField) { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static void _HAL_MSPI_RWBUFSize(struct mstar_spi *bs,BOOL Direct, U8 Size) ++{ ++ U16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++//------------------------------------------------------------------------------ ++/// Description : check MSPI operation complete ++/// @return TRUE : operation complete ++/// @return FAIL : failed timeout ++//------------------------------------------------------------------------------ ++static U16 _HAL_MSPI_CheckDone(struct mstar_spi *bs) ++{ ++/* ++ U16 uCheckDoneCnt = 0; ++ U16 uDoneFlag = 0; ++ while(uCheckDoneCnt < MAX_CHECK_CNT) { ++ uDoneFlag = MSPI_READ(MSPI_DONE_OFFSET); ++ if(uDoneFlag & MSPI_DONE_FLAG) { ++ printk("Done flag success!!!!!!!!!!!!!!!!!!!!!!!!\n"); ++ return TRUE; ++ } ++ // printk("..."); ++ uCheckDoneCnt++; ++ } ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("ERROR:MSPI Operation Timeout!!!!!\n")); ++ printk("ERROR:MSPI Operation asasTimeout!!!!!\n"); ++ return FALSE; ++*/ ++ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++//------------------------------------------------------------------------------ ++/// Description : Trigger MSPI operation ++/// @return TRUE : operation success ++/// @return FALSE : operation timeout ++//------------------------------------------------------------------------------ ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&bs->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ ++ timeout = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) { ++ mspi_dbgmsg("timeout\n"); ++ //goto out; ++ } ++ ++ // check operation complete ++// if(!_HAL_MSPI_CheckDone()) { ++// return FALSE; ++// } ++ // clear done flag ++// _HAL_MSPI_ClearDone(); ++ // reset read/write buffer size ++// MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return TRUE : read data success ++/// @return FALSE : read data fail ++//------------------------------------------------------------------------------------------------- ++BOOL HAL_MSPI_Read(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U16 i =0, j = 0; ++ u8 shift; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & 0x1); ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) { ++ j = MAX_READ_BUF_SIZE; ++ } else { ++ j = u16TempBuf; ++ } ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, j); ++ ++ _HAL_MSPI_Trigger(bs); ++ ++ for(u8Index = 0; u8Index < j; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ if (isMsbBitMode) ++ { ++ //MSB MODE ++ if (bs->bits_per_word <= 8) ++ { ++ //printk("u16TempBuf 0x%x\n",u16TempBuf); ++ shift = bs->bits_per_word; ++ pData[u8Index] = (u16TempBuf >> 8) & ((0x1 << shift) - 0x1); ++ pData[u8Index-1] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ else //bits_per_word=9~15 ++ { ++ shift = bs->bits_per_word - 8; ++ pData[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ pData[u8Index-1] = u16TempBuf >> 8; ++ } ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ else if(u8Index == (j -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ shift = bs->bits_per_word; ++ pData[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ } ++ pData+= j; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : read data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return TRUE : write data success ++/// @return FALSE : wirte data fail ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Write(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ u8 shift = 0; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & 0x1); ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ if(bs->bits_per_word <= 8) ++ { ++ shift = (isMsbBitMode) ? (8 - bs->bits_per_word) : 0; ++ u16TempBuf = (pData[u8Index] << (shift + 8)) | (pData[u8Index-1] << shift); ++ } ++ else ++ { ++ shift = 16 - bs->bits_per_word; ++ if(isMsbBitMode) ++ { ++ u16TempBuf = (pData[u8Index] << shift) | (pData[u8Index-1] << 8); ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ shift = 8 - bs->bits_per_word; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index] << shift); ++ } ++ } ++ ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, u16Size); ++ _HAL_MSPI_Trigger(bs); ++ // set write data size ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset CLK register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_CLKConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ U16 Tempbuf; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++U8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set TrStart timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrStart timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrStartSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrStart) ++{ ++ U8 u8TrStartMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset DC register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_DCConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++//------------------------------------------------------------------------------ ++/// Description : SPI chip select enable and disable ++/// @param Enable \b OUT: enable or disable chip select ++//------------------------------------------------------------------------------ ++static void _HAL_MSPI_ChipSelect(struct mstar_spi *bs,BOOL Enable ,U8 eSelect) ++{ ++ U16 regdata = 0; ++ U8 bitmask = 0; ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } else { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set MSPI chip select ++/// @param u8CS \u8 OUT: MSPI chip select ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetChipSelect(struct mstar_spi *bs,MSPI_CH eChannel, BOOL Enable, U8 u8CS) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ _HAL_MSPI_ChipSelect(bs, Enable, u8CS); ++ mutex_unlock(&hal_mspi_lock); ++} ++// add to sync code from utopia for localdimming to set clk ++void MDrv_MSPI_ChipSelect(struct mstar_spi *bs,U8 u8Channel, BOOL Enable, U8 u8CS) ++{ ++ HAL_MSPI_SetChipSelect(bs,(MSPI_CH)u8Channel,Enable,u8CS); ++ return; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_MSPI_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ int ret = 0; ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(U8TempLastFrameCnt) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++//------------------------------------------------------------------------------ ++/// Description : write data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ BOOL ret = false; ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(U8TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++U8 MDrv_MSPI_DMA_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ dma_addr_t data_addr; ++ ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ mutex_lock(&hal_mspi_lock); ++ ++ MOVDMA_WRITE( DMA_RW, DMA_READ); // 1 for dma read from device ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_READ); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u16Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, (u16Size>>16)& 0x00FF); // 24bit ++ ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_L, u16Size & 0xFFFF ); ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_H, u16Size>>16 ); ++ ++ data_addr=dma_map_single(NULL, pData, u16Size, DMA_TO_DEVICE); ++ if(data_addr > SPI_MIU1_BUS_BASE) ++ data_addr -= SPI_MIU1_BUS_BASE; ++ else ++ data_addr -= SPI_MIU0_BUS_BASE; ++ ++ MOVDMA_WRITE(MOV_DMA_DST_ADDR_L, data_addr & 0x0000FFFF ); ++ MOVDMA_WRITE(MOV_DMA_DST_ADDR_H, data_addr >>16 ); ++ ++ MOVDMA_WRITE(0x00,0x01);//dma enable ++ _HAL_MSPI_ChipSelect(bs,1,0);//enable chip select for device0 (pulled low) ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, 0); //spi length = 0 ++ _HAL_MSPI_Trigger(bs); ++ ++ mutex_unlock(&hal_mspi_lock); ++ return E_MSPI_OK; ++} ++ ++U8 MDrv_MSPI_DMA_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ dma_addr_t data_addr; ++ mutex_lock(&hal_mspi_lock); ++ ++ MOVDMA_WRITE( DMA_RW, DMA_WRITE );//0 for dma write to device ++ MOVDMA_WRITE( DMA_DEVICE_MODE, 0x0001 ); // 1 to enable dma device mode ++ MOVDMA_WRITE( DMA_DEVICE_SEL, bs->u8channel); //0 select mspi0 , 1 select mspi1 ++ ++ MSPI_WRITE(MSPI_DMA_ENABLE, 0x01); ++ MSPI_WRITE(MSPI_DMA_RW_MODE, MSPI_DMA_WRITE); ++ ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_L, u16Size & 0xFFFF ); ++ MSPI_WRITE(MSPI_DMA_DATA_LENGTH_H, u16Size>>16 ); ++ ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_L, u16Size & 0xFFFF ); ++ MOVDMA_WRITE(MOV_DMA_BYTE_CNT_H, u16Size>>16 ); ++ ++ data_addr=dma_map_single(NULL, pData, u16Size, DMA_FROM_DEVICE); ++ if(data_addr > SPI_MIU1_BUS_BASE) ++ data_addr -= SPI_MIU1_BUS_BASE; ++ else ++ data_addr -= SPI_MIU0_BUS_BASE; ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ MOVDMA_WRITE(MOV_DMA_SRC_ADDR_L, data_addr & 0x0000FFFF ); ++ MOVDMA_WRITE(MOV_DMA_SRC_ADDR_H, data_addr >>16); ++ ++ ++ MOVDMA_WRITE(0x00,0x01);//dma enable ++ _HAL_MSPI_ChipSelect(bs,1,0);//enable chip select for device0 (pulled low) ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, 0); ++ _HAL_MSPI_Trigger(bs); ++ ++ mutex_unlock(&hal_mspi_lock); ++ return E_MSPI_OK; ++} ++ ++u8 MDrv_MSPI_Init(struct mstar_spi *bs,u8 u8Channel,u8 u8Mode) ++{ ++ u8 errorno = E_MSPI_OK; ++ HAL_MSPI_Init(bs,(MSPI_CH)u8Channel,u8Mode); ++ HAL_MSPI_IntEnable(bs,(MSPI_CH)u8Channel,true); ++ gbInitFlag = true; ++ return errorno; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TrEnd timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrEnd timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrEndSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrEnd) ++{ ++ U8 u8TrEndMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TREND ,TrEnd); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TB timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TB timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TBSetting(struct mstar_spi *bs,U8 u8Channel,U8 TB) ++{ ++ U8 u8TBMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TB ,TB); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TRW timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TRW timging ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TRWSetting(struct mstar_spi *bs,U8 u8Channel,U8 TRW) ++{ ++ U8 u8TRWMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRW ,TRW); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of transfer timing config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_DCCONFIG_ERROR : failed to config transfer timing ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_DCConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_DCConfig *ptDCConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_INIT_FLOW_ERROR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ errnum = _MDrv_DC_TrStartSetting(bs,u8Channel,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TrEndSetting(bs,u8Channel,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TBSetting(bs,u8Channel,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TRWSetting(bs,u8Channel,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++void HAL_MSPI_SetCLKTiming(struct mstar_spi *bs,MSPI_CH eChannel, eCLK_config eCLKField, U8 u8CLKVal) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ switch(eCLKField) { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLSB(struct mstar_spi *bs,MSPI_CH eChannel, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static U8 clk_spi_ckg[3] = {108, 54, 12}; ++static U16 clk_spi_div[8] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static ST_DRV_MSPI_CLK clk_buffer[24]; ++ ++U32 HAL_MSPI_CLK_Config(struct mstar_spi *bs,U8 u8Chanel,U32 u32MspiClk) ++{ ++ U8 i = 0; ++ U8 j= 0; ++ U16 TempData = 0; ++ U32 clk =0; ++ ST_DRV_MSPI_CLK temp; ++ if(u8Chanel >=2) ++ return FALSE; ++ memset(&temp,0,sizeof(ST_DRV_MSPI_CLK)); ++ memset(&clk_buffer,0,sizeof(ST_DRV_MSPI_CLK)*24); ++ for(i = 0;i < 3;i++)//clk_spi_m_p1 ++ { ++ for(j = 0;j<8;j++)//spi div ++ { ++ clk = clk_spi_ckg[i]*1000000; ++ clk_buffer[j+8*i].u8ClkSpi_cfg = i; ++ clk_buffer[j+8*i].u8ClkSpi_DIV = j ; ++ clk_buffer[j+8*i].u32ClkSpi = clk/clk_spi_div[j]; ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ for(j = i;j<24;j++) ++ { ++ if(clk_buffer[i].u32ClkSpi > clk_buffer[j].u32ClkSpi) ++ { ++ memcpy(&temp,&clk_buffer[i],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[i],&clk_buffer[j],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[j],&temp,sizeof(ST_DRV_MSPI_CLK)); ++ } ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ if(u32MspiClk <= clk_buffer[i].u32ClkSpi) ++ { ++ break; ++ } ++ } ++ if (24 == i) ++ { ++ i--; ++ } ++ //match Closer clk ++ if ((i) && ((u32MspiClk - clk_buffer[i-1].u32ClkSpi)<(clk_buffer[i].u32ClkSpi - u32MspiClk))) ++ { ++ i -= 1; ++ } ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_P1 =%d\n",clk_buffer[i].u8ClkSpi_cfg); ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_DIV =%d\n",clk_buffer[i].u8ClkSpi_DIV); ++ mspi_dbgmsg("[Lwc Debug] u32ClkSpi = %d\n",clk_buffer[i].u32ClkSpi); ++ ++ if(u8Chanel == E_MSPI0)//mspi0 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<2); ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ } ++ else if(u8Chanel == E_MSPI1)//mspi1 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<10); ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ } ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= clk_buffer[i].u8ClkSpi_DIV << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return clk_buffer[i].u32ClkSpi; ++} ++ ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi clock setting ++/// @param ptCLKConfig \b OUT struct pointer of clock config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_CLKCONFIG_ERROR : failed to config spi clock ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_SetMode(struct mstar_spi *bs,U8 u8Channel, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++void HAL_MSPI_SetPerFrameSize(struct mstar_spi *bs,MSPI_CH eChannel, BOOL bDirect, U8 u8BufOffset, U8 u8PerFrameSize) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U8 u8BitOffset = 0; ++ U16 u16regIndex = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ if(bDirect == MSPI_READ_INDEX) { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } else { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ mutex_unlock(&hal_mspi_lock); ++ ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_FRAMECONFIG_ERROR : failed to config transfered bit per buffer ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_FRAMEConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ U8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) { ++ HAL_MSPI_Reset_FrameConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++static u8 HAL_MSPI_FRAMEConfig(struct mstar_spi *bs, U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ u8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) ++ { ++ HAL_MSPI_Reset_FrameConfig(bs, u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(bs, u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(bs, u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++u8 HAL_MSPI_SET_FRAMECFG(struct mstar_spi *bs, U8 u8Channel, int bits_per_word) ++{ ++ MSPI_FrameConfig stFrameConfig; ++ int i; ++ ++ if (bits_per_word > MSPI_MAX_SUPPORT_BITS) ++ { ++ return -EINVAL; ++ } ++ else if (bits_per_word > 8) ++ { ++ for (i = 0; i < MAX_WRITE_BUF_SIZE; i+=2) ++ { ++ stFrameConfig.u8WBitConfig[i] = bits_per_word - 8 -1; ++ stFrameConfig.u8WBitConfig[i+1] = 8 -1; ++ } ++ for (i = 0; i < MAX_READ_BUF_SIZE; i+=2) ++ { ++ stFrameConfig.u8RBitConfig[i] = bits_per_word - 8 -1; ++ stFrameConfig.u8RBitConfig[i+1] = 8 -1; ++ } ++ } ++ else ++ { ++ for (i = 0; i < MAX_WRITE_BUF_SIZE; i++) ++ { ++ stFrameConfig.u8WBitConfig[i] = bits_per_word -1; ++ } ++ for (i = 0; i < MAX_READ_BUF_SIZE; i++) ++ { ++ stFrameConfig.u8RBitConfig[i] = bits_per_word -1; ++ } ++ } ++ HAL_MSPI_FRAMEConfig(bs, u8Channel, &stFrameConfig); ++ ++ return 0; ++} ++ ++ ++// add to sync code from utopia for localdimming to set clk ++U32 MDrv_MSPI_SetCLK(struct mstar_spi *bs,U8 u8Channel, U32 u32MspiClk) ++{ ++ int u32SpiClk; ++ u32SpiClk = HAL_MSPI_CLK_Config(bs,(MSPI_CH)u8Channel,u32MspiClk); ++ return u32SpiClk; ++} ++ ++void mspi_config(struct mstar_spi *bs,u8 u8Channel) ++{ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ MDrv_MSPI_Init(bs,u8Channel,bs->u32spi_mode); ++ MDrv_MSPI_DCConfig(bs,u8Channel, &stDCConfig); ++ MDrv_MSPI_SetMode(bs,u8Channel, mspimode); ++ MDrv_MSPI_FRAMEConfig(bs,u8Channel,&stFrameConfig); ++ MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ MDrv_MSPI_ChipSelect(bs,u8Channel,0,0); ++ HAL_MSPI_SetLSB(bs,u8Channel, 0); ++ return; ++} ++ ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_0 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ ++ if(SUPPORT_DMA){ ++ mspi_dbgmsg("< Chip Select Disable >\r\n"); ++ _HAL_MSPI_ChipSelect(bs,0,0);//disable chip select for device0 (pulled high) ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static irqreturn_t mstar_spi_interrupt_spi1(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_1 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ ++ if(SUPPORT_DMA){ ++ mspi_dbgmsg("< Chip Select Disable >\r\n"); ++ _HAL_MSPI_ChipSelect(bs,0,0);//disable chip select for device0 (pulled high) ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_start_transfer]\n"); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ //reinit_completion(&bs->done); ++ bs->tx_buf = tfr->tx_buf; ++ bs->rx_buf = tfr->rx_buf; ++ bs->len = tfr->len; ++ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,1,0); ++ ++ /*if(tfr->speed_hz != NULL){ ++ MDrv_MSPI_SetCLK(_hal_msp.eCurrentCH,tfr->speed_hz); ++ }*/ ++ ++ if(bs->tx_buf != NULL){ ++ mspi_dbgmsg("bs->tx_buf=%x,%x\n",bs->tx_buf[0],bs->tx_buf[1]); ++ if(SUPPORT_DMA) ++ MDrv_MSPI_DMA_Write(bs, _hal_msp.eCurrentCH,(U8 *)bs->tx_buf,(U16)bs->len); ++ else ++ MDrv_MSPI_Write(bs, _hal_msp.eCurrentCH,(U8 *)bs->tx_buf,(U16)bs->len); ++ } ++ ++ if(bs->rx_buf != NULL){ ++ if(SUPPORT_DMA) ++ MDrv_MSPI_DMA_Read(bs,_hal_msp.eCurrentCH,(U8 *)bs->rx_buf,(U16)bs->len); ++ else ++ MDrv_MSPI_Read(bs,_hal_msp.eCurrentCH,(U8 *)bs->rx_buf,(U16)bs->len); ++ ++ mspi_dbgmsg("bs->rx_buf=%x,%x\n",bs->rx_buf[0],bs->rx_buf[1]); ++ } ++ ++ //printk("bs->len=%d\n",bs->len); ++ ++ ++ return 0; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_finish_transfer] cs_change=%d\n",cs_change); ++ ++#if 1 ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ MDrv_MSPI_ChipSelect(bs,_hal_msp.eCurrentCH,0,0); ++ //MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, 0xFFFF); ++ } ++#endif ++ return 0; ++} ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ if(bs->bits_per_word != spi->bits_per_word) ++ { ++ bs->bits_per_word = spi->bits_per_word; ++ SUPPORT_DMA = (bs->bits_per_word % 8 == 0) ? bs->use_dma : 0; ++ if (spi->bits_per_word > MSPI_MAX_SUPPORT_BITS) ++ { ++ return -EINVAL; ++ } ++ else if (spi->bits_per_word > 8) ++ { ++ bs->word_size = 2; ++ } ++ else ++ { ++ bs->word_size = 1; ++ } ++ HAL_MSPI_SET_FRAMECFG(bs, bs->u8channel, spi->bits_per_word); ++ ++ mspi_dbgmsg("setup bits : %d\n", sstar_spimst->bits_per_word); ++ } ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbgmsg("[mstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) { ++ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ mesg->actual_length += bs->len;//(tfr->len - bs->len); ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_master *master_spi1; ++ struct mstar_spi *bs; ++ int err; ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4spi_bank[5]; ++ int irq,irq2; ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#if SUPPORT_SPI_1 ++ master_spi1 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master_spi1) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#endif ++ mspi_dbgmsg( "spi_alloc_master\n"); ++ platform_set_drvdata(pdev, master); ++#if SUPPORT_SPI_1 ++ platform_set_drvdata(pdev, master_spi1); ++#endif ++ ++ master->mode_bits = MSTAR_SPI_MODE_BITS; ++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, MSPI_MAX_SUPPORT_BITS); ++ master->num_chipselect = 3; ++ master->transfer_one_message = mstar_spi_transfer_one; ++ master->dev.of_node = pdev->dev.of_node; ++ master->setup = mstar_spi_setup; ++ master->max_speed_hz = 54000000; ++ master->min_speed_hz = 46875; ++ master->bus_num = 0; ++ ++#if SUPPORT_SPI_1 ++ master_spi1->mode_bits = MSTAR_SPI_MODE_BITS; ++ master_spi1->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, MSPI_MAX_SUPPORT_BITS); ++ master_spi1->num_chipselect = 3; ++ master_spi1->transfer_one_message = mstar_spi_transfer_one; ++ master_spi1->dev.of_node = pdev->dev.of_node; ++ master_spi1->setup = mstar_spi_setup; ++ master_spi1->max_speed_hz = 54000000; ++ master_spi1->min_speed_hz = 46875; ++ master_spi1->bus_num = 1; ++#endif ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq); ++ if (request_irq(irq, mstar_spi_interrupt, 0, "MSPI_0 interrupt", (void*)master) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt failed"); ++#if SUPPORT_SPI_1 ++ irq2 = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq2); ++ if (request_irq(irq2, mstar_spi_interrupt_spi1, 0, "MSPI_1 interrupt", (void*)master_spi1) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt failed"); ++#endif ++ ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4spi_bank, 5); ++ ++ _hal_msp.eCurrentCH = E_MSPI1; ++ //_hal_msp.VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[_hal_msp.eCurrentCH])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ //_hal_msp.VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ ++ mspi_dbgmsg("u4IO_PHY_BASE %x\n",u4IO_PHY_BASE); ++ mspi_dbgmsg("u4spi_bank[0] %x\n",u4spi_bank[0]); ++ mspi_dbgmsg("u4spi_bank[1] %x\n",u4spi_bank[1]); ++ mspi_dbgmsg("u4spi_bank[2] %x\n",u4spi_bank[2]); ++ mspi_dbgmsg("u4spi_bank[3] %x\n",u4spi_bank[3]); ++ mspi_dbgmsg("u4spi_bank[4] %x\n",u4spi_bank[4]); ++ ++ bs = spi_master_get_devdata(master); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[0])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtMovdmaBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[4])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI0; ++ ++ of_property_read_u32(pdev->dev.of_node, "dma", &bs->use_dma); ++ if(bs->use_dma) ++ { ++ SUPPORT_DMA=true; ++ } ++ of_property_read_u32(pdev->dev.of_node, "spi0_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,0); ++ ++#if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(master_spi1); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[1])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtMovdmaBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[4])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI1; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi1_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,1); ++#endif ++ ++ ++ err = devm_spi_register_master(&pdev->dev, master); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_0 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#if SUPPORT_SPI_1 ++ err = devm_spi_register_master(&pdev->dev, master_spi1); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_1 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#endif ++ spi_new_device(master, &mstar_info); ++#if SUPPORT_SPI_1 ++ spi_new_device(master_spi1, &mstar_info); ++#endif ++ return 0; ++ ++//out_clk_disable: ++// clk_disable_unprepare(bs->clk); ++out_master_put: ++ spi_master_put(master); ++ mspi_dbgmsg( "((((((((((( err:%d\n", err); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++ ++#if 0 ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ ++ /* Clear FIFOs, and disable the HW block */ ++ ++ clk_disable_unprepare(bs->clk); ++#endif ++ return 0; ++} ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "sstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/sstar/spi/infinity6e/Makefile b/drivers/sstar/spi/infinity6e/Makefile +new file mode 100644 +index 000000000000..858e8817ca73 +--- /dev/null ++++ b/drivers/sstar/spi/infinity6e/Makefile +@@ -0,0 +1,2 @@ ++# SPI master controller drivers (bus) ++obj-$(CONFIG_MS_SPI_INFINITY) += mspi.o +diff --git a/drivers/sstar/spi/infinity6e/mspi.c b/drivers/sstar/spi/infinity6e/mspi.c +new file mode 100755 +index 000000000000..9c4fbd794692 +--- /dev/null ++++ b/drivers/sstar/spi/infinity6e/mspi.c +@@ -0,0 +1,1685 @@ ++/* ++* spi-infinity.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++bool gbInitFlag = false; ++static struct mutex hal_mspi_lock; ++//------------------------------------------------------------------------------------------------- ++// RegbaseAddr Disc ++//------------------------------------------------------------------------------------------------- ++#define mspi_dbg 0 ++#if mspi_dbg == 1 ++ #define mspi_dbgmsg(args...) printk(args) ++#else ++ #define mspi_dbgmsg(args...) do{}while(0) ++#endif ++ ++#define U8 u8 ++#define U16 u16 ++#define U32 u32 ++#define BOOL bool ++#define TRUE true ++#define FALSE false ++ ++#define SUPPORT_SPI_1 1 ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++ ++#define MSPI0_BANK_ADDR 0x1110 ++#define MSPI1_BANK_ADDR 0x1111 ++#define CLK__BANK_ADDR 0x1038 ++#define CHIPTOP_BANK_ADDR 0x101E ++ ++#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) ++#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) ++#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) ++#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++//------------------------------------------------------------------------------------------------- ++// Hardware Register Capability ++//------------------------------------------------------------------------------------------------- ++#define MSPI_WRITE_BUF_OFFSET 0x40 ++#define MSPI_READ_BUF_OFFSET 0x44 ++#define MSPI_WBF_SIZE_OFFSET 0x48 ++#define MSPI_RBF_SIZE_OFFSET 0x48 ++ // read/ write buffer size ++ #define MSPI_RWSIZE_MASK 0xFF ++ #define MSPI_RSIZE_BIT_OFFSET 0x8 ++ #define MAX_READ_BUF_SIZE 0x8 ++ #define MAX_WRITE_BUF_SIZE 0x8 ++// CLK config ++#define MSPI_CTRL_OFFSET 0x49 ++#define MSPI_CLK_CLOCK_OFFSET 0x49 ++ #define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 ++ #define MSPI_CLK_CLOCK_MASK 0xFF ++ #define MSPI_CLK_PHASE_MASK 0x40 ++ #define MSPI_CLK_PHASE_BIT_OFFSET 0x06 ++ #define MSPI_CLK_POLARITY_MASK 0x80 ++ #define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 ++ #define MSPI_CLK_PHASE_MAX 0x1 ++ #define MSPI_CLK_POLARITY_MAX 0x1 ++ #define MSPI_CLK_CLOCK_MAX 0x7 ++// DC config ++#define MSPI_DC_MASK 0xFF ++#define MSPI_DC_BIT_OFFSET 0x08 ++#define MSPI_DC_TR_START_OFFSET 0x4A ++ #define MSPI_DC_TRSTART_MAX 0xFF ++#define MSPI_DC_TR_END_OFFSET 0x4A ++ #define MSPI_DC_TREND_MAX 0xFF ++#define MSPI_DC_TB_OFFSET 0x4B ++ #define MSPI_DC_TB_MAX 0xFF ++#define MSPI_DC_TRW_OFFSET 0x4B ++ #define MSPI_DC_TRW_MAX 0xFF ++// Frame Config ++#define MSPI_FRAME_WBIT_OFFSET 0x4C ++#define MSPI_FRAME_RBIT_OFFSET 0x4E ++ #define MSPI_FRAME_BIT_MAX 0x07 ++ #define MSPI_FRAME_BIT_MASK 0x07 ++ #define MSPI_FRAME_BIT_FIELD 0x03 ++#define MSPI_LSB_FIRST_OFFSET 0x50 ++#define MSPI_TRIGGER_OFFSET 0x5A ++#define MSPI_DONE_OFFSET 0x5B ++#define MSPI_DONE_CLEAR_OFFSET 0x5C ++#define MSPI_CHIP_SELECT_OFFSET 0x5F ++ ++#define MSPI_FULL_DEPLUX_RD00 (0x78) ++#define MSPI_FULL_DEPLUX_RD01 (0x78) ++#define MSPI_FULL_DEPLUX_RD02 (0x79 ++#define MSPI_FULL_DEPLUX_RD03 (0x79) ++#define MSPI_FULL_DEPLUX_RD04 (0x7a) ++#define MSPI_FULL_DEPLUX_RD05 (0x7a) ++#define MSPI_FULL_DEPLUX_RD06 (0x7b) ++#define MSPI_FULL_DEPLUX_RD07 (0x7b) ++ ++#define MSPI_FULL_DEPLUX_RD08 (0x7c) ++#define MSPI_FULL_DEPLUX_RD09 (0x7c) ++#define MSPI_FULL_DEPLUX_RD10 (0x7d) ++#define MSPI_FULL_DEPLUX_RD11 (0x7d) ++#define MSPI_FULL_DEPLUX_RD12 (0x7e) ++#define MSPI_FULL_DEPLUX_RD13 (0x7e) ++#define MSPI_FULL_DEPLUX_RD14 (0x7f) ++#define MSPI_FULL_DEPLUX_RD15 (0x7f) ++ ++//chip select bit map ++ #define MSPI_CHIP_SELECT_MAX 0x07 ++// control bit ++#define MSPI_DONE_FLAG 0x01 ++#define MSPI_TRIGGER 0x01 ++#define MSPI_CLEAR_DONE 0x01 ++#define MSPI_INT_ENABLE 0x04 ++#define MSPI_RESET 0x02 ++#define MSPI_ENABLE 0x01 ++ ++// clk_mspi0 ++#define MSPI0_CLK_CFG 0x33//bit 2 ~bit 3 ++ #define MSPI0_CLK_108M 0x00 ++ #define MSPI0_CLK_54M 0x04 ++ #define MSPI0_CLK_12M 0x08 ++ #define MSPI0_CLK_MASK 0x0F ++// clk_mspi1 ++#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 ++ #define MSPI1_CLK_108M 0x0000 ++ #define MSPI1_CLK_54M 0x0400 ++ #define MSPI1_CLK_12M 0x0800 ++ #define MSPI1_CLK_MASK 0x0F00 ++ ++//CHITOP 101E mspi mode select ++#define MSPI0_MODE 0x68 //bit0~bit1 ++ #define MSPI0_MODE_MASK 0x07 ++#define MSPI1_MODE 0x68 //bit4~bit5 ++ #define MSPI1_MODE_MASK 0x70 ++#define EJTAG_MODE 0x60 ++ #define EJTAG_MODE_1 0x0080 ++ #define EJTAG_MODE_MASK 0x0180 ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile u16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile u32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } ++ ++// read 2 byte ++#define MSPI_READ(_reg_) READ_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2)) ++// write 2 byte ++#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_)) ++//write 2 byte mask ++#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(bs->VirtMspBaseAddr + ((_reg_)<<2), (_val_), (mask)) ++ ++#define CLK_READ(_reg_) READ_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2)) ++#define CLK_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtClkBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define CHIPTOP_READ(_reg_) READ_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2)) ++#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(bs->VirtChiptopBaseAddr + ((_reg_)<<2), (_val_)) ++ ++#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) ++#define MAX_CHECK_CNT 2000 ++ ++#define MSPI_READ_INDEX 0x0 ++#define MSPI_WRITE_INDEX 0x1 ++#define MSPI_MAX_SUPPORT_BITS 16 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MSPI0, ++ E_MSPI1, ++ E_MSPI_MAX, ++}MSPI_CH; ++ ++ ++typedef enum ++{ ++ E_MSPI_BIT_MSB_FIRST, ++ E_MSPI_BIT_LSB_FIRST, ++}MSPI_BitSeq_e; ++ ++typedef enum _HAL_CLK_Config ++{ ++ E_MSPI_POL, ++ E_MSPI_PHA, ++ E_MSPI_CLK ++}eCLK_config; ++ ++typedef enum _HAL_DC_Config ++{ ++ E_MSPI_TRSTART, ++ E_MSPI_TREND, ++ E_MSPI_TB, ++ E_MSPI_TRW ++}eDC_config; ++ ++typedef struct ++{ ++ u32 u32Clock; ++ u8 u8Clock; ++ bool BClkPolarity; ++ bool BClkPhase; ++ u32 u32MAXClk; ++} MSPI_CLKConfig; ++ ++ ++typedef struct ++{ ++ u8 u8ClkSpi_cfg; ++ u8 u8ClkSpi_DIV; ++ u32 u32ClkSpi; ++}ST_DRV_MSPI_CLK; ++ ++typedef enum ++{ ++ E_MSPI_DBGLV_NONE, //disable all the debug message ++ E_MSPI_DBGLV_INFO, //information ++ E_MSPI_DBGLV_NOTICE, //normal but significant condition ++ E_MSPI_DBGLV_WARNING, //warning conditions ++ E_MSPI_DBGLV_ERR, //error conditions ++ E_MSPI_DBGLV_CRIT, //critical conditions ++ E_MSPI_DBGLV_ALERT, //action must be taken immediately ++ E_MSPI_DBGLV_EMERG, //system is unusable ++ E_MSPI_DBGLV_DEBUG, //debug-level messages ++} MSPI_DbgLv; ++ ++typedef enum _MSPI_ERRORNOn { ++ E_MSPI_OK = 0 ++ ,E_MSPI_INIT_FLOW_ERROR =1 ++ ,E_MSPI_DCCONFIG_ERROR =2 ++ ,E_MSPI_CLKCONFIG_ERROR =4 ++ ,E_MSPI_FRAMECONFIG_ERROR =8 ++ ,E_MSPI_OPERATION_ERROR = 0x10 ++ ,E_MSPI_PARAM_OVERFLOW = 0x20 ++ ,E_MSPI_MMIO_ERROR = 0x40 ++ ,E_MSPI_HW_NOT_SUPPORT = 0x80 ++ ,E_MSPI_NULL ++} MSPI_ErrorNo; ++ ++typedef struct ++{ ++ MSPI_CH eCurrentCH; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++} MSPI_BaseAddr_st; ++ ++#if 0 ++static MSPI_BaseAddr_st _hal_msp = { ++ .eCurrentCH = E_MSPI0, ++ //.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR, ++ //.VirtClkBaseAddr = BASE_REG_CLK_ADDR, ++ //.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++}; ++#endif ++ ++typedef enum { ++ E_MSPI_MODE0, //CPOL = 0,CPHA =0 ++ E_MSPI_MODE1, //CPOL = 0,CPHA =1 ++ E_MSPI_MODE2, //CPOL = 1,CPHA =0 ++ E_MSPI_MODE3, //CPOL = 1,CPHA =1 ++ E_MSPI_MODE_MAX, ++} MSPI_Mode_Config_e; ++ ++typedef struct ++{ ++ u8 u8TrStart; //time from trigger to first SPI clock ++ u8 u8TrEnd; //time from last SPI clock to transferred done ++ u8 u8TB; //time between byte to byte transfer ++ u8 u8TRW; //time between last write and first read ++} MSPI_DCConfig; ++ ++typedef struct ++{ ++ u8 u8WBitConfig[8]; //bits will be transferred in write buffer ++ u8 u8RBitConfig[8]; //bits Will be transferred in read buffer ++} MSPI_FrameConfig; ++ ++ ++#define MSTAR_SPI_TIMEOUT_MS 30000 ++#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) ++ ++#define DRV_NAME "spi" ++struct mstar_spi { ++ void __iomem *regs; ++ struct clk *clk; ++ int irq; ++ struct completion done; ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++ char *VirtMspBaseAddr; ++ char *VirtClkBaseAddr; ++ char *VirtChiptopBaseAddr; ++ char u8channel; ++ int u32spi_mode; ++ u32 bits_per_word; ++ u32 word_size; ++}; ++ ++static struct spi_board_info mstar_info = { ++ .modalias = "spidev", ++}; ++ ++static void _HAL_MSPI_CheckandSetBaseAddr(MSPI_CH eChannel) ++{ ++ ++#if 0 ++ if(eChannel == _hal_msp.eCurrentCH) ++ { ++ return; ++ } else if(eChannel == E_MSPI0) ++ { ++ _hal_msp.eCurrentCH = E_MSPI0; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI0_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi0 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else if(eChannel == E_MSPI1) ++ { ++ _hal_msp.eCurrentCH = E_MSPI1; ++ _hal_msp.VirtMspBaseAddr = BASE_REG_MSPI1_ADDR; ++ _hal_msp.VirtClkBaseAddr = BASE_REG_CLK_ADDR; ++ _hal_msp.VirtChiptopBaseAddr = BASE_REG_CHIPTOP_ADDR, ++ printk(KERN_ERR"[Lwc Debug] Set mspi1 base address : %x\n",_hal_msp.VirtMspBaseAddr); ++ printk(KERN_ERR"[Lwc Debug] Set clk base address : %x\n",_hal_msp.VirtClkBaseAddr); ++ } else ++ { ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("[Mspi Error]FUN:%s MSPI Channel is out of range!\n",__FUNCTION__)); ++ printk("[Mspi Error]FUN: MSPI Channel is out of range!\n"); ++ return ; ++ } ++ ++#endif ++} ++//------------------------------------------------------------------------------ ++/// Description : Reset Frame register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_FrameConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ // Frame reset ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+2, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xFFF); ++ MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+2, 0xFFF); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : MSPI interrupt enable ++/// @param bEnable \b OUT: enable or disable mspi interrupt ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_IntEnable(struct mstar_spi *bs,MSPI_CH eChannel,bool bEnable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ if(bEnable) { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|MSPI_INT_ENABLE); ++ } else { ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)&(~MSPI_INT_ENABLE)); ++ } ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_Init(struct mstar_spi *bs,MSPI_CH eChannel,u8 u8Mode) ++{ ++ u16 TempData; ++ //init MSP ++ //DEBUG_MSPI(E_MSPI_DBGLV_INFO,printk("HAL_MSPI_Init\n")); ++ mspi_dbgmsg("HAL_MSPI_Init : Channel=%d spi mode=%d\n",eChannel,u8Mode); ++ mutex_init(&hal_mspi_lock); ++ if((eChannel > E_MSPI1) || (u8Mode < 1)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI0) && (u8Mode > 3)) ++ { ++ return; ++ } ++ else if((eChannel == E_MSPI1) && (u8Mode > 6)) ++ { ++ return; ++ } ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ ++ MSPI_WRITE(MSPI_CTRL_OFFSET,MSPI_READ(MSPI_CTRL_OFFSET)|(MSPI_RESET|MSPI_ENABLE)); ++ ++ if(eChannel == E_MSPI0) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= MSPI0_CLK_108M; ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI0_MODE); ++ TempData &= ~(MSPI0_MODE_MASK); ++ TempData |= u8Mode; ++ CHIPTOP_WRITE(MSPI0_MODE,TempData); ++ ++ //Disable jtag mode // IO PAD conflict turn off jtag ++ TempData = CHIPTOP_READ(EJTAG_MODE); ++ if(TempData == EJTAG_MODE_1) { ++ TempData &= ~(EJTAG_MODE_MASK); ++ CHIPTOP_WRITE(EJTAG_MODE,TempData); ++ } ++ } ++ else if (eChannel == E_MSPI1) ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= MSPI1_CLK_108M; ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ //select mspi mode ++ TempData = CHIPTOP_READ(MSPI1_MODE); ++ TempData &= ~(MSPI1_MODE_MASK); ++ TempData |= (u8Mode << 4); ++ CHIPTOP_WRITE(MSPI1_MODE,TempData); ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return; ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return NONE ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetDcTiming (struct mstar_spi *bs,MSPI_CH eChannel, eDC_config eDCField, U8 u8DCtiming) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr(eChannel); ++ switch(eDCField) { ++ case E_MSPI_TRSTART: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_START_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TREND: ++ u16TempBuf = MSPI_READ(MSPI_DC_TR_END_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TR_END_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TB: ++ u16TempBuf = MSPI_READ(MSPI_DC_TB_OFFSET); ++ u16TempBuf &= (~MSPI_DC_MASK); ++ u16TempBuf |= u8DCtiming; ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, u16TempBuf); ++ break; ++ case E_MSPI_TRW: ++ u16TempBuf = MSPI_READ(MSPI_DC_TRW_OFFSET); ++ u16TempBuf &= MSPI_DC_MASK; ++ u16TempBuf |= u8DCtiming << MSPI_DC_BIT_OFFSET; ++ MSPI_WRITE(MSPI_DC_TRW_OFFSET, u16TempBuf); ++ break; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static void _HAL_MSPI_RWBUFSize(struct mstar_spi *bs,BOOL Direct, U8 Size) ++{ ++ U16 u16Data = 0; ++ u16Data = MSPI_READ(MSPI_RBF_SIZE_OFFSET); ++ //printk("===RWBUFSize:%d\n",Size); ++ if(Direct == MSPI_READ_INDEX) ++ { ++ u16Data &= MSPI_RWSIZE_MASK; ++ u16Data |= Size << MSPI_RSIZE_BIT_OFFSET; ++ } ++ else ++ { ++ u16Data &= ~MSPI_RWSIZE_MASK; ++ u16Data |= Size; ++ } ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET, u16Data); ++} ++//------------------------------------------------------------------------------ ++/// Description : check MSPI operation complete ++/// @return TRUE : operation complete ++/// @return FAIL : failed timeout ++//------------------------------------------------------------------------------ ++static U16 _HAL_MSPI_CheckDone(struct mstar_spi *bs) ++{ ++/* ++ U16 uCheckDoneCnt = 0; ++ U16 uDoneFlag = 0; ++ while(uCheckDoneCnt < MAX_CHECK_CNT) { ++ uDoneFlag = MSPI_READ(MSPI_DONE_OFFSET); ++ if(uDoneFlag & MSPI_DONE_FLAG) { ++ printk("Done flag success!!!!!!!!!!!!!!!!!!!!!!!!\n"); ++ return TRUE; ++ } ++ // printk("..."); ++ uCheckDoneCnt++; ++ } ++ //DEBUG_MSPI(E_MSPI_DBGLV_ERR,printk("ERROR:MSPI Operation Timeout!!!!!\n")); ++ printk("ERROR:MSPI Operation asasTimeout!!!!!\n"); ++ return FALSE; ++*/ ++ ++ return MSPI_READ(MSPI_DONE_OFFSET); ++} ++//------------------------------------------------------------------------------ ++/// Description : Trigger MSPI operation ++/// @return TRUE : operation success ++/// @return FALSE : operation timeout ++//------------------------------------------------------------------------------ ++BOOL _HAL_MSPI_Trigger(struct mstar_spi *bs) ++{ ++ unsigned int timeout; ++ // trigger operation ++ reinit_completion(&bs->done); ++ MSPI_WRITE(MSPI_TRIGGER_OFFSET,MSPI_TRIGGER); ++ ++ ++ timeout = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(MSTAR_SPI_TIMEOUT_MS)); ++ ++ MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ ++ if (!timeout) { ++ mspi_dbgmsg("timeout\n"); ++ //goto out; ++ } ++ ++ // check operation complete ++// if(!_HAL_MSPI_CheckDone()) { ++// return FALSE; ++// } ++ // clear done flag ++// _HAL_MSPI_ClearDone(); ++ // reset read/write buffer size ++// MSPI_WRITE(MSPI_RBF_SIZE_OFFSET,0x0); ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return TRUE : read data success ++/// @return FALSE : read data fail ++//------------------------------------------------------------------------------------------------- ++BOOL HAL_MSPI_Read(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U16 i =0, j = 0; ++ u8 shift; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & 0x1); ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ for(i = 0; i < u16Size; i+= MAX_READ_BUF_SIZE) { ++ u16TempBuf = u16Size - i; ++ if(u16TempBuf > MAX_READ_BUF_SIZE) { ++ j = MAX_READ_BUF_SIZE; ++ } else { ++ j = u16TempBuf; ++ } ++ _HAL_MSPI_RWBUFSize(bs,MSPI_READ_INDEX, j); ++ ++ _HAL_MSPI_Trigger(bs); ++ ++ for(u8Index = 0; u8Index < j; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ if (isMsbBitMode) ++ { ++ //MSB MODE ++ if (bs->bits_per_word <= 8) ++ { ++ //printk("u16TempBuf 0x%x\n",u16TempBuf); ++ shift = bs->bits_per_word; ++ pData[u8Index] = (u16TempBuf >> 8) & ((0x1 << shift) - 0x1); ++ pData[u8Index-1] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ else //bits_per_word=9~15 ++ { ++ shift = bs->bits_per_word - 8; ++ pData[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ pData[u8Index-1] = u16TempBuf >> 8; ++ } ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ else if(u8Index == (j -1)) ++ { ++ u16TempBuf = MSPI_READ((MSPI_READ_BUF_OFFSET + (u8Index >> 1))); ++ shift = bs->bits_per_word; ++ pData[u8Index] = u16TempBuf & ((0x1 << shift) - 0x1); ++ } ++ } ++ pData+= j; ++ } ++ ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : read data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return TRUE : write data success ++/// @return FALSE : wirte data fail ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Write(struct mstar_spi *bs, MSPI_CH eChannel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ u8 shift = 0; ++ u8 isMsbBitMode = !(MSPI_READ(MSPI_LSB_FIRST_OFFSET) & 0x1); ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ for(u8Index = 0; u8Index < u16Size; u8Index++) ++ { ++ if(u8Index & 1) ++ { ++ if(bs->bits_per_word <= 8) ++ { ++ shift = (isMsbBitMode) ? (8 - bs->bits_per_word) : 0; ++ u16TempBuf = (pData[u8Index] << (shift + 8)) | (pData[u8Index-1] << shift); ++ } ++ else ++ { ++ shift = 16 - bs->bits_per_word; ++ if(isMsbBitMode) ++ { ++ u16TempBuf = (pData[u8Index] << shift) | (pData[u8Index-1] << 8); ++ } ++ else ++ { ++ //NO LSB ++ } ++ } ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),u16TempBuf); ++ } ++ else if(u8Index == (u16Size -1)) ++ { ++ shift = 8 - bs->bits_per_word; ++ MSPI_WRITE((MSPI_WRITE_BUF_OFFSET + (u8Index >> 1)),pData[u8Index] << shift); ++ } ++ } ++ ++ _HAL_MSPI_RWBUFSize(bs,MSPI_WRITE_INDEX, u16Size); ++ _HAL_MSPI_Trigger(bs); ++ // set write data size ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset CLK register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_CLKConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ U16 Tempbuf; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //reset clock ++ Tempbuf = MSPI_READ(MSPI_CTRL_OFFSET); ++ Tempbuf &= 0x3F; ++ MSPI_WRITE(MSPI_CTRL_OFFSET, Tempbuf); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++ ++U8 HAL_MSPI_DCConfigMax(eDC_config eDCField) ++{ ++ switch(eDCField) ++ { ++ case E_MSPI_TRSTART: ++ return MSPI_DC_TRSTART_MAX; ++ case E_MSPI_TREND: ++ return MSPI_DC_TREND_MAX; ++ case E_MSPI_TB: ++ return MSPI_DC_TB_MAX; ++ case E_MSPI_TRW: ++ return MSPI_DC_TRW_MAX; ++ default: ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set TrStart timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrStart timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrStartSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrStart) ++{ ++ U8 u8TrStartMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrStartMax = HAL_MSPI_DCConfigMax(E_MSPI_TRSTART); ++ if(TrStart > u8TrStartMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRSTART ,TrStart); ++ return errnum; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Reset DC register setting of MSPI ++/// @param NONE ++/// @return TRUE : reset complete ++//------------------------------------------------------------------------------ ++BOOL HAL_MSPI_Reset_DCConfig(struct mstar_spi *bs,MSPI_CH eChannel) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ //DC reset ++ MSPI_WRITE(MSPI_DC_TR_START_OFFSET, 0x00); ++ MSPI_WRITE(MSPI_DC_TB_OFFSET, 0x00); ++ mutex_unlock(&hal_mspi_lock); ++ return TRUE; ++} ++//------------------------------------------------------------------------------ ++/// Description : SPI chip select enable and disable ++/// @param Enable \b OUT: enable or disable chip select ++//------------------------------------------------------------------------------ ++static void _HAL_MSPI_ChipSelect(struct mstar_spi *bs,BOOL Enable ,U8 eSelect) ++{ ++ U16 regdata = 0; ++ U8 bitmask = 0; ++ regdata = MSPI_READ(MSPI_CHIP_SELECT_OFFSET); ++ if(Enable) { ++ bitmask = ~(1 << eSelect); ++ regdata &= bitmask; ++ } else { ++ bitmask = (1 << eSelect); ++ regdata |= bitmask; ++ } ++ MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, regdata); ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set MSPI chip select ++/// @param u8CS \u8 OUT: MSPI chip select ++/// @return void: ++//------------------------------------------------------------------------------ ++void HAL_MSPI_SetChipSelect(struct mstar_spi *bs,MSPI_CH eChannel, BOOL Enable, U8 u8CS) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ _HAL_MSPI_ChipSelect(bs, Enable, u8CS); ++ mutex_unlock(&hal_mspi_lock); ++} ++// add to sync code from utopia for localdimming to set clk ++void MDrv_MSPI_ChipSelect(struct mstar_spi *bs,U8 u8Channel, BOOL Enable, U8 u8CS) ++{ ++ HAL_MSPI_SetChipSelect(bs,(MSPI_CH)u8Channel,Enable,u8CS); ++ return; ++} ++//------------------------------------------------------------------------------------------------- ++/// Description : read data from MSPI ++/// @param pData \b IN :pointer to receive data from MSPI read buffer ++/// @param u16Size \ b OTU : read data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_MSPI_Read(struct mstar_spi *bs, U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ //MSPI_ErrorNo errorno = E_MSPI_OK; ++ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ int ret = 0; ++ if(pData == NULL) { ++ return E_MSPI_NULL; ++ } ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ if(U8TempLastFrameCnt) { ++ ret = HAL_MSPI_Read(bs,(MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++//------------------------------------------------------------------------------ ++/// Description : write data from MSPI ++/// @param pData \b OUT :pointer to write data to MSPI write buffer ++/// @param u16Size \ b OTU : write data size ++/// @return the errorno of operation ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_Write(struct mstar_spi *bs,U8 u8Channel, U8 *pData, U16 u16Size) ++{ ++ U8 u8Index = 0; ++ U8 u8TempFrameCnt=0; ++ U8 U8TempLastFrameCnt=0; ++ BOOL ret = false; ++ u8TempFrameCnt = u16Size/MAX_WRITE_BUF_SIZE; //Cut data to frame by max frame size ++ U8TempLastFrameCnt = u16Size%MAX_WRITE_BUF_SIZE; //Last data less than a MAX_WRITE_BUF_SIZE fame ++ for (u8Index = 0; u8Index < u8TempFrameCnt; u8Index++) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8Index*MAX_WRITE_BUF_SIZE,MAX_WRITE_BUF_SIZE); ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ } ++ ++ if(U8TempLastFrameCnt) ++ { ++ ret = HAL_MSPI_Write(bs, (MSPI_CH)u8Channel,pData+u8TempFrameCnt*MAX_WRITE_BUF_SIZE,U8TempLastFrameCnt); ++ } ++ ++ if (!ret) { ++ return E_MSPI_OPERATION_ERROR; ++ } ++ return E_MSPI_OK; ++} ++ ++u8 MDrv_MSPI_Init(struct mstar_spi *bs,u8 u8Channel,u8 u8Mode) ++{ ++ u8 errorno = E_MSPI_OK; ++ HAL_MSPI_Init(bs,(MSPI_CH)u8Channel,u8Mode); ++ HAL_MSPI_IntEnable(bs,(MSPI_CH)u8Channel,true); ++ gbInitFlag = true; ++ return errorno; ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TrEnd timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TrEnd timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TrEndSetting(struct mstar_spi *bs,U8 u8Channel,U8 TrEnd) ++{ ++ U8 u8TrEndMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TrEndMax = HAL_MSPI_DCConfigMax(E_MSPI_TREND); ++ if(TrEnd > u8TrEndMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TREND ,TrEnd); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TB timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TB timing ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TBSetting(struct mstar_spi *bs,U8 u8Channel,U8 TB) ++{ ++ U8 u8TBMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TBMax = HAL_MSPI_DCConfigMax(E_MSPI_TB); ++ if(TB > u8TBMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TB ,TB); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : Set TRW timing of DC config ++/// @return E_MSPI_OK : ++/// @return >1 : failed to set TRW timging ++//------------------------------------------------------------------------------ ++static U8 _MDrv_DC_TRWSetting(struct mstar_spi *bs,U8 u8Channel,U8 TRW) ++{ ++ U8 u8TRWMax; ++ U8 errnum = E_MSPI_OK; ++ ++ u8TRWMax = HAL_MSPI_DCConfigMax(E_MSPI_TRW); ++ if(TRW > u8TRWMax) ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ else ++ HAL_MSPI_SetDcTiming(bs,(MSPI_CH)u8Channel,E_MSPI_TRW ,TRW); ++ return errnum; ++ ++} ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of transfer timing config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_DCCONFIG_ERROR : failed to config transfer timing ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_DCConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_DCConfig *ptDCConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ //check init ++ if(!gbInitFlag) ++ return E_MSPI_INIT_FLOW_ERROR; ++ ++ if(ptDCConfig == NULL) ++ { ++ HAL_MSPI_Reset_DCConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ errnum = _MDrv_DC_TrStartSetting(bs,u8Channel,ptDCConfig->u8TrStart); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TrEndSetting(bs,u8Channel,ptDCConfig->u8TrEnd); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TBSetting(bs,u8Channel,ptDCConfig->u8TB); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ errnum = _MDrv_DC_TRWSetting(bs,u8Channel,ptDCConfig->u8TRW); ++ if(errnum != E_MSPI_OK) ++ goto ERROR_HANDLE; ++ return E_MSPI_OK; ++ ++ERROR_HANDLE: ++ errnum |= E_MSPI_DCCONFIG_ERROR; ++ return errnum; ++} ++ ++void HAL_MSPI_SetCLKTiming(struct mstar_spi *bs,MSPI_CH eChannel, eCLK_config eCLKField, U8 u8CLKVal) ++{ ++ U16 u16TempBuf = 0; ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ switch(eCLKField) { ++ case E_MSPI_POL: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_POLARITY_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_POLARITY_BIT_OFFSET; ++ break; ++ case E_MSPI_PHA: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= ~(MSPI_CLK_PHASE_MASK); ++ u16TempBuf |= u8CLKVal << MSPI_CLK_PHASE_BIT_OFFSET; ++ break; ++ case E_MSPI_CLK: ++ u16TempBuf = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ u16TempBuf &= MSPI_CLK_CLOCK_MASK; ++ u16TempBuf |= u8CLKVal << MSPI_CLK_CLOCK_BIT_OFFSET; ++ break; ++ } ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, u16TempBuf); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++void HAL_MSPI_SetLSB(struct mstar_spi *bs,MSPI_CH eChannel, BOOL enable) ++{ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ ++ MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, enable); ++ ++ mutex_unlock(&hal_mspi_lock); ++} ++ ++static U8 clk_spi_ckg[3] = {108, 54, 12}; ++static U16 clk_spi_div[8] = {2, 4, 8, 16, 32, 64, 128, 256}; ++static ST_DRV_MSPI_CLK clk_buffer[24]; ++ ++U32 HAL_MSPI_CLK_Config(struct mstar_spi *bs,U8 u8Chanel,U32 u32MspiClk) ++{ ++ U8 i = 0; ++ U8 j= 0; ++ U16 TempData = 0; ++ U32 clk =0; ++ ST_DRV_MSPI_CLK temp; ++ if(u8Chanel >=2) ++ return FALSE; ++ memset(&temp,0,sizeof(ST_DRV_MSPI_CLK)); ++ memset(&clk_buffer,0,sizeof(ST_DRV_MSPI_CLK)*24); ++ for(i = 0;i < 3;i++)//clk_spi_m_p1 ++ { ++ for(j = 0;j<8;j++)//spi div ++ { ++ clk = clk_spi_ckg[i]*1000000; ++ clk_buffer[j+8*i].u8ClkSpi_cfg = i; ++ clk_buffer[j+8*i].u8ClkSpi_DIV = j ; ++ clk_buffer[j+8*i].u32ClkSpi = clk/clk_spi_div[j]; ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ for(j = i;j<24;j++) ++ { ++ if(clk_buffer[i].u32ClkSpi > clk_buffer[j].u32ClkSpi) ++ { ++ memcpy(&temp,&clk_buffer[i],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[i],&clk_buffer[j],sizeof(ST_DRV_MSPI_CLK)); ++ ++ memcpy(&clk_buffer[j],&temp,sizeof(ST_DRV_MSPI_CLK)); ++ } ++ } ++ } ++ for(i = 0;i<24;i++) ++ { ++ if(u32MspiClk <= clk_buffer[i].u32ClkSpi) ++ { ++ break; ++ } ++ } ++ if (24 == i) ++ { ++ i--; ++ } ++ //match Closer clk ++ if ((i) && ((u32MspiClk - clk_buffer[i-1].u32ClkSpi)<(clk_buffer[i].u32ClkSpi - u32MspiClk))) ++ { ++ i -= 1; ++ } ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_P1 =%d\n",clk_buffer[i].u8ClkSpi_cfg); ++ mspi_dbgmsg("[Lwc Debug] u8ClkSpi_DIV =%d\n",clk_buffer[i].u8ClkSpi_DIV); ++ mspi_dbgmsg("[Lwc Debug] u32ClkSpi = %d\n",clk_buffer[i].u32ClkSpi); ++ ++ if(u8Chanel == E_MSPI0)//mspi0 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI0_CLK_CFG); ++ TempData &= ~(MSPI0_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<2); ++ CLK_WRITE(MSPI0_CLK_CFG, TempData); ++ } ++ else if(u8Chanel == E_MSPI1)//mspi1 ++ { ++ // CLK SETTING ++ TempData = CLK_READ(MSPI1_CLK_CFG); ++ TempData &= ~(MSPI1_CLK_MASK); ++ TempData |= (clk_buffer[i].u8ClkSpi_cfg<<10); ++ CLK_WRITE(MSPI1_CLK_CFG, TempData); ++ } ++ TempData = MSPI_READ(MSPI_CLK_CLOCK_OFFSET); ++ TempData &= MSPI_CLK_CLOCK_MASK; ++ TempData |= clk_buffer[i].u8ClkSpi_DIV << MSPI_CLK_CLOCK_BIT_OFFSET; ++ MSPI_WRITE(MSPI_CLK_CLOCK_OFFSET, TempData); ++ ++ return clk_buffer[i].u32ClkSpi; ++} ++ ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi clock setting ++/// @param ptCLKConfig \b OUT struct pointer of clock config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_CLKCONFIG_ERROR : failed to config spi clock ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_SetMode(struct mstar_spi *bs,U8 u8Channel, MSPI_Mode_Config_e eMode) ++{ ++ if (eMode >= E_MSPI_MODE_MAX) { ++ return E_MSPI_PARAM_OVERFLOW; ++ } ++ ++ switch (eMode) { ++ case E_MSPI_MODE0: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ ++ break; ++ case E_MSPI_MODE1: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,false); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ case E_MSPI_MODE2: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,false); ++ break; ++ case E_MSPI_MODE3: ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_POL ,true); ++ HAL_MSPI_SetCLKTiming(bs,(MSPI_CH)u8Channel, E_MSPI_PHA ,true); ++ break; ++ default: ++ HAL_MSPI_Reset_CLKConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OPERATION_ERROR; ++ } ++ ++ return E_MSPI_OK; ++} ++ ++void HAL_MSPI_SetPerFrameSize(struct mstar_spi *bs,MSPI_CH eChannel, BOOL bDirect, U8 u8BufOffset, U8 u8PerFrameSize) ++{ ++ U8 u8Index = 0; ++ U16 u16TempBuf = 0; ++ U8 u8BitOffset = 0; ++ U16 u16regIndex = 0; ++ ++ mutex_lock(&hal_mspi_lock); ++ _HAL_MSPI_CheckandSetBaseAddr( eChannel); ++ if(bDirect == MSPI_READ_INDEX) { ++ u16regIndex = MSPI_FRAME_RBIT_OFFSET; ++ } else { ++ u16regIndex = MSPI_FRAME_WBIT_OFFSET; ++ } ++ if(u8BufOffset >=4) { ++ u8Index++; ++ u8BufOffset -= 4; ++ } ++ u8BitOffset = u8BufOffset * MSPI_FRAME_BIT_FIELD; ++ u16TempBuf = MSPI_READ(u16regIndex+ u8Index); ++ u16TempBuf &= ~(MSPI_FRAME_BIT_MASK << u8BitOffset); ++ u16TempBuf |= u8PerFrameSize << u8BitOffset; ++ MSPI_WRITE((u16regIndex + u8Index), u16TempBuf); ++ mutex_unlock(&hal_mspi_lock); ++ ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : config spi transfer timing ++/// @param ptDCConfig \b OUT struct pointer of bits of buffer tranferred to slave config ++/// @return E_MSPI_OK : succeed ++/// @return E_MSPI_FRAMECONFIG_ERROR : failed to config transfered bit per buffer ++//------------------------------------------------------------------------------ ++U8 MDrv_MSPI_FRAMEConfig(struct mstar_spi *bs,U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ U8 errnum = E_MSPI_OK; ++ U8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) { ++ HAL_MSPI_Reset_FrameConfig(bs,(MSPI_CH)u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } else { ++ HAL_MSPI_SetPerFrameSize(bs,(MSPI_CH)u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++static u8 HAL_MSPI_FRAMEConfig(struct mstar_spi *bs, U8 u8Channel, MSPI_FrameConfig *ptFrameConfig) ++{ ++ u8 errnum = E_MSPI_OK; ++ u8 u8Index = 0; ++ ++ if(ptFrameConfig == NULL) ++ { ++ HAL_MSPI_Reset_FrameConfig(bs, u8Channel); ++ return E_MSPI_OK; ++ } ++ // read buffer bit config ++ for(u8Index = 0; u8Index < MAX_READ_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8RBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(bs, u8Channel, MSPI_READ_INDEX, u8Index, ptFrameConfig->u8RBitConfig[u8Index]); ++ } ++ } ++ //write buffer bit config ++ for(u8Index = 0; u8Index < MAX_WRITE_BUF_SIZE; u8Index++) ++ { ++ if(ptFrameConfig->u8WBitConfig[u8Index] > MSPI_FRAME_BIT_MAX) ++ { ++ errnum = E_MSPI_PARAM_OVERFLOW; ++ } ++ else ++ { ++ HAL_MSPI_SetPerFrameSize(bs, u8Channel, MSPI_WRITE_INDEX, u8Index, ptFrameConfig->u8WBitConfig[u8Index]); ++ } ++ } ++ return errnum; ++} ++ ++u8 HAL_MSPI_SET_FRAMECFG(struct mstar_spi *bs, U8 u8Channel, int bits_per_word) ++{ ++ MSPI_FrameConfig stFrameConfig; ++ int i; ++ ++ if (bits_per_word > MSPI_MAX_SUPPORT_BITS) ++ { ++ return -EINVAL; ++ } ++ else if (bits_per_word > 8) ++ { ++ for (i = 0; i < MAX_WRITE_BUF_SIZE; i+=2) ++ { ++ stFrameConfig.u8WBitConfig[i] = bits_per_word - 8 -1; ++ stFrameConfig.u8WBitConfig[i+1] = 8 -1; ++ } ++ for (i = 0; i < MAX_READ_BUF_SIZE; i+=2) ++ { ++ stFrameConfig.u8RBitConfig[i] = bits_per_word - 8 -1; ++ stFrameConfig.u8RBitConfig[i+1] = 8 -1; ++ } ++ } ++ else ++ { ++ for (i = 0; i < MAX_WRITE_BUF_SIZE; i++) ++ { ++ stFrameConfig.u8WBitConfig[i] = bits_per_word -1; ++ } ++ for (i = 0; i < MAX_READ_BUF_SIZE; i++) ++ { ++ stFrameConfig.u8RBitConfig[i] = bits_per_word -1; ++ } ++ } ++ HAL_MSPI_FRAMEConfig(bs, u8Channel, &stFrameConfig); ++ ++ return 0; ++} ++ ++ ++// add to sync code from utopia for localdimming to set clk ++U32 MDrv_MSPI_SetCLK(struct mstar_spi *bs,U8 u8Channel, U32 u32MspiClk) ++{ ++ int u32SpiClk; ++ u32SpiClk = HAL_MSPI_CLK_Config(bs,(MSPI_CH)u8Channel,u32MspiClk); ++ return u32SpiClk; ++} ++ ++void mspi_config(struct mstar_spi *bs,u8 u8Channel) ++{ ++ MSPI_DCConfig stDCConfig; ++ MSPI_FrameConfig stFrameConfig; ++ MSPI_Mode_Config_e mspimode = E_MSPI_MODE0; ++ stDCConfig.u8TB = 0; ++ stDCConfig.u8TrEnd = 0x0; ++ stDCConfig.u8TrStart = 0x0; ++ stDCConfig.u8TRW = 0; ++ ++ memset(&stFrameConfig,0x07,sizeof(MSPI_FrameConfig)); ++ MDrv_MSPI_Init(bs,u8Channel,bs->u32spi_mode); ++ MDrv_MSPI_DCConfig(bs,u8Channel, &stDCConfig); ++ MDrv_MSPI_SetMode(bs,u8Channel, mspimode); ++ MDrv_MSPI_FRAMEConfig(bs,u8Channel,&stFrameConfig); ++ MDrv_MSPI_SetCLK(bs,u8Channel,54000000); //200000 CLK ++ MDrv_MSPI_ChipSelect(bs,u8Channel,0,0); ++ HAL_MSPI_SetLSB(bs,u8Channel, 0); ++ return; ++} ++ ++static irqreturn_t mstar_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_0 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++ ++#if SUPPORT_SPI_1 ++static irqreturn_t mstar_spi_interrupt_spi1(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ int uDoneFlag = 0; ++ //static int i=0; ++ ++ uDoneFlag = _HAL_MSPI_CheckDone(bs); ++ ++ if(uDoneFlag == 1){ ++ ++ complete(&bs->done); ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<<<< SPI_1 Done >>>>>>>>>>>>>>>>>\n"); ++ }else{ ++ //printk("<<<<<<<<<<<<<<<<<<< SPI Fail >>>>>>>>>>>>>>>>>\n"); ++ } ++ _HAL_MSPI_ClearDone(); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++static int mstar_spi_start_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_start_transfer]\n"); ++ ++ mspi_dbgmsg("All = %x\n",spi->mode); ++ mspi_dbgmsg("SPI mode = %d\n",spi->mode & 0x03); ++ mspi_dbgmsg("LSB first = %d\n",spi->mode & 0x08); ++ ++ //reinit_completion(&bs->done); ++ bs->tx_buf = tfr->tx_buf; ++ bs->rx_buf = tfr->rx_buf; ++ bs->len = tfr->len; ++ ++ MDrv_MSPI_ChipSelect(bs,spi->master->bus_num,1,0); ++ ++ /*if(tfr->speed_hz != NULL){ ++ MDrv_MSPI_SetCLK(_hal_msp.eCurrentCH,tfr->speed_hz); ++ }*/ ++ ++ if(bs->tx_buf != NULL){ ++ mspi_dbgmsg("bs->tx_buf=%x,%x\n",bs->tx_buf[0],bs->tx_buf[1]); ++ MDrv_MSPI_Write(bs, spi->master->bus_num,(U8 *)bs->tx_buf,(U16)bs->len); ++ } ++ ++ if(bs->rx_buf != NULL){ ++ ++ MDrv_MSPI_Read(bs,spi->master->bus_num,(U8 *)bs->rx_buf,(U16)bs->len); ++ ++ mspi_dbgmsg("bs->rx_buf=%x,%x\n",bs->rx_buf[0],bs->rx_buf[1]); ++ } ++ ++ //printk("bs->len=%d\n",bs->len); ++ ++ ++ return 0; ++} ++ ++static int mstar_spi_finish_transfer(struct spi_device *spi, ++ struct spi_transfer *tfr, bool cs_change) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ //printk("[mstar_spi_finish_transfer] cs_change=%d\n",cs_change); ++ ++#if 1 ++ ++ if (tfr->delay_usecs) ++ udelay(tfr->delay_usecs); ++ ++ if (cs_change){ ++ /* Clear TA flag */ ++ MDrv_MSPI_ChipSelect(bs,spi->master->bus_num,0,0); ++ //MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, 0xFFFF); ++ } ++#endif ++ return 0; ++} ++ ++#if SUPPORT_SPI_1 ++static struct spi_device *mstar_spi_devices[2]; ++#else ++static struct spi_device *mstar_spi_devices[1]; ++#endif ++ ++static int mstar_spi_setup(struct spi_device *spi) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(spi->master); ++ ++ mstar_spi_devices[spi->master->bus_num] = spi; ++ ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ spi->max_speed_hz = MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ return 0; ++} ++ ++static int mstar_spi_transfer_one(struct spi_master *master, ++ struct spi_message *mesg) ++{ ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ struct spi_transfer *tfr; ++ struct spi_device *spi = mesg->spi; ++ int err = 0; ++ bool cs_change; ++ ++ //mspi_dbgmsg("[mstar_spi_transfer_one]\n"); ++ ++ list_for_each_entry(tfr, &mesg->transfers, transfer_list) { ++ ++ err = mstar_spi_start_transfer(spi, tfr); ++ if (err){ ++ mspi_dbgmsg("start_transfer err\n"); ++ goto out; ++ } ++ ++ cs_change = tfr->cs_change || ++ list_is_last(&tfr->transfer_list, &mesg->transfers); ++ ++ err = mstar_spi_finish_transfer(spi, tfr, cs_change); ++ if (err){ ++ mspi_dbgmsg("finish transfer err\n"); ++ goto out; ++ } ++ mesg->actual_length += bs->len;//(tfr->len - bs->len); ++ mspi_dbgmsg("transfered:%d\n",mesg->actual_length); ++ } ++ ++out: ++ /* Clear FIFOs, and disable the HW block */ ++ mesg->status = err; ++ spi_finalize_current_message(master); ++ ++ return 0; ++} ++ ++static struct spi_master *mstar_master0; ++#if SUPPORT_SPI_1 ++static struct spi_master *mstar_master1; ++#endif ++ ++static int mstar_spi_probe(struct platform_device *pdev) ++{ ++ struct mstar_spi *bs; ++ int err; ++ unsigned int u4IO_PHY_BASE; ++ unsigned int u4spi_bank[4]; ++ int irq; ++ #if SUPPORT_SPI_1 ++ int irq2; ++ #endif ++ ++ mspi_dbgmsg("<<<<<<<<<<<<<<<<< Probe >>>>>>>>>>>>>>>\n"); ++ ++ mstar_master0 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!mstar_master0) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#if SUPPORT_SPI_1 ++ mstar_master1 = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!mstar_master1) { ++ mspi_dbgmsg( "spi_alloc_master() failed\n"); ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ return -ENOMEM; ++ } ++#endif ++ mspi_dbgmsg( "spi_alloc_master\n"); ++ platform_set_drvdata(pdev, mstar_master0); ++#if SUPPORT_SPI_1 ++ platform_set_drvdata(pdev, mstar_master1); ++#endif ++ ++ mstar_master0->mode_bits = MSTAR_SPI_MODE_BITS; ++ mstar_master0->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, MSPI_MAX_SUPPORT_BITS); ++ mstar_master0->num_chipselect = 3; ++ mstar_master0->transfer_one_message = mstar_spi_transfer_one; ++ mstar_master0->dev.of_node = pdev->dev.of_node; ++ mstar_master0->setup = mstar_spi_setup; ++ mstar_master0->max_speed_hz = 54000000; ++ mstar_master0->min_speed_hz = 46875; ++ mstar_master0->bus_num = 0; ++ ++#if SUPPORT_SPI_1 ++ mstar_master1->mode_bits = MSTAR_SPI_MODE_BITS; ++ mstar_master1->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, MSPI_MAX_SUPPORT_BITS); ++ mstar_master1->num_chipselect = 3; ++ mstar_master1->transfer_one_message = mstar_spi_transfer_one; ++ mstar_master1->dev.of_node = pdev->dev.of_node; ++ mstar_master1->setup = mstar_spi_setup; ++ mstar_master1->max_speed_hz = 54000000; ++ mstar_master1->min_speed_hz = 46875; ++ mstar_master1->bus_num = 1; ++#endif ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq); ++ if (request_irq(irq, mstar_spi_interrupt, 0, "MSPI_0 interrupt", (void*)mstar_master0) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_0 interrupt failed"); ++#if SUPPORT_SPI_1 ++ irq2 = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ mspi_dbgmsg("[MSPI] Request IRQ: %d\n", irq2); ++ if (request_irq(irq2, mstar_spi_interrupt_spi1, 0, "MSPI_1 interrupt", (void*)mstar_master1) == 0) ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt registered\n"); ++ else ++ mspi_dbgmsg("[MSPI] MSPI_1 interrupt failed"); ++#endif ++ ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4spi_bank, 4); ++ ++ mspi_dbgmsg("u4IO_PHY_BASE %x\n",u4IO_PHY_BASE); ++ mspi_dbgmsg("u4spi_bank[0] %x\n",u4spi_bank[0]); ++ mspi_dbgmsg("u4spi_bank[1] %x\n",u4spi_bank[1]); ++ mspi_dbgmsg("u4spi_bank[2] %x\n",u4spi_bank[2]); ++ mspi_dbgmsg("u4spi_bank[3] %x\n",u4spi_bank[3]); ++ ++ bs = spi_master_get_devdata(mstar_master0); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[0])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI0; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi0_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,0); ++ ++#if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(mstar_master1); ++ init_completion(&bs->done); ++ bs->VirtMspBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[1])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtClkBaseAddr = (char*)ioremap(BANK_TO_ADDR32(u4spi_bank[2])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->VirtChiptopBaseAddr =(char*)ioremap(BANK_TO_ADDR32(u4spi_bank[3])+u4IO_PHY_BASE, BANK_SIZE); ++ bs->u8channel = E_MSPI1; ++ ++ of_property_read_u32(pdev->dev.of_node, "spi1_mode", &bs->u32spi_mode); ++ ++ /* initialise the hardware */ ++ mspi_config(bs,1); ++#endif ++ ++ ++ err = devm_spi_register_master(&pdev->dev, mstar_master0); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_0 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#if SUPPORT_SPI_1 ++ err = devm_spi_register_master(&pdev->dev, mstar_master1); ++ if (err) { ++ mspi_dbgmsg( "could not register SPI_1 master: %d\n", err); ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_master_put; ++ } ++#endif ++ spi_new_device(mstar_master0, &mstar_info); ++#if SUPPORT_SPI_1 ++ spi_new_device(mstar_master1, &mstar_info); ++#endif ++ return 0; ++ ++//out_clk_disable: ++// clk_disable_unprepare(bs->clk); ++out_master_put: ++ spi_master_put(mstar_master0); ++ mspi_dbgmsg( "((((((((((( err:%d\n", err); ++ return err; ++} ++ ++static int mstar_spi_remove(struct platform_device *pdev) ++{ ++ ++#if 0 ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mstar_spi *bs = spi_master_get_devdata(master); ++ ++ /* Clear FIFOs, and disable the HW block */ ++ ++ clk_disable_unprepare(bs->clk); ++#endif ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mstar_spi_suspend(struct device *dev) ++{ ++ return 0; ++} ++ ++static int mstar_spi_resume(struct device *dev) ++{ ++ struct mstar_spi *bs; ++ struct spi_device *spi; ++ ++ bs = spi_master_get_devdata(mstar_master0); ++ mspi_config(bs, 0); ++ spi = mstar_spi_devices[0]; ++ if(spi != NULL) ++ { ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ } ++ #if SUPPORT_SPI_1 ++ bs = spi_master_get_devdata(mstar_master1); ++ mspi_config(bs, 1); ++ spi = mstar_spi_devices[1]; ++ if(spi != NULL) ++ { ++ MDrv_MSPI_SetMode(bs,bs->u8channel, spi->mode & (SPI_CPHA | SPI_CPOL)); ++ HAL_MSPI_SetLSB(bs,bs->u8channel,(spi->mode & SPI_LSB_FIRST)>>3); ++ MDrv_MSPI_SetCLK(bs,bs->u8channel,spi->max_speed_hz); ++ mspi_dbgmsg("<~~~~~~~~~~~~~~~~>SETUP :%x,speed:%d channel:%d\n",spi->mode,spi->max_speed_hz,bs->u8channel); ++ } ++ #endif ++ return 0; ++} ++ ++#else ++#define mstar_spi_suspend NULL ++#define mstar_spi_resume NULL ++#endif ++ ++static const struct of_device_id mstar_spi_match[] = { ++ { .compatible = "sstar_spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mstar_spi_match); ++ ++static const struct dev_pm_ops mstar_spi_pm_ops = { ++ .suspend = mstar_spi_suspend, ++ .resume = mstar_spi_resume, ++}; ++ ++static struct platform_driver mstar_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .pm = &mstar_spi_pm_ops, ++ .of_match_table = mstar_spi_match, ++ }, ++ .probe = mstar_spi_probe, ++ .remove = mstar_spi_remove, ++}; ++module_platform_driver(mstar_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++ +diff --git a/drivers/sstar/spinand/Kconfig b/drivers/sstar/spinand/Kconfig +new file mode 100755 +index 000000000000..196f1a45f430 +--- /dev/null ++++ b/drivers/sstar/spinand/Kconfig +@@ -0,0 +1,34 @@ ++config MS_SPINAND ++ select MTD_NAND ++ tristate "SPI NAND" ++ default n ++ ++---help--- ++Enable compilation option for driver SPI NAND Flash. ++ ++if MS_SPINAND ++choice ++ prompt "READ" ++ default AUTO_DETECT ++config NAND_SINGLE_READ ++ bool "nand-single-read" ++config NAND_DUAL_READ ++ bool "nand-dual-read" ++config NAND_QUAL_READ ++ bool "nand-qual-read" ++config AUTO_DETECT ++ bool "cis-table-determine" ++endchoice ++ ++ ++endif ++if MS_SPINAND ++choice ++ prompt "WRITE" ++ default AUTO_DETECT_WRITE ++config NAND_QUAL_WRITE ++ bool "nand-qual-write" ++config AUTO_DETECT_WRITE ++ bool "cis-table-determine" ++endchoice ++endif +diff --git a/drivers/sstar/spinand/Makefile b/drivers/sstar/spinand/Makefile +new file mode 100755 +index 000000000000..32653b8e9ad7 +--- /dev/null ++++ b/drivers/sstar/spinand/Makefile +@@ -0,0 +1,25 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++obj-$(CONFIG_MS_SPINAND) += kdrv_spinand.o ++ ++# general options ++ ++#EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/spinand/hal/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/spinand/drv/inc ++EXTRA_CFLAGS += -Idrivers/mtd ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++ifeq ($(CONFIG_SSTAR_CHIP_NAME), infinity2) ++ MHAL_SOURCE = hal/$(CONFIG_SSTAR_CHIP_NAME)/mhal_spinand.o ++else ++ MHAL_SOURCE = hal/mhal_spinand.o ++endif ++ ++kdrv_spinand-objs := drv/mdrv_spinand.o \ ++ drv/mdrv_spinand_hal.o \ ++ $(MHAL_SOURCE) \ ++ hal/$(CONFIG_SSTAR_CHIP_NAME)/mhal_spinand_chip_config.o +diff --git a/drivers/sstar/spinand/drv/inc/mdrv_spinand_command.h b/drivers/sstar/spinand/drv/inc/mdrv_spinand_command.h +new file mode 100755 +index 000000000000..96e342ba5a5d +--- /dev/null ++++ b/drivers/sstar/spinand/drv/inc/mdrv_spinand_command.h +@@ -0,0 +1,82 @@ ++/* ++* mdrv_spinand_command.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_SPINAND_COMMAND_H_ ++#define _DRV_SPINAND_COMMAND_H_ ++ ++#undef PAGE_SIZE ++ ++typedef enum ++{ ++ E_SPINAND_DBGLV_NONE, //disable all the debug message ++ E_SPINAND_DBGLV_INFO, //information ++ E_SPINAND_DBGLV_NOTICE, //normal but significant condition ++ E_SPINAND_DBGLV_WARNING, //warning conditions ++ E_SPINAND_DBGLV_ERR, //error conditions ++ E_SPINAND_DBGLV_CRIT, //critical conditions ++ E_SPINAND_ALERT, //action must be taken immediately ++ E_SPINAND_DBGLV_EMERG, //system is unusable ++ E_SPINAND_DBGLV_DEBUG, //debug-level messages ++} SPINAND_DbgLv; ++ ++#define ID1 _gtSpinandInfo.au8_ID[0] ++#define ID2 _gtSpinandInfo.au8_ID[1] ++#define ID3 _gtSpinandInfo.au8_ID[2] ++#define SPARE_SIZE _gtSpinandInfo.u16_SpareByteCnt ++#define BLOCK_PAGE_SIZE _gtSpinandInfo.u16_BlkPageCnt ++#define SECTOR_SIZE _gtSpinandInfo.u16_SectorByteCnt ++#define PAGE_SIZE _gtSpinandInfo.u16_PageByteCnt ++#define PLANE _gtSpinandInfo.u8PlaneCnt ++#define CLKCFG _gtSpinandInfo.u8CLKConfig ++#define READ_MODE _gtSpinandInfo.u8ReadMode ++#define WRITE_MODE _gtSpinandInfo.u8WriteMode ++#define BLOCKCNT _gtSpinandInfo.u16_BlkCnt ++#define DENSITY_2G 2048 ++// SPI NAND COMMAND //opcode ++#define SPI_NAND_CMD_PGRD 0x13 //page read ++#define SPI_NAND_CMD_RDID 0x9F //read ID ++#define SPI_NAND_CMD_WREN 0x06 //write enable ++#define SPI_NAND_CMD_WRDIS 0x04 //write disable ++#define SPI_NAND_CMD_RFC 0x03 //read from cache ++#define SPI_NAND_CMD_PP 0x02 //program load x2 (load program data-2kb MAX) ++#define SPI_NAND_CMD_QPP 0x32 //program load x4 (load program data-2kb MAX) ++#define SPI_NAND_CMD_RPL 0x84 //program load random data (enter cache address / data) ++#define SPI_NAND_CMD_PE 0x10 //program execute(enter block/page address, no data, execute) ++#define SPI_NAND_CMD_GF 0x0F //get feature ++#define SPI_NAND_CMD_RESET 0xFF //reset the device ++#define SPI_NAND_CMD_SF 0x1F //set features ++#define SPI_NAND_CMD_BE 0xD8 //block erase ++#define SPI_NAND_CMD_CE 0xC7 //?? ++#define SPI_NAND_CMD_DIESELECT 0xC2 ++#define SPI_NAND_REG_PROT 0xA0 //Block lock ++#define SPI_NAND_REG_FEAT 0xB0 //OTP ++#define QUAD_ENABLE 1 ++#define SPI_NAND_REG_STAT 0xC0 //Status ++ #define E_FAIL (0x01 << 2) ++ #define P_FAIL (0x01 << 3) ++ #define ECC_STATUS_PASS (0x00 << 4) ++ #define ECC_STATUS_BITFLIP (0x01 << 4) ++ #define ECC_STATUS_ERR (0x02 << 4) ++ #define SPI_NAND_STAT_OIP (0x01 << 0) ++#define SPI_NAND_REG_FUT 0xD0 ++ ++#define SPI_NAND_ADDR_LEN 3 ++#define SPI_NAND_PAGE_ADDR_LEN 2 ++#define SPI_NAND_PLANE_OFFSET 6 ++#define SPI_PLANE_ADDR_MASK 0x40 ++ ++#endif +diff --git a/drivers/sstar/spinand/drv/inc/mdrv_spinand_common.h b/drivers/sstar/spinand/drv/inc/mdrv_spinand_common.h +new file mode 100755 +index 000000000000..b5bc538a28df +--- /dev/null ++++ b/drivers/sstar/spinand/drv/inc/mdrv_spinand_common.h +@@ -0,0 +1,100 @@ ++/* ++* mdrv_spinand_common.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_SPINAND_COMMON_H_ ++#define _DRV_SPINAND_COMMON_H_ ++ ++ ++#define DEBUG_SPINAND(debug_level, x) do { if (_u8SPINANDDbgLevel >= (debug_level)) (x); } while(0) ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++#ifndef NULL ++#define NULL (void*)0 ++#endif ++#ifndef BOOL ++#define BOOL unsigned char ++#endif ++ ++typedef enum _SPINAND_ERROR_NUM ++{ ++ ERR_SPINAND_SUCCESS, ++ ERR_SPINAND_RESET_FAIL, ++ ERR_SPINAND_TIMEOUT, ++ ERR_SPINAND_BDMA_TIMEOUT, ++ ERR_SPINAND_BAD_BLK, ++ ERR_SPINAND_E_FAIL, ++ ERR_SPINAND_W_FAIL, ++ ERR_SPINAND_INVALID, ++ ERR_SPINAND_UNKNOWN_ID, ++ ERR_SPINAND_ECC_BITFLIP, ++ ERR_SPINAND_ECC_ERROR, ++} SPINAND_FLASH_ERRNO_e; ++ ++typedef enum ++{ ++ E_SPINAND_SINGLE_MODE, ++ E_SPINAND_FAST_MODE, ++ E_SPINAND_DUAL_MODE, ++ E_SPINAND_DUAL_MODE_IO, ++ E_SPINAND_QUAD_MODE, ++ E_SPINAND_QUAD_MODE_IO, ++} SPINAND_MODE; ++ ++typedef struct ++{ ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U16 u16_SectorByteCnt; ++ U8 u8PlaneCnt; ++ U8 u8WrapConfig; ++ BOOL bRIURead; ++ U8 u8CLKConfig; ++ U8 u8_UBOOTPBA; ++ U8 u8_BL0PBA; ++ U8 u8_BL1PBA; ++ U8 u8_HashPBA[3][2]; ++ U8 u8ReadMode; ++ U8 u8WriteMode; ++} SPINAND_FLASH_INFO_t; ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++#endif +diff --git a/drivers/sstar/spinand/drv/mdrv_spinand.c b/drivers/sstar/spinand/drv/mdrv_spinand.c +new file mode 100755 +index 000000000000..0622f24c62aa +--- /dev/null ++++ b/drivers/sstar/spinand/drv/mdrv_spinand.c +@@ -0,0 +1,1245 @@ ++/* ++* mdrv_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include ++#include "mdrv_spinand_command.h" ++#include "mdrv_spinand.h" ++#include "mhal_spinand.h" ++#include "../include/ms_platform.h" ++#include "mdrv_spinand_hal.h" ++#include "mtdcore.h" ++#define HERE //printk(KERN_ERR"[%s]%d\n",__FILE__,__LINE__) ++ ++//========================================================================== ++// Global Variable ++//========================================================================== ++ ++SPINAND_FLASH_INFO_t _gtSpinandInfo; ++SPI_NAND_DRIVER_t gtSpiNandDrv; ++ ++void *drvSPINAND_get_DrvContext_address(void) // exposed API ++{ ++ return >SpiNandDrv; ++} ++ ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++#include ++uint64_t u64_TotalWriteBytes; ++uint64_t u64_TotalReadBytes; ++struct proc_dir_entry * writefile; ++const char procfs_name[] = "StorageBytes"; ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static struct mstar_spinand_info *info; ++static U32 u32_curRow = 0; ++//static U32 u32_curCol = 0; ++/* These really don't belong here, as they are specific to the NAND Model */ ++static uint8_t scan_ff_pattern[] = {0xff}; ++ ++#define DRIVER_NAME "ms-spinand" ++ ++#define CACHE_LINE 0x10 ++ ++#define MS_ASSERT(a) ++//serial flash mutex wait time ++#define SPINAND_MUTEX_WAIT_TIME 3000 ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++ ++#define NAND_USE_FLASH_BBT 0x00010000 ++#define NAND_BBT_BLOCK_NUM 4 ++ ++// static spinlock_t _gtSpiNANDLock; ++ ++/* struct nand_bbt_descr - bad block table descriptor */ ++static struct nand_bbt_descr spi_nand_bbt_descr = { ++ .options = NAND_BBT_2BIT | NAND_BBT_LASTBLOCK | NAND_BBT_VERSION | NAND_BBT_CREATE | NAND_BBT_WRITE, ++ .offs = 0, ++ .len = 1, ++ .pattern = scan_ff_pattern ++}; ++ ++#if 0 ++static struct nand_ecclayout spi_nand_oobinfo = { ++ .eccbytes = 32, ++ .eccpos = {8, 9, 10, 11, 12, 13, 14, 15, ++ 24, 25, 26, 27, 28, 29, 30, 31, ++ 40, 41, 42, 43, 44, 45, 46, 47, ++ 56, 57, 58, 59, 60, 61, 62, 63}, ++ .oobavail = 30, ++ .oobfree = { ++ {2, 6}, ++ {16, 8}, ++ {32, 8}, ++ {48, 8}, ++ {0, 0} ++ }, ++}; ++#endif ++ ++static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; ++static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; ++ ++static struct nand_bbt_descr spi_nand_bbt_main_descr = { ++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | ++ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, ++ .offs = 1, ++ .len = 3, ++ .veroffs = 4, ++ .maxblocks = NAND_BBT_BLOCK_NUM, ++ .pattern = bbt_pattern ++}; ++ ++static struct nand_bbt_descr spi_nand_bbt_mirror_descr = { ++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | ++ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, ++ .offs = 1, ++ .len = 3, ++ .veroffs = 4, ++ .maxblocks = NAND_BBT_BLOCK_NUM, ++ .pattern = mirror_pattern ++}; ++ ++ ++ ++#if defined(CONFIG_MTD_CMDLINE_PARTS) || defined(CONFIG_MTD_CMDLINE_PARTS_MODULE) ++#define MTD_PARTITION_MAX 64 ++static struct mtd_partition partition_info[MTD_PARTITION_MAX]; ++#endif ++ ++void _spiNandMain(unsigned int dwSramAddress, unsigned int dwSramSize) ++{ ++ U8 u8Data[2]; ++ MDrv_SPINAND_ReadID(2,u8Data); ++} ++ ++//========================================================================== ++// Global Function for structure nand_chip and nand_ecc_ctrl ++//========================================================================== ++ ++#if 0 ++static __inline void dump_mem_line(unsigned char *buf, int cnt) ++{ ++#if 1 ++ printk(KERN_NOTICE" 0x%08lx: " \ ++ "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X \n" \ ++ , (U32)buf, ++ buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7],buf[8],buf[9],buf[10],buf[11],buf[12],buf[13],buf[14],buf[15] ++ ); ++#else ++ int i; ++ ++ printk(KERN_NOTICE" 0x%08lx: ", (U32)buf); ++ for (i= 0; i < cnt; i++) ++ printk(KERN_NOTICE"%02X ", buf[i]); ++ ++ printk(KERN_NOTICE" | "); ++ ++ for (i = 0; i < cnt; i++) ++ printk(KERN_NOTICE"%c", (buf[i] >= 32 && buf[i] < 128) ? buf[i] : '.'); ++ ++ printk(KERN_NOTICE"\n"); ++#endif ++} ++ ++void dump_mem(unsigned char *buf, int cnt) ++{ ++ int i; ++ ++ for (i= 0; i < cnt; i+= 16) ++ dump_mem_line(buf + i, 16); ++} ++#endif ++ ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++int procfile_read(char* buffer, char ** buffer_location, off_t offset, ++ int buffer_length, int *eof, void *data) ++{ ++ int ret; ++ if (offset > 0) ++ ret = 0; ++ else ++ ret = sprintf(buffer,"TotalWriteBytes %lld GB %lld MB\nTotalReadBytes %lld GB %lld MB\n", ++ u64_TotalWriteBytes/1024/1024/1024, (u64_TotalWriteBytes/1024/1024) % 1024, ++ u64_TotalReadBytes/1024/1024/1024, (u64_TotalReadBytes/1024/1024) % 1024); ++ return ret; ++} ++#endif ++ ++uint8_t spi_nand_read_byte(struct mtd_info *mtd) ++{ ++ u8 u8_word; ++ SPI_NAND_DRIVER_t *pSpiNandDrv = (SPI_NAND_DRIVER_t*)drvSPINAND_get_DrvContext_address(); ++ spi_nand_debug(""); ++ u8_word = pSpiNandDrv->pu8_sparebuf[pSpiNandDrv->u32_column]; ++ ++ if (pSpiNandDrv->u8_statusRequest) ++ { ++ /*If write protect, the status will be 0x80. Normal will return 0x0. It revert wiht P_NAND. */ ++ /*See function nand_check_wp in nand_base.c */ ++ u8_word = ~(*(pSpiNandDrv->pu8_statusbuf)); ++ } ++ pSpiNandDrv->u32_column++; ++ return u8_word; ++} ++ ++u16 spi_nand_read_word(struct mtd_info *mtd) ++{ ++ u16 u16_word; ++ ++ spi_nand_debug(""); ++ u16_word = ((u16)gtSpiNandDrv.pu8_sparebuf[gtSpiNandDrv.u32_column] | ((u16)gtSpiNandDrv.pu8_sparebuf[gtSpiNandDrv.u32_column+1]<<8)); ++ gtSpiNandDrv.u32_column += 2; ++ ++ return u16_word; ++} ++ ++void spi_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) ++{ ++ spi_nand_debug("not support"); ++} ++ ++void spi_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ++{ ++ spi_nand_debug("not support"); ++} ++ ++int spi_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) ++{ ++ spi_nand_debug("not support"); ++ ++ return 0; ++} ++ ++void spi_nand_select_chip(struct mtd_info *mtd, int chip) ++{ ++ spi_nand_debug("not support"); ++} ++ ++void spi_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) ++{ ++ spi_nand_debug("not support"); ++} ++ ++int spi_nand_dev_ready(struct mtd_info *mtd) ++{ ++ spi_nand_debug("not support"); ++ ++ return 1; ++} ++ ++void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned command, int column, int page_addr) ++{ ++ U32 ret = 0; ++ SPI_NAND_DRIVER_t *pSpiNandDrv = (SPI_NAND_DRIVER_t*)drvSPINAND_get_DrvContext_address(); ++ pSpiNandDrv->u8_statusRequest = FALSE; ++ switch (command) { ++ ++ case NAND_CMD_STATUS: ++ spi_nand_debug("NAND_CMD_STATUS"); ++ pSpiNandDrv->u8_statusRequest = TRUE; ++ ret = MDrv_SPINAND_ReadStatusRegister(pSpiNandDrv->pu8_statusbuf, SPI_NAND_REG_PROT); ++ if (ret != ERR_SPINAND_SUCCESS) ++ spi_nand_err(" ReadStatusRegister != ERR_SPINAND_SUCCESS~! %ld \n", ret); ++// gtSpiNandDrv.pu8_sparebuf[0] = NAND_STATUS_READY|NAND_STATUS_TRUE_READY; ++// gtSpiNandDrv.u32_column = 0; ++ break; ++ ++ case NAND_CMD_READOOB: ++ spi_nand_debug("NAND_CMD_READOOB"); ++ ret = MDrv_SPINAND_Read(page_addr, (U8 *)gtSpiNandDrv.pu8_pagebuf, (U8 *)gtSpiNandDrv.pu8_sparebuf); ++ ++ if ((ret != ERR_SPINAND_SUCCESS) && (ret != ERR_SPINAND_ECC_BITFLIP)) ++ { ++ spi_nand_err("MDrv_SPINAND_Read=%lx, P: %d", ret, page_addr); ++ } ++ ++ if (ret == ERR_SPINAND_ECC_ERROR) ++ { ++ mtd->ecc_stats.failed++; ++ } ++ else if (ret == ERR_SPINAND_ECC_BITFLIP) ++ { ++ mtd->ecc_stats.corrected += 1; ++ } ++ ++ gtSpiNandDrv.u32_column = column; ++ break; ++ ++ case NAND_CMD_ERASE2: ++ spi_nand_debug("NAND_CMD_ERASE2"); ++ break; ++ ++ case NAND_CMD_ERASE1: ++ spi_nand_debug("NAND_CMD_ERASE1"); ++// spi_nand_msg("NAND_CMD_ERASE1, page_addr: 0x%X\n", page_addr); ++ gtSpiNandDrv.u8_status = NAND_STATUS_READY|NAND_STATUS_TRUE_READY; ++ ret = MDrv_SPINAND_BLOCK_ERASE(page_addr); ++ if (ret != ERR_SPINAND_SUCCESS) ++ { ++ spi_nand_err("MDrv_SPINAND_Erase= %ld \n", ret); ++ gtSpiNandDrv.u8_status |= NAND_STATUS_FAIL; ++ } ++ break; ++ ++ case NAND_CMD_RESET: //add this to avoid print "unsupported command" fo jffs2 ++ spi_nand_debug("NAND_CMD_RESET"); ++ break; ++ ++ case NAND_CMD_READ0: ++ spi_nand_debug("NAND_CMD_READ0"); ++ u32_curRow = page_addr; ++// u32_curCol = column; //set not used ++ break; ++ ++ default: ++ spi_nand_err("unsupported command %02Xh", command); ++ break; ++ } ++ ++} ++ ++int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) ++{ ++ spi_nand_debug(""); ++ ++ return (int)gtSpiNandDrv.u8_status; ++} ++ ++int spi_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, ++ uint32_t offset, int data_len, const uint8_t *buf, ++ int oob_required, int page, int cached, int raw) ++{ ++ U32 ret; ++ ++ spi_nand_debug("0x%X", page); ++ ++ ret = MDrv_SPINAND_Write(page, (U8 *)buf, (U8 *)chip->oob_poi); ++ if (ret != ERR_SPINAND_SUCCESS) ++ { ++ spi_nand_err("MDrv_SPINAND_Write=%ld", ret); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++void spi_nand_ecc_hwctl(struct mtd_info *mtd, int mode) ++{ ++ spi_nand_debug("not support"); ++} ++ ++int spi_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) ++{ ++ spi_nand_debug("not support"); ++ ++ return 0; ++} ++ ++int spi_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) ++{ ++ spi_nand_debug("not support"); ++ ++ return 0; ++} ++ ++int spi_nand_ecc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int oob_required, int page) ++{ ++ U32 ret; ++ U8 *u8_DmaBuf = buf; ++ ++ spi_nand_debug("0x%X", page); ++ ++#if defined(CONFIG_MIPS) ++ if ( ((U32)buf) >= 0xC0000000 || ((U32)buf) % CACHE_LINE ) ++#elif defined(CONFIG_ARM) ++ if (!virt_addr_valid((U32)buf) || !virt_addr_valid((U32)buf + (U32)mtd->writesize - 1) || ((U32)buf) % CACHE_LINE ) ++#endif ++ { ++ spi_nand_debug("Receive Virtual Mem:%08lXh", (U32)buf); ++ u8_DmaBuf = gtSpiNandDrv.pu8_pagebuf; ++ } ++ ++ ret = MDrv_SPINAND_Read(page, (U8 *)u8_DmaBuf, (U8 *)chip->oob_poi); ++ ++ if(ret == ERR_SPINAND_ECC_ERROR) ++ { ++// spi_nand_err("MDrv_SPINAND_Read=%x, P: 0x%x", ret, page); ++ mtd->ecc_stats.failed++; ++ } ++ else if(ret == ERR_SPINAND_ECC_BITFLIP) ++ { ++ mtd->ecc_stats.corrected += 1; ++ } ++ if (u8_DmaBuf != buf) ++ { ++ memcpy((void *) buf, (const void *) u8_DmaBuf, mtd->writesize); ++ } ++ ++ return 0; ++} ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ++int spi_nand_ecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required) ++#else ++int spi_nand_ecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required, int page) ++#endif ++{ ++ spi_nand_debug("not support"); ++ return 0; ++} ++ ++int spi_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int oob_required, int page) ++{ ++ U32 ret; ++ U8 *u8_DmaBuf = buf; ++ ++// spi_nand_msg("0x%X", page); ++ ++#if defined(CONFIG_MIPS) ++ if ( ((U32)buf) >= 0xC0000000 || ((U32)buf) % CACHE_LINE ) ++#elif defined(CONFIG_ARM) ++ if (!virt_addr_valid((U32)buf) || !virt_addr_valid((U32)buf + (U32)mtd->writesize - 1) || ((U32)buf) % CACHE_LINE ) ++#endif ++ { ++// spi_nand_msg("Receive Virtual Mem:%08lXh", (U32)buf); ++ u8_DmaBuf = gtSpiNandDrv.pu8_pagebuf; ++ } ++ ++ ret = MDrv_SPINAND_Read(page, (U8 *)u8_DmaBuf, (U8 *)chip->oob_poi); ++ ++ if(ret == ERR_SPINAND_ECC_ERROR) ++ { ++ spi_nand_err("MDrv_SPINAND_Read=0x%lx, P: %d", ret, page); ++ mtd->ecc_stats.failed++; ++ } ++ else if(ret == ERR_SPINAND_ECC_BITFLIP) ++ { ++ mtd->ecc_stats.corrected += 1; ++ } ++ ++ if (u8_DmaBuf != buf) ++ { ++ memcpy((void *) buf, (const void *) u8_DmaBuf, mtd->writesize); ++ } ++ ++ return 0; ++} ++ ++int spi_nand_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, ++ uint32_t offs, uint32_t len, uint8_t *buf, int page) ++{ ++ U32 ret = 0; ++ U8 *u8_DmaBuf; ++ ++ buf += offs; ++ u8_DmaBuf = buf; ++ ++#if defined(CONFIG_MIPS) ++ if ( ((U32)buf) >= 0xC0000000 || ((U32)buf) % CACHE_LINE ) ++#elif defined(CONFIG_ARM) ++ if (!virt_addr_valid((U32)buf) || !virt_addr_valid((U32)buf + (U32)mtd->writesize - 1) || ((U32)buf) % CACHE_LINE ) ++#endif ++ { ++// spi_nand_msg("Receive Virtual Mem:%08lXh", (U32)buf); ++ u8_DmaBuf = gtSpiNandDrv.pu8_pagebuf; ++ } ++ ++ ret = MDrv_SPINAND_Read_RandomIn(u32_curRow, offs, len, u8_DmaBuf); ++ ++ if (ret == ERR_SPINAND_SUCCESS) ++ { ++ //printk("read subpage %ld success\n", u32_curRow); ++ } ++ else if (ret == ERR_SPINAND_ECC_ERROR) ++ { ++ mtd->ecc_stats.failed++; ++ } ++ else if (ret == ERR_SPINAND_ECC_BITFLIP) ++ { ++ mtd->ecc_stats.corrected += 1; ++ } ++ ++ if (u8_DmaBuf != buf) ++ { ++ memcpy((void *) buf, (const void *) u8_DmaBuf, len); ++ } ++ ++ return 0; ++} ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ++int spi_nand_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required) ++#else ++int spi_nand_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required, int page) ++#endif ++{ ++ spi_nand_debug("not support"); ++ return 0; ++} ++ ++int spi_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page) ++{ ++ U32 ret; ++// spi_nand_msg("0x%X", page); ++ ++ ret = MDrv_SPINAND_Read(page, (U8 *)gtSpiNandDrv.pu8_pagebuf, (U8 *)chip->oob_poi); ++ ++ if (ret == ERR_SPINAND_ECC_ERROR) ++ { ++ spi_nand_err("MDrv_SPINAND_Read=%ld", ret); ++ ret = MDrv_SPINAND_Read(page, (U8 *)gtSpiNandDrv.pu8_pagebuf, (U8 *)chip->oob_poi); ++ spi_nand_err("MDrv_SPINAND_Read retry=%ld", ret); ++ } ++ ++ return 0; ++} ++ ++int spi_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page) ++{ ++#if 1 ++ spi_nand_debug("0x%X", page); ++ ++ //printk("write page 0x%X's oob, writesize(%d) oobsize(%d)\n", page, mtd->writesize, mtd->oobsize); ++ if (ERR_SPINAND_SUCCESS != MDrv_SPINAND_program(page, mtd->writesize, chip->oob_poi, mtd->oobsize)) ++ { ++ spi_nand_err("MDrv_SPINAND_program err!\n"); ++ return -EIO; ++ } ++ ++#else ++ U32 ret; ++ ++ memset((void *)gtSpiNandDrv.pu8_pagebuf, 0xFF, mtd->writesize); ++ ret = MDrv_SPINAND_Write(page, (U8 *)gtSpiNandDrv.pu8_pagebuf, (U8 *)chip->oob_poi); ++ if (ret != ERR_SPINAND_SUCCESS) ++ { ++ spi_nand_err("MDrv_SPINAND_Write=%ld", ret); ++ return -EIO; ++ } ++ ++#endif ++ return 0; ++} ++ ++static U32 _checkSum(U8 *pu8_Data, U16 u16_ByteCnt) ++{ ++ U32 u32_Sum = 0; ++ ++ while (u16_ByteCnt--) ++ u32_Sum += *pu8_Data++; ++ ++ return u32_Sum; ++} ++ ++static void _addSstarPartition(struct mtd_info* mtd, SPI_NAND_PARTITION_INFO_t *pPartInfo) ++{ ++ U32 u32_BlkSize; ++ SPI_NAND_PARTITION_RECORD_t *pRecord; ++ U8 u8_PartNo; ++ U16 u16_LastPartType; ++ int NumOfPart; ++ int nMaxRec = sizeof(pPartInfo->records) / sizeof(pPartInfo->records[0]); ++ BOOL bLogic = FALSE; ++ U16 nPartTypeNoFlag; ++ ++ u32_BlkSize = (U32)gtSpiNandDrv.tSpinandInfo.u16_PageByteCnt * (U32)gtSpiNandDrv.tSpinandInfo.u16_BlkPageCnt; ++ pRecord = pPartInfo->records; ++ u16_LastPartType = 0xFFFF; ++ u8_PartNo = 0; ++ NumOfPart = 0; ++ while(pRecord - pPartInfo->records < pPartInfo->u16_PartCnt) ++ { ++ if((pRecord->u16_PartType & UNFD_LOGI_PART) == UNFD_LOGI_PART) ++ { ++ bLogic = TRUE; ++ } ++ else ++ { ++ bLogic = FALSE; ++ } ++ if((pRecord->u16_PartType & UNFD_HIDDEN_PART) == UNFD_HIDDEN_PART) ++ { ++ pRecord++; ++ continue; ++ } ++ if (pRecord - pPartInfo->records >= nMaxRec) break; ++ nPartTypeNoFlag = pRecord->u16_PartType & 0x0FFF; ++ ++ if( u16_LastPartType == pRecord->u16_PartType) ++ u8_PartNo++; ++ else ++ u8_PartNo = 0; ++ ++ u16_LastPartType = pRecord->u16_PartType; ++ ++ switch(nPartTypeNoFlag) ++ { ++ case UNFD_PART_IPL_CUST: ++ if(u8_PartNo == 0) ++ partition_info[NumOfPart].name = "IPL_CUST0"; ++ else ++ partition_info[NumOfPart].name = "IPL_CUST1"; ++ break; ++ case UNFD_PART_BOOTLOGO: ++ partition_info[NumOfPart].name = "BOOTLOGO"; ++ break; ++ case UNFD_PART_IPL: ++ if(u8_PartNo == 0) ++ partition_info[NumOfPart].name = "IPL0"; ++ else ++ partition_info[NumOfPart].name = "IPL1"; ++ break; ++ case UNFD_PART_OS: ++ partition_info[NumOfPart].name = "OS"; ++ break; ++ case UNFD_PART_CUS: ++ partition_info[NumOfPart].name = "CUS"; ++ break; ++ case UNFD_PART_UBOOT: ++ if(u8_PartNo == 0) ++ partition_info[NumOfPart].name = "UBOOT0"; ++ else ++ partition_info[NumOfPart].name = "UBOOT1"; ++ break; ++ case UNFD_PART_SECINFO: ++ partition_info[NumOfPart].name = "SECINFO"; ++ break; ++ case UNFD_PART_OTP: ++ partition_info[NumOfPart].name = "OTP"; ++ break; ++ case UNFD_PART_RTOS: ++ partition_info[NumOfPart].name = "RTOS"; ++ break; ++ case UNFD_PART_RTOS_BACKUP: ++ partition_info[NumOfPart].name = "RTOS_BACKUP"; ++ break; ++ case UNFD_PART_KERNEL: ++ partition_info[NumOfPart].name = "KERNEL"; ++ break; ++ case UNFD_PART_UBI: ++ partition_info[NumOfPart].name = "UBI"; ++ break; ++ case UNFD_PART_KERNEL_BACKUP: ++ partition_info[NumOfPart].name = "KERNEL_BACKUP"; ++ break; ++ case UNFD_PART_RECOVERY: ++ partition_info[NumOfPart].name = "RECOVERY"; ++ break; ++ case UNFD_PART_E2PBAK: ++ partition_info[NumOfPart].name = "E2PBAK"; ++ break; ++ case UNFD_PART_NVRAMBAK: ++ partition_info[NumOfPart].name = "NVRAMBAK"; ++ break; ++ case UNFD_PART_NPT: ++ partition_info[NumOfPart].name = "NPT"; ++ break; ++ case UNFD_PART_ENV: ++ partition_info[NumOfPart].name = "ENV"; ++ break; ++ case UNFD_PART_MISC: ++ partition_info[NumOfPart].name = "MISC"; ++ break; ++ default: ++ if(nPartTypeNoFlag >= UNFD_PART_CUST0 && ++ nPartTypeNoFlag <= UNFD_PART_CUSTf) ++ { ++ partition_info[NumOfPart].name = "CUST"; ++ } ++ else ++ { ++ partition_info[NumOfPart].name = "UNKNOWN"; ++ } ++ break; ++ } ++ partition_info[NumOfPart].offset = (U32)(pRecord->u16_StartBlk * u32_BlkSize); ++ partition_info[NumOfPart].size = (U32)((pRecord->u16_BlkCnt+pRecord->u16_BackupBlkCnt)*u32_BlkSize); ++ partition_info[NumOfPart].mask_flags = 0; ++ printk("%s:%llX, %llX\n", partition_info[NumOfPart].name, ++ partition_info[NumOfPart].offset, ++ partition_info[NumOfPart].size); ++ NumOfPart++; ++ pRecord++; ++ }// while ++ pRecord--; ++ if(pRecord->u16_PartType == 0xC000) ++ { ++ partition_info[NumOfPart].name = "UBI"; ++ partition_info[NumOfPart].offset = (U32)(pRecord->u16_StartBlk * u32_BlkSize); ++ partition_info[NumOfPart].size = (U32)((gtSpiNandDrv.tSpinandInfo.u16_BlkCnt - pRecord->u16_StartBlk) * u32_BlkSize); ++ partition_info[NumOfPart].mask_flags = 0; ++ printk("%s:%llX, %llX\n", partition_info[NumOfPart].name, ++ partition_info[NumOfPart].offset, ++ partition_info[NumOfPart].size); ++ NumOfPart++; ++ } ++ printk("parse_mtd_partitions from CIS ok\n"); ++ add_mtd_partitions(mtd, partition_info, NumOfPart); ++ ++} ++ ++#ifdef CONFIG_CAM_CLK ++ #include "drv_camclk_Api.h" ++ void **pvSpinandclk = NULL; ++ u32 SpinandParentCnt = 1; ++ ++u8 spinand_ClkRegister( struct device *dev) ++{ ++ u32 u32clknum; ++ u32 SpinandClk; ++ u8 str[16]; ++ ++ if(of_find_property(dev->of_node,"camclk",&SpinandParentCnt)) ++ { ++ SpinandParentCnt /= sizeof(int); ++ //printk( "[%s] Number : %d\n", __func__, num_parents); ++ if(SpinandParentCnt < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, SpinandParentCnt); ++ return 0; ++ } ++ pvSpinandclk = kzalloc((sizeof(void *) * SpinandParentCnt), GFP_KERNEL); ++ if(!pvSpinandclk){ ++ return 0; ++ } ++ for(u32clknum = 0; u32clknum < SpinandParentCnt; u32clknum++) ++ { ++ SpinandClk = 0; ++ of_property_read_u32_index(dev->of_node,"camclk", u32clknum,&(SpinandClk)); ++ if (!SpinandClk) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ CamOsSnprintf(str, 16, "spinand_%d ",u32clknum); ++ CamClkRegister(str,SpinandClk,&(pvSpinandclk[u32clknum])); ++ } ++ } ++ } ++ else ++ { ++ printk( "[%s] W/O Camclk \n", __func__); ++ } ++ return 1; ++} ++u8 spinand_ClkUnregister(void) ++{ ++ ++ u32 u32clknum; ++ ++ for(u32clknum=0;u32clknumdev); ++ for(u32clknum = 0; u32clknum < SpinandParentCnt; u32clknum++) ++ { ++ if (pvSpinandclk[u32clknum]) ++ { ++ CamClkSetOnOff(pvSpinandclk[u32clknum],1); ++ } ++ } ++#else ++ int num_parents, i; ++ struct clk **spinand_clks; ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ spinand_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ if(spinand_clks == NULL) ++ { ++ printk( "[SPINAND]kzalloc failed!\n" ); ++ return; ++ } ++ ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spinand_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spinand_clks[i])) ++ { ++ spi_nand_err( "[SPINAND] Fail to get clk!\n" ); ++ kfree(spinand_clks); ++ return ; ++ } ++ else ++ { ++ clk_prepare_enable(spinand_clks[i]); ++ } ++ clk_put(spinand_clks[i]); ++ } ++ kfree(spinand_clks); ++ } ++#endif ++} ++ ++void _disableClock(struct platform_device *pdev) ++{ ++#ifdef CONFIG_CAM_CLK ++ u32 u32clknum = 0; ++ ++ for(u32clknum = 0; u32clknum < SpinandParentCnt; u32clknum++) ++ { ++ if (pvSpinandclk[u32clknum]) ++ { ++ CamClkSetOnOff(pvSpinandclk[u32clknum],0); ++ } ++ } ++ spinand_ClkUnregister(); ++#else ++ int num_parents, i; ++ struct clk **spinand_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ spinand_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ if(spinand_clks == NULL) ++ { ++ printk( "[SPINAND]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spinand_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spinand_clks[i])) ++ { ++ printk( "[SPINAND] Fail to get clk!\n" ); ++ kfree(spinand_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(spinand_clks[i]); ++ } ++ clk_put(spinand_clks[i]); ++ } ++ kfree(spinand_clks); ++ } ++#endif ++} ++ ++static void _dumpNandInformation(void) ++{ ++// spi_nand_warn("u8_SectorByteCntBits %d", pSpiNandDrv->u8_SectorByteCntBits); ++// spi_nand_warn("u8_PageSectorCntBits %d", pSpiNandDrv->u8_PageSectorCntBits); ++// spi_nand_warn("u8_PageByteCntBits %d", pSpiNandDrv->u8_PageByteCntBits); ++// spi_nand_warn("u8_BlkPageCntBits %d", pSpiNandDrv->u8_BlkPageCntBits); ++ spi_nand_warn("Bytes / Page : %d", gtSpiNandDrv.tSpinandInfo.u16_PageByteCnt); ++ spi_nand_warn("Pages / Block: %d", gtSpiNandDrv.tSpinandInfo.u16_BlkPageCnt); ++ spi_nand_warn("Sector/ Page : %d", gtSpiNandDrv.tSpinandInfo.u16_SectorByteCnt); ++ spi_nand_warn("Spare / Page : %d", gtSpiNandDrv.tSpinandInfo.u16_SpareByteCnt); ++ { ++ int read = 1, write = 1, drv = 1; ++#if defined(CONFIG_NAND_QUAL_READ) ++ read = 4; ++#endif ++#if defined(CONFIG_NAND_QUAL_WRITE) ++ write = 4; ++#endif ++#if defined(SUPPORT_SPINAND_QUAD) && (SUPPORT_SPINAND_QUAD) ++ drv = 4; ++#endif ++ spi_nand_warn("Current config r:%d w:%d drv:%d", read, write, drv); ++ } ++} ++ ++int _ms_mtd_param_init(struct mtd_info *mtd, ++ struct nand_chip *chip, ++ int *maf_id, int *dev_id, ++ const struct nand_flash_dev *type) ++{ ++ SPI_NAND_DRIVER_t *pNandDrv = (SPI_NAND_DRIVER_t*)drvSPINAND_get_DrvContext_address(); ++ ++ if (!mtd->name) ++ mtd->name = "nand0"; ++ HERE; ++ mtd->writesize = pNandDrv->tSpinandInfo.u16_PageByteCnt; ++ mtd->oobsize = pNandDrv->tSpinandInfo.u16_SpareByteCnt; ++ mtd->erasesize = pNandDrv->tSpinandInfo.u16_BlkPageCnt * pNandDrv->tSpinandInfo.u16_PageByteCnt; ++ chip->chipsize = (uint64_t)pNandDrv->tSpinandInfo.u16_BlkCnt * (uint64_t)pNandDrv->tSpinandInfo.u16_BlkPageCnt * (uint64_t)pNandDrv->tSpinandInfo.u16_PageByteCnt; ++ ++ if(!mtd->writesize || !mtd->oobsize || !mtd->erasesize) ++ { ++ int i; ++ printk("Unsupported NAND Flash type is detected with ID"); ++ for(i = 0; i < pNandDrv->tSpinandInfo.u8_IDByteCnt; i++) ++ printk(" 0x%X", pNandDrv->tSpinandInfo.au8_ID[i]); ++ printk("\n"); ++ return (-EINVAL); ++ } ++ chip->onfi_version = 0; ++ ++ /* Get chip options */ ++ chip->options = NAND_NO_SUBPAGE_WRITE; ++ ++ /* ++ ** Set chip as a default. Board drivers can override it, if necessary ++ **/ ++ ++ if(0) ++ chip->options |= NAND_BUSWIDTH_16; ++ ++ /* Calculate the address shift from the page size */ ++ chip->page_shift = ffs(mtd->writesize) - 1; ++ ++ /* Convert chipsize to number of pages per chip -1. */ ++ chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; ++ chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1; ++ ++ if (chip->chipsize & 0xffffffff) ++ chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; ++ else ++ chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31; ++ ++ /* Set the bad block position */ ++ chip->badblockpos = mtd->writesize > 512 ? NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; ++ chip->options |= NAND_SKIP_BBTSCAN; ++ chip->badblockbits = 8; ++ chip->bits_per_cell = 1; ++ ++ return 0; ++ ++} ++ ++// #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,1) ++// static int __init mstar_spinand_probe(struct platform_device *pdev) ++// #else ++// static int __devinit mstar_spinand_probe(struct platform_device *pdev) ++// #endif ++ ++static int mstar_spinand_probe(struct platform_device *pdev) ++{ ++ U8 u8_i; ++ U32 u32_ret; ++ SPI_NAND_PARTITION_INFO_t *ptPartInfo; ++ struct nand_chip *nand; ++ struct mtd_info* mtd; ++ int err = 0; ++ ++#if defined(CONFIG_MTD_CMDLINE_PARTS) || defined(CONFIG_MTD_CMDLINE_PARTS_MODULE) ++ static const char *part_probes[] = { "cmdlinepart", NULL, }; ++#endif ++#if defined(CONFIG_ARCH_INFINITY2) ++ if(Chip_Get_Storage_Type()!= MS_STORAGE_SPINAND_ECC) ++ return 0; ++#endif ++ _enableClock(pdev); ++ spi_nand_msg("mstar_spinand enableClock"); ++ ++ /* Allocate memory for MTD device structure and private data */ ++ info = kzalloc(sizeof(struct mstar_spinand_info), GFP_KERNEL); ++ ++ if (!info) ++ { ++ spi_nand_err("Allocate Sstar spi nand info fail\n"); ++ return -ENOMEM; ++ } ++ platform_set_drvdata(pdev, info); ++ ++ /* Get pointer to private data */ ++ info->pdev = pdev; ++ nand = &info->nand; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ++ mtd = &info->mtd; ++ /* Get pointer to private data */ ++ ++ /* Initialize structures */ ++ mtd->priv = nand; ++#else ++ mtd = &nand->mtd; ++ /* Initialize structures */ ++ mtd->priv = nand; ++#endif ++ //mtd->name = dev_name(&pdev->dev); ++ mtd->name = "nand0"; ++ mtd->owner = THIS_MODULE; ++ ++ MDrv_SPINAND_Device(&pdev->dev); ++ ++ if (MDrv_SPINAND_Init(&(gtSpiNandDrv.tSpinandInfo)) != TRUE) ++ { ++ spi_nand_err("MDrv_SPINAND_Init fail"); ++ return -ENODEV; ++ } ++ _dumpNandInformation(); ++ gtSpiNandDrv.u8_status = NAND_STATUS_READY|NAND_STATUS_TRUE_READY; ++ gtSpiNandDrv.u32_column = 0; ++ gtSpiNandDrv.pu8_pagebuf = kmalloc(gtSpiNandDrv.tSpinandInfo.u16_PageByteCnt, GFP_KERNEL); ++ gtSpiNandDrv.pu8_sparebuf = kmalloc(gtSpiNandDrv.tSpinandInfo.u16_SpareByteCnt, GFP_KERNEL); ++ gtSpiNandDrv.pu8_statusbuf = kmalloc(16, GFP_KERNEL); ++ ++ if (!gtSpiNandDrv.pu8_pagebuf || !gtSpiNandDrv.pu8_sparebuf) ++ { ++ spi_nand_err("Can not alloc memory for page/spare buffer"); ++ return -ENOMEM; ++ } ++ ++ ptPartInfo = (SPI_NAND_PARTITION_INFO_t *)gtSpiNandDrv.pu8_pagebuf; ++ for (u8_i=0 ; u8_i<2 ; u8_i+=2) ++ { ++ u32_ret = MDrv_SPINAND_Read(u8_i*gtSpiNandDrv.tSpinandInfo.u16_BlkPageCnt, gtSpiNandDrv.pu8_pagebuf, gtSpiNandDrv.pu8_sparebuf); ++ if (u32_ret == ERR_SPINAND_SUCCESS) ++ { ++ if (memcmp((const void *) gtSpiNandDrv.pu8_pagebuf, SPINAND_FLASH_INFO_TAG, 16) == 0) ++ { ++ spi_nand_msg("Magic memcmp pass"); ++ spi_nand_msg("Get partition (Block 0 : page 1)"); ++ u32_ret = MDrv_SPINAND_Read(u8_i*gtSpiNandDrv.tSpinandInfo.u16_BlkPageCnt + 1, gtSpiNandDrv.pu8_pagebuf, gtSpiNandDrv.pu8_sparebuf); ++ if (u32_ret == ERR_SPINAND_SUCCESS) ++ { ++ U32 checkresult = 0; ++ checkresult = _checkSum((u8*)&(ptPartInfo->u16_SpareByteCnt), 0x200 - 0x04); ++ if (ptPartInfo->u32_ChkSum == checkresult) ++ break; ++ } ++ } ++ } ++ } ++ ++ if (u8_i == 10) ++ { ++ spi_nand_err("CIS doesn't contain part info"); ++ gtSpiNandDrv.u8_HasPNI = 0; ++ } ++ else ++ { ++ spi_nand_msg("CIS contains part info"); ++ gtSpiNandDrv.u8_HasPNI = 1; ++ memcpy((void *)>SpiNandDrv.tPartInfo, (const void *) ptPartInfo, 0x200); ++ } ++ ++ /* please refer to include/linux/nand.h for more info. */ ++ nand->read_byte = spi_nand_read_byte; ++ nand->read_word = spi_nand_read_word; ++ nand->write_buf = spi_nand_write_buf; ++ nand->read_buf = spi_nand_read_buf; ++ nand->select_chip = spi_nand_select_chip; ++ nand->cmd_ctrl = spi_nand_cmd_ctrl; ++ nand->dev_ready = spi_nand_dev_ready; ++ nand->cmdfunc = spi_nand_cmdfunc; ++ nand->waitfunc = spi_nand_waitfunc; ++ nand->write_page = spi_nand_write_page; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,1) ++ nand->bbt_options = NAND_BBT_USE_FLASH; ++#else ++ nand->options = NAND_USE_FLASH_BBT; ++#endif ++ nand->chip_delay = 0; ++ nand->badblock_pattern = &spi_nand_bbt_descr; //using default badblock pattern. ++ nand->bbt_td = &spi_nand_bbt_main_descr; ++ nand->bbt_md = &spi_nand_bbt_mirror_descr; ++ nand->mtd_param_init = _ms_mtd_param_init; ++ nand->ecc.mode = NAND_ECC_HW; ++ nand->ecc.size = gtSpiNandDrv.tSpinandInfo.u16_PageByteCnt; ++ nand->ecc.bytes = (gtSpiNandDrv.tSpinandInfo.u16_SpareByteCnt>>1); ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,1) ++ nand->ecc.strength = 4; ++#endif ++#if 0 ++ nand->ecc.layout = &spi_nand_oobinfo; ++#endif ++ nand->ecc.hwctl = spi_nand_ecc_hwctl; ++ nand->ecc.calculate = spi_nand_ecc_calculate; ++ nand->ecc.correct = spi_nand_ecc_correct; ++ nand->ecc.read_page_raw = spi_nand_ecc_read_page_raw; ++ nand->ecc.write_page_raw = spi_nand_ecc_write_page_raw; ++ nand->ecc.read_page = spi_nand_ecc_read_page; ++ nand->ecc.read_subpage = spi_nand_ecc_read_subpage; ++ nand->ecc.write_page = spi_nand_ecc_write_page; ++ nand->ecc.read_oob = spi_nand_ecc_read_oob; ++ nand->ecc.write_oob = spi_nand_ecc_write_oob; ++// nand->options |= NAND_IS_SPI; ++ nand->options |= NAND_CACHEPRG; ++ nand->bits_per_cell = 1; ++ pr_info("%s: Before nand_scan()...\n",__FUNCTION__); ++ ++ if ((err = nand_scan(mtd, 1)) != 0) ++ { ++ spi_nand_err("can't register SPI NAND\n"); ++ kfree(mtd); ++ return -ENOMEM; ++ } ++ ++#if defined(CONFIG_MTD_CMDLINE_PARTS) || defined(CONFIG_MTD_CMDLINE_PARTS_MODULE) ++// #ifdef CONFIG_MTD_PARTITIONS ++ { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,5,0) ++ struct mtd_partitions pparts; ++ err = parse_mtd_partitions(mtd, part_probes, &pparts, 0); ++ ++ if((!err) && (pparts.nr_parts > 0)) ++ { ++ spi_nand_msg( "Mtd parts parse"); ++ add_mtd_partitions(mtd, pparts.parts, pparts.nr_parts); ++ } ++ else if (IS_ERR_VALUE(err)) ++ { ++ spi_nand_msg("parse_mtd_partitions error!!! %d\r\n", err); ++ } ++#else ++ int mtd_parts_nb = 0; ++ mtd_parts_nb = parse_mtd_partitions(mtd, part_probes, &info->parts, 0); ++ if (mtd_parts_nb > 0) ++ { ++ spi_nand_msg( "Mtd parts default"); ++ add_mtd_partitions(mtd, info->parts, mtd_parts_nb); ++ } ++#endif ++ else ++ { ++ spi_nand_msg( "Add Sstar Partition"); ++ _addSstarPartition(mtd,ptPartInfo); ++ } ++ } ++#else ++ add_mtd_partitions(mtd, NULL, 0); ++#endif ++ ++ platform_set_drvdata(pdev, &info->mtd); ++ ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++ u64_TotalWriteBytes = u64_TotalReadBytes = 0; ++ writefile = proc_create (procfs_name, 0644, NULL); ++ ++ if (writefile == NULL) ++ printk(KERN_CRIT"Error: Can not initialize /proc/%s\n", procfs_name); ++ else ++ { ++ writefile->read_proc = procfile_read; ++ writefile->mode = S_IFREG | S_IRUGO; ++ writefile->uid = 0; ++ writefile->gid = 0; ++ writefile->size = 0x10; ++ } ++#endif ++ return 0; ++} ++ ++static int mstar_spinand_remove(struct platform_device *pdev) ++{ ++ platform_set_drvdata(pdev, NULL); ++ ++ /* Release NAND device, its internal structures and partitions */ ++ nand_release(&info->mtd); ++ kfree(info); ++ kfree(gtSpiNandDrv.pu8_pagebuf); ++ kfree(gtSpiNandDrv.pu8_sparebuf); ++ kfree(gtSpiNandDrv.pu8_statusbuf); ++ _disableClock(pdev); ++ return 0; ++} ++ ++static const struct of_device_id spinand_of_dt_ids[] = ++{ ++ { .compatible = "ms-spinand" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spinand_of_dt_ids); ++ ++static struct platform_driver mstar_spinand_driver = { ++ .probe = mstar_spinand_probe, ++ .remove = mstar_spinand_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = (spinand_of_dt_ids), ++ }, ++}; ++module_platform_driver(mstar_spinand_driver); ++ ++#if (0) ++static int __init mstar_spinand_init(void) ++{ ++ int err = 0; ++ printk("mstar_spinand_init\n"); ++ if (MDrv_SPINAND_IsActive() == 0) ++ { ++ pr_info("%s device not found\n", DRIVER_NAME); ++ return -ENODEV; ++ } ++ ++ pr_info("%s driver initializing\n", DRIVER_NAME); ++ ++// err = platform_device_register(&mstar_spinand_deivce_st); ++ if (err < 0) ++ spi_nand_err("SPI NAND Err: platform device register fail %d\n", err); ++ ++ return platform_driver_register(&mstar_spinand_driver); ++} ++ ++static void __exit mstar_spinand_exit(void) ++{ ++ platform_driver_unregister(&mstar_spinand_driver); ++} ++ ++module_init(mstar_spinand_init); ++module_exit(mstar_spinand_exit); ++#endif ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("Sstar MTD SPI NAND driver"); +diff --git a/drivers/sstar/spinand/drv/mdrv_spinand.h b/drivers/sstar/spinand/drv/mdrv_spinand.h +new file mode 100755 +index 000000000000..d14a91930f01 +--- /dev/null ++++ b/drivers/sstar/spinand/drv/mdrv_spinand.h +@@ -0,0 +1,175 @@ ++/* ++* mdrv_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _DRV_SPINAND_H_ ++#define _DRV_SPINAND_H_ ++#include ++#include "inc/mdrv_spinand_common.h" ++//#include "../hal/reg_spinand.h" ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#define MID_GD 0xC8 ++#define MID_MICRON 0x2C ++#define MID_ATO 0x9B ++#define MID_WINBOND 0xEF ++#define MID_MXIC 0xC2 ++#define MID_TOSHIBA 0x98 ++#define MID_FORESEE 0xCD ++ ++/* SPI NAND messages */ ++#if 1 ++#define spi_nand_msg(fmt, ...) printk(KERN_NOTICE "%s: " fmt "\n", __func__, ##__VA_ARGS__) ++#define spi_nand_debug(fmt, ...) ++#else ++#define spi_nand_msg(fmt, ...) ++#define spi_nand_debug(fmt, ...) printk(KERN_NOTICE "%s: " fmt "\n", __func__, ##__VA_ARGS__) ++#endif ++#define spi_nand_warn(fmt, ...) printk(KERN_WARNING "%s:warning, " fmt "\n", __func__, ##__VA_ARGS__) ++#define spi_nand_err(fmt, ...) printk(KERN_ERR "%s:error, " fmt "\n", __func__, ##__VA_ARGS__) ++ ++#define SPINAND_FLASH_INFO_TAG "MSTARSEMIUSFDCIS" ++ ++#define DEBUG_SPINAND(debug_level, x) do { if (_u8SPINANDDbgLevel >= (debug_level)) (x); } while(0) ++ ++#define SPINAND_MEASURE_PERFORMANCE 0 ++#define USE_SPINAND_INFO_TABLE 0 ++ ++#define UNFD_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define UNFD_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++//#define UNFD_PART_MIU 1 ++#define UNFD_PART_IPL_CUST 1 ++#define UNFD_PART_BOOTLOGO 2 ++#define UNFD_PART_IPL 3 ++#define UNFD_PART_OS 4 ++#define UNFD_PART_CUS 5 ++#define UNFD_PART_UBOOT 6 ++#define UNFD_PART_SECINFO 7 ++#define UNFD_PART_OTP 8 ++#define UNFD_PART_RECOVERY 9 ++#define UNFD_PART_E2PBAK 10 ++#define UNFD_PART_NVRAMBAK 11 ++#define UNFD_PART_NPT 12 ++#define UNFD_PART_ENV 13 ++#define UNFD_PART_MISC 14 ++#define UNFD_PART_RTOS 0x10 ++#define UNFD_PART_RTOS_BACKUP 0x11 ++#define UNFD_PART_KERNEL 0x12 ++#define UNFD_PART_KERNEL_BACKUP 0x13 //not used now ++ ++#define UNFD_PART_CIS 0x20 ++#define UNFD_PART_UBI 0x21 ++ ++#define UNFD_PART_CUST0 0x30 ++#define UNFD_PART_CUST1 0x31 ++#define UNFD_PART_CUST2 0x32 ++#define UNFD_PART_CUST3 0x33 ++#define UNFD_PART_CUSTf 0x3F ++ ++ ++ ++struct mstar_spinand_info ++{ ++ struct mtd_info mtd; ++ struct nand_chip nand; ++ struct platform_device *pdev; ++ struct mtd_partition *parts; ++}; ++ ++ /// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++typedef struct ++{ ++ U16 u16_StartBlk; // the start block index ++ U16 u16_BlkCnt; // project team defined ++ U16 u16_PartType; // project team defined ++ U16 u16_BackupBlkCnt; // reserved good blocks count for backup, UNFD internal use. ++ // e.g. u16BackupBlkCnt = u16BlkCnt * 0.03 + 2 ++} SPI_NAND_PARTITION_RECORD_t; ++ ++typedef struct ++{ ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U16 u16_PartCnt; ++ U16 u16_UnitByteCnt; ++ SPI_NAND_PARTITION_RECORD_t records[62]; ++} SPI_NAND_PARTITION_INFO_t; ++ ++typedef struct _SPI_NAND_DRIVER ++{ ++ SPINAND_FLASH_INFO_t tSpinandInfo; ++ ++ SPI_NAND_PARTITION_INFO_t tPartInfo; ++ U8 u8_HasPNI; ++ ++ U8 *pu8_pagebuf; ++ U8 *pu8_sparebuf; ++ U8 *pu8_statusbuf; ++ U32 u32_column; ++ U8 u8_status; ++ U8 u8_statusRequest; ++ U8 *pu8_pagechkbuf; ++} SPI_NAND_DRIVER_t; ++ ++typedef struct ++{ ++ U8 au8_Tag[16]; ++ SPINAND_FLASH_INFO_t tSpiNandInfo; ++ U8 au8_Reserved[]; ++} SPINAND_FLASH_INFO_TAG_t; ++ ++ ++// BOOL MDrv_SPINAND_Init(SPINAND_FLASH_INFO_t *tSpinandInfo); ++// U32 MDrv_SPINAND_Read(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++// U32 MDrv_SPINAND_Write(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++// U32 MDrv_SPINAND_BLOCK_ERASE(U32 u32_BlkIdx); ++// U8 MDrv_SPINAND_ReadID(U16 u16Size, U8 *u8Data); ++// void _spiNandMain(unsigned int dwSramAddress, unsigned int dwSramSize); ++// U32 MDrv_SPINAND_SetMode(SPINAND_MODE eMode); ++// BOOL MDrv_SPINAND_ForceInit(SPINAND_FLASH_INFO_t *tSpinandInfo); ++// void MDrv_SPINAND_Device(struct device *dev); ++// U32 MDrv_SPINAND_WriteProtect(BOOL bEnable); ++// BOOL MDrv_SPINAND_IsActive(void); ++// U32 MDrv_SPINAND_Read_RandomIn(U32 u32_PageIdx, U32 u32_Column, U32 u32_Byte, U8 *u8Data); ++// U32 MDrv_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++// ++// // unsigned char MsOS_In_Interrupt (void); ++// inline BOOL MS_SPINAND_IN_INTERRUPT (void); ++// inline U32 MS_SPINAND_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, U32 u32Flag); ++// inline BOOL MS_SPINAND_DELETE_MUTEX(S32 s32MutexId); ++// inline BOOL MS_SPINAND_OBTAIN_MUTEX (S32 s32MutexId, U32 u32WaitMs); ++// inline BOOL MS_SPINAND_RELEASE_MUTEX (S32 s32MutexId); ++void *drvSPINAND_get_DrvContext_address(void); ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff --git a/drivers/sstar/spinand/drv/mdrv_spinand_hal.c b/drivers/sstar/spinand/drv/mdrv_spinand_hal.c +new file mode 100755 +index 000000000000..870454a3e4e8 +--- /dev/null ++++ b/drivers/sstar/spinand/drv/mdrv_spinand_hal.c +@@ -0,0 +1,542 @@ ++/* ++* mdrv_spinand_hal.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//========================================================================== ++// Common Definition ++//========================================================================== ++ ++#include ++#include "mdrv_spinand_command.h" ++#include "mdrv_spinand.h" ++#include "mhal_spinand.h" ++#include "../include/ms_platform.h" ++ ++//========================================================================== ++// Local Variables ++//========================================================================== ++U8 u8MagicData[] = {0x4D, 0x53, 0x54, 0x41, 0x52, 0x53, 0x45, 0x4D, 0x49, 0x55, 0x53, 0x46, 0x44, 0x43, 0x49, 0x53}; ++struct device *spi_nand_dev = NULL; ++static int _s32SPINAND_Mutex; ++static spinlock_t _gtSpiNANDLock; ++#if defined(SUPPORT_SPINAND_QUAD) && SUPPORT_SPINAND_QUAD ++SPINAND_MODE _SpinandRdMode = E_SPINAND_QUAD_MODE; ++#else ++SPINAND_MODE _SpinandRdMode = E_SPINAND_SINGLE_MODE; ++#endif ++ ++/********Read nand info by sni & pni, so no need the table.********/ ++#if USE_SPINAND_INFO_TABLE ++ SPINAND_FLASH_INFO_t gtSpiNandInfoTable[]= ++ { //u8_IDByteCnt au8_ID u16_SpareByteCnt u16_PageByteCnt u16_BlkPageCnt u16_BlkCnt u16_SectorByteCnt u8PlaneCnt u8WrapConfig bRIURead u8CLKConfig u8_UBOOTPBA u8_BL0PBA u8_BL1PBA u8_HashPBA eReadMode eWriteMode ++ {2, {MID_GD , 0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 4096, 512, 0}, ++ {2, {MID_GD , 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_GD , 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_GD , 0xD1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_GD , 0xD5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_GD , 0xD2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 2048, 512, 0}, ++ {2, {MID_MICRON , 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 2}, ++ {2, {MID_MICRON , 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 2048, 512, 2}, ++ {2, {MID_MICRON , 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 4096, 512, 2}, ++ {2, {MID_ATO , 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_WINBOND, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_MXIC , 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 1024, 512, 0}, ++ {2, {MID_MXIC , 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 2048, 512, 2}, ++ {2, {MID_TOSHIBA, 0xCB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 64, 2048, 64, 2048, 512, 2}, ++ {2, {0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 0, 0, 0, 0, 0, 0}, ++ }; ++#endif ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++#define MS_ASSERT(a) ++ ++//serial flash mutex wait time ++#define SPINAND_MUTEX_WAIT_TIME 3000 ++ ++//========================================================================== ++// Local Functions: SPI NAND Driver Function ++//========================================================================== ++static BOOL _MDrv_SPINAND_GET_INFO(void) ++{ ++ U32 u32Ret; ++ U8 u8Spare[16]; ++ U8 u8Data[512]; ++ U8 u8Idx, u8Status; ++ U8 *u8SrcAddr, *u8DstAddr; ++ U16 u16PageIndex; ++ u8SrcAddr = u8Data; ++ u8DstAddr = (U8*)(&_gtSpinandInfo); ++ ++ // if ecc error read back up block(block2 ,4, 6, 8) ++ for (u8Idx = 0; u8Idx < 10; u8Idx+=2) ++ { ++ u16PageIndex = 64 * u8Idx; ++ ++ //read data to cache first ++ u32Ret = HAL_SPINAND_RFC(u16PageIndex, &u8Status); ++ if (u32Ret != ERR_SPINAND_SUCCESS || (u8Status & ECC_STATUS_ERR)) ++ continue; ++ ++ // Read SPINand Data ++ u32Ret = HAL_SPINAND_RIU_READ(0, 512, u8SrcAddr); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ continue; ++ ++ // Read SPINand Spare Data ++ u32Ret = HAL_SPINAND_RIU_READ(2048, 16, u8Spare); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ continue; ++ ++ if (memcmp((const void *) u8SrcAddr, (const void *) u8MagicData, sizeof(u8MagicData)) != 0) ++ continue; ++ ++ u8SrcAddr += sizeof(u8MagicData); ++ ++ memcpy(u8DstAddr, u8SrcAddr, sizeof(SPINAND_FLASH_INFO_t)); ++ return TRUE; ++ } ++ ++ return FALSE; ++} ++ ++inline BOOL MS_SPINAND_IN_INTERRUPT (void) ++{ ++ return FALSE; ++} ++ ++inline U32 MS_SPINAND_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, U32 u32Flag) ++{ ++ spin_lock_init(&_gtSpiNANDLock); ++ return 1; ++} ++ ++inline BOOL MS_SPINAND_DELETE_MUTEX(S32 s32MutexId) ++{ ++ return TRUE; ++} ++ ++inline BOOL MS_SPINAND_OBTAIN_MUTEX (S32 s32MutexId, U32 u32WaitMs) ++{ ++ spin_lock_irq(&_gtSpiNANDLock); ++ return TRUE; ++} ++ ++inline BOOL MS_SPINAND_RELEASE_MUTEX (S32 s32MutexId) ++{ ++ spin_unlock_irq(&_gtSpiNANDLock); ++ return TRUE; ++} ++ ++BOOL MDrv_SPINAND_Init(SPINAND_FLASH_INFO_t *tSpinandInfo) ++{ ++ #define SPINAND_ID_SIZE 2 ++ U32 u32Ret; ++ ++ // 1. HAL init ++ _u8SPINANDDbgLevel = E_SPINAND_DBGLV_DEBUG; ++ ++ u32Ret = HAL_SPINAND_Init(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ spi_nand_err("Init SPI NAND fail!!!!"); ++ tSpinandInfo->au8_ID[0] = 0xFF; ++ tSpinandInfo->au8_ID[1] = 0xFF; ++ tSpinandInfo->u8_IDByteCnt = 2; ++ return FALSE; ++ } ++ ++ _s32SPINAND_Mutex= MS_SPINAND_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SPINAND", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SPINAND_Mutex >= 0); ++ ++ if (!_MDrv_SPINAND_GET_INFO()) ++ { ++ spi_nand_err("Can't find the CIS in BLOCK0!!!!"); ++ return FALSE; ++ ++ /***************************USE_SPINAND_INFO_TABLE***************************/ ++#if USE_SPINAND_INFO_TABLE ++ u32Ret = HAL_SPINAND_ReadID(SPINAND_ID_SIZE, u8ID); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ spi_nand_err("Can't not Detect SPINAND Device!!!!"); ++ tSpinandInfo->au8_ID[0] = 0xFF; ++ tSpinandInfo->au8_ID[1] = 0xFF; ++ tSpinandInfo->u8_IDByteCnt = 2; ++ return FALSE; ++ } ++ spi_nand_msg("MID =%x, DID =%x \r\n",u8ID[0], u8ID[1]); ++ ++ for (u32Index = 0; gtSpiNandInfoTable[u32Index].au8_ID[0] != 0; u32Index++) ++ { ++ if (gtSpiNandInfoTable[u32Index].au8_ID[0] == u8ID[0] && ++ gtSpiNandInfoTable[u32Index].au8_ID[1] == u8ID[1]) ++ { ++ spi_nand_msg("SPINAND Device DETECT"); ++ memcpy(tSpinandInfo, >SpiNandInfoTable[u32Index], sizeof(SPINAND_FLASH_INFO_t)); ++ memcpy(&_gtSpinandInfo, >SpiNandInfoTable[u32Index], sizeof(SPINAND_FLASH_INFO_t)); ++ break; ++ } ++ } ++ if ((!gtSpiNandInfoTable[u32Index].au8_ID[0]) && (!gtSpiNandInfoTable[u32Index].au8_ID[1])) ++ { ++ spi_nand_err("Can't not Detect SPINAND Device!!!!"); ++ tSpinandInfo->au8_ID[0] = u8ID[0]; ++ tSpinandInfo->au8_ID[1] = u8ID[1]; ++ tSpinandInfo->u8_IDByteCnt = 2; ++ if (!bReFind) ++ { ++ bReFind = TRUE; ++ HAL_SPINAND_CSCONFIG(); ++ goto MDrv_SPINAND_Init_Detect_ID; ++ } ++ return FALSE; ++ } ++#endif ++ /***************************USE_SPINAND_INFO_TABLE***************************/ ++ } ++ else ++ { ++ spi_nand_msg("Detected ID: MID =%x, DID =%x",_gtSpinandInfo.au8_ID[0] ,_gtSpinandInfo.au8_ID[1]); ++ memcpy(tSpinandInfo, &_gtSpinandInfo, sizeof(SPINAND_FLASH_INFO_t)); ++ } ++#if defined(SUPPORT_SPINAND_QUAD) && SUPPORT_SPINAND_QUAD ++ printk("\r\nQuad mode enabled\r\n"); ++ { ++ //HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++ HAL_SPINAND_PreHandle(_SpinandRdMode); ++ } ++#endif ++ ++ if (tSpinandInfo->au8_ID[0] == MID_FORESEE) ++ { ++#if defined(CONFIG_NAND_QUAL_READ) || defined(CONFIG_NAND_QUAL_WRITE) ++ U8 u8Status; ++ ++ HAL_SPINAND_ReadStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ if(!(u8Status & QUAD_ENABLE)) ++ { ++ u8Status |= QUAD_ENABLE; ++ HAL_SPINAND_WriteStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ } ++#endif ++ } ++ ++ return TRUE; ++} ++ ++BOOL MDrv_SPINAND_ForceInit(SPINAND_FLASH_INFO_t *tSpinandInfo) ++{ ++ memcpy(&_gtSpinandInfo, tSpinandInfo, sizeof(SPINAND_FLASH_INFO_t)); ++ return TRUE; ++} ++ ++static U8 MDrv_SPINAND_CountBits(U32 u32_x) ++{ ++ U8 u8_i = 0; ++ ++ while (u32_x) ++ { ++ u8_i++; ++ u32_x >>= 1; ++ } ++ ++ return u8_i-1; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read SPINAND Data ++// @param u32_PageIdx : page index of read data in specific block ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++U32 MDrv_SPINAND_Read(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf) ++{ ++ U8 u8Status; ++ U32 u32Ret = ERR_SPINAND_SUCCESS; ++ U16 u16ColumnAddr = 0; ++ ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if ((ID1 == 0xEF) && (ID2 == 0xAB) && (ID3 == 0x21)) ++ { ++ U16 u16DiePageCnt = MDrv_SPINAND_CountBits(BLOCKCNT * BLOCK_PAGE_SIZE); ++ HAL_SPINAND_DieSelect((U8)(u32_PageIdx >> (u16DiePageCnt - 1))); ++ } ++ ++ //read data to cache first ++ u32Ret = HAL_SPINAND_RFC(u32_PageIdx, &u8Status); ++ ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++ } ++ ++ if (PLANE && (((u32_PageIdx / BLOCK_PAGE_SIZE)&0x1) == 1)) //odd numbered blocks ++ { ++ u16ColumnAddr |= (1<<12); // plane select for MICRON & 2GB ++ } ++// HAL_SPINAND_PLANE_HANDLER(u32_PageIdx); ++ ++#if (defined(SUPPORT_SPINAND_QUAD) && SUPPORT_SPINAND_QUAD) || defined(CONFIG_NAND_QUAL_READ) ++ HAL_SPINAND_SetMode(E_SPINAND_QUAD_MODE); ++ // Read SPINand Data ++ u32Ret = HAL_SPINAND_Read (u16ColumnAddr, PAGE_SIZE, u8Data); ++ HAL_SPINAND_SetMode(E_SPINAND_SINGLE_MODE); ++#else ++ // Read SPINand Data ++ u32Ret = HAL_SPINAND_Read (u16ColumnAddr, PAGE_SIZE, u8Data); ++#endif ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++ } ++ ++ // Read SPINand Spare Data ++ u32Ret= HAL_SPINAND_Read(u16ColumnAddr|PAGE_SIZE, SPARE_SIZE, pu8_SpareBuf); ++ ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ { ++ if (u8Status & ECC_STATUS_ERR) ++ { ++ u32Ret = ERR_SPINAND_ECC_ERROR; ++ printk("ecc error P: %lx\r\n", u32_PageIdx); ++ } ++ else if (u8Status & ECC_STATUS_BITFLIP) ++ { ++ u32Ret = ERR_SPINAND_ECC_BITFLIP; ++ } ++ } ++ ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++ u64_TotalReadBytes+= _gtSpinandInfo.u16_PageByteCnt; ++#endif ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ ++ return u32Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read SPINAND Data From Random column address ++// @param u32_PageIdx : page index of read data in specific block ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++U32 MDrv_SPINAND_Read_RandomIn(U32 u32_PageIdx, U32 u32_Column, U32 u32_Byte, U8 *u8Data) ++{ ++ U8 u8Status; ++ U32 u32Ret = ERR_SPINAND_SUCCESS; ++ ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ //read data to cache first ++ u32Ret = HAL_SPINAND_RFC(u32_PageIdx, &u8Status); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++ } ++ ++ HAL_SPINAND_PLANE_HANDLER(u32_PageIdx); ++ ++ // Read SPINand Data ++ u32Ret = HAL_SPINAND_Read (u32_Column, u32_Byte, u8Data); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++ } ++ ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ { ++ if (u8Status & ECC_STATUS_ERR) ++ { ++ u32Ret = ERR_SPINAND_ECC_ERROR; ++ printk("ecc error P: %lx\r\n", u32_PageIdx); ++ } ++ else if (u8Status & ECC_STATUS_BITFLIP) ++ { ++ u32Ret = ERR_SPINAND_ECC_BITFLIP; ++ } ++ } ++ ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++ u64_TotalReadBytes += u32_Byte; ++#endif ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++} ++ ++U32 MDrv_SPINAND_SetMode(SPINAND_MODE eMode) ++{ ++ U32 u32Ret; ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ u32Ret = HAL_SPINAND_SetMode(eMode); ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++} ++ ++U32 MDrv_SPINAND_program(U32 u32_page, U16 u16_offset, U8 *pu8_buf, U32 u32_size) ++{ ++ U32 u32Ret; ++ ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if ((ID1 == 0xEF) && (ID2 == 0xAB) && (ID3 == 0x21)) ++ { ++ U16 u16DiePageCnt = MDrv_SPINAND_CountBits(BLOCKCNT * BLOCK_PAGE_SIZE); ++ HAL_SPINAND_DieSelect((U8)(u32_page >> (u16DiePageCnt - 1))); ++ } ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++ u64_TotalWriteBytes += _gtSpinandInfo.u16_PageByteCnt; ++#endif ++ u32Ret=HAL_SPINAND_program(u32_page, u16_offset, pu8_buf, u32_size); ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ ++ return u32Ret; ++ ++} ++ ++U32 MDrv_SPINAND_Write(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf) ++{ ++ U32 u32Ret; ++ ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if ((ID1 == 0xEF) && (ID2 == 0xAB) && (ID3 == 0x21)) ++ { ++ U16 u16DiePageCnt = MDrv_SPINAND_CountBits(BLOCKCNT * BLOCK_PAGE_SIZE); ++ HAL_SPINAND_DieSelect((U8)(u32_PageIdx >> (u16DiePageCnt - 1))); ++ } ++#if defined(SPINAND_MEASURE_PERFORMANCE) && SPINAND_MEASURE_PERFORMANCE ++ u64_TotalWriteBytes += _gtSpinandInfo.u16_PageByteCnt; ++#endif ++ u32Ret=HAL_SPINAND_Write(u32_PageIdx, u8Data, pu8_SpareBuf); ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ ++ return u32Ret; ++} ++ ++U8 MDrv_SPINAND_ReadID(U16 u16Size, U8 *u8Data) ++{ ++ U8 u8Ret; ++ ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ u8Ret=HAL_SPINAND_ReadID(u16Size, u8Data); ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u8Ret; ++} ++ ++U32 MDrv_SPINAND_BLOCK_ERASE(U32 u32_PageIdx) ++{ ++ U32 u32Ret; ++ MS_ASSERT( MS_SPINAND_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SPINAND_OBTAIN_MUTEX(_s32SPINAND_Mutex, SPINAND_MUTEX_WAIT_TIME)) ++ { ++ spi_nand_err("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if ((ID1 == 0xEF) && (ID2 == 0xAB) && (ID3 == 0x21)) ++ { ++ U16 u16DiePageCnt = MDrv_SPINAND_CountBits(BLOCKCNT * BLOCK_PAGE_SIZE); ++ HAL_SPINAND_DieSelect((U8)(u32_PageIdx >> (u16DiePageCnt - 1))); ++ } ++ ++ u32Ret=HAL_SPINAND_BLOCKERASE(u32_PageIdx); ++ ++ MS_SPINAND_RELEASE_MUTEX(_s32SPINAND_Mutex); ++ return u32Ret; ++} ++ ++void MDrv_SPINAND_Device(struct device *dev) ++{ ++ spi_nand_dev = dev; ++} ++ ++U32 MDrv_SPINAND_WriteProtect(BOOL bEnable) ++{ ++ return HAL_SPINAND_WriteProtect(bEnable); ++} ++ ++BOOL MDrv_SPINAND_IsActive(void) ++{ ++ return HAL_SPINAND_IsActive(); ++} ++ ++U32 MDrv_SPINAND_ReadStatusRegister(MS_U8 *u8Status, MS_U8 u8Addr) ++{ ++ return HAL_SPINAND_ReadStatusRegister(u8Status, u8Addr); ++} +diff --git a/drivers/sstar/spinand/drv/mdrv_spinand_hal.h b/drivers/sstar/spinand/drv/mdrv_spinand_hal.h +new file mode 100755 +index 000000000000..5df0b227dd3b +--- /dev/null ++++ b/drivers/sstar/spinand/drv/mdrv_spinand_hal.h +@@ -0,0 +1,37 @@ ++/* ++* mdrv_spinand_hal.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++BOOL MDrv_SPINAND_IsActive(void); ++BOOL MDrv_SPINAND_Init(SPINAND_FLASH_INFO_t *tSpinandInfo); ++BOOL MDrv_SPINAND_ForceInit(SPINAND_FLASH_INFO_t *tSpinandInfo); ++U8 MDrv_SPINAND_ReadID(U16 u16Size, U8 *u8Data); ++U32 MDrv_SPINAND_Read(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 MDrv_SPINAND_Write(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 MDrv_SPINAND_BLOCK_ERASE(U32 u32_BlkIdx); ++U32 MDrv_SPINAND_SetMode(SPINAND_MODE eMode); ++U32 MDrv_SPINAND_WriteProtect(BOOL bEnable); ++U32 MDrv_SPINAND_Read_RandomIn(U32 u32_PageIdx, U32 u32_Column, U32 u32_Byte, U8 *u8Data); ++U32 MDrv_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++void MDrv_SPINAND_Device(struct device *dev); ++void _spiNandMain(unsigned int dwSramAddress, unsigned int dwSramSize); ++U32 MDrv_SPINAND_program(U32 u32_page, U16 u16_offset, U8 *pu8_buf, U32 u32_size); ++ ++inline U32 MS_SPINAND_CREATE_MUTEX (MsOSAttribute eAttribute, char *pMutexName, U32 u32Flag); ++inline BOOL MS_SPINAND_IN_INTERRUPT (void); ++inline BOOL MS_SPINAND_DELETE_MUTEX(S32 s32MutexId); ++inline BOOL MS_SPINAND_OBTAIN_MUTEX (S32 s32MutexId, U32 u32WaitMs); ++inline BOOL MS_SPINAND_RELEASE_MUTEX (S32 s32MutexId); +diff --git a/drivers/sstar/spinand/hal/infinity2/mhal_spinand.c b/drivers/sstar/spinand/hal/infinity2/mhal_spinand.c +new file mode 100755 +index 000000000000..f0bcf84327d7 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2/mhal_spinand.c +@@ -0,0 +1,1418 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++ ++#include "mdrv_spinand_command.h" ++#include "mdrv_spinand_common.h" ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++#include ++#include ++ ++#define INFINITY_MIU0_BASE 0x20000000 ++#define spi_nand_err(fmt, ...) printk(KERN_ERR "%s:error, " fmt "\n", __func__, ##__VA_ARGS__) ++MS_U32 BASE_SPI_OFFSET = 0; ++ ++extern struct device *spi_nand_dev; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U8 u8Clk; ++ U16 eClkCkg; ++} hal_clk_ckg_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_NAND_SINGLE_READ ++SPINAND_MODE gNandReadMode= E_SPINAND_SINGLE_MODE; ++#endif ++ ++#ifdef CONFIG_NAND_DUAL_READ ++SPINAND_MODE gNandReadMode=E_SPINAND_DUAL_MODE; ++#endif ++ ++// redefined mask by Edie ++// #if defined (CONFIG_NAND_QUAL_READ)||(CONFIG_NAND_QUAL_WRITE) ++// SPINAND_MODE gNandReadMode=E_SPINAND_QUAD_MODE; ++// #endif ++ ++ ++static hal_fsp_t _hal_fsp = ++{ ++ .u32FspBaseAddr = I2_RIU_PM_BASE + BK_FSP, ++ .u32QspiBaseAddr = I2_RIU_PM_BASE + BK_QSPI, ++ .u32PMBaseAddr = I2_RIU_PM_BASE + BK_PMSLP, ++ .u32CLK0BaseAddr = I2_RIU_BASE + BK_CLK0, ++ .u32CHIPBaseAddr = I2_RIU_BASE + BK_CHIP, ++ .u32RiuBaseAddr= I2_RIU_PM_BASE, ++ .u32BDMABaseAddr = I2_RIU_BASE + BK_BDMA, ++}; ++ ++// ++// Spi Clk Table (List) ++// ++static hal_clk_ckg_t _hal_ckg_spi_pm[] = { ++ {12 , PM_SPI_CLK_XTALI } ++ ,{27 , PM_SPI_CLK_27MHZ } ++ ,{36 , PM_SPI_CLK_36MHZ } ++ ,{43 , PM_SPI_CLK_43MHZ } ++ ,{54 , PM_SPI_CLK_54MHZ } ++ ,{72 , PM_SPI_CLK_72MHZ } ++ ,{86 , PM_SPI_CLK_86MHZ } ++ ,{108, PM_SPI_CLK_108MHZ} ++}; ++ ++static hal_clk_ckg_t _hal_ckg_spi_nonpm[] = { ++ {12 , CLK0_CKG_SPI_XTALI } ++ ,{27 , CLK0_CKG_SPI_27MHZ } ++ ,{36 , CLK0_CKG_SPI_36MHZ } ++ ,{43 , CLK0_CKG_SPI_43MHZ } ++ ,{54 , CLK0_CKG_SPI_54MHZ } ++ ,{72 , CLK0_CKG_SPI_72MHZ } ++ ,{86 , CLK0_CKG_SPI_86MHZ } ++ ,{108, CLK0_CKG_SPI_108MHZ} ++}; ++ ++U8 _u8SPINANDDbgLevel; ++ ++ ++static struct bdma_alloc_dmem ++{ ++ dma_addr_t bdma_phy_addr ; ++ const char* DMEM_BDMA_INPUT; ++ u8 *bdma_vir_addr; ++}ALLOC_DMEM = {0, "BDMA", 0}; ++ ++#if 1 ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++#endif ++// ++// static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr ) ++// { ++// MSYS_DMEM_INFO dmem; ++// memcpy(dmem.name,name,strlen(name)+1); ++// dmem.length=size; ++// dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++// dmem.phys=(unsigned long long)((uintptr_t)addr); ++// msys_release_dmem(&dmem); ++// } ++ ++// static void _ms_bdma_mem_free(U32 u32DataSize) ++// { ++// if(ALLOC_DMEM.bdma_vir_addr != 0){ ++// free_dmem(ALLOC_DMEM.DMEM_BDMA_INPUT, u32DataSize, ALLOC_DMEM.bdma_vir_addr, ALLOC_DMEM.bdma_phy_addr); ++// ALLOC_DMEM.bdma_vir_addr = 0; ++// } ++// } ++ ++BOOL _gbRIURead = FALSE; ++ ++static BOOL FSP_WRITE_BYTE(U32 u32RegAddr, U8 u8Val) ++{ ++ if (!u32RegAddr) ++ { ++ printk(KERN_ERR"%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ((volatile U8*)(_hal_fsp.u32FspBaseAddr))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ return TRUE; ++} ++ ++static BOOL FSP_WRITE(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ printk(KERN_ERR"%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ((volatile U16*)(_hal_fsp.u32FspBaseAddr))[u32RegAddr] = u16Val; ++ return TRUE; ++} ++ ++static U8 FSP_READ_BYTE(U32 u32RegAddr) ++{ ++ return ((volatile U8*)(_hal_fsp.u32FspBaseAddr))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++} ++ ++static U16 FSP_READ(U32 u32RegAddr) ++{ ++ return ((volatile U16*)(_hal_fsp.u32FspBaseAddr))[u32RegAddr]; ++} ++ ++ ++static void _HAL_SPINAND_BDMA_INIT(U32 u32DataSize) ++{ ++ if (!(ALLOC_DMEM.bdma_vir_addr = alloc_dmem(ALLOC_DMEM.DMEM_BDMA_INPUT, ++ u32DataSize, ++ &ALLOC_DMEM.bdma_phy_addr))){ ++ printk("[input]unable to allocate aesdma memory\n"); ++ } ++ memset(ALLOC_DMEM.bdma_vir_addr, 0, u32DataSize); ++} ++ ++ ++static BOOL _HAL_FSP_ChkWaitDone(void) ++{ ++//consider as it spend very long time to check if FSP done, so it may implment timeout method to improve ++ U16 u16Try = 0; ++ U8 u8DoneFlag = 0; ++ ++ while (u16Try < CHK_NUM_WAITDONE) ++ { ++ u8DoneFlag = FSP_READ(REG_FSP_DONE); ++ if ((u8DoneFlag & DONE_FSP) == DONE_FSP) ++ { ++ return TRUE; ++ } ++ ++ if (++u16Try%1000 == 0) ++ cond_resched(); ++ ++ udelay(1); ++ } ++ return FALSE; ++} ++ ++static void _HAL_FSP_GetRData(U8 *pu8Data, U8 u8DataSize) ++{ ++ U8 u8Index = 0; ++ //printk(KERN_ERR"_HAL_FSP_GetRData %lx\r\n",(U32)u8DataSize); ++ for (u8Index = 0; u8Index < u8DataSize; u8Index++) ++ { ++ pu8Data[u8Index] = FSP_READ_BYTE(REG_FSP_READ_BUFF + u8Index); ++ } ++} ++ ++static U32 _HAL_FSP_CHECK_SPINAND_DONE(U8 *pu8Status) ++{ ++ U8 u8Data = SPI_NAND_STAT_OIP; ++ U16 u16Try = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_GF); ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + 1, SPI_NAND_REG_STAT); ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x2); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x1); ++ ++ while (1) //while(u16Try < CHK_NUM_WAITDONE) ++ { ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"CD Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ _HAL_FSP_GetRData(&u8Data, 1); ++ if ((u8Data & SPI_NAND_STAT_OIP) == 0 ) ++ break; ++ ++ if (++u16Try%1000 == 0) ++ cond_resched(); ++ ++ udelay(1); ++ } ++ ++ if (u16Try == CHK_NUM_WAITDONE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"CD Wait OIP Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ if (pu8Status) ++ *pu8Status = u8Data; ++ ++ return ERR_SPINAND_SUCCESS; ++} ++ ++static U32 _HAL_SPINAND_WRITE_ENABLE(void) ++{ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_WREN); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x1); ++ // read buffer size ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"WE Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ return ERR_SPINAND_SUCCESS; ++ ++} ++ ++void HAL_QSPI_WRAP(U8 u8Enable) ++{ ++ if(u8Enable) ++ { ++ QSPI_WRITE(REG_SPI_FUNC_SET, (REG_SPI_ADDR2_EN|REG_SPI_DUMMY_EN|REG_SPI_WRAP_EN)); ++ } ++ else ++ { ++ QSPI_WRITE(REG_SPI_FUNC_SET, (REG_SPI_ADDR2_EN|REG_SPI_DUMMY_EN)); ++ } ++} ++ ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData) ++{ ++ U32 u32Index = 0; ++ U8 u8Addr = 0; ++ U32 u32RealLength = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_RFC); ++ u8WbufIndex++; ++ ++ //Set Write & Read Length ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 4); //add 4 because it is included of command and Address setting length ++ if (u32DataSize > MAX_READ_BUF_CNT) ++ FSP_WRITE(REG_FSP_READ_SIZE, MAX_READ_BUF_CNT); ++ else ++ FSP_WRITE(REG_FSP_READ_SIZE, u32DataSize); ++ ++ for (u32Index = 0; u32Index < u32DataSize; u32Index +=MAX_READ_BUF_CNT) ++ { ++ ++ for (s8Index = (SPI_NAND_PAGE_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u16Addr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u8Addr); ++ u8WbufIndex++; ++ } ++ // set dummy byte ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), 0x00); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RIUR Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ //Get Read Data ++ u32RealLength = u32DataSize - u32Index; ++ if (u32RealLength >= MAX_READ_BUF_CNT) ++ u32RealLength = MAX_READ_BUF_CNT; ++ ++ _HAL_FSP_GetRData((u8pData + u32Index), u32RealLength); ++ ++ //Clear FSP done flag ++ FSP_WRITE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ // update Read Start Address ++ u16Addr += u32RealLength; ++ u8WbufIndex -= SPI_NAND_PAGE_ADDR_LEN; ++ ++ } ++ return ERR_SPINAND_SUCCESS; ++} ++ ++static U32 _HAL_SPINAND_BDMA_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData) ++{ ++ U32 u32Addr1; ++ U16 u16data; ++ U32 u32Timer = 0; ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ ++ //Set source and destination path ++ BDMA_WRITE(0x00, 0x0000); ++ ++ u32Addr1 = (U32)u8pData; ++ ++// u32Addr1 = dma_map_single(spi_nand_dev, (void*)u8pData, u32DataSize, DMA_FROM_DEVICE); ++ ++ BDMA_WRITE(0x02, 0X4035); //5:source device (spi) ++ //3:source device data width (8 bytes) ++ //0:destination device (MIU) 1:destination device (IMI) ++ //4:destination device data width (16 bytes) ++ #if defined(CONFIG_ARCH_INFINITY2) ++ BDMA_WRITE(0x03, 0x0000); ++ #endif ++ ++ // Set start address ++ BDMA_WRITE(0x04, (u16Addr & 0x0000FFFF)); ++ BDMA_WRITE(0x05, (u16Addr>>16)); ++ ++ // Set end address ++ BDMA_WRITE(0x06, (Chip_Phys_to_MIU(ALLOC_DMEM.bdma_phy_addr) & 0x0000FFFF)); ++ BDMA_WRITE(0x07, (Chip_Phys_to_MIU(ALLOC_DMEM.bdma_phy_addr) >> 16)); ++ ++ // Set Size ++ BDMA_WRITE(0x08, (u32DataSize & 0x0000FFFF)); ++ BDMA_WRITE(0x09, (u32DataSize >> 16)); ++ ++ // Trigger ++ BDMA_WRITE(0x00, 1); ++ do ++ { ++ //check done ++ u16data = BDMA_READ(0x01); ++ if (u16data & 8) ++ { ++ //clear done ++ BDMA_WRITE(0x01, 8); ++ u32Ret = ERR_SPINAND_SUCCESS; ++ break; ++ } ++ if (++u32Timer%1000 == 0) ++ cond_resched(); ++ ++ udelay(1); ++ } while (u32Timer < CHK_NUM_WAITDONE); ++// dma_unmap_single(spi_nand_dev, u32Addr1, u32DataSize, DMA_FROM_DEVICE); ++// Chip_Inv_Cache_Range((u32)u8pData, u32DataSize); ++ memcpy(u8pData, ALLOC_DMEM.bdma_vir_addr, u32DataSize); ++ ++// _ms_bdma_mem_free(u32DataSize); ++ ++ ++ return u32Ret; ++} ++ ++ ++static void HAL_SPINAND_PreHandle(SPINAND_MODE eMode) ++{ ++ U8 u8Status; ++ //if (_gtSpinandInfo.au8_ID[0] == 0xC8) ++ { ++ switch (eMode) ++ { ++ case E_SPINAND_SINGLE_MODE: ++ case E_SPINAND_FAST_MODE: ++ case E_SPINAND_DUAL_MODE: ++ case E_SPINAND_DUAL_MODE_IO: //GD support If QE is enabled, the quad IO operations can be executed. ++ HAL_SPINAND_ReadStatusRegister(&u8Status, SPI_NAND_REG_FEAT); //output:u8Status is OTP data. ++ u8Status &= ~(QUAD_ENABLE); ++ HAL_SPINAND_WriteStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ break; ++ case E_SPINAND_QUAD_MODE: ++ case E_SPINAND_QUAD_MODE_IO: //GD support ++ HAL_SPINAND_ReadStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ u8Status |= QUAD_ENABLE; ++ HAL_SPINAND_WriteStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ break; ++ } ++ } ++} ++ ++U32 HAL_SPINAND_Init(void) ++{ ++ //set pad mux for spinand ++// printk("MDrv_SPINAND_Init: Set pad mux\n"); ++#if defined(CONFIG_ARCH_INFINITY3) ++ CHIP_WRITE(0x50, 0x000);//disable all pad in ++ QSPI_WRITE(0x7A, 0x01);//CS ++ PM_WRITE(0x35, 0x0C); ++#endif ++ ++ if(BDMA_FLAG) ++ _HAL_SPINAND_BDMA_INIT(2048+64); ++ ++// printk("MDrv_SPINAND_Init: Set pad mux end"); ++#if 1 ++ // reset spinand ++ // FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_RESET); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 1); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"INI Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ // For first RESET condition after power up, tRST will be 1ms maximum ++ msleep(2); ++#endif ++ return ERR_SPINAND_SUCCESS; ++} ++ ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr) ++{ ++ DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk(KERN_INFO"%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr)); ++ _hal_fsp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_fsp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_fsp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_fsp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0;//BK_CLK0; ++ _hal_fsp.u32BDMABaseAddr = u32NonPMRegBaseAddr + BK_BDMA; ++ _hal_fsp.u32RiuBaseAddr = u32PMRegBaseAddr; ++ ++ ++} ++ ++/* for 1Gb this function is dummy*/ ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr) ++{ ++ if ((((u32Addr / BLOCK_PAGE_SIZE)&0x1) == 1)) //odd numbered blocks ++ { ++ u32Addr = QSPI_READ(REG_SPI_WRAP_VAL); ++ u32Addr |= (1 << REG_SPI_WRAP_BIT_OFFSET); ++ QSPI_WRITE(REG_SPI_WRAP_VAL, u32Addr); ++ HAL_QSPI_WRAP(1); ++ } ++ else ++ { ++ u32Addr = QSPI_READ(REG_SPI_WRAP_VAL); ++ u32Addr &= ~(1 << REG_SPI_WRAP_BIT_OFFSET); ++ QSPI_WRITE(REG_SPI_WRAP_VAL, u32Addr); ++ HAL_QSPI_WRAP(0); ++ } ++ return TRUE; ++} ++ ++void HAL_SPINAND_DieSelect (U8 u8Die) ++{ ++ if(u8Die != 0)//only 2 die ++ u8Die = 1; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_DIESELECT); ++ //Set Start Address ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + 1, u8Die); ++ //Set Write & Read Length ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("RID Wait FSP Done Time Out !!!!\r\n")); ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++// return HAL_SPINAND_CHECK_STATUS(); ++} ++ ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data) ++{ ++ U8 u8Addr = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index; ++ ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("HAL_SPINAND_RFC : u32Addr = %lx \r\n",u32Addr)); ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP|ENABLE_SEC_CMD)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++// FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_WREN); ++// u8WbufIndex++; ++ ++ //SECOND COMMAND READ COMMAND + 3BYTE ADDRESS ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_PGRD); ++ u8WbufIndex++; ++ //set Read Start Address ++ for (s8Index = (SPI_NAND_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u32Addr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ //THIRD COMMAND GET FATURE CHECK CAHCHE READY ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_REG_STAT); //read ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x024); //17-bit block/page address ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x010); //1 byte (receive from get feature) ++ ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RFC Wait FSP Done Time Out %lx !!!!\r\n",u32Addr)); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ _HAL_FSP_GetRData((pu8Data), 1); ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ return _HAL_FSP_CHECK_SPINAND_DONE(pu8Data); ++} ++ ++U32 HAL_SPINAND_program_load_data(U16 u16_col_address, U8 *pu8_buf, U32 u32_size) ++{ ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ U8 u8WbufIndex = 0; ++ U32 u32WrteBuf = REG_FSP_WRITE_BUFF; ++ ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("u16ColumnAddr %x u16DataSize %x Data %x \r\n", u16ColumnAddr, u16DataSize, *pu8Data)); ++ // Write Enable ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ // while(HAL_QSPI_FOR_DEBUG()==0); ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP write Command ++ // FIRSET COMMAND PRELOAD ++ ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_PP); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), (u16_col_address >> 8) & 0xff); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), u16_col_address & 0xff); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u8WbufIndex); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ //Trigger FSP ++ ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u8WbufIndex = 0; ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_ENABLE_BURST); ++ ++ while (0 < u32_size) ++ { ++ while (SINGLE_WRITE_SIZE > u8WbufIndex) ++ { ++ if (u8WbufIndex == FSP_WRITE_BUF_JUMP_OFFSET) ++ { ++ u32WrteBuf = REG_FSP_WRITE_BUFF2; ++ } ++ ++ FSP_WRITE_BYTE((u32WrteBuf + (u8WbufIndex % FSP_WRITE_BUF_JUMP_OFFSET)), *pu8_buf); ++ //printk("0x%02x, ", *pu8_buf); ++ pu8_buf++; ++ u8WbufIndex++; ++ u32_size--; ++ ++ if (0 == u32_size) ++ { ++ break; ++ } ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u8WbufIndex); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ //Trigger FSP ++ ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ u8WbufIndex = 0; ++ u32WrteBuf = REG_FSP_WRITE_BUFF; ++ //QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return _HAL_FSP_CHECK_SPINAND_DONE(NULL); ++} ++ ++U32 HAL_SPINAND_PROGRAM_LOAD_DATA(U16 u16ColumnAddr, U16 u16DataSize, U8 *pu8Data, U8 *pu8_SpareBuf) ++{ ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ U8 u8Addr = 0, u8DataIndex =0; ++ U16 u16RealLength = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index; ++ U32 u32WrteBuf = REG_FSP_WRITE_BUFF; ++ U16 u16DataIndex; ++ U8 *pu8Wdata; ++ ++ pu8Wdata = pu8Data; ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("u16ColumnAddr %x u16DataSize %x Data %x \r\n", u16ColumnAddr, u16DataSize, *pu8Data)); ++ // Write Enable ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ // while(HAL_QSPI_FOR_DEBUG()==0); ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP write Command ++ // FIRSET COMMAND PRELOAD ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_PP); ++#else ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_QPP); ++#endif ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ u8WbufIndex++; ++ ++ //PAGE Address ++ for (s8Index = (SPI_NAND_PAGE_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u16ColumnAddr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++#ifdef CONFIG_NAND_QUAL_WRITE ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x003); ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ u8WbufIndex=0; ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, ENABLE_FSP_QUAD); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++#endif ++ ++ for (u16DataIndex = 0; u16DataIndex < u16DataSize; u16DataIndex+= u16RealLength) ++ { ++ u16RealLength = u16DataSize - u16DataIndex; ++ if (u16RealLength >= SINGLE_WRITE_SIZE) ++ u16RealLength = SINGLE_WRITE_SIZE - u8WbufIndex; ++ ++ //Write Data ++ for (u8DataIndex = 0; u8DataIndex < u16RealLength; u8DataIndex++) ++ { ++ if ((u16DataIndex + u8DataIndex)== PAGE_SIZE) ++ { ++ pu8Wdata = pu8_SpareBuf; ++ } ++ ++ //printk("u8DataIndex %x u16RealLength %x \r\n",u8DataIndex, u16RealLength); ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), *pu8Wdata); ++ u8WbufIndex++; ++ pu8Wdata++; ++ if (u8WbufIndex >= FSP_WRITE_BUF_JUMP_OFFSET) ++ { ++ u32WrteBuf = REG_FSP_WRITE_BUFF2; ++ u8WbufIndex = 0; ++ } ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, SINGLE_WRITE_SIZE); ++ //Trigger FSP ++ ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u8WbufIndex = 0; ++ u32WrteBuf = REG_FSP_WRITE_BUFF; ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return _HAL_FSP_CHECK_SPINAND_DONE(NULL); ++ ++} ++ ++U32 HAL_SPINAND_READ_STATUS(U8 *pu8Status, U8 u8Addr) ++{ ++ U8 u8WbufIndex = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ //SECOND COMMAND SET READ PARAMETER ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u8Addr); ++ // write buffer size ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ // read buffer size ++ FSP_WRITE(REG_FSP_READ_SIZE, 1); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RS Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_SUCCESS; ++ } ++ //Get Read Data ++ _HAL_FSP_GetRData(pu8Status, 1); ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return ERR_SPINAND_SUCCESS; ++} ++ ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx) ++{ ++ U8 u8WbufIndex = 0; ++ S8 s8Index; ++ U8 u8Addr; ++ U32 u32Ret; ++ U8 u8Status; ++ ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ u32Ret = HAL_SPINAND_WriteProtect(FALSE); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP|ENABLE_SEC_CMD|ENABLE_THR_CMD)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_WREN); ++ u8WbufIndex++; ++ ++ //SECOND COMMAND SET Erase Command ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_BE); ++ u8WbufIndex++; ++ ++ //seet erase Start Address ++ for (s8Index = (SPI_NAND_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u32_PageIdx >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ //THIRD COMMAND GET FATURE CHECK CAHCHE READY ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_REG_STAT); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x241); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x100); ++ ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"BE Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u32Ret = _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ if (u8Status & E_FAIL) ++ u32Ret = ERR_SPINAND_E_FAIL; ++ u32Ret = HAL_SPINAND_WriteProtect(TRUE); ++ ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size) ++{ ++ U32 u32Ret; ++ U8 u8WbufIndex = 0; ++ U8 u8Status; ++ ++ u32Ret = HAL_SPINAND_WriteProtect(FALSE); ++#if 0 ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ HAL_SPINAND_SetMode(WRITE_MODE); ++#else ++ //HAL_SPINAND_SetMode(gNandReadMode); ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++#endif ++#endif ++ if ((BLOCKCNT == DENSITY_2G) && (((u32_row_address / BLOCK_PAGE_SIZE)&0x1) == 1)) ++ u16_col_address = (1<<12); // plane select for MICRON ++ ++ u32Ret = HAL_SPINAND_program_load_data(u16_col_address, pu8_buf, u32_size); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++#ifdef CONFIG_NAND_QUAL_WRITE ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, 0); ++ HAL_SPINAND_PreHandle(E_SPINAND_SINGLE_MODE); ++#endif ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP | RESET_FSP | INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ // FIRST COMMAND PAGE PROGRAM EXECUTE ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_PE); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u32_row_address >> 16); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), (u32_row_address >> 8 & 0Xff)); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u32_row_address & 0xff); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u8WbufIndex); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x000); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u32Ret = _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ if (u8Status & P_FAIL) ++ { ++ u32Ret = ERR_SPINAND_W_FAIL; ++ spi_nand_err("P_FAIL!!!\n"); ++ return u32Ret; ++ } ++ u32Ret = HAL_SPINAND_WriteProtect(TRUE); ++ ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_Write(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf) ++{ ++ U32 u32Ret; ++ U8 u8Addr = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index; ++ U16 u16DataSize; ++ U8 u8Status; ++ U16 u16ColumnAddr = 0; ++ ++ //calculate write data size ++ u16DataSize = SPARE_SIZE + PAGE_SIZE; ++ ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("addr %lx u8Data %x u32PageIndex %lx\r\n", (U32)u8Data, *u8Data, u32_PageIdx)); ++ u32Ret = HAL_SPINAND_WriteProtect(FALSE); ++#if 0 ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ HAL_SPINAND_SetMode(WRITE_MODE); ++#else ++ //HAL_SPINAND_SetMode(gNandReadMode); ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++#endif ++#endif ++ if ((BLOCKCNT == DENSITY_2G) && (((u32_PageIdx / BLOCK_PAGE_SIZE)&0x1) == 1)) ++ u16ColumnAddr = (1<<12); // plane select for MICRON ++ ++ u32Ret = HAL_SPINAND_PROGRAM_LOAD_DATA(u16ColumnAddr, u16DataSize, u8Data, pu8_SpareBuf); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++#ifdef CONFIG_NAND_QUAL_WRITE ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, 0); ++ HAL_SPINAND_PreHandle(E_SPINAND_SINGLE_MODE); ++#endif ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP|ENABLE_SEC_CMD)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ // FIRST COMMAND PAGE PROGRAM EXECUTE ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_PE); ++ u8WbufIndex++; ++ ++ //seet Write Start Address ++ for (s8Index = (SPI_NAND_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u32_PageIdx >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ //SECOND COMMAND GET FATURE CHECK CAHCHE READY ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_REG_STAT); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x024); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x010); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u32Ret = _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ if (u8Status & P_FAIL) ++ { ++ u32Ret = ERR_SPINAND_W_FAIL; ++ spi_nand_err("P_FAIL!!!\n"); ++ return u32Ret; ++ } ++ u32Ret = HAL_SPINAND_WriteProtect(TRUE); ++ ++ return u32Ret; ++ ++} ++ ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data) ++{ ++ U16 u16Addr = u32Addr & 0xFFFF; ++ U32 ret = ERR_SPINAND_SUCCESS; ++ ++ if (RIU_FLAG) ++ { ++ ret = HAL_SPINAND_RIU_READ(u16Addr, u32DataSize, pu8Data); ++ } ++ else if(BDMA_FLAG) ++ { ++ ret = _HAL_SPINAND_BDMA_READ(u16Addr, u32DataSize, pu8Data); ++ ++ if (ret != ERR_SPINAND_SUCCESS) ++ { ++ printk(KERN_ERR"R Wait BDMA Done Time Out CLK!!!!\r\n"); ++ ++ } ++ } ++ else if(XIP_FLAG) ++ { ++ if(!BASE_SPI_OFFSET) ++ { ++ if (!PAGE_SIZE) ++ BASE_SPI_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 2048+64); ++ ++ BASE_SPI_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, PAGE_SIZE+SPARE_SIZE); ++ } ++ if(BASE_SPI_OFFSET) ++ { ++ memcpy((void *)pu8Data, (const void *)(BASE_SPI_OFFSET)+u16Addr , u32DataSize); ++ } ++ } ++ return ret; ++} ++ ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data) ++{ ++ U16 u16Index =0; ++ U32 u32RealLength = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_RDID); ++ //Set Start Address ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + 1, 0x00); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ ++ //Set Write & Read Length ++ for (u16Index = 0; u16Index < u32DataSize; u16Index += u32RealLength) ++ { ++ if (u32DataSize > (MAX_READ_BUF_CNT)) ++ { ++ FSP_WRITE(REG_FSP_READ_SIZE, MAX_READ_BUF_CNT); ++ u32RealLength = MAX_READ_BUF_CNT; ++ } ++ else ++ { ++ FSP_WRITE(REG_FSP_READ_SIZE, u32DataSize); ++ u32RealLength = u32DataSize; ++ } ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RID Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ //Get Read Data ++ _HAL_FSP_GetRData((pu8Data + u16Index), u32RealLength); ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ } ++ return ERR_SPINAND_SUCCESS; ++ ++} ++ ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable) ++{ ++ U8 u8WbufIndex = 0; ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_SF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, SPI_NAND_REG_PROT); ++ u8WbufIndex++; ++ if (bEnable) ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex,0x38); //all locked(default) ++ else ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex,0x00); //all unlocked ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 3); ++ // read buffer size ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"WP Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return ERR_SPINAND_SUCCESS; ++} ++ ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode) ++{ ++ switch (eMode) ++ { ++// printk("HAL_SPINAND_SetMode 1\n"); ++ case E_SPINAND_SINGLE_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_SINGLE_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_NORMAL_MODE); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_IS_GPIO, PM_SPI_WP_GPIO_MASK); ++ break; ++ case E_SPINAND_FAST_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_FAST_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_FAST_READ); ++ break; ++ case E_SPINAND_DUAL_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_DUAL_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_3B); ++ break; ++ case E_SPINAND_DUAL_MODE_IO: ++ HAL_SPINAND_PreHandle(E_SPINAND_DUAL_MODE_IO); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_DUAL); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_BB); ++ break; ++ case E_SPINAND_QUAD_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_6B); ++ break; ++ case E_SPINAND_QUAD_MODE_IO: ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_QUAD); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_6B); ++ break; ++ } ++ return ERR_SPINAND_SUCCESS; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SPINAND_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi) ++{ ++ BOOL Ret = FALSE; ++ U8 u8nonPmIdx = 0, u8PmIdx = 0; ++ U8 u8Idx; ++ U8 u8Size; ++ u8Size = sizeof(_hal_ckg_spi_nonpm)/ sizeof(hal_clk_ckg_t); ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_INFO, printk("%s()\n", __FUNCTION__)); ++ for (u8Idx = 0; u8Idx < u8Size; u8Idx++) ++ { ++ if (u8CkgSpi < _hal_ckg_spi_nonpm[u8Idx].u8Clk) ++ { ++ if (u8Idx) ++ u8nonPmIdx = u8Idx - 1; ++ else ++ u8nonPmIdx = u8Idx; ++ break; ++ } ++ else ++ u8nonPmIdx = u8Idx; ++ } ++ ++ u8Size = sizeof(_hal_ckg_spi_pm)/ sizeof(hal_clk_ckg_t); ++ for (u8Idx = 0; u8Idx < u8Size; u8Idx++) ++ { ++ if (u8CkgSpi < _hal_ckg_spi_pm[u8Idx].u8Clk) ++ { ++ if (u8Idx) ++ u8PmIdx = u8Idx - 1; ++ else ++ u8PmIdx = u8Idx; ++ break; ++ } ++ else ++ u8PmIdx = u8Idx; ++ } ++ ++ if (_hal_ckg_spi_nonpm[u8nonPmIdx].eClkCkg == NULL || _hal_ckg_spi_pm[u8PmIdx].eClkCkg == NULL) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("CLOCK NOT SUPPORT \n")); ++ return Ret; ++ } ++ ++ // NON-PM Doman ++ CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); ++ CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CKG_SPI_108MHZ,CLK0_CKG_SPI_MASK); // set ckg_spi ++ CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++ ++ // PM Doman ++ PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++ PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[u8PmIdx].eClkCkg,PM_SPI_CLK_SEL_MASK); // set ckg_spi ++ PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++ Ret = TRUE; ++ return Ret; ++} ++ ++void HAL_SPINAND_CSCONFIG(void) ++{ ++ U16 u16Data; ++ u16Data = CHIP_READ(REG_CHIPTOP_DUMMY3); ++ u16Data |= CHIP_CS_PAD1; ++ CHIP_WRITE(REG_CHIPTOP_DUMMY3, u16Data); ++} ++ ++BOOL HAL_SPINAND_IsActive(void) ++{ ++// U16 u16Reg; ++ // Chiptop, offset 0x04, bit 4 : spi nand mode ++// u16Reg = CHIP_READ(0x04); ++// if (u16Reg&0x10) ++ return 1; ++// else ++// return 0; ++} ++ ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr) ++{ ++ U8 u8WbufIndex = 0; ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, u8Addr); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 1); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("WP Wait FSP Done Time Out !!!!\r\n")); ++ return FALSE; ++ } ++ _HAL_FSP_GetRData((u8Status), 1); ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ return ERR_SPINAND_SUCCESS; ++} ++ ++U8 HAL_SPINAND_WriteStatusRegister(U8* u8Status, U8 u8Addr) ++{ ++ U8 u8WbufIndex = 0; ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_SF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, u8Addr); ++ u8WbufIndex++; ++ ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, *u8Status); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 3); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("WP Wait FSP Done Time Out !!!!\r\n")); ++ return FALSE; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return TRUE; ++} ++ ++U8 HAL_QSPI_FOR_DEBUG(void) ++{ ++ return ((U8)(PM_READ(0x34))); ++} +diff --git a/drivers/sstar/spinand/hal/infinity2/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity2/mhal_spinand.h +new file mode 100755 +index 000000000000..90a6a16cef45 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2/mhal_spinand.h +@@ -0,0 +1,127 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG FALSE ++#define XIP_FLAG TRUE ++// Write method ++#define BDMA_W_FLAG FALSE ++#define DENSITY_2G 2048 ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity2/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity2/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..1c2efaa47a6e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2/mhal_spinand_chip_config.c +@@ -0,0 +1,26 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ /*chip dependence configure*/ ++} +diff --git a/drivers/sstar/spinand/hal/infinity2/reg_spinand.h b/drivers/sstar/spinand/hal/infinity2/reg_spinand.h +new file mode 100755 +index 000000000000..5a8dd779ad54 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2/reg_spinand.h +@@ -0,0 +1,192 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I2_RIU_PM_BASE 0xFD000000 ++#define I2_RIU_BASE 0xFD200000 ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++#define BK_FSP 0x2C00 ++#define BK_QSPI 0x2E00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x1200 ++#define BK_CHIP 0x3C00 ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity2m/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity2m/mhal_spinand.h +new file mode 100755 +index 000000000000..3b3c42960390 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2m/mhal_spinand.h +@@ -0,0 +1,126 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG TRUE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity2m/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity2m/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..1c2efaa47a6e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2m/mhal_spinand_chip_config.c +@@ -0,0 +1,26 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ /*chip dependence configure*/ ++} +diff --git a/drivers/sstar/spinand/hal/infinity2m/reg_spinand.h b/drivers/sstar/spinand/hal/infinity2m/reg_spinand.h +new file mode 100755 +index 000000000000..ced7f50f019d +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity2m/reg_spinand.h +@@ -0,0 +1,193 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++ ++#define BK_FSP 0x2C00 ++#define BK_QSPI 0x2E00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x0400 ++#define BK_CHIP 0x3C00 ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78*2 ++#define REG_FSP_WBF_OUTSIDE 0x79*2 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity3/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity3/mhal_spinand.h +new file mode 100755 +index 000000000000..1cc1c318b773 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity3/mhal_spinand.h +@@ -0,0 +1,127 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG FALSE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity3/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity3/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..1c2efaa47a6e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity3/mhal_spinand_chip_config.c +@@ -0,0 +1,26 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ /*chip dependence configure*/ ++} +diff --git a/drivers/sstar/spinand/hal/infinity3/reg_spinand.h b/drivers/sstar/spinand/hal/infinity3/reg_spinand.h +new file mode 100755 +index 000000000000..ced7f50f019d +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity3/reg_spinand.h +@@ -0,0 +1,193 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++ ++#define BK_FSP 0x2C00 ++#define BK_QSPI 0x2E00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x0400 ++#define BK_CHIP 0x3C00 ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78*2 ++#define REG_FSP_WBF_OUTSIDE 0x79*2 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity5/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity5/mhal_spinand.h +new file mode 100755 +index 000000000000..a58479c8c547 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity5/mhal_spinand.h +@@ -0,0 +1,132 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++#if defined(CONFIG_NAND_QUAL_READ) ++#define SUPPORT_SPINAND_QUAD 1 ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG TRUE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++void HAL_SPINAND_PreHandle(SPINAND_MODE eMode); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity5/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity5/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..1c2efaa47a6e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity5/mhal_spinand_chip_config.c +@@ -0,0 +1,26 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ /*chip dependence configure*/ ++} +diff --git a/drivers/sstar/spinand/hal/infinity5/reg_spinand.h b/drivers/sstar/spinand/hal/infinity5/reg_spinand.h +new file mode 100755 +index 000000000000..ced7f50f019d +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity5/reg_spinand.h +@@ -0,0 +1,193 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++ ++#define BK_FSP 0x2C00 ++#define BK_QSPI 0x2E00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x0400 ++#define BK_CHIP 0x3C00 ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78*2 ++#define REG_FSP_WBF_OUTSIDE 0x79*2 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity6/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity6/mhal_spinand.h +new file mode 100755 +index 000000000000..2f1e4cbbf44c +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6/mhal_spinand.h +@@ -0,0 +1,127 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG TRUE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity6/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity6/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..1c2efaa47a6e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6/mhal_spinand_chip_config.c +@@ -0,0 +1,26 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ /*chip dependence configure*/ ++} +diff --git a/drivers/sstar/spinand/hal/infinity6/reg_spinand.h b/drivers/sstar/spinand/hal/infinity6/reg_spinand.h +new file mode 100755 +index 000000000000..ced7f50f019d +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6/reg_spinand.h +@@ -0,0 +1,193 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++ ++#define BK_FSP 0x2C00 ++#define BK_QSPI 0x2E00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x0400 ++#define BK_CHIP 0x3C00 ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78*2 ++#define REG_FSP_WBF_OUTSIDE 0x79*2 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity6b0/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity6b0/mhal_spinand.h +new file mode 100755 +index 000000000000..2f1e4cbbf44c +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6b0/mhal_spinand.h +@@ -0,0 +1,127 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG TRUE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity6b0/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity6b0/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..1c2efaa47a6e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6b0/mhal_spinand_chip_config.c +@@ -0,0 +1,26 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ /*chip dependence configure*/ ++} +diff --git a/drivers/sstar/spinand/hal/infinity6b0/reg_spinand.h b/drivers/sstar/spinand/hal/infinity6b0/reg_spinand.h +new file mode 100755 +index 000000000000..ced7f50f019d +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6b0/reg_spinand.h +@@ -0,0 +1,193 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++ ++#define BK_FSP 0x2C00 ++#define BK_QSPI 0x2E00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x0400 ++#define BK_CHIP 0x3C00 ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78*2 ++#define REG_FSP_WBF_OUTSIDE 0x79*2 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity6e/mhal_spinand.h b/drivers/sstar/spinand/hal/infinity6e/mhal_spinand.h +new file mode 100755 +index 000000000000..2f1e4cbbf44c +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6e/mhal_spinand.h +@@ -0,0 +1,127 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG TRUE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/infinity6e/mhal_spinand_chip_config.c b/drivers/sstar/spinand/hal/infinity6e/mhal_spinand_chip_config.c +new file mode 100755 +index 000000000000..ea6a06e8089f +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6e/mhal_spinand_chip_config.c +@@ -0,0 +1,48 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: nick.lin ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++ ++extern hal_fsp_t _hal_fsp; ++ ++//check Bounding Type bank 0x101E , offset 0x48 bit[5:4] ++#define CHIP_BOUND_TYPES (0x30) ++#define CHIP_BOUND_QFN88 0x00//00: QFN88 ++#define CHIP_BOUND_QFN128 (0x10)//01: QFN128 ++#define CHIP_BOUND_BGA1 (0x20)//10: BGA1 ++#define CHIP_BOUND_BGA2A2B (0x30)//11: BGA2A & BGA2B ++ ++void HAL_SPINAND_Chip_Config(void) ++{ ++ U8 u8BoundID; ++ ++ //chekc boundID to select pm-spi or non-pm spi ++ u8BoundID = CHIP_READ(0x48) & CHIP_BOUND_TYPES; ++ switch(u8BoundID) ++ { ++ case CHIP_BOUND_QFN88: ++ _hal_fsp.u32FspBaseAddr = I3_RIU_PM_BASE + BK_PM_FSP; ++ _hal_fsp.u32QspiBaseAddr = I3_RIU_PM_BASE + BK_PM_QSPI; ++ break; ++ default: ++ _hal_fsp.u32FspBaseAddr = I3_RIU_BASE + BK_FSP; ++ _hal_fsp.u32QspiBaseAddr = I3_RIU_BASE + BK_QSPI; ++ break; ++ } ++ ++} +diff --git a/drivers/sstar/spinand/hal/infinity6e/reg_spinand.h b/drivers/sstar/spinand/hal/infinity6e/reg_spinand.h +new file mode 100755 +index 000000000000..3c52c3d4b07d +--- /dev/null ++++ b/drivers/sstar/spinand/hal/infinity6e/reg_spinand.h +@@ -0,0 +1,197 @@ ++/* ++* reg_spinand.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef _REG_SPINAND_H_ ++#define _REG_SPINAND_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++//------------------------------ ++#define I3_RIU_PM_BASE 0xFD000000 ++#define I3_RIU_BASE 0xFD200000 ++ ++#define BK_PM_FSP 0x2C00 ++#define BK_PM_QSPI 0x2E00 ++#define BK_FSP 0x1A00 ++#define BK_QSPI 0x1C00 ++#define BK_PMSLP 0x1C00 ++#define BK_CLK0 0x1600 ++#define BK_BDMA 0x0400 ++#define BK_CHIP 0x3C00 ++#define PM_FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_PM_BASE, BK_PM_FSP) ++#define PM_QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_PM_BASE, BK_PM_QSPI) ++#define FSP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_FSP) ++#define QSPI_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_QSPI) ++#define PMSLP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_PMSLP) ++#define CLK0_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CLK0) ++#define BDMA_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_BDMA) ++#define CHIP_REG_BASE_ADDR GET_REG_ADDR(I3_RIU_BASE, BK_CHIP) ++ ++//----- Chip flash ------------------------- ++// #include "mhal_chiptop_reg.h" ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_27MHZ BITS(4:2, 1) ++#define CLK0_CKG_SPI_36MHZ BITS(4:2, 2) ++#define CLK0_CKG_SPI_43MHZ BITS(4:2, 3) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_72MHZ BITS(4:2, 5) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++//CHIP_TOP ++#define REG_CHIPTOP_DUMMY3 0x1F ++#define CHIP_CS_PAD1 0x100 ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++#define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++#define PM_SPI_CLK_XTALI BITS(13:10, 0) ++#define PM_SPI_CLK_27MHZ BITS(13:10, 1) ++#define PM_SPI_CLK_36MHZ BITS(13:10, 2) ++#define PM_SPI_CLK_43MHZ BITS(13:10, 3) ++#define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++#define PM_SPI_CLK_72MHZ BITS(13:10, 5) ++#define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++#define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++#define PM_SPI_CLK_24MHZ BITS(13:10, 15) ++#define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++#define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++#define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define CHK_NUM_WAITDONE 20000 ++ ++// FSP Register ++#define REG_FSP_WRITE_BUFF 0x60*2 ++#define REG8_FSP_COMMAND 0x00 ++#define REG8_FSP_COMMAND1 0x01 ++#define REG8_FSP_RADDR_L 0x03 ++#define REG8_FSP_RADRR_M 0x02 ++#define REG8_FSP_RADDR_H 0x01 ++#define REG8_FSP_WADDR_L 0x04 ++#define REG8_FSP_WADDR_M 0x03 ++#define REG8_FSP_WADDR_H 0x02 ++ ++#define REG8_FSP_WDATA 0x05 ++#define REG8_FSP_WDATA10 0x10 ++ ++#define REG_FSP_QUAD_MODE 0x75*2 ++#define REG_FSP_READ_BUFF 0x65*2 ++#define REG_FSP_WRITE_SIZE 0x6A*2 ++#define REG_FSP_READ_SIZE 0x6B*2 ++#define REG_FSP_CTRL 0x6C*2 ++#define REG_FSP_TRIGGER 0x6D*2 ++#define TRIGGER_FSP 1 ++#define REG_FSP_DONE 0x6E*2 ++#define DONE_FSP 1 ++#define REG_FSP_AUTO_CHECK_ERROR 0x6E*2 ++#define AUTOCHECK_ERROR_FSP 2 ++#define REG_FSP_CLEAR_DONE 0x6F*2 ++#define CLEAR_DONE_FSP 1 ++#define REG_FSP_WRITE_BUFF2 0x70*2 ++#define FSP_WRITE_BUF_JUMP_OFFSET 0x0A ++#define REG_FSP_CTRL2 0x75*2 ++#define REG_FSP_CTRL3 0x75*2 ++#define REG_FSP_CTRL4 0x76*2 ++#define REG_FSP_WDATA 0x00 ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78*2 ++#define REG_FSP_WBF_OUTSIDE 0x79*2 ++ ++ ++#define REG_FSP_RDATA 0x05 ++#define MAX_WRITE_BUF_CNT 17 ++#define SINGLE_WRITE_SIZE 15 ++ ++#define REG_FSP_RSIZE 0x0B ++#define MAX_READ_BUF_CNT 10 ++ ++#define ENABLE_FSP_QUAD 1 ++#define ENABLE_FSP 1 ++#define RESET_FSP 2 ++#define INT_FSP 4 ++#define AUTOCHECK_FSP 8 ++#define ENABLE_SEC_CMD 0x8000 ++#define ENABLE_THR_CMD 0x4000 ++#define ENCMD2_3 0xF000 ++#define FLASH_BUSY_BIT 1 ++#define FLASH_WRITE_ENANLE 2 ++#define FLASH_BUSY_BIT_EREASE 3 ++// writet protect register ++#define WRITE_PROTECT_ENABLE 0xFC ++#define WRITE_PROTECT_DISABLE 0x00 ++ ++//QSPI Register ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++#define REG_SPI_WRAP_VAL 0x54 ++#define REG_SPI_WRAP_BIT_OFFSET 0x8 ++#define REG_SPI_WRAP_BIT_MASK 0xF ++#define REG_SPI_CKG_SPI 0x70 ++#define REG_SPI_USER_DUMMY_EN 0x10 ++#define REG_SPI_DUMMY_CYC_SINGLE 0x07 ++#define REG_SPI_DUMMY_CYC_DUAL 0x03 ++#define REG_SPI_DUMMY_CYC_QUAD 0x01 ++#define REG_SPI_MODE_SEL 0x72 ++#define REG_SPI_NORMAL_MODE 0x00 ++#define REG_SPI_FAST_READ 0x01 ++#define REG_SPI_CMD_3B 0x02 ++#define REG_SPI_CMD_BB 0x03 ++#define REG_SPI_CMD_6B 0x0A ++#define REG_SPI_CMD_EB 0x0B ++#define REG_SPI_CMD_0B 0x0C ++#define REG_SPI_CMD_4EB 0x0D ++#define REG_SPI_FUNC_SET 0x7D ++#define REG_SPI_ADDR2_EN 0x800 ++#define REG_SPI_DUMMY_EN 0x1000 ++//only for two plane nand ++#define REG_SPI_WRAP_EN 0x2000 ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++#define _BIT(x) (1<<(x)) ++ ++#define BMASK(bits) (_BIT(((1)?bits)+1)-_BIT(((0)?bits))) ++#define BITS(bits,value) ((_BIT(((1)?bits)+1)-_BIT(((0)?bits))) & (value<<((0)?bits))) ++ ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#endif // _REG_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/mercury6/mhal_spinand.h b/drivers/sstar/spinand/hal/mercury6/mhal_spinand.h +new file mode 100755 +index 000000000000..ef3a06eaddf3 +--- /dev/null ++++ b/drivers/sstar/spinand/hal/mercury6/mhal_spinand.h +@@ -0,0 +1,126 @@ ++/* ++* mhal_spinand.h- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#ifndef _HAL_SPINAND_H_ ++#define _HAL_SPINAND_H_ ++#include "mdrv_spinand_common.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Structures definition ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 u32FspBaseAddr; // REG_ISP_BASE ++ U32 u32QspiBaseAddr; // REG_QSPI_BASE ++ U32 u32PMBaseAddr; // REG_PM_BASE ++ U32 u32CLK0BaseAddr; // REG_PM_BASE ++ U32 u32CHIPBaseAddr; // REG_CHIP_BASE ++ U32 u32RiuBaseAddr; // REG_PM_BASE ++ U32 u32BDMABaseAddr; // REG_BDMA_BASE ++} hal_fsp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++#define READ_WORD(_reg) (*(volatile U16*)(_reg)) ++#define WRITE_WORD(_reg, _val) { (*((volatile U16*)(_reg))) = (U16)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile U16*)(_reg))) = ((*((volatile U16*)(_reg))) & ~(_mask)) | ((U16)(_val) & (_mask)); } ++#define BDMA_READ(addr) READ_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2)) ++#define BDMA_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32BDMABaseAddr + (addr<<2),(val)) ++#define QSPI_READ(addr) READ_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32QspiBaseAddr + (addr<<2),(val)) ++#define CLK_READ(addr) READ_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2)) ++#define CLK_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CLK0BaseAddr + (addr<<2),(val)) ++#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++#define CHIP_READ(addr) READ_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2)) ++#define CHIP_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32CHIPBaseAddr + (addr<<2),(val)) ++#define CHIP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32CHIPBaseAddr + ((addr)<<2), (val), (mask)) ++#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_fsp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++#define PM_READ(addr) READ_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2)) ++#define PM_WRITE(addr, val) WRITE_WORD(_hal_fsp.u32PMBaseAddr + (addr<<2),(val)) ++#define ISP_READ(addr) READ_WORD(_hal_fsp.u32ISPBaseAddr + (addr<<2)) ++ ++// Read method ++#define RIU_FLAG FALSE ++#define BDMA_FLAG TRUE ++#define XIP_FLAG FALSE ++// Write method ++#define BDMA_W_FLAG TRUE ++ ++#define MS_SPI_ADDR 0x14000000 ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern SPINAND_FLASH_INFO_t _gtSpinandInfo; ++extern U8 _u8SPINANDDbgLevel; ++void HAL_SPINAND_DieSelect(U8 u8Die); ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr); ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr); ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_Write( U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf); ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data); ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data); ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr); ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx); ++U32 HAL_SPINAND_Init(void); ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable); ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr); ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode); ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi); ++void HAL_SPINAND_CSCONFIG(void); ++BOOL HAL_SPINAND_IsActive(void); ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData); ++U8 HAL_QSPI_FOR_DEBUG(void); ++void HAL_SPINAND_Chip_Config(void); ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#endif // _HAL_SPINAND_H_ +diff --git a/drivers/sstar/spinand/hal/mhal_spinand.c b/drivers/sstar/spinand/hal/mhal_spinand.c +new file mode 100755 +index 000000000000..cc3ff3c8874e +--- /dev/null ++++ b/drivers/sstar/spinand/hal/mhal_spinand.c +@@ -0,0 +1,1728 @@ ++/* ++* mhal_spinand.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: edie.chen ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include "mhal_spinand.h" ++#include "reg_spinand.h" ++#include "mdrv_spinand_command.h" ++#include "mdrv_spinand_common.h" ++#include ++#include ++// #include "registers.h" ++// #include "registers.h" ++// #include "chip_int.h" ++// #include "chip_setup.h" ++#define spi_nand_err(fmt, ...) printk(KERN_ERR "%s:error, " fmt "\n", __func__, ##__VA_ARGS__) ++MS_U32 BASE_SPI_OFFSET = 0; ++ ++//extern struct device *spi_nand_dev; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro definition ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ U8 u8Clk; ++ U16 eClkCkg; ++} hal_clk_ckg_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_NAND_SINGLE_READ ++SPINAND_MODE gNandReadMode= E_SPINAND_SINGLE_MODE; ++#endif ++ ++#ifdef CONFIG_NAND_DUAL_READ ++SPINAND_MODE gNandReadMode=E_SPINAND_DUAL_MODE; ++#endif ++ ++#if defined (CONFIG_NAND_QUAL_READ)|| defined(CONFIG_NAND_QUAL_WRITE) ++SPINAND_MODE gNandReadMode=E_SPINAND_QUAD_MODE; ++#endif ++ ++ ++hal_fsp_t _hal_fsp = ++{ ++ .u32FspBaseAddr = I3_RIU_PM_BASE + BK_FSP, ++ .u32QspiBaseAddr = I3_RIU_PM_BASE + BK_QSPI, ++ .u32PMBaseAddr = I3_RIU_PM_BASE + BK_PMSLP, ++ .u32CLK0BaseAddr = I3_RIU_BASE + BK_CLK0, ++ .u32CHIPBaseAddr = I3_RIU_BASE + BK_CHIP, ++ .u32RiuBaseAddr= I3_RIU_PM_BASE, ++ .u32BDMABaseAddr = I3_RIU_BASE + BK_BDMA, ++}; ++ ++// ++// Spi Clk Table (List) ++// ++static hal_clk_ckg_t _hal_ckg_spi_pm[] = { ++ {12 , PM_SPI_CLK_XTALI } ++ ,{27 , PM_SPI_CLK_27MHZ } ++ ,{36 , PM_SPI_CLK_36MHZ } ++ ,{43 , PM_SPI_CLK_43MHZ } ++ ,{54 , PM_SPI_CLK_54MHZ } ++ ,{72 , PM_SPI_CLK_72MHZ } ++ ,{86 , PM_SPI_CLK_86MHZ } ++ ,{108, PM_SPI_CLK_108MHZ} ++}; ++ ++static hal_clk_ckg_t _hal_ckg_spi_nonpm[] = { ++ {12 , CLK0_CKG_SPI_XTALI } ++ ,{27 , CLK0_CKG_SPI_27MHZ } ++ ,{36 , CLK0_CKG_SPI_36MHZ } ++ ,{43 , CLK0_CKG_SPI_43MHZ } ++ ,{54 , CLK0_CKG_SPI_54MHZ } ++ ,{72 , CLK0_CKG_SPI_72MHZ } ++ ,{86 , CLK0_CKG_SPI_86MHZ } ++ ,{108, CLK0_CKG_SPI_108MHZ} ++}; ++ ++U8 _u8SPINANDDbgLevel; ++ ++static struct bdma_alloc_dmem ++{ ++ dma_addr_t bdma_phy_addr ; ++ const char* DMEM_BDMA_INPUT; ++ u8 *bdma_vir_addr; ++}ALLOC_DMEM = {0, "BDMA", 0}; ++ ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++// ++// static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr ) ++// { ++// MSYS_DMEM_INFO dmem; ++// memcpy(dmem.name,name,strlen(name)+1); ++// dmem.length=size; ++// dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++// dmem.phys=(unsigned long long)((uintptr_t)addr); ++// msys_release_dmem(&dmem); ++// } ++ ++// static void _ms_bdma_mem_free(U32 u32DataSize) ++// { ++// if(ALLOC_DMEM.bdma_vir_addr != 0){ ++// free_dmem(ALLOC_DMEM.DMEM_BDMA_INPUT, u32DataSize, ALLOC_DMEM.bdma_vir_addr, ALLOC_DMEM.bdma_phy_addr); ++// ALLOC_DMEM.bdma_vir_addr = 0; ++// } ++// } ++ ++BOOL _gbRIURead = FALSE; ++ ++static BOOL FSP_WRITE_BYTE(U32 u32RegAddr, U8 u8Val) ++{ ++ if (!u32RegAddr) ++ { ++ printk(KERN_ERR"%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ((volatile U8*)(_hal_fsp.u32FspBaseAddr))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ return TRUE; ++} ++ ++static BOOL FSP_WRITE(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ printk(KERN_ERR"%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ((volatile U16*)(_hal_fsp.u32FspBaseAddr))[u32RegAddr] = u16Val; ++ return TRUE; ++} ++ ++static U8 FSP_READ_BYTE(U32 u32RegAddr) ++{ ++ return ((volatile U8*)(_hal_fsp.u32FspBaseAddr))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++} ++ ++static U16 FSP_READ(U32 u32RegAddr) ++{ ++ return ((volatile U16*)(_hal_fsp.u32FspBaseAddr))[u32RegAddr]; ++} ++ ++static void _HAL_SPINAND_BDMA_INIT(U32 u32DataSize) ++{ ++ if (!(ALLOC_DMEM.bdma_vir_addr = alloc_dmem(ALLOC_DMEM.DMEM_BDMA_INPUT, ++ u32DataSize, ++ &ALLOC_DMEM.bdma_phy_addr))){ ++ printk("[input]unable to allocate aesdma memory\n"); ++ } ++ ++ memset(ALLOC_DMEM.bdma_vir_addr, 0, u32DataSize); ++} ++ ++static BOOL _HAL_FSP_ChkWaitDone(void) ++{ ++//consider as it spend very long time to check if FSP done, so it may implment timeout method to improve ++ U16 u16Try = 0; ++ U8 u8DoneFlag = 0; ++ ++ while (u16Try < CHK_NUM_WAITDONE) ++ { ++ u8DoneFlag = FSP_READ(REG_FSP_DONE); ++ if ((u8DoneFlag & DONE_FSP) == DONE_FSP) ++ { ++ return TRUE; ++ } ++ ++ if (++u16Try%1000 == 0) ++ cond_resched(); ++ ++ udelay(1); ++ } ++ return FALSE; ++} ++ ++static void _HAL_FSP_GetRData(U8 *pu8Data, U8 u8DataSize) ++{ ++ U8 u8Index = 0; ++ //printk(KERN_ERR"_HAL_FSP_GetRData %lx\r\n",(U32)u8DataSize); ++ for (u8Index = 0; u8Index < u8DataSize; u8Index++) ++ { ++ pu8Data[u8Index] = FSP_READ_BYTE(REG_FSP_READ_BUFF + u8Index); ++ } ++} ++ ++static U32 _HAL_FSP_CHECK_SPINAND_DONE(U8 *pu8Status) ++{ ++ U8 u8Data = SPI_NAND_STAT_OIP; ++ U16 u16Try = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_GF); ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + 1, SPI_NAND_REG_STAT); ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x2); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x1); ++ ++ while (1) //while(u16Try < CHK_NUM_WAITDONE) ++ { ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"CD Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ _HAL_FSP_GetRData(&u8Data, 1); ++ if ((u8Data & SPI_NAND_STAT_OIP) == 0 ) ++ break; ++ ++ if (++u16Try%1000 == 0) ++ cond_resched(); ++ ++ udelay(1); ++ } ++ ++ if (u16Try == CHK_NUM_WAITDONE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"CD Wait OIP Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ if (pu8Status) ++ *pu8Status = u8Data; ++ ++ return ERR_SPINAND_SUCCESS; ++} ++ ++static U32 _HAL_SPINAND_WRITE_ENABLE(void) ++{ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_WREN); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x1); ++ // read buffer size ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"WE Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ return ERR_SPINAND_SUCCESS; ++ ++} ++ ++U32 HAL_SPINAND_RIU_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData) ++{ ++ U32 u32Index = 0; ++ U8 u8Addr = 0; ++ U32 u32RealLength = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_RFC); ++ u8WbufIndex++; ++ ++ //Set Write & Read Length ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 4); //add 4 because it is included of command and Address setting length ++ if (u32DataSize > MAX_READ_BUF_CNT) ++ FSP_WRITE(REG_FSP_READ_SIZE, MAX_READ_BUF_CNT); ++ else ++ FSP_WRITE(REG_FSP_READ_SIZE, u32DataSize); ++ ++ for (u32Index = 0; u32Index < u32DataSize; u32Index +=MAX_READ_BUF_CNT) ++ { ++ ++ for (s8Index = (SPI_NAND_PAGE_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u16Addr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u8Addr); ++ u8WbufIndex++; ++ } ++ // set dummy byte ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), 0x00); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RIUR Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ //Get Read Data ++ u32RealLength = u32DataSize - u32Index; ++ if (u32RealLength >= MAX_READ_BUF_CNT) ++ u32RealLength = MAX_READ_BUF_CNT; ++ ++ _HAL_FSP_GetRData((u8pData + u32Index), u32RealLength); ++ ++ //Clear FSP done flag ++ FSP_WRITE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ // update Read Start Address ++ u16Addr += u32RealLength; ++ u8WbufIndex -= SPI_NAND_PAGE_ADDR_LEN; ++ ++ } ++ return ERR_SPINAND_SUCCESS; ++} ++ ++static U32 _HAL_SPINAND_BDMA_READ(U16 u16Addr, U32 u32DataSize, U8 *u8pData) ++{ ++ ++ U16 u16data = 0; ++ U32 u32Timer = 0; ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ ++ //Set source and destination path ++ BDMA_WRITE(0x00, 0x0000); ++ ++ ++// u32Addr1 = dma_map_single(spi_nand_dev, (void*)u8pData, u32DataSize, DMA_FROM_DEVICE); ++ ++ BDMA_WRITE(0x02, 0X4035); //5:source device (spi) ++ //3:source device data width (8 bytes) ++ //0:destination device (channel0) ++ //4:destination device data width (16 bytes) ++ ++ BDMA_WRITE(0x03, 0X0000); //0: channel0 => MIU0 ++ ++ // Set start address ++ BDMA_WRITE(0x04, (u16Addr & 0x0000FFFF)); ++ BDMA_WRITE(0x05, (u16Addr>>16)); ++ ++ // Set end address ++ BDMA_WRITE(0x06, (Chip_Phys_to_MIU(ALLOC_DMEM.bdma_phy_addr) & 0x0000FFFF)); ++ BDMA_WRITE(0x07, (Chip_Phys_to_MIU(ALLOC_DMEM.bdma_phy_addr) >> 16)); ++ ++ // Set Size ++ BDMA_WRITE(0x08, (u32DataSize & 0x0000FFFF)); ++ BDMA_WRITE(0x09, (u32DataSize >> 16)); ++ ++ // Trigger ++ BDMA_WRITE(0x00, 1); ++ ++ do ++ { ++ //check done ++ u16data = BDMA_READ(0x01); ++ if (u16data & 8) ++ { ++ //clear done ++ BDMA_WRITE(0x01, 8); ++ u32Ret = ERR_SPINAND_SUCCESS; ++ break; ++ } ++ if (++u32Timer%1000 == 0) ++ cond_resched(); ++ ++ udelay(1); ++ } while (u32Timer < CHK_NUM_WAITDONE); ++ ++// dma_unmap_single(spi_nand_dev, u32Addr1, u32DataSize, DMA_FROM_DEVICE); ++ memcpy(u8pData, ALLOC_DMEM.bdma_vir_addr, u32DataSize); ++ ++// _ms_bdma_mem_free(u32DataSize); ++ ++ return u32Ret; ++} ++ ++void HAL_SPINAND_SetNormalMode(void) ++{ ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_NORMAL_MODE); ++} ++ ++void HAL_SPINAND_AssertNormalMode(void) ++{ ++ U16 u16Reg; ++ BOOL bBug = FALSE; ++ ++ u16Reg = QSPI_READ(REG_SPI_CKG_SPI); ++ if((u16Reg & REG_SPI_USER_DUMMY_EN) && ((u16Reg & 0xF) != REG_SPI_DUMMY_CYC_SINGLE)) ++ { ++ printk("Invalid REG_SPI_CKG_SPI %X\n", u16Reg); ++ bBug = TRUE; ++ } ++ u16Reg = QSPI_READ(REG_SPI_MODE_SEL); ++ if(((u16Reg & 0xF) != REG_SPI_NORMAL_MODE) && ((u16Reg & 0xF) != REG_SPI_FAST_READ)) ++ { ++ printk("Invalid REG_SPI_MODE_SEL %X\n", u16Reg); ++ bBug = TRUE; ++ } ++ if(bBug) ++ { ++ dump_stack(); ++ HAL_SPINAND_SetNormalMode(); ++ } ++} ++ ++void HAL_SPINAND_PreHandle(SPINAND_MODE eMode) ++{ ++ U8 u8Status = 0; ++ U16 u16Reg; ++ ++ HAL_SPINAND_SetNormalMode(); ++ ++ u16Reg = QSPI_READ(REG_SPI_CKG_SPI); ++ if((u16Reg & 0xF) != REG_SPI_DUMMY_CYC_SINGLE) ++ { ++ printk("Invalid REG_SPI_CKG_SPI %X\n", u16Reg); ++ BUG(); ++ } ++ u16Reg = QSPI_READ(REG_SPI_MODE_SEL); ++ if((u16Reg & 0xF) != REG_SPI_NORMAL_MODE) ++ { ++ printk("Invalid REG_SPI_MODE_SEL %X\n", u16Reg); ++ BUG(); ++ } ++ //if (_gtSpinandInfo.au8_ID[0] == 0xC8) ++ { ++ switch (eMode) ++ { ++ case E_SPINAND_SINGLE_MODE: ++ case E_SPINAND_FAST_MODE: ++ case E_SPINAND_DUAL_MODE: ++ case E_SPINAND_DUAL_MODE_IO: //GD support If QE is enabled, the quad IO operations can be executed. ++ HAL_SPINAND_ReadStatusRegister(&u8Status, SPI_NAND_REG_FEAT); //output:u8Status is OTP data. ++ if(u8Status & QUAD_ENABLE) ++ { ++ u8Status &= ~(QUAD_ENABLE); ++ HAL_SPINAND_WriteStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ } ++ break; ++ case E_SPINAND_QUAD_MODE: ++ case E_SPINAND_QUAD_MODE_IO: //GD support ++ HAL_SPINAND_ReadStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ if((u8Status & QUAD_ENABLE) == 0) ++ { ++ u8Status |= QUAD_ENABLE; ++ HAL_SPINAND_WriteStatusRegister(&u8Status, SPI_NAND_REG_FEAT); ++ } ++ break; ++ } ++ } ++} ++ ++U32 HAL_SPINAND_Init(void) ++{ ++ U8 u8Status = 0; ++ ++ HAL_SPINAND_Chip_Config(); ++ ++ //set pad mux for spinand ++// printk("MDrv_SPINAND_Init: Set pad mux\n"); ++ CHIP_WRITE(0x50, 0x000);//disable all pad in ++ QSPI_WRITE(0x7A, 0x00);//CS ++// PM_WRITE(0x35, 0x08); //SPI FUART MAY USE THIS PAD ++ if(BDMA_FLAG) ++ _HAL_SPINAND_BDMA_INIT(2048+64); ++// printk("MDrv_SPINAND_Init: Set pad mux end"); ++ ++ // reset spinand ++ // FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_RESET); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 1); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"INI Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ // For first RESET condition after power up, tRST will be 1ms maximum ++ return _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++} ++ ++void HAL_SPINAND_Config(U32 u32PMRegBaseAddr, U32 u32NonPMRegBaseAddr) ++{ ++ DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk(KERN_INFO"%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr)); ++ _hal_fsp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_fsp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_fsp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_fsp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0;//BK_CLK0; ++ _hal_fsp.u32BDMABaseAddr = u32NonPMRegBaseAddr + BK_BDMA; ++ _hal_fsp.u32RiuBaseAddr = u32PMRegBaseAddr; ++} ++ ++BOOL HAL_SPINAND_PLANE_HANDLER(U32 u32Addr) ++{ ++ if (PLANE && (((u32Addr / BLOCK_PAGE_SIZE)&0x1) == 1)) //odd numbered blocks ++ { ++ u32Addr = QSPI_READ(REG_SPI_WRAP_VAL); ++ u32Addr |= (1 << REG_SPI_WRAP_BIT_OFFSET); ++ QSPI_WRITE(REG_SPI_WRAP_VAL, u32Addr); ++ } ++ else ++ { ++ u32Addr = QSPI_READ(REG_SPI_WRAP_VAL); ++ u32Addr &= ~(1 << REG_SPI_WRAP_BIT_OFFSET); ++ QSPI_WRITE(REG_SPI_WRAP_VAL, u32Addr); ++ } ++ return TRUE; ++} ++ ++void HAL_SPINAND_DieSelect (U8 u8Die) ++{ ++ if(u8Die != 0)//only 2 die ++ u8Die = 1; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_DIESELECT); ++ //Set Start Address ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + 1, u8Die); ++ //Set Write & Read Length ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("RID Wait FSP Done Time Out !!!!\r\n")); ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++} ++ ++U32 HAL_SPINAND_RFC(U32 u32Addr, U8 *pu8Data) ++{ ++ U8 u8Addr = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("HAL_SPINAND_RFC : u32Addr = %lx \r\n",u32Addr)); ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP|ENABLE_SEC_CMD)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++// FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_WREN); ++// u8WbufIndex++; ++ ++ //SECOND COMMAND READ COMMAND + 3BYTE ADDRESS ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_PGRD); ++ u8WbufIndex++; ++ //set Read Start Address ++ for (s8Index = (SPI_NAND_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u32Addr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ //THIRD COMMAND GET FATURE CHECK CAHCHE READY ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_REG_STAT); //read ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x024); //17-bit block/page address ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x010); //1 byte (receive from get feature) ++ ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RFC Wait FSP Done Time Out %lx !!!!\r\n",u32Addr)); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ _HAL_FSP_GetRData((pu8Data), 1); ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ return _HAL_FSP_CHECK_SPINAND_DONE(pu8Data); ++} ++ ++static U32 _HAL_SPINAND_BDMA_Write(U32 u32DataSize) ++{ ++ U32 u32Ret = ERR_SPINAND_SUCCESS; ++ ++ if(BDMA_READ(0x00) & 1) ++ { ++ BDMA_WRITE(0x00, 0x10); ++ if(BDMA_READ(0x00) & 0x10) ++ { ++ BDMA_WRITE(0x00, 0x00); ++ } ++ } ++ //Set source and destination path ++ BDMA_WRITE(0x00, 0x0000); ++ BDMA_WRITE(0x02, 0X2B40); //0:source device (channel0) ++ //4:source device data width (16 bytes) ++ //B:destination device (MIU) 1:destination device (IMI) ++ //2:destination device data width (16 bytes) ++ BDMA_WRITE(0x03, 0x0000); //channel0: MIU0 ++ ++ // Set start address ++ BDMA_WRITE(0x04, (Chip_Phys_to_MIU(ALLOC_DMEM.bdma_phy_addr) & 0x0000FFFF)); ++ BDMA_WRITE(0x05, (Chip_Phys_to_MIU(ALLOC_DMEM.bdma_phy_addr) >> 16)); ++ ++ // Set end address ++ BDMA_WRITE(0x06, (0x0 & 0x0000FFFF)); ++ BDMA_WRITE(0x07, (0x0 >> 16)); ++ ++ // Set Size ++ BDMA_WRITE(0x08, (u32DataSize & 0xFFFF)); ++ BDMA_WRITE(0x09, (u32DataSize >> 16)); ++ ++ // Trigger ++ BDMA_WRITE(0x00, 1); ++ ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_program_load_data(U16 u16_col_address, U8 *pu8_buf, U32 u32_size) ++{ ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ U8 u8WbufIndex = 0; ++ U32 u32WrteBuf = REG_FSP_WRITE_BUFF; ++ ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("u16ColumnAddr %x u16DataSize %x Data %x \r\n", u16ColumnAddr, u16DataSize, *pu8Data)); ++ // Write Enable ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ // while(HAL_QSPI_FOR_DEBUG()==0); ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP write Command ++ // FIRSET COMMAND PRELOAD ++ ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_PP); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), (u16_col_address >> 8) & 0xff); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), u16_col_address & 0xff); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u8WbufIndex); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ //Trigger FSP ++ ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u8WbufIndex = 0; ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE, REG_SPI_ENABLE_BURST); ++ ++ while (0 < u32_size) ++ { ++ while (SINGLE_WRITE_SIZE > u8WbufIndex) ++ { ++ if (u8WbufIndex == FSP_WRITE_BUF_JUMP_OFFSET) ++ { ++ u32WrteBuf = REG_FSP_WRITE_BUFF2; ++ } ++ ++ FSP_WRITE_BYTE((u32WrteBuf + (u8WbufIndex % FSP_WRITE_BUF_JUMP_OFFSET)), *pu8_buf); ++ //printk("0x%02x, ", *pu8_buf); ++ pu8_buf++; ++ u8WbufIndex++; ++ u32_size--; ++ ++ if (0 == u32_size) ++ { ++ break; ++ } ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u8WbufIndex); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ //Trigger FSP ++ ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ u8WbufIndex = 0; ++ u32WrteBuf = REG_FSP_WRITE_BUFF; ++ //QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return _HAL_FSP_CHECK_SPINAND_DONE(NULL); ++} ++ ++U32 HAL_SPINAND_PROGRAM_BY_BDMA(U16 u16ColumnAddr, U16 u16DataSize) ++{ ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ U8 u8Addr = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ U32 u32WrteBuf = REG_FSP_WRITE_BUFF; ++ U32 u32Timer = 0; ++ ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ _HAL_SPINAND_BDMA_Write(u16DataSize); ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP write Command ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_PP); ++#else ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_QPP); ++#endif ++ u8WbufIndex++; ++ ++ //PAGE Address ++ for (s8Index = (SPI_NAND_PAGE_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u16ColumnAddr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x3); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, (u16DataSize+1)&0x00FFFFFF); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x1003); ++ //trigger ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ u32Ret = ERR_SPINAND_BDMA_TIMEOUT; ++ //check BDMA don ++ do ++ { ++ //check done ++ if (BDMA_READ(0x01) & 8) ++ { ++ //clear done ++ BDMA_WRITE(0x01, 8); ++ u32Ret = ERR_SPINAND_SUCCESS; ++ break; ++ } ++ if (++u32Timer%1000 == 0) ++ cond_resched(); ++ udelay(1); ++ } while (u32Timer < CHK_NUM_WAITDONE); ++ if(u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"BDMA Time Out !!!!\r\n")); ++ } ++ ++ if(_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ u32Ret = ERR_SPINAND_TIMEOUT; ++ } ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return u32Ret; ++} ++ ++//4:Quad mode version BDMA ++U32 HAL_SPINAND_PROGRAM_BY_BDMA4(U16 u16ColumnAddr, U16 u16DataSize) ++{ ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ U8 u8Addr = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ U32 u32WrteBuf = REG_FSP_WRITE_BUFF; ++ U32 u32Timer = 0; ++ ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ //_HAL_SPINAND_BDMA_Write(u16DataSize); ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); //h6c reg_fsp_ctrl0 = BIT0 | BIT1 | BIT2 ++ FSP_WRITE(REG_FSP_CTRL2, 0); //h75 reg_fsp_ctrl2, reg_fsp_ctrl3 = 0 ++ FSP_WRITE(REG_FSP_CTRL4, 0); //h76 reg_fsp_ctrl4, reg_spare_0 = 0 ++ ++ //Set FSP write Command ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_PP); ++#else ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_QPP); ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, 0); ++#endif ++ u8WbufIndex++; ++ ++ //PAGE Address ++ for (s8Index = (SPI_NAND_PAGE_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u16ColumnAddr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x3); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x0); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ //set FSP Outside replace ++ //0 : wbf0 = reg_fsp_wbf_size_outside + reg_fsp_wbf_size0 ++ //trigger ++ QSPI_WRITE(REG_SPI_BURST_WRITE, 0); ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ if(_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ u32Ret = ERR_SPINAND_TIMEOUT; ++ } ++ ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, (u16DataSize+1) & 0x0FFF); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x1000);//reg_fsp_wbf_outside_en = 1, reg_fsp_wbf_mode = 0, reg_fsp_wbf_replaced = 3. ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x0); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x0); ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, ENABLE_FSP_QUAD); ++ _HAL_SPINAND_BDMA_Write(u16DataSize); ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //check BDMA done ++ u32Ret = ERR_SPINAND_BDMA_TIMEOUT; ++ do ++ { ++ //check done ++ if (BDMA_READ(0x01) & 8) ++ { ++ //clear done ++ BDMA_WRITE(0x01, 8); ++ u32Ret = ERR_SPINAND_SUCCESS; ++ break; ++ } ++ if (++u32Timer%1000 == 0) ++ cond_resched(); ++ udelay(1); ++ } while (u32Timer < CHK_NUM_WAITDONE); ++ if(u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"BDMA Time Out !!!!\r\n")); ++ } ++ ++ if(_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ u32Ret = ERR_SPINAND_TIMEOUT; ++ } ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ QSPI_WRITE(REG_SPI_BURST_WRITE, 0); ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x0); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x0); ++#ifndef CONFIG_AUTO_DETECT_WRITE ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, 0); ++#endif ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_PROGRAM_LOAD_DATA(U16 u16ColumnAddr, U16 u16DataSize, U8 *pu8Data, U8 *pu8_SpareBuf) ++{ ++ U32 u32Ret = ERR_SPINAND_TIMEOUT; ++ U8 u8Addr = 0, u8DataIndex =0; ++ U16 u16RealLength = 0, u16FspWriteSize = SINGLE_WRITE_SIZE; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ U32 u32WrteBuf = REG_FSP_WRITE_BUFF; ++ U16 u16DataIndex = 0; ++ U8 *pu8Wdata = NULL; ++ U8 u8Status = 0; ++ ++ pu8Wdata = pu8Data; ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("u16ColumnAddr %x u16DataSize %x Data %x \r\n", u16ColumnAddr, u16DataSize, *pu8Data)); ++ // Write Enable ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ // while(HAL_QSPI_FOR_DEBUG()==0); ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP write Command ++ // FIRSET COMMAND PRELOAD ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_PP); ++#else ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), SPI_NAND_CMD_QPP); ++#endif ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x00); ++ u8WbufIndex++; ++ ++ //PAGE Address ++ for (s8Index = (SPI_NAND_PAGE_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u16ColumnAddr >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++#ifdef CONFIG_NAND_QUAL_WRITE ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x003); ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ u8WbufIndex=0; ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, ENABLE_FSP_QUAD); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++#endif ++ ++ for (u16DataIndex = 0; u16DataIndex < u16DataSize; u16DataIndex+= u16RealLength) ++ { ++ u16RealLength = u16DataSize - u16DataIndex; ++ if (u16RealLength >= SINGLE_WRITE_SIZE) ++ { ++ u16RealLength = SINGLE_WRITE_SIZE - u8WbufIndex; ++ } ++ else ++ { ++ u16FspWriteSize = u16RealLength; ++ } ++ ++ //Write Data ++ for (u8DataIndex = 0; u8DataIndex < u16RealLength; u8DataIndex++) ++ { ++ if ((u16DataIndex + u8DataIndex)== PAGE_SIZE) ++ { ++ pu8Wdata = pu8_SpareBuf; ++ } ++ ++ //printk("u8DataIndex %x u16RealLength %x \r\n",u8DataIndex, u16RealLength); ++ FSP_WRITE_BYTE((u32WrteBuf + u8WbufIndex), *pu8Wdata); ++ u8WbufIndex++; ++ pu8Wdata++; ++ if (u8WbufIndex >= FSP_WRITE_BUF_JUMP_OFFSET) ++ { ++ u32WrteBuf = REG_FSP_WRITE_BUFF2; ++ u8WbufIndex = 0; ++ } ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u16FspWriteSize); ++ //Trigger FSP ++ ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PL Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u8WbufIndex = 0; ++ u32WrteBuf = REG_FSP_WRITE_BUFF; ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, 0); ++ ++ return _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ ++} ++ ++U32 HAL_SPINAND_READ_STATUS(U8 *pu8Status, U8 u8Addr) ++{ ++ U8 u8WbufIndex = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ //SECOND COMMAND SET READ PARAMETER ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u8Addr); ++ // write buffer size ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ // read buffer size ++ FSP_WRITE(REG_FSP_READ_SIZE, 1); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RS Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_SUCCESS; ++ } ++ //Get Read Data ++ _HAL_FSP_GetRData(pu8Status, 1); ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return ERR_SPINAND_SUCCESS; ++} ++ ++U32 HAL_SPINAND_BLOCKERASE(U32 u32_PageIdx) ++{ ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ U8 u8Addr = 0; ++ U32 u32Ret = 0; ++ U8 u8Status = 0; ++ ++ u32Ret = _HAL_SPINAND_WRITE_ENABLE(); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ u32Ret = HAL_SPINAND_WriteProtect(FALSE); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP|ENABLE_SEC_CMD|ENABLE_THR_CMD)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ // FIRSET COMMAND PRELOAD ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_WREN); ++ u8WbufIndex++; ++ ++ //SECOND COMMAND SET Erase Command ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_BE); ++ u8WbufIndex++; ++ ++ //seet erase Start Address ++ for (s8Index = (SPI_NAND_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u32_PageIdx >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ //THIRD COMMAND GET FATURE CHECK CAHCHE READY ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_REG_STAT); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x241); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x100); ++ ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"BE Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u32Ret = _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ { ++ if (u8Status & E_FAIL) ++ { ++ u32Ret = ERR_SPINAND_E_FAIL; ++ spi_nand_err("E_FAIL!!!\n"); ++ return u32Ret; ++ } ++ } ++ u32Ret = HAL_SPINAND_WriteProtect(TRUE); ++ ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_program(U32 u32_row_address, U16 u16_col_address, U8 *pu8_buf, U32 u32_size) ++{ ++ U32 u32Ret; ++ U8 u8WbufIndex = 0; ++ U8 u8Status; ++ ++ u32Ret = HAL_SPINAND_WriteProtect(FALSE); ++#if 0 ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ HAL_SPINAND_SetMode(WRITE_MODE); ++#else ++ //HAL_SPINAND_SetMode(gNandReadMode); ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++#endif ++#endif ++ if ((BLOCKCNT == DENSITY_2G) && (((u32_row_address / BLOCK_PAGE_SIZE)&0x1) == 1)) ++ u16_col_address = (1<<12); // plane select for MICRON ++ ++ u32Ret = HAL_SPINAND_program_load_data(u16_col_address, pu8_buf, u32_size); ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++ ++#ifdef CONFIG_NAND_QUAL_WRITE ++ FSP_WRITE_BYTE(REG_FSP_QUAD_MODE, 0); ++ HAL_SPINAND_PreHandle(E_SPINAND_SINGLE_MODE); ++#endif ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP | RESET_FSP | INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ // FIRST COMMAND PAGE PROGRAM EXECUTE ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_PE); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u32_row_address >> 16); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), (u32_row_address >> 8 & 0Xff)); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), u32_row_address & 0xff); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, u8WbufIndex); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x000); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u32Ret = _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ { ++ if (u8Status & P_FAIL) ++ { ++ u32Ret = ERR_SPINAND_W_FAIL; ++ spi_nand_err("P_FAIL!!!\n"); ++ return u32Ret; ++ } ++ } ++ u32Ret = HAL_SPINAND_WriteProtect(TRUE); ++ ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_Write(U32 u32_PageIdx, U8 *u8Data, U8 *pu8_SpareBuf) ++{ ++ U32 u32Ret = 0; ++ U8 u8Addr = 0; ++ U8 u8WbufIndex = 0; ++ S8 s8Index = 0; ++ U16 u16DataSize = 0; ++ U8 u8Status = 0; ++ U16 u16ColumnAddr = 0; ++ ++ //calculate write data size ++ u16DataSize = SPARE_SIZE + PAGE_SIZE; ++ ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_DEBUG, printk("addr %lx u8Data %x u32PageIndex %lx\r\n", (U32)u8Data, *u8Data, u32_PageIdx)); ++ u32Ret = HAL_SPINAND_WriteProtect(FALSE); ++ ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ return u32Ret; ++#if 0 ++#ifdef CONFIG_AUTO_DETECT_WRITE ++ HAL_SPINAND_SetMode((SPINAND_MODE)WRITE_MODE); ++#else ++ //HAL_SPINAND_SetMode(gNandReadMode); ++ //HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE); ++#endif ++#endif ++ if (PLANE && (((u32_PageIdx / BLOCK_PAGE_SIZE)&0x1) == 1)) ++ u16ColumnAddr = (1<<12); // plane select for MICRON ++ ++//under this condition, Load data would use QPP, which on some SPINAND device, it would require ++//QE bit enabled, but BE bit could be cleared in UBOOT or Quad Read. ++#if defined(CONFIG_NAND_QUAL_WRITE) && !defined(CONFIG_AUTO_DETECT_WRITE) ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE); ++#endif ++ ++ if (BDMA_W_FLAG && (PAGE_SIZE <= 2048)) // outsize bit number is insufficient for 4KB page, force using RIU mode ++ { ++ memcpy(ALLOC_DMEM.bdma_vir_addr, u8Data, PAGE_SIZE); ++ memcpy(ALLOC_DMEM.bdma_vir_addr+PAGE_SIZE, pu8_SpareBuf, SPARE_SIZE); ++ Chip_Flush_MIU_Pipe(); ++#if defined (CONFIG_NAND_QUAL_WRITE) ++ u32Ret = HAL_SPINAND_PROGRAM_BY_BDMA4(u16ColumnAddr, u16DataSize); ++#else ++ u32Ret = HAL_SPINAND_PROGRAM_BY_BDMA(u16ColumnAddr, u16DataSize); ++#endif ++ } ++ else { ++ u32Ret = HAL_SPINAND_PROGRAM_LOAD_DATA(u16ColumnAddr, u16DataSize, u8Data, pu8_SpareBuf); ++ } ++ if (u32Ret != ERR_SPINAND_SUCCESS) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"PAGE LOAD FAIL %lx \r\n",u32Ret)); ++ return u32Ret; ++ } ++ ++#ifdef CONFIG_NAND_QUAL_WRITE ++ HAL_SPINAND_PreHandle(E_SPINAND_SINGLE_MODE); ++#endif ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ // FIRST COMMAND PAGE PROGRAM EXECUTE ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex), SPI_NAND_CMD_PE); ++ u8WbufIndex++; ++ ++ //set Write Start Address ++ for (s8Index = (SPI_NAND_ADDR_LEN - 1); s8Index >= 0 ; s8Index--) ++ { ++ u8Addr = (u32_PageIdx >> (8 * s8Index) )& 0xFF; ++ FSP_WRITE_BYTE((REG_FSP_WRITE_BUFF + u8WbufIndex),u8Addr); ++ u8WbufIndex++; ++ } ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 0x004); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0x000); ++ //Trigger FSP ++ FSP_WRITE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ u32Ret = _HAL_FSP_CHECK_SPINAND_DONE(&u8Status); ++ ++ if (u32Ret == ERR_SPINAND_SUCCESS) ++ { ++ if (u8Status & P_FAIL) ++ { ++ u32Ret = ERR_SPINAND_W_FAIL; ++ spi_nand_err("P_FAIL!!!\n"); ++ return u32Ret; ++ } ++ } ++ u32Ret = HAL_SPINAND_WriteProtect(TRUE); ++ ++ return u32Ret; ++} ++ ++U32 HAL_SPINAND_Read (U32 u32Addr, U32 u32DataSize, U8 *pu8Data) ++{ ++ U16 u16Addr = u32Addr & 0xFFFF; ++ U32 ret = ERR_SPINAND_SUCCESS; ++ ++ if (RIU_FLAG) ++ { ++ ret = HAL_SPINAND_RIU_READ(u16Addr, u32DataSize, pu8Data); ++ } ++ else if(BDMA_FLAG) ++ { ++ // config SPI waveform for BDMA ++ if (0) //pSpiNandDrv->tSpinandInfo.u8PlaneCnt ++ { ++ QSPI_WRITE(REG_SPI_FUNC_SET, (REG_SPI_ADDR2_EN|REG_SPI_DUMMY_EN|REG_SPI_WRAP_EN)); ++ } ++ else ++ { ++ QSPI_WRITE(REG_SPI_FUNC_SET, (REG_SPI_ADDR2_EN|REG_SPI_DUMMY_EN)); ++ } ++ //Set dummy cycle ++ //QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGAL); ++// _HAL_SPINAND_BDMA_INIT(u32DataSize); ++ ret = _HAL_SPINAND_BDMA_READ(u16Addr, u32DataSize, pu8Data); ++ } ++ else if(XIP_FLAG) ++ { ++ if (0) //pSpiNandDrv->tSpinandInfo.u8PlaneCnt ++ { ++ QSPI_WRITE(REG_SPI_FUNC_SET, (REG_SPI_ADDR2_EN|REG_SPI_DUMMY_EN|REG_SPI_WRAP_EN)); ++ } ++ else ++ { ++ QSPI_WRITE(REG_SPI_FUNC_SET, (REG_SPI_ADDR2_EN|REG_SPI_DUMMY_EN)); ++ } ++ ++ if(!BASE_SPI_OFFSET) ++ { ++ if (!PAGE_SIZE) ++ BASE_SPI_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 2048+16); ++ ++ BASE_SPI_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, PAGE_SIZE+SPARE_SIZE); ++ } ++ if(BASE_SPI_OFFSET) ++ { ++// Chip_Clean_Cache_Range_VA_PA((u32)pu8Data, __pa((u32)pu8Data), u32DataSize); ++// Chip_Inv_Cache_Range((u32)pu8Data, u32DataSize); ++ memcpy((void *)pu8Data, (const void *)(BASE_SPI_OFFSET)+u16Addr , u32DataSize); ++ } ++ ++ if (ret != ERR_SPINAND_SUCCESS) ++ { ++ printk(KERN_ERR"R Wait BDMA Done Time Out CLK!!!!\r\n"); ++ ++ } ++ } ++ return ret; ++} ++ ++U32 HAL_SPINAND_ReadID(U32 u32DataSize, U8 *pu8Data) ++{ ++ U16 u16Index =0; ++ U32 u32RealLength = 0; ++ ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_RDID); ++ //Set Start Address ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + 1, 0x00); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ ++ //Set Write & Read Length ++ for (u16Index = 0; u16Index < u32DataSize; u16Index += u32RealLength) ++ { ++ if (u32DataSize > (MAX_READ_BUF_CNT)) ++ { ++ FSP_WRITE(REG_FSP_READ_SIZE, MAX_READ_BUF_CNT); ++ u32RealLength = MAX_READ_BUF_CNT; ++ } ++ else ++ { ++ FSP_WRITE(REG_FSP_READ_SIZE, u32DataSize); ++ u32RealLength = u32DataSize; ++ } ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"RID Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ //Get Read Data ++ _HAL_FSP_GetRData((pu8Data + u16Index), u32RealLength); ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ } ++ return ERR_SPINAND_SUCCESS; ++ ++} ++ ++U32 HAL_SPINAND_WriteProtect(BOOL bEnable) ++{ ++ U8 u8WbufIndex = 0; ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_SF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, SPI_NAND_REG_PROT); ++ u8WbufIndex++; ++ if (bEnable) ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex,0x38); //all locked(default) ++ else ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex,0x00); //all unlocked ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 3); ++ // read buffer size ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk(KERN_ERR"WP Wait FSP Done Time Out !!!!\r\n")); ++ return ERR_SPINAND_TIMEOUT; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return ERR_SPINAND_SUCCESS; ++} ++ ++U32 HAL_SPINAND_SetMode(SPINAND_MODE eMode) ++{ ++ switch (eMode) ++ { ++ case E_SPINAND_SINGLE_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_SINGLE_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_NORMAL_MODE); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_IS_GPIO, PM_SPI_WP_GPIO_MASK); ++ break; ++ case E_SPINAND_FAST_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_FAST_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_FAST_READ); ++ break; ++ case E_SPINAND_DUAL_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_DUAL_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_3B); ++ break; ++ case E_SPINAND_DUAL_MODE_IO: ++ HAL_SPINAND_PreHandle(E_SPINAND_DUAL_MODE_IO); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_DUAL); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_BB); ++ break; ++ case E_SPINAND_QUAD_MODE: ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_SINGLE); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_6B); ++ break; ++ case E_SPINAND_QUAD_MODE_IO: ++ HAL_SPINAND_PreHandle(E_SPINAND_QUAD_MODE_IO); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ QSPI_WRITE(REG_SPI_CKG_SPI, REG_SPI_USER_DUMMY_EN|REG_SPI_DUMMY_CYC_QUAD); ++ //QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_6B); ++ QSPI_WRITE(REG_SPI_MODE_SEL, REG_SPI_CMD_EB); ++ break; ++ } ++ return ERR_SPINAND_SUCCESS; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SPINAND_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_SPINAND_SetCKG(U8 u8CkgSpi) ++{ ++ BOOL Ret = FALSE; ++ U8 u8nonPmIdx = 0, u8PmIdx = 0; ++ U8 u8Idx = 0; ++ U8 u8Size = 0; ++ u8Size = sizeof(_hal_ckg_spi_nonpm)/ sizeof(hal_clk_ckg_t); ++ //DEBUG_SPINAND(E_SPINAND_DBGLV_INFO, printk("%s()\n", __FUNCTION__)); ++ for (u8Idx = 0; u8Idx < u8Size; u8Idx++) ++ { ++ if (u8CkgSpi < _hal_ckg_spi_nonpm[u8Idx].u8Clk) ++ { ++ if (u8Idx) ++ u8nonPmIdx = u8Idx - 1; ++ else ++ u8nonPmIdx = u8Idx; ++ break; ++ } ++ else ++ u8nonPmIdx = u8Idx; ++ } ++ ++ u8Size = sizeof(_hal_ckg_spi_pm)/ sizeof(hal_clk_ckg_t); ++ for (u8Idx = 0; u8Idx < u8Size; u8Idx++) ++ { ++ if (u8CkgSpi < _hal_ckg_spi_pm[u8Idx].u8Clk) ++ { ++ if (u8Idx) ++ u8PmIdx = u8Idx - 1; ++ else ++ u8PmIdx = u8Idx; ++ break; ++ } ++ else ++ u8PmIdx = u8Idx; ++ } ++ ++ if (_hal_ckg_spi_nonpm[u8nonPmIdx].eClkCkg == NULL || _hal_ckg_spi_pm[u8PmIdx].eClkCkg == NULL) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("CLOCK NOT SUPPORT \n")); ++ return Ret; ++ } ++ ++ // NON-PM Doman ++ CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); ++ CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CKG_SPI_108MHZ,CLK0_CKG_SPI_MASK); // set ckg_spi ++ CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++ ++ // PM Doman ++ PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++ PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[u8PmIdx].eClkCkg,PM_SPI_CLK_SEL_MASK); // set ckg_spi ++ PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++ Ret = TRUE; ++ return Ret; ++} ++ ++void HAL_SPINAND_CSCONFIG(void) ++{ ++ U16 u16Data = 0; ++ u16Data = CHIP_READ(REG_CHIPTOP_DUMMY3); ++ u16Data |= CHIP_CS_PAD1; ++ CHIP_WRITE(REG_CHIPTOP_DUMMY3, u16Data); ++} ++ ++BOOL HAL_SPINAND_IsActive(void) ++{ ++// U16 u16Reg; ++ // Chiptop, offset 0x04, bit 4 : spi nand mode ++// u16Reg = CHIP_READ(0x04); ++// if (u16Reg&0x10) ++ return 1; ++// else ++// return 0; ++} ++ ++U8 HAL_SPINAND_ReadStatusRegister(U8 *u8Status, U8 u8Addr) ++{ ++ U8 u8WbufIndex = 0; ++ ++ HAL_SPINAND_AssertNormalMode(); ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_GF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, u8Addr); ++ u8WbufIndex++; ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 2); ++ ++ FSP_WRITE(REG_FSP_READ_SIZE, 1); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("WP Wait FSP Done Time Out !!!!\r\n")); ++ return FALSE; ++ } ++ _HAL_FSP_GetRData((u8Status), 1); ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ ++ return ERR_SPINAND_SUCCESS; ++} ++ ++U8 HAL_SPINAND_WriteStatusRegister(U8 *u8Status, U8 u8Addr) ++{ ++ U8 u8WbufIndex = 0; ++ ++ HAL_SPINAND_AssertNormalMode(); ++ //FSP init config ++ FSP_WRITE(REG_FSP_CTRL, (ENABLE_FSP|RESET_FSP|INT_FSP)); ++ FSP_WRITE(REG_FSP_CTRL2, 0); ++ FSP_WRITE(REG_FSP_CTRL4, 0); ++ ++ //Set FSP Read Command ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF, SPI_NAND_CMD_SF); ++ u8WbufIndex++; ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, u8Addr); ++ u8WbufIndex++; ++ ++ FSP_WRITE_BYTE(REG_FSP_WRITE_BUFF + u8WbufIndex, *u8Status); ++ ++ FSP_WRITE(REG_FSP_WRITE_SIZE, 3); ++ FSP_WRITE(REG_FSP_READ_SIZE, 0); ++ ++ //Trigger FSP ++ FSP_WRITE_BYTE(REG_FSP_TRIGGER, TRIGGER_FSP); ++ ++ //Check FSP done flag ++ if (_HAL_FSP_ChkWaitDone() == FALSE) ++ { ++ DEBUG_SPINAND(E_SPINAND_DBGLV_ERR, printk("WP Wait FSP Done Time Out !!!!\r\n")); ++ return FALSE; ++ } ++ ++ //Clear FSP done flag ++ FSP_WRITE_BYTE(REG_FSP_CLEAR_DONE, CLEAR_DONE_FSP); ++ return TRUE; ++} ++ ++U8 HAL_QSPI_FOR_DEBUG(void) ++{ ++ return ((U8)(PM_READ(0x34))); ++} +diff --git a/drivers/sstar/swtoe/Kconfig b/drivers/sstar/swtoe/Kconfig +new file mode 100755 +index 000000000000..635a9725ec81 +--- /dev/null ++++ b/drivers/sstar/swtoe/Kconfig +@@ -0,0 +1,16 @@ ++config SS_SWTOE ++select NET ++select NET_ETHERNET ++select MII ++select PACKET ++select USE_POLICY_FWD ++select INET ++select NETDEVICES ++select MS_EMAC_TOE ++ ++tristate "SWTOE" ++default n ++ ++---help--- ++Enable compilation option for driver SSTAR SW TOE ++ +diff --git a/drivers/sstar/swtoe/Makefile b/drivers/sstar/swtoe/Makefile +new file mode 100755 +index 000000000000..b5e145a7182d +--- /dev/null ++++ b/drivers/sstar/swtoe/Makefile +@@ -0,0 +1,21 @@ ++# ++# Makefile for MStar EMAC device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/swtoe ++EXTRA_CFLAGS += -Iinclude/linux ++ ++# specific options ++# EXTRA_CFLAGS += -DRED_LION ++# files ++obj-$(CONFIG_SS_SWTOE) := kdrv_swtoe.o ++kdrv_swtoe-y := mdrv_swtoe.o ++kdrv_swtoe-y += mdrv_swtoe_cb.o ++kdrv_swtoe-y += mdrv_swtoe_rxq.o ++kdrv_swtoe-y += mdrv_swtoe_txq.o ++kdrv_swtoe-y += mdrv_swtoe_prot.o +diff --git a/drivers/sstar/swtoe/mdrv_swtoe.c b/drivers/sstar/swtoe/mdrv_swtoe.c +new file mode 100755 +index 000000000000..6384873d6b7f +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe.c +@@ -0,0 +1,149 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#if 0 ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#else ++#include ++#include ++#include ++#include ++#include ++#include "drv_dualos.h" ++#include "mdrv_swtoe.h" ++#include "mdrv_swtoe_intl.h" ++#endif ++ ++#define IPC_TEST_THREAD 0 ++ ++#if IPC_TEST_THREAD ++static int swtoe_ipc_test_thread(void *arg) ++{ ++ int cnt = 0; ++ int ret; ++ ++ while (1) ++ { ++ msleep(5000); ++ { ++ { ++ char* p = (char*) 0xc2e45000; ++ printk(" %02x %02x %02x %02x %02x %02x %02x %02x\n", ++ p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); ++ } ++ } ++ // printk("[%s][%d] ipc start\n", __FUNCTION__, __LINE__); ++ ret = signal_rtos(0x11000000, cnt, cnt+1, cnt+2); ++ // printk("[%s][%d] ipc end. %d\n", __FUNCTION__, __LINE__, ret); ++ cnt++; ++ } ++ return 0; ++} ++#endif ++ ++static int sstar_swtoe_drv_probe(struct platform_device *pdev) ++{ ++ drv_swtoe_cnx_rxq_create(0); // @FIXME : service id has to be refined ++#if IPC_TEST_THREAD ++ kthread_run(swtoe_ipc_test_thread, NULL, "ipc_test_thread"); ++#endif ++ return 0; ++} ++ ++static int sstar_swtoe_drv_remove(struct platform_device *pdev) ++{ ++ platform_set_drvdata(pdev, NULL); ++ return 0; ++} ++ ++static int sstar_swtoe_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int sstar_swtoe_drv_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#if defined (CONFIG_OF) ++static struct of_device_id sstar_swtoe_of_device_ids[] = { ++ {.compatible = "sstar-swtoe"}, ++ {}, ++}; ++#endif ++ ++static struct platform_driver Sstar_swtoe_driver = { ++ .probe = sstar_swtoe_drv_probe, ++ .remove = sstar_swtoe_drv_remove, ++ .suspend = sstar_swtoe_drv_suspend, ++ .resume = sstar_swtoe_drv_resume, ++ ++ .driver = { ++ .name = "Sstar-swtoe", ++#if defined(CONFIG_OF) ++ .of_match_table = sstar_swtoe_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init sstar_swtoe_drv_init_module(void) ++{ ++ int retval=0; ++ ++ drv_swtoe_glue_init(); ++ ++ retval = platform_driver_register(&Sstar_swtoe_driver); ++ if (retval) ++ { ++ printk(KERN_INFO "Sstar_swtoe_driver register failed...\n"); ++ return retval; ++ } ++ ++ return retval; ++} ++ ++static void __exit sstar_swtoe_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Sstar_swtoe_driver); ++} ++ ++module_init(sstar_swtoe_drv_init_module); ++module_exit(sstar_swtoe_drv_exit_module); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("SW TOE driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/swtoe/mdrv_swtoe_cb.c b/drivers/sstar/swtoe/mdrv_swtoe_cb.c +new file mode 100755 +index 000000000000..8fc0dba30077 +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe_cb.c +@@ -0,0 +1,503 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe_cb.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mstar_chip.h" ++#include "drv_dualos.h" ++#include "mdrv_swtoe.h" ++#include "mdrv_swtoe_intl.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Data structure definition ++//-------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 saddr; ++ u32 daddr; ++ u16 sport; ++ u16 dport; ++ u32 blk : 1; ++ u32 status : 1; ++ u32 reserved : 30; ++} __attribute__ ((packed)) sstoe_prot_cnx_resp_t; ++ ++typedef struct ++{ ++ u32 prot_cmd; ++ u32 cnx_id : 11; ++ u32 reserved : 21; ++ union ++ { ++ sstoe_prot_cnx_resp_t cnx_resp; ++ } u; ++} __attribute__ ((packed)) sstoe_prot_info_t; ++ ++typedef struct ++{ ++ struct list_head list; ++ sstoe_prot_info_t prot_info; ++} _ipcq_data_t; ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++static int _drv_swtoe_glue_ctrl_alloc(void); ++ ++// static void swtoe_work_func(unsigned long data); ++static void swtoe_work_func(struct work_struct *work); ++ ++//-------------------------------------------------------------------------------------------------- ++// Data definition ++//-------------------------------------------------------------------------------------------------- ++static struct work_struct swtoe_work; ++static DEFINE_SPINLOCK(mutex_L2R); ++static DEFINE_SPINLOCK(mutex_R2L); ++ ++// RXQ ++#define R2L_SIGNAL_RCOM 0 ++#define R2L_SIGNAL_TCOM 1 ++static unsigned long r2l_signal = 0; /// @FIXME: refine this one ++static unsigned long _cnx_signal_r2l[LONG_DIV(MAX_CNX_TXQ_NUM)] = { 0 }; ++ ++ ++#define L2R_SIGNAL_XMIT 0 ++static unsigned long l2r_signal = 0; /// @FIXME: refine this one ++static unsigned long _cnx_signal_l2r[LONG_DIV(MAX_CNX_TXQ_NUM)] = { 0 }; ++static unsigned long _cnx_signal_wq[LONG_DIV(MAX_CNX_TXQ_NUM)] = { 0 }; ++ ++// IPC control ++sstoe_ipc_ctrl_t* g_pIpcInfo = NULL; ++static dma_addr_t _ipc_ctrl_phys = 0; ++ ++// connection information ++static sstoe_cnx_info cnx_info[MAX_CNX_TXQ_NUM] = { 0 }; ++sstoe_cnx_info* g_pCnxInfo = cnx_info; ++ ++// ipc command queue from RTK to Linux ++static struct list_head _ipcq_r2l; ++ ++/// @FIXME : end : collect these data structure into one ++ ++//-------------------------------------------------------------------------------------------------- ++// Implementation ++//-------------------------------------------------------------------------------------------------- ++int drv_swtoe_glue_init(void) ++{ ++ int ret = 0; ++ ++ if ((ret = _drv_swtoe_glue_ctrl_alloc())) ++ { ++ return ret; ++ } ++ INIT_WORK(&swtoe_work, swtoe_work_func); ++ INIT_LIST_HEAD(&_ipcq_r2l); ++ return 0; ++} ++ ++int drv_swtoe_glue_req(int cnx_id, drv_swtoe_cb_func_t cb, void* cb_data) ++{ ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ CNX_SANITY(cnx_id); ++ pCNX->cb_func = cb; ++ pCNX->cb_data = cb_data; ++ ++ return 0; ++} ++ ++int drv_swtoe_glue_en(int cnx_id, int mask, int bEn) ++{ ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ CNX_SANITY(cnx_id); ++ /// @FIXME : to be refined ++ pCNX->cb_mask = (bEn) ? SET_FLAGS(pCNX->cb_mask, mask) : CLR_FLAGS(pCNX->cb_mask, mask); ++ return 0; ++} ++ ++int drv_swtoe_glue_invoke(u32 arg1, u32 arg2, u32 arg3) ++{ ++ unsigned long flag; ++ ++ spin_lock_irqsave(&mutex_L2R, flag); ++ switch (arg1) ++ { ++ case SWTOE_IPC_ARG1_TXQ_PUT: ++ // txq_signal[arg2 >> 5] |= (1 << (arg2 & 0x1f)); ++ SET_BITS_POS(_cnx_signal_l2r, arg2); ++ SET_BITS(l2r_signal, L2R_SIGNAL_XMIT); ++ break; ++ } ++ spin_unlock_irqrestore(&mutex_L2R, flag); ++ schedule_work(&swtoe_work); ++ return 0; ++} ++ ++static _ipcq_data_t* _drv_swtoe_cb_hdl_cnx_resp(u32 arg2, u32 arg3) ++{ ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int cnx_id = (int) arg2 & 0xFFFF; ++ _ipcq_data_t* pqdata = NULL; ++ ++ CNX_SANITY(cnx_id); ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ if (NULL == (pqdata = kmalloc(sizeof(_ipcq_data_t), GFP_ATOMIC))) ++ { ++ printk("[%s][%d] kmalloc %d bytes fail\n", __FUNCTION__, __LINE__, sizeof(_ipcq_data_t)); ++ return NULL; ++ } ++ if (pTXQ_IPC->cnx_info.status) ++ { ++ pqdata->prot_info.prot_cmd = DRV_SWTOE_GLUE_CNX_FAIL; ++ pqdata->prot_info.cnx_id = cnx_id; ++ } ++ else ++ { ++ pqdata->prot_info.prot_cmd = DRV_SWTOE_GLUE_CNX_OK; ++ pqdata->prot_info.cnx_id = cnx_id; ++ pqdata->prot_info.u.cnx_resp.saddr = htonl(pTXQ_IPC->cnx_info.saddr); ++ pqdata->prot_info.u.cnx_resp.daddr = htonl(pTXQ_IPC->cnx_info.daddr); ++ pqdata->prot_info.u.cnx_resp.sport = htons(pTXQ_IPC->cnx_info.sport); ++ pqdata->prot_info.u.cnx_resp.dport = htons(pTXQ_IPC->cnx_info.dport); ++ pqdata->prot_info.u.cnx_resp.blk = pTXQ_IPC->cnx_info.blk; ++ pqdata->prot_info.u.cnx_resp.status = pTXQ_IPC->cnx_info.status; ++ } ++ return pqdata; ++} ++ ++static _ipcq_data_t* _drv_swtoe_cb_hdl_cls_resp(u32 arg2, u32 arg3) ++{ ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int cnx_id = (int) arg2 & 0xFFFF; ++ _ipcq_data_t* pqdata = NULL; ++ ++ CNX_SANITY(cnx_id); ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ if (NULL == (pqdata = kmalloc(sizeof(_ipcq_data_t), GFP_ATOMIC))) ++ { ++ printk("[%s][%d] kmalloc %d bytes fail\n", __FUNCTION__, __LINE__, sizeof(_ipcq_data_t)); ++ return NULL; ++ } ++ pqdata->prot_info.prot_cmd = DRV_SWTOE_GLUE_CLS_RESP; ++ pqdata->prot_info.cnx_id = cnx_id; ++ return pqdata; ++} ++ ++static void _drv_swtoe_cb_hdl_bind_resp(u32 arg2, u32 arg3) ++{ ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int cnx_id = (int) arg2 & 0xFFFF; ++ sstoe_cnx_info* pCNX = NULL; ++ ++ CNX_SANITY(cnx_id); ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ pCNX = &g_pCnxInfo[cnx_id]; ++ pCNX->bind_ready = (0x80 | pTXQ_IPC->cnx_info.status); ++} ++ ++static _ipcq_data_t* _drv_swtoe_cb_hdl_lstn_resp(u32 arg2, u32 arg3) ++{ ++ int cnx_id = (int) arg2 & 0xFFFF; ++ _ipcq_data_t* pqdata = NULL; ++ ++ CNX_SANITY(cnx_id); ++ drv_swtoe_lstn_resp(cnx_id); ++ ++ if (NULL == (pqdata = kmalloc(sizeof(_ipcq_data_t), GFP_ATOMIC))) ++ { ++ printk("[%s][%d] kmalloc %d bytes fail\n", __FUNCTION__, __LINE__, sizeof(_ipcq_data_t)); ++ return NULL; ++ } ++ pqdata->prot_info.prot_cmd = DRV_SWTOE_GLUE_LSTN_RESP; ++ pqdata->prot_info.cnx_id = cnx_id; ++ return pqdata; ++} ++ ++int drv_swtoe_cb_hdl(u32 arg0, u32 arg1, u32 arg2, u32 arg3) ++{ ++ char bWakeUp = 1; ++ unsigned long flag; ++ _ipcq_data_t* pqdata = NULL; ++ int cnx_id = 0; ++ ++ if (SWTOE_IPC_ARG0 != arg0) ++ { ++ printk("[%s][%d] invalid IPC CMD from RTK (arg0, arg1, arg2, arg3) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, (int)arg0, (int)arg1, (int)arg2, (int)arg3); ++ return -1; ++ } ++ ++ switch (arg1) ++ { ++ case SWTOE_IPC_ARG1_TXQ_GET: ++ spin_lock_irqsave(&mutex_R2L, flag); ++ SET_BITS_POS(_cnx_signal_r2l, arg2); ++ SET_BITS(r2l_signal, R2L_SIGNAL_TCOM); ++ TX_MEM_IPC_FREE_INC(); ++ spin_unlock_irqrestore(&mutex_R2L, flag); ++ break; ++ case SWTOE_IPC_ARG1_RXQ_GET: ++ cnx_id = arg2 & 0x0000FFFF; ++ // @FIXME : only trigger connection 0 for bypassing mode at this stage ++ spin_lock_irqsave(&mutex_R2L, flag); ++ SET_BITS(r2l_signal, R2L_SIGNAL_RCOM); ++ spin_unlock_irqrestore(&mutex_R2L, flag); ++ break; ++ case SWTOE_IPC_ARG1_PROT_CNX_RESP: ++ pqdata = _drv_swtoe_cb_hdl_cnx_resp(arg2, arg3); ++ break; ++ case SWTOE_IPC_ARG1_PROT_BIND_RESP: ++ _drv_swtoe_cb_hdl_bind_resp(arg2, arg3); ++ break; ++ case SWTOE_IPC_ARG1_PROT_LSTN_RESP: ++ pqdata = _drv_swtoe_cb_hdl_lstn_resp(arg2, arg3); ++ break; ++ case SWTOE_IPC_ARG1_PROT_CLS_RESP: ++ pqdata = _drv_swtoe_cb_hdl_cls_resp(arg2, arg3); ++ break; ++ default: ++ printk("[%s][%d] invalid IPC CMD from RTK (arg0, arg1, arg2, arg3) = (0x%08x, 0x%08x, 0x%08x, 0x%08x)\n", __FUNCTION__, __LINE__, (int)arg0, (int)arg1, (int)arg2, (int)arg3); ++ bWakeUp = 0; ++ break; ++ } ++ if (pqdata) ++ { ++ spin_lock_irqsave(&mutex_R2L, flag); ++ list_add_tail(&pqdata->list, &_ipcq_r2l); ++ spin_unlock_irqrestore(&mutex_R2L, flag); ++ } ++ ++ if (bWakeUp) ++ { ++ schedule_work(&swtoe_work); ++ } ++ return 0; ++} ++ ++static void _swtoe_work_func_prot_cnx_resp(_ipcq_data_t* pqdata) ++{ ++ drv_swtoe_glue_cnx_data cnx_data; ++ int cnx_id = pqdata->prot_info.cnx_id; ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ if (DRV_SWTOE_GLUE_CNX_FAIL == pqdata->prot_info.prot_cmd) ++ { ++ (pCNX->cb_func)(cnx_id, DRV_SWTOE_GLUE_CNX_FAIL, NULL, pCNX->cb_data); ++ return; ++ } ++ ++ cnx_data.saddr = pqdata->prot_info.u.cnx_resp.saddr; ++ cnx_data.daddr = pqdata->prot_info.u.cnx_resp.daddr; ++ cnx_data.sport = pqdata->prot_info.u.cnx_resp.sport; ++ cnx_data.dport = pqdata->prot_info.u.cnx_resp.dport; ++ cnx_data.blk = pqdata->prot_info.u.cnx_resp.blk; ++ (pCNX->cb_func)(cnx_id, DRV_SWTOE_GLUE_CNX_OK, (void*)&cnx_data, pCNX->cb_data); ++} ++ ++static void _swtoe_work_func_prot_cls_resp(_ipcq_data_t* pqdata) ++{ ++ int cnx_id = pqdata->prot_info.cnx_id; ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ drv_swtoe_cnx_txq_free(cnx_id); ++ (pCNX->cb_func)(cnx_id, DRV_SWTOE_GLUE_CLS_RESP, NULL, pCNX->cb_data); ++ drv_swtoe_cnx_txq_free(cnx_id); ++} ++ ++static void _swtoe_work_func_prot_lstn_resp(_ipcq_data_t* pqdata) ++{ ++ int cnx_id = pqdata->prot_info.cnx_id; ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ drv_swtoe_glue_cnx_data lstn_data; ++ ++ lstn_data.saddr = pqdata->prot_info.u.cnx_resp.saddr; ++ lstn_data.daddr = pqdata->prot_info.u.cnx_resp.daddr; ++ lstn_data.sport = pqdata->prot_info.u.cnx_resp.sport; ++ lstn_data.dport = pqdata->prot_info.u.cnx_resp.dport; ++ (pCNX->cb_func)(cnx_id, DRV_SWTOE_GLUE_LSTN_RESP, (void*)&lstn_data, pCNX->cb_data); ++} ++ ++static void _swtoe_work_func_prot(void) ++{ ++ _ipcq_data_t* pqdata = NULL; ++ struct list_head *p_list, *p_list_tmp; ++ // unsigned long flag; ++ ++ // @FIXME : spinlock is temporarily removed since listen response, however ... ++ // spin_lock_irqsave(&mutex_R2L, flag); ++ if (list_empty(&_ipcq_r2l)) ++ { ++ // spin_unlock_irqrestore(&mutex_R2L, flag); ++ return; ++ } ++ ++ list_for_each_safe(p_list, p_list_tmp, &_ipcq_r2l) ++ { ++ pqdata = list_entry(p_list, _ipcq_data_t, list); ++ switch (pqdata->prot_info.prot_cmd) ++ { ++ case DRV_SWTOE_GLUE_CNX_OK: ++ case DRV_SWTOE_GLUE_CNX_FAIL: ++ _swtoe_work_func_prot_cnx_resp(pqdata); ++ break; ++ case DRV_SWTOE_GLUE_CLS_RESP: ++ _swtoe_work_func_prot_cls_resp(pqdata); ++ break; ++ case DRV_SWTOE_GLUE_LSTN_RESP: ++ _swtoe_work_func_prot_lstn_resp(pqdata); ++ break; ++ default: ++ printk("[%s][%d] invalid protocol CMD 0x%08x\n", __FUNCTION__, __LINE__, (int)pqdata->prot_info.prot_cmd); ++ break; ++ } ++ list_del(&pqdata->list); ++ kfree(pqdata); ++ } ++ // spin_unlock_irqrestore(&mutex_R2L, flag); ++} ++ ++static void swtoe_work_func_xmit(unsigned long* cnx_signal) ++{ ++ int i; ++ unsigned long* p; ++ long base, pos; ++ int cnx_id; ++ ++ for (i = 0; i < LONG_DIV(MAX_CNX_TXQ_NUM); i++) ++ { ++ p = &cnx_signal[i]; ++ base = LONG_MULT(i); ++ pos = -1; ++ do ++ { ++ pos = find_next_bit(p, BITS_PER_LONG, pos+1); ++ if (BITS_PER_LONG == pos) ++ { ++ *p = 0; ++ break; ++ } ++ cnx_id = base + pos; ++ /// if ((HAS_BITS(pCNX->cb_mask, DRV_SWTOE_CB_RCOM)) && (pCNX->cb_func)) ++ if (1) ++ { ++ signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_TXQ_PUT, cnx_id & 0xFFFF, 0); ++ } ++ } while (pos < BITS_PER_LONG); ++ } ++} ++ ++static void swtoe_work_func_tcom(unsigned long* cnx_signal) ++{ ++ int i; ++ unsigned long* p; ++ long base, pos; ++ int cnx_id; ++ ++ for (i = 0; i < LONG_DIV(MAX_CNX_TXQ_NUM); i++) ++ { ++ p = &cnx_signal[i]; ++ base = LONG_MULT(i); ++ pos = -1; ++ do ++ { ++ pos = find_next_bit(p, BITS_PER_LONG, pos+1); ++ if (BITS_PER_LONG == pos) ++ { ++ *p = 0; ++ break; ++ } ++ cnx_id = base + pos; ++ drv_swtoe_tx_consume(cnx_id); ++ } while (pos < BITS_PER_LONG); ++ } ++ return; ++} ++ ++static void swtoe_work_func(struct work_struct *work) ++{ ++ unsigned long flag; ++ int bTCOM, bRCOM, bXMIT; ++ ++ /// protocol part (RTK to Linux) ++ _swtoe_work_func_prot(); ++ ++ /// Linux to RTK ++ spin_lock_irqsave(&mutex_L2R, flag); ++ bXMIT = HAS_BITS(l2r_signal, L2R_SIGNAL_XMIT); ++ if (bXMIT) ++ { ++ memcpy(_cnx_signal_wq, _cnx_signal_l2r, sizeof(_cnx_signal_l2r)); ++ memset(_cnx_signal_l2r, 0, sizeof(_cnx_signal_l2r)); ++ } ++ l2r_signal = 0; ++ spin_unlock_irqrestore(&mutex_L2R, flag); ++ if (bXMIT) ++ { ++ swtoe_work_func_xmit(_cnx_signal_wq); ++ } ++ ++ /// RTK to Linux ++ spin_lock_irqsave(&mutex_R2L, flag); ++ bRCOM = HAS_BITS(r2l_signal, R2L_SIGNAL_RCOM); ++ bTCOM = HAS_BITS(r2l_signal, R2L_SIGNAL_TCOM); ++ if (bTCOM) ++ { ++ memcpy(_cnx_signal_wq, _cnx_signal_r2l, sizeof(_cnx_signal_r2l)); ++ memset(_cnx_signal_r2l, 0, sizeof(_cnx_signal_r2l)); ++ } ++ r2l_signal = 0; ++ spin_unlock_irqrestore(&mutex_R2L, flag); ++ ++ if (bRCOM) ++ { ++ drv_swtoe_rx_data_put(); ++ } ++ if (bTCOM) ++ { ++ swtoe_work_func_tcom(_cnx_signal_wq); ++ } ++} ++ ++int _drv_swtoe_glue_ctrl_alloc(void) ++{ ++ if (g_pIpcInfo) ++ { ++ printk("[%s][%d] IPC control has been allocated\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ ++ if (NULL == (g_pIpcInfo = (sstoe_ipc_ctrl_t*) dma_alloc_coherent(NULL, sizeof(sstoe_ipc_ctrl_t), &_ipc_ctrl_phys, GFP_KERNEL))) ++ { ++ printk("[%s][%d] IPC control allocate fail\n", __FUNCTION__, __LINE__); ++ return -ENOMEM; ++ } ++ memset(g_pIpcInfo, 0, sizeof(sstoe_ipc_ctrl_t)); ++ signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_CTRL_BUF_ALLOC, PA2BUS(_ipc_ctrl_phys), sizeof(sstoe_ipc_ctrl_t) & 0xFFFF); ++ return 0; ++} ++ +diff --git a/drivers/sstar/swtoe/mdrv_swtoe_intl.h b/drivers/sstar/swtoe/mdrv_swtoe_intl.h +new file mode 100755 +index 000000000000..610ef36f5430 +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe_intl.h +@@ -0,0 +1,239 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe_intl.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MDRV_SWTOE_INTL_H__ ++#define _MDRV_SWTOE_INTL_H__ ++ ++#include "mdrv_swtoe_ipc.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define MAX_RXQ_DEPTH 256 ++#define MAX_RXQ_PKT_SIZE 0x4000 ++ ++#define MAX_TXQ_DEPTH 128 ++#define MAX_TXQ_PKT_SIZE 0x4000 ++#define MAX_TXQ_DATA_SIZE 0x3FF0 ++ ++#define DBG_CNX_SANITY 1 ++#define DBG_CNX 0 ++#define DBG_TX_MEM 0 ++#define DBG_TX_PERF 0 ++ ++//-------------------------------------------------------------------------------------------------- ++// Some helper functions ++//-------------------------------------------------------------------------------------------------- ++#if (BITS_PER_LONG == 32) ++ #define LONG_DIV_SHFT (0x05) ++ #define LONG_MOD_MASK (0x1f) ++#elif (BITS_PER_LONG == 64) ++ #define LONG_DIV_SHFT (0x06) ++ #define LONG_MOD_MASK (0x3f) ++#endif ++ ++#define LONG_DIV(a) ((a) >> LONG_DIV_SHFT) ++#define LONG_MOD(a) ((a) & LONG_MOD_MASK) ++#define LONG_MULT(a) ((a) << LONG_DIV_SHFT) ++ ++#define CLR_BITS(a, pos) clear_bit((pos), &(a)) ++#define SET_BITS(a, pos) set_bit((pos), &(a)) ++#define HAS_BITS(a, pos) test_bit((pos), &(a)) ++ ++#define CLR_BITS_POS(a, pos) clear_bit(LONG_MOD((pos)), &(a)[LONG_DIV((pos))]) ++#define SET_BITS_POS(a, pos) set_bit(LONG_MOD((pos)), &(a)[LONG_DIV((pos))]) ++#define HAS_BITS_POS(a, pos) test_bit(LONG_MOD((pos)), &(a)[LONG_DIV((pos))]) ++ ++#define CLR_FLAGS(a, flags) ((a) & (~(flags))) ++#define SET_FLAGS(a, flags) ((a) | (flags)) ++#define HAS_FLAGS(a, flags) ((a) & (flags)) ++ ++#define PA2BUS(a) CLR_FLAGS(a, MSTAR_MIU0_BUS_BASE) ++#define BUS2PA(a) SET_FLAGS(a, MSTAR_MIU0_BUS_BASE) ++ ++#define BUS2VIRT(a) phys_to_virt(BUS2PA((a))) ++#define VIRT2BUS(a) PA2BUS(virt_to_phys((a))) ++ ++//-------------------------------------------------------------------------------------------------- ++// Data structure definition ++//-------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ /// TX data part ++ sstoe_tx_desc_t* tx_desc; ++ u16 read_lx; ++ void** RTF; /// Resource To Free ++ struct list_head wdata_queue; ++#define MAX_CNX_WDATA_QUEUE_SIZE 8 ++ int wdata_queue_size; ++ ++ /// RX data part ++ struct list_head rdata_queue; /// _msg_queue_rx ++ ++ /// callback function ++ drv_swtoe_cb_func_t cb_func; /// swtoe_cb_func ++ void* cb_data; /// swtoe_cb_data ++ u32 cb_mask; /// swtoe_cb_mask ++ ++ /// binding ++ char bind_ready; ++ ++ /// listen data ++ struct list_head lstn_queue; ++ ++ /// mutex ++ spinlock_t lock; ++ ++} sstoe_cnx_info; ++ ++//-------------------------------------------------------------------------------------------------- ++// global variables ++//-------------------------------------------------------------------------------------------------- ++extern sstoe_ipc_ctrl_t* g_pIpcInfo; ++extern sstoe_cnx_info* g_pCnxInfo; ++ ++#if DBG_TX_MEM ++extern int g_cnt_alloc; ++extern int g_cnt_free; ++extern int g_cnt_ipc_free; ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// malloc helper function ++//-------------------------------------------------------------------------------------------------- ++#define MEM_ALLOC_FRAG 0 ++ ++#if MEM_ALLOC_FRAG ++ #define SWTOE_MALLOC(size) netdev_alloc_frag((size)) ++ #define SWTOE_FREE(p) skb_free_frag((p)) ++#else ++ // #define SWTOE_MALLOC(size) kmalloc((size), GFP_ATOMIC) ++ #define SWTOE_MALLOC(size) kmalloc((size), GFP_KERNEL) ++ #define SWTOE_FREE(p) kfree((p)) ++#endif ++ ++#if LONG_MOD(MAX_CNX_TXQ_NUM) ++#pragma GCC error "MAX_CNX_TXQ_NUM should be mutiple of long" ++#endif ++ ++#if DBG_CNX_SANITY ++#define CNX_SANITY(cnx_id) \ ++{ \ ++ if (MAX_CNX_TXQ_NUM <= (cnx_id)) \ ++ { \ ++ printk("[%s][%d] invalid cnx_id %d\n", __FUNCTION__, __LINE__, (cnx_id)); \ ++ } \ ++ if (0 == g_pIpcInfo->txq_info[(cnx_id)].used) \ ++ { \ ++ printk("[%s][%d] cnx_id = %d is not created\n", __FUNCTION__, __LINE__, (cnx_id)); \ ++ } \ ++} ++#else ++#define CNX_SANITY(cnx_id) {} ++#endif ++ ++#if DBG_CNX ++#define CNX_DUMP(cnx_id) \ ++{ \ ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; \ ++ if (MAX_CNX_TXQ_NUM <= (cnx_id)) \ ++ { \ ++ printk("[%s][%d] invalid cnx_id %d\n", __FUNCTION__, __LINE__, (cnx_id)); \ ++ } \ ++ pTXQ_IPC = &g_pIpcInfo->txq_info[(cnx_id)]; \ ++ printk("[%s][%d] (cnx, used, prot, pkt_size, depth, write, read) = (%d, %d, %d, %d, %d, %d, %d)\n", \ ++ __FUNCTION__, __LINE__, \ ++ (cnx_id), \ ++ pTXQ_IPC->used, pTXQ_IPC->prot, \ ++ pTXQ_IPC->pkt_size, pTXQ_IPC->depth, \ ++ pTXQ_IPC->write, pTXQ_IPC->read); \ ++} ++#else ++#define CNX_DUMP(cnx_id) {} ++#endif ++ ++#if DBG_TX_MEM ++#define TX_MEM_ALLOC_INC() { g_cnt_alloc++; } ++#define TX_MEM_FREE_INC() { g_cnt_free++; } ++#define TX_MEM_IPC_FREE_INC() { g_cnt_ipc_free++; } ++#define TX_MEM_INFO_DUMP() { printk("[%s][%d] TX mem (alloc, free, free_ipc) = (%d, %d, %d)\n", __FUNCTION__, __LINE__, g_cnt_alloc, g_cnt_free, g_cnt_ipc_free); } ++#else ++#define TX_MEM_ALLOC_INC() { } ++#define TX_MEM_FREE_INC() { } ++#define TX_MEM_IPC_FREE_INC() { } ++#define TX_MEM_INFO_DUMP() { } ++#endif ++ ++#if DBG_TX_PERF ++#define CNX_PERF_TXQ_UNDERRUN(cnx_id) \ ++{ \ ++ if (g_pIpcInfo->txq_info[(cnx_id)].read == g_pIpcInfo->txq_info[(cnx_id)].write) \ ++ { \ ++ printk("[%s][%d] TXQ underrun. cnx_id = %d\n", __FUNCTION__, __LINE__, (cnx_id)); \ ++ } \ ++} ++#else ++#define CNX_PERF_TXQ_UNDERRUN(cnx_id) {} ++#endif ++ ++// #define CNX_LOCK(pCNX, flags) spin_lock_irqsave(&(pCNX)->lock, (flags)) ++// #define CNX_UNLOCK(pCNX, flags) spin_unlock_irqrestore(&(pCNX)->lock, (flags)) ++ ++//-------------------------------------------------------------------------------------------------- ++// function declaration ++//-------------------------------------------------------------------------------------------------- ++int drv_swtoe_glue_init(void); ++int drv_swtoe_glue_invoke(u32 arg1, u32 arg2, u32 arg3); ++ ++/// @FIXME : temporarily put it here ++int drv_swtoe_tx_consume(int cnx_id); ++ ++/// rx ++int drv_swtoe_rx_data_put(void); ++ ++/// listen ++int drv_swtoe_lstn_resp(int cnx_id); ++ ++ ++ ++ ++// txq/rxq can be put in private header file ++int drv_swtoe_cnx_txq_create(int prot, int* cnx_id); ++ ++// int drv_swtoe_cnx_txq_put(int cnx_id, struct sk_buff* skb); ++int drv_swtoe_cnx_txq_free(int cnx_id); ++// int drv_swtoe_cnx_txq_avail(int cnx_id, int n); ++// int drv_swtoe_cnx_txq_put(int cnx_id, dma_addr_t addr, int size); ++// int drv_swtoe_cnx_txq_size(int cnx_id); ++// int drv_swtoe_cnx_txq_free(int cnx_id); ++// int drv_swtoe_cnx_txq_used(int cnx_id); ++// int drv_swtoe_cnx_txq_full(int cnx_id); ++// int drv_swtoe_cnx_txq_empty(int cnx_id); ++ ++// int drv_swtoe_cnx_rxq_create(int serv_id); ++// int drv_swtoe_cnx_rxq_close(int cnx_id); ++int drv_swtoe_cnx_rxq_create(int serv_id); ++int drv_swtoe_cnx_rxq_get(int* cnx_id, char** buf, int* buf_size, char** data, int* data_size); ++// int drv_swtoe_cnx_rxq_put(int cnx_id, dma_addr_t addr, int size); ++int drv_swtoe_cnx_rxq_size(int cnx_id); ++int drv_swtoe_cnx_rxq_free(int cnx_id); ++int drv_swtoe_cnx_rxq_used(int cnx_id); ++ ++ ++#endif +diff --git a/drivers/sstar/swtoe/mdrv_swtoe_ipc.h b/drivers/sstar/swtoe/mdrv_swtoe_ipc.h +new file mode 100755 +index 000000000000..b33eba325490 +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe_ipc.h +@@ -0,0 +1,183 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe_ipc.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _MDRV_SWTOE_IPC_H__ ++#define _MDRV_SWTOE_IPC_H__ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define MAX_CNX_TXQ_NUM 2048 ++ ++// IPC ++// arg0 ++#define SWTOE_IPC_ARG0 0xfe000000 ++ ++#define SWTOE_IPC_ARG1_CTRL_BUF_ALLOC 0x01000001 ++#define SWTOE_IPC_ARG1_CTRL_BUF_FREE 0x01000002 /// must but not used at this stage ++// #define SWTOE_IPC_ARG1_STATS_BUF_ALLOC 0x01000003 /// must but not used at this stage ++// #define SWTOE_IPC_ARG1_STATS_BUF_FREE 0x01000004 /// must but not used at this stage ++ ++#define SWTOE_IPC_ARG1_CTRL_TXQ_ALLOC 0x01000005 ++#define SWTOE_IPC_ARG1_CTRL_TXQ_FREE 0x01000006 /// must but not used at this stage ++#define SWTOE_IPC_ARG1_CTRL_RXQ_ALLOC 0x01000007 /// must but not used at this stage ++#define SWTOE_IPC_ARG1_CTRL_RXQ_FREE 0x01000008 /// must but not used at this stage ++ ++// TX arg1 ++#define SWTOE_IPC_ARG1_TXQ_PUT 0x02000001 ++#define SWTOE_IPC_ARG1_TXQ_GET 0x02000002 ++ ++// RX ++#define SWTOE_IPC_ARG1_RXQ_GET 0x03000001 ++ ++// Protocol ++#define SWTOE_IPC_ARG1_PROT_CREATE 0x04000001 ++ ++#define SWTOE_IPC_ARG1_PROT_CNX_REQ 0x04000002 ++#define SWTOE_IPC_ARG1_PROT_CNX_RESP 0x04000003 ++ ++#define SWTOE_IPC_ARG1_PROT_DISCNX_REQ 0x04000004 ++#define SWTOE_IPC_ARG1_PROT_DISCNX_RESP 0x04000005 // Is this required?? ++ ++#define SWTOE_IPC_ARG1_PROT_BIND_REQ 0x04000006 ++#define SWTOE_IPC_ARG1_PROT_BIND_RESP 0x04000007 ++ ++#define SWTOE_IPC_ARG1_PROT_LSTN_START 0x04000008 ++#define SWTOE_IPC_ARG1_PROT_LSTN_STOP 0x04000009 ++#define SWTOE_IPC_ARG1_PROT_LSTN_RESP 0x0400000a ++ ++#define SWTOE_IPC_ARG1_PROT_ACPT_REQ 0x0400000c ++#define SWTOE_IPC_ARG1_PROT_ACPT_RESP 0x0400000d // Is this required?? ++ ++#define SWTOE_IPC_ARG1_PROT_SHDN_REQ 0x040000F0 ++#define SWTOE_IPC_ARG1_PROT_SHDN_RESP 0x040000F1 // Is this required?? ++#define SWTOE_IPC_ARG1_PROT_CLS_REQ 0x040000F2 ++#define SWTOE_IPC_ARG1_PROT_CLS_RESP 0x040000F3 ++ ++//-------------------------------------------------------------------------------------------------- ++// Some helper functions ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Data structure definition ++//-------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ u32 saddr; ++ u32 daddr; ++ u16 sport; ++ u16 dport; ++ u32 blk : 1; ++ u32 status : 1; ++ u32 cause : 2; ++ /// 0x0 : 'connection' information from SWTOE_IPC_ARG1_PROT_CNX_REQ ++ /// 0x1 : 'binding' information from SWTOE_IPC_ARG1_PROT_BIND_REQ ++ /// 0x2 : 'listen' information ++ u32 reserved : 28; ++} __attribute__ ((packed)) sstoe_prot_cnx_info_t; ++ ++typedef struct ++{ ++ u32 used : 1; ++ u32 prot : 2; ++ u32 cnx_id : 11; ++ u32 reserved : 16; ++ u32 desc_addr; ++ u16 pkt_size; ++ u16 depth; ++ u16 write; // Linux write. RTK read ++ u16 read; // Linux read. RTK write ++ sstoe_prot_cnx_info_t cnx_info; ++} __attribute__ ((packed)) sstoe_ipc_txq_info; ++ ++typedef struct ++{ ++ u32 used : 1; ++ u32 cnx_id : 11; ++ u32 reserved : 20; ++ u32 desc_addr; ++ u16 pkt_size; ++ u16 depth; ++ u16 write; // Linux read. RTK write ++ u16 read; // Linux write. RTK read ++} __attribute__ ((packed)) sstoe_ipc_rxq_info; ++ ++typedef struct ++{ ++ u32 dummy; ++} __attribute__ ((packed)) sstoe_ipc_stats_t; ++ ++typedef struct ++{ ++ sstoe_prot_cnx_info_t lstn; // lstn data. Linux read only. RTK read/write ++ u32 lock_lx : 2; // 0x0 : initial state which RTK can write it ++ // 0x1 : RTK write complete and Linux can read it ++ // 0x2 : Linux read complete and RTK can write it ++ u32 reserved : 30; // Linux read/write. RTK read only ++} __attribute__ ((packed)) sstoe_ipc_lstn_t; ++ ++typedef struct ++{ ++ sstoe_ipc_txq_info txq_info[MAX_CNX_TXQ_NUM]; ++ sstoe_ipc_rxq_info rxq_info[1]; ++ sstoe_ipc_lstn_t lstn_data; ++ ++ /// @FIXME : to be refine ++ // u32 txq_signal[((MAX_CNX_TXQ_NUM + 31)>> 3)/sizeof(u32)]; /// this should be used, but ... ++ /// @FIXME : to be refine ++ // u32 rxq_signal[((1 + 31)>> 3)/sizeof(u32)]; ++ sstoe_ipc_stats_t stats; ++} __attribute__ ((packed)) sstoe_ipc_ctrl_t; ++ ++typedef struct ++{ ++ u32 hw_own : 1; ++ u32 eof : 1; ++ u32 reserved1 : 6; ++ u32 buf_size : 16; ++ /// u32 reserved2 : 2; ++ u32 buf_addr : 29; ++ u32 reserved3 : 11; ++} __attribute__ ((packed)) sstoe_tx_desc_t; ++ ++// rx desc : 12 bytes ++typedef struct ++{ ++ u32 hw_own : 1; ++ u32 crc_flag : 2; // might not be required ++ // #define CHECKSUM_NONE 0 ++ // #define CHECKSUM_UNNECESSARY 1 ++ // #define CHECKSUM_COMPLETE 2 ++ // #define CHECKSUM_PARTIAL 3 ++ u32 reserved1 : 5; ++ u32 buf_size : 16; ++ u32 buf_addr : 29; ++ u32 cnx_id : 11; ++ // u32 seq_num : 32; ++} __attribute__ ((packed)) sstoe_rx_desc_t; ++ ++//-------------------------------------------------------------------------------------------------- ++// global variables ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// malloc helper function ++//-------------------------------------------------------------------------------------------------- ++ ++#endif +diff --git a/drivers/sstar/swtoe/mdrv_swtoe_prot.c b/drivers/sstar/swtoe/mdrv_swtoe_prot.c +new file mode 100755 +index 000000000000..b9dbd3c9e02f +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe_prot.c +@@ -0,0 +1,311 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "drv_dualos.h" ++#include "mdrv_swtoe.h" ++#include "mdrv_swtoe_intl.h" ++ ++int drv_swtoe_create(int prot, int* cnx_id) ++{ ++ int ret = 0; ++ int txq_id; ++ ++ if (0 != (ret = drv_swtoe_cnx_txq_create(prot, &txq_id))) ++ { ++ return ret; ++ } ++ if (DRV_SWTOE_PROT_BYPASS != prot) ++ { ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_CREATE, txq_id & 0xFFFF, 0))) ++ { ++ printk("[%s][%d] TX packet IPC fail %d\n", __FUNCTION__, __LINE__, ret); ++ return ret; ++ } ++ } ++ *cnx_id = txq_id; ++ return 0; ++} ++ ++int drv_swtoe_connect(int cnx_id, struct sockaddr* addr, int blk) ++{ ++ struct sockaddr_in *usin = (struct sockaddr_in *)addr; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int ret; ++ ++ /// support ipv4 at this stage. don't know how to deal with ipv6 now ++ if (PF_INET != usin->sin_family) ++ { ++ printk("[%s][%d] not ipv4 protocol %d\n", __FUNCTION__, __LINE__, (int)usin->sin_family); ++ return -1; ++ } ++ CNX_SANITY(cnx_id); ++ ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ pTXQ_IPC->cnx_info.cause = 0x0; ++ pTXQ_IPC->cnx_info.blk = blk; ++ ++ pTXQ_IPC->cnx_info.dport = htons(usin->sin_port); ++ pTXQ_IPC->cnx_info.daddr = htonl(usin->sin_addr.s_addr); ++ ++ /// refine source address port later ++ pTXQ_IPC->cnx_info.sport = htons(0); /// any port ++ pTXQ_IPC->cnx_info.saddr = htonl(INADDR_ANY); /// any address ++ ++ printk("[%s][%d] (daddr, dport) = (0x%08x, 0x%04x)\n", __FUNCTION__, __LINE__, pTXQ_IPC->cnx_info.daddr, pTXQ_IPC->cnx_info.dport); ++ printk("[%s][%d] (saddr, sport) = (0x%08x, 0x%04x)\n", __FUNCTION__, __LINE__, pTXQ_IPC->cnx_info.saddr, pTXQ_IPC->cnx_info.sport); ++ printk("[%s][%d] blocking mode = %d\n", __FUNCTION__, __LINE__, pTXQ_IPC->cnx_info.blk); ++ ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_CNX_REQ, cnx_id & 0xFFFF, 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_CNX_REQ); ++ return -1; ++ } ++ return 0; ++} ++ ++int drv_swtoe_disconnect(int cnx_id) ++{ ++ int ret; ++ ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_DISCNX_REQ, cnx_id & 0xFFFF, 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_DISCNX_REQ); ++ return -1; ++ } ++ return 0; ++} ++ ++int drv_swtoe_shutdown(int cnx_id) ++{ ++ int ret = 0; ++ ++ CNX_SANITY(cnx_id); ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_SHDN_REQ, cnx_id & 0xFFFF, 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_SHDN_REQ); ++ return -1; ++ } ++ /// @FIXME : how to handle the synchronization ++ drv_swtoe_cnx_txq_free(cnx_id); ++ return 0; ++} ++ ++int drv_swtoe_close(int cnx_id) ++{ ++ int ret = 0; ++ ++ CNX_SANITY(cnx_id); ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_CLS_REQ, cnx_id & 0xFFFF, 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_CLS_REQ); ++ return -1; ++ } ++ return 0; ++} ++ ++int drv_swtoe_bind(int cnx_id, struct sockaddr* addr) ++{ ++ struct sockaddr_in *usin = (struct sockaddr_in *)addr; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int ret; ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ /// support ipv4 at this stage. don't know how to deal with ipv6 now ++ if (PF_INET != usin->sin_family) ++ { ++ printk("[%s][%d] not ipv4 protocol %d\n", __FUNCTION__, __LINE__, (int)usin->sin_family); ++ return -1; ++ } ++ CNX_SANITY(cnx_id); ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ ++ pCNX->bind_ready = 0; ++ pTXQ_IPC->cnx_info.blk = 0; ++ pTXQ_IPC->cnx_info.sport = htons(usin->sin_port); ++ pTXQ_IPC->cnx_info.saddr = htonl(usin->sin_addr.s_addr); ++ ++ /// refine source address port later ++ pTXQ_IPC->cnx_info.dport = htons(0); /// any port ++ pTXQ_IPC->cnx_info.daddr = htonl(INADDR_ANY); /// any address ++ pTXQ_IPC->cnx_info.cause = 0x1; ++ ++ ++ printk("[%s][%d] (daddr, dport) = (0x%08x, 0x%04x)\n", __FUNCTION__, __LINE__, pTXQ_IPC->cnx_info.daddr, pTXQ_IPC->cnx_info.dport); ++ printk("[%s][%d] (saddr, sport) = (0x%08x, 0x%04x)\n", __FUNCTION__, __LINE__, pTXQ_IPC->cnx_info.saddr, pTXQ_IPC->cnx_info.sport); ++ // printk("[%s][%d] blocking mode = %d\n", __FUNCTION__, __LINE__, pTXQ_IPC->cnx_info.blk); ++ ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_BIND_REQ, cnx_id & 0xFFFF, 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_CNX_REQ); ++ return -1; ++ } ++ return 0; ++} ++ ++int drv_swtoe_bind_status(int cnx_id) ++{ ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ CNX_SANITY(cnx_id); ++ return (HAS_FLAGS(pCNX->bind_ready, 0x80)) ? -(pCNX->bind_ready & 0x1) : 1; ++} ++ ++int drv_swtoe_lstn_start(int cnx_id, int backlog) /// max of backlog is 128, SOMAXCONN ++{ ++ int ret = 0; ++ ++ CNX_SANITY(cnx_id); ++ ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_LSTN_START, (backlog << 16) | (cnx_id & 0xFFFF), 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_LSTN_START); ++ return -1; ++ } ++ return 0; ++} ++ ++int drv_swtoe_lstn_stop(int cnx_id) ++{ ++ int ret = 0; ++ ++ CNX_SANITY(cnx_id); ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_PROT_LSTN_STOP, (cnx_id & 0xFFFF), 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, cmd) = (%d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, SWTOE_IPC_ARG1_PROT_LSTN_STOP); ++ return -1; ++ } ++ return 0; ++} ++ ++typedef struct ++{ ++ struct list_head list; ++ drv_swtoe_glue_cnx_data lstn_data; ++} lstn_data_t; ++ ++int drv_swtoe_lstn_resp(int cnx_id) ++ { ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ lstn_data_t* plstn_data; ++ ++ CNX_SANITY(cnx_id); ++ if (0x1 != g_pIpcInfo->lstn_data.lock_lx) ++ { ++ printk("[%s][%d] bad state for listen data lock %d (should be 1)\n", __FUNCTION__, __LINE__, g_pIpcInfo->lstn_data.lock_lx); ++ return -1; ++ } ++ if (NULL == (plstn_data = kmalloc(sizeof(lstn_data_t), GFP_ATOMIC))) ++ { ++ printk("[%s][%d] kmalloc %d bytes fail\n", __FUNCTION__, __LINE__, sizeof(lstn_data_t)); ++ return -1; ++ } ++ ++ plstn_data->lstn_data.saddr = htonl(g_pIpcInfo->lstn_data.lstn.saddr); ++ plstn_data->lstn_data.daddr = htonl(g_pIpcInfo->lstn_data.lstn.daddr); ++ plstn_data->lstn_data.sport = htons(g_pIpcInfo->lstn_data.lstn.sport); ++ plstn_data->lstn_data.dport = htons(g_pIpcInfo->lstn_data.lstn.dport); ++ list_add_tail(&plstn_data->list, &pCNX->lstn_queue); ++ g_pIpcInfo->lstn_data.lock_lx = 0x2; ++ return 0; ++} ++ ++int drv_swtoe_lstn_empty(int cnx_id) ++{ ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ CNX_SANITY(cnx_id); ++ return (list_empty(&pCNX->lstn_queue)) ? 1 : 0; ++} ++ ++int drv_swtoe_lstn_remove(int cnx_id, drv_swtoe_lstn_data* pdrv_lstn_data) ++{ ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ lstn_data_t* plstn_data; ++ ++ CNX_SANITY(cnx_id); ++ if (list_empty(&pCNX->lstn_queue)) ++ { ++ return -1; ++ } ++ ++ plstn_data = list_first_entry(&pCNX->lstn_queue, lstn_data_t, list); ++ memcpy(pdrv_lstn_data, plstn_data, sizeof(drv_swtoe_lstn_data)); ++ list_del(&plstn_data->list); ++ return 0; ++} ++ ++int drv_swtoe_lstn_clr(int cnx_id) ++{ ++ drv_swtoe_lstn_data lstn_data; ++ ++ while (!drv_swtoe_lstn_remove(cnx_id, &lstn_data)); ++ ++ return 0; ++} ++ ++int drv_swtoe_clone(int cnx_id, int* new_cnx_id, drv_swtoe_lstn_data* plstn_data) ++{ ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC_new = NULL; ++ int ret; ++ ++ CNX_SANITY(cnx_id); ++ ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ ++ ++ if ((ret = drv_swtoe_create(pTXQ_IPC->prot, new_cnx_id))) ++ { ++ printk("[%s][%d] drv_swtoe_create fail\n", __FUNCTION__, __LINE__); ++ return ret; ++ } ++ ++ pTXQ_IPC_new = &g_pIpcInfo->txq_info[*new_cnx_id]; ++ ++ pTXQ_IPC_new->cnx_info.dport = htons(plstn_data->dport); ++ pTXQ_IPC_new->cnx_info.daddr = htonl(plstn_data->daddr); ++ pTXQ_IPC_new->cnx_info.sport = htons(plstn_data->sport); ++ pTXQ_IPC_new->cnx_info.saddr = htonl(plstn_data->saddr); ++ ++ return 0; ++} ++ ++int drv_swtoe_acpt(int cnx_id, int new_cnx_id) ++{ ++ int ret; ++ ++ CNX_SANITY(cnx_id); ++ CNX_SANITY(new_cnx_id); ++ ++ if ((ret = signal_rtos(SWTOE_IPC_ARG0, ++ SWTOE_IPC_ARG1_PROT_ACPT_REQ, ++ (((new_cnx_id & 0xFFFF)<< 16) | (cnx_id & 0xFFFF)), ++ 0))) ++ { ++ printk("[%s][%d] IPC fail %d. (cnx_id, new_cnx_id, cmd) = (%d, %d, 0x%08x)\n", __FUNCTION__, __LINE__, ret, cnx_id, new_cnx_id, SWTOE_IPC_ARG1_PROT_ACPT_REQ); ++ return -1; ++ } ++ ++ return 0; ++} +diff --git a/drivers/sstar/swtoe/mdrv_swtoe_rxq.c b/drivers/sstar/swtoe/mdrv_swtoe_rxq.c +new file mode 100755 +index 000000000000..9156dbc98d8a +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe_rxq.c +@@ -0,0 +1,381 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe_rxq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mstar_chip.h" ++#include "drv_dualos.h" ++#include "mdrv_swtoe.h" ++#include "mdrv_swtoe_intl.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Data structure definition ++//-------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ // int rx_pkt_size; ++ // int rxq_depth; ++ // virtual addr ++ sstoe_rx_desc_t* rxq; ++ // miu address ++ // dma_addr_t rxq_phy; ++ ++ // ++ // struct sk_buff** skb_list; ++ ++ // char used; ++ // u16 read; ++ char** buf_list; ++ // int buf_size; ++ int frag_size; ++} sstoe_rxq_info; ++ ++//-------------------------------------------------------------------------------------------------- ++// Data definition ++//-------------------------------------------------------------------------------------------------- ++static sstoe_rxq_info rxq_info[1]; ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++// static int _drv_sstoe_rxq_skb_alloc(struct sk_buff **skb, int size); ++// static void _drv_sstoe_rxq_skb_free(struct sk_buff *skb); ++ ++#if 0 ++static inline int mtk_max_frag_size(int mtu) ++{ ++ /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ ++ if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) ++ mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; ++ ++ return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++} ++ ++static inline int mtk_max_buf_size(int frag_size) ++{ ++ int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ ++ WARN_ON(buf_size < MTK_MAX_RX_LENGTH); ++ ++ return buf_size; ++} ++#endif ++ ++#if 0 ++ /* receive data */ ++ skb = build_skb(data, ring->frag_size); ++ if (unlikely(!skb)) { ++ SWTOE_FREE(new_data); ++ netdev->stats.rx_dropped++; ++ goto release_desc; ++ } ++ skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); ++ ++#endif ++#if 0 ++ dma_addr = dma_map_single(eth->dev, ++ new_data + NET_SKB_PAD, ++ ring->buf_size, ++ DMA_FROM_DEVICE); ++#endif ++//-------------------------------------------------------------------------------------------------- ++// Implementation ++//-------------------------------------------------------------------------------------------------- ++int drv_swtoe_cnx_rxq_create(int serv_id) ++{ ++ sstoe_rxq_info* pRXQ = NULL; ++ sstoe_ipc_rxq_info* pRXQ_IPC = NULL; ++ int i; ++ ++ if (1 <= serv_id) ++ { ++ printk("[%s][%d] illegal ervice Id. (max, requested) = (%d, %d)\n", __FUNCTION__, __LINE__, 1, serv_id); ++ return -1; ++ } ++ pRXQ_IPC = &g_pIpcInfo->rxq_info[serv_id]; ++ if (1 == pRXQ_IPC->used) ++ { ++ printk("[%s][%d] RX queue of service %d has been created\n", __FUNCTION__, __LINE__, serv_id); ++ return 0; ++ } ++ pRXQ = &rxq_info[serv_id]; ++ pRXQ->frag_size = MAX_RXQ_PKT_SIZE; ++ pRXQ_IPC->depth = MAX_RXQ_DEPTH; // @FIXME : dynamic ++ // pRXQ_IPC->pkt_size = pRXQ->frag_size - NET_SKB_PAD - NET_IP_ALIGN - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); ++ pRXQ_IPC->pkt_size = pRXQ->frag_size; ++ // printk("[%s][%d] try to allocate rx desc = %d, %d, %d\n", __FUNCTION__, __LINE__, pRXQ_IPC->depth, sizeof(sstoe_rx_desc_t), pRXQ_IPC->depth*sizeof(sstoe_rx_desc_t)); ++ pRXQ->rxq = (sstoe_rx_desc_t*) dma_alloc_coherent(NULL, pRXQ_IPC->depth*sizeof(sstoe_rx_desc_t), &pRXQ_IPC->desc_addr, GFP_KERNEL); ++ if (NULL == pRXQ->rxq) ++ { ++ printk("[%s][%d] allocate rx descriptor memory fail\n", __FUNCTION__, __LINE__); ++ goto create_fail; ++ } ++ memset(pRXQ->rxq, 0, pRXQ_IPC->depth*sizeof(sstoe_rx_desc_t)); ++ if (NULL == (pRXQ->buf_list = kzalloc(pRXQ_IPC->depth*sizeof(char*), GFP_KERNEL))) ++ { ++ printk("[%s][%d] allocate rx buffer list fail\n", __FUNCTION__, __LINE__); ++ goto create_fail; ++ } ++ ++ for (i = 0; i < pRXQ_IPC->depth; i++) ++ { ++ if (NULL == (pRXQ->buf_list[i] = SWTOE_MALLOC(pRXQ->frag_size))) ++ { ++ goto create_fail; ++ } ++ // pRXQ->rxq[i].buf_addr = VIRT2BUS(pRXQ->buf_list[i] + NET_IP_ALIGN); ++ pRXQ->rxq[i].buf_addr = VIRT2BUS(pRXQ->buf_list[i]); ++ pRXQ->rxq[i].buf_size = 0; ++ pRXQ->rxq[i].hw_own = 1; ++ } ++ pRXQ_IPC->used = 1; ++ pRXQ_IPC->read = pRXQ_IPC->write = 0; ++ ++ return 0; ++create_fail: ++ for (i = 0; i < pRXQ_IPC->depth; i++) ++ { ++ if (pRXQ->buf_list[i]) ++ { ++ SWTOE_FREE(pRXQ->buf_list[i]); ++ pRXQ->buf_list[i] = NULL; ++ } ++ } ++ if (pRXQ->buf_list) ++ { ++ kfree(pRXQ->buf_list); ++ pRXQ->buf_list = NULL; ++ } ++ if (pRXQ->rxq) ++ { ++ dma_free_coherent(NULL, pRXQ_IPC->depth*sizeof(sstoe_rx_desc_t), pRXQ->rxq, pRXQ_IPC->desc_addr); ++ pRXQ->rxq = NULL; ++ pRXQ_IPC->desc_addr = 0; ++ } ++ return -ENOMEM; ++} ++ ++int drv_swtoe_cnx_rxq_get(int* cnx_id, char** buf, int* buf_size, char** data, int* data_size) ++{ ++ sstoe_rxq_info* pRXQ = NULL; ++ sstoe_ipc_rxq_info* pRXQ_IPC = NULL; ++ sstoe_rx_desc_t* pDesc = NULL; ++ int read; ++ int serv_id = 0; ++ ++ pRXQ_IPC = &g_pIpcInfo->rxq_info[serv_id]; ++ if (NULL == pRXQ_IPC) ++ { ++ panic("what heppen for NULL pRXQ_IPC, %d", serv_id); ++ return -1; ++ } ++ if (0 == pRXQ_IPC->used) ++ { ++ // printk("[%s][%d] RX queue of service %d has not been created\n", __FUNCTION__, __LINE__, serv_id); ++ return -1; ++ } ++ if (pRXQ_IPC->read == pRXQ_IPC->write) ++ { ++ return -2; ++ } ++ pRXQ = &rxq_info[serv_id]; ++ read = pRXQ_IPC->read; ++ pDesc = &pRXQ->rxq[read]; ++ if (NULL == pDesc) ++ { ++ panic("what heppen for NULL pRXQ desc %d", read); ++ return -1; ++ } ++ if (pDesc->hw_own) ++ { ++ printk("[%s][%d] descriptor belongs to RTOS\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ *cnx_id = pDesc->cnx_id; ++ *buf = pRXQ->buf_list[read]; ++ *buf_size = pRXQ->frag_size; ++ *data = BUS2VIRT(pDesc->buf_addr); ++ *data_size = pDesc->buf_size; ++ ++ CNX_SANITY(*cnx_id); ++ ++ if (NULL == (pRXQ->buf_list[read] = SWTOE_MALLOC(pRXQ->frag_size))) ++ { ++ panic("allocaate TOE rx buffer for %d bytes fail]\n", pRXQ->frag_size); ++ } ++ pDesc->cnx_id = 0; ++ pDesc->buf_addr = VIRT2BUS(pRXQ->buf_list[read]); ++ pDesc->buf_size = 0; ++ pDesc->hw_own = 1; ++ ++ read++; ++ if (read >= pRXQ_IPC->depth) ++ { ++ read -= pRXQ_IPC->depth; ++ } ++ pRXQ_IPC->read = read; ++ // return (pRXQ_IPC->read == pRXQ_IPC->write) ? 0 : 1; ++ return 0; ++} ++ ++ ++typedef struct ++{ ++ struct list_head list; ++ drv_swtoe_rx_data msg_rx; ++} msg_queue_rx; ++ ++int drv_swtoe_rx_data_get(int cnx_id, drv_swtoe_rx_data* from, drv_swtoe_rx_data** pp_rx_data) ++{ ++ msg_queue_rx* p_msg_rx; ++ msg_queue_rx* p_prev = NULL; ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ CNX_SANITY(cnx_id); ++ *pp_rx_data = NULL; ++ if (list_empty(&pCNX->rdata_queue)) ++ { ++ return -1; ++ } ++ if (!from) ++ { ++ p_msg_rx = list_first_entry(&pCNX->rdata_queue, msg_queue_rx, list); ++ *pp_rx_data = &p_msg_rx->msg_rx; ++ return 0; ++ } ++ ++ p_prev = container_of(from, msg_queue_rx, msg_rx); ++ if (list_is_last(&p_prev->list, &pCNX->rdata_queue)) ++ { ++ return -1; ++ } ++ ++ p_msg_rx = list_next_entry(p_prev, list); ++ *pp_rx_data = &p_msg_rx->msg_rx; ++ return 0; ++ } ++ ++int drv_swtoe_rx_data_free(int cnx_id, drv_swtoe_rx_data* p_rx_data, int free) ++{ ++ msg_queue_rx* p_msg_rx = container_of(p_rx_data, msg_queue_rx, msg_rx); ++ ++ CNX_SANITY(cnx_id); ++ if (!p_msg_rx) ++ { ++ printk("[%s][%d] container of fail. 0x%08x\n", __FUNCTION__, __LINE__, (int)p_rx_data); ++ return -1; ++ } ++ list_del(&p_msg_rx->list); ++ ++ if ((free) && (p_msg_rx->msg_rx.buf)) ++ { ++ SWTOE_FREE(p_msg_rx->msg_rx.buf); ++ } ++ kfree(p_msg_rx); ++ return 0; ++} ++ ++int drv_swtoe_rx_data_avail(int cnx_id) ++{ ++ msg_queue_rx* p_msg_rx; ++ sstoe_cnx_info* pCNX = &g_pCnxInfo[cnx_id]; ++ ++ CNX_SANITY(cnx_id); ++ if (list_empty(&pCNX->rdata_queue)) ++ { ++ return -1; ++ } ++ p_msg_rx = list_first_entry(&pCNX->rdata_queue, msg_queue_rx, list); ++ return (p_msg_rx->msg_rx.data_size == p_msg_rx->msg_rx.offset) ? -1 : 0; ++ // return (p_msg_rx->msg_rx.data_size) ? 0 : -1; ++} ++ ++static unsigned long cnx_signal[LONG_DIV(MAX_CNX_TXQ_NUM)] = { 0 }; ++ ++int drv_swtoe_rx_data_put(void) ++{ ++ int ret; ++ char *buf, *data; ++ int buf_size, data_size; ++ msg_queue_rx* p_queue_data_rx = NULL; ++ int i; ++ unsigned long* p; ++ long base, pos; ++ int cnx_id; ++ sstoe_cnx_info* pCNX = NULL; ++ ++ while (1) ++{ ++ ret = drv_swtoe_cnx_rxq_get(&cnx_id, &buf, &buf_size, &data, &data_size); ++ if (0 > ret) ++ break; ++ CNX_SANITY(cnx_id); ++ if (NULL == (p_queue_data_rx = kmalloc(sizeof(msg_queue_rx), GFP_ATOMIC))) ++ { ++ printk("[%s][%d] alloc fail. size = %d\n", __FUNCTION__, __LINE__, sizeof(msg_queue_rx)); ++ continue; ++} ++ pCNX = &g_pCnxInfo[cnx_id]; ++ p_queue_data_rx->msg_rx.buf = buf; ++ p_queue_data_rx->msg_rx.buf_size = buf_size; ++ p_queue_data_rx->msg_rx.data = data; ++ p_queue_data_rx->msg_rx.data_size = data_size; ++ p_queue_data_rx->msg_rx.offset = 0; ++ list_add_tail(&p_queue_data_rx->list, &pCNX->rdata_queue); ++ ++ SET_BITS_POS(cnx_signal, cnx_id); ++ if (0 == ret) ++{ ++ break; ++ } ++ } ++ for (i = 0; i < LONG_DIV(MAX_CNX_TXQ_NUM); i++) ++ { ++ p = &cnx_signal[i]; ++ base = LONG_MULT(i); ++ pos = -1; ++ do ++ { ++ pos = find_next_bit(p, BITS_PER_LONG, pos+1); ++ if (BITS_PER_LONG == pos) ++ { ++ *p = 0; ++ break; ++ } ++ cnx_id = base + pos; ++ pCNX = &g_pCnxInfo[cnx_id]; ++ /// if ((HAS_BITS(pCNX->cb_mask, DRV_SWTOE_CB_RCOM)) && (pCNX->cb_func)) ++ if (1) ++ { ++ (pCNX->cb_func)(cnx_id, DRV_SWTOE_GLUE_RCOM, NULL, pCNX->cb_data); ++ } ++ } while (pos < BITS_PER_LONG); ++ } ++ return 0; ++} +diff --git a/drivers/sstar/swtoe/mdrv_swtoe_txq.c b/drivers/sstar/swtoe/mdrv_swtoe_txq.c +new file mode 100755 +index 000000000000..6fcc8fb64393 +--- /dev/null ++++ b/drivers/sstar/swtoe/mdrv_swtoe_txq.c +@@ -0,0 +1,554 @@ ++/* SigmaStar trade secret */ ++/* ++* mdrv_swtoe_txq.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mstar_chip.h" ++#include "ms_platform.h" ++#include "drv_dualos.h" ++#include "mdrv_swtoe.h" ++#include "mdrv_swtoe_intl.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Data structure definition ++//-------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ struct list_head list; ++ void* p; ++ u32 size : 16; ++ u32 data_cat : 2; ++ u32 reserved1 : 14; ++ void* p2; ++} prequeue_data; ++ ++//-------------------------------------------------------------------------------------------------- ++// Helper functions ++//-------------------------------------------------------------------------------------------------- ++#define SANITY_DESC_LX_PRIVATE(p) \ ++{ \ ++ if (HAS_FLAGS((int)(p), 0x1)) \ ++ { \ ++ printk("[%s][%d] address is odd = 0x%08x\n", __FUNCTION__, __LINE__, (int)(p)); \ ++ } \ ++} ++ ++//-------------------------------------------------------------------------------------------------- ++// Data definition ++//-------------------------------------------------------------------------------------------------- ++#if DBG_TX_MEM ++int g_cnt_alloc = 0; ++int g_cnt_free = 0; ++int g_cnt_ipc_free = 0; ++#endif ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Implementation ++//-------------------------------------------------------------------------------------------------- ++int drv_swtoe_cnx_txq_create(int prot, int* cnx_id) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int ipc_ret; ++ int i; ++ ++ switch (prot) ++ { ++ case DRV_SWTOE_PROT_BYPASS: ++ case DRV_SWTOE_PROT_TCP: ++ case DRV_SWTOE_PROT_UDP: ++ break; ++ default: ++ printk("[%s][%d] unknown txq protocol type %d\n", __FUNCTION__, __LINE__, prot); ++ return -1; ++ } ++ for (i = 0; i < MAX_CNX_TXQ_NUM; i++) ++ { ++ if (0 == g_pIpcInfo->txq_info[i].used) ++ { ++ pTXQ_IPC = &g_pIpcInfo->txq_info[i]; ++ pCNX = &g_pCnxInfo[i]; ++ break; ++ } ++ } ++ if (NULL == pTXQ_IPC) ++ { ++ printk("[%s][%d] unable to find a free connection\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ pCNX->tx_desc = (sstoe_tx_desc_t*) dma_alloc_coherent(NULL, MAX_TXQ_DEPTH*sizeof(sstoe_tx_desc_t), &pTXQ_IPC->desc_addr, GFP_ATOMIC); ++ if (NULL == pCNX->tx_desc) ++ { ++ printk("[%s][%d] allocate tx descriptor memory fail\n", __FUNCTION__, __LINE__); ++ goto create_fail; ++ } ++ if (!(pCNX->RTF = kzalloc(MAX_TXQ_DEPTH * sizeof(void*), GFP_KERNEL))) ++ { ++ printk("[%s][%d] allocate RTF buffer fail\n", __FUNCTION__, __LINE__); ++ goto create_fail; ++ } ++ memset(pCNX->tx_desc, 0, MAX_TXQ_DEPTH*sizeof(sstoe_tx_desc_t)); ++ pTXQ_IPC->depth = MAX_TXQ_DEPTH; // @FIXME : dynamic ++ pTXQ_IPC->pkt_size = MAX_TXQ_PKT_SIZE; // @FIXME : dynamic ++ pTXQ_IPC->used = 1; ++ pTXQ_IPC->prot = prot; ++ pTXQ_IPC->write = 0; ++ pTXQ_IPC->read = pCNX->read_lx = 0; ++ pTXQ_IPC->desc_addr = PA2BUS(pTXQ_IPC->desc_addr); ++ Chip_Flush_MIU_Pipe(); ++ INIT_LIST_HEAD(&pCNX->wdata_queue); ++ pCNX->wdata_queue_size = 0; ++ INIT_LIST_HEAD(&pCNX->rdata_queue); ++ INIT_LIST_HEAD(&pCNX->lstn_queue); ++ ++ spin_lock_init(&pCNX->lock); ++ pCNX->cb_func = NULL; ++ pCNX->cb_data = NULL; ++ pCNX->cb_mask = 0; ++ pCNX->bind_ready = 0; ++ ++ if ((ipc_ret = signal_rtos(SWTOE_IPC_ARG0, SWTOE_IPC_ARG1_CTRL_TXQ_ALLOC, i, sizeof(sstoe_ipc_txq_info) & 0xFFFF))) ++ { ++ printk("[%s][%d] TX packet IPC fail %d\n", __FUNCTION__, __LINE__, ipc_ret); ++ return -1; ++ } ++ *cnx_id = i; ++ return 0; ++ ++create_fail: ++ if (pCNX->RTF) ++ { ++ kfree(pCNX->RTF); ++ pCNX->RTF = NULL; ++ } ++ if (pTXQ_IPC->desc_addr) ++ { ++ dma_free_coherent(NULL, pTXQ_IPC->depth*sizeof(sstoe_tx_desc_t), pCNX->tx_desc, BUS2PA(pTXQ_IPC->desc_addr)); ++ pCNX->tx_desc = NULL; ++ memset(pTXQ_IPC, 0, sizeof(*pTXQ_IPC)); ++ } ++ return -ENOMEM; ++} ++ ++int drv_swtoe_cnx_txq_free(int cnx_id) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ // sstoe_tx_desc_t* pDesc = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ ++ CNX_SANITY(cnx_id); ++ pCNX = &g_pCnxInfo[cnx_id]; ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ ++ if (pTXQ_IPC->desc_addr) ++ { ++ dma_free_coherent(NULL, pTXQ_IPC->depth*sizeof(sstoe_tx_desc_t), pCNX->tx_desc, BUS2PA(pTXQ_IPC->desc_addr)); ++ pCNX->tx_desc = NULL; ++ memset(pTXQ_IPC, 0, sizeof(*pTXQ_IPC)); ++ } ++ return 0; ++} ++ ++static int _drv_swtoe_tx_avail(int cnx_id, int n) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ sstoe_tx_desc_t* pDesc = NULL; ++ u16 write; ++ u16 read; ++ int space; ++ ++ CNX_SANITY(cnx_id); ++ if (0 >= n) ++ return 0; ++ ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ pCNX = &g_pCnxInfo[cnx_id]; ++ if (pTXQ_IPC->depth < n) ++ return -1; ++ write = pTXQ_IPC->write; ++ pDesc = &(pCNX->tx_desc[write]); ++ if (pDesc->hw_own) ++ return -1; ++ read = pCNX->read_lx; ++ space = (write >= read) ? pTXQ_IPC->depth - write + read : (read - write); ++ space--; ++ return (space >= n) ? 0 : -1; ++} ++ ++int drv_swtoe_tx_avail(int cnx_id, int n) ++{ ++ return _drv_swtoe_tx_avail(cnx_id, n); ++} ++ ++int drv_swtoe_tx_consume(int cnx_id) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ sstoe_tx_desc_t* pDesc = NULL; ++ u16 read; ++ u16 read_lx; ++ u16 depth; ++ void* p; ++ int cnt = 0; ++ ++ pCNX = &g_pCnxInfo[cnx_id]; ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ read = pTXQ_IPC->read; ++ read_lx = pCNX->read_lx; ++ ++ if (read_lx == pTXQ_IPC->read) ++ { ++ return 0; ++ } ++ ++ depth = pTXQ_IPC->depth; ++ ++ while (read_lx != read) ++ { ++ pDesc = &(pCNX->tx_desc[read_lx]); ++ p = pCNX->RTF[read_lx]; ++ TX_MEM_FREE_INC(); ++ if (NULL == p) ++ { ++ /// iov copy ++ p = BUS2VIRT(pDesc->buf_addr); ++ // printk("[%s][%d] free memory =0x%08x\n", __FUNCTION__, __LINE__, (int)p); ++ SWTOE_FREE(p); ++ } ++ else if (HAS_FLAGS((int)p, 0x1)) ++ { ++ /// pages ++ p = (void*)CLR_FLAGS((int)p, 0x1); ++ // printk("[%s][%d] free page =0x%08x\n", __FUNCTION__, __LINE__, (int)p); ++ put_page((struct page*)p); ++ } ++ else ++ { ++ // printk("[%s][%d] free skb =0x%08x\n", __FUNCTION__, __LINE__, (int)p); ++ /// skb ++ dev_kfree_skb_any((struct sk_buff*)p); ++ } ++ memset(pDesc, 0, sizeof(*pDesc)); ++ read_lx++; ++ cnt++; ++ if (read_lx >= depth) ++ { ++ read_lx = 0; ++ } ++ } ++ pCNX->read_lx = read_lx; ++ Chip_Flush_MIU_Pipe(); ++ return cnt; ++} ++ ++static int _drv_swtoe_txq_preput(int cnx_id, void* p, int size, int data_cat, void* p2) ++{ ++ prequeue_data *preq_data; ++ sstoe_cnx_info* pCNX = NULL; ++ ++ CNX_SANITY(cnx_id); ++ if (NULL == (preq_data = kmalloc(sizeof(prequeue_data), GFP_KERNEL))) ++ { ++ printk("[%s][%d] kmalloc %d byte fail.\n", __FUNCTION__, __LINE__, sizeof(prequeue_data)); ++ return -1; ++ } ++ pCNX = &g_pCnxInfo[cnx_id]; ++ preq_data->p = p; ++ preq_data->size = size & 0xFFFF; ++ preq_data->data_cat = data_cat & 0x3; ++ preq_data->p2 = p2; ++ list_add_tail(&preq_data->list, &pCNX->wdata_queue); ++ pCNX->wdata_queue_size++; ++ return 0; ++} ++ ++static int _drv_swtoe_tx_pump_skb(int cnx_id, struct sk_buff *skb) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ sstoe_tx_desc_t* pDesc = NULL; ++ int nr_frags = skb_shinfo(skb)->nr_frags; ++ int i; ++ int len = 0; ++ u16 write; ++ u16 depth; ++ void** pRTF = NULL; ++ ++ if (_drv_swtoe_tx_avail(cnx_id, nr_frags + 1)) ++ { ++ return 0; ++ } ++ ++ pCNX = &g_pCnxInfo[cnx_id]; ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ write = pTXQ_IPC->write; ++ depth = pTXQ_IPC->depth; ++ pDesc = &(pCNX->tx_desc[write]); ++ pRTF = &pCNX->RTF[write]; ++ ++ Chip_Flush_Cache_Range((size_t)skb->data, skb_headlen(skb)); ++ pDesc->buf_size = skb_headlen(skb); ++ pDesc->buf_addr = VIRT2BUS(skb->data); ++ pDesc->eof = 0; ++ *pRTF = 0; ++ pDesc->hw_own = 1; ++ write++; ++ if (write >= depth) ++ { ++ write = 0; ++ } ++ len += pDesc->buf_size; ++ ++ for (i = 0; i < nr_frags; i++) ++ { ++ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; ++ pDesc = &(pCNX->tx_desc[write]); ++ pRTF = &pCNX->RTF[write]; ++ ++ if (pDesc->hw_own) ++ { ++ panic("[%s][%d] should not happen. no descriptor space for skb\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ Chip_Flush_Cache_Range((size_t)skb_frag_address(frag), skb_frag_size(frag)); ++ pDesc->buf_size = skb_frag_size(frag); ++ pDesc->buf_addr = VIRT2BUS(skb_frag_address(frag)); ++ pDesc->eof = 0; ++ *pRTF = 0; ++ pDesc->hw_own = 1; ++ write++; ++ if (write >= depth) ++ { ++ write = 0; ++ } ++ len += pDesc->buf_size; ++ } ++ pDesc->eof = 1; ++ SANITY_DESC_LX_PRIVATE(skb); ++ *pRTF = (void*)skb; ++ ++ pTXQ_IPC->write = write; ++ Chip_Flush_MIU_Pipe(); ++ if (len > pTXQ_IPC->pkt_size) ++ { ++ panic("[%s][%d] TX packet size exceed max TX packet size (%d, %d)\n", __FUNCTION__, __LINE__, len, pTXQ_IPC->pkt_size); ++ return -1; ++ } ++ return nr_frags + 1; ++} ++ ++static int _drv_swtoe_tx_pump_iov_page(int cnx_id, char* p, int size, void* p2) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ sstoe_tx_desc_t* pDesc = NULL; ++ u16 write; ++ u16 depth; ++ void** pRTF; ++ ++ if (_drv_swtoe_tx_avail(cnx_id, 1)) ++ { ++ return 0; ++ } ++ pCNX = &g_pCnxInfo[cnx_id]; ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ if (size > pTXQ_IPC->pkt_size) ++ { ++ panic("[%s][%d] TX packet size exceed max TX packet size (%d, %d)\n", __FUNCTION__, __LINE__, size, pTXQ_IPC->pkt_size); ++ return 0; ++ } ++ Chip_Flush_Cache_Range((size_t)p, size); ++ ++ write = pTXQ_IPC->write; ++ depth = pTXQ_IPC->depth; ++ ++ pDesc = &(pCNX->tx_desc[write]); ++ pRTF = &pCNX->RTF[write]; ++ pDesc->buf_size = size; ++ pDesc->buf_addr = VIRT2BUS(p); ++ pDesc->eof = 1; ++ if (pDesc->buf_size != size) ++ { ++ panic("[%s][%d] (desc size, data size) = (0x%08x, 0x%8x)\n", __FUNCTION__, __LINE__, pDesc->buf_size, size); ++ } ++ ++ SANITY_DESC_LX_PRIVATE(p2); ++ *pRTF = (void*)((p2) ? (long)(p2) | 0x1 : 0); ++ pDesc->hw_own = 1; ++ Chip_Flush_MIU_Pipe(); ++ ++ write++; ++ if (write >= depth) ++ { ++ write = 0; ++ } ++ pTXQ_IPC->write = write; ++ return 1; ++} ++ ++int drv_swtoe_tx_pump(int cnx_id) ++{ ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ int ipc_ret; ++ int prot; ++ struct list_head *p_list, *p_list_tmp; ++ prequeue_data *preq_data; ++ int nDesc, nPump; ++ ++ CNX_SANITY(cnx_id); ++ pCNX = &g_pCnxInfo[cnx_id]; ++ ++ if (list_empty(&pCNX->wdata_queue)) ++ { ++ return 0; ++ } ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ prot = pTXQ_IPC->prot; ++ ++ nPump = 0; ++ list_for_each_safe(p_list, p_list_tmp, &pCNX->wdata_queue) ++ { ++ preq_data = list_entry(p_list, prequeue_data, list); ++ // nDesc = (DRV_SWTOE_PROT_BYPASS == prot) ? _drv_swtoe_tx_pump_skb(cnx_id, (struct sk_buff*)preq_data->p) : _drv_swtoe_tx_pump_iov(cnx_id, preq_data->p, preq_data->size); ++ switch (preq_data->data_cat) ++ { ++ case SWTOE_TX_SEND_SKB: ++ nDesc = _drv_swtoe_tx_pump_skb(cnx_id, (struct sk_buff*)preq_data->p); ++ break; ++ case SWTOE_TX_SEND_IOV: ++ case SWTOE_TX_SEND_PAGE: ++ nDesc = _drv_swtoe_tx_pump_iov_page(cnx_id, preq_data->p, preq_data->size, preq_data->p2); ++ break; ++ default: ++ printk("[%s][%d] unknown data catagory %d\n", __FUNCTION__, __LINE__, preq_data->data_cat); ++ break; ++ } ++ if (!nDesc) ++ { ++ break; ++ } ++ nPump += nDesc; ++ list_del(&preq_data->list); ++ kfree(preq_data); ++ pCNX->wdata_queue_size--; ++ } ++ if (nPump) ++ { ++ if ((ipc_ret = drv_swtoe_glue_invoke(SWTOE_IPC_ARG1_TXQ_PUT, cnx_id, 0))) ++ { ++ printk("[%s][%d] IPC SWTOE_IPC_ARG1_TXQ_PUT fail. (cnx_id, ret) = (%d, %d)\n", __FUNCTION__, __LINE__, cnx_id, ipc_ret); ++ } ++ return -1; ++ } ++ return 0; ++} ++ ++int drv_swtoe_tx_send(int cnx_id, void* p, int size, int offset, int data_cat) ++{ ++ int copy = 0; ++ struct iov_iter *iov = NULL; ++ sstoe_cnx_info* pCNX = NULL; ++ sstoe_ipc_txq_info* pTXQ_IPC = NULL; ++ void* p1 = NULL; ++ ++ CNX_SANITY(cnx_id); ++ pCNX = &g_pCnxInfo[cnx_id]; ++ pTXQ_IPC = &g_pIpcInfo->txq_info[cnx_id]; ++ ++ drv_swtoe_tx_pump(cnx_id); ++ ++ if (MAX_CNX_WDATA_QUEUE_SIZE <= pCNX->wdata_queue_size) ++ { ++ return 0; ++ } ++ if (SWTOE_TX_SEND_SKB == data_cat) ++ { ++ if (_drv_swtoe_txq_preput(cnx_id, p, 0, SWTOE_TX_SEND_SKB, 0)) ++ { ++ printk("[%s][%d] _drv_swtoe_txq_preput fail\n", __FUNCTION__, __LINE__); ++ goto jmp_err; ++ } ++ CNX_PERF_TXQ_UNDERRUN(cnx_id); ++ return 1; ++ } ++ ++ TX_MEM_INFO_DUMP(); ++ CNX_DUMP(cnx_id); ++ ++ if (SWTOE_TX_SEND_IOV == data_cat) ++ { ++ iov = (struct iov_iter*)p; ++ copy = min_t(size_t, iov_iter_count(iov), MAX_TXQ_DATA_SIZE); ++ TX_MEM_ALLOC_INC(); ++ if (NULL == (p1 = SWTOE_MALLOC(copy))) ++ { ++ printk("[%s][%d] allocate %d bytes fail\n", __FUNCTION__, __LINE__, copy); ++ return 0; ++ } ++ if (copy != copy_from_iter(p1, copy, iov)) ++ { ++ printk("[%s][%d] copy_from_iter. what happen\n", __FUNCTION__, __LINE__); ++ goto jmp_err; ++ } ++ if (_drv_swtoe_txq_preput(cnx_id, p1, copy, SWTOE_TX_SEND_IOV, 0)) ++ { ++ printk("[%s][%d] _drv_swtoe_txq_preput fail\n", __FUNCTION__, __LINE__); ++ goto jmp_err; ++ } ++ CNX_PERF_TXQ_UNDERRUN(cnx_id); ++ return copy; ++ } ++ if (SWTOE_TX_SEND_PAGE == data_cat) ++ { ++ struct page *pge = (struct page*)p; ++ ++ copy = min_t(size_t, size, MAX_TXQ_DATA_SIZE); ++ p1 = page_address(pge) + offset; ++ if (_drv_swtoe_txq_preput(cnx_id, p1, copy, SWTOE_TX_SEND_PAGE, (void*)pge)) ++ { ++ printk("[%s][%d] _drv_swtoe_txq_preput fail\n", __FUNCTION__, __LINE__); ++ goto jmp_err; ++ } ++ get_page(pge); ++ CNX_PERF_TXQ_UNDERRUN(cnx_id); ++ return copy; ++ } ++ return copy; ++jmp_err: ++ if (p1) ++ { ++ SWTOE_FREE(p1); ++ // kfree(p1); ++ } ++ return 0; ++} +diff --git a/drivers/sstar/usb/Kconfig b/drivers/sstar/usb/Kconfig +new file mode 100755 +index 000000000000..775eb8cfda00 +--- /dev/null ++++ b/drivers/sstar/usb/Kconfig +@@ -0,0 +1,3 @@ ++config MS_USB_OLD_PLATFORM ++ tristate "USB support for platform" ++ depends on CONFIG_USB_SUPPORT +diff --git a/drivers/sstar/usb/gadget/udc/usb20/Kconfig b/drivers/sstar/usb/gadget/udc/usb20/Kconfig +new file mode 100755 +index 000000000000..0cf4b340f6e3 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/Kconfig +@@ -0,0 +1,25 @@ ++config USB_GADGET_SSTAR_DEVICE ++ tristate "Sstar USB 2.0 Device Controller" ++ help ++ Sstar USB device ++ ++config USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET ++ boolean "Avoid short packet in bulk out with DMA for ethernet" ++ depends on USB_GADGET_SSTAR_DEVICE ++ ++config USB_DEBUG_MESSAGE ++ boolean "Enable debug messages" ++ depends on USB_GADGET_SSTAR_DEVICE ++ ++config USB_FPGA_VERIFICATION ++ boolean "FPGA verification only" ++ depends on USB_GADGET_SSTAR_DEVICE ++ ++config USB_CHARGER_DETECT ++ boolean "Charger detection" ++ depends on USB_GADGET_SSTAR_DEVICE ++ #default y ++config USB_ENABLE_UPLL ++ boolean "Enable clock for controller" ++ depends on USB_GADGET_SSTAR_DEVICE ++ +diff --git a/drivers/sstar/usb/gadget/udc/usb20/Makefile b/drivers/sstar/usb/gadget/udc/usb20/Makefile +new file mode 100755 +index 000000000000..a71fc8b3e908 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/Makefile +@@ -0,0 +1,12 @@ ++# ++# Makefile for SStar USB device drivers. ++# ++ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++EXTRA_CFLAGS += -I$(srctree)/drivers/sstar/usb/gadget/udc/usb20/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -I$(srctree)/drivers/sstar/usb/gadget/udc/usb20/include ++EXTRA_CFLAGS += -I$(srctree)/drivers/usb/gadget/udc ++ ++obj-$(CONFIG_USB_GADGET_SSTAR_DEVICE) = udc-msb250x.o ++udc-msb250x-y := src/msb250x_gadget.o src/msb250x_dma.o src/msb250x_ep.o src/msb250x_udc.o +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/infinity5/msb250x_udc_common.h b/drivers/sstar/usb/gadget/udc/usb20/include/infinity5/msb250x_udc_common.h +new file mode 100755 +index 000000000000..f5f88f2daab2 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/infinity5/msb250x_udc_common.h +@@ -0,0 +1,99 @@ ++#ifndef MSB250X_MEMORY_H ++#define MSB250X_MEMORY_H ++ ++#define RIU_BASE_ADDR 0xFD000000 ++#define UTMI_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142100) ++#define USBC_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142300) ++#define OTG0_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142500) ++ ++#define MIU0_BASE_ADDR 0x20000000 ++#define MIU1_BASE_ADDR 0xA0000000 ++ ++#define MIU0_SIZE ((unsigned long) 0x10000000) ++#define MIU1_SIZE ((unsigned long) 0x20000000) ++ ++#define MIU0_BUS_BASE_ADDR ((unsigned long) 0x00000000) ++#define MIU1_BUS_BASE_ADDR ((unsigned long) 0x80000000) ++ ++#define USB_MIU_SEL0 ((u8) 0x70U) ++#define USB_MIU_SEL1 ((u8) 0xe8U) ++#define USB_MIU_SEL2 ((u8) 0xefU) ++#define USB_MIU_SEL3 ((u8) 0xefU) ++ ++#define MSB250X_MAX_ENDPOINTS 8 ++#define MSB250X_USB_DMA_CHANNEL 3 ++ ++#define ENABLE_OTG_USB_NEW_MIU_SLE 1 ++ ++#define MSB250X_EPS_CAP(_dev, _ep_op) \ ++ .ep[0] = { \ ++ .ep = { \ ++ .name = ep0name, \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[1] = { \ ++ .ep = { \ ++ .name = "ep1", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[2] = { \ ++ .ep = { \ ++ .name = "ep2", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[3] = { \ ++ .ep = { \ ++ .name = "ep3", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[4] = { \ ++ .ep = { \ ++ .name = "ep4", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[5] = { \ ++ .ep = { \ ++ .name = "ep5", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[6] = { \ ++ .ep = { \ ++ .name = "ep6", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[7] = { \ ++ .ep = { \ ++ .name = "ep7", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ } ++ ++#define MSB250X_HIGH_BANDWIDTH_EP(_dev) &((_dev)->ep[7].ep) ++ ++#define MSB250X_PA2BUS(a) ((MIU1_BASE_ADDR > a)? (MIU0_BUS_BASE_ADDR | (a - MIU0_BASE_ADDR)) : (MIU1_BUS_BASE_ADDR + (a - MIU1_BASE_ADDR))) ++#define MSB250X_BUS2PA(a) ((MIU1_BUS_BASE_ADDR > a)? ((a - MIU0_BUS_BASE_ADDR) + MIU0_BASE_ADDR) : ((a - MIU1_BUS_BASE_ADDR) + MIU1_BASE_ADDR)) ++ ++#endif +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/infinity6/msb250x_udc_common.h b/drivers/sstar/usb/gadget/udc/usb20/include/infinity6/msb250x_udc_common.h +new file mode 100755 +index 000000000000..10b6ba4472b8 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/infinity6/msb250x_udc_common.h +@@ -0,0 +1,65 @@ ++#ifndef MSB250X_MEMORY_H ++#define MSB250X_MEMORY_H ++ ++#define RIU_BASE_ADDR 0xFD000000 ++#define UTMI_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142100) ++#define USBC_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142300) ++#define OTG0_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142500) ++ ++#define MIU0_BASE_ADDR 0x20000000 ++ ++#define MIU0_SIZE ((unsigned long) 0x10000000) ++ ++#define MIU0_BUS_BASE_ADDR ((unsigned long) 0x00000000) ++#define MIU1_BUS_BASE_ADDR ((unsigned long) 0x80000000) ++ ++#define USB_MIU_SEL0 ((u8) 0x70U) ++#define USB_MIU_SEL1 ((u8) 0xefU) ++#define USB_MIU_SEL2 ((u8) 0xefU) ++#define USB_MIU_SEL3 ((u8) 0xefU) ++ ++#define MSB250X_MAX_ENDPOINTS 4 ++#define MSB250X_USB_DMA_CHANNEL 3 ++ ++#define ENABLE_OTG_USB_NEW_MIU_SLE 1 ++ ++#define MSB250X_EPS_CAP(_dev, _ep_op) \ ++ .ep[0] = { \ ++ .ep = { \ ++ .name = ep0name, \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[1] = { \ ++ .ep = { \ ++ .name = "ep1", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[2] = { \ ++ .ep = { \ ++ .name = "ep2", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[3] = { \ ++ .ep = { \ ++ .name = "ep3", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ } ++ ++#define MSB250X_HIGH_BANDWIDTH_EP(_dev) &((_dev)->ep[1].ep) ++ ++#define MSB250X_PA2BUS(a) (MIU0_BUS_BASE_ADDR | (a - MIU0_BASE_ADDR)) ++#define MSB250X_BUS2PA(a) ((a - MIU0_BUS_BASE_ADDR) + MIU0_BASE_ADDR) ++ ++#endif +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/infinity6b0/msb250x_udc_common.h b/drivers/sstar/usb/gadget/udc/usb20/include/infinity6b0/msb250x_udc_common.h +new file mode 100644 +index 000000000000..10b6ba4472b8 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/infinity6b0/msb250x_udc_common.h +@@ -0,0 +1,65 @@ ++#ifndef MSB250X_MEMORY_H ++#define MSB250X_MEMORY_H ++ ++#define RIU_BASE_ADDR 0xFD000000 ++#define UTMI_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142100) ++#define USBC_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142300) ++#define OTG0_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142500) ++ ++#define MIU0_BASE_ADDR 0x20000000 ++ ++#define MIU0_SIZE ((unsigned long) 0x10000000) ++ ++#define MIU0_BUS_BASE_ADDR ((unsigned long) 0x00000000) ++#define MIU1_BUS_BASE_ADDR ((unsigned long) 0x80000000) ++ ++#define USB_MIU_SEL0 ((u8) 0x70U) ++#define USB_MIU_SEL1 ((u8) 0xefU) ++#define USB_MIU_SEL2 ((u8) 0xefU) ++#define USB_MIU_SEL3 ((u8) 0xefU) ++ ++#define MSB250X_MAX_ENDPOINTS 4 ++#define MSB250X_USB_DMA_CHANNEL 3 ++ ++#define ENABLE_OTG_USB_NEW_MIU_SLE 1 ++ ++#define MSB250X_EPS_CAP(_dev, _ep_op) \ ++ .ep[0] = { \ ++ .ep = { \ ++ .name = ep0name, \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[1] = { \ ++ .ep = { \ ++ .name = "ep1", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[2] = { \ ++ .ep = { \ ++ .name = "ep2", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[3] = { \ ++ .ep = { \ ++ .name = "ep3", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ } ++ ++#define MSB250X_HIGH_BANDWIDTH_EP(_dev) &((_dev)->ep[1].ep) ++ ++#define MSB250X_PA2BUS(a) (MIU0_BUS_BASE_ADDR | (a - MIU0_BASE_ADDR)) ++#define MSB250X_BUS2PA(a) ((a - MIU0_BUS_BASE_ADDR) + MIU0_BASE_ADDR) ++ ++#endif +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/infinity6e/msb250x_udc_common.h b/drivers/sstar/usb/gadget/udc/usb20/include/infinity6e/msb250x_udc_common.h +new file mode 100755 +index 000000000000..840de2625766 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/infinity6e/msb250x_udc_common.h +@@ -0,0 +1,69 @@ ++#ifndef MSB250X_MEMORY_H ++#define MSB250X_MEMORY_H ++ ++#define GET_REG_ADDR(x, y) ((x) + ((y) << 2)) ++#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) ++ ++#define RIU_BASE 0xFD200000 ++#define UTMI_BASE_ADDR GET_BASE_ADDR_BY_BANK(RIU_BASE, 0x42100) ++#define USBC_BASE_ADDR GET_BASE_ADDR_BY_BANK(RIU_BASE, 0x42300) ++#define OTG0_BASE_ADDR GET_BASE_ADDR_BY_BANK(RIU_BASE, 0x42500) ++ ++#define MIU0_BASE_ADDR 0x20000000 ++ ++#define MIU0_SIZE ((unsigned long) 0x10000000) ++ ++#define MIU0_BUS_BASE_ADDR ((unsigned long) 0x00000000) ++#define MIU1_BUS_BASE_ADDR ((unsigned long) 0x80000000) ++ ++#define USB_MIU_SEL0 ((u8) 0x70U) ++#define USB_MIU_SEL1 ((u8) 0xefU) ++#define USB_MIU_SEL2 ((u8) 0xefU) ++#define USB_MIU_SEL3 ((u8) 0xefU) ++ ++ ++#define MSB250X_MAX_ENDPOINTS 4 ++#define MSB250X_USB_DMA_CHANNEL 3 ++ ++#define ENABLE_OTG_USB_NEW_MIU_SLE 1 ++ ++#define MSB250X_EPS_CAP(_dev, _ep_op) \ ++ .ep[0] = { \ ++ .ep = { \ ++ .name = ep0name, \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[1] = { \ ++ .ep = { \ ++ .name = "ep1", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[2] = { \ ++ .ep = { \ ++ .name = "ep2", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ }, \ ++ .ep[3] = { \ ++ .ep = { \ ++ .name = "ep3", \ ++ .ops = _ep_op, \ ++ .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL), \ ++ }, \ ++ .dev = _dev, \ ++ } ++ ++#define MSB250X_HIGH_BANDWIDTH_EP(_dev) &((_dev)->ep[1].ep) ++ ++#define MSB250X_PA2BUS(a) (MIU0_BUS_BASE_ADDR | (a - MIU0_BASE_ADDR)) ++#define MSB250X_BUS2PA(a) ((a - MIU0_BUS_BASE_ADDR) + MIU0_BASE_ADDR) ++ ++#endif +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_dma.h b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_dma.h +new file mode 100755 +index 000000000000..dd06581d5567 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_dma.h +@@ -0,0 +1,71 @@ ++/* SigmaStar trade secret */ ++/* ++* ms_dma.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef __MSB250X_DMA_H ++#define __MSB250X_DMA_H ++ ++#if 0 ++#include ++#include ++#include ++#if defined( CONFIG_ARM ) ++//#include ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++//#include ++#include ++ ++#include ++#include ++#include ++ ++#include "msb250x_udc.h" ++#include "msb250x_udc_reg.h" ++#endif ++ ++u8 msb250x_dma_find_channel_by_ep(u8 ep_num); ++ ++void msb250x_dma_release_channel(s8 ch); ++ ++int msb250x_dma_setup_control(struct usb_ep *_ep, ++ struct msb250x_request *req, ++ u32 bytes); ++ ++void msb250x_dma_isr_handler(u8 ch, ++ struct msb250x_udc *dev); ++ ++#endif +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_ep.h b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_ep.h +new file mode 100755 +index 000000000000..514ad5b4519a +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_ep.h +@@ -0,0 +1,64 @@ ++#ifndef __MSB250X_EP_H ++#define __MSB250X_EP_H ++/****************************************************************************** ++ * Function definition ++ ******************************************************************************/ ++ ++static inline void ep_set_ipr(u8 ep_num) ++{ ++ ms_writeb((ms_readb(MSB250X_OTG0_EP_TXCSR1_REG(ep_num)) | MSB250X_OTG0_TXCSR1_TXPKTRDY), MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++} ++ ++static inline void ep_set_opr(u8 ep_num) ++{ ++ ms_writeb((ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)) & ~MSB250X_OTG0_RXCSR1_RXPKTRDY), MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++} ++ ++void msb250x_ep0_clear_opr(void); ++ ++void msb250x_ep0_clear_sst(void); ++ ++void msb250x_ep0_clear_se(void); ++ ++void msb250x_ep0_set_ipr(void); ++ ++void msb250x_ep0_set_de(void); ++ ++void msb250x_ep0_set_ss(void); ++ ++void msb250x_ep0_clr_opr_set_ss(void); ++ ++void msb250x_ep0_set_de_out(void); ++ ++void msb250x_ep0_set_sse_out(void); ++ ++void msb250x_ep0_set_de_in(void); ++ ++int msb250x_ep_enable(struct usb_ep *_ep, const ++ struct usb_endpoint_descriptor *desc); ++ ++int msb250x_ep_disable(struct usb_ep *_ep); ++ ++struct usb_request* ++msb250x_ep_alloc_request(struct usb_ep *_ep, ++ gfp_t gfp_flags); ++ ++void msb250x_ep_free_request(struct usb_ep *_ep, ++ struct usb_request *_req); ++ ++int msb250x_ep_queue(struct usb_ep *_ep, ++ struct usb_request *_req, ++ gfp_t gfp_flags); ++ ++int msb250x_ep_dequeue(struct usb_ep *_ep, ++ struct usb_request *_req); ++ ++int msb250x_ep_set_halt(struct usb_ep *_ep, ++ int value); ++ ++void msb250x_ep0_isr_handler(struct msb250x_udc *dev); ++ ++void msb250x_ep_isr_handler(struct msb250x_udc* dev, ++ struct msb250x_ep *ep); ++ ++#endif +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_gadget.h b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_gadget.h +new file mode 100755 +index 000000000000..42c5c374d206 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_gadget.h +@@ -0,0 +1,38 @@ ++#ifndef __MSB250X_GAGET_H ++#define __MSB250X_GAGET_H ++ ++void msb250x_gadget_sync_request(struct usb_gadget* gadget, struct usb_request* req, int offset, int size); ++ ++int msb250x_gadget_map_request(struct usb_gadget* gadget, struct usb_request* req, int is_in); ++ ++void msb250x_gadget_unmap_request(struct usb_gadget* gadget, struct usb_request* req, int is_in); ++ ++void msb250x_gadget_pullup_i(int is_on); ++ ++int msb250x_gadget_get_frame(struct usb_gadget *g); ++ ++struct usb_ep* ++msb250x_gadget_match_ep(struct usb_gadget *g, ++ struct usb_endpoint_descriptor *desc, ++ struct usb_ss_ep_comp_descriptor *ep_comp); ++ ++int msb250x_gadget_wakeup(struct usb_gadget *_gadget); ++ ++int msb250x_gadget_set_selfpowered(struct usb_gadget *g, ++ int value); ++ ++int msb250x_gadget_pullup(struct usb_gadget *g, ++ int is_on); ++ ++int msb250x_gadget_vbus_session(struct usb_gadget *g, ++ int is_active); ++ ++int msb250x_gadget_vbus_draw(struct usb_gadget *g, ++ unsigned ma); ++ ++int msb250x_gadget_udc_start(struct usb_gadget *g, ++ struct usb_gadget_driver *driver); ++ ++int msb250x_gadget_udc_stop(struct usb_gadget *g); ++ ++#endif +\ No newline at end of file +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_udc.h b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_udc.h +new file mode 100755 +index 000000000000..535420dc64fc +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_udc.h +@@ -0,0 +1,169 @@ ++/* SigmaStar trade secret */ ++/* ++* msb250x_udc.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ PROJECT: MSB250x Linux BSP ++ DESCRIPTION: ++ MSB250x dual role USB device controllers ++ ++ ++ HISTORY: ++ 6/11/2010 Calvin Hung First Revision ++ ++-------------------------------------------------------------------------------*/ ++#ifndef __MSB250X_UDC_H ++#define __MSB250X_UDC_H ++ ++/****************************************************************************** ++ * Include Files ++ ******************************************************************************/ ++#include ++#include ++#include ++//#include "msb250x_udc_common.h" ++/****************************************************************************** ++ * Constants ++ ******************************************************************************/ ++#define USB_HIGH_SPEED 1 ++#define QC_BOARD 1 ++#define EP0_FIFO_SIZE 64 ++#define EP_FIFO_SIZE 512 ++ ++#define ms_readb(a) readb((void*)(a)) ++#define ms_writeb(v, a) writeb((v), (void*)(a)) ++ ++#define ms_readw(a) readw((void*)(a)) ++#define ms_writew(v, a) writew((v), (void*)(a)) ++ ++#define ms_writesb(v, a, l) ({ \ ++ prefetch((void*)(v)); \ ++ writesb((volatile void *)(a), (void *)(v), (l)); \ ++ }) ++ ++#define ms_readsb(v, a, l) readsb((const volatile void*)(a), (void*)(v), (l)) ++#if 1 ++#define ms_writelw(v, a) ms_writew((v & 0xffff), (a)); \ ++ ms_writew(((v >> 16) & 0xffff), ((volatile u32*)(a) + 1)); ++#define ms_readlw(a) (volatile u32)((ms_readw((a)) & 0xffff) | (ms_readw(((volatile u32*)(a) + 1)) << 16)); ++#endif ++/****************************************************************************** ++ * Variables ++ ******************************************************************************/ ++enum ep0_state ++{ ++ EP0_IDLE, ++ EP0_IN_DATA_PHASE, ++ EP0_OUT_DATA_PHASE, ++}; ++ ++struct msb250x_ep ++{ ++ struct list_head queue; ++ struct usb_gadget *gadget; ++ struct msb250x_udc *dev; ++ struct usb_ep ep; ++ ++ unsigned short fifo_size; ++ u8 autoNAK_cfg; ++ u8 halted : 1; ++ u8 already_seen : 1; ++ u8 setup_stage : 1; ++ u8 shortPkt : 1; ++ u8 zero : 1; ++}; ++ ++struct msb250x_request ++{ ++ struct list_head queue; /* ep's requests */ ++ struct usb_request req; ++}; ++ ++struct msb250x_udc ++{ ++ spinlock_t lock; ++ ++ struct msb250x_ep ep[MSB250X_MAX_ENDPOINTS]; ++ struct usb_gadget gadget; ++ struct usb_gadget_driver *driver; ++ struct msb250x_request fifo_req; ++ struct platform_device *pdev; ++ u16 devstatus; ++ int address; ++ enum ep0_state ep0state; ++ unsigned got_irq : 1; ++ unsigned req_std : 1; ++ unsigned delay_status : 1; ++ unsigned req_pending : 1; ++ unsigned soft_conn : 1; ++ unsigned using_dma : 1; ++}; ++ ++/* --------------------- container_of ops ----------------------------------*/ ++static inline struct msb250x_ep *to_msb250x_ep(struct usb_ep *ep) ++{ ++ return container_of(ep, struct msb250x_ep, ep); ++} ++ ++static inline struct msb250x_udc *to_msb250x_udc(struct usb_gadget *gadget) ++{ ++ return container_of(gadget, struct msb250x_udc, gadget); ++} ++ ++static inline struct msb250x_request *to_msb250x_req(struct usb_request *req) ++{ ++ return container_of(req, struct msb250x_request, req); ++} ++ ++static inline void msb250x_set_ep_halt(struct msb250x_ep* ep, int value) ++{ ++ ep->halted = value; ++} ++ ++/* -----------------------------------------------------------*/ ++ ++int msb250x_udc_get_autoNAK_cfg(u8 ep_num); ++ ++int msb250x_udc_release_autoNAK_cfg(u8 cfg); ++ ++void msb250x_udc_enable_autoNAK(u8 ep_num, u8 cfg); ++void msb250x_udc_ok2rcv_for_packets(u8 cfg, u16 pkt_num); ++void msb250x_udc_allowAck(u8 cfg); ++ ++void msb250x_request_nuke(struct msb250x_udc *udc, ++ struct msb250x_ep *ep, int status); ++ ++void msb250x_request_continue(struct msb250x_ep *ep); ++ ++void msb250x_request_done(struct msb250x_ep *ep, ++ struct msb250x_request *req, ++ int status); ++ ++struct msb250x_request* ++msb250x_request_handler(struct msb250x_ep* ep, ++ struct msb250x_request* req); ++ ++int msb250x_udc_get_status(struct msb250x_udc *dev, ++ struct usb_ctrlrequest *crq); ++void msb250x_udc_deinit_utmi(void); ++void msb250x_udc_init_utmi(void); ++void msb250x_udc_init_usb_ctrl(void); ++void msb250x_udc_reset_otg(void); ++void msb250x_udc_init_otg(struct msb250x_udc *udc); ++ ++ ++#endif /* __MSB250X_UDC_H */ +diff --git a/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_udc_reg.h b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_udc_reg.h +new file mode 100755 +index 000000000000..863508d3e84b +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/include/msb250x_udc_reg.h +@@ -0,0 +1,482 @@ ++/* SigmaStar trade secret */ ++/* ++* msb250x_udc_reg.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++/*------------------------------------------------------------------------------ ++ PROJECT: MSB250x Linux BSP ++ DESCRIPTION: ++ MSB250x dual role USB device controllers ++ ++ ++ HISTORY: ++ 6/11/2010 Calvin Hung First Revision ++-------------------------------------------------------------------------------*/ ++#ifndef _MSB250X_OTG0_REG_H ++#define _MSB250X_OTG0_REG_H ++ ++#include "msb250x_udc_common.h" ++ ++#define GET_REG16_ADDR(x, y) ((x) + ((y) << 2)) ++#define GET_REG8_ADDR(x, y) ((x) + ((y) << 1) - ((y) & 1)) ++ ++//#define RIU_BASE_ADDR 0xFD000000 ++//#define UTMI_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142100) ++//#define USBC_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142300) ++//#define OTG0_BASE_ADDR GET_REG8_ADDR(RIU_BASE_ADDR, 0x142500) ++ ++#define CPU_OFF_SHIFT 0 /* 16 bit */ ++ ++#ifndef BIT0 ++#define BIT0 0x0001 ++#define BIT1 0x0002 ++#define BIT2 0x0004 ++#define BIT3 0x0008 ++#define BIT4 0x0010 ++#define BIT5 0x0020 ++#define BIT6 0x0040 ++#define BIT7 0x0080 ++#define BIT8 0x0100 ++#define BIT9 0x0200 ++#define BIT10 0x0400 ++#define BIT11 0x0800 ++#define BIT12 0x1000 ++#define BIT13 0x2000 ++#define BIT14 0x4000 ++#define BIT15 0x8000 ++#endif ++ ++/* 00h ~ 0Fh */ ++#define MSB250X_OTG0_FADDR_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x00) ++#define MSB250X_OTG0_PWR_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x01) ++#define MSB250X_OTG0_INTRTX_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x02) ++/* 03h reserved */ ++#define MSB250X_OTG0_INTRRX_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x04) ++/* 05h reserved */ ++#define MSB250X_OTG0_INTRTXE_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x06) ++/* 07h reserved */ ++#define MSB250X_OTG0_INTRRXE_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x08) ++/* 09h reserved */ ++#define MSB250X_OTG0_INTRUSB_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x0A) ++#define MSB250X_OTG0_INTRUSBE_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x0B) ++#define MSB250X_OTG0_FRAME_L_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x0C) ++#define MSB250X_OTG0_FRAME_H_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x0D) ++#define MSB250X_OTG0_INDEX_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x0E) ++#define MSB250X_OTG0_TESTMODE_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x0F) ++ ++/* 10h ~ 1Fh*/ ++#define MSB250X_OTG0_TXMAP_L_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x10) ++#define MSB250X_OTG0_TXMAP_H_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x11) ++/* 12h ~ 1Fh for EP_SEL = 0 */ ++#define MSB250X_OTG0_CSR0_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x12) ++#define MSB250X_OTG0_CSR0_FLSH_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x13) ++/* 14h ~ 17h reserved */ ++#define MSB250X_OTG0_COUNT0_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x18) ++/* 19h ~ 1Eh reserved */ ++#define MSB250X_OTG0_CONFDATA_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x1F) ++/* 12h ~ 1Fh for EP_SEL != 0 (EP1 ~ EPx) */ ++#define MSB250X_OTG0_TXCSR1_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x12) ++#define MSB250X_OTG0_TXCSR2_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x13) ++#define MSB250X_OTG0_RXMAP_L_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x14) ++#define MSB250X_OTG0_RXMAP_H_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x15) ++#define MSB250X_OTG0_RXCSR1_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x16) ++#define MSB250X_OTG0_RXCSR2_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x17) ++#define MSB250X_OTG0_RXCOUNT_L_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x18) ++#define MSB250X_OTG0_RXCOUNT_H_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x19) ++/* 1Ah ~ 1Eh reserved */ ++#define MSB250X_OTG0_FIFOSIZE_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x1F) ++ ++/* 20h ~ 5Fh*/ ++#define OTG0_EP_FIFO_ACCESS_L(x) GET_REG8_ADDR(OTG0_BASE_ADDR, (0x20 + ((x) << 2))) ++/* 40h ~ 5Fh reserved for infinity5 */ ++/* 30h ~ 5Fh reserved for infinity6 */ ++ ++/* 60h */ ++#define MSB250X_OTG0_DEVCTL_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x60) ++ ++/* 80h ~ 95h */ ++#define MSB250X_OTG0_USB_CFG0_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x80) ++#define MSB250X_OTG0_USB_CFG0_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x81) ++#define MSB250X_OTG0_USB_CFG1_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x82) ++#define MSB250X_OTG0_USB_CFG1_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x83) ++#define MSB250X_OTG0_USB_CFG2_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x84) ++#define MSB250X_OTG0_USB_CFG2_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x85) ++#define MSB250X_OTG0_USB_CFG3_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x86) ++#define MSB250X_OTG0_USB_CFG3_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x87) ++#define MSB250X_OTG0_USB_CFG4_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x88) ++#define MSB250X_OTG0_USB_CFG4_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x89) ++#define MSB250X_OTG0_USB_CFG5_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x8A) ++#define MSB250X_OTG0_USB_CFG5_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x8B) ++#define MSB250X_OTG0_USB_CFG6_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x8C) ++#define MSB250X_OTG0_USB_CFG6_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x8D) ++#define MSB250X_OTG0_USB_CFG7_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x8E) ++#define MSB250X_OTG0_USB_CFG7_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x8F) ++#define MSB250X_OTG0_USB_CFG8_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x90) ++#define MSB250X_OTG0_USB_CFG8_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x91) ++#define MSB250X_OTG0_USB_CFG9_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x92) ++#define MSB250X_OTG0_USB_CFG9_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x93) ++#define MSB250X_OTG0_USB_CFGA_L GET_REG8_ADDR(OTG0_BASE_ADDR, 0x94) ++#define MSB250X_OTG0_USB_CFGA_H GET_REG8_ADDR(OTG0_BASE_ADDR, 0x95) ++ ++/* 100h ~ 180h */ ++#define MSB250X_OTG0_EP_TXMAP_L_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x100 + ((x) << 4)) ++#define MSB250X_OTG0_EP_TXMAP_H_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x101 + ((x) << 4)) ++/* for EP_SEL = 0, 102h ~ 10Fh (EP1 ~ EPx) */ ++#define MSB250X_OTG0_EP0_CSR0_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x102) ++#define MSB250X_OTG0_EP0_CSR0_FLSH_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x103) ++/* 104h ~ 107h reserved */ ++#define MSB250X_OTG0_EP0_COUNT0_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x108) ++/* 109h ~ 10Eh reserved */ ++#define MSB250X_OTG0_EP0_CONFDATA_REG GET_REG8_ADDR(OTG0_BASE_ADDR, 0x10F) ++/* for EP_SEL != 0, 112h ~ 11Fh (EP1 ~ EPx) */ ++#define MSB250X_OTG0_EP_TXCSR1_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x102 + ((x) << 4)) ++#define MSB250X_OTG0_EP_TXCSR2_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x103 + ((x) << 4)) ++#define MSB250X_OTG0_EP_RXMAP_L_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x104 + ((x) << 4)) ++#define MSB250X_OTG0_EP_RXMAP_H_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x105 + ((x) << 4)) ++#define MSB250X_OTG0_EP_RXCSR1_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x106 + ((x) << 4)) ++#define MSB250X_OTG0_EP_RXCSR2_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x107 + ((x) << 4)) ++#define MSB250X_OTG0_EP_RXCOUNT_L_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x108 + ((x) << 4)) ++#define MSB250X_OTG0_EP_RXCOUNT_H_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x109 + ((x) << 4)) ++#define MSB250X_OTG0_EP_FIFOSIZE_REG(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x10F + ((x) << 4)) ++ ++/* 200h */ ++#define MSB250X_OTG0_DMA_INTR GET_REG8_ADDR(OTG0_BASE_ADDR, 0x200) ++#define MSB250X_OTG0_DMA_CNTL(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x204 + ((x - 1) << 4)) ++#define MSB250X_OTG0_DMA_ADDR(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x208 + ((x - 1) << 4)) ++#define MSB250X_OTG0_DMA_ADDR_LW(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x208 + ((x - 1) << 4)) ++#define MSB250X_OTG0_DMA_ADDR_HW(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x20A + ((x - 1) << 4)) ++#define MSB250X_OTG0_DMA_COUNT(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x20C + ((x - 1) << 4)) ++#define MSB250X_OTG0_DMA_COUNT_LW(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x20C + ((x - 1) << 4)) ++#define MSB250X_OTG0_DMA_COUNT_HW(x) GET_REG8_ADDR(OTG0_BASE_ADDR, 0x20E + ((x - 1) << 4)) ++ ++/* custom */ ++#define MSB250X_OTG0_INTR_EP(x) (1 << x) ++ ++#define MSB250X_OTG0_AUTONAK0_EP_BULKOUT MSB250X_OTG0_USB_CFG3_L ++#define MSB250X_OTG0_AUTONAK1_EP_BULKOUT MSB250X_OTG0_USB_CFG0_H ++#define MSB250X_OTG0_AUTONAK2_EP_BULKOUT MSB250X_OTG0_USB_CFG8_L ++ ++#define MSB250X_OTG0_AUTONAK0_RX_PKT_CNT MSB250X_OTG0_USB_CFG5_L ++#define MSB250X_OTG0_AUTONAK1_RX_PKT_CNT MSB250X_OTG0_USB_CFG1_L ++#define MSB250X_OTG0_AUTONAK2_RX_PKT_CNT MSB250X_OTG0_USB_CFG9_L ++ ++//#define MSB250X_OTG0_AUTONAK0_CTRL MSB250X_OTG0_USB_CFG5_H ++#define MSB250X_OTG0_AUTONAK0_CTRL MSB250X_OTG0_USB_CFG5_L ++#define MSB250X_OTG0_AUTONAK1_CTRL MSB250X_OTG0_USB_CFG0_H ++#define MSB250X_OTG0_AUTONAK2_CTRL MSB250X_OTG0_USB_CFG8_L ++ ++#define MSB250X_OTG0_AUTONAK0_EN 0x2000 ++#define MSB250X_OTG0_AUTONAK1_EN 0x10 ++#define MSB250X_OTG0_AUTONAK2_EN 0x0100 ++ ++#define MSB250X_OTG0_AUTONAK0_OK2Rcv 0x8000 ++#define MSB250X_OTG0_AUTONAK1_OK2Rcv 0x40 ++#define MSB250X_OTG0_AUTONAK2_OK2Rcv 0x0400 ++ ++#define MSB250X_OTG0_AUTONAK0_AllowAck 0x4000 ++#define MSB250X_OTG0_AUTONAK1_AllowAck 0x20 ++#define MSB250X_OTG0_AUTONAK2_AllowAck 0x04 ++ ++#define MSB250X_OTG0_DMA_MODE_CTL MSB250X_OTG0_USB_CFG5_L ++#define MSB250X_OTG0_DMA_MODE_CTL1 (MSB250X_OTG0_USB_CFG0_L + 1) ++ ++#define MSB250X_OTG0_CFG1_H_SHORT_ECO 0x40 ++#define MSB250X_OTG0_CFG6_H_SHORT_MODE 0x20 ++#define MSB250X_OTG0_CFG6_H_BUS_OP_FIX 0x40 ++#define MSB250X_OTG0_CFG6_H_REG_MI_WDFIFO_CTRL 0x80 ++ ++/* new mode1 in Peripheral mode */ ++#define M_Mode1_P_BulkOut_EP 0x0002 ++#define M_Mode1_P_OK2Rcv 0x8000 ++#define M_Mode1_P_AllowAck 0x4000 ++#define M_Mode1_P_Enable 0x2000 ++#define M_Mode1_P_NAK_Enable 0x2000 ++#define M_Mode1_P_NAK_Enable_1 0x10 ++#define M_Mode1_P_AllowAck_1 0x20 ++#define M_Mode1_P_OK2Rcv_1 0x40 ++ ++/* MSB250X_OTG0_PWR_REG */ /* RW */ ++#define MSB250X_OTG0_PWR_ISOUP (1 << 7) ++#define MSB250X_OTG0_PWR_SOFT_CONN (1 << 6) ++#define MSB250X_OTG0_PWR_HS_EN (1 << 5) ++#define MSB250X_OTG0_PWR_HS_MODE (1 << 4) ++#define MSB250X_OTG0_PWR_RESET (1 << 3) ++#define MSB250X_OTG0_PWR_RESUME (1 << 2) ++#define MSB250X_OTG0_PWR_SUSPEND (1 << 1) ++#define MSB250X_OTG0_PWR_ENSUSPEND (1 << 0) ++ ++/* MSB250X_OTG0_INTRUSB_REG */ /* RO */ ++#define MSB250X_OTG0_INTRUSB_VBUS_ERR (1 << 7) ++#define MSB250X_OTG0_INTRUSB_SESS_REQ (1 << 6) ++#define MSB250X_OTG0_INTRUSB_DISCONN (1 << 5) ++#define MSB250X_OTG0_INTRUSB_CONN (1 << 4) ++#define MSB250X_OTG0_INTRUSB_SOF (1 << 3) ++#define MSB250X_OTG0_INTRUSB_RESET (1 << 2) ++#define MSB250X_OTG0_INTRUSB_RESUME (1 << 1) ++#define MSB250X_OTG0_INTRUSB_SUSPEND (1 << 0) ++ ++/* MSB250X_OTG0_INTRUSBE_REG */ /* RW */ ++#define MSB250X_OTG0_INTRUSBE_VBUS_ERR (1 << 7) ++#define MSB250X_OTG0_INTRUSBE_SESS_REQ (1 << 6) ++#define MSB250X_OTG0_INTRUSBE_DISCONN (1 << 5) ++#define MSB250X_OTG0_INTRUSBE_CONN (1 << 4) ++#define MSB250X_OTG0_INTRUSBE_SOF (1 << 3) ++#define MSB250X_OTG0_INTRUSBE_RESET (1 << 2) ++#define MSB250X_OTG0_INTRUSBE_BABBLE (1 << 2) ++#define MSB250X_OTG0_INTRUSBE_RESUME (1 << 1) ++#define MSB250X_OTG0_INTRUSBE_SUSPEND (1 << 0) ++ ++/* MSB250X_OTG0_TESTMODE_REG */ /* RW */ ++#define MSB250X_OTG0_TESTMODE_FORCE_HOST (1 << 7) ++#define MSB250X_OTG0_TESTMODE_FIFO_ACCESS (1 << 6) ++#define MSB250X_OTG0_TESTMODE_FORCE_FS (1 << 5) ++#define MSB250X_OTG0_TESTMODE_FORCE_HS (1 << 4) ++#define MSB250X_OTG0_TESTMODE_TEST_PACKET (1 << 3) ++#define MSB250X_OTG0_TESTMODE_TEST_K (1 << 2) ++#define MSB250X_OTG0_TESTMODE_TEST_J (1 << 1) ++#define MSB250X_OTG0_TESTMODE_TEST_SE0_NAK (1 << 0) ++ ++/* MSB250X_OTG0_CSR0_REG */ /* RO, WO */ ++#define MSB250X_OTG0_CSR0_SSETUPEND (1 << 7) ++#define MSB250X_OTG0_CSR0_SRXPKTRDY (1 << 6) ++#define MSB250X_OTG0_CSR0_SENDSTALL (1 << 5) ++#define MSB250X_OTG0_CSR0_SETUPEND (1 << 4) ++#define MSB250X_OTG0_CSR0_DATAEND (1 << 3) ++#define MSB250X_OTG0_CSR0_SENTSTALL (1 << 2) ++#define MSB250X_OTG0_CSR0_TXPKTRDY (1 << 1) ++#define MSB250X_OTG0_CSR0_RXPKTRDY (1 << 0) ++ ++/* CSR0 in host mode */ ++#define MSB250X_OTG0_CSR0_STATUSPACKET (1 << 6) ++#define MSB250X_OTG0_CSR0_REQPACKET (1 << 5) ++#define MSB250X_OTG0_CSR0_SETUPPACKET (1 << 3) ++#define MSB250X_OTG0_CSR0_RXSTALL (1 << 2) ++ ++ ++/* MSB250X_OTG0_TXCSR1_REG */ /* RO, WO */ ++#define MSB250X_OTG0_TXCSR1_AUTOSET (1 << 15) ++#define MSB250X_OTG0_TXCSR1_MODE (1 << 13) ++#define MSB250X_OTG0_TXCSR1_DMAREQENAB (1 << 12) ++#define MSB250X_OTG0_TXCSR1_FRCDATAOG (1 << 11) ++#define MSB250X_OTG0_TXCSR1_DMAREQMODE (1 << 10) ++#define MSB250X_OTG0_TXCSR1_CLRDATAOTG (1 << 6) ++#define MSB250X_OTG0_TXCSR1_SENTSTALL (1 << 5) ++#define MSB250X_OTG0_TXCSR1_SENDSTALL (1 << 4) ++#define MSB250X_OTG0_TXCSR1_FLUSHFIFO (1 << 3) ++#define MSB250X_OTG0_TXCSR1_UNDERRUN (1 << 2) ++#define MSB250X_OTG0_TXCSR1_FIFONOEMPTY (1 << 1) ++#define MSB250X_OTG0_TXCSR1_TXPKTRDY (1 << 0) ++ ++/* host mode */ ++#define MSB250X_OTG0_TXCSR1_RXSTALL (1 << 5) ++ ++/* MSB250X_OTG0_TXCSR2_REG */ /* RW */ ++#define MSB250X_OTG0_TXCSR2_AUTOSET (1 << 7) ++#define MSB250X_OTG0_TXCSR2_ISOC (1 << 6) ++#define MSB250X_OTG0_TXCSR2_MODE (1 << 5) ++#define MSB250X_OTG0_TXCSR2_DMAREQENAB (1 << 4) ++#define MSB250X_OTG0_TXCSR2_FRCDATAOG (1 << 3) ++#define MSB250X_OTG0_TXCSR2_DMAREQMODE (1 << 2) ++ ++/* MSB250X_OTG0_RXCSR1_REG */ /* RW, RO */ ++#define MSB250X_OTG0_RXCSR1_CLRDATATOG (1 << 7) ++#define MSB250X_OTG0_RXCSR1_SENTSTALL (1 << 6) ++#define MSB250X_OTG0_RXCSR1_SENDSTALL (1 << 5) ++#define MSB250X_OTG0_RXCSR1_FLUSHFIFO (1 << 4) ++#define MSB250X_OTG0_RXCSR1_DATAERROR (1 << 3) ++#define MSB250X_OTG0_RXCSR1_OVERRUN (1 << 2) ++#define MSB250X_OTG0_RXCSR1_FIFOFULL (1 << 1) ++#define MSB250X_OTG0_RXCSR1_RXPKTRDY (1 << 0) ++ ++/* host mode */ ++#define MSB250X_OTG0_RXCSR1_RXSTALL (1 << 6) ++#define MSB250X_OTG0_RXCSR1_REQPKT (1 << 5) ++ ++/* MSB250X_OTG0_RXCSR2_REG */ /* RW */ ++#define MSB250X_OTG0_RXCSR2_AUTOCLR (1 << 7) ++#define MSB250X_OTG0_RXCSR2_ISOC (1 << 6) ++#define MSB250X_OTG0_RXCSR2_DMAREQEN (1 << 5) ++#define MSB250X_OTG0_RXCSR2_DISNYET (1 << 4) ++#define MSB250X_OTG0_RXCSR2_DMAREQMD (1 << 3) ++ ++ ++/* MSB250X_OTG0_DEVCTL_REG */ ++#define MSB250X_OTG0_B_DEVIC (1 << 7) ++#define MSB250X_OTG0_FS_DEVIC (1 << 6) ++#define MSB250X_OTG0_LS_DEVIC (1 << 5) ++#define MSB250X_OTG0_HOST_MODE (1 << 2) ++#define MSB250X_OTG0_HOST_REQ (1 << 1) ++#define MSB250X_OTG0_SESSION (1 << 0) ++ ++/* CH_DMA_CNTL */ ++#define MSB250X_OTG0_DMA_BURST_MODE (3 << 9) ++#define MSB250X_OTG0_DMA_INT_EN (1 << 3) ++#define MSB250X_OTG0_DMA_AUTO (1 << 2) ++#define MSB250X_OTG0_DMA_TX (1 << 1) ++#define MSB250X_OTG0_EN_DMA (1 << 0) ++ ++/* USB_CFG0_L */ ++#define MSB250X_OTG0_CFG0_SRST_N (1 << 0) ++ ++#define RXCSR2_MODE1 (MSB250X_OTG0_RXCSR2_AUTOCLR | MSB250X_OTG0_RXCSR2_DMAREQEN | MSB250X_OTG0_RXCSR2_DMAREQMD) ++#define TXCSR2_MODE1 (MSB250X_OTG0_TXCSR2_DMAREQENAB | MSB250X_OTG0_TXCSR2_AUTOSET | MSB250X_OTG0_TXCSR2_DMAREQMODE) ++ ++struct otg0_ep_txcsr_h { ++ __u8 bUnused: 2; ++ __u8 bDMAReqMode: 1; ++ __u8 bFrcDataTog: 1; ++ __u8 bDMAReqEnab: 1; ++ __u8 bMode: 1; ++ __u8 bISO: 1; ++ __u8 bAutoSet: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_ep_txcsr_l { ++ __u8 bTxPktRdy: 1; ++ __u8 bFIFONotEmpty: 1; ++ __u8 bUnderRun: 1; ++ __u8 bFlushFIFO: 1; ++ __u8 bSendStall: 1; ++ __u8 bSentStall: 1; ++ __u8 bClrDataTog: 1; ++ __u8 bIncompTx: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_ep_rxcsr_h { ++ __u8 bIncompRx: 1; ++ __u8 bUnused: 2; ++ __u8 bDMAReqMode: 1; ++ __u8 bDisNyet: 1; ++ __u8 bDMAReqEnab: 1; ++ __u8 bISO: 1; ++ __u8 bAutoClear: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_ep_rxcsr_l { ++ __u8 bRxPktRdy: 1; ++ __u8 bFIFOFull: 1; ++ __u8 bOverRun: 1; ++ __u8 bDataError: 1; ++ __u8 bFlushFIFO: 1; ++ __u8 bSendStall: 1; ++ __u8 bSentStall: 1; ++ __u8 bClrDataTog: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_ep0_csr_h { ++ __u8 bFlushFIF0: 1; ++ __u8 bUnused: 7; ++} __attribute__ ((packed)); ++ ++struct otg0_ep0_csr_l { ++ __u8 bRxPktRdy: 1; ++ __u8 bTxPktRdy: 1; ++ __u8 bSentStall: 1; ++ __u8 bDataEnd: 1; ++ __u8 bSetupEnd: 1; ++ __u8 bSendStall: 1; ++ __u8 bServicedRxPktRdy: 1; ++ __u8 bServicedSetupEnd: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_usb_power { ++ __u8 bEnableSuspendM: 1; ++ __u8 bSuspendMode: 1; ++ __u8 bResume: 1; ++ __u8 bReset: 1; ++ __u8 bHSMode: 1; ++ __u8 bHSEnab: 1; ++ __u8 bSoftConn: 1; ++ __u8 bISOUpdate: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_usb_intr { ++ __u8 bSuspend: 1; ++ __u8 bResume: 1; ++ __u8 bReset: 1; ++ __u8 bSOF: 1; ++ __u8 bConn: 1; ++ __u8 bDiscon: 1; ++ __u8 bSessReq: 1; ++ __u8 bVBusError: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_usb_cfg0_l { ++ __u8 bSRST_N: 1; ++ __u8 bOTG_TM_1: 1; ++ __u8 bDebugSel: 4; ++ __u8 bUSBOTG: 1; ++ __u8 bMIUPriority: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_usb_cfg0_h { ++ __u8 bEP_BULKOUT_1: 4; ++ __u8 bECO4NAK_EN_1: 1; ++ __u8 bSetAllow_ACK_1: 1; ++ __u8 bSet_OK2Rcv_1: 1; ++ __u8 bDMPullDown: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_usb_cfg6_h { ++ __u8 bDMABugFix: 1; ++ __u8 bDMAMCU_RD_Fix: 1; ++ __u8 bDMAMCU_WR_Fix: 1; ++ __u8 bINT_WR_CLR_EN: 1; ++ __u8 bMCU_HLT_DMA_EN: 1; ++ __u8 bShortMode: 1; ++ __u8 bBusOPFix: 1; ++ __u8 bREG_MI_WDFIFO_CTRL: 1; ++} __attribute__ ((packed)); ++ ++struct utmi_signal_status_l { ++ __u8 bVBUSVALID: 1; ++ __u8 bAVALID: 1; ++ __u8 bBVALID: 1; ++ __u8 bIDDIG: 1; ++ __u8 bHOSTDISCON: 1; ++ __u8 bSESSEND: 1; ++ __u8 bLINESTATE: 2; ++} __attribute__ ((packed)); ++ ++struct usbc0_rst_ctrl_l { ++ __u8 bUSB_RST: 1; ++ __u8 bUHC_RST: 1; ++ __u8 bOTG_RST: 1; ++ __u8 bREG_SUSPEND: 1; ++ __u8 bReserved0: 1; ++ __u8 bUHC_XIU_ENABLE: 1; ++ __u8 bOTG_XIU_ENABLE: 1; ++ __u8 bReserved1: 1; ++} __attribute__ ((packed)); ++ ++struct otg0_dma_ctrlrequest { ++ __u8 bEnableDMA: 1; ++ __u8 bDirection: 1; ++ __u8 bDMAMode: 1; ++ __u8 bInterruptEnable: 1; ++ __u8 bEndpointNumber: 4; ++ __u8 bBusError: 1; ++ __u8 bRurstMode: 2; ++ __u8 bReserved: 5; ++} __attribute__ ((packed)); ++ ++struct otg0_ep_tx_maxp { ++ __u16 wMaximumPayload: 11; ++ __u8 bMult: 2; ++ __u8 bUnused: 3; ++} __attribute__ ((packed)); ++ ++#endif /* _MSB250X_OTG0_REG_H */ +diff --git a/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_dma.c b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_dma.c +new file mode 100755 +index 000000000000..09d70bf43de7 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_dma.c +@@ -0,0 +1,406 @@ ++/* SigmaStar trade secret */ ++/* ++* ms_dma.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++/****************************************************************************** ++ * Include Files ++ ******************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "msb250x_udc_reg.h" ++#include "msb250x_udc.h" ++#include "msb250x_gadget.h" ++ ++#define ENABLED_DMA_BYTES 512 ++#if 0 ++static inline void ms_writelw(uintptr_t val, u32 volatile* Reg) ++{ ++ ms_writew((u32)(val & 0xffff), (uintptr_t) Reg); ++ ms_writew((u32)(val>>16), (uintptr_t) (Reg+1)); ++ //printk( "write val:%x ",(val >> 16)); ++ //printk( " *(Reg+4):%x\n",*(Reg+4)); ++} ++ ++static inline u32 ms_readlw(u32 volatile* Reg) ++{ ++ return (volatile u32) ((ms_readw((uintptr_t) Reg)&0xffff)|(ms_readw((uintptr_t) (Reg+1))<<16)); ++} ++#endif ++ ++static inline s8 msb250x_dma_get_channel(void) ++{ ++ s8 ch; ++ u16 ctrl = 0; ++ ++ struct otg0_dma_ctrlrequest* dma_ctrl = (struct otg0_dma_ctrlrequest*) &ctrl; ++ ++ for (ch = 1; ch <= MSB250X_USB_DMA_CHANNEL; ch++) ++ { ++ ctrl = ms_readw(MSB250X_OTG0_DMA_CNTL(ch)); ++ ++ if (0 == dma_ctrl->bEnableDMA && 0 == dma_ctrl->bEndpointNumber) ++ { ++ return ch; ++ } ++ ++ } ++ ++ printk("[DMA] No available channel!\n"); ++ /* cyg_semaphore_post(&ChannelDmaSem); */ ++ return -1; ++} ++ ++u8 msb250x_dma_find_channel_by_ep(u8 ep_num) ++{ ++ s8 ch = 0; ++ u16 ctrl = 0; ++ ++ struct otg0_dma_ctrlrequest* dma_ctrl = (struct otg0_dma_ctrlrequest*) &ctrl; ++ ++ for (ch = 1; ch <= MSB250X_USB_DMA_CHANNEL; ch++) ++ { ++ ctrl = ms_readw(MSB250X_OTG0_DMA_CNTL(ch)); ++ ++ if (ep_num == dma_ctrl->bEndpointNumber) ++ { ++ return ch; ++ } ++ ++ } ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(msb250x_dma_find_channel_by_ep); ++ ++void msb250x_dma_release_channel(s8 ch) ++{ ++ u8 ep_num = 0; ++ u16 ctrl = 0; ++ struct otg0_dma_ctrlrequest* dma_ctrl = (struct otg0_dma_ctrlrequest*) &ctrl; ++ ++ //ctrl = ms_readw((uintptr_t) (DMA_CNTL_REGISTER(ch))); ++ //ep_num = dma_ctrl->bEndpointNumber; ++ ++ ctrl = 0; ++ ms_writew(ctrl, MSB250X_OTG0_DMA_CNTL(ch)); ++ ctrl = ms_readw(MSB250X_OTG0_DMA_CNTL(ch)); ++ ++ if (0 != dma_ctrl->bEndpointNumber) ++ { ++ printk("[%d] DMA[%d] doesn't release!\n", ep_num, ch); ++ } ++} ++ ++EXPORT_SYMBOL(msb250x_dma_release_channel); ++ ++int msb250x_dma_setup_control(struct usb_ep *_ep, ++ struct msb250x_request *req, ++ u32 bytes) ++{ ++ s8 ch = 0; ++ u8 csr1 = 0; ++ u8 csr2 = 0; ++ ++ u16 control = 0; ++ u8 ep_num = 0; ++ ++ struct otg0_dma_ctrlrequest* dma_ctrl = (struct otg0_dma_ctrlrequest*) &control; ++ struct otg0_ep_rxcsr_h* rxcsr_h = NULL; ++ struct otg0_ep_rxcsr_l* rxcsr_l = NULL; ++ struct otg0_ep_txcsr_h* txcsr_h = NULL; ++ ++ //struct msb250x_ep *ep = to_msb250x_ep(_ep); ++ ++ ep_num = usb_endpoint_num(_ep->desc); ++ ++ dma_ctrl->bEndpointNumber = ep_num; ++ dma_ctrl->bEnableDMA = 1; ++ dma_ctrl->bInterruptEnable = 1; ++ dma_ctrl->bRurstMode = 3; ++ dma_ctrl->bDirection = usb_endpoint_dir_out(_ep->desc)? 0 : 1; ++ ++ if (usb_endpoint_xfer_bulk(_ep->desc) && _ep->maxpacket < bytes) ++ { ++ dma_ctrl->bDMAMode = 1; ++ } ++ ++ if (usb_endpoint_dir_out(_ep->desc)) // dma write ++ { ++ csr1 = ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ csr2 = ms_readb(MSB250X_OTG0_EP_RXCSR2_REG(ep_num)); ++ ++ rxcsr_l = (struct otg0_ep_rxcsr_l*) &csr1; ++ rxcsr_h = (struct otg0_ep_rxcsr_h*) &csr2; ++ ++ csr2 &= ~RXCSR2_MODE1; ++ ++ if (1 == dma_ctrl->bDMAMode) ++ { ++ csr2 |= RXCSR2_MODE1; ++ #if 0 ++ if (0 < (count % _ep->maxpacket)) ++ { ++ rxcsr_h->bDMAReqMode = 0; ++ } ++ #endif ++ rxcsr_h->bDisNyet = 1; ++ } ++ ++ } ++ else // dma read ++ { ++ txcsr_h = (struct otg0_ep_txcsr_h*) &csr2; ++ csr2 = ms_readb(MSB250X_OTG0_EP_TXCSR2_REG(ep_num)); ++ ++ csr2 &= ~TXCSR2_MODE1; ++ ++ if (1 == dma_ctrl->bDMAMode) ++ { ++ csr2 |= TXCSR2_MODE1; ++ } ++ } ++ ++ if (ENABLED_DMA_BYTES > bytes) ++ { ++ #if 0 ++ if (usb_endpoint_dir_out(_ep->desc)) ++ { ++ if (1 == rxcsr_l->bRxPktRdy) ++ { ++ printk(KERN_DEBUG "[%d][DMA] bRxPktRdy/rxcount(%d/0x%04x) buf/actual/length(0x%p/0x%04x/0x%04x)\n", ++ ep_num, rxcsr_l->bRxPktRdy, ms_readw(MSB250X_OTG0_EP_RXCOUNT_L_REG(ep_num)), req->req.buf, req->req.actual, req->req.length); ++ } ++ } ++ #endif ++ return -1; ++ } ++ ++ if (0 >= (ch = msb250x_dma_get_channel())) /* no free channel */ ++ { ++ printk("[%d][DMA] Get DMA channel fail!\n", ep_num); ++ return -1; ++ } ++ ++ ms_writeb(csr2, ((usb_endpoint_dir_out(_ep->desc))? MSB250X_OTG0_EP_RXCSR2_REG(ep_num) : MSB250X_OTG0_EP_TXCSR2_REG(ep_num))); ++#if 0 ++ ms_writelw((uintptr_t) (req->req.dma + req->req.actual), (u32 volatile*) MSB250X_OTG0_DMA_ADDR(ch)); ++ ms_writelw((uintptr_t) count, (u32 volatile*) MSB250X_OTG0_DMA_COUNT(ch)); ++#else ++ ms_writelw((req->req.dma + req->req.actual), MSB250X_OTG0_DMA_ADDR(ch)); ++ ms_writelw(bytes, MSB250X_OTG0_DMA_COUNT(ch)); ++#endif ++ ms_writew(control, MSB250X_OTG0_DMA_CNTL(ch)); ++ ++#if 0 ++ //if (usb_endpoint_dir_out(ep->ep.desc)) ++ printk(KERN_DEBUG "[%s][DMA][%d] %s mode/ctrl(0x%x/0x%04x) buff/bytes/actual/length(0x%p/0x%04x/0x%04x/0x%04x)\n", ++ _ep->name, ++ ch, ++ (usb_endpoint_dir_out(_ep->desc))? "RX" : "TX", ++ dma_ctrl->bDMAMode, ++ control, ++ req->req.buf, ++ bytes, ++ req->req.actual, ++ req->req.length); ++#endif ++ return 0; ++} ++ ++EXPORT_SYMBOL(msb250x_dma_setup_control); ++ ++void msb250x_dma_isr_handler(u8 ch, ++ struct msb250x_udc *dev) ++{ ++ int is_last = 0; ++ ++ u32 bytesleft, bytesdone, control; ++ u8 csr2 = 0,csr1 = 0; ++ dma_addr_t dma_handle; ++ u8 ep_num; ++ ++ u16 ep_maxpacket = 0; ++ ++// struct platform_device* pdev = dev->pdev; ++ struct msb250x_ep* ep; ++ struct usb_ep* _ep; ++ struct msb250x_request *req = NULL; ++ ++ struct otg0_dma_ctrlrequest* dma_ctrl = (struct otg0_dma_ctrlrequest*) &control; ++ struct otg0_ep_rxcsr_h* rxcsr_h = NULL; ++ struct otg0_ep_rxcsr_l* rxcsr_l = NULL; ++// struct ep_txcsr_h* txcsr_h = NULL; ++ struct otg0_ep_txcsr_l* txcsr_l = NULL; ++ ++ control = ms_readw(MSB250X_OTG0_DMA_CNTL(ch)); ++ dma_handle = (dma_addr_t) ms_readlw((u32 volatile*) MSB250X_OTG0_DMA_ADDR(ch)); ++ ++ bytesleft = ms_readlw((u32 volatile*) MSB250X_OTG0_DMA_COUNT(ch)); ++ ++ ep_num = dma_ctrl->bEndpointNumber; ++ ++ ep = &dev->ep[ep_num]; ++ _ep = &ep->ep; ++ msb250x_dma_release_channel(ch); ++ ++ if (!_ep->desc) ++ { ++ //printk(KERN_ERR "[%s][DMA][%d] DMA had been disabled.\n", _ep->name, ch); ++ return; ++ } ++ ++ /* release DMA channel */ ++ ++ if (likely(!list_empty(&ep->queue))) ++ { ++ req = list_entry(ep->queue.next, struct msb250x_request, queue); ++ } ++ ++ if (req) ++ { ++ bytesdone = dma_handle - req->req.dma - req->req.actual; ++ ++ if (1 == dma_ctrl->bBusError) ++ { ++ printk(KERN_ERR "[DMA] Bus ERR!\n"); ++ ++ //ep->halted = 1; /* Winder */ ++ ++ return; ++ } ++ ++ ep_maxpacket = ep->ep.maxpacket; ++ ++ if (usb_endpoint_dir_in(ep->ep.desc)) ++ { ++ csr1 = ms_readb(MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ txcsr_l = (struct otg0_ep_txcsr_l*) &csr1; ++ ++ csr2 = ms_readb(MSB250X_OTG0_EP_TXCSR2_REG(ep_num)); ++ ms_writeb((csr2 & ~TXCSR2_MODE1), MSB250X_OTG0_EP_TXCSR2_REG(ep_num)); ++ ++ if (0 == dma_ctrl->bDMAMode || 0 < (bytesdone % ep_maxpacket)) /* short packet || TX DMA mode0 */ ++ { ++ txcsr_l->bTxPktRdy = 1; ++ ++ ms_writeb(csr1, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ #if 0 ++ if (1 == dma_ctrl->bDMAMode) ++ { ++ DBG_MSG("DMA_TX mode1 short packet\n"); ++ } ++ #endif ++ } ++ } ++ else ++ { ++ csr1 = ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ csr2 = ms_readb(MSB250X_OTG0_EP_RXCSR2_REG(ep_num)); ++ ++ rxcsr_l = (struct otg0_ep_rxcsr_l*) &csr1; ++ rxcsr_h = (struct otg0_ep_rxcsr_h*) &csr2; ++ ++ ms_writeb((csr2 & ~RXCSR2_MODE1), MSB250X_OTG0_EP_RXCSR2_REG(ep_num)); ++ ++ #if 1 ++ if (0 == bytesleft) ++ { ++ if (usb_endpoint_xfer_bulk(_ep->desc)) ++ { ++ if (1 == dma_ctrl->bDMAMode) ++ { ++ msb250x_udc_ok2rcv_for_packets(ep->autoNAK_cfg, 0); ++ } ++ ++ while (0 == (ms_readb(MSB250X_OTG0_USB_CFG7_H) & 0x80)) //last done bit ++ { ++ //printk(KERN_DEBUG "[DMA][%d] Last done bit.\n", ep_num); ++ } ++ ++ } ++ ++ if (0 == dma_ctrl->bDMAMode || 0 == rxcsr_h->bDMAReqMode) ++ { ++ rxcsr_l->bRxPktRdy = 0; ++ ms_writeb(csr1, MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ } ++ } ++ #endif ++ ++ msb250x_gadget_sync_request(ep->gadget, &req->req, req->req.actual, bytesdone); ++ } ++ ++ req->req.actual += bytesdone; ++ ++ if (req->req.actual == req->req.length || (1 != dma_ctrl->bDMAMode && 0 < (bytesdone % ep->ep.maxpacket))) ++ { ++ is_last = 1; ++ } ++#if 0 ++ //if (!usb_endpoint_xfer_int(ep->ep.desc) && !usb_endpoint_dir_in(ep->ep.desc)) ++ //if (usb_endpoint_dir_out(ep->ep.desc)) ++ //if (1 == dma_ctrl->bDMAMode && 0 < (bytesdone % ep->ep.maxpacket)) ++ printk(KERN_DEBUG "[%s][DMA][%d] %s mode/%s/ctrl/bytesdone/bytesleft(0x%x/0x%x/0x%04x/0x%04x/0x%04x) buff/%s/actual/length(0x%p/0x%04x/0x%04x/0x%04x)\n", ++ _ep->name, ++ ch, ++ (usb_endpoint_dir_out(_ep->desc))? "RX" : "TX", ++ (usb_endpoint_dir_out(_ep->desc))? "bRxPktRdy" : "bTxPktRdy", ++ dma_ctrl->bDMAMode, ++ (usb_endpoint_dir_out(_ep->desc))? rxcsr_l->bRxPktRdy : txcsr_l->bTxPktRdy, ++ control, ++ bytesdone, ++ bytesleft, ++ (usb_endpoint_dir_out(_ep->desc))? "count" : "last", ++ req->req.buf, ++ (usb_endpoint_dir_out(_ep->desc))? ms_readw(MSB250X_OTG0_EP_RXCOUNT_L_REG(ep_num)) : is_last, ++ req->req.actual, ++ req->req.length); ++#endif ++ if (1 == is_last) ++ { ++ msb250x_request_done(ep, req, 0); ++ } ++ } ++ ++ if (usb_endpoint_dir_out(ep->ep.desc) || !usb_endpoint_xfer_isoc(_ep->desc)) ++ { ++ msb250x_set_ep_halt(ep, 0); ++ msb250x_request_continue(ep); ++ } ++ ++ return; ++ ++} ++ ++EXPORT_SYMBOL(msb250x_dma_isr_handler); +diff --git a/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_ep.c b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_ep.c +new file mode 100755 +index 000000000000..10e71c9e03f9 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_ep.c +@@ -0,0 +1,1153 @@ ++#include ++#include "msb250x_udc_reg.h" ++#include "msb250x_udc.h" ++#include "msb250x_gadget.h" ++#include "msb250x_dma.h" ++ ++extern const char ep0name[]; ++#if 0 ++static const char *ep0states[]= { ++ "EP0_IDLE", ++ "EP0_IN_DATA_PHASE", ++ "EP0_OUT_DATA_PHASE", ++ "EP0_END_XFER", ++ "EP0_STALL", ++}; ++#endif ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_clear_opr +++------------------------------------------------------------------------------ ++| DESCRIPTION : to clear the RxPktRdy bit ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++ ++void msb250x_ep0_clear_opr(void) ++{ ++ ms_writeb(MSB250X_OTG0_CSR0_SRXPKTRDY, MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_clear_opr); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_clear_sst +++------------------------------------------------------------------------------ ++| DESCRIPTION : to clear SENT_STALL ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_clear_sst(void) ++{ ++ ms_writeb(0x00, MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_clear_sst); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_clear_se +++------------------------------------------------------------------------------ ++| DESCRIPTION : to clear the SetupEnd bit ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_clear_se(void) ++{ ++ ms_writeb(MSB250X_OTG0_CSR0_SSETUPEND, MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_clear_se); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_set_ipr +++------------------------------------------------------------------------------ ++| DESCRIPTION : to set the TxPktRdy bit affer loading a data packet into the FIFO ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_set_ipr(void) ++{ ++ ms_writeb(MSB250X_OTG0_CSR0_TXPKTRDY, MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_set_ipr); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_set_de +++------------------------------------------------------------------------------ ++| DESCRIPTION : to set the DataEnd bit ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_set_de(void) ++{ ++ ms_writeb(MSB250X_OTG0_CSR0_DATAEND, MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_set_de); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_set_ss +++------------------------------------------------------------------------------ ++| DESCRIPTION : to set the SendStall bit to terminate the current transaction ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_set_ss(void) ++{ ++ ms_writeb(MSB250X_OTG0_CSR0_SENDSTALL, MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_set_ss); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_clr_opr_set_ss +++------------------------------------------------------------------------------ ++| DESCRIPTION : to set the SendStall & ServiceRxPktRdy bit to stall EP0 ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++static inline void msb250x_ep0_clr_opr_set_ss(void) ++{ ++ ms_writeb((MSB250X_OTG0_CSR0_SRXPKTRDY | MSB250X_OTG0_CSR0_SENDSTALL), MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_clr_opr_set_ss); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_set_de_out +++------------------------------------------------------------------------------ ++| DESCRIPTION : to clear the ServiceRxPktRdy bit and set the DataEnd bit ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_set_de_out(void) ++{ ++ ms_writeb((MSB250X_OTG0_CSR0_SRXPKTRDY | MSB250X_OTG0_CSR0_DATAEND), MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_set_de_out); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_set_sse_out +++------------------------------------------------------------------------------ ++| DESCRIPTION : to clear the ServiceRxPktRdy bit and clear the ServiceSetupEnd bit ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_set_sse_out(void) ++{ ++ ms_writeb((MSB250X_OTG0_CSR0_SRXPKTRDY | MSB250X_OTG0_CSR0_SSETUPEND), MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_set_sse_out); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_set_de_in +++------------------------------------------------------------------------------ ++| DESCRIPTION : to set the TxPktRdy bit and set the DataEnd bit ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_set_de_in(void) ++{ ++ ms_writeb((MSB250X_OTG0_CSR0_TXPKTRDY | MSB250X_OTG0_CSR0_DATAEND), MSB250X_OTG0_EP0_CSR0_REG); ++} ++EXPORT_SYMBOL(msb250x_ep0_set_de_in); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_enable +++------------------------------------------------------------------------------ ++| DESCRIPTION : configure endpoint, making it usable ++| ++| RETURN : zero, or a negative error code. +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| desc |x | | usb_endpoint_descriptor struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_ep_enable(struct usb_ep *_ep, ++ const struct usb_endpoint_descriptor *desc) ++{ ++ struct msb250x_udc *dev = NULL; ++ struct msb250x_ep *ep = NULL; ++ u8 ep_num = 0; ++ u8 csr1 = 0, csr2 = 0; ++ ++ unsigned long flags; ++#if 1 ++ u8 power = 0; ++ struct otg0_usb_power* pst_power = (struct otg0_usb_power*) &power; ++#endif ++ ep = to_msb250x_ep(_ep); ++ ++ if (!_ep || !desc || _ep->name == ep0name || desc->bDescriptorType != USB_DT_ENDPOINT) ++ { ++ printk(KERN_ERR " %s EINVAL\n", __func__); ++ return -EINVAL; ++ } ++ ++ dev = ep->dev; ++ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) ++ { ++ printk(KERN_ERR " %s ESHUTDOWN\n", __func__); ++ return -ESHUTDOWN; ++ } ++ ++ spin_lock_irqsave(&ep->dev->lock, flags);//local_irq_save (flags); ++ _ep->maxpacket = usb_endpoint_maxp(desc) & 0x7ff; ++ _ep->mult = usb_endpoint_maxp_mult(desc); ++ ep_num = usb_endpoint_num(desc); ++ ++ ep->autoNAK_cfg = 0; ++ ++ /* set type, direction, address; reset fifo counters */ ++ if (usb_endpoint_dir_in(desc)) ++ { ++ csr1 = MSB250X_OTG0_TXCSR1_FLUSHFIFO | MSB250X_OTG0_TXCSR1_CLRDATAOTG; ++ csr2 = MSB250X_OTG0_TXCSR2_MODE; ++ ++ if (usb_endpoint_xfer_isoc(desc)) ++ { ++ csr2 |= MSB250X_OTG0_TXCSR2_ISOC; ++ #if 0 ++ if (usb_endpoint_maxp(desc) > _ep->maxpacket) ++ { ++ power = ms_readb(MSB250X_OTG0_PWR_REG); ++ pst_power->bISOUpdate = 1; ++ ms_writeb(power, MSB250X_OTG0_PWR_REG); ++ } ++ #endif ++ } ++ ++ ms_writew(usb_endpoint_maxp(desc), MSB250X_OTG0_EP_TXMAP_L_REG(ep_num)); ++ ms_writeb(csr1, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ ms_writeb(csr2, MSB250X_OTG0_EP_TXCSR2_REG(ep_num)); ++ ++ ep->fifo_size = 1 << (ms_readb(MSB250X_OTG0_EP_FIFOSIZE_REG(ep_num)) & 0xf0 >> 4); ++ #ifndef CONFIG_USB_FPGA_VERIFICATION ++ /* enable irqs */ ++ ms_writeb((ms_readb(MSB250X_OTG0_INTRTXE_REG) | MSB250X_OTG0_INTR_EP(ep_num)), MSB250X_OTG0_INTRTXE_REG); ++ #endif ++ } ++ else ++ { ++ /* enable the enpoint direction as Rx */ ++ csr1 = MSB250X_OTG0_RXCSR1_FLUSHFIFO | MSB250X_OTG0_RXCSR1_CLRDATATOG; ++ csr2 = 0; ++ ++ if(usb_endpoint_xfer_isoc(desc)) ++ { ++ csr2 |= MSB250X_OTG0_RXCSR2_ISOC; ++ } ++ ++ if (usb_endpoint_xfer_bulk(desc)) ++ { ++ ep->autoNAK_cfg = msb250x_udc_get_autoNAK_cfg(ep_num); ++ msb250x_udc_enable_autoNAK(ep_num, ep->autoNAK_cfg); ++ } ++ ++ ms_writew(usb_endpoint_maxp(desc), MSB250X_OTG0_EP_RXMAP_L_REG(ep_num)); ++ ms_writeb(csr1, MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ ms_writeb(csr2, MSB250X_OTG0_EP_RXCSR2_REG(ep_num)); ++ ++ ep->fifo_size = 1 << (ms_readb(MSB250X_OTG0_EP_FIFOSIZE_REG(ep_num)) & 0x0f); ++ //ep->fifo_size = ms_readb(MSB250X_OTG0_FIFOSIZE_REG); ++ /* enable irqs */ ++ ms_writeb((ms_readb(MSB250X_OTG0_INTRRXE_REG) | MSB250X_OTG0_INTR_EP(ep_num)), MSB250X_OTG0_INTRRXE_REG); ++ } ++#if 1 ++ if (usb_endpoint_xfer_isoc(desc)) ++ { ++ power = ms_readb(MSB250X_OTG0_PWR_REG); ++ ++ if (0 == pst_power->bISOUpdate) ++ { ++ pst_power->bISOUpdate = 1; ++ ms_writeb(power, MSB250X_OTG0_PWR_REG); ++ } ++ } ++#endif ++ msb250x_set_ep_halt(ep, 0); ++ ep->shortPkt = 0; ++ printk(KERN_INFO "[EP][%d] Enable for %s %s with maxpacket/fifo(%d/%d)\r\n", ++ ep_num, ++ usb_endpoint_xfer_bulk(desc)? "BULK" : (usb_endpoint_xfer_isoc(desc)? "ISOC" : "INT"), usb_endpoint_dir_in(desc)? "IN" : "OUT", ++ _ep->maxpacket, ++ ep->fifo_size); ++ ++ spin_unlock_irqrestore(&ep->dev->lock, flags);//local_irq_restore (flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_ep_enable); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_disable +++------------------------------------------------------------------------------ ++| DESCRIPTION : endpoint is no longer usable ++| ++| RETURN : zero, or a negative error code. +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_ep_disable(struct usb_ep *_ep) ++{ ++ struct msb250x_ep *ep = to_msb250x_ep(_ep); ++ u8 ch = 0; ++ u8 ep_num = 0; ++ unsigned long flags; ++ struct msb250x_udc *dev; ++ ++ ++ if (!_ep || !_ep->desc) ++ { ++ printk("[%s] not enabled\n",_ep ? ep->ep.name : NULL); ++ return -EINVAL; ++ } ++ ++ dev = ep->dev; ++ ++ spin_lock_irqsave(&dev->lock,flags);//local_irq_save(flags); ++ ++ msb250x_set_ep_halt(ep, 1); ++ ep_num = usb_endpoint_num(_ep->desc); ++ ++ if (0 < (ch = msb250x_dma_find_channel_by_ep(ep_num))) ++ { ++ msb250x_dma_release_channel(ch); ++ } ++ ++ /* disable irqs */ ++ if (usb_endpoint_dir_in(_ep->desc)) ++ { ++ ms_writeb((ms_readb(MSB250X_OTG0_INTRTXE_REG) & ~(MSB250X_OTG0_INTR_EP(ep_num))), MSB250X_OTG0_INTRTXE_REG); ++ } ++ else ++ { ++ if (usb_endpoint_xfer_bulk(_ep->desc)) ++ { ++ msb250x_udc_release_autoNAK_cfg(ep->autoNAK_cfg); ++ ep->autoNAK_cfg = 0; ++ } ++ ++ ms_writeb((ms_readb(MSB250X_OTG0_INTRRXE_REG) & ~(MSB250X_OTG0_INTR_EP(ep_num))), MSB250X_OTG0_INTRRXE_REG); ++ } ++ ++ msb250x_request_nuke(ep->dev, ep, -ESHUTDOWN); ++ ++ _ep->desc = NULL; ++ ++ spin_unlock_irqrestore(&dev->lock,flags);//local_irq_restore(flags); ++#if 0 ++ DMA_DUMP(); ++#endif ++ ++ printk(KERN_DEBUG"[EP][%d] disabled\n", ep_num); ++//printb(); ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_ep_disable); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_alloc_request +++------------------------------------------------------------------------------ ++| DESCRIPTION : allocate a request object to use with this endpoint ++| ++| RETURN : the request, or null if one could not be allocated. +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++|gfp_flags |x | | GFP_* flags to use +++--------------------+---+---+------------------------------------------------- ++*/ ++struct usb_request* ++msb250x_ep_alloc_request(struct usb_ep *_ep, ++ gfp_t gfp_flags) ++{ ++ struct msb250x_request *req = NULL; ++ ++ if (!_ep) ++ return NULL; ++ ++ req = kzalloc (sizeof(struct msb250x_request), gfp_flags); ++ if (!req) ++ return NULL; ++ ++ INIT_LIST_HEAD (&req->queue); ++ return &req->req; ++} ++EXPORT_SYMBOL(msb250x_ep_alloc_request); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_free_request +++------------------------------------------------------------------------------ ++| DESCRIPTION : frees a request object ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| _req |x | |usb_request struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep_free_request(struct usb_ep *_ep, ++ struct usb_request *_req) ++{ ++ struct msb250x_ep *ep = to_msb250x_ep(_ep); ++ struct msb250x_request *req = to_msb250x_req(_req); ++ ++ if (!ep || !_req || (!_ep->desc && _ep->name != ep0name)) ++ return; ++ ++ WARN_ON (!list_empty (&req->queue)); ++ kfree(req); ++} ++EXPORT_SYMBOL(msb250x_ep_free_request); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_queue +++------------------------------------------------------------------------------ ++| DESCRIPTION : queues (submits) an I/O request to an endpoint ++| ++| RETURN : zero, or a negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| _req |x | |usb_request struct point ++|--------------------+---+---+------------------------------------------------- ++| gfp_flags |x | | GFP_* flags to use +++--------------------+---+---+------------------------------------------------- ++*/ ++ ++int msb250x_ep_queue(struct usb_ep *_ep, ++ struct usb_request *_req, ++ gfp_t gfp_flags) ++{ ++ struct msb250x_request* req = to_msb250x_req(_req); ++ struct msb250x_ep* ep = to_msb250x_ep(_ep); ++ struct msb250x_udc* dev = NULL; ++ unsigned long flags; ++ ++ if (unlikely (!_ep || (!_ep->desc && ep->ep.name != ep0name))) ++ { ++ printk("%s: invalid args\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ dev = ep->dev; ++ ++ if (unlikely (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) ++ { ++ return -ESHUTDOWN; ++ } ++ ++ spin_lock_irqsave(&dev->lock, flags);//local_irq_save (flags); ++ ++ if (unlikely(!_req || !_req->complete || !_req->buf || !list_empty(&req->queue))) ++ { ++ if (!_req) ++ printk("%s: 1 X X X\n", __FUNCTION__); ++ else ++ { ++ printk("%s: 0 %01d %01d %01d\n", ++ __FUNCTION__, !_req->complete,!_req->buf, ++ !list_empty(&req->queue)); ++ } ++ ++ spin_unlock_irqrestore(&dev->lock,flags);//local_irq_restore(flags); ++ return -EINVAL; ++ } ++ ++ _req->status = -EINPROGRESS; ++ _req->actual = 0; ++ ++ if (ep0name != ep->ep.name && dev->using_dma) ++ { ++ msb250x_gadget_map_request(ep->gadget, _req, usb_endpoint_dir_in(_ep->desc)); ++ } ++ ++ if(list_empty(&ep->queue)) ++ { ++ req = msb250x_request_handler(ep, req); ++ } ++ ++ if (req != NULL) ++ { ++ list_add_tail(&req->queue, &ep->queue); ++ } ++ ++ spin_unlock_irqrestore(&dev->lock,flags);//local_irq_restore(flags); ++ ++ return 0; ++ ++} ++EXPORT_SYMBOL(msb250x_ep_queue); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_dequeue +++------------------------------------------------------------------------------ ++| DESCRIPTION : dequeues (cancels, unlinks) an I/O request from an endpoint ++| ++| RETURN : zero, or a negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| _req |x | | usb_request struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_ep_dequeue(struct usb_ep *_ep, ++ struct usb_request *_req) ++{ ++ struct msb250x_ep *ep = to_msb250x_ep(_ep); ++ //struct msb250x_udc *udc = NULL; ++ struct msb250x_udc *dev; ++ struct msb250x_request *req = NULL; ++ int retval = -EINVAL; ++ unsigned long flags; ++ ++ dev = ep->dev; ++ ++ if (!dev->driver) ++ return -ESHUTDOWN; ++ ++ if(!_ep || !_req) ++ return retval; ++ ++ // udc = to_msb250x_udc(ep->gadget); ++ ++ spin_lock_irqsave(&dev->lock,flags);//local_irq_save (flags); ++ ++ list_for_each_entry (req, &ep->queue, queue) ++ { ++ if (&req->req == _req) ++ { ++ list_del_init (&req->queue); ++ _req->status = -ECONNRESET; ++ retval = 0; ++ break; ++ } ++ } ++ ++ if (retval == 0) ++ { ++#if 0 ++ printk(KERN_DEBUG"dequeued req %p from %s, len %d buf %p\n", ++ req, _ep->name, _req->length, _req->buf); ++#endif ++ msb250x_request_done(ep, req, -ECONNRESET); ++ } ++ ++ spin_unlock_irqrestore(&dev->lock,flags);//local_irq_restore (flags); ++ return retval; ++} ++EXPORT_SYMBOL(msb250x_ep_dequeue); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_set_halt +++------------------------------------------------------------------------------ ++| DESCRIPTION : sets the endpoint halt feature. ++| ++| RETURN : zero, or a negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep |x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| value |x | |set halt or not +++--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_ep_set_halt(struct usb_ep *_ep, ++ int value) ++{ ++ u8 csr = 0; ++ u8 ep_num = 0; ++ ++ struct msb250x_ep *ep = to_msb250x_ep(_ep); ++ struct otg0_ep_rxcsr_l* rxcsr_l = NULL; ++ struct otg0_ep_txcsr_l* txcsr_l = NULL; ++ ++ if (unlikely (!_ep || (!_ep->desc && ep->ep.name != ep0name))) ++ { ++ printk("%s: inval 2\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ //spin_lock_irqsave(&ep->dev->lock,flags);//local_irq_save (flags); ++ ++ msb250x_set_ep_halt(ep, value ? 1 : 0); ++ ++ if (IS_ERR_OR_NULL(_ep->desc)) ++ { ++ msb250x_ep0_clr_opr_set_ss(); ++ } ++ else ++ { ++ ep_num = usb_endpoint_num(_ep->desc); ++ ++ if (usb_endpoint_dir_out(_ep->desc)) ++ { ++ csr = ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ rxcsr_l = (struct otg0_ep_rxcsr_l*) &csr; ++ ++ if (value) ++ { ++ rxcsr_l->bSendStall = 1; ++ ms_writeb(csr, MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ } ++ else ++ { ++ rxcsr_l->bSendStall = 0; ++ rxcsr_l->bClrDataTog = 1; ++ ms_writeb(csr, MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ ++ if (1 == rxcsr_l->bRxPktRdy) ++ { ++ msb250x_request_continue(ep); ++ } ++ } ++ ++ } ++ else ++ { ++ csr = ms_readb(MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ txcsr_l = (struct otg0_ep_txcsr_l*) &csr; ++ ++ if (value) ++ { ++ if (1 == txcsr_l->bFIFONotEmpty) ++ { ++ printk("[%s] fifo busy, cannot halt\n", _ep->name); ++ msb250x_set_ep_halt(ep, 1); ++ //spin_unlock_irqrestore(&ep->dev->lock,flags);//local_irq_restore (flags); ++ return -EAGAIN; ++ } ++ ++ txcsr_l->bSendStall = 1; ++ ms_writeb(csr, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ } ++ else ++ { ++ txcsr_l->bClrDataTog = 1; ++ ms_writeb(csr, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ ms_writeb(0, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ ++ if (0 == txcsr_l->bTxPktRdy) ++ { ++ msb250x_request_continue(ep); ++ } ++ } ++ ++ ++ } ++ } ++ ++ //spin_unlock_irqrestore(&ep->dev->lock,flags);//local_irq_restore (flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_ep_set_halt); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_handle_idle +++------------------------------------------------------------------------------ ++| DESCRIPTION :handle the endpoint 0 when endpoint 0 is idle ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev |x | | msb250x_udc struct point ++|--------------------+---+---+------------------------------------------------- ++| ep |x | | msb250x_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| crq |x | | usb_ctrlrequest struct point ++|--------------------+---+---+------------------------------------------------- ++| ep0csr |x | | the csr0 register value +++--------------------+---+---+------------------------------------------------- ++*/ ++static void msb250x_ep0_handle_idle(struct msb250x_udc *dev, ++ struct msb250x_ep *ep) ++{ ++ u8 address = 0; ++ int len = 0, ret = 0; ++ struct usb_ctrlrequest ctrl_req; ++ u8 testPacket[53] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xAA, ++ 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xEE,0xEE,0xEE, ++ 0xEE,0xEE,0xEE,0xEE,0xEE,0xFE,0xFF,0xFF,0xFF,0xFF, ++ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0xBF,0xDF, ++ 0xEF,0xF7,0xFB,0xFD,0xFC,0x7E,0xBF,0xDF,0xEF,0xF7, ++ 0xFB,0xFD,0x7E}; ++ ++ len = ms_readb(MSB250X_OTG0_EP0_COUNT0_REG); ++ ++ if (sizeof(struct usb_ctrlrequest) != len) ++ { ++ printk(KERN_ERR "setup begin: fifo READ ERROR" ++ " wanted %d bytes got %d. Stalling out...\n", ++ sizeof(struct usb_ctrlrequest), len); ++ ++ msb250x_ep0_clr_opr_set_ss(); ++ return; ++ } ++ ++ ms_readsb(&ctrl_req,(void *) OTG0_EP_FIFO_ACCESS_L(0), len); ++#if 0 ++ printk(KERN_DEBUG "[EP][0][SETUP][%s] bRequestType/bRequest/wValue/wIndex/wlength(0x%02x/0x%02x/0x%04x/0x%04x/0x%04x)\r\n", ++ (ctrl_req.bRequestType & USB_DIR_IN)? "IN" : "OUT", ++ ctrl_req.bRequestType, ++ ctrl_req.bRequest, ++ le16_to_cpu(ctrl_req.wValue), ++ le16_to_cpu(ctrl_req.wIndex), ++ le16_to_cpu(ctrl_req.wLength)); ++#endif ++ /* cope with automagic for some standard requests. */ ++ dev->req_std = (ctrl_req.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD; ++ dev->delay_status = 0; ++ dev->req_pending = 1; ++ ++ if (dev->req_std) ++ { ++ switch (ctrl_req.bRequest) ++ { ++ case USB_REQ_SET_CONFIGURATION: ++ //printk(KERN_DEBUG "USB_REQ_SET_CONFIGURATION ... \n"); ++ if (ctrl_req.bRequestType == USB_RECIP_DEVICE) ++ { ++ dev->delay_status++; ++ } ++ break; ++ ++ case USB_REQ_SET_INTERFACE: ++ //printk(KERN_DEBUG "USB_REQ_SET_INTERFACE ... \n"); ++ if (ctrl_req.bRequestType == USB_RECIP_INTERFACE) ++ { ++ dev->delay_status++; ++ } ++ break; ++ ++ case USB_REQ_SET_ADDRESS: ++ //printk(KERN_DEBUG "USB_REQ_SET_ADDRESS ... \n"); ++ if (ctrl_req.bRequestType == USB_RECIP_DEVICE) ++ { ++ address = ctrl_req.wValue & 0x7F; ++ dev->address = address; ++ ms_writeb(address, MSB250X_OTG0_FADDR_REG); ++ usb_gadget_set_state(&dev->gadget, USB_STATE_ADDRESS); ++ msb250x_ep0_clear_opr(); ++ return; ++ } ++ break; ++ ++ case USB_REQ_GET_STATUS: ++ //printk(KERN_DEBUG "USB_REQ_GET_STATUS ... \n"); ++ msb250x_ep0_clear_opr(); ++ if (dev->req_std) ++ { ++ if (0 == msb250x_udc_get_status(dev, &ctrl_req)) ++ { ++ msb250x_ep0_set_de_in(); ++ return; ++ } ++ } ++ break; ++ ++ case USB_REQ_CLEAR_FEATURE: ++ //printk(KERN_DEBUG "USB_REQ_CLEAR_FEATURE ... \n"); ++ if (ctrl_req.bRequestType != USB_RECIP_ENDPOINT) ++ break; ++ ++ if (ctrl_req.wValue != USB_ENDPOINT_HALT || ctrl_req.wLength != 0) ++ break; ++ ++ msb250x_ep_set_halt(&dev->ep[ctrl_req.wIndex & 0x7f].ep, 0); ++ msb250x_ep0_clear_opr(); ++ return; ++ ++ case USB_REQ_SET_FEATURE: ++ //printk(KERN_DEBUG "USB_REQ_SET_FEATURE ... \n"); ++ msb250x_ep0_clear_opr(); ++ if(ctrl_req.bRequestType == USB_RECIP_DEVICE) ++ { ++ if(ctrl_req.wValue == USB_DEVICE_TEST_MODE) //USB20_TEST_MODE ++ { ++ switch (ctrl_req.wIndex >> 8) { ++ case TEST_J: ++ printk("TEST_J mode\n"); ++ ms_writeb(MSB250X_OTG0_TESTMODE_TEST_J, MSB250X_OTG0_TESTMODE_REG); ++ break; ++ case TEST_K: ++ printk("TEST_K mode\n"); ++ ms_writeb(MSB250X_OTG0_TESTMODE_TEST_K, MSB250X_OTG0_TESTMODE_REG); ++ break; ++ case TEST_SE0_NAK: ++ printk("TEST_SE0_NAK mode\n"); ++ ms_writeb(MSB250X_OTG0_TESTMODE_TEST_SE0_NAK, MSB250X_OTG0_TESTMODE_REG); ++ break; ++ case TEST_PACKET: ++ printk("TEST_PACKET mode\n"); ++ ms_writeb(MSB250X_OTG0_TESTMODE_TEST_PACKET, MSB250X_OTG0_TESTMODE_REG); ++ ms_writesb(testPacket, OTG0_EP_FIFO_ACCESS_L(0), 53); ++ msb250x_ep0_set_de_in(); ++ break; ++ default: ++ printk("UNKNOWN TEST mode\n"); ++ break; ++ } ++ return; ++ } ++ } ++ if (ctrl_req.bRequestType != USB_RECIP_ENDPOINT) ++ break; ++ ++ if (ctrl_req.wValue != USB_ENDPOINT_HALT || ctrl_req.wLength != 0) ++ break; ++ ++ msb250x_ep_set_halt(&dev->ep[ctrl_req.wIndex & 0x7f].ep, 1); ++ msb250x_ep0_clear_opr(); ++ return; ++ ++ default: ++ msb250x_ep0_clear_opr(); ++ break; ++ } ++ } ++ else ++ { ++ msb250x_ep0_clear_opr(); ++ } ++ ++ if (ctrl_req.bRequestType & USB_DIR_IN) ++ { ++ dev->ep0state = EP0_IN_DATA_PHASE; ++ } ++ else ++ { ++ dev->ep0state = EP0_OUT_DATA_PHASE; ++ } ++ ++ if (0 == ctrl_req.wLength) ++ { ++ dev->ep0state = EP0_IDLE; ++ } ++ ++ if (dev->driver && dev->driver->setup) ++ { ++ spin_unlock (&dev->lock); ++ ret = dev->driver->setup(&dev->gadget, &ctrl_req); ++ spin_lock (&dev->lock); ++ } ++ else ++ ret = -EINVAL; ++ ++ if (ret < 0) ++ { ++ if (0 < dev->delay_status) ++ { ++ printk(" config change %02x fail %d?\n", ++ ctrl_req.bRequest, ret); ++ return; ++ } ++ ++ if (ret == -EOPNOTSUPP) ++ printk(" Operation not supported\n"); ++ else ++ printk(" dev->driver->setup failed. (%d)\n", ret); ++ ++ msb250x_ep0_clr_opr_set_ss(); ++ ++ dev->ep0state = EP0_IDLE; ++ ++ /* deferred i/o == no response yet */ ++ } ++ else if (dev->req_pending) ++ { ++ //printk(KERN_DEBUG "dev->req_pending... what now?\n"); ++ dev->req_pending = 0; ++ } ++ ++ //printk(KERN_DEBUG "[0][EP] state(%s)\n", ep0states[dev->ep0state]); ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep0_isr_handler +++------------------------------------------------------------------------------ ++| DESCRIPTION :handle the endpoint 0 ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev |x | | msb250x_udc struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep0_isr_handler(struct msb250x_udc *dev) ++{ ++ u8 ep0csr = 0; ++ ++ struct msb250x_ep* ep = &dev->ep[0]; ++ struct msb250x_request* req = NULL; ++ ++ ep0csr = ms_readb(MSB250X_OTG0_EP0_CSR0_REG); ++ ++ /* clear stall status */ ++ if (ep0csr & MSB250X_OTG0_CSR0_SENTSTALL) ++ { ++ //printk("[0][EP] ... clear SENT_STALL ...\n"); ++ msb250x_request_nuke(dev, ep, -EPIPE); ++ msb250x_ep0_clear_sst(); ++ dev->ep0state = EP0_IDLE; ++ msb250x_set_ep_halt(ep, 0); ++ return; ++ } ++ ++ /* clear setup end */ ++ if (ep0csr & MSB250X_OTG0_CSR0_SETUPEND) ++ { ++ //printk("... serviced SETUP_END ...\n"); ++ msb250x_request_nuke(dev, ep, 0); ++ msb250x_ep0_clear_se(); ++ ++ dev->ep0state = EP0_IDLE; ++ } ++ ++ switch (dev->ep0state) ++ { ++ case EP0_IDLE: ++ if (ep0csr & MSB250X_OTG0_CSR0_RXPKTRDY) ++ { ++ msb250x_ep0_handle_idle(dev, ep); ++ } ++ break; ++ ++ case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ ++ case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ ++ if (!list_empty(&ep->queue)) ++ { ++ req = list_entry(ep->queue.next, struct msb250x_request, queue); ++ msb250x_set_ep_halt(ep, 0); ++ msb250x_request_handler(ep, req); ++ } ++ break; ++ ++ default: ++ dev->ep0state = EP0_IDLE; ++ printk("EP0 status ... what now?\n"); ++ break; ++ } ++} ++EXPORT_SYMBOL(msb250x_ep0_isr_handler); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_ep_isr_handler +++------------------------------------------------------------------------------ ++| DESCRIPTION :handle the endpoint except endpoint 0 ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| ep |x | | msb250x_ep struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_ep_isr_handler(struct msb250x_udc* dev, ++ struct msb250x_ep *ep) ++{ ++ struct usb_ep* _ep = &ep->ep; ++ struct msb250x_request* req = NULL; ++ struct otg0_ep_rxcsr_h* pst_rxcsr_h = NULL; ++ struct otg0_ep_rxcsr_l* pst_rxcsr_l = NULL; ++ struct otg0_ep_txcsr_l* pst_txcsr_l = NULL; ++ ++ u8 ep_num = 0; ++ u8 csr1 = 0, csr2 = 0; ++ u8 using_dma = 0; ++ u16 counts = 0; ++ u16 pkt_num = 0; ++ //u16 ok2rcv_packets = 0; ++ ++ ep_num = usb_endpoint_num(_ep->desc); ++ using_dma = msb250x_dma_find_channel_by_ep(ep_num); ++ ++ if (likely(!list_empty(&ep->queue))) ++ { ++ req = list_entry(ep->queue.next, struct msb250x_request, queue); ++ } ++ ++ if (usb_endpoint_dir_in(_ep->desc)) ++ { ++ csr1 = ms_readb(MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ pst_txcsr_l = (struct otg0_ep_txcsr_l*) &csr1; ++ ++ if (1 == pst_txcsr_l->bIncompTx) ++ { ++ printk(KERN_DEBUG "[ep][%d] Incomplete transfer.\n", ep_num); ++ //pst_txcsr_l->bIncompTx = 0; ++ //ms_writeb(csr1, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ //return; ++ } ++ ++ if (1 == pst_txcsr_l->bSentStall) ++ { ++ pst_txcsr_l->bSentStall = 0; ++ ms_writeb(csr1, MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ return; ++ } ++ ++ if (!using_dma) ++ { ++ msb250x_set_ep_halt(ep, 0); ++ } ++ } ++ else ++ { ++ csr1 = ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ csr2 = ms_readb(MSB250X_OTG0_EP_RXCSR2_REG(ep_num)); ++ ++ pst_rxcsr_l = (struct otg0_ep_rxcsr_l*) &csr1; ++ pst_rxcsr_h = (struct otg0_ep_rxcsr_h*) &csr2; ++ ++ if (1 == pst_rxcsr_l->bSentStall) ++ { ++ pst_rxcsr_l->bSentStall = 0; ++ ms_writeb(csr1, MSB250X_OTG0_RXCSR1_REG); ++ return; ++ } ++ ++ if (req) ++ { ++ if (1 == pst_rxcsr_l->bRxPktRdy) ++ { ++ if (usb_endpoint_xfer_bulk(_ep->desc)) ++ { ++ counts = ms_readw(MSB250X_OTG0_EP_RXCOUNT_L_REG(ep_num)); ++ pkt_num = (req->req.length - req->req.actual + (_ep->maxpacket - 1)) / _ep->maxpacket; ++ ++ if (req->req.length <= _ep->maxpacket || counts < _ep->maxpacket || 1 == pkt_num) ++ { ++ msb250x_udc_ok2rcv_for_packets(ep->autoNAK_cfg, 0); ++ ++ if (counts < _ep->maxpacket) ++ { ++ ep->shortPkt |= 1; ++ } ++ #if 0 ++ printk(KERN_DEBUG "[EP][%d] RX[INT] actual/length(0x%04x/0x%04x) dma/shortPkt/fifo/pkt_num(%d/%d/0x%04x/%d).\n", ++ ep_num, ++ req->req.actual, ++ req->req.length, ++ using_dma, ++ ep->shortPkt, ++ counts, ++ pkt_num); ++ #endif ++ } ++ } ++ ++ if (using_dma) ++ { ++ msb250x_dma_isr_handler(using_dma, dev); //meet short packet ++ msb250x_set_ep_halt(ep, 0); ++ } ++ else ++ { ++ msb250x_set_ep_halt(ep, 0); ++ req = msb250x_request_handler(ep, req); ++ } ++ ++ using_dma = msb250x_dma_find_channel_by_ep(ep_num); //need to refresh dma channel after handle request ++ ++ if (!using_dma) ++ { ++ /* ++ 1. zero length packet need to continue request again. ++ 2. when request is completed by riu mode, it is necessary to continue request. ++ */ ++ if (NULL == req || 0 == counts) ++ { ++ msb250x_set_ep_halt(ep, 0); ++ } ++ } ++ } ++ ++ } ++ } ++ ++ msb250x_request_continue(ep); ++} ++EXPORT_SYMBOL(msb250x_ep_isr_handler); ++ +diff --git a/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_gadget.c b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_gadget.c +new file mode 100755 +index 000000000000..69b96803e529 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_gadget.c +@@ -0,0 +1,325 @@ ++/*------------------------- usb_gadget_ops ----------------------------------*/ ++#include ++#include ++#include "msb250x_udc_reg.h" ++#include "msb250x_udc.h" ++ ++void msb250x_gadget_sync_request(struct usb_gadget* gadget, struct usb_request* req, int offset, int size) ++{ ++ #ifdef __arch_pfn_to_dma ++ dma_sync_single_range_for_cpu(gadget->dev.parent, req->dma, offset, size, DMA_FROM_DEVICE); ++ #else ++ dma_addr_t __dma = req->dma; ++ //__dma = (MIU1_BUS_BASE_ADDR > __dma)? ((__dma - MIU0_BUS_BASE_ADDR) + MIU0_BASE_ADDR) : ((__dma - MIU1_BUS_BASE_ADDR) + MIU1_BASE_ADDR); ++ __dma = MSB250X_BUS2PA(__dma); ++ dma_sync_single_range_for_cpu(gadget->dev.parent, __dma, offset, size, DMA_FROM_DEVICE); ++ #endif ++ ++} ++EXPORT_SYMBOL(msb250x_gadget_sync_request); ++ ++int msb250x_gadget_map_request(struct usb_gadget* gadget, struct usb_request* req, int is_in) ++{ ++ int ret = usb_gadget_map_request(gadget, req, is_in); ++ dma_addr_t __dma = req->dma; ++ ++ if (is_in) ++ { ++ dma_sync_single_for_device(gadget->dev.parent, req->dma, req->length, DMA_TO_DEVICE); ++ } ++ ++#ifndef __arch_pfn_to_dma ++ //__dma = (MIU1_BASE_ADDR > __dma)? (MIU0_BUS_BASE_ADDR | (__dma - MIU0_BASE_ADDR)) : (MIU1_BUS_BASE_ADDR + (__dma - MIU1_BASE_ADDR)); ++ __dma = MSB250X_PA2BUS(__dma); ++ req->dma = __dma; ++#endif ++ ++ return ret; ++} ++EXPORT_SYMBOL(msb250x_gadget_map_request); ++ ++void msb250x_gadget_unmap_request(struct usb_gadget* gadget, struct usb_request* req, int is_in) ++{ ++#ifndef __arch_pfn_to_dma ++ dma_addr_t __dma = req->dma; ++ //__dma = (MIU1_BUS_BASE_ADDR > __dma)? ((__dma - MIU0_BUS_BASE_ADDR) + MIU0_BASE_ADDR) : ((__dma - MIU1_BUS_BASE_ADDR) + MIU1_BASE_ADDR); ++ __dma = MSB250X_BUS2PA(__dma); ++ req->dma = __dma; ++#endif ++ ++ usb_gadget_unmap_request(gadget, req, is_in); ++} ++EXPORT_SYMBOL(msb250x_gadget_unmap_request); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_pullup_i +++------------------------------------------------------------------------------ ++| DESCRIPTION : internal software connection function ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| is_on |x | | enable the software connection or not ++|--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_gadget_pullup_i(int is_on) ++{ ++ u8 power = 0; ++ struct otg0_usb_power* pst_power = (struct otg0_usb_power*) &power; ++ ++ power = ms_readb(MSB250X_OTG0_PWR_REG); ++ pst_power->bSoftConn = is_on; ++ ++ ms_writeb(power, MSB250X_OTG0_PWR_REG); ++ ++ printk("[GADGET] PULL_UP(%s)\n", (0 == is_on)? "OFF" : "ON"); ++} ++ ++EXPORT_SYMBOL(msb250x_gadget_pullup_i); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_get_frame +++------------------------------------------------------------------------------ ++| DESCRIPTION : get frame count ++| ++| RETURN : the current frame number +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _gadget |x | | usb_gadget struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_gadget_get_frame(struct usb_gadget *g) ++{ ++ return ms_readw(MSB250X_OTG0_FRAME_L_REG); ++} ++EXPORT_SYMBOL(msb250x_gadget_get_frame); ++ ++struct usb_ep* ++msb250x_gadget_match_ep(struct usb_gadget *g, ++ struct usb_endpoint_descriptor *desc, ++ struct usb_ss_ep_comp_descriptor *ep_comp) ++{ ++ struct msb250x_udc* dev = to_msb250x_udc(g); ++ struct usb_ep* ep = NULL; ++ ++ switch (usb_endpoint_type(desc)) ++ { ++ case USB_ENDPOINT_XFER_ISOC: ++ if (1 < usb_endpoint_maxp_mult(desc)) ++ { ++ ep = MSB250X_HIGH_BANDWIDTH_EP(dev); ++ } ++ break; ++ case USB_ENDPOINT_XFER_INT: ++ ep = &dev->ep[3].ep; ++ break; ++ default: ++ /* nothing */ ; ++ } ++ ++ return ep; ++} ++EXPORT_SYMBOL(msb250x_gadget_match_ep); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_wakeup +++------------------------------------------------------------------------------ ++| DESCRIPTION : tries to wake up the host connected to this gadget ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _gadget |x | | usb_gadget struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_gadget_wakeup(struct usb_gadget *g) ++{ ++ printk("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_wakeup); ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_set_selfpowered +++------------------------------------------------------------------------------ ++| DESCRIPTION : sets the device selfpowered feature ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| gadget |x | | usb_gadget struct point ++|--------------------+---+---+------------------------------------------------- ++| value |x | | set this feature or not ++|--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_gadget_set_selfpowered(struct usb_gadget *g, ++ int value) ++{ ++ struct msb250x_udc *udc = to_msb250x_udc(g); ++ ++ if (value) ++ udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED); ++ else ++ udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED); ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_set_selfpowered); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_pullup +++------------------------------------------------------------------------------ ++| DESCRIPTION : software-controlled connect to USB host ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| gadget |x | | usb_gadget struct point ++|--------------------+---+---+------------------------------------------------- ++| is_on |x | | set software-controlled connect to USB host or not ++|--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_gadget_pullup(struct usb_gadget *g, ++ int is_on) ++{ ++ struct msb250x_udc *dev = to_msb250x_udc(g); ++ ++ u8 power = ms_readb(MSB250X_OTG0_PWR_REG); ++ struct otg0_usb_power* pst_power = (struct otg0_usb_power*) &power; ++ ++ dev->soft_conn = pst_power->bSoftConn; ++ ++ if (1 == is_on) ++ { ++ if (0 == dev->soft_conn) ++ { ++ msb250x_gadget_pullup_i(is_on); ++ } ++ } ++ else ++ { ++ if (1 == dev->soft_conn) ++ { ++ msb250x_gadget_pullup_i(is_on); ++ } ++ } ++ ++ dev->soft_conn = is_on; ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_pullup); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_vbus_session +++------------------------------------------------------------------------------ ++| DESCRIPTION : establish the USB session ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| gadget |x | | usb_gadget struct point ++|--------------------+---+---+------------------------------------------------- ++| is_active |x | | establish the session or not ++|--------------------+---+---+------------------------------------------------- ++*/ ++ ++int msb250x_gadget_vbus_session(struct usb_gadget *g, ++ int is_active) ++{ ++ printk("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_vbus_session); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_gadget_vbus_draw +++------------------------------------------------------------------------------ ++| DESCRIPTION : constrain controller's VBUS power usage ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _gadget |x | | usb_gadget struct point ++|--------------------+---+---+------------------------------------------------- ++| ma |x | | milliAmperes ++|--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_gadget_vbus_draw(struct usb_gadget *g, ++ unsigned ma) ++{ ++ printk("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_vbus_draw); ++ ++ ++int msb250x_gadget_udc_start(struct usb_gadget *g, ++ struct usb_gadget_driver *driver) ++{ ++ struct msb250x_udc *dev = NULL; ++ ++ if (!g) ++ { ++ printk("[GADGET] ENODEV!\n"); ++ return -ENODEV; ++ } ++ ++ dev = to_msb250x_udc(g); ++ ++ dev->driver = driver; ++ dev->gadget.dev.driver = &driver->driver; ++ ++ msb250x_udc_deinit_utmi(); ++ msb250x_udc_init_utmi(); ++ msb250x_udc_init_usb_ctrl(); ++ msb250x_udc_reset_otg(); ++ msb250x_udc_init_otg(dev); ++ ++ mdelay(1); ++ ++ printk("[GADGET] UDC start\n"); ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_udc_start); ++ ++int msb250x_gadget_udc_stop(struct usb_gadget *g) ++{ ++ struct msb250x_udc *dev = NULL; ++ int i; ++ ++ if (!g) ++ { ++ printk("[GADGET] ENODEV!\n"); ++ return -ENODEV; ++ } ++ ++ dev = to_msb250x_udc(g); ++ ++ for (i = 0; i < MSB250X_MAX_ENDPOINTS; i++) ++ { ++ dev->ep[i].ep.desc = NULL; ++ } ++ dev->driver = NULL; ++ dev->gadget.dev.driver = NULL; ++ ++ msb250x_udc_init_usb_ctrl(); ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_gadget_udc_stop); ++ +diff --git a/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_udc.c b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_udc.c +new file mode 100755 +index 000000000000..612b15bc3f80 +--- /dev/null ++++ b/drivers/sstar/usb/gadget/udc/usb20/src/msb250x_udc.c +@@ -0,0 +1,1588 @@ ++/* SigmaStar trade secret */ ++/* ++* msb250x_udc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++ ++/****************************************************************************** ++ * Include Files ++ ******************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include // Mstar OTG operation ++#include ++#include /* copy_*_user */ ++ ++#include ++#include ++#include ++//#include ++#include ++//#include ++ ++//#include ++#if defined(CONFIG_ARM64) ++#else ++#include ++#endif ++ ++#if 0 ++#include "padmux.h" ++#include "mdrv_padmux.h" ++#include "mdrv_gpio.h" ++#include "mdrv_gpio_io.h" ++#endif ++ ++#include ++#include ++ ++#include "msb250x_udc_reg.h" ++#include "msb250x_udc.h" ++#include "msb250x_gadget.h" ++#include "msb250x_ep.h" ++#include "msb250x_dma.h" ++ ++//#define REG_ADDR_BASE_PM_GPIO GET_REG8_ADDR(RIU_BASE_ADDR, 0x0F00) ++ ++/* the module parameter */ ++#define DRIVER_DESC "MSB250x USB Device Controller Gadget" ++#define DRIVER_VERSION "5 June 2019" ++#define DRIVER_AUTHOR "sigmastar.com" ++ ++#define AUTONAK_COUNT 2 ++#define MAX_ETHERNET_PACKET_SIZE 1518 ++ ++/****************************************************************************** ++ * Variables ++ ******************************************************************************/ ++const char ep0name[] = "ep0"; ++ ++static const char sg_gadget_name[] = "msb250x_udc"; ++ ++static const struct usb_ep_ops msb250x_ep_ops = ++{ ++ .enable = msb250x_ep_enable, ++ .disable = msb250x_ep_disable, ++ ++ .alloc_request = msb250x_ep_alloc_request, ++ .free_request = msb250x_ep_free_request, ++ ++ .queue = msb250x_ep_queue, ++ .dequeue = msb250x_ep_dequeue, ++ ++ .set_halt = msb250x_ep_set_halt, ++}; ++ ++static const struct usb_gadget_ops msb250x_gadget_ops = ++{ ++ .get_frame = msb250x_gadget_get_frame, ++ .wakeup = msb250x_gadget_wakeup, ++ .set_selfpowered = msb250x_gadget_set_selfpowered, ++ .pullup = msb250x_gadget_pullup, ++ //.vbus_session = msb250x_gadget_vbus_session, ++ //.vbus_draw = msb250x_gadget_vbus_draw, ++ .udc_start = msb250x_gadget_udc_start, ++ .match_ep = msb250x_gadget_match_ep, ++ .udc_stop = msb250x_gadget_udc_stop, ++}; ++ ++static struct msb250x_udc memory = { ++ .gadget = { ++ .ep0 = &memory.ep[0].ep, ++ .ops = &msb250x_gadget_ops, ++ .max_speed = USB_SPEED_HIGH, ++ .name = sg_gadget_name, ++ .dev = { ++ //.bus_id = "gadget", ++ .init_name = "gadget", ++ //.release = nop_release, ++ }, ++ }, ++ MSB250X_EPS_CAP(&memory, &msb250x_ep_ops), ++}; ++ ++extern unsigned int irq_of_parse_and_map(struct device_node *node, int index); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_write_riu +++------------------------------------------------------------------------------ ++| DESCRIPTION : write the usb request info ++| ++| RETURN : length +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| ep |x | | msb250x_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| req |x | | msb250x_request struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++static int msb250x_udc_write_riu(struct msb250x_ep *ep, ++ struct msb250x_request *req, ++ u32 bytes) ++{ ++ u8 ep_num = 0; ++ ++ int is_last = 0; ++ ++ struct usb_ep* _ep = &ep->ep; ++ ++ ep_num = IS_ERR_OR_NULL(_ep->desc)? 0 : usb_endpoint_num(_ep->desc); ++ ++ if (0 < bytes) ++ { ++ ms_writesb((req->req.buf + req->req.actual), OTG0_EP_FIFO_ACCESS_L(ep_num), bytes); ++ } ++ ++ req->req.actual += bytes; ++ ++ /* last packet is often short (sometimes a zlp) */ ++ if (bytes != ep->ep.maxpacket || req->req.length == req->req.actual) ++ { ++ is_last = 1; ++ } ++ ++#if 0 ++ if (!IS_ERR_OR_NULL(_ep->desc)) ++ printk(KERN_DEBUG "[UDC][%d][TX] maxpacket/bytesDone(0x%04x/0x%04x) buff/last/actual/length(%p/%d/0x%04x/0x%04x) \n", ++ ep_num, ++ ep->ep.maxpacket, ++ count, ++ req->req.buf, ++ is_last, ++ req->req.actual, ++ req->req.length); ++#endif ++#if 1 ++ if (is_last) ++ { ++ msb250x_request_done(ep, req, 0); ++ } ++#endif ++ return is_last; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_read_riu +++------------------------------------------------------------------------------ ++| DESCRIPTION : read the usb request info ++| ++| RETURN : length +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| ep |x | | msb250x_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| req |x | | msb250x_request struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++static int msb250x_udc_read_riu(struct msb250x_ep *ep, ++ struct msb250x_request *req, ++ u32 bytes) ++{ ++ u8 ep_num = 0; ++ int is_last = 0; ++ ++ struct usb_ep* _ep = &ep->ep; ++ //struct otg0_ep_rxcsr_l* rxcsr_l = NULL; ++ ++ if (0 == req->req.length) ++ { ++ return 1; ++ } ++ ++ ep_num = IS_ERR_OR_NULL(_ep->desc)? 0 : usb_endpoint_num(_ep->desc); ++ ++ if (0 < bytes) ++ { ++ ms_readsb((req->req.buf + req->req.actual), OTG0_EP_FIFO_ACCESS_L(ep_num), bytes); ++ ++ req->req.actual += bytes; ++ ++ if (bytes != ep->ep.maxpacket || req->req.zero) ++ { ++ is_last = 1; ++ } ++ } ++ ++ if (req->req.length == req->req.actual) ++ { ++ is_last = 1; ++ } ++ ++#if 0 ++ if (!IS_ERR_OR_NULL(_ep->desc)) ++ { ++ printk(KERN_DEBUG "[UDC][%d] RX[RIU] count/maxpacket(0x%04x/0x%04x) buff/last/actual/length(%p/%d/0x%04x/0x%04x) \n", ++ ep_num, ++ count, ++ ep->ep.maxpacket, ++ req->req.buf, ++ is_last, ++ req->req.actual, ++ req->req.length); ++ } ++#endif ++ ++ if (is_last) ++ { ++ msb250x_request_done(ep, req, 0); ++ } ++ ++ return is_last; ++} ++ ++int msb250x_udc_get_autoNAK_cfg(u8 ep_num) ++{ ++ int cfg = 0; ++ u8 ep_bulkout = 0; ++ ++ for (cfg = 0; cfg < AUTONAK_COUNT; cfg++) ++ { ++ switch(cfg) ++ { ++ case 0: ++ ep_bulkout = (ms_readb(MSB250X_OTG0_AUTONAK0_EP_BULKOUT) & 0x0f); ++ break; ++ case 1: ++ ep_bulkout = (ms_readb(MSB250X_OTG0_AUTONAK1_EP_BULKOUT) & 0x0f); ++ break; ++ case 2: ++ ep_bulkout = (ms_readb(MSB250X_OTG0_AUTONAK2_EP_BULKOUT) & 0xf0); ++ ep_bulkout = ep_bulkout >> 4; ++ break; ++ } ++ ++ if (0 == ep_bulkout) ++ { ++ return (cfg + 1); ++ } ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_udc_get_autoNAK_cfg); ++ ++int msb250x_udc_release_autoNAK_cfg(u8 cfg) ++{ ++ cfg--; ++ ++ switch(cfg) ++ { ++ case 0: ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK0_EP_BULKOUT) & 0xf0), MSB250X_OTG0_AUTONAK0_EP_BULKOUT); ++ ms_writew(0x0000, MSB250X_OTG0_USB_CFG5_L); ++ #if 0 ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK0_CTRL) & ~(MSB250X_OTG0_AUTONAK0_EN | MSB250X_OTG0_AUTONAK0_OK2Rcv | MSB250X_OTG0_AUTONAK0_AllowAck)), ++ MSB250X_OTG0_AUTONAK0_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK0_RX_PKT_CNT) & 0xE000), MSB250X_OTG0_AUTONAK0_RX_PKT_CNT); ++ #endif ++ break; ++ case 1: ++ ms_writeb(ms_readb(MSB250X_OTG0_USB_CFG0_H) & 0x80, MSB250X_OTG0_USB_CFG0_H); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK1_RX_PKT_CNT) & 0xE000), MSB250X_OTG0_AUTONAK1_RX_PKT_CNT); ++ #if 0 ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK1_EP_BULKOUT) & 0xf0), MSB250X_OTG0_AUTONAK1_EP_BULKOUT); ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK1_CTRL) & ~(MSB250X_OTG0_AUTONAK1_EN | MSB250X_OTG0_AUTONAK1_OK2Rcv | MSB250X_OTG0_AUTONAK1_AllowAck)), ++ MSB250X_OTG0_AUTONAK1_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK1_RX_PKT_CNT) & 0xE000), MSB250X_OTG0_AUTONAK1_RX_PKT_CNT); ++ #endif ++ break; ++ case 2: ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK2_EP_BULKOUT) & 0x0f), MSB250X_OTG0_AUTONAK2_EP_BULKOUT); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK2_CTRL) & ~(MSB250X_OTG0_AUTONAK2_EN | MSB250X_OTG0_AUTONAK2_OK2Rcv | MSB250X_OTG0_AUTONAK2_AllowAck)), MSB250X_OTG0_AUTONAK2_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK2_RX_PKT_CNT) & 0xE000), MSB250X_OTG0_AUTONAK2_RX_PKT_CNT); ++ break; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_udc_release_autoNAK_cfg); ++ ++int msb250x_udc_init_autoNAK_cfg(void) ++{ ++ int cfg = 0; ++ ++ for (cfg = 0; cfg < AUTONAK_COUNT; cfg++) ++ { ++ msb250x_udc_release_autoNAK_cfg((cfg + 1)); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_udc_init_autoNAK_cfg); ++ ++void msb250x_udc_enable_autoNAK(u8 ep_num, u8 cfg) ++{ ++ cfg--; ++ ++ switch(cfg) ++ { ++ case 0: ++ ep_num &= 0x0f; ++ ms_writeb(ep_num, MSB250X_OTG0_AUTONAK0_EP_BULKOUT); ++ { ++ u16 ctrl = 0; ++ ctrl |= MSB250X_OTG0_AUTONAK0_EN; ++ ms_writew(ctrl, MSB250X_OTG0_AUTONAK0_CTRL); ++ } ++ break; ++ case 1: ++ ep_num &= 0x0f; ++ ms_writeb(MSB250X_OTG0_AUTONAK1_EN | ep_num, MSB250X_OTG0_AUTONAK1_CTRL); ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK1_CTRL) & ~(MSB250X_OTG0_AUTONAK1_OK2Rcv | MSB250X_OTG0_AUTONAK1_AllowAck)), MSB250X_OTG0_AUTONAK1_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK1_RX_PKT_CNT) & 0xE000), MSB250X_OTG0_AUTONAK1_RX_PKT_CNT); ++ break; ++ case 2: ++ ep_num = ep_num << 4; ++ ep_num &= 0xf0; ++ ms_writew(MSB250X_OTG0_AUTONAK2_EN | (u16) ep_num, MSB250X_OTG0_AUTONAK2_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK2_CTRL) & ~(MSB250X_OTG0_AUTONAK2_OK2Rcv | (u16) MSB250X_OTG0_AUTONAK2_AllowAck)), MSB250X_OTG0_AUTONAK2_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK2_RX_PKT_CNT) & 0xE000), MSB250X_OTG0_AUTONAK2_RX_PKT_CNT); ++ break; ++ } ++ ++ //printk(KERN_DEBUG "[UDC][NAK][%d] enable autoNAK!\n", cfg); ++} ++EXPORT_SYMBOL(msb250x_udc_enable_autoNAK); ++ ++void msb250x_udc_ok2rcv_for_packets(u8 cfg, u16 pkt_num) ++{ ++ u16 ctrl = 0; ++ cfg--; ++ ++ switch(cfg) ++ { ++ case 0: ++ ctrl |= MSB250X_OTG0_AUTONAK0_EN; ++ ctrl |= (pkt_num & ~0xE000); ++ ++ if (0 < pkt_num) ++ { ++ ctrl |= MSB250X_OTG0_AUTONAK0_OK2Rcv; ++ } ++ ++ ms_writew(ctrl, MSB250X_OTG0_AUTONAK0_CTRL); ++ break; ++ case 1: ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK1_RX_PKT_CNT) & ~0xE000) | pkt_num, MSB250X_OTG0_AUTONAK1_RX_PKT_CNT); ++ ctrl = ms_readb(MSB250X_OTG0_AUTONAK1_CTRL); ++ ++ if (0 < pkt_num) ++ { ++ ctrl |= MSB250X_OTG0_AUTONAK1_OK2Rcv; ++ } ++ ++ ms_writeb(ctrl & 0xFF, MSB250X_OTG0_AUTONAK1_CTRL); ++ break; ++ case 2: ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK2_RX_PKT_CNT) & ~0xE000) | pkt_num, MSB250X_OTG0_AUTONAK2_RX_PKT_CNT); ++ ctrl = ms_readw(MSB250X_OTG0_AUTONAK2_CTRL); ++ ++ if (0 < pkt_num) ++ { ++ ctrl |= MSB250X_OTG0_AUTONAK2_OK2Rcv; ++ } ++ ++ ms_writew(ctrl, MSB250X_OTG0_AUTONAK2_CTRL); ++ break; ++ ++ } ++ ++ //printk(KERN_DEBUG "[UDC][NAK][%d] ok2rcv %d packets\n", cfg, pkt_num); ++} ++EXPORT_SYMBOL(msb250x_udc_ok2rcv_for_packets); ++ ++void msb250x_udc_allowAck(u8 cfg) ++{ ++ cfg--; ++ ++ switch(cfg) ++ { ++ case 0: ++ ms_writew(ms_readw(MSB250X_OTG0_AUTONAK0_CTRL), MSB250X_OTG0_AUTONAK0_CTRL); ++ ms_writew((ms_readw(MSB250X_OTG0_AUTONAK0_CTRL) | MSB250X_OTG0_AUTONAK0_AllowAck), MSB250X_OTG0_AUTONAK0_CTRL); ++ break; ++ case 1: ++ ms_writeb(ms_readb(MSB250X_OTG0_AUTONAK1_CTRL), MSB250X_OTG0_AUTONAK1_CTRL); ++ ms_writeb((ms_readb(MSB250X_OTG0_AUTONAK1_CTRL) | MSB250X_OTG0_AUTONAK1_AllowAck), MSB250X_OTG0_AUTONAK1_CTRL); ++ break; ++ case 2: ++ ms_writeb(ms_readw(MSB250X_OTG0_AUTONAK2_CTRL), MSB250X_OTG0_AUTONAK2_CTRL); ++ ms_writeb((ms_readw(MSB250X_OTG0_AUTONAK2_CTRL) | MSB250X_OTG0_AUTONAK2_AllowAck), MSB250X_OTG0_AUTONAK2_CTRL); ++ break; ++ } ++ //printk(KERN_DEBUG "[UDC][NAK][%d] allowAck\n", cfg); ++} ++EXPORT_SYMBOL(msb250x_udc_allowAck); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_request_handler +++------------------------------------------------------------------------------ ++| DESCRIPTION : dispatch request to use DMA or FIFO ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| _ep | x | | usb_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| _req | x | | usb_request struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++ ++struct msb250x_request * ++msb250x_request_handler(struct msb250x_ep* ep, ++ struct msb250x_request* req) ++{ ++ u32 bytes; ++ u16 pkt_num = 0; ++ ++ u8 ep_num = 0; ++ u8 csr = 0; ++ u8 intrusb = 0; ++ u8 is_last = 0; ++ ++ struct msb250x_udc *dev = ep->dev; ++ struct usb_ep* _ep = &ep->ep; ++ struct otg0_ep0_csr_l* csr_l = NULL; ++ struct otg0_ep_rxcsr_l* rxcsr_l = NULL; ++ struct otg0_ep_txcsr_l* txcsr_l = NULL; ++ struct otg0_usb_intr* st_intrusb = (struct otg0_usb_intr*) &intrusb; ++ ++ if (0 == ep->halted) ++ { ++ msb250x_set_ep_halt(ep, 1); ++ ++ intrusb = ms_readb(MSB250X_OTG0_INTRUSB_REG); ++ ++ if (1 == st_intrusb->bReset) ++ { ++ return req; ++ } ++ ++ bytes = req->req.length - req->req.actual; ++ ++ if (IS_ERR_OR_NULL(_ep->desc)) ++ { ++ csr = ms_readb(MSB250X_OTG0_EP0_CSR0_REG); ++ csr_l = (struct otg0_ep0_csr_l*) &csr; ++ ++ switch (ep->dev->ep0state) ++ { ++ case EP0_IDLE: ++ if (0 < dev->delay_status) ++ { ++ msb250x_ep0_clear_opr(); ++ dev->delay_status--; ++ is_last = 1; ++ } ++ ++ break; ++ case EP0_IN_DATA_PHASE: ++ if (0 == csr_l->bTxPktRdy) ++ { ++ bytes = min((u16)_ep->maxpacket, (u16)bytes); ++ ++ is_last = msb250x_udc_write_riu(ep, req, bytes); ++ ++ if (is_last) ++ { ++ msb250x_ep0_set_de_in(); ++ ep->dev->ep0state = EP0_IDLE; ++ } ++ else ++ { ++ msb250x_ep0_set_ipr(); ++ } ++ } ++ break; ++ ++ case EP0_OUT_DATA_PHASE: ++ if (1 == csr_l->bRxPktRdy) ++ { ++ u16 counts = ms_readw(MSB250X_OTG0_EP_RXCOUNT_L_REG(ep_num)); ++ ++ if (bytes < counts) ++ { ++ printk(KERN_WARNING "[UDC][%d] Bytes in fifo(0x%04x) is more than buffer size. buf/actual/length(0x%p/0x%04x/0x%04x)!\n", ++ ep_num, ++ counts, ++ req->req.buf, ++ req->req.actual, ++ req->req.length); ++ } ++ ++ bytes = min((u16)counts, (u16)bytes); ++ ++ is_last = msb250x_udc_read_riu(ep, req, bytes); ++ ++ if (is_last) ++ { ++ msb250x_ep0_set_de_out(); ++ ep->dev->ep0state = EP0_IDLE; ++ } ++ else ++ { ++ msb250x_ep0_clear_opr(); ++ } ++ } ++ ++ break; ++ ++ default: ++ printk(KERN_ERR " EP0 Request Error !!\n"); ++ } ++ ++ msb250x_set_ep_halt(ep, 0); ++ } ++ else ++ { ++ ep_num = usb_endpoint_num(_ep->desc); ++ ++ if (!usb_endpoint_xfer_bulk(_ep->desc)) ++ { ++ bytes = min((u16)(usb_endpoint_maxp_mult(_ep->desc) * _ep->maxpacket), (u16)bytes); ++ } ++ ++ if (usb_endpoint_dir_in(_ep->desc)) ++ { ++ txcsr_l = (struct otg0_ep_txcsr_l*) &csr; ++ csr = ms_readb(MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ ++ //if (0 == (txcsr_l->bTxPktRdy | txcsr_l->bFIFONotEmpty)) ++ if (0 == txcsr_l->bTxPktRdy) ++ { ++ if (0 == dev->using_dma || 0 != msb250x_dma_setup_control(_ep, req, bytes)) ++ { ++ is_last = msb250x_udc_write_riu(ep, req, bytes); ++ ep_set_ipr(ep_num); ++ } ++ } ++ } ++ else if (usb_endpoint_dir_out(_ep->desc)) ++ { ++ csr = ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ rxcsr_l = (struct otg0_ep_rxcsr_l*) &csr; ++ ++ if (usb_endpoint_xfer_bulk(_ep->desc)) ++ { ++ if (0 == rxcsr_l->bRxPktRdy) ++ { ++ pkt_num = (bytes + (_ep->maxpacket - 1)) / _ep->maxpacket; ++ ++ if (1 == ep->shortPkt) ++ { ++ udelay(125); ++ } ++ ++ #if defined(CONFIG_USB_AVOID_SHORT_PACKET_IN_BULK_OUT_WITH_DMA_FOR_ETHERNET) ++ #if 0 ++ if (MAX_ETHERNET_PACKET_SIZE < bytes) ++ { ++ pkt_num = (MAX_ETHERNET_PACKET_SIZE + (_ep->maxpacket - 1)) / _ep->maxpacket; ++ } ++ else ++ #endif ++ { ++ pkt_num = 1; ++ } ++ #endif ++ ++ //if (ep->ep.maxpacket >= req->req.length) ++ if (1 == pkt_num) ++ { ++ msb250x_udc_allowAck(ep->autoNAK_cfg); ++ ep->shortPkt = 0; ++ } ++ else ++ { ++ bytes = min((u16)(pkt_num * _ep->maxpacket), (u16)bytes); ++ ++ msb250x_dma_setup_control(&ep->ep, req, bytes); ++ msb250x_udc_ok2rcv_for_packets(ep->autoNAK_cfg, pkt_num); ++ ep->shortPkt = 1; ++ } ++ } ++ } ++ ++ if (1 == rxcsr_l->bRxPktRdy) ++ { ++ bytes = min((u16)bytes, (u16)ms_readw(MSB250X_OTG0_EP_RXCOUNT_L_REG(ep_num))); ++ ++ if (0 == dev->using_dma || 0 != msb250x_dma_setup_control(&ep->ep, req, bytes)) ++ { ++ is_last = msb250x_udc_read_riu(ep, req, bytes); ++ ep_set_opr(ep_num); ++ } ++ } ++ } ++ } ++ } ++ ++ if (1 == is_last) ++ { ++ req = NULL; ++ } ++ ++ return req; ++} ++EXPORT_SYMBOL(msb250x_request_handler); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_request_nuke +++------------------------------------------------------------------------------ ++| DESCRIPTION : dequeue ALL requests ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| ep | x | | msb250x_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| req | x | | msb250x_request struct point ++|--------------------+---+---+------------------------------------------------- ++| status | x | | reports completion code, zero or a negative errno +++--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_request_nuke(struct msb250x_udc *udc, ++ struct msb250x_ep *ep, int status) ++{ ++ /* Sanity check */ ++ if (&ep->queue == NULL) ++ return; ++ ++ while (!list_empty (&ep->queue)) ++ { ++ struct msb250x_request *req; ++ req = list_entry (ep->queue.next, struct msb250x_request, queue); ++ msb250x_request_done(ep, req, status); ++ } ++} ++EXPORT_SYMBOL(msb250x_request_nuke); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_request_continue +++------------------------------------------------------------------------------ ++| DESCRIPTION : Schedule the next packet for this EP ++| ++| RETURN : +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|----------------+---+---+----------------------------------------------------- ++| ep | x | | msb250x_ep struct point +++-------------- -+---+---+----------------------------------------------------- ++*/ ++void msb250x_request_continue(struct msb250x_ep *ep) ++{ ++ ++ //printk("msb250x_request_continue\n"); ++ ++ struct msb250x_request *req = NULL; ++ ++ if (likely(!list_empty(&ep->queue))) ++ { ++ req = list_entry(ep->queue.next, struct msb250x_request, queue); ++ msb250x_request_handler(ep, req); ++ } ++} ++ ++EXPORT_SYMBOL(msb250x_request_continue); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_request_done +++------------------------------------------------------------------------------ ++| DESCRIPTION : complete the usb request ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| ep | x | | msb250x_ep struct point ++|--------------------+---+---+------------------------------------------------- ++| req | x | | msb250x_request struct point ++|--------------------+---+---+------------------------------------------------- ++| status | x | | reports completion code, zero or a negative errno +++--------------------+---+---+------------------------------------------------- ++*/ ++ ++void msb250x_request_done(struct msb250x_ep *ep, ++ struct msb250x_request *req, int status) ++{ ++ struct msb250x_udc* dev = NULL; ++ ++ unsigned halted = ep->halted; ++ ++ dev = ep->dev; ++ ++ if(req==NULL) ++ { ++ printk(" EP[%d] REQ NULL\n", IS_ERR_OR_NULL(ep->ep.desc)? 0 : usb_endpoint_num(ep->ep.desc)); ++ return; ++ } ++ ++ if (ep0name != ep->ep.name && dev->using_dma) ++ { ++ msb250x_gadget_unmap_request(ep->gadget, &req->req, usb_endpoint_dir_in(ep->ep.desc)); ++ } ++ ++ list_del_init(&req->queue); ++ ++ if (likely (req->req.status == -EINPROGRESS)) ++ req->req.status = status; ++ else ++ status = req->req.status; ++ ++ msb250x_set_ep_halt(ep, 1); ++ spin_unlock(&dev->lock); ++ usb_gadget_giveback_request(&ep->ep, &req->req); ++ spin_lock(&dev->lock); ++ msb250x_set_ep_halt(ep, halted); ++} ++ ++EXPORT_SYMBOL(msb250x_request_done); ++ ++static irqreturn_t msb250x_udc_link_isr(struct msb250x_udc *dev) ++{ ++ u8 usb_status = 0; ++ u8 power = 0; ++ ++ struct otg0_usb_power* pst_power = (struct otg0_usb_power*) &power; ++ struct otg0_usb_intr* usb_st = (struct otg0_usb_intr*) &usb_status; ++ ++ usb_status = ms_readb(MSB250X_OTG0_INTRUSB_REG); ++ ms_writeb(usb_status, MSB250X_OTG0_INTRUSB_REG); ++ ++ power = ms_readb(MSB250X_OTG0_PWR_REG); ++ ++ /* RESET */ ++ //if (usb_status & MSB250X_OTG0_INTRUSB_RESET) ++ ++ if (1 == usb_st->bReset) ++ { ++ /* two kind of reset : ++ * - reset start -> pwr reg = 8 ++ * - reset end -> pwr reg = 0 ++ **/ ++ printk(KERN_INFO "[LINK] Bus reset.\r\n"); ++ #ifndef CONFIG_USB_FPGA_VERIFICATION ++ ms_writeb(0x10, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)); //TX-current adjust to 105%=> bit <4> set 1 ++ ms_writeb(0x02, (GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16) + 1)); // Pre-emphasis enable=> bit <1> set 1 ++ //ms_writeb(0x01, (GET_REG16_ADDR(UTMI_BASE_ADDR, 0x17) + 1)); //HS_TX common mode current enable (100mV)=> bit <7> set 1 ++ #endif ++ ++ if (dev->driver && dev->driver->disconnect && USB_STATE_DEFAULT <= dev->gadget.state) ++ { ++ spin_unlock(&dev->lock); ++ dev->driver->disconnect(&dev->gadget); ++ spin_lock(&dev->lock); ++ } ++ ++ //msb250x_udc_init_otg(dev); ++ ms_writeb(0, MSB250X_OTG0_FADDR_REG); ++ ++ dev->address = 0; ++ dev->ep0state = EP0_IDLE; ++ ++ //if (ms_readb(MSB250X_OTG0_PWR_REG)&MSB250X_OTG0_PWR_HS_MODE) ++ if (1 == pst_power->bHSMode) ++ { ++ dev->gadget.speed = USB_SPEED_HIGH; ++ printk(KERN_INFO "[LINK] High speed device\r\n"); ++ #ifndef CONFIG_USB_FPGA_VERIFICATION ++ ms_writew(0x0230, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)); //B2 analog parameter ++ #endif ++ } ++ else ++ { ++ dev->gadget.speed = USB_SPEED_FULL; ++ printk(KERN_INFO "[LINK] Full speed device\r\n"); ++ #ifndef CONFIG_USB_FPGA_VERIFICATION ++ ms_writew(0x0030, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)); //B2 analog parameter ++ #endif ++ } ++ ++ msb250x_udc_init_autoNAK_cfg(); ++ ++ usb_gadget_set_state(&dev->gadget, USB_STATE_DEFAULT); ++ } ++ ++ /* RESUME */ ++ //if (usb_status & MSB250X_OTG0_INTRUSB_RESUME) ++ if (1 == usb_st->bResume) ++ { ++ printk(KERN_INFO "[LINK] Resume\r\n"); ++ ++ if (dev->gadget.speed != USB_SPEED_UNKNOWN && ++ dev->driver && ++ dev->driver->resume) ++ { ++ spin_unlock(&dev->lock); ++ dev->driver->resume(&dev->gadget); ++ spin_lock(&dev->lock); ++ } ++ } ++ ++ /* SUSPEND */ ++ //if (usb_status & MSB250X_OTG0_INTRUSB_SUSPEND) ++ if (1 == usb_st->bSuspend) ++ { ++ printk(KERN_INFO "[LINK] Suspend\r\n"); ++ ++ //if (1 == pst_power->bSuspendMode) ++ { ++ if (dev->gadget.speed != USB_SPEED_UNKNOWN && ++ dev->driver && ++ dev->driver->suspend) ++ { ++ printk("call gadget->suspend\n"); ++ spin_unlock(&dev->lock); ++ dev->driver->suspend(&dev->gadget); ++ spin_lock(&dev->lock); ++ ++ dev->ep0state = EP0_IDLE; ++ ++ usb_gadget_set_state(&dev->gadget, USB_STATE_SUSPENDED); ++ } ++ ++ ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t msb250x_udc_ep_isr(struct msb250x_udc *dev) ++{ ++ u8 ep_num = 0; ++ ++ u8 usb_intr_rx = 0, usb_intr_tx = 0; ++ ++ usb_intr_rx = ms_readb(MSB250X_OTG0_INTRRX_REG); ++ usb_intr_tx = ms_readb(MSB250X_OTG0_INTRTX_REG); ++ ms_writeb(usb_intr_rx, MSB250X_OTG0_INTRRX_REG); ++ ms_writeb(usb_intr_tx, MSB250X_OTG0_INTRTX_REG); ++ ++ if (usb_intr_tx & MSB250X_OTG0_INTR_EP(0)) ++ { ++ msb250x_ep0_isr_handler(dev); ++ } ++ ++ for (ep_num = 1; MSB250X_MAX_ENDPOINTS > ep_num; ep_num++) ++ { ++ if ((usb_intr_rx | usb_intr_tx) & MSB250X_OTG0_INTR_EP(ep_num)) ++ { ++ msb250x_ep_isr_handler(dev, &dev->ep[ep_num]); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t msb250x_udc_dma_isr(struct msb250x_udc *dev) ++{ ++ u8 dma_ch = 0; ++ u8 dma_intr; ++ ++ dma_intr = ms_readb(MSB250X_OTG0_DMA_INTR); ++ ms_writeb(dma_intr, MSB250X_OTG0_DMA_INTR); ++ ++ if (dma_intr) ++ { ++ for (dma_ch = 0; dma_ch < MSB250X_USB_DMA_CHANNEL; dma_ch++) ++ { ++ if (dma_intr & (1 << dma_ch)) ++ { ++ msb250x_dma_isr_handler((dma_ch + 1), dev); ++ } ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t msb250x_udc_isr(int irq, void *_dev) ++{ ++ struct msb250x_udc *dev = _dev; ++ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->lock, flags); ++/* ++ ms_writeb(ms_readb(GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)) & ~BIT1, GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)); ++ ms_writeb(ms_readb(GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)) | BIT1, GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)); ++*/ ++ msb250x_udc_dma_isr(dev); ++ msb250x_udc_link_isr(dev); ++ msb250x_udc_ep_isr(dev); ++ //ms_writeb((ms_readb(GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)) & ~BIT1), GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)); ++ spin_unlock_irqrestore(&dev->lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_get_status +++------------------------------------------------------------------------------ ++| DESCRIPTION :get the USB device status ++| ++| RETURN :0 when success, error code in other case. +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev |x | | msb250x_udc struct point ++|--------------------+---+---+------------------------------------------------- ++| crq |x | | usb_ctrlrequest struct point +++--------------------+---+---+------------------------------------------------- ++*/ ++int msb250x_udc_get_status(struct msb250x_udc *dev, ++ struct usb_ctrlrequest *crq) ++{ ++ u8 status = 0; ++ u8 ep_num = crq->wIndex & 0x7F; ++ u8 is_in = crq->wIndex & USB_DIR_IN; ++ ++ switch (crq->bRequestType & USB_RECIP_MASK) ++ { ++ case USB_RECIP_INTERFACE: ++ break; ++ ++ case USB_RECIP_DEVICE: ++ status = dev->devstatus; ++ break; ++ ++ case USB_RECIP_ENDPOINT: ++ if (MSB250X_MAX_ENDPOINTS < ep_num || crq->wLength > 2) ++ return 1; ++ ++ if (ep_num == 0) ++ { ++ status = ms_readb(MSB250X_OTG0_EP0_CSR0_REG); ++ status &= MSB250X_OTG0_CSR0_SENDSTALL; ++ } ++ else ++ { ++ if (is_in) ++ { ++ status = ms_readb(MSB250X_OTG0_EP_TXCSR1_REG(ep_num)); ++ status &= MSB250X_OTG0_TXCSR1_SENDSTALL; ++ } ++ else ++ { ++ status = ms_readb(MSB250X_OTG0_EP_RXCSR1_REG(ep_num)); ++ status &= MSB250X_OTG0_RXCSR1_SENDSTALL; ++ } ++ } ++ ++ status = status ? 1 : 0; ++ break; ++ ++ default: ++ return 1; ++ } ++ ++ /* Seems to be needed to get it working. ouch :( */ ++ udelay(5); ++ ms_writeb(status & 0xFF, OTG0_EP_FIFO_ACCESS_L(0)); ++ ms_writeb(0, OTG0_EP_FIFO_ACCESS_L(0)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(msb250x_udc_get_status); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_disable +++------------------------------------------------------------------------------ ++| DESCRIPTION : disable udc ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev |x | | msb250x_udc struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++void msb250x_udc_disable(struct msb250x_udc *dev) ++{ ++ /* Disable all interrupts */ ++ ms_writeb(0x00, MSB250X_OTG0_INTRUSBE_REG); ++ ms_writeb(0x00, MSB250X_OTG0_INTRTXE_REG); ++ ms_writeb(0x00, MSB250X_OTG0_INTRRXE_REG); ++ ++ /* Clear the interrupt registers */ ++ /* All active interrupts will be cleared when this register is read */ ++ ms_writeb(ms_readb(MSB250X_OTG0_INTRUSB_REG), MSB250X_OTG0_INTRUSB_REG); ++ ms_writeb(ms_readb(MSB250X_OTG0_INTRTX_REG), MSB250X_OTG0_INTRTX_REG); ++ ms_writeb(ms_readb(MSB250X_OTG0_INTRRX_REG), MSB250X_OTG0_INTRRX_REG); ++ ++ /* Good bye, cruel world */ ++ msb250x_gadget_pullup_i(0); ++ ++ /* Set speed to unknown */ ++ dev->gadget.speed = USB_SPEED_UNKNOWN; ++ ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_reinit +++------------------------------------------------------------------------------ ++| DESCRIPTION : reinit the ep list ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev |x | | msb250x_udc struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++static void msb250x_udc_reinit(struct msb250x_udc *dev) ++{ ++ u8 ep_num = 0; ++ ++ /* device/ep0 records init */ ++ INIT_LIST_HEAD (&dev->gadget.ep_list); ++ INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); ++ ++ dev->gadget.speed = USB_SPEED_UNKNOWN; ++ ++ for (ep_num = 0; ep_num < MSB250X_MAX_ENDPOINTS; ep_num++) ++ { ++ struct msb250x_ep *ep = &dev->ep[ep_num]; ++ ++ list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); ++ //ep->dev = dev; ++ INIT_LIST_HEAD (&ep->queue); ++ ++ usb_ep_set_maxpacket_limit(&ep->ep, 1024); ++ ep->gadget = &dev->gadget; ++ } ++ ++ usb_ep_set_maxpacket_limit(&dev->ep[0].ep, 64); ++ dev->gadget.ep0 = &dev->ep[0].ep; ++ list_del_init(&dev->ep[0].ep.ep_list); ++} ++ ++void msb250x_udc_init_usb_ctrl(void) ++{ ++ u8 ctrl_l = 0; ++ struct usbc0_rst_ctrl_l* pst_usbc0_rst_ctrl_l = (struct usbc0_rst_ctrl_l*) &ctrl_l; ++ ++ // Reset OTG controllers ++ //USBC_REG_WRITE8(0, 0xC); ++ //USBC_REG_WRITE8(0, USBC_REG_READ8(0)|(OTG_BIT3|OTG_BIT2)); ++ ctrl_l = ms_readb(GET_REG16_ADDR(USBC_BASE_ADDR, 0)); ++ pst_usbc0_rst_ctrl_l->bOTG_RST = 1; ++ pst_usbc0_rst_ctrl_l->bREG_SUSPEND = 1; ++ ms_writeb(ctrl_l, GET_REG16_ADDR(USBC_BASE_ADDR, 0)); ++ ++ // Unlock Register R/W functions (RST_CTRL[6] = 1) ++ // Enter suspend (RST_CTRL[3] = 1) ++ //USBC_REG_WRITE8(0, 0x48); ++ //USBC_REG_WRITE8(0, (USBC_REG_READ8(0)&~(OTG_BIT2))|OTG_BIT6); ++ ctrl_l = ms_readb(GET_REG16_ADDR(USBC_BASE_ADDR, 0)); ++ pst_usbc0_rst_ctrl_l->bOTG_RST = 0; ++ pst_usbc0_rst_ctrl_l->bOTG_XIU_ENABLE = 1; ++ ms_writeb(ctrl_l, GET_REG16_ADDR(USBC_BASE_ADDR, 0)); ++ ++ printk(KERN_DEBUG "[GADGET] Init USB controller\n"); ++} ++ ++EXPORT_SYMBOL(msb250x_udc_init_usb_ctrl); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_init_otg +++------------------------------------------------------------------------------ ++| DESCRIPTION : enable udc ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev |x | | msb250x_udc struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++ ++#if defined(ENABLE_OTG_USB_NEW_MIU_SLE) ++static void msb250x_udc_init_MIU_sel(void) ++{ ++ printk("[miu] [%x] [%x] [%x] [%x].\n", USB_MIU_SEL0, USB_MIU_SEL1, USB_MIU_SEL2, USB_MIU_SEL3); ++ ms_writeb(USB_MIU_SEL0, GET_REG16_ADDR(USBC_BASE_ADDR, 0x0A)); //Setting MIU0 segment ++ ms_writeb(USB_MIU_SEL1, GET_REG16_ADDR(USBC_BASE_ADDR, 0x0B)); //Setting MIU1 segment ++ ms_writeb(USB_MIU_SEL2, GET_REG16_ADDR(USBC_BASE_ADDR, 0x0B) + 1); //Setting MIU2 segment ++ ms_writeb(USB_MIU_SEL3, GET_REG16_ADDR(USBC_BASE_ADDR, 0x0C)); //Setting MIU3 segment ++ ms_writeb((ms_readb(GET_REG16_ADDR(USBC_BASE_ADDR, 0x0C) + 1) | 0x1), GET_REG16_ADDR(USBC_BASE_ADDR, 0x0C) + 1); //Enable miu partition mechanism ++ ++#if 0//defined(DISABLE_MIU_LOW_BOUND_ADDR_SUBTRACT_ECO) ++ printk("[USB] enable miu lower bound address subtraction\n"); ++ writeb(readb((void*)(USBC_base+0x0F*2-1)) | 0x1, (void*)(USBC_base+0x0F*2-1)); ++#endif ++} ++#endif ++ ++void msb250x_udc_deinit_utmi(void) ++{ ++ //SETREG16(0x1f28420c, 0x0103); // bit0: RX sw reset; bit1: Tx sw reset; bit8: Tx FSM sw reset; ++ //SETREG16(0x1f284220, 0x1000); // bit12: pwr good reset ++ ms_writew(ms_readw(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03)) | BIT0 | BIT1 | BIT8, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03)); ++ ms_writew(ms_readw(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x08)) | BIT12, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x08)); ++ mdelay(1); ++ // clear reset ++ //CLRREG16(0x1f28420c, 0x0103); // bit0: RX sw reset; bit1: Tx sw reset; bit8: Tx FSM sw reset; ++ //CLRREG16(0x1f284220, 0x1000); // bit12: pwr good reset ++ ms_writew(ms_readw(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03)) & (~(BIT0 | BIT1 | BIT8)), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x03)); ++ ms_writew(ms_readw(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x08)) & (~BIT12), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x08)); ++ // power down utmi ++ //OUTREG16(0x1f284200, 0x7F03); ++ ms_writew(0x7F03, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x0)); ++ mdelay(5); ++ printk("[GADGET] Deinit phy\n"); ++} ++ ++void msb250x_udc_init_utmi(void) ++{ ++#if defined(ENABLE_OTG_USB_NEW_MIU_SLE) ++ msb250x_udc_init_MIU_sel(); ++#endif ++ ++ ms_writew(0x0C2F, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x4)); ++ ++ // Disable UHC and OTG controllers ++ //USBC_REG_WRITE8(0x4, USBC_REG_READ8(0x4)& (~0x3)); ++#if !defined(CONFIG_USB_MS_OTG) ++ // Enable OTG controller ++ ms_writeb(((ms_readb(GET_REG16_ADDR(USBC_BASE_ADDR, 0x01)) & ~(BIT0 | BIT1)) | BIT1), GET_REG16_ADDR(USBC_BASE_ADDR, 0x01)); ++#endif ++ ++#ifndef CONFIG_USB_FPGA_VERIFICATION ++#ifdef CONFIG_USB_ENABLE_UPLL ++ //UTMI_REG_WRITE16(0, 0x4000); ++ ms_writew(0x6BC3, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); // Turn on UPLL, reg_pdn: bit<9> reg_pdn: bit<15>, bit <2> ref_pdn ++ mdelay(1); ++ ms_writeb(0x69, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); // Turn on UPLL, reg_pdn: bit<9> ++ mdelay(2); ++ ms_writew(0x0001, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); //Turn all (including hs_current) use override mode ++ // Turn on UPLL, reg_pdn: bit<9> ++ mdelay(3); ++#else ++ // Turn on UTMI if it was powered down ++ if (0x0001 != ms_readw(GET_REG16_ADDR(UTMI_BASE_ADDR, 0))) ++ { ++ ms_writew(0x0001, GET_REG16_ADDR(UTMI_BASE_ADDR, 0)); //Turn all (including hs_current) use override mode ++ mdelay(3); ++ } ++#endif ++ ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x3c)) | 0x01), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x3c)); // set CA_START as 1 ++ mdelay(10); ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x3c)) & ~0x01), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x3c)); // release CA_START ++ while (0 == (ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x3c)) & 0x02)); // polling bit <1> (CA_END) ++ ++ //msb250x_udc_init_usb_ctrl(); ++ ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x06)) & 0x9F) | 0x40, GET_REG8_ADDR(UTMI_BASE_ADDR, 0x06)); //reg_tx_force_hs_current_enable ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x03)) | 0x28), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x03)); //Disconnect window select ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x03)) & 0xef), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x03)); //Disconnect window select ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x07)) & 0xfd), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x07)); //Disable improved CDR ++ ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x09)) | 0x81), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x09)); // UTMI RX anti-dead-loc, ISI effect improvement ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x15)) | 0x20), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x15)); // Chirp signal source select ++ ms_writeb((ms_readb(GET_REG8_ADDR(UTMI_BASE_ADDR, 0x0b)) | 0x80), GET_REG8_ADDR(UTMI_BASE_ADDR, 0x0b)); // set reg_ck_inv_reserved[6] to solve timing problem ++ ++ ++#if 0//defined(CONFIG_MSTAR_CEDRIC) ++ ms_writeb(0x10, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)); ++ ms_writeb(0x02, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16) + 1); ++ ms_writeb(0x81, GET_REG16_ADDR(UTMI_BASE_ADDR, 0x17) + 1); ++ //UTMI_REG_WRITE8(0x2c*2, 0x10); ++ //UTMI_REG_WRITE8(0x2d*2-1, 0x02); ++ //UTMI_REG_WRITE8(0x2f*2-1, 0x81); ++#else ++ //ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)) | 0x98), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)); ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)) | 0x10), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16)); ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16) + 1) | 0x02), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x16) + 1); ++ //ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x17)) | 0x10), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x17)); ++ //ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x17) + 1) | 0x01), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x17) + 1); ++ //UTMI_REG_WRITE8(0x2c*2, UTMI_REG_READ8(0x2c*2) |0x98); ++ //UTMI_REG_WRITE8(0x2d*2-1, UTMI_REG_READ8(0x2d*2-1) |0x02); ++ //UTMI_REG_WRITE8(0x2e*2, UTMI_REG_READ8(0x2e*2) |0x10); ++ //UTMI_REG_WRITE8(0x2f*2-1, UTMI_REG_READ8(0x2f*2-1) |0x01) ++#endif ++ ++ ++ ms_writeb((ms_readb(GET_REG16_ADDR(UTMI_BASE_ADDR, 0x02)) | 0x80), GET_REG16_ADDR(UTMI_BASE_ADDR, 0x02)); //avoid glitch ++#endif ++} ++ ++void msb250x_udc_reset_otg(void) ++{ ++ ms_writeb(ms_readb(MSB250X_OTG0_USB_CFG0_L) & ~MSB250X_OTG0_CFG0_SRST_N, MSB250X_OTG0_USB_CFG0_L); //low active ++ ms_writeb(ms_readb(MSB250X_OTG0_USB_CFG0_L) | MSB250X_OTG0_CFG0_SRST_N, MSB250X_OTG0_USB_CFG0_L); //default set as 1 ++} ++EXPORT_SYMBOL(msb250x_udc_reset_otg); ++ ++void msb250x_udc_init_otg(struct msb250x_udc *udc) ++{ ++ //u8 ep_num = 0; ++ u8 power = 0; ++ u8 usb_cfg_l = 0; ++ u8 usb_cfg_h = 0; ++ u8 usb_intr = 0; ++ ++ struct otg0_usb_cfg0_h* pst_usb_cfg0_h = (struct otg0_usb_cfg0_h*) &usb_cfg_h; ++ struct otg0_usb_cfg6_h* pst_usb_cfg6_h = NULL; ++ struct otg0_usb_power* pst_power = (struct otg0_usb_power*) &power; ++ struct otg0_usb_intr* pst_intr_usb = (struct otg0_usb_intr*) &usb_intr; ++ ++ //ms_writeb((ms_readb(MSB250X_OTG0_USB_CFG6_H) | (MSB250X_OTG0_CFG6_H_SHORT_MODE | MSB250X_OTG0_CFG6_H_BUS_OP_FIX | MSB250X_OTG0_CFG6_H_REG_MI_WDFIFO_CTRL)), MSB250X_OTG0_USB_CFG6_H); ++ ++ //ms_writeb(ms_readb(MSB250X_OTG0_USB_CFG1_H) | MSB250X_OTG0_CFG1_H_SHORT_ECO, MSB250X_OTG0_USB_CFG1_H); ++ usb_cfg_l = ms_readb(MSB250X_OTG0_USB_CFG0_L); ++ usb_cfg_h = ms_readb(MSB250X_OTG0_USB_CFG0_H); ++ ++ pst_usb_cfg0_h->bDMPullDown = 1; ++ ms_writeb(usb_cfg_h, MSB250X_OTG0_USB_CFG0_H); //Enable DM pull down ++ //printk("[UDC] Enable DM pull down\n"); ++ ++ //USB_REG_WRITE16(0x100, USB_REG_READ16(0x100)|0x8000); /* Disable DM pull-down */ ++ ++ // Set FAddr to 0 ++ ms_writeb(0, MSB250X_OTG0_FADDR_REG); ++ ++ pst_usb_cfg6_h = (struct otg0_usb_cfg6_h*) &usb_cfg_h; ++ usb_cfg_h = ms_readb(MSB250X_OTG0_USB_CFG6_H); ++ ++ pst_usb_cfg6_h->bINT_WR_CLR_EN = 1; ++ pst_usb_cfg6_h->bBusOPFix = 1; ++ pst_usb_cfg6_h->bShortMode = 1; ++ pst_usb_cfg6_h->bREG_MI_WDFIFO_CTRL = 1; ++ ms_writeb(usb_cfg_h, MSB250X_OTG0_USB_CFG6_H); ++ ++ /* ++ USB_REG_WRITE8(M_REG_CFG6_H, USB_REG_READ8(M_REG_CFG6_H) | 0x08); ++ USB_REG_WRITE8(M_REG_CFG6_H, USB_REG_READ8(M_REG_CFG6_H) | 0x40); ++ */ ++ ++ //while(0x18 != (USB_REG_READ8(M_REG_DEVCTL) & 0x18)); ++ ++ power = ms_readb(MSB250X_OTG0_PWR_REG); ++ ++ pst_power->bSuspendMode = 0; ++ pst_power->bSoftConn = 0; ++ ++ if (USB_SPEED_HIGH == udc->gadget.max_speed) ++ { ++ pst_power->bHSEnab = 1; ++ } ++ else ++ { ++ pst_power->bHSEnab = 0; ++ } ++ ms_writeb(power, MSB250X_OTG0_PWR_REG); ++ ++ ms_writeb(0, MSB250X_OTG0_DEVCTL_REG); ++ ++ usb_intr = 0xff; ++ pst_intr_usb->bConn = 0; ++ pst_intr_usb->bSOF = 0; ++ ms_writeb(usb_intr, MSB250X_OTG0_INTRUSB_REG); ++ //printk("[UDC] Enable usb interrupt\n"); ++ ++ ms_readb(MSB250X_OTG0_INTRUSB_REG); ++ ++ // Flush the next packet to be transmitted/ read from the endpoint 0 FIFO ++ ms_writeb(0, MSB250X_OTG0_INDEX_REG); ++ ms_writeb(0x1 , MSB250X_OTG0_CSR0_FLSH_REG); ++ ++ ms_writeb(0x01, MSB250X_OTG0_INTRTXE_REG); ++ ms_writeb(0x01, MSB250X_OTG0_INTRRXE_REG); ++ ++ ms_readb(MSB250X_OTG0_INTRTXE_REG); ++ //ms_readb(MSB250X_OTG0_INTRRXE_REG); ++} ++EXPORT_SYMBOL(msb250x_udc_init_otg); ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_utmi_init +++------------------------------------------------------------------------------ ++| DESCRIPTION : initial the UTMI interface ++| ++| RETURN : NULL +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++*/ ++#if 0 ++static void msb250x_utmi_init(void) ++{ ++ u32 temp; ++ ++ temp=ms_readw(UTMI_BASE_ADDR + 0x0C) | 0x0040; ++ temp &= 0xDBFD; ++ ms_writew(temp, UTMI_BASE_ADDR + 0x0C); ++ ++ temp = ms_readb(UTMI_BASE_ADDR + 0x11) | 0x62; ++ ms_writeb(temp, UTMI_BASE_ADDR + 0x11); ++ ++ temp = ms_readb(UTMI_BASE_ADDR + 0x4D) | 0x08; ++ temp &= 0xFB; ++ ms_writeb(temp, UTMI_BASE_ADDR + 0x4D); ++ ++ temp = ms_readb(UTMI_BASE_ADDR + 0x51) | 0x08; ++ ms_writeb(temp, UTMI_BASE_ADDR + 0x51); ++ ++ temp = ms_readb(UTMI_BASE_ADDR + 0x54) & 0xF0; ++ ms_writeb(temp, UTMI_BASE_ADDR + 0x54); ++ ++ temp=ms_readw(UTMI_BASE_ADDR + 0x58) | 0x0791; ++ temp &= 0xFFCD; ++ ms_writew(temp, UTMI_BASE_ADDR + 0x58); ++ ++ temp = ms_readb(UTMI_BASE_ADDR + 0x5D) | 0x0E; ++ ms_writeb(temp, UTMI_BASE_ADDR + 0x5D); ++ ++ while((ms_readb(UTMI_BASE_ADDR + 0x60) & 0x0001) == 0); ++ ++ temp = ms_readb(USBC_BASE_ADDR + 0x04) | 0x02; ++ ms_writeb(temp, USBC_BASE_ADDR + 0x04); ++ ++ temp = ms_readb(OTG0_BASE_ADDR + 0x100) & 0xFE; /* Reset OTG */ ++ ms_writeb(temp, OTG0_BASE_ADDR + 0x100); ++ ++ temp = ms_readb(OTG0_BASE_ADDR + 0x100) | 0x01; ++ ms_writeb(temp, OTG0_BASE_ADDR + 0x100); ++ ++ temp = ms_readb(OTG0_BASE_ADDR + 0x118) | 0x01; ++ ms_writeb(temp, OTG0_BASE_ADDR + 0x118); ++} ++#endif ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : The generic driver interface function which called for initial udc ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pdev |x | | platform_device struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++ ++static int msb250x_udc_probe(struct platform_device *pdev) ++{ ++ struct msb250x_udc *dev = &memory; ++ int retval = 0; ++ int irq = -1; ++ ++ spin_lock_init(&dev->lock); ++ ++ dev->gadget.dev.parent = &pdev->dev; ++ dev->pdev = pdev; ++ ++ platform_set_drvdata(pdev, dev); ++ ++ msb250x_udc_disable(dev); ++ ++ msb250x_udc_reinit(dev); ++ ++ /* irq setup after old hardware state is cleaned up */ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ ++ if (0 != (retval = request_irq(irq/*INT_MS_OTG*/, msb250x_udc_isr, 0, sg_gadget_name, dev))) ++ { ++ printk(KERN_ERR "[DRV] request_irq fail. irq/err(%d/%d)\n", irq, retval); ++ return -EBUSY; ++ } ++ ++ dev->got_irq = 1; ++ printk(KERN_INFO "[DRV] %s irq --> %d\n", pdev->name, irq); ++ ++ if (0 != usb_add_gadget_udc(&pdev->dev, &dev->gadget)) ++ { ++ printk(KERN_ERR "[DRV] Error in probe.\n"); ++ return -EBUSY; ++ } ++ ++ dev->using_dma = (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))? 1 : 0; ++ ++ //msb250x_udc_init_otg(udc); ++ msb250x_udc_init_utmi(); ++ usb_gadget_set_state(&dev->gadget, USB_STATE_POWERED); ++#if 0 ++ MDrv_GPIO_PadVal_Set(76, PINMUX_FOR_GPIO_MODE); ++ ms_writeb(ms_readb(GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)) & ~BIT0, GET_REG8_ADDR(REG_ADDR_BASE_PM_GPIO, 0X94)); ++#endif ++ printk(KERN_INFO "[DRV] complete porbe\n"); ++ return retval; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : The generic driver interface function which called for disable udc ++| ++| RETURN : zero on success, else negative error code +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pdev |x | | platform_device struct point ++|--------------------+---+---+------------------------------------------------- ++*/ ++static int msb250x_udc_remove(struct platform_device *pdev) ++{ ++ struct msb250x_udc *dev = platform_get_drvdata(pdev); ++ int irq; ++ ++ if (!dev->driver) ++ return -EBUSY; ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if(dev->got_irq) ++ { ++ //printk("free irq: %d \n", udc->irq); ++ free_irq(irq, dev); ++ dev->got_irq = 0; ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ usb_del_gadget_udc(&dev->gadget); ++ ++ printk(KERN_INFO "[UDC] remove ok\n"); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int msb250x_udc_suspend(struct platform_device *pdev, pm_message_t message) ++{ ++ struct msb250x_udc *udc = platform_get_drvdata(pdev); ++ ++ // disable udc ++ msb250x_udc_disable(udc); ++ ++ // disable power ++ ms_writeb(0, MSB250X_OTG0_PWR_REG); ++ return 0; ++} ++ ++int msb250x_udc_resume(struct platform_device *pdev) ++{ ++ struct msb250x_udc *udc = platform_get_drvdata(pdev); ++ ++ { ++ if (udc->driver) ++ { ++ // enable udc ++ msb250x_udc_reset_otg(); ++ msb250x_udc_init_otg(udc); ++ mdelay(1); ++ } ++ } ++ return 0; ++} ++#else ++#define msb250x_udc_suspend NULL ++#define msb250x_udc_resume NULL ++#endif ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : msb250x_udc_init +++------------------------------------------------------------------------------ ++| DESCRIPTION : The generic driver interface function for register this driver ++| to Linux Kernel. ++| ++| RETURN : 0 when success, error code in other case. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| | | | +++--------------------+---+---+------------------------------------------------- ++*/ ++ ++ ++static struct of_device_id mstar_udc_of_device_ids[] = ++{ ++ {.compatible = "sstar,infinity-udc"}, ++ {}, ++}; ++ ++static struct platform_driver ss_udc_driver = ++{ ++ .probe = msb250x_udc_probe, ++ .remove = msb250x_udc_remove, ++#ifdef CONFIG_PM ++ .suspend = msb250x_udc_suspend, ++ .resume = msb250x_udc_resume, ++#endif ++ .driver = { ++ .name = "soc:Sstar-udc", ++ .of_match_table = mstar_udc_of_device_ids, ++// .bus = &platform_bus_type, ++ } ++}; ++ ++module_platform_driver(ss_udc_driver); ++ ++MODULE_AUTHOR(DRIVER_AUTHOR); ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_VERSION(DRIVER_VERSION); ++MODULE_LICENSE("GPL"); ++ ++ ++//arch_initcall(ms_udc_device_init); ++//fs_initcall(msb250x_udc_init); //use fs_initcall due to this should be earlier than ADB module_init ++//module_exit(msb250x_udc_exit); ++ ++//MODULE_ALIAS(DRIVER_NAME); ++//MODULE_LICENSE("GPL"); ++//MODULE_DESCRIPTION(DRIVER_DESC); +diff --git a/drivers/sstar/usb/host/Makefile b/drivers/sstar/usb/host/Makefile +new file mode 100755 +index 000000000000..4f13e7eb8ba2 +--- /dev/null ++++ b/drivers/sstar/usb/host/Makefile +@@ -0,0 +1,7 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++ ++#ifneq ($(wildcard drivers/sstar/usb/$(CONFIG_SSTAR_CHIP_NAME)/),) ++obj-$(CONFIG_MS_USB_OLD_PLATFORM) += $(CONFIG_SSTAR_CHIP_NAME)/ ++#endif ++ ++obj-y += $(CONFIG_SSTAR_CHIP_NAME)/ +diff --git a/drivers/sstar/usb/host/bc-mstar.c b/drivers/sstar/usb/host/bc-mstar.c +new file mode 100644 +index 000000000000..f94c56c93a0b +--- /dev/null ++++ b/drivers/sstar/usb/host/bc-mstar.c +@@ -0,0 +1,152 @@ ++/* ++ * Mstar battery charger ++ * Copyright (C) 2012 MStar Inc. ++ * Date: Dec 2012 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "bc-mstar.h" ++#include "ehci-mstar.h" ++ ++void usb_bc_enable(struct usb_hcd *hcd, bool enable) ++{ ++ if(hcd->bc_base == 0) ++ { ++ //printk("This IC do not support USB BC funciton (%s)\n", __func__); ++ return; ++ } ++ ++ if (enable) { ++ printk("BC enable \n"); ++ writeb(readb((void *)(hcd->utmi_base+(0x1*2-1))) | 0x40, (void *)(hcd->utmi_base+(0x1*2-1))); //IREF_PDN=1¡¦b1. (utmi+0x01[6] ) ++ writeb(readb((void *)(hcd->bc_base+(0x3*2-1))) | 0x40, (void *)(hcd->bc_base+(0x3*2-1))); // [6]= reg_host_bc_en ++ writeb(readb((void *)(hcd->bc_base+(0xc*2))) | 0x40, (void *)(hcd->bc_base+(0xc*2))); // [6]= reg_into_host_bc_sw_tri ++ writew(0x0000, (void *)(hcd->bc_base)); // [15:0] = bc_ctl_ov_en ++ writeb(readb((void *)(hcd->bc_base+(0xa*2))) | 0x80, (void *)(hcd->bc_base+(0xa*2))); // [7]=reg_bc_switch_en ++ hcd->bc_enable_flag = true; ++ } ++ else { ++ // disable BC ++ printk("BC disable \n"); ++ writeb(readb((void *)(hcd->bc_base+(0xc*2))) & (u8)(~0x40), (void *)(hcd->bc_base+(0xc*2))); // [6]= reg_into_host_bc_sw_tri ++ writeb(readb((void *)(hcd->bc_base+(0x3*2-1))) & (u8)(~0x40), (void *)(hcd->bc_base+(0x3*2-1))); // [6]= reg_host_bc_en ++ writeb(readb((void *)(hcd->utmi_base+(0x1*2-1))) & (u8)(~0x40), (void *)(hcd->utmi_base+(0x1*2-1))); //IREF_PDN=1¡¦b1. (utmi+0x01[6] ) ++ hcd->bc_enable_flag = false; ++ } ++ ++} ++ ++void usb_power_saving_enable(struct usb_hcd *hcd, bool enable) ++{ ++ ++ if (enable) { ++ ++ //printk("utmi off\n"); ++ ++ if (hcd->utmi_base != 0) ++ { ++ //([0]: power down override, [1]:Termination override, [6]:15Kohm pull low for dp, [7] :15Kohm pull low for dm) ++ writeb(readb((void*)(hcd->utmi_base)) | (BIT1|BIT6|BIT7), (void*) (hcd->utmi_base)); ++ /* new HW term overwrite: on */ ++ writeb(readb((void*)(hcd->utmi_base+0x52*2)) | (BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0), (void*) (hcd->utmi_base+0x52*2)); ++ //([2]:TED power down, [3]Preamp power down, [6]TX power down) ++ writeb(readb((void*)(hcd->utmi_base+0x1*2-1)) | (BIT2|BIT3|BIT6), (void*) (hcd->utmi_base+0x1*2-1)); ++ } ++ ++ #if !defined(ENABLE_BATTERY_CHARGE) ++ if (hcd->bc_base != 0) ++ { ++ //BC power down ++ writeb(0xFF, (void*) (hcd->bc_base)); ++ } ++ #endif ++ ++ } ++ else { ++ ++ //printk("utmi on\n"); ++ ++ if (hcd->utmi_base != 0) ++ { ++ //([0]: power down override, [1]:Termination override, [6]:15Kohm pull low for dp, [7] :15Kohm pull low for dm) ++ writeb(readb((void*)(hcd->utmi_base)) & (u8)(~(BIT1|BIT6|BIT7)), (void*) (hcd->utmi_base)); ++ /* new HW term overwrite: off */ ++ writeb(readb((void*)(hcd->utmi_base+0x52*2)) & (u8)(~(BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0)), (void*) (hcd->utmi_base+0x52*2)); ++ //([2]:TED power down, [3]Preamp power down, [6]TX power down) ++ writeb(readb((void*)(hcd->utmi_base+0x1*2-1)) & (u8)(~(BIT2|BIT3|BIT6)), (void*) (hcd->utmi_base+0x1*2-1)); ++ } ++ ++ #if !defined(ENABLE_BATTERY_CHARGE) ++ if (hcd->bc_base != 0) ++ { ++ //BC power on ++ writeb(0, (void*) (hcd->bc_base)); ++ } ++ #endif ++ ++ } ++} ++ ++EXPORT_SYMBOL_GPL(usb_bc_enable); ++EXPORT_SYMBOL_GPL(usb_power_saving_enable); ++ ++#ifdef USB3_MAC_SRAM_POWER_DOWN_ENABLE ++void usb30mac_sram_power_saving(struct usb_hcd *hcd, bool enable) ++{ ++ bool usb3_sram_pd = !!(readw((void*)USB3_MAC_SRAM_CTRL_ADDR(hcd)) & USB3_MAC_SRAM_CTRL_BIT(hcd)); ++ ++ if (-1 == USB3_MAC_SRAM_CTRL_BIT(hcd)) { ++ printk("[USB3][SRAM PD] CTRL_BIT error!\n"); ++ BUG(); ++ } ++ ++ if ((enable ^ usb3_sram_pd) == 0) ++ return; ++ ++ if (enable) { ++ printk("usb3 port %d sram off\n", hcd->port_index); ++ writew(readw((void*) USB3_MAC_SRAM_CTRL_ADDR(hcd)) | (u16)USB3_MAC_SRAM_CTRL_BIT(hcd), (void*) USB3_MAC_SRAM_CTRL_ADDR(hcd)); ++ } ++ else { ++ printk("usb3 port %d sram on\n", hcd->port_index); ++ writew(readw((void*) USB3_MAC_SRAM_CTRL_ADDR(hcd)) & (u16)(~USB3_MAC_SRAM_CTRL_BIT(hcd)), (void*) USB3_MAC_SRAM_CTRL_ADDR(hcd)); ++ } ++ //printk("[USB DBG] SRAM PD Reg value 0x%x\n", readw((void*)USB3_MAC_SRAM_CTRL_ADDR(hcd)) & USB3_MAC_SRAM_CTRL_BIT(hcd)); ++} ++EXPORT_SYMBOL_GPL(usb30mac_sram_power_saving); ++#endif ++ ++#ifdef USB_MAC_SRAM_POWER_DOWN_ENABLE ++void usb20mac_sram_power_saving(struct usb_hcd *hcd, bool enable) ++{ ++ bool usb2_sram_pd = !!(readw((void*)USB_MAC_SRAM_CTRL_ADDR(hcd)) & USB_MAC_SRAM_CTRL_BIT(hcd)); ++ ++ if (-1 == USB_MAC_SRAM_CTRL_BIT(hcd)) { ++ printk("[USB2][SRAM PD] CTRL_BIT error!\n"); ++ BUG(); ++ } ++ ++ if (USB_MAC_SRAM_CTRL_BIT(hcd) == 0) ++ return; ++ ++ if ((enable ^ usb2_sram_pd) == 0) ++ return; ++ ++ if (enable) { ++ printk("usb2 port %d sram off\n", hcd->port_index); ++ writew(readw((void*) USB_MAC_SRAM_CTRL_ADDR(hcd)) | (u16)USB_MAC_SRAM_CTRL_BIT(hcd), (void*) USB_MAC_SRAM_CTRL_ADDR(hcd)); ++ } ++ else { ++ printk("usb2 port %d sram on\n", hcd->port_index); ++ writew(readw((void*) USB_MAC_SRAM_CTRL_ADDR(hcd)) & (u16)(~USB_MAC_SRAM_CTRL_BIT(hcd)), (void*) USB_MAC_SRAM_CTRL_ADDR(hcd)); ++ } ++ //printk("[USB DBG] SRAM PD Reg value 0x%x\n", readw((void*)USB_MAC_SRAM_CTRL_ADDR(hcd)) & USB_MAC_SRAM_CTRL_BIT(hcd)); ++} ++EXPORT_SYMBOL_GPL(usb20mac_sram_power_saving); ++#endif +diff --git a/drivers/sstar/usb/host/bc-mstar.h b/drivers/sstar/usb/host/bc-mstar.h +new file mode 100644 +index 000000000000..0e01969f5b14 +--- /dev/null ++++ b/drivers/sstar/usb/host/bc-mstar.h +@@ -0,0 +1,11 @@ ++#ifndef __BC_MSTAR_H ++#define __BC_MSTAR_H ++ ++ ++extern void usb_bc_enable(struct usb_hcd *hcd, bool enable); ++extern int apple_charger_support(struct usb_hcd *hcd, struct usb_device *udev); ++ ++extern void usb_power_saving_enable(struct usb_hcd *hcd, bool enable); ++extern void usb20mac_sram_power_saving(struct usb_hcd *hcd, bool enable); ++extern void usb30mac_sram_power_saving(struct usb_hcd *hcd, bool enable); ++#endif +diff --git a/drivers/sstar/usb/host/ehci-mstar.c b/drivers/sstar/usb/host/ehci-mstar.c +new file mode 100755 +index 000000000000..7b94bca99e99 +--- /dev/null ++++ b/drivers/sstar/usb/host/ehci-mstar.c +@@ -0,0 +1,1103 @@ ++/* ++* ehci-mstar.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "../../../usb/host/ehci.h" ++#include "ehci-mstar.h" ++#include "xhci-mstar.h" ++#include "bc-mstar.h" ++#include "mstar-lib.h" ++#include "usb_pad.h" ++//#include "../../sstar/include/ms_platform.h" ++ ++static struct hc_driver __read_mostly ehci_mstar_hc_driver; ++ ++#if defined(DYNAMIC_MIU_SIZE_MAPPING) ++uintptr_t TO_MIU_SIZE(MIU_DDR_SIZE miu_size) ++{ ++ uintptr_t retval; ++ switch(miu_size) ++ { ++ case E_MIU_DDR_2MB: ++ retval = 0x00200000; ++ break; ++ case E_MIU_DDR_4MB: ++ retval = 0x00400000; ++ break; ++ case E_MIU_DDR_8MB: ++ retval = 0x00800000; ++ break; ++ case E_MIU_DDR_16MB: ++ retval = 0x01000000; ++ break; ++ case E_MIU_DDR_32MB: ++ retval = 0x02000000; ++ break; ++ case E_MIU_DDR_64MB: ++ retval = 0x04000000; ++ break; ++ case E_MIU_DDR_128MB: ++ retval = 0x08000000; ++ break; ++ case E_MIU_DDR_256MB: ++ retval = 0x10000000; ++ break; ++ case E_MIU_DDR_512MB: ++ retval = 0x20000000; ++ break; ++ case E_MIU_DDR_1024MB: ++ retval = 0x40000000; ++ break; ++ case E_MIU_DDR_2048MB: ++ retval = 0x80000000; ++ break; ++ default: ++ retval = 0; ++ } ++ return retval; ++} ++ ++uintptr_t MIU0_PHY_BASE_ADDR; ++uintptr_t MIU0_SIZE; ++uintptr_t MIU1_PHY_BASE_ADDR; ++uintptr_t MIU1_SIZE; ++uintptr_t MIU2_PHY_BASE_ADDR; ++uintptr_t MIU2_SIZE; ++uintptr_t MIU3_PHY_BASE_ADDR; ++uintptr_t MIU3_SIZE; ++EXPORT_SYMBOL(MIU0_PHY_BASE_ADDR); ++EXPORT_SYMBOL(MIU0_SIZE); ++EXPORT_SYMBOL(MIU1_PHY_BASE_ADDR); ++EXPORT_SYMBOL(MIU1_SIZE); ++EXPORT_SYMBOL(MIU2_PHY_BASE_ADDR); ++EXPORT_SYMBOL(MIU2_SIZE); ++EXPORT_SYMBOL(MIU3_PHY_BASE_ADDR); ++EXPORT_SYMBOL(MIU3_SIZE); ++ ++u8 USB_MIU_SEL0; ++u8 USB_MIU_SEL1; ++u8 USB_MIU_SEL2; ++u8 USB_MIU_SEL3; ++EXPORT_SYMBOL(USB_MIU_SEL0); ++EXPORT_SYMBOL(USB_MIU_SEL1); ++EXPORT_SYMBOL(USB_MIU_SEL2); ++EXPORT_SYMBOL(USB_MIU_SEL3); ++ ++u8 TO_MIU_HW_SEL(uintptr_t phy_start, uintptr_t miu_size) ++{ ++ u8 start_blk; ++ u8 span_blk; ++ ++ if(miu_size == 0) ++ return USB_MIU_SEL_NULL; ++ ++ if(miu_size%USB_MIU_SEL_BLK) ++ printk("[USB] Warning miu size 0x%x not mutiple of blk 0x%x\n", ++ (unsigned int)miu_size, (unsigned int)USB_MIU_SEL_BLK); ++ ++ start_blk = phy_start / USB_MIU_SEL_BLK; ++ span_blk = (miu_size-1) / USB_MIU_SEL_BLK; ++ ++ return ((start_blk+span_blk) << 4) | start_blk; ++} ++ ++int MIU_dynamic_size_init(void) ++{ ++ MIU_DDR_SIZE size_miu0 = 0x0; ++ MIU_DDR_SIZE size_miu1 = 0x0; ++ MIU_DDR_SIZE size_miu2 = 0x0; ++ MIU_DDR_SIZE size_miu3 = 0x0; ++ uintptr_t configed_addr = (uintptr_t)USB_MIU_PHY_START; ++ ++ USB_MIU_SEL0 = 0x0; ++ USB_MIU_SEL1 = 0x0; ++ USB_MIU_SEL2 = 0x0; ++ USB_MIU_SEL3 = 0x0; ++ ++ /* get MIUs size */ ++ if(!MDrv_MIU_Dram_ReadSize(0, &size_miu0)) ++ printk("[USB] request MIU0 Size fail\n"); ++ else ++ MIU0_SIZE = TO_MIU_SIZE(size_miu0); ++ ++ if(!MDrv_MIU_Dram_ReadSize(1, &size_miu1)) ++ printk("[USB] request MIU1 Size fail\n"); ++ else ++ MIU1_SIZE = TO_MIU_SIZE(size_miu1); ++ ++ if(!MDrv_MIU_Dram_ReadSize(2, &size_miu2)) ++ printk("[USB] request MIU2 Size fail\n"); ++ else ++ MIU2_SIZE = TO_MIU_SIZE(size_miu2); ++ ++ if(!MDrv_MIU_Dram_ReadSize(3, &size_miu3)) ++ printk("[USB] request MIU3 Size fail\n"); ++ else ++ MIU3_SIZE = TO_MIU_SIZE(size_miu3); ++ ++ printk("[USB] get RAW MIU size:\n [0x%x] [0x%x] [0x%x] [0x%x]\n", ++ (unsigned int)MIU0_SIZE, (unsigned int)MIU1_SIZE, ++ (unsigned int)MIU2_SIZE, (unsigned int)MIU3_SIZE); ++ ++ /* set USB phy addr*/ ++ /* config MIU0 */ ++ MIU0_PHY_BASE_ADDR = configed_addr; ++ ++ if(configed_addr + MIU0_SIZE > USB_HW_MAX_SIZE) ++ { ++ MIU0_SIZE = USB_HW_MAX_SIZE - configed_addr; ++ } ++ ++ configed_addr += ((MIU0_SIZE+USB_MIU_SEL_BLK-1)/USB_MIU_SEL_BLK)*USB_MIU_SEL_BLK; ++ ++ /* config MIU1 */ ++ MIU1_PHY_BASE_ADDR = configed_addr; ++ ++ if(configed_addr + MIU1_SIZE > USB_HW_MAX_SIZE) ++ { ++ MIU1_SIZE = USB_HW_MAX_SIZE - configed_addr; ++ } ++ ++ configed_addr += ((MIU1_SIZE+USB_MIU_SEL_BLK-1)/USB_MIU_SEL_BLK)*USB_MIU_SEL_BLK; ++ ++ /* config MIU2 */ ++ MIU2_PHY_BASE_ADDR = configed_addr; ++ ++ if(configed_addr + MIU2_SIZE > USB_HW_MAX_SIZE) ++ { ++ MIU2_SIZE = USB_HW_MAX_SIZE - configed_addr; ++ } ++ ++ configed_addr += ((MIU2_SIZE+USB_MIU_SEL_BLK-1)/USB_MIU_SEL_BLK)*USB_MIU_SEL_BLK; ++ ++ /* config MIU3 */ ++ MIU3_PHY_BASE_ADDR = configed_addr; ++ ++ if(configed_addr + MIU3_SIZE > USB_HW_MAX_SIZE) ++ { ++ MIU3_SIZE = USB_HW_MAX_SIZE - configed_addr; ++ } ++ ++ printk("[USB] Config USB Phy:\n"); ++ printk(" MIU0: addr:%p szie 0x%x\n", ++ (void*)MIU0_PHY_BASE_ADDR, (unsigned int)MIU0_SIZE); ++ printk(" MIU1: addr:%p szie 0x%x\n", ++ (void*)MIU1_PHY_BASE_ADDR, (unsigned int)MIU1_SIZE); ++ printk(" MIU2: addr:%p szie 0x%x\n", ++ (void*)MIU2_PHY_BASE_ADDR, (unsigned int)MIU2_SIZE); ++ printk(" MIU3: addr:%p szie 0x%x\n", ++ (void*)MIU3_PHY_BASE_ADDR, (unsigned int)MIU3_SIZE); ++ ++ USB_MIU_SEL0 = TO_MIU_HW_SEL(MIU0_PHY_BASE_ADDR, MIU0_SIZE); ++ USB_MIU_SEL1 = TO_MIU_HW_SEL(MIU1_PHY_BASE_ADDR, MIU1_SIZE); ++ USB_MIU_SEL2 = TO_MIU_HW_SEL(MIU2_PHY_BASE_ADDR, MIU2_SIZE); ++ USB_MIU_SEL3 = TO_MIU_HW_SEL(MIU3_PHY_BASE_ADDR, MIU3_SIZE); ++ ++ return 0; ++} ++#endif ++ ++#if defined(ENABLE_USB_NEW_MIU_SLE) ++void MIU_select_setting_ehc(uintptr_t USBC_base) ++{ ++ printk("[USB] config miu select [%02x] [%02x] [%02x] [%02x]\n", USB_MIU_SEL0, USB_MIU_SEL1, USB_MIU_SEL2, USB_MIU_SEL3); ++ writeb(USB_MIU_SEL0, (void*)(USBC_base+0x14*2)); //Setting MIU0 segment ++ writeb(USB_MIU_SEL1, (void*)(USBC_base+0x16*2)); //Setting MIU1 segment ++ writeb(USB_MIU_SEL2, (void*)(USBC_base+0x17*2-1)); //Setting MIU2 segment ++ writeb(USB_MIU_SEL3, (void*)(USBC_base+0x18*2)); //Setting MIU3 segment ++ writeb(readb((void*)(USBC_base+0x19*2-1)) | BIT0, (void*)(USBC_base+0x19*2-1)); //Enable miu partition mechanism ++#if !defined(DISABLE_MIU_LOW_BOUND_ADDR_SUBTRACT_ECO) ++ printk("[USB] enable miu lower bound address subtraction\n"); ++ writeb(readb((void*)(USBC_base+0x0F*2-1)) | BIT0, (void*)(USBC_base+0x0F*2-1)); ++#endif ++} ++#endif ++ ++//extern int Enable_USB_VBUS(int param); ++ ++void Titania3_series_start_ehc(uintptr_t UTMI_base, uintptr_t USBC_base, uintptr_t UHC_base, unsigned int flag) ++{ ++ printk("Titania3_series_start_ehc start\n"); ++ ++ writew(0x0001, (void*) (UTMI_base+0x0*2)); ++#if defined(ENABLE_USB_NEW_MIU_SLE) ++ MIU_select_setting_ehc(USBC_base); ++#endif ++ writew(0x0C2F, (void*) (UTMI_base+0x8*2)); ++ if (flag & EHCFLAG_TESTPKG) ++ { ++ writew(0x2084, (void*)(UTMI_base+0x2*2)); ++ writew(0x8051, (void*)(UTMI_base+0x20*2)); ++ } ++ ++#if _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH ++ /* ++ * patch for DM always keep high issue ++ * init overwrite register ++ */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~BIT3), (void*) (UTMI_base+0x0*2)); //DP_PUEN = 0 ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~BIT4), (void*) (UTMI_base+0x0*2)); //DM_PUEN = 0 ++ ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~BIT5), (void*) (UTMI_base+0x0*2)); //R_PUMODE = 0 ++ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT6, (void*) (UTMI_base+0x0*2)); //R_DP_PDEN = 1 ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT7, (void*) (UTMI_base+0x0*2)); //R_DM_PDEN = 1 ++ ++ writeb(readb((void*)(UTMI_base+0x10*2)) | BIT6, (void*) (UTMI_base+0x10*2)); //hs_txser_en_cb = 1 ++ writeb(readb((void*)(UTMI_base+0x10*2)) & (u8)(~BIT7), (void*) (UTMI_base+0x10*2)); //hs_se0_cb = 0 ++ ++ /* turn on overwrite mode */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT1, (void*) (UTMI_base+0x0*2)); //tern_ov = 1 ++ /* new HW term overwrite: on */ ++ writeb(readb((void*)(UTMI_base+0x52*2)) | (BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0), (void*) (UTMI_base+0x52*2)); ++#endif ++ ++ /* Turn on overwirte mode for D+/D- floating issue when UHC reset ++ * Before UHC reset, R_DP_PDEN = 1, R_DM_PDEN = 1, tern_ov = 1 */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | (BIT7|BIT6|BIT1), (void*) (UTMI_base+0x0*2)); ++ /* new HW term overwrite: on */ ++ writeb(readb((void*)(UTMI_base+0x52*2)) | (BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0), (void*) (UTMI_base+0x52*2)); ++ ++#ifdef ENABLE_DOUBLE_DATARATE_SETTING ++ writeb(readb((void*)(UTMI_base+0x0D*2-1)) | BIT0, (void*) (UTMI_base+0x0D*2-1)); // set reg_double_data_rate, To get better jitter performance ++#endif ++#ifdef ENABLE_UPLL_SETTING ++ // sync code from eCos ++ { ++ u16 reg_t; ++ ++ reg_t = readw((void*)(UTMI_base+0x22*2)); ++ if ((reg_t & 0x10e0) != 0x10e0) ++ writew(0x10e0, (void*)(UTMI_base+0x22*2)); ++ reg_t = readw((void*)(UTMI_base+0x24*2)); ++ if (reg_t != 0x1) ++ writew(0x1, (void*)(UTMI_base+0x24*2)); ++ } ++ //writeb(0, (void*) (UTMI_base+0x21*2-1)); ++ //writeb(0x10, (void*) (UTMI_base+0x23*2-1)); ++ //writeb(0x01, (void*) (UTMI_base+0x24*2)); ++#endif ++ ++ writeb(0x0a, (void*)(USBC_base)); // Disable MAC initial suspend, Reset UHC ++ writeb(0x28, (void*)(USBC_base)); // Release UHC reset, enable UHC and OTG XIU function ++ ++ if (flag & EHCFLAG_DOUBLE_DATARATE) ++ { ++ if ((flag & EHCFLAG_DDR_MASK) == EHCFLAG_DDR_x15) ++ { ++ // Set usb bus = 480MHz x 1.5 ++ writeb(readb((void*)(UTMI_base+0x20*2)) | 0x76, (void*)(UTMI_base+0x20*2)); ++ } ++ else if ((flag & EHCFLAG_DDR_MASK) == EHCFLAG_DDR_x18) ++ { ++ // Set usb bus = 480MHz x 1.8 ++ writeb(readb((void*)(UTMI_base+0x20*2)) | 0x8e, (void*)(UTMI_base+0x20*2)); ++ } ++#if 0 ++ else if ((flag & EHCFLAG_DDR_MASK) == EHCFLAG_DDR_x20) ++ { ++ // Set usb bus = 480MHz x2 ++ writeb(readb((void*)(UTMI_base+0xd*2-1)) | 0x01, (void*)(UTMI_base+0xd*2-1)); ++ } ++#endif ++ /* Set slew rate control for overspeed (or 960MHz) */ ++ writeb(readb((void*)(UTMI_base+0x2c*2)) | BIT0, (void*) (UTMI_base+0x2c*2)); ++ } ++ ++ /* Init UTMI squelch level setting befor CA */ ++ if(UTMI_DISCON_LEVEL_2A & (BIT3|BIT2|BIT1|BIT0)) ++ { ++ writeb((UTMI_DISCON_LEVEL_2A & (BIT3|BIT2|BIT1|BIT0)), (void*)(UTMI_base+0x2a*2)); ++ printk("[USB] init squelch level 0x%x\n", readb((void*)(UTMI_base+0x2a*2))); ++ } ++ ++ writeb(readb((void*)(UTMI_base+0x3c*2)) | BIT0, (void*)(UTMI_base+0x3c*2)); // set CA_START as 1 ++ mdelay(1); ++ ++ writeb(readb((void*)(UTMI_base+0x3c*2)) & (u8)(~BIT0), (void*)(UTMI_base+0x3c*2)); // release CA_START ++ ++ while ((readb((void*)(UTMI_base+0x3c*2)) & BIT1) == 0); // polling bit <1> (CA_END) ++ ++ if ((0xFFF0 == (readw((void*)(UTMI_base+0x3C*2)) & 0xFFF0 )) || ++ (0x0000 == (readw((void*)(UTMI_base+0x3C*2)) & 0xFFF0 )) ) ++ printk("WARNING: CA Fail !! \n"); ++ ++ if (flag & EHCFLAG_DPDM_SWAP) ++ writeb(readb((void*)(UTMI_base+0x0b*2-1)) | BIT5, (void*)(UTMI_base+0x0b*2-1)); // dp dm swap ++#if defined(CONFIG_USB_MS_OTG) || defined(CONFIG_USB_MS_OTG_MODULE) ++ if(flag & EHCFLAG_ENABLE_OTG) ++ { ++ // let OTG driver to handle the UTMI switch control ++ } ++ else ++#endif ++ writeb((u8)((readb((void*)(USBC_base+0x02*2)) & ~BIT1) | BIT0), (void*)(USBC_base+0x02*2)); // UHC select enable ++ ++ writeb(readb((void*)(UHC_base+0x40*2)) & (u8)(~BIT4), (void*)(UHC_base+0x40*2)); // 0: VBUS On. ++ udelay(1); // delay 1us ++ ++ writeb(readb((void*)(UHC_base+0x40*2)) | BIT3, (void*)(UHC_base+0x40*2)); // Active HIGH ++ ++ /* Turn on overwirte mode for D+/D- floating issue when UHC reset ++ * After UHC reset, disable overwrite bits */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~(BIT7|BIT6|BIT1)), (void*) (UTMI_base+0x0*2)); ++ /* new HW term overwrite: off */ ++ writeb(readb((void*)(UTMI_base+0x52*2)) & (u8)(~(BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0)), (void*) (UTMI_base+0x52*2)); ++ ++ /* improve the efficiency of USB access MIU when system is busy */ ++ writeb(readb((void*)(UHC_base+0x81*2-1)) | (BIT0 | BIT1 | BIT2 | BIT3 | BIT7), (void*)(UHC_base+0x81*2-1)); ++ ++ writeb((u8)((readb((void*)(UTMI_base+0x06*2)) & ~BIT5) | BIT6), (void*)(UTMI_base+0x06*2)); // reg_tx_force_hs_current_enable ++ ++ writeb((u8)((readb((void*)(UTMI_base+0x03*2-1)) & ~BIT4) | (BIT3 | BIT5)), (void*)(UTMI_base+0x03*2-1)); // Disconnect window select ++ ++ writeb(readb((void*)(UTMI_base+0x07*2-1)) & (u8)(~BIT1), (void*)(UTMI_base+0x07*2-1)); // Disable improved CDR ++ ++#if defined(ENABLE_UTMI_240_AS_120_PHASE_ECO) ++ #if defined(UTMI_240_AS_120_PHASE_ECO_INV) ++ writeb(readb((void*)(UTMI_base+0x08*2)) & (u8)(~BIT3), (void*)(UTMI_base+0x08*2)); //Set sprcial value for Eiffel USB analog LIB issue ++ #else ++ /* bit<3> for 240's phase as 120's clock set 1, bit<4> for 240Mhz in mac 0 for faraday 1 for etron */ ++ writeb(readb((void*)(UTMI_base+0x08*2)) | BIT3, (void*)(UTMI_base+0x08*2)); ++ #endif ++#endif ++ ++ writeb(readb((void*)(UTMI_base+0x09*2-1)) | (BIT0 | BIT7), (void*)(UTMI_base+0x09*2-1)); // UTMI RX anti-dead-loc, ISI effect improvement ++ ++ if ((flag & EHCFLAG_DOUBLE_DATARATE)==0) ++ writeb(readb((void*)(UTMI_base+0x0b*2-1)) | BIT7, (void*)(UTMI_base+0x0b*2-1)); // TX timing select latch path ++ ++ writeb(readb((void*)(UTMI_base+0x15*2-1)) | BIT5, (void*)(UTMI_base+0x15*2-1)); // Chirp signal source select ++ ++#if defined(ENABLE_UTMI_55_INTERFACE) ++ writeb(readb((void*)(UTMI_base+0x15*2-1)) | BIT6, (void*)(UTMI_base+0x15*2-1)); // change to 55 interface ++#endif ++ ++ /* new HW chrip design, defualt overwrite to reg_2A */ ++ writeb(readb((void*)(UTMI_base+0x40*2)) & (u8)(~BIT4), (void*)(UTMI_base+0x40*2)); ++ ++ /* Init UTMI disconnect level setting */ ++ writeb(UTMI_DISCON_LEVEL_2A, (void*)(UTMI_base+0x2a*2)); ++ ++#if defined(ENABLE_NEW_HW_CHRIP_PATCH) ++ /* Init chrip detect level setting */ ++ writeb(UTMI_CHIRP_DCT_LEVEL_42, (void*)(UTMI_base+0x42*2)); ++ /* enable HW control chrip/disconnect level */ ++ writeb(readb((void*)(UTMI_base+0x40*2)) & (u8)(~BIT3), (void*)(UTMI_base+0x40*2)); ++#endif ++ ++ /* Init UTMI eye diagram parameter setting */ ++ writeb(readb((void*)(UTMI_base+0x2c*2)) | UTMI_EYE_SETTING_2C, (void*)(UTMI_base+0x2c*2)); ++ writeb(readb((void*)(UTMI_base+0x2d*2-1)) | UTMI_EYE_SETTING_2D, (void*)(UTMI_base+0x2d*2-1)); ++ writeb(readb((void*)(UTMI_base+0x2e*2)) | UTMI_EYE_SETTING_2E, (void*)(UTMI_base+0x2e*2)); ++ writeb(readb((void*)(UTMI_base+0x2f*2-1)) | UTMI_EYE_SETTING_2F, (void*)(UTMI_base+0x2f*2-1)); ++ ++#if defined(ENABLE_LS_CROSS_POINT_ECO) ++ /* Enable deglitch SE0 (low-speed cross point) */ ++ writeb(readb((void*)(UTMI_base+LS_CROSS_POINT_ECO_OFFSET)) | LS_CROSS_POINT_ECO_BITSET, (void*)(UTMI_base+LS_CROSS_POINT_ECO_OFFSET)); ++#endif ++ ++#if defined(ENABLE_PWR_NOISE_ECO) ++ /* Enable use eof2 to reset state machine (power noise) */ ++ writeb(readb((void*)(USBC_base+0x02*2)) | BIT6, (void*)(USBC_base+0x02*2)); ++#endif ++ ++#if defined(ENABLE_TX_RX_RESET_CLK_GATING_ECO) ++ /* Enable hw auto deassert sw reset(tx/rx reset) */ ++ writeb(readb((void*)(UTMI_base+TX_RX_RESET_CLK_GATING_ECO_OFFSET)) | TX_RX_RESET_CLK_GATING_ECO_BITSET, (void*)(UTMI_base+TX_RX_RESET_CLK_GATING_ECO_OFFSET)); ++#endif ++ ++#if defined(ENABLE_LOSS_SHORT_PACKET_INTR_ECO) ++ /* Enable patch for the assertion of interrupt(Lose short packet interrupt) */ ++ #if defined(LOSS_SHORT_PACKET_INTR_ECO_OPOR) ++ writeb(readb((void*)(USBC_base+LOSS_SHORT_PACKET_INTR_ECO_OFFSET)) | LOSS_SHORT_PACKET_INTR_ECO_BITSET, (void*)(USBC_base+LOSS_SHORT_PACKET_INTR_ECO_OFFSET)); ++ #else ++ writeb(readb((void*)(USBC_base+0x04*2)) & (u8)(~BIT7), (void*)(USBC_base+0x04*2)); ++ #endif ++#endif ++ ++#if defined(ENABLE_BABBLE_ECO) ++ /* Enable add patch to Period_EOF1(babble problem) */ ++ writeb(readb((void*)(USBC_base+0x04*2)) | BIT6, (void*)(USBC_base+0x04*2)); ++#endif ++ ++#if defined(ENABLE_MDATA_ECO) ++ /* Enable short packet MDATA in Split transaction clears ACT bit (LS dev under a HS hub) */ ++ writeb(readb((void*)(USBC_base+MDATA_ECO_OFFSET)) | MDATA_ECO_BITSET, (void*) (USBC_base+MDATA_ECO_OFFSET)); ++#endif ++ ++#if defined(ENABLE_HS_DM_KEEP_HIGH_ECO) ++ /* Change override to hs_txser_en. Dm always keep high issue */ ++ writeb(readb((void*)(UTMI_base+0x10*2)) | BIT6, (void*) (UTMI_base+0x10*2)); ++#endif ++ ++#if defined(ENABLE_HS_CONNECTION_FAIL_INTO_VFALL_ECO) ++ /* HS connection fail problem (Gate into VFALL state) */ ++ writeb(readb((void*)(USBC_base+0x11*2-1)) | BIT1, (void*)(USBC_base+0x11*2-1)); ++#endif ++ ++#if _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH ++ /* ++ * patch for DM always keep high issue ++ * init overwrite register ++ */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT6, (void*) (UTMI_base+0x0*2)); //R_DP_PDEN = 1 ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT7, (void*) (UTMI_base+0x0*2)); //R_DM_PDEN = 1 ++ ++ /* turn on overwrite mode */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT1, (void*) (UTMI_base+0x0*2)); //tern_ov = 1 ++ /* new HW term overwrite: on */ ++ writeb(readb((void*)(UTMI_base+0x52*2)) | (BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0), (void*) (UTMI_base+0x52*2)); ++#endif ++ ++#if defined (ENABLE_PV2MI_BRIDGE_ECO) ++ writeb(readb((void*)(USBC_base+0x0a*2)) | BIT6, (void*)(USBC_base+0x0a*2)); ++#endif ++ ++#if _USB_ANALOG_RX_SQUELCH_PATCH ++ /* squelch level adjust by calibration value */ ++ { ++ unsigned int ca_da_ov, ca_db_ov, ca_tmp; ++ ++ ca_tmp = readw((void*)(UTMI_base+0x3c*2)); ++ ca_da_ov = (((ca_tmp >> 4) & 0x3f) - 5) + 0x40; ++ ca_db_ov = (((ca_tmp >> 10) & 0x3f) - 5) + 0x40; ++ printk("[%x]-5 -> (ca_da_ov, ca_db_ov)=(%x,%x)\n", ca_tmp, ca_da_ov, ca_db_ov); ++ writeb(ca_da_ov ,(void*)(UTMI_base+0x3B*2-1)); ++ writeb(ca_db_ov ,(void*)(UTMI_base+0x24*2)); ++ } ++#endif ++ ++#if _USB_MINI_PV2MI_BURST_SIZE ++ writeb(readb((void*)(USBC_base+0x0b*2-1)) & ~(BIT1|BIT2|BIT3|BIT4), (void*)(USBC_base+0x0b*2-1)); ++#endif ++ ++#if defined(ENABLE_UHC_PREAMBLE_ECO) ++ /* [7]: reg_etron_en, to enable utmi Preamble function */ ++ writeb(readb((void*)(UTMI_base+0x3f*2-1)) | BIT7, (void*) (UTMI_base+0x3f*2-1)); ++ ++ /* [3:]: reg_preamble_en, to enable Faraday Preamble */ ++ writeb(readb((void*)(USBC_base+0x0f*2-1)) | BIT3, (void*)(USBC_base+0x0f*2-1)); ++ ++ /* [0]: reg_preamble_babble_fix, to patch Babble occurs in Preamble */ ++ writeb(readb((void*)(USBC_base+0x10*2)) | BIT0, (void*)(USBC_base+0x10*2)); ++ ++ /* [1]: reg_preamble_fs_within_pre_en, to patch FS crash problem */ ++ writeb(readb((void*)(USBC_base+0x10*2)) | BIT1, (void*)(USBC_base+0x10*2)); ++ ++ /* [2]: reg_fl_sel_override, to override utmi to have FS drive strength */ ++ writeb(readb((void*)(UTMI_base+0x03*2-1)) | BIT2, (void*) (UTMI_base+0x03*2-1)); ++#endif ++ ++#if defined(ENABLE_UHC_RUN_BIT_ALWAYS_ON_ECO) ++ /* Don't close RUN bit when device disconnect */ ++ writeb(readb((void*)(UHC_base+0x34*2)) | BIT7, (void*)(UHC_base+0x34*2)); ++#endif ++ ++#if _USB_MIU_WRITE_WAIT_LAST_DONE_Z_PATCH ++ /* Enabe PVCI i_miwcplt wait for mi2uh_last_done_z */ ++ writeb(readb((void*)(UHC_base+0x83*2-1)) | BIT4, (void*)(UHC_base+0x83*2-1)); ++#endif ++ ++#if defined(ENABLE_UHC_EXTRA_HS_SOF_ECO) ++ /* Extra HS SOF after bus reset */ ++ writeb(readb((void*)(UHC_base+0x8C*2)) | BIT0, (void*)(UHC_base+0x8C*2)); ++#endif ++ ++ /* Enable HS ISO IN Camera Cornor case ECO function */ ++#if defined(HS_ISO_IN_ECO_OFFSET) ++ writeb(readb((void*)(USBC_base+HS_ISO_IN_ECO_OFFSET)) | HS_ISO_IN_ECO_BITSET, (void*) (USBC_base+HS_ISO_IN_ECO_OFFSET)); ++#else ++ writeb(readb((void*)(USBC_base+0x13*2-1)) | BIT0, (void*)(USBC_base+0x13*2-1)); ++#endif ++ ++#if defined(ENABLE_DISCONNECT_SPEED_REPORT_RESET_ECO) ++ /* UHC speed type report should be reset by device disconnection */ ++ writeb(readb((void*)(USBC_base+0x20*2)) | BIT0, (void*)(USBC_base+0x20*2)); ++#endif ++ ++#if defined(ENABLE_BABBLE_PCD_ONE_PULSE_TRIGGER_ECO) ++ /* Port Change Detect (PCD) is triggered by babble. ++ * Pulse trigger will not hang this condition. ++ */ ++ writeb(readb((void*)(USBC_base+0x20*2)) | BIT1, (void*)(USBC_base+0x20*2)); ++#endif ++ ++#if defined(ENABLE_HC_RESET_FAIL_ECO) ++ /* generation of hhc_reset_u */ ++ writeb(readb((void*)(USBC_base+0x20*2)) | BIT2, (void*)(USBC_base+0x20*2)); ++#endif ++ ++#if defined(ENABLE_INT_AFTER_WRITE_DMA_ECO) ++ /* DMA interrupt after the write back of qTD */ ++ writeb(readb((void*)(USBC_base+0x20*2)) | BIT3, (void*)(USBC_base+0x20*2)); ++#endif ++ ++#if defined(ENABLE_DISCONNECT_HC_KEEP_RUNNING_ECO) ++ /* EHCI keeps running when device is disconnected */ ++ writeb(readb((void*)(USBC_base+0x19*2-1)) | BIT3, (void*)(USBC_base+0x19*2-1)); ++#endif ++ ++#if !defined(_EHC_SINGLE_SOF_TO_CHK_DISCONN) ++ writeb(0x05, (void*)(USBC_base+0x03*2-1)); //Use 2 SOFs to check disconnection ++#endif ++ ++#if defined(ENABLE_SRAM_CLK_GATING_ECO) ++ /* do SRAM clock gating automatically to save power */ ++ writeb(readb((void*)(USBC_base+0x20*2)) & (u8)(~BIT4), (void*)(USBC_base+0x20*2)); ++#endif ++ ++#if defined (ENABLE_INTR_SITD_CS_IN_ZERO_ECO) ++ /* Enable interrupt in sitd cs in zero packet */ ++ writeb(readb((void*)(USBC_base+0x11*2-1)) | BIT7, (void*)(USBC_base+0x11*2-1)); ++#endif ++ ++ if (flag & EHCFLAG_TESTPKG) ++ { ++ writew(0x0600, (void*) (UTMI_base+0x14*2)); ++ writew(0x0078, (void*) (UTMI_base+0x10*2)); ++ writew(0x0bfe, (void*) (UTMI_base+0x32*2)); ++ } ++} ++ ++/* configure so an HC device and id are always provided */ ++/* always called with process context; sleeping is OK */ ++ ++#if defined(CONFIG_OF) ++extern unsigned int irq_of_parse_and_map(struct device_node *node, int index); ++#endif ++ ++#if MP_USB_MSTAR && _USB_VBUS_RESET_PATCH ++ int vbus_gpio_of_parse_and_map(struct device_node *node) ++{ ++ return Get_USB_VBUS_Pin(node); ++} ++ EXPORT_SYMBOL_GPL(vbus_gpio_of_parse_and_map); ++#endif ++ ++/** ++ * usb_ehci_au1xxx_probe - initialize Au1xxx-based HCDs ++ * Context: !in_interrupt() ++ * ++ * Allocates basic resources for this USB host controller, and ++ * then invokes the start() method for the HCD associated with it ++ * through the hotplug entry's driver_data. ++ * ++ */ ++ ++int ehci_hcd_mstar_drv_probe(struct platform_device *dev) ++{ ++ int retval=0; ++ int irq = -1; ++ struct usb_hcd *hcd; ++ struct ehci_hcd *ehci; ++ unsigned int flag = 0; ++ u64 dma_mask; ++ int param = 0; ++#if defined(CONFIG_OF) ++ u32 val; ++ int ret; ++ struct device_node *node = dev->dev.of_node; ++#endif ++#ifdef ENABLE_SECOND_XHC ++ #ifdef _MSTAR_EHC0_COMP_PORT ++ struct comp_port ehc0_comp = {_MSTAR_EHC0_COMP_PORT, _MSTAR_EHC0_COMP_U3TOP_BASE, _MSTAR_EHC0_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC1_COMP_PORT ++ struct comp_port ehc1_comp = {_MSTAR_EHC1_COMP_PORT, _MSTAR_EHC1_COMP_U3TOP_BASE, _MSTAR_EHC1_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC2_COMP_PORT ++ struct comp_port ehc2_comp = {_MSTAR_EHC2_COMP_PORT, _MSTAR_EHC2_COMP_U3TOP_BASE, _MSTAR_EHC2_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC3_COMP_PORT ++ struct comp_port ehc3_comp = {_MSTAR_EHC3_COMP_PORT, _MSTAR_EHC3_COMP_U3TOP_BASE, _MSTAR_EHC3_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC4_COMP_PORT ++ struct comp_port ehc4_comp = {_MSTAR_EHC4_COMP_PORT, _MSTAR_EHC4_COMP_U3TOP_BASE, _MSTAR_EHC4_COMP_PORT_INDEX}; ++ #endif ++#else /* one root case */ ++ #ifdef _MSTAR_EHC0_COMP_PORT ++ struct comp_port ehc0_comp = {_MSTAR_EHC0_COMP_PORT, _MSTAR_U3TOP_BASE, _MSTAR_EHC0_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC1_COMP_PORT ++ struct comp_port ehc1_comp = {_MSTAR_EHC1_COMP_PORT, _MSTAR_U3TOP_BASE, _MSTAR_EHC1_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC2_COMP_PORT ++ struct comp_port ehc2_comp = {_MSTAR_EHC2_COMP_PORT, _MSTAR_U3TOP_BASE, _MSTAR_EHC2_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC3_COMP_PORT ++ struct comp_port ehc3_comp = {_MSTAR_EHC3_COMP_PORT, _MSTAR_U3TOP_BASE, _MSTAR_EHC3_COMP_PORT_INDEX}; ++ #endif ++ #ifdef _MSTAR_EHC4_COMP_PORT ++ struct comp_port ehc4_comp = {_MSTAR_EHC4_COMP_PORT, _MSTAR_U3TOP_BASE, _MSTAR_EHC4_COMP_PORT_INDEX}; ++ #endif ++#endif ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++#ifdef ENABLE_CHIPTOP_PERFORMANCE_SETTING ++ int chipVER = readw((void *)(MSTAR_CHIP_TOP_BASE+0xCE*2)); ++ /* chip top performance tuning [11:9] = 0xe00 */ ++ if (chipVER == 0x101) // U02 ++ writew(readw((void*)(MSTAR_CHIP_TOP_BASE+0x46*2)) | 0xe00, ++ (void*) (MSTAR_CHIP_TOP_BASE+0x46*2)); ++#endif ++ #define NAME_LEN (16) ++ if( 0==strncmp(dev->name, "soc:Sstar-ehci-1", NAME_LEN) ) ++ { ++ printk("Sstar-ehci-1 H.W init\n"); ++ #if _USB_UTMI_DPDM_SWAP_P0 ++ flag |= EHCFLAG_DPDM_SWAP; ++ #endif ++ #ifdef _USB_ENABLE_OTG_P0 ++ flag |= EHCFLAG_ENABLE_OTG; ++ #endif ++ #if defined(CONFIG_OF) ++ ret = of_property_read_u32(node, "dpdm_swap", &val); ++ if(ret == 0) ++ flag |= val;//EHCFLAG_DPDM_SWAP ++ #endif ++ param = 1&0xFF; // param = (port_num << 16) | (vbus_en & 0xFF) ++ Enable_USB_VBUS(param); ++ Titania3_series_start_ehc(_MSTAR_UTMI0_BASE, _MSTAR_USBC0_BASE, _MSTAR_UHC0_BASE, flag); ++ } ++#if !defined(DISABLE_SECOND_EHC) ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-2", NAME_LEN) ) ++ { ++ printk("Sstar-ehci-2 H.W init\n"); ++ #if _USB_UTMI_DPDM_SWAP_P1 ++ flag |= EHCFLAG_DPDM_SWAP; ++ #endif ++ #ifdef _USB_ENABLE_OTG_P1 ++ flag |= EHCFLAG_ENABLE_OTG; ++ #endif ++ #if defined(CONFIG_OF) ++ ret = of_property_read_u32(node, "dpdm_swap", &val); ++ if(ret == 0) ++ flag |= val;//EHCFLAG_DPDM_SWAP ++ #endif ++ param = ((1<<16) | (1&0xFF)); // param = (port_num << 16) | (vbus_en & 0xFF) ++ Enable_USB_VBUS(param); ++ Titania3_series_start_ehc(_MSTAR_UTMI1_BASE, _MSTAR_USBC1_BASE, _MSTAR_UHC1_BASE, flag); ++ } ++#endif ++#ifdef ENABLE_THIRD_EHC ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-3", NAME_LEN) ) ++ { ++ printk("Sstar-ehci-3 H.W init\n"); ++#if _USB_UTMI_DPDM_SWAP_P2 ++ flag |= EHCFLAG_DPDM_SWAP; ++#endif ++ #ifdef _USB_ENABLE_OTG_P2 ++ flag |= EHCFLAG_ENABLE_OTG; ++ #endif ++#if defined(CONFIG_OF) ++ ret = of_property_read_u32(node, "dpdm_swap", &val); ++ if(ret == 0) ++ flag |= val;//EHCFLAG_DPDM_SWAP ++#endif ++ param = ((2<<16) | (1&0xFF)); // param = (port_num << 16) | (vbus_en & 0xFF) ++ Enable_USB_VBUS(param); ++ Titania3_series_start_ehc(_MSTAR_UTMI2_BASE, _MSTAR_USBC2_BASE, _MSTAR_UHC2_BASE, flag ); ++ } ++#endif ++#ifdef ENABLE_FOURTH_EHC ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-4", NAME_LEN) ) ++ { ++ printk("Sstar-ehci-4 H.W init\n"); ++ #ifdef _USB_ENABLE_OTG_P3 ++ flag |= EHCFLAG_ENABLE_OTG; ++ #endif ++ param = ((3<<16) | (1&0xFF)); // param = (port_num << 16) | (vbus_en & 0xFF) ++ Enable_USB_VBUS(param); ++ Titania3_series_start_ehc(_MSTAR_UTMI3_BASE, _MSTAR_USBC3_BASE, _MSTAR_UHC3_BASE, flag ); ++ } ++#endif ++#ifdef ENABLE_FIFTH_EHC ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-5", NAME_LEN) ) ++ { ++ printk("Sstar-ehci-5 H.W init\n"); ++ #ifdef _USB_ENABLE_OTG_P4 ++ flag |= EHCFLAG_ENABLE_OTG; ++ #endif ++ Titania3_series_start_ehc(_MSTAR_UTMI4_BASE, _MSTAR_USBC4_BASE, _MSTAR_UHC4_BASE, flag ); ++ } ++#endif ++ ++#if defined(CONFIG_OF) ++ if (!dev->dev.platform_data) ++ { ++ printk(KERN_WARNING "[USB] no platform_data, device tree coming\n"); ++ } ++ ++ if (!dev->dev.dma_mask) ++ dev->dev.dma_mask = &dev->dev.coherent_dma_mask; ++ ++ if(IS_ENABLED(CONFIG_ARM64) && IS_ENABLED(CONFIG_ZONE_DMA)) ++ { ++#if defined(EHC_DMA_BIT_MASK) ++ dma_mask = EHC_DMA_BIT_MASK; ++#else ++ /* default: 32bit to mask lowest 4G address */ ++ dma_mask = DMA_BIT_MASK(32); ++#endif ++ } else ++ dma_mask = DMA_BIT_MASK(64); ++ ++ if(dma_set_mask(&dev->dev, dma_mask) || ++ dma_set_coherent_mask(&dev->dev, dma_mask)) ++ { ++ printk(KERN_ERR "[USB][EHC] cannot accept dma mask 0x%llx\n", dma_mask); ++ return -EOPNOTSUPP; ++ } ++ ++ printk(KERN_NOTICE "[USB][EHC] dma coherent_mask 0x%llx mask 0x%llx\n", ++ dev->dev.coherent_dma_mask, *dev->dev.dma_mask); ++ ++ /* try to get irq from device tree */ ++ irq = irq_of_parse_and_map(dev->dev.of_node, 0); ++#else ++ if (dev->resource[2].flags != IORESOURCE_IRQ) { ++ printk(KERN_WARNING "resource[2] is not IORESOURCE_IRQ"); ++ } ++ else ++ { ++ irq = dev->resource[2].start; ++ } ++#endif ++ ++#if !defined(ENABLE_IRQ_REMAP) ++ if(irq <= 0) ++ { ++ printk(KERN_ERR "[USB] can not get irq for %s\n", dev->name); ++ return -ENODEV; ++ } ++#endif ++ ++ hcd = usb_create_hcd(&ehci_mstar_hc_driver, &dev->dev, "mstar"); ++ if (!hcd) ++ return -ENOMEM; ++ ++ /* ehci_hcd_init(hcd_to_ehci(hcd)); */ ++ if( 0==strncmp(dev->name, "soc:Sstar-ehci-1", NAME_LEN) ) ++ { ++ hcd->port_index = 1; ++ hcd->utmi_base = _MSTAR_UTMI0_BASE; ++ hcd->ehc_base = _MSTAR_UHC0_BASE; ++ hcd->usbc_base = _MSTAR_USBC0_BASE; ++ hcd->bc_base = _MSTAR_BC0_BASE; ++ #ifdef _MSTAR_EHC0_COMP_PORT ++ hcd->companion = ehc0_comp; ++ #endif ++ #ifdef ENABLE_IRQ_REMAP ++ irq = MSTAR_EHC1_IRQ; ++ #endif ++ } ++#if !defined(DISABLE_SECOND_EHC) ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-2", NAME_LEN) ) ++ { ++ hcd->port_index = 2; ++ hcd->utmi_base = _MSTAR_UTMI1_BASE; ++ hcd->ehc_base = _MSTAR_UHC1_BASE; ++ hcd->usbc_base = _MSTAR_USBC1_BASE; ++ hcd->bc_base = _MSTAR_BC1_BASE; ++ #ifdef _MSTAR_EHC1_COMP_PORT ++ hcd->companion = ehc1_comp; ++ #endif ++ #ifdef ENABLE_IRQ_REMAP ++ irq = MSTAR_EHC2_IRQ; ++ #endif ++ } ++#endif ++#ifdef ENABLE_THIRD_EHC ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-3", NAME_LEN) ) ++ { ++ hcd->port_index = 3; ++ hcd->utmi_base = _MSTAR_UTMI2_BASE; ++ hcd->ehc_base = _MSTAR_UHC2_BASE; ++ hcd->usbc_base = _MSTAR_USBC2_BASE; ++ hcd->bc_base = _MSTAR_BC2_BASE; ++ #ifdef _MSTAR_EHC2_COMP_PORT ++ hcd->companion = ehc2_comp; ++ #endif ++ #ifdef ENABLE_IRQ_REMAP ++ irq = MSTAR_EHC3_IRQ; ++ #endif ++ } ++#endif ++#ifdef ENABLE_FOURTH_EHC ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-4", NAME_LEN) ) ++ { ++ hcd->port_index = 4; ++ hcd->utmi_base = _MSTAR_UTMI3_BASE; ++ hcd->ehc_base = _MSTAR_UHC3_BASE; ++ hcd->usbc_base = _MSTAR_USBC3_BASE; ++ hcd->bc_base = _MSTAR_BC3_BASE; ++ #ifdef _MSTAR_EHC3_COMP_PORT ++ hcd->companion = ehc3_comp; ++ #endif ++ #ifdef ENABLE_IRQ_REMAP ++ irq = MSTAR_EHC4_IRQ; ++ #endif ++ } ++#endif ++#ifdef ENABLE_FIFTH_EHC ++ else if( 0==strncmp(dev->name, "soc:Sstar-ehci-5", NAME_LEN) ) ++ { ++ hcd->port_index = 5; ++ hcd->utmi_base = _MSTAR_UTMI4_BASE; ++ hcd->ehc_base = _MSTAR_UHC4_BASE; ++ hcd->usbc_base = _MSTAR_USBC4_BASE; ++ hcd->bc_base = _MSTAR_BC4_BASE; ++ #ifdef _MSTAR_EHC4_COMP_PORT ++ hcd->companion = ehc4_comp; ++ #endif ++ #ifdef ENABLE_IRQ_REMAP ++ irq = MSTAR_EHC5_IRQ; ++ #endif ++ } ++#endif ++ ++ hcd->rsrc_start = hcd->ehc_base; ++ hcd->rsrc_len = (0xfe<<1); ++ hcd->has_tt = 1; ++#if _USB_XIU_TIMEOUT_PATCH ++ hcd->usb_reset_lock = __SPIN_LOCK_UNLOCKED(hcd->usb_reset_lock); ++#endif ++ ++ hcd->regs = (void *)hcd->rsrc_start; // tony ++ if (!hcd->regs) { ++ pr_debug("ioremap failed"); ++ retval = -ENOMEM; ++ goto err1; ++ } ++ ++ ehci = hcd_to_ehci(hcd); ++ ehci->caps = hcd->regs; ++ ehci->regs = (struct ehci_regs *)((uintptr_t)hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase))); ++ ++ //printk("\nDean: [%s] ehci->regs: 0x%x\n", __FILE__, (unsigned int)ehci->regs); ++ /* cache this readonly data; minimize chip reads */ ++ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ ++ //Disable default setting ++ usb_bc_enable(hcd, false); ++ ++#if _UTMI_PWR_SAV_MODE_ENABLE ++ usb_power_saving_enable(hcd, true); ++#endif ++ ++#ifdef USB_MAC_SRAM_POWER_DOWN_ENABLE ++ usb20mac_sram_power_saving(hcd, true); ++#endif ++ ++ printk(KERN_INFO "[USB] %s irq --> %d\n", dev->name, irq); ++ ++ /* IRQF_DISABLED was removed from kernel 4.1 ++ commit d8bf368d0631d4bc2612d8bf2e4e8e74e620d0cc. */ ++ retval = usb_add_hcd(hcd, irq, 0); ++ ++ hcd->root_port_devnum=0; ++ hcd->enum_port_flag=0; ++ hcd->enum_dbreset_flag=0; ++ hcd->lock_usbreset=__SPIN_LOCK_UNLOCKED(hcd->lock_usbreset); ++ ++ //usb_add_hcd(hcd, dev->resource[2].start, IRQF_DISABLED | IRQF_SHARED); ++ if (retval == 0) ++ return retval; ++err1: ++ usb_put_hcd(hcd); ++ return retval; ++} ++ ++/* may be called without controller electrically present */ ++/* may be called with controller, bus, and devices active */ ++ ++/** ++ * usb_ehci_hcd_au1xxx_remove - shutdown processing for Au1xxx-based HCDs ++ * @dev: USB Host Controller being removed ++ * Context: !in_interrupt() ++ * ++ * Reverses the effect of usb_ehci_hcd_au1xxx_probe(), first invoking ++ * the HCD's stop() method. It is always called from a thread ++ * context, normally "rmmod", "apmd", or something similar. ++ * ++ */ ++static int ehci_hcd_mstar_drv_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ ++ usb_remove_hcd(hcd); ++ usb_put_hcd(hcd); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int ehci_hcd_mstar_drv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(pdev); ++ ++ printk("ehci_hcd_mstar_platform_suspend...port %d\n", hcd->port_index); ++ return ehci_suspend(hcd, false); ++} ++ ++static int ehci_hcd_mstar_drv_resume(struct platform_device *pdev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(pdev); ++ unsigned int flag = 0; ++ ++#if (_USB_UTMI_DPDM_SWAP_P0) || (_USB_UTMI_DPDM_SWAP_P1) ++ flag |= (hcd->port_index == 1 || hcd->port_index == 2) ? EHCFLAG_DPDM_SWAP : 0; ++#endif ++ ++ printk("ehci_hcd_mstar_platform_resume...port %d\n", hcd->port_index); ++ ++ Titania3_series_start_ehc(hcd->utmi_base, hcd->usbc_base, hcd->ehc_base, flag); ++ ++ //Disable default setting ++ usb_bc_enable(hcd, false); ++ ++ ehci_resume(hcd, false); ++ return 0; ++} ++#endif ++ ++/*-------------------------------------------------------------------------*/ ++ ++#if defined(CONFIG_OF) ++static struct of_device_id mstar_ehci_1_of_device_ids[] = { ++ {.compatible = "Sstar-ehci-1"}, ++ {}, ++}; ++ ++#if !defined(DISABLE_SECOND_EHC) ++static struct of_device_id mstar_ehci_2_of_device_ids[] = { ++ {.compatible = "Sstar-ehci-2"}, ++ {}, ++}; ++#endif ++ ++#ifdef ENABLE_THIRD_EHC ++static struct of_device_id mstar_ehci_3_of_device_ids[] = { ++ {.compatible = "Sstar-ehci-3"}, ++ {}, ++}; ++#endif ++ ++#ifdef ENABLE_FOURTH_EHC ++static struct of_device_id mstar_ehci_4_of_device_ids[] = { ++ {.compatible = "Sstar-ehci-4"}, ++ {}, ++}; ++#endif ++ ++#ifdef ENABLE_FIFTH_EHC ++static struct of_device_id mstar_ehci_5_of_device_ids[] = { ++ {.compatible = "Sstar-ehci-5"}, ++ {}, ++}; ++#endif ++#endif ++ ++static struct platform_driver ehci_hcd_mstar_driver = { ++ .probe = ehci_hcd_mstar_drv_probe, ++ .remove = ehci_hcd_mstar_drv_remove, ++#ifdef CONFIG_PM ++ .suspend = ehci_hcd_mstar_drv_suspend, ++ .resume = ehci_hcd_mstar_drv_resume, ++#endif ++ .driver = { ++ .name = "Sstar-ehci-1", ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_ehci_1_of_device_ids, ++#endif ++// .bus = &platform_bus_type, ++ } ++}; ++#if !defined(DISABLE_SECOND_EHC) ++static struct platform_driver second_ehci_hcd_mstar_driver = { ++ .probe = ehci_hcd_mstar_drv_probe, ++ .remove = ehci_hcd_mstar_drv_remove, ++#ifdef CONFIG_PM ++ .suspend = ehci_hcd_mstar_drv_suspend, ++ .resume = ehci_hcd_mstar_drv_resume, ++#endif ++ .driver = { ++ .name = "Sstar-ehci-2", ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_ehci_2_of_device_ids, ++#endif ++// .bus = &platform_bus_type, ++ } ++}; ++#endif ++#ifdef ENABLE_THIRD_EHC ++static struct platform_driver third_ehci_hcd_mstar_driver = { ++ .probe = ehci_hcd_mstar_drv_probe, ++ .remove = ehci_hcd_mstar_drv_remove, ++#ifdef CONFIG_PM ++ .suspend = ehci_hcd_mstar_drv_suspend, ++ .resume = ehci_hcd_mstar_drv_resume, ++#endif ++ .driver = { ++ .name = "Sstar-ehci-3", ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_ehci_3_of_device_ids, ++#endif ++// .bus = &platform_bus_type, ++ } ++}; ++#endif ++#ifdef ENABLE_FOURTH_EHC ++static struct platform_driver fourth_ehci_hcd_mstar_driver = { ++ .probe = ehci_hcd_mstar_drv_probe, ++ .remove = ehci_hcd_mstar_drv_remove, ++#ifdef CONFIG_PM ++ .suspend = ehci_hcd_mstar_drv_suspend, ++ .resume = ehci_hcd_mstar_drv_resume, ++#endif ++ .driver = { ++ .name = "Sstar-ehci-4", ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_ehci_4_of_device_ids, ++#endif ++// .bus = &platform_bus_type, ++ } ++}; ++#endif ++#ifdef ENABLE_FIFTH_EHC ++static struct platform_driver fifth_ehci_hcd_mstar_driver = { ++ .probe = ehci_hcd_mstar_drv_probe, ++ .remove = ehci_hcd_mstar_drv_remove, ++#ifdef CONFIG_PM ++ .suspend = ehci_hcd_mstar_drv_suspend, ++ .resume = ehci_hcd_mstar_drv_resume, ++#endif ++ .driver = { ++ .name = "Sstar-ehci-5", ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_ehci_5_of_device_ids, ++#endif ++// .bus = &platform_bus_type, ++ } ++}; ++#endif +diff --git a/drivers/sstar/usb/host/ehci-mstar.h b/drivers/sstar/usb/host/ehci-mstar.h +new file mode 100755 +index 000000000000..2417086ca443 +--- /dev/null ++++ b/drivers/sstar/usb/host/ehci-mstar.h +@@ -0,0 +1,363 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++ ++#ifndef _EHCI_MSTAR_H ++#define _EHCI_MSTAR_H ++ ++#include ++ ++#define EHCI_MSTAR_VERSION "20180309" ++ ++//#include ++//------ General constant definition --------------------------------- ++#if !defined(ENABLE) && !defined(DISABLE) ++#define DISABLE 0 ++#define ENABLE 1 ++#endif ++ ++#if !defined(BIT0) && !defined(BIT1) ++#define BIT0 0x01 ++#define BIT1 0x02 ++#define BIT2 0x04 ++#define BIT3 0x08 ++#define BIT4 0x10 ++#define BIT5 0x20 ++#define BIT6 0x40 ++#define BIT7 0x80 ++#endif ++ ++//------ RIU base addr and bus-addr to phy-addr translation ---------- ++#if defined(CONFIG_ARM) ++ //#include ++ #define _MSTAR_USB_BASEADR 0xfd200000 ++ ++ ++ #define MIU0_BUS_BASE_ADDR MSTAR_MIU0_BUS_BASE ++ #define MIU1_BUS_BASE_ADDR MSTAR_MIU1_BUS_BASE ++ ++ #define MIU0_PHY_BASE_ADDR ((unsigned long)0x00000000) ++ /* MIU0 256M*/ ++ #define MIU0_SIZE ((unsigned long)0x80000000) //TBD ++ ++ #define MIU1_PHY_BASE_ADDR ((unsigned long)0x80000000) //TBD ++ /* MIU1 512M*/ ++ #define MIU1_SIZE ((unsigned long)0x20000000) //TBD ++ #define BUS_PA_PATCH 1 ++ ++ #define ENABLE_USB_NEW_MIU_SLE 1 ++ #define USB_MIU_SEL0 ((u8) 0x70U) //TBD ++ #define USB_MIU_SEL1 ((u8) 0xe8U) //TBD ++ #define USB_MIU_SEL2 ((u8) 0xefU) ++ #define USB_MIU_SEL3 ((u8) 0xefU) ++ ++ #define BUS2PA(A) \ ++ (((A>=MIU0_BUS_BASE_ADDR)&&(A<(MIU0_BUS_BASE_ADDR+MIU0_SIZE)))? \ ++ (A-MIU0_BUS_BASE_ADDR+MIU0_PHY_BASE_ADDR): \ ++ (((A>= MIU1_BUS_BASE_ADDR)&&(A=MIU0_PHY_BASE_ADDR)&&(A<(MIU0_PHY_BASE_ADDR+MIU0_SIZE)))? \ ++ (A-MIU0_PHY_BASE_ADDR+MIU0_BUS_BASE_ADDR): \ ++ (((A>= MIU1_PHY_BASE_ADDR)&&(A for 240's phase as 120's clock set 1, bit<4> for 240Mhz in mac 0 for faraday 1 for etron */ ++#define ENABLE_UTMI_240_AS_120_PHASE_ECO ++ ++//---- 11. double date rate (480MHz) ++//#define ENABLE_DOUBLE_DATARATE_SETTING ++ ++//---- 12. UPLL setting, normally it should be done in sboot ++//#define ENABLE_UPLL_SETTING ++ ++//---- 13. chip top performance tuning ++//#define ENABLE_CHIPTOP_PERFORMANCE_SETTING ++ ++//---- 14. HS connection fail problem (Gate into VFALL state) ++#define ENABLE_HS_CONNECTION_FAIL_INTO_VFALL_ECO ++ ++//---- 15. Enable UHC Preamble ECO function ++#define ENABLE_UHC_PREAMBLE_ECO ++ ++//---- 16. Don't close RUN bit when device disconnect ++#define ENABLE_UHC_RUN_BIT_ALWAYS_ON_ECO ++ ++//---- 18. Extra HS SOF after bus reset ++#define ENABLE_UHC_EXTRA_HS_SOF_ECO ++ ++//---- 19. Not yet support MIU lower bound address subtraction ECO (for chips which use ENABLE_USB_NEW_MIU_SLE) ++//#define DISABLE_MIU_LOW_BOUND_ADDR_SUBTRACT_ECO ++ ++//---- 20. UHC speed type report should be reset by device disconnection ++#define ENABLE_DISCONNECT_SPEED_REPORT_RESET_ECO ++ ++//---- 21. Port Change Detect (PCD) is triggered by babble. Pulse trigger will not hang this condition. ++/* 1'b0: level trigger ++* 1'b1: one-pulse trigger ++*/ ++#define ENABLE_BABBLE_PCD_ONE_PULSE_TRIGGER_ECO ++ ++//---- 22. generation of hhc_reset_u ++/* 1'b0: hhc_reset is_u double sync of hhc_reset ++* 1'b1: hhc_reset_u is one-pulse of hhc_reset ++*/ ++#define ENABLE_HC_RESET_FAIL_ECO ++ ++//---- 23. EHCI keeps running when device is disconnected ++//#define ENABLE_DISCONNECT_HC_KEEP_RUNNING_ECO ++ ++//---- 24. Chirp patch use software overwrite value ++/* reg_sw_chirp_override_bit set to 0 */ ++#define DISABLE_NEW_HW_CHRIP_ECO ++ ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Software patch enable switch -------------------------------- ++//---- 1. flush MIU pipe ++#if 0 // every chip must apply it ++ #define _USB_T3_WBTIMEOUT_PATCH 0 ++#else ++ #define _USB_T3_WBTIMEOUT_PATCH 1 ++#endif ++ ++//---- 2. data structure (qtd ,...) must be 128-byte aligment ++#if 0 // every chip must apply it ++ #define _USB_128_ALIGMENT 0 ++#else ++ #define _USB_128_ALIGMENT 1 ++#endif ++ ++//---- 3. tx/rx reset clock gating cause XIU timeout ++#if 0 ++ #define _USB_XIU_TIMEOUT_PATCH 1 ++#else ++ #define _USB_XIU_TIMEOUT_PATCH 0 ++#endif ++ ++//---- 4. short packet lose interrupt without IOC ++#if 0 ++ #define _USB_SHORT_PACKET_LOSE_INT_PATCH 1 ++#else ++ #define _USB_SHORT_PACKET_LOSE_INT_PATCH 0 ++#endif ++ ++//---- 5. QH blocking in MDATA condition, split zero-size data ++#if 0 // every chip must apply it ++ #define _USB_SPLIT_MDATA_BLOCKING_PATCH 0 ++#else ++ #define _USB_SPLIT_MDATA_BLOCKING_PATCH 1 ++#endif ++ ++//---- 6. DM always keep high issue ++#if 1 // if without ECO solution, use SW patch. ++ #if 0 ++ #define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 1 ++ #else ++ #define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 0 ++ #endif ++#else ++ #define _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH 0 ++#endif ++ ++//---- 7. clear port eanble when device disconnect while bus reset ++#if 0 // every chip must apply it, so far ++ #define _USB_CLEAR_PORT_ENABLE_AFTER_FAIL_RESET_PATCH 0 ++#else ++ #define _USB_CLEAR_PORT_ENABLE_AFTER_FAIL_RESET_PATCH 1 ++#endif ++ ++//---- 8. mstar host only supports "Throttle Mode" in split translation ++#if 0 // every chip must apply it, so far ++ #define _USB_TURN_ON_TT_THROTTLE_MODE_PATCH 0 ++#else ++ #define _USB_TURN_ON_TT_THROTTLE_MODE_PATCH 1 ++#endif ++ ++//---- 9. lower squelch level to cover weak cable link ++#if 0 ++ #define _USB_ANALOG_RX_SQUELCH_PATCH 1 ++#else ++ #define _USB_ANALOG_RX_SQUELCH_PATCH 0 ++#endif ++ ++//---- 10. high speed reset chirp patch ++#define _USB_HS_CHIRP_PATCH 1 ++ ++//---- 11. friendly customer patch ++#define _USB_FRIENDLY_CUSTOMER_PATCH 1 ++ ++//---- 12. enabe PVCI i_miwcplt wait for mi2uh_last_done_z ++#define _USB_MIU_WRITE_WAIT_LAST_DONE_Z_PATCH 1 ++ ++//---- 13. enabe VBUS reset when ERR_INT_SOF_RXACTIVE occur ++#define _USB_VBUS_RESET_PATCH 1 ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Reduce EOF1 to 12us for performance imporvement ------------- ++#if 1 ++/* Enlarge EOP1 from 12us to 16us for babble prvention under hub case. ++ * However, we keep the "old config name". 20130121 ++ */ ++ #define ENABLE_12US_EOF1 ++#endif ++//-------------------------------------------------------------------- ++ ++#if 0 ++ #define _UTMI_PWR_SAV_MODE_ENABLE 1 ++#else ++ #define _UTMI_PWR_SAV_MODE_ENABLE 0 ++#endif ++ ++//---- Setting PV2MI bridge read/write burst size to minimum ++#define _USB_MINI_PV2MI_BURST_SIZE 1 ++ ++//-------------------------------------------------------------------- ++#define _USB_UTMI_DPDM_SWAP_P0 0 ++#define _USB_UTMI_DPDM_SWAP_P1 0 ++#define _USB_UTMI_DPDM_SWAP_P2 0 ++ ++//------ Titania3_series_start_ehc flag ------------------------------ ++// Use low word as flag ++#define EHCFLAG_NONE 0x0 ++#define EHCFLAG_DPDM_SWAP 0x1 ++#define EHCFLAG_TESTPKG 0x2 ++#define EHCFLAG_DOUBLE_DATARATE 0x4 ++// Use high word as data ++#define EHCFLAG_DDR_MASK 0xF0000000 ++#define EHCFLAG_DDR_x15 0x10000000 //480MHz x1.5 ++#define EHCFLAG_DDR_x18 0x20000000 //480MHz x1.8 ++//-------------------------------------------------------------------- ++// 0x00: 550mv, 0x20: 575, 0x40: 600, 0x60: 625 ++#define UTMI_DISCON_LEVEL_2A (0x62) ++extern int vbus_gpio_of_parse_and_map(struct device_node *node); ++//------ UTMI eye diagram parameters --------------------------------- ++#if 0 ++ // for 40nm ++ #define UTMI_EYE_SETTING_2C (0x98) ++ #define UTMI_EYE_SETTING_2D (0x02) ++ #define UTMI_EYE_SETTING_2E (0x10) ++ #define UTMI_EYE_SETTING_2F (0x01) ++#elif 0 ++ // for 40nm after Agate, use 55nm setting7 ++ #define UTMI_EYE_SETTING_2C (0x90) ++ #define UTMI_EYE_SETTING_2D (0x03) ++ #define UTMI_EYE_SETTING_2E (0x30) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#elif 0 ++ // for 40nm after Agate, use 55nm setting6 ++ #define UTMI_EYE_SETTING_2C (0x10) ++ #define UTMI_EYE_SETTING_2D (0x03) ++ #define UTMI_EYE_SETTING_2E (0x30) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#elif 0 ++ // for 40nm after Agate, use 55nm setting5 ++ #define UTMI_EYE_SETTING_2C (0x90) ++ #define UTMI_EYE_SETTING_2D (0x02) ++ #define UTMI_EYE_SETTING_2E (0x30) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#elif 0 ++ // for 40nm after Agate, use 55nm setting4 ++ #define UTMI_EYE_SETTING_2C (0x90) ++ #define UTMI_EYE_SETTING_2D (0x03) ++ #define UTMI_EYE_SETTING_2E (0x00) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#elif 0 ++ // for 40nm after Agate, use 55nm setting3 ++ #define UTMI_EYE_SETTING_2C (0x10) ++ #define UTMI_EYE_SETTING_2D (0x03) ++ #define UTMI_EYE_SETTING_2E (0x00) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#elif 0 ++ // for 40nm after Agate, use 55nm setting2 ++ #define UTMI_EYE_SETTING_2C (0x90) ++ #define UTMI_EYE_SETTING_2D (0x02) ++ #define UTMI_EYE_SETTING_2E (0x00) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#else ++ // for 40nm after Agate, use 55nm setting1, the default ++ #define UTMI_EYE_SETTING_2C (0x10) ++ #define UTMI_EYE_SETTING_2D (0x02) ++ #define UTMI_EYE_SETTING_2E (0x00) ++ #define UTMI_EYE_SETTING_2F (0x81) ++#endif ++ ++#endif /* _EHCI_MSTAR_H */ +diff --git a/drivers/sstar/usb/host/infinity2/Makefile b/drivers/sstar/usb/host/infinity2/Makefile +new file mode 100644 +index 000000000000..536bab6d70e0 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2/Makefile +@@ -0,0 +1,6 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += usb_pad.o ++ +diff --git a/drivers/sstar/usb/host/infinity2/ehci-mstar-chip.h b/drivers/sstar/usb/host/infinity2/ehci-mstar-chip.h +new file mode 100644 +index 000000000000..1b6e2a1b5a49 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2/ehci-mstar-chip.h +@@ -0,0 +1,65 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++#ifndef _EHCI_MSTAR_CHIP_H ++#define _EHCI_MSTAR_CHIP_H ++ ++//---Port ----------------------------------------------------------------- ++/* If only 1 ports */ ++//#define DISABLE_SECOND_EHC ++ ++//------ Additional port enable (default: 2 ports) ------------------- ++#define ENABLE_THIRD_EHC ++ ++#define ENABLE_FOURTH_EHC ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Battery charger -------------------- ------------------- ++//#define ENABLE_BATTERY_CHARGE ++//#define ENABLE_APPLE_CHARGER_SUPPORT ++//#define USB_NO_BC_FUNCTION ++//#define USB_BATTERY_CHARGE_SETTING_1 ++//-------------------------------------------------------------------- ++ ++ ++//------ UTMI, USBC and UHC base address ----------------------------- ++//---- Port0 ++#define _MSTAR_UTMI0_BASE (_MSTAR_USB_BASEADR+(0x3A80*2)) ++#define _MSTAR_BC0_BASE (_MSTAR_USB_BASEADR+(0x13700*2)) ++#define _MSTAR_USBC0_BASE (_MSTAR_USB_BASEADR+(0x0700*2)) ++#define _MSTAR_UHC0_BASE (_MSTAR_USB_BASEADR+(0x2400*2)) ++ ++//---- Port1 ++#define _MSTAR_UTMI1_BASE (_MSTAR_USB_BASEADR+(0x3A00*2)) ++#define _MSTAR_BC1_BASE (_MSTAR_USB_BASEADR+(0x13720*2)) ++#define _MSTAR_USBC1_BASE (_MSTAR_USB_BASEADR+(0x0780*2)) ++#define _MSTAR_UHC1_BASE (_MSTAR_USB_BASEADR+(0x0D00*2)) ++ ++//---- Port2 ++#define _MSTAR_UTMI2_BASE (_MSTAR_USB_BASEADR+(0x3A80*2)) ++#define _MSTAR_BC2_BASE (_MSTAR_USB_BASEADR+(0x13700*2)) ++#define _MSTAR_USBC2_BASE (_MSTAR_USB_BASEADR+(0x40600*2)) ++#define _MSTAR_UHC2_BASE (_MSTAR_USB_BASEADR+(0x40400*2)) ++ ++//---- Port3 ++#define _MSTAR_UTMI3_BASE (_MSTAR_USB_BASEADR+(0x3880*2)) ++#define _MSTAR_UHC3_BASE (_MSTAR_USB_BASEADR+(0x71A00*2)) ++#define _MSTAR_USBC3_BASE (_MSTAR_USB_BASEADR+(0x71B80*2)) ++#define _MSTAR_BC3_BASE (_MSTAR_USB_BASEADR+(0x3740*2)) ++ ++ ++//---- Chiptop for Chip version ++//#define MSTAR_CHIP_TOP_BASE (_MSTAR_USB_BASEADR+(0x1E00*2)) ++//-------------------------------------------------------------------- ++ ++ ++#endif /* _EHCI_MSTAR_CHIP_H */ +diff --git a/drivers/sstar/usb/host/infinity2/usb_pad.c b/drivers/sstar/usb/host/infinity2/usb_pad.c +new file mode 100755 +index 000000000000..f52eaa43d1a1 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2/usb_pad.c +@@ -0,0 +1,129 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "usb_pad.h" ++ ++ ++int Enable_USB_VBUS(int param) ++{ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ printk(KERN_ERR "[%s_%d] \n", __FUNCTION__,__LINE__); ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else if (1 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-3"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ } ++ ++ if (power_en_gpio >= 0) ++ { ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL(Enable_USB_VBUS); ++ ++int Get_USB_VBUS_Pin(struct device_node *np) ++{ ++ int power_en_gpio=-1; ++ int pin_data; ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ return power_en_gpio; ++} ++EXPORT_SYMBOL(Get_USB_VBUS_Pin); ++ +diff --git a/drivers/sstar/usb/host/infinity2/usb_pad.h b/drivers/sstar/usb/host/infinity2/usb_pad.h +new file mode 100755 +index 000000000000..944f56cadffa +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2/usb_pad.h +@@ -0,0 +1,8 @@ ++#ifndef __USB_PAD_H ++#define __USB_PAD_H ++ ++ ++int Enable_USB_VBUS(int param); ++int Get_USB_VBUS_Pin(struct device_node *np); ++ ++#endif //__USB_PAD_H +diff --git a/drivers/sstar/usb/host/infinity2/usb_patch_mstar.h b/drivers/sstar/usb/host/infinity2/usb_patch_mstar.h +new file mode 100644 +index 000000000000..db27cbafb373 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2/usb_patch_mstar.h +@@ -0,0 +1,36 @@ ++#ifndef _MPATCH_MACRO_H ++#define _MPATCH_MACRO_H ++ ++#define MSTAR_MIU_BUS_BASE_NONE 0xFFFFFFFF ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000 ++#define MSTAR_MIU1_BUS_BASE MSTAR_MIU_BUS_BASE_NONE ++ ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_MSTAR ++ #define MP_USB_MSTAR 1 ++#else ++ #define MP_USB_MSTAR 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_MSTAR_DEBUG ++ #define MP_USB_MSTAR_DEBUG 1 ++#else ++ #define MP_USB_MSTAR_DEBUG 0 ++#endif ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_STR_PATCH ++ #define MP_USB_STR_PATCH 1 ++#else ++ #define MP_USB_STR_PATCH 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH_DEBUG ++ #define MP_USB_STR_PATCH_DEBUG 1 ++#else ++ #define MP_USB_STR_PATCH_DEBUG 0 ++#endif ++ ++#endif //_MPATCH_MACRO_H +diff --git a/drivers/sstar/usb/host/infinity2m/Makefile b/drivers/sstar/usb/host/infinity2m/Makefile +new file mode 100644 +index 000000000000..83d0357c3faf +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2m/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += usb_pad.o +diff --git a/drivers/sstar/usb/host/infinity2m/ehci-mstar-chip.h b/drivers/sstar/usb/host/infinity2m/ehci-mstar-chip.h +new file mode 100644 +index 000000000000..50bb2ecc693e +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2m/ehci-mstar-chip.h +@@ -0,0 +1,58 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++#ifndef _EHCI_MSTAR_CHIP_H ++#define _EHCI_MSTAR_CHIP_H ++ ++//---Port ----------------------------------------------------------------- ++/* If only 1 ports */ ++//#define DISABLE_SECOND_EHC ++ ++//------ Additional port enable (default: 2 ports) ------------------- ++#define ENABLE_THIRD_EHC ++ ++//#define ENABLE_FOURTH_EHC ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Battery charger -------------------- ------------------- ++//#define ENABLE_BATTERY_CHARGE ++//#define ENABLE_APPLE_CHARGER_SUPPORT ++//#define USB_NO_BC_FUNCTION ++//#define USB_BATTERY_CHARGE_SETTING_1 ++//-------------------------------------------------------------------- ++ ++ ++//------ UTMI, USBC and UHC base address ----------------------------- ++//---- Port0 ++#define _MSTAR_UTMI0_BASE (_MSTAR_USB_BASEADR+(0x42100*2)) ++#define _MSTAR_BC0_BASE (_MSTAR_USB_BASEADR+(0x42200*2)) ++#define _MSTAR_USBC0_BASE (_MSTAR_USB_BASEADR+(0x42300*2)) ++#define _MSTAR_UHC0_BASE (_MSTAR_USB_BASEADR+(0x42400*2)) ++ ++//---- Port1 ++#define _MSTAR_UTMI1_BASE (_MSTAR_USB_BASEADR+(0x42500*2)) ++#define _MSTAR_BC1_BASE (_MSTAR_USB_BASEADR+(0x42600*2)) ++#define _MSTAR_USBC1_BASE (_MSTAR_USB_BASEADR+(0x42700*2)) ++#define _MSTAR_UHC1_BASE (_MSTAR_USB_BASEADR+(0x42800*2)) ++ ++//---- Port2 ++#define _MSTAR_UTMI2_BASE (_MSTAR_USB_BASEADR+(0x42900*2)) ++#define _MSTAR_BC2_BASE (_MSTAR_USB_BASEADR+(0x43000*2)) ++#define _MSTAR_USBC2_BASE (_MSTAR_USB_BASEADR+(0x43100*2)) ++#define _MSTAR_UHC2_BASE (_MSTAR_USB_BASEADR+(0x43200*2)) ++ ++//---- Chiptop for Chip version ++//#define MSTAR_CHIP_TOP_BASE (_MSTAR_USB_BASEADR+(0x1E00*2)) ++//-------------------------------------------------------------------- ++ ++ ++#endif /* _EHCI_MSTAR_CHIP_H */ +diff --git a/drivers/sstar/usb/host/infinity2m/usb_pad.c b/drivers/sstar/usb/host/infinity2m/usb_pad.c +new file mode 100755 +index 000000000000..65789255bef4 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2m/usb_pad.c +@@ -0,0 +1,129 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "usb_pad.h" ++ ++ ++int Enable_USB_VBUS(int param) ++{ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else if (1 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-3"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ } ++ ++ if (power_en_gpio >= 0) ++ { ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL(Enable_USB_VBUS); ++ ++int Get_USB_VBUS_Pin(struct device_node *np) ++{ ++ int power_en_gpio=-1; ++ int pin_data; ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ /*else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ }*/ ++ return power_en_gpio; ++} ++EXPORT_SYMBOL(Get_USB_VBUS_Pin); ++ +diff --git a/drivers/sstar/usb/host/infinity2m/usb_pad.h b/drivers/sstar/usb/host/infinity2m/usb_pad.h +new file mode 100755 +index 000000000000..944f56cadffa +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2m/usb_pad.h +@@ -0,0 +1,8 @@ ++#ifndef __USB_PAD_H ++#define __USB_PAD_H ++ ++ ++int Enable_USB_VBUS(int param); ++int Get_USB_VBUS_Pin(struct device_node *np); ++ ++#endif //__USB_PAD_H +diff --git a/drivers/sstar/usb/host/infinity2m/usb_patch_mstar.h b/drivers/sstar/usb/host/infinity2m/usb_patch_mstar.h +new file mode 100644 +index 000000000000..db27cbafb373 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity2m/usb_patch_mstar.h +@@ -0,0 +1,36 @@ ++#ifndef _MPATCH_MACRO_H ++#define _MPATCH_MACRO_H ++ ++#define MSTAR_MIU_BUS_BASE_NONE 0xFFFFFFFF ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000 ++#define MSTAR_MIU1_BUS_BASE MSTAR_MIU_BUS_BASE_NONE ++ ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_MSTAR ++ #define MP_USB_MSTAR 1 ++#else ++ #define MP_USB_MSTAR 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_MSTAR_DEBUG ++ #define MP_USB_MSTAR_DEBUG 1 ++#else ++ #define MP_USB_MSTAR_DEBUG 0 ++#endif ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_STR_PATCH ++ #define MP_USB_STR_PATCH 1 ++#else ++ #define MP_USB_STR_PATCH 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH_DEBUG ++ #define MP_USB_STR_PATCH_DEBUG 1 ++#else ++ #define MP_USB_STR_PATCH_DEBUG 0 ++#endif ++ ++#endif //_MPATCH_MACRO_H +diff --git a/drivers/sstar/usb/host/infinity3/Makefile b/drivers/sstar/usb/host/infinity3/Makefile +new file mode 100755 +index 000000000000..782bcc97f6c4 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity3/Makefile +@@ -0,0 +1,2 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++obj-$(CONFIG_MS_USB_INFINITY3) += ms_usb.o +diff --git a/drivers/sstar/usb/host/infinity3/ms_usb.c b/drivers/sstar/usb/host/infinity3/ms_usb.c +new file mode 100755 +index 000000000000..9e46f15ec642 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity3/ms_usb.c +@@ -0,0 +1,215 @@ ++/* ++* ms_usb.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "infinity/irqs.h" ++#include ++ ++#if defined(CONFIG_MSTAR_AMBER3) || defined(CONFIG_MSTAR_CEDRIC) ++#define ENABLE_THIRD_EHC ++#endif ++ ++#define UTMI_BASE_ADDRESS_START 0xFD284200 ++#define UTMI_BASE_ADDRESS_END 0xFD2842FC ++#define USB_HOST20_ADDRESS_START 0xFD284800 ++#define USB_HOST20_ADDRESS_END 0xFD2849FC ++ ++ ++static struct resource Sstar_usb_ehci_resources[] = { ++ [0] = { ++ .start = UTMI_BASE_ADDRESS_START, ++ .end = UTMI_BASE_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = USB_HOST20_ADDRESS_START, ++ .end = USB_HOST20_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = INT_IRQ_UHC, ++ .end = INT_IRQ_UHC, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++#ifdef ENABLE_THIRD_EHC ++static struct resource Third_Sstar_usb_ehci_resources[] = { ++ [0] = { ++ .start = THIRD_UTMI_BASE_ADDRESS_START, ++ .end = THIRD_UTMI_BASE_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = THIRD_USB_HOST20_ADDRESS_START, ++ .end = THIRD_USB_HOST20_ADDRESS_END, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = INT_IRQ_UHC2, ++ .end = INT_IRQ_UHC2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++#endif ++ ++/* The dmamask must be set for EHCI to work */ ++static u64 ehci_dmamask = ~(u32)0; ++ ++static struct platform_device Sstar_usb_ehci_device = { ++ .name = "Sstar-ehci-1", ++ .id = 0, ++ .dev = { ++ .dma_mask = &ehci_dmamask, ++ .coherent_dma_mask = 0xffffffff, // for limit DMA range ++ }, ++ .num_resources = ARRAY_SIZE(Sstar_usb_ehci_resources), ++ .resource = Sstar_usb_ehci_resources, ++}; ++ ++#ifdef ENABLE_THIRD_EHC ++static struct platform_device Third_Sstar_usb_ehci_device = { ++ .name = "Sstar-ehci-3", ++ .id = 2, ++ .dev = { ++ .dma_mask = &ehci_dmamask, ++ .coherent_dma_mask = 0xffffffff, // for limit DMA range ++ }, ++ .num_resources = ARRAY_SIZE(Third_Sstar_usb_ehci_resources), ++ .resource = Third_Sstar_usb_ehci_resources, ++}; ++#endif ++ ++static struct platform_device *Sstar_platform_devices[] = { ++ &Sstar_usb_ehci_device, ++#ifdef ENABLE_THIRD_EHC ++ &Third_Sstar_usb_ehci_device, ++#endif ++}; ++ ++int Sstar_ehc_platform_init(void) ++{ ++ printk("[USB] add host platform dev....\n"); ++ return platform_add_devices(Sstar_platform_devices, ARRAY_SIZE(Sstar_platform_devices)); ++} ++ ++/* The following code is for OTG implementation */ ++#define USB_USBC_ADDRESS_START 0xFD284600 ++#define USB_USBC_ADDRESS_END 0xFD2846FC ++#define USB_MOTG_ADDRESS_START 0xFD284A00 ++#define USB_MOTG_ADDRESS_END 0xFD284DFC ++ ++static struct resource ms_otg_device_resource[] = ++{ ++ [0] = { ++ .start = USB_USBC_ADDRESS_START, ++ .end = USB_USBC_ADDRESS_END, ++ .name = "usbc-base", ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = USB_HOST20_ADDRESS_START, ++ .end = USB_HOST20_ADDRESS_END, ++ .name = "uhc-base", ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = USB_MOTG_ADDRESS_START, ++ .end = USB_MOTG_ADDRESS_END, ++ .name = "motg-base", ++ .flags = IORESOURCE_MEM, ++ }, ++ [3] = { ++ .start = 94,//INT_IRQ_USB, ++ .end = 94,//INT_IRQ_USB, ++ .name = "usb-int", ++ .flags = IORESOURCE_IRQ, ++ }, ++ [4] = { ++ .start = UTMI_BASE_ADDRESS_START, ++ .end = UTMI_BASE_ADDRESS_END, ++ .name = "utmi-base", ++ .flags = IORESOURCE_MEM, ++ }, ++ [5] = { ++ .start = 95,//INT_IRQ_UHC, ++ .end = 95,//INT_IRQ_UHC, ++ .name = "uhc-int", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device Sstar_otg_device = ++{ ++ .name = "mstar-otg", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ms_otg_device_resource), ++ .resource = ms_otg_device_resource, ++}; ++ ++/* MST154A-D02A0-S utilize GPIO3 to control VBUS */ ++#define MSTAR_CEDRIC_RIU_BASE 0xFD200000 ++extern int Chip_Function_Set(int function_id, int param); ++int ms_BD154A_set_vbus(unsigned int on) ++{ ++ printk("[OTG] set_vbus %d\n", on); ++ ++ Chip_Function_Set(CHIP_FUNC_USB_VBUS_CONTROL , on); ++ //*((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x1A13<<1))) = *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x1A13<<1))) & (u16)0xfff7; ++ //*((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x1A15<<1))) = *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x1A15<<1))) & (u16)0xfff7; ++ //*((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x2B0C<<1))) = *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x2B0C<<1))) & (u16)0xfffd; ++ ++ //if (on) ++ // *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x2B0C<<1))) = *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x2B0C<<1))) | (u16)0x0001; ++ //else ++ // *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x2B0C<<1))) = *((u16 volatile*)(MSTAR_CEDRIC_RIU_BASE+(0x2B0C<<1))) & (u16)0xfffe; ++ return on; ++} ++ ++struct ms_usb_platform_data ms_otg_platform_data = ++{ ++ .mode = 0,//MS_USB_MODE_OTG, ++ .set_vbus = ms_BD154A_set_vbus, ++}; ++ ++int Sstar_otg_platform_init(void) ++{ ++ printk("[OTG] Sstar_otg_device_init\n"); ++ Sstar_otg_device.dev.platform_data = &ms_otg_platform_data; ++ ++ return platform_device_register(&Sstar_otg_device); ++} ++ ++#define DRIVER_DESC "ms_usb" ++#define DRIVER_VERSION "Sep 13, 2012" ++ ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_VERSION(DRIVER_VERSION); ++MODULE_LICENSE("GPL"); ++ ++ ++//arch_initcall(Sstar_ehc_platform_init); ++arch_initcall(Sstar_otg_platform_init); +diff --git a/drivers/sstar/usb/host/infinity5/Makefile b/drivers/sstar/usb/host/infinity5/Makefile +new file mode 100644 +index 000000000000..83d0357c3faf +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity5/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += usb_pad.o +diff --git a/drivers/sstar/usb/host/infinity5/ehci-mstar-chip.h b/drivers/sstar/usb/host/infinity5/ehci-mstar-chip.h +new file mode 100644 +index 000000000000..902f4412f783 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity5/ehci-mstar-chip.h +@@ -0,0 +1,52 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++ ++#ifndef _EHCI_MSTAR_CHIP_H ++#define _EHCI_MSTAR_CHIP_H ++ ++//---Port ----------------------------------------------------------------- ++/* If only 1 ports */ ++//#define DISABLE_SECOND_EHC ++ ++//------ Additional port enable (default: 2 ports) ------------------- ++//#define ENABLE_THIRD_EHC ++ ++//#define ENABLE_FOURTH_EHC ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Battery charger -------------------- ------------------- ++//#define ENABLE_BATTERY_CHARGE ++//#define ENABLE_APPLE_CHARGER_SUPPORT ++//#define USB_NO_BC_FUNCTION ++//#define USB_BATTERY_CHARGE_SETTING_1 ++//-------------------------------------------------------------------- ++ ++ ++//------ UTMI, USBC and UHC base address ----------------------------- ++//---- Port0 ++#define _MSTAR_UTMI0_BASE (_MSTAR_USB_BASEADR+(0x42100*2)) ++#define _MSTAR_BC0_BASE (_MSTAR_USB_BASEADR+(0x42200*2)) ++#define _MSTAR_USBC0_BASE (_MSTAR_USB_BASEADR+(0x42300*2)) ++#define _MSTAR_UHC0_BASE (_MSTAR_USB_BASEADR+(0x42400*2)) ++ ++//---- Port1 ++#define _MSTAR_UTMI1_BASE (_MSTAR_USB_BASEADR+(0x42900*2)) ++#define _MSTAR_BC1_BASE (_MSTAR_USB_BASEADR+(0x43000*2)) ++#define _MSTAR_USBC1_BASE (_MSTAR_USB_BASEADR+(0x43100*2)) ++#define _MSTAR_UHC1_BASE (_MSTAR_USB_BASEADR+(0x43200*2)) ++ ++//---- Chiptop for Chip version ++//#define MSTAR_CHIP_TOP_BASE (_MSTAR_USB_BASEADR+(0x1E00*2)) ++//-------------------------------------------------------------------- ++ ++#endif /* _EHCI_MSTAR_CHIP_H */ +diff --git a/drivers/sstar/usb/host/infinity5/usb_pad.c b/drivers/sstar/usb/host/infinity5/usb_pad.c +new file mode 100755 +index 000000000000..0635be928c86 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity5/usb_pad.c +@@ -0,0 +1,128 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "usb_pad.h" ++ ++ ++int Enable_USB_VBUS(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++ ++ ++EXPORT_SYMBOL(Enable_USB_VBUS); ++ ++int Get_USB_VBUS_Pin(struct device_node *np) ++{ ++ int power_en_gpio=-1; ++ int pin_data; ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ return power_en_gpio; ++} ++EXPORT_SYMBOL(Get_USB_VBUS_Pin); ++ +diff --git a/drivers/sstar/usb/host/infinity5/usb_pad.h b/drivers/sstar/usb/host/infinity5/usb_pad.h +new file mode 100755 +index 000000000000..944f56cadffa +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity5/usb_pad.h +@@ -0,0 +1,8 @@ ++#ifndef __USB_PAD_H ++#define __USB_PAD_H ++ ++ ++int Enable_USB_VBUS(int param); ++int Get_USB_VBUS_Pin(struct device_node *np); ++ ++#endif //__USB_PAD_H +diff --git a/drivers/sstar/usb/host/infinity5/usb_patch_mstar.h b/drivers/sstar/usb/host/infinity5/usb_patch_mstar.h +new file mode 100644 +index 000000000000..b266e1b7e3d1 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity5/usb_patch_mstar.h +@@ -0,0 +1,35 @@ ++#ifndef _MPATCH_MACRO_H ++#define _MPATCH_MACRO_H ++ ++#define MSTAR_MIU_BUS_BASE_NONE 0xFFFFFFFF ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000 ++#define MSTAR_MIU1_BUS_BASE 0xA0000000 ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_MSTAR ++ #define MP_USB_MSTAR 1 ++#else ++ #define MP_USB_MSTAR 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_MSTAR_DEBUG ++ #define MP_USB_MSTAR_DEBUG 1 ++#else ++ #define MP_USB_MSTAR_DEBUG 0 ++#endif ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_STR_PATCH ++ #define MP_USB_STR_PATCH 1 ++#else ++ #define MP_USB_STR_PATCH 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH_DEBUG ++ #define MP_USB_STR_PATCH_DEBUG 1 ++#else ++ #define MP_USB_STR_PATCH_DEBUG 0 ++#endif ++ ++#endif //_MPATCH_MACRO_H +diff --git a/drivers/sstar/usb/host/infinity6/Makefile b/drivers/sstar/usb/host/infinity6/Makefile +new file mode 100644 +index 000000000000..83d0357c3faf +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += usb_pad.o +diff --git a/drivers/sstar/usb/host/infinity6/ehci-mstar-chip.h b/drivers/sstar/usb/host/infinity6/ehci-mstar-chip.h +new file mode 100644 +index 000000000000..48f313c48681 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6/ehci-mstar-chip.h +@@ -0,0 +1,52 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++ ++#ifndef _EHCI_MSTAR_CHIP_H ++#define _EHCI_MSTAR_CHIP_H ++ ++//---Port ----------------------------------------------------------------- ++/* If only 1 ports */ ++#define DISABLE_SECOND_EHC ++ ++//------ Additional port enable (default: 2 ports) ------------------- ++//#define ENABLE_THIRD_EHC ++ ++//#define ENABLE_FOURTH_EHC ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Battery charger -------------------- ------------------- ++//#define ENABLE_BATTERY_CHARGE ++//#define ENABLE_APPLE_CHARGER_SUPPORT ++//#define USB_NO_BC_FUNCTION ++//#define USB_BATTERY_CHARGE_SETTING_1 ++//-------------------------------------------------------------------- ++ ++ ++//------ UTMI, USBC and UHC base address ----------------------------- ++//---- Port0 ++#define _MSTAR_UTMI0_BASE (_MSTAR_USB_BASEADR+(0x42100*2)) ++#define _MSTAR_BC0_BASE (_MSTAR_USB_BASEADR+(0x42200*2)) ++#define _MSTAR_USBC0_BASE (_MSTAR_USB_BASEADR+(0x42300*2)) ++#define _MSTAR_UHC0_BASE (_MSTAR_USB_BASEADR+(0x42400*2)) ++ ++//---- Port1 ++#define _MSTAR_UTMI1_BASE (_MSTAR_USB_BASEADR+(0x42900*2)) ++#define _MSTAR_BC1_BASE (_MSTAR_USB_BASEADR+(0x43000*2)) ++#define _MSTAR_USBC1_BASE (_MSTAR_USB_BASEADR+(0x43100*2)) ++#define _MSTAR_UHC1_BASE (_MSTAR_USB_BASEADR+(0x43200*2)) ++ ++//---- Chiptop for Chip version ++//#define MSTAR_CHIP_TOP_BASE (_MSTAR_USB_BASEADR+(0x1E00*2)) ++//-------------------------------------------------------------------- ++ ++#endif /* _EHCI_MSTAR_H */ +diff --git a/drivers/sstar/usb/host/infinity6/usb_pad.c b/drivers/sstar/usb/host/infinity6/usb_pad.c +new file mode 100755 +index 000000000000..09f90a393a1a +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6/usb_pad.c +@@ -0,0 +1,127 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "usb_pad.h" ++ ++ ++int Enable_USB_VBUS(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ //printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ //printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++EXPORT_SYMBOL(Enable_USB_VBUS); ++ ++int Get_USB_VBUS_Pin(struct device_node *np) ++{ ++ int power_en_gpio=-1; ++ int pin_data; ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ return power_en_gpio; ++} ++EXPORT_SYMBOL(Get_USB_VBUS_Pin); ++ +diff --git a/drivers/sstar/usb/host/infinity6/usb_pad.h b/drivers/sstar/usb/host/infinity6/usb_pad.h +new file mode 100755 +index 000000000000..944f56cadffa +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6/usb_pad.h +@@ -0,0 +1,8 @@ ++#ifndef __USB_PAD_H ++#define __USB_PAD_H ++ ++ ++int Enable_USB_VBUS(int param); ++int Get_USB_VBUS_Pin(struct device_node *np); ++ ++#endif //__USB_PAD_H +diff --git a/drivers/sstar/usb/host/infinity6/usb_patch_mstar.h b/drivers/sstar/usb/host/infinity6/usb_patch_mstar.h +new file mode 100644 +index 000000000000..db27cbafb373 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6/usb_patch_mstar.h +@@ -0,0 +1,36 @@ ++#ifndef _MPATCH_MACRO_H ++#define _MPATCH_MACRO_H ++ ++#define MSTAR_MIU_BUS_BASE_NONE 0xFFFFFFFF ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000 ++#define MSTAR_MIU1_BUS_BASE MSTAR_MIU_BUS_BASE_NONE ++ ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_MSTAR ++ #define MP_USB_MSTAR 1 ++#else ++ #define MP_USB_MSTAR 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_MSTAR_DEBUG ++ #define MP_USB_MSTAR_DEBUG 1 ++#else ++ #define MP_USB_MSTAR_DEBUG 0 ++#endif ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_STR_PATCH ++ #define MP_USB_STR_PATCH 1 ++#else ++ #define MP_USB_STR_PATCH 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH_DEBUG ++ #define MP_USB_STR_PATCH_DEBUG 1 ++#else ++ #define MP_USB_STR_PATCH_DEBUG 0 ++#endif ++ ++#endif //_MPATCH_MACRO_H +diff --git a/drivers/sstar/usb/host/infinity6b0/Makefile b/drivers/sstar/usb/host/infinity6b0/Makefile +new file mode 100644 +index 000000000000..83d0357c3faf +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6b0/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += usb_pad.o +diff --git a/drivers/sstar/usb/host/infinity6b0/ehci-mstar-chip.h b/drivers/sstar/usb/host/infinity6b0/ehci-mstar-chip.h +new file mode 100644 +index 000000000000..48f313c48681 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6b0/ehci-mstar-chip.h +@@ -0,0 +1,52 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++ ++#ifndef _EHCI_MSTAR_CHIP_H ++#define _EHCI_MSTAR_CHIP_H ++ ++//---Port ----------------------------------------------------------------- ++/* If only 1 ports */ ++#define DISABLE_SECOND_EHC ++ ++//------ Additional port enable (default: 2 ports) ------------------- ++//#define ENABLE_THIRD_EHC ++ ++//#define ENABLE_FOURTH_EHC ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Battery charger -------------------- ------------------- ++//#define ENABLE_BATTERY_CHARGE ++//#define ENABLE_APPLE_CHARGER_SUPPORT ++//#define USB_NO_BC_FUNCTION ++//#define USB_BATTERY_CHARGE_SETTING_1 ++//-------------------------------------------------------------------- ++ ++ ++//------ UTMI, USBC and UHC base address ----------------------------- ++//---- Port0 ++#define _MSTAR_UTMI0_BASE (_MSTAR_USB_BASEADR+(0x42100*2)) ++#define _MSTAR_BC0_BASE (_MSTAR_USB_BASEADR+(0x42200*2)) ++#define _MSTAR_USBC0_BASE (_MSTAR_USB_BASEADR+(0x42300*2)) ++#define _MSTAR_UHC0_BASE (_MSTAR_USB_BASEADR+(0x42400*2)) ++ ++//---- Port1 ++#define _MSTAR_UTMI1_BASE (_MSTAR_USB_BASEADR+(0x42900*2)) ++#define _MSTAR_BC1_BASE (_MSTAR_USB_BASEADR+(0x43000*2)) ++#define _MSTAR_USBC1_BASE (_MSTAR_USB_BASEADR+(0x43100*2)) ++#define _MSTAR_UHC1_BASE (_MSTAR_USB_BASEADR+(0x43200*2)) ++ ++//---- Chiptop for Chip version ++//#define MSTAR_CHIP_TOP_BASE (_MSTAR_USB_BASEADR+(0x1E00*2)) ++//-------------------------------------------------------------------- ++ ++#endif /* _EHCI_MSTAR_H */ +diff --git a/drivers/sstar/usb/host/infinity6b0/usb_pad.c b/drivers/sstar/usb/host/infinity6b0/usb_pad.c +new file mode 100755 +index 000000000000..09f90a393a1a +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6b0/usb_pad.c +@@ -0,0 +1,127 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "usb_pad.h" ++ ++ ++int Enable_USB_VBUS(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ //printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ //printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++EXPORT_SYMBOL(Enable_USB_VBUS); ++ ++int Get_USB_VBUS_Pin(struct device_node *np) ++{ ++ int power_en_gpio=-1; ++ int pin_data; ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ return power_en_gpio; ++} ++EXPORT_SYMBOL(Get_USB_VBUS_Pin); ++ +diff --git a/drivers/sstar/usb/host/infinity6b0/usb_pad.h b/drivers/sstar/usb/host/infinity6b0/usb_pad.h +new file mode 100755 +index 000000000000..944f56cadffa +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6b0/usb_pad.h +@@ -0,0 +1,8 @@ ++#ifndef __USB_PAD_H ++#define __USB_PAD_H ++ ++ ++int Enable_USB_VBUS(int param); ++int Get_USB_VBUS_Pin(struct device_node *np); ++ ++#endif //__USB_PAD_H +diff --git a/drivers/sstar/usb/host/infinity6b0/usb_patch_mstar.h b/drivers/sstar/usb/host/infinity6b0/usb_patch_mstar.h +new file mode 100644 +index 000000000000..db27cbafb373 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6b0/usb_patch_mstar.h +@@ -0,0 +1,36 @@ ++#ifndef _MPATCH_MACRO_H ++#define _MPATCH_MACRO_H ++ ++#define MSTAR_MIU_BUS_BASE_NONE 0xFFFFFFFF ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000 ++#define MSTAR_MIU1_BUS_BASE MSTAR_MIU_BUS_BASE_NONE ++ ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_MSTAR ++ #define MP_USB_MSTAR 1 ++#else ++ #define MP_USB_MSTAR 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_MSTAR_DEBUG ++ #define MP_USB_MSTAR_DEBUG 1 ++#else ++ #define MP_USB_MSTAR_DEBUG 0 ++#endif ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_STR_PATCH ++ #define MP_USB_STR_PATCH 1 ++#else ++ #define MP_USB_STR_PATCH 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH_DEBUG ++ #define MP_USB_STR_PATCH_DEBUG 1 ++#else ++ #define MP_USB_STR_PATCH_DEBUG 0 ++#endif ++ ++#endif //_MPATCH_MACRO_H +diff --git a/drivers/sstar/usb/host/infinity6e/Makefile b/drivers/sstar/usb/host/infinity6e/Makefile +new file mode 100644 +index 000000000000..83d0357c3faf +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6e/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-y += usb_pad.o +diff --git a/drivers/sstar/usb/host/infinity6e/ehci-mstar-chip.h b/drivers/sstar/usb/host/infinity6e/ehci-mstar-chip.h +new file mode 100644 +index 000000000000..48f313c48681 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6e/ehci-mstar-chip.h +@@ -0,0 +1,52 @@ ++/* ++ * eHCI host controller driver ++ * ++ * Copyright (C) 2012~2017 MStar Inc. ++ * ++ * ++ * Date: 2015.12.11 ++ * 1. software patch of VFall state machine mistake is removed, all chips ++ * run with kernel 4.4.3 should be VFall hardware ECO ++ */ ++ ++#ifndef _EHCI_MSTAR_CHIP_H ++#define _EHCI_MSTAR_CHIP_H ++ ++//---Port ----------------------------------------------------------------- ++/* If only 1 ports */ ++#define DISABLE_SECOND_EHC ++ ++//------ Additional port enable (default: 2 ports) ------------------- ++//#define ENABLE_THIRD_EHC ++ ++//#define ENABLE_FOURTH_EHC ++ ++//-------------------------------------------------------------------- ++ ++ ++//------ Battery charger -------------------- ------------------- ++//#define ENABLE_BATTERY_CHARGE ++//#define ENABLE_APPLE_CHARGER_SUPPORT ++//#define USB_NO_BC_FUNCTION ++//#define USB_BATTERY_CHARGE_SETTING_1 ++//-------------------------------------------------------------------- ++ ++ ++//------ UTMI, USBC and UHC base address ----------------------------- ++//---- Port0 ++#define _MSTAR_UTMI0_BASE (_MSTAR_USB_BASEADR+(0x42100*2)) ++#define _MSTAR_BC0_BASE (_MSTAR_USB_BASEADR+(0x42200*2)) ++#define _MSTAR_USBC0_BASE (_MSTAR_USB_BASEADR+(0x42300*2)) ++#define _MSTAR_UHC0_BASE (_MSTAR_USB_BASEADR+(0x42400*2)) ++ ++//---- Port1 ++#define _MSTAR_UTMI1_BASE (_MSTAR_USB_BASEADR+(0x42900*2)) ++#define _MSTAR_BC1_BASE (_MSTAR_USB_BASEADR+(0x43000*2)) ++#define _MSTAR_USBC1_BASE (_MSTAR_USB_BASEADR+(0x43100*2)) ++#define _MSTAR_UHC1_BASE (_MSTAR_USB_BASEADR+(0x43200*2)) ++ ++//---- Chiptop for Chip version ++//#define MSTAR_CHIP_TOP_BASE (_MSTAR_USB_BASEADR+(0x1E00*2)) ++//-------------------------------------------------------------------- ++ ++#endif /* _EHCI_MSTAR_H */ +diff --git a/drivers/sstar/usb/host/infinity6e/usb_pad.c b/drivers/sstar/usb/host/infinity6e/usb_pad.c +new file mode 100755 +index 000000000000..ac5a6b9cf43d +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6e/usb_pad.c +@@ -0,0 +1,128 @@ ++/* ++* soc.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: Karl.Xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "gpio.h" ++#include "registers.h" ++#include "mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++#include "usb_pad.h" ++ ++ ++int Enable_USB_VBUS(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ int port_num = param >> 16; ++ int vbus_enable = param & 0xFF; ++ if((vbus_enable<0 || vbus_enable>1) && (port_num<0 || port_num>1)) ++ { ++ printk(KERN_ERR "[%s] param invalid:%d %d\n", __FUNCTION__, port_num, vbus_enable); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ if(0 == port_num) ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-1"); ++ } ++ else ++ { ++ np = of_find_node_by_path("/soc/Sstar-ehci-2"); ++ } ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == vbus_enable) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == vbus_enable) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++ ++EXPORT_SYMBOL(Enable_USB_VBUS); ++ ++int Get_USB_VBUS_Pin(struct device_node *np) ++{ ++ int power_en_gpio=-1; ++ int pin_data; ++ ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ return power_en_gpio; ++} ++EXPORT_SYMBOL(Get_USB_VBUS_Pin); ++ +diff --git a/drivers/sstar/usb/host/infinity6e/usb_pad.h b/drivers/sstar/usb/host/infinity6e/usb_pad.h +new file mode 100755 +index 000000000000..944f56cadffa +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6e/usb_pad.h +@@ -0,0 +1,8 @@ ++#ifndef __USB_PAD_H ++#define __USB_PAD_H ++ ++ ++int Enable_USB_VBUS(int param); ++int Get_USB_VBUS_Pin(struct device_node *np); ++ ++#endif //__USB_PAD_H +diff --git a/drivers/sstar/usb/host/infinity6e/usb_patch_mstar.h b/drivers/sstar/usb/host/infinity6e/usb_patch_mstar.h +new file mode 100644 +index 000000000000..db27cbafb373 +--- /dev/null ++++ b/drivers/sstar/usb/host/infinity6e/usb_patch_mstar.h +@@ -0,0 +1,36 @@ ++#ifndef _MPATCH_MACRO_H ++#define _MPATCH_MACRO_H ++ ++#define MSTAR_MIU_BUS_BASE_NONE 0xFFFFFFFF ++ ++#define MSTAR_MIU0_BUS_BASE 0x20000000 ++#define MSTAR_MIU1_BUS_BASE MSTAR_MIU_BUS_BASE_NONE ++ ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_MSTAR ++ #define MP_USB_MSTAR 1 ++#else ++ #define MP_USB_MSTAR 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_MSTAR_DEBUG ++ #define MP_USB_MSTAR_DEBUG 1 ++#else ++ #define MP_USB_MSTAR_DEBUG 0 ++#endif ++ ++//=========================== Module:USB======================================= ++#ifdef CONFIG_MP_USB_STR_PATCH ++ #define MP_USB_STR_PATCH 1 ++#else ++ #define MP_USB_STR_PATCH 0 ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH_DEBUG ++ #define MP_USB_STR_PATCH_DEBUG 1 ++#else ++ #define MP_USB_STR_PATCH_DEBUG 0 ++#endif ++ ++#endif //_MPATCH_MACRO_H +diff --git a/drivers/sstar/usb/host/mstar-lib.c b/drivers/sstar/usb/host/mstar-lib.c +new file mode 100644 +index 000000000000..b7f79646b01d +--- /dev/null ++++ b/drivers/sstar/usb/host/mstar-lib.c +@@ -0,0 +1,93 @@ ++/* ++ * Mstar USB host lib ++ * Copyright (C) 2014 MStar Inc. ++ * Date: AUG 2014 ++ */ ++ ++#include ++#include ++#include ++#include "ehci-mstar.h" ++#include "mstar-lib.h" ++ ++ ++static inline void mstar_efuse_set_addr(uintptr_t addr, u16 u16value) ++{ ++ //writew(XHC_EFUSE_OFFSET, (void*)(_MSTAR_EFUSE_BASE+0x4E*2)); ++ writew(u16value, (void*)addr); ++} ++ ++static inline void mstar_efuse_trig_read(uintptr_t addr, u16 u16value) ++{ ++ writew(readw((void*)addr) | u16value, (void*)addr); ++} ++ ++void mstar_efuse_wait_complete(uintptr_t addr, u16 u16value) ++{ ++ int i; ++ ++ for (i=0; i<10000; i++) { ++ if ((readw((void*)addr) & u16value) == 0) ++ break; ++ udelay(1); ++ } ++ if (10000==i) { ++ // timeout: 10ms ++ printk(" !!! WARNING: read eFuse timeout !!!\n"); ++ return; ++ } ++} ++ ++static inline u16 mstar_efuse_read_data(uintptr_t addr) ++{ ++ return readw((void*)addr); ++} ++ ++u32 mstar_efuse_read(struct mstar_efuse *efuse) ++{ ++ unsigned long flags; ++ u16 val; ++ u32 ret; ++ spinlock_t efuse_lock=__SPIN_LOCK_UNLOCKED(efuse_lock); ++ ++ spin_lock_irqsave (&efuse_lock, flags); ++ ++ //set address ++ mstar_efuse_set_addr(efuse->efuse_base_addr+efuse->reg_set_addr, efuse->bank_addr); ++ ++ //trig read command ++ mstar_efuse_trig_read(efuse->efuse_base_addr+efuse->reg_read, efuse->issue_read); ++ ++ //wait read complete ++ mstar_efuse_wait_complete(efuse->efuse_base_addr+efuse->reg_read, efuse->issue_read); ++ ++ //read data ++ val = mstar_efuse_read_data(efuse->efuse_base_addr+efuse->reg_data); ++ ret = val; ++ val = mstar_efuse_read_data(efuse->efuse_base_addr+efuse->reg_data+0x2*2); ++ ret += ((u32)val<<16); ++ ++ spin_unlock_irqrestore (&efuse_lock, flags); ++ ++ return ret; ++ ++} ++ ++#if defined(MSTAR_EFUSE_RTERM) ++u16 mstar_efuse_rterm(void) ++{ ++ struct mstar_efuse efuse; ++ ++ efuse.efuse_base_addr = MSTAR_EFUSE_BASE; ++ efuse.reg_set_addr = EFUSE_REG_ADDR; ++ efuse.reg_read = EFUSE_REG_READ; ++ efuse.reg_data = EFUSE_REG_DATA; ++ efuse.bank_addr = RTERM_BANK; ++ efuse.issue_read = EFUSE_READ_TRIG; ++ ++ return (u16)mstar_efuse_read(&efuse); ++} ++ ++EXPORT_SYMBOL_GPL(mstar_efuse_read); ++EXPORT_SYMBOL_GPL(mstar_efuse_rterm); ++#endif +diff --git a/drivers/sstar/usb/host/mstar-lib.h b/drivers/sstar/usb/host/mstar-lib.h +new file mode 100644 +index 000000000000..f773ee44287c +--- /dev/null ++++ b/drivers/sstar/usb/host/mstar-lib.h +@@ -0,0 +1,18 @@ ++#ifndef __MSTAR_USB_LIB_H ++#define __MSTAR_USB_LIB_H ++ ++ ++struct mstar_efuse { ++ uintptr_t efuse_base_addr; ++ u32 reg_set_addr; //register offset for set_addr ++ u32 reg_read; //register offset for issue_read ++ u32 reg_data; //register offset for data ++ u16 bank_addr; ++ u16 issue_read; ++}; ++ ++ ++extern u32 mstar_efuse_read(struct mstar_efuse *efuse); ++extern u16 mstar_efuse_rterm(void); ++ ++#endif +diff --git a/drivers/sstar/usb/host/usb_common_sstar.h b/drivers/sstar/usb/host/usb_common_sstar.h +new file mode 100644 +index 000000000000..55a3aa8f1fa7 +--- /dev/null ++++ b/drivers/sstar/usb/host/usb_common_sstar.h +@@ -0,0 +1,26 @@ ++ ++ ++#ifndef _USB_SSTAR_H ++#define _USB_SSTAR_H ++ ++//#if (MP_USB_MSTAR==1) ++#if 1 ++ ++//Host ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ ++#include "ehci-mstar.h" ++ ++//Core ++#include "xhci-mstar.h" ++#include ++#if (_UTMI_PWR_SAV_MODE_ENABLE == 1) || defined(USB_MAC_SRAM_POWER_DOWN_ENABLE) ++#include "bc-mstar.h" ++#endif ++ ++ ++#endif ++ ++#endif /* _USB_SSTAR_H */ +diff --git a/drivers/sstar/usb/host/xhci-mstar-chip.h b/drivers/sstar/usb/host/xhci-mstar-chip.h +new file mode 100644 +index 000000000000..313e6e75b03a +--- /dev/null ++++ b/drivers/sstar/usb/host/xhci-mstar-chip.h +@@ -0,0 +1,148 @@ ++/* ++ * xHCI host controller driver ++ * ++ * Copyright (C) 2013 MStar Inc. ++ * ++ */ ++ ++#ifndef _XHCI_MSTAR_CIP_H ++#define _XHCI_MSTAR_CIP_H ++ ++#include "ehci-mstar.h" ++ ++// ----- Don't modify it !---------- ++#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) ++#define XHCI_PA_PATCH 1 ++#else ++#define XHCI_PA_PATCH 0 ++#endif ++#define XHCI_FLUSHPIPE_PATCH 1 ++//------------------------------ ++ ++#define XHCI_CHIRP_PATCH 1 ++#define ENABLE_XHCI_SSC 1 ++ ++#if (ENABLE_XHCI_SSC) ++#define XHCI_SSC_TX_SYNTH_SET_C0 0x9374 ++#define XHCI_SSC_TX_SYNTH_SET_C2 0x18 ++#define XHCI_SSC_TX_SYNTH_STEP_C4 0x7002 ++#define XHCI_SSC_TX_SYNTH_SPAN_C6 0x04D8 ++#endif ++ ++#define ENABLE_SECOND_XHC ++ ++#define XHCI_TX_SWING_PATCH 1 ++ ++//------ for test ----------------- ++//#define XHCI_CURRENT_SHARE_PATCH 0 //Only for USB3; will cause USB2 chirp handshake fail. ++#define XHCI_ENABLE_DEQ 0 ++#define XHCI_ENABLE_TESTBUS 0 ++//-------------------------------- ++ ++//Inter packet delay setting for all chips ++#define XHCI_IPACKET_DELAY_PATCH ++ ++#define XHCI_DISABLE_COMPLIANCE ++#define XHCI_DISABLE_TESTMODE ++#define XHCI_SSDISABLED_PATCH ++#define XHCI_HC_RESET_PATCH ++ ++#define MSTAR_LOST_SLOT_PATCH 0 ++ ++#define XHCI_TX_ERR_EVENT_PATCH ++ ++//#define XHCI_ENABLE_PPC ++ ++//-------- Setting option ----------- ++ ++#define XHCI_ENABLE_240MHZ ++ ++#define XHCI_ENABLE_LASTDOWNZ ++ ++//-------------------------------- ++ ++ ++// --------- ECO option --------- ++#define XHCI_ENABLE_LOOPBACK_ECO ++#define LOOPBACK_ECO_OFFSET 0x20*2 ++#define LOOPBACK_ECO_BIT BIT4|BIT5 ++ ++//-------------------------------- ++ ++ ++//-------- U3 PHY IP ----------- ++#define XHCI_PHY_MS28 ++ ++#ifdef XHCI_PHY_MS28 ++#define GCR_USB3RX0_RCTRL (0x08*2) ++#define GCR_USB3TX0_RT (0x10*2) ++#define GCR_USB3RX1_RCTRL (0x08*2) ++#define GCR_USB3TX1_RT (0x10*2) ++ ++#define USB30RX0_EFUSE_BITOFFSET 8 ++#define USB30TX0_EFUSE_BITOFFSET 0 ++#define USB30RX1_EFUSE_BITOFFSET 24 ++#define USB30TX1_EFUSE_BITOFFSET 16 ++#endif ++ ++//#define XHCI_2PORTS ++ ++#define XHCI_COMPANION ++ ++//#define XHCI_ENABLE_PD_OVERRIDE ++ ++#define U3PHY_RX_DETECT_POWER_SAVING ++ ++#if defined(XHCI_2PORTS) ++#define XHCI_SSDISABLE_POWERDOWN_PATCH ++#endif ++ ++//#define XHCI_PHY_ENABLE_RX_LOCK ++ ++//#define XHCI_PWS_P2 ++ ++//-------------------------------- ++ ++#if defined(CONFIG_ARM64) ++ extern ptrdiff_t mstar_pm_base; ++ #define _MSTAR_PM_BASE (mstar_pm_base) ++#elif defined(CONFIG_ARM) ++ #define _MSTAR_PM_BASE 0xFD000000 ++#else ++ #define _MSTAR_PM_BASE 0xBF000000 ++#endif ++ ++//------ U3TOP, DTOP, ATOP and XHC base address ----------------------------- ++//---- Port0 ++//#define _MSTAR_U3PHY_DTOP_BASE (_MSTAR_USB_BASEADR+(0x11C00*2)) ++//#define _MSTAR_U3PHY_ATOP_BASE (_MSTAR_USB_BASEADR+(0x22100*2)) ++//#define _MSTAR_U3UTMI_BASE 0 ++//#define _MSTAR_U3TOP_BASE (_MSTAR_USB_BASEADR+(0x40200*2)) ++//#define _MSTAR_XHCI_BASE (_MSTAR_PM_BASE+(0x380000*2)) ++//#define _MSTAR_U3BC_BASE 0 ++ ++#define _MSTAR_U3PHY_DTOP0_BASE (_MSTAR_USB_BASEADR+(0x02000*2)) ++#define _MSTAR_U3PHY_ATOP0_BASE (_MSTAR_USB_BASEADR+(0x02100*2)) ++#define _MSTAR_U3TOP0_BASE (_MSTAR_USB_BASEADR+(0x40200*2)) ++#define _MSTAR_XHCI0_BASE (_MSTAR_PM_BASE+(0x380000*2)) ++#define _MSTAR_U3UTMI0_BASE 0 ++#define _MSTAR_U3BC0_BASE 0 ++ ++//---- Port1 ++#ifdef ENABLE_SECOND_XHC ++#define _MSTAR_U3PHY_DTOP1_BASE (_MSTAR_USB_BASEADR+(0x02200*2)) ++#define _MSTAR_U3PHY_ATOP1_BASE (_MSTAR_USB_BASEADR+(0x02300*2)) ++#define _MSTAR_U3TOP1_BASE (_MSTAR_USB_BASEADR+(0x71900*2)) ++#define _MSTAR_XHCI1_BASE (_MSTAR_PM_BASE+(0x390000*2)) ++#define _MSTAR_U3UTMI1_BASE 0 ++#define _MSTAR_U3BC1_BASE 0 ++#endif ++ ++#define XHC_HSPORT_OFFSET 0x420 ++#define XHC_SSPORT_OFFSET 0x430 ++ ++#if defined(XHCI_PHY_EFUSE) ++ #define RTERM_XHC_BANK (0x50*4) //bank 0x50 ++#endif ++ ++#endif /* _XHCI_MSTAR_CIP_H */ +diff --git a/drivers/sstar/usb/host/xhci-mstar.h b/drivers/sstar/usb/host/xhci-mstar.h +new file mode 100644 +index 000000000000..73d182711620 +--- /dev/null ++++ b/drivers/sstar/usb/host/xhci-mstar.h +@@ -0,0 +1,30 @@ ++/* ++ * xHCI host controller driver ++ * ++ * Copyright (C) 2013~2017 MStar Inc. ++ * ++ */ ++ ++#ifndef _XHCI_MSTAR_H ++#define _XHCI_MSTAR_H ++ ++#define XHCI_MSTAR_VERSION "20171018" ++ ++#include "xhci-mstar-chip.h" ++ ++struct u3phy_addr_base { ++ uintptr_t utmi_base; ++ uintptr_t bc_base; ++ uintptr_t u3top_base; ++ uintptr_t xhci_base; ++ uintptr_t u3dtop_base; ++ uintptr_t u3atop_base; ++ uintptr_t u3dtop1_base; /* XHCI 2 ports */ ++ uintptr_t u3atop1_base; ++}; ++ ++/* ---- Mstar XHCI Flag ----- */ ++#define XHCFLAG_NONE 0x0 ++#define XHCFLAG_DEGRADATION 0x1000 ++ ++#endif /* _XHCI_MSTAR_H */ +diff --git a/drivers/sstar/vcore_dvfs/Kconfig b/drivers/sstar/vcore_dvfs/Kconfig +new file mode 100755 +index 000000000000..2499f9913983 +--- /dev/null ++++ b/drivers/sstar/vcore_dvfs/Kconfig +@@ -0,0 +1,10 @@ ++config VCORE_DVFS ++ tristate "vcore_dvfs driver" ++ default y if ARCH_INFINITY2 ++ help ++ Say Y here to enable the driver for the vcore. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called vcore_dvfs. +diff --git a/drivers/sstar/vcore_dvfs/Makefile b/drivers/sstar/vcore_dvfs/Makefile +new file mode 100755 +index 000000000000..682aeb5a8a92 +--- /dev/null ++++ b/drivers/sstar/vcore_dvfs/Makefile +@@ -0,0 +1,15 @@ ++# ++# Makefile for SStar vcore_dvfs drivers. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/gpio ++ ++# specific options ++EXTRA_CFLAGS += -DTITANIA ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_VCORE_DVFS) += vcore_dvfs.o +diff --git a/drivers/sstar/vcore_dvfs/vcore_dvfs.c b/drivers/sstar/vcore_dvfs/vcore_dvfs.c +new file mode 100755 +index 000000000000..6f2127c0af90 +--- /dev/null ++++ b/drivers/sstar/vcore_dvfs/vcore_dvfs.c +@@ -0,0 +1,1199 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// ++#include "mdrv_gpio.h" ++#include "vcore_dvfs.h" ++ ++ ++ ++#define VCORE_DVFS_DEBUG (0) ++ ++// ++#if VCORE_DVFS_DEBUG ++#define VCORE_DVFS_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define VCORE_DVFS_DBG(fmt, arg...) ++#endif ++#define VCORE_DVFS_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#define vcore_dvfs_success (0) ++#define vcore_dvfs_fail (-1) ++ ++// ++DEFINE_MUTEX(vcore_dvfs_mutex_lock); ++ ++//#define VCORE_DVFS_MUTEX_INIT(x) mutex_init(x) // Use DEFINE_MUTEX, so don't need this. ++#define VCORE_DVFS_MUTEX_LOCK(x) mutex_lock(x) ++#define VCORE_DVFS_MUTEX_UNLOCK(x) mutex_unlock(x) ++ ++#define IF_NOT_ININTED() (vcore_dvfs_info.inited != true) ++#define IF_IDX_VALID(x) ((0 <= x) && (x < vcore_dvfs_info.voltages_total_num)) ++#define IF_SEQ_VALID(x) (IF_IDX_VALID(x)) ++#define IF_DEMENDER_VALID(x) ((0 <= x) && (x < VCORE_DVFS_DEMANDER_TOTAL)) ++ ++ ++ ++struct rate_voltage { ++ unsigned long rate; ++ int voltage; ++}; ++ ++ ++// ++#define VOLTAGE_BY_INIT_0 (0) ++#define VOLTAGE_BY_INIT_1 (-1) ++ ++#define RATE_CEVA_PLL_0 (500000000) ++#define RATE_CEVA_PLL_1 (600000000) ++#define RATE_CEVA_PLL_TOTAL (2) ++ ++static struct rate_voltage rate_voltage_ceva_pll[RATE_CEVA_PLL_TOTAL] = ++{ ++ {RATE_CEVA_PLL_0, VOLTAGE_BY_INIT_0}, ++ {RATE_CEVA_PLL_1, VOLTAGE_BY_INIT_1}, ++}; ++ ++static struct rate_voltage *rate_voltage_all_table[VCORE_DVFS_DEMANDER_TOTAL] = ++{ ++ rate_voltage_ceva_pll, ++}; ++ ++static int rate_voltage_num_table[VCORE_DVFS_DEMANDER_TOTAL] = ++{ ++ RATE_CEVA_PLL_TOTAL, ++}; ++ ++// ++struct vcore_dvfs_info { ++ unsigned int gpio_total_num; ++ unsigned int *gpio_pins; ++ int *voltages; ++ int *voltages_sort_idxs; ++ unsigned int voltages_total_num; ++ int voltage_current; ++ int voltage_init; ++ int voltage_init_seq; ++ int inited; ++}; ++ ++struct vcore_dvfs { ++ vcore_dvfs_demander_e demander; ++ int active; ++ unsigned long rate; ++ int voltage; ++ struct rate_voltage *rate_vol; ++ int rate_vol_num; ++ struct list_head list; ++}; ++ ++ ++ ++static LIST_HEAD(vcore_dvfs_list); ++ ++static struct vcore_dvfs_info vcore_dvfs_info = ++{ ++ .voltage_init = -1, ++ .voltage_init_seq = -1, ++ .inited = false, ++}; ++ ++ ++static int vcore_dvfs_bubble_sort(int* value, int* idxs, int num); ++static int vcore_dvfs_get_curr_idx(int* idx); ++static int vcore_dvfs_set_curr_voltage_by_idx(int idx); ++static int vcore_dvfs_get_demander_voltage_by_rate(vcore_dvfs_demander_e demander, unsigned long rate); ++static int vcore_dvfs_get_idx_by_voltage(int voltage); ++static int vcore_dvfs_get_voltage_by_idx(int idx); ++static int vcore_dvfs_get_seq_by_idx(int idx); ++/* // mask it, just avoid warning. ++static int vcore_dvfs_get_idx_by_seq(int seq); ++*/ ++static int vcore_dvfs_init(void); ++static int vcore_dvfs_update_voltage(void); ++ ++static int vcore_dvfs_bubble_sort(int* value, int* idxs, int num) ++{ ++ int c, d, swap, swap_idx; ++ ++ for (c = 0; c < (num - 1); c++) ++ { ++ for (d = 0; d < (num - c - 1); d++) ++ { ++ if (value[d] > value[d+1]) // small -> large ++ { ++ // value ++ swap = value[d]; ++ value[d] = value[d+1]; ++ value[d+1] = swap; ++ ++ // idx ++ swap_idx = idxs[d]; ++ idxs[d] = idxs[d+1]; ++ idxs[d+1] = swap_idx; ++ } ++ } ++ } ++ ++ return vcore_dvfs_success; ++} ++ ++static int vcore_dvfs_get_curr_idx(int* idx) ++{ ++ int i = 0, idx_i = 0; ++ int *gpio_values = NULL; ++ ++ gpio_values = kzalloc(sizeof(int) * vcore_dvfs_info.gpio_total_num, GFP_KERNEL); ++ if (!gpio_values) ++ goto fail; ++ ++ for (i = 0; i < vcore_dvfs_info.gpio_total_num; i++) ++ { ++ gpio_values[i] = MDrv_GPIO_Pad_Read(vcore_dvfs_info.gpio_pins[i]); ++ idx_i += (( gpio_values[i] & 1 ) << i ); ++ } ++ ++ if (gpio_values) ++ { ++ kfree(gpio_values); ++ gpio_values = NULL; ++ } ++ ++ if (IF_IDX_VALID(idx_i) != true) ++ { ++ goto fail; ++ } ++ ++ *idx = idx_i; ++ ++ return vcore_dvfs_success; ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_get_curr_idx FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++} ++ ++static int vcore_dvfs_set_curr_voltage_by_idx(int idx) ++{ ++ int i = 0; ++ ++ if (IF_IDX_VALID(idx) != true) ++ { ++ goto fail; ++ } ++ ++ for (i = 0; i < vcore_dvfs_info.gpio_total_num; i++) ++ { ++ if ((idx >> i) & 0x1) ++ { ++ MDrv_GPIO_Set_High(vcore_dvfs_info.gpio_pins[i]); ++ } ++ else ++ { ++ MDrv_GPIO_Set_Low(vcore_dvfs_info.gpio_pins[i]); ++ } ++ } ++ ++ return vcore_dvfs_success; ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_set_curr_voltage_by_idx FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++} ++ ++static int vcore_dvfs_get_demander_voltage_by_rate(vcore_dvfs_demander_e demander, unsigned long rate) ++{ ++ int j = 0; ++ ++ for (j = 0; j < rate_voltage_num_table[demander]; j++) ++ { ++ if (rate_voltage_all_table[demander][j].rate == rate) ++ { ++ return rate_voltage_all_table[demander][j].voltage; ++ } ++ } ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_get_demander_voltage_by_rate FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++} ++ ++static int vcore_dvfs_get_idx_by_voltage(int voltage) ++{ ++ int i = 0, idx = -1; ++ ++ for (i = 0; i < vcore_dvfs_info.voltages_total_num; i++) ++ { ++ if (voltage == vcore_dvfs_info.voltages[i]) ++ { ++ idx = i; ++ break; ++ } ++ } ++ ++ if (IF_IDX_VALID(idx) != true) ++ { ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_get_idx_by_voltage FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++ } ++ ++ return idx; ++} ++ ++static int vcore_dvfs_get_voltage_by_idx(int idx) ++{ ++ if (IF_IDX_VALID(idx) != true) ++ { ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_get_voltage_by_idx FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++ } ++ ++ return vcore_dvfs_info.voltages[idx]; ++} ++ ++static int vcore_dvfs_get_seq_by_idx(int idx) ++{ ++ int i = 0, seq = vcore_dvfs_fail; ++ ++ for (i = 0; i < vcore_dvfs_info.voltages_total_num; i++) ++ { ++ if (idx == vcore_dvfs_info.voltages_sort_idxs[i]) ++ { ++ seq = i; ++ break; ++ } ++ } ++ ++ if (IF_SEQ_VALID(seq) != true) ++ { ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_get_seq_by_idx FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++ } ++ ++ return seq; ++} ++ ++/* // mask it, just avoid warning. ++static int vcore_dvfs_get_idx_by_seq(int seq) ++{ ++ int idx = vcore_dvfs_fail; ++ ++ if (IF_SEQ_VALID(seq) != true) ++ { ++ return vcore_dvfs_fail; ++ } ++ ++ idx = vcore_dvfs_info.voltages_sort_idxs[seq]; ++ ++ if (IF_IDX_VALID(idx) != true) ++ { ++ return vcore_dvfs_fail; ++ } ++ ++ return idx; ++} ++*/ ++ ++static int vcore_dvfs_init(void) ++{ ++ int ret = vcore_dvfs_success; ++ struct device_node *np = NULL; ++ int i = 0, j = 0, curr_idx = 0; ++ int *vol_sort = NULL; ++ ++ if ((np = of_find_node_by_name(NULL, "vcore_info"))) ++ { ++ // get gpio_total_num from DTS ++ ret = of_property_read_u32(np, "gpio_total_num", &vcore_dvfs_info.gpio_total_num); ++ if ( ret || (vcore_dvfs_info.gpio_total_num < 1)) ++ goto fail; ++ ++ // get gpio_pins from DTS ++ vcore_dvfs_info.gpio_pins = kzalloc(sizeof(unsigned int) * vcore_dvfs_info.gpio_total_num, GFP_KERNEL); ++ if (!vcore_dvfs_info.gpio_pins) ++ { ++ ret = -ENOMEM; ++ goto fail; ++ } ++ ++ ret = of_property_read_u32_array(np, "gpio_pins", vcore_dvfs_info.gpio_pins, vcore_dvfs_info.gpio_total_num); ++ if (ret) ++ goto fail; ++ ++ // cal voltages_total_num ++ vcore_dvfs_info.voltages_total_num = (1 << vcore_dvfs_info.gpio_total_num); ++ ++ // get voltages from DTS ++ vcore_dvfs_info.voltages = kzalloc(sizeof(int) * vcore_dvfs_info.voltages_total_num, GFP_KERNEL); ++ if (!vcore_dvfs_info.voltages) ++ { ++ ret = -ENOMEM; ++ goto fail; ++ } ++ ++ ret = of_property_read_u32_array(np, "voltages", vcore_dvfs_info.voltages, vcore_dvfs_info.voltages_total_num); ++ if (ret) ++ goto fail; ++ ++ // voltages_sort, voltages_sort_idxs ++ vol_sort = kzalloc(sizeof(int) * vcore_dvfs_info.voltages_total_num, GFP_KERNEL); ++ if (!vol_sort) ++ { ++ ret = -ENOMEM; ++ goto fail; ++ } ++ ++ vcore_dvfs_info.voltages_sort_idxs = kzalloc(sizeof(int) * vcore_dvfs_info.voltages_total_num, GFP_KERNEL); ++ if (!vcore_dvfs_info.voltages_sort_idxs) ++ { ++ ret = -ENOMEM; ++ goto fail; ++ } ++ ++ for (i = 0; i < vcore_dvfs_info.voltages_total_num; i++) ++ { ++ vol_sort[i] = vcore_dvfs_info.voltages[i]; ++ vcore_dvfs_info.voltages_sort_idxs[i] = i; ++ } ++ ++ // sort ++ vcore_dvfs_bubble_sort(vol_sort, vcore_dvfs_info.voltages_sort_idxs, vcore_dvfs_info.voltages_total_num); ++ kfree(vol_sort); ++ vol_sort = NULL; ++ ++ // get vcore init seq from IPL ++ if (vcore_dvfs_get_curr_idx(&curr_idx) == vcore_dvfs_success) ++ { ++ vcore_dvfs_info.voltage_init = vcore_dvfs_get_voltage_by_idx(curr_idx); ++ vcore_dvfs_info.voltage_init_seq = vcore_dvfs_get_seq_by_idx(curr_idx); ++ vcore_dvfs_info.voltage_current = vcore_dvfs_info.voltage_init; ++ } ++ else ++ { ++ goto fail; ++ } ++ ++ // update table if voltage is decided by init. ++ for (i = 0; i < VCORE_DVFS_DEMANDER_TOTAL; i++) ++ { ++ for (j = 0; j < rate_voltage_num_table[i]; j++) ++ { ++ if (rate_voltage_all_table[i][j].voltage == VOLTAGE_BY_INIT_0) ++ { ++ rate_voltage_all_table[i][j].voltage = vcore_dvfs_info.voltage_init; ++ } ++ else if (rate_voltage_all_table[i][j].voltage == VOLTAGE_BY_INIT_1) ++ { ++ if (IF_SEQ_VALID(vcore_dvfs_info.voltage_init_seq + 1) != true) ++ { ++ goto fail; ++ } ++ ++ rate_voltage_all_table[i][j].voltage = vcore_dvfs_get_voltage_by_idx(vcore_dvfs_info.voltages_sort_idxs[(vcore_dvfs_info.voltage_init_seq + 1)]); ++ } ++ } ++ } ++ ++ // init done ++ vcore_dvfs_info.inited = true; ++ ++ VCORE_DVFS_DBG("[VCORE_DVFS]vcore_dvfs_init SUCCESS\n"); ++ } ++ else ++ { ++ VCORE_DVFS_ERR("[VCORE_DVFS]can't get vcore_info node\n"); ++ goto fail; ++ } ++ ++ return vcore_dvfs_success; ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_init FAIL !\n"); ++ ++ if (vcore_dvfs_info.gpio_pins) ++ { ++ kfree(vcore_dvfs_info.gpio_pins); ++ vcore_dvfs_info.gpio_pins = NULL; ++ } ++ ++ if (vcore_dvfs_info.voltages) ++ { ++ kfree(vcore_dvfs_info.voltages); ++ vcore_dvfs_info.voltages = NULL; ++ } ++ ++ if (vol_sort) ++ { ++ kfree(vol_sort); ++ vol_sort = NULL; ++ } ++ ++ if (vcore_dvfs_info.voltages_sort_idxs) ++ { ++ kfree(vcore_dvfs_info.voltages_sort_idxs); ++ vcore_dvfs_info.voltages_sort_idxs = NULL; ++ } ++ ++ return vcore_dvfs_fail; ++} ++ ++static int vcore_dvfs_update_voltage(void) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ int max_vol = 0, idx = 0; ++ ++ max_vol = vcore_dvfs_info.voltage_init; ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ if (vcore_dvfs_i->active == true) ++ { ++ if (max_vol < vcore_dvfs_i->voltage) ++ { ++ max_vol = vcore_dvfs_i->voltage; ++ } ++ } ++ } ++ ++ idx = vcore_dvfs_get_idx_by_voltage(max_vol); ++ if (IF_IDX_VALID(idx) != true) ++ { ++ goto fail; ++ } ++ ++ if (vcore_dvfs_set_curr_voltage_by_idx(idx)) ++ { ++ goto fail; ++ } ++ ++ vcore_dvfs_info.voltage_current = max_vol; ++ ++ return vcore_dvfs_success; ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_update_voltage FAIL !\n"); ++ ++ return vcore_dvfs_fail; ++} ++ ++int vcore_dvfs_register(vcore_dvfs_demander_e demander, struct vcore_dvfs_init_data *init_data) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ ++ VCORE_DVFS_MUTEX_LOCK(&vcore_dvfs_mutex_lock); ++ ++ if (IF_NOT_ININTED()) ++ { ++ vcore_dvfs_init(); ++ } ++ ++ if (IF_DEMENDER_VALID(demander) != true) ++ { ++ goto fail; ++ } ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ if (vcore_dvfs_i->demander == demander) ++ { ++ goto fail; ++ } ++ } ++ ++ vcore_dvfs_i = NULL; ++ ++ vcore_dvfs_i = kzalloc(sizeof(*vcore_dvfs_i), GFP_KERNEL); ++ if (!vcore_dvfs_i) ++ { ++ goto fail; ++ } ++ ++ vcore_dvfs_i->demander = demander; ++ vcore_dvfs_i->rate_vol = rate_voltage_all_table[demander]; ++ vcore_dvfs_i->rate_vol_num = rate_voltage_num_table[demander]; ++ vcore_dvfs_i->rate = init_data->rate; ++ ++ vcore_dvfs_i->voltage = vcore_dvfs_get_demander_voltage_by_rate(demander, vcore_dvfs_i->rate); ++ if ( vcore_dvfs_i->voltage < 0 ) ++ { ++ goto fail; ++ } ++ ++ vcore_dvfs_i->active = init_data->active; ++ ++ list_add(&vcore_dvfs_i->list, &vcore_dvfs_list); ++ ++ if (vcore_dvfs_i->active == true) ++ { ++ vcore_dvfs_update_voltage(); ++ } ++ ++ VCORE_DVFS_DBG("[VCORE_DVFS]%s SUCCESS, demander = %d\n", __FUNCTION__, (int)demander); ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_success; ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]%s FAIL !\n", __FUNCTION__); ++ ++ if (vcore_dvfs_i) ++ { ++ kfree(vcore_dvfs_i); ++ vcore_dvfs_i = NULL; ++ } ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_fail; ++} ++ ++int vcore_dvfs_unregister(vcore_dvfs_demander_e demander) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ ++ VCORE_DVFS_MUTEX_LOCK(&vcore_dvfs_mutex_lock); ++ ++ if (IF_NOT_ININTED()) ++ { ++ goto fail; ++ } ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ if (vcore_dvfs_i->demander == demander) ++ { ++ list_del(&vcore_dvfs_i->list); ++ kfree(vcore_dvfs_i); ++ vcore_dvfs_i = NULL; ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_success; ++ } ++ } ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]%s FAIL !\n", __FUNCTION__); ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_fail; ++} ++ ++int vcore_dvfs_clk_enable(vcore_dvfs_demander_e demander, clk_enable_hw clk_enable_hw) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ ++ VCORE_DVFS_MUTEX_LOCK(&vcore_dvfs_mutex_lock); ++ ++ if (IF_NOT_ININTED()) ++ { ++ goto fail; ++ } ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ if (vcore_dvfs_i->demander == demander) ++ { ++ vcore_dvfs_i->active = true; ++ if (vcore_dvfs_update_voltage() != vcore_dvfs_success) ++ { ++ goto fail; ++ } ++ ++ if (clk_enable_hw) ++ { ++ if (clk_enable_hw() != vcore_dvfs_success) ++ { ++ goto fail; ++ } ++ } ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_success; ++ } ++ } ++ ++fail: ++ ++ vcore_dvfs_i->active = false; ++ vcore_dvfs_update_voltage(); // ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]%s FAIL !\n", __FUNCTION__); ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_fail; ++} ++ ++int vcore_dvfs_clk_disable(vcore_dvfs_demander_e demander, clk_disable_hw clk_disable_hw) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ ++ VCORE_DVFS_MUTEX_LOCK(&vcore_dvfs_mutex_lock); ++ ++ if (IF_NOT_ININTED()) ++ { ++ goto fail; ++ } ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ if (vcore_dvfs_i->demander == demander) ++ { ++ vcore_dvfs_i->active = false; ++ if (vcore_dvfs_update_voltage() != vcore_dvfs_success) ++ { ++ goto fail; ++ } ++ ++ if (clk_disable_hw) ++ { ++ clk_disable_hw(); ++ } ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_success; ++ } ++ } ++ ++fail: ++ ++/* ++ vcore_dvfs_i->active = true; ++ if (vcore_dvfs_update_voltage() != vcore_dvfs_success) ++ { ++ // Fatal Error ++ } ++*/ ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]%s FAIL !\n", __FUNCTION__); ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_fail; ++} ++ ++int vcore_dvfs_clk_set_rate(vcore_dvfs_demander_e demander, unsigned long rate, set_rate_hw set_rate_hw) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ unsigned long old_rate; ++ ++ ++ VCORE_DVFS_MUTEX_LOCK(&vcore_dvfs_mutex_lock); ++ ++ if (IF_NOT_ININTED()) ++ { ++ goto fail; ++ } ++ ++ VCORE_DVFS_DBG("[VCORE_DVFS]%s !\n",__FUNCTION__); ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ if (vcore_dvfs_i->demander == demander) ++ { ++ old_rate = vcore_dvfs_i->rate; ++ ++ vcore_dvfs_i->rate = rate; ++ vcore_dvfs_i->voltage = vcore_dvfs_get_demander_voltage_by_rate(demander, vcore_dvfs_i->rate); ++ if ( vcore_dvfs_i->voltage < 0 ) ++ { ++ goto fail; ++ } ++ ++ if (vcore_dvfs_i->active == true) ++ { ++ if (rate < old_rate) ++ { ++ set_rate_hw(rate); ++ ++ if (vcore_dvfs_update_voltage() != vcore_dvfs_success) ++ { ++ goto fail; ++ } ++ } ++ else if (rate > old_rate) ++ { ++ if (vcore_dvfs_update_voltage() != vcore_dvfs_success) ++ { ++ goto fail; ++ } ++ ++ set_rate_hw(rate); ++ } ++ else if (rate == old_rate) ++ { ++ set_rate_hw(rate); ++ } ++ } ++ else ++ { ++ set_rate_hw(rate); ++ } ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_success; ++ } ++ } ++ ++fail: ++ ++ VCORE_DVFS_ERR("[VCORE_DVFS]%s FAIL !\n",__FUNCTION__); ++ ++ VCORE_DVFS_MUTEX_UNLOCK(&vcore_dvfs_mutex_lock); ++ return vcore_dvfs_fail; ++} ++ ++EXPORT_SYMBOL(vcore_dvfs_register); ++EXPORT_SYMBOL(vcore_dvfs_unregister); ++EXPORT_SYMBOL(vcore_dvfs_clk_enable); ++EXPORT_SYMBOL(vcore_dvfs_clk_disable); ++EXPORT_SYMBOL(vcore_dvfs_clk_set_rate); ++ ++ ++ ++static int vcore_dvfs_open(struct inode *inode, struct file *file); ++static long vcore_dvfs_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++static const struct file_operations vcore_dvfs_fops = ++{ ++ .open = vcore_dvfs_open, ++ .unlocked_ioctl = vcore_dvfs_ioctl, ++}; ++ ++static long vcore_dvfs_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int s32Err= 0; ++ ++ /* ++ * extract the type and number bitfields, and don't decode ++ * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ */ ++ if ((VCORE_DVFS_IOC_MAGIC!= _IOC_TYPE(cmd)) || (_IOC_NR(cmd)> VCORE_DVFS_IOC_MAXNR)) ++ { ++ return -ENOTTY; ++ } ++ ++ /* ++ * the direction is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. `Type' is user-oriented, while ++ * access_ok is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ { ++ s32Err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ { ++ s32Err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ if (s32Err) ++ { ++ return -EFAULT; ++ } ++ ++ switch(cmd) ++ { ++ case VCORE_DVFS_INIT: ++ break; ++ ++ case VCORE_DVFS_OP: ++ break; ++ ++ default: ++ printk("ioctl: unknown command\n"); ++ return -ENOTTY; ++ } ++ ++ return 0; ++} ++ ++static int vcore_dvfs_open(struct inode *inode, struct file *file) ++{ ++ int ret=0; ++ if (ret) ++ { ++ VCORE_DVFS_ERR("[VCORE_DVFS]vcore_dvfs_open FAIL !\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int vcore_dvfs_probe(struct platform_device *pdev) ++{ ++ VCORE_DVFS_DBG("[VCORE_DVFS]vcore_dvfs_probe \n"); ++ ++ return 0; ++} ++ ++static int vcore_dvfs_remove(struct platform_device *pdev) ++{ ++ struct vcore_dvfs *vcore_dvfs_i; ++ ++ VCORE_DVFS_DBG("[VCORE_DVFS]vcore_dvfs_remove \n"); ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ list_del(&vcore_dvfs_i->list); ++ kfree(vcore_dvfs_i); ++ } ++ ++ if (vcore_dvfs_info.gpio_pins) ++ { ++ kfree(vcore_dvfs_info.gpio_pins); ++ vcore_dvfs_info.gpio_pins = NULL; ++ } ++ ++ if (vcore_dvfs_info.voltages) ++ { ++ kfree(vcore_dvfs_info.voltages); ++ vcore_dvfs_info.voltages = NULL; ++ } ++ ++ if (vcore_dvfs_info.voltages_sort_idxs) ++ { ++ kfree(vcore_dvfs_info.voltages_sort_idxs); ++ vcore_dvfs_info.voltages_sort_idxs = NULL; ++ } ++ ++ vcore_dvfs_info.inited = false; ++ ++/* ++ Set to init voltage first here !? ++ vcore_dvfs_update_voltage(); ++*/ ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int vcore_dvfs_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ VCORE_DVFS_DBG("[VCORE_DVFS]vcore_dvfs_suspend \n"); ++ return 0; ++} ++ ++static int vcore_dvfs_resume(struct platform_device *dev) ++{ ++ VCORE_DVFS_DBG("[VCORE_DVFS]vcore_dvfs_resume \n"); ++ return 0; ++} ++#else ++#define vcore_dvfs_suspend NULL ++#define vcore_dvfs_resume NULL ++#endif /* CONFIG_PM */ ++ ++static const struct of_device_id vcore_dvfs_of_match_table[] = ++{ ++ { .compatible = "sstar,vcore_dvfs" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, vcore_dvfs_of_match_table); ++ ++static struct platform_driver vcore_dvfs_driver = ++{ ++ .probe = vcore_dvfs_probe, ++ .remove = vcore_dvfs_remove, ++#ifdef CONFIG_PM ++ .suspend = vcore_dvfs_suspend, ++ .resume = vcore_dvfs_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "vcore_dvfs", ++ .of_match_table = vcore_dvfs_of_match_table, ++ }, ++}; ++ ++ ++ ++#if 0 // Only for debug ++static ssize_t dbg_debug_register_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ static int val = 0; ++ ++ val++; ++ if (val % 2) ++ { ++ vcore_dvfs_clk_enable(VCORE_DVFS_DEMANDER_TEST, NULL); ++ } ++ else ++ { ++ vcore_dvfs_clk_disable(VCORE_DVFS_DEMANDER_TEST, NULL); ++ } ++ ++ return sprintf(buf, "%d\n", val); ++} ++ ++ ++static ssize_t dbg_debug_register_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ struct vcore_dvfs_init_data init_data; ++ ++ if (NULL != buf) ++ { ++ printk("VCORE_DVFS_DEBUG: %s\r\n",__FUNCTION__); ++ init_data.rate = 333; ++ init_data.active = false; // true; ++ vcore_dvfs_register(VCORE_DVFS_DEMANDER_TEST, &init_data); ++ } ++ ++ return count; ++} ++ ++static ssize_t dbg_debug_set_rate_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return 0; ++} ++ ++static ssize_t dbg_debug_set_rate_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ struct clk *clk; ++ unsigned long rate = 0; ++ int ret; ++ struct device_node *np = NULL; ++ ++ if (NULL != buf) ++ { ++ np = of_find_node_by_name(NULL, "xm6"); ++ ++ if (np == NULL) ++ { ++ printk("VCORE_DVFS_DEBUG: np == NULL\r\n"); ++ return -1; ++ } ++ ++ clk = of_clk_get(np, 0); ++ ++ if (clk == NULL) ++ { ++ printk("VCORE_DVFS_DEBUG: clk == NULL\r\n"); ++ return -1; ++ } ++ ++ if (buf[0] == '5') ++ { ++ rate = 500000000; ++ } ++ else ++ { ++ rate = 600000000; ++ } ++ //rate = atol(buf); ++ ++ printk("VCORE_DVFS_DEBUG: rate = %lu\r\n",rate); ++ ++ ret = clk_set_rate(clk, rate); ++ } ++ ++ return count; ++} ++#endif ++ ++static ssize_t dbg_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ int i = 0; ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "---VCORE DVFS INFO---\r\n"); ++ str += scnprintf(str, end - str, "gpio_total_num = %d\r\n",vcore_dvfs_info.gpio_total_num); ++ for (i = 0; i < vcore_dvfs_info.gpio_total_num; i++) ++ { ++ str += scnprintf(str, end - str, "gpio_pins[%d] = %d\r\n",i, vcore_dvfs_info.gpio_pins[i]); ++ } ++ ++ str += scnprintf(str, end - str, "voltages_total_num = %d\r\n",vcore_dvfs_info.voltages_total_num); ++ ++ for (i = 0; i < vcore_dvfs_info.voltages_total_num; i++) ++ { ++ str += scnprintf(str, end - str, "voltages[%d] = %d\r\n",i, vcore_dvfs_info.voltages[i]); ++ } ++ ++ for (i = 0; i < vcore_dvfs_info.voltages_total_num; i++) ++ { ++ str += scnprintf(str, end - str, "voltages_sort_idxs[%d] = %d\r\n",i, vcore_dvfs_info.voltages_sort_idxs[i]); ++ } ++ ++ str += scnprintf(str, end - str, "voltage_current = %d\r\n",vcore_dvfs_info.voltage_current); ++ str += scnprintf(str, end - str, "voltage_init = %d\r\n",vcore_dvfs_info.voltage_init); ++ str += scnprintf(str, end - str, "voltage_init_seq = %d\r\n",vcore_dvfs_info.voltage_init_seq); ++ ++ return (str - buf); ++} ++ ++static ssize_t dbg_demander_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct vcore_dvfs *vcore_dvfs_i; ++ ++ str += scnprintf(str, end - str, "---VCORE DVFS DEMANDER INFO---\r\n"); ++ ++ list_for_each_entry(vcore_dvfs_i, &vcore_dvfs_list, list) ++ { ++ str += scnprintf(str, end - str, "------\r\n"); ++ str += scnprintf(str, end - str, "demander = %d\r\n",vcore_dvfs_i->demander); ++ str += scnprintf(str, end - str, "active = %d\r\n",vcore_dvfs_i->active); ++ str += scnprintf(str, end - str, "rate = %lu\r\n",vcore_dvfs_i->rate); ++ str += scnprintf(str, end - str, "voltage = %d\r\n",vcore_dvfs_i->voltage); ++ str += scnprintf(str, end - str, "rate_vol_num = %d\r\n",vcore_dvfs_i->rate_vol_num); ++ } ++ ++ return (str - buf); ++} ++ ++static ssize_t dbg_rate_vol_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i = 0, j = 0; ++ ++ str += scnprintf(str, end - str, "---VCORE DVFS RATE VOL INFO---\r\n"); ++ ++ for (i = 0; i < VCORE_DVFS_DEMANDER_TOTAL; i++) ++ { ++ str += scnprintf(str, end - str, "Demander %d:\r\n", i); ++ ++ for (j = 0; j < rate_voltage_num_table[i]; j++) ++ { ++ str += scnprintf(str, end - str, "[%d]rate = %lu\t vol=%d\r\n", j, rate_voltage_all_table[i][j].rate, rate_voltage_all_table[i][j].voltage); ++ } ++ } ++ ++ return (str - buf); ++} ++ ++static ssize_t dbg_gpio_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ int i = 0; ++ int idx_i = 0; ++ int *gpio_values = NULL; ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "---VCORE DVFS GPIO INFO---\r\n"); ++ ++ gpio_values = kzalloc(sizeof(int) * vcore_dvfs_info.gpio_total_num, GFP_KERNEL); ++ if (!gpio_values) ++ goto fail; ++ ++ for (i = 0; i < vcore_dvfs_info.gpio_total_num; i++) ++ { ++ gpio_values[i] = MDrv_GPIO_Pad_Read(vcore_dvfs_info.gpio_pins[i]); ++ idx_i += (( gpio_values[i] & 1 ) << i ); ++ } ++ ++ str += scnprintf(str, end - str, "IDX = %d\r\n", idx_i); ++ str += scnprintf(str, end - str, "( "); ++ for (i = 0; i < vcore_dvfs_info.gpio_total_num; i++) ++ { ++ str += scnprintf(str, end - str, "%d ", gpio_values[(vcore_dvfs_info.gpio_total_num - i - 1)]); ++ } ++ str += scnprintf(str, end - str, ")\r\n"); ++ str += scnprintf(str, end - str, "voltage = %d\r\n", vcore_dvfs_get_voltage_by_idx(idx_i)); ++ ++ if (gpio_values) ++ { ++ kfree(gpio_values); ++ gpio_values = NULL; ++ } ++ ++fail: ++ ++ if (gpio_values) ++ { ++ kfree(gpio_values); ++ gpio_values = NULL; ++ } ++ ++ return (str - buf); ++} ++ ++static ssize_t dbg_gpio_info_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ if (NULL != buf) ++ { ++/* ++ if (buf[0] == '5') ++ { ++ } ++ else ++ { ++ } ++*/ ++ return count; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(vcore_dvfs_info, 0444, dbg_info_show, NULL); ++static DEVICE_ATTR(vcore_dvfs_demander_info, 0444, dbg_demander_info_show, NULL); ++static DEVICE_ATTR(vcore_dvfs_rate_vol_info, 0444, dbg_rate_vol_info_show, NULL); ++static DEVICE_ATTR(vcore_dvfs_gpio_info, 0644, dbg_gpio_info_show, dbg_gpio_info_store); ++ ++static struct miscdevice vcore_dvfs_miscdev = {MISC_DYNAMIC_MINOR, "vcore_dvfs", &vcore_dvfs_fops}; ++ ++#if 0 ++module_platform_driver(vcore_dvfs_driver); ++#else ++static int __init vcore_dvfs_driver_init(void) ++{ ++ struct device *dev; ++ ++ misc_register(&vcore_dvfs_miscdev); ++ ++ dev = vcore_dvfs_miscdev.this_device; ++ ++ device_create_file(dev, &dev_attr_vcore_dvfs_info); ++ device_create_file(dev, &dev_attr_vcore_dvfs_demander_info); ++ device_create_file(dev, &dev_attr_vcore_dvfs_rate_vol_info); ++ device_create_file(dev, &dev_attr_vcore_dvfs_gpio_info); ++ ++ return platform_driver_register(&vcore_dvfs_driver); ++} ++ ++//module_init(vcore_dvfs_driver_init); ++subsys_initcall(vcore_dvfs_driver_init); ++ ++static void __exit vcore_dvfs_driver_exit(void) ++{ ++ misc_deregister(&vcore_dvfs_miscdev); ++ ++ return platform_driver_unregister(&vcore_dvfs_driver); ++} ++module_exit(vcore_dvfs_driver_exit); ++#endif ++ ++MODULE_AUTHOR("SStar Semiconductor, Inc."); ++MODULE_DESCRIPTION("infinity Vcore Dvfs Device Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:vcore_dvfs"); +diff --git a/drivers/sstar/voltage/Kconfig b/drivers/sstar/voltage/Kconfig +new file mode 100755 +index 000000000000..b0219afb0aec +--- /dev/null ++++ b/drivers/sstar/voltage/Kconfig +@@ -0,0 +1,11 @@ ++config SS_VOLTAGE_CTRL ++ tristate "SStar Voltage Control" ++ depends on MS_GPIO && !ARCH_INFINITY2 ++ default y ++ help ++ ++config SS_VOLTAGE_CTRL_WITH_OSC ++ tristate "SStar Voltage Control With OSC" ++ depends on ARCH_INFINITY6E && SS_VOLTAGE_CTRL ++ default y ++ help +diff --git a/drivers/sstar/voltage/Makefile b/drivers/sstar/voltage/Makefile +new file mode 100755 +index 000000000000..3c31cb8e6c5d +--- /dev/null ++++ b/drivers/sstar/voltage/Makefile +@@ -0,0 +1,6 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage_ctrl.o ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += $(CONFIG_SSTAR_CHIP_NAME)/ +\ No newline at end of file +diff --git a/drivers/sstar/voltage/infinity2m/Makefile b/drivers/sstar/voltage/infinity2m/Makefile +new file mode 100755 +index 000000000000..b4d68f131c63 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity2m/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage_request_init.o +diff --git a/drivers/sstar/voltage/infinity2m/voltage_request_init.c b/drivers/sstar/voltage/infinity2m/voltage_request_init.c +new file mode 100755 +index 000000000000..232c71947074 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity2m/voltage_request_init.c +@@ -0,0 +1,27 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "registers.h" ++#include "ms_platform.h" ++#include "voltage_ctrl.h" ++#include "voltage_ctrl_demander.h" ++ ++int voltage_request_chip(void) ++{ ++ return 0; ++} +diff --git a/drivers/sstar/voltage/infinity5/Makefile b/drivers/sstar/voltage/infinity5/Makefile +new file mode 100755 +index 000000000000..b4d68f131c63 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity5/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage_request_init.o +diff --git a/drivers/sstar/voltage/infinity5/voltage_request_init.c b/drivers/sstar/voltage/infinity5/voltage_request_init.c +new file mode 100755 +index 000000000000..eb4c82e276a5 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity5/voltage_request_init.c +@@ -0,0 +1,26 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "registers.h" ++#include "ms_platform.h" ++#include "voltage_ctrl.h" ++ ++int voltage_request_chip(void) ++{ ++ return 0; ++} +diff --git a/drivers/sstar/voltage/infinity6/Makefile b/drivers/sstar/voltage/infinity6/Makefile +new file mode 100755 +index 000000000000..b4d68f131c63 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity6/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage_request_init.o +diff --git a/drivers/sstar/voltage/infinity6/voltage_request_init.c b/drivers/sstar/voltage/infinity6/voltage_request_init.c +new file mode 100755 +index 000000000000..68a190f8ee80 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity6/voltage_request_init.c +@@ -0,0 +1,45 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "registers.h" ++#include "ms_platform.h" ++#include "voltage_ctrl.h" ++#include "voltage_ctrl_demander.h" ++ ++void voltage_request_miu(void) ++{ ++ unsigned int miupll_freq_Mhz = 0; ++ unsigned int miu_data_rate = 0; ++ ++ // Check MIUPLL and determine core voltage request ++ miupll_freq_Mhz = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ miu_data_rate = 1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8); ++ if (miupll_freq_Mhz > 480 || (miu_data_rate <=4 && miupll_freq_Mhz > 240)) ++ set_core_voltage(VOLTAGE_DEMANDER_MIU, VOLTAGE_CORE_1000); ++ else ++ set_core_voltage(VOLTAGE_DEMANDER_MIU, VOLTAGE_CORE_900); ++ ++ return; ++} ++ ++int voltage_request_chip(void) ++{ ++ voltage_request_miu(); ++ ++ return 0; ++} +diff --git a/drivers/sstar/voltage/infinity6b0/Makefile b/drivers/sstar/voltage/infinity6b0/Makefile +new file mode 100755 +index 000000000000..b4d68f131c63 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity6b0/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage_request_init.o +diff --git a/drivers/sstar/voltage/infinity6b0/voltage_request_init.c b/drivers/sstar/voltage/infinity6b0/voltage_request_init.c +new file mode 100755 +index 000000000000..68a190f8ee80 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity6b0/voltage_request_init.c +@@ -0,0 +1,45 @@ ++/* ++* ms_complex_clk.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include "registers.h" ++#include "ms_platform.h" ++#include "voltage_ctrl.h" ++#include "voltage_ctrl_demander.h" ++ ++void voltage_request_miu(void) ++{ ++ unsigned int miupll_freq_Mhz = 0; ++ unsigned int miu_data_rate = 0; ++ ++ // Check MIUPLL and determine core voltage request ++ miupll_freq_Mhz = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ miu_data_rate = 1 << (INREGMSK16(BASE_REG_MIU_PA + REG_ID_01, 0x0300) >> 8); ++ if (miupll_freq_Mhz > 480 || (miu_data_rate <=4 && miupll_freq_Mhz > 240)) ++ set_core_voltage(VOLTAGE_DEMANDER_MIU, VOLTAGE_CORE_1000); ++ else ++ set_core_voltage(VOLTAGE_DEMANDER_MIU, VOLTAGE_CORE_900); ++ ++ return; ++} ++ ++int voltage_request_chip(void) ++{ ++ voltage_request_miu(); ++ ++ return 0; ++} +diff --git a/drivers/sstar/voltage/infinity6e/Makefile b/drivers/sstar/voltage/infinity6e/Makefile +new file mode 100755 +index 000000000000..b4d68f131c63 +--- /dev/null ++++ b/drivers/sstar/voltage/infinity6e/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/include/$(CONFIG_SSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_SS_VOLTAGE_CTRL) += voltage_request_init.o +diff --git a/drivers/sstar/voltage/infinity6e/voltage_request_init.c b/drivers/sstar/voltage/infinity6e/voltage_request_init.c +new file mode 100755 +index 000000000000..6714f126928b +--- /dev/null ++++ b/drivers/sstar/voltage/infinity6e/voltage_request_init.c +@@ -0,0 +1,44 @@ ++/* ++* voltage_request_init.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include ++#include "registers.h" ++#include "ms_platform.h" ++#include "voltage_ctrl.h" ++#include "voltage_ctrl_demander.h" ++ ++void voltage_request_miu(void) ++{ ++ unsigned int miupll_freq_Mhz = 0; ++ ++ // Check MIUPLL and determine core voltage request ++ miupll_freq_Mhz = 24 * INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x00FF) / ((INREGMSK16(BASE_REG_MIUPLL_PA + REG_ID_03, 0x0700) >> 8) + 2); ++ ++ if (miupll_freq_Mhz > 400) ++ set_core_voltage(VOLTAGE_DEMANDER_MIU, VOLTAGE_CORE_1000); ++ else ++ set_core_voltage(VOLTAGE_DEMANDER_MIU, VOLTAGE_CORE_900); ++ ++ return; ++} ++ ++int voltage_request_chip(void) ++{ ++ voltage_request_miu(); ++ ++ return 0; ++} ++ +diff --git a/drivers/sstar/voltage/voltage_ctrl.c b/drivers/sstar/voltage/voltage_ctrl.c +new file mode 100755 +index 000000000000..53487e2a7bc0 +--- /dev/null ++++ b/drivers/sstar/voltage/voltage_ctrl.c +@@ -0,0 +1,596 @@ ++/* ++* voltage_ctrl.c- Sigmastar ++* ++* Copyright (c) [2019~2020] SigmaStar Technology. ++* ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License version 2 for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "registers.h" ++#include "ms_platform.h" ++#include "voltage_ctrl.h" ++#include "voltage_ctrl_demander.h" ++#include "voltage_request_init.h" ++ ++struct device dev_core; ++ ++static struct bus_type voltage_subsys = { ++ .name = "voltage", ++ .dev_name = "voltage", ++}; ++ ++u8 enable_scaling_voltage = 0; ++ ++#define VOLCTRL_DEBUG 0 ++ ++#if VOLCTRL_DEBUG ++#define VOLCTRL_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define VOLCTRL_DBG(fmt, arg...) ++#endif ++#define VOLCTRL_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++unsigned int gpio_vid_width = 0; ++unsigned int *gpio_vid_pins = NULL; ++unsigned int *gpio_vid_voltages = NULL; ++ ++int _gCurrentVoltageCore = 0; ++ ++int _gVoltageDemanderRequestValue[VOLTAGE_DEMANDER_MAX] = {0}; ++const char *_gVoltageDemanderName[] = { ++ FOREACH_DEMANDER(GENERATE_STRING) ++}; ++#ifdef CONFIG_SS_VOLTAGE_CTRL_WITH_OSC ++struct voltage_range { ++ int TT; ++ int LV; ++}; ++static struct voltage_range _gVoltageDemanderRange[VOLTAGE_DEMANDER_MAX] = {{0}}; ++#endif ++int gVoltageCoreGpioInited = 0; ++DEFINE_MUTEX(core_voltage_mutex); ++ ++static int check_voltage_valid(int mV) ++{ ++ int voltage_lv_cnt = 0; ++ int vcore_total_lv = 1 << gpio_vid_width; ++ ++ // Check core voltage setting(mV) valid or not. ++ for (voltage_lv_cnt = 0; voltage_lv_cnt < vcore_total_lv; voltage_lv_cnt++) ++ { ++ if (mV == gpio_vid_voltages[voltage_lv_cnt]) ++ { ++ break; ++ } ++ } ++ ++ if (voltage_lv_cnt == vcore_total_lv) // If core voltage setting(mV) is invalid, Try to find ceiling setting. ++ { ++ for (voltage_lv_cnt = 0; voltage_lv_cnt < vcore_total_lv; voltage_lv_cnt++) ++ { ++ if (mV < gpio_vid_voltages[voltage_lv_cnt]) ++ { ++ VOLCTRL_ERR("[Core Voltage] %s: Not support %dmV, use %dmV\n", ++ __FUNCTION__, mV, gpio_vid_voltages[voltage_lv_cnt]); ++ mV = gpio_vid_voltages[voltage_lv_cnt]; ++ break; ++ } ++ } ++ ++ if (voltage_lv_cnt == vcore_total_lv) // If no ceiling setting, use highest setting. ++ { ++ voltage_lv_cnt--; ++ VOLCTRL_ERR("[Core Voltage] %s: Not support %dmV, use %dmV\n", ++ __FUNCTION__, mV, gpio_vid_voltages[voltage_lv_cnt]); ++ mV = gpio_vid_voltages[voltage_lv_cnt]; ++ } ++ } ++ ++ return mV; ++} ++ ++static void sync_core_voltage(void) ++{ ++ int voltage_lv_cnt = 0; ++ int gpio_lv_cnt = 0; ++ int i = 0; ++ int vcore_max = 0; ++ int vcore_total_lv = 1 << gpio_vid_width; ++ ++ mutex_lock(&core_voltage_mutex); ++ ++ if(gVoltageCoreGpioInited && gpio_vid_width && enable_scaling_voltage) ++ { ++ for (i=0; i 0) ++ { ++ for (voltage_lv_cnt = 0; voltage_lv_cnt < vcore_total_lv; voltage_lv_cnt++) ++ { ++ if (vcore_max == gpio_vid_voltages[voltage_lv_cnt]) ++ { ++ for (gpio_lv_cnt=0; gpio_lv_cnt> gpio_lv_cnt) & 0x1) ++ { ++ gpio_direction_output(gpio_vid_pins[gpio_lv_cnt], 1); ++ VOLCTRL_DBG("[Core Voltage] %s: gpio%d set high\n", __FUNCTION__, gpio_vid_pins[gpio_lv_cnt]); ++ } ++ else ++ { ++ gpio_direction_output(gpio_vid_pins[gpio_lv_cnt], 0); ++ VOLCTRL_DBG("[Core Voltage] %s: gpio%d set low\n", __FUNCTION__, gpio_vid_pins[gpio_lv_cnt]); ++ } ++ } ++ ++ _gCurrentVoltageCore = gpio_vid_voltages[voltage_lv_cnt]; ++ break; ++ } ++ } ++ } ++ } ++ else ++ { ++ VOLCTRL_DBG("[Core Voltage] %s: voltage scaling not enable\n", __FUNCTION__); ++ } ++ ++ VOLCTRL_DBG("[Core Voltage] %s: current core voltage %dmV\n", __FUNCTION__, _gCurrentVoltageCore); ++ ++ mutex_unlock(&core_voltage_mutex); ++} ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL_WITH_OSC ++void voltage_level_reconfig (VOLTAGE_DEMANDER_E demander, int voltage) ++{ ++ ++ if (demander == VOLTAGE_DEMANDER_TEMPERATURE) ++ return; ++ ++ _gVoltageDemanderRange[demander].TT = voltage; ++ ++ if (demander == VOLTAGE_DEMANDER_USER || (gpio_vid_width == 1)) ++ { ++ _gVoltageDemanderRange[demander].LV = voltage; ++ } ++ else ++ { ++ if (voltage == VOLTAGE_CORE_1000) { ++ _gVoltageDemanderRange[demander].LV = VOLTAGE_CORE_950; ++ } ++ else { ++ _gVoltageDemanderRange[demander].LV = VOLTAGE_CORE_900; ++ } ++ } ++} ++ ++int sync_core_voltage_with_OSC_and_TEMP( int useTT) ++{ ++ int i; ++ int update = 0; ++ ++ mutex_lock(&core_voltage_mutex); ++ ++ for (i=0; i= VOLTAGE_DEMANDER_MAX) ++ { ++ VOLCTRL_ERR("[Core Voltage] %s: demander number out of range (%d)\n", __FUNCTION__, demander); ++ return; ++ } ++ ++ mutex_lock(&core_voltage_mutex); ++ ++#ifdef CONFIG_SS_VOLTAGE_CTRL_WITH_OSC ++ voltage_level_reconfig(demander, mV); ++#endif ++ _gVoltageDemanderRequestValue[demander] = mV; ++ VOLCTRL_DBG("[Core Voltage] %s: %s request %dmV\n", __FUNCTION__, _gVoltageDemanderName[demander], mV); ++ ++ if(gVoltageCoreGpioInited && gpio_vid_width && enable_scaling_voltage) ++ { ++ for (i=0; i 0) ++ { ++ for (voltage_lv_cnt = 0; voltage_lv_cnt < vcore_total_lv; voltage_lv_cnt++) ++ { ++ if (vcore_max == gpio_vid_voltages[voltage_lv_cnt]) ++ { ++ for (gpio_lv_cnt=0; gpio_lv_cnt> gpio_lv_cnt) & 0x1) ++ { ++ gpio_direction_output(gpio_vid_pins[gpio_lv_cnt], 1); ++ VOLCTRL_DBG("[Core Voltage] %s: gpio%d set high\n", __FUNCTION__, gpio_vid_pins[gpio_lv_cnt]); ++ } ++ else ++ { ++ gpio_direction_output(gpio_vid_pins[gpio_lv_cnt], 0); ++ VOLCTRL_DBG("[Core Voltage] %s: gpio%d set low\n", __FUNCTION__, gpio_vid_pins[gpio_lv_cnt]); ++ } ++ } ++ ++ _gCurrentVoltageCore = gpio_vid_voltages[voltage_lv_cnt]; ++ break; ++ } ++ } ++ } ++ } ++ else ++ { ++ VOLCTRL_DBG("[Core Voltage] %s: voltage scaling not enable\n", __FUNCTION__); ++ } ++ ++ VOLCTRL_DBG("[Core Voltage] %s: current core voltage %dmV\n", __FUNCTION__, _gCurrentVoltageCore); ++ ++ mutex_unlock(&core_voltage_mutex); ++} ++EXPORT_SYMBOL(set_core_voltage); ++ ++int get_core_voltage(void) ++{ ++ return _gCurrentVoltageCore; ++} ++EXPORT_SYMBOL(get_core_voltage); ++ ++static int core_voltage_get_gpio(void) ++{ ++ struct device_node *np = NULL; ++ unsigned int i; ++ char name[10]; ++ int ret; ++ ++ mutex_lock(&core_voltage_mutex); ++ ++ if((np=of_find_node_by_name(NULL, "core_voltage"))) ++ { ++ if (0 != of_property_read_u32(np, "vid_width", &gpio_vid_width) || gpio_vid_width < 1) ++ goto core_voltage_get_gpio_err; ++ ++ gpio_vid_pins = vzalloc(sizeof(unsigned int) * gpio_vid_width); ++ if (!gpio_vid_pins) ++ goto core_voltage_get_gpio_err; ++ ++ gpio_vid_voltages = vzalloc(sizeof(unsigned int) * (1 << gpio_vid_width)); ++ if (!gpio_vid_voltages) ++ goto core_voltage_get_gpio_err; ++ ++ if (gpio_vid_width != of_property_read_variable_u32_array(np, "vid_gpios", gpio_vid_pins, 0, gpio_vid_width)) ++ goto core_voltage_get_gpio_err; ++ if ((1 << gpio_vid_width) != of_property_read_variable_u32_array(np, "vid_voltages", gpio_vid_voltages, 0, (1 << gpio_vid_width))) ++ goto core_voltage_get_gpio_err; ++ for(i = 0; i < gpio_vid_width; i++) ++ { ++ sprintf(name, "vid%d", i); ++ ret = gpio_request(gpio_vid_pins[i], (const char *)name); ++ if (ret) ++ goto core_voltage_get_gpio_err; ++ gpio_export(gpio_vid_pins[i], 0); ++ } ++ } ++ else ++ { ++ VOLCTRL_ERR("[Core Voltage] %s: can't get core_voltage node\n", __FUNCTION__); ++ } ++ ++ gVoltageCoreGpioInited = 1; ++ ++ mutex_unlock(&core_voltage_mutex); ++ return 0; ++ ++core_voltage_get_gpio_err: ++ gpio_vid_width = 0; ++ if (gpio_vid_pins) ++ { ++ vfree(gpio_vid_pins); ++ gpio_vid_pins = NULL; ++ } ++ if (gpio_vid_voltages) ++ { ++ vfree(gpio_vid_voltages); ++ gpio_vid_voltages = NULL; ++ } ++ ++ mutex_unlock(&core_voltage_mutex); ++ return -1; ++} ++ ++int core_voltage_available(unsigned int **voltages, unsigned int *num) ++{ ++ if (voltages && num) ++ { ++ *num = 1 << gpio_vid_width; ++ *voltages = gpio_vid_voltages; ++ return 0; ++ } ++ else ++ { ++ return -1; ++ } ++} ++EXPORT_SYMBOL(core_voltage_available); ++ ++int core_voltage_pin(unsigned int **pins, unsigned int *num) ++{ ++ if (pins && num) ++ { ++ *num = gpio_vid_width; ++ *pins = gpio_vid_pins; ++ return 0; ++ } ++ else ++ { ++ return -1; ++ } ++} ++EXPORT_SYMBOL(core_voltage_pin); ++ ++static ssize_t show_scaling_voltage(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ mutex_lock(&core_voltage_mutex); ++ str += scnprintf(str, end - str, "%d\n", enable_scaling_voltage); ++ mutex_unlock(&core_voltage_mutex); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_scaling_voltage(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ mutex_lock(&core_voltage_mutex); ++ if(enable) ++ { ++ enable_scaling_voltage=1; ++ VOLCTRL_DBG("[Core Voltage] %s: scaling ON\n", __FUNCTION__); ++ } ++ else ++ { ++ enable_scaling_voltage=0; ++ VOLCTRL_DBG("[Core Voltage] %s: scaling OFF\n", __FUNCTION__); ++ } ++ mutex_unlock(&core_voltage_mutex); ++ sync_core_voltage(); ++ ++ return count; ++} ++DEVICE_ATTR(scaling_voltage, 0644, show_scaling_voltage, store_scaling_voltage); ++ ++static ssize_t show_voltage_available(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned int gpio_bitmap = 0; ++ unsigned int *pins = NULL; ++ unsigned int pin_num = 0; ++ unsigned int *voltages = NULL; ++ unsigned int voltage_num = 0; ++ u8 i,j; ++ ++ str += scnprintf(str, end - str, "\tVcore(mV)"); ++ ++ if(core_voltage_pin(&pins, &pin_num) == 0) ++ { ++ for (i = 0; i < pin_num; i++) ++ { ++ str += scnprintf(str, end - str, "\tvid_%d(%d)", i, pins[i]); ++ } ++ } ++ else ++ { ++ goto out; ++ } ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ if (pin_num) ++ { ++ if(core_voltage_available(&voltages, &voltage_num) == 0) ++ { ++ for (j = 0; j < voltage_num; j++, gpio_bitmap++) ++ { ++ str += scnprintf(str, end - str, "[%d]\t%u", j, voltages[j]); ++ ++ for(i=0;i ++ ++#ifndef _DEV_DEBUG_H_ ++#define _DEV_DEBUG_H_ ++ ++//for debug ++#define LOG_WARP_TIMING (0) ++ ++// Defines reference kern levels of printfk ++#define DEV_MSG_ERR 3 ++#define DEV_MSG_WRN 4 ++#define DEV_MSG_DBG 5 ++ ++#define DEV_MSG_LEVL DEV_MSG_WRN ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#define DEV_MSG_ENABLE ++ ++#if defined(DEV_MSG_ENABLE) ++#define DEV_MSG_FUNC_ENABLE ++ ++#define DEV_STRINGIFY(x) #x ++#define DEV_TOSTRING(x) DEV_STRINGIFY(x) ++ ++#if defined(DEV_MSG_FUNC_ENABLE) ++#define DEV_MSG_TITLE "[DEV, %s] " ++#define DEV_MSG_FUNC __func__ ++#else // NOT defined(DEV_MSG_FUNC_ENABLE) ++#define DEV_MSG_TITLE "[DEV] %s" ++#define DEV_MSG_FUNC "" ++#endif // NOT defined(DEV_MSG_FUNC_ENABLE) ++ ++#define DEV_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= DEV_MSG_LEVL) { \ ++ printk(KERN_SOH DEV_TOSTRING(dbglv) DEV_MSG_TITLE _fmt, DEV_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++#else // NOT defined(DEV_MSG_ENABLE) ++#define DEV_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(DEV_MSG_ENABLE) ++ ++#endif // _DEV_DEBUG_H_ +\ No newline at end of file +diff --git a/drivers/sstar/warp/drv/inc/dev_warp.h b/drivers/sstar/warp/drv/inc/dev_warp.h +new file mode 100755 +index 000000000000..bd180e1b72c7 +--- /dev/null ++++ b/drivers/sstar/warp/drv/inc/dev_warp.h +@@ -0,0 +1,51 @@ ++#ifndef _DEV_WARP_H_ ++#define _DEV_WARP_H_ ++ ++#include ++ ++typedef enum ++{ ++ WARP_DEV_STATE_READY = 0, ++ WARP_DEV_STATE_PROCESSING = 1, ++ WARP_DEV_STATE_DONE = 2, ++ WARP_DEV_STATE_AXI_ERROR = 3 ++} WARP_DEV_STATE; ++ ++typedef enum ++{ ++ WARP_DEV_PROC_STATE_OK = 0x0000, ++ WARP_DEV_PROC_STATE_PARAM_ERROR = 0x1000, ++ WARP_DEV_PROC_STATE_ADDRESS_NOT_ALIGNED_ERROR = 0x1001, ++ WARP_DEV_PROC_STATE_BOUND_BOX_CALC_ERROR = 0x1002, ++ WARP_DEV_PROC_STATE_BOUND_BOX_FORMAT_ERROR = 0x1003, ++ WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR = 0x1004, ++ WARP_DEV_PROC_STATE_OP_ERROR = 0x1005, ++ WARP_DEV_PROC_STATE_OUT_OF_MEMORY = 0x1006, ++ WARP_DEV_PROC_STATE_HW_UNAVAILABLE = 0x1007, ++ WARP_DEV_PROC_STATE_MEMORY_FAILURE = 0x1008, ++ WARP_DEV_PROC_STATE_BUSY = 0x1009, ++ WARP_DEV_PROC_STATE_PROC_CONFIG_ERROR = 0x100a, ++ WARP_DEV_PROC_STATE_CLK_ERROR = 0x100b, ++ WARP_DEV_PROC_STATE_DISP_MAP_CALC_ERROR = 0x100c, ++ WARP_DEV_PROC_STATE_IMAGE_INPUT_SIZE_ERROR = 0x100d, ++ WARP_DEV_PROC_STATE_IMAGE_OUTPUT_SIZE_ERROR = 0x100e ++} WARP_DEV_PROC_STATE_E; ++ ++typedef struct ++{ ++ unsigned short tile_h; ++ unsigned short tile_w; ++ unsigned short format; ++ unsigned short dummy[5]; ++ ++}BOUND_BOX_HEARDER_T; ++ ++ ++typedef void (*WARP_DEV_POST_CALLBACK)(MHAL_WARP_DEV_HANDLE, void *, WARP_DEV_STATE); ++ ++WARP_DEV_STATE warp_dev_isr_proc(MHAL_WARP_DEV_HANDLE device); ++s32 warp_dev_create(MHAL_WARP_DEV_HANDLE *device, phys_addr_t base_warp, phys_addr_t base_sys, phys_addr_t base_axi2miu0, phys_addr_t base_axi2miu1, phys_addr_t base_axi2miu2, phys_addr_t base_axi2miu3); ++s32 warp_dev_destroy(MHAL_WARP_DEV_HANDLE device); ++WARP_DEV_PROC_STATE_E warp_dev_trigger(MHAL_WARP_DEV_HANDLE device, MHAL_WARP_CONFIG *config, WARP_DEV_POST_CALLBACK callback, void *user_data); ++ ++#endif //_DEV_WARP_H_ +diff --git a/drivers/sstar/warp/drv/inc/lxdrv_warp.h b/drivers/sstar/warp/drv/inc/lxdrv_warp.h +new file mode 100755 +index 000000000000..466ce9858f3d +--- /dev/null ++++ b/drivers/sstar/warp/drv/inc/lxdrv_warp.h +@@ -0,0 +1,32 @@ ++#include ++#include ++#include ++#include ++ ++#include "mhal_warp.h" ++ ++#ifndef _MDRV_WARP_H_ ++#define _MDRV_WARP_H_ ++ ++// Device data ++typedef struct ++{ ++ struct platform_device *pdev; // platform device data ++ struct cdev cdev; // character device ++ struct clk **clk; // clock ++ s32 clk_num; // clock number ++ u32 irq; // IRQ number ++ MHAL_WARP_DEV_HANDLE dev_handle; // MHAL device handle ++ struct mutex mutex; // for critical section ++} warp_dev_data; ++ ++ ++// File private data ++typedef struct ++{ ++ warp_dev_data *dev_data; // Device data ++ MHAL_WARP_INST_HANDLE instance; // MHAL instance handle ++ wait_queue_head_t wait_queue; // Wait queue for polling operation ++} warp_file_data; ++ ++#endif // _MDRV_WARP_H_ +\ No newline at end of file +diff --git a/drivers/sstar/warp/drv/inc/mhal_common.h b/drivers/sstar/warp/drv/inc/mhal_common.h +new file mode 100755 +index 000000000000..ee10072a4020 +--- /dev/null ++++ b/drivers/sstar/warp/drv/inc/mhal_common.h +@@ -0,0 +1,241 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsTypes.h ++/// @brief MStar General Data Types ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MHAL_COMMON_H_ ++#define _MHAL_COMMON_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// data type unsigned char, data length 1 byte ++typedef unsigned char MS_U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short MS_U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int MS_U32; // 4 bytes ++/// data type unsigned int, data length 8 byte ++typedef unsigned long long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int, data length 8 byte ++typedef signed long long MS_S64; // 8 bytes ++/// data type float, data length 4 byte ++typedef float MS_FLOAT; // 4 bytes ++/// data type hardware physical address ++typedef unsigned long long MS_PHYADDR; // 32bit physical address ++/// definition for MS_BOOL ++typedef unsigned char MS_BOOL; ++ ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++ ++/// definition for VOID ++typedef void VOID; ++/// definition for FILEID ++typedef MS_S32 FILEID; ++ ++typedef MS_U64 MS_PHY; ++ ++ ++//#ifndef true ++/// definition for true ++//#define true 1 ++/// definition for false ++//#define false 0 ++//#endif ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++typedef MS_U16 MHAL_AUDIO_DEV; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// MHAL Interface Return Value Define ++//------------------------------------------------------------------------------------------------- ++ ++ ++#define MHAL_SUCCESS (0) ++#define MHAL_FAILURE (-1) ++#define MHAL_ERR_ID (0x80000000L + 0x20000000L) ++ ++ ++/****************************************************************************** ++|----------------------------------------------------------------| ++| 1 | APP_ID | MOD_ID | ERR_LEVEL | ERR_ID | ++|----------------------------------------------------------------| ++|<--><--7bits----><----8bits---><--3bits---><------13bits------->| ++******************************************************************************/ ++ ++#define MHAL_DEF_ERR( module, level, errid) \ ++ ((MS_S32)( (MHAL_ERR_ID) | ((module) << 16 ) | ((level)<<13) | (errid) )) ++ ++typedef enum ++{ ++ E_MHAL_ERR_LEVEL_INFO, /* informational */ ++ E_MHAL_ERR_LEVEL_WARNING, /* warning conditions */ ++ E_MHAL_ERR_LEVEL_ERROR, /* error conditions */ ++ E_MHAL_ERR_LEVEL_BUTT ++}MHAL_ErrLevel_e; ++ ++typedef enum ++{ ++ E_MHAL_ERR_INVALID_DEVID = 1, /* invlalid device ID */ ++ E_MHAL_ERR_INVALID_CHNID = 2, /* invlalid channel ID */ ++ E_MHAL_ERR_ILLEGAL_PARAM = 3, /* at lease one parameter is illagal ++ * eg, an illegal enumeration value */ ++ E_MHAL_ERR_EXIST = 4, /* resource exists */ ++ E_MHAL_ERR_UNEXIST = 5, /* resource unexists */ ++ E_MHAL_ERR_NULL_PTR = 6, /* using a NULL point */ ++ E_MHAL_ERR_NOT_CONFIG = 7, /* try to enable or initialize system, device ++ ** or channel, before configing attribute */ ++ E_MHAL_ERR_NOT_SUPPORT = 8, /* operation or type is not supported by NOW */ ++ E_MHAL_ERR_NOT_PERM = 9, /* operation is not permitted ++ ** eg, try to change static attribute */ ++ E_MHAL_ERR_NOMEM = 12,/* failure caused by malloc memory */ ++ E_MHAL_ERR_NOBUF = 13,/* failure caused by malloc buffer */ ++ E_MHAL_ERR_BUF_EMPTY = 14,/* no data in buffer */ ++ E_MHAL_ERR_BUF_FULL = 15,/* no buffer for new data */ ++ E_MHAL_ERR_SYS_NOTREADY = 16,/* System is not ready,maybe not initialed or ++ ** loaded. Returning the error code when opening ++ ** a device file failed. */ ++ E_MHAL_ERR_BADADDR = 17,/* bad address, ++ ** eg. used for copy_from_user & copy_to_user */ ++ E_MHAL_ERR_BUSY = 18,/* resource is busy, ++ ** eg. destroy a venc chn without unregister it */ ++ E_MHAL_ERR_BUTT = 63,/* maxium code, private error code of all modules ++ ** must be greater than it */ ++}MHAL_ErrCode_e; ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/sstar/warp/drv/pub/mhal_warp.h b/drivers/sstar/warp/drv/pub/mhal_warp.h +new file mode 100755 +index 000000000000..f41626b4ab9c +--- /dev/null ++++ b/drivers/sstar/warp/drv/pub/mhal_warp.h +@@ -0,0 +1,227 @@ ++#ifndef __MHAL_WARP_H__ ++#define __MHAL_WARP_H__ ++ ++/////////////////////////////////////////////////////////////////////////////// ++// Copyright (c) 2018 Sigmastar Semiconductor, Inc. All rights reserved. ++// ++// Wrapper device interface in kernel space ++/////////////////////////////////////////////////////////////////////////////// ++#include "mhal_common.h" ++ ++typedef void* MHAL_WARP_DEV_HANDLE; ++typedef void* MHAL_WARP_INST_HANDLE; ++ ++/// @brief MHAL WARP operation modes enumeration ++typedef enum ++{ ++ MHAL_WARP_OP_MODE_PERSPECTIVE = 0, ++ MHAL_WARP_OP_MODE_MAP = 1 ++} MHAL_WARP_OP_MODE_E; ++ ++/// @brief MHAL WARP image formats enumeration ++typedef enum ++{ ++ MHAL_WARP_IMAGE_FORMAT_RGBA = 0, ++ MHAL_WARP_IMAGE_FORMAT_YUV422 = 1, ++ MHAL_WARP_IMAGE_FORMAT_YUV420 = 2 ++} MHAL_WARP_IMAGE_FORMAT_E; ++ ++/// @brief MHAL WARP perspective coefficients enumeration ++typedef enum ++{ ++ MHAL_WARP_PERSECTIVE_COEFFS_C00 = 0, ++ MHAL_WARP_PERSECTIVE_COEFFS_C01 = 1, ++ MHAL_WARP_PERSECTIVE_COEFFS_C02 = 2, ++ MHAL_WARP_PERSECTIVE_COEFFS_C10 = 3, ++ MHAL_WARP_PERSECTIVE_COEFFS_C11 = 4, ++ MHAL_WARP_PERSECTIVE_COEFFS_C12 = 5, ++ MHAL_WARP_PERSECTIVE_COEFFS_C20 = 6, ++ MHAL_WARP_PERSECTIVE_COEFFS_C21 = 7, ++ MHAL_WARP_PERSECTIVE_COEFFS_C22 = 8, ++ MHAL_WARP_PERSECTIVE_COEFFS_NUM_COEFFS = 9 ++} MHAL_WARP_PERSECTIVE_COEFFS_E; ++ ++/// @brief MHAL WARP displacement map resolution enumeration ++typedef enum ++{ ++ MHAL_WARP_MAP_RESLOUTION_8X8 = 0, ++ MHAL_WARP_MAP_RESLOUTION_16X16 = 1 ++} MHAL_WARP_MAP_RESLOUTION_E; ++ ++/// @brief MHAL WARP displacement map format enumeration ++typedef enum ++{ ++ MHAL_WARP_MAP_FORMAT_ABSOLUTE = 0, ++ MHAL_WARP_MAP_FORMAT_RELATIVE = 1 ++} MHAL_WARP_MAP_FORMAT_E; ++ ++/// @brief WARP image plane index enumeration ++typedef enum ++{ ++ MHAL_WARP_IMAGE_PLANE_RGBA = 0, ++ MHAL_WARP_IMAGE_PLANE_Y = 0, ++ MHAL_WARP_IMAGE_PLANE_UV = 1 ++} MHAL_WARP_IMAGE_PLANE_E; ++ ++typedef enum ++{ ++ MHAL_WARP_INSTANCE_STATE_READY = 0, ++ MHAL_WARP_INSTANCE_STATE_PROCESSING = 1, ++ MHAL_WARP_INSTANCE_STATE_DONE = 2, ++ MHAL_WARP_INSTANCE_STATE_AXI_ERROR = 3, ++ MHAL_WARP_INSTANCE_STATE_PROC_ERROR = 4 ++} MHAL_WARP_INSTANCE_STATE_E; ++ ++typedef enum ++{ ++ MHAL_WARP_ISR_STATE_DONE = 0, ++ MHAL_WARP_ISR_STATE_PROCESSING = 1 ++} MHAL_WARP_ISR_STATE_E; ++ ++/// @brief MHAL WARP displacement map entry for absolute coordinates format ++typedef struct ++{ ++ MS_S32 y; ++ MS_S32 x; ++} MHAL_WARP_DISPPLAY_ABSOLUTE_ENTRY_T; ++ ++/// @brief MHAL WARP displacement map entry for coordinates' relative offset format ++typedef struct ++{ ++ MS_S16 y; ++ MS_S16 x; ++} MHAL_WARP_DISPPLAY_RELATIVE_ENTRY_T; ++ ++/// @brief MHAL WARP displacement table descriptor ++typedef struct ++{ ++ MHAL_WARP_MAP_RESLOUTION_E resolution; // map resolution ++ MHAL_WARP_MAP_FORMAT_E format; // map format (absolute, relative) ++ MS_S32 size; // size of Disp. ++ MS_PHY table; ++} MHAL_WARP_DISPLAY_TABLE_T; ++ ++typedef struct ++{ ++ MS_S16 height; // input tile height ++ MS_S16 width; // input tile width ++ MS_S16 y; // input tile top left y coordinate ++ MS_S16 x; // input tile top left x coordinate ++} MHAL_WARP_BOUND_BOX_ENTRY_T; ++ ++typedef struct ++{ ++ MS_S32 size; // bytes of bound boxes ++ MS_PHY table; // list of all bound boxes ++}MHAL_WARP_BOUND_BOX_TABLE_T; ++ ++/// @brief MHAL WARP image descriptor ++typedef struct ++{ ++ MHAL_WARP_IMAGE_FORMAT_E format; // image format ++ MS_U32 width; // image width (for YUV - Y plane width) ++ MS_U32 height; // image height (for YUV - Y plane width) ++} MHAL_WARP_IMAGE_DESC_T; ++ ++/// @brief MHAL WARP image data structure ++typedef struct ++{ ++ MS_U32 num_planes; // number of image planes ++ MS_PHY data[2]; // pointers to the image planes' data ++} MHAL_WARP_IMAGE_DATA_T; ++ ++/// @brief MHAL WARP hardware configuration structure ++typedef struct ++{ ++ MHAL_WARP_OP_MODE_E op_mode; // Operation mode ++ MHAL_WARP_DISPLAY_TABLE_T disp_table; // Displacement table descriptor ++ MHAL_WARP_BOUND_BOX_TABLE_T bb_table; // Bounding box table descriptor ++ ++ int coeff[MHAL_WARP_PERSECTIVE_COEFFS_NUM_COEFFS]; // Perspective transform coefficients ++ ++ MHAL_WARP_IMAGE_DESC_T input_image; // Input image ++ MHAL_WARP_IMAGE_DATA_T input_data; ++ ++ MHAL_WARP_IMAGE_DESC_T output_image; // Output image ++ MHAL_WARP_IMAGE_DATA_T output_data; ++ ++ MS_U8 fill_value[2]; // Fill value for out of range pixels ++ ++} MHAL_WARP_CONFIG; ++ ++//------------------------------------------------------------------------------ ++/// @brief Get warp IRQ id ++/// @return IrqId ++//------------------------------------------------------------------------------ ++MS_U32 MHAL_WARP_GetIrqNum(void); ++ ++/// @brief MHAL WARP call back for process done ++/// @param[in] instance: Instance handle. ++/// @param[in] user_data: user data passed by MHAL_WARP_Trigger() ++/// @return 0: Instance is not ready for next request, MHAL_WARP_ReadyForNext() ++/// has to be called to unlock instance ++/// 1: Instance is ready for next request ++typedef MS_BOOL (*MHAL_WARP_CALLBACK)(MHAL_WARP_INST_HANDLE instance, void *user_data); ++ ++//------------------------------------------------------------------------------ ++/// @brief Get Device Handle ++/// @param[in] id: Device Core ID. ++/// @param[out] device: Pointer to device handle. ++/// @return MHAL_ErrCode_e ++//------------------------------------------------------------------------------ ++MS_S32 MHAL_WARP_CreateDevice(MS_U32 id, MHAL_WARP_DEV_HANDLE *device); ++ ++//------------------------------------------------------------------------------ ++/// @brief Destroy Device Handle ++/// @param[in] device: Device handle. ++/// @return MHAL_ErrCode_e ++//------------------------------------------------------------------------------ ++MS_S32 MHAL_WARP_DestroyDevice(MHAL_WARP_DEV_HANDLE device); ++ ++//------------------------------------------------------------------------------ ++/// @brief Get Instance Handle ++/// @param[in] device: Device handle. ++/// @param[out] instance: Pointer to instance handle. ++/// @return MHAL_ErrCode_e ++//------------------------------------------------------------------------------ ++MS_S32 MHAL_WARP_CreateInstance(MHAL_WARP_DEV_HANDLE device, MHAL_WARP_INST_HANDLE *instance); ++ ++//------------------------------------------------------------------------------ ++/// @brief Destroy Instance Handle ++/// @param[in] instance: Instance handle. ++/// @return MHAL_ErrCode_e ++//------------------------------------------------------------------------------ ++MS_S32 MHAL_WARP_DestroyInstance(MHAL_WARP_INST_HANDLE instance); ++ ++//------------------------------------------------------------------------------ ++/// @brief Trigger Wrap Process ++/// @param[in] instance: Instance handle. ++/// @param[in] config: configuration. ++/// @param[in] data: ++/// @return MHAL_ErrCode_e ++//------------------------------------------------------------------------------ ++MS_S32 MHAL_WARP_Trigger(MHAL_WARP_INST_HANDLE instance, MHAL_WARP_CONFIG* config, MHAL_WARP_CALLBACK callback, void *user_data); ++ ++//------------------------------------------------------------------------------ ++/// @brief Check Instance status ++/// @param[in] instance: Instance handle. ++/// @return MHAL_ErrCode_e ++//------------------------------------------------------------------------------ ++MHAL_WARP_INSTANCE_STATE_E MHAL_WARP_CheckState(MHAL_WARP_INST_HANDLE instance); ++ ++//------------------------------------------------------------------------------ ++/// @brief Set state of Warp instance to be ready if process done ++/// @param[in] instance: Instance handle. ++/// @return MHAL_WARP_INSTANCE_STATE_E ++//------------------------------------------------------------------------------ ++MHAL_WARP_INSTANCE_STATE_E MHAL_WARP_ReadyForNext(MHAL_WARP_INST_HANDLE instance); ++ ++//------------------------------------------------------------------------------ ++/// @brief Device Interrupt Processing ++/// @param[in] device: Device handle. ++/// @return MHAL_WARP_ISR_STATE_E ++//------------------------------------------------------------------------------ ++MHAL_WARP_ISR_STATE_E MHAL_WARP_IsrProc(MHAL_WARP_DEV_HANDLE device); ++ ++ ++#endif /* __MHAL_WARP_H__ */ +diff --git a/drivers/sstar/warp/drv/src/common/dev_warp.c b/drivers/sstar/warp/drv/src/common/dev_warp.c +new file mode 100755 +index 000000000000..2917b69886db +--- /dev/null ++++ b/drivers/sstar/warp/drv/src/common/dev_warp.c +@@ -0,0 +1,766 @@ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "ms_platform.h" ++#include "mhal_warp.h" ++#include "dev_warp.h" ++#include "hal_clk.h" ++#include "hal_warp.h" ++#include "hal_ceva.h" ++ ++#include "dev_debug.h" ++ ++#define WARP_MAX_IMAGE_WIDTH 8189 ++#define WARP_MIN_IMAGE_WIDTH 16 ++#define WARP_MAX_IMAGE_HEIGHT 8189 ++#define WARP_MIN_IMAGE_HEIGHT 16 ++#define COEF_PREC 12 ++#define WS_COEF_PREC 24 ++#define ALIGNMENT_VALUE_2 2 ++#define ALIGNMENT_VALUE_4 4 ++#define ALIGNMENT_VALUE_16 16 ++#define ALIGNMENT_VALUE_32 32 ++#define ALIGNMENT_MASK_2 (ALIGNMENT_VALUE_2 - 1) ++#define ALIGNMENT_MASK_4 (ALIGNMENT_VALUE_4 - 1) ++#define ALIGNMENT_MASK_16 (ALIGNMENT_VALUE_16 - 1) ++#define ALIGNMENT_MASK_32 (ALIGNMENT_VALUE_32 - 1) ++#define CHECK_ALIGNEMT_2(a) (((u32)(a) & ALIGNMENT_MASK_2) != 0) ++#define CHECK_ALIGNEMT_4(a) (((u32)(a) & ALIGNMENT_MASK_4) != 0) ++#define CHECK_ALIGNEMT_16(a) (((u32)(a) & ALIGNMENT_MASK_16) != 0) ++#define CHECK_ALIGNEMT_32(a) (((u32)(a) & ALIGNMENT_MASK_32) != 0) ++ ++#define ABS(a) ((a)>(0) ? (a) : (-(a))) ++ ++typedef struct ++{ ++ struct list_head list; ++ MHAL_WARP_CONFIG *config; ++ WARP_DEV_POST_CALLBACK callback; ++ void *user_data; ++} warp_request_data; ++ ++/// @brief Data structure for driver ++typedef struct ++{ ++ warp_hal_handle hal_handle; // HAL handle for real HW configuration ++ ceva_hal_handle ceva_hal_handle; ++ s32 ceva_irq; ++ WARP_DEV_STATE state; // device state ++ struct list_head request_list; // request list to queue waiting requst ++ struct work_struct work_queue; // work queue for post process after ISR ++ struct mutex mutex; // for critical section ++} warp_dev_handle; ++ ++#if LOG_WARP_TIMING ++struct timespec gT_start; ++struct timespec gT_end; ++#endif ++/******************************************************************************************************************* ++ * warp_dev_check_config ++ * check config status before HW engine run ++ * ++ * Parameters: ++ * handle: device handle ++ * config: WARP configurations ++ * ++ * Return: ++ * WARP_DEV_PROC_STATE_E ++ */ ++static WARP_DEV_PROC_STATE_E warp_dev_check_config(MHAL_WARP_CONFIG *config) ++{ ++ int width = 0; ++ int height = 0; ++ int size = 0; ++ int decimation_factor = 0; ++ BOUND_BOX_HEARDER_T* ptbb_header; ++ int tile_w = 0; ++ int tile_h = 0; ++ u32 virt_addr = 0; ++ u32 phy_addr = 0; ++ ++ MHAL_WARP_IMAGE_DATA_T* input_data = &config->input_data; ++ MHAL_WARP_IMAGE_DATA_T* output_data = &config->output_data; ++ MHAL_WARP_IMAGE_DESC_T* input_image = &config->input_image; ++ MHAL_WARP_IMAGE_DESC_T* output_image = &config->output_image; ++ ++ MHAL_WARP_DISPLAY_TABLE_T* disp_table = &config->disp_table; ++ MHAL_WARP_BOUND_BOX_TABLE_T* bound_box = &config->bb_table; ++ int* coeff = config->coeff; ++ MHAL_WARP_OP_MODE_E op = config->op_mode; ++ ++ //check config null or not ++ if (NULL == config || ++ NULL == input_data || NULL == output_data || ++ NULL == disp_table || ++ NULL == bound_box) ++ { ++ return WARP_DEV_PROC_STATE_PARAM_ERROR; ++ } ++ ++ //check image format ++ if (input_image->format != output_image->format) ++ { ++ return WARP_DEV_PROC_STATE_PARAM_ERROR; ++ } ++ ++ //check image size : input and output ++ if (WARP_MIN_IMAGE_WIDTH > input_image->width || ++ WARP_MIN_IMAGE_HEIGHT > input_image->height || ++ WARP_MAX_IMAGE_WIDTH < input_image->width || ++ WARP_MAX_IMAGE_HEIGHT < input_image->height) ++ { ++ return WARP_DEV_PROC_STATE_PARAM_ERROR; ++ } ++ if (WARP_MIN_IMAGE_WIDTH > output_image->width || ++ WARP_MIN_IMAGE_HEIGHT > output_image->height || ++ WARP_MAX_IMAGE_WIDTH < output_image->width || ++ WARP_MAX_IMAGE_HEIGHT < output_image->height) ++ { ++ return WARP_DEV_PROC_STATE_PARAM_ERROR; ++ } ++ //check input image size restriction ++ switch(input_image->format) ++ { ++ case MHAL_WARP_IMAGE_FORMAT_RGBA: ++ if (CHECK_ALIGNEMT_4(input_image->width)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_INPUT_SIZE_ERROR; ++ } ++ break; ++ case MHAL_WARP_IMAGE_FORMAT_YUV422: ++ if (CHECK_ALIGNEMT_16(input_image->width)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_INPUT_SIZE_ERROR; ++ } ++ break; ++ case MHAL_WARP_IMAGE_FORMAT_YUV420: ++ if (CHECK_ALIGNEMT_16(input_image->width)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_INPUT_SIZE_ERROR; ++ } ++ if (CHECK_ALIGNEMT_2(input_image->height)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_INPUT_SIZE_ERROR; ++ } ++ break; ++ default: ++ return WARP_DEV_PROC_STATE_IMAGE_INPUT_SIZE_ERROR; ++ break; ++ } ++ //check output image size restriction ++ switch(output_image->format) ++ { ++ case MHAL_WARP_IMAGE_FORMAT_RGBA: ++ if (CHECK_ALIGNEMT_16(output_image->width)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_OUTPUT_SIZE_ERROR; ++ } ++ break; ++ case MHAL_WARP_IMAGE_FORMAT_YUV422: ++ if (CHECK_ALIGNEMT_32(output_image->width)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_OUTPUT_SIZE_ERROR; ++ } ++ break; ++ case MHAL_WARP_IMAGE_FORMAT_YUV420: ++ if (CHECK_ALIGNEMT_32(output_image->width)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_OUTPUT_SIZE_ERROR; ++ } ++ if (CHECK_ALIGNEMT_2(output_image->height)) ++ { ++ return WARP_DEV_PROC_STATE_IMAGE_OUTPUT_SIZE_ERROR; ++ } ++ break; ++ default: ++ return WARP_DEV_PROC_STATE_IMAGE_OUTPUT_SIZE_ERROR; ++ break; ++ } ++ ++ //check image buffer aligned or not ++ if (CHECK_ALIGNEMT_16(input_data->data[MHAL_WARP_IMAGE_PLANE_RGBA]) || ++ CHECK_ALIGNEMT_16(output_data->data[MHAL_WARP_IMAGE_PLANE_RGBA])) ++ { ++ return WARP_DEV_PROC_STATE_ADDRESS_NOT_ALIGNED_ERROR; ++ } ++ ++ if (config->input_image.format != MHAL_WARP_IMAGE_FORMAT_RGBA) //UV ++ { ++ if (CHECK_ALIGNEMT_16(input_data->data[MHAL_WARP_IMAGE_PLANE_UV]) || ++ CHECK_ALIGNEMT_16(output_data->data[MHAL_WARP_IMAGE_PLANE_UV])) ++ { ++ return WARP_DEV_PROC_STATE_ADDRESS_NOT_ALIGNED_ERROR; ++ } ++ } ++ //Check bb size and format from b.b header. ++ phy_addr = (u32)Chip_MIU_to_Phys(bound_box->table); ++ virt_addr = (u32)phys_to_virt(phy_addr); ++ ptbb_header = (BOUND_BOX_HEARDER_T*)(virt_addr); ++ tile_w = ptbb_header->tile_w; ++ tile_h = ptbb_header->tile_h; ++ width = (output_image->width + tile_w - 1) / tile_w; ++ height = (output_image->height + tile_h - 1) / tile_h; ++ size = sizeof(BOUND_BOX_HEARDER_T) + (width * height * sizeof(MHAL_WARP_BOUND_BOX_ENTRY_T) ); ++ ++ if( config->bb_table.size != size ) ++ { ++ return WARP_DEV_PROC_STATE_BOUND_BOX_CALC_ERROR; ++ } ++ ++ if( config->input_image.format != (MHAL_WARP_IMAGE_FORMAT_E)(ptbb_header->format - 1) ) ++ { ++ return WARP_DEV_PROC_STATE_BOUND_BOX_FORMAT_ERROR; ++ } ++ ++ //check bb table aligned or not ++ if (CHECK_ALIGNEMT_16(bound_box->table)) ++ { ++ return WARP_DEV_PROC_STATE_ADDRESS_NOT_ALIGNED_ERROR; ++ } ++ ++ switch(op) ++ { ++ case MHAL_WARP_OP_MODE_MAP: ++ //check disp. table aligned or not ++ if (CHECK_ALIGNEMT_16(disp_table->table)) ++ { ++ return WARP_DEV_PROC_STATE_ADDRESS_NOT_ALIGNED_ERROR; ++ } ++ ++ //grid size 8x8 or 16x16 ++ if ( disp_table->resolution == MHAL_WARP_MAP_RESLOUTION_8X8) ++ { ++ decimation_factor = 8; ++ } ++ else if (disp_table->resolution == MHAL_WARP_MAP_RESLOUTION_16X16) ++ { ++ decimation_factor = 16; ++ } ++ else ++ { ++ //error grid size ++ return WARP_DEV_PROC_STATE_DISP_MAP_CALC_ERROR; ++ } ++ ++ //check Disp. size ++ width = ((output_image->width + decimation_factor - 1) / decimation_factor) + 1; ++ height = ((output_image->height + decimation_factor - 1) / decimation_factor) + 1; ++ ++ switch(disp_table->format) ++ { ++ case MHAL_WARP_MAP_FORMAT_ABSOLUTE: ++ width = ( (width + 1)/2 ) * 2; ++ size = (height * width * 2) * 4; ++ break; ++ case MHAL_WARP_MAP_FORMAT_RELATIVE: ++ width = ( (width + 3)/4 ) * 4; ++ size = (height * width * 2) * 4; ++ break; ++ default: ++ return WARP_DEV_PROC_STATE_DISP_MAP_CALC_ERROR; ++ ++ }//end switch(format) ++ ++ if(disp_table->size != size) ++ { ++ return WARP_DEV_PROC_STATE_DISP_MAP_CALC_ERROR; ++ } ++ ++ break; ++ ++ case MHAL_WARP_OP_MODE_PERSPECTIVE: ++ ++ //check persepective value range ++ if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C00]) >= (8 << COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C01]) >= (8 << COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C10]) >= (8 << COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C11]) >= (8 << COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C22]) >= (8 << WS_COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C20]) >= (1 << WS_COEF_PREC)>>9 ) // 1.0/512 ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C21]) >= (1 << WS_COEF_PREC)>>9 ) // 1.0/512 ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C02]) > (8191 << COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ else if ( ABS(coeff[MHAL_WARP_PERSECTIVE_COEFFS_C12]) > (8191 << COEF_PREC) ) ++ { ++ return WARP_DEV_PROC_STATE_MATRIX_VALUES_ERROR; ++ } ++ break; ++ ++ default : ++ return WARP_DEV_PROC_STATE_OP_ERROR; ++ break; ++ }//end switch(op) ++ ++ return WARP_DEV_PROC_STATE_OK; ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_start ++ * Start HW engine ++ * ++ * Parameters: ++ * handle: device handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++static void warp_dev_start(warp_dev_handle *handle, MHAL_WARP_CONFIG *config) ++{ ++ warp_hal_handle* hal_handle; // HAL handle for real HW configuration ++ MHAL_WARP_OP_MODE_E op_mode; ++ BOUND_BOX_HEARDER_T* bb_header; ++ s32 bb_header_len = 0; ++ u32 virt_addr = 0; ++ u32 phy_addr = 0; ++ ++ hal_handle = &handle->hal_handle; ++ op_mode = config->op_mode; ++ ++ phy_addr = (u32)Chip_MIU_to_Phys(config->bb_table.table); ++ virt_addr = (u32)phys_to_virt(phy_addr); ++ ++ bb_header = (BOUND_BOX_HEARDER_T*)virt_addr; ++ bb_header_len = sizeof(BOUND_BOX_HEARDER_T); ++ ++ DEV_MSG(DEV_MSG_DBG, "op_mode: %d\n", op_mode ); //disp. map or perspective ++ DEV_MSG(DEV_MSG_DBG, "base address = 0x%08x\n", hal_handle->base_addr); //base address ++ ++ //set AXI bus ++ warp_hal_set_axi(hal_handle, (HAL_WARP_CONFIG *)config); ++ ++ //set image buffer pointer ++ warp_hal_set_image_point(hal_handle, (HAL_WARP_CONFIG *)config); ++ ++ //set output tile size ++ warp_hal_set_output_tile(hal_handle, bb_header->tile_w, bb_header->tile_h); ++ ++ //set image size ++ warp_hal_set_image_size(hal_handle, (HAL_WARP_CONFIG *)config); ++ ++ //point to displacement map ++ warp_hal_set_disp(hal_handle, (HAL_WARP_CONFIG *)config); ++ ++ //point to B.B table ++ warp_hal_set_bb(hal_handle, (s32)(config->bb_table.table + bb_header_len)); ++ ++ //set perspective transform coefficient matrix ++ warp_hal_set_pers_matirx(hal_handle, (HAL_WARP_CONFIG *)config); ++ ++ //set out of range pixel fill value ++ warp_hal_set_out_of_range(hal_handle, (HAL_WARP_CONFIG *)config); ++ ++ //set configure, and enable hw engine ++ warp_hal_set_config(hal_handle, (HAL_WARP_CONFIG *)config); ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_extract_request ++ * Extract a request from waiting list ++ * The request is removed from list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * ++ * Return: ++ * File data of IVE driver ++ */ ++static warp_request_data* warp_dev_extract_request(warp_dev_handle *handle) ++{ ++ warp_request_data *list_data = NULL; ++ ++ // check resuest list is empty. ++ if (list_empty(&handle->request_list)) ++ { ++ return NULL; ++ } ++ ++ // get data from list ++ list_data = list_first_entry(&handle->request_list, warp_request_data, list); ++ if (list_data != NULL) ++ { ++ list_del(handle->request_list.next); //delete first data in list ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "extract: 0x%p\n", list_data); ++ ++ return list_data; ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_get_request ++ * Get a request from waiting list ++ * The request is still kpet in list ++ * ++ * Parameters: ++ * warp_dev_handle: driver handle ++ * ++ * Return: ++ * File data of WARP driver ++ */ ++static warp_request_data* warp_dev_get_request(warp_dev_handle *handle) ++{ ++ warp_request_data *list_data = NULL; ++ ++ //check if request list is empty ++ if (list_empty(&handle->request_list)) ++ { ++ return NULL; ++ } ++ ++ //get data from request list ++ list_data = list_first_entry(&handle->request_list, warp_request_data, list); ++ if (list_data != NULL) ++ { ++ DEV_MSG(DEV_MSG_DBG, "get: 0x%p, 0x%p\n", list_data, list_data->config); ++ return list_data; ++ } ++ else ++ { ++ DEV_MSG(DEV_MSG_DBG, "get: 0x%p\n", list_data); ++ } ++ ++ return NULL; ++} ++/******************************************************************************************************************* ++ * warp_dev_add_request ++ * Add a request to waiting list ++ * ++ * Parameters: ++ * warp_dev_handle: driver handle ++ * file_data: File data of WARP driver ++ * ++ * Return: ++ * none ++ */ ++static void warp_dev_add_request(warp_dev_handle *handle, MHAL_WARP_CONFIG *config, WARP_DEV_POST_CALLBACK callback, void *user_data) ++{ ++ warp_request_data *list_data; ++ ++ //setup request data ++ list_data = kcalloc(1, sizeof(warp_request_data), GFP_KERNEL); ++ list_data->config = config; ++ list_data->callback = callback; ++ list_data->user_data = user_data; ++ ++ DEV_MSG(DEV_MSG_DBG, "add: 0x%p, 0x%p\n", list_data, config); ++ ++ //add request data to list ++ if (list_data != NULL) ++ { ++ list_add_tail(&list_data->list, &handle->request_list); ++ } ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_trigger ++ * Start WARP process image ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * WARP_DEV_PROC_STATE_E ++ */ ++WARP_DEV_PROC_STATE_E warp_dev_trigger(MHAL_WARP_DEV_HANDLE device, MHAL_WARP_CONFIG *config, WARP_DEV_POST_CALLBACK callback, void *user_data) ++{ ++ warp_dev_handle *handle = (warp_dev_handle*)device; ++ WARP_DEV_PROC_STATE_E ret = WARP_DEV_PROC_STATE_OK; ++ warp_request_data *request; ++ ++ //Check the configuration, such as image, disp. table, ...... ++ ret = warp_dev_check_config(config); ++ if(ret != WARP_DEV_PROC_STATE_OK) ++ { ++ return ret; ++ } ++ ++ mutex_lock(&handle->mutex); ++ ++ //add a request to linked list ++ warp_dev_add_request(handle, config, callback, user_data); ++ ++ // do nothing if hw is not ready ++ if (handle->state != WARP_DEV_STATE_READY) ++ { ++ DEV_MSG(DEV_MSG_DBG, "HW is busy\n"); ++ ret = WARP_DEV_PROC_STATE_OK; ++ goto RETURN; ++ } ++ ++ //get a request from liked list ++ request = warp_dev_get_request(handle); ++ if (request == NULL) //no more request in queue ++ { ++ DEV_MSG(DEV_MSG_DBG, "no more request in queue\n"); ++ ret = WARP_DEV_PROC_STATE_MEMORY_FAILURE; ++ goto RETURN; ++ } ++ ++ //run warp ++ handle->state = WARP_DEV_STATE_PROCESSING; ++ ++ DEV_MSG(DEV_MSG_DBG, "process: %p\n", (void*)(u32)config->input_data.data[0]); ++ ++ //set miu bus ++ ceva_hal_set_axi2miu(&handle->ceva_hal_handle); ++ ++ //enable ceva warp of wrapper ++ ceva_hal_enable_warp(&handle->ceva_hal_handle); ++ ++#if LOG_WARP_TIMING ++ getnstimeofday(&gT_start); ++#endif ++ ++ //enable warp ++ warp_dev_start(handle, config); //start HW engine ++ ++RETURN: ++ mutex_unlock(&handle->mutex); ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_post_proc ++ * Post process after WARP HW done ++ * ++ * Parameters: ++ * wq: work queue ++ * ++ * Return: ++ * none ++ */ ++void warp_dev_post_proc(struct work_struct *wq) ++{ ++ warp_dev_handle *handle; ++ warp_request_data *current_request = NULL; ++ warp_request_data *next_request = NULL; ++ warp_request_data temp_request; ++ ++ handle = (warp_dev_handle*)container_of(wq, warp_dev_handle, work_queue); ++ ++ mutex_lock(&handle->mutex); ++ ++ DEV_MSG(DEV_MSG_DBG, "post proc handle: 0x%p\n", handle); ++ ++ //get processed file_data from request list, then delete it in the list. ++ current_request = warp_dev_extract_request(handle); ++ if (current_request == NULL) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't get current request\n"); ++ goto RETURN; ++ } ++ ++ // copy current to temporary instance ++ memcpy(&temp_request, current_request, sizeof(temp_request)); ++ ++ // free buffer ++ kfree(current_request); ++ ++ //get current file_data from request list, it will be used by warp_dev_start(). ++ next_request = warp_dev_get_request(handle); ++ ++ //reset ceva warp of wrapper ++ ceva_hal_reset_warp(&handle->ceva_hal_handle); ++ ++ if (next_request == NULL) ++ { ++ DEV_MSG(DEV_MSG_DBG, "no more request in queue\n"); ++ handle->state = WARP_DEV_STATE_READY; ++ ++ //Run callback to notify caller to do post-process ++ if (temp_request.callback) ++ { ++ temp_request.callback(handle, temp_request.user_data, handle->state); ++ } ++ } ++ else ++ { ++ //Run callback to notify caller to do post-process ++ if (temp_request.callback) ++ { ++ temp_request.callback(handle, temp_request.user_data, handle->state); ++ } ++ ++ //run warp ++ handle->state = WARP_DEV_STATE_PROCESSING; ++ DEV_MSG(DEV_MSG_DBG, "process: %p\n", (void*)(u32)next_request->config->input_data.data[0]); ++ ++ //set miu bus ++ ceva_hal_set_axi2miu(&handle->ceva_hal_handle); ++ ++ //enable ceva warp of wrapper ++ ceva_hal_enable_warp(&handle->ceva_hal_handle); ++ ++ //enable warp ++ warp_dev_start(handle, next_request->config); ++ } ++ ++RETURN: ++ mutex_unlock(&handle->mutex); ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_isr_proc ++ * ISR handler, check and clear ISR ++ * ++ * Parameters: ++ * irq: interrupt number ++ * handle: device handle ++ * ++ * Return: ++ * None ++ */ ++WARP_DEV_STATE warp_dev_isr_proc(MHAL_WARP_DEV_HANDLE device) ++{ ++ warp_dev_handle *handle = (warp_dev_handle*)device; ++ u32 irq_status; ++ u32 irq_ceva; ++ ++#if LOG_WARP_TIMING ++ getnstimeofday(&gT_end); ++ DEV_MSG(DEV_MSG_WRN, "Warp proc %lld us\n", (long long)gT_end.tv_sec * 1000000 + (long long)gT_end.tv_nsec/1000 - (long long)gT_start.tv_sec*1000000 - (long long)gT_start.tv_nsec/1000); ++#endif ++ ++ // get warp IRQ status from target. ++ irq_ceva = (u32)ceva_hal_get_irq_status(&handle->ceva_hal_handle); ++ ++ // do nothing if WARP IRQ is not triggered ++ if((irq_ceva & handle->ceva_irq) == 0) ++ { ++ if (irq_ceva == 0) ++ { ++ DEV_MSG(DEV_MSG_ERR, "unexpected irq: 0x%X (0x%X), status = 0x%X\n", irq_ceva, handle->ceva_irq, irq_status); ++ } ++ return handle->state; ++ } ++ ++ // check and clear IRQ status ++ warp_hal_get_hw_status(&handle->hal_handle); //read status register (read /clear) ++ irq_status = (u32)handle->hal_handle.reg_bank.sta.fields.oc; //operation complete bit ++ ++ DEV_MSG(DEV_MSG_DBG, "handle: 0x%p, irq: 0x%X (0x%X), status = 0x%X\n", handle, irq_ceva, handle->ceva_irq, irq_status); ++ ++ // do nothing if WARP internal status is not enabled ++ if (!irq_status) ++ { ++ DEV_MSG(DEV_MSG_ERR, "WARP status is not triggered: 0x%X (0x%X), status = 0x%X\n", irq_ceva, handle->ceva_irq, irq_status); ++ return handle->state; ++ } ++ ++ // Check AXI bus error bit of satus register ++ if (handle->hal_handle.reg_bank.sta.fields.axierr) // we should use HAL function, not check register directly ++ { ++ DEV_MSG(DEV_MSG_ERR, "AXI ERROR: 0x%X (0x%X), status = 0x%X, err = 0x%X\n", irq_ceva, handle->ceva_irq, irq_status, handle->hal_handle.reg_bank.sta.fields.axierr); ++ handle->state = WARP_DEV_STATE_AXI_ERROR; ++ } else { ++ handle->state = WARP_DEV_STATE_DONE; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "start post proc handle: 0x%p\n", handle); ++ ++ INIT_WORK(&handle->work_queue, warp_dev_post_proc); ++ schedule_work(&handle->work_queue); ++ ++ return handle->state; ++} ++ ++/******************************************************************************************************************* ++ * warp_dev_destroy ++ * Release WARP settings ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * none ++ */ ++s32 warp_dev_destroy(MHAL_WARP_DEV_HANDLE device) ++{ ++ warp_dev_handle *handle = (warp_dev_handle*)device; ++ ++ if (handle->state != WARP_DEV_STATE_READY) ++ return E_MHAL_ERR_BUSY; ++ ++ mutex_destroy(&handle->mutex); ++ kfree(handle); ++ ++ return MHAL_SUCCESS; ++} ++/******************************************************************************************************************* ++ * warp_dev_create ++ * create WARP device ++ * ++ * Parameters: ++ * handle: device handle ++ * pdev: platform device ++ * base_addr: base addr of HW register bank ++ * ++ * Return: ++ * none ++ */ ++s32 warp_dev_create(MHAL_WARP_DEV_HANDLE *device, phys_addr_t base_warp, phys_addr_t base_sys, phys_addr_t base_axi2miu0, phys_addr_t base_axi2miu1, phys_addr_t base_axi2miu2, phys_addr_t base_axi2miu3) ++{ ++ warp_dev_handle *handle; ++ ++ handle = kcalloc(1, sizeof(warp_dev_handle), GFP_KERNEL); ++ if (handle == NULL) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't allocate buffer for device\n"); ++ return E_MHAL_ERR_NOMEM; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "addr 0x%08X\n", base_warp); ++ ++ memset(handle, 0, sizeof(warp_dev_handle)); ++ ++ //initialize hal_handle, setting physical address ++ warp_hal_init(&handle->hal_handle, base_warp); ++ ceva_hal_init(&handle->ceva_hal_handle, base_sys, base_axi2miu0, base_axi2miu1, base_axi2miu2, base_axi2miu3); ++ ++ //set warp IRQ for ceva wrapper ++ handle->ceva_irq = CEVA_HAL_IRQ_WARP; ++ ++ //initialize request list ++ INIT_LIST_HEAD(&handle->request_list); ++ DEV_MSG(DEV_MSG_DBG, "list_empty = %d\n", list_empty(&handle->request_list)); ++ ++ // enable IRQ ++ // ceva_hal_enable_irq(&handle->ceva_hal_handle, handle->ceva_irq_target, handle->ceva_irq); ++ ++ handle->state = WARP_DEV_STATE_READY; ++ mutex_init(&handle->mutex); ++ ++ *device = (MHAL_WARP_DEV_HANDLE)handle; ++ ++ return MHAL_SUCCESS; ++} +diff --git a/drivers/sstar/warp/drv/src/common/mhal_warp.c b/drivers/sstar/warp/drv/src/common/mhal_warp.c +new file mode 100755 +index 000000000000..090970cb5d96 +--- /dev/null ++++ b/drivers/sstar/warp/drv/src/common/mhal_warp.c +@@ -0,0 +1,257 @@ ++#include "mhal_warp.h" ++ ++#include ++#include ++#include ++ ++#include "infinity2/irqs.h" ++#include "dev_warp.h" ++#include "dev_debug.h" ++ ++#define RIU_BASE_ADDR (0x1F000000) ++#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR)) ++ ++#define BANK_CEVA_SYS0 (BANK_CAL(0x1128)) ++#define BANK_CEVA_BUS0 (BANK_CAL(0x1126)) ++#define BANK_CEVA_BUS1 (BANK_CAL(0x1127)) ++#define BANK_CWVA_WARP (BANK_CAL(0x1A24)) ++ ++typedef struct ++{ ++ MHAL_WARP_DEV_HANDLE device; ++ MHAL_WARP_INSTANCE_STATE_E state; ++ MHAL_WARP_CONFIG config; ++ MHAL_WARP_CALLBACK callback; ++ void *user_data; ++ struct mutex mutex; // for critical section ++} mhal_warp_instance; ++ ++static void dump_config(MHAL_WARP_CONFIG* config) ++{ ++ DEV_MSG(DEV_MSG_DBG, "config %p\n", config); ++ ++ DEV_MSG(DEV_MSG_DBG, ".op_mode = %d,\n", config->op_mode); ++ DEV_MSG(DEV_MSG_DBG, ".disp_table = {%d, %d, %d, 0x%p},\n", config->disp_table.resolution, config->disp_table.format,config->disp_table.size, (void*)(MS_U32)config->disp_table.table); ++ DEV_MSG(DEV_MSG_DBG, ".bb_table = {%d, 0x%p},\n", config->bb_table.size,(void*)(MS_U32)config->bb_table.table); ++ DEV_MSG(DEV_MSG_DBG, ".coeff = {%d, %d, %d, %d, %d, %d, %d, %d, %d},\n", config->coeff[0], config->coeff[1], config->coeff[2], config->coeff[3], config->coeff[4], config->coeff[5], config->coeff[6], config->coeff[7], config->coeff[8]); ++ DEV_MSG(DEV_MSG_DBG, ".input_image = {%d, %d, %d},\n", config->input_image.format, config->input_image.width, config->input_image.height); ++ DEV_MSG(DEV_MSG_DBG, ".input_data = {%d, 0x%p, 0x%p},\n", config->input_data.num_planes, (void*)(MS_U32)config->input_data.data[0], (void*)(MS_U32)config->input_data.data[1]); ++ DEV_MSG(DEV_MSG_DBG, ".output_image = {%d, %d, %d},\n", config->output_image.format, config->output_image.width, config->output_image.height); ++ DEV_MSG(DEV_MSG_DBG, ".output_data = {%d, 0x%p, 0x%p},\n", config->output_data.num_planes, (void*)(MS_U32)config->output_data.data[0], (void*)(MS_U32)config->output_data.data[1]); ++ DEV_MSG(DEV_MSG_DBG, ".fill_value = {%d, %d},\n", config->fill_value[0], config->fill_value[1]); ++} ++ ++MS_U32 MHAL_WARP_GetIrqNum(void) ++{ ++ MS_U32 irqid = 0; ++ irqid = INT_IRQ_78_WARP2RIU_INT+32; ++ return irqid; ++} ++ ++MS_S32 MHAL_WARP_CreateDevice(MS_U32 id, MHAL_WARP_DEV_HANDLE *device) ++{ ++ s32 ret; ++ ++ ret = warp_dev_create(device, BANK_CWVA_WARP, BANK_CEVA_SYS0, BANK_CEVA_BUS0, BANK_CEVA_BUS0 + 0x100, BANK_CEVA_BUS1, BANK_CEVA_BUS1 + 0x100); ++ if (ret != 0) ++ { ++ DEV_MSG(DEV_MSG_ERR, "failed to init device\n"); ++ return E_MHAL_ERR_INVALID_DEVID; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "device buffer 0x%p\n", *device); ++ ++ return MHAL_SUCCESS; ++} ++ ++MS_S32 MHAL_WARP_DestroyDevice(MHAL_WARP_DEV_HANDLE device) ++{ ++ return warp_dev_destroy(device); ++} ++ ++MS_S32 MHAL_WARP_CreateInstance(MHAL_WARP_DEV_HANDLE device, MHAL_WARP_INST_HANDLE *instance) ++{ ++ mhal_warp_instance *inst_handle; ++ ++ inst_handle = kcalloc(1, sizeof(mhal_warp_instance), GFP_KERNEL); ++ if (inst_handle == NULL) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't allocate buffer for instance\n"); ++ return E_MHAL_ERR_NOMEM; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "device: 0x%p, instance buffer 0x%p\n", device, inst_handle); ++ ++ inst_handle->device = device; ++ inst_handle->state = MHAL_WARP_INSTANCE_STATE_READY; ++ mutex_init(&inst_handle->mutex); ++ ++ *instance = (MHAL_WARP_INST_HANDLE)inst_handle; ++ ++ return MHAL_SUCCESS; ++} ++ ++MS_S32 MHAL_WARP_DestroyInstance(MHAL_WARP_INST_HANDLE instance) ++{ ++ mhal_warp_instance *inst_handle = (mhal_warp_instance*)instance; ++ ++ DEV_MSG(DEV_MSG_DBG, "destroy instance 0x%p\n", inst_handle); ++ ++ switch (MHAL_WARP_CheckState(instance)) ++ { ++ case MHAL_WARP_INSTANCE_STATE_PROCESSING: ++ case MHAL_WARP_INSTANCE_STATE_DONE: ++ DEV_MSG(DEV_MSG_ERR, "instance 0x%p is still processing\n", inst_handle); ++ return E_MHAL_ERR_BUSY; ++ ++ default: ++ break; ++ } ++ ++ mutex_destroy(&inst_handle->mutex); ++ kfree(inst_handle); ++ ++ return MHAL_SUCCESS; ++} ++ ++void MHAL_WARP_PostProc(MHAL_WARP_DEV_HANDLE device, void *user_data, WARP_DEV_STATE dev_state) ++{ ++ mhal_warp_instance *inst_handle = (mhal_warp_instance*)user_data; ++ ++ if (inst_handle == NULL) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't get instance\n"); ++ return; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "post process instance 0x%p\n", inst_handle); ++ ++ mutex_lock(&inst_handle->mutex); ++ ++ switch (dev_state) ++ { ++ case WARP_DEV_STATE_DONE: ++ inst_handle->state = MHAL_WARP_INSTANCE_STATE_DONE; ++ break; ++ ++ case WARP_DEV_STATE_READY: ++ inst_handle->state = MHAL_WARP_INSTANCE_STATE_READY; ++ break; ++ ++ case WARP_DEV_STATE_AXI_ERROR: ++ default: ++ inst_handle->state = MHAL_WARP_INSTANCE_STATE_AXI_ERROR; ++ break; ++ ++ } ++ ++ mutex_unlock(&inst_handle->mutex); ++ ++ DEV_MSG(DEV_MSG_DBG, "instance 0x%p state is %d\n", inst_handle, inst_handle->state); ++ ++ if (inst_handle->callback) ++ { ++ if (inst_handle->callback((MHAL_WARP_INST_HANDLE)inst_handle, inst_handle->user_data)) ++ { ++ MHAL_WARP_ReadyForNext((MHAL_WARP_INST_HANDLE)inst_handle); ++ } ++ } ++} ++ ++ ++MS_S32 MHAL_WARP_Trigger(MHAL_WARP_INST_HANDLE instance, MHAL_WARP_CONFIG* config, MHAL_WARP_CALLBACK callback, void *user_data) ++{ ++ mhal_warp_instance *inst_handle = (mhal_warp_instance*)instance; ++ WARP_DEV_PROC_STATE_E ret; ++ ++ mutex_lock(&inst_handle->mutex); ++ ++ // Process can be start only if instance is READY ++ if (inst_handle->state != MHAL_WARP_INSTANCE_STATE_READY) ++ { ++ DEV_MSG(DEV_MSG_ERR, "instance 0x%p is not ready to service\n", inst_handle); ++ mutex_unlock(&inst_handle->mutex); ++ return E_MHAL_ERR_BUSY; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "instance 0x%p start process\n", inst_handle); ++ ++ // dump config (debug only) ++ dump_config(config); ++ ++ memcpy(&inst_handle->config, config, sizeof(MHAL_WARP_CONFIG)); ++ inst_handle->callback = callback; ++ inst_handle->user_data = user_data; ++ ++ ret = warp_dev_trigger(inst_handle->device, &inst_handle->config, MHAL_WARP_PostProc, inst_handle); ++ if (ret != WARP_DEV_PROC_STATE_OK) ++ { ++ DEV_MSG(DEV_MSG_ERR, "failed to process instance 0x%p, err no. 0x%X\n", inst_handle, ret); ++ mutex_unlock(&inst_handle->mutex); ++ return E_MHAL_ERR_NOT_CONFIG; ++ } ++ ++ inst_handle->state = MHAL_WARP_INSTANCE_STATE_PROCESSING; ++ ++ mutex_unlock(&inst_handle->mutex); ++ ++ return MHAL_SUCCESS; ++} ++ ++MHAL_WARP_INSTANCE_STATE_E MHAL_WARP_CheckState(MHAL_WARP_INST_HANDLE instance) ++{ ++ mhal_warp_instance *inst_handle = (mhal_warp_instance*)instance; ++ ++ DEV_MSG(DEV_MSG_DBG, "instance 0x%p state is %d\n", inst_handle, inst_handle->state); ++ ++ return inst_handle->state; ++} ++ ++MHAL_WARP_INSTANCE_STATE_E MHAL_WARP_ReadyForNext(MHAL_WARP_INST_HANDLE instance) ++{ ++ mhal_warp_instance *inst_handle = (mhal_warp_instance*)instance; ++ ++ // We seperate state of DONE and READY for multi-instance. ++ // All instance can service one process only, and other request should be wait until state read is set. ++ // Linux kernel calls poll as a barrier before because we change the state READY here ++ if (inst_handle->state == MHAL_WARP_INSTANCE_STATE_DONE) ++ { ++ mutex_lock(&inst_handle->mutex); ++ ++ DEV_MSG(DEV_MSG_DBG, "change instance 0x%p state to ready\n", inst_handle); ++ inst_handle->state = MHAL_WARP_INSTANCE_STATE_READY; ++ ++ mutex_unlock(&inst_handle->mutex); ++ } ++ ++ return inst_handle->state; ++} ++ ++ ++MHAL_WARP_ISR_STATE_E MHAL_WARP_IsrProc(MHAL_WARP_DEV_HANDLE device) ++{ ++ WARP_DEV_STATE state; ++ ++ DEV_MSG(DEV_MSG_DBG, "ISR for device 0x%p\n", device); ++ ++ state = warp_dev_isr_proc(device); ++ if (state == WARP_DEV_STATE_DONE) ++ { ++ return MHAL_WARP_ISR_STATE_DONE; ++ } ++ ++ return MHAL_WARP_ISR_STATE_PROCESSING; ++} ++ ++#if 0 ++EXPORT_SYMBOL(MHAL_WARP_GetIrqNum); ++EXPORT_SYMBOL(MHAL_WARP_CreateDevice); ++EXPORT_SYMBOL(MHAL_WARP_DestroyDevice); ++EXPORT_SYMBOL(MHAL_WARP_CreateInstance); ++EXPORT_SYMBOL(MHAL_WARP_DestroyInstance); ++EXPORT_SYMBOL(MHAL_WARP_PostProc); ++EXPORT_SYMBOL(MHAL_WARP_Trigger); ++EXPORT_SYMBOL(MHAL_WARP_CheckState); ++EXPORT_SYMBOL(MHAL_WARP_ReadyForNext); ++EXPORT_SYMBOL(MHAL_WARP_IsrProc); ++#endif +\ No newline at end of file +diff --git a/drivers/sstar/warp/drv/src/linux/lxdrv_warp.c b/drivers/sstar/warp/drv/src/linux/lxdrv_warp.c +new file mode 100755 +index 000000000000..acf33352b9bc +--- /dev/null ++++ b/drivers/sstar/warp/drv/src/linux/lxdrv_warp.c +@@ -0,0 +1,634 @@ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "lxdrv_warp.h" ++#include "mdrv_warp_io.h" ++ ++#include "dev_debug.h" ++ ++#define STAND_ALONE (1) //trun on/off module_init and module_exit ++ ++#define WARP_LXDRV_DEVICE_COUNT (1) // How many device will be installed ++#define WARP_LXDRV_NAME "mstar_warp" ++#define WARP_LXDRV_MINOR (0) ++#define WARP_LXDRV_CLASS_NAME "mstar_warp_class" ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_post_proc ++ * Post process after IRQ triggered ++ * ++ * Parameters: ++ * device: ++ * ++ * ++ * Return: ++ * ++ */ ++MS_BOOL warp_lxdrv_post_proc(MHAL_WARP_INST_HANDLE instance, void *user_data) ++{ ++ warp_file_data *file_data = (warp_file_data*)user_data; ++ MHAL_WARP_INSTANCE_STATE_E state; ++ ++ state = MHAL_WARP_CheckState(file_data->instance); ++ if (state != MHAL_WARP_INSTANCE_STATE_READY) ++ { ++ DEV_MSG(DEV_MSG_ERR, "unexpect state %d\n", state); ++ } ++ ++ // set ready and wake up waiting thread/process ++ wake_up_interruptible(&file_data->wait_queue); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_isr_proc ++ * ISR handler ++ * ++ * Parameters: ++ * irq: IRQ ++ * dev_data: Device data which is assigned from request_irq() ++ * ++ * Return: ++ * Always IRQ_HANDLED to stop parsing ISR ++ */ ++irqreturn_t warp_lxdrv_isr_proc(s32 irq, void* data) ++{ ++ warp_dev_data *dev_data = (warp_dev_data*)data; ++ MHAL_WARP_ISR_STATE_E state; ++ ++ state = MHAL_WARP_IsrProc(dev_data->dev_handle); ++ switch(state) ++ { ++ case MHAL_WARP_ISR_STATE_DONE: ++ return IRQ_HANDLED; ++ ++ default: ++ return IRQ_NONE; ++ } ++ ++ return IRQ_NONE; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_open ++ * File open handler ++ * The device can has a instance at the same time, and the open ++ * operator also enable the request ISR. ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++ ++static s32 warp_lxdrv_open(struct inode *inode, struct file *filp) ++{ ++ warp_dev_data *dev_data; ++ warp_file_data *file_data; ++ s32 err = 0; ++ ++ //get dev_data struct pointer ++ dev_data = container_of(inode->i_cdev, warp_dev_data, cdev); ++ ++ //allocate buffer for file_data ++ file_data = devm_kcalloc(&dev_data->pdev->dev, 1, sizeof(warp_file_data), GFP_KERNEL); ++ if (file_data == NULL) ++ { ++ DEV_MSG(DEV_MSG_ERR, "error: can't allocate buffer\n"); ++ return -ENOSPC; //? ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "filp: 0x%p, file_data: 0x%p\n", filp, file_data); ++ ++ //Assgin dev_data and keep file_data in the file structure ++ if (MHAL_SUCCESS != MHAL_WARP_CreateInstance(dev_data->dev_handle, &file_data->instance)) ++ { ++ err = -EIO; ++ goto ERROR_1; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "filp: 0x%p, file_data: 0x%p, instance: 0x%p\n", filp, file_data, file_data->instance); ++ ++ file_data->dev_data = dev_data; ++ filp->private_data = file_data; ++ ++ //Init wait queue ++ init_waitqueue_head(&file_data->wait_queue); ++ ++ return 0; ++ ++ERROR_1: ++ devm_kfree(&dev_data->pdev->dev, file_data); ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_release ++ * File close handler ++ * The operator will release ISR ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++static s32 warp_lxdrv_release(struct inode *inode, struct file *filp) ++{ ++ warp_file_data *file_data; ++ warp_dev_data *dev_data ; ++ ++ file_data = (warp_file_data*)filp->private_data; ++ dev_data = file_data->dev_data; ++ ++ DEV_MSG(DEV_MSG_DBG, "filp: 0x%p\n", filp); ++ ++ MHAL_WARP_DestroyInstance(file_data->instance); ++ ++ // Release memory ++ devm_kfree(&dev_data->pdev->dev, file_data); ++ ++ return 0; ++} ++/******************************************************************************************************************* ++ * warp_lxdrv_ioctl_trigger ++ * IOCTL handler for WARP_IOC_TRIGGER ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of warp_lxdrv_ioctl from userspace ++ * ++ * Return: ++ * 0 indicates success, others indicate failure ++ */ ++static s32 warp_lxdrv_ioctl_trigger(warp_file_data *file_data, unsigned long arg) ++{ ++ unsigned long proc_config_status = 0; ++ MHAL_WARP_CONFIG config; ++ ++ if (MHAL_WARP_INSTANCE_STATE_READY != MHAL_WARP_CheckState(file_data->instance)) ++ { ++ DEV_MSG(DEV_MSG_ERR, "One instance can request once at the same time only\n"); ++ return E_MHAL_ERR_BUSY; ++ } ++ ++ //get config setting from user space ++ proc_config_status = copy_from_user(&config, (void*)arg, sizeof(MHAL_WARP_CONFIG) ); ++ if(proc_config_status != 0) ++ { ++ DEV_MSG(DEV_MSG_ERR, "Can't copy config from user space\n"); ++ return E_MHAL_ERR_ILLEGAL_PARAM; ++ } ++ ++ if (MHAL_SUCCESS != MHAL_WARP_Trigger(file_data->instance, &config, warp_lxdrv_post_proc, (void*)file_data)) ++ { ++ DEV_MSG(DEV_MSG_ERR, "Can't process warp\n"); ++ return E_MHAL_ERR_NOT_CONFIG; ++ } ++ ++ return MHAL_SUCCESS; ++ ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_ioctl ++ * IOCTL handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * cmd: command ++ * arg: argument from user space ++ * ++ * Return: ++ * standard return value ++ */ ++long warp_lxdrv_ioctl(struct file *filp, u32 cmd, unsigned long arg) ++{ ++ warp_file_data *file_data; ++ warp_dev_data *dev_data; ++ s32 err = MHAL_SUCCESS; ++ ++ //get file_data and device_data struct pointer ++ file_data = (warp_file_data*)filp->private_data; ++ dev_data = file_data->dev_data; ++ ++ DEV_MSG(DEV_MSG_DBG, "filp: 0x%p, file_data: 0x%p\n", filp, file_data); ++ ++ // Enter critical section ++ mutex_lock(&dev_data->mutex); ++ ++ switch(cmd) ++ { ++ case WARP_IOC_TRIGGER: ++ err = warp_lxdrv_ioctl_trigger(file_data, arg); ++ break; ++ ++ default: ++ err = ESRCH; ++ break; ++ } ++ ++//RETURN: ++ // Leave critical section ++ mutex_unlock(&dev_data->mutex); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_ioctl ++ * poll handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * wait: wait queue ++ * ++ * Return: ++ * only 0 or POLLIN | POLLRDNORM ++ */ ++static u32 warp_lxdrv_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ warp_file_data *file_data = (warp_file_data*)filp->private_data; ++ MHAL_WARP_INSTANCE_STATE_E state; ++ ++ DEV_MSG(DEV_MSG_DBG, "polling, file_data 0x%p, instance 0x%p\n", file_data, file_data->instance); ++ ++ state = MHAL_WARP_CheckState(file_data->instance); ++ ++ DEV_MSG(DEV_MSG_DBG, "polling 0x%p 0x%X\n", &file_data->wait_queue, state); ++ ++ // Check before wait ++ switch(state ) ++ { ++ case MHAL_WARP_INSTANCE_STATE_DONE: ++ DEV_MSG(DEV_MSG_DBG, "Operation ready before polling\n"); ++ MHAL_WARP_ReadyForNext(file_data->instance); ++ return POLLIN | POLLRDNORM; ++ ++ case MHAL_WARP_INSTANCE_STATE_READY: ++ DEV_MSG(DEV_MSG_DBG, "Operation ready before polling\n"); ++ return POLLIN | POLLRDNORM; ++ ++ case MHAL_WARP_INSTANCE_STATE_AXI_ERROR: ++ case MHAL_WARP_INSTANCE_STATE_PROC_ERROR: ++ DEV_MSG(DEV_MSG_ERR, "AXI error occurs (occurs before polling)\n"); ++ MHAL_WARP_ReadyForNext(file_data->instance); ++ return POLLERR; ++ ++ case MHAL_WARP_INSTANCE_STATE_PROCESSING: ++ break; ++ ++ default: ++ DEV_MSG(DEV_MSG_ERR, "unexpect state %d (occurs before polling)\n", state); ++ break; ++ } ++ ++ poll_wait(filp, &file_data->wait_queue, wait); //add file_data to wait list, then block until HW finish (isr_post_process) ++ ++ state = MHAL_WARP_CheckState(file_data->instance); ++ ++ // Check after wait ++ switch(state ) ++ { ++ case MHAL_WARP_INSTANCE_STATE_DONE: ++ DEV_MSG(DEV_MSG_DBG, "Operation ready after polling\n"); ++ MHAL_WARP_ReadyForNext(file_data->instance); ++ return POLLIN | POLLRDNORM; ++ ++ case MHAL_WARP_INSTANCE_STATE_AXI_ERROR: ++ case MHAL_WARP_INSTANCE_STATE_PROC_ERROR: ++ DEV_MSG(DEV_MSG_ERR, "AXI error occurs\n"); ++ MHAL_WARP_ReadyForNext(file_data->instance); ++ return POLLERR; ++ ++ case MHAL_WARP_INSTANCE_STATE_PROCESSING: ++ break; ++ ++ default: ++ DEV_MSG(DEV_MSG_ERR, "unexpect state %d\n", state); ++ break; ++ } ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Platform functions ++//------------------------------------------------------------------------------------------------- ++// Use a struct to gather all global variable ++static struct ++{ ++ s32 major; // cdev major number ++ s32 minor_star; // begining of cdev minor number ++ s32 reg_count; // registered count ++ struct class *class; //class pointer ++} g_warp_drv = {0, 0, 0, NULL}; ++ ++static const struct file_operations warp_fops = { ++ .owner = THIS_MODULE, ++ .open = warp_lxdrv_open, ++ .release = warp_lxdrv_release, ++ .unlocked_ioctl = warp_lxdrv_ioctl, ++ .poll = warp_lxdrv_poll, ++}; ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_probe ++ * Platform device prob handler ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static s32 warp_lxdrv_probe(struct platform_device *pdev) ++{ ++ s32 err; ++ warp_dev_data *dev_data; ++ struct device *dev; ++ ++ // create drv data buffer ++ dev_data = devm_kcalloc(&pdev->dev, 1, sizeof(warp_dev_data), GFP_KERNEL); ++ if (dev_data == NULL) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't allocate dev data buffer\n"); ++ return -ENOMEM; ++ } ++ DEV_MSG(DEV_MSG_DBG, "dev_data: 0x%p (size = %d)\n", dev_data, sizeof(warp_dev_data)); ++ ++ //Inti mutex ++ mutex_init(&dev_data->mutex); ++ ++ // Init dev_data ++ dev_data->pdev = pdev; ++ ++ err = MHAL_WARP_CreateDevice(0, &dev_data->dev_handle); ++ if (err != MHAL_SUCCESS) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't init device\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ // Retrieve IRQ ++ dev_data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (dev_data->irq < 0) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't find IRQ\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ // Register a ISR ++ err = request_irq(dev_data->irq, warp_lxdrv_isr_proc, 0, "warp isr", dev_data); ++ if (err != 0) ++ { ++ DEV_MSG(DEV_MSG_ERR, "warp interrupt failed (irq: %d, errno:%d)\n", dev_data->irq, err); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ // Add cdev ++ cdev_init(&dev_data->cdev, &warp_fops); ++ err= cdev_add(&dev_data->cdev, MKDEV(g_warp_drv.major, g_warp_drv.minor_star + g_warp_drv.reg_count), 1); ++ if (err) ++ { ++ DEV_MSG(DEV_MSG_ERR, "Unable add a character device\n"); ++ goto ERROR_2; ++ } ++ ++ // Create a instance in class ++ dev = device_create(g_warp_drv.class, ++ NULL, ++ MKDEV(g_warp_drv.major, g_warp_drv.minor_star + g_warp_drv.reg_count), ++ dev_data, ++ WARP_LXDRV_NAME); ++ ++ if (IS_ERR(dev)) ++ { ++ DEV_MSG(DEV_MSG_ERR, "can't create device\n"); ++ err = -ENODEV; ++ goto ERROR_3; ++ } ++ ++ // Increase registered count ++ g_warp_drv.reg_count++; ++ ++ dev_set_drvdata(&pdev->dev, dev_data); ++ ++ return 0; ++ ++ERROR_3: ++ cdev_del(&dev_data->cdev); ++ ++ERROR_2: ++ free_irq(dev_data->irq, dev_data); ++ ++ERROR_1: ++ devm_kfree(&dev_data->pdev->dev, dev_data); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_remove ++ * Platform device remove handler ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static s32 warp_lxdrv_remove(struct platform_device *pdev) ++{ ++ warp_dev_data* dev_data; ++ ++ dev_data = (warp_dev_data*)dev_get_drvdata(&pdev->dev); ++ ++ DEV_MSG(DEV_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ //IRQ release ++ free_irq(dev_data->irq, dev_data); ++ ++ MHAL_WARP_DestroyDevice(dev_data->dev_handle); ++ ++ //instance release ++ device_destroy(g_warp_drv.class, dev_data->cdev.dev); ++ ++ //cdev delete (fops) ++ cdev_del(&dev_data->cdev); ++ ++ //dev_data release ++ devm_kfree(&dev_data->pdev->dev, dev_data); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_suspend ++ * Platform device suspend handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static s32 warp_lxdrv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ warp_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ DEV_MSG(DEV_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_resume ++ * Platform device resume handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static s32 warp_lxdrv_resume(struct platform_device *pdev) ++{ ++ warp_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ DEV_MSG(DEV_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Data strucure for device driver ++//------------------------------------------------------------------------------------------------- ++static const struct of_device_id warp_lxdrv_match[] = { ++ { ++ .compatible = "sstar,infinity2-warp", ++ /*.data = NULL,*/ ++ }, ++ {}, ++}; ++ ++static struct platform_driver warp_lxdrv_driver = { ++ .probe = warp_lxdrv_probe, ++ .remove = warp_lxdrv_remove, ++ .suspend = warp_lxdrv_suspend, ++ .resume = warp_lxdrv_resume, ++ ++ .driver = { ++ .of_match_table = of_match_ptr(warp_lxdrv_match), ++ .name = "mstar_warp", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++/************************************************************************************************* ++ * warp_lxdrv_module_init ++ * module init function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++s32 warp_lxdrv_module_init(void) ++{ ++ s32 err; ++ dev_t dev; ++ ++ DEV_MSG(DEV_MSG_DBG, "Moudle Init\n"); ++ ++ // Allocate cdev id ++ err = alloc_chrdev_region(&dev, WARP_LXDRV_MINOR, WARP_LXDRV_DEVICE_COUNT, WARP_LXDRV_NAME); ++ if (err) ++ { ++ DEV_MSG(DEV_MSG_ERR, "Unable allocate cdev id\n"); ++ return err; ++ } ++ ++ g_warp_drv.major = MAJOR(dev); ++ g_warp_drv.minor_star = MINOR(dev); ++ g_warp_drv.reg_count = 0; ++ ++ // Register device class ++ g_warp_drv.class = class_create(THIS_MODULE, WARP_LXDRV_CLASS_NAME); ++ ++ if (IS_ERR(g_warp_drv.class)) ++ { ++ DEV_MSG(DEV_MSG_ERR, "Failed at class_create().Please exec [mknod] before operate the device\n"); ++ err = PTR_ERR(g_warp_drv.class); ++ goto ERR_RETURN_1; ++ } ++ ++ // Register platform driver ++ err = platform_driver_register(&warp_lxdrv_driver); ++ if (err != 0) ++ { ++ DEV_MSG(DEV_MSG_ERR, "Fail at platform_driver_register().\n"); ++ goto ERR_RETURN_2; ++ } ++ ++ DEV_MSG(DEV_MSG_DBG, "pass all warp_lxdrv_module_init function. \n"); ++ ++ return 0; ++ ++ERR_RETURN_2: ++ class_destroy(g_warp_drv.class); ++ ++ERR_RETURN_1: ++ unregister_chrdev_region(MKDEV(g_warp_drv.major, g_warp_drv.minor_star), WARP_LXDRV_DEVICE_COUNT); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * warp_lxdrv_module_exit ++ * module exit function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++void warp_lxdrv_module_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ DEV_MSG(DEV_MSG_DBG, "Modules Exit\n"); ++ ++ platform_driver_unregister(&warp_lxdrv_driver); ++ class_destroy(g_warp_drv.class); ++ unregister_chrdev_region(MKDEV(g_warp_drv.major, g_warp_drv.minor_star), WARP_LXDRV_DEVICE_COUNT); ++} ++ ++#if STAND_ALONE ++module_init(warp_lxdrv_module_init); ++module_exit(warp_lxdrv_module_exit); ++#endif ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("WARP ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/sstar/warp/drv/src/linux/warp_sample.c b/drivers/sstar/warp/drv/src/linux/warp_sample.c +new file mode 100755 +index 000000000000..0752a1464841 +--- /dev/null ++++ b/drivers/sstar/warp/drv/src/linux/warp_sample.c +@@ -0,0 +1,126 @@ ++#include ++#include ++#include ++#include ++#include "mhal_warp.h" ++#include "irqs.h" ++ ++ ++//the example for config ++//MHAL_WARP_CONFIG config = ++//{ ++// .op_mode = MHAL_WARP_OP_MODE_MAP, ++// .disp_table = {.resolution = MHAL_WARP_MAP_RESLOUTION_16X16, .format = MHAL_WARP_MAP_FORMAT_ABSOLUTE, .size = 263296, .absolute_table = NULL/*mi_3840x2160_disp_484x136_abs.bin*/}, ++// .bb_table = {.size = 816, .table = NULL /*bb_undist.bin.bin*/}, ++// .coeff = {0, 0, 0, 0, 0, 0, 0, 0, 0}, ++// .input_image = {.format = MHAL_WARP_IMAGE_FORMAT_YUV420, .width = 3840, .height = 2160}, ++// .input_data = {.num_planes = 2, .data[0] = NULL/*input Y buffer*/, .data[1] = NULL/*input UV buffer*/}, ++// .output_image = {.format = MHAL_WARP_IMAGE_FORMAT_YUV420, .width = 3840, .height = 2160}, ++// .output_data = {.num_planes = 2, .data[0] = NULL/*output Y buffer*/, .data[1] = NULL/*output UV buffer*/}, ++// .afbc_en = 0, ++// .fill_value = {0, 0x80}, ++// .axi_max_read_burst_size = 8, ++// .axi_max_write_burst_size = 8, ++// .axi_max_read_outstanding = 8, ++// .axi_max_write_outstanding = 8, ++// .debug_bypass_displacement_en = 0, ++// .debug_bypass_interp_en = 0, ++// .output_tiles_width = 160, ++// .output_tiles_height = 64, ++// .num_output_tiles = 816 ++//}; ++ ++irqreturn_t warp_sample_isr(s32 irq, void* data) ++{ ++ MHAL_WARP_DEV_HANDLE device = (MHAL_WARP_DEV_HANDLE*)data; ++ MHAL_WARP_ISR_STATE_E state; ++ ++ state = MHAL_WARP_IsrProc(device); ++ switch(state) ++ { ++ case MHAL_WARP_ISR_STATE_DONE: ++ return IRQ_HANDLED; ++ ++ default: ++ return IRQ_NONE; ++ } ++ ++ return IRQ_NONE; ++} ++ ++MS_BOOL warp_sample_callback(MHAL_WARP_INST_HANDLE instance, void *user_data) ++{ ++ struct semaphore *sema = (struct semaphore *)user_data; ++ ++ printk("callback is called\n"); ++ ++ up(sema); ++ ++ return 1; ++} ++ ++void warp_sample(MHAL_WARP_DEV_HANDLE device, MHAL_WARP_CONFIG* config) ++{ ++ MHAL_WARP_DEV_HANDLE local_device = device; ++ MHAL_WARP_INST_HANDLE instance; ++ struct semaphore sema; ++ s32 ret; ++ ++ sema_init(&sema, 0); ++ ++ // create a local device if caller does not pass a device ++ if (local_device == NULL) ++ { ++ ret = MHAL_WARP_CreateDevice(0, &local_device); ++ if (ret != MHAL_SUCCESS) ++ { ++ printk("can't create device!!\n"); ++ return; ++ } ++ ++ // Register a ISR ++ // irqs.h is for dtsi, c source has to add 32 if we use the define ++ ret = request_irq(INT_IRQ_78_WARP2RIU_INT+32, warp_sample_isr, IRQ_TYPE_LEVEL_HIGH, "warp isr", local_device); ++ if (ret != 0) ++ { ++ printk("can't request a irq\n"); ++ goto RETURN_0; ++ } ++ ++ } ++ ++ // create instance ++ ret = MHAL_WARP_CreateInstance(local_device, &instance); ++ if (ret != MHAL_SUCCESS) ++ { ++ printk("can't create instance!!\n"); ++ goto RETURN_1; ++ } ++ ++ // proce a image ++ ret = MHAL_WARP_Trigger(instance, config, warp_sample_callback, &sema); ++ if (ret != MHAL_SUCCESS) ++ { ++ printk("can't process image!!\n"); ++ goto RETURN_2; ++ } ++ ++ down(&sema); ++ ++ printk("process done\n"); ++ ++RETURN_2: ++ MHAL_WARP_DestroyInstance(instance); ++ ++RETURN_1: ++ if (local_device != device) ++ { ++ free_irq(INT_IRQ_78_WARP2RIU_INT, local_device); ++ } ++ ++RETURN_0: ++ if (local_device != device) ++ { ++ MHAL_WARP_DestroyDevice(local_device); ++ } ++} +diff --git a/drivers/sstar/warp/hal/inc/hal_debug.h b/drivers/sstar/warp/hal/inc/hal_debug.h +new file mode 100755 +index 000000000000..5fcbd47df134 +--- /dev/null ++++ b/drivers/sstar/warp/hal/inc/hal_debug.h +@@ -0,0 +1,38 @@ ++#ifndef __HAL_DEBUG_H__ ++#define __HAL_DEBUG_H__ ++ ++#include ++ ++// Defines debug message levels of HAL_MSG ++#define HAL_MSG_ERR 3 ++#define HAL_MSG_WRN 4 ++#define HAL_MSG_DBG 5 ++ ++#define HAL_MSG_LEVL HAL_MSG_WRN ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#define HAL_MSG_ENABLE // enable/disable message ++#define HAL_MSG_FUNC_ENABLE // enable/disable function name dump ++ ++#if defined(HAL_MSG_ENABLE) ++ ++#define HAL_STRINGIFY(x) #x ++#define HAL_TOSTRING(x) HAL_STRINGIFY(x) ++ ++#if defined(HAL_MSG_FUNC_ENABLE) ++#define HAL_MSG_TITLE "[HAL, %s] " ++#define HAL_MSG_FUNC __func__ ++#else // NOT defined(HAL_MSG_FUNC_ENABLE) ++#define HAL_MSG_TITLE "[HAL] %s" ++#define HAL_MSG_FUNC "" ++#endif // NOT defined(HAL_MSG_FUNC_ENABLE) ++ ++#define HAL_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= HAL_MSG_LEVL) { \ ++ printk(KERN_SOH HAL_TOSTRING(dbglv) HAL_MSG_TITLE _fmt, HAL_MSG_FUNC, ## _args); \ ++ } while(0) ++#else // NOT defined(HAL_MSG_ENABLE) ++#define HAL_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(HAL_MSG_ENABLE) ++ ++#endif // __HAL_DEBUG_H__ +diff --git a/drivers/sstar/warp/hal/pub/hal_ceva.h b/drivers/sstar/warp/hal/pub/hal_ceva.h +new file mode 100755 +index 000000000000..65fb37877e85 +--- /dev/null ++++ b/drivers/sstar/warp/hal/pub/hal_ceva.h +@@ -0,0 +1,86 @@ ++#ifndef HAL_CEVA_H ++#define HAL_CEVA_H ++ ++#include "hal_ceva_reg.h" ++#include ++ ++typedef enum ++{ ++ CEVA_HAL_XM6_PWR_DISABLE = 0x0, ++ CEVA_HAL_XM6_PWR_ENABLE = 0x1 ++} CEVA_HAL_XM6_PWR; ++ ++typedef enum ++{ ++ CEVA_HAL_RESET_WARP_SYS = 0x01, ++ CEVA_HAL_RESET_WARP_MIU = 0x02, ++ CEVA_HAL_RESET_WARP_MCU = 0x04, ++ CEVA_HAL_RESET_WARP_ALL = 0x07, ++} CEVA_HAL_RESET_WARP; ++ ++typedef enum ++{ ++ CEVA_HAL_IRQ_GVI = 0x00000001, // General Violation Indication ++ CEVA_HAL_IRQ_UOP = 0x00000002, // Undefined Opcode Interrupt ++ CEVA_HAL_IRQ_PI = 0x00000004, // Permission Interrupt ++ CEVA_HAL_IRQ_MAPV = 0x00000008, // Access Protection Violation ++ CEVA_HAL_IRQ_EDP_WDOG = 0x00000010, // EDP Watchdog Timeout ++ CEVA_HAL_IRQ_IOP_WDOG = 0x00000020, // I/O Port Watchdog Timeout ++ CEVA_HAL_IRQ_EPP_WDOG = 0x00000040, // EPP Watchdog timeout ++ CEVA_HAL_IRQ_SNOOP0 = 0x00000080, // Snooping Interrupt 0 ++ CEVA_HAL_IRQ_SNOOP1 = 0x00000100, // Snooping Interrupt 1 ++ CEVA_HAL_IRQ_MCCI_MES = 0x00000200, // Multicore Messaging Interface Interrupt ++ CEVA_HAL_IRQ_DDMA_DBG_MATCH = 0x00000400, // External Acknowledge for DDMA debug match ++ CEVA_HAL_IRQ_QMAN = 0x00008000, // QMAN Violation Indications Interrupt ++ CEVA_HAL_IRQ_WARP = 0x00001000, // WARP Accelerator Output Interrupt ++ CEVA_HAL_IRQ_MCCI_RD = 0x00002000, // Multicore Messaging Interface read indication ++ CEVA_HAL_IRQ_ISP2CEVA_INT = 0x00004000, // Interrupt Signal from MStar side = 0x0000, // such as timer interrpt ++ CEVA_HAL_IRQ_INT0 = 0x00010000, // XM6 Maskable interrupt 0 ++ CEVA_HAL_IRQ_INT1 = 0x00020000, // XM6 Maskable interrupt 1 ++ CEVA_HAL_IRQ_INT2 = 0x00040000, // XM6 Maskable interrupt 2 ++ CEVA_HAL_IRQ_INT3 = 0x00080000, // XM6 Maskable interrupt 3 ++ CEVA_HAL_IRQ_INT4 = 0x00100000, // XM6 Maskable interrupt 4 ++ CEVA_HAL_IRQ_BP = 0x00200000, // XM6 Emulation software interrupt / Breakpoint interrupt ++ CEVA_HAL_IRQ_NMI = 0x00400000, // XM6 Non-maskable interrupt ++ CEVA_HAL_IRQ_VINT = 0x00800000, // XM6 Vectored interrupt ++ CEVA_HAL_IRQ_TRP_SRV = 0x01000000, // XM6 Software interrupt ++ CEVA_HAL_IRQ_GPOUT_31 = 0x02000000, // XM6 General-purpose output pin 31 ++ CEVA_HAL_IRQ_OCM_GPOUT_3 = 0x04000000, // XM6 OCM General-purpose output pin 3 ++} CEVA_HAL_IRQ; ++ ++typedef enum ++{ ++ CEVA_HAL_IRQ_TARGET_ARM = 0, ++ CEVA_HAL_IRQ_TARGET_XM6_INT0 = 1, ++ CEVA_HAL_IRQ_TARGET_XM6_INT1 = 2, ++ CEVA_HAL_IRQ_TARGET_XM6_INT2 = 3, ++ CEVA_HAL_IRQ_TARGET_XM6_NMI = 4, ++ CEVA_HAL_IRQ_TARGET_XM6_VINT = 5, ++} CEVA_HAL_IRQ_TARGET; ++ ++typedef struct ++{ ++ phys_addr_t base_sys; ++ ceva_hal_reg_sys reg_sys; ++ ++ phys_addr_t base_axi2miu0; ++ ceva_hal_reg_bus reg_axi2miu0; ++ ++ phys_addr_t base_axi2miu1; ++ ceva_hal_reg_bus reg_axi2miu1; ++ ++ phys_addr_t base_axi2miu2; ++ ceva_hal_reg_bus reg_axi2miu2; ++ ++ phys_addr_t base_axi2miu3; ++ ceva_hal_reg_bus reg_axi2miu3; ++} ceva_hal_handle; ++ ++void ceva_hal_init(ceva_hal_handle *handle, phys_addr_t base_sys, phys_addr_t base_axi2miu0, phys_addr_t base_axi2miu1, phys_addr_t base_axi2miu2, phys_addr_t base_axi2miu3); ++void ceva_hal_enable_irq(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target, CEVA_HAL_IRQ irq); ++CEVA_HAL_IRQ ceva_hal_get_irq_status(ceva_hal_handle *handle); ++void ceva_hal_reset_warp(ceva_hal_handle *handle); ++void ceva_hal_enable_warp(ceva_hal_handle *handle); ++void ceva_hal_set_axi2miu(ceva_hal_handle *handle); ++ ++#endif // HAL_CEVA_H +diff --git a/drivers/sstar/warp/hal/pub/hal_ceva_reg.h b/drivers/sstar/warp/hal/pub/hal_ceva_reg.h +new file mode 100755 +index 000000000000..1e52c5365792 +--- /dev/null ++++ b/drivers/sstar/warp/hal/pub/hal_ceva_reg.h +@@ -0,0 +1,2342 @@ ++#ifndef __HAL_CEVA_REG_H__ ++#define __HAL_CEVA_REG_H__ ++ ++#include ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_forbidden:1; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_div_num_bus:4; ++ u16 reg_div_num_wdog:4; ++ u16 reg_div_num_warp:4; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rstz_ceva_core:1; ++ u16 reg_rstz_ceva_sys:1; ++ u16 reg_rstz_ceva_ocem:1; ++ u16 reg_rstz_ceva_global:1; ++ u16 reg_rstz_miu:1; ++ u16 reg_rstz_mcu:1; ++ u16 reg_rstz_mcu2ceva:1; ++ u16 reg_rstz_isp2ceva:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva2riu_int_en:16; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva2riu_int_en2:16; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_int0_en:16; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_int1_en:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_int2_en:16; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_nmi_en:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_vint_en:16; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_uop_int_wc:1; ++ }; ++ u16 reg0a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_wc_low:16; ++ }; ++ u16 reg0b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_wc_high:16; ++ }; ++ u16 reg0c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_ind_low:16; ++ }; ++ u16 reg0d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcci_rd_ind_high:16; ++ }; ++ u16 reg0e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_warp_r1_sel:1; ++ u16 reg_warp_r2_sel:1; ++ u16 reg_warp_w1_sel:1; ++ u16 reg_warp_w1_sel2:1; ++ u16 reg_rq_mask_miu:4; ++ u16 reg_rq_mask_imi:4; ++ }; ++ u16 reg0f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_dbus_low:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_dbus_high:8; ++ u16 reg_ceva_dbus_sel:8; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clktest_in:8; ++ u16 reg_clktest_out:8; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva2mcu_ldz_en:1; ++ u16 reg_ceva2isp_ldz_en:1; ++ u16 reg_ceva_eflag_wc:1; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mi02ceva_last_done_z:1; ++ u16 reg_mi12ceva_last_done_z:1; ++ u16 reg_mi22ceva_last_done_z:1; ++ u16 reg_mi32ceva_last_done_z:1; ++ u16 reg_imi02ceva_last_done_z:1; ++ u16 reg_imi12ceva_last_done_z:1; ++ u16 reg_imi22ceva_last_done_z:1; ++ u16 reg_imi32ceva_last_done_z:1; ++ u16 reg_ceva2mcu_last_done_z:1; ++ u16 reg_ceva2isp_last_done_z:1; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_boot:1; ++ u16 reg_ceva_csysreq:1; ++ u16 reg_ceva_core_rcvr:1; ++ u16 reg_ceva_external_wait:1; ++ u16 reg_ceva_mcache_invalidate_strap:1; ++ u16 reg_ceva_acu_lock:1; ++ u16 reg_ceva_acu_slv_acc:1; ++ u16 reg_ceva_ddma_dbg_match_ack:1; ++ u16 reg_ceva_next_ddma:1; ++ u16 reg_ceva_bs_reg_tdo:1; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_vector_low:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_vector_high:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_is:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_is2:16; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_psu_dsp_idle:1; ++ u16 reg_ceva_psu_core_idle:1; ++ u16 reg_ceva_psu_core_wait:1; ++ u16 reg_ceva_psu_cactive:1; ++ u16 reg_ceva_psu_csysack:1; ++ u16 reg_ceva_epp_aps:1; ++ u16 reg_ceva_iop_aps:1; ++ u16 reg_ceva_edp_aps:1; ++ }; ++ u16 reg1a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_ocm_gp_out:4; ++ u16 reg_ceva_ocm_jtag_state:4; ++ u16 reg_ceva_ocm_core_rst:1; ++ u16 reg_ceva_ocm_debug:1; ++ u16 reg_ceva_cverbit:1; ++ u16 reg_ceva_seq_eotbit:1; ++ u16 reg_ceva_seq_om:2; ++ }; ++ u16 reg1b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpin_low:16; ++ }; ++ u16 reg1c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpin_high:16; ++ }; ++ u16 reg1d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpout_low:16; ++ }; ++ u16 reg1e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_ceva_gpout_high:16; ++ }; ++ u16 reg1f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_qman_desc_en:8; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_xiu_be_err:1; ++ u16 reg_ceva2mcu_bresp:1; ++ u16 reg_ceva2mcu_rresp:1; ++ u16 reg_ceva2mcu_wstrb:1; ++ u16 reg_ceva2isp_bresp:1; ++ u16 reg_ceva2isp_rresp:1; ++ u16 reg_ceva2isp_wstrb:1; ++ u16 reg_epp_awlen:1; ++ u16 reg_epp_arlen:1; ++ u16 reg_edp_awlen:1; ++ u16 reg_edp_arlen:1; ++ u16 reg_axir1_arlen:1; ++ u16 reg_axir2_arlen:1; ++ u16 reg_axiw1_awlen:1; ++ u16 reg_apb_pslverr:1; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_axi_maxlen:8; ++ u16 reg_ceva_apbs_paddr:3; ++ u16 reg_ceva_jt_ap:1; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_forbidden_1:1; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rstz_warp:3; ++ }; ++ u16 reg42; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_warp2cmdq_trig_en:16; ++ }; ++ u16 reg43; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_warp2cmdq_trig_en2:16; ++ }; ++ u16 reg44; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_0:16; ++ }; ++ u16 reg60; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_1:16; ++ }; ++ u16 reg61; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_2:16; ++ }; ++ u16 reg62; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_3:16; ++ }; ++ u16 reg63; ++ }; ++ ++}ceva_hal_reg_sys; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg0b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg0c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg0d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg0e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg0f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg1a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg1b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg1c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg1d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg1e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg1f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg26; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg37; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg38; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg3a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg3b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg3c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg3d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg3e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg3f; ++ }; ++#if 1 ++}ceva_hal_reg_bus; ++#else ++// Maybe we can use a single structure for all axi2miu buses, maybe not... ++}ceva_hal_reg_bus_axi2miu0; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg41; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg42; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg43; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg44; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg45; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg46; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg47; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg48; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg49; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg4b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg4c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg4d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg4e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg4f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg50; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg51; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg52; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg53; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg54; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg55; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg56; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg57; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg58; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg59; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg5a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg5b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg5c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg5d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg5e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg5f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg60; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg61; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg62; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg63; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg64; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg65; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg66; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg77; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg78; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg7a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg7b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg7c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg7d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg7e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg7f; ++ }; ++}ceva_hal_reg_bus_axi2miu1; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg0b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg0c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg0d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg0e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg0f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg1a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg1b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg1c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg1d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg1e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg1f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg26; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg37; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg38; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg3a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg3b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg3c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg3d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg3e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg3f; ++ }; ++}ceva_hal_reg_bus_axi2miu2; ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 reg_uncache_no_pack_miu0_en:1; ++ u16 reg_uncache_no_pack_imi_en:1; ++ u16 reg_w_pack_always_no_hit_miu0:1; ++ u16 reg_w_pack_always_no_hit_imi:1; ++ u16 reg_w_always_flush_miu0:1; ++ u16 reg_w_always_flush_imi:1; ++ u16 reg_miu_access_mode:1; ++ u16 reg_l3_dynamic_gat_en:1; ++ u16 reg_l3_clk_latency:2; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_max_miu0:7; ++ u16 reg_clk_miu2x_sel:1; ++ u16 reg_mcu_req_max_imi:7; ++ u16 reg_wriu_32b_en:1; ++ }; ++ u16 reg41; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_mcu_req_prior_miu0:6; ++ u16 reg_clk_miu2x_en_switch:1; ++ u16 reg_clk_miu1x_en_switch:1; ++ u16 reg_mcu_req_prior_imi:6; ++ u16 reg_clk_miu2x_switch_bypass_waiting:1; ++ }; ++ u16 reg42; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_w_pack_timeout:16; ++ }; ++ u16 reg43; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_44:16; ++ }; ++ u16 reg44; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy_45:16; ++ }; ++ u16 reg45; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_timeout_cnt:16; ++ }; ++ u16 reg46; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_status_clear:1; ++ u16 reg_ro_resp_flag_ms0:2; ++ u16 reg_ro_resp_flag_ms1:2; ++ u16 reg_req_wait_cyc:4; ++ u16 reg_acp_req_mask:1; ++ }; ++ u16 reg47; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_low:16; ++ }; ++ u16 reg48; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_debug_port_out_high:8; ++ u16 reg_debug_port_sel:3; ++ }; ++ u16 reg49; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testout_sel:2; ++ u16 reg_ca9miu_strb_inv:1; ++ }; ++ u16 reg4b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_low:16; ++ }; ++ u16 reg4c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_debug_high:16; ++ }; ++ u16 reg4d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_acp_pack_timeout:4; ++ u16 reg_acp_idle:1; ++ }; ++ u16 reg4e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_testbus_en:1; ++ u16 reg_ckg_alldft:1; ++ u16 reg_ro_miucmd_come_before_set_miu2x:1; ++ u16 reg_ro_clk_miu2x_state:2; ++ }; ++ u16 reg4f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_0:16; ++ }; ++ u16 reg50; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_1:16; ++ }; ++ u16 reg51; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_2:16; ++ }; ++ u16 reg52; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_3:16; ++ }; ++ u16 reg53; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_4:16; ++ }; ++ u16 reg54; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_5:16; ++ }; ++ u16 reg55; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_6:16; ++ }; ++ u16 reg56; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_force_axi_rd_7:16; ++ }; ++ u16 reg57; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_dummy50_ro:16; ++ }; ++ u16 reg58; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_security_oneway_prot:1; ++ u16 reg_rom_memory_en:1; ++ u16 reg_rom_lightsleep:1; ++ u16 reg_rom_shutdown:1; ++ u16 reg_hemcu_iso_ctrl:2; ++ }; ++ u16 reg59; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w:1; ++ u16 reg_map_nodefine_hit_r:1; ++ u16 reg_rxiu_nodefine_hit:1; ++ u16 reg_rxiu_timeout_int:1; ++ }; ++ u16 reg5a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_low:16; ++ }; ++ u16 reg5b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_w_addr_high:16; ++ }; ++ u16 reg5c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_low:16; ++ }; ++ u16 reg5d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_map_nodefine_hit_r_addr_high:16; ++ }; ++ u16 reg5e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_low:16; ++ }; ++ u16 reg5f; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_nodefine_hit_addr_high:16; ++ }; ++ u16 reg60; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_low:16; ++ }; ++ u16 reg61; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rxiu_timeout_adr_high:16; ++ }; ++ u16 reg62; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nodefine_hit_clear:1; ++ }; ++ u16 reg63; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_enable:1; ++ u16 reg_protect_area_offset_start:4; ++ u16 reg_protect_area_offset_end:4; ++ }; ++ u16 reg64; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_low:16; ++ }; ++ u16 reg65; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_protect_area_base_high:10; ++ }; ++ u16 reg66; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_pcie_noe_flush_en:1; ++ u16 reg_pcie_wflush_en:1; ++ }; ++ u16 reg77; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riu_s2:4; ++ u16 reg_c_riu_s0:4; ++ u16 reg_c_delayriu_w_pulse:1; ++ u16 reg_c_resetbridge:1; ++ u16 reg_c_resetmcu:1; ++ }; ++ u16 reg78; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_riurwtimeout:16; ++ }; ++ u16 re79; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_c_maskint:1; ++ u16 reg_c_forceint:1; ++ }; ++ u16 reg7a; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_nonbuf_always_flush:1; ++ }; ++ u16 reg7b; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_keep_write_pcie_miu_order:1; ++ }; ++ u16 reg7c; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_rom_tc:4; ++ u16 reg_rom_pd:1; ++ u16 reg_rom_cs:1; ++ }; ++ u16 reg7d; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_64b_wful_on:1; ++ u16 reg_fpkfifo_no_merge:1; ++ }; ++ u16 reg7e; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_clear_crossdie:1; ++ }; ++ u16 reg7f; ++ }; ++}ceva_hal_reg_bus_axi2miu3; ++#endif ++#endif // __HAL_CEVA_REG_H__ +diff --git a/drivers/sstar/warp/hal/pub/hal_clk.h b/drivers/sstar/warp/hal/pub/hal_clk.h +new file mode 100755 +index 000000000000..fd5366d16b19 +--- /dev/null ++++ b/drivers/sstar/warp/hal/pub/hal_clk.h +@@ -0,0 +1,8 @@ ++#ifndef HAL_CLK_H ++#define HAL_CLK_H ++ ++#include "ms_platform.h" ++#include ++int clk_hal_init(void); ++ ++#endif +diff --git a/drivers/sstar/warp/hal/pub/hal_warp.h b/drivers/sstar/warp/hal/pub/hal_warp.h +new file mode 100755 +index 000000000000..3077027561db +--- /dev/null ++++ b/drivers/sstar/warp/hal/pub/hal_warp.h +@@ -0,0 +1,36 @@ ++#ifndef _HAL_WARP_H_ ++#define _HAL_WARP_H_ ++ ++#include "hal_warp_reg.h" ++#include "hal_warp_data.h" ++ ++#include ++ ++#define AXI_MAX_WRITE_BURST_SIZE (16) ++#define AXI_MAX_READ_BURST_SIZE (16) ++#define AXI_MAX_WRITE_OUTSTANDING (16) ++#define AXI_MAX_READ_OUTSTANDING (16) ++ ++#define DEBUG_BYPASS_DISPLACEMENT_EN (0) ++#define DEBUG_BYPASS_INTERP_EN (0) ++ ++typedef struct ++{ ++ phys_addr_t base_addr; ++ warp_hal_reg_bank reg_bank; ++ ++} warp_hal_handle; ++ ++void warp_hal_set_axi(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++void warp_hal_set_image_point(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++void warp_hal_set_image_size(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++void warp_hal_set_output_tile(warp_hal_handle* handle, u16 tile_w, u16 tile_h); ++void warp_hal_set_disp(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++ void warp_hal_set_bb(warp_hal_handle* handle, s32 table_addr); ++void warp_hal_set_pers_matirx(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++void warp_hal_set_out_of_range(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++void warp_hal_set_config(warp_hal_handle* handle, HAL_WARP_CONFIG* config); ++void warp_hal_get_hw_status(warp_hal_handle* handle); ++void warp_hal_init(warp_hal_handle *handle, phys_addr_t base_addr); ++ ++#endif //_HAL_WARP_H_ +diff --git a/drivers/sstar/warp/hal/pub/hal_warp_data.h b/drivers/sstar/warp/hal/pub/hal_warp_data.h +new file mode 100755 +index 000000000000..ca627641c8e1 +--- /dev/null ++++ b/drivers/sstar/warp/hal/pub/hal_warp_data.h +@@ -0,0 +1,144 @@ ++#ifndef _HAL_WARP_DATA_H_ ++#define _HAL_WARP_DATA_H_ ++ ++#include ++ ++/// @brief MHAL WARP operation modes enumeration ++typedef enum ++{ ++ HAL_WARP_OP_MODE_PERSPECTIVE = 0, ++ HAL_WARP_OP_MODE_MAP = 1 ++} HAL_WARP_OP_MODE_E; ++ ++/// @brief MHAL WARP image formats enumeration ++typedef enum ++{ ++ HAL_WARP_IMAGE_FORMAT_RGBA = 0, ++ HAL_WARP_IMAGE_FORMAT_YUV422 = 1, ++ HAL_WARP_IMAGE_FORMAT_YUV420 = 2 ++} HAL_WARP_IMAGE_FORMAT_E; ++ ++/// @brief MHAL WARP perspective coefficients enumeration ++typedef enum ++{ ++ HAL_WARP_PERSECTIVE_COEFFS_C00 = 0, ++ HAL_WARP_PERSECTIVE_COEFFS_C01 = 1, ++ HAL_WARP_PERSECTIVE_COEFFS_C02 = 2, ++ HAL_WARP_PERSECTIVE_COEFFS_C10 = 3, ++ HAL_WARP_PERSECTIVE_COEFFS_C11 = 4, ++ HAL_WARP_PERSECTIVE_COEFFS_C12 = 5, ++ HAL_WARP_PERSECTIVE_COEFFS_C20 = 6, ++ HAL_WARP_PERSECTIVE_COEFFS_C21 = 7, ++ HAL_WARP_PERSECTIVE_COEFFS_C22 = 8, ++ HAL_WARP_PERSECTIVE_COEFFS_NUM_COEFFS = 9 ++} HAL_WARP_PERSECTIVE_COEFFS_E; ++ ++/// @brief MHAL WARP displacement map resolution enumeration ++typedef enum ++{ ++ HAL_WARP_MAP_RESLOUTION_8X8 = 0, ++ HAL_WARP_MAP_RESLOUTION_16X16 = 1 ++} HAL_WARP_MAP_RESLOUTION_E; ++ ++/// @brief MHAL WARP displacement map format enumeration ++typedef enum ++{ ++ HAL_WARP_MAP_FORMAT_ABSOLUTE = 0, ++ HAL_WARP_MAP_FORMAT_RELATIVE = 1 ++} HAL_WARP_MAP_FORMAT_E; ++ ++/// @brief WARP image plane index enumeration ++typedef enum ++{ ++ HAL_WARP_IMAGE_PLANE_RGBA = 0, ++ HAL_WARP_IMAGE_PLANE_Y = 0, ++ HAL_WARP_IMAGE_PLANE_UV = 1 ++} HAL_WARP_IMAGE_PLANE_E; ++ ++typedef enum ++{ ++ HAL_WARP_INSTANCE_STATE_READY = 0, ++ HAL_WARP_INSTANCE_STATE_PROCESSING = 1, ++ HAL_WARP_INSTANCE_STATE_DONE = 2, ++ HAL_WARP_INSTANCE_STATE_AXI_ERROR = 3, ++ HAL_WARP_INSTANCE_STATE_PROC_ERROR = 4 ++} HAL_WARP_INSTANCE_STATE_E; ++ ++typedef enum ++{ ++ HAL_WARP_ISR_STATE_DONE = 0, ++ HAL_WARP_ISR_STATE_PROCESSING = 1 ++} HAL_WARP_ISR_STATE_E; ++ ++/// @brief MHAL WARP displacement map entry for absolute coordinates format ++typedef struct ++{ ++ s32 y; ++ s32 x; ++} HAL_WARP_DISPPLAY_ABSOLUTE_ENTRY_T; ++ ++/// @brief MHAL WARP displacement map entry for coordinates' relative offset format ++typedef struct ++{ ++ s16 y; ++ s16 x; ++} HAL_WARP_DISPPLAY_RELATIVE_ENTRY_T; ++ ++/// @brief MHAL WARP displacement table descriptor ++typedef struct ++{ ++ HAL_WARP_MAP_RESLOUTION_E resolution; // map resolution ++ HAL_WARP_MAP_FORMAT_E format; // map format (absolute, relative) ++ s32 size; // size of Disp. ++ u64 table; ++} HAL_WARP_DISPLAY_TABLE_T; ++ ++typedef struct ++{ ++ s16 height; // input tile height ++ s16 width; // input tile width ++ s16 y; // input tile top left y coordinate ++ s16 x; // input tile top left x coordinate ++} HAL_WARP_BOUND_BOX_ENTRY_T; ++ ++typedef struct ++{ ++ s32 size; // number of bound boxes ++ u64 table; // list of all bound boxes ++}HAL_WARP_BOUND_BOX_TABLE_T; ++ ++/// @brief MHAL WARP image descriptor ++typedef struct ++{ ++ HAL_WARP_IMAGE_FORMAT_E format; // image format ++ u32 width; // image width (for YUV - Y plane width) ++ u32 height; // image height (for YUV - Y plane width) ++} HAL_WARP_IMAGE_DESC_T; ++ ++/// @brief MHAL WARP image data structure ++typedef struct ++{ ++ u32 num_planes; // number of image planes ++ u64 data[2]; // pointers to the image planes' data ++} HAL_WARP_IMAGE_DATA_T; ++ ++/// @brief MHAL WARP hardware configuration structure ++typedef struct ++{ ++ HAL_WARP_OP_MODE_E op_mode; // Operation mode ++ HAL_WARP_DISPLAY_TABLE_T disp_table; // Displacement table descriptor ++ HAL_WARP_BOUND_BOX_TABLE_T bb_table; // Bounding box table descriptor ++ ++ int coeff[HAL_WARP_PERSECTIVE_COEFFS_NUM_COEFFS]; // Perspective transform coefficients ++ ++ HAL_WARP_IMAGE_DESC_T input_image; // Input image ++ HAL_WARP_IMAGE_DATA_T input_data; ++ ++ HAL_WARP_IMAGE_DESC_T output_image; // Output image ++ HAL_WARP_IMAGE_DATA_T output_data; ++ ++ u8 fill_value[2]; // Fill value for out of range pixels ++ ++} HAL_WARP_CONFIG; ++ ++#endif //_HAL_WARP_DATA_H_ +diff --git a/drivers/sstar/warp/hal/pub/hal_warp_reg.h b/drivers/sstar/warp/hal/pub/hal_warp_reg.h +new file mode 100755 +index 000000000000..8309aaf8fcf9 +--- /dev/null ++++ b/drivers/sstar/warp/hal/pub/hal_warp_reg.h +@@ -0,0 +1,180 @@ ++#ifndef __HAL_WARP_REG_H__ ++#define __HAL_WARP_REG_H__ ++ ++//#define WARP_BASE (0x0) ++#define REG_ADDR(a) (uint)(a)//(uint*)(WARP_BASE + (a)) ++ ++#define WARP_CTL_REG_ADDR REG_ADDR(0x00) ++#define WARP_STA_REG_ADDR REG_ADDR(0x04) ++#define WARP_AXI_CFG1_REG_ADDR REG_ADDR(0x08) ++#define WARP_AXI_CFG2_REG_ADDR REG_ADDR(0x0C) ++#define WARP_DLUA_YRGB_REG_ADDR REG_ADDR(0x10) ++#define WARP_DLUA_UV_REG_ADDR REG_ADDR(0x14) ++#define WARP_DLUA_VB_REG_ADDR REG_ADDR(0x18) ++#define WARP_CDLA_REG_ADDR REG_ADDR(0x1C) ++#define WARP_DSUA_YRGB_REG_ADDR REG_ADDR(0x20) ++#define WARP_DSUA_UV_REG_ADDR REG_ADDR(0x24) ++#define WARP_DSUA_VB_REG_ADDR REG_ADDR(0x28) ++#define WARP_CDSA_REG_ADDR REG_ADDR(0x2C) ++#define WARP_OCS_REG_ADDR REG_ADDR(0x30) ++#define WARP_OCSNUM_REG_ADDR REG_ADDR(0x34) ++#define WARP_IFSZ_REG_ADDR REG_ADDR(0x38) ++#define WARP_OFSZ_REG_ADDR REG_ADDR(0x3C) ++#define WARP_DISTBA_REG_ADDR REG_ADDR(0x40) ++#define WARP_BBA_REG_ADDR REG_ADDR(0x44) ++#define WARP_PDC_C00_REGS_ADDR REG_ADDR(0x48) ++#define WARP_PDC_C01_REGS_ADDR REG_ADDR(0x4C) ++#define WARP_PDC_C02_REGS_ADDR REG_ADDR(0x50) ++#define WARP_PDC_C10_REGS_ADDR REG_ADDR(0x54) ++#define WARP_PDC_C11_REGS_ADDR REG_ADDR(0x58) ++#define WARP_PDC_C12_REGS_ADDR REG_ADDR(0x5C) ++#define WARP_PDC_C20_REGS_ADDR REG_ADDR(0x60) ++#define WARP_PDC_C21_REGS_ADDR REG_ADDR(0x64) ++#define WARP_PDC_C22_REGS_ADDR REG_ADDR(0x68) ++#define WARP_PDOFFSET_REG_ADDR REG_ADDR(0x6C) ++#define WARP_CSFV_REG_ADDR REG_ADDR(0x70) ++ ++typedef struct { ++ int go : 1; ++ int reserved1 : 1; ++ int dispm : 1; ++ int dxym : 1; ++ int afbcm : 1; ++ int eofie : 1; ++ int oie : 1; ++ int reserved2 : 1; ++ int axierie : 1; ++ int dtibsz : 2; ++ int reserved3 : 2; ++ int iif : 3; ++ int bpdu : 1; ++ int bpiu : 1; ++ int reserved4 :14; ++} wrp_ctl_reg_bits_t; ++ ++typedef union ++{ ++ wrp_ctl_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_ctl_t; ++ ++typedef struct { ++ unsigned int idle : 1; ++ unsigned int oc : 1; ++ unsigned int reserved1 : 1; ++ unsigned int axierr : 1; ++ unsigned int reserved2 :12; ++ unsigned int version : 8; ++ unsigned int id : 8; ++} wrp_sta_reg_bits_t; ++ ++typedef union ++{ ++ wrp_sta_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_sta_t; ++ ++typedef struct { ++ char reserved1; ++ unsigned char rrc_c; ++ unsigned char wrc; ++ unsigned char rrc; ++} wrp_axi_cfg1_reg_bits_t; ++ ++typedef union ++{ ++ wrp_axi_cfg1_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_axi_cfg1_t; ++ ++typedef struct { ++ unsigned char mwb; ++ unsigned char mrb; ++ unsigned char moutstw; ++ unsigned char moutstr; ++} wrp_axi_cfg2_reg_bits_t; ++ ++typedef union ++{ ++ wrp_axi_cfg2_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_axi_cfg2_t; ++ ++typedef struct { ++ unsigned short ocsx; ++ unsigned short ocsy; ++} wrp_ocs_reg_bits_t; ++ ++typedef union ++{ ++ wrp_ocs_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_ocs_t; ++ ++typedef struct { ++ unsigned short ifszx; ++ unsigned short ifszy; ++} wrp_ifsz_reg_bits_t; ++ ++typedef union ++{ ++ wrp_ifsz_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_ifsz_t; ++ ++typedef struct { ++ unsigned short ofszx; ++ unsigned short ofszy; ++} wrp_ofsz_reg_bits_t; ++ ++typedef union ++{ ++ wrp_ofsz_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_ofsz_t; ++ ++typedef struct { ++ unsigned char yfv_rgbfv; ++ unsigned char uvfv; ++ unsigned short reserved; ++} wrp_csfv_reg_bits_t; ++ ++typedef union ++{ ++ wrp_csfv_reg_bits_t fields; ++ unsigned int overlay; ++} wrp_csfv_t; ++ ++typedef struct ++{ ++ wrp_ctl_t ctl; //0x00, WRP_CTL ++ wrp_sta_t sta; //0x04, WRP_STA ++ wrp_axi_cfg1_t axi_cfg1; //0x08, AXI_CFG1 ++ wrp_axi_cfg2_t axi_cfg2; //0x0C, AXI_CFG2 ++ int dlua_yrgb; //0x10, DLUA_YRGB ++ int dlua_uvg; //0x14, DLUA_UV ++ int cdla; //0x1C, CDLA ++ int dsua_yrgb; //0x20, DSUA_YRGB ++ int dsua_uvg; //0x24, DSUA_UV ++ int dsua_vb; ++ int cdsa; //0x2C, CDSA ++ wrp_ocs_t ocs; //0x30, OCS ++ int ocsnum; ++ wrp_ifsz_t ifsz; //0x38, IFSZ ++ wrp_ofsz_t ofsz; //0x3C, OFSZ ++ int distba; //0x40, DUSTBA ++ int bba; //0x44, BBA ++ int c00; //0x48, PDC_C00 ++ int c01; //0x4C, PDC_C01 ++ int c02; //0x50, PDC_C02 ++ int c10; //0x54, PDC_C10 ++ int c11; //0x58, PDC_C11 ++ int c12; //0x5C, PDC_C12 ++ int c20; //0x60, PDC_C20 ++ int c21; //0x64, PDC_C21 ++ int c22; //0x68, PDC_C22 ++ wrp_csfv_t csfv; //0x70, CSFV ++ ++} warp_hal_reg_bank; ++ ++#endif // __HAL_WARP_REG_H__ +diff --git a/drivers/sstar/warp/hal/src/hal_ceva.c b/drivers/sstar/warp/hal/src/hal_ceva.c +new file mode 100755 +index 000000000000..f023ed50bba3 +--- /dev/null ++++ b/drivers/sstar/warp/hal/src/hal_ceva.c +@@ -0,0 +1,145 @@ ++#include "hal_ceva.h" ++#include "hal_debug.h" ++ ++#include "ms_platform.h" ++#include ++ ++// #define ENABLE_JTAG ++ ++#ifdef ENABLE_JTAG ++#define RIU_BASE_ADDR (0x1F000000) ++#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR)) ++#define BANK_GOP (BANK_CAL(0x1026)) ++#endif // ENABLE_JTAG ++ ++#define LOW_U16(value) (((u32)(value))&0x0000FFFF) ++#define HIGH_U16(value) ((((u32)(value))&0xFFFF0000)>>16) ++ ++#define MAKE_U32(high, low) ((((u32)high)<<16) | low) ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++void ceva_hal_init(ceva_hal_handle *handle, phys_addr_t base_sys, phys_addr_t base_axi2miu0, phys_addr_t base_axi2miu1, phys_addr_t base_axi2miu2, phys_addr_t base_axi2miu3) ++{ ++ HAL_MSG(HAL_MSG_DBG, "init 0x%p, 0x%X, 0x%X, 0x%X, 0x%X, 0x%X\n", handle, base_sys, base_axi2miu0, base_axi2miu1, base_axi2miu2, base_axi2miu3); ++ ++ memset(handle, 0, sizeof(ceva_hal_handle)); ++ handle->base_sys = base_sys; ++ handle->base_axi2miu0 = base_axi2miu0; ++ handle->base_axi2miu1 = base_axi2miu1; ++ handle->base_axi2miu2 = base_axi2miu2; ++ handle->base_axi2miu3 = base_axi2miu3; ++} ++ ++void ceva_hal_enable_irq(ceva_hal_handle *handle, CEVA_HAL_IRQ_TARGET target, CEVA_HAL_IRQ irq) ++{ ++ u16 irq0 = LOW_U16(irq); ++ u16 irq1 = HIGH_U16(irq); ++ ++ switch(target) ++ { ++ case CEVA_HAL_IRQ_TARGET_ARM: ++ handle->reg_sys.reg03 = REGR(handle->base_sys, 0x03); ++ handle->reg_sys.reg_ceva2riu_int_en |= irq0; ++ REGW(handle->base_sys, 0x03, handle->reg_sys.reg03); ++ ++ handle->reg_sys.reg04 = REGR(handle->base_sys, 0x04); ++ handle->reg_sys.reg_ceva2riu_int_en2 |= irq1; ++ REGW(handle->base_sys, 0x04, handle->reg_sys.reg04); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT0: ++ handle->reg_sys.reg05 = REGR(handle->base_sys, 0x05); ++ handle->reg_sys.reg_ceva_int0_en |= irq0; ++ REGW(handle->base_sys, 0x05, handle->reg_sys.reg05); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT1: ++ handle->reg_sys.reg06 = REGR(handle->base_sys, 0x06); ++ handle->reg_sys.reg_ceva_int1_en |= irq0; ++ REGW(handle->base_sys, 0x06, handle->reg_sys.reg06); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_INT2: ++ handle->reg_sys.reg07 = REGR(handle->base_sys, 0x07); ++ handle->reg_sys.reg_ceva_int2_en |= irq0; ++ REGW(handle->base_sys, 0x07, handle->reg_sys.reg07); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_NMI: ++ handle->reg_sys.reg08 = REGR(handle->base_sys, 0x08); ++ handle->reg_sys.reg_ceva_nmi_en |= irq0; ++ REGW(handle->base_sys, 0x08, handle->reg_sys.reg08); ++ break; ++ ++ case CEVA_HAL_IRQ_TARGET_XM6_VINT: ++ handle->reg_sys.reg09 = REGR(handle->base_sys, 0x09); ++ handle->reg_sys.reg_ceva_vint_en |= irq0; ++ REGW(handle->base_sys, 0x09, handle->reg_sys.reg09); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++CEVA_HAL_IRQ ceva_hal_get_irq_status(ceva_hal_handle *handle) ++{ ++ u32 irq; ++ ++ handle->reg_sys.reg18 = REGR(handle->base_sys, 0x18); ++ handle->reg_sys.reg19 = REGR(handle->base_sys, 0x19); ++ irq = MAKE_U32(handle->reg_sys.reg_ceva_is2, handle->reg_sys.reg_ceva_is); ++ ++ return irq; ++} ++ ++void ceva_hal_reset_warp(ceva_hal_handle *handle) ++{ ++ ++ handle->reg_sys.reg_rstz_warp = 0; // ~CEVA_HAL_RESET_WARP_ALL ++ REGW(handle->base_sys, 0x42, handle->reg_sys.reg42); ++ ++ // delay 1us ++ udelay(1); ++} ++ ++void ceva_hal_enable_warp(ceva_hal_handle *handle) ++{ ++ handle->reg_sys.reg_rstz_warp = 0; ++ REGW(handle->base_sys, 0x42, handle->reg_sys.reg42); ++ ++ // delay 1us ++ udelay(1); ++ ++ // handle->reg_sys.reg_rstz_warp = 0xFFFF; ++ handle->reg_sys.reg42 = CEVA_HAL_RESET_WARP_ALL; ++ REGW(handle->base_sys, 0x42, handle->reg_sys.reg42); ++ ++ // delay 1us ++ udelay(1); ++} ++ ++void ceva_hal_set_axi2miu(ceva_hal_handle *handle) ++{ ++ unsigned short axi2miu2_data = 0; ++ unsigned short axi2miu3_data = 0; ++ ++ axi2miu2_data = REGR(handle->base_axi2miu2, 0x02); ++ axi2miu3_data = REGR(handle->base_axi2miu3, 0x02); ++ ++ axi2miu2_data = axi2miu2_data | 0x0001; ++ axi2miu3_data = axi2miu3_data | 0x0001; ++ ++ REGW(handle->base_axi2miu2, 0x02, axi2miu2_data); ++ REGW(handle->base_axi2miu3, 0x02, axi2miu2_data); ++ ++ REGW(handle->base_axi2miu2, 0x01, 0x4040); ++ REGW(handle->base_axi2miu3, 0x01, 0x4040); ++} +diff --git a/drivers/sstar/warp/hal/src/hal_clk.c b/drivers/sstar/warp/hal/src/hal_clk.c +new file mode 100755 +index 000000000000..b07fdb8ab743 +--- /dev/null ++++ b/drivers/sstar/warp/hal/src/hal_clk.c +@@ -0,0 +1,67 @@ ++#include "hal_clk.h" ++#include "hal_debug.h" ++ ++#define RIU_BASE_ADDR (0x1F000000) ++#define BANK_CAL(addr) ((addr<<9) + (RIU_BASE_ADDR)) ++ ++#define BANK_TOP_RESET (BANK_CAL(0x101e)) ++#define BANK_TOP_CLK (BANK_CAL(0x112a)) ++#define BANK_WD_EN (BANK_CAL(0x1410)) ++#define BANK_PLL (BANK_CAL(0x162e)) ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++/******************************************************************************************************************* ++ * clk_hal_init ++ * init device clock ++ * ++ * Parameters: ++ * RIU_BASE_ADDR: clock base address ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++////CEVA PLL: 600MHz setting ++int clk_hal_init(void) ++{ ++ int err_state = 0; ++ unsigned short reg_cevapll_pd; ++ unsigned short pll_value_low, pll_value_high; ++ ++ pll_value_low = REGR(BANK_PLL, 0x60); ++ pll_value_high = REGR(BANK_PLL, 0x61); ++ ++ HAL_MSG(HAL_MSG_WRN, "reg_pll_value = %04X %04X\n", pll_value_high, pll_value_low); ++ ++ // 0x00374BC6 is the default value of pll. ++ // Check default value to prevent init pll twice. ++ if((pll_value_high != 0x0037) && (pll_value_low != 0x4BC6)) ++ { ++ HAL_MSG(HAL_MSG_WRN, "pll clock is set already (%04X %04X)\n", pll_value_high, pll_value_low); ++ return 0; ++ } ++ ++ reg_cevapll_pd = REGR(BANK_PLL, 0x11); ++ reg_cevapll_pd = reg_cevapll_pd & 0x00ff; ++ ++ // Set PLL as 500 MHz ++ REGW(BANK_PLL, 0x60, 0x978c); ++ REGW(BANK_PLL, 0x61, 0x006e); ++ ++ REGW(BANK_PLL, 0x62, 0x0001); ++ REGW(BANK_PLL, 0x11, reg_cevapll_pd); ++ ++ REGW(BANK_WD_EN, 0x50, 0x00c6); ++ REGW(BANK_TOP_RESET, 0x24, 0x0005); ++ ++ // REGW(BANK_TOP_CLK, 0x20, 0x0000); // 12 MHz ++ REGW(BANK_TOP_CLK, 0x20, 0x0001); // From PLL ++ ++ return err_state; ++} +diff --git a/drivers/sstar/warp/hal/src/hal_warp.c b/drivers/sstar/warp/hal/src/hal_warp.c +new file mode 100755 +index 000000000000..6d03ce1b972b +--- /dev/null ++++ b/drivers/sstar/warp/hal/src/hal_warp.c +@@ -0,0 +1,268 @@ ++#include "hal_warp.h" ++#include "hal_debug.h" ++ ++#include "ms_platform.h" ++ ++#if (HAL_MSG_LEVL < HAL_MSG_DBG) ++#define REGR(base,idx) ms_readl(((uint)base+(idx))) ++#define REGW(base,idx,val) ms_writel(val,((uint)base+(idx))) ++#else ++#define REGR(base,idx) ms_readl(((uint)base+(idx))) ++#define REGW(base,idx,val) do{HAL_MSG(HAL_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)), val); ms_writel(val,((uint)base+(idx)));} while(0) ++#endif ++ ++/******************************************************************************************************************* ++ * warp_hal_set_axi ++ * Set AXI bus ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_axi(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++ { ++ handle->reg_bank.axi_cfg2.fields.mwb = (u8)(AXI_MAX_WRITE_BURST_SIZE & 0xff ); ++ handle->reg_bank.axi_cfg2.fields.mrb = (u8)(AXI_MAX_READ_BURST_SIZE & 0xff); ++ handle->reg_bank.axi_cfg2.fields.moutstw = (u8)(AXI_MAX_WRITE_OUTSTANDING & 0xff); ++ handle->reg_bank.axi_cfg2.fields.moutstr = (u8)(AXI_MAX_READ_OUTSTANDING & 0xff); ++ ++ REGW(handle->base_addr,WARP_AXI_CFG2_REG_ADDR, handle->reg_bank.axi_cfg2.overlay); //0x0c, AXI_CFG2 ++ } ++/******************************************************************************************************************* ++ * warp_hal_image_set ++ * Set image buffer pointer ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_image_point(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++ { ++ HAL_WARP_IMAGE_DATA_T* input_data = &config->input_data; ++ HAL_WARP_IMAGE_DATA_T* output_data = &config->output_data; ++ ++ //point to image plane ++ handle->reg_bank.dlua_yrgb = (s32)Chip_MIU_to_Phys(input_data->data[HAL_WARP_IMAGE_PLANE_Y]); //physical address ++ handle->reg_bank.dlua_uvg = (s32)Chip_MIU_to_Phys(input_data->data[HAL_WARP_IMAGE_PLANE_UV]); //physical address ++ handle->reg_bank.dsua_yrgb = (s32)Chip_MIU_to_Phys(output_data->data[HAL_WARP_IMAGE_PLANE_Y]); //physical address ++ handle->reg_bank.dsua_uvg = (s32)Chip_MIU_to_Phys(output_data->data[HAL_WARP_IMAGE_PLANE_UV]);; //physical address ++ ++ REGW(handle->base_addr,WARP_DLUA_YRGB_REG_ADDR, handle->reg_bank.dlua_yrgb ); //0x10, RGBA or Y base address of input ++ REGW(handle->base_addr,WARP_DLUA_UV_REG_ADDR, handle->reg_bank.dlua_uvg ); //0x14, UV base address of input ++ REGW(handle->base_addr,WARP_DSUA_YRGB_REG_ADDR, handle->reg_bank.dsua_yrgb ); //0x20, RGBA or Y base address of output ++ REGW(handle->base_addr,WARP_DSUA_UV_REG_ADDR, handle->reg_bank.dsua_uvg ); //0x24, UV base address of output ++ } ++/******************************************************************************************************************* ++ * warp_hal_image_size_set ++ * Set image size ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_image_size(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++ { ++ HAL_WARP_IMAGE_DESC_T* input_image = &config->input_image; ++ HAL_WARP_IMAGE_DESC_T* output_image = &config->output_image; ++ ++ //point to image plane ++ handle->reg_bank.ifsz.fields.ifszx = (u16)input_image->width; ++ handle->reg_bank.ifsz.fields.ifszy = (u16)input_image->height; ++ handle->reg_bank.ofsz.fields.ofszx= (u16)output_image->width; ++ handle->reg_bank.ofsz.fields.ofszy = (u16)output_image->height; ++ ++ REGW(handle->base_addr,WARP_IFSZ_REG_ADDR, handle->reg_bank.ifsz.overlay); //0x38, Input frame heigth and width ++ REGW(handle->base_addr,WARP_OFSZ_REG_ADDR, handle->reg_bank.ofsz.overlay); //0x3c, Output frame heigth and width ++ } ++/******************************************************************************************************************* ++ * warp_hal_output_tile_set ++ * Set output tile size ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_output_tile(warp_hal_handle* handle, u16 tile_w, u16 tile_h) ++ { ++ handle->reg_bank.ocs.fields.ocsx = (u16)tile_w; ++ handle->reg_bank.ocs.fields.ocsy = (u16)tile_h; ++ ++ REGW(handle->base_addr,WARP_OCS_REG_ADDR, handle->reg_bank.ocs.overlay); //0x30, Output tile scanning block height and width ++ } ++ /******************************************************************************************************************* ++ * warp_hal_set_disp ++ * Point to displacement map ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_disp(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++ { ++ HAL_WARP_DISPLAY_TABLE_T* disp_table = &config->disp_table; //< Displacement table descriptor ++ ++ handle->reg_bank.distba = (s32)Chip_MIU_to_Phys(disp_table->table); ++ ++ REGW(handle->base_addr,WARP_DISTBA_REG_ADDR, handle->reg_bank.distba ); //0x40, dist. table base address ++ } ++ /******************************************************************************************************************* ++ * warp_hal_set_bb ++ * Point to bounding box table ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_bb(warp_hal_handle* handle, s32 table_addr) ++ { ++ handle->reg_bank.bba = (s32)Chip_MIU_to_Phys(table_addr); ++ ++ REGW(handle->base_addr,WARP_BBA_REG_ADDR, handle->reg_bank.bba ); //0x44, B.B base address ++ } ++ /******************************************************************************************************************* ++ * warp_hal_pers_matirx_set ++ * Set perspective transform coefficient ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++ void warp_hal_set_pers_matirx(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++ { ++ handle->reg_bank.c00 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C00]; ++ handle->reg_bank.c01 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C01]; ++ handle->reg_bank.c02 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C02]; ++ handle->reg_bank.c10 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C10]; ++ handle->reg_bank.c11 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C11]; ++ handle->reg_bank.c12 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C12]; ++ handle->reg_bank.c20 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C20]; ++ handle->reg_bank.c21 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C21]; ++ handle->reg_bank.c22 = config->coeff[HAL_WARP_PERSECTIVE_COEFFS_C22]; ++ ++ REGW(handle->base_addr,WARP_PDC_C00_REGS_ADDR, handle->reg_bank.c00 ); //0x48, perspective transform coefficient(0x48~0x68) ++ REGW(handle->base_addr,WARP_PDC_C01_REGS_ADDR, handle->reg_bank.c01 );//0x4c ++ REGW(handle->base_addr,WARP_PDC_C02_REGS_ADDR, handle->reg_bank.c02 );//0x50 ++ REGW(handle->base_addr,WARP_PDC_C10_REGS_ADDR, handle->reg_bank.c10 ); //0x54 ++ REGW(handle->base_addr,WARP_PDC_C11_REGS_ADDR, handle->reg_bank.c11 );//0x58 ++ REGW(handle->base_addr,WARP_PDC_C12_REGS_ADDR, handle->reg_bank.c12 );//0x5C ++ REGW(handle->base_addr,WARP_PDC_C20_REGS_ADDR, handle->reg_bank.c20 ); //0x60 ++ REGW(handle->base_addr,WARP_PDC_C21_REGS_ADDR, handle->reg_bank.c21 );//0x64 ++ REGW(handle->base_addr,WARP_PDC_C22_REGS_ADDR, handle->reg_bank.c22 );//0x68 ++ } ++/******************************************************************************************************************* ++ * warp_hal_set_out_of_range ++ * Set out of range pixel fill value ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++void warp_hal_set_out_of_range(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++{ ++ handle->reg_bank.csfv.overlay= *((u32*)(config->fill_value)); ++ REGW(handle->base_addr,WARP_CSFV_REG_ADDR, handle->reg_bank.csfv.overlay ); //0x70, out of range pixel fill value ++} ++/******************************************************************************************************************* ++ * warp_hal_set_config ++ * Set configure ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * ++ * Return: ++ * ++ */ ++void warp_hal_set_config(warp_hal_handle* handle, HAL_WARP_CONFIG* config) ++{ ++ //handle->reg_bank.ctl.overlay = 0x4205; //default ++ handle->reg_bank.ctl.fields.dispm = config->op_mode; ++ handle->reg_bank.ctl.fields.dxym = config->disp_table.format; // 0 is abs mode, 1 is relative mode ++ handle->reg_bank.ctl.fields.eofie = 1; // End of frame interrupt enable ++ handle->reg_bank.ctl.fields.oie = 1; // Output interrupt enable ++ handle->reg_bank.ctl.fields.axierie = 1; // AXI error interrupt enable ++ handle->reg_bank.ctl.fields.dtibsz = config->disp_table.resolution; // gride size : 8x8 or 16x16 ++ handle->reg_bank.ctl.fields.iif = config->input_image.format; // RGBA, YUV422 NV16 or YUV420 NV12 ++ handle->reg_bank.ctl.fields.bpdu = DEBUG_BYPASS_DISPLACEMENT_EN; // Bypass Displacement unit (Debug hook) ++ handle->reg_bank.ctl.fields.bpiu = DEBUG_BYPASS_INTERP_EN; // Bypass Interpolation unit (Debug hook) ++ handle->reg_bank.ctl.fields.go = 1; // WARP accelerator starts ++ ++ REGW(handle->base_addr,WARP_CTL_REG_ADDR, handle->reg_bank.ctl.overlay ); //0x00, warp config setting ++} ++/******************************************************************************************************************* ++ * warp_hal_start ++ * Enable hw engine ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * en : enable hardware engine ++ * ++ * Return: ++ * ++ */ ++void warp_hal_start(warp_hal_handle* handle, uint en) ++{ ++ handle->reg_bank.ctl.fields.go = (en & 1); ++ ++ REGW(handle->base_addr,WARP_CTL_REG_ADDR, handle->reg_bank.ctl.overlay );//0x00, warp config setting ++} ++/******************************************************************************************************************* ++ * warp_hal_get_hw_status ++ * Get hardware status ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * config: WARP configurations ++ * en : enable hardware engine ++ * ++ * Return: ++ * ++ */ ++void warp_hal_get_hw_status(warp_hal_handle* handle) ++{ ++ u32 status = 0; ++ status = (u32)REGR(handle->base_addr,WARP_STA_REG_ADDR); ++ handle->reg_bank.sta.overlay = status; ++ ++ HAL_MSG(HAL_MSG_DBG, "REGR: addr 0x%02X, value 0x%08X\n", WARP_STA_REG_ADDR, handle->reg_bank.sta.overlay); ++} ++/******************************************************************************************************************* ++ * warp_hal_init ++ * init Warp HAL layer ++ * ++ * Parameters: ++ * handle: WARP HAL handle ++ * base_addr: base address ++ * ++ * Return: ++ * none ++ */ ++void warp_hal_init(warp_hal_handle *handle, phys_addr_t base_addr) ++{ ++ memset(handle, 0, sizeof(warp_hal_handle)); ++ handle->base_addr = base_addr; ++} +diff --git a/drivers/sstar/watchdog/Kconfig b/drivers/sstar/watchdog/Kconfig +new file mode 100755 +index 000000000000..70c5441dd7aa +--- /dev/null ++++ b/drivers/sstar/watchdog/Kconfig +@@ -0,0 +1,9 @@ ++config MS_WATCHDOG ++ tristate "watchdog driver" ++ help ++ Say Y here to enable the driver for the watchdog. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mdrv_wdt. +diff --git a/drivers/sstar/watchdog/Makefile b/drivers/sstar/watchdog/Makefile +new file mode 100755 +index 000000000000..925bf080d0f6 +--- /dev/null ++++ b/drivers/sstar/watchdog/Makefile +@@ -0,0 +1,3 @@ ++obj-$(CONFIG_MS_WATCHDOG) += mdrv_wdt.o ++ ++EXTRA_CFLAGS += -Idrivers/sstar/include +\ No newline at end of file +diff --git a/drivers/sstar/watchdog/mdrv_wdt.c b/drivers/sstar/watchdog/mdrv_wdt.c +new file mode 100755 +index 000000000000..f8d9f79a79ca +--- /dev/null ++++ b/drivers/sstar/watchdog/mdrv_wdt.c +@@ -0,0 +1,454 @@ ++/* ++* mdrv_wdt.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include /* for MODULE_ALIAS_MISCDEV */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "mdrv_wdt.h" ++#ifdef CONFIG_SS_DUALOS ++#include "drv_dualos.h" ++#endif ++#include "drv_camclk_Api.h" ++ ++//#define OPEN_WDT_DEBUG ++ ++#ifdef OPEN_WDT_DEBUG //switch printk ++#define wdtDbg printk ++#else ++#define wdtDbg(...) ++#endif ++#define wdtErr printk ++#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING) ++#define CONFIG_WATCHDOG_ATBOOT (0) ++#define CONFIG_WATCHDOG_DEFAULT_TIME (10) //unit=SEC ++#define REPEAT_DELAY 500 //unit=10ms ++ ++int tmr_margin = CONFIG_WATCHDOG_DEFAULT_TIME; ++//static bool nowayout = WATCHDOG_NOWAYOUT; ++ ++struct ms_wdt { ++ struct device *dev; ++ struct watchdog_device wdt_device; ++ void __iomem *reg_base; ++ spinlock_t lock; ++}; ++ ++static int infinity_wdt_start(struct watchdog_device *wdd); ++static int infinity_wdt_stop(struct watchdog_device *wdd); ++static int infinity_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout); ++static int infinity_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout); ++static int infinity_wdt_ping(struct watchdog_device *wdd); ++ ++static DEFINE_SPINLOCK(wdt_lock); ++ ++static U32 g_u32Clock; ++static struct timer_list wdt_timer; ++#ifdef CONFIG_PM_SLEEP ++static U8 watchdog_open_flag = 0; ++#endif ++static unsigned long next_heartbeat; ++ ++static const struct watchdog_info infinity_wdt_ident = { ++ .options = OPTIONS, ++ .firmware_version = 0, ++ .identity = "infinity Watchdog", ++}; ++ ++ ++static struct watchdog_ops infinity_wdt_ops = { ++ .owner = THIS_MODULE, ++ .start = infinity_wdt_start, ++ .stop = infinity_wdt_stop, ++ .set_timeout= infinity_wdt_set_timeout, ++ .ping = infinity_wdt_ping, ++}; ++ ++static struct watchdog_device infinity_wdd = { ++ .info = &infinity_wdt_ident, ++ .ops = &infinity_wdt_ops, ++}; ++ ++#ifdef CONFIG_SS_DUALOS ++static int write_riu_via_rtos(u32 addr, u16 val) ++{ ++ rtkinfo_t* rtk = NULL; ++ ++ rtk = get_rtkinfo(); ++ if (rtk) ++ { ++ snprintf(rtk->sbox, sizeof(rtk->sbox), "regset 0x%08X 0x%04X", (u32)addr, val); ++ signal_rtos(INTEROS_SC_L2R_RTK_CLI, 0, 0, 0); ++ } ++ else ++ { ++ pr_warn("[WatchDog] Get RTOS handle fail\n"); ++ } ++ ++ return 0; ++} ++#endif ++ ++U32 __infinity_wdt_get_clk_rate(void) ++{ ++ struct device_node *dev_node; ++ struct platform_device *pdev; ++ char compatible_name[64]; ++#ifdef CONFIG_CAM_CLK ++ u32 WdtClk = 0; ++#else ++ struct clk *clk; ++#endif ++ U32 rate = 0; ++ ++ sprintf(compatible_name, "sstar,infinity-wdt"); //"sstar,cmdq0" ++ dev_node = of_find_compatible_node(NULL, NULL, compatible_name); ++ ++ if (!dev_node) { ++ if (!dev_node) ++ return 0; ++ } ++ pdev = of_find_device_by_node(dev_node); ++ if (!pdev) { ++ of_node_put(dev_node); ++ return 0; ++ } ++#ifdef CONFIG_CAM_CLK ++ of_property_read_u32_index(pdev->dev.of_node,"camclk", 0,&(WdtClk)); ++ if (!WdtClk) ++ { ++ printk(KERN_DEBUG "[%s] Fail to get clk!\n", __func__); ++ } ++ else ++ { ++ rate = CamClkRateGet(WdtClk); ++ } ++#else ++ clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(clk)) ++ { ++ return 0; ++ } ++ ++ rate = (U32)clk_get_rate(clk); ++ clk_put(clk); ++#endif ++ return rate; ++} ++ ++void check_osc_clk(void) ++{ ++ g_u32Clock = __infinity_wdt_get_clk_rate(); ++ if (g_u32Clock == 0) ++ { ++ g_u32Clock = OSC_CLK_12000000; ++ } ++} ++ ++ ++static void __infinity_wdt_stop(void) ++{ ++ wdtDbg("__infinity_wdt_stop \n"); ++ OUTREG16(BASE_REG_WDT_PA + WDT_WDT_CLR, 0); ++ OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_H, 0x0000); ++ OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_L, 0x0000); ++} ++ ++static int infinity_wdt_stop(struct watchdog_device *wdd) ++{ ++ wdtDbg("[WatchDog]infinity_wdt_stop \n"); ++ ++ spin_lock(&wdt_lock); ++ del_timer(&wdt_timer); ++ __infinity_wdt_stop(); ++#ifdef CONFIG_PM_SLEEP ++ watchdog_open_flag = 0; ++#endif ++ spin_unlock(&wdt_lock); ++ ++ return 0; ++} ++ ++static void __infinity_wdt_start(U32 u32LaunchTim) ++{ ++ wdtDbg("__infinity_wdt_start \n"); ++ OUTREG16(BASE_REG_WDT_PA + WDT_WDT_CLR, CLEAR_WDT); ++ OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_H, (((g_u32Clock*u32LaunchTim)>>16) & 0xFFFF)); ++ OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_L, ((g_u32Clock*u32LaunchTim) & 0xFFFF)); ++} ++/* ++static void infinity_wdt_timer(unsigned long data) ++{ ++ unsigned long j; ++ ++ wdtDbg("[WatchDog]infinity_wdt_timer data=%lx \r\n",data); ++ ++ infinity_wdt_set_heartbeat(&infinity_wdd, data); ++ j = jiffies; ++ wdt_timer.expires = j + REPEAT_DELAY; ++ next_heartbeat = wdt_timer.expires; ++ add_timer(&wdt_timer); ++} ++*/ ++static int infinity_wdt_start(struct watchdog_device *wdd) ++{ ++ unsigned long j; ++ ++ wdtDbg("[WatchDog]infinity_wdt_start \n"); ++ spin_lock(&wdt_lock); ++ ++ __infinity_wdt_stop(); ++ ++ __infinity_wdt_start(tmr_margin); ++ ++ init_timer(&wdt_timer); ++ ++ //wdt_timer.data = (unsigned long)tmr_margin; ++ //wdt_timer.function = infinity_wdt_timer; ++ ++ j = jiffies; ++ wdt_timer.expires = j + REPEAT_DELAY*tmr_margin; ++ next_heartbeat = wdt_timer.expires; ++ //add_timer(&wdt_timer); ++#ifdef CONFIG_PM_SLEEP ++ watchdog_open_flag = 1; ++#endif ++ spin_unlock(&wdt_lock); ++ return 0; ++} ++ ++static int infinity_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout) ++{ ++ unsigned long j; ++ wdtDbg("[WatchDog]infinity_wdt_set_timeout=%d \n",timeout); ++ if (timeout < 5) ++ timeout = 5; ++ ++ j = jiffies; ++ next_heartbeat = j + REPEAT_DELAY*timeout; ++ ++ spin_lock(&wdt_lock); ++ wdd->timeout = timeout; ++ tmr_margin=timeout; ++ wdt_timer.data = (unsigned long)tmr_margin; ++ OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_H, (((g_u32Clock*tmr_margin)>>16) & 0xFFFF)); ++ OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_L, ((g_u32Clock*tmr_margin) & 0xFFFF)); ++ ++ spin_unlock(&wdt_lock); ++ wdtDbg("[WatchDog]infinity_wdt_set_timeout data=%lx \r\n",wdt_timer.data); ++ return 0; ++} ++ ++static int infinity_wdt_ping(struct watchdog_device *wdd) ++{ ++ /* If we got a heartbeat pulse within the WDT_US_INTERVAL ++ * we agree to ping the WDT ++ */ ++ unsigned long j; ++ ++ if (time_before(jiffies, next_heartbeat)) ++ { ++ // wdtDbg("[WatchDog] infinity_wdt_ping tmr_margin=%lx \r\n",(jiffies-next_heartbeat)); ++ ++ /* Ping the WDT */ ++#ifdef CONFIG_SS_DUALOS ++ //write_riu_via_rtos(BASE_REG_WDT_PA + WDT_MAX_PRD_H, (((g_u32Clock*tmr_margin)>>16) & 0xFFFF)); ++ //write_riu_via_rtos(BASE_REG_WDT_PA + WDT_MAX_PRD_L, ((g_u32Clock*tmr_margin) & 0xFFFF)); ++ write_riu_via_rtos(BASE_REG_WDT_PA + WDT_WDT_CLR, CLEAR_WDT); ++ spin_lock(&wdt_lock); ++#else ++ spin_lock(&wdt_lock); ++ //OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_H, (((g_u32Clock*tmr_margin)>>16) & 0xFFFF)); ++ //OUTREG16(BASE_REG_WDT_PA + WDT_MAX_PRD_L, ((g_u32Clock*tmr_margin) & 0xFFFF)); ++ OUTREG16(BASE_REG_WDT_PA + WDT_WDT_CLR, CLEAR_WDT); ++#endif ++ j = jiffies; ++ next_heartbeat = j + REPEAT_DELAY*tmr_margin; ++ ++ ++ spin_unlock(&wdt_lock); ++ wdtDbg("[WatchDog] infinity_wdt_ping tmr_margin=%x \r\n",tmr_margin); ++ ++ /* Re-set the timer interval */ ++ //mod_timer(&wdt_timer, jiffies + REPEAT_DELAY); ++ } ++ else { ++ pr_warn("Heartbeat lost! Will not ping the watchdog\n"); ++ } ++ ++ return 0; ++} ++ ++static int infinity_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) ++{ ++ //struct ms_wdt *wdt = watchdog_get_drvdata(wdd); ++ if (timeout < 1) ++ return -EINVAL; ++ //if(timeout>40)///for test ++ // return -EINVAL; ++ wdtDbg("[WatchDog]infinity_wdt_set_heartbeat \n"); ++ ++ OUTREG16(BASE_REG_WDT_PA + WDT_WDT_CLR, CLEAR_WDT); ++ ++ wdd->timeout = timeout; ++ ++ return 0; ++} ++ ++static int infinity_wdt_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct device *dev; ++ struct ms_wdt *wdt; ++ int started = 0; ++ struct resource *res; ++ ++ wdtDbg("[WatchDog]infinity_wdt_probe \n"); ++ dev = &pdev->dev; ++ wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); ++ if (!wdt) ++ return -ENOMEM; ++ ++ wdt->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ wdtDbg("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ wdt->reg_base = devm_ioremap_resource(&pdev->dev, res); ++ check_osc_clk(); ++ wdt->wdt_device = infinity_wdd; ++ ++ watchdog_set_drvdata(&wdt->wdt_device, wdt); ++ ++ if (infinity_wdt_set_heartbeat(&infinity_wdd, tmr_margin)) { ++ started = infinity_wdt_set_heartbeat(&infinity_wdd, CONFIG_WATCHDOG_DEFAULT_TIME); ++ ++ if (started == 0) ++ dev_info(dev, "tmr_margin value out of range, default %d used\n", CONFIG_WATCHDOG_DEFAULT_TIME); ++ else ++ dev_info(dev, "default timer value is out of range, cannot start\n"); ++ } ++ ++ //watchdog_set_nowayout(&infinity_wdd, nowayout); ++ ++ ret = watchdog_register_device(&infinity_wdd); ++ if (ret) { ++ dev_err(dev, "cannot register watchdog (%d)\n", ret); ++ goto err; ++ } ++ ++ //init_timer(&wdt_timer); ++ ++ //wdt_timer.data = (unsigned long)tmr_margin; ++ //wdt_timer.function = infinity_wdt_timer; ++ //infinity_wdt_start(&infinity_wdd); ++ ++ return 0; ++ ++ err: ++ watchdog_unregister_device(&infinity_wdd); ++ ++ return ret; ++} ++ ++static int infinity_wdt_remove(struct platform_device *dev) ++{ ++ wdtDbg("[WatchDog]infinity_wdt_remove\n"); ++ infinity_wdt_stop(&infinity_wdd); ++ watchdog_unregister_device(&infinity_wdd); ++ ++ return 0; ++} ++ ++static void infinity_wdt_shutdown(struct platform_device *dev) ++{ ++ wdtDbg("[WatchDog]infinity_wdt_shutdown\n"); ++ ++ infinity_wdt_stop(&infinity_wdd); ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int infinity_wdt_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ wdtDbg("[WatchDog]infinity_wdt_suspend\n"); ++ if(watchdog_open_flag == 1) { ++ infinity_wdt_stop(&infinity_wdd); ++ watchdog_open_flag = 1; // flag is clear by infinity_wdt_stop, need to be set again for resume ++ } ++ return 0; ++} ++ ++static int infinity_wdt_resume(struct platform_device *dev) ++{ ++ wdtDbg("[WatchDog]infinity_wdt_resume\n"); ++ /* Restore watchdog state. */ ++ if(watchdog_open_flag == 1) { ++ infinity_wdt_start(&infinity_wdd); ++ } ++ return 0; ++} ++#else ++#define infinity_wdt_suspend NULL ++#define infinity_wdt_resume NULL ++#endif /* CONFIG_PM_SLEEP */ ++ ++static const struct of_device_id ms_watchdog_of_match_table[] = { ++ { .compatible = "sstar,infinity-wdt" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_watchdog_of_match_table); ++ ++static struct platform_driver infinity_wdt_driver = { ++ .probe = infinity_wdt_probe, ++ .remove = infinity_wdt_remove, ++ .shutdown = infinity_wdt_shutdown, ++#ifdef CONFIG_PM_SLEEP ++ .suspend = infinity_wdt_suspend, ++ .resume = infinity_wdt_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "infinity-wdt", ++ .of_match_table = ms_watchdog_of_match_table, ++ }, ++}; ++ ++module_platform_driver(infinity_wdt_driver); ++ ++MODULE_AUTHOR("SSTAR"); ++MODULE_DESCRIPTION("infinity Watchdog Device Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:infinity-wdt"); ++ +diff --git a/drivers/sstar/watchdog/mdrv_wdt.h b/drivers/sstar/watchdog/mdrv_wdt.h +new file mode 100755 +index 000000000000..babdc077fd22 +--- /dev/null ++++ b/drivers/sstar/watchdog/mdrv_wdt.h +@@ -0,0 +1,71 @@ ++/* ++* mdrv_wdt.h- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: richard.guo ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef __MDRV_WDT_H ++#define __MDRV_WDT_H ++ ++//#include ++//#include "mach/platform.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#define BASE_REG_RIU_PA (0x1F000000) ++#define BASE_REG_WDT_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x001800) ++//#define BASE_REG_PM_PA GET_REG_ADDR(CHICAGO_BASE_REG_RIU_PA, 0x000700) ++#define BK_REG(reg) ((reg) << 2) ++ ++#define WDT_WDT_CLR BK_REG(0x00) ++#define WDT_DUMMY_REG_1 BK_REG(0x01) ++#define WDT_RST_RSTLEN BK_REG(0x02) ++#define WDT_INTR_PERIOD BK_REG(0x03) ++#define WDT_MAX_PRD_L BK_REG(0x04) ++#define WDT_MAX_PRD_H BK_REG(0x05) ++ ++ ++#define CLEAR_WDT 0x1 ++ ++#define OSC_CLK_26000000 26000000 ++#define OSC_CLK_24000000 24000000 ++#define OSC_CLK_16369000 16369000 ++#define OSC_CLK_12000000 12000000 ++#define OSC_CLK_4000000 4000000 ++ ++// Chip revisions ++#define REVISION_U01 (0x0) ++#define REVISION_U02 (0x1) ++#define REVISION_U03 (0x2) ++#define REVISION_U04 (0x3) ++#define REVISION_UNKNOWN (0x4) ++ ++#define BIT_0 0x1 ++#define BIT_1 0x2 ++#define BIT_2 0x4 ++#define BIT_3 0x8 ++#define BIT_4 0x10 ++#define BIT_5 0x20 ++#define BIT_6 0x40 ++#define BIT_7 0x80 ++#define BIT_8 0x100 ++#define BIT_9 0x200 ++#define BIT_10 0x400 ++#define BIT_11 0x800 ++#define BIT_12 0x1000 ++#define BIT_13 0x2000 ++#define BIT_14 0x4000 ++#define BIT_15 0x8000 ++ ++#endif +diff --git a/drivers/sstar/xpm/Kconfig b/drivers/sstar/xpm/Kconfig +new file mode 100755 +index 000000000000..33d8ed5a4c98 +--- /dev/null ++++ b/drivers/sstar/xpm/Kconfig +@@ -0,0 +1,4 @@ ++config MS_XPM ++ bool "eXtend PM driver" ++ ++ +\ No newline at end of file +diff --git a/drivers/sstar/xpm/Makefile b/drivers/sstar/xpm/Makefile +new file mode 100755 +index 000000000000..e173a5aaaee9 +--- /dev/null ++++ b/drivers/sstar/xpm/Makefile +@@ -0,0 +1,3 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ ++obj-$(CONFIG_MS_XPM) = ms_xpm.o +\ No newline at end of file +diff --git a/drivers/sstar/xpm/ms_xpm.c b/drivers/sstar/xpm/ms_xpm.c +new file mode 100755 +index 000000000000..1897e1a978cf +--- /dev/null ++++ b/drivers/sstar/xpm/ms_xpm.c +@@ -0,0 +1,679 @@ ++/* ++* ms_xpm.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: karl.xiao ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define USE_WAKEUP_SOURCE 0 ++ ++#define XPM_DEBUG 1 ++#define MINOR_XPM_NUM 129 ++ ++#if XPM_DEBUG ++#define PRINT(fmt, args...) printk("[XPM] " fmt, ## args) ++#else ++#define PRINT(fmt, args...) ++#endif ++ ++ ++#define XPM_NAME_SIZE 16 ++#define XPM_MIN_SUSPEND_WAIT_MS 20 ++ ++static int xpm_open(struct inode *inode, struct file *filp); ++static int xpm_release(struct inode *inode, struct file *filp); ++static long xpm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++static ssize_t xpm_read(struct file *filp, char __user *buf, size_t sz, loff_t *off); ++static ssize_t xpm_write(struct file *filp, const char __user *buf, size_t sz, loff_t *off); ++static unsigned int xpm_poll(struct file *filp, struct poll_table_struct *wait); ++static int xpm_deregister_source(struct file *filp); ++ ++static struct file_operations xpm_fops = { ++ .owner = THIS_MODULE, ++ .open = xpm_open, ++ .release = xpm_release, ++ .write = xpm_write, ++ .read = xpm_read, ++ .poll = xpm_poll, ++ .unlocked_ioctl=xpm_ioctl, ++}; ++ ++ ++static struct miscdevice xpm_dev = { ++ .minor = MINOR_XPM_NUM, ++ .name = "xpm", ++ .fops = &xpm_fops, ++ ++}; ++ ++typedef struct ++{ ++ char name[XPM_NAME_SIZE]; ++ unsigned int option; //reserved ++ EN_XPM_SOURCE_STATUS status; ++ struct file* fp; ++ EN_XPM_STATE poll_state; ++#if USE_WAKEUP_SOURCE ++ struct wakeup_source *wake; ++#endif ++} XPM_SOURCE; ++ ++struct XPM_SOURCE_LIST ++{ ++ ++ XPM_SOURCE source; ++ struct list_head list; ++ ++}; ++ ++typedef struct ++{ ++ EN_XPM_STATE state; ++ struct mutex mutex; ++ wait_queue_head_t wq; ++} XPM_MANAGER; ++ ++static XPM_MANAGER xpmm; ++static struct list_head kept_source_list_head; ++ ++static int suspend_wait_time=500; //ms ++ ++ ++//static void *mm_mem_virt = NULL; /* virtual address of frame buffer 1 */ ++ ++ ++ ++static int source_registered(XPM_SOURCE *src) ++{ ++ return (strlen(src->name)>0); ++} ++ ++EN_XPM_STATE xpm_get_state(void) ++{ ++ ++ return xpmm.state; ++} ++ ++ ++static int xpm_open(struct inode *inode, struct file *filp) ++{ ++ ++ int err=0; ++ struct XPM_SOURCE_LIST *new=(struct XPM_SOURCE_LIST *)kmalloc(sizeof(struct XPM_SOURCE_LIST),GFP_KERNEL); ++ if(!new){ ++ err=-ENOMEM; ++ goto BEACH; ++ } ++ new->source.fp=NULL; ++ ++ mutex_lock(&xpmm.mutex); ++ ++ if(!(xpm_get_state()&XPM_STATE_WAKEUPED)) ++ { ++ err=-EBUSY; ++ goto BEACH; ++ } ++ ++ memset(new->source.name,0,sizeof(new->source.name)); ++ ++ list_add(&new->list, &kept_source_list_head); ++ ++ new->source.fp=filp; ++ new->source.poll_state=XPM_STATE_WAKEUPED; ++ filp->private_data=new; ++ ++ ++BEACH: ++ mutex_unlock(&xpmm.mutex); ++ ++ if(err==-ENOMEM) ++ { ++ printk(KERN_ERR "ERROR!! Failed to allocate memory for xpm source\n" ) ; ++ } ++ ++ if(0==err) ++ { ++ PRINT("new xpm source: 0x%08X\n",(unsigned int)new->source.fp); ++ } ++ ++ return err; ++} ++ ++static int xpm_release(struct inode *inode, struct file *filp) ++{ ++ struct XPM_SOURCE_LIST *entry; ++ int err=0; ++ ++ mutex_lock(&xpmm.mutex); ++ ++ ++ entry=(struct XPM_SOURCE_LIST *)filp->private_data; ++ if(entry!=NULL) ++ { ++ list_del_init(&entry->list); ++ } ++ ++ err=xpm_deregister_source(filp); ++ if(err) goto BEACH; ++ ++ entry->source.fp=NULL; ++ filp->private_data=NULL; ++ ++ kfree(entry); ++ ++ ++BEACH: ++ mutex_unlock(&xpmm.mutex); ++ if(0==err) ++ { ++ PRINT("release XPM source: 0x%08X\n",(unsigned int)filp); ++ } ++ ++ ++ return err; ++} ++ ++ ++ ++static int xpm_register_source(char* name,struct file *filp) ++{ ++ ++ struct list_head *ptr; ++ struct XPM_SOURCE_LIST *entry,*match_entry=NULL; ++ int err=0; ++ ++// mutex_lock(&xpm.mutex); ++ if(!(xpm_get_state()&XPM_STATE_WAKEUPED)) ++ { ++ err=-EBUSY; ++ goto BEACH_ERROR; ++ } ++ ++ list_for_each(ptr, &kept_source_list_head) ++ { ++ entry = list_entry(ptr, struct XPM_SOURCE_LIST, list); ++ if (0==strcmp(name,entry->source.name)) ++ { ++ err=-1; ++ PRINT("ERROR!! XPM source name:[%s] already registered\n",name); ++ goto BEACH_ERROR; ++ } ++ } ++ ++ ++ list_for_each(ptr, &kept_source_list_head) ++ { ++ entry = list_entry(ptr, struct XPM_SOURCE_LIST, list); ++ if (entry->source.fp==filp) ++ { ++ match_entry=entry; ++ break;; ++ } ++ } ++ ++ if(match_entry==NULL) ++ { ++ err=-1; ++ PRINT("WARNING!! no XPM source:0x%08X found\n",(unsigned int)filp); ++ goto BEACH_ERROR; ++ } ++ ++ if(strlen(match_entry->source.name)>0) ++ { ++ err=-2; ++ PRINT("WARNING!! XPM source:0x%08X already registered with name [%s]\n",(unsigned int)filp,match_entry->source.name); ++ goto BEACH_ERROR; ++ } ++ ++ strncpy(match_entry->source.name,name,(XPM_NAME_SIZE-1)); ++ match_entry->source.status=XPM_SOURCE_ACTIVE; ++ ++ PRINT("successfully register XPM source: 0x%08X[%s]\n",(unsigned int)match_entry->source.fp,match_entry->source.name); ++ ++BEACH_ERROR: ++// mutex_unlock(&xpm.mutex); ++ return err; ++ ++} ++ ++static int xpm_deregister_source(struct file *filp) ++{ ++ ++ struct list_head *ptr; ++ struct XPM_SOURCE_LIST *entry,*match_entry=NULL; ++ int err=0; ++ ++// mutex_lock(&xpm.mutex); ++ list_for_each(ptr, &kept_source_list_head) ++ { ++ entry = list_entry(ptr, struct XPM_SOURCE_LIST, list); ++ if (entry->source.fp==filp) ++ { ++ match_entry=entry; ++ break;; ++ } ++ } ++ ++ if(match_entry==NULL) ++ { ++ err=-1; ++ PRINT("WARNING!! no XPM source:0x%08X found\n",(unsigned int)filp); ++ goto BEACH_ERROR; ++ } ++ ++ memset(match_entry->source.name,0,sizeof(match_entry->source.name)); ++ ++ PRINT("successfully deregister XPM source: 0x%08X\n",(unsigned int)match_entry->source.fp); ++ ++BEACH_ERROR: ++// mutex_unlock(&xpm.mutex); ++ return err; ++ ++} ++static long xpm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int err= 0; ++ ++ // extract the type and number bitfields, and don��t decode ++ // wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ if (_IOC_TYPE(cmd) != XPM_IOCTL_MAGIC) return -ENOTTY; ++ if (_IOC_NR(cmd) > IOCTL_XPM_MAXNR) return -ENOTTY; ++ switch(cmd) ++ { ++ ++ case IOCTL_XPM_REGISTER_SOURCE: ++ { ++ char _name[XPM_NAME_SIZE]={'\0'}; ++ if( copy_from_user((void*)_name, (void __user *)arg, (XPM_NAME_SIZE>strlen((char *)arg))? (strlen((char *)arg)+1): XPM_NAME_SIZE-1 ) ) ++ { ++ BUG(); ++ ++ } ++ if(strlen(_name)>0) ++ { ++ mutex_lock(&xpmm.mutex); ++ err=xpm_register_source(_name,filp); ++ mutex_unlock(&xpmm.mutex); ++ } ++ ++ } ++ break; ++ ++ case IOCTL_XPM_DEREGISTER_SOURCE: ++ { ++ mutex_lock(&xpmm.mutex); ++ err=xpm_deregister_source(filp); ++ mutex_unlock(&xpmm.mutex); ++ ++ } ++ break; ++ ++ default: ++ PRINT("ERROR!! unknown IOCTL command 0x%08X\n", cmd); ++ return -ENOTTY; ++ } ++ ++ ++ return err; ++} ++ ++//static int mpm_supend_count=0; ++//static int mpm_supend_task_delay=0; ++//static int suspend_retry_count=0; ++// ++// ++//static void _mpm_suspend_to_ram_task() ++//{ ++// ++//} ++ ++ ++ ++ ++void xpm_change_state(int state) ++{ ++ ++ ++ xpmm.state=state; ++ if(XPM_STATE_SUSPENDED != state) ++ { ++ wake_up_interruptible(&xpmm.wq); ++ } ++ ++} ++ ++static ssize_t xpm_read(struct file *filp, char __user *buf, size_t sz, loff_t *off) ++{ ++ ++ if(szprivate_data)->source; ++ ++ if(!source_registered(source)) ++ { ++ PRINT("WANRING!! no effect on unregistered XPM source: 0x%08X\n",(unsigned int)filp); ++ break; ++ } ++ ++ source->status=XPM_SOURCE_STANDBY; ++ PRINT("XPM source: 0x%08X[%s] STANDBY done\n",(unsigned int)source->fp,source->name); ++ } ++ break; ++ ++ ++ ++ default: ++ PRINT("unknown XPM source command: 0x%08X\n",cmd); ++ } ++ ++//BEACH: ++ return err; ++} ++ ++ ++ ++static unsigned int xpm_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ++ EN_XPM_STATE st=XPM_STATE_END; ++ unsigned int mask = 0; ++ XPM_SOURCE *source=&((struct XPM_SOURCE_LIST*)filp->private_data)->source; ++ ++ if(!source_registered(source)) ++ { ++ PRINT("ERROR!! can not poll unregistered XPM source: 0x%08X\n",(unsigned int)filp); ++ return POLLNVAL; ++ } ++ ++ ++ poll_wait(filp, &xpmm.wq, wait); ++ st=xpm_get_state(); ++ if(( st == XPM_STATE_SUSPENDING) && (source->poll_state!=XPM_STATE_SUSPENDING)) ++ { ++ PRINT("POLLIN XPM source: 0x%08X[%s][XPM_STATE_SUSPENDING]\n",(unsigned int)source->fp,source->name); ++ source->poll_state=XPM_STATE_SUSPENDING; ++ mask = POLLIN | POLLWRNORM; ++ } ++ else if(( st == XPM_STATE_WAKEUPED) && (source->poll_state!=XPM_STATE_WAKEUPED)) ++ { ++ PRINT("POLLIN XPM source: 0x%08X[%s][XPM_STATE_WAKEUPED]\n",(unsigned int)source->fp,source->name); ++ source->poll_state=XPM_STATE_WAKEUPED; ++ mask = POLLIN | POLLWRNORM; ++ } ++ else if(( st == (XPM_STATE_WAKEUPED|XPM_STATE_SUSPEND_ABORT)) && (source->poll_state!=(XPM_STATE_WAKEUPED|XPM_STATE_SUSPEND_ABORT))) ++ { ++ PRINT("POLLIN XPM source: 0x%08X[%s][XPM_STATE_WAKEUPED]\n",(unsigned int)source->fp,source->name); ++ source->poll_state=(XPM_STATE_WAKEUPED|XPM_STATE_SUSPEND_ABORT); ++ mask = POLLIN | POLLWRNORM; ++ } ++ ++ return mask; ++} ++ ++int xpm_prepare_suspend(void) ++{ ++ int t=0; ++ int err=0; ++// int xpm_source_count=xpm_get_registered_source_count(); ++ ++ ++ mutex_lock(&xpmm.mutex); ++ xpm_change_state(XPM_STATE_SUSPENDING); ++ while(true) ++ { ++ struct list_head *ptr; ++ struct XPM_SOURCE_LIST *entry; ++ int active_source_count=0; ++ ++ msleep(XPM_MIN_SUSPEND_WAIT_MS); ++ t+=XPM_MIN_SUSPEND_WAIT_MS; ++ ++ list_for_each(ptr, &kept_source_list_head) ++ { ++ entry = list_entry(ptr, struct XPM_SOURCE_LIST, list); ++ if(source_registered(&entry->source) && entry->source.status != XPM_SOURCE_STANDBY) ++ { ++ active_source_count++; ++ if(t>suspend_wait_time) ++ { ++ xpm_change_state(XPM_STATE_SUSPEND_ABORT|XPM_STATE_WAKEUPED); ++ PRINT("XPM suspend aborted!! XPM source: 0x%08X[%s]\n",(unsigned int)entry->source.fp,entry->source.name); ++ err=-EBUSY; ++ goto BEACH; ++ } ++ ++ break; ++ } ++ } ++ ++ if(0==active_source_count) ++ { ++ break; ++ } ++ } ++ ++ ++BEACH: ++ ++ if(0==err) ++ { ++ PRINT("XPM suspend\n"); ++ xpm_change_state(XPM_STATE_SUSPENDED); ++ } ++ ++ mutex_unlock(&xpmm.mutex); ++ return err; ++} ++EXPORT_SYMBOL(xpm_prepare_suspend); ++ ++ ++int xpm_notify_wakeup(void) ++{ ++ struct list_head *ptr; ++ struct XPM_SOURCE_LIST *entry; ++ ++ mutex_lock(&xpmm.mutex); ++ xpm_change_state(XPM_STATE_WAKEUPED); ++ ++ list_for_each(ptr, &kept_source_list_head) ++ { ++ entry = list_entry(ptr, struct XPM_SOURCE_LIST, list); ++ if(source_registered(&entry->source)) ++ { ++ entry->source.status = XPM_SOURCE_ACTIVE; ++ } ++ } ++ ++ mutex_unlock(&xpmm.mutex); ++ PRINT("XPM wakeuped\n"); ++ return 0; ++} ++ ++EXPORT_SYMBOL(xpm_notify_wakeup); ++ ++ssize_t xpm_show(struct kobject *kobj,struct kobj_attribute *attr, char *buf) ++{ ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct list_head *ptr; ++ struct XPM_SOURCE_LIST *entry; ++ int i=0; ++ ++ str += scnprintf(str, end - str, "XPM state: 0x%02X\n", xpm_get_state()); ++ ++ list_for_each(ptr, &kept_source_list_head) ++ { ++ XPM_SOURCE *source; ++ entry = list_entry(ptr, struct XPM_SOURCE_LIST, list); ++ source=(XPM_SOURCE *)(&entry->source); ++ str += scnprintf(str, end - str, "%04d: 0x%08X[%s], 0x%02X \n",i,(unsigned int)source->fp,source->name,source->status); ++ i++; ++ } ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++EXPORT_SYMBOL(xpm_show); ++ ++ssize_t xpm_store(struct kobject *kobj, struct kobj_attribute *attr,const char *buf, size_t n) ++{ ++ int err=0; ++ long st; ++ ++ ++ if(kstrtoul(buf,10,&st)) ++ { ++ return -EINVAL; ++ } ++ ++ ++ if((st!=(long)XPM_STATE_SUSPENDING) && (st!=(long)XPM_STATE_WAKEUPED) && (st!=(long)(XPM_STATE_WAKEUPED|XPM_STATE_SUSPEND_ABORT)) ) ++ { ++ printk(KERN_ERR"Unsupport XPM state:0x%02X\n",(unsigned int)st); ++ err=-EINVAL; ++ } ++ else ++ { ++ if(st==(long)XPM_STATE_SUSPENDING) ++ { ++ xpm_prepare_suspend(); ++ } ++ else ++ { ++ xpm_notify_wakeup(); ++ } ++ } ++ ++ return err ? err : n; ++} ++EXPORT_SYMBOL(xpm_store); ++ ++ ++ssize_t xpm_suspend_wait_ms_show(struct kobject *kobj,struct kobj_attribute *attr, char *buf) ++{ ++ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", suspend_wait_time); ++ ++ return (str - buf); ++} ++ ++EXPORT_SYMBOL(xpm_suspend_wait_ms_show); ++ ++ssize_t xpm_suspend_wait_ms_store(struct kobject *kobj, struct kobj_attribute *attr,const char *buf, size_t n) ++{ ++ long st; ++ ++ if(kstrtoul(buf,10,&st)) ++ { ++ return 0; ++ } ++ suspend_wait_time=(stdev_name, + drv->tty_driver->name_base + port->line, + address, port->irq, port->uartclk / 16, uart_type(port)); ++ + } + + static void +diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c +index 8d9f9a803b42..49fad8375fab 100644 +--- a/drivers/tty/tty_io.c ++++ b/drivers/tty/tty_io.c +@@ -2618,10 +2618,10 @@ static int tiocspgrp(struct tty_struct *tty, struct tty_struct *real_tty, pid_t + if (session_of_pgrp(pgrp) != task_session(current)) + goto out_unlock; + retval = 0; +- spin_lock_irq(&tty->ctrl_lock); ++ spin_lock_irq(&real_tty->ctrl_lock); + put_pid(real_tty->pgrp); + real_tty->pgrp = get_pid(pgrp); +- spin_unlock_irq(&tty->ctrl_lock); ++ spin_unlock_irq(&real_tty->ctrl_lock); + out_unlock: + rcu_read_unlock(); + return retval; +diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig +old mode 100644 +new mode 100755 +index 0103f777b97a..e85e37398550 +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -37,6 +37,10 @@ menuconfig USB_SUPPORT + + if USB_SUPPORT + ++config MP_USB_MSTAR ++ bool "Sstar Host patches" ++ depends on ARCH_CEDRIC || ARCH_INFINITY || ARCH_INFINITY3 || ARCH_INFINITY5 || ARCH_INFINITY6 || ARCH_INFINITY2M || ARCH_INFINITY6E || ARCH_INFINITY6B0 || ARCH_INFINITY2 ++ default y + config USB_COMMON + tristate + +diff --git a/drivers/usb/core/Kconfig b/drivers/usb/core/Kconfig +index 0e5a889742b3..367d7ea0658d 100644 +--- a/drivers/usb/core/Kconfig ++++ b/drivers/usb/core/Kconfig +@@ -3,6 +3,7 @@ + # + config USB_ANNOUNCE_NEW_DEVICES + bool "USB announce new devices" ++ default y + help + Say Y here if you want the USB core to always announce the + idVendor, idProduct, Manufacturer, Product, and SerialNumber +diff --git a/drivers/usb/core/Makefile b/drivers/usb/core/Makefile +index b99b871c4b9d..2a3112b2ba51 100644 +--- a/drivers/usb/core/Makefile ++++ b/drivers/usb/core/Makefile +@@ -2,10 +2,23 @@ + # Makefile for USB Core files and filesystem + # + ++# mstar_porting_plat >>> ++EXTRA_CFLAGS += -Idrivers/sstar/usb/host ++EXTRA_CFLAGS += -Idrivers/sstar/usb/host/$(CONFIG_SSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++# necessary if defined(DYNAMIC_MIU_SIZE_MAPPING) ++#EXTRA_CFLAGS += -Idrivers/sstar2/include/sys/common ++#EXTRA_CFLAGS += -Idrivers/sstar2/include ++#EXTRA_CFLAGS += -Idrivers/sstar2/drv/miu ++# mstar_porting_plat <<< + usbcore-y := usb.o hub.o hcd.o urb.o message.o driver.o + usbcore-y += config.o file.o buffer.o sysfs.o endpoint.o + usbcore-y += devio.o notify.o generic.o quirks.o devices.o + usbcore-y += port.o ++# mstar_porting_plat >>> ++usbcore-$(CONFIG_MP_USB_MSTAR) += ../../sstar/usb/host/bc-mstar.o ++usbcore-$(CONFIG_MP_USB_MSTAR) += ../../sstar/usb/host/mstar-lib.o ++# mstar_porting_plat <<< + + usbcore-$(CONFIG_OF) += of.o + usbcore-$(CONFIG_PCI) += hcd-pci.o +diff --git a/drivers/usb/core/buffer.c b/drivers/usb/core/buffer.c +index 98e39f91723a..b9753ba48bb9 100644 +--- a/drivers/usb/core/buffer.c ++++ b/drivers/usb/core/buffer.c +@@ -16,6 +16,9 @@ + #include + #include + ++#ifdef CONFIG_MP_USB_MSTAR ++#include "usb_common_sstar.h" ++#endif + + /* + * DMA-Coherent Buffers +@@ -28,6 +31,9 @@ static size_t pool_max[HCD_BUFFER_POOLS] = { + + void __init usb_init_pool_max(void) + { ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ pool_max[0] = 0; /* Don't use this pool */ ++#else + /* + * The pool_max values must never be smaller than + * ARCH_KMALLOC_MINALIGN. +@@ -40,6 +46,7 @@ void __init usb_init_pool_max(void) + pool_max[0] = 0; /* Don't use this pool */ + else + BUILD_BUG(); /* We don't allow this */ ++#endif + } + + /* SETUP primitives */ +diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c +index 7c54a19b20e0..35b9a4a211c8 100644 +--- a/drivers/usb/core/config.c ++++ b/drivers/usb/core/config.c +@@ -8,11 +8,18 @@ + #include + #include "usb.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif + + #define USB_MAXALTSETTING 128 /* Hard limit */ + + #define USB_MAXCONFIG 8 /* Arbitrary limit */ + ++#if (MP_USB_MSTAR==1) ++extern u8 hcd_readb(struct usb_hcd *, size_t); ++extern void hcd_writeb(struct usb_hcd *, u8, size_t); ++#endif + + static inline const char *plural(int n) + { +@@ -394,6 +401,22 @@ static int usb_parse_endpoint(struct device *ddev, int cfgno, int inum, + usb_parse_ss_endpoint_companion(ddev, cfgno, + inum, asnum, endpoint, buffer, size); + ++#if (MP_USB_MSTAR == 1) ++ if ((to_usb_device(ddev)->speed == USB_SPEED_HIGH) && ++ (to_usb_device(ddev)->descriptor.bDeviceClass != USB_CLASS_HUB) && ++ usb_endpoint_xfer_isoc(d)) { ++ if (to_usb_device(ddev)->parent) { ++ if (to_usb_device(ddev)->parent->parent == NULL) { ++ struct usb_hcd *hcd = bus_to_hcd(to_usb_device(ddev)->bus); ++ if (hcd->ehc_base) { ++ if (((hcd_readb(hcd, 0x34)>>2) & 0x3) != 0x3) { ++ hcd_writeb(hcd, (hcd_readb(hcd, 0x34) | ((1U<<2)|(1U<<3))), 0x34); ++ } ++ } ++ } ++ } ++ } ++#endif + /* Skip over any Class Specific or Vendor Specific descriptors; + * find the next endpoint or interface descriptor */ + endpoint->extra = buffer; +@@ -825,6 +848,13 @@ int usb_get_configuration(struct usb_device *dev) + if (!desc) + goto err2; + ++#if (MP_USB_MSTAR==1) ++ if((le16_to_cpu(dev->descriptor.idVendor) == 0x043e) && ++ (le16_to_cpu(dev->descriptor.idProduct) == 0x3009)) ++ { ++ mdelay(500); ++ } ++#endif + result = 0; + for (; cfgno < ncfg; cfgno++) { + /* We grab just the first descriptor so we know how long +diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c +index 893ebae51029..893bfd53e222 100644 +--- a/drivers/usb/core/devio.c ++++ b/drivers/usb/core/devio.c +@@ -56,6 +56,9 @@ + + #include "usb.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif + #define USB_MAXBUS 64 + #define USB_DEVICE_MAX (USB_MAXBUS * 128) + #define USB_SG_SIZE 16384 /* split-size for large txs */ +@@ -1122,6 +1125,10 @@ static int proc_control(struct usb_dev_state *ps, void __user *arg) + i = usb_control_msg(dev, pipe, ctrl.bRequest, + ctrl.bRequestType, ctrl.wValue, ctrl.wIndex, + tbuf, ctrl.wLength, tmo); ++#if (MP_USB_MSTAR==1) ++ if (dev->state != USB_STATE_CONFIGURED) ++ msleep(1); ++#endif + usb_lock_device(dev); + snoop_urb(dev, NULL, pipe, max(i, 0), min(i, 0), COMPLETE, + tbuf, max(i, 0)); +diff --git a/drivers/usb/core/generic.c b/drivers/usb/core/generic.c +index 358ca8dd784f..5b7b750449eb 100644 +--- a/drivers/usb/core/generic.c ++++ b/drivers/usb/core/generic.c +@@ -21,6 +21,9 @@ + #include + #include "usb.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif + static inline const char *plural(int n) + { + return (n == 1 ? "" : "s"); +@@ -169,6 +172,18 @@ static int generic_probe(struct usb_device *udev) + else { + c = usb_choose_configuration(udev); + if (c >= 0) { ++#if (MP_USB_MSTAR==1) ++ int i; ++ for (i = 0; i < 3; ++i) { ++ err = usb_set_configuration(udev, c); ++ if (!err) ++ break; ++ if (err && err != -ENODEV) { ++ dev_err(&udev->dev, "can't set config #%d, error %d%s\n", ++ c, err, i<2 ? ", retry...": ""); ++ } ++ } ++#else + err = usb_set_configuration(udev, c); + if (err && err != -ENODEV) { + dev_err(&udev->dev, "can't set config #%d, error %d\n", +@@ -176,6 +191,7 @@ static int generic_probe(struct usb_device *udev) + /* This need not be fatal. The user can try to + * set other configurations. */ + } ++#endif + } + } + /* USB device state == configured ... usable */ +diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c +index fcc7aa248ce7..3131c8bd1bb9 100644 +--- a/drivers/usb/core/hcd.c ++++ b/drivers/usb/core/hcd.c +@@ -50,7 +50,11 @@ + + #include "usb.h" + +- ++#ifdef CONFIG_MP_USB_MSTAR ++#include "ms_platform.h" ++#include "usb_common_sstar.h" ++extern u8 hcd_readb(struct usb_hcd *, size_t); ++#endif + /*-------------------------------------------------------------------------*/ + + /* +@@ -1433,6 +1437,10 @@ static void hcd_free_coherent(struct usb_bus *bus, dma_addr_t *dma_handle, + + void usb_hcd_unmap_urb_setup_for_dma(struct usb_hcd *hcd, struct urb *urb) + { ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ if (urb->transfer_flags & (URB_SETUP_MAP_SINGLE | URB_SETUP_MAP_LOCAL)) ++ urb->setup_dma = PA2BUS(urb->setup_dma); ++#endif + if (IS_ENABLED(CONFIG_HAS_DMA) && + (urb->transfer_flags & URB_SETUP_MAP_SINGLE)) + dma_unmap_single(hcd->self.controller, +@@ -1466,6 +1474,21 @@ void usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) + usb_hcd_unmap_urb_setup_for_dma(hcd, urb); + + dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ if (urb->transfer_flags & URB_DMA_MAP_SG) ++ { ++ struct scatterlist *s; ++ int i; ++ for_each_sg(urb->sg, s, urb->num_sgs, i) { ++ s->dma_address = PA2BUS(s->dma_address); ++ } ++ } ++ else if (urb->transfer_flags & (URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE | URB_MAP_LOCAL)) ++ urb->transfer_dma = PA2BUS(urb->transfer_dma); ++ else if (urb->transfer_buffer_length != 0 ++ && (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) ++ urb->transfer_dma = PA2BUS(urb->transfer_dma); ++#endif + if (IS_ENABLED(CONFIG_HAS_DMA) && + (urb->transfer_flags & URB_DMA_MAP_SG)) + dma_unmap_sg(hcd->self.controller, +@@ -1531,6 +1554,9 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + urb->setup_dma)) + return -EAGAIN; + urb->transfer_flags |= URB_SETUP_MAP_SINGLE; ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ urb->setup_dma = BUS2PA(urb->setup_dma); ++#endif + } else if (hcd->driver->flags & HCD_LOCAL_MEM) { + ret = hcd_alloc_coherent( + urb->dev->bus, mem_flags, +@@ -1538,6 +1564,9 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + (void **)&urb->setup_packet, + sizeof(struct usb_ctrlrequest), + DMA_TO_DEVICE); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ urb->setup_dma = BUS2PA(urb->setup_dma); ++#endif + if (ret) + return ret; + urb->transfer_flags |= URB_SETUP_MAP_LOCAL; +@@ -1562,6 +1591,16 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + urb->sg, + urb->num_sgs, + dir); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ if (n > 0) ++ { ++ struct scatterlist *s; ++ int i; ++ for_each_sg(urb->sg, s, urb->num_sgs, i) { ++ s->dma_address = BUS2PA(s->dma_address); ++ } ++ } ++#endif + if (n <= 0) + ret = -EAGAIN; + else +@@ -1583,6 +1622,9 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + ret = -EAGAIN; + else + urb->transfer_flags |= URB_DMA_MAP_PAGE; ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ urb->transfer_dma = BUS2PA(urb->transfer_dma); ++#endif + } else if (is_vmalloc_addr(urb->transfer_buffer)) { + WARN_ONCE(1, "transfer buffer not dma capable\n"); + ret = -EAGAIN; +@@ -1597,6 +1639,9 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + ret = -EAGAIN; + else + urb->transfer_flags |= URB_DMA_MAP_SINGLE; ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ urb->transfer_dma = BUS2PA(urb->transfer_dma); ++#endif + } + } else if (hcd->driver->flags & HCD_LOCAL_MEM) { + ret = hcd_alloc_coherent( +@@ -1605,6 +1650,9 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + &urb->transfer_buffer, + urb->transfer_buffer_length, + dir); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ urb->transfer_dma = BUS2PA(urb->transfer_dma); ++#endif + if (ret == 0) + urb->transfer_flags |= URB_MAP_LOCAL; + } +@@ -1612,6 +1660,14 @@ int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + URB_SETUP_MAP_LOCAL))) + usb_hcd_unmap_urb_for_dma(hcd, urb); + } ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ else if (urb->transfer_buffer_length != 0 ++ && (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) ++ { ++ Chip_Flush_MIU_Pipe(); ++ urb->transfer_dma = BUS2PA(urb->transfer_dma); ++ } ++#endif + return ret; + } + EXPORT_SYMBOL_GPL(usb_hcd_map_urb_for_dma); +@@ -1914,6 +1970,9 @@ rescan: + } + spin_unlock_irq(&hcd_urb_list_lock); + ++#if (MP_USB_MSTAR==1) ++ msleep(10); //120316, modify for wifi load/unload repeatly ++#endif + /* Wait until the endpoint queue is completely empty */ + while (!list_empty (&ep->urb_list)) { + spin_lock_irq(&hcd_urb_list_lock); +@@ -2245,8 +2304,12 @@ int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg) + (PMSG_IS_AUTO(msg) ? "auto-" : ""), + rhdev->do_remote_wakeup); + if (HCD_DEAD(hcd)) { ++#if (MP_USB_MSTAR==1) ++ printk("continue suspend for dead bus\n"); ++#else + dev_dbg(&rhdev->dev, "skipped %s of dead bus\n", "suspend"); + return 0; ++#endif + } + + if (!hcd->driver->bus_suspend) { +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c +old mode 100644 +new mode 100755 +index d0d3f9ef9f10..6d622a1408cf +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -33,6 +33,8 @@ + #include "hub.h" + #include "otg_whitelist.h" + ++#include "usb_common_sstar.h" ++ + #define USB_VENDOR_GENESYS_LOGIC 0x05e3 + #define HUB_QUIRK_CHECK_PORT_AUTOSUSPEND 0x01 + +@@ -101,7 +103,58 @@ EXPORT_SYMBOL_GPL(ehci_cf_port_reset_rwsem); + + static void hub_release(struct kref *kref); + static int usb_reset_and_verify_device(struct usb_device *udev); ++#if (MP_USB_MSTAR==1) ++static int hub_port_disable(struct usb_hub *hub, int port1, int set_state, int set_disable); ++#else + static int hub_port_disable(struct usb_hub *hub, int port1, int set_state); ++#endif ++ ++#if (MP_USB_MSTAR==1) ++/* ++ * 20111224 for tx/rx reset hit XIU timeout ++ */ ++u8 hcd_readb(struct usb_hcd *hcd, size_t reg) ++{ ++ u8 result; ++ ++#if _USB_XIU_TIMEOUT_PATCH ++ unsigned long flags; ++ spin_lock_irqsave(&(hcd->usb_reset_lock), flags); ++#endif ++ ++ if(reg & BIT0) ++ result = readb((void *)(hcd->ehc_base + (reg*2-1))); ++ else ++ result = readb((void *)(hcd->ehc_base + (reg*2))); ++ ++#if _USB_XIU_TIMEOUT_PATCH ++ spin_unlock_irqrestore(&(hcd->usb_reset_lock), flags); ++#endif ++ ++ return result; ++} ++ ++/* ++ * 20111224 for tx/rx reset hit XIU timeout ++ */ ++void hcd_writeb(struct usb_hcd *hcd, u8 data, size_t reg) ++{ ++#if _USB_XIU_TIMEOUT_PATCH ++ unsigned long flags; ++ spin_lock_irqsave(&(hcd->usb_reset_lock), flags); ++#endif ++ ++ if(reg & BIT0) ++ writeb(data, (void *)(hcd->ehc_base + (reg*2-1))); ++ else ++ writeb(data, (void *)(hcd->ehc_base + (reg*2))); ++ ++#if _USB_XIU_TIMEOUT_PATCH ++ spin_unlock_irqrestore(&(hcd->usb_reset_lock), flags); ++#endif ++ ++} ++#endif + + static inline char *portspeed(struct usb_hub *hub, int portstatus) + { +@@ -916,7 +969,12 @@ static int hub_set_port_link_state(struct usb_hub *hub, int port1, + static void hub_port_logical_disconnect(struct usb_hub *hub, int port1) + { + dev_dbg(&hub->ports[port1 - 1]->dev, "logical disconnect\n"); ++ ++#if (MP_USB_MSTAR==1) ++ hub_port_disable(hub, port1, 1, 0); ++#else + hub_port_disable(hub, port1, 1); ++#endif + + /* FIXME let caller ask to power down the port: + * - some devices won't enumerate without a VBUS power cycle +@@ -2091,6 +2149,128 @@ void usb_disconnect(struct usb_device **pdev) + struct usb_device *udev = *pdev; + struct usb_hub *hub = NULL; + int port1 = 1; ++#if (MP_USB_MSTAR==1) // HOTPLUG tony ++ int devnum=udev->devnum; ++ struct usb_hcd *hcd = bus_to_hcd(udev->bus); ++#endif ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_SSDISABLED_PATCH) ++ struct usb_device *hdev; ++ unsigned long value; ++#endif ++ ++#if (MP_USB_MSTAR==1) ++ if (!udev) { ++ pr_debug ("%s nodev\n", __func__); ++ return; ++ } ++ ++ /* If EHC halted while roothub dev disconnect, restart EHC by set ++ * its run bit. The periodic schedule urb reclaiming will reference ++ * the frame index, so we should not halt the EHC while disconnect. ++ */ ++ if ((hcd->ehc_base != 0) && (hcd->root_port_devnum == devnum)) ++ { ++ /* Make sure the EHC is halted already */ ++ if(hcd_readb(hcd, 0x15) & BIT4) ++ { ++ hcd_writeb(hcd, hcd_readb(hcd, 0x10) | BIT0, 0x10); ++ } ++ } ++#endif ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_SSDISABLED_PATCH) && (!defined(XHCI_DISABLE_SS_MODE)) ++ #if defined(XHCI_COMPANION) ++ if ((hcd->ehc_base != 0) && (hcd->companion.comp_port_addr != 0)) { ++ hdev = udev->parent; ++ if (hdev) { ++ if ((!hdev->parent) && (!hub_is_superspeed(hdev))) { ++ #if defined(XHCI_SSDISABLE_XUSB_PCIE_PATCH) ++ if (hcd->companion.port_index == 0) { ++ printk("[override value 00 @P0]\n"); ++ writeb((u8)((readb((void*)(_MSTAR_U3PHY_P0_DTOP_BASE+0x38*2)) & (u8)(~BIT2)) & (u8)(~BIT3)), ++ (void*)(_MSTAR_U3PHY_P0_DTOP_BASE+0x38*2)); // [3:2]='2b00 ++ } ++ #endif ++ ++ //check U3phy init done ++ if (readb((void *)(hcd->companion.u3top_base+0xEA*2)) & BIT0) { ++ value = readl((void *)(hcd->companion.comp_port_addr)); ++ if ( ((value>>5)&0xF) == 0x4 ) { ++ printk("Recover SS.Disable \n"); ++ value = (value & 0x4F00FE09) | 0x100A0; ++ writel(value, (void *)(hcd->companion.comp_port_addr)); ++ } ++ } ++ else { ++ printk("WARN: U3phy not yet ready \n"); ++ } ++ ++ #if defined(XHCI_SSDISABLE_POWERDOWN_PATCH) ++ if (hcd->companion.port_index == 0) { ++ if (readb((void *)(hcd->companion.u3top_base+0x2A*2)) & BIT4) { ++ udelay(5); ++ printk("[Non-override P0]\n"); ++ /* Override pipe_powerdown to P0 [4:3] = 2'b10 -> 2'b00 */ ++ writeb(readb((void *)(hcd->companion.u3top_base+0x2A*2)) & (u8)(~(BIT4|BIT3)), ++ (void *)(hcd->companion.u3top_base+0x2A*2)); ++ } ++ } ++ #endif ++ ++ #if defined(XHCI_SSDISABLE_XUSB_PCIE_PATCH) ++ if (hcd->companion.port_index == 0) { ++ printk("DPHY clock disable override P0\n"); ++ writeb((u8)(readb((void*)(_MSTAR_U3PHY_P0_DTOP_BASE+0x3C*2)) & (u8)(~BIT1)), ++ (void*)(_MSTAR_U3PHY_P0_DTOP_BASE+0x3C*2)); // [1]='2b0 ++ } ++ #endif ++ } ++ } ++ } ++ #else ++ if (hcd->xhci_base != 0) { ++ hdev = udev->parent; ++ if (hdev) { ++ if ((!hdev->parent) && (!hub_is_superspeed(hdev))) { ++ value = readl((void *)(hcd->xhci_base + XHC_SSPORT_OFFSET)); ++ if ( ((value>>5)&0xF) == 0x4) { ++ printk("Recover SS.Disable \n"); ++ value = (value & 0x4F00FE09) | 0x100A0; ++ writel(value, (void *)(hcd->xhci_base + XHC_SSPORT_OFFSET)); ++ } ++ } ++ } ++ } ++ #endif ++#endif ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_HS_FORCE_CURRENT) ++ if ((hcd->xhci_base != 0) &&(hcd->utmi_base != 0)) { ++ hdev = udev->parent; ++ if (hdev) { ++ if (!hdev->parent) { ++ if (readb((void *)(hcd->utmi_base+0x06*2)) & BIT2 ) { ++ writeb(readb((void *)(hcd->utmi_base+0x06*2)) & (u8)(~BIT2), ++ (void *) (hcd->utmi_base+0x06*2)); //Disable HS TX current ++ } ++ } ++ } ++ } ++#endif ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_SSC_QUIRK_PATCH) ++ //---Add quirks patch for SS_SSC---- ++ if (hcd->ms_flag & MS_FLAG_P0_SSC) { ++ writew(0x04D0, (void *)(hcd->u3dphy_base[0]+0xC6*2)); ++ hcd->ms_flag &= ~MS_FLAG_P0_SSC; ++ } ++ if (hcd->ms_flag & MS_FLAG_P1_SSC) { ++ writew(0x04D0, (void *)(hcd->u3dphy_base[1]+0xC6*2)); ++ hcd->ms_flag &= ~MS_FLAG_P1_SSC; ++ } ++#endif ++ + + /* mark the device as inactive, so any further urb submissions for + * this device (and any of its children) will fail immediately. +@@ -2159,6 +2339,30 @@ void usb_disconnect(struct usb_device **pdev) + hub_free_dev(udev); + + put_device(&udev->dev); ++#if (MP_USB_MSTAR==1) // HOTPLUG, tony add for dvice read/write hotplug ++ if ((hcd->ehc_base != 0) && (hcd->root_port_devnum == devnum)) ++ { ++ printk("root hub reinitial [usbdis]\n"); ++ hcd->driver->stop(hcd); ++ hcd->driver->reset(hcd); ++ hcd->driver->start(hcd); ++ ++ hcd->root_port_devnum=0; ++ hcd->enum_port_flag=0; ++ hcd->enum_dbreset_flag=0; ++ hcd_writeb(hcd, hcd_readb(hcd, 0x40) & (u8)(~BIT7), 0x40); //clear force full speed ++ #if defined(USB_MAC_SRAM_POWER_DOWN_ENABLE) ++ /* BIT6: periodic schedule, BIT7: asynchronous schedule */ ++ if ((hcd_readb(hcd, 0x15) & (BIT6 | BIT7)) == 0) ++ usb20mac_sram_power_saving(hcd, true); ++ #endif ++ } ++ #if defined(USB3_MAC_SRAM_POWER_DOWN_ENABLE) ++ if ((hcd->xhci_base != 0) && (hcd->root_port_devnum == devnum)) { ++ usb30mac_sram_power_saving(hcd, true); ++ } ++ #endif ++#endif + } + + #ifdef CONFIG_USB_ANNOUNCE_NEW_DEVICES +@@ -2216,7 +2420,7 @@ static int usb_enumerate_device_otg(struct usb_device *udev) + /* descriptor may appear anywhere in config */ + err = __usb_get_extra_descriptor(udev->rawdescriptors[0], + le16_to_cpu(udev->config[0].desc.wTotalLength), +- USB_DT_OTG, (void **) &desc); ++ USB_DT_OTG, (void **) &desc, sizeof(*desc)); + if (err || !(desc->bmAttributes & USB_OTG_HNP)) + return 0; + +@@ -2295,7 +2499,21 @@ static int usb_enumerate_device(struct usb_device *udev) + udev->manufacturer = usb_cache_string(udev, + udev->descriptor.iManufacturer); + udev->serial = usb_cache_string(udev, udev->descriptor.iSerialNumber); ++#if (MP_USB_MSTAR==1) ++ if ((le16_to_cpu(udev->descriptor.idVendor) == 0x8065) ++ && (le16_to_cpu(udev->descriptor.idProduct) == 0x6000)) ++ { ++ if (udev->manufacturer) { ++ char manufacturer[] = {0x73, 0x73, 0x74, 0x61, 0x72, 0x00}; ++ memcpy(udev->manufacturer, manufacturer, sizeof(manufacturer)); ++ } + ++ if (udev->product) { ++ char product[] = {0x73, 0x73, 0x74, 0x61, 0x72, 0x20, 0x55, 0x53, 0x42, 0x00}; ++ memcpy(udev->product, product, sizeof(product)); ++ } ++ } ++#endif + err = usb_enumerate_device_otg(udev); + if (err < 0) + return err; +@@ -2444,6 +2662,14 @@ int usb_new_device(struct usb_device *udev) + if (udev->parent) + set_usb_port_removable(udev); + ++#if (MP_USB_MSTAR==1) ++ if((le16_to_cpu(udev->descriptor.idVendor) == 0x0dd8) ++ && (le16_to_cpu(udev->descriptor.idProduct) == 0x2005)) ++ { ++ /* OnlyDisk: Add more delay to wait device ready */ ++ msleep(500); ++ } ++#endif + /* Register the device. The device driver is responsible + * for configuring the device and invoking the add-device + * notifier chain (used by usbfs and possibly others). +@@ -2636,6 +2862,13 @@ static bool hub_port_warm_reset_required(struct usb_hub *hub, int port1, + u16 portstatus) + { + u16 link_state; ++#if (MP_USB_MSTAR==1) && defined(XHCI_DISABLE_COMPLIANCE) ++ struct usb_hcd *hcd = bus_to_hcd(hub->hdev->bus); ++ u8 bDisableComp=0; ++ ++ if (hcd->xhci_base) ++ bDisableComp = readb((void*)(hcd->xhci_base+0x6817)) & BIT7; ++#endif + + if (!hub_is_superspeed(hub->hdev)) + return false; +@@ -2645,7 +2878,14 @@ static bool hub_port_warm_reset_required(struct usb_hub *hub, int port1, + + link_state = portstatus & USB_PORT_STAT_LINK_STATE; + return link_state == USB_SS_PORT_LS_SS_INACTIVE ++#if (MP_USB_MSTAR==1) && defined(XHCI_DISABLE_TESTMODE) ++ || link_state == USB_SS_PORT_LS_LOOPBACK ++#endif ++#if (MP_USB_MSTAR==1) && defined(XHCI_DISABLE_COMPLIANCE) ++ || ((link_state == USB_SS_PORT_LS_COMP_MOD) && bDisableComp); ++#else + || link_state == USB_SS_PORT_LS_COMP_MOD; ++#endif + } + + static int hub_port_wait_reset(struct usb_hub *hub, int port1, +@@ -2656,12 +2896,36 @@ static int hub_port_wait_reset(struct usb_hub *hub, int port1, + u16 portchange; + u32 ext_portstatus = 0; + ++#if (MP_USB_MSTAR==1) ++ struct usb_device *hdev = hub->hdev; ++ struct usb_hcd *hcd = bus_to_hcd(hdev->bus); ++ #if !defined(ENABLE_NEW_HW_CHRIP_PATCH) //_USB_HS_CHIRP_PATCH ++ u8 bRestore = 1; ++ #endif ++ if(hcd->reduce_wait_reset_time_flag == 1) { ++ if(delay >=30){ ++ delay -= 30; ++ printk("Reduce wait reset time to %d\n", delay); ++ } ++ } ++#endif ++ + for (delay_time = 0; + delay_time < HUB_RESET_TIMEOUT; + delay_time += delay) { + /* wait to give the device a chance to reset */ + msleep(delay); + ++#if (MP_USB_MSTAR==1) && !defined(ENABLE_NEW_HW_CHRIP_PATCH) //_USB_HS_CHIRP_PATCH ++ if ((hcd->utmi_base) && (hcd->ehc_base) && ++ (!hub->hdev->parent) && bRestore) { ++ /* Chirp K detection level: 0x80 => 400mv, 0x20 => 575mv */ ++ writeb(UTMI_DISCON_LEVEL_2A , (void*)(hcd->utmi_base+0x2A*2)); ++ msleep(20); ++ bRestore = 0; ++ } ++#endif ++ + /* read and decode port status */ + if (hub_is_superspeedplus(hub->hdev)) + ret = hub_ext_port_status(hub, port1, +@@ -2735,6 +2999,83 @@ static int hub_port_wait_reset(struct usb_hub *hub, int port1, + udev->speed = USB_SPEED_LOW; + else + udev->speed = USB_SPEED_FULL; ++ ++#if (MP_USB_MSTAR==1) ++ if ((hcd->ehc_base) && (!hub->hdev->parent) && ++ (udev->speed != USB_SPEED_WIRELESS)) ++ { ++ #if defined(_USB_SPEED_REPORT_RESET_PATCH) && (_USB_SPEED_REPORT_RESET_PATCH) ++ u8 spd_val; ++ #define SPD_HS 0x0C ++ #define SPD_FS 0x06 ++ #define SPD_LS 0x05 ++ ++ spd_val = (hcd_readb(hcd, 0x84) & BIT7) >> 7; ++ spd_val |= (hcd_readb(hcd, 0x85) & 0x0F) << 1; ++ ++ switch(udev->speed) { ++ case USB_SPEED_LOW: ++ if (spd_val != SPD_LS) ++ udev->speed = USB_SPEED_UNKNOWN; ++ break; ++ ++ case USB_SPEED_FULL: ++ if (spd_val != SPD_FS) ++ udev->speed = USB_SPEED_UNKNOWN; ++ break; ++ ++ case USB_SPEED_HIGH: ++ if (spd_val != SPD_HS) ++ udev->speed = USB_SPEED_UNKNOWN; ++ break; ++ ++ default: ++ break; ++ } ++ if (udev->speed == USB_SPEED_UNKNOWN) { ++ printk("[USB unknown speed] DBUS_SPEED:0x%x UHC:0x%x\n", spd_val, hcd_readb(hcd, 0x41)); ++ } ++ #endif ++ ++ if(udev->speed == USB_SPEED_HIGH){ ++ hub->hdev->speed = USB_SPEED_HIGH; ++ ++#if 0 /* move HS EOF1 setting to later */ ++ /* improve performace 20120405 */ ++ #if defined(ENABLE_12US_EOF1) ++ /* set minimum EOF1 time for performance */ ++ /* enlarge EOP1 from 12us to 16us for babble prvention under hub case 20130121 */ ++ hcd_writeb(hcd, (hcd_readb(hcd, 0x34) & (u8)(~BIT3)) | BIT2, 0x34); ++ #else ++ //tony add for Babble issue (HS) ++ //"1.Babble issue (EOF1): (1) if device is HS => bit <3:2> set 11 (2) ifdevice is FS => bit <3:2> set 10" ++ hcd_writeb(hcd, hcd_readb(hcd, 0x34) | (BIT3|BIT2), 0x34); ++ //printk("HS 4868:%x\n", hcd_readb(hcd, 0x34)); ++ #endif ++#endif ++ } else if(udev->speed == USB_SPEED_FULL){ ++ hub->hdev->speed=USB_SPEED_FULL; ++ //tony add for Babble issue (FS) ++ //"1.Babble issue (EOF1): (1) if device is HS => bit <3:2> set 11 (2) ifdevice is FS => bit <3:2> set 10" ++ hcd_writeb(hcd, hcd_readb(hcd, 0x34) | BIT3, 0x34); ++ hcd_writeb(hcd, hcd_readb(hcd, 0x34) & (u8)(~BIT2), 0x34); ++ //printk("FS 4868:%x\n", hcd_readb(hcd, 0x34)); ++ } else if(udev->speed == USB_SPEED_LOW){ ++ hub->hdev->speed=USB_SPEED_LOW; ++ }else{ ++ printk("unknow port1 usb device speed\n"); ++ return -ENOTCONN; ++ } ++ } ++ /* Benson_20130529: set UTMI force full speed hub driving timing */ ++ if ((hcd->utmi_base!=0) && (!hub->hdev->parent)) ++ { ++ if (hub->hdev->speed == USB_SPEED_FULL) ++ writeb(readb((void*)(hcd->utmi_base+0x03*2-1)) | BIT2, (void*)(hcd->utmi_base+0x03*2-1)); ++ else ++ writeb(readb((void*)(hcd->utmi_base+0x03*2-1)) & (u8)(~BIT2), (void*)(hcd->utmi_base+0x03*2-1)); ++ } ++#endif + return 0; + } + +@@ -2745,6 +3086,15 @@ static int hub_port_reset(struct usb_hub *hub, int port1, + int i, status; + u16 portchange, portstatus; + struct usb_port *port_dev = hub->ports[port1 - 1]; ++#if (MP_USB_MSTAR==1) ++ struct usb_device *hdev = hub->hdev; ++ bool bU2RH = false; ++ struct usb_hcd *hcd; ++ #if (_USB_XIU_TIMEOUT_PATCH) ++ unsigned long flag=0; ++ #endif ++#endif ++ + + if (!hub_is_superspeed(hub->hdev)) { + if (warm) { +@@ -2768,8 +3118,62 @@ static int hub_port_reset(struct usb_hub *hub, int port1, + } + clear_bit(port1, hub->warm_reset_bits); + ++#if (MP_USB_MSTAR==1) ++ hcd = bus_to_hcd(hdev->bus); ++ ++ /* _USB_HS_CHIRP_PATCH */ ++ if ((hcd->utmi_base) && (!hdev->parent) && (!hub_is_superspeed(hub->hdev))) { ++ bU2RH = true; ++ } ++ ++ #if (_UTMI_PWR_SAV_MODE_ENABLE) ++ if ( (hdev->parent == NULL) && !hub_is_superspeed(hub->hdev) ) ++ { ++ usb_power_saving_enable(hcd, false); ++ } ++ #endif ++ ++ #ifdef USB_MAC_SRAM_POWER_DOWN_ENABLE ++ if (hdev->parent == NULL && hcd->ehc_base != 0) ++ usb20mac_sram_power_saving(hcd, false); ++ #endif ++ #ifdef USB3_MAC_SRAM_POWER_DOWN_ENABLE ++ if (hdev->parent == NULL && hcd->xhci_base != 0) ++ usb30mac_sram_power_saving(hcd, false); ++ #endif ++ ++ #if (_USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH) ++ /* turn off overwrite mode */ ++ if ((hcd->utmi_base != 0) && (hdev->parent == NULL)) ++ { ++ writeb(readb((void*)(hcd->utmi_base+0x0*2)) & (u8)(~BIT1), (void*) (hcd->utmi_base+0x0*2)); //tern_ov = 0 ++ /* new HW term overwrite: off */ ++ writeb(readb((void*)(hcd->utmi_base+0x52*2)) & (u8)(~(BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0)), (void*) (hcd->utmi_base+0x52*2)); ++ } ++ #endif ++#endif ++ + /* Reset the port */ + for (i = 0; i < PORT_RESET_TRIES; i++) { ++ ++#if (MP_USB_MSTAR==1) //_USB_HS_CHIRP_PATCH ++ if (bU2RH) ++ { ++ writeb(0x10, (void*)(hcd->utmi_base+0x2C*2)); ++ writeb(0x00, (void*)(hcd->utmi_base+0x2D*2-1)); ++ writeb(0x00, (void*)(hcd->utmi_base+0x2E*2)); ++ writeb(0x00, (void*)(hcd->utmi_base+0x2F*2-1)); ++ #if !defined(ENABLE_NEW_HW_CHRIP_PATCH) ++ writeb(0x80 ,(void*)(hcd->utmi_base+0x2A*2)); ++ #endif ++ ++ /* make sure RUN is enabled for EHC */ ++ if((hcd->ehc_base != 0) && !(hcd_readb(hcd, 0x10) & BIT0)) ++ hcd_writeb(hcd, hcd_readb(hcd, 0x10) | BIT0, 0x10); ++ } ++#endif ++ + status = set_port_feature(hub->hdev, port1, (warm ? + USB_PORT_FEAT_BH_PORT_RESET : + USB_PORT_FEAT_RESET)); +@@ -2786,8 +3190,36 @@ static int hub_port_reset(struct usb_hub *hub, int port1, + dev_dbg(hub->intfdev, + "port_wait_reset: err = %d\n", + status); ++#if (MP_USB_MSTAR==1) && _USB_CLEAR_PORT_ENABLE_AFTER_FAIL_RESET_PATCH ++ if ((!hdev->parent) && hcd->ehc_base && ((hcd_readb(hcd, 0x30) & BIT0) == 0x0)) ++ { ++ hcd_writeb(hcd, hcd_readb(hcd, 0x30) & (u8)(~(BIT5 | BIT3 | BIT2 | BIT1)), 0x30); ++ } ++#endif + } + ++#if (MP_USB_MSTAR==1) ++ if (bU2RH) //_USB_HS_CHIRP_PATCH ++ { ++ writeb(UTMI_EYE_SETTING_2C, (void*)(hcd->utmi_base+0x2C*2)); ++ writeb(UTMI_EYE_SETTING_2D, (void*)(hcd->utmi_base+0x2D*2-1)); ++ writeb(UTMI_EYE_SETTING_2E, (void*)(hcd->utmi_base+0x2E*2)); ++ writeb(UTMI_EYE_SETTING_2F, (void*)(hcd->utmi_base+0x2F*2-1)); ++ #if !defined(ENABLE_NEW_HW_CHRIP_PATCH) ++ writeb(UTMI_DISCON_LEVEL_2A , (void*)(hcd->utmi_base+0x2A*2)); ++ #endif ++ ++ #if _USB_XIU_TIMEOUT_PATCH ++ spin_lock_irqsave (&(hcd->usb_reset_lock), flag); ++ #endif ++ writeb(readb((void*)(hcd->utmi_base+0x06*2)) | (BIT1|BIT0), (void*)(hcd->utmi_base+0x06*2)); // reset UTMI ++ writeb(readb((void*)(hcd->utmi_base+0x06*2)) & (u8)(~(BIT1|BIT0)), (void*)(hcd->utmi_base+0x06*2)); // clear reset UTMI ++ #if _USB_XIU_TIMEOUT_PATCH ++ spin_unlock_irqrestore (&(hcd->usb_reset_lock), flag); ++ #endif ++ } ++#endif ++ + /* Check for disconnect or reset */ + if (status == 0 || status == -ENOTCONN || status == -ENODEV) { + usb_clear_port_feature(hub->hdev, port1, +@@ -2826,6 +3258,10 @@ static int hub_port_reset(struct usb_hub *hub, int port1, + } + } + ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ if ( is_suspending()) ++ goto done; ++#endif /* CONFIG_MP_USB_STR_PATCH */ + dev_dbg(&port_dev->dev, + "not enabled, trying %sreset again...\n", + warm ? "warm " : ""); +@@ -2926,6 +3362,13 @@ static int check_port_resume_type(struct usb_device *udev, + && hub_port_warm_reset_required(hub, port1, portstatus)) { + /* pass */; + } ++ #if (MP_USB_MSTAR==1) ++ else if ((status >= 0) && hub_is_superspeed(hub->hdev)) ++ { ++ printk("Force USB 3.0 disconnect\n"); ++ status = -ENODEV; ++ } ++ #endif + /* Is the device still present? */ + else if (status || port_is_suspended(hub, portstatus) || + !port_is_power_on(hub, portstatus)) { +@@ -3345,6 +3788,7 @@ static int finish_port_resume(struct usb_device *udev) + * + * This routine should only be called when persist is enabled. + */ ++#if (MP_USB_MSTAR==0) + static int wait_for_connected(struct usb_device *udev, + struct usb_hub *hub, int *port1, + u16 *portchange, u16 *portstatus) +@@ -3361,6 +3805,7 @@ static int wait_for_connected(struct usb_device *udev, + dev_dbg(&udev->dev, "Waited %dms for CONNECT\n", delay_ms); + return status; + } ++#endif + + /* + * usb_port_resume - re-activate a suspended usb device's upstream port +@@ -3458,9 +3903,20 @@ int usb_port_resume(struct usb_device *udev, pm_message_t msg) + } + } + ++ #if (MP_USB_MSTAR==1) ++ if (hub_is_superspeed(hub->hdev)) { ++ printk("usb_port_resume : warm_reset\n"); ++ hub_port_reset(hub, port1, NULL, HUB_BH_RESET_TIME, true); ++ } ++ #endif ++ ++#if (MP_USB_MSTAR==1) ++ // Before exist USB3.0 persist device requirement, remove ss_enable waiting to speed up resume time. ++#else + if (udev->persist_enabled) + status = wait_for_connected(udev, hub, &port1, &portchange, + &portstatus); ++#endif + + status = check_port_resume_type(udev, + hub, port1, status, portchange, portstatus); +@@ -3468,7 +3924,20 @@ int usb_port_resume(struct usb_device *udev, pm_message_t msg) + status = finish_port_resume(udev); + if (status < 0) { + dev_dbg(&udev->dev, "can't resume, status %d\n", status); ++#if (MP_USB_MSTAR==1) ++ if (hub_is_superspeed(hub->hdev) && !hub->hdev->parent) { ++ printk("[USB] Set hub change in SS resume\n"); ++ if (hub->ports[port1 - 1]->child) ++ usb_set_device_state(hub->ports[port1 - 1]->child, ++ USB_STATE_NOTATTACHED); ++ set_bit(port1, hub->change_bits); ++ kick_hub_wq(hub); ++ } ++ else ++ hub_port_logical_disconnect(hub, port1); ++#else + hub_port_logical_disconnect(hub, port1); ++#endif + } else { + /* Try to enable USB2 hardware LPM */ + if (udev->usb2_hw_lpm_capable == 1) +@@ -3536,7 +4005,11 @@ static int hub_handle_remote_wakeup(struct usb_hub *hub, unsigned int port, + connect_change = 1; + } else { + ret = -ENODEV; ++#if (MP_USB_MSTAR==1) ++ hub_port_disable(hub, (int)port, 1, 0); ++#else + hub_port_disable(hub, port, 1); ++#endif + } + dev_dbg(&port_dev->dev, "resume, status %d\n", ret); + return connect_change; +@@ -4093,6 +4566,110 @@ void usb_unlocked_enable_lpm(struct usb_device *udev) + } + EXPORT_SYMBOL_GPL(usb_unlocked_enable_lpm); + ++/* ++ * If USB 3.0 ports are placed into the Disabled state, they will no longer ++ * detect any device connects or disconnects. This is generally not what the ++ * USB core wants, since it expects a disabled port to produce a port status ++ * change event when a new device connects. ++ * ++ * Instead, set the link state to Disabled, wait for the link to settle into ++ * that state, clear any change bits, and then put the port into the RxDetect ++ * state. ++ */ ++#if (MP_USB_MSTAR==1) ++static int mstar_hub_usb3_port_disable(struct usb_hub *hub, int port1, int set_disable) ++{ ++ struct usb_device *hdev = hub->hdev; ++ #if defined(XHCI_SSDISABLED_PATCH) && defined(XHCI_SSDISABLE_POWERDOWN_PATCH) ++ struct usb_hcd *hcd = bus_to_hcd(hdev->bus); ++ #endif ++ int ret = 0; ++ int total_time; ++ u16 portchange, portstatus; ++ ++ if (!hub_is_superspeed(hub->hdev)) ++ return -EINVAL; ++ ++ ret = hub_port_status(hub, port1, &portstatus, &portchange); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * USB controller Advanced Micro Devices, Inc. [AMD] FCH USB XHCI ++ * Controller [1022:7814] will have spurious result making the following ++ * usb 3.0 device hotplugging route to the 2.0 root hub and recognized ++ * as high-speed device if we set the usb 3.0 port link state to ++ * Disabled. Since it's already in USB_SS_PORT_LS_RX_DETECT state, we ++ * check the state here to avoid the bug. ++ */ ++ /* ++ * MStar swings port speed while in USB_SS_PORT_LS_RX_DETECT state, ++ * we could not apply this AMD quirk patch ++ */ ++ ++ if ((portstatus & USB_PORT_STAT_LINK_STATE) == USB_SS_PORT_LS_SS_DISABLED) ++ return 0; ++ ++ printk("mstar_hub_port_disable \n"); ++ ++ if (!hdev->parent) { ++ ret = usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_ENABLE); ++ } ++ else { ++ ret = hub_set_port_link_state(hub, port1, USB_SS_PORT_LS_SS_DISABLED); ++ } ++ ++ if (ret) { ++ dev_err(hub->intfdev, "cannot disable port %d (err = %d)\n", ++ port1, ret); ++ return ret; ++ } ++ ++ /* Wait for the link to enter the disabled state. */ ++ for (total_time = 0; ; total_time += HUB_DEBOUNCE_STEP) { ++ ret = hub_port_status(hub, port1, &portstatus, &portchange); ++ if (ret < 0) ++ return ret; ++ ++ if ((portstatus & USB_PORT_STAT_LINK_STATE) == ++ USB_SS_PORT_LS_SS_DISABLED) ++ break; ++ if (total_time >= HUB_DEBOUNCE_TIMEOUT) ++ break; ++ msleep(HUB_DEBOUNCE_STEP); ++ } ++ if (total_time >= HUB_DEBOUNCE_TIMEOUT) ++ printk("Could not disable port %d after %d ms\n", port1, total_time); ++ ++ #if defined(XHCI_SSDISABLED_PATCH) ++ if ((!set_disable) || (hdev->parent != NULL)) ++ { ++ ret = hub_set_port_link_state(hub, port1, USB_SS_PORT_LS_RX_DETECT); ++ ++ #if defined(XHCI_SSDISABLE_POWERDOWN_PATCH) ++ if ((!hdev->parent) ) { ++ if (hcd->u3top_base && port1 == 1) { ++ if (readb((void *)(hcd->u3top_base+0x2A*2)) & BIT4) { ++ udelay(5); ++ printk("[Non-override P0]\n"); ++ /* Override pipe_powerdown to P0 [4:3] = 2'b10 -> 2'b00 */ ++ writeb(readb((void *)(hcd->u3top_base+0x2A*2)) & (u8)(~(BIT4|BIT3)), ++ (void *)(hcd->u3top_base+0x2A*2)); ++ } ++ } ++ } ++ #endif ++ return ret; ++ } ++ #else ++ return hub_set_port_link_state(hub, port1, USB_SS_PORT_LS_RX_DETECT); ++ #endif ++ ++ return ret; ++} ++#endif ++ ++#if (MP_USB_MSTAR==0) + /* usb3 devices use U3 for disabled, make sure remote wakeup is disabled */ + static void hub_usb3_port_prepare_disable(struct usb_hub *hub, + struct usb_port *port_dev) +@@ -4113,6 +4690,7 @@ static void hub_usb3_port_prepare_disable(struct usb_hub *hub, + udev->do_remote_wakeup = 0; + } + } ++#endif + + #else /* CONFIG_PM */ + +@@ -4163,17 +4741,29 @@ static int hub_handle_remote_wakeup(struct usb_hub *hub, unsigned int port, + * a connection with a plugged-in cable but will signal the host when the cable + * is unplugged. Disable remote wake and set link state to U3 for USB-3 devices + */ ++#if (MP_USB_MSTAR==1) ++static int hub_port_disable(struct usb_hub *hub, int port1, int set_state, int set_disable) ++#else + static int hub_port_disable(struct usb_hub *hub, int port1, int set_state) ++#endif + { + struct usb_port *port_dev = hub->ports[port1 - 1]; + struct usb_device *hdev = hub->hdev; + int ret = 0; + ++#if (MP_USB_MSTAR==1) ++ printk("hub_port_disable: %d hub->err: %d \n", set_disable, hub->error); ++#endif ++ + if (!hub->error) { + if (hub_is_superspeed(hub->hdev)) { ++#if (MP_USB_MSTAR==1) && defined(CONFIG_PM) ++ ret = mstar_hub_usb3_port_disable(hub, port1, set_disable); ++#else + hub_usb3_port_prepare_disable(hub, port_dev); + ret = hub_set_port_link_state(hub, port_dev->portnum, + USB_SS_PORT_LS_U3); ++#endif + } else { + ret = usb_clear_port_feature(hdev, port1, + USB_PORT_FEAT_ENABLE); +@@ -4230,6 +4820,9 @@ int hub_port_debounce(struct usb_hub *hub, int port1, bool must_be_connected) + if (portchange & USB_PORT_STAT_C_CONNECTION) { + usb_clear_port_feature(hub->hdev, port1, + USB_PORT_FEAT_C_CONNECTION); ++#if (MP_USB_MSTAR==1) ++ total_time = 0; // reset the counter //Colin, 100310, for Plug-in/out quickly ++#endif + } + + if (total_time >= HUB_DEBOUNCE_TIMEOUT) +@@ -4349,10 +4942,31 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + const char *speed; + int devnum = udev->devnum; + ++#if (MP_USB_MSTAR==1) && defined(XHCI_ENABLE_LS_UEVENT) ++ char *event_string = NULL; ++ char *envp[2]; ++#endif ++ ++#if (MP_USB_MSTAR==1) ++ int bus_reset_retry=0; ++ ++ if (hcd->ehc_base != 0) ++ printk("==%s==> hub_port_init %d #%d\n", EHCI_MSTAR_VERSION, port1, retry_counter); ++ else if (hcd->xhci_base != 0) ++ printk("==> hub_port_init_%s %d \n", XHCI_MSTAR_VERSION, port1); ++#endif ++ + /* root hub ports have a slightly longer reset period + * (from USB 2.0 spec, section 7.1.7.5) + */ + if (!hdev->parent) { ++#if (MP_USB_MSTAR==1) ++ printk("Plug in USB Port%d\n", hcd->port_index); ++ hcd->enum_port_flag=2; //initial enum_port1_flag ++#endif ++#if (MP_USB_MSTAR==1) ++ hcd->root_port_devnum = devnum; //tony HOTPLUG ++#endif + delay = HUB_ROOT_RESET_TIME; + if (port1 == hdev->bus->otg_port) + hdev->bus->b_hnp_enable = 0; +@@ -4365,11 +4979,29 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + + mutex_lock(hcd->address0_mutex); + ++#if (MP_USB_MSTAR==1) ++do_port_reset: ++#endif ++ + /* Reset the device; full speed may morph to high speed */ + /* FIXME a USB 2.0 device may morph into SuperSpeed on reset. */ + retval = hub_port_reset(hub, port1, udev, delay, false); + if (retval < 0) /* error or disconnect */ + goto fail; ++ ++#if (MP_USB_MSTAR==1) ++ /* Go fail, if there is no enable bit for EHCI */ ++ if (hcd->ehc_base && (!hdev->parent)) ++ { ++ if(!(hcd_readb(hcd, 0x30) & BIT2)) ++ { ++ printk("[USB] ERR, after reset no PE: port status 0x%x\n", hcd_readb(hcd, 0x30)); ++ retval = -ENODEV; ++ goto fail; ++ } ++ } ++#endif ++ + /* success, speed is known */ + + retval = -ENODEV; +@@ -4421,12 +5053,63 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + (udev->config) ? "reset" : "new", speed, + devnum, udev->bus->controller->driver->name); + ++#if (MP_USB_MSTAR==1) && defined(XHCI_DISABLE_LS) ++ if ((hcd->xhci_base != 0) && (hub->hdev->parent == NULL) && (udev->speed == USB_SPEED_LOW)) ++ { ++ printk("USB LS not support !\n"); ++ retval = -ENOTCONN; // Don't retry ++ ++ #if defined(XHCI_ENABLE_LS_UEVENT) ++ event_string = kmalloc(40, GFP_KERNEL); ++ if (!event_string) { ++ printk("!! uevent kmalloc fail !!\n"); ++ goto fail; ++ } ++ sprintf(event_string, "USBLS=NOT SUPPORT"); ++ envp[0] = event_string; ++ envp[1] = NULL; ++ printk("Send LS uevent\n"); ++ kobject_uevent_env(&hub->hdev->dev.kobj, KOBJ_ADD, envp); ++ kfree(event_string); ++ #endif ++ ++ goto fail; ++ } ++#endif ++ ++#if (MP_USB_MSTAR==1) ++ #ifdef XHCI_IPACKET_DELAY_PATCH ++ if ((hcd->xhci_base != 0) && (!hdev->parent)) { ++ switch (udev->speed) { ++ case USB_SPEED_LOW: ++ case USB_SPEED_FULL: ++ // delay between SOF and 1st packet ++ writeb(readb((void*)(hcd->xhci_base+0x430F)) | (BIT7|BIT6), (void*)(hcd->xhci_base+0x430F)); //Inter packet delay (bit6~7 = "11") ++ break; ++ case USB_SPEED_HIGH: ++ // delay between SOF and 1st packet ++ writeb(readb((void*)(hcd->xhci_base+0x430F)) & (u8)(~(BIT7|BIT6)), (void*)(hcd->xhci_base+0x430F)); //Inter packet delay (bit6~7 = "00") ++ break; ++ default: break; ++ } ++ } ++ #endif /* XHCI_IPACKET_DELAY_PATCH */ ++#endif ++ + /* Set up TT records, if needed */ + if (hdev->tt) { + udev->tt = hdev->tt; + udev->ttport = hdev->ttport; +- } else if (udev->speed != USB_SPEED_HIGH ++ } ++#if (MP_USB_MSTAR==1) ++ /* After kernel 4, FS and LS devices connect through external high speed hub or ++ connect direct to MStar EHCI root hub need tt */ ++ else if (udev->speed < USB_SPEED_HIGH ++ && (hdev->parent == NULL || hdev->speed == USB_SPEED_HIGH)) { ++#else ++ else if (udev->speed != USB_SPEED_HIGH + && hdev->speed == USB_SPEED_HIGH) { ++#endif + if (!hub->tt.hub) { + dev_err(&udev->dev, "parent hub has no TT\n"); + retval = -EINVAL; +@@ -4476,12 +5159,69 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + * 512 (WUSB1.0[4.8.1]). + */ + for (operations = 0; operations < 3; ++operations) { ++#if (MP_USB_MSTAR==1) ++ u16 portchange, portstatus; ++ ++ if (hub_port_status(hub, port1, &portstatus, &portchange) == 0) ++ { ++ //printk("[USB] portstatus: 0x%x, portchange: 0x%x\n", portstatus, portchange); ++ if (portchange & USB_PORT_STAT_C_CONNECTION) ++ { ++ printk("[USB] ERR, 1st get_dev_desc CSC: status 0x%x change 0x%x\n", portstatus, portchange); ++ retval = -ENOTCONN; ++ kfree(buf); ++ goto fail; ++ } ++ ++ if (!(portstatus & USB_PORT_STAT_ENABLE)) ++ { ++ printk("[USB] ERR, 1st get_dev_desc no PE status 0x%x change 0x%x\n", portstatus, portchange); ++ retval = -ENODEV; ++ kfree(buf); ++ goto fail; ++ } ++ } ++ else ++ { ++ printk("[USB] WAR, can not get port status\n"); ++ } ++#endif + buf->bMaxPacketSize0 = 0; + r = usb_control_msg(udev, usb_rcvaddr0pipe(), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + USB_DT_DEVICE << 8, 0, + buf, GET_DESCRIPTOR_BUFSIZE, + initial_descriptor_timeout); ++ ++#if (MP_USB_MSTAR==1) ++ /* Patch for MTK WIFI dongle (idVendor=148f, idProduct=7601) ++ * only works on High Speed. ++ */ ++ //printk("[USB dbg] max pkt size0 %d, r = %d\n", buf->bMaxPacketSize0, r); ++ if ( (r == USB_DT_DEVICE_SIZE) ) ++ { ++ if((buf->idVendor == 0x148F) && ++ (buf->idProduct == 0x7601) ) ++ { ++ if ((udev->speed != USB_SPEED_HIGH)) ++ { ++ bus_reset_retry++; ++ kfree(buf); ++ if (bus_reset_retry < 6) { ++ printk("## Hello FS MTK WIFI. Go HS retry : %d !\n", bus_reset_retry); ++ oldspeed = USB_SPEED_UNKNOWN; ++ goto do_port_reset; ++ } else { ++ printk("## FS MTK WIFI retry fail !!!!\n"); ++ hcd->enum_port_flag = 1; ++ retval = -ENOTSUPP; ++ goto fail; ++ } ++ } ++ } ++ } ++#endif ++ + switch (buf->bMaxPacketSize0) { + case 8: case 16: case 32: case 64: case 255: + if (buf->bDescriptorType == +@@ -4503,11 +5243,32 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + */ + if (r == 0 || (r == -ETIMEDOUT && retries == 0)) + break; ++ ++#if defined(CONFIG_SUSPEND) && (MP_USB_STR_PATCH==1) ++ if ( (r == -ETIMEDOUT) && (is_suspending()) ) ++ { ++ printk("[USB] ERR, get_dev_desc timeout when is suspending...\n"); ++ retval = -ENOTCONN; ++ kfree(buf); ++ goto fail; ++ } ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ ++ + } + udev->descriptor.bMaxPacketSize0 = + buf->bMaxPacketSize0; + kfree(buf); +- ++#if (MP_USB_MSTAR==1) && _USB_FRIENDLY_CUSTOMER_PATCH ++ /* patch for special card reader ++ * 1) Kwangwon Electronics, UHC381 hub + card reader ++ */ ++ if((le16_to_cpu(hdev->descriptor.idVendor) == 0x0409) && (le16_to_cpu(hdev->descriptor.idProduct) == 0x005a)) ++ { ++ dev_dbg(&udev->dev, "[USB] device reset again is not needed\n"); ++ retval = 0; ++ } ++ else ++#endif + retval = hub_port_reset(hub, port1, udev, delay, false); + if (retval < 0) /* error or disconnect */ + goto fail; +@@ -4639,6 +5400,16 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + } + } + ++#if (MP_USB_MSTAR==1) ++ if((le16_to_cpu(udev->descriptor.idVendor) == 0x066F) ++ && (le16_to_cpu(udev->descriptor.idProduct) == 0x857C)) ++ { ++ /* Aigo MP3 : Add more delay to wait device ready */ ++ msleep (400); ++ } ++ hcd->reduce_wait_reset_time_flag = 0; ++#endif ++ + retval = 0; + /* notify HCD that we have a device connected and addressed */ + if (hcd->driver->update_device) +@@ -4646,7 +5417,14 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, + hub_set_initial_usb2_lpm_policy(udev); + fail: + if (retval) { ++#if (MP_USB_MSTAR==1) ++ /* also consider PLS at in-active case */ ++ if (retval != -ENODEV) ++ hcd->reduce_wait_reset_time_flag = 1; ++ hub_port_disable(hub, port1, 0, (retval == -ENOTCONN) ? 0 : 1); ++#else + hub_port_disable(hub, port1, 0); ++#endif + update_devnum(udev, devnum); /* for disconnect processing */ + } + mutex_unlock(hcd->address0_mutex); +@@ -4764,6 +5542,26 @@ static void hub_port_connect(struct usb_hub *hub, int port1, u16 portstatus, + dev_err(&port_dev->dev, "connect-debounce failed\n"); + portstatus &= ~USB_PORT_STAT_CONNECTION; + unreliable_port = port1; ++#if (MP_USB_MSTAR==1) ++ /* Colin, 100310, for the plug in-out USB disk quickly. */ ++ if (hub->hdev->parent == NULL) ++ { ++ if (hcd->ehc_base != 0) ++ { ++ printk("root hub reinitial\n"); ++ hcd->driver->stop(hcd); ++ hcd->driver->reset(hcd); ++ hcd->driver->start(hcd); ++ ++ hcd->root_port_devnum=0; ++ hcd->enum_port_flag=0; ++ hcd->enum_dbreset_flag=0; ++ hcd_writeb(hcd, hcd_readb(hcd, 0x40) & (u8)(~BIT7), 0x40); //clear force full speed ++ ++ goto done; ++ } ++ } ++#endif + } else { + portstatus = status; + } +@@ -4793,6 +5591,17 @@ static void hub_port_connect(struct usb_hub *hub, int port1, u16 portstatus, + else + unit_load = 100; + ++#if (MP_USB_MSTAR==1) && defined(XHCI_HS_FORCE_CURRENT) ++ if ((hcd->xhci_base != 0) && (hcd->utmi_base != 0)) { ++ if ((hub->hdev->parent == NULL) && ++ (readb((void *)(hcd->xhci_base + XHC_SSPORT_OFFSET)) & BIT0) && ++ (readb((void *)(hcd->xhci_base + XHC_HSPORT_OFFSET)) & BIT0) ) { ++ printk("Enable HS current\n"); ++ writeb(readb((void*)(hcd->utmi_base+0x06*2)) | BIT2, (void*) (hcd->utmi_base+0x06*2)); //Force HS TX current ++ } ++ } ++#endif ++ + status = 0; + for (i = 0; i < SET_CONFIG_TRIES; i++) { + +@@ -4827,12 +5636,51 @@ static void hub_port_connect(struct usb_hub *hub, int port1, u16 portstatus, + usb_lock_port(port_dev); + status = hub_port_init(hub, udev, port1, i); + usb_unlock_port(port_dev); ++#if (MP_USB_MSTAR == 1) ++ if (udev->speed == USB_SPEED_UNKNOWN) ++ status = -ENOTCONN; /* Don't retry */ ++#endif + if (status < 0) + goto loop; + + if (udev->quirks & USB_QUIRK_DELAY_INIT) + msleep(2000); + ++#if (MP_USB_MSTAR==1) && defined(XHCI_SSC_QUIRK_PATCH) ++ //---Add quirks patch for SS_SSC---- ++ if ((le16_to_cpu(udev->descriptor.idVendor) == 0x1b1c) && ++ (le16_to_cpu(udev->descriptor.idProduct) == 0x1a09) && ++ (udev->speed == USB_SPEED_SUPER) && ++ (hub->hdev->parent == NULL) ) { ++ if (hcd->u3dphy_base[port1-1]) { ++ writew(0, (void*) (hcd->u3dphy_base[port1-1]+0xC6*2)); ++ if (port1==1) ++ hcd->ms_flag |= MS_FLAG_P0_SSC; ++ else if (port1==2) ++ hcd->ms_flag |= MS_FLAG_P1_SSC; ++ } ++ } ++#endif ++ ++ #if (MP_USB_MSTAR == 1) ++ /* Set EOF1 for HS device attached on roothub */ ++ if ((hcd->ehc_base!=0) && (udev->speed == USB_SPEED_HIGH) && (hub->hdev->parent == NULL)) { ++ if (udev->descriptor.bDeviceClass == USB_CLASS_HUB) { ++ /* set EOF1 to 20us for hub case */ ++ if (((hcd_readb(hcd, 0x34)>>2) & 0x3) != 0x2) { ++ hcd_writeb(hcd, (hcd_readb(hcd, 0x34) & (u8)(~BIT2)) | BIT3, 0x34); ++ //printk("[EHCI EOF1-20]\n"); ++ } ++ } else { ++ /* set EOF1 to 16us for non hub case; set to 24 us for ISO later */ ++ if (((hcd_readb(hcd, 0x34)>>2) & 0x3) != 0x1) { ++ hcd_writeb(hcd, (hcd_readb(hcd, 0x34) & (u8)(~BIT3)) | BIT2, 0x34); ++ //printk("[EHCI EOF1-16]\n"); ++ } ++ } ++ } ++ #endif ++ + /* consecutive bus-powered hubs aren't reliable; they can + * violate the voltage drop budget. if the new child has + * a "powered" LED, users should notice we didn't enable it +@@ -4917,7 +5765,11 @@ static void hub_port_connect(struct usb_hub *hub, int port1, u16 portstatus, + return; + + loop_disable: ++#if (MP_USB_MSTAR==1) ++ hub_port_disable(hub, port1, 1, 1); ++#else + hub_port_disable(hub, port1, 1); ++#endif + loop: + usb_ep0_reinit(udev); + release_devnum(udev); +@@ -4934,7 +5786,40 @@ loop: + usb_hub_set_port_power(hdev, hub, port1, true); + msleep(hub_power_on_good_delay(hub)); + } ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ if(is_suspending()) ++ break; ++#endif /* CONFIG_MP_USB_STR_PATCH */ ++ } ++#if (MP_USB_MSTAR==1) ++ if (hub->hdev->parent==NULL) ++ { ++ if ((hcd->ehc_base!=0) && (hcd->enum_port_flag==2)) ++ { ++ int high_line; ++ if ((hcd_readb(hcd, 0x30) & BIT0) && ++ ((high_line=(hcd_readb(hcd, 0x41) & BIT2)) || ++ (hcd_readb(hcd, 0x41) & BIT1) )) // for Plug-in/out the USB disk quickly ++ { ++ printk("Force Retry, current speed %s\n", high_line? "HIGH": "LOW"); ++ hcd->enum_port_flag=high_line?1:4; //tony will force device to FS and enum again ++ } ++ } ++ ++ /* patch for DM always keep high issue */ ++ #if (_USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH) ++ /* turn on overwrite mode */ ++ if (hcd->utmi_base != 0) ++ { ++ //printk("turn on overwrite mode..\n"); ++ writeb(readb((void*)(hcd->utmi_base+0x0*2)) | BIT1, (void*) (hcd->utmi_base+0x0*2)); //tern_ov = 1 ++ /* new HW term overwrite: on */ ++ writeb(readb((void*)(hcd->utmi_base+0x52*2)) | (BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0), (void*) (hcd->utmi_base+0x52*2)); ++ } ++ #endif + } ++#endif + if (hub->hdev->parent || + !hcd->driver->port_handed_over || + !(hcd->driver->port_handed_over)(hcd, port1)) { +@@ -4944,7 +5829,11 @@ loop: + } + + done: ++#if (MP_USB_MSTAR==1) ++ hub_port_disable(hub, port1, 1, 1); ++#else + hub_port_disable(hub, port1, 1); ++#endif + if (hcd->driver->relinquish_port && !hub->hdev->parent) { + if (status != -ENOTCONN && status != -ENODEV) + hcd->driver->relinquish_port(hcd, port1); +@@ -5012,6 +5901,9 @@ static void hub_port_connect_change(struct usb_hub *hub, int port1, + usb_lock_port(port_dev); + } + ++#if (MP_USB_MSTAR==1) ++#define HUB_BAD_DEV_HPCG_RETRY_NUMBER 5 ++#endif + static void port_event(struct usb_hub *hub, int port1) + __must_hold(&port_dev->status_lock) + { +@@ -5020,17 +5912,62 @@ static void port_event(struct usb_hub *hub, int port1) + struct usb_device *udev = port_dev->child; + struct usb_device *hdev = hub->hdev; + u16 portstatus, portchange; ++#if (MP_USB_MSTAR==1) ++ struct usb_hcd *hcd; ++ u8 temp; ++ u8 bad_dev_retry_cnt; // x12 patch ++ u8 do_ehc_reset = 0; ++ int ls_tracked = 0; ++ int ret; ++#endif + ++#if (MP_USB_MSTAR==1) ++testtry: ++#endif + connect_change = test_bit(port1, hub->change_bits); + clear_bit(port1, hub->event_bits); + clear_bit(port1, hub->wakeup_bits); + ++#if (MP_USB_MSTAR==1) ++ bad_dev_retry_cnt = 0; // x12 patch ++ do_ehc_reset = 0; ++#endif ++ ++#if (MP_USB_MSTAR==1) ++ ret = hub_port_status(hub, port1, &portstatus, &portchange); ++ /* tony add for disconnect & hotplug */ ++ hcd = bus_to_hcd(hdev->bus); ++ if ((hcd->ehc_base!=0)&&(hdev->parent == NULL)) { ++ temp = hcd_readb(hcd, 0x30); ++ if ((ret < 0 ) && ((temp & (BIT1|BIT0))==0x01)) ++ return; ++ } ++#else + if (hub_port_status(hub, port1, &portstatus, &portchange) < 0) + return; ++#endif + + if (portchange & USB_PORT_STAT_C_CONNECTION) { + usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_C_CONNECTION); + connect_change = 1; ++ ++ /* patch for DM always keep high issue */ ++#if (MP_USB_MSTAR==1) && (_USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH) ++ /* turn on overwrite mode */ ++ if ((hcd->utmi_base != 0) && hdev->parent == NULL) { ++ writeb(readb((void*)(hcd->utmi_base+0x0*2)) | BIT1, (void*) (hcd->utmi_base+0x0*2)); //tern_ov = 1 ++ /* new HW term overwrite: on */ ++ writeb(readb((void*)(hcd->utmi_base+0x52*2)) | (BIT5|BIT4| ++ BIT3|BIT2|BIT1|BIT0), (void*) (hcd->utmi_base+0x52*2)); ++ } ++#endif ++ ++#if (MP_USB_MSTAR==1) && (_UTMI_PWR_SAV_MODE_ENABLE) ++ if ( (hdev->parent == NULL) && !hub_is_superspeed(hub->hdev) ) { ++ usb_power_saving_enable(hcd, true); ++ } ++#endif ++ + } + + if (portchange & USB_PORT_STAT_C_ENABLE) { +@@ -5048,6 +5985,14 @@ static void port_event(struct usb_hub *hub, int port1) + && !connect_change && udev) { + dev_err(&port_dev->dev, "disabled by hub (EMI?), re-enabling...\n"); + connect_change = 1; ++ #if (MP_USB_MSTAR==1) ++ if ( (hcd->ehc_base!=0) && (hdev->parent == NULL) ++ && (hcd_readb(hcd, 0x87) & 0x08) ) ++ { ++ dev_err(&port_dev->dev, "Clear PED fail, shall do EHCI reset!\n"); ++ do_ehc_reset = 1; ++ } ++ #endif + } + } + +@@ -5080,9 +6025,32 @@ static void port_event(struct usb_hub *hub, int port1) + USB_PORT_FEAT_C_PORT_LINK_STATE); + } + if (portchange & USB_PORT_STAT_C_CONFIG_ERROR) { ++#if (MP_USB_MSTAR==1) ++ printk(" !! port CEC detected : 0x%x !! \n", (portstatus & USB_PORT_STAT_LINK_STATE)); ++#endif + dev_warn(&port_dev->dev, "config error\n"); + usb_clear_port_feature(hdev, port1, + USB_PORT_FEAT_C_PORT_CONFIG_ERROR); ++ ++#if (MP_USB_MSTAR==1) ++ if (hub_is_superspeed(hub->hdev) ++ && ((portstatus & USB_PORT_STAT_LINK_STATE) != USB_SS_PORT_LS_U0)) ++ { ++ hub_port_reset(hub, port1, NULL, HUB_BH_RESET_TIME, true); ++ ret = hub_port_status(hub, port1, &portstatus, &portchange); ++ if (ret == 0) { ++ if (portchange & USB_PORT_STAT_C_CONFIG_ERROR) { ++ printk("Clear CEC again: 0x%x !! \n", (portstatus & USB_PORT_STAT_LINK_STATE)); ++ usb_clear_port_feature(hub->hdev, port1, USB_PORT_FEAT_C_PORT_CONFIG_ERROR); ++ } ++ ++ if (!(portstatus & USB_PORT_STAT_CONNECTION)) ++ hub_port_disable(hub, port1, 1, 1); ++ } ++ else ++ hub_port_disable(hub, port1, 1, 1); ++ } ++#endif + } + + /* skip port actions that require the port to be powered on */ +@@ -5100,9 +6068,17 @@ static void port_event(struct usb_hub *hub, int port1) + dev_dbg(&port_dev->dev, "do warm reset\n"); + if (!udev || !(portstatus & USB_PORT_STAT_CONNECTION) + || udev->state == USB_STATE_NOTATTACHED) { ++#if (MP_USB_MSTAR==1) ++ if (hub_port_reset(hub, port1, NULL, ++ HUB_BH_RESET_TIME, true) < 0) ++ hub_port_disable(hub, port1, 1, 1); ++ else if ((portstatus & USB_PORT_STAT_LINK_STATE)== USB_SS_PORT_LS_LOOPBACK) ++ hub_port_disable(hub, port1, 1, 1); ++#else + if (hub_port_reset(hub, port1, NULL, + HUB_BH_RESET_TIME, true) < 0) + hub_port_disable(hub, port1, 1); ++#endif + } else { + usb_unlock_port(port_dev); + usb_lock_device(udev); +@@ -5113,8 +6089,104 @@ static void port_event(struct usb_hub *hub, int port1) + } + } + ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ if ( is_suspending()) ++ { ++ if (do_ehc_reset == 0) ++ { ++ usb_unlock_device(hdev); ++ dev_info(&port_dev->dev, "Skip hub event, sta: %x, chg: %x\n", portstatus, portchange); ++ return; ++ } ++ } ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ ++ ++#if (MP_USB_MSTAR==1) ++bad_dev_retry: // x12 patch ++#endif + if (connect_change) + hub_port_connect_change(hub, port1, portstatus, portchange); ++ ++#if (MP_USB_MSTAR==1) ++ /* tony add for compatibility issue if enum fail then go into FS and retry enum */ ++ hcd = bus_to_hcd(hub->hdev->bus); ++ if((hcd->ehc_base!=0) && (hcd->enum_port_flag & 5) ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ && !is_suspending() ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ ++ ) { // 1: HS, 4: LS ++ int rh_dev_speed_high = (hcd->enum_port_flag==1) ? 1 : 0; ++ if (ls_tracked) ++ { ++ hcd->enum_port_flag=0; //tony just try 1 time ++ printk("Relieve LS Force Retry!!!\n"); ++ return; ++ } ++ ++ hcd->driver->stop(hcd); ++ hcd->driver->reset(hcd); ++ hcd->driver->start(hcd); ++ ++ // x12 patch ++ /* Before go into Full Speed, give the Bad Dev 2 another chances ++ of enumerating in High Speed. */ ++ if(bad_dev_retry_cnt > HUB_BAD_DEV_HPCG_RETRY_NUMBER) ++ { ++ hcd->enum_port_flag=0; //tony just try 1 time ++ if (rh_dev_speed_high) ++ { ++ hcd_writeb(hcd, hcd_readb(hcd, 0x40) | BIT7, 0x40); //force full speed ++ printk("##[USB] bad dev is going into Full Speed, retry %d ##\n", bad_dev_retry_cnt); ++ } ++ } ++ else ++ { ++ printk("##[USB] bad dev %s Speed retry (%d) ##\n", rh_dev_speed_high ? "High" : "Low", rh_dev_speed_high ? bad_dev_retry_cnt : ls_tracked); ++ } ++ // x12 patch ++ if(bad_dev_retry_cnt > HUB_BAD_DEV_HPCG_RETRY_NUMBER) ++ { ++ usb_unlock_device(hdev); ++ goto testtry; ++ } ++ else if (rh_dev_speed_high == 0) // low speed ++ { ++ ls_tracked++; //do while(1) ++ } ++ else ++ { ++ bad_dev_retry_cnt++; ++ msleep(500); //Add delay waiting for root hub ++ ret = hub_port_status(hub, port1, &portstatus, &portchange); ++ if (ret < 0) ++ return; ++ ++ printk("portstatus:0x%x portchange:0x%x\n", portstatus, portchange); ++ if (portstatus & USB_PORT_STAT_CONNECTION) ++ goto bad_dev_retry; ++ } ++ } ++#endif ++ ++#if (MP_USB_MSTAR==1) ++ if ( (hcd->ehc_base!=0) && (hdev->parent == NULL) ++ && (hub->ports[port1 - 1]->child == NULL) ++ && (portstatus==0) && (portchange & USB_PORT_STAT_C_ENABLE) ++ && (hcd_readb(hcd, 0x87) & 0x08) ) ++ { ++ printk("[USB] reset EHCI ...\n"); ++ hcd->driver->stop(hcd); ++ hcd->driver->reset(hcd); ++ hcd->driver->start(hcd); ++ usb_unlock_device(hdev); ++ ++ //When the device disconnect and change to SS in IN-NAK state, ++ //we need to reset EHCI to exit from the abnormal babble state. ++ return; ++ ++ } ++#endif ++ + } + + static void hub_event(struct work_struct *work) +@@ -5478,6 +6550,18 @@ static int usb_reset_and_verify_device(struct usb_device *udev) + + /* ep0 maxpacket size may change; let the HCD know about it. + * Other endpoints will be handled by re-enumeration. */ ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ if(is_suspending()) ++ { ++ ret=-ETIMEDOUT; ++ break; ++ } ++ if(!udev->can_submit) ++ { ++ ret = -ENOTCONN; ++ break; ++ } ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH*/ + usb_ep0_reinit(udev); + ret = hub_port_init(parent_hub, udev, port1, i); + if (ret >= 0 || ret == -ENOTCONN || ret == -ENODEV) +@@ -5573,6 +6657,13 @@ re_enumerate: + usb_release_bos_descriptor(udev); + udev->bos = bos; + re_enumerate_no_bos: ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ if(is_suspending()) ++ { ++ //logical_disconnect will be done during resume stage. ++ return ret; ++ } ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ + /* LPM state doesn't matter when we're about to destroy the device. */ + hub_port_logical_disconnect(parent_hub, port1); + return -ENODEV; +diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c +index 4c388451f31f..cc3562a49aaa 100644 +--- a/drivers/usb/core/message.c ++++ b/drivers/usb/core/message.c +@@ -19,6 +19,10 @@ + + #include "usb.h" + ++#ifdef CONFIG_MP_USB_MSTAR ++#include "usb_common_sstar.h" ++#endif ++ + static void cancel_async_set_config(struct usb_device *udev); + + struct api_context { +@@ -34,6 +38,9 @@ static void usb_api_blocking_completion(struct urb *urb) + complete(&ctx->done); + } + ++#if (MP_USB_MSTAR==1) ++extern unsigned char hcd_readb(struct usb_hcd *, size_t); ++#endif + + /* + * Starts urb and waits for completion or timeout. Note that this call +@@ -55,6 +62,56 @@ static int usb_start_wait_urb(struct urb *urb, int timeout, int *actual_length) + goto out; + + expire = timeout ? msecs_to_jiffies(timeout) : MAX_SCHEDULE_TIMEOUT; ++#if (MP_USB_MSTAR==1) ++ { ++ #define TIMEOUT_SETP_MS 100 ++ unsigned long timeout_step = msecs_to_jiffies(TIMEOUT_SETP_MS); ++ unsigned long total_time = 0; ++ struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); ++ do { ++ if (!wait_for_completion_timeout(&ctx.done, timeout_step)) { ++ total_time += timeout_step; ++ if(total_time >= expire) ++ { ++ usb_kill_urb(urb); ++ retval = (ctx.status == -ENOENT ? -ETIMEDOUT : ctx.status); ++ dev_dbg(&urb->dev->dev, ++ "%s timed out on ep%d%s len=%u/%u\n", ++ current->comm, ++ usb_endpoint_num(&urb->ep->desc), ++ usb_urb_dir_in(urb) ? "in" : "out", ++ urb->actual_length, ++ urb->transfer_buffer_length); ++ break; ++ } ++ if(((urb->dev->parent != NULL) && (urb->dev->parent->parent == NULL) // device on roothub ++ && (hcd->ehc_base != 0) && (hcd_readb(hcd, 0x30) & BIT1)) // CSC happen on ehci port ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ || is_suspending()) ++#else ++ ) ++#endif /* CONFIG_MP_USB_STR_PATCH */ ++ { ++ usb_kill_urb(urb); ++ retval = (ctx.status == -ENOENT ? -ETIMEDOUT : ctx.status); ++ dev_dbg(&urb->dev->dev, ++ "[USB] %s CSC happen on ep%d%s len=%u/%u\n", ++ current->comm, ++ usb_endpoint_num(&urb->ep->desc), ++ usb_urb_dir_in(urb) ? "in" : "out", ++ urb->actual_length, ++ urb->transfer_buffer_length); ++ break; ++ } ++ } ++ else ++ { ++ retval = ctx.status; ++ break; ++ } ++ } while (true); ++ } ++#else + if (!wait_for_completion_timeout(&ctx.done, expire)) { + usb_kill_urb(urb); + retval = (ctx.status == -ENOENT ? -ETIMEDOUT : ctx.status); +@@ -68,6 +125,7 @@ static int usb_start_wait_urb(struct urb *urb, int timeout, int *actual_length) + urb->transfer_buffer_length); + } else + retval = ctx.status; ++#endif + out: + if (actual_length) + *actual_length = urb->actual_length; +@@ -145,6 +203,23 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, __u8 request, + dr->wValue = cpu_to_le16(value); + dr->wIndex = cpu_to_le16(index); + dr->wLength = cpu_to_le16(size); ++#if (MP_USB_MSTAR==1) //20121029, for logitech webcam, it needs 1.2 secs but timeout value is 1 sec ++ if ( (le16_to_cpu(dev->descriptor.idVendor) == 0x046d) && ++ (le16_to_cpu(dev->descriptor.idProduct) == 0x0825) && ++ usb_pipeout(pipe) ) ++ { ++ timeout = USB_CTRL_SET_TIMEOUT + 5000; ++ } ++#endif ++#if (MP_USB_MSTAR==1) ++ if ( ((dev->descriptor.idProduct==0x7603 && dev->descriptor.idVendor ==0x0e8d) || ++ (dev->descriptor.idProduct==0x7601 && dev->descriptor.idVendor ==0x148f)) ++ && (dr->wLength==0x100) ) ++ { ++ printk("[USB] change control transfer length from 256 to 255...\n"); ++ dr->wLength=0xff; ++ } ++#endif + + ret = usb_internal_control_msg(dev, pipe, dr, data, size, timeout); + +@@ -561,8 +636,29 @@ void usb_sg_wait(struct usb_sg_request *io) + * So could the submit loop above ... but it's easier to + * solve neither problem than to solve both! + */ ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ while(1) ++ { ++ long timeleft = wait_for_completion_interruptible_timeout( ++ &io->complete, 0.1*HZ); ++ if(timeleft == 0) ++ { ++ if(is_suspending()) ++ { ++ if (printk_ratelimit()) { ++ dev_err(&io->dev->dev, ++ "%s, cancel io on suspend, %d/%d\n", ++ __func__, io->count, io->entries); ++ } ++ usb_sg_cancel(io); ++ } ++ } ++ else ++ break; ++ } ++#else + wait_for_completion(&io->complete); +- ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ + sg_clean(io); + } + EXPORT_SYMBOL_GPL(usb_sg_wait); +@@ -824,6 +920,10 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) + if (err < 0) + goto errout; + ++#if (MP_USB_MSTAR==1) && _USB_FRIENDLY_CUSTOMER_PATCH ++ if(le16_to_cpu(dev->descriptor.idVendor) == 0x04E8 && le16_to_cpu(dev->descriptor.idProduct) == 0x5092) ++ goto errout; ++#endif + err = usb_string_sub(dev, dev->string_langid, index, tbuf); + if (err < 0) + goto errout; +diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c +index 5133ab965229..79d893a63b20 100644 +--- a/drivers/usb/core/urb.c ++++ b/drivers/usb/core/urb.c +@@ -8,6 +8,10 @@ + #include + #include + ++#ifdef CONFIG_MP_USB_MSTAR ++#include "usb_common_sstar.h" ++#endif ++ + #define to_urb(d) container_of(d, struct urb, kref) + + +@@ -180,6 +184,9 @@ void usb_unanchor_urb(struct urb *urb) + } + EXPORT_SYMBOL_GPL(usb_unanchor_urb); + ++#if (MP_USB_MSTAR==1) ++extern u8 hcd_readb(struct usb_hcd *, size_t); ++#endif + /*-------------------------------------------------------------------*/ + + /** +@@ -517,8 +524,27 @@ int usb_submit_urb(struct urb *urb, gfp_t mem_flags) + case USB_SPEED_FULL: /* units are frames/msec */ + case USB_SPEED_LOW: + if (xfertype == USB_ENDPOINT_XFER_INT) { ++#if (MP_USB_MSTAR==1) //tony add for hotplug (FS) ++ struct usb_hcd *hcd; ++ hcd = bus_to_hcd(urb->dev->bus); ++ if (hcd->ehc_base!=0) ++ { ++ if((hcd_readb(hcd, 0x30) & BIT0)){ ++ if (urb->interval > 255){ ++ urb->interval = 255; //Colin, 090305, Don't return EINVAL, the root hub would stop ++ } ++ } ++ } ++ else ++ { ++ if (urb->interval > 255){ ++ urb->interval = 255; //Colin, 090305, Don't return EINVAL, the root hub would stop ++ } ++ } ++#else + if (urb->interval > 255) + return -EINVAL; ++#endif + /* NOTE ohci only handles up to 32 */ + max = 128; + } else { +diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c +index eaf1c3b06f02..3bc641c76f11 100644 +--- a/drivers/usb/core/usb.c ++++ b/drivers/usb/core/usb.c +@@ -45,6 +45,9 @@ + + #include "usb.h" + ++#ifdef CONFIG_MP_USB_MSTAR ++#include "usb_common_sstar.h" ++#endif + + const char *usbcore_name = "usbcore"; + +@@ -362,9 +365,11 @@ static const struct dev_pm_ops usb_device_pm_ops = { + .thaw = usb_dev_thaw, + .poweroff = usb_dev_poweroff, + .restore = usb_dev_restore, ++#if (MP_USB_MSTAR==0) + .runtime_suspend = usb_runtime_suspend, + .runtime_resume = usb_runtime_resume, + .runtime_idle = usb_runtime_idle, ++#endif + }; + + #endif /* CONFIG_PM */ +@@ -694,14 +699,14 @@ EXPORT_SYMBOL_GPL(usb_get_current_frame_number); + */ + + int __usb_get_extra_descriptor(char *buffer, unsigned size, +- unsigned char type, void **ptr) ++ unsigned char type, void **ptr, size_t minsize) + { + struct usb_descriptor_header *header; + + while (size >= sizeof(struct usb_descriptor_header)) { + header = (struct usb_descriptor_header *)buffer; + +- if (header->bLength < 2) { ++ if (header->bLength < 2 || header->bLength > size) { + printk(KERN_ERR + "%s: bogus descriptor, type %d length %d\n", + usbcore_name, +@@ -710,7 +715,7 @@ int __usb_get_extra_descriptor(char *buffer, unsigned size, + return -1; + } + +- if (header->bDescriptorType == type) { ++ if (header->bDescriptorType == type && header->bLength >= minsize) { + *ptr = header; + return 0; + } +diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c +old mode 100644 +new mode 100755 +index fea446900cad..f03632ccf42d +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -19,6 +19,7 @@ + * along with this program. If not, see . + */ + ++#include + #include + #include + #include +@@ -49,6 +50,11 @@ + + #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ + ++/* module parameters specific whether hibernation is supported */ ++static bool hibernation_support = 0; ++module_param(hibernation_support, bool, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(hibernation_support, "0(not support), 1(support). default:0"); ++ + /** + * dwc3_get_dr_mode - Validates and sets dr_mode + * @dwc: pointer to our context structure +@@ -151,7 +157,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) + * XHCI driver will reset the host block. If dwc3 was configured for + * host-only mode, then we can return early. + */ +- if (dwc->dr_mode == USB_DR_MODE_HOST) ++ if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->is_hibernated == true) + return 0; + + reg = dwc3_readl(dwc->regs, DWC3_DCTL); +@@ -161,12 +167,26 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) + do { + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + if (!(reg & DWC3_DCTL_CSFTRST)) +- return 0; ++ goto done; + + udelay(1); + } while (--retries); + ++ phy_exit(dwc->usb3_generic_phy); ++ phy_exit(dwc->usb2_generic_phy); ++ + return -ETIMEDOUT; ++ ++done: ++ /* ++ * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, ++ * we must wait at least 50ms before accessing the PHY domain ++ * (synchronization delay). DWC_usb31 programming guide section 1.3.2. ++ */ ++ if (dwc3_is_usb31(dwc)) ++ msleep(50); ++ ++ return 0; + } + + /** +@@ -213,8 +233,7 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc) + + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + dft = reg & DWC3_GFLADJ_30MHZ_MASK; +- if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, +- "request value same as default, ignoring\n")) { ++ if (dft != dwc->fladj) { + reg &= ~DWC3_GFLADJ_30MHZ_MASK; + reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); +@@ -251,6 +270,9 @@ static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, + + evt->dwc = dwc; + evt->length = length; ++ evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); ++ if (!evt->cache) ++ return ERR_PTR(-ENOMEM); + evt->buf = dma_alloc_coherent(dwc->dev, length, + &evt->dma, GFP_KERNEL); + if (!evt->buf) +@@ -303,6 +325,7 @@ static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) + static int dwc3_event_buffers_setup(struct dwc3 *dwc) + { + struct dwc3_event_buffer *evt; ++ dma_addr_t miu_addr; + + evt = dwc->ev_buf; + dwc3_trace(trace_dwc3_core, +@@ -312,10 +335,11 @@ static int dwc3_event_buffers_setup(struct dwc3 *dwc) + + evt->lpos = 0; + ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(evt->dma); + dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), +- lower_32_bits(evt->dma)); ++ lower_32_bits(miu_addr)); + dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), +- upper_32_bits(evt->dma)); ++ upper_32_bits(miu_addr)); + dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), + DWC3_GEVNTSIZ_SIZE(evt->length)); + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); +@@ -340,25 +364,71 @@ static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) + + static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) + { ++ dma_addr_t dma_adr; ++ int i; ++ + if (!dwc->has_hibernation) + return 0; + + if (!dwc->nr_scratch) + return 0; + +- dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, +- DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); +- if (!dwc->scratchbuf) +- return -ENOMEM; +- +- return 0; ++ if (dwc->scratchpad_array) ++ return 0; ++ dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(dwc->hwparams.hwparams4); ++ ++ if (dwc->nr_scratch) { ++ /* Allocate scratchpad buffer address array */ ++ dwc->scratchpad_array = dma_alloc_coherent(NULL, ++ sizeof(*dwc->scratchpad_array), ++ &dwc->scratchpad_array_dma, ++ GFP_KERNEL); ++ //printk("[%s]scratchpad_array:x%p scratchpad_array_dma:x%x\n", __FUNCTION__, dwc->scratchpad_array, dwc->scratchpad_array_dma); ++ if (!dwc->scratchpad_array) ++ goto err; ++ } ++ else { ++ printk("[%s]failed nr_scratch=0 \n", __FUNCTION__); ++ } ++ /* Allocate scratchpad buffers */ ++ for (i = 0; i < dwc->nr_scratch; i++) { ++ dwc->scratchpad[i] = dma_alloc_coherent(NULL, ++ DWC3_SCRATCHBUF_SIZE, ++ &dma_adr, ++ GFP_KERNEL); ++ //printk("\n%d scratchpad:x%p dma_adr:x%x\n\n", i, dwc->scratchpad[i], dma_adr); ++ if (!dwc->scratchpad[i]) { ++ while (--i >= 0) { ++ dma_adr = (dma_addr_t)dwc->scratchpad_array->dma_adr[i]; ++ dma_free_coherent(NULL, ++ DWC3_SCRATCHBUF_SIZE, ++ dwc->scratchpad[i], ++ dma_adr); ++ dwc->scratchpad[i] = NULL; ++ } ++ ++ goto err_free; ++ } ++ ++ dwc->scratchpad_array->dma_adr[i] = cpu_to_le64((dma_addr_t)Chip_Phys_to_MIU(dma_adr)); ++ } ++ ++ return 0; ++ ++err_free: ++ dma_free_coherent(NULL, ++ sizeof(*dwc->scratchpad_array), ++ dwc->scratchpad_array, ++ dwc->scratchpad_array_dma); ++ dwc->scratchpad_array = NULL; ++err: ++ return -ENOMEM; + } +- + static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) + { +- dma_addr_t scratch_addr; + u32 param; + int ret; ++ dma_addr_t miu_addr; + + if (!dwc->has_hibernation) + return 0; +@@ -367,28 +437,31 @@ static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) + return 0; + + /* should never fall here */ +- if (!WARN_ON(dwc->scratchbuf)) ++ if (WARN_ON(!dwc->scratchpad_array->dma_adr[0])) + return 0; + +- scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, +- dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, +- DMA_BIDIRECTIONAL); +- if (dma_mapping_error(dwc->dev, scratch_addr)) { +- dev_err(dwc->dev, "failed to map scratch buffer\n"); +- ret = -EFAULT; +- goto err0; +- } +- +- dwc->scratch_addr = scratch_addr; +- +- param = lower_32_bits(scratch_addr); ++ #if (0) ++ { ++ u32 i; ++ u32 *ptr = (u32 *)(dwc->scratchpad_array); ++ ++ printk("\n[%s]scratchpad:%p scratchpad_array_dma:x%x\n", __FUNCTION__, dwc->scratchpad[0], dwc->scratchpad_array_dma); ++ printk("x%p:x%8x x%8x x%8x x%8x[WARNING BF]\n\n", ptr, ptr[0], ptr[1], ptr[2], ptr[3]); ++ ptr = (dwc->scratchpad[0]); ++ for (i = 0; iscratchpad_array_dma); ++ param = lower_32_bits(miu_addr); + + ret = dwc3_send_gadget_generic_command(dwc, + DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); + if (ret < 0) + goto err1; + +- param = upper_32_bits(scratch_addr); ++ param = upper_32_bits(miu_addr); + + ret = dwc3_send_gadget_generic_command(dwc, + DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); +@@ -398,28 +471,41 @@ static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) + return 0; + + err1: +- dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * +- DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); ++ dma_unmap_single(dwc->dev, ++ dwc->scratchpad_array_dma, ++ dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, ++ DMA_BIDIRECTIONAL); + +-err0: + return ret; + } + + static void dwc3_free_scratch_buffers(struct dwc3 *dwc) + { +- if (!dwc->has_hibernation) +- return; +- +- if (!dwc->nr_scratch) +- return; +- +- /* should never fall here */ +- if (!WARN_ON(dwc->scratchbuf)) +- return; +- +- dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * +- DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); +- kfree(dwc->scratchbuf); ++ dma_addr_t dma_adr; ++ int hiberbufs, i; ++ ++ //if (!dwc3_hiber_enabled(dwc)) ++ // return; ++ ++ hiberbufs = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(dwc->hwparams.hwparams4); ++ for (i = 0; i < hiberbufs; i++) { ++ if (dwc->scratchpad[i] != NULL) { ++ dma_adr = (dma_addr_t)dwc->scratchpad_array->dma_adr[i]; ++ dma_free_coherent(NULL, ++ DWC3_SCRATCHBUF_SIZE, ++ dwc->scratchpad[i], ++ dma_adr); ++ dwc->scratchpad[i] = NULL; ++ } ++ } ++ ++ if (dwc->scratchpad_array) { ++ dma_free_coherent(NULL, ++ sizeof(*dwc->scratchpad_array), ++ dwc->scratchpad_array, ++ dwc->scratchpad_array_dma); ++ dwc->scratchpad_array = NULL; ++ } + } + + static void dwc3_core_num_eps(struct dwc3 *dwc) +@@ -463,6 +549,12 @@ static int dwc3_phy_setup(struct dwc3 *dwc) + + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + ++ /* ++ * Make sure UX_EXIT_PX is cleared as that causes issues with some ++ * PHYs. Also, this bit is not supposed to be used in normal operation. ++ */ ++ reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; ++ + /* + * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY + * to '0' during coreConsultant configuration. So default value +@@ -470,7 +562,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc) + * to '1' after the core initialization is completed. + */ + if (dwc->revision > DWC3_REVISION_194A) +- reg |= DWC3_GUSB3PIPECTL_SUSPHY; ++ //reg |= DWC3_GUSB3PIPECTL_SUSPHY; + + if (dwc->u2ss_inp3_quirk) + reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; +@@ -600,7 +692,7 @@ static void dwc3_core_exit(struct dwc3 *dwc) + * + * Returns 0 on success otherwise negative errno. + */ +-static int dwc3_core_init(struct dwc3 *dwc) ++int dwc3_core_init(struct dwc3 *dwc) + { + u32 hwparams4 = dwc->hwparams.hwparams4; + u32 reg; +@@ -634,18 +726,24 @@ static int dwc3_core_init(struct dwc3 *dwc) + dwc->maximum_speed = USB_SPEED_HIGH; + } + +- /* issue device SoftReset too */ +- ret = dwc3_soft_reset(dwc); +- if (ret) +- goto err0; +- +- ret = dwc3_core_soft_reset(dwc); +- if (ret) +- goto err0; +- +- ret = dwc3_phy_setup(dwc); +- if (ret) +- goto err0; ++ if (!dwc->is_hibernated) ++ { ++ /* issue device SoftReset too */ ++ ret = dwc3_soft_reset(dwc); ++ if (ret) { ++ goto err0; ++ } ++ ++ ret = dwc3_core_soft_reset(dwc); ++ if (ret) { ++ goto err0; ++ } ++ ++ ret = dwc3_phy_setup(dwc); ++ if (ret) { ++ goto err0; ++ } ++ } + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_SCALEDOWN_MASK; +@@ -680,6 +778,14 @@ static int dwc3_core_init(struct dwc3 *dwc) + * REVISIT Enabling this bit so that host-mode hibernation + * will work. Device-mode hibernation is not yet implemented. + */ ++ if (hibernation_support && (!(INREG16(0x1F000000+(0x1524<<9)+(0x28<<2))&0x01))) { ++ dwc->has_hibernation = (dwc->is_hibernated)? true : true; ++ } else { ++ dwc->has_hibernation = false; ++ } ++ ret = dwc3_alloc_scratch_buffers(dwc); ++ if (ret) ++ goto err5; + reg |= DWC3_GCTL_GBLHIBERNATIONEN; + break; + default: +@@ -717,22 +823,29 @@ static int dwc3_core_init(struct dwc3 *dwc) + + dwc3_core_num_eps(dwc); + +- ret = dwc3_setup_scratch_buffers(dwc); +- if (ret) +- goto err1; +- ++ if (!dwc->is_hibernated) ++ { ++ ret = dwc3_setup_scratch_buffers(dwc); ++ if (ret) ++ goto err1; ++ } ++ + /* Adjust Frame Length */ + dwc3_frame_length_adjustment(dwc); + +- usb_phy_set_suspend(dwc->usb2_phy, 0); +- usb_phy_set_suspend(dwc->usb3_phy, 0); +- ret = phy_power_on(dwc->usb2_generic_phy); +- if (ret < 0) +- goto err2; +- +- ret = phy_power_on(dwc->usb3_generic_phy); +- if (ret < 0) +- goto err3; ++ if (!dwc->is_hibernated) ++ { ++ usb_phy_set_suspend(dwc->usb2_phy, 0); ++ usb_phy_set_suspend(dwc->usb3_phy, 0); ++ ret = phy_power_on(dwc->usb2_generic_phy); ++ if (ret < 0) { ++ goto err2; ++ } ++ ret = phy_power_on(dwc->usb3_generic_phy); ++ if (ret < 0) { ++ goto err3; ++ } ++ } + + ret = dwc3_event_buffers_setup(dwc); + if (ret) { +@@ -767,7 +880,8 @@ static int dwc3_core_init(struct dwc3 *dwc) + } + + return 0; +- ++err5: ++ dwc3_free_scratch_buffers(dwc); + err4: + phy_power_off(dwc->usb3_generic_phy); + +@@ -917,6 +1031,18 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) + /* do nothing */ + break; + } ++ ++ /* de-assert DRVVBUS for HOST and OTG mode */ ++ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); ++} ++ ++/* check whether the core supports IMOD */ ++bool dwc3_has_imod(struct dwc3 *dwc) ++{ ++ return ((dwc3_is_usb3(dwc) && ++ dwc->revision >= DWC3_REVISION_300A) || ++ (dwc3_is_usb31(dwc) && ++ dwc->revision >= DWC3_USB31_REVISION_120A)); + } + + #define DWC3_ALIGN_MASK (16 - 1) +@@ -926,6 +1052,7 @@ static int dwc3_probe(struct platform_device *pdev) + struct device *dev = &pdev->dev; + struct resource *res; + struct dwc3 *dwc; ++ struct clk* clock; + u8 lpm_nyet_threshold; + u8 tx_de_emphasis; + u8 hird_threshold; +@@ -955,7 +1082,7 @@ static int dwc3_probe(struct platform_device *pdev) + dwc->xhci_resources[0].flags = res->flags; + dwc->xhci_resources[0].name = res->name; + +- res->start += DWC3_GLOBALS_REGS_START; ++ //res->start += DWC3_GLOBALS_REGS_START; + + /* + * Request memory region but exclude xHCI regs, +@@ -971,7 +1098,7 @@ static int dwc3_probe(struct platform_device *pdev) + dwc->regs_size = resource_size(res); + + /* default to highest possible threshold */ +- lpm_nyet_threshold = 0xff; ++ lpm_nyet_threshold = 0xf; + + /* default to -3.5dB de-emphasis */ + tx_de_emphasis = 1; +@@ -1044,6 +1171,9 @@ static int dwc3_probe(struct platform_device *pdev) + platform_set_drvdata(pdev, dwc); + dwc3_cache_hwparams(dwc); + ++ clock = of_clk_get_by_name(dev->of_node, "ss_clk"); ++ clk_prepare_enable(clock); ++ + ret = dwc3_core_get_phy(dwc); + if (ret) + goto err0; +@@ -1077,16 +1207,30 @@ static int dwc3_probe(struct platform_device *pdev) + if (ret) + goto err3; + +- ret = dwc3_alloc_scratch_buffers(dwc); +- if (ret) +- goto err3; + + ret = dwc3_core_init(dwc); + if (ret) { +- dev_err(dev, "failed to initialize core\n"); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to initialize core: %d\n", ret); + goto err4; + } + ++ if (dwc3_has_imod(dwc)) ++ dwc->imod_interval = 500; // 125us, in unit of 250ns ++ else ++ dwc->imod_interval = 0; ++ ++ /* ++ * Workaround for STAR 9000961433 which affects only version ++ * 3.00a of the DWC_usb3 core. This prevents the controller ++ * interrupt from being masked while handling events. IMOD ++ * allows us to work around this issue. Enable it for the ++ * affected version. ++ */ ++ if (!dwc->imod_interval && ++ (dwc->revision == DWC3_REVISION_300A)) ++ dwc->imod_interval = 1; ++ + /* Check the maximum_speed parameter */ + switch (dwc->maximum_speed) { + case USB_SPEED_LOW: +@@ -1125,6 +1269,7 @@ static int dwc3_probe(struct platform_device *pdev) + + err5: + dwc3_event_buffers_cleanup(dwc); ++ dwc3_ulpi_exit(dwc); + + err4: + dwc3_free_scratch_buffers(dwc); +@@ -1154,7 +1299,7 @@ err0: + static int dwc3_remove(struct platform_device *pdev) + { + struct dwc3 *dwc = platform_get_drvdata(pdev); +- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ //struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + pm_runtime_get_sync(&pdev->dev); + /* +@@ -1162,7 +1307,7 @@ static int dwc3_remove(struct platform_device *pdev) + * probe is deferred, we don't end up getting error in request the + * memory region the next time probe is called. + */ +- res->start -= DWC3_GLOBALS_REGS_START; ++ //res->start -= DWC3_GLOBALS_REGS_START; + + dwc3_debugfs_exit(dwc); + dwc3_core_exit_mode(dwc); +@@ -1333,12 +1478,18 @@ static int dwc3_resume(struct device *dev) + struct dwc3 *dwc = dev_get_drvdata(dev); + int ret; + +- pinctrl_pm_select_default_state(dev); +- +- ret = dwc3_resume_common(dwc); +- if (ret) +- return ret; +- ++ pinctrl_pm_select_default_state(dev); ++ ++ if (dwc->is_hibernated) { ++ dwc3_gadget_exit_hibernation(dwc); ++ } ++ else ++ { ++ ret = dwc3_resume_common(dwc); ++ if (ret) { ++ return ret; ++ } ++ } + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); +diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h +old mode 100644 +new mode 100755 +index 884c43714456..9661a67f8e03 +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -34,13 +34,34 @@ + + #include + ++/* ++ * Schedule EP0 stages handling in a dedicated thread ++ * Part of EP0 stages will be handled in the gap of isoc IN transfer ++ */ ++#define DWC3_EP0_SCHEDULING ++#ifdef DWC3_EP0_SCHEDULING ++/* Enable monitor isoc xfer activation */ ++#define DWC3_ISOC_MONITOR ++#include ++#include ++#ifdef DWC3_ISOC_MONITOR ++#include ++#endif ++#endif ++/* Give high priority to dwc3 irq thread */ ++#define DWC3_IRQ_THREAD_HP ++/* Enable kernel log for tracing ep0 flow */ ++//#define DWC3_TRACE_EP0 + #define DWC3_MSG_MAX 500 + ++#define DWC3_SCRATCH_BUF_DP_NUM 0x0010 ++ + /* Global constants */ + #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ + #define DWC3_EP0_BOUNCE_SIZE 512 + #define DWC3_ENDPOINTS_NUM 32 + #define DWC3_XHCI_RESOURCES_NUM 2 ++#define DWC3_ISOC_MAX_RETRIES 40 + + #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ + #define DWC3_EVENT_BUFFERS_SIZE 4096 +@@ -63,6 +84,7 @@ + #define DWC3_DEVICE_EVENT_OVERFLOW 11 + + #define DWC3_GEVNTCOUNT_MASK 0xfffc ++#define DWC3_GEVNTCOUNT_EHB BIT(31) + #define DWC3_GSNPSID_MASK 0xffff0000 + #define DWC3_GSNPSREV_MASK 0xffff + +@@ -103,6 +125,11 @@ + #define DWC3_GHWPARAMS7 0xc15c + #define DWC3_GDBGFIFOSPACE 0xc160 + #define DWC3_GDBGLTSSM 0xc164 ++#define DWC3_GDBGBMU 0xc16c ++#define DWC3_GDBGLSPMUX 0xc170 ++#define DWC3_GDBGLSP 0xc174 ++#define DWC3_GDBGEPINFO0 0xc178 ++#define DWC3_GDBGEPINFO1 0xc17c + #define DWC3_GPRTBIMAP_HS0 0xc180 + #define DWC3_GPRTBIMAP_HS1 0xc184 + #define DWC3_GPRTBIMAP_FS0 0xc188 +@@ -145,6 +172,10 @@ + #define DWC3_DEPCMDPAR0 0x08 + #define DWC3_DEPCMD 0x0c + ++#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) ++#define DWC3_DEV_IMODC(n) ((n & 0xffff) << 16) ++#define DWC3_DEV_IMODI(n) (n & 0xffff) ++ + /* OTG Registers */ + #define DWC3_OCFG 0xcc00 + #define DWC3_OCTL 0xcc04 +@@ -159,13 +190,15 @@ + #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) + #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) + +-#define DWC3_TXFIFOQ 1 +-#define DWC3_RXFIFOQ 3 +-#define DWC3_TXREQQ 5 +-#define DWC3_RXREQQ 7 +-#define DWC3_RXINFOQ 9 +-#define DWC3_DESCFETCHQ 13 +-#define DWC3_EVENTQ 15 ++#define DWC3_TXFIFOQ 0 ++#define DWC3_RXFIFOQ 1 ++#define DWC3_TXREQQ 2 ++#define DWC3_RXREQQ 3 ++#define DWC3_RXINFOQ 4 ++#define DWC3_PSTATQ 5 ++#define DWC3_DESCFETCHQ 6 ++#define DWC3_EVENTQ 7 ++#define DWC3_AUXEVENTQ 8 + + /* Global RX Threshold Configuration Register */ + #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) +@@ -223,6 +256,7 @@ + #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) + #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) + #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28) ++#define DWC3_GUSB3PIPECTL_UX_EXIT_PX (1 << 27) + #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) + #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) + #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) +@@ -235,6 +269,8 @@ + #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) + + /* Global TX Fifo Size Register */ ++#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ ++#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */ + #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) + #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) + +@@ -446,6 +482,8 @@ + #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) + #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) + ++#define DWC3_DEPCMD_CMD(x) ((x) & 0xf) ++ + /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ + #define DWC3_DALEPENA_EP(n) (1 << n) + +@@ -461,6 +499,7 @@ struct dwc3_trb; + /** + * struct dwc3_event_buffer - Software event buffer representation + * @buf: _THE_ buffer ++ * @cache: The buffer cache used in the threaded interrupt + * @length: size of this buffer + * @lpos: event offset + * @count: cache of last read event count register +@@ -470,6 +509,7 @@ struct dwc3_trb; + */ + struct dwc3_event_buffer { + void *buf; ++ void *cache; + unsigned length; + unsigned int lpos; + unsigned int count; +@@ -536,6 +576,7 @@ struct dwc3_ep { + #define DWC3_EP_BUSY (1 << 4) + #define DWC3_EP_PENDING_REQUEST (1 << 5) + #define DWC3_EP_MISSED_ISOC (1 << 6) ++#define DWC3_EP_TRANSFER_STARTED (1 << 7) + + /* This last one is specific to EP0 */ + #define DWC3_EP0_DIR_IN (1 << 31) +@@ -557,6 +598,7 @@ struct dwc3_ep { + u8 resource_index; + u32 allocated_requests; + u32 queued_requests; ++ u32 pending_requests; + u32 interval; + + char name[20]; +@@ -833,14 +875,15 @@ struct dwc3_scratchpad_array { + struct dwc3 { + struct usb_ctrlrequest *ctrl_req; + struct dwc3_trb *ep0_trb; ++ struct dwc3_scratchpad_array *scratchpad_array; + void *ep0_bounce; + void *zlp_buf; +- void *scratchbuf; ++ void *scratchpad[DWC3_MAX_HIBER_SCRATCHBUFS]; + u8 *setup_buf; + dma_addr_t ctrl_req_addr; + dma_addr_t ep0_trb_addr; + dma_addr_t ep0_bounce_addr; +- dma_addr_t scratch_addr; ++ dma_addr_t scratchpad_array_dma; + struct dwc3_request ep0_usb_req; + + /* device lock */ +@@ -873,6 +916,9 @@ struct dwc3 { + + u32 fladj; + u32 irq_gadget; ++#ifdef DWC3_IRQ_THREAD_HP ++ u32 irq_thread_hp; ++#endif + u32 nr_scratch; + u32 u1u2; + u32 maximum_speed; +@@ -914,6 +960,7 @@ struct dwc3 { + */ + #define DWC3_REVISION_IS_DWC31 0x80000000 + #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) ++#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) + + enum dwc3_ep0_next ep0_next_event; + enum dwc3_ep0_state ep0state; +@@ -935,6 +982,8 @@ struct dwc3 { + struct dwc3_hwparams hwparams; + struct dentry *root; + struct debugfs_regset32 *regset; ++#define DWC3_DEBUGFS_DBGDUMP 0 ++#define DWC3_DEBUGFS_EVENTS 0 + + u8 test_mode; + u8 test_mode_nr; +@@ -945,6 +994,11 @@ struct dwc3 { + + unsigned connected:1; + unsigned delayed_status:1; ++#ifdef DWC3_EP0_SCHEDULING ++ unsigned ep0_wait_setup_recv:1; ++ unsigned ep0_schedule_indicator:1; ++ unsigned ep0_scheduled:1; ++#endif + unsigned ep0_bounced:1; + unsigned ep0_expect_in:1; + unsigned has_hibernation:1; +@@ -974,6 +1028,23 @@ struct dwc3 { + + unsigned tx_de_emphasis_quirk:1; + unsigned tx_de_emphasis:2; ++ unsigned is_hibernated:1; ++ ++ u32 *saved_regs; ++ u16 imod_interval; ++ ++#ifdef DWC3_EP0_SCHEDULING ++ /* ep0 thread */ ++ struct task_struct *ep0_evt_task; ++ struct completion ep0_comp; ++#ifdef DWC3_ISOC_MONITOR ++ struct workqueue_struct *isoc_in_wq; // workq to monitor the activation of isoc in xfer ++ struct delayed_work isoc_in_monitor; ++ u8 isoc_in_ep_activated; // xfer state of isoc_in ep ++#endif ++ u8 isoc_in_ep; // isoc_in ep we care ++ u8 isoc_in_ep_stopxfer; // isoc_in ep needs to be end xfer ++#endif + }; + + /* -------------------------------------------------------------------------- */ +@@ -1129,6 +1200,12 @@ struct dwc3_gadget_ep_cmd_params { + void dwc3_set_mode(struct dwc3 *dwc, u32 mode); + u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); + ++/* check whether we are on the DWC_usb3 core */ ++static inline bool dwc3_is_usb3(struct dwc3 *dwc) ++{ ++ return !(dwc->revision & DWC3_REVISION_IS_DWC31); ++} ++ + /* check whether we are on the DWC_usb31 core */ + static inline bool dwc3_is_usb31(struct dwc3 *dwc) + { +@@ -1154,6 +1231,7 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); + int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, + struct dwc3_gadget_ep_cmd_params *params); + int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); ++int dwc3_core_init(struct dwc3 *dwc); + #else + static inline int dwc3_gadget_init(struct dwc3 *dwc) + { return 0; } +diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c +old mode 100644 +new mode 100755 +index 31926dda43c9..bbb4642e53a7 +--- a/drivers/usb/dwc3/debugfs.c ++++ b/drivers/usb/dwc3/debugfs.c +@@ -282,6 +282,30 @@ static const struct debugfs_reg32 dwc3_regs[] = { + dump_register(OSTS), + }; + ++static int dwc3_regdump_show(struct seq_file *s, void *unused) ++{ ++ struct dwc3 *dwc = s->private; ++ u32 n; ++ ++ for(n = 0; n < dwc->regset->nregs; n++) { ++ seq_printf(s, "%s = 0x%08x\n", dwc3_regs[n].name, dwc3_readl(dwc->regs, dwc3_regs[n].offset)); ++ } ++ ++ return 0; ++} ++ ++static int dwc3_regdump_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dwc3_regdump_show, inode->i_private); ++} ++ ++static const struct file_operations dwc3_regdump_fops = { ++ .open = dwc3_regdump_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ + static int dwc3_mode_show(struct seq_file *s, void *unused) + { + struct dwc3 *dwc = s->private; +@@ -720,17 +744,29 @@ static int dwc3_ep_trb_ring_show(struct seq_file *s, void *unused) + unsigned long flags; + int i; + +- spin_lock_irqsave(&dwc->lock, flags); +- if (dep->number <= 1) { +- seq_printf(s, "--\n"); +- goto out; +- } +- + seq_printf(s, "enqueue pointer %d\n", dep->trb_enqueue); + seq_printf(s, "dequeue pointer %d\n", dep->trb_dequeue); + seq_printf(s, "\n--------------------------------------------------\n\n"); + seq_printf(s, "buffer_addr,size,type,ioc,isp_imi,csp,chn,lst,hwo\n"); + ++ spin_lock_irqsave(&dwc->lock, flags); ++ if (dep->number <= 1) { ++ for (i = 0; i < 2; i++) { ++ struct dwc3_trb *trb = &dwc->ep0_trb[i]; ++ ++ seq_printf(s, "%08x%08x,%d,%s,%d,%d,%d,%d,%d,%d\n", ++ trb->bph, trb->bpl, trb->size, ++ dwc3_trb_type_string(trb), ++ !!(trb->ctrl & DWC3_TRB_CTRL_IOC), ++ !!(trb->ctrl & DWC3_TRB_CTRL_ISP_IMI), ++ !!(trb->ctrl & DWC3_TRB_CTRL_CSP), ++ !!(trb->ctrl & DWC3_TRB_CTRL_CHN), ++ !!(trb->ctrl & DWC3_TRB_CTRL_LST), ++ !!(trb->ctrl & DWC3_TRB_CTRL_HWO)); ++ } ++ goto out; ++ } ++ + for (i = 0; i < DWC3_TRB_NUM; i++) { + struct dwc3_trb *trb = &dep->trb_pool[i]; + +@@ -843,6 +879,99 @@ static void dwc3_debugfs_create_endpoint_dirs(struct dwc3 *dwc, + } + } + ++#if DWC3_DEBUGFS_DBGDUMP ++static int dwc3_dbgdump_show(struct seq_file *s, void *unused) ++{ ++ struct dwc3 *dwc = s->private; ++ unsigned long flags; ++ u32 i, data[3][16], bmu; ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ for (i = 0; i < 16; i++) { ++ dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, i << 4); ++ data[0][i] = dwc3_readl(dwc->regs, DWC3_GDBGLSP); ++ } ++ for (i = 0; i < 16; i++) { ++ dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, i); ++ data[1][i] = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO0); ++ data[2][i] = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1); ++ } ++ bmu = dwc3_readl(dwc->regs, DWC3_GDBGBMU); ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ ++ for (i = 0; i < 16; i++) { ++ seq_printf(s, "lsp: %08x\n", data[0][i]); ++ } ++ for (i = 0; i < 16; i++) { ++ seq_printf(s, "ep: %08x %08x\n", data[1][i], data[2][i]); ++ } ++ seq_printf(s, "bmu: %08x\n", bmu); ++ ++ return 0; ++} ++ ++static int dwc3_dbgdump_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dwc3_dbgdump_show, inode->i_private); ++} ++ ++static const struct file_operations dwc3_dbgdump_fops = { ++ .open = dwc3_dbgdump_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++#endif ++ ++#if DWC3_DEBUGFS_EVENTS ++static int dwc3_events_show(struct seq_file *s, void *unused) ++{ ++ struct dwc3 *dwc = s->private; ++ unsigned long flags; ++ int i = 0; ++ union dwc3_event event; ++ struct dwc3_event_buffer *evt = dwc->ev_buf; ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ seq_printf(s, "================= dump events ==============\n"); ++ ++ for(i = 0; i < DWC3_EVENT_BUFFERS_SIZE; i+=4) { ++ event.raw = *(u32 *)(evt->cache + i); ++ if (event.raw & 0x1) { ++ seq_printf(s, "D_%X_%X\t\t", (event.raw&0x1F00)>>8, (event.raw&0x1FF0000)>>16); ++ } ++ else { ++ seq_printf(s, "E_%X_%X_%X_%X\t", (event.raw&0x3E)>>1, (event.raw&0x3C0)>>6, ++ (event.raw&0xF000)>>12, (event.raw&0xFFFF0000)>>16); ++ } ++ if (i != evt->lpos) { ++ seq_printf(s, "\n"); ++ } ++ else { ++ seq_printf(s, "<- lpos\n"); ++ } ++ } ++ ++ seq_printf(s, "============================================\n"); ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ ++ return 0; ++} ++ ++static int dwc3_events_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dwc3_events_show, inode->i_private); ++} ++ ++static const struct file_operations dwc3_events_fops = { ++ .open = dwc3_events_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++#endif ++ + void dwc3_debugfs_init(struct dwc3 *dwc) + { + struct dentry *root; +@@ -866,7 +995,7 @@ void dwc3_debugfs_init(struct dwc3 *dwc) + dwc->regset->nregs = ARRAY_SIZE(dwc3_regs); + dwc->regset->base = dwc->regs - DWC3_GLOBALS_REGS_START; + +- file = debugfs_create_regset32("regdump", S_IRUGO, root, dwc->regset); ++ file = debugfs_create_file("regdump", S_IRUGO, root, dwc, &dwc3_regdump_fops); + if (!file) + dev_dbg(dwc->dev, "Can't create debugfs regdump\n"); + +@@ -891,6 +1020,21 @@ void dwc3_debugfs_init(struct dwc3 *dwc) + + dwc3_debugfs_create_endpoint_dirs(dwc, root); + } ++ ++ if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { ++#if DWC3_DEBUGFS_DBGDUMP ++ file = debugfs_create_file("dbgdump", S_IRUGO, root, ++ dwc, &dwc3_dbgdump_fops); ++ if (!file) ++ dev_dbg(dwc->dev, "Can't create debugfs dbgdump\n"); ++#endif ++#if DWC3_DEBUGFS_EVENTS ++ file = debugfs_create_file("events", S_IRUGO, root, ++ dwc, &dwc3_events_fops); ++ if (!file) ++ dev_dbg(dwc->dev, "Can't create debugfs events\n"); ++#endif ++ } + } + + void dwc3_debugfs_exit(struct dwc3 *dwc) +diff --git a/drivers/usb/dwc3/dwc3-keystone.c b/drivers/usb/dwc3/dwc3-keystone.c +index 72664700b8a2..12ee23f53cdd 100644 +--- a/drivers/usb/dwc3/dwc3-keystone.c ++++ b/drivers/usb/dwc3/dwc3-keystone.c +@@ -107,6 +107,10 @@ static int kdwc3_probe(struct platform_device *pdev) + return PTR_ERR(kdwc->usbss); + + kdwc->clk = devm_clk_get(kdwc->dev, "usb"); ++ if (IS_ERR(kdwc->clk)) { ++ dev_err(kdwc->dev, "unable to get usb clock\n"); ++ return PTR_ERR(kdwc->clk); ++ } + + error = clk_prepare_enable(kdwc->clk); + if (error < 0) { +diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c +index a3e2200f5b5f..58526932d2b6 100644 +--- a/drivers/usb/dwc3/dwc3-of-simple.c ++++ b/drivers/usb/dwc3/dwc3-of-simple.c +@@ -132,8 +132,9 @@ static int dwc3_of_simple_remove(struct platform_device *pdev) + + of_platform_depopulate(dev); + +- pm_runtime_put_sync(dev); + pm_runtime_disable(dev); ++ pm_runtime_put_noidle(dev); ++ pm_runtime_set_suspended(dev); + + return 0; + } +diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c +index 35b63518baf6..8e69150776f5 100644 +--- a/drivers/usb/dwc3/dwc3-omap.c ++++ b/drivers/usb/dwc3/dwc3-omap.c +@@ -512,15 +512,6 @@ static int dwc3_omap_probe(struct platform_device *pdev) + + /* check the DMA Status */ + reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); +- irq_set_status_flags(omap->irq, IRQ_NOAUTOEN); +- ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, +- dwc3_omap_interrupt_thread, IRQF_SHARED, +- "dwc3-omap", omap); +- if (ret) { +- dev_err(dev, "failed to request IRQ #%d --> %d\n", +- omap->irq, ret); +- goto err1; +- } + + ret = dwc3_omap_extcon_register(omap); + if (ret < 0) +@@ -532,8 +523,15 @@ static int dwc3_omap_probe(struct platform_device *pdev) + goto err2; + } + ++ ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, ++ dwc3_omap_interrupt_thread, IRQF_SHARED, ++ "dwc3-omap", omap); ++ if (ret) { ++ dev_err(dev, "failed to request IRQ #%d --> %d\n", ++ omap->irq, ret); ++ goto err1; ++ } + dwc3_omap_enable_irqs(omap); +- enable_irq(omap->irq); + return 0; + + err2: +@@ -598,9 +596,25 @@ static int dwc3_omap_resume(struct device *dev) + return 0; + } + ++static void dwc3_omap_complete(struct device *dev) ++{ ++ struct dwc3_omap *omap = dev_get_drvdata(dev); ++ ++ if (extcon_get_state(omap->edev, EXTCON_USB)) ++ dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); ++ else ++ dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); ++ ++ if (extcon_get_state(omap->edev, EXTCON_USB_HOST)) ++ dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); ++ else ++ dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); ++} ++ + static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { + + SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) ++ .complete = dwc3_omap_complete, + }; + + #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) +diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c +index 427291a19e6d..d6493abcf6bc 100644 +--- a/drivers/usb/dwc3/dwc3-pci.c ++++ b/drivers/usb/dwc3/dwc3-pci.c +@@ -173,7 +173,7 @@ static int dwc3_pci_probe(struct pci_dev *pci, + ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res)); + if (ret) { + dev_err(dev, "couldn't add resources to dwc3 device\n"); +- return ret; ++ goto err; + } + + dwc3->dev.parent = dev; +diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c +old mode 100644 +new mode 100755 +index 2331469f943d..8e837cc3a4d3 +--- a/drivers/usb/dwc3/ep0.c ++++ b/drivers/usb/dwc3/ep0.c +@@ -34,6 +34,7 @@ + #include "debug.h" + #include "gadget.h" + #include "io.h" ++#include "../drivers/sstar/include/ms_platform.h" + + static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); + static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, +@@ -55,11 +56,39 @@ static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) + } + } + ++#ifdef DWC3_TRACE_EP0 ++static const char *dwc3_ep0_trb_type_string(u32 type) ++{ ++ switch (type) ++ { ++ case DWC3_TRBCTL_NORMAL: ++ return "normal"; ++ case DWC3_TRBCTL_CONTROL_SETUP: ++ return "setup"; ++ case DWC3_TRBCTL_CONTROL_STATUS2: ++ return "status2"; ++ case DWC3_TRBCTL_CONTROL_STATUS3: ++ return "status3"; ++ case DWC3_TRBCTL_CONTROL_DATA: ++ return "data"; ++ case DWC3_TRBCTL_ISOCHRONOUS_FIRST: ++ return "isoc-first"; ++ case DWC3_TRBCTL_ISOCHRONOUS: ++ return "isoc"; ++ case DWC3_TRBCTL_LINK_TRB: ++ return "link"; ++ default: ++ return "UNKNOWN"; ++ } ++} ++#endif ++ + static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum, + dma_addr_t buf_dma, u32 len, u32 type, bool chain) + { + struct dwc3_trb *trb; + struct dwc3_ep *dep; ++ dma_addr_t miu_addr; + + dep = dwc->eps[epnum]; + +@@ -68,8 +97,9 @@ static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum, + if (chain) + dep->trb_enqueue++; + +- trb->bpl = lower_32_bits(buf_dma); +- trb->bph = upper_32_bits(buf_dma); ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(buf_dma); ++ trb->bpl = lower_32_bits(miu_addr); ++ trb->bph = upper_32_bits(miu_addr); + trb->size = len; + trb->ctrl = type; + +@@ -83,6 +113,19 @@ static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum, + | DWC3_TRB_CTRL_LST); + + trace_dwc3_prepare_trb(dep, trb); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "ep0_prepare_trb: %d/%d trb %p buf %08x%08x size %d ctrl %08x (%c%c%c%c:%c%c:%s)", ++ dep->queued_requests, dep->allocated_requests, ++ trb, trb->bph, trb->bpl, ++ trb->size, trb->ctrl, ++ trb->ctrl & DWC3_TRB_CTRL_HWO ? 'H' : 'h', ++ trb->ctrl & DWC3_TRB_CTRL_LST ? 'L' : 'l', ++ trb->ctrl & DWC3_TRB_CTRL_CHN ? 'C' : 'c', ++ trb->ctrl & DWC3_TRB_CTRL_CSP ? 'S' : 's', ++ trb->ctrl & DWC3_TRB_CTRL_ISP_IMI ? 'S' : 's', ++ trb->ctrl & DWC3_TRB_CTRL_IOC ? 'C' : 'c', ++ dwc3_ep0_trb_type_string(trb->ctrl & 0x3f0)); ++#endif + } + + static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum) +@@ -90,21 +133,30 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum) + struct dwc3_gadget_ep_cmd_params params; + struct dwc3_ep *dep; + int ret; ++ dma_addr_t miu_addr; + + dep = dwc->eps[epnum]; + if (dep->flags & DWC3_EP_BUSY) { + dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =%s still busy", dep->name); ++#endif + return 0; + } + + memset(¶ms, 0, sizeof(params)); +- params.param0 = upper_32_bits(dwc->ep0_trb_addr); +- params.param1 = lower_32_bits(dwc->ep0_trb_addr); ++ Chip_Flush_MIU_Pipe(); ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(dwc->ep0_trb_addr); ++ params.param0 = upper_32_bits(miu_addr); ++ params.param1 = lower_32_bits(miu_addr); + + ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); + if (ret < 0) { + dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed", + dep->name); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =%s STARTTRANSFER failed", dep->name); ++#endif + return ret; + } + +@@ -138,7 +190,7 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, + if (dep->flags & DWC3_EP_PENDING_REQUEST) { + unsigned direction; + +- direction = !!(dep->flags & DWC3_EP0_DIR_IN); ++ direction = dwc->ep0_expect_in; + + if (dwc->ep0state != EP0_DATA_PHASE) { + dev_WARN(dwc->dev, "Unexpected pending request\n"); +@@ -147,8 +199,7 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, + + __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); + +- dep->flags &= ~(DWC3_EP_PENDING_REQUEST | +- DWC3_EP0_DIR_IN); ++ dep->flags &= ~DWC3_EP_PENDING_REQUEST; + + return 0; + } +@@ -164,11 +215,26 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, + dwc->delayed_status = false; + usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); + +- if (dwc->ep0state == EP0_STATUS_PHASE) ++ if (dwc->ep0state == EP0_STATUS_PHASE) { ++#ifdef DWC3_EP0_SCHEDULING ++ // indicator flag hints that schedule contol status by ep0 thread is needed ++ if (dwc->ep0_schedule_indicator) { ++ dwc->ep0_scheduled = true; ++ return 0; ++ } ++ else { ++ dwc->ep0_scheduled = false; ++ } ++#endif + __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); +- else ++ } ++ else { + dwc3_trace(trace_dwc3_ep0, + "too early for delayed status"); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =too early for delayed status"); ++#endif ++ } + + return 0; + } +@@ -209,11 +275,19 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, + unsigned direction; + + direction = dwc->ep0_expect_in; ++#ifdef DWC3_EP0_SCHEDULING ++ // indicator flag hints that schedule IN contol data by ep0 thread is needed ++ if (dwc->ep0_schedule_indicator) { ++ dwc->ep0_scheduled = true; ++ return 0; ++ } ++ else { ++ dwc->ep0_scheduled = false; ++ } ++#endif + dwc->ep0state = EP0_DATA_PHASE; + + __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); +- +- dep->flags &= ~DWC3_EP0_DIR_IN; + } + + return 0; +@@ -235,6 +309,9 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, + dwc3_trace(trace_dwc3_ep0, + "trying to queue request %p to disabled %s", + request, dep->name); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =trying to queue request %p to disabled %s", request, dep->name); ++#endif + ret = -ESHUTDOWN; + goto out; + } +@@ -249,6 +326,18 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, + "queueing request %p to %s length %d state '%s'", + request, dep->name, request->length, + dwc3_ep0_state_string(dwc->ep0state)); ++#ifdef DWC3_TRACE_EP0 ++ { ++ unsigned direction; ++ if (dwc->ep0state == EP0_SETUP_PHASE && dwc->three_stage_setup) ++ direction = dwc->ep0_expect_in; ++ else ++ direction = !dwc->ep0_expect_in; ++ printk(KERN_DEBUG "queueing request %p to %s length %d state '%s'", ++ request, dwc->eps[direction]->name, request->length, ++ dwc3_ep0_state_string(dwc->ep0state)); ++ } ++#endif + + ret = __dwc3_gadget_ep0_queue(dep, req); + +@@ -433,10 +522,10 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, + return -EINVAL; + + reg = dwc3_readl(dwc->regs, DWC3_DCTL); +- if (set) +- reg |= DWC3_DCTL_INITU1ENA; +- else +- reg &= ~DWC3_DCTL_INITU1ENA; ++ //if (set) ++ //reg |= DWC3_DCTL_INITU1ENA; ++ //else ++ //reg &= ~DWC3_DCTL_INITU1ENA; + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + break; + +@@ -448,10 +537,10 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, + return -EINVAL; + + reg = dwc3_readl(dwc->regs, DWC3_DCTL); +- if (set) +- reg |= DWC3_DCTL_INITU2ENA; +- else +- reg &= ~DWC3_DCTL_INITU2ENA; ++ //if (set) ++ //reg |= DWC3_DCTL_INITU2ENA; ++ //else ++ //reg &= ~DWC3_DCTL_INITU2ENA; + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + break; + +@@ -595,7 +684,7 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) + * nothing is pending from application. + */ + reg = dwc3_readl(dwc->regs, DWC3_DCTL); +- reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); ++ //reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + } + break; +@@ -768,6 +857,13 @@ static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, + + trace_dwc3_ctrl_req(ctrl); + ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->ep0_wait_setup_recv) { ++ complete(&dwc->ep0_comp); ++ dwc->ep0_wait_setup_recv = false; ++ } ++#endif ++ + len = le16_to_cpu(ctrl->wLength); + if (!len) { + dwc->three_stage_setup = false; +@@ -816,6 +912,19 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, + trb = dwc->ep0_trb; + + trace_dwc3_complete_trb(ep0, trb); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "ep0_complete_trb: %d/%d trb %p buf %08x%08x size %d ctrl %08x (%c%c%c%c:%c%c:%s)", ++ ep0->queued_requests, ep0->allocated_requests, ++ trb, trb->bph, trb->bpl, ++ trb->size, trb->ctrl, ++ trb->ctrl & DWC3_TRB_CTRL_HWO ? 'H' : 'h', ++ trb->ctrl & DWC3_TRB_CTRL_LST ? 'L' : 'l', ++ trb->ctrl & DWC3_TRB_CTRL_CHN ? 'C' : 'c', ++ trb->ctrl & DWC3_TRB_CTRL_CSP ? 'S' : 's', ++ trb->ctrl & DWC3_TRB_CTRL_ISP_IMI ? 'S' : 's', ++ trb->ctrl & DWC3_TRB_CTRL_IOC ? 'C' : 'c', ++ dwc3_ep0_trb_type_string(trb->ctrl & 0x3f0)); ++#endif + + r = next_request(&ep0->pending_list); + if (!r) +@@ -826,7 +935,9 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, + dwc->setup_packet_pending = true; + + dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); +- ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =Setup Pending received"); ++#endif + if (r) + dwc3_gadget_giveback(ep0, r, -ECONNRESET); + +@@ -904,6 +1015,19 @@ static void dwc3_ep0_complete_status(struct dwc3 *dwc, + trb = dwc->ep0_trb; + + trace_dwc3_complete_trb(dep, trb); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "ep0_complete_trb: %d/%d trb %p buf %08x%08x size %d ctrl %08x (%c%c%c%c:%c%c:%s)", ++ dep->queued_requests, dep->allocated_requests, ++ trb, trb->bph, trb->bpl, ++ trb->size, trb->ctrl, ++ trb->ctrl & DWC3_TRB_CTRL_HWO ? 'H' : 'h', ++ trb->ctrl & DWC3_TRB_CTRL_LST ? 'L' : 'l', ++ trb->ctrl & DWC3_TRB_CTRL_CHN ? 'C' : 'c', ++ trb->ctrl & DWC3_TRB_CTRL_CSP ? 'S' : 's', ++ trb->ctrl & DWC3_TRB_CTRL_ISP_IMI ? 'S' : 's', ++ trb->ctrl & DWC3_TRB_CTRL_IOC ? 'C' : 'c', ++ dwc3_ep0_trb_type_string(trb->ctrl & 0x3f0)); ++#endif + + if (!list_empty(&dep->pending_list)) { + r = next_request(&dep->pending_list); +@@ -927,10 +1051,18 @@ static void dwc3_ep0_complete_status(struct dwc3 *dwc, + if (status == DWC3_TRBSTS_SETUP_PENDING) { + dwc->setup_packet_pending = true; + dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =Setup Pending received"); ++#endif + } + + dwc->ep0state = EP0_SETUP_PHASE; + dwc3_ep0_out_start(dwc); ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->ep0_scheduled) { ++ complete(&dwc->ep0_comp); // ep0 xfer was scheduled & wait completion, wakeup up ep0 thread here ++ } ++#endif + } + + static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, +@@ -951,6 +1083,11 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, + case EP0_DATA_PHASE: + dwc3_trace(trace_dwc3_ep0, "Data Phase"); + dwc3_ep0_complete_data(dwc, event); ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->ep0_scheduled) { ++ complete(&dwc->ep0_comp); // ep0 xfer was scheduled & wait completion, wakeup up ep0 thread here ++ } ++#endif + break; + + case EP0_STATUS_PHASE: +@@ -983,6 +1120,9 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, + dep->number); + if (ret) { + dwc3_trace(trace_dwc3_ep0, "failed to map request"); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =failed to map request"); ++#endif + return; + } + +@@ -1012,6 +1152,9 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, + dep->number); + if (ret) { + dwc3_trace(trace_dwc3_ep0, "failed to map request"); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =failed to map request"); ++#endif + return; + } + +@@ -1047,6 +1190,16 @@ static void dwc3_ep0_do_control_status(struct dwc3 *dwc, + { + struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; + ++#ifdef DWC3_EP0_SCHEDULING ++ // indicator flag hints that schedule contol status by ep0 thread is needed ++ if (dwc->ep0_schedule_indicator) { ++ dwc->ep0_scheduled = true; ++ return; ++ } ++ else { ++ dwc->ep0_scheduled = false; ++ } ++#endif + __dwc3_ep0_do_control_status(dwc, dep); + } + +@@ -1089,6 +1242,13 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc, + + dwc3_trace(trace_dwc3_ep0, + "Wrong direction for Data phase"); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =Wrong direction for Data phase %d %d", dwc->ep0_expect_in, event->endpoint_number); ++ printk(KERN_DEBUG "bRequestType %02x bRequest %02x wValue %04x wIndex %04x wLength %d", ++ dwc->ctrl_req->bRequestType, dwc->ctrl_req->bRequest, ++ dwc->ctrl_req->wValue, dwc->ctrl_req->wIndex, ++ dwc->ctrl_req->wLength); ++#endif + dwc3_ep0_end_control_data(dwc, dep); + dwc3_ep0_stall_and_restart(dwc); + return; +@@ -1106,7 +1266,13 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc, + + if (dwc->delayed_status) { + WARN_ON_ONCE(event->endpoint_number != 1); ++#ifdef DWC3_EP0_SCHEDULING ++ dwc->ep0_scheduled = false; ++#endif + dwc3_trace(trace_dwc3_ep0, "Delayed Status"); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "\t =Delayed Status"); ++#endif + return; + } + +@@ -1120,6 +1286,10 @@ void dwc3_ep0_interrupt(struct dwc3 *dwc, + dwc3_trace(trace_dwc3_ep0, "%s: state '%s'", + dwc3_ep_event_string(event), + dwc3_ep0_state_string(dwc->ep0state)); ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "%s %s %x", dwc3_ep_event_string(event), ++ dwc3_ep0_state_string(dwc->ep0state), event->status); ++#endif + + switch (event->endpoint_event) { + case DWC3_DEPEVT_XFERCOMPLETE: +@@ -1137,3 +1307,99 @@ void dwc3_ep0_interrupt(struct dwc3 *dwc, + break; + } + } ++ ++#ifdef DWC3_EP0_SCHEDULING ++extern void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); ++ ++int dwc3_ep0_thread(void *arg) ++{ ++ struct dwc3 *dwc = (struct dwc3 *)arg; ++ unsigned long flags, completed; ++ struct dwc3_ep *ep0, *dep; ++ ++ while(!kthread_should_stop()) ++ { ++ wait_for_completion(&dwc->ep0_comp); ++ ep0 = dwc->eps[0]; ++ ++ if (!dwc->ep0_scheduled) ++ goto do_endxfer; ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ if ((dwc->ep0state == EP0_SETUP_PHASE) && !list_empty(&ep0->pending_list) && dwc->three_stage_setup) ++ { ++ dwc->ep0state = EP0_DATA_PHASE; ++ if (dwc->ep0_expect_in) ++ dep = dwc->eps[1]; ++ else ++ dep = dwc->eps[0]; ++ __dwc3_ep0_do_control_data(dwc, dep, next_request(&ep0->pending_list)); ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ wait_for_completion(&dwc->ep0_comp); ++ } ++ else if (dwc->ep0state == EP0_STATUS_PHASE && dwc->ep0_next_event == DWC3_EP0_NRDY_STATUS) ++ { ++ if (dwc->ep0_expect_in) ++ dep = dwc->eps[0]; ++ else ++ dep = dwc->eps[1]; ++ __dwc3_ep0_do_control_status(dwc, dep); ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ wait_for_completion(&dwc->ep0_comp); ++ } ++ else { ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ } ++ spin_lock_irqsave(&dwc->lock, flags); ++ if (!dwc->ep0_schedule_indicator) // no need to schedule ep0 xfer, let's handle ep0 in irq thread ++ dwc->ep0_scheduled = false; ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ ++do_endxfer: ++ if (dwc->isoc_in_ep_stopxfer) { ++ u32 ep_num = 0; ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ if (dwc->ep0state == EP0_SETUP_PHASE && dwc->ep0_next_event == DWC3_EP0_COMPLETE) { ++ u32 reg = dwc3_readl(dwc->regs, DWC3_DSTS); ++ if (!(reg & DWC3_DSTS_RXFIFOEMPTY)) { // RxFIFO is not empty, wait till setup xfer completed ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG"@Rx"); ++#endif ++ dwc->ep0_wait_setup_recv = true; ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ completed = wait_for_completion_timeout(&dwc->ep0_comp, __msecs_to_jiffies(10)); ++ if (!completed) ++ dwc->ep0_wait_setup_recv = false; ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG"^Rx%ld", completed); ++#endif ++ } ++ else { ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ } ++ } ++ else { ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ } ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ ep_num = dwc->isoc_in_ep_stopxfer; ++ dep = dwc->eps[ep_num]; ++ dwc3_stop_active_transfer(dwc, ep_num, true); ++ dep->flags = DWC3_EP_ENABLED; ++ dwc->isoc_in_ep_stopxfer = 0; ++ if (dep->pending_requests || dep->queued_requests) { ++ dwc->ep0_schedule_indicator = true; ++#ifdef DWC3_ISOC_MONITOR ++ dwc->isoc_in_ep_activated = false; ++ // 35ms delayed work to monitor whether isoc xfer keeps in progressing ++ mod_delayed_work(dwc->isoc_in_wq, &dwc->isoc_in_monitor, __msecs_to_jiffies(35)); ++#endif ++ } ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ } ++ } ++ return 0; ++} ++#endif +diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c +old mode 100644 +new mode 100755 +index f483c3b1e971..50be8c5ed2e0 +--- a/drivers/usb/dwc3/gadget.c ++++ b/drivers/usb/dwc3/gadget.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -34,6 +35,74 @@ + #include "core.h" + #include "gadget.h" + #include "io.h" ++#include "../drivers/sstar/include/ms_platform.h" ++ ++/* ++ * Under USB version 2.10 or later, windows cannot support ++ * bulk endpoint with maxpacket size less than 512 bytes. ++ * So in this case, we can use this instance to use usb version 2.0. ++ */ ++static bool assume_high_speed = false; ++module_param(assume_high_speed, bool, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(assume_high_speed, "1: Force DWC3 run under high speed mode"); ++ ++#define MS_IO_OFFSET 0xDE000000 ++/* macro to get at MMIO space when running virtually */ ++#define IO_ADDRESS(x) ( (u32)(x) + MS_IO_OFFSET ) ++#define ms_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++#define ms_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++#define INREG16(x) ms_readw(x) ++#define OUTREG16(x, y) ms_writew((u16)(y), x) ++#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) ++#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) ++ ++#define DWC3_ALIGN_FRAME(f, i, n) (((f) + ((i) * (n))) \ ++ & ~((i) - 1)) ++ ++extern void phy_utmi_reset(void); ++ ++/* array of registers to save on hibernation and restore them on wakeup */ ++static u32 save_reg_addr[] = { ++ DWC3_DCTL, ++ DWC3_DCFG, ++ DWC3_DEVTEN, ++ DWC3_GSBUSCFG0, ++ DWC3_GSBUSCFG1, ++ DWC3_GTXTHRCFG, ++ DWC3_GRXTHRCFG, ++ DWC3_GCTL, ++ DWC3_GUSB2PHYCFG(0), ++ DWC3_GUSB3PIPECTL(0), ++ DWC3_GTXFIFOSIZ(0), ++ DWC3_GRXFIFOSIZ(0) ++}; ++ ++#ifdef DWC3_ISOC_MONITOR ++/** ++ * __dwc3_gadget_check_isoc_activating - Check if a specified isoc in ep xfer is activating or not ++ * ++ * This function checks whether the specified isoc in ep has an activated xfer. ++ * If xfer was stopped due to no more TP/IN from host, we should handle ep0 xfer in irq thread directly. ++ */ ++static void __dwc3_gadget_check_isoc_activating(struct work_struct *work) ++{ ++ struct dwc3 *dwc = container_of(to_delayed_work(work), struct dwc3, isoc_in_monitor); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dwc->lock, flags); ++ if (dwc->ep0_schedule_indicator && (dwc->isoc_in_ep_activated == false)) { ++ // now ep0 xfer is handled by ep0 thread which will be triggered by isoc xfer. ++ // we check the activating of isoc xfer here, and return ep0 xfer handling back to irq thread ++ // if isoc xfer is unexpectedly stopped. ++ dwc->ep0_schedule_indicator = false; ++ if (dwc->ep0_scheduled) ++ complete(&dwc->ep0_comp); ++ ++ printk(KERN_DEBUG"isoc xfer seems stopped"); ++ } ++ spin_unlock_irqrestore(&dwc->lock, flags); ++} ++#endif + + /** + * dwc3_gadget_set_test_mode - Enables USB2 Test Modes +@@ -63,6 +132,11 @@ int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) + return -EINVAL; + } + ++ if ((mode == TEST_J) || (mode == TEST_K) || (mode == TEST_SE0_NAK)) ++ CLRREG16(0x1F284200 + 0x16*4, 0x200); ++ if (mode == TEST_PACKET) ++ SETREG16(0x1F284200 + 0x16*4, 0xc); ++ + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + + return 0; +@@ -234,6 +308,7 @@ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) + if (!timeout) { + ret = -ETIMEDOUT; + status = -ETIMEDOUT; ++ printk("failed to generic_command TMO\n"); + } + + trace_dwc3_gadget_generic_cmd(cmd, param, status); +@@ -247,13 +322,14 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, + struct dwc3_gadget_ep_cmd_params *params) + { + struct dwc3 *dwc = dep->dwc; +- u32 timeout = 1000; ++#define SEND_EP_CMD_TIMEOUT 2000 ++ u32 timeout = SEND_EP_CMD_TIMEOUT; + u32 reg; + + int cmd_status = 0; + int susphy = false; +- int ret = -EINVAL; +- ++ int ret = -EINVAL; //-22 ++ const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; + /* + * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if + * we're issuing an endpoint command, we must check if +@@ -271,7 +347,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, + } + } + +- if (cmd == DWC3_DEPCMD_STARTTRANSFER) { ++ if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { + int needs_wakeup; + + needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || +@@ -289,7 +365,13 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, + dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); + dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); + +- dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT); ++ if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && ++ !usb_endpoint_xfer_isoc(desc)) ++ cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); ++ else ++ cmd |= DWC3_DEPCMD_CMDACT; ++ ++ dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); + do { + reg = dwc3_readl(dep->regs, DWC3_DEPCMD); + if (!(reg & DWC3_DEPCMD_CMDACT)) { +@@ -322,21 +404,46 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, + + break; + } ++ /* ++ * For isoc transfer, send EP ENDTRANSFER command ++ * is used to generate a XferNotReady event. ++ * We might not need to wait CMDACT bit clear here because ++ * any further operation is impossible without the XferNotReady event. ++ */ ++ if ((DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) && ++ (timeout < (SEND_EP_CMD_TIMEOUT - 50)) && ++ (dep->endpoint.desc) && ++ (usb_endpoint_xfer_isoc(dep->endpoint.desc))) ++ { ++ // no wait CMDACT clear ++ ret = 0; ++ printk(KERN_DEBUG "EP%dTO\r\n", dep->number); ++ break; ++ } + } while (--timeout); + + if (timeout == 0) { + ret = -ETIMEDOUT; + cmd_status = -ETIMEDOUT; ++ printk("[%s]L:%d failed TMO\n", __FUNCTION__, __LINE__); + } + + trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); + ++ if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { ++ dep->flags |= DWC3_EP_TRANSFER_STARTED; ++ dwc3_gadget_ep_get_transfer_index(dep); ++ } ++ + if (unlikely(susphy)) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg |= DWC3_GUSB2PHYCFG_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + } + ++ if (ret && (ret != -EAGAIN)) { ++ printk("send cmd %x failed to ret:%d sts:%d\n", DWC3_DEPCMD_CMD(cmd), ret, cmd_status); ++ } + return ret; + } + +@@ -448,6 +555,7 @@ static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) + memset(¶ms, 0x00, sizeof(params)); + cmd = DWC3_DEPCMD_DEPSTARTCFG; + ++ Chip_Flush_MIU_Pipe(); + ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); + if (ret) + return ret; +@@ -466,6 +574,21 @@ static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) + return 0; + } + ++static void dwc3_gadget_get_ep_state(struct dwc3 *dwc, struct dwc3_ep *dep) ++{ ++ struct dwc3_gadget_ep_cmd_params params; ++ int ret; ++ u32 cmd; ++ ++ memset(¶ms, 0, sizeof(params)); ++ cmd = DWC3_DEPCMD_GETEPSTATE; ++ ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); ++ if (ret == 0) { ++ dep->saved_state = dwc3_readl(dep->regs, DWC3_DEPCMDPAR2); ++ } ++ ++} ++ + static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, + const struct usb_endpoint_descriptor *desc, + const struct usb_ss_ep_comp_descriptor *comp_desc, +@@ -562,21 +685,26 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, + struct dwc3 *dwc = dep->dwc; + u32 reg; + int ret; ++ dma_addr_t miu_addr; + + dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); + +- if (!(dep->flags & DWC3_EP_ENABLED)) { ++ if (!(dep->flags & DWC3_EP_ENABLED) || dwc->is_hibernated) { + ret = dwc3_gadget_start_config(dwc, dep); +- if (ret) +- return ret; ++ if (ret) { ++ printk("[%s]L:%d\n", __FUNCTION__, __LINE__); ++ return ret; ++ } + } + + ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify, + restore); +- if (ret) +- return ret; ++ if (ret) { ++ printk("[%s]L:%d\n", __FUNCTION__, __LINE__); ++ return ret; ++ } + +- if (!(dep->flags & DWC3_EP_ENABLED)) { ++ if (!(dep->flags & DWC3_EP_ENABLED) || dwc->is_hibernated) { + struct dwc3_trb *trb_st_hw; + struct dwc3_trb *trb_link; + +@@ -593,29 +721,48 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, + return 0; + + /* Initialize the TRB ring */ +- dep->trb_dequeue = 0; +- dep->trb_enqueue = 0; +- memset(dep->trb_pool, 0, +- sizeof(struct dwc3_trb) * DWC3_TRB_NUM); ++ if(!dwc->is_hibernated) ++ { ++ dep->trb_dequeue = 0; ++ dep->trb_enqueue = 0; ++ memset(dep->trb_pool, 0, sizeof(struct dwc3_trb) * DWC3_TRB_NUM); ++ } + + /* Link TRB. The HWO bit is never reset */ + trb_st_hw = &dep->trb_pool[0]; + + trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; +- trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); +- trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(dwc3_trb_dma_offset(dep, trb_st_hw)); ++ trb_link->bpl = lower_32_bits(miu_addr); ++ trb_link->bph = upper_32_bits(miu_addr); + trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; + trb_link->ctrl |= DWC3_TRB_CTRL_HWO; ++#ifdef DWC3_EP0_SCHEDULING ++ // FIXME: we only care about (ep1 isoc IN) here, which able to send long burst data ++ if (dep->direction && usb_endpoint_xfer_isoc(desc) && (dep->number == 3)) { ++ dwc->isoc_in_ep = dep->number; ++ dwc->isoc_in_ep_stopxfer = 0; ++ } ++#endif + } + + return 0; + } + ++#ifdef DWC3_EP0_SCHEDULING ++void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); ++#else + static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); ++#endif + static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) + { + struct dwc3_request *req; + ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep_stopxfer == dep->number) { ++ dwc->isoc_in_ep_stopxfer = 0; ++ } ++#endif + dwc3_stop_active_transfer(dwc, dep->number, true); + + /* - giveback all requests to gadget driver */ +@@ -627,6 +774,7 @@ static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) + + while (!list_empty(&dep->pending_list)) { + req = next_request(&dep->pending_list); ++ dep->pending_requests--; + + dwc3_gadget_giveback(dep, req, -ESHUTDOWN); + } +@@ -648,6 +796,16 @@ static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) + dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); + + dwc3_remove_requests(dwc, dep); ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep == dep->number) { ++ dwc->isoc_in_ep = 0; ++ dwc->isoc_in_ep_stopxfer = 0; ++ dwc->ep0_schedule_indicator = false; ++ if (dwc->ep0_scheduled) { ++ complete(&dwc->ep0_comp); ++ } ++ } ++#endif + + /* make sure HW endpoint isn't stalled */ + if (dep->flags & DWC3_EP_STALL) +@@ -729,16 +887,30 @@ static int dwc3_gadget_ep_disable(struct usb_ep *ep) + dep = to_dwc3_ep(ep); + dwc = dep->dwc; + +- if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), +- "%s is already disabled\n", +- dep->name)) +- return 0; +- + spin_lock_irqsave(&dwc->lock, flags); ++ if (!(dep->flags & DWC3_EP_ENABLED)) { ++ if ((dep->endpoint.desc) && usb_endpoint_xfer_isoc(dep->endpoint.desc) && ++#ifdef DWC3_EP0_SCHEDULING ++ ((dep->flags == DWC3_EP_PENDING_REQUEST) || (dwc->isoc_in_ep_stopxfer == dep->number))) ++#else ++ (dep->flags == DWC3_EP_PENDING_REQUEST)) ++#endif ++ { ++ // isoc ep has stopped due to no started reqeusts ++ } ++ else { ++ goto ep_disabled; ++ } ++ } ++ + ret = __dwc3_gadget_ep_disable(dep); + spin_unlock_irqrestore(&dwc->lock, flags); + + return ret; ++ ++ep_disabled: ++ printk(KERN_DEBUG"\n%s is already disabled, flag %x\n", dep->name, dep->flags); ++ return 0; + } + + static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, +@@ -780,13 +952,14 @@ static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep); + * @req: dwc3_request pointer + */ + static void dwc3_prepare_one_trb(struct dwc3_ep *dep, +- struct dwc3_request *req, dma_addr_t dma, ++ struct dwc3_request *req, dma_addr_t dma, unsigned total_len, + unsigned length, unsigned chain, unsigned node) + { + struct dwc3_trb *trb; + struct dwc3 *dwc = dep->dwc; + struct usb_gadget *gadget = &dwc->gadget; + enum usb_device_speed speed = gadget->speed; ++ dma_addr_t miu_addr; + + dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s", + dep->name, req, (unsigned long long) dma, +@@ -800,13 +973,15 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, + req->trb_dma = dwc3_trb_dma_offset(dep, trb); + req->first_trb_index = dep->trb_enqueue; + dep->queued_requests++; ++ dep->pending_requests--; + } + + dwc3_ep_inc_enq(dep); + + trb->size = DWC3_TRB_SIZE_LENGTH(length); +- trb->bpl = lower_32_bits(dma); +- trb->bph = upper_32_bits(dma); ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(dma); ++ trb->bpl = lower_32_bits(miu_addr); ++ trb->bph = upper_32_bits(miu_addr); + + switch (usb_endpoint_type(dep->endpoint.desc)) { + case USB_ENDPOINT_XFER_CONTROL: +@@ -841,15 +1016,15 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, + */ + if (speed == USB_SPEED_HIGH) { + struct usb_ep *ep = &dep->endpoint; +- unsigned int mult = ep->mult - 1; ++ unsigned int mult = 2; + unsigned int maxp; + + maxp = usb_endpoint_maxp(ep->desc) & 0x07ff; + +- if (length <= (2 * maxp)) ++ if (total_len <= (2 * maxp)) + mult--; + +- if (length <= maxp) ++ if (total_len <= maxp) + mult--; + + trb->size |= DWC3_TRB_SIZE_PCM1(mult); +@@ -949,6 +1124,16 @@ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, + dma_addr_t dma; + int i; + ++ unsigned total_len = 0; ++ ++ for_each_sg(sg, s, req->num_pending_sgs, i) { ++ total_len += sg_dma_len(s); ++ if (sg_is_last(s)) ++ break; ++ if (!dwc3_calc_trbs_left(dep)) ++ return; ++ } ++ + for_each_sg(sg, s, req->num_pending_sgs, i) { + unsigned chain = true; + +@@ -958,7 +1143,7 @@ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, + if (sg_is_last(s)) + chain = false; + +- dwc3_prepare_one_trb(dep, req, dma, length, ++ dwc3_prepare_one_trb(dep, req, dma, total_len, length, + chain, i); + + if (!dwc3_calc_trbs_left(dep)) +@@ -975,7 +1160,7 @@ static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, + dma = req->request.dma; + length = req->request.length; + +- dwc3_prepare_one_trb(dep, req, dma, length, ++ dwc3_prepare_one_trb(dep, req, dma, length, length, + false, 0); + } + +@@ -1015,6 +1200,7 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) + int starting; + int ret; + u32 cmd; ++ dma_addr_t miu_addr; + + starting = !(dep->flags & DWC3_EP_BUSY); + +@@ -1026,10 +1212,11 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) + } + + memset(¶ms, 0, sizeof(params)); +- ++ Chip_Flush_MIU_Pipe(); + if (starting) { +- params.param0 = upper_32_bits(req->trb_dma); +- params.param1 = lower_32_bits(req->trb_dma); ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(req->trb_dma); ++ params.param0 = upper_32_bits(miu_addr); ++ params.param1 = lower_32_bits(miu_addr); + cmd = DWC3_DEPCMD_STARTTRANSFER | + DWC3_DEPCMD_PARAM(cmd_param); + } else { +@@ -1039,6 +1226,8 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) + + ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); + if (ret < 0) { ++ if (ret == -EAGAIN) ++ return ret; + /* + * FIXME we need to iterate over the list of requests + * here and stop, unmap, free and del each of the linked +@@ -1055,6 +1244,16 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) + if (starting) { + dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); + WARN_ON_ONCE(!dep->resource_index); ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep == dep->number) { ++ dwc->ep0_schedule_indicator = true; ++ dwc->isoc_in_ep_stopxfer = 0; ++#ifdef DWC3_ISOC_MONITOR ++ dwc->isoc_in_ep_activated = false; ++ mod_delayed_work(dwc->isoc_in_wq, &dwc->isoc_in_monitor, __msecs_to_jiffies(30)); ++#endif ++ } ++#endif + } + + return 0; +@@ -1063,20 +1262,70 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) + static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, + struct dwc3_ep *dep, u32 cur_uf) + { ++ int ret; ++ int i; + u32 uf; + +- if (list_empty(&dep->pending_list)) { ++ if (list_empty(&dep->pending_list) && list_empty(&dep->started_list)) { + dwc3_trace(trace_dwc3_gadget, + "ISOC ep %s run out for requests", + dep->name); ++ printk(KERN_DEBUG"ISOC ep%d run out for requests", dep->number); + dep->flags |= DWC3_EP_PENDING_REQUEST; ++ // due to no StartXfer, we don't have the resource index for later EndXfer. ++ // here we use hw ep number as the resource index, it's dirty but it works. ++ dep->resource_index = dep->number; + return; + } + +- /* 4 micro frames in the future */ +- uf = cur_uf + dep->interval * 4; ++ // start isoc xfer in next u-frame of XferNotReady event seems too rush ++ // and results in miss-isoc easily in high speed. ++ // for high or lower speed, start isoc xfer in next two u-frame ++ i = (dwc->gadget.speed >= USB_SPEED_SUPER) ? 0 : 1; ++ for (; i < DWC3_ISOC_MAX_RETRIES; i++) { ++ uf = DWC3_ALIGN_FRAME(cur_uf, dep->interval, i+1); ++ ++ ret = __dwc3_gadget_kick_transfer(dep, uf); ++ if (ret != -EAGAIN) ++ break; ++ } ++ ++ /* ++ * After a number of unsuccessful start attempts due to bus-expiry ++ * status, issue END_TRANSFER command and retry on the next XferNotReady ++ * event. ++ */ ++ if (ret == -EAGAIN) { ++ if (!dep->resource_index) { ++ // due to no StartXfer, we don't have the resource index for later EndXfer. ++ // here we use hw ep number as the resource index, it's dirty but it works. ++ dep->resource_index = dep->number; ++ } ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep == dep->number) { ++ dwc->isoc_in_ep_stopxfer = dep->number; ++ dwc->ep0_schedule_indicator = true; ++ complete(&dwc->ep0_comp); ++ } ++ else { ++ dwc3_stop_active_transfer(dwc, dep->number, true); ++ dep->flags = DWC3_EP_ENABLED; ++ } ++#else ++ struct dwc3_gadget_ep_cmd_params params; ++ u32 cmd; ++ ++ cmd = DWC3_DEPCMD_ENDTRANSFER | ++ DWC3_DEPCMD_CMDIOC | ++ DWC3_DEPCMD_PARAM(dep->resource_index); ++ ++ //dep->resource_index = 0; ++ memset(¶ms, 0, sizeof(params)); + +- __dwc3_gadget_kick_transfer(dep, uf); ++ ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); ++#endif ++ printk(KERN_DEBUG"ISOC ep%d(%d) over max retry", dep->number, dep->resource_index); ++ } + } + + static void dwc3_gadget_start_isoc(struct dwc3 *dwc, +@@ -1127,6 +1376,12 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) + req->num_pending_sgs = req->request.num_mapped_sgs; + + list_add_tail(&req->list, &dep->pending_list); ++ dep->pending_requests++; ++ ++ /* If core is hibernated, need to wakeup (remote wakeup) */ ++ if (dwc->is_hibernated) { ++ printk("Wake up\n"); ++ } + + /* + * NOTICE: Isochronous endpoints should NEVER be prestarted. We must +@@ -1139,8 +1394,22 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) + if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { + if ((dep->flags & DWC3_EP_PENDING_REQUEST) && + list_empty(&dep->started_list)) { ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep == dep->number) { ++ dwc->isoc_in_ep_stopxfer = dep->number; ++ dwc->ep0_schedule_indicator = true; ++ // wake-up ep0 thread for stopping isoc transfer ++ complete(&dwc->ep0_comp); ++ dep->flags &= ~(DWC3_EP_PENDING_REQUEST); ++ } ++ else { ++ dwc3_stop_active_transfer(dwc, dep->number, true); ++ dep->flags = DWC3_EP_ENABLED; ++ } ++#else + dwc3_stop_active_transfer(dwc, dep->number, true); + dep->flags = DWC3_EP_ENABLED; ++#endif + } + return 0; + } +@@ -1231,8 +1500,10 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, + spin_lock_irqsave(&dwc->lock, flags); + + list_for_each_entry(r, &dep->pending_list, list) { +- if (r == req) ++ if (r == req) { ++ dep->pending_requests--; + break; ++ } + } + + if (r != req) { +@@ -1243,10 +1514,21 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, + if (r == req) { + /* wait until it is processed */ + dwc3_stop_active_transfer(dwc, dep->number, true); ++#ifdef DWC3_EP0_SCHEDULING ++ if ((dwc->isoc_in_ep == dep->number) && dwc->ep0_schedule_indicator) { ++ dwc->isoc_in_ep_stopxfer = 0; ++ dwc->ep0_schedule_indicator = false; ++ if (dwc->ep0_scheduled) { ++ // now isoc IN ep was stopped, wake up ep0 thread ++ complete(&dwc->ep0_comp); ++ } ++ } ++#endif ++ dep->queued_requests--; + goto out1; + } +- dev_err(dwc->dev, "request %pK was not queued to %s\n", +- request, ep->name); ++ //printk(KERN_DEBUG"request %pK was not queued to %s\n", ++ // request, ep->name); + ret = -EINVAL; + goto out0; + } +@@ -1280,9 +1562,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) + unsigned transfer_in_flight; + unsigned started; + +- if (dep->flags & DWC3_EP_STALL) +- return 0; +- + if (dep->number > 1) + trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); + else +@@ -1307,8 +1586,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) + else + dep->flags |= DWC3_EP_STALL; + } else { +- if (!(dep->flags & DWC3_EP_STALL)) +- return 0; + + ret = dwc3_send_clear_stall_ep_cmd(dep); + if (ret) +@@ -1574,6 +1851,10 @@ static void dwc3_gadget_enable_irq(struct dwc3 *dwc) + DWC3_DEVTEN_USBRSTEN | + DWC3_DEVTEN_DISCONNEVTEN); + ++ /* Enable hibernation IRQ */ ++ if (dwc->has_hibernation) ++ reg |= DWC3_DEVTEN_HIBERNATIONREQEVTEN; ++ + dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); + } + +@@ -1676,6 +1957,17 @@ static int __dwc3_gadget_start(struct dwc3 *dwc) + } + dwc3_writel(dwc->regs, DWC3_DCFG, reg); + ++ /* ++ * Use IMOD if enabled via dwc->imod_interval. Otherwise, if ++ * the core supports IMOD, disable it. ++ */ ++ if (dwc->imod_interval) { ++ dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), DWC3_DEV_IMODI(dwc->imod_interval)); ++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); ++ } else { ++ dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); ++ } ++ + /* + * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP + * field instead of letting dwc3 itself calculate that automatically. +@@ -1710,6 +2002,7 @@ static int __dwc3_gadget_start(struct dwc3 *dwc) + + /* begin to receive SETUP packets */ + dwc->ep0state = EP0_SETUP_PHASE; ++ dwc->link_state = DWC3_LINK_STATE_SS_DIS; + dwc3_ep0_out_start(dwc); + + dwc3_gadget_enable_irq(dwc); +@@ -1732,6 +2025,13 @@ static int dwc3_gadget_start(struct usb_gadget *g, + int irq; + + irq = dwc->irq_gadget; ++#ifdef DWC3_IRQ_THREAD_HP ++ dwc->irq_thread_hp = 0; ++#ifdef CONFIG_SMP ++ if (cpu_online(1)) ++ irq_set_affinity_hint(irq, cpumask_of(1)); ++#endif ++#endif + ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, + IRQF_SHARED, "dwc3", dwc->ev_buf); + if (ret) { +@@ -1786,11 +2086,98 @@ static int dwc3_gadget_stop(struct usb_gadget *g) + dwc->gadget_driver = NULL; + spin_unlock_irqrestore(&dwc->lock, flags); + +- free_irq(dwc->irq_gadget, dwc->ev_buf); ++#ifdef DWC3_IRQ_THREAD_HP ++ if (dwc->irq_thread_hp) ++ dwc->irq_thread_hp = 0; + ++#ifdef CONFIG_SMP ++ irq_set_affinity_hint(dwc->irq_gadget, NULL); ++#endif ++#endif ++ free_irq(dwc->irq_gadget, dwc->ev_buf); + return 0; + } + ++struct usb_ep* ++dwc3_gadget_match_ep(struct usb_gadget *g, ++ struct usb_endpoint_descriptor *desc, ++ struct usb_ss_ep_comp_descriptor *ep_comp) ++{ ++ struct dwc3 *dwc = gadget_to_dwc(g); ++ struct dwc3_ep *dep = NULL; ++ static bool ep_occupied[8] = {}; ++ int maxpacket = usb_endpoint_maxp(desc); ++ int dir_in = usb_endpoint_dir_in(desc); ++ ++ if (!maxpacket) ++ { ++ switch (usb_endpoint_type(desc)) ++ { ++ case USB_ENDPOINT_XFER_ISOC: ++ case USB_ENDPOINT_XFER_BULK: ++ maxpacket = 1024; ++ break; ++ default: ++ break; ++ } ++ } ++ ++ if (maxpacket <= 64)//ep4-7 ++ { ++ int i; ++ for (i = 4;i < 8;i++) ++ { ++ if (!ep_occupied[i]) ++ { ++ if (dir_in) ++ dep = dwc->eps[2*i+1]; ++ else ++ dep = dwc->eps[2*i]; ++ ++ ep_occupied[i] = true; ++ break; ++ } ++ } ++ } ++ ++ if (!dep && maxpacket <= 192 && !ep_occupied[3])//ep3 ++ { ++ if (dir_in) ++ dep = dwc->eps[7]; ++ else ++ dep = dwc->eps[6]; ++ ++ ep_occupied[3] = true; ++ } ++ ++ if (!dep && maxpacket >= 192)//ep1-2 ++ { ++ int i; ++ for (i=1; i< 3;i++) ++ { ++ if (!ep_occupied[i]) ++ { ++ if (dir_in) ++ dep = dwc->eps[2*i+1]; ++ else ++ dep = dwc->eps[2*i]; ++ ++ ep_occupied[i] = true; ++ break; ++ } ++ } ++ } ++ if (dep && usb_endpoint_type(desc)==USB_ENDPOINT_XFER_BULK && maxpacket < 512) ++ { ++ if (assume_high_speed) ++ { ++ g->max_speed = USB_SPEED_HIGH; ++ } ++ } ++ return dep?&dep->endpoint:NULL; ++} ++EXPORT_SYMBOL(dwc3_gadget_match_ep); ++ + static const struct usb_gadget_ops dwc3_gadget_ops = { + .get_frame = dwc3_gadget_get_frame, + .wakeup = dwc3_gadget_wakeup, +@@ -1798,6 +2185,7 @@ static const struct usb_gadget_ops dwc3_gadget_ops = { + .pullup = dwc3_gadget_pullup, + .udc_start = dwc3_gadget_start, + .udc_stop = dwc3_gadget_stop, ++ .match_ep = dwc3_gadget_match_ep, + }; + + /* -------------------------------------------------------------------------- */ +@@ -1828,7 +2216,7 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, + spin_lock_init(&dep->lock); + + dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); +- ++#if 0 + if (epnum == 0 || epnum == 1) { + usb_ep_set_maxpacket_limit(&dep->endpoint, 512); + dep->endpoint.maxburst = 1; +@@ -1848,7 +2236,51 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, + if (ret) + return ret; + } ++#else ++ if (epnum == 0 || epnum == 1) { ++ usb_ep_set_maxpacket_limit(&dep->endpoint, 512); ++ dep->endpoint.maxburst = 1; ++ dep->endpoint.ops = &dwc3_gadget_ep0_ops; ++ if (!epnum) ++ dwc->gadget.ep0 = &dep->endpoint; ++ } else if (epnum == 2 || epnum == 3 || epnum == 4 || epnum == 5) { ++ int ret; ++ ++ usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); ++ dep->endpoint.max_streams = 15; ++ dep->endpoint.ops = &dwc3_gadget_ep_ops; ++ list_add_tail(&dep->endpoint.ep_list, ++ &dwc->gadget.ep_list); ++ ++ ret = dwc3_alloc_trb_pool(dep); ++ if (ret) ++ return ret; ++ } else if (epnum == 6||epnum == 7) { ++ int ret; ++ ++ usb_ep_set_maxpacket_limit(&dep->endpoint, 192); ++ dep->endpoint.max_streams = 1; ++ dep->endpoint.ops = &dwc3_gadget_ep_ops; ++ list_add_tail(&dep->endpoint.ep_list, ++ &dwc->gadget.ep_list); ++ ++ ret = dwc3_alloc_trb_pool(dep); ++ if (ret) ++ return ret; ++ } else { ++ int ret; ++ ++ usb_ep_set_maxpacket_limit(&dep->endpoint, 64); ++ dep->endpoint.max_streams = 1; ++ dep->endpoint.ops = &dwc3_gadget_ep_ops; ++ list_add_tail(&dep->endpoint.ep_list, ++ &dwc->gadget.ep_list); + ++ ret = dwc3_alloc_trb_pool(dep); ++ if (ret) ++ return ret; ++ } ++#endif + if (epnum == 0 || epnum == 1) { + dep->endpoint.caps.type_control = true; + } else { +@@ -1977,10 +2409,9 @@ static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, + * request in the pending_list. + */ + dep->flags |= DWC3_EP_MISSED_ISOC; ++ printk(KERN_DEBUG"\t*M%d*", dep->number); + } else { +- dev_err(dwc->dev, "incomplete IN transfer %s\n", +- dep->name); +- status = -ECONNRESET; ++ printk(KERN_DEBUG"%s incomplete IN %x", dep->name, count); + } + } else { + dep->flags &= ~DWC3_EP_MISSED_ISOC; +@@ -2051,6 +2482,15 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, + if (ret && chain && (actual < length) && req->num_pending_sgs) + return __dwc3_gadget_kick_transfer(dep, 0); + ++ /* ++ * In facing of MISSED_ISOC flag, data might lost in transmission. ++ * We now has no way to do re-transmission but just inform gadget that phenomenon ++ */ ++ if (dep->flags & DWC3_EP_MISSED_ISOC) { ++ dep->flags &= ~(DWC3_EP_MISSED_ISOC); ++ status = -ENOSR; ++ } ++ + dwc3_gadget_giveback(dep, req, status); + + if (ret) { +@@ -2079,9 +2519,32 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, + * entry is added into request list. + */ + dep->flags = DWC3_EP_PENDING_REQUEST; ++ dep->pending_requests = 0; ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep == dep->number) { ++ dwc->ep0_schedule_indicator = false; ++ if (dwc->ep0_scheduled) { ++ complete(&dwc->ep0_comp); ++ } ++ } ++#endif + } else { ++#ifdef DWC3_EP0_SCHEDULING ++ if (dwc->isoc_in_ep == dep->number) { ++ if (dwc->isoc_in_ep_stopxfer != dep->number) { ++ dwc->isoc_in_ep_stopxfer = dep->number; ++ dwc->ep0_schedule_indicator = true; ++ complete(&dwc->ep0_comp); ++ } ++ } ++ else { ++ dwc3_stop_active_transfer(dwc, dep->number, true); ++ dep->flags = DWC3_EP_ENABLED; ++ } ++#else + dwc3_stop_active_transfer(dwc, dep->number, true); + dep->flags = DWC3_EP_ENABLED; ++#endif + } + return 1; + } +@@ -2142,7 +2605,13 @@ static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, + if (!dep->endpoint.desc) + return; + +- if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { ++#ifdef DWC3_EP0_SCHEDULING ++ if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) || ++ (!clean_busy && (dep->interval != 1) && (dep->number != dwc->isoc_in_ep))) ++#else ++ if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) || (!clean_busy && (dep->interval != 1))) ++#endif ++ { + int ret; + + ret = __dwc3_gadget_kick_transfer(dep, 0); +@@ -2182,10 +2651,30 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc, + break; + case DWC3_DEPEVT_XFERINPROGRESS: + dwc3_endpoint_transfer_complete(dwc, dep, event); ++#ifdef DWC3_EP0_SCHEDULING ++ if (dep->number == dwc->isoc_in_ep) { ++#ifdef DWC3_ISOC_MONITOR ++ dwc->isoc_in_ep_activated = true; ++#endif ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "#P%d", dep->pending_requests); ++#endif ++ } ++#endif + break; + case DWC3_DEPEVT_XFERNOTREADY: + if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { + dwc3_gadget_start_isoc(dwc, dep, event); ++#ifdef DWC3_EP0_SCHEDULING ++ if (dep->number == dwc->isoc_in_ep) { ++#ifdef DWC3_ISOC_MONITOR ++ dwc->isoc_in_ep_activated = true; ++#endif ++#ifdef DWC3_TRACE_EP0 ++ printk(KERN_DEBUG "=N%d", dep->queued_requests); ++#endif ++ } ++#endif + } else { + int active; + int ret; +@@ -2247,6 +2736,14 @@ static void dwc3_disconnect_gadget(struct dwc3 *dwc) + + static void dwc3_suspend_gadget(struct dwc3 *dwc) + { ++ if (dwc->is_hibernated) { ++ /* ++ * As we are about to suspend, wake the controller from ++ * D3 & hibernation states ++ */ ++ printk("Suspend\n"); ++ } ++ + if (dwc->gadget_driver && dwc->gadget_driver->suspend) { + spin_unlock(&dwc->lock); + dwc->gadget_driver->suspend(&dwc->gadget); +@@ -2274,8 +2771,11 @@ static void dwc3_reset_gadget(struct dwc3 *dwc) + spin_lock(&dwc->lock); + } + } +- ++#ifdef DWC3_EP0_SCHEDULING ++void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) ++#else + static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) ++#endif + { + struct dwc3_ep *dep; + struct dwc3_gadget_ep_cmd_params params; +@@ -2325,7 +2825,13 @@ static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) + memset(¶ms, 0, sizeof(params)); + ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); + WARN_ON_ONCE(ret); +- dep->resource_index = 0; ++ /* ++ * For isoc ep, the resource index will be kept. ++ * If next time Start Transfer failed due to the future u-frame time has passed, ++ * software can issue End Transfer for another XferNotReady event to attempt Start Transfer again. ++ */ ++ if (dep->endpoint.desc && !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ++ dep->resource_index = 0; + dep->flags &= ~DWC3_EP_BUSY; + + if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) +@@ -2510,6 +3016,12 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) + dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); + dwc->gadget.ep0->maxpacket = 512; + dwc->gadget.speed = USB_SPEED_SUPER; ++ /* ++ * for self-power case, start udc before plug-in cable might ++ * pop an additional unknown 2.0 device while device connected at super speed. ++ * to avoid this issue, reset utmi in connecting with super speed. ++ */ ++ phy_utmi_reset(); + break; + case DWC3_DSTS_HIGHSPEED: + dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); +@@ -2528,6 +3040,8 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) + break; + } + ++ dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket; ++ + /* Enable USB2 LPM Capability */ + + if ((dwc->revision > DWC3_REVISION_194A) && +@@ -2682,6 +3196,9 @@ static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, + } + + switch (next) { ++ case DWC3_LINK_STATE_U0: ++ //printk("U0\n"); ++ break; + case DWC3_LINK_STATE_U1: + if (dwc->speed == USB_SPEED_SUPER) + dwc3_suspend_gadget(dwc); +@@ -2693,6 +3210,17 @@ static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, + case DWC3_LINK_STATE_RESUME: + dwc3_resume_gadget(dwc); + break; ++ case DWC3_LINK_STATE_RX_DET: ++ printk("RxDET\n"); ++ break; ++ case DWC3_LINK_STATE_SS_INACT: ++ phy_reset(dwc->usb3_generic_phy); ++ printk("SS INACT\n"); ++ break; ++ case DWC3_LINK_STATE_SS_DIS: ++ phy_reset(dwc->usb3_generic_phy); ++ printk("SS DIS\n"); ++ break; + default: + /* do nothing */ + break; +@@ -2712,10 +3240,719 @@ static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, + dwc->link_state = next; + } + ++static void dwc3_gadget_flush_fifo(struct dwc3 *dwc, ++ u32 fifo_sel) ++{ ++ u32 param; ++ int ret; ++ ++ param = fifo_sel; ++ ++ ret = dwc3_send_gadget_generic_command(dwc, ++ DWC3_DGCMD_SELECTED_FIFO_FLUSH, param); ++} ++ ++static int dwc3_gadget_save_regs(struct dwc3 *dwc) ++{ ++ int i; ++ ++ if (!dwc->saved_regs) { ++ dwc->saved_regs = devm_kmalloc(dwc->dev, ++ sizeof(save_reg_addr), ++ GFP_KERNEL); ++ ++ if (!dwc->saved_regs) { ++ dev_err(dwc->dev, "Not enough memory to save regs\n"); ++ return -ENOMEM; ++ } ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(save_reg_addr); i++) { ++ dwc->saved_regs[i] = dwc3_readl(dwc->regs, save_reg_addr[i]); ++ } ++ return 0; ++} ++ ++static void dwc3_gadget_restore_regs(struct dwc3 *dwc) ++{ ++ int i; ++ ++ if (!dwc->saved_regs) { ++ dev_warn(dwc->dev, "Regs not saved\n"); ++ return; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(save_reg_addr); i++) ++ dwc3_writel(dwc->regs, save_reg_addr[i], dwc->saved_regs[i]); ++ ++} ++ ++static int dwc3_gadget_restore_eps(struct dwc3 *dwc) ++{ ++ int epnum, ret; ++ dma_addr_t miu_addr; ++ ++ for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { ++ /* Enable the endpoint */ ++ struct dwc3_ep *dep = dwc->eps[epnum]; ++ ++ if (!dep) ++ continue; ++ ++ if (!(dep->flags & DWC3_EP_ENABLED)) ++ continue; ++ ++ ret = __dwc3_gadget_ep_enable(dep, dep->endpoint.desc, dep->endpoint.comp_desc, false, ++ true); ++ if (ret) { ++ dev_err(dwc->dev, "failed to enable %s\n", dep->name); ++ return ret; ++ } ++ } ++ ++ for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { ++ struct dwc3_ep *dep = dwc->eps[epnum]; ++ ++ if (!dep) ++ continue; ++ ++ if (!(dep->flags & DWC3_EP_ENABLED)) ++ continue; ++ ++ if (dep->flags & DWC3_EP_STALL) { ++ /* Set stall for the endpoint */ ++ struct dwc3_gadget_ep_cmd_params params; ++ ++ memset(¶ms, 0x00, sizeof(params)); ++ ++ ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, ++ ¶ms); ++ if (ret) { ++ dev_err(dwc->dev, "failed to set STALL on %s\n", ++ dep->name); ++ return ret; ++ } ++ } else { ++ u32 cmd; ++ struct dwc3_gadget_ep_cmd_params params; ++ struct dwc3_trb *trb; ++ u8 trb_dequeue = dep->trb_dequeue; ++ ++ trb = &dep->trb_pool[trb_dequeue]; ++ ++ /* ++ * check the last processed TRBSTS field has value ++ * 4 (TRBInProgress), if yes resubmit the same TRB ++ */ ++ if (DWC3_TRB_SIZE_TRBSTS(trb->size) == ++ DWC3_TRB_STS_XFER_IN_PROG) { ++ /* Set the HWO bit */ ++ trb->ctrl |= DWC3_TRB_CTRL_HWO; ++ ++ /* Clear the TRBSTS field */ ++ trb->size &= ~(0x0F << 28); ++ ++ memset(¶ms, 0, sizeof(params)); ++ ++ /* Issue starttransfer */ ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(dwc3_trb_dma_offset(dep, trb)); ++ params.param0 = ++ upper_32_bits(miu_addr); ++ params.param1 = ++ lower_32_bits(miu_addr); ++ ++ cmd = DWC3_DEPCMD_STARTTRANSFER | ++ DWC3_DEPCMD_PARAM(0); ++ ++ dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); ++ ++ dwc3_gadget_ep_get_transfer_index(dep); ++ } else { ++ ret = __dwc3_gadget_kick_transfer(dep, 0); ++ if (ret) { ++ dev_err(dwc->dev, ++ "%s: restart transfer failed\n", ++ dep->name); ++ return ret; ++ } ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int dwc3_gadget_restart_ep0_trans(struct dwc3 *dwc, int epnum) ++{ ++ struct dwc3_ep *dep = dwc->eps[epnum]; ++ struct dwc3_trb *trb = dwc->ep0_trb; ++ struct dwc3_gadget_ep_cmd_params params; ++ dma_addr_t miu_addr; ++ int ret; ++ u32 cmd; ++ ++ memset(¶ms, 0, sizeof(params)); ++ miu_addr = (dma_addr_t)Chip_Phys_to_MIU(dwc->ep0_trb_addr); ++ params.param0 = upper_32_bits(miu_addr); ++ params.param1 = lower_32_bits(miu_addr); ++ ++ /* set HWO bit back to 1 and restart transfer */ ++ trb->ctrl |= DWC3_TRB_CTRL_HWO; ++ ++ /* Clear the TRBSTS feild */ ++ trb->size &= ~(0x0F << 28); ++ ++ cmd = DWC3_DEPCMD_STARTTRANSFER | DWC3_DEPCMD_PARAM(0); ++ ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); ++ if (ret < 0) { ++ dev_err(dwc->dev, "failed to restart transfer on %s\n", ++ dep->name); ++ return ret; ++ } ++ ++ dwc3_gadget_ep_get_transfer_index(dep); ++ ++ return 0; ++} ++ ++ ++static int dwc3_gadget_restore_ep0(struct dwc3 *dwc) ++{ ++ int epnum, ret; ++ ++ for (epnum = 0; epnum < 2; epnum++) { ++ struct dwc3_ep *dep = dwc->eps[epnum]; ++ ++ if (!dep) ++ continue; ++ ++ if (!(dep->flags & DWC3_EP_ENABLED)) ++ continue; ++ ++ ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, ++ true); ++ if (ret) { ++ dev_err(dwc->dev, "failed to enable %s L:%d\n", dep->name, __LINE__); ++ return ret; ++ } ++ ++ if (dep->flags & DWC3_EP_STALL) { ++ struct dwc3_gadget_ep_cmd_params params; ++ ++ memset(¶ms, 0x00, sizeof(params)); ++ ++ ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, ++ ¶ms); ++ if (ret) { ++ dev_err(dwc->dev, "failed to set STALL on %s\n", ++ dep->name); ++ return ret; ++ } ++ } else { ++ if (!dep->resource_index && epnum) ++ continue; ++ ++ ret = dwc3_gadget_restart_ep0_trans(dwc, epnum); ++ if (ret) { ++ dev_err(dwc->dev, ++ "failed to restart transfer on: %s\n", ++ dep->name); ++ return ret; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++ ++static int dwc3_setup_scratch_buffers_hiber(struct dwc3 *dwc) ++{ ++ u32 param; ++ int ret; ++ dma_addr_t miu_addr; ++ ++ if (!dwc->is_hibernated) ++ return 0; ++ ++ if (!dwc->nr_scratch) ++ return 0; ++ printk("Hibernation ? %d, scratch buf:%x\n", dwc->has_hibernation, (u32)dwc->scratchpad[0]); ++ ++ ++ #if (0) ++ { ++ u32 i = 0; ++ u32 *ptr = (u32 *)(dwc->scratchpad_array); ++ ++ printk("\n[%s]scratchbuf:%p scratchpad_array_dma:x%x sz:%d\n", __FUNCTION__, dwc->scratchpad[0], dwc->scratchpad_array_dma, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE); ++ printk("x%p:x%8x x%8x x%8x x%8x[WARNING]BF\n\n", ptr, ptr[0], ptr[1], ptr[2], ptr[3]); ++ ptr = (dwc->scratchpad[0]); ++ for (i = 0; iscratchpad_array_dma); ++ param = lower_32_bits(miu_addr); ++ printk("Scratch buffer num:%d, addr:%x, size:%d\n", dwc->nr_scratch, dwc->scratchpad_array_dma, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE); ++ ++ ret = dwc3_send_gadget_generic_command(dwc, ++ DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); ++ if (ret < 0) ++ goto err1; ++ ++ param = upper_32_bits(miu_addr); ++ ++ ret = dwc3_send_gadget_generic_command(dwc, ++ DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); ++ if (ret < 0) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ dma_unmap_single(dwc->dev, ++ dwc->scratchpad_array_dma, ++ dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, ++ DMA_BIDIRECTIONAL); ++ ++ return ret; ++} ++ ++void dwc3_gadget_power_setting_at_suspend(struct dwc3 *dwc) ++{ ++ u32 tmp; ++ ++ printk(KERN_INFO "disabled USB pwr setting!\n"); ++ ++ //Bank: 0x1524 offset: 0x20 bit[0]=1'b1 //pd_txpll ++ //Bank: 0x1524 offset: 0x30 bit[0]=1'b1 //pd_rxpll ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x20<<2))|BIT(0); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x20<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x30<<2))|BIT(0); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x30<<2), tmp); ++ ++ //TXPLL SYN_IN/XTAL_IN OFF ... ++ //Bank: 0x1524 offset: 0x10 bit[15:0]=16'h0030 //reg_sata_test[15:0] ++ //Bank: 0x1524 offset: 0x11 bit[15:0]=16'h0005 //reg_sata_test[31:16],TXPLL SYN_IN/XTAL_IN OFF ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x10<<2), 0x0030); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x11<<2), 0x0005); ++ ++ // disable AFE ++ //Bank: 0x1523 offset: 0x0d bit[14]=1'b1 //force_afe_pwd ++ //Bank: 0x1523 offset: 0x3c bit[0]=1'b1 //ssusb_afe_pwd ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x0D<<2))|BIT(14); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x0D<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x3C<<2))|BIT(0); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x3C<<2), tmp); ++ ++ // disable Bandgap ++ //Bank: 0x1523 offset: 0x51 bit[15]=1'b0 //ssusb_bgr_en=1'b0 ++ //Bank: 0x1523 offset: 0x08 bit[1:0]=2'b11 //force biasimr_pwd, bias_pwd ++ //Bank: 0x1523 offset: 0x00 bit[1:0]=2'b11 //set biasimr_pwd=1'b1, bias_pwd=1'b1 ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x51<<2))& ~(BIT(15)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x51<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x08<<2))|(BIT(1)|BIT(0)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x08<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x00<<2))|(BIT(1)|BIT(0)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x00<<2), tmp); ++ ++ //wriu 0x142108 0x80 bit[2] reg_xtal_enable ++ //wriu 0x142109 0x00 ++ OUTREG16(0x1F000000+(0x1421<<9)+(0x04<<2), 0x0080); ++ ++ //wriu 0x142100 0x05 bit[2]=1 Power down XCVR reference block ++ //wriu 0x142101 0xFE(x7D) ++ //[4] reg_fl_xcvr_pdn => set to 0 for suspend mode ++ //[0]=1 Power down de-serializer block ++ //[8:2]=1 Power down HS TED block/HS pre-amplifier block/FS&LS transceiver block/USB_XCVR VBUS detector block/HS current reference block/built-in regulator block ++ OUTREG16(0x1F000000+(0x1421<<9)+(0x00<<2), 0x7D05); ++ ++ return; ++} ++ ++void dwc3_gadget_power_setting_at_wakeup(struct dwc3 *dwc) ++{ ++ u32 tmp; ++ ++ printk(KERN_INFO "enabled USB pwr setting!\n"); ++ ++ //Bank: 0x1524 offset: 0x20 bit[0]=1'b0 // pd_txpll ++ //Bank: 0x1524 offset: 0x30 bit[0]=1'b0 // pd_rxpll ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x20<<2))&~(BIT(0)); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x20<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x30<<2))&~(BIT(0)); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x30<<2), tmp); ++ ++ //TXPLL SYN_IN/XTAL_IN OFF ... ++ //Bank: 0x1524 offset: 0x10 bit[15:0]=16'h0000 //reg_sata_test[15:0] ++ //Bank: 0x1524 offset: 0x11 bit[15:0]=16'h0000 //reg_sata_test[31:16],TXPLL SYN_IN/XTAL_IN OFF ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x10<<2), 0x0000); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x11<<2), 0x0000); ++ ++ // disable AFE ++ //Bank: 0x1523 offset: 0x0d bit[14]=1'b0 //force_afe_pwd ++ //Bank: 0x1523 offset: 0x3c bit[0]=1'b1 //ssusb_afe_pwd ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x0D<<2))&~(BIT(14)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x0D<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x3C<<2))|(BIT(0)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x3C<<2), tmp); ++ ++ // disable Bandgap ++ //Bank: 0x1523 offset: 0x51 bit[15]=1'b0 //ssusb_bgr_en=1'b0 ++ //Bank: 0x1523 offset: 0x08 bit[1:0]=2'b00 //force biasimr_pwd, bias_pwd ++ //Bank: 0x1523 offset: 0x00 bit[1:0]=2'b11 //set biasimr_pwd=1'b1, bias_pwd=1'b1 ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x51<<2))& ~(BIT(15)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x51<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x08<<2))& ~(BIT(1)|BIT(0)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x08<<2), tmp); ++ tmp = INREG16(0x1F000000+(0x1523<<9)+(0x00<<2))|(BIT(1)|BIT(0)); ++ OUTREG16(0x1F000000+(0x1523<<9)+(0x00<<2), tmp); ++ ++ //wriu 0x142108 0x2F ++ //[2] reg_xtal_enable ++ //wriu 0x142109 0x8D ++ OUTREG16(0x1F000000+(0x1421<<9)+(0x04<<2), 0x8D2F); ++ ++ //wriu 0x142100 0x01 ++ //[2]=1 => Power down XCVR reference block ++ //wriu 0x142101 0x00 ++ //[4] reg_fl_xcvr_pdn => set to 0 for suspend mode ++ //[0]=1 => Power down de-serializer block ++ //[2]-[8] =1 => Power down HS TED block/HS pre-amplifier block/FS&LS transceiver block/USB_XCVR VBUS detector block/HS current reference block/built-in regulator block ++ OUTREG16(0x1F000000+(0x1421<<9)+(0x00<<2), 0x0001); ++ ++ return; ++} ++ ++void dwc3_gadget_exit_hibernation(struct dwc3 *dwc) ++{ ++ ++ u32 tmp; ++ u32 link_state; ++ int ret; ++ int retries; ++ int power_good_timeout = 100000; //10ms ++ ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x28<<2)); //usb3_phya0:x1524_x28 ++ if((tmp&0x01)) ++ { ++ u16 lreg_enter_u3_mode = INREG16(0x1F000000+(0x1524<<9)+(0x28<<2)) & ~(0x01); ++ u16 u3_symb = INREG16(0x1F000000+(0x1524<<9)+(0x2F<<2)); ++ ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x28<<2), lreg_enter_u3_mode); ++ dwc3_gadget_power_setting_at_wakeup(dwc); ++ printk("[LeaveIso]x1524_x28[B0]=x%x;_x2F=x%x\n", lreg_enter_u3_mode, u3_symb); ++ OUTREG16(0x1F000000+(0x1524<<9)+(0x2F<<2), 0x2018); ++ do { ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x48<<2)); ++ udelay(10); ++ } while(!(tmp & BIT(12)) && (--power_good_timeout)); ++ ++ if (!power_good_timeout) { ++ printk("[Warning]u3->pme_generation_u3pmu:x%x TMO\n", tmp); ++ } ++ CLRREG16(0x1F000000+(0x1524<<9)+(0x48<<2), 0x303); ++ } ++ do { ++ tmp = INREG16(0x1F000000+(0x1524<<9)+(0x48<<2)); ++ udelay(10); ++ } while((tmp & 0x0C0C) && (--power_good_timeout)); ++ if (!power_good_timeout) { ++ printk("failed to pwr_good(x%x) TMO(>10ms)\n", tmp); ++ } ++ //6.2.4 Exiting Hibernation in Device Mode While Connected ++ dwc3_core_init(dwc); ++ CLRREG16(0x1F000000+(0x1433<<9)+(0x21<<2), 0x0002); //INT enable. ++ //(3)If the power on initialization values of the GSBUSCFG0 and GSBUSCFG1 registers (DWC_USB3_GSBUSCFG0_INT and ++ // DWC_USB3_GSBUSCFG1) are not the same as the normal system operating value, ++ // then re-program these registers with the characteristics of the system bus. ++ dwc3_gadget_restore_regs(dwc); ++ ++ //(4)Issue a Set Scratchpad Buffer Array device generic command and ++ // wait for completion by polling the DGCMD.CmdAct bit. ++ ret = dwc3_setup_scratch_buffers_hiber(dwc); ++ if (ret) { ++ dev_err(dwc->dev, "Failed to setup scratch buffers: %d\n", ret); ++ goto err; ++ } ++ ++ //(5)Write 1 to DCTL.CRS to star the restore process and ++ // wait for completion by polling the DSTS.RSS bit. ++ ++ /* ask controller to save the non-sticky registers */ ++ tmp = dwc3_readl(dwc->regs, DWC3_DCTL); ++ tmp |= DWC3_DCTL_CRS; ++ dwc3_writel(dwc->regs, DWC3_DCTL, tmp); ++ ++ tmp = dwc3_readl(dwc->regs, DWC3_DCTL); ++ printk("Start resotre:%x\n", tmp); ++ ++ /* Wait till non-sticky registers are restored */ ++ retries = 500; ++ do { ++ tmp = dwc3_readl(dwc->regs, DWC3_DSTS); ++ if (!(tmp & DWC3_DSTS_RSS)) ++ break; ++ ++ udelay(100); ++ } while (--retries); ++ if (retries < 0) { ++ dev_err(dwc->dev, "failed to non-sticky TMO\n"); ++ } ++ ++ /* restore ep0 endpoints */ ++ ret = dwc3_gadget_restore_ep0(dwc); ++ if (ret) { ++ dev_err(dwc->dev, "Failed in restorig EP0 states\n"); ++ goto err; ++ } ++ ++ //(7)Set DCTL.RunStop=1 and DCTL.KeepConnect=1 ++ // (while keeping other DCTL bits intact, that is, do a read-modify-write). ++ ++ /* start the controller */ ++ ret = dwc3_gadget_run_stop(dwc, true, false); ++ if (ret < 0) { ++ dev_err(dwc->dev, "USB core failed to start on wakeup\n"); ++ goto err; ++ } ++ ++ //(8)Poll the DSTS register until DSTS.DCNRdy is 0. ++ // Read the DSTS.USBLnkSt field to see the current link state. ++ ++ /* Wait until device controller is ready */ ++ retries = 20000; ++ while (--retries) { ++ tmp = dwc3_readl(dwc->regs, DWC3_DSTS); ++ if (tmp & DWC3_DSTS_DCNRD) ++ udelay(5); ++ else ++ break; ++ } ++ ++ if (retries < 0) { ++ dev_err(dwc->dev, "USB core failed to restore controller\n"); ++ goto err; ++ } ++ ++ link_state = dwc3_gadget_get_link_state(dwc); ++ ++ /* check if the link state is in a valid state */ ++ switch (link_state) { ++ case DWC3_LINK_STATE_RESET: ++ /* Reset devaddr */ ++ tmp = dwc3_readl(dwc->regs, DWC3_DCFG); ++ tmp &= ~(DWC3_DCFG_DEVADDR_MASK); ++ dwc3_writel(dwc->regs, DWC3_DCFG, tmp); ++ ++ /* issue recovery on the link */ ++ ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); ++ if (ret < 0) { ++ dev_err(dwc->dev, ++ "Failed to set link state to Recovery\n"); ++ goto err; ++ } ++ ++ break; ++ ++ case DWC3_LINK_STATE_SS_DIS: ++ /* Clear keep connect from reconnecting to HOST */ ++ tmp = dwc3_readl(dwc->regs, DWC3_DCTL); ++ tmp &= ~DWC3_DCTL_KEEP_CONNECT; ++ dwc3_writel(dwc->regs, DWC3_DCTL, tmp); ++ /* fall through */ ++ case DWC3_LINK_STATE_U3: ++ /* Ignore wakeup event as the link is still in U3 state */ ++ dev_dbg(dwc->dev, "False wakeup event %d\n", link_state); ++ ++ default: ++ /* issue recovery on the link */ ++ ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); ++ if (ret < 0) { ++ dev_err(dwc->dev, ++ "Failed to set link state to Recovery\n"); ++ goto err; ++ } ++ ++ break; ++ } ++ ++ if (link_state != DWC3_LINK_STATE_SS_DIS) { ++ /* Restore non EP0 EPs */ ++ ret = dwc3_gadget_restore_eps(dwc); ++ if (ret) { ++ dev_err(dwc->dev, "Failed restoring non-EP0 states\n"); ++ goto err; ++ } ++ } ++ ++ /* clear the flag */ ++ dwc->is_hibernated = false; ++ ++ ++ return; ++err: ++ printk("Resotre fail:%x\n", tmp); ++} ++ ++static void dwc3_gadget_enter_hibernation(struct dwc3 *dwc, ++ unsigned int evtinfo) ++{ ++ u32 epnum; ++ u32 tmp; ++ int i; ++ int retries; ++ ++ /* Check if the link state is valid before hibernating */ ++ switch (dwc3_gadget_get_link_state(dwc)) { ++ case DWC3_LINK_STATE_U3: ++ case DWC3_LINK_STATE_SS_DIS: ++ printk("Enter hibernation, link state:%d\n", dwc3_gadget_get_link_state(dwc)); ++ break; ++ default: ++ dev_dbg(dwc->dev, ++ "%s: Got fake hiber event\n", __func__); ++ return; ++ } ++ ++ tmp = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); ++ tmp |= DWC3_GUSB3PIPECTL_SUSPHY; ++ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), tmp); ++ ++ ++ /* ++ * 6.2.2 Entering Hibernation in Device Mode While Connected ++ * ++ * 3. ++ * Issue an "End Transfer" command for all active transfers with the ++ * ForceRM field set to 0, including the default control endpoint 0. ++ * ++ * 4. ++ * After that, issue a "Get Endpoint State" endpoint command for each active ++ * endpoint, and save the bits that are returned for use after ++ * coming out of hibernation. ++ * ++ * In addition, software must remember if the endpoint is ++ * currently in a Halted state. The endpoint is in a Halted ++ * state if software has issued a "Set STALL" command and has ++ * not issued a "Clear STALL" command. ++ */ ++ ++ for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { ++ struct dwc3_ep *dep; ++ ++ dep = dwc->eps[epnum]; ++ if (!dep) ++ continue; ++ ++ if (!(dep->flags & DWC3_EP_ENABLED)) ++ continue; ++ ++ if (dep->flags & DWC3_EP_TRANSFER_STARTED) ++ dwc3_stop_active_transfer(dwc, dep->number, false); ++ ++ dwc3_gadget_get_ep_state(dwc, dep); ++ } ++ ++ /* ++ * 5. ++ * Set DCTL.RunStop to 0, DCTL.KeepConnect to 1 (or 0 if disconnected), ++ * and wait for DSTS.Halted to be set to 1. Software must service any ++ * events that are generated while it is waiting for Halted to be set ++ * to 1. ++ */ ++ ++ dwc3_gadget_run_stop(dwc, false, true); ++ dwc->is_hibernated = true; ++ ++ tmp = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); ++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), tmp); ++ dwc->ev_buf->count = 0; ++ dwc->ev_buf->flags &= ~DWC3_EVENT_PENDING; ++ ++ i = 25000; ++ do { ++ tmp = dwc3_readl(dwc->regs, DWC3_DSTS); ++ if(--i == 0) { ++ if(!(tmp & DWC3_DSTS_DEVCTRLHLT)) { ++ dwc3_gadget_flush_fifo(dwc, 0); ++ } ++ } ++ } while (!(tmp & DWC3_DSTS_DEVCTRLHLT)); ++ ++ tmp = dwc3_readl(dwc->regs, DWC3_DCTL); ++ if (dwc3_gadget_get_link_state(dwc) == DWC3_LINK_STATE_SS_DIS) { ++ tmp &= ~DWC3_DCTL_KEEP_CONNECT; ++ dwc3_writel(dwc->regs, DWC3_DCTL, tmp); ++ } else { ++ tmp |= DWC3_DCTL_KEEP_CONNECT; ++ dwc3_writel(dwc->regs, DWC3_DCTL, tmp); ++ } ++ ++ /* ++ * 6. ++ * Save D* and G* registers. ++ * D* registers(DCTL, DCFG, DEVTEN) ++ * G* registers(GSBUSCFG0/1, GCTL, GTXTHRCFG, GRXTHRCFG, GTXFIFOSIZn, GRXFIFOSIZn, ++ * GUSB3PIPECTL0, GUSB2PHYCFG0) ++ */ ++ ++ dwc3_gadget_save_regs(dwc); ++ ++ tmp = dwc3_readl(dwc->regs, DWC3_DCTL); ++ tmp |= DWC3_DCTL_CSS; ++ dwc3_writel(dwc->regs, DWC3_DCTL, tmp); ++ ++ retries = 500; ++ do { ++ tmp = dwc3_readl(dwc->regs, DWC3_DSTS); ++ if (!(tmp & DWC3_DSTS_SSS)) ++ break; ++ ++ udelay(100); ++ } while (--retries); ++ ++ if (retries < 0) { ++ dev_err(dwc->dev, "USB core failed to save state\n"); ++ goto err; ++ } ++ ++ #if (0) ++ { ++ u32 i = 0; ++ u32 *ptr =(u32 *)(dwc->scratchpad_array); ++ ++ printk("x%p:x%8x x%8x x%8x x%8x[WARNING]CHK\n\n", ptr, ptr[0], ptr[1], ptr[2], ptr[3]); ++ ptr = (dwc->scratchpad[0]); ++ for (i = 0; ispeed == USB_SPEED_SUPER)) +- return; + ++ //if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) ++ // return; ++ ++ dwc3_gadget_enter_hibernation(dwc, evtinfo); + /* enter hibernation here */ + } + +@@ -2744,7 +3983,7 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc, + dwc3_gadget_disconnect_interrupt(dwc); + break; + case DWC3_DEVICE_EVENT_RESET: +- dwc3_gadget_reset_interrupt(dwc); ++ dwc3_gadget_reset_interrupt(dwc); + break; + case DWC3_DEVICE_EVENT_CONNECT_DONE: + dwc3_gadget_conndone_interrupt(dwc); +@@ -2831,7 +4070,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) + while (left > 0) { + union dwc3_event event; + +- event.raw = *(u32 *) (evt->buf + evt->lpos); ++ event.raw = *(u32 *) (evt->cache + evt->lpos); + + dwc3_process_event_entry(dwc, &event); + +@@ -2844,21 +4083,29 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) + * boundary so I worry about that once we try to handle + * that. + */ +- evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; ++ evt->lpos = (evt->lpos + 4) % evt->length; + left -= 4; + +- dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); ++ if (dwc->is_hibernated) ++ break; + } + + evt->count = 0; + evt->flags &= ~DWC3_EVENT_PENDING; + ret = IRQ_HANDLED; + ++ if (dwc->is_hibernated) ++ return ret; ++ + /* Unmask interrupt */ + reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); + reg &= ~DWC3_GEVNTSIZ_INTMASK; + dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); + ++ if (dwc->imod_interval) { ++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); ++ } ++ + return ret; + } + +@@ -2869,6 +4116,15 @@ static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) + unsigned long flags; + irqreturn_t ret = IRQ_NONE; + ++#ifdef DWC3_IRQ_THREAD_HP ++ if (!dwc->irq_thread_hp) { ++ struct sched_param param = { ++ .sched_priority = MAX_USER_RT_PRIO -1, ++ }; ++ dwc->irq_thread_hp = 1; ++ sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m); ++ } ++#endif + spin_lock_irqsave(&dwc->lock, flags); + ret = dwc3_process_event_buf(evt); + spin_unlock_irqrestore(&dwc->lock, flags); +@@ -2879,6 +4135,7 @@ static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) + static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) + { + struct dwc3 *dwc = evt->dwc; ++ u32 amount; + u32 count; + u32 reg; + +@@ -2889,6 +4146,9 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) + return IRQ_HANDLED; + } + ++ if (dwc->is_hibernated) ++ return IRQ_HANDLED; ++ + /* + * With PCIe legacy interrupt, test shows that top-half irq handler can + * be called again after HW interrupt deassertion. Check if bottom-half +@@ -2911,6 +4171,17 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) + reg |= DWC3_GEVNTSIZ_INTMASK; + dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); + ++ amount = min(count, evt->length - evt->lpos); ++ memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); ++ ++ if (amount < count) ++ memcpy(evt->cache, evt->buf, count - amount); ++ ++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); ++ if (dwc->imod_interval) { ++ dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), DWC3_DEV_IMODC(dwc->imod_interval) | DWC3_DEV_IMODI(dwc->imod_interval)); ++ } ++ + return IRQ_WAKE_THREAD; + } + +@@ -2996,7 +4267,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) + + dwc->gadget.ops = &dwc3_gadget_ops; + dwc->gadget.speed = USB_SPEED_UNKNOWN; +- dwc->gadget.sg_supported = true; ++ dwc->gadget.sg_supported = false; + dwc->gadget.name = "dwc3-gadget"; + dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; + +@@ -3038,6 +4309,29 @@ int dwc3_gadget_init(struct dwc3 *dwc) + if (ret) + goto err5; + ++#ifdef DWC3_EP0_SCHEDULING ++ init_completion(&dwc->ep0_comp); ++ dwc->ep0_evt_task = kthread_run(dwc3_ep0_thread, (void *)dwc, "dw3_ep0"); ++ if (IS_ERR(dwc->ep0_evt_task)) { ++ dev_err(dwc->dev, "failed to create ep0 event thread\n"); ++ goto err5; ++ } ++ else { ++ struct sched_param param = { ++ .sched_priority = MAX_USER_RT_PRIO -1, ++ }; ++ sched_setscheduler_nocheck(dwc->ep0_evt_task, SCHED_FIFO, ¶m); ++ } ++#ifdef DWC3_ISOC_MONITOR ++ dwc->isoc_in_wq = create_workqueue("dwc3_isoc_wq"); ++ if (!dwc->isoc_in_wq) { ++ dev_err(dwc->dev, "failed to create dwc3_isoc_wq\n"); ++ goto err5; ++ } ++ INIT_DELAYED_WORK(&dwc->isoc_in_monitor, __dwc3_gadget_check_isoc_activating); ++#endif ++#endif ++ + ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); + if (ret) { + dev_err(dwc->dev, "failed to register udc\n"); +@@ -3073,6 +4367,20 @@ err0: + + void dwc3_gadget_exit(struct dwc3 *dwc) + { ++#ifdef DWC3_EP0_SCHEDULING ++ complete(&dwc->ep0_comp); ++ kthread_stop(dwc->ep0_evt_task); ++#ifdef DWC3_ISOC_MONITOR ++ cancel_delayed_work(&dwc->isoc_in_monitor); ++ flush_workqueue(dwc->isoc_in_wq); ++ destroy_workqueue(dwc->isoc_in_wq); ++ dwc->isoc_in_ep_activated = false; ++#endif ++ dwc->isoc_in_ep = 0; ++ dwc->isoc_in_ep_stopxfer = 0; ++ dwc->ep0_scheduled = false; ++ dwc->ep0_schedule_indicator = false; ++#endif + usb_del_gadget_udc(&dwc->gadget); + + dwc3_gadget_free_endpoints(dwc); +@@ -3092,6 +4400,9 @@ void dwc3_gadget_exit(struct dwc3 *dwc) + + int dwc3_gadget_suspend(struct dwc3 *dwc) + { ++ if (dwc->has_hibernation) ++ return 0; ++ + if (!dwc->gadget_driver) + return 0; + +@@ -3099,6 +4410,8 @@ int dwc3_gadget_suspend(struct dwc3 *dwc) + dwc3_disconnect_gadget(dwc); + __dwc3_gadget_stop(dwc); + ++ synchronize_irq(dwc->irq_gadget); ++ + return 0; + } + +diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h +index 39459b718e98..cce4915253f2 100644 +--- a/drivers/usb/dwc3/gadget.h ++++ b/drivers/usb/dwc3/gadget.h +@@ -78,7 +78,9 @@ static inline void dwc3_gadget_move_started_request(struct dwc3_request *req) + + void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, + int status); +- ++#ifdef DWC3_EP0_SCHEDULING ++int dwc3_ep0_thread(void *arg); ++#endif + void dwc3_ep0_interrupt(struct dwc3 *dwc, + const struct dwc3_event_depevt *event); + void dwc3_ep0_out_start(struct dwc3 *dwc); +@@ -87,6 +89,10 @@ int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value); + int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, + gfp_t gfp_flags); + int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol); ++void dwc3_gadget_power_setting_at_suspend(struct dwc3 *dwc); ++void dwc3_gadget_power_setting_at_wakeup(struct dwc3 *dwc); ++void dwc3_gadget_exit_hibernation(struct dwc3 *dwc); ++ + + /** + * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW +diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h +index a06f9a8fecc7..879cead64649 100644 +--- a/drivers/usb/dwc3/io.h ++++ b/drivers/usb/dwc3/io.h +@@ -23,6 +23,59 @@ + #include "trace.h" + #include "debug.h" + #include "core.h" ++#include "../drivers/sstar/include/ms_platform.h" ++ ++ ++static inline u32 dwc3_to_sigma_rebase(u32 offset, u32 value) ++{ ++ u32 axi_offset = offset >> 8; ++ u32 bank = 0, bank_offset = 0; ++ switch (axi_offset) { ++ case 0xC1: ++ case 0xC2: ++ bank = 0x1A21; ++ axi_offset = 0xC1; ++ break; ++ case 0xC3: ++ case 0xC4: ++ axi_offset = 0xC3; ++ bank = 0x1A22; ++ break; ++ case 0xC6: ++ case 0xC7: ++ axi_offset = 0xC6; ++ bank = 0x1A23; ++ break; ++ case 0xC8: ++ case 0xC9: ++ axi_offset = 0xC8; ++ bank = 0x1A24; ++ break; ++ case 0xCA: ++ case 0xCB: ++ axi_offset = 0xCA; ++ bank = 0x1A25; ++ break; ++ case 0xD0: ++ case 0xD1: ++ axi_offset = 0xD0; ++ bank = 0x1A26; ++ break; ++ case 0xD8: ++ case 0xD9: ++ axi_offset = 0xD8; ++ bank = 0x1A27; ++ break; ++ case 0xDA: ++ case 0xDB: ++ axi_offset = 0xDA; ++ bank = 0x1A28; ++ break; ++ }; ++ bank_offset = (offset - (axi_offset << 8)); ++ ++ return (bank << 9) + 0x1F000000 + bank_offset; ++} + + static inline u32 dwc3_readl(void __iomem *base, u32 offset) + { +@@ -33,15 +86,16 @@ static inline u32 dwc3_readl(void __iomem *base, u32 offset) + * space, see dwc3_probe in core.c. + * However, the offsets are given starting from xHCI address space. + */ +- value = readl(base + offset - DWC3_GLOBALS_REGS_START); + ++ offset += ((u32)base -0xFD344200); ++ value = INREG32(dwc3_to_sigma_rebase(offset, 0)); + /* + * When tracing we want to make it easy to find the correct address on + * documentation, so we revert it back to the proper addresses, the + * same way they are described on SNPS documentation + */ +- dwc3_trace(trace_dwc3_readl, "addr %p value %08x", +- base - DWC3_GLOBALS_REGS_START + offset, value); ++ dwc3_trace(trace_dwc3_readl, "addr %08x value %08x", ++ offset, value); + + return value; + } +@@ -53,15 +107,17 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) + * space, see dwc3_probe in core.c. + * However, the offsets are given starting from xHCI address space. + */ +- writel(value, base + offset - DWC3_GLOBALS_REGS_START); ++ ++ offset += ((u32)base -0xFD344200); ++ OUTREG32(dwc3_to_sigma_rebase(offset, value), value); + + /* + * When tracing we want to make it easy to find the correct address on + * documentation, so we revert it back to the proper addresses, the + * same way they are described on SNPS documentation + */ +- dwc3_trace(trace_dwc3_writel, "addr %p value %08x", +- base - DWC3_GLOBALS_REGS_START + offset, value); ++ dwc3_trace(trace_dwc3_writel, "addr %08x value %08x", ++ offset, value); + } + + #endif /* __DRIVERS_USB_DWC3_IO_H */ +diff --git a/drivers/usb/dwc3/trace.c b/drivers/usb/dwc3/trace.c +index 6cd166412ad0..83a90cd513db 100644 +--- a/drivers/usb/dwc3/trace.c ++++ b/drivers/usb/dwc3/trace.c +@@ -16,4 +16,5 @@ + */ + + #define CREATE_TRACE_POINTS ++#include "../drivers/sstar/include/ms_platform.h" + #include "trace.h" +diff --git a/drivers/usb/dwc3/trace.h b/drivers/usb/dwc3/trace.h +index d24cefd191b5..b57bb20c3c7c 100644 +--- a/drivers/usb/dwc3/trace.h ++++ b/drivers/usb/dwc3/trace.h +@@ -248,9 +248,9 @@ DECLARE_EVENT_CLASS(dwc3_log_trb, + __entry->size = trb->size; + __entry->ctrl = trb->ctrl; + ), +- TP_printk("%s: %d/%d trb %p buf %08x%08x size %d ctrl %08x (%c%c%c%c:%c%c:%s)", ++ TP_printk("%s: %d/%d trb %08x buf %08x%08x size %d ctrl %08x (%c%c%c%c:%c%c:%s)", + __get_str(name), __entry->queued, __entry->allocated, +- __entry->trb, __entry->bph, __entry->bpl, ++ (u32)Chip_Phys_to_MIU(virt_to_phys(__entry->trb)), __entry->bph, __entry->bpl, + __entry->size, __entry->ctrl, + __entry->ctrl & DWC3_TRB_CTRL_HWO ? 'H' : 'h', + __entry->ctrl & DWC3_TRB_CTRL_LST ? 'L' : 'l', +diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig +old mode 100644 +new mode 100755 +index f3ee80ece682..0dcbb18884c1 +--- a/drivers/usb/gadget/Kconfig ++++ b/drivers/usb/gadget/Kconfig +@@ -17,6 +17,7 @@ menuconfig USB_GADGET + tristate "USB Gadget Support" + select USB_COMMON + select NLS ++ select SS_GADGET + help + USB is a master/slave protocol, organized with one master + host (such as a PC) controlling up to 127 peripheral devices. +@@ -146,6 +147,9 @@ config USB_LIBCOMPOSITE + select CONFIGFS_FS + depends on USB_GADGET + ++config SS_GADGET ++ tristate ++ + config USB_F_ACM + tristate + +@@ -158,6 +162,9 @@ config USB_U_SERIAL + config USB_U_ETHER + tristate + ++config USB_U_AUDIO ++ tristate ++ + config USB_F_SERIAL + tristate + +@@ -188,9 +195,15 @@ config USB_F_MASS_STORAGE + config USB_F_FS + tristate + ++config USB_F_BI_DIRECTION ++ tristate ++ + config USB_F_UAC1 + tristate + ++config USB_F_UAC1_LEGACY ++ tristate ++ + config USB_F_UAC2 + tristate + +@@ -209,6 +222,9 @@ config USB_F_PRINTER + config USB_F_TCM + tristate + ++config USB_F_DFU ++ tristate ++ + # this first set of drivers all depend on bulk-capable hardware. + + config USB_CONFIGFS +@@ -368,12 +384,30 @@ config USB_CONFIGFS_F_UAC1 + depends on SND + select USB_LIBCOMPOSITE + select SND_PCM ++ select USB_U_AUDIO + select USB_F_UAC1 + help + This Audio function implements 1 AudioControl interface, + 1 AudioStreaming Interface each for USB-OUT and USB-IN. +- This driver requires a real Audio codec to be present +- on the device. ++ This driver doesn't expect any real Audio codec to be present ++ on the device - the audio streams are simply sinked to and ++ sourced from a virtual ALSA sound card created. The user-space ++ application may choose to do whatever it wants with the data ++ received from the USB Host and choose to provide whatever it ++ wants as audio data to the USB Host. ++ ++config USB_CONFIGFS_F_UAC1_LEGACY ++ bool "Audio Class 1.0 (legacy implementation)" ++ depends on USB_CONFIGFS ++ depends on SND ++ select USB_LIBCOMPOSITE ++ select SND_PCM ++ select USB_F_UAC1_LEGACY ++ help ++ This Audio function implements 1 AudioControl interface, ++ 1 AudioStreaming Interface each for USB-OUT and USB-IN. ++ This is a legacy driver and requires a real Audio codec ++ to be present on the device. + + config USB_CONFIGFS_F_UAC2 + bool "Audio Class 2.0" +@@ -381,6 +415,7 @@ config USB_CONFIGFS_F_UAC2 + depends on SND + select USB_LIBCOMPOSITE + select SND_PCM ++ select USB_U_AUDIO + select USB_F_UAC2 + help + This Audio function is compatible with USB Audio Class +diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile +index 598a67d6ba05..5634d2f3f6bb 100644 +--- a/drivers/usb/gadget/Makefile ++++ b/drivers/usb/gadget/Makefile +@@ -3,7 +3,6 @@ + # + subdir-ccflags-$(CONFIG_USB_GADGET_DEBUG) := -DDEBUG + subdir-ccflags-$(CONFIG_USB_GADGET_VERBOSE) += -DVERBOSE_DEBUG +-ccflags-y += -I$(srctree)/drivers/usb/gadget/udc + + obj-$(CONFIG_USB_LIBCOMPOSITE) += libcomposite.o + libcomposite-y := usbstring.o config.o epautoconf.o +diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c +index 406758ed0b23..085a42eb3bfb 100644 +--- a/drivers/usb/gadget/composite.c ++++ b/drivers/usb/gadget/composite.c +@@ -242,6 +242,80 @@ ep_found: + } + EXPORT_SYMBOL_GPL(config_ep_by_speed); + ++int config_ep_by_endp_desc(struct usb_gadget *g, ++ struct usb_endpoint_descriptor *chosen_desc, ++ struct usb_ss_ep_comp_descriptor *comp_desc, ++ struct usb_ep *_ep) ++{ ++ int want_comp_desc = 0; ++ ++ if (!g || !_ep || !chosen_desc) ++ return -EIO; ++ ++ /* select desired speed */ ++ switch (g->speed) { ++ case USB_SPEED_SUPER_PLUS: ++ if (gadget_is_superspeed_plus(g)) { ++ want_comp_desc = 1; ++ break; ++ } ++ /* else: Fall trough */ ++ case USB_SPEED_SUPER: ++ if (gadget_is_superspeed(g)) { ++ want_comp_desc = 1; ++ break; ++ } ++ /* else: Fall trough */ ++ case USB_SPEED_HIGH: ++ default: ++ break; ++ } ++ ++ /* commit results */ ++ _ep->maxpacket = usb_endpoint_maxp(chosen_desc) & 0x7ff; ++ _ep->desc = chosen_desc; ++ _ep->comp_desc = NULL; ++ _ep->maxburst = 0; ++ _ep->mult = 1; ++ ++ if (g->speed == USB_SPEED_HIGH && (usb_endpoint_xfer_isoc(_ep->desc) || ++ usb_endpoint_xfer_int(_ep->desc))) ++ _ep->mult = ((usb_endpoint_maxp(_ep->desc) & 0x1800) >> 11) + 1; ++ ++ if (!want_comp_desc) ++ return 0; ++ ++ /* ++ * Companion descriptor should follow EP descriptor ++ * USB 3.0 spec, #9.6.7 ++ */ ++ if (!comp_desc || ++ (comp_desc->bDescriptorType != USB_DT_SS_ENDPOINT_COMP)) ++ return -EIO; ++ _ep->comp_desc = comp_desc; ++ if (g->speed >= USB_SPEED_SUPER) { ++ switch (usb_endpoint_type(_ep->desc)) { ++ case USB_ENDPOINT_XFER_ISOC: ++ /* mult: bits 1:0 of bmAttributes */ ++ _ep->mult = (comp_desc->bmAttributes & 0x3) + 1; ++ case USB_ENDPOINT_XFER_BULK: ++ case USB_ENDPOINT_XFER_INT: ++ _ep->maxburst = comp_desc->bMaxBurst + 1; ++ break; ++ default: ++ if (comp_desc->bMaxBurst != 0) { ++ struct usb_composite_dev *cdev; ++ ++ cdev = get_gadget_data(g); ++ ERROR(cdev, "ep0 bMaxBurst must be 0\n"); ++ } ++ _ep->maxburst = 1; ++ break; ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL_GPL(config_ep_by_endp_desc); + /** + * usb_add_function() - add a function to a configuration + * @config: the configuration +@@ -318,6 +392,9 @@ void usb_remove_function(struct usb_configuration *c, struct usb_function *f) + list_del(&f->list); + if (f->unbind) + f->unbind(c, f); ++ ++ if (f->bind_deactivated) ++ usb_function_activate(f); + } + EXPORT_SYMBOL_GPL(usb_remove_function); + +@@ -959,12 +1036,8 @@ static void remove_config(struct usb_composite_dev *cdev, + + f = list_first_entry(&config->functions, + struct usb_function, list); +- list_del(&f->list); +- if (f->unbind) { +- DBG(cdev, "unbind function '%s'/%p\n", f->name, f); +- f->unbind(config, f); +- /* may free memory for "f" */ +- } ++ ++ usb_remove_function(config, f); + } + list_del(&config->list); + if (config->unbind) { +@@ -1998,6 +2071,11 @@ void composite_disconnect(struct usb_gadget *gadget) + /* REVISIT: should we have config and device level + * disconnect callbacks? + */ ++ if(!cdev) { ++ printk("%s: Enable UDC First\n",__func__); ++ return; ++ } ++ + spin_lock_irqsave(&cdev->lock, flags); + if (cdev->config) + reset_config(cdev); +@@ -2250,6 +2328,12 @@ void composite_suspend(struct usb_gadget *gadget) + * suspend/resume callbacks? + */ + DBG(cdev, "suspend\n"); ++ ++ if(!cdev) { ++ printk("%s: Enable UDC First\n",__func__); ++ return; ++ } ++ + if (cdev->config) { + list_for_each_entry(f, &cdev->config->functions, list) { + if (f->suspend) +@@ -2274,6 +2358,12 @@ void composite_resume(struct usb_gadget *gadget) + * suspend/resume callbacks? + */ + DBG(cdev, "resume\n"); ++ ++ if(!cdev) { ++ printk("%s: Enable UDC First\n",__func__); ++ return; ++ } ++ + if (cdev->driver->resume) + cdev->driver->resume(cdev); + if (cdev->config) { +diff --git a/drivers/usb/gadget/function/Makefile b/drivers/usb/gadget/function/Makefile +old mode 100644 +new mode 100755 +index cb8c225e8549..daced3a21526 +--- a/drivers/usb/gadget/function/Makefile ++++ b/drivers/usb/gadget/function/Makefile +@@ -32,8 +32,13 @@ usb_f_mass_storage-y := f_mass_storage.o storage_common.o + obj-$(CONFIG_USB_F_MASS_STORAGE)+= usb_f_mass_storage.o + usb_f_fs-y := f_fs.o + obj-$(CONFIG_USB_F_FS) += usb_f_fs.o +-usb_f_uac1-y := f_uac1.o u_uac1.o ++obj-$(CONFIG_USB_U_AUDIO) += u_audio.o ++usb_f_uac1-y := f_uac1.o + obj-$(CONFIG_USB_F_UAC1) += usb_f_uac1.o ++usb_f_uac1_legacy-y := f_uac1_legacy.o u_uac1_legacy.o ++obj-$(CONFIG_USB_F_UAC1_LEGACY) += usb_f_uac1_legacy.o ++usb_f_bi_direction-y := f_bi_direction.o u_bi_direction.o ++obj-$(CONFIG_USB_F_BI_DIRECTION) += usb_f_bi_direction.o + usb_f_uac2-y := f_uac2.o + obj-$(CONFIG_USB_F_UAC2) += usb_f_uac2.o + usb_f_uvc-y := f_uvc.o uvc_queue.o uvc_v4l2.o uvc_video.o uvc_configfs.o +@@ -46,3 +51,5 @@ usb_f_printer-y := f_printer.o + obj-$(CONFIG_USB_F_PRINTER) += usb_f_printer.o + usb_f_tcm-y := f_tcm.o + obj-$(CONFIG_USB_F_TCM) += usb_f_tcm.o ++usb_f_dfu-y := f_dfu.o ++obj-$(CONFIG_USB_F_DFU) += usb_f_dfu.o +diff --git a/drivers/usb/gadget/function/f_bi_direction.c b/drivers/usb/gadget/function/f_bi_direction.c +new file mode 100644 +index 000000000000..6945da798676 +--- /dev/null ++++ b/drivers/usb/gadget/function/f_bi_direction.c +@@ -0,0 +1,563 @@ ++/* ++ * f_bi_direction.c ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "u_bi_direction.h" ++ ++/* ++ * NEURAL NETWORK FUNCTION ... a testing vehicle for USB peripherals, ++ * ++ */ ++/*-------------------------------------------------------------------------*/ ++unsigned int log_level = LOG_ERR; ++module_param(log_level, uint, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(log_level, "Log level For Bi Module"); ++ ++static struct usb_interface_descriptor bi_intf = { ++ .bLength = sizeof bi_intf, ++ .bDescriptorType = USB_DT_INTERFACE, ++ ++ .bNumEndpoints = 2, ++ .bInterfaceClass = USB_CLASS_VENDOR_SPEC, ++ /* .iInterface = DYNAMIC */ ++}; ++ ++/* full speed support: */ ++ ++static struct usb_endpoint_descriptor fs_bi_in_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++}; ++ ++static struct usb_endpoint_descriptor fs_bi_out_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bEndpointAddress = USB_DIR_OUT, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++}; ++ ++static struct usb_descriptor_header *fs_bi_descs[] = { ++ (struct usb_descriptor_header *) &bi_intf, ++ (struct usb_descriptor_header *) &fs_bi_out_ep_desc, ++ (struct usb_descriptor_header *) &fs_bi_in_ep_desc, ++ NULL, ++}; ++ ++/* high speed support: */ ++ ++static struct usb_endpoint_descriptor hs_bi_in_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = cpu_to_le16(512), ++}; ++ ++static struct usb_endpoint_descriptor hs_bi_out_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = cpu_to_le16(512), ++}; ++ ++static struct usb_descriptor_header *hs_bi_descs[] = { ++ (struct usb_descriptor_header *) &bi_intf, ++ (struct usb_descriptor_header *) &hs_bi_in_ep_desc, ++ (struct usb_descriptor_header *) &hs_bi_out_ep_desc, ++ NULL, ++}; ++ ++/* super speed support: */ ++ ++static struct usb_endpoint_descriptor ss_bi_in_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = cpu_to_le16(1024), ++}; ++ ++static struct usb_ss_ep_comp_descriptor ss_bi_in_ep_comp_desc = { ++ .bLength = USB_DT_SS_EP_COMP_SIZE, ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++ .bMaxBurst = 0, ++ .bmAttributes = 0, ++ .wBytesPerInterval = 0, ++}; ++ ++static struct usb_endpoint_descriptor ss_bi_out_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = cpu_to_le16(1024), ++}; ++ ++static struct usb_ss_ep_comp_descriptor ss_bi_out_ep_comp_desc = { ++ .bLength = USB_DT_SS_EP_COMP_SIZE, ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++ .bMaxBurst = 0, ++ .bmAttributes = 0, ++ .wBytesPerInterval = 0, ++}; ++ ++static struct usb_descriptor_header *ss_bi_descs[] = { ++ (struct usb_descriptor_header *) &bi_intf, ++ (struct usb_descriptor_header *) &ss_bi_in_ep_desc, ++ (struct usb_descriptor_header *) &ss_bi_in_ep_comp_desc, ++ (struct usb_descriptor_header *) &ss_bi_out_ep_desc, ++ (struct usb_descriptor_header *) &ss_bi_out_ep_comp_desc, ++ NULL, ++}; ++ ++/* function-specific strings: */ ++ ++static struct usb_string strings_bi[] = { ++ [0].s = "bi input and output", ++ { } /* end of list */ ++}; ++ ++static struct usb_gadget_strings stringtab_bi = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings_bi, ++}; ++ ++static struct usb_gadget_strings *bi_function_strings[] = { ++ &stringtab_bi, ++ NULL, ++}; ++ ++/*-------------------------------------------------------------------------*/ ++static int bi_function_bind(struct usb_configuration *c, struct usb_function *f) ++{ ++ struct usb_composite_dev *cdev = c->cdev; ++ struct bi_device *bi = func_to_bi(f); ++ int id; ++ int ret; ++ ++ /* allocate interface ID(s) */ ++ id = usb_interface_id(c, f); ++ if (id < 0) ++ return id; ++ bi_intf.bInterfaceNumber = id; ++ ++ id = usb_string_id(cdev); ++ if (id < 0) ++ return id; ++ strings_bi[0].id = id; ++ bi_intf.iInterface = id; ++ ++ /* allocate endpoints */ ++ /* control ep */ ++//todo ++ /* Bulk In Endpoint */ ++ bi->in_ep = usb_ep_autoconfig(cdev->gadget, &fs_bi_in_ep_desc); ++ if (!bi->in_ep) { ++autoconf_fail: ++ ERROR(cdev, "%s: can't autoconfigure on %s\n", ++ f->name, cdev->gadget->name); ++ return -ENODEV; ++ } ++ bi->in_ep->driver_data = cdev; /* claim */ ++ ++ /* Bulk In Endpoint */ ++ bi->out_ep = usb_ep_autoconfig(cdev->gadget, &fs_bi_out_ep_desc); ++ if (!bi->out_ep) ++ goto autoconf_fail; ++ bi->out_ep->driver_data = cdev; /* claim */ ++ ++ /* support high speed hardware */ ++ hs_bi_in_ep_desc.bEndpointAddress = ++ fs_bi_in_ep_desc.bEndpointAddress; ++ hs_bi_out_ep_desc.bEndpointAddress = fs_bi_out_ep_desc.bEndpointAddress; ++ ++ /* support super speed hardware */ ++ ss_bi_in_ep_desc.bEndpointAddress = ++ fs_bi_in_ep_desc.bEndpointAddress; ++ ss_bi_out_ep_desc.bEndpointAddress = fs_bi_out_ep_desc.bEndpointAddress; ++ ++ ret = usb_assign_descriptors(f, fs_bi_descs, hs_bi_descs, ++ ss_bi_descs,NULL); ++ if (ret) ++ return ret; ++ ++ ret = bi_device_register(&cdev->gadget->dev, bi); ++ if (ret) ++ return ret; ++ ++ DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n", ++ (gadget_is_superspeed(c->cdev->gadget) ? "super" : ++ (gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full")), ++ f->name, bi->in_ep->name, bi->out_ep->name); ++ return 0; ++} ++ ++static void bi_function_unbind(struct usb_configuration * c, ++ struct usb_function * f) ++{ ++ struct bi_device *bi = func_to_bi(f); ++ ++ bi_device_unregister(bi); ++} ++ ++static void bi_function_free(struct usb_function *f) ++{ ++ struct f_bd_opts *opts; ++ ++ opts = container_of(f->fi, struct f_bd_opts, func_inst); ++ ++ mutex_lock(&opts->lock); ++ opts->refcnt--; ++ mutex_unlock(&opts->lock); ++ ++ usb_free_all_descriptors(f); ++ kfree(func_to_bi(f)); ++} ++ ++static int bi_function_set_alt(struct usb_function *f, ++ unsigned intf, unsigned alt) ++{ ++ struct bi_device *ndev = func_to_bi(f); ++ ++ /* we know alt is bi_direction */ ++ ++ if (ndev->in_ep->driver_data) ++ disable_bi_device(ndev); ++ return enable_bi_device(ndev); ++} ++ ++static void bi_function_disable(struct usb_function *f) ++{ ++ struct bi_device *bi = func_to_bi(f); ++ ++ disable_bi_device(bi); ++} ++ ++static int bi_function_setup(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_configuration *c = f->config; ++ struct usb_request *req = c->cdev->req; ++ int value = -EOPNOTSUPP; ++ u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 w_length = le16_to_cpu(ctrl->wLength); ++ ++ req->length = USB_COMP_EP0_BUFSIZ; ++ /* composite driver infrastructure handles everything except ++ * the two control test requests. ++ */ ++ ++ goto unknown;//todo ++ switch (ctrl->bRequest) { ++ ++ default: ++unknown: ++ VDBG(c->cdev, ++ "unknown control req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, w_length); ++ } ++ ++ /* respond with data transfer or status phase? */ ++ if (value >= 0) { ++ //VDBG ++ INFO(c->cdev, "in_ep/out_ep req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, w_length); ++ req->zero = 0; ++ req->length = value; ++ value = usb_ep_queue(c->cdev->gadget->ep0, req, GFP_ATOMIC); ++ if (value < 0) ++ ERROR(c->cdev, "in_ep/out_ep response, err %d\n", ++ value); ++ } ++ ++ /* device either stalls (value < 0) or reports success */ ++ return value; ++} ++ ++static void bi_function_suspend(struct usb_function * f) ++{ ++ //todo ++} ++ ++static void bi_function_resume(struct usb_function * f) ++{ ++ //todo ++} ++ ++static struct usb_function *bi_alloc(struct usb_function_instance *fi) ++{ ++ struct bi_device *bi; ++ struct f_bd_opts *bd_opts; ++ ++ bi = kzalloc(sizeof *bi, GFP_KERNEL); ++ if (!bi) ++ return ERR_PTR(-ENOMEM); ++ ++ bd_opts = container_of(fi, struct f_bd_opts, func_inst); ++ ++ mutex_lock(&bd_opts->lock); ++ bd_opts->refcnt++; ++ mutex_unlock(&bd_opts->lock); ++ ++ bi->bulk_in_buflen = bd_opts->bulk_in_buflen; ++ bi->bulk_in_qlen = bd_opts->bulk_in_qlen; ++ bi->bulk_out_buflen = bd_opts->bulk_out_buflen; ++ bi->bulk_out_qlen = bd_opts->bulk_out_qlen; ++ ++ bi->function.name = "bi"; ++ bi->function.bind = bi_function_bind; ++ bi->function.unbind = bi_function_unbind; ++ bi->function.setup = bi_function_setup; ++ bi->function.set_alt = bi_function_set_alt; ++ bi->function.disable = bi_function_disable; ++ bi->function.resume = bi_function_resume; ++ bi->function.suspend = bi_function_suspend; ++ bi->function.strings = bi_function_strings; ++ ++ bi->function.free_func = bi_function_free; ++ ++ return &bi->function; ++} ++ ++static inline struct f_bd_opts *to_f_bd_opts(struct config_item *item) ++{ ++ return container_of(to_config_group(item), struct f_bd_opts, ++ func_inst.group); ++} ++ ++static void bd_attr_release(struct config_item *item) ++{ ++ struct f_bd_opts *bd_opts = to_f_bd_opts(item); ++ ++ usb_put_function_instance(&bd_opts->func_inst); ++} ++ ++static struct configfs_item_operations bd_item_ops = { ++ .release = bd_attr_release, ++}; ++ ++static ssize_t f_bd_opts_bulk_in_qlen_show(struct config_item *item, char *page) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int result; ++ ++ mutex_lock(&opts->lock); ++ result = sprintf(page, "%d", opts->bulk_in_qlen); ++ mutex_unlock(&opts->lock); ++ ++ return result; ++} ++ ++static ssize_t f_bd_opts_bulk_out_qlen_show(struct config_item *item, char *page) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int result; ++ ++ mutex_lock(&opts->lock); ++ result = sprintf(page, "%d", opts->bulk_out_qlen); ++ mutex_unlock(&opts->lock); ++ ++ return result; ++} ++ ++static ssize_t f_bd_opts_bulk_in_qlen_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int ret; ++ u32 num; ++ ++ mutex_lock(&opts->lock); ++ if (opts->refcnt) { ++ ret = -EBUSY; ++ goto end; ++ } ++ ++ ret = kstrtou32(page, 0, &num); ++ if (ret) ++ goto end; ++ ++ opts->bulk_in_qlen = num; ++ ret = len; ++end: ++ mutex_unlock(&opts->lock); ++ return ret; ++} ++ ++static ssize_t f_bd_opts_bulk_out_qlen_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int ret; ++ u32 num; ++ ++ mutex_lock(&opts->lock); ++ if (opts->refcnt) { ++ ret = -EBUSY; ++ goto end; ++ } ++ ++ ret = kstrtou32(page, 0, &num); ++ if (ret) ++ goto end; ++ ++ opts->bulk_out_qlen = num; ++ ret = len; ++end: ++ mutex_unlock(&opts->lock); ++ return ret; ++} ++ ++CONFIGFS_ATTR(f_bd_opts_, bulk_in_qlen); ++CONFIGFS_ATTR(f_bd_opts_, bulk_out_qlen); ++ ++static ssize_t f_bd_opts_bulk_in_buflen_show(struct config_item *item, char *page) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int result; ++ ++ mutex_lock(&opts->lock); ++ result = sprintf(page, "%d", opts->bulk_in_buflen); ++ mutex_unlock(&opts->lock); ++ ++ return result; ++} ++ ++static ssize_t f_bd_opts_bulk_out_buflen_show(struct config_item *item, char *page) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int result; ++ ++ mutex_lock(&opts->lock); ++ result = sprintf(page, "%d", opts->bulk_out_buflen); ++ mutex_unlock(&opts->lock); ++ ++ return result; ++} ++ ++static ssize_t f_bd_opts_bulk_in_buflen_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int ret; ++ u32 num; ++ ++ mutex_lock(&opts->lock); ++ if (opts->refcnt) { ++ ret = -EBUSY; ++ goto end; ++ } ++ ++ ret = kstrtou32(page, 0, &num); ++ if (ret) ++ goto end; ++ ++ opts->bulk_in_buflen = num; ++ ret = len; ++end: ++ mutex_unlock(&opts->lock); ++ return ret; ++} ++ ++static ssize_t f_bd_opts_bulk_out_buflen_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct f_bd_opts *opts = to_f_bd_opts(item); ++ int ret; ++ u32 num; ++ ++ mutex_lock(&opts->lock); ++ if (opts->refcnt) { ++ ret = -EBUSY; ++ goto end; ++ } ++ ++ ret = kstrtou32(page, 0, &num); ++ if (ret) ++ goto end; ++ ++ opts->bulk_out_buflen = num; ++ ret = len; ++end: ++ mutex_unlock(&opts->lock); ++ return ret; ++} ++ ++CONFIGFS_ATTR(f_bd_opts_, bulk_in_buflen); ++CONFIGFS_ATTR(f_bd_opts_, bulk_out_buflen); ++ ++static struct configfs_attribute *bd_attrs[] = { ++ &f_bd_opts_attr_bulk_in_qlen, ++ &f_bd_opts_attr_bulk_out_qlen, ++ &f_bd_opts_attr_bulk_in_buflen, ++ &f_bd_opts_attr_bulk_out_buflen, ++ NULL, ++}; ++ ++static struct config_item_type bd_func_type = { ++ .ct_item_ops = &bd_item_ops, ++ .ct_attrs = bd_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static void bd_free_instance(struct usb_function_instance *fi) ++{ ++ struct f_bd_opts *bd_opts; ++ ++ bd_opts = container_of(fi, struct f_bd_opts, func_inst); ++ kfree(bd_opts); ++} ++ ++static struct usb_function_instance *bi_alloc_instance(void) ++{ ++ struct f_bd_opts *bd_opts; ++ ++ bd_opts = kzalloc(sizeof(*bd_opts), GFP_KERNEL); ++ if (!bd_opts) ++ return ERR_PTR(-ENOMEM); ++ mutex_init(&bd_opts->lock); ++ bd_opts->func_inst.free_func_inst = bd_free_instance; ++ bd_opts->bulk_in_buflen = GBI_DIRECTION_BULK_IN_BUFLEN; ++ bd_opts->bulk_in_qlen = GBI_DIRECTION_BULK_IN_QLEN; ++ bd_opts->bulk_out_buflen = GBI_DIRECTION_BULK_OUT_BUFLEN; ++ bd_opts->bulk_out_qlen = GBI_DIRECTION_BULK_OUT_QLEN; ++ ++ config_group_init_type_name(&bd_opts->func_inst.group, "", ++ &bd_func_type); ++ ++ return &bd_opts->func_inst; ++} ++DECLARE_USB_FUNCTION(Bi, bi_alloc_instance, bi_alloc); ++ ++int __init bd_modinit(void) ++{ ++ int ret; ++ ++ ret = usb_function_register(&Biusb_func); ++ if (ret) ++ return ret; ++ return ret; ++} ++void __exit bd_modexit(void) ++{ ++ usb_function_unregister(&Biusb_func); ++} ++module_init(bd_modinit); ++module_exit(bd_modexit); ++ ++MODULE_AUTHOR("Claude Rao"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/usb/gadget/function/f_dfu.c b/drivers/usb/gadget/function/f_dfu.c +new file mode 100755 +index 000000000000..f24ab0fbba3c +--- /dev/null ++++ b/drivers/usb/gadget/function/f_dfu.c +@@ -0,0 +1,729 @@ ++/* ++ * f_dfu.c ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "f_dfu.h" ++ ++static char *version_file = "/customer/version_info"; ++module_param(version_file, charp, S_IRUGO|S_IWUSR); ++ ++static char dfu_buf[100]={0}; ++/* ++ * Device Firmware Upgrade FUNCTION ... a testing vehicle for USB peripherals, ++ * ++ */ ++/*-------------------------------------------------------------------------*/ ++static const struct dfu_function_descriptor dfu_func = { ++ .bLength = sizeof dfu_func, ++ .bDescriptorType = DFU_DT_FUNC, ++ .bmAttributes = DFU_BIT_WILL_DETACH | ++ DFU_BIT_MANIFESTATION_TOLERANT | ++ DFU_BIT_CAN_UPLOAD | ++ DFU_BIT_CAN_DNLOAD, ++ .wDetachTimeOut = 0, ++ .wTransferSize = DFU_USB_BUFSIZ, ++ .bcdDFUVersion = __constant_cpu_to_le16(0x0110), ++}; ++ ++static struct usb_interface_descriptor dfu_intf = { ++ .bLength = sizeof dfu_intf, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_APP_SPEC, ++ .bInterfaceSubClass = 1, ++ .bInterfaceProtocol = 1, ++ /* .iInterface = DYNAMIC */ ++}; ++ ++/* ++static struct usb_descriptor_header *dfu_runtime_descs[] = { ++ (struct usb_descriptor_header *) &dfu_intf, ++ NULL, ++}; ++*/ ++ ++static struct usb_descriptor_header *fs_dfu_descs[] = { ++ (struct usb_descriptor_header *) &dfu_intf, ++ (struct usb_descriptor_header *) &dfu_func, ++ NULL, ++}; ++ ++static struct usb_descriptor_header *hs_dfu_descs[] = { ++ (struct usb_descriptor_header *) &dfu_intf, ++ (struct usb_descriptor_header *) &dfu_func, ++ NULL, ++}; ++ ++/* super speed support: */ ++static struct usb_descriptor_header *ss_dfu_descs[] = { ++ (struct usb_descriptor_header *) &dfu_intf, ++ (struct usb_descriptor_header *) &dfu_func, ++ NULL, ++}; ++ ++/* function-specific strings: */ ++ ++static struct usb_string strings_dfu[] = { ++ [0].s = "At Runtime Mode", ++ [1].s = "At Dfu Mode", ++ { } /* end of list */ ++}; ++ ++static struct usb_gadget_strings stringtab_dfu = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings_dfu, ++}; ++ ++static struct usb_gadget_strings *dfu_function_strings[] = { ++ &stringtab_dfu, ++ NULL, ++}; ++ ++/*-------------------------------------------------------------------------*/ ++static void delay_reboot(struct work_struct *data) ++{ ++ struct file *filp = NULL; ++ char *str_path[] = {"/bin", "/usr/bin", "/config", "/sbin", "/customer", "/etc"}; ++ char cmd_bin[] = "/fw_setenv"; ++ char cur_path[50] = "\0"; ++ ++ char *cmd_argv[] = {cur_path, "enter_dfu_mode", "1", NULL}; ++ char *cmd_envp[] = { ++ "HOME=/", ++ "PATH=/sbin:/usr/sbin:/bin:/usr/bin:/etc:/customer", ++ NULL}; ++ int index = 0; ++ ++ for (index = 0; index < sizeof(str_path)/sizeof(char*);index++) ++ { ++ strcpy(cur_path, str_path[index]); ++ strcat(cur_path, cmd_bin); ++ ++ filp = filp_open(cur_path, O_RDONLY, 0); ++ if (IS_ERR_OR_NULL(filp)) { ++ continue; ++ } ++ break; ++ } ++ if (IS_ERR_OR_NULL(filp)) ++ { ++ printk("no fw_setenv tool\n"); ++ return; ++ } else ++ { ++ printk("Found %s tool\n", cur_path); ++ filp_close(filp, NULL); ++ filp = NULL; ++ call_usermodehelper(cur_path, cmd_argv, cmd_envp, UMH_WAIT_PROC); ++ } ++ ++ kernel_restart("to Uboot DFU Mode"); ++} ++ ++static int dfu_function_bind(struct usb_configuration *c, struct usb_function *f) ++{ ++ struct usb_composite_dev *cdev = c->cdev; ++ struct f_dfu *dfu = func_to_dfu(f); ++ int id; ++ int ret; ++ ++ struct file* fp = NULL; ++ struct inode *inode; ++ ++ mm_segment_t old_fs; ++ loff_t fsize; ++ ++ fp = filp_open(version_file,O_RDWR ,0); ++ if(IS_ERR(fp)) { ++ printk("%s open fail\n", version_file); ++ } ++ else { ++ inode = file_inode(fp); ++ fsize = inode->i_size; ++ if(fsize < 100) ++ { ++ old_fs = get_fs(); ++ set_fs(KERNEL_DS); ++ vfs_read(fp, dfu_buf, fsize+1, &(fp->f_pos)); ++ filp_close(fp,NULL); ++ set_fs(old_fs); ++ strings_dfu[0].s = dfu_buf; ++ } ++ else ++ { ++ printk("version and production info too long show default info: %s\n",strings_dfu[0].s); ++ } ++ } ++ printk("strings_dfu[0].s = %s\n",strings_dfu[0].s); ++ ++ /* allocate interface ID(s) */ ++ id = usb_interface_id(c, f); ++ if (id < 0) ++ return id; ++ dfu_intf.bInterfaceNumber = id; ++ ++ /* allocate string ID(s) */ ++ id = usb_string_id(cdev); ++ if (id < 0) ++ return id; ++ strings_dfu[0].id = id; ++ ++ id = usb_string_id(cdev); ++ if (id < 0) ++ return id; ++ strings_dfu[1].id = id; ++ ++ dfu_intf.iInterface = strings_dfu[0].id; ++ dfu_intf.bInterfaceProtocol = 1; ++ ++ /* assign descriptors */ ++ ret = usb_assign_descriptors(f, fs_dfu_descs, hs_dfu_descs, ++ ss_dfu_descs,NULL); ++ if (ret) ++ return ret; ++ ++ dfu->dfu_state = DFU_STATE_appIDLE; ++ dfu->dfu_status = DFU_STATUS_OK; ++ INIT_WORK(&dfu->reboot, delay_reboot); ++ ++ DBG(cdev, "%s speed %s\n", ++ (gadget_is_superspeed(c->cdev->gadget) ? "super" : ++ (gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full")), ++ f->name); ++ return 0; ++} ++ ++static void dfu_function_unbind(struct usb_configuration * c, ++ struct usb_function * f) ++{ ++ //struct f_dfu *dfu = func_to_dfu(f); ++} ++ ++static void dfu_function_free(struct usb_function *f) ++{ ++ struct f_dfu_opts *opts; ++ ++ opts = container_of(f->fi, struct f_dfu_opts, func_inst); ++ ++ mutex_lock(&opts->lock); ++ opts->refcnt--; ++ mutex_unlock(&opts->lock); ++ ++ usb_free_all_descriptors(f); ++ kfree(func_to_dfu(f)); ++} ++ ++static int dfu_function_set_alt(struct usb_function *f, ++ unsigned intf, unsigned alt) ++{ ++ /* we know alt is dfu */ ++ ++ return 0; ++} ++ ++static void dfu_function_disable(struct usb_function *f) ++{ ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->length == 0) ++ printk("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); ++} ++ ++static void handle_getstatus(struct f_dfu *f_dfu, struct usb_request *req) ++{ ++ struct dfu_status *dstat = (struct dfu_status *)req->buf; ++ ++ switch (f_dfu->dfu_state) { ++ case DFU_STATE_dfuDNLOAD_SYNC: ++ case DFU_STATE_dfuDNBUSY: ++ f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE; ++ break; ++ case DFU_STATE_dfuMANIFEST_SYNC: ++ break; ++ default: ++ break; ++ } ++ ++ /* send status response */ ++ dstat->bStatus = f_dfu->dfu_status; ++ dstat->bwPollTimeout[0] = 0; ++ dstat->bwPollTimeout[1] = 0; ++ dstat->bwPollTimeout[2] = 0; ++ dstat->bState = f_dfu->dfu_state; ++ dstat->iString = dfu_intf.bInterfaceProtocol == 1?0:1; ++} ++ ++static void handle_getstate(struct f_dfu *f_dfu, struct usb_request *req) ++{ ++ ((u8 *)req->buf)[0] = f_dfu->dfu_state; ++ req->actual = sizeof(u8); ++} ++ ++static inline void to_dfu_mode(struct f_dfu *f_dfu) ++{ ++ struct usb_function *f = &f_dfu->usb_function; ++ ++ dfu_intf.iInterface = strings_dfu[1].id; ++ dfu_intf.bInterfaceProtocol = 2; ++ ++ usb_free_all_descriptors(f); ++ usb_assign_descriptors(f, fs_dfu_descs, hs_dfu_descs, ++ ss_dfu_descs,NULL); ++ ++ //to uboot ++ schedule_work(&f_dfu->reboot); ++} ++ ++static inline void to_runtime_mode(struct f_dfu *f_dfu) ++{ ++ struct usb_function *f = &f_dfu->usb_function; ++ ++ dfu_intf.iInterface = strings_dfu[0].id; ++ dfu_intf.bInterfaceProtocol = 1; ++ ++ usb_free_all_descriptors(f); ++ usb_assign_descriptors(f, fs_dfu_descs, hs_dfu_descs, ++ ss_dfu_descs,NULL); ++} ++ ++static int handle_upload(struct f_dfu *f_dfu, struct usb_request *req, u16 len) ++{ ++ return len; ++} ++ ++static int handle_dnload(struct f_dfu *f_dfu,struct usb_gadget *gadget, u16 len) ++{ ++ struct usb_composite_dev *cdev = get_gadget_data(gadget); ++ struct usb_request *req = cdev->req; ++ ++ if (len == 0) ++ f_dfu->dfu_state = DFU_STATE_dfuMANIFEST_SYNC; ++ ++ req->complete = dnload_request_complete; ++ ++ return len; ++} ++/*-------------------------------------------------------------------------*/ ++/* DFU state machine */ ++static int state_app_idle(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ int value = 0; ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ case USB_REQ_DFU_DETACH: ++ f_dfu->dfu_state = DFU_STATE_appDETACH; ++ to_dfu_mode(f_dfu); ++ f_dfu->dfu_state = DFU_STATE_dfuIDLE; ++ value = RET_ZLP; ++ break; ++ default: ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_app_detach(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_appIDLE; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_idle(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_DNLOAD: ++ if (len == 0) { ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_SYNC; ++ f_dfu->blk_seq_num = w_value; ++ value = handle_dnload(f_dfu, gadget, len); ++ break; ++ case USB_REQ_DFU_UPLOAD: ++ f_dfu->dfu_state = DFU_STATE_dfuUPLOAD_IDLE; ++ f_dfu->blk_seq_num = 0; ++ value = handle_upload(f_dfu, req, len); ++ break; ++ case USB_REQ_DFU_ABORT: ++ /* no zlp? */ ++ value = RET_ZLP; ++ break; ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ case USB_REQ_DFU_DETACH: ++ /* ++ * Proprietary extension: 'detach' from idle mode and ++ * get back to runtime mode in case of USB Reset. As ++ * much as I dislike this, we just can't use every USB ++ * bus reset to switch back to runtime mode, since at ++ * least the Linux USB stack likes to send a number of ++ * resets in a row :( ++ */ ++ f_dfu->dfu_state = ++ DFU_STATE_dfuMANIFEST_WAIT_RST; ++ to_runtime_mode(f_dfu); ++ f_dfu->dfu_state = DFU_STATE_appIDLE; ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_dnload_sync(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_dnbusy(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_dnload_idle(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_DNLOAD: ++ f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_SYNC; ++ f_dfu->blk_seq_num = w_value; ++ value = handle_dnload(f_dfu, gadget, len); ++ break; ++ case USB_REQ_DFU_ABORT: ++ f_dfu->dfu_state = DFU_STATE_dfuIDLE; ++ value = RET_ZLP; ++ break; ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_manifest_sync(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_GETSTATUS: ++ /* We're MainfestationTolerant */ ++ f_dfu->dfu_state = DFU_STATE_dfuIDLE; ++ handle_getstatus(f_dfu, req); ++ f_dfu->blk_seq_num = 0; ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_upload_idle(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_UPLOAD: ++ /* state transition if less data then requested */ ++ f_dfu->blk_seq_num = w_value; ++ value = handle_upload(f_dfu, req, len); ++ if (value >= 0 && value < len) ++ f_dfu->dfu_state = DFU_STATE_dfuIDLE; ++ break; ++ case USB_REQ_DFU_ABORT: ++ f_dfu->dfu_state = DFU_STATE_dfuIDLE; ++ /* no zlp? */ ++ value = RET_ZLP; ++ break; ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static int state_dfu_error(struct f_dfu *f_dfu, ++ const struct usb_ctrlrequest *ctrl, ++ struct usb_gadget *gadget, ++ struct usb_request *req) ++{ ++ int value = 0; ++ ++ switch (ctrl->bRequest) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(f_dfu, req); ++ value = RET_STAT_LEN; ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(f_dfu, req); ++ break; ++ case USB_REQ_DFU_CLRSTATUS: ++ f_dfu->dfu_state = DFU_STATE_dfuIDLE; ++ f_dfu->dfu_status = DFU_STATUS_OK; ++ /* no zlp? */ ++ value = RET_ZLP; ++ break; ++ default: ++ f_dfu->dfu_state = DFU_STATE_dfuERROR; ++ value = RET_STALL; ++ break; ++ } ++ ++ return value; ++} ++ ++static dfu_state_fn dfu_state[] = { ++ state_app_idle, /* DFU_STATE_appIDLE */ ++ state_app_detach, /* DFU_STATE_appDETACH */ ++ state_dfu_idle, /* DFU_STATE_dfuIDLE */ ++ state_dfu_dnload_sync, /* DFU_STATE_dfuDNLOAD_SYNC */ ++ state_dfu_dnbusy, /* DFU_STATE_dfuDNBUSY */ ++ state_dfu_dnload_idle, /* DFU_STATE_dfuDNLOAD_IDLE */ ++ state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */ ++ NULL, /* DFU_STATE_dfuMANIFEST */ ++ NULL, /* DFU_STATE_dfuMANIFEST_WAIT_RST */ ++ state_dfu_upload_idle, /* DFU_STATE_dfuUPLOAD_IDLE */ ++ state_dfu_error /* DFU_STATE_dfuERROR */ ++}; ++ ++static int dfu_function_setup(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_configuration *c = f->config; ++ struct usb_request *req = c->cdev->req; ++ struct f_dfu *dfu = func_to_dfu(f); ++ struct usb_gadget *gadget = f->config->cdev->gadget; ++ int value = -EOPNOTSUPP; ++ //u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 w_length = le16_to_cpu(ctrl->wLength); ++ u8 req_type = ctrl->bRequestType & USB_TYPE_MASK; ++ ++ INFO(c->cdev, "0x%p dfu->dfu_state: 0x%x bReqType: 0x%x bRequest: 0x%x " ++ "w_value: 0x%x w_length: 0x%x\n", dfu, ++ dfu->dfu_state, req_type, ctrl->bRequest, w_value, w_length); ++ ++ if (req_type == USB_TYPE_STANDARD) { ++ if (ctrl->bRequest == USB_REQ_GET_DESCRIPTOR && ++ (w_value >> 8) == DFU_DT_FUNC) { ++ value = min(w_length, (u16) sizeof(dfu_func)); ++ memcpy(req->buf, &dfu_func, value); ++ } ++ } else /* DFU specific request */ ++ value = dfu_state[dfu->dfu_state] (dfu, ctrl, gadget, req); ++ ++ if (value >= 0) { ++ req->length = value; ++ req->zero = value < w_length; ++ value = usb_ep_queue(gadget->ep0, req, 0); ++ if (value < 0) { ++ printk("ep_queue --> %d\n", value); ++ req->status = 0; ++ } ++ } ++ ++ return value; ++} ++ ++static void dfu_function_suspend(struct usb_function * f) ++{ ++ //todo ++} ++ ++static void dfu_function_resume(struct usb_function * f) ++{ ++ //todo ++} ++ ++static struct usb_function *dfu_alloc(struct usb_function_instance *fi) ++{ ++ struct f_dfu *dfu; ++ struct f_dfu_opts *dfu_opts; ++ ++ dfu = kzalloc(sizeof *dfu, GFP_KERNEL); ++ if (!dfu) ++ return ERR_PTR(-ENOMEM); ++ ++ dfu_opts = container_of(fi, struct f_dfu_opts, func_inst); ++ ++ mutex_lock(&dfu_opts->lock); ++ dfu_opts->refcnt++; ++ mutex_unlock(&dfu_opts->lock); ++ ++ dfu->usb_function.name = "dfu"; ++ dfu->usb_function.bind = dfu_function_bind; ++ dfu->usb_function.unbind = dfu_function_unbind; ++ dfu->usb_function.setup = dfu_function_setup; ++ dfu->usb_function.set_alt = dfu_function_set_alt; ++ dfu->usb_function.disable = dfu_function_disable; ++ dfu->usb_function.resume = dfu_function_resume; ++ dfu->usb_function.suspend = dfu_function_suspend; ++ dfu->usb_function.strings = dfu_function_strings; ++ ++ dfu->usb_function.free_func = dfu_function_free; ++ ++ return &dfu->usb_function; ++} ++ ++static inline struct f_dfu_opts *to_f_dfu_opts(struct config_item *item) ++{ ++ return container_of(to_config_group(item), struct f_dfu_opts, ++ func_inst.group); ++} ++ ++static void dfu_free_instance(struct usb_function_instance *fi) ++{ ++ struct f_dfu_opts *dfu_opts; ++ ++ dfu_opts = container_of(fi, struct f_dfu_opts, func_inst); ++ kfree(dfu_opts); ++} ++ ++static struct usb_function_instance *dfu_alloc_instance(void) ++{ ++ struct f_dfu_opts *dfu_opts; ++ ++ dfu_opts = kzalloc(sizeof(*dfu_opts), GFP_KERNEL); ++ if (!dfu_opts) ++ return ERR_PTR(-ENOMEM); ++ mutex_init(&dfu_opts->lock); ++ dfu_opts->func_inst.free_func_inst = dfu_free_instance; ++ ++ return &dfu_opts->func_inst; ++} ++DECLARE_USB_FUNCTION_INIT(dfu, dfu_alloc_instance, dfu_alloc); ++ ++MODULE_AUTHOR("Claude Rao"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/usb/gadget/function/f_dfu.h b/drivers/usb/gadget/function/f_dfu.h +new file mode 100755 +index 000000000000..d74472deba5d +--- /dev/null ++++ b/drivers/usb/gadget/function/f_dfu.h +@@ -0,0 +1,133 @@ ++/* ++ * f_dfu.h -- Device Firmware Update gadget ++ * ++ * Copyright (C) 2011-2012 Samsung Electronics ++ * author: Andrzej Pietrasiewicz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __F_DFU_H_ ++#define __F_DFU_H_ ++ ++#include ++#include ++ ++#define DFU_CONFIG_VAL 1 ++#define DFU_DT_FUNC 0x21 ++ ++#define DFU_BIT_WILL_DETACH (0x1 << 3) ++#define DFU_BIT_MANIFESTATION_TOLERANT (0x1 << 2) ++#define DFU_BIT_CAN_UPLOAD (0x1 << 1) ++#define DFU_BIT_CAN_DNLOAD 0x1 ++ ++/* big enough to hold our biggest descriptor */ ++#define DFU_USB_BUFSIZ 4096 ++ ++#define USB_REQ_DFU_DETACH 0x00 ++#define USB_REQ_DFU_DNLOAD 0x01 ++#define USB_REQ_DFU_UPLOAD 0x02 ++#define USB_REQ_DFU_GETSTATUS 0x03 ++#define USB_REQ_DFU_CLRSTATUS 0x04 ++#define USB_REQ_DFU_GETSTATE 0x05 ++#define USB_REQ_DFU_ABORT 0x06 ++ ++#define DFU_STATUS_OK 0x00 ++#define DFU_STATUS_errTARGET 0x01 ++#define DFU_STATUS_errFILE 0x02 ++#define DFU_STATUS_errWRITE 0x03 ++#define DFU_STATUS_errERASE 0x04 ++#define DFU_STATUS_errCHECK_ERASED 0x05 ++#define DFU_STATUS_errPROG 0x06 ++#define DFU_STATUS_errVERIFY 0x07 ++#define DFU_STATUS_errADDRESS 0x08 ++#define DFU_STATUS_errNOTDONE 0x09 ++#define DFU_STATUS_errFIRMWARE 0x0a ++#define DFU_STATUS_errVENDOR 0x0b ++#define DFU_STATUS_errUSBR 0x0c ++#define DFU_STATUS_errPOR 0x0d ++#define DFU_STATUS_errUNKNOWN 0x0e ++#define DFU_STATUS_errSTALLEDPKT 0x0f ++ ++#define RET_STALL -1 ++#define RET_ZLP 0 ++#define RET_STAT_LEN 6 ++ ++typedef enum dfu_state { ++ DFU_STATE_appIDLE = 0, ++ DFU_STATE_appDETACH = 1, ++ DFU_STATE_dfuIDLE = 2, ++ DFU_STATE_dfuDNLOAD_SYNC = 3, ++ DFU_STATE_dfuDNBUSY = 4, ++ DFU_STATE_dfuDNLOAD_IDLE = 5, ++ DFU_STATE_dfuMANIFEST_SYNC = 6, ++ DFU_STATE_dfuMANIFEST = 7, ++ DFU_STATE_dfuMANIFEST_WAIT_RST = 8, ++ DFU_STATE_dfuUPLOAD_IDLE = 9, ++ DFU_STATE_dfuERROR = 10, ++} dfu_state_e; ++ ++struct dfu_status { ++ __u8 bStatus; ++ __u8 bwPollTimeout[3]; ++ __u8 bState; ++ __u8 iString; ++} __packed; ++ ++struct dfu_function_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bmAttributes; ++ __le16 wDetachTimeOut; ++ __le16 wTransferSize; ++ __le16 bcdDFUVersion; ++} __packed; ++ ++struct f_dfu_opts { ++ struct usb_function_instance func_inst; ++ /* ++ * Read/write access to configfs attributes is handled by configfs. ++ * ++ * This is to protect the data from concurrent access by read/write ++ * and create symlink/remove symlink. ++ */ ++ struct mutex lock; ++ int refcnt; ++}; ++ ++ ++struct f_dfu { ++ char name[20]; ++ struct usb_function usb_function; ++ dfu_state_e dfu_state; ++ unsigned int dfu_status; ++ ++ struct work_struct reboot; ++ /* Send/received block number is handy for data integrity check */ ++ int blk_seq_num; ++ ++}; ++ ++static inline struct f_dfu *func_to_dfu(struct usb_function *f) ++{ ++ return container_of(f, struct f_dfu, usb_function); ++} ++ ++typedef int (*dfu_state_fn) (struct f_dfu *, ++ const struct usb_ctrlrequest *, ++ struct usb_gadget *, ++ struct usb_request *); ++ ++#endif /* __F_DFU_H_ */ +diff --git a/drivers/usb/gadget/function/f_midi.c b/drivers/usb/gadget/function/f_midi.c +index a5719f271bf0..70ac1963b598 100644 +--- a/drivers/usb/gadget/function/f_midi.c ++++ b/drivers/usb/gadget/function/f_midi.c +@@ -389,7 +389,8 @@ static int f_midi_set_alt(struct usb_function *f, unsigned intf, unsigned alt) + if (err) { + ERROR(midi, "%s: couldn't enqueue request: %d\n", + midi->out_ep->name, err); +- free_ep_req(midi->out_ep, req); ++ if (req->buf != NULL) ++ free_ep_req(midi->out_ep, req); + return err; + } + } +diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c +index ba00cdb809d6..ec3a8f15fd44 100644 +--- a/drivers/usb/gadget/function/f_rndis.c ++++ b/drivers/usb/gadget/function/f_rndis.c +@@ -29,6 +29,10 @@ + #include "rndis.h" + #include "configfs.h" + ++static unsigned int bulk_maxpacket = 0; ++module_param_named(maxpacket, bulk_maxpacket, uint, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(maxpacket, "1 - 64 (FS), 1 - 512 (HS), 1 - 1024 (SS)"); ++ + /* + * This function is an RNDIS Ethernet port -- a Microsoft protocol that's + * been promoted instead of the standard CDC Ethernet. The published RNDIS +@@ -479,6 +483,12 @@ rndis_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + */ + switch ((ctrl->bRequestType << 8) | ctrl->bRequest) { + ++#ifdef CONFIG_USB_WEBCAM_RNDIS // ss patch ++ case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8) ++ | USB_CDC_SET_ETHERNET_PACKET_FILTER: ++ value = 0; ++ break; ++#endif + /* RNDIS uses the CDC command encapsulation mechanism to implement + * an RPC scheme, with much getting/setting of attributes by OID. + */ +@@ -740,6 +750,11 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f) + + status = -ENODEV; + ++ if (bulk_maxpacket) ++ { ++ fs_in_desc.wMaxPacketSize = bulk_maxpacket; ++ fs_out_desc.wMaxPacketSize = bulk_maxpacket; ++ } + /* allocate instance-specific endpoints */ + ep = usb_ep_autoconfig(cdev->gadget, &fs_in_desc); + if (!ep) +@@ -777,10 +792,22 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f) + * hardware is dual speed, all bulk-capable endpoints work at + * both speeds + */ ++ if (hs_in_desc.wMaxPacketSize > rndis->port.in_ep->maxpacket_limit) ++ hs_in_desc.wMaxPacketSize = rndis->port.in_ep->maxpacket_limit; ++ ++ if (hs_out_desc.wMaxPacketSize > rndis->port.out_ep->maxpacket_limit) ++ hs_out_desc.wMaxPacketSize = rndis->port.out_ep->maxpacket_limit; ++ + hs_in_desc.bEndpointAddress = fs_in_desc.bEndpointAddress; + hs_out_desc.bEndpointAddress = fs_out_desc.bEndpointAddress; + hs_notify_desc.bEndpointAddress = fs_notify_desc.bEndpointAddress; + ++ if (ss_in_desc.wMaxPacketSize > rndis->port.in_ep->maxpacket_limit) ++ ss_in_desc.wMaxPacketSize = rndis->port.in_ep->maxpacket_limit; ++ ++ if (ss_out_desc.wMaxPacketSize > rndis->port.out_ep->maxpacket_limit) ++ ss_out_desc.wMaxPacketSize = rndis->port.out_ep->maxpacket_limit; ++ + ss_in_desc.bEndpointAddress = fs_in_desc.bEndpointAddress; + ss_out_desc.bEndpointAddress = fs_out_desc.bEndpointAddress; + ss_notify_desc.bEndpointAddress = fs_notify_desc.bEndpointAddress; +diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c +index f2ac0cbc29a4..3169dc3ccab5 100644 +--- a/drivers/usb/gadget/function/f_uac1.c ++++ b/drivers/usb/gadget/function/f_uac1.c +@@ -1,37 +1,64 @@ ++// SPDX-License-Identifier: GPL-2.0+ + /* +- * f_audio.c -- USB Audio class function driver +- * +- * Copyright (C) 2008 Bryan Wu +- * Copyright (C) 2008 Analog Devices, Inc ++ * f_uac1.c -- USB Audio Class 1.0 Function (using u_audio API) + * +- * Enter bugs at http://blackfin.uclinux.org/ ++ * Copyright (C) 2016 Ruslan Bilovol + * +- * Licensed under the GPL-2 or later. ++ * This driver doesn't expect any real Audio codec to be present ++ * on the device - the audio streams are simply sinked to and ++ * sourced from a virtual ALSA sound card created. ++ * ++ * This file is based on f_uac1.c which is ++ * Copyright (C) 2008 Bryan Wu ++ * Copyright (C) 2008 Analog Devices, Inc + */ + +-#include +-#include ++#include + #include +-#include +-#include + ++#include "u_audio.h" + #include "u_uac1.h" + ++ ++struct f_uac1 { ++ struct g_audio g_audio; ++ u8 ac_intf, as_in_intf, as_out_intf; ++ u8 ac_alt, as_in_alt, as_out_alt; /* needed for get_alt() */ ++ ++ /* Control Set command */ ++ struct work_struct cmd_work; ++ struct list_head cs; ++ u8 set_cmd, ready_cmd; ++ int ready_value; ++ struct usb_audio_control *set_con, *ready_con; ++}; ++ ++static struct f_uac1 *g_f_uac1 = NULL; + static int generic_set_cmd(struct usb_audio_control *con, u8 cmd, int value); + static int generic_get_cmd(struct usb_audio_control *con, u8 cmd); + ++static inline struct f_uac1 *func_to_uac1(struct usb_function *f) ++{ ++ return container_of(f, struct f_uac1, g_audio.func); ++} ++ + /* + * DESCRIPTORS ... most are static, but strings and full + * configuration descriptors are built on demand. + */ + + /* +- * We have two interfaces- AudioControl and AudioStreaming +- * TODO: only supcard playback currently ++ * We have three interfaces - one AudioControl and two AudioStreaming ++ * ++ * The driver implements a simple UAC_1 topology. ++ * USB-OUT -> IT_1 -> OT_2 -> ALSA_Capture ++ * ALSA_Playback -> IT_3 -> OT_4 -> USB-IN + */ +-#define F_AUDIO_AC_INTERFACE 0 +-#define F_AUDIO_AS_INTERFACE 1 +-#define F_AUDIO_NUM_INTERFACES 1 ++#define F_AUDIO_AC_INTERFACE 0 ++#define F_AUDIO_AS_OUT_INTERFACE 1 ++#define F_AUDIO_AS_IN_INTERFACE 2 ++/* Number of streaming interfaces */ ++#define F_AUDIO_NUM_INTERFACES 2 + + /* B.3.1 Standard AC Interface Descriptor */ + static struct usb_interface_descriptor ac_interface_desc = { +@@ -42,93 +69,147 @@ static struct usb_interface_descriptor ac_interface_desc = { + .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL, + }; + ++ + /* + * The number of AudioStreaming and MIDIStreaming interfaces + * in the Audio Interface Collection + */ + DECLARE_UAC_AC_HEADER_DESCRIPTOR(1); ++#define UAC_DT_AC_HEADER_LENGTH_1 UAC_DT_AC_HEADER_SIZE(1) ++/* 1 input terminal, 1 output terminal */ ++#define UAC_DT_TOTAL_LENGTH_1 (UAC_DT_AC_HEADER_LENGTH_1 \ ++ + UAC_DT_INPUT_TERMINAL_SIZE + UAC_DT_FEATURE_UNIT_SIZE(0) \ ++ + UAC_DT_OUTPUT_TERMINAL_SIZE) ++/* B.3.2 Class-Specific AC Interface Descriptor */ ++static struct uac1_ac_header_descriptor_1 ac_header_desc_1 = { ++ .bLength = UAC_DT_AC_HEADER_LENGTH_1, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_HEADER, ++ .bcdADC = cpu_to_le16(0x0100), ++ .wTotalLength = cpu_to_le16(UAC_DT_TOTAL_LENGTH_1), ++ .bInCollection = 1, ++ .baInterfaceNr = { ++ /* Interface number of the first AudioStream interface */ ++ /* ++ [0] = F_AUDIO_AS_OUT_INTERFACE / F_AUDIO_AS_IN_INTERFACE, ++ */ ++ } ++}; + +-#define UAC_DT_AC_HEADER_LENGTH UAC_DT_AC_HEADER_SIZE(F_AUDIO_NUM_INTERFACES) +-/* 1 input terminal, 1 output terminal and 1 feature unit */ +-#define UAC_DT_TOTAL_LENGTH (UAC_DT_AC_HEADER_LENGTH + UAC_DT_INPUT_TERMINAL_SIZE \ +- + UAC_DT_OUTPUT_TERMINAL_SIZE + UAC_DT_FEATURE_UNIT_SIZE(0)) ++DECLARE_UAC_AC_HEADER_DESCRIPTOR(2); ++#define UAC_DT_AC_HEADER_LENGTH_2 UAC_DT_AC_HEADER_SIZE(2) ++/* 2 input terminal, 2 output terminal */ ++#define UAC_DT_TOTAL_LENGTH_2 (UAC_DT_AC_HEADER_LENGTH_2 \ ++ + 2*UAC_DT_INPUT_TERMINAL_SIZE + UAC_DT_FEATURE_UNIT_SIZE(0) \ ++ + 2*UAC_DT_OUTPUT_TERMINAL_SIZE) + /* B.3.2 Class-Specific AC Interface Descriptor */ +-static struct uac1_ac_header_descriptor_1 ac_header_desc = { +- .bLength = UAC_DT_AC_HEADER_LENGTH, ++static struct uac1_ac_header_descriptor_2 ac_header_desc_2 = { ++ .bLength = UAC_DT_AC_HEADER_LENGTH_2, + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubtype = UAC_HEADER, +- .bcdADC = __constant_cpu_to_le16(0x0100), +- .wTotalLength = __constant_cpu_to_le16(UAC_DT_TOTAL_LENGTH), +- .bInCollection = F_AUDIO_NUM_INTERFACES, ++ .bcdADC = cpu_to_le16(0x0100), ++ .wTotalLength = cpu_to_le16(UAC_DT_TOTAL_LENGTH_2), ++ .bInCollection = 2, + .baInterfaceNr = { + /* Interface number of the first AudioStream interface */ +- [0] = 1, ++ /* ++ [0] = F_AUDIO_AS_OUT_INTERFACE, ++ [1] = F_AUDIO_AS_IN_INTERFACE, ++ */ + } + }; + +-#define INPUT_TERMINAL_ID 1 +-static struct uac_input_terminal_descriptor input_terminal_desc = { ++ ++#define USB_OUT_IT_ID 1 ++#define IO_OUT_OT_ID 2 ++#define IO_IN_IT_ID 3 ++#define USB_IN_OT_ID 4 ++#define USB_IN_FU_ID 5 ++ ++static struct uac_input_terminal_descriptor usb_out_it_desc = { + .bLength = UAC_DT_INPUT_TERMINAL_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubtype = UAC_INPUT_TERMINAL, +- .bTerminalID = INPUT_TERMINAL_ID, +- .wTerminalType = UAC_TERMINAL_STREAMING, +- .bAssocTerminal = 0, +- .wChannelConfig = 0x3, ++ .bTerminalID = USB_OUT_IT_ID, ++ .wTerminalType = cpu_to_le16(UAC_TERMINAL_STREAMING), ++ .bAssocTerminal = IO_OUT_OT_ID, ++ .wChannelConfig = cpu_to_le16(0x3), + }; + +-DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(0); +- +-#define FEATURE_UNIT_ID 2 +-static struct uac_feature_unit_descriptor_0 feature_unit_desc = { +- .bLength = UAC_DT_FEATURE_UNIT_SIZE(0), ++static struct uac1_output_terminal_descriptor io_out_ot_desc = { ++ .bLength = UAC_DT_OUTPUT_TERMINAL_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubtype = UAC_FEATURE_UNIT, +- .bUnitID = FEATURE_UNIT_ID, +- .bSourceID = INPUT_TERMINAL_ID, +- .bControlSize = 2, +- .bmaControls[0] = (UAC_FU_MUTE | UAC_FU_VOLUME), +-}; +- +-static struct usb_audio_control mute_control = { +- .list = LIST_HEAD_INIT(mute_control.list), +- .name = "Mute Control", +- .type = UAC_FU_MUTE, +- /* Todo: add real Mute control code */ +- .set = generic_set_cmd, +- .get = generic_get_cmd, ++ .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, ++ .bTerminalID = IO_OUT_OT_ID, ++ .wTerminalType = cpu_to_le16(UAC_OUTPUT_TERMINAL_SPEAKER), ++ .bAssocTerminal = USB_OUT_IT_ID, ++ .bSourceID = USB_OUT_IT_ID, + }; + +-static struct usb_audio_control volume_control = { +- .list = LIST_HEAD_INIT(volume_control.list), +- .name = "Volume Control", ++static struct usb_audio_control playback_volume_control = { ++ .list = LIST_HEAD_INIT(playback_volume_control.list), ++ .name = "Playback Volume Control", + .type = UAC_FU_VOLUME, + /* Todo: add real Volume control code */ + .set = generic_set_cmd, + .get = generic_get_cmd, + }; + +-static struct usb_audio_control_selector feature_unit = { +- .list = LIST_HEAD_INIT(feature_unit.list), +- .id = FEATURE_UNIT_ID, +- .name = "Mute & Volume Control", +- .type = UAC_FEATURE_UNIT, +- .desc = (struct usb_descriptor_header *)&feature_unit_desc, ++static struct usb_audio_control_selector playback_fu_controls = { ++ .list = LIST_HEAD_INIT(playback_fu_controls.list), ++ .name = "Playback Function Unit Controls", + }; + +-#define OUTPUT_TERMINAL_ID 3 +-static struct uac1_output_terminal_descriptor output_terminal_desc = { +- .bLength = UAC_DT_OUTPUT_TERMINAL_SIZE, ++static struct uac_input_terminal_descriptor io_in_it_desc = { ++ .bLength = UAC_DT_INPUT_TERMINAL_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, +- .bTerminalID = OUTPUT_TERMINAL_ID, +- .wTerminalType = UAC_OUTPUT_TERMINAL_SPEAKER, +- .bAssocTerminal = FEATURE_UNIT_ID, +- .bSourceID = FEATURE_UNIT_ID, ++ .bDescriptorSubtype = UAC_INPUT_TERMINAL, ++ .bTerminalID = IO_IN_IT_ID, ++ .wTerminalType = cpu_to_le16(UAC_INPUT_TERMINAL_MICROPHONE), ++ .bAssocTerminal = 0, ++ .wChannelConfig = cpu_to_le16(0x3), ++}; ++ ++DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(0); ++ ++static struct uac_feature_unit_descriptor_0 usb_capture_fu_desc = { ++ .bLength = UAC_DT_FEATURE_UNIT_SIZE(0), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_FEATURE_UNIT, ++ .bUnitID = USB_IN_FU_ID, ++ .bSourceID = IO_IN_IT_ID, ++ .bControlSize = 1, ++ .bmaControls[0] = (UAC_FU_VOLUME), ++}; ++ ++static struct uac1_output_terminal_descriptor usb_in_ot_desc = { ++ .bLength = UAC_DT_OUTPUT_TERMINAL_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, ++ .bTerminalID = USB_IN_OT_ID, ++ .wTerminalType = cpu_to_le16(UAC_TERMINAL_STREAMING), ++ .bAssocTerminal = 0, ++ .bSourceID = USB_IN_FU_ID, ++}; ++ ++static struct usb_audio_control capture_volume_control = { ++ .list = LIST_HEAD_INIT(capture_volume_control.list), ++ .name = "Capture Volume Control", ++ .type = UAC_FU_VOLUME, ++ /* Todo: add real Volume control code */ ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++ ++static struct usb_audio_control_selector capture_fu_controls = { ++ .list = LIST_HEAD_INIT(capture_fu_controls.list), ++ .id = USB_IN_FU_ID, ++ .name = "Capture Mute & Volume Control", ++ .desc = (struct usb_descriptor_header *)&usb_in_ot_desc, + }; + + /* B.4.1 Standard AS Interface Descriptor */ +-static struct usb_interface_descriptor as_interface_alt_0_desc = { ++static struct usb_interface_descriptor as_out_interface_alt_0_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bAlternateSetting = 0, +@@ -137,7 +218,25 @@ static struct usb_interface_descriptor as_interface_alt_0_desc = { + .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, + }; + +-static struct usb_interface_descriptor as_interface_alt_1_desc = { ++static struct usb_interface_descriptor as_out_interface_alt_1_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bAlternateSetting = 1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, ++}; ++ ++static struct usb_interface_descriptor as_in_interface_alt_0_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, ++}; ++ ++static struct usb_interface_descriptor as_in_interface_alt_1_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bAlternateSetting = 1, +@@ -147,18 +246,27 @@ static struct usb_interface_descriptor as_interface_alt_1_desc = { + }; + + /* B.4.2 Class-Specific AS Interface Descriptor */ +-static struct uac1_as_header_descriptor as_header_desc = { ++static struct uac1_as_header_descriptor as_out_header_desc = { + .bLength = UAC_DT_AS_HEADER_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubtype = UAC_AS_GENERAL, +- .bTerminalLink = INPUT_TERMINAL_ID, ++ .bTerminalLink = USB_OUT_IT_ID, + .bDelay = 1, +- .wFormatTag = UAC_FORMAT_TYPE_I_PCM, ++ .wFormatTag = cpu_to_le16(UAC_FORMAT_TYPE_I_PCM), ++}; ++ ++static struct uac1_as_header_descriptor as_in_header_desc = { ++ .bLength = UAC_DT_AS_HEADER_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_AS_GENERAL, ++ .bTerminalLink = USB_IN_OT_ID, ++ .bDelay = 1, ++ .wFormatTag = cpu_to_le16(UAC_FORMAT_TYPE_I_PCM), + }; + + DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(1); + +-static struct uac_format_type_i_discrete_descriptor_1 as_type_i_desc = { ++static struct uac_format_type_i_discrete_descriptor_1 as_out_type_i_desc = { + .bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1), + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubtype = UAC_FORMAT_TYPE, +@@ -179,201 +287,274 @@ static struct usb_endpoint_descriptor as_out_ep_desc = { + .bInterval = 4, + }; + ++static struct usb_ss_ep_comp_descriptor ss_as_out_ep_comp_desc = { ++ .bLength = USB_DT_SS_EP_COMP_SIZE, ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++}; ++ + /* Class-specific AS ISO OUT Endpoint Descriptor */ + static struct uac_iso_endpoint_descriptor as_iso_out_desc = { + .bLength = UAC_ISO_ENDPOINT_DESC_SIZE, + .bDescriptorType = USB_DT_CS_ENDPOINT, + .bDescriptorSubtype = UAC_EP_GENERAL, +- .bmAttributes = 1, ++ .bmAttributes = 1, + .bLockDelayUnits = 1, +- .wLockDelay = __constant_cpu_to_le16(1), ++ .wLockDelay = cpu_to_le16(1), ++}; ++ ++static struct uac_format_type_i_discrete_descriptor_1 as_in_type_i_desc = { ++ .bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_FORMAT_TYPE, ++ .bFormatType = UAC_FORMAT_TYPE_I, ++ .bSubframeSize = 2, ++ .bBitResolution = 16, ++ .bSamFreqType = 1, ++}; ++ ++/* Standard ISO IN Endpoint Descriptor */ ++static struct usb_endpoint_descriptor as_in_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_AUDIO_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ .wMaxPacketSize = cpu_to_le16(UAC1_OUT_EP_MAX_PACKET_SIZE), ++ .bInterval = 4, ++}; ++ ++static struct usb_ss_ep_comp_descriptor ss_as_in_ep_comp_desc = { ++ .bLength = USB_DT_SS_EP_COMP_SIZE, ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, + }; + +-static struct usb_descriptor_header *f_audio_desc[] = { ++/* Class-specific AS ISO IN Endpoint Descriptor */ ++static struct uac_iso_endpoint_descriptor as_iso_in_desc = { ++ .bLength = UAC_ISO_ENDPOINT_DESC_SIZE, ++ .bDescriptorType = USB_DT_CS_ENDPOINT, ++ .bDescriptorSubtype = UAC_EP_GENERAL, ++ .bmAttributes = 1, ++ .bLockDelayUnits = 0, ++ .wLockDelay = 0, ++}; ++ ++static struct usb_interface_assoc_descriptor ++audio_iad_descriptor = { ++ .bLength = sizeof(audio_iad_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, ++ .bFirstInterface = 0, /* updated at bind */ ++ .bInterfaceCount = 3, ++ .bFunctionClass = USB_CLASS_AUDIO, ++ .bFunctionSubClass = 0, ++ .bFunctionProtocol = UAC_VERSION_1, ++}; ++ ++/* super-speed */ ++static struct usb_descriptor_header *f_audio_ss_desc_0[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, + (struct usb_descriptor_header *)&ac_interface_desc, +- (struct usb_descriptor_header *)&ac_header_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_1, + +- (struct usb_descriptor_header *)&input_terminal_desc, +- (struct usb_descriptor_header *)&output_terminal_desc, +- (struct usb_descriptor_header *)&feature_unit_desc, ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, + +- (struct usb_descriptor_header *)&as_interface_alt_0_desc, +- (struct usb_descriptor_header *)&as_interface_alt_1_desc, +- (struct usb_descriptor_header *)&as_header_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, + +- (struct usb_descriptor_header *)&as_type_i_desc, ++ (struct usb_descriptor_header *)&as_out_type_i_desc, + + (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&ss_as_out_ep_comp_desc, + (struct usb_descriptor_header *)&as_iso_out_desc, + NULL, + }; + +-enum { +- STR_AC_IF, +- STR_INPUT_TERMINAL, +- STR_INPUT_TERMINAL_CH_NAMES, +- STR_FEAT_DESC_0, +- STR_OUTPUT_TERMINAL, +- STR_AS_IF_ALT0, +- STR_AS_IF_ALT1, +-}; ++ static struct usb_descriptor_header *f_audio_ss_desc_1[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_1, + +-static struct usb_string strings_uac1[] = { +- [STR_AC_IF].s = "AC Interface", +- [STR_INPUT_TERMINAL].s = "Input terminal", +- [STR_INPUT_TERMINAL_CH_NAMES].s = "Channels", +- [STR_FEAT_DESC_0].s = "Volume control & mute", +- [STR_OUTPUT_TERMINAL].s = "Output terminal", +- [STR_AS_IF_ALT0].s = "AS Interface", +- [STR_AS_IF_ALT1].s = "AS Interface", +- { }, +-}; ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_capture_fu_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, + +-static struct usb_gadget_strings str_uac1 = { +- .language = 0x0409, /* en-us */ +- .strings = strings_uac1, +-}; ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, + +-static struct usb_gadget_strings *uac1_strings[] = { +- &str_uac1, ++ (struct usb_descriptor_header *)&as_in_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&ss_as_in_ep_comp_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, + NULL, + }; + +-/* +- * This function is an ALSA sound card following USB Audio Class Spec 1.0. +- */ ++static struct usb_descriptor_header *f_audio_ss_desc_2[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_2, + +-/*-------------------------------------------------------------------------*/ +-struct f_audio_buf { +- u8 *buf; +- int actual; +- struct list_head list; ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_capture_fu_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, ++ ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, ++ ++ (struct usb_descriptor_header *)&as_out_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&ss_as_out_ep_comp_desc, ++ (struct usb_descriptor_header *)&as_iso_out_desc, ++ ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, ++ ++ (struct usb_descriptor_header *)&as_in_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&ss_as_in_ep_comp_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, ++ NULL, + }; + +-static struct f_audio_buf *f_audio_buffer_alloc(int buf_size) +-{ +- struct f_audio_buf *copy_buf; ++/* high-speed */ ++static struct usb_descriptor_header *f_audio_desc_0[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_1, + +- copy_buf = kzalloc(sizeof *copy_buf, GFP_ATOMIC); +- if (!copy_buf) +- return ERR_PTR(-ENOMEM); ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, + +- copy_buf->buf = kzalloc(buf_size, GFP_ATOMIC); +- if (!copy_buf->buf) { +- kfree(copy_buf); +- return ERR_PTR(-ENOMEM); +- } ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, + +- return copy_buf; +-} ++ (struct usb_descriptor_header *)&as_out_type_i_desc, + +-static void f_audio_buffer_free(struct f_audio_buf *audio_buf) +-{ +- kfree(audio_buf->buf); +- kfree(audio_buf); +-} +-/*-------------------------------------------------------------------------*/ ++ (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_out_desc, ++ NULL, ++}; + +-struct f_audio { +- struct gaudio card; ++ static struct usb_descriptor_header *f_audio_desc_1[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_1, + +- /* endpoints handle full and/or high speeds */ +- struct usb_ep *out_ep; ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_capture_fu_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, + +- spinlock_t lock; +- struct f_audio_buf *copy_buf; +- struct work_struct playback_work; +- struct list_head play_queue; ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, + +- /* Control Set command */ +- struct list_head cs; +- u8 set_cmd; +- struct usb_audio_control *set_con; ++ (struct usb_descriptor_header *)&as_in_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, ++ NULL, + }; + +-static inline struct f_audio *func_to_audio(struct usb_function *f) +-{ +- return container_of(f, struct f_audio, card.func); +-} ++static struct usb_descriptor_header *f_audio_desc_2[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_2, + +-/*-------------------------------------------------------------------------*/ ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_capture_fu_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, + +-static void f_audio_playback_work(struct work_struct *data) +-{ +- struct f_audio *audio = container_of(data, struct f_audio, +- playback_work); +- struct f_audio_buf *play_buf; ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, + +- spin_lock_irq(&audio->lock); +- if (list_empty(&audio->play_queue)) { +- spin_unlock_irq(&audio->lock); +- return; +- } +- play_buf = list_first_entry(&audio->play_queue, +- struct f_audio_buf, list); +- list_del(&play_buf->list); +- spin_unlock_irq(&audio->lock); ++ (struct usb_descriptor_header *)&as_out_type_i_desc, + +- u_audio_playback(&audio->card, play_buf->buf, play_buf->actual); +- f_audio_buffer_free(play_buf); +-} ++ (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_out_desc, + +-static int f_audio_out_ep_complete(struct usb_ep *ep, struct usb_request *req) +-{ +- struct f_audio *audio = req->context; +- struct usb_composite_dev *cdev = audio->card.func.config->cdev; +- struct f_audio_buf *copy_buf = audio->copy_buf; +- struct f_uac1_opts *opts; +- int audio_buf_size; +- int err; ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, + +- opts = container_of(audio->card.func.fi, struct f_uac1_opts, +- func_inst); +- audio_buf_size = opts->audio_buf_size; ++ (struct usb_descriptor_header *)&as_in_type_i_desc, + +- if (!copy_buf) +- return -EINVAL; ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, ++ NULL, ++}; + +- /* Copy buffer is full, add it to the play_queue */ +- if (audio_buf_size - copy_buf->actual < req->actual) { +- list_add_tail(©_buf->list, &audio->play_queue); +- schedule_work(&audio->playback_work); +- copy_buf = f_audio_buffer_alloc(audio_buf_size); +- if (IS_ERR(copy_buf)) +- return -ENOMEM; +- } ++enum { ++ STR_AC_IF, ++ STR_USB_OUT_IT, ++ STR_USB_OUT_IT_CH_NAMES, ++ STR_IO_OUT_OT, ++ STR_IO_IN_IT, ++ STR_IO_IN_IT_CH_NAMES, ++ STR_USB_IN_OT, ++ STR_AS_OUT_IF_ALT0, ++ STR_AS_OUT_IF_ALT1, ++ STR_AS_IN_IF_ALT0, ++ STR_AS_IN_IF_ALT1, ++}; + +- memcpy(copy_buf->buf + copy_buf->actual, req->buf, req->actual); +- copy_buf->actual += req->actual; +- audio->copy_buf = copy_buf; ++static struct usb_string strings_uac1[] = { ++ [STR_AC_IF].s = "AC Interface", ++ [STR_USB_OUT_IT].s = "Playback Input terminal", ++ [STR_USB_OUT_IT_CH_NAMES].s = "Playback Channels", ++ [STR_IO_OUT_OT].s = "Playback Output terminal", ++ [STR_IO_IN_IT].s = "Capture Input terminal", ++ [STR_IO_IN_IT_CH_NAMES].s = "Capture Channels", ++ [STR_USB_IN_OT].s = "Capture Output terminal", ++ [STR_AS_OUT_IF_ALT0].s = "Playback Inactive", ++ [STR_AS_OUT_IF_ALT1].s = "Playback Active", ++ [STR_AS_IN_IF_ALT0].s = "Capture Inactive", ++ [STR_AS_IN_IF_ALT1].s = "Capture Active", ++ { }, ++}; + +- err = usb_ep_queue(ep, req, GFP_ATOMIC); +- if (err) +- ERROR(cdev, "%s queue req: %d\n", ep->name, err); ++static struct usb_gadget_strings str_uac1 = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings_uac1, ++}; + +- return 0; ++static struct usb_gadget_strings *uac1_strings[] = { ++ &str_uac1, ++ NULL, ++}; + +-} ++/* ++ * This function is an ALSA sound card following USB Audio Class Spec 1.0. ++ */ + + static void f_audio_complete(struct usb_ep *ep, struct usb_request *req) + { +- struct f_audio *audio = req->context; ++ struct f_uac1 *uac1 = req->context; + int status = req->status; + u32 data = 0; +- struct usb_ep *out_ep = audio->out_ep; + + switch (status) { +- + case 0: /* normal completion? */ +- if (ep == out_ep) +- f_audio_out_ep_complete(ep, req); +- else if (audio->set_con) { ++ if (uac1->set_con) { + memcpy(&data, req->buf, req->length); +- audio->set_con->set(audio->set_con, audio->set_cmd, ++ uac1->set_con->set(uac1->set_con, uac1->set_cmd, + le16_to_cpu(data)); +- audio->set_con = NULL; ++ uac1->set_con = NULL; + } ++ + break; ++ case -ESHUTDOWN: + default: + break; + } +@@ -382,7 +563,7 @@ static void f_audio_complete(struct usb_ep *ep, struct usb_request *req) + static int audio_set_intf_req(struct usb_function *f, + const struct usb_ctrlrequest *ctrl) + { +- struct f_audio *audio = func_to_audio(f); ++ struct f_uac1 *uac1 = func_to_uac1(f); + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_request *req = cdev->req; + u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); +@@ -396,11 +577,11 @@ static int audio_set_intf_req(struct usb_function *f, + DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n", + ctrl->bRequest, w_value, len, id); + +- list_for_each_entry(cs, &audio->cs, list) { ++ list_for_each_entry(cs, &uac1->cs, list) { + if (cs->id == id) { + list_for_each_entry(con, &cs->control, list) { + if (con->type == con_sel) { +- audio->set_con = con; ++ uac1->set_con = con; + break; + } + } +@@ -408,8 +589,8 @@ static int audio_set_intf_req(struct usb_function *f, + } + } + +- audio->set_cmd = cmd; +- req->context = audio; ++ uac1->set_cmd = cmd; ++ req->context = uac1; + req->complete = f_audio_complete; + + return len; +@@ -418,7 +599,7 @@ static int audio_set_intf_req(struct usb_function *f, + static int audio_get_intf_req(struct usb_function *f, + const struct usb_ctrlrequest *ctrl) + { +- struct f_audio *audio = func_to_audio(f); ++ struct f_uac1 *uac1 = func_to_uac1(f); + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_request *req = cdev->req; + int value = -EOPNOTSUPP; +@@ -433,7 +614,7 @@ static int audio_get_intf_req(struct usb_function *f, + DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n", + ctrl->bRequest, w_value, len, id); + +- list_for_each_entry(cs, &audio->cs, list) { ++ list_for_each_entry(cs, &uac1->cs, list) { + if (cs->id == id) { + list_for_each_entry(con, &cs->control, list) { + if (con->type == con_sel && con->get) { +@@ -445,7 +626,7 @@ static int audio_get_intf_req(struct usb_function *f, + } + } + +- req->context = audio; ++ req->context = uac1; + req->complete = f_audio_complete; + len = min_t(size_t, sizeof(value), len); + memcpy(req->buf, &value, len); +@@ -531,14 +712,6 @@ f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + * activation uses set_alt(). + */ + switch (ctrl->bRequestType) { +- case USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE: +- value = audio_set_intf_req(f, ctrl); +- break; +- +- case USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE: +- value = audio_get_intf_req(f, ctrl); +- break; +- + case USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_ENDPOINT: + value = audio_set_endpoint_req(f, ctrl); + break; +@@ -547,6 +720,14 @@ f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + value = audio_get_endpoint_req(f, ctrl); + break; + ++ case USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE: ++ value = audio_set_intf_req(f, ctrl); ++ break; ++ ++ case USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE: ++ value = audio_get_intf_req(f, ctrl); ++ break; ++ + default: + ERROR(cdev, "invalid control req%02x.%02x v%04x i%04x l%d\n", + ctrl->bRequestType, ctrl->bRequest, +@@ -571,198 +752,331 @@ f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + + static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt) + { +- struct f_audio *audio = func_to_audio(f); + struct usb_composite_dev *cdev = f->config->cdev; +- struct usb_ep *out_ep = audio->out_ep; +- struct usb_request *req; +- struct f_uac1_opts *opts; +- int req_buf_size, req_count, audio_buf_size; +- int i = 0, err = 0; +- +- DBG(cdev, "intf %d, alt %d\n", intf, alt); ++ struct usb_gadget *gadget = cdev->gadget; ++ struct device *dev = &gadget->dev; ++ struct f_uac1 *uac1 = func_to_uac1(f); ++ int ret = 0; ++ ++ /* No i/f has more than 2 alt settings */ ++ if (alt > 1) { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return -EINVAL; ++ } + +- opts = container_of(f->fi, struct f_uac1_opts, func_inst); +- req_buf_size = opts->req_buf_size; +- req_count = opts->req_count; +- audio_buf_size = opts->audio_buf_size; +- +- if (intf == 1) { +- if (alt == 1) { +- err = config_ep_by_speed(cdev->gadget, f, out_ep); +- if (err) +- return err; +- +- usb_ep_enable(out_ep); +- audio->copy_buf = f_audio_buffer_alloc(audio_buf_size); +- if (IS_ERR(audio->copy_buf)) +- return -ENOMEM; +- +- /* +- * allocate a bunch of read buffers +- * and queue them all at once. +- */ +- for (i = 0; i < req_count && err == 0; i++) { +- req = usb_ep_alloc_request(out_ep, GFP_ATOMIC); +- if (req) { +- req->buf = kzalloc(req_buf_size, +- GFP_ATOMIC); +- if (req->buf) { +- req->length = req_buf_size; +- req->context = audio; +- req->complete = +- f_audio_complete; +- err = usb_ep_queue(out_ep, +- req, GFP_ATOMIC); +- if (err) +- ERROR(cdev, +- "%s queue req: %d\n", +- out_ep->name, err); +- } else +- err = -ENOMEM; +- } else +- err = -ENOMEM; +- } ++ if (intf == uac1->ac_intf) { ++ /* Control I/f has only 1 AltSetting - 0 */ ++ if (alt) { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return -EINVAL; ++ } ++ return 0; ++ } + +- } else { +- struct f_audio_buf *copy_buf = audio->copy_buf; +- if (copy_buf) { +- list_add_tail(©_buf->list, +- &audio->play_queue); +- schedule_work(&audio->playback_work); +- } ++ if (intf == uac1->as_out_intf) { ++ if (alt && uac1->as_out_alt == alt) { ++ printk(KERN_DEBUG"force reset intf %d alt %d", intf, alt); ++ u_audio_stop_capture(&uac1->g_audio); ++ } ++ uac1->as_out_alt = alt; ++ ++ if (alt) ++ ret = u_audio_start_capture(&uac1->g_audio); ++ else ++ u_audio_stop_capture(&uac1->g_audio); ++ } else if (intf == uac1->as_in_intf) { ++ if (alt && uac1->as_in_alt == alt) { ++ printk(KERN_DEBUG"force reset intf %d alt %d", intf, alt); ++ u_audio_stop_playback(&uac1->g_audio); + } ++ uac1->as_in_alt = alt; ++ ++ if (alt) ++ ret = u_audio_start_playback(&uac1->g_audio); ++ else ++ u_audio_stop_playback(&uac1->g_audio); ++ } else { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return -EINVAL; + } + +- return err; ++ return ret; + } + +-static void f_audio_disable(struct usb_function *f) ++static int f_audio_get_alt(struct usb_function *f, unsigned intf) + { +- return; ++ struct usb_composite_dev *cdev = f->config->cdev; ++ struct usb_gadget *gadget = cdev->gadget; ++ struct device *dev = &gadget->dev; ++ struct f_uac1 *uac1 = func_to_uac1(f); ++ ++ if (intf == uac1->ac_intf) ++ return uac1->ac_alt; ++ else if (intf == uac1->as_out_intf) ++ return uac1->as_out_alt; ++ else if (intf == uac1->as_in_intf) ++ return uac1->as_in_alt; ++ else ++ dev_err(dev, "%s:%d Invalid Interface %d!\n", ++ __func__, __LINE__, intf); ++ ++ return -EINVAL; + } + +-/*-------------------------------------------------------------------------*/ + +-static void f_audio_build_desc(struct f_audio *audio) ++static void f_audio_disable(struct usb_function *f) + { +- struct gaudio *card = &audio->card; +- u8 *sam_freq; +- int rate; ++ struct f_uac1 *uac1 = func_to_uac1(f); + +- /* Set channel numbers */ +- input_terminal_desc.bNrChannels = u_audio_get_playback_channels(card); +- as_type_i_desc.bNrChannels = u_audio_get_playback_channels(card); +- +- /* Set sample rates */ +- rate = u_audio_get_playback_rate(card); +- sam_freq = as_type_i_desc.tSamFreq[0]; +- memcpy(sam_freq, &rate, 3); +- +- /* Todo: Set Sample bits and other parameters */ ++ uac1->as_out_alt = 0; ++ uac1->as_in_alt = 0; + +- return; ++ u_audio_stop_capture(&uac1->g_audio); + } + ++/*-------------------------------------------------------------------------*/ ++ + /* audio function driver setup/binding */ +-static int +-f_audio_bind(struct usb_configuration *c, struct usb_function *f) ++static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) + { +- struct usb_composite_dev *cdev = c->cdev; +- struct f_audio *audio = func_to_audio(f); +- struct usb_string *us; +- int status; +- struct usb_ep *ep = NULL; +- struct f_uac1_opts *audio_opts; ++ static struct usb_descriptor_header **f_audio_desc = NULL; ++ static struct usb_descriptor_header **f_audio_ss_desc = NULL; //super-speed ++ struct usb_composite_dev *cdev = c->cdev; ++ struct usb_gadget *gadget = cdev->gadget; ++ struct f_uac1 *uac1 = func_to_uac1(f); ++ struct g_audio *audio = func_to_g_audio(f); ++ struct f_uac1_opts *audio_opts; ++ struct usb_ep *ep = NULL; ++ struct usb_string *us; ++ u8 *sam_freq; ++ int rate; ++ int status; + + audio_opts = container_of(f->fi, struct f_uac1_opts, func_inst); +- audio->card.gadget = c->cdev->gadget; +- /* set up ASLA audio devices */ +- if (!audio_opts->bound) { +- status = gaudio_setup(&audio->card); +- if (status < 0) +- return status; +- audio_opts->bound = true; ++ ++ /* Sanity check the streaming endpoint module parameters. ++ */ ++ audio_opts->c_mpsize = audio_opts->c_mpsize > 1024?1024:audio_opts->c_mpsize; ++ audio_opts->p_mpsize = audio_opts->p_mpsize > 1024?1024:audio_opts->p_mpsize; ++ ++ as_out_ep_desc.wMaxPacketSize = cpu_to_le16(audio_opts->c_mpsize); ++ as_in_ep_desc.wMaxPacketSize = cpu_to_le16(audio_opts->p_mpsize); ++ ++ /* super-speed */ ++ if(gadget_is_superspeed(gadget)) ++ { ++ ss_as_out_ep_comp_desc.bmAttributes = cpu_to_le16(0); ++ ss_as_out_ep_comp_desc.bMaxBurst = cpu_to_le16(0); ++ ss_as_out_ep_comp_desc.wBytesPerInterval = cpu_to_le16(as_out_ep_desc.wMaxPacketSize); ++ ss_as_in_ep_comp_desc.bmAttributes = cpu_to_le16(0); ++ ss_as_in_ep_comp_desc.bMaxBurst = cpu_to_le16(0); ++ ss_as_in_ep_comp_desc.wBytesPerInterval = cpu_to_le16(as_in_ep_desc.wMaxPacketSize); + } ++ + us = usb_gstrings_attach(cdev, uac1_strings, ARRAY_SIZE(strings_uac1)); + if (IS_ERR(us)) + return PTR_ERR(us); + ac_interface_desc.iInterface = us[STR_AC_IF].id; +- input_terminal_desc.iTerminal = us[STR_INPUT_TERMINAL].id; +- input_terminal_desc.iChannelNames = us[STR_INPUT_TERMINAL_CH_NAMES].id; +- feature_unit_desc.iFeature = us[STR_FEAT_DESC_0].id; +- output_terminal_desc.iTerminal = us[STR_OUTPUT_TERMINAL].id; +- as_interface_alt_0_desc.iInterface = us[STR_AS_IF_ALT0].id; +- as_interface_alt_1_desc.iInterface = us[STR_AS_IF_ALT1].id; ++ usb_out_it_desc.iTerminal = us[STR_USB_OUT_IT].id; ++ usb_out_it_desc.iChannelNames = us[STR_USB_OUT_IT_CH_NAMES].id; ++ io_out_ot_desc.iTerminal = us[STR_IO_OUT_OT].id; ++ as_out_interface_alt_0_desc.iInterface = us[STR_AS_OUT_IF_ALT0].id; ++ as_out_interface_alt_1_desc.iInterface = us[STR_AS_OUT_IF_ALT1].id; ++ io_in_it_desc.iTerminal = us[STR_IO_IN_IT].id; ++ io_in_it_desc.iChannelNames = us[STR_IO_IN_IT_CH_NAMES].id; ++ usb_in_ot_desc.iTerminal = us[STR_USB_IN_OT].id; ++ as_in_interface_alt_0_desc.iInterface = us[STR_AS_IN_IF_ALT0].id; ++ as_in_interface_alt_1_desc.iInterface = us[STR_AS_IN_IF_ALT1].id; + ++ /* Set channel numbers */ ++ usb_out_it_desc.bNrChannels = num_channels(audio_opts->c_chmask); ++ usb_out_it_desc.wChannelConfig = cpu_to_le16(audio_opts->c_chmask); ++ as_out_type_i_desc.bNrChannels = num_channels(audio_opts->c_chmask); ++ as_out_type_i_desc.bSubframeSize = audio_opts->c_ssize; ++ as_out_type_i_desc.bBitResolution = audio_opts->c_ssize * 8; ++ io_in_it_desc.bNrChannels = num_channels(audio_opts->p_chmask); ++ io_in_it_desc.wChannelConfig = cpu_to_le16(audio_opts->p_chmask); ++ as_in_type_i_desc.bNrChannels = num_channels(audio_opts->p_chmask); ++ as_in_type_i_desc.bSubframeSize = audio_opts->p_ssize; ++ as_in_type_i_desc.bBitResolution = audio_opts->p_ssize * 8; + +- f_audio_build_desc(audio); ++ /* Set sample rates */ ++ rate = audio_opts->c_srate; ++ sam_freq = as_out_type_i_desc.tSamFreq[0]; ++ memcpy(sam_freq, &rate, 3); ++ rate = audio_opts->p_srate; ++ sam_freq = as_in_type_i_desc.tSamFreq[0]; ++ memcpy(sam_freq, &rate, 3); + + /* allocate instance-specific interface IDs, and patch descriptors */ + status = usb_interface_id(c, f); + if (status < 0) + goto fail; + ac_interface_desc.bInterfaceNumber = status; ++ audio_iad_descriptor.bFirstInterface = status; ++ uac1->ac_intf = status; ++ uac1->ac_alt = 0; + +- status = usb_interface_id(c, f); +- if (status < 0) +- goto fail; +- as_interface_alt_0_desc.bInterfaceNumber = status; +- as_interface_alt_1_desc.bInterfaceNumber = status; ++ if(ENABLE_SPEAKER == audio_opts->audio_play_mode) ++ { ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ as_out_interface_alt_0_desc.bInterfaceNumber = status; ++ as_out_interface_alt_1_desc.bInterfaceNumber = status; ++ ac_header_desc_1.baInterfaceNr[0] = status; ++ uac1->as_out_intf = status; ++ uac1->as_out_alt = 0; ++ } ++ ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode) ++ { ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ as_in_interface_alt_0_desc.bInterfaceNumber = status; ++ as_in_interface_alt_1_desc.bInterfaceNumber = status; ++ ac_header_desc_1.baInterfaceNr[0] = status; ++ uac1->as_in_intf = status; ++ uac1->as_in_alt = 0; ++ } ++ ++ if(ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode) ++ { ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ as_out_interface_alt_0_desc.bInterfaceNumber = status; ++ as_out_interface_alt_1_desc.bInterfaceNumber = status; ++ ac_header_desc_2.baInterfaceNr[0] = status; ++ uac1->as_out_intf = status; ++ uac1->as_out_alt = 0; ++ ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ as_in_interface_alt_0_desc.bInterfaceNumber = status; ++ as_in_interface_alt_1_desc.bInterfaceNumber = status; ++ ac_header_desc_2.baInterfaceNr[1] = status; ++ uac1->as_in_intf = status; ++ uac1->as_in_alt = 0; ++ } ++ ++ audio->gadget = gadget; + + status = -ENODEV; + +- /* allocate instance-specific endpoints */ +- ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc); +- if (!ep) +- goto fail; +- audio->out_ep = ep; +- audio->out_ep->desc = &as_out_ep_desc; ++ if(gadget_is_superspeed(gadget)) ++ { ++ /* allocate instance-specific endpoints */ ++ if(ENABLE_SPEAKER == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++ { ++ ep = usb_ep_autoconfig_ss(cdev->gadget, &as_out_ep_desc, &ss_as_in_ep_comp_desc); ++ if (!ep) ++ goto fail; ++ audio->out_ep = ep; ++ audio->out_ep->desc = &as_out_ep_desc; ++ audio->out_ep->comp_desc = &ss_as_out_ep_comp_desc; ++ } ++ ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++ { ++ ep = usb_ep_autoconfig_ss(cdev->gadget, &as_in_ep_desc, &ss_as_in_ep_comp_desc); ++ if (!ep) ++ goto fail; ++ audio->in_ep = ep; ++ audio->in_ep->desc = &as_in_ep_desc; ++ audio->in_ep->comp_desc = &ss_as_in_ep_comp_desc; ++ } ++ } ++ else ++ { ++ /* allocate instance-specific endpoints */ ++ if(ENABLE_SPEAKER == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++ { ++ ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc); ++ if (!ep) ++ goto fail; ++ audio->out_ep = ep; ++ audio->out_ep->desc = &as_out_ep_desc; ++ } ++ ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++ { ++ ep = usb_ep_autoconfig(cdev->gadget, &as_in_ep_desc); ++ if (!ep) ++ goto fail; ++ audio->in_ep = ep; ++ audio->in_ep->desc = &as_in_ep_desc; ++ } ++ } ++ ++ ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode) ++ { ++ audio_iad_descriptor.bInterfaceCount = 2; ++ ++ if(gadget_is_superspeed(gadget)) ++ f_audio_ss_desc = f_audio_ss_desc_1; ++ ++ f_audio_desc = f_audio_desc_1; ++ ++ } ++ else if(ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode) ++ { ++ audio_iad_descriptor.bInterfaceCount = 3; + +- status = -ENOMEM; ++ if(gadget_is_superspeed(gadget)) ++ f_audio_ss_desc = f_audio_ss_desc_2; ++ ++ f_audio_desc = f_audio_desc_2; ++ ++ } ++ else if (ENABLE_SPEAKER == audio_opts->audio_play_mode) ++ { ++ audio_iad_descriptor.bInterfaceCount = 2; ++ ++ if(gadget_is_superspeed(gadget)) ++ f_audio_ss_desc = f_audio_ss_desc_0; ++ ++ f_audio_desc = f_audio_desc_0; ++ ++ } + + /* copy descriptors, and track endpoint copies */ +- status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, NULL, ++ status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, f_audio_ss_desc, + NULL); + if (status) + goto fail; +- return 0; + +-fail: +- gaudio_cleanup(&audio->card); +- return status; +-} ++ audio->out_ep_maxpsize = le16_to_cpu(as_out_ep_desc.wMaxPacketSize); ++ audio->in_ep_maxpsize = le16_to_cpu(as_in_ep_desc.wMaxPacketSize); + +-/*-------------------------------------------------------------------------*/ ++ audio->params.c_chmask = audio_opts->c_chmask; ++ audio->params.c_srate = audio_opts->c_srate; ++ audio->params.c_ssize = audio_opts->c_ssize; ++ audio->params.p_chmask = audio_opts->p_chmask; ++ audio->params.p_srate = audio_opts->p_srate; ++ audio->params.p_ssize = audio_opts->p_ssize; ++ audio->params.req_number = audio_opts->req_number; + +-static int generic_set_cmd(struct usb_audio_control *con, u8 cmd, int value) +-{ +- con->data[cmd] = value; ++ status = g_audio_setup(audio, "UAC1_PCM", "UAC1_Gadget"); ++ if (status) ++ goto err_card_register; + + return 0; +-} + +-static int generic_get_cmd(struct usb_audio_control *con, u8 cmd) +-{ +- return con->data[cmd]; ++err_card_register: ++ usb_free_all_descriptors(f); ++fail: ++ return status; + } + +-/* Todo: add more control selecotor dynamically */ +-static int control_selector_init(struct f_audio *audio) +-{ +- INIT_LIST_HEAD(&audio->cs); +- list_add(&feature_unit.list, &audio->cs); +- +- INIT_LIST_HEAD(&feature_unit.control); +- list_add(&mute_control.list, &feature_unit.control); +- list_add(&volume_control.list, &feature_unit.control); +- +- volume_control.data[UAC__CUR] = 0xffc0; +- volume_control.data[UAC__MIN] = 0xe3a0; +- volume_control.data[UAC__MAX] = 0xfff0; +- volume_control.data[UAC__RES] = 0x0030; +- +- return 0; +-} ++/*-------------------------------------------------------------------------*/ + + static inline struct f_uac1_opts *to_f_uac1_opts(struct config_item *item) + { +@@ -781,9 +1095,10 @@ static struct configfs_item_operations f_uac1_item_ops = { + .release = f_uac1_attr_release, + }; + +-#define UAC1_INT_ATTRIBUTE(name) \ +-static ssize_t f_uac1_opts_##name##_show(struct config_item *item, \ +- char *page) \ ++#define UAC1_ATTRIBUTE(name) \ ++static ssize_t f_uac1_opts_##name##_show( \ ++ struct config_item *item, \ ++ char *page) \ + { \ + struct f_uac1_opts *opts = to_f_uac1_opts(item); \ + int result; \ +@@ -795,7 +1110,8 @@ static ssize_t f_uac1_opts_##name##_show(struct config_item *item, \ + return result; \ + } \ + \ +-static ssize_t f_uac1_opts_##name##_store(struct config_item *item, \ ++static ssize_t f_uac1_opts_##name##_store( \ ++ struct config_item *item, \ + const char *page, size_t len) \ + { \ + struct f_uac1_opts *opts = to_f_uac1_opts(item); \ +@@ -822,64 +1138,26 @@ end: \ + \ + CONFIGFS_ATTR(f_uac1_opts_, name) + +-UAC1_INT_ATTRIBUTE(req_buf_size); +-UAC1_INT_ATTRIBUTE(req_count); +-UAC1_INT_ATTRIBUTE(audio_buf_size); +- +-#define UAC1_STR_ATTRIBUTE(name) \ +-static ssize_t f_uac1_opts_##name##_show(struct config_item *item, \ +- char *page) \ +-{ \ +- struct f_uac1_opts *opts = to_f_uac1_opts(item); \ +- int result; \ +- \ +- mutex_lock(&opts->lock); \ +- result = sprintf(page, "%s\n", opts->name); \ +- mutex_unlock(&opts->lock); \ +- \ +- return result; \ +-} \ +- \ +-static ssize_t f_uac1_opts_##name##_store(struct config_item *item, \ +- const char *page, size_t len) \ +-{ \ +- struct f_uac1_opts *opts = to_f_uac1_opts(item); \ +- int ret = -EBUSY; \ +- char *tmp; \ +- \ +- mutex_lock(&opts->lock); \ +- if (opts->refcnt) \ +- goto end; \ +- \ +- tmp = kstrndup(page, len, GFP_KERNEL); \ +- if (tmp) { \ +- ret = -ENOMEM; \ +- goto end; \ +- } \ +- if (opts->name##_alloc) \ +- kfree(opts->name); \ +- opts->name##_alloc = true; \ +- opts->name = tmp; \ +- ret = len; \ +- \ +-end: \ +- mutex_unlock(&opts->lock); \ +- return ret; \ +-} \ +- \ +-CONFIGFS_ATTR(f_uac1_opts_, name) +- +-UAC1_STR_ATTRIBUTE(fn_play); +-UAC1_STR_ATTRIBUTE(fn_cap); +-UAC1_STR_ATTRIBUTE(fn_cntl); ++UAC1_ATTRIBUTE(c_mpsize); ++UAC1_ATTRIBUTE(c_chmask); ++UAC1_ATTRIBUTE(c_srate); ++UAC1_ATTRIBUTE(c_ssize); ++UAC1_ATTRIBUTE(p_mpsize); ++UAC1_ATTRIBUTE(p_chmask); ++UAC1_ATTRIBUTE(p_srate); ++UAC1_ATTRIBUTE(p_ssize); ++UAC1_ATTRIBUTE(req_number); + + static struct configfs_attribute *f_uac1_attrs[] = { +- &f_uac1_opts_attr_req_buf_size, +- &f_uac1_opts_attr_req_count, +- &f_uac1_opts_attr_audio_buf_size, +- &f_uac1_opts_attr_fn_play, +- &f_uac1_opts_attr_fn_cap, +- &f_uac1_opts_attr_fn_cntl, ++ &f_uac1_opts_attr_c_mpsize, ++ &f_uac1_opts_attr_c_chmask, ++ &f_uac1_opts_attr_c_srate, ++ &f_uac1_opts_attr_c_ssize, ++ &f_uac1_opts_attr_p_mpsize, ++ &f_uac1_opts_attr_p_chmask, ++ &f_uac1_opts_attr_p_srate, ++ &f_uac1_opts_attr_p_ssize, ++ &f_uac1_opts_attr_req_number, + NULL, + }; + +@@ -894,12 +1172,6 @@ static void f_audio_free_inst(struct usb_function_instance *f) + struct f_uac1_opts *opts; + + opts = container_of(f, struct f_uac1_opts, func_inst); +- if (opts->fn_play_alloc) +- kfree(opts->fn_play); +- if (opts->fn_cap_alloc) +- kfree(opts->fn_cap); +- if (opts->fn_cntl_alloc) +- kfree(opts->fn_cntl); + kfree(opts); + } + +@@ -917,23 +1189,34 @@ static struct usb_function_instance *f_audio_alloc_inst(void) + config_group_init_type_name(&opts->func_inst.group, "", + &f_uac1_func_type); + +- opts->req_buf_size = UAC1_OUT_EP_MAX_PACKET_SIZE; +- opts->req_count = UAC1_REQ_COUNT; +- opts->audio_buf_size = UAC1_AUDIO_BUF_SIZE; +- opts->fn_play = FILE_PCM_PLAYBACK; +- opts->fn_cap = FILE_PCM_CAPTURE; +- opts->fn_cntl = FILE_CONTROL; ++ opts->c_mpsize = UAC1_OUT_EP_MAX_PACKET_SIZE; ++ opts->c_chmask = UAC1_DEF_CCHMASK; ++ opts->c_srate = UAC1_DEF_CSRATE; ++ opts->c_ssize = UAC1_DEF_CSSIZE; ++ opts->p_mpsize = UAC1_OUT_EP_MAX_PACKET_SIZE; ++ opts->p_chmask = UAC1_DEF_PCHMASK; ++ opts->p_srate = UAC1_DEF_PSRATE; ++ opts->p_ssize = UAC1_DEF_PSSIZE; ++ opts->req_number = UAC1_DEF_REQ_NUM; ++ + return &opts->func_inst; + } + + static void f_audio_free(struct usb_function *f) + { +- struct f_audio *audio = func_to_audio(f); ++ struct g_audio *audio; + struct f_uac1_opts *opts; + +- gaudio_cleanup(&audio->card); ++ struct f_uac1 *uac1 = func_to_uac1(f); ++ if (g_f_uac1 !=uac1) ++ return; ++ ++ audio = func_to_g_audio(f); + opts = container_of(f->fi, struct f_uac1_opts, func_inst); + kfree(audio); ++ ++ uac1 = NULL; ++ + mutex_lock(&opts->lock); + --opts->refcnt; + mutex_unlock(&opts->lock); +@@ -941,42 +1224,119 @@ static void f_audio_free(struct usb_function *f) + + static void f_audio_unbind(struct usb_configuration *c, struct usb_function *f) + { ++ struct g_audio *audio = func_to_g_audio(f); ++ ++ g_audio_cleanup(audio); + usb_free_all_descriptors(f); ++ ++ audio->gadget = NULL; ++} ++ ++static void mixer_cmd_work(struct work_struct *data) ++{ ++ struct f_uac1 *uac1 = g_f_uac1; ++ struct usb_audio_control *con = uac1->ready_con; ++ int value = uac1->ready_value; ++ ++ if (!con) ++ return; ++ ++ switch (con->type) ++ { ++ case UAC_FU_VOLUME: ++ uac1->g_audio.volume = UAC_VOLUME_ATTR_TO_DB(value); ++ g_audio_notify(&uac1->g_audio); ++ break; ++ default: ++ break; ++ } ++ ++ uac1->ready_con = NULL; ++} ++ ++static int generic_set_cmd(struct usb_audio_control *con, u8 cmd, int value) ++{ ++ struct f_uac1 *uac1 = g_f_uac1; ++ if (!uac1) ++ return -EINVAL; ++ ++ if (uac1->ready_con) ++ return -EINVAL; ++ ++ uac1->ready_con = con; ++ uac1->ready_cmd = cmd; ++ uac1->ready_value = value; ++ ++ con->data[cmd] = value; ++ schedule_work(&uac1->cmd_work); ++ return 0; ++} ++ ++static int generic_get_cmd(struct usb_audio_control *con, u8 cmd) ++{ ++ return con->data[cmd]; ++} ++ ++static int control_selector_init(struct f_uac1 *uac1) ++{ ++ INIT_LIST_HEAD(&uac1->cs); ++ list_add(&capture_fu_controls.list,&uac1->cs); ++ list_add(&playback_fu_controls.list,&uac1->cs); ++ ++ INIT_LIST_HEAD(&capture_fu_controls.control); ++ list_add(&capture_volume_control.list, ++ &capture_fu_controls.control); ++ ++ INIT_LIST_HEAD(&playback_fu_controls.control); ++ list_add(&playback_volume_control.list, ++ &playback_fu_controls.control); ++ ++ capture_volume_control.data[UAC__CUR] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_CUR); ++ capture_volume_control.data[UAC__MIN] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_MIN); ++ capture_volume_control.data[UAC__MAX] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_MAX); ++ capture_volume_control.data[UAC__RES] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_STEP); ++ playback_volume_control.data[UAC__CUR] = 0xffc0; ++ playback_volume_control.data[UAC__MIN] = 0xe3a0; ++ playback_volume_control.data[UAC__MAX] = 0xfff0; ++ playback_volume_control.data[UAC__RES] = 0x0030; ++ ++ return 0; + } + + static struct usb_function *f_audio_alloc(struct usb_function_instance *fi) + { +- struct f_audio *audio; ++ struct f_uac1 *uac1; + struct f_uac1_opts *opts; + ++ if (g_f_uac1) ++ return ERR_PTR(-EAGAIN); ++ + /* allocate and initialize one new instance */ +- audio = kzalloc(sizeof(*audio), GFP_KERNEL); +- if (!audio) ++ uac1 = kzalloc(sizeof(*uac1), GFP_KERNEL); ++ if (!uac1) + return ERR_PTR(-ENOMEM); + +- audio->card.func.name = "g_audio"; +- + opts = container_of(fi, struct f_uac1_opts, func_inst); + mutex_lock(&opts->lock); + ++opts->refcnt; + mutex_unlock(&opts->lock); +- INIT_LIST_HEAD(&audio->play_queue); +- spin_lock_init(&audio->lock); +- +- audio->card.func.bind = f_audio_bind; +- audio->card.func.unbind = f_audio_unbind; +- audio->card.func.set_alt = f_audio_set_alt; +- audio->card.func.setup = f_audio_setup; +- audio->card.func.disable = f_audio_disable; +- audio->card.func.free_func = f_audio_free; + +- control_selector_init(audio); ++ uac1->g_audio.func.name = "uac1_func"; ++ uac1->g_audio.func.bind = f_audio_bind; ++ uac1->g_audio.func.unbind = f_audio_unbind; ++ uac1->g_audio.func.set_alt = f_audio_set_alt; ++ uac1->g_audio.func.get_alt = f_audio_get_alt; ++ uac1->g_audio.func.setup = f_audio_setup; ++ uac1->g_audio.func.disable = f_audio_disable; ++ uac1->g_audio.func.free_func = f_audio_free; + +- INIT_WORK(&audio->playback_work, f_audio_playback_work); ++ control_selector_init(uac1); ++ INIT_WORK(&uac1->cmd_work, mixer_cmd_work); ++ g_f_uac1 = uac1; + +- return &audio->card.func; ++ return &uac1->g_audio.func; + } + + DECLARE_USB_FUNCTION_INIT(uac1, f_audio_alloc_inst, f_audio_alloc); + MODULE_LICENSE("GPL"); +-MODULE_AUTHOR("Bryan Wu"); ++MODULE_AUTHOR("Ruslan Bilovol"); +diff --git a/drivers/usb/gadget/function/f_uac1_legacy.c b/drivers/usb/gadget/function/f_uac1_legacy.c +new file mode 100755 +index 000000000000..4a997f766596 +--- /dev/null ++++ b/drivers/usb/gadget/function/f_uac1_legacy.c +@@ -0,0 +1,1768 @@ ++/* ++ * f_audio.c -- USB Audio class function driver ++ * ++ * Copyright (C) 2008 Bryan Wu ++ * Copyright (C) 2008 Analog Devices, Inc ++ * ++ * Enter bugs at http://blackfin.uclinux.org/ ++ * ++ * Licensed under the GPL-2 or later. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "u_uac1_legacy.h" ++ ++static int generic_set_cmd(struct usb_audio_control *con, u8 cmd, int value); ++static int generic_get_cmd(struct usb_audio_control *con, u8 cmd); ++ ++#define USB_OUT_IT_ID 1 ++#define IO_OUT_OT_ID 2 ++#define IO_IN_IT_ID 3 ++#define USB_IN_OT_ID 4 ++#define USB_IN_FU_ID 5 ++ ++/* ++ * DESCRIPTORS ... most are static, but strings and full ++ * configuration descriptors are built on demand. ++ */ ++ ++/* ++ * We have three interfaces - one AudioControl and two AudioStreaming ++ * ++ * The driver implements a simple UAC_1 topology. ++ * USB-OUT -> IT_1 -> OT_2 -> ALSA_Capture ++ * ALSA_Playback -> IT_3 -> OT_4 -> USB-IN ++ */ ++#define F_AUDIO_AC_INTERFACE 0 ++/* this two index for interface ,no id */ ++#define F_AUDIO_AS_OUT_INTERFACE 0 ++#define F_AUDIO_AS_IN_INTERFACE 1 ++/* Number of streaming interfaces */ ++#define F_AUDIO_NUM_INTERFACES 2 ++ ++/* B.3.1 Standard AC Interface Descriptor */ ++static struct usb_interface_descriptor ac_interface_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL, ++}; ++ ++/* ++ * The number of AudioStreaming and MIDIStreaming interfaces ++ * in the Audio Interface Collection ++ */ ++DECLARE_UAC_AC_HEADER_DESCRIPTOR(1); ++#define UAC_DT_AC_HEADER_LENGTH_1 UAC_DT_AC_HEADER_SIZE(1) ++/* 1 input terminal, 1 output terminal */ ++#define UAC_DT_TOTAL_LENGTH_1 (UAC_DT_AC_HEADER_LENGTH_1 \ ++ + UAC_DT_INPUT_TERMINAL_SIZE + UAC_DT_FEATURE_UNIT_SIZE(0) \ ++ + UAC_DT_OUTPUT_TERMINAL_SIZE) ++/* B.3.2 Class-Specific AC Interface Descriptor */ ++static struct uac1_ac_header_descriptor_1 ac_header_desc_1 = { ++ .bLength = UAC_DT_AC_HEADER_LENGTH_1, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_HEADER, ++ .bcdADC = cpu_to_le16(0x0100), ++ .wTotalLength = cpu_to_le16(UAC_DT_TOTAL_LENGTH_1), ++ .bInCollection = 1, ++ .baInterfaceNr = { ++ /* Interface number of the first AudioStream interface */ ++ /* ++ [0] = F_AUDIO_AS_OUT_INTERFACE / F_AUDIO_AS_IN_INTERFACE, ++ */ ++ } ++}; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++DECLARE_UAC_AC_HEADER_DESCRIPTOR(2); ++#define UAC_DT_AC_HEADER_LENGTH_2 UAC_DT_AC_HEADER_SIZE(2) ++/* 2 input terminal, 2 output terminal */ ++#define UAC_DT_TOTAL_LENGTH_2 (UAC_DT_AC_HEADER_LENGTH_2 \ ++ + 2*UAC_DT_INPUT_TERMINAL_SIZE + UAC_DT_FEATURE_UNIT_SIZE(0) \ ++ + 2*UAC_DT_OUTPUT_TERMINAL_SIZE) ++/* B.3.2 Class-Specific AC Interface Descriptor */ ++static struct uac1_ac_header_descriptor_2 ac_header_desc_2 = { ++ .bLength = UAC_DT_AC_HEADER_LENGTH_2, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_HEADER, ++ .bcdADC = cpu_to_le16(0x0100), ++ .wTotalLength = cpu_to_le16(UAC_DT_TOTAL_LENGTH_2), ++ .bInCollection = 2, ++ .baInterfaceNr = { ++ /* Interface number of the first AudioStream interface */ ++ /* ++ [0] = F_AUDIO_AS_OUT_INTERFACE, ++ [1] = F_AUDIO_AS_IN_INTERFACE, ++ */ ++ } ++}; ++#endif ++static struct uac_input_terminal_descriptor usb_out_it_desc = { ++ .bLength = UAC_DT_INPUT_TERMINAL_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_INPUT_TERMINAL, ++ .bTerminalID = USB_OUT_IT_ID, ++ .wTerminalType = cpu_to_le16(UAC_TERMINAL_STREAMING), ++ .bAssocTerminal = IO_OUT_OT_ID, ++ .wChannelConfig = cpu_to_le16(0x3), ++}; ++ ++static struct uac1_output_terminal_descriptor io_out_ot_desc = { ++ .bLength = UAC_DT_OUTPUT_TERMINAL_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, ++ .bTerminalID = IO_OUT_OT_ID, ++ .wTerminalType = cpu_to_le16(UAC_OUTPUT_TERMINAL_SPEAKER), ++ .bAssocTerminal = USB_OUT_IT_ID, ++ .bSourceID = USB_OUT_IT_ID, ++}; ++/* add more control dynamically */ ++static struct usb_audio_control playback_mute_control = { ++ .list = LIST_HEAD_INIT(playback_mute_control.list), ++ .name = "Playback Mute Control", ++ .type = UAC_FU_MUTE, ++ /* Todo: add real Mute control code */ ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++static struct usb_audio_control playback_volume_control = { ++ .list = LIST_HEAD_INIT(playback_volume_control.list), ++ .name = "Playback Volume Control", ++ .type = UAC_FU_VOLUME, ++ /* Todo: add real Volume control code */ ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++static struct usb_audio_control playback_sample_freq_control = { ++ .list = LIST_HEAD_INIT(playback_sample_freq_control.list), ++ .name = "Playback Sampling Frequency Control", ++ .type = UAC_EP_CS_ATTR_SAMPLE_RATE, ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++static struct usb_audio_control_selector playback_fu_controls = { ++ .list = LIST_HEAD_INIT(playback_fu_controls.list), ++ .name = "Playback Function Unit Controls", ++}; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++static struct uac_input_terminal_descriptor io_in_it_desc = { ++ .bLength = UAC_DT_INPUT_TERMINAL_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_INPUT_TERMINAL, ++ .bTerminalID = IO_IN_IT_ID, ++ .wTerminalType = cpu_to_le16(UAC_INPUT_TERMINAL_MICROPHONE), ++ .bAssocTerminal = 0, ++ .wChannelConfig = cpu_to_le16(0x3), ++}; ++ ++DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(0); ++ ++static struct uac_feature_unit_descriptor_0 usb_capture_fu_desc = { ++ .bLength = UAC_DT_FEATURE_UNIT_SIZE(0), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_FEATURE_UNIT, ++ .bUnitID = USB_IN_FU_ID, ++ .bSourceID = IO_IN_IT_ID, ++ .bControlSize = 2, ++ .bmaControls[0] = (UAC_FU_MUTE | UAC_FU_VOLUME), ++}; ++ ++static struct uac1_output_terminal_descriptor usb_in_ot_desc = { ++ .bLength = UAC_DT_OUTPUT_TERMINAL_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, ++ .bTerminalID = USB_IN_OT_ID, ++ .wTerminalType = cpu_to_le16(UAC_TERMINAL_STREAMING), ++ .bAssocTerminal = 0, ++ .bSourceID = USB_IN_FU_ID, ++}; ++/* add more control dynamically */ ++static struct usb_audio_control capture_mute_control = { ++ .list = LIST_HEAD_INIT(capture_mute_control.list), ++ .name = "Capture Mute Control", ++ .type = UAC_FU_MUTE, ++ /* Todo: add real Mute control code */ ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++static struct usb_audio_control capture_volume_control = { ++ .list = LIST_HEAD_INIT(capture_volume_control.list), ++ .name = "Capture Volume Control", ++ .type = UAC_FU_VOLUME, ++ /* Todo: add real Volume control code */ ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++static struct usb_audio_control capture_sample_freq_control = { ++ .list = LIST_HEAD_INIT(capture_sample_freq_control.list), ++ .name = "Capture Sampling Frequency Control", ++ .type = UAC_EP_CS_ATTR_SAMPLE_RATE, ++ .set = generic_set_cmd, ++ .get = generic_get_cmd, ++}; ++static struct usb_audio_control_selector capture_fu_controls = { ++ .list = LIST_HEAD_INIT(capture_fu_controls.list), ++ .id = USB_IN_FU_ID, ++ .name = "Capture Mute & Volume Control", ++ .desc = (struct usb_descriptor_header *)&usb_in_ot_desc, ++}; ++#endif ++/* B.4.1 Standard AS Interface Descriptor */ ++static struct usb_interface_descriptor as_out_interface_alt_0_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, ++}; ++static struct usb_interface_descriptor as_out_interface_alt_1_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bAlternateSetting = 1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, ++}; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++static struct usb_interface_descriptor as_in_interface_alt_0_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, ++}; ++static struct usb_interface_descriptor as_in_interface_alt_1_desc = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bAlternateSetting = 1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING, ++}; ++#endif ++/* B.4.2 Class-Specific AS Interface Descriptor */ ++static struct uac1_as_header_descriptor as_out_header_desc = { ++ .bLength = UAC_DT_AS_HEADER_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_AS_GENERAL, ++ .bTerminalLink = USB_OUT_IT_ID, ++ .bDelay = 1, ++ .wFormatTag = cpu_to_le16(UAC_FORMAT_TYPE_I_PCM), ++}; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++static struct uac1_as_header_descriptor as_in_header_desc = { ++ .bLength = UAC_DT_AS_HEADER_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_AS_GENERAL, ++ .bTerminalLink = USB_IN_OT_ID, ++ .bDelay = 1, ++ .wFormatTag = cpu_to_le16(UAC_FORMAT_TYPE_I_PCM), ++}; ++#endif ++ ++DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(1); ++ ++static struct uac_format_type_i_discrete_descriptor_1 as_out_type_i_desc = { ++ .bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_FORMAT_TYPE, ++ .bFormatType = UAC_FORMAT_TYPE_I, ++ .bSubframeSize = 2, ++ .bBitResolution = 16, ++ .bSamFreqType = 1, ++}; ++ ++/* Standard ISO OUT Endpoint Descriptor */ ++static struct usb_endpoint_descriptor as_out_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_AUDIO_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_OUT, ++ .bmAttributes = USB_ENDPOINT_SYNC_ADAPTIVE ++ | USB_ENDPOINT_XFER_ISOC, ++ .bInterval = 4, ++}; ++ ++/* Class-specific AS ISO OUT Endpoint Descriptor */ ++static struct uac_iso_endpoint_descriptor as_iso_out_desc = { ++ .bLength = UAC_ISO_ENDPOINT_DESC_SIZE, ++ .bDescriptorType = USB_DT_CS_ENDPOINT, ++ .bDescriptorSubtype = UAC_EP_GENERAL, ++ .bmAttributes = 1, ++ .bLockDelayUnits = 1, ++ .wLockDelay = __constant_cpu_to_le16(1), ++}; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++static struct uac_format_type_i_discrete_descriptor_1 as_in_type_i_desc = { ++ .bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubtype = UAC_FORMAT_TYPE, ++ .bFormatType = UAC_FORMAT_TYPE_I, ++ .bSubframeSize = 2, ++ .bBitResolution = 16, ++ .bSamFreqType = 1, ++}; ++ ++/* Standard ISO OUT Endpoint Descriptor */ ++static struct usb_endpoint_descriptor as_in_ep_desc = { ++ .bLength = USB_DT_ENDPOINT_AUDIO_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ .bInterval = 4, ++}; ++ ++/* Class-specific AS ISO OUT Endpoint Descriptor */ ++static struct uac_iso_endpoint_descriptor as_iso_in_desc = { ++ .bLength = UAC_ISO_ENDPOINT_DESC_SIZE, ++ .bDescriptorType = USB_DT_CS_ENDPOINT, ++ .bDescriptorSubtype = UAC_EP_GENERAL, ++ .bmAttributes = 1, ++ .bLockDelayUnits = 0, ++ .wLockDelay = 0, ++}; ++#endif ++static struct usb_interface_assoc_descriptor ++audio_iad_descriptor = { ++ .bLength = sizeof(audio_iad_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, ++ .bFirstInterface = 0, /* updated at bind */ ++ .bInterfaceCount = 3, ++ .bFunctionClass = USB_CLASS_AUDIO, ++ .bFunctionSubClass = 0, ++ .bFunctionProtocol = UAC_VERSION_1, ++}; ++ ++static struct usb_descriptor_header *f_audio_desc_0[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_1, ++ ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, ++ ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, ++ ++ (struct usb_descriptor_header *)&as_out_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_out_desc, ++ NULL, ++}; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++static struct usb_descriptor_header *f_audio_desc_1[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_1, ++ ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_capture_fu_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, ++ ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, ++ ++ (struct usb_descriptor_header *)&as_in_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, ++ NULL, ++}; ++ ++static struct usb_descriptor_header *f_audio_desc_2[] = { ++ (struct usb_descriptor_header *)&audio_iad_descriptor, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc_2, ++ ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_capture_fu_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, ++ ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, ++ ++ (struct usb_descriptor_header *)&as_out_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_out_desc, ++ ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, ++ ++ (struct usb_descriptor_header *)&as_in_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, ++ NULL, ++}; ++#endif ++ ++enum { ++ STR_AC_IF, ++ STR_USB_OUT_IT, ++ STR_USB_OUT_IT_CH_NAMES, ++ STR_IO_OUT_OT, ++ STR_AS_OUT_IF_ALT0, ++ STR_AS_OUT_IF_ALT1, ++ STR_IO_IN_IT, ++ STR_IO_IN_IT_CH_NAMES, ++ STR_USB_IN_OT, ++ STR_AS_IN_IF_ALT0, ++ STR_AS_IN_IF_ALT1, ++}; ++ ++static struct usb_string strings_uac1[] = { ++ [STR_AC_IF].s = "AC Interface", ++ [STR_USB_OUT_IT].s = "Playback Input terminal", ++ [STR_USB_OUT_IT_CH_NAMES].s = "Playback Channels", ++ [STR_IO_OUT_OT].s = "Playback Output terminal", ++ [STR_AS_OUT_IF_ALT0].s = "Playback Inactive", ++ [STR_AS_OUT_IF_ALT1].s = "Playback Active", ++ [STR_IO_IN_IT].s = "Capture Input terminal", ++ [STR_IO_IN_IT_CH_NAMES].s = "Capture Channels", ++ [STR_USB_IN_OT].s = "Capture Output terminal", ++ [STR_AS_IN_IF_ALT0].s = "Capture Inactive", ++ [STR_AS_IN_IF_ALT1].s = "Capture Active", ++ { }, ++}; ++ ++ ++static struct usb_gadget_strings str_uac1 = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings_uac1, ++}; ++ ++static struct usb_gadget_strings *uac1_strings[] = { ++ &str_uac1, ++ NULL, ++}; ++ ++/* ++ * This function is an ALSA sound card following USB Audio Class Spec 1.0. ++ */ ++ ++/*-------------------------------------------------------------------------*/ ++struct f_audio_buf { ++ u8 *buf; ++ int actual; ++ struct list_head list; ++}; ++ ++static struct f_audio_buf *f_audio_buffer_alloc(int buf_size) ++{ ++ struct f_audio_buf *copy_buf; ++ ++ copy_buf = kzalloc(sizeof *copy_buf, GFP_ATOMIC); ++ if (!copy_buf) ++ return ERR_PTR(-ENOMEM); ++ ++ copy_buf->buf = kzalloc(buf_size, GFP_ATOMIC); ++ if (!copy_buf->buf) { ++ kfree(copy_buf); ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ return copy_buf; ++} ++ ++static void f_audio_buffer_free(struct f_audio_buf *audio_buf) ++{ ++ kfree(audio_buf->buf); ++ kfree(audio_buf); ++} ++/*-------------------------------------------------------------------------*/ ++typedef struct rbuf_s ++{ ++ uint8_t *buffer; ++ int32_t r_ptr; ++ int32_t w_ptr; ++ int32_t valid_size; ++ int32_t total_size; ++} rbuf_t; ++ ++struct f_audio { ++ struct gaudio card; ++ ++ /* endpoints handle full and/or high speeds */ ++ struct usb_ep *out_ep; ++ struct usb_ep *in_ep; ++ struct usb_request **in_reqs; ++ ++ spinlock_t playback_lock; ++ struct f_audio_buf *playback_copy_buf; ++ struct work_struct playback_work; ++ struct list_head playback_play_queue;//store buf playback to audio ++ ++ struct task_struct * capture_task; ++ spinlock_t capture_lock; ++ spinlock_t capture_req_lock; ++ rbuf_t *capture_buf_pool; ++ struct list_head capture_req_free; ++ ++ u8 alt_intf[F_AUDIO_NUM_INTERFACES]; ++ ++ /* Control Set command */ ++ struct work_struct cmd_work; ++ struct list_head cs; ++ u8 set_cmd, ready_cmd; ++ int ready_value; ++ struct usb_audio_control *set_con, *ready_con; ++}; ++ ++static inline struct f_audio *func_to_audio(struct usb_function *f) ++{ ++ return container_of(f, struct f_audio, card.func); ++} ++ ++static inline struct f_uac1_legacy_opts *fi_to_opts(const struct usb_function_instance *fi) ++{ ++ return container_of(fi,struct f_uac1_legacy_opts, func_inst); ++} ++ ++/** ++ * Global Resoure ++ **/ ++static struct f_audio *g_f_audio = NULL; ++ ++/*-------------------------------------------------------------------------*/ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++void rbuf_init(rbuf_t *rbuf, int32_t buff_size) ++{ ++ rbuf->buffer = kmalloc(buff_size, GFP_KERNEL); ++ memset(rbuf->buffer, 0, buff_size); ++ ++ rbuf->r_ptr = 0; ++ rbuf->w_ptr = 0; ++ rbuf->valid_size = 0; ++ rbuf->total_size = buff_size; ++} ++ ++void rbuf_deinit(rbuf_t *rbuf) ++{ ++ if (rbuf->buffer != NULL) ++ { ++ kfree(rbuf->buffer); ++ } ++ memset(rbuf, 0, sizeof(rbuf_t)); ++} ++ ++void rbuf_clear(rbuf_t *rbuf) ++{ ++ rbuf->r_ptr = 0; ++ rbuf->w_ptr = 0; ++ rbuf->valid_size = 0; ++} ++ ++bool rbuf_valid_write(int32_t size, rbuf_t *rbuf) ++{ ++ int32_t total_size = rbuf->total_size; ++ ++ return (rbuf->valid_size + size > total_size)?false:true; ++} ++ ++void rbuf_write(void *buffer_to_write, int32_t size, rbuf_t *rbuf) ++{ ++ int32_t w_ptr = rbuf->w_ptr; ++ int32_t total_size = rbuf->total_size; ++ int32_t first_write_size = 0; ++ ++ if (rbuf->valid_size + size > total_size) ++ { ++ return; ++ } ++ ++ if (size + w_ptr <= total_size) ++ { ++ memcpy(rbuf->buffer + w_ptr, buffer_to_write, size); ++ } ++ else ++ { ++ first_write_size = total_size - w_ptr; ++ memcpy(rbuf->buffer + w_ptr, buffer_to_write, first_write_size); ++ memcpy(rbuf->buffer, buffer_to_write + first_write_size, size - first_write_size); ++ } ++ rbuf->w_ptr += size; ++ rbuf->w_ptr %= total_size; ++ rbuf->valid_size += size; ++} ++ ++bool rbuf_valid_read(rbuf_t *rbuf, int32_t size) ++{ ++ return (size > rbuf->valid_size)?false:true; ++} ++ ++void rbuf_read(rbuf_t *rbuf, void *buff, int32_t size) ++{ ++ int32_t r_ptr = rbuf->r_ptr; ++ int32_t total_size = rbuf->total_size; ++ int32_t first_read_size = 0; ++ ++ if (size > rbuf->valid_size) ++ { ++ return; ++ } ++ ++ if (total_size - r_ptr >= size) ++ { ++ memcpy(buff, rbuf->buffer + r_ptr, size); ++ } ++ else ++ { ++ first_read_size = total_size - r_ptr; ++ memcpy(buff, rbuf->buffer + r_ptr, first_read_size); ++ memcpy(buff + first_read_size, rbuf->buffer, size - first_read_size); ++ } ++ ++ rbuf->r_ptr += size; ++ rbuf->r_ptr %= total_size; ++ rbuf->valid_size -= size; ++} ++ ++static int f_audio_capture_buf_work(void *data) ++{ ++ struct f_audio *audio = (struct f_audio *)data; ++ struct f_audio_buf *capture_buf = NULL; ++ struct f_uac1_legacy_opts *opts = fi_to_opts(audio->card.func.fi); ++ struct usb_request *req; ++ unsigned int in_req_buf_size = opts->in_req_buf_size; ++ unsigned long flags; ++ int total_buf_size = 0; ++ int period_size = 0; ++ int num_of_buf = 0; ++ int res = 0; ++ ++ total_buf_size = opts->audio_capture_buf_size; ++ period_size = opts->audio_capture_period_size; ++ num_of_buf = total_buf_size/period_size; ++ ++ pr_debug("%s Started\n", __func__); ++ while(!kthread_should_stop()) ++ { ++ if (!opts->bound) ++ { ++ usleep_range(500, 1000); ++ continue; ++ } ++ ++ spin_lock_irqsave(&audio->capture_lock, flags); ++ if (!audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] && audio->capture_buf_pool) ++ { ++ if (!rbuf_valid_write(period_size, audio->capture_buf_pool)) ++ { ++ rbuf_read(audio->capture_buf_pool, capture_buf->buf, period_size); ++ } ++ } else ++ { ++ if (!audio->capture_buf_pool) ++ { ++ audio->capture_buf_pool = kzalloc(sizeof(rbuf_t), GFP_KERNEL); ++ rbuf_init(audio->capture_buf_pool, total_buf_size); ++ capture_buf = f_audio_buffer_alloc(period_size); ++ } ++ } ++ if (!rbuf_valid_write(period_size, audio->capture_buf_pool)) ++ { ++ spin_unlock_irqrestore(&audio->capture_lock, flags); ++ usleep_range(500, 1000); ++ continue; ++ } ++ spin_unlock_irqrestore(&audio->capture_lock, flags); ++ ++ res = u_audio_capture(&audio->card, ++ capture_buf->buf, ++ period_size); ++ if (res) { ++ printk(KERN_DEBUG"copying failed"); ++ usleep_range(500, 1000); ++ continue; ++ } ++ spin_lock_irqsave(&audio->capture_lock, flags); ++ rbuf_write(capture_buf->buf, period_size, audio->capture_buf_pool); ++ spin_unlock_irqrestore(&audio->capture_lock, flags); ++ ++ if (!audio->alt_intf[F_AUDIO_AS_IN_INTERFACE]) ++ { ++ continue; ++ } ++ ++ spin_lock_irqsave(&audio->capture_req_lock, flags); ++ if (list_empty(&audio->capture_req_free)) { ++ spin_unlock_irqrestore(&audio->capture_req_lock, flags); ++ usleep_range(500, 1000); ++ continue; ++ } ++ req = list_first_entry(&audio->capture_req_free, struct usb_request, ++ list); ++ list_del(&req->list); ++ spin_unlock_irqrestore(&audio->capture_req_lock, flags); ++ ++ spin_lock_irqsave(&audio->capture_lock, flags); ++ rbuf_read(audio->capture_buf_pool, req->buf, in_req_buf_size); ++ spin_unlock_irqrestore(&audio->capture_lock, flags); ++ ++ if (usb_ep_queue(audio->in_ep, req, GFP_ATOMIC)) ++ { ++ spin_lock_irqsave(&audio->capture_req_lock, flags); ++ list_add_tail(&req->list, &audio->capture_req_free); ++ spin_unlock_irqrestore(&audio->capture_req_lock, flags); ++ } ++ } ++ spin_lock_irqsave(&audio->capture_lock, flags); ++ if (audio->capture_buf_pool) ++ { ++ f_audio_buffer_free(capture_buf); ++ rbuf_deinit(audio->capture_buf_pool); ++ audio->capture_buf_pool = NULL; ++ } ++ spin_unlock_irqrestore(&audio->capture_lock, flags); ++ opts->bound = false; ++ return 0; ++} ++#endif ++ ++static void f_audio_playback_work(struct work_struct *data) ++{ ++ struct f_audio *audio = container_of(data, struct f_audio, ++ playback_work); ++ struct f_audio_buf *play_buf; ++ ++ spin_lock_irq(&audio->playback_lock); ++ if (list_empty(&audio->playback_play_queue)) { ++ spin_unlock_irq(&audio->playback_lock); ++ return; ++ } ++ play_buf = list_first_entry(&audio->playback_play_queue, ++ struct f_audio_buf, list); ++ list_del(&play_buf->list); ++ spin_unlock_irq(&audio->playback_lock); ++ ++ u_audio_playback(&audio->card, play_buf->buf, play_buf->actual); ++ f_audio_buffer_free(play_buf); ++} ++ ++static void f_audio_in_ep_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct f_audio *audio = req->context; ++ struct f_uac1_legacy_opts *opts = fi_to_opts(audio->card.func.fi); ++ unsigned int in_req_buf_size = opts->in_req_buf_size; ++ unsigned long flags; ++ ++ if (!audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] || req->status==-ESHUTDOWN) ++ return; ++ ++ spin_lock_irqsave(&audio->capture_lock, flags); ++ if (audio->capture_buf_pool && rbuf_valid_read(audio->capture_buf_pool, in_req_buf_size)) ++ { ++ rbuf_read(audio->capture_buf_pool, req->buf, in_req_buf_size); ++ req->length = in_req_buf_size; ++ if (usb_ep_queue(ep, req, GFP_ATOMIC)) ++ { ++ printk(KERN_DEBUG"%s error\n", __func__); ++ } ++ } else { ++ spin_lock_irqsave(&audio->capture_req_lock, flags); ++ list_add_tail(&req->list, &audio->capture_req_free); ++ spin_unlock_irqrestore(&audio->capture_req_lock, flags); ++ } ++ spin_unlock_irqrestore(&audio->capture_lock, flags); ++} ++ ++static int f_audio_out_ep_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct f_audio *audio = req->context; ++ struct usb_composite_dev *cdev = audio->card.func.config->cdev; ++ struct f_audio_buf *playback_copy_buf = audio->playback_copy_buf; ++ struct f_uac1_legacy_opts *opts; ++ int audio_playback_buf_size; ++ int err; ++ ++ opts = container_of(audio->card.func.fi, struct f_uac1_legacy_opts, ++ func_inst); ++ audio_playback_buf_size = opts->audio_playback_buf_size; ++ ++ if (!audio->alt_intf[F_AUDIO_AS_OUT_INTERFACE])//cancel buf (SHUTDOWN) ++ { ++ kfree(req->buf); ++ usb_ep_free_request(ep, req); ++ return 0; ++ } ++ ++ if (!playback_copy_buf) ++ return -EINVAL; ++ ++ /* Copy buffer is full, add it to the playback_play_queue */ ++ if (audio_playback_buf_size - playback_copy_buf->actual < req->actual) { ++ list_add_tail(&playback_copy_buf->list, &audio->playback_play_queue); ++ schedule_work(&audio->playback_work); ++ playback_copy_buf = f_audio_buffer_alloc(audio_playback_buf_size); ++ if (IS_ERR(playback_copy_buf)) ++ return -ENOMEM; ++ } ++ ++ memcpy(playback_copy_buf->buf + playback_copy_buf->actual, req->buf, req->actual); ++ playback_copy_buf->actual += req->actual; ++ audio->playback_copy_buf = playback_copy_buf; ++ ++ err = usb_ep_queue(ep, req, GFP_ATOMIC); ++ if (err) ++ ERROR(cdev, "%s queue req: %d\n", ep->name, err); ++ ++ return 0; ++ ++} ++ ++static void f_audio_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct f_audio *audio = req->context; ++ int status = req->status; ++ u32 data = 0; ++ struct usb_ep *out_ep = audio->out_ep,*in_ep = audio->in_ep; ++ ++ switch (status) { ++ ++ case 0: /* normal completion? */ ++ if (ep == out_ep) ++ f_audio_out_ep_complete(ep, req); ++ else if (ep == in_ep) { ++ f_audio_in_ep_complete(ep, req); ++ } ++ else if (audio->set_con) { ++ memcpy(&data, req->buf, req->length); ++ audio->set_con->set(audio->set_con, audio->set_cmd, ++ le16_to_cpu(data)); ++ audio->set_con = NULL; ++ } ++ break; ++ case -ESHUTDOWN: ++ if (ep == out_ep) ++ { ++ f_audio_out_ep_complete(ep, req); ++ } ++ else if (ep == in_ep) ++ { ++ f_audio_in_ep_complete(ep, req); ++ } ++ default: ++ break; ++ } ++} ++ ++static int audio_set_intf_req(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct f_audio *audio = func_to_audio(f); ++ struct usb_composite_dev *cdev = f->config->cdev; ++ struct usb_request *req = cdev->req; ++ u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u8 con_sel = (w_value >> 8) & 0xFF; ++ u8 cmd = (ctrl->bRequest & 0x0F); ++ struct usb_audio_control_selector *cs; ++ struct usb_audio_control *con; ++ ++ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n", ++ ctrl->bRequest, w_value, len, id); ++ ++ list_for_each_entry(cs, &audio->cs, list) { ++ if (cs->id == id) { ++ list_for_each_entry(con, &cs->control, list) { ++ if (con->type == con_sel) { ++ audio->set_con = con; ++ break; ++ } ++ } ++ break; ++ } ++ } ++ ++ audio->set_cmd = cmd; ++ req->context = audio; ++ req->complete = f_audio_complete; ++ ++ return len; ++} ++ ++static int audio_get_intf_req(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct f_audio *audio = func_to_audio(f); ++ struct usb_composite_dev *cdev = f->config->cdev; ++ struct usb_request *req = cdev->req; ++ int value = -EOPNOTSUPP; ++ u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u8 con_sel = (w_value >> 8) & 0xFF; ++ u8 cmd = (ctrl->bRequest & 0x0F); ++ struct usb_audio_control_selector *cs; ++ struct usb_audio_control *con; ++ ++ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n", ++ ctrl->bRequest, w_value, len, id); ++ ++ list_for_each_entry(cs, &audio->cs, list) { ++ if (cs->id == id) { ++ list_for_each_entry(con, &cs->control, list) { ++ if (con->type == con_sel && con->get) { ++ value = con->get(con, cmd); ++ break; ++ } ++ } ++ break; ++ } ++ } ++ ++ req->context = audio; ++ req->complete = f_audio_complete; ++ len = min_t(size_t, sizeof(value), len); ++ memcpy(req->buf, &value, len); ++ ++ return len; ++} ++ ++static int audio_set_endpoint_req(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_composite_dev *cdev = f->config->cdev; ++ int value = -EOPNOTSUPP; ++ u16 ep = le16_to_cpu(ctrl->wIndex); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ ++ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n", ++ ctrl->bRequest, w_value, len, ep); ++ ++ switch (ctrl->bRequest) { ++ case UAC_SET_CUR: ++ value = len; ++ break; ++ ++ case UAC_SET_MIN: ++ break; ++ ++ case UAC_SET_MAX: ++ break; ++ ++ case UAC_SET_RES: ++ break; ++ ++ case UAC_SET_MEM: ++ break; ++ ++ default: ++ break; ++ } ++ ++ return value; ++} ++ ++static int audio_get_endpoint_req(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_composite_dev *cdev = f->config->cdev; ++ int value = -EOPNOTSUPP; ++ u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); ++ u16 len = le16_to_cpu(ctrl->wLength); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ ++ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n", ++ ctrl->bRequest, w_value, len, ep); ++ ++ switch (ctrl->bRequest) { ++ case UAC_GET_CUR: ++ case UAC_GET_MIN: ++ case UAC_GET_MAX: ++ case UAC_GET_RES: ++ value = len; ++ break; ++ case UAC_GET_MEM: ++ break; ++ default: ++ break; ++ } ++ ++ return value; ++} ++ ++static int ++f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_composite_dev *cdev = f->config->cdev; ++ struct usb_request *req = cdev->req; ++ int value = -EOPNOTSUPP; ++ u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 w_length = le16_to_cpu(ctrl->wLength); ++ ++ /* composite driver infrastructure handles everything; interface ++ * activation uses set_alt(). ++ */ ++ DBG(cdev, "control req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, w_length); ++ ++ switch (ctrl->bRequestType) { ++ case USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE: ++ DBG(cdev,"USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE\n"); ++ value = audio_set_intf_req(f, ctrl); ++ break; ++ ++ case USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE: ++ DBG(cdev,"USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE\n"); ++ value = audio_get_intf_req(f, ctrl); ++ break; ++ ++ case USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_ENDPOINT: ++ DBG(cdev,"USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_ENDPOINT\n"); ++ value = audio_set_endpoint_req(f, ctrl); ++ break; ++ ++ case USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_ENDPOINT: ++ DBG(cdev,"USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE\n"); ++ value = audio_get_endpoint_req(f, ctrl); ++ break; ++ ++ default: ++ ERROR(cdev, "invalid control req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, w_length); ++ } ++ ++ /* respond with data transfer or status phase? */ ++ if (value >= 0) { ++ DBG(cdev, "audio req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, w_length); ++ req->zero = 0; ++ req->length = value; ++ value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC); ++ if (value < 0) ++ ERROR(cdev, "audio response on err %d\n", value); ++ } ++ ++ /* device either stalls (value < 0) or reports success */ ++ return value; ++} ++ ++static int f_audio_get_alt(struct usb_function *f, unsigned intf) ++{ ++ struct f_audio *audio = func_to_audio(f); ++ struct f_uac1_legacy_opts *opts; ++ ++ opts = container_of(f->fi, struct f_uac1_legacy_opts, func_inst); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if ((ENABLE_MICROPHONE == opts->audio_play_mode) || ++ (ENABLE_MIC_AND_SPK == opts->audio_play_mode && ++ intf == ac_header_desc_2.baInterfaceNr[F_AUDIO_AS_IN_INTERFACE])) ++ { ++ return audio->alt_intf[F_AUDIO_AS_IN_INTERFACE]; ++ } ++ if ((ENABLE_SPEAKER == opts->audio_play_mode) || ++ (ENABLE_MIC_AND_SPK == opts->audio_play_mode && ++ intf == ac_header_desc_2.baInterfaceNr[F_AUDIO_AS_OUT_INTERFACE])) ++#endif ++ { ++ return audio->alt_intf[F_AUDIO_AS_OUT_INTERFACE]; ++ } ++ ++ return 0; ++} ++ ++static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt) ++{ ++ struct f_audio *audio = func_to_audio(f); ++ struct usb_composite_dev *cdev = f->config->cdev; ++ struct usb_request *req; ++ struct f_uac1_legacy_opts *opts; ++ struct usb_ep *out_ep = audio->out_ep; ++ int out_req_buf_size, out_req_count, audio_playback_buf_size; ++ unsigned long flags; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ struct usb_ep *in_ep = audio->in_ep; ++ int in_req_buf_size, in_req_count; ++#endif ++ int i = 0, err = 0; ++ ++ INFO(cdev, "uac1 intf %d, alt %d\n", intf, alt); ++ ++ opts = container_of(f->fi, struct f_uac1_legacy_opts, func_inst); ++ out_req_buf_size = opts->out_req_buf_size; ++ out_req_count = opts->out_req_count; ++ audio_playback_buf_size = opts->audio_playback_buf_size; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ in_req_buf_size = opts->in_req_buf_size; ++ in_req_count = opts->in_req_count; ++ ++ if( (ENABLE_MICROPHONE == opts->audio_play_mode) || ++ (ENABLE_MIC_AND_SPK == opts->audio_play_mode && intf == ac_header_desc_2.baInterfaceNr[F_AUDIO_AS_IN_INTERFACE])) ++ { ++ if (alt == 1) { ++ err = config_ep_by_speed(cdev->gadget, f, in_ep); ++ if (err) ++ return err; ++ ++ audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] = alt; ++ ++ usb_ep_enable(in_ep); ++ ++ audio->in_reqs = kzalloc(in_req_count * ++ sizeof(struct usb_request *), GFP_KERNEL); ++ for (i = 0; i < in_req_count && err == 0; i++) { ++ /* Allocate a write buffer */ ++ req = usb_ep_alloc_request(in_ep, GFP_ATOMIC); ++ if (!req) { ++ pr_err("request allocation failed\n"); ++ return -ENOMEM; ++ } ++ req->buf = kzalloc(in_req_buf_size,GFP_ATOMIC); ++ if (!req->buf) ++ return -ENOMEM; ++ ++ audio->in_reqs[i] = req; ++ ++ req->zero = 0; ++ req->length = 0; ++ req->context = audio; ++ req->complete = f_audio_complete; ++ ++ spin_lock_irqsave(&audio->capture_req_lock, flags); ++#if 1 ++ err = usb_ep_queue(in_ep, ++ req, GFP_ATOMIC); ++ if (err) { ++ ERROR(cdev, ++ "%s queue req: %d\n", ++ out_ep->name, err); ++ } ++#endif ++ spin_unlock_irqrestore(&audio->capture_req_lock, flags); ++ } ++ } else { ++ if (audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] && in_ep) ++ { ++ audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] = alt; ++ if (audio->in_reqs) ++ { ++ for (i = 0; i < in_req_count; i++) { ++ { ++ usb_ep_dequeue(in_ep, audio->in_reqs[i]); ++ kfree(audio->in_reqs[i]->buf); ++ usb_ep_free_request(in_ep, audio->in_reqs[i]); ++ audio->in_reqs[i] = NULL; ++ } ++ } ++ kfree(audio->in_reqs); ++ audio->in_reqs = NULL; ++ } ++ usb_ep_disable(in_ep); ++ } ++ INIT_LIST_HEAD(&audio->capture_req_free); ++ } ++ } else if ((ENABLE_SPEAKER == opts->audio_play_mode) || ++ (ENABLE_MIC_AND_SPK == opts->audio_play_mode && intf == ac_header_desc_2.baInterfaceNr[F_AUDIO_AS_OUT_INTERFACE])) ++#endif ++ { ++ audio->alt_intf[F_AUDIO_AS_OUT_INTERFACE] = alt; ++ if (alt == 1) { ++ err = config_ep_by_speed(cdev->gadget, f, out_ep); ++ if (err) ++ return err; ++ ++ usb_ep_enable(out_ep); ++ audio->playback_copy_buf = f_audio_buffer_alloc(audio_playback_buf_size); ++ if (IS_ERR(audio->playback_copy_buf)) ++ return -ENOMEM; ++ ++ /* ++ * allocate a bunch of read buffers ++ * and queue them all at once. ++ */ ++ for (i = 0; i < out_req_count && err == 0; i++) { ++ req = usb_ep_alloc_request(out_ep, GFP_ATOMIC); ++ if (req) { ++ req->buf = kzalloc(out_req_buf_size, ++ GFP_ATOMIC); ++ if (req->buf) { ++ req->length = out_req_buf_size; ++ req->context = audio; ++ req->complete = ++ f_audio_complete; ++ err = usb_ep_queue(out_ep, ++ req, GFP_ATOMIC); ++ if (err) ++ ERROR(cdev, ++ "%s queue req: %d\n", ++ out_ep->name, err); ++ } else ++ err = -ENOMEM; ++ } else ++ err = -ENOMEM; ++ } ++ } else { ++ struct f_audio_buf *playback_copy_buf = audio->playback_copy_buf; ++ if (playback_copy_buf) { ++ list_add_tail(&playback_copy_buf->list, ++ &audio->playback_play_queue); ++ schedule_work(&audio->playback_work); ++ audio->playback_copy_buf = NULL; ++ } ++ usb_ep_disable(out_ep); ++ } ++ } ++ return err; ++} ++ ++static void f_audio_disable(struct usb_function *f) ++{ ++ struct f_audio *audio = func_to_audio(f); ++ struct usb_composite_dev *cdev = f->config->cdev; ++ ++ DBG(cdev, "%s\n",__func__); ++ ++ audio->alt_intf[F_AUDIO_AS_OUT_INTERFACE] = 0; ++ audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] = 0; ++ ++ return; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void f_audio_build_desc(struct f_audio *audio) ++{ ++ struct gaudio *card = &audio->card; ++ u8 *sam_freq; ++ int rate; ++ ++ /* Set channel numbers */ ++ usb_out_it_desc.bNrChannels = u_audio_get_playback_channels(card); ++ as_out_type_i_desc.bNrChannels = u_audio_get_playback_channels(card); ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ io_in_it_desc.bNrChannels = u_audio_get_capture_channels(card); ++ as_in_type_i_desc.bNrChannels = u_audio_get_capture_channels(card); ++#endif ++ /* Set sample rates */ ++ rate = u_audio_get_playback_rate(card); ++ sam_freq = as_out_type_i_desc.tSamFreq[0]; ++ memcpy(sam_freq, &rate, 3); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ rate = u_audio_get_capture_rate(card); ++ sam_freq = as_in_type_i_desc.tSamFreq[0]; ++ memcpy(sam_freq, &rate, 3); ++#endif ++ ++ /* Todo: Set Sample bits and other parameters */ ++ ++ return; ++} ++ ++static void mixer_cmd_work(struct work_struct *data) ++{ ++ struct f_audio * audio = g_f_audio; ++ struct usb_audio_control *con = audio->ready_con; ++ int value = audio->ready_value; ++ ++ if (!con) ++ return; ++ ++ switch (con->type) ++ { ++ case UAC_FU_VOLUME: // actual db / CAPTURE_VOLUME_STEP ++ gaudio_mixer_control(CAPTURE_VOLUME_ID, UAC_VOLUME_ATTR_TO_MIXER_VALUE(value)); ++ break; ++ default: ++ break; ++ } ++ ++ audio->ready_con = NULL; ++} ++ ++/* audio function driver setup/binding */ ++static int ++f_audio_bind(struct usb_configuration *c, struct usb_function *f) ++{ ++ struct usb_composite_dev *cdev = c->cdev; ++ struct f_audio *audio = func_to_audio(f); ++ struct usb_string *us; ++ int status; ++ static struct usb_descriptor_header **f_audio_desc = NULL; ++ struct usb_ep *ep = NULL; ++ struct f_uac1_legacy_opts *audio_opts; ++ ++ audio_opts = container_of(f->fi, struct f_uac1_legacy_opts, func_inst); ++ audio->card.gadget = c->cdev->gadget; ++ /* set up ASLA audio devices */ ++ if (!audio_opts->bound) { ++ status = gaudio_setup(&audio->card); ++ if (status < 0) ++ return status; ++ audio_opts->bound = true; ++ } ++ /* Set Strings Desc & attach to releated desc*/ ++ us = usb_gstrings_attach(cdev, uac1_strings, ARRAY_SIZE(strings_uac1)); ++ if (IS_ERR(us)) ++ return PTR_ERR(us); ++ ac_interface_desc.iInterface = us[STR_AC_IF].id; ++ usb_out_it_desc.iTerminal = us[STR_USB_OUT_IT].id; ++ usb_out_it_desc.iChannelNames = us[STR_USB_OUT_IT_CH_NAMES].id; ++ io_out_ot_desc.iTerminal = us[STR_IO_OUT_OT].id; ++ as_out_interface_alt_0_desc.iInterface = us[STR_AS_OUT_IF_ALT0].id; ++ as_out_interface_alt_1_desc.iInterface = us[STR_AS_OUT_IF_ALT1].id; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ io_in_it_desc.iTerminal = us[STR_IO_IN_IT].id; ++ io_in_it_desc.iChannelNames = us[STR_IO_IN_IT_CH_NAMES].id; ++ usb_in_ot_desc.iTerminal = us[STR_USB_IN_OT].id; ++ as_in_interface_alt_0_desc.iInterface = us[STR_AS_IN_IF_ALT0].id; ++ as_in_interface_alt_1_desc.iInterface = us[STR_AS_IN_IF_ALT1].id; ++#endif ++ f_audio_build_desc(audio); ++ ++ /* allocate instance-specific interface IDs, and patch descriptors */ ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ ac_interface_desc.bInterfaceNumber = status; ++ audio_iad_descriptor.bFirstInterface = status; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_SPEAKER == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++#endif ++ { ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ as_out_interface_alt_0_desc.bInterfaceNumber = status; ++ as_out_interface_alt_1_desc.bInterfaceNumber = status; ++ audio->alt_intf[F_AUDIO_AS_OUT_INTERFACE] = 0; ++ } ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode) ++ ac_header_desc_2.baInterfaceNr[F_AUDIO_AS_OUT_INTERFACE] = status; ++#endif ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++ { ++ status = usb_interface_id(c, f); ++ if (status < 0) ++ goto fail; ++ as_in_interface_alt_0_desc.bInterfaceNumber = status; ++ as_in_interface_alt_1_desc.bInterfaceNumber = status; ++ audio->alt_intf[F_AUDIO_AS_IN_INTERFACE] = 0; ++ } ++#endif ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode) ++ ac_header_desc_2.baInterfaceNr[F_AUDIO_AS_IN_INTERFACE] = status; ++ else ++#endif ++ ac_header_desc_1.baInterfaceNr[0] = status; ++ ++ status = -ENODEV; ++ ++ /* allocate instance-specific endpoints */ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_SPEAKER == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++#endif ++ { ++ as_out_ep_desc.wMaxPacketSize = audio_opts->out_req_buf_size; ++ ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc); ++ if (!ep) ++ goto fail; ++ audio->out_ep = ep; ++ audio->out_ep->desc = &as_out_ep_desc; ++ } ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode ) ++ { ++ as_in_ep_desc.wMaxPacketSize = audio_opts->in_req_buf_size; ++ ep = usb_ep_autoconfig(cdev->gadget, &as_in_ep_desc); ++ if (!ep) ++ goto fail; ++ audio->in_ep = ep; ++ audio->in_ep->desc = &as_in_ep_desc; ++ } ++#endif ++ status = -ENOMEM; ++ ++ /* Finally Build the Descriptors */ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_MICROPHONE == audio_opts->audio_play_mode) { ++ audio_iad_descriptor.bInterfaceCount = 2; ++ f_audio_desc = f_audio_desc_1; ++ } ++ else if(ENABLE_MIC_AND_SPK == audio_opts->audio_play_mode) { ++ audio_iad_descriptor.bInterfaceCount = 3; ++ f_audio_desc = f_audio_desc_2; ++ } else if (ENABLE_SPEAKER == audio_opts->audio_play_mode) ++#endif ++ { ++ audio_iad_descriptor.bInterfaceCount = 2; ++ f_audio_desc = f_audio_desc_0; ++ } ++ ++ /* copy descriptors, and track endpoint copies */ ++ status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, NULL, ++ NULL); ++ if (status) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ gaudio_cleanup(&audio->card); ++ return status; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int generic_set_cmd(struct usb_audio_control *con, u8 cmd, int value) ++{ ++ struct f_audio *audio = g_f_audio; ++ ++ if (!audio) ++ return -EINVAL; ++ ++ if (audio->ready_con) ++ return -EINVAL; ++ ++ audio->ready_con = con; ++ audio->ready_cmd = cmd; ++ audio->ready_value = value; ++ ++ con->data[cmd] = value; ++ schedule_work(&audio->cmd_work); ++ return 0; ++} ++ ++static int generic_get_cmd(struct usb_audio_control *con, u8 cmd) ++{ ++ return con->data[cmd]; ++} ++static int control_selector_init(struct f_audio *audio) ++{ ++ INIT_LIST_HEAD(&audio->cs); ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ list_add(&capture_fu_controls.list,&audio->cs); ++#endif ++ list_add(&playback_fu_controls.list,&audio->cs); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ INIT_LIST_HEAD(&capture_fu_controls.control); ++ list_add(&capture_mute_control.list, ++ &capture_fu_controls.control); ++ list_add(&capture_volume_control.list, ++ &capture_fu_controls.control); ++#endif ++ INIT_LIST_HEAD(&playback_fu_controls.control); ++ list_add(&playback_mute_control.list, ++ &playback_fu_controls.control); ++ list_add(&playback_volume_control.list, ++ &playback_fu_controls.control); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ capture_volume_control.data[UAC__CUR] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_CUR); ++ capture_volume_control.data[UAC__MIN] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_MIN); ++ capture_volume_control.data[UAC__MAX] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_MAX); ++ capture_volume_control.data[UAC__RES] = DB_TO_UAC_VOLUME_ATTR(CAPTURE_VOLUME_STEP); ++#endif ++ playback_volume_control.data[UAC__CUR] = 0xffc0; ++ playback_volume_control.data[UAC__MIN] = 0xe3a0; ++ playback_volume_control.data[UAC__MAX] = 0xfff0; ++ playback_volume_control.data[UAC__RES] = 0x0030; ++ ++ return 0; ++} ++static inline struct f_uac1_legacy_opts *to_f_uac1_legacy_opts(struct config_item *item) ++{ ++ return container_of(to_config_group(item), struct f_uac1_legacy_opts, ++ func_inst.group); ++} ++ ++static void f_uac1_attr_release(struct config_item *item) ++{ ++ struct f_uac1_legacy_opts *opts = to_f_uac1_legacy_opts(item); ++ ++ usb_put_function_instance(&opts->func_inst); ++} ++ ++static struct configfs_item_operations f_uac1_item_ops = { ++ .release = f_uac1_attr_release, ++}; ++ ++#define UAC1_INT_ATTRIBUTE(name) \ ++static ssize_t f_uac1_legacy_opts_##name##_show(struct config_item *item, \ ++ char *page) \ ++{ \ ++ struct f_uac1_legacy_opts *opts = to_f_uac1_legacy_opts(item); \ ++ int result; \ ++ \ ++ mutex_lock(&opts->lock); \ ++ result = sprintf(page, "%u\n", opts->name); \ ++ mutex_unlock(&opts->lock); \ ++ \ ++ return result; \ ++} \ ++ \ ++static ssize_t f_uac1_legacy_opts_##name##_store(struct config_item *item, \ ++ const char *page, size_t len) \ ++{ \ ++ struct f_uac1_legacy_opts *opts = to_f_uac1_legacy_opts(item); \ ++ int ret; \ ++ u32 num; \ ++ \ ++ mutex_lock(&opts->lock); \ ++ if (opts->refcnt) { \ ++ ret = -EBUSY; \ ++ goto end; \ ++ } \ ++ \ ++ ret = kstrtou32(page, 0, &num); \ ++ if (ret) \ ++ goto end; \ ++ \ ++ opts->name = num; \ ++ ret = len; \ ++ \ ++end: \ ++ mutex_unlock(&opts->lock); \ ++ return ret; \ ++} \ ++ \ ++CONFIGFS_ATTR(f_uac1_legacy_opts_, name) ++ ++UAC1_INT_ATTRIBUTE(out_req_buf_size); ++UAC1_INT_ATTRIBUTE(out_req_count); ++UAC1_INT_ATTRIBUTE(audio_playback_buf_size); ++ ++UAC1_INT_ATTRIBUTE(in_req_buf_size); ++UAC1_INT_ATTRIBUTE(in_req_count); ++UAC1_INT_ATTRIBUTE(audio_capture_buf_size); ++ ++#define UAC1_STR_ATTRIBUTE(name) \ ++static ssize_t f_uac1_legacy_opts_##name##_show(struct config_item *item, \ ++ char *page) \ ++{ \ ++ struct f_uac1_legacy_opts *opts = to_f_uac1_legacy_opts(item); \ ++ int result; \ ++ \ ++ mutex_lock(&opts->lock); \ ++ result = sprintf(page, "%s\n", opts->name); \ ++ mutex_unlock(&opts->lock); \ ++ \ ++ return result; \ ++} \ ++ \ ++static ssize_t f_uac1_legacy_opts_##name##_store(struct config_item *item, \ ++ const char *page, size_t len) \ ++{ \ ++ struct f_uac1_legacy_opts *opts = to_f_uac1_legacy_opts(item); \ ++ int ret = -EBUSY; \ ++ char *tmp; \ ++ \ ++ mutex_lock(&opts->lock); \ ++ if (opts->refcnt) \ ++ goto end; \ ++ \ ++ tmp = kstrndup(page, len, GFP_KERNEL); \ ++ if (tmp) { \ ++ ret = -ENOMEM; \ ++ goto end; \ ++ } \ ++ if (opts->name##_alloc) \ ++ kfree(opts->name); \ ++ opts->name##_alloc = true; \ ++ opts->name = tmp; \ ++ ret = len; \ ++ \ ++end: \ ++ mutex_unlock(&opts->lock); \ ++ return ret; \ ++} \ ++ \ ++CONFIGFS_ATTR(f_uac1_legacy_opts_, name) ++ ++UAC1_STR_ATTRIBUTE(fn_play); ++UAC1_STR_ATTRIBUTE(fn_cap); ++UAC1_STR_ATTRIBUTE(fn_cntl); ++ ++static struct configfs_attribute *f_uac1_attrs[] = { ++ &f_uac1_legacy_opts_attr_out_req_buf_size, ++ &f_uac1_legacy_opts_attr_out_req_count, ++ &f_uac1_legacy_opts_attr_audio_playback_buf_size, ++ &f_uac1_legacy_opts_attr_in_req_buf_size, ++ &f_uac1_legacy_opts_attr_in_req_count, ++ &f_uac1_legacy_opts_attr_audio_capture_buf_size, ++ &f_uac1_legacy_opts_attr_fn_play, ++ &f_uac1_legacy_opts_attr_fn_cap, ++ &f_uac1_legacy_opts_attr_fn_cntl, ++ NULL, ++}; ++ ++static struct config_item_type f_uac1_func_type = { ++ .ct_item_ops = &f_uac1_item_ops, ++ .ct_attrs = f_uac1_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static void f_audio_free_inst(struct usb_function_instance *f) ++{ ++ struct f_uac1_legacy_opts *opts; ++ ++ opts = container_of(f, struct f_uac1_legacy_opts, func_inst); ++ if (opts->fn_play_alloc) ++ kfree(opts->fn_play); ++ if (opts->fn_cap_alloc) ++ kfree(opts->fn_cap); ++ if (opts->fn_cntl_alloc) ++ kfree(opts->fn_cntl); ++ kfree(opts); ++} ++ ++static struct usb_function_instance *f_audio_alloc_inst(void) ++{ ++ struct f_uac1_legacy_opts *opts; ++ ++ opts = kzalloc(sizeof(*opts), GFP_KERNEL); ++ if (!opts) ++ return ERR_PTR(-ENOMEM); ++ ++ mutex_init(&opts->lock); ++ opts->func_inst.free_func_inst = f_audio_free_inst; ++ ++ config_group_init_type_name(&opts->func_inst.group, "", ++ &f_uac1_func_type); ++ ++ opts->fn_play = FILE_PCM_PLAYBACK; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ opts->fn_cap = FILE_PCM_CAPTURE; ++#endif ++ opts->fn_cntl = FILE_CONTROL; ++ return &opts->func_inst; ++} ++ ++static void f_audio_free(struct usb_function *f) ++{ ++ struct f_audio *audio = func_to_audio(f); ++ struct f_uac1_legacy_opts *opts; ++ ++ if (g_f_audio!=audio) ++ return; ++ ++ opts = container_of(f->fi, struct f_uac1_legacy_opts, func_inst); ++ ++ if (audio->capture_task) ++ { ++ kthread_stop(audio->capture_task); ++ while(opts->bound) ++ { ++ printk(KERN_DEBUG"%s wait unbind...\n", __func__); ++ msleep(5); ++ } ++ audio->capture_task = NULL; ++ } ++ ++ gaudio_cleanup(&audio->card); ++ kfree(audio); ++ g_f_audio = NULL; ++ mutex_lock(&opts->lock); ++ --opts->refcnt; ++ mutex_unlock(&opts->lock); ++} ++ ++static void f_audio_unbind(struct usb_configuration *c, struct usb_function *f) ++{ ++ usb_free_all_descriptors(f); ++} ++ ++static struct usb_function *f_audio_alloc(struct usb_function_instance *fi) ++{ ++ struct f_audio *audio; ++ struct f_uac1_legacy_opts *opts; ++ ++ if (g_f_audio) ++ return ERR_PTR(-EAGAIN); ++ ++ /* allocate and initialize one new instance */ ++ audio = kzalloc(sizeof(*audio), GFP_KERNEL); ++ if (!audio) ++ return ERR_PTR(-ENOMEM); ++ ++ audio->card.func.name = "g_audio"; ++ ++ opts = container_of(fi, struct f_uac1_legacy_opts, func_inst); ++ mutex_lock(&opts->lock); ++ ++opts->refcnt; ++ mutex_unlock(&opts->lock); ++ INIT_LIST_HEAD(&audio->playback_play_queue); ++ INIT_LIST_HEAD(&audio->capture_req_free); ++ spin_lock_init(&audio->playback_lock); ++ spin_lock_init(&audio->capture_lock); ++ spin_lock_init(&audio->capture_req_lock); ++ ++ audio->card.func.bind = f_audio_bind; ++ audio->card.func.unbind = f_audio_unbind; ++ audio->card.func.get_alt = f_audio_get_alt; ++ audio->card.func.set_alt = f_audio_set_alt; ++ audio->card.func.setup = f_audio_setup; ++ audio->card.func.disable = f_audio_disable; ++ audio->card.func.free_func = f_audio_free; ++ ++ control_selector_init(audio); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if(ENABLE_MICROPHONE == opts->audio_play_mode) ++ { ++ audio->capture_task = ++ kthread_run(f_audio_capture_buf_work, audio, "uac_capture_work"); ++ } ++ else if(ENABLE_MIC_AND_SPK == opts->audio_play_mode) ++ { ++ audio->capture_task = ++ kthread_run(f_audio_capture_buf_work, audio, "uac_capture_work"); ++ INIT_WORK(&audio->playback_work, f_audio_playback_work); ++ } ++ else if (ENABLE_SPEAKER == opts->audio_play_mode) ++#endif ++ INIT_WORK(&audio->playback_work, f_audio_playback_work); ++ ++ INIT_WORK(&audio->cmd_work, mixer_cmd_work); ++ g_f_audio = audio; ++ return &audio->card.func; ++} ++ ++DECLARE_USB_FUNCTION_INIT(uac1_legacy, f_audio_alloc_inst, f_audio_alloc); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Bryan Wu"); +diff --git a/drivers/usb/gadget/function/f_uac2.c b/drivers/usb/gadget/function/f_uac2.c +old mode 100644 +new mode 100755 +index 969cfe741380..ff0f118e0340 +--- a/drivers/usb/gadget/function/f_uac2.c ++++ b/drivers/usb/gadget/function/f_uac2.c +@@ -1,30 +1,19 @@ ++// SPDX-License-Identifier: GPL-2.0+ + /* + * f_uac2.c -- USB Audio Class 2.0 Function + * + * Copyright (C) 2011 + * Yadwinder Singh (yadi.brar01@gmail.com) + * Jaswinder Singh (jaswinder.singh@linaro.org) +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. + */ + + #include + #include +-#include + #include + +-#include +-#include +-#include +- ++#include "u_audio.h" + #include "u_uac2.h" + +-/* Keep everyone on toes */ +-#define USB_XFERS 2 +- + /* + * The driver implements a simple UAC_2 topology. + * USB-OUT -> IT_1 -> OT_3 -> ALSA_Capture +@@ -33,12 +22,8 @@ + * controlled by two clock sources : + * CLK_5 := c_srate, and CLK_6 := p_srate + */ +-#define USB_OUT_IT_ID 1 +-#define IO_IN_IT_ID 2 +-#define IO_OUT_OT_ID 3 +-#define USB_IN_OT_ID 4 +-#define USB_OUT_CLK_ID 5 +-#define USB_IN_CLK_ID 6 ++#define USB_OUT_CLK_ID (out_clk_src_desc.bClockID) ++#define USB_IN_CLK_ID (in_clk_src_desc.bClockID) + + #define CONTROL_ABSENT 0 + #define CONTROL_RDONLY 1 +@@ -54,504 +39,26 @@ + #define UNFLW_CTRL 8 + #define OVFLW_CTRL 10 + +-static const char *uac2_name = "snd_uac2"; +- +-struct uac2_req { +- struct uac2_rtd_params *pp; /* parent param */ +- struct usb_request *req; +-}; +- +-struct uac2_rtd_params { +- struct snd_uac2_chip *uac2; /* parent chip */ +- bool ep_enabled; /* if the ep is enabled */ +- /* Size of the ring buffer */ +- size_t dma_bytes; +- unsigned char *dma_area; +- +- struct snd_pcm_substream *ss; +- +- /* Ring buffer */ +- ssize_t hw_ptr; +- +- void *rbuf; +- +- size_t period_size; +- +- unsigned max_psize; +- struct uac2_req ureq[USB_XFERS]; +- +- spinlock_t lock; +-}; +- +-struct snd_uac2_chip { +- struct platform_device pdev; +- struct platform_driver pdrv; +- +- struct uac2_rtd_params p_prm; +- struct uac2_rtd_params c_prm; ++#define EPIN_EN(_opts) ((_opts)->p_chmask != 0) ++#define EPOUT_EN(_opts) ((_opts)->c_chmask != 0) + +- struct snd_card *card; +- struct snd_pcm *pcm; +- +- /* timekeeping for the playback endpoint */ +- unsigned int p_interval; +- unsigned int p_residue; +- +- /* pre-calculated values for playback iso completion */ +- unsigned int p_pktsize; +- unsigned int p_pktsize_residue; +- unsigned int p_framesize; +-}; +- +-#define BUFF_SIZE_MAX (PAGE_SIZE * 16) +-#define PRD_SIZE_MAX PAGE_SIZE +-#define MIN_PERIODS 4 +- +-static struct snd_pcm_hardware uac2_pcm_hardware = { +- .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER +- | SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID +- | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, +- .rates = SNDRV_PCM_RATE_CONTINUOUS, +- .periods_max = BUFF_SIZE_MAX / PRD_SIZE_MAX, +- .buffer_bytes_max = BUFF_SIZE_MAX, +- .period_bytes_max = PRD_SIZE_MAX, +- .periods_min = MIN_PERIODS, +-}; +- +-struct audio_dev { +- u8 ac_intf, ac_alt; +- u8 as_out_intf, as_out_alt; +- u8 as_in_intf, as_in_alt; +- +- struct usb_ep *in_ep, *out_ep; +- struct usb_function func; +- +- /* The ALSA Sound Card it represents on the USB-Client side */ +- struct snd_uac2_chip uac2; ++struct f_uac2 { ++ struct g_audio g_audio; ++ u8 ac_intf, as_in_intf, as_out_intf; ++ u8 ac_alt, as_in_alt, as_out_alt; /* needed for get_alt() */ + }; + +-static inline +-struct audio_dev *func_to_agdev(struct usb_function *f) ++static inline struct f_uac2 *func_to_uac2(struct usb_function *f) + { +- return container_of(f, struct audio_dev, func); ++ return container_of(f, struct f_uac2, g_audio.func); + } + + static inline +-struct audio_dev *uac2_to_agdev(struct snd_uac2_chip *u) +-{ +- return container_of(u, struct audio_dev, uac2); +-} +- +-static inline +-struct snd_uac2_chip *pdev_to_uac2(struct platform_device *p) +-{ +- return container_of(p, struct snd_uac2_chip, pdev); +-} +- +-static inline +-struct f_uac2_opts *agdev_to_uac2_opts(struct audio_dev *agdev) ++struct f_uac2_opts *g_audio_to_uac2_opts(struct g_audio *agdev) + { + return container_of(agdev->func.fi, struct f_uac2_opts, func_inst); + } + +-static inline +-uint num_channels(uint chanmask) +-{ +- uint num = 0; +- +- while (chanmask) { +- num += (chanmask & 1); +- chanmask >>= 1; +- } +- +- return num; +-} +- +-static void +-agdev_iso_complete(struct usb_ep *ep, struct usb_request *req) +-{ +- unsigned pending; +- unsigned long flags; +- unsigned int hw_ptr; +- bool update_alsa = false; +- int status = req->status; +- struct uac2_req *ur = req->context; +- struct snd_pcm_substream *substream; +- struct uac2_rtd_params *prm = ur->pp; +- struct snd_uac2_chip *uac2 = prm->uac2; +- +- /* i/f shutting down */ +- if (!prm->ep_enabled || req->status == -ESHUTDOWN) +- return; +- +- /* +- * We can't really do much about bad xfers. +- * Afterall, the ISOCH xfers could fail legitimately. +- */ +- if (status) +- pr_debug("%s: iso_complete status(%d) %d/%d\n", +- __func__, status, req->actual, req->length); +- +- substream = prm->ss; +- +- /* Do nothing if ALSA isn't active */ +- if (!substream) +- goto exit; +- +- spin_lock_irqsave(&prm->lock, flags); +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +- /* +- * For each IN packet, take the quotient of the current data +- * rate and the endpoint's interval as the base packet size. +- * If there is a residue from this division, add it to the +- * residue accumulator. +- */ +- req->length = uac2->p_pktsize; +- uac2->p_residue += uac2->p_pktsize_residue; +- +- /* +- * Whenever there are more bytes in the accumulator than we +- * need to add one more sample frame, increase this packet's +- * size and decrease the accumulator. +- */ +- if (uac2->p_residue / uac2->p_interval >= uac2->p_framesize) { +- req->length += uac2->p_framesize; +- uac2->p_residue -= uac2->p_framesize * +- uac2->p_interval; +- } +- +- req->actual = req->length; +- } +- +- pending = prm->hw_ptr % prm->period_size; +- pending += req->actual; +- if (pending >= prm->period_size) +- update_alsa = true; +- +- hw_ptr = prm->hw_ptr; +- prm->hw_ptr = (prm->hw_ptr + req->actual) % prm->dma_bytes; +- +- spin_unlock_irqrestore(&prm->lock, flags); +- +- /* Pack USB load in ALSA ring buffer */ +- pending = prm->dma_bytes - hw_ptr; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +- if (unlikely(pending < req->actual)) { +- memcpy(req->buf, prm->dma_area + hw_ptr, pending); +- memcpy(req->buf + pending, prm->dma_area, +- req->actual - pending); +- } else { +- memcpy(req->buf, prm->dma_area + hw_ptr, req->actual); +- } +- } else { +- if (unlikely(pending < req->actual)) { +- memcpy(prm->dma_area + hw_ptr, req->buf, pending); +- memcpy(prm->dma_area, req->buf + pending, +- req->actual - pending); +- } else { +- memcpy(prm->dma_area + hw_ptr, req->buf, req->actual); +- } +- } +- +-exit: +- if (usb_ep_queue(ep, req, GFP_ATOMIC)) +- dev_err(&uac2->pdev.dev, "%d Error!\n", __LINE__); +- +- if (update_alsa) +- snd_pcm_period_elapsed(substream); +- +- return; +-} +- +-static int +-uac2_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +-{ +- struct snd_uac2_chip *uac2 = snd_pcm_substream_chip(substream); +- struct uac2_rtd_params *prm; +- unsigned long flags; +- int err = 0; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- prm = &uac2->p_prm; +- else +- prm = &uac2->c_prm; +- +- spin_lock_irqsave(&prm->lock, flags); +- +- /* Reset */ +- prm->hw_ptr = 0; +- +- switch (cmd) { +- case SNDRV_PCM_TRIGGER_START: +- case SNDRV_PCM_TRIGGER_RESUME: +- prm->ss = substream; +- break; +- case SNDRV_PCM_TRIGGER_STOP: +- case SNDRV_PCM_TRIGGER_SUSPEND: +- prm->ss = NULL; +- break; +- default: +- err = -EINVAL; +- } +- +- spin_unlock_irqrestore(&prm->lock, flags); +- +- /* Clear buffer after Play stops */ +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && !prm->ss) +- memset(prm->rbuf, 0, prm->max_psize * USB_XFERS); +- +- return err; +-} +- +-static snd_pcm_uframes_t uac2_pcm_pointer(struct snd_pcm_substream *substream) +-{ +- struct snd_uac2_chip *uac2 = snd_pcm_substream_chip(substream); +- struct uac2_rtd_params *prm; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- prm = &uac2->p_prm; +- else +- prm = &uac2->c_prm; +- +- return bytes_to_frames(substream->runtime, prm->hw_ptr); +-} +- +-static int uac2_pcm_hw_params(struct snd_pcm_substream *substream, +- struct snd_pcm_hw_params *hw_params) +-{ +- struct snd_uac2_chip *uac2 = snd_pcm_substream_chip(substream); +- struct uac2_rtd_params *prm; +- int err; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- prm = &uac2->p_prm; +- else +- prm = &uac2->c_prm; +- +- err = snd_pcm_lib_malloc_pages(substream, +- params_buffer_bytes(hw_params)); +- if (err >= 0) { +- prm->dma_bytes = substream->runtime->dma_bytes; +- prm->dma_area = substream->runtime->dma_area; +- prm->period_size = params_period_bytes(hw_params); +- } +- +- return err; +-} +- +-static int uac2_pcm_hw_free(struct snd_pcm_substream *substream) +-{ +- struct snd_uac2_chip *uac2 = snd_pcm_substream_chip(substream); +- struct uac2_rtd_params *prm; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- prm = &uac2->p_prm; +- else +- prm = &uac2->c_prm; +- +- prm->dma_area = NULL; +- prm->dma_bytes = 0; +- prm->period_size = 0; +- +- return snd_pcm_lib_free_pages(substream); +-} +- +-static int uac2_pcm_open(struct snd_pcm_substream *substream) +-{ +- struct snd_uac2_chip *uac2 = snd_pcm_substream_chip(substream); +- struct snd_pcm_runtime *runtime = substream->runtime; +- struct audio_dev *audio_dev; +- struct f_uac2_opts *opts; +- int p_ssize, c_ssize; +- int p_srate, c_srate; +- int p_chmask, c_chmask; +- +- audio_dev = uac2_to_agdev(uac2); +- opts = container_of(audio_dev->func.fi, struct f_uac2_opts, func_inst); +- p_ssize = opts->p_ssize; +- c_ssize = opts->c_ssize; +- p_srate = opts->p_srate; +- c_srate = opts->c_srate; +- p_chmask = opts->p_chmask; +- c_chmask = opts->c_chmask; +- uac2->p_residue = 0; +- +- runtime->hw = uac2_pcm_hardware; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +- spin_lock_init(&uac2->p_prm.lock); +- runtime->hw.rate_min = p_srate; +- switch (p_ssize) { +- case 3: +- runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_3LE; +- break; +- case 4: +- runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE; +- break; +- default: +- runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; +- break; +- } +- runtime->hw.channels_min = num_channels(p_chmask); +- runtime->hw.period_bytes_min = 2 * uac2->p_prm.max_psize +- / runtime->hw.periods_min; +- } else { +- spin_lock_init(&uac2->c_prm.lock); +- runtime->hw.rate_min = c_srate; +- switch (c_ssize) { +- case 3: +- runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_3LE; +- break; +- case 4: +- runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE; +- break; +- default: +- runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; +- break; +- } +- runtime->hw.channels_min = num_channels(c_chmask); +- runtime->hw.period_bytes_min = 2 * uac2->c_prm.max_psize +- / runtime->hw.periods_min; +- } +- +- runtime->hw.rate_max = runtime->hw.rate_min; +- runtime->hw.channels_max = runtime->hw.channels_min; +- +- snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); +- +- return 0; +-} +- +-/* ALSA cries without these function pointers */ +-static int uac2_pcm_null(struct snd_pcm_substream *substream) +-{ +- return 0; +-} +- +-static struct snd_pcm_ops uac2_pcm_ops = { +- .open = uac2_pcm_open, +- .close = uac2_pcm_null, +- .ioctl = snd_pcm_lib_ioctl, +- .hw_params = uac2_pcm_hw_params, +- .hw_free = uac2_pcm_hw_free, +- .trigger = uac2_pcm_trigger, +- .pointer = uac2_pcm_pointer, +- .prepare = uac2_pcm_null, +-}; +- +-static int snd_uac2_probe(struct platform_device *pdev) +-{ +- struct snd_uac2_chip *uac2 = pdev_to_uac2(pdev); +- struct snd_card *card; +- struct snd_pcm *pcm; +- struct audio_dev *audio_dev; +- struct f_uac2_opts *opts; +- int err; +- int p_chmask, c_chmask; +- +- audio_dev = uac2_to_agdev(uac2); +- opts = container_of(audio_dev->func.fi, struct f_uac2_opts, func_inst); +- p_chmask = opts->p_chmask; +- c_chmask = opts->c_chmask; +- +- /* Choose any slot, with no id */ +- err = snd_card_new(&pdev->dev, -1, NULL, THIS_MODULE, 0, &card); +- if (err < 0) +- return err; +- +- uac2->card = card; +- +- /* +- * Create first PCM device +- * Create a substream only for non-zero channel streams +- */ +- err = snd_pcm_new(uac2->card, "UAC2 PCM", 0, +- p_chmask ? 1 : 0, c_chmask ? 1 : 0, &pcm); +- if (err < 0) +- goto snd_fail; +- +- strcpy(pcm->name, "UAC2 PCM"); +- pcm->private_data = uac2; +- +- uac2->pcm = pcm; +- +- snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &uac2_pcm_ops); +- snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &uac2_pcm_ops); +- +- strcpy(card->driver, "UAC2_Gadget"); +- strcpy(card->shortname, "UAC2_Gadget"); +- sprintf(card->longname, "UAC2_Gadget %i", pdev->id); +- +- snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, +- snd_dma_continuous_data(GFP_KERNEL), 0, BUFF_SIZE_MAX); +- +- err = snd_card_register(card); +- if (!err) { +- platform_set_drvdata(pdev, card); +- return 0; +- } +- +-snd_fail: +- snd_card_free(card); +- +- uac2->pcm = NULL; +- uac2->card = NULL; +- +- return err; +-} +- +-static int snd_uac2_remove(struct platform_device *pdev) +-{ +- struct snd_card *card = platform_get_drvdata(pdev); +- +- if (card) +- return snd_card_free(card); +- +- return 0; +-} +- +-static void snd_uac2_release(struct device *dev) +-{ +- dev_dbg(dev, "releasing '%s'\n", dev_name(dev)); +-} +- +-static int alsa_uac2_init(struct audio_dev *agdev) +-{ +- struct snd_uac2_chip *uac2 = &agdev->uac2; +- int err; +- +- uac2->pdrv.probe = snd_uac2_probe; +- uac2->pdrv.remove = snd_uac2_remove; +- uac2->pdrv.driver.name = uac2_name; +- +- uac2->pdev.id = 0; +- uac2->pdev.name = uac2_name; +- uac2->pdev.dev.release = snd_uac2_release; +- +- /* Register snd_uac2 driver */ +- err = platform_driver_register(&uac2->pdrv); +- if (err) +- return err; +- +- /* Register snd_uac2 device */ +- err = platform_device_register(&uac2->pdev); +- if (err) +- platform_driver_unregister(&uac2->pdrv); +- +- return err; +-} +- +-static void alsa_uac2_exit(struct audio_dev *agdev) +-{ +- struct snd_uac2_chip *uac2 = &agdev->uac2; +- +- platform_driver_unregister(&uac2->pdrv); +- platform_device_unregister(&uac2->pdev); +-} +- +- + /* --------- USB Function Interface ------------- */ + + enum { +@@ -627,7 +134,7 @@ static struct uac_clock_source_descriptor in_clk_src_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC2_CLOCK_SOURCE, +- .bClockID = USB_IN_CLK_ID, ++ /* .bClockID = DYNAMIC */ + .bmAttributes = UAC_CLOCK_SOURCE_TYPE_INT_FIXED, + .bmControls = (CONTROL_RDONLY << CLK_FREQ_CTRL), + .bAssocTerminal = 0, +@@ -639,7 +146,7 @@ static struct uac_clock_source_descriptor out_clk_src_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC2_CLOCK_SOURCE, +- .bClockID = USB_OUT_CLK_ID, ++ /* .bClockID = DYNAMIC */ + .bmAttributes = UAC_CLOCK_SOURCE_TYPE_INT_FIXED, + .bmControls = (CONTROL_RDONLY << CLK_FREQ_CTRL), + .bAssocTerminal = 0, +@@ -651,12 +158,12 @@ static struct uac2_input_terminal_descriptor usb_out_it_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC_INPUT_TERMINAL, +- .bTerminalID = USB_OUT_IT_ID, ++ /* .bTerminalID = DYNAMIC */ + .wTerminalType = cpu_to_le16(UAC_TERMINAL_STREAMING), + .bAssocTerminal = 0, +- .bCSourceID = USB_OUT_CLK_ID, ++ /* .bCSourceID = DYNAMIC */ + .iChannelNames = 0, +- .bmControls = (CONTROL_RDWR << COPY_CTRL), ++ .bmControls = cpu_to_le16(CONTROL_RDWR << COPY_CTRL), + }; + + /* Input Terminal for I/O-In */ +@@ -665,12 +172,12 @@ static struct uac2_input_terminal_descriptor io_in_it_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC_INPUT_TERMINAL, +- .bTerminalID = IO_IN_IT_ID, ++ /* .bTerminalID = DYNAMIC */ + .wTerminalType = cpu_to_le16(UAC_INPUT_TERMINAL_UNDEFINED), + .bAssocTerminal = 0, +- .bCSourceID = USB_IN_CLK_ID, ++ /* .bCSourceID = DYNAMIC */ + .iChannelNames = 0, +- .bmControls = (CONTROL_RDWR << COPY_CTRL), ++ .bmControls = cpu_to_le16(CONTROL_RDWR << COPY_CTRL), + }; + + /* Ouput Terminal for USB_IN */ +@@ -679,12 +186,12 @@ static struct uac2_output_terminal_descriptor usb_in_ot_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, +- .bTerminalID = USB_IN_OT_ID, ++ /* .bTerminalID = DYNAMIC */ + .wTerminalType = cpu_to_le16(UAC_TERMINAL_STREAMING), + .bAssocTerminal = 0, +- .bSourceID = IO_IN_IT_ID, +- .bCSourceID = USB_IN_CLK_ID, +- .bmControls = (CONTROL_RDWR << COPY_CTRL), ++ /* .bSourceID = DYNAMIC */ ++ /* .bCSourceID = DYNAMIC */ ++ .bmControls = cpu_to_le16(CONTROL_RDWR << COPY_CTRL), + }; + + /* Ouput Terminal for I/O-Out */ +@@ -693,12 +200,12 @@ static struct uac2_output_terminal_descriptor io_out_ot_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC_OUTPUT_TERMINAL, +- .bTerminalID = IO_OUT_OT_ID, ++ /* .bTerminalID = DYNAMIC */ + .wTerminalType = cpu_to_le16(UAC_OUTPUT_TERMINAL_UNDEFINED), + .bAssocTerminal = 0, +- .bSourceID = USB_OUT_IT_ID, +- .bCSourceID = USB_OUT_CLK_ID, +- .bmControls = (CONTROL_RDWR << COPY_CTRL), ++ /* .bSourceID = DYNAMIC */ ++ /* .bCSourceID = DYNAMIC */ ++ .bmControls = cpu_to_le16(CONTROL_RDWR << COPY_CTRL), + }; + + static struct uac2_ac_header_descriptor ac_hdr_desc = { +@@ -708,9 +215,10 @@ static struct uac2_ac_header_descriptor ac_hdr_desc = { + .bDescriptorSubtype = UAC_MS_HEADER, + .bcdADC = cpu_to_le16(0x200), + .bCategory = UAC2_FUNCTION_IO_BOX, +- .wTotalLength = sizeof in_clk_src_desc + sizeof out_clk_src_desc +- + sizeof usb_out_it_desc + sizeof io_in_it_desc +- + sizeof usb_in_ot_desc + sizeof io_out_ot_desc, ++ .wTotalLength = cpu_to_le16(sizeof in_clk_src_desc ++ + sizeof out_clk_src_desc + sizeof usb_out_it_desc ++ + sizeof io_in_it_desc + sizeof usb_in_ot_desc ++ + sizeof io_out_ot_desc), + .bmControls = 0, + }; + +@@ -744,7 +252,7 @@ static struct uac2_as_header_descriptor as_out_hdr_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC_AS_GENERAL, +- .bTerminalLink = USB_OUT_IT_ID, ++ /* .bTerminalLink = DYNAMIC */ + .bmControls = 0, + .bFormatType = UAC_FORMAT_TYPE_I, + .bmFormats = cpu_to_le32(UAC_FORMAT_TYPE_I_PCM), +@@ -821,7 +329,7 @@ static struct uac2_as_header_descriptor as_in_hdr_desc = { + .bDescriptorType = USB_DT_CS_INTERFACE, + + .bDescriptorSubtype = UAC_AS_GENERAL, +- .bTerminalLink = USB_IN_OT_ID, ++ /* .bTerminalLink = DYNAMIC */ + .bmControls = 0, + .bFormatType = UAC_FORMAT_TYPE_I, + .bmFormats = cpu_to_le32(UAC_FORMAT_TYPE_I_PCM), +@@ -929,40 +437,16 @@ static struct usb_descriptor_header *hs_audio_desc[] = { + }; + + struct cntrl_cur_lay3 { +- __u32 dCUR; ++ __le32 dCUR; + }; + + struct cntrl_range_lay3 { +- __u16 wNumSubRanges; +- __u32 dMIN; +- __u32 dMAX; +- __u32 dRES; ++ __le16 wNumSubRanges; ++ __le32 dMIN; ++ __le32 dMAX; ++ __le32 dRES; + } __packed; + +-static inline void +-free_ep(struct uac2_rtd_params *prm, struct usb_ep *ep) +-{ +- struct snd_uac2_chip *uac2 = prm->uac2; +- int i; +- +- if (!prm->ep_enabled) +- return; +- +- prm->ep_enabled = false; +- +- for (i = 0; i < USB_XFERS; i++) { +- if (prm->ureq[i].req) { +- usb_ep_dequeue(ep, prm->ureq[i].req); +- usb_ep_free_request(ep, prm->ureq[i].req); +- prm->ureq[i].req = NULL; +- } +- } +- +- if (usb_ep_disable(ep)) +- dev_err(&uac2->pdev.dev, +- "%s:%d Error!\n", __func__, __LINE__); +-} +- + static void set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts, + struct usb_endpoint_descriptor *ep_desc, + unsigned int factor, bool is_playback) +@@ -986,15 +470,133 @@ static void set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts, + le16_to_cpu(ep_desc->wMaxPacketSize))); + } + ++/* Use macro to overcome line length limitation */ ++#define USBDHDR(p) (struct usb_descriptor_header *)(p) ++ ++static void setup_descriptor(struct f_uac2_opts *opts) ++{ ++ /* patch descriptors */ ++ int i = 1; /* ID's start with 1 */ ++ ++ if (EPOUT_EN(opts)) ++ usb_out_it_desc.bTerminalID = i++; ++ if (EPIN_EN(opts)) ++ io_in_it_desc.bTerminalID = i++; ++ if (EPOUT_EN(opts)) ++ io_out_ot_desc.bTerminalID = i++; ++ if (EPIN_EN(opts)) ++ usb_in_ot_desc.bTerminalID = i++; ++ if (EPOUT_EN(opts)) ++ out_clk_src_desc.bClockID = i++; ++ if (EPIN_EN(opts)) ++ in_clk_src_desc.bClockID = i++; ++ ++ usb_out_it_desc.bCSourceID = out_clk_src_desc.bClockID; ++ usb_in_ot_desc.bSourceID = io_in_it_desc.bTerminalID; ++ usb_in_ot_desc.bCSourceID = in_clk_src_desc.bClockID; ++ io_in_it_desc.bCSourceID = in_clk_src_desc.bClockID; ++ io_out_ot_desc.bCSourceID = out_clk_src_desc.bClockID; ++ io_out_ot_desc.bSourceID = usb_out_it_desc.bTerminalID; ++ as_out_hdr_desc.bTerminalLink = usb_out_it_desc.bTerminalID; ++ as_in_hdr_desc.bTerminalLink = usb_in_ot_desc.bTerminalID; ++ ++ iad_desc.bInterfaceCount = 1; ++ ac_hdr_desc.wTotalLength = 0; ++ ++ if (EPIN_EN(opts)) { ++ u16 len = le16_to_cpu(ac_hdr_desc.wTotalLength); ++ ++ len += sizeof(in_clk_src_desc); ++ len += sizeof(usb_in_ot_desc); ++ len += sizeof(io_in_it_desc); ++ ac_hdr_desc.wTotalLength = cpu_to_le16(len); ++ iad_desc.bInterfaceCount++; ++ } ++ if (EPOUT_EN(opts)) { ++ u16 len = le16_to_cpu(ac_hdr_desc.wTotalLength); ++ ++ len += sizeof(out_clk_src_desc); ++ len += sizeof(usb_out_it_desc); ++ len += sizeof(io_out_ot_desc); ++ ac_hdr_desc.wTotalLength = cpu_to_le16(len); ++ iad_desc.bInterfaceCount++; ++ } ++ ++ i = 0; ++ fs_audio_desc[i++] = USBDHDR(&iad_desc); ++ fs_audio_desc[i++] = USBDHDR(&std_ac_if_desc); ++ fs_audio_desc[i++] = USBDHDR(&ac_hdr_desc); ++ if (EPIN_EN(opts)) ++ fs_audio_desc[i++] = USBDHDR(&in_clk_src_desc); ++ if (EPOUT_EN(opts)) { ++ fs_audio_desc[i++] = USBDHDR(&out_clk_src_desc); ++ fs_audio_desc[i++] = USBDHDR(&usb_out_it_desc); ++ } ++ if (EPIN_EN(opts)) { ++ fs_audio_desc[i++] = USBDHDR(&io_in_it_desc); ++ fs_audio_desc[i++] = USBDHDR(&usb_in_ot_desc); ++ } ++ if (EPOUT_EN(opts)) { ++ fs_audio_desc[i++] = USBDHDR(&io_out_ot_desc); ++ fs_audio_desc[i++] = USBDHDR(&std_as_out_if0_desc); ++ fs_audio_desc[i++] = USBDHDR(&std_as_out_if1_desc); ++ fs_audio_desc[i++] = USBDHDR(&as_out_hdr_desc); ++ fs_audio_desc[i++] = USBDHDR(&as_out_fmt1_desc); ++ fs_audio_desc[i++] = USBDHDR(&fs_epout_desc); ++ fs_audio_desc[i++] = USBDHDR(&as_iso_out_desc); ++ } ++ if (EPIN_EN(opts)) { ++ fs_audio_desc[i++] = USBDHDR(&std_as_in_if0_desc); ++ fs_audio_desc[i++] = USBDHDR(&std_as_in_if1_desc); ++ fs_audio_desc[i++] = USBDHDR(&as_in_hdr_desc); ++ fs_audio_desc[i++] = USBDHDR(&as_in_fmt1_desc); ++ fs_audio_desc[i++] = USBDHDR(&fs_epin_desc); ++ fs_audio_desc[i++] = USBDHDR(&as_iso_in_desc); ++ } ++ fs_audio_desc[i] = NULL; ++ ++ i = 0; ++ hs_audio_desc[i++] = USBDHDR(&iad_desc); ++ hs_audio_desc[i++] = USBDHDR(&std_ac_if_desc); ++ hs_audio_desc[i++] = USBDHDR(&ac_hdr_desc); ++ if (EPIN_EN(opts)) ++ hs_audio_desc[i++] = USBDHDR(&in_clk_src_desc); ++ if (EPOUT_EN(opts)) { ++ hs_audio_desc[i++] = USBDHDR(&out_clk_src_desc); ++ hs_audio_desc[i++] = USBDHDR(&usb_out_it_desc); ++ } ++ if (EPIN_EN(opts)) { ++ hs_audio_desc[i++] = USBDHDR(&io_in_it_desc); ++ hs_audio_desc[i++] = USBDHDR(&usb_in_ot_desc); ++ } ++ if (EPOUT_EN(opts)) { ++ hs_audio_desc[i++] = USBDHDR(&io_out_ot_desc); ++ hs_audio_desc[i++] = USBDHDR(&std_as_out_if0_desc); ++ hs_audio_desc[i++] = USBDHDR(&std_as_out_if1_desc); ++ hs_audio_desc[i++] = USBDHDR(&as_out_hdr_desc); ++ hs_audio_desc[i++] = USBDHDR(&as_out_fmt1_desc); ++ hs_audio_desc[i++] = USBDHDR(&hs_epout_desc); ++ hs_audio_desc[i++] = USBDHDR(&as_iso_out_desc); ++ } ++ if (EPIN_EN(opts)) { ++ hs_audio_desc[i++] = USBDHDR(&std_as_in_if0_desc); ++ hs_audio_desc[i++] = USBDHDR(&std_as_in_if1_desc); ++ hs_audio_desc[i++] = USBDHDR(&as_in_hdr_desc); ++ hs_audio_desc[i++] = USBDHDR(&as_in_fmt1_desc); ++ hs_audio_desc[i++] = USBDHDR(&hs_epin_desc); ++ hs_audio_desc[i++] = USBDHDR(&as_iso_in_desc); ++ } ++ hs_audio_desc[i] = NULL; ++} ++ + static int + afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) + { +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; ++ struct f_uac2 *uac2 = func_to_uac2(fn); ++ struct g_audio *agdev = func_to_g_audio(fn); + struct usb_composite_dev *cdev = cfg->cdev; + struct usb_gadget *gadget = cdev->gadget; +- struct device *dev = &uac2->pdev.dev; +- struct uac2_rtd_params *prm; ++ struct device *dev = &gadget->dev; + struct f_uac2_opts *uac2_opts; + struct usb_string *us; + int ret; +@@ -1040,100 +642,103 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) + dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); + return ret; + } +- std_ac_if_desc.bInterfaceNumber = ret; +- agdev->ac_intf = ret; +- agdev->ac_alt = 0; +- +- ret = usb_interface_id(cfg, fn); +- if (ret < 0) { +- dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); +- return ret; +- } +- std_as_out_if0_desc.bInterfaceNumber = ret; +- std_as_out_if1_desc.bInterfaceNumber = ret; +- agdev->as_out_intf = ret; +- agdev->as_out_alt = 0; ++ iad_desc.bFirstInterface = ret; + +- ret = usb_interface_id(cfg, fn); +- if (ret < 0) { +- dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); +- return ret; +- } +- std_as_in_if0_desc.bInterfaceNumber = ret; +- std_as_in_if1_desc.bInterfaceNumber = ret; +- agdev->as_in_intf = ret; +- agdev->as_in_alt = 0; ++ std_ac_if_desc.bInterfaceNumber = ret; ++ uac2->ac_intf = ret; ++ uac2->ac_alt = 0; + +- agdev->out_ep = usb_ep_autoconfig(gadget, &fs_epout_desc); +- if (!agdev->out_ep) { +- dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); +- return ret; ++ if (EPOUT_EN(uac2_opts)) { ++ ret = usb_interface_id(cfg, fn); ++ if (ret < 0) { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return ret; ++ } ++ std_as_out_if0_desc.bInterfaceNumber = ret; ++ std_as_out_if1_desc.bInterfaceNumber = ret; ++ uac2->as_out_intf = ret; ++ uac2->as_out_alt = 0; + } + +- agdev->in_ep = usb_ep_autoconfig(gadget, &fs_epin_desc); +- if (!agdev->in_ep) { +- dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); +- return ret; ++ if (EPIN_EN(uac2_opts)) { ++ ret = usb_interface_id(cfg, fn); ++ if (ret < 0) { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return ret; ++ } ++ std_as_in_if0_desc.bInterfaceNumber = ret; ++ std_as_in_if1_desc.bInterfaceNumber = ret; ++ uac2->as_in_intf = ret; ++ uac2->as_in_alt = 0; + } + +- uac2->p_prm.uac2 = uac2; +- uac2->c_prm.uac2 = uac2; +- + /* Calculate wMaxPacketSize according to audio bandwidth */ + set_ep_max_packet_size(uac2_opts, &fs_epin_desc, 1000, true); + set_ep_max_packet_size(uac2_opts, &fs_epout_desc, 1000, false); + set_ep_max_packet_size(uac2_opts, &hs_epin_desc, 8000, true); + set_ep_max_packet_size(uac2_opts, &hs_epout_desc, 8000, false); + ++ if (EPOUT_EN(uac2_opts)) { ++ agdev->out_ep = usb_ep_autoconfig(gadget, &fs_epout_desc); ++ if (!agdev->out_ep) { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return -ENODEV; ++ } ++ } ++ ++ if (EPIN_EN(uac2_opts)) { ++ agdev->in_ep = usb_ep_autoconfig(gadget, &fs_epin_desc); ++ if (!agdev->in_ep) { ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ return -ENODEV; ++ } ++ } ++ ++ agdev->in_ep_maxpsize = max_t(u16, ++ le16_to_cpu(fs_epin_desc.wMaxPacketSize), ++ le16_to_cpu(hs_epin_desc.wMaxPacketSize)); ++ agdev->out_ep_maxpsize = max_t(u16, ++ le16_to_cpu(fs_epout_desc.wMaxPacketSize), ++ le16_to_cpu(hs_epout_desc.wMaxPacketSize)); ++ + hs_epout_desc.bEndpointAddress = fs_epout_desc.bEndpointAddress; + hs_epin_desc.bEndpointAddress = fs_epin_desc.bEndpointAddress; + ++ setup_descriptor(uac2_opts); ++ + ret = usb_assign_descriptors(fn, fs_audio_desc, hs_audio_desc, NULL, + NULL); + if (ret) + return ret; + +- prm = &agdev->uac2.c_prm; +- prm->max_psize = hs_epout_desc.wMaxPacketSize; +- prm->rbuf = kzalloc(prm->max_psize * USB_XFERS, GFP_KERNEL); +- if (!prm->rbuf) { +- prm->max_psize = 0; +- goto err_free_descs; +- } +- +- prm = &agdev->uac2.p_prm; +- prm->max_psize = hs_epin_desc.wMaxPacketSize; +- prm->rbuf = kzalloc(prm->max_psize * USB_XFERS, GFP_KERNEL); +- if (!prm->rbuf) { +- prm->max_psize = 0; +- goto err; +- } ++ agdev->gadget = gadget; + +- ret = alsa_uac2_init(agdev); ++ agdev->params.p_chmask = uac2_opts->p_chmask; ++ agdev->params.p_srate = uac2_opts->p_srate; ++ agdev->params.p_ssize = uac2_opts->p_ssize; ++ agdev->params.c_chmask = uac2_opts->c_chmask; ++ agdev->params.c_srate = uac2_opts->c_srate; ++ agdev->params.c_ssize = uac2_opts->c_ssize; ++ agdev->params.req_number = uac2_opts->req_number; ++ ret = g_audio_setup(agdev, "UAC2 PCM", "UAC2_Gadget"); + if (ret) +- goto err; ++ goto err_free_descs; + return 0; + +-err: +- kfree(agdev->uac2.p_prm.rbuf); +- kfree(agdev->uac2.c_prm.rbuf); + err_free_descs: + usb_free_all_descriptors(fn); +- return -EINVAL; ++ agdev->gadget = NULL; ++ return ret; + } + + static int + afunc_set_alt(struct usb_function *fn, unsigned intf, unsigned alt) + { + struct usb_composite_dev *cdev = fn->config->cdev; +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; ++ struct f_uac2 *uac2 = func_to_uac2(fn); + struct usb_gadget *gadget = cdev->gadget; +- struct device *dev = &uac2->pdev.dev; +- struct usb_request *req; +- struct usb_ep *ep; +- struct uac2_rtd_params *prm; +- int req_len, i; ++ struct device *dev = &gadget->dev; ++ int ret = 0; + + /* No i/f has more than 2 alt settings */ + if (alt > 1) { +@@ -1141,7 +746,7 @@ afunc_set_alt(struct usb_function *fn, unsigned intf, unsigned alt) + return -EINVAL; + } + +- if (intf == agdev->ac_intf) { ++ if (intf == uac2->ac_intf) { + /* Control I/f has only 1 AltSetting - 0 */ + if (alt) { + dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); +@@ -1150,96 +755,42 @@ afunc_set_alt(struct usb_function *fn, unsigned intf, unsigned alt) + return 0; + } + +- if (intf == agdev->as_out_intf) { +- ep = agdev->out_ep; +- prm = &uac2->c_prm; +- config_ep_by_speed(gadget, fn, ep); +- agdev->as_out_alt = alt; +- req_len = prm->max_psize; +- } else if (intf == agdev->as_in_intf) { +- struct f_uac2_opts *opts = agdev_to_uac2_opts(agdev); +- unsigned int factor, rate; +- struct usb_endpoint_descriptor *ep_desc; +- +- ep = agdev->in_ep; +- prm = &uac2->p_prm; +- config_ep_by_speed(gadget, fn, ep); +- agdev->as_in_alt = alt; +- +- /* pre-calculate the playback endpoint's interval */ +- if (gadget->speed == USB_SPEED_FULL) { +- ep_desc = &fs_epin_desc; +- factor = 1000; +- } else { +- ep_desc = &hs_epin_desc; +- factor = 8000; +- } +- +- /* pre-compute some values for iso_complete() */ +- uac2->p_framesize = opts->p_ssize * +- num_channels(opts->p_chmask); +- rate = opts->p_srate * uac2->p_framesize; +- uac2->p_interval = factor / (1 << (ep_desc->bInterval - 1)); +- uac2->p_pktsize = min_t(unsigned int, rate / uac2->p_interval, +- prm->max_psize); ++ if (intf == uac2->as_out_intf) { ++ uac2->as_out_alt = alt; + +- if (uac2->p_pktsize < prm->max_psize) +- uac2->p_pktsize_residue = rate % uac2->p_interval; ++ if (alt) ++ ret = u_audio_start_capture(&uac2->g_audio); + else +- uac2->p_pktsize_residue = 0; ++ u_audio_stop_capture(&uac2->g_audio); ++ } else if (intf == uac2->as_in_intf) { ++ uac2->as_in_alt = alt; + +- req_len = uac2->p_pktsize; +- uac2->p_residue = 0; ++ if (alt) ++ ret = u_audio_start_playback(&uac2->g_audio); ++ else ++ u_audio_stop_playback(&uac2->g_audio); + } else { + dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); + return -EINVAL; + } + +- if (alt == 0) { +- free_ep(prm, ep); +- return 0; +- } +- +- prm->ep_enabled = true; +- usb_ep_enable(ep); +- +- for (i = 0; i < USB_XFERS; i++) { +- if (!prm->ureq[i].req) { +- req = usb_ep_alloc_request(ep, GFP_ATOMIC); +- if (req == NULL) +- return -ENOMEM; +- +- prm->ureq[i].req = req; +- prm->ureq[i].pp = prm; +- +- req->zero = 0; +- req->context = &prm->ureq[i]; +- req->length = req_len; +- req->complete = agdev_iso_complete; +- req->buf = prm->rbuf + i * prm->max_psize; +- } +- +- if (usb_ep_queue(ep, prm->ureq[i].req, GFP_ATOMIC)) +- dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); +- } +- +- return 0; ++ return ret; + } + + static int + afunc_get_alt(struct usb_function *fn, unsigned intf) + { +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; +- +- if (intf == agdev->ac_intf) +- return agdev->ac_alt; +- else if (intf == agdev->as_out_intf) +- return agdev->as_out_alt; +- else if (intf == agdev->as_in_intf) +- return agdev->as_in_alt; ++ struct f_uac2 *uac2 = func_to_uac2(fn); ++ struct g_audio *agdev = func_to_g_audio(fn); ++ ++ if (intf == uac2->ac_intf) ++ return uac2->ac_alt; ++ else if (intf == uac2->as_out_intf) ++ return uac2->as_out_alt; ++ else if (intf == uac2->as_in_intf) ++ return uac2->as_in_alt; + else +- dev_err(&uac2->pdev.dev, ++ dev_err(&agdev->gadget->dev, + "%s:%d Invalid Interface %d!\n", + __func__, __LINE__, intf); + +@@ -1249,22 +800,19 @@ afunc_get_alt(struct usb_function *fn, unsigned intf) + static void + afunc_disable(struct usb_function *fn) + { +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; +- +- free_ep(&uac2->p_prm, agdev->in_ep); +- agdev->as_in_alt = 0; ++ struct f_uac2 *uac2 = func_to_uac2(fn); + +- free_ep(&uac2->c_prm, agdev->out_ep); +- agdev->as_out_alt = 0; ++ uac2->as_in_alt = 0; ++ uac2->as_out_alt = 0; ++ u_audio_stop_capture(&uac2->g_audio); ++ u_audio_stop_playback(&uac2->g_audio); + } + + static int + in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) + { + struct usb_request *req = fn->config->cdev->req; +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; ++ struct g_audio *agdev = func_to_g_audio(fn); + struct f_uac2_opts *opts; + u16 w_length = le16_to_cpu(cr->wLength); + u16 w_index = le16_to_cpu(cr->wIndex); +@@ -1274,7 +822,7 @@ in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) + int value = -EOPNOTSUPP; + int p_srate, c_srate; + +- opts = agdev_to_uac2_opts(agdev); ++ opts = g_audio_to_uac2_opts(agdev); + p_srate = opts->p_srate; + c_srate = opts->c_srate; + +@@ -1283,9 +831,9 @@ in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) + memset(&c, 0, sizeof(struct cntrl_cur_lay3)); + + if (entity_id == USB_IN_CLK_ID) +- c.dCUR = p_srate; ++ c.dCUR = cpu_to_le32(p_srate); + else if (entity_id == USB_OUT_CLK_ID) +- c.dCUR = c_srate; ++ c.dCUR = cpu_to_le32(c_srate); + + value = min_t(unsigned, w_length, sizeof c); + memcpy(req->buf, &c, value); +@@ -1293,7 +841,7 @@ in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) + *(u8 *)req->buf = 1; + value = min_t(unsigned, w_length, 1); + } else { +- dev_err(&uac2->pdev.dev, ++ dev_err(&agdev->gadget->dev, + "%s:%d control_selector=%d TODO!\n", + __func__, __LINE__, control_selector); + } +@@ -1305,8 +853,7 @@ static int + in_rq_range(struct usb_function *fn, const struct usb_ctrlrequest *cr) + { + struct usb_request *req = fn->config->cdev->req; +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; ++ struct g_audio *agdev = func_to_g_audio(fn); + struct f_uac2_opts *opts; + u16 w_length = le16_to_cpu(cr->wLength); + u16 w_index = le16_to_cpu(cr->wIndex); +@@ -1317,26 +864,26 @@ in_rq_range(struct usb_function *fn, const struct usb_ctrlrequest *cr) + int value = -EOPNOTSUPP; + int p_srate, c_srate; + +- opts = agdev_to_uac2_opts(agdev); ++ opts = g_audio_to_uac2_opts(agdev); + p_srate = opts->p_srate; + c_srate = opts->c_srate; + + if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) { + if (entity_id == USB_IN_CLK_ID) +- r.dMIN = p_srate; ++ r.dMIN = cpu_to_le32(p_srate); + else if (entity_id == USB_OUT_CLK_ID) +- r.dMIN = c_srate; ++ r.dMIN = cpu_to_le32(c_srate); + else + return -EOPNOTSUPP; + + r.dMAX = r.dMIN; + r.dRES = 0; +- r.wNumSubRanges = 1; ++ r.wNumSubRanges = cpu_to_le16(1); + + value = min_t(unsigned, w_length, sizeof r); + memcpy(req->buf, &r, value); + } else { +- dev_err(&uac2->pdev.dev, ++ dev_err(&agdev->gadget->dev, + "%s:%d control_selector=%d TODO!\n", + __func__, __LINE__, control_selector); + } +@@ -1371,13 +918,13 @@ out_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) + static int + setup_rq_inf(struct usb_function *fn, const struct usb_ctrlrequest *cr) + { +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; ++ struct f_uac2 *uac2 = func_to_uac2(fn); ++ struct g_audio *agdev = func_to_g_audio(fn); + u16 w_index = le16_to_cpu(cr->wIndex); + u8 intf = w_index & 0xff; + +- if (intf != agdev->ac_intf) { +- dev_err(&uac2->pdev.dev, ++ if (intf != uac2->ac_intf) { ++ dev_err(&agdev->gadget->dev, + "%s:%d Error!\n", __func__, __LINE__); + return -EOPNOTSUPP; + } +@@ -1394,8 +941,7 @@ static int + afunc_setup(struct usb_function *fn, const struct usb_ctrlrequest *cr) + { + struct usb_composite_dev *cdev = fn->config->cdev; +- struct audio_dev *agdev = func_to_agdev(fn); +- struct snd_uac2_chip *uac2 = &agdev->uac2; ++ struct g_audio *agdev = func_to_g_audio(fn); + struct usb_request *req = cdev->req; + u16 w_length = le16_to_cpu(cr->wLength); + int value = -EOPNOTSUPP; +@@ -1407,14 +953,15 @@ afunc_setup(struct usb_function *fn, const struct usb_ctrlrequest *cr) + if ((cr->bRequestType & USB_RECIP_MASK) == USB_RECIP_INTERFACE) + value = setup_rq_inf(fn, cr); + else +- dev_err(&uac2->pdev.dev, "%s:%d Error!\n", __func__, __LINE__); ++ dev_err(&agdev->gadget->dev, "%s:%d Error!\n", ++ __func__, __LINE__); + + if (value >= 0) { + req->length = value; + req->zero = value < w_length; + value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC); + if (value < 0) { +- dev_err(&uac2->pdev.dev, ++ dev_err(&agdev->gadget->dev, + "%s:%d Error!\n", __func__, __LINE__); + req->status = 0; + } +@@ -1487,6 +1034,7 @@ UAC2_ATTRIBUTE(p_ssize); + UAC2_ATTRIBUTE(c_chmask); + UAC2_ATTRIBUTE(c_srate); + UAC2_ATTRIBUTE(c_ssize); ++UAC2_ATTRIBUTE(req_number); + + static struct configfs_attribute *f_uac2_attrs[] = { + &f_uac2_opts_attr_p_chmask, +@@ -1495,6 +1043,7 @@ static struct configfs_attribute *f_uac2_attrs[] = { + &f_uac2_opts_attr_c_chmask, + &f_uac2_opts_attr_c_srate, + &f_uac2_opts_attr_c_ssize, ++ &f_uac2_opts_attr_req_number, + NULL, + }; + +@@ -1532,15 +1081,16 @@ static struct usb_function_instance *afunc_alloc_inst(void) + opts->c_chmask = UAC2_DEF_CCHMASK; + opts->c_srate = UAC2_DEF_CSRATE; + opts->c_ssize = UAC2_DEF_CSSIZE; ++ opts->req_number = UAC2_DEF_REQ_NUM; + return &opts->func_inst; + } + + static void afunc_free(struct usb_function *f) + { +- struct audio_dev *agdev; ++ struct g_audio *agdev; + struct f_uac2_opts *opts; + +- agdev = func_to_agdev(f); ++ agdev = func_to_g_audio(f); + opts = container_of(f->fi, struct f_uac2_opts, func_inst); + kfree(agdev); + mutex_lock(&opts->lock); +@@ -1550,26 +1100,21 @@ static void afunc_free(struct usb_function *f) + + static void afunc_unbind(struct usb_configuration *c, struct usb_function *f) + { +- struct audio_dev *agdev = func_to_agdev(f); +- struct uac2_rtd_params *prm; ++ struct g_audio *agdev = func_to_g_audio(f); + +- alsa_uac2_exit(agdev); +- +- prm = &agdev->uac2.p_prm; +- kfree(prm->rbuf); +- +- prm = &agdev->uac2.c_prm; +- kfree(prm->rbuf); ++ g_audio_cleanup(agdev); + usb_free_all_descriptors(f); ++ ++ agdev->gadget = NULL; + } + + static struct usb_function *afunc_alloc(struct usb_function_instance *fi) + { +- struct audio_dev *agdev; ++ struct f_uac2 *uac2; + struct f_uac2_opts *opts; + +- agdev = kzalloc(sizeof(*agdev), GFP_KERNEL); +- if (agdev == NULL) ++ uac2 = kzalloc(sizeof(*uac2), GFP_KERNEL); ++ if (uac2 == NULL) + return ERR_PTR(-ENOMEM); + + opts = container_of(fi, struct f_uac2_opts, func_inst); +@@ -1577,16 +1122,16 @@ static struct usb_function *afunc_alloc(struct usb_function_instance *fi) + ++opts->refcnt; + mutex_unlock(&opts->lock); + +- agdev->func.name = "uac2_func"; +- agdev->func.bind = afunc_bind; +- agdev->func.unbind = afunc_unbind; +- agdev->func.set_alt = afunc_set_alt; +- agdev->func.get_alt = afunc_get_alt; +- agdev->func.disable = afunc_disable; +- agdev->func.setup = afunc_setup; +- agdev->func.free_func = afunc_free; ++ uac2->g_audio.func.name = "uac2_func"; ++ uac2->g_audio.func.bind = afunc_bind; ++ uac2->g_audio.func.unbind = afunc_unbind; ++ uac2->g_audio.func.set_alt = afunc_set_alt; ++ uac2->g_audio.func.get_alt = afunc_get_alt; ++ uac2->g_audio.func.disable = afunc_disable; ++ uac2->g_audio.func.setup = afunc_setup; ++ uac2->g_audio.func.free_func = afunc_free; + +- return &agdev->func; ++ return &uac2->g_audio.func; + } + + DECLARE_USB_FUNCTION_INIT(uac2, afunc_alloc_inst, afunc_alloc); +diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c +old mode 100644 +new mode 100755 +index f8a1881609a2..01d1e6124e66 +--- a/drivers/usb/gadget/function/f_uvc.c ++++ b/drivers/usb/gadget/function/f_uvc.c +@@ -2,7 +2,7 @@ + * uvc_gadget.c -- USB Video Class Gadget driver + * + * Copyright (C) 2009-2010 +- * Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -33,8 +33,18 @@ + #include "uvc_v4l2.h" + #include "uvc_video.h" + ++bool using_cma_buf = true; ++module_param(using_cma_buf, bool, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(using_cma_buf, "0 (Use Kmalloc buf for request) / " ++ "1 (Use Cma Buf for request)"); ++ ++static int interrupt_ep_enable = 1; ++module_param(interrupt_ep_enable, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(interrupt_ep_enable, "you can choose: 0(disable), 1(enable)"); ++ + unsigned int uvc_gadget_trace_param; + ++#define EXT_MULT_MASK 10000 + /* -------------------------------------------------------------------------- + * Function descriptors + */ +@@ -69,7 +79,7 @@ static struct usb_interface_assoc_descriptor uvc_iad = { + .bLength = sizeof(uvc_iad), + .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, + .bFirstInterface = 0, +- .bInterfaceCount = 2, ++ .bInterfaceCount = 1 + MULTI_STREAM_NUM, + .bFunctionClass = USB_CLASS_VIDEO, + .bFunctionSubClass = UVC_SC_VIDEO_INTERFACE_COLLECTION, + .bFunctionProtocol = 0x00, +@@ -81,7 +91,7 @@ static struct usb_interface_descriptor uvc_control_intf = { + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = UVC_INTF_VIDEO_CONTROL, + .bAlternateSetting = 0, +- .bNumEndpoints = 1, ++ /* .bNumEndpoints = DYNAMIC */ + .bInterfaceClass = USB_CLASS_VIDEO, + .bInterfaceSubClass = UVC_SC_VIDEOCONTROL, + .bInterfaceProtocol = 0x00, +@@ -113,6 +123,70 @@ static struct uvc_control_endpoint_descriptor uvc_control_cs_ep = { + .wMaxTransferSize = cpu_to_le16(UVC_STATUS_MAX_PACKET_SIZE), + }; + ++static struct usb_interface_descriptor uvc_bulk_streaming_intf_alt0 = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, ++ .bInterfaceProtocol = 0x00, ++ .iInterface = 0, ++}; ++ ++static struct usb_endpoint_descriptor uvc_fs_bulk_streaming_ep = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = 64, ++ .bInterval = 0, ++}; ++ ++static struct usb_endpoint_descriptor uvc_hs_bulk_streaming_ep = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = 512, ++ .bInterval = 0, ++}; ++ ++static struct usb_endpoint_descriptor uvc_ss_bulk_streaming_ep = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = 1024, ++ .bInterval = 0, ++}; ++ ++static struct usb_ss_ep_comp_descriptor uvc_ss_bulk_streaming_comp = { ++ .bLength = sizeof(uvc_ss_bulk_streaming_comp), ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++ /* The following 3 values can be tweaked if necessary. */ ++ .bMaxBurst = 0, ++ .bmAttributes = 0, ++ .wBytesPerInterval = cpu_to_le16(1024), ++}; ++ ++static const struct usb_descriptor_header * const uvc_fs_bulk_streaming[] = { ++ (struct usb_descriptor_header *) &uvc_fs_bulk_streaming_ep, ++ NULL, ++}; ++ ++static const struct usb_descriptor_header * const uvc_hs_bulk_streaming[] = { ++ (struct usb_descriptor_header *) &uvc_hs_bulk_streaming_ep, ++ NULL, ++}; ++ ++static const struct usb_descriptor_header * const uvc_ss_bulk_streaming[] = { ++ (struct usb_descriptor_header *) &uvc_ss_bulk_streaming_ep, ++ (struct usb_descriptor_header *) &uvc_ss_bulk_streaming_comp, ++ NULL, ++}; ++ + static struct usb_interface_descriptor uvc_streaming_intf_alt0 = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, +@@ -179,19 +253,108 @@ static struct usb_ss_ep_comp_descriptor uvc_ss_streaming_comp = { + */ + }; + +-static const struct usb_descriptor_header * const uvc_fs_streaming[] = { ++struct uvc_streaming_desc_comp { ++ struct usb_interface_descriptor intf; ++ struct usb_endpoint_descriptor fs_endp; ++ struct usb_endpoint_descriptor hs_endp; ++ struct usb_endpoint_descriptor ss_endp; ++ struct usb_ss_ep_comp_descriptor ss_endp_comp; ++}; ++ ++#define DECLARE_STREAMING_DESCS(_num, packet_size, mult, burst, interval) \ ++[_num] = { \ ++ .intf = { \ ++ .bLength = USB_DT_INTERFACE_SIZE, \ ++ .bDescriptorType = USB_DT_INTERFACE, \ ++ .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, \ ++ .bAlternateSetting = _num + 1, \ ++ .bNumEndpoints = 1, \ ++ .bInterfaceClass = USB_CLASS_VIDEO, \ ++ .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, \ ++ .bInterfaceProtocol = 0x00, \ ++ .iInterface = 0, \ ++ }, \ ++ .fs_endp = { \ ++ .bLength = USB_DT_ENDPOINT_SIZE, \ ++ .bDescriptorType = USB_DT_ENDPOINT, \ ++ .bEndpointAddress = USB_DIR_IN, \ ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC \ ++ | USB_ENDPOINT_XFER_ISOC, \ ++ .wMaxPacketSize = packet_size, \ ++ .bInterval = interval, \ ++ }, \ ++ .hs_endp = { \ ++ .bLength = USB_DT_ENDPOINT_SIZE, \ ++ .bDescriptorType = USB_DT_ENDPOINT, \ ++ .bEndpointAddress = USB_DIR_IN, \ ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC \ ++ | USB_ENDPOINT_XFER_ISOC, \ ++ .wMaxPacketSize = packet_size | ((mult - 1) << 11), \ ++ .bInterval = interval, \ ++ }, \ ++ .ss_endp = { \ ++ .bLength = USB_DT_ENDPOINT_SIZE, \ ++ .bDescriptorType = USB_DT_ENDPOINT, \ ++ .bEndpointAddress = USB_DIR_IN, \ ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC \ ++ | USB_ENDPOINT_XFER_ISOC, \ ++ .wMaxPacketSize = packet_size, \ ++ .bInterval = interval, \ ++ }, \ ++ .ss_endp_comp = { \ ++ .bLength = sizeof(struct usb_ss_ep_comp_descriptor), \ ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, \ ++ .bMaxBurst = burst - 1, \ ++ .bmAttributes = mult - 1, \ ++ .wBytesPerInterval = burst * mult * (packet_size), \ ++ }, \ ++} ++ ++struct uvc_streaming_desc_comp uvc_streaming_comp_descs[] = { ++ DECLARE_STREAMING_DESCS(0, 64, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(1, 64, 3, 1, 1), ++ DECLARE_STREAMING_DESCS(2, 192, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(3, 192, 3, 1, 1), ++ DECLARE_STREAMING_DESCS(4, 384, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(5, 512, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(6, 640, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(7, 800, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(8, 944, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(9, 1024, 1, 1, 1), ++ DECLARE_STREAMING_DESCS(10, 640, 2, 1, 1), ++ DECLARE_STREAMING_DESCS(11, 992, 2, 1, 1), ++ DECLARE_STREAMING_DESCS(12, 1024, 2, 1, 1), ++ DECLARE_STREAMING_DESCS(13, 896, 3, 1, 1), ++ DECLARE_STREAMING_DESCS(14, 1024, 3, 1, 1), ++ DECLARE_STREAMING_DESCS(15, 1024, 3, 2, 1), ++ DECLARE_STREAMING_DESCS(16, 1024, 3, 3, 1), ++ DECLARE_STREAMING_DESCS(17, 1024, 3, 4, 1), ++ DECLARE_STREAMING_DESCS(18, 1024, 3, 5, 1), ++ DECLARE_STREAMING_DESCS(19, 1024, 3, 6, 1), ++ DECLARE_STREAMING_DESCS(20, 1024, 3, 7, 1), ++ DECLARE_STREAMING_DESCS(21, 1024, 3, 9, 1), ++ DECLARE_STREAMING_DESCS(22, 1024, 3, 10, 1), ++ DECLARE_STREAMING_DESCS(23, 1024, 3, 11, 1), ++ DECLARE_STREAMING_DESCS(24, 1024, 3, 12, 1), ++ DECLARE_STREAMING_DESCS(25, 1024, 3, 13, 1), ++ DECLARE_STREAMING_DESCS(26, 1024, 3, 14, 1), ++ DECLARE_STREAMING_DESCS(27, 1024, 3, 15, 1), ++}; ++#define MAX_STREAMING_DESC 100 ++ ++static const struct usb_descriptor_header * uvc_fs_streaming[MAX_STREAMING_DESC] = { + (struct usb_descriptor_header *) &uvc_streaming_intf_alt1, + (struct usb_descriptor_header *) &uvc_fs_streaming_ep, + NULL, + }; + +-static const struct usb_descriptor_header * const uvc_hs_streaming[] = { ++static const struct usb_descriptor_header * uvc_hs_streaming[MAX_STREAMING_DESC] = { + (struct usb_descriptor_header *) &uvc_streaming_intf_alt1, + (struct usb_descriptor_header *) &uvc_hs_streaming_ep, + NULL, + }; + +-static const struct usb_descriptor_header * const uvc_ss_streaming[] = { ++static const struct usb_descriptor_header * uvc_ss_streaming[MAX_STREAMING_DESC] = { + (struct usb_descriptor_header *) &uvc_streaming_intf_alt1, + (struct usb_descriptor_header *) &uvc_ss_streaming_ep, + (struct usb_descriptor_header *) &uvc_ss_streaming_comp, +@@ -207,6 +370,21 @@ EXPORT_SYMBOL(uvc_set_trace_param); + /* -------------------------------------------------------------------------- + * Control requests + */ ++bool uvc_function_req_match(struct usb_function *f, ++ const struct usb_ctrlrequest *ctrl, ++ bool config0) ++{ ++ if (config0) ++ return false; ++ ++ /* access condition(user define) */ ++ if ((ctrl->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) { ++ return true; ++ } ++ else { ++ return false; ++ } ++} + + static void + uvc_function_ep0_complete(struct usb_ep *ep, struct usb_request *req) +@@ -214,6 +392,9 @@ uvc_function_ep0_complete(struct usb_ep *ep, struct usb_request *req) + struct uvc_device *uvc = req->context; + struct v4l2_event v4l2_event; + struct uvc_event *uvc_event = (void *)&v4l2_event.u.data; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++#endif + + if (uvc->event_setup_out) { + uvc->event_setup_out = 0; +@@ -222,7 +403,16 @@ uvc_function_ep0_complete(struct usb_ep *ep, struct usb_request *req) + v4l2_event.type = UVC_EVENT_DATA; + uvc_event->data.length = req->actual; + memcpy(&uvc_event->data.data, req->buf, req->actual); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (stream->event_setup_out) { ++ stream->event_setup_out = 0; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ } ++ } ++#else + v4l2_event_queue(&uvc->vdev, &v4l2_event); ++#endif + } + } + +@@ -232,14 +422,17 @@ uvc_function_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + struct uvc_device *uvc = to_uvc(f); + struct v4l2_event v4l2_event; + struct uvc_event *uvc_event = (void *)&v4l2_event.u.data; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++ int first_stream_intf = 0; ++#endif + +- /* printk(KERN_INFO "setup request %02x %02x value %04x index %04x %04x\n", +- * ctrl->bRequestType, ctrl->bRequest, le16_to_cpu(ctrl->wValue), +- * le16_to_cpu(ctrl->wIndex), le16_to_cpu(ctrl->wLength)); +- */ ++ uvc_trace(UVC_TRACE_CONTROL,"setup request %02x %02x value %04x index %04x %04x\n", ++ ctrl->bRequestType, ctrl->bRequest, le16_to_cpu(ctrl->wValue), ++ le16_to_cpu(ctrl->wIndex), le16_to_cpu(ctrl->wLength)); + + if ((ctrl->bRequestType & USB_TYPE_MASK) != USB_TYPE_CLASS) { +- INFO(f->config->cdev, "invalid request type\n"); ++ uvcg_info(f, "invalid request type\n"); + return -EINVAL; + } + +@@ -256,7 +449,26 @@ uvc_function_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + memset(&v4l2_event, 0, sizeof(v4l2_event)); + v4l2_event.type = UVC_EVENT_SETUP; + memcpy(&uvc_event->req, ctrl, sizeof(uvc_event->req)); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (!first_stream_intf) ++ { ++ first_stream_intf = stream->streaming_intf; ++ } ++ ++ if (stream->streaming_intf == (le16_to_cpu(ctrl->wIndex) & 0xff)) { ++ stream->event_setup_out = uvc->event_setup_out; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ }else //only the first stream can get ep0 setup ++ if (0 == (le16_to_cpu(ctrl->wIndex) & 0xff) && ++ first_stream_intf == stream->streaming_intf) { ++ stream->event_setup_out = uvc->event_setup_out; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ } ++ } ++#else + v4l2_event_queue(&uvc->vdev, &v4l2_event); ++#endif + + return 0; + } +@@ -272,17 +484,40 @@ static int + uvc_function_get_alt(struct usb_function *f, unsigned interface) + { + struct uvc_device *uvc = to_uvc(f); ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(f->fi); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++#endif + +- INFO(f->config->cdev, "uvc_function_get_alt(%u)\n", interface); ++ uvcg_info(f, "%s(%u)\n", __func__, interface); + + if (interface == uvc->control_intf) + return 0; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (interface != stream->streaming_intf) ++ continue; ++ else ++ { ++ if (opts->bulk_streaming_ep) ++ return 0; ++ return stream->video.altsetting; ++ } ++ } ++ return -EINVAL; ++#else //CONFIG_SS_GADGET_UVC_MULTI_STREAM + else if (interface != uvc->streaming_intf) + return -EINVAL; + else +- return uvc->video.ep->enabled ? 1 : 0; ++ { ++ if (opts->bulk_streaming_ep) ++ return 0; ++ return uvc->video.altsetting; ++ } ++#endif //CONFIG_SS_GADGET_UVC_MULTI_STREAM + } + ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM + static int + uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) + { +@@ -290,22 +525,188 @@ uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) + struct usb_composite_dev *cdev = f->config->cdev; + struct v4l2_event v4l2_event; + struct uvc_event *uvc_event = (void *)&v4l2_event.u.data; +- int ret; ++ struct uvc_streaming *stream; ++ int ret, index; ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(f->fi); + +- INFO(cdev, "uvc_function_set_alt(%u, %u)\n", interface, alt); ++ uvcg_info(f, "%s(%u, %u)\n", __func__, interface, alt); + + if (interface == uvc->control_intf) { + if (alt) + return -EINVAL; + +- INFO(cdev, "reset UVC Control\n"); +- usb_ep_disable(uvc->control_ep); ++ uvcg_info(f, "reset UVC Control\n"); ++ ++ if (interrupt_ep_enable) { ++ usb_ep_disable(uvc->control_ep); ++ ++ if (!uvc->control_ep->desc) ++ if (config_ep_by_speed(cdev->gadget, f, uvc->control_ep)) ++ return -EINVAL; ++ ++ usb_ep_enable(uvc->control_ep); ++ } ++ ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (stream->state == UVC_STATE_DISCONNECTED) { ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_CONNECT; ++ uvc_event->speed = cdev->gadget->speed; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ ++ stream->state = UVC_STATE_CONNECTED; ++ } ++ } + +- if (!uvc->control_ep->desc) +- if (config_ep_by_speed(cdev->gadget, f, uvc->control_ep)) ++ return 0; ++ } ++ ++ /*if (interface != uvc->streaming_intf) ++ return -EINVAL;*/ ++ index = 0; ++ list_for_each_entry(stream, &uvc->streams, list) { ++ index++; ++ ++ if (interface != stream->streaming_intf) ++ continue; ++ ++ if (opts->bulk_streaming_ep) ++ { ++ switch (stream->state) { ++ case UVC_STATE_CONNECTED: ++ if (stream->video.ep) { ++ ret = config_ep_by_speed(f->config->cdev->gadget, ++ &(uvc->func), stream->video.ep); ++ ++ if (ret) ++ return ret; ++ usb_ep_enable(stream->video.ep); ++ ++ } else { ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMON; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ ++ stream->state = UVC_STATE_STREAMING; ++ } ++ return 0; ++ case UVC_STATE_STREAMING: ++ if (stream->video.ep) ++ usb_ep_disable(stream->video.ep); ++ ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMOFF; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ stream->state = UVC_STATE_CONNECTED; ++ return 0; ++ default: + return -EINVAL; ++ } ++ } ++ else ++ { ++ stream->video.altsetting = alt; ++ ++ switch (alt) { ++ case 0: ++ if (stream->state != UVC_STATE_STREAMING) ++ return 0; ++ ++ if (stream->video.ep) ++ usb_ep_disable(stream->video.ep); ++ ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMOFF; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ ++ stream->state = UVC_STATE_CONNECTED; ++ return 0; ++ ++ case 1: ++ default: ++ if (stream->state != UVC_STATE_CONNECTED) ++ return 0; ++ ++ if (!stream->video.ep) ++ return -EINVAL; ++ ++ uvcg_info(f, "reset UVC\n"); ++ usb_ep_disable(stream->video.ep); ++ ++ switch (f->config->cdev->gadget->speed) ++ { ++ case USB_SPEED_SUPER_PLUS: ++ case USB_SPEED_SUPER: ++ memcpy(&stream->video.ep_desc, &uvc_streaming_comp_descs[alt - 1].ss_endp, sizeof(stream->video.ep_desc)); ++ memcpy(&stream->video.ep_comp_desc, &uvc_streaming_comp_descs[alt - 1].ss_endp_comp, sizeof(stream->video.ep_comp_desc)); ++ stream->video.ep_desc.bInterval = opts->streaming_interval[index - 1]; ++ stream->video.ep_desc.bEndpointAddress = stream->video.ep->address; ++ ret = config_ep_by_endp_desc(f->config->cdev->gadget, ++ &stream->video.ep_desc, ++ &stream->video.ep_comp_desc, ++ stream->video.ep); ++ break; ++ case USB_SPEED_HIGH: ++ memcpy(&stream->video.ep_desc, &uvc_streaming_comp_descs[alt - 1].hs_endp, sizeof(stream->video.ep_desc)); ++ stream->video.ep_desc.bInterval = opts->streaming_interval[index - 1]; ++ stream->video.ep_desc.bEndpointAddress = stream->video.ep->address; ++ ret = config_ep_by_endp_desc(f->config->cdev->gadget, ++ &stream->video.ep_desc, ++ NULL, ++ stream->video.ep); ++ break; ++ default: ++ memcpy(&stream->video.ep_desc, &uvc_streaming_comp_descs[alt - 1].fs_endp, sizeof(stream->video.ep_desc)); ++ stream->video.ep_desc.bInterval = opts->streaming_interval[index - 1]; ++ stream->video.ep_desc.bEndpointAddress = stream->video.ep->address; ++ ret = config_ep_by_endp_desc(f->config->cdev->gadget, ++ &stream->video.ep_desc, ++ NULL, ++ stream->video.ep); ++ break; ++ } ++ if (ret) ++ return ret; ++ usb_ep_enable(stream->video.ep); ++ ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMON; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ //uvcg_info(f, "%s %d(%u, %u)\n", __func__, __LINE__, interface, alt); ++ return USB_GADGET_DELAYED_STATUS; ++ ++ } ++ } ++ } ++ return -EINVAL; ++} ++#else ++static int ++uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) ++{ ++ struct uvc_device *uvc = to_uvc(f); ++ struct usb_composite_dev *cdev = f->config->cdev; ++ struct v4l2_event v4l2_event; ++ struct uvc_event *uvc_event = (void *)&v4l2_event.u.data; ++ int ret; ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(f->fi); ++ uvcg_info(f, "%s(%u, %u)\n", __func__, interface, alt); ++ ++ if (interface == uvc->control_intf) { ++ if (alt) ++ return -EINVAL; ++ ++ uvcg_info(f, "reset UVC Control\n"); ++ ++ if (interrupt_ep_enable) { ++ usb_ep_disable(uvc->control_ep); + +- usb_ep_enable(uvc->control_ep); ++ if (!uvc->control_ep->desc) ++ if (config_ep_by_speed(cdev->gadget, f, uvc->control_ep)) ++ return -EINVAL; ++ ++ usb_ep_enable(uvc->control_ep); ++ } + + if (uvc->state == UVC_STATE_DISCONNECTED) { + memset(&v4l2_event, 0, sizeof(v4l2_event)); +@@ -322,68 +723,146 @@ uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) + if (interface != uvc->streaming_intf) + return -EINVAL; + +- /* TODO +- if (usb_endpoint_xfer_bulk(&uvc->desc.vs_ep)) +- return alt ? -EINVAL : 0; +- */ ++ if (opts->bulk_streaming_ep) ++ { ++ switch (uvc->state) { ++ case UVC_STATE_CONNECTED: ++ if (uvc->video.ep) { ++ ret = config_ep_by_speed(f->config->cdev->gadget, ++ &(uvc->func), uvc->video.ep); ++ ++ if (ret) ++ return ret; ++ usb_ep_enable(uvc->video.ep); ++ ++ } else { ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMON; ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ ++ uvc->state = UVC_STATE_STREAMING; ++ } ++ return 0; ++ case UVC_STATE_STREAMING: ++ if (uvc->video.ep) ++ usb_ep_disable(uvc->video.ep); + +- switch (alt) { +- case 0: +- if (uvc->state != UVC_STATE_STREAMING) ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMOFF; ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ uvc->state = UVC_STATE_CONNECTED; + return 0; ++ default: ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ uvc->video.altsetting = alt; + +- if (uvc->video.ep) +- usb_ep_disable(uvc->video.ep); ++ switch (alt) { ++ case 0: ++ if (uvc->state != UVC_STATE_STREAMING) ++ return 0; + +- memset(&v4l2_event, 0, sizeof(v4l2_event)); +- v4l2_event.type = UVC_EVENT_STREAMOFF; +- v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ if (uvc->video.ep) ++ usb_ep_disable(uvc->video.ep); + +- uvc->state = UVC_STATE_CONNECTED; +- return 0; ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMOFF; ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); + +- case 1: +- if (uvc->state != UVC_STATE_CONNECTED) ++ uvc->state = UVC_STATE_CONNECTED; + return 0; + +- if (!uvc->video.ep) +- return -EINVAL; ++ case 1: ++ default: ++ if (uvc->state != UVC_STATE_CONNECTED) ++ return 0; + +- INFO(cdev, "reset UVC\n"); +- usb_ep_disable(uvc->video.ep); ++ if (!uvc->video.ep) ++ return -EINVAL; + +- ret = config_ep_by_speed(f->config->cdev->gadget, +- &(uvc->func), uvc->video.ep); +- if (ret) +- return ret; +- usb_ep_enable(uvc->video.ep); ++ uvcg_info(f, "reset UVC\n"); ++ usb_ep_disable(uvc->video.ep); + +- memset(&v4l2_event, 0, sizeof(v4l2_event)); +- v4l2_event.type = UVC_EVENT_STREAMON; +- v4l2_event_queue(&uvc->vdev, &v4l2_event); +- return USB_GADGET_DELAYED_STATUS; ++ switch (f->config->cdev->gadget->speed) ++ { ++ case USB_SPEED_SUPER_PLUS: ++ case USB_SPEED_SUPER: ++ memcpy(&uvc->video.ep_desc, &uvc_streaming_comp_descs[alt - 1].ss_endp, sizeof(uvc->video.ep_desc)); ++ memcpy(&uvc->video.ep_comp_desc, &uvc_streaming_comp_descs[alt - 1].ss_endp_comp, sizeof(uvc->video.ep_comp_desc)); ++ uvc->video.ep_desc.bInterval = opts->streaming_interval; ++ uvc->video.ep_desc.bEndpointAddress = uvc->video.ep->address; ++ ret = config_ep_by_endp_desc(f->config->cdev->gadget, ++ &uvc->video.ep_desc, ++ &uvc->video.ep_comp_desc, ++ uvc->video.ep); ++ break; ++ case USB_SPEED_HIGH: ++ memcpy(&uvc->video.ep_desc, &uvc_streaming_comp_descs[alt - 1].hs_endp, sizeof(uvc->video.ep_desc)); ++ uvc->video.ep_desc.bInterval = opts->streaming_interval; ++ uvc->video.ep_desc.bEndpointAddress = uvc->video.ep->address; ++ ret = config_ep_by_endp_desc(f->config->cdev->gadget, ++ &uvc->video.ep_desc, ++ NULL, ++ uvc->video.ep); ++ break; ++ default: ++ memcpy(&uvc->video.ep_desc, &uvc_streaming_comp_descs[alt - 1].fs_endp, sizeof(uvc->video.ep_desc)); ++ uvc->video.ep_desc.bInterval = opts->streaming_interval; ++ uvc->video.ep_desc.bEndpointAddress = uvc->video.ep->address; ++ ret = config_ep_by_endp_desc(f->config->cdev->gadget, ++ &uvc->video.ep_desc, ++ NULL, ++ uvc->video.ep); ++ break; ++ } ++ if (ret) ++ return ret; ++ usb_ep_enable(uvc->video.ep); + +- default: +- return -EINVAL; ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMON; ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ return USB_GADGET_DELAYED_STATUS; ++ } + } + } ++#endif + + static void + uvc_function_disable(struct usb_function *f) + { + struct uvc_device *uvc = to_uvc(f); + struct v4l2_event v4l2_event; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++#endif + +- INFO(f->config->cdev, "uvc_function_disable\n"); ++ uvcg_info(f, "%s()\n", __func__); + + memset(&v4l2_event, 0, sizeof(v4l2_event)); + v4l2_event.type = UVC_EVENT_DISCONNECT; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ list_for_each_entry(stream, &uvc->streams, list) { ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ ++ stream->state = UVC_STATE_DISCONNECTED; ++ if (stream->active) ++ stream->active = 0; ++ usb_ep_disable(stream->video.ep); ++ } ++#else + v4l2_event_queue(&uvc->vdev, &v4l2_event); + + uvc->state = UVC_STATE_DISCONNECTED; + + usb_ep_disable(uvc->video.ep); +- usb_ep_disable(uvc->control_ep); ++#endif ++ ++ if (interrupt_ep_enable) ++ usb_ep_disable(uvc->control_ep); + } + + /* -------------------------------------------------------------------------- +@@ -393,32 +872,96 @@ uvc_function_disable(struct usb_function *f) + void + uvc_function_connect(struct uvc_device *uvc) + { +- struct usb_composite_dev *cdev = uvc->func.config->cdev; + int ret; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++ unsigned int n_active = 0; + ++ if (uvc->func.config->cdev->deactivations == 0) { ++ uvcg_info(&uvc->func, "May be other stream has connected done\n"); ++ return; ++ } ++ ++ if (uvc->nstreams) { ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (stream->active) ++ n_active++; ++ } ++ //printk(KERN_ERR "%s %d active:%d\n", __func__, __LINE__, n_active); ++ if (uvc->nstreams == n_active) { ++ if ((ret = usb_function_activate(&uvc->func)) < 0) ++ uvcg_info(&uvc->func, "UVC connect failed with %d\n", ret); ++ } ++ } ++#else + if ((ret = usb_function_activate(&uvc->func)) < 0) +- INFO(cdev, "UVC connect failed with %d\n", ret); ++ uvcg_info(&uvc->func, "UVC connect failed with %d\n", ret); ++#endif + } + + void + uvc_function_disconnect(struct uvc_device *uvc) + { +- struct usb_composite_dev *cdev = uvc->func.config->cdev; + int ret; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ if (uvc->func.config->cdev->deactivations) { ++ uvcg_info(&uvc->func, "May be other stream has disconnected done\n"); ++ return; ++ } ++#endif + + if ((ret = usb_function_deactivate(&uvc->func)) < 0) +- INFO(cdev, "UVC disconnect failed with %d\n", ret); ++ uvcg_info(&uvc->func, "UVC disconnect failed with %d\n", ret); + } + + /* -------------------------------------------------------------------------- + * USB probe and disconnect + */ + ++static ssize_t function_name_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct uvc_device *uvc = dev_get_drvdata(dev); ++ ++ return sprintf(buf, "%s\n", uvc->func.fi->group.cg_item.ci_name); ++} ++ ++static DEVICE_ATTR_RO(function_name); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++static int ++uvc_register_video(struct uvc_device *uvc, struct uvc_streaming *stream) ++#else + static int + uvc_register_video(struct uvc_device *uvc) ++#endif + { + struct usb_composite_dev *cdev = uvc->func.config->cdev; ++ int ret; + ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ /* TODO reference counting. */ ++ stream->vdev.v4l2_dev = &stream->v4l2_dev; ++ stream->vdev.fops = &uvc_v4l2_fops; ++ stream->vdev.ioctl_ops = &uvc_v4l2_ioctl_ops; ++ stream->vdev.release = video_device_release_empty; ++ stream->vdev.vfl_dir = VFL_DIR_TX; ++ stream->vdev.lock = &stream->video.mutex; ++ stream->vdev.device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; ++ strlcpy(stream->vdev.name, cdev->gadget->name, sizeof(stream->vdev.name)); ++ ++ stream->dev = uvc; ++ video_set_drvdata(&stream->vdev, stream); ++ ++ ret = video_register_device(&stream->vdev, VFL_TYPE_GRABBER, -1); ++ if (ret < 0) ++ return ret; ++ ++ ret = device_create_file(&stream->vdev.dev, &dev_attr_function_name); ++ if (ret < 0) { ++ video_unregister_device(&stream->vdev); ++ return ret; ++ } ++#else + /* TODO reference counting. */ + uvc->vdev.v4l2_dev = &uvc->v4l2_dev; + uvc->vdev.fops = &uvc_v4l2_fops; +@@ -426,11 +969,23 @@ uvc_register_video(struct uvc_device *uvc) + uvc->vdev.release = video_device_release_empty; + uvc->vdev.vfl_dir = VFL_DIR_TX; + uvc->vdev.lock = &uvc->video.mutex; ++ uvc->vdev.device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + strlcpy(uvc->vdev.name, cdev->gadget->name, sizeof(uvc->vdev.name)); + + video_set_drvdata(&uvc->vdev, uvc); + +- return video_register_device(&uvc->vdev, VFL_TYPE_GRABBER, -1); ++ ret = video_register_device(&uvc->vdev, VFL_TYPE_GRABBER, -1); ++ if (ret < 0) ++ return ret; ++ ++ ret = device_create_file(&uvc->vdev.dev, &dev_attr_function_name); ++ if (ret < 0) { ++ video_unregister_device(&uvc->vdev); ++ return ret; ++ } ++ ++#endif ++ return 0; + } + + #define UVC_COPY_DESCRIPTOR(mem, dst, desc) \ +@@ -449,7 +1004,244 @@ uvc_register_video(struct uvc_device *uvc) + mem += (*__src)->bLength; \ + } \ + } while (0) ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++static struct usb_descriptor_header ** ++uvc_copy_descriptors(struct uvc_device *uvc, enum usb_device_speed speed) ++{ ++ struct uvc_input_header_descriptor *uvc_streaming_header; ++ struct uvc_header_descriptor *uvc_control_header; ++ const struct uvc_descriptor_header * const *uvc_control_desc; ++ const struct uvc_descriptor_header * const *uvc_streaming_cls; ++ const struct usb_descriptor_header * const *uvc_streaming_std; ++ const struct usb_descriptor_header * const *src; ++ struct usb_descriptor_header **dst; ++ struct usb_descriptor_header **hdr; ++ unsigned int control_size; ++ unsigned int n_desc = 0; ++ unsigned int bytes = 0; ++ unsigned int index; ++ struct uvc_streaming *stream; ++ void *mem; ++ ++ struct usb_interface_descriptor *streaming_intf_alt0; ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(uvc->func.fi); ++ ++ switch (speed) { ++ case USB_SPEED_SUPER: ++ uvc_control_desc = uvc->desc.ss_control; ++ uvc_streaming_cls = uvc->desc.ss_streaming; ++ break; ++ ++ case USB_SPEED_HIGH: ++ uvc_control_desc = uvc->desc.fs_control; ++ uvc_streaming_cls = uvc->desc.hs_streaming; ++ break; ++ ++ case USB_SPEED_FULL: ++ default: ++ uvc_control_desc = uvc->desc.fs_control; ++ uvc_streaming_cls = uvc->desc.fs_streaming; ++ break; ++ } ++ ++ if (!uvc_control_desc || !uvc_streaming_cls) ++ return ERR_PTR(-ENODEV); ++ ++ /* Descriptors layout ++ * ++ * uvc_iad ++ * uvc_control_intf ++ * Class-specific UVC control descriptors ++ * uvc_control_ep ++ * uvc_control_cs_ep ++ * uvc_ss_control_comp (for SS only) ++ * uvc_streaming_intf_alt0 ++ * Class-specific UVC streaming descriptors ++ * uvc_{fs|hs}_streaming ++ */ ++ ++ if (opts->bulk_streaming_ep) ++ streaming_intf_alt0 = &uvc_bulk_streaming_intf_alt0; ++ else ++ streaming_intf_alt0 = &uvc_streaming_intf_alt0; ++ ++ /* Count descriptors and compute their size. */ ++ control_size = 0; ++ //streaming_size = 0; ++ ++ if (interrupt_ep_enable) { ++ bytes = uvc_iad.bLength + uvc_control_intf.bLength ++ + uvc_control_ep.bLength + uvc_control_cs_ep.bLength ++ + streaming_intf_alt0->bLength * uvc->nstreams; ++ ++ if (speed == USB_SPEED_SUPER) { ++ bytes += uvc_ss_control_comp.bLength; ++ n_desc = 5 + uvc->nstreams; ++ } else { ++ n_desc = 4 + uvc->nstreams; ++ } ++ } else { ++ bytes = uvc_iad.bLength + uvc_control_intf.bLength + streaming_intf_alt0->bLength * uvc->nstreams; ++ n_desc = 2 + uvc->nstreams; ++ } ++ uvcg_info(&uvc->func, "(%d)n_desc:%d bytes:%d\n", __LINE__, n_desc, bytes); ++ ++ for (src = (const struct usb_descriptor_header **)uvc_control_desc; ++ *src; ++src) { ++ control_size += (*src)->bLength; ++ bytes += (*src)->bLength; ++ n_desc++; ++ } ++ ++ index = 0; ++ list_for_each_entry(stream, &uvc->streams, list) { ++ int i = index; ++ const struct uvc_descriptor_header * const *offset = uvc_streaming_cls; ++ while(i-- > 0) ++ { ++ /* skip current stream's input header and find next */ ++ offset++; ++ while(*offset==NULL || (*offset)->bDescriptorSubType != UVC_VS_INPUT_HEADER) { ++ offset++; ++ } ++ } ++ ++ for (src = (const struct usb_descriptor_header **)offset; ++ *src; ++src) { ++ //*streaming_size += (*src)->bLength; ++ switch (speed) { ++ case USB_SPEED_SUPER: ++ stream->ss_streaming_size += (*src)->bLength; ++ break; ++ case USB_SPEED_HIGH: ++ stream->hs_streaming_size += (*src)->bLength; ++ break; ++ case USB_SPEED_FULL: ++ default: ++ stream->fs_streaming_size += (*src)->bLength; ++ break; ++ } ++ bytes += (*src)->bLength; ++ n_desc++; ++ } ++ ++ switch (speed) { ++ case USB_SPEED_SUPER: ++ uvc_streaming_std = (const struct usb_descriptor_header * const *)stream->ss_streaming_buf; ++ break; ++ case USB_SPEED_HIGH: ++ uvc_streaming_std = (const struct usb_descriptor_header * const *)stream->hs_streaming_buf; ++ break; ++ case USB_SPEED_FULL: ++ default: ++ uvc_streaming_std = (const struct usb_descriptor_header * const *)stream->fs_streaming_buf; ++ break; ++ } ++ ++ for (src = uvc_streaming_std; *src; ++src) { ++ bytes += (*src)->bLength; ++ n_desc++; ++ } ++ ++#if 0 ++ uvcg_info(&uvc->func, "(%d)n_desc:%d bytes:%d control_size:%d fs_streaming_size:%d hs_streaming_size:%d ss_streaming_size:%d\n", ++ __LINE__, n_desc, bytes, control_size, stream->fs_streaming_size, stream->hs_streaming_size, stream->ss_streaming_size); ++#endif ++ ++ index++; ++ } ++ ++ mem = kmalloc((n_desc + 1) * sizeof(*src) + bytes, GFP_KERNEL); ++ if (mem == NULL) ++ return NULL; ++ ++ hdr = mem; ++ dst = mem; ++ mem += (n_desc + 1) * sizeof(*src); + ++ /* Copy the descriptors. */ ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_iad); ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_intf); ++ ++ uvc_control_header = mem; ++ UVC_COPY_DESCRIPTORS(mem, dst, ++ (const struct usb_descriptor_header **)uvc_control_desc); ++ uvc_control_header->wTotalLength = cpu_to_le16(control_size); ++ uvc_control_header->bInCollection = uvc->nstreams; ++ index = 0; ++ list_for_each_entry(stream, &uvc->streams, list) { ++ uvc_control_header->baInterfaceNr[index++] = stream->streaming_intf; ++ } ++ ++ if (interrupt_ep_enable) { ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_ep); ++ if (speed == USB_SPEED_SUPER) ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_ss_control_comp); ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_cs_ep); ++ } ++ ++ index = 0; ++ list_for_each_entry(stream, &uvc->streams, list) { ++ int i = index; ++ const struct uvc_descriptor_header * const *offset = uvc_streaming_cls; ++ while(i-- > 0) ++ { ++ /* skip current stream's input header and find next */ ++ offset++; ++ while(*offset==NULL || (*offset)->bDescriptorSubType != UVC_VS_INPUT_HEADER) { ++ offset++; ++ } ++ } ++ ++ if (opts->bulk_streaming_ep) { ++ uvc_bulk_streaming_intf_alt0.iInterface = stream->iInterface; ++ uvc_bulk_streaming_intf_alt0.bInterfaceNumber = stream->streaming_intf; ++ } else ++ { ++ uvc_streaming_intf_alt0.iInterface = stream->iInterface; ++ uvc_streaming_intf_alt0.bInterfaceNumber = stream->streaming_intf; ++ } ++ UVC_COPY_DESCRIPTOR(mem, dst, streaming_intf_alt0); ++ ++ uvc_streaming_header = mem; ++ ++ UVC_COPY_DESCRIPTORS(mem, dst, ++ (const struct usb_descriptor_header**)offset); ++ ++ switch (speed) { ++ case USB_SPEED_SUPER: ++ uvc_streaming_header->wTotalLength = cpu_to_le16(stream->ss_streaming_size); ++ break; ++ case USB_SPEED_HIGH: ++ uvc_streaming_header->wTotalLength = cpu_to_le16(stream->hs_streaming_size); ++ break; ++ case USB_SPEED_FULL: ++ default: ++ uvc_streaming_header->wTotalLength = cpu_to_le16(stream->fs_streaming_size); ++ break; ++ } ++ uvc_streaming_header->bEndpointAddress = stream->video.ep->address; ++ ++ switch (speed) { ++ case USB_SPEED_SUPER: ++ uvc_streaming_std = (const struct usb_descriptor_header * const *)stream->ss_streaming_buf; ++ break; ++ case USB_SPEED_HIGH: ++ uvc_streaming_std = (const struct usb_descriptor_header * const *)stream->hs_streaming_buf; ++ break; ++ case USB_SPEED_FULL: ++ default: ++ uvc_streaming_std = (const struct usb_descriptor_header * const *)stream->fs_streaming_buf; ++ break; ++ } ++ UVC_COPY_DESCRIPTORS(mem, dst, uvc_streaming_std); ++ ++ index++; ++ } ++ *dst = NULL; ++ return hdr; ++} ++#else + static struct usb_descriptor_header ** + uvc_copy_descriptors(struct uvc_device *uvc, enum usb_device_speed speed) + { +@@ -467,24 +1259,33 @@ uvc_copy_descriptors(struct uvc_device *uvc, enum usb_device_speed speed) + unsigned int bytes; + void *mem; + ++ struct usb_interface_descriptor *streaming_intf_alt0; ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(uvc->func.fi); ++ + switch (speed) { + case USB_SPEED_SUPER: + uvc_control_desc = uvc->desc.ss_control; + uvc_streaming_cls = uvc->desc.ss_streaming; +- uvc_streaming_std = uvc_ss_streaming; ++ uvc_streaming_std = ++ (opts->bulk_streaming_ep)?uvc_ss_bulk_streaming: ++ uvc_ss_streaming; + break; + + case USB_SPEED_HIGH: + uvc_control_desc = uvc->desc.fs_control; + uvc_streaming_cls = uvc->desc.hs_streaming; +- uvc_streaming_std = uvc_hs_streaming; ++ uvc_streaming_std = ++ (opts->bulk_streaming_ep)?uvc_hs_bulk_streaming: ++ uvc_hs_streaming; + break; + + case USB_SPEED_FULL: + default: + uvc_control_desc = uvc->desc.fs_control; + uvc_streaming_cls = uvc->desc.fs_streaming; +- uvc_streaming_std = uvc_fs_streaming; ++ uvc_streaming_std = ++ (opts->bulk_streaming_ep)?uvc_fs_bulk_streaming: ++ uvc_fs_streaming; + break; + } + +@@ -504,28 +1305,39 @@ uvc_copy_descriptors(struct uvc_device *uvc, enum usb_device_speed speed) + * uvc_{fs|hs}_streaming + */ + ++ if (opts->bulk_streaming_ep) ++ streaming_intf_alt0 = &uvc_bulk_streaming_intf_alt0; ++ else ++ streaming_intf_alt0 = &uvc_streaming_intf_alt0; ++ + /* Count descriptors and compute their size. */ + control_size = 0; + streaming_size = 0; +- bytes = uvc_iad.bLength + uvc_control_intf.bLength +- + uvc_control_ep.bLength + uvc_control_cs_ep.bLength +- + uvc_streaming_intf_alt0.bLength; + +- if (speed == USB_SPEED_SUPER) { +- bytes += uvc_ss_control_comp.bLength; +- n_desc = 6; ++ if (interrupt_ep_enable) { ++ bytes = uvc_iad.bLength + uvc_control_intf.bLength ++ + uvc_control_ep.bLength + uvc_control_cs_ep.bLength ++ + streaming_intf_alt0->bLength; ++ ++ if (speed == USB_SPEED_SUPER) { ++ bytes += uvc_ss_control_comp.bLength; ++ n_desc = 6; ++ } else { ++ n_desc = 5; ++ } + } else { +- n_desc = 5; ++ bytes = uvc_iad.bLength + uvc_control_intf.bLength + streaming_intf_alt0->bLength; ++ n_desc = 3; + } + + for (src = (const struct usb_descriptor_header **)uvc_control_desc; +- *src; ++src) { ++ *src; ++src) { + control_size += (*src)->bLength; + bytes += (*src)->bLength; + n_desc++; + } + for (src = (const struct usb_descriptor_header **)uvc_streaming_cls; +- *src; ++src) { ++ *src; ++src) { + streaming_size += (*src)->bLength; + bytes += (*src)->bLength; + n_desc++; +@@ -554,12 +1366,14 @@ uvc_copy_descriptors(struct uvc_device *uvc, enum usb_device_speed speed) + uvc_control_header->bInCollection = 1; + uvc_control_header->baInterfaceNr[0] = uvc->streaming_intf; + +- UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_ep); +- if (speed == USB_SPEED_SUPER) +- UVC_COPY_DESCRIPTOR(mem, dst, &uvc_ss_control_comp); ++ if (interrupt_ep_enable) { ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_ep); ++ if (speed == USB_SPEED_SUPER) ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_ss_control_comp); ++ UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_cs_ep); ++ } + +- UVC_COPY_DESCRIPTOR(mem, dst, &uvc_control_cs_ep); +- UVC_COPY_DESCRIPTOR(mem, dst, &uvc_streaming_intf_alt0); ++ UVC_COPY_DESCRIPTOR(mem, dst, streaming_intf_alt0); + + uvc_streaming_header = mem; + UVC_COPY_DESCRIPTORS(mem, dst, +@@ -572,7 +1386,596 @@ uvc_copy_descriptors(struct uvc_device *uvc, enum usb_device_speed speed) + *dst = NULL; + return hdr; + } ++#endif ++ ++int uvc_function_stop(struct usb_function *f,bool streamoff) ++{ ++ struct uvc_device *uvc = to_uvc(f); ++ struct v4l2_event v4l2_event; ++ int ret = 0; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (stream->state != UVC_STATE_STREAMING) ++ continue; ++ ++ if (stream->video.ep) { ++ usb_ep_disable(stream->video.ep); ++ stream->video.ep->driver_data = NULL; ++ } ++ ++ if (streamoff) ++ { ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMOFF; ++ v4l2_event_queue(&stream->vdev, &v4l2_event); ++ } ++ stream->state = UVC_STATE_CONNECTED; ++ } ++#else ++ if (uvc->state != UVC_STATE_STREAMING) ++ return ret; ++ if (uvc->video.ep) { ++ usb_ep_disable(uvc->video.ep); ++ uvc->video.ep->driver_data = NULL; ++ } ++ if (streamoff) ++ { ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMOFF; ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ } ++ uvc->state = UVC_STATE_CONNECTED; ++#endif ++ return ret; ++} ++int uvc_function_start(struct usb_function *f,bool streamon) ++{ ++ struct uvc_device *uvc = to_uvc(f); ++ int ret = 0; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (stream->state != UVC_STATE_CONNECTED) ++ continue; ++ ++ if (!stream->video.ep) ++ continue; ++ if (stream->video.ep->driver_data) { ++ usb_ep_disable(stream->video.ep); ++ stream->video.ep->driver_data = NULL; ++ } ++ ++ ret = config_ep_by_speed(f->config->cdev->gadget, ++ &(uvc->func), stream->video.ep); ++ if (ret) ++ return ret; ++ usb_ep_enable(stream->video.ep); ++ stream->video.ep->driver_data = uvc; ++ stream->state = UVC_STATE_STREAMING; ++ } ++#else ++ if (uvc->state != UVC_STATE_CONNECTED) ++ return ret; ++ if (!uvc->video.ep) ++ return -EINVAL; ++ if (uvc->video.ep->driver_data) { ++ usb_ep_disable(uvc->video.ep); ++ uvc->video.ep->driver_data = NULL; ++ } ++ ret = config_ep_by_speed(f->config->cdev->gadget, ++ &(uvc->func), uvc->video.ep); ++ if (ret) ++ return ret; ++ usb_ep_enable(uvc->video.ep); ++ uvc->video.ep->driver_data = uvc; ++ uvc->state = UVC_STATE_STREAMING; ++#endif ++ return ret; ++} ++ ++static void ++uvc_function_suspend(struct usb_function *f) ++{ ++ uvc_function_stop(f,true); ++} ++static void ++uvc_function_resume(struct usb_function *f) ++{ ++ uvc_function_start(f,true); ++} ++ ++static inline int config_streaming_desc(struct usb_interface_descriptor *intf, ++ struct usb_endpoint_descriptor *fs_desc, struct usb_endpoint_descriptor *hs_desc, ++ struct usb_endpoint_descriptor *ss_desc, struct usb_ss_ep_comp_descriptor *ss_comp_desc) ++{ ++ int i = 0; ++ unsigned maxpacket = 0, tmp_maxpacket; ++ unsigned mult = 0, tmp_mult; ++ unsigned burst = 0, tmp_burst; ++ struct uvc_streaming_desc_comp * comp = uvc_streaming_comp_descs; ++ struct usb_descriptor_header **fs = (struct usb_descriptor_header ** )uvc_fs_streaming, ++ **hs = (struct usb_descriptor_header ** )uvc_hs_streaming, ++ **ss = (struct usb_descriptor_header ** )uvc_ss_streaming; ++ ++ unsigned int total_comp_array_size = ++ sizeof(uvc_streaming_comp_descs)/sizeof(struct uvc_streaming_desc_comp); ++ ++ //uvc_fs ++ if (fs_desc) ++ { ++ maxpacket = usb_endpoint_maxp(fs_desc) & 0x3ff; ++ for (i = 0; i < total_comp_array_size; i++) ++ { ++ tmp_maxpacket = usb_endpoint_maxp(&comp[i].fs_endp); ++ ++ if (tmp_maxpacket > maxpacket || (usb_endpoint_maxp(&comp[i].hs_endp) > 1023)) ++ continue; ++ ++ comp[i].intf.iInterface = intf->iInterface; ++ comp[i].intf.bInterfaceNumber = intf->bInterfaceNumber; ++ ++ comp[i].fs_endp.bInterval = fs_desc->bInterval; ++ comp[i].fs_endp.bEndpointAddress = fs_desc->bEndpointAddress; ++ ++ *fs++ = (struct usb_descriptor_header *)&comp[i].intf; ++ *fs++ = (struct usb_descriptor_header *)&comp[i].fs_endp; ++ ++ //printk("fs tmp_maxpacket %d\n", tmp_maxpacket); ++ } ++ *fs++ = NULL; ++ } ++ ++ if (hs_desc) ++ { ++ maxpacket = (usb_endpoint_maxp(hs_desc) & 0x7ff); ++ mult = (usb_endpoint_maxp_mult(hs_desc)); ++ ++ for (i = 0; i < total_comp_array_size; i++) ++ { ++ tmp_maxpacket = (usb_endpoint_maxp(&comp[i].hs_endp) & 0x7ff); ++ tmp_mult = usb_endpoint_maxp_mult(&comp[i].hs_endp); ++ ++ if (tmp_maxpacket > maxpacket || tmp_mult > mult || comp[i].ss_endp_comp.bMaxBurst) ++ continue; ++ ++ comp[i].intf.iInterface = intf->iInterface; ++ comp[i].intf.bInterfaceNumber = intf->bInterfaceNumber; ++ ++ comp[i].hs_endp.bInterval = hs_desc->bInterval; ++ comp[i].hs_endp.bEndpointAddress = hs_desc->bEndpointAddress; ++ ++ *hs++ = (struct usb_descriptor_header *)&comp[i].intf; ++ *hs++ = (struct usb_descriptor_header *)&comp[i].hs_endp; ++#if 0 ++ printk("hs tmp_maxpacket %d %d %d\n", tmp_maxpacket, ++ (usb_endpoint_maxp(&comp[i].hs_endp) & 0x7ff), ++ (usb_endpoint_maxp_mult(&comp[i].hs_endp))); ++#endif ++ ++ } ++ *hs++ = NULL; ++ } ++ ++ if (ss_desc && ss_comp_desc) ++ { ++ maxpacket = (usb_endpoint_maxp(ss_desc) & 0x7ff); ++ mult = ((ss_comp_desc->bmAttributes & 0x03) + 1); ++ burst = (ss_comp_desc->bMaxBurst + 1); ++ ++ for (i = 0; i < total_comp_array_size; i++) ++ { ++ tmp_maxpacket = (usb_endpoint_maxp(&comp[i].ss_endp) & 0x7ff); ++ tmp_mult = ((comp[i].ss_endp_comp.bmAttributes & 0x03) + 1); ++ tmp_burst = (comp[i].ss_endp_comp.bMaxBurst + 1); ++ ++ if (tmp_maxpacket > maxpacket || tmp_mult > mult || tmp_burst > burst) ++ continue; ++ ++ comp[i].intf.iInterface = intf->iInterface; ++ comp[i].intf.bInterfaceNumber = intf->bInterfaceNumber; ++ ++ comp[i].ss_endp.bInterval = ss_desc->bInterval; ++ comp[i].ss_endp.bEndpointAddress = ss_desc->bEndpointAddress; ++ ++ *ss++ = (struct usb_descriptor_header *)&comp[i].intf; ++ *ss++ = (struct usb_descriptor_header *)&comp[i].ss_endp; ++ *ss++ = (struct usb_descriptor_header *)&comp[i].ss_endp_comp; ++#if 0 ++ printk("ss tmp_maxpacket %d %d %d\n", tmp_maxpacket, ++ (usb_endpoint_maxp(&comp[i].ss_endp) & 0x7ff), ++ ((comp[i].ss_endp_comp.bmAttributes & 0x03) + 1)); ++#endif ++ } ++ *ss++ = NULL; ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++static int ++uvc_function_bind(struct usb_configuration *c, struct usb_function *f) ++{ ++ struct usb_composite_dev *cdev = c->cdev; ++ struct uvc_device *uvc = to_uvc(f); ++ struct usb_string *us; ++ unsigned int max_packet_mult; ++ unsigned int max_packet_size; ++ struct usb_ep *ep; ++ struct f_uvc_opts *opts; ++ const struct uvc_descriptor_header * const *uvc_control_desc; ++ const struct uvc_descriptor_header * const *tmp; ++ struct uvc_streaming *stream; ++ struct list_head *p, *n; ++ int ret = -EINVAL, index; ++ ++ uvcg_info(f, "%s()\n", __func__); ++ ++ opts = fi_to_f_uvc_opts(f->fi); ++ ++ if (interrupt_ep_enable) { ++ /* Allocate endpoints. */ ++ ep = usb_ep_autoconfig(cdev->gadget, &uvc_control_ep); ++ if (!ep) { ++ uvcg_info(f, "Unable to allocate control EP\n"); ++ goto error; ++ } ++ ++ uvc->control_ep = ep; ++ uvc_control_intf.bNumEndpoints = 1; ++ } else { ++ uvc->control_ep = NULL; ++ uvc_control_intf.bNumEndpoints = 0; ++ } ++ ++ us = usb_gstrings_attach(cdev, uvc_function_strings, ++ ARRAY_SIZE(uvc_en_us_strings)); ++ if (IS_ERR(us)) { ++ ret = PTR_ERR(us); ++ goto error; ++ } ++ uvc_iad.iFunction = us[UVC_STRING_CONTROL_IDX].id; ++ uvc_control_intf.iInterface = us[UVC_STRING_CONTROL_IDX].id; ++ ++ /* Allocate interface IDs. */ ++ if ((ret = usb_interface_id(c, f)) < 0) ++ goto error; ++ uvc_iad.bFirstInterface = ret; ++ uvc_control_intf.bInterfaceNumber = ret; ++ uvc->control_intf = ret; ++ ++ if (gadget_is_superspeed(c->cdev->gadget)) { ++ uvc_control_desc = uvc->desc.ss_control; ++ } else { ++ uvc_control_desc = uvc->desc.fs_control; ++ } ++ ++ for(tmp = uvc_control_desc, index = 0; *tmp; tmp++) { ++ if ((*tmp)->bDescriptorType == USB_DT_CS_INTERFACE && ++ (*tmp)->bDescriptorSubType == UVC_VC_OUTPUT_TERMINAL) { ++ stream = kzalloc(sizeof *stream, GFP_KERNEL); ++ if (stream == NULL) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ index++; ++ /* Sanity check the streaming endpoint module parameters. ++ */ ++ if (opts->bulk_streaming_ep) { ++ opts->streaming_maxpacket[index - 1] = clamp(opts->streaming_maxpacket[index - 1], 1U, 1024U); ++ opts->streaming_maxburst[index - 1] = min(opts->streaming_maxburst[index - 1], 15U); ++ } else ++ { ++ opts->streaming_interval[index - 1] = clamp(opts->streaming_interval[index - 1], 1U, 16U); ++ if (!(opts->streaming_maxpacket[index - 1]/EXT_MULT_MASK)) ++ { ++ opts->streaming_maxpacket[index - 1] = clamp(opts->streaming_maxpacket[index - 1], 1U, 3072U); ++ } ++ opts->streaming_maxburst[index - 1] = min(opts->streaming_maxburst[index - 1], 15U); ++ } ++ ++ /* For SS, wMaxPacketSize has to be 1024 if bMaxBurst is not 0 */ ++ if (opts->streaming_maxburst[index - 1] && (opts->streaming_maxpacket[index - 1] % 1024) != 0) ++ { ++ opts->streaming_maxpacket[index - 1] = roundup(opts->streaming_maxpacket[index - 1], 1024); ++ uvcg_info(f, "overriding streaming_maxpacket to %d\n", ++ opts->streaming_maxpacket[index - 1]); ++ } ++ ++ /* Fill in the FS/HS/SS Video Streaming specific descriptors from the ++ * module parameters. ++ * ++ * NOTE: We assume that the user knows what they are doing and won't ++ * give parameters that their UDC doesn't support. ++ */ ++ if (opts->streaming_maxpacket[index - 1] <= 1024) { ++ max_packet_mult = 1; ++ max_packet_size = opts->streaming_maxpacket[index - 1]; ++ } else if (opts->streaming_maxpacket[index - 1] <= 2048) { ++ max_packet_mult = 2; ++ max_packet_size = opts->streaming_maxpacket[index - 1] / 2; ++ } else if (opts->streaming_maxpacket[index - 1] <= 3072) { ++ max_packet_mult = 3; ++ max_packet_size = opts->streaming_maxpacket[index - 1] / 3; ++ } else { ++ max_packet_mult = opts->streaming_maxpacket[index - 1] / EXT_MULT_MASK; ++ max_packet_size = opts->streaming_maxpacket[index - 1] % EXT_MULT_MASK % 1024; ++ } ++ if (opts->bulk_streaming_ep) ++ { ++ uvc_fs_bulk_streaming_ep.wMaxPacketSize = ++ min(opts->streaming_maxpacket[index - 1], 64U); ++ uvc_hs_bulk_streaming_ep.wMaxPacketSize = ++ min(opts->streaming_maxpacket[index - 1], 512U); ++ uvc_ss_bulk_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size); ++ uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst[index - 1]; ++ uvc_ss_streaming_comp.wBytesPerInterval = ++ max_packet_size * (opts->streaming_maxburst[index - 1] + 1); ++ } ++ else ++ { ++ uvc_fs_streaming_ep.wMaxPacketSize = ++ cpu_to_le16(min(max_packet_size, 1023U)); ++ uvc_fs_streaming_ep.bInterval = opts->streaming_interval[index - 1]; ++ ++ uvc_hs_streaming_ep.wMaxPacketSize = ++ cpu_to_le16(max_packet_size | ((max_packet_mult - 1) << 11)); ++ uvc_hs_streaming_ep.bInterval = opts->streaming_interval[index - 1]; ++ ++ uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size); ++ uvc_ss_streaming_ep.bInterval = opts->streaming_interval[index - 1]; ++ uvc_ss_streaming_comp.bmAttributes = max_packet_mult - 1; ++ uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst[index - 1]; ++ uvc_ss_streaming_comp.wBytesPerInterval = ++ cpu_to_le16(max_packet_size * max_packet_mult * ++ (opts->streaming_maxburst[index - 1] + 1)); ++#if 1 ++ uvcg_info(&uvc->func, "maxpacket:0x%04x burst:%d interval:%d\n", ++ opts->streaming_maxpacket[index - 1], ++ opts->streaming_maxburst[index - 1], ++ opts->streaming_interval[index - 1]); ++#endif ++ } ++ ++ stream->dev=uvc; ++ stream->state = UVC_STATE_DISCONNECTED; ++ stream->bTerminalID = ((struct uvc_output_terminal_descriptor *)(*tmp))->bTerminalID; ++ mutex_init(&stream->video.mutex); ++ if (opts->bulk_streaming_ep) ++ { ++ ep = usb_ep_autoconfig(cdev->gadget, ++ &uvc_fs_bulk_streaming_ep); ++ } ++ else ++ { ++ if (gadget_is_superspeed(c->cdev->gadget)) { ++ ep = usb_ep_autoconfig_ss(cdev->gadget, ++ &uvc_ss_streaming_ep, ++ &uvc_ss_streaming_comp); ++ } else if (gadget_is_dualspeed(cdev->gadget)) { ++ ep = usb_ep_autoconfig(cdev->gadget, ++ &uvc_hs_streaming_ep); ++ } else { ++ ep = usb_ep_autoconfig(cdev->gadget, ++ &uvc_fs_streaming_ep); ++ } ++ } ++ ++ if (!ep) { ++ uvcg_info(f, "Unable to allocate streaming EP\n"); ++ goto error; ++ } ++ ++ stream->video.ep = ep; ++ stream->iInterface = us[UVC_STRING_STREAMING_IDX].id; ++ if ((ret = usb_interface_id(c, f)) < 0) ++ goto error; ++ stream->streaming_intf = ret; ++ uvc->nstreams++; ++ uvcg_info(f, "add stream ID:%d total:%d\n", stream->streaming_intf, uvc->nstreams); ++ list_add_tail(&stream->list, &uvc->streams); ++ ++ if (!opts->bulk_streaming_ep) { ++ uvc_streaming_intf_alt1.iInterface = stream->iInterface; ++ uvc_streaming_intf_alt1.bInterfaceNumber = stream->streaming_intf; ++ } ++ ++ if (opts->bulk_streaming_ep) { ++ uvc_fs_bulk_streaming_ep.bEndpointAddress = stream->video.ep->address; ++ uvc_hs_bulk_streaming_ep.bEndpointAddress = stream->video.ep->address; ++ uvc_ss_bulk_streaming_ep.bEndpointAddress = stream->video.ep->address; ++ } else ++ { ++ uvc_fs_streaming_ep.bEndpointAddress = stream->video.ep->address; ++ uvc_hs_streaming_ep.bEndpointAddress = stream->video.ep->address; ++ uvc_ss_streaming_ep.bEndpointAddress = stream->video.ep->address; ++ } ++ ++ if (!opts->bulk_streaming_ep) { ++ config_streaming_desc(&uvc_streaming_intf_alt1, ++ &uvc_fs_streaming_ep, &uvc_hs_streaming_ep, &uvc_ss_streaming_ep, &uvc_ss_streaming_comp); ++ } ++ ++ { ++ const struct usb_descriptor_header * const *src; ++ struct usb_descriptor_header **dst; ++ struct usb_descriptor_header **hdr; ++ unsigned int n_desc = 0; ++ unsigned int bytes = 0; ++ ++ for (src = (opts->bulk_streaming_ep) ? uvc_fs_bulk_streaming : uvc_fs_streaming; *src; ++src) { ++ n_desc++; ++ bytes += (*src)->bLength; ++ } ++ ++ stream->fs_streaming_buf = kmalloc((n_desc + 1) * sizeof(*src) + bytes, GFP_KERNEL); ++ if (stream->fs_streaming_buf == NULL) ++ goto error; ++ memset(stream->fs_streaming_buf, 0, (n_desc + 1) * sizeof(*src) + bytes); ++ ++ hdr = stream->fs_streaming_buf; ++ dst = stream->fs_streaming_buf; ++ stream->fs_streaming_buf += (n_desc + 1) * sizeof(*src); ++ ++ if (opts->bulk_streaming_ep) { ++ UVC_COPY_DESCRIPTORS(stream->fs_streaming_buf, dst, ++ (const struct usb_descriptor_header **)uvc_fs_bulk_streaming); ++ } else ++ { ++ UVC_COPY_DESCRIPTORS(stream->fs_streaming_buf, dst, ++ (const struct usb_descriptor_header **)uvc_fs_streaming); ++ } ++ ++ stream->fs_streaming_buf = hdr; ++ } ++ ++ if (gadget_is_dualspeed(cdev->gadget)) { ++ const struct usb_descriptor_header * const *src; ++ struct usb_descriptor_header **dst; ++ struct usb_descriptor_header **hdr; ++ unsigned int n_desc = 0; ++ unsigned int bytes = 0; ++ ++ for (src = (opts->bulk_streaming_ep) ? uvc_hs_bulk_streaming : uvc_hs_streaming; *src; ++src) { ++ n_desc++; ++ bytes += (*src)->bLength; ++ } ++ ++ stream->hs_streaming_buf = kmalloc((n_desc + 1) * sizeof(*src) + bytes, GFP_KERNEL); ++ if (stream->hs_streaming_buf == NULL) ++ goto error; ++ memset(stream->hs_streaming_buf, 0, (n_desc + 1) * sizeof(*src) + bytes); ++ ++ hdr = stream->hs_streaming_buf; ++ dst = stream->hs_streaming_buf; ++ stream->hs_streaming_buf += (n_desc + 1) * sizeof(*src); ++ ++ if (opts->bulk_streaming_ep) { ++ UVC_COPY_DESCRIPTORS(stream->hs_streaming_buf, dst, ++ (const struct usb_descriptor_header **)uvc_hs_bulk_streaming); ++ } else ++ { ++ UVC_COPY_DESCRIPTORS(stream->hs_streaming_buf, dst, ++ (const struct usb_descriptor_header **)uvc_hs_streaming); ++ } ++ ++ stream->hs_streaming_buf = hdr; ++ } ++ ++ if (gadget_is_superspeed(c->cdev->gadget)) { ++ const struct usb_descriptor_header * const *src; ++ struct usb_descriptor_header **dst; ++ struct usb_descriptor_header **hdr; ++ unsigned int n_desc = 0; ++ unsigned int bytes = 0; ++ ++ for (src = (opts->bulk_streaming_ep) ? uvc_ss_bulk_streaming : uvc_ss_streaming; *src; ++src) { ++ n_desc++; ++ bytes += (*src)->bLength; ++ } ++ ++ stream->ss_streaming_buf = kmalloc((n_desc + 1) * sizeof(*src) + bytes, GFP_KERNEL); ++ if (stream->ss_streaming_buf == NULL) ++ goto error; ++ memset(stream->ss_streaming_buf, 0, (n_desc + 1) * sizeof(*src) + bytes); ++ ++ hdr = stream->ss_streaming_buf; ++ dst = stream->ss_streaming_buf; ++ stream->ss_streaming_buf += (n_desc + 1) * sizeof(*src); ++ ++ if (opts->bulk_streaming_ep) { ++ UVC_COPY_DESCRIPTORS(stream->ss_streaming_buf, dst, ++ (const struct usb_descriptor_header **)uvc_ss_bulk_streaming); ++ } else ++ { ++ UVC_COPY_DESCRIPTORS(stream->ss_streaming_buf, dst, ++ (const struct usb_descriptor_header **)uvc_ss_streaming); ++ } ++ ++ stream->ss_streaming_buf = hdr; ++ } ++ } ++ } ++ ++ /* Copy descriptors */ ++ f->fs_descriptors = uvc_copy_descriptors(uvc, USB_SPEED_FULL); ++ if (IS_ERR(f->fs_descriptors)) { ++ ret = PTR_ERR(f->fs_descriptors); ++ f->fs_descriptors = NULL; ++ goto error; ++ } ++ if (gadget_is_dualspeed(cdev->gadget)) { ++ f->hs_descriptors = uvc_copy_descriptors(uvc, USB_SPEED_HIGH); ++ if (IS_ERR(f->hs_descriptors)) { ++ ret = PTR_ERR(f->hs_descriptors); ++ f->hs_descriptors = NULL; ++ goto error; ++ } ++ } ++ if (gadget_is_superspeed(c->cdev->gadget)) { ++ f->ss_descriptors = uvc_copy_descriptors(uvc, USB_SPEED_SUPER); ++ if (IS_ERR(f->ss_descriptors)) { ++ ret = PTR_ERR(f->ss_descriptors); ++ f->ss_descriptors = NULL; ++ goto error; ++ } ++ } ++ ++ /* Preallocate control endpoint request. */ ++ uvc->control_req = usb_ep_alloc_request(cdev->gadget->ep0, GFP_KERNEL); ++ uvc->control_buf = kmalloc(UVC_MAX_REQUEST_SIZE, GFP_KERNEL); ++ if (uvc->control_req == NULL || uvc->control_buf == NULL) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ uvc->control_req->buf = uvc->control_buf; ++ uvc->control_req->complete = uvc_function_ep0_complete; ++ uvc->control_req->context = uvc; + ++ list_for_each_entry(stream, &uvc->streams, list) { ++ if (v4l2_device_register(&cdev->gadget->dev, &stream->v4l2_dev)) { ++ uvcg_err(f, "failed to register V4L2 device\n"); ++ goto error; ++ } ++ ++ /* Initialise video. */ ++ ret = uvcg_video_init(&stream->video, uvc); ++ if (ret < 0) ++ goto error; ++ ++ /* Register a V4L2 device. */ ++ ret = uvc_register_video(uvc, stream); ++ if (ret < 0) { ++ uvcg_err(f, "failed to register video device\n"); ++ goto error; ++ } ++ } ++ return 0; ++ ++error: ++ list_for_each_safe(p, n, &uvc->streams) { ++ stream = list_entry(p, struct uvc_streaming, list); ++ v4l2_device_unregister(&stream->v4l2_dev); ++ ++ kfree(stream->fs_streaming_buf); ++ if (gadget_is_dualspeed(cdev->gadget)) ++ kfree(stream->hs_streaming_buf); ++ if (gadget_is_superspeed(cdev->gadget)) ++ kfree(stream->ss_streaming_buf); ++ ++ kfree(stream); ++ } ++ ++ if (uvc->control_req) ++ usb_ep_free_request(cdev->gadget->ep0, uvc->control_req); ++ kfree(uvc->control_buf); ++ ++ usb_free_all_descriptors(f); ++ return ret; ++} ++#else + static int + uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + { +@@ -585,21 +1988,30 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + struct f_uvc_opts *opts; + int ret = -EINVAL; + +- INFO(cdev, "uvc_function_bind\n"); ++ uvcg_info(f, "%s()\n", __func__); + + opts = fi_to_f_uvc_opts(f->fi); + /* Sanity check the streaming endpoint module parameters. + */ +- opts->streaming_interval = clamp(opts->streaming_interval, 1U, 16U); +- opts->streaming_maxpacket = clamp(opts->streaming_maxpacket, 1U, 3072U); +- opts->streaming_maxburst = min(opts->streaming_maxburst, 15U); ++ if (opts->bulk_streaming_ep) { ++ opts->streaming_maxpacket = clamp(opts->streaming_maxpacket, 1U, 1024U); ++ opts->streaming_maxburst = min(opts->streaming_maxburst, 15U); ++ } else ++ { ++ opts->streaming_interval = clamp(opts->streaming_interval, 1U, 16U); ++ if (!(opts->streaming_maxpacket / EXT_MULT_MASK)) ++ { ++ opts->streaming_maxpacket = clamp(opts->streaming_maxpacket, 1U, 3072U); ++ } ++ opts->streaming_maxburst = min(opts->streaming_maxburst, 15U); ++ } + + /* For SS, wMaxPacketSize has to be 1024 if bMaxBurst is not 0 */ +- if (opts->streaming_maxburst && +- (opts->streaming_maxpacket % 1024) != 0) { ++ if (opts->streaming_maxburst && (opts->streaming_maxpacket % 1024) != 0) ++ { + opts->streaming_maxpacket = roundup(opts->streaming_maxpacket, 1024); +- INFO(cdev, "overriding streaming_maxpacket to %d\n", +- opts->streaming_maxpacket); ++ uvcg_info(f, "overriding streaming_maxpacket to %d\n", ++ opts->streaming_maxpacket); + } + + /* Fill in the FS/HS/SS Video Streaming specific descriptors from the +@@ -614,52 +2026,96 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + } else if (opts->streaming_maxpacket <= 2048) { + max_packet_mult = 2; + max_packet_size = opts->streaming_maxpacket / 2; +- } else { ++ } else if (opts->streaming_maxpacket <= 3072) { + max_packet_mult = 3; + max_packet_size = opts->streaming_maxpacket / 3; ++ } else { //streaming_maxpacket: mult* EXT_MULT_MASK + maxpacket ++ max_packet_mult = opts->streaming_maxpacket / EXT_MULT_MASK; ++ max_packet_size = opts->streaming_maxpacket % EXT_MULT_MASK % 1024; ++ } ++ if (opts->bulk_streaming_ep) ++ { ++ uvc_fs_bulk_streaming_ep.wMaxPacketSize = ++ min(opts->streaming_maxpacket, 64U); ++ uvc_hs_bulk_streaming_ep.wMaxPacketSize = ++ min(opts->streaming_maxpacket, 512U); ++ uvc_ss_bulk_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size); ++ uvc_ss_bulk_streaming_comp.bMaxBurst = opts->streaming_maxburst; ++ uvc_ss_bulk_streaming_comp.wBytesPerInterval = 0; ++ } ++ else ++ { ++ uvc_fs_streaming_ep.wMaxPacketSize = ++ cpu_to_le16(min(max_packet_size, 1023U)); ++ uvc_fs_streaming_ep.bInterval = opts->streaming_interval; ++ ++ uvc_hs_streaming_ep.wMaxPacketSize = ++ cpu_to_le16(max_packet_size | ((max_packet_mult - 1) << 11)); ++ uvc_hs_streaming_ep.bInterval = opts->streaming_interval; ++ ++ uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size); ++ uvc_ss_streaming_ep.bInterval = opts->streaming_interval; ++ uvc_ss_streaming_comp.bmAttributes = max_packet_mult - 1; ++ uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst; ++ uvc_ss_streaming_comp.wBytesPerInterval = ++ cpu_to_le16(max_packet_size * max_packet_mult * ++ (opts->streaming_maxburst + 1)); + } + +- uvc_fs_streaming_ep.wMaxPacketSize = +- cpu_to_le16(min(opts->streaming_maxpacket, 1023U)); +- uvc_fs_streaming_ep.bInterval = opts->streaming_interval; +- +- uvc_hs_streaming_ep.wMaxPacketSize = +- cpu_to_le16(max_packet_size | ((max_packet_mult - 1) << 11)); +- uvc_hs_streaming_ep.bInterval = opts->streaming_interval; +- +- uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size); +- uvc_ss_streaming_ep.bInterval = opts->streaming_interval; +- uvc_ss_streaming_comp.bmAttributes = max_packet_mult - 1; +- uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst; +- uvc_ss_streaming_comp.wBytesPerInterval = +- cpu_to_le16(max_packet_size * max_packet_mult * +- (opts->streaming_maxburst + 1)); ++ if (interrupt_ep_enable) { ++ /* Allocate endpoints. */ ++ ep = usb_ep_autoconfig(cdev->gadget, &uvc_control_ep); ++ if (!ep) { ++ uvcg_info(f, "Unable to allocate control EP\n"); ++ goto error; ++ } + +- /* Allocate endpoints. */ +- ep = usb_ep_autoconfig(cdev->gadget, &uvc_control_ep); +- if (!ep) { +- INFO(cdev, "Unable to allocate control EP\n"); +- goto error; ++ uvc->control_ep = ep; ++ uvc_control_intf.bNumEndpoints = 1; ++ } else { ++ uvc->control_ep = NULL; ++ uvc_control_intf.bNumEndpoints = 0; + } +- uvc->control_ep = ep; + +- if (gadget_is_superspeed(c->cdev->gadget)) +- ep = usb_ep_autoconfig_ss(cdev->gadget, &uvc_ss_streaming_ep, +- &uvc_ss_streaming_comp); +- else if (gadget_is_dualspeed(cdev->gadget)) +- ep = usb_ep_autoconfig(cdev->gadget, &uvc_hs_streaming_ep); ++ if (opts->bulk_streaming_ep) ++ { ++ uvc_fs_bulk_streaming_ep.wMaxPacketSize = opts->streaming_maxpacket; ++ ep = usb_ep_autoconfig(cdev->gadget, ++ &uvc_fs_bulk_streaming_ep); ++ } + else +- ep = usb_ep_autoconfig(cdev->gadget, &uvc_fs_streaming_ep); ++ { ++ if (gadget_is_superspeed(c->cdev->gadget)) { ++ ep = usb_ep_autoconfig_ss(cdev->gadget, ++ &uvc_ss_streaming_ep, ++ &uvc_ss_streaming_comp); ++ } else if (gadget_is_dualspeed(cdev->gadget)) { ++ ep = usb_ep_autoconfig(cdev->gadget, ++ &uvc_hs_streaming_ep); ++ } else { ++ ep = usb_ep_autoconfig(cdev->gadget, ++ &uvc_fs_streaming_ep); ++ } ++ } + + if (!ep) { +- INFO(cdev, "Unable to allocate streaming EP\n"); ++ uvcg_info(f, "Unable to allocate streaming EP\n"); + goto error; + } + uvc->video.ep = ep; + +- uvc_fs_streaming_ep.bEndpointAddress = uvc->video.ep->address; +- uvc_hs_streaming_ep.bEndpointAddress = uvc->video.ep->address; +- uvc_ss_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ if (opts->bulk_streaming_ep) { ++ uvc_fs_bulk_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ uvc_hs_bulk_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ uvc_ss_bulk_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ } else ++ { ++ uvc_fs_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ uvc_hs_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ uvc_ss_streaming_ep.bEndpointAddress = uvc->video.ep->address; ++ } ++ ++ uvc_en_us_strings[UVC_STRING_CONTROL_IDX].s = opts->streaming_name; + + us = usb_gstrings_attach(cdev, uvc_function_strings, + ARRAY_SIZE(uvc_en_us_strings)); +@@ -667,12 +2123,18 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + ret = PTR_ERR(us); + goto error; + } ++ + uvc_iad.iFunction = us[UVC_STRING_CONTROL_IDX].id; + uvc_control_intf.iInterface = us[UVC_STRING_CONTROL_IDX].id; + ret = us[UVC_STRING_STREAMING_IDX].id; +- uvc_streaming_intf_alt0.iInterface = ret; +- uvc_streaming_intf_alt1.iInterface = ret; + ++ if (opts->bulk_streaming_ep) { ++ uvc_bulk_streaming_intf_alt0.iInterface = ret; ++ } else ++ { ++ uvc_streaming_intf_alt0.iInterface = ret; ++ uvc_streaming_intf_alt1.iInterface = ret; ++ } + /* Allocate interface IDs. */ + if ((ret = usb_interface_id(c, f)) < 0) + goto error; +@@ -682,10 +2144,23 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + + if ((ret = usb_interface_id(c, f)) < 0) + goto error; +- uvc_streaming_intf_alt0.bInterfaceNumber = ret; +- uvc_streaming_intf_alt1.bInterfaceNumber = ret; ++ ++ if (opts->bulk_streaming_ep) { ++ uvc_bulk_streaming_intf_alt0.bInterfaceNumber = ret; ++ } else ++ { ++ uvc_streaming_intf_alt0.bInterfaceNumber = ret; ++ uvc_streaming_intf_alt1.bInterfaceNumber = ret; ++ } + uvc->streaming_intf = ret; + ++ // dynamic setting of uvc_fs/hs/ss_streaming ++ if (!opts->bulk_streaming_ep) ++ { ++ config_streaming_desc(&uvc_streaming_intf_alt1, ++ &uvc_fs_streaming_ep, &uvc_hs_streaming_ep, &uvc_ss_streaming_ep, &uvc_ss_streaming_comp); ++ } ++ + /* Copy descriptors */ + f->fs_descriptors = uvc_copy_descriptors(uvc, USB_SPEED_FULL); + if (IS_ERR(f->fs_descriptors)) { +@@ -723,19 +2198,19 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + uvc->control_req->context = uvc; + + if (v4l2_device_register(&cdev->gadget->dev, &uvc->v4l2_dev)) { +- printk(KERN_INFO "v4l2_device_register failed\n"); ++ uvcg_err(f, "failed to register V4L2 device\n"); + goto error; + } + + /* Initialise video. */ +- ret = uvcg_video_init(&uvc->video); ++ ret = uvcg_video_init(&uvc->video, uvc); + if (ret < 0) + goto error; + + /* Register a V4L2 device. */ + ret = uvc_register_video(uvc); + if (ret < 0) { +- printk(KERN_INFO "Unable to register video device\n"); ++ uvcg_err(f, "failed to register video device\n"); + goto error; + } + +@@ -751,6 +2226,7 @@ error: + usb_free_all_descriptors(f); + return ret; + } ++#endif + + /* -------------------------------------------------------------------------- + * USB gadget function +@@ -845,9 +2321,10 @@ static struct usb_function_instance *uvc_alloc_inst(void) + opts->ss_control = + (const struct uvc_descriptor_header * const *)ctl_cls; + ++#ifndef CONFIG_SS_GADGET_UVC_MULTI_STREAM + opts->streaming_interval = 1; + opts->streaming_maxpacket = 1024; +- ++#endif + uvcg_attach_configfs(opts); + return &opts->func_inst; + } +@@ -856,7 +2333,7 @@ static void uvc_free(struct usb_function *f) + { + struct uvc_device *uvc = to_uvc(f); + struct f_uvc_opts *opts = container_of(f->fi, struct f_uvc_opts, +- func_inst); ++ func_inst); + --opts->refcnt; + kfree(uvc); + } +@@ -865,11 +2342,28 @@ static void uvc_unbind(struct usb_configuration *c, struct usb_function *f) + { + struct usb_composite_dev *cdev = c->cdev; + struct uvc_device *uvc = to_uvc(f); +- +- INFO(cdev, "%s\n", __func__); +- ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream; ++ struct list_head *p, *n; ++ uvcg_info(f, "%s\n", __func__); ++ ++ list_for_each_safe(p, n, &uvc->streams) { ++ stream = list_entry(p, struct uvc_streaming, list); ++ video_unregister_device(&stream->vdev); ++ v4l2_device_unregister(&stream->v4l2_dev); ++ ++ kfree(stream->fs_streaming_buf); ++ if (gadget_is_dualspeed(cdev->gadget)) ++ kfree(stream->hs_streaming_buf); ++ if (gadget_is_superspeed(cdev->gadget)) ++ kfree(stream->ss_streaming_buf); ++ ++ kfree(stream); ++ } ++#else + video_unregister_device(&uvc->vdev); + v4l2_device_unregister(&uvc->v4l2_dev); ++#endif + + usb_ep_free_request(cdev->gadget->ep0, uvc->control_req); + kfree(uvc->control_buf); +@@ -887,8 +2381,12 @@ static struct usb_function *uvc_alloc(struct usb_function_instance *fi) + if (uvc == NULL) + return ERR_PTR(-ENOMEM); + ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ INIT_LIST_HEAD(&uvc->streams); ++#else + mutex_init(&uvc->video.mutex); + uvc->state = UVC_STATE_DISCONNECTED; ++#endif + opts = fi_to_f_uvc_opts(fi); + + mutex_lock(&opts->lock); +@@ -920,11 +2418,17 @@ static struct usb_function *uvc_alloc(struct usb_function_instance *fi) + uvc->func.name = "uvc"; + uvc->func.bind = uvc_function_bind; + uvc->func.unbind = uvc_unbind; ++ uvc->func.req_match = uvc_function_req_match; + uvc->func.get_alt = uvc_function_get_alt; + uvc->func.set_alt = uvc_function_set_alt; + uvc->func.disable = uvc_function_disable; + uvc->func.setup = uvc_function_setup; + uvc->func.free_func = uvc_free; ++ if (opts->bulk_streaming_ep) ++ { ++ uvc->func.suspend = uvc_function_suspend; ++ uvc->func.resume = uvc_function_resume; ++ } + uvc->func.bind_deactivated = true; + + return &uvc->func; +diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c +new file mode 100755 +index 000000000000..4ec86fd43d37 +--- /dev/null ++++ b/drivers/usb/gadget/function/u_audio.c +@@ -0,0 +1,683 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * u_audio.c -- interface to USB gadget "ALSA sound card" utilities ++ * ++ * Copyright (C) 2016 ++ * Author: Ruslan Bilovol ++ * ++ * Sound card implementation was cut-and-pasted with changes ++ * from f_uac2.c and has: ++ * Copyright (C) 2011 ++ * Yadwinder Singh (yadi.brar01@gmail.com) ++ * Jaswinder Singh (jaswinder.singh@linaro.org) ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "u_audio.h" ++ ++#define BUFF_SIZE_MAX (PAGE_SIZE * 16) ++#define PRD_SIZE_MAX PAGE_SIZE ++#define MIN_PERIODS 4 ++ ++static int snd_uac_pcm_vol_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = CAPTURE_VOLUME_MIN; ++ uinfo->value.integer.max = CAPTURE_VOLUME_MAX; ++ uinfo->value.integer.step = CAPTURE_VOLUME_STEP; ++ return 0; ++} ++ ++static int snd_uac_pcm_vol_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct g_audio *g_audio= (struct g_audio *)kcontrol->private_data; ++ int value = g_audio->volume; ++ ucontrol->value.integer.value[0] = value; ++ return 0; ++} ++ ++static int snd_uac_pcm_vol_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int value; ++ value = ucontrol->value.integer.value[0]; ++ return 0; ++} ++ ++static struct snd_kcontrol_new snd_uac_pcm_volume = { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "Capture Volume Control", ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, ++ .index = 0, ++ .info = snd_uac_pcm_vol_info, ++ .get = snd_uac_pcm_vol_get, ++ .put = snd_uac_pcm_vol_put, ++}; ++ ++struct uac_req { ++ struct uac_rtd_params *pp; /* parent param */ ++ struct usb_request *req; ++}; ++ ++/* Runtime data params for one stream */ ++struct uac_rtd_params { ++ struct snd_uac_chip *uac; /* parent chip */ ++ bool ep_enabled; /* if the ep is enabled */ ++ ++ struct snd_pcm_substream *ss; ++ ++ /* Ring buffer */ ++ ssize_t hw_ptr; ++ ++ void *rbuf; ++ ++ unsigned int max_psize; /* MaxPacketSize of endpoint */ ++ struct uac_req *ureq; ++ ++ spinlock_t lock; ++}; ++ ++struct snd_uac_chip { ++ struct g_audio *audio_dev; ++ ++ struct uac_rtd_params p_prm; ++ struct uac_rtd_params c_prm; ++ ++ struct snd_card *card; ++ struct snd_pcm *pcm; ++ ++ /* timekeeping for the playback endpoint */ ++ unsigned int p_interval; ++ unsigned int p_residue; ++ ++ /* pre-calculated values for playback iso completion */ ++ unsigned int p_pktsize; ++ unsigned int p_pktsize_residue; ++ unsigned int p_framesize; ++ ++ struct snd_kcontrol *volume_ctl; ++}; ++ ++void g_audio_notify(struct g_audio *g_audio) ++{ ++ struct snd_card *card = g_audio->uac->card; ++ struct snd_kcontrol *ctl = g_audio->uac->volume_ctl; ++ snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_VALUE, &ctl->id); ++} ++EXPORT_SYMBOL_GPL(g_audio_notify); ++ ++static const struct snd_pcm_hardware uac_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER ++ | SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID ++ | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS, ++ .periods_max = BUFF_SIZE_MAX / PRD_SIZE_MAX, ++ .buffer_bytes_max = BUFF_SIZE_MAX, ++ .period_bytes_max = PRD_SIZE_MAX, ++ .periods_min = MIN_PERIODS, ++}; ++ ++static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ unsigned int pending; ++ unsigned long flags, flags2; ++ unsigned int hw_ptr; ++ int status = req->status; ++ struct uac_req *ur = req->context; ++ struct snd_pcm_substream *substream; ++ struct snd_pcm_runtime *runtime; ++ struct uac_rtd_params *prm = ur->pp; ++ struct snd_uac_chip *uac = prm->uac; ++ ++ /* i/f shutting down */ ++ if (!prm->ep_enabled || req->status == -ESHUTDOWN) ++ return; ++ ++ /* ++ * We can't really do much about bad xfers. ++ * Afterall, the ISOCH xfers could fail legitimately. ++ */ ++ if (status) ++ pr_debug("%s: iso_complete status(%d) %d/%d\n", ++ __func__, status, req->actual, req->length); ++ ++ substream = prm->ss; ++ ++ /* Do nothing if ALSA isn't active */ ++ if (!substream) ++ goto exit; ++ ++ snd_pcm_stream_lock_irqsave(substream, flags2); ++ ++ runtime = substream->runtime; ++ if (!runtime || !snd_pcm_running(substream)) { ++ snd_pcm_stream_unlock_irqrestore(substream, flags2); ++ goto exit; ++ } ++ ++ spin_lock_irqsave(&prm->lock, flags); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ /* ++ * For each IN packet, take the quotient of the current data ++ * rate and the endpoint's interval as the base packet size. ++ * If there is a residue from this division, add it to the ++ * residue accumulator. ++ */ ++ req->length = uac->p_pktsize; ++ uac->p_residue += uac->p_pktsize_residue; ++ ++ /* ++ * Whenever there are more bytes in the accumulator than we ++ * need to add one more sample frame, increase this packet's ++ * size and decrease the accumulator. ++ */ ++ if (uac->p_residue / uac->p_interval >= uac->p_framesize) { ++ req->length += uac->p_framesize; ++ uac->p_residue -= uac->p_framesize * ++ uac->p_interval; ++ } ++ ++ req->actual = req->length; ++ } ++ ++ hw_ptr = prm->hw_ptr; ++ ++ spin_unlock_irqrestore(&prm->lock, flags); ++ ++ /* Pack USB load in ALSA ring buffer */ ++ pending = runtime->dma_bytes - hw_ptr; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ if (unlikely(pending < req->actual)) { ++ memcpy(req->buf, runtime->dma_area + hw_ptr, pending); ++ memcpy(req->buf + pending, runtime->dma_area, ++ req->actual - pending); ++ } else { ++ memcpy(req->buf, runtime->dma_area + hw_ptr, ++ req->actual); ++ } ++ } else { ++ if (unlikely(pending < req->actual)) { ++ memcpy(runtime->dma_area + hw_ptr, req->buf, pending); ++ memcpy(runtime->dma_area, req->buf + pending, ++ req->actual - pending); ++ } else { ++ memcpy(runtime->dma_area + hw_ptr, req->buf, ++ req->actual); ++ } ++ } ++ ++ spin_lock_irqsave(&prm->lock, flags); ++ /* update hw_ptr after data is copied to memory */ ++ prm->hw_ptr = (hw_ptr + req->actual) % runtime->dma_bytes; ++ hw_ptr = prm->hw_ptr; ++ spin_unlock_irqrestore(&prm->lock, flags); ++ snd_pcm_stream_unlock_irqrestore(substream, flags2); ++ ++ if ((hw_ptr % snd_pcm_lib_period_bytes(substream)) < req->actual) ++ snd_pcm_period_elapsed(substream); ++ ++exit: ++ if (usb_ep_queue(ep, req, GFP_ATOMIC)) ++ dev_err(uac->card->dev, "%d Error!\n", __LINE__); ++} ++ ++static int uac_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct snd_uac_chip *uac = snd_pcm_substream_chip(substream); ++ struct uac_rtd_params *prm; ++ struct g_audio *audio_dev; ++ struct uac_params *params; ++ unsigned long flags; ++ int err = 0; ++ ++ audio_dev = uac->audio_dev; ++ params = &audio_dev->params; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ prm = &uac->p_prm; ++ else ++ prm = &uac->c_prm; ++ ++ spin_lock_irqsave(&prm->lock, flags); ++ ++ /* Reset */ ++ prm->hw_ptr = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ prm->ss = substream; ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ prm->ss = NULL; ++ break; ++ default: ++ err = -EINVAL; ++ } ++ ++ spin_unlock_irqrestore(&prm->lock, flags); ++ ++ /* Clear buffer after Play stops */ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && !prm->ss) ++ memset(prm->rbuf, 0, prm->max_psize * params->req_number); ++ ++ return err; ++} ++ ++static snd_pcm_uframes_t uac_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_uac_chip *uac = snd_pcm_substream_chip(substream); ++ struct uac_rtd_params *prm; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ prm = &uac->p_prm; ++ else ++ prm = &uac->c_prm; ++ ++ return bytes_to_frames(substream->runtime, prm->hw_ptr); ++} ++ ++static int uac_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *hw_params) ++{ ++ return snd_pcm_lib_malloc_pages(substream, ++ params_buffer_bytes(hw_params)); ++} ++ ++static int uac_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++static int uac_pcm_open(struct snd_pcm_substream *substream) ++{ ++ struct snd_uac_chip *uac = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct g_audio *audio_dev; ++ struct uac_params *params; ++ int p_ssize, c_ssize; ++ int p_srate, c_srate; ++ int p_chmask, c_chmask; ++ ++ audio_dev = uac->audio_dev; ++ params = &audio_dev->params; ++ p_ssize = params->p_ssize; ++ c_ssize = params->c_ssize; ++ p_srate = params->p_srate; ++ c_srate = params->c_srate; ++ p_chmask = params->p_chmask; ++ c_chmask = params->c_chmask; ++ uac->p_residue = 0; ++ ++ runtime->hw = uac_pcm_hardware; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ spin_lock_init(&uac->p_prm.lock); ++ runtime->hw.rate_min = p_srate; ++ switch (p_ssize) { ++ case 3: ++ runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_3LE; ++ break; ++ case 4: ++ runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE; ++ break; ++ default: ++ runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; ++ break; ++ } ++ runtime->hw.channels_min = num_channels(p_chmask); ++ runtime->hw.period_bytes_min = 2 * uac->p_prm.max_psize ++ / runtime->hw.periods_min; ++ } else { ++ spin_lock_init(&uac->c_prm.lock); ++ runtime->hw.rate_min = c_srate; ++ switch (c_ssize) { ++ case 3: ++ runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_3LE; ++ break; ++ case 4: ++ runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE; ++ break; ++ default: ++ runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; ++ break; ++ } ++ runtime->hw.channels_min = num_channels(c_chmask); ++ runtime->hw.period_bytes_min = 2 * uac->c_prm.max_psize ++ / runtime->hw.periods_min; ++ } ++ ++ runtime->hw.rate_max = runtime->hw.rate_min; ++ runtime->hw.channels_max = runtime->hw.channels_min; ++ ++ snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); ++ ++ return 0; ++} ++ ++/* ALSA cries without these function pointers */ ++static int uac_pcm_null(struct snd_pcm_substream *substream) ++{ ++ return 0; ++} ++ ++static const struct snd_pcm_ops uac_pcm_ops = { ++ .open = uac_pcm_open, ++ .close = uac_pcm_null, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = uac_pcm_hw_params, ++ .hw_free = uac_pcm_hw_free, ++ .trigger = uac_pcm_trigger, ++ .pointer = uac_pcm_pointer, ++ .prepare = uac_pcm_null, ++}; ++ ++static inline void free_ep(struct uac_rtd_params *prm, struct usb_ep *ep) ++{ ++ struct snd_uac_chip *uac = prm->uac; ++ struct g_audio *audio_dev; ++ struct uac_params *params; ++ int i; ++ ++ if (!prm->ep_enabled) ++ return; ++ ++ prm->ep_enabled = false; ++ ++ audio_dev = uac->audio_dev; ++ params = &audio_dev->params; ++ ++ for (i = 0; i < params->req_number; i++) { ++ if (prm->ureq[i].req) { ++ usb_ep_dequeue(ep, prm->ureq[i].req); ++ usb_ep_free_request(ep, prm->ureq[i].req); ++ prm->ureq[i].req = NULL; ++ } ++ } ++ ++ if (usb_ep_disable(ep)) ++ dev_err(uac->card->dev, "%s:%d Error!\n", __func__, __LINE__); ++} ++ ++ ++int u_audio_start_capture(struct g_audio *audio_dev) ++{ ++ struct snd_uac_chip *uac = audio_dev->uac; ++ struct usb_gadget *gadget = audio_dev->gadget; ++ struct device *dev = &gadget->dev; ++ struct usb_request *req; ++ struct usb_ep *ep; ++ struct uac_rtd_params *prm; ++ struct uac_params *params = &audio_dev->params; ++ int req_len, i; ++ ++ ep = audio_dev->out_ep; ++ prm = &uac->c_prm; ++ config_ep_by_speed(gadget, &audio_dev->func, ep); ++ req_len = prm->max_psize; ++ ++ prm->ep_enabled = true; ++ usb_ep_enable(ep); ++ ++ for (i = 0; i < params->req_number; i++) { ++ if (!prm->ureq[i].req) { ++ req = usb_ep_alloc_request(ep, GFP_ATOMIC); ++ if (req == NULL) ++ return -ENOMEM; ++ ++ prm->ureq[i].req = req; ++ prm->ureq[i].pp = prm; ++ ++ req->zero = 0; ++ req->context = &prm->ureq[i]; ++ req->length = req_len; ++ req->complete = u_audio_iso_complete; ++ req->buf = prm->rbuf + i * prm->max_psize; ++ } ++ ++ if (usb_ep_queue(ep, prm->ureq[i].req, GFP_ATOMIC)) ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(u_audio_start_capture); ++ ++void u_audio_stop_capture(struct g_audio *audio_dev) ++{ ++ struct snd_uac_chip *uac = audio_dev->uac; ++ ++ free_ep(&uac->c_prm, audio_dev->out_ep); ++} ++EXPORT_SYMBOL_GPL(u_audio_stop_capture); ++ ++int u_audio_start_playback(struct g_audio *audio_dev) ++{ ++ struct snd_uac_chip *uac = audio_dev->uac; ++ struct usb_gadget *gadget = audio_dev->gadget; ++ struct device *dev = &gadget->dev; ++ struct usb_request *req; ++ struct usb_ep *ep; ++ struct uac_rtd_params *prm; ++ struct uac_params *params = &audio_dev->params; ++ unsigned int factor, rate; ++ const struct usb_endpoint_descriptor *ep_desc; ++ int req_len, i; ++ ++ ep = audio_dev->in_ep; ++ prm = &uac->p_prm; ++ config_ep_by_speed(gadget, &audio_dev->func, ep); ++ ++ ep_desc = ep->desc; ++ ++ /* pre-calculate the playback endpoint's interval */ ++ if (gadget->speed == USB_SPEED_FULL) ++ factor = 1000; ++ else ++ factor = 8000; ++ ++ /* pre-compute some values for iso_complete() */ ++ uac->p_framesize = params->p_ssize * ++ num_channels(params->p_chmask); ++ rate = params->p_srate * uac->p_framesize; ++ uac->p_interval = factor / (1 << (ep_desc->bInterval - 1)); ++ uac->p_pktsize = min_t(unsigned int, rate / uac->p_interval, ++ prm->max_psize); ++ ++ if (uac->p_pktsize < prm->max_psize) ++ uac->p_pktsize_residue = rate % uac->p_interval; ++ else ++ uac->p_pktsize_residue = 0; ++ ++ req_len = uac->p_pktsize; ++ uac->p_residue = 0; ++ ++ prm->ep_enabled = true; ++ usb_ep_enable(ep); ++ ++ for (i = 0; i < params->req_number; i++) { ++ if (!prm->ureq[i].req) { ++ req = usb_ep_alloc_request(ep, GFP_ATOMIC); ++ if (req == NULL) ++ return -ENOMEM; ++ ++ prm->ureq[i].req = req; ++ prm->ureq[i].pp = prm; ++ ++ req->zero = 0; ++ req->context = &prm->ureq[i]; ++ req->length = req_len; ++ req->complete = u_audio_iso_complete; ++ req->buf = prm->rbuf + i * prm->max_psize; ++ } ++ ++ if (usb_ep_queue(ep, prm->ureq[i].req, GFP_ATOMIC)) ++ dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(u_audio_start_playback); ++ ++void u_audio_stop_playback(struct g_audio *audio_dev) ++{ ++ struct snd_uac_chip *uac = audio_dev->uac; ++ ++ free_ep(&uac->p_prm, audio_dev->in_ep); ++} ++EXPORT_SYMBOL_GPL(u_audio_stop_playback); ++ ++int g_audio_setup(struct g_audio *g_audio, const char *pcm_name, ++ const char *card_name) ++{ ++ struct snd_uac_chip *uac; ++ struct snd_card *card; ++ struct snd_pcm *pcm; ++ struct uac_params *params; ++ int p_chmask, c_chmask; ++ int err; ++ ++ if (!g_audio) ++ return -EINVAL; ++ ++ uac = kzalloc(sizeof(*uac), GFP_KERNEL); ++ if (!uac) ++ return -ENOMEM; ++ g_audio->uac = uac; ++ uac->audio_dev = g_audio; ++ ++ params = &g_audio->params; ++ p_chmask = params->p_chmask; ++ c_chmask = params->c_chmask; ++ ++ if (c_chmask) { ++ struct uac_rtd_params *prm = &uac->c_prm; ++ ++ uac->c_prm.uac = uac; ++ prm->max_psize = g_audio->out_ep_maxpsize; ++ ++ prm->ureq = kcalloc(params->req_number, sizeof(struct uac_req), ++ GFP_KERNEL); ++ if (!prm->ureq) { ++ err = -ENOMEM; ++ goto fail; ++ } ++ ++ prm->rbuf = kcalloc(params->req_number, prm->max_psize, ++ GFP_KERNEL); ++ if (!prm->rbuf) { ++ prm->max_psize = 0; ++ err = -ENOMEM; ++ goto fail; ++ } ++ } ++ ++ if (p_chmask) { ++ struct uac_rtd_params *prm = &uac->p_prm; ++ ++ uac->p_prm.uac = uac; ++ prm->max_psize = g_audio->in_ep_maxpsize; ++ ++ prm->ureq = kcalloc(params->req_number, sizeof(struct uac_req), ++ GFP_KERNEL); ++ if (!prm->ureq) { ++ err = -ENOMEM; ++ goto fail; ++ } ++ ++ prm->rbuf = kcalloc(params->req_number, prm->max_psize, ++ GFP_KERNEL); ++ if (!prm->rbuf) { ++ prm->max_psize = 0; ++ err = -ENOMEM; ++ goto fail; ++ } ++ } ++ ++ /* Choose any slot, with no id */ ++ err = snd_card_new(&g_audio->gadget->dev, ++ -1, NULL, THIS_MODULE, 0, &card); ++ if (err < 0) ++ goto fail; ++ ++ uac->card = card; ++ ++ /* ++ * Create first PCM device ++ * Create a substream only for non-zero channel streams ++ */ ++ err = snd_pcm_new(uac->card, pcm_name, 0, ++ p_chmask ? 1 : 0, c_chmask ? 1 : 0, &pcm); ++ if (err < 0) ++ goto snd_fail; ++ ++ strlcpy(pcm->name, pcm_name, sizeof(pcm->name)); ++ pcm->private_data = uac; ++ uac->pcm = pcm; ++ ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &uac_pcm_ops); ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &uac_pcm_ops); ++ ++ strlcpy(card->driver, card_name, sizeof(card->driver)); ++ strlcpy(card->shortname, card_name, sizeof(card->shortname)); ++ sprintf(card->longname, "%s %i", card_name, card->dev->id); ++ ++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data(GFP_KERNEL), 0, BUFF_SIZE_MAX); ++ ++ uac->volume_ctl = snd_ctl_new1(&snd_uac_pcm_volume, g_audio); ++ if ((err = snd_ctl_add(card, uac->volume_ctl)) < 0) ++ return err; ++ ++ err = snd_card_register(card); ++ ++ if (!err) ++ return 0; ++ ++snd_fail: ++ snd_card_free(card); ++fail: ++ kfree(uac->p_prm.ureq); ++ kfree(uac->c_prm.ureq); ++ kfree(uac->p_prm.rbuf); ++ kfree(uac->c_prm.rbuf); ++ kfree(uac); ++ ++ return err; ++} ++EXPORT_SYMBOL_GPL(g_audio_setup); ++ ++void g_audio_cleanup(struct g_audio *g_audio) ++{ ++ struct snd_uac_chip *uac; ++ struct snd_card *card; ++ ++ if (!g_audio || !g_audio->uac) ++ return; ++ ++ uac = g_audio->uac; ++ card = uac->card; ++ if (card) ++ snd_card_free(card); ++ ++ kfree(uac->p_prm.ureq); ++ kfree(uac->c_prm.ureq); ++ kfree(uac->p_prm.rbuf); ++ kfree(uac->c_prm.rbuf); ++ kfree(uac); ++} ++EXPORT_SYMBOL_GPL(g_audio_cleanup); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("USB gadget \"ALSA sound card\" utilities"); ++MODULE_AUTHOR("Ruslan Bilovol"); +diff --git a/drivers/usb/gadget/function/u_audio.h b/drivers/usb/gadget/function/u_audio.h +new file mode 100755 +index 000000000000..8caf63363775 +--- /dev/null ++++ b/drivers/usb/gadget/function/u_audio.h +@@ -0,0 +1,103 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * u_audio.h -- interface to USB gadget "ALSA sound card" utilities ++ * ++ * Copyright (C) 2016 ++ * Author: Ruslan Bilovol ++ */ ++ ++#ifndef __U_AUDIO_H ++#define __U_AUDIO_H ++ ++#include ++ ++#include ++#include ++#include ++ ++struct uac_params { ++ /* playback */ ++ int p_chmask; /* channel mask */ ++ int p_srate; /* rate in Hz */ ++ int p_ssize; /* sample size */ ++ ++ /* capture */ ++ int c_chmask; /* channel mask */ ++ int c_srate; /* rate in Hz */ ++ int c_ssize; /* sample size */ ++ ++ int req_number; /* number of preallocated requests */ ++}; ++ ++struct g_audio { ++ struct usb_function func; ++ struct usb_gadget *gadget; ++ ++ struct usb_ep *in_ep; ++ struct usb_ep *out_ep; ++ ++ /* Max packet size for all in_ep possible speeds */ ++ unsigned int in_ep_maxpsize; ++ /* Max packet size for all out_ep possible speeds */ ++ unsigned int out_ep_maxpsize; ++ ++ /* The ALSA Sound Card it represents on the USB-Client side */ ++ struct snd_uac_chip *uac; ++ ++ struct uac_params params; ++ ++ int volume ; ++}; ++ ++static inline struct g_audio *func_to_g_audio(struct usb_function *f) ++{ ++ return container_of(f, struct g_audio, func); ++} ++ ++static inline uint num_channels(uint chanmask) ++{ ++ uint num = 0; ++ ++ while (chanmask) { ++ num += (chanmask & 1); ++ chanmask >>= 1; ++ } ++ ++ return num; ++} ++ ++/* ++ * g_audio_setup - initialize one virtual ALSA sound card ++ * @g_audio: struct with filled params, in_ep_maxpsize, out_ep_maxpsize ++ * @pcm_name: the id string for a PCM instance of this sound card ++ * @card_name: name of this soundcard ++ * ++ * This sets up the single virtual ALSA sound card that may be exported by a ++ * gadget driver using this framework. ++ * ++ * Context: may sleep ++ * ++ * Returns zero on success, or a negative error on failure. ++ */ ++void g_audio_notify(struct g_audio *g_audio); ++int g_audio_setup(struct g_audio *g_audio, const char *pcm_name, ++ const char *card_name); ++void g_audio_cleanup(struct g_audio *g_audio); ++ ++int u_audio_start_capture(struct g_audio *g_audio); ++void u_audio_stop_capture(struct g_audio *g_audio); ++int u_audio_start_playback(struct g_audio *g_audio); ++void u_audio_stop_playback(struct g_audio *g_audio); ++ ++ ++#define UAC_VOLUME_STEP (256) ++#define CAPTURE_VOLUME_ID (0) ++#define CAPTURE_VOLUME_MAX (10) ++#define CAPTURE_VOLUME_MIN (-10) ++#define CAPTURE_VOLUME_STEP (1) ++#define CAPTURE_VOLUME_CUR (CAPTURE_VOLUME_MAX) ++ ++#define UAC_VOLUME_ATTR_TO_DB(attr) (s8)((short)attr / UAC_VOLUME_STEP) ++#define DB_TO_UAC_VOLUME_ATTR(db) (short)(db * UAC_VOLUME_STEP) ++ ++#endif /* __U_AUDIO_H */ +diff --git a/drivers/usb/gadget/function/u_bi_direction.c b/drivers/usb/gadget/function/u_bi_direction.c +new file mode 100644 +index 000000000000..f6615a82055c +--- /dev/null ++++ b/drivers/usb/gadget/function/u_bi_direction.c +@@ -0,0 +1,1235 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "u_bi_direction.h" ++#include "u_f.h" ++ ++#if (USB_PROC_DEBUG_ENABLE==1) ++#include ++#include ++#endif ++ ++extern unsigned int log_level; ++ ++/* ++ 1. buffer_queue_deinit ++ 2. buffer_queue_init ++ 3. buffer_queue_find_buf ++ 4. buffer_queue_find_free_buf ++ 5. buffer_queue_finish_buf ++ 6. buffer_queue_queue_data ++ 7. buffer_queue_dequeue_data ++ 8. buffer_queue_is_empty ++ 9. buffer_queue_used_list_is_empty ++ 10. buffer_queue_reset ++ */ ++static int buffer_queue_deinit(bi_buffer_queue_t *queue) ++{ ++ int i; ++ ++ BDBG(" Enter\n"); ++ if(!queue->inited) ++ return 0; ++ ++ for(i = 0; i < queue->qlen; i++) ++ { ++ if(queue->buf[i].buf.vaddr) ++ vfree(queue->buf[i].buf.vaddr); ++ } ++ kfree(queue->buf); ++ queue->buf = NULL; ++ queue->qlen = 0; ++ queue->inited = false; ++ INIT_LIST_HEAD(&queue->used_list); ++ return 0; ++} ++ ++static int buffer_queue_init(bi_buffer_queue_t *queue, ++ unsigned int qlen, unsigned int len, unsigned int base_off) ++{ ++ int i; ++ ++ BDBG(" Enter\n"); ++ if(queue->inited) ++ return 0; ++ ++ queue->qlen = qlen; ++ queue->buf = kzalloc(qlen * sizeof(bi_data_t), GFP_KERNEL); ++ if(queue->buf == NULL) ++ { ++ BERR("kzalloc Failed\n"); ++ return -ENOMEM; ++ } ++ INIT_LIST_HEAD(&queue->used_list); ++ spin_lock_init(&queue->lock); ++ ++ for(i = 0; i < qlen; i++) ++ { ++ queue->buf[i].used = false; ++ queue->buf[i].buf.index = i; ++ queue->buf[i].buf.length = len; ++ queue->buf[i].buf.bytesused = 0; ++ queue->buf[i].buf.mem_offset = PAGE_ALIGN(i * len + base_off); ++ queue->buf[i].buf.vaddr = vmalloc_user(len); ++ if(queue->buf[i].buf.vaddr == NULL) { ++ BERR("vmalloc_user failed, ret %d\n", (int)queue->buf[i].buf.vaddr); ++ goto error; ++ } ++ BINFO("alloc a dev, offset 0x%x, addr 0x%x, len %u, index %d, memoffset 0x%x\n", ++ queue->buf[i].buf.mem_offset, (unsigned int)queue->buf[i].buf.vaddr, ++ queue->buf[i].buf.length, queue->buf[i].buf.index, queue->buf[i].buf.mem_offset); ++ } ++ queue->inited = true; ++ return 0; ++ ++error: ++ buffer_queue_deinit(queue); ++ return -EINVAL; ++} ++ ++/* Get ready Data from list */ ++static buffer_t * buffer_queue_dequeue_data(bi_buffer_queue_t *queue) ++{ ++ unsigned long flags; ++ bi_data_t * data; ++ BDBG("Enter\n"); ++ if(!queue->inited) ++ { ++ BERR("queue 0x%x, queue->buf 0x%x\n", ++ (unsigned int)queue, (unsigned int)queue->buf); ++ return NULL; ++ } ++ ++ spin_lock_irqsave(&queue->lock, flags); ++ if (list_empty(&queue->used_list)) { ++ spin_unlock_irqrestore(&queue->lock, flags); ++ BWRN("No Ready Buf to be dequeue\n"); ++ return NULL; ++ } ++ data = list_first_entry(&queue->used_list, bi_data_t,list); ++ list_del(&data->list); ++ spin_unlock_irqrestore(&queue->lock, flags); ++ return &data->buf; ++} ++ ++/* Put A data to list_used */ ++static int buffer_queue_queue_data(bi_buffer_queue_t *queue, buffer_t *data, void *buf, unsigned int len) ++{ ++ int i; ++ unsigned long flags; ++ ++ BDBG("Enter \n"); ++ if(!queue->inited) ++ { ++ BERR("queue 0x%x, queue->buf 0x%x, queue->qlen %u\n", ++ (unsigned int)queue, (unsigned int)queue->buf, queue->qlen); ++ return -EINVAL; ++ } ++ ++ if(data && data->bytesused) ++ { ++ for(i = 0; i < queue->qlen ; i++) ++ { ++ if(queue->buf[i].buf.index != data->index || ++ queue->buf[i].used == true) ++ continue; ++ ++ queue->buf[i].buf.bytesused = data->bytesused; ++ BINFO("queue index %d bytesused %u\n", ++ queue->buf[i].buf.index, ++ queue->buf[i].buf.bytesused); ++ spin_lock_irqsave(&queue->lock, flags); ++ queue->buf[i].used = true; ++ list_add_tail(&queue->buf[i].list, &queue->used_list); ++ spin_unlock_irqrestore(&queue->lock, flags); ++ return 0; ++ } ++ return -EINVAL; ++ } ++ ++ if(!buf || !len) ++ return -EINVAL; ++ ++ for(i = 0; i < queue->qlen ; i++) ++ { ++ if(queue->buf[i].used == true) ++ continue; ++ ++ if(queue->buf[i].buf.length < len) ++ { ++ BWRN("buflen %u, putdata len %u \n", ++ queue->buf[i].buf.length, len); ++ return -EINVAL; ++ } ++ spin_lock_irqsave(&queue->lock, flags); ++ queue->buf[i].used = true; ++ memcpy(queue->buf[i].buf.vaddr, buf, len); ++ queue->buf[i].buf.bytesused = len; ++ ++ list_add_tail(&queue->buf[i].list, &queue->used_list); ++ spin_unlock_irqrestore(&queue->lock, flags); ++ return 0; ++ } ++ BWRN("No Free Buf\n"); ++ return -ENOMEM; ++} ++ ++/* Set the used flags to free */ ++static int buffer_queue_finish_buf(bi_buffer_queue_t *queue, buffer_t *buf) ++{ ++ unsigned long flags; ++ bi_data_t *qbuf = NULL; ++ bi_data_t *data = NULL; ++ ++ if(!queue->inited) ++ { ++ BERR("queue 0x%x, queue->buf 0x%x, buf 0x%x\n", ++ (unsigned int)queue, (unsigned int)queue->buf, (unsigned int)buf); ++ return -EINVAL; ++ } ++ ++ data = container_of(buf, bi_data_t ,buf); ++ ++ spin_lock_irqsave(&queue->lock, flags); ++ list_for_each_entry(qbuf, &queue->used_list, list) ++ { ++ if(qbuf->buf.vaddr == buf->vaddr || ++ qbuf->buf.index == buf->index || ++ qbuf->buf.mem_offset == buf->mem_offset) ++ { ++ BWRN("BUF need to be handled !!!\n"); ++ return -EBUSY; ++ } ++ } ++ spin_unlock_irqrestore(&queue->lock, flags); ++ buf->bytesused = 0; ++ data->used = false; ++ return 0; ++} ++ ++static buffer_t * buffer_queue_find_free_buf(bi_buffer_queue_t *queue) ++{ ++ int i = 0; ++ ++ if(!queue->inited) ++ { ++ BERR("queue 0x%x, queue->buf 0x%x, queue->qlen %u\n", ++ (unsigned int)queue, (unsigned int)queue->buf, queue->qlen); ++ return NULL; ++ } ++ ++ for(i = 0; i qlen; i++) ++ { ++ if(queue->buf[i].used == false) ++ return &queue->buf[i].buf; ++ } ++ return NULL; ++} ++ ++static buffer_t * buffer_queue_find_buf(bi_buffer_queue_t *queue, void *vaddr, unsigned int index, unsigned int mem_offset) ++{ ++ int i = 0; ++ buffer_t * buf = NULL; ++ ++ if(!queue->inited) ++ { ++ BERR("queue 0x%x, queue->buf 0x%x, queue->qlen %u\n", ++ (unsigned int)queue, (unsigned int)queue->buf, queue->qlen); ++ return NULL; ++ } ++ ++ for(i = 0; i qlen; i++) ++ { ++ buf = &queue->buf[i].buf; ++ BDBG("tmp index %d mem 0x%x offset 0x%x\n", buf->index, buf->mem_offset, mem_offset); ++ if(buf->index == index) ++ { ++ BINFO("Find A buf By index %d\n", buf->index) ++ return buf; ++ } ++ if(buf->vaddr == vaddr) ++ { ++ BINFO("Find A buf By vadd 0x%x\n", (unsigned int)buf->vaddr) ++ return buf; ++ } ++ if(buf->mem_offset == mem_offset) ++ { ++ BINFO("Find A buf By offset 0x%x\n",buf->mem_offset) ++ return buf; ++ } ++ } ++ return NULL; ++} ++ ++/* check if queue is empty (all is used) */ ++static bool buffer_queue_is_empty(bi_buffer_queue_t *queue) ++{ ++ int i; ++ ++ if(!queue->inited) ++ { ++ BERR("queue 0x%x, queue->buf 0x%x, queue->qlen %u\n", ++ (unsigned int)queue, (unsigned int)queue->buf, queue->qlen); ++ return -EINVAL; ++ } ++ ++ for(i = 0; i < queue->qlen; i++) ++ { ++ if(queue->buf[i].used == false) ++ return false; ++ } ++ return true; ++} ++ ++static bool buffer_queue_used_list_is_empty(bi_buffer_queue_t *queue) ++{ ++ if(!queue->inited) ++ return -EINVAL; ++ ++ return list_empty(&queue->used_list); ++} ++ ++static int buffer_queue_reset(bi_buffer_queue_t *queue) ++{ ++ buffer_t *buf; ++ ++ if(!queue->inited) ++ return -EINVAL; ++ ++ while(1) { ++ buf = buffer_queue_dequeue_data(queue); ++ if(buf == NULL) ++ break; ++ buffer_queue_finish_buf(queue, buf); ++ } ++ return 0; ++} ++ ++static long bi_reqbufs(struct bi_device *bdev, requeset_buf_t *user_data) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ ++ requeset_buf_t rb; ++ long ret = 0; ++ BDBG(" Enter\n") ++ ++ ret = copy_from_user(&rb, user_data, sizeof(buffer_t)); ++ if(ret) { ++ BERR("copy_from_user ERR %ld \n", ret); ++ return ret; ++ } ++ ++ BINFO(" count %d type %s length %u\n", rb.count, rb.type == TRANSFER_IN?"in":"out", rb.length); ++ if(rb.type == TRANSFER_IN) ++ { ++ if(rb.count) ++ { ++ if(rb.length > 0 && rb.length <= GBI_DIRECTION_BULK_IN_BUFLEN) ++ return buffer_queue_init(&h->bulk_in_queue, rb.count, ++ rb.length, BULK_IN_QUEUE_BASE_OFFSET); ++ else ++ BERR("request buf size to large \n"); ++ } ++ else ++ return buffer_queue_deinit(&h->bulk_in_queue); ++ } ++ else if(rb.type == TRANSFER_OUT) ++ { ++ if(rb.count) ++ { ++ if(rb.length > 0 && rb.length <= GBI_DIRECTION_BULK_OUT_BUFLEN) ++ return buffer_queue_init(&h->bulk_out_queue, rb.count, ++ rb.length, BULK_OUT_QUEUE_BASE_OFFSET); ++ else ++ BERR("request buf size to large \n"); ++ } ++ else ++ return buffer_queue_deinit(&h->bulk_out_queue); ++ } ++ return -EINVAL; ++} ++ ++/* QUEUE A BUF To IN QUEUE*/ ++static long bi_queue_buf(struct bi_device *bdev, buffer_t *user_data) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ buffer_t fdata; ++ long ret = 0; ++ BDBG("Enter\n"); ++ ++ ret = copy_from_user(&fdata, user_data, sizeof(buffer_t)); ++ if(ret) ++ return ret; ++ ++ return buffer_queue_queue_data(&h->bulk_in_queue, &fdata, NULL, 0); ++} ++ ++/* Get A Free BUF From IN QUEUE*/ ++static long bi_dequeue_buf(struct bi_device *bdev, buffer_t *user_data) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ buffer_t *buf = NULL; ++ BDBG("Enter\n"); ++ ++ buf = buffer_queue_find_free_buf(&h->bulk_in_queue); ++ if(buf == NULL) ++ return -EBUSY; ++ BINFO("get a free buf, index %d\n", buf->index); ++ return copy_to_user(user_data, buf, sizeof(buffer_t)); ++} ++ ++static long bi_query_buf(struct bi_device *bdev, buffer_t *user_data) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ buffer_t fdata, *buf = NULL; ++ unsigned int ret = 0; ++ BDBG("Enter\n"); ++ ++ ret = copy_from_user(&fdata, user_data, sizeof(buffer_t)); ++ if(ret) ++ return ret; ++ ++ BINFO("find %s buf , index %d \n", fdata.type == TRANSFER_IN? "IN":"OUT", fdata.index); ++ if(fdata.type == TRANSFER_IN) ++ buf = buffer_queue_find_buf(&h->bulk_in_queue, (void*)0xFFFFFFFF, fdata.index, 0xFFFFFFFF); ++ else if(fdata.type == TRANSFER_OUT) ++ buf = buffer_queue_find_buf(&h->bulk_out_queue, (void*)0xFFFFFFFF, fdata.index, 0xFFFFFFFF); ++ else ++ return -EINVAL; ++ ++ if(buf == NULL) ++ return -EINVAL; ++ ++ return copy_to_user(user_data, buf, sizeof(buffer_t)); ++} ++ ++static long bi_finish_buf(struct bi_device *bdev, buffer_t *user_data) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ buffer_t fdata, *buf = NULL; ++ unsigned int ret = 0; ++ ++ BDBG("Enter\n"); ++ ++ ret = copy_from_user(&fdata, user_data, sizeof(buffer_t)); ++ if(ret) ++ return ret; ++ ++ buf = buffer_queue_find_buf(&h->bulk_out_queue, fdata.vaddr, fdata.index, fdata.mem_offset); ++ if(buf == NULL) ++ return -EINVAL; ++ ++ return buffer_queue_finish_buf(&h->bulk_out_queue, buf); ++} ++ ++static long bi_dequeue_event(struct bi_device *bdev, buffer_t *buf) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ buffer_t *data = NULL; ++ ++ BDBG("Enter\n"); ++ ++ if((data = buffer_queue_dequeue_data(&h->bulk_out_queue)) == NULL) ++ return -ENOMEM; ++ ++ return copy_to_user(buf, data, sizeof(buffer_t)); ++} ++ ++static int bi_queue_in_packet(struct bi_device *bdev, void *data, unsigned int len) ++{ ++ struct usb_request *req = NULL; ++ unsigned long flags, ret = 0; ++ ++ BDBG("Enter\n"); ++ if (!len || !data) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&bdev->in_req_lock, flags); ++ if (list_empty(&bdev->in_req_free)) { ++ spin_unlock_irqrestore(&bdev->in_req_lock, flags); ++ return 0; ++ } ++ req = list_first_entry(&bdev->in_req_free, struct usb_request, list); ++ list_del(&req->list); ++ spin_unlock_irqrestore(&bdev->in_req_lock, flags); ++ ++ req->length = min_t(unsigned int, bdev->bulk_in_buflen, len); ++ req->zero = len < bdev->bulk_in_buflen; ++ memcpy(req->buf, data, req->length); ++ BINFO("queue a in request , size %d\n", req->length); ++ if((ret = usb_ep_queue(bdev->in_ep, req, GFP_KERNEL)) < 0) ++ { ++ BERR("Queue A buf Failed \n"); ++ return -1; ++ } ++ return 0; ++} ++ ++static long bi_device_ioctl(struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ struct bi_device *bdev = file->private_data; ++ struct bi_device_handle *h = bdev->devh; ++ ++ BDBG("Enter\n"); ++ if(!h || h->status < DEVICE_INITIALIZED) ++ { ++ BERR(" device status %d \n",!h ? 0 : h->status); ++ return -EINVAL; ++ } ++ ++ switch (cmd) { ++ case USB_NERVE_DEQUEUE_EVENT: ++ return bi_dequeue_event(bdev, (void*)arg); ++ ++ case USB_NERVE_FINISH_EVENT: ++ return bi_finish_buf(bdev, (void*)arg); ++ ++ case USB_NERVE_DEQUEUE_BUF: ++ return bi_dequeue_buf(bdev, (void*)arg); ++ ++ case USB_NERVE_QUEUE_BUF: ++ return bi_queue_buf(bdev, (void*)arg); ++ ++ case USB_NERVE_REQBUFS: ++ return bi_reqbufs(bdev, (void*)arg); ++ ++ case USB_NERVE_QUERYBUF: ++ return bi_query_buf(bdev, (void*)arg); ++ ++ default: ++ return -ENOIOCTLCMD; ++ } ++ return 0; ++} ++ ++static void bi_device_queue_reset(struct bi_device *bdev) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ ++ buffer_queue_reset(&h->bulk_in_queue); ++ buffer_queue_reset(&h->bulk_out_queue); ++} ++ ++static int bi_device_open(struct inode *inode, struct file *file) ++{ ++ struct bi_device_handle *h = ++ container_of(inode->i_cdev, struct bi_device_handle, cdev); ++ ++ BDBG("Enter\n"); ++ if(!h || h->status < DEVICE_INITIALIZED || h->opened) ++ return -EINVAL; ++ ++ init_waitqueue_head(&h->waitq); ++ file->private_data = h->bdev; ++ ++ h->opened = true; ++ return 0; ++} ++ ++static int bi_device_release(struct inode *inode, struct file *file) ++{ ++ struct bi_device *bdev = file->private_data; ++ struct bi_device_handle *h = bdev->devh; ++ ++ BDBG("Enter\n"); ++ if(!h || h->status < DEVICE_INITIALIZED || !h->opened) ++ return -EINVAL; ++ ++ file->private_data = NULL; ++ ++ h->opened = false; ++ return 0; ++} ++ ++static unsigned int bi_device_poll(struct file *file, poll_table *wait) ++{ ++ struct bi_device *bdev = file->private_data; ++ struct bi_device_handle *h = bdev->devh; ++ unsigned int mask = 0; ++ ++ BDBG("Enter\n"); ++ poll_wait(file, &h->waitq, wait); ++ ++ /* ++ * use wake_up to toggle ++ */ ++ if(buffer_queue_used_list_is_empty(&h->bulk_out_queue) == false) ++ mask |= POLLIN | POLLRDNORM; ++ else ++ BINFO("status 0x%x \n", h->status); ++ ++ return mask; ++} ++ ++static int bi_device_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ struct bi_device *bdev = file->private_data; ++ struct bi_device_handle *h = bdev->devh; ++ unsigned long off = vma->vm_pgoff << PAGE_SHIFT; ++ buffer_t * buf; ++ int ret; ++ ++ BINFO("pageoffset %lx offset %lx \n", vma->vm_pgoff, off); ++ ++ if(BULK_IN_BUFFER(off)) ++ { ++ if (!(vma->vm_flags & VM_SHARED)) { ++ BWRN("Invalid vma flags, VM_SHARED needed\n"); ++ return -EINVAL; ++ } ++ if (!(vma->vm_flags & VM_READ)) { ++ BWRN("Invalid vma flags, VM_READ needed\n"); ++ return -EINVAL; ++ } ++ buf = buffer_queue_find_buf(&h->bulk_in_queue, (void*)0xFFFFFFFF, 0xFFFFFFFF, off); ++ if(buf == NULL) { ++ BWRN("no such buf\n"); ++ return -ENOMEM; ++ } ++ } ++ else if(BULK_OUT_BUFFER(off)) ++ { ++ if (!(vma->vm_flags & VM_SHARED)) { ++ BWRN("Invalid vma flags, VM_SHARED needed\n"); ++ return -EINVAL; ++ } ++ if (!(vma->vm_flags & VM_WRITE)) { ++ BWRN("Invalid vma flags, VM_WRITE needed\n"); ++ return -EINVAL; ++ } ++ buf = buffer_queue_find_buf(&h->bulk_out_queue, (void*)0xFFFFFFFF, 0xFFFFFFFF, off); ++ if(buf == NULL) { ++ BWRN("no such buf\n"); ++ return -ENOMEM; ++ } ++ } else { ++ BERR("wrong mem offset\n"); ++ return -EINVAL; ++ } ++ ++ ret = remap_vmalloc_range(vma, buf->vaddr, 0); ++ if (ret) { ++ BERR("Remapping vmalloc memory, error: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++static const struct file_operations bi_fops = { ++ .owner = THIS_MODULE, ++ .open = bi_device_open, ++ .release = bi_device_release, ++ .unlocked_ioctl = bi_device_ioctl, ++ .poll = bi_device_poll, ++ .mmap = bi_device_mmap, ++}; ++ ++#if (USB_PROC_DEBUG_ENABLE==1) ++static inline char* getLogLevel(int log_level) ++{ ++ switch(log_level) ++ { ++ case LOG_DBG: ++ return "LOG_DBG"; ++ case LOG_INFO: ++ return "LOG_INFO"; ++ case LOG_WRN: ++ return "LOG_WRN"; ++ case LOG_ERR: ++ return "LOG_ERR"; ++ default: ++ return "Unknown Level"; ++ } ++ return NULL; ++} ++ ++static inline int setLogLevel(char *level) ++{ ++ if (!strncmp(level, "LOG_DBG", 7)) ++ log_level = LOG_DBG; ++ else if (!strncmp(level, "LOG_INFO", 8)) ++ log_level = LOG_INFO; ++ else if (!strncmp(level, "LOG_WRN", 7)) ++ log_level = LOG_WRN; ++ else if (!strncmp(level, "LOG_ERR", 7)) ++ log_level = LOG_ERR; ++ else ++ { ++ printk("Invalid Args [%s]", level); ++ printk("echo param >/proc/usb_bi/debug_level\n" ++ " param: LOG_DBG\n" ++ " LOG_INFO\n" ++ " LOG_WRN\n" ++ " LOG_ERR\n"); ++ }; ++ return 0; ++} ++ ++static int bd_proc_show(struct seq_file *m, void *v) ++{ ++ const struct file *file = m->file; ++ ++ if(!strcmp(file->f_path.dentry->d_iname, "debug_level")) ++ { ++ seq_printf(m, "%s\n", getLogLevel(log_level)); ++ } ++ else ++ if(!strcmp(file->f_path.dentry->d_iname, PROG_ENTRY)) ++ { ++ seq_printf(m, "%s entity[%s] todo\n", __func__, PROG_ENTRY); ++ } ++ return 0; ++} ++ ++static int bd_proc_write( ++ struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *f_pos) ++{ ++ char *args = NULL; ++ ++ args = kzalloc((count+1), GFP_KERNEL); ++ if(!args) ++ return -ENOMEM; ++ ++ if(copy_from_user(args, buffer, count)) ++ { ++ kfree(args); ++ return EFAULT; ++ } ++ ++ if(!strcmp(file->f_path.dentry->d_iname, "debug_level")) ++ { ++ setLogLevel(args); ++ } else ++ if(!strcmp(file->f_path.dentry->d_iname, PROG_ENTRY)) ++ { ++ printk("%s entity[%s] todo\n", __func__, PROG_ENTRY); ++ } else ++ count = -EINVAL; ++ ++ kfree(args); ++ return count; ++} ++ ++static int bd_proc_open(struct inode *inode, struct file *file) ++{ ++ struct bi_device *bdev = file->private_data; ++ ++ return single_open(file, bd_proc_show, bdev); ++} ++ ++static const struct file_operations bd_proc_fops = { ++ .open = bd_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++ .write = bd_proc_write, ++}; ++ ++static int bd_proc_create(struct bi_device_handle *h) ++{ ++ h->proc_entry = proc_mkdir(PROG_ENTRY, 0); ++ if(!h->proc_entry) ++ BINFO("Dir esist\n"); ++ ++ proc_create_data("debug_level", 0, h->proc_entry, &bd_proc_fops, h->bdev); ++ proc_create_data(PROG_ENTRY, 0, h->proc_entry, &bd_proc_fops, h->bdev); ++ ++ return 0; ++} ++ ++static void bd_proc_destroy(struct bi_device_handle *h) ++{ ++ proc_remove(h->proc_entry); ++} ++#endif ++ ++static int f_bi_out_ep_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct bi_device *bi = ep->driver_data; ++ unsigned long flags; ++ int status; ++ ++ BDBG("Enter\n"); ++ bi_out_packet_handle(ep, req); ++ ++ BINFO("queue a out request , size %d\n", req->length); ++ status = usb_ep_queue(ep, req, GFP_ATOMIC); ++ if (status == 0) { ++ return 0; ++ } else { ++ BWRN("Unable to queue buffer to %s: %d\n",ep->name, status); ++ goto free_req; ++ } ++ ++free_req: ++ spin_lock_irqsave(&bi->out_req_lock,flags); ++ req->length = 0; ++ list_add_tail(&req->list, &bi->out_req_free); ++ spin_unlock_irqrestore(&bi->out_req_lock,flags); ++ return status; ++} ++ ++static int f_bi_in_ep_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct bi_device *bi = ep->driver_data; ++ unsigned long flags; ++ BDBG("Enter\n"); ++ ++ spin_lock_irqsave(&bi->in_req_lock,flags); ++ req->length = 0; ++ list_add_tail(&req->list, &bi->in_req_free); ++ spin_unlock_irqrestore(&bi->in_req_lock,flags); ++ ++ return 0; ++} ++ ++static void bi_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct bi_device *bi = ep->driver_data; ++ int status = req->status; ++ unsigned long flags; ++ ++ BDBG("Enter\n"); ++ ++ switch (status) { ++ ++ case 0: /* normal completion? */ ++ if (ep == bi->out_ep) { ++ f_bi_out_ep_complete(ep, req); ++ } else { ++ f_bi_in_ep_complete(ep, req); ++ } ++ break; ++ default: ++ BERR("%s bi complete --> %d, %d/%d\n", ep->name, ++ status, req->actual, req->length); ++ /* FALLTHROUGH */ ++ ++ /* NOTE: since this driver doesn't maintain an explicit record ++ * of requests it submitted (just maintains qlen count), we ++ * rely on the hardware driver to clean up on discobdect or ++ * endpoint disable. ++ */ ++ case -ECONNABORTED: /* hardware forced ep reset */ ++ case -ECONNRESET: /* request dequeued */ ++ case -ESHUTDOWN: /* discobdect from host */ ++ if(ep == bi->out_ep) { ++ spin_lock_irqsave(&bi->out_req_lock,flags); ++ req->length = 0; ++ list_add_tail(&req->list, &bi->out_req_free); ++ spin_unlock_irqrestore(&bi->out_req_lock,flags); ++ } ++ else { ++ spin_lock_irqsave(&bi->in_req_lock,flags); ++ req->length = 0; ++ list_add_tail(&req->list, &bi->in_req_free); ++ spin_unlock_irqrestore(&bi->in_req_lock,flags); ++ } ++ return; ++ } ++} ++ ++static int bi_free_request(struct bi_device *bdev) ++{ ++ unsigned int i; ++ struct f_bd_opts *bd_opts = NULL; ++ struct usb_ep *ep = NULL; ++ ++ bd_opts = container_of(bdev->function.fi, struct f_bd_opts, func_inst); ++ ++ /* in ep */ ++ ep = bdev->in_ep; ++ for (i = 0; i < bd_opts->bulk_in_qlen; ++i) { ++ if (bdev->in_req[i]) { ++ usb_ep_dequeue(ep, bdev->in_req[i]); ++ free_ep_req(ep, bdev->in_req[i]); ++ } ++ bdev->in_req[i] = NULL; ++ } ++ INIT_LIST_HEAD(&bdev->in_req_free); ++ ++ /* out ep */ ++ ep = bdev->out_ep; ++ for (i = 0; i < bd_opts->bulk_out_qlen; ++i) { ++ if (bdev->out_req[i]) { ++ usb_ep_dequeue(ep, bdev->out_req[i]); ++ free_ep_req(ep, bdev->out_req[i]); ++ } ++ bdev->out_req[i] = NULL; ++ } ++ INIT_LIST_HEAD(&bdev->out_req_free); ++ return 0; ++} ++ ++/* ++ * Alloc OUT Endpoint Request and Queue For RX Control ++ * Alloc IN Endpoint and add it to Free Queue ++ */ ++static int bi_alloc_request(struct bi_device *bdev) ++{ ++ unsigned i; ++ int result; ++ struct usb_ep *ep = NULL; ++ struct f_bd_opts *bd_opts = NULL; ++ struct usb_composite_dev *cdev = NULL; ++ ++ result = 0; ++ cdev = bdev->function.config->cdev; ++ bd_opts = container_of(bdev->function.fi, struct f_bd_opts, func_inst); ++ ++ /* in ep */ ++ ep = bdev->in_ep; ++ for (i = 0; i < bdev->bulk_in_qlen; i++) { ++ bdev->in_req[i] = alloc_ep_req(ep, bd_opts->bulk_in_buflen); ++ if (!bdev->in_req[i]) ++ break; ++ ++ bdev->in_req[i]->actual = 0; ++ bdev->in_req[i]->length = 0; ++ bdev->in_req[i]->complete = bi_complete; ++ bdev->in_req[i]->context = bdev; ++ ++ BINFO("%s %s alloc req buf len %u addr 0x%x \n", ++ __func__,ep->name,bd_opts->bulk_in_buflen, (unsigned int)bdev->in_req[i]->buf); ++ list_add_tail(&bdev->in_req[i]->list, &bdev->in_req_free); ++ } ++ ++ /* out ep */ ++ ep = bdev->out_ep; ++ for (i = 0; i < bdev->bulk_out_qlen && result == 0; i++) { ++ bdev->out_req[i] = alloc_ep_req(ep, bd_opts->bulk_out_buflen); ++ if (!bdev->out_req[i]) ++ goto fail; ++ ++ bdev->out_req[i]->actual = 0; ++ bdev->out_req[i]->length = CONTROL_REQUEST_SIZE; ++ bdev->out_req[i]->complete = bi_complete; ++ bdev->out_req[i]->context = bdev; ++ ++ BINFO("%s %s alloc req buf len %u addr 0x%x \n", ++ __func__,ep->name, bd_opts->bulk_out_buflen, (unsigned int)bdev->out_req[i]->buf); ++ result = usb_ep_queue(ep, bdev->out_req[i], GFP_ATOMIC); ++ if (result) { ++ ERROR(cdev, "%s queue req --> %d\n",ep->name, result); ++ goto fail; ++ } ++ } ++ return 0; ++ ++fail: ++ return result; ++} ++ ++static void disable_ep(struct usb_composite_dev *cdev, struct usb_ep *ep) ++{ ++ int value; ++ ++ if (ep->driver_data) { ++ value = usb_ep_disable(ep); ++ if (value < 0) ++ DBG(cdev, "disable %s --> %d\n",ep->name, value); ++ ep->driver_data = NULL; ++ } ++} ++ ++void disable_endpoints(struct usb_composite_dev *cdev, ++ struct usb_ep *in, struct usb_ep *out, ++ struct usb_ep *int_in, struct usb_ep *int_out) ++{ ++ BDBG("Enter\n"); ++ disable_ep(cdev, in); ++ disable_ep(cdev, out); ++ if (int_in) ++ disable_ep(cdev, int_in); ++ if (int_out) ++ disable_ep(cdev, int_out); ++} ++ ++void disable_bi_device(struct bi_device *bdev) ++{ ++ struct usb_composite_dev *cdev = NULL; ++ struct bi_device_handle *h = bdev->devh; ++ ++ BDBG("Enter\n"); ++ if(!bdev || h->status < DEVICE_WAITING) ++ return; ++ ++ cdev = bdev->function.config->cdev; ++ if(!cdev) ++ return; ++ ++ BINFO("disable eps \n"); ++ disable_endpoints(cdev, bdev->in_ep, bdev->out_ep, NULL, NULL); ++ ++ bi_free_request(bdev); ++ ++ h->status = DEVICE_INITIALIZED; ++ BINFO("%s disabled\n", bdev->function.name); ++} ++ ++static int enable_endpoint(struct usb_composite_dev *cdev, struct bi_device *bi, ++ struct usb_ep *ep) ++{ ++ int result; ++ ++ result = config_ep_by_speed(cdev->gadget, &(bi->function), ep); ++ if (result) ++ goto fail; ++ result = usb_ep_enable(ep); ++ if (result < 0) ++ goto fail; ++ ep->driver_data = bi; ++ return 0; ++ ++fail: ++ return result; ++} ++ ++int enable_bi_device(struct bi_device *bdev) ++{ ++ int result = 0; ++ struct usb_composite_dev * cdev = NULL; ++ struct bi_device_handle *h = bdev->devh; ++ ++ cdev = bdev->function.config->cdev; ++ ++ BDBG("Enter\n"); ++ if(!bdev || !cdev || h->status != DEVICE_INITIALIZED) ++ return -EINVAL; ++ ++ BINFO("enable ep in\n"); ++ result = enable_endpoint(cdev, bdev, bdev->in_ep); ++ if (result) ++ return result; ++ ++ BINFO("enable ep out\n"); ++ result = enable_endpoint(cdev, bdev, bdev->out_ep); ++ if (result) ++ return result; ++ ++ result = bi_alloc_request(bdev); ++ if (result) ++ return result; ++ ++ h->status = DEVICE_WAITING; ++ BINFO("%s enabled\n", bdev->function.name); ++ return result; ++} ++ ++/* ++ * bind with gadget dev and create a char dev ++ */ ++int bi_device_register(struct device *dev, struct bi_device *bdev) ++{ ++ dev_t devid; ++ int major = 0, ret = 0; ++ struct device *char_dev = NULL; ++ struct class *nclass = NULL; ++ struct bi_device_handle *h = NULL; ++ ++ BDBG("Enter\n"); ++ printk("%s version: %s\n", NERVE_NAME, MODULE_VERION); ++ ++ if(!bdev) ++ return -EINVAL; ++ ++ /* alloc a bi dev handle to process dev*/ ++ h = kzalloc(sizeof(*h), GFP_KERNEL); ++ if(!h) ++ return -ENOMEM; ++ ++ strcpy(bdev->name, NERVE_NAME); ++ /* associate with gadget device */ ++ get_device(dev); ++ bdev->dev = dev; ++ if (dev == NULL) { ++ /* If dev == NULL, then name must be filled in by the caller */ ++ if (WARN_ON(!bdev->name[0])) { ++ ret = -EINVAL; ++ } ++ return 0; ++ } ++ /* Set name to driver name + device name if it is empty. */ ++ if (!bdev->name[0]) ++ snprintf(bdev->name, sizeof(bdev->name), "%s %s", ++ dev->driver->name, dev_name(dev)); ++ if (!dev_get_drvdata(dev)) ++ dev_set_drvdata(dev, bdev); ++ ++ /* Alloc a char device */ ++ devid = MKDEV(major, 0); ++ ret = alloc_chrdev_region(&devid, 0, 1, bdev->name); ++ if(ret < 0) ++ return -EINVAL; ++ major = MAJOR(devid); ++ ++ cdev_init(&h->cdev, &bi_fops); ++ h->cdev.owner= bi_fops.owner; ++ ++ ret = cdev_add(&h->cdev, MKDEV(major, 0), 1); ++ if(ret < 0) { ++ printk(KERN_INFO "Error %d adding char_mem device", ret); ++ goto cdev_detroy; ++ } ++ ++ /* register sys class and create a device */ ++ nclass = class_create(THIS_MODULE, bdev->name); ++ if(IS_ERR(nclass)) { ++ ret = PTR_ERR(nclass); ++ goto cdev_detroy; ++ } ++ ++ char_dev = device_create(nclass, NULL, devid, bdev, bdev->name); ++ if(IS_ERR(char_dev)) { ++ ret = PTR_ERR(char_dev); ++ goto class_destroy; ++ } ++ ++ h->major = major; ++ h->nclass = nclass; ++ h->dev = char_dev; ++ h->status = DEVICE_INITIALIZED; ++ h->opened = 0; ++ ++ h->bdev = bdev; ++ bdev->devh = h; ++ ++ /* alloc endpoint requeset*/ ++ BINFO("Init req Spin lock and list\n"); ++ INIT_LIST_HEAD(&bdev->in_req_free); ++ spin_lock_init(&bdev->in_req_lock); ++ INIT_LIST_HEAD(&bdev->out_req_free); ++ spin_lock_init(&bdev->out_req_lock); ++ ++#if (USB_PROC_DEBUG_ENABLE==1)//bi_device_handle ++ bd_proc_create(h); ++#endif ++ ++ return 0; ++ ++class_destroy: ++ class_destroy(nclass); ++cdev_detroy: ++ cdev_del(&h->cdev); ++ unregister_chrdev_region(devid, 1); ++ return ret; ++} ++ ++void bi_device_unregister(struct bi_device *bdev) ++{ ++ struct bi_device_handle *h = bdev->devh; ++ int major = h->major; ++ struct device *char_dev = h->dev; ++ struct class *nclass = h->nclass; ++ dev_t devid = MKDEV(major, 0); ++ ++ if(!bdev || !h || h->status == DEVICE_NOT_INIT) ++ return; ++ ++ if(nclass && char_dev) ++ device_destroy(nclass, devid); ++ ++ if(nclass) ++ class_destroy(nclass); ++ ++ cdev_del(&h->cdev); ++ ++ unregister_chrdev_region(devid, 1); ++ bd_proc_destroy(h); ++ kfree(h); ++ bdev->devh = NULL; ++ ++ return; ++} ++ ++int bi_ep0_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ return 0; ++} ++ ++int bi_ep0_setup(struct usb_ep *ep, struct usb_request *req) ++{ ++ return 0; ++} ++ ++int bi_out_packet_handle(struct usb_ep *ep, struct usb_request *req) ++{ ++ bi_control_header_t *crq = req->buf; ++ struct bi_device *bdev = ep->driver_data; ++ struct bi_device_handle *h = bdev->devh; ++ bi_operation_permit_t permit = {0xFFFF, 0}; ++ buffer_t *buf = NULL; ++ ++ BINFO("Enter crq->magic 0x%x, reqlen %u, actual %u\n", crq->magic, req->length, req->actual); ++ if(req->length != sizeof(bi_control_header_t) || ++ crq->magic != USB_CAMMAND_MAGIC){ ++ BDBG("Dealing specify out data reqlen %d \n",req->actual); ++ if(req->actual) ++ buffer_queue_queue_data(&h->bulk_out_queue, NULL, req->buf, req->actual); ++ ++ if(h->opened) ++ wake_up_interruptible(&h->waitq); ++ goto requeue_std_crq; ++ } ++ ++ if(req->length != sizeof(bi_control_header_t)) ++ goto requeue_std_crq; ++ ++ /* only support a request now!!! */ ++ switch(crq->cmd) ++ { ++ case USB_GET_DEVICE_STATUS: ++ BINFO("USB_GET_DEVICE_STATUS\n"); ++ bi_queue_in_packet(bdev, &h->status, sizeof(sizeof(h->status))); ++ goto requeue_std_crq; ++ case USB_RESET_REQUEST: ++ BINFO("USB_RESET_REQUEST\n"); ++ bi_device_queue_reset(bdev); ++ if (bdev->in_ep->driver_data) ++ disable_bi_device(bdev); ++ return enable_bi_device(bdev); ++ //need to info user to reset ++ case USB_HOST_GET_DATA: ++ BINFO("USB_HOST_GET_DATA\n"); ++ buf = buffer_queue_dequeue_data(&h->bulk_in_queue); ++ if(buf == NULL) ++ { ++ bi_queue_in_packet(bdev, &permit, sizeof(permit)); ++ goto requeue_std_crq; ++ } ++ permit.magic = 0xABCD; ++ permit.length = min_t(unsigned int, buf->bytesused, crq->dataLength); ++ if(crq->dataLength != buf->bytesused) ++ BWRN("Get Length %u, Buf len %u\n",crq->dataLength, buf->bytesused); ++ bi_queue_in_packet(bdev, &permit, sizeof(permit)); ++ bi_queue_in_packet(bdev, buf->vaddr, permit.length); ++ buffer_queue_finish_buf(&h->bulk_in_queue, buf); ++ break; ++ case USB_HOST_SET_DATA: ++ BINFO("USB_HOST_SET_DATA\n"); ++ if(buffer_queue_is_empty(&h->bulk_out_queue)) ++ { ++ bi_queue_in_packet(bdev, &permit, sizeof(permit)); ++ goto requeue_std_crq; ++ } ++ permit.magic = 0xABCD; ++ permit.length = min_t(unsigned int, bdev->bulk_out_buflen, crq->dataLength); ++ bi_queue_in_packet(bdev, &permit, sizeof(permit)); ++ req->length = permit.length; ++ return 0; ++ default: ++ goto requeue_std_crq; ++ } ++ ++requeue_std_crq: ++ req->length = CONTROL_REQUEST_SIZE; ++ BINFO("Queue A Standard OUT Request\n"); ++ return 0; ++} +diff --git a/drivers/usb/gadget/function/u_bi_direction.h b/drivers/usb/gadget/function/u_bi_direction.h +new file mode 100755 +index 000000000000..1fe68ec6d46e +--- /dev/null ++++ b/drivers/usb/gadget/function/u_bi_direction.h +@@ -0,0 +1,212 @@ ++#ifndef __U_BI_DIRECTION_H ++#define __U_BI_DIRECTION_H ++ ++#include ++#include ++#include ++ ++#define GBI_DIRECTION_BULK_IN_BUFLEN 20 * 1024 ++#define GBI_DIRECTION_BULK_OUT_BUFLEN 40 * 1024 ++#define GBI_DIRECTION_BULK_IN_QLEN 3 ++#define GBI_DIRECTION_BULK_OUT_QLEN 1 ++ ++#define NERVE_DEVICE_NAME_SIZE 36 ++#define NERVE_NAME "usb_bi" ++#define MODULE_VERION "1.0.0" ++#define USB_PROC_DEBUG_ENABLE 1 ++#define PROG_ENTRY "usb_bi" ++ ++#define CONTROL_REQUEST_SIZE 64 ++#define MAX_NAME_LENGTH 52 ++ ++#define MASK 0xFF000000 ++#define BULK_IN_QUEUE_BASE_OFFSET 0x0F000000 ++#define BULK_OUT_QUEUE_BASE_OFFSET 0xF0000000 ++#define BULK_IN_BUFFER(off) (((off & MASK) == BULK_IN_QUEUE_BASE_OFFSET)) ++#define BULK_OUT_BUFFER(off) (((off & MASK) == BULK_OUT_QUEUE_BASE_OFFSET)) ++ ++typedef enum { ++ LOG_DBG, ++ LOG_INFO, ++ LOG_WRN, ++ LOG_ERR, ++} log_level_e; ++ ++#define BDBG(fmt, args...) \ ++ {do{if(log_level<=LOG_DBG){printk("[DBG]:%s[%d]: " fmt , __FUNCTION__,__LINE__,##args);}}while(0);} ++#define BINFO(fmt, args...) \ ++ {do{if(log_level<=LOG_INFO){printk("[INFO]:%s[%d]: " fmt , __FUNCTION__,__LINE__,##args);}}while(0);} ++#define BWRN(fmt, args...) \ ++ {do{if(log_level<=LOG_WRN){printk("[WRN]:%s[%d]: " fmt , __FUNCTION__,__LINE__,##args);}}while(0);} ++#define BERR(fmt, args...) \ ++ {do{if(log_level<=LOG_ERR){printk("[ERR]:%s[%d]: " fmt , __FUNCTION__,__LINE__,##args);}}while(0);} ++ ++typedef enum { ++ TRANSFER_IN = 0xABBA, ++ TRANSFER_OUT = 0xBAAB ++} buf_type_e; ++ ++typedef struct ++{ ++ __u32 count; ++ __u32 type; /* for usr to set */ ++ __u32 length; ++} requeset_buf_t; ++ ++typedef struct ++{ ++ __u32 type; ++ __u32 index; ++ __u32 length; ++ __u32 bytesused; ++ __u32 mem_offset; ++ __u8 *vaddr; ++} buffer_t; ++ ++typedef struct { ++ bool used; ++ buffer_t buf; ++ struct list_head list; ++} bi_data_t; ++ ++typedef struct { ++ bool inited; ++ __u32 qlen; ++ bi_data_t *buf; ++ spinlock_t lock; ++ struct list_head used_list; ++} bi_buffer_queue_t; ++ ++typedef struct { ++ __u32 magic; ++ __u32 length; ++} bi_operation_permit_t; ++ ++#define USB_CAMMAND_MAGIC 0xFDCB ++ ++typedef struct { ++ __u8 cmd; ++ __u8 hostready; ++ __u16 magic; ++ __u32 dataLength; ++ __u32 offset; ++ char name[MAX_NAME_LENGTH]; ++} bi_control_header_t; ++ ++typedef enum { ++ USB_GET_DEVICE_STATUS = 0, ++ USB_RESET_REQUEST, ++ USB_HOST_SET_DATA, ++ USB_HOST_GET_DATA ++} Usbcommands_t; ++ ++#define USB_NERVE_DEQUEUE_EVENT _IOR('N', 1, buffer_t) ++#define USB_NERVE_FINISH_EVENT _IOW('N', 2, buffer_t) ++#define USB_NERVE_DEQUEUE_BUF _IOWR('N', 3, buffer_t) ++#define USB_NERVE_QUEUE_BUF _IOWR('N', 4, buffer_t) ++#define USB_NERVE_REQBUFS _IOWR('N', 5, requeset_buf_t) ++#define USB_NERVE_QUERYBUF _IOWR('N', 6, buffer_t) ++ ++struct usb_bi_direction_options { ++ unsigned bulk_in_buflen; ++ unsigned bulk_out_buflen; ++ unsigned bulk_in_qlen; ++ unsigned bulk_out_qlen; ++}; ++ ++struct f_bd_opts { ++ struct usb_function_instance func_inst; ++ unsigned bulk_in_buflen; ++ unsigned bulk_in_qlen; ++ unsigned bulk_out_buflen; ++ unsigned bulk_out_qlen; ++ ++ /* ++ * Read/write access to configfs attributes is handled by configfs. ++ * ++ * This is to protect the data from concurrent access by read/write ++ * and create symlink/remove symlink. ++ */ ++ struct mutex lock; ++ int refcnt; ++}; ++ ++/* ++ * DEVICE_NOT_INIT ： ++ * Unreqister, the dev is unbound ++ * DEVICE_INITIALIZED : ++ * Register, the dev is bound ++ * DEVICE_WAITING : ++ * Host is cobdect to dev, and enable bi, waiting for control req ++ * DEVICE_RUNNING : ++ * A control request is dealing ++ * DEVICE_FINISHED : ++ * A data required is finished, and ready for tx ++ * DEVICE_PENDING : ++ * A OUT DATA Packet is ready to Recv ++ * ++ * Attention: user is only for user space ++ */ ++ ++typedef enum { ++ DEVICE_NOT_INIT = 0, ++ DEVICE_INITIALIZED = 0x10, ++ DEVICE_WAITING = 0x11, ++ DEVICE_RUNNING = 0x12, ++ DEVICE_FINISHED = 0x13, ++ DEVICE_PENDING = 0x14, ++} DeviceStatus_t; ++ ++struct bi_device_handle ++{ ++ bool opened; ++ dev_t major; ++ ++ DeviceStatus_t status; ++ ++ bi_buffer_queue_t bulk_in_queue; ++ bi_buffer_queue_t bulk_out_queue; ++ ++ struct bi_device *bdev; //gadget device ++ struct device *dev; //char device associated ++#if (USB_PROC_DEBUG_ENABLE==1) ++ struct proc_dir_entry* proc_entry; ++#endif ++ struct cdev cdev; ++ struct class *nclass; ++ wait_queue_head_t waitq; ++}; ++ ++struct bi_device { ++ char name[NERVE_DEVICE_NAME_SIZE]; ++ struct usb_function function; ++ unsigned bulk_in_qlen; ++ unsigned bulk_out_qlen; ++ unsigned bulk_in_buflen; ++ unsigned bulk_out_buflen; ++ struct usb_ep *in_ep; ++ struct usb_ep *out_ep; ++ struct list_head in_req_free; ++ struct list_head out_req_free; ++ struct usb_request *in_req[GBI_DIRECTION_BULK_IN_QLEN]; ++ struct usb_request *out_req[GBI_DIRECTION_BULK_OUT_QLEN]; ++ ++ spinlock_t in_req_lock; ++ spinlock_t out_req_lock; ++ ++ struct device *dev; // gadget struct releated device ++ struct bi_device_handle *devh; //module handle ++}; ++ ++/* func specific */ ++static inline struct bi_device *func_to_bi(struct usb_function *f) ++{ ++ return container_of(f, struct bi_device, function); ++} ++ ++int bi_device_register(struct device *dev, struct bi_device *ndev); ++void bi_device_unregister(struct bi_device *ndev); ++int enable_bi_device(struct bi_device *ndev); ++void disable_bi_device(struct bi_device *ndev); ++int bi_out_packet_handle(struct usb_ep *ep, struct usb_request *req); ++#endif /* __BI_DIRECTION_H */ +diff --git a/drivers/usb/gadget/function/u_uac1.h b/drivers/usb/gadget/function/u_uac1.h +old mode 100644 +new mode 100755 +index 5c2ac8e8456d..017efd3b81a6 +--- a/drivers/usb/gadget/function/u_uac1.h ++++ b/drivers/usb/gadget/function/u_uac1.h +@@ -1,82 +1,48 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +- * u_uac1.h -- interface to USB gadget "ALSA AUDIO" utilities ++ * u_uac1.h - Utility definitions for UAC1 function + * +- * Copyright (C) 2008 Bryan Wu +- * Copyright (C) 2008 Analog Devices, Inc +- * +- * Enter bugs at http://blackfin.uclinux.org/ +- * +- * Licensed under the GPL-2 or later. ++ * Copyright (C) 2016 Ruslan Bilovol + */ + +-#ifndef __U_AUDIO_H +-#define __U_AUDIO_H ++#ifndef __U_UAC1_H ++#define __U_UAC1_H + +-#include +-#include +-#include + #include + +-#include +-#include +-#include +- +-#define FILE_PCM_PLAYBACK "/dev/snd/pcmC0D0p" +-#define FILE_PCM_CAPTURE "/dev/snd/pcmC0D0c" +-#define FILE_CONTROL "/dev/snd/controlC0" +- + #define UAC1_OUT_EP_MAX_PACKET_SIZE 200 +-#define UAC1_REQ_COUNT 256 +-#define UAC1_AUDIO_BUF_SIZE 48000 +- +-/* +- * This represents the USB side of an audio card device, managed by a USB +- * function which provides control and stream interfaces. +- */ +- +-struct gaudio_snd_dev { +- struct gaudio *card; +- struct file *filp; +- struct snd_pcm_substream *substream; +- int access; +- int format; +- int channels; +- int rate; +-}; +- +-struct gaudio { +- struct usb_function func; +- struct usb_gadget *gadget; +- +- /* ALSA sound device interfaces */ +- struct gaudio_snd_dev control; +- struct gaudio_snd_dev playback; +- struct gaudio_snd_dev capture; +- +- /* TODO */ +-}; ++#define UAC1_DEF_CCHMASK 0x3 ++#define UAC1_DEF_CSRATE 48000 ++#define UAC1_DEF_CSSIZE 2 ++#define UAC1_DEF_PCHMASK 0x3 ++#define UAC1_DEF_PSRATE 48000 ++#define UAC1_DEF_PSSIZE 2 ++#define UAC1_DEF_REQ_NUM 8 ++ ++typedef enum audio_mode { ++ DISABLE_UAC, ++ ENABLE_SPEAKER, ++ ENABLE_MICROPHONE, ++ ENABLE_MIC_AND_SPK, ++ UNKNOWN_COMMAND, ++} audio_mode_e; + + struct f_uac1_opts { + struct usb_function_instance func_inst; +- int req_buf_size; +- int req_count; +- int audio_buf_size; +- char *fn_play; +- char *fn_cap; +- char *fn_cntl; ++ int c_mpsize; ++ int c_chmask; ++ int c_srate; ++ int c_ssize; ++ int p_mpsize; ++ int p_chmask; ++ int p_srate; ++ int p_ssize; ++ int req_number; + unsigned bound:1; +- unsigned fn_play_alloc:1; +- unsigned fn_cap_alloc:1; +- unsigned fn_cntl_alloc:1; ++ + struct mutex lock; + int refcnt; ++ audio_mode_e audio_play_mode; + }; + +-int gaudio_setup(struct gaudio *card); +-void gaudio_cleanup(struct gaudio *the_card); +- +-size_t u_audio_playback(struct gaudio *card, void *buf, size_t count); +-int u_audio_get_playback_channels(struct gaudio *card); +-int u_audio_get_playback_rate(struct gaudio *card); +- +-#endif /* __U_AUDIO_H */ ++#endif /* __U_UAC1_H */ +diff --git a/drivers/usb/gadget/function/u_uac1_legacy.c b/drivers/usb/gadget/function/u_uac1_legacy.c +new file mode 100755 +index 000000000000..8ead972a97ec +--- /dev/null ++++ b/drivers/usb/gadget/function/u_uac1_legacy.c +@@ -0,0 +1,539 @@ ++/* ++ * u_uac1.c -- ALSA audio utilities for Gadget stack ++ * ++ * Copyright (C) 2008 Bryan Wu ++ * Copyright (C) 2008 Analog Devices, Inc ++ * ++ * Enter bugs at http://blackfin.uclinux.org/ ++ * ++ * Licensed under the GPL-2 or later. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "u_uac1_legacy.h" ++ ++/* ++ * This component encapsulates the ALSA devices for USB audio gadget ++ */ ++int gaudio_mixer_control(int info_id, int value) ++{ ++ char cmd_bin[50] = "\0"; ++ char cur_cmd[100] = "\0"; ++ ++ char *cmd_argv[] = {cmd_bin, "-c", cur_cmd, NULL}; ++ char *cmd_envp[] = { ++ "HOME=/", ++ "TERM=linux", ++ "PATH=/sbin:/usr/sbin:/bin:/usr/bin", ++ "LD_LIBRARY_PATH=/lib", ++ NULL ++ }; ++ ++ switch (info_id) ++ { ++ case CAPTURE_VOLUME_ID: ++ sprintf(cmd_bin, "/bin/sh"); ++ sprintf(cur_cmd, "echo set_ai_volume 0 %d 0 > /proc/mi_modules/mi_ai/mi_ai0", value); ++ break; ++ default: ++ printk("Unknow mixer info\n"); ++ return -1; ++ } ++ ++ return call_usermodehelper(cmd_bin, cmd_argv, cmd_envp, UMH_WAIT_PROC); ++} ++ ++/*-------------------------------------------------------------------------*/ ++/** ++ * Some ALSA internal helper functions ++ */ ++static int snd_interval_refine_set(struct snd_interval *i, unsigned int val) ++{ ++ struct snd_interval t; ++ t.empty = 0; ++ t.min = t.max = val; ++ t.openmin = t.openmax = 0; ++ t.integer = 1; ++ return snd_interval_refine(i, &t); ++} ++ ++static int _snd_pcm_hw_param_set(struct snd_pcm_hw_params *params, ++ snd_pcm_hw_param_t var, unsigned int val, ++ int dir) ++{ ++ int changed; ++ if (hw_is_mask(var)) { ++ struct snd_mask *m = hw_param_mask(params, var); ++ if (val == 0 && dir < 0) { ++ changed = -EINVAL; ++ snd_mask_none(m); ++ } else { ++ if (dir > 0) ++ val++; ++ else if (dir < 0) ++ val--; ++ changed = snd_mask_refine_set( ++ hw_param_mask(params, var), val); ++ } ++ } else if (hw_is_interval(var)) { ++ struct snd_interval *i = hw_param_interval(params, var); ++ if (val == 0 && dir < 0) { ++ changed = -EINVAL; ++ snd_interval_none(i); ++ } else if (dir == 0) ++ changed = snd_interval_refine_set(i, val); ++ else { ++ struct snd_interval t; ++ t.openmin = 1; ++ t.openmax = 1; ++ t.empty = 0; ++ t.integer = 0; ++ if (dir < 0) { ++ t.min = val - 1; ++ t.max = val; ++ } else { ++ t.min = val; ++ t.max = val+1; ++ } ++ changed = snd_interval_refine(i, &t); ++ } ++ } else ++ return -EINVAL; ++ if (changed) { ++ params->cmask |= 1 << var; ++ params->rmask |= 1 << var; ++ } ++ return changed; ++} ++/*-------------------------------------------------------------------------*/ ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++/** ++ * Set default hardware params ++ */ ++static int capture_default_hw_params(struct gaudio_snd_dev *snd) ++{ ++ struct snd_pcm_substream *substream = snd->substream; ++ struct snd_pcm_hw_params *params; ++ struct snd_pcm_sw_params sparams; ++ snd_pcm_sframes_t result; ++ struct f_uac1_legacy_opts *audio_opts = ++ container_of(snd->card->func.fi, struct f_uac1_legacy_opts, func_inst); ++ ++ /* ++ * SNDRV_PCM_ACCESS_RW_INTERLEAVED, ++ * SNDRV_PCM_FORMAT_S16_LE ++ * CHANNELS: 1 ++ * RATE: 16000 ++ */ ++ snd->access = SNDRV_PCM_ACCESS_RW_INTERLEAVED; ++ snd->format = SNDRV_PCM_FORMAT_S16_LE; ++ snd->channels = audio_opts->capture_channel_count; ++ snd->rate = audio_opts->capture_sample_rate; ++ snd->period_bytes = audio_opts->audio_capture_period_size; ++ snd->buffer_bytes = audio_opts->audio_capture_buf_size; ++ ++ params = kzalloc(sizeof(*params), GFP_KERNEL); ++ if (!params) ++ return -ENOMEM; ++ ++ _snd_pcm_hw_params_any(params); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_ACCESS, ++ snd->access, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_FORMAT, ++ snd->format, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_CHANNELS, ++ snd->channels, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_RATE, ++ snd->rate, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ snd->period_bytes, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, ++ snd->buffer_bytes, 0); ++ ++ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_DROP, NULL); ++ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_HW_PARAMS, params); ++ ++ /*sw params*/ ++ memset(&sparams, 0, sizeof(sparams)); ++ sparams.tstamp_mode = SNDRV_PCM_TSTAMP_ENABLE; ++ sparams.period_step = 1; ++ sparams.avail_min = 1; ++ ++ sparams.start_threshold = 1; ++ /* pick a high stop threshold - todo: does this need further tuning */ ++ sparams.stop_threshold = snd->buffer_bytes * 5; ++ sparams.silence_size = 0; ++ sparams.silence_threshold = 0; ++ sparams.boundary = snd->buffer_bytes / snd->format; ++ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_SW_PARAMS, &sparams); ++ ++ result = snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_PREPARE, NULL); ++ if (result < 0) { ++ ERROR(snd->card, ++ "Preparing sound card failed: %d\n", (int)result); ++ kfree(params); ++ return result; ++ } ++ ++ /* Store the hardware parameters */ ++ snd->access = params_access(params); ++ snd->format = params_format(params); ++ snd->channels = params_channels(params); ++ snd->rate = params_rate(params); ++ ++ kfree(params); ++ ++ INFO(snd->card, ++ "Capture Dev Hw params: access %x, format %x, channels %d, rate %d\n", ++ snd->access, snd->format, snd->channels, snd->rate); ++ ++ return 0; ++} ++#endif ++/** ++ * Set default hardware params ++ */ ++static int playback_default_hw_params(struct gaudio_snd_dev *snd) ++{ ++ struct snd_pcm_substream *substream = snd->substream; ++ struct snd_pcm_hw_params *params; ++ snd_pcm_sframes_t result; ++ struct f_uac1_legacy_opts *audio_opts = ++ container_of(snd->card->func.fi, struct f_uac1_legacy_opts, func_inst); ++ ++ /* ++ * SNDRV_PCM_ACCESS_RW_INTERLEAVED, ++ * SNDRV_PCM_FORMAT_S16_LE ++ * CHANNELS: 1 ++ * RATE: 16000 ++ */ ++ snd->access = SNDRV_PCM_ACCESS_RW_INTERLEAVED; ++ snd->format = SNDRV_PCM_FORMAT_S16_LE; ++ snd->channels = audio_opts->playback_channel_count; ++ snd->rate = audio_opts->playback_sample_rate; ++ snd->period_bytes = audio_opts->audio_playback_buf_size / 2; ++ snd->buffer_bytes = audio_opts->audio_playback_buf_size; ++ ++ params = kzalloc(sizeof(*params), GFP_KERNEL); ++ if (!params) ++ return -ENOMEM; ++ ++ _snd_pcm_hw_params_any(params); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_ACCESS, ++ snd->access, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_FORMAT, ++ snd->format, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_CHANNELS, ++ snd->channels, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_RATE, ++ snd->rate, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ snd->period_bytes, 0); ++ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, ++ snd->buffer_bytes, 0); ++ ++ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_DROP, NULL); ++ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_HW_PARAMS, params); ++ ++ result = snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_PREPARE, NULL); ++ if (result < 0) { ++ ERROR(snd->card, ++ "Preparing sound card failed: %d\n", (int)result); ++ kfree(params); ++ return result; ++ } ++ ++ /* Store the hardware parameters */ ++ snd->access = params_access(params); ++ snd->format = params_format(params); ++ snd->channels = params_channels(params); ++ snd->rate = params_rate(params); ++ ++ kfree(params); ++ ++ INFO(snd->card, ++ "Capture Dev Hw params: access %x, format %x, channels %d, rate %d\n", ++ snd->access, snd->format, snd->channels, snd->rate); ++ ++ return 0; ++} ++/** ++ * Capture audio buffer data by ALSA PCM device ++ */ ++size_t u_audio_capture(struct gaudio *card, void *buf, size_t count) ++{ ++ struct gaudio_snd_dev *snd = &card->capture; ++ struct snd_pcm_substream *substream = snd->substream; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ mm_segment_t old_fs; ++ ssize_t result, retry_count = 0; ++ snd_pcm_sframes_t frames; ++#ifdef debug_uac ++ static loff_t f_pos = 0; ++ struct file* fp = NULL; ++ int rcount = 0; ++#endif ++try_again: ++ if(retry_count++ > 0 && retry_count < 1000) ++ msleep(30); ++ else if(retry_count > 1000) ++ return -EINVAL; ++ ++ if (runtime->status->state == SNDRV_PCM_STATE_XRUN || ++ runtime->status->state == SNDRV_PCM_STATE_SUSPENDED || ++ runtime->status->state == SNDRV_PCM_STATE_SETUP) { ++ result = snd_pcm_kernel_ioctl(substream, ++ SNDRV_PCM_IOCTL_PREPARE, NULL); ++ if (result < 0) { ++ pr_err("Preparing capture failed: %d\n", ++ (int)result); ++ return result; ++ } ++ } ++ frames = bytes_to_frames(runtime, count); ++ old_fs = get_fs(); ++ set_fs(KERNEL_DS); ++ ++ pr_debug("frames = %d, count = %zd \n", (int)frames, count); ++#ifdef debug_uac ++ fp = filp_open("/config/input.pcm",O_RDONLY ,0); ++ if(IS_ERR(fp)) { ++ pr_err("No such PCM File: %s\n", "/config/input.pcm"); ++ set_fs(old_fs); ++ goto try_again;//do nothing ++ } ++ else { ++ rcount = vfs_read(fp,buf,count,&f_pos); ++ if(count > rcount) ++ f_pos = 0; ++ filp_close(fp,NULL); ++ pr_debug("read count %d need count %d \n",rcount,count); ++ } ++#else ++ result = snd_pcm_lib_read(substream, buf, frames); ++ if (result != frames) { ++ pr_debug("Capture warring: %d count%d, state%d \n", (int)result, count, runtime->status->state); ++ set_fs(old_fs); ++ goto try_again; ++ } ++#endif ++ set_fs(old_fs); ++ return 0; ++} ++ ++/** ++ * Playback audio buffer data by ALSA PCM device ++ */ ++size_t u_audio_playback(struct gaudio *card, void *buf, size_t count) ++{ ++ struct gaudio_snd_dev *snd = &card->playback; ++ struct snd_pcm_substream *substream = snd->substream; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ mm_segment_t old_fs; ++ ssize_t result; ++ snd_pcm_sframes_t frames; ++ ++try_again: ++ if (runtime->status->state == SNDRV_PCM_STATE_XRUN || ++ runtime->status->state == SNDRV_PCM_STATE_SUSPENDED) { ++ result = snd_pcm_kernel_ioctl(substream, ++ SNDRV_PCM_IOCTL_PREPARE, NULL); ++ if (result < 0) { ++ ERROR(card, "Preparing sound card failed: %d\n", ++ (int)result); ++ return result; ++ } ++ } ++ ++ frames = bytes_to_frames(runtime, count); ++ old_fs = get_fs(); ++ set_fs(KERNEL_DS); ++ pr_debug("frames = %d, count = %zd \n", (int)frames, count); ++ ++ result = snd_pcm_lib_write(snd->substream, (void __user *)buf, frames); ++ if (result != frames) { ++ pr_debug("Playback error: %d\n", (int)result); ++ set_fs(old_fs); ++ goto try_again; ++ } ++ set_fs(old_fs); ++ ++ return 0; ++} ++ ++int u_audio_get_playback_channels(struct gaudio *card) ++{ ++ return card->playback.channels; ++} ++ ++int u_audio_get_playback_rate(struct gaudio *card) ++{ ++ return card->playback.rate; ++} ++ ++int u_audio_get_capture_channels(struct gaudio *card) ++{ ++ return card->capture.channels; ++} ++ ++int u_audio_get_capture_rate(struct gaudio *card) ++{ ++ return card->capture.rate; ++} ++ ++/** ++ * Open ALSA PCM and control device files ++ * Initial the PCM or control device ++ */ ++static int gaudio_open_snd_dev(struct gaudio *card) ++{ ++ struct snd_pcm_file *pcm_file; ++ struct gaudio_snd_dev *snd; ++ struct f_uac1_legacy_opts *opts; ++ char *fn_play, *fn_cap, *fn_cntl; ++ ++ opts = container_of(card->func.fi, struct f_uac1_legacy_opts, func_inst); ++ fn_play = opts->fn_play; ++ fn_cap = opts->fn_cap; ++ fn_cntl = opts->fn_cntl; ++ ++ /* Open control device */ ++ snd = &card->control; ++ snd->filp = filp_open(fn_cntl, O_RDWR, 0); ++ if (IS_ERR(snd->filp)) { ++ int ret = PTR_ERR(snd->filp); ++ ERROR(card, "unable to open sound control device file: %s\n", ++ fn_cntl); ++ snd->filp = NULL; ++ return ret; ++ } ++ snd->card = card; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ /* Open PCM playback device and setup substream */ ++ if(ENABLE_SPEAKER == opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == opts->audio_play_mode ) ++#endif ++ { ++ snd = &card->playback; ++ snd->filp = filp_open(fn_play, O_WRONLY, 0); ++ if (IS_ERR(snd->filp)) { ++ int ret = PTR_ERR(snd->filp); ++ ERROR(card, "No such PCM playback device: %s\n", fn_play); ++ snd->substream = NULL; ++ snd->card = NULL; ++ snd->filp = NULL; ++ return ret; ++ } else ++ { ++ pcm_file = snd->filp->private_data; ++ snd->substream = pcm_file->substream; ++ snd->card = card; ++ playback_default_hw_params(snd); ++ } ++ } ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ /* Open PCM capture device and setup substream */ ++ if(ENABLE_MICROPHONE == opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == opts->audio_play_mode ) ++ { ++ snd = &card->capture; ++ snd->filp = filp_open(fn_cap, O_RDONLY, 0); ++ if (IS_ERR(snd->filp)) { ++ int ret = PTR_ERR(snd->filp); ++ ERROR(card, "No such PCM capture device: %s\n", fn_cap); ++ snd->substream = NULL; ++ snd->card = NULL; ++ snd->filp = NULL; ++ return ret; ++ } else { ++ pcm_file = snd->filp->private_data; ++ snd->substream = pcm_file->substream; ++ snd->card = card; ++ capture_default_hw_params(snd); ++ } ++ } ++#endif ++ return 0; ++} ++ ++/** ++ * Close ALSA PCM and control device files ++ */ ++static int gaudio_close_snd_dev(struct gaudio *gau) ++{ ++ struct gaudio_snd_dev *snd; ++ struct f_uac1_legacy_opts *opts; ++ ++ opts = container_of(gau->func.fi, struct f_uac1_legacy_opts, func_inst); ++ ++ /* Close control device */ ++ snd = &gau->control; ++ if (snd->filp) ++ filp_close(snd->filp, NULL); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ /* Close PCM playback device and setup substream */ ++ if(ENABLE_SPEAKER == opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == opts->audio_play_mode ) ++#endif ++ { ++ snd = &gau->playback; ++ if (snd->filp) ++ filp_close(snd->filp, NULL); ++ } ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ /* Close PCM capture device and setup substream */ ++ if(ENABLE_MICROPHONE == opts->audio_play_mode || ++ ENABLE_MIC_AND_SPK == opts->audio_play_mode ) ++ { ++ snd = &gau->capture; ++ if (snd->filp) ++ filp_close(snd->filp, NULL); ++ } ++#endif ++ ++ return 0; ++} ++ ++/** ++ * gaudio_setup - setup ALSA interface and preparing for USB transfer ++ * ++ * This sets up PCM, mixer or MIDI ALSA devices fore USB gadget using. ++ * ++ * Returns negative errno, or zero on success ++ */ ++int gaudio_setup(struct gaudio *card) ++{ ++ int ret; ++ ++ ret = gaudio_open_snd_dev(card); ++ if (ret) ++ ERROR(card, "we need at least one control device\n"); ++ ++ return ret; ++ ++} ++ ++/** ++ * gaudio_cleanup - remove ALSA device interface ++ * ++ * This is called to free all resources allocated by @gaudio_setup(). ++ */ ++void gaudio_cleanup(struct gaudio *the_card) ++{ ++ if (the_card) ++ gaudio_close_snd_dev(the_card); ++} ++ +diff --git a/drivers/usb/gadget/function/u_uac1_legacy.h b/drivers/usb/gadget/function/u_uac1_legacy.h +new file mode 100755 +index 000000000000..6fa6d768afa1 +--- /dev/null ++++ b/drivers/usb/gadget/function/u_uac1_legacy.h +@@ -0,0 +1,137 @@ ++/* ++ * u_uac1.h -- interface to USB gadget "ALSA AUDIO" utilities ++ * ++ * Copyright (C) 2008 Bryan Wu ++ * Copyright (C) 2008 Analog Devices, Inc ++ * ++ * Enter bugs at http://blackfin.uclinux.org/ ++ * ++ * Licensed under the GPL-2 or later. ++ */ ++ ++#ifndef __U_AUDIO_H ++#define __U_AUDIO_H ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define FILE_PCM_PLAYBACK "/dev/snd/pcmC0D0p" ++#define FILE_PCM_CAPTURE "/dev/snd/pcmC0D0c" ++#define FILE_CONTROL "/dev/snd/controlC0" ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++#define UAC1_CAPTURE_SAMPLE_RATE 16000 ++#define UAC1_CAPTURE_CHANNEL_COUNT 1 ++#define UAC1_IN_EP_MAX_PACKET_SIZE 32//512 ++#define UAC1_IN_REQ_COUNT 16 ++#define UAC1_AUDIO_CAPTURE_BUF_SIZE 4096 ++#define UAC1_AUDIO_PTN_PER_FRAME_SIZE 1024 ++ ++#define UAC1_PLAYBACK_SAMPLE_RATE 16000 ++#define UAC1_PLAYBACK_CHANNEL_COUNT 1 ++#endif ++#define UAC1_OUT_EP_MAX_PACKET_SIZE 512 ++#define UAC1_OUT_REQ_COUNT 8 ++#define UAC1_AUDIO_PLAYBACK_BUF_SIZE 2048 ++ ++/** ++ * mixer control info ++ * ++ * AMIC: (-6, 57)db, value(0, 21) ++ **/ ++#define UAC_VOLUME_STEP 256 ++#define CAPTURE_VOLUME_ID 0 ++#define CAPTURE_VOLUME_MAX 57 ++#define CAPTURE_VOLUME_MIN -6 ++#define CAPTURE_VOLUME_STEP 3 ++#define CAPTURE_VOLUME_CUR 12 ++ ++#define UAC_VOLUME_ATTR_TO_DB(attr) ((s8)((attr / UAC_VOLUME_STEP))) ++#define DB_TO_UAC_VOLUME_ATTR(db) ((u16)(db * UAC_VOLUME_STEP)) ++#define DB_TO_MIXER_VALUE(db) (db/CAPTURE_VOLUME_STEP + 2) ++#define UAC_VOLUME_ATTR_TO_MIXER_VALUE(attr) DB_TO_MIXER_VALUE(UAC_VOLUME_ATTR_TO_DB(attr)) ++ ++/* ++ * This represents the USB side of an audio card device, managed by a USB ++ * function which provides control and stream interfaces. ++ */ ++ ++struct gaudio_snd_dev { ++ struct gaudio *card; ++ struct file *filp; ++ struct snd_pcm_substream *substream; ++ int access; ++ int format; ++ int channels; ++ int rate; ++ int period_bytes; ++ int buffer_bytes; ++}; ++ ++struct gaudio { ++ struct usb_function func; ++ struct usb_gadget *gadget; ++ ++ /* ALSA sound device interfaces */ ++ struct gaudio_snd_dev control; ++ struct gaudio_snd_dev playback; ++ struct gaudio_snd_dev capture; ++ ++ /* TODO */ ++}; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++typedef enum audio_mode { ++ DISABLE_UAC, ++ ENABLE_SPEAKER, ++ ENABLE_MICROPHONE, ++ ENABLE_MIC_AND_SPK, ++ UNKNOWN_COMMAND, ++} audio_mode_e; ++#endif ++struct f_uac1_legacy_opts { ++ struct usb_function_instance func_inst; ++ int out_req_buf_size; ++ int out_req_count; ++ int audio_playback_buf_size; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ int playback_channel_count; ++ int playback_sample_rate; ++ ++ int capture_channel_count; ++ int capture_sample_rate; ++ int in_req_buf_size; ++ int in_req_count; ++ int audio_capture_period_size; ++ int audio_capture_buf_size; ++ audio_mode_e audio_play_mode; ++#endif ++ char *fn_play; ++ char *fn_cap; ++ char *fn_cntl; ++ unsigned bound:1; ++ unsigned fn_play_alloc:1; ++ unsigned fn_cap_alloc:1; ++ unsigned fn_cntl_alloc:1; ++ struct mutex lock; ++ int refcnt; ++}; ++ ++int gaudio_setup(struct gaudio *card); ++void gaudio_cleanup(struct gaudio *the_card); ++ ++size_t u_audio_playback(struct gaudio *card, void *buf, size_t count); ++size_t u_audio_capture(struct gaudio *card, void *buf, size_t count); ++ ++int u_audio_get_playback_channels(struct gaudio *card); ++int u_audio_get_playback_rate(struct gaudio *card); ++int u_audio_get_capture_channels(struct gaudio *card); ++int u_audio_get_capture_rate(struct gaudio *card); ++int gaudio_mixer_control(int info_id, int value); ++#endif /* __U_AUDIO_H */ +diff --git a/drivers/usb/gadget/function/u_uac2.h b/drivers/usb/gadget/function/u_uac2.h +old mode 100644 +new mode 100755 +index 78dd37279bd4..82048791eb6e +--- a/drivers/usb/gadget/function/u_uac2.h ++++ b/drivers/usb/gadget/function/u_uac2.h +@@ -1,3 +1,4 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* + * u_uac2.h + * +@@ -6,11 +7,7 @@ + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * +- * Author: Andrzej Pietrasiewicz +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. ++ * Author: Andrzej Pietrasiewicz + */ + + #ifndef U_UAC2_H +@@ -24,6 +21,7 @@ + #define UAC2_DEF_CCHMASK 0x3 + #define UAC2_DEF_CSRATE 64000 + #define UAC2_DEF_CSSIZE 2 ++#define UAC2_DEF_REQ_NUM 2 + + struct f_uac2_opts { + struct usb_function_instance func_inst; +@@ -33,6 +31,7 @@ struct f_uac2_opts { + int c_chmask; + int c_srate; + int c_ssize; ++ int req_number; + bool bound; + + struct mutex lock; +diff --git a/drivers/usb/gadget/function/u_uvc.h b/drivers/usb/gadget/function/u_uvc.h +old mode 100644 +new mode 100755 +index 4676b60a5063..680935ab826a +--- a/drivers/usb/gadget/function/u_uvc.h ++++ b/drivers/usb/gadget/function/u_uvc.h +@@ -19,15 +19,45 @@ + #include + #include + ++#ifndef CONFIG_MULTI_STREAM_FUNC_NUM ++#define CONFIG_MULTI_STREAM_FUNC_NUM 1 ++#endif ++ ++#define MAX_STREAM_SUPPORT 4 ++#define DEFAULT_STREAM_NAME "UVC Camera" ++#define MULTI_STREAM_NUM CONFIG_MULTI_STREAM_FUNC_NUM ++ ++#if (MULTI_STREAM_NUM>1) ++#define CONFIG_SS_GADGET_UVC_MULTI_STREAM ++#endif ++ + #define fi_to_f_uvc_opts(f) container_of(f, struct f_uvc_opts, func_inst) ++#define fuvc_to_gadget(f) (f.config->cdev->gadget) ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++#define video_to_stream(f) container_of(f, struct uvc_streaming, video) ++#define video_to_uvc(f) (video_to_stream(f))->dev ++#else ++#define video_to_uvc(f) container_of(f, struct uvc_device, video) ++#endif + + struct f_uvc_opts { + struct usb_function_instance func_inst; + unsigned int uvc_gadget_trace_param; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ unsigned int streaming_interval[MAX_STREAM_SUPPORT]; ++ unsigned int streaming_maxpacket[MAX_STREAM_SUPPORT]; ++ unsigned int streaming_maxburst[MAX_STREAM_SUPPORT]; ++ const char * streaming_name[MAX_STREAM_SUPPORT]; ++#else + unsigned int streaming_interval; + unsigned int streaming_maxpacket; + unsigned int streaming_maxburst; ++ const char * streaming_name; ++#endif + ++#if defined(CONFIG_SS_GADGET) || defined(CONFIG_SS_GADGET_MODULE) ++ bool bulk_streaming_ep; ++#endif + /* + * Control descriptors array pointers for full-/high-speed and + * super-speed. They point by default to the uvc_fs_control_cls and +diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h +old mode 100644 +new mode 100755 +index 7d3bb6272e06..97947c1814cb +--- a/drivers/usb/gadget/function/uvc.h ++++ b/drivers/usb/gadget/function/uvc.h +@@ -24,7 +24,8 @@ + #define UVC_EVENT_STREAMOFF (V4L2_EVENT_PRIVATE_START + 3) + #define UVC_EVENT_SETUP (V4L2_EVENT_PRIVATE_START + 4) + #define UVC_EVENT_DATA (V4L2_EVENT_PRIVATE_START + 5) +-#define UVC_EVENT_LAST (V4L2_EVENT_PRIVATE_START + 5) ++#define UVC_EVENT_FORCEIDR (V4L2_EVENT_PRIVATE_START + 6) ++#define UVC_EVENT_LAST (V4L2_EVENT_PRIVATE_START + 6) + + struct uvc_request_data + { +@@ -59,6 +60,7 @@ struct uvc_event + #include + #include + ++#include "u_uvc.h" + #include "uvc_queue.h" + + #define UVC_TRACE_PROBE (1 << 0) +@@ -83,20 +85,23 @@ extern unsigned int uvc_gadget_trace_param; + printk(KERN_DEBUG "uvcvideo: " msg); \ + } while (0) + +-#define uvc_warn_once(dev, warn, msg...) \ +- do { \ +- if (!test_and_set_bit(warn, &dev->warnings)) \ +- printk(KERN_INFO "uvcvideo: " msg); \ +- } while (0) +- +-#define uvc_printk(level, msg...) \ +- printk(level "uvcvideo: " msg) ++#define uvcg_dbg(f, fmt, args...) \ ++ dev_dbg(&(f)->config->cdev->gadget->dev, "%s: " fmt, (f)->name, ##args) ++#define uvcg_info(f, fmt, args...) \ ++ dev_info(&(f)->config->cdev->gadget->dev, "%s: " fmt, (f)->name, ##args) ++#define uvcg_warn(f, fmt, args...) \ ++ dev_warn(&(f)->config->cdev->gadget->dev, "%s: " fmt, (f)->name, ##args) ++#define uvcg_err(f, fmt, args...) \ ++ dev_err(&(f)->config->cdev->gadget->dev, "%s: " fmt, (f)->name, ##args) + + /* ------------------------------------------------------------------------ + * Driver specific constants + */ +- +-#define UVC_NUM_REQUESTS 4 ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++#define UVC_NUM_REQUESTS 8 ++#else ++#define UVC_NUM_REQUESTS 20 ++#endif + #define UVC_MAX_REQUEST_SIZE 64 + #define UVC_MAX_EVENTS 4 + +@@ -104,10 +109,15 @@ extern unsigned int uvc_gadget_trace_param; + * Structures + */ + +-struct uvc_video +-{ ++struct uvc_video { ++ struct uvc_device *uvc; + struct usb_ep *ep; + ++ struct usb_endpoint_descriptor ep_desc; ++ struct usb_ss_ep_comp_descriptor ep_comp_desc; ++ ++ struct work_struct pump; ++ + /* Frame parameters */ + u8 bpp; + u32 fcc; +@@ -120,6 +130,7 @@ struct uvc_video + unsigned int req_size; + struct usb_request *req[UVC_NUM_REQUESTS]; + __u8 *req_buffer[UVC_NUM_REQUESTS]; ++ dma_addr_t req_buffer_dma_handle[UVC_NUM_REQUESTS]; + struct list_head req_free; + spinlock_t req_lock; + +@@ -132,6 +143,7 @@ struct uvc_video + + struct uvc_video_queue queue; + unsigned int fid; ++ unsigned int altsetting; + }; + + enum uvc_state +@@ -141,6 +153,65 @@ enum uvc_state + UVC_STATE_STREAMING, + }; + ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++struct uvc_device ++{ ++ //struct video_device vdev; ++ //struct v4l2_device v4l2_dev; ++ //enum uvc_state state; ++ struct usb_function func; ++ //struct uvc_video video; ++ struct list_head streams; ++ unsigned int nstreams; ++ ++ /* Descriptors */ ++ struct { ++ const struct uvc_descriptor_header * const *fs_control; ++ const struct uvc_descriptor_header * const *ss_control; ++ const struct uvc_descriptor_header * const *fs_streaming; ++ const struct uvc_descriptor_header * const *hs_streaming; ++ const struct uvc_descriptor_header * const *ss_streaming; ++ } desc; ++ ++ unsigned int control_intf; ++ struct usb_ep *control_ep; ++ struct usb_request *control_req; ++ void *control_buf; ++ ++ /* Events */ ++ unsigned int event_length; ++ unsigned int event_setup_out : 1; ++}; ++ ++struct uvc_streaming { ++ struct list_head list; ++ struct uvc_device *dev; ++ struct video_device vdev; ++ struct v4l2_device v4l2_dev; ++ struct uvc_video video; ++ int active; ++ enum uvc_state state; ++ ++ unsigned char iInterface; ++ unsigned char bTerminalID; ++ unsigned int streaming_intf; ++ ++ unsigned int fs_streaming_size; ++ unsigned int hs_streaming_size; ++ unsigned int ss_streaming_size; ++ unsigned int event_setup_out : 1; ++ /* Descriptors */ ++ struct { ++ const struct uvc_descriptor_header * const *fs_streaming; ++ const struct uvc_descriptor_header * const *hs_streaming; ++ const struct uvc_descriptor_header * const *ss_streaming; ++ } desc; ++ ++ void *fs_streaming_buf; ++ void *hs_streaming_buf; ++ void *ss_streaming_buf; ++}; ++#else + struct uvc_device + { + struct video_device vdev; +@@ -169,7 +240,7 @@ struct uvc_device + unsigned int event_length; + unsigned int event_setup_out : 1; + }; +- ++#endif + static inline struct uvc_device *to_uvc(struct usb_function *f) + { + return container_of(f, struct uvc_device, func); +@@ -188,6 +259,56 @@ struct uvc_file_handle + * Functions + */ + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++static inline struct scatterlist *sg_advance(struct scatterlist *sg, int consumed) ++{ ++ while (consumed >= sg->length) { ++ consumed -= sg->length; ++ ++ sg = sg_next(sg); ++ if (!sg) ++ break; ++ } ++ ++ WARN_ON(!sg && consumed); ++ ++ if (!sg) ++ return NULL; ++ ++ sg->offset += consumed; ++ sg->length -= consumed; ++ ++ if (sg->offset >= PAGE_SIZE) { ++ struct page *page = ++ nth_page(sg_page(sg), sg->offset / PAGE_SIZE); ++ sg_set_page(sg, page, sg->length, sg->offset % PAGE_SIZE); ++ } ++ ++ return sg; ++} ++ ++static inline int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len) ++{ ++ while (len > sg_from->length) { ++ len -= sg_from->length; ++ ++ sg_set_page(sg_to, sg_page(sg_from), ++ sg_from->length, sg_from->offset); ++ ++ sg_to = sg_next(sg_to); ++ sg_from = sg_next(sg_from); ++ ++ if (len && (!sg_from || !sg_to)) ++ return -ENOMEM; ++ } ++ ++ if (len) ++ sg_set_page(sg_to, sg_page(sg_from), ++ len, sg_from->offset); ++ sg_mark_end(sg_to); ++ return 0; ++} ++#endif + extern void uvc_function_setup_continue(struct uvc_device *uvc); + extern void uvc_endpoint_stream(struct uvc_device *dev); + +diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c +index d7dcd39fe12c..9b899d9a23ae 100644 +--- a/drivers/usb/gadget/function/uvc_configfs.c ++++ b/drivers/usb/gadget/function/uvc_configfs.c +@@ -2187,21 +2187,25 @@ UVC_ATTR(f_uvc_opts_, cname, cname) + + #define identity_conv(x) (x) + ++#ifndef CONFIG_SS_GADGET_UVC_MULTI_STREAM + UVCG_OPTS_ATTR(streaming_interval, streaming_interval, identity_conv, + kstrtou8, u8, identity_conv, 16); + UVCG_OPTS_ATTR(streaming_maxpacket, streaming_maxpacket, le16_to_cpu, + kstrtou16, u16, le16_to_cpu, 3072); + UVCG_OPTS_ATTR(streaming_maxburst, streaming_maxburst, identity_conv, + kstrtou8, u8, identity_conv, 15); ++#endif + + #undef identity_conv + + #undef UVCG_OPTS_ATTR + + static struct configfs_attribute *uvc_attrs[] = { ++#ifndef CONFIG_SS_GADGET_UVC_MULTI_STREAM + &f_uvc_opts_attr_streaming_interval, + &f_uvc_opts_attr_streaming_maxpacket, + &f_uvc_opts_attr_streaming_maxburst, ++#endif + NULL, + }; + +diff --git a/drivers/usb/gadget/function/uvc_queue.c b/drivers/usb/gadget/function/uvc_queue.c +index 6377e9fee6e5..8db84cd363a7 100644 +--- a/drivers/usb/gadget/function/uvc_queue.c ++++ b/drivers/usb/gadget/function/uvc_queue.c +@@ -21,8 +21,12 @@ + #include + + #include +-#include + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++#include ++#else ++#include ++#endif + #include "uvc.h" + + /* ------------------------------------------------------------------------ +@@ -54,7 +58,9 @@ static int uvc_queue_setup(struct vb2_queue *vq, + *nplanes = 1; + + sizes[0] = video->imagesize; +- ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ alloc_devs[0] = &video->uvc->func.config->cdev->gadget->dev; ++#endif + return 0; + } + +@@ -63,6 +69,12 @@ static int uvc_buffer_prepare(struct vb2_buffer *vb) + struct uvc_video_queue *queue = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct uvc_buffer *buf = container_of(vbuf, struct uvc_buffer, buf); ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_video *video = container_of(queue, struct uvc_video, queue); ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++ struct sg_table *sgt; ++#endif + + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT && + vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) { +@@ -81,6 +93,18 @@ static int uvc_buffer_prepare(struct vb2_buffer *vb) + else + buf->bytesused = vb2_get_plane_payload(vb, 0); + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ sgt = vb2_plane_cookie(vb, 0); ++ sg_alloc_table(&buf->sgt, sgt->nents, GFP_KERNEL); ++ sg_init_table(buf->sgt.sgl, sgt->nents); ++ if (sg_copy(sgt->sgl, buf->sgt.sgl, buf->bytesused)) ++ { ++ printk("%s sg copy error\n", __func__); ++ } ++ } ++#endif + return 0; + } + +@@ -89,10 +113,18 @@ static void uvc_buffer_queue(struct vb2_buffer *vb) + struct uvc_video_queue *queue = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct uvc_buffer *buf = container_of(vbuf, struct uvc_buffer, buf); ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_video *video = container_of(queue, struct uvc_video, queue); ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif + unsigned long flags; + + spin_lock_irqsave(&queue->irqlock, flags); + ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ buf->bFrameEnd = queue->bFrameEnd; ++#endif + if (likely(!(queue->flags & UVC_QUEUE_DISCONNECTED))) { + list_add_tail(&buf->queue, &queue->irqqueue); + } else { +@@ -100,6 +132,12 @@ static void uvc_buffer_queue(struct vb2_buffer *vb) + * directly. The next QBUF call will fail with -ENODEV. + */ + buf->state = UVC_BUF_STATE_ERROR; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ sg_free_table(&buf->sgt); ++ } ++#endif + vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); + } + +@@ -125,7 +163,11 @@ int uvcg_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type, + queue->queue.buf_struct_size = sizeof(struct uvc_buffer); + queue->queue.ops = &uvc_queue_qops; + queue->queue.lock = lock; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ queue->queue.mem_ops = &vb2_dma_sg_memops; ++#else + queue->queue.mem_ops = &vb2_vmalloc_memops; ++#endif + queue->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC + | V4L2_BUF_FLAG_TSTAMP_SRC_EOF; + ret = vb2_queue_init(&queue->queue); +@@ -236,6 +278,11 @@ unsigned long uvcg_queue_get_unmapped_area(struct uvc_video_queue *queue, + void uvcg_queue_cancel(struct uvc_video_queue *queue, int disconnect) + { + struct uvc_buffer *buf; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_video *video = container_of(queue, struct uvc_video, queue); ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif + unsigned long flags; + + spin_lock_irqsave(&queue->irqlock, flags); +@@ -244,6 +291,12 @@ void uvcg_queue_cancel(struct uvc_video_queue *queue, int disconnect) + queue); + list_del(&buf->queue); + buf->state = UVC_BUF_STATE_ERROR; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ sg_free_table(&buf->sgt); ++ } ++#endif + vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR); + } + /* This must be protected by the irqlock spinlock to avoid race +@@ -276,6 +329,11 @@ void uvcg_queue_cancel(struct uvc_video_queue *queue, int disconnect) + */ + int uvcg_queue_enable(struct uvc_video_queue *queue, int enable) + { ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_video *video = container_of(queue, struct uvc_video, queue); ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif + unsigned long flags; + int ret = 0; + +@@ -286,6 +344,12 @@ int uvcg_queue_enable(struct uvc_video_queue *queue, int enable) + + queue->sequence = 0; + queue->buf_used = 0; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ queue->cur_sg = NULL; ++ } ++#endif + } else { + ret = vb2_streamoff(&queue->queue, queue->queue.type); + if (ret < 0) +@@ -307,10 +371,47 @@ int uvcg_queue_enable(struct uvc_video_queue *queue, int enable) + return ret; + } + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++void uvcg_complete_sg(struct uvc_video_queue *queue) ++{ ++ struct uvc_buffer *buf = NULL; ++ ++ list_for_each_entry(buf, &queue->irqqueue, queue) ++ { ++ if (buf->state == UVC_BUF_STATE_DONE) ++ { ++ uvcg_queue_next_buffer(queue, buf); ++ return; ++ } ++ } ++} ++ ++struct uvc_buffer *uvcg_prepare_sg(struct uvc_video_queue *queue) ++{ ++ struct uvc_buffer *buf = NULL; ++ ++ list_for_each_entry(buf, &queue->irqqueue, queue) ++ { ++ if (buf->state != UVC_BUF_STATE_DONE) ++ { ++ return buf; ++ } ++ } ++ ++ queue->flags |= UVC_QUEUE_PAUSED; ++ return NULL; ++} ++#endif ++ + /* called with &queue_irqlock held.. */ + struct uvc_buffer *uvcg_queue_next_buffer(struct uvc_video_queue *queue, + struct uvc_buffer *buf) + { ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_video *video = container_of(queue, struct uvc_video, queue); ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif + struct uvc_buffer *nextbuf; + + if ((queue->flags & UVC_QUEUE_DROP_INCOMPLETE) && +@@ -332,6 +433,12 @@ struct uvc_buffer *uvcg_queue_next_buffer(struct uvc_video_queue *queue, + buf->buf.vb2_buf.timestamp = ktime_get_ns(); + + vb2_set_plane_payload(&buf->buf.vb2_buf, 0, buf->bytesused); ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ sg_free_table(&buf->sgt); ++ } ++#endif + vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE); + + return nextbuf; +diff --git a/drivers/usb/gadget/function/uvc_queue.h b/drivers/usb/gadget/function/uvc_queue.h +old mode 100644 +new mode 100755 +index ac461a9a1a70..15aa1f14f3aa +--- a/drivers/usb/gadget/function/uvc_queue.h ++++ b/drivers/usb/gadget/function/uvc_queue.h +@@ -12,6 +12,7 @@ + #define UVC_MAX_FRAME_SIZE (16*1024*1024) + /* Maximum number of video buffers. */ + #define UVC_MAX_VIDEO_BUFFERS 32 ++#define UVC_MAX_REQ_SG_LIST_NUM 12 + + /* ------------------------------------------------------------------------ + * Structures. +@@ -31,8 +32,14 @@ struct uvc_buffer { + + enum uvc_buffer_state state; + void *mem; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct sg_table sgt; ++#endif + unsigned int length; + unsigned int bytesused; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ bool bFrameEnd; ++#endif + }; + + #define UVC_QUEUE_DISCONNECTED (1 << 0) +@@ -46,7 +53,20 @@ struct uvc_video_queue { + __u32 sequence; + + unsigned int buf_used; +- ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct scatterlist *cur_sg; ++#endif ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ bool bFrameEnd; ++#endif ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ /* Use to inform host to drop the receiving frame(s) */ ++ __u8 bXferFlag; ++ #define FLAG_UVC_XFER_OK 0x00 ++ #define FLAG_UVC_XFER_ERR 0x01 // flag to indicate data loss in xfer ++ #define FLAG_UVC_EVENT_KEYFRAME 0x40 // flag to send forceIDR event ++ #define FLAG_UVC_WAIT_KEYFRAME 0x80 // flag to keep drop frames unitl I-frame queue ++#endif + spinlock_t irqlock; /* Protects flags and irqqueue */ + struct list_head irqqueue; + }; +@@ -90,6 +110,14 @@ struct uvc_buffer *uvcg_queue_next_buffer(struct uvc_video_queue *queue, + + struct uvc_buffer *uvcg_queue_head(struct uvc_video_queue *queue); + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ ++void uvcg_complete_sg(struct uvc_video_queue *queue); ++ ++struct uvc_buffer *uvcg_prepare_sg(struct uvc_video_queue *queue); ++ ++#endif ++ + #endif /* __KERNEL__ */ + + #endif /* _UVC_QUEUE_H_ */ +diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c +old mode 100644 +new mode 100755 +index f4ccbd56f4d2..5d2f72493913 +--- a/drivers/usb/gadget/function/uvc_v4l2.c ++++ b/drivers/usb/gadget/function/uvc_v4l2.c +@@ -23,6 +23,7 @@ + #include + + #include "f_uvc.h" ++#include "u_uvc.h" + #include "uvc.h" + #include "uvc_queue.h" + #include "uvc_video.h" +@@ -61,14 +62,22 @@ struct uvc_format + + static struct uvc_format uvc_formats[] = { + { 16, V4L2_PIX_FMT_YUYV }, ++ { 12, V4L2_PIX_FMT_NV12 }, + { 0, V4L2_PIX_FMT_MJPEG }, ++ { 0, V4L2_PIX_FMT_H264 }, ++ { 0, V4L2_PIX_FMT_H265 }, + }; + + static int + uvc_v4l2_querycap(struct file *file, void *fh, struct v4l2_capability *cap) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_device *uvc = stream->dev; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); ++#endif + struct usb_composite_dev *cdev = uvc->func.config->cdev; + + strlcpy(cap->driver, "g_uvc", sizeof(cap->driver)); +@@ -76,8 +85,6 @@ uvc_v4l2_querycap(struct file *file, void *fh, struct v4l2_capability *cap) + strlcpy(cap->bus_info, dev_name(&cdev->gadget->dev), + sizeof(cap->bus_info)); + +- cap->device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; +- cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; + + return 0; + } +@@ -86,8 +93,13 @@ static int + uvc_v4l2_get_format(struct file *file, void *fh, struct v4l2_format *fmt) + { + struct video_device *vdev = video_devdata(file); +- struct uvc_device *uvc = video_get_drvdata(vdev); +- struct uvc_video *video = &uvc->video; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_video *video = &stream->video; ++#else ++ struct uvc_device *uvc = video_get_drvdata(vdev); ++ struct uvc_video *video = &uvc->video; ++#endif + + fmt->fmt.pix.pixelformat = video->fcc; + fmt->fmt.pix.width = video->width; +@@ -105,8 +117,14 @@ static int + uvc_v4l2_set_format(struct file *file, void *fh, struct v4l2_format *fmt) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_device *uvc = stream->dev; ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#endif + struct uvc_format *format; + unsigned int imagesize; + unsigned int bpl; +@@ -119,8 +137,8 @@ uvc_v4l2_set_format(struct file *file, void *fh, struct v4l2_format *fmt) + } + + if (i == ARRAY_SIZE(uvc_formats)) { +- printk(KERN_INFO "Unsupported format 0x%08x.\n", +- fmt->fmt.pix.pixelformat); ++ uvcg_info(&uvc->func, "Unsupported format 0x%08x.\n", ++ fmt->fmt.pix.pixelformat); + return -EINVAL; + } + +@@ -146,8 +164,13 @@ static int + uvc_v4l2_reqbufs(struct file *file, void *fh, struct v4l2_requestbuffers *b) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#endif + + if (b->type != video->queue.queue.type) + return -EINVAL; +@@ -159,8 +182,14 @@ static int + uvc_v4l2_querybuf(struct file *file, void *fh, struct v4l2_buffer *b) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#endif + + return uvcg_query_buffer(&video->queue, b); + } +@@ -169,23 +198,45 @@ static int + uvc_v4l2_qbuf(struct file *file, void *fh, struct v4l2_buffer *b) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; +- int ret; ++#endif + ++ int ret; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ /* verify the FrameEnd flags */ ++ if (b->reserved == 1) ++ video->queue.bFrameEnd = false; ++ else ++ video->queue.bFrameEnd = true; ++ b->reserved = 0; ++#endif + ret = uvcg_queue_buffer(&video->queue, b); + if (ret < 0) + return ret; + +- return uvcg_video_pump(video); ++ schedule_work(&video->pump); ++ ++ return ret; + } + + static int + uvc_v4l2_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#endif + + return uvcg_dequeue_buffer(&video->queue, b, file->f_flags & O_NONBLOCK); + } +@@ -194,8 +245,18 @@ static int + uvc_v4l2_streamon(struct file *file, void *fh, enum v4l2_buf_type type) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_device *uvc = stream->dev; ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#endif ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(uvc->func.fi); ++#endif + int ret; + + if (type != video->queue.queue.type) +@@ -206,12 +267,27 @@ uvc_v4l2_streamon(struct file *file, void *fh, enum v4l2_buf_type type) + if (ret < 0) + return ret; + ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if (opts->bulk_streaming_ep) ++ #ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ stream->state = UVC_STATE_STREAMING; ++ #else ++ uvc->state = UVC_STATE_STREAMING; ++ #endif ++ else ++#endif ++ { + /* + * Complete the alternate setting selection setup phase now that + * userspace is ready to provide video frames. + */ +- uvc_function_setup_continue(uvc); +- uvc->state = UVC_STATE_STREAMING; ++ uvc_function_setup_continue(uvc); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ stream->state = UVC_STATE_STREAMING; ++#else ++ uvc->state = UVC_STATE_STREAMING; ++#endif ++ } + + return 0; + } +@@ -220,8 +296,14 @@ static int + uvc_v4l2_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ struct uvc_video *video = &stream->video; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#endif + + if (type != video->queue.queue.type) + return -EINVAL; +@@ -231,7 +313,7 @@ uvc_v4l2_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) + + static int + uvc_v4l2_subscribe_event(struct v4l2_fh *fh, +- const struct v4l2_event_subscription *sub) ++ const struct v4l2_event_subscription *sub) + { + if (sub->type < UVC_EVENT_FIRST || sub->type > UVC_EVENT_LAST) + return -EINVAL; +@@ -241,22 +323,26 @@ uvc_v4l2_subscribe_event(struct v4l2_fh *fh, + + static int + uvc_v4l2_unsubscribe_event(struct v4l2_fh *fh, +- const struct v4l2_event_subscription *sub) ++ const struct v4l2_event_subscription *sub) + { + return v4l2_event_unsubscribe(fh, sub); + } + + static long + uvc_v4l2_ioctl_default(struct file *file, void *fh, bool valid_prio, +- unsigned int cmd, void *arg) ++ unsigned int cmd, void *arg) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_device *uvc = stream->dev; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); ++#endif + + switch (cmd) { + case UVCIOC_SEND_RESPONSE: + return uvc_send_response(uvc, arg); +- + default: + return -ENOIOCTLCMD; + } +@@ -285,7 +371,12 @@ static int + uvc_v4l2_open(struct file *file) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_device *uvc = stream->dev; ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); ++#endif + struct uvc_file_handle *handle; + + handle = kzalloc(sizeof(*handle), GFP_KERNEL); +@@ -295,7 +386,12 @@ uvc_v4l2_open(struct file *file) + v4l2_fh_init(&handle->vfh, vdev); + v4l2_fh_add(&handle->vfh); + ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ handle->device = &stream->video; ++ stream->active = 1; ++#else + handle->device = &uvc->video; ++#endif + file->private_data = &handle->vfh; + + uvc_function_connect(uvc); +@@ -306,11 +402,19 @@ static int + uvc_v4l2_release(struct file *file) + { + struct video_device *vdev = video_devdata(file); +- struct uvc_device *uvc = video_get_drvdata(vdev); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ struct uvc_device *uvc = stream->dev; ++#else ++ struct uvc_device *uvc = video_get_drvdata(vdev); ++#endif + struct uvc_file_handle *handle = to_uvc_file_handle(file->private_data); + struct uvc_video *video = handle->device; + + uvc_function_disconnect(uvc); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ stream->active = 0; ++#endif + + mutex_lock(&video->mutex); + uvcg_video_enable(video, 0); +@@ -329,18 +433,32 @@ static int + uvc_v4l2_mmap(struct file *file, struct vm_area_struct *vma) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ ++ return uvcg_queue_mmap(&stream->video.queue, vma); ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + + return uvcg_queue_mmap(&uvc->video.queue, vma); ++#endif + } + + static unsigned int + uvc_v4l2_poll(struct file *file, poll_table *wait) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ ++ return uvcg_queue_poll(&stream->video.queue, file, wait); ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + + return uvcg_queue_poll(&uvc->video.queue, file, wait); ++#endif + } + + #ifndef CONFIG_MMU +@@ -349,9 +467,16 @@ static unsigned long uvcg_v4l2_get_unmapped_area(struct file *file, + unsigned long flags) + { + struct video_device *vdev = video_devdata(file); ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ struct uvc_streaming *stream = video_get_drvdata(vdev); ++ //struct uvc_device *uvc = stream->dev; ++ ++ return uvcg_queue_get_unmapped_area(&stream->video.queue, pgoff); ++#else + struct uvc_device *uvc = video_get_drvdata(vdev); + + return uvcg_queue_get_unmapped_area(&uvc->video.queue, pgoff); ++#endif + } + #endif + +diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c +old mode 100644 +new mode 100755 +index 0f01c04d7cbd..22f712d52fd8 +--- a/drivers/usb/gadget/function/uvc_video.c ++++ b/drivers/usb/gadget/function/uvc_video.c +@@ -18,26 +18,179 @@ + #include + + #include ++#include + + #include "uvc.h" + #include "uvc_queue.h" + #include "uvc_video.h" ++#include "u_uvc.h" ++ ++extern bool using_cma_buf; + + /* -------------------------------------------------------------------------- + * Video codecs + */ + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++static int ++uvc_video_encode_header_sgt(struct uvc_video *video, struct uvc_buffer *buf, ++ struct usb_request *req, int len) ++{ ++#define UVC_HEADER_LEN 12 ++ ++ char *data = req->buf; ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ struct uvc_video_queue *queue = &video->queue; ++#endif ++ ++ data[0] = UVC_HEADER_LEN; ++ data[1] = UVC_STREAM_EOH | video->fid; ++ data[2] = 0; ++ data[3] = 0; ++ data[4] = 0; ++ data[5] = 0; ++ data[6] = 0; ++ data[7] = 0; ++ data[8] = 0; ++ data[9] = 0; ++ data[10] = 0; ++ data[11] = 0; ++ ++ if ((buf->bytesused - video->queue.buf_used <= len - UVC_HEADER_LEN) && (buf->bFrameEnd)) { ++ data[1] |= UVC_STREAM_EOF; ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ if (queue->bXferFlag & FLAG_UVC_XFER_ERR) { ++ data[1] |= UVC_STREAM_ERR; // inform host to drop the outgoing frame ++ queue->bXferFlag = FLAG_UVC_XFER_OK; ++ if ((video->fcc == V4L2_PIX_FMT_H264) || (video->fcc == V4L2_PIX_FMT_H265)) { ++ // flag to send forceIDR event and wait key frame to xfer ++ queue->bXferFlag = FLAG_UVC_EVENT_KEYFRAME | FLAG_UVC_WAIT_KEYFRAME; ++ } ++ } ++ else if (queue->bXferFlag & FLAG_UVC_WAIT_KEYFRAME) { ++ if (buf->buf.flags & V4L2_BUF_FLAG_KEYFRAME) { ++ queue->bXferFlag = FLAG_UVC_XFER_OK; ++ } ++ else { ++ data[1] |= UVC_STREAM_ERR; // keep inform host to drop the outgoing frame until key frame ++ } ++ } ++#endif ++ } ++ ++ if (!video->queue.cur_sg) ++ { ++ video->queue.cur_sg = buf->sgt.sgl; ++ } ++ sg_init_table(req->sgt.sgl, req->sgt.nents); ++ return UVC_HEADER_LEN; ++} ++ ++static int ++uvc_video_encode_data_sgt(struct uvc_video *video, struct uvc_buffer *buf, ++ struct usb_request *req, int len) ++{ ++ struct uvc_video_queue *queue = &video->queue; ++ unsigned int nbytes; ++ void *mem; ++ ++ /* Copy video data to the USB buffer. */ ++ mem = buf->mem + queue->buf_used; ++ nbytes = min((unsigned int)len, buf->bytesused - queue->buf_used); ++ ++ sg_set_buf(req->sgt.sgl, req->buf, UVC_HEADER_LEN); ++ if (sg_copy(queue->cur_sg, sg_next(req->sgt.sgl), nbytes)) ++ { ++ BUG(); ++ } ++ req->sg = req->sgt.sgl; ++ req->num_sgs = sg_nents(req->sgt.sgl); ++ queue->cur_sg = sg_advance(queue->cur_sg, nbytes); ++ ++ queue->buf_used += nbytes; ++ ++ return nbytes; ++} ++ ++static void ++uvc_video_encode_isoc_sgt(struct usb_request *req, struct uvc_video *video, ++ struct uvc_buffer *buf) ++{ ++ int len = video->req_size; ++ int ret; ++ ++ /* Add the header. */ ++ ret = uvc_video_encode_header_sgt(video, buf, req, len); ++ len -= ret; ++ ++ /* Process video data. */ ++ ret = uvc_video_encode_data_sgt(video, buf, req, len); ++ len -= ret; ++ ++ req->length = video->req_size - len; ++ req->last_req = 0; ++ ++ if (buf->bytesused == video->queue.buf_used) { ++ req->last_req = 1; ++ video->queue.cur_sg = NULL; ++ video->queue.buf_used = 0; ++ buf->state = UVC_BUF_STATE_DONE; ++ ++ if (buf->bFrameEnd) ++ video->fid ^= UVC_STREAM_FID; ++ } ++} ++#endif ++ + static int + uvc_video_encode_header(struct uvc_video *video, struct uvc_buffer *buf, + u8 *data, int len) + { +- data[0] = 2; +- data[1] = UVC_STREAM_EOH | video->fid; ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ struct uvc_video_queue *queue = &video->queue; ++#endif + +- if (buf->bytesused - video->queue.buf_used <= len - 2) ++ data[0] = 12; ++ data[1] = UVC_STREAM_EOH | video->fid; ++ data[2] = 0; ++ data[3] = 0; ++ data[4] = 0; ++ data[5] = 0; ++ data[6] = 0; ++ data[7] = 0; ++ data[8] = 0; ++ data[9] = 0; ++ data[10] = 0; ++ data[11] = 0; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if ((buf->bytesused - video->queue.buf_used <= len - 12) && (buf->bFrameEnd)) ++#else ++ if (buf->bytesused - video->queue.buf_used <= len - 12) ++#endif ++ { + data[1] |= UVC_STREAM_EOF; ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ if (queue->bXferFlag & FLAG_UVC_XFER_ERR) { ++ data[1] |= UVC_STREAM_ERR; // inform host to drop the outgoing frame ++ queue->bXferFlag = FLAG_UVC_XFER_OK; ++ if ((video->fcc == V4L2_PIX_FMT_H264) || (video->fcc == V4L2_PIX_FMT_H265)) { ++ // flag to send forceIDR event and wait key frame to xfer ++ queue->bXferFlag = FLAG_UVC_EVENT_KEYFRAME | FLAG_UVC_WAIT_KEYFRAME; ++ } ++ } ++ else if (queue->bXferFlag & FLAG_UVC_WAIT_KEYFRAME) { ++ if (buf->buf.flags & V4L2_BUF_FLAG_KEYFRAME) { ++ queue->bXferFlag = FLAG_UVC_XFER_OK; ++ } ++ else { ++ data[1] |= UVC_STREAM_ERR; // keep inform host to drop the outgoing frame until key frame ++ } ++ } ++#endif ++ } + +- return 2; ++ return 12; + } + + static int +@@ -58,6 +211,7 @@ uvc_video_encode_data(struct uvc_video *video, struct uvc_buffer *buf, + return nbytes; + } + ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) + static void + uvc_video_encode_bulk(struct usb_request *req, struct uvc_video *video, + struct uvc_buffer *buf) +@@ -88,7 +242,8 @@ uvc_video_encode_bulk(struct usb_request *req, struct uvc_video *video, + video->queue.buf_used = 0; + buf->state = UVC_BUF_STATE_DONE; + uvcg_queue_next_buffer(&video->queue, buf); +- video->fid ^= UVC_STREAM_FID; ++ if (buf->bFrameEnd) ++ video->fid ^= UVC_STREAM_FID; + + video->payload_size = 0; + } +@@ -97,6 +252,7 @@ uvc_video_encode_bulk(struct usb_request *req, struct uvc_video *video, + buf->bytesused == video->queue.buf_used) + video->payload_size = 0; + } ++#endif + + static void + uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video, +@@ -121,13 +277,66 @@ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video, + video->queue.buf_used = 0; + buf->state = UVC_BUF_STATE_DONE; + uvcg_queue_next_buffer(&video->queue, buf); ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if (buf->bFrameEnd) ++ video->fid ^= UVC_STREAM_FID; ++#else + video->fid ^= UVC_STREAM_FID; ++#endif + } + } + + /* -------------------------------------------------------------------------- + * Request handling + */ ++static int uvcg_video_ep_queue(struct uvc_video *video, struct usb_request *req) ++{ ++ int ret = -ESHUTDOWN; ++ ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++#ifdef DEBUG_SG//test ++{ ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++ ++ if (gadget->sg_supported) ++ { ++ char *buf = kmalloc(req->length, GFP_KERNEL); ++ unsigned int copy_len = 0; ++ unsigned int correct = 1; ++ unsigned i; ++ ++ copy_len = sg_pcopy_to_buffer(req->sgt.sgl, req->sgt.nents, buf, req->length, 0); ++ ++ for (i=0; i < req->length;i++) ++ { ++ if (buf[i]!= ((char*)req->buf)[i]) ++ { ++ printk(KERN_DEBUG"index%d val%d val%d\n", i, buf[i], ((char*)req->buf)[i]); ++ correct = 0; ++ } ++ } ++ printk(KERN_DEBUG"data is header0x%x 0x%x\n", buf[0], buf[1]); ++ printk(KERN_DEBUG"data is (%s) reqlen%d copylen%d req->num_sgs%d\n", ++ correct?"right":"bad", req->length, copy_len, req->num_sgs); ++ kfree(buf); ++ } ++} ++#endif ++#endif ++ if (video->ep && video->ep->enabled) { ++ ret = usb_ep_queue(video->ep, req, GFP_ATOMIC); ++ if (ret < 0) { ++ uvcg_err(&video->uvc->func, "Failed to queue request (%d).\n", ret); ++ ++ /* Isochronous endpoints can't be halted. */ ++ if (video->ep->desc && usb_endpoint_xfer_bulk(video->ep->desc)) ++ usb_ep_set_halt(video->ep); ++ } ++ } ++ ++ return ret; ++} + + /* + * I somehow feel that synchronisation won't be easy to achieve here. We have +@@ -164,65 +373,77 @@ uvc_video_complete(struct usb_ep *ep, struct usb_request *req) + { + struct uvc_video *video = req->context; + struct uvc_video_queue *queue = &video->queue; +- struct uvc_buffer *buf; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif + unsigned long flags; +- int ret; + + switch (req->status) { + case 0: ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported && req->last_req == 1) ++ { ++ req->last_req = 0; ++ uvcg_complete_sg(queue); ++ } ++#endif + break; + + case -ESHUTDOWN: /* disconnect from host. */ +- printk(KERN_DEBUG "VS request cancelled.\n"); ++ uvcg_dbg(&video->uvc->func, "VS request cancelled.\n"); + uvcg_queue_cancel(queue, 1); +- goto requeue; +- +- default: +- printk(KERN_INFO "VS request completed with status %d.\n", +- req->status); +- uvcg_queue_cancel(queue, 0); +- goto requeue; +- } +- +- spin_lock_irqsave(&video->queue.irqlock, flags); +- buf = uvcg_queue_head(&video->queue); +- if (buf == NULL) { +- spin_unlock_irqrestore(&video->queue.irqlock, flags); +- goto requeue; +- } ++ break; + +- video->encode(req, video, buf); ++ case -ENOSR: /* uncompleted request */ ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ spin_lock_irqsave(&queue->irqlock, flags); ++ if (queue->bXferFlag == FLAG_UVC_XFER_OK) ++ queue->bXferFlag = FLAG_UVC_XFER_ERR; ++ spin_unlock_irqrestore(&queue->irqlock, flags); ++#endif ++ req->status = 0; ++ break; + +- if ((ret = usb_ep_queue(ep, req, GFP_ATOMIC)) < 0) { +- printk(KERN_INFO "Failed to queue request (%d).\n", ret); +- usb_ep_set_halt(ep); +- spin_unlock_irqrestore(&video->queue.irqlock, flags); ++ default: ++ uvcg_info(&video->uvc->func, ++ "VS request completed with status %d.\n", ++ req->status); + uvcg_queue_cancel(queue, 0); +- goto requeue; + } +- spin_unlock_irqrestore(&video->queue.irqlock, flags); +- +- return; + +-requeue: + spin_lock_irqsave(&video->req_lock, flags); + list_add_tail(&req->list, &video->req_free); + spin_unlock_irqrestore(&video->req_lock, flags); ++ ++ schedule_work(&video->pump); + } + + static int + uvc_video_free_requests(struct uvc_video *video) + { + unsigned int i; ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); + + for (i = 0; i < UVC_NUM_REQUESTS; ++i) { + if (video->req[i]) { ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ sg_free_table(&video->req[i]->sgt); ++ } ++#endif + usb_ep_free_request(video->ep, video->req[i]); + video->req[i] = NULL; + } + + if (video->req_buffer[i]) { +- kfree(video->req_buffer[i]); ++ if (!using_cma_buf) ++ kfree(video->req_buffer[i]); ++ else ++ dma_free_coherent(&gadget->dev, video->req_size, ++ video->req_buffer[i], video->req_buffer_dma_handle[i]); + video->req_buffer[i] = NULL; + } + } +@@ -237,18 +458,48 @@ uvc_video_alloc_requests(struct uvc_video *video) + { + unsigned int req_size; + unsigned int i; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(uvc->func.fi); ++#endif + int ret = -ENOMEM; + ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++ + BUG_ON(video->req_size); + +- req_size = video->ep->maxpacket +- * max_t(unsigned int, video->ep->maxburst, 1) +- * (video->ep->mult); ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if (opts->bulk_streaming_ep) ++ { ++ req_size = 50 * 1024; ++ video->max_payload_size = req_size; ++ } ++ else ++#endif ++ { ++ req_size = video->ep->maxpacket ++ * max_t(unsigned int, video->ep->maxburst, 1) ++ * (video->ep->mult); ++ } + + for (i = 0; i < UVC_NUM_REQUESTS; ++i) { +- video->req_buffer[i] = kmalloc(req_size, GFP_KERNEL); ++ if (!using_cma_buf) ++ video->req_buffer[i] = kmalloc(req_size, GFP_KERNEL); ++ else ++ { ++ static u64 dma_mask = 0xffffffffUL; ++ ++ gadget->dev.dma_mask = &dma_mask; ++ gadget->dev.coherent_dma_mask = dma_mask; ++ ++ video->req_buffer[i] = dma_alloc_coherent(&gadget->dev, ++ req_size, &video->req_buffer_dma_handle[i], GFP_KERNEL); ++ } + if (video->req_buffer[i] == NULL) ++ { ++ printk("alloc buffer err\n"); + goto error; ++ } + + video->req[i] = usb_ep_alloc_request(video->ep, GFP_KERNEL); + if (video->req[i] == NULL) +@@ -259,6 +510,18 @@ uvc_video_alloc_requests(struct uvc_video *video) + video->req[i]->complete = uvc_video_complete; + video->req[i]->context = video; + ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ ret = sg_alloc_table(&video->req[i]->sgt, ++ UVC_MAX_REQ_SG_LIST_NUM, ++ GFP_KERNEL); ++ if (ret) ++ { ++ goto error; ++ } ++ } ++#endif + list_add_tail(&video->req[i]->list, &video->req_free); + } + +@@ -281,11 +544,16 @@ error: + * This function fills the available USB requests (listed in req_free) with + * video data from the queued buffers. + */ +-int uvcg_video_pump(struct uvc_video *video) ++static void uvcg_video_pump(struct work_struct *work) + { ++ struct uvc_video *video = container_of(work, struct uvc_video, pump); + struct uvc_video_queue *queue = &video->queue; + struct usb_request *req; + struct uvc_buffer *buf; ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif + unsigned long flags; + int ret; + +@@ -300,7 +568,7 @@ int uvcg_video_pump(struct uvc_video *video) + spin_lock_irqsave(&video->req_lock, flags); + if (list_empty(&video->req_free)) { + spin_unlock_irqrestore(&video->req_lock, flags); +- return 0; ++ return; + } + req = list_first_entry(&video->req_free, struct usb_request, + list); +@@ -311,7 +579,28 @@ int uvcg_video_pump(struct uvc_video *video) + * request, protected by the video queue irqlock. + */ + spin_lock_irqsave(&queue->irqlock, flags); +- buf = uvcg_queue_head(queue); ++ ++#if defined(CONFIG_UVC_STREAM_ERR_SUPPORT) ++ // send event to force encoding a key frame ++ if (queue->bXferFlag & FLAG_UVC_EVENT_KEYFRAME) { ++ struct v4l2_event v4l2_event; ++ ++ queue->bXferFlag &= ~(FLAG_UVC_EVENT_KEYFRAME); ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_FORCEIDR; ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ v4l2_event_queue(&((video_to_stream(video))->vdev), &v4l2_event); ++#else ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); ++#endif ++ } ++#endif ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ buf = uvcg_prepare_sg(queue); ++ else ++#endif ++ buf = uvcg_queue_head(queue); + if (buf == NULL) { + spin_unlock_irqrestore(&queue->irqlock, flags); + break; +@@ -320,21 +609,19 @@ int uvcg_video_pump(struct uvc_video *video) + video->encode(req, video, buf); + + /* Queue the USB request */ +- ret = usb_ep_queue(video->ep, req, GFP_ATOMIC); ++ ret = uvcg_video_ep_queue(video, req); ++ spin_unlock_irqrestore(&queue->irqlock, flags); ++ + if (ret < 0) { +- printk(KERN_INFO "Failed to queue request (%d)\n", ret); +- usb_ep_set_halt(video->ep); +- spin_unlock_irqrestore(&queue->irqlock, flags); + uvcg_queue_cancel(queue, 0); + break; + } +- spin_unlock_irqrestore(&queue->irqlock, flags); + } + + spin_lock_irqsave(&video->req_lock, flags); + list_add_tail(&req->list, &video->req_free); + spin_unlock_irqrestore(&video->req_lock, flags); +- return 0; ++ return; + } + + /* +@@ -344,14 +631,24 @@ int uvcg_video_enable(struct uvc_video *video, int enable) + { + unsigned int i; + int ret; ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(uvc->func.fi); ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct usb_gadget * gadget = fuvc_to_gadget(uvc->func); ++#endif ++#endif + + if (video->ep == NULL) { +- printk(KERN_INFO "Video enable failed, device is " +- "uninitialized.\n"); ++ uvcg_info(&video->uvc->func, ++ "Video enable failed, device is uninitialized.\n"); + return -ENODEV; + } + + if (!enable) { ++ cancel_work_sync(&video->pump); ++ uvcg_queue_cancel(&video->queue, 0); ++ + for (i = 0; i < UVC_NUM_REQUESTS; ++i) + if (video->req[i]) + usb_ep_dequeue(video->ep, video->req[i]); +@@ -364,32 +661,60 @@ int uvcg_video_enable(struct uvc_video *video, int enable) + if ((ret = uvcg_queue_enable(&video->queue, 1)) < 0) + return ret; + +- if ((ret = uvc_video_alloc_requests(video)) < 0) +- return ret; +- +- if (video->max_payload_size) { ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if (opts->bulk_streaming_ep) ++ { + video->encode = uvc_video_encode_bulk; + video->payload_size = 0; + } else ++#endif ++ { + video->encode = uvc_video_encode_isoc; + +- return uvcg_video_pump(video); ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ if (gadget->sg_supported) ++ { ++ video->encode = uvc_video_encode_isoc_sgt; ++ } ++#endif ++ } ++ ++ if ((ret = uvc_video_alloc_requests(video)) < 0) ++ { ++ video->encode = NULL; ++ return ret; ++ } ++ ++ schedule_work(&video->pump); ++ ++ return ret; + } + + /* + * Initialize the UVC video stream. + */ +-int uvcg_video_init(struct uvc_video *video) ++int uvcg_video_init(struct uvc_video *video, struct uvc_device *uvcdev) + { ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ struct uvc_device *uvc = video_to_uvc(video); ++ struct f_uvc_opts *opts = fi_to_f_uvc_opts(uvc->func.fi); ++#endif ++ + INIT_LIST_HEAD(&video->req_free); + spin_lock_init(&video->req_lock); ++ INIT_WORK(&video->pump, uvcg_video_pump); + ++ video->uvc = uvcdev; + video->fcc = V4L2_PIX_FMT_YUYV; + video->bpp = 16; + video->width = 320; + video->height = 240; + video->imagesize = 320 * 240 * 2; + ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ if (opts->bulk_streaming_ep) ++ video->max_payload_size = video->imagesize; ++#endif + /* Initialize the video buffers queue. */ + uvcg_queue_init(&video->queue, V4L2_BUF_TYPE_VIDEO_OUTPUT, + &video->mutex); +diff --git a/drivers/usb/gadget/function/uvc_video.h b/drivers/usb/gadget/function/uvc_video.h +old mode 100644 +new mode 100755 +index ef00f06fa00b..eb2df5510cc6 +--- a/drivers/usb/gadget/function/uvc_video.h ++++ b/drivers/usb/gadget/function/uvc_video.h +@@ -15,10 +15,8 @@ + #ifndef __UVC_VIDEO_H__ + #define __UVC_VIDEO_H__ + +-int uvcg_video_pump(struct uvc_video *video); +- + int uvcg_video_enable(struct uvc_video *video, int enable); + +-int uvcg_video_init(struct uvc_video *video); ++int uvcg_video_init(struct uvc_video *video, struct uvc_device *uvc); + + #endif /* __UVC_VIDEO_H__ */ +diff --git a/drivers/usb/gadget/legacy/Kconfig b/drivers/usb/gadget/legacy/Kconfig +old mode 100644 +new mode 100755 +index 0b36878eb5fd..901d64662533 +--- a/drivers/usb/gadget/legacy/Kconfig ++++ b/drivers/usb/gadget/legacy/Kconfig +@@ -49,13 +49,22 @@ config USB_ZERO_HNPTEST + the "B-Peripheral" role, that device will use HNP to let this + one serve as the USB host instead (in the "B-Host" role). + ++config USB_BI_DIRECTION ++ tristate "USB BI DIRECTION For DLA" ++ select USB_LIBCOMPOSITE ++ select USB_F_BI_DIRECTION ++ help ++ Test Sample For Bi Direction ++ + config USB_AUDIO + tristate "Audio Gadget" + depends on SND + select USB_LIBCOMPOSITE + select SND_PCM +- select USB_F_UAC1 if GADGET_UAC1 ++ select USB_F_UAC1 if (GADGET_UAC1 && !GADGET_UAC1_LEGACY) ++ select USB_F_UAC1_LEGACY if (GADGET_UAC1 && GADGET_UAC1_LEGACY) + select USB_F_UAC2 if !GADGET_UAC1 ++ select USB_U_AUDIO if (USB_F_UAC2 || USB_F_UAC1) + help + This Gadget Audio driver is compatible with USB Audio Class + specification 2.0. It implements 1 AudioControl interface, +@@ -73,8 +82,15 @@ config USB_AUDIO + dynamically linked module called "g_audio". + + config GADGET_UAC1 +- bool "UAC 1.0 (Legacy)" ++ bool "UAC 1.0" + depends on USB_AUDIO ++ help ++ If you instead want older USB Audio Class specification 1.0 support ++ with similar driver capabilities. ++ ++config GADGET_UAC1_LEGACY ++ bool "UAC 1.0 (Legacy)" ++ depends on GADGET_UAC1 + help + If you instead want older UAC Spec-1.0 driver that also has audio + paths hardwired to the Audio codec chip on-board and doesn't work +@@ -139,22 +155,22 @@ config USB_ETH_RNDIS + is given in comments found in that info file. + + config USB_ETH_EEM +- bool "Ethernet Emulation Model (EEM) support" +- depends on USB_ETH ++ bool "Ethernet Emulation Model (EEM) support" ++ depends on USB_ETH + select USB_LIBCOMPOSITE + select USB_F_EEM +- default n +- help +- CDC EEM is a newer USB standard that is somewhat simpler than CDC ECM +- and therefore can be supported by more hardware. Technically ECM and +- EEM are designed for different applications. The ECM model extends +- the network interface to the target (e.g. a USB cable modem), and the +- EEM model is for mobile devices to communicate with hosts using +- ethernet over USB. For Linux gadgets, however, the interface with +- the host is the same (a usbX device), so the differences are minimal. +- +- If you say "y" here, the Ethernet gadget driver will use the EEM +- protocol rather than ECM. If unsure, say "n". ++ default n ++ help ++ CDC EEM is a newer USB standard that is somewhat simpler than CDC ECM ++ and therefore can be supported by more hardware. Technically ECM and ++ EEM are designed for different applications. The ECM model extends ++ the network interface to the target (e.g. a USB cable modem), and the ++ EEM model is for mobile devices to communicate with hosts using ++ ethernet over USB. For Linux gadgets, however, the interface with ++ the host is the same (a usbX device), so the differences are minimal. ++ ++ If you say "y" here, the Ethernet gadget driver will use the EEM ++ protocol rather than ECM. If unsure, say "n". + + config USB_G_NCM + tristate "Network Control Model (NCM) support" +@@ -470,10 +486,7 @@ endif + # or video class gadget drivers), or specific hardware, here. + config USB_G_WEBCAM + tristate "USB Webcam Gadget" +- depends on VIDEO_DEV + select USB_LIBCOMPOSITE +- select VIDEOBUF2_VMALLOC +- select USB_F_UVC + help + The Webcam Gadget acts as a composite USB Audio and Video Class + device. It provides a userspace API to process UVC control requests +@@ -481,3 +494,72 @@ config USB_G_WEBCAM + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_webcam". ++ ++config USB_WEBCAM_UVC ++ bool "Include configuration with UVC (Video)" ++ depends on USB_G_WEBCAM && VIDEO_DEV ++ select VIDEOBUF2_VMALLOC ++ select USB_F_UVC ++ default y ++ help ++ external uvc function for webcam ++ ++config MULTI_STREAM_FUNC_NUM ++ int "Multi Stream Under One Function" ++ depends on USB_WEBCAM_UVC ++ default 1 ++ help ++ external uvc function for webcam ++ ++config USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ bool "Support Sgtable for webcam uvc" ++ depends on USB_G_WEBCAM && VIDEO_DEV ++ depends on USB_WEBCAM_UVC ++ select VIDEOBUF2_DMA_SG ++ default 0 ++ help ++ Support Sgtable for webcam uvc ++ ++config UVC_STREAM_ERR_SUPPORT ++ bool "Set UVC_STREAM_ERR bit in header to indicate an error frame" ++ depends on USB_WEBCAM_UVC ++ default n ++ help ++ If udc controller reports NOSNR (Out of streams resources) error, it means ++ there are data lost during frame data transmission. ++ Indicate host that the sending frame might be corrupted and should be drop by ++ set UVC_STREAM_ERR bit in payload header. ++ ++config USB_WEBCAM_UAC ++ bool "Include configuration with UAC (Audio)" ++ depends on USB_G_WEBCAM && SND ++ select SND_PCM ++ select USB_F_UAC1 if !USB_WEBCAM_UAC1_LEGACY ++ select USB_F_UAC1_LEGACY if USB_WEBCAM_UAC1_LEGACY ++ select USB_U_AUDIO if !USB_WEBCAM_UAC1_LEGACY ++ help ++ external uac1 function for webcam ++ ++config USB_WEBCAM_UAC1_LEGACY ++ bool "UAC 1.0 (Legacy)" ++ depends on USB_WEBCAM_UAC ++ help ++ If you instead want older UAC Spec-1.0 driver that also has audio ++ paths hardwired to the Audio codec chip on-board and doesn't work ++ without one. ++ ++config USB_WEBCAM_RNDIS ++ bool "Include configuration with RNDIS" ++ depends on USB_G_WEBCAM && NET ++ select USB_U_ETHER ++ select USB_F_RNDIS ++ select CRC32 ++ help ++ external rndis function for webcam ++ ++config USB_WEBCAM_DFU ++ bool "Include configuration with (DFU)" ++ depends on USB_G_WEBCAM ++ select USB_F_DFU ++ help ++ external dfu function for webcam +diff --git a/drivers/usb/gadget/legacy/Makefile b/drivers/usb/gadget/legacy/Makefile +index 7f485f25705e..afaaab7a05a1 100644 +--- a/drivers/usb/gadget/legacy/Makefile ++++ b/drivers/usb/gadget/legacy/Makefile +@@ -8,6 +8,7 @@ ccflags-y += -I$(srctree)/drivers/usb/gadget/function/ + + g_zero-y := zero.o + g_audio-y := audio.o ++g_bi_direction-y := bi_direction.o + g_ether-y := ether.o + g_serial-y := serial.o + g_midi-y := gmidi.o +@@ -26,6 +27,7 @@ g_tcm_usb_gadget-y := tcm_usb_gadget.o + + obj-$(CONFIG_USB_ZERO) += g_zero.o + obj-$(CONFIG_USB_AUDIO) += g_audio.o ++obj-$(CONFIG_USB_BI_DIRECTION) += g_bi_direction.o + obj-$(CONFIG_USB_ETH) += g_ether.o + obj-$(CONFIG_USB_GADGETFS) += gadgetfs.o + obj-$(CONFIG_USB_FUNCTIONFS) += g_ffs.o +diff --git a/drivers/usb/gadget/legacy/audio.c b/drivers/usb/gadget/legacy/audio.c +old mode 100644 +new mode 100755 +index 5d7b3c6a422b..bd11b4886242 +--- a/drivers/usb/gadget/legacy/audio.c ++++ b/drivers/usb/gadget/legacy/audio.c +@@ -53,8 +53,40 @@ static int c_ssize = UAC2_DEF_CSSIZE; + module_param(c_ssize, uint, S_IRUGO); + MODULE_PARM_DESC(c_ssize, "Capture Sample Size(bytes)"); + #else ++#ifndef CONFIG_GADGET_UAC1_LEGACY + #include "u_uac1.h" + ++/* Playback(USB-IN) Default Stereo - Fl/Fr */ ++static int p_chmask = UAC1_DEF_PCHMASK; ++module_param(p_chmask, uint, S_IRUGO); ++MODULE_PARM_DESC(p_chmask, "Playback Channel Mask"); ++ ++/* Playback Default 48 KHz */ ++static int p_srate = UAC1_DEF_PSRATE; ++module_param(p_srate, uint, S_IRUGO); ++MODULE_PARM_DESC(p_srate, "Playback Sampling Rate"); ++ ++/* Playback Default 16bits/sample */ ++static int p_ssize = UAC1_DEF_PSSIZE; ++module_param(p_ssize, uint, S_IRUGO); ++MODULE_PARM_DESC(p_ssize, "Playback Sample Size(bytes)"); ++ ++/* Capture(USB-OUT) Default Stereo - Fl/Fr */ ++static int c_chmask = UAC1_DEF_CCHMASK; ++module_param(c_chmask, uint, S_IRUGO); ++MODULE_PARM_DESC(c_chmask, "Capture Channel Mask"); ++ ++/* Capture Default 48 KHz */ ++static int c_srate = UAC1_DEF_CSRATE; ++module_param(c_srate, uint, S_IRUGO); ++MODULE_PARM_DESC(c_srate, "Capture Sampling Rate"); ++ ++/* Capture Default 16bits/sample */ ++static int c_ssize = UAC1_DEF_CSSIZE; ++module_param(c_ssize, uint, S_IRUGO); ++MODULE_PARM_DESC(c_ssize, "Capture Sample Size(bytes)"); ++#else /* CONFIG_GADGET_UAC1_LEGACY */ ++#include "u_uac1_legacy.h" + static char *fn_play = FILE_PCM_PLAYBACK; + module_param(fn_play, charp, S_IRUGO); + MODULE_PARM_DESC(fn_play, "Playback PCM device file name"); +@@ -67,17 +99,53 @@ static char *fn_cntl = FILE_CONTROL; + module_param(fn_cntl, charp, S_IRUGO); + MODULE_PARM_DESC(fn_cntl, "Control device file name"); + +-static int req_buf_size = UAC1_OUT_EP_MAX_PACKET_SIZE; +-module_param(req_buf_size, int, S_IRUGO); +-MODULE_PARM_DESC(req_buf_size, "ISO OUT endpoint request buffer size"); ++static int playback_channel_count = UAC1_PLAYBACK_CHANNEL_COUNT; ++module_param(playback_channel_count, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(playback_channel_count, "Speaker Channel Counts"); ++ ++static int capture_channel_count = UAC1_CAPTURE_CHANNEL_COUNT; ++module_param(capture_channel_count, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(capture_channel_count, "Microphone Channel Counts"); ++ ++static int playback_sample_rate = UAC1_PLAYBACK_SAMPLE_RATE; ++module_param(playback_sample_rate, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(playback_sample_rate, "Speaker Sample Rate"); ++ ++static int capture_sample_rate = UAC1_CAPTURE_SAMPLE_RATE; ++module_param(capture_sample_rate, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(capture_sample_rate, "Microphone Sample Rate"); ++ ++static int out_req_buf_size = UAC1_OUT_EP_MAX_PACKET_SIZE; ++module_param(out_req_buf_size, int, S_IRUGO); ++MODULE_PARM_DESC(out_req_buf_size, "ISO OUT endpoint request buffer size"); ++ ++static int out_req_count = UAC1_OUT_REQ_COUNT; ++module_param(out_req_count, int, S_IRUGO); ++MODULE_PARM_DESC(out_req_count, "ISO OUT endpoint request count"); ++ ++static int audio_playback_buf_size = UAC1_AUDIO_PLAYBACK_BUF_SIZE; ++module_param(audio_playback_buf_size, int, S_IRUGO); ++MODULE_PARM_DESC(audio_playback_buf_size, "Audio playback buffer size"); ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++static int in_req_buf_size = UAC1_IN_EP_MAX_PACKET_SIZE; ++module_param(in_req_buf_size, int, S_IRUGO); ++MODULE_PARM_DESC(in_req_buf_size, "ISO IN endpoint request buffer size"); ++ ++static int in_req_count = UAC1_IN_REQ_COUNT; ++module_param(in_req_count, int, S_IRUGO); ++MODULE_PARM_DESC(in_req_count, "ISO IN endpoint request count"); + +-static int req_count = UAC1_REQ_COUNT; +-module_param(req_count, int, S_IRUGO); +-MODULE_PARM_DESC(req_count, "ISO OUT endpoint request count"); ++static int audio_capture_buf_size = UAC1_AUDIO_CAPTURE_BUF_SIZE; ++module_param(audio_capture_buf_size, int, S_IRUGO); ++MODULE_PARM_DESC(audio_capture_buf_size, "Audio capture buffer size"); + +-static int audio_buf_size = UAC1_AUDIO_BUF_SIZE; +-module_param(audio_buf_size, int, S_IRUGO); +-MODULE_PARM_DESC(audio_buf_size, "Audio buffer size"); ++static int audio_play_mode = 3; ++module_param(audio_play_mode, int, S_IRUGO); ++MODULE_PARM_DESC(audio_play_mode, "Audio Play Mode, 0: Disable UAC Function, " ++ "1: Speaker Only, 2: Microphone Only, 3: Speaker & Microphone"); ++#endif ++#endif + #endif + + /* string IDs are assigned dynamically */ +@@ -125,7 +193,7 @@ static struct usb_device_descriptor device_desc = { + + /* .bcdUSB = DYNAMIC */ + +-#ifdef CONFIG_GADGET_UAC1 ++#ifdef CONFIG_GADGET_UAC1_LEGACY + .bDeviceClass = USB_CLASS_PER_INTERFACE, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, +@@ -207,7 +275,11 @@ static int audio_bind(struct usb_composite_dev *cdev) + #ifndef CONFIG_GADGET_UAC1 + struct f_uac2_opts *uac2_opts; + #else ++#ifndef CONFIG_GADGET_UAC1_LEGACY + struct f_uac1_opts *uac1_opts; ++#else ++ struct f_uac1_legacy_opts *uac1_opts; ++#endif + #endif + int status; + +@@ -216,7 +288,11 @@ static int audio_bind(struct usb_composite_dev *cdev) + if (IS_ERR(fi_uac2)) + return PTR_ERR(fi_uac2); + #else ++#ifndef CONFIG_GADGET_UAC1_LEGACY + fi_uac1 = usb_get_function_instance("uac1"); ++#else ++ fi_uac1 = usb_get_function_instance("uac1_legacy"); ++#endif + if (IS_ERR(fi_uac1)) + return PTR_ERR(fi_uac1); + #endif +@@ -229,14 +305,37 @@ static int audio_bind(struct usb_composite_dev *cdev) + uac2_opts->c_chmask = c_chmask; + uac2_opts->c_srate = c_srate; + uac2_opts->c_ssize = c_ssize; ++ uac2_opts->req_number = UAC2_DEF_REQ_NUM; + #else ++#ifndef CONFIG_GADGET_UAC1_LEGACY + uac1_opts = container_of(fi_uac1, struct f_uac1_opts, func_inst); ++ uac1_opts->p_chmask = p_chmask; ++ uac1_opts->p_srate = p_srate; ++ uac1_opts->p_ssize = p_ssize; ++ uac1_opts->c_chmask = c_chmask; ++ uac1_opts->c_srate = c_srate; ++ uac1_opts->c_ssize = c_ssize; ++ uac1_opts->req_number = UAC1_DEF_REQ_NUM; ++#else /* CONFIG_GADGET_UAC1_LEGACY */ ++ uac1_opts = container_of(fi_uac1, struct f_uac1_legacy_opts, func_inst); + uac1_opts->fn_play = fn_play; + uac1_opts->fn_cap = fn_cap; + uac1_opts->fn_cntl = fn_cntl; +- uac1_opts->req_buf_size = req_buf_size; +- uac1_opts->req_count = req_count; +- uac1_opts->audio_buf_size = audio_buf_size; ++ uac1_opts->playback_channel_count = playback_channel_count; ++ uac1_opts->playback_sample_rate = playback_sample_rate; ++ uac1_opts->capture_channel_count = capture_channel_count; ++ uac1_opts->capture_sample_rate = capture_sample_rate; ++ uac1_opts->out_req_buf_size = out_req_buf_size; ++ uac1_opts->out_req_count = out_req_count; ++ uac1_opts->audio_playback_buf_size = audio_playback_buf_size; ++ ++#if defined(CONFIG_SS_GADGET) ||defined(CONFIG_SS_GADGET_MODULE) ++ uac1_opts->in_req_buf_size = in_req_buf_size; ++ uac1_opts->in_req_count = in_req_count; ++ uac1_opts->audio_capture_buf_size = audio_capture_buf_size; ++ uac1_opts->audio_play_mode = audio_play_mode; ++#endif ++#endif + #endif + + status = usb_string_ids_tab(cdev, strings_dev); +diff --git a/drivers/usb/gadget/legacy/bi_direction.c b/drivers/usb/gadget/legacy/bi_direction.c +new file mode 100644 +index 000000000000..29232f637764 +--- /dev/null ++++ b/drivers/usb/gadget/legacy/bi_direction.c +@@ -0,0 +1,285 @@ ++/* ++ * bi_direction.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "u_bi_direction.h" ++/*-------------------------------------------------------------------------*/ ++USB_GADGET_COMPOSITE_OPTIONS(); ++ ++#define DRIVER_VERSION "Sep 9 2018" ++ ++static const char longname[] = "MDD Bi"; ++ ++static struct usb_bi_direction_options gbi_direction_options = { ++ .bulk_in_buflen = GBI_DIRECTION_BULK_IN_BUFLEN, ++ .bulk_out_buflen = GBI_DIRECTION_BULK_OUT_BUFLEN, ++ .bulk_in_qlen = GBI_DIRECTION_BULK_IN_QLEN, ++ .bulk_out_qlen = GBI_DIRECTION_BULK_OUT_QLEN, ++}; ++ ++#ifndef CONFIG_USB_BI_DIRECTION_HNPTEST ++#define DRIVER_VENDOR_NUM 0x0525 ++#define DRIVER_PRODUCT_NUM 0xa4a0 ++#define DEFAULT_AUTORESUME 0 ++#else ++#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ ++#define DRIVER_PRODUCT_NUM 0xbadd ++#define DEFAULT_AUTORESUME 5 ++#endif ++ ++/* If the optional "autoresume" mode is enabled, it provides good ++ * functional coverage for the "USBCV" test harness from USB-IF. ++ * It's always set if OTG mode is enabled. ++ */ ++static unsigned autoresume = DEFAULT_AUTORESUME; ++module_param(autoresume, uint, S_IRUGO); ++MODULE_PARM_DESC(autoresume, "bi_direction, or seconds before remote wakeup"); ++ ++/* Maximum Autoresume time */ ++static unsigned max_autoresume; ++module_param(max_autoresume, uint, S_IRUGO); ++MODULE_PARM_DESC(max_autoresume, "maximum seconds before remote wakeup"); ++ ++/* Interval between two remote wakeups */ ++static unsigned autoresume_interval_ms; ++module_param(autoresume_interval_ms, uint, S_IRUGO); ++MODULE_PARM_DESC(autoresume_interval_ms, ++ "milliseconds to increase successive wakeup delays"); ++ ++static unsigned autoresume_step_ms; ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_device_descriptor device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ ++ .bcdUSB = cpu_to_le16(0x0200), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ ++ .idVendor = cpu_to_le16(DRIVER_VENDOR_NUM), ++ .idProduct = cpu_to_le16(DRIVER_PRODUCT_NUM), ++ .bNumConfigurations = 1, ++}; ++ ++#ifdef CONFIG_USB_OTG ++static struct usb_otg_descriptor otg_descriptor = { ++ .bLength = sizeof otg_descriptor, ++ .bDescriptorType = USB_DT_OTG, ++ ++ /* REVISIT SRP-only hardware is possible, although ++ * it would not be called "OTG" ... ++ */ ++ .bmAttributes = USB_OTG_SRP | USB_OTG_HNP, ++}; ++ ++static const struct usb_descriptor_header *otg_desc[] = { ++ (struct usb_descriptor_header *) &otg_descriptor, ++ NULL, ++}; ++#else ++#define otg_desc NULL ++#endif ++ ++/* string IDs are assigned dynamically */ ++/* default serial number takes at least two packets */ ++static char serial[] = "03e72160"; ++ ++#define USB_GBI_DIRECTION_NN_DESC (USB_GADGET_FIRST_AVAIL_IDX + 0) ++ ++static struct usb_string strings_dev[] = { ++ [USB_GADGET_MANUFACTURER_IDX].s = "Sigmastar Ltd", ++ [USB_GADGET_PRODUCT_IDX].s = longname, ++ [USB_GADGET_SERIAL_IDX].s = serial, ++ [USB_GBI_DIRECTION_NN_DESC].s = "Bi Net Dev", ++ { } /* end of list */ ++}; ++ ++static struct usb_gadget_strings stringtab_dev = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings_dev, ++}; ++ ++static struct usb_gadget_strings *dev_strings[] = { ++ &stringtab_dev, ++ NULL, ++}; ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct timer_list autoresume_timer; ++ ++static void bi_direction_autoresume(unsigned long _c) ++{ ++ struct usb_composite_dev *cdev = (void *)_c; ++ struct usb_gadget *g = cdev->gadget; ++ ++ if (!cdev->config) ++ return; ++ ++ if (g->speed != USB_SPEED_UNKNOWN) { ++ int status = usb_gadget_wakeup(g); ++ INFO(cdev, "%s --> %d\n", __func__, status); ++ } ++} ++ ++static void bi_direction_suspend(struct usb_composite_dev *cdev) ++{ ++ if (cdev->gadget->speed == USB_SPEED_UNKNOWN) ++ return; ++ ++ if (autoresume) { ++ if (max_autoresume && ++ (autoresume_step_ms > max_autoresume * 1000)) ++ autoresume_step_ms = autoresume * 1000; ++ ++ mod_timer(&autoresume_timer, jiffies + ++ msecs_to_jiffies(autoresume_step_ms)); ++ DBG(cdev, "suspend, wakeup in %d milliseconds\n", ++ autoresume_step_ms); ++ ++ autoresume_step_ms += autoresume_interval_ms; ++ } else ++ DBG(cdev, "%s\n", __func__); ++} ++ ++static void bi_direction_resume(struct usb_composite_dev *cdev) ++{ ++ DBG(cdev, "%s\n", __func__); ++ del_timer(&autoresume_timer); ++} ++ ++/*-------------------------------------------------------------------------*/ ++module_param_named(bulk_in_buflen, gbi_direction_options.bulk_in_buflen, uint, 0); ++module_param_named(bulk_out_buflen, gbi_direction_options.bulk_out_buflen, uint, 0); ++ ++static struct usb_function *func_bd; ++static struct usb_function_instance *func_inst_bd; ++ ++module_param_named(bulk_in_qlen, gbi_direction_options.bulk_in_qlen, uint, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(bulk_in_qlen, "depth of bi bulk in queue"); ++ ++module_param_named(bulk_out_qlen, gbi_direction_options.bulk_out_qlen, uint, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(bulk_out_qlen, "depth of bi bulk out queue"); ++ ++static int bd_config_setup(struct usb_configuration *c, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ switch (ctrl->bRequest) { ++ case 0x5b: ++ case 0x5c: ++ return func_bd->setup(func_bd, ctrl); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static struct usb_configuration bi_driver = { ++ .label = "bi", ++ .setup = bd_config_setup,//todo ++ .bConfigurationValue = 1, ++ .bmAttributes = USB_CONFIG_ATT_SELFPOWER, ++ /* .iConfiguration = DYNAMIC */ ++}; ++ ++static int __init bi_direction_bind(struct usb_composite_dev *cdev) ++{ ++ struct f_bd_opts *bd_opts; ++ int status; ++ ++ status = usb_string_ids_tab(cdev, strings_dev); ++ if (status < 0) ++ return status; ++ ++ device_desc.iManufacturer = strings_dev[USB_GADGET_MANUFACTURER_IDX].id; ++ device_desc.iProduct = strings_dev[USB_GADGET_PRODUCT_IDX].id; ++ device_desc.iSerialNumber = strings_dev[USB_GADGET_SERIAL_IDX].id; ++ ++ setup_timer(&autoresume_timer, bi_direction_autoresume, (unsigned long) cdev); ++ ++ func_inst_bd = usb_get_function_instance("Bi"); ++ if (IS_ERR(func_inst_bd)) { ++ status = PTR_ERR(func_inst_bd); ++ return status; ++ } ++ ++ bd_opts = container_of(func_inst_bd, struct f_bd_opts, func_inst); ++ bd_opts->bulk_in_buflen = gbi_direction_options.bulk_in_buflen; ++ bd_opts->bulk_in_qlen = gbi_direction_options.bulk_in_qlen; ++ bd_opts->bulk_out_buflen = gbi_direction_options.bulk_out_buflen; ++ bd_opts->bulk_out_qlen = gbi_direction_options.bulk_out_qlen; ++ ++ func_bd = usb_get_function(func_inst_bd); ++ if (IS_ERR(func_bd)) { ++ status = PTR_ERR(func_bd); ++ goto err_put_func_inst_bd; ++ } ++ ++ bi_driver.iConfiguration = strings_dev[USB_GBI_DIRECTION_NN_DESC].id; ++ ++ /* support autoresume for remote wakeup testing */ ++ bi_driver.bmAttributes &= ~USB_CONFIG_ATT_WAKEUP; ++ bi_driver.descriptors = NULL; ++ if (autoresume) { ++ bi_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP; ++ autoresume_step_ms = autoresume * 1000; ++ } ++ ++ /* support OTG systems */ ++ if (gadget_is_otg(cdev->gadget)) { ++ bi_driver.descriptors = otg_desc; ++ bi_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP; ++ } ++ ++ usb_add_config_only(cdev, &bi_driver); ++ ++ status = usb_add_function(&bi_driver, func_bd); ++ if (status) ++ goto err_conf_fbd; ++ ++ usb_ep_autoconfig_reset(cdev->gadget); ++ usb_composite_overwrite_options(cdev, &coverwrite); ++ ++ INFO(cdev, "%s, version: " DRIVER_VERSION "\n", longname); ++ ++ return 0; ++ ++err_conf_fbd: ++ usb_put_function(func_bd); ++ func_bd = NULL; ++err_put_func_inst_bd: ++ usb_put_function_instance(func_inst_bd); ++ func_inst_bd = NULL; ++ return status; ++} ++ ++static int bi_direction_unbind(struct usb_composite_dev *cdev) ++{ ++ del_timer_sync(&autoresume_timer); ++ if (!IS_ERR_OR_NULL(func_bd)) ++ usb_put_function(func_bd); ++ usb_put_function_instance(func_inst_bd); ++ return 0; ++} ++ ++static __refdata struct usb_composite_driver bi_direction_driver = { ++ .name = "bi_direction", ++ .dev = &device_desc, ++ .strings = dev_strings, ++ .max_speed = USB_SPEED_SUPER, ++ .bind = bi_direction_bind, ++ .unbind = bi_direction_unbind, ++ .suspend = bi_direction_suspend, ++ .resume = bi_direction_resume, ++}; ++ ++module_usb_composite_driver(bi_direction_driver); ++ ++MODULE_AUTHOR("Claude Rao"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/usb/gadget/legacy/g_ffs.c b/drivers/usb/gadget/legacy/g_ffs.c +index 6da7316f8e87..4544b249d1a6 100644 +--- a/drivers/usb/gadget/legacy/g_ffs.c ++++ b/drivers/usb/gadget/legacy/g_ffs.c +@@ -77,7 +77,7 @@ static struct usb_device_descriptor gfs_dev_desc = { + }; + + static char *func_names[GFS_MAX_DEVS]; +-static unsigned int func_num; ++static unsigned int func_num = 2; + + module_param_named(bDeviceClass, gfs_dev_desc.bDeviceClass, byte, 0644); + MODULE_PARM_DESC(bDeviceClass, "USB Device class"); +diff --git a/drivers/usb/gadget/legacy/uvc_ait_xu.h b/drivers/usb/gadget/legacy/uvc_ait_xu.h +new file mode 100755 +index 000000000000..00c84c75d6fb +--- /dev/null ++++ b/drivers/usb/gadget/legacy/uvc_ait_xu.h +@@ -0,0 +1,33 @@ ++#ifndef _UVC_AIT_XU_H_ ++#define _UVC_AIT_XU_H_ ++ ++#include ++#include "u_uvc.h" ++ ++/*************************************************************/ ++/* */ ++/* MACROS */ ++/* */ ++/*************************************************************/ ++/* ---------------------- ++* AIT XU descriptor GUID. ++*/ ++#define USE_AIT_XU ++ ++#define UUID_LE_AIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ ++{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ ++ (b) & 0xff, ((b) >> 8) & 0xff, \ ++ (c) & 0xff, ((c) >> 8) & 0xff, \ ++ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } ++ ++#define UUID_BE_AIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ ++{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ ++ ((b) >> 8) & 0xff, (b) & 0xff, \ ++ ((c) >> 8) & 0xff, (c) & 0xff, \ ++ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } ++ ++ ++#define UVC_AIT_EU1_GUID UUID_LE_AIT(0x23E49ED0, 0x1178, 0x4f31, 0xAE, 0x52, 0xD2, 0xFB, 0x8A, 0x8D, 0x3B, 0x48) ++#define UVC_CUS_EU2_GUID UUID_LE_AIT(0x2C49D16A, 0x32B8, 0x4485, 0x3E, 0xA8, 0x64, 0x3A, 0x15, 0x23, 0x62, 0xF2) ++ ++#endif//_UVC_AIT_XU_H_ +diff --git a/drivers/usb/gadget/legacy/webcam.c b/drivers/usb/gadget/legacy/webcam.c +old mode 100644 +new mode 100755 +index f9661cd627c8..4f4f5ee2f7b2 +--- a/drivers/usb/gadget/legacy/webcam.c ++++ b/drivers/usb/gadget/legacy/webcam.c +@@ -2,7 +2,7 @@ + * webcam.c -- USB webcam gadget driver + * + * Copyright (C) 2009-2010 +- * Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -14,33 +14,209 @@ + #include + #include + #include +- +-#include "u_uvc.h" ++#include + + USB_GADGET_COMPOSITE_OPTIONS(); +- + /*-------------------------------------------------------------------------*/ + ++#if defined(CONFIG_USB_WEBCAM_UVC) ++#include "u_uvc.h" ++#include "uvc_ait_xu.h" ++ + /* module parameters specific to the Video streaming endpoint */ +-static unsigned int streaming_interval = 1; +-module_param(streaming_interval, uint, S_IRUGO|S_IWUSR); ++static unsigned int nr_name; ++static char *streaming_name[MAX_STREAM_SUPPORT] = ++ {DEFAULT_STREAM_NAME, DEFAULT_STREAM_NAME, DEFAULT_STREAM_NAME, DEFAULT_STREAM_NAME}; ++module_param_array(streaming_name, charp, &nr_name, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(streaming_name, "Uvc Stream Name"); ++ ++static unsigned int nr_interval; ++static unsigned int streaming_interval[MAX_STREAM_SUPPORT] = {1, 1, 1, 1}; ++module_param_array(streaming_interval, uint, &nr_interval, S_IRUGO|S_IWUSR); + MODULE_PARM_DESC(streaming_interval, "1 - 16"); + +-static unsigned int streaming_maxpacket = 1024; +-module_param(streaming_maxpacket, uint, S_IRUGO|S_IWUSR); +-MODULE_PARM_DESC(streaming_maxpacket, "1 - 1023 (FS), 1 - 3072 (hs/ss)"); ++static unsigned int nr_maxpacket; ++static unsigned int streaming_maxpacket[MAX_STREAM_SUPPORT] = {1024 * 3, 1024 * 3, 30192, 30064}; ++module_param_array(streaming_maxpacket, uint, &nr_maxpacket, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(streaming_maxpacket, "ISOC: 1 - 1023 (FS), 1 - 3072 (hs/ss) / " ++ "BULK: 1 - 64 (FS), 1 - 512 (HS), 1 - 1024 (SS)"); + +-static unsigned int streaming_maxburst; +-module_param(streaming_maxburst, uint, S_IRUGO|S_IWUSR); ++static unsigned int nr_maxburst; ++static unsigned int streaming_maxburst[MAX_STREAM_SUPPORT] = {0, 0, 0, 0}; ++module_param_array(streaming_maxburst, uint, &nr_maxburst, S_IRUGO|S_IWUSR); + MODULE_PARM_DESC(streaming_maxburst, "0 - 15 (ss only)"); + ++static bool bulk_streaming_ep = 0; ++module_param(bulk_streaming_ep, bool, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(bulk_streaming_ep, "0 (Use ISOC video streaming ep) / " ++ "1 (Use BULK video streaming ep)"); ++ ++static int uvc_function_enable = 1; ++module_param(uvc_function_enable, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(uvc_function_enable, "UVC Function Enable," ++ "0: Disable UVC, 1: Enable UVC"); + static unsigned int trace; + module_param(trace, uint, S_IRUGO|S_IWUSR); + MODULE_PARM_DESC(trace, "Trace level bitmask"); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UAC) ++#ifndef CONFIG_USB_WEBCAM_UAC1_LEGACY ++#include "u_uac1.h" ++ ++/* Playback(USB-IN) Endpoint Size */ ++static int p_mpsize = UAC1_OUT_EP_MAX_PACKET_SIZE; ++module_param(p_mpsize, uint, S_IRUGO); ++MODULE_PARM_DESC(p_mpsize, "Playback Endpoint Max Packet Size"); ++ ++/* Playback(USB-IN) Default Stereo - Fl/Fr */ ++static int p_chmask = UAC1_DEF_PCHMASK; ++module_param(p_chmask, uint, S_IRUGO); ++MODULE_PARM_DESC(p_chmask, "Playback Channel Mask"); ++ ++/* Playback Default 48 KHz */ ++static int p_srate = UAC1_DEF_PSRATE; ++module_param(p_srate, uint, S_IRUGO); ++MODULE_PARM_DESC(p_srate, "Playback Sampling Rate"); ++ ++/* Playback Default 16bits/sample */ ++static int p_ssize = UAC1_DEF_PSSIZE; ++module_param(p_ssize, uint, S_IRUGO); ++MODULE_PARM_DESC(p_ssize, "Playback Sample Size(bytes)"); ++ ++/* Capture(USB-OUT) Endpoint Size */ ++static int c_mpsize = UAC1_OUT_EP_MAX_PACKET_SIZE; ++module_param(c_mpsize, uint, S_IRUGO); ++MODULE_PARM_DESC(c_mpsize, "Capture Endpoint Max Packet Size"); ++ ++/* Capture(USB-OUT) Default Stereo - Fl/Fr */ ++static int c_chmask = UAC1_DEF_CCHMASK; ++module_param(c_chmask, uint, S_IRUGO); ++MODULE_PARM_DESC(c_chmask, "Capture Channel Mask"); ++ ++/* Capture Default 48 KHz */ ++static int c_srate = UAC1_DEF_CSRATE; ++module_param(c_srate, uint, S_IRUGO); ++MODULE_PARM_DESC(c_srate, "Capture Sampling Rate"); ++ ++/* Capture Default 16bits/sample */ ++static int c_ssize = UAC1_DEF_CSSIZE; ++module_param(c_ssize, uint, S_IRUGO); ++MODULE_PARM_DESC(c_ssize, "Capture Sample Size(bytes)"); ++ ++static int uac_function_enable = 0; ++module_param(uac_function_enable, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(uac_function_enable, "Audio Play Mode, 0: Disable UAC Function, " ++ "1: Speaker Only, 2: Microphone Only, 3: Speaker & Microphone"); ++#else /* CONFIG_USB_WEBCAM_UAC1_LEGACY */ ++#include "u_uac1_legacy.h" ++ ++static char *fn_play = FILE_PCM_PLAYBACK; ++module_param(fn_play, charp, S_IRUGO); ++MODULE_PARM_DESC(fn_play, "Playback PCM device file name"); ++ ++static char *fn_cap = FILE_PCM_CAPTURE; ++module_param(fn_cap, charp, S_IRUGO); ++MODULE_PARM_DESC(fn_cap, "Capture PCM device file name"); ++ ++static char *fn_cntl = FILE_CONTROL; ++module_param(fn_cntl, charp, S_IRUGO); ++MODULE_PARM_DESC(fn_cntl, "Control device file name"); ++ ++static int playback_channel_count = UAC1_PLAYBACK_CHANNEL_COUNT; ++module_param(playback_channel_count, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(playback_channel_count, "Speaker Channel Counts"); ++ ++static int capture_channel_count = UAC1_CAPTURE_CHANNEL_COUNT; ++module_param(capture_channel_count, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(capture_channel_count, "Microphone Channel Counts"); ++ ++static int playback_sample_rate = UAC1_PLAYBACK_SAMPLE_RATE; ++module_param(playback_sample_rate, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(playback_sample_rate, "Speaker Sample Rate"); ++ ++static int capture_sample_rate = UAC1_CAPTURE_SAMPLE_RATE; ++module_param(capture_sample_rate, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(capture_sample_rate, "Microphone Sample Rate"); ++ ++static int out_req_buf_size = UAC1_OUT_EP_MAX_PACKET_SIZE; ++module_param(out_req_buf_size, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(out_req_buf_size, "ISO OUT endpoint request buffer size"); ++ ++static int in_req_buf_size = UAC1_IN_EP_MAX_PACKET_SIZE; ++module_param(in_req_buf_size, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(in_req_buf_size, "ISO IN endpoint request buffer size"); ++ ++static int out_req_count = UAC1_OUT_REQ_COUNT; ++module_param(out_req_count, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(out_req_count, "ISO OUT endpoint request count"); ++ ++static int in_req_count = UAC1_IN_REQ_COUNT; ++module_param(in_req_count, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(in_req_count, "ISO IN endpoint request count"); ++ ++static int audio_playback_buf_size = UAC1_AUDIO_PLAYBACK_BUF_SIZE; ++module_param(audio_playback_buf_size, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(audio_playback_buf_size, "Audio playback buffer size"); ++ ++static int audio_capture_period_size = UAC1_AUDIO_PTN_PER_FRAME_SIZE; ++module_param(audio_capture_period_size, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(audio_capture_period_size, "Audio capture PtNumPerFrm size"); ++ ++static int audio_capture_buf_size = UAC1_AUDIO_CAPTURE_BUF_SIZE; ++module_param(audio_capture_buf_size, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(audio_capture_buf_size, "Audio capture buffer size"); ++ ++static int uac_function_enable = 0; ++module_param(uac_function_enable, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(uac_function_enable, "Audio Play Mode, 0: Disable UAC Function, " ++ "1: Speaker Only, 2: Microphone Only, 3: Speaker & Microphone"); ++#endif ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_RNDIS) ++#include "u_ether.h" ++#include "u_gether.h" ++#include "u_rndis.h" ++#include "rndis.h" ++ ++USB_ETHERNET_MODULE_PARAMETERS(); ++ ++static int rndis_function_enable = 0; ++module_param(rndis_function_enable, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(rndis_function_enable, "RNDIS Function Enable"); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_DFU) ++#include "f_dfu.h" ++ ++static int dfu_function_enable = 0; ++module_param(dfu_function_enable, int, S_IRUGO|S_IWUSR); ++MODULE_PARM_DESC(dfu_function_enable, "0: Disable 1: Enable"); ++#endif ++ + /* -------------------------------------------------------------------------- +- * Device descriptor ++ * Customer Define + */ ++#ifdef USE_AIT_XU ++#define UVC_EU1_GUID UVC_AIT_EU1_GUID ++#define UVC_EU2_GUID UVC_CUS_EU2_GUID ++#else ++#define UVC_EU1_GUID UVC_AIT_EU1_GUID ++#define UVC_EU2_GUID UVC_CUS_EU2_GUID ++#endif ++// termail link: ++// UVC_IT_ID -> UVC_PU_ID -> UVC_EU1_ID -> UVC_EU2_ID -> UVC_OT_ID; ++ ++#define UVC_EU1_ID (0x6) //for Isp use ++#define UVC_EU2_ID (0x2) //for customer to use ++#define UVC_PU_ID (0x3) ++#define UVC_IT_ID (0x1) ++#define UVC_OT_ID (0x7) + ++/* -------------------------------------------------------------------------- ++ * Device descriptor ++ */ + #define WEBCAM_VENDOR_ID 0x1d6b /* Linux Foundation */ + #define WEBCAM_PRODUCT_ID 0x0102 /* Webcam A/V gadget */ + #define WEBCAM_DEVICE_BCD 0x0010 /* 0.10 */ +@@ -62,7 +238,7 @@ static struct usb_string webcam_strings[] = { + }; + + static struct usb_gadget_strings webcam_stringtab = { +- .language = 0x0409, /* en-us */ ++ .language = 0x0409, /* en-us */ + .strings = webcam_strings, + }; + +@@ -71,8 +247,25 @@ static struct usb_gadget_strings *webcam_device_strings[] = { + NULL, + }; + +-static struct usb_function_instance *fi_uvc; +-static struct usb_function *f_uvc; ++#if defined(CONFIG_USB_WEBCAM_UVC) ++static struct usb_function_instance **fi_uvc; ++static struct usb_function **f_uvc; ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UAC) ++static struct usb_function_instance *fi_uac1; ++static struct usb_function *f_uac1; ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_RNDIS) // need to be the first interface ++static struct usb_function_instance *fi_rndis; ++static struct usb_function *f_rndis; ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_DFU) ++static struct usb_function_instance *fi_dfu; ++static struct usb_function *f_dfu; ++#endif + + static struct usb_device_descriptor webcam_device_descriptor = { + .bLength = USB_DT_DEVICE_SIZE, +@@ -88,27 +281,35 @@ static struct usb_device_descriptor webcam_device_descriptor = { + .iManufacturer = 0, /* dynamic */ + .iProduct = 0, /* dynamic */ + .iSerialNumber = 0, /* dynamic */ +- .bNumConfigurations = 0, /* dynamic */ ++ .bNumConfigurations = 0, /* dynamic */ + }; + +-DECLARE_UVC_HEADER_DESCRIPTOR(1); ++#if defined(CONFIG_USB_WEBCAM_UVC) ++#define UVC_HEADER_DESCRIPTOR_EX(num) UVC_HEADER_DESCRIPTOR(num) ++ ++DECLARE_UVC_HEADER_DESCRIPTOR(MULTI_STREAM_NUM); + +-static const struct UVC_HEADER_DESCRIPTOR(1) uvc_control_header = { +- .bLength = UVC_DT_HEADER_SIZE(1), ++static struct UVC_HEADER_DESCRIPTOR_EX(MULTI_STREAM_NUM) uvc_control_header = { ++ .bLength = UVC_DT_HEADER_SIZE(MULTI_STREAM_NUM), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VC_HEADER, ++ .bDescriptorSubType = UVC_VC_HEADER, ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++ .bcdUVC = cpu_to_le16(0x0150), ++#else + .bcdUVC = cpu_to_le16(0x0100), ++#endif + .wTotalLength = 0, /* dynamic */ + .dwClockFrequency = cpu_to_le32(48000000), + .bInCollection = 0, /* dynamic */ + .baInterfaceNr[0] = 0, /* dynamic */ + }; ++#endif + +-static const struct uvc_camera_terminal_descriptor uvc_camera_terminal = { ++static struct uvc_camera_terminal_descriptor uvc_camera_terminal = { + .bLength = UVC_DT_CAMERA_TERMINAL_SIZE(3), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VC_INPUT_TERMINAL, +- .bTerminalID = 1, ++ .bDescriptorSubType = UVC_VC_INPUT_TERMINAL, ++ .bTerminalID = UVC_IT_ID, + .wTerminalType = cpu_to_le16(0x0201), + .bAssocTerminal = 0, + .iTerminal = 0, +@@ -116,240 +317,1408 @@ static const struct uvc_camera_terminal_descriptor uvc_camera_terminal = { + .wObjectiveFocalLengthMax = cpu_to_le16(0), + .wOcularFocalLength = cpu_to_le16(0), + .bControlSize = 3, +- .bmControls[0] = 2, ++ .bmControls[0] = 1, + .bmControls[1] = 0, + .bmControls[2] = 0, + }; + +-static const struct uvc_processing_unit_descriptor uvc_processing = { ++DECLARE_UVC_EXTENSION_UNIT_DESCRIPTOR(1, 2); ++ ++static struct UVC_EXTENSION_UNIT_DESCRIPTOR(1,2) uvc_extension_unit1 = { ++ .bLength = UVC_DT_EXTENSION_UNIT_SIZE(1,2), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VC_EXTENSION_UNIT, ++ .bUnitID = UVC_EU1_ID, ++ .guidExtensionCode = UVC_EU1_GUID, ++ .bNumControls = 0x0E, ++ .bNrInPins = 0x01, ++ .baSourceID[0] = UVC_PU_ID, ++ .bControlSize = 0x02, ++ .bmControls[0] = 0xFF, ++ .bmControls[1] = 0x6F, ++ .iExtension = 0x00, ++}; ++ ++static struct UVC_EXTENSION_UNIT_DESCRIPTOR(1, 2) uvc_extension_unit2 = { ++ .bLength = UVC_DT_EXTENSION_UNIT_SIZE(1,2), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VC_EXTENSION_UNIT, ++ .bUnitID = UVC_EU2_ID, ++ .guidExtensionCode = UVC_EU2_GUID, ++ .bNumControls = 0x06, ++ .bNrInPins = 0x01, ++ .baSourceID[0] = UVC_EU1_ID, ++ .bControlSize = 0x02, ++ .bmControls[0] = 0x3F, ++ .bmControls[1] = 0x00, ++ .iExtension = 0x00, ++}; ++ ++static struct uvc_processing_unit_descriptor uvc_processing = { + .bLength = UVC_DT_PROCESSING_UNIT_SIZE(2), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VC_PROCESSING_UNIT, +- .bUnitID = 2, +- .bSourceID = 1, ++ .bDescriptorSubType = UVC_VC_PROCESSING_UNIT, ++ .bUnitID = UVC_PU_ID, ++ .bSourceID = UVC_IT_ID, + .wMaxMultiplier = cpu_to_le16(16*1024), + .bControlSize = 2, +- .bmControls[0] = 1, +- .bmControls[1] = 0, ++ .bmControls[0] = 0xFF, ++ .bmControls[1] = 0x7F, ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++ .bmControls[2] = 0, ++#endif + .iProcessing = 0, + }; + +-static const struct uvc_output_terminal_descriptor uvc_output_terminal = { ++static struct uvc_output_terminal_descriptor uvc_output_terminal[MAX_STREAM_SUPPORT] = {{ + .bLength = UVC_DT_OUTPUT_TERMINAL_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VC_OUTPUT_TERMINAL, +- .bTerminalID = 3, ++ .bDescriptorSubType = UVC_VC_OUTPUT_TERMINAL, ++ .bTerminalID = UVC_OT_ID, + .wTerminalType = cpu_to_le16(0x0101), + .bAssocTerminal = 0, +- .bSourceID = 2, ++ .bSourceID = UVC_EU2_ID, + .iTerminal = 0, +-}; ++}}; + +-DECLARE_UVC_INPUT_HEADER_DESCRIPTOR(1, 2); ++DECLARE_UVC_INPUT_HEADER_DESCRIPTOR(1, 5); ++DECLARE_UVC_FRAME_UNCOMPRESSED(3); ++DECLARE_UVC_FRAME_FRAMEBASE(3); ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++DECLARE_UVC_FRAME_H264(3); ++#endif ++ ++#define SUPPORT_YUY2 ++#define SUPPORT_NV12 ++#define SUPPORT_MJPG ++#define SUPPORT_H264 ++#define SUPPORT_H265 + +-static const struct UVC_INPUT_HEADER_DESCRIPTOR(1, 2) uvc_input_header = { +- .bLength = UVC_DT_INPUT_HEADER_SIZE(1, 2), ++static struct UVC_INPUT_HEADER_DESCRIPTOR(1, 5) uvc_input_header[MAX_STREAM_SUPPORT] = {{ ++ .bLength = UVC_DT_INPUT_HEADER_SIZE(1, 5), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_INPUT_HEADER, +- .bNumFormats = 2, ++ .bDescriptorSubType = UVC_VS_INPUT_HEADER, ++ .bNumFormats = 5, + .wTotalLength = 0, /* dynamic */ + .bEndpointAddress = 0, /* dynamic */ + .bmInfo = 0, +- .bTerminalLink = 3, ++ .bTerminalLink = UVC_OT_ID, + .bStillCaptureMethod = 0, + .bTriggerSupport = 0, + .bTriggerUsage = 0, + .bControlSize = 1, + .bmaControls[0][0] = 0, + .bmaControls[1][0] = 4, +-}; ++ .bmaControls[2][0] = 4, ++ .bmaControls[3][0] = 4, ++}}; + +-static const struct uvc_format_uncompressed uvc_format_yuv = { ++#ifdef SUPPORT_YUY2 ++static struct uvc_format_uncompressed uvc_format_yuy2 = { + .bLength = UVC_DT_FORMAT_UNCOMPRESSED_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_FORMAT_UNCOMPRESSED, ++ .bDescriptorSubType = UVC_VS_FORMAT_UNCOMPRESSED, + .bFormatIndex = 1, +- .bNumFrameDescriptors = 2, ++ .bNumFrameDescriptors = 7, + .guidFormat = +- { 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00, ++ { 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00, + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}, + .bBitsPerPixel = 16, +- .bDefaultFrameIndex = 1, ++ .bDefaultFrameIndex = 1, + .bAspectRatioX = 0, + .bAspectRatioY = 0, + .bmInterfaceFlags = 0, + .bCopyProtect = 0, + }; + +-DECLARE_UVC_FRAME_UNCOMPRESSED(1); +-DECLARE_UVC_FRAME_UNCOMPRESSED(3); + +-static const struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuv_360p = { ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_240p = { + .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, + .bFrameIndex = 1, + .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(320), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(320*240*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(320*240*2.0*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(320*240*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_480p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 2, ++ .bmCapabilities = 0, + .wWidth = cpu_to_le16(640), +- .wHeight = cpu_to_le16(360), +- .dwMinBitRate = cpu_to_le32(18432000), +- .dwMaxBitRate = cpu_to_le32(55296000), +- .dwMaxVideoFrameBufferSize = cpu_to_le32(460800), +- .dwDefaultFrameInterval = cpu_to_le32(666666), +- .bFrameIntervalType = 3, +- .dwFrameInterval[0] = cpu_to_le32(666666), +- .dwFrameInterval[1] = cpu_to_le32(1000000), +- .dwFrameInterval[2] = cpu_to_le32(5000000), ++ .wHeight = cpu_to_le16(480), ++ .dwMinBitRate = cpu_to_le32(640*480*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(640*480*2.0*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(640*480*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_720p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 3, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1280), ++ .wHeight = cpu_to_le16(720), ++ .dwMinBitRate = cpu_to_le32(1280*720*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(1280*720*2.0*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(1280*720*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_1080p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 4, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1920), ++ .wHeight = cpu_to_le16(1080), ++ .dwMinBitRate = cpu_to_le32(1920*1080*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(1920*1080*2.0*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(1920*1080*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_2kp = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 5, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(2560), ++ .wHeight = cpu_to_le16(1440), ++ .dwMinBitRate = cpu_to_le32(2560*1440*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(2560*1440*2.0*8*10), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(2560*1440*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_4kp = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 6, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(3840), ++ .wHeight = cpu_to_le16(2160), ++ .dwMinBitRate = cpu_to_le32(3840*2160*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(3840*2160*2.0*8*10), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(3840*2160*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(666666), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_yuy2_424x240p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 7, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(424), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(424*240*2.0*8*10), ++ .dwMaxBitRate = cpu_to_le32(424*240*2.0*8*10), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(424*240*2.0), ++ .dwDefaultFrameInterval = cpu_to_le32(666666), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + +-static const struct UVC_FRAME_UNCOMPRESSED(1) uvc_frame_yuv_720p = { +- .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(1), ++#define UVC_DESCRIPTOR_HEADERS_OF_YUY2_FRAME \ ++ (struct uvc_descriptor_header *) &uvc_format_yuy2, \ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_240p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_480p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_720p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_1080p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_2kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_4kp,\ ++ (struct uvc_descriptor_header *) &uvc_frame_yuy2_424x240p, ++#else ++#define UVC_DESCRIPTOR_HEADERS_OF_YUY2_FRAME ++#endif ++#ifdef SUPPORT_NV12 ++static struct uvc_format_uncompressed uvc_format_nv12 = { ++ .bLength = UVC_DT_FORMAT_UNCOMPRESSED_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FORMAT_UNCOMPRESSED, ++ .bFormatIndex = 2, ++ .bNumFrameDescriptors = 7, ++ .guidFormat = ++ { 'N', 'V', '1', '2', 0x00, 0x00, 0x10, 0x00, ++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}, ++ .bBitsPerPixel = 12, ++ .bDefaultFrameIndex = 1, ++ .bAspectRatioX = 0, ++ .bAspectRatioY = 0, ++ .bmInterfaceFlags = 0, ++ .bCopyProtect = 0, ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_240p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 1, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(320), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(320*240*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(320*240*1.5*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(320*240*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_480p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, + .bFrameIndex = 2, + .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(640), ++ .wHeight = cpu_to_le16(480), ++ .dwMinBitRate = cpu_to_le32(640*480*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(640*480*1.5*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(640*480*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_720p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 3, ++ .bmCapabilities = 0, + .wWidth = cpu_to_le16(1280), + .wHeight = cpu_to_le16(720), +- .dwMinBitRate = cpu_to_le32(29491200), +- .dwMaxBitRate = cpu_to_le32(29491200), +- .dwMaxVideoFrameBufferSize = cpu_to_le32(1843200), +- .dwDefaultFrameInterval = cpu_to_le32(5000000), +- .bFrameIntervalType = 1, +- .dwFrameInterval[0] = cpu_to_le32(5000000), ++ .dwMinBitRate = cpu_to_le32(1280*720*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(1280*720*1.5*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(1280*720*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_1080p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 4, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1920), ++ .wHeight = cpu_to_le16(1080), ++ .dwMinBitRate = cpu_to_le32(1920*1080*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(1920*1080*1.5*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(1920*1080*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_2kp = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 5, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(2560), ++ .wHeight = cpu_to_le16(1440), ++ .dwMinBitRate = cpu_to_le32(2560*1440*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(2560*1440*1.5*8*10), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(2560*1440*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_4kp = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 6, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(3840), ++ .wHeight = cpu_to_le16(2160), ++ .dwMinBitRate = cpu_to_le32(3840*2160*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(3840*2160*1.5*8*10), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(3840*2160*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(666666), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_UNCOMPRESSED(3) uvc_frame_nv12_424x240p = { ++ .bLength = UVC_DT_FRAME_UNCOMPRESSED_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_UNCOMPRESSED, ++ .bFrameIndex = 7, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(424), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(424*240*1.5*8*10), ++ .dwMaxBitRate = cpu_to_le32(424*240*1.5*8*10), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(424*240*1.5), ++ .dwDefaultFrameInterval = cpu_to_le32(666666), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + +-static const struct uvc_format_mjpeg uvc_format_mjpg = { ++#define UVC_DESCRIPTOR_HEADERS_OF_NV12_FRAME \ ++ (struct uvc_descriptor_header *) &uvc_format_nv12, \ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_240p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_480p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_720p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_1080p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_2kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_4kp,\ ++ (struct uvc_descriptor_header *) &uvc_frame_nv12_424x240p, ++#else ++#define UVC_DESCRIPTOR_HEADERS_OF_NV12_FRAME ++#endif ++ ++#ifdef SUPPORT_MJPG ++static struct uvc_format_mjpeg uvc_format_mjpg = { + .bLength = UVC_DT_FORMAT_MJPEG_SIZE, + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_FORMAT_MJPEG, +- .bFormatIndex = 2, +- .bNumFrameDescriptors = 2, ++ .bDescriptorSubType = UVC_VS_FORMAT_MJPEG, ++ .bFormatIndex = 3, ++ .bNumFrameDescriptors = 7, + .bmFlags = 0, +- .bDefaultFrameIndex = 1, ++ .bDefaultFrameIndex = 1, + .bAspectRatioX = 0, + .bAspectRatioY = 0, + .bmInterfaceFlags = 0, + .bCopyProtect = 0, + }; + +-DECLARE_UVC_FRAME_MJPEG(1); + DECLARE_UVC_FRAME_MJPEG(3); + +-static const struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_360p = { ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_240p = { + .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, + .bFrameIndex = 1, + .bmCapabilities = 0, +- .wWidth = cpu_to_le16(640), +- .wHeight = cpu_to_le16(360), +- .dwMinBitRate = cpu_to_le32(18432000), +- .dwMaxBitRate = cpu_to_le32(55296000), +- .dwMaxVideoFrameBufferSize = cpu_to_le32(460800), +- .dwDefaultFrameInterval = cpu_to_le32(666666), +- .bFrameIntervalType = 3, +- .dwFrameInterval[0] = cpu_to_le32(666666), +- .dwFrameInterval[1] = cpu_to_le32(1000000), +- .dwFrameInterval[2] = cpu_to_le32(5000000), ++ .wWidth = cpu_to_le16(320), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(320*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(320*240*2*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(320*240*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; +- +-static const struct UVC_FRAME_MJPEG(1) uvc_frame_mjpg_720p = { +- .bLength = UVC_DT_FRAME_MJPEG_SIZE(1), ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_480p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, + .bFrameIndex = 2, + .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(640), ++ .wHeight = cpu_to_le16(480), ++ .dwMinBitRate = cpu_to_le32(640*480*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(640*480*2*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(640*480*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_720p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bFrameIndex = 3, ++ .bmCapabilities = 0, + .wWidth = cpu_to_le16(1280), + .wHeight = cpu_to_le16(720), +- .dwMinBitRate = cpu_to_le32(29491200), +- .dwMaxBitRate = cpu_to_le32(29491200), +- .dwMaxVideoFrameBufferSize = cpu_to_le32(1843200), +- .dwDefaultFrameInterval = cpu_to_le32(5000000), +- .bFrameIntervalType = 1, +- .dwFrameInterval[0] = cpu_to_le32(5000000), ++ .dwMinBitRate = cpu_to_le32(1280*720*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(1280*720*2*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(1280*720*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_1080p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bFrameIndex = 4, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1920), ++ .wHeight = cpu_to_le16(1080), ++ .dwMinBitRate = cpu_to_le32(1920*1080*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(1920*1080*2*8*30), ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(1920*1080*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + +-static const struct uvc_color_matching_descriptor uvc_color_matching = { +- .bLength = UVC_DT_COLOR_MATCHING_SIZE, ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_2kp = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), + .bDescriptorType = USB_DT_CS_INTERFACE, +- .bDescriptorSubType = UVC_VS_COLORFORMAT, +- .bColorPrimaries = 1, +- .bTransferCharacteristics = 1, +- .bMatrixCoefficients = 4, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bFrameIndex = 5, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(2560), ++ .wHeight = cpu_to_le16(1440), ++ .dwMinBitRate = cpu_to_le32(2560*1440*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(2560*1440*2*8*10), //overflow ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(2560*1440*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_4kp = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bFrameIndex = 6, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(3840), ++ .wHeight = cpu_to_le16(2160), ++ .dwMinBitRate = cpu_to_le32(3840*2160*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(3840*2160*2*8*10), //overflow ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(3840*2160*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_MJPEG(3) uvc_frame_mjpg_424x240p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_MJPEG, ++ .bFrameIndex = 7, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(424), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(424*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(424*240*2*8*10), //overflow ++ .dwMaxVideoFrameBufferSize = cpu_to_le32(424*240*2), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + +-static const struct uvc_descriptor_header * const uvc_fs_control_cls[] = { +- (const struct uvc_descriptor_header *) &uvc_control_header, +- (const struct uvc_descriptor_header *) &uvc_camera_terminal, +- (const struct uvc_descriptor_header *) &uvc_processing, +- (const struct uvc_descriptor_header *) &uvc_output_terminal, +- NULL, ++#define UVC_DESCRIPTOR_HEADERS_OF_MJPG_FRAME \ ++ (struct uvc_descriptor_header *) &uvc_format_mjpg, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_240p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_480p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_720p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_1080p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_2kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_4kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_mjpg_424x240p, ++#else ++#define UVC_DESCRIPTOR_HEADERS_OF_MJPG_FRAME ++#endif ++ ++#ifdef SUPPORT_H264 ++#if 0 ++static struct uvc_format_h264 uvc_format_h264 = { ++ .bLength = UVC_DT_FORMAT_H264_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FORMAT_H264, ++ .bFormatIndex = 3, ++ .bNumFrameDescriptors = 1, ++ .bDefaultFrameIndex = 1, ++ .bMaxCodecConfigDelay = 0x4, ++ .bmSupportedSliceModes = 0, ++ .bmSupportedSyncFrameTypes = 0x76, ++ .bResolutionScaling = 0, ++ .Reserved1 = 0, ++ .bmSupportedRateControlModes = 0x3F, ++ .wMaxMBperSecOneResNoScalability = cpu_to_le16(972), ++ .wMaxMBperSecTwoResNoScalability = 0, ++ .wMaxMBperSecThreeResNoScalability = 0, ++ .wMaxMBperSecFourResNoScalability = 0, ++ .wMaxMBperSecOneResTemporalScalability = cpu_to_le16(972), ++ .wMaxMBperSecTwoResTemporalScalability = 0, ++ .wMaxMBperSecThreeResTemporalScalability = 0, ++ .wMaxMBperSecFourResTemporalScalability = 0, ++ .wMaxMBperSecOneResTemporalQualityScalability = cpu_to_le16(972), ++ .wMaxMBperSecTwoResTemporalQualityScalability = 0, ++ .wMaxMBperSecThreeResTemporalQualityScalability = 0, ++ .wMaxMBperSecFourResTemporalQualityScalability = 0, ++ .wMaxMBperSecOneResTemporalSpatialScalability = 0, ++ .wMaxMBperSecTwoResTemporalSpatialScalability = 0, ++ .wMaxMBperSecThreeResTemporalSpatialScalability = 0, ++ .wMaxMBperSecFourResTemporalSpatialScalability = 0, ++ .wMaxMBperSecOneResFullScalability = 0, ++ .wMaxMBperSecTwoResFullScalability = 0, ++ .wMaxMBperSecThreeResFullScalability = 0, ++ .wMaxMBperSecFourResFullScalability = 0, + }; + +-static const struct uvc_descriptor_header * const uvc_ss_control_cls[] = { +- (const struct uvc_descriptor_header *) &uvc_control_header, +- (const struct uvc_descriptor_header *) &uvc_camera_terminal, +- (const struct uvc_descriptor_header *) &uvc_processing, +- (const struct uvc_descriptor_header *) &uvc_output_terminal, +- NULL, ++static struct UVC_FRAME_H264(3) uvc_frame_h264_240p = { ++ .bLength = UVC_DT_FRAME_H264_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_H264, ++ .bFrameIndex = 1, ++ .wWidth = cpu_to_le16(320), ++ .wHeight = cpu_to_le16(240), ++ .wSARwidth = 1, ++ .wSARheight = 1, ++ .wProfile = 0x6400, ++ .bLevelIDC = 0x33, ++ .bmSupportedUsages = 0x70003, ++ .wConstrainedToolset = cpu_to_le16(0), ++ .bmCapabilities = 0x47, ++ .bmSVCCapabilities = 0x4, ++ .bmMVCCapabilities = 0, ++ .dwMinBitRate = cpu_to_le32(320*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(320*240*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bNumFrameIntervals = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + +-static const struct uvc_descriptor_header * const uvc_fs_streaming_cls[] = { +- (const struct uvc_descriptor_header *) &uvc_input_header, +- (const struct uvc_descriptor_header *) &uvc_format_yuv, +- (const struct uvc_descriptor_header *) &uvc_frame_yuv_360p, +- (const struct uvc_descriptor_header *) &uvc_frame_yuv_720p, +- (const struct uvc_descriptor_header *) &uvc_format_mjpg, +- (const struct uvc_descriptor_header *) &uvc_frame_mjpg_360p, +- (const struct uvc_descriptor_header *) &uvc_frame_mjpg_720p, +- (const struct uvc_descriptor_header *) &uvc_color_matching, +- NULL, ++static struct UVC_FRAME_H264(3) uvc_frame_h264_480p; ++static struct UVC_FRAME_H264(3) uvc_frame_h264_720p; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_1080p; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_2kp; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_4kp; ++#else ++static struct uvc_format_framebase uvc_format_h264 = { ++ .bLength = UVC_DT_FORMAT_FRAMEBASE_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FORMAT_FRAME_BASED, ++ .bFormatIndex = 4, ++ .bNumFrameDescriptors = 7, ++ .guidFormat = ++ { 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, ++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}, ++ .bBitsPerPixel = 16, ++ .bDefaultFrameIndex = 1, ++ .bAspectRatioX = 0, ++ .bAspectRatioY = 0, ++ .bmInterfaceFlags = 0, ++ .bCopyProtect = 0, ++ .bVariableSize = 1 + }; + +-static const struct uvc_descriptor_header * const uvc_hs_streaming_cls[] = { +- (const struct uvc_descriptor_header *) &uvc_input_header, +- (const struct uvc_descriptor_header *) &uvc_format_yuv, +- (const struct uvc_descriptor_header *) &uvc_frame_yuv_360p, +- (const struct uvc_descriptor_header *) &uvc_frame_yuv_720p, +- (const struct uvc_descriptor_header *) &uvc_format_mjpg, +- (const struct uvc_descriptor_header *) &uvc_frame_mjpg_360p, +- (const struct uvc_descriptor_header *) &uvc_frame_mjpg_720p, +- (const struct uvc_descriptor_header *) &uvc_color_matching, +- NULL, ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_240p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 1, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(320), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(320*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(320*240*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_480p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 2, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(640), ++ .wHeight = cpu_to_le16(480), ++ .dwMinBitRate = cpu_to_le32(640*480*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(640*480*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_720p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 3, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1280), ++ .wHeight = cpu_to_le16(720), ++ .dwMinBitRate = cpu_to_le32(1280*720*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(1280*720*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_1080p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 4, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1920), ++ .wHeight = cpu_to_le16(1080), ++ .dwMinBitRate = cpu_to_le32(1920*1080*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(1920*1080*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_2kp = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 5, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(2560), ++ .wHeight = cpu_to_le16(1440), ++ .dwMinBitRate = cpu_to_le32(2560*1440*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(2560*1440*2*8*10), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_4kp = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 6, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(3840), ++ .wHeight = cpu_to_le16(2160), ++ .dwMinBitRate = cpu_to_le32(3840*2160*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(3840*2160*2*8*10), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h264_424x240p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 7, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(424), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(424*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(424*240*2*8*10), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + +-static const struct uvc_descriptor_header * const uvc_ss_streaming_cls[] = { +- (const struct uvc_descriptor_header *) &uvc_input_header, +- (const struct uvc_descriptor_header *) &uvc_format_yuv, +- (const struct uvc_descriptor_header *) &uvc_frame_yuv_360p, +- (const struct uvc_descriptor_header *) &uvc_frame_yuv_720p, +- (const struct uvc_descriptor_header *) &uvc_format_mjpg, +- (const struct uvc_descriptor_header *) &uvc_frame_mjpg_360p, +- (const struct uvc_descriptor_header *) &uvc_frame_mjpg_720p, +- (const struct uvc_descriptor_header *) &uvc_color_matching, +- NULL, ++#endif ++#define UVC_DESCRIPTOR_HEADERS_OF_H264_FRAME \ ++ (struct uvc_descriptor_header *) &uvc_format_h264, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_240p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_480p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_720p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_1080p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_2kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_4kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h264_424x240p, ++#else ++#define UVC_DESCRIPTOR_HEADERS_OF_H264_FRAME ++#endif ++ ++#ifdef SUPPORT_H265 ++static struct uvc_format_framebase uvc_format_h265 = { ++ .bLength = UVC_DT_FORMAT_FRAMEBASE_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FORMAT_FRAME_BASED, ++ .bFormatIndex = 5, ++ .bNumFrameDescriptors = 7, ++ .guidFormat = ++ { 'H', '2', '6', '5', 0x00, 0x00, 0x10, 0x00, ++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}, ++ .bBitsPerPixel = 16, ++ .bDefaultFrameIndex = 1, ++ .bAspectRatioX = 0, ++ .bAspectRatioY = 0, ++ .bmInterfaceFlags = 0, ++ .bCopyProtect = 0, ++ .bVariableSize = 1 ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_240p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 1, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(320), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(320*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(320*240*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_480p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 2, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(640), ++ .wHeight = cpu_to_le16(480), ++ .dwMinBitRate = cpu_to_le32(640*480*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(640*480*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_720p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 3, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1280), ++ .wHeight = cpu_to_le16(720), ++ .dwMinBitRate = cpu_to_le32(1280*720*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(1280*720*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_1080p = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 4, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(1920), ++ .wHeight = cpu_to_le16(1080), ++ .dwMinBitRate = cpu_to_le32(1920*1080*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(1920*1080*2*8*30), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_2kp = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 5, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(2560), ++ .wHeight = cpu_to_le16(1440), ++ .dwMinBitRate = cpu_to_le32(2560*1440*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(2560*1440*2*8*10), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_4kp = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 6, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(3840), ++ .wHeight = cpu_to_le16(2160), ++ .dwMinBitRate = cpu_to_le32(3840*2160*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(3840*2160*2*8*10), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), ++}; ++static struct UVC_FRAME_FRAMEBASE(3) uvc_frame_h265_424x240 = { ++ .bLength = UVC_DT_FRAME_MJPEG_SIZE(3), ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_FRAME_FRAME_BASED, ++ .bFrameIndex = 7, ++ .bmCapabilities = 0, ++ .wWidth = cpu_to_le16(424), ++ .wHeight = cpu_to_le16(240), ++ .dwMinBitRate = cpu_to_le32(424*240*2*8*10), ++ .dwMaxBitRate = cpu_to_le32(424*240*2*8*10), ++ .dwDefaultFrameInterval = cpu_to_le32(333333), ++ .bFrameIntervalType = 3, ++ .dwFrameInterval[0] = cpu_to_le32(333333), ++ .dwFrameInterval[1] = cpu_to_le32(666666), ++ .dwFrameInterval[2] = cpu_to_le32(1000000), + }; + ++#define UVC_DESCRIPTOR_HEADERS_OF_H265_FRAME \ ++ (struct uvc_descriptor_header *) &uvc_format_h265, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_240p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_480p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_720p, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_1080p,\ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_2kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_4kp, \ ++ (struct uvc_descriptor_header *) &uvc_frame_h265_424x240, \ ++ (struct uvc_descriptor_header *) &uvc_color_matching, ++#else ++#define UVC_DESCRIPTOR_HEADERS_OF_H265_FRAME ++#endif ++ ++static struct uvc_color_matching_descriptor uvc_color_matching = { ++ .bLength = UVC_DT_COLOR_MATCHING_SIZE, ++ .bDescriptorType = USB_DT_CS_INTERFACE, ++ .bDescriptorSubType = UVC_VS_COLORFORMAT, ++ .bColorPrimaries = 1, ++ .bTransferCharacteristics = 1, ++ .bMatrixCoefficients = 4, ++}; ++ ++#define MAX_CONTROL_SIZE 10 ++#define BASE_CONTROL_SIZE 6 ++static struct uvc_descriptor_header ** uvc_fs_control_cls; ++static struct uvc_descriptor_header ** uvc_ss_control_cls; ++ ++#define MAX_FORMAT_COUNT 50 ++static struct uvc_descriptor_header ** uvc_fs_streaming_cls; ++static struct uvc_descriptor_header ** uvc_hs_streaming_cls; ++static struct uvc_descriptor_header ** uvc_ss_streaming_cls; ++static struct uvc_descriptor_header * uvc_streaming_cls_std[MAX_STREAM_SUPPORT][MAX_FORMAT_COUNT] = { ++ { ++ (struct uvc_descriptor_header *) &uvc_input_header[0], ++ UVC_DESCRIPTOR_HEADERS_OF_YUY2_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_NV12_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_MJPG_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H264_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H265_FRAME ++ NULL, ++ }, ++ { ++ (struct uvc_descriptor_header *) &uvc_input_header[1], ++ UVC_DESCRIPTOR_HEADERS_OF_YUY2_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_NV12_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_MJPG_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H264_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H265_FRAME ++ NULL, ++ }, ++ { ++ (struct uvc_descriptor_header *) &uvc_input_header[2], ++ UVC_DESCRIPTOR_HEADERS_OF_YUY2_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_NV12_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_MJPG_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H264_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H265_FRAME ++ NULL, ++ }, ++ { ++ (struct uvc_descriptor_header *) &uvc_input_header[3], ++ UVC_DESCRIPTOR_HEADERS_OF_YUY2_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_NV12_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_MJPG_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H264_FRAME ++ UVC_DESCRIPTOR_HEADERS_OF_H265_FRAME ++ NULL, ++ } ++}; + /* -------------------------------------------------------------------------- + * USB configuration + */ ++#if defined(CONFIG_USB_WEBCAM_UVC) ++static int video_bind_config(struct usb_configuration *c) ++{ ++ int status = 0, i; ++ ++ f_uvc = kzalloc(uvc_function_enable * sizeof(*f_uvc), GFP_KERNEL); ++ for (i = 0;i < uvc_function_enable;i++) ++ { ++ f_uvc[i] = usb_get_function(fi_uvc[i]); ++ if (IS_ERR(f_uvc[i])) ++ return PTR_ERR(f_uvc[i]); ++ ++ status = usb_add_function(c, f_uvc[i]); ++ if (status < 0) ++ { ++ usb_put_function(f_uvc[i]); ++ break; ++ } ++ } ++ return status; ++} ++ + + static int +-webcam_config_bind(struct usb_configuration *c) ++video_unbind(struct usb_composite_dev *cdev) ++{ ++ int i; ++ ++ for (i = 0;i < uvc_function_enable;i++) ++ { ++ if (!IS_ERR_OR_NULL(f_uvc[i])) ++ { ++ usb_put_function(f_uvc[i]); ++ } ++ if (!IS_ERR_OR_NULL(fi_uvc[i])) ++ { ++ usb_put_function_instance(fi_uvc[i]); ++ } ++ } ++ if (!IS_ERR_OR_NULL(f_uvc)) ++ { ++ kfree(f_uvc); ++ f_uvc = NULL; ++ } ++ if (!IS_ERR_OR_NULL(fi_uvc)) ++ { ++ kfree(fi_uvc); ++ fi_uvc = NULL; ++ } ++ if (uvc_fs_streaming_cls) ++ { ++ kfree(uvc_fs_streaming_cls); ++ kfree(uvc_hs_streaming_cls); ++ kfree(uvc_ss_streaming_cls); ++ uvc_fs_streaming_cls = NULL; ++ uvc_hs_streaming_cls = NULL; ++ uvc_ss_streaming_cls = NULL; ++ } ++ if (uvc_fs_control_cls) ++ { ++ kfree(uvc_fs_control_cls); ++ kfree(uvc_ss_control_cls); ++ uvc_fs_control_cls = NULL; ++ uvc_ss_control_cls = NULL; ++ } ++ return 0; ++} ++ ++static int __init video_bind(struct usb_composite_dev *cdev) ++{ ++ int i,j; ++ struct f_uvc_opts *uvc_opts; ++ struct uvc_descriptor_header ** fs_control_cls = NULL; ++ struct uvc_descriptor_header ** ss_control_cls = NULL; ++ struct uvc_descriptor_header ** fs_streaming_cls = NULL; ++ struct uvc_descriptor_header ** hs_streaming_cls = NULL; ++ struct uvc_descriptor_header ** ss_streaming_cls = NULL; ++ ++ if (MULTI_STREAM_NUM > MAX_STREAM_SUPPORT) ++ { ++ BUG(); ++ } ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ uvc_function_enable = 1; ++#endif ++ ++ if (!uvc_fs_control_cls) ++ { ++ uvc_fs_control_cls = ++ kzalloc(sizeof(void*) * uvc_function_enable * MAX_CONTROL_SIZE, GFP_KERNEL); ++ uvc_ss_control_cls = ++ kzalloc(sizeof(void*) * uvc_function_enable * MAX_CONTROL_SIZE, GFP_KERNEL); ++ } ++ ++ if (!uvc_fs_streaming_cls) ++ { ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ uvc_fs_streaming_cls = ++ kzalloc(sizeof(void*) * MAX_STREAM_SUPPORT * MAX_FORMAT_COUNT, GFP_KERNEL); ++ uvc_hs_streaming_cls = ++ kzalloc(sizeof(void*) * MAX_STREAM_SUPPORT * MAX_FORMAT_COUNT, GFP_KERNEL); ++ uvc_ss_streaming_cls = ++ kzalloc(sizeof(void*) * MAX_STREAM_SUPPORT * MAX_FORMAT_COUNT, GFP_KERNEL); ++#else ++ uvc_fs_streaming_cls = ++ kzalloc(sizeof(void*) * uvc_function_enable * MAX_FORMAT_COUNT, GFP_KERNEL); ++ uvc_hs_streaming_cls = ++ kzalloc(sizeof(void*) * uvc_function_enable * MAX_FORMAT_COUNT, GFP_KERNEL); ++ uvc_ss_streaming_cls = ++ kzalloc(sizeof(void*) * uvc_function_enable * MAX_FORMAT_COUNT, GFP_KERNEL); ++#endif ++ } ++ fi_uvc = kzalloc(uvc_function_enable * sizeof(*fi_uvc), GFP_KERNEL); ++ for (i=0; i < uvc_function_enable; i++) ++ { ++ uvc_opts = NULL; ++ ++ fi_uvc[i] = usb_get_function_instance("uvc"); ++ if (IS_ERR(fi_uvc[i])) ++ return PTR_ERR(fi_uvc[i]); ++ ++ uvc_opts = container_of(fi_uvc[i], struct f_uvc_opts, func_inst); ++ if(IS_ERR(uvc_opts)) ++ return PTR_ERR(uvc_opts); ++ ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ for (j=0; j < MULTI_STREAM_NUM; j++) ++ { ++ uvc_opts->streaming_interval[j] = streaming_interval[j]; ++ uvc_opts->streaming_maxpacket[j] = streaming_maxpacket[j]; ++ uvc_opts->streaming_maxburst[j] = streaming_maxburst[j]; ++ uvc_opts->streaming_name[j] = streaming_name[j]; ++ } ++#else ++ uvc_opts->streaming_interval = streaming_interval[i]; ++ uvc_opts->streaming_maxpacket = streaming_maxpacket[i]; ++ uvc_opts->streaming_maxburst = streaming_maxburst[i]; ++ uvc_opts->streaming_name = streaming_name[i]; ++#endif ++ uvc_opts->bulk_streaming_ep = bulk_streaming_ep; ++ ++ /* ++ * controls: ++ */ ++ fs_control_cls = &uvc_fs_control_cls[i * MAX_CONTROL_SIZE]; ++ ss_control_cls = &uvc_ss_control_cls[i * MAX_CONTROL_SIZE]; ++ ++ for (j=0;j < MAX_STREAM_SUPPORT;j++) ++ { ++ memcpy(&uvc_output_terminal[j], &uvc_output_terminal[0], sizeof(uvc_output_terminal[0])); ++ uvc_output_terminal[j].bTerminalID = UVC_OT_ID + j; ++ } ++ ++ { ++ fs_control_cls[0] = (struct uvc_descriptor_header *) &uvc_control_header; ++ fs_control_cls[1] = (struct uvc_descriptor_header *) &uvc_camera_terminal; ++ fs_control_cls[2] = (struct uvc_descriptor_header *) &uvc_processing; ++ fs_control_cls[3] = (struct uvc_descriptor_header *) &uvc_extension_unit1; ++ fs_control_cls[4] = (struct uvc_descriptor_header *) &uvc_extension_unit2; ++ fs_control_cls[5] = (struct uvc_descriptor_header *) &uvc_output_terminal[i]; ++ for (j=1; j < MULTI_STREAM_NUM; j++) ++ { ++ fs_control_cls[5+j] = (struct uvc_descriptor_header *) &uvc_output_terminal[j]; ++ } ++ fs_control_cls[5+MULTI_STREAM_NUM] = NULL; ++ ++ ss_control_cls[0] = (struct uvc_descriptor_header *) &uvc_control_header; ++ ss_control_cls[1] = (struct uvc_descriptor_header *) &uvc_camera_terminal; ++ ss_control_cls[2] = (struct uvc_descriptor_header *) &uvc_processing; ++ ss_control_cls[3] = (struct uvc_descriptor_header *) &uvc_extension_unit1; ++ ss_control_cls[4] = (struct uvc_descriptor_header *) &uvc_extension_unit2; ++ ss_control_cls[5] = (struct uvc_descriptor_header *) &uvc_output_terminal[i]; ++ for (j=1;j < MULTI_STREAM_NUM;j++) ++ { ++ ss_control_cls[5+j] = (struct uvc_descriptor_header *) &uvc_output_terminal[j]; ++ } ++ ss_control_cls[5+MULTI_STREAM_NUM] = NULL; ++ } ++ ++ uvc_opts->fs_control = ++ (const struct uvc_descriptor_header * const *)fs_control_cls; ++ uvc_opts->ss_control = ++ (const struct uvc_descriptor_header * const *)ss_control_cls; ++ ++ /* ++ * Formats: ++ */ ++ fs_streaming_cls = &uvc_fs_streaming_cls[i * MAX_FORMAT_COUNT]; ++ hs_streaming_cls = &uvc_hs_streaming_cls[i * MAX_FORMAT_COUNT]; ++ ss_streaming_cls = &uvc_ss_streaming_cls[i * MAX_FORMAT_COUNT]; ++ ++#ifdef CONFIG_SS_GADGET_UVC_MULTI_STREAM ++ for (j=0; j < MAX_STREAM_SUPPORT; j++) ++ { ++ memcpy(&uvc_input_header[j], &uvc_input_header[0], sizeof(uvc_input_header[j])); ++ uvc_input_header[j].bTerminalLink = UVC_OT_ID + j; ++ ++ memcpy(fs_streaming_cls + j * MAX_FORMAT_COUNT, uvc_streaming_cls_std[j], sizeof(uvc_streaming_cls_std[j])); ++ memcpy(hs_streaming_cls + j * MAX_FORMAT_COUNT, uvc_streaming_cls_std[j], sizeof(uvc_streaming_cls_std[j])); ++ memcpy(ss_streaming_cls + j * MAX_FORMAT_COUNT, uvc_streaming_cls_std[j], sizeof(uvc_streaming_cls_std[j])); ++ } ++#else ++ { ++ memcpy(&uvc_input_header[i], &uvc_input_header[0], sizeof(uvc_input_header[i])); ++ uvc_input_header[i].bTerminalLink = UVC_OT_ID + i; ++ ++ memcpy(fs_streaming_cls, uvc_streaming_cls_std[i], sizeof(uvc_streaming_cls_std[i])); ++ memcpy(hs_streaming_cls, uvc_streaming_cls_std[i], sizeof(uvc_streaming_cls_std[i])); ++ memcpy(ss_streaming_cls, uvc_streaming_cls_std[i], sizeof(uvc_streaming_cls_std[i])); ++ } ++#endif ++ ++ fs_streaming_cls[0] = ++ (struct uvc_descriptor_header *) &uvc_input_header[i]; ++ hs_streaming_cls[0] = ++ (struct uvc_descriptor_header *) &uvc_input_header[i]; ++ ss_streaming_cls[0] = ++ (struct uvc_descriptor_header *) &uvc_input_header[i]; ++ ++ uvc_opts->fs_streaming = ++ (const struct uvc_descriptor_header * const *)fs_streaming_cls; ++ uvc_opts->hs_streaming = ++ (const struct uvc_descriptor_header * const *)hs_streaming_cls; ++ uvc_opts->ss_streaming = ++ (const struct uvc_descriptor_header * const *)ss_streaming_cls; ++ } ++ uvc_set_trace_param(trace); ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_DFU) ++static int __init dfu_bind_config(struct usb_configuration *c) ++{ ++ int status; ++ f_dfu = usb_get_function(fi_dfu); ++ if (IS_ERR(f_dfu)) { ++ status = PTR_ERR(f_dfu); ++ return status; ++ } ++ status = usb_add_function(c, f_dfu); ++ if (status < 0) { ++ usb_put_function(f_dfu); ++ return status; ++ } ++ return 0; ++} ++static int __init dfu_bind(struct usb_composite_dev *cdev) ++{ ++ struct f_dfu_opts *dfu_opts; ++ ++ fi_dfu = usb_get_function_instance("dfu"); ++ if (IS_ERR(fi_dfu)) ++ return PTR_ERR(fi_dfu); ++ ++ dfu_opts = container_of(fi_dfu, struct f_dfu_opts, func_inst); ++ if(IS_ERR(dfu_opts)) ++ return PTR_ERR(dfu_opts); ++ ++ return 0; ++} ++static int __exit dfu_unbind(struct usb_composite_dev *cdev) ++{ ++ if (!IS_ERR_OR_NULL(f_dfu)) ++ { ++ usb_put_function(f_dfu); ++ f_dfu = NULL; ++ } ++ if (!IS_ERR_OR_NULL(fi_dfu)) ++ { ++ usb_put_function_instance(fi_dfu); ++ fi_dfu = NULL; ++ } ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_RNDIS) ++static int __init rndis_bind_config(struct usb_configuration *c) + { + int status = 0; + +- f_uvc = usb_get_function(fi_uvc); +- if (IS_ERR(f_uvc)) +- return PTR_ERR(f_uvc); ++ f_rndis = usb_get_function(fi_rndis); ++ if (IS_ERR(f_rndis)) ++ return PTR_ERR(f_rndis); + +- status = usb_add_function(c, f_uvc); ++ status = usb_add_function(c, f_rndis); + if (status < 0) +- usb_put_function(f_uvc); ++ usb_put_function(f_rndis); ++ ++ return status; ++} ++ ++static int __init rndis_bind(struct usb_composite_dev *cdev) ++{ ++ struct f_rndis_opts *rndis_opts = NULL; ++ struct net_device *net; ++ int status; ++ ++ fi_rndis = usb_get_function_instance("rndis"); ++ if (IS_ERR(fi_rndis)) { ++ status = PTR_ERR(fi_rndis); ++ goto fail; ++ } ++ ++ /* set up main config label and device descriptor */ ++ rndis_opts = container_of(fi_rndis, struct f_rndis_opts, ++ func_inst); ++ ++ net = rndis_opts->net; ++ ++ gether_set_qmult(net, qmult); ++ if (!gether_set_host_addr(net, host_addr)) ++ pr_info("using host ethernet address: %s", host_addr); ++ if (!gether_set_dev_addr(net, dev_addr)) ++ pr_info("using self ethernet address: %s", dev_addr); ++ ++ fi_rndis = usb_get_function_instance("rndis"); ++ if (IS_ERR(fi_rndis)) { ++ status = PTR_ERR(fi_rndis); ++ goto fail; ++ } + ++ return 0; ++ ++fail: ++ fi_rndis = NULL; + return status; + } + ++static int __exit rndis_unbind(struct usb_composite_dev *cdev) ++{ ++ if (!IS_ERR_OR_NULL(f_rndis)) ++ { ++ usb_put_function(f_rndis); ++ f_rndis = NULL; ++ } ++ if (!IS_ERR_OR_NULL(fi_rndis)) ++ { ++ usb_put_function_instance(fi_rndis); ++ fi_rndis = NULL; ++ } ++ ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UAC) ++static int __init audio_bind_config(struct usb_configuration *c) ++{ ++ int status; ++ f_uac1 = usb_get_function(fi_uac1); ++ if (IS_ERR(f_uac1)) { ++ status = PTR_ERR(f_uac1); ++ return status; ++ } ++ status = usb_add_function(c, f_uac1); ++ if (status < 0) { ++ usb_put_function(f_uac1); ++ return status; ++ } ++ return 0; ++} ++static int __init audio_bind(struct usb_composite_dev *cdev) ++{ ++#ifndef CONFIG_USB_WEBCAM_UAC1_LEGACY ++ struct f_uac1_opts *uac1_opts; ++ fi_uac1 = usb_get_function_instance("uac1"); ++#else ++ struct f_uac1_legacy_opts *uac1_opts; ++ fi_uac1 = usb_get_function_instance("uac1_legacy"); ++#endif ++ if (IS_ERR(fi_uac1)) ++ return PTR_ERR(fi_uac1); ++ ++#ifndef CONFIG_USB_WEBCAM_UAC1_LEGACY ++ uac1_opts = container_of(fi_uac1, struct f_uac1_opts, func_inst); ++ ++ if(ENABLE_MICROPHONE== uac_function_enable||ENABLE_MIC_AND_SPK==uac_function_enable) ++ uac1_opts->p_chmask = p_chmask; ++ else ++ uac1_opts->p_chmask = 0; ++ ++ uac1_opts->p_mpsize = p_mpsize; ++ uac1_opts->p_srate = p_srate; ++ uac1_opts->p_ssize = p_ssize; ++ ++ ++ if(ENABLE_SPEAKER== uac_function_enable||ENABLE_MIC_AND_SPK==uac_function_enable) ++ uac1_opts->c_chmask = c_chmask; ++ else ++ uac1_opts->c_chmask = 0; ++ ++ uac1_opts->c_mpsize = c_mpsize; ++ uac1_opts->c_srate = c_srate; ++ uac1_opts->c_ssize = c_ssize; ++ uac1_opts->req_number = UAC1_DEF_REQ_NUM; ++ uac1_opts->audio_play_mode = uac_function_enable; ++#else /* CONFIG_USB_WEBCAM_UAC1_LEGACY */ ++ uac1_opts = container_of(fi_uac1, struct f_uac1_legacy_opts, func_inst); ++ if(IS_ERR(uac1_opts)) ++ return PTR_ERR(uac1_opts); ++ ++ uac1_opts->fn_play = fn_play; ++ uac1_opts->fn_cap = fn_cap; ++ uac1_opts->fn_cntl = fn_cntl; ++ uac1_opts->playback_channel_count = playback_channel_count; ++ uac1_opts->playback_sample_rate = playback_sample_rate; ++ uac1_opts->capture_channel_count = capture_channel_count; ++ uac1_opts->capture_sample_rate = capture_sample_rate; ++ uac1_opts->out_req_buf_size = out_req_buf_size; ++ uac1_opts->out_req_count = out_req_count; ++ uac1_opts->audio_playback_buf_size = audio_playback_buf_size; ++ uac1_opts->in_req_buf_size = in_req_buf_size; ++ uac1_opts->in_req_count = in_req_count; ++ uac1_opts->audio_capture_period_size = audio_capture_period_size; ++ uac1_opts->audio_capture_buf_size = audio_capture_buf_size; ++ uac1_opts->audio_play_mode = uac_function_enable; ++#endif ++ return 0; ++} ++static int __exit audio_unbind(struct usb_composite_dev *cdev) ++{ ++ if (!IS_ERR_OR_NULL(f_uac1)) ++ { ++ usb_put_function(f_uac1); ++ f_uac1 = NULL; ++ } ++ if (!IS_ERR_OR_NULL(fi_uac1)) ++ { ++ usb_put_function_instance(fi_uac1); ++ fi_uac1 = NULL; ++ } ++ return 0; ++} ++#endif ++ + static struct usb_configuration webcam_config_driver = { + .label = webcam_config_label, + .bConfigurationValue = 1, +@@ -358,45 +1727,57 @@ static struct usb_configuration webcam_config_driver = { + .MaxPower = CONFIG_USB_GADGET_VBUS_DRAW, + }; + +-static int +-webcam_unbind(struct usb_composite_dev *cdev) ++static int __init webcam_bind_config(struct usb_configuration *c) + { +- if (!IS_ERR_OR_NULL(f_uvc)) +- usb_put_function(f_uvc); +- if (!IS_ERR_OR_NULL(fi_uvc)) +- usb_put_function_instance(fi_uvc); +- return 0; +-} ++ int ret = 0; + +-static int +-webcam_bind(struct usb_composite_dev *cdev) +-{ +- struct f_uvc_opts *uvc_opts; +- int ret; ++#if defined(CONFIG_USB_WEBCAM_RNDIS) ++ if(rndis_function_enable) ++ { ++ ret = rndis_bind_config(c); ++ if(ret < 0) ++ return ret; ++ } ++#endif + +- fi_uvc = usb_get_function_instance("uvc"); +- if (IS_ERR(fi_uvc)) +- return PTR_ERR(fi_uvc); ++#if defined(CONFIG_USB_WEBCAM_UVC) ++ if(uvc_function_enable) ++ { ++ ret = video_bind_config(c); ++ if(ret < 0) ++ return ret; ++ } ++#endif + +- uvc_opts = container_of(fi_uvc, struct f_uvc_opts, func_inst); ++#if defined(CONFIG_USB_WEBCAM_UAC) ++ if(uac_function_enable) ++ { ++ ret = audio_bind_config(c); ++ if(ret < 0) ++ return ret; ++ } ++#endif + +- uvc_opts->streaming_interval = streaming_interval; +- uvc_opts->streaming_maxpacket = streaming_maxpacket; +- uvc_opts->streaming_maxburst = streaming_maxburst; +- uvc_set_trace_param(trace); +- +- uvc_opts->fs_control = uvc_fs_control_cls; +- uvc_opts->ss_control = uvc_ss_control_cls; +- uvc_opts->fs_streaming = uvc_fs_streaming_cls; +- uvc_opts->hs_streaming = uvc_hs_streaming_cls; +- uvc_opts->ss_streaming = uvc_ss_streaming_cls; ++#if defined(CONFIG_USB_WEBCAM_DFU) ++ if(dfu_function_enable) ++ { ++ ret = dfu_bind_config(c); ++ if(ret < 0) ++ return ret; ++ } ++#endif + ++ return ret; ++} ++static int __init webcam_bind(struct usb_composite_dev *cdev) ++{ ++ int ret; + /* Allocate string descriptor numbers ... note that string contents + * can be overridden by the composite_dev glue. + */ + ret = usb_string_ids_tab(cdev, webcam_strings); + if (ret < 0) +- goto error; ++ return ret; + webcam_device_descriptor.iManufacturer = + webcam_strings[USB_GADGET_MANUFACTURER_IDX].id; + webcam_device_descriptor.iProduct = +@@ -404,20 +1785,99 @@ webcam_bind(struct usb_composite_dev *cdev) + webcam_config_driver.iConfiguration = + webcam_strings[STRING_DESCRIPTION_IDX].id; + ++#if defined(CONFIG_USB_WEBCAM_RNDIS) ++ if(rndis_function_enable) ++ { ++ ret = rndis_bind(cdev); ++ if(ret < 0) ++ { ++ goto error; ++ } ++ } ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UVC) ++ if(uvc_function_enable) ++ { ++ ret = video_bind(cdev); ++ if(ret < 0) ++ goto error; ++ } ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UAC) ++ if(uac_function_enable) ++ { ++ ret = audio_bind(cdev); ++ if(ret < 0) ++ goto error; ++ } ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_DFU) ++ if(dfu_function_enable) ++ { ++ ret = dfu_bind(cdev); ++ if(ret < 0) ++ goto error; ++ } ++#endif ++ + /* Register our configuration. */ + if ((ret = usb_add_config(cdev, &webcam_config_driver, +- webcam_config_bind)) < 0) ++ webcam_bind_config)) < 0) ++ { + goto error; ++ } + + usb_composite_overwrite_options(cdev, &coverwrite); + INFO(cdev, "Webcam Video Gadget\n"); + return 0; + + error: +- usb_put_function_instance(fi_uvc); ++#if defined(CONFIG_USB_WEBCAM_DFU) ++ dfu_unbind(cdev); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UAC) ++ audio_unbind(cdev); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UVC) ++ video_unbind(cdev); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_RNDIS) ++ rndis_unbind(cdev); ++#endif + return ret; + } ++static int ++webcam_unbind(struct usb_composite_dev *cdev) ++{ ++ int ret = 0; + ++#if defined(CONFIG_USB_WEBCAM_RNDIS) ++ if(rndis_function_enable) ++ ret = rndis_unbind(cdev); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UVC) ++ if(uvc_function_enable) ++ ret = video_unbind(cdev); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_UAC) ++ if(uac_function_enable) ++ ret = audio_unbind(cdev); ++#endif ++ ++#if defined(CONFIG_USB_WEBCAM_DFU) ++ if(dfu_function_enable) ++ ret = dfu_unbind(cdev); ++#endif ++ return ret; ++} + /* -------------------------------------------------------------------------- + * Driver + */ +diff --git a/drivers/usb/gadget/u_f.h b/drivers/usb/gadget/u_f.h +index 7d53a4773d1a..2f03334c6874 100644 +--- a/drivers/usb/gadget/u_f.h ++++ b/drivers/usb/gadget/u_f.h +@@ -64,7 +64,9 @@ struct usb_request *alloc_ep_req(struct usb_ep *ep, size_t len); + /* Frees a usb_request previously allocated by alloc_ep_req() */ + static inline void free_ep_req(struct usb_ep *ep, struct usb_request *req) + { ++ WARN_ON(req->buf == NULL); + kfree(req->buf); ++ req->buf = NULL; + usb_ep_free_request(ep, req); + } + +diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig +index 658b8da60915..a83f2a0da77c 100644 +--- a/drivers/usb/gadget/udc/Kconfig ++++ b/drivers/usb/gadget/udc/Kconfig +@@ -415,6 +415,7 @@ config USB_DUMMY_HCD + dynamically linked module called "dummy_hcd" and force all + gadget drivers to also be dynamically linked. + ++source drivers/sstar/usb/gadget/udc/usb20/Kconfig + # NOTE: Please keep dummy_hcd LAST so that "real hardware" appears + # first and will be selected by default. + +diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig +index 0e7cc71b34a9..0ee658364256 100644 +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -29,9 +29,9 @@ config USB_XHCI_HCD + if USB_XHCI_HCD + + config USB_XHCI_PCI +- tristate ++ tristate "USB XHCI PCI support" + depends on PCI +- default y ++ default n + + config USB_XHCI_PLATFORM + tristate "Generic xHCI driver for a platform device" +@@ -79,6 +79,14 @@ config USB_XHCI_TEGRA + Say 'Y' to enable the support for the xHCI host controller + found in NVIDIA Tegra124 and later SoCs. + ++config MSTAR_XUSB_PCIE_PLATFORM ++ bool "Enable Mstar's XHCI/PCIE combo platform" ++ depends on (MSTAR_PCIE || MSTAR_PCIE2) ++ default y ++ ---help--- ++ Say 'Y' to turn on support for Mstar xHCI/PCIE combo ++ platform. ++ This will enable PCIE functionality on the USB3.0 combo ports. + endif # USB_XHCI_HCD + + config USB_EHCI_HCD +@@ -106,6 +114,9 @@ config USB_EHCI_HCD + config USB_EHCI_ROOT_HUB_TT + bool "Root Hub Transaction Translators" + depends on USB_EHCI_HCD ++# mstar_porting_plat >>> ++ default y ++# mstar_porting_plat <<< + ---help--- + Some EHCI chips have vendor-specific extensions to integrate + transaction translators, so that no OHCI or UHCI companion +@@ -135,12 +146,18 @@ config USB_EHCI_TT_NEWSCHED + + If unsure, say Y. + ++config USB_EHCI_SUSPEND_PORT ++ bool "Support function to suspend the port" ++ depends on USB_EHCI_HCD ++ ---help--- ++ Provide suspend/reset function through ++ /sys/devices/platform/Mstar-ehci-x.x/port_suspend + if USB_EHCI_HCD + + config USB_EHCI_PCI +- tristate ++ tristate "EHCI PCI support" + depends on PCI +- default y ++ default n + + config USB_EHCI_HCD_PMC_MSP + tristate "EHCI support for on-chip PMC MSP71xx USB controller" +diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile +index 6ef785b0ea8f..cc0c7d4096ce 100644 +--- a/drivers/usb/host/Makefile ++++ b/drivers/usb/host/Makefile +@@ -1,10 +1,23 @@ + # + # Makefile for USB Host Controller Drivers + # ++#CONFIG_SSTAR_CHIP_NAME := $(subst ",,$(CONFIG_SSTAR_CHIP_NAME)) + + # tell define_trace.h where to find the xhci trace header + CFLAGS_xhci-trace.o := -I$(src) + ++EXTRA_CFLAGS += -Idrivers/sstar/usb/host ++EXTRA_CFLAGS += -Idrivers/sstar/include ++EXTRA_CFLAGS += -Idrivers/sstar/usb/host/$(CONFIG_SSTAR_CHIP_NAME) ++#EXTRA_CFLAGS += -Idrivers/sstar2/hal/$(CONFIG_SSTAR_CHIP_NAME)/usb ++#ifdef CONFIG_MSTAR_BDMA ++#EXTRA_CFLAGS += -Idrivers/sstar2/include ++#endif ++# necessary if defined(DYNAMIC_MIU_SIZE_MAPPING) ++#EXTRA_CFLAGS += -Idrivers/sstar2/include/sys/common ++#EXTRA_CFLAGS += -Idrivers/sstar2/include ++#EXTRA_CFLAGS += -Idrivers/sstar2/drv/miu ++# mstar_porting_plat <<< + fhci-y := fhci-hcd.o fhci-hub.o fhci-q.o + fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o + +@@ -24,6 +37,10 @@ endif + ifneq ($(CONFIG_USB_XHCI_RCAR), ) + xhci-plat-hcd-y += xhci-rcar.o + endif ++# mstar_porting_plat >>> ++xhci-hcd-$(CONFIG_MP_USB_MSTAR) += xhci-mstar.o ++xhci-hcd-$(CONFIG_MP_USB_MSTAR) += xhci-mstar-sysfs.o ++# mstar_porting_plat <<< + + obj-$(CONFIG_USB_WHCI_HCD) += whci/ + +diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c +old mode 100644 +new mode 100755 +index 063064801ceb..8e6e6c3f4aba +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -49,6 +50,12 @@ + #include + #endif + ++#ifdef CONFIG_MP_USB_MSTAR ++#include "usb_common_sstar.h" ++#include ++#include ++#endif ++ + /*-------------------------------------------------------------------------*/ + + /* +@@ -76,7 +83,11 @@ static const char hcd_name [] = "ehci_hcd"; + /* magic numbers that can affect system performance */ + #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ + #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ ++#if (MP_USB_MSTAR==1) && (_USB_TURN_ON_TT_THROTTLE_MODE_PATCH) ++#define EHCI_TUNE_RL_TT 4 ++#else + #define EHCI_TUNE_RL_TT 0 ++#endif + #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ + #define EHCI_TUNE_MULT_TT 1 + /* +@@ -85,7 +96,12 @@ static const char hcd_name [] = "ehci_hcd"; + * code). In an attempt to avoid trouble, we will use a minimum scheduling + * length of 512 frames instead of 256. + */ ++ ++#if (MP_USB_MSTAR==1) ++#define EHCI_TUNE_FLS 0 /* 1024-frame schedule */ ++#else + #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ ++#endif + + /* Initial IRQ latency: faster than hw default */ + static int log2_irq_thresh = 0; // 0 to 6 +@@ -93,15 +109,33 @@ module_param (log2_irq_thresh, int, S_IRUGO); + MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); + + /* initial park setting: slower than hw default */ ++#if (MP_USB_MSTAR==1) && defined(ENABLE_12US_EOF1) ++static unsigned park = 3; ++#else + static unsigned park = 0; ++#endif + module_param (park, uint, S_IRUGO); + MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); + + /* for flakey hardware, ignore overcurrent indicators */ ++#if (MP_USB_MSTAR==1) //tony ignore oc ++static bool ignore_oc = 1; ++#else + static bool ignore_oc; ++#endif ++#if MP_USB_MSTAR ++int ehci_monitor_status = 0; ++struct task_struct *ehci_monitor_task; ++struct usb_hcd *ehci_mstar_hcd; ++struct platform_device *ehci_hcd_mstar_platform_dev; ++int vbus_gpio = -1; ++#endif ++ + module_param (ignore_oc, bool, S_IRUGO); + MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); +- ++#if MP_USB_MSTAR ++#define STS_ERR_RXACTIVE (1<<6) ++#endif + #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) + + /*-------------------------------------------------------------------------*/ +@@ -129,10 +163,32 @@ static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci) + return uf; + } + ++#if (MP_USB_MSTAR==1) ++static unsigned ehci_mstar_read_frame_index(struct ehci_hcd *ehci) ++{ ++ struct usb_hcd *hcd = ehci_to_hcd(ehci); ++ unsigned int frame_index; ++ ++ frame_index = hcd->ms_flag >> 16; ++ frame_index += 800; //Jump 100ms ++ if (frame_index > 0x3FFF) ++ frame_index = 0; ++ ++ hcd->ms_flag &= 0x0000FFFF; ++ hcd->ms_flag |= frame_index << 16; ++ ++ return (unsigned) frame_index; ++} ++#endif ++ + static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) + { + if (ehci->frame_index_bug) + return ehci_moschip_read_frame_index(ehci); ++#if (MP_USB_MSTAR==1) ++ if (ehci_to_hcd(ehci)->ms_flag & MS_FLAG_SW_FRM_IDX) ++ return ehci_mstar_read_frame_index(ehci); ++#endif + return ehci_readl(ehci, &ehci->regs->frame_index); + } + +@@ -179,10 +235,14 @@ EXPORT_SYMBOL_GPL(ehci_handshake); + /* check TDI/ARC silicon is in host mode */ + static int tdi_in_host_mode (struct ehci_hcd *ehci) + { ++#if (MP_USB_MSTAR==1) ++ return 1; ++#else + u32 tmp; + + tmp = ehci_readl(ehci, &ehci->regs->usbmode); + return (tmp & 3) == USBMODE_CM_HC; ++#endif + } + + /* +@@ -222,6 +282,9 @@ static int ehci_halt (struct ehci_hcd *ehci) + /* put TDI/ARC silicon into EHCI mode */ + static void tdi_reset (struct ehci_hcd *ehci) + { ++#if (MP_USB_MSTAR==1) ++ ++#else + u32 tmp; + + tmp = ehci_readl(ehci, &ehci->regs->usbmode); +@@ -233,6 +296,7 @@ static void tdi_reset (struct ehci_hcd *ehci) + if (ehci_big_endian_mmio(ehci)) + tmp |= USBMODE_BE; + ehci_writel(ehci, tmp, &ehci->regs->usbmode); ++#endif + } + + /* +@@ -257,6 +321,11 @@ int ehci_reset(struct ehci_hcd *ehci) + retval = ehci_handshake(ehci, &ehci->regs->command, + CMD_RESET, 0, 250 * 1000); + ++#if (MP_USB_MSTAR==1) && defined(ENABLE_UHC_RUN_BIT_ALWAYS_ON_ECO) ++ /* Don't close RUN bit when device disconnect */ ++ ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->hcmisc) | BIT7, &ehci->regs->hcmisc); ++#endif ++ + if (ehci->has_hostpc) { + ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, + &ehci->regs->usbmode_ex); +@@ -400,6 +469,9 @@ static void ehci_work (struct ehci_hcd *ehci) + * it reports urb completions. this flag guards against bogus + * attempts at re-entrant schedule scanning. + */ ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ Chip_Flush_MIU_Pipe(); //Flush Read buffer when H/W finished ++#endif + if (ehci->scanning) { + ehci->need_rescan = true; + return; +@@ -516,10 +588,15 @@ static int ehci_init(struct usb_hcd *hcd) + return retval; + + /* controllers may cache some of the periodic schedule ... */ ++#if (MP_USB_MSTAR==1) //tony add for FUSB200 ++ ehci->i_thresh = 8; ++ ehci->periodic_count = 0; ++#else + if (HCC_ISOC_CACHE(hcc_params)) // full frame cache + ehci->i_thresh = 0; + else // N microframes cached + ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); ++#endif + + /* + * dedicate a qh for the async ring head, since we couldn't unlink +@@ -584,7 +661,10 @@ static int ehci_init(struct usb_hcd *hcd) + static int ehci_run (struct usb_hcd *hcd) + { + struct ehci_hcd *ehci = hcd_to_ehci (hcd); ++#if (MP_USB_MSTAR==1) // tony ignore oc ++#else + u32 temp; ++#endif + u32 hcc_params; + + hcd->uses_new_polling = 1; +@@ -646,14 +726,15 @@ static int ehci_run (struct usb_hcd *hcd) + up_write(&ehci_cf_port_reset_rwsem); + ehci->last_periodic_enable = ktime_get_real(); + ++#if (MP_USB_MSTAR==0) // tony ignore oc + temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); + ehci_info (ehci, + "USB %x.%x started, EHCI %x.%02x%s\n", + ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), + temp >> 8, temp & 0xff, + ignore_oc ? ", overcurrent ignored" : ""); +- +- ehci_writel(ehci, INTR_MASK, ++#endif ++ ehci_writel(ehci, INTR_MASK | STS_ERR_RXACTIVE, + &ehci->regs->intr_enable); /* Turn On Interrupts */ + + /* GRR this is run-once init(), being done every time the HC starts. +@@ -727,7 +808,7 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) + * We don't use STS_FLR, but some controllers don't like it to + * remain on, so mask it out along with the other status bits. + */ +- masked_status = status & (INTR_MASK | STS_FLR); ++ masked_status = status & (INTR_MASK | STS_FLR | STS_ERR_RXACTIVE); + + /* Shared IRQ? */ + if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { +@@ -798,6 +879,18 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) + pstatus = ehci_readl(ehci, + &ehci->regs->port_status[i]); + ++#if (MP_USB_MSTAR==1) ++ /* Clear port enable bit when root device disconnect ++ * Patch for hub+device hot plug frequency then lost disconnect event issue ++ */ ++ if (pstatus & PORT_CSC) ++ { ++ pstatus &= ~(PORT_PE|PORT_CSC|PORT_PEC); ++ ehci_writel(ehci, pstatus, &ehci->regs->port_status[i]); ++ //printk("[IRQ]Clear PORT_PE\n"); ++ } ++#endif ++ + if (pstatus & PORT_OWNER) + continue; + if (!(test_bit(i, &ehci->suspended_ports) && +@@ -819,7 +912,19 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) + mod_timer(&hcd->rh_timer, ehci->reset_done[i]); + } + } +- ++ #if MP_USB_MSTAR ++ if (status & STS_ERR_RXACTIVE){ ++ ehci_monitor_status = 1; ++ ehci_mstar_hcd = hcd; ++ ehci_hcd_mstar_platform_dev = container_of(hcd->self.controller, struct platform_device, dev); ++ printk("ERR_INT_SOF_RXACTIVE issue @platform:%p\n", ehci_hcd_mstar_platform_dev); ++ #if _USB_VBUS_RESET_PATCH ++ if (ehci_hcd_mstar_platform_dev) ++ vbus_gpio = vbus_gpio_of_parse_and_map(ehci_hcd_mstar_platform_dev->dev.of_node); ++ gpio_direction_output(vbus_gpio, 0); ++ #endif ++ } ++ #endif + /* PCI errors [4.15.2.4] */ + if (unlikely ((status & STS_FATAL) != 0)) { + ehci_err(ehci, "fatal error\n"); +@@ -848,6 +953,20 @@ dead: + return IRQ_HANDLED; + } + ++#if (MP_USB_MSTAR==1) ++static struct usb_device * ms_get_root_dev (struct usb_device *udev) ++{ ++ struct usb_device *iter; ++ ++ iter = udev; ++ while (iter != NULL && iter->parent != udev->bus->root_hub) ++ iter = iter->parent; ++ ++ BUG_ON(iter == NULL); ++ return iter; ++} ++#endif ++ + /*-------------------------------------------------------------------------*/ + + /* +@@ -894,6 +1013,11 @@ static int ehci_urb_enqueue ( + case PIPE_ISOCHRONOUS: + if (urb->dev->speed == USB_SPEED_HIGH) + return itd_submit (ehci, urb, mem_flags); ++#if (MP_USB_MSTAR==1) ++ /* Colin, patch for not real split-transaction mode */ ++ else if (ms_get_root_dev(urb->dev)->speed != USB_SPEED_HIGH) ++ return itd_submit (ehci, urb, mem_flags); ++#endif + else + return sitd_submit (ehci, urb, mem_flags); + } +@@ -909,6 +1033,9 @@ static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + struct ehci_qh *qh; + unsigned long flags; + int rc; ++ #if (MP_USB_MSTAR==1) ++ unsigned int frm_idx = 0xFFFF; ++ #endif + + spin_lock_irqsave (&ehci->lock, flags); + rc = usb_hcd_check_unlink_urb(hcd, urb, status); +@@ -921,6 +1048,41 @@ static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + * Just wait until they complete normally or their + * time slot expires. + */ ++#if (MP_USB_MSTAR==1) ++ ++ if ( !(ehci_readl(ehci, &ehci->regs->port_status[0]) & BIT0) || ++ ehci_readl(ehci, &ehci->regs->port_status[0]) & BIT1 ) ++ { ++ ++ while (atomic_read(&urb->use_count) > 0) ++ { ++ //Check port disconnect ++ if ( !(hcd->ms_flag & MS_FLAG_SW_FRM_IDX) && ++ (frm_idx != 0xFFFF) && ++ (frm_idx == ehci_readl(ehci, &ehci->regs->frame_index)) ) ++ { ++ printk("[USB][%s] EHCI SW frame index start...\n", __func__); ++ hcd->ms_flag |= MS_FLAG_SW_FRM_IDX; ++ hcd->ms_flag &= 0x0000FFFF; ++ hcd->ms_flag |= ehci_readl(ehci, &ehci->regs->frame_index) << 16; ++ } ++ ++ if (hcd->ms_flag & MS_FLAG_SW_FRM_IDX) ++ { ++ if (ehci->isoc_count > 0) ++ turn_on_sitd_watchdog(ehci); ++ } ++ ++ frm_idx = ehci_readl(ehci, &ehci->regs->frame_index); ++ spin_unlock_irqrestore (&ehci->lock, flags); ++ schedule_timeout_uninterruptible(1); ++ spin_lock_irqsave (&ehci->lock, flags); ++ ++ } ++ hcd->ms_flag &= ~MS_FLAG_SW_FRM_IDX; ++ ++ } ++#endif + } else { + qh = (struct ehci_qh *) urb->hcpriv; + qh->unlink_reason |= QH_UNLINK_REQUESTED; +@@ -959,6 +1121,9 @@ ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) + struct ehci_hcd *ehci = hcd_to_ehci (hcd); + unsigned long flags; + struct ehci_qh *qh; ++#if (MP_USB_MSTAR==1) ++ unsigned int frm_idx = 0xFFFF; ++#endif + + /* ASSERT: any requests/urbs are being unlinked */ + /* ASSERT: nobody can be submitting urbs for this any more */ +@@ -976,7 +1141,36 @@ rescan: + struct ehci_iso_stream *stream = ep->hcpriv; + + if (!list_empty(&stream->td_list)) ++#if (MP_USB_MSTAR==1) ++ { ++ //Check port disconnect ++ if ( !(ehci_readl(ehci, &ehci->regs->port_status[0]) & BIT0) || ++ ehci_readl(ehci, &ehci->regs->port_status[0]) & BIT1 ) ++ { ++ if ( !(hcd->ms_flag & MS_FLAG_SW_FRM_IDX) && ++ (frm_idx != 0xFFFF) && ++ (frm_idx == ehci_readl(ehci, &ehci->regs->frame_index)) ) ++ { ++ printk("[USB][%s] EHCI SW frame index start...\n", __func__); ++ hcd->ms_flag |= MS_FLAG_SW_FRM_IDX; ++ hcd->ms_flag &= 0x0000FFFF; ++ hcd->ms_flag |= ehci_readl(ehci, &ehci->regs->frame_index) << 16; ++ } ++ ++ if (hcd->ms_flag & MS_FLAG_SW_FRM_IDX) ++ { ++ if (ehci->isoc_count > 0) ++ turn_on_sitd_watchdog(ehci); ++ } ++ ++ frm_idx = ehci_readl(ehci, &ehci->regs->frame_index); ++ } ++ ++ goto idle_timeout; ++ } ++#else + goto idle_timeout; ++#endif + + /* BUG_ON(!list_empty(&stream->free_list)); */ + reserve_release_iso_bandwidth(ehci, stream, -1); +@@ -1023,6 +1217,9 @@ idle_timeout: + break; + } + done: ++#if (MP_USB_MSTAR==1) ++ hcd->ms_flag &= ~MS_FLAG_SW_FRM_IDX; ++#endif + ep->hcpriv = NULL; + spin_unlock_irqrestore (&ehci->lock, flags); + } +@@ -1308,6 +1505,66 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ehci_mv_driver + #endif + ++#if (MP_USB_MSTAR==1) ++#include "ehci-mstar.c" ++#define PLATFORM_DRIVER ehci_hcd_mstar_driver ++#define SECOND_PLATFORM_DRIVER second_ehci_hcd_mstar_driver ++#define THIRD_PLATFORM_DRIVER third_ehci_hcd_mstar_driver ++#define FOURTH_PLATFORM_DRIVER fourth_ehci_hcd_mstar_driver ++#define FIFTH_PLATFORM_DRIVER fifth_ehci_hcd_mstar_driver ++#endif ++ ++#if (MP_USB_MSTAR==1) ++static int ehci_monitor_thread(void *data) ++{ ++ printk(KERN_INFO "ehci monitor start running\n"); ++ while(1) ++ { ++ if (ehci_monitor_status) { ++ #if _USB_VBUS_RESET_PATCH ++ gpio_direction_output(vbus_gpio, 1); ++ #endif ++ ehci_monitor_status = 0; ++ if (ehci_mstar_hcd) { ++ printk(KERN_EMERG "ERR_INT_SOF_RXACTIVE occur\n"); ++ usb_remove_hcd(ehci_mstar_hcd); ++ usb_put_hcd(ehci_mstar_hcd); ++ ++ if (ehci_hcd_mstar_platform_dev) ++ { ++ ehci_hcd_mstar_drv_probe(ehci_hcd_mstar_platform_dev); ++ } ++ else ++ printk(KERN_EMERG "ehci_hcd_mstar_platform_dev null\n"); ++ } else { ++ printk(KERN_EMERG "ehci_mstar_hcd null\n"); ++ } ++ } ++ msleep(100); ++ } ++ return 0; ++} ++ ++static int __init ehci_monitor_thread_init(void) ++{ ++ ehci_monitor_task = kthread_create(ehci_monitor_thread, NULL, "ehci_monitor"); ++ if (IS_ERR(ehci_monitor_task)) ++ { ++ printk(KERN_EMERG "Create ehci monitor thread fail\n"); ++ return PTR_ERR(ehci_monitor_task); ++ } ++ wake_up_process(ehci_monitor_task); ++ ++ return 0; ++} ++ ++static void __exit ehci_monitor_thread_exit(void) ++{ ++ kthread_stop(ehci_monitor_task); ++ return; ++} ++#endif ++ + static int __init ehci_hcd_init(void) + { + int retval = 0; +@@ -1315,6 +1572,10 @@ static int __init ehci_hcd_init(void) + if (usb_disabled()) + return -ENODEV; + ++#if (MP_USB_MSTAR==1) ++ ehci_init_driver(&ehci_mstar_hc_driver, NULL); ++ ehci_monitor_thread_init(); ++#endif + printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); + set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); + if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || +@@ -1336,10 +1597,42 @@ static int __init ehci_hcd_init(void) + #endif + + #ifdef PLATFORM_DRIVER ++#if (MP_USB_MSTAR==1) ++ printk("Mstar_ehc_init version:%s\n", EHCI_MSTAR_VERSION); ++ ++ #if defined(DYNAMIC_MIU_SIZE_MAPPING) ++ MIU_dynamic_size_init(); ++ #endif ++ ++ #if !defined(DISABLE_SECOND_EHC) ++ retval = platform_driver_register(&SECOND_PLATFORM_DRIVER); ++ if (retval < 0) ++ goto clean0; ++ #endif ++ retval = platform_driver_register(&PLATFORM_DRIVER); ++ if (retval < 0) ++ goto clean0; ++ #ifdef ENABLE_THIRD_EHC ++ retval = platform_driver_register(&THIRD_PLATFORM_DRIVER); ++ if (retval < 0) ++ goto clean0; ++ #endif ++ #ifdef ENABLE_FOURTH_EHC ++ retval = platform_driver_register(&FOURTH_PLATFORM_DRIVER); ++ if (retval < 0) ++ goto clean0; ++ #endif ++ #ifdef ENABLE_FIFTH_EHC ++ retval = platform_driver_register(&FIFTH_PLATFORM_DRIVER); ++ if (retval < 0) ++ goto clean0; ++ #endif ++#else + retval = platform_driver_register(&PLATFORM_DRIVER); + if (retval < 0) + goto clean0; + #endif ++#endif + + #ifdef PS3_SYSTEM_BUS_DRIVER + retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); +@@ -1395,7 +1688,24 @@ static void __exit ehci_hcd_cleanup(void) + platform_driver_unregister(&OF_PLATFORM_DRIVER); + #endif + #ifdef PLATFORM_DRIVER ++#if (MP_USB_MSTAR==1) ++ ehci_monitor_thread_exit(); + platform_driver_unregister(&PLATFORM_DRIVER); ++#if !defined(DISABLE_SECOND_EHC) ++ platform_driver_unregister(&SECOND_PLATFORM_DRIVER); ++#endif ++#ifdef ENABLE_THIRD_EHC ++ platform_driver_unregister(&THIRD_PLATFORM_DRIVER); ++#endif ++#ifdef ENABLE_FOURTH_EHC ++ platform_driver_unregister(&FOURTH_PLATFORM_DRIVER); ++#endif ++#ifdef ENABLE_FIFTH_EHC ++ platform_driver_unregister(&FIFTH_PLATFORM_DRIVER); ++#endif ++#else ++ platform_driver_unregister(&PLATFORM_DRIVER); ++#endif + #endif + #ifdef PS3_SYSTEM_BUS_DRIVER + ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); +diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c +index 74f62d68f013..11d325bab0b4 100644 +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -29,6 +29,9 @@ + /*-------------------------------------------------------------------------*/ + #include + ++#ifndef MP_USB_MSTAR ++#include ++#endif + #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) + + #ifdef CONFIG_PM +@@ -366,6 +369,9 @@ static int ehci_bus_suspend (struct usb_hcd *hcd) + + done: + ehci->next_statechange = jiffies + msecs_to_jiffies(10); ++#if (MP_USB_MSTAR==1) ++ disable_irq(hcd->irq); //20120301, for system suspend-resume ++#endif + ehci->enabled_hrtimer_events = 0; + ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT; + spin_unlock_irq (&ehci->lock); +@@ -506,6 +512,9 @@ static int ehci_bus_resume (struct usb_hcd *hcd) + spin_lock_irq(&ehci->lock); + if (ehci->shutdown) + goto shutdown; ++#if (MP_USB_MSTAR==1) ++ enable_irq(hcd->irq); //20150226, suspend fail cause ehci_hcd_mstar_drv_resume() not running ++#endif + ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable); + (void) ehci_readl(ehci, &ehci->regs->intr_enable); + spin_unlock_irq(&ehci->lock); +@@ -1216,6 +1225,15 @@ int ehci_hub_control( + * which can be fine if this root hub has a + * transaction translator built in. + */ ++#if (MP_USB_MSTAR==1) ++ if (!(temp & PORT_CONNECT)) ++ { ++ printk("[USB] device has gone before bus reset\n"); ++ retval = -ENODEV; ++ goto error_exit; ++ } ++ { ++#else + if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT + && !ehci_is_TDI(ehci) + && PORT_USB11 (temp)) { +@@ -1224,6 +1242,7 @@ int ehci_hub_control( + wIndex + 1); + temp |= PORT_OWNER; + } else { ++#endif + temp |= PORT_RESET; + temp &= ~PORT_PE; + +diff --git a/drivers/usb/host/ehci-mem.c b/drivers/usb/host/ehci-mem.c +index 4de43011df23..4ac4a99b5847 100644 +--- a/drivers/usb/host/ehci-mem.c ++++ b/drivers/usb/host/ehci-mem.c +@@ -35,6 +35,9 @@ + + /* Allocate the key transfer structures from the previously allocated pool */ + ++#ifndef MP_USB_MSTAR ++#include ++#endif + static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd, + dma_addr_t dma) + { +@@ -52,6 +55,9 @@ static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags) + dma_addr_t dma; + + qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ dma = BUS2PA(dma); ++#endif + if (qtd != NULL) { + ehci_qtd_init(ehci, qtd, dma); + } +@@ -60,6 +66,9 @@ static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags) + + static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd) + { ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ qtd->qtd_dma = PA2BUS(qtd->qtd_dma); ++#endif + dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma); + } + +@@ -73,6 +82,9 @@ static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh) + } + if (qh->dummy) + ehci_qtd_free (ehci, qh->dummy); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ qh->qh_dma = PA2BUS(qh->qh_dma); ++#endif + dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma); + kfree(qh); + } +@@ -87,6 +99,9 @@ static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags) + goto done; + qh->hw = (struct ehci_qh_hw *) + dma_pool_alloc(ehci->qh_pool, flags, &dma); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ dma = BUS2PA(dma); ++#endif + if (!qh->hw) + goto fail; + memset(qh->hw, 0, sizeof *qh->hw); +@@ -104,6 +119,9 @@ static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags) + done: + return qh; + fail1: ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ qh->qh_dma = PA2BUS(qh->qh_dma); ++#endif + dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma); + fail: + kfree(qh); +@@ -137,6 +155,10 @@ static void ehci_mem_cleanup (struct ehci_hcd *ehci) + dma_pool_destroy(ehci->sitd_pool); + ehci->sitd_pool = NULL; + ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ if (ehci->periodic) ++ ehci->periodic_dma = PA2BUS(ehci->periodic_dma); ++#endif + if (ehci->periodic) + dma_free_coherent (ehci_to_hcd(ehci)->self.controller, + ehci->periodic_size * sizeof (u32), +@@ -157,7 +179,11 @@ static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) + ehci->qtd_pool = dma_pool_create ("ehci_qtd", + ehci_to_hcd(ehci)->self.controller, + sizeof (struct ehci_qtd), ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ 128 /* byte alignment (for hw parts) */, ++#else + 32 /* byte alignment (for hw parts) */, ++#endif + 4096 /* can't cross 4K */); + if (!ehci->qtd_pool) { + goto fail; +@@ -167,7 +193,11 @@ static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) + ehci->qh_pool = dma_pool_create ("ehci_qh", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_qh_hw), ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ 128 /* byte alignment (for hw parts) */, ++#else + 32 /* byte alignment (for hw parts) */, ++#endif + 4096 /* can't cross 4K */); + if (!ehci->qh_pool) { + goto fail; +@@ -181,7 +211,11 @@ static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) + ehci->itd_pool = dma_pool_create ("ehci_itd", + ehci_to_hcd(ehci)->self.controller, + sizeof (struct ehci_itd), ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ 128 /* byte alignment (for hw parts) */, ++#else + 32 /* byte alignment (for hw parts) */, ++#endif + 4096 /* can't cross 4K */); + if (!ehci->itd_pool) { + goto fail; +@@ -191,7 +225,11 @@ static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) + ehci->sitd_pool = dma_pool_create ("ehci_sitd", + ehci_to_hcd(ehci)->self.controller, + sizeof (struct ehci_sitd), ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ 128 /* byte alignment (for hw parts) */, ++#else + 32 /* byte alignment (for hw parts) */, ++#endif + 4096 /* can't cross 4K */); + if (!ehci->sitd_pool) { + goto fail; +@@ -202,6 +240,9 @@ static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) + dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller, + ehci->periodic_size * sizeof(__le32), + &ehci->periodic_dma, flags); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ ehci->periodic_dma = BUS2PA(ehci->periodic_dma); ++#endif + if (ehci->periodic == NULL) { + goto fail; + } +diff --git a/drivers/usb/host/ehci-mstar-sysfs.c b/drivers/usb/host/ehci-mstar-sysfs.c +new file mode 100644 +index 000000000000..0754e7c1f47b +--- /dev/null ++++ b/drivers/usb/host/ehci-mstar-sysfs.c +@@ -0,0 +1,79 @@ ++/* ++* ehci-mstar-sysfs.c- Sigmastar ++* ++* Copyright (C) 2018 Sigmastar Technology Corp. ++* ++* Author: raul.wang ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#if (MP_USB_MSTAR==1) && defined(CONFIG_USB_EHCI_SUSPEND_PORT) ++static ssize_t show_port_suspend(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct ehci_hcd *ehci; ++ u32 __iomem *reg; ++ u32 status; ++ unsigned isSuspend; ++ ++ ehci = hcd_to_ehci(bus_to_hcd(dev_get_drvdata(dev))); ++ reg = &ehci->regs->port_status[0]; ++ status = ehci_readl(ehci, reg); ++ if (status & 0x80) ++ isSuspend = 1; ++ else ++ isSuspend = 0; ++ ++ return sprintf(buf, "%d\n", isSuspend);; ++} ++ ++static ssize_t set_port_suspend(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct ehci_hcd *ehci; ++ ssize_t ret; ++ int config; ++ u32 __iomem *reg; ++ u32 status; ++ ++ if ( sscanf(buf, "%d", &config) != 1 ) ++ return -EINVAL; ++ ++ ehci = hcd_to_ehci(bus_to_hcd(dev_get_drvdata(dev))); ++ reg = &ehci->regs->port_status[0]; ++ status = ehci_readl(ehci, reg); ++ ++ if (config == 1) ++ { ++ if ( !(status & PORT_SUSPEND) && (status & PORT_CONNECT) ) ++ { ++ //printk("ehci suspend\n"); ++ ehci_writel(ehci, status | PORT_SUSPEND, reg); ++ } ++ } ++ else ++ { ++ if ( status & PORT_SUSPEND ) ++ { ++ //printk("ehci port reset\n"); ++ ehci_writel(ehci, status | (PORT_RESET |PORT_RESUME), reg); ++ msleep(70); ++ ehci_writel(ehci, status & ~(PORT_RESET|PORT_RESUME), reg); ++ } ++ } ++ ++ ret = count; ++ return ret; ++} ++static DEVICE_ATTR(port_suspend, 0644, show_port_suspend, set_port_suspend); ++#endif +diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c +index eca3710d8fc4..0df3e81bf351 100644 +--- a/drivers/usb/host/ehci-q.c ++++ b/drivers/usb/host/ehci-q.c +@@ -17,6 +17,13 @@ + */ + + /* this file is part of ehci-hcd.c */ ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++#include "ms_platform.h" ++#endif + + /*-------------------------------------------------------------------------*/ + +@@ -217,6 +224,9 @@ static int qtd_copy_status ( + /* serious "can't proceed" faults reported by the hardware */ + if (token & QTD_STS_HALT) { + if (token & QTD_STS_BABBLE) { ++#if (MP_USB_MSTAR==1) ++ printk("QTD_STS_BABBLE :%x\n",token); ++#endif + /* FIXME "must" disable babbling device's port too */ + status = -EOVERFLOW; + /* CERR nonzero + halt --> stall */ +@@ -228,6 +238,9 @@ static int qtd_copy_status ( + * Which to test first is rather arbitrary. + */ + } else if (token & QTD_STS_MMF) { ++#if (MP_USB_MSTAR==1) ++ printk("QTD_STS_MMF!\n"); ++#endif + /* fs/ls interrupt xfer missed the complete-split */ + status = -EPROTO; + } else if (token & QTD_STS_DBE) { +@@ -411,7 +424,27 @@ qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh) + stopped = 1; + qh->unlink_reason |= QH_UNLINK_SHORT_READ; + } ++#if (MP_USB_MSTAR==1) && (_USB_SPLIT_MDATA_BLOCKING_PATCH) ++ else if((token & QTD_STS_STS) /* SplitXstate = 1 in qTD */ ++ && (hc32_to_cpu(ehci, qh->hw->hw_info2) & QH_HUBADDR) /* hub addr */ ++ && (hc32_to_cpu(ehci, qh->hw->hw_info2) & QH_CMASK) /* split complite mask */ ++ && usb_pipeint(urb->pipe) && usb_pipein(urb->pipe) /* Interrupt IN transaction */ ++ && (urb->dev->speed == USB_SPEED_LOW || urb->dev->speed == USB_SPEED_FULL)) ++ { ++ u32 hw_token; ++ ++ hw_token = hc32_to_cpu(ehci, qh->hw->hw_token); ++ /* ++ * MDATA: should toggle ++ * zero-size pkg: should "not" toggle ++ */ ++ //hw_token ^= QTD_TOGGLE; ++ hw_token &= (u32)(~QTD_STS_STS); + ++ wmb (); ++ qh->hw->hw_token = cpu_to_hc32(ehci, hw_token); ++ } ++#endif + /* stop scanning when we reach qtds the hc is using */ + } else if (likely (!stopped + && ehci->rh_state >= EHCI_RH_RUNNING)) { +@@ -661,6 +694,13 @@ qh_urb_transaction ( + for (;;) { + int this_qtd_len; + ++#if (MP_USB_MSTAR==1) && (_USB_SHORT_PACKET_LOSE_INT_PATCH) ++ if (is_input && usb_pipebulk (urb->pipe) && ++ (!(urb->transfer_flags & URB_NO_INTERRUPT)) && (!(urb->transfer_flags & URB_SHORT_NOT_OK))) ++ { ++ token |= QTD_IOC; ++ } ++#endif + this_qtd_len = qtd_fill(ehci, qtd, buf, this_sg_len, token, + maxpacket); + this_sg_len -= this_qtd_len; +@@ -1070,7 +1110,9 @@ static struct ehci_qh *qh_append_tds ( + */ + token = qtd->hw_token; + qtd->hw_token = HALT_BIT(ehci); +- ++#if (MP_USB_MSTAR==1) && _USB_FRIENDLY_CUSTOMER_PATCH ++ wmb (); ++#endif + dummy = qh->dummy; + + dma = dummy->qtd_dma; +@@ -1150,6 +1192,10 @@ submit_async ( + */ + if (likely (qh->qh_state == QH_STATE_IDLE)) + qh_link_async(ehci, qh); ++ ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ Chip_Flush_MIU_Pipe(); ++#endif + done: + spin_unlock_irqrestore (&ehci->lock, flags); + if (unlikely (qh == NULL)) +@@ -1279,6 +1325,13 @@ static void single_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh) + prev->qh_next = qh->qh_next; + if (ehci->qh_scan_next == qh) + ehci->qh_scan_next = qh->qh_next.qh; ++ ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ /* must make sure the qh is unlinked before send IAAD to HC. ++ * wifi driver uses urb with 32KB buffer for iperf test would makes bulk-in timeout. ++ */ ++ Chip_Flush_MIU_Pipe(); ++#endif + } + + static void start_iaa_cycle(struct ehci_hcd *ehci) +@@ -1408,6 +1461,9 @@ static void end_unlink_async(struct ehci_hcd *ehci) + return; + + /* Process the idle QHs */ ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ Chip_Flush_MIU_Pipe(); //Flush Read buffer when H/W finished ++#endif + ehci->async_unlinking = true; + while (!list_empty(&ehci->async_idle)) { + qh = list_first_entry(&ehci->async_idle, struct ehci_qh, +diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c +index 1dfe54f14737..3a92796bbb0c 100644 +--- a/drivers/usb/host/ehci-sched.c ++++ b/drivers/usb/host/ehci-sched.c +@@ -33,6 +33,9 @@ + * It keeps track of every ITD (or SITD) that's linked, and holds enough + * pre-calculated schedule data to make appending to the queue be quick. + */ ++#ifndef MP_USB_MSTAR ++#include ++#endif + + static int ehci_get_frame(struct usb_hcd *hcd); + +@@ -591,7 +594,7 @@ static void qh_link_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) + qh->hw->hw_next = *hw_p; + wmb(); + prev->qh = qh; +- *hw_p = QH_NEXT(ehci, qh->qh_dma); ++ *hw_p = QH_NEXT (ehci, qh->qh_dma); + } + } + qh->qh_state = QH_STATE_LINKED; +@@ -979,7 +982,9 @@ static int intr_submit( + + /* ... update usbfs periodic stats */ + ehci_to_hcd(ehci)->self.bandwidth_int_reqs++; +- ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ Chip_Flush_MIU_Pipe(); ++#endif + done: + if (unlikely(status)) + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); +@@ -1092,13 +1097,42 @@ iso_stream_init( + stream->ps.period = urb->interval >> 3; + stream->bandwidth = stream->ps.usecs * 8 / + stream->ps.bw_uperiod; ++#if (MP_USB_MSTAR==1) ++ } else if ((ehci_readl(ehci, &ehci->regs->bmcs) & 0x0600) != 0x0400) //Colin, patch for not real split-transaction mode ++ { ++ unsigned multi = 1; ++ ++ maxp = max_packet(maxp); ++ buf1 |= maxp; + ++ stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum); // linux warning as above ++ stream->buf1 = cpu_to_hc32(ehci, buf1); ++ stream->buf2 = cpu_to_hc32(ehci, multi); ++ ++ stream->ps.usecs = HS_USECS_ISO (maxp); ++ ++ /* period for bandwidth allocation */ ++ tmp = min_t(unsigned, EHCI_BANDWIDTH_FRAMES, ++ 1 << (urb->ep->desc.bInterval - 1)); ++ ++ /* Allow urb->interval to override */ ++ stream->ps.bw_period = min_t(unsigned, tmp, urb->interval); ++ stream->ps.bw_uperiod = stream->ps.bw_period << 3; ++ stream->ps.period = urb->interval; ++ stream->uperiod = urb->interval << 3; ++ stream->bandwidth = stream->ps.usecs * 1; // 1st uFrame ++ stream->bandwidth /= urb->interval << 3; ++#endif + } else { + u32 addr; + int think_time; + int hs_transfers; + + addr = dev->ttport << 24; ++ ++#if (MP_USB_MSTAR==1) ++ if (dev->tt) ++#endif + if (!ehci_is_TDI(ehci) + || (dev->tt->hub != + ehci_to_hcd(ehci)->self.root_hub)) +@@ -1278,7 +1312,11 @@ itd_urb_transaction( + + itd_sched_init(ehci, sched, stream, urb); + ++#if (MP_USB_MSTAR==1) ++ if ((urb->interval < 8) && stream->highspeed) ++#else + if (urb->interval < 8) ++#endif + num_itds = 1 + (sched->span + 7) / 8; + else + num_itds = urb->number_of_packets; +@@ -1303,6 +1341,10 @@ itd_urb_transaction( + spin_unlock_irqrestore(&ehci->lock, flags); + itd = dma_pool_alloc(ehci->itd_pool, mem_flags, + &itd_dma); ++/* tony.yu map between PHY addr & BUS addr */ ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ itd_dma = BUS2PA(itd_dma); ++#endif + spin_lock_irqsave(&ehci->lock, flags); + if (!itd) { + iso_sched_free(stream, sched); +@@ -1539,6 +1581,13 @@ iso_stream_schedule( + if (stream->highspeed) { + if (itd_slot_ok(ehci, stream, start)) + done = 1; ++#if (MP_USB_MSTAR==1) ++ } else if ((ehci_readl(ehci, &ehci->regs->bmcs) & 0x0600) != 0x0400) { //Colin, patch for not real split-transaction mode ++ if ((start % 8) >= 1) ++ continue; ++ if (itd_slot_ok(ehci, stream, start)) ++ done = 1; ++#endif + } else { + if ((start % 8) >= 6) + continue; +@@ -1587,7 +1636,11 @@ iso_stream_schedule( + * Use ehci->last_iso_frame as the base. There can't be any + * TDs scheduled for earlier than that. + */ ++#if (MP_USB_MSTAR==1) ++ base = stream->last_iso_frame << 3; ++#else + base = ehci->last_iso_frame << 3; ++#endif + next = (next - base) & (mod - 1); + start = (stream->next_uframe - base) & (mod - 1); + +@@ -1614,8 +1667,12 @@ iso_stream_schedule( + if (likely(!empty || start <= now2 + period)) { + + /* URB_ISO_ASAP: make sure that start >= next */ ++#if (MP_USB_MSTAR==1) ++ if (unlikely(start < next)) ++#else + if (unlikely(start < next && + (urb->transfer_flags & URB_ISO_ASAP))) ++#endif + goto do_ASAP; + + /* Otherwise use start, if it's not in the past */ +@@ -1669,6 +1726,9 @@ iso_stream_schedule( + start += base; + stream->next_uframe = (start + skip) & (mod - 1); + ++#if (MP_USB_MSTAR==1) ++ stream->last_iso_frame = now >> 3; ++#endif + /* report high speed start in uframes; full speed, in frames */ + urb->start_frame = start & (mod - 1); + if (!stream->highspeed) +@@ -1676,6 +1736,9 @@ iso_stream_schedule( + return status; + + fail: ++#if (MP_USB_MSTAR==1) ++ stream->last_iso_frame = (ehci_read_frame_index(ehci) & (mod - 1)) >> 3; ++#endif + iso_sched_free(stream, sched); + urb->hcpriv = NULL; + return status; +@@ -1802,6 +1865,22 @@ static void itd_link_urb( + itd_init(ehci, stream, itd); + } + ++#if (MP_USB_MSTAR==1) ++ if (urb->dev->speed != USB_SPEED_HIGH) //Colin, patch for not real split-transaction mode ++ { ++ uframe = 0; //always is transaction 0 of itd ++ frame = next_uframe >> 3; ++ ++ itd_patch(ehci, itd, iso_sched, packet, uframe); // linux warning as below ++ itd_link (ehci, frame % ehci->periodic_size, itd); ++ itd = NULL; ++ ++ next_uframe += (unsigned)(urb->interval << 3); ++ next_uframe &= mod - 1; // new patch ++ packet++; ++ continue; ++ } ++#endif + uframe = next_uframe & 0x07; + frame = next_uframe >> 3; + +@@ -1875,12 +1954,20 @@ static bool itd_complete(struct ehci_hcd *ehci, struct ehci_itd *itd) + + /* HC need not update length with this error */ + if (!(t & EHCI_ISOC_BABBLE)) { ++#if (MP_USB_MSTAR==1) ++ desc->actual_length = desc->length - EHCI_ITD_LENGTH (t); //Our EHCI send back left data which haven't recved ++#else + desc->actual_length = EHCI_ITD_LENGTH(t); ++#endif + urb->actual_length += desc->actual_length; + } + } else if (likely((t & EHCI_ISOC_ACTIVE) == 0)) { + desc->status = 0; ++#if (MP_USB_MSTAR==1) ++ desc->actual_length = desc->length - EHCI_ITD_LENGTH (t); //Our EHCI send back left data which haven't recved ++#else + desc->actual_length = EHCI_ITD_LENGTH(t); ++#endif + urb->actual_length += desc->actual_length; + } else { + /* URB was too late */ +@@ -1948,6 +2035,17 @@ static int itd_submit(struct ehci_hcd *ehci, struct urb *urb, + ehci_dbg(ehci, "can't get iso stream\n"); + return -ENOMEM; + } ++#if (MP_USB_MSTAR==1) ++ if ((ehci_readl(ehci, &ehci->regs->bmcs) & 0x0600) != 0x0400) ++ { ++ if (unlikely((urb->interval<<3) != stream->uperiod)) { ++ ehci_dbg(ehci, "can't change iso interval %d --> %d\n", ++ stream->uperiod, urb->interval); ++ goto done; ++ } ++ } ++ else ++#endif + if (unlikely(urb->interval != stream->uperiod)) { + ehci_dbg(ehci, "can't change iso interval %d --> %d\n", + stream->uperiod, urb->interval); +@@ -1990,6 +2088,9 @@ static int itd_submit(struct ehci_hcd *ehci, struct urb *urb, + } else { + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); + } ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ Chip_Flush_MIU_Pipe(); ++#endif + done_not_linked: + spin_unlock_irqrestore(&ehci->lock, flags); + done: +@@ -2097,6 +2198,10 @@ sitd_urb_transaction( + spin_unlock_irqrestore(&ehci->lock, flags); + sitd = dma_pool_alloc(ehci->sitd_pool, mem_flags, + &sitd_dma); ++/* tony.yu map between PHY addr & BUS addr */ ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ sitd_dma = BUS2PA(sitd_dma); ++#endif + spin_lock_irqsave(&ehci->lock, flags); + if (!sitd) { + iso_sched_free(stream, iso_sched); +@@ -2219,6 +2324,9 @@ static void sitd_link_urb( + + ++ehci->isoc_count; + enable_periodic(ehci); ++#if (MP_USB_MSTAR==1) && !defined (ENABLE_INTR_SITD_CS_IN_ZERO_ECO) ++ turn_on_sitd_watchdog(ehci); ++#endif + } + + /*-------------------------------------------------------------------------*/ +@@ -2266,8 +2374,22 @@ static bool sitd_complete(struct ehci_hcd *ehci, struct ehci_sitd *sitd) + urb->error_count++; + } else { + desc->status = 0; ++#if (MP_USB_MSTAR==1) ++ if( desc->length < SITD_LENGTH (t) ) ++ { ++ desc->actual_length = desc->length - SITD_LENGTH(t)+1024; ++ urb->actual_length += desc->actual_length; ++ printk("\r\n Error Data..."); ++ } ++ else ++ { ++ desc->actual_length = desc->length - SITD_LENGTH(t); ++ urb->actual_length += desc->actual_length; ++ } ++#else + desc->actual_length = desc->length - SITD_LENGTH(t); + urb->actual_length += desc->actual_length; ++#endif + } + + /* handle completion now? */ +@@ -2369,6 +2491,9 @@ static int sitd_submit(struct ehci_hcd *ehci, struct urb *urb, + } else { + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); + } ++#if (MP_USB_MSTAR==1) && (_USB_T3_WBTIMEOUT_PATCH) ++ Chip_Flush_MIU_Pipe(); ++#endif + done_not_linked: + spin_unlock_irqrestore(&ehci->lock, flags); + done: +diff --git a/drivers/usb/host/ehci-sysfs.c b/drivers/usb/host/ehci-sysfs.c +index 5216f2b09d63..0ac12e9c7a68 100644 +--- a/drivers/usb/host/ehci-sysfs.c ++++ b/drivers/usb/host/ehci-sysfs.c +@@ -17,7 +17,13 @@ + */ + + /* this file is part of ehci-hcd.c */ ++#ifndef MP_USB_MSTAR ++#include ++#endif + ++#if (MP_USB_MSTAR==1) && defined(CONFIG_USB_EHCI_SUSPEND_PORT) ++#include "ehci-mstar-sysfs.c" ++#endif + + /* Display the ports dedicated to the companion controller */ + static ssize_t show_companion(struct device *dev, +@@ -171,6 +177,14 @@ static inline int create_sysfs_files(struct ehci_hcd *ehci) + goto out; + + i = device_create_file(controller, &dev_attr_uframe_periodic_max); ++ ++#if (MP_USB_MSTAR==1) && defined(CONFIG_USB_EHCI_SUSPEND_PORT) ++ if (i) ++ goto out; ++ ++ i = device_create_file(controller, &dev_attr_port_suspend); ++#endif ++ + out: + return i; + } +@@ -184,4 +198,7 @@ static inline void remove_sysfs_files(struct ehci_hcd *ehci) + device_remove_file(controller, &dev_attr_companion); + + device_remove_file(controller, &dev_attr_uframe_periodic_max); ++#if (MP_USB_MSTAR==1) && defined(CONFIG_USB_EHCI_SUSPEND_PORT) ++ device_remove_file(controller, &dev_attr_port_suspend); ++#endif + } +diff --git a/drivers/usb/host/ehci-timer.c b/drivers/usb/host/ehci-timer.c +index 69f50e6533a6..be5435968801 100644 +--- a/drivers/usb/host/ehci-timer.c ++++ b/drivers/usb/host/ehci-timer.c +@@ -15,6 +15,9 @@ + /* This file is part of ehci-hcd.c */ + + /*-------------------------------------------------------------------------*/ ++#ifndef MP_USB_MSTAR ++#include ++#endif + + /* Set a bit in the USBCMD register */ + static void ehci_set_command_bit(struct ehci_hcd *ehci, u32 bit) +@@ -73,6 +76,9 @@ static unsigned event_delays_ns[] = { + 1125 * NSEC_PER_USEC, /* EHCI_HRTIMER_UNLINK_INTR */ + 2 * NSEC_PER_MSEC, /* EHCI_HRTIMER_FREE_ITDS */ + 2 * NSEC_PER_MSEC, /* EHCI_HRTIMER_ACTIVE_UNLINK */ ++#if (MP_USB_MSTAR==1) ++ 4 * NSEC_PER_MSEC, /* EHCI_HRTIMER_SITD_WATCHDOG */ ++#endif + 5 * NSEC_PER_MSEC, /* EHCI_HRTIMER_START_UNLINK_INTR */ + 6 * NSEC_PER_MSEC, /* EHCI_HRTIMER_ASYNC_UNLINKS */ + 10 * NSEC_PER_MSEC, /* EHCI_HRTIMER_IAA_WATCHDOG */ +@@ -309,12 +315,19 @@ static void end_free_itds(struct ehci_hcd *ehci) + + list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) { + list_del(&itd->itd_list); ++/* tony.yu map between PHY addr & BUS addr */ ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ itd->itd_dma = PA2BUS(itd->itd_dma); ++#endif + dma_pool_free(ehci->itd_pool, itd, itd->itd_dma); + if (itd == ehci->last_itd_to_free) + break; + } + list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) { + list_del(&sitd->sitd_list); ++#if (MP_USB_MSTAR==1) && defined(BUS_PA_PATCH) ++ sitd->sitd_dma = PA2BUS(sitd->sitd_dma); ++#endif + dma_pool_free(ehci->sitd_pool, sitd, sitd->sitd_dma); + if (sitd == ehci->last_sitd_to_free) + break; +@@ -384,6 +397,26 @@ static void turn_on_io_watchdog(struct ehci_hcd *ehci) + ehci_enable_event(ehci, EHCI_HRTIMER_IO_WATCHDOG, true); + } + ++#if (MP_USB_MSTAR==1) ++static void turn_on_sitd_watchdog(struct ehci_hcd *ehci) ++{ ++ /* Not needed if the controller isn't running or it's already enabled */ ++ if (ehci->rh_state != EHCI_RH_RUNNING || ++ (ehci->enabled_hrtimer_events & ++ BIT(EHCI_HRTIMER_SITD_WATCHDOG))) ++ return; ++ ++ /* ++ * Isochronous transfers always need the watchdog. ++ * For other sorts we use it only if the flag is set. ++ */ ++ if (ehci->isoc_count > 0 || (ehci->need_io_watchdog && ++ ehci->async_count + ehci->intr_count > 0)) ++ { ++ ehci_enable_event(ehci, EHCI_HRTIMER_SITD_WATCHDOG, true); ++ } ++} ++#endif + + /* + * Handler functions for the hrtimer event types. +@@ -397,6 +430,9 @@ static void (*event_handlers[])(struct ehci_hcd *) = { + ehci_handle_intr_unlinks, /* EHCI_HRTIMER_UNLINK_INTR */ + end_free_itds, /* EHCI_HRTIMER_FREE_ITDS */ + end_unlink_async, /* EHCI_HRTIMER_ACTIVE_UNLINK */ ++#if (MP_USB_MSTAR==1) ++ ehci_work, /* EHCI_HRTIMER_SITD_WATCHDOG */ ++#endif + ehci_handle_start_intr_unlinks, /* EHCI_HRTIMER_START_UNLINK_INTR */ + unlink_empty_async, /* EHCI_HRTIMER_ASYNC_UNLINKS */ + ehci_iaa_watchdog, /* EHCI_HRTIMER_IAA_WATCHDOG */ +diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h +index 3f3b74aeca97..ee8a6b08745c 100644 +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -19,6 +19,10 @@ + #ifndef __LINUX_EHCI_HCD_H + #define __LINUX_EHCI_HCD_H + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ + /* definitions used for the EHCI driver */ + + /* +@@ -111,6 +115,9 @@ enum ehci_hrtimer_event { + EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ + EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ + EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */ ++#if (MP_USB_MSTAR==1) ++ EHCI_HRTIMER_SITD_WATCHDOG,/* Check for missing SITD IRQs */ ++#endif + EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ + EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ + EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ +@@ -327,7 +334,11 @@ struct ehci_qtd { + struct list_head qtd_list; /* sw qtd list */ + struct urb *urb; /* qtd's urb */ + size_t length; /* length of buffer */ ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++} __aligned(128); ++#else + } __aligned(32); ++#endif + + /* mask NakCnt+T in qh->hw_alt_next */ + #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f) +@@ -411,7 +422,11 @@ struct ehci_qh_hw { + __hc32 hw_token; + __hc32 hw_buf[5]; + __hc32 hw_buf_hi[5]; ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++} __aligned(128); ++#else + } __aligned(32); ++#endif + + struct ehci_qh { + struct ehci_qh_hw *hw; /* Must come first */ +@@ -485,6 +500,9 @@ struct ehci_iso_stream { + + u8 bEndpointAddress; + u8 highspeed; ++#if (MP_USB_MSTAR==1) ++ u32 last_iso_frame; /* previous frame index */ ++#endif + struct list_head td_list; /* queued itds/sitds */ + struct list_head free_list; /* list of unused itds/sitds */ + +@@ -545,7 +563,11 @@ struct ehci_itd { + unsigned frame; /* where scheduled */ + unsigned pg; + unsigned index[8]; /* in urb->iso_frame_desc */ ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++} __aligned(128); ++#else + } __aligned(32); ++#endif + + /*-------------------------------------------------------------------------*/ + +@@ -651,6 +673,29 @@ struct ehci_tt { + + /*-------------------------------------------------------------------------*/ + ++#if (MP_USB_MSTAR==1) ++static inline unsigned int ehci_readl(struct ehci_hcd *ehci, ++ __u32 __iomem * regs); ++/* Returns the speed of a device attached to a port on the root hub. */ ++static inline unsigned int ++ehci_mstar_port_speed(struct ehci_hcd *ehci) ++{ ++ unsigned int bmcs = ehci_readl(ehci, &ehci->regs->bmcs); ++ ++ switch ((bmcs >> 9) & 3) { ++ case 0: ++ return 0; // full speed ++ case 1: ++ return USB_PORT_STAT_LOW_SPEED; ++ case 2: ++ return USB_PORT_STAT_HIGH_SPEED; ++ default: ++ printk("[USB] unknow port1 usb device speed\n"); ++ return USB_PORT_STAT_HIGH_SPEED; ++ } ++} ++#endif ++ + #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT + + /* +@@ -667,6 +712,9 @@ static inline unsigned int + ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) + { + if (ehci_is_TDI(ehci)) { ++#if (MP_USB_MSTAR==1) ++ return ehci_mstar_port_speed(ehci); ++#else + switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { + case 0: + return 0; +@@ -676,6 +724,7 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) + default: + return USB_PORT_STAT_HIGH_SPEED; + } ++#endif + } + return USB_PORT_STAT_HIGH_SPEED; + } +@@ -684,8 +733,13 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) + + #define ehci_is_TDI(e) (0) + ++#if (MP_USB_MSTAR==1) ++#error !!! Please select CONFIG_USB_EHCI_ROOT_HUB_TT in memnuconfig USB Driver ++#define ehci_port_speed(ehci, portsc) ehci_mstar_port_speed(ehci) ++#else + #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED + #endif ++#endif + + /*-------------------------------------------------------------------------*/ + +@@ -740,6 +794,30 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) + #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) + #endif + ++#if (MP_USB_MSTAR==1) ++#include "ehci-mstar.h" ++#endif ++ ++#if (MP_USB_MSTAR==1) ++static inline unsigned int ehci_readl(struct ehci_hcd *ehci, ++ __u32 __iomem * regs) ++{ ++ unsigned int result; ++ #if _USB_XIU_TIMEOUT_PATCH ++ struct usb_hcd *hcd = ehci_to_hcd(ehci); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&(hcd->usb_reset_lock), flags); ++ #endif ++ regs = (u32 *)( ((uintptr_t)regs & ~(0xffUL)) + (((uintptr_t)regs & 0xffUL)<<1)); ++ result = (readl((void*)regs) & 0xffffU)|((readl((void*)((uintptr_t)regs+4))<<16) & (0xffffU<<16)); ++ ++ #if _USB_XIU_TIMEOUT_PATCH ++ spin_unlock_irqrestore(&(hcd->usb_reset_lock), flags); ++ #endif ++ return result; ++} ++#else + static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, + __u32 __iomem *regs) + { +@@ -751,6 +829,7 @@ static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, + return readl(regs); + #endif + } ++#endif + + #ifdef CONFIG_SOC_IMX28 + static inline void imx28_ehci_writel(const unsigned int val, +@@ -764,6 +843,26 @@ static inline void imx28_ehci_writel(const unsigned int val, + { + } + #endif ++ ++#if (MP_USB_MSTAR==1) ++static inline void ehci_writel(struct ehci_hcd *ehci, ++ const unsigned int val, __u32 __iomem *regs) ++{ ++ #if _USB_XIU_TIMEOUT_PATCH ++ struct usb_hcd *hcd = ehci_to_hcd(ehci); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&(hcd->usb_reset_lock), flags); ++ #endif ++ regs = (u32 *)(((uintptr_t)regs & ~(0xffUL)) + (((uintptr_t)regs & 0xffUL)<<1)); ++ writel(val & 0xffffU,(void*)regs); ++ writel(((val>>16) & 0xffffU),(void*)((uintptr_t)regs+4)); ++ ++ #if _USB_XIU_TIMEOUT_PATCH ++ spin_unlock_irqrestore(&(hcd->usb_reset_lock), flags); ++ #endif ++} ++#else + static inline void ehci_writel(const struct ehci_hcd *ehci, + const unsigned int val, __u32 __iomem *regs) + { +@@ -778,6 +877,7 @@ static inline void ehci_writel(const struct ehci_hcd *ehci, + writel(val, regs); + #endif + } ++#endif + + /* + * On certain ppc-44x SoC there is a HW issue, that could only worked around with +diff --git a/drivers/usb/host/hwa-hc.c b/drivers/usb/host/hwa-hc.c +index 1db0626c8bf4..97750f162f01 100644 +--- a/drivers/usb/host/hwa-hc.c ++++ b/drivers/usb/host/hwa-hc.c +@@ -654,7 +654,7 @@ static int hwahc_security_create(struct hwahc *hwahc) + top = itr + itr_size; + result = __usb_get_extra_descriptor(usb_dev->rawdescriptors[index], + le16_to_cpu(usb_dev->actconfig->desc.wTotalLength), +- USB_DT_SECURITY, (void **) &secd); ++ USB_DT_SECURITY, (void **) &secd, sizeof(*secd)); + if (result == -1) { + dev_warn(dev, "BUG? WUSB host has no security descriptors\n"); + return 0; +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index 0722f75f1d6a..13d80c5a10cc 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -27,6 +27,17 @@ + #include "xhci.h" + #include "xhci-trace.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++extern void Chip_Flush_Memory(void); ++#endif ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++extern bool is_suspending(void); ++#endif /* CONFIG_MP_USB_STR_PATCH */ ++ + #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) + #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ + PORT_RC | PORT_PLC | PORT_PE) +@@ -435,13 +446,50 @@ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) + spin_unlock_irqrestore(&xhci->lock, flags); + + /* Wait for last stop endpoint command to finish */ ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ { ++ unsigned long total_time = 0, timeout_val; ++ int timeleft; ++ ++ timeout_val = msecs_to_jiffies(USB_CTRL_SET_TIMEOUT); ++ ++ while(1) ++ { ++ timeleft = wait_for_completion_interruptible_timeout( ++ cmd->completion, msecs_to_jiffies(HZ)); ++ ++ if(timeleft <= 0) ++ { ++ total_time += msecs_to_jiffies(HZ); ++ printk("[XHCI] waiting for stop dev... %lu\n", total_time); ++ if ( (timeleft < 0) || is_suspending() || (total_time >= timeout_val) ) ++ { ++ xhci_warn(xhci, "%s while waiting for stop endpoint command\n", ++ total_time >= timeout_val ? "Timeout" : "Signal"); ++ spin_lock_irqsave(&xhci->lock, flags); ++ /* The timeout might have raced with the event ring handler, so ++ * only delete from the list if the item isn't poisoned. ++ */ ++ if (cmd->cmd_list.next != LIST_POISON1) ++ list_del(&cmd->cmd_list); ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ ret = -ETIME; ++ break; ++ } ++ } ++ else ++ break; ++ } ++ } ++ ++#else + wait_for_completion(cmd->completion); + + if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) { + xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); + ret = -ETIME; + } +- ++#endif /* CONFIG_MP_USB_STR_PATCH */ + cmd_cleanup: + xhci_free_command(xhci, cmd); + return ret; +@@ -455,6 +503,10 @@ void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) + int i, s; + struct xhci_virt_ep *ep; + ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ Chip_Flush_Memory(); ++#endif ++ + for (i = 0; i < LAST_EP_INDEX + 1; i++) { + ep = &xhci->devs[slot_id]->eps[i]; + +@@ -472,12 +524,33 @@ void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) + static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, + u16 wIndex, __le32 __iomem *addr, u32 port_status) + { ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_SSDISABLED_PATCH) ++ #if defined(XHCI_SSDISABLE_POWERDOWN_PATCH) ++ if ((hcd->speed == HCD_USB3) && (wIndex==0)) { ++ printk("[override P0]\n"); ++ writeb((u8)((readb((void*)(hcd->u3top_base+0x2A*2)) & (u8)(~BIT3)) | BIT4), ++ (void*)(hcd->u3top_base+0x2A*2)); /// Override pipe_powerdown to P0 [4:3] = 2'b10 ++ } ++ #endif /* XHCI_SSDISABLE_POWERDOWN_PATCH */ ++ #if defined(XHCI_SSDISABLE_XUSB_PCIE_PATCH) ++ if ((hcd->speed == HCD_USB3) && (wIndex==0)) { ++ printk("[DPHY clock override P0]\n"); ++ writeb((u8)((readb((void*)(hcd->u3dphy_base[0]+0x38*2)) & (u8)(~BIT2)) & (u8)(~BIT3)), ++ (void*)(hcd->u3dphy_base[0]+0x38*2)); // [3:2]='2b00 ++ writeb((u8)(readb((void*)(hcd->u3dphy_base[0]+0x3C*2)) | BIT1), ++ (void*)(hcd->u3dphy_base[0]+0x3C*2)); // [1]='2b1 ++ } ++ #endif ++#else ++ + /* Don't allow the USB core to disable SuperSpeed ports. */ + if (hcd->speed >= HCD_USB3) { + xhci_dbg(xhci, "Ignoring request to disable " + "SuperSpeed port.\n"); + return; + } ++#endif + + if (xhci->quirks & XHCI_BROKEN_PORT_PED) { + xhci_dbg(xhci, +@@ -488,8 +561,31 @@ static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, + /* Write 1 to disable the port */ + writel(port_status | PORT_PE, addr); + port_status = readl(addr); ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_SSDISABLED_PATCH) ++ #if defined(XHCI_SSDISABLE_POWERDOWN_PATCH) ++ if ((hcd->speed == HCD_USB3) && ((readb((void*)(hcd->u3top_base+0x2A*2)) & (u8)(BIT4|BIT3)) == (u8)BIT4)) { ++ printk("[USB] make Fake HW signal\n"); ++ udelay(5); ++ #if defined(XHCI_PHY_MS28) ++ writeb(0x40, (void*)(hcd->u3dphy_base[wIndex]+0x3A*2)); ++ writeb(0x04, (void*)(hcd->u3dphy_base[wIndex]+0x3E*2)); ++ writeb(0x00, (void*)(hcd->u3dphy_base[wIndex]+0x3E*2)); ++ #endif ++ } ++ #endif ++ #if defined(XHCI_SSDISABLE_XUSB_PCIE_PATCH) ++ if ((hcd->speed == HCD_USB3) && (wIndex==0)) { ++ writeb((u8)((readb((void*)(hcd->u3dphy_base[0]+0x38*2)) & (u8)(~BIT2)) | BIT3), ++ (void*)(hcd->u3dphy_base[0]+0x38*2)); // [3:2]='2b10 ++ } ++ #endif ++ printk("disable port, actual port %d status = 0x%x\n", ++ wIndex, port_status); ++#else + xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", + wIndex, port_status); ++#endif + } + + static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, +@@ -1143,6 +1239,9 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + wIndex, temp); + break; + case USB_PORT_FEAT_BH_PORT_RESET: ++#if (MP_USB_MSTAR==1) ++ printk("==> hub_port_warm_reset \n"); ++#endif + temp |= PORT_WR; + writel(temp, port_array[wIndex]); + +@@ -1323,6 +1422,10 @@ int xhci_bus_suspend(struct usb_hcd *hcd) + struct xhci_bus_state *bus_state; + unsigned long flags; + ++#if (MP_USB_MSTAR==1) ++ printk("xhci_bus_suspend \n"); ++#endif ++ + max_ports = xhci_get_ports(hcd, &port_array); + bus_state = &xhci->bus_state[hcd_index(hcd)]; + +@@ -1381,6 +1484,9 @@ int xhci_bus_suspend(struct usb_hcd *hcd) + } + hcd->state = HC_STATE_SUSPENDED; + bus_state->next_statechange = jiffies + msecs_to_jiffies(10); ++#if (MP_USB_MSTAR==1) ++ disable_irq(hcd->irq); //20141106, for system suspend-resume ++#endif + spin_unlock_irqrestore(&xhci->lock, flags); + return 0; + } +@@ -1427,6 +1533,10 @@ int xhci_bus_resume(struct usb_hcd *hcd) + int slot_id; + int sret; + ++#if (MP_USB_MSTAR==1) ++ printk("xhci_bus_resume \n"); ++#endif ++ + max_ports = xhci_get_ports(hcd, &port_array); + bus_state = &xhci->bus_state[hcd_index(hcd)]; + +@@ -1514,7 +1624,9 @@ int xhci_bus_resume(struct usb_hcd *hcd) + temp |= CMD_EIE; + writel(temp, &xhci->op_regs->command); + temp = readl(&xhci->op_regs->command); +- ++#if (MP_USB_MSTAR==1) ++ enable_irq(hcd->irq); //20150226, suspend fail cause ehci_hcd_mstar_drv_resume() not running ++#endif + spin_unlock_irqrestore(&xhci->lock, flags); + return 0; + } +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 3b7d69ca83be..0bb3c2a3ffae 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -29,6 +29,18 @@ + #include "xhci.h" + #include "xhci-trace.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ ++#if (MP_USB_MSTAR==1) ++#include "xhci-mstar.h" ++#endif ++ ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++extern void Chip_Flush_Memory(void); ++#endif ++ + /* + * Allocates a generic ring segment from the ring pool, sets the dma address, + * initializes the segment to zero, and sets the private next pointer to NULL. +@@ -55,6 +67,9 @@ static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, + return NULL; + } + ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ dma = BUS2PA(dma); ++#endif + if (max_packet) { + seg->bounce_buf = kzalloc(max_packet, flags); + if (!seg->bounce_buf) { +@@ -77,6 +92,9 @@ static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, + static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) + { + if (seg->trbs) { ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ seg->dma = PA2BUS(seg->dma); ++#endif + dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); + seg->trbs = NULL; + } +@@ -535,6 +553,11 @@ static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci + kfree(ctx); + return NULL; + } ++ ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ ctx->dma = BUS2PA(ctx->dma); ++#endif ++ + return ctx; + } + +@@ -543,6 +566,11 @@ static void xhci_free_container_ctx(struct xhci_hcd *xhci, + { + if (!ctx) + return; ++ ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ ctx->dma = PA2BUS(ctx->dma); ++#endif ++ + dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); + kfree(ctx); + } +@@ -589,6 +617,10 @@ static void xhci_free_stream_ctx(struct xhci_hcd *xhci, + struct device *dev = xhci_to_hcd(xhci)->self.controller; + size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; + ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ dma = PA2BUS(dma); ++#endif ++ + if (size > MEDIUM_STREAM_ARRAY_SIZE) + dma_free_coherent(dev, size, + stream_ctx, dma); +@@ -617,6 +649,23 @@ static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, + struct device *dev = xhci_to_hcd(xhci)->self.controller; + size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; + ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ struct xhci_stream_ctx *pRet; ++ ++ if (size > MEDIUM_STREAM_ARRAY_SIZE) ++ pRet = dma_alloc_coherent(dev, size, ++ dma, mem_flags); ++ else if (size <= SMALL_STREAM_ARRAY_SIZE) ++ pRet = dma_pool_alloc(xhci->small_streams_pool, ++ mem_flags, dma); ++ else ++ pRet = dma_pool_alloc(xhci->medium_streams_pool, ++ mem_flags, dma); ++ ++ *dma = BUS2PA(*dma); ++ ++ return pRet; ++#else + if (size > MEDIUM_STREAM_ARRAY_SIZE) + return dma_alloc_coherent(dev, size, + dma, mem_flags); +@@ -626,6 +675,7 @@ static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, + else + return dma_pool_alloc(xhci->medium_streams_pool, + mem_flags, dma); ++#endif + } + + struct xhci_ring *xhci_dma_to_transfer_ring( +@@ -1723,6 +1773,10 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) + if (!xhci->scratchpad->sp_array) + goto fail_sp2; + ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ xhci->scratchpad->sp_dma = BUS2PA(xhci->scratchpad->sp_dma); ++#endif ++ + xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); + if (!xhci->scratchpad->sp_buffers) + goto fail_sp3; +@@ -1741,6 +1795,9 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) + if (!buf) + goto fail_sp5; + ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ dma = BUS2PA(dma); ++#endif + xhci->scratchpad->sp_array[i] = dma; + xhci->scratchpad->sp_buffers[i] = buf; + xhci->scratchpad->sp_dma_buffers[i] = dma; +@@ -1750,6 +1807,9 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) + + fail_sp5: + for (i = i - 1; i >= 0; i--) { ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ xhci->scratchpad->sp_dma_buffers[i] = PA2BUS(xhci->scratchpad->sp_dma_buffers[i]); ++#endif + dma_free_coherent(dev, xhci->page_size, + xhci->scratchpad->sp_buffers[i], + xhci->scratchpad->sp_dma_buffers[i]); +@@ -1760,6 +1820,9 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) + kfree(xhci->scratchpad->sp_buffers); + + fail_sp3: ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ xhci->scratchpad->sp_dma = PA2BUS(xhci->scratchpad->sp_dma); ++#endif + dma_free_coherent(dev, num_sp * sizeof(u64), + xhci->scratchpad->sp_array, + xhci->scratchpad->sp_dma); +@@ -1784,12 +1847,19 @@ static void scratchpad_free(struct xhci_hcd *xhci) + num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); + + for (i = 0; i < num_sp; i++) { ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ xhci->scratchpad->sp_dma_buffers[i] = ++ PA2BUS(xhci->scratchpad->sp_dma_buffers[i]); ++#endif + dma_free_coherent(dev, xhci->page_size, + xhci->scratchpad->sp_buffers[i], + xhci->scratchpad->sp_dma_buffers[i]); + } + kfree(xhci->scratchpad->sp_dma_buffers); + kfree(xhci->scratchpad->sp_buffers); ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ xhci->scratchpad->sp_dma = PA2BUS(xhci->scratchpad->sp_dma); ++#endif + dma_free_coherent(dev, num_sp * sizeof(u64), + xhci->scratchpad->sp_array, + xhci->scratchpad->sp_dma); +@@ -1860,9 +1930,18 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci) + + /* Free the Event Ring Segment Table and the actual Event Ring */ + size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ if (xhci->erst.entries) { ++ xhci->erst.erst_dma_addr = PA2BUS(xhci->erst.erst_dma_addr); ++ dma_free_coherent(dev, size, ++ xhci->erst.entries, xhci->erst.erst_dma_addr); ++ } ++#else + if (xhci->erst.entries) + dma_free_coherent(dev, size, + xhci->erst.entries, xhci->erst.erst_dma_addr); ++#endif ++ + xhci->erst.entries = NULL; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); + if (xhci->event_ring) +@@ -1910,9 +1989,18 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci) + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Freed medium stream array pool"); + ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ if (xhci->dcbaa) { ++ xhci->dcbaa->dma = PA2BUS(xhci->dcbaa->dma); ++ dma_free_coherent(dev, sizeof(*xhci->dcbaa), ++ xhci->dcbaa, xhci->dcbaa->dma); ++ } ++#else + if (xhci->dcbaa) + dma_free_coherent(dev, sizeof(*xhci->dcbaa), + xhci->dcbaa, xhci->dcbaa->dma); ++#endif ++ + xhci->dcbaa = NULL; + + scratchpad_free(xhci); +@@ -2109,7 +2197,11 @@ static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci) + return 0; + } + ++#if (MP_USB_MSTAR==1) ++void xhci_set_hc_event_deq(struct xhci_hcd *xhci) ++#else + static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) ++#endif + { + u64 temp; + dma_addr_t deq; +@@ -2450,6 +2542,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + flags); + if (!xhci->dcbaa) + goto fail; ++ ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ dma = BUS2PA(dma); ++#endif ++ + memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); + xhci->dcbaa->dma = dma; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, +@@ -2469,7 +2566,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + + /* See Table 46 and Note on Figure 55 */ + xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ 2112, 128, xhci->page_size); ++#else + 2112, 64, xhci->page_size); ++#endif + if (!xhci->segment_pool || !xhci->device_pool) + goto fail; + +@@ -2478,10 +2579,18 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + */ + xhci->small_streams_pool = + dma_pool_create("xHCI 256 byte stream ctx arrays", ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ dev, SMALL_STREAM_ARRAY_SIZE, 128, 0); ++#else + dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); ++#endif + xhci->medium_streams_pool = + dma_pool_create("xHCI 1KB stream ctx arrays", ++#if (MP_USB_MSTAR==1) && (_USB_128_ALIGMENT) ++ dev, MEDIUM_STREAM_ARRAY_SIZE, 128, 0); ++#else + dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); ++#endif + /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE + * will be allocated with dma_alloc_coherent() + */ +@@ -2546,6 +2655,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + flags); + if (!xhci->erst.entries) + goto fail; ++ ++#if (MP_USB_MSTAR==1) && (XHCI_PA_PATCH) ++ dma = BUS2PA(dma); ++#endif ++ + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "// Allocated event ring segment table at 0x%llx", + (unsigned long long)dma); +@@ -2568,6 +2682,10 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + seg = seg->next; + } + ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ Chip_Flush_Memory(); ++#endif ++ + /* set ERST count with the number of entries in the segment table */ + val = readl(&xhci->ir_set->erst_size); + val &= ERST_SIZE_MASK; +diff --git a/drivers/usb/host/xhci-mstar-sysfs.c b/drivers/usb/host/xhci-mstar-sysfs.c +new file mode 100644 +index 000000000000..7e2df0feba8e +--- /dev/null ++++ b/drivers/usb/host/xhci-mstar-sysfs.c +@@ -0,0 +1,360 @@ ++/* ++ * xHCI host controller driver ++ * ++ * Copyright (C) 2014 MStar Inc. ++ * ++ * Date: May 2014 ++ */ ++ ++#include "xhci.h" ++#include "xhci-mstar.h" ++ ++static int bP0VbusSetting=0; ++#ifdef XHCI_2PORTS ++static int bP1VbusSetting=0; ++#endif ++ ++/* Display the SS port0 status */ ++static ssize_t show_ss0vbus(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ int count; ++ char *ptr = buf; ++ ++ count = scnprintf(ptr, 4, "%d\n", bP0VbusSetting); ++ return count; ++} ++ ++/* Turn the SS port0 on or off */ ++static ssize_t store_ss0vbus(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int bOn; ++ struct usb_hcd *hcd; ++ u16 addr_w, bit_num; ++ uintptr_t addr, gpio_addr; ++ u8 value, low_active; ++ ++ if (sscanf(buf, "%d", &bOn) != 1) ++ return -EINVAL; ++ ++ if (bOn) ++ bOn = 1; ++ bP0VbusSetting = bOn; ++ ++ hcd = bus_to_hcd(dev_get_drvdata(dev)); ++ addr_w = readw((void*)(hcd->u3top_base+0xFC*2)); ++ addr = (uintptr_t)addr_w << 8; ++ addr_w = readw((void*)(hcd->u3top_base+0xFE*2)); ++ addr |= addr_w & 0xFF; ++ bit_num = (addr_w >> 8) & 0x7; ++ low_active = (u8)((addr_w >> 11) & 0x1); ++ ++ if (addr) ++ { ++ printk("ss0vbus: %d\n", bOn); ++ printk("Addr: 0x%lx bit_num: %d low_active:%d\n", addr, bit_num, low_active); ++ ++ value = 1 << bit_num; ++ ++ if (addr & 0x1) ++ gpio_addr = _MSTAR_PM_BASE+addr*2-1; ++ else ++ gpio_addr = _MSTAR_PM_BASE+addr*2; ++ ++ if (low_active^bOn) ++ { ++ writeb(readb((void*)gpio_addr) | value, (void*)gpio_addr); ++ } ++ else ++ { ++ writeb(readb((void*)gpio_addr) & (u8)(~value), (void*)gpio_addr); ++ } ++ } ++ else { ++ printk("\n\n!!!! ERROR : xhci: no GPIO information for vbus port0 power control !!!! \n\n"); ++ return -EIO; ++ } ++ ++ return count; ++} ++ ++static DEVICE_ATTR(ss0vbus, 0644, show_ss0vbus, store_ss0vbus); ++ ++ ++#ifdef XHCI_2PORTS ++ ++/* Display the SS port0 status */ ++static ssize_t show_ss1vbus(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ int count; ++ char *ptr = buf; ++ ++ count = scnprintf(ptr, 4, "%d\n", bP1VbusSetting); ++ return count; ++} ++ ++/* Turn the SS port0 on or off */ ++static ssize_t store_ss1vbus(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int bOn; ++ struct usb_hcd *hcd; ++ u16 addr_w, bit_num; ++ uintptr_t addr, gpio_addr; ++ u8 value, low_active; ++ ++ if (sscanf(buf, "%d", &bOn) != 1) ++ return -EINVAL; ++ ++ if (bOn) ++ bOn = 1; ++ bP1VbusSetting = bOn; ++ ++ hcd = bus_to_hcd(dev_get_drvdata(dev)); ++ addr_w = readw((void*)(hcd->u3top_base+0xE6*2)); ++ addr = (uintptr_t)addr_w << 8; ++ addr_w = readw((void*)(hcd->u3top_base+0xE8*2)); ++ addr |= addr_w & 0xFF; ++ bit_num = (addr_w >> 8) & 0x7; ++ low_active = (u8)((addr_w >> 8) & 0x8); ++ ++ if (addr) ++ { ++ printk("ss1vbus: %d\n", bOn); ++ printk("Addr: 0x%x bit_num: %d low_active:%d\n", addr, bit_num, low_active); ++ ++ value = 1 << bit_num; ++ ++ if (addr & 0x1) ++ gpio_addr = _MSTAR_PM_BASE+addr*2-1; ++ else ++ gpio_addr = _MSTAR_PM_BASE+addr*2; ++ ++ if (low_active^bOn) ++ { ++ writeb(readb((void*)gpio_addr) | value, (void*)gpio_addr); ++ } ++ else ++ { ++ writeb(readb((void*)gpio_addr) & (u8)(~value), (void*)gpio_addr); ++ } ++ } ++ else { ++ printk("\n\n!!!! ERROR : xhci: no GPIO information for vbus port1 power control !!!! \n\n"); ++ return -EIO; ++ } ++ ++ return count; ++} ++ ++static DEVICE_ATTR(ss1vbus, 0644, show_ss1vbus, store_ss1vbus); ++ ++#endif ++ ++static ssize_t xhci_ssport_set_state(struct xhci_hcd *xhci, int portnum, int bOn) ++{ ++ u32 temp; ++ ++ if (portnum >= xhci->num_usb3_ports) ++ return -EINVAL; ++ ++ temp = readl(xhci->usb3_ports[portnum]); ++ if (bOn) { ++ if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_SS_DISABLED) { ++ ++ temp = xhci_port_state_to_neutral(temp); ++ temp &= ~PORT_PLS_MASK; ++ temp |= PORT_LINK_STROBE | USB_SS_PORT_LS_RX_DETECT; ++ ++ writel(temp, xhci->usb3_ports[portnum]); ++ } ++ } else { ++ if ((temp & PORT_PLS_MASK) != USB_SS_PORT_LS_SS_DISABLED) { ++ ++ temp = xhci_port_state_to_neutral(temp); ++ writel(temp | PORT_PE, xhci->usb3_ports[portnum]); ++ } ++ } ++ ++ return 0; ++} ++ ++static ssize_t xhci_ssport_get_state(struct xhci_hcd *xhci, int portnum, int *state) ++{ ++ u32 temp; ++ ++ if (portnum >= xhci->num_usb3_ports) ++ return -EINVAL; ++ ++ temp = readl(xhci->usb3_ports[portnum]); ++ if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_SS_DISABLED) ++ *state = 0; ++ else ++ *state = 1; ++ ++ return 0; ++} ++ ++/* Display the SS port0 status */ ++static ssize_t show_ss0control(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct xhci_hcd *xhci; ++ int status, count; ++ ssize_t ret; ++ char *ptr = buf; ++ ++ xhci = hcd_to_xhci(bus_to_hcd(dev_get_drvdata(dev))); ++ ++ ret = xhci_ssport_get_state(xhci, 0, &status); ++ if (ret < 0) ++ return ret; ++ ++ count = scnprintf(ptr, 4, "%d\n", status); ++ return count; ++} ++ ++/* Turn the SS port0 on or off */ ++static ssize_t store_ss0control(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct usb_hcd *hcd; ++ struct xhci_hcd *xhci; ++ int bOn; ++ ssize_t ret; ++ ++ hcd = bus_to_hcd(dev_get_drvdata(dev)); ++ xhci = hcd_to_xhci(hcd); ++ if (sscanf(buf, "%d", &bOn) != 1) ++ return -EINVAL; ++ ++ ret = xhci_ssport_set_state(xhci, 0, bOn); ++ if (ret < 0) ++ return ret; ++ ++ //Record the setting to register ++ if (bOn) ++ writeb(readb((void*)(hcd->u3top_base+0xFF*2-1)) & (~0x10), (void*)(hcd->u3top_base+0xFF*2-1)); ++ else ++ writeb(readb((void*)(hcd->u3top_base+0xFF*2-1)) | 0x10, (void*)(hcd->u3top_base+0xFF*2-1)); ++ ++ return count; ++} ++ ++static DEVICE_ATTR(ss0control, 0644, show_ss0control, store_ss0control); ++ ++ ++#ifdef XHCI_2PORTS ++ ++/* Display the SS port1 status */ ++static ssize_t show_ss1control(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct xhci_hcd *xhci; ++ int status, count; ++ ssize_t ret; ++ char *ptr = buf; ++ ++ xhci = hcd_to_xhci(bus_to_hcd(dev_get_drvdata(dev))); ++ ++ ret = xhci_ssport_get_state(xhci, 1, &status); ++ if (ret < 0) ++ return ret; ++ ++ count = scnprintf(ptr, 4, "%d\n", status); ++ return count; ++} ++ ++/* Turn the SS port1 on or off */ ++static ssize_t store_ss1control(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct usb_hcd *hcd; ++ struct xhci_hcd *xhci; ++ int bOn; ++ ssize_t ret; ++ ++ hcd = bus_to_hcd(dev_get_drvdata(dev)); ++ xhci = hcd_to_xhci(hcd); ++ if (sscanf(buf, "%d", &bOn) != 1) ++ return -EINVAL; ++ ++ ret = xhci_ssport_set_state(xhci, 1, bOn); ++ if (ret < 0) ++ return ret; ++ ++ //Record the setting to register ++ if (bOn) ++ writeb(readb((void*)(hcd->u3top_base+0xE9*2-1)) & (~0x10), (void*)(hcd->u3top_base+0xE9*2-1)); ++ else ++ writeb(readb((void*)(hcd->u3top_base+0xE9*2-1)) | 0x10, (void*)(hcd->u3top_base+0xE9*2-1)); ++ ++ return count; ++} ++ ++static DEVICE_ATTR(ss1control, 0644, show_ss1control, store_ss1control); ++ ++#endif ++ ++int create_xhci_sysfs_files(struct xhci_hcd *xhci) ++{ ++ struct device *controller = xhci->shared_hcd->self.controller; ++ int i, ret = 0; ++ ++ i = device_create_file(controller, &dev_attr_ss0control); ++ if (i) { ++ printk("\n\n!!!! xhci device_create_file dev_attr_ss0control fail %d !!!! \n\n", i); ++ ret=1; ++ } ++ ++ i = device_create_file(controller, &dev_attr_ss0vbus); ++ if (i) { ++ printk("\n\n!!!! xhci device_create_file dev_attr_ss0vbus fail %d !!!! \n\n", i); ++ ret=1; ++ } ++ ++ if (xhci->num_usb3_ports == 1) ++ return ret; ++ ++#ifdef XHCI_2PORTS ++ i = device_create_file(controller, &dev_attr_ss1control); ++ if (i) { ++ printk("\n\n!!!! xhci device_create_file dev_attr_ss1control fail %d !!!! \n\n", i); ++ ret=1; ++ } ++ ++ i = device_create_file(controller, &dev_attr_ss1vbus); ++ if (i) { ++ printk("\n\n!!!! xhci device_create_file dev_attr_ss1vbus fail %d !!!! \n\n", i); ++ ret=1; ++ } ++#endif ++ ++ return ret; ++} ++ ++void remove_xhci_sysfs_files(struct xhci_hcd *xhci) ++{ ++ struct device *controller = xhci->shared_hcd->self.controller; ++ ++ device_remove_file(controller, &dev_attr_ss0control); ++ device_remove_file(controller, &dev_attr_ss0vbus); ++ ++#ifdef XHCI_2PORTS ++ if (xhci->num_usb3_ports == 1) ++ return; ++ ++ device_remove_file(controller, &dev_attr_ss1control); ++ device_remove_file(controller, &dev_attr_ss1vbus); ++#endif ++} +diff --git a/drivers/usb/host/xhci-mstar.c b/drivers/usb/host/xhci-mstar.c +new file mode 100644 +index 000000000000..0de65a656378 +--- /dev/null ++++ b/drivers/usb/host/xhci-mstar.c +@@ -0,0 +1,1101 @@ ++/* ++ * xhci-mstar.c - xHCI host controller driver platform Bus Glue. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "xhci.h" ++#include "xhci-mstar.h" ++#include "bc-mstar.h" ++#include "mstar-lib.h" ++ ++extern int create_xhci_sysfs_files(struct xhci_hcd *xhci); ++extern void remove_xhci_sysfs_files(struct xhci_hcd *xhci); ++ ++static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) ++{ ++ /* ++ * As of now platform drivers don't provide MSI support so we ensure ++ * here that the generic code does not try to make a pci_dev from our ++ * dev struct in order to setup MSI ++ */ ++ xhci->quirks |= XHCI_PLAT; ++ xhci->quirks |= XHCI_RESET_ON_RESUME; ++ xhci->quirks |= XHCI_SPURIOUS_SUCCESS; ++ // xhci->quirks |= XHCI_TRUST_TX_LENGTH; ++ xhci->hci_version = 0x96; //modified for real version. ++} ++ ++/* called during probe() after chip reset completes */ ++static int xhci_plat_setup(struct usb_hcd *hcd) ++{ ++ return xhci_gen_setup(hcd, xhci_plat_quirks); ++} ++ ++static struct hc_driver mstar_plat_xhci_driver = { ++ .description = "sstar-xhci-hcd", ++ .product_desc = "Sstar xHCI Host Controller", ++ .hcd_priv_size = sizeof(struct xhci_hcd *), ++ ++ /* ++ * generic hardware linkage ++ */ ++ .irq = xhci_irq, ++ .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, ++ ++ /* ++ * basic lifecycle operations ++ */ ++ .reset = xhci_plat_setup, ++ .start = xhci_run, ++ .stop = xhci_stop, ++ .shutdown = xhci_shutdown, ++ ++ /* ++ * managing i/o requests and associated device resources ++ */ ++ .urb_enqueue = xhci_urb_enqueue, ++ .urb_dequeue = xhci_urb_dequeue, ++ .alloc_dev = xhci_alloc_dev, ++ .free_dev = xhci_free_dev, ++ .alloc_streams = xhci_alloc_streams, ++ .free_streams = xhci_free_streams, ++ .add_endpoint = xhci_add_endpoint, ++ .drop_endpoint = xhci_drop_endpoint, ++ .endpoint_reset = xhci_endpoint_reset, ++ .check_bandwidth = xhci_check_bandwidth, ++ .reset_bandwidth = xhci_reset_bandwidth, ++ .address_device = xhci_address_device, ++ .update_hub_device = xhci_update_hub_device, ++ .reset_device = xhci_discover_or_reset_device, ++ ++ /* ++ * scheduling support ++ */ ++ .get_frame_number = xhci_get_frame, ++ ++ /* Root hub support */ ++ .hub_control = xhci_hub_control, ++ .hub_status_data = xhci_hub_status_data, ++ .bus_suspend = xhci_bus_suspend, ++ .bus_resume = xhci_bus_resume, ++}; ++ ++void DEQ_init(uintptr_t U3PHY_D_base, uintptr_t U3PHY_A_base) ++{ ++ writeb(0x00, (void*)(U3PHY_A_base+0xAE*2)); ++ writew(0x080C, (void*)(U3PHY_D_base+0x82*2)); ++ writeb(0x10, (void*)(U3PHY_D_base+0xA4*2)); //0x10 0x30 ++ writew(0x4100, (void*)(U3PHY_D_base+0xA0*2)); ++ ++ writew(0x06, (void*)(U3PHY_A_base+0x06*2)); ++} ++ ++void XHCI_enable_testbus(uintptr_t CHIPTOP_base, uintptr_t U3TOP_base, uintptr_t XHCI_base) ++{ ++ writeb(0x00, (void*)(CHIPTOP_base+0xEC*2)); ++ writeb(0x20, (void*)(CHIPTOP_base+0x24*2)); ++ writeb(0x42, (void*)(CHIPTOP_base+0xEE*2)); // select usb30_test_out ++ // writeb(0x00, (void*)(CHIPTOP_base+0xEA*2)); ++ writeb(0x40, (void*)(CHIPTOP_base+0xEB*2-1)); ++ //writew(0xFFFF, (void*)(CHIPTOP_base+0x12*2)); ++ //writew(0xFFFF, (void*)(CHIPTOP_base+0x14*2)); ++ //writeb(0xFF, (void*)(CHIPTOP_base+0x16*2)); ++ //writeb(0x01, (void*)(CHIPTOP_base+0x21*2-1)); ++ //writeb(0x02, (void*)(CHIPTOP_base+0x3A*2)); ++ ++ //writeb(0x0d, (void*)(U3PHY_D_base+0xD5*2-1)); ++ //writeb(0x23, (void*)(U3PHY_D_base+0x2E*2)); ++ //writeb(0x40, (void*)(U3PHY_D_base+0x2F*2-1)); ++ ++ //writeb(0x09, (void*)(U3TOP_base+0x0C*2)); // [5] = reg_debug_mask to 1'b0 ++ // [4:0] = 0x06= rrdy & wrdy ++ writeb(0x00, (void*)(U3TOP_base+0x0C*2)); ++ ++ writeb(0x11, (void*) (XHCI_base+0x608c)); ++ writeb(0x30, (void*) (XHCI_base+0x608f)); ++ writeb(0x39, (void*) (XHCI_base+0x6805)); ++ writeb(0x3a, (void*) (XHCI_base+0x6806)); ++ writeb(0x21, (void*) (XHCI_base+0x6807)); ++} ++ ++#if defined(XHCI_ENABLE_PPC) ++ ++static void XHCI_enable_PPC(uintptr_t U3TOP_base) ++{ ++ u16 addr_w, bit_num; ++ uintptr_t addr; ++ u8 value, low_active; ++ u8 i, portnum=1; ++ ++ for (i=0; i> 8) & 0x7; ++ low_active = (u8)((addr_w >> 8) & 0x8); ++ break; ++ case 1: ++ addr_w = readw((void*)(U3TOP_base+0xE6*2)); ++ addr = (uintptr_t)addr_w << 8; ++ addr_w = readw((void*)(U3TOP_base+0xE8*2)); ++ addr |= addr_w & 0xFF; ++ bit_num = (addr_w >> 8) & 0x7; ++ low_active = (u8)((addr_w >> 8) & 0x8); ++ break; ++ default: /* "can't happen" */ ++ return; ++ } ++ ++ if (addr) ++ { ++ printk("XHCI_enable_PPC: Turn on USB3.0 port %d power \n", i); ++ printk("Addr: 0x%lx bit_num: %d low_active:%d\n", addr, bit_num, low_active); ++ ++ value = (u8)(1 << bit_num); ++ ++ if (low_active) ++ { ++ if (addr & 0x1) ++ writeb(readb((void*)(_MSTAR_PM_BASE+addr*2-1)) & (u8)(~value), (void*)(_MSTAR_PM_BASE+addr*2-1)); ++ else ++ writeb(readb((void*)(_MSTAR_PM_BASE+addr*2)) & (u8)(~value), (void*)(_MSTAR_PM_BASE+addr*2)); ++ } ++ else ++ { ++ if (addr & 0x1) ++ writeb(readb((void*)(_MSTAR_PM_BASE+addr*2-1)) | value, (void*)(_MSTAR_PM_BASE+addr*2-1)); ++ else ++ writeb(readb((void*)(_MSTAR_PM_BASE+addr*2)) | value, (void*)(_MSTAR_PM_BASE+addr*2)); ++ } ++ } ++ } ++} ++#endif ++ ++void Mstar_U2utmi_init(uintptr_t UTMI_base, uintptr_t U3TOP_base, unsigned int flag) ++{ ++ if ((UTMI_base==0) || (U3TOP_base==0)) ++ return; ++ ++ if (0 == readw((void*)(UTMI_base+0x20*2))) ++ { ++ printk("utmi clk enable\n"); ++ writew(0x8051, (void*) (UTMI_base+0x20*2)); ++ writew(0x2088, (void*) (UTMI_base+0x22*2)); ++ writew(0x0004, (void*) (UTMI_base+0x2*2)); ++ writew(0x6BC3, (void*) (UTMI_base)); ++ mdelay(1); ++ writew(0x69C3, (void*) (UTMI_base)); ++ mdelay(1); ++ writew(0x0001, (void*) (UTMI_base)); ++ mdelay(1); ++ } ++ ++ writeb(0x07, (void*) (UTMI_base+0x8*2)); //default value 0x7; don't change it. ++ ++ if (flag & EHCFLAG_TESTPKG) ++ { ++ writew(0x2084, (void*) (UTMI_base+0x2*2)); ++ writew(0x8051, (void*) (UTMI_base+0x20*2)); ++ } ++ ++#if _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH ++ /* ++ * patch for DM always keep high issue ++ * init overwrite register ++ */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~BIT3), (void*) (UTMI_base+0x0*2)); //DP_PUEN = 0 ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~BIT4), (void*) (UTMI_base+0x0*2)); //DM_PUEN = 0 ++ ++ writeb(readb((void*)(UTMI_base+0x0*2)) & (u8)(~BIT5), (void*) (UTMI_base+0x0*2)); //R_PUMODE = 0 ++ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT6, (void*) (UTMI_base+0x0*2)); //R_DP_PDEN = 1 ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT7, (void*) (UTMI_base+0x0*2)); //R_DM_PDEN = 1 ++ ++ writeb(readb((void*)(UTMI_base+0x10*2)) | BIT6, (void*) (UTMI_base+0x10*2)); //hs_txser_en_cb = 1 ++ writeb(readb((void*)(UTMI_base+0x10*2)) & (u8)(~BIT7), (void*) (UTMI_base+0x10*2)); //hs_se0_cb = 0 ++ ++ /* turn on overwrite mode */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT1, (void*) (UTMI_base+0x0*2)); //tern_ov = 1 ++#endif ++ ++ writeb(readb((void*)(UTMI_base+0x3C*2)) | 0x01, (void*) (UTMI_base+0x3C*2)); // set CA_START as 1 ++ mdelay(1); ++ ++ writeb(readb((void*)(UTMI_base+0x3C*2)) & (u8)(~0x01), (void*) (UTMI_base+0x3C*2)); // release CA_START ++ ++ while ((readb((void*)(UTMI_base+0x3C*2)) & 0x02) == 0); // polling bit <1> (CA_END) ++ ++ if ((0xFFF0 == (readw((void*)(UTMI_base+0x3C*2)) & 0xFFF0 )) || ++ (0x0000 == (readw((void*)(UTMI_base+0x3C*2)) & 0xFFF0 )) ) ++ { ++ printk("WARNING: CA Fail !! \n"); ++ } ++ ++ if (flag & EHCFLAG_DPDM_SWAP) ++ writeb(readb((void*)(UTMI_base+0x0b*2-1)) |0x20, (void*) (UTMI_base+0x0b*2-1)); // dp dm swap ++ ++ writeb((u8)((readb((void*)(UTMI_base+0x06*2)) & 0x9F) | 0x40), (void*) (UTMI_base+0x06*2)); //reg_tx_force_hs_current_enable ++ ++ writeb(readb((void*)(UTMI_base+0x03*2-1)) | 0x28, (void*) (UTMI_base+0x03*2-1)); //Disconnect window select ++ writeb(readb((void*)(UTMI_base+0x03*2-1)) & 0xef, (void*) (UTMI_base+0x03*2-1)); //Disconnect window select ++ ++ writeb(readb((void*)(UTMI_base+0x07*2-1)) & 0xfd, (void*) (UTMI_base+0x07*2-1)); //Disable improved CDR ++ writeb(readb((void*)(UTMI_base+0x09*2-1)) |0x81, (void*) (UTMI_base+0x09*2-1)); // UTMI RX anti-dead-loc, ISI effect improvement ++ writeb(readb((void*)(UTMI_base+0x0b*2-1)) |0x80, (void*) (UTMI_base+0x0b*2-1)); // TX timing select latch path ++ writeb(readb((void*)(UTMI_base+0x15*2-1)) |0x20, (void*) (UTMI_base+0x15*2-1)); // Chirp signal source select ++ ++ //Enable XHCI preamble function with keep-alive ++ writeb(readb((void*)(UTMI_base+0x3F*2-1)) |0x80, (void*) (UTMI_base+0x3F*2-1)); // Enable XHCI preamble function ++ ++#if defined(XHCI_ENABLE_240MHZ) //exclude Agate ++ /* before Madison, bit4 [for 240 setting], bit5 [no use] ++ * after Madison, bit4 [no use], bit5 [for 240 setting] ++ * setting both bits for all chips. ++ */ ++ writeb(readb((void*)(UTMI_base+0x08*2)) | 0x38, (void*) (UTMI_base+0x08*2)); // for 240's phase as 120's clock ++ #if defined(XHCI_USE_120_PHASE) ++ //Fix it for Eiffel Only. ++ writeb(readb((void*)(UTMI_base+0x08*2)) & 0xF7, (void*) (UTMI_base+0x08*2)); // Clear setting of "240's phase as 120's clock" ++ #endif ++#endif ++ ++ // change to 55 timing; for all chips. ++ writeb(readb((void*)(UTMI_base+0x15*2-1)) |0x40, (void*) (UTMI_base+0x15*2-1)); // change to 55 timing ++ ++ // for CLK 120 override enable; for xHCI on all chips ++ writeb(readb((void*)(UTMI_base+0x09*2-1)) |0x04, (void*) (UTMI_base+0x09*2-1)); // for CLK 120 override enable ++ ++ /* Init UTMI disconnect level setting */ ++ writeb(UTMI_DISCON_LEVEL_2A, (void*)(UTMI_base+0x2a*2)); ++ ++ writeb(UTMI_EYE_SETTING_2C, (void*) (UTMI_base+0x2c*2)); ++ writeb(UTMI_EYE_SETTING_2D, (void*) (UTMI_base+0x2d*2-1)); ++ writeb(UTMI_EYE_SETTING_2E, (void*) (UTMI_base+0x2e*2)); ++ writeb(UTMI_EYE_SETTING_2F, (void*) (UTMI_base+0x2f*2-1)); ++ ++#if defined(ENABLE_LS_CROSS_POINT_ECO) ++ writeb(readb((void*)(UTMI_base+0x04*2)) | 0x40, (void*) (UTMI_base+0x04*2)); //enable deglitch SE0¡¨(low-speed cross point) ++#endif ++ ++#if defined(ENABLE_TX_RX_RESET_CLK_GATING_ECO) ++ writeb(readb((void*)(UTMI_base+0x04*2)) | 0x20, (void*) (UTMI_base+0x04*2)); //enable hw auto deassert sw reset(tx/rx reset) ++#endif ++ ++#if defined(ENABLE_KEEPALIVE_ECO) ++ writeb(readb((void*)(UTMI_base+0x04*2)) | 0x80, (void*) (UTMI_base+0x04*2)); //enable LS keep alive & preamble ++#endif ++ ++#if defined(ENABLE_HS_DM_KEEP_HIGH_ECO) ++ /* Change override to hs_txser_en. Dm always keep high issue */ ++ writeb(readb((void*)(UTMI_base+0x10*2)) | BIT6, (void*) (UTMI_base+0x10*2)); ++#endif ++ ++#if _USB_HS_CUR_DRIVE_DM_ALLWAYS_HIGH_PATCH ++ /* ++ * patch for DM always keep high issue ++ * init overwrite register ++ */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT6, (void*) (UTMI_base+0x0*2)); //R_DP_PDEN = 1 ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT7, (void*) (UTMI_base+0x0*2)); //R_DM_PDEN = 1 ++ ++ /* turn on overwrite mode */ ++ writeb(readb((void*)(UTMI_base+0x0*2)) | BIT1, (void*) (UTMI_base+0x0*2)); //tern_ov = 1 ++#endif ++ ++#if _USB_ANALOG_RX_SQUELCH_PATCH ++ /* squelch level adjust by calibration value */ ++ { ++ unsigned int ca_da_ov, ca_db_ov, ca_tmp; ++ ca_tmp = readw((void*)(UTMI_base+0x3c*2)); ++ ca_da_ov = (((ca_tmp >> 4) & 0x3f) - 5) + 0x40; ++ ca_db_ov = (((ca_tmp >> 10) & 0x3f) - 5) + 0x40; ++ printk("[%x]-5 ->(ca_da_ov, ca_db_ov) = (%x,%x)\n", ca_tmp, ca_da_ov, ca_db_ov); ++ writeb(ca_da_ov ,(void*)(UTMI_base+0x3B*2-1)); ++ writeb(ca_db_ov ,(void*)(UTMI_base+0x24*2)); ++ } ++#endif ++ ++#if (XHCI_CHIRP_PATCH) ++ writeb(UTMI_DISCON_LEVEL_2A, (void*) (UTMI_base+0x3E*2)); //override value ++ writeb((u8)((readb((void*)(U3TOP_base+0x24*2)) & 0xF0) | 0x0A), (void*)(U3TOP_base+0x24*2)); // set T1=50, T2=20 ++ writeb(readb((void*)(UTMI_base+0x3F*2-1)) | 0x1, (void*) (UTMI_base+0x3F*2-1)); //enable the patch ++#endif ++ ++ if (flag & EHCFLAG_TESTPKG) ++ { ++ writew(0x0600, (void*) (UTMI_base+0x14*2)); ++ writew(0x0078, (void*) (UTMI_base+0x10*2)); ++ writew(0x0BFE, (void*) (UTMI_base+0x32*2)); ++ } ++} ++ ++ ++#if defined(XHCI_PHY_MS40) ++static void Mstar_U3phy_MS40_init(uintptr_t U3PHY_D_base, uintptr_t U3PHY_A_base) ++{ ++ ++ //U3phy initial sequence ++ writew(0x0, (void*) (U3PHY_A_base)); // power on rx atop ++ writew(0x0, (void*) (U3PHY_A_base+0x2*2)); // power on tx atop ++ writew(0x0910, (void*) (U3PHY_D_base+0x4*2)); ++ writew(0x0, (void*) (U3PHY_A_base+0x3A*2)); ++ writew(0x0160, (void*) (U3PHY_D_base+0x18*2)); ++ writew(0x0, (void*) (U3PHY_D_base+0x20*2)); // power on u3_phy clockgen ++ writew(0x0, (void*) (U3PHY_D_base+0x22*2)); // power on u3_phy clockgen ++ ++ writew(0x013F, (void*) (U3PHY_D_base+0x4A*2)); ++ writew(0x1010, (void*) (U3PHY_D_base+0x4C*2)); ++ ++ writew(0x0, (void*) (U3PHY_A_base+0x3A*2)); // override PD control ++ writeb(0x1C, (void*) (U3PHY_A_base+0xCD*2-1)); // reg_test_usb3aeq_acc; long EQ converge ++ writeb(0x40, (void*) (U3PHY_A_base+0xC9*2-1)); // reg_gcr_usb3aeq_threshold_abs ++ writeb(0x10, (void*) (U3PHY_A_base+0xE5*2-1)); // [4]: AEQ select PD no-delay and 2elay path, 0: delay, 1: no- ++ writeb(0x11, (void*) (U3PHY_A_base+0xC6*2)); // analog symbol lock and EQ converage step ++ writeb(0x02, (void*) (U3PHY_D_base+0xA0*2)); // [1] aeq mode ++ ++ writeb(0x07, (void*) (U3PHY_A_base+0xB0*2)); // reg_gcr_usb3rx_eq_str_ov_value ++ ++#if (ENABLE_XHCI_SSC) ++ writew(0x04D8, (void*) (U3PHY_D_base+0xC6*2)); //reg_tx_synth_span ++ writew(0x0003, (void*) (U3PHY_D_base+0xC4*2)); //reg_tx_synth_step ++ writew(0x9375, (void*) (U3PHY_D_base+0xC0*2)); //reg_tx_synth_set ++ writeb(0x18, (void*) (U3PHY_D_base+0xC2*2)); //reg_tx_synth_set ++#endif ++ ++ ////Set Tolerance //only for Agate_U01 ++ /// writew(0x0103, (void*) (U3PHY_D_base+0x44*2)); ++ ++ // Comma ++ // writeb(0x84, (void*) (U3PHY_A_base+0xCD*2-1)); // reg_test_aeq_acc, 8bit ++ ++ // RX phase control ++ writew(0x0100, (void*)(U3PHY_A_base+0x90*2)); ++ writew(0x0302, (void*)(U3PHY_A_base+0x92*2)); ++ writew(0x0504, (void*)(U3PHY_A_base+0x94*2)); ++ writew(0x0706, (void*)(U3PHY_A_base+0x96*2)); ++ writew(0x1708, (void*)(U3PHY_A_base+0x98*2)); ++ writew(0x1516, (void*)(U3PHY_A_base+0x9A*2)); ++ writew(0x1314, (void*)(U3PHY_A_base+0x9C*2)); ++ writew(0x1112, (void*)(U3PHY_A_base+0x9E*2)); ++ writew(0x3000, (void*)(U3PHY_D_base+0xA8*2)); ++ writew(0x7380, (void*)(U3PHY_A_base+0x40*2)); ++ ++#if (XHCI_ENABLE_DEQ) ++ DEQ_init(U3PHY_D_base, U3PHY_A_base); ++#endif ++ ++#if (XHCI_TX_SWING_PATCH) ++ writeb(0x3F, (void*)(U3PHY_A_base+0x60*2)); ++ writeb(0x39, (void*)(U3PHY_A_base+0x62*2)); ++#endif ++} ++#endif ++ ++#if defined(XHCI_PHY_MS28) ++static void Mstar_U3phy_MS28_init(uintptr_t U3PHY_D_base, uintptr_t U3PHY_A_base, unsigned int flag) ++{ ++#ifdef XHCI_SINGLE_PORT_ENABLE_MAC ++ writeb(readb((void*)(U3PHY_D_base+0x84*2))| 0x40, (void*)(U3PHY_D_base+0x84*2)); // open XHCI MAC clock ++#endif ++ ++ if (flag & XHCFLAG_DEGRADATION) { ++ #ifdef XHCI_DEGRAD_REP ++ writeb(readb((void*)(U3PHY_D_base+0xB6*2))| BIT0, (void*)(U3PHY_D_base+0xB6*2)); ++ writew(0x03E8, (void*) (U3PHY_D_base+0xA*2)); ++ #endif ++ } ++ ++ //-- 28 hpm mstar only--- ++ writew(0x0104, (void*) (U3PHY_A_base+0x6*2)); // for Enable 1G clock pass to UTMI //[2] reg_pd_usb3_purt [7:6] reg_gcr_hpd_vsel ++ ++ //U3phy initial sequence ++ writew(0x0, (void*) (U3PHY_A_base)); // power on rx atop ++ writew(0x0, (void*) (U3PHY_A_base+0x2*2)); // power on tx atop ++ //writew(0x0910, (void*) (U3PHY_D_base+0x4*2)); // the same as default ++ writew(0x0, (void*) (U3PHY_A_base+0x3A*2)); // overwrite power on rx/tx atop ++ writew(0x0160, (void*) (U3PHY_D_base+0x18*2)); ++ writew(0x0, (void*) (U3PHY_D_base+0x20*2)); // power on u3_phy clockgen ++ writew(0x0, (void*) (U3PHY_D_base+0x22*2)); // power on u3_phy clockgen ++ ++ //writew(0x013F, (void*) (U3PHY_D_base+0x4A*2)); // the same as default ++ //writew(0x1010, (void*) (U3PHY_D_base+0x4C*2)); // the same as default ++ ++ writew(0x0, (void*) (U3PHY_A_base+0x3A*2)); // override PD control ++#ifdef XHCI_ENABLE_PD_OVERRIDE ++ writew(0x308, (void*) (U3PHY_A_base+0x3A*2)); // [9,8,3] PD_TXCLK_USB3TXPLL, PD_USB3_IBIAS, PD_USB3TXPLL override enable ++ writeb(readb((void*)(U3PHY_A_base+0x3*2-1)) & 0xbb, (void*)(U3PHY_A_base+0x3*2-1)); // override value 0 ++#endif ++ ++#if 0 // not for MS28 ++ writeb(0x1C, (void*) (U3PHY_A_base+0xCD*2-1)); // reg_test_usb3aeq_acc; long EQ converge ++ writeb(0x40, (void*) (U3PHY_A_base+0xC9*2-1)); // reg_gcr_usb3aeq_threshold_abs ++ writeb(0x10, (void*) (U3PHY_A_base+0xE5*2-1)); // [4]: AEQ select PD no-delay and 2elay path, 0: delay, 1: no- ++ writeb(0x11, (void*) (U3PHY_A_base+0xC6*2)); // analog symbol lock and EQ converage step ++ writeb(0x02, (void*) (U3PHY_D_base+0xA0*2)); // [1] aeq mode ++ ++ writeb(0x07, (void*) (U3PHY_A_base+0xB0*2)); // reg_gcr_usb3rx_eq_str_ov_value ++#endif ++ ++#if (ENABLE_XHCI_SSC) ++#ifdef XHCI_SSC_TX_SYNTH_SET_C0 ++ writew(XHCI_SSC_TX_SYNTH_SET_C0, (void*) (U3PHY_D_base+0xC0*2)); //reg_tx_synth_set ++ writeb(XHCI_SSC_TX_SYNTH_SET_C2, (void*) (U3PHY_D_base+0xC2*2)); //reg_tx_synth_set ++ writew(XHCI_SSC_TX_SYNTH_STEP_C4, (void*) (U3PHY_D_base+0xC4*2)); //reg_tx_synth_step ++ writew(XHCI_SSC_TX_SYNTH_SPAN_C6, (void*) (U3PHY_D_base+0xC6*2)); //reg_tx_synth_span ++#else ++ writew(0x04D0, (void*) (U3PHY_D_base+0xC6*2)); //reg_tx_synth_span ++ writew(0x0003, (void*) (U3PHY_D_base+0xC4*2)); //reg_tx_synth_step ++ writew(0x9375, (void*) (U3PHY_D_base+0xC0*2)); //reg_tx_synth_set ++ writeb(0x18, (void*) (U3PHY_D_base+0xC2*2)); //reg_tx_synth_set ++#endif ++#endif ++ ++ // -- TX current --- ++ //writeb(0x01, (void*) (U3PHY_A_base+0x35*2-1)); ++ writew(0x3939 /* 0x3932 */, (void*) (U3PHY_A_base+0x60*2)); ++ writew(0x3924 /* 0x3939 */, (void*) (U3PHY_A_base+0x62*2)); ++ writew(0x3932, (void*) (U3PHY_A_base+0x64*2)); ++ writew(0x3939, (void*) (U3PHY_A_base+0x66*2)); ++ writew(0x0400, (void*) (U3PHY_A_base+0x12*2)); ++ // --------------- ++ ++ //-------- New for MS28 --------- ++ writeb(0x0, (void*) (U3PHY_A_base+0xA1*2-1)); //bit[15] EQ override ++ writeb(0xF4, (void*) (U3PHY_D_base+0x12*2)); //TX lock threshold ++ ++ writeb(readb((void*)(U3PHY_A_base+0xF*2-1))&(u8)(~0x4), (void*)(U3PHY_A_base+0xF*2-1)); // 0xF[10] Fix AEQ RX-reset issue ++ ++#ifdef XHCI_PHY_ENABLE_RX_LOCK ++ writeb(readb((void*)(U3PHY_A_base+0x21*2-1)) | 0x80, (void*)(U3PHY_A_base+0x21*2-1)); // enable rx_lock behavior. ++#endif ++ ++#ifdef XHCI_PWS_P2 ++ writeb(readb((void*)(U3PHY_D_base+0x1E*2))| 0x1, (void*)(U3PHY_D_base+0x1E*2)); //P2 power saving ++#endif ++ ++} ++#endif ++ ++#ifdef U3PHY_RX_DETECT_POWER_SAVING ++/* 20170522, U3PHY new power saveing mode */ ++void Mstar_U3phy_power_saving(uintptr_t U3PHY_D_base, u8 regval) ++{ ++ u8 c_val; ++ ++ c_val = readb((void*)(U3PHY_D_base+0x3F*2-1)) & 0xf; ++ if ((c_val & 0xf) == regval) // the same setting ++ return; ++ ++ c_val &= ~0xf; ++ c_val |= regval; ++ writeb(c_val, (void*)(U3PHY_D_base+0x3F*2-1)); ++} ++#endif ++ ++#if defined(ENABLE_USB_NEW_MIU_SLE) ++void MIU_select_setting_xhc(uintptr_t U3TOP_base) ++{ ++ printk("[USB] config miu select [%02x] [%02x] [%02x] [%02x]\n", USB_MIU_SEL0, USB_MIU_SEL1, USB_MIU_SEL2, USB_MIU_SEL3); ++ writeb(USB_MIU_SEL0, (void*)(U3TOP_base+0x3A*2)); //Setting MIU0 segment ++ writeb(USB_MIU_SEL1, (void*)(U3TOP_base+0x36*2)); //Setting MIU1 segment ++ writeb(USB_MIU_SEL2, (void*)(U3TOP_base+0x37*2-1)); //Setting MIU2 segment ++ writeb(USB_MIU_SEL3, (void*)(U3TOP_base+0x38*2)); //Setting MIU3 segment ++ writeb(readb((void*)(U3TOP_base+0x39*2-1)) | BIT6, (void*)(U3TOP_base+0x39*2-1)); //Enable miu partition mechanism ++#if !defined(DISABLE_MIU_LOW_BOUND_ADDR_SUBTRACT_ECO) ++ printk("[USB] enable miu lower bound address subtraction\n"); ++ writeb(readb((void*)(U3TOP_base+0x39*2-1)) | BIT7, (void*)(U3TOP_base+0x39*2-1)); ++#endif ++ ++} ++#endif ++ ++static void Mstar_xhc_init(const struct u3phy_addr_base *u3phy_addr, ++ unsigned int flag) ++{ ++ uintptr_t UTMI_base = u3phy_addr->utmi_base; ++ uintptr_t XHCI_base = u3phy_addr->xhci_base; ++ uintptr_t U3TOP_base = u3phy_addr->u3top_base; ++ ++ printk("Mstar_xhc_init version:%s\n", XHCI_MSTAR_VERSION); ++ ++ // Init USB2 UTMI ++ Mstar_U2utmi_init(UTMI_base, U3TOP_base, flag); ++ ++ // Init USB3 PHY ++#ifdef U3PHY_RX_DETECT_POWER_SAVING ++ Mstar_U3phy_power_saving(u3phy_addr->u3dtop_base, 0xf); ++#endif ++ ++#if defined(XHCI_PHY_MS28) ++ Mstar_U3phy_MS28_init(u3phy_addr->u3dtop_base, u3phy_addr->u3atop_base, flag); ++ #if defined(XHCI_2PORTS) && !defined(CONFIG_MSTAR_XUSB_PCIE_PLATFORM) ++ Mstar_U3phy_MS28_init(u3phy_addr->u3dtop1_base, u3phy_addr->u3atop1_base, flag); ++ #endif ++#elif defined(XHCI_PHY_MS40) ++ Mstar_U3phy_MS40_init(u3phy_addr->u3dtop_base, u3phy_addr->u3atop_base); ++#else ++ #error Unknown xHCI PHY ++#endif ++ ++#if defined(ENABLE_USB_NEW_MIU_SLE) ++ MIU_select_setting_xhc(U3TOP_base); ++#endif ++ ++ //First token idle ++ writeb(readb((void*)(XHCI_base+0x4308)) | 0x0C, (void*)(XHCI_base+0x4308)); //First token idle (bit2~3 = "11") ++ //Inter packet delay ++ writeb(readb((void*)(XHCI_base+0x430F)) | 0xC0, (void*)(XHCI_base+0x430F)); //Inter packet delay (bit6~7 = "11") ++ //LFPS patch ++ writeb(readb((void*)(XHCI_base+0x681A)) | 0x10, (void*)(XHCI_base+0x681A)); //LFPS patch (bit4 = 1) ++ ++ //Ignore checking of max packet size=0 in endpoint context (configure endpoint). ++ writeb(readb((void*)(XHCI_base+0x4209)) | 0x08, (void*)(XHCI_base+0x4209)); //for SS_BI_0 ++ writeb(readb((void*)(XHCI_base+0x4249)) | 0x08, (void*)(XHCI_base+0x4249)); //for SS_BI_1 ++ ++ //force one queue option for IN direction ++ writeb(readb((void*)(XHCI_base+0x4210)) | 0x01, (void*)(XHCI_base+0x4210)); ++ ++ //mask tx and rx stop ep cmd to avoid stop cmd halt issue ++ writeb(readb((void*)(XHCI_base+0x4291)) | (BIT5|BIT6), (void*)(XHCI_base+0x4291)); ++ ++#if defined(XHCI_DISABLE_COMPLIANCE) ++ writeb(readb((void*)(XHCI_base+0x6817)) | 0x80, (void*)(XHCI_base+0x6817)); ++#endif ++ ++ //Bus Reset setting => default 50ms; T1=30; T2=20 ++#if defined(XHCI_BUSRESET_REG_OFFSET_CHG) ++ writeb((readb((void*)(U3TOP_base+XHCI_NEW_BUSRESET_REG_OFFSET)) & 0xF0) | 0x8, (void*)(U3TOP_base+XHCI_NEW_BUSRESET_REG_OFFSET)); ++#else ++ writeb((u8)((readb((void*)(U3TOP_base+0x24*2)) & 0xF0) | 0x8), (void*)(U3TOP_base+0x24*2)); // [5] = reg_debug_mask to 1'b0 ++#endif ++ ++#if defined(XHCI_ENABLE_LASTDOWNZ) ++ writeb(readb((void*)(U3TOP_base+0x12*2)) | 0x8, (void*)(U3TOP_base+0x12*2)); //check both last_down_z & data count enable ++#endif ++ ++#if defined(XHCI_MIU1_SEL_BIT30) ++ writeb(readb((void*)(U3TOP_base+0x11*2-1)) | 0x2, (void*)(U3TOP_base+0x11*2-1)); //set reg_miu1_sel to check address bit 30 ++#endif ++ ++#if defined(XHCI_MIU_PROTECT_ENABLE) ++ writeb(readb((void*)(U3TOP_base+0x21*2-1)) | 0x8, (void*)(U3TOP_base+0x21*2-1)); // enable miu protect ECO ++#endif ++ ++#if defined (XHCI_ENABLE_LOOPBACK_ECO) ++ writeb(readb((void*)(U3TOP_base+LOOPBACK_ECO_OFFSET))|LOOPBACK_ECO_BIT , (void*)(U3TOP_base+LOOPBACK_ECO_OFFSET)); ++#endif ++ ++#if defined(XHCI_ENABLE_HOTRESET_ECO) ++ //Re-enable again to prevent from overwitting by sboot PPC function. Only for Edison. ++ writeb(readb((void*)(U3TOP_base+0xFF*2-1))|0x80, (void*)(U3TOP_base+0xFF*2-1)); ++#endif ++ ++#if defined(XHCI_ALLOW_LOOPBACK_MODE) //only for Nike, allow HW enter loopback mode ++ writeb(readb((void*)(U3TOP_base+0xf8*2)) | 0x1, (void*)(U3TOP_base+0xf8*2)); ++#endif ++ ++#if (XHCI_ENABLE_TESTBUS) ++ XHCI_enable_testbus((_MSTAR_USB_BASEADR+(0x1E00*2)), U3TOP_base, XHCI_base); ++#endif ++ ++#if defined(XHCI_ENABLE_PPC) && !defined(XHCI_DISABLE_SS_MODE) ++ XHCI_enable_PPC(U3TOP_base); ++#endif ++ ++ // SW note U3Phy init done. ++ writeb(readb((void*)(U3TOP_base+0xEA*2)) | BIT0, (void*)(U3TOP_base+0xEA*2)); ++ // Don't wait trbp response when link not in U0 ++ writeb(readb((void*)(XHCI_base+0x4205)) | 0x80, (void*)(XHCI_base+0x4205)); ++} ++ ++unsigned int mstar_xhci_get_flag(struct platform_device *pdev) ++{ ++ unsigned int flag=0; ++ ++#if defined(XHCI_ENABLE_DPDM_SWAP) ++ flag |= EHCFLAG_DPDM_SWAP; ++#endif ++ ++ // get degration flag ++ ++ return flag; ++} ++ ++ ++#if defined(CONFIG_OF) ++extern unsigned int irq_of_parse_and_map(struct device_node *node, int index); ++#endif ++ ++static int xhci_mstar_plat_probe(struct platform_device *pdev) ++{ ++ const struct hc_driver *driver; ++ struct xhci_hcd *xhci; ++ struct usb_hcd *hcd; ++ int ret; ++ int irq; ++ unsigned int flag=0; ++#if defined(CONFIG_OF) ++ u64 dma_mask; ++#endif ++ struct u3phy_addr_base u3phy_init_addr; ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ printk("xHCI_%x%04x \n", readb((void*)(_MSTAR_PM_BASE+0x1ECC*2)), readw((void*)(_MSTAR_PM_BASE+0x1ECE*2))); ++ printk("Sstar-xhci H.W init\n"); ++ ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", strlen("soc:Sstar-xhci-1")) ) ++ { ++ #ifdef DISABLE_FIRST_XHC ++ printk("[XHCI] can't init first xHCI due to DISABLE_FIRST_XHC.....\n"); ++ return -ENODEV; ++ #endif ++ } ++ else if( 0==strncmp(pdev->name, "soc:Sstar-xhci-2", strlen("soc:Sstar-xhci-2")) ) ++ { ++ #ifdef DISABLE_SECOND_XHC ++ printk("[XHCI] can't init second xHCI due to DISABLE_SECOND_XHC.....\n"); ++ return -ENODEV; ++ #endif ++ } ++ ++#ifdef ENABLE_SECOND_XHC /* 2 roots case */ ++ #define NAME_LEN (16) ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", NAME_LEN) ) ++ { ++ u3phy_init_addr.utmi_base = _MSTAR_U3UTMI0_BASE; ++ u3phy_init_addr.xhci_base = _MSTAR_XHCI0_BASE; ++ u3phy_init_addr.u3top_base = _MSTAR_U3TOP0_BASE; ++ u3phy_init_addr.bc_base = _MSTAR_U3BC0_BASE; ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP0_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP0_BASE; ++ } ++ else if(0==strncmp(pdev->name, "soc:Sstar-xhci-2", NAME_LEN)) { ++ u3phy_init_addr.utmi_base = _MSTAR_U3UTMI1_BASE; ++ u3phy_init_addr.xhci_base = _MSTAR_XHCI1_BASE; ++ u3phy_init_addr.u3top_base = _MSTAR_U3TOP1_BASE; ++ u3phy_init_addr.bc_base = _MSTAR_U3BC1_BASE; ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP1_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP1_BASE; ++ } ++#else /* one root case */ ++ u3phy_init_addr.utmi_base = _MSTAR_U3UTMI_BASE; ++ u3phy_init_addr.xhci_base = _MSTAR_XHCI_BASE; ++ u3phy_init_addr.u3top_base = _MSTAR_U3TOP_BASE; ++ u3phy_init_addr.bc_base = _MSTAR_U3BC_BASE; ++#if defined(XHCI_PHY_MS28) ++ #if defined(XHCI_2PORTS) ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_P0_DTOP_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_P0_ATOP_BASE; ++ u3phy_init_addr.u3dtop1_base = _MSTAR_U3PHY_P1_DTOP_BASE; ++ u3phy_init_addr.u3atop1_base = _MSTAR_U3PHY_P1_ATOP_BASE; ++ #else ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP_BASE; ++ #endif ++#elif defined(XHCI_PHY_MS40) ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP_BASE; ++#else ++ #error Unknown xHCI PHY ++#endif ++#endif ++ ++ flag |= mstar_xhci_get_flag(pdev); ++ ++ Mstar_xhc_init(&u3phy_init_addr, flag); ++ ++ driver = &mstar_plat_xhci_driver; ++ ++#if defined(CONFIG_OF) ++ if (!pdev->dev.platform_data) ++ { ++ printk(KERN_WARNING "[USB][XHC] no platform_data, device tree coming\n"); ++ } ++ ++ if(IS_ENABLED(CONFIG_ARM64) && IS_ENABLED(CONFIG_ZONE_DMA)) ++ { ++#if defined(XHC_DMA_BIT_MASK) ++ dma_mask = XHC_DMA_BIT_MASK; ++#else ++ /* default: 32bit to mask lowest 4G address */ ++ dma_mask = DMA_BIT_MASK(32); ++#endif ++ } else ++ dma_mask = DMA_BIT_MASK(64); ++ ++ if (dma_set_mask_and_coherent(&pdev->dev, dma_mask) ) { ++ printk(KERN_ERR "[USB][XHC] cannot accept dma mask 0x%llx\n", dma_mask); ++ return -EOPNOTSUPP; ++ } ++ ++ printk(KERN_NOTICE "[USB][XHC] dma coherent_mask 0x%llx mask 0x%llx\n", ++ pdev->dev.coherent_dma_mask, *pdev->dev.dma_mask); ++ ++ /* try to get irq from device tree */ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++#else ++ irq = platform_get_irq(pdev, 0); ++#endif ++ ++ #if !defined(ENABLE_IRQ_REMAP) ++ if (irq < 0) ++ return -ENODEV; ++ #endif ++ ++ #if defined(ENABLE_IRQ_REMAP) ++ #ifdef ENABLE_SECOND_XHC ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", NAME_LEN) ) ++ irq = MSTAR_XHCI_IRQ; ++ else if( 0==strncmp(pdev->name, "soc:Sstar-xhci-2", NAME_LEN) ) ++ irq = MSTAR_XHCI2_IRQ; ++ #else /* one root case */ ++ irq = MSTAR_XHCI_IRQ; ++ #endif ++ #endif ++ ++ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++#ifdef ENABLE_SECOND_XHC ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", NAME_LEN) ) ++ hcd->rsrc_start = _MSTAR_XHCI0_BASE; ++ else if( 0==strncmp(pdev->name, "soc:Sstar-xhci-2", NAME_LEN) ) ++ hcd->rsrc_start = _MSTAR_XHCI1_BASE; ++#else /* one root case */ ++ hcd->rsrc_start = _MSTAR_XHCI_BASE; ++#endif ++ hcd->rsrc_len = 0x4000<<1; ++ ++ hcd->regs = (void *)(uintptr_t)(hcd->rsrc_start); ++ if (!hcd->regs) { ++ dev_dbg(&pdev->dev, "error mapping memory\n"); ++ ret = -EFAULT; ++ goto put_hcd; ++ } ++ ++#ifdef ENABLE_SECOND_XHC ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", NAME_LEN) ) { ++ hcd->xhci_base = _MSTAR_XHCI0_BASE; ++ hcd->u3top_base = _MSTAR_U3TOP0_BASE; ++ hcd->utmi_base = _MSTAR_U3UTMI0_BASE; ++ hcd->bc_base = _MSTAR_U3BC0_BASE; ++ hcd->u3dphy_base[0] = _MSTAR_U3PHY_DTOP0_BASE; ++ hcd->port_index = 1; ++ } ++ else if( 0==strncmp(pdev->name, "soc:Sstar-xhci-2", NAME_LEN) ) { ++ hcd->xhci_base = _MSTAR_XHCI1_BASE; ++ hcd->u3top_base = _MSTAR_U3TOP1_BASE; ++ hcd->utmi_base = _MSTAR_U3UTMI1_BASE; ++ hcd->bc_base = _MSTAR_U3BC1_BASE; ++ hcd->u3dphy_base[0] = _MSTAR_U3PHY_DTOP1_BASE; ++ hcd->port_index = 2; ++ } ++#else /* one root case */ ++ hcd->xhci_base = _MSTAR_XHCI_BASE; ++ hcd->u3top_base = _MSTAR_U3TOP_BASE; ++ hcd->utmi_base = _MSTAR_U3UTMI_BASE; ++ hcd->bc_base = _MSTAR_U3BC_BASE; ++#ifdef XHCI_PHY_MS28 ++ #ifdef XHCI_2PORTS ++ hcd->u3dphy_base[0] = _MSTAR_U3PHY_P0_DTOP_BASE; ++ hcd->u3dphy_base[1] = _MSTAR_U3PHY_P1_DTOP_BASE; ++ #else ++ hcd->u3dphy_base[0] = _MSTAR_U3PHY_DTOP_BASE; ++ #endif ++#endif ++#endif ++ ++ //Disable default setting. ++ usb_bc_enable(hcd, false); ++ ++#if _UTMI_PWR_SAV_MODE_ENABLE ++ usb_power_saving_enable(hcd, true); ++#endif ++ ++#ifdef USB3_MAC_SRAM_POWER_DOWN_ENABLE ++ usb30mac_sram_power_saving(hcd, true); ++#endif ++ ++ xhci = hcd_to_xhci(hcd); ++ xhci->main_hcd = hcd; ++ xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev, ++ dev_name(&pdev->dev), hcd); ++ if (!xhci->shared_hcd) { ++ ret = -ENOMEM; ++ goto put_hcd; ++ } ++ ++#ifdef ENABLE_SECOND_XHC ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", NAME_LEN) ) { ++ xhci->shared_hcd->xhci_base = _MSTAR_XHCI0_BASE; ++ xhci->shared_hcd->u3top_base = _MSTAR_U3TOP0_BASE; ++ xhci->shared_hcd->utmi_base = _MSTAR_U3UTMI0_BASE; ++ xhci->shared_hcd->bc_base = _MSTAR_U3BC0_BASE; ++ xhci->shared_hcd->u3dphy_base[0] = _MSTAR_U3PHY_DTOP0_BASE; ++ xhci->shared_hcd->port_index = 1; ++ } ++ else if( 0==strncmp(pdev->name, "soc:Sstar-xhci-2", NAME_LEN) ) { ++ xhci->shared_hcd->xhci_base = _MSTAR_XHCI1_BASE; ++ xhci->shared_hcd->u3top_base = _MSTAR_U3TOP1_BASE; ++ xhci->shared_hcd->utmi_base = _MSTAR_U3UTMI1_BASE; ++ xhci->shared_hcd->bc_base = _MSTAR_U3BC1_BASE; ++ xhci->shared_hcd->u3dphy_base[0] = _MSTAR_U3PHY_DTOP1_BASE; ++ xhci->shared_hcd->port_index = 2; ++ } ++#else /* one root case */ ++ xhci->shared_hcd->xhci_base = _MSTAR_XHCI_BASE; ++ xhci->shared_hcd->u3top_base = _MSTAR_U3TOP_BASE; ++ xhci->shared_hcd->utmi_base = _MSTAR_U3UTMI_BASE; ++ xhci->shared_hcd->bc_base = _MSTAR_U3BC_BASE; ++#ifdef XHCI_PHY_MS28 ++ #ifdef XHCI_2PORTS ++ xhci->shared_hcd->u3dphy_base[0] = _MSTAR_U3PHY_P0_DTOP_BASE; ++ xhci->shared_hcd->u3dphy_base[1] = _MSTAR_U3PHY_P1_DTOP_BASE; ++ #else ++ xhci->shared_hcd->u3dphy_base[0] = _MSTAR_U3PHY_DTOP_BASE; ++ #endif ++#endif ++#endif ++ ++ /* IRQF_DISABLED was removed from kernel 4.1 ++ commit d8bf368d0631d4bc2612d8bf2e4e8e74e620d0cc. */ ++ ret = usb_add_hcd(hcd, (unsigned int)irq, 0); ++ if (ret) ++ goto put_usb3_hcd; ++ ++ ret = usb_add_hcd(xhci->shared_hcd, (unsigned int)irq, 0); ++ if (ret) ++ goto dealloc_usb2_hcd; ++ ++#if defined(XHCI_ENABLE_PPC) && defined(XHCI_DISABLE_SS_MODE) ++ //disable SS mode ++ { ++ int i; ++ for (i=1; i<=xhci->num_usb3_ports; i++) ++ xhci_hub_control(xhci->shared_hcd, ClearPortFeature, USB_PORT_FEAT_ENABLE, i, NULL, 0); ++ } ++ XHCI_enable_PPC(hcd->u3top_base); ++#endif ++ ++//================================= ++ create_xhci_sysfs_files(xhci); ++//================================= ++ ++ return 0; ++ ++ ++dealloc_usb2_hcd: ++ usb_remove_hcd(hcd); ++ ++put_usb3_hcd: ++ usb_put_hcd(xhci->shared_hcd); ++ ++put_hcd: ++ usb_put_hcd(hcd); ++ ++ return ret; ++} ++ ++static int xhci_mstar_plat_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ ++//================================= ++ remove_xhci_sysfs_files(xhci); ++//================================= ++ ++ usb_remove_hcd(xhci->shared_hcd); ++ usb_remove_hcd(hcd); ++ ++ usb_put_hcd(xhci->shared_hcd); ++ usb_put_hcd(hcd); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int xhci_hcd_mstar_drv_suspend(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ ++ ++ printk("xhci_hcd_mstar_drv_suspend \n"); ++ ++ return xhci_suspend(xhci, device_may_wakeup(dev)); ++} ++ ++static int xhci_hcd_mstar_drv_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ unsigned int flag=0; ++ int retval = 0; ++ struct u3phy_addr_base u3phy_init_addr; ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ printk("xhci_hcd_mstar_drv_resume \n"); ++ ++#ifdef ENABLE_SECOND_XHC /* 2 roots case */ ++ { ++ #define NAME_LEN (16) ++ ++ if( 0==strncmp(pdev->name, "soc:Sstar-xhci-1", NAME_LEN) ) { ++ u3phy_init_addr.utmi_base = _MSTAR_U3UTMI0_BASE; ++ u3phy_init_addr.xhci_base = _MSTAR_XHCI0_BASE; ++ u3phy_init_addr.u3top_base = _MSTAR_U3TOP0_BASE; ++ u3phy_init_addr.bc_base = _MSTAR_U3BC0_BASE; ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP0_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP0_BASE; ++ } ++ else if( 0==strncmp(pdev->name, "soc:Sstar-xhci-2", NAME_LEN) ) { ++ u3phy_init_addr.utmi_base = _MSTAR_U3UTMI1_BASE; ++ u3phy_init_addr.xhci_base = _MSTAR_XHCI1_BASE; ++ u3phy_init_addr.u3top_base = _MSTAR_U3TOP1_BASE; ++ u3phy_init_addr.bc_base = _MSTAR_U3BC1_BASE; ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP1_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP1_BASE; ++ } ++ } ++#else /* one root case */ ++ u3phy_init_addr.utmi_base = _MSTAR_U3UTMI_BASE; ++ u3phy_init_addr.xhci_base = _MSTAR_XHCI_BASE; ++ u3phy_init_addr.u3top_base = _MSTAR_U3TOP_BASE; ++ u3phy_init_addr.bc_base = _MSTAR_U3BC_BASE; ++#if defined(XHCI_PHY_MS28) ++ #if defined(XHCI_2PORTS) ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_P0_DTOP_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_P0_ATOP_BASE; ++ u3phy_init_addr.u3dtop1_base = _MSTAR_U3PHY_P1_DTOP_BASE; ++ u3phy_init_addr.u3atop1_base = _MSTAR_U3PHY_P1_ATOP_BASE; ++ #else ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP_BASE; ++ #endif ++#elif defined(XHCI_PHY_MS40) ++ u3phy_init_addr.u3dtop_base = _MSTAR_U3PHY_DTOP_BASE; ++ u3phy_init_addr.u3atop_base = _MSTAR_U3PHY_ATOP_BASE; ++#else ++ #error Unknown xHCI PHY ++#endif ++#endif ++ ++ flag |= mstar_xhci_get_flag(pdev); ++ ++ Mstar_xhc_init(&u3phy_init_addr, flag); ++ ++ //Disable default setting. ++ usb_bc_enable(hcd, false); ++ ++ retval = xhci_resume(xhci, false); ++ if (retval) { ++ printk(" xhci_resume FAIL : -0x%x !!", -retval); ++ return retval; ++ } ++ ++#if defined(XHCI_ENABLE_PPC) && defined(XHCI_DISABLE_SS_MODE) ++ //disable SS mode ++ { ++ int i; ++ for (i=1; i<=xhci->num_usb3_ports; i++) ++ xhci_hub_control(xhci->shared_hcd, ClearPortFeature, USB_PORT_FEAT_ENABLE, i, NULL, 0); ++ } ++ XHCI_enable_PPC(hcd->u3top_base); ++#endif ++ ++ return 0; ++} ++static const struct dev_pm_ops mstar_xhci_plat_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(xhci_hcd_mstar_drv_suspend, xhci_hcd_mstar_drv_resume) ++}; ++#define DEV_PM_OPS (&mstar_xhci_plat_pm_ops) ++#else ++#define DEV_PM_OPS NULL ++#endif /* CONFIG_PM_SLEEP */ ++ ++#if defined(CONFIG_OF) ++static struct of_device_id mstar_xhci_of_device_ids[] = { ++ {.compatible = "Sstar-xhci-1"}, ++ {}, ++}; ++#ifdef ENABLE_SECOND_XHC ++static struct of_device_id mstar_xhci_1_of_device_ids[] = { ++ {.compatible = "Sstar-xhci-2"}, ++ {}, ++}; ++#endif ++#endif ++ ++static struct platform_driver xhci_mstar_driver = { ++ ++ .probe = xhci_mstar_plat_probe, ++ .remove = xhci_mstar_plat_remove, ++ ++ .driver = { ++ .name = "Sstar-xhci-1", ++ .pm = DEV_PM_OPS, ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_xhci_of_device_ids, ++#endif ++ }, ++}; ++#ifdef ENABLE_SECOND_XHC ++static struct platform_driver second_xhci_mstar_driver = { ++ ++ .probe = xhci_mstar_plat_probe, ++ .remove = xhci_mstar_plat_remove, ++ ++ .driver = { ++ .name = "Sstar-xhci-2", ++ .pm = DEV_PM_OPS, ++#if defined(CONFIG_OF) ++ .of_match_table = mstar_xhci_1_of_device_ids, ++#endif ++ }, ++}; ++#endif ++ ++MODULE_ALIAS("platform:mstar-xhci-hcd"); ++ ++static const struct xhci_driver_overrides mstar_xhci_plat_overrides __initconst = { ++ .extra_priv_size = sizeof(struct xhci_hcd), ++}; ++ ++int xhci_register_plat(void) ++{ ++ int retval = 0; ++ ++ //xhci_init_driver(&mstar_plat_xhci_driver, &mstar_xhci_plat_overrides); ++ mstar_plat_xhci_driver.hcd_priv_size += mstar_xhci_plat_overrides.extra_priv_size; ++ ++ retval = platform_driver_register(&xhci_mstar_driver); ++ if (retval < 0) ++ return retval; ++ ++#ifdef ENABLE_SECOND_XHC ++ retval = platform_driver_register(&second_xhci_mstar_driver); ++#endif ++ ++ return retval; ++} ++ ++void xhci_unregister_plat(void) ++{ ++ platform_driver_unregister(&xhci_mstar_driver); ++#ifdef ENABLE_SECOND_XHC ++ platform_driver_unregister(&second_xhci_mstar_driver); ++#endif ++} +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 89a14d5f6ad8..e57a8f046c85 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -71,6 +71,18 @@ + #include "xhci-trace.h" + #include "xhci-mtk.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++extern void Chip_Flush_Memory(void); ++extern void Chip_Read_Memory(void); ++#endif ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++extern bool is_suspending(void); ++#endif /* CONFIG_MP_USB_STR_PATCH */ ++ + /* + * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA + * address of the TRB. +@@ -251,6 +263,10 @@ static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, + /* Ring the host controller doorbell after placing a command on the ring */ + void xhci_ring_cmd_db(struct xhci_hcd *xhci) + { ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ Chip_Flush_Memory(); ++#endif ++ + if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) + return; + +@@ -410,6 +426,10 @@ static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, + unsigned int stream_id; + struct xhci_virt_ep *ep; + ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ Chip_Flush_Memory(); ++#endif ++ + ep = &xhci->devs[slot_id]->eps[ep_index]; + + /* A ring has pending URBs if its TD list is not empty */ +@@ -918,7 +938,29 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg) + xhci = ep->xhci; + + spin_lock_irqsave(&xhci->lock, flags); ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ if (ep->stop_cmds_pending > 0 && (ep->ep_state & EP_HALT_PENDING)) ++ { ++ ep->stop_cmd_timer_count++; ++ printk("[XHCI] stop_cmd_timer_count %d ", ep->stop_cmd_timer_count); ++ if ( is_suspending() ) ++ { ++ //printk("... suspend end\n"); ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ return; ++ } + ++ if ( ep->stop_cmd_timer_count < XHCI_STOP_EP_CMD_TIMEOUT ) ++ { ++ //printk("...continue\n"); ++ ep->stop_cmd_timer.expires = jiffies + HZ; ++ add_timer(&ep->stop_cmd_timer); ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ return; ++ } ++ //printk("...end\n"); ++ } ++#endif /* CONFIG_MP_USB_STR_PATCH */ + ep->stop_cmds_pending--; + if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, +@@ -2562,12 +2604,28 @@ static int handle_tx_event(struct xhci_hcd *xhci, + trb_in_td(xhci, ep_ring->deq_seg, + ep_ring->dequeue, td->last_trb, + event_dma, true); ++#if (MP_USB_MSTAR==1) && defined(XHCI_TX_ERR_EVENT_PATCH) ++ if (trb_comp_code == COMP_TX_ERR) { ++ printk("Patch TRB ptr\n"); ++ event_dma = xhci_trb_virt_to_dma(ep_ring->deq_seg, ep_ring->dequeue); ++ event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, ++ td->last_trb, event_dma, false); ++ if (event_seg) ++ goto GO_TX_EVENT; ++ } ++#endif ++ + return -ESHUTDOWN; + } + + ret = skip_isoc_td(xhci, td, event, ep, &status); + goto cleanup; + } ++ ++#if (MP_USB_MSTAR==1) && defined(XHCI_TX_ERR_EVENT_PATCH) ++GO_TX_EVENT: ++#endif ++ + if (trb_comp_code == COMP_SHORT_TX) + ep_ring->last_td_was_short = true; + else +@@ -2745,7 +2803,15 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) + union xhci_trb *event_ring_deq; + dma_addr_t deq; + ++#if (MP_USB_MSTAR==1) ++ u32 handled_events; ++#endif ++ + spin_lock(&xhci->lock); ++ ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ Chip_Read_Memory(); //Flush Read buffer when H/W finished ++#endif + /* Check if the xHC generated the interrupt, or the irq is shared */ + status = readl(&xhci->op_regs->status); + if (status == 0xffffffff) +@@ -2797,10 +2863,27 @@ hw_died: + } + + event_ring_deq = xhci->event_ring->dequeue; ++#if (MP_USB_MSTAR==1) ++ //Force to update ERDP every 16 events. ++ //For some USB devices, like camera or wifi dongle. ++ //In some busy case, driver has no time to update ++ //the event ring dequeue pointer. It makes XHC to think ++ //the event ring is full. ++ handled_events = 1; ++ while (xhci_handle_event(xhci) > 0) ++ { ++ if (handled_events++ % 16 == 0) ++ { ++ xhci_set_hc_event_deq(xhci); ++ event_ring_deq = xhci->event_ring->dequeue; ++ } ++ } ++#else + /* FIXME this should be a delayed service routine + * that clears the EHB. + */ + while (xhci_handle_event(xhci) > 0) {} ++#endif + + temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); + /* If necessary, update the HW's version of the event ring deq ptr. */ +@@ -2988,9 +3071,13 @@ static int prepare_transfer(struct xhci_hcd *xhci, + static unsigned int count_trbs(u64 addr, u64 len) + { + unsigned int num_trbs; +- ++#if (MP_USB_MSTAR==1) //XHCI_CROSS64K_PATCH ++ num_trbs = DIV_ROUND_UP(len, ++ TRB_MAX_BUFF_SIZE); ++#else + num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), + TRB_MAX_BUFF_SIZE); ++#endif + if (num_trbs == 0) + num_trbs++; + +@@ -3056,6 +3143,12 @@ static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, + start_trb->field[3] |= cpu_to_le32(start_cycle); + else + start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); ++ ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ wmb(); ++ Chip_Flush_Memory(); ++#endif ++ + xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); + } + +@@ -3278,7 +3371,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, + field = TRB_TYPE(TRB_NORMAL); + + /* TRB buffer should not cross 64KB boundaries */ ++#if (MP_USB_MSTAR==1) //XHCI_CROSS64K_PATCH ++ trb_buff_len = TRB_MAX_BUFF_SIZE; ++#else + trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); ++#endif + trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); + + if (enqd_len + trb_buff_len > full_len) +@@ -3746,7 +3843,11 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, + field |= TRB_BEI; + } + /* Calculate TRB length */ ++#if (MP_USB_MSTAR==1) //XHCI_CROSS64K_PATCH ++ trb_buff_len = TRB_MAX_BUFF_SIZE; ++#else + trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); ++#endif + if (trb_buff_len > td_remain_len) + trb_buff_len = td_remain_len; + +@@ -3973,6 +4074,17 @@ int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, + | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); + } + ++#if (MP_USB_MSTAR==1) ++int xhci_queue_address_device_BSR(struct xhci_hcd *xhci, ++ struct xhci_command *cmd,dma_addr_t in_ctx_ptr, u32 slot_id) ++{ ++ return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), ++ upper_32_bits(in_ctx_ptr), 0, ++ TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) | (0x1 << 9), ++ false); ++} ++#endif ++ + int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, + u32 field1, u32 field2, u32 field3, u32 field4) + { +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index a7d239f5fc5f..6b07c250a56b 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -33,6 +33,14 @@ + #include "xhci-trace.h" + #include "xhci-mtk.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++extern void Chip_Flush_Memory(void); ++#endif ++ + #define DRIVER_AUTHOR "Sarah Sharp" + #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" + +@@ -186,6 +194,25 @@ int xhci_reset(struct xhci_hcd *xhci) + */ + if (xhci->quirks & XHCI_INTEL_HOST) + udelay(1000); ++#if (MP_USB_MSTAR==1) && defined(XHCI_HC_RESET_PATCH) ++ /* ++ * During xHCI reset period, the reading value of xHCI register could be zero. ++ * It isn't reliable to check the command & status register below. ++ * Add the checking of non-zero read-only register to wait for reset end. ++ * Added by Jonas. ++ */ ++ for (i = 0; i< 1000; i++) ++ { ++ if (0 == readl(&xhci->cap_regs->hcc_params)) ++ { ++ udelay(1000); ++ if (999==i) ++ printk("\n!! [xHCI ERROR] : hw reset doesn't end !! \n\n"); ++ } ++ else ++ break; ++ } ++#endif + + ret = xhci_handshake(&xhci->op_regs->command, + CMD_RESET, 0, 10 * 1000 * 1000); +@@ -554,6 +581,10 @@ int xhci_init(struct usb_hcd *hcd) + retval = xhci_mem_init(xhci, GFP_KERNEL); + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); + ++#if (MP_USB_MSTAR==1) && (XHCI_FLUSHPIPE_PATCH) ++ Chip_Flush_Memory(); ++#endif ++ + /* Initializing Compliance Mode Recovery Data If Needed */ + if (xhci_compliance_mode_recovery_timer_quirk_check()) { + xhci->quirks |= XHCI_COMP_MODE_QUIRK; +@@ -947,6 +978,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) + /* step 3: save registers */ + xhci_save_registers(xhci); + ++#if (MP_USB_MSTAR==0) + /* step 4: set CSS flag */ + command = readl(&xhci->op_regs->command); + command |= CMD_CSS; +@@ -957,6 +989,8 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) + spin_unlock_irq(&xhci->lock); + return -ETIMEDOUT; + } ++#endif ++ + spin_unlock_irq(&xhci->lock); + + /* +@@ -973,8 +1007,11 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) + + /* step 5: remove core well power */ + /* synchronize irq when using MSI-X */ ++#if (MP_USB_MSTAR==1) ++ synchronize_irq(hcd->irq); ++#else + xhci_msix_sync_irqs(xhci); +- ++#endif + return rc; + } + EXPORT_SYMBOL_GPL(xhci_suspend); +@@ -1050,6 +1087,27 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) + spin_unlock_irq(&xhci->lock); + xhci_cleanup_msix(xhci); + ++#if (MP_USB_MSTAR==1) ++ { ++ int ii, jj; ++ struct xhci_virt_device *virt_dev; ++ ++ for (ii = 1; ii < MAX_HC_SLOTS; ii++) ++ { ++ if ( !xhci->devs[ii] ) ++ continue; ++ ++ virt_dev = xhci->devs[ii]; ++ ++ for (jj = 0; jj < 31; ++jj) ++ { ++ virt_dev->eps[jj].ep_state &= ~EP_HALT_PENDING; ++ del_timer_sync(&virt_dev->eps[jj].stop_cmd_timer); ++ } ++ } ++ printk("[XHCI] stop all stop_cmd_timers...\n"); ++ } ++#endif + xhci_dbg(xhci, "// Disabling event ring interrupts\n"); + temp = readl(&xhci->op_regs->status); + writel(temp & ~STS_EINT, &xhci->op_regs->status); +@@ -1354,6 +1412,15 @@ int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) + goto exit; + } + ++#if (MP_USB_MSTAR==1) ++ if (!xhci->devs[slot_id]) ++ { ++ printk("[XHCI] virt dev is freed, stop to enqueue...\n"); ++ ret = -ENODEV; ++ goto exit; ++ } ++#endif ++ + if (usb_endpoint_xfer_isoc(&urb->ep->desc)) + size = urb->number_of_packets; + else if (usb_endpoint_is_bulk_out(&urb->ep->desc) && +@@ -1572,8 +1639,16 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + } + ep->ep_state |= EP_HALT_PENDING; + ep->stop_cmds_pending++; ++#if (MP_USB_MSTAR==1) ++ printk("[XHCI] issue stop cmd\n"); ++#endif ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ ep->stop_cmd_timer.expires = jiffies + HZ; ++ ep->stop_cmd_timer_count = 0; ++#else + ep->stop_cmd_timer.expires = jiffies + + XHCI_STOP_EP_CMD_TIMEOUT * HZ; ++#endif /* CONFIG_MP_USB_STR_PATCH */ + add_timer(&ep->stop_cmd_timer); + xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id, + ep_index, 0); +@@ -4917,6 +4992,10 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) + if (xhci->quirks & XHCI_NO_64BIT_SUPPORT) + xhci->hcc_params &= ~BIT(0); + ++#if (MP_USB_MSTAR==1) ++ printk(KERN_NOTICE "[USB][XHC] primary_hcd dma_mask 0x%llx\n", ++ *hcd->self.controller->dma_mask); ++#else + /* Set dma_mask and coherent_dma_mask to 64-bits, + * if xHC supports 64-bit addressing */ + if (HCC_64BIT_ADDR(xhci->hcc_params) && +@@ -4934,6 +5013,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) + xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n"); + dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + } ++#endif + + xhci_dbg(xhci, "Calling HCD init\n"); + /* Initialize HCD and host controller data structures. */ +@@ -5034,6 +5114,15 @@ MODULE_LICENSE("GPL"); + + static int __init xhci_hcd_init(void) + { ++#if (MP_USB_MSTAR==1) // temp xhci init ++ int retval; ++ ++ retval = xhci_register_plat(); ++ if (retval < 0) { ++ printk(KERN_DEBUG "Problem registering platform driver."); ++ return retval; ++ } ++#endif + /* + * Check the compiler generated sizes of structures that must be laid + * out in specific ways for hardware access. +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 836398ade58d..ebfae7e70b87 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -31,9 +31,18 @@ + #include + + /* Code sharing between pci-quirks and xhci hcd */ +-#include "xhci-ext-caps.h" ++#include "xhci-ext-caps.h" + #include "pci-quirks.h" + ++#ifndef MP_USB_MSTAR ++//#include ++#include "usb_patch_mstar.h" ++#endif ++ ++#if (MP_USB_MSTAR==1) ++#include "xhci-mstar.h" ++#endif ++ + /* xHCI PCI Configuration Registers */ + #define XHCI_SBRN_OFFSET (0x60) + +@@ -927,6 +936,9 @@ struct xhci_virt_ep { + /* Watchdog timer for stop endpoint command to cancel URBs */ + struct timer_list stop_cmd_timer; + int stop_cmds_pending; ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ unsigned int stop_cmd_timer_count; ++#endif /* CONFIG_MP_USB_STR_PATCH */ + struct xhci_hcd *xhci; + /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue + * command. We'll need to update the ring's dequeue segment and dequeue +@@ -1369,7 +1381,11 @@ struct xhci_td { + }; + + /* xHCI command default timeout value */ ++#if (MP_USB_MSTAR==1) ++#define XHCI_CMD_DEFAULT_TIMEOUT (10 * HZ) ++#else + #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) ++#endif + + /* command descriptor */ + struct xhci_cd { +@@ -1849,6 +1865,13 @@ void xhci_urb_free_priv(struct urb_priv *urb_priv); + void xhci_free_command(struct xhci_hcd *xhci, + struct xhci_command *command); + ++#if (MP_USB_MSTAR==1) \ ++ || defined(CONFIG_USB_XHCI_PLATFORM) \ ++ || defined(CONFIG_USB_XHCI_PLATFORM_MODULE) ++int xhci_register_plat(void); ++void xhci_unregister_plat(void); ++#endif ++ + /* xHCI host controller glue */ + typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); + int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); +@@ -1913,6 +1936,11 @@ int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, + u32 trb_type, u32 slot_id); + int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, + dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); ++#if (MP_USB_MSTAR==1) ++int xhci_queue_address_device_BSR(struct xhci_hcd *xhci, ++ struct xhci_command *cmd,dma_addr_t in_ctx_ptr, u32 slot_id); ++void xhci_set_hc_event_deq(struct xhci_hcd *xhci); ++#endif + int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, + u32 field1, u32 field2, u32 field3, u32 field4); + int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, +diff --git a/drivers/usb/misc/yurex.c b/drivers/usb/misc/yurex.c +index 54e53ac4c08f..f36968ee2e70 100644 +--- a/drivers/usb/misc/yurex.c ++++ b/drivers/usb/misc/yurex.c +@@ -406,8 +406,7 @@ static ssize_t yurex_read(struct file *file, char __user *buffer, size_t count, + loff_t *ppos) + { + struct usb_yurex *dev; +- int retval = 0; +- int bytes_read = 0; ++ int len = 0; + char in_buffer[20]; + unsigned long flags; + +@@ -415,26 +414,16 @@ static ssize_t yurex_read(struct file *file, char __user *buffer, size_t count, + + mutex_lock(&dev->io_mutex); + if (!dev->interface) { /* already disconnected */ +- retval = -ENODEV; +- goto exit; ++ mutex_unlock(&dev->io_mutex); ++ return -ENODEV; + } + + spin_lock_irqsave(&dev->lock, flags); +- bytes_read = snprintf(in_buffer, 20, "%lld\n", dev->bbu); ++ len = snprintf(in_buffer, 20, "%lld\n", dev->bbu); + spin_unlock_irqrestore(&dev->lock, flags); +- +- if (*ppos < bytes_read) { +- if (copy_to_user(buffer, in_buffer + *ppos, bytes_read - *ppos)) +- retval = -EFAULT; +- else { +- retval = bytes_read - *ppos; +- *ppos += bytes_read; +- } +- } +- +-exit: + mutex_unlock(&dev->io_mutex); +- return retval; ++ ++ return simple_read_from_buffer(buffer, count, ppos, in_buffer, len); + } + + static ssize_t yurex_write(struct file *file, const char __user *user_buffer, +diff --git a/drivers/usb/storage/Makefile b/drivers/usb/storage/Makefile +index 4cd55481b309..feb20c072435 100644 +--- a/drivers/usb/storage/Makefile ++++ b/drivers/usb/storage/Makefile +@@ -4,6 +4,7 @@ + # 15 Aug 2000, Christoph Hellwig + # Rewritten to use lists instead of if-statements. + # ++EXTRA_CFLAGS += -Idrivers/sstar/usb/host/$(CONFIG_SSTAR_CHIP_NAME) + + ccflags-y := -Idrivers/scsi + +diff --git a/drivers/usb/storage/scsiglue.c b/drivers/usb/storage/scsiglue.c +index 8cd2926fb1fe..14abee65e03f 100644 +--- a/drivers/usb/storage/scsiglue.c ++++ b/drivers/usb/storage/scsiglue.c +@@ -59,6 +59,9 @@ + #include "transport.h" + #include "protocol.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif + /* + * Vendor IDs for companies that seem to include the READ CAPACITY bug + * in all their devices +@@ -413,6 +416,12 @@ static int command_abort(struct scsi_cmnd *srb) + + usb_stor_dbg(us, "%s called\n", __func__); + ++#if (MP_USB_MSTAR==1) ++ if (srb->cmnd[0] == TEST_UNIT_READY) ++ { ++ msleep(1000); ++ } ++#endif + /* + * us->srb together with the TIMED_OUT, RESETTING, and ABORTING + * bits are protected by the host lock. +diff --git a/drivers/usb/storage/transport.c b/drivers/usb/storage/transport.c +index a3ccb899df60..97c7f71dc59f 100644 +--- a/drivers/usb/storage/transport.c ++++ b/drivers/usb/storage/transport.c +@@ -64,6 +64,9 @@ + #include + #include "../../scsi/sd.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif + + /*********************************************************************** + * Data transfer routines +@@ -179,8 +182,41 @@ static int usb_stor_msg_common(struct us_data *us, int timeout) + } + + /* wait for the completion of the URB */ ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ { ++ #define TIMEOUT_SETP_MS 100 ++ unsigned long timeout_step = msecs_to_jiffies(TIMEOUT_SETP_MS); ++ unsigned long expire; ++ unsigned long total_time = 0; ++ expire = timeout ? timeout : MAX_SCHEDULE_TIMEOUT; ++ while (1) ++ { ++ timeleft = wait_for_completion_interruptible_timeout(&urb_done, timeout_step); ++ if (timeleft <= 0) ++ { ++ total_time += timeout_step; ++ if(is_suspending()) ++ { ++ set_bit(US_FLIDX_DISCONNECTING, &us->dflags); ++ break; ++ } ++ if(us->pusb_dev->state == USB_STATE_NOTATTACHED) ++ { ++ printk(KERN_EMERG "[USB] stor wait_ctrl_msg fail: disconnect timeleft->[%ld]\n", timeleft); ++ set_bit(US_FLIDX_DISCONNECTING, &us->dflags); ++ break; ++ } ++ if ( (timeleft < 0) || (total_time >= expire) ) ++ break; ++ } ++ else ++ break; ++ } ++ } ++#else + timeleft = wait_for_completion_interruptible_timeout( + &urb_done, timeout ? : MAX_SCHEDULE_TIMEOUT); ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ + + clear_bit(US_FLIDX_URB_ACTIVE, &us->dflags); + +@@ -628,6 +664,10 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us) + if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags)) { + usb_stor_dbg(us, "-- command was aborted\n"); + srb->result = DID_ABORT << 16; ++#if (MP_USB_MSTAR==1) ++ if (srb->cmnd[0] == INQUIRY) //for HD+bad cable, Colin, 090216 ++ printk("[USB] First Inquiry command timeout!!!\n"); ++#endif + goto Handle_Errors; + } + +@@ -1355,6 +1395,9 @@ static int usb_stor_reset_common(struct us_data *us, + { + int result; + int result2; ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ int i; ++#endif /* CONFIG_MP_USB_STR_PATCH */ + + if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags)) { + usb_stor_dbg(us, "No reset during disconnect\n"); +@@ -1373,9 +1416,25 @@ static int usb_stor_reset_common(struct us_data *us, + * Give the device some time to recover from the reset, + * but don't delay disconnect processing. + */ ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++ for(i=1;i<=60;i++) ++ { ++ long timeleft = wait_event_interruptible_timeout(us->delay_wait, ++ test_bit(US_FLIDX_DISCONNECTING, &us->dflags), ++ 0.1*HZ); ++ if(timeleft==0) ++ { ++ if(is_suspending()) ++ return -ETIMEDOUT; ++ } ++ else ++ break; ++ } ++#else + wait_event_interruptible_timeout(us->delay_wait, + test_bit(US_FLIDX_DISCONNECTING, &us->dflags), + HZ*6); ++#endif /* CONFIG_MP_USB_STR_PATCH */ + if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags)) { + usb_stor_dbg(us, "Reset interrupted by disconnect\n"); + return -EIO; +diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h +index b605115eb47a..7edbf94fd969 100644 +--- a/drivers/usb/storage/unusual_devs.h ++++ b/drivers/usb/storage/unusual_devs.h +@@ -66,6 +66,10 @@ + * maintained at http://www.draisberghof.de/usb_modeswitch/ + */ + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ + #if !defined(CONFIG_USB_STORAGE_SDDR09) && \ + !defined(CONFIG_USB_STORAGE_SDDR09_MODULE) + #define NO_SDDR09 +@@ -663,6 +667,14 @@ UNUSUAL_DEV( 0x054c, 0x0010, 0x0106, 0x0450, + USB_SC_SCSI, USB_PR_DEVICE, NULL, + US_FL_SINGLE_LUN | US_FL_NOT_LOCKABLE | US_FL_NO_WP_DETECT ), + ++#if defined(CONfIG_MP_USB_MSTAR) ++UNUSUAL_DEV( 0x14cd, 0x6116, 0x0000, 0x9999, ++ "SAMSUNG ", ++ "HM250HI ", ++ USB_SC_SCSI, USB_PR_BULK, NULL, ++ US_FL_NO_WP_DETECT), ++#endif /* CONfIG_MP_USB_MSTAR */ ++ + /* + * Submitted by Lars Jacob + * This entry is needed because the device reports Sub=ff +@@ -2356,6 +2368,27 @@ UNUSUAL_DEV( 0xed10, 0x7636, 0x0001, 0x0001, + "Digital MP3 Audio Player", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_NOT_LOCKABLE ), + ++#if (MP_USB_MSTAR==1) ++/*Colin, 090317, for Transcend 16GB JF V85, wrong residual*/ ++UNUSUAL_DEV( 0x058F, 0x6387, 0x0000, 0x9999, ++ "JetFlash", ++ "Mass Storage Device", ++ USB_SC_SCSI, USB_PR_BULK, NULL, ++ US_FL_IGNORE_RESIDUE ), ++ ++UNUSUAL_DEV( 0x0dd8, 0x1414, 0x0100, 0x0100, ++ "Netac", ++ "USB Flash Disk", ++ USB_SC_SCSI, USB_PR_BULK, NULL, ++ US_FL_MAX_SECTORS_64 ), ++ ++UNUSUAL_DEV( 0x05e3, 0x0731, 0x0000, 0x9999, ++ "EAGET", ++ "H500", ++ USB_SC_SCSI, USB_PR_BULK, NULL, ++ US_FL_FIX_INQUIRY), ++#endif ++ + /* Unusual uas devices */ + #if IS_ENABLED(CONFIG_USB_UAS) + #include "unusual_uas.h" +diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c +index 2cba13a532cd..6ddd402dec8f 100644 +--- a/drivers/usb/storage/usb.c ++++ b/drivers/usb/storage/usb.c +@@ -73,6 +73,10 @@ + #include "sierra_ms.h" + #include "option_ms.h" + ++#ifndef MP_USB_MSTAR ++#include ++#endif ++ + #if IS_ENABLED(CONFIG_USB_UAS) + #include "uas-detect.h" + #endif +@@ -1175,7 +1179,11 @@ static struct usb_driver usb_storage_driver = { + .post_reset = usb_stor_post_reset, + .id_table = usb_storage_usb_ids, + .supports_autosuspend = 1, ++#if (MP_USB_MSTAR==1) ++ .soft_unbind = 0, ++#else + .soft_unbind = 1, ++#endif + }; + + module_usb_stor_driver(usb_storage_driver, usb_stor_host_template, DRV_NAME); +diff --git a/drivers/usb/storage/usb.h b/drivers/usb/storage/usb.h +index 8fae28b40bb4..6dcfdc7270b0 100644 +--- a/drivers/usb/storage/usb.h ++++ b/drivers/usb/storage/usb.h +@@ -205,6 +205,9 @@ extern int usb_stor_probe1(struct us_data **pus, + struct scsi_host_template *sht); + extern int usb_stor_probe2(struct us_data *us); + extern void usb_stor_disconnect(struct usb_interface *intf); ++#if defined(CONFIG_SUSPEND) && defined(CONFIG_MP_USB_STR_PATCH) ++extern bool is_suspending(void); ++#endif /* CONFIG_SUSPEND && CONFIG_MP_USB_STR_PATCH */ + + extern void usb_stor_adjust_quirks(struct usb_device *dev, + unsigned long *fflags); +diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c +index cd38f5add254..e63b53a16ffb 100644 +--- a/drivers/vhost/vhost.c ++++ b/drivers/vhost/vhost.c +@@ -1889,7 +1889,7 @@ static int get_indirect(struct vhost_virtqueue *vq, + /* If this is an input descriptor, increment that count. */ + if (access == VHOST_ACCESS_WO) { + *in_num += ret; +- if (unlikely(log)) { ++ if (unlikely(log && ret)) { + log[*log_num].addr = vhost64_to_cpu(vq, desc.addr); + log[*log_num].len = vhost32_to_cpu(vq, desc.len); + ++*log_num; +@@ -2025,7 +2025,7 @@ int vhost_get_vq_desc(struct vhost_virtqueue *vq, + /* If this is an input descriptor, + * increment that count. */ + *in_num += ret; +- if (unlikely(log)) { ++ if (unlikely(log && ret)) { + log[*log_num].addr = vhost64_to_cpu(vq, desc.addr); + log[*log_num].len = vhost32_to_cpu(vq, desc.len); + ++*log_num; +diff --git a/drivers/video/fbdev/uvesafb.c b/drivers/video/fbdev/uvesafb.c +index 98af9e02959b..9fe0d0bcdf62 100644 +--- a/drivers/video/fbdev/uvesafb.c ++++ b/drivers/video/fbdev/uvesafb.c +@@ -1059,7 +1059,8 @@ static int uvesafb_setcmap(struct fb_cmap *cmap, struct fb_info *info) + info->cmap.len || cmap->start < info->cmap.start) + return -EINVAL; + +- entries = kmalloc(sizeof(*entries) * cmap->len, GFP_KERNEL); ++ entries = kmalloc_array(cmap->len, sizeof(*entries), ++ GFP_KERNEL); + if (!entries) + return -ENOMEM; + +diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c +old mode 100644 +new mode 100755 +index 32930a073a12..a8c9d7cdef9b +--- a/drivers/watchdog/watchdog_dev.c ++++ b/drivers/watchdog/watchdog_dev.c +@@ -842,9 +842,9 @@ static int watchdog_release(struct inode *inode, struct file *file) + */ + if (!test_bit(WDOG_ACTIVE, &wdd->status)) + err = 0; +- else if (test_and_clear_bit(_WDOG_ALLOW_RELEASE, &wd_data->status) || +- !(wdd->info->options & WDIOF_MAGICCLOSE)) +- err = watchdog_stop(wdd); ++ //else if (test_and_clear_bit(_WDOG_ALLOW_RELEASE, &wd_data->status) || ++ // !(wdd->info->options & WDIOF_MAGICCLOSE)) ++ // err = watchdog_stop(wdd); + + /* If the watchdog was not stopped, send a keepalive ping */ + if (err < 0) { +diff --git a/fs/block_dev.c b/fs/block_dev.c +index cb936c90ae82..cb61a49e18ae 100644 +--- a/fs/block_dev.c ++++ b/fs/block_dev.c +@@ -1250,10 +1250,8 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) + */ + if (!for_part) { + ret = devcgroup_inode_permission(bdev->bd_inode, perm); +- if (ret != 0) { +- bdput(bdev); ++ if (ret != 0) + return ret; +- } + } + + restart: +@@ -1323,8 +1321,10 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) + goto out_clear; + BUG_ON(for_part); + ret = __blkdev_get(whole, mode, 1); +- if (ret) ++ if (ret) { ++ bdput(whole); + goto out_clear; ++ } + bdev->bd_contains = whole; + bdev->bd_part = disk_get_part(disk, partno); + if (!(disk->flags & GENHD_FL_UP) || +@@ -1374,7 +1374,6 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) + put_disk(disk); + module_put(owner); + out: +- bdput(bdev); + + return ret; + } +@@ -1460,6 +1459,9 @@ int blkdev_get(struct block_device *bdev, fmode_t mode, void *holder) + bdput(whole); + } + ++ if (res) ++ bdput(bdev); ++ + return res; + } + EXPORT_SYMBOL(blkdev_get); +diff --git a/fs/char_dev.c b/fs/char_dev.c +index 44a240c4bb65..fb8507f521b2 100644 +--- a/fs/char_dev.c ++++ b/fs/char_dev.c +@@ -471,6 +471,85 @@ int cdev_add(struct cdev *p, dev_t dev, unsigned count) + return 0; + } + ++/** ++ * cdev_set_parent() - set the parent kobject for a char device ++ * @p: the cdev structure ++ * @kobj: the kobject to take a reference to ++ * ++ * cdev_set_parent() sets a parent kobject which will be referenced ++ * appropriately so the parent is not freed before the cdev. This ++ * should be called before cdev_add. ++ */ ++void cdev_set_parent(struct cdev *p, struct kobject *kobj) ++{ ++ WARN_ON(!kobj->state_initialized); ++ p->kobj.parent = kobj; ++} ++ ++/** ++ * cdev_device_add() - add a char device and it's corresponding ++ * struct device, linkink ++ * @dev: the device structure ++ * @cdev: the cdev structure ++ * ++ * cdev_device_add() adds the char device represented by @cdev to the system, ++ * just as cdev_add does. It then adds @dev to the system using device_add ++ * The dev_t for the char device will be taken from the struct device which ++ * needs to be initialized first. This helper function correctly takes a ++ * reference to the parent device so the parent will not get released until ++ * all references to the cdev are released. ++ * ++ * This helper uses dev->devt for the device number. If it is not set ++ * it will not add the cdev and it will be equivalent to device_add. ++ * ++ * This function should be used whenever the struct cdev and the ++ * struct device are members of the same structure whose lifetime is ++ * managed by the struct device. ++ * ++ * NOTE: Callers must assume that userspace was able to open the cdev and ++ * can call cdev fops callbacks at any time, even if this function fails. ++ */ ++int cdev_device_add(struct cdev *cdev, struct device *dev) ++{ ++ int rc = 0; ++ ++ if (dev->devt) { ++ cdev_set_parent(cdev, &dev->kobj); ++ ++ rc = cdev_add(cdev, dev->devt, 1); ++ if (rc) ++ return rc; ++ } ++ ++ rc = device_add(dev); ++ if (rc) ++ cdev_del(cdev); ++ ++ return rc; ++} ++ ++/** ++ * cdev_device_del() - inverse of cdev_device_add ++ * @dev: the device structure ++ * @cdev: the cdev structure ++ * ++ * cdev_device_del() is a helper function to call cdev_del and device_del. ++ * It should be used whenever cdev_device_add is used. ++ * ++ * If dev->devt is not set it will not remove the cdev and will be equivalent ++ * to device_del. ++ * ++ * NOTE: This guarantees that associated sysfs callbacks are not running ++ * or runnable, however any cdevs already open will remain and their fops ++ * will still be callable even after this function returns. ++ */ ++void cdev_device_del(struct cdev *cdev, struct device *dev) ++{ ++ device_del(dev); ++ if (dev->devt) ++ cdev_del(cdev); ++} ++ + static void cdev_unmap(dev_t dev, unsigned count) + { + kobj_unmap(cdev_map, dev, count); +@@ -482,6 +561,10 @@ static void cdev_unmap(dev_t dev, unsigned count) + * + * cdev_del() removes @p from the system, possibly freeing the structure + * itself. ++ * ++ * NOTE: This guarantees that cdev device will no longer be able to be ++ * opened, however any cdevs already open will remain and their fops will ++ * still be callable even after cdev_del returns. + */ + void cdev_del(struct cdev *p) + { +@@ -570,5 +653,8 @@ EXPORT_SYMBOL(cdev_init); + EXPORT_SYMBOL(cdev_alloc); + EXPORT_SYMBOL(cdev_del); + EXPORT_SYMBOL(cdev_add); ++EXPORT_SYMBOL(cdev_set_parent); ++EXPORT_SYMBOL(cdev_device_add); ++EXPORT_SYMBOL(cdev_device_del); + EXPORT_SYMBOL(__register_chrdev); + EXPORT_SYMBOL(__unregister_chrdev); +diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c +index 538d9b55699a..c3db2a882aee 100644 +--- a/fs/cifs/sess.c ++++ b/fs/cifs/sess.c +@@ -344,13 +344,12 @@ void build_ntlmssp_negotiate_blob(unsigned char *pbuffer, + /* BB is NTLMV2 session security format easier to use here? */ + flags = NTLMSSP_NEGOTIATE_56 | NTLMSSP_REQUEST_TARGET | + NTLMSSP_NEGOTIATE_128 | NTLMSSP_NEGOTIATE_UNICODE | +- NTLMSSP_NEGOTIATE_NTLM | NTLMSSP_NEGOTIATE_EXTENDED_SEC; +- if (ses->server->sign) { ++ NTLMSSP_NEGOTIATE_NTLM | NTLMSSP_NEGOTIATE_EXTENDED_SEC | ++ NTLMSSP_NEGOTIATE_SEAL; ++ if (ses->server->sign) + flags |= NTLMSSP_NEGOTIATE_SIGN; +- if (!ses->server->session_estab || +- ses->ntlmssp->sesskey_per_smbsess) +- flags |= NTLMSSP_NEGOTIATE_KEY_XCH; +- } ++ if (!ses->server->session_estab || ses->ntlmssp->sesskey_per_smbsess) ++ flags |= NTLMSSP_NEGOTIATE_KEY_XCH; + + sec_blob->NegotiateFlags = cpu_to_le32(flags); + +@@ -407,13 +406,12 @@ int build_ntlmssp_auth_blob(unsigned char **pbuffer, + flags = NTLMSSP_NEGOTIATE_56 | + NTLMSSP_REQUEST_TARGET | NTLMSSP_NEGOTIATE_TARGET_INFO | + NTLMSSP_NEGOTIATE_128 | NTLMSSP_NEGOTIATE_UNICODE | +- NTLMSSP_NEGOTIATE_NTLM | NTLMSSP_NEGOTIATE_EXTENDED_SEC; +- if (ses->server->sign) { ++ NTLMSSP_NEGOTIATE_NTLM | NTLMSSP_NEGOTIATE_EXTENDED_SEC | ++ NTLMSSP_NEGOTIATE_SEAL; ++ if (ses->server->sign) + flags |= NTLMSSP_NEGOTIATE_SIGN; +- if (!ses->server->session_estab || +- ses->ntlmssp->sesskey_per_smbsess) +- flags |= NTLMSSP_NEGOTIATE_KEY_XCH; +- } ++ if (!ses->server->session_estab || ses->ntlmssp->sesskey_per_smbsess) ++ flags |= NTLMSSP_NEGOTIATE_KEY_XCH; + + tmp = *pbuffer + sizeof(AUTHENTICATE_MESSAGE); + sec_blob->NegotiateFlags = cpu_to_le32(flags); +diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c +index 94c4c1901222..92196e06bf52 100644 +--- a/fs/cifs/smb2pdu.c ++++ b/fs/cifs/smb2pdu.c +@@ -707,15 +707,13 @@ SMB2_sess_establish_session(struct SMB2_sess_data *sess_data) + struct cifs_ses *ses = sess_data->ses; + + mutex_lock(&ses->server->srv_mutex); +- if (ses->server->sign && ses->server->ops->generate_signingkey) { ++ if (ses->server->ops->generate_signingkey) { + rc = ses->server->ops->generate_signingkey(ses); +- kfree(ses->auth_key.response); +- ses->auth_key.response = NULL; + if (rc) { + cifs_dbg(FYI, + "SMB3 session key generation failed\n"); + mutex_unlock(&ses->server->srv_mutex); +- goto keygen_exit; ++ return rc; + } + } + if (!ses->server->session_estab) { +@@ -729,12 +727,6 @@ SMB2_sess_establish_session(struct SMB2_sess_data *sess_data) + ses->status = CifsGood; + ses->need_reconnect = false; + spin_unlock(&GlobalMid_Lock); +- +-keygen_exit: +- if (!ses->server->sign) { +- kfree(ses->auth_key.response); +- ses->auth_key.response = NULL; +- } + return rc; + } + +diff --git a/fs/exec.c b/fs/exec.c +index b8c43be24751..556b8405a393 100644 +--- a/fs/exec.c ++++ b/fs/exec.c +@@ -938,7 +938,7 @@ int kernel_read_file(struct file *file, void **buf, loff_t *size, + i_size - pos); + if (bytes < 0) { + ret = bytes; +- goto out; ++ goto out_free; + } + + if (bytes == 0) +@@ -1791,7 +1791,7 @@ static int do_execveat_common(int fd, struct filename *filename, + current->fs->in_exec = 0; + current->in_execve = 0; + acct_update_integrals(current); +- task_numa_free(current); ++ task_numa_free(current, false); + free_bprm(bprm); + kfree(pathbuf); + putname(filename); +diff --git a/fs/ext4/balloc.c b/fs/ext4/balloc.c +index e04ec868e37e..a61bd2f7cf43 100644 +--- a/fs/ext4/balloc.c ++++ b/fs/ext4/balloc.c +@@ -339,20 +339,25 @@ static ext4_fsblk_t ext4_valid_block_bitmap(struct super_block *sb, + /* check whether block bitmap block number is set */ + blk = ext4_block_bitmap(sb, desc); + offset = blk - group_first_block; +- if (!ext4_test_bit(EXT4_B2C(sbi, offset), bh->b_data)) ++ if (offset < 0 || EXT4_B2C(sbi, offset) >= sb->s_blocksize || ++ !ext4_test_bit(EXT4_B2C(sbi, offset), bh->b_data)) + /* bad block bitmap */ + return blk; + + /* check whether the inode bitmap block number is set */ + blk = ext4_inode_bitmap(sb, desc); + offset = blk - group_first_block; +- if (!ext4_test_bit(EXT4_B2C(sbi, offset), bh->b_data)) ++ if (offset < 0 || EXT4_B2C(sbi, offset) >= sb->s_blocksize || ++ !ext4_test_bit(EXT4_B2C(sbi, offset), bh->b_data)) + /* bad block bitmap */ + return blk; + + /* check whether the inode table block number is set */ + blk = ext4_inode_table(sb, desc); + offset = blk - group_first_block; ++ if (offset < 0 || EXT4_B2C(sbi, offset) >= sb->s_blocksize || ++ EXT4_B2C(sbi, offset + sbi->s_itb_per_group) >= sb->s_blocksize) ++ return blk; + next_zero_bit = ext4_find_next_zero_bit(bh->b_data, + EXT4_B2C(sbi, offset + EXT4_SB(sb)->s_itb_per_group), + EXT4_B2C(sbi, offset)); +@@ -418,6 +423,7 @@ struct buffer_head * + ext4_read_block_bitmap_nowait(struct super_block *sb, ext4_group_t block_group) + { + struct ext4_group_desc *desc; ++ struct ext4_sb_info *sbi = EXT4_SB(sb); + struct buffer_head *bh; + ext4_fsblk_t bitmap_blk; + int err; +@@ -426,6 +432,12 @@ ext4_read_block_bitmap_nowait(struct super_block *sb, ext4_group_t block_group) + if (!desc) + return ERR_PTR(-EFSCORRUPTED); + bitmap_blk = ext4_block_bitmap(sb, desc); ++ if ((bitmap_blk <= le32_to_cpu(sbi->s_es->s_first_data_block)) || ++ (bitmap_blk >= ext4_blocks_count(sbi->s_es))) { ++ ext4_error(sb, "Invalid block bitmap block %llu in " ++ "block_group %u", bitmap_blk, block_group); ++ return ERR_PTR(-EFSCORRUPTED); ++ } + bh = sb_getblk(sb, bitmap_blk); + if (unlikely(!bh)) { + ext4_error(sb, "Cannot get buffer for block bitmap - " +diff --git a/fs/ext4/ialloc.c b/fs/ext4/ialloc.c +index 2d94e8524839..d5fccce083c3 100644 +--- a/fs/ext4/ialloc.c ++++ b/fs/ext4/ialloc.c +@@ -157,6 +157,7 @@ static struct buffer_head * + ext4_read_inode_bitmap(struct super_block *sb, ext4_group_t block_group) + { + struct ext4_group_desc *desc; ++ struct ext4_sb_info *sbi = EXT4_SB(sb); + struct buffer_head *bh = NULL; + ext4_fsblk_t bitmap_blk; + int err; +@@ -166,6 +167,12 @@ ext4_read_inode_bitmap(struct super_block *sb, ext4_group_t block_group) + return ERR_PTR(-EFSCORRUPTED); + + bitmap_blk = ext4_inode_bitmap(sb, desc); ++ if ((bitmap_blk <= le32_to_cpu(sbi->s_es->s_first_data_block)) || ++ (bitmap_blk >= ext4_blocks_count(sbi->s_es))) { ++ ext4_error(sb, "Invalid inode bitmap blk %llu in " ++ "block_group %u", bitmap_blk, block_group); ++ return ERR_PTR(-EFSCORRUPTED); ++ } + bh = sb_getblk(sb, bitmap_blk); + if (unlikely(!bh)) { + ext4_error(sb, "Cannot read inode bitmap - " +diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c +index 5cccec68a0a5..398d2d459cc0 100644 +--- a/fs/ext4/inode.c ++++ b/fs/ext4/inode.c +@@ -4494,6 +4494,12 @@ struct inode *ext4_iget(struct super_block *sb, unsigned long ino) + goto bad_inode; + raw_inode = ext4_raw_inode(&iloc); + ++ if ((ino == EXT4_ROOT_INO) && (raw_inode->i_links_count == 0)) { ++ EXT4_ERROR_INODE(inode, "root inode unallocated"); ++ ret = -EFSCORRUPTED; ++ goto bad_inode; ++ } ++ + if (EXT4_INODE_SIZE(inode->i_sb) > EXT4_GOOD_OLD_INODE_SIZE) { + ei->i_extra_isize = le16_to_cpu(raw_inode->i_extra_isize); + if (EXT4_GOOD_OLD_INODE_SIZE + ei->i_extra_isize > +diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c +index 3eeed8f0aa06..da127c8af2f5 100644 +--- a/fs/ext4/xattr.c ++++ b/fs/ext4/xattr.c +@@ -1425,6 +1425,11 @@ static int ext4_xattr_make_inode_space(handle_t *handle, struct inode *inode, + last = IFIRST(header); + /* Find the entry best suited to be pushed into EA block */ + for (; !IS_LAST_ENTRY(last); last = EXT4_XATTR_NEXT(last)) { ++ /* never move system.data out of the inode */ ++ if ((last->e_name_len == 4) && ++ (last->e_name_index == EXT4_XATTR_INDEX_SYSTEM) && ++ !memcmp(last->e_name, "data", 4)) ++ continue; + total_size = + EXT4_XATTR_SIZE(le32_to_cpu(last->e_value_size)) + + EXT4_XATTR_LEN(last->e_name_len); +diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c +index f11792672977..46468ea63eed 100644 +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -1946,10 +1946,8 @@ static ssize_t fuse_dev_splice_write(struct pipe_inode_info *pipe, + rem += pipe->bufs[(pipe->curbuf + idx) & (pipe->buffers - 1)].len; + + ret = -EINVAL; +- if (rem < len) { +- pipe_unlock(pipe); +- goto out; +- } ++ if (rem < len) ++ goto out_free; + + rem = len; + while (rem) { +@@ -1967,7 +1965,9 @@ static ssize_t fuse_dev_splice_write(struct pipe_inode_info *pipe, + pipe->curbuf = (pipe->curbuf + 1) & (pipe->buffers - 1); + pipe->nrbufs--; + } else { +- pipe_buf_get(pipe, ibuf); ++ if (!pipe_buf_get(pipe, ibuf)) ++ goto out_free; ++ + *obuf = *ibuf; + obuf->flags &= ~PIPE_BUF_FLAG_GIFT; + obuf->len = rem; +@@ -1989,10 +1989,12 @@ static ssize_t fuse_dev_splice_write(struct pipe_inode_info *pipe, + + ret = fuse_dev_do_write(fud, &cs, len); + ++ pipe_lock(pipe); ++out_free: + for (idx = 0; idx < nbuf; idx++) + pipe_buf_release(pipe, &bufs[idx]); ++ pipe_unlock(pipe); + +-out: + kfree(bufs); + return ret; + } +diff --git a/fs/hfsplus/dir.c b/fs/hfsplus/dir.c +index 31d5e3f1fe17..193d5411210a 100644 +--- a/fs/hfsplus/dir.c ++++ b/fs/hfsplus/dir.c +@@ -77,13 +77,13 @@ again: + cpu_to_be32(HFSP_HARDLINK_TYPE) && + entry.file.user_info.fdCreator == + cpu_to_be32(HFSP_HFSPLUS_CREATOR) && ++ HFSPLUS_SB(sb)->hidden_dir && + (entry.file.create_date == + HFSPLUS_I(HFSPLUS_SB(sb)->hidden_dir)-> + create_date || + entry.file.create_date == + HFSPLUS_I(d_inode(sb->s_root))-> +- create_date) && +- HFSPLUS_SB(sb)->hidden_dir) { ++ create_date)) { + struct qstr str; + char name[32]; + +diff --git a/fs/inode.c b/fs/inode.c +index 920aa0b1c6b0..a73ae4d93bb1 100644 +--- a/fs/inode.c ++++ b/fs/inode.c +@@ -392,6 +392,13 @@ void __iget(struct inode *inode) + atomic_inc(&inode->i_count); + } + ++void __iget_wrap(struct inode * inode) ++{ ++ __iget(inode); ++} ++EXPORT_SYMBOL(__iget_wrap); ++ ++ + /* + * get additional reference to inode; caller must already hold one. + */ +diff --git a/fs/ncpfs/ncplib_kernel.c b/fs/ncpfs/ncplib_kernel.c +index 88dbbc9fcf4d..f571570a2e72 100644 +--- a/fs/ncpfs/ncplib_kernel.c ++++ b/fs/ncpfs/ncplib_kernel.c +@@ -980,6 +980,10 @@ ncp_read_kernel(struct ncp_server *server, const char *file_id, + goto out; + } + *bytes_read = ncp_reply_be16(server, 0); ++ if (*bytes_read > to_read) { ++ result = -EINVAL; ++ goto out; ++ } + source = ncp_reply_data(server, 2 + (offset & 1)); + + memcpy(target, source, *bytes_read); +diff --git a/fs/pipe.c b/fs/pipe.c +index 34345535f63d..92dfd6321634 100644 +--- a/fs/pipe.c ++++ b/fs/pipe.c +@@ -193,9 +193,9 @@ EXPORT_SYMBOL(generic_pipe_buf_steal); + * in the tee() system call, when we duplicate the buffers in one + * pipe into another. + */ +-void generic_pipe_buf_get(struct pipe_inode_info *pipe, struct pipe_buffer *buf) ++bool generic_pipe_buf_get(struct pipe_inode_info *pipe, struct pipe_buffer *buf) + { +- get_page(buf->page); ++ return try_get_page(buf->page); + } + EXPORT_SYMBOL(generic_pipe_buf_get); + +diff --git a/fs/proc/base.c b/fs/proc/base.c +index e67fec3c9856..3fec83ba75fa 100644 +--- a/fs/proc/base.c ++++ b/fs/proc/base.c +@@ -252,7 +252,7 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, + * Inherently racy -- command line shares address space + * with code and data. + */ +- rv = access_remote_vm(mm, arg_end - 1, &c, 1, 0); ++ rv = access_remote_vm(mm, arg_end - 1, &c, 1, FOLL_ANON); + if (rv <= 0) + goto out_free_page; + +@@ -270,7 +270,7 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, + int nr_read; + + _count = min3(count, len, PAGE_SIZE); +- nr_read = access_remote_vm(mm, p, page, _count, 0); ++ nr_read = access_remote_vm(mm, p, page, _count, FOLL_ANON); + if (nr_read < 0) + rv = nr_read; + if (nr_read <= 0) +@@ -305,7 +305,7 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, + bool final; + + _count = min3(count, len, PAGE_SIZE); +- nr_read = access_remote_vm(mm, p, page, _count, 0); ++ nr_read = access_remote_vm(mm, p, page, _count, FOLL_ANON); + if (nr_read < 0) + rv = nr_read; + if (nr_read <= 0) +@@ -354,7 +354,7 @@ skip_argv: + bool final; + + _count = min3(count, len, PAGE_SIZE); +- nr_read = access_remote_vm(mm, p, page, _count, 0); ++ nr_read = access_remote_vm(mm, p, page, _count, FOLL_ANON); + if (nr_read < 0) + rv = nr_read; + if (nr_read <= 0) +@@ -970,7 +970,7 @@ static ssize_t environ_read(struct file *file, char __user *buf, + max_len = min_t(size_t, PAGE_SIZE, count); + this_len = min(max_len, this_len); + +- retval = access_remote_vm(mm, (env_start + src), page, this_len, 0); ++ retval = access_remote_vm(mm, (env_start + src), page, this_len, FOLL_ANON); + + if (retval <= 0) { + ret = retval; +diff --git a/fs/proc/generic.c b/fs/proc/generic.c +index 6047471575bb..63e20add1d08 100644 +--- a/fs/proc/generic.c ++++ b/fs/proc/generic.c +@@ -341,7 +341,7 @@ static int proc_register(struct proc_dir_entry * dir, struct proc_dir_entry * dp + write_lock(&proc_subdir_lock); + dp->parent = dir; + if (pde_subdir_insert(dir, dp) == false) { +- WARN(1, "proc_dir_entry '%s/%s' already registered\n", ++ WARN(0, "proc_dir_entry '%s/%s' already registered\n", + dir->name, dp->name); + write_unlock(&proc_subdir_lock); + proc_free_inum(dp->low_ino); +diff --git a/fs/proc/root.c b/fs/proc/root.c +old mode 100644 +new mode 100755 +index 8d3e484055a6..9c8f09e86cfa +--- a/fs/proc/root.c ++++ b/fs/proc/root.c +@@ -117,6 +117,36 @@ static struct file_system_type proc_fs_type = { + .fs_flags = FS_USERNS_MOUNT, + }; + ++#ifdef CONFIG_DEFERRED_INIICALLS ++extern void do_deferred_initcalls(void); ++static ssize_t deferred_initcalls_read_proc(struct file *file, char __user *buf, ++ size_t nbytes, loff_t *ppos) ++{ ++ static int deferred_initcalls_done = 0; ++ int len, ret; ++ char tmp[3] = "1\n"; ++ ++ if (*ppos >= 3) ++ return 0; ++ ++ if ((! deferred_initcalls_done) && ! (*ppos)) { ++ tmp[0] = '0'; ++ do_deferred_initcalls(); ++ deferred_initcalls_done = 1; ++ } ++ ++ len = min(nbytes, (size_t)3); ++ ret = copy_to_user(buf, tmp, len); ++ if (ret) ++ return -EFAULT; ++ *ppos += len; ++ return len; ++} ++ ++static const struct file_operations deferred_initcalls_fops = { ++ .read = deferred_initcalls_read_proc, ++}; ++#endif + void __init proc_root_init(void) + { + int err; +@@ -127,6 +157,9 @@ void __init proc_root_init(void) + return; + + proc_self_init(); ++#ifdef CONFIG_DEFERRED_INIICALLS ++ proc_create("deferred_initcalls", 0, NULL, &deferred_initcalls_fops); ++#endif + proc_thread_self_init(); + proc_symlink("mounts", NULL, "self/mounts"); + +diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c +index 5138e781737a..4b207b10db03 100644 +--- a/fs/proc/task_mmu.c ++++ b/fs/proc/task_mmu.c +@@ -1057,6 +1057,24 @@ static ssize_t clear_refs_write(struct file *file, const char __user *buf, + count = -EINTR; + goto out_mm; + } ++ /* ++ * Avoid to modify vma->vm_flags ++ * without locked ops while the ++ * coredump reads the vm_flags. ++ */ ++ if (!mmget_still_valid(mm)) { ++ /* ++ * Silently return "count" ++ * like if get_task_mm() ++ * failed. FIXME: should this ++ * function have returned ++ * -ESRCH if get_task_mm() ++ * failed like if ++ * get_proc_task() fails? ++ */ ++ up_write(&mm->mmap_sem); ++ goto out_mm; ++ } + for (vma = mm->mmap; vma; vma = vma->vm_next) { + vma->vm_flags &= ~VM_SOFTDIRTY; + vma_set_page_prot(vma); +diff --git a/fs/splice.c b/fs/splice.c +index 8dd79ecfd383..78822ccb9911 100644 +--- a/fs/splice.c ++++ b/fs/splice.c +@@ -1585,7 +1585,11 @@ retry: + * Get a reference to this pipe buffer, + * so we can copy the contents over. + */ +- pipe_buf_get(ipipe, ibuf); ++ if (!pipe_buf_get(ipipe, ibuf)) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } + *obuf = *ibuf; + + /* +@@ -1657,7 +1661,11 @@ static int link_pipe(struct pipe_inode_info *ipipe, + * Get a reference to this pipe buffer, + * so we can copy the contents over. + */ +- pipe_buf_get(ipipe, ibuf); ++ if (!pipe_buf_get(ipipe, ibuf)) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } + + obuf = opipe->bufs + nbuf; + *obuf = *ibuf; +diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c +index 784d667475ae..8bf425a103f0 100644 +--- a/fs/userfaultfd.c ++++ b/fs/userfaultfd.c +@@ -479,6 +479,8 @@ static int userfaultfd_release(struct inode *inode, struct file *file) + * taking the mmap_sem for writing. + */ + down_write(&mm->mmap_sem); ++ if (!mmget_still_valid(mm)) ++ goto skip_mm; + prev = NULL; + for (vma = mm->mmap; vma; vma = vma->vm_next) { + cond_resched(); +@@ -501,6 +503,7 @@ static int userfaultfd_release(struct inode *inode, struct file *file) + vma->vm_flags = new_flags; + vma->vm_userfaultfd_ctx = NULL_VM_UFFD_CTX; + } ++skip_mm: + up_write(&mm->mmap_sem); + mmput(mm); + wakeup: +@@ -802,6 +805,9 @@ static int userfaultfd_register(struct userfaultfd_ctx *ctx, + goto out; + + down_write(&mm->mmap_sem); ++ if (!mmget_still_valid(mm)) ++ goto out_unlock; ++ + vma = find_vma_prev(mm, start, &prev); + if (!vma) + goto out_unlock; +@@ -947,6 +953,9 @@ static int userfaultfd_unregister(struct userfaultfd_ctx *ctx, + goto out; + + down_write(&mm->mmap_sem); ++ if (!mmget_still_valid(mm)) ++ goto out_unlock; ++ + vma = find_vma_prev(mm, start, &prev); + if (!vma) + goto out_unlock; +diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c +index 33c389934238..7bfddcd32d73 100644 +--- a/fs/xfs/xfs_iops.c ++++ b/fs/xfs/xfs_iops.c +@@ -774,6 +774,7 @@ xfs_setattr_nonsize( + + out_cancel: + xfs_trans_cancel(tp); ++ xfs_iunlock(ip, XFS_ILOCK_EXCL); + out_dqrele: + xfs_qm_dqrele(udqp); + xfs_qm_dqrele(gdqp); +diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h +old mode 100644 +new mode 100755 +index 2e6000a4eb2c..d5e82778d5a9 +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -713,6 +713,29 @@ + KEEP(*(.initcall##level##.init)) \ + KEEP(*(.initcall##level##s.init)) \ + ++#ifdef CONFIG_DEFERRED_INIICALLS ++#define DEFERRED_INITCALLS \ ++ VMLINUX_SYMBOL(__deferred_initcall_start) = .; \ ++ *(.deferred_initcall.init) \ ++ VMLINUX_SYMBOL(__deferred_initcall_end) = .; ++ ++#define INIT_CALLS \ ++ VMLINUX_SYMBOL(__initcall_start) = .; \ ++ KEEP(*(.initcallearly.init)) \ ++ INIT_CALLS_LEVEL(0) \ ++ INIT_CALLS_LEVEL(1) \ ++ INIT_CALLS_LEVEL(2) \ ++ INIT_CALLS_LEVEL(3) \ ++ INIT_CALLS_LEVEL(4) \ ++ INIT_CALLS_LEVEL(5) \ ++ INIT_CALLS_LEVEL(rootfs) \ ++ INIT_CALLS_LEVEL(6) \ ++ INIT_CALLS_LEVEL(7) \ ++ VMLINUX_SYMBOL(__initcall_end) = .; \ ++ DEFERRED_INITCALLS ++ ++#else ++ + #define INIT_CALLS \ + VMLINUX_SYMBOL(__initcall_start) = .; \ + KEEP(*(.initcallearly.init)) \ +@@ -727,6 +750,7 @@ + INIT_CALLS_LEVEL(7) \ + VMLINUX_SYMBOL(__initcall_end) = .; + ++#endif + #define CON_INITCALL \ + VMLINUX_SYMBOL(__con_initcall_start) = .; \ + KEEP(*(.con_initcall.init)) \ +diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h +old mode 100644 +new mode 100755 +index a270f25ee7c7..6e5612f8a42f +--- a/include/linux/ahci_platform.h ++++ b/include/linux/ahci_platform.h +@@ -23,6 +23,24 @@ struct ahci_host_priv; + struct platform_device; + struct scsi_host_template; + ++//#if 1//def CONFIG_SS_SATA_AHCI_PLATFORM_HOST ++#if 0 ++struct ahci_platform_data { ++#if defined(CONFIG_ARCH_INFINITY2) ++ int (*init)(struct device *dev, void __iomem *addr , int id); ++#elif defined(CONFIG_ARCH_INFINITY2M) ++ int (*init)(struct device *dev, void __iomem *addr); ++#endif ++ void (*exit)(struct device *dev); ++ int (*suspend)(struct device *dev); ++ int (*resume)(struct device *dev); ++ const struct ata_port_info *ata_port_info; ++ unsigned int force_port_map; ++ unsigned int mask_port_map; ++}; ++#endif ++ ++ + int ahci_platform_enable_clks(struct ahci_host_priv *hpriv); + void ahci_platform_disable_clks(struct ahci_host_priv *hpriv); + int ahci_platform_enable_regulators(struct ahci_host_priv *hpriv); +diff --git a/include/linux/atalk.h b/include/linux/atalk.h +index 73fd8b7e9534..716d53799d1f 100644 +--- a/include/linux/atalk.h ++++ b/include/linux/atalk.h +@@ -150,7 +150,7 @@ extern int sysctl_aarp_retransmit_limit; + extern int sysctl_aarp_resolve_time; + + #ifdef CONFIG_SYSCTL +-extern void atalk_register_sysctl(void); ++extern int atalk_register_sysctl(void); + extern void atalk_unregister_sysctl(void); + #else + #define atalk_register_sysctl() do { } while(0) +diff --git a/include/linux/cdev.h b/include/linux/cdev.h +index f8763615a5f2..408bc09ce497 100644 +--- a/include/linux/cdev.h ++++ b/include/linux/cdev.h +@@ -4,6 +4,7 @@ + #include + #include + #include ++#include + + struct file_operations; + struct inode; +@@ -26,6 +27,10 @@ void cdev_put(struct cdev *p); + + int cdev_add(struct cdev *, dev_t, unsigned); + ++void cdev_set_parent(struct cdev *p, struct kobject *kobj); ++int cdev_device_add(struct cdev *cdev, struct device *dev); ++void cdev_device_del(struct cdev *cdev, struct device *dev); ++ + void cdev_del(struct cdev *); + + void cd_forget(struct inode *); +diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h +old mode 100644 +new mode 100755 +index eb0ed31193a3..63423ff85387 +--- a/include/linux/compiler-gcc.h ++++ b/include/linux/compiler-gcc.h +@@ -242,6 +242,12 @@ + #define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__))) + #endif + ++#if GCC_VERSION >= 90100 ++#define __copy(symbol) __attribute__((__copy__(symbol))) ++#else ++#define __copy(symbol) ++#endif ++ + /* + * GCC 'asm goto' miscompiles certain code sequences: + * +diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h +index a80516fd65c8..2e306cbb834e 100644 +--- a/include/linux/ieee80211.h ++++ b/include/linux/ieee80211.h +@@ -2630,4 +2630,57 @@ static inline bool ieee80211_action_contains_tpc(struct sk_buff *skb) + return true; + } + ++struct element { ++ u8 id; ++ u8 datalen; ++ u8 data[]; ++}; ++ ++/* element iteration helpers */ ++#define for_each_element(element, _data, _datalen) \ ++ for (element = (void *)(_data); \ ++ (u8 *)(_data) + (_datalen) - (u8 *)element >= \ ++ sizeof(*element) && \ ++ (u8 *)(_data) + (_datalen) - (u8 *)element >= \ ++ sizeof(*element) + element->datalen; \ ++ element = (void *)(element->data + element->datalen)) ++ ++#define for_each_element_id(element, _id, data, datalen) \ ++ for_each_element(element, data, datalen) \ ++ if (element->id == (_id)) ++ ++#define for_each_element_extid(element, extid, data, datalen) \ ++ for_each_element(element, data, datalen) \ ++ if (element->id == WLAN_EID_EXTENSION && \ ++ element->datalen > 0 && \ ++ element->data[0] == (extid)) ++ ++#define for_each_subelement(sub, element) \ ++ for_each_element(sub, (element)->data, (element)->datalen) ++ ++#define for_each_subelement_id(sub, id, element) \ ++ for_each_element_id(sub, id, (element)->data, (element)->datalen) ++ ++#define for_each_subelement_extid(sub, extid, element) \ ++ for_each_element_extid(sub, extid, (element)->data, (element)->datalen) ++ ++/** ++ * for_each_element_completed - determine if element parsing consumed all data ++ * @element: element pointer after for_each_element() or friends ++ * @data: same data pointer as passed to for_each_element() or friends ++ * @datalen: same data length as passed to for_each_element() or friends ++ * ++ * This function returns %true if all the data was parsed or considered ++ * while walking the elements. Only use this if your for_each_element() ++ * loop cannot be broken out of, otherwise it always returns %false. ++ * ++ * If some data was malformed, this returns %false since the last parsed ++ * element will not fill the whole remaining data. ++ */ ++static inline bool for_each_element_completed(const struct element *element, ++ const void *data, size_t datalen) ++{ ++ return (u8 *)element == (u8 *)data + datalen; ++} ++ + #endif /* LINUX_IEEE80211_H */ +diff --git a/include/linux/init.h b/include/linux/init.h +old mode 100644 +new mode 100755 +index 8e346d1bd837..e0266b4c5e66 +--- a/include/linux/init.h ++++ b/include/linux/init.h +@@ -212,6 +212,13 @@ extern bool initcall_debug; + static initcall_t __initcall_##fn \ + __used __section(.security_initcall.init) = fn + ++#ifdef CONFIG_DEFERRED_INIICALLS ++#define deferred_initcall(fn) \ ++ static initcall_t __initcall_##fn \ ++ __used __section(.deferred_initcall.init) = fn ++ ++#define deferred_module_init(x) deferred_initcall(x); ++#endif + struct obs_kernel_param { + const char *str; + int (*setup_func)(char *); +diff --git a/include/linux/ip6303_battery.h b/include/linux/ip6303_battery.h +new file mode 100644 +index 000000000000..b0862c63cca8 +--- /dev/null ++++ b/include/linux/ip6303_battery.h +@@ -0,0 +1,201 @@ ++/* ++ * ip6303_battery.h ++ * fuel-gauge systems for lithium-ion (Li+) batteries ++ * ++ * Copyright (C) 2019 SStar ++ * lei.qin ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#ifndef __IP6303_BATTERY_H_ ++#define __IP6303_BATTERY_H_ ++ ++#define GPIO_HIGH 1 ++#define GPIO_LOW 0 ++#define PMU_IRQ_ACT_LEVEL (1) ++ ++#define BIT0 0x01 ++#define BIT1 0x02 ++#define BIT2 0x04 ++#define BIT3 0x08 ++#define BIT4 0x10 ++#define BIT5 0x20 ++#define BIT6 0x40 ++#define BIT7 0x80 ++ ++typedef unsigned int MMP_ULONG; ++ ++struct ip6303_platform_data { ++ int (*battery_online)(void); ++ int (*charger_online)(void); ++ int (*charger_enable)(void); ++}; ++ ++enum _IP_PMU_INTR_MASK ++{ ++ IP_PMU_INTR_UNMASK = 0, ++ IP_PMU_INTR_MASK ++}; ++ ++enum _IP6303_REG_E ++{ ++ PSTATE_CTL0 = 0x00, ++ PSTATE_CTL1 = 0x01, ++ PSTATE_CTL2 = 0x02, ++ PSTATE_CTL3 = 0x03, ++ PSTATE_SET = 0X04, ++ PROTECT_CTL4 = 0X0A, ++ PWROFF_REC0 = 0X10, ++ PWROFF_REC1 = 0X11, ++ PWROFF_REC2 = 0X12, ++ WDOG_CTL = 0x1A, ++ DC1_VSET = 0X21, ++ DC2_VSET = 0X26, ++ DC3_VSET = 0X2B, ++ LDO_EN = 0X40, ++ LDO2_VSET = 0X42, ++ LDO3_VSET = 0X43, ++ LDO4_VSET = 0X44, ++ LDO5_VSET = 0X45, ++ CHG_ANA_CTL0 = 0x50, ++ CHG_ANA_CTL1 = 0x51, ++ CHG_DIG_CTL0 = 0x53, ++ CHG_DIG_CTL1 = 0x54, ++ CHG_DIG_CTL2 = 0x55, ++ CHG_DIG_CTL3 = 0x58, ++ ADC_ANA_CTL0 = 0x60, ++ ADC_DATA_VBAT = 0x64, ++ ADC_DATA_IBAT = 0x65, ++ ADC_DATA_ICHG = 0x66, ++ ADC_DATA_GP1 = 0x67, ++ ADC_DATA_GP2 = 0x68, ++ INTS_CTL = 0x70, ++ INTR_FLAG_0 = 0x71, ++ INTR_FLAG_1 = 0x72, ++ INTR_MASK_0 = 0x73, ++ INTR_MASK_1 = 0x74, ++ MFP_CTL0 = 0x75, ++ MFP_CTL1 = 0x76, ++}; ++ ++typedef struct _IpWDogCtl_T ++{ ++ unsigned int uTimerType : 2; //00:0.5s 01:2s 10:8s 11:16s ++ unsigned int bTimerClr : 1; //д1 Çå³ý ++ unsigned int bIsWDogEn : 1; // 1:ʹÄÜ 0:½ûÖ¹ ++ unsigned int bRsvd : 28; ++}IpWDogCtl_T, *PIpWDogCtl_T; ++ ++typedef union _IP6303_WDogCtl_U ++{ ++ unsigned int uData; ++ IpWDogCtl_T tFlag; ++}IP6303WDogCtl_U, *pIP6303WDogCtl_U; ++ ++//REG_0x00 ++typedef struct _IPPStateCtl0_T ++{ ++ MMP_ULONG bPwrOffEn : 1;//1:½øÈëS2/S3 ++ MMP_ULONG bInstPowerDown : 1;//д0 :˳Ðòµôµç£¬1:ͬʱµôµç ++ MMP_ULONG bPorOffEn : 1;//1:ʹÄÜPORÀ­µÍ¹Ø»úʹÄÜ ++ MMP_ULONG bVBusWkEn : 1;//1:ʹÄÜVBUS»½ÐÑ ++ MMP_ULONG bSOnoffWkEn : 1;//1:ʹÄ̰ܶ´ONOFF»½ÐÑ ++ MMP_ULONG bLOnoffWkEn : 1;//1:ʹÄܳ¤°´ONOFF»½ÐÑ ++ MMP_ULONG bIrqWkEn : 1;//1:ʹÄÜÍⲿÖжϻ½ÐÑ ++ MMP_ULONG bAlarmWkEn : 1;//1:ʹÄÜAlarm»½ÐÑ ++ MMP_ULONG bRsvd : 24; ++}IPPStateCtl0_T, *PIPPStateCtl0_T; ++typedef union _IPPStateCtl0_U ++{ ++ MMP_ULONG uData; ++ IPPStateCtl0_T tFlag; ++}IPPStateCtl0_U, *PIPPStateCtl0_U; ++ ++//REG_0x58 ++typedef struct _IpChgDigCtl3_T ++{ ++ MMP_ULONG bRsvd0 : 1; ++ MMP_ULONG bEnChg : 1;//1:ʹÄܳäµç ++ MMP_ULONG uChgLedMode : 1;//0:³äµçÁÁ£¬³äÂúÃ𣬷ŵçÃ𣬵͵çÂýÉÁ;1:³äµç¿ìÉÁ£¬³äÂú³£ÁÁ£¬·Åµç³£ÁÁ£¬µÍµçÂýÉÁ ++ MMP_ULONG bRsvd : 29; ++}IpChgDigCtl3_T, *PIpChgDigCtl3_T; ++typedef union _IpChgDigCtl3_U ++{ ++ MMP_ULONG uData; ++ IpChgDigCtl3_T tFlag; ++}IpChgDigCtl3_U, *PIpChgDigCtl3_U; ++ ++//REG_0x60 ++typedef struct _IpAdcAnaCtl0_T ++{ ++ MMP_ULONG bEnVBatAdc : 1;//1:ʹÄܵç³ØµçѹADC ¼ì²â ++ MMP_ULONG bEnIBatAdc : 1;//ʹÄܵç³ØµçÁ÷ADC ¼ì²â ++ MMP_ULONG bEnIChgAdc : 1;//1:ʹÄܳäµçµçÁ÷ADC ¼ì²â ++ MMP_ULONG bEnGp1Adc : 1;//1:ʹÄÜGP1 ADC ¼ì²â ++ MMP_ULONG bEnGp2Adc : 1;//1:ʹÄÜGP2 ADC ¼ì²â ++ MMP_ULONG bRsvd : 27; ++}IpAdcAnaCtl0_T, *PIpAdcAnaCtl0_T; ++typedef union _IpAdcAnaCtl0_U ++{ ++ MMP_ULONG uData; ++ IpAdcAnaCtl0_T tFlag; ++}IpAdcAnaCtl0_U, *PIpAdcAnaCtl0_U; ++ ++//REG_0x70 ++typedef struct _IpIntsCtl_T ++{ ++ MMP_ULONG bIrqPolHighValid : 1;//IRQ¼«ÐÔ1:High Valid,0:Low Valid ++ MMP_ULONG bIrqClr : 1;//д1 ºóIRQÊä³öÎÞЧµçÆ¿£¬delay 32 usºóÔÙÊä³öÓÐЧµçÆ¿ ++ MMP_ULONG bRsvd : 30; ++}IpIntsCtl_T, *PIpIntsCtl_T; ++typedef union _IpIntsCtl_U ++{ ++ MMP_ULONG uData; ++ IpIntsCtl_T tFlag; ++}IpIntsCtl_U, *PIpIntsCtl_U; ++ ++ ++//REG_0x71 ++typedef struct _IpIntrFlag0_T ++{ ++ MMP_ULONG bShortPressOnOff : 1;//¶Ì°´¼ü ++ MMP_ULONG bLongPressOnOff : 1;//³¤°´¼ü ++ MMP_ULONG bUShortPressOnOff : 1;//³¬¶Ì°´°´¼ü ++ MMP_ULONG bVBusIn : 1;//VBUS²åÈë ++ MMP_ULONG bVBusOut : 1;//VBUS°Î³ö ++ MMP_ULONG bLowBat : 1;//µç³ØµÍµç ++ MMP_ULONG bRsvd : 1; ++ MMP_ULONG bAlarm : 1;//ALARM ++ MMP_ULONG bRsvd1 : 24; ++}IpIntrFlag0_T, *PIpIntrFlag0_T; ++typedef union _IpIntrFlag0_U ++{ ++ MMP_ULONG uData; ++ IpIntrFlag0_T tFlag; ++}IpIntrFlag0_U, *PIpIntrFlag0_U; ++ ++ ++//REG_0x73 ++typedef struct _IpIntrMask0_T ++{ ++ MMP_ULONG bShortPressOnOff : 1;//¶Ì°´¼ü ++ MMP_ULONG bLongPressOnOff : 1;//³¤°´¼ü ++ MMP_ULONG bUShortPressOnOff : 1;//³¬¶Ì°´°´¼ü ++ MMP_ULONG bVBusIn : 1;//VBUS²åÈë ++ MMP_ULONG bVBusOut : 1;//VBUS°Î³ö ++ MMP_ULONG bLowBat : 1;//µç³ØµÍµç ++ MMP_ULONG bRsvd : 1; ++ MMP_ULONG bAlarm : 1;//ALARM ++ MMP_ULONG bRsvd1 : 24; ++}IpIntrMask0_T, *PIpIntrMask0_T; ++typedef union _IpIntrMask0_U ++{ ++ MMP_ULONG uData; ++ IpIntrMask0_T tFlag; ++}IpIntrMask0_U, *PIpIntrMask0_U; ++ ++#endif +diff --git a/include/linux/kasan.h b/include/linux/kasan.h +index 820c0ad54a01..228482869018 100644 +--- a/include/linux/kasan.h ++++ b/include/linux/kasan.h +@@ -10,6 +10,7 @@ struct vm_struct; + + #ifdef CONFIG_KASAN + ++#define KASAN_SHADOW_INIT 0 + #define KASAN_SHADOW_SCALE_SHIFT 3 + + #include +@@ -49,7 +50,7 @@ void kasan_unpoison_stack_above_sp_to(const void *watermark); + void kasan_alloc_pages(struct page *page, unsigned int order); + void kasan_free_pages(struct page *page, unsigned int order); + +-void kasan_cache_create(struct kmem_cache *cache, size_t *size, ++void kasan_cache_create(struct kmem_cache *cache, unsigned int *size, + unsigned long *flags); + void kasan_cache_shrink(struct kmem_cache *cache); + void kasan_cache_destroy(struct kmem_cache *cache); +@@ -95,7 +96,7 @@ static inline void kasan_alloc_pages(struct page *page, unsigned int order) {} + static inline void kasan_free_pages(struct page *page, unsigned int order) {} + + static inline void kasan_cache_create(struct kmem_cache *cache, +- size_t *size, ++ unsigned int *size, + unsigned long *flags) {} + static inline void kasan_cache_shrink(struct kmem_cache *cache) {} + static inline void kasan_cache_destroy(struct kmem_cache *cache) {} +diff --git a/include/linux/kfifo.h b/include/linux/kfifo.h +index 41eb6fdf87a8..86b5fb08e96c 100644 +--- a/include/linux/kfifo.h ++++ b/include/linux/kfifo.h +@@ -113,7 +113,8 @@ struct kfifo_rec_ptr_2 __STRUCT_KFIFO_PTR(unsigned char, 2, void); + * array is a part of the structure and the fifo type where the array is + * outside of the fifo structure. + */ +-#define __is_kfifo_ptr(fifo) (sizeof(*fifo) == sizeof(struct __kfifo)) ++#define __is_kfifo_ptr(fifo) \ ++ (sizeof(*fifo) == sizeof(STRUCT_KFIFO_PTR(typeof(*(fifo)->type)))) + + /** + * DECLARE_KFIFO_PTR - macro to declare a fifo pointer object +diff --git a/include/linux/libata.h b/include/linux/libata.h +old mode 100644 +new mode 100755 +diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h +old mode 100644 +new mode 100755 +index c1458fede1f9..b231d9d9936a +--- a/include/linux/lockdep.h ++++ b/include/linux/lockdep.h +@@ -562,9 +562,23 @@ do { \ + lock_acquire(&(lock)->dep_map, 0, 0, 1, 1, NULL, _THIS_IP_); \ + lock_release(&(lock)->dep_map, 0, _THIS_IP_); \ + } while (0) ++ ++#define lockdep_assert_irqs_enabled() do { \ ++ WARN_ONCE(debug_locks && !current->lockdep_recursion && \ ++ !current->hardirqs_enabled, \ ++ "IRQs not enabled as expected\n"); \ ++ } while (0) ++ ++#define lockdep_assert_irqs_disabled() do { \ ++ WARN_ONCE(debug_locks && !current->lockdep_recursion && \ ++ current->hardirqs_enabled, \ ++ "IRQs not disabled as expected\n"); \ ++ } while (0) + #else + # define might_lock(lock) do { } while (0) + # define might_lock_read(lock) do { } while (0) ++# define lockdep_assert_irqs_enabled() do { } while (0) ++# define lockdep_assert_irqs_disabled() do { } while (0) + #endif + + #ifdef CONFIG_LOCKDEP +diff --git a/include/linux/memblock.h b/include/linux/memblock.h +index 4024af00b137..e7c724121d84 100644 +--- a/include/linux/memblock.h ++++ b/include/linux/memblock.h +@@ -321,6 +321,7 @@ static inline bool memblock_bottom_up(void) { return false; } + /* Flags for memblock_alloc_base() amd __memblock_alloc_base() */ + #define MEMBLOCK_ALLOC_ANYWHERE (~(phys_addr_t)0) + #define MEMBLOCK_ALLOC_ACCESSIBLE 0 ++#define MEMBLOCK_ALLOC_KASAN 1 + + phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align, + phys_addr_t start, phys_addr_t end, +diff --git a/include/linux/mm.h b/include/linux/mm.h +index 2217e2f18247..fbca83634878 100644 +--- a/include/linux/mm.h ++++ b/include/linux/mm.h +@@ -759,6 +759,10 @@ static inline bool is_zone_device_page(const struct page *page) + } + #endif + ++/* 127: arbitrary random number, small enough to assemble well */ ++#define page_ref_zero_or_close_to_overflow(page) \ ++ ((unsigned int) page_ref_count(page) + 127u <= 127u) ++ + static inline void get_page(struct page *page) + { + page = compound_head(page); +@@ -766,13 +770,22 @@ static inline void get_page(struct page *page) + * Getting a normal page or the head of a compound page + * requires to already have an elevated page->_refcount. + */ +- VM_BUG_ON_PAGE(page_ref_count(page) <= 0, page); ++ VM_BUG_ON_PAGE(page_ref_zero_or_close_to_overflow(page), page); + page_ref_inc(page); + + if (unlikely(is_zone_device_page(page))) + get_zone_device_page(page); + } + ++static inline __must_check bool try_get_page(struct page *page) ++{ ++ page = compound_head(page); ++ if (WARN_ON_ONCE(page_ref_count(page) <= 0)) ++ return false; ++ page_ref_inc(page); ++ return true; ++} ++ + static inline void put_page(struct page *page) + { + page = compound_head(page); +@@ -1175,6 +1188,26 @@ void zap_page_range(struct vm_area_struct *vma, unsigned long address, + unsigned long size, struct zap_details *); + void unmap_vmas(struct mmu_gather *tlb, struct vm_area_struct *start_vma, + unsigned long start, unsigned long end); ++/* ++ * This has to be called after a get_task_mm()/mmget_not_zero() ++ * followed by taking the mmap_sem for writing before modifying the ++ * vmas or anything the coredump pretends not to change from under it. ++ * ++ * NOTE: find_extend_vma() called from GUP context is the only place ++ * that can modify the "mm" (notably the vm_start/end) under mmap_sem ++ * for reading and outside the context of the process, so it is also ++ * the only case that holds the mmap_sem for reading that must call ++ * this function. Generally if the mmap_sem is hold for reading ++ * there's no need of this check after get_task_mm()/mmget_not_zero(). ++ * ++ * This function can be obsoleted and the check can be removed, after ++ * the coredump code will hold the mmap_sem for writing before ++ * invoking the ->core_dump methods. ++ */ ++static inline bool mmget_still_valid(struct mm_struct *mm) ++{ ++ return likely(!mm->core_state); ++} + + /** + * mm_walk - callbacks for walk_page_range +@@ -2229,6 +2262,7 @@ static inline struct page *follow_page(struct vm_area_struct *vma, + #define FOLL_MLOCK 0x1000 /* lock present pages */ + #define FOLL_REMOTE 0x2000 /* we are working on non-current tsk/mm */ + #define FOLL_COW 0x4000 /* internal GUP flag */ ++#define FOLL_ANON 0x8000 /* don't do file mappings */ + + typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr, + void *data); +diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h +index e8471c2ca83a..8d6decd50220 100644 +--- a/include/linux/mm_types.h ++++ b/include/linux/mm_types.h +@@ -396,7 +396,7 @@ struct kioctx_table; + struct mm_struct { + struct vm_area_struct *mmap; /* list of VMAs */ + struct rb_root mm_rb; +- u32 vmacache_seqnum; /* per-thread vmacache */ ++ u64 vmacache_seqnum; /* per-thread vmacache */ + #ifdef CONFIG_MMU + unsigned long (*get_unmapped_area) (struct file *filp, + unsigned long addr, unsigned long len, +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +index 0b2439441cc8..4b891ea4ef0c 100644 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -23,164 +23,167 @@ + #include + + struct mmc_ios { +- unsigned int clock; /* clock rate */ +- unsigned short vdd; ++ unsigned int clock; /* clock rate */ ++ unsigned short vdd; + + /* vdd stores the bit number of the selected voltage range from below. */ + +- unsigned char bus_mode; /* command output mode */ ++ unsigned char bus_mode; /* command output mode */ + +-#define MMC_BUSMODE_OPENDRAIN 1 +-#define MMC_BUSMODE_PUSHPULL 2 ++#define MMC_BUSMODE_OPENDRAIN 1 ++#define MMC_BUSMODE_PUSHPULL 2 + +- unsigned char chip_select; /* SPI chip select */ ++ unsigned char chip_select; /* SPI chip select */ + +-#define MMC_CS_DONTCARE 0 +-#define MMC_CS_HIGH 1 +-#define MMC_CS_LOW 2 ++#define MMC_CS_DONTCARE 0 ++#define MMC_CS_HIGH 1 ++#define MMC_CS_LOW 2 + +- unsigned char power_mode; /* power supply mode */ ++ unsigned char power_mode; /* power supply mode */ + +-#define MMC_POWER_OFF 0 +-#define MMC_POWER_UP 1 +-#define MMC_POWER_ON 2 +-#define MMC_POWER_UNDEFINED 3 ++#define MMC_POWER_OFF 0 ++#define MMC_POWER_UP 1 ++#define MMC_POWER_ON 2 ++#define MMC_POWER_UNDEFINED 3 + +- unsigned char bus_width; /* data bus width */ ++ unsigned char bus_width; /* data bus width */ + +-#define MMC_BUS_WIDTH_1 0 +-#define MMC_BUS_WIDTH_4 2 +-#define MMC_BUS_WIDTH_8 3 ++#define MMC_BUS_WIDTH_1 0 ++#define MMC_BUS_WIDTH_4 2 ++#define MMC_BUS_WIDTH_8 3 + +- unsigned char timing; /* timing specification used */ ++ unsigned char timing; /* timing specification used */ + +-#define MMC_TIMING_LEGACY 0 +-#define MMC_TIMING_MMC_HS 1 +-#define MMC_TIMING_SD_HS 2 +-#define MMC_TIMING_UHS_SDR12 3 +-#define MMC_TIMING_UHS_SDR25 4 +-#define MMC_TIMING_UHS_SDR50 5 +-#define MMC_TIMING_UHS_SDR104 6 +-#define MMC_TIMING_UHS_DDR50 7 +-#define MMC_TIMING_MMC_DDR52 8 +-#define MMC_TIMING_MMC_HS200 9 +-#define MMC_TIMING_MMC_HS400 10 ++#define MMC_TIMING_LEGACY 0 ++#define MMC_TIMING_MMC_HS 1 ++#define MMC_TIMING_SD_HS 2 ++#define MMC_TIMING_UHS_SDR12 3 ++#define MMC_TIMING_UHS_SDR25 4 ++#define MMC_TIMING_UHS_SDR50 5 ++#define MMC_TIMING_UHS_SDR104 6 ++#define MMC_TIMING_UHS_DDR50 7 ++#define MMC_TIMING_MMC_DDR52 8 ++#define MMC_TIMING_MMC_HS200 9 ++#define MMC_TIMING_MMC_HS400 10 + +- unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ ++ unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ + +-#define MMC_SIGNAL_VOLTAGE_330 0 +-#define MMC_SIGNAL_VOLTAGE_180 1 +-#define MMC_SIGNAL_VOLTAGE_120 2 ++#define MMC_SIGNAL_VOLTAGE_330 0 ++#define MMC_SIGNAL_VOLTAGE_180 1 ++#define MMC_SIGNAL_VOLTAGE_120 2 + +- unsigned char drv_type; /* driver type (A, B, C, D) */ ++ unsigned char drv_type; /* driver type (A, B, C, D) */ + +-#define MMC_SET_DRIVER_TYPE_B 0 +-#define MMC_SET_DRIVER_TYPE_A 1 +-#define MMC_SET_DRIVER_TYPE_C 2 +-#define MMC_SET_DRIVER_TYPE_D 3 ++#define MMC_SET_DRIVER_TYPE_B 0 ++#define MMC_SET_DRIVER_TYPE_A 1 ++#define MMC_SET_DRIVER_TYPE_C 2 ++#define MMC_SET_DRIVER_TYPE_D 3 + +- bool enhanced_strobe; /* hs400es selection */ ++ bool enhanced_strobe; /* hs400es selection */ + }; + + struct mmc_host_ops { +- /* +- * It is optional for the host to implement pre_req and post_req in +- * order to support double buffering of requests (prepare one +- * request while another request is active). +- * pre_req() must always be followed by a post_req(). +- * To undo a call made to pre_req(), call post_req() with +- * a nonzero err condition. +- */ +- void (*post_req)(struct mmc_host *host, struct mmc_request *req, +- int err); +- void (*pre_req)(struct mmc_host *host, struct mmc_request *req, +- bool is_first_req); +- void (*request)(struct mmc_host *host, struct mmc_request *req); +- +- /* +- * Avoid calling the next three functions too often or in a "fast +- * path", since underlaying controller might implement them in an +- * expensive and/or slow way. Also note that these functions might +- * sleep, so don't call them in the atomic contexts! +- */ +- +- /* +- * Notes to the set_ios callback: +- * ios->clock might be 0. For some controllers, setting 0Hz +- * as any other frequency works. However, some controllers +- * explicitly need to disable the clock. Otherwise e.g. voltage +- * switching might fail because the SDCLK is not really quiet. +- */ +- void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); +- +- /* +- * Return values for the get_ro callback should be: +- * 0 for a read/write card +- * 1 for a read-only card +- * -ENOSYS when not supported (equal to NULL callback) +- * or a negative errno value when something bad happened +- */ +- int (*get_ro)(struct mmc_host *host); +- +- /* +- * Return values for the get_cd callback should be: +- * 0 for a absent card +- * 1 for a present card +- * -ENOSYS when not supported (equal to NULL callback) +- * or a negative errno value when something bad happened +- */ +- int (*get_cd)(struct mmc_host *host); +- +- void (*enable_sdio_irq)(struct mmc_host *host, int enable); +- +- /* optional callback for HC quirks */ +- void (*init_card)(struct mmc_host *host, struct mmc_card *card); +- +- int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios); +- +- /* Check if the card is pulling dat[0:3] low */ +- int (*card_busy)(struct mmc_host *host); +- +- /* The tuning command opcode value is different for SD and eMMC cards */ +- int (*execute_tuning)(struct mmc_host *host, u32 opcode); +- +- /* Prepare HS400 target operating frequency depending host driver */ +- int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); +- /* Prepare enhanced strobe depending host driver */ +- void (*hs400_enhanced_strobe)(struct mmc_host *host, +- struct mmc_ios *ios); +- int (*select_drive_strength)(struct mmc_card *card, +- unsigned int max_dtr, int host_drv, +- int card_drv, int *drv_type); +- void (*hw_reset)(struct mmc_host *host); +- void (*card_event)(struct mmc_host *host); +- +- /* +- * Optional callback to support controllers with HW issues for multiple +- * I/O. Returns the number of supported blocks for the request. +- */ +- int (*multi_io_quirk)(struct mmc_card *card, +- unsigned int direction, int blk_size); ++ /* ++ * It is optional for the host to implement pre_req and post_req in ++ * order to support double buffering of requests (prepare one ++ * request while another request is active). ++ * pre_req() must always be followed by a post_req(). ++ * To undo a call made to pre_req(), call post_req() with ++ * a nonzero err condition. ++ */ ++ void (*post_req)(struct mmc_host *host, struct mmc_request *req, ++ int err); ++ void (*pre_req)(struct mmc_host *host, struct mmc_request *req, ++ bool is_first_req); ++ void (*request)(struct mmc_host *host, struct mmc_request *req); ++ ++ /* ++ * Avoid calling the next three functions too often or in a "fast ++ * path", since underlaying controller might implement them in an ++ * expensive and/or slow way. Also note that these functions might ++ * sleep, so don't call them in the atomic contexts! ++ */ ++ ++ /* ++ * Notes to the set_ios callback: ++ * ios->clock might be 0. For some controllers, setting 0Hz ++ * as any other frequency works. However, some controllers ++ * explicitly need to disable the clock. Otherwise e.g. voltage ++ * switching might fail because the SDCLK is not really quiet. ++ */ ++ void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); ++ ++ /* ++ * Return values for the get_ro callback should be: ++ * 0 for a read/write card ++ * 1 for a read-only card ++ * -ENOSYS when not supported (equal to NULL callback) ++ * or a negative errno value when something bad happened ++ */ ++ int (*get_ro)(struct mmc_host *host); ++ ++ /* ++ * Return values for the get_cd callback should be: ++ * 0 for a absent card ++ * 1 for a present card ++ * -ENOSYS when not supported (equal to NULL callback) ++ * or a negative errno value when something bad happened ++ */ ++ int (*get_cd)(struct mmc_host *host); ++ ++ void (*enable_sdio_irq)(struct mmc_host *host, int enable); ++ ++ /* optional callback for HC quirks */ ++ void (*init_card)(struct mmc_host *host, struct mmc_card *card); ++ ++ int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios); ++ ++ /* Check if the card is pulling dat[0:3] low */ ++ int (*card_busy)(struct mmc_host *host); ++ ++ /* The tuning command opcode value is different for SD and eMMC cards */ ++ int (*execute_tuning)(struct mmc_host *host, u32 opcode); ++ ++ /* Prepare HS400 target operating frequency depending host driver */ ++ int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); ++ /* Prepare enhanced strobe depending host driver */ ++ void (*hs400_enhanced_strobe)(struct mmc_host *host, ++ struct mmc_ios *ios); ++ int (*select_drive_strength)(struct mmc_card *card, ++ unsigned int max_dtr, ++ int host_drv, ++ int card_drv, ++ int *drv_type); ++ void (*hw_reset)(struct mmc_host *host); ++ void (*card_event)(struct mmc_host *host); ++ ++ /* ++ * Optional callback to support controllers with HW issues for multiple ++ * I/O. Returns the number of supported blocks for the request. ++ */ ++ int (*multi_io_quirk)(struct mmc_card *card, ++ unsigned int direction, ++ int blk_size); + }; + + struct mmc_card; + struct device; + + struct mmc_async_req { +- /* active mmc request */ +- struct mmc_request *mrq; +- /* +- * Check error status of completed mmc request. +- * Returns 0 if success otherwise non zero. +- */ +- int (*err_check) (struct mmc_card *, struct mmc_async_req *); ++ /* active mmc request */ ++ struct mmc_request *mrq; ++ /* ++ * Check error status of completed mmc request. ++ * Returns 0 if success otherwise non zero. ++ */ ++ int (*err_check) (struct mmc_card *, struct mmc_async_req *); + }; + + /** + * struct mmc_slot - MMC slot functions + * +- * @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL +- * @handler_priv: MMC/SD-card slot context ++ * @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL ++ * @handler_priv: MMC/SD-card slot context + * + * Some MMC/SD host controllers implement slot-functions like card and + * write-protect detection natively. However, a large number of controllers +@@ -188,216 +191,217 @@ struct mmc_async_req { + * such slot-function drivers. + */ + struct mmc_slot { +- int cd_irq; +- void *handler_priv; ++ int cd_irq; ++ void *handler_priv; + }; + + /** + * mmc_context_info - synchronization details for mmc context +- * @is_done_rcv wake up reason was done request +- * @is_new_req wake up reason was new request +- * @is_waiting_last_req mmc context waiting for single running request +- * @wait wait queue +- * @lock lock to protect data fields ++ * @is_done_rcv wake up reason was done request ++ * @is_new_req wake up reason was new request ++ * @is_waiting_last_req mmc context waiting for single running request ++ * @wait wait queue ++ * @lock lock to protect data fields + */ + struct mmc_context_info { +- bool is_done_rcv; +- bool is_new_req; +- bool is_waiting_last_req; +- wait_queue_head_t wait; +- spinlock_t lock; ++ bool is_done_rcv; ++ bool is_new_req; ++ bool is_waiting_last_req; ++ wait_queue_head_t wait; ++ spinlock_t lock; + }; + + struct regulator; + struct mmc_pwrseq; + + struct mmc_supply { +- struct regulator *vmmc; /* Card power supply */ +- struct regulator *vqmmc; /* Optional Vccq supply */ ++ struct regulator *vmmc; /* Card power supply */ ++ struct regulator *vqmmc; /* Optional Vccq supply */ + }; + + struct mmc_host { +- struct device *parent; +- struct device class_dev; +- int index; +- const struct mmc_host_ops *ops; +- struct mmc_pwrseq *pwrseq; +- unsigned int f_min; +- unsigned int f_max; +- unsigned int f_init; +- u32 ocr_avail; +- u32 ocr_avail_sdio; /* SDIO-specific OCR */ +- u32 ocr_avail_sd; /* SD-specific OCR */ +- u32 ocr_avail_mmc; /* MMC-specific OCR */ ++ struct device *parent; ++ struct device class_dev; ++ int index; ++ const struct mmc_host_ops *ops; ++ struct mmc_pwrseq *pwrseq; ++ unsigned int f_min; ++ unsigned int f_max; ++ unsigned int f_init; ++ u32 ocr_avail; ++ u32 ocr_avail_sdio; /* SDIO-specific OCR */ ++ u32 ocr_avail_sd; /* SD-specific OCR */ ++ u32 ocr_avail_mmc; /* MMC-specific OCR */ + #ifdef CONFIG_PM_SLEEP +- struct notifier_block pm_notify; ++ struct notifier_block pm_notify; + #endif +- u32 max_current_330; +- u32 max_current_300; +- u32 max_current_180; +- +-#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +-#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +-#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +-#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +-#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +-#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +-#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +-#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +-#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +-#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +-#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +-#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +-#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +-#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +-#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +-#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +-#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ +- +- u32 caps; /* Host capabilities */ +- +-#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ +-#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ +-#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ +-#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ +-#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ +-#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ +-#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ +-#define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ +-#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ +-#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ +-#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ +-#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ +- /* DDR mode at 1.8V */ +-#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ +- /* DDR mode at 1.2V */ +-#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ +-#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ +-#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ +-#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ +-#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ +-#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ +-#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ +-#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ +-#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ +-#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ +-#define MMC_CAP_CMD_DURING_TFR (1 << 29) /* Commands during data transfer */ +-#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ +-#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ +- +- u32 caps2; /* More host capabilities */ +- +-#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ +-#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ +-#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ +-#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ +-#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ +- MMC_CAP2_HS200_1_2V_SDR) +-#define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ +-#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ +-#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ +-#define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */ +-#define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */ +-#define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ +- MMC_CAP2_PACKED_WR) +-#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ +-#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ +-#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ +-#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ +- MMC_CAP2_HS400_1_2V) +-#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) ++ u32 max_current_330; ++ u32 max_current_300; ++ u32 max_current_180; ++ ++#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ ++#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ ++#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ ++#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ ++#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ ++#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ ++#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ ++#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ ++#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ ++#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ ++#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ ++#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ ++#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ ++#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ ++#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ ++#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ ++#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ ++ ++ u32 caps; /* Host capabilities */ ++ ++#define MMC_CAP_1_BIT_DATA (0) /* TL-Added: Can the host do 1 bit transfers */ ++#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ ++#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ ++#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ ++#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ ++#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ ++#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ ++#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ ++#define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ ++#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ ++#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ ++#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ ++#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ ++ /* DDR mode at 1.8V */ ++#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ ++ /* DDR mode at 1.2V */ ++#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ ++#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ ++#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ ++#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ ++#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ ++#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ ++#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ ++#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ ++#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ ++#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ ++#define MMC_CAP_CMD_DURING_TFR (1 << 29) /* Commands during data transfer */ ++#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ ++#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ ++ ++ u32 caps2; /* More host capabilities */ ++ ++#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ ++#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ ++#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ ++#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ ++#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ ++ MMC_CAP2_HS200_1_2V_SDR) ++#define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ ++#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ ++#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ ++#define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */ ++#define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */ ++#define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ ++ MMC_CAP2_PACKED_WR) ++#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ ++#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ ++#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ ++#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ ++ MMC_CAP2_HS400_1_2V) ++#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) + #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) +-#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ +-#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */ +-#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ +-#define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */ +-#define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ +- +- mmc_pm_flag_t pm_caps; /* supported pm features */ +- +- /* host specific block data */ +- unsigned int max_seg_size; /* see blk_queue_max_segment_size */ +- unsigned short max_segs; /* see blk_queue_max_segments */ +- unsigned short unused; +- unsigned int max_req_size; /* maximum number of bytes in one req */ +- unsigned int max_blk_size; /* maximum size of one mmc block */ +- unsigned int max_blk_count; /* maximum number of blocks in one req */ +- unsigned int max_busy_timeout; /* max busy timeout in ms */ +- +- /* private data */ +- spinlock_t lock; /* lock for claim and bus ops */ +- +- struct mmc_ios ios; /* current io bus settings */ +- +- /* group bitfields together to minimize padding */ +- unsigned int use_spi_crc:1; +- unsigned int claimed:1; /* host exclusively claimed */ +- unsigned int bus_dead:1; /* bus has been released */ ++#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ ++#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */ ++#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ ++#define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */ ++#define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ ++ ++ mmc_pm_flag_t pm_caps; /* supported pm features */ ++ ++ /* host specific block data */ ++ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ ++ unsigned short max_segs; /* see blk_queue_max_segments */ ++ unsigned short unused; ++ unsigned int max_req_size; /* maximum number of bytes in one req */ ++ unsigned int max_blk_size; /* maximum size of one mmc block */ ++ unsigned int max_blk_count; /* maximum number of blocks in one req */ ++ unsigned int max_busy_timeout; /* max busy timeout in ms */ ++ ++ /* private data */ ++ spinlock_t lock; /* lock for claim and bus ops */ ++ ++ struct mmc_ios ios; /* current io bus settings */ ++ ++ /* group bitfields together to minimize padding */ ++ unsigned int use_spi_crc:1; ++ unsigned int claimed:1; /* host exclusively claimed */ ++ unsigned int bus_dead:1; /* bus has been released */ + #ifdef CONFIG_MMC_DEBUG +- unsigned int removed:1; /* host is being removed */ ++ unsigned int removed:1; /* host is being removed */ + #endif +- unsigned int can_retune:1; /* re-tuning can be used */ +- unsigned int doing_retune:1; /* re-tuning in progress */ +- unsigned int retune_now:1; /* do re-tuning at next req */ +- unsigned int retune_paused:1; /* re-tuning is temporarily disabled */ ++ unsigned int can_retune:1; /* re-tuning can be used */ ++ unsigned int doing_retune:1; /* re-tuning in progress */ ++ unsigned int retune_now:1; /* do re-tuning at next req */ ++ unsigned int retune_paused:1; /* re-tuning is temporarily disabled */ + +- int rescan_disable; /* disable card detection */ +- int rescan_entered; /* used with nonremovable devices */ ++ int rescan_disable; /* disable card detection */ ++ int rescan_entered; /* used with nonremovable devices */ + +- int need_retune; /* re-tuning is needed */ +- int hold_retune; /* hold off re-tuning */ +- unsigned int retune_period; /* re-tuning period in secs */ +- struct timer_list retune_timer; /* for periodic re-tuning */ ++ int need_retune; /* re-tuning is needed */ ++ int hold_retune; /* hold off re-tuning */ ++ unsigned int retune_period; /* re-tuning period in secs */ ++ struct timer_list retune_timer; /* for periodic re-tuning */ + +- bool trigger_card_event; /* card_event necessary */ ++ bool trigger_card_event; /* card_event necessary */ + +- struct mmc_card *card; /* device attached to this host */ ++ struct mmc_card *card; /* device attached to this host */ + +- wait_queue_head_t wq; +- struct task_struct *claimer; /* task that has host claimed */ +- int claim_cnt; /* "claim" nesting count */ ++ wait_queue_head_t wq; ++ struct task_struct *claimer; /* task that has host claimed */ ++ int claim_cnt; /* "claim" nesting count */ + +- struct delayed_work detect; +- int detect_change; /* card detect flag */ +- struct mmc_slot slot; ++ struct delayed_work detect; ++ int detect_change; /* card detect flag */ ++ struct mmc_slot slot; + +- const struct mmc_bus_ops *bus_ops; /* current bus driver */ +- unsigned int bus_refs; /* reference counter */ ++ const struct mmc_bus_ops *bus_ops; /* current bus driver */ ++ unsigned int bus_refs; /* reference counter */ + +- unsigned int sdio_irqs; +- struct task_struct *sdio_irq_thread; +- bool sdio_irq_pending; +- atomic_t sdio_irq_thread_abort; ++ unsigned int sdio_irqs; ++ struct task_struct *sdio_irq_thread; ++ bool sdio_irq_pending; ++ atomic_t sdio_irq_thread_abort; + +- mmc_pm_flag_t pm_flags; /* requested pm features */ ++ mmc_pm_flag_t pm_flags; /* requested pm features */ + +- struct led_trigger *led; /* activity led */ ++ struct led_trigger *led; /* activity led */ + + #ifdef CONFIG_REGULATOR +- bool regulator_enabled; /* regulator state */ ++ bool regulator_enabled; /* regulator state */ + #endif +- struct mmc_supply supply; ++ struct mmc_supply supply; + +- struct dentry *debugfs_root; ++ struct dentry *debugfs_root; + +- struct mmc_async_req *areq; /* active async req */ +- struct mmc_context_info context_info; /* async synchronization info */ ++ struct mmc_async_req *areq; /* active async req */ ++ struct mmc_context_info context_info; /* async synchronization info */ + +- /* Ongoing data transfer that allows commands during transfer */ +- struct mmc_request *ongoing_mrq; ++ /* Ongoing data transfer that allows commands during transfer */ ++ struct mmc_request *ongoing_mrq; + + #ifdef CONFIG_FAIL_MMC_REQUEST +- struct fault_attr fail_mmc_request; ++ struct fault_attr fail_mmc_request; + #endif + +- unsigned int actual_clock; /* Actual HC clock rate */ ++ unsigned int actual_clock; /* Actual HC clock rate */ + +- unsigned int slotno; /* used for sdio acpi binding */ ++ unsigned int slotno; /* used for sdio acpi binding */ + +- int dsr_req; /* DSR value is valid */ +- u32 dsr; /* optional driver stage (DSR) value */ ++ int dsr_req; /* DSR value is valid */ ++ u32 dsr; /* optional driver stage (DSR) value */ + +- unsigned long private[0] ____cacheline_aligned; ++ unsigned long private[0] ____cacheline_aligned; + }; + + struct mmc_host *mmc_alloc_host(int extra, struct device *); +@@ -408,14 +412,14 @@ int mmc_of_parse(struct mmc_host *host); + + static inline void *mmc_priv(struct mmc_host *host) + { +- return (void *)host->private; ++ return (void *)host->private; + } + +-#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) ++#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) + +-#define mmc_dev(x) ((x)->parent) +-#define mmc_classdev(x) (&(x)->class_dev) +-#define mmc_hostname(x) (dev_name(&(x)->class_dev)) ++#define mmc_dev(x) ((x)->parent) ++#define mmc_classdev(x) (&(x)->class_dev) ++#define mmc_hostname(x) (dev_name(&(x)->class_dev)) + + int mmc_power_save_host(struct mmc_host *host); + int mmc_power_restore_host(struct mmc_host *host); +@@ -426,10 +430,10 @@ void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq); + + static inline void mmc_signal_sdio_irq(struct mmc_host *host) + { +- host->ops->enable_sdio_irq(host, 0); +- host->sdio_irq_pending = true; +- if (host->sdio_irq_thread) +- wake_up_process(host->sdio_irq_thread); ++ host->ops->enable_sdio_irq(host, 0); ++ host->sdio_irq_pending = true; ++ if (host->sdio_irq_thread) ++ wake_up_process(host->sdio_irq_thread); + } + + void sdio_run_irqs(struct mmc_host *host); +@@ -437,26 +441,26 @@ void sdio_run_irqs(struct mmc_host *host); + #ifdef CONFIG_REGULATOR + int mmc_regulator_get_ocrmask(struct regulator *supply); + int mmc_regulator_set_ocr(struct mmc_host *mmc, +- struct regulator *supply, +- unsigned short vdd_bit); ++ struct regulator *supply, ++ unsigned short vdd_bit); + int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios); + #else + static inline int mmc_regulator_get_ocrmask(struct regulator *supply) + { +- return 0; ++ return 0; + } + + static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, +- struct regulator *supply, +- unsigned short vdd_bit) ++ struct regulator *supply, ++ unsigned short vdd_bit) + { +- return 0; ++ return 0; + } + + static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc, +- struct mmc_ios *ios) ++ struct mmc_ios *ios) + { +- return -EINVAL; ++ return -EINVAL; + } + #endif + +@@ -464,86 +468,86 @@ int mmc_regulator_get_supply(struct mmc_host *mmc); + + static inline int mmc_card_is_removable(struct mmc_host *host) + { +- return !(host->caps & MMC_CAP_NONREMOVABLE); ++ return !(host->caps & MMC_CAP_NONREMOVABLE); + } + + static inline int mmc_card_keep_power(struct mmc_host *host) + { +- return host->pm_flags & MMC_PM_KEEP_POWER; ++ return host->pm_flags & MMC_PM_KEEP_POWER; + } + + static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) + { +- return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; ++ return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; + } + + static inline int mmc_host_cmd23(struct mmc_host *host) + { +- return host->caps & MMC_CAP_CMD23; ++ return host->caps & MMC_CAP_CMD23; + } + + static inline int mmc_boot_partition_access(struct mmc_host *host) + { +- return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC); ++ return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC); + } + + static inline int mmc_host_uhs(struct mmc_host *host) + { +- return host->caps & +- (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | +- MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | +- MMC_CAP_UHS_DDR50); ++ return host->caps & ++ (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | ++ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | ++ MMC_CAP_UHS_DDR50); + } + + static inline int mmc_host_packed_wr(struct mmc_host *host) + { +- return host->caps2 & MMC_CAP2_PACKED_WR; ++ return host->caps2 & MMC_CAP2_PACKED_WR; + } + + static inline int mmc_card_hs(struct mmc_card *card) + { +- return card->host->ios.timing == MMC_TIMING_SD_HS || +- card->host->ios.timing == MMC_TIMING_MMC_HS; ++ return card->host->ios.timing == MMC_TIMING_SD_HS || ++ card->host->ios.timing == MMC_TIMING_MMC_HS; + } + + static inline int mmc_card_uhs(struct mmc_card *card) + { +- return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && +- card->host->ios.timing <= MMC_TIMING_UHS_DDR50; ++ return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && ++ card->host->ios.timing <= MMC_TIMING_UHS_DDR50; + } + + static inline bool mmc_card_hs200(struct mmc_card *card) + { +- return card->host->ios.timing == MMC_TIMING_MMC_HS200; ++ return card->host->ios.timing == MMC_TIMING_MMC_HS200; + } + + static inline bool mmc_card_ddr52(struct mmc_card *card) + { +- return card->host->ios.timing == MMC_TIMING_MMC_DDR52; ++ return card->host->ios.timing == MMC_TIMING_MMC_DDR52; + } + + static inline bool mmc_card_hs400(struct mmc_card *card) + { +- return card->host->ios.timing == MMC_TIMING_MMC_HS400; ++ return card->host->ios.timing == MMC_TIMING_MMC_HS400; + } + + static inline bool mmc_card_hs400es(struct mmc_card *card) + { +- return card->host->ios.enhanced_strobe; ++ return card->host->ios.enhanced_strobe; + } + + void mmc_retune_timer_stop(struct mmc_host *host); + + static inline void mmc_retune_needed(struct mmc_host *host) + { +- if (host->can_retune) +- host->need_retune = 1; ++ if (host->can_retune) ++ host->need_retune = 1; + } + + static inline void mmc_retune_recheck(struct mmc_host *host) + { +- if (host->hold_retune <= 1) +- host->retune_now = 1; ++ if (host->hold_retune <= 1) ++ host->retune_now = 1; + } + + void mmc_retune_pause(struct mmc_host *host); +diff --git a/include/linux/module.h b/include/linux/module.h +old mode 100644 +new mode 100755 +index d2224a09b4b5..99a06c665fa8 +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -129,13 +129,13 @@ extern void cleanup_module(void); + #define module_init(initfn) \ + static inline initcall_t __inittest(void) \ + { return initfn; } \ +- int init_module(void) __attribute__((alias(#initfn))); ++ int init_module(void) __copy(initfn) __attribute__((alias(#initfn))); + + /* This is only required if you want to be unloadable. */ + #define module_exit(exitfn) \ + static inline exitcall_t __exittest(void) \ + { return exitfn; } \ +- void cleanup_module(void) __attribute__((alias(#exitfn))); ++ void cleanup_module(void) __copy(exitfn) __attribute__((alias(#exitfn))); + + #endif + +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index d8905a229f34..3f5cc9b163b6 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -824,8 +824,10 @@ struct nand_chip { + int (*setup_data_interface)(struct mtd_info *mtd, + const struct nand_data_interface *conf, + bool check_only); +- +- ++#if defined(CONFIG_MS_NAND) || defined(CONFIG_MS_NAND_MODULE) || defined(CONFIG_MS_SPINAND)|| defined(CONFIG_MS_SPINAND_MODULE) ++ int (*mtd_param_init)(struct mtd_info *mtd,struct nand_chip *chip, int *maf_id, int *dev_id, ++ const struct nand_flash_dev *type); ++#endif + int chip_delay; + unsigned int options; + unsigned int bbt_options; +diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h +index 78ed8105e64d..f72d36c7cfae 100644 +--- a/include/linux/perf_event.h ++++ b/include/linux/perf_event.h +@@ -470,7 +470,7 @@ struct pmu { + */ + struct perf_addr_filter { + struct list_head entry; +- struct inode *inode; ++ struct path path; + unsigned long offset; + unsigned long size; + unsigned int range : 1, +diff --git a/include/linux/pipe_fs_i.h b/include/linux/pipe_fs_i.h +index e7497c9dde7f..acfb484c3b53 100644 +--- a/include/linux/pipe_fs_i.h ++++ b/include/linux/pipe_fs_i.h +@@ -107,18 +107,20 @@ struct pipe_buf_operations { + /* + * Get a reference to the pipe buffer. + */ +- void (*get)(struct pipe_inode_info *, struct pipe_buffer *); ++ bool (*get)(struct pipe_inode_info *, struct pipe_buffer *); + }; + + /** + * pipe_buf_get - get a reference to a pipe_buffer + * @pipe: the pipe that the buffer belongs to + * @buf: the buffer to get a reference to ++ * ++ * Return: %true if the reference was successfully obtained. + */ +-static inline void pipe_buf_get(struct pipe_inode_info *pipe, ++static inline __must_check bool pipe_buf_get(struct pipe_inode_info *pipe, + struct pipe_buffer *buf) + { +- buf->ops->get(pipe, buf); ++ return buf->ops->get(pipe, buf); + } + + /** +@@ -178,7 +180,7 @@ struct pipe_inode_info *alloc_pipe_info(void); + void free_pipe_info(struct pipe_inode_info *); + + /* Generic pipe buffer ops functions */ +-void generic_pipe_buf_get(struct pipe_inode_info *, struct pipe_buffer *); ++bool generic_pipe_buf_get(struct pipe_inode_info *, struct pipe_buffer *); + int generic_pipe_buf_confirm(struct pipe_inode_info *, struct pipe_buffer *); + int generic_pipe_buf_steal(struct pipe_inode_info *, struct pipe_buffer *); + void generic_pipe_buf_release(struct pipe_inode_info *, struct pipe_buffer *); +diff --git a/include/linux/posix-clock.h b/include/linux/posix-clock.h +index 34c4498b800f..6b192187c7ba 100644 +--- a/include/linux/posix-clock.h ++++ b/include/linux/posix-clock.h +@@ -104,29 +104,32 @@ struct posix_clock_operations { + * + * @ops: Functional interface to the clock + * @cdev: Character device instance for this clock +- * @kref: Reference count. ++ * @dev: Pointer to the clock's device. + * @rwsem: Protects the 'zombie' field from concurrent access. + * @zombie: If 'zombie' is true, then the hardware has disappeared. +- * @release: A function to free the structure when the reference count reaches +- * zero. May be NULL if structure is statically allocated. + * + * Drivers should embed their struct posix_clock within a private + * structure, obtaining a reference to it during callbacks using + * container_of(). ++ * ++ * Drivers should supply an initialized but not exposed struct device ++ * to posix_clock_register(). It is used to manage lifetime of the ++ * driver's private structure. It's 'release' field should be set to ++ * a release function for this private structure. + */ + struct posix_clock { + struct posix_clock_operations ops; + struct cdev cdev; +- struct kref kref; ++ struct device *dev; + struct rw_semaphore rwsem; + bool zombie; +- void (*release)(struct posix_clock *clk); + }; + + /** + * posix_clock_register() - register a new clock +- * @clk: Pointer to the clock. Caller must provide 'ops' and 'release' +- * @devid: Allocated device id ++ * @clk: Pointer to the clock. Caller must provide 'ops' field ++ * @dev: Pointer to the initialized device. Caller must provide ++ * 'release' field + * + * A clock driver calls this function to register itself with the + * clock device subsystem. If 'clk' points to dynamically allocated +@@ -135,7 +138,7 @@ struct posix_clock { + * + * Returns zero on success, non-zero otherwise. + */ +-int posix_clock_register(struct posix_clock *clk, dev_t devid); ++int posix_clock_register(struct posix_clock *clk, struct device *dev); + + /** + * posix_clock_unregister() - unregister a clock +diff --git a/include/linux/posix-timers.h b/include/linux/posix-timers.h +index 62d44c176071..e4b8678183f5 100644 +--- a/include/linux/posix-timers.h ++++ b/include/linux/posix-timers.h +@@ -65,8 +65,8 @@ struct k_itimer { + spinlock_t it_lock; + clockid_t it_clock; /* which timer type */ + timer_t it_id; /* timer id */ +- int it_overrun; /* overrun on pending signal */ +- int it_overrun_last; /* overrun on last delivered signal */ ++ s64 it_overrun; /* overrun on pending signal */ ++ s64 it_overrun_last; /* overrun on last delivered signal */ + int it_requeue_pending; /* waiting to requeue this timer */ + #define REQUEUE_PENDING 1 + int it_sigev_notify; /* notify word of sigevent struct */ +diff --git a/include/linux/random.h b/include/linux/random.h +index 16ab429735a7..30972a998876 100644 +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -8,6 +8,7 @@ + + #include + #include ++#include + + #include + +@@ -55,6 +56,8 @@ struct rnd_state { + __u32 s1, s2, s3, s4; + }; + ++DECLARE_PER_CPU(struct rnd_state, net_rand_state); ++ + u32 prandom_u32_state(struct rnd_state *state); + void prandom_bytes_state(struct rnd_state *state, void *buf, size_t nbytes); + void prandom_seed_full_state(struct rnd_state __percpu *pcpu_state); +diff --git a/include/linux/sched.h b/include/linux/sched.h +index a4d0afc009a7..ab1a472e51e7 100644 +--- a/include/linux/sched.h ++++ b/include/linux/sched.h +@@ -1558,7 +1558,7 @@ struct task_struct { + + struct mm_struct *mm, *active_mm; + /* per-thread vma caching */ +- u32 vmacache_seqnum; ++ u64 vmacache_seqnum; + struct vm_area_struct *vmacache[VMACACHE_SIZE]; + #if defined(SPLIT_RSS_COUNTING) + struct task_rss_stat rss_stat; +@@ -2042,7 +2042,7 @@ static inline bool in_vfork(struct task_struct *tsk) + extern void task_numa_fault(int last_node, int node, int pages, int flags); + extern pid_t task_numa_group_id(struct task_struct *p); + extern void set_numabalancing_state(bool enabled); +-extern void task_numa_free(struct task_struct *p); ++extern void task_numa_free(struct task_struct *p, bool final); + extern bool should_numa_migrate_memory(struct task_struct *p, struct page *page, + int src_nid, int dst_cpu); + #else +@@ -2057,7 +2057,7 @@ static inline pid_t task_numa_group_id(struct task_struct *p) + static inline void set_numabalancing_state(bool enabled) + { + } +-static inline void task_numa_free(struct task_struct *p) ++static inline void task_numa_free(struct task_struct *p, bool final) + { + } + static inline bool should_numa_migrate_memory(struct task_struct *p, +diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h +index 601dfa849d30..13bf13b0dd23 100644 +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -222,7 +222,8 @@ + /* Maximum value in skb->csum_level */ + #define SKB_MAX_CSUM_LEVEL 3 + +-#define SKB_DATA_ALIGN(X) ALIGN(X, SMP_CACHE_BYTES) ++//#define SKB_DATA_ALIGN(X) ALIGN(X, SMP_CACHE_BYTES) ++#define SKB_DATA_ALIGN(X) ALIGN(X, 256) + #define SKB_WITH_OVERHEAD(X) \ + ((X) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) + #define SKB_MAX_ORDER(X, ORDER) \ +@@ -642,9 +643,14 @@ struct sk_buff { + struct skb_mstamp skb_mstamp; + }; + }; +- struct rb_node rbnode; /* used in netem & tcp stack */ ++ struct rb_node rbnode; /* used in netem, ip4 defrag, and tcp stack */ + }; +- struct sock *sk; ++ ++ union { ++ struct sock *sk; ++ int ip_defrag_offset; ++ }; ++ + struct net_device *dev; + + /* +@@ -2413,7 +2419,7 @@ static inline void __skb_queue_purge(struct sk_buff_head *list) + kfree_skb(skb); + } + +-void skb_rbtree_purge(struct rb_root *root); ++unsigned int skb_rbtree_purge(struct rb_root *root); + + void *netdev_alloc_frag(unsigned int fragsz); + +@@ -2982,6 +2988,14 @@ static inline int __skb_grow_rcsum(struct sk_buff *skb, unsigned int len) + return __skb_grow(skb, len); + } + ++#define rb_to_skb(rb) rb_entry_safe(rb, struct sk_buff, rbnode) ++ ++#define rb_to_skb(rb) rb_entry_safe(rb, struct sk_buff, rbnode) ++#define skb_rb_first(root) rb_to_skb(rb_first(root)) ++#define skb_rb_last(root) rb_to_skb(rb_last(root)) ++#define skb_rb_next(skb) rb_to_skb(rb_next(&(skb)->rbnode)) ++#define skb_rb_prev(skb) rb_to_skb(rb_prev(&(skb)->rbnode)) ++ + #define skb_queue_walk(queue, skb) \ + for (skb = (queue)->next; \ + skb != (struct sk_buff *)(queue); \ +@@ -2996,6 +3010,18 @@ static inline int __skb_grow_rcsum(struct sk_buff *skb, unsigned int len) + for (; skb != (struct sk_buff *)(queue); \ + skb = skb->next) + ++#define skb_rbtree_walk(skb, root) \ ++ for (skb = skb_rb_first(root); skb != NULL; \ ++ skb = skb_rb_next(skb)) ++ ++#define skb_rbtree_walk_from(skb) \ ++ for (; skb != NULL; \ ++ skb = skb_rb_next(skb)) ++ ++#define skb_rbtree_walk_from_safe(skb, tmp) \ ++ for (; tmp = skb ? skb_rb_next(skb) : NULL, (skb != NULL); \ ++ skb = tmp) ++ + #define skb_queue_walk_from_safe(queue, skb, tmp) \ + for (tmp = skb->next; \ + skb != (struct sk_buff *)(queue); \ +diff --git a/include/linux/sys_soc.h b/include/linux/sys_soc.h +old mode 100644 +new mode 100755 +index 2739ccb69571..982acc194b91 +--- a/include/linux/sys_soc.h ++++ b/include/linux/sys_soc.h +@@ -13,6 +13,9 @@ struct soc_device_attribute { + const char *family; + const char *revision; + const char *soc_id; ++#ifdef CONFIG_ARCH_SSTAR ++ const char *api_version; ++#endif + }; + + /** +diff --git a/include/linux/tcp.h b/include/linux/tcp.h +index f50b717ce644..0dbb914e45e1 100644 +--- a/include/linux/tcp.h ++++ b/include/linux/tcp.h +@@ -433,4 +433,7 @@ static inline void tcp_saved_syn_free(struct tcp_sock *tp) + tp->saved_syn = NULL; + } + ++int tcp_skb_shift(struct sk_buff *to, struct sk_buff *from, int pcount, ++ int shiftlen); ++ + #endif /* _LINUX_TCP_H */ +diff --git a/include/linux/usb.h b/include/linux/usb.h +old mode 100644 +new mode 100755 +index eba1f10e8cfd..f8ecaa6ec1be +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -7,6 +7,9 @@ + #define USB_MAJOR 180 + #define USB_DEVICE_MAJOR 189 + ++#if defined(CONFIG_MP_USB_MSTAR) ++#define HOTPLUG //tony add for hotplug ++#endif + + #ifdef __KERNEL__ + +@@ -336,11 +339,11 @@ struct usb_host_bos { + }; + + int __usb_get_extra_descriptor(char *buffer, unsigned size, +- unsigned char type, void **ptr); ++ unsigned char type, void **ptr, size_t min); + #define usb_get_extra_descriptor(ifpoint, type, ptr) \ + __usb_get_extra_descriptor((ifpoint)->extra, \ + (ifpoint)->extralen, \ +- type, (void **)ptr) ++ type, (void **)ptr, sizeof(**(ptr))) + + /* ----------------------------------------------------------------------- */ + +@@ -544,6 +547,9 @@ struct usb3_lpm_parameters { + */ + struct usb_device { + int devnum; ++#if defined(CONFIG_MP_USB_MSTAR) && defined(HOTPLUG) ++ int devnum1; //tony for hotplug check ++#endif + char devpath[16]; + u32 route; + enum usb_device_state state; +diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h +index 4616a49a1c2e..8b40a59f8b97 100644 +--- a/include/linux/usb/composite.h ++++ b/include/linux/usb/composite.h +@@ -51,7 +51,7 @@ + #define USB_GADGET_DELAYED_STATUS 0x7fff /* Impossibly large value */ + + /* big enough to hold our biggest descriptor */ +-#define USB_COMP_EP0_BUFSIZ 1024 ++#define USB_COMP_EP0_BUFSIZ (1024 * 8) + + #define USB_MS_TO_HS_INTERVAL(x) (ilog2((x * 1000 / 125)) + 1) + struct usb_configuration; +@@ -248,6 +248,11 @@ int usb_interface_id(struct usb_configuration *, struct usb_function *); + int config_ep_by_speed(struct usb_gadget *g, struct usb_function *f, + struct usb_ep *_ep); + ++int config_ep_by_endp_desc(struct usb_gadget *g, ++ struct usb_endpoint_descriptor *chosen_desc, ++ struct usb_ss_ep_comp_descriptor *comp_desc, ++ struct usb_ep *_ep); ++ + #define MAX_CONFIG_INTERFACES 16 /* arbitrary; max 255 */ + + /** +diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h +index e479033bd782..701fbc0edde8 100644 +--- a/include/linux/usb/ehci_def.h ++++ b/include/linux/usb/ehci_def.h +@@ -112,7 +112,10 @@ struct ehci_regs { + u32 frame_list; /* points to periodic list */ + /* ASYNCLISTADDR: offset 0x18 */ + u32 async_next; /* address of next async queue head */ +- ++#if (MP_USB_MSTAR==1) ++ u32 txfill_tuning; /* for compile */ ++#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ ++#else + u32 reserved1[2]; + + /* TXFILLTUNING: offset 0x24 */ +@@ -120,13 +123,20 @@ struct ehci_regs { + #define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ + + u32 reserved2[6]; ++#endif + ++#if (MP_USB_MSTAR==0) + /* CONFIGFLAG: offset 0x40 */ + u32 configured_flag; + #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ ++#endif + ++#if (MP_USB_MSTAR==1) ++ u32 port_status[1]; /* up to N_PORTS */ ++#else + /* PORTSC: offset 0x44 */ + u32 port_status[0]; /* up to N_PORTS */ ++#endif + /* EHCI 1.1 addendum */ + #define PORTSC_SUSPEND_STS_ACK 0 + #define PORTSC_SUSPEND_STS_NYET 1 +@@ -163,6 +173,28 @@ struct ehci_regs { + #define PORT_CSC (1<<1) /* connect status change */ + #define PORT_CONNECT (1<<0) /* device connected */ + #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) ++#if (MP_USB_MSTAR==1) ++ u32 hcmisc ; ++ u32 reserved1 [2]; ++ u32 bmcs; ++ u32 busmonintsts; ++ u32 busmoninten; ++ u32 configured_flag; /* for compile */ ++#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ ++ u32 reserved3 [1]; ++ u32 usbmode; /* for compile */ ++#define USBMODE_SDIS (1<<3) /* Stream disable */ ++#define USBMODE_BE (1<<2) /* BE/LE endianness select */ ++#define USBMODE_CM_HC (3<<0) /* host controller mode */ ++#define USBMODE_CM_IDLE (0<<0) /* idle state */ ++ u32 hostpc[1]; /* for compile */ ++#define HOSTPC_PHCD (1<<22) /* Phy clock disable */ ++#define HOSTPC_PSPD (3<<25) /* Port speed detection */ ++ u32 usbmode_ex; /* for compile */ ++#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ ++#define USBMODE_EX_HC (3<<0) /* host controller mode */ ++}; ++#else + + u32 reserved3[9]; + +@@ -191,5 +223,6 @@ struct ehci_regs { + #define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ + #define USBMODE_EX_HC (3<<0) /* host controller mode */ + }; ++#endif + + #endif /* __LINUX_USB_EHCI_DEF_H */ +diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h +index e4516e9ded0f..ce4d900f1867 100644 +--- a/include/linux/usb/gadget.h ++++ b/include/linux/usb/gadget.h +@@ -94,7 +94,9 @@ struct usb_request { + void *buf; + unsigned length; + dma_addr_t dma; +- ++#ifdef CONFIG_USB_WEBCAM_UVC_SUPPORT_SG_TABLE ++ struct sg_table sgt; ++#endif + struct scatterlist *sg; + unsigned num_sgs; + unsigned num_mapped_sgs; +@@ -111,6 +113,8 @@ struct usb_request { + + int status; + unsigned actual; ++ ++ unsigned last_req:1; + }; + + /*-------------------------------------------------------------------------*/ +diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h +index 492034126876..481c6ef4d5fe 100644 +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -24,6 +24,9 @@ + #include + #include + #include ++#if (CONFIG_MP_USB_MSTAR==1) ++#define HOTPLUG //tony add for hotplug when read/write device ++#endif + + #define MAX_TOPO_LEVEL 6 + +@@ -52,6 +55,16 @@ + #define USB_PID_STALL 0x1e + #define USB_PID_MDATA 0x0f /* USB 2.0 */ + ++#if (CONFIG_MP_USB_MSTAR==1) ++//usb port power control ++struct usb_ppc { ++ uintptr_t port_addr; ++ u8 bit_addr; ++ u8 out_en_bit_addr; ++ u8 out_en_hi_active; ++ u8 reserved[1]; ++}; ++#endif + /*-------------------------------------------------------------------------*/ + + /* +@@ -70,6 +83,13 @@ struct giveback_urb_bh { + struct tasklet_struct bh; + struct usb_host_endpoint *completing_ep; + }; ++#if (CONFIG_MP_USB_MSTAR==1) ++struct comp_port { ++ uintptr_t comp_port_addr; ++ uintptr_t u3top_base; ++ u8 port_index; ++}; ++#endif + + struct usb_hcd { + +@@ -128,22 +148,10 @@ struct usb_hcd { + #define HCD_RH_RUNNING(hcd) ((hcd)->flags & (1U << HCD_FLAG_RH_RUNNING)) + #define HCD_DEAD(hcd) ((hcd)->flags & (1U << HCD_FLAG_DEAD)) + +- /* +- * Specifies if interfaces are authorized by default +- * or they require explicit user space authorization; this bit is +- * settable through /sys/class/usb_host/X/interface_authorized_default +- */ + #define HCD_INTF_AUTHORIZED(hcd) \ + ((hcd)->flags & (1U << HCD_FLAG_INTF_AUTHORIZED)) +- +- /* +- * Specifies if devices are authorized by default +- * or they require explicit user space authorization; this bit is +- * settable through /sys/class/usb_host/X/authorized_default +- */ + #define HCD_DEV_AUTHORIZED(hcd) \ + ((hcd)->flags & (1U << HCD_FLAG_DEV_AUTHORIZED)) +- + /* Flags that get set only during HCD registration or removal. */ + unsigned rh_registered:1;/* is root hub registered? */ + unsigned rh_pollable:1; /* may we poll the root hub? */ +@@ -203,6 +211,39 @@ struct usb_hcd { + + #define HC_IS_RUNNING(state) ((state) & __ACTIVE) + #define HC_IS_SUSPENDED(state) ((state) & __SUSPEND) ++#if (CONFIG_MP_USB_MSTAR==1) ++ // Refactoring --- 2011.10.27 --- ++ u32 port_index; ++ uintptr_t utmi_base; ++ uintptr_t ehc_base; ++ uintptr_t usbc_base; ++ uintptr_t bc_base; ++ ++ uintptr_t xhci_base; ++ uintptr_t u3top_base; ++ uintptr_t u3dphy_base[2]; ++ struct comp_port companion; ++ u32 ms_flag; ++ /* ms_flag */ ++#define MS_FLAG_P0_SSC 1<<0 ++#define MS_FLAG_P1_SSC 1<<1 ++#define MS_FLAG_SW_FRM_IDX 1<<2 ++ ++ int root_port_devnum; ++ u8 enum_port_flag; ++ u8 enum_dbreset_flag; ++ u8 rootflag; ++ ++ u8 startup_conn_flag; //120210, for port reset when connected at startup ++ u8 bc_enable_flag; ++ u8 bc_apple_enable_flag; ++ u8 reduce_wait_reset_time_flag; //190802, for some 3.0 device can't wait so long during bus reset ++ /* lock for usb reset */ ++ spinlock_t usb_reset_lock; ++ spinlock_t lock_usbreset; ++ ++ struct usb_ppc ppc; ++#endif + + /* more shared queuing code would be good; it should support + * smarter scheduling, handle transaction translators, etc; +diff --git a/include/linux/vm_event_item.h b/include/linux/vm_event_item.h +index 2edb150f1a4d..544cd50fbbd0 100644 +--- a/include/linux/vm_event_item.h ++++ b/include/linux/vm_event_item.h +@@ -97,7 +97,6 @@ enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT, + #ifdef CONFIG_DEBUG_VM_VMACACHE + VMACACHE_FIND_CALLS, + VMACACHE_FIND_HITS, +- VMACACHE_FULL_FLUSHES, + #endif + NR_VM_EVENT_ITEMS + }; +diff --git a/include/linux/vmacache.h b/include/linux/vmacache.h +index c3fa0fd43949..4f58ff2dacd6 100644 +--- a/include/linux/vmacache.h ++++ b/include/linux/vmacache.h +@@ -15,7 +15,6 @@ static inline void vmacache_flush(struct task_struct *tsk) + memset(tsk->vmacache, 0, sizeof(tsk->vmacache)); + } + +-extern void vmacache_flush_all(struct mm_struct *mm); + extern void vmacache_update(unsigned long addr, struct vm_area_struct *newvma); + extern struct vm_area_struct *vmacache_find(struct mm_struct *mm, + unsigned long addr); +@@ -29,10 +28,6 @@ extern struct vm_area_struct *vmacache_find_exact(struct mm_struct *mm, + static inline void vmacache_invalidate(struct mm_struct *mm) + { + mm->vmacache_seqnum++; +- +- /* deal with overflows */ +- if (unlikely(mm->vmacache_seqnum == 0)) +- vmacache_flush_all(mm); + } + + #endif /* __LINUX_VMACACHE_H */ +diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h +old mode 100644 +new mode 100755 +index 3d9d786a943c..6030018620e4 +--- a/include/linux/vmalloc.h ++++ b/include/linux/vmalloc.h +@@ -123,6 +123,12 @@ extern struct vm_struct *find_vm_area(const void *addr); + + extern int map_vm_area(struct vm_struct *area, pgprot_t prot, + struct page **pages); ++ ++#ifdef CONFIG_MSTAR_MMAHEAP ++int vmap_page_range(unsigned long start, unsigned long end, ++ pgprot_t prot, struct page **pages); ++#endif ++ + #ifdef CONFIG_MMU + extern int map_kernel_range_noflush(unsigned long start, unsigned long size, + pgprot_t prot, struct page **pages); +diff --git a/include/net/inet_frag.h b/include/net/inet_frag.h +index 634d19203e7d..b7c06062f0c3 100644 +--- a/include/net/inet_frag.h ++++ b/include/net/inet_frag.h +@@ -1,14 +1,19 @@ + #ifndef __NET_FRAG_H__ + #define __NET_FRAG_H__ + ++#include ++ + struct netns_frags { ++ struct rhashtable rhashtable ____cacheline_aligned_in_smp; ++ + /* Keep atomic mem on separate cachelines in structs that include it */ +- atomic_t mem ____cacheline_aligned_in_smp; ++ atomic_long_t mem ____cacheline_aligned_in_smp; + /* sysctls */ ++ long high_thresh; ++ long low_thresh; + int timeout; +- int high_thresh; +- int low_thresh; + int max_dist; ++ struct inet_frags *f; + }; + + /** +@@ -24,12 +29,30 @@ enum { + INET_FRAG_COMPLETE = BIT(2), + }; + ++struct frag_v4_compare_key { ++ __be32 saddr; ++ __be32 daddr; ++ u32 user; ++ u32 vif; ++ __be16 id; ++ u16 protocol; ++}; ++ ++struct frag_v6_compare_key { ++ struct in6_addr saddr; ++ struct in6_addr daddr; ++ u32 user; ++ __be32 id; ++ u32 iif; ++}; ++ + /** + * struct inet_frag_queue - fragment queue + * +- * @lock: spinlock protecting the queue ++ * @node: rhash node ++ * @key: keys identifying this frag. + * @timer: queue expiration timer +- * @list: hash bucket list ++ * @lock: spinlock protecting this frag + * @refcnt: reference count of the queue + * @fragments: received fragments head + * @fragments_tail: received fragments tail +@@ -39,115 +62,78 @@ enum { + * @flags: fragment queue flags + * @max_size: maximum received fragment size + * @net: namespace that this frag belongs to +- * @list_evictor: list of queues to forcefully evict (e.g. due to low memory) ++ * @rcu: rcu head for freeing deferall + */ + struct inet_frag_queue { +- spinlock_t lock; ++ struct rhash_head node; ++ union { ++ struct frag_v4_compare_key v4; ++ struct frag_v6_compare_key v6; ++ } key; + struct timer_list timer; +- struct hlist_node list; ++ spinlock_t lock; + atomic_t refcnt; +- struct sk_buff *fragments; ++ struct sk_buff *fragments; /* Used in IPv6. */ ++ struct rb_root rb_fragments; /* Used in IPv4. */ + struct sk_buff *fragments_tail; + ktime_t stamp; + int len; + int meat; + __u8 flags; + u16 max_size; +- struct netns_frags *net; +- struct hlist_node list_evictor; +-}; +- +-#define INETFRAGS_HASHSZ 1024 +- +-/* averaged: +- * max_depth = default ipfrag_high_thresh / INETFRAGS_HASHSZ / +- * rounded up (SKB_TRUELEN(0) + sizeof(struct ipq or +- * struct frag_queue)) +- */ +-#define INETFRAGS_MAXDEPTH 128 +- +-struct inet_frag_bucket { +- struct hlist_head chain; +- spinlock_t chain_lock; ++ struct netns_frags *net; ++ struct rcu_head rcu; + }; + + struct inet_frags { +- struct inet_frag_bucket hash[INETFRAGS_HASHSZ]; +- +- struct work_struct frags_work; +- unsigned int next_bucket; +- unsigned long last_rebuild_jiffies; +- bool rebuild; +- +- /* The first call to hashfn is responsible to initialize +- * rnd. This is best done with net_get_random_once. +- * +- * rnd_seqlock is used to let hash insertion detect +- * when it needs to re-lookup the hash chain to use. +- */ +- u32 rnd; +- seqlock_t rnd_seqlock; + int qsize; + +- unsigned int (*hashfn)(const struct inet_frag_queue *); +- bool (*match)(const struct inet_frag_queue *q, +- const void *arg); + void (*constructor)(struct inet_frag_queue *q, + const void *arg); + void (*destructor)(struct inet_frag_queue *); + void (*frag_expire)(unsigned long data); + struct kmem_cache *frags_cachep; + const char *frags_cache_name; ++ struct rhashtable_params rhash_params; + }; + + int inet_frags_init(struct inet_frags *); + void inet_frags_fini(struct inet_frags *); + +-static inline void inet_frags_init_net(struct netns_frags *nf) ++static inline int inet_frags_init_net(struct netns_frags *nf) + { +- atomic_set(&nf->mem, 0); ++ atomic_long_set(&nf->mem, 0); ++ return rhashtable_init(&nf->rhashtable, &nf->f->rhash_params); + } +-void inet_frags_exit_net(struct netns_frags *nf, struct inet_frags *f); +- +-void inet_frag_kill(struct inet_frag_queue *q, struct inet_frags *f); +-void inet_frag_destroy(struct inet_frag_queue *q, struct inet_frags *f); +-struct inet_frag_queue *inet_frag_find(struct netns_frags *nf, +- struct inet_frags *f, void *key, unsigned int hash); ++void inet_frags_exit_net(struct netns_frags *nf); + ++void inet_frag_kill(struct inet_frag_queue *q); ++void inet_frag_destroy(struct inet_frag_queue *q); ++struct inet_frag_queue *inet_frag_find(struct netns_frags *nf, void *key); + void inet_frag_maybe_warn_overflow(struct inet_frag_queue *q, + const char *prefix); + +-static inline void inet_frag_put(struct inet_frag_queue *q, struct inet_frags *f) ++static inline void inet_frag_put(struct inet_frag_queue *q) + { + if (atomic_dec_and_test(&q->refcnt)) +- inet_frag_destroy(q, f); +-} +- +-static inline bool inet_frag_evicting(struct inet_frag_queue *q) +-{ +- return !hlist_unhashed(&q->list_evictor); ++ inet_frag_destroy(q); + } + + /* Memory Tracking Functions. */ + +-static inline int frag_mem_limit(struct netns_frags *nf) +-{ +- return atomic_read(&nf->mem); +-} +- +-static inline void sub_frag_mem_limit(struct netns_frags *nf, int i) ++static inline long frag_mem_limit(const struct netns_frags *nf) + { +- atomic_sub(i, &nf->mem); ++ return atomic_long_read(&nf->mem); + } + +-static inline void add_frag_mem_limit(struct netns_frags *nf, int i) ++static inline void sub_frag_mem_limit(struct netns_frags *nf, long val) + { +- atomic_add(i, &nf->mem); ++ atomic_long_sub(val, &nf->mem); + } + +-static inline int sum_frag_mem_limit(struct netns_frags *nf) ++static inline void add_frag_mem_limit(struct netns_frags *nf, long val) + { +- return atomic_read(&nf->mem); ++ atomic_long_add(val, &nf->mem); + } + + /* RFC 3168 support : +diff --git a/include/net/ip.h b/include/net/ip.h +index 0e3dcd5a134d..8f5bdc7615b7 100644 +--- a/include/net/ip.h ++++ b/include/net/ip.h +@@ -541,7 +541,6 @@ static inline struct sk_buff *ip_check_defrag(struct net *net, struct sk_buff *s + return skb; + } + #endif +-int ip_frag_mem(struct net *net); + + /* + * Functions provided by ip_forward.c +diff --git a/include/net/ipv6.h b/include/net/ipv6.h +index e64210c98c2b..951ea5944c7f 100644 +--- a/include/net/ipv6.h ++++ b/include/net/ipv6.h +@@ -337,13 +337,6 @@ static inline bool ipv6_accept_ra(struct inet6_dev *idev) + idev->cnf.accept_ra; + } + +-#if IS_ENABLED(CONFIG_IPV6) +-static inline int ip6_frag_mem(struct net *net) +-{ +- return sum_frag_mem_limit(&net->ipv6.frags); +-} +-#endif +- + #define IPV6_FRAG_HIGH_THRESH (4 * 1024*1024) /* 4194304 */ + #define IPV6_FRAG_LOW_THRESH (3 * 1024*1024) /* 3145728 */ + #define IPV6_FRAG_TIMEOUT (60 * HZ) /* 60 seconds */ +@@ -537,17 +530,8 @@ enum ip6_defrag_users { + __IP6_DEFRAG_CONNTRACK_BRIDGE_IN = IP6_DEFRAG_CONNTRACK_BRIDGE_IN + USHRT_MAX, + }; + +-struct ip6_create_arg { +- __be32 id; +- u32 user; +- const struct in6_addr *src; +- const struct in6_addr *dst; +- int iif; +- u8 ecn; +-}; +- + void ip6_frag_init(struct inet_frag_queue *q, const void *a); +-bool ip6_frag_match(const struct inet_frag_queue *q, const void *a); ++extern const struct rhashtable_params ip6_rhash_params; + + /* + * Equivalent of ipv4 struct ip +@@ -555,19 +539,13 @@ bool ip6_frag_match(const struct inet_frag_queue *q, const void *a); + struct frag_queue { + struct inet_frag_queue q; + +- __be32 id; /* fragment id */ +- u32 user; +- struct in6_addr saddr; +- struct in6_addr daddr; +- + int iif; + unsigned int csum; + __u16 nhoffset; + u8 ecn; + }; + +-void ip6_expire_frag_queue(struct net *net, struct frag_queue *fq, +- struct inet_frags *frags); ++void ip6_expire_frag_queue(struct net *net, struct frag_queue *fq); + + static inline bool ipv6_addr_any(const struct in6_addr *a) + { +diff --git a/include/net/sock.h b/include/net/sock.h +old mode 100644 +new mode 100755 +index 6d42ed883bf9..f6a1f3d19ded +--- a/include/net/sock.h ++++ b/include/net/sock.h +@@ -40,6 +40,16 @@ + #ifndef _SOCK_H + #define _SOCK_H + ++// turn on/off TOE ++#ifdef CONFIG_SS_SWTOE ++#define CONFIG_SS_SWTOE_TCP ++#endif ++ ++#ifdef CONFIG_SS_SWTOE_TCP ++#define CONFIG_SS_SWTOE_TCP_SERVER ++#define CONFIG_SS_SWTOE_TCP_CLIENT ++#endif ++ + #include + #include + #include +@@ -448,6 +458,13 @@ struct sock { + void (*sk_destruct)(struct sock *sk); + struct sock_reuseport __rcu *sk_reuseport_cb; + struct rcu_head sk_rcu; ++ ++#ifdef CONFIG_SS_SWTOE_TCP ++ u16 ss_swtoe : 1; ++ u16 ss_swtoe_cnx : 11; ++ u16 ss_swtoe_blk : 1; ++ u16 reserved : 3; ++#endif + }; + + #define __sk_user_data(sk) ((*((void __rcu **)&(sk)->sk_user_data))) +diff --git a/include/net/tcp.h b/include/net/tcp.h +index caf35e062639..4c9477df0ddd 100644 +--- a/include/net/tcp.h ++++ b/include/net/tcp.h +@@ -53,6 +53,8 @@ void tcp_time_wait(struct sock *sk, int state, int timeo); + + #define MAX_TCP_HEADER (128 + MAX_HEADER) + #define MAX_TCP_OPTION_SPACE 40 ++#define TCP_MIN_SND_MSS 48 ++#define TCP_MIN_GSO_SIZE (TCP_MIN_SND_MSS - MAX_TCP_OPTION_SPACE) + + /* + * Never offer a window over 32767 without using window scaling. Some +diff --git a/include/uapi/asm-generic/socket.h b/include/uapi/asm-generic/socket.h +old mode 100644 +new mode 100755 +index 67d632f1743d..3c9f96062078 +--- a/include/uapi/asm-generic/socket.h ++++ b/include/uapi/asm-generic/socket.h +@@ -92,4 +92,8 @@ + + #define SO_CNX_ADVICE 53 + ++#ifdef CONFIG_SS_SWTOE_TCP ++#define SO_SS_SWTOE 54 ++#endif ++ + #endif /* __ASM_GENERIC_SOCKET_H */ +diff --git a/include/uapi/linux/snmp.h b/include/uapi/linux/snmp.h +index e7a31f830690..3442a26d36d9 100644 +--- a/include/uapi/linux/snmp.h ++++ b/include/uapi/linux/snmp.h +@@ -55,6 +55,7 @@ enum + IPSTATS_MIB_ECT1PKTS, /* InECT1Pkts */ + IPSTATS_MIB_ECT0PKTS, /* InECT0Pkts */ + IPSTATS_MIB_CEPKTS, /* InCEPkts */ ++ IPSTATS_MIB_REASM_OVERLAPS, /* ReasmOverlaps */ + __IPSTATS_MIB_MAX + }; + +diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h +old mode 100644 +new mode 100755 +index 69ab695fad2e..812feffafa92 +--- a/include/uapi/linux/usb/video.h ++++ b/include/uapi/linux/usb/video.h +@@ -29,6 +29,7 @@ + /* A.3. Video Interface Protocol Codes */ + #define UVC_PC_PROTOCOL_UNDEFINED 0x00 + #define UVC_PC_PROTOCOL_15 0x01 ++#define USB_VIDEO_CLASS_VERSION 0x100 + + /* A.5. Video Class-Specific VC Interface Descriptor Subtypes */ + #define UVC_VC_DESCRIPTOR_UNDEFINED 0x00 +@@ -54,6 +55,10 @@ + #define UVC_VS_FORMAT_FRAME_BASED 0x10 + #define UVC_VS_FRAME_FRAME_BASED 0x11 + #define UVC_VS_FORMAT_STREAM_BASED 0x12 ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++#define UVC_VS_FORMAT_H264 0x13 ++#define UVC_VS_FRAME_H264 0x14 ++#endif + + /* A.7. Video Class-Specific Endpoint Descriptor Subtypes */ + #define UVC_EP_UNDEFINED 0x00 +@@ -291,6 +296,20 @@ struct UVC_SELECTOR_UNIT_DESCRIPTOR(n) { \ + } __attribute__ ((packed)) + + /* 3.7.2.5. Processing Unit Descriptor */ ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++struct uvc_processing_unit_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bUnitID; ++ __u8 bSourceID; ++ __u16 wMaxMultiplier; ++ __u8 bControlSize; ++ __u8 bmControls[3]; ++ __u8 iProcessing; ++ __u8 bmVideoStandards; ++} __attribute__((__packed__)); ++#else + struct uvc_processing_unit_descriptor { + __u8 bLength; + __u8 bDescriptorType; +@@ -302,8 +321,13 @@ struct uvc_processing_unit_descriptor { + __u8 bmControls[2]; + __u8 iProcessing; + } __attribute__((__packed__)); ++#endif + ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++#define UVC_DT_PROCESSING_UNIT_SIZE(n) (10+(n)) ++#else + #define UVC_DT_PROCESSING_UNIT_SIZE(n) (9+(n)) ++#endif + + /* 3.7.2.6. Extension Unit Descriptor */ + struct uvc_extension_unit_descriptor { +@@ -565,5 +589,149 @@ struct UVC_FRAME_MJPEG(n) { \ + __u32 dwFrameInterval[n]; \ + } __attribute__ ((packed)) + +-#endif /* __LINUX_USB_VIDEO_H */ ++#if (USB_VIDEO_CLASS_VERSION==0x150) ++/* H264 Payload - 3.1.1. H264 Video Format Descriptor */ ++struct uvc_format_h264 { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bFormatIndex; ++ __u8 bNumFrameDescriptors; ++ __u8 bDefaultFrameIndex; ++ __u8 bMaxCodecConfigDelay; ++ __u8 bmSupportedSliceModes; ++ __u8 bmSupportedSyncFrameTypes; ++ __u8 bResolutionScaling; ++ __u8 Reserved1; ++ __u8 bmSupportedRateControlModes; ++ __u16 wMaxMBperSecOneResNoScalability; ++ __u16 wMaxMBperSecTwoResNoScalability; ++ __u16 wMaxMBperSecThreeResNoScalability; ++ __u16 wMaxMBperSecFourResNoScalability; ++ __u16 wMaxMBperSecOneResTemporalScalability; ++ __u16 wMaxMBperSecTwoResTemporalScalability; ++ __u16 wMaxMBperSecThreeResTemporalScalability; ++ __u16 wMaxMBperSecFourResTemporalScalability; ++ __u16 wMaxMBperSecOneResTemporalQualityScalability; ++ __u16 wMaxMBperSecTwoResTemporalQualityScalability; ++ __u16 wMaxMBperSecThreeResTemporalQualityScalability; ++ __u16 wMaxMBperSecFourResTemporalQualityScalability; ++ __u16 wMaxMBperSecOneResTemporalSpatialScalability; ++ __u16 wMaxMBperSecTwoResTemporalSpatialScalability; ++ __u16 wMaxMBperSecThreeResTemporalSpatialScalability; ++ __u16 wMaxMBperSecFourResTemporalSpatialScalability; ++ __u16 wMaxMBperSecOneResFullScalability; ++ __u16 wMaxMBperSecTwoResFullScalability; ++ __u16 wMaxMBperSecThreeResFullScalability; ++ __u16 wMaxMBperSecFourResFullScalability; ++} __attribute__((__packed__)); + ++#define UVC_DT_FORMAT_H264_SIZE 52 ++ ++/* H264 Payload - 3.1.2. H264 Video Frame Descriptor */ ++struct uvc_frame_h264 { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bFrameIndex; ++ __u16 wWidth; ++ __u16 wHeight; ++ __u16 wSARwidth; ++ __u16 wSARheight; ++ __u16 wProfile; ++ __u8 bLevelIDC; ++ __u16 wConstrainedToolset; ++ __u32 bmSupportedUsages; ++ __u16 bmCapabilities; ++ __u32 bmSVCCapabilities; ++ __u32 bmMVCCapabilities; ++ __u32 dwMinBitRate; ++ __u32 dwMaxBitRate; ++ __u32 dwDefaultFrameInterval; ++ __u8 bNumFrameIntervals; ++ __u32 dwFrameInterval[]; ++} __attribute__((__packed__)); ++ ++#define UVC_DT_FRAME_H264_SIZE(n) (44+4*(n)) ++ ++#define UVC_FRAME_H264(n) \ ++ uvc_frame_h264_##n ++ ++#define DECLARE_UVC_FRAME_H264(n) \ ++struct UVC_FRAME_H264(n) { \ ++ __u8 bLength; \ ++ __u8 bDescriptorType; \ ++ __u8 bDescriptorSubType; \ ++ __u8 bFrameIndex; \ ++ __u16 wWidth; \ ++ __u16 wHeight; \ ++ __u16 wSARwidth; \ ++ __u16 wSARheight; \ ++ __u16 wProfile; \ ++ __u8 bLevelIDC; \ ++ __u16 wConstrainedToolset; \ ++ __u32 bmSupportedUsages; \ ++ __u16 bmCapabilities; \ ++ __u32 bmSVCCapabilities; \ ++ __u32 bmMVCCapabilities; \ ++ __u32 dwMinBitRate; \ ++ __u32 dwMaxBitRate; \ ++ __u32 dwDefaultFrameInterval; \ ++ __u8 bNumFrameIntervals; \ ++ __u32 dwFrameInterval[n]; \ ++} __attribute__ ((packed)) ++#endif ++ ++struct uvc_format_framebase{ ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bFormatIndex; ++ __u8 bNumFrameDescriptors; ++ __u8 guidFormat[16]; ++ __u8 bBitsPerPixel; ++ __u8 bDefaultFrameIndex; ++ __u8 bAspectRatioX; ++ __u8 bAspectRatioY; ++ __u8 bmInterfaceFlags; ++ __u8 bCopyProtect; ++ __u8 bVariableSize; ++} __attribute__((__packed__)); ++#define UVC_DT_FORMAT_FRAMEBASE_SIZE 28 ++struct uvc_frame_framebase { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bFrameIndex; ++ __u8 bmCapabilities; ++ __u16 wWidth; ++ __u16 wHeight; ++ __u32 dwMinBitRate; ++ __u32 dwMaxBitRate; ++ __u32 dwDefaultFrameInterval; ++ __u8 bFrameIntervalType; ++ __u32 dwBytesPerLine; ++ __u32 dwFrameInterval[]; ++} __attribute__((__packed__)); ++ ++#define UVC_DT_FRAME_FRAMEBASE_SIZE(n) (26+4*(n)) ++ ++#define UVC_FRAME_FRAMEBASE(n) \ ++ uvc_frame_framebase_##n ++#define DECLARE_UVC_FRAME_FRAMEBASE(n) \ ++struct UVC_FRAME_FRAMEBASE(n) { \ ++ __u8 bLength; \ ++ __u8 bDescriptorType; \ ++ __u8 bDescriptorSubType; \ ++ __u8 bFrameIndex; \ ++ __u8 bmCapabilities; \ ++ __u16 wWidth; \ ++ __u16 wHeight; \ ++ __u32 dwMinBitRate; \ ++ __u32 dwMaxBitRate; \ ++ __u32 dwDefaultFrameInterval; \ ++ __u8 bFrameIntervalType; \ ++ __u32 dwBytesPerLine; \ ++ __u32 dwFrameInterval[n]; \ ++} __attribute__ ((packed)) ++#endif /* __LINUX_USB_VIDEO_H */ +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +old mode 100644 +new mode 100755 +index 7f34d3c67648..c65a6d70c553 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -591,6 +591,7 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ + #define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ + #define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */ ++#define V4L2_PIX_FMT_H265 v4l2_fourcc('H', '2', '6', '5') /* H265 with start codes */ + #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ + #define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ + #define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ +diff --git a/init/initramfs.c b/init/initramfs.c +old mode 100644 +new mode 100755 +index 981f286c1d16..07ed1d85ca0d +--- a/init/initramfs.c ++++ b/init/initramfs.c +@@ -645,7 +645,7 @@ static int __init populate_rootfs(void) + err = unpack_to_rootfs((char *)initrd_start, + initrd_end - initrd_start); + if (err) +- printk(KERN_EMERG "Initramfs unpacking failed: %s\n", err); ++ printk(KERN_ERR "Initramfs unpacking failed: %s\n", err); + free_initrd(); + #endif + flush_delayed_fput(); +diff --git a/init/main.c b/init/main.c +old mode 100644 +new mode 100755 +index 99f026565608..fda1470cb9a2 +--- a/init/main.c ++++ b/init/main.c +@@ -10,6 +10,12 @@ + */ + + #define DEBUG /* Enable initcall_debug */ ++#ifdef CONFIG_SS_PROFILING_TIME ++extern void recode_timestamp(int mark, const char* name); ++extern void recode_show(void); ++extern unsigned int read_timestamp(void); ++extern void recode_timestamp_ext(int mark, const char* name, unsigned int timestamp); ++#endif + + #include + #include +@@ -481,7 +487,9 @@ asmlinkage __visible void __init start_kernel(void) + { + char *command_line; + char *after_dashes; +- ++#ifdef CONFIG_SS_PROFILING_TIME ++ unsigned int t1 = read_timestamp(); ++#endif + set_task_stack_end_magic(&init_task); + smp_setup_processor_id(); + debug_objects_early_init(); +@@ -504,6 +512,10 @@ asmlinkage __visible void __init start_kernel(void) + page_address_init(); + pr_notice("%s", linux_banner); + setup_arch(&command_line); ++#ifdef CONFIG_SS_PROFILING_TIME ++ recode_timestamp_ext(0, "start_kernel+", t1); ++ recode_timestamp(__LINE__, "setup_arch-"); ++#endif + mm_init_cpumask(&init_mm); + setup_command_line(command_line); + setup_nr_cpu_ids(); +@@ -848,7 +860,9 @@ static void __init do_initcall_level(int level) + static void __init do_initcalls(void) + { + int level; +- ++#ifdef CONFIG_SS_PROFILING_TIME ++ recode_timestamp(__LINE__, "do_initcalls+"); ++#endif + for (level = 0; level < ARRAY_SIZE(initcall_levels) - 1; level++) + do_initcall_level(level); + } +@@ -862,6 +876,9 @@ static void __init do_initcalls(void) + */ + static void __init do_basic_setup(void) + { ++#ifdef CONFIG_SS_PROFILING_TIME ++ recode_timestamp(__LINE__, "do_basic_setup+"); ++#endif + cpuset_init_smp(); + shmem_init(); + driver_init(); +@@ -869,6 +886,9 @@ static void __init do_basic_setup(void) + do_ctors(); + usermodehelper_enable(); + do_initcalls(); ++#ifdef CONFIG_SS_PROFILING_TIME ++ recode_timestamp(__LINE__, "do_basic_setup-"); ++#endif + } + + static void __init do_pre_smp_initcalls(void) +@@ -939,17 +959,23 @@ static inline void mark_readonly(void) + static int __ref kernel_init(void *unused) + { + int ret; +- ++#ifdef CONFIG_SS_PROFILING_TIME ++ recode_timestamp(__LINE__, "kernel_init+"); ++#endif + kernel_init_freeable(); + /* need to finish all async __init code before freeing the memory */ + async_synchronize_full(); ++#ifndef CONFIG_DEFERRED_INIICALLS + free_initmem(); ++#endif + mark_readonly(); + system_state = SYSTEM_RUNNING; + numa_default_policy(); + + rcu_end_inkernel_boot(); +- ++#ifdef CONFIG_SS_PROFILING_TIME ++ recode_timestamp(__LINE__, "ramdisk_execute_command+"); ++#endif + if (ramdisk_execute_command) { + ret = run_init_process(ramdisk_execute_command); + if (!ret) +@@ -1045,3 +1071,33 @@ static noinline void __init kernel_init_freeable(void) + integrity_load_keys(); + load_default_modules(); + } ++ ++#ifdef CONFIG_DEFERRED_INIICALLS ++extern initcall_t __deferred_initcall_start[], __deferred_initcall_end[]; ++/* call deferred init routines */ ++void do_deferred_initcalls(void) ++{ ++ initcall_t *call; ++ static int already_run=0; ++ ++ if (already_run) { ++ printk("do_deferred_initcalls() has already run\n"); ++ return; ++ } ++ ++ already_run=1; ++ ++ printk("Running do_deferred_initcalls()\n"); ++ ++// lock_kernel(); /* make environment similar to early boot */ ++ ++ for(call = __deferred_initcall_start; ++ call < __deferred_initcall_end; call++) ++ do_one_initcall(*call); ++ ++ flush_scheduled_work(); ++ ++ free_initmem(); ++// unlock_kernel(); ++} ++#endif +diff --git a/kernel/events/core.c b/kernel/events/core.c +old mode 100644 +new mode 100755 +index 13b9784427b0..01360a4234ca +--- a/kernel/events/core.c ++++ b/kernel/events/core.c +@@ -6218,7 +6218,7 @@ static void perf_event_addr_filters_exec(struct perf_event *event, void *data) + + raw_spin_lock_irqsave(&ifh->lock, flags); + list_for_each_entry(filter, &ifh->list, entry) { +- if (filter->inode) { ++ if (filter->path.dentry) { + event->addr_filters_offs[count] = 0; + restart++; + } +@@ -6752,7 +6752,11 @@ static bool perf_addr_filter_match(struct perf_addr_filter *filter, + struct file *file, unsigned long offset, + unsigned long size) + { +- if (filter->inode != file->f_inode) ++ /* d_inode(NULL) won't be equal to any mapped user-space file */ ++ if (!filter->path.dentry) ++ return false; ++ ++ if (d_inode(filter->path.dentry) != file_inode(file)) + return false; + + if (filter->offset > offset + size) +@@ -7964,8 +7968,7 @@ static void free_filters_list(struct list_head *filters) + struct perf_addr_filter *filter, *iter; + + list_for_each_entry_safe(filter, iter, filters, entry) { +- if (filter->inode) +- iput(filter->inode); ++ path_put(&filter->path); + list_del(&filter->entry); + kfree(filter); + } +@@ -8059,7 +8062,7 @@ static void perf_event_addr_filters_apply(struct perf_event *event) + * Adjust base offset if the filter is associated to a binary + * that needs to be mapped: + */ +- if (filter->inode) ++ if (filter->path.dentry) + event->addr_filters_offs[count] = + perf_addr_filter_apply(filter, mm); + +@@ -8132,7 +8135,6 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, + { + struct perf_addr_filter *filter = NULL; + char *start, *orig, *filename = NULL; +- struct path path; + substring_t args[MAX_OPT_ARGS]; + int state = IF_STATE_ACTION, token; + unsigned int kernel = 0; +@@ -8195,6 +8197,7 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, + if (token == IF_SRC_FILE || token == IF_SRC_FILEADDR) { + int fpos = filter->range ? 2 : 1; + ++ kfree(filename); + filename = match_strdup(&args[fpos]); + if (!filename) { + ret = -ENOMEM; +@@ -8223,19 +8226,15 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, + goto fail; + + /* look up the path and grab its inode */ +- ret = kern_path(filename, LOOKUP_FOLLOW, &path); ++ ret = kern_path(filename, LOOKUP_FOLLOW, ++ &filter->path); + if (ret) +- goto fail_free_name; +- +- filter->inode = igrab(d_inode(path.dentry)); +- path_put(&path); +- kfree(filename); +- filename = NULL; ++ goto fail; + + ret = -EINVAL; +- if (!filter->inode || +- !S_ISREG(filter->inode->i_mode)) +- /* free_filters_list() will iput() */ ++ if (!filter->path.dentry || ++ !S_ISREG(d_inode(filter->path.dentry) ++ ->i_mode)) + goto fail; + } + +@@ -8248,13 +8247,13 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, + if (state != IF_STATE_ACTION) + goto fail; + ++ kfree(filename); + kfree(orig); + + return 0; + +-fail_free_name: +- kfree(filename); + fail: ++ kfree(filename); + free_filters_list(filters); + kfree(orig); + +@@ -10872,7 +10871,11 @@ unlock: + + return ret; + } ++#ifdef CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS ++deferred_module_init(perf_event_sysfs_init); ++#else + device_initcall(perf_event_sysfs_init); ++#endif + + #ifdef CONFIG_CGROUP_PERF + static struct cgroup_subsys_state * +diff --git a/kernel/fork.c b/kernel/fork.c +index 70e10cb49be0..ae728a3b693b 100644 +--- a/kernel/fork.c ++++ b/kernel/fork.c +@@ -386,7 +386,7 @@ void __put_task_struct(struct task_struct *tsk) + WARN_ON(tsk == current); + + cgroup_free(tsk); +- task_numa_free(tsk); ++ task_numa_free(tsk, true); + security_task_free(tsk); + exit_creds(tsk); + delayacct_tsk_free(tsk); +diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c +old mode 100644 +new mode 100755 +index d3f24905852c..acfd0945da69 +--- a/kernel/irq/handle.c ++++ b/kernel/irq/handle.c +@@ -18,6 +18,10 @@ + + #include + ++#if defined(CONFIG_MP_IRQ_TRACE) ++#include "../../drivers/sstar/include/ms_msys.h" ++#endif ++ + #include "internals.h" + + /** +@@ -137,12 +141,26 @@ irqreturn_t __handle_irq_event_percpu(struct irq_desc *desc, unsigned int *flags + irqreturn_t retval = IRQ_NONE; + unsigned int irq = desc->irq_data.irq; + struct irqaction *action; +- ++#if defined(CONFIG_MP_IRQ_TRACE) ++ MSYS_IRQ_INFO irq_info; ++#endif + for_each_action_of_desc(desc, action) { + irqreturn_t res; + + trace_irq_handler_entry(irq, action); ++#if defined(CONFIG_MP_IRQ_TRACE) ++ if(irq > 32) ++ { ++ irq_info.IRQNumber = irq; ++ irq_info.timeStart = sched_clock(); ++ } ++#endif + res = action->handler(irq, action->dev_id); ++ ++#if defined(CONFIG_MP_IRQ_TRACE) ++ if(irq > 32) ++ irq_info.timeEnd = sched_clock(); ++#endif + trace_irq_handler_exit(irq, action, res); + + if (WARN_ONCE(!irqs_disabled(),"irq %u handler %pF enabled interrupts\n", +@@ -173,7 +191,16 @@ irqreturn_t __handle_irq_event_percpu(struct irq_desc *desc, unsigned int *flags + + retval |= res; + } +- ++#if defined(CONFIG_MP_IRQ_TRACE) ++ if(irq > 32) ++ { ++ if (irq_info.timeEnd - irq_info.timeStart > 1000000) ++ { ++ ms_records_irq(&irq_info); ++ ms_record_large_latency_in_top(&irq_info); ++ } ++ } ++#endif + return retval; + } + +diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c +old mode 100644 +new mode 100755 +index 77977f55dff7..379859127fce +--- a/kernel/irq/irqdesc.c ++++ b/kernel/irq/irqdesc.c +@@ -287,7 +287,12 @@ static int __init irq_sysfs_init(void) + + return 0; + } ++ ++#ifdef DEFERRED_INIICALLS_MORE_SYSFS ++deferred_module_init(irq_sysfs_init); ++#else + postcore_initcall(irq_sysfs_init); ++#endif + + #else /* !CONFIG_SYSFS */ + +diff --git a/kernel/params.c b/kernel/params.c +old mode 100644 +new mode 100755 +index a6d6149c0fe6..aef201bb97cf +--- a/kernel/params.c ++++ b/kernel/params.c +@@ -1006,10 +1006,22 @@ static int __init param_sysfs_init(void) + module_sysfs_initialized = 1; + + version_sysfs_builtin(); ++#ifndef CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS + param_sysfs_builtin(); ++#endif + + return 0; + } + subsys_initcall(param_sysfs_init); + ++#ifdef CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS ++static int __init do_param_sysfs_builtin(void) ++{ ++ param_sysfs_builtin(); ++ return 0; ++} ++deferred_module_init(do_param_sysfs_builtin); ++#endif ++ ++ + #endif /* CONFIG_SYSFS */ +diff --git a/kernel/power/Makefile b/kernel/power/Makefile +old mode 100644 +new mode 100755 +index eb4f717705ba..d791374e54b6 +--- a/kernel/power/Makefile ++++ b/kernel/power/Makefile +@@ -3,7 +3,7 @@ ccflags-$(CONFIG_PM_DEBUG) := -DDEBUG + + KASAN_SANITIZE_snapshot.o := n + +-obj-y += qos.o ++obj-$(CONFIG_PM) += qos.o + obj-$(CONFIG_PM) += main.o + obj-$(CONFIG_VT_CONSOLE_SLEEP) += console.o + obj-$(CONFIG_FREEZER) += process.o +diff --git a/kernel/power/main.c b/kernel/power/main.c +old mode 100644 +new mode 100755 +index 281a697fd458..0c8adc351a68 +--- a/kernel/power/main.c ++++ b/kernel/power/main.c +@@ -593,6 +593,16 @@ power_attr(pm_freeze_timeout); + + #endif /* CONFIG_FREEZER*/ + ++#ifdef CONFIG_MS_XPM ++extern ssize_t xpm_show(struct kobject *kobj,struct kobj_attribute *attr, char *buf); ++extern ssize_t xpm_store(struct kobject *kobj, struct kobj_attribute *attr,const char *buf, size_t n); ++extern ssize_t xpm_suspend_wait_ms_show(struct kobject *kobj,struct kobj_attribute *attr, char *buf); ++extern ssize_t xpm_suspend_wait_ms_store(struct kobject *kobj, struct kobj_attribute *attr,const char *buf, size_t n); ++ ++power_attr(xpm); ++power_attr(xpm_suspend_wait_ms); ++#endif ++ + static struct attribute * g[] = { + &state_attr.attr, + #ifdef CONFIG_PM_TRACE +@@ -619,6 +629,10 @@ static struct attribute * g[] = { + #endif + #ifdef CONFIG_FREEZER + &pm_freeze_timeout_attr.attr, ++#endif ++#ifdef CONFIG_MS_XPM ++ &xpm_attr.attr, ++ &xpm_suspend_wait_ms_attr.attr, + #endif + NULL, + }; +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +old mode 100644 +new mode 100755 +index 6ccb08f57fcb..e70d1233784a +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -32,9 +32,32 @@ + + #include "power.h" + ++ + const char *pm_labels[] = { "mem", "standby", "freeze", NULL }; + const char *pm_states[PM_SUSPEND_MAX]; + ++#ifdef CONFIG_SS_PROFILING_TIME ++extern void recode_timestamp_init(void); ++extern void recode_timestamp(int mark, const char* name); ++#endif ++ ++#ifdef CONFIG_MP_USB_STR_PATCH ++typedef enum ++{ ++ E_STR_NONE, ++ E_STR_IN_SUSPEND, ++ E_STR_IN_RESUME ++}EN_STR_STATUS; ++ ++static EN_STR_STATUS enStrStatus=E_STR_NONE; ++ ++bool is_suspending(void) ++{ ++ return (enStrStatus == E_STR_IN_SUSPEND); ++} ++EXPORT_SYMBOL_GPL(is_suspending); ++#endif ++ + unsigned int pm_suspend_global_flags; + EXPORT_SYMBOL_GPL(pm_suspend_global_flags); + +@@ -382,27 +405,40 @@ static int suspend_enter(suspend_state_t state, bool *wakeup) + } else if (*wakeup) { + error = -EBUSY; + } ++#ifdef CONFIG_MP_USB_STR_PATCH ++ enStrStatus=E_STR_IN_RESUME; ++#endif ++ recode_timestamp_init(); ++ recode_timestamp(__LINE__, "resume+"); + syscore_resume(); + } + ++ recode_timestamp(__LINE__, "en_irqs+"); + arch_suspend_enable_irqs(); + BUG_ON(irqs_disabled()); + + Enable_cpus: ++ recode_timestamp(__LINE__, "en_cpus+"); + enable_nonboot_cpus(); + + Platform_wake: ++ recode_timestamp(__LINE__, "plat_noirq+"); + platform_resume_noirq(state); ++ recode_timestamp(__LINE__, "dpm_noirq+"); ++ pr_info("PM: dpm_noirq\n"); + dpm_resume_noirq(PMSG_RESUME); + + Platform_early_resume: ++ recode_timestamp(__LINE__, "plat_early+"); + platform_resume_early(state); + + Devices_early_resume: ++ recode_timestamp(__LINE__, "dev_early+"); + dpm_resume_early(PMSG_RESUME); + + Platform_finish: + platform_resume_finish(state); ++ recode_timestamp(__LINE__, "plat_finish-"); + return error; + } + +@@ -438,14 +474,19 @@ int suspend_devices_and_enter(suspend_state_t state) + } while (!error && !wakeup && platform_suspend_again(state)); + + Resume_devices: ++ recode_timestamp(__LINE__, "resume_end+"); + suspend_test_start(); ++ pr_info("PM: dpm_resume_end\n"); + dpm_resume_end(PMSG_RESUME); + suspend_test_finish("resume devices"); ++ recode_timestamp(__LINE__, "resume_end-"); + trace_suspend_resume(TPS("resume_console"), state, true); + resume_console(); + trace_suspend_resume(TPS("resume_console"), state, false); ++ recode_timestamp(__LINE__, "console-"); + + Close: ++ recode_timestamp(__LINE__, "plat_end+"); + platform_resume_end(state); + return error; + +@@ -492,6 +533,9 @@ static int enter_state(suspend_state_t state) + } + if (!mutex_trylock(&pm_mutex)) + return -EBUSY; ++#ifdef CONFIG_MP_USB_STR_PATCH ++ enStrStatus=E_STR_IN_SUSPEND; ++#endif + + if (state == PM_SUSPEND_FREEZE) + freeze_begin(); +@@ -523,6 +567,9 @@ static int enter_state(suspend_state_t state) + pr_debug("PM: Finishing wakeup.\n"); + suspend_finish(); + Unlock: ++#ifdef CONFIG_MP_USB_STR_PATCH ++ enStrStatus=E_STR_NONE; ++#endif + mutex_unlock(&pm_mutex); + return error; + } +diff --git a/kernel/ptrace.c b/kernel/ptrace.c +index f39a7be98fc1..e0de589adca9 100644 +--- a/kernel/ptrace.c ++++ b/kernel/ptrace.c +@@ -74,9 +74,7 @@ void __ptrace_link(struct task_struct *child, struct task_struct *new_parent, + */ + static void ptrace_link(struct task_struct *child, struct task_struct *new_parent) + { +- rcu_read_lock(); +- __ptrace_link(child, new_parent, __task_cred(new_parent)); +- rcu_read_unlock(); ++ __ptrace_link(child, new_parent, current_cred()); + } + + /** +diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c +old mode 100644 +new mode 100755 +index d1a02877a42c..c92d9c06d1a7 +--- a/kernel/rcu/tree.c ++++ b/kernel/rcu/tree.c +@@ -1413,7 +1413,9 @@ static void print_other_cpu_stall(struct rcu_state *rsp, unsigned long gpnum) + + force_quiescent_state(rsp); /* Kick them all. */ + } +- ++#if defined(CONFIG_MP_IRQ_TRACE) ++#include "../../drivers/sstar/include/ms_msys.h" ++#endif + static void print_cpu_stall(struct rcu_state *rsp) + { + int cpu; +@@ -1431,6 +1433,12 @@ static void print_cpu_stall(struct rcu_state *rsp) + * See Documentation/RCU/stallwarn.txt for info on how to debug + * RCU CPU stall warnings. + */ ++#if defined(CONFIG_MP_IRQ_TRACE) ++ printk("debug:\n"); ++ msys_dump_sirq_info(); ++ ms_dump_irq_count(); ++ msys_dump_irq_info(); ++#endif + pr_err("INFO: %s self-detected stall on CPU", rsp->name); + print_cpu_stall_info_begin(); + print_cpu_stall_info(rsp, smp_processor_id()); +diff --git a/kernel/sched/core.c b/kernel/sched/core.c +old mode 100644 +new mode 100755 +index bce3a7ad4253..8990d14f7def +--- a/kernel/sched/core.c ++++ b/kernel/sched/core.c +@@ -3798,7 +3798,7 @@ int can_nice(const struct task_struct *p, const int nice) + return (nice_rlim <= task_rlimit(p, RLIMIT_NICE) || + capable(CAP_SYS_NICE)); + } +- ++EXPORT_SYMBOL(can_nice); + #ifdef __ARCH_WANT_SYS_NICE + + /* +diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c +index 3d862f5b0331..46cfee136d9d 100644 +--- a/kernel/sched/fair.c ++++ b/kernel/sched/fair.c +@@ -2253,13 +2253,23 @@ no_join: + return; + } + +-void task_numa_free(struct task_struct *p) ++/* ++ * Get rid of NUMA staticstics associated with a task (either current or dead). ++ * If @final is set, the task is dead and has reached refcount zero, so we can ++ * safely free all relevant data structures. Otherwise, there might be ++ * concurrent reads from places like load balancing and procfs, and we should ++ * reset the data back to default state without freeing ->numa_faults. ++ */ ++void task_numa_free(struct task_struct *p, bool final) + { + struct numa_group *grp = p->numa_group; +- void *numa_faults = p->numa_faults; ++ unsigned long *numa_faults = p->numa_faults; + unsigned long flags; + int i; + ++ if (!numa_faults) ++ return; ++ + if (grp) { + spin_lock_irqsave(&grp->lock, flags); + for (i = 0; i < NR_NUMA_HINT_FAULT_STATS * nr_node_ids; i++) +@@ -2272,8 +2282,14 @@ void task_numa_free(struct task_struct *p) + put_numa_group(grp); + } + +- p->numa_faults = NULL; +- kfree(numa_faults); ++ if (final) { ++ p->numa_faults = NULL; ++ kfree(numa_faults); ++ } else { ++ p->total_numa_faults = 0; ++ for (i = 0; i < NR_NUMA_HINT_FAULT_STATS * nr_node_ids; i++) ++ numa_faults[i] = 0; ++ } + } + + /* +diff --git a/kernel/softirq.c b/kernel/softirq.c +old mode 100644 +new mode 100755 +index 744fa611cae0..821aaf173b74 +--- a/kernel/softirq.c ++++ b/kernel/softirq.c +@@ -30,6 +30,11 @@ + #define CREATE_TRACE_POINTS + #include + ++#if defined(CONFIG_MP_IRQ_TRACE) ++#include "../../drivers/sstar/include/ms_msys.h" ++extern int sirq_head_initialized ; ++extern void ms_records_sirq(MSYS_IRQ_INFO *irq_info); ++#endif + /* + - No shared variables, all the data are CPU local. + - If a softirq needs serialization, let it serialize itself +@@ -137,7 +142,7 @@ EXPORT_SYMBOL(__local_bh_disable_ip); + + static void __local_bh_enable(unsigned int cnt) + { +- WARN_ON_ONCE(!irqs_disabled()); ++ lockdep_assert_irqs_disabled(); + + if (softirq_count() == (cnt & SOFTIRQ_MASK)) + trace_softirqs_on(_RET_IP_); +@@ -158,7 +163,8 @@ EXPORT_SYMBOL(_local_bh_enable); + + void __local_bh_enable_ip(unsigned long ip, unsigned int cnt) + { +- WARN_ON_ONCE(in_irq() || irqs_disabled()); ++ WARN_ON_ONCE(in_irq()); ++ lockdep_assert_irqs_enabled(); + #ifdef CONFIG_TRACE_IRQFLAGS + local_irq_disable(); + #endif +@@ -248,6 +254,9 @@ asmlinkage __visible void __softirq_entry __do_softirq(void) + __u32 pending; + int softirq_bit; + ++#if defined(CONFIG_MP_IRQ_TRACE) ++ MSYS_IRQ_INFO irq_info; ++#endif + /* + * Mask out PF_MEMALLOC s current task context is borrowed for the + * softirq. A softirq handled such as network RX might set PF_MEMALLOC +@@ -280,9 +289,25 @@ restart: + + kstat_incr_softirqs_this_cpu(vec_nr); + ++#if defined(CONFIG_MP_IRQ_TRACE) ++ irq_info.IRQNumber = vec_nr; ++ irq_info.action = h->action; ++ irq_info.timeStart = sched_clock(); ++#endif + trace_softirq_entry(vec_nr); + h->action(h); + trace_softirq_exit(vec_nr); ++ ++#if defined(CONFIG_MP_IRQ_TRACE) ++ irq_info.timeEnd = sched_clock(); ++ if (irq_info.timeEnd - irq_info.timeStart > 2500000) ++ { ++ if(sirq_head_initialized) ++ { ++ ms_records_sirq(&irq_info); ++ } ++ } ++#endif + if (unlikely(prev_count != preempt_count())) { + pr_err("huh, entered softirq %u %s %p with preempt_count %08x, exited with %08x?\n", + vec_nr, softirq_to_name[vec_nr], h->action, +@@ -396,7 +421,7 @@ void irq_exit(void) + #ifndef __ARCH_IRQ_EXIT_IRQS_DISABLED + local_irq_disable(); + #else +- WARN_ON_ONCE(!irqs_disabled()); ++ lockdep_assert_irqs_disabled(); + #endif + + account_irq_exit_time(current); +@@ -488,7 +513,7 @@ EXPORT_SYMBOL(__tasklet_hi_schedule); + + void __tasklet_hi_schedule_first(struct tasklet_struct *t) + { +- BUG_ON(!irqs_disabled()); ++ lockdep_assert_irqs_disabled(); + + t->next = __this_cpu_read(tasklet_hi_vec.head); + __this_cpu_write(tasklet_hi_vec.head, t); +diff --git a/kernel/stacktrace.c b/kernel/stacktrace.c +old mode 100644 +new mode 100755 +diff --git a/kernel/time/Makefile b/kernel/time/Makefile +old mode 100644 +new mode 100755 +index 49eca0beed32..e8fc682d542e +--- a/kernel/time/Makefile ++++ b/kernel/time/Makefile +@@ -1,3 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/sstar/include ++ + obj-y += time.o timer.o hrtimer.o itimer.o posix-timers.o posix-cpu-timers.o + obj-y += timekeeping.o ntp.o clocksource.o jiffies.o timer_list.o + obj-y += timeconv.o timecounter.o posix-clock.o alarmtimer.o +diff --git a/kernel/time/clockevents.c b/kernel/time/clockevents.c +old mode 100644 +new mode 100755 +index 2c5bc77c0bb0..e610c39f64a4 +--- a/kernel/time/clockevents.c ++++ b/kernel/time/clockevents.c +@@ -759,5 +759,11 @@ static int __init clockevents_init_sysfs(void) + err = tick_init_sysfs(); + return err; + } ++ ++#ifdef CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS ++deferred_module_init(clockevents_init_sysfs); ++#else + device_initcall(clockevents_init_sysfs); ++#endif ++ + #endif /* SYSFS */ +diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c +old mode 100644 +new mode 100755 +index 7e4fad75acaa..32a1d3640edf +--- a/kernel/time/clocksource.c ++++ b/kernel/time/clocksource.c +@@ -1021,7 +1021,12 @@ static int __init init_clocksource_sysfs(void) + return error; + } + ++#ifdef CONFIG_DEFERRED_INIICALLS_MORE_SYSFS ++deferred_module_init(init_clocksource_sysfs); ++#else + device_initcall(init_clocksource_sysfs); ++#endif ++ + #endif /* CONFIG_SYSFS */ + + /** +diff --git a/kernel/time/posix-clock.c b/kernel/time/posix-clock.c +index 9cff0ab82b63..dfb386931512 100644 +--- a/kernel/time/posix-clock.c ++++ b/kernel/time/posix-clock.c +@@ -25,8 +25,6 @@ + #include + #include + +-static void delete_clock(struct kref *kref); +- + /* + * Returns NULL if the posix_clock instance attached to 'fp' is old and stale. + */ +@@ -168,7 +166,7 @@ static int posix_clock_open(struct inode *inode, struct file *fp) + err = 0; + + if (!err) { +- kref_get(&clk->kref); ++ get_device(clk->dev); + fp->private_data = clk; + } + out: +@@ -184,7 +182,7 @@ static int posix_clock_release(struct inode *inode, struct file *fp) + if (clk->ops.release) + err = clk->ops.release(clk); + +- kref_put(&clk->kref, delete_clock); ++ put_device(clk->dev); + + fp->private_data = NULL; + +@@ -206,38 +204,35 @@ static const struct file_operations posix_clock_file_operations = { + #endif + }; + +-int posix_clock_register(struct posix_clock *clk, dev_t devid) ++int posix_clock_register(struct posix_clock *clk, struct device *dev) + { + int err; + +- kref_init(&clk->kref); + init_rwsem(&clk->rwsem); + + cdev_init(&clk->cdev, &posix_clock_file_operations); ++ err = cdev_device_add(&clk->cdev, dev); ++ if (err) { ++ pr_err("%s unable to add device %d:%d\n", ++ dev_name(dev), MAJOR(dev->devt), MINOR(dev->devt)); ++ return err; ++ } + clk->cdev.owner = clk->ops.owner; +- err = cdev_add(&clk->cdev, devid, 1); ++ clk->dev = dev; + +- return err; ++ return 0; + } + EXPORT_SYMBOL_GPL(posix_clock_register); + +-static void delete_clock(struct kref *kref) +-{ +- struct posix_clock *clk = container_of(kref, struct posix_clock, kref); +- +- if (clk->release) +- clk->release(clk); +-} +- + void posix_clock_unregister(struct posix_clock *clk) + { +- cdev_del(&clk->cdev); ++ cdev_device_del(&clk->cdev, clk->dev); + + down_write(&clk->rwsem); + clk->zombie = true; + up_write(&clk->rwsem); + +- kref_put(&clk->kref, delete_clock); ++ put_device(clk->dev); + } + EXPORT_SYMBOL_GPL(posix_clock_unregister); + +diff --git a/kernel/time/posix-cpu-timers.c b/kernel/time/posix-cpu-timers.c +index 39008d78927a..21a27bb73587 100644 +--- a/kernel/time/posix-cpu-timers.c ++++ b/kernel/time/posix-cpu-timers.c +@@ -103,7 +103,7 @@ static void bump_cpu_timer(struct k_itimer *timer, + continue; + + timer->it.cpu.expires += incr; +- timer->it_overrun += 1 << i; ++ timer->it_overrun += 1LL << i; + delta -= incr; + } + } +diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c +index fc7c37ad90a0..0e6ed2e7d066 100644 +--- a/kernel/time/posix-timers.c ++++ b/kernel/time/posix-timers.c +@@ -355,6 +355,17 @@ static __init int init_posix_timers(void) + + __initcall(init_posix_timers); + ++/* ++ * The siginfo si_overrun field and the return value of timer_getoverrun(2) ++ * are of type int. Clamp the overrun value to INT_MAX ++ */ ++static inline int timer_overrun_to_int(struct k_itimer *timr, int baseval) ++{ ++ s64 sum = timr->it_overrun_last + (s64)baseval; ++ ++ return sum > (s64)INT_MAX ? INT_MAX : (int)sum; ++} ++ + static void schedule_next_timer(struct k_itimer *timr) + { + struct hrtimer *timer = &timr->it.real.timer; +@@ -362,12 +373,11 @@ static void schedule_next_timer(struct k_itimer *timr) + if (timr->it.real.interval.tv64 == 0) + return; + +- timr->it_overrun += (unsigned int) hrtimer_forward(timer, +- timer->base->get_time(), +- timr->it.real.interval); ++ timr->it_overrun += hrtimer_forward(timer, timer->base->get_time(), ++ timr->it.real.interval); + + timr->it_overrun_last = timr->it_overrun; +- timr->it_overrun = -1; ++ timr->it_overrun = -1LL; + ++timr->it_requeue_pending; + hrtimer_restart(timer); + } +@@ -396,7 +406,7 @@ void do_schedule_next_timer(struct siginfo *info) + else + schedule_next_timer(timr); + +- info->si_overrun += timr->it_overrun_last; ++ info->si_overrun = timer_overrun_to_int(timr, info->si_overrun); + } + + if (timr) +@@ -491,8 +501,7 @@ static enum hrtimer_restart posix_timer_fn(struct hrtimer *timer) + now = ktime_add(now, kj); + } + #endif +- timr->it_overrun += (unsigned int) +- hrtimer_forward(timer, now, ++ timr->it_overrun += hrtimer_forward(timer, now, + timr->it.real.interval); + ret = HRTIMER_RESTART; + ++timr->it_requeue_pending; +@@ -633,7 +642,7 @@ SYSCALL_DEFINE3(timer_create, const clockid_t, which_clock, + it_id_set = IT_ID_SET; + new_timer->it_id = (timer_t) new_timer_id; + new_timer->it_clock = which_clock; +- new_timer->it_overrun = -1; ++ new_timer->it_overrun = -1LL; + + if (timer_event_spec) { + if (copy_from_user(&event, timer_event_spec, sizeof (event))) { +@@ -762,7 +771,7 @@ common_timer_get(struct k_itimer *timr, struct itimerspec *cur_setting) + */ + if (iv.tv64 && (timr->it_requeue_pending & REQUEUE_PENDING || + timr->it_sigev_notify == SIGEV_NONE)) +- timr->it_overrun += (unsigned int) hrtimer_forward(timer, now, iv); ++ timr->it_overrun += hrtimer_forward(timer, now, iv); + + remaining = __hrtimer_expires_remaining_adjusted(timer, now); + /* Return 0 only, when the timer is expired and not pending */ +@@ -824,7 +833,7 @@ SYSCALL_DEFINE1(timer_getoverrun, timer_t, timer_id) + if (!timr) + return -EINVAL; + +- overrun = timr->it_overrun_last; ++ overrun = timer_overrun_to_int(timr, 0); + unlock_timer(timr, flags); + + return overrun; +diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c +old mode 100644 +new mode 100755 +index dae1a45be504..9c2c5cd0687c +--- a/kernel/time/tick-sched.c ++++ b/kernel/time/tick-sched.c +@@ -30,6 +30,10 @@ + + #include + ++#ifdef CONFIG_LH_RTOS ++#include "drv_dualos.h" ++#endif ++ + /* + * Per-CPU nohz control structure + */ +@@ -550,14 +554,33 @@ update_ts_time_stats(int cpu, struct tick_sched *ts, ktime_t now, u64 *last_upda + + } + ++#ifndef CONFIG_LH_RTOS + static void tick_nohz_stop_idle(struct tick_sched *ts, ktime_t now) + { + update_ts_time_stats(smp_processor_id(), ts, now, NULL); + ts->idle_active = 0; +- ++ + sched_clock_idle_wakeup_event(0); + } ++#else ++static void tick_nohz_stop_idle(struct tick_sched *ts, ktime_t now) ++{ ++ rtkinfo_t *rtk; ++ ++ update_ts_time_stats(smp_processor_id(), ts, now, NULL); ++ ts->idle_active = 0; ++ rtk = get_rtkinfo(); ++ if (rtk) ++ { ++ rtk->linux_idle = 0; ++ /* Chip_Flush_MIU_Pipe(); move this to monitor sw */ ++ } ++ ++ sched_clock_idle_wakeup_event(0); ++} ++#endif + ++#ifndef CONFIG_LH_RTOS + static ktime_t tick_nohz_start_idle(struct tick_sched *ts) + { + ktime_t now = ktime_get(); +@@ -567,6 +590,25 @@ static ktime_t tick_nohz_start_idle(struct tick_sched *ts) + sched_clock_idle_sleep_event(); + return now; + } ++#else ++static ktime_t tick_nohz_start_idle(struct tick_sched *ts) ++{ ++ ktime_t now; ++ rtkinfo_t *rtk; ++ ++ now = ktime_get(); ++ ts->idle_entrytime = now; ++ rtk = get_rtkinfo(); ++ if (rtk) ++ { ++ rtk->linux_idle = 1; ++ /* Chip_Flush_MIU_Pipe(); move this to monitor sw */ ++ } ++ ts->idle_active = 1; ++ sched_clock_idle_sleep_event(); ++ return now; ++} ++#endif + + /** + * get_cpu_idle_time_us - get the total idle time of a CPU +diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c +old mode 100644 +new mode 100755 +index d831827d7ab0..f9ae8a8bc7d7 +--- a/kernel/time/timekeeping.c ++++ b/kernel/time/timekeeping.c +@@ -247,12 +247,24 @@ static inline cycle_t timekeeping_get_delta(struct tk_read_base *tkr) + * + * Unless you're the timekeeping code, you should not be using this! + */ ++#ifdef CONFIG_LH_RTOS ++#include "drv_dualos.h" ++#endif + static void tk_setup_internals(struct timekeeper *tk, struct clocksource *clock) + { + cycle_t interval; + u64 tmp, ntpinterval; + struct clocksource *old_clock; + ++#ifdef CONFIG_LH_RTOS ++ rtkinfo_t *rtk = get_rtkinfo(); ++ if (rtk) ++ { ++ rtk->linux_idle = 0; ++ rtk->linux_idle_in_rtos_time = 0; ++ } ++#endif ++ + ++tk->cs_was_changed_seq; + old_clock = tk->tkr_mono.clock; + tk->tkr_mono.clock = clock; +diff --git a/kernel/time/timer.c b/kernel/time/timer.c +index 2d5cc7dfee14..8162b37409ef 100644 +--- a/kernel/time/timer.c ++++ b/kernel/time/timer.c +@@ -42,6 +42,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -1633,6 +1634,13 @@ void update_process_times(int user_tick) + #endif + scheduler_tick(); + run_posix_cpu_timers(p); ++ ++ /* The current CPU might make use of net randoms without receiving IRQs ++ * to renew them often enough. Let's update the net_rand_state from a ++ * non-constant value that's not affine to the number of calls to make ++ * sure it's updated when there's some activity (we don't care in idle). ++ */ ++ this_cpu_add(net_rand_state.s1, rol32(jiffies, 24) + user_tick); + } + + /** +diff --git a/kernel/time/timer_list.c b/kernel/time/timer_list.c +index ba7d8b288bb3..7e7edaf34d70 100644 +--- a/kernel/time/timer_list.c ++++ b/kernel/time/timer_list.c +@@ -290,6 +290,7 @@ static inline void timer_list_header(struct seq_file *m, u64 now) + SEQ_printf(m, "Timer List Version: v0.8\n"); + SEQ_printf(m, "HRTIMER_MAX_CLOCK_BASES: %d\n", HRTIMER_MAX_CLOCK_BASES); + SEQ_printf(m, "now at %Ld nsecs\n", (unsigned long long)now); ++ SEQ_printf(m, "CONFIG_HZ: %d\n", CONFIG_HZ); + SEQ_printf(m, "\n"); + } + +diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c +index 15b02645ce8b..35437f4d860c 100644 +--- a/kernel/trace/trace.c ++++ b/kernel/trace/trace.c +@@ -6129,12 +6129,16 @@ static void buffer_pipe_buf_release(struct pipe_inode_info *pipe, + buf->private = 0; + } + +-static void buffer_pipe_buf_get(struct pipe_inode_info *pipe, ++static bool buffer_pipe_buf_get(struct pipe_inode_info *pipe, + struct pipe_buffer *buf) + { + struct buffer_ref *ref = (struct buffer_ref *)buf->private; + ++ if (ref->ref > INT_MAX/2) ++ return false; ++ + ref->ref++; ++ return true; + } + + /* Pipe buffer operations for a buffer. */ +diff --git a/kernel/watchdog.c b/kernel/watchdog.c +old mode 100644 +new mode 100755 +index 63177be0159e..759849d76976 +--- a/kernel/watchdog.c ++++ b/kernel/watchdog.c +@@ -221,7 +221,10 @@ bool is_hardlockup(void) + __this_cpu_write(hrtimer_interrupts_saved, hrint); + return false; + } +- ++#if defined(CONFIG_MP_IRQ_TRACE) ++unsigned long lastTouch = 0; ++#include "../drivers/sstar/include/ms_msys.h" ++#endif + static int is_softlockup(unsigned long touch_ts) + { + unsigned long now = get_timestamp(); +@@ -230,6 +233,19 @@ static int is_softlockup(unsigned long touch_ts) + /* Warn about unreasonable delays. */ + if (time_after(now, touch_ts + get_softlockup_thresh())) + return now - touch_ts; ++ ++#if defined(CONFIG_MP_IRQ_TRACE) ++ if((now - touch_ts) > lastTouch) ++ { ++ lastTouch = now - touch_ts; ++ ++ if(lastTouch >= (watchdog_thresh/2)) ++ { ++ printk("!!!!!! lastTouch(s): %ld now:%lld\r\n", lastTouch, local_clock()); ++ ms_dump_irq_count(); ++ } ++ } ++#endif + } + return 0; + } +@@ -254,6 +270,10 @@ void __weak watchdog_nmi_disable(unsigned int cpu) + static int watchdog_enable_all_cpus(void); + static void watchdog_disable_all_cpus(void); + ++#if defined(CONFIG_MP_IRQ_TRACE) ++ #include "../../drivers/sstar/include/ms_msys.h" ++#endif ++ + /* watchdog kicker functions */ + static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer) + { +@@ -334,7 +354,12 @@ static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer) + return HRTIMER_RESTART; + } + } +- ++#if defined(CONFIG_MP_IRQ_TRACE) ++ printk("debug:\n"); ++ ms_dump_irq_count(); ++ msys_dump_sirq_info(); ++ msys_dump_irq_info(); ++#endif + pr_emerg("BUG: soft lockup - CPU#%d stuck for %us! [%s:%d]\n", + smp_processor_id(), duration, + current->comm, task_pid_nr(current)); +@@ -346,6 +371,7 @@ static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer) + else + dump_stack(); + ++ + if (softlockup_all_cpu_backtrace) { + /* Avoid generating two back traces for current + * given that one is already made above +diff --git a/lib/random32.c b/lib/random32.c +index fa594b1140e6..d5c3137d93f4 100644 +--- a/lib/random32.c ++++ b/lib/random32.c +@@ -47,7 +47,7 @@ static inline void prandom_state_selftest(void) + } + #endif + +-static DEFINE_PER_CPU(struct rnd_state, net_rand_state) __latent_entropy; ++DEFINE_PER_CPU(struct rnd_state, net_rand_state) __latent_entropy; + + /** + * prandom_u32_state - seeded pseudo-random number generator. +diff --git a/list_config.sh b/list_config.sh +new file mode 100755 +index 000000000000..3a47e6c65541 +--- /dev/null ++++ b/list_config.sh +@@ -0,0 +1,7 @@ ++#!/bin/bash ++dir=arch/arm/configs ++if [ "${1}" == "" ]; then echo -e "Usage ${0##*/} [PREFIX] \nPREFIX: 3 5 6 2m"; fi ++pushd $dir > /dev/null ++echo -e "to $dir/\n" ++ls -1 infinity${1}*_defconfig ++popd > /dev/null +diff --git a/mm/debug.c b/mm/debug.c +index 9feb699c5d25..bebe48aece6d 100644 +--- a/mm/debug.c ++++ b/mm/debug.c +@@ -95,7 +95,7 @@ EXPORT_SYMBOL(dump_vma); + + void dump_mm(const struct mm_struct *mm) + { +- pr_emerg("mm %p mmap %p seqnum %d task_size %lu\n" ++ pr_emerg("mm %p mmap %p seqnum %llu task_size %lu\n" + #ifdef CONFIG_MMU + "get_unmapped_area %p\n" + #endif +@@ -125,7 +125,7 @@ void dump_mm(const struct mm_struct *mm) + #endif + "def_flags: %#lx(%pGv)\n", + +- mm, mm->mmap, mm->vmacache_seqnum, mm->task_size, ++ mm, mm->mmap, (long long) mm->vmacache_seqnum, mm->task_size, + #ifdef CONFIG_MMU + mm->get_unmapped_area, + #endif +diff --git a/mm/gup.c b/mm/gup.c +index c63a0341ae38..3bb40e950e7e 100644 +--- a/mm/gup.c ++++ b/mm/gup.c +@@ -61,13 +61,22 @@ static int follow_pfn_pte(struct vm_area_struct *vma, unsigned long address, + } + + /* +- * FOLL_FORCE can write to even unwritable pte's, but only +- * after we've gone through a COW cycle and they are dirty. ++ * FOLL_FORCE or a forced COW break can write even to unwritable pte's, ++ * but only after we've gone through a COW cycle and they are dirty. + */ + static inline bool can_follow_write_pte(pte_t pte, unsigned int flags) + { +- return pte_write(pte) || +- ((flags & FOLL_FORCE) && (flags & FOLL_COW) && pte_dirty(pte)); ++ return pte_write(pte) || ((flags & FOLL_COW) && pte_dirty(pte)); ++} ++ ++/* ++ * A (separate) COW fault might break the page the other way and ++ * get_user_pages() would return the page from what is now the wrong ++ * VM. So we need to force a COW break at GUP time even for reads. ++ */ ++static inline bool should_force_cow_break(struct vm_area_struct *vma, unsigned int flags) ++{ ++ return is_cow_mapping(vma->vm_flags) && (flags & (FOLL_GET)); + } + + static struct page *follow_page_pte(struct vm_area_struct *vma, +@@ -153,7 +162,10 @@ retry: + } + + if (flags & FOLL_GET) { +- get_page(page); ++ if (unlikely(!try_get_page(page))) { ++ page = ERR_PTR(-ENOMEM); ++ goto out; ++ } + + /* drop the pgmap reference now that we hold the page */ + if (pgmap) { +@@ -292,7 +304,10 @@ struct page *follow_page_mask(struct vm_area_struct *vma, + if (pmd_trans_unstable(pmd)) + ret = -EBUSY; + } else { +- get_page(page); ++ if (unlikely(!try_get_page(page))) { ++ spin_unlock(ptl); ++ return ERR_PTR(-ENOMEM); ++ } + spin_unlock(ptl); + lock_page(page); + ret = split_huge_page(page); +@@ -348,7 +363,10 @@ static int get_gate_page(struct mm_struct *mm, unsigned long address, + goto unmap; + *page = pte_page(*pte); + } +- get_page(*page); ++ if (unlikely(!try_get_page(*page))) { ++ ret = -ENOMEM; ++ goto unmap; ++ } + out: + ret = 0; + unmap: +@@ -430,6 +448,9 @@ static int check_vma_flags(struct vm_area_struct *vma, unsigned long gup_flags) + if (vm_flags & (VM_IO | VM_PFNMAP)) + return -EFAULT; + ++ if (gup_flags & FOLL_ANON && !vma_is_anonymous(vma)) ++ return -EFAULT; ++ + if (write) { + if (!(vm_flags & VM_WRITE)) { + if (!(gup_flags & FOLL_FORCE)) +@@ -565,12 +586,18 @@ static long __get_user_pages(struct task_struct *tsk, struct mm_struct *mm, + if (!vma || check_vma_flags(vma, gup_flags)) + return i ? : -EFAULT; + if (is_vm_hugetlb_page(vma)) { ++ if (should_force_cow_break(vma, foll_flags)) ++ foll_flags |= FOLL_WRITE; + i = follow_hugetlb_page(mm, vma, pages, vmas, + &start, &nr_pages, i, +- gup_flags); ++ foll_flags); + continue; + } + } ++ ++ if (should_force_cow_break(vma, foll_flags)) ++ foll_flags |= FOLL_WRITE; ++ + retry: + /* + * If we have a pending SIGKILL, don't keep faulting pages and +@@ -1166,6 +1193,20 @@ struct page *get_dump_page(unsigned long addr) + */ + #ifdef CONFIG_HAVE_GENERIC_RCU_GUP + ++/* ++ * Return the compund head page with ref appropriately incremented, ++ * or NULL if that failed. ++ */ ++static inline struct page *try_get_compound_head(struct page *page, int refs) ++{ ++ struct page *head = compound_head(page); ++ if (WARN_ON_ONCE(page_ref_count(head) < 0)) ++ return NULL; ++ if (unlikely(!page_cache_add_speculative(head, refs))) ++ return NULL; ++ return head; ++} ++ + #ifdef __HAVE_ARCH_PTE_SPECIAL + static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end, + int write, struct page **pages, int *nr) +@@ -1198,9 +1239,9 @@ static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end, + + VM_BUG_ON(!pfn_valid(pte_pfn(pte))); + page = pte_page(pte); +- head = compound_head(page); + +- if (!page_cache_get_speculative(head)) ++ head = try_get_compound_head(page, 1); ++ if (!head) + goto pte_unmap; + + if (unlikely(pte_val(pte) != pte_val(*ptep))) { +@@ -1248,17 +1289,16 @@ static int gup_huge_pmd(pmd_t orig, pmd_t *pmdp, unsigned long addr, + return 0; + + refs = 0; +- head = pmd_page(orig); +- page = head + ((addr & ~PMD_MASK) >> PAGE_SHIFT); ++ page = pmd_page(orig) + ((addr & ~PMD_MASK) >> PAGE_SHIFT); + do { +- VM_BUG_ON_PAGE(compound_head(page) != head, page); + pages[*nr] = page; + (*nr)++; + page++; + refs++; + } while (addr += PAGE_SIZE, addr != end); + +- if (!page_cache_add_speculative(head, refs)) { ++ head = try_get_compound_head(pgd_page(orig), refs); ++ if (!head) { + *nr -= refs; + return 0; + } +@@ -1283,17 +1323,16 @@ static int gup_huge_pud(pud_t orig, pud_t *pudp, unsigned long addr, + return 0; + + refs = 0; +- head = pud_page(orig); +- page = head + ((addr & ~PUD_MASK) >> PAGE_SHIFT); ++ page = pud_page(orig) + ((addr & ~PUD_MASK) >> PAGE_SHIFT); + do { +- VM_BUG_ON_PAGE(compound_head(page) != head, page); + pages[*nr] = page; + (*nr)++; + page++; + refs++; + } while (addr += PAGE_SIZE, addr != end); + +- if (!page_cache_add_speculative(head, refs)) { ++ head = try_get_compound_head(pmd_page(orig), refs); ++ if (!head) { + *nr -= refs; + return 0; + } +@@ -1319,17 +1358,16 @@ static int gup_huge_pgd(pgd_t orig, pgd_t *pgdp, unsigned long addr, + return 0; + + refs = 0; +- head = pgd_page(orig); +- page = head + ((addr & ~PGDIR_MASK) >> PAGE_SHIFT); ++ page = pgd_page(orig) + ((addr & ~PGDIR_MASK) >> PAGE_SHIFT); + do { +- VM_BUG_ON_PAGE(compound_head(page) != head, page); + pages[*nr] = page; + (*nr)++; + page++; + refs++; + } while (addr += PAGE_SIZE, addr != end); + +- if (!page_cache_add_speculative(head, refs)) { ++ head = try_get_compound_head(pud_page(orig), refs); ++ if (!head) { + *nr -= refs; + return 0; + } +@@ -1417,6 +1455,10 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end, + /* + * Like get_user_pages_fast() except it's IRQ-safe in that it won't fall back to + * the regular GUP. It will only return non-negative values. ++ * ++ * Careful, careful! COW breaking can go either way, so a non-write ++ * access can get ambiguous page results. If you call this function without ++ * 'write' set, you'd better be sure that you're ok with that ambiguity. + */ + int __get_user_pages_fast(unsigned long start, int nr_pages, int write, + struct page **pages) +@@ -1446,6 +1488,12 @@ int __get_user_pages_fast(unsigned long start, int nr_pages, int write, + * + * We do not adopt an rcu_read_lock(.) here as we also want to + * block IPIs that come from THPs splitting. ++ * ++ * NOTE! We allow read-only gup_fast() here, but you'd better be ++ * careful about possible COW pages. You'll get _a_ COW page, but ++ * not necessarily the one you intended to get depending on what ++ * COW event happens after this. COW may break the page copy in a ++ * random direction. + */ + + local_irq_save(flags); +@@ -1494,7 +1542,14 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, + int nr, ret; + + start &= PAGE_MASK; +- nr = __get_user_pages_fast(start, nr_pages, write, pages); ++ /* ++ * The FAST_GUP case requires FOLL_WRITE even for pure reads, ++ * because get_user_pages() may need to cause an early COW in ++ * order to avoid confusing the normal COW routines. So only ++ * targets that are already writable are safe to do by just ++ * looking at the page tables. ++ */ ++ nr = __get_user_pages_fast(start, nr_pages, 1, pages); + ret = nr; + + if (nr < nr_pages) { +diff --git a/mm/huge_memory.c b/mm/huge_memory.c +index c234c078693c..b1b31b3017e8 100644 +--- a/mm/huge_memory.c ++++ b/mm/huge_memory.c +@@ -1120,13 +1120,12 @@ out_unlock: + } + + /* +- * FOLL_FORCE can write to even unwritable pmd's, but only +- * after we've gone through a COW cycle and they are dirty. ++ * FOLL_FORCE or a forced COW break can write even to unwritable pmd's, ++ * but only after we've gone through a COW cycle and they are dirty. + */ + static inline bool can_follow_write_pmd(pmd_t pmd, unsigned int flags) + { +- return pmd_write(pmd) || +- ((flags & FOLL_FORCE) && (flags & FOLL_COW) && pmd_dirty(pmd)); ++ return pmd_write(pmd) || ((flags & FOLL_COW) && pmd_dirty(pmd)); + } + + struct page *follow_trans_huge_pmd(struct vm_area_struct *vma, +diff --git a/mm/hugetlb.c b/mm/hugetlb.c +index 6ff65c405243..649c9994760c 100644 +--- a/mm/hugetlb.c ++++ b/mm/hugetlb.c +@@ -3961,6 +3961,7 @@ long follow_hugetlb_page(struct mm_struct *mm, struct vm_area_struct *vma, + unsigned long vaddr = *position; + unsigned long remainder = *nr_pages; + struct hstate *h = hstate_vma(vma); ++ int err = -EFAULT; + + while (vaddr < vma->vm_end && remainder) { + pte_t *pte; +@@ -4032,6 +4033,19 @@ long follow_hugetlb_page(struct mm_struct *mm, struct vm_area_struct *vma, + + pfn_offset = (vaddr & ~huge_page_mask(h)) >> PAGE_SHIFT; + page = pte_page(huge_ptep_get(pte)); ++ ++ /* ++ * Instead of doing 'try_get_page()' below in the same_page ++ * loop, just check the count once here. ++ */ ++ if (unlikely(page_count(page) <= 0)) { ++ if (pages) { ++ spin_unlock(ptl); ++ remainder = 0; ++ err = -ENOMEM; ++ break; ++ } ++ } + same_page: + if (pages) { + pages[i] = mem_map_offset(page, pfn_offset); +@@ -4058,7 +4072,7 @@ same_page: + *nr_pages = remainder; + *position = vaddr; + +- return i ? i : -EFAULT; ++ return i ? i : err; + } + + #ifndef __HAVE_ARCH_FLUSH_HUGETLB_TLB_RANGE +diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c +index 0e9505f66ec1..db268c706704 100644 +--- a/mm/kasan/kasan.c ++++ b/mm/kasan/kasan.c +@@ -116,94 +116,30 @@ static __always_inline bool memory_is_poisoned_1(unsigned long addr) + return false; + } + +-static __always_inline bool memory_is_poisoned_2(unsigned long addr) ++static __always_inline bool memory_is_poisoned_2_4_8(unsigned long addr, ++ unsigned long size) + { +- u16 *shadow_addr = (u16 *)kasan_mem_to_shadow((void *)addr); +- +- if (unlikely(*shadow_addr)) { +- if (memory_is_poisoned_1(addr + 1)) +- return true; +- +- /* +- * If single shadow byte covers 2-byte access, we don't +- * need to do anything more. Otherwise, test the first +- * shadow byte. +- */ +- if (likely(((addr + 1) & KASAN_SHADOW_MASK) != 0)) +- return false; +- +- return unlikely(*(u8 *)shadow_addr); +- } ++ u8 *shadow_addr = (u8 *)kasan_mem_to_shadow((void *)addr); + +- return false; +-} +- +-static __always_inline bool memory_is_poisoned_4(unsigned long addr) +-{ +- u16 *shadow_addr = (u16 *)kasan_mem_to_shadow((void *)addr); +- +- if (unlikely(*shadow_addr)) { +- if (memory_is_poisoned_1(addr + 3)) +- return true; +- +- /* +- * If single shadow byte covers 4-byte access, we don't +- * need to do anything more. Otherwise, test the first +- * shadow byte. +- */ +- if (likely(((addr + 3) & KASAN_SHADOW_MASK) >= 3)) +- return false; +- +- return unlikely(*(u8 *)shadow_addr); +- } +- +- return false; +-} +- +-static __always_inline bool memory_is_poisoned_8(unsigned long addr) +-{ +- u16 *shadow_addr = (u16 *)kasan_mem_to_shadow((void *)addr); +- +- if (unlikely(*shadow_addr)) { +- if (memory_is_poisoned_1(addr + 7)) +- return true; +- +- /* +- * If single shadow byte covers 8-byte access, we don't +- * need to do anything more. Otherwise, test the first +- * shadow byte. +- */ +- if (likely(IS_ALIGNED(addr, KASAN_SHADOW_SCALE_SIZE))) +- return false; +- +- return unlikely(*(u8 *)shadow_addr); +- } ++ /* ++ * Access crosses 8(shadow size)-byte boundary. Such access maps ++ * into 2 shadow bytes, so we need to check them both. ++ */ ++ if (unlikely(((addr + size - 1) & KASAN_SHADOW_MASK) < size - 1)) ++ return *shadow_addr || memory_is_poisoned_1(addr + size - 1); + +- return false; ++ return memory_is_poisoned_1(addr + size - 1); + } + + static __always_inline bool memory_is_poisoned_16(unsigned long addr) + { +- u32 *shadow_addr = (u32 *)kasan_mem_to_shadow((void *)addr); +- +- if (unlikely(*shadow_addr)) { +- u16 shadow_first_bytes = *(u16 *)shadow_addr; +- +- if (unlikely(shadow_first_bytes)) +- return true; +- +- /* +- * If two shadow bytes covers 16-byte access, we don't +- * need to do anything more. Otherwise, test the last +- * shadow byte. +- */ +- if (likely(IS_ALIGNED(addr, KASAN_SHADOW_SCALE_SIZE))) +- return false; ++ u16 *shadow_addr = (u16 *)kasan_mem_to_shadow((void *)addr); + +- return memory_is_poisoned_1(addr + 15); +- } ++ /* Unaligned 16-bytes access maps into 3 shadow bytes. */ ++ if (unlikely(!IS_ALIGNED(addr, KASAN_SHADOW_SCALE_SIZE))) ++ return *shadow_addr || memory_is_poisoned_1(addr + 15); + +- return false; ++ return *shadow_addr; + } + + static __always_inline unsigned long bytes_is_zero(const u8 *start, +@@ -274,11 +210,9 @@ static __always_inline bool memory_is_poisoned(unsigned long addr, size_t size) + case 1: + return memory_is_poisoned_1(addr); + case 2: +- return memory_is_poisoned_2(addr); + case 4: +- return memory_is_poisoned_4(addr); + case 8: +- return memory_is_poisoned_8(addr); ++ return memory_is_poisoned_2_4_8(addr, size); + case 16: + return memory_is_poisoned_16(addr); + default: +@@ -371,9 +305,9 @@ void kasan_free_pages(struct page *page, unsigned int order) + * Adaptive redzone policy taken from the userspace AddressSanitizer runtime. + * For larger allocations larger redzones are used. + */ +-static size_t optimal_redzone(size_t object_size) ++static unsigned int optimal_redzone(unsigned int object_size) + { +- int rz = ++ return + object_size <= 64 - 16 ? 16 : + object_size <= 128 - 32 ? 32 : + object_size <= 512 - 64 ? 64 : +@@ -381,14 +315,13 @@ static size_t optimal_redzone(size_t object_size) + object_size <= (1 << 14) - 256 ? 256 : + object_size <= (1 << 15) - 512 ? 512 : + object_size <= (1 << 16) - 1024 ? 1024 : 2048; +- return rz; + } + +-void kasan_cache_create(struct kmem_cache *cache, size_t *size, ++void kasan_cache_create(struct kmem_cache *cache, unsigned int *size, + unsigned long *flags) + { ++ unsigned int orig_size = *size; + int redzone_adjust; +- int orig_size = *size; + + /* Add alloc meta. */ + cache->kasan_info.alloc_meta_offset = *size; +@@ -406,7 +339,8 @@ void kasan_cache_create(struct kmem_cache *cache, size_t *size, + if (redzone_adjust > 0) + *size += redzone_adjust; + +- *size = min(KMALLOC_MAX_SIZE, max(*size, cache->object_size + ++ *size = min_t(unsigned int, KMALLOC_MAX_SIZE, ++ max(*size, cache->object_size + + optimal_redzone(cache->object_size))); + + /* +diff --git a/mm/memblock.c b/mm/memblock.c +index 42b98af6a415..735b6dd6f8ba 100644 +--- a/mm/memblock.c ++++ b/mm/memblock.c +@@ -204,7 +204,8 @@ phys_addr_t __init_memblock memblock_find_in_range_node(phys_addr_t size, + phys_addr_t kernel_end, ret; + + /* pump up @end */ +- if (end == MEMBLOCK_ALLOC_ACCESSIBLE) ++ if (end == MEMBLOCK_ALLOC_ACCESSIBLE || ++ end == MEMBLOCK_ALLOC_KASAN) + end = memblock.current_limit; + + /* avoid allocating the first page */ +@@ -1303,13 +1304,15 @@ done: + ptr = phys_to_virt(alloc); + memset(ptr, 0, size); + +- /* +- * The min_count is set to 0 so that bootmem allocated blocks +- * are never reported as leaks. This is because many of these blocks +- * are only referred via the physical address which is not +- * looked up by kmemleak. +- */ +- kmemleak_alloc(ptr, size, 0, 0); ++ /* Skip kmemleak for kasan_init() due to high volume. */ ++ if (max_addr != MEMBLOCK_ALLOC_KASAN) ++ /* ++ * The min_count is set to 0 so that bootmem allocated ++ * blocks are never reported as leaks. This is because many ++ * of these blocks are only referred via the physical ++ * address which is not looked up by kmemleak. ++ */ ++ kmemleak_alloc(ptr, size, 0, 0); + + return ptr; + } +diff --git a/mm/mlock.c b/mm/mlock.c +old mode 100644 +new mode 100755 +index f0505692a5f4..d65c2891f416 +--- a/mm/mlock.c ++++ b/mm/mlock.c +@@ -709,6 +709,10 @@ static __must_check int do_mlock(unsigned long start, size_t len, vm_flags_t fla + return 0; + } + ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(__mm_populate); ++#endif ++ + SYSCALL_DEFINE2(mlock, unsigned long, start, size_t, len) + { + return do_mlock(start, len, VM_LOCKED); +diff --git a/mm/mmap.c b/mm/mmap.c +old mode 100644 +new mode 100755 +index 45ac5b973459..fdeaf34637ef +--- a/mm/mmap.c ++++ b/mm/mmap.c +@@ -1469,6 +1469,10 @@ unsigned long do_mmap(struct file *file, unsigned long addr, + return addr; + } + ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(do_mmap); ++#endif ++ + SYSCALL_DEFINE6(mmap_pgoff, unsigned long, addr, unsigned long, len, + unsigned long, prot, unsigned long, flags, + unsigned long, fd, unsigned long, pgoff) +@@ -2417,7 +2421,8 @@ find_extend_vma(struct mm_struct *mm, unsigned long addr) + vma = find_vma_prev(mm, addr, &prev); + if (vma && (vma->vm_start <= addr)) + return vma; +- if (!prev || expand_stack(prev, addr)) ++ /* don't alter vm_end if the coredump is running */ ++ if (!prev || !mmget_still_valid(mm) || expand_stack(prev, addr)) + return NULL; + if (prev->vm_flags & VM_LOCKED) + populate_vma_page_range(prev, addr, prev->vm_end, NULL); +@@ -2443,6 +2448,9 @@ find_extend_vma(struct mm_struct *mm, unsigned long addr) + return vma; + if (!(vma->vm_flags & VM_GROWSDOWN)) + return NULL; ++ /* don't alter vm_start if the coredump is running */ ++ if (!mmget_still_valid(mm)) ++ return NULL; + start = vma->vm_start; + if (expand_stack(vma, addr)) + return NULL; +@@ -2702,6 +2710,10 @@ int do_munmap(struct mm_struct *mm, unsigned long start, size_t len) + return 0; + } + ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(do_munmap); ++#endif ++ + int vm_munmap(unsigned long start, size_t len) + { + int ret; +diff --git a/mm/mremap.c b/mm/mremap.c +index 15976716dd40..15abad7d1385 100644 +--- a/mm/mremap.c ++++ b/mm/mremap.c +@@ -213,7 +213,7 @@ unsigned long move_page_tables(struct vm_area_struct *vma, + new_pmd = alloc_new_pmd(vma->vm_mm, vma, new_addr); + if (!new_pmd) + break; +- if (pmd_trans_huge(*old_pmd)) { ++ if (pmd_trans_huge(*old_pmd) || pmd_devmap(*old_pmd)) { + if (extent == HPAGE_PMD_SIZE) { + bool moved; + /* See comment in move_ptes() */ +diff --git a/mm/page-writeback.c b/mm/page-writeback.c +index 439cc63ad903..decf2a9fc516 100644 +--- a/mm/page-writeback.c ++++ b/mm/page-writeback.c +@@ -2752,6 +2752,7 @@ int test_clear_page_writeback(struct page *page) + unlock_page_memcg(page); + return ret; + } ++EXPORT_SYMBOL(test_clear_page_writeback); + + int __test_set_page_writeback(struct page *page, bool keep_write) + { +diff --git a/mm/percpu.c b/mm/percpu.c +index f014cebbf405..e9b22750f406 100644 +--- a/mm/percpu.c ++++ b/mm/percpu.c +@@ -2047,8 +2047,8 @@ int __init pcpu_embed_first_chunk(size_t reserved_size, size_t dyn_size, + ai->groups[group].base_offset = areas[group] - base; + } + +- pr_info("Embedded %zu pages/cpu @%p s%zu r%zu d%zu u%zu\n", +- PFN_DOWN(size_sum), base, ai->static_size, ai->reserved_size, ++ pr_info("Embedded %zu pages/cpu s%zu r%zu d%zu u%zu\n", ++ PFN_DOWN(size_sum), ai->static_size, ai->reserved_size, + ai->dyn_size, ai->unit_size); + + rc = pcpu_setup_first_chunk(ai, base); +@@ -2161,8 +2161,8 @@ int __init pcpu_page_first_chunk(size_t reserved_size, + } + + /* we're ready, commit */ +- pr_info("%d %s pages/cpu @%p s%zu r%zu d%zu\n", +- unit_pages, psize_str, vm.addr, ai->static_size, ++ pr_info("%d %s pages/cpu s%zu r%zu d%zu\n", ++ unit_pages, psize_str, ai->static_size, + ai->reserved_size, ai->dyn_size); + + rc = pcpu_setup_first_chunk(ai, vm.addr); +diff --git a/mm/readahead.c b/mm/readahead.c +index c8a955b1297e..5f9aee835b68 100644 +--- a/mm/readahead.c ++++ b/mm/readahead.c +@@ -202,6 +202,14 @@ out: + return ret; + } + ++int do_page_cache_readahead(struct address_space *mapping, struct file *filp, pgoff_t offset, unsigned long nr_to_read) ++{ ++ int ret = 0; ++ ret = __do_page_cache_readahead(mapping, filp, offset, nr_to_read, 0); ++ return ret; ++} ++EXPORT_SYMBOL(do_page_cache_readahead); ++ + /* + * Chunk the readahead into 2 megabyte units, so that we don't pin too much + * memory at once. +diff --git a/mm/slab.c b/mm/slab.c +index 1f82d16a0518..9dd0e5242679 100644 +--- a/mm/slab.c ++++ b/mm/slab.c +@@ -2034,7 +2034,7 @@ __kmem_cache_create (struct kmem_cache *cachep, unsigned long flags) + size_t ralign = BYTES_PER_WORD; + gfp_t gfp; + int err; +- size_t size = cachep->size; ++ unsigned int size = cachep->size; + + #if DEBUG + #if FORCED_DEBUG +diff --git a/mm/slub.c b/mm/slub.c +old mode 100644 +new mode 100755 +index edc79ca3c6d5..777d6afa9d33 +--- a/mm/slub.c ++++ b/mm/slub.c +@@ -3414,7 +3414,7 @@ static void set_min_partial(struct kmem_cache *s, unsigned long min) + static int calculate_sizes(struct kmem_cache *s, int forced_order) + { + unsigned long flags = s->flags; +- size_t size = s->object_size; ++ unsigned int size = s->object_size; + int order; + + /* +@@ -4647,7 +4647,7 @@ static void __init resiliency_test(void) + validate_slab_cache(kmalloc_caches[9]); + } + #else +-#ifdef CONFIG_SYSFS ++#if defined(CONFIG_SYSFS) && !defined(CONFIG_DISABLE_SLAB_SYSFS_SUPPORT) + static void resiliency_test(void) {}; + #endif + #endif +@@ -5714,7 +5714,12 @@ static int __init slab_sysfs_init(void) + return 0; + } + ++#ifdef CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS ++deferred_module_init(slab_sysfs_init); ++#else + __initcall(slab_sysfs_init); ++#endif ++ + #endif /* CONFIG_SYSFS */ + + /* +diff --git a/mm/vmacache.c b/mm/vmacache.c +index 035fdeb35b43..c9ca3dd46b97 100644 +--- a/mm/vmacache.c ++++ b/mm/vmacache.c +@@ -5,44 +5,6 @@ + #include + #include + +-/* +- * Flush vma caches for threads that share a given mm. +- * +- * The operation is safe because the caller holds the mmap_sem +- * exclusively and other threads accessing the vma cache will +- * have mmap_sem held at least for read, so no extra locking +- * is required to maintain the vma cache. +- */ +-void vmacache_flush_all(struct mm_struct *mm) +-{ +- struct task_struct *g, *p; +- +- count_vm_vmacache_event(VMACACHE_FULL_FLUSHES); +- +- /* +- * Single threaded tasks need not iterate the entire +- * list of process. We can avoid the flushing as well +- * since the mm's seqnum was increased and don't have +- * to worry about other threads' seqnum. Current's +- * flush will occur upon the next lookup. +- */ +- if (atomic_read(&mm->mm_users) == 1) +- return; +- +- rcu_read_lock(); +- for_each_process_thread(g, p) { +- /* +- * Only flush the vmacache pointers as the +- * mm seqnum is already set and curr's will +- * be set upon invalidation when the next +- * lookup is done. +- */ +- if (mm == p->mm) +- vmacache_flush(p); +- } +- rcu_read_unlock(); +-} +- + /* + * This task may be accessing a foreign mm via (for example) + * get_user_pages()->find_vma(). The vmacache is task-local and this +diff --git a/mm/vmalloc.c b/mm/vmalloc.c +old mode 100644 +new mode 100755 +index 195de42bea1f..fedaf9a0ef41 +--- a/mm/vmalloc.c ++++ b/mm/vmalloc.c +@@ -203,9 +203,13 @@ static int vmap_page_range_noflush(unsigned long start, unsigned long end, + + return nr; + } +- ++#ifdef CONFIG_MSTAR_MMAHEAP ++int vmap_page_range(unsigned long start, unsigned long end, ++ pgprot_t prot, struct page **pages) ++#else + static int vmap_page_range(unsigned long start, unsigned long end, + pgprot_t prot, struct page **pages) ++#endif + { + int ret; + +@@ -214,6 +218,10 @@ static int vmap_page_range(unsigned long start, unsigned long end, + return ret; + } + ++#ifdef CONFIG_MSTAR_MMAHEAP ++EXPORT_SYMBOL(vmap_page_range); ++#endif ++ + int is_vmalloc_or_module_addr(const void *x) + { + /* +@@ -492,7 +500,7 @@ overflow: + } + } + +- if (printk_ratelimit()) ++ if (printk_ratelimit() && !(gfp_mask & __GFP_NOWARN)) + pr_warn("vmap allocation for size %lu failed: use vmalloc= to increase size\n", + size); + kfree(va); +@@ -1426,14 +1434,14 @@ struct vm_struct *get_vm_area(unsigned long size, unsigned long flags) + NUMA_NO_NODE, GFP_KERNEL, + __builtin_return_address(0)); + } +- ++EXPORT_SYMBOL(get_vm_area); + struct vm_struct *get_vm_area_caller(unsigned long size, unsigned long flags, + const void *caller) + { + return __get_vm_area_node(size, 1, flags, VMALLOC_START, VMALLOC_END, + NUMA_NO_NODE, GFP_KERNEL, caller); + } +- ++EXPORT_SYMBOL(get_vm_area_caller); + /** + * find_vm_area - find a continuous kernel virtual area + * @addr: base address +diff --git a/mm/vmstat.c b/mm/vmstat.c +index 3863b5d6d598..4a28eecd68d4 100644 +--- a/mm/vmstat.c ++++ b/mm/vmstat.c +@@ -1086,7 +1086,6 @@ const char * const vmstat_text[] = { + #ifdef CONFIG_DEBUG_VM_VMACACHE + "vmacache_find_calls", + "vmacache_find_hits", +- "vmacache_full_flushes", + #endif + #endif /* CONFIG_VM_EVENTS_COUNTERS */ + }; +diff --git a/ms_pack_modules.sh b/ms_pack_modules.sh +new file mode 100755 +index 000000000000..617d08001723 +--- /dev/null ++++ b/ms_pack_modules.sh +@@ -0,0 +1,85 @@ ++#!/bin/bash ++ ++while getopts "i:a:x" opt; do ++ case $opt in ++ a) ++ arch=$OPTARG ++ ;; ++ i) ++ api_version=$OPTARG ++ ;; ++ x) ++ XIP=1 ++ ;; ++ \?) ++ echo "Invalid option: -$OPTARG" >&2 ++ ;; ++ esac ++done ++ ++#kl_dir=$1 ++#api_version=$2 ++ ++if [ "${arch}" = "" ] ++then ++ echo ++# echo " ARCH is not specified via -a parameter, set to arm !!" ++ echo ++ arch=arm ++fi ++ ++ ++ ++kl_dir=$(pwd) ++XIP_PREFIX= ++ ++IMAGE=Image ++ ++if [ "${XIP}" = "1" ]; then ++ IMAGE=xipImage ++ XIP_PREFIX='xip' ++fi ++ ++ ++TMP=.pack_tmp ++rm -Rf ${TMP} ++#rm -Rf ${dst_dir} ++mkdir -p ${TMP} ++ ++ ++ ++kernel_id=$(strings ${kl_dir}/arch/${arch}/boot/${IMAGE} | grep MVX.*KL_LX | cut -b 17-28 | sed -n 's/KL_\([^#]*\)#*/\1/p') ++platform_id=$(strings ${kl_dir}/arch/${arch}/boot/${IMAGE} | grep MVX.*KL_LX | cut -b 7-8) ++commit=$(strings ${kl_dir}/arch/${arch}/boot/${IMAGE} | grep MVX.*KL_LX | cut -b 10-16) ++ ++MODULE_DIR=${XIP_PREFIX}modules ++ ++echo " Packing modules to '${kl_dir}/${MODULE_DIR}'" ++echo ++ ++ rm -Rf ${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR} ++ mkdir -p ${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR} ++ rm -Rf ${kl_dir}/${MODULE_DIR} ++ exec < ${kl_dir}/modules.order ++ while read line ++ do ++ module_file=$(echo ${line} | sed -e 's/^kernel\///g') ++ #echo ${module_file} ++ file_name=$(echo ${module_file} | sed 's/.*\///g') ++ #echo f=${file_name} ++ if [ -e "${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR}/${file_name}" ] ++ then ++ echo " ERROR!! Duplicated module file: ${module_file} " ++ echo " Please check module list to avoid this problem. " ++ echo " Aborted" ++ exit -1 ++ fi ++# echo " cp -f ${kl_dir}/${module_file} ${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR}/${file_name}" ++ cp -f ${kl_dir}/${module_file} ${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR}/${file_name} ++ echo ${file_name} >> ${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR}/modules.list ++ done ++ cp -Rf ${TMP}/${platform_id}/${kernel_id}/${MODULE_DIR} ${kl_dir}/ ++ chmod -Rf 777 ${kl_dir}/${MODULE_DIR} ++ rm -Rf ${TMP} ++echo ++ +diff --git a/net/appletalk/atalk_proc.c b/net/appletalk/atalk_proc.c +index af46bc49e1e9..b5f84f428aa6 100644 +--- a/net/appletalk/atalk_proc.c ++++ b/net/appletalk/atalk_proc.c +@@ -293,7 +293,7 @@ out_interface: + goto out; + } + +-void __exit atalk_proc_exit(void) ++void atalk_proc_exit(void) + { + remove_proc_entry("interface", atalk_proc_dir); + remove_proc_entry("route", atalk_proc_dir); +diff --git a/net/appletalk/ddp.c b/net/appletalk/ddp.c +index 10d2bdce686e..e206d98b3b82 100644 +--- a/net/appletalk/ddp.c ++++ b/net/appletalk/ddp.c +@@ -1912,12 +1912,16 @@ static const char atalk_err_snap[] __initconst = + /* Called by proto.c on kernel start up */ + static int __init atalk_init(void) + { +- int rc = proto_register(&ddp_proto, 0); ++ int rc; + +- if (rc != 0) ++ rc = proto_register(&ddp_proto, 0); ++ if (rc) + goto out; + +- (void)sock_register(&atalk_family_ops); ++ rc = sock_register(&atalk_family_ops); ++ if (rc) ++ goto out_proto; ++ + ddp_dl = register_snap_client(ddp_snap_id, atalk_rcv); + if (!ddp_dl) + printk(atalk_err_snap); +@@ -1925,12 +1929,33 @@ static int __init atalk_init(void) + dev_add_pack(<alk_packet_type); + dev_add_pack(&ppptalk_packet_type); + +- register_netdevice_notifier(&ddp_notifier); ++ rc = register_netdevice_notifier(&ddp_notifier); ++ if (rc) ++ goto out_sock; ++ + aarp_proto_init(); +- atalk_proc_init(); +- atalk_register_sysctl(); ++ rc = atalk_proc_init(); ++ if (rc) ++ goto out_aarp; ++ ++ rc = atalk_register_sysctl(); ++ if (rc) ++ goto out_proc; + out: + return rc; ++out_proc: ++ atalk_proc_exit(); ++out_aarp: ++ aarp_cleanup_module(); ++ unregister_netdevice_notifier(&ddp_notifier); ++out_sock: ++ dev_remove_pack(&ppptalk_packet_type); ++ dev_remove_pack(<alk_packet_type); ++ unregister_snap_client(ddp_dl); ++ sock_unregister(PF_APPLETALK); ++out_proto: ++ proto_unregister(&ddp_proto); ++ goto out; + } + module_init(atalk_init); + +diff --git a/net/appletalk/sysctl_net_atalk.c b/net/appletalk/sysctl_net_atalk.c +index ebb864361f7a..4e6042e0fcac 100644 +--- a/net/appletalk/sysctl_net_atalk.c ++++ b/net/appletalk/sysctl_net_atalk.c +@@ -44,9 +44,12 @@ static struct ctl_table atalk_table[] = { + + static struct ctl_table_header *atalk_table_header; + +-void atalk_register_sysctl(void) ++int __init atalk_register_sysctl(void) + { + atalk_table_header = register_net_sysctl(&init_net, "net/appletalk", atalk_table); ++ if (!atalk_table_header) ++ return -ENOMEM; ++ return 0; + } + + void atalk_unregister_sysctl(void) +diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c +index f5c11bbe27db..5a89a4ac86ef 100644 +--- a/net/bridge/netfilter/ebtables.c ++++ b/net/bridge/netfilter/ebtables.c +@@ -2031,7 +2031,9 @@ static int ebt_size_mwt(struct compat_ebt_entry_mwt *match32, + if (match_kern) + match_kern->match_size = ret; + +- WARN_ON(type == EBT_COMPAT_TARGET && size_left); ++ if (WARN_ON(type == EBT_COMPAT_TARGET && size_left)) ++ return -EINVAL; ++ + match32 = (struct compat_ebt_entry_mwt *) buf; + } + +@@ -2087,6 +2089,15 @@ static int size_entry_mwt(struct ebt_entry *entry, const unsigned char *base, + * + * offsets are relative to beginning of struct ebt_entry (i.e., 0). + */ ++ for (i = 0; i < 4 ; ++i) { ++ if (offsets[i] >= *total) ++ return -EINVAL; ++ if (i == 0) ++ continue; ++ if (offsets[i-1] > offsets[i]) ++ return -EINVAL; ++ } ++ + for (i = 0, j = 1 ; j < 4 ; j++, i++) { + struct compat_ebt_entry_mwt *match32; + unsigned int size; +diff --git a/net/core/Makefile b/net/core/Makefile +old mode 100644 +new mode 100755 +index d6508c2ddca5..d3090779e75c +--- a/net/core/Makefile ++++ b/net/core/Makefile +@@ -27,3 +27,7 @@ obj-$(CONFIG_LWTUNNEL) += lwtunnel.o + obj-$(CONFIG_DST_CACHE) += dst_cache.o + obj-$(CONFIG_HWBM) += hwbm.o + obj-$(CONFIG_NET_DEVLINK) += devlink.o ++ ++ifeq ($(CONFIG_SS_SWTOE), y) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++endif +diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c +index 6e4f34721080..3333693d8052 100644 +--- a/net/core/net-sysfs.c ++++ b/net/core/net-sysfs.c +@@ -1380,6 +1380,9 @@ static int register_queue_kobjects(struct net_device *dev) + error: + netdev_queue_update_kobjects(dev, txq, 0); + net_rx_queue_update_kobjects(dev, rxq, 0); ++#ifdef CONFIG_SYSFS ++ kset_unregister(dev->queues_kset); ++#endif + return error; + } + +diff --git a/net/core/skbuff.c b/net/core/skbuff.c +index a64515583bc1..4cbb1fb28997 100644 +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -2423,20 +2423,27 @@ EXPORT_SYMBOL(skb_queue_purge); + /** + * skb_rbtree_purge - empty a skb rbtree + * @root: root of the rbtree to empty ++ * Return value: the sum of truesizes of all purged skbs. + * + * Delete all buffers on an &sk_buff rbtree. Each buffer is removed from + * the list and one reference dropped. This function does not take + * any lock. Synchronization should be handled by the caller (e.g., TCP + * out-of-order queue is protected by the socket lock). + */ +-void skb_rbtree_purge(struct rb_root *root) ++unsigned int skb_rbtree_purge(struct rb_root *root) + { +- struct sk_buff *skb, *next; ++ struct rb_node *p = rb_first(root); ++ unsigned int sum = 0; + +- rbtree_postorder_for_each_entry_safe(skb, next, root, rbnode) +- kfree_skb(skb); ++ while (p) { ++ struct sk_buff *skb = rb_entry(p, struct sk_buff, rbnode); + +- *root = RB_ROOT; ++ p = rb_next(p); ++ rb_erase(&skb->rbnode, root); ++ sum += skb->truesize; ++ kfree_skb(skb); ++ } ++ return sum; + } + + /** +diff --git a/net/core/sock.c b/net/core/sock.c +old mode 100644 +new mode 100755 +index e3b60460dc9c..0efe88a83c84 +--- a/net/core/sock.c ++++ b/net/core/sock.c +@@ -141,6 +141,10 @@ + #include + #include + ++#ifdef CONFIG_SS_SWTOE_TCP ++#include "mdrv_swtoe.h" ++#endif ++ + static DEFINE_MUTEX(proto_list_mutex); + static LIST_HEAD(proto_list); + +@@ -661,6 +665,10 @@ int sock_setsockopt(struct socket *sock, int level, int optname, + struct linger ling; + int ret = 0; + ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++#endif ++ + /* + * Options without arguments + */ +@@ -1001,6 +1009,13 @@ set_rcvbuf: + if (val == 1) + dst_negative_advice(sk); + break; ++/* ++#ifdef CONFIG_SS_SWTOE_TCP /// todo ++ case SO_SS_SWTOE: ++ sk->ss_swtoe = 1; ++ break; ++#endif ++*/ + default: + ret = -ENOPROTOOPT; + break; +@@ -2476,6 +2491,13 @@ void sock_init_data(struct socket *sock, struct sock *sk) + sk->sk_max_pacing_rate = ~0U; + sk->sk_pacing_rate = ~0U; + sk->sk_incoming_cpu = -1; ++ ++#ifdef CONFIG_SS_SWTOE_TCP /// done ++ sk->ss_swtoe = 0; ++ sk->ss_swtoe_cnx = DRV_SWTOE_CNX_INVALID; ++ sk->ss_swtoe_blk = 1; ++#endif ++ + /* + * Before updating sk_refcnt, we must commit prior changes to memory + * (Documentation/RCU/rculist_nulls.txt for details) +diff --git a/net/ieee802154/6lowpan/6lowpan_i.h b/net/ieee802154/6lowpan/6lowpan_i.h +index 5ac778962e4e..3bfec472734a 100644 +--- a/net/ieee802154/6lowpan/6lowpan_i.h ++++ b/net/ieee802154/6lowpan/6lowpan_i.h +@@ -16,37 +16,19 @@ typedef unsigned __bitwise__ lowpan_rx_result; + #define LOWPAN_DISPATCH_FRAG1 0xc0 + #define LOWPAN_DISPATCH_FRAGN 0xe0 + +-struct lowpan_create_arg { ++struct frag_lowpan_compare_key { + u16 tag; + u16 d_size; +- const struct ieee802154_addr *src; +- const struct ieee802154_addr *dst; ++ const struct ieee802154_addr src; ++ const struct ieee802154_addr dst; + }; + +-/* Equivalent of ipv4 struct ip ++/* Equivalent of ipv4 struct ipq + */ + struct lowpan_frag_queue { + struct inet_frag_queue q; +- +- u16 tag; +- u16 d_size; +- struct ieee802154_addr saddr; +- struct ieee802154_addr daddr; + }; + +-static inline u32 ieee802154_addr_hash(const struct ieee802154_addr *a) +-{ +- switch (a->mode) { +- case IEEE802154_ADDR_LONG: +- return (((__force u64)a->extended_addr) >> 32) ^ +- (((__force u64)a->extended_addr) & 0xffffffff); +- case IEEE802154_ADDR_SHORT: +- return (__force u32)(a->short_addr + (a->pan_id << 16)); +- default: +- return 0; +- } +-} +- + int lowpan_frag_rcv(struct sk_buff *skb, const u8 frag_type); + void lowpan_net_frag_exit(void); + int lowpan_net_frag_init(void); +diff --git a/net/ieee802154/6lowpan/reassembly.c b/net/ieee802154/6lowpan/reassembly.c +index f85b08baff16..c9de21000571 100644 +--- a/net/ieee802154/6lowpan/reassembly.c ++++ b/net/ieee802154/6lowpan/reassembly.c +@@ -37,47 +37,15 @@ static struct inet_frags lowpan_frags; + static int lowpan_frag_reasm(struct lowpan_frag_queue *fq, + struct sk_buff *prev, struct net_device *ldev); + +-static unsigned int lowpan_hash_frag(u16 tag, u16 d_size, +- const struct ieee802154_addr *saddr, +- const struct ieee802154_addr *daddr) +-{ +- net_get_random_once(&lowpan_frags.rnd, sizeof(lowpan_frags.rnd)); +- return jhash_3words(ieee802154_addr_hash(saddr), +- ieee802154_addr_hash(daddr), +- (__force u32)(tag + (d_size << 16)), +- lowpan_frags.rnd); +-} +- +-static unsigned int lowpan_hashfn(const struct inet_frag_queue *q) +-{ +- const struct lowpan_frag_queue *fq; +- +- fq = container_of(q, struct lowpan_frag_queue, q); +- return lowpan_hash_frag(fq->tag, fq->d_size, &fq->saddr, &fq->daddr); +-} +- +-static bool lowpan_frag_match(const struct inet_frag_queue *q, const void *a) +-{ +- const struct lowpan_frag_queue *fq; +- const struct lowpan_create_arg *arg = a; +- +- fq = container_of(q, struct lowpan_frag_queue, q); +- return fq->tag == arg->tag && fq->d_size == arg->d_size && +- ieee802154_addr_equal(&fq->saddr, arg->src) && +- ieee802154_addr_equal(&fq->daddr, arg->dst); +-} +- + static void lowpan_frag_init(struct inet_frag_queue *q, const void *a) + { +- const struct lowpan_create_arg *arg = a; ++ const struct frag_lowpan_compare_key *key = a; + struct lowpan_frag_queue *fq; + + fq = container_of(q, struct lowpan_frag_queue, q); + +- fq->tag = arg->tag; +- fq->d_size = arg->d_size; +- fq->saddr = *arg->src; +- fq->daddr = *arg->dst; ++ BUILD_BUG_ON(sizeof(*key) > sizeof(q->key)); ++ memcpy(&q->key, key, sizeof(*key)); + } + + static void lowpan_frag_expire(unsigned long data) +@@ -93,10 +61,10 @@ static void lowpan_frag_expire(unsigned long data) + if (fq->q.flags & INET_FRAG_COMPLETE) + goto out; + +- inet_frag_kill(&fq->q, &lowpan_frags); ++ inet_frag_kill(&fq->q); + out: + spin_unlock(&fq->q.lock); +- inet_frag_put(&fq->q, &lowpan_frags); ++ inet_frag_put(&fq->q); + } + + static inline struct lowpan_frag_queue * +@@ -104,21 +72,17 @@ fq_find(struct net *net, const struct lowpan_802154_cb *cb, + const struct ieee802154_addr *src, + const struct ieee802154_addr *dst) + { +- struct inet_frag_queue *q; +- struct lowpan_create_arg arg; +- unsigned int hash; + struct netns_ieee802154_lowpan *ieee802154_lowpan = + net_ieee802154_lowpan(net); ++ struct frag_lowpan_compare_key key = { ++ .tag = cb->d_tag, ++ .d_size = cb->d_size, ++ .src = *src, ++ .dst = *dst, ++ }; ++ struct inet_frag_queue *q; + +- arg.tag = cb->d_tag; +- arg.d_size = cb->d_size; +- arg.src = src; +- arg.dst = dst; +- +- hash = lowpan_hash_frag(cb->d_tag, cb->d_size, src, dst); +- +- q = inet_frag_find(&ieee802154_lowpan->frags, +- &lowpan_frags, &arg, hash); ++ q = inet_frag_find(&ieee802154_lowpan->frags, &key); + if (IS_ERR_OR_NULL(q)) { + inet_frag_maybe_warn_overflow(q, pr_fmt()); + return NULL; +@@ -229,7 +193,7 @@ static int lowpan_frag_reasm(struct lowpan_frag_queue *fq, struct sk_buff *prev, + struct sk_buff *fp, *head = fq->q.fragments; + int sum_truesize; + +- inet_frag_kill(&fq->q, &lowpan_frags); ++ inet_frag_kill(&fq->q); + + /* Make the one we just received the head. */ + if (prev) { +@@ -437,7 +401,7 @@ int lowpan_frag_rcv(struct sk_buff *skb, u8 frag_type) + ret = lowpan_frag_queue(fq, skb, frag_type); + spin_unlock(&fq->q.lock); + +- inet_frag_put(&fq->q, &lowpan_frags); ++ inet_frag_put(&fq->q); + return ret; + } + +@@ -447,24 +411,22 @@ err: + } + + #ifdef CONFIG_SYSCTL +-static int zero; + + static struct ctl_table lowpan_frags_ns_ctl_table[] = { + { + .procname = "6lowpanfrag_high_thresh", + .data = &init_net.ieee802154_lowpan.frags.high_thresh, +- .maxlen = sizeof(int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, ++ .proc_handler = proc_doulongvec_minmax, + .extra1 = &init_net.ieee802154_lowpan.frags.low_thresh + }, + { + .procname = "6lowpanfrag_low_thresh", + .data = &init_net.ieee802154_lowpan.frags.low_thresh, +- .maxlen = sizeof(int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, +- .extra1 = &zero, ++ .proc_handler = proc_doulongvec_minmax, + .extra2 = &init_net.ieee802154_lowpan.frags.high_thresh + }, + { +@@ -580,14 +542,20 @@ static int __net_init lowpan_frags_init_net(struct net *net) + { + struct netns_ieee802154_lowpan *ieee802154_lowpan = + net_ieee802154_lowpan(net); ++ int res; + + ieee802154_lowpan->frags.high_thresh = IPV6_FRAG_HIGH_THRESH; + ieee802154_lowpan->frags.low_thresh = IPV6_FRAG_LOW_THRESH; + ieee802154_lowpan->frags.timeout = IPV6_FRAG_TIMEOUT; ++ ieee802154_lowpan->frags.f = &lowpan_frags; + +- inet_frags_init_net(&ieee802154_lowpan->frags); +- +- return lowpan_frags_ns_sysctl_register(net); ++ res = inet_frags_init_net(&ieee802154_lowpan->frags); ++ if (res < 0) ++ return res; ++ res = lowpan_frags_ns_sysctl_register(net); ++ if (res < 0) ++ inet_frags_exit_net(&ieee802154_lowpan->frags); ++ return res; + } + + static void __net_exit lowpan_frags_exit_net(struct net *net) +@@ -596,7 +564,7 @@ static void __net_exit lowpan_frags_exit_net(struct net *net) + net_ieee802154_lowpan(net); + + lowpan_frags_ns_sysctl_unregister(net); +- inet_frags_exit_net(&ieee802154_lowpan->frags, &lowpan_frags); ++ inet_frags_exit_net(&ieee802154_lowpan->frags); + } + + static struct pernet_operations lowpan_frags_ops = { +@@ -604,32 +572,63 @@ static struct pernet_operations lowpan_frags_ops = { + .exit = lowpan_frags_exit_net, + }; + +-int __init lowpan_net_frag_init(void) ++static u32 lowpan_key_hashfn(const void *data, u32 len, u32 seed) + { +- int ret; ++ return jhash2(data, ++ sizeof(struct frag_lowpan_compare_key) / sizeof(u32), seed); ++} + +- ret = lowpan_frags_sysctl_register(); +- if (ret) +- return ret; ++static u32 lowpan_obj_hashfn(const void *data, u32 len, u32 seed) ++{ ++ const struct inet_frag_queue *fq = data; + +- ret = register_pernet_subsys(&lowpan_frags_ops); +- if (ret) +- goto err_pernet; ++ return jhash2((const u32 *)&fq->key, ++ sizeof(struct frag_lowpan_compare_key) / sizeof(u32), seed); ++} ++ ++static int lowpan_obj_cmpfn(struct rhashtable_compare_arg *arg, const void *ptr) ++{ ++ const struct frag_lowpan_compare_key *key = arg->key; ++ const struct inet_frag_queue *fq = ptr; ++ ++ return !!memcmp(&fq->key, key, sizeof(*key)); ++} ++ ++static const struct rhashtable_params lowpan_rhash_params = { ++ .head_offset = offsetof(struct inet_frag_queue, node), ++ .hashfn = lowpan_key_hashfn, ++ .obj_hashfn = lowpan_obj_hashfn, ++ .obj_cmpfn = lowpan_obj_cmpfn, ++ .automatic_shrinking = true, ++}; ++ ++int __init lowpan_net_frag_init(void) ++{ ++ int ret; + +- lowpan_frags.hashfn = lowpan_hashfn; + lowpan_frags.constructor = lowpan_frag_init; + lowpan_frags.destructor = NULL; + lowpan_frags.qsize = sizeof(struct frag_queue); +- lowpan_frags.match = lowpan_frag_match; + lowpan_frags.frag_expire = lowpan_frag_expire; + lowpan_frags.frags_cache_name = lowpan_frags_cache_name; ++ lowpan_frags.rhash_params = lowpan_rhash_params; + ret = inet_frags_init(&lowpan_frags); + if (ret) +- goto err_pernet; ++ goto out; + ++ ret = lowpan_frags_sysctl_register(); ++ if (ret) ++ goto err_sysctl; ++ ++ ret = register_pernet_subsys(&lowpan_frags_ops); ++ if (ret) ++ goto err_pernet; ++out: + return ret; + err_pernet: + lowpan_frags_sysctl_unregister(); ++err_sysctl: ++ inet_frags_fini(&lowpan_frags); + return ret; + } + +diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile +old mode 100644 +new mode 100755 +index bc6a6c8b9bcd..7df5f872deed +--- a/net/ipv4/Makefile ++++ b/net/ipv4/Makefile +@@ -61,3 +61,7 @@ obj-$(CONFIG_NETLABEL) += cipso_ipv4.o + + obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ + xfrm4_output.o xfrm4_protocol.o ++ ++ifeq ($(CONFIG_SS_SWTOE), y) ++EXTRA_CFLAGS += -Idrivers/sstar/include ++endif +\ No newline at end of file +diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c +old mode 100644 +new mode 100755 +index b5116ec31757..53b097d98b1f +--- a/net/ipv4/af_inet.c ++++ b/net/ipv4/af_inet.c +@@ -121,6 +121,9 @@ + #endif + #include + ++#ifdef CONFIG_SS_SWTOE_TCP ++#include "mdrv_swtoe.h" ++#endif + + /* The inetsw table contains everything that inet_create needs to + * build a new socket. +@@ -223,7 +226,6 @@ int inet_listen(struct socket *sock, int backlog) + fastopen_queue_tune(sk, backlog); + tcp_fastopen_init_key_once(true); + } +- + err = inet_csk_listen_start(sk, backlog); + if (err) + goto out; +@@ -237,6 +239,107 @@ out: + } + EXPORT_SYMBOL(inet_listen); + ++#ifdef CONFIG_SS_SWTOE_TCP ++extern struct sock* _swtoe_create_sock(const struct sock *sk, drv_swtoe_lstn_data* lstn_data); ++int _inet_swtoe_cb(int cnx, int reason, void* reason_data, void* cb_data); ++ ++static int _inet_swtoe_cnx_ok(struct socket* sock, int reason, drv_swtoe_glue_cnx_data* p_cnx_data) ++{ ++ struct sock* sk = sock->sk; ++ struct inet_sock* inet = inet_sk(sk); ++ ++ inet->inet_daddr = p_cnx_data->daddr; ++ inet->inet_dport = p_cnx_data->dport; ++ inet->inet_saddr = p_cnx_data->saddr; ++ inet->inet_sport = p_cnx_data->sport; ++ /// what is inet_rcv_saddr for? ++ inet->inet_rcv_saddr = p_cnx_data->saddr; ++ ++/* ++ printk("[%s][%d] (daddr, dport) = (0x%08x, 0x%04x, %d)\n", __FUNCTION__, __LINE__, inet->inet_daddr, inet->inet_dport, inet->inet_dport); ++ printk("[%s][%d] (saddr, sport) = (0x%08x, 0x%04x, %d)\n", __FUNCTION__, __LINE__, inet->inet_saddr, inet->inet_sport, inet->inet_sport); ++ printk("[%s][%d] (saddr) = (0x%08x)\n", __FUNCTION__, __LINE__, inet->inet_rcv_saddr); ++ printk("[%s][%d] sk_state = %d\n", __FUNCTION__, __LINE__, sk->sk_state); ++*/ ++ if (!sock_flag(sk, SOCK_DEAD)) ++ { ++ tcp_set_state(sk, TCP_ESTABLISHED); ++ // printk("[%s][%d] sk_state = %d\n", __FUNCTION__, __LINE__, sk->sk_state); ++ sk->sk_state_change(sk); ++ sk_wake_async(sk, SOCK_WAKE_IO, POLL_OUT); ++ } ++ return 0; ++} ++ ++static int _inet_swtoe_cnx_lstn(struct socket* sock) ++{ ++ struct sock* sk = sock->sk; ++ drv_swtoe_lstn_data lstn_data; ++ int ncnx; ++ struct sock *newsk; ++ ++ drv_swtoe_lstn_remove(sk->ss_swtoe_cnx, &lstn_data); ++ newsk = _swtoe_create_sock(sk, &lstn_data); ++ ++ if (drv_swtoe_clone(sk->ss_swtoe_cnx, &ncnx, &lstn_data)) ++ { ++ printk("[%s][%d] clone connection fail. cnx = %d\n", __FUNCTION__, __LINE__, sk->ss_swtoe_cnx); ++ } ++ else ++ { ++ struct request_sock *req; ++ ++ newsk->ss_swtoe = 1; ++ newsk->ss_swtoe_cnx = ncnx; ++ drv_swtoe_glue_req(newsk->ss_swtoe_cnx, _inet_swtoe_cb, (void*)newsk); ++ req = kmalloc(sizeof(struct request_sock), GFP_KERNEL); ++ inet_csk_reqsk_queue_add(sk, req, newsk); ++ } ++ return 0; ++} ++ ++int _inet_swtoe_cb(int cnx, int reason, void* reason_data, void* cb_data) ++{ ++ struct socket* sock = (struct socket*)cb_data; ++ struct sock* sk = sock->sk; ++ ++ if (!sk->ss_swtoe) ++ { ++ return -1; ++ } ++ if ((SOCK_STREAM != sock->type) || (IPPROTO_TCP != sk->sk_protocol)) ++ { ++ return -1; ++ } ++ switch (reason) ++ { ++ case DRV_SWTOE_GLUE_RCOM: ++ sk->sk_data_ready(sk); ++ break; ++ case DRV_SWTOE_GLUE_LSTN_RESP: ++ _inet_swtoe_cnx_lstn(sock); ++ sk->sk_data_ready(sk); ++ break; ++ case DRV_SWTOE_GLUE_CNX_OK: ++ _inet_swtoe_cnx_ok(sock, reason, (drv_swtoe_glue_cnx_data*)reason_data); ++ break; ++ case DRV_SWTOE_GLUE_CNX_FAIL: ++ // how to do it ++ break; ++ case DRV_SWTOE_GLUE_CLS_RESP: ++ tcp_set_state(sk, TCP_CLOSE); ++ sk->ss_swtoe = 0; ++ sk->ss_swtoe_cnx = DRV_SWTOE_CNX_INVALID; ++ sk->ss_swtoe_blk = 0; ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(_inet_swtoe_cb); ++#endif ++ + /* + * Create an inet socket. + */ +@@ -377,6 +480,25 @@ lookup_protocol: + if (err) + sk_common_release(sk); + } ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete due to not CB, should be queue ++ if ((SOCK_STREAM == sock->type) && (IPPROTO_TCP == protocol)) ++ { ++ int cnx_id; ++ if (0 == drv_swtoe_create(DRV_SWTOE_PROT_TCP, &cnx_id)) ++ { ++ sk->ss_swtoe_cnx = cnx_id; ++ sk->ss_swtoe = 1; ++ drv_swtoe_glue_req(sk->ss_swtoe_cnx, _inet_swtoe_cb, (void*)sock); /// todo : how to deal with CB? ++ } ++ else ++ { ++ err = -ENOSR; ++ printk("[%s][%d] create ss_swtoe_cnx fail\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ } ++#endif ++ + out: + return err; + out_rcu_unlock: +@@ -418,6 +540,58 @@ int inet_release(struct socket *sock) + } + EXPORT_SYMBOL(inet_release); + ++ ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER ++#if 1 ++static long inet_bind_wait(struct sock *sk) ++{ ++ DEFINE_WAIT_FUNC(wait, woken_wake_function); ++ long timeo = HZ/2; ++ ++ add_wait_queue(sk_sleep(sk), &wait); ++ ++ while (0 < drv_swtoe_bind_status(sk->ss_swtoe_cnx)) ++ { ++ timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, timeo); ++ if (signal_pending(current) || !timeo) ++ break; ++ } ++ remove_wait_queue(sk_sleep(sk), &wait); ++ return timeo; ++} ++#else ++static int inet_bind_wait(struct sock *sk) ++{ ++ DEFINE_WAIT(wait); ++ int err; ++ long timeo = HZ; // MAX_SCHEDULE_TIMEOUT; ++ ++ for (;;) { ++ prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE); ++ if (0 < drv_swtoe_bind_status(sk->ss_swtoe_cnx)) ++ { ++ timeo = schedule_timeout(timeo); ++ } ++ sched_annotate_sleep(); ++ err = 0; ++ if (!drv_swtoe_bind_status(sk->ss_swtoe_cnx)) ++ { ++ break; ++ } ++ err = -EINVAL; ++ err = sock_intr_errno(timeo); ++ if (signal_pending(current)) ++ break; ++ err = -EAGAIN; ++ if (!timeo) ++ break; ++ } ++ finish_wait(sk_sleep(sk), &wait); ++ return err; ++} ++#endif ++#endif ++ + int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) + { + struct sockaddr_in *addr = (struct sockaddr_in *)uaddr; +@@ -448,6 +622,19 @@ int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) + goto out; + } + ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER ++ if (sk->ss_swtoe) ++ { ++ if (drv_swtoe_bind(sk->ss_swtoe_cnx, uaddr)) ++ { ++ printk("[%s][%d] swtoe bind IPC fail %d\n", __FUNCTION__, __LINE__, sk->ss_swtoe_cnx); ++ return -EINVAL; ++ } ++ inet_bind_wait(sk); ++ return (drv_swtoe_bind_status(sk->ss_swtoe_cnx)) ? -EINVAL : 0; ++ } ++#endif ++ + tb_id = l3mdev_fib_table_by_index(net, sk->sk_bound_dev_if) ? : tb_id; + chk_addr_ret = inet_addr_type_table(net, addr->sin_addr.s_addr, tb_id); + +@@ -590,7 +777,12 @@ int __inet_stream_connect(struct socket *sock, struct sockaddr *uaddr, + err = -EISCONN; + if (sk->sk_state != TCP_CLOSE) + goto out; +- ++#ifdef CONFIG_SS_SWTOE_TCP_CLIENT ++ if (sk->ss_swtoe) ++ { ++ sk->ss_swtoe_blk = (flags & O_NONBLOCK)? 0 : 1; ++ } ++#endif + err = sk->sk_prot->connect(sk, uaddr, addr_len); + if (err < 0) + goto out; +@@ -607,6 +799,19 @@ int __inet_stream_connect(struct socket *sock, struct sockaddr *uaddr, + + timeo = sock_sndtimeo(sk, flags & O_NONBLOCK); + ++#if 0 /// todo : unnecessary at this first stage, but do it later ++#ifdef CONFIG_SS_SWTOE_TCP_CLIENT ++ if (sk->ss_swtoe) ++ { ++ if (drv_swtoe_connect_timeo(sk->ss_swtoe_cnx, timeo)) ++ { ++ printk("[%s][%d] drv_swtoe_connect_timeo fail\n", __FUNCTION__, __LINE__); ++ goto out; ++ } ++ } ++#endif ++#endif ++ + if ((1 << sk->sk_state) & (TCPF_SYN_SENT | TCPF_SYN_RECV)) { + int writebias = (sk->sk_protocol == IPPROTO_TCP) && + tcp_sk(sk)->fastopen_req && +@@ -700,6 +905,12 @@ int inet_getname(struct socket *sock, struct sockaddr *uaddr, + DECLARE_SOCKADDR(struct sockaddr_in *, sin, uaddr); + + sin->sin_family = AF_INET; ++ ++/* ++should do nothing if below state/variables are correct ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++#endif ++*/ + if (peer) { + if (!inet->inet_dport || + (((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_SYN_SENT)) && +diff --git a/net/ipv4/cipso_ipv4.c b/net/ipv4/cipso_ipv4.c +index 972353cd1778..65a15889d432 100644 +--- a/net/ipv4/cipso_ipv4.c ++++ b/net/ipv4/cipso_ipv4.c +@@ -1523,9 +1523,17 @@ unsigned char *cipso_v4_optptr(const struct sk_buff *skb) + int taglen; + + for (optlen = iph->ihl*4 - sizeof(struct iphdr); optlen > 0; ) { +- if (optptr[0] == IPOPT_CIPSO) ++ switch (optptr[0]) { ++ case IPOPT_CIPSO: + return optptr; +- taglen = optptr[1]; ++ case IPOPT_END: ++ return NULL; ++ case IPOPT_NOOP: ++ taglen = 1; ++ break; ++ default: ++ taglen = optptr[1]; ++ } + optlen -= taglen; + optptr += taglen; + } +diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c +old mode 100644 +new mode 100755 +index d1cab49393e2..e6392da22aaa +--- a/net/ipv4/inet_connection_sock.c ++++ b/net/ipv4/inet_connection_sock.c +@@ -26,6 +26,10 @@ + #include + #include + ++#ifdef CONFIG_SS_SWTOE_TCP ++#include "mdrv_swtoe.h" ++#endif ++ + #ifdef INET_CSK_DEBUG + const char inet_csk_timer_bug_msg[] = "inet_csk BUG: unknown timer value\n"; + EXPORT_SYMBOL(inet_csk_timer_bug_msg); +@@ -106,6 +110,13 @@ int inet_csk_get_port(struct sock *sk, unsigned short snum) + kuid_t uid = sock_i_uid(sk); + u32 remaining, offset; + ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++#endif ++ + if (port) { + have_port: + head = &hinfo->bhash[inet_bhashfn(net, port, +@@ -292,6 +303,221 @@ static int inet_csk_wait_for_connect(struct sock *sk, long timeo) + return err; + } + ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER ++// struct sock* tcp_create_openreq_child(const struct sock *sk, drv_swtoe_lstn_data* lstn_data) ++// + ++// struct sock *tcp_v4_syn_recv_sock(const struct sock *sk, struct sk_buff *skb, ++struct sock* _swtoe_create_sock(const struct sock *sk, drv_swtoe_lstn_data* lstn_data) ++{ ++ struct request_sock *req = inet_reqsk(sk); ++ struct sock *newsk = inet_csk_clone_lock(sk, req, GFP_ATOMIC); ++ ++ // if (!newsk) ++ // return NULL; ++ ++ if (newsk) { ++ const struct inet_request_sock *ireq = inet_rsk(req); ++ struct tcp_request_sock *treq = tcp_rsk(req); ++ struct inet_connection_sock *newicsk = inet_csk(newsk); ++ struct tcp_sock *newtp = tcp_sk(newsk); ++ struct inet_sock *newinet; ++ ++ /* Now setup tcp_sock */ ++ newtp->pred_flags = 0; ++ ++ newtp->rcv_wup = newtp->copied_seq = ++ newtp->rcv_nxt = treq->rcv_isn + 1; ++ newtp->segs_in = 1; ++ ++ newtp->snd_sml = newtp->snd_una = ++ newtp->snd_nxt = newtp->snd_up = treq->snt_isn + 1; ++ ++ tcp_prequeue_init(newtp); ++ INIT_LIST_HEAD(&newtp->tsq_node); ++ ++ tcp_init_wl(newtp, treq->rcv_isn); ++ ++ newtp->srtt_us = 0; ++ newtp->mdev_us = jiffies_to_usecs(TCP_TIMEOUT_INIT); ++ minmax_reset(&newtp->rtt_min, tcp_time_stamp, ~0U); ++ newicsk->icsk_rto = TCP_TIMEOUT_INIT; ++ newicsk->icsk_ack.lrcvtime = tcp_time_stamp; ++ ++ newtp->packets_out = 0; ++ newtp->retrans_out = 0; ++ newtp->sacked_out = 0; ++ newtp->fackets_out = 0; ++ newtp->snd_ssthresh = TCP_INFINITE_SSTHRESH; ++ tcp_enable_early_retrans(newtp); ++ newtp->tlp_high_seq = 0; ++ newtp->lsndtime = treq->snt_synack.stamp_jiffies; ++ newsk->sk_txhash = treq->txhash; ++ newtp->last_oow_ack_time = 0; ++ newtp->total_retrans = req->num_retrans; ++ ++ /* So many TCP implementations out there (incorrectly) count the ++ * initial SYN frame in their delayed-ACK and congestion control ++ * algorithms that we must have the following bandaid to talk ++ * efficiently to them. -DaveM ++ */ ++ newtp->snd_cwnd = TCP_INIT_CWND; ++ newtp->snd_cwnd_cnt = 0; ++ ++ /* There's a bubble in the pipe until at least the first ACK. */ ++ newtp->app_limited = ~0U; ++ ++ tcp_init_xmit_timers(newsk); ++ newtp->write_seq = newtp->pushed_seq = treq->snt_isn + 1; ++ ++ newtp->rx_opt.saw_tstamp = 0; ++ ++ newtp->rx_opt.dsack = 0; ++ newtp->rx_opt.num_sacks = 0; ++ ++ newtp->urg_data = 0; ++ ++ if (sock_flag(newsk, SOCK_KEEPOPEN)) ++ inet_csk_reset_keepalive_timer(newsk, ++ keepalive_time_when(newtp)); ++ ++ newtp->rx_opt.tstamp_ok = ireq->tstamp_ok; ++ if ((newtp->rx_opt.sack_ok = ireq->sack_ok) != 0) { ++ if (sysctl_tcp_fack) ++ tcp_enable_fack(newtp); ++ } ++ newtp->window_clamp = req->rsk_window_clamp; ++ newtp->rcv_ssthresh = req->rsk_rcv_wnd; ++ newtp->rcv_wnd = req->rsk_rcv_wnd; ++ newtp->rx_opt.wscale_ok = ireq->wscale_ok; ++ if (newtp->rx_opt.wscale_ok) { ++ newtp->rx_opt.snd_wscale = ireq->snd_wscale; ++ newtp->rx_opt.rcv_wscale = ireq->rcv_wscale; ++ } else { ++ newtp->rx_opt.snd_wscale = newtp->rx_opt.rcv_wscale = 0; ++ newtp->window_clamp = min(newtp->window_clamp, 65535U); ++ } ++#if 0 ++ newtp->snd_wnd = (ntohs(tcp_hdr(skb)->window) << ++ newtp->rx_opt.snd_wscale); ++#else ++ newtp->snd_wnd = 0; ++#endif ++ newtp->max_window = newtp->snd_wnd; ++ ++ if (newtp->rx_opt.tstamp_ok) { ++ newtp->rx_opt.ts_recent = req->ts_recent; ++ newtp->rx_opt.ts_recent_stamp = get_seconds(); ++ newtp->tcp_header_len = sizeof(struct tcphdr) + TCPOLEN_TSTAMP_ALIGNED; ++ } else { ++ newtp->rx_opt.ts_recent_stamp = 0; ++ newtp->tcp_header_len = sizeof(struct tcphdr); ++ } ++ newtp->tsoffset = 0; ++#ifdef CONFIG_TCP_MD5SIG ++ newtp->md5sig_info = NULL; /*XXX*/ ++ if (newtp->af_specific->md5_lookup(sk, newsk)) ++ newtp->tcp_header_len += TCPOLEN_MD5SIG_ALIGNED; ++#endif ++/* ++ if (skb->len >= TCP_MSS_DEFAULT + newtp->tcp_header_len) ++ newicsk->icsk_ack.last_seg_size = skb->len - newtp->tcp_header_len; ++*/ ++ newtp->rx_opt.mss_clamp = req->mss; ++ ++ newtp->ecn_flags = inet_rsk(req)->ecn_ok ? TCP_ECN_OK : 0; // tcp_ecn_openreq_child(newtp, req); ++ ++ newtp->fastopen_req = NULL; ++ newtp->fastopen_rsk = NULL; ++ newtp->syn_data_acked = 0; ++ newtp->rack.mstamp.v64 = 0; ++ newtp->rack.advanced = 0; ++ ++ __TCP_INC_STATS(sock_net(sk), TCP_MIB_PASSIVEOPENS); ++ ++ newsk->sk_gso_type = SKB_GSO_TCPV4; ++ // inet_sk_rx_dst_set(newsk, skb); ++ ++ newtp = tcp_sk(newsk); ++ newinet = inet_sk(newsk); ++ // ireq = inet_rsk(req); ++ sk_daddr_set(newsk, lstn_data->daddr); // sk_daddr_set(newsk, ireq->ir_rmt_addr); ++ sk_rcv_saddr_set(newsk, lstn_data->saddr); // sk_rcv_saddr_set(newsk, ireq->ir_loc_addr); ++ // newsk->sk_bound_dev_if = ireq->ir_iif; ++ newinet->inet_saddr = lstn_data->saddr; // newinet->inet_saddr = ireq->ir_loc_addr; ++ // inet_opt = rcu_dereference(ireq->ireq_opt); ++ // RCU_INIT_POINTER(newinet->inet_opt, inet_opt); ++ // newinet->mc_index = inet_iif(skb); ++ // newinet->mc_ttl = ip_hdr(skb)->ttl; ++ // newinet->rcv_tos = ip_hdr(skb)->tos; ++ inet_csk(newsk)->icsk_ext_hdr_len = 0; ++ // if (inet_opt) ++ // inet_csk(newsk)->icsk_ext_hdr_len = inet_opt->opt.optlen; ++ // newinet->inet_id = newtp->write_seq ^ jiffies; ++ ++#if 0 ++ if (!dst) { ++ dst = inet_csk_route_child_sock(sk, newsk, req); ++ if (!dst) ++ goto put_and_exit; ++ } else { ++ /* syncookie case : see end of cookie_v4_check() */ ++ } ++ sk_setup_caps(newsk, dst); ++ ++ tcp_ca_openreq_child(newsk, dst); ++ ++ tcp_sync_mss(newsk, dst_mtu(dst)); ++ newtp->advmss = dst_metric_advmss(dst); ++ if (tcp_sk(sk)->rx_opt.user_mss && ++ tcp_sk(sk)->rx_opt.user_mss < newtp->advmss) ++ newtp->advmss = tcp_sk(sk)->rx_opt.user_mss; ++#endif ++ ++ tcp_initialize_rcv_mss(newsk); ++ ++#if 0 ++#ifdef CONFIG_TCP_MD5SIG ++ /* Copy over the MD5 key from the original socket */ ++ key = tcp_md5_do_lookup(sk, (union tcp_md5_addr *)&newinet->inet_daddr, ++ AF_INET); ++ if (key) { ++ /* ++ * We're using one, so create a matching key ++ * on the newsk structure. If we fail to get ++ * memory, then we end up not copying the key ++ * across. Shucks. ++ */ ++ tcp_md5_do_add(newsk, (union tcp_md5_addr *)&newinet->inet_daddr, ++ AF_INET, key->key, key->keylen, GFP_ATOMIC); ++ sk_nocaps_add(newsk, NETIF_F_GSO_MASK); ++ } ++#endif ++#endif ++ ++#if 1 ++ __inet_inherit_port(sk, newsk); ++#else ++ if (__inet_inherit_port(sk, newsk) < 0) ++ goto put_and_exit; ++#endif ++ // *own_req = inet_ehash_nolisten(newsk, req_to_sk(req_unhash)); ++#if 0 ++ if (likely(*own_req)) { ++ tcp_move_syn(newtp, req); ++ ireq->ireq_opt = NULL; ++ } else { ++ newinet->inet_opt = NULL; ++ } ++#endif ++ } ++ return newsk; ++} ++EXPORT_SYMBOL(_swtoe_create_sock); ++ ++extern int _inet_swtoe_cb(int cnx, int reason, void* reason_data, void* cb_data); ++ ++#endif ++ + /* + * This will accept the next outstanding connection. + */ +@@ -327,6 +553,12 @@ struct sock *inet_csk_accept(struct sock *sk, int flags, int *err) + } + req = reqsk_queue_remove(queue, sk); + newsk = req->sk; ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER ++ if (sk->ss_swtoe) ++ { ++ drv_swtoe_acpt(sk->ss_swtoe_cnx, newsk->ss_swtoe_cnx); ++ } ++#endif + + if (sk->sk_protocol == IPPROTO_TCP && + tcp_rsk(req)->tfo_listener) { +@@ -345,8 +577,15 @@ struct sock *inet_csk_accept(struct sock *sk, int flags, int *err) + } + out: + release_sock(sk); ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER ++ if (req) ++ { ++ (sk->ss_swtoe) ? kfree(req) : reqsk_put(req); ++ } ++#else + if (req) + reqsk_put(req); ++#endif + return newsk; + out_err: + newsk = NULL; +@@ -750,16 +989,25 @@ int inet_csk_listen_start(struct sock *sk, int backlog) + * after validation is complete. + */ + sk_state_store(sk, TCP_LISTEN); ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER /// not complete ++ if (sk->ss_swtoe) ++ { ++ if (drv_swtoe_lstn_start(sk->ss_swtoe_cnx, backlog)) ++ { ++ printk("[%s][%d] drv_swtoe_listen fail (sk, cnx, backlog) = (0x%08x, %d, %d)\n", __FUNCTION__, __LINE__, (int)sk, sk->ss_swtoe_cnx, backlog); ++ sk->sk_state = TCP_CLOSE; ++ return err; ++ } ++ return 0; ++ } ++#endif + if (!sk->sk_prot->get_port(sk, inet->inet_num)) { + inet->inet_sport = htons(inet->inet_num); +- + sk_dst_reset(sk); + err = sk->sk_prot->hash(sk); +- + if (likely(!err)) + return 0; + } +- + sk->sk_state = TCP_CLOSE; + return err; + } +@@ -841,6 +1089,14 @@ void inet_csk_listen_stop(struct sock *sk) + struct request_sock_queue *queue = &icsk->icsk_accept_queue; + struct request_sock *next, *req; + ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER ++ if (sk->ss_swtoe) ++ { ++ drv_swtoe_lstn_stop(sk->ss_swtoe_cnx); ++ drv_swtoe_lstn_clr(sk->ss_swtoe_cnx); ++ } ++#endif ++ + /* Following specs, it would be better either to send FIN + * (and enter FIN-WAIT-1, it is normal close) + * or to send active reset (abort). +diff --git a/net/ipv4/inet_fragment.c b/net/ipv4/inet_fragment.c +index 631c0d0d7cf8..f673ca01ef7c 100644 +--- a/net/ipv4/inet_fragment.c ++++ b/net/ipv4/inet_fragment.c +@@ -25,12 +25,6 @@ + #include + #include + +-#define INETFRAGS_EVICT_BUCKETS 128 +-#define INETFRAGS_EVICT_MAX 512 +- +-/* don't rebuild inetfrag table with new secret more often than this */ +-#define INETFRAGS_MIN_REBUILD_INTERVAL (5 * HZ) +- + /* Given the OR values of all fragments, apply RFC 3168 5.3 requirements + * Value : 0xff if frame should be dropped. + * 0 or INET_ECN_CE value, to be ORed in to final iph->tos field +@@ -52,154 +46,8 @@ const u8 ip_frag_ecn_table[16] = { + }; + EXPORT_SYMBOL(ip_frag_ecn_table); + +-static unsigned int +-inet_frag_hashfn(const struct inet_frags *f, const struct inet_frag_queue *q) +-{ +- return f->hashfn(q) & (INETFRAGS_HASHSZ - 1); +-} +- +-static bool inet_frag_may_rebuild(struct inet_frags *f) +-{ +- return time_after(jiffies, +- f->last_rebuild_jiffies + INETFRAGS_MIN_REBUILD_INTERVAL); +-} +- +-static void inet_frag_secret_rebuild(struct inet_frags *f) +-{ +- int i; +- +- write_seqlock_bh(&f->rnd_seqlock); +- +- if (!inet_frag_may_rebuild(f)) +- goto out; +- +- get_random_bytes(&f->rnd, sizeof(u32)); +- +- for (i = 0; i < INETFRAGS_HASHSZ; i++) { +- struct inet_frag_bucket *hb; +- struct inet_frag_queue *q; +- struct hlist_node *n; +- +- hb = &f->hash[i]; +- spin_lock(&hb->chain_lock); +- +- hlist_for_each_entry_safe(q, n, &hb->chain, list) { +- unsigned int hval = inet_frag_hashfn(f, q); +- +- if (hval != i) { +- struct inet_frag_bucket *hb_dest; +- +- hlist_del(&q->list); +- +- /* Relink to new hash chain. */ +- hb_dest = &f->hash[hval]; +- +- /* This is the only place where we take +- * another chain_lock while already holding +- * one. As this will not run concurrently, +- * we cannot deadlock on hb_dest lock below, if its +- * already locked it will be released soon since +- * other caller cannot be waiting for hb lock +- * that we've taken above. +- */ +- spin_lock_nested(&hb_dest->chain_lock, +- SINGLE_DEPTH_NESTING); +- hlist_add_head(&q->list, &hb_dest->chain); +- spin_unlock(&hb_dest->chain_lock); +- } +- } +- spin_unlock(&hb->chain_lock); +- } +- +- f->rebuild = false; +- f->last_rebuild_jiffies = jiffies; +-out: +- write_sequnlock_bh(&f->rnd_seqlock); +-} +- +-static bool inet_fragq_should_evict(const struct inet_frag_queue *q) +-{ +- return q->net->low_thresh == 0 || +- frag_mem_limit(q->net) >= q->net->low_thresh; +-} +- +-static unsigned int +-inet_evict_bucket(struct inet_frags *f, struct inet_frag_bucket *hb) +-{ +- struct inet_frag_queue *fq; +- struct hlist_node *n; +- unsigned int evicted = 0; +- HLIST_HEAD(expired); +- +- spin_lock(&hb->chain_lock); +- +- hlist_for_each_entry_safe(fq, n, &hb->chain, list) { +- if (!inet_fragq_should_evict(fq)) +- continue; +- +- if (!del_timer(&fq->timer)) +- continue; +- +- hlist_add_head(&fq->list_evictor, &expired); +- ++evicted; +- } +- +- spin_unlock(&hb->chain_lock); +- +- hlist_for_each_entry_safe(fq, n, &expired, list_evictor) +- f->frag_expire((unsigned long) fq); +- +- return evicted; +-} +- +-static void inet_frag_worker(struct work_struct *work) +-{ +- unsigned int budget = INETFRAGS_EVICT_BUCKETS; +- unsigned int i, evicted = 0; +- struct inet_frags *f; +- +- f = container_of(work, struct inet_frags, frags_work); +- +- BUILD_BUG_ON(INETFRAGS_EVICT_BUCKETS >= INETFRAGS_HASHSZ); +- +- local_bh_disable(); +- +- for (i = ACCESS_ONCE(f->next_bucket); budget; --budget) { +- evicted += inet_evict_bucket(f, &f->hash[i]); +- i = (i + 1) & (INETFRAGS_HASHSZ - 1); +- if (evicted > INETFRAGS_EVICT_MAX) +- break; +- } +- +- f->next_bucket = i; +- +- local_bh_enable(); +- +- if (f->rebuild && inet_frag_may_rebuild(f)) +- inet_frag_secret_rebuild(f); +-} +- +-static void inet_frag_schedule_worker(struct inet_frags *f) +-{ +- if (unlikely(!work_pending(&f->frags_work))) +- schedule_work(&f->frags_work); +-} +- + int inet_frags_init(struct inet_frags *f) + { +- int i; +- +- INIT_WORK(&f->frags_work, inet_frag_worker); +- +- for (i = 0; i < INETFRAGS_HASHSZ; i++) { +- struct inet_frag_bucket *hb = &f->hash[i]; +- +- spin_lock_init(&hb->chain_lock); +- INIT_HLIST_HEAD(&hb->chain); +- } +- +- seqlock_init(&f->rnd_seqlock); +- f->last_rebuild_jiffies = 0; + f->frags_cachep = kmem_cache_create(f->frags_cache_name, f->qsize, 0, 0, + NULL); + if (!f->frags_cachep) +@@ -211,83 +59,75 @@ EXPORT_SYMBOL(inet_frags_init); + + void inet_frags_fini(struct inet_frags *f) + { +- cancel_work_sync(&f->frags_work); ++ /* We must wait that all inet_frag_destroy_rcu() have completed. */ ++ rcu_barrier(); ++ + kmem_cache_destroy(f->frags_cachep); ++ f->frags_cachep = NULL; + } + EXPORT_SYMBOL(inet_frags_fini); + +-void inet_frags_exit_net(struct netns_frags *nf, struct inet_frags *f) ++static void inet_frags_free_cb(void *ptr, void *arg) + { +- unsigned int seq; +- int i; +- +- nf->low_thresh = 0; ++ struct inet_frag_queue *fq = ptr; + +-evict_again: +- local_bh_disable(); +- seq = read_seqbegin(&f->rnd_seqlock); +- +- for (i = 0; i < INETFRAGS_HASHSZ ; i++) +- inet_evict_bucket(f, &f->hash[i]); +- +- local_bh_enable(); +- cond_resched(); +- +- if (read_seqretry(&f->rnd_seqlock, seq) || +- sum_frag_mem_limit(nf)) +- goto evict_again; +-} +-EXPORT_SYMBOL(inet_frags_exit_net); +- +-static struct inet_frag_bucket * +-get_frag_bucket_locked(struct inet_frag_queue *fq, struct inet_frags *f) +-__acquires(hb->chain_lock) +-{ +- struct inet_frag_bucket *hb; +- unsigned int seq, hash; +- +- restart: +- seq = read_seqbegin(&f->rnd_seqlock); +- +- hash = inet_frag_hashfn(f, fq); +- hb = &f->hash[hash]; ++ /* If we can not cancel the timer, it means this frag_queue ++ * is already disappearing, we have nothing to do. ++ * Otherwise, we own a refcount until the end of this function. ++ */ ++ if (!del_timer(&fq->timer)) ++ return; + +- spin_lock(&hb->chain_lock); +- if (read_seqretry(&f->rnd_seqlock, seq)) { +- spin_unlock(&hb->chain_lock); +- goto restart; ++ spin_lock_bh(&fq->lock); ++ if (!(fq->flags & INET_FRAG_COMPLETE)) { ++ fq->flags |= INET_FRAG_COMPLETE; ++ atomic_dec(&fq->refcnt); + } ++ spin_unlock_bh(&fq->lock); + +- return hb; ++ inet_frag_put(fq); + } + +-static inline void fq_unlink(struct inet_frag_queue *fq, struct inet_frags *f) ++void inet_frags_exit_net(struct netns_frags *nf) + { +- struct inet_frag_bucket *hb; ++ nf->low_thresh = 0; /* prevent creation of new frags */ + +- hb = get_frag_bucket_locked(fq, f); +- hlist_del(&fq->list); +- fq->flags |= INET_FRAG_COMPLETE; +- spin_unlock(&hb->chain_lock); ++ rhashtable_free_and_destroy(&nf->rhashtable, inet_frags_free_cb, NULL); + } ++EXPORT_SYMBOL(inet_frags_exit_net); + +-void inet_frag_kill(struct inet_frag_queue *fq, struct inet_frags *f) ++void inet_frag_kill(struct inet_frag_queue *fq) + { + if (del_timer(&fq->timer)) + atomic_dec(&fq->refcnt); + + if (!(fq->flags & INET_FRAG_COMPLETE)) { +- fq_unlink(fq, f); ++ struct netns_frags *nf = fq->net; ++ ++ fq->flags |= INET_FRAG_COMPLETE; ++ rhashtable_remove_fast(&nf->rhashtable, &fq->node, nf->f->rhash_params); + atomic_dec(&fq->refcnt); + } + } + EXPORT_SYMBOL(inet_frag_kill); + +-void inet_frag_destroy(struct inet_frag_queue *q, struct inet_frags *f) ++static void inet_frag_destroy_rcu(struct rcu_head *head) ++{ ++ struct inet_frag_queue *q = container_of(head, struct inet_frag_queue, ++ rcu); ++ struct inet_frags *f = q->net->f; ++ ++ if (f->destructor) ++ f->destructor(q); ++ kmem_cache_free(f->frags_cachep, q); ++} ++ ++void inet_frag_destroy(struct inet_frag_queue *q) + { + struct sk_buff *fp; + struct netns_frags *nf; + unsigned int sum, sum_truesize = 0; ++ struct inet_frags *f; + + WARN_ON(!(q->flags & INET_FRAG_COMPLETE)); + WARN_ON(del_timer(&q->timer) != 0); +@@ -295,68 +135,34 @@ void inet_frag_destroy(struct inet_frag_queue *q, struct inet_frags *f) + /* Release all fragment data. */ + fp = q->fragments; + nf = q->net; +- while (fp) { +- struct sk_buff *xp = fp->next; +- +- sum_truesize += fp->truesize; +- kfree_skb(fp); +- fp = xp; ++ f = nf->f; ++ if (fp) { ++ do { ++ struct sk_buff *xp = fp->next; ++ ++ sum_truesize += fp->truesize; ++ kfree_skb(fp); ++ fp = xp; ++ } while (fp); ++ } else { ++ sum_truesize = skb_rbtree_purge(&q->rb_fragments); + } + sum = sum_truesize + f->qsize; + +- if (f->destructor) +- f->destructor(q); +- kmem_cache_free(f->frags_cachep, q); ++ call_rcu(&q->rcu, inet_frag_destroy_rcu); + + sub_frag_mem_limit(nf, sum); + } + EXPORT_SYMBOL(inet_frag_destroy); + +-static struct inet_frag_queue *inet_frag_intern(struct netns_frags *nf, +- struct inet_frag_queue *qp_in, +- struct inet_frags *f, +- void *arg) +-{ +- struct inet_frag_bucket *hb = get_frag_bucket_locked(qp_in, f); +- struct inet_frag_queue *qp; +- +-#ifdef CONFIG_SMP +- /* With SMP race we have to recheck hash table, because +- * such entry could have been created on other cpu before +- * we acquired hash bucket lock. +- */ +- hlist_for_each_entry(qp, &hb->chain, list) { +- if (qp->net == nf && f->match(qp, arg)) { +- atomic_inc(&qp->refcnt); +- spin_unlock(&hb->chain_lock); +- qp_in->flags |= INET_FRAG_COMPLETE; +- inet_frag_put(qp_in, f); +- return qp; +- } +- } +-#endif +- qp = qp_in; +- if (!mod_timer(&qp->timer, jiffies + nf->timeout)) +- atomic_inc(&qp->refcnt); +- +- atomic_inc(&qp->refcnt); +- hlist_add_head(&qp->list, &hb->chain); +- +- spin_unlock(&hb->chain_lock); +- +- return qp; +-} +- + static struct inet_frag_queue *inet_frag_alloc(struct netns_frags *nf, + struct inet_frags *f, + void *arg) + { + struct inet_frag_queue *q; + +- if (!nf->high_thresh || frag_mem_limit(nf) > nf->high_thresh) { +- inet_frag_schedule_worker(f); ++ if (!nf->high_thresh || frag_mem_limit(nf) > nf->high_thresh) + return NULL; +- } + + q = kmem_cache_zalloc(f->frags_cachep, GFP_ATOMIC); + if (!q) +@@ -368,59 +174,51 @@ static struct inet_frag_queue *inet_frag_alloc(struct netns_frags *nf, + + setup_timer(&q->timer, f->frag_expire, (unsigned long)q); + spin_lock_init(&q->lock); +- atomic_set(&q->refcnt, 1); ++ atomic_set(&q->refcnt, 3); + + return q; + } + + static struct inet_frag_queue *inet_frag_create(struct netns_frags *nf, +- struct inet_frags *f, + void *arg) + { ++ struct inet_frags *f = nf->f; + struct inet_frag_queue *q; ++ int err; + + q = inet_frag_alloc(nf, f, arg); + if (!q) + return NULL; + +- return inet_frag_intern(nf, q, f, arg); +-} ++ mod_timer(&q->timer, jiffies + nf->timeout); + +-struct inet_frag_queue *inet_frag_find(struct netns_frags *nf, +- struct inet_frags *f, void *key, +- unsigned int hash) +-{ +- struct inet_frag_bucket *hb; +- struct inet_frag_queue *q; +- int depth = 0; +- +- if (frag_mem_limit(nf) > nf->low_thresh) +- inet_frag_schedule_worker(f); +- +- hash &= (INETFRAGS_HASHSZ - 1); +- hb = &f->hash[hash]; +- +- spin_lock(&hb->chain_lock); +- hlist_for_each_entry(q, &hb->chain, list) { +- if (q->net == nf && f->match(q, key)) { +- atomic_inc(&q->refcnt); +- spin_unlock(&hb->chain_lock); +- return q; +- } +- depth++; ++ err = rhashtable_insert_fast(&nf->rhashtable, &q->node, ++ f->rhash_params); ++ if (err < 0) { ++ q->flags |= INET_FRAG_COMPLETE; ++ inet_frag_kill(q); ++ inet_frag_destroy(q); ++ return NULL; + } +- spin_unlock(&hb->chain_lock); ++ return q; ++} ++EXPORT_SYMBOL(inet_frag_create); + +- if (depth <= INETFRAGS_MAXDEPTH) +- return inet_frag_create(nf, f, key); ++/* TODO : call from rcu_read_lock() and no longer use refcount_inc_not_zero() */ ++struct inet_frag_queue *inet_frag_find(struct netns_frags *nf, void *key) ++{ ++ struct inet_frag_queue *fq; + +- if (inet_frag_may_rebuild(f)) { +- if (!f->rebuild) +- f->rebuild = true; +- inet_frag_schedule_worker(f); ++ rcu_read_lock(); ++ fq = rhashtable_lookup(&nf->rhashtable, key, nf->f->rhash_params); ++ if (fq) { ++ if (!atomic_inc_not_zero(&fq->refcnt)) ++ fq = NULL; ++ rcu_read_unlock(); ++ return fq; + } +- +- return ERR_PTR(-ENOBUFS); ++ rcu_read_unlock(); ++ return inet_frag_create(nf, key); + } + EXPORT_SYMBOL(inet_frag_find); + +@@ -428,8 +226,7 @@ void inet_frag_maybe_warn_overflow(struct inet_frag_queue *q, + const char *prefix) + { + static const char msg[] = "inet_frag_find: Fragment hash bucket" +- " list length grew over limit " __stringify(INETFRAGS_MAXDEPTH) +- ". Dropping fragment.\n"; ++ " list length grew over limit. Dropping fragment.\n"; + + if (PTR_ERR(q) == -ENOBUFS) + net_dbg_ratelimited("%s%s", prefix, msg); +diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c +old mode 100644 +new mode 100755 +index b9bcf3db3af9..c0a502b6fd3b +--- a/net/ipv4/inet_hashtables.c ++++ b/net/ipv4/inet_hashtables.c +@@ -498,6 +498,17 @@ int inet_hash(struct sock *sk) + { + int err = 0; + ++#if 0 /// if toe, return ?? ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++ printk("[%s][%d] newsk = 0x%08x\n", __FUNCTION__, __LINE__, (int)newsk); ++#endif ++#endif ++ + if (sk->sk_state != TCP_CLOSE) { + local_bh_disable(); + err = __inet_hash(sk, NULL, ipv4_rcv_saddr_equal); +@@ -515,6 +526,16 @@ void inet_unhash(struct sock *sk) + bool listener = false; + int done; + ++#if 0 /// if toe, return ?? ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++ printk("[%s][%d] newsk = 0x%08x\n", __FUNCTION__, __LINE__, (int)newsk); ++#endif ++#endif + if (sk_unhashed(sk)) + return; + +diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c +index 4bf3b8af0257..bb748dbab252 100644 +--- a/net/ipv4/ip_fragment.c ++++ b/net/ipv4/ip_fragment.c +@@ -56,27 +56,13 @@ + */ + static const char ip_frag_cache_name[] = "ip4-frags"; + +-struct ipfrag_skb_cb +-{ +- struct inet_skb_parm h; +- int offset; +-}; +- +-#define FRAG_CB(skb) ((struct ipfrag_skb_cb *)((skb)->cb)) +- + /* Describe an entry in the "incomplete datagrams" queue. */ + struct ipq { + struct inet_frag_queue q; + +- u32 user; +- __be32 saddr; +- __be32 daddr; +- __be16 id; +- u8 protocol; + u8 ecn; /* RFC3168 support */ + u16 max_df_size; /* largest frag with DF set seen */ + int iif; +- int vif; /* L3 master device index */ + unsigned int rid; + struct inet_peer *peer; + }; +@@ -88,49 +74,9 @@ static u8 ip4_frag_ecn(u8 tos) + + static struct inet_frags ip4_frags; + +-int ip_frag_mem(struct net *net) +-{ +- return sum_frag_mem_limit(&net->ipv4.frags); +-} +- + static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, + struct net_device *dev); + +-struct ip4_create_arg { +- struct iphdr *iph; +- u32 user; +- int vif; +-}; +- +-static unsigned int ipqhashfn(__be16 id, __be32 saddr, __be32 daddr, u8 prot) +-{ +- net_get_random_once(&ip4_frags.rnd, sizeof(ip4_frags.rnd)); +- return jhash_3words((__force u32)id << 16 | prot, +- (__force u32)saddr, (__force u32)daddr, +- ip4_frags.rnd); +-} +- +-static unsigned int ip4_hashfn(const struct inet_frag_queue *q) +-{ +- const struct ipq *ipq; +- +- ipq = container_of(q, struct ipq, q); +- return ipqhashfn(ipq->id, ipq->saddr, ipq->daddr, ipq->protocol); +-} +- +-static bool ip4_frag_match(const struct inet_frag_queue *q, const void *a) +-{ +- const struct ipq *qp; +- const struct ip4_create_arg *arg = a; +- +- qp = container_of(q, struct ipq, q); +- return qp->id == arg->iph->id && +- qp->saddr == arg->iph->saddr && +- qp->daddr == arg->iph->daddr && +- qp->protocol == arg->iph->protocol && +- qp->user == arg->user && +- qp->vif == arg->vif; +-} + + static void ip4_frag_init(struct inet_frag_queue *q, const void *a) + { +@@ -139,17 +85,12 @@ static void ip4_frag_init(struct inet_frag_queue *q, const void *a) + frags); + struct net *net = container_of(ipv4, struct net, ipv4); + +- const struct ip4_create_arg *arg = a; ++ const struct frag_v4_compare_key *key = a; + +- qp->protocol = arg->iph->protocol; +- qp->id = arg->iph->id; +- qp->ecn = ip4_frag_ecn(arg->iph->tos); +- qp->saddr = arg->iph->saddr; +- qp->daddr = arg->iph->daddr; +- qp->vif = arg->vif; +- qp->user = arg->user; ++ q->key.v4 = *key; ++ qp->ecn = 0; + qp->peer = q->net->max_dist ? +- inet_getpeer_v4(net->ipv4.peers, arg->iph->saddr, arg->vif, 1) : ++ inet_getpeer_v4(net->ipv4.peers, key->saddr, key->vif, 1) : + NULL; + } + +@@ -167,7 +108,7 @@ static void ip4_frag_free(struct inet_frag_queue *q) + + static void ipq_put(struct ipq *ipq) + { +- inet_frag_put(&ipq->q, &ip4_frags); ++ inet_frag_put(&ipq->q); + } + + /* Kill ipq entry. It is not destroyed immediately, +@@ -175,7 +116,7 @@ static void ipq_put(struct ipq *ipq) + */ + static void ipq_kill(struct ipq *ipq) + { +- inet_frag_kill(&ipq->q, &ip4_frags); ++ inet_frag_kill(&ipq->q); + } + + static bool frag_expire_skip_icmp(u32 user) +@@ -192,8 +133,11 @@ static bool frag_expire_skip_icmp(u32 user) + */ + static void ip_expire(unsigned long arg) + { +- struct ipq *qp; ++ const struct iphdr *iph; ++ struct sk_buff *head = NULL; + struct net *net; ++ struct ipq *qp; ++ int err; + + qp = container_of((struct inet_frag_queue *) arg, struct ipq, q); + net = container_of(qp->q.net, struct net, ipv4.frags); +@@ -206,51 +150,60 @@ static void ip_expire(unsigned long arg) + + ipq_kill(qp); + __IP_INC_STATS(net, IPSTATS_MIB_REASMFAILS); ++ __IP_INC_STATS(net, IPSTATS_MIB_REASMTIMEOUT); + +- if (!inet_frag_evicting(&qp->q)) { +- struct sk_buff *clone, *head = qp->q.fragments; +- const struct iphdr *iph; +- int err; +- +- __IP_INC_STATS(net, IPSTATS_MIB_REASMTIMEOUT); ++ if (!(qp->q.flags & INET_FRAG_FIRST_IN)) ++ goto out; + +- if (!(qp->q.flags & INET_FRAG_FIRST_IN) || !qp->q.fragments) ++ /* sk_buff::dev and sk_buff::rbnode are unionized. So we ++ * pull the head out of the tree in order to be able to ++ * deal with head->dev. ++ */ ++ if (qp->q.fragments) { ++ head = qp->q.fragments; ++ qp->q.fragments = head->next; ++ } else { ++ head = skb_rb_first(&qp->q.rb_fragments); ++ if (!head) + goto out; ++ rb_erase(&head->rbnode, &qp->q.rb_fragments); ++ memset(&head->rbnode, 0, sizeof(head->rbnode)); ++ barrier(); ++ } ++ if (head == qp->q.fragments_tail) ++ qp->q.fragments_tail = NULL; + +- head->dev = dev_get_by_index_rcu(net, qp->iif); +- if (!head->dev) +- goto out; ++ sub_frag_mem_limit(qp->q.net, head->truesize); ++ ++ head->dev = dev_get_by_index_rcu(net, qp->iif); ++ if (!head->dev) ++ goto out; + + +- /* skb has no dst, perform route lookup again */ +- iph = ip_hdr(head); +- err = ip_route_input_noref(head, iph->daddr, iph->saddr, ++ /* skb has no dst, perform route lookup again */ ++ iph = ip_hdr(head); ++ err = ip_route_input_noref(head, iph->daddr, iph->saddr, + iph->tos, head->dev); +- if (err) +- goto out; ++ if (err) ++ goto out; + +- /* Only an end host needs to send an ICMP +- * "Fragment Reassembly Timeout" message, per RFC792. +- */ +- if (frag_expire_skip_icmp(qp->user) && +- (skb_rtable(head)->rt_type != RTN_LOCAL)) +- goto out; ++ /* Only an end host needs to send an ICMP ++ * "Fragment Reassembly Timeout" message, per RFC792. ++ */ ++ if (frag_expire_skip_icmp(qp->q.key.v4.user) && ++ (skb_rtable(head)->rt_type != RTN_LOCAL)) ++ goto out; + +- clone = skb_clone(head, GFP_ATOMIC); ++ spin_unlock(&qp->q.lock); ++ icmp_send(head, ICMP_TIME_EXCEEDED, ICMP_EXC_FRAGTIME, 0); ++ goto out_rcu_unlock; + +- /* Send an ICMP "Fragment Reassembly Timeout" message. */ +- if (clone) { +- spin_unlock(&qp->q.lock); +- icmp_send(clone, ICMP_TIME_EXCEEDED, +- ICMP_EXC_FRAGTIME, 0); +- consume_skb(clone); +- goto out_rcu_unlock; +- } +- } + out: + spin_unlock(&qp->q.lock); + out_rcu_unlock: + rcu_read_unlock(); ++ if (head) ++ kfree_skb(head); + ipq_put(qp); + } + +@@ -260,17 +213,17 @@ out_rcu_unlock: + static struct ipq *ip_find(struct net *net, struct iphdr *iph, + u32 user, int vif) + { ++ struct frag_v4_compare_key key = { ++ .saddr = iph->saddr, ++ .daddr = iph->daddr, ++ .user = user, ++ .vif = vif, ++ .id = iph->id, ++ .protocol = iph->protocol, ++ }; + struct inet_frag_queue *q; +- struct ip4_create_arg arg; +- unsigned int hash; +- +- arg.iph = iph; +- arg.user = user; +- arg.vif = vif; + +- hash = ipqhashfn(iph->id, iph->saddr, iph->daddr, iph->protocol); +- +- q = inet_frag_find(&net->ipv4.frags, &ip4_frags, &arg, hash); ++ q = inet_frag_find(&net->ipv4.frags, &key); + if (IS_ERR_OR_NULL(q)) { + inet_frag_maybe_warn_overflow(q, pr_fmt()); + return NULL; +@@ -294,7 +247,7 @@ static int ip_frag_too_far(struct ipq *qp) + end = atomic_inc_return(&peer->rid); + qp->rid = end; + +- rc = qp->q.fragments && (end - start) > max; ++ rc = qp->q.fragments_tail && (end - start) > max; + + if (rc) { + struct net *net; +@@ -308,7 +261,6 @@ static int ip_frag_too_far(struct ipq *qp) + + static int ip_frag_reinit(struct ipq *qp) + { +- struct sk_buff *fp; + unsigned int sum_truesize = 0; + + if (!mod_timer(&qp->q.timer, jiffies + qp->q.net->timeout)) { +@@ -316,20 +268,14 @@ static int ip_frag_reinit(struct ipq *qp) + return -ETIMEDOUT; + } + +- fp = qp->q.fragments; +- do { +- struct sk_buff *xp = fp->next; +- +- sum_truesize += fp->truesize; +- kfree_skb(fp); +- fp = xp; +- } while (fp); ++ sum_truesize = skb_rbtree_purge(&qp->q.rb_fragments); + sub_frag_mem_limit(qp->q.net, sum_truesize); + + qp->q.flags = 0; + qp->q.len = 0; + qp->q.meat = 0; + qp->q.fragments = NULL; ++ qp->q.rb_fragments = RB_ROOT; + qp->q.fragments_tail = NULL; + qp->iif = 0; + qp->ecn = 0; +@@ -340,7 +286,9 @@ static int ip_frag_reinit(struct ipq *qp) + /* Add new segment to existing queue. */ + static int ip_frag_queue(struct ipq *qp, struct sk_buff *skb) + { +- struct sk_buff *prev, *next; ++ struct net *net = container_of(qp->q.net, struct net, ipv4.frags); ++ struct rb_node **rbn, *parent; ++ struct sk_buff *skb1; + struct net_device *dev; + unsigned int fragsize; + int flags, offset; +@@ -403,94 +351,58 @@ static int ip_frag_queue(struct ipq *qp, struct sk_buff *skb) + if (err) + goto err; + +- /* Find out which fragments are in front and at the back of us +- * in the chain of fragments so far. We must know where to put +- * this fragment, right? +- */ +- prev = qp->q.fragments_tail; +- if (!prev || FRAG_CB(prev)->offset < offset) { +- next = NULL; +- goto found; +- } +- prev = NULL; +- for (next = qp->q.fragments; next != NULL; next = next->next) { +- if (FRAG_CB(next)->offset >= offset) +- break; /* bingo! */ +- prev = next; +- } +- +-found: +- /* We found where to put this one. Check for overlap with +- * preceding fragment, and, if needed, align things so that +- * any overlaps are eliminated. ++ /* Note : skb->rbnode and skb->dev share the same location. */ ++ dev = skb->dev; ++ /* Makes sure compiler wont do silly aliasing games */ ++ barrier(); ++ ++ /* RFC5722, Section 4, amended by Errata ID : 3089 ++ * When reassembling an IPv6 datagram, if ++ * one or more its constituent fragments is determined to be an ++ * overlapping fragment, the entire datagram (and any constituent ++ * fragments) MUST be silently discarded. ++ * ++ * We do the same here for IPv4 (and increment an snmp counter). + */ +- if (prev) { +- int i = (FRAG_CB(prev)->offset + prev->len) - offset; + +- if (i > 0) { +- offset += i; +- err = -EINVAL; +- if (end <= offset) +- goto err; +- err = -ENOMEM; +- if (!pskb_pull(skb, i)) +- goto err; +- if (skb->ip_summed != CHECKSUM_UNNECESSARY) +- skb->ip_summed = CHECKSUM_NONE; +- } +- } +- +- err = -ENOMEM; +- +- while (next && FRAG_CB(next)->offset < end) { +- int i = end - FRAG_CB(next)->offset; /* overlap is 'i' bytes */ +- +- if (i < next->len) { +- /* Eat head of the next overlapped fragment +- * and leave the loop. The next ones cannot overlap. +- */ +- if (!pskb_pull(next, i)) +- goto err; +- FRAG_CB(next)->offset += i; +- qp->q.meat -= i; +- if (next->ip_summed != CHECKSUM_UNNECESSARY) +- next->ip_summed = CHECKSUM_NONE; +- break; +- } else { +- struct sk_buff *free_it = next; +- +- /* Old fragment is completely overridden with +- * new one drop it. +- */ +- next = next->next; +- +- if (prev) +- prev->next = next; +- else +- qp->q.fragments = next; +- +- qp->q.meat -= free_it->len; +- sub_frag_mem_limit(qp->q.net, free_it->truesize); +- kfree_skb(free_it); +- } +- } +- +- FRAG_CB(skb)->offset = offset; +- +- /* Insert this fragment in the chain of fragments. */ +- skb->next = next; +- if (!next) ++ /* Find out where to put this fragment. */ ++ skb1 = qp->q.fragments_tail; ++ if (!skb1) { ++ /* This is the first fragment we've received. */ ++ rb_link_node(&skb->rbnode, NULL, &qp->q.rb_fragments.rb_node); ++ qp->q.fragments_tail = skb; ++ } else if ((skb1->ip_defrag_offset + skb1->len) < end) { ++ /* This is the common/special case: skb goes to the end. */ ++ /* Detect and discard overlaps. */ ++ if (offset < (skb1->ip_defrag_offset + skb1->len)) ++ goto discard_qp; ++ /* Insert after skb1. */ ++ rb_link_node(&skb->rbnode, &skb1->rbnode, &skb1->rbnode.rb_right); + qp->q.fragments_tail = skb; +- if (prev) +- prev->next = skb; +- else +- qp->q.fragments = skb; ++ } else { ++ /* Binary search. Note that skb can become the first fragment, but ++ * not the last (covered above). */ ++ rbn = &qp->q.rb_fragments.rb_node; ++ do { ++ parent = *rbn; ++ skb1 = rb_to_skb(parent); ++ if (end <= skb1->ip_defrag_offset) ++ rbn = &parent->rb_left; ++ else if (offset >= skb1->ip_defrag_offset + skb1->len) ++ rbn = &parent->rb_right; ++ else /* Found an overlap with skb1. */ ++ goto discard_qp; ++ } while (*rbn); ++ /* Here we have parent properly set, and rbn pointing to ++ * one of its NULL left/right children. Insert skb. */ ++ rb_link_node(&skb->rbnode, parent, rbn); ++ } ++ rb_insert_color(&skb->rbnode, &qp->q.rb_fragments); + +- dev = skb->dev; +- if (dev) { ++ if (dev) + qp->iif = dev->ifindex; +- skb->dev = NULL; +- } ++ skb->ip_defrag_offset = offset; ++ + qp->q.stamp = skb->tstamp; + qp->q.meat += skb->len; + qp->ecn |= ecn; +@@ -512,7 +424,7 @@ found: + unsigned long orefdst = skb->_skb_refdst; + + skb->_skb_refdst = 0UL; +- err = ip_frag_reasm(qp, prev, dev); ++ err = ip_frag_reasm(qp, skb, dev); + skb->_skb_refdst = orefdst; + return err; + } +@@ -520,20 +432,24 @@ found: + skb_dst_drop(skb); + return -EINPROGRESS; + ++discard_qp: ++ inet_frag_kill(&qp->q); ++ err = -EINVAL; ++ __IP_INC_STATS(net, IPSTATS_MIB_REASM_OVERLAPS); + err: + kfree_skb(skb); + return err; + } + +- + /* Build a new IP datagram from all its fragments. */ +- +-static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, ++static int ip_frag_reasm(struct ipq *qp, struct sk_buff *skb, + struct net_device *dev) + { + struct net *net = container_of(qp->q.net, struct net, ipv4.frags); + struct iphdr *iph; +- struct sk_buff *fp, *head = qp->q.fragments; ++ struct sk_buff *fp, *head = skb_rb_first(&qp->q.rb_fragments); ++ struct sk_buff **nextp; /* To build frag_list. */ ++ struct rb_node *rbn; + int len; + int ihlen; + int err; +@@ -547,26 +463,21 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, + goto out_fail; + } + /* Make the one we just received the head. */ +- if (prev) { +- head = prev->next; +- fp = skb_clone(head, GFP_ATOMIC); ++ if (head != skb) { ++ fp = skb_clone(skb, GFP_ATOMIC); + if (!fp) + goto out_nomem; +- +- fp->next = head->next; +- if (!fp->next) ++ rb_replace_node(&skb->rbnode, &fp->rbnode, &qp->q.rb_fragments); ++ if (qp->q.fragments_tail == skb) + qp->q.fragments_tail = fp; +- prev->next = fp; +- +- skb_morph(head, qp->q.fragments); +- head->next = qp->q.fragments->next; +- +- consume_skb(qp->q.fragments); +- qp->q.fragments = head; ++ skb_morph(skb, head); ++ rb_replace_node(&head->rbnode, &skb->rbnode, ++ &qp->q.rb_fragments); ++ consume_skb(head); ++ head = skb; + } + +- WARN_ON(!head); +- WARN_ON(FRAG_CB(head)->offset != 0); ++ WARN_ON(head->ip_defrag_offset != 0); + + /* Allocate a new buffer for the datagram. */ + ihlen = ip_hdrlen(head); +@@ -590,24 +501,36 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, + clone = alloc_skb(0, GFP_ATOMIC); + if (!clone) + goto out_nomem; +- clone->next = head->next; +- head->next = clone; + skb_shinfo(clone)->frag_list = skb_shinfo(head)->frag_list; + skb_frag_list_init(head); + for (i = 0; i < skb_shinfo(head)->nr_frags; i++) + plen += skb_frag_size(&skb_shinfo(head)->frags[i]); + clone->len = clone->data_len = head->data_len - plen; +- head->data_len -= clone->len; +- head->len -= clone->len; ++ skb->truesize += clone->truesize; + clone->csum = 0; + clone->ip_summed = head->ip_summed; + add_frag_mem_limit(qp->q.net, clone->truesize); ++ skb_shinfo(head)->frag_list = clone; ++ nextp = &clone->next; ++ } else { ++ nextp = &skb_shinfo(head)->frag_list; + } + +- skb_shinfo(head)->frag_list = head->next; + skb_push(head, head->data - skb_network_header(head)); + +- for (fp=head->next; fp; fp = fp->next) { ++ /* Traverse the tree in order, to build frag_list. */ ++ rbn = rb_next(&head->rbnode); ++ rb_erase(&head->rbnode, &qp->q.rb_fragments); ++ while (rbn) { ++ struct rb_node *rbnext = rb_next(rbn); ++ fp = rb_to_skb(rbn); ++ rb_erase(rbn, &qp->q.rb_fragments); ++ rbn = rbnext; ++ *nextp = fp; ++ nextp = &fp->next; ++ fp->prev = NULL; ++ memset(&fp->rbnode, 0, sizeof(fp->rbnode)); ++ fp->sk = NULL; + head->data_len += fp->len; + head->len += fp->len; + if (head->ip_summed != fp->ip_summed) +@@ -618,7 +541,9 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, + } + sub_frag_mem_limit(qp->q.net, head->truesize); + ++ *nextp = NULL; + head->next = NULL; ++ head->prev = NULL; + head->dev = dev; + head->tstamp = qp->q.stamp; + IPCB(head)->frag_max_size = max(qp->max_df_size, qp->q.max_size); +@@ -646,6 +571,7 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, + + __IP_INC_STATS(net, IPSTATS_MIB_REASMOKS); + qp->q.fragments = NULL; ++ qp->q.rb_fragments = RB_ROOT; + qp->q.fragments_tail = NULL; + return 0; + +@@ -654,7 +580,7 @@ out_nomem: + err = -ENOMEM; + goto out_fail; + out_oversize: +- net_info_ratelimited("Oversized IP packet from %pI4\n", &qp->saddr); ++ net_info_ratelimited("Oversized IP packet from %pI4\n", &qp->q.key.v4.saddr); + out_fail: + __IP_INC_STATS(net, IPSTATS_MIB_REASMFAILS); + return err; +@@ -729,24 +655,23 @@ struct sk_buff *ip_check_defrag(struct net *net, struct sk_buff *skb, u32 user) + EXPORT_SYMBOL(ip_check_defrag); + + #ifdef CONFIG_SYSCTL +-static int zero; ++static int dist_min; + + static struct ctl_table ip4_frags_ns_ctl_table[] = { + { + .procname = "ipfrag_high_thresh", + .data = &init_net.ipv4.frags.high_thresh, +- .maxlen = sizeof(int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, ++ .proc_handler = proc_doulongvec_minmax, + .extra1 = &init_net.ipv4.frags.low_thresh + }, + { + .procname = "ipfrag_low_thresh", + .data = &init_net.ipv4.frags.low_thresh, +- .maxlen = sizeof(int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, +- .extra1 = &zero, ++ .proc_handler = proc_doulongvec_minmax, + .extra2 = &init_net.ipv4.frags.high_thresh + }, + { +@@ -762,7 +687,7 @@ static struct ctl_table ip4_frags_ns_ctl_table[] = { + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, +- .extra1 = &zero ++ .extra1 = &dist_min, + }, + { } + }; +@@ -844,6 +769,8 @@ static void __init ip4_frags_ctl_register(void) + + static int __net_init ipv4_frags_init_net(struct net *net) + { ++ int res; ++ + /* Fragment cache limits. + * + * The fragment memory accounting code, (tries to) account for +@@ -868,16 +795,21 @@ static int __net_init ipv4_frags_init_net(struct net *net) + net->ipv4.frags.timeout = IP_FRAG_TIME; + + net->ipv4.frags.max_dist = 64; +- +- inet_frags_init_net(&net->ipv4.frags); +- +- return ip4_frags_ns_ctl_register(net); ++ net->ipv4.frags.f = &ip4_frags; ++ ++ res = inet_frags_init_net(&net->ipv4.frags); ++ if (res < 0) ++ return res; ++ res = ip4_frags_ns_ctl_register(net); ++ if (res < 0) ++ inet_frags_exit_net(&net->ipv4.frags); ++ return res; + } + + static void __net_exit ipv4_frags_exit_net(struct net *net) + { + ip4_frags_ns_ctl_unregister(net); +- inet_frags_exit_net(&net->ipv4.frags, &ip4_frags); ++ inet_frags_exit_net(&net->ipv4.frags); + } + + static struct pernet_operations ip4_frags_ops = { +@@ -885,17 +817,49 @@ static struct pernet_operations ip4_frags_ops = { + .exit = ipv4_frags_exit_net, + }; + ++ ++static u32 ip4_key_hashfn(const void *data, u32 len, u32 seed) ++{ ++ return jhash2(data, ++ sizeof(struct frag_v4_compare_key) / sizeof(u32), seed); ++} ++ ++static u32 ip4_obj_hashfn(const void *data, u32 len, u32 seed) ++{ ++ const struct inet_frag_queue *fq = data; ++ ++ return jhash2((const u32 *)&fq->key.v4, ++ sizeof(struct frag_v4_compare_key) / sizeof(u32), seed); ++} ++ ++static int ip4_obj_cmpfn(struct rhashtable_compare_arg *arg, const void *ptr) ++{ ++ const struct frag_v4_compare_key *key = arg->key; ++ const struct inet_frag_queue *fq = ptr; ++ ++ return !!memcmp(&fq->key, key, sizeof(*key)); ++} ++ ++static const struct rhashtable_params ip4_rhash_params = { ++ .head_offset = offsetof(struct inet_frag_queue, node), ++ .key_offset = offsetof(struct inet_frag_queue, key), ++ .key_len = sizeof(struct frag_v4_compare_key), ++ .hashfn = ip4_key_hashfn, ++ .obj_hashfn = ip4_obj_hashfn, ++ .obj_cmpfn = ip4_obj_cmpfn, ++ .automatic_shrinking = true, ++}; ++ + void __init ipfrag_init(void) + { +- ip4_frags_ctl_register(); +- register_pernet_subsys(&ip4_frags_ops); +- ip4_frags.hashfn = ip4_hashfn; + ip4_frags.constructor = ip4_frag_init; + ip4_frags.destructor = ip4_frag_free; + ip4_frags.qsize = sizeof(struct ipq); +- ip4_frags.match = ip4_frag_match; + ip4_frags.frag_expire = ip_expire; + ip4_frags.frags_cache_name = ip_frag_cache_name; ++ ip4_frags.rhash_params = ip4_rhash_params; + if (inet_frags_init(&ip4_frags)) + panic("IP: failed to allocate ip4_frags cache\n"); ++ ip4_frags_ctl_register(); ++ register_pernet_subsys(&ip4_frags_ops); + } +diff --git a/net/ipv4/proc.c b/net/ipv4/proc.c +index 7143ca1a6af9..ec48d8eafc7e 100644 +--- a/net/ipv4/proc.c ++++ b/net/ipv4/proc.c +@@ -54,7 +54,6 @@ + static int sockstat_seq_show(struct seq_file *seq, void *v) + { + struct net *net = seq->private; +- unsigned int frag_mem; + int orphans, sockets; + + local_bh_disable(); +@@ -74,8 +73,9 @@ static int sockstat_seq_show(struct seq_file *seq, void *v) + sock_prot_inuse_get(net, &udplite_prot)); + seq_printf(seq, "RAW: inuse %d\n", + sock_prot_inuse_get(net, &raw_prot)); +- frag_mem = ip_frag_mem(net); +- seq_printf(seq, "FRAG: inuse %u memory %u\n", !!frag_mem, frag_mem); ++ seq_printf(seq, "FRAG: inuse %u memory %lu\n", ++ atomic_read(&net->ipv4.frags.rhashtable.nelems), ++ frag_mem_limit(&net->ipv4.frags)); + return 0; + } + +@@ -134,6 +134,7 @@ static const struct snmp_mib snmp4_ipextstats_list[] = { + SNMP_MIB_ITEM("InECT1Pkts", IPSTATS_MIB_ECT1PKTS), + SNMP_MIB_ITEM("InECT0Pkts", IPSTATS_MIB_ECT0PKTS), + SNMP_MIB_ITEM("InCEPkts", IPSTATS_MIB_CEPKTS), ++ SNMP_MIB_ITEM("ReasmOverlaps", IPSTATS_MIB_REASM_OVERLAPS), + SNMP_MIB_SENTINEL + }; + +diff --git a/net/ipv4/sysctl_net_ipv4.c b/net/ipv4/sysctl_net_ipv4.c +index 566cfc50f7cf..759285f3871b 100644 +--- a/net/ipv4/sysctl_net_ipv4.c ++++ b/net/ipv4/sysctl_net_ipv4.c +@@ -41,6 +41,7 @@ static int tcp_syn_retries_min = 1; + static int tcp_syn_retries_max = MAX_TCP_SYNCNT; + static int ip_ping_group_range_min[] = { 0, 0 }; + static int ip_ping_group_range_max[] = { GID_T_MAX, GID_T_MAX }; ++static int one_day_secs = 24 * 3600; + + /* Update system visible IP port range */ + static void set_local_port_range(struct net *net, int range[2]) +@@ -451,7 +452,9 @@ static struct ctl_table ipv4_table[] = { + .data = &sysctl_tcp_min_rtt_wlen, + .maxlen = sizeof(int), + .mode = 0644, +- .proc_handler = proc_dointvec ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &zero, ++ .extra2 = &one_day_secs + }, + { + .procname = "tcp_low_latency", +diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c +old mode 100644 +new mode 100755 +index 0d1a767db1bb..07cda46202ab +--- a/net/ipv4/tcp.c ++++ b/net/ipv4/tcp.c +@@ -282,6 +282,10 @@ + #include + #include + ++#ifdef CONFIG_SS_SWTOE_TCP ++#include "mdrv_swtoe.h" ++#endif ++ + int sysctl_tcp_min_tso_segs __read_mostly = 2; + + int sysctl_tcp_autocorking __read_mostly = 1; +@@ -326,6 +330,15 @@ EXPORT_SYMBOL(tcp_memory_pressure); + + void tcp_enter_memory_pressure(struct sock *sk) + { ++#if 0 // what is this for? ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif + if (!tcp_memory_pressure) { + NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPMEMORYPRESSURES); + tcp_memory_pressure = 1; +@@ -457,6 +470,15 @@ unsigned int tcp_poll(struct file *file, struct socket *sock, poll_table *wait) + const struct tcp_sock *tp = tcp_sk(sk); + int state; + ++#if 0 /// seems useless ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++#endif ++#endif ++ + sock_rps_record_flow(sk); + + sock_poll_wait(file, sk_sleep(sk), wait); +@@ -553,6 +575,14 @@ int tcp_ioctl(struct sock *sk, int cmd, unsigned long arg) + struct tcp_sock *tp = tcp_sk(sk); + int answ; + bool slow; ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++#endif ++#endif + + switch (cmd) { + case SIOCINQ: +@@ -703,6 +733,17 @@ static int __tcp_splice_read(struct sock *sk, struct tcp_splice_state *tss) + .count = tss->len, + }; + ++// SWTOE_RX ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + return tcp_read_sock(sk, &rd_desc, tcp_splice_data_recv); + } + +@@ -910,6 +951,37 @@ static ssize_t do_tcp_sendpages(struct sock *sk, struct page *page, int offset, + if (sk->sk_err || (sk->sk_shutdown & SEND_SHUTDOWN)) + goto out_err; + ++#ifdef CONFIG_SS_SWTOE_TCP ++ if (sk->ss_swtoe) ++ { ++ int copy = 0; ++ copied = copy = 0; ++ while (size) ++ { ++ copy = drv_swtoe_tx_send(sk->ss_swtoe_cnx, (void*)page, size, offset, SWTOE_TX_SEND_PAGE); ++ if (!copy) ++ { ++ if (copied) ++ { ++ drv_swtoe_tx_pump(sk->ss_swtoe_cnx); ++ } ++ err = sk_stream_wait_memory(sk, &timeo); ++ if (err != 0) ++ { ++ break; ++ } ++ } ++ size -= copy; ++ offset += copy; ++ copied += copy; ++ } ++ if (copied) ++ { ++ drv_swtoe_tx_pump(sk->ss_swtoe_cnx); ++ } ++ return copied; ++ } ++#endif + while (size > 0) { + struct sk_buff *skb = tcp_write_queue_tail(sk); + int copy, i; +@@ -1082,6 +1154,22 @@ static int tcp_sendmsg_fastopen(struct sock *sk, struct msghdr *msg, + struct sockaddr *uaddr = msg->msg_name; + int err, flags; + ++#ifdef CONFIG_SS_SWTOE_TCP_CLIENT ++ if (sk->ss_swtoe) ++ { ++ /* ++ if (drv_swtoe_connect_fast(sk->ss_swtoe_cnx, uaddr, sk->ss_swtoe_blk)) ++ { ++ printk("[%s][%d] swtoe connect fail %d\n", __FUNCTION__, __LINE__, sk->ss_swtoe_cnx); ++ return -EINVAL;; ++ } ++ return 0; ++ */ ++ printk("[%s][%d] SWTOE support NO fast open\n", __FUNCTION__, __LINE__); ++ return -EOPNOTSUPP; ++ } ++#endif ++ + if (!(sysctl_tcp_fastopen & TFO_CLIENT_ENABLE) || + (uaddr && msg->msg_namelen >= sizeof(uaddr->sa_family) && + uaddr->sa_family == AF_UNSPEC)) +@@ -1176,6 +1264,37 @@ restart: + if (sk->sk_err || (sk->sk_shutdown & SEND_SHUTDOWN)) + goto do_error; + ++#ifdef CONFIG_SS_SWTOE_TCP ++ if (sk->ss_swtoe) ++ { ++ int copy = 0; ++ copied = copy = 0; ++ while (msg_data_left(msg)) ++ { ++ copy = drv_swtoe_tx_send(sk->ss_swtoe_cnx, (void*)&msg->msg_iter, 0, 0, SWTOE_TX_SEND_IOV); ++ if (!copy) ++ { ++ if (copied) ++ { ++ drv_swtoe_tx_pump(sk->ss_swtoe_cnx); ++ } ++ err = sk_stream_wait_memory(sk, &timeo); ++ if (err != 0) ++ { ++ break; ++ } ++ } ++ copied += copy; ++ } ++ if (copied) ++ { ++ drv_swtoe_tx_pump(sk->ss_swtoe_cnx); ++ } ++ release_sock(sk); ++ return copied; ++ } ++#endif ++ + sg = !!(sk->sk_route_caps & NETIF_F_SG); + + while (msg_data_left(msg)) { +@@ -1540,6 +1659,16 @@ int tcp_read_sock(struct sock *sk, read_descriptor_t *desc, + u32 offset; + int copied = 0; + ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + if (sk->sk_state == TCP_LISTEN) + return -ENOTCONN; + while ((skb = tcp_recv_skb(sk, seq, &offset)) != NULL) { +@@ -1605,10 +1734,179 @@ EXPORT_SYMBOL(tcp_read_sock); + + int tcp_peek_len(struct socket *sock) + { ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++#endif ++#endif + return tcp_inq(sock->sk); + } + EXPORT_SYMBOL(tcp_peek_len); + ++ ++#ifdef CONFIG_SS_SWTOE_TCP ++ ++#define _SWTOE_RX_DATA_READY (!drv_swtoe_rx_data_avail((sk)->ss_swtoe_cnx)) ++ ++int _swtoe_tcp_wait_data(struct sock *sk, long *timeo) ++{ ++ int rc; ++ DEFINE_WAIT(wait); ++ ++ if ((!sk->ss_swtoe) || (DRV_SWTOE_CNX_INVALID == sk->ss_swtoe_cnx)) ++ { ++ return -1; ++ } ++ ++ if (*timeo == 0) ++ { ++ return drv_swtoe_rx_data_avail(sk->ss_swtoe_cnx); ++ } ++/* ++ if (sk->sk_err || ++ sock_flag(sk, SOCK_DONE) || (sk->sk_shutdown & RCV_SHUTDOWN)) ++ return 0; ++*/ ++ ++ prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE); ++ set_bit(SOCKWQ_ASYNC_WAITDATA, &sk->sk_socket->flags); ++ rc = sk_wait_event(sk, timeo, _SWTOE_RX_DATA_READY); ++ clear_bit(SOCKWQ_ASYNC_WAITDATA, &sk->sk_socket->flags); ++ finish_wait(sk_sleep(sk), &wait); ++ ++ return rc; ++} ++ ++static int _tcp_recvmsg_swtoe(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, ++ int flags, int *addr_len) ++{ ++ int copied = 0; ++ int target; /* Read at least this many bytes */ ++ long timeo; ++ drv_swtoe_rx_data* p_rxq_data = NULL; ++ drv_swtoe_rx_data* p_prev = NULL; ++ char* p_data; ++ int copy; ++ ++ timeo = sock_rcvtimeo(sk, nonblock); ++ target = sock_rcvlowat(sk, flags & MSG_WAITALL, len); ++ ++ do { ++ if (copied >= target) ++ { ++ break; ++ } ++ ++ if (p_rxq_data) ++ { ++ if (p_rxq_data->offset == p_rxq_data->data_size) ++ { ++ if (flags & MSG_PEEK) ++ { ++ p_rxq_data->offset = 0; ++ p_prev = p_rxq_data; ++ p_rxq_data = NULL; ++ } ++ else ++ { ++ drv_swtoe_rx_data_free(sk->ss_swtoe_cnx, p_rxq_data, 1); ++ p_prev = p_rxq_data = NULL; ++ } ++ } ++ else ++ { ++ p_prev = NULL; ++ } ++ } ++ if (!p_rxq_data) ++ drv_swtoe_rx_data_get(sk->ss_swtoe_cnx, p_prev, &p_rxq_data); ++ ++ if (p_rxq_data) ++ { ++ copy = p_rxq_data->data_size - p_rxq_data->offset; ++ copy = min_t(size_t, target, copy); ++ ++ if (!copy) /// should this happen??? ++ { ++ break; ++ } ++ ++ if (!(flags & MSG_TRUNC)) ++ { ++ int done; ++ p_data = p_rxq_data->data + p_rxq_data->offset; ++ done = copy_to_iter(p_data, copy, &msg->msg_iter); ++ if (done != copy) ++ { ++ panic("[%s][%d] copy_to_iter fail (copy, done) = (%d, %d)\n", __FUNCTION__, __LINE__, copy, done); ++ } ++ } ++ p_rxq_data->offset += copy; ++ len -= copy; ++ copied += copy; ++ } ++ ++ if (copied){ ++ if (sk->sk_err || ++ sk->sk_state == TCP_CLOSE || ++ (sk->sk_shutdown & RCV_SHUTDOWN) || ++ !timeo || ++ signal_pending(current)) ++ { ++ break; ++ } ++ } else { ++ if (sock_flag(sk, SOCK_DONE)) ++ { ++ break; ++ } ++ ++ if (sk->sk_err) { ++ copied = sock_error(sk); ++ break; ++ } ++ ++ if (sk->sk_shutdown & RCV_SHUTDOWN) ++ { ++ break; ++ } ++ ++ if (sk->sk_state == TCP_CLOSE) { ++ if (!sock_flag(sk, SOCK_DONE)) { ++ /* This occurs when user tries to read ++ * from never connected socket. ++ */ ++ copied = -ENOTCONN; ++ break; ++ } ++ break; ++ } ++ ++ if (!timeo) { /// Richard : Yes && drv_swtoe_rx_data_get has no data ++ copied = -EAGAIN; ++ break; ++ } ++ ++ if (signal_pending(current)) { ++ copied = sock_intr_errno(timeo); ++ break; ++ } ++ } ++ ++ if ((!p_rxq_data) && (copied < target)) ++ { ++ _swtoe_tcp_wait_data(sk, &timeo); ++ } ++ } while (len > 0); ++ ++ return copied; ++} ++ ++#endif ++ + /* + * This routine copies from a sock struct into the user buffer. + * +@@ -1672,13 +1970,22 @@ int tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, + seq = &peek_seq; + } + ++#ifdef CONFIG_SS_SWTOE_TCP ++ if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ { ++ copied = _tcp_recvmsg_swtoe(sk, msg, len, nonblock, flags, addr_len); ++ release_sock(sk); ++ return copied; ++ } ++#endif ++ + target = sock_rcvlowat(sk, flags & MSG_WAITALL, len); + + do { + u32 offset; + + /* Are we at urgent data? Stop if we have read anything or have SIGURG pending. */ +- if (tp->urg_data && tp->urg_seq == *seq) { ++ if (tp->urg_data && tp->urg_seq == *seq) { // Richard : do NOT care + if (copied) + break; + if (signal_pending(current)) { +@@ -1717,10 +2024,11 @@ int tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, + + /* Well, if we have backlog, try to process it now yet. */ + +- if (copied >= target && !sk->sk_backlog.tail) ++ if (copied >= target && !sk->sk_backlog.tail) /// Richard : ending condition + break; + + if (copied) { ++ /// Richard : Yes + if (sk->sk_err || + sk->sk_state == TCP_CLOSE || + (sk->sk_shutdown & RCV_SHUTDOWN) || +@@ -1728,18 +2036,18 @@ int tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, + signal_pending(current)) + break; + } else { +- if (sock_flag(sk, SOCK_DONE)) ++ if (sock_flag(sk, SOCK_DONE)) /// Richard : Yes + break; + +- if (sk->sk_err) { ++ if (sk->sk_err) { /// Richard : Yes + copied = sock_error(sk); + break; + } + +- if (sk->sk_shutdown & RCV_SHUTDOWN) ++ if (sk->sk_shutdown & RCV_SHUTDOWN) /// Richard : Yes + break; + +- if (sk->sk_state == TCP_CLOSE) { ++ if (sk->sk_state == TCP_CLOSE) { /// Richard : Yes + if (!sock_flag(sk, SOCK_DONE)) { + /* This occurs when user tries to read + * from never connected socket. +@@ -1750,12 +2058,12 @@ int tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, + break; + } + +- if (!timeo) { ++ if (!timeo) { /// Richard : Yes + copied = -EAGAIN; + break; + } + +- if (signal_pending(current)) { ++ if (signal_pending(current)) { /// Richard : Yes + copied = sock_intr_errno(timeo); + break; + } +@@ -1763,7 +2071,7 @@ int tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, + + tcp_cleanup_rbuf(sk, copied); + +- if (!sysctl_tcp_low_latency && tp->ucopy.task == user_recv) { ++ if (!sysctl_tcp_low_latency && tp->ucopy.task == user_recv) { /// Richard : NO + /* Install new reader */ + if (!user_recv && !(flags & (MSG_TRUNC | MSG_PEEK))) { + user_recv = current; +@@ -1808,12 +2116,12 @@ int tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, int nonblock, + /* __ Set realtime policy in scheduler __ */ + } + +- if (copied >= target) { ++ if (copied >= target) { /// Richard : NO + /* Do not sleep, just process backlog. */ + release_sock(sk); + lock_sock(sk); + } else { +- sk_wait_data(sk, &timeo, last); ++ sk_wait_data(sk, &timeo, last); /// Richard : Yes + } + + if (user_recv) { +@@ -1857,7 +2165,7 @@ do_prequeue: + used = len; + + /* Do we have urgent data here? */ +- if (tp->urg_data) { ++ if (tp->urg_data) { /// Richard : NO + u32 urg_offset = tp->urg_seq - *seq; + if (urg_offset < used) { + if (!urg_offset) { +@@ -1874,7 +2182,7 @@ do_prequeue: + } + } + +- if (!(flags & MSG_TRUNC)) { ++ if (!(flags & MSG_TRUNC)) { /// Richard : Yes already + err = skb_copy_datagram_msg(skb, offset, msg, used); + if (err) { + /* Exception. Bailout! */ +@@ -2038,6 +2346,18 @@ void tcp_shutdown(struct sock *sk, int how) + if (!(how & SEND_SHUTDOWN)) + return; + ++ // @FIXME : not a good implementation ++ #ifdef CONFIG_SS_SWTOE_TCP ++ if (sk->ss_swtoe) ++ { ++ drv_swtoe_shutdown(sk->ss_swtoe_cnx); ++ sk->ss_swtoe = 0; ++ sk->ss_swtoe_cnx = DRV_SWTOE_CNX_INVALID; ++ sk->ss_swtoe_blk = 0; ++ return; ++ } ++ #endif ++ + /* If we've already sent a FIN, or it's a closed state, skip this. */ + if ((1 << sk->sk_state) & + (TCPF_ESTABLISHED | TCPF_SYN_SENT | +@@ -2072,6 +2392,19 @@ void tcp_close(struct sock *sk, long timeout) + lock_sock(sk); + sk->sk_shutdown = SHUTDOWN_MASK; + ++ // @FIXME : not a good implementation ++ #ifdef CONFIG_SS_SWTOE_TCP ++ if (sk->ss_swtoe) ++ { ++ drv_swtoe_close(sk->ss_swtoe_cnx); ++ sk_stream_wait_close(sk, timeout); ++ sk->ss_swtoe = 0; ++ sk->ss_swtoe_cnx = DRV_SWTOE_CNX_INVALID; ++ sk->ss_swtoe_blk = 0; ++ goto adjudge_to_death; ++ } ++ #endif ++ + if (sk->sk_state == TCP_LISTEN) { + tcp_set_state(sk, TCP_CLOSE); + +@@ -2271,7 +2604,12 @@ int tcp_disconnect(struct sock *sk, int flags) + /* The last check adjusts for discrepancy of Linux wrt. RFC + * states + */ ++#ifdef CONFIG_SS_SWTOE_TCP ++ if (!sk->ss_swtoe) ++ { + tcp_send_active_reset(sk, gfp_any()); ++ } ++#endif + sk->sk_err = ECONNRESET; + } else if (old_state == TCP_SYN_SENT) + sk->sk_err = ECONNRESET; +@@ -2322,6 +2660,17 @@ int tcp_disconnect(struct sock *sk, int flags) + sk->sk_frag.offset = 0; + } + ++#ifdef CONFIG_SS_SWTOE_TCP ++ if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ { ++ if (drv_swtoe_disconnect(sk->ss_swtoe_cnx)) ++ { ++ printk("[%s][%d] drv_swtoe_disconnect %d\n", __FUNCTION__, __LINE__, sk->ss_swtoe_cnx); ++ return -EINVAL;; ++ } ++ } ++#endif ++ + sk->sk_error_report(sk); + return err; + } +@@ -2426,6 +2775,16 @@ static int do_tcp_setsockopt(struct sock *sk, int level, + int val; + int err = 0; + ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + /* These are data/string values, all the others are ints */ + switch (optname) { + case TCP_CONGESTION: { +@@ -2713,6 +3072,16 @@ int tcp_setsockopt(struct sock *sk, int level, int optname, char __user *optval, + { + const struct inet_connection_sock *icsk = inet_csk(sk); + ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + if (level != SOL_TCP) + return icsk->icsk_af_ops->setsockopt(sk, level, optname, + optval, optlen); +@@ -2847,6 +3216,16 @@ static int do_tcp_getsockopt(struct sock *sk, int level, + struct net *net = sock_net(sk); + int val, len; + ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + if (get_user(len, optlen)) + return -EFAULT; + +@@ -3057,6 +3436,16 @@ int tcp_getsockopt(struct sock *sk, int level, int optname, char __user *optval, + { + struct inet_connection_sock *icsk = inet_csk(sk); + ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (DRV_SWTOE_CNX_INVALID != sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + if (level != SOL_TCP) + return icsk->icsk_af_ops->getsockopt(sk, level, optname, + optval, optlen); +@@ -3307,6 +3696,7 @@ void __init tcp_init(void) + unsigned long limit; + unsigned int i; + ++ BUILD_BUG_ON(TCP_MIN_SND_MSS <= MAX_TCP_OPTION_SPACE); + BUILD_BUG_ON(sizeof(struct tcp_skb_cb) > + FIELD_SIZEOF(struct sk_buff, cb)); + +diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c +old mode 100644 +new mode 100755 +index 2f107e46355c..82d503a6640f +--- a/net/ipv4/tcp_input.c ++++ b/net/ipv4/tcp_input.c +@@ -1312,7 +1312,7 @@ static bool tcp_shifted_skb(struct sock *sk, struct sk_buff *skb, + TCP_SKB_CB(skb)->seq += shifted; + + tcp_skb_pcount_add(prev, pcount); +- BUG_ON(tcp_skb_pcount(skb) < pcount); ++ WARN_ON_ONCE(tcp_skb_pcount(skb) < pcount); + tcp_skb_pcount_add(skb, -pcount); + + /* When we're adding to gso_segs == 1, gso_size will be zero, +@@ -1379,6 +1379,21 @@ static int skb_can_shift(const struct sk_buff *skb) + return !skb_headlen(skb) && skb_is_nonlinear(skb); + } + ++int tcp_skb_shift(struct sk_buff *to, struct sk_buff *from, ++ int pcount, int shiftlen) ++{ ++ /* TCP min gso_size is 8 bytes (TCP_MIN_GSO_SIZE) ++ * Since TCP_SKB_CB(skb)->tcp_gso_segs is 16 bits, we need ++ * to make sure not storing more than 65535 * 8 bytes per skb, ++ * even if current MSS is bigger. ++ */ ++ if (unlikely(to->len + shiftlen >= 65535 * TCP_MIN_GSO_SIZE)) ++ return 0; ++ if (unlikely(tcp_skb_pcount(to) + pcount > 65535)) ++ return 0; ++ return skb_shift(to, from, shiftlen); ++} ++ + /* Try collapsing SACK blocks spanning across multiple skbs to a single + * skb. + */ +@@ -1390,6 +1405,7 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb, + struct tcp_sock *tp = tcp_sk(sk); + struct sk_buff *prev; + int mss; ++ int next_pcount; + int pcount = 0; + int len; + int in_sack; +@@ -1487,7 +1503,7 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb, + if (!after(TCP_SKB_CB(skb)->seq + len, tp->snd_una)) + goto fallback; + +- if (!skb_shift(prev, skb, len)) ++ if (!tcp_skb_shift(prev, skb, pcount, len)) + goto fallback; + if (!tcp_shifted_skb(sk, skb, state, pcount, len, mss, dup_sack)) + goto out; +@@ -1506,11 +1522,11 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb, + goto out; + + len = skb->len; +- if (skb_shift(prev, skb, len)) { +- pcount += tcp_skb_pcount(skb); +- tcp_shifted_skb(sk, skb, state, tcp_skb_pcount(skb), len, mss, 0); ++ next_pcount = tcp_skb_pcount(skb); ++ if (tcp_skb_shift(prev, skb, next_pcount, len)) { ++ pcount += next_pcount; ++ tcp_shifted_skb(sk, skb, state, next_pcount, len, mss, 0); + } +- + out: + state->fack_count += pcount; + return prev; +@@ -4084,6 +4100,16 @@ void tcp_fin(struct sock *sk) + { + struct tcp_sock *tp = tcp_sk(sk); + ++#if 0 /// do nothing if toe is on ???? ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + inet_csk_schedule_ack(sk); + + sk->sk_shutdown |= RCV_SHUTDOWN; +@@ -4374,7 +4400,7 @@ static void tcp_ofo_queue(struct sock *sk) + + p = rb_first(&tp->out_of_order_queue); + while (p) { +- skb = rb_entry(p, struct sk_buff, rbnode); ++ skb = rb_to_skb(p); + if (after(TCP_SKB_CB(skb)->seq, tp->rcv_nxt)) + break; + +@@ -4438,7 +4464,7 @@ static int tcp_try_rmem_schedule(struct sock *sk, struct sk_buff *skb, + static void tcp_data_queue_ofo(struct sock *sk, struct sk_buff *skb) + { + struct tcp_sock *tp = tcp_sk(sk); +- struct rb_node **p, *q, *parent; ++ struct rb_node **p, *parent; + struct sk_buff *skb1; + u32 seq, end_seq; + bool fragstolen; +@@ -4496,7 +4522,7 @@ coalesce_done: + parent = NULL; + while (*p) { + parent = *p; +- skb1 = rb_entry(parent, struct sk_buff, rbnode); ++ skb1 = rb_to_skb(parent); + if (before(seq, TCP_SKB_CB(skb1)->seq)) { + p = &parent->rb_left; + continue; +@@ -4540,9 +4566,7 @@ insert: + + merge_right: + /* Remove other segments covered by skb. */ +- while ((q = rb_next(&skb->rbnode)) != NULL) { +- skb1 = rb_entry(q, struct sk_buff, rbnode); +- ++ while ((skb1 = skb_rb_next(skb)) != NULL) { + if (!after(end_seq, TCP_SKB_CB(skb1)->seq)) + break; + if (before(end_seq, TCP_SKB_CB(skb1)->end_seq)) { +@@ -4557,7 +4581,7 @@ merge_right: + tcp_drop(sk, skb1); + } + /* If there is no skb after us, we are the last_skb ! */ +- if (!q) ++ if (!skb1) + tp->ooo_last_skb = skb; + + add_sack: +@@ -4760,7 +4784,7 @@ static struct sk_buff *tcp_skb_next(struct sk_buff *skb, struct sk_buff_head *li + if (list) + return !skb_queue_is_last(list, skb) ? skb->next : NULL; + +- return rb_entry_safe(rb_next(&skb->rbnode), struct sk_buff, rbnode); ++ return skb_rb_next(skb); + } + + static struct sk_buff *tcp_collapse_one(struct sock *sk, struct sk_buff *skb, +@@ -4789,7 +4813,7 @@ static void tcp_rbtree_insert(struct rb_root *root, struct sk_buff *skb) + + while (*p) { + parent = *p; +- skb1 = rb_entry(parent, struct sk_buff, rbnode); ++ skb1 = rb_to_skb(parent); + if (before(TCP_SKB_CB(skb)->seq, TCP_SKB_CB(skb1)->seq)) + p = &parent->rb_left; + else +@@ -4907,27 +4931,22 @@ end: + static void tcp_collapse_ofo_queue(struct sock *sk) + { + struct tcp_sock *tp = tcp_sk(sk); ++ u32 range_truesize, sum_tiny = 0; + struct sk_buff *skb, *head; +- struct rb_node *p; + u32 start, end; + +- p = rb_first(&tp->out_of_order_queue); +- skb = rb_entry_safe(p, struct sk_buff, rbnode); ++ skb = skb_rb_first(&tp->out_of_order_queue); + new_range: + if (!skb) { +- p = rb_last(&tp->out_of_order_queue); +- /* Note: This is possible p is NULL here. We do not +- * use rb_entry_safe(), as ooo_last_skb is valid only +- * if rbtree is not empty. +- */ +- tp->ooo_last_skb = rb_entry(p, struct sk_buff, rbnode); ++ tp->ooo_last_skb = skb_rb_last(&tp->out_of_order_queue); + return; + } + start = TCP_SKB_CB(skb)->seq; + end = TCP_SKB_CB(skb)->end_seq; ++ range_truesize = skb->truesize; + + for (head = skb;;) { +- skb = tcp_skb_next(skb, NULL); ++ skb = skb_rb_next(skb); + + /* Range is terminated when we see a gap or when + * we are at the queue end. +@@ -4935,11 +4954,20 @@ new_range: + if (!skb || + after(TCP_SKB_CB(skb)->seq, end) || + before(TCP_SKB_CB(skb)->end_seq, start)) { +- tcp_collapse(sk, NULL, &tp->out_of_order_queue, +- head, skb, start, end); ++ /* Do not attempt collapsing tiny skbs */ ++ if (range_truesize != head->truesize || ++ end - start >= SKB_WITH_OVERHEAD(SK_MEM_QUANTUM)) { ++ tcp_collapse(sk, NULL, &tp->out_of_order_queue, ++ head, skb, start, end); ++ } else { ++ sum_tiny += range_truesize; ++ if (sum_tiny > sk->sk_rcvbuf >> 3) ++ return; ++ } + goto new_range; + } + ++ range_truesize += skb->truesize; + if (unlikely(before(TCP_SKB_CB(skb)->seq, start))) + start = TCP_SKB_CB(skb)->seq; + if (after(TCP_SKB_CB(skb)->end_seq, end)) +@@ -4954,6 +4982,7 @@ new_range: + * 2) not add too big latencies if thousands of packets sit there. + * (But if application shrinks SO_RCVBUF, we could still end up + * freeing whole queue here) ++ * 3) Drop at least 12.5 % of sk_rcvbuf to avoid malicious attacks. + * + * Return true if queue has shrunk. + */ +@@ -4961,23 +4990,29 @@ static bool tcp_prune_ofo_queue(struct sock *sk) + { + struct tcp_sock *tp = tcp_sk(sk); + struct rb_node *node, *prev; ++ int goal; + + if (RB_EMPTY_ROOT(&tp->out_of_order_queue)) + return false; + + NET_INC_STATS(sock_net(sk), LINUX_MIB_OFOPRUNED); ++ goal = sk->sk_rcvbuf >> 3; + node = &tp->ooo_last_skb->rbnode; + do { + prev = rb_prev(node); + rb_erase(node, &tp->out_of_order_queue); +- tcp_drop(sk, rb_entry(node, struct sk_buff, rbnode)); +- sk_mem_reclaim(sk); +- if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf && +- !tcp_under_memory_pressure(sk)) +- break; ++ goal -= rb_to_skb(node)->truesize; ++ tcp_drop(sk, rb_to_skb(node)); ++ if (!prev || goal <= 0) { ++ sk_mem_reclaim(sk); ++ if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf && ++ !tcp_under_memory_pressure(sk)) ++ break; ++ goal = sk->sk_rcvbuf >> 3; ++ } + node = prev; + } while (node); +- tp->ooo_last_skb = rb_entry(prev, struct sk_buff, rbnode); ++ tp->ooo_last_skb = rb_to_skb(prev); + + /* Reset SACK state. A conforming SACK implementation will + * do the same at a timeout based retransmit. When a connection +@@ -5009,6 +5044,9 @@ static int tcp_prune_queue(struct sock *sk) + else if (tcp_under_memory_pressure(sk)) + tp->rcv_ssthresh = min(tp->rcv_ssthresh, 4U * tp->advmss); + ++ if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) ++ return 0; ++ + tcp_collapse_ofo_queue(sk); + if (!skb_queue_empty(&sk->sk_receive_queue)) + tcp_collapse(sk, &sk->sk_receive_queue, NULL, +@@ -5734,6 +5772,17 @@ static int tcp_rcv_synsent_state_process(struct sock *sk, struct sk_buff *skb, + * state to ESTABLISHED..." + */ + ++#if 0 /// do nothing if toe is on ???? ++#ifdef CONFIG_SS_SWTOE_TCP_CLIENT /// not complete ++ // We are client and complete 3 ways handshaking with server ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + tcp_ecn_rcv_synack(tp, th); + + tcp_init_wl(tp, TCP_SKB_CB(skb)->seq); +diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c +old mode 100644 +new mode 100755 +index b3960738464e..8d58fcf426c8 +--- a/net/ipv4/tcp_ipv4.c ++++ b/net/ipv4/tcp_ipv4.c +@@ -84,6 +84,10 @@ + #include + #include + ++#ifdef CONFIG_SS_SWTOE_TCP ++#include "mdrv_swtoe.h" ++#endif ++ + int sysctl_tcp_tw_reuse __read_mostly; + int sysctl_tcp_low_latency __read_mostly; + +@@ -154,6 +158,21 @@ int tcp_v4_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len) + if (usin->sin_family != AF_INET) + return -EAFNOSUPPORT; + ++#ifdef CONFIG_SS_SWTOE_TCP_CLIENT ++ if (sk->ss_swtoe) ++ { ++ if (drv_swtoe_connect(sk->ss_swtoe_cnx, uaddr, sk->ss_swtoe_blk)) ++ { ++ printk("[%s][%d] swtoe connect fail %d\n", __FUNCTION__, __LINE__, sk->ss_swtoe_cnx); ++ return -EINVAL;; ++ } ++ // tcp_set_state(sk, TCP_SYN_SENT); ++ sk_state_store(sk, TCP_SYN_SENT); ++ sk->sk_gso_type = SKB_GSO_TCPV4; ++ return 0; ++ } ++#endif // #ifdef CONFIG_SS_SWTOE_TCP_CLIENT ++ + nexthop = daddr = usin->sin_addr.s_addr; + inet_opt = rcu_dereference_protected(inet->inet_opt, + lockdep_sock_is_held(sk)); +@@ -1351,6 +1370,17 @@ struct sock *tcp_v4_syn_recv_sock(const struct sock *sk, struct sk_buff *skb, + } else { + newinet->inet_opt = NULL; + } ++#if 0 /// do nothing or assert if toe is on ???? ++#ifdef CONFIG_SS_SWTOE_TCP_SERVER /// not complete /// todo. should be done by callback ++ // We are server and complete 3 ways handshaking with client ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + return newsk; + + exit_overflow: +@@ -1391,6 +1421,18 @@ int tcp_v4_do_rcv(struct sock *sk, struct sk_buff *skb) + { + struct sock *rsk; + ++#if 0 /// do nothing or assert if toe is on ???? ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ should be empty ++ // We are client and complete 3 ways handshaking with server ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + if (sk->sk_state == TCP_ESTABLISHED) { /* Fast path */ + struct dst_entry *dst = sk->sk_rx_dst; + +@@ -1859,6 +1901,17 @@ void tcp_v4_destroy_sock(struct sock *sk) + { + struct tcp_sock *tp = tcp_sk(sk); + ++#if 0 /// forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // We are client and complete 3 ways handshaking with server ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + tcp_clear_xmit_timers(sk); + + tcp_cleanup_congestion_control(sk); +diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c +old mode 100644 +new mode 100755 +index 3d7b59ecc76c..93826679bb93 +--- a/net/ipv4/tcp_output.c ++++ b/net/ipv4/tcp_output.c +@@ -800,6 +800,18 @@ void tcp_release_cb(struct sock *sk) + struct tcp_sock *tp = tcp_sk(sk); + unsigned long flags, nflags; + ++#if 0 /// do not know what it is. forget it at this stage ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // what's this? should be empty? ++ // We are client and complete 3 ways handshaking with server ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ // or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + /* perform an atomic operation only if at least one flag is set */ + do { + flags = tp->tsq_flags; +@@ -1343,8 +1355,8 @@ static inline int __tcp_mtu_to_mss(struct sock *sk, int pmtu) + mss_now -= icsk->icsk_ext_hdr_len; + + /* Then reserve room for full set of TCP options and 8 bytes of data */ +- if (mss_now < 48) +- mss_now = 48; ++ if (mss_now < TCP_MIN_SND_MSS) ++ mss_now = TCP_MIN_SND_MSS; + return mss_now; + } + +@@ -2928,6 +2940,17 @@ void tcp_send_fin(struct sock *sk) + struct sk_buff *skb, *tskb = tcp_write_queue_tail(sk); + struct tcp_sock *tp = tcp_sk(sk); + ++#if 0 /// do nothing or assert if toe is on ???? ++#ifdef CONFIG_SS_SWTOE_TCP /// not complete ++ // We are client and complete 3 ways handshaking with server ++ // [TBD] IPC for toe? ++ // if ((sk->ss_swtoe) && (INVALID == sk->ss_swtoe_cnx)) ++ // { ++ // } ++ or add this in sk->sky_prot->shutdown ++#endif ++#endif ++ + /* Optimization, tack on the FIN if we have one skb in write queue and + * this skb was not yet sent, or we are under memory pressure. + * Note: in the latter case, FIN packet will be sent after a timeout, +diff --git a/net/ipv6/datagram.c b/net/ipv6/datagram.c +index 38062f403ceb..57e76f94d900 100644 +--- a/net/ipv6/datagram.c ++++ b/net/ipv6/datagram.c +@@ -569,7 +569,8 @@ void ip6_datagram_recv_common_ctl(struct sock *sk, struct msghdr *msg, + struct sk_buff *skb) + { + struct ipv6_pinfo *np = inet6_sk(sk); +- bool is_ipv6 = skb->protocol == htons(ETH_P_IPV6); ++ static bool is_ipv6; ++ is_ipv6 = skb->protocol == htons(ETH_P_IPV6); + + if (np->rxopt.bits.rxinfo) { + struct in6_pktinfo src_info; +diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c +index a30e7e925c9b..1eb5c5b8dcf8 100644 +--- a/net/ipv6/ip6mr.c ++++ b/net/ipv6/ip6mr.c +@@ -1666,6 +1666,10 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns + struct net *net = sock_net(sk); + struct mr6_table *mrt; + ++ if (sk->sk_type != SOCK_RAW || ++ inet_sk(sk)->inet_num != IPPROTO_ICMPV6) ++ return -EOPNOTSUPP; ++ + mrt = ip6mr_get_table(net, raw6_sk(sk)->ip6mr_table ? : RT6_TABLE_DFLT); + if (!mrt) + return -ENOENT; +@@ -1677,9 +1681,6 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns + + switch (optname) { + case MRT6_INIT: +- if (sk->sk_type != SOCK_RAW || +- inet_sk(sk)->inet_num != IPPROTO_ICMPV6) +- return -EOPNOTSUPP; + if (optlen < sizeof(int)) + return -EINVAL; + +@@ -1815,6 +1816,10 @@ int ip6_mroute_getsockopt(struct sock *sk, int optname, char __user *optval, + struct net *net = sock_net(sk); + struct mr6_table *mrt; + ++ if (sk->sk_type != SOCK_RAW || ++ inet_sk(sk)->inet_num != IPPROTO_ICMPV6) ++ return -EOPNOTSUPP; ++ + mrt = ip6mr_get_table(net, raw6_sk(sk)->ip6mr_table ? : RT6_TABLE_DFLT); + if (!mrt) + return -ENOENT; +diff --git a/net/ipv6/netfilter/nf_conntrack_reasm.c b/net/ipv6/netfilter/nf_conntrack_reasm.c +index b263bf3a19f7..7905d092f8fa 100644 +--- a/net/ipv6/netfilter/nf_conntrack_reasm.c ++++ b/net/ipv6/netfilter/nf_conntrack_reasm.c +@@ -63,7 +63,6 @@ struct nf_ct_frag6_skb_cb + static struct inet_frags nf_frags; + + #ifdef CONFIG_SYSCTL +-static int zero; + + static struct ctl_table nf_ct_frag6_sysctl_table[] = { + { +@@ -76,18 +75,17 @@ static struct ctl_table nf_ct_frag6_sysctl_table[] = { + { + .procname = "nf_conntrack_frag6_low_thresh", + .data = &init_net.nf_frag.frags.low_thresh, +- .maxlen = sizeof(unsigned int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, +- .extra1 = &zero, ++ .proc_handler = proc_doulongvec_minmax, + .extra2 = &init_net.nf_frag.frags.high_thresh + }, + { + .procname = "nf_conntrack_frag6_high_thresh", + .data = &init_net.nf_frag.frags.high_thresh, +- .maxlen = sizeof(unsigned int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, ++ .proc_handler = proc_doulongvec_minmax, + .extra1 = &init_net.nf_frag.frags.low_thresh + }, + { } +@@ -152,23 +150,6 @@ static inline u8 ip6_frag_ecn(const struct ipv6hdr *ipv6h) + return 1 << (ipv6_get_dsfield(ipv6h) & INET_ECN_MASK); + } + +-static unsigned int nf_hash_frag(__be32 id, const struct in6_addr *saddr, +- const struct in6_addr *daddr) +-{ +- net_get_random_once(&nf_frags.rnd, sizeof(nf_frags.rnd)); +- return jhash_3words(ipv6_addr_hash(saddr), ipv6_addr_hash(daddr), +- (__force u32)id, nf_frags.rnd); +-} +- +- +-static unsigned int nf_hashfn(const struct inet_frag_queue *q) +-{ +- const struct frag_queue *nq; +- +- nq = container_of(q, struct frag_queue, q); +- return nf_hash_frag(nq->id, &nq->saddr, &nq->daddr); +-} +- + static void nf_ct_frag6_expire(unsigned long data) + { + struct frag_queue *fq; +@@ -177,30 +158,23 @@ static void nf_ct_frag6_expire(unsigned long data) + fq = container_of((struct inet_frag_queue *)data, struct frag_queue, q); + net = container_of(fq->q.net, struct net, nf_frag.frags); + +- ip6_expire_frag_queue(net, fq, &nf_frags); ++ ip6_expire_frag_queue(net, fq); + } + + /* Creation primitives. */ +-static inline struct frag_queue *fq_find(struct net *net, __be32 id, +- u32 user, struct in6_addr *src, +- struct in6_addr *dst, int iif, u8 ecn) ++static struct frag_queue *fq_find(struct net *net, __be32 id, u32 user, ++ const struct ipv6hdr *hdr, int iif) + { ++ struct frag_v6_compare_key key = { ++ .id = id, ++ .saddr = hdr->saddr, ++ .daddr = hdr->daddr, ++ .user = user, ++ .iif = iif, ++ }; + struct inet_frag_queue *q; +- struct ip6_create_arg arg; +- unsigned int hash; +- +- arg.id = id; +- arg.user = user; +- arg.src = src; +- arg.dst = dst; +- arg.iif = iif; +- arg.ecn = ecn; + +- local_bh_disable(); +- hash = nf_hash_frag(id, src, dst); +- +- q = inet_frag_find(&net->nf_frag.frags, &nf_frags, &arg, hash); +- local_bh_enable(); ++ q = inet_frag_find(&net->nf_frag.frags, &key); + if (IS_ERR_OR_NULL(q)) { + inet_frag_maybe_warn_overflow(q, pr_fmt()); + return NULL; +@@ -230,7 +204,7 @@ static int nf_ct_frag6_queue(struct frag_queue *fq, struct sk_buff *skb, + + if ((unsigned int)end > IPV6_MAXPLEN) { + pr_debug("offset is too large.\n"); +- return -1; ++ return -EINVAL; + } + + ecn = ip6_frag_ecn(ipv6_hdr(skb)); +@@ -263,7 +237,8 @@ static int nf_ct_frag6_queue(struct frag_queue *fq, struct sk_buff *skb, + * this case. -DaveM + */ + pr_debug("end of fragment not rounded to 8 bytes.\n"); +- return -1; ++ inet_frag_kill(&fq->q); ++ return -EPROTO; + } + if (end > fq->q.len) { + /* Some bits beyond end -> corruption. */ +@@ -355,9 +330,9 @@ found: + return 0; + + discard_fq: +- inet_frag_kill(&fq->q, &nf_frags); ++ inet_frag_kill(&fq->q); + err: +- return -1; ++ return -EINVAL; + } + + /* +@@ -377,7 +352,7 @@ nf_ct_frag6_reasm(struct frag_queue *fq, struct sk_buff *prev, struct net_devic + int payload_len; + u8 ecn; + +- inet_frag_kill(&fq->q, &nf_frags); ++ inet_frag_kill(&fq->q); + + WARN_ON(head == NULL); + WARN_ON(NFCT_FRAG6_CB(head)->offset != 0); +@@ -478,6 +453,7 @@ nf_ct_frag6_reasm(struct frag_queue *fq, struct sk_buff *prev, struct net_devic + else if (head->ip_summed == CHECKSUM_COMPLETE) + head->csum = csum_add(head->csum, fp->csum); + head->truesize += fp->truesize; ++ fp->sk = NULL; + } + sub_frag_mem_limit(fq->q.net, head->truesize); + +@@ -496,6 +472,7 @@ nf_ct_frag6_reasm(struct frag_queue *fq, struct sk_buff *prev, struct net_devic + head->csum); + + fq->q.fragments = NULL; ++ fq->q.rb_fragments = RB_ROOT; + fq->q.fragments_tail = NULL; + + return true; +@@ -566,6 +543,7 @@ find_prev_fhdr(struct sk_buff *skb, u8 *prevhdrp, int *prevhoff, int *fhoff) + + int nf_ct_frag6_gather(struct net *net, struct sk_buff *skb, u32 user) + { ++ u16 savethdr = skb->transport_header; + struct net_device *dev = skb->dev; + int fhoff, nhoff, ret; + struct frag_hdr *fhdr; +@@ -590,8 +568,8 @@ int nf_ct_frag6_gather(struct net *net, struct sk_buff *skb, u32 user) + fhdr = (struct frag_hdr *)skb_transport_header(skb); + + skb_orphan(skb); +- fq = fq_find(net, fhdr->identification, user, &hdr->saddr, &hdr->daddr, +- skb->dev ? skb->dev->ifindex : 0, ip6_frag_ecn(hdr)); ++ fq = fq_find(net, fhdr->identification, user, hdr, ++ skb->dev ? skb->dev->ifindex : 0); + if (fq == NULL) { + pr_debug("Can't find and can't create new queue\n"); + return -ENOMEM; +@@ -599,8 +577,12 @@ int nf_ct_frag6_gather(struct net *net, struct sk_buff *skb, u32 user) + + spin_lock_bh(&fq->q.lock); + +- if (nf_ct_frag6_queue(fq, skb, fhdr, nhoff) < 0) { +- ret = -EINVAL; ++ ret = nf_ct_frag6_queue(fq, skb, fhdr, nhoff); ++ if (ret < 0) { ++ if (ret == -EPROTO) { ++ skb->transport_header = savethdr; ++ ret = 0; ++ } + goto out_unlock; + } + +@@ -615,25 +597,33 @@ int nf_ct_frag6_gather(struct net *net, struct sk_buff *skb, u32 user) + + out_unlock: + spin_unlock_bh(&fq->q.lock); +- inet_frag_put(&fq->q, &nf_frags); ++ inet_frag_put(&fq->q); + return ret; + } + EXPORT_SYMBOL_GPL(nf_ct_frag6_gather); + + static int nf_ct_net_init(struct net *net) + { ++ int res; ++ + net->nf_frag.frags.high_thresh = IPV6_FRAG_HIGH_THRESH; + net->nf_frag.frags.low_thresh = IPV6_FRAG_LOW_THRESH; + net->nf_frag.frags.timeout = IPV6_FRAG_TIMEOUT; +- inet_frags_init_net(&net->nf_frag.frags); +- +- return nf_ct_frag6_sysctl_register(net); ++ net->nf_frag.frags.f = &nf_frags; ++ ++ res = inet_frags_init_net(&net->nf_frag.frags); ++ if (res < 0) ++ return res; ++ res = nf_ct_frag6_sysctl_register(net); ++ if (res < 0) ++ inet_frags_exit_net(&net->nf_frag.frags); ++ return res; + } + + static void nf_ct_net_exit(struct net *net) + { + nf_ct_frags6_sysctl_unregister(net); +- inet_frags_exit_net(&net->nf_frag.frags, &nf_frags); ++ inet_frags_exit_net(&net->nf_frag.frags); + } + + static struct pernet_operations nf_ct_net_ops = { +@@ -645,13 +635,12 @@ int nf_ct_frag6_init(void) + { + int ret = 0; + +- nf_frags.hashfn = nf_hashfn; + nf_frags.constructor = ip6_frag_init; + nf_frags.destructor = NULL; + nf_frags.qsize = sizeof(struct frag_queue); +- nf_frags.match = ip6_frag_match; + nf_frags.frag_expire = nf_ct_frag6_expire; + nf_frags.frags_cache_name = nf_frags_cache_name; ++ nf_frags.rhash_params = ip6_rhash_params; + ret = inet_frags_init(&nf_frags); + if (ret) + goto out; +diff --git a/net/ipv6/proc.c b/net/ipv6/proc.c +index e88bcb8ff0fd..dc04c024986c 100644 +--- a/net/ipv6/proc.c ++++ b/net/ipv6/proc.c +@@ -38,7 +38,6 @@ + static int sockstat6_seq_show(struct seq_file *seq, void *v) + { + struct net *net = seq->private; +- unsigned int frag_mem = ip6_frag_mem(net); + + seq_printf(seq, "TCP6: inuse %d\n", + sock_prot_inuse_get(net, &tcpv6_prot)); +@@ -48,7 +47,9 @@ static int sockstat6_seq_show(struct seq_file *seq, void *v) + sock_prot_inuse_get(net, &udplitev6_prot)); + seq_printf(seq, "RAW6: inuse %d\n", + sock_prot_inuse_get(net, &rawv6_prot)); +- seq_printf(seq, "FRAG6: inuse %u memory %u\n", !!frag_mem, frag_mem); ++ seq_printf(seq, "FRAG6: inuse %u memory %lu\n", ++ atomic_read(&net->ipv6.frags.rhashtable.nelems), ++ frag_mem_limit(&net->ipv6.frags)); + return 0; + } + +diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c +index e585c0a2591c..af195cbbc689 100644 +--- a/net/ipv6/reassembly.c ++++ b/net/ipv6/reassembly.c +@@ -79,57 +79,17 @@ static struct inet_frags ip6_frags; + static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, + struct net_device *dev); + +-/* +- * callers should be careful not to use the hash value outside the ipfrag_lock +- * as doing so could race with ipfrag_hash_rnd being recalculated. +- */ +-static unsigned int inet6_hash_frag(__be32 id, const struct in6_addr *saddr, +- const struct in6_addr *daddr) +-{ +- net_get_random_once(&ip6_frags.rnd, sizeof(ip6_frags.rnd)); +- return jhash_3words(ipv6_addr_hash(saddr), ipv6_addr_hash(daddr), +- (__force u32)id, ip6_frags.rnd); +-} +- +-static unsigned int ip6_hashfn(const struct inet_frag_queue *q) +-{ +- const struct frag_queue *fq; +- +- fq = container_of(q, struct frag_queue, q); +- return inet6_hash_frag(fq->id, &fq->saddr, &fq->daddr); +-} +- +-bool ip6_frag_match(const struct inet_frag_queue *q, const void *a) +-{ +- const struct frag_queue *fq; +- const struct ip6_create_arg *arg = a; +- +- fq = container_of(q, struct frag_queue, q); +- return fq->id == arg->id && +- fq->user == arg->user && +- ipv6_addr_equal(&fq->saddr, arg->src) && +- ipv6_addr_equal(&fq->daddr, arg->dst) && +- (arg->iif == fq->iif || +- !(ipv6_addr_type(arg->dst) & (IPV6_ADDR_MULTICAST | +- IPV6_ADDR_LINKLOCAL))); +-} +-EXPORT_SYMBOL(ip6_frag_match); +- + void ip6_frag_init(struct inet_frag_queue *q, const void *a) + { + struct frag_queue *fq = container_of(q, struct frag_queue, q); +- const struct ip6_create_arg *arg = a; ++ const struct frag_v6_compare_key *key = a; + +- fq->id = arg->id; +- fq->user = arg->user; +- fq->saddr = *arg->src; +- fq->daddr = *arg->dst; +- fq->ecn = arg->ecn; ++ q->key.v6 = *key; ++ fq->ecn = 0; + } + EXPORT_SYMBOL(ip6_frag_init); + +-void ip6_expire_frag_queue(struct net *net, struct frag_queue *fq, +- struct inet_frags *frags) ++void ip6_expire_frag_queue(struct net *net, struct frag_queue *fq) + { + struct net_device *dev = NULL; + +@@ -138,7 +98,7 @@ void ip6_expire_frag_queue(struct net *net, struct frag_queue *fq, + if (fq->q.flags & INET_FRAG_COMPLETE) + goto out; + +- inet_frag_kill(&fq->q, frags); ++ inet_frag_kill(&fq->q); + + rcu_read_lock(); + dev = dev_get_by_index_rcu(net, fq->iif); +@@ -146,10 +106,6 @@ void ip6_expire_frag_queue(struct net *net, struct frag_queue *fq, + goto out_rcu_unlock; + + __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMFAILS); +- +- if (inet_frag_evicting(&fq->q)) +- goto out_rcu_unlock; +- + __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMTIMEOUT); + + /* Don't send error if the first segment did not arrive. */ +@@ -166,7 +122,7 @@ out_rcu_unlock: + rcu_read_unlock(); + out: + spin_unlock(&fq->q.lock); +- inet_frag_put(&fq->q, frags); ++ inet_frag_put(&fq->q); + } + EXPORT_SYMBOL(ip6_expire_frag_queue); + +@@ -178,27 +134,26 @@ static void ip6_frag_expire(unsigned long data) + fq = container_of((struct inet_frag_queue *)data, struct frag_queue, q); + net = container_of(fq->q.net, struct net, ipv6.frags); + +- ip6_expire_frag_queue(net, fq, &ip6_frags); ++ ip6_expire_frag_queue(net, fq); + } + + static struct frag_queue * +-fq_find(struct net *net, __be32 id, const struct in6_addr *src, +- const struct in6_addr *dst, int iif, u8 ecn) ++fq_find(struct net *net, __be32 id, const struct ipv6hdr *hdr, int iif) + { ++ struct frag_v6_compare_key key = { ++ .id = id, ++ .saddr = hdr->saddr, ++ .daddr = hdr->daddr, ++ .user = IP6_DEFRAG_LOCAL_DELIVER, ++ .iif = iif, ++ }; + struct inet_frag_queue *q; +- struct ip6_create_arg arg; +- unsigned int hash; + +- arg.id = id; +- arg.user = IP6_DEFRAG_LOCAL_DELIVER; +- arg.src = src; +- arg.dst = dst; +- arg.iif = iif; +- arg.ecn = ecn; ++ if (!(ipv6_addr_type(&hdr->daddr) & (IPV6_ADDR_MULTICAST | ++ IPV6_ADDR_LINKLOCAL))) ++ key.iif = 0; + +- hash = inet6_hash_frag(id, src, dst); +- +- q = inet_frag_find(&net->ipv6.frags, &ip6_frags, &arg, hash); ++ q = inet_frag_find(&net->ipv6.frags, &key); + if (IS_ERR_OR_NULL(q)) { + inet_frag_maybe_warn_overflow(q, pr_fmt()); + return NULL; +@@ -359,7 +314,7 @@ found: + return -1; + + discard_fq: +- inet_frag_kill(&fq->q, &ip6_frags); ++ inet_frag_kill(&fq->q); + err: + __IP6_INC_STATS(net, ip6_dst_idev(skb_dst(skb)), + IPSTATS_MIB_REASMFAILS); +@@ -386,7 +341,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, + int sum_truesize; + u8 ecn; + +- inet_frag_kill(&fq->q, &ip6_frags); ++ inet_frag_kill(&fq->q); + + ecn = ip_frag_ecn_table[fq->ecn]; + if (unlikely(ecn == 0xff)) +@@ -504,6 +459,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, + __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMOKS); + rcu_read_unlock(); + fq->q.fragments = NULL; ++ fq->q.rb_fragments = RB_ROOT; + fq->q.fragments_tail = NULL; + return 1; + +@@ -525,6 +481,7 @@ static int ipv6_frag_rcv(struct sk_buff *skb) + struct frag_queue *fq; + const struct ipv6hdr *hdr = ipv6_hdr(skb); + struct net *net = dev_net(skb_dst(skb)->dev); ++ int iif; + + if (IP6CB(skb)->flags & IP6SKB_FRAGMENTED) + goto fail_hdr; +@@ -553,17 +510,18 @@ static int ipv6_frag_rcv(struct sk_buff *skb) + return 1; + } + +- fq = fq_find(net, fhdr->identification, &hdr->saddr, &hdr->daddr, +- skb->dev ? skb->dev->ifindex : 0, ip6_frag_ecn(hdr)); ++ iif = skb->dev ? skb->dev->ifindex : 0; ++ fq = fq_find(net, fhdr->identification, hdr, iif); + if (fq) { + int ret; + + spin_lock(&fq->q.lock); + ++ fq->iif = iif; + ret = ip6_frag_queue(fq, skb, fhdr, IP6CB(skb)->nhoff); + + spin_unlock(&fq->q.lock); +- inet_frag_put(&fq->q, &ip6_frags); ++ inet_frag_put(&fq->q); + return ret; + } + +@@ -584,24 +542,22 @@ static const struct inet6_protocol frag_protocol = { + }; + + #ifdef CONFIG_SYSCTL +-static int zero; + + static struct ctl_table ip6_frags_ns_ctl_table[] = { + { + .procname = "ip6frag_high_thresh", + .data = &init_net.ipv6.frags.high_thresh, +- .maxlen = sizeof(int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, ++ .proc_handler = proc_doulongvec_minmax, + .extra1 = &init_net.ipv6.frags.low_thresh + }, + { + .procname = "ip6frag_low_thresh", + .data = &init_net.ipv6.frags.low_thresh, +- .maxlen = sizeof(int), ++ .maxlen = sizeof(unsigned long), + .mode = 0644, +- .proc_handler = proc_dointvec_minmax, +- .extra1 = &zero, ++ .proc_handler = proc_doulongvec_minmax, + .extra2 = &init_net.ipv6.frags.high_thresh + }, + { +@@ -709,19 +665,27 @@ static void ip6_frags_sysctl_unregister(void) + + static int __net_init ipv6_frags_init_net(struct net *net) + { ++ int res; ++ + net->ipv6.frags.high_thresh = IPV6_FRAG_HIGH_THRESH; + net->ipv6.frags.low_thresh = IPV6_FRAG_LOW_THRESH; + net->ipv6.frags.timeout = IPV6_FRAG_TIMEOUT; ++ net->ipv6.frags.f = &ip6_frags; + +- inet_frags_init_net(&net->ipv6.frags); ++ res = inet_frags_init_net(&net->ipv6.frags); ++ if (res < 0) ++ return res; + +- return ip6_frags_ns_sysctl_register(net); ++ res = ip6_frags_ns_sysctl_register(net); ++ if (res < 0) ++ inet_frags_exit_net(&net->ipv6.frags); ++ return res; + } + + static void __net_exit ipv6_frags_exit_net(struct net *net) + { + ip6_frags_ns_sysctl_unregister(net); +- inet_frags_exit_net(&net->ipv6.frags, &ip6_frags); ++ inet_frags_exit_net(&net->ipv6.frags); + } + + static struct pernet_operations ip6_frags_ops = { +@@ -729,14 +693,55 @@ static struct pernet_operations ip6_frags_ops = { + .exit = ipv6_frags_exit_net, + }; + ++static u32 ip6_key_hashfn(const void *data, u32 len, u32 seed) ++{ ++ return jhash2(data, ++ sizeof(struct frag_v6_compare_key) / sizeof(u32), seed); ++} ++ ++static u32 ip6_obj_hashfn(const void *data, u32 len, u32 seed) ++{ ++ const struct inet_frag_queue *fq = data; ++ ++ return jhash2((const u32 *)&fq->key.v6, ++ sizeof(struct frag_v6_compare_key) / sizeof(u32), seed); ++} ++ ++static int ip6_obj_cmpfn(struct rhashtable_compare_arg *arg, const void *ptr) ++{ ++ const struct frag_v6_compare_key *key = arg->key; ++ const struct inet_frag_queue *fq = ptr; ++ ++ return !!memcmp(&fq->key, key, sizeof(*key)); ++} ++ ++const struct rhashtable_params ip6_rhash_params = { ++ .head_offset = offsetof(struct inet_frag_queue, node), ++ .hashfn = ip6_key_hashfn, ++ .obj_hashfn = ip6_obj_hashfn, ++ .obj_cmpfn = ip6_obj_cmpfn, ++ .automatic_shrinking = true, ++}; ++EXPORT_SYMBOL(ip6_rhash_params); ++ + int __init ipv6_frag_init(void) + { + int ret; + +- ret = inet6_add_protocol(&frag_protocol, IPPROTO_FRAGMENT); ++ ip6_frags.constructor = ip6_frag_init; ++ ip6_frags.destructor = NULL; ++ ip6_frags.qsize = sizeof(struct frag_queue); ++ ip6_frags.frag_expire = ip6_frag_expire; ++ ip6_frags.frags_cache_name = ip6_frag_cache_name; ++ ip6_frags.rhash_params = ip6_rhash_params; ++ ret = inet_frags_init(&ip6_frags); + if (ret) + goto out; + ++ ret = inet6_add_protocol(&frag_protocol, IPPROTO_FRAGMENT); ++ if (ret) ++ goto err_protocol; ++ + ret = ip6_frags_sysctl_register(); + if (ret) + goto err_sysctl; +@@ -745,16 +750,6 @@ int __init ipv6_frag_init(void) + if (ret) + goto err_pernet; + +- ip6_frags.hashfn = ip6_hashfn; +- ip6_frags.constructor = ip6_frag_init; +- ip6_frags.destructor = NULL; +- ip6_frags.qsize = sizeof(struct frag_queue); +- ip6_frags.match = ip6_frag_match; +- ip6_frags.frag_expire = ip6_frag_expire; +- ip6_frags.frags_cache_name = ip6_frag_cache_name; +- ret = inet_frags_init(&ip6_frags); +- if (ret) +- goto err_pernet; + out: + return ret; + +@@ -762,6 +757,8 @@ err_pernet: + ip6_frags_sysctl_unregister(); + err_sysctl: + inet6_del_protocol(&frag_protocol, IPPROTO_FRAGMENT); ++err_protocol: ++ inet_frags_fini(&ip6_frags); + goto out; + } + +diff --git a/net/irda/af_irda.c b/net/irda/af_irda.c +index 101ed6c42808..4497d78281e0 100644 +--- a/net/irda/af_irda.c ++++ b/net/irda/af_irda.c +@@ -2016,7 +2016,11 @@ static int irda_setsockopt(struct socket *sock, int level, int optname, + err = -EINVAL; + goto out; + } +- irias_insert_object(ias_obj); ++ ++ /* Only insert newly allocated objects */ ++ if (free_ias) ++ irias_insert_object(ias_obj); ++ + kfree(ias_opt); + break; + case IRLMP_IAS_DEL: +diff --git a/net/rds/tcp.c b/net/rds/tcp.c +index d36effbf7614..2daba5316caa 100644 +--- a/net/rds/tcp.c ++++ b/net/rds/tcp.c +@@ -527,7 +527,7 @@ static void rds_tcp_kill_sock(struct net *net) + list_for_each_entry_safe(tc, _tc, &rds_tcp_conn_list, t_tcp_node) { + struct net *c_net = read_pnet(&tc->t_cpath->cp_conn->c_net); + +- if (net != c_net || !tc->t_sock) ++ if (net != c_net) + continue; + if (!list_has_conn(&tmp_list, tc->t_cpath->cp_conn)) { + list_move_tail(&tc->t_tcp_node, &tmp_list); +diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c +index 91722e97cdd5..df48121471c4 100644 +--- a/net/wireless/nl80211.c ++++ b/net/wireless/nl80211.c +@@ -213,6 +213,36 @@ cfg80211_get_dev_from_info(struct net *netns, struct genl_info *info) + return __cfg80211_rdev_from_attrs(netns, info->attrs); + } + ++static int validate_beacon_head(const struct nlattr *attr) ++{ ++ const u8 *data = nla_data(attr); ++ unsigned int len = nla_len(attr); ++ const struct element *elem; ++ const struct ieee80211_mgmt *mgmt = (void *)data; ++ unsigned int fixedlen = offsetof(struct ieee80211_mgmt, ++ u.beacon.variable); ++ ++ if (len < fixedlen) ++ goto err; ++ ++ if (ieee80211_hdrlen(mgmt->frame_control) != ++ offsetof(struct ieee80211_mgmt, u.beacon)) ++ goto err; ++ ++ data += fixedlen; ++ len -= fixedlen; ++ ++ for_each_element(elem, data, len) { ++ /* nothing */ ++ } ++ ++ if (for_each_element_completed(elem, data, len)) ++ return 0; ++ ++err: ++ return -EINVAL; ++} ++ + /* policy for the attributes */ + static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = { + [NL80211_ATTR_WIPHY] = { .type = NLA_U32 }, +@@ -3677,6 +3707,11 @@ static int nl80211_parse_beacon(struct nlattr *attrs[], + memset(bcn, 0, sizeof(*bcn)); + + if (attrs[NL80211_ATTR_BEACON_HEAD]) { ++ int ret = validate_beacon_head(attrs[NL80211_ATTR_BEACON_HEAD]); ++ ++ if (ret) ++ return ret; ++ + bcn->head = nla_data(attrs[NL80211_ATTR_BEACON_HEAD]); + bcn->head_len = nla_len(attrs[NL80211_ATTR_BEACON_HEAD]); + if (!bcn->head_len) +diff --git a/net/wireless/scan.c b/net/wireless/scan.c +index 35ad69fd0838..a3bd221cfb7b 100644 +--- a/net/wireless/scan.c ++++ b/net/wireless/scan.c +@@ -407,6 +407,8 @@ const u8 *cfg80211_find_ie_match(u8 eid, const u8 *ies, int len, + const u8 *match, int match_len, + int match_offset) + { ++ const struct element *elem; ++ + /* match_offset can't be smaller than 2, unless match_len is + * zero, in which case match_offset must be zero as well. + */ +@@ -414,14 +416,10 @@ const u8 *cfg80211_find_ie_match(u8 eid, const u8 *ies, int len, + (!match_len && match_offset))) + return NULL; + +- while (len >= 2 && len >= ies[1] + 2) { +- if ((ies[0] == eid) && +- (ies[1] + 2 >= match_offset + match_len) && +- !memcmp(ies + match_offset, match, match_len)) +- return ies; +- +- len -= ies[1] + 2; +- ies += ies[1] + 2; ++ for_each_element_id(elem, eid, ies, len) { ++ if (elem->datalen >= match_offset - 2 + match_len && ++ !memcmp(elem->data + match_offset - 2, match, match_len)) ++ return (void *)elem; + } + + return NULL; +diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c +index 5d33967d9aa1..da6faed60fed 100644 +--- a/net/xfrm/xfrm_user.c ++++ b/net/xfrm/xfrm_user.c +@@ -1335,7 +1335,7 @@ static int verify_newpolicy_info(struct xfrm_userpolicy_info *p) + ret = verify_policy_dir(p->dir); + if (ret) + return ret; +- if (p->index && ((p->index & XFRM_POLICY_MAX) != p->dir)) ++ if (p->index && (xfrm_policy_id2dir(p->index) != p->dir)) + return -EINVAL; + + return 0; +diff --git a/release_kernel_to_alkaid.sh b/release_kernel_to_alkaid.sh +new file mode 100755 +index 000000000000..8f31f0ce4b30 +--- /dev/null ++++ b/release_kernel_to_alkaid.sh +@@ -0,0 +1,1258 @@ ++#!/bin/bash ++ ++while getopts "a:c:j:" opt; do ++ case $opt in ++ a) ++ alkaid_dir=$OPTARG ++ ;; ++ c) ++ chip=$OPTARG ++ ;; ++ j) ++ jobs=$OPTARG ++ ;; ++ \?) ++ echo "Invalid option: -$OPTARG" >&2 ++ ;; ++ esac ++done ++if [ "${jobs}" = "" ] ++then ++ echo ++ echo "Set default 2 jobs for make" ++ jobs=2 ++fi ++ ++kernel_dir=$PWD ++uImage_dir=${kernel_dir}/arch/arm/boot ++LD_ADDR=0x20008000 ++MKIMAGE_BIN=scripts/mkimage ++MZ_BIN=scripts/mz ++TOOL_DIR=scripts/dtc ++ ++function replace_dtb_to_kernel() ++{ ++ echo CROSS_COMPILE=$1 ++ CC=$1 ++ echo dts-name=$2 ++ dtb_name=$2 ++ # build dtb ++ ${CC}gcc -E -nostdinc -I${uImage_dir}/dts -I${uImage_dir}/dts/include -undef -D__DTS__ -x assembler-with-cpp -o ${uImage_dir}/dts/${dtb_name}.dtb.tmp ${uImage_dir}/dts/${dtb_name}.dts ++ ${TOOL_DIR}/dtc -O dtb -o ${uImage_dir}/dts/${dtb_name}.dtb -b 0 ${uImage_dir}/dts/${dtb_name}.dtb.tmp ++ python scripts/ms_builtin_dtb_update.py ${uImage_dir}/Image ${uImage_dir}/dts/${dtb_name}.dtb ++ IMGNAME=$(strings -a -T binary ${uImage_dir}/Image | grep 'MVX' | grep 'LX' | sed 's/\\*MVX/MVX/g' | cut -c 1-32) ++ # uImage ++ ${MKIMAGE_BIN} -A arm -O linux -T kernel -C none -a ${LD_ADDR} -e ${LD_ADDR} -n ${IMGNAME} -d ${uImage_dir}/Image ${uImage_dir}/uImage ++ # xz Image ++ xz -z -k -f ${uImage_dir}/Image ++ ${MKIMAGE_BIN} -A arm -O linux -C lzma -a ${LD_ADDR} -e ${LD_ADDR} -n ${IMGNAME} -d ${uImage_dir}/Image.xz ${uImage_dir}/uImage.xz ++ # mz Image ++ ${MZ_BIN} c ${uImage_dir}/Image ${uImage_dir}/Image.mz ++ ${MKIMAGE_BIN} -A arm -O linux -C mz -a ${LD_ADDR} -e ${LD_ADDR} -n ${IMGNAME} -d ${uImage_dir}/Image.mz ${uImage_dir}/uImage.mz ++} ++ ++ ++if [ "${chip}" = "i5" ] ++then ++ ########################## gclibc 4.8.3 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/arm-linux-gnueabihf-4.8.3-201404/bin:$PATH" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ whereis ${CROSS_COMPILE}gcc ++ ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/4.9.84/" ++ ++ echo "infinity5_ssc007a_s01a_spinand_defconfig" ++ make infinity5_ssc007a_s01a_spinand_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007A -p ipc -f spinand -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007a_s01a_defconfig" ++ make infinity5_ssc007a_s01a_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007A -p ipc -f nor -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007b_s01b_spinand_defconfig" ++ make infinity5_ssc007b_s01b_spinand_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007B -p ipc -f spinand -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007b_s01b_defconfig" ++ make infinity5_ssc007b_s01b_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007B -p ipc -f nor -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007a_s01a_spinand_uvc_defconfig" ++ make infinity5_ssc007a_s01a_spinand_uvc_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007A -p usb_cam -f spinand -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007a_s01a_uvc_defconfig" ++ make infinity5_ssc007a_s01a_uvc_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007A -p usb_cam -f nor -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007b_s01b_spinand_uvc_defconfig" ++ make infinity5_ssc007b_s01b_spinand_uvc_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007B -p usb_cam -f spinand -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007b_s01b_uvc_defconfig" ++ make infinity5_ssc007b_s01b_uvc_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007B -p usb_cam -f nor -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007a_s01a_coprocessor_defconfig" ++ make infinity5_ssc007a_s01a_coprocessor_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007A -p cop -f nor -o glibc ++ cd ${kernel_dir} ++ ++ echo "infinity5_ssc007a_s01a_spinand_coprocessor_defconfig" ++ make infinity5_ssc007a_s01a_spinand_coprocessor_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007A -p cop -f spinand -o glibc ++ cd ${kernel_dir} ++ ++ ########################## uclibc ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/arm-buildroot-linux-uclibcgnueabihf-4.9.4/bin" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-buildroot-linux-uclibcgnueabihf-" ++ whereis ${CROSS_COMPILE}gcc ++ ++ echo "infinity5_ssc007b_s01b_defconfig" ++ make infinity5_ssc007b_s01b_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 007B -p ipc -f nor -o uclibc ++ cd ${kernel_dir} ++fi ++if [ "${chip}" = "i6" ] ++then ++ ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_defconfig ++ make infinity6_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f nor -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_uvc_defconfig ++ make infinity6_uvc_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f nor -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_uvc_fastboot_defconfig ++ make infinity6_uvc_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A-fastboot -p usbcam -f nor -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_ssc009b_s01a_defconfig ++ make infinity6_ssc009b_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f nor -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_spinand_defconfig ++ make infinity6_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f spinand -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_spinand_uvc_defconfig ++ make infinity6_spinand_uvc_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f spinand -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_ssc009b_s01a_spinand_defconfig ++ make infinity6_ssc009b_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f spinand -c i6 -l glibc -v 8.2.1 ++ cd ${kernel_dir} ++ ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-buildroot-linux-uclibcgnueabihf-" ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_defconfig ++ make infinity6_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f nor -c i6 -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_uvc_defconfig ++ make infinity6_uvc_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f nor -c i6 -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_uvc_fastboot_defconfig ++ make infinity6_uvc_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A-fastboot -p usbcam -f nor -c i6 -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_ssc009b_s01a_defconfig ++ make infinity6_ssc009b_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f nor -c i6 -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ declare -x PATH="/tools/toolchain/arm-linux-gnueabihf-4.8.3-201404/bin:$PATH" ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_defconfig ++ make infinity6_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f nor -c i6 -l glibc -v 4.8.3 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_ssc009b_s01a_defconfig ++ make infinity6_ssc009b_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f nor -c i6 -l glibc -v 4.8.3 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_spinand_defconfig ++ make infinity6_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f spinand -c i6 -l glibc -v 4.8.3 ++ cd ${kernel_dir} ++ ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ echo make infinity6_ssc009b_s01a_spinand_defconfig ++ make infinity6_ssc009b_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f spinand -c i6 -l glibc -v 4.8.3 ++ cd ${kernel_dir} ++fi ++ ++if [ "${chip}" = "i6_dualos" ] ++then ++ ++ # infinity6_ssc009a_s01a_lh_defconfig --> DualOS QFN88 for spinand ++ # infinity6_ssc009a_s01a_lh_defconfig --> DualOS QFN88 for nor ++ # infinity6_ssc009b_s01a_lh_defconfig --> DualOS QFN128 for spinand ++ ++ ########################## gclibc 8.2.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-arm-8.2-2018.08-x86_64-arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ env ++ ++ PRODUCT_TYPE="ipc-rtos" ++ CHIP_TYPE="i6" ++ CLIB="glibc" ++ GCC_VERSION="8.2.1" ++ API_VERSION="4.9.84" ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/${API_VERSION}/" ++ ++ # SPI_NAND Ramdisk 009A ++ BOARD_TYPE="009A" ++ FLASH_TYPE="spinand" ++ KERNEL_DECONFIG="infinity6_ssc009a_s01a_lh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # SPI_NOR Ramdisk 009A ++ BOARD_TYPE="009A" ++ FLASH_TYPE="nor" ++ KERNEL_DECONFIG="infinity6_ssc009a_s01a_lh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # SPI_NAND Ramdisk 009B ++ BOARD_TYPE="009B" ++ FLASH_TYPE="spinand" ++ KERNEL_DECONFIG="infinity6_ssc009a_s01a_lh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++fi ++ ++if [ "${chip}" = "i2m" ] ++then ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ GCC_VERSION=$(${CROSS_COMPILE}gcc --version | head -n 1 | sed -e 's/.*\([0-9]\.[0-9]\.[0-9]\).*/\1/') ++ echo GCC_VERSION=${GCC_VERSION} ++ ++ # NVR SPI_NAND ++ echo "infinity2m_spinand_ssc010a_s01a_defconfig" ++ make infinity2m_spinand_ssc010a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A -p nvr -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # NVR SPI_NOR ++ echo "infinity2m_ssc010a_s01a_defconfig" ++ make infinity2m_ssc010a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A -p nvr -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # NVR SPI_NAND ++ echo "infinity2m_spinand_ssc010a_ssr623_s01a_defconfig" ++ make infinity2m_spinand_ssc010a_ssr623_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A-623 -p nvr -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # NVR SPI_NOR ++ echo "infinity2m_ssc010a_ssr623_s01a_defconfig" ++ make infinity2m_ssc010a_ssr623_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A-623 -p nvr -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ ++ # P2 SPI_NAND ++ echo "infinity2m_spinand_ssc011a_s01a_defconfig" ++ make infinity2m_spinand_ssc011a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A -p nvr -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # P2 SPI_NOR ++ echo "infinity2m_ssc011a_s01a_defconfig" ++ make infinity2m_ssc011a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A -p nvr -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ ++ echo "infinity2m_ssc011a_s01a_fastboot_defconfig" ++ make infinity2m_ssc011a_s01a_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A-fastboot -p nvr -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ echo "infinity2m_ssc011a_s01a_minigui_defconfig" ++ make infinity2m_ssc011a_s01a_minigui_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A-cus -p nvr -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ echo "infinity2m_spinand_ssc011a_s01a_minigui_defconfig" ++ make infinity2m_spinand_ssc011a_s01a_minigui_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A-cus -p nvr -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-buildroot-linux-uclibcgnueabihf-" ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ GCC_VERSION=$(${CROSS_COMPILE}gcc --version | head -n 1 | sed -e 's/.*\([0-9]\.[0-9]\.[0-9]\).*/\1/') ++ echo GCC_VERSION=${GCC_VERSION} ++ ++ # NVR SPI_NAND ++ echo "infinity2m_spinand_ssc010a_s01a_defconfig" ++ make infinity2m_spinand_ssc010a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A -p nvr -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # NVR SPI_NOR ++ echo "infinity2m_ssc010a_s01a_defconfig" ++ make infinity2m_ssc010a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A -p nvr -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # P2 SPI_NAND ++ echo "infinity2m_spinand_ssc011a_s01a_defconfig" ++ make infinity2m_spinand_ssc011a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A -p nvr -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # P2 SPI_NOR ++ echo "infinity2m_ssc011a_s01a_defconfig" ++ make infinity2m_ssc011a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 011A -p nvr -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++fi ++ ++if [ "${chip}" = "i2m-dualos-amp" ] ++then ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ GCC_VERSION=$(${CROSS_COMPILE}gcc --version | head -n 1 | sed -e 's/.*\([0-9]\.[0-9]\.[0-9]\).*/\1/') ++ echo GCC_VERSION=${GCC_VERSION} ++ ++ # NVR SPI_NAND ++ echo "infinity2m_spinand_ssc010a_s01a_swtoe_defconfig" ++ make infinity2m_spinand_ssc010a_s01a_swtoe_defconfig ++ #echo "infinity2m_spinand_ssc010a_s01a_amp_defconfig" ++ #make infinity2m_spinand_ssc010a_s01a_amp_defconfig ++ ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 010A -p nvr-rtos -f spinand -c i2m -l glibc -v ${GCC_VERSION} -i 4.9.84 ++ cd ${kernel_dir} ++fi ++ ++if [ "${chip}" = "i6e" ] ++then ++ ########################## gclibc 8.2.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-arm-8.2-2018.08-x86_64-arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ whereis ${CROSS_COMPILE}gcc ++ ++ GCC_VERSION=8.2.1 ++ API_VERSION="4.9.84" ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/${API_VERSION}/" ++ ++ # cardv DEMO SPI_NOR ++ echo make infinity6e_ssc013a_s01a_miniGUI_defconfig [${GCC_VERSION}] ++ make infinity6e_ssc013a_s01a_miniGUI_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b DEMO -p cardv -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ echo make infinity6e_ssc013a_s01a_miniGUI_fastboot_defconfig [${GCC_VERSION}] ++ make infinity6e_ssc013a_s01a_miniGUI_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b DEMO-fastboot -p cardv -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ########################## gclibc 9.1.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-sigmastar-9.1.0-2019.11-x86_64_arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-9.1.0-" ++ whereis ${CROSS_COMPILE}gcc ++ ++ GCC_VERSION=9.1.0 ++ ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_defconfig ++ make infinity6e_ssc012b_s01a_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 015A SPI_NOR ++ echo make infinity6e_ssc015a_s01a_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc015a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 015A -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_defconfig ++ make infinity6e_ssc012b_s01a_spinand_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 015A SPI_NAND ++ echo make infinity6e_ssc015a_s01a_spinand_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc015a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 015A -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ## ipcam fastboot ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_spinand_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ##### for usbcam ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_usbcam_defconfig ++ make infinity6e_ssc012b_s01a_usbcam_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p usbcam -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_usbcam_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p usbcam -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_usbcam_defconfig ++ make infinity6e_ssc012b_s01a_spinand_usbcam_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p usbcam -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_usbcam_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p usbcam -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ## usbcam fastboot ++ echo make infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p usbcam -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_usbcam_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p usbcam -f nor -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p usbcam -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_usbcam_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p usbcam -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ########################## uclibc ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/arm-buildroot-linux-uclibcgnueabihf-4.9.4/bin" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-buildroot-linux-uclibcgnueabihf-" ++ whereis ${CROSS_COMPILE}gcc ++ GCC_VERSION=$(${CROSS_COMPILE}gcc --version | head -n 1 | sed -e 's/.*\([0-9]\.[0-9]\.[0-9]\).*/\1/') ++ ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_defconfig ++ make infinity6e_ssc012b_s01a_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p ipc -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p ipc -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 015A SPI_NOR ++ echo make infinity6e_ssc015a_s01a_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc015a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 015A -p ipc -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_defconfig ++ make infinity6e_ssc012b_s01a_spinand_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p ipc -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p ipc -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 015A SPI_NAND ++ echo make infinity6e_ssc015a_s01a_spinand_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc015a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 015A -p ipc -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ## ipcam fastboot ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p ipc -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p ipc -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_spinand_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p ipc -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p ipc -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ## usbcam ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_usbcam_defconfig ++ make infinity6e_ssc012b_s01a_usbcam_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p usbcam -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_usbcam_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p usbcam -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_usbcam_defconfig ++ make infinity6e_ssc012b_s01a_spinand_usbcam_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B -p usbcam -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_usbcam_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A -p usbcam -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ ## usbcam fastboot ++ # 012B SPI_NOR ++ echo make infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_usbcam_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p usbcam -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NOR ++ echo make infinity6e_ssc013a_s01a_usbcam_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p usbcam -f nor -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 012B SPI_NAND ++ echo make infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig ++ make infinity6e_ssc012b_s01a_spinand_usbcam_fastboot_defconfig; make clean; make -j ${jobs} ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 012B-fastboot -p usbcam -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ echo make infinity6e_ssc013a_s01a_spinand_usbcam_fastboot_defconfig ++ replace_dtb_to_kernel ${CROSS_COMPILE} infinity6e-ssc013a-s01a ++ cd ${RELEASE_PATH} ++ ./release.sh -k ${kernel_dir} -b 013A-fastboot -p usbcam -f spinand -c ${chip} -l uclibc -v ${GCC_VERSION} -i ${API_VERSION} ++ cd ${kernel_dir} ++fi ++ ++if [ "${chip}" = "i6e-dualos-amp" ] ++then ++ # infinity6e_ssc012b_s01a_spinand_amp_defconfig -> dualOS QFN for spinand ++ # infinity6e_ssc013a_s01a_spinand_amp_defconfig -> dualOS BGA for spinand ++ ++ ########################## gclibc 8.2.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-arm-8.2-2018.08-x86_64-arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ env ++ ++ FLASH_TYPE="spinand" ++ CHIP_TYPE="i6e" ++ CLIB="glibc" ++ GCC_VERSION="8.2.1" ++ API_VERSION="4.9.84" ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/${API_VERSION}/" ++ ++ # 012B SPI_NAND ++ BOARD_TYPE="012B" ++ PRODUCT_TYPE="ipc-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc012b_s01a_spinand_amp_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ BOARD_TYPE="013A" ++ PRODUCT_TYPE="ipc-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc013a_s01a_spinand_amp_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ ##### for usbcam ++ # 012B SPI_NAND (for usbcam) ++ BOARD_TYPE="012B" ++ PRODUCT_TYPE="usbcam-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc012b_s01a_spinand_amp_usbcam_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND (for usbcam) ++ BOARD_TYPE="013A" ++ PRODUCT_TYPE="usbcam-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc013a_s01a_spinand_amp_usbcam_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ ########################## gclibc 9.1.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-sigmastar-9.1.0-2019.11-x86_64_arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-9.1.0-" ++ env ++ ++ FLASH_TYPE="spinand" ++ CHIP_TYPE="i6e" ++ CLIB="glibc" ++ GCC_VERSION="9.1.0" ++ API_VERSION="4.9.84" ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/${API_VERSION}/" ++ ++ # 012B SPI_NAND ++ BOARD_TYPE="012B" ++ PRODUCT_TYPE="ipc-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc012b_s01a_spinand_amp_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ BOARD_TYPE="013A" ++ PRODUCT_TYPE="ipc-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc013a_s01a_spinand_amp_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ ##### for usbcam ++ # 012B SPI_NAND (for usbcam) ++ BOARD_TYPE="012B" ++ PRODUCT_TYPE="usbcam-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc012b_s01a_spinand_amp_usbcam_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND (for usbcam) ++ BOARD_TYPE="013A" ++ PRODUCT_TYPE="usbcam-rtos" ++ KERNEL_DECONFIG="infinity6e_ssc013a_s01a_spinand_amp_usbcam_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++fi ++ ++if [ "${chip}" = "i6e-dualos-smplh" ] ++then ++ # infinity6e_ssc012b_s01a_spinand_smplh_defconfig -> dualOS QFN for spinand ++ # infinity6e_ssc013a_s01a_spinand_smplh_defconfig -> dualOS BGA for spinand ++ ++ ########################## gclibc 8.2.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-arm-8.2-2018.08-x86_64-arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-" ++ env ++ ++ PRODUCT_TYPE="ipc-rtos-smplh" ++ FLASH_TYPE="spinand" ++ CHIP_TYPE="i6e" ++ CLIB="glibc" ++ GCC_VERSION="8.2.1" ++ API_VERSION="4.9.84" ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/${API_VERSION}/" ++ ++ # 012B SPI_NAND ++ BOARD_TYPE="012B" ++ KERNEL_DECONFIG="infinity6e_ssc012b_s01a_spinand_smplh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ BOARD_TYPE="013A" ++ KERNEL_DECONFIG="infinity6e_ssc013a_s01a_spinand_smplh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ ########################## gclibc 9.1.0 ############################### ++ TOOLCHAIN_PATH="/tools/toolchain/gcc-sigmastar-9.1.0-2019.11-x86_64_arm-linux-gnueabihf/bin/" ++ declare -x PATH=${TOOLCHAIN_PATH}:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-9.1.0-" ++ env ++ ++ PRODUCT_TYPE="ipc-rtos-smplh" ++ FLASH_TYPE="spinand" ++ CHIP_TYPE="i6e" ++ CLIB="glibc" ++ GCC_VERSION="9.1.0" ++ API_VERSION="4.9.84" ++ RELEASE_PATH="${alkaid_dir}/project/kbuild/${API_VERSION}/" ++ ++ # 012B SPI_NAND ++ BOARD_TYPE="012B" ++ KERNEL_DECONFIG="infinity6e_ssc012b_s01a_spinand_smplh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++ # 013A SPI_NAND ++ BOARD_TYPE="013A" ++ KERNEL_DECONFIG="infinity6e_ssc013a_s01a_spinand_smplh_defconfig" ++ RELEASE_SCRIPT="./release.sh -k ${kernel_dir} -b ${BOARD_TYPE} -p ${PRODUCT_TYPE} -f ${FLASH_TYPE} -c ${CHIP_TYPE} -l ${CLIB} -v ${GCC_VERSION} -i ${API_VERSION}" ++ echo ${CHIP_TYPE}/${BOARD_TYPE}/${PRODUCT_TYPE}/${FLASH_TYPE}/${CLIB}/GCC_VERSION=${GCC_VERSION}/API_VERSION=${API_VERSION} ++ echo make ${KERNEL_DECONFIG} ++ make ${KERNEL_DECONFIG} ++ make clean;make -j ${jobs} ++ cd ${RELEASE_PATH} ++ echo ${RELEASE_SCRIPT} ++ ${RELEASE_SCRIPT} ++ cd ${kernel_dir} ++ ++fi ++ ++if [ "${chip}" = "i6b0" ] ++then ++ declare -x PATH=/tools/toolchain/gcc-sigmastar-9.1.0-2019.11-x86_64_arm-linux-gnueabihf/bin/:$PATH ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-linux-gnueabihf-9.1.0-" ++ echo CROSS_COMPILE=$CROSS_COMPILE ++ whereis ${CROSS_COMPILE}gcc ++ GCC_VERSION=$(${CROSS_COMPILE}gcc --version | head -n 1 | sed -e 's/.*\([0-9]\.[0-9]\.[0-9]\).*/\1/') ++ echo GCC_VERSION=${GCC_VERSION} ++ ++ ## For ipcam ++ # qfn88 009A SPI_NOR ++ echo "infinity6b0_ssc009a_s01a_defconfig" ++ make infinity6b0_ssc009a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn88 009A SPI_NAND ++ echo "infinity6b0_ssc009a_s01a_spinand_defconfig" ++ make infinity6b0_ssc009a_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn88 009D SPI_NOR ++ echo "infinity6b0_ssc009d_s01a_defconfig" ++ make infinity6b0_ssc009d_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009D -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn88 009D SPI_NAND ++ echo "infinity6b0_ssc009d_s01a_spinand_defconfig" ++ make infinity6b0_ssc009d_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009D -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NOR ++ echo "infinity6b0_ssc009b_s01a_defconfig" ++ make infinity6b0_ssc009b_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NAND ++ echo "infinity6b0_ssc009b_s01a_spinand_defconfig" ++ make infinity6b0_ssc009b_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ ## For ipcam fastboot ++ # qfn88 009A SPI_NOR ++ echo "infinity6b0_ssc009a_s01a_fastboot_defconfig" ++ make infinity6b0_ssc009a_s01a_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A-fastboot -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn88 009A SPI_NAND ++ echo "infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig" ++ make infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A-fastboot -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NOR ++ echo "infinity6b0_ssc009b_s01a_fastboot_defconfig" ++ make infinity6b0_ssc009b_s01a_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B-fastboot -p ipc -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NAND ++ echo "infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig" ++ make infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B-fastboot -p ipc -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ ## For usbcam ++ # qfn88 009A SPI_NOR ++ echo "infinity6b0_ssc009a_s01a_usbcam_defconfig" ++ make infinity6b0_ssc009a_s01a_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn88 009A SPI_NAND ++ echo "infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig" ++ make infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NOR ++ echo "infinity6b0_ssc009b_s01a_usbcam_defconfig" ++ make infinity6b0_ssc009b_s01a_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p usbcam -f nor -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NAND ++ echo "infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig" ++ make infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p usbcam -f spinand -c ${chip} -l glibc -v ${GCC_VERSION} ++ cd ${kernel_dir} ++ ++ declare -x PATH="/tools/toolchain/arm-buildroot-linux-uclibcgnueabihf-4.9.4/bin/:$PATH" ++ declare -x ARCH="arm" ++ declare -x CROSS_COMPILE="arm-buildroot-linux-uclibcgnueabihf-" ++ ++ ## For ipcam ++ # qfn88 009A SPI_NOR ++ echo "infinity6b0_ssc009a_s01a_defconfig" ++ make infinity6b0_ssc009a_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f nor -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ echo "infinity6b0_ssc009a_s01a_spinand_defconfig" ++ make infinity6b0_ssc009a_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p ipc -f spinand -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NOR ++ echo "infinity6b0_ssc009b_s01a_defconfig" ++ make infinity6b0_ssc009b_s01a_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f nor -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NAND ++ echo "infinity6b0_ssc009b_s01a_spinand_defconfig" ++ make infinity6b0_ssc009b_s01a_spinand_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p ipc -f spinand -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ ## for ipcam fastboot ++ # qfn88 009A SPI_NOR ++ echo "infinity6b0_ssc009a_s01a_fastboot_defconfig" ++ make infinity6b0_ssc009a_s01a_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A-fastboot -p ipc -f nor -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ echo "infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig" ++ make infinity6b0_ssc009a_s01a_spinand_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A-fastboot -p ipc -f spinand -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NOR ++ echo "infinity6b0_ssc009b_s01a_fastboot_defconfig" ++ make infinity6b0_ssc009b_s01a_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B-fastboot -p ipc -f nor -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NAND ++ echo "infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig" ++ make infinity6b0_ssc009b_s01a_spinand_fastboot_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B-fastboot -p ipc -f spinand -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ ## For usbcam ++ # qfn88 009A SPI_NOR ++ echo "infinity6b0_ssc009a_s01a_usbcam_defconfig" ++ make infinity6b0_ssc009a_s01a_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f nor -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ echo "infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig" ++ make infinity6b0_ssc009a_s01a_spinand_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009A -p usbcam -f spinand -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NOR ++ echo "infinity6b0_ssc009b_s01a_usbcam_defconfig" ++ make infinity6b0_ssc009b_s01a_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p usbcam -f nor -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++ ++ # qfn128 009B SPI_NAND ++ echo "infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig" ++ make infinity6b0_ssc009b_s01a_spinand_usbcam_defconfig ++ make clean;make -j ${jobs} ++ cd ${alkaid_dir}/project/kbuild/4.9.84/ ++ ./release.sh -k ${kernel_dir} -b 009B -p usbcam -f spinand -c ${chip} -l uclibc -v 4.9.4 ++ cd ${kernel_dir} ++fi +diff --git a/scripts/basic/fixdep.exe b/scripts/basic/fixdep.exe +new file mode 100755 +index 000000000000..6449a019e57f +Binary files /dev/null and b/scripts/basic/fixdep.exe differ +diff --git a/scripts/dtc/dtb2unfdt/build_dtb2unfdt.sh b/scripts/dtc/dtb2unfdt/build_dtb2unfdt.sh +new file mode 100755 +index 000000000000..1d7fcf640c37 +--- /dev/null ++++ b/scripts/dtc/dtb2unfdt/build_dtb2unfdt.sh +@@ -0,0 +1,6 @@ ++rm dtb2unfdt ++ ++gcc dtb2unfdt.c ../libfdt/fdt_ro.c ../libfdt/fdt.c ../util.c -o dtb2unfdt -I.. -I../libfdt -m32 ++ ++#./dtb2dtst ../../../arch/arm/boot/dts/infinity6-ssc009a-s01a-lh.dtb ../../../arch/arm/boot/unfdt.bin ++ +diff --git a/scripts/dtc/dtb2unfdt/dtb2unfdt b/scripts/dtc/dtb2unfdt/dtb2unfdt +new file mode 100755 +index 000000000000..a2be8ad42939 +Binary files /dev/null and b/scripts/dtc/dtb2unfdt/dtb2unfdt differ +diff --git a/scripts/dtc/dtb2unfdt/dtb2unfdt.c b/scripts/dtc/dtb2unfdt/dtb2unfdt.c +new file mode 100755 +index 000000000000..229b7aed04de +--- /dev/null ++++ b/scripts/dtc/dtb2unfdt/dtb2unfdt.c +@@ -0,0 +1,529 @@ ++/* ++ * dtb2unfdt.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++//#include ++//#include ++#include ++#include ++ ++#include "dtb2unfdt.h" ++ ++//#include ++#define EINVAL 22 /* Invalid argument */ ++ ++//=================== ++#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) ++#define PALIGN(p, a) ((void *)(ALIGN((unsigned long)(p), (a)))) ++#define GET_CELL(p) (p += 4, *((const uint32_t *)(p-4))) ++#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) //linux/kernel.h ++ ++//=================== ++#define pr_warn printf ++#define pr_debug ++#define pr_warning printf ++#define pr_err printf ++#define WARN_ON_ONCE(x) (x) ++ ++//=================== ++//convert be32_to_cpu/cpu_to_be32 ++#include ++#define cpu_to_be32(x) htonl((uint32_t )x) ++#define be32_to_cpu(x) ntohl((uint32_t )x) ++ ++//=================== ++#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2)) ++#define of_prop_cmp(s1, s2) strcmp((s1), (s2)) ++#define of_node_cmp(s1, s2) strcasecmp((s1), (s2)) ++ ++ ++static struct property *__of_find_property(const struct device_node *np, ++ const char *name, int *lenp) ++{ ++ struct property *pp; ++ ++ if (!np) ++ return NULL; ++ ++ for (pp = np->properties; pp; pp = pp->next) { ++ if (of_prop_cmp(pp->name, name) == 0) { ++ if (lenp) ++ *lenp = pp->length; ++ break; ++ } ++ } ++ ++ return pp; ++} ++struct property *of_find_property(const struct device_node *np, ++ const char *name, ++ int *lenp) ++{ ++ struct property *pp; ++ //unsigned long flags; ++ ++ //raw_spin_lock_irqsave(&devtree_lock, flags); ++ pp = __of_find_property(np, name, lenp); ++ //raw_spin_unlock_irqrestore(&devtree_lock, flags); ++ ++ return pp; ++} ++const void *of_get_property(const struct device_node *np, const char *name, ++ int *lenp) ++{ ++ struct property *pp = of_find_property(np, name, lenp); ++ ++ return pp ? pp->value : NULL; ++} ++//================= ++static void *unflatten_dt_alloc(void **mem, unsigned long size, ++ unsigned long align) ++{ ++ void *res; ++ ++ *mem = PTR_ALIGN(*mem, align); ++ res = *mem; ++ *mem += size; ++ ++ return res; ++} ++ ++static void populate_properties(const void *blob, ++ int offset, ++ void **mem, ++ struct device_node *np, ++ const char *nodename, ++ bool dryrun) ++{ ++ struct property *pp, **pprev = NULL; ++ int cur; ++ bool has_name = false; ++ ++ pprev = &np->properties; ++ for (cur = fdt_first_property_offset(blob, offset); ++ cur >= 0; ++ cur = fdt_next_property_offset(blob, cur)) { ++ const __be32 *val; ++ const char *pname; ++ u32 sz; ++ ++ val = fdt_getprop_by_offset(blob, cur, &pname, &sz); ++ if (!val) { ++ pr_warn("Cannot locate property at 0x%x\n", cur); ++ continue; ++ } ++ ++ if (!pname) { ++ pr_warn("Cannot find property name at 0x%x\n", cur); ++ continue; ++ } ++ ++ if (!strcmp(pname, "name")) ++ has_name = true; ++ ++ pp = unflatten_dt_alloc(mem, sizeof(struct property), ++ __alignof__(struct property)); ++ if (dryrun) ++ continue; ++ ++ /* We accept flattened tree phandles either in ++ * ePAPR-style "phandle" properties, or the ++ * legacy "linux,phandle" properties. If both ++ * appear and have different values, things ++ * will get weird. Don't do that. ++ */ ++ if (!strcmp(pname, "phandle") || ++ !strcmp(pname, "linux,phandle")) { ++ if (!np->phandle) ++ np->phandle = be32_to_cpu(*val); ++ } ++ ++ /* And we process the "ibm,phandle" property ++ * used in pSeries dynamic device tree ++ * stuff ++ */ ++ if (!strcmp(pname, "ibm,phandle")) ++ np->phandle = be32_to_cpu(*val); ++ ++ pp->name = (char *)pname; ++ pp->length = sz; ++ pp->value = (__be32 *)val; ++ *pprev = pp; ++ pprev = &pp->next; ++ } ++ ++ /* With version 0x10 we may not have the name property, ++ * recreate it here from the unit name if absent ++ */ ++ if (!has_name) { ++ const char *p = nodename, *ps = p, *pa = NULL; ++ int len; ++ ++ while (*p) { ++ if ((*p) == '@') ++ pa = p; ++ else if ((*p) == '/') ++ ps = p + 1; ++ p++; ++ } ++ ++ if (pa < ps) ++ pa = p; ++ len = (pa - ps) + 1; ++ pp = unflatten_dt_alloc(mem, sizeof(struct property) + len, ++ __alignof__(struct property)); ++ if (!dryrun) { ++ pp->name = "name"; ++ pp->length = len; ++ pp->value = pp + 1; ++ *pprev = pp; ++ pprev = &pp->next; ++ memcpy(pp->value, ps, len - 1); ++ ((char *)pp->value)[len - 1] = 0; ++ pr_debug("fixed up name for %s -> %s\n", ++ nodename, (char *)pp->value); ++ } ++ } ++ ++ if (!dryrun) ++ *pprev = NULL; ++} ++ ++static unsigned int populate_node(const void *blob, ++ int offset, ++ void **mem, ++ struct device_node *dad, ++ unsigned int fpsize, ++ struct device_node **pnp, ++ bool dryrun) ++{ ++ struct device_node *np; ++ const char *pathp; ++ unsigned int l, allocl; ++ int new_format = 0; ++ ++ pathp = fdt_get_name(blob, offset, &l); ++ if (!pathp) { ++ *pnp = NULL; ++ return 0; ++ } ++ ++ allocl = ++l; ++ ++ /* version 0x10 has a more compact unit name here instead of the full ++ * path. we accumulate the full path size using "fpsize", we'll rebuild ++ * it later. We detect this because the first character of the name is ++ * not '/'. ++ */ ++ if ((*pathp) != '/') { ++ new_format = 1; ++ if (fpsize == 0) { ++ /* root node: special case. fpsize accounts for path ++ * plus terminating zero. root node only has '/', so ++ * fpsize should be 2, but we want to avoid the first ++ * level nodes to have two '/' so we use fpsize 1 here ++ */ ++ fpsize = 1; ++ allocl = 2; ++ l = 1; ++ pathp = ""; ++ } else { ++ /* account for '/' and path size minus terminal 0 ++ * already in 'l' ++ */ ++ fpsize += l; ++ allocl = fpsize; ++ } ++ } ++ ++ np = unflatten_dt_alloc(mem, sizeof(struct device_node) + allocl, ++ __alignof__(struct device_node)); ++ if (!dryrun) { ++ char *fn; ++ //of_node_init(np); ++ np->full_name = fn = ((char *)np) + sizeof(*np); ++ if (new_format) { ++ /* rebuild full path for new format */ ++ if (dad && dad->parent) { ++ strcpy(fn, dad->full_name); ++#ifdef DEBUG ++ if ((strlen(fn) + l + 1) != allocl) { ++ pr_debug("%s: p: %d, l: %d, a: %d\n", ++ pathp, (int)strlen(fn), ++ l, allocl); ++ } ++#endif ++ fn += strlen(fn); ++ } ++ *(fn++) = '/'; ++ } ++ memcpy(fn, pathp, l); ++ ++ if (dad != NULL) { ++ np->parent = dad; ++ np->sibling = dad->child; ++ dad->child = np; ++ } ++ } ++ ++ populate_properties(blob, offset, mem, np, pathp, dryrun); ++ if (!dryrun) { ++ np->name = of_get_property(np, "name", NULL); ++ np->type = of_get_property(np, "device_type", NULL); ++ ++ if (!np->name) ++ np->name = ""; ++ if (!np->type) ++ np->type = ""; ++ } ++ ++ *pnp = np; ++ return fpsize; ++} ++ ++static void reverse_nodes(struct device_node *parent) ++{ ++ struct device_node *child, *next; ++ ++ /* In-depth first */ ++ child = parent->child; ++ while (child) { ++ reverse_nodes(child); ++ ++ child = child->sibling; ++ } ++ ++ /* Reverse the nodes in the child list */ ++ child = parent->child; ++ parent->child = NULL; ++ while (child) { ++ next = child->sibling; ++ ++ child->sibling = parent->child; ++ parent->child = child; ++ child = next; ++ } ++} ++ ++/** ++ * unflatten_dt_nodes - Alloc and populate a device_node from the flat tree ++ * @blob: The parent device tree blob ++ * @mem: Memory chunk to use for allocating device nodes and properties ++ * @dad: Parent struct device_node ++ * @nodepp: The device_node tree created by the call ++ * ++ * It returns the size of unflattened device tree or error code ++ */ ++static int unflatten_dt_nodes(const void *blob, ++ void *mem, ++ struct device_node *dad, ++ struct device_node **nodepp) ++{ ++ struct device_node *root; ++ int offset = 0, depth = 0, initial_depth = 0; ++#define FDT_MAX_DEPTH 64 ++ unsigned int fpsizes[FDT_MAX_DEPTH]; ++ struct device_node *nps[FDT_MAX_DEPTH]; ++ void *base = mem; ++ bool dryrun = !base; ++ ++ if (nodepp) ++ *nodepp = NULL; ++ ++ /* ++ * We're unflattening device sub-tree if @dad is valid. There are ++ * possibly multiple nodes in the first level of depth. We need ++ * set @depth to 1 to make fdt_next_node() happy as it bails ++ * immediately when negative @depth is found. Otherwise, the device ++ * nodes except the first one won't be unflattened successfully. ++ */ ++ if (dad) ++ depth = initial_depth = 1; ++ ++ root = dad; ++ fpsizes[depth] = dad ? strlen(of_node_full_name(dad)) : 0; ++ nps[depth] = dad; ++ ++ for (offset = 0; ++ offset >= 0 && depth >= initial_depth; ++ offset = fdt_next_node(blob, offset, &depth)) { ++ if (WARN_ON_ONCE(depth >= FDT_MAX_DEPTH)) ++ continue; ++ ++ fpsizes[depth+1] = populate_node(blob, offset, &mem, ++ nps[depth], ++ fpsizes[depth], ++ &nps[depth+1], dryrun); ++ if (!fpsizes[depth+1]) ++ return mem - base; ++ ++ if (!dryrun && nodepp && !*nodepp) ++ *nodepp = nps[depth+1]; ++ if (!dryrun && !root) ++ root = nps[depth+1]; ++ } ++ ++ if (offset < 0 && offset != -FDT_ERR_NOTFOUND) { ++ pr_err("Error %d processing FDT\n", offset); ++ return -EINVAL; ++ } ++ ++ /* ++ * Reverse the child list. Some drivers assumes node order matches .dts ++ * node order ++ */ ++ if (!dryrun) ++ reverse_nodes(root); ++ ++ return mem - base; ++} ++ ++/** ++ * __unflatten_device_tree - create tree of device_nodes from flat blob ++ * ++ * unflattens a device-tree, creating the ++ * tree of struct device_node. It also fills the "name" and "type" ++ * pointers of the nodes so the normal device-tree walking functions ++ * can be used. ++ * @blob: The blob to expand ++ * @dad: Parent device node ++ * @mynodes: The device_node tree created by the call ++ * @dt_alloc: An allocator that provides a virtual address to memory ++ * for the resulting tree ++ * ++ * Returns NULL on failure or the memory chunk containing the unflattened ++ * device tree on success. ++ */ ++static void *__unflatten_device_tree(const void *blob, ++ struct device_node *dad, ++ struct device_node **mynodes, ++ bool detached, int* unfdt_size) ++{ ++ int size; ++ void *mem; ++ ++ pr_debug(" -> unflatten_device_tree()\n"); ++ ++ if (!blob) { ++ pr_debug("No device tree pointer\n"); ++ return NULL; ++ } ++ ++ ++ pr_err("blob size: 0x%x\n", fdt_totalsize(blob)); ++ pr_err("blob base: 0x%08x\n", (unsigned int)blob); ++ pr_debug(" magic: 0x%08x\n", fdt_magic(blob)); ++ pr_debug("version: 0x%08x\n", fdt_version(blob)); ++ ++ if (fdt_check_header(blob)) { ++ pr_err("Invalid device tree blob header\n"); ++ return NULL; ++ } ++ ++ /* First pass, scan for size */ ++ size = unflatten_dt_nodes(blob, NULL, dad, NULL); ++ if (size < 0) ++ return NULL; ++ ++ ++ size = ALIGN(size, 4); ++ pr_err("unflattened size: 0x%x\n", size); ++ *unfdt_size = size; ++ ++ /* Allocate memory for the expanded device tree */ ++ mem = malloc(size + 4); //mem = dt_alloc(size + 4, __alignof__(struct device_node)); ++ if (!mem) ++ return NULL; ++ ++ memset(mem, 0, size); ++ ++ *(__be32 *)(mem + size) = cpu_to_be32(0xdeadbeef); ++ ++ pr_err("unflattened base: 0x%08x\n", (unsigned int)mem); ++ ++ /* Second pass, do actual unflattening */ ++ unflatten_dt_nodes(blob, mem, dad, mynodes); ++ if (be32_to_cpu(*(__be32 *)(mem + size)) != 0xdeadbeef) ++ pr_warning("End of tree marker overwritten: %08x\n", ++ be32_to_cpu(*(__be32 *)(mem + size))); ++ ++ if (detached && mynodes) { ++ of_node_set_flag(*mynodes, OF_DETACHED); ++ pr_debug("unflattened tree is detached\n"); ++ } ++ ++ pr_debug(" <- unflatten_device_tree()\n"); ++ return mem; ++} ++ ++ ++int main(int argc, char *argv[]) ++{ ++ int fd = 0; /* assume stdin */ ++ char *blob_buf; ++ int unfdt_size; ++ void *unfdt_buf; ++ struct device_node *of_root; ++ char *input_name; ++ char *output_name; ++ FILE *outf = NULL; ++ ++ if (argc < 3) { ++ printf("supply input filename\n"); ++ return 5; ++ } ++ ++ input_name = argv[1]; ++ output_name = argv[2]; ++ printf ("%s: %s\n", " input", input_name); ++ printf ("%s: %s\n", "output", output_name); ++ blob_buf = (char *)utilfdt_read(input_name); ++ ++ ++ unfdt_buf = __unflatten_device_tree(blob_buf, NULL, &of_root, false, &unfdt_size); ++ free(blob_buf); ++ ++#if 1 ++ outf = fopen(output_name, "wb"); ++ if (! outf) ++ printf("Couldn't open output file %s\n", output_name); ++ ++ ++ if (fwrite(&unfdt_buf, 4, 1, outf) != 1) ++ printf("Error writing \n"); ++ ++ if (fwrite(&blob_buf, 4, 1, outf) != 1) ++ printf("Error writing \n"); ++ ++ if (fwrite(unfdt_buf, unfdt_size, 1, outf) != 1) ++ printf("Error writing \n"); ++ ++ fclose(outf); ++#endif ++ ++#if 0 ++ { ++ char (*__kobject)[sizeof(struct kobject)]; ++ printf("%d", __kobject ); //36 ++ } ++ { ++ char (*__property)[sizeof(struct property)]; ++ printf("%d", __property );//target 52 ++ } ++ { ++ char (*__device_node)[sizeof(struct device_node)]; ++ printf("%d", __device_node );//144 target 88 ++ } ++ { ++ char (*__void_p)[sizeof(void *)]; ++ printf("%d", __void_p );//144 target 88 ++ } ++#endif ++ return 0; ++} +diff --git a/scripts/dtc/dtb2unfdt/dtb2unfdt.h b/scripts/dtc/dtb2unfdt/dtb2unfdt.h +new file mode 100755 +index 000000000000..3de67cd6963a +--- /dev/null ++++ b/scripts/dtc/dtb2unfdt/dtb2unfdt.h +@@ -0,0 +1,147 @@ ++//================================== ++//int-ll64.h ++typedef signed char s8; ++typedef unsigned char u8; ++ ++typedef signed short s16; ++typedef unsigned short u16; ++ ++typedef signed int s32; ++typedef unsigned int u32; ++ ++typedef signed long long s64; ++typedef unsigned long long u64; ++ ++//=================== ++//types.h include\uapi\linux ++ ++typedef unsigned short __u16; ++ ++typedef unsigned int __u32; ++ ++typedef __u16 __le16; ++typedef __u16 __be16; ++typedef __u32 __le32; ++typedef __u32 __be32; ++ ++//================== ++//kobject.h include\linux ++ ++//fake ++struct kobject { ++ char padding[36]; ++}; ++ ++ ++//================== ++// include\linux\sysfs.h ++typedef unsigned short umode_t; ++ ++typedef struct attribute { ++ const char *name; ++ umode_t mode; ++#ifdef CONFIG_DEBUG_LOCK_ALLOC ++ bool ignore_lockdep:1; ++ struct lock_class_key *key; ++ struct lock_class_key skey; ++#endif ++}attribute; ++ ++struct bin_attribute { // 28 ++ struct attribute attr; ++ size_t size; ++ void *private; ++ int (*read)(void * para); ++ int (*write)(void * para); ++ int (*mmap)(void * para); ++}; ++ ++ ++//================================== ++//#include ++enum fwnode_type { ++ FWNODE_INVALID = 0, ++ FWNODE_OF, ++ FWNODE_ACPI, ++ FWNODE_ACPI_DATA, ++ FWNODE_PDATA, ++ FWNODE_IRQCHIP, ++}; ++ ++struct fwnode_handle { ++ enum fwnode_type type; ++ struct fwnode_handle *secondary; ++}; ++//================================== ++//of.h ++ ++/* flag descriptions (need to be visible even when !CONFIG_OF) */ ++#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ ++#define OF_DETACHED 2 /* node has been detached from the device tree */ ++#define OF_POPULATED 3 /* device already created for the node */ ++#define OF_POPULATED_BUS 4 /* of_platform_populate recursed to children of this node */ ++ ++#define OF_BAD_ADDR ((u64)-1) ++typedef u32 phandle; ++typedef u32 ihandle; ++//typedef u32 bool; ++ ++struct property { //52 ++ char *name; ++ int length; ++ void *value; ++ struct property *next; ++ unsigned long _flags; ++ unsigned int unique_id; ++ struct bin_attribute attr; ++}; ++ ++struct device_node { //88 ++ const char *name; ++ const char *type; ++ phandle phandle; ++ const char *full_name; ++ struct fwnode_handle fwnode; ++ ++ struct property *properties; ++ struct property *deadprops; /* removed properties */ ++ struct device_node *parent; ++ struct device_node *child; ++ struct device_node *sibling; ++ struct kobject kobj; ++ unsigned long _flags; ++ void *data; ++#if defined(CONFIG_SPARC) ++ const char *path_component_name; ++ unsigned int unique_id; ++ struct of_irq_controller *irq_trans; ++#endif ++}; ++ ++static inline const char *of_node_full_name(const struct device_node *np) ++{ ++ return np ? np->full_name : ""; ++} ++#ifdef CONFIG_64BIT ++#define BITS_PER_LONG 64 ++#else ++#define BITS_PER_LONG 32 ++#endif /* CONFIG_64BIT */ ++#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) ++#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) ++static inline void set_bit(int nr, volatile unsigned long *addr) ++{ ++ unsigned long mask = BIT_MASK(nr); ++ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); ++ unsigned long flags; ++ ++// _atomic_spin_lock_irqsave(p, flags); ++ *p |= mask; ++// _atomic_spin_unlock_irqrestore(p, flags); ++} ++ ++static inline void of_node_set_flag(struct device_node *n, unsigned long flag) ++{ ++ set_bit(flag, &n->_flags); ++} ++ +diff --git a/scripts/dtc/dtc-lexer.lex.c_shipped b/scripts/dtc/dtc-lexer.lex.c_shipped +index ba525c2f9fc2..a2fe8dbc0fd3 100644 +--- a/scripts/dtc/dtc-lexer.lex.c_shipped ++++ b/scripts/dtc/dtc-lexer.lex.c_shipped +@@ -637,7 +637,7 @@ char *yytext; + #include "srcpos.h" + #include "dtc-parser.tab.h" + +-YYLTYPE yylloc; ++extern YYLTYPE yylloc; + extern bool treesource_error; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ +diff --git a/scripts/dtc/fdtdump.c b/scripts/dtc/fdtdump.c +old mode 100644 +new mode 100755 +index 207a46d64864..a78401f66edc +--- a/scripts/dtc/fdtdump.c ++++ b/scripts/dtc/fdtdump.c +@@ -7,9 +7,9 @@ + #include + #include + #include +- +-#include + #include ++#include ++ + + #include "util.h" + +diff --git a/scripts/mkimage b/scripts/mkimage +new file mode 100755 +index 000000000000..26e985cbd4ee +Binary files /dev/null and b/scripts/mkimage differ +diff --git a/scripts/ms_bin_option_get_int.py b/scripts/ms_bin_option_get_int.py +new file mode 100755 +index 000000000000..1049a679e231 +--- /dev/null ++++ b/scripts/ms_bin_option_get_int.py +@@ -0,0 +1,24 @@ ++#!/usr/bin/python ++ ++import re, fnmatch, os, sys, mmap, struct ++ ++if __name__ == '__main__': ++ ++ name=sys.argv[2] ++# if sys.argv[3].upper().startswith( '0X' ): ++# value=long(sys.argv[3],16) ++# else: ++# value=long(sys.argv[3]) ++ ++ fmap=mmap.mmap(os.open(sys.argv[1],os.O_RDWR),0) ++ ++ offset=fmap.find(name) ++# print ('%s:%d\n' % (name,offset)) ++ if offset >= 0: ++ fmap.seek(offset + 8, os.SEEK_SET) ++ if len(sys.argv) > 3 and sys.argv[3].upper()==( '16' ): ++ print ('0x%08X' % struct.unpack(' (64*1024): ++ print ('DTB size 0x%08X too big to fit in 64K limit!!' % dtb.size()) ++ sys.exit() ++ ++ fmap=mmap.mmap(os.open(sys.argv[1],os.O_RDWR),0) ++ ++ offset=fmap.find(name) ++ if offset >=0: ++ print ('offset:0x%08X' % offset) ++ print (' size:0x%08X' % size ) ++ fmap.seek(offset + 8, os.SEEK_SET) ++ fmap.write(struct.pack(' (128*1024): ++ print ('UNFDT size 0x%08X too big!!' % dtb.size()) ++ sys.exit() ++ ++ fmap=mmap.mmap(os.open(sys.argv[1],os.O_RDWR),0) ++ ++ offset=fmap.find(name) ++ if offset >=0: ++ print ('Refill unflatten device tree...') ++ print ('offset:0x%08X' % offset) ++ print (' size:0x%08X' % size ) ++ fmap.seek(offset + 8, os.SEEK_SET) ++ #fmap.write(struct.pack(' 0 : ++ ext_str += ext_val ++ ++ version_file.write('/*\n') ++ version_file.write(' * Modified Information for CEVA XM6 Version Control\n') ++ version_file.write(' */\n') ++ version_file.write('\n') ++ ++ version_file.write('#define CEVA_SRC_VERSION 1 \n') ++ version_file.write('#define CEVA_LOCAL_LIB_VERSION 2 \n') ++ version_file.write('#define CEVA_SUBVERSION 1 \n') ++ ++ version_file.write("\n") ++ version_file.write('#define CEVA_XM6_GIT_BRANCH "' + args.branch + '"\n') ++ version_file.write('#define CEVA_XM6_GIT_VERSION "' + args.gitver + '"\n') ++ version_file.write('#define CEVA_XM6_BUILD_DATE "' + args.builddate + '"\n') ++ version_file.write('#define CEVA_XM6_BUILD_USR "' + args.buildusr + '"\n\n') ++ ++ ++ version_file.write('typedef struct \n') ++ version_file.write('{ \n') ++ version_file.write(' unsigned int Main;\n') ++ version_file.write(' unsigned int Second;\n') ++ version_file.write(' unsigned int Sub;\n') ++ version_file.write('}CEVA_VerCTL_Info;\n') ++ ++ if(args.buildusr == 'causer'): ++ version_file.write('#define SERVER_BUILD 1 \n') ++ else: ++ version_file.write('#define SERVER_BUILD 0 \n') ++ ++ version_file.write("\n") ++ version_file.write('#define VERSION_INFO_LENGTH 128 \n') ++ version_file.write('struct Version_Info{\n') ++ version_file.write(' CEVA_VerCTL_Info CEVA_VInfo;\n') ++ version_file.write(' char GitBranch[VERSION_INFO_LENGTH];\n') ++ version_file.write(' char GitVersion[VERSION_INFO_LENGTH];\n') ++ version_file.write(' char BuildCodeData[VERSION_INFO_LENGTH];\n') ++ version_file.write(' unsigned int FormalReleaseFlg;\n') ++ version_file.write('};\n') ++ version_file.close() +diff --git a/scripts/ms_gen_mvxv_h.py b/scripts/ms_gen_mvxv_h.py +new file mode 100755 +index 000000000000..d0b01715f16f +--- /dev/null ++++ b/scripts/ms_gen_mvxv_h.py +@@ -0,0 +1,71 @@ ++#!/usr/bin/python ++ ++import re, fnmatch, os, sys, subprocess, argparse ++ ++if __name__ == '__main__': ++ parser = argparse.ArgumentParser(description='Generate MVXXVM .h file for P4 system') ++ ++ parser.add_argument("file", help="Output File") ++ parser.add_argument("--changelist", help="Change List String", default="#0000000") ++ parser.add_argument("--lib_type", help="Library Type",default="#") ++ parser.add_argument("--chip_id", help="Chip ID",default="##") ++ parser.add_argument("--comp_id", help="COMP_ID",default="############") ++# parser.add_argument("--p4_change", help="Write the $Change for P4",action="store_true") ++ ++ parser.add_argument("--branch", help="branch") ++ args=parser.parse_args() ++ ++ #print args ++ ++ if args.file is None : ++ print ('ERROR: must specify output header file!!') ++ sys.exit(-1) ++ ++ version_file=open(args.file,'w') ++ ++# if args.p4_change is not None: ++# version_file.write("// $Change: %s $\n" % args.changelist[1:]) ++ ++ while len(args.comp_id) < 10 : ++ args.comp_id += '#' ++ ++ while len(args.chip_id) < 4 : ++ args.chip_id += '#' ++ ++ while len(args.changelist) < 8 : ++ args.changelist += '#' ++ ++ while len(args.lib_type) < 2 : ++ args.lib_type += '#' ++ ++ ext_val='' ++ ext_str='' ++ if args.branch is not None : ++ ext_val += '[BR:' ++ ext_val += args.branch ++ ext_val += ']' ++ ++ if len(ext_val) > 0 : ++ ext_str += ext_val ++ ++ version_file.write('/*\n') ++ version_file.write(' * DO NOT MODIFY.\n') ++ version_file.write(' * This file was generated by ms_gen_mvxv_h.py\n') ++ version_file.write(' */\n') ++ ++# version_file.write('#define MVXV_HEAD_VER ' + str(list('2')).replace('[','{').replace(']','}') + '\n') ++# version_file.write('#define MVXV_LIB_TYPE ' + str(list(args.lib_type)).replace('[','{').replace(']','}') + '\n') ++# version_file.write('#define MVXV_CHIP_ID ' + str(list(args.chip_id)).replace('[','{').replace(']','}') + '\n') ++# version_file.write('#define MVXV_CHANGELIST ' + str(list(args.changelist)).replace('[','{').replace(']','}') + '\n') ++# version_file.write('#define MVXV_COMP_ID ' + str(list(args.comp_id)).replace('[','{').replace(']','}') + '\n') ++ version_file.write('#define MVXV_HEAD_VER "' + '4'+'"\n') ++ version_file.write('#define MVXV_LIB_TYPE "' + args.lib_type + '"\n') ++ version_file.write('#define MVXV_CHIP_ID "' + args.chip_id + '"\n') ++ version_file.write('#define MVXV_CHANGELIST "' + args.changelist + '"\n') ++ version_file.write('#define MVXV_COMP_ID "' + args.comp_id + '"\n') ++ if len(ext_str) > 0 : ++ #ext_str=str(list(ext_str)) ++ #ext_str=ext_str[1:(len(ext_str)-1)] ++ version_file.write('#define MVXV_EXT "' + ext_str + '"\n') ++ version_file.write("\n") ++ version_file.close() +diff --git a/scripts/mz b/scripts/mz +new file mode 100755 +index 000000000000..0baac48b0d47 +Binary files /dev/null and b/scripts/mz differ +diff --git a/scripts/setlocalversion b/scripts/setlocalversion +index 966dd3924ea9..02c87466de12 100755 +--- a/scripts/setlocalversion ++++ b/scripts/setlocalversion +@@ -160,15 +160,15 @@ res="${res}${CONFIG_LOCALVERSION}${LOCALVERSION}" + if test "$CONFIG_LOCALVERSION_AUTO" = "y"; then + # full scm version string + res="$res$(scm_version)" +-else ++#else + # append a plus sign if the repository is not in a clean + # annotated or signed tagged state (as git describe only + # looks at signed or annotated tags - git tag -a/-s) and + # LOCALVERSION= is not specified +- if test "${LOCALVERSION+set}" != "set"; then +- scm=$(scm_version --short) +- res="$res${scm:++}" +- fi ++ #if test "${LOCALVERSION+set}" != "set"; then ++ # scm=$(scm_version --short) ++ # res="$res${scm:++}" ++ #fi + fi + + echo "$res" +diff --git a/scripts/sstar/.cscope.mk b/scripts/sstar/.cscope.mk +new file mode 100644 +index 000000000000..31be885d1400 +--- /dev/null ++++ b/scripts/sstar/.cscope.mk +@@ -0,0 +1,38 @@ ++include Makefile ++ ++CSCOPE_FIND_FLAGS = -regex '\(Makefile\|makefile\|Kbuild\|Kconfig\|.*\.\(c\|h\|s\|S\|mk\|mak\)\)' ++ ++CSCOPE_ROOT = $(shell pwd) ++CSCOPE_ARCH_DIR = arch ++CSCOPE_COMMON_DIR = common ++ ++CSCOPE_ARCH_MACHINE_PREFIX = mach- ++CSCOPE_ARCH_PLATFORM_PREFIX = plat- ++ ++include $(CSCOPE_ROOT)/$(CSCOPE_ARCH_DIR)/$(ARCH)/Makefile ++ ++CSCOPE_TOP_SRC_PATH = init ipc virt samples drivers include block crypto mm security fs sound net scripts lib kernel firmware ++CSCOPE_SRC_PATH = $(foreach d, $(CSCOPE_TOP_SRC_PATH), $(CSCOPE_ROOT)/$(d)) ++CSCOPE_MACHDIRS = $(CSCOPE_ROOT)/$(shell echo $(machdirs) | cut -d' ' -f1 ) ++CSCOPE_ARCHDIRS = $(CSCOPE_ROOT)/$(CSCOPE_ARCH_DIR)/$(ARCH) ++ ++CSCOPE_NAMEFILE = .cscope.files ++ ++gen_db: ++ @echo ++ @echo Clean up ... ++ @rm -f $(CSCOPE_NAMEFILE) ++ @echo ++ @echo List files ... option:$(CSCOPE_FIND_FLAGS) ++ @echo +++ $(CSCOPE_ARCHDIRS) ++ @echo --- $(CSCOPE_ARCHDIRS)/$(CSCOPE_ARCH_MACHINE_PREFIX) ++ @echo --- $(CSCOPE_ARCHDIRS)/$(CSCOPE_ARCH_PLATFORM_PREFIX) ++ @find $(CSCOPE_ARCHDIRS) $(CSCOPE_FIND_FLAGS) -type f | grep -v $(CSCOPE_ARCHDIRS)/$(CSCOPE_ARCH_MACHINE_PREFIX) | grep -v $(CSCOPE_ARCHDIRS)/$(CSCOPE_ARCH_PLATFORM_PREFIX) > $(CSCOPE_NAMEFILE) ++ @echo +++ $(CSCOPE_MACHDIRS) ++ @find $(CSCOPE_MACHDIRS) $(CSCOPE_FIND_FLAGS) -type f >> $(CSCOPE_NAMEFILE) ++ @echo +++ $(CSCOPE_SRC_PATH) ++ @find $(CSCOPE_SRC_PATH) $(CSCOPE_FIND_FLAGS) -type f >> $(CSCOPE_NAMEFILE) ++ @echo ++ @echo Generate cscope db ... ++ @cscope -i $(CSCOPE_NAMEFILE) -bqkR ++ @echo +diff --git a/scripts/sstar/.cscope.sh b/scripts/sstar/.cscope.sh +new file mode 100755 +index 000000000000..69c8822a5b73 +--- /dev/null ++++ b/scripts/sstar/.cscope.sh +@@ -0,0 +1,2 @@ ++#!/bin/sh ++make -f scripts/sstar/.cscope.mk gen_db 2>&1 | grep -v warning +diff --git a/scripts/sstar/benchmark/README b/scripts/sstar/benchmark/README +new file mode 100644 +index 000000000000..f71d886ea165 +--- /dev/null ++++ b/scripts/sstar/benchmark/README +@@ -0,0 +1,69 @@ ++[Introduction] ++The following shell scripts utilize 'perf' with ARM/PL310 PMU for memcpy ++profiling. ++ - perf_memcpy_I2_l2x0.sh ++ script for I2 with both ARM Cortex-A9 PMU & PL310 PMU profiling. ++ - perf_memcpy_I3.sh ++ script for I2 with both ARM Cortex-A9 PMU & LLC PMU profiling. ++ ++[Prerequisites] ++for I2: ++ - Linux 3.18 Kernel with the follwoing CONFIGs: ++ CONFIG_HAVE_PERF_EVENTS=y ++ CONFIG_PERF_EVENTS=y ++ CONFIG_HW_PERF_EVENTS=y ++ CONFIG_CACHE_L2X0_PMU=y ++ - perf executable ++ - mstar ms_sys driver ++ - shell script (perf_memcpy_I2_l2x0.sh) ++ ++for I3: ++ - Linux 3.18 Kernel with the follwoing CONFIGs: ++ CONFIG_HAVE_PERF_EVENTS=y ++ CONFIG_PERF_EVENTS=y ++ CONFIG_HW_PERF_EVENTS=y ++ - perf executable ++ - mstar ms_sys driver ++ - shell script (perf_memcpy_I3.sh) ++ ++[Usage] ++ ++for I2: ++ ++Usage: ./perf_memcpy_I2_l2x0.sh BUFFER_SIZE L2_PMU_SELECT [memcpy scheme] ++[memory type] [cachable] ++ BUFFER_SIZE: number of KB for each iteration (total bytes transfer: 64KB * ++10000) ++ L2_PMU_SELECT: valid option r|w|e|x ++ r: drreq and drhit ++ w: dwreq and dwhit ++ e: cc and ipfalloc ++ x: dwtreq and wa ++ [memcpy scheme]: valid option 0|1|2 ++ 0: C runtime memcpy ++ 1: memcpy.S with NEON ++ 2: memcpy.S without NEON ++ [memory type]: valid option MIU|IMI ++ [cachable]: valid option 0|1 ++ ++EXAMPLE: ./perf_memcpy_I2_l2x0.sh 32 r 0 ++ [CRT] memcpy scheme test with [32]KB buffer for 20000 iterations and use ++perf PMU for profiling with addtional L2 PMU [drreq/drhit]. ++ ++for I3: ++ ++Usage: ./perf_memcpy_I3.sh BUFFER_SIZE L2_PMU_SELECT [memcpy scheme] [memory ++type] [cachable] ++ BUFFER_SIZE: number of KB for each iteration (total bytes transfer: 64KB * ++10000) ++ L2_PMU_SELECT: not valid for I3 ++ [memcpy scheme]: valid option 0|1|2 ++ 0: C runtime memcpy ++ 1: memcpy.S with NEON ++ 2: memcpy.S without NEON ++ [memory type]: valid option MIU|IMI ++ [cachable]: valid option 0|1 ++ ++EXAMPLE: ./perf_memcpy_I3.sh 32 r 0 ++ [CRT] memcpy scheme test with [32]KB buffer for 20000 iterations and use ++perf PMU for profiling with LLC PMU. +diff --git a/scripts/sstar/benchmark/perf_memcpy_I2_l2x0.sh b/scripts/sstar/benchmark/perf_memcpy_I2_l2x0.sh +new file mode 100755 +index 000000000000..bcdb1ed07c92 +--- /dev/null ++++ b/scripts/sstar/benchmark/perf_memcpy_I2_l2x0.sh +@@ -0,0 +1,75 @@ ++FILTER_BASIC="-e cpu-cycles -e instructions -e cache-references -e cache-misses -e branch-instructions -e branch-misses -e stalled-cycles-frontend -e stalled-cycles-backend -e L1-dcache-loads -e L1-dcache-load-misses -e L1-dcache-stores -e L1-dcache-store-misses -e L1-icache-load-misses -e context-switches -e cpu-migrations -e page-faults -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -e branch-loads -e branch-load-misses" ++ ++VERBOSE= ++LOOP_BASE=10000 ++MEM_TYPE="MIU" ++CACHABLE="1" ++ ++usage() ++{ ++ echo '' ++ echo "Usage: $0 BUFFER_SIZE L2_PMU_SELECT [memcpy scheme] [memory type] [cachable]" ++ echo ' BUFFER_SIZE: number of KB for each iteration (total bytes transfer: 64KB * 10000)' ++ echo ' L2_PMU_SELECT: valid option r|w|e|x' ++ echo ' r: drreq and drhit' ++ echo ' w: dwreq and dwhit' ++ echo ' e: cc and ipfalloc' ++ echo ' x: dwtreq and wa' ++ echo ' [memcpy scheme]: valid option 0|1|2' ++ echo ' 0: C runtime memcpy' ++ echo ' 1: memcpy.S with NEON' ++ echo ' 2: memcpy.S without NEON' ++ echo ' [memory type]: valid option MIU|IMI' ++ echo ' [cachable]: valid option 0|1' ++ echo '' ++ echo "EXAMPLE: $0 32 r 0" ++ echo ' [CRT] memcpy scheme test with [32]KB buffer for 20000 iterations and use perf PMU for profiling with addtional L2 PMU [drreq/drhit].' ++ echo '' ++} ++ ++if [ "$1" == "" ] ++then ++ usage ++ exit 1 ++fi ++ ++BUFFER_SIZE=$(($1*1024)) ++LOOP_COUNT=$((64*1024*$LOOP_BASE/$BUFFER_SIZE)) ++echo 'R/W:' $2 ', BUFFER_SIZE: ' $BUFFER_SIZE ', LOOP_COUNT: ' $LOOP_COUNT ', scheme: ' $3 ', mem type: ' $4 ', cachable: ' $5 ++ ++if [ "$2" = "r" ] ++then ++ FILTER_EX="-e l2c_310/drreq/ -e l2c_310/drhit/" ++elif [ "$2" = "w" ] ++then ++ FILTER_EX="-e l2c_310/dwreq/ -e l2c_310/dwhit/" ++elif [ "$2" = "e" ] ++then ++ FILTER_EX="-e l2c_310/co/ -e l2c_310/ipfalloc/" ++elif [ "$2" = "x" ] ++then ++ FILTER_EX="-e l2c_310/dwtreq/ -e l2c_310/wa/" ++else ++ echo 'ERROR: invalid parameter' ++ echo '' ++ usage ++ exit 1 ++fi ++ ++if [ "$4" = "IMI" ] || [ "$4" = "MIU" ] ++then ++ MEM_TYPE=$4 ++else ++ MEM_TYPE="MIU" ++fi ++ ++if [ "$5" = "0" ] || [ "$5" = "1" ] ++then ++ CACHABLE=$5 ++else ++ CACHABLE="1" ++fi ++ ++./perf stat $VERBOSE $FILTER_BASIC $FILTER_EX echo $MEM_TYPE $CACHABLE $MEM_TYPE $CACHABLE $LOOP_COUNT $BUFFER_SIZE $3 > /sys/devices/virtual/sstar/msys/perf_test ++#./perf stat $VERBOSE $FILTER_BASIC $FILTER_EX echo MIU 1 MIU 1 $LOOP_COUNT $BUFFER_SIZE $3 > /sys/devices/virtual/sstar/msys/perf_test ++# -e l2c_310/co/ -e l2c_310/drhit/ -e l2c_310/drreq/ -e l2c_310/dwhit/ -e l2c_310/dwreq/ -e l2c_310/dwtreq/ -e l2c_310/epfalloc/ -e l2c_310/epfhit/ -e l2c_310/epfrcvd -e l2c_310/ipfalloc/ -e l2c_310/irhit/ -e l2c_310/irreq/ -e l2c_310/srconf/ -e l2c_310/srrcvd/ -e l2c_310/wa/ +diff --git a/scripts/sstar/benchmark/perf_memcpy_I3.sh b/scripts/sstar/benchmark/perf_memcpy_I3.sh +new file mode 100755 +index 000000000000..26a48ae4cc88 +--- /dev/null ++++ b/scripts/sstar/benchmark/perf_memcpy_I3.sh +@@ -0,0 +1,54 @@ ++FILTER_BASIC="-e cpu-cycles -e instructions -e cache-references -e cache-misses -e branch-instructions -e branch-misses -e stalled-cycles-frontend -e stalled-cycles-backend -e L1-dcache-loads -e L1-dcache-load-misses -e L1-dcache-stores -e L1-dcache-store-misses -e L1-icache-load-misses -e context-switches -e cpu-migrations -e page-faults -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -e branch-loads -e branch-load-misses" ++ ++VERBOSE= ++LOOP_BASE=10000 ++MEM_TYPE="MIU" ++CACHABLE="1" ++ ++usage() ++{ ++ echo '' ++ echo "Usage: $0 BUFFER_SIZE L2_PMU_SELECT [memcpy scheme] [memory type] [cachable]" ++ echo ' BUFFER_SIZE: number of KB for each iteration (total bytes transfer: 64KB * 10000)' ++ echo ' L2_PMU_SELECT: not valid for I3' ++ echo ' [memcpy scheme]: valid option 0|1|2' ++ echo ' 0: C runtime memcpy' ++ echo ' 1: memcpy.S with NEON' ++ echo ' 2: memcpy.S without NEON' ++ echo ' [memory type]: valid option MIU|IMI' ++ echo ' [cachable]: valid option 0|1' ++ echo '' ++ echo "EXAMPLE: $0 32 r 0" ++ echo ' [CRT] memcpy scheme test with [32]KB buffer for 20000 iterations and use perf PMU for profiling with addtional L2 PMU [drreq/drhit].' ++ echo '' ++} ++ ++if [ "$1" == "" ] ++then ++ usage ++ exit 1 ++fi ++ ++BUFFER_SIZE=$(($1*1024)) ++LOOP_COUNT=$((64*1024*$LOOP_BASE/$BUFFER_SIZE)) ++echo 'R/W:' $2 ', BUFFER_SIZE: ' $BUFFER_SIZE ', LOOP_COUNT: ' $LOOP_COUNT ', neon: ' $3 ', mem type: ' $4 ', cachable: ' $5 ++ ++FILTER_EX="-e LLC-loads -e LLC-load-misses -e LLC-stores -e LLC-store-misses" ++FILTER_EX2="-e armv7_cortex_a7/l1d_cache/ -e armv7_cortex_a7/l1d_cache_refill/ -e armv7_cortex_a7/l1d_cache_wb/ -e armv7_cortex_a7/l2d_cache/ -e armv7_cortex_a7/l2d_cache_refill/ -e armv7_cortex_a7/l2d_cache_wb/ -e armv7_cortex_a7/ld_retired/ -e armv7_cortex_a7/st_retired/" ++FILTER_RAW="-e r013 -e r015 -e r019 -e r01d -e r060 -e r061 -e r0c0 -e r0c1 -e r0c2 -e r0c3 -e r0c4 -e r0c5" ++ ++if [ "$4" = "IMI" ] || [ "$4" = "MIU" ] ++then ++ MEM_TYPE=$4 ++else ++ MEM_TYPE="MIU" ++fi ++ ++if [ "$5" = "0" ] || [ "$5" = "1" ] ++then ++ CACHABLE=$5 ++else ++ CACHABLE="1" ++fi ++ ++./perf stat $VERBOSE $FILTER_BASIC $FILTER_EX $FILTER_EX2 $FILTER_RAW echo $MEM_TYPE $CACHABLE $MEM_TYPE $CACHABLE $LOOP_COUNT $BUFFER_SIZE $3 > /sys/devices/virtual/sstar/msys/perf_test +diff --git a/scripts/sstar/benchmark/perf_usleep_I3.sh b/scripts/sstar/benchmark/perf_usleep_I3.sh +new file mode 100755 +index 000000000000..c6d5d3848eec +--- /dev/null ++++ b/scripts/sstar/benchmark/perf_usleep_I3.sh +@@ -0,0 +1,8 @@ ++FILTER_BASIC="-e cpu-cycles -e instructions -e cache-references -e cache-misses -e branch-instructions -e branch-misses -e stalled-cycles-frontend -e stalled-cycles-backend -e L1-dcache-loads -e L1-dcache-load-misses -e L1-dcache-stores -e L1-dcache-store-misses -e L1-icache-load-misses -e context-switches -e cpu-migrations -e page-faults -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -e branch-loads -e branch-load-misses" ++FILTER_EX="-e LLC-loads -e LLC-load-misses -e LLC-stores -e LLC-store-misses" ++FILTER_EX2="-e armv7_cortex_a7/l1d_cache/ -e armv7_cortex_a7/l1d_cache_refill/ -e armv7_cortex_a7/l1d_cache_wb/ -e armv7_cortex_a7/l2d_cache/ -e armv7_cortex_a7/l2d_cache_refill/ -e armv7_cortex_a7/l2d_cache_wb/ -e armv7_cortex_a7/ld_retired/ -e armv7_cortex_a7/st_retired/" ++FILTER_RAW="-e r013 -e r015 -e r019 -e r01d -e r060 -e r061 -e r0c0 -e r0c1 -e r0c2 -e r0c3 -e r0c4 -e r0c5" ++ ++CMDLINE="usleep" ++ ++./perf stat $FILTER_BASIC $FILTER_EX $FILTER_EX2 $FILTER_RAW $CMDLINE $1 +diff --git a/scripts/sstar/benchmark/task_stat.sh b/scripts/sstar/benchmark/task_stat.sh +new file mode 100755 +index 000000000000..21fca1d353d7 +--- /dev/null ++++ b/scripts/sstar/benchmark/task_stat.sh +@@ -0,0 +1,30 @@ ++printf "#\n# Auto detect find...@ " ++if [ -e /usr/bin/find ] ++then ++ _FIND=/usr/bin/find ++else ++ _FIND=find ++fi ++printf "$_FIND\n" ++ ++printf "# Auto detect awk...@ " ++if [ -e /usr/bin/awk ] ++then ++ _AWK=/usr/bin/awk ++else ++ _AWK=awk ++fi ++printf "$_AWK\n#\n" ++ ++printf "#%5s %6s %20s %6s %6s %6s %6s %6s\n" "PPID" "PID" "Name" "nThrd" "Prio" "Nice" "PrioRT" "policy" ++#/usr/bin/find /proc -type f -mindepth 2 -maxdepth 2 -iname 'stat' -exec cat {} \; | /usr/bin/awk '{printf " PID %6d %20s priority %4d nice %3d\n",$1,$2,$18,$19}' ++#/usr/bin/find /proc -type f -mindepth 2 -maxdepth 2 -iname 'stat' -exec cat {} \;| /usr/bin/awk '{printf "%6d %6d %30s %6d %6d %6d %6d %6d\n",$4,$1,$2,$20,$18,$19,$40,$41}' ++$_FIND /proc -type f -mindepth 2 -maxdepth 2 -iname 'stat' -exec cat {} \; | $_AWK -F ' \(|\) ' '{ ++ for(i=1;i<=NF;i++) { ++ if(i==2) { ++ gsub(" ","/",$i) ++ } ++ printf "%s ",$i ++ } ++ printf "\n" ++}' | $_AWK '{printf "%6d %6d %20s %6d %6d %6d %6d %6d\n",$4,$1,$2,$20,$18,$19,$40,$41} +diff --git a/scripts/sstar/gdb/main.gdb b/scripts/sstar/gdb/main.gdb +new file mode 100644 +index 000000000000..5f8b64e5006b +--- /dev/null ++++ b/scripts/sstar/gdb/main.gdb +@@ -0,0 +1,7 @@ ++# connect to remote JLinkGDBServer ++target remote gdbserver:2331 ++# load symobl ++file vmlinux ++#symbol-file ++#add-symbol-file vmlinux 0x23f26000 ++#add-symbol-file vmlinux 0x23008000 +diff --git a/scripts/sstar/gdb/start_gdb.sh b/scripts/sstar/gdb/start_gdb.sh +new file mode 100755 +index 000000000000..0bd6e8f73c5a +--- /dev/null ++++ b/scripts/sstar/gdb/start_gdb.sh +@@ -0,0 +1,4 @@ ++#!/bin/sh ++ROOT_DIR=$(pwd) ++SCRIPT_PATH=scripts/sstar/gdb ++arm-linux-gnueabihf-gdb -command=$ROOT_DIR/$SCRIPT_PATH/main.gdb +diff --git a/scripts/sstar/release/Makefile b/scripts/sstar/release/Makefile +new file mode 100644 +index 000000000000..654b3298b561 +--- /dev/null ++++ b/scripts/sstar/release/Makefile +@@ -0,0 +1,53 @@ ++_WD := scripts/sstar/release ++_ROOT_DIR := $(subst $(_WD),,$(shell pwd)) ++KCONFIG_DIR := $(_ROOT_DIR)scripts/kconfig ++MCONF_BIN := $(KCONFIG_DIR)/mconf ++ARCH_DIR := $(_ROOT_DIR)/arch/arm/mach-sstar/ ++KCONFIG := $(_ROOT_DIR)$(_WD)/Kconfig ++DEFAULT_CONFIG := $(_ROOT_DIR)$(_WD)/.config ++RELEASE_SCRIPT := $(_ROOT_DIR)$(_WD)/rel.sh ++# enumerate chip names from $(ARCH_DIR) ++CHIP_LIST := $(sort $(shell find $(ARCH_DIR) -mindepth 1 -maxdepth 1 -type d -exec basename {} \; | xargs)) ++ ++# Kconfig select item template ++CHIP_NAME_TEMP := _CHIP_TEMPLATE_ ++ITEM_TEMPLATE := menuconfig $(CHIP_NAME_TEMP)\n\tbool \"SStar SoC platform $(CHIP_NAME_TEMP)\"\n\tdefault n\n ++# replace template string with chip names ++SELECT_ITEMS := $(foreach chip,$(CHIP_LIST),$(subst $(CHIP_NAME_TEMP),$(chip),$(ITEM_TEMPLATE))) ++ ++.PHONY: all debug autogen menuconfig release ++ ++all: autogen menuconfig release ++ @echo "------------------------------" ++ @echo " Cutomer release done!" ++ @echo "------------------------------" ++ ++debug: ++ @echo "------------------------------" ++ @echo " DEBUG" ++ @echo "------------------------------" ++ @echo $(_WD) ++ @echo $(_ROOT_DIR) ++ @echo $(MCONF_BIN) ++ @echo $(CHIP_LIST) ++ @printf "$(SELECT_ITEMS)" ++ ++autogen: ++ @echo "------------------------------" ++ @echo " Auto generate Kconfig..." ++ @echo "------------------------------" ++ @rm -f $(KCONFIG) ++ @rm -f $(DEFAULT_CONFIG) ++ @echo "mainmenu \"Customer Release Chips Configuration\"" > $(KCONFIG) ++ @printf "$(SELECT_ITEMS)" >> $(KCONFIG) ++ @cat $(KCONFIG) ++ ++menuconfig: ++ @$(MCONF_BIN) $(KCONFIG) ++ ++release: ++ @echo "------------------------------" ++ @echo " Execute customer release..." ++ @echo "------------------------------" ++ @$(RELEASE_SCRIPT) $(shell cat .config | grep -e '^# CONFIG_' | sed 's/^# CONFIG_\(.*\) is not set/\1/g') ++ +diff --git a/scripts/sstar/release/infinity2.blacklist b/scripts/sstar/release/infinity2.blacklist +new file mode 100644 +index 000000000000..b785a967788f +--- /dev/null ++++ b/scripts/sstar/release/infinity2.blacklist +@@ -0,0 +1,2 @@ ++drivers/sstar/ceva_link ++linux-4.9 /scripts/ms_gen_ceva_version_h.py +diff --git a/scripts/sstar/release/rel.sh b/scripts/sstar/release/rel.sh +new file mode 100755 +index 000000000000..9bff4b0f62bd +--- /dev/null ++++ b/scripts/sstar/release/rel.sh +@@ -0,0 +1,27 @@ ++#!/bin/sh ++ ++KERNEL_ROOT_DIR=../../.. ++KERNEL_CONFIG_DIR=../../../arch/arm/configs ++KERNEL_DTS_DIR=../../../arch/arm/boot/dts ++ ++for i in $@;do ++ echo ">>>>>> Handle $i:" ++ find $KERNEL_ROOT_DIR -type d -iname $i | xargs rm -rfv ++ find $KERNEL_CONFIG_DIR -type f -iname "$i""_*defconfig" | xargs rm -rfv ++ find $KERNEL_DTS_DIR -type f -regex ".*$i\(\.\|-\).*\(dts\|dtsi\|dtb\)" | xargs rm -rfv ++ echo "<<<<<<" ++ if [ -f "$i.blacklist" ]; then ++ echo ">>>>>> Handle $i.blacklist:" ++ while read -r line ++ do ++ echo " remove $KERNEL_ROOT_DIR/$line" ++ rm -rf "$KERNEL_ROOT_DIR/$line" ++ done < $i.blacklist ++ echo "<<<<<<" ++ fi ++done ++ ++# clear platform specify release blacklist file ++find -iname '*.blacklist' -exec rm {} \; ++ ++ +diff --git a/scripts/sstar/scm/README b/scripts/sstar/scm/README +new file mode 100644 +index 000000000000..a85c08a42af9 +--- /dev/null ++++ b/scripts/sstar/scm/README +@@ -0,0 +1,9 @@ ++Software Configuration Managment ++================================ ++ ++1. Coverity & Black duck ++ ++ Tool: cov_scan.sh ++ Purpose: List file modification commit exception intial commit. ++ Uage: ./cov_scan.sh coveriy_192.txt ++ +diff --git a/scripts/sstar/scm/cov_scan.sh b/scripts/sstar/scm/cov_scan.sh +new file mode 100755 +index 000000000000..cd7f01ac7a6e +--- /dev/null ++++ b/scripts/sstar/scm/cov_scan.sh +@@ -0,0 +1,33 @@ ++#!/bin/sh ++ ++num=1 ++clean_num=0 ++tanted_num=0 ++ ++# retreive initial commit id ++first_commit=$( git log --reverse --pretty=format:'%h' | tr '\n' ':' | cut -d':' -f1 ) ++ ++# make sure the new line is unix format ++dos2unix $1 ++ ++while read -r line ++do ++ git_log=$( git log --color --graph --pretty=format:'%h -%d %s (%cr) <%an>' --abbrev-commit -- $line | grep -v $first_commit ) ++ if [ "$git_log" == "" ] ++ then ++ echo $num:$line:'CLEAN' ++ clean_num=$(( clean_num+1 )) ++ else ++ echo $num:$line:'TANTED' ++ git log --color --graph --pretty=format:'%h -%d %s (%cr) <%an>' --abbrev-commit -- $line ++ echo '' ++ tanted_num=$(( tanted_num+1 )) ++ fi ++ #echo '' ++ num=$(( num+1 )) ++done < $1 ++ ++echo ====================================== ++echo CLEAN: $clean_num, TANTED: $tanted_num ++echo ====================================== ++ +diff --git a/scripts/sstar/scm/coverity_192.txt b/scripts/sstar/scm/coverity_192.txt +new file mode 100755 +index 000000000000..717f9252fc30 +--- /dev/null ++++ b/scripts/sstar/scm/coverity_192.txt +@@ -0,0 +1,192 @@ ++arch/arm/boot/compressed/atags_to_fdt.c ++arch/arm/kernel/atags_parse.c ++arch/arm/kernel/devtree.c ++arch/arm/kernel/vdso.c ++arch/arm/kernel/vdso.c ++block/bio.c ++block/blk-ioc.c ++block/blk-map.c ++block/blk-map.c ++block/elevator.c ++block/elevator.c ++crypto/ablkcipher.c ++crypto/ablkcipher.c ++crypto/arc4.c ++crypto/blkcipher.c ++crypto/cbc.c ++crypto/cbc.c ++crypto/crypto_null.c ++crypto/ctr.c ++crypto/ctr.c ++drivers/clk/clk.c ++drivers/cpufreq/cpufreq.c ++drivers/gpio/gpiolib.c ++drivers/mtd/nand/nand_ecc.c ++drivers/mtd/ubi/attach.c ++drivers/mtd/ubi/attach.c ++drivers/mtd/ubi/attach.c ++drivers/mtd/ubi/attach.c ++drivers/mtd/ubi/attach.c ++drivers/mtd/ubi/build.c ++drivers/of/fdt.c ++drivers/of/fdt.c ++drivers/scsi/scsi_lib.c ++drivers/scsi/sd.c ++drivers/tty/serial/serial_core.c ++drivers/tty/serial/serial_core.c ++drivers/tty/serial/serial_core.c ++drivers/tty/serial/serial_core.c ++drivers/tty/serial/serial_core.c ++drivers/tty/serial/serial_core.c ++drivers/tty/serial/serial_core.c ++drivers/usb/host/ehci-sched.c ++drivers/usb/host/ehci-sched.c ++drivers/usb/host/ehci-sched.c ++drivers/video/fbdev/core/fbmem.c ++fs/aio.c ++fs/binfmt_elf.c ++fs/buffer.c ++fs/buffer.c ++fs/buffer.c ++fs/buffer.c ++fs/cifs/cifsencrypt.c ++fs/cifs/cifsfs.c ++fs/cifs/cifsfs.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/cifssmb.c ++fs/cifs/misc.c ++fs/configfs/mount.c ++fs/dcache.c ++fs/dcache.c ++fs/eventpoll.c ++fs/eventpoll.c ++fs/fcntl.c ++fs/file_table.c ++fs/jffs2/fs.c ++fs/jffs2/gc.c ++fs/jffs2/malloc.c ++fs/jffs2/scan.c ++fs/kernfs/mount.c ++fs/locks.c ++fs/mpage.c ++fs/namespace.c ++fs/namespace.c ++fs/nfs/direct.c ++fs/nfs/direct.c ++fs/nfs/direct.c ++fs/nfs/pagelist.c ++fs/nfs/pagelist.c ++fs/nfs/pagelist.c ++fs/nfs/read.c ++fs/nfs/write.c ++fs/notify/dnotify/dnotify.c ++fs/notify/inotify/inotify_user.c ++fs/ntfs/aops.c ++fs/ntfs/compress.c ++fs/ntfs/namei.c ++fs/ntfs/runlist.c ++fs/ntfs/super.c ++fs/proc/base.c ++fs/proc/base.c ++fs/proc/base.c ++fs/proc/self.c ++fs/proc/task_mmu.c ++fs/proc/thread_self.c ++fs/signalfd.c ++fs/splice.c ++fs/squashfs/decompressor.c ++fs/ubifs/lpt.c ++fs/ubifs/tnc.c ++fs/ubifs/tnc.c ++fs/ubifs/tnc.c ++include/crypto/sha256_base.h ++include/linux/writeback.h ++ipc/msg.c ++kernel/cred.c ++kernel/events/core.c ++kernel/fork.c ++kernel/futex.c ++kernel/ksysfs.c ++kernel/nsproxy.c ++kernel/pid.c ++kernel/pid_namespace.c ++kernel/pid_namespace.c ++kernel/printk/printk.c ++kernel/ptrace.c ++kernel/ptrace.c ++kernel/resource.c ++kernel/resource.c ++kernel/resource.c ++kernel/signal.c ++kernel/sysctl.c ++kernel/time/alarmtimer.c ++kernel/time/alarmtimer.c ++kernel/time/posix-timers.c ++kernel/user.c ++kernel/workqueue.c ++lib/argv_split.c ++lib/idr.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/iov_iter.c ++lib/sg_pool.c ++lib/zlib_deflate/deflate.c ++mm/early_ioremap.c ++mm/early_ioremap.c ++mm/rmap.c ++mm/shmem.c ++mm/slub.c ++mm/slub.c ++mm/vmscan.c ++mm/vmscan.c ++mm/vmscan.c ++mm/vmscan.c ++mm/vmscan.c ++net/core/dst.c ++net/core/dst.c ++net/core/ethtool.c ++net/core/flow_dissector.c ++net/core/flow_dissector.c ++net/core/neighbour.c ++net/core/skbuff.c ++net/core/sock.c ++net/ipv4/fib_trie.c ++net/ipv4/fib_trie.c ++net/ipv4/fib_trie.c ++net/ipv4/fib_trie.c ++net/ipv4/fib_trie.c ++net/ipv4/fib_trie.c ++net/ipv4/inetpeer.c ++net/ipv4/route.c ++net/ipv4/route.c ++net/ipv4/tcp.c ++net/ipv4/tcp_metrics.c ++net/ipv4/tcp_metrics.c ++net/ipv4/tcp_metrics.c ++net/ipv4/tcp_metrics.c ++net/ipv4/tcp_metrics.c ++net/ipv4/tcp_minisocks.c ++net/ipv4/tcp_minisocks.c ++net/packet/af_packet.c ++net/sunrpc/sched.c ++net/wireless/util.c ++net/wireless/util.c ++net/wireless/util.c ++net/wireless/util.c +diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c +index dedf8eb4570e..1166ec87bd2d 100644 +--- a/sound/usb/mixer.c ++++ b/sound/usb/mixer.c +@@ -1874,7 +1874,7 @@ static int build_audio_procunit(struct mixer_build *state, int unitid, + char *name) + { + struct uac_processing_unit_descriptor *desc = raw_desc; +- int num_ins = desc->bNrInPins; ++ int num_ins; + struct usb_mixer_elem_info *cval; + struct snd_kcontrol *kctl; + int i, err, nameid, type, len; +@@ -1889,7 +1889,13 @@ static int build_audio_procunit(struct mixer_build *state, int unitid, + 0, NULL, default_value_info + }; + +- if (desc->bLength < 13 || desc->bLength < 13 + num_ins || ++ if (desc->bLength < 13) { ++ usb_audio_err(state->chip, "invalid %s descriptor (id %d)\n", name, unitid); ++ return -EINVAL; ++ } ++ ++ num_ins = desc->bNrInPins; ++ if (desc->bLength < 13 + num_ins || + desc->bLength < num_ins + uac_processing_unit_bControlSize(desc, state->mixer->protocol)) { + usb_audio_err(state->chip, "invalid %s descriptor (id %d)\n", name, unitid); + return -EINVAL; +diff --git a/tools/perf/build_ca7.sh b/tools/perf/build_ca7.sh +new file mode 100755 +index 000000000000..70e3ce13ac14 +--- /dev/null ++++ b/tools/perf/build_ca7.sh +@@ -0,0 +1,3 @@ ++#!/bin/sh ++make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- CC=arm-linux-gnueabihf-gcc CXX=arm-linux-gnueabihf-g++ WERROR=0 JOBS=8 ++arm-linux-gnueabihf-strip --strip-unneeded perf +diff --git a/virt/kvm/coalesced_mmio.c b/virt/kvm/coalesced_mmio.c +index 571c1ce37d15..5c1efb869df2 100644 +--- a/virt/kvm/coalesced_mmio.c ++++ b/virt/kvm/coalesced_mmio.c +@@ -39,7 +39,7 @@ static int coalesced_mmio_in_range(struct kvm_coalesced_mmio_dev *dev, + return 1; + } + +-static int coalesced_mmio_has_room(struct kvm_coalesced_mmio_dev *dev) ++static int coalesced_mmio_has_room(struct kvm_coalesced_mmio_dev *dev, u32 last) + { + struct kvm_coalesced_mmio_ring *ring; + unsigned avail; +@@ -51,7 +51,7 @@ static int coalesced_mmio_has_room(struct kvm_coalesced_mmio_dev *dev) + * there is always one unused entry in the buffer + */ + ring = dev->kvm->coalesced_mmio_ring; +- avail = (ring->first - ring->last - 1) % KVM_COALESCED_MMIO_MAX; ++ avail = (ring->first - last - 1) % KVM_COALESCED_MMIO_MAX; + if (avail == 0) { + /* full */ + return 0; +@@ -66,24 +66,27 @@ static int coalesced_mmio_write(struct kvm_vcpu *vcpu, + { + struct kvm_coalesced_mmio_dev *dev = to_mmio(this); + struct kvm_coalesced_mmio_ring *ring = dev->kvm->coalesced_mmio_ring; ++ __u32 insert; + + if (!coalesced_mmio_in_range(dev, addr, len)) + return -EOPNOTSUPP; + + spin_lock(&dev->kvm->ring_lock); + +- if (!coalesced_mmio_has_room(dev)) { ++ insert = READ_ONCE(ring->last); ++ if (!coalesced_mmio_has_room(dev, insert) || ++ insert >= KVM_COALESCED_MMIO_MAX) { + spin_unlock(&dev->kvm->ring_lock); + return -EOPNOTSUPP; + } + + /* copy data in first free entry of the ring */ + +- ring->coalesced_mmio[ring->last].phys_addr = addr; +- ring->coalesced_mmio[ring->last].len = len; +- memcpy(ring->coalesced_mmio[ring->last].data, val, len); ++ ring->coalesced_mmio[insert].phys_addr = addr; ++ ring->coalesced_mmio[insert].len = len; ++ memcpy(ring->coalesced_mmio[insert].data, val, len); + smp_wmb(); +- ring->last = (ring->last + 1) % KVM_COALESCED_MMIO_MAX; ++ ring->last = (insert + 1) % KVM_COALESCED_MMIO_MAX; + spin_unlock(&dev->kvm->ring_lock); + return 0; + } diff --git a/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/ssc338q.sdcard.config.camhi b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/ssc338q.sdcard.config.camhi new file mode 100755 index 0000000..624ba64 --- /dev/null +++ b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/board/infinity6e/kernel/ssc338q.sdcard.config.camhi @@ -0,0 +1,2544 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.84 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="ipcam" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_FHANDLE is not set +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="initramfs/initramfs_list" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_BASE_FULL is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR_NONE is not set +CONFIG_CC_STACKPROTECTOR_REGULAR=y +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=1 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INFINITY2 is not set +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MESON is not set +CONFIG_ARCH_SSTAR=y +# CONFIG_SS_DUALOS is not set +CONFIG_MODULES_AREA_SIZE=0x00800000 + +# +# Options +# +CONFIG_SS_DTB_NAME="infinity6e-ssc338q-camhi" +CONFIG_SS_BUILTIN_DTB=y +CONFIG_MS_KERNEL_TYPE="" +CONFIG_SSTAR_CHIP_NAME="infinity6e" +CONFIG_SSTAR_SHORT_NAME="" +CONFIG_MP_IRQ_TRACE=y +CONFIG_SS_GIC_SET_MULTI_CPUS=y +CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y + +# +# Fast boot +# +# CONFIG_SS_BUILTIN_UNFDT is not set +# CONFIG_FB_DTS_SKIP_CRC is not set +# CONFIG_FB_DTS_SCAN_MEMORY_ONCE is not set +# CONFIG_FB_DTS_SKIP_ATAGS_TO_FDT is not set +CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y +CONFIG_DEFERRED_INIICALLS=y +# CONFIG_DEFERRED_INIICALLS_SLAB_SYSFS is not set +# CONFIG_DEFERRED_INIICALLS_PARAM_SYSFS is not set +# CONFIG_DEFERRED_INIICALLS_PPERF_SYSFS is not set +# CONFIG_DEFERRED_INIICALLS_MORE_SYSFS is not set +# CONFIG_DEFERRED_CREATE_DTS_SYSNODE is not set +# CONFIG_CRYPTO_MANAGER_NO_TESTS_THREAD is not set +CONFIG_ARCH_INFINITY6E=y +CONFIG_SS_PROFILING_TIME=y +CONFIG_SS_MIU_ARBITRATION=y +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MEDIATEK is not set + +# +# TI OMAP/AM/DM/DRA Family +# +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TANGO is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_VDSO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_ARM_ERRATA_643719=y +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_818325_852422 is not set +# CONFIG_ARM_ERRATA_821420 is not set +# CONFIG_ARM_ERRATA_825619 is not set +# CONFIG_ARM_ERRATA_852421 is not set +# CONFIG_ARM_ERRATA_852423 is not set + +# +# Bus support +# +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_MCPM is not set +# CONFIG_BIG_LITTLE is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_THUMB2_KERNEL=y +CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y +CONFIG_ARM_ASM_UNIFIED=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_AEABI=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_CMA=y +CONFIG_CMA_DEBUG=y +CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_AREAS=1 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=10 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_CMDLINE="" +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +# CONFIG_CPUFREQ_DT is not set +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +# CONFIG_QORIQ_CPUFREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_APM_EMULATION=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_XFRM_USER is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +# CONFIG_IP_MULTIPLE_TABLES is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IP_TUNNEL is not set +# CONFIG_IP_MROUTE is not set +CONFIG_SYN_COOKIES=y +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_NV is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_CDG is not set +# CONFIG_TCP_CONG_BBR is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_SOCK_CGROUP_DATA is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +# CONFIG_DST_CACHE is not set +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +# CONFIG_DMA_SHARED_BUFFER is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=2 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=4 + +# +# Bus devices +# +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCI5xx_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_OF_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PLATRAM=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI_DT is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_BRCMNAND is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_HISI504 is not set +# CONFIG_MTD_NAND_MTK is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +# CONFIG_MTD_SPI_NOR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=4 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +# CONFIG_NET_CORE is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_ETHERNET is not set +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set + +# +# ACP (Audio CoProcessor) Configuration +# + +# +# Frame buffer Devices +# +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_SOUND is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_MP_USB_MSTAR=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_SUSPEND_PORT is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +CONFIG_SS_FAST_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_PRUSS is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +CONFIG_COMMON_CLK_PWM=y +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_PHY_SSTAR_INFINITY6E=y +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_ARM_PMU=y +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +CONFIG_NVMEM=m +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set +CONFIG_MSTAR_DRIVERS=y +# CONFIG_CAM_DRIVERS is not set +# CONFIG_DLA_DRIVER is not set +# CONFIG_MS_PIU_TIMER is not set +CONFIG_MS_MSYS=y +CONFIG_MS_ZEN=y +# CONFIG_MS_MSYS_LOG is not set +# CONFIG_MSYS_PERF_TEST is not set +# CONFIG_MSYS_BENCH_MEMORY_FUNC is not set +# CONFIG_MSYS_MIU_PROTECT is not set +# CONFIG_MSYS_DMEM_SYSFS_ALL is not set +CONFIG_MS_SERIAL=y +# CONFIG_MS_USCLK is not set +# CONFIG_MS_FLASH_ISP is not set +CONFIG_MS_PWM=y +# CONFIG_PWM_NEW is not set +CONFIG_MS_SPINAND=y +# CONFIG_NAND_SINGLE_READ is not set +# CONFIG_NAND_DUAL_READ is not set +# CONFIG_NAND_QUAL_READ is not set +CONFIG_AUTO_DETECT=y +# CONFIG_NAND_QUAL_WRITE is not set +CONFIG_AUTO_DETECT_WRITE=y +# CONFIG_MS_SPI_INFINITY is not set +# CONFIG_SS_MSPI is not set +# CONFIG_CAM_CLK is not set +# CONFIG_MS_EMMC is not set +CONFIG_MS_SDMMC=y +CONFIG_MS_EMAC=y +# CONFIG_EMAC_SUPPLY_RNG is not set +# CONFIG_MSTAR_HW_TX_CHECKSUM is not set +# CONFIG_K3_RX_SWPATCH is not set +CONFIG_DISCONNECT_DELAY_S=1 +# CONFIG_MSTAR_EEE is not set +# CONFIG_EMAC_PHY_RESTART_AN is not set +# CONFIG_EMAC_DPHY_REINIT is not set +# CONFIG_MS_IRCUT is not set +CONFIG_MS_RTC=y +# CONFIG_RTC_INNER is not set +CONFIG_RTCPWC_INNER=y +CONFIG_RTCPWC_SW_RST_OFF=y +CONFIG_RTCPWC_INNER_EHHE=y +CONFIG_MS_CRYPTO=y +# CONFIG_SS_AESDMA_INTR is not set +# CONFIG_SS_RNG is not set +CONFIG_CRYPTODEV=m +CONFIG_MS_CPU_FREQ=y +CONFIG_MS_IVE=y +CONFIG_MS_NOTIFY=y +CONFIG_SS_ISP_ISRCB=y +CONFIG_MSTAR_MIU=y +CONFIG_SSC007A_S01A=y +CONFIG_MS_BDMA=y +CONFIG_MS_BDMA_LINE_OFFSET_ON=y +CONFIG_MS_MOVE_DMA=y +# CONFIG_MS_IR is not set +CONFIG_MS_I2C=y +CONFIG_MS_I2C_INT_ISR=y +CONFIG_MS_GPIO=y +# CONFIG_MS_SW_I2C is not set +CONFIG_MS_PADMUX=y +CONFIG_MS_WATCHDOG=y +# CONFIG_MS_SAR is not set +# CONFIG_MS_SARKEY is not set +CONFIG_MSTAR_MMAHEAP=y +CONFIG_SSTAR_NETPHY=y +CONFIG_SS_VOLTAGE_CTRL=y +CONFIG_SS_VOLTAGE_CTRL_WITH_OSC=y +CONFIG_MS_IOPOWER=y +# CONFIG_SS_SWTOE is not set +# CONFIG_MS_EMAC_TOE is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_HAVE_ARM_SMCCC=y + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_OVERLAY_FS=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_ZLIB is not set +# CONFIG_UBIFS_ATIME_SUPPORT is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_LZ4 is not set +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=4096 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +# CONFIG_KASAN is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHED_INFO is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_PTDUMP is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_HW is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/projects/ssc338q_sdcard/br-ext-chip-sigmastar/configs/ssc338q_sdcard_defconfig b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/configs/ssc338q_sdcard_defconfig new file mode 100644 index 0000000..3858bee --- /dev/null +++ b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/configs/ssc338q_sdcard_defconfig @@ -0,0 +1,104 @@ +# Architecture +BR2_arm=y +BR2_cortex_a7=y +BR2_ARM_EABIHF=y +BR2_ARM_FPU_NEON_VFPV4=y +BR2_ARM_INSTRUCTIONS_THUMB2=y +BR2_KERNEL_HEADERS_VERSION=y +BR2_DEFAULT_KERNEL_VERSION="4.9.84" +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9=y + +# Toolchain +BR2_PER_PACKAGE_DIRECTORIES=y +BR2_GCC_VERSION_9_X=y +BR2_TOOLCHAIN_USES_GLIBC=y +BR2_TOOLCHAIN_BUILDROOT_GLIBC=y +BR2_TOOLCHAIN_BUILDROOT_LIBC="glibc" +BR2_TOOLCHAIN_BUILDROOT_CXX=y +BR2_TOOLCHAIN_BUILDROOT_LOCALE=y +BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y + +# Kernel +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.84" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_SIGMASTAR_PATH)/board/infinity6e/kernel/ssc338q.sdcard.config.camhi" +BR2_LINUX_KERNEL_UIMAGE=y +BR2_LINUX_KERNEL_XZ=y +BR2_LINUX_KERNEL_EXT_SIGMASTAR_PATCHER=y +BR2_LINUX_KERNEL_EXT_SIGMASTAR_PATCHER_LIST="$(BR2_EXTERNAL_SIGMASTAR_PATH)/board/infinity6e/kernel/patches/ $(BR2_EXTERNAL_SIGMASTAR_PATH)/board/infinity6e/kernel/overlay" +BR2_LINUX_KERNEL_EXT_SIGMASTAR_INITRAMFS=y + +# Filesystem +# BR2_TARGET_TZ_INFO is not set +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_SQUASHFS=y +BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y +BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" + +# OpenIPC configuration +BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" +BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC" +BR2_TARGET_GENERIC_HOSTNAME="openipc-ssc338q" +BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" + +# OpenIPC packages +BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" +BR2_PACKAGE_DROPBEAR_OPENIPC=y +# BR2_PACKAGE_FDK_AAC_OPENIPC is not set +BR2_PACKAGE_FWPRINTENV_OPENIPC=y +BR2_PACKAGE_HASERL=y +BR2_PACKAGE_IPCTOOL=y +BR2_PACKAGE_JSON_C=y +BR2_PACKAGE_JSONFILTER=y +BR2_PACKAGE_LIBCURL_OPENIPC=y +BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y +# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set +BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y +BR2_PACKAGE_LIBEVENT_OPENIPC=y +BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y +BR2_PACKAGE_LIBOGG_OPENIPC=y +BR2_PACKAGE_LIBYAML=y +# BR2_PACKAGE_MAJESTIC_FONTS is not set +# BR2_PACKAGE_MAJESTIC is not set +BR2_PACKAGE_MBEDTLS_OPENIPC=y +# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set +# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set +BR2_PACKAGE_MICROBE_WEB=y +# BR2_PACKAGE_MINI_SNMPD is not set +# BR2_PACKAGE_MOTORS is not set +BR2_PACKAGE_OPUS_OPENIPC=y +BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y +BR2_PACKAGE_SIGMASTAR_OSDRV_INFINITY6E=y +BR2_PACKAGE_SIGMASTAR_OSDRV_SENSOR="imx415" +BR2_PACKAGE_SIGMASTAR_SENSOR_OPENIPC=y +BR2_PACKAGE_DOSFSTOOLS=y +BR2_PACKAGE_DOSFSTOOLS_FSCK_FAT=y +# BR2_PACKAGE_SSHPASS is not set +BR2_PACKAGE_UACME_OPENIPC=y +BR2_PACKAGE_VTUND_OPENIPC=y +BR2_PACKAGE_YAML_CLI=y +BR2_PACKAGE_ZLIB=y + +# Wireless +BR2_PACKAGE_WIRELESS_TOOLS=y +BR2_PACKAGE_WPA_SUPPLICANT=y +BR2_PACKAGE_WPA_SUPPLICANT_CLI=y +BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y +BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y +BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y +BR2_PACKAGE_RTL8733BU_OPENIPC=y +BR2_PACKAGE_WIRELESS_CONFIGURATION=y + +# Wireguard +# BR2_PACKAGE_WIREGUARD_LINUX_COMPAT is not set +# BR2_PACKAGE_WIREGUARD_TOOLS is not set + +# Debug +BR2_PACKAGE_HOST_GDB=y +BR2_PACKAGE_GDB=y diff --git a/projects/ssc338q_sdcard/br-ext-chip-sigmastar/package/sigmastar-osdrv-infinity6e b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/package/sigmastar-osdrv-infinity6e new file mode 120000 index 0000000..8849835 --- /dev/null +++ b/projects/ssc338q_sdcard/br-ext-chip-sigmastar/package/sigmastar-osdrv-infinity6e @@ -0,0 +1 @@ +../../general/package/sigmastar-osdrv-infinity6e \ No newline at end of file diff --git a/projects/ssc338q_sdcard/general/overlay/init b/projects/ssc338q_sdcard/general/overlay/init new file mode 100755 index 0000000..3555cd5 --- /dev/null +++ b/projects/ssc338q_sdcard/general/overlay/init @@ -0,0 +1,62 @@ +#!/bin/sh + +on_exit() { + mountpoint -q /proc && umount /proc + exec /sbin/init $* +} + +trap on_exit 0 + +mount -t proc proc /proc || exit +grep -q overlay /proc/filesystems || exit + +if ! grep -q 'root=.*nfs\|mmcblk\|ram' /proc/cmdline; then + if grep -q ubifs /proc/cmdline; then + mount -t ubifs ubi0:rootfs_data /overlay + elif grep -q loop /proc/devices; then + mount -t devtmpfs devtmpfs /dev + mount -t tmpfs tmpfs /overlay + sleep 1 + mkdir -p /overlay/sdcard + mount -r /dev/mmcblk0p1 /overlay/sdcard + tar -xf /overlay/sdcard/settings.tar -C /overlay && echo OpenIPC: Extract settings from sdcard + umount /overlay/sdcard + rmdir /overlay/sdcard + else + mtdblkdev=$(awk -F ':' '/rootfs_data/ {print $1}' /proc/mtd | sed 's/mtd/mtdblock/') + mtdchrdev=$(grep 'rootfs_data' /proc/mtd | cut -d: -f1) + mount -t jffs2 /dev/${mtdblkdev} /overlay + + if [ $? -ne 0 ] || { dmesg | grep "jffs2.*: Magic bitmask.*not found" >/dev/null 2>&1; }; then + echo "jffs2 health check error, format required!" + flash_eraseall -j /dev/${mtdchrdev} + echo "Done! Remounting..." + mount -t jffs2 /dev/${mtdblkdev} /overlay || mount -t tmpfs tmpfs /overlay || exit + if ! cat /proc/mounts | grep ${mtdblkdev}; then + echo "--------------------------------" + echo "Crash - your flash in the trash!" + echo "--------------------------------" + fi + fi + fi + + if grep -q overlayfs /proc/filesystems; then + mount -t overlayfs overlayfs -o lowerdir=/,upperdir=/overlay,ro /mnt || { + umount /overlay + exit + } + else + overlay_rootdir=/overlay/root + overlay_workdir=/overlay/work + mkdir -p ${overlay_rootdir} ${overlay_workdir} + mount -t overlay overlay -o lowerdir=/,upperdir=${overlay_rootdir},workdir=${overlay_workdir} /mnt || { + umount /overlay + exit + } + fi + + pivot_root /mnt /mnt/rom + mount -o noatime,move /rom/proc /proc + mount -o noatime,move /rom/dev /dev + mount -o noatime,move /rom/overlay /overlay +fi diff --git a/projects/ssc338q_sdcard/general/overlay/usr/sbin/savesettings b/projects/ssc338q_sdcard/general/overlay/usr/sbin/savesettings new file mode 100755 index 0000000..7a0aa25 --- /dev/null +++ b/projects/ssc338q_sdcard/general/overlay/usr/sbin/savesettings @@ -0,0 +1,5 @@ +#!/bin/sh +if grep -q loop /proc/devices; then + tar -cf /tmp/settings.tar -C /overlay root + mv -f /tmp/settings.tar /mnt/mmcblk0p1 && echo OpenIPC: Save settings to sdcard +fi diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/Config.in b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/Config.in new file mode 100644 index 0000000..ef04331 --- /dev/null +++ b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/Config.in @@ -0,0 +1,9 @@ +config BR2_PACKAGE_SIGMASTAR_OSDRV_INFINITY6E + bool "sigmastar-osdrv-infinity6e" + help + sigmastar-osdrv-infinity6e - SigmaStar kernel modules and libs + +config BR2_PACKAGE_SIGMASTAR_OSDRV_SENSOR + depends on BR2_PACKAGE_SIGMASTAR_OSDRV_INFINITY6E + string "Camera sensor" + default "imx415" diff --git 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b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/bin/ircut_demo @@ -0,0 +1,84 @@ +#!/bin/sh + +# DAY mode +ir_cut_enable() { + # Pin_mux + [ ! -d /sys/class/gpio/gpio$gpio_0 ] && echo "$gpio_0" >/sys/class/gpio/export + [ ! -d /sys/class/gpio/gpio$gpio_1 ] && echo "$gpio_1" >/sys/class/gpio/export + + # Dir + echo "out" >/sys/class/gpio/gpio$gpio_0/direction + echo "out" >/sys/class/gpio/gpio$gpio_1/direction + + # Data, gpio_1: 0, gpio_0: 1 (day mode) + echo "1" >/sys/class/gpio/gpio$gpio_0/value + echo "0" >/sys/class/gpio/gpio$gpio_1/value + + # Sleep 1s + sleep 1 + + # Back to original + echo "0" >/sys/class/gpio/gpio$gpio_0/value + echo "0" >/sys/class/gpio/gpio$gpio_1/value +} + +# NIGHT mode +ir_cut_disable() { + # Pin_mux + [ ! -d /sys/class/gpio/gpio$gpio_0 ] && echo "$gpio_0" >/sys/class/gpio/export + [ ! -d /sys/class/gpio/gpio$gpio_1 ] && echo "$gpio_1" >/sys/class/gpio/export + + # Dir + echo "out" >/sys/class/gpio/gpio$gpio_0/direction + echo "out" >/sys/class/gpio/gpio$gpio_1/direction + + # Data, gpio_1: 1, gpio_0: 0 (night mode) + echo "0" >/sys/class/gpio/gpio$gpio_0/value + echo "1" >/sys/class/gpio/gpio$gpio_1/value + + # Sleep 1s + sleep 1 + + # Back to original + echo "0" >/sys/class/gpio/gpio$gpio_0/value + echo "0" >/sys/class/gpio/gpio$gpio_1/value +} + +gpio_0=0 +gpio_1=0 + +if [ $# -lt 2 ]; then + echo "Usage: ircut_demo " + echo "For example:" + echo "NIGHT: ircut_demo anjoy 1" +else + if [ $1 = "anjoy" ]; then + gpio_0=78 + gpio_1=79 + elif [ $1 = "brovotech" ]; then + gpio_0=78 + gpio_1=79 + elif [ $1 = "camhi" ]; then + gpio_0=23 + gpio_1=24 + elif [ $1 = "gospell" ]; then + gpio_0=78 + gpio_1=79 + elif [ $1 = "uniview" ]; then + gpio_0=78 + gpio_1=79 + else + echo -e "Wrong vendor name: $1\nPlease select: anjoy, brovotech, camhi, gospell, uniview" + exit + fi + + if [ $2 -eq 0 ]; then + echo "DAY mode, ir_cut on" + ir_cut_enable >/dev/null + elif [ $2 -eq 1 ]; then + echo "NIGHT mode, ir_cut off" + ir_cut_disable >/dev/null + else + echo "Invalid mode, please slect 0 or 1" + fi +fi diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/bin/load_sigmastar b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/bin/load_sigmastar new file mode 100755 index 0000000..4754e5a --- /dev/null +++ b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/bin/load_sigmastar @@ -0,0 +1,101 @@ +#!/bin/sh +# +# OpenIPC.org | 2023.03.01 +# +# Usage: load_sigmastar [-r|-i|-a] +# -r : remove all modules +# -i : insert all modules +# default : remove and insert all modules + +PATH_MODULE=/lib/modules/4.9.84/sigmastar +PATH_FIRMWARE=/etc/sensors/venc_fw/chagall.bin + +# Sensor +sensor= + +# Watchdog +watchdog -t 10 /dev/watchdog + +insert_ko() { + insmod ${PATH_MODULE}/mhal.ko + insmod ${PATH_MODULE}/mi_common.ko + insmod ${PATH_MODULE}/mi_sys.ko cmdQBufSize=768 logBufSize=256 + insmod ${PATH_MODULE}/mi_rgn.ko + insmod ${PATH_MODULE}/mi_ldc.ko + insmod ${PATH_MODULE}/mi_ai.ko + insmod ${PATH_MODULE}/mi_ao.ko + insmod ${PATH_MODULE}/mi_mipitx.ko + insmod ${PATH_MODULE}/mi_sensor.ko + insmod ${PATH_MODULE}/mi_shadow.ko + insmod ${PATH_MODULE}/mi_divp.ko thread_priority=98 + insmod ${PATH_MODULE}/mi_vif.ko thread_priority=98 + insmod ${PATH_MODULE}/mi_vpe.ko thread_priority=98 + + case $sensor in + imx415) + insmod ${PATH_MODULE}/mi_venc.ko fw_path=${PATH_FIRMWARE}; + ;; + *) + echo -e "\n\e[1;31mAn UNSUPPORTED sensor type is specified - ${sensor}\e[0m\n" | logger -s -t OpenIPC; + ;; + esac + + if [ ! -e /dev/mi_poll ]; then + major=$(awk '$2=="mi_poll" {print $1}' /proc/devices | head -n 1) + mknod /dev/mi_poll c $major 0 + fi + + # Change iqfile folder + echo isproot /etc/sensors/iqfile > /dev/ispmid + + case $sensor in + imx415) + insmod ${PATH_MODULE}/sensor_${sensor}_mipi.ko chmap=1; + ;; + *) + echo -e "\n\e[1;31mAn UNSUPPORTED sensor type is specified - ${sensor}\e[0m\n" | logger -s -t OpenIPC; + ;; + esac + + mdev -s +} + +remove_ko() { + rmmod -w drv_ms_cus_${sensor}_MIPI + rmmod -w mi_venc + rmmod -w mi_shadow + rmmod -w mi_sensor + rmmod -w mi_mipitx + rmmod -w mi_ao + rmmod -w mi_ai + rmmod -w mi_vpe + rmmod -w mi_vif + rmmod -w mi_divp + rmmod -w mi_ldc + rmmod -w mi_rgn + rmmod -w mi_sys + rmmod -w mi_common + rmmod -w mhal +} + +if [ -z ${sensor} ]; then + echo -e "\n\e[1;31mThe sensor parameter is MISSING\e[0m\n" | logger -s -t OpenIPC + exit 1 +else + echo -e "\n\e[1;32mThe sensor is assigned - ${sensor}\e[0m\n" | logger -s -t OpenIPC +fi + +if [ "$1" = "-i" ]; then + insert_ko +fi + +if [ "$1" = "-r" ]; then + remove_ko +fi + +if [ $# -eq 0 ] || [ "$1" = "-a" ]; then + remove_ko + insert_ko +fi + +exit 0 diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/init.d/S80sigmastar b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/init.d/S80sigmastar new file mode 100755 index 0000000..562c08c --- /dev/null +++ b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/script/init.d/S80sigmastar @@ -0,0 +1,72 @@ +#!/bin/sh +DAEMON="majestic" +PIDFILE="/var/run/$DAEMON.pid" +DAEMON_ARGS="-s" + +[ -r "/etc/default/$DAEMON" ] && . "/etc/default/$DAEMON" + +load_majestic() { + printf 'Starting %s: ' "$DAEMON" + [ -f /usr/bin/$DAEMON ] || echo -en "DISABLED, " + [ -f /etc/coredump.conf ] && . /etc/coredump.conf + if [ "$coredump_enabled" ]; then + [ "$(yaml-cli -i /etc/majestic.yaml -g .watchdog.timeout)" -lt "30" ] && yaml-cli -i /etc/majestic.yaml -s .watchdog.timeout 30 + ulimit -c unlimited && echo "|/usr/sbin/sendcoredump.sh" >/proc/sys/kernel/core_pattern + fi + start-stop-daemon -b -m -S -q -p "$PIDFILE" -x "/usr/bin/$DAEMON" \ + -- $DAEMON_ARGS + status=$? + if [ "$status" -eq 0 ]; then + echo "OK" + else + echo "FAIL" + fi + return "$status" +} + +# The daemon does not create a pidfile, and use "-m" to instruct start-stop-daemon to create one. +start() { + logger -s -p daemon.info -t sigmastar "Check MAC for Sigmastar devices" + if [ "$(fw_printenv -n ethaddr)" = "00:00:23:34:45:66" ]; then + logger -s -p daemon.info -t sigmastar "The eth0 interface has a lousy MAC, let's try to change it.." + else + logger -s -p daemon.info -t sigmastar "The eth0 interface has a correct MAC - $(fw_printenv -n ethaddr)" + fi + logger -s -p daemon.info -t sigmastar "Loading of kernel modules and initialization of the video system has started" + export TZ=$(cat /etc/TZ) + load_sigmastar -i + load_majestic +} + +stop() { + printf 'Stopping %s: ' "$DAEMON" + [ -f /usr/bin/$DAEMON ] || echo -en "DISABLED, " + start-stop-daemon -K -q -p "$PIDFILE" + status=$? + if [ "$status" -eq 0 ]; then + rm -f "$PIDFILE" + echo "OK" + else + echo "FAIL" + fi + return "$status" +} + +restart() { + stop + sleep 1 + reload +} + +reload() { + load_majestic +} + +case "$1" in + start|stop|restart|reload) + "$1" + ;; + *) + echo "Usage: $0 {start|stop|restart|reload}" + exit 1 +esac diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/imx415/imx415_iqfile.bin b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/imx415/imx415_iqfile.bin new file mode 100644 index 0000000..b562969 Binary files /dev/null and b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/imx415/imx415_iqfile.bin differ diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/imx415/sensor_imx415_mipi.ko b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/imx415/sensor_imx415_mipi.ko new file mode 100644 index 0000000..cf3f1d6 Binary files /dev/null and b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/imx415/sensor_imx415_mipi.ko differ diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/venc_fw/chagall.bin b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/venc_fw/chagall.bin new file mode 100644 index 0000000..f28a4cd Binary files /dev/null and b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/files/sensor/venc_fw/chagall.bin differ diff --git a/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/sigmastar-osdrv-infinity6e.mk b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/sigmastar-osdrv-infinity6e.mk new file mode 100644 index 0000000..d76110a --- /dev/null +++ b/projects/ssc338q_sdcard/general/package/sigmastar-osdrv-infinity6e/sigmastar-osdrv-infinity6e.mk @@ -0,0 +1,40 @@ +################################################################################ +# +# sigmastar-osdrv-infinity6e +# +################################################################################ + +SIGMASTAR_OSDRV_INFINITY6E_VERSION = +SIGMASTAR_OSDRV_INFINITY6E_SITE = +SIGMASTAR_OSDRV_INFINITY6E_LICENSE = MIT +SIGMASTAR_OSDRV_INFINITY6E_LICENSE_FILES = LICENSE + +SIGMASTAR_OSDRV_INFINITY6E_PATH = $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-infinity6e/files +SIGMASTAR_OSDRV_INFINITY6E_SENSOR = $(call qstrip,$(BR2_PACKAGE_SIGMASTAR_OSDRV_SENSOR)) + +define SIGMASTAR_OSDRV_INFINITY6E_INSTALL_TARGET_CMDS + $(INSTALL) -m 755 -d $(TARGET_DIR)/usr/bin + $(INSTALL) -m 755 -t $(TARGET_DIR)/usr/bin $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/script/bin/* + + $(INSTALL) -m 755 -d $(TARGET_DIR)/etc/init.d + $(INSTALL) -m 755 -t $(TARGET_DIR)/etc/init.d $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/script/init.d/* + + $(INSTALL) -m 755 -d $(TARGET_DIR)/usr/lib + $(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/lib/*.so + + $(INSTALL) -m 755 -d $(TARGET_DIR)/lib/modules/4.9.84/sigmastar + $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/4.9.84/sigmastar $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/kmod/*.ko + $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/4.9.84/sigmastar $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/sensor/$(SIGMASTAR_OSDRV_INFINITY6E_SENSOR)/*.ko + + $(INSTALL) -m 755 -d $(TARGET_DIR)/etc/sensors/iqfile + $(INSTALL) -m 644 -t $(TARGET_DIR)/etc/sensors/iqfile $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/sensor/$(SIGMASTAR_OSDRV_INFINITY6E_SENSOR)/$(SIGMASTAR_OSDRV_INFINITY6E_SENSOR)_iqfile.bin + ln -sf $(SIGMASTAR_OSDRV_INFINITY6E_SENSOR)_iqfile.bin $(TARGET_DIR)/etc/sensors/iqfile/iqfile0.bin + + $(INSTALL) -m 755 -d $(TARGET_DIR)/etc/sensors/venc_fw + $(INSTALL) -m 644 -t $(TARGET_DIR)/etc/sensors/venc_fw $(SIGMASTAR_OSDRV_INFINITY6E_PATH)/sensor/venc_fw/chagall.bin + + # Set sensor for insmod + sed -i "s/sensor=/sensor=$(SIGMASTAR_OSDRV_INFINITY6E_SENSOR)/g" $(TARGET_DIR)/usr/bin/load_sigmastar +endef + +$(eval $(generic-package))